Abstract:
An improved bandgap voltage reference circuit for providing a stable reference output voltage, useful in circuits associated with power supply voltage operations as low as approximately 1.3 Volts. The ΔV BE  generator is comprised of a pair of bipolar transistors operating at different current densities. Resistors in series with the transistors, in conjunction with an operational amplifier and current sources, produce a larger Voltage drop proportional to the ΔV BE  of the transistors. Output from the operational amplifier is connected to the base of a third bipolar transistor. The third bipolar transistor is provided as the bandgap voltage output device.

Description:
TECHNICAL FIELD OF THE INVENTION 
     The present invention relates in general to solid state voltage reference elements and, in particular, to bandgap voltage reference elements, which can operate from a low supply voltage. 
     BACKGROUND OF THE INVENTION 
     Without limiting the scope of the invention, its background is described in connection with the design of bias circuits for integrated circuits using CMOS technology. It should be appreciated by one skilled in the art that the principles of the present invention may be implemented in a wide variety of applications. 
     A bandgap reference circuit  10  known in the prior art is shown in FIG.  1 A. Bandgap reference circuit  10  generally comprises bipolar transistors  12  (Q 1 ) and  14  (Q 2 ), resistors  16  (R 2 ),  18  (R 1 ), and  20  (R 1 ), operational amplifier  22 , and an offset voltage source  24 . (R 1  represents the resistance of either resistor  18  or resistor  20 .) Under ideal situations, the voltage provided by the offset voltage source  24  is zero volts. In addition, the base terminal and the collector terminal of bipolar transistors  12  (Q 1 ) and  14  (Q 2 ) are shown connected to a power supply voltage terminal  26  (V SS ), which is typically zero volts. 
     The equation describing the bandgap output voltage V BG  of the circuit  10  in FIG. 1A is shown below: 
     
       
         V BG =V BE +(R 1 /R 2 )·V BE ,  (1) 
       
     
     where V BE  is the base-to-emitter voltage across bipolar transistor  12  (Q 1 ), and ΔV BE  is the difference of the base-to-emitter voltages between bipolar transistor  12  (Q 1 ) and bipolar transistor  14  (Q 2 ), which are operated at different current densities. V BE  has a negative temperature coefficient, while ΔV BE  has a positive temperature coefficient. The ΔV BE  voltage is imposed across resistor  16  (R 2 ). An image of the current flowing through resistor  16  (R 2 ), which is ΔV BE /R 2 , is forced to flow through resistor  18  (R 1 ). This gives rise to the term (R 1 /R 2 )·ΔV BE . 
     By properly selecting the value of (R 1 /R 2 ), the magnitude of the positive temperature coefficient term can be scaled and then added to the negative temperature coefficient term to substantially cancel the temperature effects. This zero, or extremely low, temperature coefficient output voltage is known as the bandgap output voltage. 
     A bandgap reference circuit can therefore provide a stable output voltage with respect to temperature. Furthermore, a bandgap reference circuit, such as the one shown in FIG. 1A, can also be designed such that when the supply voltage exceeds a minimum voltage level for proper biasing, the bandgap voltage reference will have a very good power supply rejection ratio. These characteristics makes the bandgap reference circuit a desirable candidate for use as a voltage reference for integrated circuits such as analog-to-digital converters, digital-to-analog converters, and bias current generators. In general, a bandgap voltage reference may be used in analog circuits or mixed-signal circuits to generate a stable, temperature-independent voltage reference. 
     It has been described in the prior art that it is very desirable to generate as large as possible of a ΔV BE  term, which is the voltage drop across resistor R 2 , in order to make the term (R 1 /R 2 ) as small as possible. The (R 1 /R 2 ) term increases any non-ideal conditions associated with the generation of ΔV BE , as well as any noise voltage associated with R 2 . 
     In previous attempts to increase the ΔV BE  term, a stack of two V BE  diode arrays has been used. FIG. 1B shows a circuit in the prior art utilizing this approach. The circuit in FIG. 1B has a diode stack containing two diodes. The voltage difference between the two stacked diodes yields a larger ΔV BE  term. This will yield a ΔV BE  term that is twice as large as the ΔV BE  term generated in the circuit  10  shown in FIG.  1 A. 
     However, the addition of stacked diode arrays increases the minimum supply voltage required for proper operation, as well as increasing the overall physical size of the bandgap voltage reference circuit. For a sub-micron CMOS process, the number of diodes in a stack is limited to a stack of two diodes due to the maximum allowed supply voltage, which is typically 3.6 volts. Therefore, the usefulness of stacked diode arrays to minimize noise associated with the (R 1 /R 2 ) term is limited. 
     In a sub-micron CMOS process, using a bandgap voltage reference circuit as the voltage reference of a high resolution (i.e., greater than 12 bit resolution) analog-to-digital converter or digital-to-analog converter, the noise present at the output of the prior art bandgap voltage circuit is very large and must be filtered out. This filtering is typically accomplished with a large value capacitor, which is external to the integrated circuit. Electrical connection to this external capacitor is achieved with bond wires and package leads. The problem of electromagnetic coupling to the bond wires and package leads limit the usefulness of external capacitors as filter elements. Thus, it is desirable to have a bandgap voltage reference circuit with low noise so that an external capacitor is not required. 
     SUMMARY OF THE INVENTION 
     From the foregoing, it can be appreciated that a need exists for a voltage reference circuit that overcomes the problems in the prior art. It is desirable that such a voltage reference circuit has an output voltage that is not subject to substantial variations due to temperature changes. It is further desirable that such a voltage reference circuit has a lower output noise voltage than the prior art. It is believed that the features of the present invention described herein solve and address the foregoing problems and limitations. 
     In accordance with the present invention, a bandgap voltage reference circuit is provided that is associated with low power supply voltage operation. The value of the power supply voltage can be as low as approximately 1.3 volts, which makes the inventive bandgap voltage reference topology suitable for sub-micron CMOS processes wherein supply voltages may typically range from approximately 1.8 volts to approximately 3.6 volts. 
     An improved bandgap voltage reference circuit is described herein for providing a stable reference output voltage. In accordance with a preferred embodiment of the present invention, the improved bandgap voltage reference circuit comprises a pair of bipolar transistors connected in common collector configuration and operating at different emitter current densities. The circuit further comprises resistors connected in series with each of the bipolar transistor emitters for establishing a voltage drop. The circuit further comprises a pair of CMOS transistors connected in common source configuration and functioning as current sources, wherein the source terminals are connected to a positive supply voltage, and the drain terminals are connected with the resistors. The circuit further comprises an operational amplifier wherein the output terminal is connected to the gates of the CMOS transistors. 
     The circuit also includes a CMOS transistor operating as a positive temperature coefficient current source, wherein the gate is connected to the output of the operational amplifier, and the source is connected to a positive voltage supply. Another CMOS transistor is included, which operates as a current source, wherein the gate is connected to the output of the operational amplifier, and the source is connected to the positive voltage supply. The circuit further comprises another bipolar transistor for serving as the output device of the bandgap voltage generator, wherein the base is connected to the drain of the CMOS transistor operating as a current source. 
     The circuit of the present invention may also include a base compensation circuit for canceling any errors introduced into the circuit by the base current of the output bipolar transistor. The circuit of the present invention may further include a feedback voltage adjustment circuit comprising resistive elements and switch elements controlled by digital logic. 
     A preferred method of providing a bandgap voltage reference is also disclosed herein. The inventive method comprises the steps of operating a pair of bipolar transistors at different emitter current densities, providing one or more resistive elements in series with the pair of bipolar transistors for establishing a voltage drop, operating a pair of CMOS transistors as current sources, configuring an operational amplifier for providing a positive temperature coefficient current source, providing a control voltage for the positive temperature coefficient current source, providing a positive temperature coefficient voltage source, and providing a third bipolar transistor as a bandgap voltage output device. The method may further comprise the step of offsetting error introduced by the base current of the bandgap voltage output device. The method may further comprise the step of adjusting the value of the resistance of the resistive elements. 
     For a more complete understanding of the present invention, including its features and advantages, reference is now made to the following detailed description, taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings: 
     FIG. 1A depicts a schematic diagram of a prior art bandgap voltage reference circuit; 
     FIG. 1B depicts a schematic diagram of a prior art bandgap voltage reference circuit using a stacked diode array; 
     FIG. 2 depicts a schematic diagram of a bandgap voltage reference circuit in accordance with an embodiment of the present invention; 
     FIG. 3 depicts a block diagram of a prior art bandgap voltage reference circuit in conjunction with an external filter capacitor used as a reference for an analog-to-digital converter; and 
     FIG. 4 depicts a schematic diagram of a low output impedance bandgap voltage reference circuit in accordance with a preferred embodiment of the present invention. 
     Corresponding numerals and symbols in the different figures refer to corresponding parts unless otherwise indicated. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Reference is now made to FIG. 2, which depicts a schematic diagram of an exemplary bandgap voltage reference circuit  100  in accordance with the present invention. Circuit  100  comprises CMOS (complementary metal-oxide semiconductor) transistor  102  (M 1 ), CMOS transistor  104  (M 2 ), and CMOS transistor  106  (M 3 ), resistor  108  (R 1 ), resistor  110  (R 2 ) and resistor  112  (R 3 ), bipolar transistor  114  (Q 1 ), bipolar transistor  116  (Q 2 ), and bipolar transistor  118  (Q 3 ), and a feedback operational-amplifier  120 . Circuit  100  includes a terminal to a supply voltage  122  (V DD ), and a reference to ground  124 . 
     The circuit  100  shown in FIG. 2 is suitable for a standard all CMOS process. In a standard CMOS only process, PNP bipolar transistors may be formed by p +  diffusion area inside an n-well area. The p +  diffusion area inside of an n-well area creates the emitter; the n-well creates the base; and the substrate creates the collector. 
     Circuit  100  can also be manufactured in a BiCMOS process. In addition, if all PMOS (p-channel metal-oxide-semiconductor) transistors are replaced with PNP bipolar transistors whose collectors are not electrically connected to the substrate, then circuit  100  could also be manufactured in a pure PNP bipolar process. Thus, while CMOS transistor  102  (M 1 ), CMOS transistor  104  (M 2 ), and CMOS transistor  106  (M 3 ) are shown in FIG. 2 as PMOS transistors, and bipolar transistor  114  (Q 1 ), bipolar transistor  116  (Q 2 ) and bipolar transistor  118  (Q 3 ) are depicted as PNP bipolar transistors, it should be appreciated by one skilled in the art that the principles of the present invention may be implemented using other types of semiconductor processes. 
     In addition, the circuit  100  can achieve a large voltage drop across resistor  110  (R 2 ) without the need of stacked diode arrays. The circuit of the present invention, however, may be implemented with or without stacked diode arrays. 
     The operational-amplifier  120  has sufficient gain such that the voltage at node A designated as  126  (V A ) and the voltage at node B designated as  128  (V B ) are assumed to be equal. Transistor  102  (M 1 ) and transistor  104  (M 2 ) are also assumed to have equal current flowing through them. (This assumption is used to simply the following equations. In practice, the currents flowing through transistor  102  (M 1 ) and transistor  104  (M 2 ) need only be linearly related to each other.) 
     Therefore, we have: 
     
       
         V A =V B   (2) 
       
     
     Referring to FIG. 2, the voltage at node A  126  (V A  and the voltage at node B  128  (V B ) are given as follows: 
     
       
         V A =V BE2 +V R2   (3) 
       
     
     and 
     
       
         V B =V BE1 +V R3   (4) 
       
     
     where V BE2  is the base-emitter voltage across transistor  116  (Q 2 ), V BE1  is the base-emitter voltage across transistor  114  (Q 1 ), V R2  is the voltage across resistor  110  (R 2 ), and VR 3  is the voltage across resistor  112  (R 3 ). 
     Combining Eqs. 2, 3, and 4 yields: 
     
       
         V A =V BE2 +V R2 =V BE1 +V R3 .  (5) 
       
     
     FIG. 2 illustrates transistor  116  (Q 2 ) as eight times larger than transistor  114  (Q 1 ). Therefore, V BE1 ≠V BE2 . 
     Rearranging Eq. 5 yields: 
     
       
         V R2 =V BE1 +V R3 −V BE2 .  (6) 
       
     
     Since transistor  102  (M 1 ) and transistor  104  (M 2 ) are also assumed to have equal current flowing through them, it follows that: 
     
       
         I R2 =I M2 =I M1 =I R2 .  (7) 
       
     
     The current I R2  flowing through resistor  110  (R 2 ) can be shown as: 
     
       
         I R2 =V R2 /R 2 .  (8) 
       
     
     The voltage V R3  across resistor  112  (R 3 ) can be shown as: 
     
       
         V R3 =I R2 ·R 3 =(VR 2 /R 2 )·R 3 .  (9) 
       
     
     Therefore, combining Eqs. 6 and 9 results in the following equation: 
     
       
         V R2 =V BE1 −V BE2 +(V R2 ·(R 3 /R 2 )).  (10) 
       
     
     Solving Eq. 10 for V R2  results in the following equation: 
     
       
         V R2 =(V BE1 −V BE2 )/(1−(R 3 /R 2 ))=ΔV BE /(1−(R 3 /R 2 )).  (11) 
       
     
     From Eq. 11, it is shown that the voltage across resistor  110  (R 2 ) is a ΔV BE  term multiplied by a factor of 1/(1−(R 3 /R 2 )). The term 1/(1−(R 3 / R2 )) can be made very large by proper selection of resistors  112  (R 3 ) and  110  (R 2 ). 
     As shown in FIG. 2, the bandgap voltage  130  (V BG ) is given by the following: 
     
       
         V BG =V R1 +V BE3 .  (12) 
       
     
     Again, assuming that I M1 =I M3 , it follows that: 
     
       
         V R1 =(V R2 /R 2 )·R 1 ={(ΔV BE /(1−(R 3 /R 2 )))·(R 1 /R 2 )},  (13) 
       
     
     and 
     
       
         V BG =V BE3 +{(ΔV BE /(1−(R 3 R 2 )))·(R 1 /R 2 )}.  (14) 
       
     
     For simplicity, the foregoing assumes that transistor  102  (M 1 ), transistor  104  (M 2 ), and transistor  106  (M 3 ) all have the same value of current flowing through them; however, the currents flowing through transistor  102  (M 1 ), transistor  104  (M 2 ), and transistor  106  (M 3 ) do not have to be of equal value. Rather, these currents only need to be linearly related to each other. When the currents of transistor  102  (M 1 ), transistor  104  (M 2 ), and transistor  106  (M 3 ) are not equal to each other, but instead are linearly related to each other, the preceding analysis must be modified by the current ratios of transistor  102  (M 1 ) to transistor  104  (M 2 ), as well as the current ratios of transistor  102  (M 1 ) to transistor  106  (M 3 ). One skilled in the art should be able to modify Eq. 14 to include such current ratios. 
     Now referring to FIGS. 1A &amp; 1B, the equation for the output voltage for the two circuits, which is noted as V BG , is given in the next two equations: 
     
       
         V BG =V BE3 +{ΔV BE ·(R 1 /R 2 )}  (15) 
       
     
     
       
         V BG =V BE3 +{2ΔV BE ·(R 1 / R2 )},  (16) 
       
     
     Where V BG  in Eq. 15 is the bandgap voltage in the circuit in FIG. 1A, and V BG  in Eq. 16 is the bandgap voltage in the circuit in FIG.  1 B. 
     The output voltage V BG , of FIG. 1A, FIG. 1B, and FIG. 2 are assumed to be all the same value. In addition, the negative temperature coefficient term, V BE3 , is also assumed to be the same value. Furthermore, the positive temperature coefficient term, ΔV BE , is also assumed to be all the same value. The difference in Eqs. 14, 15, and 16 is in the factors that multiply the positive temperature coefficient term. 
     Eq. 15 shows a term R 1 /R 2 , whereas Eq. 16 shows a term of 2·(R 1 /R 2 ). The factor  2  in Eq. 16 results from the fact that the voltage drop across R 2  in FIG. 1B is twice as large as the voltage drop across R 2  in FIG.  1 A. Therefore, the ratio R 1 /R 2  of Eq. 16 is half the ratio of Eq. 15. The (R 1 /R 2 ) term increases any non-ideal conditions associated with the generation of the ΔV BE , as well as any noise voltage associated with R 2 . Thus, the noise source associated with R 2  in FIG.  1 B and any non-idealities associated with generating the voltage drop across R 2  has half the effect as the R 2  in FIG.  1 A. 
     Eq. 14 shows a term of {(R 1 /R 2 )/(1−(R 3 /R 2 ))}. The voltage drop across R 2  in FIG. 2 can be made arbitrarily large by simply adjusting the value of R 3 . Thus, the noise source associated with R 2  in FIG.  2  and any non-idealities associated with generating the voltage drop across R 2  in FIG. 2 are greatly reduced when compared to the prior art. 
     The output noise spectral density of a bandgap voltage reference is normally dominated by the thermal noise generated by the resistors in the circuit. Referring to FIG. 2, the output noise spectral density of the invention is thus given by the following equation: 
     
       
         4kt{R 3 ·(R 1 /R 2 ) 2 )+(R 2 ·(R 1 /R 3 ) 2 )+R 1 }=V Noise   2 /Hz,  (17) 
       
     
     where k is Boltzmann&#39;s constant, and t is the temperature in degrees Kelvin. Comparatively, the output noise spectral density of the prior art circuit in FIG. 1A is given by the following equation: 
     
       
         4kt{(R 1   2 /R 2 )+R 1 }=V Noise   2 /Hz.  (18) 
       
     
     The prior art circuit  10  shown in FIG. 1A has two noise sources that must be considered, while the circuit  100  of the present invention shown in FIG. 2 has 3 noise sources that need to be considered; however, the term (R 1   2 /R 2 ) in Eq. 18 is very large in the prior art circuit  10 , resulting in much greater output noise than the circuit  100  of the present invention shown in FIG.  2 . 
     As an example, the following are calculations of the different resistor ratios required, as well as the output noise due to the resistors, for a temperature-stabilized output of the prior art circuit  10  of FIG.  1 A and the circuit  100  of the present invention shown in FIG.  2 . 
     For a bandgap voltage reference circuit, the temperature stabilized output dc level, where d/dt Vout=0, comes about at an output voltage level on the order of +1.25 Volts. Assume that the V BE  term has a voltage equal to 0.6 Volts, and the ΔV BE  term has a voltage of 0.65 Volts. For the prior art circuit  10  shown in FIG. 1A, assume that the transistors Q 1  and Q 2  have the same magnitude of emitter current flowing through them and that Q 2  has eight times the emitter area of Q 1 . For the circuit  100  in FIG. 2 assume that the transistors Q 1  and Q 3  have the same magnitude of emitter current flowing through them. Furthermore, assume that Q 2  has eight times the emitter area of Q 3 . 
     For the prior art circuit  10  of FIG.  1 A: 
     
       
         0.65 Volts=R 1 /R 2 ·V t ·ln(8),  (19) 
       
     
     where V t , is defined as the thermal voltage, which is equal to 26 mVolts at room temperature. Therefore, 
     
       
         R 1 /R 2 =6  (20) 
       
     
     The Output Noise Spectral Density of the Prior Art is given in Eq. 18, and referring to Eq. 19 and substituting for R 2  yields as follows: 
     
       
         4kt{6·(R 1   2 /R 1 )+R 1 }=V Noise   2 /Hz  (21) 
       
     
     and 
     
       
         48kt·R 1 =V Noise   2 /Hz.  (22) 
       
     
     For the circuit  100  of FIG.  2 : 
     
       
         0.65 Volts {(R 1 /R 2 )·(1/(1−(R 3 /R 2 ))·V t ·ln(8)}(23) 
       
     
     
       
         Set R 1 /R 2 =1  (24) 
       
     
     
       
         Therefore, R 3 /R 2 =0.917.  (25) 
       
     
     Using Eqs. 24 and 25 to substitute for R 2  and R 3  in Eq. 17 yields: 
     
       
         4kt{(0.917·R 1 )+(R 1 ·(1/0.917 2 ))+R 1 }=V Noise   2 /Hz.  (26) 
       
     
     
       
         4kt·R 1 {(0.917)+(1/0.917 2 )+1}=V Noise   2 /Hz.  (27) 
       
     
     
       
         4kt·R 1 {(0.917)+(1/0.917 2 )+1}=V Noise   2 /Hz.  (28) 
       
     
     
       
         12.43kt·R 1 =V Noise   2 /Hz.  (30) 
       
     
     Comparing Eq. 21 to Eq. 30 shows that for the same value of R 1 , the circuit of the present invention  100  is approximately 3.86 times quieter than the prior art circuit  10  shown in FIG.  1 A. Likewise, it can be shown that the circuit  100  of the present invention is approximately 1.93 times quieter than the prior art circuit shown in FIG.  1 B. 
     A circuit  400  in accordance with the preferred topology of the present invention is shown in FIG.  4 . Circuit  400  comprises CMOS transistor  402  (M 1 ), CMOS transistor  404  (M 2 ), CMOS transistor  406  (M 3 ), CMOS transistor  436  (M 4 ), CMOS transistor  438  (M 5 ), CMOS transistor  432  (M 6 ) and CMOS transistor  434  (M 7 ), resistor  408  (R 1 ) and resistor  410  (R 2 ), resistor  412  (R 3 ), bipolar transistor  414  (Q 1 ), bipolar transistor  416  (Q 2 ), bipolar transistor  418  (Q 3 ), and bipolar transistor  430  (Q 4 ), and a feedback operational-amplifier  420 . Circuit  400  includes a terminal to a supply voltage  422  (V DD ), and a reference to ground  424 . 
     Circuit  400  has the following characteristics: 
     1. The effective value of resistor  412  (R 3 ) can be adjusted by digital control logic. This allows for the adjustment of the feedback voltage measured across resistor  412  (R 3 ). This feature allows for correction of resistor ratio mismatches as well as transistor current source mismatches and offset voltage of operational amplifier  420 . 
     2. The voltage drop across resistor  408  (R 1 ) due to the base current of transistor  414  (Q 1 ) is eliminated. 
     Referring again to FIG. 4, resistor  412  (R 3 ) is made adjustable, or more precisely, if the voltage difference between the input terminal  428  (V B ) of operational amplifier  420  and the emitter terminal of transistor  414  (Q 1 ) is made adjustable, then the resistor ratio term that multiplies the V BE  term can be used to adjust for any errors in the resistor ratios due to mismatches arising out of the manufacturing process. In Eq. 14, R 3  represents the resistor that is connected between the input terminal  428  (V B ) of the operational amplifier  420  and the emitter terminal of transistor  414  (Q 1 ). This resistor value depends upon which of the switch(es) is closed. Furthermore, a salient feature of having the above mentioned adjustment circuit is that not only are mismatches in resistor ratios accounted for but also any matching errors in the currents flowing through transistor  402  (M 1 ) and transistor  404  (M 2 ) can also be corrected. It is noted that the same mismatch corrections can be made if resistor  410  (R 2 ) is made adjustable instead of resistor  412  (R 3 ). 
     Another significant feature of circuit  400  is that the voltage drop across resistor  408  (R 1 ) due to the base current of transistor  418  (Q 3 ) is eliminated. The base current of transistor  418  (Q 3 ) in circuit  400  has a very large temperature coefficient and is very process dependent. If the base current of transistor  418  (Q 3 ) flows through resistor  408  (R 1 ), then the DC output voltage will have a process dependent voltage error that is not very well controlled. The preferred embodiment of the present invention has circuitry that subtracts the base current of transistor  418  (Q 3 ) before this current flows through resistor  408  (R 1 ). 
     The base current cancellation is accomplished with transistors  436  (M 4 ),  432  (M 6 ),  434  (M 7 ), and  430  (Q 4 ). The current flowing through transistor  436  (M 4 ) which is the emitter current flowing through transistor  430  (Q 4 ), is related to the emitter current flowing through the output transistor  418  (Q 3 ). The base current of transistor  430  (Q 4 ) flows through transistor  432  (M 6 ). The gate of transistor  434  (M 7 ) is connected to the gate of transistor  432  (M 6 ). The ratio of the current flowing  434  (M 7 ) with respect to transistor  432  (M 6 ) should be the same ratio as the current flowing through transistor  436  (M 4 ) with respect to transistor  406  (M 3 ). 
     While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments as well as other embodiments of the invention will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.