Abstract:
This invention is a method allowing for interfacing high speed hard disk drives (ATA-HDD) in high throughput PIO modes to currently available digital media processors (DMP). The prescribed interface programs signals available in the DMP external memory interface (EMIF) functions to match the requirements of ATA-HDD PIO functions. Selected signal redefinition and minimal glue logic is employed to form a seamless link between the EMIF I/O of the digital media processor DMP and the ATA-HDD hard drive.

Description:
TECHNICAL FIELD OF THE INVENTION 
       [0001]    The technical field of this invention is personal media players. 
       BACKGROUND OF THE INVENTION 
       [0002]    A variety of Texas Instruments digital media processors have been developed for digital cameras and the digital media players. These processors are designed for products requiring high data transfer throughput including portable media players (PMP). 
         [0003]    One of the major functions of PMP is to play movies requiring mass storage in hard drives of extremely small physical size. The movie playback frame rate and resolution both depend on a high level of data transfer throughput between the PMP and the hard drive it accesses. 
         [0004]    Digital movie data in portable media players is generally compressed in an MPEG4 format and utilizes mass storage in the range of many gigabytes. The movie playback frame rate and resolution depend on how effectively the processor can respond to data coming from the hard drive. Playback quality is a direct function of the level of throughput that the PMP player and its storage medium can offer. 
         [0005]    Integrated Drive Electronics (IDE) was created as a way to standardize the use of hard drives in computers with the hard drive and the controller combined. The controller is a small circuit board with semiconductor chips that guide how the hard drive stores and accesses data. Most controllers also include some memory that acts as a buffer to enhance hard drive performance. 
         [0006]    Before IDE, controllers and hard drives were separate and often proprietary. Thus, a controller from one manufacturer might not operate properly with a hard drive from another manufacturer. The distance between the controller and the hard drive could result in poor signal quality and affect performance. IBM introduced the AT computer in 1984 with a several key innovations. 
         [0007]    1. Additional slots in the computer for adding cards used a new version of the Industry Standard Architecture (ISA) bus. The new bus was capable of transmitting information 16 bits at a time, compared to 8 bits on the original ISA bus. 
         [0008]    2. A hard drive designed for the AT computer was introduced using a new combined drive/controller. A ribbon cable from the drive/controller combination ran to an ISA card to connect to the computer, giving birth to the AT Attachment (ATA) interface. 
         [0009]    3. In 1986 ATA standard drives were introduced. This drive/controller combination was based on the ATA standard developed by IBM. Vendors then began offering IDE drives. IDE became the term that covered the entire range of integrated drive/controller devices. Since almost all IDE drives are ATA-based, the two terms are used interchangeably. 
         [0010]    Currently, an IDE hard disk may be configured to work in one of the five PC I/O modes (PIO modes) with a range of corresponding data transfer rates. Table 1 summarizes the mode designations of the five currently identified PIO modes and their transfer rates. 
         [0000]                                                      TABLE 1                           Data Rate   Access Rate           PIO Mode   (Mbytes/sec)   (nsec/access)                                        PIO-0   3.3   606           PIO-1   5.2   385           PIO-2   8.3   240           PIO-3   11.1   180           PIO-4   16.6   120                        
The host digital media processor negotiates the desired data transfer rate with the IDE hard disk during initialization depending on the capability of the hard disk. Older hard disk drives may accommodate only one of the lower PIO modes, but many newer hard disks can support all the transfer rates of Table 1. Likewise slower processors cannot access hard disks at the higher PIO modes.
 
         [0011]      FIG. 1  illustrates a block diagram of a host digital media processor (DMP)  100  and its interface in Prior Art to an ATA/IDE high-density drive media device  101  via a CFC True IDE Mode interface  102  built into the digital media processor  100 . The ATA-IDE HDD controller  103  is shown separately to emphasize the presence of I/O registers crucial to HDD operation. Compact Flash Association specification rev. 1.4 dated 1998 defines the compact flash card (CFC), which allows for three major modes of usage: PC Card Memory Mode; PC Card I/O Mode; and CFC True IDE Mode. 
         [0012]    The CFC True IDE Mode interface  102  built in to the digital media processor chip supports CFC card data transfers where each read or write access to the hard disk takes typically 255 nsec per word (slower than the PIO-2 mode). Thus the use of the CFC True IDE interface requires that the digital media processor must set the hard disk to work at PIO-1 mode rate where maximum throughput is 5.2 Mbytes per second. In CFC True IDE Mode, CFC True IDE interface  102  uses signals  104  derived from the DMP processor to drive the ATA/IDE HDD high density drive  101 . Table 2 lists the signals for read cycle timing. 
         [0000]    
       
         
               
               
               
               
               
             
               
               
               
               
               
             
           
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                   
                   
                 Min 
                 Max 
               
               
                   
                 Item 
                 Symbol 
                 nsec 
                 nsec 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 Data delay after IORD_ (212) 
                 tDdRD —   
                   
                 100 
               
               
                   
                 Data hold following 
                 tDhRD 
                 0 
               
               
                   
                 IORD_ (211) 
               
               
                   
                 IORD_ width (208) 
                 twRD 
                 165 
               
               
                   
                 Address setup before 
                 tAsuRD 
                 70 
               
               
                   
                 IORD_ (205) 
               
               
                   
                 Address hold after IORD_ (206) 
                 tAhRD 
                 20 
               
               
                   
                 CE_ setup before IORD_ (207) 
                 tCEsuRD 
                 5 
               
               
                   
                 CE_ hold following 
                 tCEhRD 
                 20 
               
               
                   
                 IORD_ (209) 
               
               
                   
                   
               
             
          
         
       
     
         [0013]      FIG. 2  illustrates descriptive waveforms of the read signals. These read signals include: 
         [0014]    ADDR_valid ( 201 ) defines the time window for which addressing is valid; 
         [0015]    CE_ 202  is a chip enable signal for read operations and is active low; 
         [0016]    IORD_ 203  determines duration of READ cycle and is active low; 
         [0017]    Data[15:0]  204  defines data read interval; 
         [0018]    tAsuRD  205  is the address setup time prior to IORD_; 
         [0019]    tAhRD  206  is the address hold after IORD_; 
         [0020]    tCEsuRD  207  is the chip enable setup time prior to leading edge of IORD_; 
         [0021]    twRD  208  is the pulse width of IORD_; 
         [0022]    tCEhRD  209  is the chip enable hold time after trailing edge of IORD_; 
         [0023]    tDsuRD  210  is the data setup time prior to trailing edge of IORD_; 
         [0024]    tDhRD  211  is the data hold time after trailing edge of IORD_; and 
         [0025]    tDdRD  212  is the data delay time after leading edge of IORD_. 
         [0026]    Table 3 lists the signals for write cycle timing. 
         [0000]    
       
         
               
               
               
               
               
             
               
               
               
               
               
             
           
               
                   
                 TABLE 3 
               
               
                   
                   
               
               
                   
                   
                   
                 Min 
                 Max 
               
               
                   
                 Item 
                 Symbol 
                 nsec 
                 nsec 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 Data delay after IOWR_ (312) 
                 tDdWR —   
                 60 
                   
               
               
                   
                 Data hold following 
                 tDhWR 
                 30 
               
               
                   
                 IOWR_ (311) 
               
               
                   
                 IOWR_ width (308) 
                 twWR 
                 165 
               
               
                   
                 Address setup before 
                 tAsuWR 
                 70 
               
               
                   
                 IOWR_ (305) 
               
               
                   
                 Address hold after IOWR_ (306) 
                 tAhWR 
                 20 
               
               
                   
                 CE_ setup before IOWR_ (307) 
                 tCEsuWR 
                 5 
               
               
                   
                 CE_ hold following 
                 tCEhWR 
                 20 
               
               
                   
                 IOWR_ (309) 
               
               
                   
                   
               
             
          
         
       
     
         [0027]      FIG. 3  illustrates descriptive waveforms of the write signals. These write signals include: 
         [0028]    ADDR_valid  301  defines the time window for which addressing is valid; 
         [0029]    CE_ 302  is the chip enable signal for write operations and is active low; 
         [0030]    IOWR_ 303  determines the duration of a WRITE cycle and is active low; 
         [0031]    Data[15:0]  304  defines the data write interval; 
         [0032]    tAsuWR  305  is the address setup time prior to IOWR_; 
         [0033]    tAhWR  306  is the address hold after IOWR_; 
         [0034]    tCEsuWR  307  is the chip enable setup time prior to leading edge of IOWR_; 
         [0035]    twWR  308  is the pulse width of IOWR_; 
         [0036]    tCEhWR  309  is the chip enable hold time after trailing edge of IOWR_; 
         [0037]    tDsuWR  310  is the data setup time prior to trailing edge of IOWR_; 
         [0038]    tDsuWR  311  is the data hold time after trailing edge of IOWR_; and 
         [0039]    tDdWR  312  is the data delay time after leading edge of IOWR_. 
         [0040]      FIG. 4  illustrates the ATA/IDE HDD controller  103  and associated registers  105  for extended memory interface (EMIF) addressing and control signals to the HDD I/O registers  105  of the prior art. Two types of data are involved in the HDD operation: (a) control data to direct operation from the HDD registers  105 ; and (b) information data to be stored. In initial operation of any read/write cycle, control data is transferred from the host to the HDD controller addressable registers  401  through  410 . Then the ATA/IDE HDD controller  103  performs all of the operations necessary to properly write information data to, or read information data from the media. Information data  430  read from media device  101  is stored in device buffer  407  pending transfer to cache  106 . In the write cycle, information data  430  is transferred from cache  106  to device buffer  407  to be written to media  101 . ATA/IDE HDD controllers  103  using this interface are programmed by the host computer to perform commands and return status to the host at command completion. 
         [0041]    Communication to or from HDD media device  101  is through host interface  400  to I/O registers  401  through  410  that route the input or output data to or from registers addressed by the signals from the host:
       (CSO_, CS 1 _, DA[2:0], DIOR_, and DIOW_)
 
All data written to any of the registers  401  through  410  pass from the host via input  430 . Inputs  431  through  433  provide all the control signals described in conjunction with  FIGS. 2 and 3 .
       
 
         [0043]    Control block registers driven by HDD device control  421  and HDD data control  422  are used for device control and to post alternate status. These registers include: write control register  401 ; alternate status registers  402 ; and data register  407 . 
         [0044]    Command block registers are used for sending commands to the device or posting status from the device. These registers include: write command register  403 ; read status register  404 ; cylinder high register  405 ; cylinder low register  406 ; device/head register  409 ; error register  412 ; features register  413 ; sector count register  410 ; and sector number register  408 . 
       SUMMARY OF THE INVENTION 
       [0045]    This invention is methods and hardware interfacing high speed hard disk drives (ATA-HDD) in high throughput PIO modes to digital media processors (DMP). The prescribed interface programs signals available in the DMP external memory interface (EMIF) functions to match the requirements of ATA-HDD PIO functions. Selected signal redefinition and minimal glue logic forms a seamless link between the EMIF I/O of the digital media processor DMP and the ATA-HDD hard drive. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0046]    These and other aspects of this invention are illustrated in the drawings, in which: 
           [0047]      FIG. 1  illustrates the block diagram of a digital media processor (DMP) and its interface to an ATA/HDD high density hard drive via a compact flash card interface (CFC) built into the digital media processor chip (Prior Art); 
           [0048]      FIG. 2  illustrates the timing diagram for read functionality requirements of the ATA-IDE controller and the interface between the CFC flash card interface to an ATA/HDD high density hard drive (Prior Art); 
           [0049]      FIG. 3  illustrates the timing diagram for write functionality requirements of the ATA-IDE controller and the interface between the CFC flash card interface to an ATA/HDD high density hard drive (Prior Art); 
           [0050]      FIG. 4  illustrates the ATA-HDD controller and associated registers for interfacing EMIF addressing and control signals to the HDD I/O registers (Prior Art); 
           [0051]      FIG. 5  illustrates the block diagram of a digital media processor (DMP) and EMIF interface to an ATA/HDD high density hard drive via the glue logic of the invention and special EMIF signal programming; 
           [0052]      FIG. 6  illustrates the ATA/HDD hard drive signal timing as programmed according to the present invention; 
           [0053]      FIG. 7  illustrates the use of EMIF address bits A[4:0] to directly address the ATA-HDD I/O registers of  FIG. 4 ; 
           [0054]      FIG. 8  illustrates the signal connections between the DMP EMIF and the ATA/IDE hard drive via the glue logic of the invention; and 
           [0055]      FIG. 9  illustrates a programming example for EMIF timing that allows PIO4 mode operation according to the technique of the invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0056]      FIG. 5  illustrates the block diagram of a digital media processor (DMP)  500  and its interface to an ATA/IDE high-density hard drive  510  using only the DMP EMIF interface  509  and a set of simple glue logic gates  502 . The signals derived from the DMP processor EMIF are adapted and supplemented to secure a seamless interface to the ATA/IDE HDD hard disk drive  510 . Signals  501  pass through the glue logic  502  creating the required signals  503  allowing for flexible programming of the interface permitting a very high speed interface between the DMP and the ATA/IDE hard drive. EMIF address bits A[4:0]  504  translate directly to required I/O register address bits  505  including DA[2:0], chip select CS 0  and chip select CS 1  (see  FIG. 7 ). Glue logic  502  (see  FIG. 8 ) matches signals  506  to signals  507  at the interface. Data bus  508  is a direct pass through. 
         [0057]    The ATA/IDE hard drive interface matches ATA/IDE selection addresses with the requirements of the ATA-HDD HDD controller  511  and the I/O port registers illustrated in  FIG. 4 . These ATA-HDD I/O registers direct the ATA-HDD operation allowing all data and control signals to execute the completion of hard drive media storage. 
         [0058]      FIG. 6  illustrates the timing of all control and data signals between the EMIF and ATA/IDE hard drive interface. Table 4 lists numerical values for all the timing requirements of parameters described in  FIG. 6 . 
         [0000]                                                                      TABLE 4                   Mode0   Mode1   Mode2   Mode3   Mode4       PIO Timing Parameters   nsec   nsec   nsec   nsec   nsec                                t0   Cycle Time   600   383   240   180   120       t1   Address Valid to   70   50   30   30   25           DIOR_/DIOW setup time (min)       t2   DIOR_/DIOW width (min)   165   125   100   80   70       t2r   DIOR_/DIOW recovery time   —   —   —   70   25           (min)       t3   DIOW_ data setup time (min)   60   45   30   30   20       t4   DIOW_ data hold time (min)   30   20   15   10   10       t5   DIOR_ data setup time (min)   50   35   20   20   20       t6   DIOR_ data hold time (min)   5   5   5   5   5       t6z   DIOR_ data release (max)   30   30   30   30   30       tg   DIOR_/DIOW to address valid   20   15   10   10   10           hold time (min)                    
The highest defined PIO mode4 data transfer rate requires the following timing:
 
         [0059]    Access cycle time  600  is a full cycle of DIOR_/DIOW_ illustrated in  FIG. 6 , t 0  is a minimum of 12O nsec for a data transfer rate of 16.6 MBytes/sec; 
         [0060]    Address valid to write or read setup time  605  t 1  is a minimum of 25 nsec; 
         [0061]    Write or read pulse width  608  in DIOR_/DIOW_ 602  t 2  is a minimum of 70 nsec; 
         [0062]    For data write, EMIF write data  603  must be valid on data bus t 3  is a minimum of 20 nsec before DIOW negates at interval  610 ; 
         [0063]    For data write, EMIF write data  603  must be valid on data bus t 4  a minimum of 10 nsec after DIOW negates at interval  611 ; 
         [0064]    For data read, HDD output data  604  must be valid on data bus t 5  a minimum of 20 nsec before DIOR negates at interval  612 ; and 
         [0065]    For data read, HDD output data must be held valid on data bus t 6  a minimum of 10 nsec after DIOR negates at interval  613 . 
         [0066]      FIG. 7  illustrates the use of EMIF address bits A[4:0] to directly address the ATA-HDD I/O registers of  FIG. 4 . The EMIF bits A[4:0] pass to ATA/IDE hard drive with signals renamed DA[2:0], CS 0  and CS 1  with no translation required. 
         [0067]      FIG. 8  illustrates the signal connections between the DMP EMIF  800  and the ATA/IDE hard drive  810  via the glue logic of this invention. Only two OR gates  811  and  812  are required for the interface and these may be housed conveniently in a flex PC card designed to plug into present DMP processors configured to interface to current hard drives. The signals of the glue interface illustrated in  FIG. 8  include: 
         [0068]    ADDR_valid  801  defines the time window for which addressing is valid; 
         [0069]    A[2:0]  802  is the least significant 3 bits of the address bus from DMP_EMIF which drives DA[2:0] of the ATA/IDE hard drive; 
         [0070]    A[3]  803  is bit  3  of the address bus from DMP_EMIF which drives CS 0  of the ATA/IDE hard drive; 
         [0071]    A[4]  804  is bit  4  of the address bus from DMP_EMIF which drives CS 1  of the ATA/IDE hard drive; 
         [0072]    CE_  805  is the chip enable signal for write/read operations which is active low; 
         [0073]    WR_  806  is the write/read signal from DMP_EMIF; 
         [0074]    OE_  807  is the output enable signal from DMP_EMIF; 
         [0075]    D[15:0]  808  is the data transfer bus containing the data to be transferred; 
         [0076]    WAIT/IORDY  809  is the wait request from ATA/IDE to DMP EMIF; 
         [0077]    INT/INTRQ  815  is the interrupt request from ATA/IDE to DMP EMIF; 
         [0078]    DIOW_  813  determines the duration of WRITE cycle and is active low; and 
         [0079]    DIOR_  814  determines duration of READ cycle and is active low. 
         [0080]      FIG. 9  illustrates a programming example for EMIF timing that allows PIO-4 mode operation using this invention. Programming of the crucial timing signals between the input and the output signals of the glue logic of  FIG. 8  proceeds as follows. 
         [0081]    (1) Program CPU clock  900  with 12 cycles so that 12×1O nsec=12O nsec, which meets t 0 =12O nsec maximum for PIO mode4 access cycle time. 
         [0082]    (2) Program CE setup time  901  t 1  with 10 cycles. 
         [0083]    (3) Program both WR_ setup time  902  and OE_ setup time  903  with 3 cycles. This makes the address valid setup time equal to 3O nsec, which meets t 1  greater than or equal to 25 nsec timing limit for PIO mode4 timing. 
         [0084]    (4) Program both WR_ width  904  and OE_ width  905  with 7 cycles. This makes the read or write pulse width is 7×10=7O nsec, which meets t 2 =70 nsec requirement for PIO mode4 for DIOR_ and DIOW_  906 . 
         [0085]    (5) The above timing settings leave address valid hold time of 120 nsec−30 nsec−70 nsec=20 nsec. This meets the t 9 =10 nsec requirement for PIO mode4 at  911 . 
         [0086]    (6) For reads from the HDD, the HDD places read data output on the data bus t 5 =2O nsec before DIOR_ negates, and holds the data valid on the bus for t 6 =1O nsec after DIOR_ negates as illustrated at  909  and  910 . 
         [0087]    The EMIF requires only that data to be valid 8 nsec before DIOR_ negates. This requirement is less than t 5 =2O nsec of this example. The EMIF does require that data be valid immediately following DIOR_ negating. Thus EMIF read operation timing meets HDD PIO mode4 read timing requirements. 
         [0088]    (7) For writes to the HDD, the HDD PI0-4 expects data to be valid t 3 =2O nsec before DIOW_ negates and held valid for t 4 =1O nsec after DIOW_ negates as illustrated at  907  and  908 . EMIF places D[15-0] on the data bus when the address and CE are valid. Thus, the EMIF data is valid during both t 3  and t 4  for HDD to clock data in. Thus, write operation timing is satisfied. 
         [0089]    The above timing check illustrates that the programmed EMIF timing after the glue logic meets ATA-PIO mode4 timing requirements. Therefore, it supports data write and data read at PIO mode4 speed where 2 bytes are processed every 12O nsec or 16.7 MBytes/second. 
         [0090]    Compared to CFC interface to access HDD, the CFC access rate is limited by 290 nsec for each read or write operation. This happens where 290 nsec=7O nsec address setup time÷165 nsec read/write pulse width÷2O nsec address hold time plus 35 nsec for a 16-bit read/write operation. This means when using CFC interface to HDD, the system could not sustain PIO mode2 operation which requires 240 ns access rate.