Abstract:
Disclosed is a digital multifrequency signaling receiving system in which a first operation device executes an operation to multiply multifrequency signals composed of N samples as input signals by a window function including coefficients required for fast Fourier transform. An output produced at the first operation device, as a sample signal, is subjected to fast Fourier transformation at a second operation device which includes a subtractor and a logic circuit. In the subtractor, the sample signals are delayed N/2 samples to halve the number of sample signals. The logic circuit executes an operation for the sample signals, taking advantage of the fact that some frequencies of the outputs of the Fourier transform are represented as the conjugate complex of the other outputs of the Fourier transform. The sample signals fast-Fourier-transformed and produced at the second operation device are subjected discrete Fourier transformation in a processor, where an output for detecting the multifrequency signals is obtained.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a digital multifrequency signaling receiving system using discrete Fourier transform and more specifically to a digital multifrequency signaling receiving system with reduced number of operations. 
     Presently, multifrequency signaling (hereinafter referred to as MF signaling) is used for transmission of inter-office register signaling as standardized signaling between crossbar exchanges. For the exchanges themselves, stored-program controlled exchanges and time division multiplexed exchanges have come to be used, and for the signaling system, there is a movement to swtich over to the common channel signaling system. These stored-program controlled exchanges, however, must employ the MF signaling for the crossbar exchanges, so that it is important to improve receiving systems for such MF signaling. 
     In such MF signaling receiving systems, the input frequency has conventionally been detected by the digital filter (DF) method. This DF method detects the frequency of the input signal through filter banks. For technical literature, reference is made to &#34;An All Digital Telephony Signalling Module&#34; (IEEE Proc. circuit and system theory, 1975), by P. Kaul and H. Lieberman. 
     According to the DF method, however, filters for an analogue receiver are directly replaced by the digital filters, so that the order of the filters becomes large and the size of hardware used or number of operations will be increased. 
     As another conventional method, there is the discrete Fourier transform (DFT) method. In this method, the input signal is Fourier-transformed, and the input frequency is detected by obtaining the coefficients of the Fourier series of the input signal. For technical literature concerning this method, reference is made to &#34;Digital MF Receiver using Discrete Fourier Transform&#34; (IEEE Trans. on Communications vol. COM-21, No. 12). 
     However, as may be seen from the above literature, software in a universal computer cannot process the input signal in real time in the DFT MF reception system, so that the receiver need be composed of dedicated hardware. Although such receiver may effectively be used as a receiver for large-office service, it is defective in economical efficiency, extension cost, etc. for small-office use. 
     SUMMARY OF THE INVENTION 
     The object of this invention is to provide a digital multifrequency signaling receiving system eliminating the above defects, reducing the number of operations in the operation processes for MF signals, and providing high economical efficiency and extensibility even for small-office use. 
     In order to attain the above object, the digital multifrequency signaling receiving system of this invention comprises a first operation means for executing an operation to multiply multifrequency (MF) signals as input signals composed of N samples by a window function to obtain products, the window function including coefficients required for fast Fourier transformation of the products; a second operation means for fast Fourier transforming of the products as sample signals, the second operation means including a delay means for delaying the products to halve the number of the products and a subtractor for delivering difference signals or N/2 sample signals representing the difference between the delayed products and the current products, and a logic circuit for executing a logical operation on the difference signals or N/2 sample signals, taking advantage of the fact that some outputs of a Fourier transform are represented as the conjugate complex of the other outputs of Fourier transformation in the process of Fourier transform for the N/2 sample signals delivered from the subtractor; a third operation means for executing discrete Fourier transform for the MF signal samples delivered from the logic circuit; and a fourth operation means for providing an output to detect the input frequencies of the discrete-Fourier-transformed MF signals. 
     With the above-mentioned construction, the digital multifrequency signaling receiving system of this invention performs fast Fourier transformation of the sample signals immediately before discrete Fourier transformation at the second operation means. The number of multiplications in the detection of the input MF signals can be reduced be using fast Fourier transform and by taking advantage of the fact that some outputs of the fast Fourier transform may be represented by the conjugate complex of the other outputs in the fast Fourier transform process. Accordingly, there may be provided an economical digital multifrequency signaling receiving system using a general microprocessor in which a calculation program in accordance with a flow chart is performed, and which is efficient for a small-office use receiving system. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram for illustrating the operation processes for MF signals according to this invention; 
     FIG. 2 is a chart showing the operation sequences of fast Fourier transform (FFT) parts shown in FIG. 1; 
     FIG. 3 is a chart indicating that the operation sequences of FIG. 2 can be simplified; 
     FIG. 4 is a block diagram showing the specific arrangements of sections for executing the operations in the operation processes as shown in FIG. 3; 
     FIG. 5 is a circuit diagram showing an example of an input part as shown in FIG. 4; 
     FIG. 6 is a circuit diagram showing another example of the input part as shown in FIG. 4; 
     FIG. 7 is a specific circuit diagram of a logic circuit in an FFT operation part as shown in FIG. 4; 
     FIG. 8 is a more specific block diagram based on the block diagram of FIG. 4; 
     FIG. 9 is a specific connection diagram of a logic circuit constituting the FFT operation part as shown in FIG. 8; 
     FIG. 10 is a specific connection diagram of another logic circuit as shown in FIG. 8; 
     FIG. 11 is a specific connection diagram of still another logic circuit as shown in FIG. 8; 
     FIG. 12 is a specific connection diagram of a logic circuit constituting the discrete Fourier transform (DFT) operation part as shown in FIG. 8; 
     FIG. 13 is a block diagram showing an example in which part of the hardware of FIG. 4 is included in a processor; 
     FIG. 14 is a block diagram showing an example in which part of the hardware of FIG. 13 is included in a processor; 
     FIG. 15 shows another example of a subtractor at section B1 as shown in FIG. 4; 
     FIG. 16 is a time chart for illustrating the operation of the example of FIG. 15; 
     FIG. 17 is a block diagram showing circuit arrangements according to another embodiment of this invention; and 
     FIG. 18 is a block diagram showing still another embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In general, MF signaling is formed by combining two out of six frequencies--700 Hz, 900 Hz, 1,100 Hz, 1,300 Hz, 1,500 Hz and 1,700 Hz. The common period of the six frequencies is 10 msec. MF signaling sampled with a sampling period of 125 μsec, 80 samples of the MF signal are obtained. That is, the frequency of the MF signaling may be detected by making an analysis for each 80 samples. The discrete Fourier transform F k  of an MF signaling f n  =f(nT) (n=0, 1, . . . N-1) at K×100 Hz (k=7, 9, 11, 13, 15, 17) is calculated as follows: ##EQU1## where T is sampling period (125 μsec), N is number of samples (80), Ω is detection frequency space of discrete Fourier transform (Ω=2π/NT=2π×100), and j=√-1. 
     The existence of signals for each of the MF signaling frequencies may be detected by comparing the square of the absolute value of F k , that is, 
     
         P(kΩ)=|F(kΩ)|.sup.2 (k=7, 9, 11, 13, 15, 17) 
    
                                                                (2) 
     with a fixed threshold value. Here h n  is a window function for improving the frequency selectivity of P(kΩ), such as humming window given by ##EQU2## 
     In equation (1), ##EQU3## W is a unit vector obtained by dividing into 80 equal parts a unit circle of a Gaussian plane with real and imaginary numbers respectively on the axes of the abscissa and ordinate, shifted -2π/80 radian from the real axis. For example, W 0  =1, W 40  =-1, W 20  =-j, W 60  =j, ##EQU4## 
     80-point DFT system or DFT 80  directly calculates equation (1). Suffix n of DFT n  represents the number of points of the discrete Fourier transform. The DFT 80  system requires 80 multiplications of the window function, 8×6 multiplications of a sine wave of W and 80×6 multiplications of a cosine wave of W. Thus, 1,040 (=80+80×6×2) multiplications must be carried out in 10 msec in a DFT 80 system. Here the operation of a vector sum and comparator is not included, because this part can be realized only by ROMs as will be described later. 
     FIG. 1 indicates that the operation processes for the MF signals of this invention are executed by an input part or means 1, a window function multiplication part or means 2, an FFT operation part or means 3, a DFT 5  operation part or means 4 for 5-point discrete Fourier transform, a vector sum and comparator part or means 5, and an output part or means 6. The window function multiplication part 2 consists of 5 portions W 0  to W 4 , and the FFT operation part 4 consists of 5 portions FFT 0  to FFT 4 . The DFT 5  operation part 4 consists of 6 DFT 5  &#39;s corresponding to 6 frequencies of the MF signaling. 
     The input part 1 classifies the MF signals into 80 samples f 0  to f 79 , applying f n  to W 0  where 
     
         n=5l+20j(l=0, 1, 2, 3; j=0, 1, 2, 3),                      (4) 
    
     to W 1  where 
     
         n=5l+2j+1(l=0, 1, 2, 3; j=0, 1, 2, 3),                     (5) 
    
     to W 2  where 
     
         n=5l+20j+2(l=0, 1, 2, 3; j=0, 1, 2, 3),                    (6) 
    
     to W 3  where 
     
         n=5l+20j+3(l=0, 1, 2, 3; j=0, 1, 2, 3),                    (7) 
    
     and to W 4  where 
     
         n=5l+20j+4(l=0, 1, 2, 3; j=0, 1, 2, 3).                    (8) 
    
     In the window function multiplication part 2, the 80 samples of input MF signals f 0  to f 79  are multiplied by g n  obtained by multiplying the window function h n  by A=cos π/8 and or 1/√2 as constants required for fast Fourier transform as will be mentioned later. Thus, g n  can be given by ##EQU5## where i=0, 1, 2, 3, 4 and j=0, 1, 2, 3. If n=11, for example, i=1 and j=0, and so f 11  is multiplied by g 11  =(1/√2)h 11 . 
     FIG. 3 shows the FFT operation part 3 in detail. In order to give a detailed explanation of the drawing of FIG. 3, it is necessary first to describe the operation sequences, with reference to FIG. 2. FIG. 2 illustrates a W 0  -FFT 0  part of FIG. 1 in detail, in which the FFT operation part 3 is formed of B1, B2, B3 and B4. In FIG. 2, &#34;An algorithm for the Machine Calculation of Complex Fourier Series&#34; (Mathematics of Computation, Vol. 19, No. 90, 1965) by Cooley, J. W. and Tukey, L. W. is applied to the 80 samples of the MF signaling. 
     The input and output samples of the FFT operation part 3 in FIG. 2 are selected from those for W 0  and FFT 0 , for example; the description here may cover also other W i  and FFT i  (i=1, 2, 3, 4). In FIG. 2, an input MF signal f n  (n=0, 1, . . . 79) is multiplied by h n  (n=0, 1, . . . 79) at the window function multiplication part 2. That is 
     
         x.sub.n =h.sub.n f.sub.n                                   (10) 
    
     Then, x n  (n=0, 1, . . . 79) is applied to the input of the FFT operation part 3. 
     In the FFT operation part 3, the output F k  of DFT 80  is obtained as follows: ##EQU6## In equation (11), the sum covering n=0 to 79 may be divided into two portions; n=0 to 39 and n=40 to 79. Thus, F k  can be obtained as follows: ##EQU7## Here the second term may be changed into ##EQU8## 
     W.sup.(n+40)k by replacing n with n+40. Then we obtain ##EQU9## That is, it will be required only that a n  =x n  +x n+40  W 40k  be calculated for the input signal x n , and that 40-point DFT (DFT 40 ) be calculated for a n , assuming, ##EQU10## Considering that W 40  is -1 as mentioned before and k is an odd number in an MF receiver, a n  is 
     
         a.sub.n =x.sub.n -x.sub.n+40                               (15) 
    
     These operations are performed at B1 of FIG. 2. 
     Thus, F k  may be calculated according to equation (14) from a n  which can be obtained from x n . Hereupon, equation (14) may be divided into two portions; n=0 to 19 and n=20 to 39. That is, we obtain ##EQU11## Then, after b n  =a n  +a n+20  W 20k  is calculated, F k  can obtained from 20-point DFT (DFT 20 ) given by ##EQU12## Since W 20  is -j as mentioned before, W 20k  =j for k=7, 11, 15 and W 20k  is 31j for k=9, 13, 17. Namely, b n  =a n  +ja n+20  is calculated for 700 Hz, 1,100 Hz and 1,500 Hz, and b n  =a n  -ja n+20  is calculated for 900 Hz, 1,300 Hz and 1,700 Hz. These operations are performed at B2 of FIG. 2. 
     Thus, F k  may be calculated according to equation (17), obtaining a n  from x n  and b n  from a n . Equation (17) may be divided into two portions: n=0 to 9 and n=10 to 19. That is, we obtain ##EQU13## Then, after c n  =b n  +b n+10  W 10k  is calculated, F k  can be obtained from 10-point DFT (DFT 10 ) given by ##EQU14## Since W 10  is (1/√2)(1-j) as mentioned before, we obtain ##EQU15## That is, ##EQU16## are calculated. These operations are performed at B3 of FIG. 2. 
     Thus, F k  may be calculated according to equation (19), obtaining a n  from x n , b n  from a n , and c n  from b n . Equation (19) may be divided into two portions; n=0 to 4 and n=5 to 9. That is, we obtain ##EQU17## Then, after d n  =c n  +c n+5  W 5k  is calculated, F k  can be obtained from 5-point DFT (DFT 5 ) given by ##EQU18## Since ##EQU19## as mentioned before, d n  is ##EQU20## Accordingly, d n  can be calculated from c n  according to equation (23). 
     These operations are performed at B4 of FIG. 2. 
     Thus, the input signal f n  is multiplied by the window function h n  to provide x n , from which a n  is obtained. Then, b n , c n  and d n  are obtained from a n , b n  and c n  respectively, and finally F k  can be obtained from d n  according to equation (23). Further, the frequency of the input signal may be detected by obtaining P(kΩ) (k=7, 9, 11, 13, 15, 17) from F k  according to equation (2) and comparing it with the fixed threshold value. These processes are shown in the flow charts of FIGS. 1 and 2. 
     The input part makes rearrangements in accordance with equations (4) to (8), and then the window function multiplication part calculates x n  =h n  f n . Moreover, sections B1, B2, B3 and B4 perform operations of a n  =x n  -x n+40 , b n  =a n  +a n+20  W 20k , c n  =b n  +b n+10   W 10k , and d n  +c n  +c n+5  W 5k  respectively, the DFT 4  operation part operates ##EQU21## and the vector sum and comparator part operates P(kΩ)=|F k  | 2  (k=7, 9, . . . 17). 
     Now there will be described features and advantages of this invention. 
     FIG. 2, in which the FFT is applied to an MF receiver, can be simplified as shown in FIG. 3, and the number of operations can be reduced. The first facility for such simplification is the relations ##EQU22## in FIG. 2. Here c n   k  is c n  for k. The second facility is that the number of multiplications at the FFT operation part can be reduced by previously multiplying the window function h n  by the coefficient 1/√2 of equation (20) and coefficient A of equation (24). Namely, the input MF signal is multiplied by g n  given by equation (9) as follows: 
     
         y.sub.n =f.sub.n g.sub.n                                   (26) 
    
     These two points are the features of this invention. 
     Meanwhile, it can be understood that equation (25) holds as follows. That is, in the equation d n   9  =d n   7 , the real part of d n   9  equals the real part of d n   7 , and the imaginary part of d n   9  equals the imaginary part of d n   7 , provided its sign is inverted; d n   9  and d n   7  are conjugate complex numbers. 
     With respect to d n   9  =d n   7 , for example, d n   9  is ##EQU23## according to equation (24). From equation (20), c n   9  is ##EQU24## In equation (28), b n   9  becomes ##EQU25## Further, a n   9  is ##EQU26## Here x n  -x n+40  =a n   7 , so that equation (29), (28) and (27) can be respectively rewritten as follows: ##EQU27## Accordingly, d n   9  =d n   7  holds. 
     Likewise, d n   17  =d n   15  of equation (25) holds because we can obtain ##EQU28## 
     Moreover, d n   13  =c n   13  +(B=Aj)c n+5   13  of equation (24) also holds because we can obtain ##EQU29## 
     From this first point of view, the outputs of d n   9 , d n   13  and d n   17  need not be calculated, but may be obtained from the outputs of d n   7 , d n   11  and d n   15  respectively. 
     Further, from a second point of view, the operations for the sections B3 and B4 may be simplified by incorporating the multiplications for the sections B3 and B4 into the window function. g n  (n=0, 1, . . . 79) is the product of the window function and the constants for the sections B3 and B4, and y n  is the products of the input f n  and g n . 
     As may be seen from the above description, the operation processes of FIG. 2 can be simplified as shown in FIG. 3. A section B5 of the FFT operation part is a section for obtaining d n   9 , d n   13  and d n   17  respectively from d n   7 , d n   11  and d n   15 , omitting the operations for d n   9 , d n   13  and d n   17  at the sections B2, B3 and B4. 
     According to the operation of FIG. 3, for the reception of MF signaling, 16×5 multiplications of the window function and the constant g n , 4×5 multiplications of c at a section B 4-1  and 4×4×6 the multiplications at the DFT 5  operation part are required. Thus, the number of multiplications is 16×5+4×5+4×4×6=196 in 10 msec. 
     FIG. 4 shows the specific hardware arrangements of sections for actually executing the operations in the operation processes as shown in FIG. 3. The input part 1 to which the MF signal is applied is provided with an analogue-digital converter 11 when the MF signal is an analogue signal. When the MF signal is a digital signal, there is provided a digital interface circuit 12, as shown in FIG. 5. Moreover, if the digital signal is compressed in a nonlinear code, there will be added a digital expander 13 for converting the nonlinear code into a linear code, as shown in FIG. 6. The digital expander 13 may be composed of ROMs (read-only memory), for example. The MF signal f n  from the input part 1 is applied to a multiplier 21 of the window function multiplication part 2. The constant g n  given by equation (9) is stored in the ROM 22, which delivers g n  corresponding to f n  to multiply the MF signal f n  by g n  at the multiplier 21. 
     Outputs from the window function multiplication part 2 are applied to the section B1 of the FFT operation part 3. The section B1 is composed of a delay circuit 31 for delaying the input signal 40 samples, for example, the delay circuit 31 including a shift register or RAM (random access memory), and a subtractor 32 providing the difference between the current input signal and the delayed output from the delay circuit 31. 
     The outputs from the subtractor 32 are applied to the sections B2 and B3. The sections B2 and B3, which are composed of a register section 33 including four parallel-connected registers 0, 1, 2, 3, a first logic circuit 34 and a register 35, perform operations for processors B 21  and B &#39;-1  as shown in FIG. 3, as well as time-divided operations for processes B 2-2  and B 3-2  and processes B 2-1 , B 3-1 , B 2-2  and B 3-2  of another FFT i  (i=1, 2, 3, 4). 
     The four registers 0, 1, 2 and 3 are supplied respectively with 
     a 0 , a 1 , a 2 , a 3 , a 4 , a 5 , a 6 , a 7 , a 8  and a 9  (for register 0), 
     a 20 , a 21 , a 22 , a 23 , a 24 , a 25 , a 26 , a 27 , a 28  and a 29  (for register 1), 
     a 10 , a 11 , a 12 , a 13 , a 14 , a 15 , a 16 , a 17 , a 18  and a 19  (for register 2) and 
     a 30 , a 31 , a 32 , a 33 , a 34 , a 35 , a 36 , a 37 , a 38  and a 39  (for register 3). 
     First, prescribed operations are executed for a 0 , a 20 , a 10  and a 30  at the first logic circuit 34, and the results are transferred to a register 35 and then applied to a buffer memory 36. 
     FIG. 7 shows a specific arrangement of the first logic circuit 34, where prescribed operations are performed for the processes B 2-1  and B 3-1  of FIG. 3. In FIG. 7, adders 1 to 6 calculate, respectively, a i+10  +a i+30 , a i+10  -a i+30 , the sum of the output of the adder 1 and a i+20 , the difference between a i-20  and the output of the adder 1, the sum of a i  and the output of the adder 2, and the difference between a i  and the output of the adder 2, and there appear ##EQU30## outputs 7 to 10 respectively. Here i varies from 0 to 9. These outputs are applied to a logic circuit 41 through the register 35 and the buffer memory 36 logic circuit. 
     For example, a processor is used as the logic circuit 41 
     In the logic circuit 41, ##EQU31## are calculated with i=5, 6, 7, 8, 9 for the outputs U i , X i , Y i  and Z i . These outputs are the outputs of B 4-1  as shown in FIG. 3. 
     Then, ##EQU32## are calculated with i=0, 1, 2, 3, 4. These outputs are the outputs of B4 of FIG. 3, which correspond to the real and imaginary parts of d i   7 , d i   11 , d i   15  and d i   13  respectively. 
     Subsequently, to calculate d i   9 , d i   17  and d i   13 , ##EQU33## are calculated respectively for the imaginary parts of d i   9 , d i   17  and d i   13 . Thus, the operations for the section B5 of FIG. 3 are completed. 
     Then, operations corresponding to the DFT 5  operation part 4 of FIG. 1 are performed. First, d n   k  is multiplied by W nk  with k=7 and n=0, 1, 2, 3, 4, and ##EQU34## is calculated. Likewise ##EQU35## for k=9, 11, 13, 15, 17 is calculated. 
     In the vector sum and comparator 5, the sum of the square of the real part of F k  and the square of the imaginary part of F k  is calculated for k=7, 9, 11, 13, 15, 17, and is compared with a predetermined fixed threshold value. The output of the logic circuit 41, logical value &#34;1&#34; (when the sum is larger than the fixed threshold value) or logical value &#34;0&#34; (when the sum is smaller than the threshold value) is delivered to a central processor of an exchange via the interface of the output part 6. 
     Referring now to FIGS. 8 to 12, there will be described further specific arrangements of the FFT operation part 3 and the DFT 5  operation part 4 as shown in FIG. 4. 
     In FIG. 8, the same reference numerals are employed to designate parts as elements corresponding to those shown in FIG. 1. 
     The register 0 to 7 (33 1  and 33 2 ) at the sections B2 and B3 of the FFT operation part 3 are supplied with a i  as shown in FIG. 3 or given by equation (15). That is, 
     a 0 , a 1 , a 2 , a 3 , and a 4  (for register 0), 
     a 20 , a 21 , a 22 , a 23  and a 24  (for register 1), 
     a 10 , a 11 , a 12 , a 13  and a 14  (for register 2), 
     a 30 , a 31 , a 32 , a 33  and a 34  (for register 3), 
     a 5 , a 6 , a 7 , a 8  and a 9  (for register 4), 
     a 25 , a 26 , a 27 , a 28  and a 29  (for register 5), 
     a 15 , a 16 , a 17 , a 18  and a 19  (for register 6), and 
     a 35 , a 36 , a 37 , a 38  and a 39  (for register 7) 
     are applied to the registers 0 to 7 respectively. 
     Subsequently, (a i , a i+20 , a i+10  and a i+30 ) and (a i+5 , a i+25 , a i+15  and a i+35 ) (i=0, 1, 2, 3, 4) are applied to two logic circuits 34 1  and 34 2  respectively. For these logic circuits 34 1  and 34 2 , the circuit arrangement of FIG. 7 may be used. 
     Outputs U i , X i , Y i  and Z i  of the logic circuit 34 1  are applied to delay circuits 35 0 , 1, 2, 3 respectively. These delay circuits 35, composed of shift registers or RAM&#39;s, for example, provide a delay equivalent to the delay of a logic circuit 37. 
     Outputs U i+5 , X i+5 , Y i+5  and Z i+5  of the logic circuit 34 2  are applied to the logic circuit 37. 
     The logic circuit 37, which is so constructed as shown in FIG. 9, performs operations corresponding to equation (34). As shown in FIG. 9, the logic circuit 37 is composed of four multipliers 90, 91, 92 and 93, adder-subtractors 94, 95, 96 and 97, and complementary circuits 98 and 99. 
     In the logic circuit 37, inputs U i+5 , X i+5 , Y i+5  and Z i+5  are severally multiplied by a constant C(=B/A=tan(π/8)), X i+5  is added to the output of the multiplier 90 by the adder 94, and the sign of the resultant figure is inverted by the complementary circuit 98 to provide an output Q i+5 . 
     The output of the multiplier 91 is subtracted from U i+5  by the subtractor 95 to provide an output P i+5 . 
     Z i+5  is added to the output of the multiplier 92 by the adder 96, and an output R i+5  is obtained by inverting the sign of the output by means of the complementary circuit 99. 
     The output of the multiplier 93 is subtracted from Y i+5  by the subtractor 97 to provide an output S i+5 . Here i varies from 0 to 4. These outputs are applied to a logic circuit 38. 
     The logic circuit 38, which is supplied with outputs U i , X i , Y i  and Z i  of the delay circuits 35 0 , 1, 2, 3, and outputs P i+5 , Q i+5 , R i+5  and S i+5  of the logic circuit 37, performs operations for B 4-2  of FIG. 3 corresponding to equation (34). The logic circuit 38, as shown in FIG. 10, is composed of adders 1 to 4 and subtractors 5 to 8. U i  and P i+5  are added by the adder 1 to provide an output Re(d i   7 ). X i  and Q i+5  are added by the adder 2 to provide an output Im(d i   7 ). Y i  and P i+5  are added by the adder 3 to provide an output Re(d i   11 ). Z i  and S i+5  are added by the adder 4 to provide an output Im(d i   11 ). P i+5  is subtracted from U i  by the subtractor 5 to provide an output Re(d i   15 ). Q i+5  is subtracted from X i  by the subtractor 6 to provide an output Im(d i   15 ). R i+5  is subtracted from Y i  by the subtractor 7 to provide an output Re(d i   13 ). S i+5  is subtracted from Z i  by the subtractor 8 to provide an output -Im(d i   13 ). Here i varies from 0 to 4. These outputs are applied to a logic circuit 39. 
     The logic circuit 39, which includes complementary circuit 39 1 , 39 2  and 39 3  as shown in FIG. 11, receives outputs from the logic circuit 38 and performs operations for the section B5 of the FFT operation part as shown in FIG. 3 or operations corresponding to equation (36). Outputs Im(d i   9 ), Im(d i   15 ) and Im(d i   17 ) are obtained by inverting the signs of inputs Im(d i   7 ), Im(d i   13 ) and -Im(d i   17 ) respectively. Here i varies from 0 to 4, and these outputs are applied to a logic circuit 42 as shown in FIG. 8. 
     The logic circuit 42, as shown in FIG. 12, is composed of, for example, twelve registers 0 to 11, two selectors 120 and 121 for suitably selecting sample outputs from these registers 0 to 11, first and second multipliers 122 and 123 provided for the outputs from the selector 120, third and fourth multipliers 124 and 125 provided for the outputs from the selector 121, a first adder 126 connected to the first and third multipliers 122 and 124 and a second adder 127 following the first adder 126, a third adder 128 connected to the multipliers 123 and 125 and a fourth adder 129 following the third adder 128, and shift registers 130 and 131 provided correspondingly to the adders 127 and 129. The logic circuit 42 has its registers 0 to 11 supplied with outputs Re(d i   k ) and Im(d i   k ) (i=0, 1, 2, 3, 4; k=7, 9, 11, 13, 15, 17) from the logic circuit 39, as illustrated. For example, 5 samples for i=0, 1, 2, 3, 4 are supplied to each of the registers 0  to 11, and zeroth samples of th registers 0 , 1 are selected by the selectors 120 and 121 and multiplied by Re(W i7 ) at the first and fourth multipliers 122 and 125. The samples are multiplied by Im(W i7 ) at the second and third multipliers 123 and 124, and the results of multiplication are subjected to addition or subtraction at the first and third adders 126 and 128, the outputs of which are added respectively to the outputs of the shift registers 130 and 131 by the second and fourth adders 127 and 129. Then, first, second, third and fourth samples are selected by the selectors 120 and 121, operated as aforesaid, and added to the zeroth, first, second and third operation results stored in the shift registers. Re(W i9 ) and Im(W i9 ) are applied for the zeroth samples of the registers 2 , 3, while Re(W i11 ) and Im(W i11 ) are supplied for the zeroth samples of the registers 4 and 5. Re(d i   k ) and Im(d i   k ) applied successively to the registers are subjected to prescribed operations, and then final outputs F k  (k=7, 9, 11, 13, 15, 17) are obtained as Re(F k ) and Im(F k  ). Namely, as mentioned before, the logic circuit 42 performs operations for the DFT 5  operation part 4 as shown in FIG. 1 or operations corresponding to equation (23). 
     The outputs obtained from the logic circuit 42 are applied to a logic circuit 51 formed of the vector sum and comparator part 5 as shown in FIG. 1 or ROM. 
     The vector sum and comparator part 5, as shown in FIG. 17, is composed of multipliers 178 and 179 to which outputs Re(F k ) and Im(F k ) from the DFT operation part are applied respectively, an adder 180 for adding outputs from the multipliers 178 and 179 or making a calculation (Re(F k )) 2  +(Im(F k )) 2 , and a comparator 181 for comparing an output from a threshold value generator 182 with an output from the adder 180. If a ROM is used for the vector sum and comparator part, address bits necessary for the ROM is at most the sum of the bits to express the absolute value of Re(F k ) and the bits to express the absolute value of Im(F k ). The contents of ROM is 1 for the addresses that (Re(F k )) 2  +(Im(F k )) 2  is larger than the threshold value, and 0 for the addresses that the threshold value is larger. With such ROM, a result of comparison with the threshold value may be obtained at the output of ROM by applying the absolute values of Re(F K ) and Im(F k ) to the address port of ROM. 
     Although this invention may be formed of the hardware as shown in FIG. 4 or 8, as described hereinbefore, the outputs from the section B1 composed of the delay circuit 31 and subtractor 32 forming part of the FFT operation part 3 may alternatively be applied directly to the register 35 1 , as shown in FIG. 13, to perform the operations for the registers 33 and logic circuit 34 of the FFT operation part 3 as shown in FIG. 4 in the processor 41 through a buffer memory 36 1 . 
     Referring to FIG. 14, the outputs of the window function multiplication part 2 are directly applied to the register 35 2 , whereby the operations for the difference operation part B1, registers 33 and the logic circuit 34 of the FFT operation part 3 as shown in FIG. 4 may be performed in the logic circuit 41 through a buffer memory 36 2 . 
     FIG. 15 shows another example of the section B1 of the FFT operation part 3 for delaying and difference operation, in which two sets of delay circuits 31a, 31b and subtractors 32a, 32b are connected in parallel with each other. As may be seen from the description of the section B1 with reference to FIG. 3, this is an example which enables processing of input signals with a double number of circuits, in consideration of the fact that 80-point discrete Fourier transform DFT 80  may be reduced to 40-point DFT 40  or halved in the number of operations. FIG. 16 is a time chart for such processing. Referring to FIG. 16(a), a first MF signaling expressed by Z, A, B, each consisting of 40 samples, is applied to the subtractor 32a. The first MF signaling (Z, A, B) is delayed 40 samples by the delay circuit 31a (FIG. 16(b)). A second MF signaling (C, D, E) (FIG. 16(c)) is applied to the subtractor 32b, and at the same time delayed 40 samples by the delay circuit 31b (FIG. 16(d)). Subtractor 32a produces the difference signals (Z-A) and (A-B) (FIG. 16(e)). The subtractor 32b produces difference signals (C-D) and (D-E) (FIG. 16(f) after subtraction. FIG. 16(g) shows a control signal supplied to a selector 150. At its low level the control signal causes the selector 150 to select an output f from the subtractor 32b, while at the high level it induces the selector 150 to select an output e from the subtractor 32a. With an output thus obtained from the selector 150, the first MF signaling (A, B) with the samples of 10 msec is reduced to a signal (A-B) (FIG. 16(h)) with samples of 5 msec, and the second MF signal (C, D) is also reduced to a signal (C-D) (FIG. 16(h)) with samples of 5 msec. For each of these signals (A-B) and (C-D), 40-sample discrete Fourier transform DFT 40  is performed. Accordingly, a double number of circuits may be processed by using the conventional DFT 80 . 
     The operation for the output of the selector 150 can be achieved by the DFT 40  and vector sum and comparator 5 according to the prior art, as shown in FIG. 15. When performing the operation in the processor 41, as shown in FIG. 13, instead of using the DFT 40 , however, the function g n  may be stored in the ROM of the window function multiplication part 2 for reducing the number of operations. 
     FIG. 17 is a specific circuit diagram showing the DFT 40  and vector sum and comparator of FIG. 15. The DFT 40  is composed of a register 171, multipliers 172 and 173 for multiplying an output from the register 171 respectively by sine and cosine components, and adders 174 and 175 and shift registers 176 and 177 provided for the respective products from the multipliers 127 and 173. In this case, the shift registers 176 and 177 have double memory capacity so that input signals for the double number of circuits may be processed in response to the use of the two sets of delay circuits and subtractors in the difference operation part B1. 
     FIG. 18 shows an embodiment capable of processing signals for the same number of circuits with the conventional DFT, but reduced hardware for the DFT 40 . The DFT 40  is composed of a register 181, a multiplier 182 for multiplying an output from the register 181 by sine and cosine components, and an adder 183 and a shift register 184 provided for the products from the multiplier 182. In this embodiment, the 80-sample MF signal is reduced to a 40-sample MF signal by the difference operation part B1, so that the number of operations are reduced to the half of the conventional case. In this case, a multiplier 182 serially performs the multiplications by the sine and cosine components, making the most of the surplus processing time for 40 samples. The shift register 184 has a memory capacity capable of storing the sum of the multiplication values from the sine and cosine components. In the vector sum and comparator part 5 of this embodiment, the products of the output obtained from the DFT 40  and the sine and cosine components are squared by a multiplier 185 and delayed by a shift register 187, the subsequently obtained sine or cosine component is added to the cosine or sine component by an adder 186, and the output of the adder 186 is compared with an output from a threshold value generator 182. As a result, a logical level &#34;1&#34; is delivered if the output is larger than the threshold value, whereas a logical level &#34;0&#34; is delivered if the output is smaller than the threshold value. 
     The multipliers and adder-subtractors used in the above embodiment may be selected among those which appear in &#34;An Approach to the Implementation of Digital Filters&#34; (IEEE, Trans. Audio Electroacoustics, vol. AU-16 pp. 413 to 421, September, 1968) by Leland B. Jackson, James F. Kaiser and Henry S. McDonald. For the processor may be used a microcomputer, such as 8080 manufactured by Intel Corporation and M 6800 manufactured by Motorola Semiconductor Products Inc., etc.