Abstract:
The control circuit according to the invention consists firstly of two control terminals (S 1 , S 2 ) to which drive pulses of at least two different types can be applied, i.e. a first pulse type (S) designed to obtain one position (S) of the solenoid and which present a first level of amplitude, and a second pulse type (R) designed to obtain a second position (R) of the solenoid and which present a second level of amplitude different from that of the pulses (S) of the first type and with the same polarity and secondly, a discrimination circuit (R 1 , R 2 , A) for the pulses (R, S) of these two types according to their level of amplitude, this discrimination circuit (R 1 , R 2 , A) being connected to a switching circuit (CS, CS&#39;, CR, CR&#39;) controlling supply of the solenoid (B). The invention is also applicable to solenoids comprising one coil as well as to solenoids having two separate coils or with a common intermediate connecting point.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention concerns a control circuit for a bistable solenoid which can be used particularly, but not exclusively, in an electromagnetic relay, in a magnetic control electromagnet, for example for clamping or releasing of a lock, or even in a bistable electrovalve. 
     It should be borne in mind that a bistable solenoid usually consists of a magnetic circuit acting on a mobile armature in order to lead it to one or other of the following two stable positions: 
     a first position R corresponding to a maximum reluctance of the magnetic circuit, and 
     a second position S corresponding to a minimum reluctance of the magnetic circuit. 
     These two positions are usually denoted by the terms &#34;RESET&#34;, as regards the first, and &#34;SET&#34; as regards the second. 
     The magnetic circuit enabling these two positions to be obtained generally includes: 
     a permanent magnet which polarizes the magnetic field inside the circuit, in the absence of any external field, and 
     at least one coil which, when crossed by a current, creates a field which entrenches itself or is added to the one created by the magnet. 
     Control of these bistable solenoids is carried out using pulses, the duration of which must be sufficient in order that the mobile armature and mobile equipment connected to it take up the sought after stable position. 
     When the bistable solenoid includes only one coil, it is necessary to invert the polarities at the terminals of this coil so as to obtain the two sought after stable positions S and R. 
     On the other hand, where the solenoid includes two coils connected in series and to each other through a middle point, the pulse intended to obtain position S is applied to the terminals of one of the coils, whilst the pulse intended to obtain position R is applied to the terminals of the other coil, the middle point between the two coils capable of being permanently connected to one of the two feed coils. 
     DESCRIPTION OF THE PRIOR ART 
     These circuits, although currently used, present a certain number of drawbacks. 
     Where they include a single coil, they require crossing of the connections in order to obtain from the two feed wires an inversion of the current crossing the coil. 
     Where they include two coils with an intermediate connecting point, they introduce at least three connection terminals and two control pulse sources in order to obtain positions S and R. 
     Moreover, these solutions are not suitable for the realization of control circuits with a matric structure, indeed: 
     the single coil solution does not enable a reverse-lock diode to be inserted inside the circuit of this coil, 
     the two coil solution requires either the number of matrix lines or colums to be doubled. 
     OBJECT OF THE INVENTION 
     The aim of the invention, therefore, is to eliminate these drawbacks. It does this by proposing a control circuit for a bistable solenoid in which an active electronic control circuit is connected to the magnetic circuit unit, permanent magnet and coils so as to allow for control of the coil by the voltage pulses delivered on two wires and without polarity inversion. 
     SUMMARY OF THE INVENTION 
     According to the invention, this control circuit is particularly characterized in that it includes firstly, two control terminals to which can be applied control pulses of at least two different types, i.e. a first pulse type S designed to obtain solenoid position S, the pulses of this type presenting a first level of amplitude, and a second pulse type R designed to obtain solenoid position R, the pulses of this type presenting a second level of amplitude different to that of pulses S of the first type and with the same polarity and secondly, a discrimination circuit for pulses R, S of these two types according to their level of amplitude, this discrimination circuit being connected to a switching circuit controlling feed of the solenoid so as to obtain a minimum reluctance of the magnetic circuit in response to pulses S of the first type and a maximum reluctance in response to pulses R of the second type. 
     Of course, the solenoid control circuit is also applicable both to solenoids comprising one coil and those having two coils or with a common intermediate connecting point. 
     Moreover, according to another characteristic of the invention, the abovementioned discrimination circuit includes means for enabling the amplitude of the pulses applied to the above-mentioned control terminals to be compared in relation to three successive predetermined reference voltage zones, namely: 
     a first voltage zone including the voltage level of pulses S of the first type, 
     a second voltage zone including the voltage level of pulses R of the second type, and 
     a third voltage zone included between the levels of the two types of pulses R, S, and where the amplitude of the said pulses must never occur. 
     In this case, the switching means connected to the discrimination circuit control feed of the coil in such a way as to obtain a minimum reluctance of the magnetic circuit when the amplitude of the pulses supplied by the generator is included in the first voltage zone and a maximum reluctance of the magnetic circuit when the amplitude of the pulses supplied by the generator is included in the second reference voltage zone. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Embodiments of the invention shall be described later by means of examples which are not exclusive and with reference to the drawings annexed in which: 
     FIG. 1 is a diagram representing the form of the two types of pulses used for control of the solenoid as well as the three reference voltage zones used by the control circuit. 
     FIG. 2 is a theoretical diagram of a single coil solenoid control circuit. 
     FIG. 3 is a theoretical diagram of a two coil control circuit. 
     FIG. 4 is a diagram illustrating the incidence of the fall and rise times of the control pulses as regards the functioning of the circuits represented in FIGS. 2 and 3. 
     FIG. 5 is an embodiment of a solenoid control circuit with one coil realized according to transistor technology. 
     FIG. 6 is a partial diagram of a control circuit of the type represented by FIG. 2 but in which the amplitude limiter is realized in a different manner. 
     FIG. 7 is an embodiment of a solenoid control circuit with two coils realized according to transistor technology. 
     FIG. 8 is the diagram of a static switch and decoder control system. 
     FIG. 9 is the diagram of a matric type control system. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     As previously mentioned, the control device of a bistable solenoid according to the invention requires the use of a generator allowing the delivery, on its control terminals S 1  and S 2 , of pulses with two levels of amplitude, i.e. a first pulse type S to control passage of the solenoid to the stable state S and a second pulse type R to control the passage of the solenoid to stable state R. These two types of pulses are illustrated on FIG. 1 on which appear: 
     a pulse I 1  of type S which presents an amplitude VS situated in the voltage zone ZS between one voltage VSm (&#34;Vset minimum&#34;) and one voltage VS M  (&#34;Vset maximum&#34;), and 
     a type R pulse I 2  which presents an amplitude VR situated in a voltage zone ZR included between one voltage VRm (&#34;VReset minimum&#34;) and one voltage VR M  (&#34;VReset maximum&#34;). 
     The zone between voltage VS M  and voltage VRm is a neutral zone ZN in which the amplitude of pulses must never be situated for, in this zone, the dicriminator may not determine for certain whether the pulse is type S or type R. 
     For example, the rated value of the amplitude of type S pulses I 1  could be equal to 12 V, the value VSm equal to 9 V and the value VS M  equal to 14 V. Likewise, the rated value of the amplitude of type R pulses I 2  could be equal to 24 V, value VRm equal to 16 V and value VR M  equal to 30 V. Zone ZS shall then have a width of 5 V, zone ZR a width of 14 V and zone ZN a width of 2 V. 
     In the example represented in FIG. 2, the bistable solenoid includes a single coil B connected to the control terminals S 1  and S 2  of the circuit by means of a switching circuit designed to reverse the direction of the current circulating in the coil B, according to the level of amplitude of the pulses applied to terminals S 1  and S 2 . 
     With this end in view, each of the extremities of the coil B is connected to terminals S 1  and S 2  of the generator by means of two controllable switches, i.e. switches CS and CR&#39; for one of the extremities of coil B and switches CR and CS&#39; as regards the other extremity. 
     These switches CS, CS&#39;, CR and CR&#39; are controlled by a discriminator type circuit including a voltage divider bridge made up of two resistances R 1  and R 2  connected in series between the two control terminals S 1  and S 2  and whose connection point is connected to the inverter terminal of a comparator A whose direct input is carried to a reference voltage VREF. 
     The output of this comparator A is connected firstly by a direct link to the control devices of switches CS and CS&#39; and secondly, by means of an inverter Io to the control devices of switches CR and CR&#39;. 
     Moreover, this circuit introduces a resistance R&#39;e connected in series with the switch CR&#39;, a resistance Re connected in series with the switch CR, an amplitude limiter E connected in parallel on the coil B and a diode D 1  connected in the link between the control terminal S1 and the unit formed by the discriminator and the switching circuit monitoring the coil B. 
     It should be noted that in this circuit, the voltage VSm, i.e. the minimum voltage of zone ZS, is determined by the minimum action voltage of the coil B provoking passage of the bistable solenoid to state S. As regards voltage VRm, this is determined by the value of the voltage VREF applied to the comparator. 
     Therefore, the functioning of this circuit can be demonstrated as follows: 
     where the pulse generator delivers on terminals S 1  and S 2  a voltage pulse VS, the voltage applied to the inverter input of the comparator will be lower than the reference voltage VREF with the result that the output of the comparator A will deliver a control signal (logic state 1) resulting in the closing of switches CS and CS&#39; and, by virtue of the inverter I, the opening of switches CR and CR&#39;. The coil B is therefore carried to a voltage VS directed initially in a first direction leading to passage of the solenoid to state S, 
     where the pulse generator delivers a voltage impulse VR, the voltage applied to the inverter input of the comparator A will be greater than or equal to the reference voltage VREF with the result that the output of this comparator A will deliver a control signal (logic state 0) leading to the opening of switches CS and CS&#39; and, by virtue of the inverter I, the closing of switches CR and CR&#39;. The coil will then be carried at a voltage VR directed in a second direction leading to passage of the solenoid to state R. 
     The resistance Re and Re&#39; used in the circuit previously described play two roles. First of all, they enable the switches to be protected in the event of overlapping in conduction CS, CR&#39; or CR, CS&#39;. Moreover, the coil B being defined to act from voltage VSm, the resistances Re and Re&#39;, which are then in series, limit the current inside the coil B when the voltage pulse VR is applied, especially when voltage VR is equel to voltage VR M . 
     Likewise, the diode D 1  used also plays two roles: it ensures protection against polarity inversion and it serves as a reverse-lock diode in the case of a matric control. 
     The control circuit represented in FIG. 3 introduces a diode D 1  and a discriminator composed of the resistances R 1  and R 2  and a comparator A connected in a way identical to that of FIG. 2. However, unlike the preceding circuit, this circuit includes two coils BS and BR shunted by two respective diodes D 2  and D 3  and connected through one of their extremities to the control terminal S 2  and through their other extremities to the diode D 1  by means of two controllable switches, respectively CS and CR. In this case, the output of the comparator A is directly connected to the control device of the switch CS and, by means of an inverter I&#39;o, to the control device of switch CR. According to this circuit, the transmission of a voltage pulse VS will provoke the closing of switch CS and the opening of switch CR with the result that only the coil BS will be fed. The solenoid will consequently pass to state S. On the other hand, the transmission of a voltage pulse VR will provoke the opening of switch CS and the closing of switch CR with the result that only coil BR will be fed. The solenoid will then pass to state R. 
     It should be noted that in this circuit, the voltage VSm is determined by the minimum action voltage of BS and the voltage VRm by the reference voltage VREF. However, the coil BR must be dimensioned so that its action makes the solenoid pass from state S to state R as regards a voltage of VBR less than or equal to VRm. 
     Preferably, the coil BR can be dimensioned in such a way as to support the voltage VRM without consuming too much current. However, in order to obtain such a current limitation, it is, if necessary, possible to arrange a resistance Re in series with the coil BR. 
     In the circuits illustrated in FIGS. 2 and 3, the rise time tm of type S and R pulses (FIG. 4) does not affect the functioning of these circuits. 
     On the other hand, the fall time td must be less than the response time of the bistable solenoid. Indeed, during the fall of the type R pulse, the voltage crosses zone ZS during a time tds. 
     It is essential that the passage of the bistable solenoid to state S is not activated during this period. 
     This result can be obtained by reducing as far as possible the fall time td and/or by increasing the response time of the bistable solenoid to a type S pulse, for example by delaying by a time constant Rc the closing of contactor CS or contactors CS and CS&#39;. 
     This problem can be resolved by providing the response times of the bistable solenoid with a type S pulse (response time t B  S) and type R pulse (response time t B  R) and by providing pulse periods tS for type S and tR for type R which meet the following conditions: 
     
         2t.sub.B S≦TS≦3t.sub.B S 
    
     
         2t.sub.B S&lt;tR≦3t.sub.B R 
    
     with 
     
         t.sub.B S≠≠T.sub.B R˜several ms 
    
     
         tS≠≠tR≃10 ms 
    
     and ##EQU1## The control circuits illustrated in FIGS. 5 and 7 concern realization examples using a minimum number of components and, because of this, they are very economical. The bipolar transistors used in these circuits can be replaced, subject to slight modifications, by MOS power transistors. The implementation of these circuits can make use of well-known connection technologies using, for example: 
     rigid or supple printed circuits, 
     thick-film hybrid circuits, 
     a specific integrated circuit of the Mos, C Mos or bipolar (CUSTOM) type. 
     The circuit illustrated in FIG. 5 applies to a solenoid with a single coil B and presents a structure similar to that of the circuit shown on FIG. 2. Consequently, this circuit similarly includes a diode D 1 , a voltage divider bridge R 1 , R 2 , four transistors TS 1 , TS&#39; 1 , TR 1 , TR&#39; 1  respectively playing the role of controllable switches CS, CS&#39;, CR, CR&#39;, resistances R 9  and R 10 , similar to resistances Re and Re&#39; which are mounted in the circuits connecting the collectors of transistors TR&#39; and TR to the two extremities of the coil B, and an amplitude limiter E connected in parallel on the coil B. 
     The transistors TS 1  and TR 1  are type PNP and their transmitters are connected to the diode D 1 , directly as regards transistor TR 1  and by means of a diode D 3&#39;   as regards transistor TS 1 . 
     Transistors TR&#39; 1  and TS&#39; 1  are type NPN and are connected by their transmitter to control terminal S 2 . The collectors of transistors TS 1  and TS&#39; 1  are respectively connected to the two extremities of coil B. 
     The base of transistor TS 1  is connected to the connection point of resistances R 1  and R 2  of the voltage divider bridge as well as to the collector of transistor TR 1  by means of a diode D&#39; 2 . 
     The base of transistor TR 1  is connected by means of a resistance R 3  to the connection point of a resistance R 4  itself connected to the diode D 1  and of a Zener (breakdown) diode DZ 1  of, for example, 15 volts and whose anode is connected to control terminal S 2 . 
     The base of transistor TR&#39; 1  is connected to the connection point of two resistances R 5  and R 6  which constitute a voltage divider bridge between the collector of transistor TS&#39; 1  and the control terminal S 2 . 
     The base of transistor TS&#39; 1  is connected to the connection point of two resistances R 7  and R 8  which constitute a voltage divider bridge between the collector of transistor TR&#39; 1  and the control terminal S 2 . A capacitor C designed to delay by a time constant conduction of the transistor TS&#39; 1  is mounted in parallel on the resistance R 8 . According to this circuit, when the pulse generator delivers a type S pulse, e.g. of 12 volts, the transistor TS 1  whose base is polarized by the bridge R 1 , R 2  becomes a conductor and then, after the loading of the capacitor C, transistor TS&#39; 1 , whose base is polarized by the circuit including diode D&#39; 3 , transistor TS 1  and resistances R 10 , R 7  and R 8  also becomes conductor. 
     Due to the conduction of transistor TS&#39; 1 , the transistor TR&#39; 1  is kept in a blocked state. The same is true for transistor TR 1  whose base is carried at a voltage close to its transmitter voltage. 
     The coil B is then crossed by a current which circulates in a first direction suitable for leading the bistable solenoid to state S. 
     On the other hand, when the pulse generator delivers a type R pulse of, for example, 24 volts, the base/transmitter potential difference of transistor TR 1  which is then about 9 volts by virtue of the Zener diode DZ 1 , is sufficient to provoke the conduction of transistor TR 1 . This conduction results in the blockage, thanks to diode D&#39; 2 , of transistor TS 1  and, by means of the circuit including resistances R 9 , R 5  and R 6 , conduction of transistor TR&#39; 1 . The coil B is then crossed by a current which circulates in a second direction suitable for leading the bistable solenoid to state R. 
     It thus appears that in this realization mode, the voltage VRm is determined by the Zener didoe DZ 1 . 
     Of course, the invention is not limited to the realization modes previously described. Thus, for example, the amplitude limiter E could be replaced, as shown on FIG. 6, by four diodes D 4 , D 5 , D 6  and D 7  mounted in antiparallel fashion on transistors TS 1 , TS&#39; 1  and TR 1 , TR&#39; 1  and a Zener diode DZ 2  connected between diode D 1  and the control terminal S 2 . 
     The circuit illustrated in FIG. 7 includes two coils BS and BR connected to the feed terminals by means of two transistors TS 2  and TR 2  respectively and a common diode D 1 . The base of transistor TS 2  is connected to its transmitter by means of a capacitor C and to the collector of transistor TR 2  by means of a resistance R 10 . The base of transistor TR 2  is connected to the connection point of a resistance R 13  connected to the collectors of transistors TS 2  and TR 2  and of a Zener diode DZ 2  connected to the control terminal S 2 . 
     In the circuit connecting the collector of transistor TR 2  to the coil B R , a resistance R 12  may also be disposed. 
     Therefore, when the pulse generator delivers a type S pulse, transistor TS 2  becomes a conductor after a slight delay time (polarization of its base by the circuit C, R 10 , BR) whilst the transistor TR 2  remains blocked due to the voltage of the pulse being less than the threshold voltage of the Zener diode DZ 2 . Only the coil BS will be crossed by a current. 
     On the other hand, when the pulse generator delivers a type R pulse, the transistor TR 2  becomes a conductor and provokes the blockage of transistor TS 2  (polarization of the base by R 13 , DZ 2  and R 11 ). Only the coil BR will then be crossed by a current. 
     As mentioned previously, the control circuits according to the invention can favorably equip bistable relays usable in conventional control circuits. 
     FIG. 8 shows an example of the realization of a decoder and static switch control circuit which includes a plurality of active bistable relays RBA 1 , RBA 2  . . . RBA n . These relays each use a control circuit not represented as those previously described which each present two control terminals. 
     The terminals S1 of these relays are connected to a type S and R pulse generator which includes, in conventional fashion, a switch CC connected to two voltage sources, one to a voltage of V+12 volts as regards type S pulses and the other of V+24 volts for type R pulses, and controlled by an inverter circuit I 3  receiving a two level logic signal, i.e. a type S logic signal (for example of level 1) and a type R logic signal (for example of level 0). 
     The terminals S 2  of relays RBA . . . RBA n  are connected to a reference voltage source V o , for example the earth (ground), by means of respective transistors T 1 , T 2  . . . T n , the bases of which are monitored by a decoder DEC. This decoder DEC includes a logic input, e.g. with four terminals e 1 , e 2 , e 3 , e 4  and a validation input ev and which enables in particular the period to be defined for pulses applied to the bistable relays RBA 1 , RBA 2  . . . RBA n . 
     Thus, for a defined logic combination applied to inputs e 1 , e 2 , e 3  and e 4  of the decoder DEC and during the pulse validation period, a corresponding bistable relay RBA will be subjected to a pulse, the type of which will be defined by the logic level applied to the switch CC. 
     FIG. 9 illustrates an example of the application of the invention to the realization of a matric control system. 
     This system includes, in a conventional way, a meshed conductor network with n lines and m columns at the intersections of which are connected, in a conventional way, the active bistable relays: ##EQU2## Each of the lines of this network is connected, by means of a switch L 1 , L 2  . . . L n-1 , L n , to a type S and R pulse generator which conventionally includes a switch CC connected to two voltage sources, one at V+12 volts for type S pulses and the other of V+24 volts for type R pulses. This switch is controlled by an inverter I 4  receiving a two level logic signal, i.e. a type S logic signal (e.g. of level 1) and a type R logic signal (e.g. of level 0). 
     Moreover, the columns of this network are connected to the reference voltage V o , for example OV, by means of switches C 1 , C 2  . . . C m-1 , C m . 
     The line switches L 1 , L 2  . . . L n-1 , L N  are monitored by a line decoder DECI which includes as many outputs L&#39; 1 , L&#39; 2  . . . L&#39; n  as there are switches L 1 , L 2  . . . L n . 
     In the same way, the column switches C 1 , C 2  . . . C n  are monitored by a column decoder DECC which includes as many outputs C&#39; 1 , C&#39; 2  . . . C&#39; n  as there are switches C 1 , C 2  . . . C n . 
     These lines decoders DECL and column decoders DECC respectively receive on their inputs line and column addressing logic signals. 
     Moreover, the column decoder DECC includes a validation input ev which enables the type S and type R pulse time applied to the bistable relays RBA to be defined. 
     Consequently, for a given line address applied to the line decoder and for a given column address applied to the address decoder and during the period of the validation signal, a bistable relay of the network will be activated according to the state of the switch CC by a type S or type R signal. 
     It should be noted that in this type of application, reverse-lock diodes D 1  must be provided in each bistable relay RBA. 
     The advantage of the system previously described lies in the fact that it can introduce a large number of on/off relays. It is therefore particularly suitable in the field of industrial process automation.