Abstract:
A memory cell having a low storage node resistance and a method of manufacturing the same are provided. A trench type memory cell, in addition to storage node polysilicon, has other conductive material embedded in the storage node. Conductive material may be one of WSi, TiSi, W, Ti, and TiN. The additional conductive material provides a low storage node resistance which facilitates the realization of 256 Mbit memory cells and beyond.

Description:
FIELD OF INVENTION 
     The invention generally relates to a trench for a semiconductor device and, more particularly, to a trench fill structure in which conductive material (other than polysilicon) is embedded in the trench to decrease the resistance of the trench fill. 
     BACKGROUND OF INVENTION 
     Very large scale integration semiconductor technologies have substantially increased the circuit density on a chip. Miniaturization of devices built in and on semiconductor substrates has led to ultra large scale integration with minimum device dimensions less than a micrometer and more than a million transistors on a chip. With the improved integration, circuit elements such as memory cells experience electrical limitations resulting from their downsizing. 
     It is desirable to increase the integration density of memory cells on a memory chip by making the MOS transfer transistor and the storage capacitor which comprise a memory cell smaller. This has been particularly desirable with dynamic random access memory (DRAM) storage cells. However, the storage capacitor must be large enough to store sufficient charge for ensuring that data is correctly read from and written to the memory cell. Trench capacitors have been developed to increase the capacitance of the storage capacitor while permitting the integration density of memory cells to be increased. 
     FIGS 1A and 1B show a memory cell described in Nesbit et al., A 0.6 μm 2  256 Mb Trench DRAM Cell With Self-Aligned BuriEd STrap (BEST), IEDM 93-627-630, the contents of which are incorporated herein. Specifically, FIG. 1A illustrates a top-down view of a DRAM cell having a self-aligned buried strap and FIG. 1B is a cross-sectional view taken along I-I&#39; of FIG. 1A. DRAM cell 50 includes a trench capacitor 55 and a transfer gate 60. Trench capacitor 55 includes a first N +  polysilicon fill 65, a second N +   polysilicon fill 67, and a collar oxide 71. Transfer gate 60 includes N-type source/drain regions 73 and 74 formed in a P-well 75 and a polysilicon gate 77 insulatively spaced from the channel between source/drain regions 73 and 74. A bit line contact 79 electrically connects source/drain region 73 to bit line 81. A shallow trench isolation (STI) arrangement 80 electrically isolates DRAM cell 50 from an adjacent memory cell and passing word line 92. A diffusion region 83 is formed to electrically connect third polysilicon fill 69 and source/drain region 74 of MOS transfer gate 60 by outdiffusing dopants from highly doped polysilicon fill in the storage trench into the P-well 75. Diffusion region 83 and third polysilicon fill 69 constitute a buried strap for connecting trench capacitor 55 to transfer gate 60. 
     One of the problems is that the resistance of the storage node (Rsn) poly becomes a much greater factor as technological advances are made to accommodate 256 Mbit, 1 GBit and larger DRAM cells. Consequently, with the shrinking design groundrule of high capacity DRAMs, the signal delay (tsd) in the sensing operation performed by a sense amplifier coupled to the bit line associated with a memory cell becomes increasingly large, thereby increasing memory cell access time to undesirable levels. For example, in a simulation of sensing delay versus storage node resistance for a 256 Mbit trench DRAM with a self-aligned BuriEd STrap (BEST) structure, it was found that the storage node resistance Rsn was 60 kOhms and the sensing signal delay tsn was 5.5 nanoseconds (ns). In the simulation for a 1 Gbit DRAM, the storage node resistance Rsn was 130 kOhms and the sensing signal delay tsn was 10 ns. The simulation was performed using both a lumped RC model and a distributed RC model, respectively shown in FIGS. 2A and 2B, with the following relations: Vto (transfer gate voltage)=0.75 volts@ Vpwell=0 volts; WL Vpp=3.5 volts; BL Vblh=1.8 volts; and &#34;1&#34; is data read. Using SPICE (circuit simulator) with the distributed and lumped RC models, the sensing delay (i.e., the delay time from the transfer gate being turned on to 90% signal output at the sense amplifier) was simulated. The results of the simulation are graphically represented in FIG. 2C which shows sensing delay vs. storage node resistance. The DRAM storage node resistance substantially increases between a 256 Mbit DRAM and a 1 Gbit DRAM. For a 1 Gbit DRAM, the diameter of the trench decreases as the design rule (feature size) decreases. However, the depth of the trench does not decrease so that a reasonable amount of storage capacitance (Cs) can be maintained. Thus, the deep trench polysilicon becomes much narrower, resulting in a storage node resistance substantially higher than the 256 Mbit DRAM. 
     SUMMARY OF THE INVENTION 
     The present invention overcomes the aforementioned disadvantages by providing a trench type DRAM cell having additional conductive material embedded in the storage node to suppress resistance. This is particularly useful for trench type DRAM cells of 256 Mbit and beyond to suppress storage node resistance. 
     A method of forming a coupled capacitor and transistor according to an illustrative embodiment of the present invention includes the steps of forming a trench in a semiconductor substrate, forming a first conductive region by filling the trench with at least first and second conductive materials, the first conductive material being a first impurity-doped conductive material and the second conductive material being a material other than polysilicon, etching back the first conductive region to a first level within the trench, forming an insulating layer on a sidewall of the portion of the trench opened by the etching back of the first conductive region, forming a second conductive region by filling the remainder of the trench with the first conductive material, and etching back the insulating layer and the second conductive region to a second level within the trench. The method further includes the steps of forming a third conductive region in the portion of the trench opened by the etching back of the insulating layer and the second conductive region, etching back the third conductive region to a third level within the trench, outdiffusing impurities from at least one of the conductive regions to the semiconductor substrate, and forming a source/drain region of the transistor adjacent to an intersection of the trench and the surface of the semiconductor substrate, the outdiffused impurities comprising a buried strap for electrically connecting the first and second conductive materials in the trench to the source/drain region. 
     An illustrative memory cell structure according to the present invention includes a semiconductor substrate, a trench formed in the semiconductor substrate, a first trench fill including a first conductive region of at least first and second conductive materials, the first conductive material being a first impurity-doped conductive material and the second conductive material being a material other than polysilicon, an insulating layer formed on a sidewall of the portion of the trench above the first trench fill, a second trench fill formed on the first conductive region and including a second conductive region, a third trench fill formed on the second conductive region and the insulating layer and including a third conductive region, a transistor having a source/drain region adjacent to an intersection of the trench and the surface of the semiconductor substrate, and a buried strap, formed by outdiffusing impurities from at least one of the conductive regions to the semiconductor substrate, for electrically connecting the first and second conductive materials in the trench to the source/drain region. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will now be described in more detail with reference to preferred embodiments of the invention, given only by way of example, and illustrated in the accompanying drawings in which: 
     FIGS. 1A and 1B are top-down and cross-sectional views, respectively, of a DRAM cell with a self-aligned buried strap. 
     FIGS. 2A and 2B show the models used to perform a simulated test using the conventional semiconductor structure. 
     FIG. 2C is a graphical representation of signal delays versus storage node resistance for a simulated test using the conventional semiconductor structure. 
     FIGS. 3A-3J illustrate a manufacturing method according to a first embodiment of the present invention. 
     FIGS. 4A-4C illustrate a manufacturing method according to a second embodiment of the present invention. 
     FIGS. 5A-5C illustrate a manufacturing method according to a third embodiment of the present invention. 
     FIGS. 6A and 6B illustrate a manufacturing method according to a fourth embodiment of the present invention. 
     FIG. 7 is an illustration of a resulting structure according to a fifth embodiment of the present invention. 
     FIG. 8 is an illustration of a resulting structure according to a sixth embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     The present invention is discussed below with reference to a trench type DRAM cell. However, the present invention generally may be applied to fills for any type of memory cell or semiconductor device. For example, the present invention may be applied to other structures and applications including, but not limited to, a poly stud for a bit line contact in a memory cell array. 
     FIGS. 3A-3J illustrate a method in accordance with a first embodiment of the present invention. FIG. 3A shows a substrate 100 having a buried N-well 101. As shown in FIG. 3B, a silicon nitride layer 102 of about 0.2 micrometers (μm) is formed by chemical vapor deposition, for example, on the surface of a thin oxide layer 104 (e.g., about 10 nanometers) which is thermally grown on semiconductor substrate 100. An oxide layer 106 is formed by PECVD (plasma enhanced chemical vapor deposition) on the SiN layer 102. The oxide layer 106 serves as a pad oxide and suppresses erosion of the SiN layer 102 which can occur during a DT (deep trench) RIE etch. 
     Oxide layer 104, silicon nitride layer 102, and oxide layer 106 are patterned and etched to provide a mask for etching a trench 103. Trench 103 is etched using an anisotropic etching process to a depth of about 8 micrometers as shown in FIG. 3B. After storage node trench 103 is etched, an oxidized nitride (ON) storage node dielectric (not shown) is formed in trench 103. After the dielectric is formed, trench 103 is filled by a first conductive region of a stacked-layer structure which includes a first layer 105 of an impurity-doped first conductive material (such as thin N +  -type polycrystalline silicon), a second layer 107 of a second conductive material other than polysilicon such as WSi, TiSi, W, Ti, or TiN, and a third layer 109 of an impurity-doped third conductive material (such as N +  -type polycrystalline silicon) as shown in FIG. 3C. The first conductive region is then etched back to a first level within trench 103 using an anisotropic etch process to form a first trench fill as shown in FIG. 3D. During the etch back or recess etch, the oxide layer 106 is also removed. The level of first trench fill is about 1.0 micrometer (μm) below the surface of semiconductor substrate 100. A collar oxide 111 is then formed on the sidewall of the portion of trench 103 opened by etching back the first conductive region using LPCVD or PECVD TEOS as shown in FIG. 3E. 
     A second conductive region is formed by filling in the remainder of trench 103 with a conductive material 113 as shown in FIG. 3F. The conductive material 113 may be, for example, N +  -type polycrystalline silicon or undoped polycrystalline silicon and may be formed by chemical vapor deposition. Thereafter, the oxide collar 111 and the conductive material 113 are etched as shown in FIG. 3G. 
     The portion of trench 103 opened by the etching back of oxide collar 111 and the conductive material 113 is then filled by depositing polysilicon 119 using chemical vapor deposition, for example. The polysilicon 119 is then etched back using reactive ion etching, for example, to form a third trench fill as shown in FIG. 3H. The polysilicon 119 is preferably etched back to about 0.05 micrometer (μm) below the surface of semiconductor substrate 100 as determined by tolerable resistance of the buried strap (e.g., less than 10 kOhm) which is much less than the storage node resistance, and the recess etch controllability. At this juncture, the polysilicon 119 forms a strap along the entire perimeter of the trench 103. 
     Next, the structure in FIG. 3H undergoes a shallow trench isolation process. With reference to FIG. 3I, a reactive ion etch is performed to provide shallow trench 123 for shallow trench isolation. In general, shallow trench isolation is used to isolate discrete memory cell devices to prevent interference therebetween. Accordingly, a shallow trench such as shallow trench 123 is formed between adjacent deep trench configurations to ensure that they operate independently. 
     Shallow trench 123 is then filled in to ensure isolation from adjacent trench structures. For example, with reference to FIG. 3J, an oxide lining 125 may be formed over the layer 119 and the interior surface of shallow trench 123 by, for example, thermal oxidation. A nitride lining 127 may then be formed over oxide lining 125 by, for example, CVD. The oxide and nitride linings 125, 127 serve to isolate collar oxide 111 from oxidant, and thereby suppress dislocation and stress. Finally, shallow trench 123 may be filled according to techniques known in the art. For example, an oxide 129 may be deposited to fill in shallow trench 123. 
     Other shallow trench isolation techniques may be used such as the technique described in U.S. application Ser. No. 08/351,161 entitled &#34;Shallow Trench Isolation with Deep Trench Cap&#34;, which is incorporated herein by reference thereto. 
     During the complete DRAM fabrication process, impurities from one or a combination of the conductive regions within the trench are outdiffused to form strap portion 131, e.g., an n +  buried strap. A gate insulator may then be formed on the planar surface, and gate material may be deposited and patterned to form gate electrodes. Using the gate electrodes as masks, source/drain regions may be formed by ion implantation. Accordingly, transfer gates coupled to trench capacitors are realized. Interconnections between devices and metallization to the output terminals are formed using techniques known in the art. Then, the bit line process and back end of line process follow. According to this embodiment, the resistance of the first trench fill is decreased. For example in a 256 Mbit DRAM, the total depth of the trench is 8 μm and the depth of the second fill 113 is only about 1 μm. The second conductive material enhances the conductance of the storage node throughout a substantial portion of the other 7 μm depth of the trench. As a result, the aforedescribed structure substantially reduces the storage node resistance. Assuming a buried strap resistance of 10 kOhm, using the above embodiment, the storage node resistance and sensing delay respectively decrease from 60 kOhm to 16 kOhm and from 5.5 ns to 4 ns for a 256 Mbit DRAM, and from 130 kOhm to 25 kOhm and 10 ns to 6 ns for a 1 Gbit DRAM. 
     FIGS. 4A-4C illustrate a method in accordance with a second embodiment of the present invention. 
     According to the second embodiment, the steps to realize the structure in FIG. 3E are carried out. Next, trench 103 is filled by a second conductive region of a stacked-layer structure which includes a first layer 140 of an impurity-doped first conductive material (such as thin N +  -type polycrystalline silicon), a second layer 142 of a second conductive material such as WSi, TiSi, W, Ti, or TiN, and a third layer 144 of an impurity-doped third conductive material (such as N +  -type polycrystalline silicon) as shown in FIG. 4A. The non-polysilicon conductive material in the first conductive region can be different from the non-polysilicon conductive material in the second conductive region. 
     The second conductive region and the oxide collar 111 are then etched back to a second level within trench 103 to form a second trench fill insulated from the semiconductor substrate by oxide collar 111 similar to that shown in FIG. 3G. The depth of the buried strap to be formed in a subsequent process step is defined by this controlled etch-back of the conductive region and oxide collar 111. The second trench fill is etched back to about 0.1 μm below the surface of semiconductor substrate 100. 
     The portion of trench 103 opened by the etching back of oxide collar 111 and the conductive region is then filled by depositing polysilicon 119 using chemical vapor deposition, for example. The polysilicon 119 is then etched back using reactive ion etching, for example, to form a third trench fill as shown in FIG. 4B. The polysilicon 119 is preferably etched back to about 0.05 micrometer (μm) below the surface of semiconductor substrate 100 as determined by the tolerable resistance of the buried strap, and by the recess etch controllability. At this juncture, the polysilicon 119 forms a strap along the entire perimeter of the trench 103. 
     The process described above with respect to shallow trench isolation described above is performed on the structure shown in FIG. 4B and the resulting structure is shown in FIG. 4C. This embodiment decreases the resistance of both the first and second trench fills. Thus, the second embodiment can reduce the storage resistance more than the first embodiment. For example, if the buried strap resistance is 10 kOhm, for a 256 Mbit DRAM, the storage node resistance is reduced from 60 kOhm to 11 kOhm and the sensing delay is reduced from 5.5 ns to 3.5 ns. For a 1 Gbit DRAM, the storage node resistance is reduced from 130 kOhm to 12 kOhm and the sensing delay is reduced from 10 ns to 3.5 ns. 
     FIGS. 5A-5C illustrate a method in accordance with a third embodiment of the present invention. 
     According to the third embodiment, the steps to realize the structure in FIG. 3E are carried out. Next, trench 103 is filled by a second conductive region of a stacked-layer structure which includes a first layer 150 of a first conductive material (preferably WSi, but may be one of TiSi, W, Ti and TiN), and a second layer 152 of an impurity-doped second conductive material (such as N +  -type polycrystalline silicon) as shown in FIG. 5A. 
     The second conductive region and the oxide collar 111 are then etched back to a second level within trench 103 to form a second trench fill insulated from the semiconductor substrate by oxide collar 111 similar to that shown in FIGS. 3G and 4B. The depth of the buried strap to be formed in a subsequent process step is defined by this controlled etch-back of the conductive region and oxide collar 111. The second trench fill is etched back to about 0.1 micrometer (μm) below the surface of semiconductor substrate 100. 
     The portion of trench 103 opened by the etching back of oxide collar 111 and the second conductive region is then filled by depositing a third conductive region of a stacked-layer structure which includes a first layer 154 of a first conductive material (preferably TiSi, but may be one of WSi, W, Ti, and TiN), and a second layer 156 of a conductive material such as polysilicon as shown in FIG. 5B. The third conductive region is then etched back using reactive ion etching, for example, to form a third trench fill as shown in FIG. 5B. The third conductive region is preferably etched back to about 0.05 micrometer (μm) below the surface of semiconductor substrate 100 as determined by the tolerable resistance of the buried strap, and by the recess etch controllability. At this juncture, the third conductive region forms a strap connection along the entire perimeter of the trench 103. 
     The process described above with respect to shallow trench isolation described above is performed on the structure shown in FIG. 5B and the resulting structure is shown in FIG. 5C. In addition to decreasing the resistance of the first and second trench fills, the third embodiment also decreases the resistance of the third trench fill and the buried strap. Thus, this embodiment reduces the storage node resistance more than the first and second embodiments. For example, if the buried strap resistance is 200 kOhm, for a 256 Mbit DRAM, the storage node resistance is reduced from 60 kOhm to 1 kOhm and the sensing delay is reduced from 5.5 ns to 3 ns. For a 1 Gbit DRAM, the storage node resistance is reduced from 130 kOhm to 2 kOhm and the sensing delay is reduced from 10 ns to 3 ns. 
     FIGS. 6A and 6B illustrate a method in accordance with a fourth embodiment of the present invention. 
     According to the fourth embodiment, the steps to realize the structure in FIG. 3B are carried out. Next, trench 103 is filled by a first conductive region of a stacked-layer structure which includes a first layer 105 of an impurity-doped first conductive material (such as N +  -type polycrystalline silicon) and a second layer 108 of a second conductive material (preferably WSi, but may be one of TiSi, W, Ti and TiN). The first conductive region is then etched back to a first level within trench 103 using an anisotropic etch process to form a first trench fill as shown in FIG. 6A. Next, the steps described above and shown in FIGS. 3E-3J are carried out on the structure shown in FIG. 6A resulting in the structure shown in FIG. 6B. 
     FIG. 7 illustrates the structure realized according to a fifth embodiment where a conductive material (preferably W, but may be one of TiSi, Ti, TiN, and WSi) is used in the storage node of an SOI (silicon-on-insulator) trench-type DRAM cell. A similar memory structure can be found in Japanese Patent Publication No. 6104398, to Hieda published Apr. 15, 1994 and entitled &#34;Semiconductor Storage Device and Manufacture Thereof. In FIG. 7, the structure shown includes trenches with a conductive region of a stacked-layer structure which includes a first layer 170 of an impurity-doped first conductive material (such as N +  -type polycrystalline silicon) and a second layer 172 of a second conductive material (preferably W, but may be one of TiSi, W, Ti and TiN). Also shown in the SOI trench-type DRAM cell structure is an oxide 174, preferably SiO 2 , and gate conductors GC. This structure can be realized by manufacturing process steps including filling the trenches with the conductive regions, etching the conductive regions back and forming the remainder of SOI structure as known in the art. 
     FIG. 8 illustrates the structure realized according to a sixth embodiment where a conductive material (preferably W, but may be one of TiSi, Ti, TiN, and WSi) is used in the storage node of a wafer bonding SOI trench-type DRAM cell. In FIG. 8, the structure shown includes trenches with a conductive region of a stacked-layer structure which includes a first layer 180 of an impurity-doped first conductive material (such as N +  -type polycrystalline silicon) and a second layer 182 of a second conductive material (preferably W, but may be one of TiSi, W, Ti and TiN). Also shown in the wafer bonding SOI trench-type DRAM cell structure is an oxide 184, preferably SiO 2 , and gate conductors GC. This structure can be realized by manufacturing process steps including fill the trenches with the conductive regions, etching the conductive regions back and forming the remainder of wafer bonding SOI structure as known in the art. 
     While particular embodiments of the present invention have been described and illustrated, it should be understood that the invention is not limited thereto since modifications may be made by persons skilled in the art. The present application contemplates any and all modifications that fall within the spirit and scope of the underlying invention disclosed and to claimed herein.