Abstract:
A server computer includes an SDRAM and a service processor that transmits a boot firmware program. The server computer further also includes a CPU that includes a cache for the boot firmware program transmitted from the service processor to be stored in. The CPU executes the boot firmware program stored in the cache to activate the SDRAM, and performs a startup of the server computer by using the activated SDRAM.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2014-070339, filed on Mar. 28, 2014, the entire contents of which are incorporated herein by reference. 
       FIELD 
       [0002]    The embodiment discussed herein is related to an information processing apparatus, a method for controlling the information processing apparatus, and a control program of the information processing apparatus. 
       BACKGROUND 
       [0003]    Recent information processing apparatuses such as a server computer often include a service processor. The service processor is an independent computer for performing remote control and management of operations of the entire information processing apparatus including a CPU (Central Processing Unit) serving as a processor. For example, the service processor performs emergency control when the server computer is in trouble, and performs starting/stopping at normal time. 
         [0004]    A conventional information processing apparatus including a service processor will be described with reference to  FIG. 9 .  FIG. 9  is a diagram illustrating an example of a conventional server computer including a service processor. For example, a server computer  900  includes a CPU  902  and a service processor  901 , which are connected by a reset signal line  905 . The CPU  902  is further connected to an SDRAM (Synchronous Dynamic Random Access Memory)  903  which is a volatile main storage device. The CPU  902  is connected with a boot ROM (Read Only Memory)  904  by a bus  906 . The SDRAM  903  is an SDRAM group including a plurality of SDRAMs. The boot ROM  904  contains a boot firmware program. 
         [0005]    The CPU  902  includes one or more cores  921  to be recognized as a single processor by a program, and a cache  922  for the SDRAM  903 . The CPU  902  is connected to an IO (Input Output) controller  907  and a network interface controller  909  by a bus. The IO controller  907  is connected with an external storage device  908  such as a hard disk. 
         [0006]    The server computer  900  performs a system reset and boot, for example, by the following procedure. The service processor  901  inputs a reset signal to the CPU  902  via the reset signal line  905 . Specifically, the service processor  901  inputs 0 to the CPU  902  other than when inputting the reset signal. When inputting the reset signal, the service processor  901  changes the value input to the CPU  902  to 1. The service processor  901  then restores the value input to the CPU  902  to 0 to cancel the reset signal, and inputs an execution instruction to reset the CPU  902  to the CPU  902 . 
         [0007]    All the core(s)  921  included in the CPU  902  receive(s) the input of the reset execution instruction from the service processor  901 . All the core(s)  921  start(s) an instruction fetch from a fixed address in the boot ROM  904 , to which fixed physical address are assigned, and an execution instruction for startup processing. The fixed address is also referred to as a reset address. 
         [0008]    Here, the cache  922  built in the CPU  902  operates as an SDRAM device that is accessed in a non-cacheable manner and to which fixed physical addresses are assigned. 
         [0009]    A boot firmware program  941  serving as a program for booting the server computer  900  is stored in the reset address in the boot ROM  904 . When the reset signal is cancelled, the CPU  902  executes the boot firmware program  941  stored in the boot ROM  904 . 
         [0010]    The CPU  902  executes the boot firmware program  941  to perform the following processing. Initially, a POST (Power On Self-Test) is performed to do an operation test inside the CPU  902 . Next, if serious failures are not detected by the POST and operations can be continued, the SDRAM  903  is initialized and refreshing of the SDRAM  903  is started. The SDRAM  903  hereafter retains written data and operates as a main storage device. Next, the boot firmware program  941  is copied to the SDRAM  903 . A data area to be used by the boot firmware program in the SDRAM  903  is initialized. The operation mode of the server computer is then changed to a mode where the cache  922  included in the CPU  902  operates as a cache of the SDRAM  903 . All the core(s)  921  included in the CPU  902  execute(s) the boot firmware program stored in the SDRAM  903 . The SDRAM  903  is hereafter used as a storage area of the boot firmware program and a storage area of data at boot time. The hardware other than the service processor  901 , the CPU  902 , the SDRAM  903 , or the boot ROM  904  is then initialized. The CPU  902  reads an OS (Operating System) boot loader for I/O (Input/Output) devices, and starts to execute the read OS boot loader. 
         [0011]    As a method for booting a computer, there is a conventional technique in which a baseboard management controller loads firmware from a memory, stores the firmware into a cache memory, and performs a boot. There is a conventional technique in which a CPU reads and stores a boot firmware program into a cache memory, and performs a boot. There is a conventional technique in which a processor for diagnosing a server computer copies a boot firmware program to a main memory device and performs a boot. 
         [0012]    Patent Document 1: Japanese National Publication of International Patent Application No. 2006-515940 
         [0013]    Patent Document 2: Japanese Laid-open Patent Publication No. 2008-16020 
         [0014]    Patent Document 3: Japanese Laid-open Patent Publication No. 2009-217336 
         [0015]    However, the conventional information processing apparatuses are provided with the boot ROM in which the boot firmware program used for booting is stored. This increases the product cost. 
         [0016]    Even with the conventional techniques of reading the boot firmware program into a cache memory or a main storage device, the provision of the boot ROM or other storage devices containing the boot firmware program makes it difficult to reduce the product cost. 
       SUMMARY 
       [0017]    According to an aspect of an embodiment, an information processing apparatus includes a main storage unit; a program transmission unit that transmits a starting program; and a processor that includes a built-in storage unit for the starting program transmitted from the program transmission unit to be stored in, executes the starting program stored in the built-in storage unit to activate the main storage unit, and performs a startup of the information processing apparatus by using the activated main storage unit. 
         [0018]    The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
         [0019]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0020]      FIG. 1  is a schematic diagram illustrating a hardware configuration of a server computer according to an embodiment. 
           [0021]      FIG. 2  is a first diagram for explaining an operation at boot time of the server computer according to the embodiment. 
           [0022]      FIG. 3  is a second diagram for explaining the operation at boot time of the server computer according to the embodiment. 
           [0023]      FIG. 4  is a third diagram for explaining the operation at boot time of the server computer according to the embodiment. 
           [0024]      FIG. 5  is a fourth diagram for explaining the operation at boot time of the server computer according to the embodiment. 
           [0025]      FIG. 6  is a fifth diagram for explaining the operation at boot time of the server computer according to the embodiment. 
           [0026]      FIG. 7  is a sixth diagram for explaining the operation at boot time of the server computer according to the embodiment. 
           [0027]      FIG. 8  is a flow chart of boot processing of the server computer according to the embodiment. 
           [0028]      FIG. 9  is a diagram illustrating an example of a conventional server computer including a service processor. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0029]    Preferred embodiments of the present invention will be explained with reference to accompanying drawings. Note that the information processing apparatus, the method for controlling the information processing apparatus, and the control program of the information processing apparatus disclosed in the present application are not limited to the embodiments described below. 
         [0030]      FIG. 1  is a schematic diagram illustrating a hardware configuration of a server computer according to the embodiment. A server computer  1  serving as an information processing apparatus includes a service processor  11 , a CPU  12  serving as a processor, and an SDRAM  13  serving as a main storage device. The server computer  1  further includes a network interface controller  14 , an IO controller  15 , an external storage device  16 , and a network interface controller  17 . 
         [0031]    The network interface controller  14  is an interface for connecting to a network  2 . 
         [0032]    The service processor  11  is connected with the CPU  12  by a reset signal line  21 . The service processor  11  is also connected with cores  121  of the CPU  12  with an instruction fetch stop signal line  22 . The service processor  11  is further connected with a cache  122  built in the CPU  12  by a CPU-SVP (Service Processor) data bus  23 . 
         [0033]    The service processor  11  is connected to the network interface controller  14 . 
         [0034]    The service processor  11  is supplied with power even when the server computer  1  is powered off. In contrast, the hardware of the server computer  1  other than the service processor  11  is supplied with power after power-on. 
         [0035]    The service processor  11  outputs a reset signal having a value of 0 to the CPU  12  via the reset signal line  21  until a boot is performed. The service processor  11  also outputs an instruction fetch stop signal having a value of 0 to the cores  121  of the CPU  12  via the instruction fetch stop signal line  22  until a boot is performed. 
         [0036]    The service processor  11  receives a boot instruction to the server computer  1  from an external apparatus via the network  2 . In the present embodiment, the case where the service processor  11  receives the boot instruction from outside is described as an example of the case where a boot is performed. However, this is not restrictive. The processing described in the present embodiment is performed at any timing when the server computer  1  is booted. For example, a boot at power-on or under a restart instruction is also applicable. 
         [0037]    When receiving the boot instruction to the server computer  1 , the service processor  11  changes the value of the reset signal output to the CPU  12  via the reset signal line  21  to 1. This puts the CPU  12  on standby for the execution of a reset. The service processor  11  also changes the value of the instruction fetch stop signal output to the cores  121  via the instruction fetch stop signal line  22  to 1. This puts the cores  121  into a state in which an instruction fetch and instruction execution are stopped. 
         [0038]    Next, the service processor  11  changes the value of the reset signal output to the CPU  12  via the reset signal line  21  to 0, whereby the CPU  12  is made to perform a reset. 
         [0039]    Next, the service processor  11  obtains a boot firmware program from the network  2 . Specifically, the service processor  11  obtains the boot firmware program from another server computer or the like located on the network  2 . While in the present embodiment the service processor  11  obtains the boot firmware program from the network  2 , this is not restrictive. For example, the service processor  11  may store the boot firmware program in advance. The boot firmware program corresponds to an example of the “starting program.” 
         [0040]    The service processor  11  then transmits and stores the boot firmware program into the cache  122  built in the CPU  12  via the CPU-SVP data bus  23 . 
         [0041]    Next, the service processor  11  changes the instruction fetch stop signal output to the cores  121  via the instruction fetch stop signal line  22  to 0. As a result, the cores  121  start an instruction fetch and instruction execution. The service processor  11  corresponds to an example of the “program transmission unit.” 
         [0042]    The SDRAM  13  is an SDRAM group including a plurality of SDRAMs which are volatile main storage devices. After the SDRAM  13  is initialized and starts being refreshed by the cores  121 , the SDRAM  13  retains written data and operates as a main storage device. 
         [0043]    The CPU  12  includes the plurality of cores  121  and the cache  122 . Each core  121  and the cache  122  are connected by an internal bus. The cache  122  is connected to the SDRAM  13 . Note that such a connection is just an example. For example, the cores  121  and the SDRAM  13  may be directly connected. The cache  122  corresponds to an example of the “built-in storage unit.” 
         [0044]    The CPU  12  is further connected to the IO controller  15  and the network interface controller  17  via a bus  24 . 
         [0045]    If the value of the reset signal input from the service processor  11  changes from 1 to 0, the CPU  12  resets the entire CPU  12 . Specifically, the CPU  12  instructs the cores  121  to make their program counters (PCs) point at a reset address. The reset address is a fixed address of the cache  122  operating as an SDRAM. The CPU  12  also instructs the cache  122  to operate as an SDRAM that has a fixed reset address and is accessed in a non-cacheable manner. 
         [0046]    The cores  121  include an instruction register  123  and a PC register  124  each. The cores  121  receive the input of the instruction fetch stop signal having a value of 1 from the service processor  11  via the instruction fetch stop signal line  22 . While receiving the instruction fetch stop signal having a value of 1, the cores  121  continue stopping an instruction fetch and instruction execution. 
         [0047]    The cores  121  receive an instruction from the CPU  12  to make their PCs point at the reset address of the cache  122 . The cores  121  then set the PCs retained in the PC registers  124  to point at the reset address of the cache  122 . 
         [0048]    The cores  121  then receive the input of the instruction fetch stop signal having a value of 0 from the service processor  11  via the instruction fetch stop signal line  22 . In other words, the value of the instruction fetch stop signal input to the cores  121  changes from 1 to 0. If the value of the instruction fetch stop signal changes from 1 to 0, the cores  121  perform an instruction fetch from the boot firmware program stored in the reset address of the cache  122  pointed by the PC registers  124 , and store instruction code into the instruction registers  123 . The cores  121  then execute the instruction code stored in the instruction registers  123 . 
         [0049]    The cores  121  execute the instruction code obtained from the boot firmware program to perform the following processing. Initially, the cores  121  perform a POST to do an operation test inside the CPU  12 . If serious failures are not detected by the POST and operations can be continued, the cores  121  initialize the SDRAM  13 . The cores  121  then start refreshing the SDRAM  13 . The SDRAM  13  hereafter retains written data and operates as a main storage device. 
         [0050]    After the SDRAM  13  starts to operate as a main storage device, the cores  121  execute the instruction code obtained from the boot firmware program to perform the following processing. The cores  121  copy the boot firmware program stored in the cache  122  to the SDRAM  13 . The cores  121  further initialize a data area on the SDRAM  13  to be used for the execution of the boot firmware program. The cores  121  further change the cache  122  into a mode in which the cache  122  operates as a cache of the SDRAM  13 . 
         [0051]    Next, the cores  121  make a change to execute the following boot processing by using the boot firmware program stored in the SDRAM  13 . Such processing may be referred to as that the cores  121  are made to jump to the boot firmware program on the SDRAM  13 . This processing is also implemented by the cores  121  executing the instruction code obtained from the boot firmware program. Consequently, the cores  121  hereafter operate by using the SDRAM  13  both as a program storage area and as a data storage area when executing the boot firmware program. 
         [0052]    The cores  121  then execute the boot firmware program on the SDRAM  13  to perform the following processing. The cores  121  initialize the hardware of the server computer  1  other than the service processor  11 , the CPU  12 , or the SDRAM  13  (for example, the IO controller  15 , the external storage device  16 , and the network interface controller  17 ). The cores  121  then read an OS boot loader, for example, from the external storage device  16 . The cores  121  further execute the read OS boot loader. In the present embodiment, the cores  121  read the OS boot loader from the external storage device  16 , whereas the location to read an OS from is not limited thereto. For example, the cores  121  may read an OS from a network  3 . The foregoing processing is performed by each individual core  121 . 
         [0053]    The IO controller  15  controls reading and writing of data from/to the external storage device  16 . The external storage device  16  is an auxiliary storage device such as a hard disk. The network interface controller  17  is an interface for connecting to the network  3 . 
         [0054]    Next, a flow of processing of the server computer  1  at boot time and the move of the boot firmware program will be collectively described with reference to  FIGS. 2 to 7 .  FIGS. 2 to 7  are first to sixth diagrams for describing the operation at boot time of the server computer according to the embodiment, respectively. 
         [0055]    As illustrated in  FIG. 2 , the service processor  11  obtains a boot firmware program  101  on the network  2  (step S 1 ). In  FIG. 2 , in step S 1 , the boot firmware program obtained by the service processor  11  is illustrated as a boot firmware program  102 . 
         [0056]    Next, as illustrated in  FIG. 3 , the service processor  11  outputs 1 as the reset signal to the CPU  12  via the reset signal line  21  (step S 2 ). The service processor  11  outputs 1 as the instruction fetch stop signal to the cores  121  via the instruction fetch stop signal line  22  (step S 3 ). Next, the service processor  11  transmits the boot firmware program  102  to the cache  122  via the CPU-SVP data bus  23  so that the boot firmware program  102  is stored in the cache  122  as a boot firmware program  103  (step S 4 ). 
         [0057]    Next, as illustrated in  FIG. 4 , the service processor  11  outputs 0 as the instruction fetch stop signal to the cores  121  via the instruction fetch stop signal line  22  (step S 5 ). When the input instruction fetch stop signal is changed to 0, the cores  121  obtain the reset address of the cache  122  stored in the PC registers  124 . The cores  121  then perform an instruction fetch from the boot firmware program  103  stored in the obtained reset address of the cache  122 , store boot firmware execution instruction code  104  into the instruction registers  123 , and execute the boot firmware execution instruction code  104  (step S 6 ). Here, the cores  121  perform a POST to test operations inside the CPU  12 . 
         [0058]    If serious failures are not detected by the POST and operations can be continued, as illustrated in  FIG. 5 , the cores  121  initialize the SDRAM  13  and then start refresh (step S 7 ). 
         [0059]    Next, as illustrated in  FIG. 6 , the cores  121  perform an instruction fetch from the boot firmware program  103  on the cache  122  (step S 8 ) to perform the following processing. The cores  121  copies the boot firmware program  103  stored in the cache  122  to the SDRAM  13 , so that the boot firmware program  103  is stored in the SDRAM  13  as a boot firmware program  105  (step S 9 ). The cores  121  further initialize the data area to be used for the execution of the boot firmware program on the SDRAM  13  (step S 10 ). 
         [0060]    The cores  121  then change the program to execute to the boot firmware program  105  on the SDRAM  13 . As illustrated in  FIG. 7 , the cores  121  then perform an instruction fetch from the boot firmware program  105  on the SDRAM  13 , store boot firmware execution instruction code  107  into the instruction registers  123 , and execute the boot firmware execution instruction code  107  (step S 11 ). Here, the cores  121  store data  106  into the initialized data area on the SDRAM  13  while executing the boot firmware program. The cores  121  thereby initialize the hardware of the server computer  1  other than the service processor  11 , the CPU  12 , or the SDRAM  13 . The cores  121  further read the OS boot loader from the external storage device  16  and execute the read OS boot loader. 
         [0061]    The flow of the boot processing by the server computer according to the present embodiment will be further described with reference to  FIG. 8 .  FIG. 8  is a flow chart of the boot processing of the server computer according to the present embodiment. 
         [0062]    The service processor  11  inputs 1 as the reset signal to the CPU  12 . The service processor  11  also inputs 1 as the instruction fetch stop signal to the cores  121  (step S 101 ). 
         [0063]    Next, the service processor  11  inputs 0 as the reset signal (step S 102 ). In other words, the reset signal input to the CPU  12  changes from 1 to 0. 
         [0064]    Next, the service processor  11  writes the boot firmware program into the cache  122  built in the CPU  12  (step S 103 ). 
         [0065]    The service processor  11  then inputs 0 as the instruction fetch stop signal (step S 104 ). In other words, the input fetch stop signal input to the cores  121  changes from 1 to 0. 
         [0066]    The cores  121  perform an instruction fetch from the boot firmware program stored in the reset address of the cache  122  built in the CPU  12 , and execute the boot firmware execution instruction code  104  (step S 105 ). 
         [0067]    The cores  121  then perform a POST (step S 106 ). 
         [0068]    If serious failures are not detected by the POST and operations can be continued, the cores  121  initialize and refresh the SDRAM  13  (step S 107 ). 
         [0069]    The cores  121  further copy the boot firmware program stored in the cache  122  to the SDRAM  13 . The cores  121  initialize the data area of the SDRAM  13  to be used for the execution of the boot firmware program (step S 108 ). 
         [0070]    The cores  121  then change the program to execute to the boot firmware program on the SDRAM  13  (step S 109 ). 
         [0071]    Subsequently, the cores  121  execute the boot firmware program on the SDRAM  13  to initialize the rest of the hardware of the server computer  1  other than the service processor  11 , the CPU  12 , or the SDRAM  13  (step S 110 ). 
         [0072]    The cores  121  then read the OS boot loader from the external storage device  16  and execute the OS boot loader (step S 111 ). 
         [0073]    As described above, the information processing apparatus according to the present embodiment does not need to include a boot ROM containing the boot firmware program. This can suppress the manufacturing cost of the entire product. 
         [0074]    The information processing apparatus according to the present embodiment fetches instructions of the boot firmware program from the cache built in the CPU and execute the instructions. The execution speed is therefore faster than with the conventional technique in which instructions are fetched from the boot firmware program on the main storage device. The information processing apparatus according to the present embodiment has an execution speed even faster than when using a boot firmware program stored in a cache outside the CPU. 
         [0075]    Moreover, the information processing apparatus according to the present embodiment can obtain the boot firmware program from outside. This eliminates the need to rewrite the boot ROM when the boot firmware program is updated. The writing speed of the ROM is lower than that of the operations of the CPU and SDRAM, and the update operation takes time. The information processing apparatus according to the present embodiment can reduce such a time-consuming update operation of the boot ROM. 
         [0076]    According to an aspect of the information processing apparatus, the method for controlling the information processing apparatus, and the control program of the information processing apparatus disclosed in the present application, the effect of enabling a reduction in product cost is obtained. 
         [0077]    All examples and conditional language recited herein are intended for pedagogical purposes of aiding the reader in understanding the invention and the concepts contributed by the inventor to further the art, and are not to be construed as limitations to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiment of the present invention has been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.