Abstract:
A 2n×n multiplexing switch has 2n VD(valid) extractors for validating the routing tags of the inputted cells and determine if the cell is to be saved or not, and generate VD signals, a FIFO buffer selector for selecting the FIFO buffer to store each cell using the VD signal and for transferring the cell to the selected FIFO buffer, a shared FIFO buffer consisting of 2n shared FIFO buffers and storing cells, an output device for reading cells stored in the FIFO buffers and for transferring n cells to output ports and a cell counter for counting cells currently stored in the shared FIFO buffer using the data from the FIFO buffer selector and the output device.

Description:
CLAIM OF PRIORITY 
     This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. §119 from an application for 2n×n MULTIPLEXING SWITCH earlier filed in the Korean Industrial Property Office on May 21, 1997 and there duly assigned Ser. No. 19656/1997. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a 2n×n multiplexing switch used for implementing the Advanced ATM Exchange and particularly relates to a 2n×n multiplexing switch including a VD (Valid) extracting part for generating a VD signal for determining whether or not a cell is to be transmitted, a shared FIFO (First In First Out) buffer selecting device for selecting the shared FIFO buffer, an output device and a cell counter. 
     2. Description of the Related Art 
     Up to now the Advanced (large capacity) Switch is implemented using full identical −n×n switches. 
     The earlier n×n switch used for implementing large capacity switches, includes a port filtering device including n port filters for each port, a FIFO (First In First Out) buffer selecting device, a shared FIFO buffering device including n FIFOs and an output device. Namely, in the past for implementing an n×n switch 2n port filters, n FIFO buffer selecting devices, 2n FIFOs and n output devices were indispensable. 
     The switch, first of all, copies the input cells n times and respectively transmits them to the port filter for each port. The port filter recognizes whether the cell being inputted is to be transmitted to its port. If the cell being inputted is to be transmitted to its port, the port filter transmits the cell to the FIFO buffer selecting device. If not, the port filter discards the cell. 
     The FIFO buffer selecting device configures the FIFO address and the transmission line so that the cell which has passed through the port filter can be stored in the shared FIFO buffering device, and the output device reads a cell from the shared FIFO buffering device every cell time and transmits it to the output port. 
     For implementing the n×n switch as stated above, it has problems in that quite a few steps are required, and the shared FIFO buffering device, which is included correspondingly to each port, cannot be shared, so that the FIFO buffer to need be very large. 
     Particularly, when a large-capacity switch is to be implemented, it has also problems in that the complete sharing of the output port cannot be easily implemented and for implementing the large-capacity switch, a very large quantity of logic gates are needed. 
     In addition, there is a problem in that if once the large-capacity switch is implemented using the n×n switch, it has basically the architecture of a Banyan network and in the above case, a degradation to a considerable extent is unavoidable. 
     The following patents each disclose features in common with the present invention but do not teach or suggest the specifically recited multiplexing switch of the present invention: U.S. Pat. No. 5,745,489 to Diaz et al., entitled Buffered Crosspoint Matrix For An Asynchronous Transfer Mode Switch And Method Of Operation, U.S. Pat. No. 5,724,354 to Tremel et al., entitled Method For The Insertion Of Cells Into An ATM Type Flow And Implementation Device, U.S. Pat. No. 5,684,798 to Gauthier, entitled Communication System Comprising A Network And A Multiplexing Device And Multiplexing Device Suitable For Such A System, U.S. Pat. No. 5,687,172 to Cloonan et al., entitled Terabit Per Second Distribution Network, U.S. Pat. No. 5,724,352 to Cloonan et al., entitled Terabit Per Second Packet Switch Having Assignable Multiple Packet Loss Probabilities, U.S. Pat. No. 5,608,719 to Hyodo et al., entitled ATM Multiplex Transmission System Having Test Equipment, U.S. Pat. No. 5,610,914 to Yamada, entitled Shared Buffer Memory Switch For An ATM Switching System And Its Broadcasting Control Method, U.S. Pat. No. 5,619,510 to Kurano, entitled Output Buffer Type Asynchronous Transfer Mode Switch And Detecting Error Boards Thereof, U.S. Pat. No. 5,642,349 to Cloonan et al., entitled Terabit Per Second ATM Packet Switch Having Distributed Out-Of-Band Control, U.S. Pat. No. 5,577,035 to Hayter et al., entitled Apparatus And Method Of Processing Bandwidth Requirements In An ATM Switch, U.S. Pat. No. 5,383,181 to Aramaki, entitled Packet Switching System Capable Qf Reducing A Delay Time For Each Packet, U.S. Pat. No. 5,406,554 to Parry, entitled Synchronous FIFO Having An Alterable Buffer Store, U.S. Pat. No. 5,448,559 to Hayter et al, entitled ATM Communication System With Interrogation Of Output Port Servers For Available Handing Capacity, U.S. Pat. No. 5,550,823 to Irie et al., entitled Method And Apparatus For Performing Priority Control For Cells In Output Buffer Type ATM Switch, U.S. Pat. No. 5,535,197 to Cotton, entitled Shared Buffer Switching Module, U.S. Pat. No. 5,732,085 to Kim et al., entitled Fixed Length Packet Switching Apparatus Using Multiplexers And Demultiplexers, U.S. Pat. No. 5,732,069 to Nagino et al., entitled ATM Switch, U.S. Pat. No. 5,710,770 to Kozaki et al., entitled ATM Cell Switching System, and U.S. Pat. No. 5,548,588 to Ganmukhi et al., entitled Method And Apparatus For Switching, Multicasting Multiplexing And Demultiplexing An ATM Cell. 
     SUMMARY OF THE INVENTION 
     To solve the above described problems, it is the object of the present invention to provide a 2n×2 multiplexing switch, which makes it possible to use n output ports uniformly, and uses a smaller number of path assignment tags as compared to earlier arrangements, and can minimize the diminishment of the efficiency by using a common buffer type switch. 
     Other objects and benefits of the present invention become apparent, if the following detailed description of the present invention is read and the attached drawings are referenced. A preferable embodiment of a 2n×n multiplexing switch may be constructed according to the principles of the present invention with a VD (valid) extracting device having 2n VD extractors, which validate the routing tags of the inputted cells and determine if the cell is to be saved or not and generates a VD signal; a FIFO buffer selecting device, which selects FIFO buffer to store each cell using said VD signal and transfers each cell to the selected FIFO buffer; a shared FIFO buffering device having 2n shared FIFO buffers and storing cells; an output device, which reads cells stored in the FIFO buffers and transfers n cells to output ports; and a cell counter, which counts cells stored currently in the shared FIFO buffering device using the data from the FIFO buffer selecting device and the output device. In the practice of the present invention, it is preferable that the FIFO buffer selecting device comprises a FIFO buffer address extracting device and a Banyan routing network. 
     It is preferable that the FIFO buffer address extracing device generates a FIFO address buffer (FAB) using 2n adders and 2n buffers. It is preferable that the adders inputs an FAB read finally at the previous cell time and VD, and if the VD is zero, then one is added, or else zero is added, and the result becomes the input of the next adders and at the same time it is stored in the buffer. 
     It is preferable that the output device be constructed with a read FIFO buffer address (RFA) generator reading cell count(CCNT); a FIFO buffer read enable (FRE) generator, which inputs the read FIFO buffer address from the read FIFO buffer address generator; and an output cell multiplexing device, which inputs the read FIFO buffer address from the read FIFO buffer address generator and inputs cells from the shared FIFO buffering device. 
     It is preferable that the read FIFO buffer address generator be constructed with n adders, which add one if the cell count read finally before one cell time is above zero, or else adds zero, and inputs the result to the next adder; and n buffers, which at the same time inputs the values inputted from the adders. 
     It is preferable that the i th  adder adds one, if the cell count inputted from previous adder is above i, or else adds zero, and transfers the result to the next adder and to the buffers. 
     It is preferable that the FIFO buffer read enable generator generates a FIFO buffer address enable signal using an RFA generated by the RFA generator, and includes 4n+1 comparators, 4n OR gates and 6n AND gates. 
     It is preferable that the output cell multiplexing device has n number of 2n×1 multiplexers and selects one cell from among read cells using an RFA generated by the RFA generator, and outputs it. 
     It is preferable that the cell count includes two subtracters, which compute the newly stored cells and the newly read cells at this cell time; and an adder-subtractor, which adds the cell count stored in shared FIFO buffering device up to before one cell time and the cell count stored newly at this cell time, and subtracts the cell count to be read newly, and finally computes the cell count stored in the shared FIFO buffering device at this cell time, and outputs to the adders of the RFA generator of the output device in order to compute the FIFO buffer address to be read from among the shared FIFO buffer at the next cell time. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A more complete appreciation of this invention, and many of the attendant advantages thereof, will be readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein: 
     FIG. 1 is a block diagram of an earlier n×n switch. 
     FIG. 2 is a block diagram of a 2n×n multiplexing switch constructed according to the principles of the present invention. 
     FIG. 3 is a detailed block diagram of the FIFO buffer selecting device of FIG. 2; 
     FIG. 4 is a detailed block diagram of the FIFO buffer address extracting device of FIG. 3; 
     FIG. 5 is a detailed block diagram of the output device of FIG. 2; 
     FIG. 6 is a detailed block diagram of the RFA generator of FIG. 5; 
     FIG. 7 is a detailed block diagram of the FRE generator of FIG. 5; 
     FIG. 8 is a detailed block diagram of the output cell multiplexing device of FIG. 5; and 
     FIG. 9 is a detailed block diagram of the cell counter of FIG.  5 ; 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 is a block diagram of the earlier n×n switch discussed in the Description of the Related Art above. A plurality of port filtering devices  10  feed a plurality of FIFO buffer selecting devices  20  which in turn feed a plurality of shared FIFO buffering devices  30  which in turn feed a plurality of output devices  40 . 
     The present invention is explained in detail referring to FIG. 2 hereafter. FIG. 2 is a block diagram of a 2n×n multiplexing switch of the present invention. In the present invention, as the input of 2n×n multiplexing switch, 2n cells are inputted to a VD extracting device ( 50 ) including 2n VD extractors. 
     The cell transmitted to each input port has a cell form, wherein the cell is effective every cell time, or a dummy cell form. And in the 2n×n multiplexing switch, the cells are selectively chosen and stored in a FIFO buffer selecting device ( 70 ) according to a routing tag among the 2n cells (I o ˜I 2n−1 ) being inputted every period and transmitted to an output device ( 90 ) through a shared FIFO buffering device ( 80 ). The output device ( 90 ) generates n cells (O 0 ˜O n−1 ) which are outputted through the output port every cell period. 
     The structure of the device ( 70 ) should be composed according to what the user wants, so there is no fixed structure. 
     The FIFO buffer selecting device ( 70 ) selects the FIFO buffer where each cell should be stored, referring to the cells (I o ˜I 2n−1 ) that are transmitted through 2n VD extractors and referring to the VD bits (VD o ˜VD 2n−1 ), and transmits the cell to the corresponding FIFO buffer. A cell counter ( 60 ) reads the address of each FIFO buffer in the shared FIFO buffering device ( 80 ), where the address is stored in the buffer by the FIFO buffer selecting device ( 70 ). Then the cell counter informs the output device ( 90 ) of the result of the cell count. The cell counter reads the FIFO address for reading from the output device ( 90 ). 
     FIG. 3 is a detailed block diagram of the FIFO buffer selecting device ( 70 ). The FIFO buffer selecting device ( 70 ) comprises a FIFO buffer address extracting device ( 100 ) and a Banyan routing network ( 110 ), i.e., the data inputted from the VD extracting device ( 50 ) is stored in the shared FIFO buffering device ( 80 ) uniformly through the FIFO buffer address extracting device ( 100 ) and the Banyan routing network ( 110 ). 
     FIG. 4 is a detailed block diagram of the FIFO buffer address extracting device ( 100 ) within the FIFO buffer selecting device ( 70 ); the FIFO buffer address extracting device ( 100 ) includes 2n adders and 2n buffers. The ADDER 0  adds 1, if the value of VD 0  in the FIFO address buffer FAB 2n−1  that is finally read at the previous cell time is 0, and adds 0 if the value is 1 so that it can be inputted to the next adder VD 1  and the result is stored in the BUFFER 0  at the same time. 
     The values (FAB 0 ˜FAB 2n−1 ) that are stored in these buffers (BUFFER 0 ˜BUFFER 2n−1 ) represent the addresses for each address of FIFO buffer in the shared FIFO buffering device ( 80 ) where each cell should be stored, and used as the routing tag representing the routing path that should be passed to the next phase of Banyan routing network ( 110 ). 
     The Banyan routing network( 110 ) transmits the cell to the FIFO buffer in the shared FIFO buffering device ( 80 ) to which each cell is to be reached using the FAB. 
     FIG. 5 is a detailed block diagram of the output device ( 90 ) of the present invention. The output device ( 90 ) reads out the 2n cells that are stored in the shared FIFO buffers with Round-robin scheduling in the order that is stored, to the maximum n, and transmits the cell to the output port. If the number of cells that are in the shared FIFO buffer is less than n, as many cells as there exist are outputted along with dummy cells to the output ports. 
     The output device ( 90 ) includes, as illustrated in FIG. 5, a FIFO read enable generator ( 140 ), a read FIFO buffer address generator ( 150 ) and an output cell multiplexing device ( 160 ). 
     If the cell count (CCNT) of the FIFO buffer read finally before one cell time is larger than zero, ADDER 0  adds one, or else adds zero, and the result is inputted to the next adder and to the buffer BUFFER 0  at the same time. If the CCNT is larger than i, ADDER i  adds one to the inputted value from former adder ADDER i−1 , or else adds zero, and then transfers the result to the next adder ADDER i+1  and buffer BUFFER i . 
     FIG. 6 is a detailed block diagram of the RFA generator ( 150 ) in the output device ( 90 ). The RFA generator includes n adders and n buffers. The FIFO address to be read is stored in the buffer. 
     FIG. 7 is a detailed block diagram of the FRE generator ( 140 ) of FIG.  5 . The FRE is generated using the RFA, which is generated by the RFA generator ( 150 ). As illustrated in FIG. 7, the FRE generator can be constructed using 4n+1 comparators ( 190 ), 4n OR gates ( 220 )( 230 ) and 6n AND gates ( 200 ), ( 210 ), ( 240 ). 
     COMPARATOR 0  ( 190 ) compares RFA 0  and RFA n−1 , and if RFA n−1  is larger than RFA 0 , it outputs one, or else zero. And if COMPARATOR 0 &#39;s (l 90 ) result is one, then COMPARATOR k0 &#39;s result L k and COMPARATOR k1 &#39;s result H k  are multiplied logically by AND gates ( 200 ) and ( 210 ) it becomes the value of each FRE k . If COMPARATOR 0 &#39;s ( 190 ) result is zero, then COMPARATOR k0 &#39;s result L k  and COMPARATOR k1 &#39;s result H k  are added logically by OR gate ( 230 ) and AND gate ( 240 ) and the result becomes the value of each FRE k  ( 220 ). 
     If the FRE k  is zero, then a cell from the kth FIFO buffer is read, or else if FRE k  is one, then F 0   k  is generated as a dummy cell. The cells (F 0   0 ˜F 0   2n−1 ) which were read through such a method are transferred to the output cell multiplexing device ( 160 ). 
     The multiplexer ( 250 ) of FIG. 8 selects one cell from among the read cells (F 0   0 ˜F 0   2n−1 ) by using the RFA generated by the RFA generator ( 150 ) and outputs it. That is, the OUTPUT PORT 0  selects the xth cell FO x  according to the value x of RFA 0 . The cell counter ( 60 ) records the number of cells currently being stored in the shared FIFO buffering device ( 80 ). The cell counter ( 60 ) is constructed of two subtracters ( 260 ),( 270 ) and an adder- subtractor ( 280 ) as illustrated in FIG.  9 . 
     The two subtracters ( 260 ),( 270 ) compute the number of cells which have been newly stored at this cell time (t=1 for example) and the number of cells which have been newly read respectively, and the adder-subtractor ( 280 ) computes the number of cells which will be newly saved at this time (t=1 for example) and the number of cells which have been newly read respectively. The adder-subtractor( 280 ) adds the CCNT (at t=0 for example) and the newly stored cell(NSC) and subtracts the newly read cell(NRC) and computes the number of cells which are stored in the shared FIFO buffering device ( 80 ) at this cell time (t=1 for example), and the result is transferred to the adder of the RFA generator for computing the address of the FIFO buffer to be read from the shared FIFO buffering device( 80 ) at the next cell time, where the NSC is the number of the newly stored cell which has been stored at this cell time (t=1 for example) and the NRC is the number of the cells which have been stored at this cell time (t=1for example), and the CCNT has been stored in the shared FIFO buffering device( 80 ) up to before one cell time (t=0 for example). 
     It should be understood that the present invention is not limited to the particular embodiment disclosed herein as the best mode contemplated for carrying out the present invention, but rather that the present invention is not limited to the specific embodiments described in this specification except as defined in the appended claims.