Abstract:
A programmable read-only memory device comprising a memory cell transistor which has a floating gate and a control gate formed above the floating gate. The programmable read-only memory device further comprises a means for delaying the application timing of a high voltage to the control gate from that of a high voltage to the drain of the memory cell transistor when a data programming operation is performed by applying the high voltage to the control gate and the drain of the memory cell transistor, thereby ensuring reliable a data write operation even at a low programming voltage.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor memory device and, more particularly, to a programmable read-only memory device wherein each memory cell comprises a transistor (referred to as a floating gate transistor hereinafter) having a floating gate and a control gate formed above the floating gate, and data can be programmed into the floating gate transistor reliably even at a low programming voltage. 
     2. Description of the Prior Art 
     Recently, the programming voltage for an EPROM (erasable programmable read-only memory) having a floating gate transistor as a memory cell has been lowered. This is mainly because transistors in a peripheral circuit are micropatterned and have a low breakdown voltage to realize a high density memory device, and the programming voltage must be lowered in accordance with such a reduced breakdown voltage. However, when the programming voltage is lowered, a programming current is also reduced to realize a high memory density memory device. As a result, data may not be properly programmed into a memory cell. For this reason, the peripheral circuit or the like must be improved to ensure that data is properly programmed into the corresponding memory cell. 
     In a conventional memory device, data is programmed into a memory cell, i.e., a floating gate transistor, by applying high voltages to the control gate and the drain of the transistor. However, since the application timings of the high voltages are not particularly determined, the programming operation of the floating gate transistor is not properly performed, especially when the high voltage is applied to the drain after it is applied to the control gate, or after the control gate voltage becomes relatively high. 
     SUMMARY OF THE INVENTION 
     The object of the present invention is to resolve the above problem, by providing a semiconductor memory device wherein each cell is constituted by a floating gate transistor, a drain voltage at the floating gate transistor increases faster than a gate voltage so as to properly program data into a memory cell even if a low programming voltage is used or a small programming current flow, and the transistors in the peripheral circuit or the like are micropatterned to realize a high density memory device. 
     According to the present invention, there is provided a programmable read-only memory device comprising: a memory cell transistor having a source, a drain, a floating gate, and a control gate formed above the floating gate; and a delay means for delaying the application timing of a high voltage applied to the control gate from that of a high voltage applied to the drain of the memory cell transistor when a data programming operation is performed by applying the high voltages to the control gate and the drain of the memory cell transistor. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a partial circuit diagram illustrating an equivalent circuit in a programming mode of a general EPROM device; 
     FIG. 2 is a cross section of a floating gate transistor used in the device of FIG. 1; 
     FIGS. 3A and 3B are graphs depicting the operating states of the circuit of FIG. 1 under different operating conditions; 
     FIG. 3A depicts a conventional example, and FIG. 3B depicts operation in accordance with the present invention; 
     FIGS. 4, 5, and 6 are circuit diagrams showing various circuit portions of a memory device as an embodiment of the present invention; 
     FIG. 7 is a waveform diagram illustrating the operation of the memory device including the circuit portions of FIGS. 4, 5, and 6; and 
     FIGS. 8, 9, 10, 11, and 12 are circuit diagrams showing various circuit portions of a memory device as another embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Before describing the preferred embodiments, an explanation will be made of the programming operation of a floating-gate transistor used as a memory cell of an EPROM device. 
     FIG. 1 shows an equivalent circuit diagram of a conventional EPROM in the programing mode. Referring to FIG. 1, reference symbol Q 1  denotes a data programming transistor; Q 2 , a column selection transistor; and Q 3 , a memory cell transistor having a floating gate (floating gate transistor). These transistors are connected in series between a high voltage of V PP , for example, 25 V, as a write voltage and a voltage V SS  as the ground voltage. A program signal IN is applied to the gate of the transistor Q 1 . The program signal IN is set at the high voltage V PP  when programming data of logic &#34;0&#34; is supplied. However, the program signal IN is set at the ground voltage when programming data of logic &#34;1&#34; is supplied. A column selection signal CLM is applied to the gate of the transistor Q 2 , and a row selection signal RWS is applied to the gate of the floating gate transistor Q 3 . These signals CLM and RWS are set at the high voltage V PP  when the corresponding column and row are selected in the programming mode. However, when the column and row are not selected in the programming mode, the signal CLM and RWS are set at a ground voltage V SS  of 0 V. The signals CLM and RWS are set at a high level, i.e., V CC  (e.g., 5 V), when the corresponding column and row are selected in the read mode. However, when the column and row are not selected in the read mode, these signals CLM and RWS are set at the ground voltage V SS . 
     FIG. 2 illustrates a structure of the floating gate transistor Q 3  used in the circuit of FIG. 1. The floating gate transistor Q 3  comprises an N +  -type source region 1 and an N +  -type drain region 2 both formed on a P -  -type semiconductor substrate 3, a floating gate 4 made of, e.g., polycrystalline silicon, and formed on the P +  -type channel region 5 of the substrate 3 via an insulation layer (not shown), and a control gate 6 made of, e.g., polycrystalline silicon, and formed on the floating gate 4 via an insultation layer (not shown). 
     In order to program data into the floating gate transistor Q 3  in the circuit of FIG. 1, the column selection signal CLM and the row selection signal RWS are set at the high voltage V PP , and the program signal IN is set at the high voltage V PP  or the ground voltage V SS  of 0 V accordance with the logical state of the programming of the data. In particular, when data of logic &#34;0&#34; is programmed, the program signal IN is set at the high voltage V PP , and the transistors Q 1  and Q 2  are turned on. For this reason, the drain and gate of the floating gate transistor Q 3  receive the high voltage V PP . Then, as is well known, electrons are injected into the floating gate of the floating gate transistor Q 3  by avalanche breakdown injection (including so-called channel injection), thereby programming data. 
     That is, in the structure of FIG. 2, when the high voltage is applied to the drain region 2, the drain side end of the channel region becomes pinched off due to the pinch-off effect and a depletion region extends between the end of the channel region and the drain. Therefore, the intensity of the electric field of the depletion region becomes very large and carriers in the depletion region are greatly accelerated by the electric field so that hot electrons are generated. In this case, if a high voltage is applied to the control gate 6, the hot electrons are attracted toward and injected into the floating gate 4 by the electric field generated by the high voltage of the control gate 6. 
     In the conventional EPROM, the application timings of the column selection signal CLM and the row selection signal RWS are not specifically controlled in the programming mode. In this case, no problem occurs when the programming voltage V PP  is as high as, for example, 25 V, and the breakdown voltages of the transistors Q 1  and Q 2  are sufficiently high. However, when the size of the transistors Q 1  and Q 2  is decreased to realize a high density circuit, the programming current is restricted to a small value, so that a programming operation cannot be properly performed. 
     As shown in FIG. 3A, when the row selection signal RWS increases prior to an increase in the column selection signal CLM and has reached the voltage V PP , voltage-current characteristics between the drain-source path of the transistor Q 3  become as given by curve R 4  in FIG. 3A. In this state, when the column selection signal CLM increases, the characteristics of a load circuit of the transistors Q 1  and Q 2  are shifted upward from those of curves L 1 , L 2  . . . and reach those of curve L 4  in FIG. 3A. Assuming that the curve L 4  is given as a load curve when the column selection signal CLM has reached V PP , then the programming voltage cannot reach a programming region WA subjected to avalanche injection of the transistor Q 3  although the column selection signal CLM has reached the high voltage V PP . Therefore, the programming operation cannot be performed. This is because the gate voltage at the transistor Q 3  goes to a high level faster than the drain voltage of the transistor. Thus, the current flowing through the transistor Q 3  becomes excessively large, and the programming currents of the transistors Q 1  and Q 2  are limited. As a result, the drain voltage will not be set at a high voltage (programming level), and the aforementioned hot electrons are not generated in the depletion region, so that the so-called avalanche injection or channel injection will not occur. Moreover, even when the row selection signal RWS and the column selection signal CLM simultaneously increase, the programming operation cannot be properly performed for the same reason as described above, if the programming current is not sufficiently large. 
     According to the present invention, in order to eliminate the problem with the conventional memory device, a column selection signal goes to a high level prior to the rising of a row selection signal, thereby effectively programming data. As shown in FIG. 3B, the column selection signal is increased to V PP  and is set in a state indicated by a load curve L 5 . In this state, the row selection signal RWS goes to a high level to shift the voltage-current characteristics of the transistor Q 3  upward in the order indicated by curves R 1 , R 2 , and R 3 . At the leading edge of the row selection signal RWS, even if a conductance of the transistor Q 2  is small, a sufficiently high voltage (approximately V PP ) is applied to the drain of the memory cell transistor Q 3 . Immediately after the transistor Q 3  is turned on, a parasitic capacitor attributed to the drain of the transistor Q 3  and charged with a sufficiently high voltage is discharged through the transistor Q 3 , and thus a larger load of curve L 5   than the steady load of curve L 4  determined by an ON resistance of the transistor Q 2  is present during a transition period due to the parasitic capacitor. Therefore, during the transition period, the operating point of the transistor Q 3  can reach inside a programming region (subjected to avalanche injection or channel injection) WA. 
     When electrons are gradually stored in the floating gate by avalanche injection after the programming operation is started, an electrical field acting from the control gate to the channel region of the memory cell transistor Q 3  decreases, thereby decreasing the conductance. Therefore, even if the ON resistance of the column selection transistor Q 2  is sufficiently high, the self-conductance of the memory cell transistor Q 3  is gradually decreased, so that a high voltage substantially the same as the voltage V PP  is gradually applied to the drain of the memory cell transistor Q 3 , and the operating point falls within the programming region, thereby performing complete programming. To promote this effect, the row selection signal RWS should have a longer rise time in order to prolong the period of the high-efficiency avalanche injection which occurs immediately after the programming operation is started. Thus, even if a low programming voltage or small programming current is used, the operating point can reach the programming region WA in accordance with the method described above. 
     FIGS. 4, 5, and 6 show a semiconductor memory device using N-channel MIS transistors according to an embodiment of the present invention. FIG. 4 is a circuit diagram of a delay circuit for delaying a programming instruction signal, i.e., a program signal PGM. This delay circuit comprises inverter transistors Q 4 , Q 5 , . . . , and Q 11 , and capacitors C 1 , C 2 , and C 3  connected to the output terminals of the respective inverters and power supply V SS . It should be noted that the transistors Q 4 , Q 6  and Q 8  are depletion type. The transistor Q 10  comprises a high-breakdown voltage depletion type transistor, and the transistor Q 11  is a high-breakdown voltage enhancement type transistor. 
     FIG. 5 shows a unit circuit of a row decoder provided to each row of the memory matrix (not shown). This unit decoder circuit comprises a NOR gate G 1  for receiving a unique combination of noninverted address signals (not shown) and inverted address signals ADD, a high-breakdown voltage depletion type transistor Q 12 , a high-breakdown voltage deep-depletion (low threshold voltage) type transistor Q 14  and a high-breakdown voltage non-dosed (zero threshold voltage) type transistor Q 13 . The transistor Q 14  comprises a transistor having a lower threshold voltage (e.g., V th  =-5 V) than the conventional depletion transistor (e.g., V th  =-3 V). The transistor Q 13  has a threshold voltage of 0 V. In the circuit shown in FIG. 5, an output from the gate G 1  goes to a high level when the associated row is to be selected. A row selection signal having the level V CC  is applied to the gate of the corresponding memory cell transistor through the transistor Q 12 . In this case, when a delayed program signal DPGM generated from the circuit of FIG. 4 goes to a level of the high voltage V PP , the transistor Q 13  is turned on, and the high voltage V PP  is generated as the row selection signal through the transistor Q 14 . This high voltage signal is cut off by the transistor Q 12  from the gate G 1 . The row selection signal RWS is set substantially at the V CC  level in the read mode and is set at the V PP  level in the programming mode. However, when the row is not selected, the output of 0 V from the gate G 1  appears as the row selection signal. The programming high voltage V PP  is cut off by the transistor Q 14  and will not be applied to the gate G 1 . During this operation, the power supply voltage V CC  is set to be, for example, 5 V, and the programming high voltage V PP  is set to be, for example, 12.5 V. 
     FIG. 6 shows the arrangement of a unit column decoder circuit. The unit column decoder circuit comprises a gate G 2  for receiving a unique combination of noninverted address signals (not shown) and inverted address signals ADD, a high-breakdown voltage depletion type transistor Q 15 , a high-breakdown voltage non-dosed type transistor Q 16 , and a high-breakdown voltage deep depletion type transistor Q 17 . The transistors Q 16  and Q 17  are the same as the transistors Q 13  and Q 14  of the decoder shown in FIG. 5, respectively. Unlike the decoder circuit in FIG. 5, the gate of the transistor Q 16  in the decoder circuit shown in FIG. 6 directly receives the program signal PGM. The operation of the decoder circuit in FIG. 6 is basically the same as that of FIG. 5, in that, when the associated column is to be selected, the output from the gate G 2  goes high, and the program signal PGM is set at the high voltage V PP , thereby generating a column selection signal CLM which is set substantially at the high voltage V PP . 
     In the above description, the program signal PGM is directly applied to the transistor Q 16  of the column decoder, and the program signal DPGM delayed by the delay circuit in FIG. 4 is supplied to the gate of the transistor Q 13  in the row decoder. Therefore, the leading edge of the row selection signal is delayed from that of the column selection signal. As shown in FIG. 7, the row and column selection signals simultaneously rise to the power supply voltage V CC  after the level of the address signal ADD changes, and the program signal PGM then rises. The delayed program signal DPGM rises after a short period of time has elapsed from the rise of the program signal PGM. The column selection signal CLM rises from the V CC  level to the V PP  level, and thereafter, the row selection signal RWS rises from the V CC  level to the V PP  level. Therefore, the data can be properly programmed even if the programming voltage V PP  is relatively low. 
     A semiconductor memory device using a CMIS circuit will be described in accordance with another embodiment of the present invention. FIG. 8 shows a delay circuit using a CMIS circuit. This delay circuit corresponds to that shown in FIG. 4. In the circuit shown in FIG. 8, the program signal PGMC is inverted by a CMIS inverter 11 consisting of a P-channel MOS transistor Q 18  and an N-channel MIS transistor Q 19 . The inverted program signal is supplied to a parallel circuit of an N-channel MIS transistor Q 20  and a P-channel MIS transistor Q 21 . The parallel circuit of the transistors Q 20  and Q 21  serves as a resistor, and this parallel circuit and capacitors C 4  and C 5  constitute an integrator. The inverted program signal is delayed by the integrator and is inverted again by a CMIS inverter 12 consisting of a P-channel MIS transistor Q 22  and an N-channel MIS transistor Q 23 , thereby obtaining a delayed program signal PGMR. 
     FIG. 9 shows a power switching circuit for generating an internal power supply voltage V PPI  (C) to be supplied to the column decoder. The power switching circuit comprises a CMIS inverter 13 consisting of a P-channel MIS transistor Q 24  and an N-channel MIS transistor Q 25 , high-breakdown voltage cut off N-channel MIS transistors Q 26  and Q 27 , a high-breakdown voltage P-channel MIS transistor Q 28 , a CMIS inverter 14 consisting of a high-breakdown voltage P-channel MIS transistor Q 29  and a high-breakdown voltage N-channel MIS transistor Q 30 , a power supply switch consisting of a high-breakdown voltage N-channel non-dosed MIS transistor Q 31  and a high-breakdown voltage N-channel depletion type MIS transistor Q 32 , and a CMIS inverter 15 consisting of a P-channel MIS transistor Q 33  and an N-channel MIS transistor Q 34 . 
     When the program signal PGMC is set at a high level, the circuit shown in FIG. 9 is set in the programming mode. In this case an output from the CMIS inverter 13 goes to a low level, and an output from the CMIS inverter 14 goes to a high level. The transistor Q 31  is thus turned on. Since an output from the CMIS inverter 15 is set at a low level, the transistor Q 32  is turned off. Therefore, the high voltage V PP  is applied as the internal high voltage V PPI  (C) to the column decoder through the transistor Q 31 . 
     On the other hand, when the program signal PGMC is set at a low level, an output from the CMIS inverter 13 goes to a high level, and an output from the CMIS inverter 14 goes to a low level, so that the transistor Q 31  is cut off. Then an output from the CMIS inverter 15 goes to a high level, and the transistor Q 32  is turned on. The power supply voltage V CC  is applied to the column decoder through the transistor Q 32 , and thus the read operation is performed. In this case, since the output from the CMIS inverter 14 is set at a low level, the transistor Q 28  is turned on to completely cut off the transistor Q 29 . Therefore, the input level of the transistor Q 31  is completely set at the power supply voltage V PP . 
     FIG. 10 shows a power supply switching circuit for generating an internal power supply voltage V PPI  (R) to be supplied to the row decoder. The circuit in FIG. 10 has the same arrangement as shown in FIG. 9 and comprises a CMIS inverter 16 composed of the transistors Q 35  and Q 36 , a separator for transistors Q 37  and Q 38 , a CMIS inverter 17 composed of the transistors Q 39 , Q 40 , and Q 41 , a power supply switch for transistors Q 42  and Q 43 , and a CMIS inverter 18 composed of transistors Q 44  and Q 45 . The operation of the circuit in FIG. 10 is substantially the same as that of FIG. 9, except that the delayed program signal PGMR from the circuit of FIG. 8 is supplied to the CMIS inverters 16 and 18. Therefore, the internal power supply voltage V PPI  (R) from the circuit of FIG. 10 is sligtly delayed from the internal power supply voltage V PPI  (C) from the circuit in FIG. 9. 
     FIG. 11 shows a unit row decoder circuit provided to each row of the memory matrix. This unit row decoder circuit comprises an OR gate G 3 , a high-withstand voltage N-channel MIS transistor Q 46 , a high-breakdown voltage P-channel MIS transistor Q 47 , and a CMIS inverter 19 consisting of a high-breakdown voltage P-channel MIS transistor Q 48  and a high-breakdown voltage N-channel MIS transistor Q 49 . 
     When the associated row is selected, an output from the gate G 3  in the unit row decoder circuit in FIG. 11 goes to a low level, and an output (i.e., the row selection signal RWS) from the CMIS inverter 19 goes to a high level. In this case, when the memory device is set in the programming mode, the internal power supply voltage V PPI  (R) from the power supply switching circuit in FIG. 10 is set at the high voltage V PP , so that the row selection signal RWS becomes substantially the same as the high voltage V PP . On the other hand, in the read mode, the internal power supply voltage V PPI  (R) becomes substantially the same as the power supply voltage V CC . Therefore, the row selection signal RWS becomes substantially the same as the power supply voltage V CC . In this case, the transistor Q 47  is kept turned off. 
     When the row is not selected, an output from the gate G 3  goes to a high level, and the row selection signal RWS goes to a low level. In this case, the transistor Q 47  is turned on and the input terminal of the CMIS inverter 19 rises. Therefore, the row selection signal RWS is completely clamped to a low level. 
     FIG. 12 shows the arrangement of a unit column decoder circuit. This unit column decoder circuit has the same arrangement as the row decoder circuit of FIG. 11, except that the power supply voltage V PPI  (C) supplied from the power supply switching circuit in FIG. 9 is used as the internal power supply voltage. As is apparent from the circuits shown in FIGS. 11 and 12, the row selection signal RWS is slightly delayed from the column selection signal CLM. Thus, even if the programming voltage V PP  is low, data can be properly programmed. 
     According to the present invention, since the high voltage applied to the control gate of the floating gate transistor is delayed from the high voltage applied to the drain, data can be properly programmed even if the programming voltage is low, the sizes of the peripheral transistors can be decreased, and hence a highly integrated memory can be obtained.