Abstract:
A compact, low current flash EPROM cell that is scaleable to dee-submicron levels for future generations of flash memory arrays is disclosed. This flash memory cell can be fabricated using a twelve masks, triple-poly, salicided process. Source-side injection for programming and poly-to-poly erasing demand very little current and power and such demand can easily be met by charge pump techniques. A select gate in series with the cell channel guarantees enhancement threshold and its sell-alignment and constant channel length will give uniform electrical characteristics in every respect. A virtual ground array fabricated using a self-aligned salicidation process provides a compact cell with high access speed. The cell area is approximately 3F×2F where F is a given minimum dimension.

Description:
FIELD OF THE INVENTION 
     The present invention generally relates to flash memory cells and arrays, and, in particular, to flash EPROM cells and arrays. 
     BACKGROUND OF THE INVENTION 
     Single transistor non-volatile electrically alterable memory devices where bits can be individually programmed but collectively erased are known as flash EPROM memory devices. A representative example now in production is described in U.S. Pat. No. 5,242,848. The floating gate of the flash cell as taught in that patent disclosure is strongly coupled with the deep diffusion of the bit line, but is only weakly coupled to the word line through a thick LOCOS oxide grown on the floating gate. The polysilicon word line serves as an erase line at the bird&#39;s beak of the floating gate and also as a select gate which allows for programming by source-side injection. 
     Such a cell design, although viable, has a number of short comings. The large lateral drain diffusion needed for coupling requires a large fraction of the cell area, leaving only a small channel length to the floating gate for control of the channel. Since the field oxide edges can not be self-aligned to any of the gates, allowances must be made for misalignment, variations in diffusion line width and select gate length, and waste in cell area. All these features make it difficult to scale the device down, especially in the deep sub-micron regime where dimensional uncertainty must comprise only a small fraction of the overall geometry. 
     Therefore, it would be desirable to have a method for manufacturing of EPROM memory cells that is scaleable to deep-submicron levels using self alignment techniques and have a resulting memory array that requires low current for programming the memory cells. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a method for fabricating memory cells for a memory array using self alignment techniques to allow scaling of the device, to eliminate source corner misalignment effect, and to provide cells having uniform electrical characteristics. 
     It is another object of the present invention to provide a method for fabricating memory cells for a memory array having select gates for selecting one or more memory cells for program or erase operations. 
     It is still another object of the present invention to provide a method for fabricating memory cells for a memory array requiring only low current for source side injection in programming the memory cells. 
     It is yet another object of the present invention to provide a method for fabricating memory cells for a memory array that does not require high voltage on the source or bit line for the erase operation. 
     Briefly, the present invention discloses a compact, low current flash EPROM cell that is scaleable to deep-submicron levels for future generations of flash memory cells. This flash memory cell can be fabricated using a twelve masks, triple-poly, salicided process. Source-side injection for programming and poly-to-poly erasing demand very little current and power and such demand can easily be met by charge pump techniques. A select gate in series with the cell channel guarantees enhancement threshold. Self-alignment of both the spacer and drain/source regions and constant channel will give uniform electrical characteristics in every respect. A virtual ground array fabricated using a self-aligned salicidation process provides a compact cell with high access speed. The cell area is approximately 3F×2F where F is a given minimum dimension. For example, for 0.25 μm generation, the cell area is 0.56 μm 2 , which is capable of yielding a 256 mb chip 1.3 cm on a side. 
     An advantage of the present invention is that it provides a method for fabricating memory cells for a memory array using self alignment techniques to allow scaling of the device, to eliminate source corner misalignment effect, and to provide cells having uniform electrical characteristics. 
     Another advantage of the present invention is that it provides a method for fabricating memory cells for a memory array having select gates for selecting one or more memory cells for program or erase operations. 
     Still another advantage of the present invention is that it provides a method for fabricating memory cells for a memory array requiring only low current for source side injection in programming the memory cells. 
     Yet another advantage of the present invention is that it provides a method for fabricating memory cells for a memory array that does not require high voltage on the source or bit line for the erase operation. 
     These and other features and advantages of the present invention will become well understood upon examining the figures and reading the following detailed description of the invention. 
    
    
     DRAWINGS 
     FIGS. 1a, 1b, and 1c show a table listing the steps in fabricating a preferred embodiment of the memory cells and array of the present invention. 
     FIG. 2 illustrates a top view of the memory array of the preferred embodiment of the present invention. 
     FIG. 3A illustrates a cross-sectional view of a memory cell of the preferred embodiment in forming the select gate stripes. 
     FIG. 3B illustrates another cross-sectional view of a memory cell of the preferred embodiment when forming the select gate stripes. 
     FIG. 3C illustrates yet another cross-sectional view showing FOX and bird&#39;s beaks. 
     FIG. 4A illustrates a cross-sectional view of a memory cell of the preferred embodiment after removing the right side stripe and leaving the left stripe as the select gate stripe. 
     FIG. 4B illustrates another cross-sectional view of a memory cell of the preferred embodiment after removing the right side stripe and leaving the left stripe as the select gate stripe. 
     FIG. 4C illustrates yet another cross-sectional view showing FOX and bird&#39;s beaks after removing the right side stripe and leaving the left stripe as the select gate stripe. 
     FIG. 5A illustrates a cross-sectional view of a memory cell of the preferred embodiment after doping the source and drain regions. 
     FIG. 5B illustrates another cross-sectional view of a memory cell of the preferred embodiment after doping the source and drain regions. 
     FIG. 5C illustrates yet another cross-sectional view showing FOX and bird&#39;s beaks after doping the source and drain regions. 
     FIG. 6A illustrates a cross-sectional view of a memory cell of the preferred embodiment after the word line has been laid. 
     FIG. 6B illustrates another cross-sectional view of a memory cell of the preferred embodiment after the word line has been laid. 
     FIG. 6C illustrates yet another cross-sectional view showing FOX and bird&#39;s beaks after the word line has been laid. 
     FIG. 7 shows a circuit layout of the memory array of the preferred embodiment of the present invention. 
     FIG. 8 illustrates a top view of the memory array structure after processing (control gates not shown). 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In a presently preferred embodiment of the present invention, a scaleable, compact, low current hash EPROM cell and memory array fabricated by using a twelve masks, triple-poly, salicided process are disclosed. Referring to FIGS. 1a, 1b, and 1c, a detailed listing of the steps for the fabrication of the memory array of the present invention is illustrated. In step 1, as part of the process in forming a triple well set-up (negative voltage on), deep n-wells are defined by using a p-Si substrate and growing initial oxide to about 2000 Å. Then, the defined areas for the formation of the n-well are masked and etched to expose these areas for doping. In step 2, implantation of phosphorous ions is performed and the ions are driven in at about 1100° C. to form the n-wells. In step 3, p-well regions are defined and doped for both the array area and the periphery by first masking the defined p-well regions, oxide etching these regions, and implanting the regions with boron. In step 4, n-well regions for the periphery (outside of the array) are defined and doped by a similar process of masking the defined regions, oxide etching these regions, and implanting the regions with boron. In step 5, a diffusion process is used for forming the n-wells and p-wells where corresponding dopants are driven into the respective wells, and the silicon is then made bare by oxide etching. In the next step, step 6, pad oxides are grown and nitride is deposited to define active areas. In step 7, boron field implantation is performed and local oxidation of silicon (LOCOS) is carried out to grow approximately 4000 Å of oxide. At this point, the bird&#39;s beaks are formed. 
     After the field oxide is grown, in step 8, the oxide for insulating the floating gates are grown by first etching off the nitride and the pad oxide, and the gate oxide is grown to approximately 120 Å. In the next step (step 9), about 2000 Å of composite polysilicon is deposited and doped with phosphorous and about another 2000 Å of nitride is deposited in succession. In this manner, the floating gate poly is formed. In step 10, floating gate stripes are made by masking and etching the nitride and poly 1 in succession in the appropriate areas. FIG. 2 illustrates a top view of the memory array after this step, showing the floating gate stripes overlapping the field oxide (FOX) stripes. Additionally, three cross-sectional indicators, A-A&#39;, B-B&#39;, and C-C&#39; are provided for reference purposes for later figures to illustrate the cross-sections of the physical structure of the memory array during the various stages of the fabrication process. The cross-sectional view as indicated by A-A&#39; illustrates a cut-away view including both the FOX and the floating gate stripes; the cross-sectional view as indicated by B-B&#39; illustrates the floating gate stripes in relation to the silicon; and the cross sectional view as indicated by C-C&#39; illustrates the FOX and the bird&#39;s beak. 
     Next, tunnel oxide and gate oxide for the select gate is grown. In this process, referring to step 11, oxide is thermally grown to produce about 300 Å on the polysilicon side walls and about 120 Å on the substrate due to the difference in doping levels in the silicon. Now, the threshold voltage Vt is adjusted for the select gate by masking the appropriate areas to perform boron implantation. Then, the select gate polysilicon is made (step 13) by depositing a polysilicon film of approximately 4000 Å and implanting phosphorous on the film. Next, in step 14, poly 2 (second polysilicon layer) spacers and their connecting pads are formed by masking the appropriate areas and performing reactive ion etching (RIE)-type of anisotropic etching on those areas. In this step, the periphery is covered with photo resist. The method for forming the select gate and the resulting structure is self-aligned to the floating gate and is of precise and uniform gate length. FIG. 3A illustrates a cross-sectional view (including FOX) of the memory cells after step 14 where there is a stripe of select gate 10 on each side of the floating gate 12. There is a layer of nitride deposited on the floating gate to serve as an etch stop. FIG. 3B illustrates another cross-sectional view in an area without the FOX where there is again a stripe of select gate 10 on each side of the floating gate 12. FIG. 3C illustrates a cross-sectional view of the bird&#39;s beak after this step showing the field oxide 14, the floating gate 16, and the nitride layer 18. The channel region is indicated at 20. 
     In step 15, the right side poly 2 spacer is etched out by masking and performing isotropic poly etching of the desired areas (the CMOS areas are also covered). FIGS. 4A illustrates a cross-sectional view of the memory cell (including the FOX) after the stripe on the right has been removed. FIG. 4B illustrates a cross-sectional view in the active areas after the stripe on the right has been removed. Similarly, FIG. 4C illustrates the bird&#39;s beak after the removal of the stripe on the right side, noting that there has not been any changes from this view. In a self aligned method, using the floating gate and select gate as a mask, RIE oxide etching is then performed to remove the field oxide and expose the silicon (step 16). 
     After the silicon is made bare, the source and drain regions (within the array) can be made by arsenic implantation (step 17). FIGS. 5A and 5B illustrate the memory cell after the source and drain regions 20 have been formed. FIG. 5C illustrates the bird&#39;s beak of the LOCOS oxide after this step where the certain other field oxide areas were made bare for implanting the drain and source regions. 
     In the next step (step 18), the select gate side wall oxides are thermally grown to about 1000 Å, and an additional oxide layer about 1000 Å is deposited and then RIE etched to form an oxide spacer. These two oxide layers help to protect the structure against etching so that in subsequent steps the select gate is still protected while the floating gate is being etched and patterned. Then, the floating gate surface is made bare by a phosphoric acid nitride etching process (step 19). In the next step, step 20, an inter-poly dielectric layer is formed by depositing a composite ONO film. In step 21, the word line (control gate) poly is formed by depositing a third layer of polysilicon (poly 3) having a thickness of about 2000 Å and an oxide layer grown for about another 1000 Å. In step 22, plasma etching is performed on the word line oxide (poly 3) and ONO, down to the floating gate surface. To form individual poly 1 islands (step 23), the same etching sequence continues to etch the floating gate, using the word line (control gate) as masks where the select gates are protected by oxide spacers. FIGS. 6A and 6B illustrate the physical structure of the memory cell after this step, and FIG. 6C illustrates the cross-sectional view of the bird&#39;s beak. 
     Next, n-channel gates are formed from poly 2 by covering the p-channel devices and performing RIE poly etching accordingly for the n-channel gates (step 24), and LDD implant of phosphorous ions is subsequently performed (step 25). In the next step, step 26, oxide spacers are formed for n-channel devices and floating gate edges by depositing about 1000 Å of oxide and a blanket RIE etching is performed. Next, the source and drain regions are formed for the n-channel devices by arsenic implantation (step 27). Note that since both the p-channel and memory areas are sealed in polysilicon, no masking step is necessary. Having now completed the n-channel devices, the p-channel devices can be formed by masking the n-channel devices and etching the poly gates for the p-channel devices (steps 28, 29, and 30). The source and drain regions for p-channel devices can be created by implanting BF 2  ions in the same manner. 
     To start the saliciation process forming C49 TiSi 2 , a titanium film having a thickness of about 500 Å is deposited and rapid thermo annealing (RTA) is performed at about 500° C. in nitrogen (step 30). A wet chemical etching process is performed to remove unreacted Ti and RTA annealed at 750° C. to form C54 TiSi 2  over the word, source, and bit lines and the peripheral diffusion areas (steps 31 and 32). ILD is formed by depositing a layer of about 3000 Å of BPSF and using a reflow process (step 33). The contacts to the memory cells are formed by masking and oxide etching the appropriate areas (step 34). A layer of composite metal film (Ti/TiN/Al) is deposited for forming the metal lines (step 35), and a final masking and RIE etching of the areas for forming the metal lines is performed (step 36). 
     A memory array fabricated using the above described process can be layout as shown in FIG. 7. In operating such a memory array, Table 1 lists the operating voltages for each respective line for performing the desired operations. 
     
         ______________________________________       Operation        Program 1  Program 2Electrode    (SSI)      (CHE)    Erase  Read______________________________________WL Selected  12 V       5 V      -10 V  4 VSG Selected  2 V        5 V      8 V    4 VSource Selected        0 V        0 V      F      0 VBL Selected  5 V        8 V      F      2 VWL Not-Selected        0 V        0 V      0 V    0 VSG Not-Selected        0 V        0 V      0 V    0 VSource Not-Selected        0 V        0 V      0 V    0 VBL Not-Selected        0 V        0 V      0 V    0 V______________________________________ 
    
     As is shown by Table 1, in operating the one or more memory cells, there are four lines associated with each of the memory cells, the word line or control gate (WL), select gate line (SG), source line, and the bit line (BL or drain line). One or more selected memory cells can be operated by properly applying the necessary voltage potential to the respective lines. For the non-selected memory cells, no voltage potential is needed at any of the lines. 
     In programming one or more selected memory cells using the source side injection method (SSI), referring to column 1 of Table 1, 12 V is placed on the word line, 2 V is placed on the select gate, 0 V is placed on the source line, and 5 V is placed on the bit-line. In programming selected memory cells using the CHE method, 5 V is placed on the word line, 5 V is placed on the select gate line, 8 V is placed on the bit-line, and the source-line is at 0 V. In the erase operation, 10 V is applied at the word line of the selected memory cell or cells, 8 V is placed on the select gate line, and the source and BL lines are floating. Note that single cell cross-point erasure is possible by addressing the respective select gate and control gate which is perpendicular to each other. In the read operation, 4 V is applied at the word line, another 4 V is applied at the select gate line, 2 V is applied at the bit-line, and no voltage potential is applied at the source line. 
     Note that the select gate is also used as an erase gate when conducting erase operations. An erase operation is achieved through FN tunneling of the electrons between the select gate and the floating gate. 
     Although the present invention has been described in terms of specific embodiments it is anticipated that alterations and modifications thereof will no doubt become apparent to those skilled in the art. It is therefore intended that the following claims be interpreted as covering all such alterations and modifications as fall within the true spirit and scope of the invention.