Abstract:
A ramp generator for an analog-to-digital converter comprises an array of capacitors each controlled by a switch responsive to one or more control signals and operable to connect/disconnect one or more of the capacitors relative to the array and a current source operable to charge at least one of the capacitors. A method for operating a ramp generator having an array of capacitors comprises resetting the ramp generator, enabling a current generator to charge at least one capacitor in the switched capacitor array, and controlling the state of one or more switches, wherein the switches are operable to connect and disconnect one or more of the capacitors relative to the array. The output of the ramp generator having a plurality of programmable breakpoints. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Description:
BACKGROUND 
   The present invention relates generally to a ramp generator for analog-to-digital (A/D) conversion applications and more particularly to a programmable non-linear ramp generator which utilizes a switched-capacitor array for A/D conversion applications. 
   An analog-to-digital converter (ADC) may be used to translate an analog signal (e.g., a current or voltage produced by a sensor) into a digital signal that can be used by another device (for example, a microprocessor). In complimentary metal-oxide semiconductor (CMOS) imaging applications, for example, ADCs are increasingly being used as the preferred means for converting charge captured by CMOS sensors into a digital read-out. 
   Several types of ADCs are currently used, each type differing in the technique utilized to complete the A/D conversion. For example, feed-back type converters, dual-slope converters, flash converters, charge-redistribution converters, and digital ramp converters are known in the art. 
   A feedback-type converter typically employs a comparator, an up-down counter, and a digital-to-analog converter (DAC).  FIG. 8  is a simplified diagram of a prior art feedback-type converter. An analog signal (V A ) is fed to one input of the comparator. The output of the comparator is connected to the input of the counter. The outputs of the counter are connected to the inputs of the DAC and the output of the DAC (V o ) is fed back to another of the comparator&#39;s inputs. The counter also receives a clock signal. Whenever the output of the comparator is high (i.e., when the difference between V A  and V o  is positive), the counter counts the pulses of the clock signal and the output of the counter increases. This in turn causes the voltage V o  to rise. When V o  equals V A , the output of the comparator goes low and the counter is stopped. At this point, the counter&#39;s output represents the digital equivalent of the analog signal voltage. 
     FIG. 9  is a simplified diagram of a prior art dual-slope converter. A dual-slope converter typically functions in two stages. In the first stage, an analog signal (V A ) is applied for a fixed time period to charge the capacitor C 1  and produce a voltage v 1 . The voltage v 1  typically has a variable slope during this first stage. In the second stage, a reference signal (V ref ) is applied for a variable time period and allows the voltage v 1  to discharge from the capacitor C 1 . The voltage v 1  typically has a constant slope during the second stage. Control logic provides signals to control switching between the first and second stages. The control logic also provides control signals to a counter which is used to count pulses from a fixed-frequency clock. The count recorded by the counter during the second stage represents the digital equivalent of the analog voltage applied during stage  1 . 
     FIG. 10  is a simplified diagram of a prior art flash converter. A flash converter typically uses 2 N-1  comparators to simultaneously compare the analog input signal level (V A ) to each of the 2 N-1  possible quantization levels. A 4-bit DAC, for example, uses sixteen comparators to convert an analog signal into a 4-bit digital word. The DAC includes a logic block that encodes the output from each of the sixteen comparators into the N-bits of the digital word. For instance, an analog input signal between 0 and 5V may be represented using the 4-bit binary number. The 4-bit binary number may represent 2 4  (i.e., 16) different values (i.e., from 0 to 15). The resolution of the conversion will thus be 5V/15=⅓V. Accordingly, the first quantization level (e.g., for bit  0000 ) corresponds to an analog signal of 0V, the second quantization level (e.g., for bit  0001 ) corresponds to an analog signal of ⅓V, the third quantization level (e.g., for bit  0010 ) corresponds to an analog signal of ⅔V, and so on. This pattern is repeated for each of the sixteen quantization levels (i.e., up to bit  1111 , which corresponds to an analog signal of 5V). 
     FIG. 11  is a simplified diagram of a prior art charge-redistribution converter. A charge-redistribution converter typically uses a capacitor array, a comparator, switches, and control logic, among others. During operation, a voltage (v A ) proportional to the analog input voltage (V A ) is first stored across the capacitors in the capacitor array by connecting one side of the array to V A  and the other side of the array (e.g., the side also connected to an input of the comparator) to ground. The plates of capacitors connected to the input terminal of the comparator are then open-circuited (e.g., switch S 2  is opened) while the plates of the capacitors on the other side of the capacitor array are switched to ground (e.g., SC 1 , SC 2 , . . . SC 6  are connected to ground). Next, the charge stored by the capacitors is redistributed by switching the individual capacitors to the reference voltage and/or ground until the voltage across the plates of the capacitors reaches zero. The final position of the switches (i.e., SC 1 , SC 2 , . . . SC 6 ) represents the output of the digital word. For example, a switch that is connected to ground in its final position represents a “0”; whereas a switch connected to the reference voltage source in its final position represents a “1”. 
   A digital ramp converter typically includes a comparator and a ramp generator. An analog signal is fed to one input of the comparator and the output of the ramp generator is fed to another input of the comparator.  FIG. 12  is a simplified circuit diagram of a ramp generator  100  and a comparator  102  according to the prior art.  FIG. 13  is a timing diagram for a ramp generator  100  of  FIG. 12  according to the prior art. The ramp generator  100  is comprised of a plurality of identical switching current sources  101 ( 1 ),  101 ( 2 ),  101 ( 3 ), . . .  101 ( n ), a capacitor  103 , and reset switch S 0 . Operation begins by placing the ramp generator  100  into the reset mode by opening switches S 1 , S 2 , S 3 , . . . S n  and closing switch S 0 . Referring to  FIG. 13 , at t o , signal T o  goes high and signals T 1  through T n  remain low (which keep switches  101 ( 1 ) through  101 ( n ) open). When signal T 0  goes high, switch S 0  is closed and the output of the ramp generator  100  is connected to the voltage source V ref  (i.e., V ramp  equals V ref ). 
   At t 1 , signal T 0  goes low opening switch S 0  and signal T 1  goes high closing switch S 1  and enabling current source  101 ( 1 ). Current source  101 ( 1 ) charges capacitor  103  and the output of the ramp generator (i.e., V ramp ) begins to rise above V ref  at a constant rate which is proportional to the value of the current source  101 ( 1 ). At the first break point, t 2 , signal T 2  goes high closing switch S 2  and enabling current source  101 ( 2 ). The slew rate of the ramp generator output is now doubled. At the next break point, t 3 , signal T 3  goes high closing switch S 3  and enabling current source  101 ( 3 ). This increases the slew rate of the ramp generator again. The final break point occurs at t n  when the last current source  101 ( n ) is enabled by signal T n  closing switch S n . 
   Returning to  FIG. 12 , the output of the ramp generator (i.e., V ramp ) is supplied to an input terminal comparator  102 . Comparator  102  compares V ramp  with an analog signal V a , which is supplied to another input terminal of the comparator  102 . If V a  is greater than V ramp , the output of comparator  102  is high and the ramp generator  100  continues to increase V ramp . If V ramp  is greater than V a , the output of the comparator  102  goes low and the ramp generator  100  stops increasing V ramp . An ADC code counter (not shown) is used to stop the ramp and to determine the ADC code. 
   One major drawback inherent to prior art ramp generators  100 , however, is the difficulty encountered in trying to manufacture matched current generators. Due to the manufacturing techniques used to construct the transistors comprising the current sources, a current source can typically only be matched within approximately 2% of another current source. The inability to accurately match current source leads to inaccurate conversion of the analog signal. 
   As discussed above, ADCs are increasingly being used as the preferred means for converting charge captured by CMOS sensors into a digital read-out in CMOS imaging applications. The error inherent in the prior art ADCs adversely effects the results obtained in the CMOS imaging applications. 
   Accordingly, a need exists for a modulating ramp A/D converter which overcomes these problems and which overcomes other limitations inherent in the prior art. More specifically, a need exists for a modulating ramp A/D converter which can be used in CMOS imaging applications, for example, to convert charge captured by CMOS sensors into a digital read-out. 
   SUMMARY 
   One aspect of the invention relates to a ramp generator for an analog-to-digital converter comprising an array of capacitors each controlled by a switch operable to connect/disconnect one or more of the capacitors within the array, wherein each of the switches is responsive to one or more control signals and a current source operable to charge at least one of the plurality of capacitors within the array. 
   Another aspect of the invention relates to a ramp generator comprising first and second operational amplifiers. The first operational amplifier has an input for receiving a first reference voltage, an input connected to at least one of a first current source, a first bias current source, and a first side of a first array of capacitors each controlled by a switch, and an output connected to a second side of the first array. The second operational amplifier has an input for receiving a second reference voltage, an input connected to at least one of a second current source, a second bias current source, and a first side of a second array of capacitors each controlled by a switch, and an output connected to a second side of the second array. 
   Another aspect of the invention relates to a method for operating a ramp generator having an array of capacitors each controlled by a switch comprising resetting the ramp generator, enabling a current generator, the current generator charging at least one capacitor within the array, and controlling the state of one or more switches, wherein the switches are operable to connect/disconnect one or more capacitors within the array. 
   Another aspect of the invention relates to an analog-to-digital converter comprising a comparator and a ramp generator. The ramp generator is comprised of an array of capacitors each controlled by a switch operable to connect/disconnect one or more of a plurality of capacitors within the array, wherein the plurality of switches are responsive to one or more control signals and a current source operable to charge at least one of the plurality of capacitors within the array. 
   Another aspect of the invention relates to a method for generating a ramp output using a ramp generator having an array of capacitors each controlled by a switch, the method comprising resetting the ramp output to a constant level, changing the ramp output at a rate of change corresponding to a least significant bit, and changing the ramp output at another rate of change corresponding to a another least significant bit. 
   Another aspect of the invention relates to an analog-to-digital converter comprising a ramp generator and a conversion circuit. The ramp generator comprises first and second operational amplifiers, the first operational amplifier having an input for receiving a first reference voltage, an input connected to at least one of a first current source, a first bias current source, and a first side of a first array of capacitors each controlled by a switch, and an output connected to a second side of the first array, the output operable to carry a falling ramp signal, and the second operational amplifier having an input for receiving a second reference voltage, an input connected to at least one of a second current source, a second bias current source, and a first side of a second array of capacitors each controlled by a switch, and an output connected to a second side of the second array, the output operable to carry a rising ramp signal. The conversion circuit comprises a differential amplifier operable to produce an amplified differential signal responsive to two or more input signals, a comparator operable to compare the amplified differential signal to the difference of the falling ramp signal and the rising ramp signal, and a logic circuit operable to produce a digital output responsive to the comparison completed by the comparator. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     To enable the present invention to be easily understood and readily practiced, the present invention will now be described for purposes of illustration and not limitation, in connection with the following figures wherein: 
       FIG. 1  is a simplified diagram of an analog-to-digital converter according to one embodiment. 
       FIG. 2  is a simplified diagram of the ramp generator of  FIG. 1  according to one embodiment. 
       FIG. 3  is a timing diagram for the ramp generator of  FIG. 2  according to one embodiment. 
       FIG. 4  is a simplified diagram of the ramp generator of  FIG. 1  according to an alternative embodiment. 
       FIG. 5  is a timing diagram for the ramp generator of  FIG. 4  according to an alternative embodiment. 
       FIG. 6  illustrates a simplified diagram of the ramp generator of  FIG. 1  according to another embodiment. 
       FIG. 7  illustrates a simplified diagram of a ramp generator according to another embodiment. 
       FIG. 7A  illustrates a simplified diagram of a digital conversion circuit according to one embodiment. 
       FIG. 8  is a simplified diagram of a feedback-type analog-to-digital converter according to the prior art. 
       FIG. 9  is a simplified diagram of a dual-slope analog-to-digital converter according to the prior art. 
       FIG. 10  is a simplified diagram of a flash analog-to-digital converter according to the prior art. 
       FIG. 11  is a simplified diagram of a charge-redistribution analog-to-digital converter according to the prior art. 
       FIG. 12  is a simplified diagram of a ramp generator and comparator for a digital ramp analog-to-digital converter according to the prior art. 
       FIG. 13  is a timing diagram for the ramp generator of  FIG. 12  according to the prior art. 
   

   DETAILED DESCRIPTION 
   The detailed description sets forth specific embodiments which are described in sufficient detail to enable those skilled in the art to practice the present invention. It should be apparent to those skilled in the art that other embodiments may be utilized, and that logical, mechanical, and electrical changes may be made, while remaining within the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the invention is defined only by the appended claims. 
     FIG. 1  is a simplified diagram of an analog-to-digital converter (ADC)  5  according to one embodiment. ADC  5  includes a comparator  8  and a ramp generator  10 . Comparator  8  receives an analog signal (V A ) at a first input and the ramp voltage (V ramp ) from the output of the ramp generator  10  at a second input. The ramp generator  10  utilizes an array of capacitors to produce the output signal V ramp  in response to a reference voltage (V ref ) and control signals (ctrl), among others. 
   In operation, the ramp generator  10  is first reset such that V ramp  is equal to V ref . The comparator  8  compares V A  to V ramp . If V A  is greater than V ramp , the output of the comparator  8  (V out ) is high and the control signals (ctrl) cause the ramp generator  10  to increase V ramp . If V ramp  is greater than V A , V out  goes low and the control signals (ctrl) cause the ramp generator  8  to stop increasing V ramp . The digital equivalent of the input signal V A  may be determined from the ramp generator&#39;s  10  settings at the time that V out  goes low. 
     FIG. 2  is a simplified diagram of the ramp generator  10  of  FIG. 1  according to one embodiment. Ramp generator  10  includes an array of capacitors (C 1 , C 2 , C 3 , . . . C n-1 ) each controlled by an associated switch (S 1 , S 2 , S 3 , . . . S n-1 ). Each switch is responsive to a corresponding control signal (ctrl 1 , ctrl 2 , ctrl 3 , . . . ctrl n-1 ). The ramp generator  10  may also include a reset switch (S rst ) responsive to a reset control signal (crtl rst ), a capacitor C n  (which in the current embodiment does not include a corresponding switch), and a current source  12 . The current source  12  includes a corresponding switch (S C ) which is responsive to a control signal (ctrl C ). The switch S C  enables/disables (e.g., connects/disconnects) the current source  12  relative to the array, reset switch S rst , and capacitor C n . 
   In the current embodiment, the capacitors (C 1 , C 2 , C 3 , . . . C n-1 , C n ) are matched. Using the current manufacturing techniques, the capacitors (C 1 , C 2 , C 3 , . . . C n-1 , C n ) can be matched within approximately 0.05% of each other. Accordingly, an ADC incorporating the ramp generator  10  illustrated in  FIG. 2  is more accurate than an ADC converter that incorporates prior art ramp generators (such as that shown in  FIG. 12 ). It should be apparent to one skilled in the art that improved manufacturing techniques may lead to improved matching of the capacitors while remaining within the scope of the present invention. 
     FIG. 3  is a timing diagram for the ramp generator  10  of  FIG. 2  according to one embodiment. Operation begins when the ramp generator  10  is reset by disabling the current source  12  and activating the reset switch S rst . Referring to  FIG. 3 , the ramp generator is reset when control signal ctrl C  is low (thus opening switch S C  and disabling current source  12 ) and control signal ctrl rst , is pulsed high (thus closing switch S rst ). In the current embodiment, the control signals ctrl 1 , ctrl 2 , ctrl 3 , . . . ctrl n-1  are all high at this time, thus capacitors (C 1 , C 2 , C 3 , . . . C n-1 ) are connected across the array. However, when switch S rst , is closed, the ramp generator output (V ramp ) is directly connected to V ref  such that the capacitors (C 1 , C 2 , C 3 , . . . C n-1 , C n ) are effectively short circuited. 
   After the ramp generator  10  is reset, control signal ctrl rst , goes low opening switch S rst . Control signal ctrl C  then goes high closing switch S C  and enabling the current source  12 . Current I flows from the current source  12  charging the capacitors (C 1 , C 2 , C 3 , . . . C n-1 , C n ) and causing V ramp  to rise at a constant rate, for example, as illustrated as the 1LSB (i.e., least significant bit) portion of the V ramp  curve in  FIG. 3 . The slope of the 1LSB portion of the V ramp  curve can be defined as: V ramp =I*t 1 /C T , where C T =C 1 +C 2 +C 3 + . . . C n-1 +C n , and C 1 =C T /2; C 1 +C 2 =2*C T /3; C 1 +C 2 +C 3 =3*C T /4, etc. 
   After t 1  seconds, control signal ctrl 1  goes low opening switch S 1  and disconnecting capacitor C 1  from the capacitor array. This changes the slope of the V ramp  curve at the breakpoint between the 1LSB and 2LSB portions of the V ramp  curve shown in  FIG. 3 . The slope of the 2LSB portion of the V ramp  curve can be defined as V ramp =I*(t 2 −t 1 )/(C T −C 1 ) or 2I*(t 2 −t 1 )/C T . 
   After t 2  seconds, control signal ctrl 2  goes low opening switch S 2  and disconnecting capacitor C 2  from the capacitor array. This changes the slope of the V ramp  curve at the breakpoint between the 2LSB and 3LSB portions of the V ramp  curve shown in  FIG. 3 . The slope of the 3LSB portion of the V ramp  curve can be defined as V ramp =I*(t 3 −t 2 )/(C T −C 1 −C 2 ) or 3I*(t 3 −t 2 )/C T . 
   At each break point, a capacitor is disconnected from the capacitor array changing the slope of the V ramp  curve. The remaining slopes may be defined in a manner similar to that discussed above, for example, the slope of the nLSB can be defined as V ramp =I*(t n −t n-1 )/(C n ) or nI*(t n −t n-1 )/C T . 
   In the current embodiment, the ramp generator output curve has a linear portion and a compressed portion. The linear portion of the ramp may be defined as V ramp =V ref +(I*t)/C T . The compressed portion includes a plurality of discrete segments. Each segment is defined by one or more programmable breakpoints. The location of the breakpoints may be programmed by setting the time intervals t 1 , t 2 , t 3 , . . . t n-1  as desired. The compressed portion of the ramp can be defined as V ramp =V ref +(I*t 1 )/C T +2I*(t 2 −t 1 )/C T +3I*(t 3 −t 2 )/C T + . . . +nI*(t n −t n-1 )/C T . 
     FIG. 4  is a simplified diagram of the ramp generator  10  of  FIG. 1  according to an alternative embodiment. As discussed above in conjunction with  FIG. 2 , the ramp generator  10  of the alternative embodiment includes an array of capacitors (C 1 , C 2 , C 3 , . . . C n-1 ) and associated switches (S 1 , S 2 , S 3 , . . . S n-1 ). Each switch is responsive to a corresponding control signal (ctrl 1 , ctrl 2 , ctrl 3 , . . . ctrl n-1 ). The ramp generator  10  of the alternative embodiment may also include a reset switch (S rst ) responsive to a reset control signal (crtl rst ), a capacitor C n  (which does not include a corresponding-switch), and a current source  12 . The current source  12  includes a corresponding switch (S C ) which is responsive to a control signal (ctrl C ). The switch S C  enables/disables (e.g., connects/disconnects) the current source  12  relative to the array, reset switch S rst , and capacitor C n . 
   In the current embodiment, the capacitors (C 1 , C 2 , C 3 , . . . C n-1 , C n ) are matched. Using the current manufacturing techniques, the capacitors (C 1 , C 2 , C 3 , . . . C n-1 , C n ) can be matched within approximately 0.05% of each other. Accordingly, an ADC incorporating the ramp generator  10  illustrated in  FIG. 4  is more accurate than an ADC converter that incorporates prior art ramp generators (such as that shown in  FIG. 12 ). It should be apparent to one skilled in the art that improved manufacturing techniques may lead to improved matching of the capacitors while remaining within the scope of the present invention. 
   The ramp generator  10  illustrated in  FIG. 4  also includes a second current source  14 . The current source  14  includes a corresponding switch (S p ) which is responsive to a control signal (ctrl p ). The switch S p  enables/disables (e.g., connects/disconnects) the current source  14  relative to the array, reset switch S rst , and capacitor C n . The current source  14  may be used to provide a pedestal function (i.e., a bias function), for example, to offset-cancel dark currents that are present in the CMOS sensors used in imaging applications. Dark currents refer, for example, to currents that leak through the transistors comprising the CMOS sensors used in imaging applications. 
     FIG. 5  is a timing diagram for the ramp generator  10  of  FIG. 4  according to the alternative embodiment. Generally, the ramp generator  10  illustrated in  FIG.4  functions in the same manner as the ramp generator  10  discussed above in conjunction with  FIG. 2 . However, in the alternative embodiment, the current source  14  is enabled for a time period t p  after the reset switch S rst  is deactivated, but prior to current source  12  being enabled. Current I p  flows from the current source  14  causing the output of the ramp generator (V ramp ) to increase from V ref  to V ref +V ped . It should be apparent to one skilled in the art that the value of V ped  is dependent upon I p  and t p . Thus, V ped  can easily be controlled to offset any dark currents. 
     FIG. 6  illustrates a simplified diagram of the ramp generator of  FIG. 1  according to another embodiment. As discussed above in conjunction with  FIG. 4 , the ramp generator  10  of the current embodiment includes an array of capacitors (C 1 , C 2 , C 3 , . . . C n-1 ) and associated switches (S 1 , S 2 , S 3 , . . . S n-1 ). Each switch is responsive to a corresponding control signal (ctrl 1 , ctrl 2 , ctrl 3 , . . . ctrl n-1 ). The ramp generator  10  of the current embodiment also includes a reset switch (S rst ) responsive to a reset control signal (crtl rst ), a capacitor C n  (which in the current embodiment does not include a corresponding switch), a current source  12 , and a current source  14 . The current source  12  includes a corresponding switch (S c ) which is responsive to a control signal (ctrl c ), whereas the current source  14  includes a corresponding switch (S p ) which is responsive to a control signal (ctrl p ). The-switches S c  and S p  enable/disable (e.g., connect/disconnect) the current sources  12  and  14 , respectively, relative to the capacitor array. Unlike the current sources illustrated in  FIGS. 2 and 4  which are illustrated as being supplied using V DD , the current sources illustrated in  FIG. 6  are supplied by a regulated voltage supply (V reg ). 
   Additionally, the ramp generator  10  illustrated in  FIG. 6  includes an operational amplifier  16 . In the current embodiment, the outputs of the current sources  12 ,  14 , one side of capacitor C n , one side of reset switch S rst , and one side of the capacitor array are connected to the negative input terminal of the op-amp  16 . The other side of capacitor C n , the other side of reset switch S rst , and the other side of the capacitor array are connected to the output of the op-amp  16 . A reference voltage (V ref ) is connected to the positive input terminal of the op-amp  16 . The op-amp  16  reduces the loading on the reference input voltage (V ref ) and provides a constant voltage across, and eliminates voltage dependence of, the current sources  12 ,  14 . 
   It should be apparent to one skilled in the art that the ramp generator  10  illustrated in  FIG. 6  is a single-slope ramp generator. It should further be apparent to one skilled in the art that the polarity of the ramp generator&#39;s output (i.e., V ramp  rising or falling) depends upon the direction of current flow through the current sources  12 ,  14 . For example, in the configuration illustrated in  FIG. 6 , the ramp generator&#39;s output falls as current flows from V reg  through current sources  12 ,  14 . 
     FIG. 7  illustrates a simplified diagram of the ramp generator  20  of  FIG. 1  according to another embodiment. The ramp generator  20  may be used, for example, in combination with a digital conversion circuit (such as that illustrated in  FIG. 7A ) to comprise a differential column-parallel analog to digital converter. The analog-to-digital converter discussed in the current embodiment uses a differential conversion technique to obtain a 12-bit digital code from analog input signal, for example, from a CMOS sensor used in an imaging application. 
   Referring to  FIG. 7 , the ramp generator  20  illustrated is a differential output ramp generator operable to produce two separate output voltages (i.e., V ramp     —     dn  and V ramp     —     up ). In the current embodiment, the ramp generator may be divided into two halves. 
   The first half, which may be referred to as a falling ramp portion  21 , includes an op-amp  16 ( 1 ), two current sources  12 ( 1 ),  14 ( 1 ), a variable capacitor CS 1 , and a reset switch S rst1 . In the current embodiment, the outputs of the current sources  12 ( 1 ),  14 ( 1 ) and one side of the variable capacitor CS 1 , and one side of reset switch S rst1  are connected to the negative input terminal of the op-amp  16 ( 1 ). The other side of the variable capacitor CS 1  and the other side of the reset switch S rst1  are connected to the output of the op-amp  16 ( 1 ). A reference voltage (V ref     —     hi ) is connected to the positive input terminal of the op-amp  16 ( 1 ). The falling ramp portion  21  of the ramp generator  20  produces the output signal V ramp     —     dn . 
   Initially, reset switch S rst1  is closed, thus discharging variable capacitor CS 1 . At the same time, the ramp output V ramp     —     dn  is reset to V ref     —     hi . Reset switch S rst1  is then released once the output V ramp     —     dn  is settled. The current source  14 ( 1 ) is then activated by closing switch S P1 using control signal Ctrl P . The current source  14 ( 1 ) supplies a current I P1  which introduces an offset value at the output V ramp     —     n  to offset-cancel any dark currents, for example, generated by an input sensor. After switch S P1  is opened, the ramping operation begins when current source  12 ( 1 ) is activated by closing switch S C1  using control signal Ctrl 1 . The current source  12 ( 1 ) supplies a current I 1 . The slope of the output ramp is constant up to the point when the variable capacitor CS 1  is adjusted at the required break point by switching out a fraction of the capacitor. The ramp output V ramp     —     dn  can be defined by the following equation: V ramp     —     dn =V ref     —     hi −(I P1 *t P )/CS 1 −(I 1 *t 1 )/CS 1 −2I 1 *(t 2 −t 1 )/CS 1 −3I 1 *(t 3 −t 2 )/CS 1 − . . . −nI 1 *(t n −t n-1 )/CS 1 . 
   It should be noted that the variable capacitor CS 1  may be implemented using an array of capacitors, for example, capacitors (C 11 , C 12 , C 13 , . . . C 1n-1 ) and associated switches (S 11 , S 12 , S 13 , . . . S 1n-1 ), each switch responsive to a corresponding control signal (ctrl 11 , ctrl 12 , ctrl 13 , . . . ctrl 1n-1 ). Accordingly, one skilled in the art should recognize that the falling ramp portion  21  of the ramp generator  20  illustrated in  FIG. 7  may be constructed and operated in a manner similar to the ramp generator  10  discussed above in conjunction with  FIG. 6 . 
   The second half, which may be referred to as a rising ramp portion  22 , includes an op-amp  16 ( 2 ), two current sources  12 ( 2 ),  14 ( 2 ), a variable capacitor CS 2 , and a reset switch S rst2 . In the current embodiment, the outputs of the current sources  12 ( 2 ),  14 ( 2 ), one side of the variable capacitor CS 2 , and one side of reset switch S rst2  are connected to the negative input terminal of the op-amp  16 ( 2 ). The other side of the variable capacitor CS 2  and the other side of reset switch S rst2  are connected to the output of the op-amp  16 ( 2 ). A reference voltage (V ref     —     lo ) is connected to the positive input terminal of the op-amp  16 ( 2 ). The rising ramp portion  22  of the ramp generator  20  produces the output signal V ramp     —     up . 
   Initially, reset switch S rst2  is closed, thus discharging variable capacitor CS 2 . At the same time, the ramp output V ramp     —     up  is reset to V ref     —     lo . Reset switch S rst 2  is then released once the output V ramp     —     up  is settled. The current source  14 ( 2 ) is then activated by closing switch S P2  using control signal Ctrl P . The current source  14 ( 2 ) supplies a current I P2  which introduces an offset value at the output V ramp     —     up  to offset-cancel any dark current, for example, generated by an input sensor. After switch SP 2  is opened, the ramping operation begins when current source  12 ( 2 ) is activated by closing switch S C2  using control-signal Ctrl 1 . The current source  12 ( 2 ) supplies a current I 2 . The slope of the output ramp is constant up to the point when the variable capacitor CS 2  is adjusted at the required break point by switching out a fraction of the capacitor. The ramp output V ramp     —     up  can be defined by the following equation: V ramp     —     up =V ref     —     lo +(I P2 *t P )/CS 2 +(I 2 *t 1 )/CS 2 +2I 2 *(t 2 −t 1 )/CS 2 +3I 2 *(t 3 −t 2 )/CS 2 + . . . +nI 2 *(t n −t n-1 )/CS 2 . 
   It should be noted that the variable capacitor CS 2  may be implemented using an array of capacitors, for example, capacitors (C 21 , C 22 , C 23 , . . . C 2n-1 ) and associated switches (S 21 , S 22 , S 23 , . . . S 2n-1 ), each switch responsive to a corresponding control signal (ctrl 21 , ctrl 22 , ctrl 23 , . . . ctrl 2n-1 ). Accordingly, one skilled in the art should recognize that the rising ramp portion  22  of the ramp generator  20  illustrated in  FIG. 7  may be constructed and operated in a manner similar to the ramp generator  10  discussed above in conjunction with  FIG. 6 , with the exception that for the rising ramp portion  22 , the non-inverting input of Op-Amp 2  is connected to a low reference voltage (i.e., V ref     —     lo ) and the current sources (i.e.,  12 ( 2 ),  14 ( 2 )) are supplied by a sinking regulated supply (i.e., V reg2 ). It should further be noted that the falling ramp portion  21  and the rising ramp portion  22  may be operated individually or simultaneously while remaining within the scope of the present invention. 
   Referring now to  FIG. 7A , the differential conversion circuit  200  receives the output signals V ramp     —     up  and V ramp     —     dn  from the differential ramp generator  20  illustrated in  FIG. 7 . The conversion circuit  200  includes a differential amplifier  216 , a two-stage AC-coupled comparator comprised of a differential comparator  234  and a second amplifier  246 , latching/RAM logic  248 , switches  202 ,  204 ,  214 ,  218 ,  220 ,  222 ,  232 ,  236 ,  242 ,  244 , capacitors  208 ,  210 ,  224 ,  226 ,  228 ,  230 ,  238 ,  240  and variable capacitors  206 ,  212 . 
   Operation of the differential column-parallel ADC is generally as follows. Analog signals V colr  and V cols  (e.g., from a CMOS image sensor) are input to the differential amplifier  216 . The difference between V colr  and V cols  is amplified by the differential amplifier  216 . This amplified differential signal is stored between nodes Nr and Ns. Simultaneously, the two-stage AC-coupled comparator  234 ,  246  is primed for action by biasing the inputs and outputs at ˜V DD /2 and V ref . This biasing is accomplished using switches  232 ,  236 , and  244 . During the analog-to-digital conversion, the amplified differential signal stored at nodes Nr and Ns is compared to the outputs from the differential ramp generator (i.e., V ramp     —     dn  and V ramp     —up   ). The latching/RAM logic  248  generates a  12 -bit code in response to the output of the two-stage AC-coupled comparator. In the current embodiment, for example, the latching/RAM logic  248  generates a 12-bit code if the differential ramp signal is greater than the amplified differential signal. 
   It should be apparent to those of ordinary skill in the art that equivalent logic or physical circuits may be constructed using alternate logic elements while remaining within the scope of the present invention. It should further be recognized that the above-described embodiments of the invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the scope of the following claims.