Abstract:
A Magnetic Tunnel Junction (MJT) Ternary Content Addressable Memory (TCAM) employing six transistors and exhibiting reduced standby leakage and improved area-efficiency. In the proposed TCAM, data can be written to the MJT devices by conventional current induced magnetization techniques and by controlling the source line, thereby eliminating the need for external writing circuitry.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to currently U.S. Provisional Application No. 62/171,476, entitled “A 6T-2 MTJ Ternary Content Addressable Memory”, filed Jun. 5, 2015 by the same inventors, the entirety of which is incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     This invention relates to content addressable memories. More specifically, the invention provides a magnetic tunnel junction (MTJ) based ternary content addressable memory (TCAM). 
     Brief Description of the Prior Art 
     Magnetic Tunnel Junction (MTJ) is a spintronic device which stores data in the form of spin of an electron, unlike a static Complementary Metal-Oxide-Semiconductor (CMOS) memory cell, which stores data in the form of electric potential. An MJT device consists of three layers—a layer of magnetic oxide sandwiched between two layers of magnetic material. Data is stored in the form of magnetization in the two magnetic material layers. A logic ‘0’ is stored when the two magnetic layers are magnetized in the same direction and a logic ‘1’ is stored when the two magnetic layers are magnetized in the opposite direction.  FIG. 1A  illustrates an MTJ device configuration in parallel and antiparallel states. 
     Pinned Layer (PL) magnetization exhibits a fixed magnetization, whereas Free Layer (FL) magnetization can be polarized parallel or anti-parallel with respect to the PL. In this context, it should be noted that the resistance of MTJ is high when PL and FL are in antiparallel configuration, whereas the resistance of MJT is low when PL an FL are parallel to each other. The value written to the MTJ depends on the direction and the strength of the charge current. The minimum current required to flip the state of the MTJ is called the critical current.  FIG. 1B  illustrates the directions charge current to write ‘1’ and ‘0’ to an MTJ device. 
     Tunnel Magneto Resistance (TMR) is the ratio of electrical resistances of the MTJ structure in parallel and antiparallel polarization states of FL relative to PL magnetization. If R H  is the MTJ resistance in an antiparallel state and R L  is the MTJ resistance in a parallel state, the TMR is defined as 
     
       
         
           
             TMR 
             = 
             
               
                 
                   R 
                   H 
                 
                 - 
                 
                   R 
                   L 
                 
               
               
                 R 
                 L 
               
             
           
         
       
     
     Content Addressable Memory (CAM) is widely used in pattern matching, internet data processing, packet forwarding, for tag bits storage in a processor cache, for associative memory and in many other fields where searching a specific pattern of data is a major operation. The special functionality of the content search in CAM requires a comparison circuitry integrated with the memory cell. The required comparator, in addition to the memory element itself, adds area and power overhead in CAMs. 
     CAMs can be divided into two categories depending on the number of states that can be stored in the memory cell, namely: binary CAM (BCAM) and ternary CAM (TCAM). BCAM stores a binary bit, namely ‘0’ and ‘1’, whereas TCAM can store three possible values, namely ‘1’, ‘0’, and ‘don&#39;t care’ (X). CAMs can be further categorized into two topologies, namely NOR and NAND type (see  FIGS. 1C-1D ). The stored bits are compared with the data on the search line (SL) and its complement (\SL) by XOR operation with the transistor network M 1 , M 2 , M 3 , and M 4 . To store data in a TCAM cell having a NOR-type architecture, data bit and the complement are stored in two SRAM cells. 
     The ‘don&#39;t care’ bit can be realized by storing ‘1’ in both SRAM cells, i.e., D=\D=1. In the case of a match, both SL-D and \SL-\D paths are disconnected, and the match line remains precharged. In the case of miss, either of the SL-D or \SL-\D connect ML to ground, which discharges the precharged ML. 
     In a NAND-type architecture, TCAM cells are connected in series. Data bit D and \D are derived from a single SRAM cell, unlike two SRAM cells in a NOR-type TCAM. The stored bit is masked by using a mask bit (M) in a parallel SRAM cell. 
     In case of match, the precharged ML is connected to ground by series TCAM cells of the word by turning the NMOS transistor M 1  ‘ON’. Storing the mask bit as ‘1’ enables transistor M 2 , despite match or miss, which implements ‘don&#39;t care’ functionality. CMOS TCAM uses two SRAM cells, thereby doubling the area overhead, compared to conventional SRAM cells. 
     However, conventional CAMs suffer from area, power, and speed limitations. As it pertains to TCAM, the need to store and match a ‘don&#39;t care’ matching state requires two storage bits, which further worsens the area overhead. CMOS CAM is power hungry due to power consumed in match line (ML), search line, and leakage of the bit cell. In nanometer technologies, leakage power constitutes a major portion of the total power consumed in CAM memory. Non-volatile technologies, which are more area efficient than status random-access memory (SRAM) and can provide zero leakage, are attractive in such a scenario. However, continued improvement of TCAM is needed. 
     Accordingly, what is needed is improved area efficiency and non-volatility using MTJ-based TCAM for on-chip CAM applications. However, in view of the art considered as a whole at the time the present invention was made, it was not obvious to those of ordinary skill in the field of this invention how the shortcomings of the prior art could be overcome. 
     While certain aspects of conventional technologies have been discussed to facilitate disclosure of the invention. Applicant in no way disclaims these technical aspects, and it is contemplated that the claimed invention may encompass one or more of the conventional technical aspects discussed herein. 
     The present invention may address one or more of the problems and deficiencies of the prior art discussed above. However, it is contemplated that the invention may prove useful in addressing other problems and deficiencies in a number of technical areas. Therefore, the claimed invention should not necessarily be construed as limited to addressing any of the particular problems or deficiencies discussed herein. 
     In this specification, where a document, act or item of knowledge is referred to or discussed, this reference or discussion is not an admission that the document, act or item of knowledge or any combination thereof was at the priority date, publicly available, known to the public, part of common general knowledge, or otherwise constitutes prior art under the applicable statutory provisions; or is known to be relevant to an attempt to solve any problem with which this specification is concerned. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, a Magnetic Tunnel Junction (MJT) Ternary Content Addressable Memory (TCAM) employing six transistors and exhibiting reduced standby leakage and improved area-efficiency is provided. In the proposed TCAM, data can be written to the MJT devices by conventional current induced magnetization techniques and by controlling the source line, thereby eliminating the need for external writing circuitry. 
     In one embodiment of the invention, a Magnetic Tunnel Junction (MJT) Ternary Content Addressable Memory (TCAM) cell is provided comprising, a first Magnetic Tunnel Junction (MTJ) device having a first node coupled to a search line, a second MTJ device having a first node coupled between to a complement search line, a first match line discharge transistor having a gate coupled to a second node of the first MTJ device and a second match line discharge transistor having a gate coupled to a second node of the second MTJ device. The TCAM cell further includes, a first word line selection transistor having a drain coupled to the gate of the first match line discharge transistor and the second node of the first MTJ device, a second word line selection transistor having a drain coupled to the gate of the second match line discharge transistor and to the second node of the second MTJ device, a write access transistor having a drain coupled to a source of the first word line selection transistor and to the source of the second word line selection transistor and a search enable transistor having a drain coupled to a source of the first word line selection transistor and to the source of the second word line selection transistor. 
     In a particular embodiment, the first MTJ device and the second MJT device include, a first magnetic layer having a pined magnetization direction, a second magnetic layer having a free magnetization direction and a magnetic oxide disposed between the first magnetic layer and the second magnetic layer. In the MJT devices, a logic state of a bit stored in the TCAM cell is represented by the relative resistance of the first MJT device and the second MJT device. 
     In the TCAM cell of the present invention, the threshold voltage of the first match line discharge transistor and the threshold voltage of the second match line discharge transistor are greater than a voltage at the second node of the first MJT device and a voltage at the second node of the second MJT device during a match condition. In addition, the threshold voltage of the first match line discharge transistor or the threshold voltage of the second match line discharge transistor is less than a voltage at the second node of the first MJT device and a voltage at the second node of the second MJT device during a mismatch condition. 
     In a particular embodiment of the TCAM cell, the write access transistor is sized to provide a drain current that is greater than a critical write current of the first MJT device and the second MJT device during a write operation. 
     In an additional embodiment of the TCAM cell, a low resistance value of the first MJT device and the second MJT device and a size of the search enable transistor are selected to provide a search current that is below a critical current of the first MJT device and the second MJT device and in addition, a high resistance value of the first MJT device and the second MJT device is determined by the Tunnel Magneto Resistance (TMR) of the TCAM cell. 
     In accordance with an additional embodiment of the present invention, a Ternary Content Addressable Memory (TCAM) device, comprising a plurality of TCAM cells in accordance with the TCAM cell of the present invention is provided. 
     In an additional embodiment, a method for operating a Magnetic Tunnel Junction (MJT) Ternary Content Addressable Memory (TCAM) cell is provided, which includes precharging a match line of the TCAM cell to positive voltage supply level, wherein the match line is coupled to a drain of a first match line discharge transistor and to a drain of a second match line transistor, and wherein a gate of the first match line discharge transistor is coupled to a second node of a first MJT device and a gate of the second match line discharge transistor is coupled to a second node of a second MJT device. The method of operating the TCAM cell further includes, providing a ground voltage supply level to a gate of a write access transistor and to a source line coupled to a source of the write access transistor and providing a positive voltage supply level to a gate of search enable transistor and to a gate of a first word line selection transistor and a gate of a second word line selection transistor, wherein a source of the search enable transistor is coupled to the source line and a drain of the search enable transistor is coupled to a source of the first match line discharge transistor and to a source of the second match line discharge transistor. The method further includes providing search data on a search line and on a complement search line to be compared against data stored in the first MJT device and in the second MJT device, where a first node of the first MJT device is coupled to the search line and a first node of the second MJT device is coupled to the complement search line and turning the first match line discharge transistor and the second match line discharge transistor OFF to maintain a charge on the precharged match line if the search data matches the data stored in the first MJT device and in the second MJT device, or turning the first match line discharge transistor and the second match line discharge transistor ON to discharge the precharged match line. 
     In a particular embodiment, the method of operating the TCAM further includes, writing the data stored in the first MJT device and in the second MJT device, prior to precharging the match line. Writing the data further includes, providing a ground voltage supply level to the gate of the search enable transistor to disable the search enable transistor, providing a positive voltage supply level to the gate of the write access transistor, wherein a drain of the write access transistor is coupled to a source of the first wordline selection transistor and to a source of the second wordline selection transistor and providing a positive voltage supply level to a first word line coupled to the gate of the first wordline selection transistor or to a second word line coupled to the gate of the second wordline selection transistor for a selected word and controlling the search line to write stored data in the first MJT device and in the second MJT device provided by the search line and the complement search line. 
     In a particular embodiment for writing a logic “1”, the method includes, providing a positive voltage supply level to the gate of the first wordline selection transistor and providing a ground voltage supply level to the gate of the second wordline selection transistor, providing a positive voltage supply level to the source line. The method of writing a logic “1” further includes, providing a ground voltage supply level to the search line to provide a write current to write an antiparallel state to the first MTJ device in the first cycle and providing a ground voltage supply level to the gate of the first wordline selection transistor, providing a positive voltage supply level to the gate of the second wordline selection transistor and providing a write current to write a parallel state to the second MTJ device, in a second cycle. 
     In an additional embodiment for writing a logic “0”, the method includes, providing a positive voltage supply level to the gate of the first wordline selection transistor and providing a ground voltage supply level to the gate of the second wordline selection transistor, providing a positive voltage supply level to the source line and to the complement search line. The method for writing a logic “0’ further includes, providing a ground voltage supply level to the search line to provide a write current from the search line to write a parallel state to the first MTJ device in a first cycle and providing a ground voltage supply level to the gate of the first wordline selection transistor, providing a positive voltage supply level to the gate of the second wordline selection transistor, providing a ground voltage supply level to the source line to providing a write current to write an antiparallel state to the second MTJ device, in a second cycle. 
     In a particular embodiment for writing logic “X”, the method includes, providing a positive voltage supply level to the gate of the first wordline selection transistor and to the gate of the second wordline selection transistor, providing a positive voltage supply level to the source line, and providing a ground voltage supply level to the search line and to the complement search line to provide a write current from the search line to write an antiparallel state to the first MTJ device and to write an antiparallel state to the second MTJ device, in the same cycle. 
     Accordingly, the TCAM cell and method of operation of the TCAM cell, in accordance with various embodiments of the present invention provides improved area efficiency and non-volatility using MTJ-based TCAM for on-chip CAM applications. These and other important objects, advantages, and features of the invention will become clear as this disclosure proceeds. 
     The invention accordingly comprises the features of construction, combination of elements, and arrangement of parts that will be exemplified in the disclosure set forth hereinafter and the scope of the invention will be indicated in the claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a fuller understanding of the invention, reference should be made to the following detailed description, taken in connection with the accompanying drawings, in which: 
         FIG. 1A  depicts MTJ devices in anti-parallel (‘1”) and parallel (‘0’) state. 
         FIG. 1B  depicts the directions of charge current to write ‘1’ and to write ‘0’. 
         FIG. 2  is a schematic diagram of a Ternary Content Addressable Memory (TCAM) cell, in accordance with an embodiment of the present invention. 
         FIG. 3  is a V gs  margin diagram illustrating best and worst V M  and V MM  with respect to V th0 , in accordance with an embodiment of the present invention. 
         FIG. 4A  is a schematic diagram illustrating an equivalent circuit during write operation of the TCAM cell, where MTJ resistance is R H  (D=‘1’) on the left side image and MTJ resistance is R L  (\D-‘0’) on the right side image, in accordance with an embodiment of the present invention. 
         FIG. 4B  is a schematic diagram illustrating an equivalent circuit during search operation of the TCAM cell, in accordance with an embodiment of the present invention. 
         FIG. 5  illustrates a waveform showing the search operation of the TCAM cell, in accordance with an embodiment of the present invention. 
         FIG. 6A  is a graphical illustration depicting width of transistor M 5  vs. sense margin and MTJ device current from SL for various R L  (TMR=100%), in accordance with an embodiment of the present invention. 
         FIG. 6B  is a graphical illustration depicting width of M 3 /M 4  vs. sense margin and search current for various R L , in accordance with an embodiment of the present invention. 
         FIG. 7  is a graphical illustration depicting ML sense margin and search current from search line with respect to the width of NMOS M 5  for different TMR values, in accordance with an embodiment of the present invention. 
         FIG. 8A  is a graphical illustration depicting the worst case sense margin from 10° C. to 90° C., for different word sizes, in accordance with an embodiment of the present invention. 
         FIG. 8B  is a graphical illustration depicting the worst case sense delay (for 50 mV sense margin development) from 10° C. to 90° C., for different word sizes, in accordance with an embodiment of the present invention. 
         FIG. 8C  is a graphical illustration depicting the worst Power Delay Product (PDP) per bit search from 10° C. to 90° C., for different word sizes, in accordance with an embodiment of the present invention. 
         FIG. 9A  is a graphical illustration of the sensitivity of the sense margin when the operating voltage is varied from 0.7V to 1.2V, in accordance with an embodiment of the present invention. 
         FIG. 9B  is a graphical illustration of the sensitivity of the sense delay when the operating voltage is varied from 0.7V to 1.2V, in accordance with an embodiment of the present invention. 
         FIG. 9C  is a graphical illustration of the sensitivity of the PDP per bit search when the operating voltage is varied from 0.7V to 1.2V, in accordance with an embodiment of the present invention. 
         FIG. 10A  is a graphical illustration of the worst case sense margin for different supply voltages at typical-typical (TT) corner, in accordance with an embodiment of the present invention. 
         FIG. 10B  is a graphical illustration of the worst case sense margin for different supply voltages at slow-slow (SS) corner, in accordance with an embodiment of the present invention. 
         FIG. 10C  is a graphical illustration of the worst case sense margin for different supply voltages at fast-fast (FF) corner, in accordance with an embodiment of the present invention. 
         FIG. 11A  is a graphical illustration of the results at 1V for the three PV corners for 256-bit word at different SE signal voltages, and 0 mV, 50 mV and 100 mV higher Vth, in accordance with an embodiment of the present invention. 
         FIG. 11B  is a graphical illustration of the sense margin across three PV corners with Vth implants at 850 mV supply voltage in accordance with an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings, which form a part thereof, and within which are shown by way of illustration specific embodiments by which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the invention. 
     As used in this specification and the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the content clearly dictates otherwise. As used in this specification and the appended claims, the term “or” is generally employed in its sense including “and/or” unless the context clearly dictates otherwise. 
     The present invention is directed to a non-volatile NOR type TCAM cell using MTJ devices. The TCAM employs only 6 transistors and 2 MTJ devices, instead of 16 transistors, as is commonly known in the current state of the art for CMOS TCAM devices. 
     With reference to  FIG. 2 , a Magnetic Tunnel Junction (MJT) Ternary Content Addressable Memory (TCAM) cell  200 , in accordance with an embodiment of the present invention includes, a first Magnetic Tunnel Junction (MTJ) device  205  having a first node coupled to a search line  200  and a second MTJ device  210  having a first node coupled between to a complement search line  225 . The TCAM cell further includes, a first match line discharge transistor  230  having a gate coupled to a second node of the first MTJ device  205  and a second match line discharge transistor  235  having a gate coupled to a second node of the second MTJ device  210 . The TCAM cell additionally includes, a first word line selection transistor  265  having a drain coupled to the gate of the first match line discharge transistor  230  and the second node of the first MTJ device  205  and a second word line selection transistor  270  having a drain coupled to the gate of the second match line discharge transistor  235  and to the second node of the second MTJ device  210 . The TCAM cell further includes a write access transistor  245  having a drain coupled to a source of the first word line selection transistor  265  and to the source of the second word line selection transistor  270  and a search enable transistor  240  having a drain coupled to a source of the first word line selection transistor  265  and to the source of the second word line selection transistor  270 . As shown in  FIG. 2 , the first match line discharge transistor  230  further includes a drain coupled to a match line  215  and a source coupled to a source line  260  and wherein the second match line discharge transistor  235  further includes a drain coupled to the match line  215  and a source coupled to the source line  260 . In addition, a gate of the first word line selection transistor  265  is coupled to a first word line  275  and a gate of the second word line selection transistor  270  is coupled to a second word line  277 . 
     In order to enable writing to the first MJT device  205  and the second MJT device  210 , a gate of the write access transistor  245  is coupled to a write signal  255  and a source of the write access transistor is coupled to the source line  260 . In order to enable searching of the first MJT device  205  and the second MJT device  210 , a gate of the search enable transistor  240  is coupled to a search enable signal  250  and a source of the search enable transistor  240  is coupled to the source line  260 . 
     In operation of the TCAM cell  200  illustrated in  FIG. 2 , the two (2) MTJ devices  205 ,  210  store data D and complement data \D, respectively. Match line discharge transistors M 1   230  and M 2   235  form a match line (ML) discharge network to discharge a precharged match line  215 , depending upon the result of a data comparison with the search lines SL  220  and \SL  225 . During a search, transistors M 3   265  and M 5   240  and M 4   270  and M 5   240 , along with the MTJs  205 ,  210 , form a voltage divider network in which the drain voltages of M 3   265  and M 4   270  drive the gates of discharge transistors M 1   230  and M 2   235 , respectively. 
     The TCAM cell of the present invention is designed in such a way that during a match condition, the voltage of node X 1  at the gate of discharge transistor M 1   230  and the voltage of node X 2  at the gate of discharge transistor M 2   235  are below the threshold voltage of M 1   230  and M 2   235 , and as such, the match line (ML)  215  remains precharged. However, during a mismatch condition, the voltage of X 1  rises above the threshold of M 1   230  or the voltage of X 2  rises above the threshold voltage of M 2   235 , thus discharging the match line  215 . 
     Transistor M 3   265  and M 4   270  are the wordline (WL 1  and WL 2 ) selection transistors, and transistor M 6   245  is the write access transistor that turns ON only during a write (WR) operation. Transistor M 6   245  can be sized larger to allow sufficient write current. Transistor M 5   240  is driven by Search Enable (SE) signal  250  and is sized to limit the MTJ  205 ,  210  current to provide a read disturb free search operation. The ‘don&#39;t care’ bit can be stored in the cell by storing ‘1’ in both D and \D bits. The search bit can be masked by driving SL=\SL=0 on the search lines  220 ,  225 . The Source Line (SrL)  260  is used for two purposes, namely (1) write operation when the SrL  260  is connected to 0 or V dd  depending on the write data to the MTJs  205 ,  210 ; and (2) search operation when SrL  260  is driven to 0 to allow voltage division. 
     In the TCAM cell of the present invention, two match cases exist, namely (1) (D, \D)=(SL, \SL)=(1, 0); and (2) (D, \D)=(SL, \SL)=(0, 1). Since both cases are substantially similar, only the first case is explained herein. For (D, \S)=(1, 0), the left side MTJ  205  is in high resistance (R H ) state whereas the right side MTJ  210  is in low resistance (R L ) state. Since (SL, \SL)=(1, 0), the voltage at node X 1  is 
               V     X   ⁢           ⁢   1       =         V   sl     *     r       R   H     +   r         =     V   M             
and the voltage at node X 2  is 0. In this expression, r is the lumped ON resistance of transistors M 3   265  and M 5   240 , and V st  is SL voltage. To keep transistor M 1   230  OFF during match, V X1  should be lower than V th0  (i.e., the threshold voltage of M 1   230  and M 2   235 ).
 
     For the mismatch there are two cases, namely (1) (D, \D)=(1, 0) and (SL, \SL)=(0, 1); and, (2) (D, \D)=(0, 1) and (SL, \SL)=(1, 0). For the first case, the voltage at node X 1  is 0, whereas voltage at X 2  is 
               V     X   ⁢           ⁢   2       =         V     \   ⁢   sl       *     r       R   L     +   r         =     V   MM             
where V \sl  is \SL voltage. To keep transistor M 2   235  ON during mismatch, V H  should be higher than V th0 . Similar analysis applies to the 2 nd  case as well.
 
     From the above equations V MM &gt;V M  for the two cases as R H &gt;R L . For the design to function properly (i.e., discharge ML during a mismatch condition at a higher speed compared to that of a match condition), R H , R L , and r should be selected such that V M &lt;V th0 &lt;V MM . The following analytical equations can be used to quantify the design parameters. 
     
       
         
           
             
               
                 
                   
                     V 
                     MM 
                   
                   = 
                   
                     
                       
                         V 
                         dd 
                       
                       - 
                       
                         
                           I 
                           MM 
                         
                         * 
                         
                           R 
                           L 
                         
                       
                     
                     = 
                     
                       
                         
                           V 
                           
                             \ 
                             ⁢ 
                             sl 
                           
                         
                         * 
                         
                           r 
                           
                             
                               R 
                               L 
                             
                             + 
                             r 
                           
                         
                       
                       = 
                       
                         
                           V 
                           
                             th 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             0 
                           
                         
                         + 
                         
                           Δ 
                           1 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     
       
         
           
             
               
                 
                   
                     V 
                     M 
                   
                   = 
                   
                     
                       
                         V 
                         dd 
                       
                       - 
                       
                         
                           I 
                           M 
                         
                         * 
                         
                           R 
                           H 
                         
                       
                     
                     = 
                     
                       
                         
                           V 
                           sl 
                         
                         * 
                         
                           r 
                           
                             
                               R 
                               H 
                             
                             + 
                             r 
                           
                         
                       
                       = 
                       
                         
                           V 
                           
                             th 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             0 
                           
                         
                         - 
                         
                           Δ 
                           2 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
     IMM and IM are the currents drawn from SL and \SL in case of mismatch and match, respectively, and Δ 1 , Δ 2  are the offset voltages with respect to V th0 . Subtracting Eqs. (1) and (2) and using RH=RL*(1+TMR), the following is obtained: 
     
       
         
           
             
               
                 
                   
                     
                       V 
                       MM 
                     
                     - 
                     
                       V 
                       M 
                     
                   
                   = 
                   
                     
                       
                         V 
                         dd 
                       
                       ⁡ 
                       
                         ( 
                         
                           
                             r 
                             
                               
                                 R 
                                 L 
                               
                               + 
                               r 
                             
                           
                           - 
                           
                             r 
                             
                               
                                 R 
                                 H 
                               
                               + 
                               r 
                             
                           
                         
                         ) 
                       
                     
                     = 
                     
                       
                         Δ 
                         1 
                       
                       + 
                       
                         Δ 
                         2 
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     
       
         
           
             
               
                 
                   
                     
                       V 
                       MM 
                     
                     - 
                     
                       V 
                       M 
                     
                   
                   = 
                   
                     
                       
                         V 
                         dd 
                       
                       ⁡ 
                       
                         ( 
                         
                           
                             
                               rR 
                               L 
                             
                             ⁢ 
                             TMR 
                           
                           
                             
                               ( 
                               
                                 
                                   R 
                                   L 
                                 
                                 + 
                                 r 
                               
                               ) 
                             
                             ⁢ 
                             
                               ( 
                               
                                 
                                   
                                     R 
                                     L 
                                   
                                   ⁡ 
                                   
                                     ( 
                                     
                                       1 
                                       + 
                                       TMR 
                                     
                                     ) 
                                   
                                 
                                 + 
                                 r 
                               
                               ) 
                             
                           
                         
                         ) 
                       
                     
                     = 
                     
                       
                         Δ 
                         1 
                       
                       + 
                       
                         Δ 
                         2 
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     As such, the TCAM cell in accordance with the present invention an be optimized using three primary approaches: (1) maximizing the difference between mismatch and match voltages i.e., (Δ 1 +Δ 2 ); (2) maximizing the absolute values of offsets from V th0 , i.e., |Δ 1 | and |Δ 2 | to keep M 1 /M 2  strongly ON or OFF as needed during mismatch and match, respectively, and (3) lowering the search current below critical write current of MTJ. 
     From Eq. (4), it can be concluded that higher TMR, higher R H , and higher r can be employed to enhance (Δ 1 +Δ 2 ). Although higher r and R L  is also good for maximizing Δ 1 , it minimizes Δ 2 . A lower Δ 2  can turn ON M 1 /M 2  during match, degrading the sense margin.  FIG. 3  illustrates a V gs  margin diagram illustrating the best and worst V M  and V MM  with respect to V th0 . 
     The voltages V MM1 , V MM3 , V M1  and V M3  provide poor sense margin compared to V MM2  and V M2 , even with the same magnitude of Δ 1 +Δ 2 . The ideal margin is obtained when R H =∞ and R L =0, which gives V MM =V dd  and V M =0. However, a lower R L  could be detrimental for read disturb due to the resulting high search current conditions. High values of R H  and R L  ensure low search line currents. This, in combination with high TMR can provide better V gs  margin, i.e., (Δ 1 +Δ 2 ) with low search power consumption. 
     In the TCAM of the present invention  200 , the search lines SL  220  and \SL  225  are used to write data to the MTJ devices  205 ,  210 . Table 1 summarizes the states of the control signals in the write operation. Writing ‘1’ and ‘0’ requires two cycles to write to the two MTJs  205 ,  210  while ‘X’ can be written in a single cycle. During a write the ML precharge is disabled to avoid power consumption from the ML  215 . This is achieved by pulling the ‘precharge’ signal high. NMOS transistor M 6   245  is turned ON during write by WR signal  255 . Note that M 6   245  is sized to provide a drain current greater than the critical write current of the MTJ devices  205 ,  210 . The search enable signal SE  250  is pulled to ground which disables transistor M 5   240 . The WL x  is turned ON only for the selected word so that the unselected cells are unaffected. The source line SrL  260  is controlled appropriately to write a ‘1’ or ‘0’. 
       FIG. 4A  illustrates the equivalent circuit of the TCAM cell during write to /D bit. The transistors are replaced with equivalent ON resistances. Resistors r 3 , r 4  and, r 6  are equivalent resistors of M 3   265 , M 4   270  and M 6   245 , respectively. The writing operation is described below. In the first cycle, writing to D bit is enabled by pulling WL 1   275  to V dd  and path to \D is disabled by pulling WL 2   277  to ground. In the second cycle of write operation, writing to \D bit is enabled by pulling WL 2   277  to V dd  and D bit path is disabled by pulling WL 1   275  to ground. 
     
       
         
               
             
               
               
             
               
               
               
             
               
               
               
               
               
               
               
             
               
               
               
               
               
             
               
               
             
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 States of control signals TCAM memory operations 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 Write operation: WR = V dd , SE = 0 
               
             
          
           
               
                   
                 Write D bit 
                 Write \D bit 
               
               
                   
                 WL1 = V dd ,WL2 = 0 
                 WL1 = 0,WL2 = V dd   
               
             
          
           
               
                   
                 SL 
                 \SL 
                 SrL 
                 SL 
                 \SL 
                 SrL 
               
               
                   
               
               
                 Write ‘1’ 
                 0 
                 X 
                 V dd   
                 X 
                 V dd   
                 0 
               
               
                 Write ‘0’ 
                 V dd   
                 X 
                 0 
                 X 
                 0 
                 V dd   
               
             
          
           
               
                 Write ‘X’ 
                 0 
                 0 
                 V dd   
                 WL1 = WL2 = V dd   
               
               
                   
               
             
          
           
               
                   
                 Search operation: WL1 = WL2 = V dd ,  
               
               
                   
                 WR = 0, SE = V dd   
               
             
          
           
               
                   
                 SL 
                 \SL 
                 SrL 
               
               
                   
               
               
                 Search ‘1’ 
                 V dd   
                 0 
                 0 
               
               
                 Search ‘0’ 
                 0 
                 V dd   
                 0 
               
               
                 Search ‘X’ 
                 0 
                 0 
                 0 
               
               
                   
               
             
          
         
       
     
     1. Writing ‘1’: In the first cycle, SrL  260  is pulled high and SL  220  line is pulled to ground. The write current flows from SL  220  writing antiparallel state to the first MTJ device  205  storing bit D. There is no current through the other MTJ device  210  as the WL 2   277  control signal is at zero potential. In the second cycle the SrL  260  is held high, SL  220  is pulled to V dd  and \SL  225  is pulled low which programs the second MTJ device  210 , storing \D to parallel state. There is no current through the other MTJ  205  as SL  220  and SrL  260  are both high. 
     2. Writing ‘0’: In the first cycle, the SrL  260  and \SL  225  are pulled high and the SL  220  line is pulled low. The first cycle writes parallel magnetization state to MTJ storing D bit. In the second cycle, the SrL  260  is pulled low while retaining the states of SL  220  and \SL  225  at 0 and \V dd , respectively, which programs the \D bit to antiparallel state. 
     3. Writing ‘X’: The ‘X’ state can be stored by writing logic 1 to both D and \D. Both the word lines WL 1   275  and WL 2   277  are pulled high. The SrL  260  is pulled to V dd  and the search lines SL  220  and \SL  225  are pulled to ground. The current flows through both the MTJ devices  205 ,  210  storing antiparallel states to D and \D. 
     In the TCAM cell of the present invention, search is a single cycle operation. The ML  215  is precharged to V dd  and WR  255  is pulled to ground. The SrL  260  is pulled to ground throughout the search operation. Next, SE  250 , WL 1   275  and WL 2   277  are pulled high to enable the conducting path through M 5   240 , M 3   265  and M 4   270  (Table 1). Either V MM  or V M  voltage is developed depending on the match or mismatch, respectively, at the gate of M 1   230  or M 2   235 . The search line SL  220  is pulled to Vdd and complement search line \SL  225  is pulled low to search a logic ‘1’. Similarly, SL  220  is pulled low an, \SL  225  is pulled to Vdd to search for logic ‘0’. Both SL  220  and \SL  225  are pulled low to search ‘X’. Circuit operation in match and mismatch cases are discussed below.  FIG. 4B  shows the equivalent circuit during search operation. 
     1. Match: Let (D, \D)=(SL, \SL)=(1, 0). Voltages V X     1    and V X     2    are given by 
     
       
         
           
             
               V 
               
                 X 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 1 
               
             
             = 
             
               
                 V 
                 dh 
               
               = 
               
                 
                   V 
                   dd 
                 
                 * 
                 
                   
                     
                       r 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       3 
                     
                     + 
                     
                       r 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       5 
                     
                   
                   
                     
                       R 
                       H 
                     
                     + 
                     
                       r 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       3 
                     
                     + 
                     
                       r 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       5 
                     
                   
                 
               
             
           
         
       
       
         
           
             
               V 
               
                 X 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 2 
               
             
             = 
             
               
                 V 
                 dl 
               
               = 
               
                 
                   V 
                   dd 
                 
                 * 
                 
                   
                     
                       r 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       5 
                     
                     + 
                     
                       R 
                       L 
                     
                   
                   
                     
                       ( 
                       
                         
                           R 
                           H 
                         
                         + 
                         
                           r 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           3 
                         
                         + 
                         
                           r 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           5 
                         
                       
                       ) 
                     
                     ⁢ 
                     
                       ( 
                       
                         
                           r 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           4 
                         
                         + 
                         
                           r 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           5 
                         
                       
                       ) 
                     
                   
                 
               
             
           
         
       
     
     It should be noted that V X2  is less than V X1  and appears due to the potential across r 5  which results in a current though R L  even when \SL=0. The transistors M 3   265  and M 5   250  are sized such that V X1 &lt;V th0 . So M 1   230  and M 2   235  are turned OFF and the ML  215  remains precharged. The other match case i.e., (D, \D)=(SL, \SL)=(0, 1) is similar. 
     2. Mismatch: Let (D, \D)=(1, 0) and (SL, \SL)=(0, 1). Then, 
     
       
         
           
             
               V 
               
                 X 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 1 
               
             
             = 
             
               
                 V 
                 dl 
               
               = 
               
                 
                   V 
                   dd 
                 
                 * 
                 
                   
                     
                       r 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       4 
                     
                     + 
                     
                       r 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       5 
                     
                   
                   
                     
                       R 
                       L 
                     
                     + 
                     
                       r 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       4 
                     
                     + 
                     
                       r 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       5 
                     
                   
                 
               
             
           
         
       
       
         
           
             
               V 
               
                 X 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 2 
               
             
             = 
             
               
                 V 
                 dh 
               
               = 
               
                 
                   V 
                   dd 
                 
                 * 
                 
                   
                     
                       r 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       5 
                     
                     + 
                     
                       R 
                       H 
                     
                   
                   
                     
                       ( 
                       
                         
                           R 
                           H 
                         
                         + 
                         
                           r 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           3 
                         
                       
                       ) 
                     
                     ⁢ 
                     
                       ( 
                       
                         
                           R 
                           L 
                         
                         + 
                         
                           r 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           4 
                         
                         + 
                         
                           r 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           5 
                         
                       
                       ) 
                     
                   
                 
               
             
           
         
       
     
     V d1  (mismatch)&gt;V th0 &gt;V dh  (match). Under these conditions both M 1   230  and M 2   235  are turned ON to discharge the precharged ML  215  which provides better sense margin. 
       FIG. 5  illustrates the ML  215  voltages during search operation for the TCAM cell of varied word sizes, namely 1, 16, 128 and 256-bit for match and mismatch. Predictive 22 nm model is used for simulations. The waveforms correspond to the worst case sense margin (i.e., single miss in the whole word). The rate of discharge of ML line  215  in match case increases with the word size due to the increased number of cells leaking the ML current through weakly driven M 1   230  and M 2   235 . This in turn limits the sense margin for larger word sizes. 
     The low MTJ resistance and sizing of the sense enable transistor M 5   240  are chosen to keep the search current below the critical current while providing a sufficient V gs  to drive M 1   230  and M 2   235  in order to differentiate the miss and match cases. The high MTJ resistance is determined by the Tunnel Magneto Resistance (TMR). 
     The write access transistor M 6   255  is sized to provide greater than critical current to the MTJ during write operation. A range of R L  (5 k to 9 k) was simulated with fixed TMR of 100%. The trend is shown in the  FIG. 6A , for a 16-bit word. It can be observed from the plot that high resistance values with smaller NMOS widths provide good sense margin (close to V dd /2) with lower MTJ current from the search line. Based on this, R L =8 kΩ is selected for the current design. The MTJ current during mismatch is also plotted. It should be noted that mismatch current is always greater than the match current, and thus it was considered for estimating the worst case read disturb during search operation. 
     Width of the NMOS devices M 3   265 , M 4   270  and M 5   240  are important parameters to ensure low search current and reduce the power dissipated from the search lines. The plot in the  FIG. 6A  shows the distribution of MTJ current for various widths of the NMOS device M 5   240  with different R L  values. Smaller width of NMOS devices offers higher resistance, reduces search current (good for lower read disturb and power) and also improves the sense margin. However, minimum sized transistor can be susceptible to manufacturing process variations. 
     In an exemplary embodiment, a width of 50 nm was selected for M 5   240  for the low search current and process variation tolerance, respectively. It can be observed from the plot in  FIG. 6A  that miss case current is highly dependent upon the width of the M 5  NMOS device  240  and remains almost the same for different R L  values. In this embodiment, high R L  is selected to keep the TMR within practical limits, 100%-150%. To determine the optimal size of transistors M 3   265  and M 4   270 , the size was swept and the sense margin and sense current was observed for 50 nm M 5   240  width, as illustrated in  FIG. 6B . It is evident from the plot of  FIG. 6B  that the sense margin increases sharply from 50 nm up to 200 nm. After 200 nm, improvement in the sense margin saturates. Also, the search current increases by approximately 10× with increase in the width by 25 nm. Thus, in an exemplary embodiment, the width of M 3   365  and M 4   270  was selected to be 200 nm. 
       FIG. 7  illustrates the trend of match current and sense margin versus width of NMOS M 5   240  for different TMR values. The R L  of MTJ is fixed to 8 K for this analysis and TMR and R H  are selected for low match case search current and higher sense margin. It can be seen that higher TMR ensures better sense margin and low MTJ match current with fixed R L . It can be seen from the plot of  FIG. 7  that the NMOS width does not affect the MTJ current compared to that in the miss case because of the fact that the MTJ high resistance R H  dominates the effective NMOS resistance of M 3   365 , M 4   270  and M 5   240 . This also results in low drain voltage at M 3   365  and M 4   270  compared to that in the mismatch case. So, the width of the NMOS devices is selected based on the mismatch current drawn from the SL, while the TMR is chosen to satisfy the match case conditions. It can be noted that the sense margin benefit of a TMR greater than 125% saturates. Hence, TMR=125% has been used and provides less than 45 μA of match current with a sense margin close to 500 mV. 
     Resistance of an MTJ device is shown to depend upon oxide thickness and surface area of free layer. Therefore by tuning these parameters it is possible to obtain an MTJ device resistance of R L =8 kΩ. Similarly, it has been experimentally shown that TMR could be improved up to 236%. This can be used during design time to ensure TMR=125% for proper functioning of the current TCAM cells. 
     To simulate the results of the exemplary TCAM cell of the present invention, TMR=125% was used with R L =8 kΩ, 50 nm M 5  transistor  240  and 200 nm M 3   365  and M 4   270  transistors. MTJ models were selected with 29 nm×22 nm×3 nm free layer dimension and 0.876 nm oxide (MgO) thickness for design simulations. Word size of 16, 32, 64, 128 and 256-bit was simulated to analyze the design with respect to process, temperature and voltage variations. 
     The worst case sense margin, sense delay (for 50 mV sense margin development) and the Power Delay Product (PDP) per bit search from 10° C. to 90° C. are shown in  FIGS. 8A-8C  for different word sizes. A single bit mismatch is considered for sense margin and sense delay as it is the worst case condition. The sense delay increases proportionally as the word size due to increment in ML interconnect capacitance. As the temperature increases, the rate of ML  215  discharge increases due to lowering of threshold voltage of the discharge transistors M 1   230  and M 2   235 . 
     Sense margin decreases with temperature due to ML  215  discharge through subthreshold leakage current of discharge transistors in the match case. Therefore, the sense delay (for 50 mV sense margin) increases as the temperature increases. The PDP is proportional to the change in sense delay while the operating voltage and the search line current are similar across different temperatures. From  FIGS. 8A-8C , a reliable sense margin of greater than 50 mV across the range of temperature till 256-bit word size was obtained. 
     In this exemplary embodiment, the operating voltage is varied from 0.7V to 1.2V to observe the sensitivity of sense margin, sense delay and PDP per bit search, as illustrated in  FIGS. 9A-9C . A 50 mV sense development time is used to measure the sense delay. Below 0.7V the sense margin of 256-bit CAM word is less than 50 mV. Sense margin and sense delay are sensitive to V dd  due to lowering of gate voltage of M 1   230  and M 2   235 , while their threshold voltages remain fixed. At lower voltages the M 1   230  and M 2   235  transistors fail to turn ON, or weakly conduct, even during mismatch, thereby degrading the sense margin (especially for wider words). Sense delay for a 256-bit TCAM word varies from 124 ps at 1.2V to 2.098 ns at of 0.7V (sense delay is plotted in log 10 scale). The increase in the sense delay results in a sharp increase in the PDP, at 0.7V. 
     For process variation analysis of the exemplary embodiment, fast-fast (FF), slow-slow (SS), and typical-typical (TT) corners were considered. The process variation was modeled by lumping the variation in channel length, oxide thickness, flat band conditions, etc., into threshold voltage of the transistor. The SS (FF) is simulated by adding (subtracting) 150 mV from nominal threshold voltage. The worst case sense margin is plotted for different supply voltages at TT, SS and FF corners, as shown in  FIGS. 10A-10C . It can be observed that the embodiment of the TCAM cell can provide a reliable sense margin of above 50 mV at all corners till 0.75V for 128-bit words or less. The poor sense margin at lower voltages is linked with poor V gs  across M 1   230  and M 2   235  that keeps the ML  215  precharged, even in mismatch conditions. 
     The 256-bit word fails to provide adequate sense margin in FF corner at 1V. This is primarily due to poor Δ 2  when V th0  moves down coupled with leakage from the match bits, as shown in  FIG. 4 . Thus, bit match and mismatch bits leak, thereby degrading the sense margin. As such, threshold voltage modulation and search enable (SE) voltage boosting or underdrive was shown to improve sense margin for 256-bit word simulations. 
     In order to solve the poor sense margin, V th0 , Δ 1  and Δ 2  were modulated by exploring threshold voltage modulation of transistor M 1   230  and M 2   235  (to tune V th0 ) and SE  250  voltage modulation (to tune Δ 1  and Δ 2 ).  FIG. 11A  illustrated the results at 1V for the three PV corners for 256-bit word at different SE signal voltages, and 0 mV, 50 mV and 100 mV higher V th . Change in the gate drive of M 3   265  and M 4   270  changes their ON resistance and results in corresponding change in Δ 1  and Δ 2 . It can be noted that an optimum choice of SE can improve the sense margin. Moreover, repositioning of V th0  can improve the sense margin even further.  FIG. 11B  illustrates the sense margin across three PV corners with V th  implants at 850 mV supply voltage. It can be noted that V th  modulation can improve the worst case sense margin significantly (FF and SS in this case) even though the sense margin in TT corner is degraded. The improvement results from decreased match case current through M 1   230  and M 2   235  at SS and the reverse effect in miss case at FF. At the same time lower SE increases the resistance of M 3 /M 4  which in turn increases Δ 2 . As expected, the sense margin in FF with V th  implant is comparable to TT corner without implant. With 100 mV V th  implant the design can provide a reliable sense margin of above 40 mV in all the PV corners, even without SE modulation. A 150 mV SE under-drive can improve the sense margin at TT to more than 120 mV and a 250 mV SE under-drive can improve the sense margin at FF to more than 50 mV. 
     TCAM cell currently known in the art consist of 16 transistors while the TCAM cell in accordance with the present invention, includes only 6 NMOS transistors and 2 MTJ devices, which results in a device that is 127% more area-efficient. 
     For power comparison, the CMOS TCAM in the prior art was implemented and simulated using 22 nm predictive model. The leakage power of the TCAM cell of the present invention is zero while SRAM TCAM consumes a considerable amount of standby power. In the mostly OFF applications, such as “Internet of Things” and smartphone, the TCAM cell of the present invention could be quite beneficial compared to CMOS CAM. While the search power consumption of the TCAM cell of the present invention is higher compared to CMOS TCAM currently known in the art, due to the search line current (—51 uA in case of a mismatch at IV) drawn to generate a secondary voltage at the drain terminals of M 3   265  and M 4   270 , which enables the discharge transistors of ML  215 . The search line current can be reduced further by selecting MTJ devices with high R L  and high TMR. The power consumption during search operation of ‘1’ and ‘0’ bits at 0.8V in MTJ device based TCAM is observed to be up to 80% higher in the worst case (successful search of ‘1’) compared to NOR type CMOS TCAM currently known in the art. Table 2 summarizes the power consumption during search operation of ‘1’, ‘0’ and ‘X’ bits at 1V and 0.8V. 
     
       
         
               
             
               
               
               
               
               
             
               
               
               
               
               
             
           
               
                 TABLE 2 
               
             
             
               
                   
               
               
                 Power (in μW) comparison of CMOS and current TCAM. 
               
             
          
           
               
                   
                 Match 
                 Miss 
                 Search ‘X’ from 
                 Search ‘X’ with 
               
               
                   
                 1/0 
                 1/0 
                 SL, /SL = 0 
                 D=/D = 1 
               
               
                   
               
             
          
           
               
                 CMOS V dd  = 0.8 V 
                 0.3 
                 2.03 
                 1.03 
                 0.2403 
               
               
                 Current V dd  = 0.8 V 
                 24.84 
                 23.8 
                 0.6 
                 22.39 
               
               
                 Current V dd  = 1 V 
                 43.07 
                 53.3 
                 1.02 
                 41.25 
               
               
                   
               
             
          
         
       
     
     A spintronic TCAM was disclosed herein and can be seen to be promising for zero standby leakage and area-efficiency, thus improving the functioning of the CAM and overall computing system. Detailed analysis was conducted in the presence of process, voltage, and temperature variations for a wide range of word sizes. As such, it is shown that, the TCAM cell design can operate with reliable sense margin up to 128-bit word size till 0.7V. Threshold voltage modulation and search enable underdrive were also discussed herein to improve sense margin for 256-bit word. The TCAM cell of the present invention is 127% area-efficient compared to conventional CMOS TCAM and 33-50% area efficient compared to other spintronic CAMs. 
     All referenced publications are incorporated herein by reference in their entirety. Furthermore, where a definition or use of a term in a reference, which is incorporated by reference herein, is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply. 
     The advantages set forth above, and those made apparent from the foregoing description, are efficiently attained. Since certain changes may be made in the above construction without departing from the scope of the invention, it is intended that all matters contained in the foregoing description or shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense. 
     It is also to be understood that the following claims are intended to cover all of the generic and specific features of the invention herein described, and all statements of the scope of the invention that, as a matter of language, might be said to fall therebetween.