Abstract:
Provided is a method, a system and a computer product to translate electronic schematic files between computer-aided software design tools. One embodiment of the invention includes converting source files, containing electronic schematic information, into output files. Creating, from the source files, export files that omit a sub-portion of the schematic information, defining omitted data, each of the export files having a file name associated therewith. Appending, to the file name of the export files, data concerning the omitted information to form an appended file name. The export files are converted to the output files retained in the appended file name. The appended name is diminished so as to remove all information therefrom, excepting information corresponding to the omitted information.

Description:
[0001]    The present invention relates to integrated circuit development, and more specifically to translation of electronic schematic files between computer aided software design tools.  
           [0002]    Computer-aided design of integrated circuits typically occurs in a multi-tool environment and may be generally divided into a front-end design phase and a back-end development phase, as shown in FIG. 1. During the front-end phase, the engineer user designs and develops, from a set of specifications, a logical representation of the integrated circuit of interest in the form of a schematic, at step  10 . The schematic is then entered into a computing platform to generate a circuit netlist, at step  12 . To that end, the computing platform includes computing hardware and one or more software tools, e.g., software applications. The netlist defines the entire integrated circuit, including all components and interconnections. Alternatively, the integrated circuit information may be developed using hardware description language (HDL) and synthesis. With the aid of integrated circuit test tools available to the computing platform, the user tests the design of the integrated circuit, at step  14 . For example, the operation of the integrated circuit design may be emulated. The integrated circuit design test process may involve several iterations of design modifications and improvements until the integrated circuit design is finalized.  
           [0003]    The back-end development involves several steps during which a final circuit layout (physical description) is developed based on the schematic. During placement step  16 , various building blocks (or cells) as defined by the finalized integrated circuit schematic are placed within a predefined floor plan. For integrated circuit designs based on array or standard cell technology, the various circuit building blocks are typically predefined. As a result, each cell may correspond to one or more electrical functions, e.g., resistor, capacitor, differential operational amplifier, J-K flip-flop and the like. Placement is followed by a routing step  18 , during which interconnects between cells are routed throughout the layout. Finally, the accuracy of the layout versus the schematic is verified at step  20 . To that end, the design rules are verified by calling a file on the server that tests the different aspects of the integrated circuit design against different design criteria. For example, the electrical performance of the electrical functions corresponding to the cells employed may be tested. Were no errors or design rule violations found, at step  22 , the circuit layout information would be used for the process of fabrication at step  24 .  
           [0004]    As standard in the computing industry, a wide variety of computing software tools to design integrated circuits exists. Often, the data generated by one software tool is not compatible for use with other software tools. For example, the Composer Tool format from Cadence Design Systems is not compatible with Mentor Graphics GDT format. As a result, considerable time and effort is required to translate, or convert, data between software tools.  
           [0005]    To facilitate data conversions, software tools are designed to interpret data in one or more common formats that may be interpreted by all computing software tools, albeit not efficiently. An example of a common format is the electronic design interchange format (EDIF). In this manner, data exchange between first and second software tools occurs through the common format. For example, a first software tool converts data from a first domestic format, which is interpreted by the first software tool, to the common format. A second computing platform then interprets the common format data and converts the same to a second domestic format for interpretation by the second software tool.  
           [0006]    Many utility applications exist that allow data conversions between two different software tools. However, many of these utility applications do not accurately convert the entire contents of data files. A need exists; therefore, to provide a method, and system and a computer product, to facilitate translation of electronic schematic files between computer-aided integrated circuit software design tools without losing information in the translation.  
         SUMMARY OF THE INVENTION  
         [0007]    The present invention provides a method, a system and a computer product to translate electronic schematic files between computer-aided software design tools. One embodiment of the invention includes converting source files, containing electronic schematic information, into output files. Creating, from the source files, export files that omit a sub-portion of the schematic information, defining omitted data, with each of the export files having a file name associated therewith. Appending, to the file name of the export files, data concerning the omitted information to form an appended file name. The export files are converted to the output files and retain the appended file name. The appended name is diminished so as to remove all information therefrom, excepting information corresponding to the omitted information. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]    [0008]FIG. 1 is a flow diagram of a process for designing integrated circuits in accordance with the prior art;  
         [0009]    [0009]FIG. 2 is a block diagram of a computing platform in accordance with the present invention;  
         [0010]    [0010]FIG. 3 is a plan view of multiple files employed during translation, in accordance with one embodiment of the present invention;  
         [0011]    [0011]FIG. 4 is a plan view showing an example of electronic schematic information and the corresponding export information that is created when translating the electronic schematic information, in accordance with an exemplary embodiment of the present invention;  
         [0012]    [0012]FIG. 5 is a plan view of randomly generated rip_cell names that is associated with a rip_cell shown in FIG. 4;  
         [0013]    [0013]FIG. 6 is a plan view of appended rip_cell names that include net_identification information, in accordance with one embodiment of the present invention;  
         [0014]    [0014]FIG. 7 is a plan view of appended rip_cell names that include an export identifier and net_identification information, in accordance with an alternate embodiment of the present invention; and  
         [0015]    [0015]FIG. 8 is a flow diagram of a method for translating electronic schematic information in accordance with one embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0016]    Referring to FIG. 2, a typical computing platform  26  in accordance with the present invention includes one or more system buses  28  placing various components thereof in data communication. For example, a microprocessor  29  is placed in data communication with both a read only memory (ROM)  30  and a random access memory (RAM)  31  via system bus  28 . ROM  30  contains among other code, the Basic Input-Output system (BIOS) that controls basic hardware operation such as the interaction with peripheral components such as disk drives  32  and  33 , as well as the keyboard  34 .  
         [0017]    RAM  31  is the main memory into which the operating system and application programs are loaded and affords at least 32 megabytes of memory space. A memory management chip  36  is in data communication with system bus  28  to control direct memory access (DMA) operations. DMA operations include passing data between the RAM  31  and the hard disk drive  32  and the floppy disk drive  33 .  
         [0018]    Also in data communication with system bus  28  are various I/O controllers: a keyboard controller  38 , a mouse controller  40 , a video controller  42 , and an audio controller  44 , which may be connected to one or more speakers  45 . Keyboard controller  38  provides a hardware interface for keyboard  34 , and mouse controller  40  provides a hardware interface for a mouse  46 , or other point and click device. Video controller  42  provides a hardware interface for a display  48 . A Network Interface Card (NIC)  50  enables data communication over the network facilitating data transmission speeds up to 1000 megabytes per second. The operating system  52  of computing platform  26  may be UNIX, LINUX, DOS, WINDOWS-based or any known operating system.  
         [0019]    Referring to FIGS. 2, 3 and  4 , a software tool translator  54  is loaded in RAM  31  to facilitate translation of source file  60  containing electronic schematic information  61  to an output file  62  via an intermediate export file  64 . Source file  60  is in a first domestic file format that may be interpreted by a software design tool,  66 , loaded in RAM  31 . Export file  62  is in a second domestic file format that may be interpreted by a software design tool,  68 , loaded in RAM  31 . Software design tool  68  is not capable of interpreting source file  60 , and software design tool  66  is not capable of interpreting output file  62 . To that end, the translation between source file  60  and output file  62  occurs via export file  64 . To that end, export file  64  is in a common format, such as EDIF, that may be interpreted by both design tools  66  and  68 .  
         [0020]    Referring to FIG. 4, electronic schematic information includes data concerning cells/electrical functions  70 ,  72  and  74 , and wire interconnect information of the cells  70 ,  72  and  74  to each other and other components (not shown) of the integrated circuit. As shown, the interconnect information includes net_identification, shown as “adr”, as well as the wire identification, e.g., &lt;0,1,2&gt;, &lt;0&gt;, &lt;1&gt; and &lt;2&gt;. Other information, not shown, is included in the interconnect information, such as any electrical signals contained on the interconnects, the duty cycle of the signals, the frequency and the like.  
         [0021]    Referring to FIGS. 3 and 4, a problem solved by the present invention concerns the loss of electronic schematic information during the translation between source file  60  and export file  64 . Specifically, translation from a mentor graphics “GDT” format to EDIF results in much of the remaining information contained in source file  60  being included in export information  63 , such as data concerning cells  70 ,  72  and  74 , as well as information concerning the wire identification e.g. &lt;0,1,2&gt;, &lt;0&gt;, &lt;1&gt; and &lt;2&gt;. Other data concerning the interconnect information resides in a rip_cell file  75 . Rip_cell  75  appears at the junction of a plurality of interconnections.  
         [0022]    Referring to FIGS. 2, 3,  4  and  5 , as a result of the translation of electronic schematic information  61  for the entire integrated circuit design to export information  63 , a set  175  of rip_cells is produced, each of which is associated with a name  76  randomly generated by the translation tool  54 . However, net_identification information is omitted entirely from the export information  63  contained in export file  64 . Without net_identification information the interconnect configuration of the cells  70 ,  72  and  74  would be difficult, if not impossible, to reconstruct once export file  64  had been translated to output file  62  in the Composer Tool format.  
         [0023]    Referring to FIGS. 3, 4 and  6 , to ensure that the net_identification associated with the interconnect information is translated to output file  62 , rip_cell  75  is analyzed to determine the net_identification associated with the wires that are connected thereto. The net_identification is deduced by examining the properties of each of the interconnects for which rip_cell  75  contains information. Once the net_identification has been determined, the name of rip_cells  176  have information appended thereto, defining an appended name, to identify the net corresponding to the wire information contained by rip_cell  75 . Appended name includes the randomly generated name portion  176   a  and the appended portion  176   b , which in this case consists of the net_identification information. After creation of appended names  176 , export information  63 , which now includes a set  276  of rip cells  75  with appended names  176 , is translated to output file  62 . Thereafter, appended name  176  is diminished so that only the appended portion  176   b  remains in the name of rip_cell  75 , e.g., the net_identification information.  
         [0024]    Referring to FIGS. 4, 6 and  7 , to associate each of the rip_cells  75  with the appropriate net_identification, it is desired to ensure that appended portion  176   b  consists of a sequence of characters that are not present in the randomly generated portion  176   a . To that end, another embodiment of appended name  376  may include additional identifier information, referred to herein as export identifier  376   c . Export identifier  376   c  is included in appended name  376 , in addition to the randomly generated name  376   a  and net_identification information  376   b . Export identifier  376   c  identifies appended name as having net_identification information appended thereto, and is selected so that the sequence character set does not coincide with the sequence of any character set present in the randomly generated name  376   a . In addition, the number of characters employed to create export identifier  376   c  is minimized to reduce the computational requirements for translation. Specifically, once appended name  376  has been generated for rip-cells  75 , translation from EDIF to composer is undertaken. The appended names  376  are then parsed. Appended names  376  are identified and the randomly generated portion  376   a  and export identifier  376   c  are removed, leaving the net_identification information.  
         [0025]    Referring to FIGS. 3, 4,  6 ,  7  and  8 , in operation at step  400  provided is a plurality of source files that contain electronic schematic information  61  in a domestic format, for example, GDT. At step  402 , a plurality of export files  64 , each containing export information  63 , is created from source files  60  by translation of electronic schematic information  61  to a common format, for example EDIF. The translation results in the omission of certain information from one or more of the export files  64 . In this example, the omitted information is net_identification information associated with interconnect information contained in rip_cell  75 . At step  404 , each of the names of rip_cells  75  of each export file  64  is compared to the net_identification information present among the various export files. At step  406 , it is determined whether there exists a common sequence of characters among one of the rip_cell names and the net_identification information. Were this the case, then the process would commence at step  408 . Otherwise, the process would proceed to step  410 . At step  408 , export identifiers  376   c  are generated and appended to the names of rip_cells  75  included in export files  64 . The export identifier  376   c  consists of a sequence of characters that would not be present in any of the randomly generated names of rip_cells  75 . Thereafter, as step  412 , the plurality of export files  64  is translated to another domestic format, for example composer format, forming a plurality of output files  62 . At step  414 , the rip_cell names in the output files  62  are parsed and the rip_cell names having export identifiers are identified. The file name of at least some, if not all of rip_cells  75  associated with export identifiers have the file name diminished to remove all information, excepting the net_identification information  376   b , at step  416 .  
         [0026]    At step  410 , net_identification information  376   b  would be generated and appended to the names of the rip_cells  75 . Specifically, net_identification  376   b  is appended to the name of the rip_cells  75  associated with the export files  64 . Thereafter, at step  418 , the plurality of export files  64  are translated to another domestic format, for example composer format, forming a plurality of output files  62 . At step  420 , the output files  62  are parsed and the names of rip_cells  75  are parsed and the file names of the rip_cells including net_identification information  376   b  are identified. The file name of the rip_cells  75  associated with these export files  62  are diminished to remove all information, excepting the net_identification information  376   b , at step  422 .  
         [0027]    Although the foregoing has been discussed with respect to integrated circuit design testing, it should be understood that the present invention may be employed in any type of computer file translations. Further, export identifiers may include information other than the presence of net_identification information that is appended to a rip_cell name. For example, the export identifiers may indicate that net_identification information is appended to a name of a rip_cell  75 , but that the rip_cell is not to be renamed to include the net_identification information once translated into output file  62 . Thus, the embodiments of the present invention described above are exemplary and the scope of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims along with their full scope of equivalents.