Abstract:
An energy-saving circuit for a motherboard includes a connecting circuit, a control circuit, a power circuit, an audio circuit, and a south bridge circuit. The connecting circuit can be connected to a number of audio devices, or may be unconnected to an audio device. A first detecting signal to the control circuit is output by the connecting circuit when an audio device is connected, and a second detecting signal is output by the connecting circuit when no audio device is connected. The power circuit powers the audio circuit according to the first control signal, and provides no power according to the second control signal. The south bridge chip allows audio communication for the first control signal, and prevents audio communication for the second control signal.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to energy-saving circuits, and particularly to an energy-saving circuit for a motherboard. 
         [0003]    2.Description of Related Art 
         [0004]    Many high-power chips, such as an audio chip arranged on the motherboard, will consume electrical energy even when the audio chip is not being used, which is a waste of energy. Therefore, there is room for improvement in the art. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]    Many aspects of the embodiments can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. 
           [0006]      FIG. 1  is a block diagram of an embodiment of an energy-saving circuit for a motherboard. 
           [0007]      FIGS. 2 and 3  are circuit diagrams constituting the energy-saving circuit of  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0008]    The disclosure, including the accompanying drawings, is illustrated by way of examples and not by way of limitation. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean “at least one.” 
         [0009]      FIG. 1  shows an embodiment of an energy-saving circuit  100 . The energy-saving circuit  100  is arranged on a motherboard and includes a connecting circuit  10 , a control circuit  20 , a power circuit  30 , an audio circuit  40 , and a south bridge chip  50 . The connecting circuit  10  is connected to a plurality of audio devices, such as an earphone, a microphone, or a Moving Picture Experts Group audio layer III (MP3) device. The connecting circuit  10  outputs a first detecting signal (such as a digital-high signal) to the control circuit  20  when the connecting circuit  10  is not connected to any audio device, or the connecting circuit  10  will output a second detecting signal (such as a digital-low signal) to the control circuit  20  when the connecting circuit  10  is connected to at least one audio device. The control circuit  20  outputs a first control signal to the power circuit  30  and the south bridge chip  50  according to the first detecting signal. The power circuit  30  provides a voltage to the audio circuit  40  when the power circuit  30  receives the first control signal. The south bridge chip  50  controls the audio circuit  40  to communicate with the audio device which is connected to the connecting circuit  10 , when the south bridge chip  50  receives the first control signal. The control circuit  20  outputs a second control signal to the power circuit  30  and the south bridge chip  50  according to the second detecting signal. When the power circuit  30  receives the second control signal, the power circuit  30  does not provide a voltage to the audio circuit  40 . The south bridge chip  50  controls the audio circuit  40  to not operate when the south bridge chip  50  receives the second control signal. 
         [0010]    Referring to  FIGS. 2 and 3 , the connecting circuit  10  includes connectors J 1 -J 3 , capacitors C 1 -C 6 , inductors L 1 -L 6 , and resistors R 1 -R 8 . In one embodiment, the connectors J 1 -J 3  are respectively connected to an earphone  202 , an MP3 device  204 , and a microphone  206 . Pin  1  of the connector J 1  is grounded through the inductor L 2  and the resistor R 2 , connected in series. A node between the inductor L 2  and the resistor R 2  is connected to the audio circuit  40  and a first end of the resistor R 4 . A second end of the resistor R 4  is connected to the audio circuit  40 . Pin  2  of the connector J 1  is grounded through the inductor L 1  and the resistor R 1 , connected in series. A node between the inductor L 1  and the resistor R 1  is connected to the audio circuit  40  and a first end of the resistor R 3 . A second end of the resistor R 3  is connected to the audio circuit  40 . The capacitor C 1  is connected between the pin  1  of the connector J 1  and ground. The capacitor C 2  is connected between the pin  2  of the connector J 1  and ground. Pin  3  of the connector J 1  is connected to the control circuit  20 . Pins  4  and  5  of the connector J 1  are grounded. 
         [0011]    Pin  1  of the connector J 2  is grounded through the inductor L 4  and the resistor R 5 , connected in series. A node between the inductor L 4  and the resistor R 5  is connected to the audio circuit  40 . Pin  2  of the connector J 2  is grounded through the inductor L 3  and the resistor R 6 , connected in series. A node between the inductor L 3  and the resistor R 6  is connected to the audio circuit  40 . Pin  3  of the connector J 2  is connected to the control circuit  20 . Pin  4  of the connector J 2  is grounded. The capacitor C 3  is connected between the pin  1  of the connector J 2  and ground. The capacitor C 4  is connected between the pin  2  of the connector J 2  and ground. 
         [0012]    Pin  1  of the connector J 3  is grounded through the inductor L 6  and the resistor R 8 , connected in series. A node between the inductor L 6  and the resistor R 8  is connected to the audio circuit  40 . Pin  2  of the connector J 3  is grounded through the inductor L 5  and the resistor R 7  connected in series. A node between the inductor L 5  and the resistor R 7  is connected to the audio circuit  40 . Pin  3  of the connector J 2  is connected to the control circuit  20 . Pin  4  of the connector J 2  is grounded. The capacitor C 5  is connected between the pin  1  of the connector J 3  and ground. The capacitor C 6  is connected between the pin  2  of the connector J 3  and ground. 
         [0013]    The control circuit  20  includes buffers U 1 -U 3 , capacitors C 7 -C 9 , resistors R 9 -R 13 , and five electronic switches Q 1 -Q 5 . In the embodiment, the electronic switches Q 1 -Q 3  and Q 5  are n-channel field effect transistors (FETs), and the electronic switch Q 4  is an npn transistor Q 4 . An input terminal of the buffer U 1  is connected to the pin  3  of the connector J 1 . An output terminal of the buffer U 1  is grounded through the capacitor C 7  and is also connected to a gate of the FET Q 1 . A source of the FET Q 1  is grounded. A drain of the FET Q 1  is connected to a source of the FET Q 2 . A gate of the FET Q 2  is connected to an output terminal of the buffer U 2  and also grounded through the capacitor C 8 . An input terminal of the buffer U 2  is connected to the pin  3  of the connector J 2 . A drain of the FET Q 2  is connected to a source of the FET Q 3 . A gate of the FET Q 3  is connected to an output terminal of the buffer U 3  and also grounded through the capacitor C 9 . An input terminal of the buffer U 3  is connected to the pin  3  of the connector J 3 . A drain of the FET Q 3  is connected to a base of the transistor Q 4 . The base of the transistor Q 4  is grounded through the resistor R 10  and also connected to a power source  3 V 3  through the resistor R 9 . An emitter of the transistor Q 4  is grounded. A collector of the transistor Q 4  is connected to a gate of the FET Q 5  and also connected to a power source  12 V through the resistor R 11 . A drain of the FET Q 5  is connected to a power source  5 V through the resistor R 12 . A source of the FET Q 5  is connected to the power circuit  30  and also grounded through the resistor R 13 . The source of the FET Q 5  is also connected to an input terminal of the south bridge chip  50 . An output terminal of the south bridge chip  50  is connected to the audio circuit  40 . 
         [0014]    The power circuit  30  includes four electronic switches Q 6 -Q 9 , resistors R 14 -R 16 , and capacitors C 10 -C 14 . In the embodiment, the electronic switches Q 6 -Q 9  are n-channel FETs. A gate of the FET Q 6  is connected to the source of the FET Q 5 . A source of the FET Q 6  is grounded. A drain of the FET Q 6  is connected to a gate of the FET Q 7  and also connected to the power source 12V through the resistor R 14 . A drain of the FET Q 7  is connected to a power source +5VA. A source of the FET Q 7  is connected to the audio circuit  40 . The capacitor C 10  is connected between the source of the FET Q 7  and ground. The capacitor C 11  is connected to the capacitor C 10  in parallel. A gate of the FET Q 8  is connected to the source of the FET Q 5 . A source of the FET Q 8  is grounded. A drain of the FET Q 8  is connected to a gate of the FET Q 9  and also connected to the power source  12 V through the resistor R 15 . A drain of the FET Q 9  is connected to a power source +3 — 3V AUX. A source of the FET Q 9  is connected to a first end of the resistor R 16 . A second end of the resistor R 16  is connected to the audio circuit  40 . The capacitor C 12  is connected between the second end of the resistor R 16  and ground. The capacitors C 13  and C 14  are connected to the capacitor C 12  in parallel. 
         [0015]    The audio circuit  40  includes an audio chip U 11  and capacitors C 15 -C 22 . A control pin CTL of the audio chip U 11  is connected to the output terminal of the south bridge chip  50 . Voltage pins DV 1  and DV 2  of the audio chip U 11  are connected to the second end of the resistor R 16 . Voltage pins AV 1  and AV 2  of the audio chip U 11  are connected to the source of the FET Q 7 . An input output (I/O) pin OUT 1  of the audio chip U 11  is connected to a node between the inductor L 5  and the resistor R 7  through the capacitor C 15 . An I/O pin OUT 2  of the audio chip U 11  is connected to a node between the inductor L 6  and the resistor R 8  through the capacitor C 16 . I/O pins MIC 1  and MIC 2  of the audio chip U 11  are respectively connected to the second ends of the resistors R 3  and R 4 . An I/O pin NC 5  of the audio chip U 11  is connected to a node between the inductor L 3  and the resistor R 6  through the capacitor C 17 . An I/O pin NC 4  of the audio chip U 1  is connected to a node between the inductor L 4  and the resistor R 5  through the capacitor C 18 . An I/O pin MIC 11  of the audio chip U 11  is connected to the first end of the resistor R 3  through the capacitor C 19 . An I/O pin MIC 22  of the audio chip U 11  is connected to the first end of the resistor R 4  through the capacitor C 20 . Ground pins DS 1 , DS 2 , AS 1 , and AS 2  of the audio chip U 11  connect to ground. A ground pin VREF of the audio chip U 11  is grounded through the capacitor C 21 . The capacitor C 22  is connected to the capacitor C 21  in parallel. 
         [0016]    In use, because pins of the audio devices corresponding to the pins  3  of the connectors J 1 -J 3  are grounded, when the connectors J 1 -J 3  are connected to the audio devices, the pins  3  of the connectors J 1 -J 3  output low level signals. When the connectors J 1 -J 3  are not connected to the audio devices, the pins  3  of the connectors J 1 -J 3  output high level signals. 
         [0017]    When the connectors J 1 -J 3  are connected to the audio devices, the FETs Q 1 -Q 3  are turned off. When the connector J 1  is not connected to the audio device, and the connectors J 2  and J 3  are connected to the audio devices, the FET Q 1  is turned on, and the FETs Q 2  and Q 3  are turned off. When the connector J 2  is not connected to the audio device, and the connectors J 1  and J 3  are connected to the audio devices, the FETs Q 1 -Q 3  are turned off. When the connectors J 1  and J 2  are not connected to the audio devices, and the connector J 3  is connected to the audio device, the FETs Q 1  and Q 2  are turned on, and the FET Q 3  is turned off. When the connectors J 1  and J 2  are connected to the audio devices, and the connector J 3  is not connected to the audio device, the FETs Q 1 -Q 3  are turned off. When the connectors J 1  and J 3  are not connected to the audio devices, and the connector J 2  is connected to an audio device, the FET Q 1  is turned on, and the FETs Q 2  and Q 3  are turned off. When the connector J 1  is connected to an audio device, and the connectors J 2  and J 3  are not connected to audio devices, the FETs Q 1 -Q 3  are turned off. Accordingly, the FET Q 4  always receives a high level signal and is turned on. The FET Q 5  always receives a low level signal and is turned off. The gates of the FETs Q 6  and Q 8  are at low level through the resistor R 13 . The FETs Q 6  and Q 8  are turned off. The FETs Q 7  and Q 9  are turned on. The audio chip U 11  receives voltages from the power source +5VA and +3 — 3V AUX through the voltage pins DV 1 , DV 2 , AV 1 , and AV 2 . At the same time, the input terminal of the south bridge chip  50  receives low level signals from the gates of the FETs Q 6  and Q 8  and controls the audio chip U 11  to communicate with the audio devices, which are connected to the connectors J 1 -J 3 . Essentially, when at least one of the connectors J 1 -J 3  is connected to an audio device, the audio chip U 11  operates to enable communication with the audio device. 
         [0018]    When the connectors J 1 -J 3  are not connected to any audio devices, the FETs Q 1 -Q 3  are turned on, the FET Q 4  receives a low level signal from the drain of the FET Q 3  and is turned off. The FET Q 5  is turned on. The gates of the FETs Q 6  and Q 8  receive high level signals from the power source 5V through the FET Q 5  and are turned on. The FETs Q 7  and Q 9  are turned off. The audio chip U 11  does not receive any voltage through the voltage pins DV 1 , DV 2 , AV 1 , and AV 2 . At the same time, the input terminal of the south bridge chip  50  receives the high level signal from the gates of the FETs Q 6  and Q 8  and controls the audio chip U 11  to not operate. Essentially, when the connectors J 1 -J 3  are not connected to any audio devices, the audio chip U 11  does not operate, and thus energy saving is realized. 
         [0019]    The energy-saving circuit  100  receives detecting signals from the connectors J 1 -J 3  through the control circuit  20  and outputs control signals to the power circuit  30  and the south bridge chip  50 , to make the audio chip U 11  operate when one of the connectors J 1 -J 3  is connected to an audio device, or to make the audio chip U 11  not operate when the connectors J 1 -J 3  are not connected to any audio devices. 
         [0020]    The foregoing description of the embodiments of the disclosure has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of everything above. The embodiments were chosen and described in order to explain the principles of the disclosure and their practical application so as to enable others of ordinary skill in the art to utilize the disclosure and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those of ordinary skills in the art to which the present disclosure pertains without departing from its spirit and scope. Accordingly, the scope of the present disclosure is defined by the appended claims rather than by the foregoing description and the exemplary embodiments described therein.