Abstract:
Circuitry for preventing damage to differentially coupled input JFETs in an integrated circuit amplifier includes first (J 2 ) and second (J 4 ) differentially coupled input JFETs. A first input signal (Vin+) is applied to a gate of the first input JFET (J 2 ), and second input signal (Vin−) is applied to a gate of the second input JFET. Needed amounts of drain current are supplied to the first and second input JFETs. A separator JFET (J 1 ) having a drain coupled to a source of the first input JFET and a source coupled to the source of the second input JFET is operated to control an amount of electrical isolation between the drain and source of the separator JFET so as to limit an amount of reverse bias voltage across a gate-source junction of one of the first and second input JFETs to a value less than a gate-source junction breakdown voltage of that the first and second input JFETs.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]     This application is a continuation-in-part of commonly assigned patent application Ser. No. 11/353,186 filed on Feb. 13, 2006, entitled “Differential Amplifier with Over-Voltage Protection and Method ”, by Alenin et al., and incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     The present invention relates generally to amplifiers, particularly to input stages for high-voltage operational amplifiers which are subject to high differential voltages, and more particularly to such input stages which utilize low voltage differential input transistors.  
         [0003]     The design of conventional differential amplifiers is well known. A typical input stage includes one or more pairs of differentially coupled input JFETs (unction field effect transistors) and associated current sources. For high voltage amplifier design, so-called high voltage transistors, which have high breakdown voltage parameters that are not exceeded during normal circuit operation, are typically used as the input transistors in order to accommodate high input voltages to which the input transistors may be subjected. So-called “low-voltage transistors” have lower breakdown voltage parameters which can be exceeded by internal node voltages in the integrated circuit input stage. For example, in some integrated circuit manufacturing processes, low-voltage N-channel JFETs can be damaged by a relatively low gate-to-source low breakdown voltage of 10 volts. High-voltage transistors usually have higher threshold voltage, higher parasitic capacitances, etc., than low-voltage transistors. The higher threshold voltages, high parasitic capacitances, etc., limit the design flexibility and the amplifier performance parameters such as bandwidth, slew rate, settling time.  
         [0004]     Referring to  FIG. 1 , a conventional input circuit  1  includes input conductors  2  and  3  to which input voltages Vin +  and Vin − , respectively, are applied. Conductor  2  is coupled by input resistor R 1  to conductor  5 , which is connected to the gate of a low-voltage N-channel JFET J 0 , the anode of a clamp diode D 0 , and the cathode of a clamp diode D 2 . Conductor  3  is coupled by input resistor R 0  to conductor  6 , which is connected to the gate of a low-voltage N-channel JFET J 1 , the anode of a clamp diode D 3 , and the cathode of a clamp diode D 1 . The sources of input JFETs J 0  and J 1  are coupled by conductor  4  to a tail current source I 1 . The drain of input transistor J 0  is connected by conductor  7  to the emitter of an NPN cascode transistor Q 3 . The drain of input transistor J 1  is connected by conductor  8  to the emitter of an NPN cascode transistor Q 4 . The bases of cascode transistors Q 3  and Q 4  are coupled to a bias voltage. The collector of cascode transistor Q 3  is connected by conductor  9  to the base and collector of a PNP current mirror input transistor Q 5 , the emitter of which is coupled to V DD . The collector of cascode transistor Q 4  is connected by an output conductor  10  to the collector of a PNP current mirror output transistor Q 6 . The base of current mirror output transistor Q 6  is connected to the base of transistor Q 5  and its emitter is connected to V DD .  
         [0005]     By way of definition, is to be understood that a JFET has two current-carrying electrodes, and that each of those two current-carrying electrodes can function interchangeably as either a source or a drain of the JFET, depending on which one is at the highest voltage relative to the other. For example, in an N-channel JFET, the current-carrying electrode which is at the higher voltage is the drain and the other current-carrying electrode is the source of the JFET. For example, if the voltage of a first current-carrying electrode of a N-channel JFET initially functions as its drain but then goes to a voltage which is lower than that of its second current-carrying electrode, then the second current-carrying electrode becomes the drain and the first current-carrying electrode becomes the source.  
         [0006]     In input stage  1  of  FIG. 1 , low voltage input JFETs J 0  and J 1 , rather than high-voltage input transistors, may be used as the input differential transistor pair in order to meet a desired amplifier bandwidth, slew rate, and/or settling time requirement. The low-voltage input JFETs J 0  and J 1  need to be fully protected against applied high input voltages. A typical input transistor protection circuit includes the back-to-back diode clamps D 0 , D 1 , D 2 , and D 3  as shown in  FIG. 1  to prevent the gate-to-source and drain-to-source voltages of various transistors from going high enough to reach their respective breakdown voltage levels. (The same approach can be used to prevent base-to-emitter and/or collector-to-emitter voltages of low-voltage NPN or PNP input transistors from going high enough to reach the various transistor breakdown voltage levels.) However, there is a potential problem with the technique shown in  FIG. 1  for protecting the input transistors. When the differential input voltage is sufficiently high, under either DC or transient conditions, the various protection diodes D 0 - 3  are turned on so as to clamp or limit the voltage differences between conductors  5  and  6 . As a result, the diode current flows thought the input conductors  2  and  3  of input stage  1 . This diode current is usually large (e.g., a milliampere or more, depending on the diode size and the size of input current limiting resistors R 1  and R 0 ), and is not acceptable in certain applications.  
         [0007]     Various circuits are known for boosting the slew rate of an amplifier, including commonly owned U.S. Pat. No. 6,359,572 entitled “Slew Rate Boost Circuitry and Method”, issued on Mar. 19, 2002 to Ivanov et al. , and commonly owned U.S. Pat. No. 6,437,645 entitled “Slew Rate Boost Circuitry and Method”, issued on Aug. 20, 2002 to Ivanov et al.  
         [0008]     Thus, there is an unmet need for a high-voltage amplifier input stage and method which utilizes low-voltage input transistors and which also has approximately the same performance as if high-voltage input transistors are used.  
         [0009]     There also is an unmet need for a high-voltage amplifier input stage and method which utilizes low-voltage input transistors and which also has approximately the same performance as if high-voltage input transistors are used instead of low-voltage input transistors.  
         [0010]     There also is an unmet need for a high-voltage amplifier input stage and method which utilizes low-voltage input transistors and does not require use of clamp diodes to prevent damage to the low-voltage input transistors when high magnitude differential input voltages are applied between inputs of the input stage.  
         [0011]     There also is an unmet need for a high-voltage amplifier input stage having a simple slew rate enhancement capability.  
       SUMMARY OF THE INVENTION  
       [0012]     It is an object of the invention to provide a high-voltage amplifier input stage and method which utilizes low-voltage input transistors and which also has approximately the same performance as if high-voltage input transistors are used.  
         [0013]     It is another object of the invention to provide a high-voltage amplifier input stage and method which utilizes low-voltage input transistors and which also has approximately the same performance as if high-voltage input transistors are used instead of low-voltage input transistors.  
         [0014]     It is another object of the invention to provide a high-voltage amplifier input stage and method which utilizes low-voltage input transistors and does not require use of clamp diodes to prevent damage to the low-voltage input transistors when high magnitude differential input voltages are applied between inputs of the input stage.  
         [0015]     It is another object of the invention to provide a high-voltage amplifier input stage having a simple slew rate enhancement capability.  
         [0016]     Briefly described, and in accordance with one embodiment, the present invention provides circuitry for preventing damage to differentially coupled input JFETs in an integrated circuit amplifier includes first (J 2 ) and second (J 4 ) differentially coupled input JFETs. A first input signal (Vin + ) is applied to a gate of the first input JFET (J 2 ), and second input signal (Vin − ) is applied to a gate of the second input JFET. Needed amounts of drain current are supplied to the first and second input JFETs. A separator JFET (J 1 ) having a drain coupled to a source of the first input JFET and a source coupled to the source of the second input JFET is operated to control an amount of electrical isolation between the drain and source of the separator JFET so as to limit an amount of reverse bias voltage across a gate-source junction of one of the first and second input JFETs to a value less than a gate-source junction breakdown voltage of that the first and second input JFETs.  
         [0017]     In one embodiment, the invention provides an input stage ( 15 ) including a differentially coupled first (J 2 ) and second (J 4 ) input JFETs (junction field-effect transistors), a gate of the first input JFET (J 2 ) being coupled to receive a first input signal (Vin+) and a gate of the second input JFET (J 4 ) being coupled to receive a second input signal (Vin−). A first active current source transistor (Q 14 ) is coupled between a first reference voltage (V DD ) and a drain of the first input JFET (J 2 ), and a second active current source transistor (Q 15 ) is coupled between the first reference voltage (V DD ) and a drain of the second input JFET (J 4 ). A separator JFET (J 1 ) has a drain coupled to a source of the first input JFET (J 2 ) and a source coupled to a source of the second input JFET (J 4 ). A control circuit (Q 11 ,D 0 ,D 1 ) has a first input coupled to the drain ( 16 ) of the first input JFET (J 2 ), a second input coupled to the drain ( 36 ) of the second input JFET (J 4 ), and an output ( 28 ) coupled to a gate of the separator JFET (J 1 ) for controlling the separator JFET (J 1 ) in response to the first (Vin+) and second (Vin−) input signals so as to limit a reverse bias voltage across a gate-source junction of one of the first (J 2 ) and second (J 4 ) input JFETs. A bias current circuitry (I 1 ,I 8 ) is coupled to bias the first (J 2 ) and second (J 4 ) input JFETs, respectively.  
         [0018]     In a described embodiment, the control circuit includes a first diode (D 0 ) having an anode coupled to the drain of the first input JFET (J 2 ) and a cathode coupled to a base of a level shift transistor (Q 11 ) having an emitter coupled to the gate of the separator JFET (J 1 ). A second diode (D 1 ) has an anode coupled to the drain of the second input JFET (J 4 ) and a cathode coupled to the base of the level shift transistor (Q 11 ). The first (J 2 ) and second (J 4 ) input JFETs are low-voltage JFETs having gate-source breakdown voltages which are less than a predetermined maximum magnitude of a difference between the first input signal (Vin + ) and the second input signal (Vin − ). A first transistor (Q 0 ) has an emitter coupled to the source of the first input JFET (J 2 ), a base coupled to the drain of the separator JFET (J 1 ), and a collector coupled to conduct a first output signal (Vout + ). A second transistor (Q 5 ) has an emitter coupled to the source of the second input JFET (J 4 ), a base coupled to the source of the separator JFET (J 1 ), and a collector coupled to conduct a second output signal (Vout − ). A first current source (I 1 ) in the bias current circuitry is coupled between the source of the first input JFET (J 2 ) and a second reference voltage (GND), and a second current source (I 8 ) in the bias current circuitry is coupled between the source of the second input JFET (J 4 ) and the second reference voltage (GND).  
         [0019]     In a described embodiment, a first JFET (J 0 ) has a gate and a drain coupled to the gate and drain, respectively, of the first input JFET (J 2 ). A second JFET (J 3 ) has a gate and a drain coupled to the gate and drain, respectively, of the second input JFET (J 4 ), a third transistor (Q 2 ) has a base and collector coupled to the drain of the separator JFET (J 1 ) and to a third current source (I 5 ) and an emitter coupled to a source of the first JFET (J 0 ), and a fourth transistor (Q 4 ) has a base and collector coupled to the source of the separator JFET (J 1 ) and to a fourth current source (I 6 ) and an emitter coupled to a source of the second JFET (J 3 ). A fifth transistor (Q 9 ) has an emitter coupled to the drain of the first JFET (J 0 ) and a base coupled to the source of the first JFET (J 0 ) for maintaining the drain of the first JFET (J 0 ) and the drain of the first input JFET (J 2 ) at a voltage that is one base-emitter voltage (V BE ) Plus one source-gate voltage (V SG ) different from the first input voltage (Vin + ). A sixth transistor (Q 13 ) has an emitter coupled to the drain of the second JFET (J 3 ) and a base coupled to the source of the second JFET (J 3 ) for maintaining the drains of the second JFET (J 3 ) and the second input JFET (J 4 ) at a voltage that is one base-emitter voltage (V BE ) plus one gate-source voltage (V GS ) different from the second input voltage (Vin − ). A seventh transistor (Q 6 ) has a collector coupled to a base of the first active current source transistor (Q 14 ) to a fifth current source (I 3 ), and an emitter coupled to a collector of the fifth transistor (Q 9 ) and to one terminal of a first resistor (R 4 ). An eighth transistor (Q 7 ) has a collector coupled to a base of the second active current source transistor (Q 15 ), to a sixth current source (I 11 ), and an emitter coupled to a collector of the sixth transistor (Q 13 ) and to one terminal of a second resistor (R 8 ).  
         [0020]     In a described embodiment, the source of the first JFET (J 0 ) is coupled by means of a third resistor (R 0 ) to a fifth current source (I 0 ) and to a first terminal of a fourth resistor (R 1 ) having a second terminal coupled to an emitter of the third transistor (Q 2 ). The source of the second JFET (J 3 ) is coupled by means of a fifth resistor (R 2 ) to a sixth current source (I 9 ) and to a first terminal of a sixth resistor (R 3 ) having a second terminal coupled to an emitter of the fourth transistor (Q 4 ).  
         [0021]     In the described embodiment, the first (J 2 ) and second (J 4 ) input JFETs are N-channel JFETs, the first (Q 0 ), second (Q 5 ), third (Q 2 ), and fourth (Q 4 ) transistors are NPN transistors, the fifth (Q 9 ) and sixth (Q 13 ) transistors are PNP transistors, and the first (Q 14 ) and second (Q 15 ) active current source transistors are PNP transistors. The seventh (Q 6 ) and eighth (Q 7 ) transistors are NPN transistors, and the first (J 0 ) and second (J 3 ) JFETs are low-voltage JFETs.  
         [0022]     In the described embodiment, the first through the eighth transistors have emitter-base breakdown voltages of no more than approximately  3  volts.  
         [0023]     In one embodiment, the invention provides a method for preventing damage to differentially coupled input JFETs in an integrated circuit amplifier, including providing first (J 2 ) and second (J 4 ) differentially coupled input JFETs, applying a first input signal (Vin+) to a gate of the first input JFET (J 2 ), and applying a second input signal (Vin−) to a gate of the second input JFET (J 4 ), supplying needed amounts of drain current to the first (J 2 ) and second (J 4 ) input JFETs, and operating a separator JFET (J 1 ) having a drain coupled to a source of the first input JFET (J 2 ) and a source coupled to a source of the second input JFET (J 4 ) to control an amount of electrical isolation between the drain and source of the separator JFET (J 1 ) so as to limit an amount of reverse bias voltage across a gate-source junction of one of the first (J 2 ) and second (J 4 ) input JFETs to a value of less than a gate-source junction breakdown voltage of that one of the first (J 2 ) and second (J 4 ) input JFETs.  
         [0024]     In one embodiment, the method includes providing a first transistor (Q 0 ) having an emitter coupled to the source of the first input JFET (J 2 ), a base coupled to the drain of the separator JFET (J 1 ), and a collector coupled to conduct a first output signal (Vout + ), a second transistor (Q 5 ) having an emitter coupled to the source of the second input JFET (J 4 ), a base coupled to the source of the separator JFET (J 1 ), and a collector coupled to conduct a second output signal (Vout − ), a first current source (I 1 ) coupled between the source of the first input JFET (J 2 ) and a second reference voltage (GND), and a second current source (I 8 ) coupled between the source of the second input JFET (J 4 ) and the second reference voltage (GND), and operating the first (J 2 ) and second (J 4 ) input JFETS, the first (Q 0 ) and second (Q 5 ) transistors, the first (I 1 ) and second ( 18 ) current sources so as to cause a larger portion of current of the first current source (I 1 ) to flow through the first transistor (Q 0 ) when the first input signal (Vin + ) causes in amount of current through the first input JFET (J 2 ) to decrease substantially and so as to cause a larger portion of current of the second current source (I 8 ) to flow through the second transistor (Q 5 ) when the second input signal (Vin − ) causes in amount of current through the second input JFET (J 4 ) to decrease substantially, to thereby provide slew boosting in the integrated circuit amplifier. In one embodiment the method includes coupling the base of the first transistor (Q 0 ) to the drain of the separator JFET (J 1 ) and coupling the base of the second transistor (Q 5 ) to the source of the separator JFET (J 1 ).  
         [0025]     In one embodiment, needed amounts of drain current are supplied by providing a first active current source transistor (Q 14 ) coupled between a first reference voltage (V DD ) and a drain of the first input JFET (J 2 ), and a second active current source transistor (Q 15 ) coupled between the first reference voltage (V DD ) and a drain of the second input JFET (J 4 ).  
         [0026]     In one embodiment, the invention provides circuitry for preventing damage to differentially coupled input JFETs in an integrated circuit amplifier, including first (J 2 ) and second (J 4 ) differentially coupled input JFETs, means ( 2 , 3 ) for applying a first input signal (Vin+) to a gate of the first input JFET (J 2 ), and applying a second input signal (Vin−) to a gate of the second input JFET (J 4 ), means (Q 14 ,Q 15 ) for supplying needed amounts of drain current to the first (J 2 ) and second (J 4 ) input JFETs, and means (Q 11 ,D 0 ,D 1 ) for operating a separator JFET (J 1 ) having a drain coupled to a source of the first input JFET (J 2 ) and a source coupled to a source of the second input JFET (J 4 ) to control an amount of electrical isolation between the drain and source of the separator JFET (J 1 ) so as to limit an amount of reverse bias voltage across a gate-source junction of one of the first (J 2 ) and second (J 4 ) input JFETs to a value of less than a gate-source junction breakdown voltage of that one of the first (J 2 ) and second (J 4 ) input JFETs.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0027]      FIG. 1  is a schematic diagram of a typical amplifier input stage utilizing diode clamps to protect the input transistors.  
         [0028]      FIG. 2  is a schematic diagram of an input stage which provides circuitry for protecting low voltage input transistors against high differential input voltages in accordance with the present invention, without using diode clamps.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0029]     To solve the above described problems of the prior art, the present invention provides a new design approach to utilize low voltage transistors as the differential input transistors of an amplifier input stage without using diode clamp protection for circuits as shown Prior Art in  FIG. 1 .  
         [0030]     Referring to  FIG. 2 , high-voltage operational amplifier input stage  15  includes an input conductor  2  which applies input voltage Vin +  to the gates of low-voltage N-channel JFETs J 0  and J 2 . The drains of JFETs J 0  and J 2  are connected by conductor  16  to the collector of a PNP transistor Q 14  and to the anode of a diode D 0 .  
         [0031]     The source of JFET J 0  is connected by conductor  19  to the base of PNP transistor Q 9 , the emitter of which is connected to conductor  16 . The collector of transistor Q 9  is connected by conductor  20  to one terminal of each of resistors R 4  and R 7  and also to the emitter of an NPN transistor Q 6 . The other terminals of resistors R 4  and R 7  are connected to ground. Conductor  19  also is connected to one terminal of a resistor R 0 , the other terminal of which is connected by conductor  21  to one terminal of a current source I 0 . The other terminal of current source I 0  is connected to ground. The cathode of diode D 0  is connected by conductor  25  to one terminal of a current source I 2 , the other terminal of which is connected to ground. The collector of NPN transistor Q 6  is connected by conductor  17  to the base of active current source transistor Q 14  and to one terminal of a current source I 3 , the other terminal of which is connected to V DD . The base of transistor Q 6  is coupled to a suitable bias voltage V BIAS .  
         [0032]     The source of input JFET J 2  is connected by conductor  18  to the emitter of an NPN transistor Q 0  and to one terminal of a current source I 1 , the other terminal of which is connected to ground. The base of transistor Q 0  is connected by conductor  24  to the base and collector of a diode-connected NPN transistor Q 2  and to the drain of a P-channel separator JFET J 1 . The collector of transistor Q 0  is connected to an output conductor  23  on which an output voltage Vout +  is produced. The emitter of transistor Q 2  is connected by conductor  22  to one terminal of a resistor R 1 , the other terminal of which is connected to conductor  21 . The base and collector of diode-connected transistor Q 2  are connected to one terminal of a current source I 5 , the other terminal of which is connected to V DD . Transistor Q 2  operates to provide the base bias voltage of transistor Q 0 .  
         [0033]     The left-hand portion of high-voltage operational amplifier input stage  15  of  FIG. 2  described above is symmetrical to the subsequently described right-hand portion thereof. Specifically, the right-hand portion includes an input conductor  3  which applies input voltage Vin −  to the gates of low-voltage N-channel JFETs J 3  and J 4 . The drains of transistors J 3  and J 4  are connected by conductor  36  to the collector of a PNP transistor Q 15  and to the anode of a diode D 1 .  
         [0034]     The source of JFET J 3  is connected by conductor  34  to the base of PNP transistor Q 13 , the emitter of which is connected to conductor  36  and the collector of which is connected by conductor  38  to one terminal of each of resistors R 8  and R 9  and also to the emitter of an NPN transistor Q 7 . The other terminals of resistors R 8  and R 9  are connected to ground. Conductor  34  also is connected to one terminal of a resistor R 2 , the other terminal of which is connected by conductor  31  to one terminal of a current source I 9 . The other terminal of current source I 9  is connected to ground. The cathode of diode D 1  is connected by conductor  25  to one terminal of a current source I 12 , the other terminal of which is connected to ground. The collector of NPN transistor Q 7  is connected by conductor  40  to the base of transistor Q 15  and to one terminal of a current source I 11 , the other terminal of which is connected to V DD . The base of transistor Q 7  is coupled to a suitable bias voltage V BIAS .  
         [0035]     The source of input JFET J 4  is connected by conductor  32  to the emitter of an NPN transistor Q 5  and to one terminal of a current source I 8 . The other terminal of current source I 8  is connected to ground. The base of transistor Q 5  is connected by conductor  27  to the base and collector of a diode-connected NPN transistor Q 4  and to the source of P-channel separator JFET J 1 . The collector of transistor Q 5  is connected to an output conductor  33  on which an output voltage Vout −  is produced. The emitter of diode-connected transistor Q 4  is connected by conductor  30  to one terminal of a resistor R 3 , the other terminal of which is connected to conductor  31 . The base and collector of diode-connected transistor Q 4  is connected to one terminal of a current source I 6 , the other terminal of which is connected to V DD .  
         [0036]     A “maximum voltage level selector and level shift circuit” circuit, including PNP transistor Q 11  and diodes D 0  and D 1 , functions to control the gate of P-channel separator JFET J 1   FIG. 2 , and is generally similar to the various embodiments of the minimum voltage level selector and level shift circuits disclosed in the assignee&#39;s previously mentioned incorporated-by-reference pending parent patent application.  
         [0037]     The gate of P-channel separator JFET J 1  is connected by conductor  28  to one terminal of a current source I 3  and to the emitter of a PNP level shift transistor Q 11 , the collector of which is connected to ground. The base of level shift transistor Q 11  is connected to conductor  25 . The other terminal of current source I 13  is connected to V DD . Diodes D 0  and D 1  are biased by current sources I 2  and I 12  respectively. Level shift transistor Q 11  is biased by current source I 13 .  
         [0038]     In the example of  FIG. 2 , N-channel JFETs J 0 , J 2 , J 3  and J 4  are low-threshold transistors which can be damaged when their gate-to-source, gate-to-drain or drain-to-source voltage exceeds, for example, approximately  10  volts. P-channel separator JFET J 1  is a high-voltage transistor in which the gate-to-source, gate-to-drain or drain-to-source voltage can be as high as V DD . The various NPN transistors and PNP transistors can be high-voltage transistors that can withstand collector-base voltages as high as V DD , but cannot have emitter-to-base voltages greater than approximately 3 volts.  
         [0039]     The maximum voltage level selector and level  12  shift circuit Q 11 ,D 0 ,D 1  operates to cause separator JFET J 1  to have very low channel resistance so that input JFETs J 2  and J 4  are to fully differentially coupled during normal balanced operation when the differential input voltage Vin + −Vin −  is very small.  
         [0040]     Maximum voltage level selector and level shift circuit Q 11 ,D 0 ,D 1  also operates to cause separator JFET J 1  to go into its pinch-off region of operation if the differential input voltage Vin + −Vin −  is excessively large so as to cause gate-to-source breakdown of either of input JFETs J 2  and J 4 . With separator JFET J 1  in its pinch-off region, its source and drain electrodes are effectively separated, and most of the Vin + −Vin −  overvoltage is, in effect, absorbed across separator JFET J 1  instead of across the gate-to-source junction of either of low-threshold input JFETs J 2  and J 4 . Therefore, low-threshold input JFETs J 2  and J 4 , with their superior high-speed performance characteristics, can be utilized because they are protected from damage that would otherwise be caused by the excessive differential Vin + −Vin −  input overvoltages.  
         [0041]     In  FIG. 2 , the input differential pair consists of N-channel input JFETs J 2  and J 4 , which function as voltage followers and are “followed” by NPN transistors Q 0  and Q 5 . Transistors Q 0  and Q 5  function as common-base gain stages. Current sources I 5  and I 6  bias diode-connected NPN transistors Q 2  and Q 4  respectively. As a result, transistor Q 2  sets the bias of transistor Q 0 , and transistor Q 4  sets the bias of transistor Q 5 . JFET J 0  is biased by the current difference between current sources I 5  and I 0 , and similarly, JFET J 3  is biased by the current difference between current sources I 6  and I 9 . JFET J 2  is biased by current source I 1  in accordance with the W/L ratio (channel-width-to-channel-length ratio) of JFET J 2  to that of JFET J 0 . Similarly, JFET J 4  is biased by current source I 8  in accordance with the W/L ratio (channel-width-to-channel-length ratio) of JFET J 4  to that of JFET J 3 . By adjusting the W/L ratio, the Q 0  and Q 4  currents can be set to appropriate amounts, which is critical to amplifier performance. Furthermore, slew rate enhancement, which is described later, also depends on the W/L ratio. The drain-to-source voltages V DS  of JFETs J 0  and J 2  are equal to the base-to-emitter voltage V BE  voltage drop of transistor Q 9 . Similarly, the V DS  voltages of JFETs J 3  and J 4  equal to the V BE  voltage of transistor Q 13 .  
         [0042]     The left and right sides of input stage  15  in  FIG. 2  are symmetrical. During steady state operation, the source voltages of JFETs J 0 , J 2  , J 3  and J 4  are the same, and are biased at one V SG  voltage higher than the gate voltage of those transistors. The base voltages of transistors Q 0 , Q 2 , Q 4  and Q 5 , and also the drain and source voltages of J 1 , are equal and are biased at V SG +V BE  volts higher than the gate voltage of JFETs J 0 , J 2  , J 3  and J 4 . Separator JFET J 1  needs to have a minimum drain-to-source resistance, i.e., channel resistance Rds in order to minimize its noise contribution, so its gate should be biased at the same voltage as its drain and source, which both are V SG +V BE  volts higher than its gate voltage. This is accomplished by maximum voltage level selector and level shift circuit Q 11 ,D 0 ,D 1 .  
         [0043]     Transistor Q 14 , along with the local feedback loop consisting of current source I 3 , transistors Q 6  and Q 9 , and resistors R 4  and R 7 , serves as an active current source and provides current as needed to JFET J 0  and input JFET J 2  during slewing operation of input stage  15  when Vin +  increases. Since only one Vsat (drain-to-source saturation voltage) of the “head room voltage” is required in order to allow normal operation of active current source transistor Q 14 , active current source transistor Q 14  also maximizes the input common-mode range.  
         [0044]     When the (+) input signal Vin +  increases as indicated by dashed line arrow A, the source voltages of JFET J 0  and input JFET J 2 , as well as the emitter voltages of transistors Q 0  and Q 2 , track Vin +  at a voltage which is one V SG  level higher than Vin + . The anode of diode D 0  also tracks Vin +  to reach a high voltage level (as indicated by dashed line arrow B), while the anode (conductor  36 ) of diode D 1  tracks the (−) input Vin −  and stays at a relatively low level. Therefore, diode D 0  stays turned on to conduct currents I 2  and I 12 , and diode D 1  is reverse biased (i.e. turned off). As a result, the gate voltage of separator JFET J 1  tracks the increasing Vin +  voltage level with a corresponding voltage level shift (i.e., the V BE  of level shift transistor Q 11 ) and separator JFET J 1  stays strongly turned on to conduct the current I 5 . Transistors Q 0  and Q 2  are turned off as their emitter voltages increase, and current I 5  flows through separator JFET J 1  as indicated by dashed line arrow H.  
         [0045]     Also for the foregoing case of increasing Vin + , in the right half of input stage  15 , transistor Q 4  conducts both currents I 5  and  16 . Current  19  is chosen to be greater than the total amount of currents I 5  and I 6  and the current difference between I 5  and I 6  flows though JFET J 3 . The source potential of JFET J 3  is biased by this current difference. Therefore, even though the (−) input signal Vin −  of input stage  15  is at a relatively low voltage level as indicated by dashed line arrow E, JFET J 3  does not turn off as much as JFET J 4  and the source voltages of JFET J 3  and input JFET J 4  track the inverting input signal Vin − , and still conducts current as indicated by dashed line arrows F and G.  
         [0046]     In the case of increasing Vin − , transistor Q 15 , along with the local feedback loop consisting of current source I 11 , transistors Q 7  and Q 13 , and resistors R 8  and R 9 , serves as an active current source and provides current as needed to JFET J 3  and input JFET J 4  during slewing operation of input stage  15  when Vin −  increases. Active current source transistor Q 15  maximizes the input common-mode range, since only one Vsat (drain-to-source saturation voltage) of head room voltage is needed to allow normal operation of active current source transistor Q 15 . As the (−) input signal Vin −  increases, the source voltages of JFET J 3  and input JFET J 4 , as well as the emitter voltages of transistors Q 5  and Q 4 , track Vin −  at a voltage which is one V SG  level higher than Vin − . The anode of diode D 1  also tracks Vin to reach a high voltage level, while the anode of diode D 0  tracks the (+) input Vin +  and stays at a relatively low level. Therefore, diode D 1  stays turned on to conduct currents I 2  and I 12  and diode D 0  is turned off. As a result, the gate voltage of separator JFET J 1  tracks the increasing Vin −  voltage level with a corresponding voltage shift (i.e., the V BE  of level shift transistor Q 11 ) and separator JFET J 1  stays strongly turned on to conduct the current I 6 . Transistors Q 5  and Q 4  are turned off as their emitter voltages increase.  
         [0047]     For the case of increasing Vin − , the left half of input stage  15 , transistor Q 2  conducts both currents I 5  and I 6 . Current I 0  is chosen to be greater than the total amount of currents I 5  and I 6  and the current difference between I 5  and I 6  flows though JFET J 0 . The source potential of JFET J 0  is biased by this current difference. Therefore, even though the (+) input signal Vin +  of input stage  15  is at a relatively low voltage level, JFET J 0  does not turn off as much as input JFET J 2  and the source voltages of JFET J 0  and input JFET J 2  track the non-inverting input signal Vin + .  
         [0048]     When a positive high voltage differential input signal Vin + −Vin −  is applied during a dynamic operating condition, the gate of P-channel separator JFET J 1  always tracks the highest potential of the input signal Vin +  and P-channel separator JFET J 1  stays turned on to conduct the current I 5 . The drain or source of P-channel separator JFET J 1  receives high or low voltage, respectively, so the source-coupled differential input JFETs J 2  and J 4  are electrically separated. Therefore, bipolar transistors Q 0 , Q 2 , Q 4  and Q 5  are protected from large reverse-bias voltages and JFETs J 0 , J 2 , J 3  and J 4  are protected from high reverse gate-source voltages and operate without being damaged because separator JFET J 1  is biased into its pinch-off region in response to differential input overvoltages that otherwise could damage JFETs J 0 , J 2 , J 3  and J 4 . Separator JFET J 1  is properly sized so as to reduce its noise contribution.  
         [0049]     Similarly, when a negative value of high voltage differential input signal Vin + −Vin −  is applied during a dynamic operating condition, the gate of P-channel separator JFET J 1  always tracks the highest potential of the input signal Vin −  and separator JFET J 1  stays turned on to conduct the current I 6 . Therefore, the drain or source of separator JFET J 1  receives high or low voltage, respectively, and accordingly goes into its pinch-off region, causing the differential JFETs J 2  and J 4  to be effectively separated. Therefore transistors Q 0 , Q 2 , Q 4  and Q 5  are protected from large reverse emitter-base voltages and JFETs J 0 , J 2 , J 3  and J 4  are protected from high reverse gate-source voltages and operate without being damaged.  
         [0050]     The slew rate of input stage  15  is usually limited by the input stage tail currents I 1  and I 8  and compensation capacitance is (not shown) for a typical amplifier design. To increase the slew rate, additional slew-boost current I 1  is provided as follows.  
         [0051]     During slewing, current sources I 1  and I 8  stay constant, and the current flowing through transistor Q 0  or transistor Q 5  determines the slew rate. During operation when substantial slewing is not occurring, only a small portion of current I 1  or I 8  flows through transistor Q 0  or Q 5 , respectively. However, during slewing, the circuitry including input JFET J 2 , transistor Q 0 , and current source I 1  operates to cause a larger portion of current I 1  to flow through transistor Q 0  when Vin +  causes the amount of current through input JFET J 2  to decrease substantially. Similarly, the during slewing, the circuitry including input JFET J 4 , transistor Q 5 , and current source I 8  operate to cause a larger portion of current I 8  to flow through transistor Q 5  when Vin −  causes the amount of current through input JFET J 4  to decrease substantially. In either case, the total supply current of input stage  15  is not increased during slewing operation.  
         [0052]     In the input stage  15 , the slew rate is proportional to the amount of current flowing through transistor Q 0  or transistor Q 5  under dynamic operating conditions. When resistors R 0 , R 1 , R 2  and R 3  are properly sized and device size ratios of transistors J 0  and J 2  and input JFETs J 3  and J 4  are selected as needed, the current provided by I 1  or I 8  and conducted by transistor Q 0  or Q 5  during the slewing is substantially increased. Thus, the effective amount of “tail” current I 1  or I 8  flowing through transistor Q 0  or Q 5  to provide slewing is boosted during the slewing, and as a result the slew rate of input stage  15  can be substantially increased. The implementation of slew rate enhancement is simple, which is a benefit of the input stage design shown in  FIG. 2 , and provides more flexibility in the design of high performance amplifiers.  
         [0053]     The input stage of the present invention can be used to provide a high-voltage operational amplifier with N-channel JFET input transistors which is fully functionally at high differential input voltages even though the N-channel JFET input transistors are low-voltage devices. The input stage of the present invention protects the low voltage N-channel JFETs from breaking down under different operational conditions. The performance of the operational amplifier is not substantially degraded in comparison with the case in which conventional high-voltage N-channel input JFETs are used. Slew rate enhancement is achieved by means of very simple circuitry.  
         [0054]     Transistor Q 14  in conjunction with transistors Q 9  and Q 6  and resistors R 4  and R 7  (also transistor Q 15  in conjunction with transistors Q 13  and Q 7 , and resistors R 8  and R 9 ) serve as active current sources to maximize the upper common-mode range of amplifier input stage  15 . The use of additional JFET J 0  and resistors R 0  and R 1  (and also JFET J 3  and resistors R 2  and R 3 ) provide a simple way of enhancing the slew rate when needed. The input stage design with JFETs J 2  and J 4  and transistors Q 0  and Q 5  allows the lower common-mode range of amplifier input stage  15  to include the negative power supply voltage.  
         [0055]     The invention provides a high-voltage amplifier input stage utilizing low voltage input transistors without using diode clamps, uses an input stage design to maximize the input common-mode range of the amplifier input stage, and uses simple circuitry to provide increased slew rate. The combination of these features is important to the performance of amplifier input stage  15 , and can not be achieved by known amplifier input stage designs.  
         [0056]     While the invention has been described with reference to several particular embodiments thereof, those skilled in the art will be able to make various modifications to the described embodiments of the invention without departing from its true spirit and scope. It is intended that all elements or steps which are insubstantially different from those recited in the claims but perform substantially the same functions, respectively, in substantially the same way to achieve the same result as what is claimed are within the scope of the invention. For example, the design technique of the present invention is also applicable to various other high voltage amplifier input stage designs where low voltage input transistors are needed to achieve the desired performance.