Abstract:
There is provided a semiconductor device. The semiconductor device includes: a first board; a second board joined to the first board; a connection terminal provided between the first board and the second board and electrically connecting the first board and the second board; and an electronic component on at least one of the first board and the second board. The connection terminal serves as an antenna.

Description:
[0001]    This application claims priority from Japanese Patent Application No. 2013-016676, filed on Jan. 31, 2013, the entire contents of which are herein incorporated by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Technical Field 
         [0003]    The present disclosure relates to a semiconductor device. 
         [0004]    2. Description of the Related Art 
         [0005]    In the related art, semiconductor devices incorporating electronic components such as active elements and passive elements have various structures. In recent years, semiconductor devices having a wireless communication module incorporating, for example, a radio-frequency (RF) communication unit, a control unit, a crystal oscillator or the like have come to be used frequently in various fields. To perform a wireless communication using an antenna, such semiconductor devices are equipped with an antenna that is connected to the RF communication unit or the like (see e.g., JP-A-2007-324231). 
         [0006]      FIG. 12  is a plan view of a related-art semiconductor device having an antenna  120 . As shown in  FIG. 12 , the related-art semiconductor device  100  includes a wiring board  110  and a control IC chip  132  and an RF IC chip  131  which are mounted on the wiring board  110 . 
         [0007]      FIG. 13  is a plan view of the wiring board  110  in the related art. In  FIG. 13 , reference symbol R 11  denotes a region where the RF IC chip  131  is to be mounted (hereinafter referred to as an RF IC mounting region R 11 ) and symbol R 12  denotes a region where the control IC chip  132  is to be mounted (hereinafter referred to as a control IC mounting region R 12 ). 
         [0008]    As shown in  FIG. 13 , the wiring board  110  has a board body  111 , connection pads  112 - 115 , traces  117 - 119 , and an antenna  120 . Each side surface of the board body  111  is formed with plural notches  111 X. Each notch  111 X is formed so as to assume a semicylindrical shape and to reach the top surface and the bottom surface of the board body  111 . 
         [0009]    The connection pads  112  and  113  are formed in the RF IC mounting region R 11  of the top surface of the board body  111 , and are electrically connected to the RF IC chip  131 . The connection pads  112  are electrically connected to edge electrodes  116  via the traces  117 , respectively. The connection pads  113  are electrically connected to connection pads  115  via the traces  118 , respectively. 
         [0010]    The connection pads  114  and  115  are formed in the control IC mounting region R 12  of the top surface of the board body  111 , and are electrically connected to the control IC chip  132 . The connection pads  114  are electrically connected to edge electrodes  116  via the traces  119 , respectively. 
         [0011]    As shown in  FIG. 14 , the antenna  120  has wiring members  121  which are formed on the top surface of the board body  111 , wiring members  122  which are formed on the bottom surface of the board body  111 , and connection members  123  which are formed on respective notches  111 X. The wiring members  121  and  122  and the connection members  123  are electrically connected mutually. The antenna  120  is electrically connected to the RF IC chip  131  shown in  FIG. 12 . 
         [0012]    Forming the portions (i.e., connection members  123 ) of the antenna  120  on the side surface of the board body  111  makes it possible to decrease an area of the top surface of the board body  111  which is occupied by the antenna  120  than in the case where the antenna is formed only on the top surface of the board body  111 . 
         [0013]    However, in the above wiring board  110 , the wiring length of the antenna  120  depends on the thickness of the board body  111 . Therefore, when the board body  111  is thin, it is impossible to secure sufficient wiring lengths of the antenna  120  utilizing the connection members  123 , resulting in difficulty designing a low-frequency antenna that requires a long wiring length. In this case, to design a low-frequency antenna, it is necessary to form long wiring members  121  and  122  on the top surface and the bottom surface, respectively, of the board body  111 , which means increase in the areas occupied by the wiring members  121  and  122 . That is, when the board body  111  is thin, a problem arises that it is difficult to reduce the horizontal area of the board body  111 , that is, to miniaturize the board body  111 , which in turn makes it difficult to miniaturize the semiconductor device  100  having the board body  111 . 
       SUMMARY OF THE INVENTION 
       [0014]    According to one or more aspects of the present invention, there is provided a semiconductor device. The semiconductor device includes: a first board; a second board joined to the first board; a connection terminal provided between the first board and the second board and electrically connecting the first board and the second board; and an electronic component on at least one of the first board and the second board. The connection terminal serves as an antenna. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1A  is a schematic sectional view, taken along lines  1   a - 1   a  in  FIGS. 2 and 3 , of a semiconductor device according to an embodiment; 
           [0016]      FIG. 1B  is a schematic sectional view, taken along lines  1   b - 1   b  in  FIGS. 2 and 3 , of the semiconductor device according to the embodiment; 
           [0017]      FIG. 2  is a schematic plan view of part of the semiconductor device according to the embodiment; 
           [0018]      FIG. 3  is a schematic plan view of another part of the semiconductor device according to the embodiment; 
           [0019]      FIG. 4  is a schematic plan view of a first board used in the embodiment; 
           [0020]      FIG. 5  is a schematic plan view of a second board used in the embodiment; 
           [0021]      FIG. 6  is a schematic bottom view of the second board used in the embodiment; 
           [0022]      FIG. 7  is a schematic sectional view, taken along lines  7 - 7  in  FIGS. 2 and 3 , of an antenna used in the embodiment; 
           [0023]      FIGS. 8A-8C  are schematic sectional views showing a manufacturing method of the semiconductor device according to the embodiment; 
           [0024]      FIG. 9  is a schematic sectional view of a semiconductor device according to a modified embodiment; 
           [0025]      FIG. 10  is a schematic sectional view of a semiconductor device according to another modified embodiment; and 
           [0026]      FIG. 11  is a schematic sectional view of a semiconductor device according to another modified embodiment; 
           [0027]      FIG. 12  is a schematic plan view of a semiconductor device in a related-art; 
           [0028]      FIG. 13  is a schematic plan view of a wiring board used in the related-art semiconductor device of  FIG. 12 ; and 
           [0029]      FIG. 14  is a schematic sectional view of an antenna in the related-art semiconductor device of  FIG. 12 . 
       
    
    
     DETAILED DESCRIPTION 
       [0030]    An embodiment will be hereinafter described with reference to the accompanying drawings. In the accompanying drawings, for the sake of convenience in facilitating understanding of an important feature, a related portion may be enlarged. Therefore, for example, the ratio between dimensions of each constituent element is not necessarily the same as an actual ratio. In each sectional view, to facilitate understanding of the sectional structures of individual members, hatching of part of them may be omitted. 
         [0031]    First, the configuration of a semiconductor device  10  will be described. The embodiment is directed to an example that an antenna  30  which is an inverted-F antenna is provided so as to bridge two wiring boards (first board  20  and second board  40 ). 
         [0032]    As shown in  FIGS. 1A and 1B , the semiconductor device  10  includes the first board  20 , the second board  40 , and cored solder balls  60  which electrically connect the first board  20  and the second board  40 . The first board  20  and the second board  40  are provided with the antenna  30  which includes part of the cored solder balls  60 . 
         [0033]    As shown in  FIGS. 1A and 2 , the top surface of the first board  20  is mounted with a semiconductor chip  70  which is an active element. For example, a control IC chip such as a CPU (central processing unit) chip can be used as the semiconductor chip  70 . In the following description, the semiconductor chip  70  may also be referred to as a control IC chip  70 . 
         [0034]    As shown in  FIGS. 1A and 3 , the top surface of the second board  40  is mounted with a semiconductor chip  71  which is an active element and passive elements  72 . For example, an RF IC (radio-frequency integrated circuit) chip can be used as the semiconductor chip  71 . In the following description, the semiconductor chip  71  may also be referred to as an RF IC chip  71 . For example, chip capacitors, chip inductors, and chip resistors can be used as the passive elements  72 . Traces connected to the passive elements  72  are omitted in  FIG. 3 . As shown in  FIG. 1A , the bottom surface of the second board  40  is formed with external connection terminals  75  which are terminals for electrical connection to a mounting board such as a mother board. For example, solder balls can be used as the external connection terminals  75 . 
         [0035]    Next, the configuration of the first board  20  will be described with reference to  FIGS. 1A and 1B  and  FIG. 4 .  FIG. 4  is a top view of the first board  20  shown in  FIG. 1A . In  FIG. 4 , reference symbol R 1  denotes a region where the control IC chip  70  is to be mounted (hereinafter referred to as a control IC mounting region R 1 ). 
         [0036]    The first board  20  has a first board body  21 , connection pads  22 , traces  23 , ground lines  24 , and connection members  25  which are formed on the top surface  21 A of the first board body  21 , connection pads  26  formed on the bottom surface  21 B of the first board body  21 , and the above-mentioned antenna  30 . It suffices that the first board body  21  be formed in such a manner that the connection members  25  and the connection pads  26  which are formed on the top surface  21 A and the bottom surface  21 B of the first board body  21 , respectively, are electrically connected mutually by lines formed inside the first board body  21 . Therefore, wiring layers may be formed inside the first board body  21  but need not always be done so. Where wiring layers are formed inside the first board body  21 , they are stacked via interlayer insulating layers and the connection members  25  and the connection pads  26  are electrically connected by vias that are formed through the wiring layers and the insulating layers. For example, a cored buildup board having a core substrate or a coreless board having no core substrate can be used as the first board body  21 . For example, such a first board body  21  may be about 0.2 to 1.0 mm in thickness. 
         [0037]    The connection pads  22  are formed in the control IC mounting region R 1  of the top surface  21 A of the first board body  21 . The connection pads  22  are pads that are to be electrically connected to the control IC chip  70 . The connection pads  22  are electrically connected to the connection members  25  via the traces  23 , respectively. A connection pad  22 , a trace  23 , and a connection member  25  that are connected to each other are integrated together. For example, the connection pads  22  and the connection members  25  are approximately circular in a plan view and the traces  23  are approximately band-shaped in a plan view. The connection pads  22 , the connection members  25 , and the connection members  25  may be made of copper or a copper alloy, for example. 
         [0038]    The ground lines  24  extend across the top surface  21 A of the first board body  21  in the top-bottom direction in  FIG. 4  so as to assume approximately band-like shapes. The ground lines  24  are electrically connected to the antenna  30  and given a ground potential. The ground lines  24  may be made of copper or a copper alloy, for example. 
         [0039]    The connection members  25  are formed in an outer peripheral region of the top surface  21 A of the first board body  21 . As shown in  FIG. 1B , part of the connection members  25  are electrically connected to part of via electrodes  27 , respectively, which penetrate through the first board body  21  in its thickness direction. The via electrodes  27  are formed in respective through-holes  21 X which penetrate through the first board body  21  so as to reach its top surface  21 A and bottom surface  21 B. The through-holes  21 X are filled with the respective via electrodes  27 . The top ends of the via electrodes  27  are connected to the above connection members  25 , and their bottom ends are connected to part of the connection pads  26 , respectively. Thus, the above connection members  25  and connection pads  26  are electrically connected mutually by these via electrodes  27 , respectively. The connection pads  26  are pads that are to be joined to cored solder balls  60  and electrically connected to connection pads  47 A,  47 B, and  47 C of the second board  40  by these cored solder balls  60 , respectively. Although not shown in any drawings, the connection pads  26  are, for example, approximately circular in a plan view. 
         [0040]    The via electrodes  27  and the connection pads  26  are made of copper or a copper alloy, for example. Although in the embodiment the through-holes  21 X are filled with the via electrodes  27  made of a conductive material such as copper, via electrodes may be formed as plated through-hole vias in the respective through-holes  21 X. 
         [0041]    Although actually the above-described traces  23 , ground lines  24 , and connection members  25  are covered with a solder resist layer, the solder resist layer is not shown in  FIGS. 1A and 1B  to facilitate understanding of the sectional structures of the individual members. 
         [0042]    Next, the configuration of the second board  40  will be described with reference to  FIGS. 1A and 1B ,  5 , and  6 .  FIG. 5  is a top view of the second board  40  shown in  FIG. 1A , and  FIG. 6  is bottom view of the second board  40  shown in  FIG. 1A . In  FIG. 5 , reference symbol R 2  denotes a region where the RF IC chip  71  is to be mounted (hereinafter referred to as an RF IC mounting region R 2 ) and symbol R 3  denotes regions where the passive elements  72  are to be mounted (hereinafter referred to as passive element mounting regions R 3 ). 
         [0043]    The second board  40  has a second board body  41 , connection pads  42 ,  43 , and  44 , traces  45 , ground lines  46 , and connection pads  47 A,  47 B, and  47 C which are formed on the top surface  41 A of the second board body  41 , connection pads  50  formed on the bottom surface  41 B of the second board body  41 , and the above-mentioned antenna  30 . It suffices that the second board body  41  be formed in such a manner that at least the connection pads  47 B among the connection pads  47 A- 47 C formed on the top surface  41 A of the second board body  41  and the corresponding connection pads  50  formed on the bottom surface  41 B of the second board body  41  be electrically connected mutually by lines formed inside the second board body  41 . Therefore, wiring layers may be formed inside the second board body  41  but need not always be done so. Where wiring layers are formed inside the second board body  41 , they are stacked via interlayer insulating layers and the connection pads  47 B and the connection pads  50  are electrically connected by vias that are formed through the wiring layers and the insulating layers. For example, a cored built-up board having a core substrate or a coreless board having no core substrate can be used as the second board body  41 . For example, such a second board body  41  may be about 0.2 to 1.0 mm in thickness. 
         [0044]    The connection pads  42 ,  43 , and  44  are formed in the RF IC mounting region R 2  of the top surface  41 A of the second board body  41 . The connection pads  42 - 44  are pads that are to be electrically connected to the RF IC chip  71 . For example, the connection pads  42 - 44  are approximately circular in a plan view. 
         [0045]    The connection pads  47 A,  47 B, and  47 C (hereinafter may be referred to generically as connection pads  47 ) are formed in a peripheral region of the top surface  41 A of the second board body  41 . The connection pads  47 A- 47 C are pads that are to be joined to the respective cored solder balls  60 . For example, the connection pads  47 A- 47 C are approximately circular in a plan view. The connection pads  42 - 44  and the connection pads  47 A- 47 C may be made of copper or a copper alloy, for example. 
         [0046]    The connection pads  42  are electrically connected to the connection pads  47 A by the corresponding traces  45 , respectively. The connection pads  47 A are to be electrically connected to part of the connection pads  26  of the first board  20  by the cored solder balls  60 , respectively (see  FIG. 1B ). Therefore, the connection pads  42  are to be electrically connected to the corresponding connection pads  22  via the corresponding traces  45 , the connection pads  47 A, the corresponding cored solder balls  60 , the corresponding connection pads  26 , the corresponding via electrodes  27 , the corresponding connection members  25 , and the traces  23 , respectively. As a result, when mounted in the RF IC mounting region R 2 , the RF IC chip  71  is electrically connected to the control IC chip  70  mounted in the control IC mounting region R 1  via the above connection pads  42 , traces  45 , connection pads  47 A, cored solder balls  60 , connection pads  26 , via electrodes  27 , connection members  25 , traces  23 , and connection pads  22 . 
         [0047]    The connection pads  43  are electrically connected to the connection pads  47 B by the corresponding traces  45 , respectively. As shown in  FIG. 1A , the connection pads  47 B are electrically connected to respective via electrodes  51  which penetrate through the second board body  41  in its thickness direction. The via electrodes  51  are formed in part of through-holes  41 X, respectively, which penetrate through the second board body  41  so as to reach its top surface  41 A and bottom surface  41 B. These through-holes  41 X are filled with the respective via electrodes  51 . The top ends of the via electrodes  51  are connected to the connection pads  47 B, and their bottom ends are connected to the corresponding connection pads  50 , respectively. Thus, the connection pads  47 B and the corresponding connection pads  50  are electrically connected mutually by the via electrodes  51 , respectively. The connection pads  50  are pads that are to be joined to part of cored solder balls  60  and electrically connected to external connection terminals  75 , respectively. As shown in  FIG. 6 , the connection pads  50  are formed in a peripheral region of the bottom surface  41 B of the second board body  41 . 
         [0048]    The via electrodes  51  and the connection pads  50  are made of copper or a copper alloy, for example. Although in the embodiment the through-holes  41 X are filled with the via electrodes  51  made of a conductive material such as copper, via electrodes may be formed as plated through-hole vias in the respective through-holes  41 X. 
         [0049]    The connection pads  44  are electrically connected to the connection pads  47 C by the ground lines  46 , respectively. The connection pads  47 C are to be electrically connected to the ground lines  24  of the first board  20  (see  FIG. 4 ) via the corresponding cored solder balls  60 , connection pads  26  (see  FIG. 1B ), and via electrodes  27  (see  FIG. 1B ). Therefore, the connection pads  44  are to be electrically connected to the ground lines  24  via the respective ground lines  46 , the connection pads  47 C, the corresponding cored solder balls  60 , the corresponding connection pads  26 , the corresponding via corresponding electrodes  27 , the corresponding connection members  25 , and the traces  23 , respectively. As a result, when mounted in the RF IC mounting region R 2 , the RF IC chip  71  is electrically connected to the ground lines  24  via the above connection pads  44 , ground lines  46 , connection pads  47 C, cored solder balls  60 , connection pads  26 , and via electrodes  27 . The ground lines  46  are given the ground potential. The ground lines  46  may be made of copper or a copper alloy, for example. 
         [0050]    As shown in  FIGS. 1A and 1B  and  FIG. 3 , the corresponding cored solder balls  60  are joined to the connection pads  47 A- 47 C, respectively. These cored solder balls  60  are also joined to the respective connection pads  26  of the first board  20  (see  FIG. 1A ). That is, these cored solder balls  60  are sandwiched between the first board  20  and the second board  40 , and their one ends are joined to the connection pads  26  and the other ends are joined to the connection pads  47 A- 47 C. The cored solder balls  60  function as connection terminals for connecting (joining) the first board  20  and the second board  40  as well as spacers for keeping the distance between the first board  20  and the second board  40  at a prescribed value. The height of the cored solder balls  60  is set greater than the thickness of the RF IC chip  71  and the heights of the passive elements  72  and also greater than the thicknesses of the first board body  21  and the second board body  41 . The height of the cored solder balls  60  can be set at about 0.8 to 1.2 mm, for example. 
         [0051]    Each cored solder ball  60  has a structure that a spherical copper core ball  61  is surrounded by a solder layer  62 . The solder layer  62  functions as a joining member and the copper core ball  61  functions as a spacer. That is, each cored solder ball  60  is joined to the associated connection pad  26  by the solder layer  62  and joined to the associated connection pad  47 A,  47 B, or  47 C by the solder layer  62 . 
         [0052]    The cored solder balls  60  include cored solder balls  60 A,  60 B,  60 C,  60 D,  60 E, and  60 F which are part of the antenna  30 . 
         [0053]    Although actually the above-described traces  45  and ground lines  46  are covered with a solder resist layer, the solder resist layer is not shown in  FIGS. 1A and 1B  to facilitate understanding of the sectional structures of the individual members. 
         [0054]    Next, the configuration of the antenna  30  will be described with reference to  FIGS. 2-7 . The antenna  30  used in the embodiment is an inverted-F antenna. The antenna  30  is electrically connected to the ground lines  24  and  46  which are formed on the first board  20  and the second board  40 , respectively, and power lines (not shown). 
         [0055]    The antenna  30  has first wiring members  31 A- 31 C, first via electrodes  32 A- 32 E, first wiring patterns  33 A- 33 E, second wiring members  34 A- 34 C, second via electrodes  35 A- 35 E, second wiring patterns  36 A- 36 F, and the cored solder balls  60 A- 60 F. 
         [0056]    The first wiring members  31 A- 31 C (hereinafter may be referred to generically as first wiring members  31 ) are formed on the top surface  21 A of the first board body  21 . Like the above-described via electrodes  27 , the first via electrodes  32 A- 32 E (hereinafter may be referred to generically as first via electrodes  32 ) are formed in respective through-holes  21 X which penetrate through the first board body  21  in its thickness direction. The first wiring patterns  33 A- 33 E (hereinafter may be referred to generically as first wiring patterns  33 ) are formed on the bottom surface  21 B of the first board body  21 . Although not shown in any drawings, the first wiring patterns  33  used in the embodiment are, for example, approximately circular in a plan view. 
         [0057]    The second wiring members  34 A- 34 C (hereinafter may be referred to generically as second wiring members  34 ) are formed on the bottom surface  41 B of the second board body  41 . Like the above-described via electrodes  51 , the second via electrodes  35 A- 35 E (hereinafter may be referred to generically as second via electrodes  35 ) are formed in respective through-holes  41 X which penetrate through the second board body  41  in its thickness direction. The second wiring patterns  36 A- 36 F (hereinafter may be referred to generically as second wiring patterns  36 ) are formed on the top surface  41 A of the second board body  41 . Although not shown in any drawings, the second wiring patterns  36  used in the embodiment are, for example, approximately circular in a plan view. The cored solder balls  60 A- 60 F are provided between the first board  20  and the second board  40 . The first wiring members  31 , the first via electrodes  32 , the first wiring patterns  33 , the second wiring members  34 , the second via electrodes  35 , and the second wiring patterns  36  are made of copper or a copper alloy, for example. 
         [0058]    The first wiring member  31 A is connected to the two first via electrodes  32 A and  32 B. As shown in  FIG. 4 , the first wiring member  31 A has connection members C 1  and C 2  which are connected to the respective first via electrodes  32 A and  32 B and a wiring member W 1  which connects the connection members C 1  and C 2 . The connection members C 1  and C 2  and the wiring member W 1  are integrated together. For example, the connection members C 1  and C 2  are approximately circular in a plan view and the wiring member W 1  is approximately band-shaped in a plan view. 
         [0059]    As shown in  FIG. 7 , the first via electrode  32 A is electrically connected to the cored solder ball  60 A by the first wiring pattern  33 A. The cored solder ball  60 A is joined to the second wiring member  34 A via the second wiring pattern  36 A and the second via electrode  35 A. As a result, the first wiring member  31 A is electrically connected to the second wiring member  34 A via the first via electrode  32 A, the first wiring pattern  33 A, the cored solder ball  60 A, the second wiring pattern  36 A, and the second via electrode  35 A. As shown in  FIG. 6 , the second wiring member  34 A is, for example, approximately circular in a plan view. 
         [0060]    On the other hand, as shown in  FIG. 7 , the first via electrode  32 B is electrically connected to the cored solder ball  60 B by the first wiring pattern  33 B. The cored solder ball  60 B is electrically connected to the second wiring member  34 B via the second wiring pattern  36 B and the second via electrode  35 B. As a result, the first wiring member  31 A is electrically connected to the second wiring member  34 B via the first via electrode  32 B, the first wiring pattern  33 B, the cored solder ball  60 B, the second wiring pattern  36 B, and the second via electrode  35 B. 
         [0061]    The second wiring member  34 B is connected to the two second via electrodes  35 A and  35 B. As shown in  FIG. 6 , the second wiring member  34 B has connection members C 11  and C 12  which are connected to the respective second via electrodes  35 A and  35 B and a wiring member W 11  which connects the connection members C 11  and C 12 . The connection members C 11  and C 12  and the wiring member W 11  are integrated together. For example, the connection members C 11  and C 12  are approximately circular in a plan view and the wiring member W 11  is approximately band-shaped in a plan view. As shown in  FIG. 7 , the second via electrode  35 C is electrically connected to the first wiring member  31 B via the second wiring pattern  36 C, the cored solder ball  60 C, the first wiring pattern  33 C, and the first via electrode  32 C. As a result, the second wiring member  34 B is electrically connected to the first wiring member  31 B via the second via electrode  35 C, the second wiring pattern  36 C, the cored solder ball  60 C, the first wiring pattern  33 C, and the first via electrode  32 C. 
         [0062]    The first wiring member  31 B is connected to the two first via electrodes  32 C and  32 D. As shown in  FIG. 4 , the first wiring member  31 B has connection members C 3  and C 4  which are connected to the respective first via electrodes  32 C and  32 D and a wiring member W 2  which connects the connection members C 3  and C 4 . The connection members C 3  and C 4  and the wiring member W 2  are integrated together. For example, the connection members C 3  and C 4  are approximately circular in a plan view and the wiring member W 2  is approximately band-shaped in a plan view. As shown in  FIG. 7 , the first via electrode  32 D is electrically connected to the second wiring member  34 C via the first wiring pattern  33 D, the cored solder ball  60 D, the second wiring pattern  36 D, and the second via electrode  35 D. As a result, the first wiring member  31 B is electrically connected to the second wiring member  34 C via the first via electrode  32 D, the first wiring pattern  33 D, the cored solder ball  60 D, the second wiring pattern  36 D, and the second via electrode  35 D. 
         [0063]    The second wiring member  34 C is connected to the two second via electrodes  35 D and  35 E. As shown in  FIG. 6 , the second wiring member  34 C has connection members C 13  and C 14  which are connected to the respective second via electrodes  35 D and  35 E and a wiring member W 12  which connects the connection members C 13  and C 14 . The connection members C 13  and C 14  and the wiring member W 12  are integrated together. For example, the connection members C 13  and C 14  are approximately circular in a plan view and the wiring member W 12  is approximately band-shaped in a plan view. As shown in  FIG. 7 , the second via electrode  35 E is electrically connected to the first wiring member  31 C via the second wiring pattern  36 E, the cored solder ball  60 E, the first wiring pattern  33 E, and the first via electrode  32 E. As a result, the second wiring member  34 C is electrically connected to the first wiring member  31 C via the second via electrode  35 E, the second wiring pattern  36 E, the cored solder ball  60 E, the first wiring pattern  33 E, and the first via electrode  32 E. 
         [0064]    As shown in  FIG. 4 , the first wiring member  31 C has a connection member C 5  which is connected to the first via electrode  32 E and wiring members W 3  and W 4 , and a connection member C 6 . The connection members C 5  and C 6  and the wiring members W 3  and W 4  are integrated together. For example, the connection members C 5  and C 6  are approximately circular in a plan view and the wiring members W 3  and W 4  are approximately L-shaped in a plan view. 
         [0065]    The wiring member W 3  electrically connects the connection member C 5  and the ground line  24 . As a result, the entire antenna  30  is connected to the ground lines  24 . The wiring member W 4  electrically connects the wiring member W 3  and the connection member C 6 . As a result, the connection member C 5  is electrically connected to the connection member C 6  via the wiring members W 3  and W 4 . The connection member C 6  is electrically connected to the cored solder ball  60 F shown in  FIG. 3  via a first via electrode  32  and a first wiring pattern  33  (neither of which is shown). The cored solder ball  60 F is electrically connected to a connection member C 21  of the second wiring pattern  36 F (see  FIG. 5 ). 
         [0066]    The second wiring pattern  36 F has the above-mentioned connection member C 21 , a connection member C 22  which is formed in the RF IC mounting region R 2 , and a wiring member W 21  which connects the connection members C 21  and C 22 . The connection members C 21  and C 22  and the wiring member W 21  are integrated together. For example, the connection members C 21  and C 22  are approximately circular in a plan view and the wiring member W 21  is band-shaped in a plan view. The connection member C 21  is electrically connected to the RF IC chip  71  which is mounted in the RF IC mounting region R 2 . As a result, the entire antenna  30  is electrically connected to the RF IC chip  71 . 
         [0067]    Although actually the above-described first wiring members  31 A- 31 C, second wiring members  34 A- 34 C, and wiring member W 21  of the second wiring pattern  36 F are covered with solder resist layers, the solder resist layers are not shown in  FIGS. 1A and 7  to facilitate understanding of the sectional structures of the individual members. For example, connection pads  26  and  47  shown in  FIG. 7  and the corresponding cored solder ball  60  are used for connection to signal lines for signal exchange between the control IC chip  70  and the RF IC chip  71  or as dummy pads and dummy connection terminals. The purpose of using them as dummy pads and dummy connection terminals is to increase the strength of the joining of the first board  20  and the second board  40  and join the first board  20  and the second board  40  together in such a manner that they are set parallel with each other. For example, the connection pads  50  shown in  FIG. 7  are used for connection to signal lines for signal exchange between the RF IC chip  71 , for example, and a mounting board or as dummy pads. Where they are used as dummy pads, external connection terminals  75  are formed on the respective dummy pads (connection pads  50 ) to increase the strength of the joining of the semiconductor device  10  and the mounting board and join the semiconductor device  10  and the mounting board together in such a manner that they are set parallel with each other. 
         [0068]    Next, a description will be made of how advantages of the semiconductor device  10  are obtained. Part of the cored solder balls  60  which are connection terminals for joining and electrically connecting the first board  20  and the second board  40  are used as part of the antenna  30 . With this measure, the height of these cored solder balls  60  (i.e., the interval between the first board  20  and the second board  40 ) can be utilized as part of the wiring length of the antenna  30 , whereby the wiring length of the antenna  30  can easily be made long. Since the height of these cored solder balls  60  is greater than the thicknesses of the first board body  21  and the second board body  41 , the wiring length of the antenna  30  can be set longer than in the conventional case in which the wiring length of the antenna  120  is increased utilizing the thickness of the board body  111 . 
         [0069]    Therefore, even in the case of designing a low-frequency antenna which requires a long wiring length, increase of the areas occupied by the first wiring members  31  and the first wiring patterns  33  or the second wiring members  34  and the first wiring patterns  36  can be prevented. In other words, even if the areas occupied by the first wiring members  31  are set small, the wiring length of the antenna  30  can be set to a desired length (e.g., a length suitable for a low frequency) by utilizing the length in the stacking direction of the first board body  21 , the second board body  41  or the like. Since in this manner the horizontal area of the first board  20  and the second board  40  can be made small, the first board  20  and the second board  40 , and hence the semiconductor device  10 , can be miniaturized. 
         [0070]    Next, a manufacturing method of the semiconductor device  10  will be described. First, a first board  20  and a second board  40  are prepared as shown in  FIG. 8A . Since the first board  20  and the second board  40  can be manufactured by known manufacturing methods, this manufacturing step will be described below briefly with reference to  FIG. 8A . 
         [0071]    The first board  20  is manufactured by forming through-holes  21 X through a copper-clad laminate (CCL), for example, then forming first via electrodes  32  etc. in the respective through-holes  21 X by electroplating, paste charging, or some other method, and finally forming first wiring members  31 , the first wiring patterns  33  or the like by a subtractive method. Likewise, the second board  40  is manufactured by forming through-holes  41 X through a copper-clad laminate, for example, then forming second via electrodes  35  in the respective through-holes  41 X by electroplating, paste charging, or some other method, and finally forming second wiring members  34 , the second wiring patterns  36  or the like by a subtractive method. Subsequently, a control IC chip  70  is mounted on the top surface  21 A of the first board body  21  of the first board  20  (e.g., by flip-chip mounting or wire bonding). And an RF IC chip  71  and passive elements  72  are mounted on the top surface  41 A of the second board body  41  of the second board  40  (e.g., by flip-chip mounting or soldering). 
         [0072]    Furthermore, in the step shown in  FIG. 8A , cored solder balls  60  are provided on (joined to) the first wiring patterns  33  and the connection pads  26  which are formed on the bottom surface  21 B of the first board body  21 . For example, after flux is applied to the first wiring patterns  33  and the connection pads  26  if necessary, cored solder balls  60  are provided on the first wiring patterns  33  and the connection pads  26  and fixed to them by reflow at about 230° C. to 260° C. Then the surface is cleaned and the flux is removed. 
         [0073]    Subsequently, the first board  20  which is mounted with the control IC chip  70  and the cored solder balls  60  is disposed over the second board  40  which is mounted with the RF IC chip  71  and the passive elements  72 . More specifically, as shown in  FIG. 8A , the bottom surface  21 B of the first board body  21  and the top surface  41 A of the second board body  41  are opposed to each other and the first board body  21  and the second board body  41  are positioned with respect to each other so that the cored solder balls  60  are opposed to the connection pads  47  and the second wiring patterns  36 . 
         [0074]    In the next step shown in  FIG. 8B , the cored solder balls  60  are joined to the connection pads  47  and the second wiring patterns  36 , respectively. More specifically, first, flux is applied to the connection pads  47  and the second wiring patterns  36  if necessary. Subsequently, the first board  20  is disposed on the second board  40  with the cored solder balls  60  sandwiched therebetween, and the thus-combined first board  20  and second board  40  are heated in a reflow furnace at about 230° C. to 260° C. The cored solder balls  60  are melted and joined to the connection pads  47  and the second wiring patterns  36 . As a result, the first wiring members  31 , the first via electrodes  32 , the first wiring patterns  33 , the cored solder balls  60 , the second wiring patterns  36 , the second via electrodes  35 , and the second wiring members  34  are electrically connected mutually and thus an antenna  30  is formed. In this step, reflow is performed while the first board  20  is pressed against the second board  40 , and the copper core balls  61  of the cored solder balls  60  function as spacers and keep the interval between the first board  20  and the second board  40  at a prescribed value. 
         [0075]    In the next step shown in  FIG. 8C , external connection terminals  75  are formed on the respective connection pads  50 . For example, after flux is applied to the connection pads  50  if necessary, the external connection terminals  75  are provided on the connection pads  50  and fixed to them by reflow at about 240° C. to 260° C. Then the surface is cleaned and the flux is removed. The manufacturing process of the semiconductor device  10  is thus completed. 
         [0076]    The above-described embodiment provides the following advantages: 
         [0077]    (1) Part of the cored solder balls  60  which are connection terminals for joining and electrically connecting the first board  20  and the second board  40  are used as part of the antenna  30 . With this measure, the height of these cored solder balls  60  (i.e., the interval between the first board  20  and the second board  40 ) can be utilized as part of the wiring length of the antenna  30 , whereby the wiring length of the antenna  30  can easily be made long. Since in this manner the horizontal area of the first board  20  and the second board  40  can be made small, the first board  20  and the second board  40 , and hence the semiconductor device  10 , can be miniaturized. 
         [0078]    Since the height of these cored solder balls  60  is utilized as part of the wiring length of the antenna  30 , the wiring length of the antenna  30  can be increased without increasing the horizontal area of the first board  20  and the second board  40  and the characteristics of the antenna  30  can thereby be improved. 
         [0079]    (2) In addition to the above cored solder balls  60 , the first via electrodes  32  formed through the first board body  21  and the second via electrodes  35  formed through the second board body  41  are used as part of the antenna  30 . With this measure, in addition to the height of the above cored solder balls  60 , the thicknesses of the first board body  21  and the second board body  41  can be utilized as part of the wiring length of the antenna  30 , whereby the wiring length of the antenna  30  can be made long even more easily. Since in this manner the horizontal area of the first board  20  and the second board  40  can be made even smaller, the first board  20  and the second board  40 , and hence the semiconductor device  10 , can be miniaturized easily. 
       Modified Embodiments 
       [0080]    The above-described embodiment is applicable to modified embodiments described below. 
         [0081]    In the above embodiment, the cored solder balls  60  are used as the connection terminals for connecting the first board  20  and the second board  40 . Instead of the cored solder balls  60 , connection terminals having spring characteristic (spring connection terminals), metal posts which are columnar connection terminals, or the like may be used as the connection terminals for connecting the first board  20  and the second board  40 . In this case, part of the spring connection terminals, the metal posts, or the like are used as part of the antenna  30 . Thus, the same advantages provided by the above embodiment can be obtained. 
         [0082]      FIG. 9  shows a semiconductor device  10 A in which spring connection terminals  80  are used as the connection terminals for connecting the first board  20  and the second board  40 . 
         [0083]    As shown in  FIG. 9 , the spring connection terminals  80  are sandwiched between the first board  20  and the second board  40 . One end of each spring connection terminal  80  is joined to a connection pad  26  or a first wiring pattern  33  and the other end is joined to a connection pad  47  or a second wiring pattern  36 . Each spring connection terminal  80  has a spring portion  81  and joining portions  82  and  83  which are integrated together. The spring connection terminals  80  are made of a metal material having a proper level of elasticity (spring characteristic, bending characteristic) and can be manufactured by subjecting a thin metal sheet having a uniform thickness to punching such as stamping and then bending resulting pieces. Example materials of the thin metal sheet are copper-based alloys such as beryllium copper (Cu—Be), phosphor bronze (Cu—Sn), and Corson alloys (Cu—Ni—Si—Mg, Cu—Ni—Si, Cu—Ni—Co—Si—Cr, etc.). 
         [0084]    The joining portion  82  is joined to the connection pad  26  or the first wiring pattern  33  which is formed on the bottom surface  21 B of the first board body  21 . For example, the joining portion  82  is soldered to the connection pad  26  or the first wiring pattern  33 . The joining portion  82  is continuous with the top end of the spring portion  81 , wider than the spring portion  81 , and flat. 
         [0085]    The joining portion  83  is joined to the connection pad  47  or the second wiring pattern  36  which is formed on the top surface  41 A of the second board body  41 . For example, the joining portion  83  is soldered to the connection pad  47  or the second wiring pattern  36 . The joining portion  83  is continuous with the bottom end of the spring portion  81 , wider than the spring portion  81 , and flat. 
         [0086]    The spring portion  81  is located between the joining portions  82  and  83 , and is curved outward (i.e., so as to go away from the joining portions  82  and  83 ). For example, the spring portion  81  is C-shaped or inverted-C-shaped in a side view. Shaped in this manner, the spring portion  81  can be deformed elastically in its height direction (i.e., in the stacking direction of the first board  20  and the second board  40 ). The spring constant of the spring portion  81  may be set at about 0.6 to 0.8 N/mm, for example. 
         [0087]    In the thus-configured semiconductor device  10 A, part of the spring connection terminals  80  are used as part of the antenna  30 . That is, the antenna  30  has the first wiring members  31 , the first via electrodes  32 , the first wiring patterns  33 , the second wiring members  34 , the second via electrodes  35 , the second wiring patterns  36 , and the spring connection terminals  80 . The first wiring members  31 , the first via electrodes  32 , and the first wiring patterns  33  which are formed in the first board  20  are electrically connected to the second wiring members  34 , the second via electrodes  35 , and the second wiring patterns  36  which are formed in the second board  40  by the spring connection terminals  80 . 
         [0088]    Since part of the spring connection terminals  80  are used as part of the antenna  30 , the lengths of these curved spring connection terminals  80  can be utilized as part of the wiring length of the antenna  30 , whereby the wiring length of the antenna  30  can easily be made long. 
         [0089]    In the above modification, the two end portions of each spring connection terminal  80  is joined to the connection pad  26  and  47 , respectively, or the first wiring pattern  33  and the second wiring pattern  36 , respectively. Alternatively, electrical continuity between the first board  20  and the second board  40  may be established by joining only one end portion (e.g., joining portion  83 ) of each spring connection terminal  80  to the connection pad  47  or the second wiring pattern  36  and pressing the connection pad  26  or the first wiring pattern  33  against the other end portion (e.g., joining portion  82 ). 
         [0090]    In the above-described embodiment, the copper core ball  61  is used as the conductive core ball of each cored solder ball  60 . Instead of the copper core ball  61 , a conductive core ball made of a metal other than copper, such as gold or nickel or a resin core ball may be used. As a further alternative, a solder ball may be used instead of each cored solder ball  60  (i.e., no conductive core ball or resin core ball is used). 
         [0091]    In the above embodiment and modified embodiment, no particular limitations are imposed on the configuration of the antenna  30 . For example, as shown in  FIG. 10 , an antenna  30 A is possible which is different from the antenna  30  according to the embodiment in that the second via electrodes  35  and the second wiring members  34  are omitted. The antenna  30 A has the first wiring members  31 A- 31 C, the first via electrodes  32 A- 32 E, the first wiring patterns  33 A- 33 E, second wiring patterns  37 A- 37 C, the cored solder balls  60 A- 60 F, and the second wiring pattern  36 F shown in  FIG. 3 . The first wiring members  31 A- 31 C, the first via electrodes  32 A- 32 E, and the first wiring patterns  33 A- 33 E which are formed in the first board  20  are electrically connected, by the cored solder balls  60 A- 60 F, to the second wiring patterns  37 A- 37 C and  36 F which are formed on the top surface  41 A of the second board body  41 . A semiconductor device that is equipped with the thus-configured antenna  30 A provides the same advantages as the semiconductor device  10  according to the embodiment. 
         [0092]    Another antenna is possible which is different from the antenna  30 A in that the first wiring patterns  33 A- 33 E are omitted. In this case, for example, the cored solder balls  60 A- 60 E are joined to the bottom surfaces of the respective first via electrodes  32 A- 32 E. 
         [0093]    An antenna is possible which is different from the antenna  30  according to the embodiment in that conversely to the antenna  30 A the first wiring members  31  and the first via electrodes  32  are omitted. The second wiring patterns  36  may further be omitted, in which case, for example, the cored solder balls  60 A- 60 E are joined to the top surfaces of the respective second via electrodes  35 A- 35 E. 
         [0094]    As shown in  FIG. 11 , an antenna  30 B is possible which is different from the antenna  30  according to the embodiment in that the first wiring members  31 A- 31 C, the first via electrodes  32 A- 32 E, the second via electrodes  35 , and the second wiring members  34  are omitted. The antenna  30 B has first wiring patterns  38 A- 38 C, second wiring patterns  37 A- 37 D, and cored solder balls  60 A- 60 E and  60 G. In the antenna  30 B, the first wiring patterns  38 A- 38 C are electrically connected to the second wiring patterns  37 A- 37 D by the cored solder balls  60 A- 60 E and  60 G. For example, the second wiring patterns  37 D extends to the RF IC mounting region R 2  and is electrically connected to the RF IC chip  71  which is mounted in the RF IC mounting region R 2 . Although not shown in  FIG. 11 , the antenna  30 B is electrically connected to the ground lines and a power line. A semiconductor device that is equipped with the thus-configured antenna  30 B also provides the advantage (1) of the semiconductor device  10  according to the embodiment. 
         [0095]    Electrodes corresponding to the first via electrodes  32  used in the embodiment or each modification may be formed on a side surface of the first board body  21  (or cuts formed in a side surface of the first board body  21 ). 
         [0096]    Electrodes corresponding to the second via electrodes  35  used in the embodiment or each modified embodiment may be formed on a side surface of the second board body  41  (or cuts formed in a side surface of the second board body  41 ). 
         [0097]    In the above embodiment, the space between the first board  20  and the second board  40  may be filled with a resin material which may be an insulative resin such as an epoxy resin or a polyimide resin. An epoxy resin, for example, mixed with a filler such as silica (SiO 2 ) may also be used as the resin material. A mold resin formed by transfer molding, compression molding, injection molding, or the like may also be used as the resin material. 
         [0098]    Although the antenna used in the semiconductor device according to the embodiment or each modification is an inverted-F antenna, the concept of the embodiment or each modified embodiment may be applied to a semiconductor device having an antenna other than an inverted-F antenna, such as an inverted-L antenna. 
         [0099]    As described above, the preferred embodiment and the modifications are described in detail. However, the present invention is not limited to the above-described embodiment and the modifications, and various modifications and replacements are applied to the above-described embodiment and the modifications without departing from the scope of claims.