Abstract:
The invention is directed to an amplifier including an absolute value circuit. The absolute value circuit may be driven by differential potentials and may include a first pair of transistors modulating a tail current of the amplifier when a differential input voltage goes high, and a second pair of transistors modulating the tail current of the amplifier when a differential input voltage goes low.

Description:
BACKGROUND 
       [0001]    Amplifiers are used in many environments and are one of the most widely used electronic devices. Typical amplifiers receive a differential voltage and have a single output. Fully differential amplifiers may receive a differential voltage and have a differential output. Typically the output of the amplifier is controlled either by negative feedback, which largely determines the magnitude the voltage gain, or by positive feedback, which facilitates regenerative gain and oscillation (i.e., it attempts to keep the input constant). 
         [0002]      FIG. 1  illustrates a front end of a fully differential amplifier  100 . The amplifier may include a first transistor  101  receiving a first input voltage Vip at a positive input terminal and a second transistor  102  receiving a second input voltage Vin at a negative input terminal of the amplifier  100 . The output Iout of the amplifier  100  is the difference in current between the collectors of transistors  101  and  102  (i.e., Ip−In). The output Iout is based upon the input voltages Vip and Vin and the tail current Itail present at the emitters of transistors  101  and  102 . The tail current is controlled by current mirror  103 . The current mirror may include a first transistor  104 , controlled by a fixed current source  106 , and a second transistor  105 , which provides the tail current Itail to the differential transistors  101  and  102 . The current mirror attempts to match the current passing through transistor  104  into transistor  105 . Accordingly Itail will be approximately equal to Ibias. 
         [0003]    When there is a large differential input voltage (i.e., when the difference between the input to the positive terminal and the negative terminal of the amplifier is large), the output of the amplifier tends to become distorted because the transconductance Gm of the input transistors in the amplifier is non-linear.  FIG. 1   b  illustrates the output current versus the differential input voltages for the amplifier illustrated in  FIG. 1   a . Ideally the output current would be linear over a large range of differential input voltages, as indicated in  FIG. 1   b . However, because of the non-linear output current behavior of the transistors in the amplifier, the actual current output from the amplifier becomes distorted. Transconductance is the derivative of ratio of the current at the output port and the voltage at the input ports (Gm=(ΔIout/ΔVinput) of the amplifier. For the amplifier illustrated in  FIG. 1   a , the transconductance can be calculated using equation 1.1: 
         [0000]    
       
         
           
             
               
                 
                   Gm 
                   = 
                   
                     
                       ( 
                       
                         
                           
                             α 
                             F 
                           
                           × 
                           
                             I 
                             tail 
                           
                         
                         
                           2 
                           × 
                           
                             V 
                             T 
                           
                         
                       
                       ) 
                     
                      
                     
                       ( 
                       
                         1 
                         - 
                         
                           
                             tanh 
                             2 
                           
                            
                           
                             ( 
                             
                               
                                 
                                   V 
                                   ip 
                                 
                                 - 
                                 
                                   V 
                                   in 
                                 
                               
                               
                                 2 
                                 × 
                                 
                                   V 
                                   T 
                                 
                               
                             
                             ) 
                           
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   1.1 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where α F  is ratio of collector current to emitter current of transistors  101  and  102  and V T  is the thermal voltage of transistors  101  and  102 . Because of the distortion caused by the transconductance of the amplifier at large differential input voltages the output of the amplifier becomes distorted. As seen in  FIG. 1   c , the transconductance Gm of the amplifier is shaped like a bell curve. Accordingly, as the differential input voltage deviates from the operating point (i.e. zero), the output of the amplifier becomes distorted. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]      FIG. 1   a  is illustrates a conventional differential amplifier front end; 
           [0005]      FIG. 1   b  illustrates a comparison between the output current and the input differential voltages for the amplifier illustrated in  FIG. 1 ; 
           [0006]      FIG. 1   c  is illustrates a comparison between the transconductance and the input differential voltages for the amplifier illustrated in  FIG. 1 ; 
           [0007]      FIG. 2   a  illustrates an exemplary amplifier according to one embodiment of the present invention; 
           [0008]      FIG. 2   b  illustrates a comparison between the output current and the input differential voltages for the amplifier illustrated in  FIG. 2   a;    
           [0009]      FIG. 2   c  illustrates a comparison between the transconductance and the input differential voltages for the amplifier illustrated in  FIG. 2   a;    
           [0010]      FIG. 3  illustrates another exemplary amplifier according to one embodiment of the present invention; 
           [0011]      FIG. 4   a  illustrates an exemplary absolute value circuit in accordance with the present invention; 
           [0012]      FIG. 4   b  illustrates a comparison of the current flowing through the absolute value circuit illustrated in  FIG. 4   a  for various input voltages Vipp−Vinn; 
           [0013]      FIG. 5   a  illustrates a comparison of the output voltage of the amplifier illustrated in  FIG. 3  over a range of input voltages Vin; 
           [0014]      FIG. 5   b  illustrates a comparison of the transconductance the amplifier illustrated in  FIG. 3  over a range of input voltages Vin; 
           [0015]      FIG. 6  illustrates yet another exemplary amplifier according to one embodiment of the present invention; 
           [0016]      FIG. 7   a  illustrates a further exemplary amplifier according to one embodiment of the present invention. 
           [0017]      FIG. 7   b  illustrates a comparison of the current output from that absolute value circuit versus the input voltage to the amplifier illustrated in  FIG. 7   a  over a range of gain values K; 
           [0018]      FIG. 7   c  illustrates a comparison of the output current versus the input current Vin (Vipp−Vinn) for various gain values K at a design ratios of X:1; 
           [0019]      FIG. 7   d  illustrates a comparison of the normalized transconductance verses the input voltages Vin (Vip−Vin) for various gain values K at a design ratio of X:1; 
           [0020]      FIG. 8  illustrates another exemplary amplifier according to one embodiment of the present invention; 
           [0021]      FIG. 9   a  illustrates yet another exemplary current modulator according to one embodiment of the present invention; 
           [0022]      FIG. 9   b  a comparison of the output current versus the input current (Vip−Vin) for the current modulator illustrated in  FIG. 9   a.    
       
    
    
     DETAILED DESCRIPTION 
       [0023]    Embodiments of the present invention provide an input stage for an operational amplifier including a current modulator that supplies a source current in common to a pair of transistors driven by differential input signals. The source current is modulated according to the differential input signals as well. When the differential input signals are equal, the source current is at its minimum. The source current increases as the input signals deviate. Coupled with the varying conductance of the transistors, the input stage generates output currents with improved linear behavior as compared to designs with non-modulated source currents. 
         [0024]    An exemplary embodiment of an amplifier  200  in accordance with the present invention can be seen in  FIG. 2   a . The amplifier  200  may include a differential amplifier  201 , current modulator  207  and current mirror  204 . The differential amplifier  201  may include a first transistor  202  receiving a first input voltage Vip and a second transistor  203 , matched to the first transistor  202  (i.e., having the same properties), receiving a second input voltage Vin. 
         [0025]    The amplifier  200  may further include a current mirror  204 , which may include matching transistors  205  and  206  and resistors R 1  and R 2 . The current mirror attempts to match the current Itail to the current Iabs_out. The current Iabs_out is controlled by the current modulator  207 . 
         [0026]    The current modulator  207  may generate an output current I ABS     —     OUT  whose magnitude varies based on the differential input voltages supplied to the amplifier. The output current I ABS     —     OUT  may follow a profile as shown in  FIG. 2   b . As shown, the output current may have its minimum value when the input voltages are equal to each other (Vip=Vin). However, as the input voltages become unbalanced, the output current increases. The current modulator  207  may become saturated at some point, at which point the output current reaches a maximum value. The output current from the current modulator  207  may be mirrored as the source current to the amplifier  201  via current mirror  204 . 
         [0027]    The current modulator  207  may receive input voltages Vipp and Vinn. Input voltages Vipp and Vinn may be based upon input voltages Vip and Vin, respectively. Vipp and Vinn may, for example, be modulated versions of Vip and Vin. By adjusting the voltage of Vipp and Vinn the profile of the output current I ABS     —     OUT  may be further modified, as described in further detail below. 
         [0028]    The differentially driven transistors of amplifier  201  provide further modulation to the source current. Considered in combination, the aggregate output current from the amplifier  201  (the difference of IP and IN) provides improved linearity over prior designs, as shown in  FIG. 2   c.    
         [0029]      FIG. 3  illustrates an amplifier  300  in which the current modulator is provided as an absolute value circuit. The absolute value circuit may include transistors  305  and  307  having a same relative size and transistors  306  and  308  having a same relative size. The collectors of transistors  305  and  307  may be connected and the collectors of transistors  306  and  308  are connected. Further, the emitters of transistors  305  and  306  are connected to a current source  309  and the emitters of  307  and  308  may be connected to a current source  310 . The base of transistors  305  and  308  may receive a modulated input voltage Vipp. The base of transistors  306  and  307  may receive a modulated input voltage Vinn. 
         [0030]    The output Iout of the amplifier  300  is equal to Ip−In, where Ip is the current output from transistor  301  and In is the current output from transistor  302 . Iout may also be represented by equation 1.2: 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     OUT 
                   
                   = 
                   
                     
                       ( 
                       
                         
                           I 
                           P 
                         
                         - 
                         
                           I 
                           N 
                         
                       
                       ) 
                     
                     = 
                     
                       
                         α 
                         F 
                       
                       × 
                       
                         I 
                         TAIL 
                       
                       × 
                       
                         tanh 
                          
                         
                           ( 
                           
                             
                               
                                 V 
                                 IP 
                               
                               - 
                               
                                 V 
                                 IN 
                               
                             
                             
                               2 
                               × 
                               
                                 V 
                                 T 
                               
                             
                           
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   1.2 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where α F  is relationship of collector current (output current) to emitter current (input current) of transistors  301  and  302  and V T  is the thermal voltage of transistors  301  and  302 . Accordingly, by using an absolute value circuit  207  to modulate the tail current Itail, the output Iout of amplifier  300  can be controlled. 
         [0031]      FIG. 4   a  illustrates the flow of current for an exemplary absolute value circuit  400 . The absolute value circuit may include transistors  401  and  402 , connected at their respective emitters and transistors  403  and  404  connected at their respective emitters. Transistors  401  and  403  may be matched transistors of a predetermined size. Further, transistors  402  and  404  may be matched and may be designed to be larger than transistors  401  and  403  by a design factor X. As seen in  FIG. 4   a , current Iabs_out is formed by currents Iabs_p and Iabs_n. 
         [0032]    As seen in  FIG. 4   b , when Vipp−Vinn is equal to or greater than 0.25V, transistor  401  supplies most of Iabs_out and transistor  403  supplies virtually none of Iabs_out. Conversely, when Vipp−Vinn is equal to −0.25V, transistor  403  supplies most of Iabs_out and transistor  401  supplies virtually none of Iabs_out. However, because both currents are added together by the absolute value circuit  400 , Iabs_out, which is designated by the solid line in  FIG. 4   b , has the same current at positive or negative excursions from the operating point. 
         [0033]    In order to improve the linearity of the transconductance Gm of the amplifier, it is preferable to have a relative minimum output current Iabs_out of the absolute value circuit at the operating point (when Vipp is approximately equal to Vinn) and a relative maximum output current at large input differential voltages. In one embodiment, this effect (i.e., shaping the transconductance of the amplifier) is achieved by changing the relative sizing of transistors  401 - 404 .  FIG. 4   b , for example, illustrates the flow of current through the absolute value circuit  400  when transistors  402  and  404  are 4 times the size of transistors  401  and  403 . Iabs_p and Iabs_n can be calculated using equations 1.3 and 1.4: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       abs_p 
                     
                     = 
                     
                       
                         α 
                         F 
                       
                       × 
                       
                         I 
                         abs_tail 
                       
                        
                       
                         
                           { 
                           
                             1 
                             + 
                             
                               exp 
                                
                               
                                 [ 
                                 
                                   
                                     ( 
                                     
                                       
                                         
                                           - 
                                           
                                             V 
                                             ipp 
                                           
                                         
                                         - 
                                         
                                           V 
                                           inn 
                                         
                                       
                                       
                                         V 
                                         T 
                                       
                                     
                                     ) 
                                   
                                   + 
                                   
                                     ln 
                                      
                                     
                                         
                                     
                                      
                                     X 
                                   
                                 
                                 ] 
                               
                             
                           
                           } 
                         
                         
                           - 
                           1 
                         
                       
                     
                   
                    
                   
                     
 
                   
                    
                   
                     
                       I 
                       abs_p 
                     
                     = 
                     
                       
                         α 
                         F 
                       
                       × 
                       
                         I 
                         abs_tail 
                       
                        
                       
                         
                           { 
                           
                             1 
                             + 
                             
                               exp 
                                
                               
                                 [ 
                                 
                                   
                                     - 
                                     
                                       ( 
                                       
                                         
                                           
                                             - 
                                             
                                               V 
                                               ipp 
                                             
                                           
                                           - 
                                           
                                             V 
                                             inn 
                                           
                                         
                                         
                                           V 
                                           T 
                                         
                                       
                                       ) 
                                     
                                   
                                   + 
                                   
                                     ln 
                                      
                                     
                                         
                                     
                                      
                                     X 
                                   
                                 
                                 ] 
                               
                             
                           
                           } 
                         
                         
                           - 
                           1 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   1.3 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where α F  is relationship of collector current (output current) to emitter current (input current) of transistors  401  (eq. 1.3) and  403  (eq. 1.4), V T  is the thermal voltage of transistors  401  and  403  and X is the design factor (ratio of the size of transistor  401  to transistor  402  (eq. 1.3) and  403  to  404  (eq. 1.4)). Because transistor  401  is in parallel with transistors  403 , the output of the absolute value circuit Iabs_out is the combination of Iabs_p and Iabs_n and may be calculated using equations 1.5: 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     abs_out 
                   
                   = 
                   
                     
                       α 
                       F 
                     
                      
                     
                       
                         I 
                         abs_tail 
                       
                        
                       
                         [ 
                         
                           
                             
                               
                                 
                                   
                                     { 
                                     
                                       1 
                                       + 
                                       
                                         exp 
                                          
                                         
                                           ( 
                                           
                                             
                                               ( 
                                               
                                                 
                                                   
                                                     - 
                                                     
                                                       V 
                                                       ipp 
                                                     
                                                   
                                                   - 
                                                   
                                                     V 
                                                     inn 
                                                   
                                                 
                                                 
                                                   V 
                                                   T 
                                                 
                                               
                                               ) 
                                             
                                             + 
                                             
                                               ln 
                                                
                                               
                                                   
                                               
                                                
                                               X 
                                             
                                           
                                           ) 
                                         
                                       
                                     
                                     } 
                                   
                                   
                                     - 
                                     1 
                                   
                                 
                                 + 
                               
                             
                           
                           
                             
                               
                                 
                                   { 
                                   
                                     1 
                                     + 
                                     
                                       exp 
                                        
                                       
                                         ( 
                                         
                                           
                                             - 
                                             
                                               ( 
                                               
                                                 
                                                   
                                                     - 
                                                     
                                                       V 
                                                       ipp 
                                                     
                                                   
                                                   - 
                                                   
                                                     V 
                                                     inn 
                                                   
                                                 
                                                 
                                                   V 
                                                   T 
                                                 
                                               
                                               ) 
                                             
                                           
                                           + 
                                           
                                             ln 
                                              
                                             
                                                 
                                             
                                              
                                             X 
                                           
                                         
                                         ) 
                                       
                                     
                                   
                                   } 
                                 
                                 
                                   - 
                                   1 
                                 
                               
                             
                           
                         
                         ] 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1.5 
                   ) 
                 
               
             
           
         
       
     
         [0000]    As seen in  FIG. 4   b , Iabs_out, represented by the solid line is the sum of Iabs_p (represented by the dotted line) and Iabs_n (represented by the dot-dash line) and has a relative maximum current at large differential inputs and a relative minimum current when Vipp is equal to Vinn. In one embodiment, the relative ratio X:1 of the transistors was selected to be 4:1. 
         [0034]      FIG. 5   a  illustrates the output current Iout versus the input current (Vip−Vin) for various design ratios X:1. As seen in  FIG. 5   a , as X increases from 1 to 4, the output current Iout becomes more linear. As X increases from 4 to 8, the absolute value circuit begins to overcorrect the transconductance. 
         [0035]      FIG. 5   b  illustrates the normalized transconductance verses the input voltages Vin (Vip−Vin) for various design ratios X. As seen in  FIG. 5   a , as the design ratio increases from 1 to 4, the transconductance Gm remains around 1 for a larger range of input voltages. Ideally, the larger the voltage range for which the transconductance remains flat (i.e., at 1 in this example), the more linear the output current Iout will be over that range of input voltages. 
         [0036]      FIG. 6  illustrates another embodiment of an amplifier  600 . The amplifier  600  may include including a first transistor  601  receiving a first input voltage Vip and a second transistor  602 , matched to the first transistor  601  (i.e., having the same properties), receiving a second input voltage Vin. The amplifier  600  may further include a current mirror  603 , which may include matching transistors  604  and  605  and resistors R 1  and R 2 . The current mirror attempts to match the current Itail to the current Iabs_out. The current Iabs_out is controlled by the absolute value circuit  606 . 
         [0037]    The amplifier  600  may further include a differential sensing circuit  607 . The differential sensing circuit may receive as its input, the input voltages Vip and Vin input into the amplifier. Based upon the input voltages, the differential sensing circuit may tune the transconductance of the amplifier to reduce distortion. This circuit may be used, for example, to modulate the input voltages Vin and Vip to provide the modulated voltages Vipp and Vinn to the current modulators discussed above. The differential voltage input to the absolute value circuit (Vipp and Vinn) is shifted, based upon a gain K, from the differential voltage input into the amplifier  600  (Vip and Vin). The modulated differential input voltage (Vipp−Vinn)=K×(Vip−Vin). The output current Iabs_out can be calculated using equations 1.6: 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     abs_out 
                   
                   = 
                   
                     
                       α 
                       F 
                     
                      
                     
                       
                         I 
                         abs_tail 
                       
                        
                       
                         [ 
                         
                           
                             
                               
                                 
                                   
                                     { 
                                     
                                       1 
                                       + 
                                       
                                         exp 
                                          
                                         
                                           ( 
                                           
                                             
                                               k 
                                                
                                               
                                                 ( 
                                                 
                                                   
                                                     
                                                       - 
                                                       
                                                         V 
                                                         ipp 
                                                       
                                                     
                                                     - 
                                                     
                                                       V 
                                                       inn 
                                                     
                                                   
                                                   
                                                     V 
                                                     T 
                                                   
                                                 
                                                 ) 
                                               
                                             
                                             + 
                                             
                                               ln 
                                                
                                               
                                                   
                                               
                                                
                                               X 
                                             
                                           
                                           ) 
                                         
                                       
                                     
                                     } 
                                   
                                   
                                     - 
                                     1 
                                   
                                 
                                 + 
                               
                             
                           
                           
                             
                               
                                 
                                   { 
                                   
                                     1 
                                     + 
                                     
                                       exp 
                                        
                                       
                                         ( 
                                         
                                           
                                             - 
                                             
                                               k 
                                                
                                               
                                                 ( 
                                                 
                                                   
                                                     
                                                       - 
                                                       
                                                         V 
                                                         ipp 
                                                       
                                                     
                                                     - 
                                                     
                                                       V 
                                                       inn 
                                                     
                                                   
                                                   
                                                     V 
                                                     T 
                                                   
                                                 
                                                 ) 
                                               
                                             
                                           
                                           + 
                                           
                                             ln 
                                              
                                             
                                                 
                                             
                                              
                                             X 
                                           
                                         
                                         ) 
                                       
                                     
                                   
                                   } 
                                 
                                 
                                   - 
                                   1 
                                 
                               
                             
                           
                         
                         ] 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1.6 
                   ) 
                 
               
             
           
         
       
     
         [0038]      FIG. 7   a  illustrates an amplifier  700  using an exemplary differential sensing circuit. The output of the absolute value circuit  705  is modified based upon a gain value K which is generated by the differential sensing circuit. The differential sense circuit may include transistors  706  and  707  whose collectors are connected by resister R 5 . The collector of transistor  706  may be connected in series with resister R 6 , while the collector of transistor  707  is connected in series with resister R 7 . The base of transistor  706  may be connected to the positive input terminal receiving voltage Vip. Conversely, the base of transistor  707  may be connected to the negative input terminal receiving voltage Vin. Resister R 6  is connected to the base of transistor  709 , while resister R 7  is connected to the base of transistor  708 . 
         [0039]    At Vip−Vin=0, no current flows through R 5 . Transistors  710  and  711 , which receive a bias voltage from voltage source  712 , are current sources pushing equal amount of current through  706  and  707 . When Vip−Vin is not equal to 0 more current is steered to  706  or  707  and this current passes through R 5 . The current flowing through resister R 5  enters the collectors of transistors  706  and  707 . The current output from transistors  706  and  707  flows through resisters R 6  and R 7 , respectively, which then generate a voltage at the base of transistors  708  and  709 . Transistor  708  passes a level shifted input Vinn into the absolute value circuit  705 . Likewise, transistor  709  passes a level shifted input Vipp into the absolute value circuit  705 . Vipp and Vinn are modulated based upon the gain value K. The gain value K=2×(R 7 /R 5 ). The gain value K is preferably set between 0.4 and 1, however the gain value may be set beyond those reference points in certain circumstances. 
         [0040]      FIG. 7   b  illustrates a comparison between the output current of the absolute value circuit Iabs_out versus the differential input voltage (Vip—Vin) at various gain values K. Note,  FIG. 7   b  is illustrated using a transistor ratio of 4 to 1 (design factor X=4). Resistors R 7  &amp; R 5  may be fixed values determined when the amplifier is manufactured, or they may be variable, allowing the shape of the output current Iabs_out to be changed based upon operating conditions. 
         [0041]      FIG. 7   c  illustrates the output current Iout versus the input current Vin (Vipp−Vinn) for various gain values K at a design ratios of X:1. As seen in  FIG. 7   c , as K increases from 0.4 to 1, the shape of the output current Iout changes. 
         [0042]      FIG. 7   d  illustrates the normalized transconductance verses the input voltages Vin (Vip−Vin) for various gain values K at a design ratio of X:1. As seen in  FIG. 7   d , as the design ratio increases from 0.4 to 1, the shape of the transconductance Gm changes. In the exemplary illustration in  FIGS. 7   c - d  the gain value K is preferably set to 0.6, however, the preferable gain value K may change depending upon the design ratio X selected. 
         [0043]    The above described absolute value circuits are merely an exemplary current modulator circuit which can linearize the transconductance of an amplifier. However, one of ordinary skill in the art would recognize that other circuits could accomplish a similar function. For example, a class AB differential input stage could be used 
         [0044]      FIG. 8  illustrates an amplifier  800  using a class AB differential input stage  807 . The amplifier  800  may include a differential amplifier  801 , class AB differential input stage  807  and current mirror  804 . The differential amplifier  801  may include a first transistor  802  receiving a first input voltage Vip and a second transistor  203 , matched to the first transistor  802  (i.e., having the same properties), receiving a second input voltage Vin. 
         [0045]    The amplifier  800  may further include a current mirror  804 , which may include matching transistors  805  and  806  and resistors R 1  and R 2 . The current mirror attempts to match the current Itail to the current Iabs_out. The current Iabs_out is controlled by the class AB differential input stage  807 . 
         [0046]    The class AB differential input stage  807  may generate an output current whose magnitude varies based on the differential input voltages, for example, modulated input voltages Vipp and Vinn, supplied to the amplifier. 
         [0047]      FIG. 9   a  illustrates an exemplary class AB differential input stage. The class AB differential input stage may include transistors  901  and  902  and may have their collectors connected and their emitters connected through a resistor R. The base of transistors  901  and  902  may be connected to a current source Ibias and to the emitters of transistors  903  and  904 , respectively. The collectors of transistors  903  and  904  may be connected to ground. The base of transistors  903  and  904  may receive the modulated input voltages Vipp and Vinn, respectively. Transistors  907  and  908  may also receive the input modulated voltages Vipp and Vinn at their respective bases. The emitters of transistors  907  and  908  may be connected to the current source Ibias and may also be connected to the base of transistors  905  and  906 , respectively. The emitters of transistors  905  and  906  may be connected to each other through the resistor R. The collectors of transistors  905  and  906  may be connected to ground. 
         [0048]      FIG. 9   b  illustrates a comparison between the current output labs from the class AB differential input stage and the input voltage Vin (i.e., Vin−Vip). As seen in  FIG. 9   b , as the input voltage deviates from zero (i.e., the operating point), the current output from the current modulator increases. As seen in  FIG. 9   b , the shape of the output current labs may be selectively changed by selecting the resistance of resistor R and the current of the current source Ibias. 
         [0049]    Transistors  901 ,  903 ,  905  and  907  may form half of the class AB differential input stage, while transistors  902 ,  904 ,  906  and  908  may form the other half. Each half of the class AB differential input stage may attempt to force the input voltage (i.e., Vip or Vin) to the emitters of transistors  901 ,  905 ,  902  and  906 , respectively. Since the emitters of transistors  901 ,  905 ,  902  and  906  are connected through resistor R, the difference in voltage Vip−Vin will be forced across the resistor R. The difference between the input voltages, divided by the resistance of resistor R will be equal to the output current labs, which is used to modulate the tail current of the amplifier. 
         [0050]    Several embodiments of the invention are specifically illustrated and/or described herein. However, it will be appreciated that modifications and variations of the invention are covered by the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the invention.