Abstract:
The invention provides a chip arrangement determining method for acquiring a group of chips as non-defective products from a substantially circular wafer. Plural pairs of grid points, having a space smaller than a diameter of a regional circle which is indicative of the size of a valid exposure area, are extracted from chip arrays arranged in a grid pattern. With respect to each of the plural pairs of grid points extracted, a regional circle having the pair of grid points on its circumference is formed on the chip arrays. Then, the number of chips entirely included within the regional circle is counted. A regional circle, having the maximum number of chips entirely included within the circle, is specified from all the regional circles formed, and this chip arrangement is determined as the optimum chip arrangement. In this manner, a strictly optimum semiconductor chip arrangement on a wafer can be obtained in a short time.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a method and apparatus for determining a chip arrangement, or a chip arrangement and shot arrangement on a wafer for exposure processing performed by an aligner which manufactures, e.g., semiconductor devices, image sensing devices (CCD or the like), liquid crystal display devices, thin-film magnetic heads and the like, and also relates to an aligner which performs exposure processing using said method and apparatus.  
         BACKGROUND OF THE INVENTION  
         [0002]    Chips are arranged in a grid pattern on a wafer since it is necessary to provide scrub lines between the chips.  
           [0003]    According to a conventional chip arrangement determining method, a chip arrangement shown in FIG. 14A, where the center of the chips matches the center of the wafer, is compared with a chip arrangement shown in FIG. 14B, where two sides of a chip match the wafer coordinate axes having its origin at the center of the wafer. Then, the arrangement that can achieve a larger number of acquirable chips in a valid exposure area is adopted.  
           [0004]    The larger the number of chips produced from one wafer, the more the manufacturing cost can be reduced. Therefore, it is important to maximize the number of acquirable chips in the valid exposure area. However, the conventional technique shown in FIGS. 14A and 14B cannot determine a chip arrangement that achieves rigorously the maximum number of chips. Furthermore, Japanese Patent Application Laid-Open No. 2000-195824 proposes a chip arrangement determining method that achieves virtually the maximum number of chips. According to the method proposed by Japanese Patent Application Laid-Open No. 2000-195824, the relative position of the valid exposure area and chip arrangement that is neatly arranged in a grid pattern is shifted in each of the X and Y directions to search for a relative position that maximizes the number of acquirable chips.  
           [0005]    However, according to this method, unless the pitch of one shift is made infinitely small, it is not always possible to obtain the relative position that maximizes the number of acquirable chips. In addition, this method raises a problem of an increased calculation time, as the pitch is made smaller. In other words, to obtain a strictly optimum chip arrangement, the required calculation time becomes extremely long.  
         SUMMARY OF THE INVENTION  
         [0006]    The present invention has been proposed to solve the above conventional problems, and has as its object to provide a method of obtaining a strictly optimum arrangement of semiconductor chips in a short time.  
           [0007]    Furthermore, in a case where a plurality of chips are projected by a single time of exposure shot, it is another object of the present invention to provide a determining method of a shot arrangement that realizes a high throughput by transferring a predetermined chip arrangement in the minimum number of shots, and a determining method of a shot arrangement that realizes a high throughput by exposing the entire surface of a valid exposure area in the minimum number of shots while covering the predetermined chip arrangement.  
           [0008]    In order to attain the above objects, the present invention provides a chip arrangement determining method for obtaining a group of chips acquirable from a substantially circular wafer, comprising: an extracting step of extracting plural pairs of grid points, having a space smaller than a diameter of a regional circle which is indicative of a size of a valid exposure area, from chip arrays where chips are arranged in a grid pattern; a forming step of forming a regional circle, having a pair of gird points on its circumference, on the chip arrays with respect to each of the plural pairs of grid points extracted in the extracting step; and a determining step of specifying a regional circle, having the maximum number of chips entirely included within the circle, from the regional circles formed in the forming step, and determining a chip arrangement on the wafer based on chip arrays of the specified regional circle.  
           [0009]    In order to attain the above objects, the present invention provides a chip arrangement determining apparatus for obtaining a group of chips acquirable from a substantially circular wafer, comprising: extracting means adopted to extract plural pairs of grid points, having a space smaller than a diameter of a regional circle which is indicative of a size of a valid exposure area, from chip arrays where chips are arranged in a grid pattern; forming means adopted to form a regional circle, having a pair of gird points on its circumference, on the chip arrays with respect to each of the plural pairs of grid points extracted by the extracting means; and determining means adopted to specify a regional circle, having the maximum number of chips entirely included within the circle, from the regional circles formed by the forming means, and determine a chip arrangement on the wafer based on chip arrays of the specified regional circle.  
           [0010]    More preferably, the above chip arrangement determining method further comprises a second determining step of determining an arrangement of a shot region in a manner such that the entire chip arrangement determined in the determining step is covered in the minimum number of shots.  
           [0011]    Furthermore, the present invention provides a chip arrangement determining apparatus which executes the above-described chip arrangement determining method. Moreover, the present invention provides: a semiconductor aligner comprising the chip arrangement determining apparatus, a semiconductor device manufactured by the semiconductor aligner, and a semiconductor device manufacturing method using the semiconductor aligner.  
           [0012]    Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.  
         [0014]    [0014]FIG. 1A is a flowchart explaining an optimization procedure of a chip arrangement and a shot arrangement;  
         [0015]    [0015]FIG. 1B is a flowchart explaining an optimization procedure of a chip arrangement and a shot arrangement;  
         [0016]    [0016]FIG. 1C is a block diagram showing a configuration of an apparatus which executes the procedure explained in FIGS. 1A and 1B;  
         [0017]    [0017]FIG. 2 is an explanatory view of a determining method of search target grid points;  
         [0018]    [0018]FIG. 3 is an explanatory view of a chip arrangement for each search target circle;  
         [0019]    [0019]FIG. 4 is an explanatory view of a shot which can obtain a plurality of chips;  
         [0020]    [0020]FIG. 5 is an explanatory view of a procedure for obtaining an optimum chip arrangement;  
         [0021]    [0021]FIG. 6 is an explanatory view of a procedure for obtaining an optimum shot arrangement;  
         [0022]    [0022]FIG. 7 is an explanatory view of a procedure for obtaining an optimum shot arrangement under a condition of wafer&#39;s entire-surface exposure;  
         [0023]    [0023]FIG. 8 is a view showing an example of an optimum chip arrangement obtained;  
         [0024]    [0024]FIG. 9 is a view showing an example of a conventional chip arrangement;  
         [0025]    [0025]FIG. 10 is a view showing an example of optimum chip arrangement and shot arrangement;  
         [0026]    [0026]FIG. 11 is a view showing an example of conventional chip arrangement and shot arrangement;  
         [0027]    [0027]FIG. 12 is a view showing an example of optimum chip arrangement and shot arrangement under a condition of wafer&#39;s entire-surface exposure;  
         [0028]    [0028]FIG. 13 is a view showing an example of conventional chip arrangement and shot arrangement under a condition of wafer&#39;s entire-surface exposure;  
         [0029]    [0029]FIGS. 14A and 14B are views showing an example of a conventional chip arrangement determining method;  
         [0030]    [0030]FIG. 15 is a flowchart of a semiconductor device production; and  
         [0031]    [0031]FIG. 16 is a flowchart of a detailed wafer process. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0032]    Preferred embodiments of the present invention will now be described in detail in accordance with the accompanying drawings.  
         [0033]    &lt;Chip Arrangement/Shot Arrangement Determining Process&gt; 
         [0034]    [0034]FIG. 1C is a block diagram showing a configuration of an exposure system according to the present embodiment. Reference numeral  111  denotes a data processing apparatus, comprising a CPU  112  similar to that of a general-purpose computer, ROM  113 , RAM  114 , and an external storage device  116 . Reference numeral  115  denotes an interface for communication between the data processing apparatus  111  and an aligner  121 .  
         [0035]    The data processing apparatus  111  determines the optimum chip arrangement and shot arrangement for a wafer based on job data for the aligner  121 , which is stored in the external storage device  116 , and informs the aligner  121  of the job data including the chip arrangement and shot arrangement. The aligner  121 , which receives the job data, performs exposure processing on the wafer using the designated chip arrangement and shot arrangement.  
         [0036]    Note although this embodiment describes the data processing apparatus  111  and aligner  121  as independent apparatuses, the aligner  121  may include a part or all of the functions of the data processing apparatus  111  described in this embodiment.  
         [0037]    [0037]FIGS. 1A and 1B are flowcharts explaining chip arrangement/shot arrangement determining procedure according to this embodiment. The procedures shown in FIGS. 1A and 1B are realized by the CPU  112  which executes a control program stored in the ROM  113  or a control program loaded from the external storage device  116  to the RAM  114 .  
         [0038]    First, in step S 101 , data such as a valid exposure radius R of a wafer subjected to exposure, a depth h of an orientation flat, an X-direction length a of a chip, a Y-direction length b of a chip, the number of X-direction shot divisions n, the number of Y-direction shot divisions m, and the like are inputted. In this embodiment, a chip arrangement that maximizes the number of acquirable chips is obtained based on the above data (S 102  to S 108 ). Next, in accordance with performing or not performing a full exposure of a wafer&#39;s valid exposure area, a shot arrangement that can minimize the necessary number of shots is obtained (S 111  to S 119 ). Note that values set in step S 101  may be acquired from the external storage device  116 , or inputted by a user through an operation panel (not shown).  
         [0039]    First, a description is provided on a method of obtaining a chip arrangement that maximizes the number of acquirable chips.  
         [0040]    In step S 102 , a chip grid coordinate system is set. Herein, rectangular chips  1 , each having a length a in the X direction and a length b in the Y direction, which are arranged neatly in a grid pattern as shown in FIG. 2, are defined as the chip grid coordinate system. The chip grid coordinate system is configured with straight lines arranged in parallel with the Y axis at equal intervals a, and straight lines arranged in parallel with the X axis at equal intervals b.  
         [0041]    Next in step S 103 , search target grid points are extracted. In this embodiment, search target grid points  3  are defined by selecting grid points in the first quadrant which fall within the region from the origin  2  to 2R of the chip grid coordinate system. Note that R, which is set in step S 101 , corresponds to the radius of a circle that covers the entire or a part of the boundary line of the valid exposure area.  
         [0042]    Next in step S 104 , one grid point is selected from the aforementioned search target grid points  3 . As shown in FIG. 3, the selected search target grid point  3  and the origin  2  are positioned on the circumference of the circle having the radius R. Accordingly, in step S 105 , it is possible to obtain the center position of the circle (hereinafter referred to as a search target circle), having the radius R, which includes the grid coordinate&#39;s origin and the search target grid point on its circumference. Note, as shown in FIG. 3, there are two search target circles for each search target grid point  3 . The present embodiment defines, as a search target circle  4 , a circle having a smaller X coordinate or a larger Y coordinate with respect to the center position coordinates of the circle; thus, each search target grid point  3  corresponds to a search target circle  4  on a one-to-one basis.  
         [0043]    When an orientation flat exists for the search target circle  4 , based on the depth h of the orientation flat, a notch-like boundary line  5  corresponding to an orientation flat is provided at, for instance, a position parallel with the X axis and having a larger Y coordinate than the center position of the search target circle. In this manner, the area which has a smaller Y coordinate than the boundary line  5  and which falls within the search target circle  4  is defined as the valid exposure area. In step S 106 , the number of chips  6  that are entirely included within the valid exposure area is counted to obtain the number of acquirable chips. Note in a case where the orientation flat does not exist (e.g., h=0), the entire search target circle is defined as a valid area.  
         [0044]    The foregoing steps S 104  to S 106  are executed with respect to all the search target grid points, and the search target circle  4  that maximizes the number of acquirable chips is obtained (step S 107 ). Then, the positions of the acquirable chips are transformed into the X′Y′ wafer coordinate system  7 , whose origin is at the center of the search target circle, thereby obtaining the strictly optimum chip arrangement. At this stage, the group of acquirable chips is defined as a non-defective chip group  8 .  
         [0045]    Next, a description is provided on a method of obtaining a shot arrangement for exposing the non-defective chip group  8  in the minimum number of shots, in a case where a plurality of chips are projected by a single time of exposure shot.  
         [0046]    [0046]FIG. 4 shows a view of one shot. In the shot shown in FIG. 4, the area is divided into n number of divisions in the X direction, and m number of divisions in the Y direction. One shot  13  includes n x m (6×11 in FIG. 4) rectangular chips  1 .  
         [0047]    In a case where one shot is divided by a plurality of chips, there are as many types of shot arrangements as the number of divisions. Therefore, it is necessary to determine n×m types of shot arrangements. More specifically, as shown in FIG. 5, from the state where an intersection point  10  of the shot boundary overlaps an arbitrary chip grid point  9  of the non-defective chip group  8  defined in the wafer coordinate system, the chip arrangement is shifted in the X-axis direction at a pitch corresponding to the X-direction length of the chip up to the number of X-direction shot divisions n, and further shifted in the Y-axis direction at a pitch corresponding to the Y-direction length of the chip up to the number of Y-direction shot divisions m.  
         [0048]    In step S 111 , whether or not the entire wafer surface is to be exposed is determined. If YES, the control proceeds to step S 112 . If NO, the control proceeds to step S 116 .  
         [0049]    If the entire wafer surface is not to be exposed, n×m types of shot arrangements are set as described above (step S 116 ). With respect to each shot arrangement, the number of shots included in the shot group  11  that covers the chip group  8  as shown in FIG. 6 is calculated (steps S 117  and S 118 ). From the n x m types of shot arrangements, a shot arrangement that requires the minimum number of shots is selected. As a result, the optimum shot arrangement is obtained (step S 119 ).  
         [0050]    Next, a description is provided on a method of obtaining a shot arrangement for exposing the entire surface of the wafer&#39;s valid exposure area in the minimum number of shots while covering a predetermined chip arrangement. This process, corresponding to exposing the entire wafer surface, is realized by executing step S 112  and the following steps in the flowchart in FIG. 1B.  
         [0051]    In this case also, there are as many types of shot arrangements as the number of divisions. Therefore, in step S 112 , n×m types of shot arrangements are set in the similar procedure to step S 116 . More specifically, as shown in FIG. 7, from the state where an intersection point of the shot boundary overlaps an arbitrary grid point of the non-defective chip group  8  defined in the wafer coordinate system, the chip arrangement is shifted in the X-axis direction at a pitch corresponding to the X-direction length of the chip up to the number of X-direction shot divisions n, and further shifted in the Y-axis direction at a pitch corresponding to the Y-direction length of the chip up to the number of Y-direction shot divisions m.  
         [0052]    With respect to each shot arrangement, the number of shots included in a shot group  12 , which consists of shot arrangements that are at least partially included in the valid exposure area, is calculated (steps S 113  and S 114 ). From the n×m types of shot arrangements, a shot arrangement that requires the minimum number of shots is selected. As a result, the optimum shot arrangement is obtained (step S 115 ).  
         [0053]    The chip arrangement and shot arrangement determining procedure is performed in the foregoing manner according to the present embodiment. In determining a chip arrangement that maximizes the number of chips acquirable from a given wafer, the key factor of the present embodiment is in that, by limiting the determination to a case where two end points in the group of acquirable chips are included in the boundary line of the valid exposure area, a problem of consecutive relative-position search of the chip arrangement and wafer by nature is turned into a discrete problem, and as a result, searching the finite number of combinations can lead to a strictly optimum chip arrangement.  
         [0054]    Hereinafter, an embodiment of determining a chip arrangement and a shot arrangement by the above-described technique is described in comparison with the arrangement determined by the conventional technique.  
         [0055]    &lt;Embodiments of Chip Arrangement/Shot Arrangement Determining Process&gt; 
         [0056]    The first embodiment describes a simple example where there is only one chip in one shot. A condition provided is as follows: a wafer diameter is 200 mm; an invalid width from an outer edge is 3 mm (i.e., diameter 2R of the valid area=194 mm); a depth of orientation flat is 5 mm; and each of the vertical and horizontal lengths of a chip is 22 mm. Under this condition, an arrangement that maximizes the number of acquirable chips is obtained by the method according to the above-described embodiment. The result is shown in FIG. 8. According to this shot arrangement, coordinates of the center position of the top right shot are (14.65 mm, 77.20 mm) in the wafer coordinate system having its origin at the center of the wafer. The number of acquirable chips is 48.  
         [0057]    On the contrary, FIG. 9 shows an arrangement obtained by the conventional method. According to this shot arrangement, coordinates of the center position of the top right shot are (44.00 mm, 66.00 mm) in the wafer coordinate system having its origin at the center of the wafer. The number of acquirable chips is 45. Therefore, the first embodiment increases the number of acquirable chips by 3, and achieves the cost reduction rate 6.3%.  
         [0058]    The second embodiment describes an example where four chips (each of the vertical and horizontal lengths of each chip is 11 mm) are exposed in one shot. A condition provided is as follows: a wafer diameter is 200 mm; an invalid width from an outer edge is 3 mm; a depth of orientation flat is 5 mm; and each of the vertical and horizontal lengths of a shot is 22 mm. Under this condition, an arrangement that maximizes the number of acquirable chips and that requires the minimum number of exposure shots is obtained by the method according to the above-described embodiment. The result is shown in FIG. 10. According to this shot arrangement, coordinates of the center position of the top right shot are (41.31 mm, 77.29 mm) in the wafer coordinate system having its origin at the center of the wafer. The number of acquirable chips is 213, and the number of exposure shots is 60.  
         [0059]    On the contrary, FIG. 11 shows an arrangement obtained by the conventional method under the above-described condition. According to this shot arrangement, coordinates of the center position of the top right shot are (49.50 mm, 82.50 mm) in the wafer coordinate system having its origin at the center of the wafer. The number of acquirable chips is 210, and the number of exposure shots is 60. Therefore, the second embodiment increases the number of acquirable chips by 3, and achieves the cost reduction rate 1.4%.  
         [0060]    The third embodiment describes an example where six chips (each of the vertical and horizontal lengths of each chip is 11 mm) are exposed in one shot. A condition provided is as follows: a wafer diameter is 300 mm; an invalid width from an outer edge is 3 mm; no orientation flat; the vertical length of a shot is 33 mm; and the horizontal length of a shot is 22 mm. Under this condition, an arrangement that maximizes the number of acquirable chips and that requires the minimum number of exposure shots is obtained by the method according to the above-described embodiment. The result is shown in FIG. 12. According to this shot arrangement, coordinates of the center position of the top right shot are (12.00 mm, 163.00 mm) in the wafer coordinate system having its origin at the center of the wafer. The number of acquirable chips is 515, and the number of exposure shots is 115.  
         [0061]    On the contrary, FIG. 13 shows a chip arrangement and a shot arrangement obtained by the conventional method under the above-described condition. According to this shot arrangement, coordinates of the center position of the top right shot are (99.00 mm, 192.00 mm) in the wafer coordinate system having its origin at the center of the wafer. The number of acquirable chips is 510, and the number of exposure shots is 114. Therefore, the third embodiment increases the number of acquirable chips by 5, and achieves the cost reduction rate 0.97%.  
         [0062]    &lt;Semiconductor Device Manufacturing Apparatus and Method&gt; 
         [0063]    Described next is an embodiment of a device manufacturing method employing the aforementioned aligner system. FIG. 15 shows a production flow of micro devices (semiconductor chips such as an IC or an LSI, liquid crystal panels, CCD, thin-film magnetic heads, micro machines and so forth).  
         [0064]    In step S 11  (circuit design), a circuit of a semiconductor device is designed. In step S 12  (mask production), a mask on which the designed circuit pattern is formed is produced. Meanwhile, in step S 13  (wafer production), a wafer is produced with a material such as silicon. In step S 14  (wafer process), which is called a pre-process, an actual circuit is formed on the wafer using the mask and wafer by a lithography technique. In step S 15  (assembly), which is called a post-process, a semiconductor chip is manufactured using the wafer produced in step S 14 . Step S 15  includes assembling process (dicing, bonding), packaging process (chip embedding) and so on. In step S 16  (inspection), the semiconductor device manufactured in step S 15  is subjected to inspection such as an operation-check test, durability test and so on. Semiconductor devices are manufactured in the foregoing processes and shipped (step S 17 ).  
         [0065]    [0065]FIG. 16 shows a flow of the aforementioned wafer process in detail. In step S 21  (oxidization), the wafer surface is oxidized. In step S 22  (CVD), an insulating film is deposited on the wafer surface. In step S 23  (electrode formation), electrodes are deposited on the wafer. In step S 24  (ion implantation), ion is implanted on the wafer. In step S 25  (resist process), a photosensitive agent is coated on the wafer. In step S 26  (exposure), the circuit pattern of the mask is exposed on the wafer by the above-described aligner. In step S 27  (development), the exposed wafer is developed. In step S 28  (etching), portions other than the developed resist image are removed. In step S 29  (resist separation), unnecessary resist after the etching process is removed. By repeating the foregoing steps, multiple circuit patterns are formed on the wafer.  
         [0066]    The manufacturing method of this embodiment enables production of highly integrated semiconductor devices, which have been difficult to produce conventionally.  
         [0067]    As has been described above, the foregoing embodiments enable determination of a strictly optimum chip arrangement and a strictly optimum shot arrangement, which ultimately contribute to cost reduction in semiconductor chip manufacturing.  
         [0068]    &lt;Other Embodiment&gt; 
         [0069]    The objects of the present invention can also be achieved by providing a storage medium, storing program codes of software realizing the above-described functions of the embodiments (chip arrangement/shot arrangement determining process), to a computer system or apparatus, reading the program codes stored in the storage medium, by a CPU or MPU of the computer system or apparatus, and executing the program.  
         [0070]    In this case, the program codes read from the storage medium realize the functions according to the embodiments, and the storage medium storing the program codes constitutes the invention.  
         [0071]    For the storage medium providing the program codes, a floppy disk, hard disk, an optical disk, a magneto-optical disk, CD-ROM, CD-R, a magnetic tape, a non-volatile type memory card, and ROM can be used.  
         [0072]    Furthermore, besides aforesaid functions according to the above embodiments are realized by executing the program codes which are read by a computer, the present invention includes a case where an OS (operating system) or the like working on the computer performs a part or the entire processes in accordance with designations of the program codes and realizes functions according to the above embodiments.  
         [0073]    Furthermore, the present invention also includes a case where, after the program codes read from the storage medium are written in a function expansion card which is inserted into the computer or in a memory provided in a function expansion unit which is connected to the computer, a CPU or the like contained in the function expansion card or unit performs a part or the entire process in accordance with designations of the program codes and realizes functions of the above embodiments.  
         [0074]    As has been described above, according to the present invention, it is possible to obtain a strictly optimum arrangement of semiconductor chips on a wafer in a short time.  
         [0075]    Furthermore, in a case where a plurality of chips are projected by a single time of exposure shot, it is possible to transfer a predetermined chip arrangement in the minimum number of shots, thereby realizing a high throughput. Similarly, it is possible to expose the entire surface of the valid exposure area in the minimum number of shots, while covering the predetermined chip arrangement, thereby realizing a high throughput.  
         [0076]    As many apparently widely different embodiments of the present invention can be made without departing from the spirit and scope thereof, it is to be understood that the invention is not limited to the specific embodiments thereof except as defined in the claims.