Abstract:
In a power supply voltage detection circuit using a reference potential generation circuit, as represented by a band gap reference circuit according to a prior art, the correction of dispersion in the detection level cannot be carried out after the completion of diffusion and assembly. Therefore, a power supply voltage detection circuit  4  is provided with a reference potential generation circuit  1,  a divided voltage potential generation circuit  2  and a differential amplification circuit  3  for comparing the divided voltage potential to the reference potential. Furthermore, a ferroelectric memory  5  which stores correction data for correcting the reference potential, a data latch circuit  7  for storing correction data that has been read out, and a microcomputer logic unit  6  for controlling ferroelectric memory  5  as well as data latch circuit  7  are provided. The reference potential is altered according to correction data so that dispersion in the power supply voltage detection level is reduced.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    This invention relates to a voltage detection level correction circuit using a non-volatile memory and to a semiconductor device on which this circuit is mounted.  
           [0003]    2. Description of Prior Art  
           [0004]    A ferroelectric memory (FeRAM) makes possible reading and writing at a low voltage, as well as high speed operation, in comparison with other non-volatile memories (for example, flash memory or EEPROM). In contrast to this, there is a possibility wherein data rewrite may be carried out even under the condition of a voltage lower than that of a product specification and, therefore, a measure, exceeding the product specification, for preventing malfunction is introduced in the circuit from the point of view of data protection such that a power supply voltage detection circuit is mounted and a command from the outside is not accepted in the case of a voltage lower than, or including, the set voltage.  
           [0005]    [0005]FIG. 10 shows a block diagram of a semiconductor device on which a ferroelectric memory, which has been conventionally utilized, is mounted. A reference potential generation circuit is denoted as  101 , a reference potential output node of the reference potential generation circuit  101  is denoted as NBGRA, a divided voltage potential generation circuit for generating a divided voltage potential is denoted as  102 , an output node of the divided voltage potential generation circuit  102  is denoted as NHALA, a differential amplification circuit for generating an output PORA at a CMOS level by amplifying a potential difference between output node NBGRA of reference potential generation circuit  101  and output node NHALA of divided voltage potential generation circuit  101  is denoted as  103 , the output node of the differential amplification circuit  103  is denoted as PORA and a power supply voltage detection circuit formed of the reference potential generation circuit  101 , the divided voltage potential generation circuit  102  and the differential amplification circuit  103  is denoted as  104 . A ferroelectric memory for storing arbitrary information is denoted as  105 . A microcomputer logic unit for controlling the ferroelectric memory  105  is denoted as  106 .  
           [0006]    In the present circuit, in the case that the power supply voltage is lower than the set level, that is to say, in the case that the potential level of node NBGR is higher than the potential level of node NHALA, the logic level of node PORA is set at “H” so that the ferroelectric memory  105  and the microcomputer logic unit  106  are converted to the deactivated condition. In addition, in contrast to this, in the case that the power supply voltage is higher than the set level, that is to say, the potential level of node NBGR is lower than the potential level of node NHALA, the logic level of node PORA is set at “L” so that the ferroelectric memory  105  and the microcomputer logic unit  106  are converted to the activated condition.  
           [0007]    [0007]FIG. 11 is a block diagram of a band gap reference circuit showing one example of a reference potential generation circuit.  
           [0008]    P channel type CMOS transistors are denoted as QP 101 , QP 102 , QP 103 , QP 104  and QP 105 , N channel type CMOS transistors are denoted as QN 101 , QN 102 , QN 103  and QN 104 , resistor elements are denoted as R 101 , R 102  and R 103 , a differential amplification circuit for amplifying the potential difference between internal nodes N 101  and N 103  formed of transistors QP 103 , QP 104 , QP 105 , QN 102 , and QN 103  is denoted as  107 , diodes are denoted as Di 101  and Di 102  and the ground voltage is denoted as VSS.  
           [0009]    The source of P channel type CMOS transistor QP 101  is connected to power supply voltage VDD, and the gate and the drain are connected to node N 104 . The source of P channel type MOS transistor QP 102  is connected to power supply voltage VDD, the gate is connected to node N 104 , and the drain is connected to node NBGRA. The source of P channel type MOS transistor QP 103  is connected to power supply voltage VDD, the gate is connected to node N 104 , and the drain is connected to N 105 . The source of P channel type MOS transistor QP 104  is connected to node N 105 , the gate is connected to node N 101  and the drain is connected to N 106 . The source of P channel type MOS transistor QP 105  is connected to node N 105 , the gate is connected to node N 103  and the drain is connected to N 107 .  
           [0010]    The gate of N channel type CMOS transistor QN 101  is connected to node NBIAS, the source is connected to ground voltage VSS and the drain is connected to node N 104 . The gate and the drain of N channel type CMOS transistor QN 102  are connected to node N 106  and the source is connected to ground voltage VSS. The gate of N channel type CMOS transistor QN 103  is connected to node N 106 , the source is connected to ground voltage VSS and the drain is connected to node N 107 . The gate of N channel type CMOS transistor QN 104  is connected to node N 107 , the source is connected to ground voltage VSS and the drain is connected to node NBGRA.  
           [0011]    As for the potential supplied to node NBIAS, a potential slightly higher than the threshold value (Vt) of QN 101  is inputted to node NBIAS so that this input allows a constant current to flow through QN 101 .  
           [0012]    The differential amplification circuit  107  is formed of transistors QP 103 , QP 104 , QP 105 , QN 102  and QN 103  and has nodes N 101  and N 103  as input terminals, and node N 107  as an output terminal. In the case that the level of node N 103  is higher than that of node N 101 , logic potential “L” is generated at node N 107  and, on the other hand, in the case that the level of node N 103  is lower than that of node N 101 , logic potential “H” is generated.  
           [0013]    One end of resistor element R 101  is connected to node NBGRA and the other end is connected to node N 101 . One end of resistor element R 102  is connected to node N 101  and the other end is connected to node N 102 . One end of resistor element R 103  is connected to node NBGRA and the other end is connected to node N 103 .  
           [0014]    The P type diffusion region of diode Di 101  is connected to node N 103  and the N type diffusion region is connected to ground voltage VSS. The P type diffusion region of diode Di 102  is connected to node N 102  and the N type diffusion region is connected to ground voltage VSS.  
           [0015]    The output voltage VREF at node NBGRA of the band gap reference circuit, shown in FIG. 11, is shown in the following equation (equation 1-1) when the threshold voltage of diode Di 101  is denoted as Vd, the resistance values of resistor elements R 101 , R 102  and R 103 , respectively, are rs 11 , rs 12  and rs 13  and the saturation currents of diodes Di 101  and Di 102 , respectively, are Is 11  and Is 12 .  
             VREF=Vd+ ( rs   11 / rs   12 )* ( k/q ) *  In{ ( Is   12 / Is   11 )*( rs   11 / rs   13 )}*  T   (equation 1-1)  
           [0016]    wherein the Boltzmann coefficient is denoted as k, the amount of charge of electrons is denoted as q and the absolute temperature is denoted as T.  
           [0017]    Vd shown above is dependent on the temperature and has a negative inclination wherein the higher the temperature is, the lower Vd is, while, the lower the temperature is, the higher Vd is.  
           [0018]    When the constant voltage portion of the first term, Vd, of the right-side member of (equation 1-1) is denoted as A 1 , the fluctuation portion thereof due to temperature is denoted as αT, the constant voltage portion of the second term of the right-side member of (equation 1-1) is denoted as B 1 , and the fluctuation portion thereof due to temperature is denoted as βT, VREF is indicated in the following equation (equation 1-2).  
             VREF=A   1 + B   1 −α T+βT   (equation 1-2)  
           [0019]    The configuration makes it possible to gain a constant reference voltage wherein the dispersion due to the process and to temperature is greatly reduced by setting the values of coefficient α and β, which are dependent on the temperature, to be equal to each other in (equation 1-2). Though in the present description the circuit configuration of FIG. 11 is used and is explained, other circuit configurations using diodes and register elements can be implemented.  
           [0020]    [0020]FIG. 12 is a circuit diagram showing an example of divided voltage potential generation circuit  102 .  
           [0021]    One end of a register element RA 101  is connected to power supply voltage VDD and the other end is connected to output node NHALA while one end of register element RA 102  is connected to ground voltage VSS and the other end is connected to output node NHALA. The power supply voltage is divided according to a ratio of resistance values of RA 101  and RA 102  so as to be outputted from node NHALA.  
           [0022]    As shown in FIGS.  10  to  12 , a band gap reference circuit is, in some cases, used as reference potential generation circuit  101  in order to limit the dispersion of the detection level due to fluctuation in process parameters, or the like, to a small value in power supply voltage detection circuit  104 . However, a slight dispersion occurs in the reference potential due to parasitic resistances and parasitic capacitances caused by the layout and due to fluctuation in process parameters inside of a wafer and among wafers. The dispersion in the power supply voltage detection voltage increases in proportion to the power supply voltage detection voltage and the reference potential. In the case that, for example, the ratio of the power supply voltage detection voltage to the reference voltage is 2 and the dispersion in the reference voltage is 50 mV, the dispersion in the power supply voltage detection voltage becomes 100 mV.  
           [0023]    In addition, in the case that a differential amplification circuit, shown as  107  in FIG. 11, is used and in the case that, for example, a difference of 30 mV occurs between the threshold values of QP 104  and QP 105 , a nominal difference of 30 mV occurs between nodes N 101  and N 103  so that a similar dispersion occurs in output node NBGRA, which becomes the reference potential. In the case that a difference occurs between the threshold values of QN 102  and QN 103 , dispersion occurs in output node NBGRA.  
           [0024]    In particular, in the case that the values of the communication distance and the power supply voltage become of a tradeoff relationship so that the necessity of tolerance in the low voltage operation increases, such as in a non-contact IC card, reduction of this dispersion becomes important.  
           [0025]    Even though fluctuation in the detection voltage level due to temperature variation and due to dispersion in the process can be reduced according to the conventional circuit configuration, it is difficult to correct, in each product, the fluctuation in the detection voltage among respective products caused by process dispersion in the same diffusion lot and in the same wafer, in particular, in the threshold value dispersion among the transistors and it is difficult to adjust the detection voltage level after completion of diffusion and after completion of assembly.  
         SUMMARY OF THE INVENTION  
         [0026]    An object of the present invention is to provide a voltage detection level correction circuit and a semiconductor device wherein the power supply detection level can be varied after completion of diffusion as well as after completion of assembly so that it becomes possible to limit the dispersion in the power supply voltage detection level for products to a low level.  
           [0027]    A voltage detection level correction circuit of the present invention comprises:  
           [0028]    a power supply voltage detection circuit having a reference potential generation circuit for generating a constant reference potential that is independent of the power supply voltage, a divided voltage potential generation circuit for generating a divided potential gained by dividing the above described power supply voltage according to a constant ratio and a differential amplification circuit for comparing the above described reference potential with the above described divided voltage potential and for outputting an output signal in the case that the above described divided potential is lower than the above described reference potential;  
           [0029]    a non-volatile memory which stores correction data for correcting the above described reference potential and which is converted to the inactive condition in response to the above described output signal of the above described differential amplification circuit;  
           [0030]    a data latch circuit for storing the above described correction data read out from the above described non-volatile memory; and  
           [0031]    a control circuit for reading out the above described correction data, which is latched to the above described data latch circuit, from the above described non-volatile memory, and  
           [0032]    the voltage detection level correction circuit is characterized in that the above described reference potential generation circuit comprises a circuit which has circuit elements for varying the above described reference potential and which allows the above described correction data to be inputted from the above described data latch circuit for switching of the above described circuit elements.  
           [0033]    According to the configuration of this invention, the reference potential can be arbitrarily varied after completion of diffusion and assembly and, therefore, the detection level of the power supply voltage detection circuit can be arbitrarily varied with respect to a product after diffusion and assembly, and it becomes possible to limit the dispersion of the power supply voltage detection level for products to a low level.  
           [0034]    In the above described invention, the resistance value of a resistance element existing within the reference potential generation circuit may be altered according to correction data and, thereby, the reference potential is altered.  
           [0035]    In addition, in the above described invention, the saturation current value of a diode element existing within the reference potential generation circuit may be altered according to correction data and, thereby, the reference potential is altered.  
           [0036]    In the above described invention, the reference potential generation circuit may have a differential amplification circuit formed of transistors and the size of a transistor, of which the gate is connected to an input terminal of the differential amplification circuit, may be altered according to correction data and, thereby, the reference potential is altered.  
           [0037]    In the above described invention, the reference potential generation circuit may have a differential amplification circuit that includes a current mirror circuit formed of transistors and the mirror ratio of the current mirror circuit may be altered according to correction data and, thereby, the reference potential is altered.  
           [0038]    In the above described invention, at least two, or more, parameters from among the resistance value of the resistance element existing within the reference potential generation circuit, the saturation current value of a diode element existing within the reference potential generation circuit, the size of a transistor of which the gate is connected to an input terminal of a differential amplification circuit formed of transistors existing within the reference potential generation circuit and the mirror ratio of a current mirror circuit in a differential amplification circuit formed of transistors existing within the reference potential generation circuit, may be altered according to correction data and, thereby, the reference potential may be altered.  
           [0039]    The above described invention may be characterized in that the above described control circuit operates in response to an output signal of the above described differential amplifier.  
           [0040]    According to another aspect of the invention, a voltage detection level correction circuit comprises:  
           [0041]    a power supply voltage detection circuit having a reference potential generation circuit for generating a constant reference potential that is independent of the power supply voltage, a divided voltage potential generation circuit for generating a divided potential gained by dividing said power supply voltage according to a constant ratio and a differential amplification circuit for comparing the above described reference potential with the above described divided voltage potential and for outputting an output signal in the case that the above described divided potential is lower than the above described reference potential;  
           [0042]    a non-volatile memory which stores correction data for correcting a divided voltage potential in the above described divided voltage potential generation circuit and which is converted to the inactive condition in response to the above described output signal of the above described differential amplification circuit;  
           [0043]    a data latch circuit for storing correction data read out from the above described non-volatile memory; and  
           [0044]    a control circuit for reading out the above described correction data, which is latched to the above described data latch circuit, from the above described non-volatile memory, and  
           [0045]    the voltage detection level correction circuit is characterized in that the above described divided voltage potential generation circuit comprises a circuit which has circuit elements for varying the above described divided voltage potential and which allows the above described correction data to be inputted from the above described data latch circuit for switching of the above described circuit elements.  
           [0046]    According to the above described configuration, the divided voltage potential can be arbitrarily varied after diffusion and assembly and, therefore, the power supply detection level can be varied after completion of diffusion and assembly, and it becomes possible to limit the dispersion in the power supply voltage detection level for products to a low level.  
           [0047]    The above described invention may be characterized in that the above described control circuit operates in response to an output signal of the above described differential amplifier.  
           [0048]    According to yet another aspect of the invention a voltage detection level correction circuit comprises:  
           [0049]    a power supply voltage detection circuit having a reference potential generation circuit for generating a constant reference potential that is independent of the power supply voltage, a divided voltage potential generation circuit for generating a divided potential gained by dividing the above described power supply voltage according to a constant ratio and a differential amplification circuit for comparing the above described reference potential with the above described divided voltage potential and for outputting an output signal in the case that the above described divided potential is lower than the above described reference potential;  
           [0050]    a non-volatile memory which stores correction data for adjusting the sensitivity of the above described differential amplification circuit and which is converted to the inactive condition in response to the above described output signal of the above described differential amplification circuit;  
           [0051]    a data latch circuit for storing correction data read out from the above described non-volatile memory; and  
           [0052]    a control circuit for reading out the above described correction data, which is latched to the above described data latch circuit, from the above described non-volatile memory, and  
           [0053]    the voltage detection level correction circuit is characterized in that the above described differential amplification circuit comprises a circuit which has circuit elements for adjusting the sensitivity of the above described differential amplification circuit so that the voltage detection level can be corrected and which allows the above described correction data to be inputted from the above described data latch circuit for switching of the above described circuit elements.  
           [0054]    According to the above described configuration, the sensitivity of the differential amplification circuit can be arbitrarily adjusted after diffusion and assembly and, therefore, the power supply detection level can be varied after completion of diffusion and assembly, and it becomes possible to limit the dispersion in the power supply voltage detection level for products to a low level.  
           [0055]    The above described invention may be characterized in that the above described control circuit operates in response to an output signal of the above described differential amplifier.  
           [0056]    According to a further aspect of the invention a voltage detection level correction circuit of the present invention comprises:  
           [0057]    a power supply voltage detection circuit having a reference potential generation circuit for generating a constant reference potential that is independent of the power supply voltage, a divided voltage potential generation circuit for generating a divided potential gained by dividing the above described power supply voltage according to a constant ratio and a differential amplification circuit for comparing the above described reference potential with the above described divided voltage potential and for outputting an output signal in the case that the above described divided potential is lower than the above described reference potential;  
           [0058]    a non-volatile memory which stores correction data for correcting the above described reference potential, correction data for correcting a divided voltage potential in the above described divided voltage potential generation circuit or correction data for adjusting the sensitivity of the above described differential amplification circuit and which is converted to the inactive condition in response to the above described output signal of the above described differential amplification circuit;  
           [0059]    a data latch circuit for storing correction data read out from the above described non-volatile memory; and  
           [0060]    a control circuit for reading out the above described correction data, which is latched to said data latch circuit, from the above described non-volatile memory, and  
           [0061]    the voltage detection level correction circuit is characterized in that at least two, or more, circuits from among the above described reference potential generation circuit, the above described divided voltage potential generation circuit and the above described differential amplifier comprise circuits which have circuit elements for varying the above described reference potential, the above described divided voltage potential or the sensitivity of the above described differential amplification circuit and which allows the above described correction data to be inputted from the above described data latch circuit for switching of the above described circuit elements.  
           [0062]    According to the above described configuration, a semiconductor device can be provided on which a voltage detection level correction circuit that can arbitrarily vary the voltage detection level is mounted so that it becomes possible to limit dispersion in the power supply voltage detection level for products to a low level.  
           [0063]    The above described configuration may be characterized in that the above described control circuit operates in response to an output signal of the above described differential amplifier.  
           [0064]    A voltage detection level correction circuit having the above described configuration may be mounted on a semiconductor device.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0065]    [0065]FIG. 1 is a block diagram of a semiconductor device having a detection voltage level correction circuit according to the first embodiment of the present invention;  
         [0066]    [0066]FIG. 2 is a diagram of a reference potential generation circuit in the detection voltage level correction circuit according to the first embodiment;  
         [0067]    [0067]FIG. 3 is a diagram of a reference potential generation circuit in a detection voltage level correction circuit according to the second embodiment;  
         [0068]    [0068]FIG. 4 is a diagram of a reference potential generation circuit in a detection voltage level correction circuit according to the third embodiment;  
         [0069]    [0069]FIG. 5 is a diagram of a reference potential generation circuit in a detection voltage level correction circuit according to the fourth embodiment;  
         [0070]    [0070]FIG. 6 is a block diagram of a semiconductor device having a detection voltage level correction circuit according to the fifth embodiment of the present invention;  
         [0071]    [0071]FIG. 7 is a diagram of a divided voltage potential generation circuit in a detection voltage level correction circuit according to the fifth embodiment;  
         [0072]    [0072]FIG. 8 is a block diagram of a semiconductor device having a detection voltage level correction circuit according to the sixth embodiment of the present invention;  
         [0073]    [0073]FIG. 9 is a block diagram of a semiconductor device having a detection voltage level correction circuit according to the seventh embodiment of the present invention;  
         [0074]    [0074]FIG. 10 is a block diagram of a semiconductor device having a power supply voltage detection circuit according to a prior art;  
         [0075]    [0075]FIG. 11 is a diagram of a reference potential generation circuit according to a prior art; and  
         [0076]    [0076]FIG. 12 is a diagram of a divided voltage potential generation circuit according to a prior art. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0077]    [0077]FIG. 1 shows a block diagram of a semiconductor device on which a voltage detection level correction circuit according to the first embodiment of the present invention is mounted.  
         [0078]    A reference potential generation circuit represented by a band gap reference circuit that generates a constant reference, which is independent of the power supply voltage, is denoted as  1  and an output node that generates reference voltage level VBGR 1  is denoted as NBGR 1 . A divided voltage potential generation circuit for generating a divided voltage level, which is dependent on the power supply voltage, is denoted as  2  and an output node that generates divided voltage level VHAL 1  is denoted as NHAL 1 . A differential amplification circuit for generating a comparison output POR by comparing output signal potential level VBGR 1  and the potential level of VHAL 1  is denoted as  3 . In the case that the power supply voltage is no greater than the set voltage, that is to say, in the case that reference voltage level VBGR 1  is higher than divided voltage level VHAL 1 , output signal POR outputs logic level “H” and converts a microcomputer logic unit  6  and a ferroelectric memory  5  to the inactive condition. In addition, in the case that the power supply voltage is no less than the set voltage, that is to say, in the case that reference potential VBGR 1  is lower than VHAL 1 , output signal POR outputs logic level “L” and converts microcomputer logic unit  6  and a ferroelectric memory  5  to the active condition. A power supply voltage detection circuit formed of reference potential generation circuit  1 , divided voltage potential generation circuit  2  and differential amplification circuit  3  is denoted as  4 . A non-volatile ferroelectric memory for storing arbitrary information is denoted as  5 . A microcomputer logic unit for controlling ferroelectric memory  5  and a data latch circuit  7  is denoted as  6 . A data latch circuit for storing data read out from ferroelectric memory  5  and for storing output signal NADJ[n] utilized for correction of reference voltage level VBGR 1  is denoted as  7 .  
         [0079]    In addition, in the following description it is assumed that the circuit (FIG. 12) described above as a conventional circuit is used for divided voltage potential generation circuit  2  in FIG. 1.  
         [0080]    [0080]FIG. 2 shows an example of reference potential generation circuit  1  according to the first embodiment of the present invention.  
         [0081]    Though in the present circuit diagram the data correction signal is shown using two signals, NADJ[ 1 ] and NADJ[ 2 ], for the purpose of simplification, the number of data correction signals NADJ[n] can, of course, be increased so that a resistance value for adjustment can be further divided into smaller values. Accordingly, it becomes possible to combine two, or more, parallel circuits of resistors and transistors that are, respectively, connected in series to resistor R 11  and resistor R 13  and, thereby, to divide the resistance value for adjustment into smaller values.  
         [0082]    P channel type MOS transistors are denoted as QP 11 , QP 12 , QP 13 , QP 14 , QP 15 , QP 16  and QP 17 , N channel type MOS transistors are denoted as QN 11 , QN 12 , QN 13  and QN 14 , resistance elements are denoted as R 11 , R 12 , R 13 , R 14  and R 15 , a differential amplification circuit for amplifying the potential difference between internal nodes N 11  and N 13  formed of the above described transistors QP 13 , QP 14 , QP 15 , QN 12  and QN 13  is denoted as  11 , diodes are denoted as Di 01  and Di 02 , the power supply voltage is denoted as VDD and the ground voltage is denoted as VSS.  
         [0083]    The source of P channel type MOS transistor QP 11  is connected to power supply voltage VDD and the gate and drain, respectively, are connected to node N 14 . The source of P channel type MOS transistor QP 12  is connected to power supply voltage VDD, the gate is connected to node N 14  and the drain is connected to output node NBGR 1 . The source of P channel type MOS transistor QP 13  is connected to power supply voltage VDD, the gate is connected to node N 14  and the drain is connected to N 15 . The source of P channel type MOS transistor QP 14  is connected to N 15 , the gate is connected to node N 11  and the drain is connected to N 16 . The source of P channel type MOS transistor QP 15  is connected to N 15 , the gate is connected to node N 13  and the drain is connected to N 17 . The source of P channel type MOS transistor QP 16  is connected to node NBGR 1 , the gate is connected to node NADJ[ 2 ] and the drain is connected to N 18 . The source of P channel type MOS transistor QP 17  is connected to NBGR 1 , the gate is connected to node NADJ[ 1 ] and the drain is connected to N 19 .  
         [0084]    The gate of N channel type MOS transistor QN 11  is connected to node NBIAS, the source is connected to ground voltage VSS and the drain is connected to node N 104 . The gate and the drain of N channel type MOS transistor QN 12  are connected to node N 16  and the source is connected to ground voltage VSS. The gate of N channel type MOS transistor QN 13  is connected to node N 16 , the source is connected to ground voltage VSS and the drain is connected to node N 17 . The gate of N channel type MOS transistor QN 14  is connected to node N 17 , the source is connected to ground voltage VSS and the drain is connected to node NBGRA.  
         [0085]    As for the potential supplied to node NBIAS, a potential slightly higher than the threshold value (Vt) of N channel type MOS transistor QN 11  is inputted in the same manner as in the conventional circuit so that the input allows a constant current to flow through N channel type MOS transistor QN 11 .  
         [0086]    Differential amplification circuit  11  is formed of the above described transistors QP 13 , QP 14 , QP 15 , QN 12  and QN 13 , wherein nodes N 11  and N 13  become input terminals and node N 17  becomes an output terminal. In the case that the level of node N 13  is higher than that of node N 11 , logic potential “L” is generated at node N 17  and, on the other hand, in the case that the level of node N 13  is lower than that of node N 11 , logic potential “H” is generated at node N 17 .  
         [0087]    One end of resistance element R 11  is connected to node N 18  and the other end is connected to node N 11 . One end of resistance element R 12  is connected to node N 11  and the other end is connected to node N 12 . One end of resistance element R 13  is connected to node N 19  and the other end is connected to node N 13 . One end of resistance element R 14  is connected to node NBGR 1  and the other end is connected to node N 18 . One end of resistance element R 15  is connected to node NBGR 1  and the other end is connected to node N 19 .  
         [0088]    The P type diffusion region of diode Di 01  is connected to node N 13  and the N type diffusion region is connected to ground voltage VSS. The P type diffusion region of diode Di 02  is connected to node N 12  and the N type diffusion region is connected to ground voltage VSS.  
         [0089]    In addition, the sizes of the transistors are set so that the resistance values of the transistors at the time when QP 16  and QP 17  become of the ON condition do not have any influence, in comparison with the resistance values of resistors R 11 , R 12 , R 13 , R 14  and R 15 .  
         [0090]    In the case that correction signals NADJ[ 1 ] and NADJ[ 2 ] are both at the “H” logic level, for example, rs 11  in equation (1-1) becomes the sum of the resistance values R 11  and R 14  while rs 13  becomes the sum of the resistance values R 13  and R 15 .  
         [0091]    That is to say, the logic level of correction signal NADJ[n] allows changes in the resistance ratio of rs 11  to rs 13  and in the resistance ratio of rs 11  to rs 12  in equation (1-1) and the value of p in (equation 1-2) can be varied and, therefore, it becomes possible to vary the reference voltage and the power supply voltage detection voltage.  
         [0092]    [0092]FIG. 3 shows a reference potential generation circuit according to the second embodiment of the present invention. Though in the present circuit diagram, data correction signals are shown using two signals, NADJ[ 3 ] and NADJ[ 4 ], for the purpose of simplification, the number of data correction signals NADJ[n] can, of course, be increased so that the value of the divided area of the diodes can further divided into smaller values. Accordingly, two, or more, series circuits of diodes and transistors can be combined so as to be, respectively, connected in parallel to diode Di 21  and to Di 22 .  
         [0093]    P channel type MOS transistors are denoted as QP 11 , QP 12 , QP 13 , QP 14  and QP 15 , N channel type MOS transistors are denoted as QN 11 , QN 12 , QN 13 , QN 14 , QN 21  and QN 22 , resistance elements are denoted as R 21 , R 22  and R 23 , a differential amplification circuit for amplifying the potential difference between internal nodes N 21  and N 23  formed of the above described transistor QP 13 , QP 14 , QP 15 , QN 12  and QN 13  is denoted as  11 , diodes are denoted as Di 21 , Di 22 , Di 23  and Di 24 , the power supply voltage is denoted as VDD and the ground voltage is denoted as VSS.  
         [0094]    The source of P channel type MOS transistor QP 11  is connected to power supply voltage VDD and the gate and drain, respectively, are connected to node N 14 . The source of P channel type MOS transistor QP 12  is connected to power supply voltage VDD, the gate is connected to node N 14  and the drain is connected to node NBGR 1 . The source of P channel type MOS transistor QP 13  is connected to power supply voltage VDD, the gate is connected to node N 14  and the drain is connected to N 15 . The source of P channel type MOS transistor QP 14  is connected to N 15 , the gate is connected to node N 21  and the drain is connected to N 16 . The source of P channel type MOS transistor QP 15  is connected to N 15 , the gate is connected to node N 23  and the drain is connected to N 17 .  
         [0095]    The gate of N channel type MOS transistor QN 11  is connected to node NBIAS, the source is connected to ground voltage VSS and the drain is connected to node N 14 . The gate and the drain of N channel type MOS transistor QN 12  are connected to node N 16  and the source is connected to ground voltage VSS. The gate of N channel type MOS transistor QN 13  is connected to node N 16 , the source is connected to ground voltage VSS and the drain is connected to node N 17 . The gate of N channel type MOS transistor QN 14  is connected to node N 17 , the source is connected to ground voltage VSS and the drain is connected to node NBGR 1 .  
         [0096]    The gate of N channel type MOS transistor QN 21  is connected to node NADJ[ 3 ], the source is connected to ground voltage VSS and the drain is connected to node N 24 . The gate of N channel type MOS transistor QN 22  is connected to node NADJ[ 4 ], the source is connected to ground voltage VSS and the drain is connected to node N 25 .  
         [0097]    As for the potential supplied to node NBIAS, a potential slightly higher than the threshold value (Vt) of N channel type MOS transistor QN 11  is inputted in the same manner as in the conventional circuit so that the input allows a constant current to flow through N channel type MOS transistor QN 11 .  
         [0098]    Differential amplification circuit  11  is formed of the above described transistors QP 13 , QP 14 , QP 15 , QN 12  and QN 13 , wherein nodes N 21  and N 23  become input terminals and node N 17  becomes an output terminal. In the case that the level of node N 23  is higher than that of node N 21 , logic potential “L” is generated at node N 17  and, on the other hand, in the case that the level of node N 23  is lower than that of node N 21 , logic potential “H” is generated at node N 17 .  
         [0099]    One end of resistance element R 21  is connected to node NBGR 1  and the other end is connected to node N 21 . One end of resistance element R 22  is connected to node N 21  and the other end is connected to node N 22 . One end of resistance element R 23  is connected to node NBGR 1  and the other end is connected to node N 23 .  
         [0100]    The P type diffusion region of diode Di 21  is connected to node N 23  and the N type diffusion region is connected to ground voltage VSS. The P type diffusion region of diode Di 22  is connected to node N 22  and the N type diffusion region is connected to ground voltage VSS. The P type diffusion region of diode Di 23  is connected to node N 23  and the N type diffusion region is connected to node N 25 . The P type diffusion region of diode Di 24  is connected to node N 22  and the N type diffusion region is connected to node N 24 .  
         [0101]    In addition, the sizes of the transistors are set so that the resistance values of the transistors at the time when QP 21  and QP 22  become of the ON condition do not have any influence, in comparison with the parasitic resistance of the diodes.  
         [0102]    In the case that correction signals NADJ[ 3 ] and NADJ[ 4 ] are both at the “H” logic level, for example, Is 11  in equation (1-1) becomes the saturation current value of the total areas of Di 21  and Di 23 , and Is 12  becomes the saturation current value of the total area of Di 22  and Di 24 .  
         [0103]    That is to say, the logic level of correction signals NADJ[n] allow alteration of the current ratio of Is 11  to Is 12  in equation (1-1), and the value of P in (equation 1-2) can be varied so that it becomes possible to vary the reference voltage and the power supply voltage detection voltage.  
         [0104]    [0104]FIG. 4 shows a reference potential generation circuit according to the third embodiment of the present invention.  
         [0105]    Though in the present circuit diagram the data correction signals are shown using two signals, NADJ[ 5 ] and NADJ[ 6 ], for the purpose of simplification, the number of data correction signals NADJ[n] can, of course, be increased so that, in regard to the amount of division, the size of the transistors can be further divided into smaller amounts. Accordingly, two, or more, parallel circuits having one pair of transistors are combined so as to be connected in series to transistors QP 31  and QP 32 , respectively, and the gate of one transistor in each circuit can be connected to the gates of transistors QP 31  and QP 32 .  
         [0106]    P channel type MOS transistors are denoted as QP 11 , QP 12 , QP 13 , QP 31 , QP 32 , QP 33  QP 34 , QP 35  and QP 36 , N channel type MOS transistors are denoted as QN 11 , QN 12 , QN 13  and QN 14 , resistance elements are denoted as R 21 , R 22  and R 23 , a differential amplification circuit for amplifying the potential difference between internal nodes N 31  and N 33  formed of the above described transistors QP 13 , QP 31 , QP 32 , QP 33 , QP 34 , QP 35 , QN 12  and QN 13  is denoted as  12 , diodes are denoted as Di 01  and Di 02 , the power supply voltage is denoted as VDD and the ground voltage is denoted as VSS.  
         [0107]    The source of P channel type MOS transistor QP 11  is connected to power supply voltage VDD and the gate and drain, respectively, are connected to node N 14 . The source of P channel type MOS transistor QP 12  is connected to power supply voltage VDD, the gate is connected to node N 14  and the drain is connected to NBGR 1 . The source of P channel type MOS transistor QP 13  is connected to power supply voltage VDD, the gate is connected to node N 14  and the drain is connected to N 35 . The source of P channel type MOS transistor QP 31  is connected to N 35 , the gate is connected to node N 31  and the drain is connected to N 38 . The source of P channel type MOS transistor QP 32  is connected to N 35 , the gate is connected to node N 33  and the drain is connected to N 39 . The source of P channel type MOS transistor QP 33  is connected to N 38 , the gate is connected to node N 31  and the drain is connected to N 36 . The source of P channel type MOS transistor QP 34  is connected to N 39 , the gate is connected to node N 33  and the drain is connected to N 37 . The source of P channel type MOS transistor QP 35  is connected to N 38 , the gate is connected to node NADJ[ 5 ] and the drain is connected to N 36 . The source of P channel type MOS transistor QP 36  is connected to N 39 , the gate is connected to node NADJ[ 6 ] and the drain is connected to N 37 .  
         [0108]    In addition, the resistance values of transistors QP 35  and QP 36 , in the case that they are in the active condition, are set so as not to have any influence, in comparison with the resistance values in the case that transistors QP 33  and QP 34  are activated.  
         [0109]    The gate of N channel type MOS transistor QN 11  is connected to node NBIAS, the source is connected to ground voltage VSS and the drain is connected to node N 14 . The gate and the drain of N channel type MOS transistor QN 12  are connected to node N 36  and the source is connected to ground voltage VSS. The gate of N channel type MOS transistor QN 13  is connected to node N 36 , the source is connected to ground voltage VSS and the drain is connected to node N 37 . The gate of N channel type MOS transistor QN 14  is connected to node N 37 , the source is connected to ground voltage VSS and the drain is connected to node NBGR 1 .  
         [0110]    As for the potential supplied to node NBIAS, a potential slightly higher than the threshold value (Vt) of QN 11  is inputted in the same manner as in the conventional circuit so that the input allows a constant current to flow through QN 11 .  
         [0111]    Differential amplification circuit  12  is formed of the above described transistors QP 13 , QP 31 , QP 32 , QP 33 , QP 34 , QP 35 , QP 36 , QN 12  and QN 13 , wherein nodes N 31  and N 33  become input terminals and node N 37  becomes an output terminal. In the case that the level of node N 33  is higher than that of node N 31 , logic potential “L” is generated at node N 37  and, on the other hand, in the case that the level of node N 33  is lower than that of node N 31 , logic potential “H” is generated at node N 37 .  
         [0112]    One end of resistance element R 21  is connected to node NBGR 1  and the other end is connected to node N 31 . One end of resistance element R 22  is connected to node N 31  and the other end is connected to node N 32 . One end of resistance element R 23  is connected to node NBGR 1  and the other end is connected to node N 33 .  
         [0113]    The P type diffusion region of diode Di 01  is connected to node N 33  and the N type diffusion region is connected to ground voltage VSS. The P type diffusion region of diode Di 02  is connected to node N 32  and the N type diffusion region is connected to ground voltage VSS.  
         [0114]    The sizes of the transistors having gates to which the nodes N 31  and N 33  are connected are changed, that is to say, it becomes possible to vary the threshold values of the transistors in the case that, for example, correction signal NADJ[ 5 ] is at the “H” logic level and NADJ[ 6 ] is at the “L” logic level and, therefore, adjustment becomes possible even in the case of dispersion in the threshold values of transistors QP 31  and QP 32 .  
         [0115]    [0115]FIG. 5 shows a reference potential generation circuit according to the fourth embodiment of the present invention.  
         [0116]    Though in the present circuit diagram the data correction signals are shown using two signals, NADJ[ 7 ] and NADJ[ 8 ], for the purpose of simplification, the number of data correction signals NADJ[n] can, of course, be increased so that, in regard to the amount of division, the size of the transistors can be further divided into smaller amounts. Accordingly, two, or more, series circuits having one pair of transistors are combined so as to be connected in parallel to transistors QN 41  and QN 42 , respectively, and the gate of one transistor in each circuit can be connected to the common gate of transistors QN 41  and QN 42 .  
         [0117]    P channel type MOS transistors are denoted as QP 11 , QP 12 , QP 13 , QP 41  and QP 42 , N channel type MOS transistors are denoted as QN 11 , QN 41 , QN 42  QN 43 , QN 44 , QN 45 , QN 46  and QN 14 , resistance elements are denoted as R 21 , R 22  and R 23 , a differential amplification circuit for amplifying the potential difference between internal nodes N 31  and N 33  formed of the above described transistors QP 13 , QP 41 , QP 42 , QN 41 , QN 42 , QN 43 , QN 44 , QN 45  and QN 46  is denoted as  13 , diodes are denoted as Di 01  and Di 02 , the power supply voltage is denoted as VDD and the ground voltage is denoted as VSS.  
         [0118]    The source of P channel type MOS transistor QP 11  is connected to power supply voltage VDD and the gate and drain, respectively, are connected to node N 14 . The source of P channel type MOS transistor QP 12  is connected to power supply voltage VDD, the gate is connected to node N 14  and the drain is connected to node NBGR 1 . The source of P channel type MOS transistor QP 13  is connected to power supply voltage VDD, the gate is connected to node N 14  and the drain is connected to N 45 . The source of P channel type MOS transistor QP 41  is connected to N 45 , the gate is connected to node N 31  and the drain is connected to N 46 . The source of P channel type MOS transistor QP 42  is connected to N 45 , the gate is connected to node N 33  and the drain is connected to N 47 .  
         [0119]    The gate of N channel type MOS transistor QN 11  is connected to node NBIAS, the source is connected to ground voltage VSS and the drain is connected to node N 14 . The gate and the drain of N channel type MOS transistor QN 41  are connected to node N 46  and the source is connected to ground voltage VSS. The gate of N channel type MOS transistor QN 42  is connected to node N 46 , the source is connected to ground voltage VSS and the drain is connected to node N 47 . The gate and the drain of N channel type MOS transistor QN 43  are connected to node N 46  and the source is connected to N 48 . The gate of N channel type MOS transistor QN 44  is connected to node N 46 , the source is connected to node N 49  and the drain is connected to node N 47 . The gate of N channel type MOS transistor QN 45  is connected to node NADJ[ 7 ], the source is connected to ground voltage VSS and the drain is connected to node N 48 . The gate of N channel type MOS transistor QN 46  is connected to node NADJ[ 8 ], the source is connected to ground voltage VSS and the drain is connected to node N 49 . The gate of N channel type MOS transistor QN 14  is connected to node N 47 , the source is connected to ground voltage VSS and the drain is connected to node NBGR 1 .  
         [0120]    In addition, the resistance values of N channel type MOS transistors QN 45  and QN 46 , in the case that they are in the active condition, are set so as not to have any influence, in comparison with the resistance values in the case that N channel type MOS transistors QN 43  and QN 44  are activated.  
         [0121]    As for the potential supplied to node NBIAS, a potential slightly higher than the threshold value (Vt) of N channel type MOS transistor QN 11  is inputted in the same manner as in the conventional circuit so that the input allows a constant current to flow through N channel type MOS transistor QN 11 .  
         [0122]    Differential amplification circuit  13  is formed of the above described transistors QP 13 , QP 41 , QP 42 , QN 41 , QN 42 , QN 43 , QN 44 , QN 45  and QN 46  wherein nodes N 31  and N 33  become input terminals and node N 47  becomes an output terminal. In the case that the level of node N 33  is higher than that of node N 31 , logic potential “L” is generated at node N 47  and, on the other hand, in the case that the level of node N 33  is lower than that of node N 31 , logic potential “H” is generated at node N 47 .  
         [0123]    One end of resistance element R 21  is connected to node NBGR 1  and the other end is connected to node N 31 . One end of resistance element R 22  is connected to node N 31  and the other end is connected to node N 32 . One end of resistance element R 23  is connected to node NBGR 1  and the other end is connected to node N 33 .  
         [0124]    The P type diffusion region of diode Di 01  is connected to node N 33  and the N type diffusion region is connected to ground voltage VSS. The P type diffusion region of diode Di 02  is connected to node N 32  and the N type diffusion region is connected to ground voltage VSS.  
         [0125]    The sizes of the transistors forming a current mirror circuit are changed, that is to say, it becomes possible to vary the threshold values of the transistors in the case that, for example, correction signal NADJ[ 7 ] is at the “H” logic level and NADJ[ 8 ] is at the “L” logic level and, thereby, adjustment becomes possible even in the case of dispersion in the threshold values of transistors QN 41  and QN 42 .  
         [0126]    Here, though the first to fourth embodiments are separately described above, it is possible to implement two, or more, types of the above embodiments in combination and the effects of adjustment in the voltage detection level can, of course, be gained.  
         [0127]    [0127]FIG. 6 shows a semiconductor device having a voltage detection level correction circuit according to the fifth embodiment of the present invention.  
         [0128]    A reference potential generation circuit represented by a band gap reference circuit is denoted as  61  and an output node for generating reference voltage level VBGR 1  is denoted as NBGR 1 . A divided voltage potential generation circuit for generating a divided voltage level that is independent of the power supply voltage is denoted as  62  and an output node for generating divided voltage level VHAL 1  is denoted as NHAL 1 . A differential amplification circuit for comparing output signal voltage level VBGR 1  to potential level VHAL 1  so as to generate a comparison output VPOR is denoted as  63 . In the case that the power supply voltage is no greater than the set voltage, that is to say, in the case that reference potential VBGR 1  is higher than divided voltage potential VHAL 1 , output signal VPOR outputs the “H” logic level and converts microcomputer logic unit  6  and ferroelectric memory  5  to the inactive condition. In addition, in the case that the power supply voltage is no less than the set voltage, that is to say, in the case that reference potential VBGR 1  is lower than divided voltage potential VHAL 1 , output signal VPOR outputs the “L” logic level and converts microcomputer logic unit  6  and ferroelectric memory  5  to the active condition. A power supply voltage detection circuit formed of reference potential generation circuit  61 , divided voltage potential generation circuit  62  and differential amplification circuit  63  is denoted as  64 .  
         [0129]    A ferroelectric memory for storing arbitrary information is denoted as  5 . A microcomputer logic unit for controlling the ferroelectric memory is denoted as  6 . A data latch circuit for storing data read out from ferroelectric memory  5  and for storing output signals NADJ[n] utilized for correction of divided voltage potential VHAL 1  is denoted as  7 .  
         [0130]    In addition, in the following description it is assumed that the circuit (FIG. 11) described as the conventional circuit is used for reference potential generation circuit  61  in FIG. 6.  
         [0131]    [0131]FIG. 7 shows a divided voltage potential generation circuit according to the fifth embodiment of the present invention.  
         [0132]    Though in the present circuit diagram the data correction signals are shown using two signals, NADJ[ 9 ] and NADJ[ 10 ], for the purpose of simplification, the number of data correction signals NADJ[n] can, of course, be increased so that the resistance value for adjustment can be further divided into smaller values. Accordingly, two, or more, parallel circuits of resistors and transistors are combined so as to be connected in series to resistors RA 01  and RA 02 , respectively.  
         [0133]    A P channel type MOS transistor is denoted as QP 71 , an N channel type MOS transistor is denoted as QN 71 , resistance elements are denoted as RA 01 , RA 02 , RA 03  and RA 04 , the power supply voltage is denoted as VDD and the ground voltage is denoted as VSS.  
         [0134]    One end of resistance element RA 03  is connected to power supply voltage VDD and the other end is connected to node N 71 . One end of resistance element RA 01  is connected to node N 71  and the other end is connected to node NHAL 1 . One end of resistance element RA 02  is connected to node N 72  and the other end is connected to node NHAL 1 . One end of resistance element RA 04  is connected to ground voltage VSS and the other end is connected to output node N 72 .  
         [0135]    The source of P channel type MOS transistor QP 71  is connected to power supply voltage VDD, the gate is connected to node NADJ[ 9 ] and the drain is connected to node N 71 .  
         [0136]    The gate of N channel type MOS transistor QN 71  is connected to node NADJ[ 10 ], the source is connected to ground voltage VSS and the drain is connected to node N 72 .  
         [0137]    The resistance values of transistors QN 71  and QP 71  at the time when they are activated are set so as not to have any influence in comparison with the resistance values of resistance elements RA 01 , RA 02 , RA 03  and RA 04 .  
         [0138]    In the case that, for example, NADJ[ 9 ] is logically at “L” and NADJ[ 10 ] is logically at “H”, divided voltage potential NHAL 1  is divided according to the ratio of resistance value RA 01  to resistance value RA 02 . In addition, in the case that NADJ[ 9 ] is logically at “H” and NADJ[ 10 ] is logically at “H”, divided voltage potential NHAL 1  is divided according to the ratio of the sum of resistance values RA 01  and RA 03  to resistance value RA 02 .  
         [0139]    Accordingly, adjustment of the divided voltage potential becomes possible according to the conditions of NADJ[n] and, therefore, it becomes possible to vary the voltage detection level.  
         [0140]    [0140]FIG. 8 shows a semiconductor device having the voltage detection level correction circuit according to the sixth embodiment of the present invention.  
         [0141]    A reference potential generation circuit represented by a band gap reference circuit is denoted as  81  and an output node for generating reference voltage level VBGR 1  is denoted as NBGR 1 . A divided voltage potential generation circuit for generating a divided voltage level that is dependent on the power supply voltage is denoted as  82  and an output node for generating divided voltage level VHAL 1  is denoted as NHAL 1 . A differential amplification circuit for comparing output signal voltage level VBGR 1  to potential level VHAL 1  so as to generate a comparison output VPOR is denoted as  83 . In the case that the power supply voltage is no greater than the set voltage, that is to say, in the case that reference potential VBGR 1  is higher than divided voltage potential VHAL 1 , output signal VPOR outputs the “H” logic level and converts microcomputer logic unit  6  and ferroelectric memory  5  to the inactive condition. In addition, in the case that the power supply voltage is no less than the set voltage, that is to say, in the case that reference potential VBGR 1  is lower than divided voltage potential VHAL 1 , output signal VPOR outputs the “L” logic level and converts microcomputer logic unit  6  and ferroelectric memory  5  to the active condition. A power supply voltage detection circuit formed of reference potential generation circuit  81 , divided voltage potential generation circuit  82  and differential amplification circuit  83  is denoted as  84 .  
         [0142]    A ferroelectric memory for storing arbitrary information is denoted as  5 . A microcomputer logic unit for controlling ferroelectric memory  5  is denoted as  6 . A data latch circuit for storing data read out from ferroelectric memory  5  and for storing output signals NADJ[n] utilized for correction of reference voltage potential VBGR 1  is denoted as  7 .  
         [0143]    In addition, in the following description, it is assumed that the circuits (FIG. 11 and FIG. 12) described as conventional circuits are used for  81  and  82  in FIG. 8.  
         [0144]    Here, it becomes possible to reduce the dispersion in the threshold values of the transistors in order to correct the voltage detection level by using a differential amplification circuit that is of the same type as differential amplification circuit  12  or  13  having the configuration described in the voltage detection level correction circuit (FIG. 4 or FIG. 5) according to the third or fourth embodiment for differential amplification circuit  83 .  
         [0145]    Though a voltage detection level correction circuit (first to fourth embodiments) for correcting the reference potential, a voltage detection level correction circuit (fifth embodiment) for correcting the divided voltage potential and a voltage detection level correction circuit (sixth embodiment) for correcting the output potential of the differential amplification circuit are shown above, it is possible to combine any two, or more, from among these three types so as to correct the voltage detection level in an effective manner.  
         [0146]    [0146]FIG. 9 shows a voltage detection level correction circuit according to the seventh embodiment, that is to say, a correction circuit in the case wherein the above described three types of voltage detection level correction circuits are combined.  
         [0147]    A fine adjustment of the reference voltage for each chip becomes possible so that the precision of detection of the power supply voltage is increased even after completion of diffusion by implementing the configuration and control of the present invention described above in reference to FIGS.  1  to  9 .  
         [0148]    Though in the present description a ferroelectric memory  5  is referred to, prevention of malfunction and data protection in the case of fluctuation in the power supply during data write-in are common issues in regard to other non-volatile memories and, therefore, the present circuit configuration is effective with respect to generic non-volatile memories.