Abstract:
A quartz-crystal oscillator circuit substantially reduces the start-up time of the crystal oscillator circuit by utilizing a start-up time reduction circuit that adds additional gain to the crystal oscillator circuit during the start-up period, and removes the additional gain as the oscillator circuit nears steady state operation. Furthermore, the start-up time reduction circuit dynamically monitors the oscillation amplitude. If the build up of oscillation is interrupted, the additional gain will be re-applied.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to crystal oscillator circuits and, more particularly, to a crystal oscillator circuit that has a start-up time reduction circuit. 
   2. Description of the Related Art 
   An oscillator is a circuit that outputs a periodic signal.  FIG. 1  shows a schematic diagram that illustrates a prior-art, quartz-crystal oscillator circuit  100 . As shown in  FIG. 1 , crystal oscillator circuit  100 , which is also known as a Pierce oscillator, includes a crystal circuit  110  that has a quartz crystal  112  and a bias resistor R. 
   Quartz crystal  112 , in turn, has a first terminal that is connected to a first node N 1 , and a second terminal that is connected to a second node N 2 . Further, bias resistor R also has a first terminal that is connected to the first node N 1 , and a second terminal that is connected to the second node N 2 . 
   In addition, crystal oscillator circuit  100  includes a first capacitor  114  that has a first plate connected to the first node N 1  and a second plate connected to ground, and a second capacitor  116  that has a first plate connected to the second node N 2  and a second plate connected to ground. 
   Crystal oscillator circuit  100  further includes a logic device  120  that has an odd number of serially-connected inverters, including a first inverter  120 A that is connected to the first node N 1 , a last inverter  120 B that is connected to the second node N 2 , and a next-to-last inverter  120 C that is connected to last inverter  120 B. Logic device  120  also has an output inverter  120 D that is connected to the input of last inverter  120 B to output a clock signal CLK. 
   In operation, when power is first applied, crystal oscillator circuit  100  produces an oscillating signal OS on the first node N 1  that builds in magnitude over a period of time until the magnitude of the oscillating signal OS reaches a final steady state level. A start-up period, in turn, is typically defined as the time from when power is first applied to when the magnitude of the oscillating signal reaches approximately 85%–90% of the final steady state level. 
     FIG. 2  shows a timing diagram that illustrates the start-up period of crystal oscillator circuit  100 . During power up, noise is amplified by oscillator circuit  100 . As shown in  FIG. 2 , through the filtering property of the quartz crystal, only the natural frequency of the crystal is amplified to produce an oscillating signal OS, while the other frequencies are attenuated. As further shown in  FIG. 2 , oscillating signal OS has an envelope  210  that builds in magnitude over the start-up period, which extends from time t 0  to time t 1 . 
   In many applications, a shorter start-up time is desirable. One approach to reducing the start-up time of a crystal oscillator circuit is to increase the gain in the crystal oscillator circuit. Increasing the gain to reduce the start-up time, however, can hasten the aging of the crystal, and hence prematurely degrade the accuracy and reliability of the crystal. 
   Another approach to reducing the start-up time of a crystal oscillator circuit is to provide additional gain during the start-up period, and then shut off the additional gain after the oscillation has been deemed to be “stable” (e.g., reached approximately 85%–90% of the final steady state level). Since the extra gain is provided only during the start-up period, the negative effect on the crystal is relatively minor. 
   However, one problem with the prior approaches to providing additional gain only during the start-up period is that these prior approaches lack any mechanism to re-apply the extra gain to aid the build up of oscillation if the determination of a “stable” oscillation is incorrect, or for any reason the oscillation is interrupted. Thus, there is a need for an approach to reducing the start-up time of a quartz-crystal oscillator circuit that eliminates the above limitations. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic diagram illustrating a prior-art, quartz-crystal oscillator circuit  100 . 
       FIG. 2  is a timing diagram illustrating the start-up period of crystal oscillator circuit  100 . 
       FIG. 3  is a schematic diagram illustrating an example of a quartz-crystal oscillator circuit  300  in accordance with the present invention. 
       FIG. 4  is a timing diagram of a simulation result illustrating an example of a start-up period of crystal oscillator circuit  300  in accordance with the present invention. 
       FIG. 5  is a timing diagram illustrating the enable signal EN 1  with respect to the oscillating signal OS in accordance with the present invention. 
       FIG. 6  is a timing diagram illustrating the enable signal EN 2  in accordance with the present invention. 
       FIG. 7  is a timing diagram illustrating the enable signal EN 3  with respect to the oscillating signal OS in accordance with the present invention. 
       FIG. 8  is a timing diagram illustrating the enable signal EN 4  with respect to the oscillating signal OS in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 3  shows a schematic diagram that illustrates an example of a quartz-crystal oscillator circuit  300  in accordance with the present invention. As described in greater detail below, crystal oscillator circuit  300  substantially reduces the start-up time by providing additional gain only during the start-up period (when the oscillation is building toward a steady state level). 
   In addition, crystal oscillator circuit  300  dynamically monitors the oscillation of circuit  300 . As a result, even if the oscillation collapses following the start-up period after the additional gain has been shut off, circuit  300  dynamically responds to the reduction of oscillation and turns on the additional gain again. 
   Crystal oscillator circuit  300  is similar to crystal oscillator circuit  100  and, as a result, utilizes the same reference numerals to designate the structures which are common to both circuits. As shown in  FIG. 3 , crystal oscillator circuit  300  differs from crystal oscillator circuit  100  in that circuit  300  includes a start-up time reduction circuit  310  that is connected to logic device  120 . Circuit  310  provides additional gain when the magnitude of the voltage on the first node N 1  is within a pre-determined range, such as within 10% to 90% of a final steady state level. 
   As further shown in  FIG. 3 , start-up time reduction circuit  310  includes a gain stage  312  that has two serially-connected inverters that lie in parallel with the last two inverters of logic device  120  such that the input of the first inverter of the last two inverters of logic device  120  and the input of the first inverter of gain stage  312  are connected together. 
   In addition, the output of the last inverter of logic device  120  and the output of the last inverter of gain stage  312  are connected together and to node N 2 . In the  FIG. 3  example, gain stage  312  is implemented with inverter  314  (which has a PMOS transistor MP 4  and an NMOS transistor MN 3 ) and inverter  316  (which has a PMOS transistor MP 2  and an NMOS transistor MN 1 ). 
   In addition to gain stage  312 , start-up time reduction circuit  300  also includes a plurality of control transistors that control gain stage  312 . The control transistors include a PMOS control transistor MP 3  that is connected to PMOS transistor MP 4  and a supply voltage, and an NMOS control transistor MN 4  that is connected to NMOS transistor MN 3  and ground. 
   The control transistors also include a PMOS control transistor MP 1 A that is connected to PMOS transistor MP 2 , and an NMOS control transistor MN 2 A that is connected to NMOS transistor MN 1 . Further, the control transistors include a PMOS control transistor MP 1  that is connected to PMOS transistor MP 1 A and the supply voltage, and an NMOS control transistor MN 2  that is connected to NMOS transistor MN 2 A and ground. 
   As further shown in  FIG. 3 , start-up time reduction circuit  310  also includes a control circuit  320  that receives the oscillating signal OS on the first node N 1 , and sets the logic states of a number of enable signals EN 1 –EN 4 , which are output to the control transistors, to enable inverters  314  and  316  via the control transistors when the magnitude of the oscillating OS is building up (e.g., is still within 10%–90% of the final steady state level). 
   In the  FIG. 3  example, control circuit  320  includes an inverter  322 , which has a PMOS transistor MP 8  and an NMOS transistor MN 8 . In accordance with the present invention, inverter  322  is sized (2/0.3 PMOS, 0.5/0.35 NMOS) to have a trip point that is substantially higher than one-half the supply voltage (VDD/2), such that inverter  322  changes the output from a logic high to a logic low when the magnitude of the oscillating signal OS on the first node N 1  exceeds the trip point. Ideally, the trip point of inverter  322  would be equal to 85%–90% of the final steady state level of the oscillating signal OS. 
   Control circuit  320  additionally includes an inverter  324 , which has a PMOS transistor MP 5  and an NMOS transistor MN 5 . Inverter  324 , which is connected to inverter  322 , outputs the enable signal EN 1  to PMOS control transistor MP 1 . In addition, control circuit  320  also includes an inverter  330 , which has a PMOS transistor MP 7  and an NMOS transistor MN 7 , and an inverter  332 , which has a PMOS transistor MP 6  and an NMOS transistor MN 6 . Inverter  332 , which is connected to inverter  330 , outputs the enable signal EN 4  to NMOS control transistor MN 2 . 
   Further, control circuit  320  includes an inverter  334 , which has a PMOS transistor MP 11  and an NMOS transistor MN 11 . In accordance with the present invention, inverter  334  is sized (1/0.3 PMOS, 0.5/0.35 NMOS) to have a trip point which is significantly lower that VDD/2 such that a small magnitude of the oscillating signal OS is enough to cause inverter  334  to change the output from a logic high to a logic low. 
   Control circuit  320  additionally includes an inverter  336 , which has a PMOS transistor MP 10  and an NMOS transistor MN 10 . Inverter  336 , which is connected to inverter  334 , outputs the enable signal EN 3 . Further, control circuit  320  includes an inverter  338 , which has a PMOS transistor MP 9  and an NMOS transistor MN 9 . Inverter  338 , which is connected to inverter  336 , outputs the enable signal EN 2 . 
   During the start-up period, the magnitude of the oscillating signal OS on the first node N 1  is greater than the trip point of inverter  334 , but less than the trip point of inverter  322 . Thus, since the magnitude of the oscillating signal OS is insufficient to trip inverter  322 , control transistors MP 1  and MN 2  are turned on. In addition, since the magnitude of the oscillating signal OS is sufficient to flip inverter  334 , the enable signal EN 3  output by inverter  336  is, therefore, high. When the enable signal EN 3  is high, control transistors MN 2 A and MN 4  respond by turning on. 
   Further, inverter  338  inverts the signal output by inverter  336  to output the enable signal EN 2 . Since the enable signal EN 3  is high and the enable signal EN 2  is low, control transistors MP 1 A and MP 3  respond by turning on. Thus, when power is first applied, transistors MP 1 , MP 1 A, MN 2 , MN 2 A, MP 3 , and MN 4  are all turned on when the magnitude of the voltage of the first node N 1  is greater than the trip point of inverter  334  and less than the trip point of inverter  322 . 
   When transistors MP 1 , MP 1 A, MN 2 , MN 2 A, MP 3 , and MN 4  are all turned on, the enable signals EN 1 –EN 4  are active and gain stage  312  is added in parallel to logic device  120 . When gain stage  312  is added in parallel, the start-up time can be significantly reduced. 
     FIG. 4  shows a timing diagram of a simulation result that illustrates an example of a start-up period of crystal oscillator circuit  300  in accordance with the present invention. As shown in  FIG. 4 , at time t 0 , circuit  300  begins generating an oscillating signal OS, which has an envelope  410 , on the first node N 1  when the supply voltage is first applied. During the start-up period, the magnitude of the oscillating signal OS increases until the voltage level reaches 90% of a final steady state level at time t 1 , approximately 400 uS later in the  FIG. 4  example. 
     FIG. 5  shows a timing diagram that illustrates the enable signal EN 1  with respect to the oscillating signal OS in accordance with the present invention. As shown in  FIG. 5 , at time t 0 , when power is first applied, the enable signal EN 1  has a logic low which, in turn, enables PMOS control transistor MP 1 . Thus, before the oscillating signal OS reaches the trip point of inverter  322 , PMOS control transistor MP 1  is enabled by enable signal EN 1 . 
   In addition, as further shown in  FIG. 5 , when the magnitude of the oscillating signal OS passes the trip point of inverter  322 , the enable signal EN 1  follows the oscillating signal OS. After this, each time the oscillating signal OS reaches a maximum value, the enable signal EN 1  turns off PMOS control transistor MP 1 . 
     FIG. 6  shows a timing diagram that illustrates the enable signal EN 2  in accordance with the present invention. As shown in  FIG. 6 , at time t 0 , when power is first applied, the enable signal EN 2  has a logic low which, in turn, enables PMOS control transistors MP 1 A and MP 3 . 
   In addition, as further shown in  FIG. 6 , when the magnitude of the oscillating signal OS passes the trip point of inverter  334 , the enable signal EN 2  is the inverse of the oscillating signal OS. After this, each time the oscillating signal OS reaches a maximum value, the enable signal EN 2  turns on PMOS control transistors MP 1 A and MP 3 . Further, as shown in  FIGS. 5 and 6 , the enable signals EN 1  and EN 2  are out of phase with each other once the magnitude of the oscillating signal OS has built up. 
     FIG. 7  shows a timing diagram that illustrates the enable signal EN 3  with respect to the oscillating signal OS in accordance with the present invention. As shown in  FIG. 7 , at time t 0 , when power is first applied, the enable signal EN 3  has a logic high which, in turn, enables NMOS control transistors MN 2 A and MN 4   
   In addition, as further shown in  FIG. 7 , when the magnitude of the oscillating signal OS passes the trip point of inverter  334 , the enable signal EN 3  is in phase with the oscillating signal OS. After this, each time the oscillating signal OS reaches a maximum value, the enable signal EN 3  has a logic high that turns on NMOS control transistors MN 2 A and MN 4 . 
     FIG. 8  shows a timing diagram that illustrates the enable signal EN 4  with respect to the oscillating signal OS in accordance with the present invention. As shown in  FIG. 8 , at time t 0 , when power is first applied, the enable signal EN 4  has a logic high which, in turn, enables NMOS control transistor MN 2 . Thus, before the oscillating signal OS reaches the trip point of inverter  322 , NMOS control transistor MN 2  is enabled by enable signal EN 4 . 
   In addition, as further shown in  FIG. 8 , when the magnitude of the oscillating signal OS passes the trip point of inverter  322 , the enable signal EN 4  is out of phase with the oscillating signal OS. After this, each time the oscillating signal OS reaches a maximum value, the enable signal EN 4  has a logic low that turns off NMOS control transistor MN 2 . Further, as shown in  FIGS. 7 and 8 , the enable signals EN 3  and EN 4  are out of phase with each other once the magnitude of the oscillating signal OS has built up. 
   During steady state operation (following the start-up period), when the oscillating signal OS has a minimum value, such as ground, inverter  322  outputs a logic high. Inverter  324  then inverts the logic high to output the enable signal EN 1  with a logic low. When the enable signal EN 1  goes low, control transistor MP 1  responds by turning on. 
   In addition, inverter  330  inverts the logic high output by inverter  322  to output a logic low, while inverter  332  inverts the logic low output by inverter  330  to output the enable signal EN 4  with a logic high. When the enable signal EN 4  goes high, control transistor MN 2  responds by turning on. 
   However, even though control transistors MP 1  and MN 2  are turned on each time the oscillating signal OS has the minimum value, transistors MP 1 A, MP 3 , MN 2 A, and MN 4  are turned off because inverter  334  outputs a logic high. When inverter  334  outputs a logic high, inverter  336  outputs the enable signal EN 3  with a logic low, and inverter  338  outputs the enable signal EN 2  with a logic high. 
   When the enable signal EN 2  goes high, control transistors MP 1 A and MP 3  respond by turning off. Similarly, when the enable signal EN 3  goes low, control transistors MN 2 A and MN 4  respond by turning off. Thus, each time the oscillating signal OS has a minimum value, such as ground, start-up time reduction circuit  310  is turned off. 
   When the oscillation signal OS has a maximum value, such as VDD, inverter  322  outputs a logic low. Inverter  324  then inverts the logic low to output the enable signal EN 1  with a logic high. When the enable signal EN 1  goes high, control transistor MP 1  responds by turning off. In addition, inverter  330  inverts the logic low output by inverter  322  to output a logic high, while inverter  332  inverts the logic high output by inverter  330  to output the enable signal EN 4  with a logic low. When the enable signal EN 4  goes low, control transistor MN 2  responds by turning off. Thus, each time the oscillating signal OS has a maximum value, such as VDD, start-up time reduction circuit  310  is turned off. 
   One of the advantages of the present invention is that the present invention substantially reduces the start-up time. As shown in  FIGS. 2 and 4 , the present invention reduces the start-up time from approximately 560 uS, as shown in the  FIG. 2  example, to approximately 400 uS as shown in the  FIG. 4  example. In addition, when the maximum value of the oscillating signal OS nears the final steady state value, gain stage  312  turns off (as explained above). 
   Another advantage of the present invention is that if the magnitude of the oscillating signal OS ever falls below the trip point of inverter  322  (and stays above the trip point of inverter  334 ), circuit  300  responds by re-applying the gain. As shown in  FIGS. 5–8 , if the oscillation magnitude is reduced, enable signals EN 1 –EN 4  are put back to the conditions when the amplitude of the oscillation is small. Therefore, there is no danger of turning off the extra gain prematurely. 
   It should be understood that the above descriptions are examples of the present invention, and that various alternatives of the invention described herein may be employed in practicing the invention. Thus, it is intended that the following claims define the scope of the invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.