Abstract:
In ATV (Advanced Television) system which compresses the band of high-definition video signal by using sub-band coding method, the high frequency components of the high-definition video signal are divided into two-dimensional blocks by a maximum value detector, and the adaptive block coefficients are generated according to the maximum value of each block by an adaptive block factor generator and are multiplied by each pixel signals to amplify the transmitting level. 
     Next, in a receiver circuit, the transmitted pixel signals of the high-definition video signal are again divided by the adaptive pixel coefficients, there by reducing the noise mixed during the channel transmission by a factor of the factor ratio.

Description:
The present invention relates to a high definition television (HDTV), and more particularly to, a noise reduction circuit for high definition video signals, wherein channel noise mixed during the data transmission is reduced in an advanced television(ATV) system which compresses the band of the high definition video signal by using the a sub-band coding method. 
     In the noise reduction circuit, after the high frequency components of the high definition video signal are divided into predetermined two-dimensional blocks, adaptive coefficients are generated according to the maximum value of each block and are multiplied by pixels to enhance the level for the channel transmission. 
     In a receiver, the transmitted level is divided by the adaptive coefficients to reduce the channel noise mixed during the channel transmission by the factor ratio. 
     Presently, many systems have been proposed for the ATV system in U.S.A. A representative method is the sub-band coding technique proposed by MIT (Massachusetts Institute of Technology) and Zenith Co., in which a video signal is divided into many sub-bands having different frequency characteristics. 
     The subbands are generally divided into low-frequency bands including a DC component and high-frequency bands, and generally the power and level width of the high-frequency components are lower than those of the low-frequency components. 
     When the band of the high definition video signal is compressed and transmitted by the sub-band coding method, a mixed signal of the high definition video signal and the noise such as the intermediate electric wave enter the receiver. In the receiver, therefore, the decoding from the transmitted data to the original data is very difficult. 
     SUMMARY OF THE INVENTION 
     The present invention has been made in consideration of this and has an object of, and providing a noise reduction circuit for high definition video signal in the ATV system employing the sub-band coding method, in which the adaptive coefficients are generated according to the maximum value of each block and are multiplied by the pixels to increase the encoded signal level for the channel transmission after dividing the high-frequency components of the high-definition video signal into the two-dimensional blocks, and in the receiver the transmitted signal is again divided by the adaptive coefficients to reduce the mixed noise by the factor ratio. 
     According to the present invention, there is provided a noise reduction circuit comprising: 
     An absolute value circuit into which a high-frequency video signal is input through an input terminal, and which outputs an absolute value of the high-frequency video signal, 
     a maximum value detecting circuit connected to the absolute value circuit, which extracts the video signal as a predetermined vertical-horizontal two-dimension block, compares the magnitudes of each pixel of the extracted block, and outputs the maximum value for each blocks, 
     a block adaptation factor generating circuit connected to the maximum value detecting circuit and is provided with the maximum value for each block, in order to output a channel peak value as a block adaptive factor if the maximum value of the block is zero or to output a channel peak value which is divided by the maximum value of the block as the block adaptive factor if the maximum value of the block is not zero and transmit it through a channel, 
     a first pixel adaptation factor generating circuit provided with the block adaptation factor, which outputs the pixel adaptive factor to be multiplied by the pixels of the block by interpolation in the horizontal direction and by taking average between lines in the vertical direction, 
     a first delay compensating circuit which delays high frequency component of pixel inputted through input terminal for a predetermined time to synchronize with the timing of the pixel adaptation factor signal, 
     a multiplier which is connected to the output terminals of pixel adaptation factor generating circuit and to the first delay compensating circuit; it and multiplies the delayed pixel signals by the pixel adaptive coefficients to amplify the level of the video signal for transmitting the amplified video signal through a channel, 
     a second pixel adaptation factor generating circuit provided to the transmitted block adaptive factor and generate the pixel adaptive coefficients by interpolation in the horizontal direction and by taking average between lines in the vertical direction, 
     a second delay compensating circuit which delays the transmitted pixel of the high frequency component video signal to be synchronized with the timing of the generated pixel adaptation factor signal from the second pixel adaptation factor generating circuit, and 
     a divider which is connected to both the output terminals of the second pixel adaptation factor generating circuit and the second delay compensating circuit, for reconstructing the high-frequency component video signal by dividing the delayed pixel by the pixel adaptive factor. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be now described in more detail with reference to the accompanying drawings, in which; 
     FIG. 1 is a noise reduction circuit for high-definition video signal according to the present invention; 
     FIG. 2 is a detailed circuit diagram of a maximum value detecting circuit in FIG. 1; 
     FIG. 3 is a detailed circuit diagram of an block adaptation factor generating circuit in FIG. 1; 
     FIG. 4 is a detailed circuit diagram of first and second pixel adaptation factor generating circuits in FIG. 1; and 
     FIG. 5 is the timing diagrams of major parts in FIG. 1. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention will now be described in more detail with reference to accompanying drawing. 
     FIG. 1 is a noise reduction circuit for high definition video signal. In an encoder 1000, an absolute value circuit 100 for receiving the high-frequency component video signal through an input terminal 101 and for providing its absolute value is connected to a maximum value detecting circuit 200 for extracting the vertical-horizontal two-dimension block data from the absolute-valued video signal and for providing the maximum value of the blocks by comparing the magnitudes of pixels in the extracted block. 
     A block adaptation factor generating circuit 300 provides a channel peak value as a block adaptation factor if the maximum value of the block is zero, while the block adaptive factor generating circuit 300 provides the channel peak value divided by the maximum value of the block as the block adaptation factor if the maximum value of the block is not zero. The output of the block adaptation factor 300 is not only provided to a pixel adaptation factor generating circuit 400 but also transmitted through the channel. 
     The pixel adaptation factor generating circuit 400 receives the block adaptation factor and then provides it by interpolation of the block factor in the horizontal direction and by taking average between lines in the vertical direction so as to multiply the pixels of each block by the pixel adaptive coefficients. 
     Also, a delay compensation circuit 500 for delaying the high-frequency component video signal to synchronize it with the timing of the pixel factor signal and the pixel adaptive factor generating circuit 400 are connected to a multiplier 600 to amplify the level of the video signal and to transmit the amplified video signal through the channel. 
     On the other hand, a decoder 2000 for decoding the transmitted video signal is composed of a pixel adaptation factor generation circuit 800, which receives the transmitted block adaptation factor and then provides the pixel adaptive coefficients in the same manner as the pixel adaptation factor generating circuit 400 in the encoder 1000, a delay compensating circuit 700, and a divider 900, which divides the delayed pixel signals of the video signal by the pixel adaptive coefficients, to reconstruct the original high frequency video signal. 
     FIG. 2 is a detailed circuit diagram of the maximum value detecting circuit 200 as shown in FIG. 1. 
     The maximum value detecting circuit 200 is composed of a block extracting circuit 20 which delays the absolute-valued video signal by 1H(H: horizontal scanning period), 2H, and 3H in the vertical direction, and also delays the 1H, 2H, and 3H delayed video signals by 1C (c:clock period), 2C, and 3C in the horizontal direction to provide 4×4 pixel data, a latch 220 which provides the 1st˜16th pixel data by a latch enable signal LE, 
     a latch controller 230 which counts the clock pulse to provide a latch enable signal for every four pixels, that is, to provide the latch enable signal LE during one horizontal scanning period, and a maximum value selecting circuit 240 which compares the 1st˜16th pixel data and selects the largest value. 
     The block extractor 210 is connected to the output terminal of the absolute value circuit 100. In the block extractor 210, three 1H delays 10, 20, and 30 delay the video signal by one horizontal scanning period, respectively. 
     Also, 1C delays 11, 21, 31, and 41 delay the 1H, 2H, and 3H delayed video signals by one clock period in the horizontal direction, respectively. Similarly, the 1C delays 12, 22, 32 and 42 are connected to the 1C delays 11, 21, 31, and 41, to delay the video signal by one clock period, respectively, and the others 13, 23, 33, and 43 are connected as well. 
     Also, the latch control circuit 230 is composed of a counter CONT1 for counting the clock signal applied through the clock input terminal 102, a line counter CONT2 for providing the pulse every horizontal scanning line period, by counting the clock signal, a counter CONT3 for counting the output of the counter CONT2, and two AND gates G1 and G2, for providing the latch enable signal LE and the output enable signal OE by the logic combination of the outputs of the counters CONT1 and CONT3, respectively. 
     In the maximum value selecting circuit 240, eight multiplexers M1˜M8 are connected to the output terminals Q0˜Q15 of the latch 220, and each multiplexer selects and provides one of two inputs, A and B, by the selecting data from a terminal S. 
     At this time, eight comparators B1˜B8 are also connected to the output terminals Q0˜Q15 of the latch 220, to provide the selecting data to each multiplexer by comparing each input pair. 
     Also, four comparators B9˜B12 are connected to the eight multiplexers M1˜M8 to provide the selecting data to four multiplexers M9˜M12 by comparing the inputs A and B provided from the multiplexers M1˜M8. 
     Similarly, two multiplexer, M13 and M14, two comparators, B13 and B14 are connected in common to the output terminals of the four multiplexers M9˜M12 and susequently, multiplexer M15 and, comparator B15 are connected to the output terminals of the two multiplexers M13 and M14. 
     FIG. 3 shows a detailed circuit diagram of the block adaptive factor generating circuit 300 shown in FIG. 1. The block adaptive factor generating circuit 300 is composed of a comparator 310, of which one input terminal A is connected to the output terminal of the maximum value detecting circuit 240 and the other terminal B is connected to the ground to compare the maximum value with zero level, a divider 320 for dividing the channel peak value applied through a channel peak input terminal 103 by the maximum value, and a multiplexer 330 for providing one of the maximum value at an input terminal A and the output of the divider 320 at another input terminal B according to the selecting data at the selecting terminal. 
     FIG. 4 shows a detailed circuit diagram of the pixel adaptive factor generating circuit 400 and 800 shown in FIG. 1. In FIG. 4, a switch 410 of which one input terminal is connected to the output terminal of the block adaptation factor generating circuit 300 and the others are connected to the ground, is connected to a low pass filter 420. 
     The switch 410 is sequentially switched by the clock signal applied through the clock input terminal 102 and then provides the block adaptation factor output every four clocks, while providing zero to the low pass filter 420 during the other clocks. 
     On the other hand, a counter CONT4 which provides the pulse every one horizontal scanning line period by counting the clock signal applied though the clock input terminal 102 is connected to another counter CONT5. Then, the counter CONT5 counts the pulse output of the counter CONT4 and provides the output signals to two input terminals of a NAND gate G3, which provides a selecting data by the logic combination. 
     Also, a multiplexer M17, of which an input terminal B is connected to the output terminal of the low pass filter 420 and the other input terminal A is connected to a half amplifier 450, provides the pixel adaptation factor signal at the terminal B through an output terminal Z during one horizontal scanning period, while providing the input signal at the terminal A, by the selecting signal at a terminal S. Then, a one-line shift register 430 delays the output of the multiplexer M17 by one horizontal scanning line period. 
     Next, a multiplier 330 provides the product of the outputs of the multiplexer M17, and both the one-line shift register and a half amplifier 450 amplifies the output of the multiplier 440 by a factor of 1/2. 
     Now the operation of the present invention is described in detail, in reference to the timing diagram as shown in FIG. 5. 
     First, when the power supply is turned on and the video signal is applied to both absolute value circuit 100 and delay compensating circuit 500, the absolute value circuit 100 changes the value of input video signal to its absolute value. 
     Subsequently, the maximum value detecting circuit 300 extracts a two-dimension block consisting of 4×4 pixels from the absolute-valued video signal by using the 1H delays 10˜30 and the 1C delays 11˜13, 21˜23, 31˜33, and 41˜42 in, order to provide the 1st˜16th pixel data. At this time, the latch 220 and the latch control circuit 230 control each block of 4×4 pixels not to be overlapped. 
     The counter CONT1 outputs a latch enable signal, as shown in FIG. 5A-(b) every, four pixels to the latch enable terminal of the latch 220, and the counter CONT3 outputs an output enable signal as shown in FIG. 5A-(c) during one of four lines. In the present invention, one block is composed of 4×4 pixels, but the block can be composed differently if necessary. 
     The latch 220 outputs the 1st˜16th pixel data to the maximum value selecting circuit 240. And the maximum value selecting circuit 240 selects the maximum value of the 1st˜16th pixel data by using the multiplexers M1˜M15 and the comparator B1˜B15 to provide it to the block adaptation factor generator 330. 
     Then, the block adaptive factor generator 300 outputs the channel peak value as the block factor, if the output value of the maximum value detecting circuit is zero, while providing the channel peak value divided by the maximum value if the output value is not zero. 
     The channel peak value represents the allowable maximum peak value of the transmission channel and is dependent on the number of bits per pixel. For example, if eight bits are used for one pixel data, the channel peak value is 127 (=27-1) since one bit is used as a sign bit. 
     Next, the block adaptive factor is applied to the pixel adaptation factor generating circuit 400 shown is FIG. 4. Then, the pixel adaptation factor generator 400 generates the pixel adaptive coefficients by interpolation. 
     That is, since the block adaptation factor signal is applied only for one line every four horizontal scanning lines, as shown in FIG. 5B-(b), the pixel adaptive factor generator 400 generates the pixel adaptive coefficients for the other three lines by using the line shift register 430 as shown in FIG. 5B-(d). 
     Thus, the variation between the pixels is not large by the interpolation in the horizontal direction and taking the line average in the vertical direction. Here, FIG. 5B-(a) represents the clock signal and FIG. 5B-(c) represents the output signal of the switch 410 of which operation is controlled by the clock signal. 
     On the other hand, since some time is delayed until the pixel adaptive coefficients are generated, the delay compensating circuit is used to synchronize the input video signal with the output signal of the pixel adaptive factor generating circuit 400. Thus, the time-compensated pixel signals are multiplied by the pixel adaptive factor signals by the multiplier 600 and are subsequently transmitted through the channel. 
     Also, when the output of the multiplier 600 is transmitted to the decoder circuit 2000, the block adaptive factor is transmitted together. In the decoder circuit 2000, then, the pixel adaptive factor generating circuit 800 which is the same as that in the encoder circuit 1000 generates the pixel adaptive coefficients again. 
     Subsequently, the pixel signals are divided by the pixel adaptive coefficients in the divider 900, thereby reconstructing the original pixel signal. At this time, the delay compensating circuit 700 compensates the delayed time for generating the pixel adaptive factor, in the encoder circuit 1000. 
     As mentioned up to now, the present invention can reduce the noise mixed during the channel transmission by a factor of the factor ratio, by dividing the high frequency components of a video signal into the two-dimension block and by generating the adaptive coefficients according to the maximum value of each block and by multiplying the adaptive coefficients to the pixel signals in the transmitting circuit, and by dividing again the transmitted signal, by the adaptive coefficients again in the receiver circuit.