Abstract:
A gain stage using switched capacitor architecture and suitable for a pipelined analog to digital converters provides for three pairs of switched capacitor banks whose use may be alternated so as to provide simultaneous sampling of two input channels for sequential gain operation without the interposition of additional circuitry in the signal chain from input to output of the gain stage.

Description:
FIELD OF THE INVENTION 
     The invention relates generally to switched capacitor gain stages, such as are used in pipelined analog digital converters and, in particular, to a gain stage providing dual input capabilities. 
     BACKGROUND OF THE INVENTION 
     Switched capacitor gain stages provide precisely defined gains determined by a ratio in values between closely matched capacitors, typically on a single integrated circuit. 
     In one type of capacitor gain stage, a pair of capacitors is charged in parallel across an input voltage and a ground reference. The capacitor terminals that are attached to the ground reference are then moved to the inverting input of an operational amplifier while one of the capacitor terminals previously attached to the input voltage is moved to the output of the amplifier and the other capacitor terminal previously attached to the input voltage is attached to a reference voltage. When the capacitors have the same value, the output of the amplifier will then be twice the input voltage plus the reference voltage, the latter which may be negative to provide for effective subtractions as well as additions. In order to increase the throughput of the gain stage, two sets of capacitor pairs may be used with one charging from the input voltage while the other is connected to the amplifier to produce an output value. 
     A rapid and precise “pipelined” analog to digital converter (AC) can be created by connecting a number of these equal capacitor gain stages in series. The first gain stage receives the voltage to be converted and outputs a voltage to the next gain stage for its input, and so forth. Each gain stage doubles the input voltage, then adds a positive voltage reference (+V ref ), a negative voltage reference (−V ref ), or zero, as determined by a comparison of the input voltage with two thresholds V h  and V 1 . Each gain stage also produces two conversion bits dependent on the thresholds process and these are combined to produce the resultant digital conversion value. 
     The operation and architecture of pipeline AC is also generally described in “A 12-bit 1-Msample/s Capacitor Error-Averaging Pipeline A/D Converter” by Bang-Sup Song, Michael F. Tempest, and Kadabar R. Lakshmikumar in the IEEE Journal of Solid-State Circuits, Vol. 23, No. 6, December 1988, pp. 1324-1333, hereby incorporated by reference. A gain stage suitable for use in such an ADC is described in U.S. Pat. No. 5,574,457 entitled: Switched Capacitor Gain Stage, issued Jun. 12, 1995, assigned to the same assignee as the present invention and hereby incorporated by reference. 
     Frequently there is a need to simultaneously convert two analog signals into their digital values, for example, in electronic systems having an “in-phase” and “quadrature” signal. Such conversions may be accomplished through the use of two ADCs but at a considerable cost and power penalty. 
     An alternative approach is to position two sample and hold circuits in front of a single ADC. The sample and hold circuits may simultaneously sample the two input values to be presented in an interleaved sequence to a single analog to digital converter for conversion. 
     A drawback to this latter approach is that it introduces additional circuitry stage between the input signal and analog converter such as may add noise or systematic errors to the digital value. Further, the buffer amplifiers, timing circuitry for the interleaving, and other circuitry required by the sample and hold circuits significantly increase the cost of the analog to digital converter. 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention provides a gain stage adapted to receive two input signals for simultaneous sampling and suitable for use with a pipelined ADC. Significantly, the gain stage of the present invention has significantly fewer parts than would be required with two sample and hold circuits and further, eliminates the introduction of additional circuitry between the input signals and the point of conversion to a digital signal because the gain stage performs both a sample and hold function and a most significant bit extraction. 
     Generally, the present invention realizes these advantages by using three sets of capacitor pairs. A first and second capacitor pair sample the two input signals while the third is connected across an amplifier. In a next clock cycle, the first capacitor pair is connected across the amplifier and then in a third clock cycle, the first and third capacitor pairs sample the dual inputs while the second capacitor pair is connected across the amplifier. In this way, simultaneous sampling of dual inputs can be obtained with no additional circuitry being introduced in the signal chain between the input signal and the final converted value. 
     Specifically, the present invention provides a switched capacitor gain stage having a first and second input and an output and including an amplifier having an output connected to the output of the gain stage, and further including a first, second and third capacitor pair. A switch network operates at a first time to switch the first capacitor pair and the second capacitor pair to receive varying voltage from the first and second inputs, respectively, and switch the third capacitor pair across the amplifier and a reference voltage to provide an amplifier output voltage equal to a gain factor times the voltage previously received on the third capacitor pair plus the reference voltage. At a second time after the first time, the switch network switches the first capacitor pair across the amplifier and a reference voltage to provide an amplifier output voltage equal to the gain factor times the voltage previously received on the first capacitor pair plus the reference voltage. At a third time after the second time, the switch network switches the first capacitor pair and the third capacitor pair to receive varying voltages from the first and second inputs, respectively, and switches the second capacitor pair across the amplifier and a reference voltage to provide an amplifier output voltage equal to the gain factor times the voltage previously received on the second capacitor pair plus the reference voltage. 
     Thus the invention provides a gain stage that may simultaneously sample two input signals for amplification without the introduction of additional circuitry between the input signals and the output of the gain stage. The cycling through of three capacitor pairs allows the same capacitors used for amplification to temporarily store input values for processing. 
     The invention may provide for simultaneous sampling of two input signals for processing by the gain stage without the duplication of all gain stage elements. By accepting a slightly lower throughput, the present invention provides simultaneous dual input sampling with only a single additional capacitor pair and associated switching circuitry over a dual phase, single channel ADC of the prior art. 
     The first, second and third capacitor pairs may be matched capacitors on a single integrated circuit. 
     Thus the invention provides for a dual input gain stage suitable for practical construction on a single integrated circuit. The design&#39;s use of standard switched capacitor techniques renders it ideal for integrated circuit implementation. 
     The present invention may be used in a pipelined dual input ADC in which a plurality of series coupled switched capacitor gain stages are used and the first switched capacitor gain stage has three switched capacitor pairs and alternate simultaneous independent sampling of the dual inputs with the first and second capacitor pairs and the first and third capacitor pairs and sequentially outputs a first output using the first capacitor pair, a second output using the second capacitor pair and a third output using the first capacitor pair and a fourth output using the third capacitor pair. 
     Thus the invention provides a dual input ADC that requires only modification of the initial gain stage for simultaneous sampling. After the first gain stage, the input values are multiplexed in time to be handled by a slightly modified dual phase ADC gain stage. 
     The foregoing and other advantages of the invention will appear from the following description. In this description, reference is made to the accompanying drawings, which form a part hereof, and in which there is shown by way of illustration, a preferred embodiment of the invention. Such embodiment and its particular objects and advantages do not define the scope of the invention, however, and reference must be made therefore to the claims for interpreting the scope of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a functional block diagram of a gain stage used in a prior art pipelined ADC; 
     FIG. 2 is a prior art block diagram showing an ADC formed of cascaded gain stages of FIG.  1  and showing the combination of output values from each gain stage to produce an output digital value; 
     FIG. 3 is a schematic diagram of a prior art circuit implementing a dual phase gain stage of FIG. 1 with two sets of switched capacitors, as may be modified by removal of the conductor of the dotted line for use in the present invention to accept two separate alternate phase input signals for later stages of a pipelined ADC per the present invention; 
     FIG. 4 is a graph plotting two phases of a clock signal against time, the clock signal suitable for activation of the two banks of switched capacitors of FIG. 3; 
     FIG. 5 is a simplified depiction of one bank of switched capacitors of FIG. 3 during a first clock phase showing connection of capacitors in parallel for receiving an input signal; 
     FIG. 6 is a figure similar to that of FIG. 5 showing connections of the capacitors during a second clock phase across an amplifier; 
     FIG. 7 a  is a schematic diagram similar to FIG. 3 showing a gain stage in accordance with the present invention having three banks of switched capacitors allowing simultaneous sampling of dual input signals; 
     FIG. 7 b  is a schematic diagram similar to FIG. 7 a  showing the addition of range comparison circuitry and a delay circuit for the timing signals of one of the dual inputs signals; 
     FIG. 8 is a figure similar to that of FIG. 4 showing the clock signals needed for the gain stage of FIG. 7 a  and showing the time multiplexed output signals; 
     FIG. 9 is a block diagram showing implementation of symmetric circuits per FIG. 7 a  for the creation of a differential pipelined ADC; 
     FIG. 10 is a chart showing the interleaving of samplings through the three banks of switched capacitors of FIG. 7 a  at different times to provide alternate channel conversions at the output of the amplifier of FIG. 7 a ; and 
     FIG. 11 is a block diagram showing the assembly of the gain stage of FIG. 7 a  together with gain stages of FIG. 3 (as modified to provide for separate I and Q inputs) for the creation of a pipelined ADC having dual input capabilities. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring now to FIG. 1, a gain stage  10 , including the necessary circuitry for production of a pipelined ADC, receives an input voltage  12  (V in ) to produce an output voltage  14  (V out ) and two conversion bits  16  (O 1  and O 0 ) used for generation of a digital value in the ADC. 
     As is understood in the prior art, gain stage  10  compares the input voltage  12  against an input range  18  spanning values between −V ref  and +V ref  where V ref  is an arbitrary reference voltage. High and low threshold values V h  and V 1  may be defined about the midpoint  20  of the range  18  where V h  can take any value between the midpoint and V ref /2 and V 1  can take any value between −V ref /2 and the midpoint. In this way, three zones  22   a ,  22   b  and  22   c  within the range  18  may be defined where  22   a  is the range between +V ref  and V h ,  22   b  is the range between V h  and V 1  and  22   c  is the range between V 1  and −V ref . 
     The gain stage  10  will treat V in  differently depending on range  22   a  through  22   c  into which it falls to produce different values of V out  and O 1  and O 0 . In range  22   a , V out  will equal two times V in  minus V ref  and O 1  will equal one and O 0  will be zero. Similarly for the range  22   b , the V out  will equal two times V in  and O 1  will equal zero and O 0  will be one. Finally for range  22   c , V out  will equal two times V in  plus V ref  and O 1  will equal zero while O 0  will equal zero. 
     Referring now to FIG. 2, a set of gain stages  10   a  through  10   d  may be assembled, for example, to produce a pipelined ADC  11  providing a conversion of four bits. Each of the gain stages  10   a-d  is connected in series so that V in  is received by gain stage  10   a  whose V out  is received as V in  for gain stage  10   b  and so forth. The conversion bits  16   a  through  16   d  of each gain stage  10 , respectively, are assembled through addition to create the output digital value  24  as follows: O 1  of output stage  10   d  is added to O 0  of output stage  10   c  to create the least significant bit of the output digital value  24 . O 1  of output stage  10   c  is added to O 0  of output stage  10   b  plus any amount carried from the previous addition for the least significant bit to create the next significant bit of the output digital value  24 . Output O 1  from gain stage  10   b  is added to output O 0  from gain stage  10   a  and added with any amount carried from the previous significant bit to create the next most significant bit of the output digital value  24 . And finally, output O 1  is added to any bit carried from the previous addition to create the most significant bit of the output digital value  24 . 
     Referring now to FIG. 3 and 4, a prior art gain stage  10  for a single input V in , sampling in two alternating clock phases (p 1  and p 2 ), employs two switched capacitor banks  28   a  and  28   b  connected via dotted line connection  26 . 
     These two switched capacitor banks  28   a  and  28   b  will operate similarly, although during different phases of a clock signal, and hence it is sufficient to describe only one switched capacitor bank  28   a  in detail. The input V in  is received by the switched capacitor banks  28   a  at a common terminal of two single-pole, single-throw switches  30   a  and  31   a  operating to close when clock signal p 1  is high Switches  30   a  and  31   a , as the other switches to be described, are all single-pole, single-throw switches and may be implemented by a complementary transistor pair of a type well known in the art to create a solid state switch. The clock signal that is high to close a given switch is shown by a notation (e.g. p 1 ) next to the switch 
     The downstream terminals of switches  30   a  and  31   a  connect to corresponding capacitors  32   a  which have their remaining terminals joined at location  34   a  to one terminal of a switch  36   a  and also to one terminal of the switch  40   a . The remaining terminal of switch  36   a  connects to ground. Switch  36   a  is closed when signal p 1  is high Conversely, the remaining terminal of switch  40  is connected to the inverting input of an operational amplifier  42  and is closed when a signal p 2  is high 
     Connected to the junction between switch  30   a  and capacitor  32   a  is one terminal of switch  44   a . Switch  44   a  is closed when signal p 2  is high, and has its remaining terminal connected to the output of the operational amplifier  42 . The junction between switch  31   a  and its capacitor  32   a  is connected to one pole of three switches  46   a ,  48   a  and  50   a . The remaining terminal of switch  46   a  connects to +V ref , the remaining terminal of switch  48   a  connects to −V ref  and the remaining terminal of switch  50   a  connects to ground. Switch  46   a  closes when a signal h 2  is high (h 2  is in phase but not identical with p 2 ). Switch  48   a  closes when a signal i 2  is high (i 2  is in phase with p 2  but not identical with p 2 ) and switch  50   a  closes when a signal m 2  is high (m 2  is in phase with p 2  but not identical with p 2 ). Generally, when p 2  is high, only one of h 2 , i 2 , and m 2  will be high as dictated by the value of V in  per the rules described above with respect to FIG.  1  and as determined by range comparison circuitry (not shown). 
     Referring now to FIG. 5, during a first phase of operation of the gain stage  10 , when p 1  is high and p 2  is low, switches  30   a ,  31   a , and  36   a  will be closed and switches  40   a ,  44   a ,  46   a ,  48   a  and  50   a  will be open resulting in the equivalent circuit of FIG. 5 in which V in  is connected simultaneously to the parallel connected capacitors  32   a  and the remaining common terminal of capacitors  32   a  is connected to ground. This will cause the charging of the capacitor  32   a  to the voltage of V in . 
     At a second phase of operation of the gain stage  10 , when p 2  is high and p 1  is low, the circuit will revert to the configuration of FIG. 6 in which switches  30   a ,  31   a  and  36   a  are open and switches  40   a ,  44   a , are closed and one of switches  46   a ,  48   a  or  50   a  are closed connecting capacitor  32   a  to one of +V ref , −V ref  or zero per the logic described with respect to FIG.  1 . The closing of switches  40   a  and  44   a  connects the common point  34   a  between capacitors  32   a  to the inverting input of the operational amplifier  42  and connecting the remaining terminal of first capacitor  32   a  to the output of the operational amplifier and connects the remaining terminal of second capacitor  32   a  to one of V ref , −V ref , or zero depending on which of switches  46   a ,  48   a  or  50   a  are closed. 
     In the situation where m 2  alone is closed, the charge on the second capacitors  32   a  is transferred to capacitor  32   a , the latter closing the feedback loop from the inverting input to the output of the operational amplifier  42 . If capacitors  32   a  are equal in value per the embodiment of the present invention for use in an ADC, this will create an output on the operation amplifier twice the voltage of V in . When either of switches  46   a  or  48   a  are closed and switch  50   a  is open, the output of the operational amplifier will be modified by the addition or subtraction of V ref  thus effecting the logic described above with respect to FIG.  1 . 
     Referring again to FIG. 4, the switched capacitor bank  28   b  is essentially identical to switched capacitor bank  28   a  with the exception that the switches  30   b ,  31   b ,  36   b ,  40   b ,  44   b ,  46   b ,  48   b , and  50   b  switch in opposite phase to switches  30   a ,  31   a ,  36   a ,  40   a ,  44   a ,  46   a ,  48   a , and  50   a  to which they otherwise correspond. By this is meant that switches of switched capacitor bank  28   a  close when p 2 , while in switched capacitor bank  28   b , they close when p 1  is high, and vice versa. Thus the switched capacitor bank  28   b  assumes the configurations of FIGS. 5 and 6 in the opposite sequence of the switched capacitor banks  28   a  allowing for the processing of two interleaved samples of V in  as is known. 
     Using the circuit of FIG. 3, V in  could be broken up so that switched capacitor bank  28   a  receives the value of I in , while switched capacitor bank  28   b  receives a value of Q in  independent of I in . In this manner, dual I and Q inputs could be accommodated by the circuit of FIG. 3 with the provision that the sampling of the inputs is staggered and out of phase. The present invention, in fact, avoids this staggering of sampling times which causes errors in many applications in which dual input ADCs are required, but uses a version related to the circuit of FIG. 3 in later stages of the pipelined where the I in  and Q in  inputs are separated. 
     Referring now to FIG. 7 a , a gain stage  10 ′ of the present invention provides for three switched capacitor banks: Switched capacitor bank  28   c , (termed “Bank A”), switched capacitor bank  28   d  (termed “Bank B”) and switched capacitor banks  28   e . Switched capacitor bank  28   c  (Bank A) and switched capacitor bank  28   d  (Bank B) both receive the input voltage Q in  while switched capacitor bank  28   e  receives the input voltage I in . Generally each of the switched capacitor banks  28   c ,  28   d , and  28   e  are of similar construction as those described above with, for example, like-numbered switches  30   c ,  31   c ,  32   c ,  40   c ,  44   c ,  46   c ,  48   c  and  50   c  for switched capacitor banks  28   c , operating similarly to their above described counterparts. The timing of the activation of the switches of these switched capacitor banks  28   c , and  28   d , and  28   e , however, differs from the timing of operation of switched capacitor banks  28   a  and  28   b  of FIG. 3, however, as will now be described. 
     Referring to FIGS. 7 a  and  8 , for the gain stage  10 ′, the signals p 1  and p 2  are augmented with signal p 2   a  having half the frequency of signal p 2  and having a high state and pulse width commensurate with every other pulse of signal p 2 . Also used is a signal p 2   b  identical to signal p 2   a  but for being out of phase by 180°, that is aligned with the pulses of signal p 2  not aligned with signal p 2   a.    
     The switches of switched capacitor banks  28   c  and  28   d  are controlled by the signals p 2   a  and p 2   b  as follows. Switches  30   c ,  31   c  and  36   c  are closed when signal p 2   a  is high whereas switches  40   c ,  44   c ,  46   c , (and selectively one of switches  46   c ,  48   c  and  50   c ) are closed when signal p 2   b  is high. This phase situation is reversed with switched capacitor banks  28   d  where switches  30   d ,  31   d  and  36   d  are closed when signal p 2   b  is high whereas switches  40   d ,  44   d ,  46   d , (and selectively one of switches  46   d ,  48   d  and  50   d ) are closed when signal p 2   b  is high Switched capacitor bank  28   e , in contrast, operates identically to switched capacitor bank  28   b  described above, with switches  30   e ,  31   e  and  36   e  closed when signal p 2  is high whereas switches  40   e ,  44   e ,  46   e , (and selectively switches  46   e ,  48   e  and  50   e ) are closed when signal p 1  is high. 
     Referring now also to FIG. 10, it will be understood that with this phase relationship during a first time t 0  (when p 1 , p 2  and p 2   a  are high), I in  and Q in  are sampled: I in  through switched capacitor bank  28   e  and Q in  through Bank A of switched capacitor bank  28   c . At the same time, a previously stored value of Q in  held on Bank B will be output by amplifier  42 . 
     The subsequent time t 1  when p 1  is high (and p 2 , p 2   a , and p 2   b  are low), the output I in  previously captured on the capacitors of switched capacitor bank  28   e  is output. 
     At time t 2 , (when p 1 , p 2  and p 2   b  are high) the values I in  and Q in  are again sampled, Q in  through Bank B of switched capacitor bank  28   d  whereas the output receives the previously sampled value of Q in  through the switched capacitor bank  28   c  of Bank A. 
     At time t 3 , I in  is again output. 
     Referring now to FIGS. 10,  7   a  and  7   b , the output of I in  is processed at times t 1  and t 3  immediately after its sampling at times t 0  and t 1  and thus the values for h 1 , l 1 , and m 1  (obtained immediately after the samplings) as processed by range comparison circuitry  66  (shown in FIG. 7 b ) can be passed directly to switches  31   e ,  46   e  and  50   e . In contrast, however, the output of Q in  are processed at times t 0  and t 2  an additional delay period after its sampling at times t −2  and t 0  and thus the values for h 2a , l 2a , and m 2a  and h 2b , l 2b , and m 2b  (obtained immediately after the sampling) as determined by range comparison circuitry  62  must be delayed. This delay is obtained by the introduction of a D-type flip flop  64  in the signal path between the range comparison circuitry  62  and the switched capacitor banks  28   c  and  28   d.    
     Referring to FIG. 8, even though the value of Q in  passes alternately between two Banks A or B, it can be seen that outputs of I in  and Q in  are interlaced and that a complete sampling occurs every clock phase of p 2 . The values of I and Q are simultaneously sampled eliminating the drawbacks to the use of the circuitry of FIG. 3 for a dual input ADC. Further, although the value of Q in  passes alternately through Bank A and Bank B, for any given sample, no additional circuitry is interposed between the input Q in  and the amplifier  42  such as may add noise or offset. 
     Referring now to FIG. 11, an ADC  11  making use of the present invention may use an initial gain stage  10 ′ according to the embodiment of FIG. 7 a  of the present invention followed by a number of gain stages  10  according to the embodiment of FIG.  3 . In the first stage, I in  and Q in  are simultaneously sampled but output in alternating fashion. In this way, the later stages may be simplified per the embodiment of FIG.  3 . Thus the additional circuitry of FIG. 7 a  is required only for the initial gain stage of an ADC  11 ′ reducing further the overall burden of circuitry over, for example, the use of completely separate ADCs. 
     Referring now to FIG. 9, the present invention may be implemented in a differential configuration by duplicating the circuitry  10 ′ in two different blocks each of which provides input to a differential amplifier  50 . Differential operation may be used to reduce common mode noise or the like. 
     Further it will be understood that the operation of the circuitry of the present invention may be operated with single ended power supplies simply by referencing each of the previously described voltages to a midpoint of the power supply range and ensuring that V in  remains between the power supply rails of the operational amplifier. 
     It is specifically intended that the present invention not be limited to the embodiments and illustrations contained herein, but that modified forms of those embodiments including portions of the embodiments and combinations of elements of different embodiments also be included as come within the scope of the following claims.