Abstract:
A shift register device includes transistor pass gates and latches connected in series and disposed along a data bit line, each latch connected to a corresponding transistor pass gate. Each transistor pass gate is controlled by a separate control signal input line that a provides a signal to the transistor pass gate connected to it. The signals are provided in a staggered time pattern beginning with a latch disposed last in succession, shifting data from one position to the next succeeding position. Each latch is capable of storing one bit of data. The shift register utilizes less silicon space while reducing the amount of power consumed during operation.

Description:
FIELD OF THE INVENTION 
     The invention pertains to shift register devices in general, and in particular, to shift register device designs employing latches in a more efficient arrangement. 
     BACKGROUND OF THE INVENTION 
     Shift registers are used in many applications in digital circuit designs. A typical prior art shift register  10  is illustrated in  FIGS. 1A and 1B .  FIG. 1A  illustrates a four bit serial shift register including four D-type flip-flops  12 ,  14 ,  16 , and  18  each with complementary latches  20  and  22 , as shown in FIG.  1 B. Each flip-flop of the shift register  10  includes a data input terminal D, a pair of clock signal input lines C A  and C B , and a data output terminal Q. The outputs Q of the flip-flops  12 ,  14 , and  16  form the data inputs D for the next or subsequent flip-flop  14 ,  16 , and  18  in the series. 
     As seen in  FIG. 1B , the transfer of data from the data input terminal D into the first latch  20  is controlled by a transistor pass gate  30 , and the transfer of data from the first latch  20  into the second latch  22  is controlled by a second transistor pass gate  32 . A pair of clock signals CLK and CLKB for the shift register  10  is physically connected to the respective pass gates  30  and  32  of each flip-flop via the clock signal input lines C A  and C B . Each flip-flop is a positive edge triggered flip-flop, which means that data is shifted from input D to output Q on the rise of the clock signal CLK and on the fall of the clock signal CLKB. 
       FIG. 2  illustrates a partial timing diagram for clock signals CLK and CLKB as applied simultaneously to each flip-flop  12 ,  14 ,  16 , and  18 . As CLK reaches a positive (rise) edge and CLKB reaches a negative (fall) edge the following data transfer occurs. Data DIN is shifted from data input terminal  21  and latched to output Q A  of flip-flop  12  (FIG.  1 ). Data A, previously stored in flip-flop  12 , is shifted and latched to output Q B  of flip-flop  14 . Data B, previously stored in flip-flop  14 , is shifted and latched to output Q C  of flip-flop  16 . Data C, previously stored in flip-flop  16  is transferred and latched to output Q D  of latch  18 . Data D, previously stored in latch  18 , is shifted out on to data output terminal  23 . On the next positive edge of CLK and negative edge of CLKB, data is shifted through to the next subsequent flip-flop. DIN, A, B, C and D represent bit data. DIN, A, B, C and D represent values that may all be the same, different or that may be various combinations of values. 
     A problem with prior shift devices, like the one just described, is that they take up much silicon space. If the area for one latch (typically 5 transistors) is represented by Y, then the amount of silicon required for a four-bit shift register having two latches per bit stored is Y(area)×2(latches)×4(bits)= 8 Y. An additional problem with some prior art registers is that much power is consumed where the clock signal input line operates to provide an input clock signal to all of the flip-flops simultaneously. 
     Therefore, it is an object of the present invention to provide a shift register device that efficiently utilizes silicon space. 
     It is a further object of the present invention to provide a shift register device that efficiently consumes power during operation. 
     SUMMARY OF THE INVENTION 
     These and other objects have been achieved by a shift register device including latches, only one per bit, that are connected in series along a data bit line. Each latch includes a transistor pass gate on its input side that is controlled via a separate control signal input line from that for the pass gates of the other latches. The pass gates are activated in a staggered time pattern, shifting data from one latch to the next, in a reverse order beginning with the last latch in the series and proceeding toward the first latch, which is loaded with a new data bit. The bits stored by each latch are read from a set of output terminals, one for each latch. 
     Each single latch is capable of storing one bit of data. The shift register device of the present invention utilizes less silicon space. For example, if the area for one latch is represented by Y, then the amount of silicon required for a four bit shift register is Y(area)×4(latches)=4Y. Furthermore, as separate control signals are applied to the series of latches in a staggered manner such that not all of the data is shifted at once, a reduced amount of power is consumed, as compared to shift registers of the prior art. 
     In one example of the present invention, the shift register includes four latches storing four bits of data total. Upon receipt of a control signal, data stored in a last latch disposed at the end of the series of latches, is replaced with data stored in a preceding latch. Upon receipt of a second control signal, the third latch in the series is loaded with a data bit shifted in from the preceding second latch. Upon receipt of a third control clock signal, data stored in a first latch is shifted into the second latch. Upon receipt of a fourth control signal, the first latch is loaded with a new bit through an input terminal. In this way, four data bits may be stored and shifted in the shift register. Data may be continuously inputted and stored data may be shifted from a preceding latch to a succeeding latch upon repeated application of staggered control signals. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a schematic diagram of a prior art shift register. 
         FIG. 1B  is a schematic diagram of a prior art flip-flop of the shift register of FIG.  1 A. 
         FIG. 2  is a prior art partial timing diagram of the shift register of FIGS.  1 A. 
         FIG. 3  is a schematic diagram of a shift register of the present invention. 
         FIG. 4  is a partial timing diagram of the shift register of FIG.  3 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     As seen in  FIG. 3 , a shift register  30  of the present invention includes latches  32   a ,  32   b ,  32   c  and  32   d  in succession and connected in series along a bit data input line  34  along which bit data is to be shifted to and from latches towards as output terminal  42 . In the example depicted in  FIG. 3 , four latches are present. However, a varying number of latches may be used if desired. Latches  32   a-d  are disposed between an input terminal  40  and output terminal  42  and are each capable of storing one bit of data. Each latch is connected to one of transistor pass gates  36   a ,  36   b ,  36   c  or  36   d  on its input side that is controlled via a separate control signal input line C 1 , C 2 , C 3  or C 4  from that of the transistor pass gates of the other latches. Thus, latches  32   a-d  are connected to control signal input lines C 1 -C 4  through the transistor pass gates. Each control signal input line is operable to provide a control signal to one of transistor pass gates  36   a-d . Each control signal, S 1 , S 2 , S 3  and S 4 , ( FIG. 4 ) is applied through the corresponding control signal input line in a staggered time pattern. In other words, control signals are applied to each transistor pass gate  36   a-d  one signal at a time. Control signals S 1 -S 4  are also applied in reverse succession as will be described below. 
     As seen in  FIGS. 3 and 4 , transistor pass gates and control signal input lines are disposed in succession beginning with transistor pass gate  36   a  and control signal input line C 1  and ending with transistor pass gate  36   d  and control signal input line C 4 . Transistor pass gate  36   d  is disposed between and adjacent to latches  32   c  and  32   d  and receives control signal S 1  via control signal input line C 4 , line C 4  being connected to transistor pass gate  36   d . Transistor pass gate  36   d , latch  32   d  and control signal input line C 4  are disposed last in succession. Control signal input line C 4  is operable to provide a first control signal S 1  to transistor pass gate  36   d . Transistor pass gate  36   c  is disposed between latches  32   c  and  32   b  and receives a control signal S 2  from control signal input line C 3 , line C 3  being connected to transistor pass gate  36   c . Transistor pass gate  36   c , latch  32   c  and control signal input line C 3  are disposed second to last in succession. Control signal input line C 3  is operable to provide a second control signal S 2  to a transistor pass gate  32   c . Transistor pass gate  36   b  is disposed between latches  32   b  and  32   a  and receives an control signal S 3  from control signal input line C 2 , line C 2  being connected to transistor pass gates  36   b . Transistor pass gate  36   b , latch  32   b  and control signal input line C 2  are disposed third to last in succession. Control signal input line C 2  is operable to provide a third control signal S 3  to a transistor pass gate  36   b . Transistor pass gate  36   a  is disposed adjacent to latch  32   a  and between latch  32   a  and input data terminal  40  and receives a control signal S 4  from control signal input line C 1 , line C 1  being connected to transistor pass gate  36   a . Transistor pass gate  36   a , latch  32   a  and control signal input line C 1  are disposed fourth to last in succession. Control signal input line C 1  is operable to provide a fourth input control signal S 4  to a transistor pass gate  32   a.    
     Upon sequential receipt of the control signals S 1 , S 2 , S 3  and S 4 , transistor pass gates  36   a-d  shift data from a preceding latch or preceding position external to the latches, such as input terminal  40 , to a succeeding latch or succeeding position external to the latches, such as output terminal  42 . Outputs of each latch  36   a-d  may be measured at locations Q 1 -Q 4  of the shift register, as discussed below with reference to FIG.  4 . 
     As seen in  FIG. 4 , control signals S 1 -S 4  are applied in a staggered time pattern to the transistor pass gates  36   a-d  to cause shifting of data DIN, A, B, C and D beginning with the last latch in the succession of latches and ending with the first latch in a succession of latches. DIN, A, B, C and D represent values of bit data that may all be the same, different or any other desired combination. The designations DIN, A, B, C and D are meant to illustrate the transfer of data and are not intended to limit the particular value of data being shifted in the shift register device  30 . The control signals S 1 -S 4  are applied at different, staggered points P 1 -P 4  along the time bar (t), thus causing data to be shifted in a staggered manner. In one example, input signal S 1  is first provided to transistor pass gate  36   d  causing data D within latch  32   d  to shift from latch  36   d , to or towards a succeeding position external to said latches, such as data output terminal  42 , and causing data C from latch  32   c  to shift into latch  32   d .  FIG. 4  indicates that the output measured at location Q 4  has changed from D to C upon application of control signal S 1 . After application of input clock signal S 1 , control signal S 2  is provided to transistor pass gate  36   c  causing data B from latch  32   b  to shift into latch  32   c .  FIG. 4  indicates that the output measured at location Q 3  has changed from C to B upon application of control signal S 2 . After application of control signal S 2 , control signal S 3  is provided to transistor pass gate  36   b  causing data A from latch  32   a  to shift into latch  32   b .  FIG. 4  indicates that the output measured at location Q 2  has changed from B to A. After application of control signal S 3 , control signal S 4  is provided to transistor pass gate  36   a  causing data DIN, at a position preceding and external to latch  32   a  such as data input terminal  40 , to shift into latch  32   a .  FIG. 4  indicates that the output measured at location Q 1  has changed from A to DIN.  FIG. 4  also indicates that input data terminal  40  has had data DIN shifted from it. 
       FIG. 4  indicates that control signal S 1  is provided to transistor pass gate  36   d , before control signal S 2  is provided to transistor pass gate  36   c , before control signal S 3  is provided to transistor pass gate  36   b  and before control signal S 4  is provided to transistor pass gate  36   a . Control signal S 2  is provided to transistor pass gate  36   c , before control signal S 3  is provided to transistor pass gate  36   b  and before control signal S 4  is provided to transistor pass gate  36   a . Control signal S 3  is provided to transistor pass gate  36   b  before input clock signal S 4  is provided to transistor pass gate  36   a . Control signal S 4  is provided to transistor pass gate  36   a  after input signals S 1 -S 3  have been provided. Application of one or more input signals S 1 -S 4  may be repeated a desired number of times. 
     As adjoining latches of the shift register device  30  are connected in series and separate clock signals are applied in a staggered manner such that not all of the data is shifted at once, a reduced amount of power is consumed as compared to shift registers of the prior art. Further as, only one latch is used per bit of data stored, the amount of area of silicon required for the shift register is reduced.