Abstract:
An apparatus and method for digitizing an analog signal and optimizing the dynamic range of the digitized signal. Dual analog-to-digital converters are preceded by respective amplifiers with different gains for receiving an analog input signal. The digital output signal from the analog-to digital converter preceded by the amplifier of higher gain is selected and stored when it is not clipped. Otherwise, the analog-to-digital converter preceded by the amplifier of lower gain is selected and its digital output signal is stored. Once digital memory is filled, an adaptive formatting program selects the most appropriate parts of the memory words to achieve maximum resolution and dynamic range in an output word size.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates in general to coded data conversion and more particularly, to analog to digital conversion. 
     For vulnerability tests where the shock loading is difficult to predict and is not always repeatable, the data acquisition procedure used for digitizing analog signals is to set the system gain low enough to allow a signal 10 times larger than expected to be recorded without clipping. Preventing clipping of the digitized signal is important since any information about peak signal is lost and the shock response spectral analysis is distorted. However, when this is done, an expected signal uses only 10% of the digitizer range, resulting in a lower signal-to-noise ratio. A worse than expected signal ({fraction (1/100)} th  of full scale) uses only 1% of the digitizer range and it has a poor signal-to-noise ratio. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of this invention to optimize the digitizing of analog signals having a large dynamic range variation. 
     This and other objects of the invention are achieved by an apparatus and a method for digitizing an analog signal and optimizing the dynamic range of the digitized signal. An analog input signal is fed to each of a pair of amplifiers with different gains and then to respective analog-to-digital converters. The digital signal from the analog-to-digital converter preceded by the amplifier of higher gain is selected and stored in a digital memory when it is not clipped. When clipping occurs, the digital signal from the analog-to-digital converter preceded by the amplifier of lower gain is selected and stored in the digital memory. Once the memory is filled, an adaptive formatting program selects the most appropriate parts of the memory words to achieve maximum resolution and dynamic range in an output word size. The adaptive reformatting provides improved dynamic range over currently available single analog-to-digital converter circuits. 
     Although designed to optimize recording of transients which typically have a high dynamic range, this technique is also applicable to testing where unexpected results are not anticipated since the low gain analog-to-digital converter provides insurance that if anything goes wrong a higher dynamic range signal will be recorded. 
     Additional advantages and features will become more apparent as the subject invention becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein: 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of an embodiment of the digitizing apparatus in accordance with the invention. 
     FIGS. 2A through 2B are a flow chart of programs to implement the invention. 
     FIG. 3 is a flow chart of a subroutine named CASE I. 
     FIG. 4 is a flow chart of a subroutine named CASE II. 
     FIG. 5 is a flow chart of a subroutine named CASE III. 
    
    
     DETAILED DESCRIPTION 
     Referring to FIG. 1, an apparatus  11  for digitizing an analog signal and optimizing the dynamic range of the digitized signal includes an input terminal  13 , a low gain amplifier  15  and a high gain amplifier  17 , each connected to the input terminal, an analog-to-digital converter  19  (indicated as ADC  1 ) connected to the output of the low gain amplifier, an analog-to-digital converter  21  (indicated as ADC  2 ) connected to the output of the high gain amplifier, and a processing means  23  connected to the outputs of both analog-to-digital converters. An exemplary system may consist, for example, of two 14 bit analog-to-digital converters preceded by two amplifiers with a gain ratio of 8. The amplifiers may be, for example, National Semiconductor model LF 353 operational amplifiers. The analog-to-digital converters may be,for example, Maxim Integrated Products Inc. model MAX 1201 analog-to-digital converters. While the processing means may take many forms, including hardware and software embodiments, conveniently it may take the form of a digital signal processor, such as, for example, a Texas Instruments model TMS320C6211 processor, having an DATA READY input connected to the DATA READY output of analog-to-digital converter ADC  2 , a CLOCK input, an ACQUIRE DATA input, and an INITIALIZE input. 
     In operation, an analog signal to be digitized is fed to the input terminal  13  and amplified simultaneously in the low gain amplifier  15  and in the high gain amplifier  17 . The analog-to-digital converter  19  (indicated as ADC  1 ) converts the low-gain-amplified signal to a low gain  14  bit digital signal, and the analog-to-digital converter  21  (indicated as ADC  2 ) converts the high-gain-amplified signal to a high gain 14 bit digital signal . The digital signal processor  23  detects whether or not the high gain digital signal is clipped. When the high gain digital signal is not clipped, the digital signal processor  23  selects and stores in its memory the high gain 14 bit digital signal. When the high gain digital signal is clipped, the digital signal processor  23  detects whether or not the low gain digital signal is greater than or equal to positive half scale or less than or equal to negative half scale, and it selects and stores in its memory the low gain 14 bit digital signal. Finally, when the memory is full, depending on the result of the detecting steps, the digital signal processor  23  adaptively reformats the stored signals to produce a 16 bit output word with maximum dynamic range. The exact format of the output word depends on the data. There are 3 cases to be considered: 
     CASE I- If ADC 2  does not clip, then a 16 bit format can be formed by sign extending the 14 bit high gain data to 16 bits. Case I uses the 14 bits from ADC 2  to produce a hybrid data format (HDF) stream with 14 bits of dynamic range. The HDF stream is shown in Table 1 in comparison with the 14 bits from ADC 2 . S stands for sign bit. SE stands for sign extension bit and b# stands for bit number. 
     
       
         
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 15 
                 14 
                 13 
                 12 
                 11 
                 10 
                 9 
                 8 
                 7 
                 6 
                 5 
                 4 
                 3 
                 2 
                 1 
                 0 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                 ADC2 
                 0 
                 0 
                 S 
                 b12 
                 b11 
                 b10 
                 b9 
                 b8 
                 b7 
                 b6 
                 b5 
                 b4 
                 b3 
                 b2 
                 b1 
                 b0 
               
               
                 HDF 
                 S 
                 SE 
                 SE 
                 b12 
                 b11 
                 b10 
                 b9 
                 b8 
                 b7 
                 b6 
                 b5 
                 b4 
                 b3 
                 b2 
                 b1 
                 b0 
               
               
                   
               
             
          
         
       
     
     CASE II- If ADC 2  clips and the output of ADC 1  is less than positive half scale or greater than negative half scale, then a 16 bit format can be formed from valid high gain words (tagged with a 0 in bit  14 ) by sign extending the 14 bit high gain data to 16 bits, and from valid low gain words (tagged with a 1 in bit  14 ) by left-shifting the entire low gain word three bits with the sign bit rotated into the most significant bit and by filling the three least significant bits with the sign complement. Bit  12  can be safely discarded as it contains no useful data since the output of ADC 1  is less than positive half scale or greater than negative half scale. Case II combines 14 bit data words from ADC 2  with  13  bit data words from ADC  1  to produce an HDF stream that has 16 bits of dynamic range. The HDF stream is shown in Table 2 in comparison with the 14 bits from ADC 2  and ADC 1 . 
     
       
         
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                 15 
                 14 
                 13 
                 12 
                 11 
                 10 
                 9 
                 8 
                 7 
                 6 
                 5 
                 4 
                 3 
                 2 
                 1 
                 0 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                 ADC2 
                 0 
                 0 
                 S 
                 b12 
                 b11 
                 b10 
                 b9 
                 b8 
                 b7 
                 b6 
                 b5 
                 b4 
                 b3 
                 b2 
                 b1 
                 b0 
               
               
                 HDF 
                 S 
                 SE 
                 SE 
                 b12 
                 b11 
                 b10 
                 b9 
                 b8 
                 b7 
                 b6 
                 b5 
                 b4 
                 b3 
                 b2 
                 b1 
                 b0 
               
               
                 ADC1 
                 0 
                 1 
                 S 
                 b12 
                 b11 
                 b10 
                 b9 
                 b8 
                 b7 
                 b6 
                 b5 
                 b4 
                 b3 
                 b2 
                 b1 
                 b0 
               
               
                 HDF 
                 S 
                 b11 
                 b10 
                 b9  
                 b8  
                 b7  
                 b6 
                 b5 
                 b4 
                 b3 
                 b2 
                 b1 
                 b0 
                 SC 
                 SC 
                 SC 
               
               
                   
               
             
          
         
       
     
     CASE III- If ADC 2  clips and the output of ADC 1  is greater than or equal to positive half scale or less than or equal to negative half scale, then a 16 bit format can be formed by using valid high gain words (tagged with a 0 in bit  14 ) and by right shifting the high gain word one bit (discarding the least significant bit) and by sign extending the 13 bit data to 16 bits, and by using valid low gain words (tagged with a 1 in bit  14 ) and by left-shifting the entire low gain word two bits with the sign bit rotated into the most significant bit and by filling the two least significant bits with the sign complement. Case III combines 13 bit data words from ADC 2  with 14 bit data words from ADC  1  to produce an HDF stream that has 16 bits of dynamic range. The HDF stream is shown in Table 3 in comparison with the 14 bits from ADC 2  and ADC 1 . 
     
       
         
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 3 
               
               
                   
                   
               
               
                   
                 15 
                 14 
                 13 
                 12 
                 11 
                 10 
                 9 
                 8 
                 7 
                 6 
                 5 
                 4 
                 3 
                 2 
                 1 
                 0 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                 ADC2 
                 0 
                 0 
                 S 
                 b12 
                 b11 
                 b10 
                 b9  
                 b8 
                 b7 
                 b6 
                 b5 
                 b4 
                 b3 
                 b2 
                 b1 
                 b0 
               
               
                 HDF 
                 S 
                 SE 
                 SE 
                 SE 
                 b12 
                 b11 
                 b10 
                 b9 
                 b8 
                 b7 
                 b6 
                 b5 
                 b4 
                 b3 
                 b2 
                 b1 
               
               
                 ADC1 
                 0 
                 1 
                 S 
                 b12 
                 b11 
                 b10 
                 b9  
                 b8 
                 b7 
                 b6 
                 b5 
                 b4 
                 b3 
                 b2 
                 b1 
                 b0 
               
               
                 HDF 
                 S 
                 b12 
                 b11 
                 b10 
                 b9  
                 b8  
                 b7  
                 b6 
                 b5 
                 b4 
                 b3 
                 b2 
                 b1 
                 b0 
                 SC 
                 SC 
               
               
                   
               
             
          
         
       
     
     FIGS. 2A through 2B are a flow chart of the programs stored in the digital signal processor  23  to implement the present invention, and FIGS. 3,  4 , and  5  are flow charts of subroutines for use in the programs. 
     Referring to FIGS. 2A through 2B, the digital signal processor  23  first executes a START program labeled at oval  101 . Block  102  is a decision block; it asks, “Is the INITIALIZE input set?” If the test is negative, the program returns to block  102  and repeats until the test is positive. If the test is positive, the program branches to block  103 . In block  103 , a CLIP FLAG is reset. In the next block  104 , a HALF SCALE FLAG is reset. Finally in block  105 , a MEMORY ADDRESS is reset, and the START program is completed. 
     The digital signal processor  23  next executes an ACQUIRE DATA program labeled at oval  106 . Block  107  is a decision block; it asks, “Is the ACQUIRE DATA input set?” If the test is negative, the program returns to block  107  and repeats until the test is positive. If the test is positive, the program branches to block  108 . Block  108  is a decision block; it asks, “Is the DATA READY input set?” If the test is negative, the program returns to block  108  and repeats until the test is positive. If the test is positive, the program branches to block  109 . In block  109 , the analog-to-digital converter ADC  2  is read. The next block  110  is a decision block; it asks, “Is the reading clipped?” If the test is negative, the program bypasses the next five blocks and branches to block  116 . In block  116 , the value is written to memory. Returning to block  110 , if the test is positive, the program branches to block  111 . In block  111 , the CLIP FLAG is set. In the next block  112 , the analog-to-digital converter ADC  1  is read. Block  113  is a decision block; it asks, “Is the ADC  1  value greater than or equal to ½full scale or less than or equal to −½full scale?” If the test is negative, the program bypasses block  114  and branches to block  115 . If the test is positive, the program branches to block  114 . In block  114 , the HALF SCALE FLAG is set. In block  115  the TAG BIT is set. In block  116 , the value is written to memory. In the next block  117 , the MEMORY ADDRESS is incremented. Block  118  is a decision block; it asks, “Is the memory full?” If the test is negative, the program returns to block  108  and repeats until it is completed. If the test is positive, the ACQUIRE DATA program is completed. 
     When the ACQUIRE DATA program is completed, the digital signal processor  23  next executes a REFORMAT DATA program labeled at oval  119 . In block  120 , the MEMORY ADDRESS is reset. The next block  121  is a decision block; it asks, “Is the CLIP FLAG set?” If the test is negative, the program calls the subroutine named CASE I. Returning to block  121 , if the test is positive, the program branches to block  122 . Block  122  is a decision block. It asks, “Is the HALF SCALE FLAG set?” If the test is negative, the program calls the subroutine named CASE II. Returning to block  122 , if the test is positive, the program calls the subroutine named CASE III. 
     Referring to FIG. 3, the subroutine named CASE I is labeled at circle  123 . In block  124 , the memory is read. In the next block  125 , bits  14  and  15  are set to the value of bit  13 . In block  126 , the word is written to memory. In block  127 , the MEMORY ADDRESS is incremented. The next block  128  is a decision block; it asks, “Is the memory full?” If the test is negative, the program returns to block  124  and repeats until the test is positive. Returning to block  128 , if the test is positive, the subroutine branches to block  129 . In block  129 , the subroutine returns to block  102  and the digital signal processor  23  repeats the START program. 
     Referring to FIG. 4, the subroutine named CASE II is labeled at circle  131 . In block  132 , the memory is read. Block  133  is a decision block; it asks, “Is the TAG BIT set?” If the test is negative, the program bypasses the next four blocks and branches to block  139  by way of block  138 . In block  138 , bits  14  and  15  are set to the value of bit  13 . In block  139 , the word is written to memory. Returning to block  133 , if the test is positive, the subroutine branches to block  134 . In block  134 , the sign bit is saved. In block  135 , the data is shifted to the left 3 bits. In block  136 , the sign bit is inserted into bit  15 . In block  137 , bits  0 ,  1 , and  2 , are set to the complement of bit  15 . Finally, in block  139 , the word is written to memory. In block  140 , the MEMORY ADDRESS is incremented. The next block  141  is a decision block; it asks, “Is the memory full?” If the test is negative, the subroutine returns to block  132  and repeats until the test is positive. Returning to block  141 , if the test is positive, the subroutine branches to block  142 . In block  142 , the subroutine returns to block  102  and the digital signal processor  23  repeats the START program. 
     Referring to FIG. 5, the subroutine named CASE III is labeled at circle  143 . In block  144 , the memory is read. Block  145  is a decision block; it asks, “Is the TAG BIT set?” If the test is negative, the program bypasses the next two blocks and branches to block  148  by way of blocks  149  and  150 . In block  149 , the data is shifted right one bit. In block  150 , bits  13 ,  14  and  15  are set to the value of bit  12 . In block  148 , the word is written in memory. Returning to block  145 , if the test is positive, the program branches to block  146 . In block  146 , the data is shifted left two bits. In block  147 , bits  0  and  1  are set to the complement of bit  15 . Finally, in block  148 , the word is written in memory. In block  151 , the MEMORY ADDRESS is incremented. The next block  152  is a decision block; it asks, “Is the memory full?” If the test is negative, the subroutine returns to block  144  and repeats until the test is positive. Returning to block  152 , if the test is positive, the subroutine branches to block  153 . In block  153 , the subroutine returns to block  102  and the digital signal processor  23  repeats the START program. 
     It is obvious that many modifications and variations of the present invention are possible in light of the above teachings. For example, the selection of a gain ratio of 8 and the choices for the output formatting are based on expected signals and-noise. Other gain ratios, of magnitude 2 raised to the nth power, where n is an integer, may also be used. In addition, other choices of output reformatting are acceptable depending on desired results. Also, three or more analog-to-digital converters could be used to extend the technique to larger dynamic ranges. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as described.