Abstract:
A vertical conduction trench FET has a plurality of trenches containing conductive polysilicon gates. The mesas between the trenches have a source diffusion region connected to a common source electrode. The trenches are spaced so that the depletion regions induced by the trench gate will overlap to pinch off conduction through the mesa to turn off the device. The gate potential is pulsed. The polysilicon in the trenches may be separated into two insulated portions. The pulses may be applied simultaneously or sequentially to the polysilicon gates.

Description:
RELATED APPLICATIONS  
       [0001]     This application claims the benefit and priority of U.S. Provisional Application No. 60/587,745, filed Jul. 14, 2004, the entire disclosure of which is incorporated by reference herein. 
     
    
     FIELD OF THE INVENTION  
       [0002]     This invention relates to field effect transistors (FETs) and more specifically to a trench type FET in which the mesas between the trenches are dynamically depleted by gate structures to turn off the device.  
       BACKGROUND OF THE INVENTION  
       [0003]     Enhancement trench type power MOSFETs are well known. Such devices employ a conventional base or channel region which is inverted by gate potential applied to polysilicon gates buried in the trenches and insulated from the trench walls by a gate oxide or other oxide layers.  
         [0004]     In the Depletion Trench MOSFET it is the accumulation region (as opposed to inversion region) that provides the device conduction as well as the bulk of the mesa.  
         [0005]     The impurity concentration of the mesa regions and the body below the trenches in such devices is relatively low in order to provide a suitable blocking voltage when the device is off, and to allow use of a low threshold gate voltage for turning the device on. This low body concentration, however, increases the device on-resistance R DSON .  
       BRIEF SUMMARY OF THE INVENTION  
       [0006]     In accordance with the invention, a buried insulated gate JFET is formed in which the body mesa and body doping level is substantially increased and the device is turned off by dynamically creating overlapping depletion regions extending from buried gates in the adjacent trenches.  
         [0007]     In accordance with the invention, termed a dynamic deep depletion FET (DDDFET or D 3  FET), spaced gates are pulsed, producing overlapping depletion regions in the mesas between gate trenches. This then permits reduced R DSON  because the dynamic mode turn off permits a higher epi concentration in the silicon base while still blocking the current along the channel.  
         [0008]     The gates may be simultaneously pulsed or alternately pulsed with voltages that allow the deep depletion to form. This device takes advantage of the known phenomenon that the depletion region at a MOS gate extends momentarily (tens of milliseconds) well beyond Wd at the threshold voltage.  
         [0009]     For example: for 2E16 cm-3 epi doping level, the depletion width at the threshold (1V) is only about 0.12 μm (due to the shielding effect of the inversion layer formed at Vt and above). This 0.12 micron depletion width is not nearly enough to block 0.5 μm channel for 0.5/0.5 pitch layout. But if pulsed with 4-10 volts it extends to over 0.5 micron, it is wide enough to block the channel and provide high blocking voltage.  
         [0010]     Other advantages of the device of the invention include: 
        Simplicity of the process integration. There are fewer layers required for this device as compared to trench MOSFET.     Higher cell density again compared to a conventional MOSFET since there is no need for the body contact.        
 
         [0013]     In Enhancement Trench MOSFET (regular Trench MOSFET that is the only MOSFET currently used in the power device industry) the mesa body is P-doped while source and drain are N+ doped. It takes gate voltage above the threshold voltage to invert (to N type) a sliver (about 200 A) of P-type body along the gate oxide to electrically connect N+ source to N+ drain. The inverted layer that is connecting Source and Drain is called the channel. The device is also called a normally “OFF” device.  
         [0014]     In the depletion trench device there is N+ source, N body or mesa and the N+ drain. So the source and the drain are already electrically connected (N+ to N to N+). In this case it is not the inverted sliver of P-doped mesa that is conducting but the whole body of mesa. So in the enhancement device the channel is the inverted sliver. In this device the whole mesa is the channel. The device is normally “ON” and it takes the threshold voltage to shut it off and provide the blocking.  
         [0015]     So in the D3 FET the whole mesa is the channel but in the Enhancement Trench FET only a sliver of mesa along the gate is the channel and the rest of the P-type mesa is called a BODY.  
         [0016]     Other possible implementations of the invention include the laterally alternately pulsed interlaced gates and vertically alternately pulsed gates when trenches are filled with two independent, electrically isolated poly layers. These layers may be stacked one on top of another.  
     
    
     BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0017]      FIG. 1  is a cross-section of a small section of a FET die constructed in accordance with the invention.  
         [0018]      FIG. 2  is a cross-section of the starting wafer for making the device of  FIG. 1  after initial oxidation and nitride deposition steps.  
         [0019]      FIG. 3  shows the wafer of  FIG. 2  after a trench mask step and the formation of a plurality of trenches into its top surface.  
         [0020]      FIG. 4  shows the wafer of  FIG. 3  after gate oxidation and polysilicon deposition steps.  
         [0021]      FIG. 5  shows the wafer of  FIG. 4  after a polysilicon mask step and polysilicon etch-back and oxidation.  
         [0022]      FIG. 6  shows the wafer of  FIG. 6  after TEOS deposition, a contact mask step and a TEOS etch and resist stip.  
         [0023]      FIG. 7  shows the wafer of  FIG. 6  after a nitride etch and an N +  implant and anneal step.  
         [0024]      FIG. 8  shows the wafer of  FIG. 7  after a metal deposition and sputter step, and metal patterning, forming the device of  FIG. 1 .  
         [0025]      FIG. 9  shows an embodiment of the invention in which each of the trenches of  FIGS. 1 and 8  contain two insulated polysilicon gates. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0026]     Referring first to  FIG. 1 , there is shown in a cross section, a small portion of a die made in accordance with the invention. The die is one of a plurality of die which are formed in a parent wafer which is singulated after processing is completed. The terms die and wafer may be used interchangeably.  
         [0027]     Thus, a wafer or die  20  of monocrystaline silicon has an N +  substrate  21  of any desired thickness, and has an N −  junction receiving region  22  which is commonly epitaxially deposited on substrate  21 .  
         [0028]     A plurality of trenches  23  (only 6 of which are shown in  FIG. 1 ) each have silicon dioxide gate oxides  24  grown on their interiors, and conductive polysilicon masses  25  fill the trenches for a portion of their height (shown as Wo) from the bottom of their trench. The trench bottoms may also contain a thicker oxide than that of the gate oxide on the trench walls. TEOS or other insulation caps  30  fill the remainder of the height of the 4 central control gate trenches  23 .  
         [0029]     The outermost trenches  23  to the extreme left and right of all 6 trenches  23  have their polysilicon fillers  25  extending upward and over oxide/nitride layers  31 / 32  as plate extensions  33 , to serve as shields and field plates. The intent of this segment of the drawing is to show how the contact to polysilicon can be made and is for illustrative purpose only. The general layout of the cells of DDDFET device is no different from any other trench device, that is, there are thousands parallel strips of trenches filled with polysilicon all connected together with one or few poly buses running across, in a comb like structure.  
         [0030]     An N +  source diffusion  40  extends across the top of layer  22  and extends over the area occupied by the central 4 trenches  23  shown (hundreds of such trenches could be present in the product.)  
         [0031]     A TEOS interlayer  41  overlies the outer polysilicon plates  33  and a source contact  50  and insulated contacts  51  are applied over the upper surface. Source contact  50  contacts the source region  40  and contacts  51  contact plates  33 .  
         [0032]     The purpose of contact  51  is to contact the poly gates to metal that is connected to a pad.  
         [0033]     A drain contact  60  is then connected to the bottom of substrate  21 .  
         [0034]     It will be noted that a buried insulated gate JFET is formed in  FIG. 1  in which the N −  body doping level in region  22  and the distance between the gate electrodes  25  in the trenches  23  are matched in such a way as to produce overlapping depletion areas, shown in dotted lines in  FIG. 1 , at a particular voltage on the gate (the blocking voltage).  
         [0035]     In accordance with the invention, the depletion column gates are pulsed either simultaneously or alternately, producing a reduced R DSON  because the dynamic mode permits a higher epi concentration in the silicon base while still blocking the voltage along the channel.  
         [0036]     The epi N− doping level in region  22  and the distance between the gate electrodes are matched in a such way as to produce overlapping depletion areas, shown in dotted lines, at a so called blocking voltage. At the gate voltages below the blocking voltage the device conducts.  
         [0037]     The device is a majority carrier device with very high bulk carrier mobility (1400 cm 2  Vsec) which helps to reduce R DSON .  
         [0038]     Further, the device has a much faster switch speed than conventional MOSFET due to the absence of recombination of minority carriers.  
         [0039]     It will be noted that the device does not have a body (buried P-type doped layer) channel (body) element and as result does not need to have it connected to the source thus allowing much higher cell density and process simplicity.  
         [0040]     Further improvements in device performance can be achieved by using a Si 2 O 4 /Si 3 N 4  sandwich gate to increase gate breakdown voltage.  
         [0041]     As shown in  FIG. 9 , the central trenches  23  may contain 2 insulated conductive polysilicon masses  25   a  and  25   b  insulated by oxide layer. These masses  25   a  and  25   b  may have a height of about 1 micron each. While shown one atop the other, they can be otherwise oriented.  
         [0042]     The device will then have much lower R DSON  because the dynamic mode allows the use of a much higher doped epi and still block the channel.  
         [0043]     More specifically, the gates are pulsed with a voltage sufficiently high that allow the Deep Depletion to form. This device takes advantage of the known phenomenon that the depletion region at a MOS gate extends momentarily (tens of milliseconds) well beyond Wd at the threshold voltage.  
         [0044]     For example: for 2E16 cm-3 epi doping level, the depletion width at the threshold (1V) is only about 0.112 μm (due to the shielding effect of the inversion layer formed at Vt and above). This 0.12 micron depletion width is not nearly enough to block 0.5 μm channel for 0.5/0.5 pitch layout. But if pulsed with 4-10 volts it extends to over 0.5 micron, it is wide enough to block the channel and provide high blocking voltage.  
         [0045]     The dynamic deep depletion FET (D 3 FET) of the invention will have a much lower R DSON  because the dynamic mode allows use of a much higher doped epi and still block the channel.  
         [0046]     The other advantages of the device of the invention include: 
        Simplicity of the process integration in that there are fewer layers required for this device as compared to trench MOSFET.     Higher cell density again compared to MOSFET since there is no need for the body contact.        
 
         [0049]     FIGS.  2  to  8  show one manufacturing process for making the device of the invention. In these Figures, the same numeral designates the same or similar elements used elsewhere in the drawings and specification.  
         [0050]      FIG. 2  shows the starting Wafer  20  with epitaxially deposited layer  22 . In a first step, a thin oxide  31 , for example a 200 Å thick oxide (non-critical) is grown on the top surface of region  22  and a Si 3  N 4  nitride layer  32 , which may have a non-critical thickness of about I 500  Å to 3000 Å, is deposited atop layer  31 .  
         [0051]      FIG. 3  shows a first mask step (the trench mask), in which a photo mask (not shown) is formed atop layer  32  and is conventional processed to open windows. A trench etch, which may be as deep as desired, for example 1.5 to 2.5 microns deep, preferably 2.5 microns, is then carried out to define trenches  23 . The photoresist is then stripped. The trenches may be cellular or parallel strips.  
         [0052]     Thereafter, and as shown in  FIG. 4 , a gate oxide  23  is grown in the trenches to a thickness of about 350 Å to 500 Å preferably about 400 Å. Conductive polysilicon is then deposited atop the wafer surface to a thickness of about 7000 Å and into trenches  23 , forming polysilicon fillers  25 , and is conventionally densified.  
         [0053]     In the next mask step, shown in  FIG. 5 , a mask (not shown) is formed atop the wafer and is processed to open windows to the polysilicon and a polysilicon plasma etch, etches the polysilicon back as shown, reducing the height of the polysilicon  25  in the trenches and defining plates  33 .  
         [0054]     Thereafter, the polysilicon is exposed to an oxidation step, growing an oxide of 200 Å to 400 Å thick (not shown).  
         [0055]     As shown in  FIG. 6 , a layer of TEOS or LTO 5000 Å to 9000 Å thick (preferably 9000 Å of TEOS) is deposited atop the wafer, and the next photomask process (a contact mask) is carried out to etch all TEOS except region  41  from the wafer surface. The photo resist is then stripped.  
         [0056]     In the next process step, and as shown in  FIG. 7 , the nitride  32  which is exposed in the contact mask step of  FIG. 6  is removed by a wet etch. An N +  implant step is then carried out to form a source region. This implant may be As at a dose of 5E15 at 120 kV. The implant is then annealed at 920° C. to 950° C., forming N +  source region  40 .  
         [0057]     Thereafter, and a shown in  FIG. 8 , a preclean (oxide etch) step removes oxide  31  and prepares the wafer surface for a metal sputter and metal patterning step, forming electrodes  50  and  51 .  
         [0058]     A bottom drain electrode  60  is then conventionally formed.  
         [0059]     The same basic process is used for the embodiment of the invention shown in  FIG. 9 , with appropriate modification, to form the polysilicon gates  25   a  and  25   b  which may be alternately pulsed. Thus, the trench depth for trenches  23  is preferably 2.5 microns; the gate oxide  24  is about 700 Å thick; there will be a first poly deposition and etch back to form poly regions  25   a  and a poly oxidation to form oxide  24   a ; a second poly deposition and etch back to form poly regions  25   b ; and a second and thin polyoxidation (200 Å). The process then continues as in  FIGS. 6, 7  and  8 .  
         [0060]     Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein.