Abstract:
A copper-diffusion plug  21  is provided within a pore in dielectric layer over a copper signal line. By positioning the plug below a chalcogenide region, the plug is effective to block copper diffusion upwardly into the pore and into the chalcogenide region and thus to avoid adversely affecting the electrical characteristics of the chalcogenide region.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the benefit under 35 U.S.C. § 119(a) of European Patent Application No. 07425437.6, filed Jul. 17, 2007, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The present invention relates generally to phase change memories that use chalcogenide materials. 
         [0004]    2. Description of the Related Art 
         [0005]    Phase change memory devices use phase change materials, i.e., materials that may be electrically switched between a generally amorphous and a generally crystalline state, for electronic memory application. One type of memory element utilizes a phase change material that is electrically switched between a structural state of generally amorphous and generally crystalline local order or between different detectable states of local order across the entire spectrum between completely amorphous and completely crystalline states. The state of the phase change materials is also non-volatile in that, when set in either a crystalline, semi-crystalline, amorphous, or semi-amorphous state representing a resistance value, that value is retained until changed by another programming event, as that value represents a phase or physical state of the material (e.g., crystalline or amorphous). The state is unaffected by removing electrical power. 
         [0006]    Thus, the use of phase-change storage elements has already been proposed in memory arrays formed by a plurality of memory cells arranged in rows and columns. In order to prevent the memory cells from being affected by noise caused by adjacent memory cells, generally each memory cell comprises a phase-change storage element and a selection element (such as an MOS transistor or a diode), coupled to the phase-change storage element. 
         [0007]    A phase-change storage element comprises a resistive element (also called a heater) and a programmable element made of a chalcogenide, also called memory element. Generally, the resistive element and the programmable element are formed by physical stacking of layers including an ovonic unified memory (OUM). 
         [0008]    The memory cells are addressed through metal lines or connections of copper, forming row and column lines. Therefore, when the cells are made using the OUM technology, their manufacturing should be compatible with copper backend step. That is, migration of copper into the chalcogenide layers forming the programmable elements should be prevented in order not to compromise the electrical characteristics of the memory cell. 
       BRIEF SUMMARY 
       [0009]    Embodiments include a phase change memory device and the manufacturing process thereof that are compatible with copper. 
         [0010]    There are provided a method of manufacturing a copper compatible chalcogenide phase change memory and a phase change memory element, as defined respectively in claims  1  and  12 . 
         [0011]    In accordance with one embodiment, the chalcogenide that forms the memory element is isolated from the copper used for interconnects. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0012]    For the understanding of the present invention, a preferred embodiment is now described, purely as a non-limitative example, with reference to the enclosed drawings, wherein: 
           [0013]      FIG. 1  is an enlarged, cross-sectional view of one embodiment of the present invention; 
           [0014]      FIGS. 2-10  are enlarged, cross-sectional view of the present memory element at subsequent stages of manufacturing in accordance with one embodiment; 
           [0015]      FIG. 11  is an enlarged, cross-sectional view of another embodiment of the present invention; and 
           [0016]      FIG. 12  is a system depiction in accordance with one embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION  
       [0017]      FIG. 1  shows a phase-change storage element  10  including a memory element of a chalcogenide material. The phase-change storage element  10  is connected to a selection device such as an ovonic threshold switch, in a per se known manner, not shown in the drawings, to form a memory cell. Furthermore, the memory cells are arranged in row and column, to form a memory array of a memory device. 
         [0018]    In  FIG. 1 , a substrate  12  of a dielectric material, such as oxide, has a copper line  16  formed therein in a damascene process. The copper line  16  forms a row line and is separated from the substrate  12  by a seed layer  14 , which may be any conventional copper seed layer made up of one or more elements. 
         [0019]    A first dielectric level  18 ,  20  extends over the substrate  12 . The dielectric level  18 ,  20  may comprise a nitride layer  18  covered by an oxide layer  20 . However, other dielectric materials may be utilized. The dielectric layer  18 ,  20  has a pore extending through it, aligned with the copper line  16 . A plug  21  made up of multiple layers of metal is formed in the pore. 
         [0020]    For example, in one embodiment, the plug  21  comprises a first metal layer  22  which is U-shaped and may be formed of tantalum. A second metal layer  24  extends on top of the first metal layer  22 , is also U-shaped and may be formed of tantalum nitride. A center region  26  of the plug  21  may be formed of titanium silicon nitride. The plug  21  reduces copper migration from the copper line  16  into the overlying chalcogenide. 
         [0021]    A second dielectric level  28 ,  30  extends on top of the first dielectric level  18 ,  20 . The second dielectric level  28 ,  30  may include one or more layers. For example, in the embodiment of  FIG. 1 , a nitride layer  28  is covered by an oxide layer  30 . The second dielectric level  28 ,  30  has an opening extending through it and aligned with the pore. The opening accommodates a pair of spacers  32  and  34 . However, more or fewer spacers may be used. A heater  38 , e.g., of titanium silicon nitride, and a memory element  36  of chalcogenide material, e.g., of GeSbTe (GST), extend inside the spacers  32 ,  34 , within the opening defined by the second dielectric level. The memory element  36  extends over the heater  38 , here having a lance shape. 
         [0022]    Finally, a top electrode  40  extends over the opening, is aligned and in contact with the memory element  36 . 
         [0023]    The top electrode  40  is patterned with a lithographic etch step and covered with a nitride encapsulation layer, not shown. Subsequently, an oxide layer may be deposited and polished. Then trenches are patterned; subsequently a seed layer and copper are deposited in the trenches to form column lines (not shown). 
         [0024]    The plug  21  is effective to reduce migration of copper from the copper line  16  upwardly to the overlying memory element  26  of chalcogenide material. 
         [0025]    The memory cell  10  of  FIG. 1  may be manufactured as shown in  FIGS. 2-10 . 
         [0026]    The fabrication sequence begins, as shown in  FIG. 2 , by forming a damascene structure in the first dielectric level  12 . In detail, the first dielectric level  12  is etched to form the first pore  13 , then the seed layer  14  is deposited. A copper layer  16  is then blanket deposited over the seed layer  14 . Any conventional technique for the deposition or formation of the copper layer  16  may be utilized, including electroplating, electroless plating, or sputtering. Thereafter, the copper layer  16  and the seed layer  14  are planarized,  FIG. 3 . 
         [0027]    Then the first dielectric level  18 ,  20  is formed over the substrate  12 . The first dielectric level  18 ,  20  includes the nitride layer  18 , covered by the oxide layer  20  of greater thickness, as shown in  FIG. 3 . 
         [0028]    Referring to  FIG. 4 , a second pore  19  is formed through the first dielectric level  18 ,  20  and the second pore is filled with the plug  21 . 
         [0029]    Here, the plug is made up of three different materials, including a first metal layer  22  of tantalum, a second metal layer  24  of tantalum nitride, and a third metal layer  26  of titanium silicon nitride. The tantalum nitride and tantalum are preferably not included within the upper portion that contacts the subsequently deposited chalcogenide because tantalum diffusion into the chalcogenide may reduce the heater resistance, which could compromise the cell electrical behavior. 
         [0030]    Then, the structure is planarized to achieve the planar structure shown in  FIG. 5 . Extensive oxide over-polish may be used to reduce underlying copper row topology. This may be done to avoid dished areas which can trap chalcogenide material in the subsequent chalcogenide chemical mechanical planarization step. 
         [0031]    After planarization, the nitride layer  28  and the oxide layer  30  are deposited and patterned. 
         [0032]    Then, referring to  FIG. 6 , the opening is formed through the second dielectric level  28 ,  30  and a dual spacer layer  32 ′,  34 ′ is formed. The use of a dual spacer layer  32 ′,  34 ′ reduces the diameter of the heater  38  and minimizes the heater seam. In detail, a first spacer layer  32 ′ is deposited to cover the walls of the opening and is anisotropically etched to remove it from the bottom of the opening and over the second dielectric layer  28 ,  30 . Thereby the spacer  32  shown in  FIG. 7  is formed from the first spacer layer  32 ′. Then, the second spacer layer  34  is deposited and, likewise, anisotropically etched to remove it from the bottom of the opening and over the second dielectric layer  28 ,  30 . Thereby the dual spacers structure  32 ,  34  shown in  FIG. 8  is obtained. 
         [0033]    A heater layer  38 , e.g., of titanium silicon nitride, is subsequently deposited into the resulting pore, as shown in  FIG. 9 . Then, the heater layer  38  is etched back to reduce its vertical height. The heater layer  38  may be etched using a dip back or wet or dry etch back. This etching back of the heater  38  leaves a recess wherein a chalcogenide layer  36 ′ is deposited, as shown in  FIG. 9 . 
         [0034]    Then the chalcogenide layer  36 ′ is polished back in a chemical-mechanical planarization step, thus forming the memory element  36  of  FIG. 10 . Thereafter, the top electrode  40  is deposited, patterned, and etched to create the structure shown in  FIG. 1 . 
         [0035]    In accordance with another embodiment of the present invention, shown in  FIG. 11 , the plug  21  is only formed by a metal region, e.g., of TiSiN. To this end, after planarizing the plug  26 , the latter is be dipped back partially, creating an opening at the upper end of that pore. Then, the spacers  32  and  34  are formed, as described above, and the heater  38  and the memory element  36  are formed thereover, still within the same pore  19  as the plug  21 . As a result, a lance structure that includes the heater  38  and the memory element  36  is self-aligned to the plug  21 . 
         [0036]    In other embodiments, the heater  38  may be totally omitted or the plug  21  may be formed by a multilayer of different metal layers, analogously to  FIG. 1 . 
         [0037]    Programming of the memory element  36  to alter the state or phase of the material may be accomplished by applying voltage potentials to the copper line  16 , formed on substrate  12 , and top electrode  40 , thereby generating a voltage potential across the phase-change storage element  10 . When the voltage potential is greater than the threshold voltage of the memory element  36 , then an electrical current may flow through the memory element  36 , and results in heating of the memory element  36  by the heater  38 . 
         [0038]    This heating may alter the memory state or phase of the memory element  36 . Altering the phase or state of the memory element  36  alters the electrical characteristic of the chalcogenide material, e.g., the resistance of the material. 
         [0039]    In the “reset” state, memory material is in an amorphous or semi-amorphous state and in the “set” state, memory material is in a crystalline or semi-crystalline state. Both “reset” and “set” states can exist without any energy (electrical, optical, mechanical) applied to bistable chalcogenide. The resistance of memory material in the amorphous or semi-amorphous state is greater than the resistance of memory material in the crystalline or semi-crystalline state. It is to be appreciated that the association of reset and set with amorphous and crystalline states, respectively, is a convention and that at least an opposite convention may be adopted. 
         [0040]    Using electrical current, memory material may be heated to a relatively higher temperature to amorphosize memory material and “reset” memory material (e.g., program memory material to a logic “0” value). Heating the volume of memory material to a relatively lower crystallization temperature crystallizes memory material and “set” memory material (e.g., program memory material to a logic “1” value). Various resistances of memory material may be achieved to store information by varying the amount of current flow and duration through the volume of memory material. 
         [0041]    Turning to  FIG. 12 , a portion of a system  500  in accordance with an embodiment is described. System  500  may be used in wireless or mobile devices such as, for example, a personal digital assistant (PDA), a laptop or portable computer with wireless capability, a web tablet, a wireless telephone, a pager, an instant messaging device, a digital music player, a digital camera, or other devices that may be adapted to transmit and/or receive information wirelessly. System  500  may be used in any of the following systems: a wireless local area network (WLAN) system, a wireless personal area network (WPAN) system, a cellular network, although the scope of the present invention is not limited in this respect. 
         [0042]    System  500  includes a controller  510 , an input/output (I/O) device  520  (e.g., a keypad, display), static random access memory (SRAM)  560 , a memory  530 , and a wireless interface  540  coupled to each other via a bus  550 . A battery  580  is used in some embodiments. 
         [0043]    Controller  510  may comprise, for example, one or more microprocessors, digital signal processors, microcontrollers, or the like. Memory  530  may be used to store messages transmitted to or by system  500 . Memory  530  may also optionally be used to store instructions that are executed by controller  510  during the operation of system  500 , and may be used to store user data. Memory  530  may be provided by one or more different types of memory. For example, memory  530  may comprise any type of random access memory, a volatile memory, a non-volatile memory such as a flash memory, besides of memory device having the phase change storage element  10  discussed herein. 
         [0044]    I/O device  520  may be used by a user to generate a message. System  500  may use wireless interface  540  to transmit and receive messages to and from a wireless communication network with a radio frequency (RF) signal. Examples of wireless interface  540  include an antenna or a wireless transceiver, although the scope of the present invention is not limited in this respect. 
         [0045]    The process as described herein is completely compatible with conventional copper interconnect lines, thereby allowing stackable phase change memory array layers. Also, the problems associated with dot patterning of the chalcogenide material may be reduced. 
         [0046]    Finally, it is clear that numerous variations and modifications may be made to the phase change memory element and process described and illustrated herein, all falling within the scope of the invention. For example, the process may dispense of the steps for forming the heater, creating a heaterless cell. 
         [0047]    The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.