Abstract:
A cacade connection of a buried channel CCD clocked with clocking signals of a few volts and a floating-diffusion electrometer operated at voltages no larger than those few volts. Undesirable flow back of charge into the CCD from the electrometer is forestalled by applying to the last CCD charge transfer stage a clocking signal voltage developed by doubling the few-volt clocking signals applied to the earlier charge transfer stages of the CCD.

Description:
The invention relates to floating-diffusion charge sensing circuitry for converting charge packets from a buried-channel charge-coupled device (CCD) to voltage samples. 
     BACKGROUND OF THE INVENTION 
     A problem encountered in the design of buried-channel CCD&#39;s to operate with 0-5 volt clock signals is the design of an output stage which can also be operated from the standard 5-volt power supply, so one can avoid the need for a high voltage supply. The problem arises due to the offset between in-channel potentials in the buried-channel and the gate potentials applied to the gate electrodes of these devices to induce these in-channel potentials. Consider a fabrication process using n-type charge transfer channels buried in a p-type silicon substrate. Two-phase clocking is used with each two-phase gate electrode structure consisting of a first-polysilicon-layer gate electrode preceded by a second-polysilicon-layer gate electrode receptive of the same gate electrode potential. This induces a two-step staircase potential profile under each two-phase gate electrode structure that facilitates charge transfer only in a forward direction. The in-channel potentials under the first-polysilicon-layer gate electrodes tend to be five or six volts more positive than the gate electrode potentials inducing them. If one uses 0-5 volt clock voltages on the gate electrodes of the buried-channel CCD, and follows the CCD with a floating-diffusion electrometer in which the floating diffusion is periodically reset to 5 volts, signal charge that has been transferred under the floating diffusion will tend to flow back under that gate electrode, as the clocking voltage applied to the first-polysilicon-layer gate electrode immediately preceding the floating diffusion goes positive. This back flow of charge causes a non-linear reduction in the signal voltage developed on the floating diffusion, which effect is undesirable. 
     Deriving higher reset drain voltages from the 5 volt supply, using voltage-doubling or voltage-tripling techniques, is an unattractive solution to this problem. If the reset drain voltage is increased, the drain voltages on the field effect transistor used in the electrometer and the source follower thereafter have to be increased also. The current demands of the field effect transistors require capacitor sizes in the doubler or tripler that are, practically speaking, too large to be integrated on the same semiconductor substrate as the burried channel CCD. 
     SUMMARY OF THE INVENTION 
     The buried channel CCD proceding a floating-diffusion electrometer is operated, in accordance with the invention, by applying a doubled clock voltage to a two-phase gate electrode structure over an extension of the buried channel in which the floating diffusion is disposed. A voltage doubler is, in a preferred embodiment of the invention, constructed on the same semiconductive substrate as the buried-channel CCD, using field effect transistors with channels induced in the same type of semiconductor material as used to form the buried channel CCD. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a schematic diagram of the buried-channel CCD and floating-diffusion electrometer as operated in accordance with the invention. 
     FIG. 2 is a schematic diagram of the voltage doubler used to generate the doubled clock voltage applied in the invention to the two-phase gate electrode structure preceding the floating diffusion of the electrometer. 
     FIG. 3 is a timing diagram of clocking voltages applied to the FIG. 2 voltage doubler. 
     FIG. 4 shows an artificial-perspective view of a preferred capacitor structure for use in the FIG. 2 voltage doubler, cut away to reveal the profile structure. 
     FIG. 5 is a schematic representation of the FIG. 4 structure. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 top shows (in the conventionally stylized form) the final portions of a buried channel CCD. The n-type buried channel 10 is beneath the surface of a p-type silicon substrate. First-polysilicon-layer gate electrodes 11, 12, 13 overlying the buried channel are shown as horizontal straight lines, and second-polysilicon-layer gate electrodes 14, 15, 16, 17 and 18 overlying the buried channel are shown as horizontal straight lines bent up at their ends. Each of a number of two-phase gate electrode structures consists of a second-polysilicon-layer gate electrode followed by a first-polysilicon-gate electrode, both of which gate electrodes receive the same gate potential. Two phases φ A  and φ A  of clocking voltage switching from zero to five volts in anti-phase are used, being applied in alternate sequence to a successive two-phase gate electrode structures crossing the buried channel 10 (only the last two two-phase gate electrode structures of this succession being explicitly shown in FIG. 1). The last in this succession of two-phase gate electrode structures (consisting of gate electrode 15, 12) has φ A  applied to it. Buried channel 10, then, has an extension to the right in which portions of the charge sensing output circuitry lie. 
     A subsequent two-phase gate electrode structure (consisting of gate electrodes 16, 13) is then receptive of the potential φ TR  generated from φ A  by voltage doubling. φ TR  has a positive excursion substantially the same +5 volts as φ A  has. φ TR  has a negative excursion to -4 volts after φ A  falls to zero, which is achieved through the voltage doubling process. This feature characterizes the invention. 
     A second-polysilicon-layer d-c gate electrode 17 follows. It is most convenient to apply substrate potential GND, or ground, to gate electrode 17. This can be done because φ TR  has a sufficiently negative excursion to transfer charge over the grounded d-c gate electrode. Substrate potential is the zero volts reference from which the clocking voltages mentioned in this specification are measured. 
     A floating diffusion 19, after the d-c gate electrode, is ohmically contacted and connected to the gate electrode of a field effect transistor Q2. Voltage applied to the gate electrode of Q2 includes an n-type channel between n+ source and drain diffusions. Q2 is operated as an electrometer, being connected as a source follower with drain connection to direct +5 V supply voltage and with source connection to ground. This source connection is shown as being through the conduction channel of a field effect transistor Q3 pulsed into conduction by φ A  applied to its gate electrode going to +5 volts. A reset drain 20 is located at the end of the buried channel extension and is ohmically contacted for application of a direct +5 V reset drain potential. A reset gate electrode 18 between floating diffusion 19 and drain diffusion 20 receives φ A  as reset pulses, to clamp floating diffusion to the +5 V reset drain potential when φ A  goes positive; this dc-restores signal at the gate of electrometer transistor Q2. 
     FIG. 2 shows a preferred voltage doubler configuration for generating φ TR . In addition to φ A  clocking voltage, two further clocking voltages φ B  and φ C  are used. The characteristics and relative timing of clocking voltages φ A , φ A  φ B  and φ C  are shown in the FIG. 3 timing diagram. Operation of the voltage doubler is most easily understood by referring to both FIGS. 2 and 3. In FIG. 3 the transitions in φ A  are delayed from those of φ A . This is attributable to φ A  being generated at the drain to drain connection of an n-type field effect transistor and a p-type field effect transistor connected gate to gate, to receive φ A  and connected at their sources to receive 0 volts and +5 volts, respectively. The n-type and p-type field effect transistors in this logic inverter connection are not explicitly shown in the drawing. 
     The FIG. 2 voltage doubler uses two p-channel field effect transistors, Q4 and Q5. Voltages applied to their gate electrodes induce p-channels between p+ source drain diffusions in the n-well(s) in which Q4 and Q5 are disposed. The n-well(s) are connected to +5 volt potential, so voltage swings in the operation of Q4 and Q5 may be substantially downward from +5 volt potential - even negative with respect to p-type substrate ground. The potential at the gate electrode of Q4 is level-shifted from φ B  by capacitor C2 and diode-connected Q5 to be about +1.5 volts when φ B  is +5 volts and to be about -3 volts when φ B  is at zero volts. That is, positive excursions of φ B  drive diode-connected Q5 into conduction, to clamp the gate electrode of Q4 to Q5 gate-to-source threshold voltage (+1.5 volts) above ground. 
     At time t 1 , when φ A  is at +5 volts, φ TR  is clamped to that +5 volts by conduction of Q4 channel. That is, the -3 volts on the gate electrode of Q4 acting against a +5 volt &#34;source&#34; potential φ A  causes Q4 to conduct, to bring the &#34;drain&#34; potential φ TR  to the +5 volt &#34;source&#34; potential. 
     At time t 2 , φ A  goes to zero volts, becoming the &#34;drain&#34; potential of Q4, with φ TR  becoming the &#34;source&#34; potential of Q4. φ B  remains zero volts, maintaining the -3 volt gate potential on Q4; therefore Q4 remains conductive to pull its &#34;drain&#34; potential φ TR  to zero volts. φ C  remains at +5 volts, so C 1  is charged to place five volts between its plates. 
     At time t 3 , φ B  goes to +5 volts, and the gate potential of Q4 goes to the +1.5 volts source-to-gate threshold voltage of Q5. This renders Q4 channel nonconductive, both ends thereof being negative respective to its gate electrode. 
     At time t 4 , φ C  goes to zero volts, and charge on C1 supporting a five volt potential between its plates forces φ TR  towards -5 volts. If C1 is sufficiently large in capacitance compared to the capacitance to substrate of gate electrodes 16 and 18 (of FIG. 1), φ TR  will go a substantial portion (e.g., -4 volts) of the -5 volt excursion that is possible. 
     At time t 5 , φ A  returns to +5 volts and is the &#34;source&#34; voltage for rendering Q4 channel conductive. This completes the cycle of operation, which then recurs. 
     FIG. 4 shows a preferred form for the capacitors C1 and C2 formed by a parallel combination. The p substrate 30 has a portion of its thickness removed, and vertical dimensions in the profile section are exaggerated. A PMOS structure is formed in an n-well 31 diffused into the top surface of substrate 30 by diffusing a p+ drain-source diffusion 32 into n-well 31 through an opening in the thick oxide 33 and by forming a first-polysilicon-layer gate electrode structure 34 over a portion of n-well 31 covered by thin oxide. Gate electrode structure 34 is ohmically contacted to aluminum bus 35 connecting to a first plate, 36, of the FIG. 4 capacitor structure. Gate electrode structure 34 is covered by a thin oxide layer, except where ohmically contacted; and a second-polysilicon-layer gate electrode structure 37 is disposed on that thin oxide layer. Gate electrode 37 and p+ diffusion 32 are ohmically contacted to aluminum bus 38 connecting to a second plate, 39, of the FIG. 4 capacitor structure. An n+ diffusion 40 in n-well 31 is ohmically contacted to aluminum bus 41, and bus 41 is connected to the most positive CCD voltage, +5 volts. 
     Minor variants are possible in this structure, which parallels a PMOS capacitor with an overlying capacitor formed between first and second polysilicon electrodes. FIG. 5 shows a schematic representative of these structures. 
     The two-phase gate electrode structure means comprising a second-polysilicon-layer gate electrode followed by a first-polysilicon-layer gate electrode electrically connected thereto can, as known, be replaced with a single gate electrode structure. Charge transfer directionability is then achieved by differential doping along the length of the gate in the channel, or by varying the thickness of the oxide under the single gate electrode structure. Such modifications are possible to provide other embodiments of the invention.