Abstract:
An all-digital frequency synthesizing system that will eliminate spurious frequencies that degrade the overall performance of the generation of a binary waveform. The frequency synthesizing system has a count series retention table that contains a series of count integers that are selected by a count signal that chooses which series of the integers are to be linked to a periodic reference counter. The periodic reference counter will count a number of periods of a periodic reference frequency and when the counter has reached the number of counts that is equal to the number of the count integer, the periodic output signal will be toggled from logic level to another logic level. A new periodic output signal period can be chosen by selecting a new series of count integers in the count retention table. A count compiler will create the series of count integers retained in the count retention table. The series of count integers will be disbursed in a manner to eliminate spurious frequencies from the periodic output signal.

Description:
RELATED PATENT 
     This invention is related to U.S. Pat. No. 5,705,945 (Wee) filed Jul. 22, 1996, issued Jan. 6, 1998, and assigned to the same assignee as the present invention. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to frequency synthesizers and in particular to an all-digital frequency synthesizer and especially to techniques used to create a lower frequency clock from a high frequency clock. 
     2. Description of Related Art 
     It is well known in the art that a multiple number of frequencies can be generated from a single source. These techniques may be either analog or digital and may have output signals that are either analog sine waves or purely digital pulse trains. 
     A typical application for a frequency synthesizer is a phase locked loop. In a phase locked loop the output of frequency synthesizer is compared to a reference signal. An error signal that represents the difference in the phase and frequency of the output of the frequency synthesizer and the reference signal are used to vary the frequency of the frequency synthesizer. The error signal is passed through a loop filter to eliminate any response to unwanted transient signals. As the error signal approaches zero, the phase locked loop is said to be locked. 
     A digital phase locked loop originally contained a binary reference signal and a binary output signal with an analog frequency synthesizer, loop filter and comparator. As digital circuits have improved in performance, the components may now be implemented in digital circuitry or a software program on a microcomputer. 
     FIG. 1 shows a block diagram of an all digital phase locked loop as described in Phase Locked Loops: Theory, Design, and Application by Best, McGraw-Hill Inc. 1993. The phase detector compares the output u 2  of the digital control oscillator DCO with the digital reference signal u 1 . The output of the phase detector is connected to the DN/UP input of the counter, which forms the loop filter. The K clock is an input to the K counter that is frequency that is a frequency that is a factor M times the desired output frequency F o  of the digital controlled oscillator DCO. The K Modulus Control sets the number at which the K counter will have carry signal. 
     The DN/UP input to the K counter causes the K counter to count up to the value of the K Modulus if the DN/UP input has a level to activate the up counting. The DN/UP input causes the K counter to count down to zero if the DN/UP input has a level to activate the down counting. If the K counter exceeds the value of the K Modulus, the carry output is activated. If the K counter is decremented to less than zero, the borrow output is activated. 
     If the signals u 1  and u 2  are of identical frequency and phase, the output of the phase detector will be a square wave. This will cause the K counter to count up for the first level of the square wave and to count down for the second level of the square wave. As long as the DN/UP input signal is a balance square wave, neither the carry or the borrow outputs will be triggered. If the signals u 1  and u 2  become out of phase and of unequal frequency, the period of the signal at the DN/UP input will not have equal period at the first level versus the second level and there will eventually be either a carry or a borrow signal. 
     The digital control oscillator DCO has and increment/decrement counter (ID counter). The ID clock input of the ID counter is a frequency that is a fraction of two times a factor N times the frequency F o  of the output signal u 2 . The output ID out  will be a frequency that is one half of the input ID clock. 
     The carry output of the Loop Filter is connected to the increment input INC of the ID counter and the borrow output of the Loop Filter is connected to the decrement input DEC of the ID counter. If the carry signal is activated, a single pulse is added to the ID counter output signal ID out  and conversely if the borrow signal is activated, a single pulse is subtracted from the ID counter output ID out . 
     The ID counter output ID out  is connected tot he input CP of the ÷N counter. The N control determines the factor of N that the input CP is divided by to form the frequency F o  of the output u 2 . 
     The variance of the phase and frequency of the output u 2  from the desired frequency is called jitter. As the phase detector compares the reference signal u 1  to the output signal u 2 , any difference in frequency will be a function of the weighted number of carry pulses from the K counter versus the number of borrow pulses. The size of the error maybe on the order of the pulse width of the two signals u 1  and u 2 . Also the time required to become totally locked to a new reference frequency u 1  will be a function of the frequency of the K clock and again maybe as long as the pulse width of the reference signal u 1  and the output signal u 2 . 
     U.S. Pat. No. 5,430,764 (Chren, Jr.) describes a frequency synthesizer using a residue number system to generate an address to find a value in a look-up table containing the digital values of a sine wave. These values are presented to a digital-to-analog converter to create an analog sine wave output. 
     U.S. Pat. No. 5,467,294 (Hsu, et al.) illustrates an apparatus for the programmable generation of sine waves. The digital values to describe the sine wave are maintained in a ROM lookup table. 
     U.S. Pat. No. 4,746,870 (Underhill) describes a frequency synthesizer with reduced jitter. The frequency synthesizer has a reference frequency source, a frequency reduction means, and a jitter compensation signal circuit. The frequency reduction means cancels pulses from a frequency to be reduced. The jitter compensation signal circuit is arranged to compensate for any jitter in the output frequency that would otherwise be caused by each cancelled cycle. The jitter compensation signal is derived from a jitter-containing pulse train via a D.C. removal circuit and an integrator. Additionally, a perturbation signal is injected by a control device which causes pulses to be added to and also to be subtracted, by a pulse addition and a &#34;pulse swallowing&#34; circuit respectively, from the frequency to be reduced. The jitter caused by this addition and subtraction also being compensated for by the compensation signal circuit. 
     U.S. Pat. No. 5,187,722 (Petty) teaches a frequency synthesis circuit which provides an output frequency that greater than a fractional multiple of a reference signal frequency. The frequency synthesis circuit utilizes a fraction multiplier that is placed in the feedback path of a phase locked loop. The fractional multiplication provided is equal to the ratio of the reference signal frequency the desired frequency. The circuit can be utilized in either analog or digitally implemented phase-locked loops and can be coupled with the use a fractional multiplier in the feedforward path of the digitally implemented phase locked loop to improve jitter performance. 
     U.S. Pat. No. 5,276,408 (Norimatsu) discloses a phase locked loop frequency synthesizer that can modify output frequency at high speed. The frequency synthesizer has, a first pulse removing circuit connected between a reference signal generator and a phase-frequency comparator. A second pulse removing circuit is connected between a variable frequency divider and the phase-frequency comparator. Upon receiving of a first removing data indicative of a first pulse number, the first pulse removing circuit removes pulses from the reference signal that are equal in number to the first pulse number for a first predetermined cycle to produce a first pulse removed signal. Upon receiving of a second removing data indicative of a second pulse number, the second pulse removing circuit removes pulses from the divided signal that are equal in number to the second pulse number for a second predetermined cycle to produce a second pulse removed signal. The current controlling circuit controls current supplied from/to a charge pump circuit after receiving a current command. A control circuit is connected between the phase-frequency comparator and the charge pump circuit. A switch is inserted between the loop filter and the voltage controlled oscillator. When the switch switches off a PLL, a DIA converter supplies a control voltage to the voltage controlled oscillator and a filter capacitor of the loop filter. The charge pump circuit comprises a control circuit, a constant current circuit, an integrating circuit, and a sample and hold circuit. 
     SUMMARY OF THE INVENTION 
     An object of this invention is the generation of a binary waveform of a frequency that is synchronized to a reference signal, wherein any change in the binary waveform is accomplished with little time. 
     Another object of this invention is to have a binary waveform with minimal jitter. Still another object of this invention is the elimination of spurious frequencies that degrade the overall performance of the generation of the binary waveform. 
     To accomplish these and other objects, the present invention provides a frequency synthesizing system that will generate a periodic output signal. The periodic output signal has a period that is composed of multiple periods of a periodic reference signal. 
     The frequency synthesizing system has a count compiler to generate a series of counting integers representing the number of periods of the periodic reference signal that compose the period of the periodic output signal. The frequency synthesizing system also has a count series retention table to store a plurality of the series of counting integers; a count incrementing means to select the individual counting integers within the count series retention table; a frequency generation means that will count the number of periods in the period reference signal and when the count is equal to the integer of the from the count series retention table will force the periodic output signal to change from one logic level to another. The count incrementing means will increment and the process will repeat continuously. If a different period for the periodic output signal is required, then a count select signal will choose another series of counting integers and a different series of counting integers will be presented to the frequency generation means. 
     The count compiler executes a first embodiment of the method to construct the series of counting integers by first dividing the frequency of the periodic reference signal by the frequency selected periodic output signal to form a quotient. The quotient is then decomposed into a weighted average of a first integer and a second integer such that the first integer is a largest integer lesser than the quotient and the second integer is a value of the first integer plus one. The quotient is simplified to a mixed number having an integer and a fraction, wherein the fraction has a numerator and a denominator. A series of counting integers is created that include the first and second integers. The number of counting integers is the value of the denominator and the number of second integers in the series of integers is the value of the numerator by the denominator and the number of first integers is the difference of the denominator and the numerator. The first integers and the second integers are then distributed uniformly over the series of counting integers. 
     The distribution of the series of counting integers is accomplished first by comparing the number of the first integers to the number of the second integers. The denominator is divided by a lessor of the number of the first integers and the number of the second integers to form an approximation quotient. The approximation quotient is then truncated to eliminate any fractional part from the approximation quotient to form an interspersal ratio, which is a size of a subsegment of the counting series. 
     If the lessor of the numbers of the first integers and the number of second integers is the number of first integers, the number of first integers in one subsegment is set to one and the number of second integers in the one subsegment is set to the interspersal ratio less one. However, if the lessor of the numbers of the first integers and the number of second integers is the number of second integers, the number of first integers in one subsegment is set to the interspersal ratio less one and the number of second integers in the one subsegment is set to one. The subsegment of the counting series is then arranged such that the first integers are arranged firstly in the subsegment and the second integers are arranged secondly in the subsegment. Each subsegment is then repeated until the number of subsegments is equal to the lessor of the numbers of the first integers and the number of second integers. If the lessor of the numbers of the first integers and the number of second integers is the number of first integers, the residual of the second integers are repeated until the number of second integers have been placed in the counting series. Or if the lessor of the numbers of the first integers and the number of second integers is the number of second integers, the residual of the first integers are repeated until the number of first integers have been placed in the counting series. 
     A first enhancement to further distribute the residual of the first integers or the second integers begins by first determining a residual interspersal ratio. The residual interspersal ratio is formed by dividing the product of the interspersal ratio and the lessor of the number of first integers and the second integers by a number of the residual numbers. The residual numbers are then dispersed over the series of counting integers such that one residual number is placed after a group of series of the counting integers. The number of the group of the counting integers is equal to the residual interspersal ratio. 
     A second enhancement to further distribute the residual of the first integers or the second integers begins by first determining a residual interspersal ratio by dividing the lessor of the number of first integers and the second integers by a number of the residual numbers. The residual numbers are then dispersed over the subsegments of the series of counting integers such that one residual number is placed after a number of subsegments. The number of subsegments is equal to the residual interspersal ratio. 
     The count compiler may execute an alternate method to construct a series of counting integers representing the number of periods of the periods of the periodic reference signal needed to generate a periodic output signal. The alternate method of constructing the series of counting integers by first dividing the frequency selected periodic output signal by the frequency of the periodic reference signal to form a quotient. The quotient is then decomposed into a weighted average of a first integer and a second integer such that the first integer is a largest integer lesser than the quotient and the second integer is a value of the first integer plus one. The quotient is simplified to a mixed number having an integer and a fraction, wherein the fraction has a numerator and a denominator. A series of counting integers is created that include the first and second integers. The number of counting integers is the value of the denominator and the number of second integers in the series of integers is the value of a residue of a dividing of the numerator by the denominator and the number of first integers is the difference of the denominator and the residue. The first integers and the second integers are then distributed uniformly over the series of counting integers. 
     The distribution of the series of counting integers is accomplished first by comparing the number of the first integers to the number of the second integers. The denominator is divided by a lessor of the number of the first integers and the number of the second integers to form an approximation quotient. The approximation quotient is then truncated to eliminate any fractional part from the approximation quotient to form an interspersal ratio, which is a size of a subsegment of the counting series. 
     If the lessor of the numbers of the first integers and the number of second integers is the number of first integers, the number of first integers in one subsegment is set to one and the number of second integers in the one subsegment is set to the interspersal ratio less one. However, if the lessor of the numbers of the first integers and the number of second integers is the number of second integers, the number of first integers in one subsegment is set to the interspersal ratio less one and the number of second integers in the one subsegment is set to one. The subsegment of the counting series is then arranged such that the first integers are arranged firstly in the subsegment and the second integers are arranged secondly in the subsegment. Each subsegment is then repeated until the number of subsegments is equal to the lessor of the numbers of the first integers and the number of second integers. The number of first and second integers of the counting series will be the product of the interspersal ratio and lessor of the numbers of the first integers and the number of second integers. 
     The distribution of the series of counting integers are such that any spurious tones of the periodic output signal are at a higher frequencies. The spurious tones can then be filtered from the period output signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of an all-digital phase locked loop containing a frequency synthesizer of prior art. 
     FIG. 2 is a block diagram of an all digital frequency synthesizer of this invention. 
     FIG. 3 is a functional block diagram detailing an all digital frequency synthesizer of this invention. 
     FIGS. 4a, 4b, and 4c are plots of the waveforms of the periodic output signal of the frequency synthesizer of this invention illustrating the methods of distribution of the series of counting integers. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Refer now to FIG. 2 for a description of an all digital frequency synthesizer having minimal jitter similar to that described in U.S. Pat. No. 5,705,945 (Wee). A frequency generator 26 has an input frequency (f i ) 24. The output frequency F o  is derived by creating each period of time that elapses between a transition of the output 28 from a logical 1 to a logical 0 or from a logical 0 to a logical 1. The period of time for the output frequency F o  is determined by counting a number of clock edges of the input frequency (f i ) 24 and toggling the output 28 from one logic level to another then counting the clock edges of the input frequency 24 again and then toggling the output 28 again from the one logic level back to the original logic level. This process is repeated to form the output frequency F o  at the output 28. 
     The number of pulses of the input frequency 24 to be counted is set by the count input 23 of the frequency generator 26. If the ratio (X n ) of the output frequency F o  to the input frequency f i  is an integer, the count input 23 is set to the value of that integer. For example if: 
     
         F.sub.o =2.457 Mhz 
    
     
         f.sub.i =12.288 Mhz 
    
     
         count=f.sub.i /F.sub.o =X.sub.n =5. 
    
     Therefore, the count input 23 has the value of 5 and the frequency generator 26 will set the output at the beginning of the sequence to a logic 1, then count 5 clock edges of the input frequency 24 then toggle the output to a logic 0 and count 5 clock edges of the input frequency 24 and repeat this process continuously. 
     However, if the ratio X n  of the input frequency f i  to the output frequency F o  is a mixed number of an integer and a fraction, it then must be decomposed into a series of numbers that is the weighted average of two integers, wherein the two integers are consecutive integers. The smaller of the two integers is the integer lesser than the mixed number and the larger number is the next larger integer. For example: 
     
         F.sub.o =2.560 Mhz 
    
     
         f.sub.i =12.288 Mhz 
    
     
         count=f.sub.i /F.sub.o =X.sub.n =44/5 
    
     
         r.sub.n =smallest number=4 
    
     
         s.sub.n =largest number=r.sub.n +1=5 
    
     The numerator of the weighted average of the ratio X n  of the input frequency f i  to the output frequency F o , will form a summation of a series S n  of the two integers r n  and s n . That is S n  =r n ,s n , r n , s n , . . . r n , s n . The number of terms in the series S n  is the denominator q n  of the fraction of the mixed number and the number of the terms N s  of the largest number s n  in the series S n  is the numerator of the fraction in the ratio X n . The number of terms N r  of the smallest number r n  in the series S n  is the difference between the denominator q n  of the fraction of the mixed number and the number of the terms N s  of the largest number s n  in the series S n . In general the formula of the ratio X n  is: ##EQU1## where: r n  is the smallest number. 
     N s  is the number of terms of the largest number s n . 
     q n  is the denominator of the ratio X n . 
     The above fraction is formed by simplifying of the mixed number by searching for the lowest common denominator of the fraction. From the example above: ##EQU2## From the above it can be seen that the q n  =5. Continuing the above example: 
     
         X.sub.n =44/5 
    
     
         q.sub.n =5 
    
     
         r.sub.n =4 
    
     
         s.sub.n =5 
    
     The number of terms N s  of the largest number s n  is N s  =4. The number of terms N r  of the smallest number r n  is N r  =q n  -s n  =1. Therefore: ##EQU3## 
     The series S n  is stored in the count series retention table 14. The count series retention table is implemented as a register based look-up table, a read-only memory, or other logic structure that can contain the series of counting integers. The output 22 of the count series retention table 14 is connected to the count input 23 of the frequency generator 26. 
     The count compiler 10 is a subfunction of an automated design system that will calculate the entries to be placed in the count series retention table 14. The count compiler 10 will have the value of the input frequency f i  and a listing of the desired output frequencies F o  from which to compile each series of the counting integers as described above. The series of counting integers are placed in the count series retention table 14 through interface 12. Interface 12 is a software compiling of the count series retention table 14 or a programming of the count series retention table 14 at the assembly of hardware for the frequency synthesizer. 
     The count select line 16 determines which series of the counting integers in the count series retention table 14 is to be sequentially presented to the frequency generator 26. 
     The output frequency F o  of the frequency generator 26 will remain constant with the jitter of one clock edge of the input frequency f i  cycle, since the counting integers differ by a value of 1. This difference of 1 within the series of counting integers translates to the period of one clock edge of the input frequency f i . 
     Referring to FIG. 3, the counts series table 14 has a plurality of look-up tables 6a, 6b, . . . , 6n that contain the plurality of series of counting integers. The output 8a, 8b, . . . , 8n of each look-up table 6a, 6b, . . . , 6n is connected to a multiplexer 5. The count select line 16 is decoded in the multiplexer 5 to place one of the outputs 8a, 8b, . . . , 8n at the output 22 of the multiplexer 5. 
     The output 20 of the count incrementer 18 is connected to the count look-up tables 6a, 6b, . . . , 6n, to increment the look-up tables 6a, 6b, . . . 6n through the series of counting integers. 
     The count incrementer 18 has a decoder 4 and a counter 2. The decoder 4 determines the number of integers in the series of counting integers from the value of the count select input 16. The value of the number of integers in the series of counting integers is the input 13 to the counter 2. The output 20 of the counter 2 will increment at the end of the period of the output frequency F o . The increment will reset to the beginning of the series of the counting integers when the counter 2 reaches the value of the output 13 of the decoder 4. 
     The frequency generator 26 has a counter 1 that will count the number of periods of the input frequency 24. The input frequency 24 is connected to the clock input clk of the counter 1 and the output 22 of the count series retention table 14 is connected to the maximum count input MAX of the counter 1. 
     The counter 1 will place a logical 1 on the output count when the number of clock edges of the input frequency 24 equal to the number at the input MAX. The counter 1 will reset and start counting again. This process will continue iteratively. The output count is connected to the input clk of the clock generator 3 and the output 22 of the count series retention table 14 is connected to the input IN1 of the clock generator 3. The output OUT of the clock generator 3 is the frequency output 28. The output 28 will toggle from one logic state to another logic state at the reception of the signal from the output count of the counter 1, a transition of the input frequency 24. The output 22 contains the &#34;divide by&#34; value for the clock generator 3 for the present counting period. This value changes as the series S n  is paced on the output 22 of the count retention table 14. 
     The counters 1 and 2 can be designed to switch at the positive edge, the negative edge, or both the positive or the negative edges of the clock input clk. If both edges are used to trigger the counter 1, or 2, the input reference frequency f i  is effectively doubled. The only detriment of this doubling is that if the duty cycle, or the amount of time that the clock is at a logical 1 versus the amount of time it is a logical zero is not 50% or equal, the output jitter will be increased by the amount of the imbalance in this time. 
     As described above the count compiler 10 of FIG. 2 will determine the count series S n . If the count series S n  is distributed inappropriately such all the terms of the smallest number r n  are grouped together within the period of the count series S n  of pulses and the all the terms for the largest number s n  are grouped together within the series S n  of pulses, there may be spurious frequencies present in the output clock F o . These spurious frequencies cause undesirable tones in applications such as pulse coded modulation (PCM). 
     To minimize the spurious frequencies within the output clock F o , the distribution of the smallest number r n  and the largest number s n  should be relatively uniformly interspersed within the counting series S n . 
     FIG. 4a shows the resulting waveform for the output clock F o  created from the counting series: 
     
         S.sub.n =(r.sub.n, s.sub.n, r.sub.n, s.sub.n, . . . , u.sub.n, u.sub.n, u.sub.n, u.sub.n). 
    
     The residual numbers u n  are the excess of the largest quantity of numbers in the counting series S n . That is: ##EQU4## The number N u  of the residual numbers u n  in this case will be: ##EQU5## This distribution, while an improvement, will still contain undesirable spurious frequencies in the output clock F o . 
     A second case, which is the first embodiment of this invention is shown in FIG. 4b. FIG. 4b is the resulting waveform of the output clock F o  of the frequency synthesizer of FIG. 2. The objective being to minimize the number of residual numbers N u  from the series S n . The count compiler will determine the integers r n  and s n . The period of the output frequency F o  will be the product of the smallest number r n  and the period T m  of the input frequency f i  or the product of the largest number s n  and the period T m  of the input frequency f i . The waveform will be formed by interleaving the waveforms having periods equal to the product of the smallest number r n  and the period T m  of the input frequency f i  and the waveforms having periods equal to the product of the largest number s n  and the period T m  of the input frequency f i . The count compiler will use the counting series S n , where: 
     
         S.sub.n =(r.sub.n, r.sub.n, . . . , s.sub.n, r.sub.n, r.sub.n, . . . , s.sub.n, . . . , u.sub.n, u.sub.n, u.sub.n, . . . ). 
    
     In this case an interspersal ratio I r  is defined as the number of terms in a subsegment X n  within the counting series S n  that will contain one (1) repetition of the lessor of the number N r  of the smallest numbers r n  or the number N s  of the largest numbers s n . The interspersal ratio I r  is the integer portion of the function: ##EQU6## The subsegment X n  within the counting series S n  will have a number of terms equal to the interspersal ratio I r . If the interspersal ratio I r  is determined by the number N r  of the smallest numbers r n , there will be one occurrence of the smallest number r n  followed by I r  -1 occurrences of the largest counting number s n . That is the counting series S n  will be: ##EQU7## However, if the interspersal ratio I r  is determined by the number N s  of the largest numbers s n , then there will be I r  -1 occurrences of the smallest number r n  followed by one (1) occurrence of the largest number s n . That is the counting series S n  will be: ##EQU8## 
     The total number of terms N x  of all the subsegments X n  will be the product of the interspersal ratio I r  and the lessor of the number N r  of the smallest numbers r n  and the number N s  of the largest number s n . That is: ##EQU9## The number of residual numbers N u  is the difference between the total number of terms q n  in the counting series S n  and the total number of terms N x  in all subsegments. That is: 
     
         N.sub.u =q.sub.n -N.sub.x. 
    
     The residual terms u n  will be the largest numbers s n  if the number N s  of the largest numbers s n  is greater than the number N r  of the smallest numbers r n , and conversely, the residual terms u n  will be the smallest number r n  if the number N s  of largest numbers s n  is less than the number of the smallest numbers r n . That is: ##EQU10## 
     The first embodiment as above described still has a residual component created by the residual terms u n  that contributes to the undesirable spurious frequencies in the output clock F o . To minimize these contributions of the residual terms u n , the first embodiment is enhanced to distribute the residual terms u n  over the groups of subsegments X n . There are two methods to accomplish the distributions. The first method distributes the residual terms evenly over all the terms of the subsegments X n . The residual interspersal ratio I w  indicates the number of terms in the subsegments X n  after which a residual terms u n  is placed. The residual interspersal ratio is determined as: ##EQU11## 
     The counting series will have one residual terms u n  placed within the final subsegment x n  of a group of subsegments x n . The group of subsegments has a number of subsegments equal to the residual interspersal ratio I w . That is, if the residual terms are the largest number s n , one of the residual largest numbers s un  is added to the final subsegment of the group of subsegments as shown: ##EQU12## where: s un  is the residual largest number. 
     Further, if the residual terms are the smallest number r n , one of the residual smallest numbers r un  is added to the final subsegment of the group of subsegments as shown: ##EQU13## where: r un  is the residual largest number. 
     The second method places the residual terms u n  evenly over the subsegments x n  of the counting series S n . That is a residual term u n  is placed between two subsegments x n  of the counting series S n . In this second method, the residual interspersal ratio I w  determines the number of segments after which each residual term is placed. In this method, the residual interspersal ratio is determined as: ##EQU14## 
     The counting series will have one residual terms u n  placed after the final subsegment x n  of a group of subsegments x n . The group of subsegments has a number of subsegments equal to the residual interspersal ratio I w . That is, if the residual terms are the largest number s n , one of the residual largest numbers s un  is added after the final subsegment of the group of subsegments as shown: ##EQU15## 
     Further, if the residual terms are the smallest number r n , one of the residual smallest numbers r un  is added after the final subsegment of the group of subsegments as shown: ##EQU16## 
     The waveform of the output clock F o  shown in FIG. 4c is created by the method for generating the counting series S n  that is the second embodiment of this invention. In this embodiment, the smallest number r n  and the largest number s n  are calculated as above. The integer portion of the ratio X n  is the smallest number r n  and the smallest number r n  plus one (1) is the largest number s n . 
     The number of terms q&#39; n  in the counting series S n  is now modified to be the number of terms N x  in all the subseqments as calculated above or the number of terms N x  in all the subseqments plus the number of subsegments depending on which is closer to the original number of terms q&#39; n . That is: ##EQU17## The new interspersal ratio I&#39; r  is either intersperal ratio I r  from above or intersperal ratio I r  plus one (I r  +1) and the residual terms are either eliminated or added to every subsegment. If the interspersal ratio I r  is determined by the number N r  of the smallest numbers r n , there will be one occurrence of the smallest number r n  followed by I r  -1 occurrences of the largest counting number s n . That is the counting series S n  will be: ##EQU18## However, if the interspersal ratio I r  is determined by the number N s  of the largest numbers s n , then there will be I&#39; r  -1 occurrences of the smallest number r n  followed by one (1) occurrence of the largest number s n . That is the counting series S n  will be: ##EQU19## 
     In this case the residual terms u n  are eliminated and the fraction is simplified. This will cause any spurious frequencies or tones that are due to the pulse-stripping jitter to be moved to higher frequencies. The higher frequencies are filtered and produces better performance for applications such as PCM. 
     Below is an example of the results of each of the cases described in FIGS. 4a, 4b, and 4c. In each example, the ratio X n  is given as: ##EQU20## Case 1: r n  =26 
     s n  =27 
     q n  =147 
     N s  =104 
     N r  =43 
     N u  =61 ##EQU21## 
     Case 2 illustrates the first embodiment of this invention and is shown as: 
     r n  =26 
     s n  =27 
     q n  =147 
     N s  =104 
     N r  =147-104=43 
     I r  =int qn/Nr=int 147/43=int(3.41860)=3 
     N x  =I r  N r  =3×43=129 
     N u  =18 ##EQU22## 
     Case 2a illustrates the first enhancement of the first embodiment of this invention and is shown as: ##EQU23## In this case, the residual number s un  is added into the series after every seventh number. 
     Case 2b illustrates the second enhancement of the first embodiment of this invention and is shown as: ##EQU24## In this case, the residual number s un  is added into the series after every second subsegment. 
     Case 3 illustrates second embodiment of this invention and is shown as: 
     r n  =26 
     s n  =27 ##EQU25## 
     As can be seen in Case 3, the series of counting integers S n  is simplified and thus the count retention table 14 of FIG. 2 is smaller and simpler. Further, the spurious frequencies due to the extra counts created by Case 3 will be of higher frequencies and can be filtered from the resulting signals in a PCM application. 
     While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details is made without departing from the spirit and scope of the invention.