Abstract:
The present disclosure includes systems and techniques relating to RFID tags including current source control in RFID memory. According to an aspect, a radio frequency identification tag includes an antenna, a radio frequency interface coupled with the antenna, and a non-volatile memory including multiple memory cells, at least one of the memory cells including a floating gate, a control gate, and a dielectric there between. The non-volatile memory includes a controlled current source operable to modify the at least one memory cell. Additionally, the non-volatile memory can include a voltage supply line regulator that limits voltage supply based on a sensed operational current that results from the controlled current source in the non-volatile memory.

Description:
BACKGROUND  
       [0001]     The present application describes systems and techniques relating to radio frequency identification (RFID) tag design and use, for example, an RFID chip design that facilitates programming and erasing of a non-volatile memory included within the RFID tag.  
         [0002]     Traditional RFID tags have included non-volatile memory, such as electrically erasable programmable read-only memory (EEPROM). Programming of RFID memory involves properly setting the voltage, which can be complicated because of the high voltages frequently required to program EEPROM memory cells. Additionally, the charge captured by an EEPROM memory cell during programming changes exponentially with the voltage. Sufficient voltages should be achieved to guarantee programming of the memory cell, but too much voltage can cause catastrophic failure of the circuitry.  
         [0003]     A typical approach to programming an RFID memory relies on trial and error. A low voltage is first applied in the programming cycle to assure that the circuitry does not become damaged and that the memory is not overstressed, which can lead to reliability problems. If the programming is found to be successful through a subsequent read of the memory, further programming is not needed. However, in many cases the programming is found to be insufficient so a second cycle is applied with a slightly higher voltage, and this may be repeated many times until the memory is properly programmed. This technique can require numerous cycles and considerable time.  
       SUMMARY  
       [0004]     The present disclosure includes systems and techniques relating to RFID tags including current source control in RFID memory. According to an aspect, a radio frequency identification tag includes an antenna, a radio frequency interface coupled with the antenna, and a non-volatile memory including multiple memory cells, at least one of the memory cells including a floating gate, a control gate, and a dielectric there between. The non-volatile memory includes a controlled current source operable to modify the at least one memory cell. Additionally, the non-volatile memory can include a voltage supply line regulator that limits voltage supply based on a sensed operational current that results from the controlled current source in the non-volatile memory.  
         [0005]     According to another aspect, a system includes a radio frequency identification (RFID) tag conveyor, a substrate having multiple RFID tags thereon, each RFID tag including a non-volatile memory having a controlled current source operable to modify memory cells in the non-volatile memory, and a programmer. The substrate can be a reel-form substrate, and the RFID tag conveyor can include at least two reels. Moreover, the programmer can be configurable to read the RFID tags, erase the RFID tags and program the RFID tags.  
         [0006]     Using the systems and techniques described, a memory cell in a non-volatile memory of a radio frequency identification tag can be modified (programmed or erased) by forcing a current in a bit line of the non-volatile memory for a predetermined period of time. The systems and techniques described can result in faster programming times and can facilitate accurately controlling the voltage on a chip so as not to cause damage to circuitry.  
         [0007]     Details of one or more implementations are set forth in the accompanying drawings and the description below. Other features and advantages may be apparent from the description and drawings, and from the claims. 
     
    
     DRAWING DESCRIPTIONS  
       [0008]      FIG. 1  illustrates an RFID tag including current source control in the RFID memory.  
         [0009]      FIG. 2  illustrates a non-volatile memory cell.  
         [0010]      FIG. 3  illustrates example RFID memory circuitry including a controlled current source.  
         [0011]      FIG. 4  illustrates example RFID memory circuitry including a voltage supply line regulator and a controlled current source.  
         [0012]      FIGS. 5 and 8 - 25  illustrate an additional example of RFID memory circuitry including a voltage supply line regulator and a controlled current source.  
         [0013]      FIG. 6  illustrates an RFID tag programming system.  
         [0014]      FIG. 7  illustrates a reel-form substrate having modular RFID tags thereon. 
     
    
       [0015]     Like reference symbols in the various drawings indicate like elements.  
       DETAILED DESCRIPTION  
       [0016]      FIG. 1  illustrates an RFID tag  100  including current source control in the RFID memory. The RFID tag  100  includes an antenna  110 , a radio frequency (RF) interface  120 , and a non-volatile memory  140 . The tag  100  can also include control logic  130 .  
         [0017]     The RFID tag  100  can be a low frequency or high frequency tag, and in general, the systems and techniques described can be applied to the full range of RFID (e.g., currently including 125 KHz, 13.56 MHz, 900 MHz, and 2.45 GHz tags). For example, the antenna  110  can be a near-field coupling element configured to operate in a high frequency band. The RFID tag  100  can be a passive or active RFID tag. The tag  100  can obtain its power from an inductive coupling of the tag to energy circulating around a reader coil. Alternatively, the tag  100  can use radiative coupling.  
         [0018]     The RF interface  120 , the control logic  130  and the memory  140  can be combined in a single integrated circuit (IC), such as a low-power complementary metal oxide semiconductor (CMOS) IC chip. The RF interface  120  can be an analog portion of the IC, and the control logic  130  and the memory  140  can be a digital portion of the IC.  
         [0019]     The IC can also include an antenna tuning capacitor and an RF-to-DC rectifier system designed for the antenna  110 , which can be the coupling element for the tag  100 . The antenna  110  can enable the RFID tag to obtain power to energize and active the tag&#39;s chip. The antenna  110  can have many different shapes and sizes, depending on the type of RFID coupling system being employed. The control logic  130  can include both digital control and data modulation circuits. The non-volatile memory  140  includes a controlled current source used in modifying (programming or erasing) the memory cells inside, and the non-volatile memory  140  can be an electrically erasable programmable read only memory (EEPROM).  
         [0020]      FIG. 2  illustrates a non-volatile memory cell  200  that is coupled with a word line  210  and a bit line  220 , such as can be used in the RFID tag of  FIG. 1 . The memory cell  200  includes a floating gate  202 , a control gate  204 , and a dielectric  206  there between. The dielectric  206  can be any number of dielectric materials, depending on the application, such as an oxide layer or an oxide/nitride layer.  
         [0021]     Fowler Nordheim (FN) tunneling current is used in programming the cell  200 . This FN tunneling current can be very difficult to control due to the exponential variation in current with electric field. The field strength across the dielectric is a function of both the applied voltage and the thickness of the dielectric. Field strength increases linearly with applied voltage and inversely with the thickness of the dielectric. Utilizing measured data from a typical silicon foundry supplier, the exponential component used to describe the relationship was found to be approximately 30: 
 
 I=C   1 ×( V/t ) 30    (1) 
 
 where I=current, V=voltage, t=-oxide thickness, and C 1 =cons tan t. 
 
         [0022]     Using this relationship, the variation in the current can be seen to vary considerably. The current used in programming an EEPROM cell is directly proportional the charge accumulated on the floating gate. The programming time required is inversely proportional to the current: 
 
 T=C   2   /I    (2) 
 
 where T=programming time, and C 2 =constant. Therefore, the programming time has the same exponential dependence on the voltage and oxide thickness: 
 
 T=C   3 ×( t/V ) 30    (3) 
 
 where C 3 =C 2 /C 1 . 
 
         [0023]     Assuming that the oxide thickness can vary wafer-to-wafer and lot-to-lot by at least ±2%, the ratio in the programming time would change by a ratio of 3.32. If the total programming voltage across the gate to source is controlled between the limits of 17.5 to 18.5 volts, this would affect the programming time by a ratio of 5.29. Therefore, the programming time based on these two independent parameters would vary by a factor of 17.6. To put this in perspective, if the chip design is configured for the highest voltage and thinnest oxide, it would take 17.6 times longer to program at the lowest voltage and thickest oxide (most difficult to program). If the voltage window is only controlled to 2 volts, this number becomes 93.4. Even if the voltage can be controlled by 0.5 volts, the programming time would vary by a factor of 7.6.  
         [0024]     The solution is to control the programming current. This eliminates the variability associated with thickness of the dielectric and voltage control. Typical current sources can be controlled to within ±20% correlating to a ratio of 1.5. This is considerably better than even the best case above, of 7.6, with voltage regulation. In addition, the circuitry and current requirements can be reduced.  
         [0025]     Controlling the current through a memory cell can eliminate the need for the trial and error approach to programming. By guaranteeing the proper programming current, overstressing of the cell and insufficient programming can be eliminated.  
         [0026]      FIG. 3  illustrates example RFID memory circuitry  300  including a controlled current source. This type of circuit can be used in controlling current through the memory cells of an RFID tag&#39;s non-volatile memory. Word  1  (WL 1 ) can be set to a high voltage (e.g., 12 volts) while Word  2  (WL 2 ) is set low (e.g., 0 volts), thus disabling any writing of cells connected to Word  2 . Transistor N 1  can be turned off while transistor N 2  is turned on. This assures that bit  2  (BL 2 ) is programmed while bit  1  (BL 1 ) is not programmed. The source of the bit line can be at −V, with the drain left floating. Transistor NTM is used as a current mirror to set up constant currents in each of the bit lines (e.g., through NT 2  but not NT 1  when N 2  is turned on and N 1  is turned off). Each bit line seeks its own voltage level to assure the proper level of current and thus, consistent programming.  
         [0027]     Although each individual bit and word line voltage can be controlled so as not to reach excessive voltages, the decode circuitry and voltage supply lines may achieve much higher levels unless regulated. The circuitry of  FIG. 3  can be enhanced to control the internal voltage supply lines or voltage applied to an RFID chip.  
         [0028]      FIG. 4  illustrates example RFID memory circuitry  400  including a voltage supply line regulator and a controlled current source. By adding a dummy cell (BLD, which can be one of multiple dummy cells on a full bit line including transistor ND) that is programmed during each program cycle, the current can be sensed and used to limit the chip&#39;s voltage. The voltage on the source of current source NTD will rise as the desired current is achieved. Transistor NTC is turned on once the voltage rises above its threshold. Transistor NTC can be made large enough to load the voltage supply line  410  and cause the voltage to be controlled.  
         [0029]     Thus, the circuit acts as a feedback loop so that any time the voltage line tries to rise beyond what is necessary to program the cell, it is sensed at the source of NTD and additional loading of the supply line takes place (current is pulled from the supply line). Although this example retains the current control on each bit line, it could also be applied without individual current sources. Since the voltage can be well controlled with the dummy cell, and the variation in the memory cells within a chip&#39;s memory is frequently minimal, a single voltage regulator monitoring the dummy cell can suffice in controlling the programming. In addition, although  FIGS. 4 and 5  discuss programming of the memory, the systems and techniques described can also be applied to erasing the memory.  
         [0030]      FIGS. 5 and 8 - 25  illustrate an additional example of RFID memory circuitry  500  including a voltage supply line regulator and a controlled current source. The RFID memory circuitry  500  includes memory array circuitry  540  and bit line control circuitry  520 . The memory array circuitry  540  is a 33×33 memory array, and details of the circuitry  540  are shown in  FIGS. 8-17  in sections  542 - 560 .  
         [0031]     Details of the bit line control circuitry  520  are shown in  FIGS. 18-25  in sections  522 - 536 . In the bit line control circuitry  520 , the current is set up with current mirrors using a voltage reference (VREFN) which can be generated in another section. By selecting various combinations of the six N channel (I 93 -I 98 ) and six P channel (I 100 -I 104 , I 114 ) transistors, the current selected through the bit lines can be varied by a factor of  36 . This allows setting of the programming time. The programming time can be reduced by increasing the bit line current.  
         [0032]     Current into each of the bit lines is therefore controlled independently through the P channel transistors I 15  and I 26 -I 57 . The switching transistors I 25  and I 59 -I 90  control which bits are to be programmed. In the normal erase mode, all the switching transistors are on so that all the bits are simultaneously erased. Also, the P channel current sources need only be activated in the program and erase modes, at which time PR is high and transistor I 106  is turned on. The four sets of bit lines (8 bit bytes each) are then fed into the memory array.  
         [0033]     An additional P channel current source (I 92 ) and switching transistor (I 91 ) have been added to the bit control circuitry. The BLB 4  line is used to set the voltage regulation for the chip&#39;s voltage supply.  
         [0034]     The systems and techniques described can be used in programming and erasing RFID memory in deployed RFID tags (i.e., tags already attached to target objects) or as part of an RFID manufacturing process.  FIG. 6  illustrates an RFID tag programming system. The system includes an RFID tag conveyor including two reels  610 ,  620  that moves a reel-form substrate  600 , having multiple RFID tags, by a programmer  630 . The programmer  630  can include functionality allowing reading, erasing and programming of the RFID tags. For example, the tags may be manufactured well in advance of use, preprogrammed with inventory information, and stored on the reel  610 . Then, when the tags are to be sold for use in a particular application, the substrate  600  can be attached to the second reel  620 , passed by the programmer  630  and prepared for the application: having the inventory information read and erased, and new application-specific information programmed in.  
         [0035]     Using the systems and techniques described, the RFID memory in the tags can be quickly modified as needed by forcing a current in a bit line of the memory for a predetermined period of time. Given the design of the RFID tags and the corresponding defined time period needed to modify the memory, the total charge applied to the memory cells is known, and the tags can be properly programmed without using a testing operation.  
         [0036]     In addition, the RFID tags can be modular in nature, providing additional flexibility in the tag manufacturing process.  FIG. 7  illustrates a reel-form substrate  700  that has modular RFID tags. A modular tag  710  includes an antenna  720  and a module  730 , which includes a conductive pattern and a chip  740 . For additional details regarding modular tag design and potential manufacturing processes, see the U.S. Patent Application entitled “ATTACHMENT OF RFID MODULES TO ANTENNAS”, U.S. application Ser. No. 10/692,497, filed Oct. 24, 2003, and also the U.S. Patent Application entitled, “CHIP ATTACHMENT IN AN RFID TAG”, U.S. application Ser. No. 10/396,932, filed Mar. 25, 2003.  
         [0037]     Other embodiments may be within the scope of the following claims.