Abstract:
A shift register circuit has a plurality of shift registers. Each of the shift registers has at least four input terminals, a signal input terminal, an output terminal, a pull-up circuit, a driving circuit, a stability driving circuit, and a pull-down circuit. The signal input terminal receives an input signal, and the pull-up circuit is configured to pull up a voltage level of a node of the shift register. The driving circuit outputs a gate driving signal according to the voltage level of the node. The pull-down circuit is configured to pull down the voltage level of the node. The stability driving circuit can pull down the voltage of the output terminal according to the voltages of the four input terminals, and, thus, can reduce the response time of the shift register circuit and increase the operation region of the shift register circuit.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The invention relates to a shift register circuit and shift register, and more particularly, to a shift register circuit and shift register that have a stability driving circuit. 
         [0003]    2. Description of the Prior Art 
         [0004]    Generally, a display panel includes a plurality of pixels, gate driving circuit, and source driving circuit. The gate driving circuit includes a plurality stages of shift register and is used to provide a plurality of gate driving signals for turning on and off the pixels. The source driving circuit is used to write the data into the turned-on pixels. 
         [0005]      FIG. 1  shows the shift register  100  according to prior art and  FIG. 2  shows the timing diagram of the shift register  100  in  FIG. 1 . The shift register  100  includes switches T 1 A and T 1 J. The first terminal of the switch T 1 A receives the gate driving signal G N−1 , the second terminal of the switch T 1 A is coupled to the node Q N , and the control terminal of the switch T 1 A is coupled to the first terminal of the switch T 1 A. The first terminal of the switch T 1 B receives the clock signal HC 1 , the second terminal of the switch T 1 B is coupled to the output terminal Out of the shift register  100  to output the gate driving signal G N , and the control terminal of the switch T 1 B is coupled to the node Q N . The first terminal of the switch T 1 C is fixed to the high gate voltage level VGH, and the control terminal of switch T 1 C is coupled to the first terminal of the switch T 1 C. The first terminal of the switch T 1 D is coupled to the first terminal of the switch T 1 C, the second terminal of the switch T 1 D is coupled to the node P N , and the control terminal of the switch T 1 D is coupled to the second terminal of the switch T 1 C. The first terminal of the switch T 1 E is coupled to the second terminal of the switch T 1 C, the second terminal of the switch T 1 E is coupled to the system voltage terminal V SS , and the control terminal of the switch TIE is coupled to the node Q N . The system voltage terminal V SS  is used to provide the low gate voltage level VGL. The first terminal of the switch T 1 F is coupled to node P N , the second terminal of the switch T 1 F is coupled to the system voltage terminal V SS , and the control terminal of the switch T 1 F is coupled to the node Q N . The first terminal of the switch T 1 G is coupled to the node Q N , the second terminal of the switch T 1 G is coupled to the output terminal Out, and the control terminal of the switch T 1 G is coupled to the node P N . The first terminal of the switch T 1 H is coupled to the out terminal Out, the second terminal of the switch T 1 H is coupled to the system voltage terminal V SS , and the control terminal of the switch T 1 H is coupled to the node P N . The first terminal of the switch T 1 I is coupled to the node Q N , the second terminal of the switch T 1 I is coupled to the output terminal Out, and the control terminal of the switch T 1 I receives the gate driving signal G N+2 . The first terminal of the switch T 1 J is coupled to the output terminal Out, the second terminal of the switch T 1 J is coupled to the system voltage terminal V SS , and the control terminal of the switch T 1 J receives the gate driving signal G N+2 . The gate driving signal G N−1  is the output signal of the shift register that is one stage prior to shift register  100 , and the gate driving signal G N+2  is the output signal of the shift register that is two stage next to shift register  100 . 
         [0006]    In  FIG. 2 , during the period of T 1 , the gate driving signal G N−1  is raised to the high gate voltage level VGH, the gate driving signal G N+2  is kept at the low gate voltage level VGL, and the clock signal HC 1  is at the low gate voltage level VGL. The switch T 1 A is turned on so the voltage level of node Q N  is also raised to the high gate voltage level VGH. Therefore, the switch T 1 B is turned on and the voltage level of the gate driving signal G N  is kept at the low gate voltage level VGL as the clock signal HC 1 . Meanwhile, the switches T 1 C, TIE and T 1 F are turned on. However, since the driving power of TIE is larger than T 1 C, the control terminal of the switch T 1 D is kept at the low gate voltage level VGL and is turned off. Since the switch T 1 F is turned on, the voltage level of the node P N  is also kept at the low gate voltage level VGL and, thus, the switched T 1 G and T 1 H are turned off. 
         [0007]    During the period of T 2 , the gate driving signals G N−1  is back to the low gate voltage level VGL, the gate driving signal G N+2  remains at the low gate voltage level VGL, and the clock signal HC 1  changes to the high gate voltage level VGH. The switch T 1 A is turned off. The switch T 1 B is still turned on, which helps to pull up the voltage level of the gate driving signal G N  to the high gate voltage level as the clock signal HC 1 . The voltage level of the node Q N  is raised to about two times of the high gate voltage level VGH, namely 2VGH, due to the coupling effect of the parasitic capacitor of the switch T 1 B. The switches T 1 C, T 1 E, and T 1 F are still turned on and the switches T 1 D, T 1 G, T 1 H, T 1 I, and T 1 J are still turned off. The voltage level of node P N  remains at the low gate voltage level VGL. 
         [0008]    During the period of T 3 , the gate driving signals G N−1  and G N+2  both remain at the low gate voltage level VGL, and the clock signal HC 1  changes to the low gate voltage level VGL. The switch T 1 A is turned off. The switch T 1 B is turned on and helps to pull down the voltage level of the gate driving signal G N  to the low gate voltage level as the clock signal HC 1 . Meanwhile, the node Q N  is floating so the voltage level of node Q N  will go down as the time goes by. The switches T 1 C, T 1 E, and T 1 F are still turned on, and the switches T 1 D, T 1 G, T 1 H, T 1 I and T 1 J are still turned off. The voltage level of node P N  remains at the low gate voltage level VGL. 
         [0009]    During the period of T 4 , the gate driving signal G N−1  remains at the low gate voltage level VGL, the gate driving signal G N+2  changes to the high gate voltage level VGH, and the clock signal HC 1  changes to the high gate voltage level VGH. The switch T 1 A is still turned off. The switches T 1 I and T 1 J are turned on so the voltage level of the gate driving signal G N  is kept at the low gate voltage level VGL and the voltage level of the node Q N  is pulled down to the low gate voltage level VGL as the gate driving signal G N . Meanwhile, the switch T 1 B, T 1 E, and T 1 F are turned off and switches T 1 C and T 1 D are turned on so the voltage level of the node P N  is pulled up to the high gate voltage level VGH. Therefore, the switches T 1 G and T 1 H are turned on, which help to ensure the voltage level of the node Q N  and the gate driving signal G N  are kept at the low gate voltage level VGL. 
         [0010]    As the resolution of the display panel becomes higher and higher, the required time for the source driving circuit of the display panel to transmit a bit pixel is also shortened. However, since the node Q N  of the aforesaid shift register  100  is floating during the period of T 3  in  FIG. 2 , the driving power of the switch T 1 B to pull down the voltage level of the gate driving signal G N  is rather weak. Consequently, the voltage transition speed of the gate driving signal G N  may not be fast enough and may cause wrong charging or wrong judgment of the display panel. 
       SUMMARY OF THE INVENTION 
       [0011]    One embodiment of the present invention discloses a shift register. The shift register comprises a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a first signal input terminal, a first output terminal, a first system voltage terminal, a second system voltage terminal, a pull-up circuit, a driving circuit, a stability driving circuit, and a pull-down circuit. The pull-up circuit is coupled to the first signal input terminal and a first node for pulling up a voltage level of the first node according to a voltage level of the first signal input terminal. The driving circuit is coupled to the first node, the first input terminal and the first output terminal for controlling the electrical connection between the first input terminal and the first output terminal according to the voltage level of the first node. The stability driving circuit comprises a capacitor, a first switch, a second switch, a third switch, and a fourth switch. The capacitor has a first terminal coupled to the first node and a second terminal coupled to a second node. The first switch has a first terminal coupled to the second system voltage terminal, a second terminal coupled to the second node, and a control terminal coupled to the first input terminal. The second switch has a first terminal coupled to the second system voltage terminal, a second terminal coupled to the second node, and a control terminal coupled to the second input terminal. The third switch has a first terminal coupled to the second node, a second terminal coupled the first system voltage terminal, and a control terminal coupled to the third input terminal. The fourth switch has a first terminal coupled to the second node, a second terminal coupled to the first system voltage terminal, and a control terminal coupled to the fourth input terminal. The pull-down circuit is coupled to the first node, the first output terminal, the first system voltage terminal and the fourth input terminal for pulling down the voltage level of the first node and the first output terminal according to a voltage level of the fourth input terminal. 
         [0012]    Another embodiment of the present invention discloses a shift register circuit. The shift register circuit has a plurality of shift registers and each shift register comprises a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a first signal input terminal, a first output terminal, a first system voltage terminal, a second system voltage terminal, a pull-up circuit, a driving circuit, a stability driving circuit, and a pull-down circuit. The pull-up circuit is coupled to the first signal input terminal and a first node for pulling up a voltage level of the first node according to a voltage level of the first signal input terminal. The driving circuit is coupled to the first node, the first input terminal and the first output terminal for controlling the electrical connection between the first input terminal and the first output terminal according to the voltage level of the first node. The stability driving circuit comprises a capacitor, a first switch, a second switch, a third switch, and a fourth switch. The capacitor has a first terminal coupled to the first node and a second terminal coupled to a second node. The first switch has a first terminal receiving a system high voltage level, a second terminal coupled to the second node, and a control terminal coupled to the first input terminal. The second switch has a first terminal receiving the system high voltage level, a second terminal coupled to the second node, and a control terminal coupled to the second input terminal. The third switch has a first terminal coupled to the second node, a second terminal coupled the first system voltage terminal, and a control terminal coupled to the third input terminal. The fourth switch has a first terminal coupled to the second node, a second terminal coupled to the first system voltage terminal, and a control terminal coupled to the fourth input terminal. The pull-down circuit is coupled to the first node, the first output terminal, the first system voltage terminal and the fourth input terminal for pulling down the voltage level of the first node and the first output terminal according to a voltage level of the fourth input terminal. 
         [0013]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]      FIG. 1  shows a shift register according to the prior art. 
           [0015]      FIG. 2  shows a timing diagram of the shift register in  FIG. 1 . 
           [0016]      FIG. 3  shows a shift register according to one embodiment of the present invention. 
           [0017]      FIG. 4  shows a shift register circuit according to one embodiment of the present invention. 
           [0018]      FIG. 5  shows a timing diagram of the shift register circuit in  FIG. 4 . 
           [0019]      FIG. 6  shows a shift register according to another embodiment of the present invention. 
           [0020]      FIG. 7  shows a shift register circuit according to another embodiment of the present invention. 
           [0021]      FIG. 8  shows a timing diagram of the shift register circuit in  FIG. 7 . 
           [0022]      FIG. 9  shows a timing diagram of a second and a third system voltage of the shift register in  FIG. 6 . 
       
    
    
     DETAILED DESCRIPTION 
       [0023]      FIG. 3  shows a shift register  300  according one embodiment of the present invention. The shift register comprises a first input terminal IN 1 , a second input terminal IN 2 , a third input terminal IN 3 , a fourth input terminal IN 4 , a first signal input terminal S 1 , a first output terminal O 1 , a first system voltage terminal V SS , a second system voltage terminal V DD , a pull-up circuit  380 , a driving circuit  310 , a stability driving circuit  320 , and a pull-down circuit  390 . The first system voltage terminal V SS  can provide a low gate voltage VGL, and the second system voltage terminal V DD  can provide a high gate voltage VGH. In one embodiment of the present invention, the high gate voltage VGH is 20V and the low gate voltage VGL is −8V. However, the aforesaid voltage setting is not to limit the present invention. In addition, the first input terminal IN 1 , the second input terminal IN 2 , and the third input terminal IN 3  are used to receive different clock signals HC 1 , HC 2  and HC 4  respectively. The fourth input terminal IN 4  is used to receive a gate driving signal G N+2 , and the first signal input terminal S 1  is used to receive a gate driving signal G N−1 . The gate driving signal G N−1  is the output of a shift register that is one stage prior to the shift register  300 , and the gate driving signal G N+1  is the output of a shift register that is two stages posterior to the shift register  300 . 
         [0024]    The pull-up circuit  380  is coupled to the first signal input terminal S 1  and a node Q N , and is used for pulling up the voltage level of the node Q N  according to the voltage level of the first signal input terminal S 1 . The driving circuit  310  is coupled to the node Q N , the first input terminal IN 1  and the first output terminal O 1 , and is used for controlling the electrical connection between the first input terminal IN 1  and the first output terminal O 1  according to the voltage level of the node Q N . The stability driving circuit  320  is coupled to the node Q N , the first input terminal IN 1 , the second input terminal IN 2 , the third input terminal IN 3 , the fourth input terminal IN 4  and the first system voltage terminal V SS . The stability driving circuit  320  is used to pull down the voltage level of the first node Q N  according to the voltage levels of the first input terminal IN 1 , the second input terminal IN 2 , the third input terminal IN 3 , the fourth input terminal IN 4 . The pull-down circuit  390  is coupled to the node Q N , the first output terminal O 1 , the first system voltage terminal V SS  and the fourth input terminal IN 4 , and is used to pull down the voltage levels of the node Q N  and the first output terminal O 1  according to the voltage level of the fourth input terminal IN 4 . 
         [0025]    In one embodiment of the present invention, the pull-up circuit  380  comprises a first input switch T 3 A having a control terminal receiving the gate driving signal G N−1 , a first terminal coupled to the control terminal of the first input switch T 3 A, and a second terminal coupled to the node Q N . The driving circuit  310  comprises a switch T 3 B having a first terminal coupled to the first input terminal IN 1 , a second terminal coupled to the first output terminal O 1 , and a control terminal coupled to the node Q N . The stability driving circuit  320  comprises a capacitor C 1 , switches T 3 K, T 3 L, T 3 M, and T 3 N. The capacitor C 1  has a first terminal coupled to the node Q N  and a second terminal coupled to a node Q′ N . The switch T 3 K has a first terminal coupled to the second system voltage terminal V DD , a second terminal coupled to the node Q′ N , and a control terminal coupled to the first input terminal IN 1 . The switch T 3 L has a first terminal coupled to the second system voltage terminal V DD , a second terminal coupled to the node Q′ N , and a control terminal coupled to the second input terminal IN 2 . The switch T 3 M has a first terminal coupled to the node Q′ N , a second terminal coupled the first system voltage terminal V SS , and a control terminal coupled to the third input terminal IN 3 . The switch T 3 N has a first terminal coupled to the node Q′ N , a second terminal coupled to the first system voltage terminal V SS , and a control terminal coupled to the fourth input terminal IN 4 . The pull-down circuit  390  comprises a main pull-down circuit  330 , a first stability control circuit  340 , and a first stability pull-down circuit  350 . The main pull-down circuit  330  is coupled to the node Q N , the first system voltage terminal V SS , the fourth input terminal IN 4  and the first output terminal O 1 , and is used for pulling down the voltage level of the first output terminal O 1  and the node Q N  according to the voltage level of fourth input terminal IN 4 . The first stability control circuit  340  is coupled to the node Q N , the first system voltage terminal V SS  and a node P N  for controlling the voltage level of the node P N  according to the voltage level of the node Q N . The first stability pull-down circuit  350  is coupled to the node Q N , the first system voltage terminal V SS , the first output terminal O 1  and the node P N , and is used for pulling down the voltage levels of the node Q N  and the first output terminal O 1  according to the voltage level of the node P N . 
         [0026]    In one embodiment of the present invention, the main pull-down circuit  330  comprises switches T 3 I and T 3 J. The switch T 3 I has a first terminal coupled to the node Q N , a second terminal coupled to the first output terminal O 1 , and a control terminal coupled to the fourth input terminal IN 4 . The switch T 3 J has a first terminal coupled to the first output terminal O 1 , a second terminal coupled to the first system voltage terminal V SS , and a control terminal coupled to the fourth input terminal IN 4 . The first stability control circuit  340  comprises switches T 3 C, T 3 D, T 3 E and T 3 F. The switch T 3 C has a first terminal coupled to the second system voltage terminal V DD , a second terminal, and a control terminal coupled to the first terminal of the switch T 3 C. The switch T 3 D has a first terminal coupled to the second system voltage terminal V DD , a second terminal coupled to the node P N , and a control terminal coupled to the second terminal of the switch T 3 C. The switch T 3 E has a first terminal coupled to the second terminal of the switch T 3 C, a second terminal coupled to the first system voltage terminal V SS , and a control terminal coupled to the node Q N . The switch T 3 F has a first terminal coupled to the node P N , a second terminal coupled to a first system voltage terminal V SS , and a control terminal coupled to the node Q N . The first stability pull-down circuit  350  comprises switches T 3 G and T 3 H. The switch T 3 G has a first terminal coupled to the node Q N , a second terminal coupled to the first output terminal O 1 , and a control terminal coupled to the node P N . The switch T 3 H has a first terminal coupled to the first output terminal O 1 , a second terminal coupled to the first system voltage terminal V SS , and a control terminal coupled to the node P N . 
         [0027]    The shift register  300  can be used as a gate driver of a display panel. The gate driver can comprise a plurality stage of the shift registers  300  for providing a plurality of gate driving signals to turn on and turn off the pixels of the display panel.  FIG. 4  shows a shift register circuit  400  according to one embodiment of the present invention and  FIG. 5  shows the timing diagram of the shift register circuit  400  in  FIG. 4 . The shift register circuit  400  comprises a plurality of shift registers  300  (for example, the shift registers  300 _ 1  to  300 _ 5 ). Each shift registers  300 _ 1  to  300 _ 5  has the same structure as the shift register  300  in  FIG. 3  has. Each of the shift registers  300 _ 1  to  300 _ 5  can output a gate driving signal G 1  to G 5  from its first output terminal O 1  to the corresponding gate line (also called scan line) in turns for turning on the corresponding row of pixels in the display panel. The first signal input terminal S 1  of each of the shift registers  300 _ 2  to  300 _ 5  receives gate driving signal G 1  to G 4  respectively. The driving signals G 1  to G 4  are outputted from the shift registers  300 _ 1  to  300 _ 4 , that is, the shift registers of prior stage. The first signal input terminal S 1  of the shift register  300 _ 1  receives an initial signal SP. In one embodiment, the shift register  300 _ 1  can output the gate driving signal G 1  firstly, and then the registers  300 _ 2 ,  300 _ 3 ,  300 _ 4  can output the gate driving signal G 2 , G 3 , and G 4  in turns. The shift register  300 _ 5  is the last shift register to output the driving signal G 5  among the five shift registers  300 _ 1  to  300 _ 5 . 
         [0028]    Furthermore, the first input terminal IN 1 , the second input terminal IN 2 , and the third input terminal IN 3  of each of the shift registers  300 _ 1  and the  300 _ 5  receive the clock signals HC 1 , HC 2  and HC 4 . The first input terminal IN 1 , the second input terminal IN 2 , and the third input terminal IN 3  of the shift register  300 _ 2  receive the clock signals HC 2 , HC 3  and HC 1  respectively. The first input terminal IN 1 , the second input terminal IN 2 , and the third input terminal IN 3  of the shift register  300 _ 3  receive the clock signals HC 3 , HC 4  and HC 2  respectively. The first input terminal IN 1 , the second input terminal IN 2 , and the third input terminal IN 3  of the shift register  300 _ 4  receive the clock signals HC 4 , HC 1  and HC 3  respectively. The voltage levels of the clock signals HC 1 , HC 2 , HC 3  and HC 4  are switching between the high gate voltage VGH and the low gate voltage VGL. In addition, the voltage level of each of the clock signals HC 1 , HC 2 , HC 3  and HC 4  switches from low gate voltage VGL to high gate voltage VGH periodically and the clock signals HC 1 , HC 2 , HC 3  and HC 4  have the voltage level at high gate voltage VGH in different time without overlapping. In  FIG. 5 , the clocks signals HC 1 , HC 2 , HC 3  and HC 4  have the same period T P , and the voltage levels of the clock signals HC 1 , HC 2 , HC 3  and HC 4  become high gate voltage VGH sequentially. In one embodiment of the present invention, the phase difference between clock signal HC 2  and cock signal HC 1  is 90°, the phase difference between clock signal HC 3  and cock signal HC 1  is 180°, the phase difference between clock signal HC 4  and cock signal HC 1  is 270°. 
         [0029]    Also, in one embodiment of the present invention, the shift register circuit  400  is operated according to the four clock signals HC 1  to HC 4 , and thus is called a four phase shift register circuit. Consequently, the clock signals received by the three input terminals IN 1  to IN 3  of the N th  shift register in shift register circuit  400  are the same as the clock signals received by the three input terminals IN 1  to IN 3  of the (N+4) th  shift register in shift register circuit  400 , wherein N is a positive integer. For example, the first input terminal IN 1 , the second input terminal IN 2 , and the third input terminal IN 3  of the first shift register  300 _ 1  receive the clock signals HC 1 , HC 2 , and HC 4  respectively, and the first input terminal IN 1 , the second input terminal IN 2 , and the third input terminal IN 3  of the first shift register  300 _ 5  also receive the clock signals HC 1 , HC 2 , and HC 4 . However, the present invention is not limited to the aforesaid example. One can also expand the phase number of the shift register  400  according to the system needs. 
         [0030]      FIG. 5  is the timing diagram of the shift register  300 _ 1  of the shift register circuit  400  in  FIG. 4 .  FIG. 5  can help to explain the features and advantages of the shift register  300  in  FIG. 3 . During period T 1 , the voltage levels of clock signals HC 1  and HC 2  are both at low gate voltage VGL, the voltage level of the clock signal HC 3  is changed from the high gate voltage VGH to the low gate voltage VGL, and the voltage level of the clock signal HC 4  is changed from the low gate voltage VGL to the high gate voltage VGH. The voltage level of the gate driving signal G N−1  is at the high gate voltage VGH, and the voltage level of the gate driving signal G N+2  is at the low gate voltage VGL. The switch T 3 A of the pull-up circuit  380  is turned on so the voltage level of the node Q N  is pulled up to the same voltage level of the gate driving signal G N−1 , namely, the high gate voltage VGH. The switch T 3 B of the driving circuit  310  is also turned on. Thus, the voltage level of the gate driving signal G N  is kept at the same voltage level of the clock signal HC 1 , namely, the low gate voltage VGL. The switches T 3 K, T 3 L, and T 3 N of the stability driving circuit  320  are all turned off and the switch T 3 M is turned on so the voltage level of the node Q′ N  is kept at the low gate voltage VGL. Furthermore, the switches T 3 C, T 3 E, and T 3 F of the first stability control circuit  340  are turned on. However, since the driving power of the switch T 3 E is greater than the switch T 3 C, the switch T 3 D is turned off and the voltage level of the node P N  is kept at the low gate voltage VGL. The switches T 3 G and T 3 H of the first stability pull-down circuit  350  are turned off, and the switches T 3 I and T 3 J of the main pull-down circuit  330  are also turned off. 
         [0031]    During the period T 2 , the voltage level of clock signal HC 1  is changed to the high gate voltage VGH, the voltage level of the clock signals HC 2  and HC 3  are at the low gate voltage VGL, and the voltage level of the clock signal HC 4  is changed from the high gate voltage VGH to the low gate voltage VGL. The voltage level of the gate driving signal G N−1  is changed to the low gate voltage VGL, and the voltage level of the gate driving signal G N+2  is also at the low gate voltage VGL. The switch T 3 A of the pull-up circuit  380  is turned off and the switch T 3 B of the driving circuit  310  is still turned on. Thus, the voltage level of the gate driving signal G N  is pulled up to the same voltage level of the clock signal HC 1 , namely, the high gate voltage VGH. The switches T 3 L, T 3 M, and T 3 N of the stability driving circuit  320  are all turned off and the switch T 3 K is turned on so the voltage level of the node Q′ N  is pulled up to the high gate voltage VGH. Meanwhile, the voltage level of the node Q N  is pulled up to about 2 times the high gate voltage VGH, namely 2VGH, due to the coupling effect of the capacitor C 1 . Furthermore, the switches T 3 C, T 3 E, and T 3 F of the first stability control circuit  340  are turned on and the switch T 3 D is still turned off so the voltage level of the node P N  is at the low gate voltage VGL. The switches T 3 G and T 3 H of the first stability pull-down circuit  350  remain turned off, and the switches T 3 I and T 3 J of the main pull-down circuit  330  are also turned off. 
         [0032]    During the period T 3 , the voltage level of clock signal HC 1  is changed to the low gate voltage VGL, the voltage level of the clock signal HC 2  is changed from the low gate voltage VGL to the high gate voltage VGH, and the voltage level of the clock signals HC 3  and HC 4  are at the low gate voltage VGL. The voltage level of the gate driving signal G N−1  is at the low gate voltage VGL, and the voltage level of the gate driving signal G N+2  is also at the low gate voltage VGL. The switch T 3 A of the pull-up circuit  380  is turned off. The switches T 3 K, T 3 M, and T 3 N of the stability driving circuit  320  are all turned off and the switch T 3 L is turned on so the voltage level of the node Q′ N  is at the high gate voltage VGH. Thus, the voltage level of the node Q N  can be kept at a voltage level higher than the high gate voltage VGH. The switch T 3 B of the driving circuit  310  remains turned on so the voltage level of the gate driving signal G N  is pulled down to the same voltage level of the clock signal HC 1 , namely, the low gate voltage VGL. Furthermore, the switches T 3 C, T 3 E, and T 3 F of the first stability control circuit  340  are still turned on and the switch T 3 D is still turned off so the voltage level of the node P N  is at the low gate voltage VGL. The switches T 3 G and T 3 H of the first stability pull-down circuit  350  remain turned off, and the switches T 3 I and T 3 J of the main pull-down circuit  330  are also turned off. 
         [0033]    During the period T 4 , the voltage level of clock signals HC 1  and HC 4  are at the low gate voltage VGL, the voltage level of the clock signal HC 2  is changed from the high gate voltage VGH to the low gate voltage VGL, and the voltage level of the clock signal HC 3  is changed from the low gate voltage VGL to the high gate voltage VGH. The voltage level of the gate driving signal G N−1  is at the low gate voltage VGL, and the voltage level of the gate driving signal G N+2  is changed from the low gate voltage VGL to the high gate voltage VGH. The switch T 3 A of the pull-up circuit  380  is turned off. The switches T 3 K and T 3 L of the stability driving circuit  320  are all turned off and the switches T 3 M and T 3 M are turned on so the voltage level of the node Q′ N  is pulled down to the low gate voltage VGL. Meanwhile, the switches T 3 I and T 3 J of the main pull-down circuit  330  are turned on so the voltage level of the node Q N  is pulled down to the low gate voltage VGL rapidly and the switch T 3 B of the driving circuit  310  is turned off. Furthermore, the switches T 3 E and T 3 F of the first stability control circuit  340  are turned off and the switches T 3 C and T 3 D are turned on so the voltage level of the node P N  is pulled up to the high gate voltage VGH. Thus, the switches T 3 G and T 3 H of the first stability pull-down circuit  350  are turned on, and the voltage level of the node Q N  and the gate driving signal G N  remain at the low gate voltage VGL stably. 
         [0034]    In one embodiment of the present invention, the switch T 3 A to T 3 F, T 3 H and T 3 I can be N-type transistors (ex, N-type TFT or N-type MOSFET), and the control terminal of each of the switch can be the gate of an N-type transistor. Therefore, the process of manufacturing the shift register according to the embodiments of the present invention can be simplified by using fewer masks. 
         [0035]    According to the aforesaid embodiments of the present invention, the stability driving circuit  320  of the shift register  300 _ 1  can keep the voltage level of the node Q′ N  at the high gate voltage VGH or the low gate voltage VGL according to the clock signals HC 1 , HC 2  and HC 4  and the gate driving signal G N+2  coming from the shift register two stages posterior. Consequently, the node Q′ N  can be free from floating. Meanwhile, during the period when the gate driving signal G N  is pulled down by the shift register  300 _ 1 , the node Q N  is kept at high voltage level and thus has stable power to pull down the voltage level of the gate driving signal G N  to the low gate voltage VGL rapidly, ensuring the waveform of the gate driving signal outputted by the shift register remains correct and preventing the display panel from wrong charging or wrong judgment. 
         [0036]    In one embodiment of the present invention, to drive a display panel with larger area, the shift register  300  may further comprise a second output terminal O 2 . The gate driving signal ST N  outputted by the second output terminal O 2  has the same timing and same function as the gate driving signal G N  outputted by the first output terminal O 1  does. In addition, to avoid the threshold voltage of the switches of the first stability control circuit  340  and the first stability pull-down circuit  350  in shift register  300  from shifting caused by operating under fixed voltage for long period of time, the pull-down circuit  390  of the shift register  300  may further comprise a second stability control circuit and a second stability pull-down circuit.  FIG. 6  shows the shift register  600  according to another embodiment of the present invention. The shift register  600  comprises a first input terminal IN 1 , a second input terminal IN 2 , a third input terminal IN 3 , a fourth input terminal IN 4 , a first signal input terminal S 1 , a second signal input terminal S 2 , a first output terminal O 1 , a second output terminal O 2 , a first system voltage terminal V SS , a second system voltage terminal LC 1 , a third system voltage LC 2 , a pull-up circuit  680 , a driving circuit  610 , a stability driving circuit  620 , and a pull-down circuit  690 . The first input terminal IN 1 , the second input terminal IN 2 , and the third input terminal IN 3  are used to receive different clock signals respectively. The fourth input terminal IN 4  is used to receive a gate driving signal ST N+2 , the first signal input terminal S 1  is used to receive a gate driving signal G N−1 , and the second signal input terminal S 2  is used to receive a gate driving signal ST N−1 . The gate driving signals G N−1  and ST N−1  are the outputs of the shift register of one stage prior to the shift register  600 , and the gate driving signals ST N+2  is the output of the shift register of two stages posterior to the shift register  600 . Since the gate driving signal ST N  and the gate driving signal G N  have the same timing, the fourth input terminal IN 4  can also be used to receive the gate driving signal G N+2  in another embodiment of the present invention. 
         [0037]    In one embodiment of the present invention, the pull-up circuit  680  comprises input switches T 6 A T 6 B and T 6 C. The first terminal of the input switch T 6 A is coupled to the first signal input terminal S 1 , the control terminal of the input switch T 6 A is coupled to the second signal input terminal S 2 . The first terminal of the input switch T 6 B is coupled to the second terminal of the input switch T 6 A, the second terminal of the input switch T 6 B is coupled the node Q N , and the control terminal of the input switch T 6 B is coupled to the second signal input terminal S 2 . The first terminal of the input switch T 6 C is coupled to the second terminal of the input switch T 6 A, the second terminal of the input switch T 6 C is coupled to the first output terminal O 1 , and the control terminal of the input switch T 6 C is coupled to the second terminal of the input switch T 6 C. The driving circuit  610  comprises switches T 3 B and T 6 D. The first terminal of the switch T 3 B is coupled to the first input terminal IN 1 , the second terminal of the switch T 3 B is coupled to the first output terminal O 1 , and the control terminal of the switch T 3 B is coupled to the node Q N . The first terminal of the switch T 6 D is coupled to the first input terminal IN 1 , the second terminal of the switch T 6 D is coupled to the second output terminal O 2 , and the control terminal of the switch T 6 D is coupled to the node Q N . Furthermore, the stability driving circuit  620  has the same structure as the stability driving circuit  320  in  FIG. 3 , except that voltage levels of the first terminals of the switches T 3 K and T 3 L are fixed to the high gate voltage VGH. The pull-down circuit  690  comprises a main pull-down circuit  630 , a first stability control circuit  640 , a first stability pull-down circuit  650 , a second stability control circuit  660 , and a second stability pull-down circuit  670 . In addition to the switches T 3 C, T 3 D, T 3 E, and T 3 F of first stability control circuit  340  in  FIG. 3 , the first stability control circuit  640  further comprises a switch T 6 E. The first terminal of the switch T 6 E is coupled to the second system voltage LC 1 , the second terminal of the switch T 6 E is coupled to the second terminal of the switch T 3 C, and the control terminal of the switch T 6 E is coupled to the first terminal of the switch T 6 E. In addition to the switches T 3 H of the first stability pull-down circuit  350  in  FIG. 3 , the first stability pull-down circuit  650  further comprises switches T 6 F and T 6 G. The first terminal of the switch T 6 F is coupled to the node Q N , the second terminal of the switch T 6 F is coupled to the second output terminal O 2 , and the control terminal of the switch T 6 F is coupled to the node P N . The first terminal of the switch T 6 G is coupled to the second output terminal O 2 , the second terminal of the switch T 6 G is coupled to the first system voltage V SS , and the control terminal of the switch T 6 G is coupled to the node P N . The second stability control circuit  660  comprises switches T 6 H, T 6 I, T 6 J, T 6 K, and T 6 L. The first terminal of the switch T 6 I is coupled to the third system voltage terminal LC 2 , and the control terminal of the switch T 6 I is coupled to the first terminal of the switch T 6 I. The first terminal of the switch T 6 J is coupled to the third system voltage terminal LC 2 , the second terminal of the switch T 6 J is coupled to the fourth node K N , and the control terminal of the switch T 6 J is coupled to the second terminal of the switch T 6 I. The first terminal of the switch T 6 K is coupled to the second terminal of the switch T 6 I, the second terminal of the switch T 6 K is coupled to the first system voltage terminal V SS , and the control terminal of the switch T 6 K is coupled to the node Q N . The first terminal of the switch T 6 L is coupled to the fourth node K N , the second terminal of the switch T 6 L is coupled to a first system voltage terminal V SS , and the control terminal of the switch T 6 L is coupled to the node Q N . The first terminal of the switch T 6 H is coupled to the third system voltage terminal LC 2 , the second terminal of the switch T 6 H is coupled to the second terminal of the switch T 6 I, and the control terminal of the switch T 6 H is coupled to the second terminal of the switch T 6 H. The second stability pull-down circuit  670  comprises switches T 6 M, T 6 N and T 60 . The first terminal of the switch T 6 M is coupled to the node Q N , the second terminal of the switch T 6 M is coupled to the second output terminal O 2 , and the control terminal of the switch T 6 M is coupled to the fourth node K N . The first terminal of the switch T 60  is coupled to the first output terminal O 1 , the second terminal of the switch T 60  is coupled to the first system voltage terminal V SS , and the control terminal of the switch T 60  is coupled to the fourth node K N . The first terminal of the switch T 6 N is coupled to the second output terminal O 2 , the second terminal of the switch T 6 N is coupled to the first system voltage terminal V SS , and the control terminal of the switch T 6 N is coupled to the fourth node K N . In addition to the switch T 3 J of the main pull-down circuit  330  in  FIG. 3 , the main pull-down circuit  630  further comprises switches T 6 P and T 6 Q. The first terminal of the switch T 6 P is coupled to the node Q N , the second terminal of the switch T 6 P is coupled to the second output terminal O 2 , and the control terminal of the switch T 6 P is coupled to the fourth input terminal IN 4 . The first terminal of the switch T 6 Q is coupled to the second output terminal O 2 , the second terminal of the switch T 6 Q is coupled to the first system voltage terminal V SS , and the control terminal of the switch T 6 Q is coupled to the fourth input terminal IN 4 . 
         [0038]    The shift register  600  can be used as a gate driver of a display panel. The gate driver can comprise a plurality of stages of the shift registers  600  for providing a plurality of gate driving signals to turn on and off the pixels of the display panel.  FIG. 7  shows a shift register circuit  700  according to one embodiment of the present invention and  FIG. 8  shows the timing diagram of the shift register circuit  700  in  FIG. 7 . The shift register circuit  700  comprises a plurality of shift registers  600  (for example, the shift registers  600 _ 1  to  600 _ 5 ). Each shift registers  600 _ 1  to  600 _ 5  has the same structure as does the shift register  600  in  FIG. 6 . Each of the shift registers  600 _ 1  to  600 _ 5  can output gate driving signals G 1  to G 5  and ST 1  to ST 5  from its first output terminal O 1  and second output terminal O 2  to the corresponding gate line (also called scan line) in turn for turning on the corresponded row of pixels in the display panel. The first signal input terminal S 1  of each of the shift registers  600 _ 2  to  500 _ 5  receives gate driving signals G 1  to G 4  outputted from the shift registers  600 _ 1  to  600 _ 4  respectively, that is, the shift registers of prior stage. The second signal input terminals S 2  of the shift registers  600 _ 2  to  500 _ 5  receive gate driving signals ST 1  to ST 4  respectively. The first signal input terminal S 1  and the second signal input terminal S 2  of the shift register  300 _ 1  receive initial signals SP 1  and SP 2 . In one embodiment, the shift register  600 _ 1  can output the gate driving signals G 1  and ST 1 firstly, and then the registers  600 _ 2 ,  600 _ 3 ,  600 _ 4  can output the gate driving signals G 2  to G 4  and ST 2  to ST 4  in turn. The shift register  600 _ 5  is the last shift register to output the driving signals G 5  and ST 5  among the five shift registers  600 _ 1  to  600 _ 5 . 
         [0039]    Furthermore, the first input terminals IN 1 , the second input terminals IN 2 , and the third input terminals IN 3  of the shift registers  600 _ 1  and the  600 _ 5  receive the clock signals HC 1 , HC 2  and HC 4 . The first input terminal IN 1 , the second input terminal IN 2 , and the third input terminal IN 3  of the shift register  600 _ 2  receives the clock signals HC 2 , HC 3  and HC 1  respectively. The first input terminal IN 1 , the second input terminal IN 2 , and the third input terminal IN 3  of the shift register  600 _ 3  receive the clock signals HC 3 , HC 4  and HC 2  respectively. The first input terminal IN 1 , the second input terminal IN 2 , and the third input terminal IN 3  of the shift register  600 _ 4  receive the clock signals HC 4 , HC 1  and HC 3  respectively. The voltage levels of the clock signals HC 1 , HC 2 , HC 3  and HC 4  are switching between the high gate voltage VGH and the low gate voltage VGL. In addition, the voltage level of each of the clock signals HC 1 , HC 2 , HC 3  and HC 4  switches from low gate voltage VGL to high gate voltage VGH periodically and the clock signals HC 1 , HC 2 , HC 3  and HC 4  have the voltage level at high gate voltage VGH at different times without overlapping. In  FIG. 8 , the clocks signals HC 1 , HC 2 , HC 3  and HC 4  have the same period T P , and the voltage levels of the clock signals HC 1 , HC 2 , HC 3  and HC 4  become high gate voltage VGH sequentially. In one embodiment of the present invention, the phase difference between clock signal HC 2  and cock signal HC 1  is 90°, the phase difference between clock signal HC 3  and cock signal HC 1  is 180°, the phase difference between clock signal HC 4  and cock signal HC 1  is 270. 
         [0040]    Also, in one embodiment of the present invention, the shift register circuit  700  is operated according to the four clock signals HC 1  to HC 4 , and thus is called a four phase shift register circuit. Consequently, the clock signals received by the three input terminals IN 1  to IN 3  of the N th  shift register in shift register circuit  700  are the same as the clock signals received by the three input terminals IN 1  to IN 3  of the (N+4) th  shift register in shift register circuit  700 , wherein N is a positive integer. For example, the first input terminal IN 1 , the second input terminal IN 2 , and the third input terminal IN 3  of the first shift register  600 _ 1  receive the clock signals HC 1 , HC 2 , and HC 4  respectively, and the first input terminal IN 1 , the second input terminal IN 2 , and the third input terminal IN 3  of the first shift register  600 _ 5  also receive the clock signals HC 1 , HC 2 , and HC 4 . However, the present invention is not limited to the aforesaid example. People with general related knowledge can also expand the phase number of the shift register circuit  700  according to the system needs. 
         [0041]      FIG. 8  is the timing diagram of the shift register  600 _ 1  of the shift register circuit  700  in  FIG. 7 .  FIG. 8  explains the features and advantages of the shift register  600 . In  FIG. 8 , the second system voltage terminal LC 1  is at the high gate voltage VGH and the third system voltage terminal LC 2  is at the low gate voltage VGL so the voltage level of the fourth node K N  is kept at the low gate voltage VGL and the second stability pull-down circuit  670  is turned off. In this case, the first stability control circuit  640  and the first stability pull-down circuit  650  are used to pull down the voltage level of the node Q N  and the gate driving signals G N , and ST N  to the low gate voltage VGL. In one embodiment of the present invention, the second system voltage terminal LC 1  and the third system voltage terminal LC 2  are switching between the high gate voltage VGH and the low gate voltage VGL after every period T f  as shown in  FIG. 9 . When the second system voltage terminal LC 1  is at the high gate voltage VGH, the third system voltage terminal LC 2  is at the low gate voltage VGL. When the second system voltage terminal LC 1  is at the low gate voltage VGL, the third system voltage terminal LC 2  is at the high gate voltage VGH. Therefore, the transistors in the first stability control circuit  640 , the first stability pull-down circuit  650 , the second stability control circuit  660 , and the second stability pull-down circuit  670  can be free from electronic characteristics shifting caused by operating under fixed voltage for long period of time, and the driving power of the transistors can be sustained. In addition, the structure of the second stability control circuit  660 , and the second stability pull-down circuit  670  are same as the structure of the first stability control circuit  640 , and the first stability pull-down circuit  650 . Therefore, the second stability control circuit  660  and the second stability pull-down circuit  670  can be used to pull down the voltage level of the node Q N  and the gate driving signals G N , and ST N  to the low gate voltage VGL when the third system voltage terminal LC 2  is at the high gate voltage VGH. In this case, the voltage level of the fourth node K N  can be seen as the voltage level of the node P N  in  FIG. 8 . In one embodiment of the present invention, the period T f  can be the time of a hundred frames of the display, however, this is not to limit the present invention. 
         [0042]    Please refer  FIGS. 6 and 8 . During period T 1 , the voltage levels of clock signals HC 1  and HC 2  are both at low gate voltage VGL, the voltage level of the clock signal HC 3  is changed from the high gate voltage VGH to the low gate voltage VGL, and the voltage level of the clock signal HC 4  is changed from the low gate voltage VGL to the high gate voltage VGH. The voltage level of the gate driving signals G N−1  and ST N−1  are at the high gate voltage VGH, and the voltage level of the gate driving signal ST N+2  is at the low gate voltage VGL. The switches T 6 A and T 6 B of the pull-up circuit  680  are turned on so the voltage level of the node Q N  is pulled up to the same voltage level of the gate driving signal G N−1 , namely, the high gate voltage VGH, and the switches T 3 B and T 6 D of the driving circuit  610  are also turned on. Thus, the voltage level of the gate driving signal G N  and ST N  are kept at the same voltage level of the clock signal HC 1 , namely, the low gate voltage VGL. The switches T 3 K, T 3 L, and T 3 N of the stability driving circuit  620  are all turned off and the switch T 3 M is turned on so the voltage level of the node Q′ N  is kept at the low gate voltage VGL. Furthermore, the switches T 3 C, T 3 E, and T 3 F of the first stability control circuit  640  are turned on. However, since the driving power of the switch T 3 E is greater than the switch T 3 C, the switch T 3 D is turned off and the voltage level of the node P N  is kept at the low gate voltage VGL. The switches T 6 F, T 6 G and T 3 H of the first stability pull-down circuit  650  are turned off, and the switches T 6 P, T 6 Q, and T 3 J of the main pull-down circuit  630  are also turned off. 
         [0043]    During the period T 2 , the voltage level of clock signal HC 1  is changed to the high gate voltage VGH, the voltage level of the clock signals HC 2  and HC 3  are at the low gate voltage VGL, and the voltage level of the clock signal HC 4  is changed from the high gate voltage VGH to the low gate voltage VGL. The voltage level of the gate driving signals G N−1  and ST N−1  are changing to the low gate voltage VGL, and the voltage level of the gate driving signal ST N+2  is also at the low gate voltage VGL. The switches TEA and T 6 B of the pull-up circuit  680  are turned off and the switches T 3 B and TED of the driving circuit  610  are still turned on. Thus, the voltage level of the gate driving signals G N  and ST N  are pulled up to the same voltage level of the clock signal HC 1 , namely, the high gate voltage VGH. The switches T 3 L, T 3 M, and T 3 N of the stability driving circuit  620  are all turned off and the switch T 3 K is turned on so the voltage level of the node Q′ N  is pulled up to the high gate voltage VGH. Meanwhile, the voltage level of the node Q N  is pulled up to about 2 times the high gate voltage VGH, namely 2VGH, due to the coupling effect of the capacitor C 1 . Furthermore, the switches T 3 C, T 3 E, and T 3 F of the first stability control circuit  640  are turned on and the switches T 3 D and TEE are still turned off so the voltage level of the node P N  is at the low gate voltage VGL. The switches T 6 F, T 6 G and T 3 H of the first stability pull-down circuit  650  remain turned off, and the switches T 3 P, T 6 Q and T 3 J of the main pull-down circuit  630  are also turned off. 
         [0044]    During the period T 3 , the voltage level of clock signal HC 1  is changed to the low gate voltage VGL, the voltage level of the clock signal HC 2  is changed from the low gate voltage VGL to the high gate voltage VGH, and the voltage level of the clock signals HC 3  and HC 4  are at the low gate voltage VGL. The voltage level of the gate driving signals G N−1  and ST N−1  are at the low gate voltage VGL, and the voltage level of the gate driving signal ST N+2  is also at the low gate voltage VGL. The switches TEA, T 6 B, and T 6 C of the pull-up circuit  680  are turned off. The switches T 3 K, T 3 M, and T 3 N of the stability driving circuit  620  are all turned off and the switch T 3 L is turned on so the voltage level of the node Q′ N  is at the high gate voltage VGH. Thus, the voltage level of the node Q N  can be kept at a voltage level higher than the high gate voltage VGH. The switches T 3 B and TED of the driving circuit  610  remain turned on so the voltage level of the gate driving signals G N  and ST N  are pulled down to the same voltage level of the clock signal HC 1 , namely, the low gate voltage VGL. Furthermore, the switches T 3 C, T 3 E, and T 3 F of the first stability control circuit  640  are still turned on and the switches T 3 D and T 6 E are still turned off so the voltage level of the node P N  is at the low gate voltage VGL. The switches T 6 F, T 6 G and T 3 H of the first stability pull-down circuit  650  remain turned off, and the switches T 6 P, T 6 Q and T 3 J of the main pull-down circuit  630  are also turned off. 
         [0045]    During the period T 4 , the voltage level of clock signals HC 1  and HC 4  are at the low gate voltage VGL, the voltage level of the clock signal HC 2  is changed from the high gate voltage VGH to the low gate voltage VGL, and the voltage level of the clock signal HC 3  is changed from the low gate voltage VGL to the high gate voltage VGH. The voltage level of the gate driving signals G N−1  and ST N−1  are at the low gate voltage VGL, and the voltage level of the gate driving signal ST N+2  is changed from the low gate voltage VGL to the high gate voltage. The switches T 6 A, T 6 B, and T 6 C of the pull-up circuit  680  are turned off. The switches T 3 K and T 3 L of the stability driving circuit  620  are all turned off and the switches T 3 M and T 3 M are turned on so the voltage level of the node Q′ N  is pulled down to the low gate voltage VGL. Meanwhile, since the switches T 6 P, T 6 Q and T 3 J of the main pull-down circuit  630  are turned on, the voltage level of the node Q N  is pulled down to the low gate voltage VGL rapidly and the switches T 3 B and T 6 D of the driving circuit  610  are turned off. Furthermore, the switches T 3 E and T 3 F of the first stability control circuit  640  are turned off and the switches T 3 C, T 3 D, and T 6 E are turned on so the voltage level of the node P N  is pulled up to the high gate voltage VGH. Thus, the switches T 6 F, T 6 G and T 3 H of the first stability pull-down circuit  650  are turned on, and the voltage level of the node Q N  and the gate driving signals G N  and ST N  remain at the low gate voltage VGL stably. 
         [0046]    According to the aforesaid embodiments of the present invention, the stability driving circuit  620  of the shift register  600 _ 1  can keep the voltage level of the node Q′ N  at the high gate voltage VGH or the low gate voltage VGL according to the clock signals HC 1 , HC 2  and HC 4  and the gate driving signal ST N+2  coming from the shift register two stages posterior. Consequently, the node Q′ N  can be free from floating. Meanwhile, during the period when the gate driving signal G N  is pulled down by the shift register  600 _ 1 , the node Q N  is kept at high voltage level and thus has stable power to pull down the voltage level of the gate driving signals G N  and ST N  to the low gate voltage VGL rapidly, ensuring the waveform of the gate driving signal outputted by the shift register remains correct and preventing the display panel from wrong charging or wrong judgment. 
         [0047]    In addition, in the explanation above, clock signals HC 1 , HC 2 , HC 3 , and HC 4  can also be called as a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. The shift register  300 _ 1  can be called as a first shift register. The shift register  300 _ 2  can be called as a second shift register. The shift register  300 _ 3  can be called as a third shift register. The shift register  300 _ 4  can be called as a fourth shift register. The capacitor C 1  can be called as a first capacitor. The switches T 3 A and T 6 A can be called as a first input switch, and the switches T 3 K, T 3 L, T 3 M, and T 3 N can also be called as first to fifth switches respectively. The switch T 6 B can be called as a second input switch. The switch T 6 C can be called as a third input switch. Furthermore, the switched T 3 I and T 6 P can be called as a sixth switch. The switch T 3 J can be called as a seventh switch, and the switch T 3 C, T 3 E, T 3 D, and T 3 F can also be called as the eighth to eleven switches respectively. The switch T 3 G and T 6 F can be called as a twelve switch. The switch T 3 H can be called as a thirteen switch. The switch T 6 E can be called as a fourteen switch. The switch T 6 G can be called as a fifteen switch. The switches T 6 I, T 6 K, T 6 J, and T 6 L can be called as sixteen to nineteen switches respectively. The switch T 6 H can be called as a twenty switch. The switches T 6 M, T 60 , and T 6 N can be called as twenty-first to twenty-third switches respectively. The switch T 6 D can also be called as a twenty-fourth switch and the switch T 6 Q can be called as a twenty-fifth switch. Moreover, the nodes Q N , Q′ N , P N , and K N  can be called as first node to fourth nodes respectively. 
         [0048]    In summary, by using the shift register of the present invention, the gate driving signal can be generated correctly to serve the needs of the display. By considering the three different clock signals and the gate driving signals outputted from shift register of one stage prior and the shift register of two stages posterior, the shift register can keep the voltage level of the critical node in the driving circuit to the high gate voltage or the low gate voltage so that the floating node situation can be avoided. In addition, the stable high voltage level of the node can also help to pull down the gate driving signal accurately and rapidly. Consequently, shift register of the present invention can generate the waveform of the gate driving signal correctly and prevent the display panel from wrong charging or wrong judgment. 
         [0049]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.