Abstract:
An embedded memory device solves the problem of the low reliability of the circuit due to the unstable power source. The embedded memory includes a metal-oxide semiconductor (MOS) capacitor and a metal-insulator-metal (MIM) capacitor to increase the stability of the power source ring to stabilize the voltage of the embedded memory and stabilize the voltage for the peripheral circuit of the embedded memory.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to an embedded memory device. In particular, this invention relates to an embedded memory device and a manufacturing method thereof that uses an integrated circuit manufacturing process to enhance stability of the voltage. 
         [0003]    2. Description of the Related Art 
         [0004]    For the industrial technology, an electronic system can be integrated into a single chip—named as system on chip (SOC). The SOC is manufactured by an integrated circuit manufacturing process, and the SOC is composed of a processor, an embedded memory, a variety of peripheral interfaces and external bus interfaces. During the evolution of technology, the development of SOC let the system designer can reduce the dimension occupied by the electronic system and the testing time. The reliability of the SOC is enhanced, and the developing time of the SOC is reduced. 
         [0005]    The embedded memory is an important electronic element for the SOC. Reference is made to  FIGS. 1A and 1B .  FIG. 1A  is a top view of the circuit layout of the embedded memory of the prior art.  FIG. 1B  is a cross-sectional view of the circuit layout of the embedded memory of the prior art. In  FIG. 1A , the embedded memory circuit includes a core circuit  10 , a grounding ring  12 , and a power ring  14 . From  FIG. 1B , the core circuit  10  is composed of an ion distributing layer  100 , a polysilicon layer  102 , a first metal layer  104 , a second metal layer  106 , a third metal layer  108 , and a fourth metal layer  110 . 
         [0006]    In SOC, because the change of operation status of the integrated circuit and the influence of the coupled capacitors between circuits, the power source oscillates varying. The unstable power source makes the voltage exceeded the range of the timing model and then the reliability of the circuit is reduced. As the circuit is developed to the deep sub-micron, the oscillation of the power source will probably make the transistor operates deviated from the normal saturation area, and the circuit function is failed. In the deep sub-micro of SOC, the dimension of the embedded memory occupies the chip area becoming higher. Therefore, the stable power source can increase the stability of the embedded memory, so that the yield rate of the SOC increases. 
       SUMMARY OF THE INVENTION 
       [0007]    In order to solve the problem of the power source being unstable in the embedded memory of the prior art, a device for enhancing the stability of the power source of the embedded memory in integrated circuit and a method are disclosed. 
         [0008]    One particular aspect of the present invention is to enhance the stability of the power source of the embedded memory in integrated circuit, without changing the circuit layout of the SOC. 
         [0009]    The device for enhancing the stability of the power source of the embedded memory in integrated circuit includes a core circuit, a metal-oxide semiconductor (MOS) capacitor, and a metal-insulator-metal (MIM) capacitor. One end of the core circuit is connected with a power source ring, and a second end of the core circuit is connected with a grounding ring. The metal-oxide semiconductor (MOS) capacitor is connected with the power source ring, and is in parallel with the core circuit. The metal-insulator-metal (MIM) capacitor is connected with the power source ring, and is in parallel with the core circuit and the MOS capacitor. Thereby, by utilizing the metal-oxide semiconductor (MOS) capacitor and the metal-insulator-metal (MIM) capacitor, the stability of the power source is enhanced. 
         [0010]    The present invention also provides a layout method for enhancing the stability of the power source of the embedded memory. The embedded memory includes a first metal layer, a polysilicon layer, an ion distributing layer, a fourth metal layer, a second metal layer and a third metal layer. The layout method includes forming a core circuit on the first metal layer, the polysilicon layer, the ion distributing layer, the second metal layer, the third metal layer and the fourth metal layer. A grounding ring and a power source ring are patterned on an additional area of the fourth metal layer. At least one metal-oxide semiconductor (MOS) capacitor is located below the grounding ring and the power source ring. A metal-insulator-metal (MIM) capacitor is formed between the fifth metal layer and the sixth metal layer. 
         [0011]    By adding the metal-oxide semiconductor (MOS) capacitor and the metal-insulator-metal (MIM) capacitor into the embedded memory, the stability of the power source ring is enhanced, and the voltage of the embedded memory is stabilized. Furthermore, the power source for the peripheral circuit of the embedded memory is also stabilized. The reliability of the SOC is enhanced. 
         [0012]    For further understanding of the invention, reference is made to the following detailed description illustrating the embodiments and examples of the invention. The description is for illustrative purpose only and is not intended to limit the scope of the claim. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    The drawings included herein provide a further understanding of the invention. A brief introduction of the drawings is as follows: 
           [0014]      FIG. 1A  is a top view of the circuit layout of the embedded memory of the prior art; 
           [0015]      FIG. 1B  is a cross-section view of the circuit layout of the embedded memory of the prior art; 
           [0016]      FIG. 2A  is a schematic diagram of the embedded memory of an embodiment of the present invention; 
           [0017]      FIG. 2B  is a cross-section view of the circuit layout of the embedded memory of an embodiment of the present invention; and 
           [0018]      FIG. 3  is a flow chart of the manufacturing method for the embedded memory circuit of an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0019]    In SOC, an unstable power source will reduce the reliability of the circuit. As the circuit manufacturing process has been developed to the deep sub-micron, the oscillation range of the power source may make the transistor depart from the saturation area of a normal operation so that the circuit function fails. In a deep sub-micron chip, the dimension of the embedded memory occupied the chip area becomes more and more large. A stable power source will enhance the reliability of the embedded memory and increase the yield rate of the chips. The present invention provides an embedded memory structure that can improve the reliability of the embedded memory affected by the unstable power source, and prevent the data from damaged. 
         [0020]    Reference is made to  FIGS. 2A and 2B .  FIG. 2A  is a schematic diagram of the embedded memory of an embodiment of the present invention.  FIG. 2B  is a cross-section view of the circuit layout of the embedded memory of an embodiment of the present invention. The embedded memory device includes a power source ring  20 , a grounding ring  22 , a core circuit  24 , a metal-insulator-metal capacitor  26  and a MOS (metal-oxide-semiconductor) capacitor  28 . The core circuit  24  is surrounded by the grounding ring  22  and the power source ring  20  in turn. The metal-insulator-metal capacitor  26  is formed above the core circuit  24 , and the MOS capacitor  28  is formed under the grounding ring  22  and the power source ring  20 . 
         [0021]    According to  FIG. 2B , the layout of the embedded memory is manufactured by the integrated circuit manufacturing process, and the embedded memory includes an ion distributing layer  30 , a polysilicon layer  32 , a first metal layer  34 , a second metal layer  36 , a third metal layer  38 , a fourth metal layer  40 , a fifth metal layer  42 , and a sixth metal layer  44 . 
         [0022]    The core circuit  24  is formed by stacking the ion distributing layer  30 , the polysilicon layer  32 , the first metal layer  34 , the second metal layer  36 , the third metal layer  38  and the fourth metal layer  40 . The ion distributing layer  30  and the polysilicon layer  32  are formed most based electrical devices in the core circuit  24  such as transistors and diodes. The terminals of above electrical devices (the transistor and the diode) can be connected by the first metal layer  34  and the second metal layer  36 . The power source ring  20  and the grounding ring  22  are located on the fourth metal layer  40 . 
         [0023]    Reference is made to  FIGS. 2B and 3 .  FIG. 3  is a flow chart of the manufacturing method for the embedded memory circuit of an embodiment of the present invention. The present invention utilizes the initial design of the circuit layout and the embedded memory structure to design the metal-insulator-metal capacitor (MIM) deposited on the core circuit of the embedded memory and the MOS capacitor (MOSCAP) below the grounding ring and the power source ring. Thereby, the reliability of the embedded memory for the unstable power source is improved. The manufacturing process for the embedded memory is described as below. 
         [0024]    Firstly, an ion distributing layer  30 , a polysilicon layer  32  and a first metal layer  34  are formed (S 100 ) in turn. Because the location of the MOS capacitor  28  has been mapped out in the initial circuit layout, the MOS capacitor  28  also is formed at the same time when the ion distributing layer  30 , the polysilicon layer  32  and the first metal layer  34  are taken shape (S 102 ). Next, a second metal layer  36 , a third metal layer  38  and a fourth metal layer  40  are formed in turn (S 104 ). The fourth metal layer  40  is patterned to form a grounding ring  22  and a power source ring  20  (S 106 ). At this time, from a top view, the embedded memory structure is mapped out into three parts including the core circuit, the grounding ring and the power source ring, and the grounding ring and the power source ring surround around the core circuit. 
         [0025]    The core circuit is formed by stacking the ion distributing layer  30 , the polysilicon layer  32 , the first metal layer  34 , the second metal layer  36 , the third metal layer  38  and the fourth metal layer  40 . The ion distributing layer  30  and the polysilicon layer  32  are formed most based electrical devices in the core circuit  24  such as transistors and diodes. The terminals of above electrical devices (the transistors and the diodes) can be connected together by the first metal layer  34  and the second metal layer  36 . The additional space (location), including three layer structure of the ion distributing layer  30 , the polysilicon layer  32  and the first metal layer  34 , below the grounding ring  22  and the power source ring  20  planned in advance is utilized to be the MOS capacitor  28 . 
         [0026]    Next, a fifth metal layer  42  is deposited on the fourth metal layer  40 , a specified metal layer  260  is formed on the fifth metal layer  42 , and a sixth metal layer  44  is formed on the specified metal layer  260  (S 108 ). This means that the specified metal layer  260  is located between the fifth metal layer  42  and the sixth metal layer  44  so that the fifth metal layer  42 , the specified metal layer  260  and the sixth metal layer  44  compose of a metal-insulator-metal capacitor (S 110 ). The specified metal layer  260  is close to the fifth metal layer  42 . Thereby, the MOS capacitor  28  is added below the power source ring  20  and the grounding ring  22  located at the rim of the embedded memory, and the metal-insulator-metal capacitor  26  is added above the core circuit of the embedded memory to increase the stability of the embedded memory for the power source. 
         [0027]    The present invention adds the MOS capacitor  28  and the metal-insulator-metal capacitor  26  into the embedded memory of the SOC chip. Therefore, the present invention does not need to substantially change the layout of the embedded memory just to utilize the three layer structure (the ion distributing layer  30 , the polysilicon layer  32 , the first metal layer  34 ) and between the fifth metal layer  42  and the sixth metal layer  44  to dispose the MOS capacitor  28  and the metal-insulator-metal capacitor  26  on the additional space respectively. Thereby, the stability of the power source ring  20  is enhanced, and the voltage of the embedded memory is stabilized. Furthermore, the power source for the peripheral circuit of the embedded memory is also stabilized, and the reliability of the SOC is enhanced. 
         [0028]    The description above only illustrates specific embodiments and examples of the invention. The invention should therefore cover various modifications and variations made to the herein-described structure and operations of the invention, provided they fall within the scope of the invention as defined in the following appended claims.