Abstract:
A common-mode shifting circuit for shifting the common-mode output voltage of a CML device to an arbitrary voltage is disclosed. A constant current source is provided at each output of the CML device. The constant current may be a positive or negative current, tending to raise or lower the common-mode output voltage, respectively. The constant current sources are preferably connected to an alternate voltage supply having a higher voltage than that the supply for the CML device. The invention further provides a method for adjusting the output signal of a current-mode logic circuit having two or more output ports, comprising the step of providing a constant current at each output port of the current-mode logic circuit, whereby the common-mode voltage at the output ports of said current-mode logic circuit is level-shifted.

Description:
CROSS-REFERENCES  
       [0001]     This application claims the benefit of U.S. Provisional Application No. 60/590,624, filed Jul. 23, 2004. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention relates generally to signal levels in current-mode logic circuits, especially in high-speed input/output interface circuits.  
       BACKGROUND OF THE INVENTION  
       [0003]     In high-speed communications equipment, e.g., optical transceivers or high-speed input-output (I/O) interface circuits, current-mode logic (“CML”) buffers are frequently employed to drive off-chip resistive loads. CML buffers generally are able to operate from relatively low power supplies and achieve very fast switching high speeds, e.g., greater than a gigahertz or several tens of gigahertz. Further, because CML buffers use differential signaling, they are relatively insensitive to common-mode noise.  
         [0004]     A conventional CML buffer circuit is shown in  FIG. 1 . CML buffer  100  includes two local (on-chip) 50-ohm resistors R 1  and R 2 , two input transistors Q 1  and Q 2 , and a “tail current” transistor Q 3 . As shown in  FIG. 1 , resistors R 1  and R 2  are connected between a supply voltage VDDO and the current-supply (or “drain”) terminals of transistors Q 1  and Q 2 , respectively. The current-sink (or “source”) terminals of transistors Q 1  and Q 2  are connected together at node A to the current-supply terminal of transistor Q 3 . Finally, the current-sink terminal of transistor Q 3  is connected to ground.  
         [0005]     Conventionally, CML buffer  100  has a differential input signal, formed from two single-ended signals DATA and DATA_B applied respectively to the control terminal (“gate”) of transistors Q 1  and Q 2 . In accordance with the differential signaling approach, input signals DATA and DATA_B have opposite polarities. CML buffer  100  further has two outputs OUT_B and OUT, which similarly form a differential signal. The outputs OUT_B and OUT of the CML buffer are further connected to off-chip resistors R 3  and R 4 , that represent the termination impedance of a chip that receives the differential output signal.  
         [0006]     In operation, a constant bias current I B  is introduced to the CML buffer by transistor Q 3 . Current I B  is predetermined and set by the bias level of the I B  current source transistor. As is well-known in the art, current I B  is provided by transistor Q 3  via a current mirror connection.  
         [0007]     By means of input signals DATA and DATA_B, current I B  is steered either to the left branch formed by resistor R 1  and transistor Q 1  or to the right branch formed by resistor R 2  and transistor Q 2 . For example, if input signal DATA is a logical value “one,” or “high,” while input signal DATA_B is a logical value “zero,” or “low,” the current through transistor Q 1  will increase and the current through transistor Q 2  will decrease (though not so much as to put transistor Q 1  or Q 2  in a cut-off or active state). Accordingly, because more current flows through resistor R 1 , a voltage drop across resistor R 1  will develop, and the output OUT_B will take on a “low” value. At the same time, because less current flows through resistor R 2 , the voltage drop across resistor R 2  will decrease, and output OUT will take on a “high” value. Alternatively, if input signal DATA is a logical “zero” signal, then current is steered through the right branch, and output OUT_B will take on a “high” value while output OUT takes on a “low” value.  
         [0008]     In this conventional CML buffer, and with reference to  FIG. 2 , the voltage swing of each output signal (i.e., at outputs OUT and OUT_B) is from a maximum output voltage V OH  ( 210  in  FIG. 2 ) of approximately the supply voltage V DDO  (also  210  in  FIG. 2 ), down to a minimum output voltage V OL  ( 230  in  FIG. 2 ) obtained by subtracting the voltage drop across resistor R 2  or R 4  from V DDO . The average value of the output signal (e.g., at output OUT) represents the “common-mode voltage” V CM  of the output signal ( 220  in  FIG. 2 ). Common-mode voltage V CM  may be approximated by assuming equal current flow through the left branch and the right branch, with the following resultant circuit equation: 
 
 V   CM   =V   DDO −( R   2 + R   4 )/2 *I   B /2, 
 
 where V CM  is the common-mode voltage, V DDO  is the supply voltage, R 2  is the on-chip resistance, R 4  is the off-chip resistance, and I B  is the tail current. For example, for R 1 =R 2 =R 3 =R 4 =50 ohms, V DDO =1.2 ohms and I B =20 mA, the resulting common-mode voltage V CM  would be 0.95 volts, which is relatively high (i.e., close to the supply voltage V DDO ). In addition, the peak-to-peak voltage V pk  of the output signal ( 250  in  FIG. 2 ) is the voltage at the highest output level V OH  minus the voltage at the lowest output level V OL . Maximum output voltage V OH  is approximately the supply voltage V DDO  (i.e., about 1.2 volts when transistor Q 2  is “off”). Minimum output voltage V OL  (when transistor Q 2  is “on”) may be determined as follows: 
 
 V   OL   =V   DDO −( R   2 * R   4 )/( R   2 + R   4 )* I   B  
 
 where V OL  is the voltage of the output signal OUT at its lowest output level, V DDO  is the supply voltage, R 2  and R 4  are the on-chip and off-chip load resistances, respectively, and I B  is the tail current. For the values used above, where R 2 =R 4 =50 ohms, and I B =20 mA, the resulting minimum output voltage V OL  would be 0.7 V. Thus, the peak-to-peak voltage V pk  would be V OH −V OL , or 1.2V−0.7 V=0.5 volts. 
 
         [0009]     A significant problem arises, however, when a CML buffer is connected to a receiver through a DC blocking capacitor (known as “AC coupling mode”). Such a connection is shown in  FIG. 3 . DC blocking capacitors C 1  and C 2  pass the AC part of the output signals at outputs OUT_B and OUT, but block the DC part of the signal. When the outputs OUT_B and OUT are AC coupled, the dynamic (AC) part of the signal “sees” the local 50-ohm resistance of resistor R 1  or resistor R 2  in parallel with the remote 50-ohm impedance of resistors R 3  or R 4 , resulting in an equivalent AC impedance of 25 ohms for each output. Meanwhile, the DC part of the signal (i.e., the DC common-mode voltage) “sees” only the 50-ohm local impedance of resistor R 1  or resistor R 2 . The relatively high 50-ohm impedance seen by the DC part gives rise to a relatively high voltage drop (or “IR” drop) of the common-mode voltage. Indeed, the DC impedance (50 ohms) is twice that of the AC equivalent impedance (25 ohms).  
         [0010]     The common-mode voltage, maximum output level, and minimum output level for an AC-coupled CML buffer may be calculated in a similar manner as above. The common-mode voltage is: 
 
 V   CM   =V   DDO   −R   2 * I   B /2=1.2  V *50 ohms*20 mA /2=0.7 V. 
 
 Assuming that C 1  and C 2  are large, the peak-to-peak voltage from an AC standpoint is about the same as above, or 0.5 V. Because the AC voltage is superimposed on the lower DC common-mode voltage of 0.7 V, the maximum output voltage V OH  here is 0.95 V and the minimum output voltage V OL  is 0.45 V. The various voltages for the AC-coupled case are depicted graphically in  FIG. 4 . It may be seen from  FIG. 4  that the AC differential signals at outputs OUT_B and OUT swing about the common-mode voltage V CM  ( 430  in  FIG. 4 ), up to V OH  ( 420  in  FIG. 4 ) and down to V OL  ( 440  in  FIG. 4 ) relative to ground  450 . 
 
         [0011]     It is clear from the foregoing that in the AC-coupled CML buffer, the DC common-mode output signal is significantly lower than in the DC-coupled case, while the AC output signal remains the same. The large downward shift in the common-mode voltage V CM  negatively impacts the AC output signal, however, by limiting the headroom or voltage swing that is available. As a result, at low power supply voltages (for example, 1.2 volts or less), “clipping” or distortion of the output signal may occur. More particularly, in a CML buffer it is preferable to operate both the input transistors Q 1  and Q 2  and the tail-current transistor Q 3  in saturation mode. The very low level of the minimum output voltage V OL  (0.45 V), however, causes these transistors to tend to operate in active or cut-off mode, causing distortion or clipping.  
         [0012]     One possible solution to the distortion problem caused by the lower common-mode voltage in AC-coupled CML devices is to increase the width to length ratio of transistors Q 1 , Q 2  and Q 3 , so that they are kept in saturation mode even for relatively low common-mode voltages. In practice, however, the benefit of a high W/L ratio must be balanced against the parasitic capacitance of the devices, which increases as the W/L ratio increases and which tends to reduce the switching frequency of the devices. Thus, it would be desirable to provide an AC-coupled CML buffer that does not suffer from the low-common-mode voltage problem described above and that may operate at high frequencies.  
       SUMMARY OF THE INVENTION  
       [0013]     Briefly described, the invention is a current-mode level-shifting circuit that can shift the common-mode output voltage of a CML device to an arbitrary voltage, preferably close to the voltage of the power supply rails. The circuit provides a common-mode output voltage that is well-suited for operation with low-voltage power supplies. In accordance with the invention, a constant current is provided at each output, respectively, of the CML device via a constant current source. If the constant current at each output is a positive current flowing into the output, the common-mode output voltage will be raised. Alternatively, if the constant current at each output is a negative current flowing out from the output, the common-mode voltage will be lowered. Preferably, the constant currents provided at the outputs are approximately the same. The constant current sources may be implemented as PMOS transistors biased to a condition sufficient to provide a current adequate to raise the common-mode voltage.  
         [0014]     Thus, the invention may broadly be described as a current-mode shifting circuit, comprising a current-mode logic circuit having two input ports and two output ports having a common-mode voltage; and two constant-current sources, each connected respectively between the two output ports of said current-mode logic circuit and a first supply voltage. The constant-current sources produce currents at the output ports that shift the common-mode voltage at the output ports. In one embodiment, the first supply voltage is greater than the common-mode voltage at the output ports, such the constant current sources inject current into the output ports and thereby raise the common-mode voltage. Alternatively, the first supply voltage may be less than the common-mode voltage at the output ports, such that the constant current sources sink current from the output ports and thereby lower the common-mode voltage. The current-mode shifting circuit may further comprise two DC block capacitors, each connected respectively to the two output ports of the current-mode logic circuit, and capable of connection to a load termination.  
         [0015]     In a further embodiment, the current-mode logic circuit is connected to a second supply voltage. Preferably, the first supply voltage (connected to the current sources) is equal to or greater than the second supply (connected to the current-mode logic circuit). The constant-current sources may then inject sufficient current into the output ports to raise the common-mode voltage at each output port to a sufficiently high value that the peak voltage at each output port of the current-mode logic circuit is greater than the first power supply voltage. It may still further include load resistors connected between the current sources and the output ports of the current-mode logic circuit. In this embodiment, it is also preferable to provide two resistors connected in series with the current sources. These resistors act as current-limiting resistors and buffer the current sources from output fluctuations.  
         [0016]     The invention further provides a method for adjusting the output signal of a current-mode logic circuit having two output ports and connected to a first supply voltage. The method comprises the step of providing a constant current at each output of the current-mode logic circuit, whereby the common-mode voltage at the output ports of the current-mode logic circuit is level-shifted. The constant current may be a negative current flowing out of each output port, thus lowering the common-mode voltage, or may be a positive current flowing into each output port, thus raising the common-mode voltage. In this latter embodiment, the constant current injected at each output port preferably raises the common-mode voltage to a sufficiently high value that the peak voltage at each output port of the current-mode logic circuit is greater than the first power supply voltage. The method preferably also includes passing the constant current at each output port through a series resistor.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]     Various embodiments of the present invention will now be described in detail in conjunction with the annexed drawings, in which:  
         [0018]      FIG. 1  is a circuit diagram of a prior art CML circuit having DC-coupled output terminations.  
         [0019]      FIG. 2  is a graph depicting various voltages in the circuit shown in  FIG. 1 ;  
         [0020]      FIG. 3  is a circuit diagram of a prior art CML circuit having AC-coupled output terminations  
         [0021]      FIG. 4  is a graph depicting various voltages in the circuit shown in  FIG. 3 ;  
         [0022]      FIG. 5  is a circuit diagram of a current-mode shifting circuit in accordance with the invention;  
         [0023]      FIG. 6  is a graph depicting various voltages in the circuit shown in  FIG. 5 ;  
         [0024]      FIG. 7  is a circuit diagram of a preferred embodiment of the current-mode shifting circuit shown in  FIG. 5 ;  
         [0025]      FIG. 8  is a circuit diagram of another embodiment of the current-mode shifting circuit in accordance with the present invention; and  
         [0026]      FIG. 9  is a circuit diagram of still another embodiment of the current-mode shifting circuit in accordance with the present invention.  
     
    
     DETAILED DESCRIPTION  
       [0027]     A current-mode shifting circuit in accordance with the present invention is shown in  FIG. 5 . Similarly to CML buffer  100  described above, current-mode shifting circuit  500 , includes two local (on-chip) 50-ohm resistors R 1  and R 2 , two input transistors Q 1  and Q 2 , and a “tail current” transistor Q 3 . Resistors R 1  and R 2  are connected between supply voltage V DDO  and the current-supply (or “drain”) terminals of transistors Q 1  and Q 2 , respectively. The current-sink (or “source”) terminals of transistors Q 1  and Q 2  are connected together at node A to the current-supply terminal of transistor Q 3 . The current-sink terminal of transistor Q 3  is connected to ground. In accordance with one embodiment of the invention, current-mode shifting circuit  500  further includes two constant-current sources CS 1  and CS 2 , each connected respectively to the two outputs OUT_B and OUT of current-mode logic circuit  500 .  
         [0028]     Like CML buffer  100  described above, current-mode shifting circuit  500  receives a differential input signal, formed from two single-ended signals DATA and DATA_B applied respectively to the control terminal (“gate”) of transistors Q 1  and Q 2 , where input signals DATA and DATA_B have opposite polarities. Current-mode shifting circuit  500  further has two outputs OUT_B and OUT, which similarly form a single differential signal. The outputs OUT_B and OUT of the CML buffer are connected to off-chip resistors R 3  and R 4 , representing the load impedance of a chip that receives the differential output signal, through DC blocking capacitances C 1  and C 2 .  
         [0029]     Current-mode shifting circuit  500  operates as follows. Like CML buffer  100 , transistor Q 3  in current-mode shifting circuit  500  provides an unswitched, constant bias current I B , that causes input transistors Q 1  and Q 2  to operate in their saturation regions. By means of input signals DATA and DATA_B. current I B  is steered either to the left branch formed by resistor R 1  and transistor Q 1  or to the right branch formed by resistor R 2  and transistor Q 2 , as described above in connection with CML buffer  100 . Thus, for example, if input signal DATA is a logical value “one,” or “high,” while input signal DATA_B is a logical value “zero,” or “low,” the current through transistor Q 1  increases while the current through transistor Q 2  decreases (though not so much as to put transistor Q 1  or Q 2  in their cut-off or active states). Accordingly, because more current flows through resistor R 1 , a voltage drop develops across resistor R 1 , and the output OUT_B takes on a “low” value. At the same time, because less current flows through resistor R 2 , the voltage drop across resistor R 2  decreases, and output OUT takes on a “high” value. Alternatively, if input signal DATA is a logical “zero” signal, then current is steered through the right branch, and output OUT_B takes on a “high” value while output OUT takes on a “low” value.  
         [0030]     In accordance with the present invention, constant current sources CS 1  and CS 2  simultaneously supply constant DC currents I C1  and I C2  to outputs OUT_B and OUT, respectively. These DC currents (I C1  and I C2 ) have the effect of sourcing some of the current demanded by transistor Q 3 , such that the currents through resistors R 1  and R 2  are correspondingly reduced (i.e., in the amount I C1  or I C2 ). More specifically, with the addition of constant current sources CS 1  and CS 2 , the common-mode currents through resistors R 1  and R 2  take the value I B /2−I C1  and I B /2−I C2 , respectively. As a result, because the voltage drop across resistors R 1  and R 2  is a function of the current passing through them, and because the common-mode voltages at outputs OUT_B and OUT are themselves determined by those voltage drops, the common-mode voltages at outputs OUT_B and OUT tend to increase proportionally as a function of I C1  and I C2 . Indeed, due to the effects of electromagnetic coupling (both inductive and capacitive), the output signals at outputs OUT_B and OUT may even be caused to swing above the supply voltage V DDO . Advantageously, because currents I C1  and I C2  are direct currents, rather than alternating currents, they do not pass through DC blocking capacitors C 1  and C 2  and thus have no effect on the peak-to-peak amplitude of the AC output signals.  
         [0031]     The various voltages in this embodiment of the present invention are depicted in  FIG. 6 . It may be seen that the common-mode voltage V CM  ( 630  in  FIG. 6 ) is adjustable, depending on the value of the constant currents I C1  and I C2 . The voltage swing of each output signal (i.e., at outputs OUT and OUT_B) is from a maximum output voltage V OH  ( 610  in  FIG. 6 )—which may be greater than the supply voltage V DDO  ( 620  in  FIG. 6 )—down to a minimum output voltage V OL  ( 640  in  FIG. 6 ), all with reference to ground  650 . The peak-to-peak amplitude V pk  of the AC output signal ( 660  in  FIG. 6 ) remains the same as with the convention CML circuit described above, but is shifted up with the common-mode voltage.  
         [0032]     Constant current sources CS 1  and CS 2  need not be implemented in any specific configuration, provided that each maintains a constant current notwithstanding the various voltages that may be present in common-mode shifting circuit  500 . As an example, in  FIG. 7  constant current source CS 1  is implemented as a PMOS transistor Q 5  in a current-mirror configuration with PMOS transistor Q 4 , wherein the current-supply (“drain”) terminals of transistors Q 4  and Q 5  are connected to supply voltage V DDO  and the control terminals (“gates”) of transistors Q 4  and Q 5  are connected to each other and to the current-sink terminal (“source”) of transistor Q 4 , and down to ground through reference current source I ref . Thus, current I C1  is predetermined and in essence set by the bias level of control terminal of transistor Q 5 . Constant current source CS 2  may be implemented similarly. Preferably, currents I C1  and I C2  are as large as possible, so that the common-mode voltage is raised to the greatest extent possible, but not so large as to cause transistors Q 5  and Q 6  to fail to operate in saturation mode.  
         [0033]      FIG. 8  depicts an alternative embodiment of the invention in which each constant current source CS 1  and CS 2  is connected to an additional voltage supply V AA . In this configuration, if voltage supply V AA  has a greater voltage than voltage supply V DDO  (e.g., V AA =2.5V), then the common mode voltage at outputs OUT and OUT_B may be raised to a voltage that approaches that of voltage supply V DDO . The increased common mode voltage provides additional voltage headroom in the circuit, so that transistors Q 1 , Q 2 , and Q 3  may be more easily kept in saturation mode. Additionally, with the additional headroom provided by supply voltage V AA , transistors Q 5  and Q 6  may be made quite small relative to transistors Q 1 , Q 2  and Q 3  without causing transistors Q 5  and Q 6  not to operate in saturation mode. Advantageously, the use of the additional supply voltage V AA  has little or no impact on the total power consumption by current-mode shifting circuit  500 , because the total DC tail current I B  remains the same.  
         [0034]     Preferably, two additional resistors R 5  and R 6  are added in series with constant current sources CS 1  and CS 2 , in order to isolate the outputs OUT and OUT_B from the parasitic capacitance created by transistors Q 5  and Q 6  in constant current sources CS 1  and CS 2 , respectively. Without these resistors, the parasitic capacitances of transistors Q 5  and Q 6  tend to reduce the switching speed of current-mode shifting circuit  500  and to create impedance mismatch with the load terminations represented by resistors R 3  and R 4 . The resistance of the additional resistors R 5  and R 6  may be of any value sufficient to satisfy the overall switching speed specifications or output impedance requirements of the circuit.  
         [0035]      FIG. 9  depicts an alternative embodiment of the invention, in which current sources CS 1  and CS 2  are connected between the outputs OUT_B and OUT, respectively, and a supply voltage that is lower than the common-mode voltage at outputs OUT_B and OUT. For example, as shown in  FIG. 9 , current sources CS 1  and CS 2  may be connected to ground. In this embodiment, constant current sources CS 1  and CS 2  act as constant current sinks that pull down or lower the common mode voltage at outputs OUT_B and OUT, respectively.  
         [0036]     The invention may be used with bipolar or BiCMOS technologies, rather than CMOS process technology as depicted. The transistors may also be of opposite type as that described above (e.g., p-type transistors instead of n-type). Further, AC output terminations may be made to either V DD , V SS  or ground. The invention further may be applied to DC-coupled CML circuits in addition to AC-coupled circuits.  
         [0037]     There has thus been described a current-mode shifting circuit capable of producing a high-speed communication signal with an improved common-mode voltage. It will be understood, however, that the foregoing description of the invention is by way of example only, and variations will be evident to those skilled in the art without departing from the scope of the invention, which is as set out in the appended claims.