Abstract:
A metal-insulator-metal capacitor for improved mixed-mode capacitor in a logic circuit of a semiconductor device is disclosed. The bottom electrode of the capacitor is polycide and the top electrode is metal formed by damascene technology. The middle layer of the capacitor is a dielectric layer formed by using a chemical vapor deposition method. The voltage coefficient of this capacitor is approximate to zero.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an embedded capacitor fabrication and, more particularly, to a method for forming a metal-insulator-metal capacitor in logic circuit. 
     2. Description of the Prior Art 
     In the field of integrated circuits, it is preferable to form circuit elements in the smallest achievable surface area in order to realize a high degree of circuit complexity into a small integrated circuit chip size, resulting in low cost per function. The mixed-mode process can provide a process flow with embedded capacitor in logic circuit. The addition of a capacitor can be used for an RC analog circuit or other special applications 
     Referring to FIG. 1, a metal-oxide-semiconductor field effect transistor having a gate  14 C, gate oxide  14 D, drain  14 B and source  14 A is formed in and on a substrate  10 . Further, a bottom electrode  20  of capacitor is formed on a field oxide region  12 . Dielectric layer  21  and top electrode  22  are formed in sequence. Then, after interlevel dielectric layer  30  is formed on the semiconductor device, contact  32  is formed in the interlevel dielectric layer  30 . 
     For a conventional mixed-mode process, the material of top electrode  22  and bottom electrode  20  is polysilicon. However, the polysilicon depletion will cause the different capacitance values under different bias voltage, as shown in FIG.  2 . 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, a method is provided for forming a metal-insulator-metal capacitor that can effectively solve the unstable capacitance problem of poly capacitor. 
     It is another object of the present invention that the excellent global planarization can also be achieved with this method 
     In one embodiment, the bottom electrode of the capacitor is formed on a field oxide region first. Then, an interlevel dielectric layer is deposited on the semiconductor device and a portion of the interlevel dielectric layer is then etched Next, having formed a dielectric layer of the capacitor on said bottom electrode, a metal layer is deposited on the dielectric layer Finally, the excess metal layer above the interlevel dielectric layer is removed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein: 
     FIG. 1 shows a cross-sectional view illustrative of a traditional mixed-mode capacitor. 
     FIG. 2 shows a prior relationship diagram between capacitance and bias voltage. 
     FIG. 3 is a flow diagram showing the steps for forming a metal-insulator-metal capacitor according to the present invention. 
     FIGS. 4A to  4 D show cross-sectional views illustrative of various stages in the fabrication of a metal-insulator-metal capacitor according to the present invention. 
     FIG. 5 shows a relationship diagram between capacitance value and bias voltage. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The following is the detailed description of this invention. Referring to FIG. 3, a flow diagram showing the steps for forming a metal-insulator-metal capacitor in accordance with this disclosure is shown First, a semiconductor device is provided and a metal-oxide-semiconductor field effect transistor is formed Then, after forming a bottom electrode of the capacitor on a field oxide region, a salicide process is performed A first interlevel dielectric layer is then formed on the semiconductor device Next, a portion of the first interlevel dielectric layer is etched back such that the dielectric layer of the capacitor can be formed on the bottom electrode. A barrier metal layer and metal layer are deposited in sequence and the excess metal layer is etched back by using chemical mechanical polishing to reach global planarization Then, a second interlevel dielectric layer having been deposited on the semiconductor device, contact is formed in the interlevel dielectric layers Suitable conditions for performing the various steps set forth in FIG. 3 are set forth below and will be explained by reference to FIGS. 4A to  4 D. 
     Referring to FIG. 4A, a metal-oxide-semiconductor field effect transistor (MOSFET) having a gate  114 C, a gate oxide  114 D, a drain  114 B and a source  114 A is conventionally formed in and on the substrate  100 . The field oxide region  112  under capacitor (formed by the following steps) is used for isolating the capacitor and transistor Another way to isolate the capacitor and transistor may use shallow trench isolation (STI). The field oxide region  112  is formed by using any conventional method such as thermal oxide process or Local Oxidation (LOCOS) process and the thickness of field oxide region  112  is about from 2000 to 6000 angstroms. A bottom electrode  120  is conventionally formed on the field oxide region  112  by depositing polysilicon and then via salicide process. The thickness of this bottom electrode  120  is about from 500 to 3000 angstroms. 
     A first interlevel dielectric layer  130  is conventionally formed on the semiconductor device, as shown in FIG.  4 B. Then, the interlevel dielectric layer  130  is global planarized by using a chemical mechanical polishing method. The following step is damascene technology to form top electrode of the capacitor. 
     Referring to FIG. 4C, a portion of interlevel dielectric layer  130  is etched by using a conventional method Then, a dielectric layer  128  is formed first on the bottom electrode  120 . The materials of the dielectric layer  128  may be silicon oxide, silicon nitride, silicon oxynitride, or tantalum oxide. Silicon oxide, silicon nitride and silicon oxynitride may be formed by using low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD), and also may be formed by using high density plasma CVD. Moreover, tantalum oxide is also formed by using a conventional CVD method such as LPCVD. The thickness of this dielectric layer  128  is about from 100 to 500 angstroms. 
     A barrier metal layer  121  is formed by using a conventional sputtering method. The materials of this layer  121  are titanium and titanium nitride (Ti/TiN). Then, a metal layer  122  is formed by using any suitable conventional method The materials of this layer  122  may be tungsten or copper. Referring to FIG. 4D, the excess metal layers  121  and  122  above interlevel dielectric layer  130  will be removed by using a conventional chemical mechanical polishing method. 
     Referring to FIG. 4E, a second interlevel dielectric layer is formed on the semiconductor device by using the same method as the first interlevel dielectric layer  130 . The thickness of this layer  131  is about 4000 to 40000 angstroms. Then, any suitable conventional methods that can form contact  132  in interlevel dielectric layers  130  and  131  are preformed to connect top electrode  122 , bottom electrode  120  and drain  114 B. 
     Referring to FIG. 5, a relationship diagram between capacitance value and bias voltage is shown. Because the material of the electrode in this capacitor is metal, no depletion is present and the capacitance value is approximate to constant under different bias voltages. 
     Although specific embodiments have been illustrated and described, it will be obvious to those skilled in the art that various modifications may be made without departing from what is intended to be limited solely by the appended claims.