Abstract:
A bidirectional AC-DC converter is presented with reduced passive component size and common mode electro-magnetic interference. The converter includes an improved input stage formed by two coupled differential inductors, two coupled common and differential inductors, one differential capacitor and two common mode capacitors. With this input structure, the volume, weight and cost of the input stage can be reduced greatly. Additionally, the input current ripple and common mode electro-magnetic interference can be greatly attenuated, so lower switching frequency can be adopted to achieve higher efficiency.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application No. 61/812,969, filed on Apr. 17, 2013. The entire disclosure of the above application is incorporated herein by reference. 
    
    
     GOVERNMENT CLAUSE 
     This invention was made with government support under grant number DE-EE0002720 awarded by the Department of Energy. The government has certain rights in this invention. 
    
    
     FIELD 
     The present disclosure relates to single phase bi-directional AC-DC converter with reduced passive components size and common mode electro-magnetic interference. 
     BACKGROUND 
     Vehicle to grid (V2G) technology is expected to be commercialized in the near future. V2G uses the battery in vehicles as energy storage units for power system. It can help balance loads by valley filling and peak shaving. As an energy buffer stage, it will be very helpful for renewable power source, such as wind and solar power, by storing the excess energy during high power output period and providing it back at high load period. To realize the V2G function, a bi-directional on-board charger which can exchange energy between the power grid and a battery is needed. As the on-board charger transfers energy from the alternating current (AC) power system to direct current (DC), a low power factor charger will draw larger current from the power grid than a high power factor one for the same amount of real power consumed. The extra current means energy circulating which brings extra loss as well as the need of larger system capacity. Thus, a power factor correction (PFC) converter is a necessary front stage in medium to high power applications for the on-board charger. The above two reasons require a bi-directional AC-DC converter with PFC function for the on-board charger. 
     For an electric vehicle charger in SAE AC level 2, the input single phase AC power can be up to 19.2 kW. At this power level, the traditional topology with one inductor at the input stage will be bulky and expensive. However, if a smaller inductor is chosen, the input current harmonics will increase which needs a bigger EMI filter to meet the regulations. If higher switching frequency is adopted to reduce the input current ripple, it means more switching loss and lower efficiency. 
     For the on-board charger, size and weight is an important factor because the vehicle will always carry the charger. Efficiency is also very important because the energy will be transferred from power source to battery first and then from battery to load again. Every transfer wastes some energy. Low efficiency means huge energy waste. To achieve compact and efficient, there is a need to reduce the passive component size without increasing the switching frequency (the efficiency usually decrease when switching frequency increases). 
     In this disclosure, a high order input filter for the AC-DC converter is proposed, such that the passive component size can be reduced. The filter integrates both the differential and common mode function and the common mode EMI problem is solved easily. To control a converter with the proposed input filter topology, a model based method with reduced calculation and measurement is also developed, which makes fast and robust performance and low control cost at the same time. 
     This section provides background information related to the present disclosure which is not necessarily prior art. 
     SUMMARY 
     This section provides a general summary of the disclosure, and is not a comprehensive disclosure of its full scope or all of its features. 
     A bidirection AC-DC converter is provided with reduced passive component size and common mode electro-magnetic interference. The AC-DC converter includes a converter circuit configured to receive an AC input and an improved input filter interposed between the AC input and the converter circuit. The converter circuit is configured to receive an AC input from the input filter and output a DC signal. The input filter is comprised of a pair of common inductors, a pair of differential inductors, a differential capacitor and two common mode capacitors. 
     A first differential inductor in the pair of differential inductors has a first terminal electrically connected to one side of the AC input; whereas, a second differential inductor in the pair of differential inductors has a first terminal electrically connected to other side of the AC input. The first and second differential inductors are inductively coupled together and share a common core. 
     Additionally, a first common inductor in the pair of common inductors has a first terminal electrically coupled to a second terminal of the first differential inductor, and a second common inductor in the pair of common inductors has a first terminal electrically coupled to a second terminal of the second differential inductor. The first and second common inductors are inductively coupled together and share a common core. 
     A first common mode capacitor is electrically coupled between the second terminal of the first differential inductor and the positive terminal of capacitor C out . A second common mode capacitor electrically is coupled between the second terminal of the second differential inductor and ground. A differential capacitor is electrically coupled across the AC input. More specifically, the differential capacitor has a first terminal electrically coupled to the second terminal of the first differential inductor and a second terminal electrically coupled to the second terminal of the second differential inductor. 
     In some embodiments, coupling coefficient for the pair of differential inductors is on the order of one; whereas, the coupling coefficient for the pair of common inductors is less than one. 
     In other embodiments, a second pair of differential inductors is coupled in series with the pair of common inductors. In this arrangement, a first differential inductor in the second pair of differential inductors has a first terminal electrically coupled to a second terminal of the first common inductor, and a second differential inductor in the second pair of differential inductors has a first terminal electrically coupled to a second terminal of the second common inductor. Again, the first and second common inductors are inductively coupled together and share a common core. 
     Further areas of applicability will become apparent from the description provided herein. The description and specific examples in this summary are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure. 
    
    
     
       DRAWINGS 
       The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present disclosure. 
         FIG. 1  is a schematic of a proposed bi-directional AC-DC converter; 
         FIG. 2  is a schematic for an alternative embodiment of a high order input filter without magnetic integration; 
         FIG. 3  is a diagram depicting a differential model of the proposed AC-DC converter; 
         FIG. 4  is a diagram depicting a common model of the proposed AC-DC converter; 
         FIG. 5  is a timing diagram illustrating an example unipolar pulse width modulation scheme for the proposed AC-DC converter; 
         FIG. 6  is diagram depicting an example feedback control method for the proposed AC-DC converter; 
         FIG. 7  is a graph depicting input current without the proposed feedback control method; 
         FIG. 8  is a graph depicting input current with the proposed feedback control method; 
         FIG. 9  is a graph depicting voltage between output ground and AC neutral line in a conventional converter with LCL input filter; 
         FIG. 10  is a graph depicting voltage between output ground and AC neutral line in the proposed AC-DC converter; 
         FIG. 11  is a graph depicting a load step response of the proposed AC-DC converter; 
         FIG. 12  is a graph depicting a source step response of the proposed AC-DC converter; 
         FIG. 13  is a graph illustrating the reactive power compensation results for the proposed AC-DC converter; and 
         FIG. 14  is a graph illustrating the harmonic current injection results for the proposed AC-DC converter. 
     
    
    
     Corresponding reference numerals indicate corresponding parts throughout the several views of the drawings. 
     DETAILED DESCRIPTION 
     Example embodiments will now be described more fully with reference to the accompanying drawings. 
       FIG. 1  depicts an example embodiment for an AC-DC converter  10 . The converter is comprised generally of an EMI filter  12 , a high order input filter  14 , a converter circuit  16  and an output capacitor  18 . In an example embodiment, the load  19  is the secondary stage of an on-board charger, such as an isolated DC/DC converter. It is readily understood that any type of load can be used in this converter. 
     The high order input filter  14  is comprised of a pair of differential inductors (L Da  and L Db ), a pair of common inductors (L Ca  and L Cb ), a differential capacitor (C X ) and two common mode capacitors (C Ya  &amp; C Yb ). A first differential inductor L Da  has a first terminal electrically connected to a load terminal of the AC input  11 ; whereas, a second differential inductor L Db  has a first terminal electrically connected to other side (or neutral terminal) of the AC input  11 . Of note, the first and second differential inductors (L Da  and L Db ) are inductively coupled together and share a common core. 
     The pair of common inductors (L Ca  and L Cb ) are electrically coupled in series with the pair of differential inductors (L Da  and L Db ). That is, the first common inductor L Ca  has its first terminal electrically coupled to a second terminal of the first differential inductor L Da , and the second common inductor L Cb  has its first terminal electrically coupled to a second terminal of the second differential inductor L Db . The second terminal of each common inductor is electrically coupled to the converter circuit  16 . Likewise, the first and second common inductors are inductively coupled together and share a common core. The common inductors (L Ca  and L Cb ) operate to reduce the circulating common current in the converter 
     In one embodiment, coupling coefficient for the pair of differential inductors (L Da  and L Db ) is on the order of one; whereas, the coupling coefficient for the pair of common inductors (L Ca  and L Cb ) is less than one. Other values for these coupling coefficients are also contemplated by this disclosure. 
     The differential capacitor C X  is electrically coupled across the AC input and functions as a differential filter. In the example embodiment, the differential capacitor has one terminal electrically coupled to a node disposed between the first differential inductor and the first common inductor while the other terminal of the differential capacitor is electrically coupled to a node disposed between the second differential inductor and the second common inductor. It is envisioned that the differential capacitor may be disposed at other locations in the converter. 
     Two common mode capacitors C Ya  &amp; C Yb  are used to cancel electromagnetic interference. One common mode capacitor C Ya  is electrically coupled between the positive terminal of capacitor C out  and a node disposed between the first differential inductor and the first common inductor; whereas, the other common mode capacitor C Yb  is electrically coupled between ground and a node disposed between the second differential inductor and the second common inductor. These two capacitors C Ya  &amp; C Yb  also attenuate the potential slew rate of PFC ground at switching. 
     Collectively, the differential inductors (L Da  &amp; L Db ), the common inductors L Ca  &amp; L Cb  and the three capacitors C X , C Ya , C Yb  perform like a three order LCL filter. The equivalent inductance, however, is much smaller than a conventional one order filter. The inductor size, cost and weight is proportional to the inductance at the same current, so significant cost savings can be achieved with this filter arrangement. Additionally, the symmetry of this filter arrangement reduces EMI problems. 
     During operation, the converter circuit  16  is configured to receive an AC input from the input filter  14  and output a DC signal. In the example embodiment, the converter circuit  16  is implemented as a full bridge inverter arrangement although other arrangements for the converter circuit also fall within the broader aspects of this disclosure. 
     In the example embodiment, the EMI filter  12  is interposed between the AC input  11  and the input filter  14 . The EMI filer operates to filter electromagnetic interference. Because of the effectiveness of the input filter  14  at reducing electromagnetic interference, the size and complexity of the EMI filter can be reduced. In some case, the EMI filter  12  have be removed from the converter  10 . 
       FIG. 2  depicts an alternative embodiment for a high order input filer  14 ′ without magnetic integration. The arrangement for this input filter  14 ′ is similar to the input filter  14  described above. A second pair of differential inductors L Da ′ &amp; L Db ′, however, is coupled in series with the pair of common inductors L Ca  &amp; L Cb . That is, a first differential inductor L Da ′ in the second pair of differential inductors has a first terminal electrically coupled to a second terminal of the first common inductor L Ca , and a second differential inductor L Db ′ in the second pair of differential inductors has a first terminal electrically coupled to a second terminal of the second common inductor L Cb . The first and second differential inductors L Da ′ &amp; L Db ′ are inductively coupled together and share a common core. During operation, the common current through L Ca  &amp; L Cb  is much smaller than the differential current and thus only a small magnetic core is needed for L Ca  &amp; L Cb  if the coupling coefficient is 1. The second pair of differential inductors (L Da ′ &amp; L Db ′) is introduced to take place of the leakage inductance of L Ca  &amp; L Cb . Although an additional component is introduced in this arrangement, the cost, size and weight is almost the same the input filter  14  shown in  FIG. 1 . Moreover, the design and manufacture process of the input filter  14 ′ can be simplified. 
       FIG. 3  depicts the differential model for the AC-DC converter  10 . L D1 , L D2  and C D  are the equivalent parameters of this model. The derivation of the model is given in the appendix. This model is used in the control algorithm described below. 
       FIG. 4  depicts the common model of the AC-DC converter  10 . L C  and C C  are the equivalent parameters of this model. The derivation for this model is also given in the appendix. 
       FIG. 5  illustrates an example unipolar PWM pattern of driving signals and resulting outputs which may be used in the AC-DC converter  10 . IN particular, the driving signals for the switches in the full bridge inverter. In this example, the switching period is divided into two half period: first half T 1  and second half T 2 . In real time control, there is always one control period delay. That is, in T 1 , the duty ratio is calculated for the next T 2  and in T 2 , the duty ratio is calculated for next T 1 . This PWM pattern ensures that  u a −u b   =d·u DC ,  u a +u b   =u DC  in every one half period. Thus, the control period is half of the switching period. It is also noted that the common voltage output for point a and b is constant, thereby ensuring the stability of the common model shown in  FIG. 4 . Not only the output voltage u ab  frequency is doubled to the switching frequency, also the control frequency is doubled, which provides superior performance for the converter  10 . At each half period, the switching pattern keeps the average value constant to maintain a stable common mode voltage. 
       FIG. 6  depicts an example current loop control diagram for the converter  10 . The control of current loop is aimed at making the input current i AC  to the converter track a given reference waveform i ref . Grid side input voltage u AC , input current i AC  and DC side output voltage u DC  are measured for control purposes. To get fast response and robust performance, state feedback control method is adopted in the system. The detail mathematic model and derivation is given in appendix later. In  FIG. 6 , a model based state feedback control method based on discrete model is used to control the converter circuit. The output of the controller is duty, which is the duty signal u ab  shown in  FIG. 5 . In order to get a state estimation without additional hardware sensors, a Kalman state estimator is adopted in the control loop. With the advanced control method, the proposed circuit can do not only the DC voltage regulation, reactive power compensation functions, but can also be an active harmonic current filter, which could improve the power grid quality. Other types of control methods are also contemplated within the broader aspects of this disclosure. 
       FIG. 7  shows the input current without the proposed control method when there is a 1 Vpp voltage source at the input filter resonant frequency. Because there is almost no damping for higher efficiency, a small voltage source at the resonant frequency will cause oscillation. To suppress the oscillation, a damping resistor is commonly placed in series with the capacitor, which brings extra loss. Also, because the weak stability of the system, it is hard to design a high gain compensator to realize fast response. 
       FIG. 8  shows the input current with the proposed control method when there is a 1 Vpp voltage source at the input filter resonant frequency. Even without a damping resistor, there is no oscillation and the efficiency is improved. Also, it is able to realize a high performance current tracking controller for the converter. 
       FIG. 9  shows the voltage between output ground and AC neutral line in a conventional converter with LCL input filter. The voltage swings a lot with an amplitude of the DC side voltage at a very short time, this means the potential slew rate of the converter is high. The stray capacitance between PFC ground and earth could bring sever EMI problems. In contrast, the voltage between the output ground and AC neutral line in the proposed converter  10  is shown in  FIG. 10 . The voltage is very smooth, this means the potential slew rate of PFC device is very low. The common mode EMI is positive proportion to the potential slew rate. Compared with the results in  FIG. 9 , converter  10  is much better in common mode EMI performance. 
       FIG. 11  shows the load step response for the proposed AC-DC converter  10 . 6.4 kW load is applied at the output terminal. The system is stable and input current is in-phase with the input voltage. 
       FIG. 12  shows the source step response of the proposed AC-DC converter. Again, 6.4 kW step power source is applied at the output terminal. The system is stable and AC side current is in 180° phase with the input voltage. 
       FIG. 13  illustrates the reactive power compensation results for the converter  10 . The reference current can be set to any waveform using the control method shown in  FIG. 6 . Accordingly, the proposed converter  10  can perform the reactive power compensation function as well. In  FIG. 11 , the reference current is set 90° ahead of the input voltage, the control method shows very good tracking ability and the converter perform as a reactive power compensator well. 
       FIG. 14  shows the harmonic current injection results for the converter  10 . The inductor of proposed input filter stage is small so fast current slew rate can be expected. This gives the converter  10  the capability of injecting high frequency current into power grid as a harmonic active filter. In  FIG. 14 , a 25-order harmonic current (1250 Hz) is injected into the power grid as an example. 
     One advantage of the present disclosure as compared to prior art is that each of the following features can be achieved concurrently: compact and low cost of input filter size; low input current ripple achieved at lower efficiency, so higher efficiency can be achieved; low common mode EMI; and fast and robust current tracking. The AC-DC converter can perform as a bi-directional PFC converter, as well as a reactive power compensator and active harmonic filter. 
     The foregoing description of the embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but, where applicable, are interchangeable and can be used in a selected embodiment, even if not specifically shown or described. The same may also be varied in many ways. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure. 
     APPENDIX 
     Derivation of the Differential and Common Models 
     The parameters are designed symmetrically, thus the value of inductors and capacitors can be expressed as L D =L Da =L Db , L C =L Ca =L Cb , C Y =C Ya =C Yb . Following equations could be got:
 
4 L   D   ·{dot over (i)}   AC   =u   AC   u   C     X      (1)
 
 L   Ca   ·{dot over (i)}   a   −M·{dot over (i)}   b   =U   PFC   −u   CYa   −u′   a    (2)
 
 L   Cb   ·{dot over (i)}   b   −M·{dot over (i)}   a   =u′   b   −u   CYb    (3)
 
 C   Ya   ·{dot over (U)}   CYa   +i   AC   =C   X   ·{dot over (u)}   C     X     +i   a    (4)
 
 C   Yb   ·{dot over (u)}   CYb   +i   AC   =C   X   ·{dot over (u)}   C     X     +i   b    (5)
 
 U   PFC   _   GND   +u   CYb =( u   AC   −u   CX )/2   (6)
 
 U   PFC   _   VCC   −u   CYb =( u   AC   −u   CX )/2   (7)
 
 u   a   =u′   a   +U   PFC   _   GND    (8)
 
 u   b   =u′   b   +U   PFC   _   GND    (9)
 
 U   PFC   =U   PFC   _   VCC   −U   PFC   _   GND    (10)
 
(2)+(3)
 
                     2   ⁢       L   k     ·           i   .     a     +       i   .     b       2         =       u     C   X       -     (       u   a   ′     -     u   b   ′       )               (   11   )               
where L k =L C −M, which is the leakage inductance of the coupled inductors L Ca  and L Cb .
 
(2)−(3)
 
( L   c   +M )·( {dot over (i)}   a   −{dot over (i)}   b )= U   PFC −( u   CYa   −u   CYb )−( u′   a   +u′   b )   (12)
 
(4)+(5)
 
                           i   a     +     i   b       2     +       C   X     ·       u   .     CX         =       i   AC     +       C   Y     ·           u   .     CYa     +       u   .     CYb       2                 (   13   )               
from (13) we can get
 
                           i   a     +     i   b       2     +       (       C   X     +       C   Y     2       )     ·       u   .     CX         =     i   AC             (   14   )               
(4)−(5)
 
 C   Y   · ({dot over (u)} CYa   −{dot over (u)}   CYb )= i   a   −i   b    (15)
 
                   i   a     -     i   b       =     i   C       ,           i   a     +     i   b       2     =     i   D       ,     
     ⁢         u   CYa     -     u   CYb       =     u   C       ,           u   CYa     +     u   CYb       2     =     u   D       ,     
     ⁢         u   a   ′     +     u   b   ′       =     u   abC   ′       ,         u   a   ′     -     u   b   ′       =     u   ab             
We can get new equations,
 
2 L   k   ·{dot over (i)}   D   =u   C     X     −u   ab    (16)
 
( L   C   +M )·{dot over (i)} C   =U   PDC   −u   C   −u′   abC    (17)
 
                       i   D     +       (       C   X     +       C   Y     2       )     ·       u   .     CX         =     i   AC             (   18   )                 C   Y   ·{dot over (u)}   C   =i   C    (19)
 
     From equations (1), (16), (18), a differential model could be derived as shown in  FIG. 3 , where L D1 =4L D , C D =C X +C Y /2, L D2 =2L k    
     From equations (17), (19), a common model could be derived as shown in  FIG. 4 , where L Ce =L C +M, C C =C Y    
     Derivation of State Feedback Control with Kalman Estimator 
     The differential equations could be write in matrix form:
 
 {dot over (X)}=A·X+B   1   ·u   ab   +B   2   ·u   AC  
 
y=C·X
 
     
       
         
           
             
               X 
               = 
               
                 [ 
                 
                   
                     
                       
                         i 
                         AC 
                       
                     
                   
                   
                     
                       
                         u 
                         CX 
                       
                     
                   
                   
                     
                       
                         i 
                         D 
                       
                     
                   
                 
                 ] 
               
             
             , 
             
               C 
               = 
               
                 
                   
                     [ 
                     
                       
                         
                           1 
                         
                         
                           0 
                         
                         
                           0 
                         
                       
                     
                     ] 
                   
                   . 
                   
                     
 
                   
                   ⁢ 
                   A 
                 
                 = 
                 
                   
                     
                       [ 
                       
                         
                           
                             0 
                           
                           
                             
                               - 
                               
                                 1 
                                 
                                   4 
                                   ⁢ 
                                   
                                     L 
                                     D 
                                   
                                 
                               
                             
                           
                           
                             0 
                           
                         
                         
                           
                             
                               1 
                               
                                 
                                   C 
                                   X 
                                 
                                 + 
                                 
                                   
                                     C 
                                     Y 
                                   
                                   2 
                                 
                               
                             
                           
                           
                             0 
                           
                           
                             
                               - 
                               
                                 1 
                                 
                                   
                                     C 
                                     X 
                                   
                                   + 
                                   
                                     
                                       C 
                                       Y 
                                     
                                     2 
                                   
                                 
                               
                             
                           
                         
                         
                           
                             0 
                           
                           
                             
                               1 
                               
                                 2 
                                 ⁢ 
                                 
                                   L 
                                   k 
                                 
                               
                             
                           
                           
                             0 
                           
                         
                       
                       ] 
                     
                     ⁢ 
                     
                       
 
                     
                     ⁢ 
                     
                       B 
                       1 
                     
                   
                   = 
                   
                     
                       
                         [ 
                         
                           
                             
                               0 
                             
                           
                           
                             
                               0 
                             
                           
                           
                             
                               
                                 - 
                                 
                                   1 
                                   
                                     2 
                                     ⁢ 
                                     
                                       L 
                                       k 
                                     
                                   
                                 
                               
                             
                           
                         
                         ] 
                       
                       ⁢ 
                       
                         B 
                         2 
                       
                     
                     = 
                     
                       [ 
                       
                         
                           
                             
                               1 
                               
                                 4 
                                 ⁢ 
                                 
                                   L 
                                   D 
                                 
                               
                             
                           
                         
                         
                           
                             0 
                           
                         
                         
                           
                             0 
                           
                         
                       
                       ] 
                     
                   
                 
               
             
           
         
       
     
     Then, discrete equations are derived based on the continuous ones above.
 
 X ( k− 1)= A   d   ·X ( k )+ B   d1   ·u   ab ( k )+B d2   ·u   AC ( k )
 
     
       
         
           
             
               A 
               d 
             
             = 
             
               
                 
                   exp 
                   
                     A 
                     · 
                     
                       T 
                       s 
                     
                   
                 
                 ⁢ 
                 
                   B 
                   dn 
                 
               
               = 
               
                 
                   ( 
                   
                     
                       ∫ 
                       0 
                       
                         T 
                         s 
                       
                     
                     ⁢ 
                     
                       
                         exp 
                         
                           A 
                           · 
                           
                             T 
                             s 
                           
                         
                       
                       · 
                       
                           
                       
                       ⁢ 
                       
                         ⅆ 
                         t 
                       
                     
                   
                   ) 
                 
                 · 
                 
                   B 
                   n 
                 
               
             
           
         
       
     
     T s  is the discrete step time. 
     To realize no static error performance, an extend the matrix for integral function is adopted.
 
{tilde over ( X )}( k+ 1)= Ã   d   ·{tilde over (X)} ( k )+ B   d1   ·u   ab ( k )+ {tilde over (B)}   d2   ·u   AC ( k )
 
where
 
     
       
         
           
             
               
                 X 
                 ~ 
               
               = 
               
                 [ 
                 
                   
                     
                       
                         x 
                         i 
                       
                     
                   
                   
                     
                       X 
                     
                   
                 
                 ] 
               
             
             , 
             
               
                 
                   A 
                   ~ 
                 
                 d 
               
               = 
               
                 [ 
                 
                   
                     
                       1 
                     
                     
                       C 
                     
                   
                   
                     
                       0 
                     
                     
                       
                         A 
                         d 
                       
                     
                   
                 
                 ] 
               
             
             , 
             
               
                 
                   B 
                   ~ 
                 
                 
                   d 
                   ⁢ 
                   1 
                 
               
               = 
               
                 [ 
                 
                   
                     
                       0 
                     
                   
                   
                     
                       
                         B 
                         
                           d 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                       
                     
                   
                 
                 ] 
               
             
             , 
             
               
                 
                   B 
                   ~ 
                 
                 
                   d 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   2 
                 
               
               = 
               
                 [ 
                 
                   
                     
                       0 
                     
                   
                   
                     
                       
                         B 
                         
                           d 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                     
                   
                 
                 ] 
               
             
           
         
       
     
     To design a tracking controller, the first step is design a regulator to regulate all the state variables to zero. A full-state feedback controller is designed in the following form:
 
 u   ab ( k )=− {tilde over (K)}·{tilde over (X)} ( k ), where  {tilde over (K)}=[K   1   K] 
 
     We use the optimal control theory, 
     The performance index is defined as: 
     
       
         
           
             J 
             = 
             
               
                 ∑ 
                 
                   k 
                   = 
                   1 
                 
                 ∞ 
               
               ⁢ 
               
                   
               
               ⁢ 
               
                 [ 
                 
                   
                     
                       
                         x 
                         ~ 
                       
                       ⁡ 
                       
                         ( 
                         k 
                         ) 
                       
                     
                     · 
                     Q 
                     · 
                     
                       
                         x 
                         ~ 
                       
                       ⁡ 
                       
                         ( 
                         k 
                         ) 
                       
                     
                   
                   + 
                   
                     
                       
                         u 
                         ab 
                       
                       ⁡ 
                       
                         ( 
                         k 
                         ) 
                       
                     
                     · 
                     R 
                     · 
                     
                       
                         u 
                         ab 
                       
                       ⁡ 
                       
                         ( 
                         k 
                         ) 
                       
                     
                   
                 
                 ] 
               
             
           
         
       
     
     The weighting matrix is designed as follows for example: 
     
       
         
           
             Q 
             = 
             
               
                 
                   [ 
                   
                     
                       
                         8 
                       
                       
                         0 
                       
                       
                         0 
                       
                       
                         0 
                       
                     
                     
                       
                         0 
                       
                       
                         128 
                       
                       
                         0 
                       
                       
                         0 
                       
                     
                     
                       
                         0 
                       
                       
                         0 
                       
                       
                         0.01 
                       
                       
                         0 
                       
                     
                     
                       
                         0 
                       
                       
                         0 
                       
                       
                         0 
                       
                       
                         0.01 
                       
                     
                   
                   ] 
                 
                 ⁢ 
                 R 
               
               = 
               1 
             
           
         
       
     
     By minimizing 
     
       
         
           
             J 
             = 
             
               
                 ∑ 
                 
                   k 
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                 ∞ 
               
               ⁢ 
               
                   
               
               ⁢ 
               
                 [ 
                 
                   
                     
                       
                         x 
                         ~ 
                       
                       ⁡ 
                       
                         ( 
                         k 
                         ) 
                       
                     
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                     Q 
                     · 
                     
                       
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                         ( 
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                         ) 
                       
                     
                   
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                         ab 
                       
                       ⁡ 
                       
                         ( 
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     We can get the solution
 
 {tilde over (K)}=[R+{tilde over (B)}   d1   T   ·P·{tilde over (B)}   d1 ] −1   ·{tilde over (B)}   d1   T   ·P·Ã   d  
 
     Where P is the solution of the following Riccati equation
 
 P=Q+Ã   d   T   ·P·[I+{tilde over (B)}   d1   ·R   −1   ·{tilde over (B)}   d1   T   ·P]   −1   ·Ã   d  
 
     To cancel the effect of input voltage u AC , a feed-forward item is introduced. Then, we got the regulator design:
 
 u   ab ( k )=− {tilde over (K)}·{tilde over (X)} ( k )+ u   AC ( k )
 
     If the regulator does not regulate all the state variables to zero but a reference value, a tracking controller could be got:
 
 u   ab   =−{tilde over (K)} ·( {tilde over (X)}−{tilde over (X)}   r )+ u   AC  
 
Where
 
                 X   ~     r     =     [         0             i   ref               u   AC               i   ref           ]           
is the reference value for the four state variables.
 
     There are usually three sensors for traditional PFC: input AC current, input AC voltage, output DC voltage. There are three more variables needed in {tilde over (X)}. However, by using an estimator, we do not need more sensors to get the value in {tilde over (X)}. x i  is a virtual variable, it can be calculated. The values of u CX  and i D  are estimated using a Kalman estimator. An estimator is designed in the following way.
 
 {circumflex over (X)} ( k )=   X   ( k )+ L ( y ( k )− C· X   ( k ))
 
                 X   _     ⁡     (     k   +   1     )       =       A   ·       X   ^     ⁡     (   k   )         +       (           B     d   ⁢           ⁢   1             B     d   ⁢           ⁢   2             )     ·     (             u   ab     ⁡     (   k   )                   u   AC     ⁡     (   k   )             )               
{circumflex over (X)}(k) Current estimate based on the current measurement
 
 X (k) Predicted estimated based on a model prediction
 
     For each calculation, the difference of y(k)−C· X (k) is used to correct the estimated value. The design of L could affect the performance of the estimator. A Kalman estimator design is used here. 
               X   ⁡     (     k   +   1     )       =       A   ·     X   ⁡     (   k   )         +       (           B     d   ⁢           ⁢   1             B     d   ⁢           ⁢   2             )     ·     (             u   ab     ⁡     (   k   )                   u   AC     ⁡     (   k   )             )       +       (           B     d   ⁢           ⁢   1             B     d   ⁢           ⁢   2             )     ·     w   ⁡     (   k   )                   y ( k )= C·X ( k )+ v ( k ) 
     Where 
               w   ⁡     (   k   )       =     (             w   1     ⁡     (   k   )                   w   2     ⁡     (   k   )             )           
is the processing noise. And v(k) is the measurement noise.
 
     The noise level could be determined by the following factors 
     w 1 (k): u ab —PWM precision, measurement noise of u DC    
     w 2 (k): u AC —measurement noise of u AC    
     v(k): i AC —measurement noise of i AC    
     Then, the mathematical expectation of the noise could be defined:
 
 Q=E{ww   T   }R=E{vv   T }.
 
     The estimator gain L could be calculated and the estimator could be designed.