Abstract:
A system and method of reducing current consumption in a low voltage booster circuit is provided. The method includes the steps of (a) enabling an input signal to activate plural out of phase clocks; and (b) disabling the input signal after a pre-determined time and after an output voltage has reached a certain level.

Description:
BACKGROUND 
       [0001]    1. Field of the Invention 
         [0002]    The present invention is related to non-volatile memory devices (“flash memory devices”), and more particularly, to low voltage booster circuits used in flash memory devices. 
         [0003]    2. Background 
         [0004]    Semiconductor memory devices have become popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other electronic devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories. 
         [0005]    Flash memory devices are comprised of an array of memory cells that are selected by word lines extending along rows of the memory cells, and bit lines extending along columns of the memory cells. Low voltage booster circuits are used to generate a voltage level higher than a given input voltage and the generated level can be used to transfer high voltage signals through transfer gates. 
         [0006]    A typical low voltage booster circuit requires a clock input which will be amplified with an internal clock doubler circuit to achieve fast ramp up of the output voltage. Although the low voltage booster circuit provides a fast ramp up time, it also has the undesirable side effect of high current consumption which generates more heat and more noise in the chip. The high current consumption is a result of two internal capacitors in the low voltage booster circuit that are used to amplify clock signals. Therefore, what is needed is a low voltage booster circuit that provides a fast ramp up time for the output voltage without consuming a large amount of current. 
       SUMMARY OF THE INVENTION 
       [0007]    In one aspect of the present invention, a method of reducing current consumption in a low voltage booster circuit is provided. The method includes the steps of (a) enabling an input signal to activate plural out of phase clocks; and (b) disabling the input signal after a pre-determined time and after an output voltage has reached a certain level. 
         [0008]    In another aspect of the present invention, a system for reducing current consumption in a low voltage booster circuit is provided. The system includes a clock doubler circuit; a high voltage stage circuit, having an output voltage, connected to the clock doubler circuit, wherein an input signal to the clock doubler circuit activates plural out of phase clocks when the input signal is enabled; and the input signal is disabled after a pre-determined time and after the output voltage has reached a certain level. 
         [0009]    This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof in connection with the attached drawings. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The foregoing features and other features of the present invention will now be described with reference to the drawings of a preferred embodiment. The illustrated embodiment is intended to illustrate, but not to limit the invention. The drawings include the following: 
           [0011]      FIG. 1  is a block diagram of a low voltage booster circuit; 
           [0012]      FIG. 2  is a block diagram of a clock doubler circuit in the low voltage booster circuit of  FIG. 1 ; 
           [0013]      FIG. 3  is a schematic diagram of the clock doubler circuit of  FIG. 2 ; 
           [0014]      FIG. 4  illustrates a schematic diagram of a high voltage stage circuit of the low voltage booster circuit of  FIG. 1 ; 
           [0015]      FIG. 5  illustrates a conventional clocking diagram of the low voltage booster circuit of  FIG. 1 ; 
           [0016]      FIG. 6  is a flow diagram for generating an output voltage signal in the low voltage booster circuit of  FIG. 1 ; 
           [0017]      FIG. 7  illustrates a clocking diagram of the low voltage booster circuit of  FIG. 1 , according to one aspect of the present invention; and 
           [0018]      FIG. 8  is a flow diagram for reducing current consumption in a low voltage booster circuit, according to one aspect of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0019]    To facilitate an understanding of the preferred embodiment, the general architecture and operation of a low voltage booster circuit will be described. The specific architecture and operation of the preferred embodiment will then be described with reference to the general architecture. 
       General Description of a Local Booster Circuit Structure 
       [0020]    A typical low voltage booster circuit  100  is shown in  FIG. 1 . Low voltage booster circuit  100  is comprised of a clock doubler circuit  104  connected to a high voltage stage circuit  108 . An output voltage VOUT  110  is generated from low voltage booster circuit  100  based on output clock signals, BCLK  105  and ACLK  106 , from clock doubler circuit  104  and an input voltage VSUP  109 . 
         [0021]    Clock doubler circuit  104  receives a clock signal INPUT_CLK  101 , an input signal BOOSTER_ENB  102  and an input signal  2 X_ENB  103 . When BOOSTER_ENB signal  102  and  2 X_ENB signal  103  are high, all clock signals within clock doubler circuit  104  are activated and output voltage VOUT  110  of high voltage stage circuit  108  ramps up to a voltage greater than VSUP  109  over a pre-determined time t. 
         [0022]      FIG. 2  is a block diagram of clock doubler circuit  104  of  FIG. 1 . Clock doubler circuit  104  comprises a first process circuit  107 A and a second process circuit  107 B generating output clock signals BCLK  105  and ACLK  106 , respectively. First process circuit  107 A is comprised of first stage 1 circuit  104 A and first stage 2 circuit  104 E, while second process circuit  107 B is comprised of second stage 1 circuit  104 B and second stage 2 circuit  104 F. 
         [0023]    First stage 1 circuit  104 A receives clock signal aCLK 1   101 A, BOOSTER_ENB signal  102  and  2 X_ENB signal  103 , generating clock signal aCLK 2   104 C. Clock signal aCLK 2   104 C is then input into first stage 2 circuit  104 E generating output clock signal BCLK  105 . Clock signal aCLK 1   101 A is comprised of a clock signal “clk” and a delayed clock signal “clkd” (see  FIG. 3 ). 
         [0024]    Second stage 1 circuit  104 B receives clock signal bCLK 1   101 B, BOOSTER_ENB signal  102  and  2 X_ENB signal  103  generating clock signal bCLK 2   104 D. Clock signal bCLK 2   104 D is then input into second stage 2 circuit  104 F generating output clock signal ACLK  106 . Clock signal bCLK 1   101 B is comprised of clock signal “clk” and delayed clock signal “clkd” (see  FIG. 3 ). 
         [0025]    Output clock signals (or “plural out of phase clocks”) BCLK  105  and ACLK  106  are reverse phase and input into high voltage stage  108  allowing output voltage VOUT  110  to ramp up to a certain level, a voltage greater than input voltage VSUP  109  over pre-determined time t. Because the voltage of BCLK  105  and ACLK  106  are amplified by second stages  104 E and  104 F, their voltage levels are in the same range of a 3V booster circuit where VDD is 3V, therefore the ramp up speed of both boosters will be similar. 
         [0026]      FIG. 3  is a schematic diagram of clock doubler circuit  104  of  FIG. 2  showing the internal circuitry of first and second stage 1 circuits  104 A and  104 B and first and second stage 2 circuits  104 E and  104 F. First stage 1 circuit  104 A includes a first OR-gate  110 , a first NAND-gate  112 , and a second OR-gate  114 . First OR-gate  110  receives clock signal “clk” and delayed clock signal “clkd” generating an output signal  113  which is input into first NAND-gate  112  along with BOOSTER_ENB signal  102 . The output of first NAND-gate aclk  115  is input into second OR-gate  114  along with inverted  2 X_ENB signal  103  generating clock signal aclk 2   104 C. 
         [0027]    Second stage 1 circuit  104 B includes a second NAND-gate  120 , a third NAND-gate  122  and a third OR-gate  124 . Second NAND-gate  120  receives clock signal “clk” and delayed clock signal “clkd” generating an output signal  121  which is input into third NAND-gate  122  along with BOOSTER_ENB signal  102 . The output of third NAND-gate bclk  123  is input into third OR-gate  124  along with inverted  2 X_ENB signal  103  generating clock signal bclk 2   104 D. 
         [0028]    First stage 2 circuit  104 E includes three MOSFET transistors  126 ,  128 ,  130  and a first capacitor Cb. The output of first stage 1 circuit aclk  115  and aclk 2   104 C is input into transistor  126  while clock signal aclk  115  is input into transistor  130  and inverted clock signal aclk  115  is input into transistor  128 . 
         [0029]    Second stage 2 circuit  104 F includes three MOSFET transistors  132 ,  134 ,  136  and a second capacitor Ca. The output of second stage 2 circuit bclk  123  and bclk 2   104 D is input into transistor  132  while clock signal bclk  123  is input into transistor  136  and inverted clock signal bclk  123  and input into transistor  134 . 
         [0030]    First capacitor Cb in first stage 2 circuit  104 E is connected between a corresponding transistor pair  126  and  128  and clock signal aclk 2   115  allowing clock signal BCLK  105  to be amplified to nearly twice as high as VDD, where VDD is the amplitude of INPUT_CLK signal  101 . 
         [0031]    Second capacitor Ca in second stage 2 circuit  104 F is connected between a corresponding transistor pair  132  and  134  and clock signal bclk 2   123  allowing clock signal ACLK  106  to be amplified to nearly twice as high as VDD. By amplifying output clocks ACLK  106  and BCLK  105 , the clock voltage becomes competitive to that of a high voltage booster circuit (3V); therefore ramp up time of low power supply booster is competitive to that of a high voltage booster as well. However, first and second capacitors Cb and Ca also cause the undesired effect of high current consumption in the circuits. 
         [0032]      FIG. 4  illustrates a schematic diagram of high voltage stage  108  of low voltage booster circuit  100  of  FIG. 1 . High voltage stage  108  includes transistors  139 ,  140 ,  142 ,  144 ,  146 ,  148 ,  149  and capacitors  150 ,  152 ,  154 ,  156 , each of which has a first terminal connected to the respective gates of transistors  142 ,  144 ,  146 ,  148  and between a corresponding transistor pair  140  and  142 ,  142  and  144 ,  144  and  146 ,  146  and  148 , respectively. The second terminal of capacitors  150  and  154  are connected to output clock signal ACLK  106  while the second terminal of capacitors  152  and  156  are connected to output clock signal BCLK  105 . Source terminals of transistors  139  and  140  are connected to input voltage VSUP  109 . BOOSTER_ENB signal  102  is transmitted through an inverter  158  and input into the gate of transistor  149 . ACLK  106  and BCLK  105  are activated while BOOSTER_ENB signal  102  is high and the output voltage VOUT is regulated at VSUP+Vt where Vt is the threshold voltage of transistor  139 . 
         [0033]    By applying boosted output clock signals ACLK  106  and BCLK  105  to high voltage stage  108 , the ramp up time for output voltage VOUT  110  is competitive to a high voltage booster circuit (3V). However, current consumption is larger than the high voltage booster circuit (3V) because of the current consumed in clock doubler  104  by first and second capacitors Cb and Ca. 
       Clocking Diagram for a Local Booster Circuit 
       [0034]      FIG. 5  illustrates a conventional clocking or timing diagram of low voltage booster circuit  100  of  FIG. 1 . Once input BOOSTER_ENB  102  becomes high, internal clocks aclk  115 , aclk 2   104 C, bclk  123 , bclk 2   104 D, ACLK  106 , and BCLK  105  are activated, and an output of local booster VOUT starts to ramp up.  2 X_ENB signal  103  is continuously high in order to boost clock signals ACLK  106  and BCLK  105  to amplitude close to twice as high as VDD. Output voltage VOUT  110  ramps up to VSUP+Vt where Vt is the threshold voltage of transistor  139 , in pre-determined time t. 
         [0035]      FIG. 6  is a flow diagram showing the steps of generating an output voltage signal in low voltage booster circuit  100  of  FIG. 1 . In step S 600 , low voltage booster circuit  108  receives input voltage VSUP  109 . In step S 601 , low voltage booster circuit  100  receives INPUT_CLK  101  and in step S 602  BOOSTER_ENB signal  102  and  2 X_ENB signal  103  are enabled. In step S 603 , output voltage VOUT is generated over pre-determined time t and is greater than VSUP  109 . 
       Clocking Diagram for a Local Booster Circuit to Reduce Current Consumption 
       [0036]      FIG. 7  illustrates a clocking diagram of low voltage booster circuit  100  of  FIG. 1 , according to one aspect of the present invention. As with the clocking diagram in  FIG. 5 , once BOOSTER_ENB signal  102  becomes high, internal clocks aclk  115 , aclk 2   104 C, bclk  123 , bclk 2   104 D, ACLK  106 , and BCLK  105  are activated, and output of local booster VOUT starts to ramp up. However, unlike the clocking diagram of  FIG. 5 ,  2 X_ENB signal  103  is disabled after a pre-determined period t 1 , allowing aclk 2   104 C and bclk 2   104 D to be disabled. During ramp up, clock signals ACLK  106  and BCLK  105  are boosted from INPUT_CLK signal amplitude VDD to an amplitude close to twice as high as VDD, and then reduced back to INPUT_CLK signal amplitude VDD upon disabling  2 X_ENB signal  103  and clock signals aclk 2   104 C and bclk 2   104 D. By disabling  2 X_ENB signal  103  after pre-determined ramp up time t 1  and reducing the amplitude of output clock signals ACLK  106  to BCLK  105  to INPUT_CLK signal amplitude VDD, current consumption in low voltage booster circuit  100  is reduced, as can be seen in  FIG. 7 . 
         [0037]    Factors such as the output load connected to VOUT, voltage of VSUP, and current drivability of the transistors within local booster circuits will determine ramp up time t 1 , which can be estimated by simulation or circuit testing. Pre-determined time t 1  can be pre-programmed based on above mentioned simulation and circuit testing. 
         [0038]      FIG. 8  is a flow diagram showing the steps of reducing current consumption in low voltage booster circuit  100 . For reducing current consumption, the same steps as in  FIG. 6  are followed with the addition of a step of disabling  2 X_ENB signal  103 . In step S 800 , high voltage booster circuit  108  receives input voltage Vsup  109 . In step S 801 , low voltage booster circuit  100  receives INPUT_CLK  101  and in step S 802  BOOSTER_ENB signal  102  and  2 X_ENB signal  103  are enabled. In step S 803 , output voltage Vout is generated over pre-determined time t and is greater than Vsup  109 . Finally, in step S 804 ,  2 X_ENB signal  103  is disabled after predetermined time t 1 . 
         [0039]    Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and not limiting. Many other applications and embodiments of the present invention will be apparent in light of this disclosure and the following claims.