Abstract:
A semiconductor chip package includes a package substrate having a first bond pad pattern. A semiconductor chip resides on the package substrate. The semiconductor chip has a second bond pad pattern. A lid cover houses the semiconductor chip and is fitted onto the package substrate. The second bond pattern of the semiconductor chip is connected to the first bond pattern of the package substrate through internal conductor traces of the lid cover.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to semiconductor chip packages. Particularly, the present invention is related to a semiconductor chip package with a package substrate and a lid cover.  
           [0003]    2. Description of The Related Art  
           [0004]    Surface mount technology (SMT), where semiconductor chips with their connection pads at the bottom surface of the chips are mounted directly onto a surface without being plugged into it, is widely used in electronic applications. Another known semiconductor chip mounting technique is referred to as the Flip-Chip mounting technique. Using this technique, a semiconductor chip having a bottom bond pad pattern is mounted with its face down directly onto a corresponding bond pad pattern of a circuit board in a manner similar to the SMT process.  
           [0005]    Semiconductor packages are used for protecting a semiconductor chip or die in a package body, and for providing connection points for connecting the packaged chip or die to the semiconductor chip or die to external devices. To cope with the high density and high pin-count of semiconductor chips, BGA (Ball Grid Array) and PGA (Pin Grid Array) packages have been developed.  
           [0006]    In a typical BGA package, the semiconductor chip is mounted to the top surface of a package substrate or printed circuit board-type substrate. The chip is wire bonded to electrical traces in the substrate, then over-molded with an encapsulating material for protection. Solder balls are bonded to the electrical traces on the bottom surface of the substrate, serving as the external electrodes for mounting on a printed circuit board. Again, this type of package is suitable to be mounted using the Flip-Chip or SMT technique. Other BGA type semiconductor chip packages are known where the semiconductor chip is connected to a bottom ball pad pattern through gold wires connected to an internal wiring leading through a multi-layer substrate.  
           [0007]    Disadvanges are associated with the prior BGA packages. One disadvantage is that the chips are subject to damages because their top surfaces are exposed during testing or packaging steps. Another disadvantage is that the prior BGA packages require wires for connection between the chip and substrate.  
         SUMMARY OF THE INVENTION  
         [0008]    One of the features of the present invention is to provide a semiconductor chip package adapted for face down mounting on circuit boards.  
           [0009]    Another feature of the present invention is to provide a wireless semiconductor chip package with increased versatility.  
           [0010]    In accordance with one embodiment of the present invention, a semiconductor chip package is provided. The package includes a package substrate having a first bond pad pattern. A semiconductor chip is attached to the package substrate and has a second bond pad pattern. A lid cover houses the semiconductor chip and is fitted onto the package substrate. The bond pad pattern of the semiconductor chip is connected to the bond pad pattern of the package substrate through internal conductor traces of the lid cover.  
           [0011]    This makes the package a wireless semiconductor chip package. Moreover, the semiconductor chip is attached to the top of the package substrate by an intermediate resin layer, and may be within the lid cover by an air gap between the top plate of the lid cover and the package substrate.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]    [0012]FIG. 1 is a bottom view of a package substrate of the semiconductor chip package in accordance with one embodiment of the present invention.  
         [0013]    [0013]FIG. 2 is a side view of the package substrate of FIG. 1 with a semiconductor chip attached on top of the package substrate.  
         [0014]    [0014]FIG. 3 is a bottom view of a lid cover to be fitted onto the package substrate of FIG. 2 thereby housing the semiconductor chip and providing electrical connection between the top bond pad pattern of the chip and the bottom bond pad pattern of the package.  
         [0015]    [0015]FIG. 4 is a side view of the lid cover of FIG. 3.  
         [0016]    [0016]FIG. 5 is a schematic side view of a wireless communication semiconductor chip package assembly of the semiconductor chip, package substrate, and lid cover shown in FIGS.  1  to  4 .  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0017]    [0017]FIG. 5 shows a side view of a semiconductor chip package  100  in accordance with one embodiment of the present invention. As will be described in more detail below, the semiconductor chip package  100  is a wireless semiconductor chip package. This means that the package  100  is without connecting and self-supported wires. The semiconductor chip  1  can also be referred to as a semiconductor (or IC) chip or die.  
         [0018]    The semiconductor chip package  100  includes a semiconductor chip  1 . The semiconductor chip  1  has a top bond pad pattern  5 . The semiconductor chip  1  is housed between a package substrate  2  and a lid cover  3 . The lid cover  3  is fitted onto the package substrate  2 . The lid cover  3  is internally plated with a bottom bond pad pattern  13  corresponding to and in contact with the top bond pad pattern  5  of the semiconductor chip  1  and provides internal conductor traces to electrically connect the semiconductor chip  1  to a bottom bond pad pattern  6  of the package substrate  2 .  
         [0019]    This makes the semiconductor chip package  100  a wireless semiconductor chip package. Moreover, the semiconductor chip  1  is attached to the top of the package substrate  2  by an intermediate resin layer  10 , and may be within the lid cover  3  by an air gap  19  between a top plate (i.e., the top plate  11  in FIG. 3) of the lid cover  3  and the package substrate  2 .  
         [0020]    This allows the wireless semiconductor chip package  100  to be adapted for face down mounting on circuit boards. This also allows the wireless semiconductor chip package  100  with increased versatility by having its semiconductor chip housed in a lid cover and surrounded by an air gap for thermal insulation purposes. The wireless semiconductor chip package  100  will be described in more detail below, also in conjunction with FIGS.  1 - 5 .  
         [0021]    The package substrate  2  is shown in more detail in FIGS. 1 and 2. The package substrate  2  is made of a non-conductive material like ceramics or that of a printed circuit board (PCB). The bottom surface  7  of the package substrate  2  is plated with a conductive material (e.g. Au/Ni/CU metal for PCB substrate) to form conductive traces of a bottom bond pad pattern  6 . The bottom bond pad pattern  6  includes a ground pad  6   a , a plurality of input/output pads  6   b , and a plurality of lead-out conductive traces  6   c  (see FIG. 2) connected to the pads  6   a  and  6   b  and extending up to and across the side surfaces  8  of the package substrate  2  as further shown in FIG. 2. The plating material is chosen for electrical connection and solderability.  
         [0022]    As can be seen from FIG. 2, the package substrate  2  prepared in the aforementioned manner then receives a resin, preferably an epoxy resin. The resin is placed onto the middle portion of the top surface  9  of the package substrate  2  to form a resin layer  10  for heat dissipation and for attaching the semiconductor chip  1 . The process for attaching the semiconductor chip  1  can be a stencil printing or, for example, an eutectic or a stamping or a dispensing process. When forming the resin layer  10 , the thickness of the resin layer  10  should be controlled tightly, and all the aforementioned processes are suitable for a good resin thickness control. The semiconductor chip  1  is then placed onto the resin layer  10 , thereby firmly attaching the semiconductor chip  1  on the package substrate  2 . At this time, the top bond pad pattern  5  of the semiconductor chip  1  is not in contact with the resin layer  10 , but rather is on the opposite side of the semiconductor chip  1 .  
         [0023]    [0023]FIGS. 3 and 4 show a bottom view and a schematic side view, respectively, of the lid cover  3 . As can be seen from FIG. 3- 4 , the lid cover  3  is a cup-shaped lid cover of non-conductive material. The non-conductive material can be, for example, a PCB substrate material. The lid cover  3  includes the top plate  11  and four side walls  12  projecting from the top plate  11 . The inner (bottom) surface of the top plate  11  is plated with the bottom bond pad pattern  13  and a plurality of conductive traces  14  connected to the bottom bond pad pattern  13  and extending along the inner surface of the top plate  11  and down along the inner surfaces of the side walls  12  to end into side bond pads  15  at the lower edge portions of side walls  12 . The plating material is a conductive and solderable metal (e.g. Au/Ni/Cu for PCB substrate material). The footprint of the bottom bond pad pattern  13  of the lid cover  3  is exactly the same as the footprint of the top bond pad pattern  5  of the seminconductor chip  1  (see FIGS.  1 - 2  and  5 ). The foot print shown is only an example for a variety of possible footprints as will be appreciated by the skilled person. The bottom bond pad pattern  13  of the lid cover  3  may even include projecting bumps of any suitable design and type.  
         [0024]    As can be seen from FIGS.  1 - 5 , the size and dimensions of the lid cover  3  and the package substrate  2  including their plating patterns are such that the inner sides of the side walls  12  of the lid cover  3  tightly fit into the side surfaces  8  of the package substrate  2  (see FIG. 2). When the lid cover  3  is fitted onto and around the package substrate  2 , the bottom bond pad pattern  13  of the lid cover  3  is pressed into electrical contact with the top bond pad pattern  5  of the semiconductor chip  1 . In addition, the side bond pads  15  of the bottom bond  5  pad pattern  13  on the inner side of the side walls  12  of the lid cover  3  are in tight contact with the conductive traces  6   c  on the side surfaces  8  of package substrate plate  2 . Therefore, electrical connection is established between the bond pads/traces  15 ,  14  of the lid cover  3  and the conductive traces  6   c  of the bottom bond pad pattern  6 .  
         [0025]    As further shown in FIGS. 1 and 3, the package substrate  2  and the lid cover  3  additionally include guard rings  16  and  17 , respectively, on diametrically opposite corners thereof. These guard rings  16 ,  17  are used to guide the position of lid cover  3  such that the foot print of the bottom bond pad pattern  13  of the lid cover  3  sits directly onto the same footprint of the top bond pad pattern  5  of the chip  1 .  
         [0026]    [0026]FIG. 4 shows the side view of lid cover  3  with the side bond pads  15  for the purpose of electrical connection and solderability towards the condcutive traces  6   c  of the bottom bond pad pattern  6  of the package substrate  2 .  
         [0027]    As further shown in FIG. 5, the lid cover  3  is finally fixed to the package substrate  2  by solder points  18  for the purpose of having the bottom bond pad pattern  13  of the lid cover  3  permanently and firmly connected to the top bond pad pattern  5  of the semiconductor chip  1 . As further shown in FIG. 5, the semiconductor chip  1  is surrounded by an air gap or space  19  between the lid cover  3  and the package substrate  2 . This is for thermal insulation purposes.  
         [0028]    The present invention is not limited to what has been described above and shown in the drawings. Especially, it is possible and may be preferable, to include bumps of any suitable design into the bond pads of the bond pad patterns.