Abstract:
This invention involves with a low power IC (Integrated Circuit) with high energy efficiency. This invention describes a Buck converter that can track the minimum energy point of the load. It works by estimating input energy of every sensing period, taking advantage of energy consumption curve of IC in sub-threshold. Energy estimation is implemented with counting conducted pulses, while maintaining constant input energy of each pulse by regulating output voltage and ON time with digital control circuit. With digital control circuit, minimum energy point can be tracked with a lookup table stored inside. Most of this invention&#39;s control circuit is digital, with benefits of low power consumption and small chip area.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This national stage application claims the benefit under 35 U.S.C. §371 of International Application No. PCT/CN2011/071375 filed on Feb. 28, 2011, entitled MINIMUM ENERGY POINT TRACKING BUCK CONVERTER, which takes its priority from Chinese Patent Application No. 2011100040743.8 filed on Feb. 18, 2011, and all of whose entire disclosures are incorporated by reference herein. 
     TECHNIQUE AREA 
     This invention involves with low power consumption IC (Integrated Circuit), especially a digital IC working in sub-threshold region, implemented in Buck converter with high energy efficiency. 
     BACKGROUND OF THE INVENTION 
     Integrated voltage regulator circuits usually include an Output Unit and a Regulating Unit. The input voltage is chopped by the Output Unit of switching power supply circuit into pulses, which is then transferred to the load after filtered. The Regulating Unit senses and regulates the output voltage. PSM (Pulse Skip Modulation) is often adopted in switching power supply circuit. The strategy of PSM control is that the output of a comparator determines this pulse skipped or not to regulate the output voltage by sampling the output voltage and comparing with the output reference voltage. PSM is based on CFCW (Constant Frequency Constant Width). Pulse will be skipped when output voltage is higher than reference voltage. Otherwise, output voltage is stable under CFCW control. At the same time, with energy module under PSM control, the input energy can be constant by manipulating output voltage and duty cycle. It is the fundamental of MEPT system tracking load&#39;s minimum energy point. 
     BRIEF SUMMARY OF THE INVENTION 
     The goal of this invention is to provide a minimum energy point tracking Buck converter by taking advantage of the particular energy consumption curve in sub-threshold region, and manipulating output voltage and duty cycle to transfer constant energy through the converter. Load energy consumption can be estimated by counting the normal on-off pulses. 
     The proposed solution is that the minimum energy point tracking Buck converter includes an Output Unit and a Regulating Unit. The Output Unit chops input voltage into pulses and transfers to the load after filtered. The Regulating Unit, including a Current Limit block, a Digital Control block  1  and a DAC (Digital Analog Converter)  3 , regulates the output voltage. The output voltage of the Output Unit, VO, and the output voltage of the DAC  3 , DAC_OUT, are compared by a comparator  8 , whose output, COMP_OUT, is connected to an AND_Gate  9 , with clock signal, CLK, as the other input. The output of the AND_Gate  9 , CLK_REF, is connected to the S port of a RS trigger  10 , and the input port of the Digital Control block. The output of the RS trigger  10  is connected to the gate port of a Power MOSFET  4  via an inverter  11   a . There are two output ports of the Digital Control block. One of them determines duty cycle of the pulse through Current Limit block  2 ; the other is connected with DAC  3  to generate different output reference voltage. The output of Current Limit block  3 , ILIM_OUT, is connected to one of the inputs of an OR_Gate  12 , via an inverter  13 . The other input port of OR_Gate  12  is connected to clock signal with maximum pulse width, DMAX. Its output is connected to the R port of the RS trigger  10 . 
     The output of the RS trigger  10  is connected to the gate of the Power MOSFET  4  via an inverter. 
     The output of the Current Limit block  2 , ILIM_OUT, possesses  6  states corresponding to 6 different duty cycles. The Current Limit block includes a PMOS  21 , and a comparator  22 . The source of PMOS  21  is connected to the input voltage, VIN, and its drain is connected to 6 rows of current mirrors, whose ON/OFF is corresponding to 6 different control states. The gate of PMOS  21  is connected to ground. The positive and negative inputs of the comparator  22 &#39;s are connected to SW and PMOS  21 &#39;s drain respectively. Its output, ILIM_OUT, is the output of the Current Limit block. 
     The output reference voltage, DAC_OUT, is determined by 5 digits, D&lt;4:0&gt;. 
     The DAC is consisted of an operational amplifier  23 , and an N-type regulating MOSFET  24 . The positive and negative inputs of the operational amplifier  23 &#39;s are connected to reference voltage, VREF, and the source of MOSFET  24 , which is connected to ground via 5 resistors  25 ˜ 29 , and a sampling resistor  30 , in series. Resistors  25 ˜ 29  could be shorted out corresponding to D&lt;4:0&gt; to generate different output reference voltage. The output of the operational amplifier  23  is connected to the gate of NMOS  24 . The drain of the NMOS  24  is connected to VIN. DAC_OUT is connected to the source of NMOS  24 . 
     The Digital Control block  1  is consisted of a Counter  31 , a Comparator Unit  32  and a Lookup Table 33. Rising edge of CLK_REF, as Counter  31 &#39;s input, is counted in certain period and then compared with Counter  31 &#39;s output of last period, M, stored in the Comparator Unit  32 . With Comparator Unit  32 &#39;s output, COMP_OUT, certain I&lt;5:0&gt; and D&lt;4:0&gt; are determined according to the Lookup Table 33. 
     The benefit of this invention is that constant input energy can be maintained when a pulse is not skipped by manipulating output voltage and duty cycle. In that way, MEPT system is able to estimate load energy consumption by counting the pulses that is conducted. Meanwhile, with a Digital Control block, minimum energy point can be determined through a Lookup Table 3 (according to output voltage). This invention can estimate the energy consumption of the real time load without switched capacitor, and increase system&#39;s efficiency by adopting PSM control. This system is with low power consumption and small chip area benefiting from that most of the system is digital circuit. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is the block diagram of the system. 
         FIG. 2  is the circuit diagram showing the arrangement of the Current Limit block. 
         FIG. 3  is the circuit diagram showing the arrangement of the DAC (Digital-Analog Converter). 
         FIG. 4  is the block diagram showing the arrangement of the Digital Control block. 
         FIG. 5  is the timing chart showing the operation of the minimum energy point tracking system. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 1  is the block diagram showing the overall arrangement of the minimum energy point tracking Buck converter. The system is consisted of a Digital Control block  1 , a Current Limit block  2  and a DAC  3 . The Digital Control block  1  counts the conducted pulses. Load minimum energy point is at the output voltage where the number of conducted pulses is minimum. Then corresponding D&lt;4:0&gt; and I&lt;5:0&gt; are determined according to the Lookup Table 33 to generate certain duty cycle and output reference voltage. The inputs of the Current Limit block  3  are connected to the I&lt;5:0&gt;, which are corresponding to 6 different duty cycles. DAC_OUT is determined by 5 digits, D&lt;4:0&gt;. 
     In  FIG. 1 , VIN, as the input of Buck converter, is connected to the source of the Power MOSFET  4 . The buck converter, as the Output Unit, is consisted of a Power MOSFET  4 , a diode  5 , an inductor  6 , and a capacitor  7 . VO is connected to the negative input of a comparator  8  and compared with DAC_OUT, which is connected to the positive input port. The output of the comparator  8 , COMP_OUT, and the clock signal, CLK, are both connected to an AND Gate  9 . The output of the AND_Gate  9 , CLK_REF, is connected to the S port of a RS trigger  10  and the input of the Digital Control block. The output of RS trigger  10  is connected to the gate of the Power MOSFET  4  via inverter  11   a . There are two outputs of the Digital Control block  1 . One is the current limit signal, I&lt;5:0&gt;; the other is the DAC signal, D&lt;4:0&gt;. With I&lt;5:0&gt; as input, the Current Limit block  2  outputs different ON time according to different input. D&lt;4:0&gt; determines the output reference voltage with DAC  3 . The output of the Current Limit block  2 , ILIM_OUT, is connected to an input of an OR_Gate  12  via inverter  13 . Maxima ON time signal, DMAX, is connected to the other input of the OR_Gate  12  via another inverter. The output of the OR_Gate  12  is connected to the R port of RS trigger  10 . 
     In  FIG. 2 , NMOSs  14 ˜ 20  build up basic current mirrors. Bias current flows through NMOS  14 . The sources of NMOSs  14 ˜ 20  are connected to ground. The gate and the drain of NMOS  14  are connected together. The gates of NMOSs  14 ˜ 20  are connected together. And, the drains of NMOSs  15 ˜ 20  are connected with a switch respectively, labeled as I 5 , I 4 , I 3 , I 2 , I 1  and I 0  and controlled by I&lt;5:0&gt;. In  FIG. 2 , PMOS  21 &#39;s gate is connected to ground with its dimension proportional to the Power MOSFET  4 &#39;s. A comparator  22  outputs ILIM_OUT, with its negative input port connected to PMOS  21 &#39;s drain and its positive input port connecting to Power MOSFET  4 &#39;s drain. 
     In  FIG. 3 , it is the circuit diagram of DAC  3 . The output of the operational amplifier  23  is connected the gate of MOSFET  24 , with output reference voltage as positive input. The negative input is connected to a sampling resistor  30 , which is connected to ground, and the source of MOSFET  24  via 5 resistors  25 ˜ 29 . Resistors  25 ˜ 29  could be shorted out corresponding to D&lt;4:0&gt; to generate different output reference voltage. The output of the operational amplifier  23  is connected to the gate of MOSFET  24 . MOSFET  24 &#39;s drain is connected to VIN. 
     In  FIG. 4 , it shows the block diagram of the Digital Control block  1 . Considering CLK_REF as input, the output of the Counter  31 , N, are connected to Comparator Unit  32  and compared with register inside, M, which is the minimum N so far. The output of the Comparator Unit determines I&lt;5:0&gt; and D&lt;4:0&gt; according to Lookup Table 33. 
     The following is the introduction of basic principle of MEPT Buck converter and energy model based on PSM control. 
     Input energy of the Buck converter based on PSM control is determined by input voltage, VIN, ON time, and output voltage. It is assumed that ΔE in  is the input energy during each normal turning on period, ΔE R  is the energy consumption of the load every cycle, ΔE L  and ΔE C  are energies dissipated by inductor and capacitor respectively. According to law of conservation of energy,
 
Δ E   in   =ΔE   R   +ΔE   L   +ΔE   C   (1)
 
     In DCM (Discontinuous conduction Mode), the energy dissipated by inductor is zero, ΔE L ≡0. Neglecting output voltage ripple, energy dissipated by capacitor can also be neglected. Therefore,
 
Δ E   in   =ΔE   R   (2)
 
     Taking advantage of basic equilibriums of the Buck converter, the following can be obtain 
     
       
         
           
             
               
                 
                   
                     L 
                     ⁢ 
                     
                       
                         ⅆ 
                         i 
                       
                       
                         ⅆ 
                         t 
                       
                     
                   
                   = 
                   
                     
                       
                         
                           V 
                           IN 
                         
                         - 
                         
                           V 
                           O 
                         
                       
                       ⇒ 
                       
                         
 
                       
                       ⁢ 
                       
                         ⅆ 
                         i 
                       
                     
                     = 
                     
                       
                         
                           
                             
                               V 
                               IN 
                             
                             - 
                             
                               V 
                               O 
                             
                           
                           L 
                         
                         ⁢ 
                         
                           ⅆ 
                           t 
                         
                       
                       ⇒ 
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
             
               
                 
                   i 
                   = 
                   
                     
                       
                         
                           ∫ 
                           0 
                           τ 
                         
                         ⁢ 
                         
                           
                             
                               
                                 V 
                                 IN 
                               
                               - 
                               
                                 V 
                                 O 
                               
                             
                             L 
                           
                           ⁢ 
                           
                             ⅆ 
                             t 
                           
                         
                       
                       ⇒ 
                       
                         
 
                       
                       ⁢ 
                       
                         I 
                         p 
                       
                     
                     = 
                     
                       
                         
                           
                             V 
                             IN 
                           
                           - 
                           
                             V 
                             O 
                           
                         
                         L 
                       
                       ⁢ 
                       
                         T 
                         on 
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     From equation (3) and (4), 
     
       
         
           
             
               
                 
                   
                     Δ 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       E 
                       in 
                     
                   
                   = 
                   
                     
                       1 
                       
                         2 
                         ⁢ 
                         L 
                       
                     
                     ⁢ 
                     
                       
                         T 
                         on 
                         2 
                       
                       ⁡ 
                       
                         ( 
                         
                           
                             V 
                             IN 
                           
                           - 
                           
                             V 
                             O 
                           
                         
                         ) 
                       
                     
                     ⁢ 
                     
                       V 
                       IN 
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
     The following equation can also be obtained: 
     
       
         
           
             
               
                 
                   
                     Δ 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       E 
                       in 
                     
                   
                   = 
                   
                     
                       L 
                       2 
                     
                     ⁢ 
                     
                       I 
                       p 
                       2 
                     
                     ⁢ 
                     
                       
                         V 
                         IN 
                       
                       
                         ( 
                         
                           
                             V 
                             IN 
                           
                           - 
                           
                             V 
                             O 
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
     From equation (5) and (6), in order to maintain constant energy input, with constant V IN  and L, 
                 T   on   2     ⁡     (       V   IN     -     V   O       )       ⁢           ⁢   and   ⁢           ⁢       I   P   2       (       V   IN     -     V   O       )             
should be constant, out of which I p  is inductor current peak.
 
     Assuming the normal on-off and skipped periods of the proposed Buck converter are M and N respectively, the input energy is M ΔE in . According to different output voltage, with certain current peak or ON time, the input energy of each pulse can be maintained constant. In that way, with constant input energy of each pulse, load&#39;s energy consumption can be estimated by counting conducted pulses. 
     With certain algorithm, MEPT system could search for the minimum energy point effectively. 
     In  FIG. 5 , at the beginning of the algorithm, original output reference voltage and corresponding current limit are set to insure the input energy of each pulse constantly. During the first algorithm period, system counts the pulses conducted, N. At the beginning of second period, output reference voltage reduces 50 mV and current peak limit is adapted to keep the input energy of each pulse constantly. Then, conducted pulses, M are counted. If M is less than N, the output reference voltage is reduced another 50 mV, current peak limit is adjusted correspondingly, and normal conducted pulses are counted again. If M is larger than N, the output reference voltage is raised 50 mV, current peak limit is adjusted correspondingly. At this output voltage, it is the minimum energy point of the system. Algorithm ends and output voltage is fixed. 
     In current peak limit block, voltages at drains of POWER MOSFET  4  and PMOS  21  are compared. POWER MOSFET  4  is power PMOS, and PMOS  21  is a PMOS, whose current is the sum of I 0 ˜I 5 . In that way, POWER MOSFET  4 &#39;s current peak is determined 
     In  FIG. 2 , NMOSs  14 ˜ 20  form basic current mirrors and NMOSs  15 ˜ 20  copy current through NMOSs  14 . For PMOS  21  and POWER MOSFET  4 , it is assumed that K(W/L) P1 =(W/L) PPMOS . Since PMOS  21  and POWER MOSFET  4  both are in deep linear region, the following is their conduction resistance: 
     
       
         
           
             
               
                 
                   
                     P 
                     
                       MP 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                   = 
                   
                     1 
                     
                       
                         μ 
                         P 
                       
                       ⁢ 
                       
                         
                           
                             C 
                             ox 
                           
                           ⁡ 
                           
                             ( 
                             
                               W 
                               L 
                             
                             ) 
                           
                         
                         
                           P 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                       
                       ⁢ 
                       
                         ( 
                         
                           
                             V 
                             IN 
                           
                           - 
                           
                             V 
                             con 
                           
                           - 
                           
                             V 
                             th 
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       
                         
                           R 
                           MPP 
                         
                         = 
                           
                         ⁢ 
                         
                           1 
                           
                             
                               μ 
                               p 
                             
                             ⁢ 
                             
                               
                                 
                                   C 
                                   ox 
                                 
                                 ⁡ 
                                 
                                   ( 
                                   
                                     W 
                                     L 
                                   
                                   ) 
                                 
                               
                               PPMOS 
                             
                             ⁢ 
                             
                               ( 
                               
                                 
                                   V 
                                   IN 
                                 
                                 - 
                                 
                                   V 
                                   con 
                                 
                                 - 
                                 
                                   V 
                                   th 
                                 
                               
                               ) 
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                         ⁢ 
                         
                           
                             ( 
                             
                               1 
                               K 
                             
                             ) 
                           
                           
                             
                               μ 
                               P 
                             
                             ⁢ 
                             
                               
                                 
                                   C 
                                   ox 
                                 
                                 ⁡ 
                                 
                                   ( 
                                   
                                     W 
                                     L 
                                   
                                   ) 
                                 
                               
                               
                                 P 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 1 
                               
                             
                             ⁢ 
                             
                               ( 
                               
                                 
                                   V 
                                   IN 
                                 
                                 - 
                                 
                                   V 
                                   con 
                                 
                                 - 
                                 
                                   V 
                                   th 
                                 
                               
                               ) 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
     From above equation (7) and (8), the conduction resistance of PMOS  21  and POWER MOSFET  4  is proportional to W/L. Therefore, R MP1  is K times of R MPP . In  FIG. 2 , with another assumption, that current through NMOSs  15 ˜ 20  is m times of current through NMOSs  14 , the voltage at the negative input of comparator  22  is:
 
 V   −   =V   IN   −mI   BIAS   R   P1   (9)
 
     The positive input of comparator  22  can be expressed as inductor current multiplied with conduction resistance:
 
 V   +   =V   IN   −I   L   R   PPMOS   (10)
 
     From equation (9) and (10), current peak limit block manipulates ON time by controlling inductor current peak. As inductor current is rising, V +  falls from V IN  definitely. When V +  is higher than V − , comparator  22  outputs high and POWER MOSFET  4  maintain conduction. V +  falls as inductor current rises. When V +  is lower than V − , comparator  22  outputs low and POWER MOSFET  4  turns off. In that way, ON time is manipulated. When V + =V − ,
 
 mI   BIAS   R   P1   =I   L   R   PPMOS   (11)
 
     As R MP1  is K times of R MPP , POWER MOSFET  4  turns off when I L =KmI BIAS , in which m is the only variable. In  FIG. 2 , m is determined by I&lt;5:0&gt;. In that way, ON time can be manipulated by controlling I L  with I&lt;5:0&gt;. 
     In  FIG. 3 , basically, the proposed DAC  3  is an amplifier with programmable number of resistors,  25 ˜ 29 , in series. 
     With negative input of operational amplifier  23  is clamped to V REF , then 
                         V     DAC   ⁢           ⁢   _   ⁢           ⁢   OUT       -     V   REF       R     =       V   REF       R   s               (   12   )               
where R is the total resistance of resistors,  25 ˜ 29 . Furthermore,
 
                     V     DAC   ⁢           ⁢   _   ⁢           ⁢   OUT       =       V   REF     ⁡     (     1   +     R     R   sense         )               (   13   )               
where R is determined by D&lt;4:0&gt;. Therefore, the output voltage of DAC  3  is determined by D&lt;4:0&gt;, too.
 
     In  FIG. 4 , Clk_REF is sensed and processed in the Digital Control block  1 . Firstly, Clk_REF is sampled by counting rising edge during certain period. The outputs of Counter  31  are sent to Comparator Unit  32 , where comparing the outputs of this period to that of the last period. After starting up, the system sets output of Counter  31  maximum to make sure that the system could track minimum energy point further. After comparing, according to the result, I&lt;5:0&gt; and D&lt;4:0&gt; of next period should be determined in the Lookup Table 33 below. 
     The following is Lookup Table 1 effective in the system. 
     
       
         
               
               
               
               
               
             
               
               
               
               
               
             
           
               
                   
                 LOOKUP TABLE 1 
               
               
                   
                   
               
               
                   
                 DAC_OUT 
                 IP 
                 D&lt;4:0&gt; 
                 I&lt;5:0&gt; 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 V1 
                 I1 
                 00001 
                 000001 
               
               
                   
                 V2 
                 I2 
                 00010 
                 000010 
               
               
                   
                 V3 
                 I3 
                 00011 
                 000011 
               
               
                   
                 V4 
                 I4 
                 00100 
                 000100 
               
               
                   
                 V5 
                 I5 
                 00101 
                 000101 
               
               
                   
                 V6 
                 I6 
                 00110 
                 000110 
               
               
                   
                 V7 
                 I7 
                 00111 
                 000111 
               
               
                   
                 V8 
                 I8 
                 0100 
                 001000 
               
               
                   
                   
               
             
          
         
       
     
     In the table above, V 1 -V 8  and I 1 -I 8  are following the equation: 
     
       
         
           
             
               
                 
                   
                     Δ 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       E 
                       in 
                     
                   
                   = 
                   
                     
                       L 
                       2 
                     
                     ⁢ 
                     
                       I 
                       p 
                       2 
                     
                     ⁢ 
                     
                       
                         V 
                         IN 
                       
                       
                         ( 
                         
                           
                             V 
                             IN 
                           
                           - 
                           
                             V 
                             O 
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   14 
                   ) 
                 
               
             
           
         
       
     
     In  FIG. 1 , when starting up, the states of DAC  3  and Current Limit block  2  are unknown. D&lt;4:0&gt; and I&lt;5:0&gt; are set to be 00001 and 000001 respectively. If VO is higher than DAC_OUT, comparator  8 &#39;s output and Clk_ref are both low. At this time, the RS trigger  10  outputs high, POWER MOSFET  4  turns off. In that way, one pulse is skipped. If VO is lower than DAC_OUT, the outputs of comparator  8  and Clk_ref are high and that of RS trigger  10  is low. POWER MOSFET  4  turns on, and VSW falls as inductor current rises. When inductor current meets current limit set by Current Limit block  2 , ILIM_OUT turns low and shuts off POWER MOSFET  4 . If ON time set by the Current Limit block  2  is larger than DMAX (much larger than clock pulse), the on-off state of POWER MOSFET  4  is determined by DMAX. During the counting period, Counter  31  counts Clk_ref s rising edge. The algorithm is executed until minimum energy point is found between V 2  and V 8 , where Counter  31 &#39;s output is larger than the last. Then VO is set to be the previous voltage and the algorithm ends.