Abstract:
The present disclosure is applied to touch technology, and provides an integrating circuit. The integrating circuit comprises an impedance unit, an amplifier, an integration capacitor, a discharge capacitor, a first switch and a second switch. The amplifier comprises a first input terminal, a second input terminal and an output terminal configured to output an output signal; the integration capacitor is coupled between the first input terminal and the output terminal; the first switch is coupled between the first input terminal of the amplifier and the second terminal of the discharge capacitor; and the second switch is coupled between the first terminal and the second terminal of the discharge capacitor.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application is a continuation of international application No. PCT/CN2016/113974 filed on Dec. 30, 2016, which claims the priority to Chinese Patent Application No. 201511031728.1, filed on Dec. 31, 2015, both of which are hereby incorporated by reference in their entireties. 
     
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
       [0002]    The present disclosure is applied to touch technology, and more particularly, is related to an integrating circuit and a capacitance sensing circuit capable of sensing a variation of capacitance effectively. 
       2. Description of the Prior Art 
       [0003]    As technology continuously grows, interface of electronic product is more and more convenient. For example, through touch panel, a user may use a finger or stylus to operate on the screen panel and to input information/text/pattern, so as to spare an effort using input devices such as a keyboard or keys. In fact, the touch panel usually includes a sensing panel and a display device disposed behind the sensing panel. The electronic device would determine the meaning of each touch action according to the touching location on the sensing panel and the picture (s) displayed by the display device at the time, and perform operations correspondingly. 
         [0004]    Capacitance touch-control technology performs sensing the capacitance variation of a detection capacitor within a detection circuit to determine the meaning of the touch action. Current capacitance touch-control technology may be classified as self-capacitance touch-control and mutual-capacitance touch-control. The capacitance sensing circuit within the self-capacitance touch-control panel or the mutual-capacitance touch-control panel may convert the capacitance of the detection capacitor as an analog output signal, and an analog-to-digital convertor (ADC) is utilized to convert the analog output signal into a digital signal, for a back-end capacitance determining circuit to determine the capacitance. However, either in the self-capacitance touch-control panel or in the mutual-capacitance touch-control panel, the capacitance variation thereof is quite small, such that a signal component caused by the capacitance variant within the analog output signal is correspondingly small. From another perspective, the analog output signal may include a fixed signal and a variation signal, where the variation signal within the analog output signal is caused by the capacitance variant. The capacitance sensing circuit would determine the capacitance variation of the detection capacitor according to the variation signal within the analog output signal. In other words, the variant signal is critical in capacitance sensing. In order to correctly determine the capacitance variation of the detection capacitor, the ADC with a large dynamic range and a high resolution is utilized to resolve the analog output signal, causing larger circuit complexity and increase of production cost. In another perspective, the large dynamic range and the high resolution of the ADC are mostly occupied by the fixed signal within the analog out signal, such that the critical variation signal in capacitance sensing is not able to be effectively resolved. Therefore, it is necessary to improve the related art. 
       SUMMARY OF THE INVENTION 
       [0005]    The technical problem to be solved by the present disclosure is to provide an integrating circuit, to sense capacitance effectively. 
         [0006]    In order to solve the above technical problem, the present disclosure provides an integrating circuit, including: 
         [0007]    an impedance unit; 
         [0008]    an amplifier, including:
       a first input terminal, coupled to the impedance unit;   a second input terminal; and   an output terminal, configured to output an output signal;   an integration capacitor, coupled between the first input terminal and the output terminal;   a discharge capacitor, including:   a first terminal, configured to receive a first voltage; and   a second terminal;   a first switch, coupled between the first input terminal of the amplifier and the second terminal of the discharge capacitor; and   a second switch, coupled between the first terminal and the second terminal of the discharge capacitor.       
 
         [0018]    In order to solve the above technical problem, the present disclosure provides a capacitance sensing circuit configured to sense a detection capacitance of an detection circuit, including:
       a first analog-to-digital convertor (ADC), configured to generate a first digital signal;   a capacitance determining circuit, coupled to the first ADC, configured to determine a capacitance variation of the detection capacitance according to the first digital signal; and   a first integrating circuit, coupled between the detection circuit and the first ADC, the first integrating circuit including:   an first amplifier, including:   a first input terminal;   a second input terminal; and   an output terminal, configured to output a first output signal to the first ADC;   a first integration capacitor, coupled between the first input terminal and the output terminal of the first amplifier;   a first discharge capacitor, including:   a first terminal, configured to receive a first voltage; and   a second terminal;   a first switch, coupled between the first input terminal of the first amplifier and the second terminal of the discharge capacitor; and   a second switch, coupled between the first terminal and the second terminal of the discharge capacitor.       
 
         [0032]    The integrating circuit provided in the embodiment of the present disclosure utilizes the discharge capacitor and the switch couple to the discharge capacitor to limit the output signal between the maximum voltage and the minimum voltage. In this regard, even after the integrating circuit integrates for a long time, the total integrating voltage may be much larger than the dynamic range of the ADC, without causing the ADC entering into the saturation status. Therefore, the integrating circuit and the capacitance sensing circuit of the present disclosure may lower the requirement of the dynamic range of the ADC, further reduce the circuit complexity and production cost, and sense the capacitance variant effectively. For ADC with a specific accuracy, the present disclosure may enhance the accuracy of the capacitance sensing circuit and enhance the SNR (signal to noise ratio) of the system. In addition, since the discharge capacitor may effectively reduce the maximum voltage of integration, relatively small capacitor may be used as the integration capacitor within the integrating circuit, such that the circuit area is reduced. 
         [0033]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0034]      FIG. 1  is a schematic diagram of a capacitance sensing circuit according to an embodiment of the present disclosure; 
           [0035]      FIG. 2  illustrates a plurality of waveforms of an embodiment of the present disclosure; 
           [0036]      FIG. 3  is a schematic diagram of an integrating circuit according to an embodiment of the present disclosure; 
           [0037]      FIG. 4  is a schematic diagram of a capacitance sensing circuit according to another embodiment of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0038]    In order to make the objects, technical solutions and advantages of the present disclosure become more apparent, the following relies on the accompanying drawings and embodiments to describe the present disclosure in further detail. It should be understood that the specific embodiments described herein are only for explaining the present disclosure and are not intended to limit the present disclosure. 
         [0039]    Please refer to  FIG. 1 , which is a schematic diagram of a capacitance sensing circuit  10  according to an embodiment of the present disclosure. The capacitance sensing circuit  10  applies a signal TX to a detection circuit  100 , and receives a signal RX from the detection circuit  100 . The capacitance sensing circuit  10  senses an detection capacitance CUT of the detection circuit  100  according to the signal TX and the signal RX. 
         [0040]    The capacitance sensing circuit  10  includes an integrating circuit  104 , an analog-to-digital convertor (ADC)  108 , a capacitance determining circuit  102 , a front-end circuit  112  and a mixer  106 . The mixer  106  is coupled between the detection circuit  100  and the integrating circuit  104 , and the mixer  106  includes a multiplier MP and a waveform generator  160 . The mixer  106  inputs an input signal VIN to the integrating circuit  104 . The integrating circuit  104  generates an output signal VOUT according to the input signal VIN. The ADC  108 , coupled to the integrating circuit  104 , is configured to convert the output signal VOUT as/into a digital signal VD. The capacitance determining circuit  102 , coupled to the ADC  108 , is configured to determine a capacitance variation of the detection capacitance CUT according to the digital signal VD. 
         [0041]    The front-end circuit  112  includes an amplifier and a filter including active circuit components. The front-end circuit  112  may adjust a magnitude of the signal RX by adjusting a gain of the amplifier, such that the signal RX would not surpass an operational range of the components of the back-end circuit. The filter is configured to filter out noise. In general, the front-end circuit  112  may flexibly perform filtering and amplifying operation over noise and interference signals, so as to enhance a resistance of the capacitance sensing circuit  10  against noise and further to enhance a signal-to-noise ratio (SNR) of the capacitance sensing circuit  10 . In addition, the front-end circuit  112  including the active components also enhances a driving capability of the circuit, and lowers an influence of the back-end circuit to the front-end detection circuit  100 . In the related art, since passive components are used to obtain charges stored in the detection capacitor by charge-transferring or charge-sharing, which requires another capacitor comparable to or even larger than the detection capacitor, such that circuit area thereof is increased. Including active components may adjust signal magnitudes, such that there is no need for the back-end capacitor to be matched up with the detection capacitor, and the circuit area is therefore reduced. 
         [0042]    The integrating circuit  104  includes: an amplifier Amp, an integration capacitor CI, a discharge capacitor CF, an impedance unit  142 , a control signal generator  140  and switches SW 1 , SW 2 . The amplifier Amp includes a negative input terminal (i.e., first input terminal, denoted as “−”), a positive input terminal (i.e., second input terminal, denoted as “+”) and an output terminal. The positive input terminal of the amplifier Amp receives a reference voltage VREF. The output terminal is configured to output the output signal VOUT. The impedance unit  142  may include a resistor R. A terminal of the resistor R is coupled to the negative input terminal of the amplifier Amp, and another terminal receives the input signal VIN. The resistor R is configured to adjust the integration/filtering characteristic of the integrating circuit  104 , and a ratio/gain between the input signal VIN and the output signal VOUT, such that the output signal VOUT may lie in a dynamic range of the ADC  108  correctly. The integration capacitor CI is coupled between the negative input terminal and the output terminal of the amplifier Amp. A first terminal of the discharge capacitor CF is configured to receive a voltage VS, and a second terminal is coupled to the switch SW 1 , wherein the voltage VS is smaller than the reference voltage VREF. The switch SW 1  is coupled between the negative input terminal of the amplifier Amp and the second terminal of the discharge capacitor CF. The switch SW 2  is coupled between the first terminal and the second terminal of the discharge capacitor CF. The switches SW 1  and SW 2  are controlled by the control signal generator  140 , which means that the control signal generator  140  generates control signals CTL 1  and CTL 2 , to control a conduction status of the switches SW 1  and SW 2 , respectively. 
         [0043]    Operation principles of the capacitance sensing circuit  10  and the integrating circuit  104  are described as followed. In a first stage T 1 , the control signal generator  140  generates the control signal CTL 1  to cutoff the switch SW 1 . At this time, the integrating circuit  104  continuously integrates the input signal VIN, i.e., electronic charges are continuously accumulated in the integration capacitor CI, and the output signal VOUT continuously decreases. In addition, at a period of time during the first stage T 1 , the control signal generator  140  generates the control signal CTL 2  to conduct the switch SW 2 , the discharge capacitor CF stores no charge since the switch SW 2  is conducted. In a second stage T 2 , the control signal generator  140  generates the control signals CTL 1  and CTL 2  to conduct the switch SW 1  and cutoff the switch SW 2 . At this time, since the voltage VS is smaller than the reference voltage VREF, the electronic charges accumulated in the integration capacitor CI would be released toward the discharge capacitor CF, i.e., charging the discharge capacitor CF. When the discharge capacitor CF is charged and saturated, the integration of the input signal VIN continues. Since the integration capacitor CI is coupled to the negative input terminal of the amplifier Amp, when the electronic charges stored in the integration capacitor CI are released to the discharge capacitor CF, the output signal VOUT would be pulled up immediately, until the discharge capacitor CF is charged to be saturated, where the output signal VOUT is pulled up by an amount of 
         [0000]    
       
         
           
             
               
                 C 
                 F 
               
               
                 C 
                 I 
               
             
              
             
               
                 ( 
                 
                   
                     V 
                     REF 
                   
                   - 
                   
                     V 
                     S 
                   
                 
                 ) 
               
               . 
             
           
         
       
     
         [0000]    After the discharge capacitor CF is charged to be saturated, the output signal VOUT continues decreasing since the integrating circuit  104  integrates the input signal VIN. 
         [0044]    Specifically, please refer to  FIG. 2 , which illustrates waveforms of the output signal VOUT and the control signals CTL 1 , CTL 2  varying with respect to time. When the control signals CTL 1 , CTL 2  are high voltage, the switches SW 1 , SW 2  are conducted/ON. When the control signals CTL 1 , CTL 2  are low voltage, the switches SW 1 , SW 2  are cutoff/OFF. The integrating circuit  104  starts to operate at a time to, and the output signal VOUT at this time is the voltage VREF. After the integrating circuit  104  starts to operate, the control signal generator  140  controls the switches SW 1 , SW 2  such that the integrating circuit  104  firstly enters into the first stage T 1 . In the first stage T 1 , the integrating circuit  104  clears electronic charges in the discharge capacitor CF. The integrating circuit  104  continues integrating the input signal VIN, the integration capacitor CI continues accumulating electronic charges, and the output signal VOUT continues decreasing. At a time t 1 , the control signal generator  140  controls the switches SW 1 , SW 2  such that the integrating circuit  104  firstly enters into the second stage T 2 . In the second stage T 2 , the electronic charges accumulated in the integration capacitor CI are released to the discharge capacitor CF, such that the output signal VOUT is pulled up until the discharge capacitor CF is charged to be saturated (corresponding to a time t 2 ). After the time t 2 , the control signal generator  140  may control the switch SW 1  such that the integrating circuit  104  secondly enters into the first stage T 1 , in which the integrating circuit  104  continues integrating the input signal VIN, and the output signal VOUT continues decreasing. During the time the integrating circuit  104  integrating the input signal VIN, the control signal generator  140  may control the switch SW 2  to clear the electronic charges within the discharge capacitor CF. The control signal generator  140  periodically controls the switch SW 1  such that the integrating circuit  104  operates back and forth between the first stage T 1  and the second stage T 2 . Every time in the first stage T 1 , the control signal generator  140  controls the switch SW 2  to clear the electronic charges within the discharge capacitor CF. Until a time t 3 , a signal value of the output signal VOUT is a voltage Vt. A number of times of the integrating circuit  104  entering the second stage T 2  within an operating time period TOP (where the operating time period TOP is referred to a time period from the time t 0  to the time t 3 ) is N times. That is, during the operating time period TOP, the integrating circuit  104  enters into the second stage T 2  by N times. Moreover, the control signal generator  140  may periodically control the integrating circuit  104  to operate back and forth between the first stage T 1  and the second stage T 2  according to a clock signal. In addition, a voltage Vini represents a decrease amount of the output signal VOUT from the integrating circuit  104  starting to operate until firstly entering into the second stage T 2 , due to integration. 
         [0045]    As can be seen from  FIG. 2 , after firstly entering into the second stage T 2 , the output signal VOUT varies between a maximum voltage Vmax and a minimum voltage Vmin, where a voltage difference between the maximum voltage Vmax and the minimum voltage Vmin is 
         [0000]    
       
         
           
             
               
                 
                   C 
                   F 
                 
                 
                   C 
                   I 
                 
               
                
               
                 ( 
                 
                   
                     V 
                     REF 
                   
                   - 
                   
                     V 
                     S 
                   
                 
                 ) 
               
             
             , 
           
         
       
     
         [0000]    and a total integrating voltage VO of the integrating circuit  104  from the time t 0  to the time t 3  is 
         [0000]    
       
         
           
             
               V 
               O 
             
             = 
             
               
                 V 
                 REF 
               
               - 
               
                 V 
                 ini 
               
               - 
               
                 N 
                  
                 
                   
                     C 
                     F 
                   
                   
                     C 
                     I 
                   
                 
                  
                 
                   ( 
                   
                     
                       V 
                       REF 
                     
                     - 
                     
                       V 
                       S 
                     
                   
                   ) 
                 
               
               - 
               
                 V 
                 t 
               
             
           
         
       
     
         [0000]    (which means that a total integrating electronic charges accumulated in the integration capacitor CI between the time t 0  and the time t 3  is CI(VO−VREF)). 
         [0046]    In order to sense a capacitance variation of the detection capacitance CUT, the capacitance sensing circuit  10  may utilize the integrating circuit  104  to perform the above operations in a first time, and obtains a first total integrating voltage VO 1  as 
         [0000]    
       
         
           
             
               V 
               
                 O 
                  
                 
                     
                 
                  
                 1 
               
             
             = 
             
               
                 V 
                 REF 
               
               - 
               
                 V 
                 ini 
               
               - 
               
                 
                   N 
                   1 
                 
                  
                 
                   
                     C 
                     F 
                   
                   
                     C 
                     I 
                   
                 
                  
                 
                   ( 
                   
                     
                       V 
                       REF 
                     
                     - 
                     
                       V 
                       S 
                     
                   
                   ) 
                 
               
               - 
               
                 
                   V 
                   
                     t 
                      
                     
                         
                     
                      
                     1 
                   
                 
                 . 
               
             
           
         
       
     
         [0000]    The capacitance sensing circuit  10  may further utilize the integrating circuit  104  to perform the above operations again in a second time, and obtains a second total integrating voltage VO 2  as 
         [0000]    
       
         
           
             
               V 
               
                 O 
                  
                 
                     
                 
                  
                 2 
               
             
             = 
             
               
                 V 
                 REF 
               
               - 
               
                 V 
                 ini 
               
               - 
               
                 
                   N 
                   2 
                 
                  
                 
                   
                     C 
                     F 
                   
                   
                     C 
                     I 
                   
                 
                  
                 
                   ( 
                   
                     
                       V 
                       REF 
                     
                     - 
                     
                       V 
                       S 
                     
                   
                   ) 
                 
               
               - 
               
                 
                   V 
                   
                     t 
                      
                     
                         
                     
                      
                     2 
                   
                 
                 . 
               
             
           
         
       
     
         [0000]    Voltages Vt 1  and Vt 2  in the above are voltage values of the output signal VOUT after the integrating circuit  104  integrates for the operating time period TOP in the first time and the second time, respectively, and the number of times N 1  and the number of times N 2  are the number of times of the integrating circuit  104  entering the second stage T 2  during the operating time period TOP at the first time and the second time, respectively. 
         [0047]    Notably, the capacitance variation of the detection capacitance CUT is related to a voltage difference VDIFF between the first total integrating voltage VO 1  and the second total integrating voltage V 02 , and the voltage difference VDIFF is 
         [0000]    
       
         
           
             
               
                 V 
                 DIFF 
               
               - 
               
                 V 
                 
                   O 
                    
                   
                       
                   
                    
                   2 
                 
               
               - 
               
                 V 
                 
                   O 
                    
                   
                       
                   
                    
                   1 
                 
               
             
             = 
             
               
                 
                   ( 
                   
                     
                       N 
                       1 
                     
                     - 
                     
                       N 
                       2 
                     
                   
                   ) 
                 
                  
                 
                   
                     C 
                     F 
                   
                   
                     C 
                     I 
                   
                 
                  
                 
                   ( 
                   
                     
                       V 
                       REF 
                     
                     - 
                     
                       V 
                       S 
                     
                   
                   ) 
                 
               
               + 
               
                 V 
                 
                   t 
                    
                   
                       
                   
                    
                   1 
                 
               
               - 
               
                 
                   V 
                   
                     t 
                      
                     
                         
                     
                      
                     2 
                   
                 
                 . 
               
             
           
         
       
     
         [0000]    In other words, the capacitance variation of the detection capacitance CUT is only related to the number of times N 1 , the number of times N 2 , the voltage Vt 1  and the voltage Vt 2 . If it is properly designed such that the number of times N 1  and the number of times N 2  are the same, the voltage difference VDIFF is only related to the voltage Vt 1  and the voltage Vt 2 , i.e., the capacitance variation of the detection capacitance CUT is only related to the voltage Vt 1  and the voltage Vt 2 . In addition, the voltage Vt 1  and the voltage Vt 2  is within a range between the maximum voltage Vmax and the minimum voltage Vmin. In other words, a dynamic range of the ADC  108  is only required to be between the maximum voltage Vmax and the minimum voltage Vmin, which lower a requirement of the dynamic range of the ADC  108 . 
         [0048]    As can be seen, the embodiment of the present disclosure utilizes the integrating circuit  104  to limit the output signal VOUT between the maximum voltage Vmax and the minimum voltage Vmin. Even after the integrating circuit  104  integrates for the operating time period TOP, the total integrating voltage VO may be much larger than the dynamic range of the ADC  108 , without causing the ADC  108  entering into a saturation status. Compared to the related art, the present disclosure may lower the requirement of the dynamic range of the ADC  108 , and further reduce the circuit complexity and production cost. For ADC with a specific accuracy, the present disclosure may enhance the accuracy of the capacitance sensing circuit and the SNR of the system. In addition, since the discharge capacitor may effectively reduce a maximum voltage of integration, a relatively small capacitor may be used as the integration capacitor CI within the integrating circuit  104 , such that the circuit area is reduced. 
         [0049]    Notably, the embodiments stated in the above are utilized for illustrating the concept of the present disclosure. Those skilled in the art may make modifications and alterations accordingly, and not limited herein. For example, the control signal generator  140  is not limited to control the integrating circuit  104  according to the clock signal to operate back and forth between the first stage T 1  and the second stage, the control signal generator  140  may generate the control signals CTL 1  and CTL 2  according to the output signal VOUT. For example, when the output signal VOUT is lower than the minimum voltage Vmin, the control signal generator  140  generates the control signals CTL 1  and CTL 2 , such that the integrating circuit  104  enters into the second stage T 2 , so as to charge the discharge capacitor CF and pull up the output signal VOUT. 
         [0050]    In addition, the resistor R in the integrating circuit  104  is used to adjust a ratio between the input signal VIN and the output signal VOUT, which is not limited thereto. A switched-capacitor module may further be utilized to adjust the ratio between the input signal VIN and the output signal VOUT, i.e., the resistor R in the integrating circuit  104  may be replaced with the switched-capacitor module. For example, please refer to  FIG. 3 , which is a schematic diagram of an integrating circuit  304  according to an embodiment of the present disclosure. The integrating circuit  304  is similar to the integrating circuit  104 , and thus, the same components are denoted by the same notations. Different from the integrating circuit  104 , the integrating circuit  304  includes an impedance unit, and the impedance unit includes a switched-capacitor module  302 , a terminal of the switched-capacitor module  302  is coupled to the negative input terminal of the amplifier Amp, another terminal is configured to receive the input signal VIN. 
         [0051]    The switched-capacitor module  302  includes a capacitor CS and switches S 1 , S 2 , S 3 , S 4 . The switch S 1  are coupled to a first terminal of the capacitor CS, configured to receive the input signal VIN. The switch S 2  is coupled between the first terminal of the capacitor CS and the ground. The switch S 3  is coupled between a second terminal of the capacitor CS and the negative input terminal of the amplifier Amp. The switch S 4  is coupled between the second terminal of the capacitor CS and the ground. The switches S 1 , S 2 , S 3  and S 4  may be controlled by clock control signals ph 1  and ph 2 , where the clock control signals ph 1  and ph 2  are mutually orthogonal (i.e., the time of the clock control signals ph 1  and ph 2  being high voltage are not mutually overlapped). Specifically, in one embodiment, the clock control signal ph 1  may be used to control the conduction status of the switches S 1  and S 3 , and the clock control signal ph 2  may be used to control the conduction status of the switches S 2  and S 4 . In another embodiment, the clock control signal ph 1  may be used to control the conduction status of the switches S 1  and S 4 , and the clock control signal ph 2  may be used to control the conduction status of the switches S 2  and S 3 . As long as the switched-capacitor module  302  is utilized to adjust the ratio between the input signal VIN and the output signal VOUT, and the clock control signals ph 1  and ph 2 , which are the mutually orthogonal, are utilized to control the conduction status of the switches S 1 , S 2 , S 3  and S 4 , it is within the scope of the present disclosure. 
         [0052]    In addition, the capacitance sensing circuit  10  only integrates the in-phase component of the signal RX, which is not limited thereto. The capacitance sensing circuit  10  may integrate the in-phase component as well as the quadrature component of the signal RX at the same time, so as to sense the detection capacitance CUT more accurately. For example, please refer to  FIG. 4 , which is a schematic diagram of a capacitance sensing circuit  40  according to another embodiment of the present disclosure. The capacitance sensing circuit  40  is similar to the capacitance sensing circuit  10 , and thus, the same components are denoted by the same notations. Similar to the capacitance sensing circuit  10 , the capacitance sensing circuit  40  utilizes an integrating circuit  404 _ a  to integrate the in-phase component of the signal RX. Different from the capacitance sensing circuit  10 , the capacitance sensing circuit  40  utilizes a phase rotator  462  and a multiplier MP 2  included in a mixer  406  to extract the quadrature component of the signal RX, and utilizes an integrating circuit  404 _ b  to integrate the quadrature component of the signal RX. The integrating circuits  404 _ a  and  404 _ b  are coupled to ADCs  408 _ a  and  408 _ b , respectively. The ADCs  408 _ a  and  408 _ b  are configured to convert the output signal VOUT 1  and VOUT 2  generated by the integrating circuits  404 _ a  and  404 _ b  as digital signals VD 1  and VD 2 , respectively. The capacitance determining circuit  102  may determine the capacitance variation of the detection capacitance CUT according to the digital signals VD 1  and VD 2 , such that the capacitance is sensed more accurately. 
         [0053]    In addition, a control signal generator  440  generates the control signals CTL 1 , CTL 2 , CTL 3  and CTL 4 , to control the conduction status of the switches SW 1 , SW 2 , SW 3  and SW 4 , respectively. The mechanism controlling the conduction status may be referred to the paragraphs stated in the above, which is not narrated herein. Notably, in  FIG. 4 , the integrating circuits  404 _ a  and  404 _ b  have the circuit structure which is the same as the integrating circuit  104 , which is not limited thereto. The integrating circuits of the current embodiment may be have the circuit structure which is the same as the integrating circuit  304  (i.e., the resistors R 1  and R 2  in the integrating circuits  404 _ a  and  404 _ b  are replaced by the switched-capacitor module  302 ), which is also within the scope of the present disclosure. 
         [0054]    As can be seen, the integrating circuit and the capacitance sensing circuit in the embodiment of the present disclosure utilize the discharge capacitor and the switch couple to the discharge capacitor to limit the output signal between the maximum voltage and the minimum voltage. In this regard, even after the integrating circuit integrates for a long time, the total integrating voltage may be much larger than the dynamic range of the ADC, without causing the ADC entering into the saturation status. Therefore, the integrating circuit and the capacitance sensing circuit of the present disclosure may lower the requirement of the dynamic range of the ADC, and further reduce the circuit complexity and production cost. For ADC with a specific accuracy, the present disclosure may enhance the accuracy of the capacitance sensing circuit and the SNR of the system. In addition, since the discharge capacitor may effectively reduce the maximum voltage of integration, relatively small capacitor may be used as the integration capacitor within the integrating circuit, such that the circuit area is reduced. 
         [0055]    The foregoing is only preferred embodiments of the present disclosure, it is not intended to limit the present disclosure, any modifications within the spirit and principles of the present disclosure made, equivalent replacement and improvement, etc., should be included in this within the scope of the disclosure. 
         [0056]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.