Abstract:
A divider divides down the output of a high frequency oscillator to generate a master clock signal MCS for the purposes of sampling an incoming composite video signal CVS. A skew measuring circuit latches the current state of the divider at a predetermined edge of every incoming horizontal sync signal pulse IHSSP to provide skew data representative of the timing or phase offset between the clock signal MCS and the incoming horizontal sync signal IHSS at the start of each new line of picture information.

Description:
This invention relates to an apparatus for determining the phase of the sampling clock relative to the incoming horizontal sync signal IHSS in a digital television (TV) receiver. 
     BACKGROUND 
     In a digital TV receiver, a broadcast analog color video signal is applied to a conventional receiving antenna. The signal received by the antenna is processed by an analog tuner and intermediate frequency (IF) circuitry. A baseband composite video signal CVS from the IF circuitry is applied to an analog-to-digital (A/D) converter. The A/D converter develops digital representations of the analog, baseband composite video signal CVS in response to a sampling or master clock signal MCS. The digital samples are processed in digital circuits to appropriately condition the luminance Y and chrominance C components of the composite video signal CVS for application to the matrix circuits of the TV receiver. The Red (R), Green (G) and Blue (B) signals developed by the matrix circuits are converted back to the analog format for application to the display device. 
     For chroma demodulation, it is advantageous to set the frequency of the sampling clock signal MCS at four (4) times the color subcarrier rate F SC , and to phase lock the 4 F SC  clock signal to the color burst signal BS incorporated in the incoming composite video signal CVS. Sampling the chrominance signal using a 4 F SC  burst locked clock (BLC) produces the following sample sequence: -(B-Y),-(R-Y),(B-Y),(R-Y),-(B-Y) and so on. Demodulation may be accomplished by merely demultiplexing the above sample sequence into separate R-Y and B-Y data streams. 
     However, for memory based features (e.g., pix-in-pix, freeze picture, zoom, recursive filtering, etc.), it is desirable to process the video signal with a line locked clock (LLC). A line locked clock produces a fixed integer number (e.g., 910 in the NTSC format) of sampling points per horizontal line. This simplifies memory based video features processing (e.g., line, field or frame memories), because the respective samples are vertically aligned (i.e., TV raster is orthogonally sampled). 
     For a standard NTSC video signal (e.g., broadcast TV signal), a sampling clock frequency, which is an even integer multiple of the color subcarrier frequency F SC , contains a fixed integer number of clock pulses in every horizontal line period. The color subcarrier frequency F SC  is established at 455/2 times the horizontal line frequency F H  (i.e., F SC  =(455/2)·F H ) in a standard NTSC TV Signal. A sampling clock frequency F MCS  of 4 F SC  has exactly 910 clock periods (4×455/2) in every horizontal line period. For a standard NTSC video signal, a clock signal may be concurrently burst locked and line locked, thereby facilitating both chroma demodulation and memory based applications (e.g., zoom). 
     However, not all NTSC compatible TV signals conform precisely to the NTSC standard format. For example, signals produced by a video cassette recorder (VCR) have varying horizontal line periods in the reproduced signal. This results in a variation in the number of clock pulses developed per horizontal line (e.g., 909.9, 910, 910.1, etc.). In general, for non-standard TV signals, it is not possible that a clock signal be simultaneously burst locked and line locked. 
     One previously known approach for processing non-standard TV signals in the digitial domain employs a burst locked clock. The use of a burst locked clock simplifies chroma demodulation. However, a burst locked clock produces a variation in the number of clock pulses per horizontal line, and, therefore, causes a line-to-line variation in the phase of the clock signal relative to the incoming horizontal synchronizing signal IHSS. The line-to-line timing or phase variation (i.e., skew errors) of the clock signal relative to the horizontal sync signal causes line-to-line misalignment of the picture elements (pixels) displayed on the TV screen, thereby requiring skew correction for memory-based features. 
     In order to compensate for the line-to-line misalignment of the pixels before they are written into the memory in a burst locked clock system, the input signal samples are time shifted or skew corrected for the phase differences between the incoming horizontal sync signal IHSS and the sampling clock signal MCS. Additionally, the signal samples read out from the memory are corrected for skew errors prior to their application to the matrix circuits of the TV receiver. U.S. Pat. No. 4,638,360, issued to Christopher, et al., and entitled &#34;TIMING CORRECTION FOR A PICTURE-IN-PICTURE TELEVISION SYSTEM&#34;, describes illustrative circuitry, responsive to a skew signal SS, for correcting skew errors in the incoming and outgoing signals in a memory-based video signal processing system, which uses a burst locked clock. 
     Another approach for processing non-standard TV signals in the digital domain uses an asynchronous or free-running clock. An advantage of an asynchronous clock system is that complicated circuitry (e.g., including a voltage controlled oscillator or VCO) is not required for locking the phase of the clock signal with the color burst phase. However, an asynchronous clock system requires skew correction for memory-based features when non-standard video signals are processed. Another disadvantage of an asynchronous clock system is that chroma demodulation is more complicated. 
     A skew measuring circuit for determining the phase errors (also known as timing or skew errors) between the clock signal and the incoming horizontal sync signal IHSS is described in detail in a commonly-assigned, copending U.S. patent application Ser. No. 761,179, entitled &#34;TIMING CORRECTION CIRCUITRY AS FOR TV SIGNAL RECURSIVE FILTERS&#34;, and filed in behalf of Willis, et al (now U.S. Pat. No. 4,667,240). An integral circuit (IC) wich includes a functionally similar skew measuring circuit is the Deflection Processor Unit (DPU2532) referred to in the ITT data book &#34;DIGIT 2000 NTSC DOUBLE-SCAN VLSI DIGITAL TV SYSTEM&#34; , published by ITT Intermetall Semiconductors, Freiburg, W. Germany. 
     SUMMARY OF THE INVENTION 
     In accordance with this invention, an alternative circuit is described for providing skew data indicative of the phase error of the clock signal MCS relative to the incoming horizontal sync signal IHSS. A divider divides down a high frequency oscillator signal HFOS to generate the master clock signal MCS. A control circuit responsive to the incoming horizontal sync signal IHSS and the high frequency oscillator signal HFOS generates a control signal pulse CSP at the start of each new line. A state capturing circuit coupled to the divider and responsive to the control signal CS provides the skew data once every horizontal line. As previously indicated, the skew data is used for correcting phase or timing errors in memory-based systems in the manner described in the aforementioned U.S. Patent issued to Christopher et al. and U.S. patent patent issued to Willis, et al. 
    
    
     IN THE DRAWINGS 
     FIG. 1 is a block diagram representation of an apparatus for generating skew data in accordance with the principles of the present invention; and 
     FIG. 2 illustrates the waveform diagrams useful in understanding the operation of the FIG. 1 skew data generating apparatus. 
    
    
     DETAILED DESCRIPTION 
     It is assumed that the incoming baseband video signal CVS nominally conforms to the NTSC standard format. Examples of signals conforming nominally to the NTSC standard format are video signals produced by a video cassette recorder (VCR) (hereinafter, non-standard video signals). It is further assumed that the desired, nominal clock frequency F MCS  is four (4) times the color subcarrier frequency F SC , which translates to 14.3 MHZ in the NTSC format. 
     It is well-known in the art that the NTSC video signal includes periodic horizontal and vertical synchronizing signals interposed between succesive lines and fields of picture information. Additionally, in order to allow the TV circuits to reconstruct the color subcarrier signal for the purposes of chroma demodulation, several cycles of the color subcarrier signal (known as the burst signal BS) are inserted into the composite video signal during the horizontal blanking intervals. 
     FIG. 1 depicts an apparatus 20 for generating a master clock signal MCS and the accompanying skew data in accordance with this invention. The FIG. 1 apparatus 20 includes a free running oscillator 22 for providing an asynchronous, fixed high frequency oscillatory signal HFOS. The frequency F HFOS  of the free running oscillator 22 is established at a fixed integer multiple K (e.g., 32) of the desired nominal frequency (e.g., 4 F SC ) of the master clock signal MCS. 
     Although it is assumed herein that the oscillator 22 is free running, the subject invention is equally applicable to a burst locked oscillator. In that case, conventional circuitry (e.g., including a voltage controlled oscillator VCO) may be provided for locking the phase of the oscillatory signal HFOS to the phase of the burst signal BS included in the incoming composite video signal CVS. 
     The choice of the oscillator frequency F HFOS  is determined by the timing resolution required for the picture elements and by the circuit designer&#39;s convenience. It is advantageous to establish the multiple K (F HFOS  /4.F SC ) equal to an integer power of two (i.e., K=2 2 , where n is an integer) to simplify the circuit design (e.g., by allowing the use of a ripple counter configuration). 
     A frequency divide-by-K circuit 30 (hereinafter, divider) is coupled to the output terminal 24 of the oscillator 22 for generating the master clock signal MCS at an output terminal 40. The divider 30 comprises a plurality (n) of toggle flip-flops 32, 34, 36 and 38 connected in a ripple configuration. 
     The FIG. 1 apparatus 20 includes a circuit 50, responsive to the incoming horizontal sync signal IHSS and the high frequency oscillatory signal HFOS, for generating a control signal CS. The horizontal sync signal IHSS is a continuous time analog signal derived from the phase locked loop portion of conventional sync separator and deflection circuits 60 of the TV receiver. 
     The control circuit 50 includes a pair of D flilp-flops 52, 54 and a NOR gate 56. The clock inputs of the flip-flops 52 and 54 are coupled for receiving the high frequency oscillatory signal HFOS. The incoming analog horizontal sync signal IHSS is applied to the data input of the first flip-flop 52. The Q 1  output of the first flip-flop 52 is applied to the data input of the second flip-flop 54. The outputs Q 1  and Q 2  of the flip-flops 52 and 54 are applied to the respective input terminals of the NOR gate 56. 
     The operation of the control circuit 50 will be explained in conjunction with the FIG. 2 waveforms. When the data terminal of the flip-flop 52 becomes a logical zero (waveform 2.b), the output Q 1  thereof goes from a logical one to a logical zero (waveform 2.c) at the occurrence of the next positive going edge 70 of the high frequency oscillator signal HFOS (waveform 2.a). The output Q 1  of the flip-flop 52 remains a logical zero as long as its data input is biased at a logical zero. The output Q 1  of the flip-flop 52 goes back to a logical one state (waveform 2.c) in response to the very first positive going edge 72 occurring after the data input of the flip-flop 52 is biased at a logical one state. 
     The output Q 2  of the second flip-flop 54 goes from a logical zero state to a logical one state (waveform 2.e) in response to the first positive going edge 80 occurring after the data input Q 1  /D 2  thereof becomes a logical one (waveform 2.d). The output Q 2  becomes a logical zero (waveform 2.e) in response to the very next positive going edge 82 occurring after the data input Q 1  /D 2  of the flip-flop 54 is biased at a logical zero state. 
     The NOR gate 56 produces a control signal pulse CSP (waveform 2.f) when both inputs Q 1  and Q 2  are simultaneously low. Thus, the control circuit 50 outputs a pulse CSP following the occurrence of a predetermined edge 62 (e.g., a negative going edge) of the continuous time horizontal sync signal pulse IHSSP at the start of each new line of picture information. 
     The skew measuring circuit 90 comprises an equal plurality (n) of D flip-flops 92, 94, 96 and 98 having their data inputs coupled for receiving the respective outputs Q 1 , Q 2 , Q 3 , . . . Q n  of the first set of flip-flops 32-38, and having their clock inputs coupled for receiving the control signal CS. THe second set of flip-flops 92-98 latch the current divider state at the beginning of each new line of picture information in response to a predetermined edge (e.g., positive going edge) of the control signal CS. The outputs Q 1 , Q 2 , Q 3  . . . Q n  of the second set of flip-flops 92-98 represent the skew data indicative of the timing or phase error between the clock signal MCS and the incoming horizontal sync signal IHSS at the start of each new horizontal line. 
     As previously indicated, the skew correction circuits (of the type described in the afore-mentioned Willis et al. patent application and the Christopher et al. patent) correct timing or phase errors in the video signals written into the memory and read out therefrom in response to the skew data provided by the skew measuring circuit 90 of the subject invention. It is believed that the subject skew measuring circuit 90 is relatively simple in construction and cost effective.