Abstract:
A power supply system for use in conjunction with digital systems and particularly adapted to avoid impairment of digital system performance by power supply generated noise. The clock frequency of the digital system is monitored, divided and then applied to control the switching frequency of a D.C. to D.C. power converter. The converter thus switches at a synchronized submultiple of the digital clock frequency such that switching transients are confined to transition times within the digital system.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates broadly to the improvement of the integrity of digital systems and more specifically to an improved power supply system, which eliminates adverse effects of power supply generated noise upon digital systems. 
     In the prior art, it is well-known to use unbalanced magnetic core D.C. to D.C. conversion in power supply systems. When D.C. to D.C. conversion is used in conjunction with digital systems, deleterious effects can arise from the unwanted noise produced as a result of the A.C. excitation of transformer coils associated with D.C. to D.C. converters. If the digital system is not protected in some manner from the noise produced by switching transients in the power supply, such transient noise will appear on the logic lines within the digital system and result in erroneous detection of data bits. While many advances have been made in the improvement of D.C. to D.C. converter power supplies themselves, prior art approaches to protecting digital systems from switching transients have remained confined to the use of extensive R.F. shielding and bulky feed-through filters. Such brute force shielding of the converter and filtering of the power lines results in increased expense, weight and cost of the digital system. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the invention to eliminate the adverse effects of power supply generated noise upon digital systems. 
     It is another object of the invention to provide a more effective, less expensive and more efficient method for eliminating the adverse effects of power supply switching transients on the integrity of digital systems. 
     It is an additional object of the invention to improve power supplies used in conjunction with digital systems. 
     It is a particular object of the invention to provide a power supply system employing the advantages of D.C. to D.C. conversion while avoiding the disadvantages occasioned by noise generation associated with such conversion. 
     These and other objects of the invention are accomplished by controlling the switching frequency within a D.C. to D.C. converter to be an exact submultiple of the clock or bit rate of the associated digital system, thus causing the D.C. to D.C. converter to switch only during bit transitions within the digital system. This control is accomplished by tapping the system clock or bit rate signal and feeding the tapped signal to a divider, which produces an output signal whose frequency is a submultiple of the clock or bit rate. This submultiple signal is then utilized to control the switching frequency of the D.C. to D.C. converter. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     Other objects, advantages and features of this invention will become more apparent after consideration of the accompanying detailed description, appended claims and drawings of which: 
     FIG. 1 is a schematic block diagram of the power supply system of the preferred embodiment of the invention. 
     FIG. 2 is a signal diagram illustrating the effect of power converter switching transients on logic lines. 
     FIG. 3 is a schematic diagram particularly showing the driver-converter circuitry of the preferred embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The technique of the invention is best understood by reference to FIG. 2, which shows the effect of unwanted transients upon digital data patterns. As a result of the fast switching time necessary for high effeciency in D.C. to D.C. converters, such converters generate electromagnetic radiation, which manifests itself on logic lines as current or voltage transients 23, 25. At the logic &#34;1&#34; or true level, the positive portion of the transient 24 is clamped at, or near a voltage level V cc . However, the negative portion of the transient 26 can swing freely towards the logic &#34;0&#34; or false level. If the negative portion of the transient 26 remains at the &#34;0&#34; level for a time within the response time of the system, a logic &#34;0&#34; will be indicated where only a logic &#34;1&#34; level should have been present. Thus, errors can be introduced into the system, resulting in improper system procedure or incorrect data readout. 
     According to the invention such problems may be eliminated by confining the occurrence of power converter transients to bit transitions 29 within the bit stream 27. In the preferred embodiment of the invention, this confinement is accomplished by synchronizing the switching frequency within the D.C. to D.C. converter to be a submultiple of the digital system clock rate. 
     In the preferred embodiment of the invention, this synchronization is accomplished by the power supply system shown generally in FIG. 1. The system includes a clock buffer 12, which transfers a sample of the system clock or bit rate from the system clock or bit rate generator 11 to a modulo-N divider 13. The modulo-N divider produces a submultiple of the system clock or bit rate signal, which is used to trigger a flip-flop driver 15. The flip-flop driver 15 in turn controls the switching of the converter switching transistors 17, which serve to modulate the D.C. input voltage supplied by supply source 19. This modulation causes transfer of power from the primary windings 20 of the converter transformer 21. Since the frequency of the flip-flop driver is a submultiple of the system clock rate, the switching frequency within the D.C. to D.C. converter coils 20, 22 is likewise a submultiple of the system clock or bit rate. 
     The clock buffer 12 minimizes loading of the clock generator 11 and prevents feedback from the modulo-N divider 13 into the clock generator 11. This buffer stage 12 can be simply constructed by connecting an operational amplifier as a unity gain voltage follower, thus presenting a high voltage impedance to the clock generator 11 and a low driving source impedance to the modulo-N divider 13. Thus, in the preferred embodiment, the intermediate signal developed by the buffer 12 and supplied to the divider 13 has the same frequency as the signal produced by the system clock or bit rate generator 11. 
     The modulo-N divider 13 of the preferred embodiment is a programmable frequency divider whose divisor N is the ratio of the clock rate developed to twice the synchronized operating frequency of the converter or: ##EQU1## For example, if the clock frequency equals 1 mHz and the desired switching frequency of the D.C. to D.C. converter is 20 kHz, then N equals 25. This magnitude of division can be easily achieved with two quinary dividers. Any other whole integer can be obtained by utilizing a maximal sequence generator having a maximum number of stable states of 2 N   -1  where N is the total number of flip-flops used in the generator. 
     The flip-flop driver 15 serves to convert the single-phase signal from the modulo-N divider to the split phase signal necessary for alternately energizing the switching transistors Q3, Q4 shown in FIG. 3. Operation of the flip-flop 15 is in its simplest mode--toggling the clock input. Operated in this manner, the Q and Q flip-flop outputs provide a square wave to the D.C. to D.C. converter at 1/2 the output rate of the divider. 
     As shown in FIG. 3, the D.C. to D.C. converter circuit of the preferred embodiment is based upon two primary windings L p1  and L p2  on transformer T1 and two switching transistors Q1, Q2. The windings L p1 , L p2  are connected in common to a source of D.C. voltage 19 at a common point 31. The opposite terminal 32 of the first primary winding L p1  is connected to the collector of a first switching transistors Q1, and the other terminal 33 of the second primary winding L p2  is connected to the collector of a second switching transistor Q2. The base of the first switching transistor Q1 is connected by a resistor R2 to the first terminal of a first feedback coil L f1 , while the base of the second switching transistor Q2 is connected via the resistor R3 to the first terminal of a second feedback coil L f2 . The respective second terminals of the feedback coils L f1  and L f2  are connected in common via a resistor R1 to the voltage source 19 and to ground via a diode D1. Together the resistor R1 and the diode D1 comprise a starting circuit for the D.C. to D.C. converter. 
     Additional elements are added to the circuit to perform frequency bypass and protection functions. In particular, clamp diodes D2, D3 are connected respectively across the base emitter junctions of switching transisters Q1 and Q2 in order to limit the reverse base-emitter voltage across Q1 and Q2. Additionally, an electrolytic capacitor C4 and a ceramic capacitor C5 are connected from the voltage source 19 to ground. These capacitors form a broad-band, low impedance capacitor which effectively bypasses the fundamental converter switching frequency and all higher harmonics. 
     From a broad perspective, the converter circuitry of FIG. 3 operates as follows. A. D.C. supply voltage 19 is applied to an A.C. intermediate stage including elements Q1, Q2, L p1 , L p2 , L f1 , L f2 , R2, R3 which cooperate to produce an A.C. oscillation. The level of this oscillation is controlled by the D.C. power supplied by the source 19. The intermediate stage includes a transformer T1, which when excited on its primary side by the A.C. oscillation produces a second alternating voltage on its secondary side. This second voltage can be supplied to a D.C. stage including rectification circuitry for producing a D.C. output at the transformed voltage level. 
     More particularly, operation of the converter in its free-running mode occurs when a D.C. voltage is applied at the terminal 19 and thus to the bases of the switching transistors Q1, Q2 through the starting resistor R1. Turn-on of the second switching transistor Q2 is favored by making the second current limiting resistor R3 lower in value as compared to the first current limiting resistor R2. 
     After the second switching transistor Q2 is turned on, its base current increases, aided by a feedback current produced by the second feedback winding L f2 . Concurrently, the collector current through the primary coil L p2  increases. When the second switching transistor Q2 is driven into saturation by the increasing base current, the collector current ceases to increase, resulting in a collapsing field in the second primary coil L p2  and a resultant flux reversal, which serves to turn on the first switching transistor Q1. This transistor Q1 likewise proceeds to saturate under the increasing base drive from the first feedback coil L f1 . The resultant stabilization of collector current turns off the first switching transistor Q1 and again turns on the second switching transistor Q2. This alternate energization of the switching transistors Q1, Q2 sets up an oscillating electrical signal in the windings of the transformer T1, resulting in the transfer of voltage from the primary windings L p1  and L p2  to the secondary winding L s1 , L s2  of the transformer T1. The voltage thus created at the secondary windings L s1  and L s2  may be subjected to rectification and regulation as known in the prior art to provide a D.C. power source for an associated digital system. 
     In the preferred embodiment, the excitation of the transformer T1 also serves to develop a voltage across first and second auxiliary windings L v1  and L v2 . These windings are provided to develop a bias voltage for the flip-flop driver 15, the modulo-N divider 13, and the system clock or bit rate generator 11. Both the auxiliary windings L v1 , L v2  are identical (bifilar wound) with sufficient turns to provide the required bias voltage in conjunction with full wave rectifier diodes D4 and D5 and a filter capacitor C1. Since the voltage developed across the auxiliary windings L v1 , L v2  is essentially a square wave, the filter capacitor C1 can be small and the bias voltage obtained will be the voltage developed across the auxiliary winding less one diode drop. 
     In order to accomplish synchronization with the digital system clock rate, the free running D.C. to D.C. converter as thus far described is subjected to the output Q, Q of the flip-flop 15 by means of first and second driver transistors Q3, Q4. The base of the transistor Q3 is connected to the Q output of the flip-flop 15 via a capacitor C2 and a resistor R4, and the base of transistor Q4 is connected to the Q output of the flip-flop 15 by a capacitor C3 and a resistor R5. This RC coupling to the bases of the driver transistors Q3, Q4 eliminates any D.C. component associated with the Q and Q outputs. The respective emitters of the driver transistors Q3 and Q4 are grounded, while their collectors are connected via Shottky diodes D6, D7 to the respective bases of the switching transistors Q1 and Q2. 
     The driver transistors Q3, Q4 are chosen to have low V ce  (sat) such that in conjunction with the Shottky diodes D6, D7 the positive voltage at the base of Q1 and Q2 during their respective unsynchronized &#34;ON&#34; times will be less than .7 volts. Thus, assuming the flip-flop output Q is high, the driver transistor Q3 is saturated and the switching transistor Q1 will remain off until the flip-flop 13 changes state. Similarly the Q2 &#34;ON&#34; time will be determined by the Q4 &#34;ON&#34; time. 
     In operation, upon completion of one full cycle of free-running, unsynchronized oscillation within the transformer T1, the bias voltage supplied by the logic supply 33 reaches its nominal output, enabling the driver flip-flop 15, the modulo-N divider 13 and the system clock 11. After a sufficient number of clock pulses have been passed through the divider 13 to change the state of the flip-flop 15, operation of the converter driver transistors Q3, Q4 occurs. As the flip-flop outputs Q and Q are alternately driven high, the respective driver transistors Q3 and Q4 are alternately driven into saturation. The switching of the switching transistor Q1, Q2 is then controlled by the driver transistors Q2, Q4, and synchronization of the converter has been achieved. The number of clock pulses necessary to obtain initial synchronization is determined by the N of the modulo divider 13 and the flip-flop 15. Once synchronized, the converter switching transitions will occur precisely at the clock or bit rate transitions within the digital system. 
     A major design consideration in the preferred embodiment of the invention is the free-running frequency of the D.C. to D.C. converter, which is determined primarily by the output transformer T1. In the preferred embodiment, the free-running frequency of the converter must be lower than the frequency at which the converter is to be synchronized. This must be true under all worst case conditions of the input line, secondary load and operating temperature range. A toroidal core having a square loop characteristic is preferred for the transformer T1. The design of transformers to meet the requirements of the preferred embodiment of the invention is well-known in the art. 
     While a particularly advantageous embodiment of the subject invention has been set forth, it is apparent that numerous modifications might be made in the method and apparatus as disclosed without departing from the scope and spirit of the invention. It is therefore to be understood that, within the scope of the appended claims, the invention may be practiced other than as specfically described.