Abstract:
A floating gate memory cell comprises a substrate with a drain and a source separated by a channel, a floating gate separated from the channel by a first insulation layer, and a control gate separated from the floating gate by a second insulation layer. The deposition environment is chosen so that the grain size of at least a portion of the floating gate opposite the first insulation layer is about 50-500 Å.

Description:
RELATED APPLICATIONS  
       [0001]     This application is a division of co-pending application Ser. No. 10/180,168 filed 26 Jun. 2002. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     One type of integrated circuit (IC) memory is called eraseable programmable read-only memory (EPROM). This type of memory permits the user to program the memory and, if desired, erase and reprogram memory. One type of EPROM is an N-channel metal oxide semiconductor field effect transistor (MOSFET), one example of which is shown in  FIGS. 1 and 2 , comprising a floating gate transistor  10  with two gates  12 ,  14  made of polysilicon. Polysilicon is commonly deposited by the thermal decomposition (pyrolysis) of silane (SiH4) or disilane (Si2H6) at about 520-700° C. using low-pressure chemical vapor deposition (LPCVD) techniques. The deposition at lower temperatures, such as 520° C., results in the deposited polysilicon being amorphous; the amorphous polysilicon can be recrystallized by subsequent annealing procedures, such as at about 900-1000° C. Gate  12  is a select or control gate while gate  14  is a floating gate. Transistor  10  comprises a substrate  16  including a source  18  and a drain  20  separated from one another by a channel  22 . Floating gate  14  is separated from channel  22  by a first insulation layer  24 , also called the gate oxide  24 , while control gate  12  is separated from floating gate  14  by a second insulation layer  26 .  
         [0003]      FIG. 1  illustrates a conventional method for programming transistor  10 . The arrow in  FIG. 1  illustrates channel hot electron injection into floating gate  14  from channel  22  adjacent to drain  20  and through first insulation layer  24  causing a negative charge to be trapped within floating gate  14 . The existence of the negative charge within floating gate  14  causes the threshold voltage of the programming transistor to the higher than prior to programming. The programmed transistor retains its programmed state even when the power supply is turned off; it has been estimated that the programmed device will retain its programmed state for as long as 100 years.  FIG. 2  illustrates the erasing of transistor  10 . The arrow in  FIG. 2  suggests Fowler-Nordheim (FN) electron tunneling current through first insulation layer  24  and into source  18  (or along channel  22 ). Transistor  10  is read by applying a voltage between high and low threshold values to control gate  12 . If transistor  10  is programmed, that is storing a 0, it will not conduct; if transistor  10  is not programmed, that is storing a 1, it will freely conduct.  
       SUMMARY OF THE INVENTION  
       [0004]     The present invention is based on the recognition that the frequency of erratic erase may be decreased when the grain size of the polysilicon material constituting the floating gate is reduced.  
         [0005]     A first aspect of the invention is directed to a floating gate memory cell of the type comprising a substrate with a drain and a source separated by a channel, a floating gate separated from the channel by a first insulation layer, and a control gate separated from the floating gate by a second insulation layer. The floating gate is a microcrystalline polysilicon material having a grain size of between about 50-500 Å. The grain size may also be between about 50-300 Å or 200-500 Å.  
         [0006]     A second aspect of the invention is directed to a method for forming a polysilicon floating gate during the manufacture of a floating gate memory cell using a deposition process. The improved method comprises selecting a reaction gas and, optionally, a second gas for forming the floating gate during the deposition process, consisting essentially of a reaction gas SiX or Si2Y or an appropriate combination thereof, and, optionally, a second gas Z, where at least one of X, Y and Z comprises deuterium (D); and forming a microcrystalline polysilicon floating gate using said selected reaction gas/second gas. X may comprise at least one of: H4, H2Cl2, HCl3, D4, D2Cl2, D3Cl. Y may comprise at least one of: H6, H4Cl2, H2Cl4, D6, D4Cl2, D2Cl4. Z is used primarily to reduce grain size and may comprise at least one of: D2, H2, D3. The floating gate may be deposited with a desired microcrystalline polysilicon grain structure. The floating gate may be deposited in an amorphous state and then treated to exhibit a desired microcrystalline polysilicon grain structure.  
         [0007]     A third aspect of the invention is directed to a method for forming a polysilicon floating gate during the manufacture of a floating gate memory cell using a deposition process. The method comprises selecting a reaction gas and, optionally, a second gas for forming the floating gate during the deposition process consisting essentially of a reaction gas SiX and, optionally, a second gas Y. The selecting step is carried out with X comprising at least one of: H4, H2Cl2, HCl3, D4, D2Cl2, D3Cl and Y comprising at least one of: D2, H2, D3. The method further comprises forming a microcrystalline polysilicon floating gate using said selected reaction gas/second gas. The forming step may comprise depositing the amorphous silicon material for the floating gate and then treating the floating gate material to exhibit a desired microcrystalline polysilicon grain structure, such as about 200-500 Å.  
         [0008]     A fourth aspect of the invention is directed to a method for forming a polysilicon floating gate during the manufacture of a floating gate memory cell using a deposition process. The method comprises selecting a reaction gas and, optionally, a second gas for forming the floating gate during the deposition process consisting essentially of a reaction gas Si2X and, optionally, a second gas Y. The selecting step is carried out with X comprising at least one of: H6, H4Cl2, H2Cl4, D6, D4Cl2, D2Cl4 and Y comprising at least one of: D2, H2, D3. The method further comprises forming a microcrystalline polysilicon floating gate using said selected reaction gas/second gas. The forming step may comprise depositing the amorphous silicon material for the floating gate and then treating the floating gate material to exhibit a desired microcrystalline polysilicon grain structure, such as about 200-500 Å.  
         [0009]     A fifth aspect of the invention is directed to a method for forming a polysilicon floating gate during the manufacture of a floating gate memory cell using a deposition process, the floating gate memory cell of a type comprising a substrate with a drain and a source separated by a channel, a floating gate separated from the channel by a first insulation layer, and a control gate separated from the floating gate by a second insulation layer. A deposition environment is chosen to include selecting a reaction gas, selecting a reaction gas flow rate, selecting a deposition pressure, and selecting a deposition time. A microcrystalline polysilicon floating gate is formed with the selecting steps chosen so that the grain size of at least a portion of the floating gate opposite the first insulation layer is about 50-500 Å. The entire floating gate may have a grain size of about 50-500 Å. The selecting steps may also be carried out so that the grain size is between about 50-300 Å. The reaction gas selecting step may comprise selecting a reaction gas and, optionally, a second gas consisting essentially of a reaction gas SiX or Si2Y or an appropriate combination thereof, and, optionally, a second gas Z, where at least one of X, Y and Z comprises deuterium (D). The reaction gas-selecting step may be carried out with X comprising at least one of: H4, H2Cl2, HCl3, D4, D2Cl2, D3Cl. The reaction gas-selecting step may also be carried out with Y comprising at least one of: H6, H4Cl2, H2Cl4, D6, D4Cl2, D2Cl4. The reaction gas-selecting step may be carried out with Z comprising at least one of: D2, H2, D3.  
         [0010]     Other features and advantages of the present invention will appear from the following description in which preferred embodiments are disclosed in detail in conjunction with the accompanying drawings.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]      FIG. 1  illustrates a prior art floating gate transistor in a programming mode;  
         [0012]      FIG. 2  illustrates the floating gate transistor of  FIG. 1  in an erase mode;  
         [0013]      FIG. 3  is an enlarged, simplified view of a portion of the transistor of  FIG. 1 ; and  
         [0014]      FIG. 4  is a view, similar to that of  FIG. 3 , of a portion of a floating gate transistor made according to the invention illustrating the smaller grains of the floating gate. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0015]     One of the most common failure modes of an individual floating gate transistor within an integrated circuit memory is called erratic erase. Erratic floating gate transistors show an unstable and unpredictable behavior in erasing. Erratic erase can cause an over erase condition. An over erase condition can cause a memory cell to be stuck as a 1 so that it cannot be programmed. The present invention is based on the concept that making at least the portion of the floating gate opposite the first insulation layer to be a microcrystalline polysilicon material with a controlled, small grain size will help eliminate erratic erase and lead to uniform erase speed.  
         [0016]      FIG. 3  is an enlarged, simplified view of a portion of transistor  10  of  FIG. 1  illustrating the relatively large grains  28  of the polysilicon material constituting that portion of floating gate  14  adjacent to first insulation layer  24 . Conventional deposition processes create grains  28  having a grain size range from about 600-3000 Å. Also illustrated is what is termed an oxide valley  30  in first insulation layer  24  at the intersection of adjacent grains  28 .  
         [0017]      FIG. 4  is a view, similar view to that of  FIG. 3 , of a portion of a floating gate transistor made according to the invention. A floating gate transistor made according to the invention is typically substantially identical to the conventional floating gate transistor  10  of  FIGS. 1-3 , except that floating gate  14 A comprises much smaller grains  28 A and smaller oxide valleys  30 A than floating gate  14 . A high density of phosphorous oxide region is designed as “oxide valley”. Floating gate  14 A is a microcrystalline polysilicon material having a grain size of between about 50-500 Å, and preferably between about 50-300 Å. It is believed that having much smaller grains  28 A leads to smaller valleys  30 A. The smaller grain size helps to decrease the erratic erase problems and leads to a more uniform erase speed. The barrier height or electron trapping will be reduced at the poly-Si/SiO2 interface due to the smaller oxide valley. The provision of smaller grains  28 A, which as illustrated are somewhat randomly sized, can also help make transistor  10  resistant to trap generation by hot electron impingement.  
         [0018]     The invention is typically carried out using an LPCVD deposition process. One such LPCVD process, known as the furnace process, is carried out at a temperature of about 500-700° C. and a pressure of about 0.1 mtorr-5 torr. Another LPCVD process, known as the single wafer process, is carried out at a temperature of about 580-800° C. and a pressure of about 10-500 torr. The floating gate may be deposited with a desired microcrystalline polysilicon grain structure. However, when the deposition takes place at temperatures below about 580° C., the deposited floating gate material may be amorphous and will need to be treated, typically annealed, to achieve the desired microcrystalline polysilicon grain structure. When the floating gate is deposited in an amorphous state and then treated to exhibit a desired microcrystalline polysilicon grain structure, the resulting grain size is typically about 200-500 Å. The invention may be carried out using deposition processes other than LPCVD, such as PECVD (plasma enhance CVD), to achieve the desired grain structure.  
         [0019]     Most of the steps in the formation of floating gate transistor  10  as part of an integrated circuit memory device are generally conventional. However, the polysilicon floating gate  14 A is formed by first selecting a reaction gas and, optionally, a second gas for forming the floating gate during the deposition process. The gas consists essentially of a reaction gas SiX or Si2Y or an appropriate combination thereof, and, optionally, a second gas Z. At least one of X, Y and Z may comprise deuterium (D). X comprises at least one of: H4, H2Cl2, HCl3, D4, D2Cl2, D3Cl. Y comprises at least one of: H6, H4Cl2, H2Cl4, D6, D4Cl2, D2Cl4. Z comprises at least one of: D2, H2, D3.  
         [0020]     In comparing the use of SiH4, SiH4/H2, SiH4/D2, SiD4/H2, and SiD4/D2, the following has been found. (The test conditions included temperature: 640˜770 C., pressure: 200˜400 torr, and SiH4 at 10˜1000 sccm). SiH4 (1) does not create a floating gate  14 A having a desired microcrystalline polysilicon grain structure, and (2) does not create a floating gate  14 A resistant to trap generation by hot electron impingement. SiH4/H2 (1) does create a floating gate  14 A having a desired microcrystalline polysilicon grain structure, and (2) does not create a floating gate  14 A resistant to trap generation by hot electron impingement. SiH4/D2 (1) does create a floating gate  14 A having a desired microcrystalline polysilicon grain structure, and (2) does create a floating gate  14 A resistant to trap generation by hot electron impingement. SiD4/H2 (1) does create a floating gate  14 A having a desired microcrystalline polysilicon grain structure, and (2) does create a floating gate  14 A resistant to trap generation by hot electron impingement. SiD4/D2 (1) does create a floating gate  14 A having a desired microcrystalline polysilicon grain structure, and (2) does create a floating gate  14 A resistant to trap generation by hot electron impingement. Of these compositions, SiD4/D2 appears to be the best.  
         [0021]     The effect of H2 flow on grain size appears to be that grain size decreases as H2 flow increases. For example, testing was done at 720 C., 275 torr, 24 sec deposition to 1000A thickness in a single-wafer POLYgen chamber using SiH4/H2. A flow rate ratio for SiH4/H2 of 100 sccm/0 sccm resulted in a grain size of about 600-800 Å. A flow rate ratio for SiH4/H2 of 100 sccm/1000 sccm resulted in a grain size of about 200-400 Å. A flow rate ratio for SiH4/H2 of 100 sccm/2000 sccm resulted in a grain size of about 50-200 Å. In another example, testing was done in a single-wafer POLYgen chamber at 640 C., 275 torr using SiH4/H2 for 38 sec deposition to 1000A thickness, and then RTP at 950 C. 30 sec in N2 ambient. A flow rate ratio for SiH4/H2 of 200 sccm/0 sccm resulted in a grain size of about 800˜1000 Å. A flow rate ratio for SiH4/H2 of 200 sccm/1000 sccm resulted in a grain size of about 400˜600 Å. A flow rate ratio for SiH4/H2 of 200 sccm/2000 sccm resulted in a grain size of about 200˜300 Å.  
         [0022]     Modification and variation can be made to be disclosed embodiments without the departing from the subject of the invention as defined in the following claims.  
         [0023]     Any and all patents, patent applications and printed publications referred to above are incorporated by reference.