Abstract:
A pipe register for use in a semiconductor memory device, wherein said semiconductor memory device includes global input/output (I/O) lines, complementary global I/O lines, and pipe registers, coupled to said global I/O lines and said complementary global I/O lines, for detecting the data loaded on said global I/O lines and complementary global I/O lines to store the data, includes: a data detecting unit, coupled to said global I/O lines and complementary global I/O lines, for detecting whether the data is loaded on said global I/O lines and complementary global I/O lines; a control signal generating unit for sensing edges of the data loaded on the global I/O line and the complementary global I/O line to generate a rising edge sensing signal and a falling edge sensing signal; and a plurality of storage units for storing the data loaded on said global I/O lines and said complementary global I/O lines in response to a reset signal, the falling edge sensing signal and the rising edge sensing signal and for outputting the data in response to the pipe counter signal outputted from said pipe counting unit.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a semiconductor memory device; and, more particularly, to a synchronous semiconductor memory device having a pipe register, which stores and outputs data at a high speed by using a pipeline scheme. 
     DESCRIPTION OF THE PRIOR ARTS 
     In a read operation, a synchronous memory device temporarily stores data to a temporary storage unit and then outputs the data through a data output pin in synchronization with an external clock. That temporary storage unit is called a pipe register. 
     FIGS.  1  and  1 A- 1 D are schematic diagrams showing a synchronous memory device having a conventional pipe register. 
     Referring to FIGS.  1  and  1 A- 1 D the synchronous memory device includes a plurality of pipe registers, each of which is coupled to four pairs of global I/O lines and complementary global I/O lines. By combining signals of the four pairs, a common prefetch signal PFETCH[ 0 : 2 ] is generated. The pipe registers, coupled to eight global I/O lines and complementary global I/O lines are commonly controlled by the common prefetch signal PFETCH[ 0 : 2 ]. 
     As shown in FIG. 1A, a prefetch signal generator  100  is coupled to four pairs of global I/O lines and complementary global I/O lines GIO&lt; 4 &gt;, GIOZ&lt; 4 &gt;, GIO&lt; 5 &gt;, GIOZ&lt; 5 &gt;, GIO&lt; 6 &gt;, GIOZ&lt; 6 &gt;, GIO&lt; 7 &gt;, GIOZ&lt; 7 &gt;. 
     A prefetch signal generator  110  is coupled to four pairs of global I/O lines and complementary global I/O lines GIO&lt; 12 &gt;, GIOZ&lt; 12 &gt;, GIO&lt; 13 &gt;, GIOZ&lt; 13 &gt;, GIO&lt; 14 &gt;, GIOZ&lt; 14 &gt;, GIO&lt; 15 &gt;, GIOZ&lt; 15 &gt;. Pipe registers  120  to  127  are respectively coupled to the global I/O lines and the complementary global I/O lines GIO&lt; 0 &gt;and GIOZ&lt; 0 &gt;, GIO&lt; 1 &gt;and GIOZ&lt; 1 &gt;, GIO&lt; 2 &gt;and GIOZ&lt; 2 &gt;, GIO&lt; 3 &gt;and GIOZ&lt; 3 &gt;, GIO&lt; 4 &gt;and GIOZ&lt; 4 &gt;, GIO&lt; 5 &gt;and GIOZ&lt; 5 &gt;, GIO&lt; 6 &gt;and GIOZ&lt; 6 &gt;, GIO&lt; 7 &gt;and GIOZ&lt; 7 ]&gt;, and receives the common prefetch signal PFETCH[ 0 : 2 ] from the prefetch signal generator  100 . 
     Pipe registers  128  to  135  are respectively coupled to four pairs of global I/O lines and complementary global I/O lines GIO&lt; 8 &gt;and GIOZ&lt; 8 &gt;, GIO&lt; 9 &gt;, GIOZ&lt; 9 &gt;, GIO&lt; 10 &gt;, GIOZ&lt; 10 &gt;, GIO&lt; 11 &gt;, GIOZ&lt; 11 &gt;, GIO&lt; 12 &gt;, GIOZ&lt; 12 &gt;, GIO&lt; 13 &gt;, GIOZ&lt; 13 &gt;, GIO&lt; 14 &gt;, GIOZ&lt; 14 &gt;, GIO&lt; 15 &gt;, GIOZ&lt; 15 &gt;, and receives the common prefetch signal PFETCH[ 0 : 2 ] from the prefetch signal generator  110 . 
     Data output buffers  136  to  151  are coupled to output terminals of the pipe register  120  to  135 , respectively. 
     A pipe counter  160  generates a pipe counter signal POCNT to the pipe registers  128  to  135 . At this time, the data output is controlled by the pipe counter signal POCNT. 
     In such a synchronous memory device, the data on each of the global I/O lines and the complementary global I/O lines have different skews due to loads thereof. Therefore, a pulse width of the common prefetch signal PFETCH[ 0 : 2 ] should be widened as much as the skew between the global I/O line and the complementary global I/O line. 
     As a result, it is difficult for the conventional synchronous memory device to latch the data into the pipe registers in a high speed in case where the prefetch signal PFETCH[ 0 : 2 ] has a wide pulse width. 
     FIG. 2 is a circuit diagram showing a conventional pipe register. The conventional pipe register includes three storage units  200 ,  210  and  220 . 
     As shown in FIG. 2, since the conventional pipe register clears data stored in storage unit  200  in response to a clear signal CL 1 , a cycle time is increased so that it is difficult to obtain a high speed of operation in the synchronous memory device. 
     SUMMARY OF THE INVENTION 
     It is, therefore, an object of the present invention to provide a synchronous memory device having a pipe register, which stores and outputs data at a high speed by using a pipeline scheme. 
     In accordance with an aspect of the present invention, there is provided a pipe register for use in a semiconductor memory device, wherein said semiconductor memory device includes global input/output (I/O) lines, complementary global I/O lines, and pipe registers, coupled to said global I/O lines and said complementary global I/O lines, for detecting the data loaded on said global I/O lines and complementary global I/O lines to store the data, said pipe register comprising: a data detecting means, coupled to said global I/O lines and complementary global I/O lines, for detecting whether the data is loaded on said global I/O lines and complementary global I/O lines; a control signal generating means for sensing edges of the data loaded on the global I/O line and the complementary global I/O line to generate a rising edge sensing signal and a falling edge sensing signal; and a plurality of storage means for storing the data loaded on said global I/O lines and said complementary global I/O lines in response to a reset signal, the falling edge sensing signal and the rising edge sensing signal and for outputting the data in response to the pipe counter signal outputted from said pipe counting means. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects and aspects of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, in which: 
     FIGS.  1  and  1 A- 1 D are schematic diagrams illustrating a synchronous memory device having a conventional pipe register; 
     FIG. 2 is a circuit diagram illustrating a conventional pipe register; 
     FIGS.  3  and  3 A- 3 D are block diagrams illustrating a synchronous memory device having a pipe register in accordance with an embodiment of the present invention; 
     FIGS.  4  and  4 A- 4 D are circuit diagrams illustrating a pipe register shown in FIG. 3; and 
     FIGS. 5A and 5B are timing charts of signals in a pipe-register shown in FIG.  4 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIGS.  3  and  3 A- 3 D are block diagrams of a synchronous memory device having a pipe register in accordance with the present invention. 
     As shown in FIGS.  3  and  3 A- 3 D, the synchronous memory device according to the present invention includes pipe registers which are directly coupled to a global I/O line and a complementary global I/O line without using an additional prefetch signal generator. 
     That is, the pipe register  300  is directly coupled to a global I/O line GIO&lt; 0 &gt;and a complementary global I/O line GIOZ&lt; 0 &gt;and the pipe register  301  is directly coupled to a global I/O line GIO&lt; 1 &gt;and the complementary global I/O line GIOZ&lt; 1 &gt;. In the same manner, the other pipe registers  302  to  315  are coupled to corresponding global I/O lines and complementary global I/O lines, respectively. 
     FIGS.  4  and  4 A- 4 D are circuit diagrams illustrating a pipe register shown in FIG.  3 . FIGS. 5A and 5B are timing charts of a pipe register in accordance with the present invention. 
     As shown, the pipe register according to the present invention includes four storage units  400 ,  410 ,  420  and  430  which are capable of supporting a column address strobe (CAS) latency maximally up to four clocks. The four storage units  400 ,  410 ,  420  and  430  are coupled to the global I/O lines GIO and the complementary global I/O lines GIOZ, so that a read data is transferred to the pipe register. At this time, the global I/O lines GIO and the complementary global I/O lines GIOZ are maintained at a precharged state of a high level, and data is loaded to the global I/O lines GIO and the complementary global I/O lines GIOZ in a state of a low level. 
     In addition, the pipe register in accordance with the present invention includes a data detector  440 , coupled to the global I/O lines GIO and the complementary global I/O lines GIOZ. The data detector  440  detects whether or not the data is loaded on the global I/O lines GIO and the complementary global I/O liens GIOZ. 
     The data detector  440  includes a NAND gate  441 , a delay unit  442 , a NOR gate  443 , and a NAND gate  444 . 
     The NAND gate  441  has an input terminal coupled to the global I/O lines GIO and the complementary global I/O lines GIOZ. The NAND gate  441  detects whether or not data is loaded on the global I/O lines GIO and the complementary global I/O lines GIOZ. 
     The delay unit  442  is coupled to an output terminal of the NAND gate  441 . The delay unit  412  inverts and delays an output signal of a NAND gate  441  for a predetermined time. 
     The NOR gate  443  detects falling edges of the data loaded on the global I/O lines GIO and the complementary global I/O lines GIOZ in response to an output signal from the NAND gate  441  and an output signal from the delay unit  442 , to generate a detection falling edge (DFE) signal as a low active signal. 
     The NAND gate  444  detects rising edges of the data loaded on the global I/O lines GIO and the complementary global I/O lines GIOZ in response to the output signal of the NAND gate  441  and the delay unit  442 , to generate a detection rising edge (DFE) signal. 
     The DRE and DFE signals outputted from the data detector  440  are transferred to the four storage units  400  to  430 . 
     At this time, when a reset signal RESET is inputted to the four storage units  400  to  430  at an initial read operation, all the data stored in the storage units  400  to  430  are deleted and the selection signal SEL[ 0 ] of the first storage unit  400  is enabled to a low level. 
     A pipe counter signal PCONT[ 3 : 0 ]) is a signal for sequentially outputting the data stored in the storage units  400  to  430  to a data output buffer in synchronous with the clock cycle of a predetermined CAS latency. 
     Hereinafter, a structure of the storage units  400  to  430  will be described in detail. 
     The first storage unit  400  includes a first latch circuit  40  that is constituted with two inverters, a second latch circuit  41  for storing data into a storage node PZ[ 0 ]. A selection signal disabling unit detects data stored in the first latch circuit  40  and the second latch circuit  41  to generate a selection signal SEL[ 0 ] for disabling selection transistors  408  and  409 . 
     A selection signal enabling unit outputs a selection signal SEL[ 0 ] for enabling the selection transistors  408  and  409  in response to a DRE signal, a control signal CL[ 0 ] and data stored in a previous storage unit  430 . 
     PMOS transistors  45  and  46  are coupled between a power terminal and the selection transistors  408  and  409 . Each gate of the PMOS transistors  45  and  46  is coupled to the global I/O line GIO and the complementary global I/O line GIOZ. 
     An initial reset unit clears data stored in the first latch circuit  40  and the second latch circuit  41  in response to a reset signal RESET at an initial operation mode and enables a selection signal SEL[ 0 ], so that the first latch circuit  40  and the second latch circuit  41  receives data loaded on the global I/O lines GIO and the complementary global I/O lines GIOZ. 
     A clear unit clears data loaded on the storage node P[ 0 ] and PZ[ 0 ] of the first latch circuit  40  and the second latch circuit  41  in response to the DFE signal and a selection signal SEL[ 3 ] of the storage unit  430 . 
     An output driving unit  50 A and  50 B drives output signals PU and PD in response to the data stored in the first and the second latch circuits  40  and  41  and the pipe counter signal POCNT[ 0 ]. 
     The selection transistors  408  and  409  are coupled between the PMOS transistors  45  and  46  and the storage units P[ 0 ] and PZ[ 0 ], respectively, and each gate receives the selection signal SEL[ 0 ]. 
     The selection signal disabling unit includes a NAND gate  404  having an input terminal coupled to the first and the second latch circuit  40  and  41 , an odd number of inverters  405  to  407  for inverting an output signal of the NAND gate  404  to output the control signal CL[ 0 ], a PMOS transistor PM 1  for pulling up the selection signal SEL[ 0 ] in response to the control signal CL[ 0 ], whose one terminal is coupled to the power terminal and gate receives the control signal CL[ 0 ]. 
     The selection enabling unit includes a NAND gate  43  for NANDing the control signal CL[ 0 ], the DRE signal and an output signal DP[ 3 ] of the fourth storage unit  430 , an inverter  44  for inverting an output signal of the NAND gate  43 , and an NMOS transistor NM 1  for pulling up the selection signal SEL[ 0 ] in response to an output signal OP[ 0 ] of the inverter  44 . The NMOS transistor NM 1  is coupled between a drain of the PMOS transistor PM 1  and a ground terminal, whose gate receives an output signal OP[ 0 ] of the inverter  44 . 
     In the initial reset unit, an NMOS transistor  401  whose gate receives the reset signal RESET is coupled between the storage node P[ 0 ] and the ground terminal. An NMOS transistor  402  whose gate receives the reset signal RESET is coupled between the storage node PZ[ 0 ] and the ground terminal. An NMOS transistor  403  whose gate receives the reset signal RESET is coupled between a node of the selection signal SEL[ 0 ] and the ground terminal. 
     In the clear unit, the DFE signal and the selection signal SEL[ 3 ] are NORed by a NOR gate  47 . An NMOS transistor  48  whose gate receives an output signal of the NOR gate  47  is coupled between the storage node P[ 0 ] and the ground terminal. An NMOS transistor  49  whose gate receives an output signal of the NOR gate  47  is coupled to the storage node PZ[ 0 ] and the ground terminal. 
     The output driving unit includes a first driving unit  50 A for driving the output signal PU of the pipe register and a second driving unit  50 B for driving the output signal PD of the pipe register. 
     The first driving unit  50 A includes a PMOS transistor whose gate receiving an inverted signal of the storage node P[ 0 ], a PMOS transistor whose gate receives the inverted pipe counter signal POCNT[D], an NMOS transistor whose gate receives the pipe counter signal POCNT[ 0 ], and an NMOS transistor whose gate receives a signal of the storage node PZ[ 0 ]. At this time, the PMOS transistors and the NMOS transistors are serially coupled between the power terminal and the ground terminal. 
     The second driving unit  50 B includes a PMOS transistor whose gate receives the inverted signal of the storage node PZ[ 0 ], a PMOS transistor whose gate receives the inverted pipe counter signal POCNT[ 0 ], an NMOS transistor whose gate receives the pipe counter signal POCNT[ 0 ], and an NMOS transistor whose gate receives a signal of the storage node P[ 0 ] . The PMOS transistors and the NMOS transistors are serially coupled between the power terminal and the ground terminal. 
     The storage units  410  to  430  have the same structure and operation as the first storage unit  400 , except the NMOS transistor  403  contained in the initial reset unit. 
     The operation of the present invention will be described below in detail with reference to FIGS. 4,  5 A and  5 B. 
     First, it is assumed that the global I/O lines GIO and the complementary global I/O lines GIOZ are precharged in a state of a high level and the selection signal SEL[ 0 ], SEL[ 1 ], SEL[ 2 ] and SEL[ 3 ]) of the first to fourth storage units  400  to  430  are maintained in a state of a high level. 
     If the read operation is initiated ( 500 , in FIG.  5 A), the reset signal RESET of a high level is applied to the pipe register. The NMOS transistors  401 ,  411 ,  421  and  431  are turned on in response to the reset signal RESET, so that the storage nodes P[ 0 ], P[ 1 ], P[ 2 ] and P[ 3 ] of the first to fourth storage units  400  to  430  are reset to a low level. In similar manner, the NMOS transistors  402 ,  412 ,  422  and  432  are turned on in response to the reset signal RESET of a high level, so that the storage nodes PZ[ 0 ], PZ[ 1 ], PZ[ 2 ] and PZ[ 3 ] of the first to fourth storage units  400  to  430  are reset to a low level ( 500 , in FIG.  5 A). 
     Next, the NMOS transistor  403  contained in the first storage unit  400  is turned on in response to the reset signal RESET of a high level and the selection signal SEL[ 0 ] of the first storage unit  400  is changed to a low level due to the turned-on NMOS transistor  403 , so that the first storage unit  400  is enabled ( 501 , in FIG.  5 A). 
     Next, in case where the data read out from a memory cell is loaded to the global I/O line GIO and the complementary global I/O line GIOZ, a level of the global I/O line GIO is changed to a low level and a level of the complementary global I/O line GIOZ is maintained at a high level. Then, the PMOS transistor  45  is turned on, so that a high level is latched in the storage node P[ 0 ] of the first storage unit  400  enabled in response to the selection signal SEL[ 0 ] and the storage node PZ[ 0 ] is maintained at a low level ( 502 , in FIG. 5A) Simultaneously, the data detector  440  senses the data loaded on the global I/O line GIO and the complementary global I/O line GIOZ to generate the DFE signal of a low level ( 503 , in FIG.  503 ). 
     Next, the NOR gate  413  receives the DFE signal of a low level and the selection signal SEL[ 0 ] of a low level to generate a signal RS[ 1 ] of a high level ( 504 , in FIG.  5 ), and the NMOS transistor  414  and  415  is turned on in response to the signal RS[ 1 ] of a high level therefore, the storage nodes P[ 0 ] and PZ[ 1 ] of the second storage unit  410  is cleared to a state of a low level. That is, the NOR gate  413  clears the data stored in the second storage unit  410  in response to the DFE signal and the selection signal SEL[ 0 ]. 
     Next, the NAND gate  404  receives the high level signal of the storage node P[ 0 ] and the low level signal of the storage node PZ[ 0 ], to generate the signal DP[ 0 ] of a high level ( 505 , in FIG. 5B) and the control signal CL[ 0 ] of a low level. Then, the PMOS transistor PM 1  is turned on in response to the control signal CL[ 0 ] of a low level, and the selection signal SEL[ 0 ] of the first storage unit  400  is changed to a high level ( 506 , in FIG.  5 A), so that the PMOS transistors  408  and  409  are turned off. That is, the NAND gate  40  and three inverters  405  to  407  detects a completion of the storing operation with respect to the first storage unit  400  and disables the first storage unit  400 . Therefore, the storage node P[ 0 ] and the storage node PZ[ 0 ] are maintained at a high level and a low level, respectively, until they are cleared. 
     Next, when a level of the global I/O line GIO is changed to a high level, the data detector  404  senses the level transition of the global I/O line GIO to generate the DRE signal of a high level ( 507 , in FIG.  5 A). 
     The DRE signal of a high level, the signals DP[ 0 ] of a high level and the control signal CL[ 1 ] of a high level are NANDed through the NAND gate  416  and an output signal of the NAND gate  416  is inverted through an inverter  417 . As a result, a signal OP[ 0 ] of a high level is outputted through the inverter  417 . 
     The NMOS transistor NM 42  is turned on in response to the signal OP[ 0 ] of a high level, so that the selection signal SEL[ 1 ] of the second storage unit  410  is driven to a low level ( 508 , in FIG.  5 A). Accordingly, the PMOS transistors  418  and  419  are turned on, and therefore, it is ready to store a second data into the global I/O line GIO and the complementary global I/O line GIOZ. 
     Next, when the second data is loaded into the global I/O line GIO and the complementary global I/O line GIOZ, that is, the global I/O line GIO is maintained at a high level and the complementary global I/O line GIOZ is changed to a low level, the PMOS transistor  51  is turned on. Then, a high level is latched to the storage node PZ[ 1 ] of the second storage unit  410  enabled in response to the selection signal SEL[ 1 ] ( 509 , in FIG. 5A) and the data detector  440  simultaneously generates the DFE signal of a low level ( 510 , in FIG.  5 A). 
     The NOR gate  423  receives the DFE signal of a low level and the selection signal SEL[ 1 ] of a low level to generate a signal RS[ 2 ] of a high level ( 511 , in FIG.  5 ), and the NMOS transistor  424  and  425  is turned on in response to the signal RS[ 2 ] of a high level. Therefore, the storage nodes P[ 2 ] and PZ[ 2 ] of the third storage unit  420  is cleared to a state of a low level. That is, the NOR gate  423  clears the data stored in the third storage unit  420  in response to the DFE signal and the selection signal SEL[ 1 ]. 
     Next, the NAND gate  414  receives the high level signal of the storage node PZ[ 1 ] and the low level signal of the storage node P[ 1 ], to generate the signal DP[ 1 ] of a high level ( 515 , in FIG. 5B) and the control signal CL[ 1 ] of a low level. Then, the PMOS transistor PM 2  is turned on in response to the control signal CL[ 1 ] of a low level, and the selection signal SEL[ 1 ] of the second storage unit  410  is changed to a high level ( 5136 , in FIG.  5 A), so that the PMOS transistors  418  and  419  are turned off. That is, the NAND gate  41  and three inverters  42 ,  43  and  44  detects a completion of the storing operation with respect to the second storage unit  410  and disables the second storage unit  410 . Therefore, the storage node PZ[ 1 ] and the storage node P[ 1 ] are maintained at a high level and a low level, respectively, until they are cleared. 
     Next, when a level of the complementary global I/O line GIOZ is changed to a high level, the data detector  404  senses the level transition of the complementary global I/O line GIOZ to generate the DRE signal of a high level ( 501 , in FIG.  5 A). 
     The DRE signal of a high level, the signal DP[ 1 ] of a high level and the control signal CL[ 2 ] of a high level are NANDed through the NAND gate  52  and an output signal of the NAND gate  52  is inverted through an inverter  53 . As a result, a signal OP[ 2 ] of a high level is outputted through the inverter  53 . 
     The NMOS transistor  54  is turned on in response to the signal OP[ 2 ] of a high level, so that the selection signal SEL[ 2 ] of the third storage unit  420  is driven to a low level ( 515 , in FIG.  5 A). Accordingly, the PMOS transistors  55  and  53  are turned on, and therefore, it is ready to store a third data into the global I/O line GIO and the complementary global I/O line GIOZ. 
     In the same manner as the first and second data, in case where a third data and a fourth data are continuously loaded on the global I/O lines GIO and the complementary global I/O lines GIOZ, the third and the fourth data are stored into the third and fourth storage units, respectively. 
     In case where the CAS latency is of 3, the pipe counter signal POCNT[ 0 ] is changed to a high level and a stored data is outputted to the data output buffer through the output driving unit  50   a  and  50 B contained in the first storage unit  400 . That is, in response to a high level signal of the storage node P[ 0 ] and a low level signal of the storage node PZ[ 0 ], the output signal PU of a high level and the output signal PD of a low level is transferred to the data output buffer ( 516 , in FIG.  5 B), and then the data loaded on the global I/O line GIO and the complementary global I/O line GIOZ are stored into the third storage unit  420 . 
     Next, at a next clock, the pipe counter signal POCNT[ 0 ] is changed to a low level, so that the output driving unit  50 A and  50 B of the first storage unit  400  is disabled. At the same time, the pipe counter signal POCNT[ 1 ] from the pipe counter is changed to a high level, so that data stored in the second storage unit  410  is transferred to the data output buffer through the output driving unit  51 A and  51 B of the second storage unit  410 . Sequentially, the data loaded on the global I/O line GIO and the complementary global I/O line GIOZ are stored into the fourth storage unit  430 . 
     Next, at a next clock, the pipe counter signal POCNT[l] is changed to a low level, so that the output driving unit  51 A and  51 B of the second storage unit  410  is disabled. At the same time, the pipe counter signal POCNT[ 2 ] from the pipe counter is changed to a high level, so that data stored in the third storage unit  420  is transferred to the data output buffer through the output  52 A and  52 B of the third storage unit  420 . Sequentially, the data loaded on the global I/O line GIO and the complementary global I/O line GIOZ are stored again into the first storage unit  400 . 
     As described above, according to the change of the cycle, the data stored in the storage unit is outputted to the data output buffer in response to the pipe counter signal and the data are alternatively stored into the storage units in response to the CAS latency. 
     Consequently, by constituting the pipe register having four storage units, if the data is loaded on the global I/O line and the complementary global I/O line, the loaded data is sensed and stored into one of the four storage units. Simultaneously, a next storage unit is cleared in response to the CAS latency, so that a next data is stored into the next storage unit. 
     While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.