Abstract:
An apparatus includes a phase locked loop circuit having a phase comparator for generating a signal indicative of a phase difference between a signal presented to a first input of the phase comparator and a signal presented to a second input of the phase comparator. The apparatus includes at least one delay element disposed so as to enable contributing at least one of the following:
       i) delay to a signal provided to the first input of the phase comparator;   ii) delay to a signal provided to the second input of the phase comparator.
 
A delay contributed by the at least one delay element varies in accordance with an associated delay control value. The phase locked loop circuit and the at least one delay element reside on a same semiconductor substrate.

Description:
BACKGROUND 
     Digital logic circuits often rely on clock signals for synchronization, derivation of reference signals, measuring phase differences, and other functions. The circuits may be segregated into different integrated circuits or different subsystems of a larger electronic device. 
     One approach for getting the clock signal to all components requiring a clock is to distribute the clock signal from a centralized clock to every component requiring the clock signal. One disadvantage of this approach is that clock signals tend to have constraints that are difficult to maintain when the distribution is over a relatively large area or used to drive a relatively large number of components. 
     Another technique for distributing a clock signal entails distributing a reference clock signal to different components or even different regions within an integrated circuit. Each component or region has a local phase locked loop (PLL) or local delay locked loop (DLL) buffer to derive one or more local clock signals from the reference clock signal. Such designs are sometimes referred to as a “clock tree”. The use of a tree structure allows clocked buffers to be configured for the specifics of the loads they are driving as well as limiting the load to be driven by any clock signal. 
       FIG. 1  illustrates one embodiment of a prior art PLL circuit  100 . The reference clock  160  is provided to the reference clock input  112  of a phase comparator  110 . The PLL clock output  180  is taken from the output of a variable frequency oscillator (VFO)  130 . A feedback loop  170  couples the PLL clock output to a feedback input  114  of the phase comparator. The phase comparator generates a phase error signal which is filtered by a low pass filter (LPF)  120 . The filtered phase error signal controls the VFO. The frequency and phase of the VFO varies in response to the filtered phase error signal. Driver  140  receives the output of VFO  130 . VFO  130  is driven to cause the PLL clock output to match the phase and frequency of the reference clock. The PLL may be fabricated on a semiconductor substrate  150 . Although only the monitored output  180  is shown, the PLL may drive multiple outputs. 
     A zero phase delay between the PLL clock output and the reference clock is often a design objective. However there are applications in which the designer needs the PLL clock output phase to lead the reference clock. Prior art clock PLL implementations introduce elements into the PLL feedback loop or select the load driven by the monitored output to change the frequency and phase relationship between the reference clock and the derived clock. Changing the amount of phase advance thus requires selecting different components for the PLL feedback loop or adjusting the load of the monitored output in such a prior art architecture. 
     SUMMARY 
     An apparatus includes a phase locked loop circuit having a phase detector for generating a signal indicative of a phase difference between a signal presented to a first input of the phase detector and a signal presented to a second input of the phase detector. At least one delay element is disposed so as to contribute at least one of: 
     i) a delay to a signal provided to the first input of the phase detector; 
     ii) a delay to a signal provided to the second input of the phase detector. 
     The delay contributed by the at least one delay element varies in accordance with an associated delay control value. The phase locked loop circuit and the at least one delay element reside on the same semiconductor substrate. 
     Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which: 
         FIG. 1  illustrates a functional block diagram of a prior art phase locked loop circuit. 
         FIG. 2  illustrates clock signals with varying phase relationships compared to a reference clock signal. 
         FIG. 3  illustrates one embodiment of a phase locked loop circuit with a programmable delay element in the feedback path. 
         FIG. 4  illustrates one embodiment of a phase locked loop circuit with a programmable delay element in the reference clock path. 
         FIG. 5  illustrates one embodiment of a phase locked loop circuit with a programmable delay element in each of the feedback path and the reference path. 
         FIG. 6  illustrates one embodiment of an all-digital phase locked loop circuit with a programmable delay element in each of the feedback path and the reference path. 
         FIG. 7  illustrates one embodiment of a delay element. 
         FIG. 8  illustrates an alternative embodiment of a digital phase lock loop with programmable input/output phase relationship 
         FIG. 9  illustrates one embodiment of a time-to-digital converter and phase offset block corresponding respectively to the time-to-digital converter and phase offset block of  FIG. 8 . 
         FIG. 10  illustrates one embodiment of a method of controlling the input/output phase relationship of a phase-locked loop circuit. 
     
    
    
     DETAILED DESCRIPTION 
     Chart  200  of  FIG. 2  illustrates clock signals (CLK_OUT 1 , CLK_OUT 2 , CLK_OUT 3 ) with varying phase relationships compared to a reference clock signal (REF_CLK). 
     CLK_OUT 1  exhibits a zero phase delay with respect to REF_CLK. CLK_OUT 2  exhibits a non-zero phase delay (lagging) with respect to REF_CLK. CLK_OUT 3  illustrates a phase advance (leading) with respect to REF_CLK. 
       FIG. 3  illustrates one embodiment of a phase locked loop circuit  300  with a programmable delay element  372  in the feedback path. The reference clock  360  is provided to the reference clock input  312  of a phase comparator  310 . The PLL clock output  380  is taken from the output of a variable frequency oscillator (VFO)  330  after it has been divided by divider  340 . 
     A feedback loop  370  couples the PLL clock output to the delay element  372  that is coupled to a feedback input  314  of the phase comparator. The phase comparator generates a phase error signal that is filtered by a low pass filter (LPF)  320 . The filtered phase error signal controls the VFO. The frequency and phase of the VFO vary in response to the filtered phase error signal. The VFO is driven to cause the PLL clock output to match the phase and frequency of the reference clock REF_CLK  360 . The PLL may be fabricated on a semiconductor substrate  350 . Although only the monitored output  380  is shown, the PLL may drive multiple outputs. 
     The delay element  372  contributes a signal delay based upon a delay control value provided by the CTRL_FBK signal  374 . In one embodiment, the delay element  372  is located on the same semiconductor substrate as the other functional blocks of the PLL circuit. CLK_FAST  332  may be utilized as the clock signal for clocking delay element  372  if necessary. In one embodiment delay element  372  includes synchronous logic. 
     The delay contributed by the delay element in the feedback path causes the PLL to advance the phase of the PLL clock output  380  such that it leads the reference clock  360 . The amount of delay is determined by the delay control value provided by CTRL_FBK  374 . 
       FIG. 4  illustrates one embodiment of a phase locked loop circuit  400  with a programmable delay element  462  in the reference clock path. The delay element  462  is coupled to receive the reference clock  460 . The output of the delay element is coupled to the reference clock input  412  of a phase comparator  410 . The PLL clock output  480  is taken from the output of a variable frequency oscillator (VFO)  430 . 
     A feedback loop  470  couples the PLL clock output to the feedback return input  414  of the phase comparator. The phase comparator generates a phase error signal which is filtered by a low pass filter (LPF)  420 . The filtered phase error signal controls the VFO. The frequency and phase of the VFO vary in response to the filtered phase error signal. The VFO is driven to cause the PLL clock output to match the phase and frequency of the reference clock REF_CLK  460 . The PLL circuit may be fabricated on a semiconductor substrate  450 . Although only the monitored output  480  is shown, the PLL circuit may drive multiple outputs. 
     Divide-by-N divider  440  is shown as an optional element. If divider  440  is included, the frequency of CLK_FAST  432  at the output of the VFO will be a multiple of the frequency of the PLL clock output  480 . 
     The delay element  462  contributes a signal delay based upon a delay control value provided by the CTRL_REF signal  464 . CLK_FAST  432  may be utilized as a clock signal for clocking delay element  462  if necessary. In one embodiment delay element  462  includes synchronous logic. In one embodiment, the delay element  462  is located on the same semiconductor substrate as the other functional blocks of the PLL circuit. 
     The delay contributed by the delay element in the reference clock path causes the PLL to delay the phase of the PLL clock output  480  such that it lags the reference clock  460 . The amount of delay is determined by the delay control value provided by CTRL_REF  464 . 
     The embodiments illustrated in  FIGS. 3 and 4  permit only advancing or delaying the PLL clock output phase relative to the reference clock, respectively.  FIG. 5  illustrates one embodiment of a phase locked loop circuit  500  with a programmable delay element in each of the feedback path and the reference path to enable both advancing and delaying the PLL clock output  580  relative to the reference clock  560 . 
     The phase locked loop circuit includes a first programmable delay element  572  in the feedback path and a second programmable delay element  562  in the reference clock path. The PLL clock output  580  is taken from the output of a variable frequency oscillator (VFO  530 ). 
     A feedback loop  570  couples the PLL clock output to the first delay element  572 . The output of the programmable delay element  562  is coupled to the feedback input  514  of the phase comparator  510 . The output of the programmable delay element  562  is coupled to the reference clock input  512  of the phase comparator  510 . The programmable delay element  562  receives the reference clock  560  as an input. 
     The phase comparator  510  generates a phase error signal indicating a phase difference between its feedback input  514  and its reference clock input  512 . The phase error signal is filtered by low pass filter  520 . The filtered phase error signal controls VFO  530 . The frequency and phase of VFO  530  vary in response to the filtered phase error signal. The PLL may be fabricated on a semiconductor substrate  550 . Although only the monitored output  580  is shown, the PLL may drive multiple outputs. 
     Divide-by-N divider  540  is shown as an optional element. If divider  540  is included, the frequency of CLK_FAST signal  532  at the output of the VFO will be a multiple of the frequency of the PLL clock output  580 . 
     The delay element  572  contributes a signal delay based upon a delay control value provided by the CTRL_FBK signal  574 . In one embodiment, the delay element  572  is located on the same semiconductor substrate as the other functional blocks of the PLL circuit. The delay contributed by the delay element in the feedback path causes the PLL to advance the phase of the PLL clock output  580  such that it leads the reference clock  560 . The amount of delay is determined by the delay control value provided by CTRL_FBK signal  574 . 
     The delay element  562  contributes a signal delay based upon a delay control value provided by the CTRL_REF signal  564 . In one embodiment, the delay element  562  is located on the same semiconductor substrate as the other functional blocks of the PLL circuit. The delay contributed by the delay element in the reference clock path causes the PLL to delay the phase of the PLL clock output  580  such that it lags the reference clock  560 . The amount of delay is determined by the delay control value provided by CTRL_REF  564 . 
     Although delay element  562  operates exclusively to delay the PLL clock output and delay element  572  operates exclusively to advance the PLL clock output, in one application the delay elements are each programmed to contribute a non-zero delay in order to permit greater resolution control of the amount of phase lead or phase lag of the PLL clock output  580 . 
     The delay elements may be introduced in either analog, digital, or mixed signal PLL circuitry. CLK_FAST  532  may be utilized as a clock signal for clocking one or both of delay elements  562 ,  572  if necessary. In one embodiment one or both of delay elements  562 ,  572  includes synchronous logic. 
       FIG. 6  illustrates one embodiment of a phase locked loop circuit  600  with digitally implemented function blocks and delay elements. The phase locked loop circuit includes a first programmable delay element  672  in the feedback path and a second programmable delay element  662  in the reference clock path. The PLL clock output  680  is taken from the output of a variable frequency oscillator (VFO  630 ). 
     A feedback loop FBK  670  couples the PLL clock output to programmable delay element  672 . The output of the programmable delay element  672  is coupled to the feedback input  614  of the phase comparator. In this embodiment the phase comparator is implemented as a time-to-digital converter  610 . The output of the programmable delay element  662  is coupled to the reference clock input  612  of the time-to-digital converter  610 . The programmable delay element receives the reference clock  660  as an input. 
     The time-to-digital converter  610  generates a detected phase error value or signal indicating a phase difference between its feedback input  614  and its reference clock input  612 . The phase error signal is filtered by a digital low pass filter  620 . The filtered phase error signal controls the VFO that is implemented as a digitally controlled oscillator (DCO  630 ). The frequency and phase of the DCO vary in response to the filtered phase error signal. Divide-by-N divider  640  will cause the DCO to be driven to generate an output signal CLK_FAST  632  having a frequency that is a multiple (N) of the frequency of the PLL clock output, CLK_OUT  680 . The PLL may be fabricated on a semiconductor substrate  650 . Although only the monitored output  680  is shown (i.e., the output providing the feedback signal, FBK), the PLL may drive multiple outputs. Although not expressly illustrated, the digital function blocks will also be coupled to receive the reference clock as the clock for driving synchronous elements. 
     The delay element  672  contributes a signal delay based upon a delay control value provided by the CTRL_FBK signal  674 . In one embodiment, the delay element  672  is located on the same semiconductor substrate as the other functional blocks of the PLL circuit. The delay contributed by the delay element in the feedback path causes the PLL to advance the phase of the PLL clock output  680  such that it leads the reference clock  660 . The amount of delay is determined by the delay control value provided by CTRL_FBK  674 . 
     The delay element  662  contributes a signal delay based upon a delay control value provided by the CTRL_REF signal  664 . In one embodiment, the delay element  662  is located on the same semiconductor substrate as the other functional blocks of the PLL circuit. The delay contributed by the delay element in the reference clock path causes the PLL to delay the phase of the PLL clock output  680  such that it lags the reference clock  660 . The amount of delay is determined by the delay control value provided by CTRL_REF  664 . 
     The all-digital phase locked loop may be referenced as a digital phase locked loop. Although delay element  662  operates exclusively to delay the DPLL clock output and delay element  672  operates exclusively to advance the DPLL clock output, in one application the delay elements are each programmed to contribute a non-zero delay in order to permit greater resolution control of the amount of phase lead or phase lag of the DPLL clock output  680 . 
     The delay elements may be implemented as analog, digital, or mixed-signal circuitry.  FIG. 7  illustrates one embodiment of a digital delay element  700 . 
     The digital delay element includes serially coupled D flip-flops  710 - 730 . Flip-flops  710 - 730  are clocked by the VFO output signal FAST_CLK  732  which corresponds by analogy to the FAST_CLK  632  of  FIG. 6 . 
     The first D flip-flop in the series receives the clock signal subject to delay at its “D” input. If the delay element is in the reference clock path then the “D” input is REF_CLK  760  (i.e., analogous to REF_CLK  660  of  FIG. 6 ). If the delay element is in the feedback path then the “D” input is CLK_OUT  780  (i.e., analogous to CLK_OUT  680  of  FIG. 6 ). 
     The Q output of each flip-flop is provided to the D input of the next flip-flop in the series. The Q outputs of the D flip-flops are also provided to a multiplexer  740 . The multiplexer selects one of the Q outputs from the plurality of serially coupled D flip-flops in accordance with a control signal. For a delay element in the reference clock path, the control signal CTRL_REF  764  is analogous to CTRL_REF  664  of  FIG. 6 . For a delay element in the feedback path, the control signal is CTRL_FBK  774  which is analogous to CTRL_FBK  674  of  FIG. 6 . 
     The delay element  700  may be utilized as the delay element for any or both of the reference clock delay element or the feedback path delay element. With reference to  FIGS. 3-6 , the CTRL_REF or CTRL_FBK signals serve as the multiplexer select signal to determine which tap of the delay line is selected by the multiplexer. 
     In one embodiment, the phase locked loop circuitry with programmable advance/delay is fabricated on a semiconductor substrate for incorporation into an integrated circuit package. In one embodiment, the integrated circuit package includes a microcontroller to facilitate programmatic control of the phase offset. 
     “Programmable” or “programmatic control” means that the delay control values can be programmatically set and varied and that the value is not permanently fixed at the time of manufacture. This may be accomplished by storing the delay control values in a register, memory, or other storage location from which the values can be retrieved. In one embodiment, the delay control values are stored in volatile memory. In an alternative embodiment, the delay control values are stored in a non-volatile memory in order to preserve the values across power-down cycles of the apparatus. 
     Referring to  FIG. 6 , the microcontroller  690  and memory  692  are illustrated as residing on the same semiconductor substrate  650  as the phase lock loop circuit and delay elements. Circuitry connecting the microcontroller to the delay elements is not expressly illustrated although the microcontroller is coupled to provide either one or both of the CTRL_REF and CTRL_FBK signals as implemented. 
       FIG. 8  illustrates an alternative embodiment of a digital phase lock loop  800  with programmable input/output phase relationship. Phase comparison is handled by time-to-digital converter  810 . The time-to-digital converter receives the PLL clock output (CLK_OUT  880 ) and the reference clock (REF_CLK  860 ). The time-to-digital converter generates a digital code indicative of the measured phase error between CLK_OUT and REF_CLK. The time delay between receipt of selected edges of the REF_CLK and CLK_OUT signals corresponds to phase error. 
     The time delay or phase error may be determined by counting the number of cycles of a higher frequency clock that occur within a window bound by a leading edge of REF_CLK and the leading edge of CLK_OUT, for example. The count corresponds to the phase error. In one embodiment, the time-to-digital converter is configured to express the count as a unary or thermometer coded value. The output of time-to-digital converter  810  is thus the measured phase error expressed as a thermometer coded value. 
     The output of the time-to-digital converter is provided to phase offset block  862 . Phase offset block  862  modifies the measured phase error in accordance with a phase offset control signal, CTRL_PHASE_OFFSET  864 . In one embodiment, the phase offset block is a shift register. 
     The modified phase error value is provided to the digital loop filter  820 . In one embodiment, the digital loop filter is a low pass filter. The output of the digital loop filter is provided to digitally controlled oscillator, DCO  830 . The output of DCO  830  is provided to the divide-by-N divider  840 . Divider  840  will cause the DCO to be driven to generate an output signal CLK_FAST  832  having a frequency that is a multiple (N) of the frequency of the PLL clock output, CLK_OUT  880 . The DCO is driven to cause the frequency of the PLL clock output, CLK_OUT  880 , to match the frequency of the reference clock REF_CLK  860 . The phase of CLK_OUT will match the phase of REF_CLK offset by an offset determined by CTRL_PHASE_OFFSET. The PLL may be fabricated on a semiconductor substrate  850 . Although only the monitored output  880  is shown, the PLL may drive multiple outputs. 
     The embodiment of  FIG. 8  eliminates delay elements in the reference clock path and the feedback path. With reference to  FIG. 6 , for example, delay elements  662 ,  672  are not needed. Instead of placing delay elements at one or more inputs of the phase comparator to alter the input/output phase relationship, the amount of phase lead or lag is controlled by directly modifying the measured or detected phase error. In one embodiment, the phase offset block modifies the measured phase error by shifting a thermometer coded value left or right—shifting in “1” or “0” as appropriate for a thermometer code. For example, given a value of “0011”, the phase offset block can cause additional lag by shifting the given value to the right, i.e., “0001”. The phase offset block can advance CLK_OUT by shifting the value to the left, i.e., “0111”. The phase offset block can control the amount of lead or lag with greater timing resolution as the number of bits of the thermometer code increases. 
     In one embodiment, the phase locked loop circuitry with programmable advance/delay is fabricated on a semiconductor substrate  850  for incorporation into an integrated circuit package. A microcontroller  890  and memory  892  are illustrated as residing on the same semiconductor substrate  850  with the remainder of the phase locked loop circuitry. Circuitry connecting the microcontroller to other elements of the phase locked loop circuit is not expressly illustrated although the microcontroller is coupled to enable programmatic control of phase locked loop circuitry. For example, the microcontroller may programmatically regulate CTRL_PHASE_OFFSET signal. 
       FIG. 9  illustrates one embodiment  900  of a time-to-digital converter and phase offset block corresponding respectively to elements  810  and  862  of  FIG. 8 . The time-to-digital converter includes a delay line  902  with a plurality of buffers  912  each of which contributes a small amount of delay to a signal propagating along the delay line. A plurality of “D” flip-flops  910 - 930  is coupled to the delay line such that the D input of each successive flip-flop taps the output of a successive buffer of the delay line. The input to the delay line is CLK_OUT  980 . Referring to  FIG. 8 , CLK_OUT is presented to the input of the time-to-delay converter  810  by FBK signal  870 . The clock for the plurality of flip-flops is REF_CLK  960  which corresponds to REF_CLK  860  of  FIG. 8 . 
     The phase offset block  862  of  FIG. 8  is implemented as a parallel shift register  962  in  FIG. 9 . The parallel shift register (i.e., phase offset block) receives a measured phase error value from the plurality of flip-flops. The measured phase error value in the illustrated embodiment is a thermometer coded value with [k] as the most significant bit and [0] as the least significant bit. CTRL_PHASE_OFFSET  964  controls the direction and number of bit positions the received thermometer coded value is shifted. The parallel shift register  962  is clocked by CLK_FAST  932  which corresponds to CLK_FAST  832  of  FIG. 8 . In an alternative embodiment, the parallel shift register may be clocked by REF_CLK  860 . The output of the phase offset block is provided to the digital low pass filter. 
       FIG. 10  illustrates one embodiment of a method of controlling the input/output phase relationship of a phase-locked loop circuit. A phase comparator of a phase locked loop circuit provides a detected phase error value to a phase offset block of the phase locked loop circuit in step  1010 . The detected phase error indicates a phase difference between an input reference clock and an output clock of the phase locked loop circuit. 
     In step  1020 , the phase offset block provides a modified phase error value. The phase offset block modifies the detected phase error in accordance with a phase offset control to generate the modified phase error value. A phase relationship between the input reference clock to the phase locked loop circuit and an output clock generated by the phase locked loop circuit varies in accordance with the modified phase error value. 
     In the preceding detailed description, the invention is described with reference to specific exemplary embodiments thereof. Various modifications and changes may be made thereto without departing from the broader scope of the invention as set forth in the claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.