Abstract:
A circuit for controlling an AC-timing parameter of a semiconductor memory device and method thereof are provided. The AC-timing parameter control circuit includes a delay-time-defining portion, a comparing portion, and a controlling portion. The control circuit compares the pulse width or period of an input signal to one or more different reference-widths pulses, with the reference width(s) set by the delay-time-defining portion and the reference pulses generated by the comparing portion. The controlling portion indicates whether the input signal width or period was less than or greater than each o the reference-width pulses. The control circuit output signals can be used to tailor the operation of the device based on a direct comparison of an AC-timing parameter to one or more reference values.

Description:
[0001]    This application claims priority from Korean Patent Application No. 2001-81254, filed on Dec. 19, 2001, the contents of which are incorporated herein by this reference in their entirety.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to a semiconductor memory device, and more particularly, to a circuit for controlling an AC-timing parameter of a semiconductor memory device by recognizing a variation in the AC-timing parameter and controlling the operation of the semiconductor memory device.  
           [0004]    2. Description of the Related Art  
           [0005]    Semiconductor memory device operation-timing (also referred to as AC-timing) parameters define a specific operating time or a time interval between specific operations, and the permitted limit of the operation timing is stipulated so as to guarantee the normal operation of a semiconductor memory device.  
           [0006]    In general, the specified value for a semiconductor memory device AC-timing parameter is defined as a multiple of a predetermined reference time or a cycling time of a reference clock signal The broader the permitted limit of the value of the specification of the AC-timing parameter, the greater guarantee for a better quality semiconductor memory device. As the permitted limit of the specified value for the AC-timing parameter is increased, however, circuit design becomes more difficult as it is difficult to obtain the same operational characteristics within the permitted limit.  
           [0007]    In a conventional semiconductor memory device, the problem is resolved by mounting a selective fuse or a selective metal, or by applying a specific mode register set (MRS) when designing circuitry. In the case of mounting a selective metal, a separate mask is required, and thus the manufacturing cost of the mask increases. In the case of mounting a selective fuse, a space for mounting the fuse must be obtained, and thus the chip size increases. Also, a fuse cutting procedure must be separately included, and thus manufacturing cost and time increase.  
           [0008]    In the case of applying a MRS, a circuit for applying a MRS must be included, and thus the chip size increases. A separate procedure such as fuse cutting is unnecessary, however, and even a finished product can be modified.  
           [0009]    In a case where the AC-timing parameter is varied and there is a need to reflect the variation when applying a MRS, however, a procedure for programming a MRS must be separately performed Thus it is difficult to maintain the same semiconductor memory device operational characteristics and the performance of the semiconductor memory device is lowered.  
         SUMMARY OF THE INVENTION  
         [0010]    It is a first object of the present invention to provide a circuit for controlling a semiconductor memory device AC-timing parameter by recognizing a variation in the AC-timing parameter and controlling the operation of the semiconductor memory device.  
           [0011]    It is a second object of the present invention to provide a method for controlling a semiconductor memory device AC-timing parameter by recognizing a variation in the AC-timing parameter and controlling the operation of the semiconductor memory device.  
           [0012]    It is a third object of the present invention to provide a circuit for recognizing a cycle of a semiconductor memory device reference clock signal and controlling the operation of the semiconductor memory device.  
           [0013]    Accordingly, to achieve the first object, there is provided a circuit for controlling a semiconductor memory device AC-timing parameter. The circuit includes a delay-time-defining portion, a comparing portion, and a controlling portion.  
           [0014]    The delay-time-defining portion receives consecutive input signals and generates first through n-th (n is a natural number) delay signals in which the input signals are delayed by corresponding predetermined delay times.  
           [0015]    The comparing portion receives the input signals and the first through n-th delay signals and generates first through n-th comparison pulse signals, each having an active section for a corresponding predetermined duration.  
           [0016]    The controlling portion receives the input signals and the first through n-th comparison pulse signals, compares the input signals with the first through n-th comparison pulse signals, and generates first through n-th operation control signals for controlling a semiconductor memory device AC timing parameter.  
           [0017]    Here, the input signals are semiconductor memory device clock signals or commands.  
           [0018]    It is preferable that the delay-time-defining portion include a first delay device for generating the first delay signal by receiving the input signals and by delaying the input signals by a predetermined delay time, a second delay device for generating the second delay signal by receiving the first delay signal and by delaying the first delay signal by a predetermined delay time, and an n-th delay device for generating the n-th delay signal by receiving an (n−1)-th delay signal and by delaying the (n−1)-th delay signal by a predetermined delay time.  
           [0019]    It is also preferable that the comparing portion include first through n-th comparing means, which receive the input signals and the corresponding first through n-th delay signals, respectively, and generate the first through n-th comparison pulse signals, each having an active section for a predetermined duration.  
           [0020]    It is also preferable that the controlling portion includes first through n-th operation-controlling parts, which receive the input signals and the corresponding first through n-th comparison pulse signals, respectively, compare times of active sections of the input signals with times of active sections of the corresponding first through n-th comparison pulse signals, and generate first through n-th operation control signals.  
           [0021]    It is also preferable that the circuit further includes an operation-determining portion, which receives the input signals and an operation-enabling signal, and determines whether or not operation input signals are transferred to the delay-time-defining portion.  
           [0022]    To achieve the second object, there is provided a method for controlling a semiconductor memory device AC timing parameter by recognizing a variation in the AC timing parameter and controlling the operation of the semiconductor memory device. The method includes (a) receiving consecutive input signals and generating first through n-th (n is a natural number) delay signals in which the input signals are delayed by corresponding predetermined delay times,  
           [0023]    (b) receiving the input signals and the first through n-th delay signals and generating first through n-th comparison pulse signals, each having an active section for a predetermined duration, and (c) receiving the input signals and the first through n-th comparison pulse signals, comparing the input signals with the first through n-th comparison pulse signals and generating first through n-th operation control signals for controlling an AC-timing parameter of the semiconductor memory device. Here, the input signals are semiconductor memory device clock signals or commands.  
           [0024]    It is preferable that step (a) includes (a1) generating the first delay signal by receiving the input signals and by delaying the input signals by a predetermined delay time, (a2) generating the second delay signal by receiving the first delay signal and delaying the first delay signal by a predetermined delay time, and (a3) generating the n-th delay signal by receiving an (n−1)-th delay signal and by delaying the (n−1)-th delay signal by a predetermined delay time.  
           [0025]    To achieve the third object, there is provided a circuit for recognizing a cycle of a reference clock signal. The circuit includes an operation-determining portion, a delay-time-defining portion, a comparing portion, and a controlling portion.  
           [0026]    The operation-determining portion receives consecutive input signals and an operation-enabling signal and generates an operation-determining signal for controlling the operation of the controlling portion.  
           [0027]    The delay-time-defining portion receives the input signals and generates first and second delay signals, in which the input signals are delayed by corresponding predetermined delay times.  
           [0028]    The comparing portion receives the first and second delay signals and generates first and second comparison pulse signals, each having an active section for a predetermined duration.  
           [0029]    The controlling portion, which receives the operation-determining signal and the first and second comparison pulse signals, compares the operation-determining signal with the first and second comparison pulse signals, and generates first and second operation control signals for controlling the semiconductor memory device.  
           [0030]    It is preferable that the delay-time-defining portion include an odd number of delay devices, which have predetermined delay times and are connected in series.  
           [0031]    It is also preferable that the comparing portion include a first comparing means, which receives the input signals and the corresponding first delay signal and generates the first comparison pulse signal having an active section for a predetermined duration, and a second comparing means, which receives the input signals and the corresponding second delay signal and generates the second comparison pulse signal having an active section for a predetermined duration.  
           [0032]    It is also preferable that the controlling portion includes a first operation-controlling part, which receives the operation-determining signal and the corresponding first comparison pulse signal, compares the duration of an active section of the operation-determining signal with the duration of an active section of the first comparison pulse signal, and generates the first operation control signal for controlling the semiconductor memory device, and a second operation-controlling part, which receives the operation-determining signal and the corresponding second comparison pulse signal, compares the duration of an active section of the operation-determining signal with the duration of an active section of the second comparison pulse signal and generates the second operation control signal for controlling the semiconductor memory device.  
           [0033]    Accordingly, the circuit for controlling an AC-timing parameter of a semiconductor memory device and method thereof according to the present invention can recognize a variation in the AC-timing parameter and can control the operation of the semiconductor memory device suitable for the AC-timing parameter. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0034]    The above objects and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings, wherein:  
         [0035]    [0035]FIG. 1 is a block diagram of a semiconductor memory device AC-timing parameter control circuit, according to a first embodiment of the present invention;  
         [0036]    [0036]FIG. 2 is a flow chart illustrating a method for controlling a semiconductor memory device AC timing parameter according to the first embodiment of the present invention;  
         [0037]    [0037]FIG. 3 is a circuit diagram of a circuit for recognizing a cycle of a reference clock signal according to the first embodiment of the present invention;  
         [0038]    [0038]FIG. 4 is a timing diagram illustrating the operation of the circuit for recognizing a cycle of a reference clock signal shown in FIG. 3;  
         [0039]    [0039]FIG. 5 is a circuit diagram illustrating a circuit using the circuit for recognizing a cycle of a reference clock signal shown in FIG. 3;  
         [0040]    [0040]FIG. 6 is a timing diagram illustrating the operation of the circuit shown in FIG. 5;  
         [0041]    [0041]FIG. 7 is a circuit diagram of a circuit for detecting a RAS time using the AC-timing parameter control circuit shown in FIG. 1;  
         [0042]    [0042]FIG. 8 is a block diagram of an internal voltage generator using a signal for controlling the operation of the circuit shown in FIG. 7;  
         [0043]    [0043]FIG. 9 is a timing diagram illustrating the operation of the internal voltage generator shown in FIG. 8;  
         [0044]    [0044]FIG. 10 is a circuit diagram of a circuit for detecting a RC time using the AC-timing parameter control circuit shown in FIG. 1;  
         [0045]    [0045]FIG. 11 illustrates a circuit for generating a control signal having information related to an RC time; and  
         [0046]    [0046]FIG. 12 is a timing diagram illustrating the operation of the circuits shown in FIGS. 10 and 11.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0047]    The present invention is described herein with reference to the accompanying drawings in which preferred embodiments of the invention are shown. Like reference numerals refer to like elements throughout the drawings.  
         [0048]    [0048]FIG. 1 is a block diagram of AC-timing-parameter control circuit according to a first embodiment of the present invention. Referring to FIG. 1, an AC-timing-parameter includes a delay-time-defining portion  110 , a comparing portion  130 , and a controlling portion  150 .  
         [0049]    The delay-time-defining portion  110  receives consecutive input signals INCK (through optional operation—determining portion  160  in FIG. 1), generates first through n-th (n is a natural number) delay signals DES 1 , DES 2 , . . . , DESn in which the input signals INCK are delayed by corresponding a predetermined delay times.  
         [0050]    The input signals INCK are semiconductor memory device clock signals or commands. More specifically, the delay-time-defining portion  110  includes several delay devices in series: a first delay device  111  in which the input signals INCK are received and delayed by a predetermined delay time; a second delay device  112  in which the first delay signal DES 1  is received and delayed by a predetermined delay time; and a “last” or n-th delay device  113  in which an (n−1)-th delay signal (not shown) is received and delayed by a predetermined delay time.  
         [0051]    In this embodiment, the first, second, and n-th delay devices  111 ,  112 , and  113  have different delay times. However, the first, second, and n-th delay devices  111 ,  112 , and  113  may have the same delay time depending on the circuit configuration.  
         [0052]    The comparing portion  130  receives the input signals INCK and the first through n-th delay signals DES 1 , DES 2 , . . . , DESn, and generates first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . , COMPn, each having an active section for a predetermined duration.  
         [0053]    More specifically, the comparing portion  130  includes first through n-th comparing means  131 ,  132 , and  133 , which each receive the input signals INCK, respectively receive the corresponding first through n-th delay signals DES 1 , DES 2 , . . . , DESn, and respectively generate the first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . , COMPn, each having an active section for a predetermined duration. The first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . , COMPn have active sections with different durations.  
         [0054]    The controlling portion  150  receives the input signals INCK and the first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . , COMPn, compares the input signals INCK with the first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . , COMPn, and generates first through n-th operation control signals OPCON 1 , OPCON 2 , . . . , OPCONn for controlling an AC-timing parameter.  
         [0055]    More specifically, the controlling portion  150  includes first through n-th operation-controlling parts  151 ,  152 , and  153 , which each receive the input signals INCK, respectively receive the corresponding first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . , COMPn, compare the duration of the active section of each of the input signals INCK with the duration of the active section of the corresponding first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . , COMPn, and generate first through n-th operation control signals OPCON 1 , OPCON 2 , . . . , OPCONn for controlling an AC-timing parameter.  
         [0056]    Here, the first through n-th operation control signals OPCON 1 , OPCON 2 , . . ., OPCONn represent whether the active section of each of the input signals INCK is longer or shorter than that of the corresponding first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . , COMPn, depending on the logic level of the corresponding first through n-th operation control signals OPCON 1 , OPCON 2 , . . . , OPCONn.  
         [0057]    The AC-timing-parameter control circuit  100  may further include an operation-determining portion  160 , which receives the input signals INCK and an operation-enabling signal OPES. The state of operation-enabling signal OPES determines whether operation-input signals OUTCK are transferred to the delay time defining portion  110  or not. Thus circuit  100  is enabled when OPES is asserted and disabled otherwise  
         [0058]    Here, the operation-enabling signal OPES is generated by a mode register set (MRS), but OPES also may be generated by an external command or an internal signal other than a MRS. The operation-determining portion  160  may be a NAND gate.  
         [0059]    Hereinafter, the operation of the AC-timing-parameter control circuit will be described in detail with reference to FIG. 1.  
         [0060]    The delay-time-defining portion  110  receives the predetermined consecutive input signals INCK and generates first through n-th delay signals DES 1 , DES 2 , . . . , DESn in which the input signals INCK are delayed by corresponding predetermined delay times.  
         [0061]    The input signals INCK may be clock signals or commands of a semiconductor memory device. For example, if control circuit  100  recognizes the cycle of the memory device reference clock signal, and thereby controls the specific operation of the semiconductor memory device, the reference clock signal may be used for the input signals INCK. If control circuit  100  recognizes a row address strobe (RAS) time (usually marked tRAS), and thereby controls the specific operation of the semiconductor memory device, a row active (RA) signal may be used for the input signals INCK. Here, the RAS time is the time required from when the RA signal is enabled to when a row precharge (RP) signal is enabled.  
         [0062]    The delay-time-defining portion  110  includes first through n-th delay devices  111 ,  112 , and  113 . The first delay device  111  generates the first delay signal DES 1  by receiving the input signals INCK and delaying the input signals INCK by a predetermined delay time. The first delay signal DES 1  is applied to the first comparing means  131  of the comparing portion  130  (to be described later), and to the second delay device  112 . The second delay device  112  generates the second delay signal DES 2  by receiving the first delay signal DES 1  and delaying the first delay signal DES 1  by a predetermined delay time. The second delay signal DES 2  is applied to the second comparing means  132  of the comparing portion  130  and to a second delay device (not shown). Similarly, the n-th delay device  113  generates the n-th delay signal DESn in which an (n−1)-th delay signal (not shown) is received and delayed by a predetermined delay time. The first through n-th delay devices  111 ,  112 , and  113  may be comprised of logic devices, such as a buffer, for delaying signals. In this embodiment, the first through n-th delay devices  111 ,  112 , and  113  have different delay times but may be embodied to have the same delay time.  
         [0063]    Since the first delay signal DES 1  is generated by delaying the input signals INCK only by the first delay device DES 1 , the first delay signal DES 1  is different from the second delay signal DES 2 , which is generated by delaying the input signals INCK by the first and second delay devices  111  and  112 . That is, the degree of the delays of the first through n-th delay signal for each DES 1 , DES 2 , . . . , DESn is different.  
         [0064]    The comparing portion  130  receives the input signals INCK and the first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . , COMPn and generates the first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . , COMPn, each having an active section for a predetermined duration.  
         [0065]    The comparing portion  130  includes the first through n-th comparing means  131 ,  132 , and  133 . The first comparing means  131  receives the input signals INCK and the corresponding first delay signal DES 1  and generates the first comparison pulse signal COMP 1  having an active section for a predetermined duration. The second comparing means  132  receives the input signals INCK and the corresponding second delay signal DES 2  and generates the second comparison pulse signal COMP 2  having an active section for a predetermined duration. Similarly, the n-th comparing means  133  receives the input signals INCK and the corresponding n-th delay signal DESn and generates the n-th comparison pulse signal COMPn having an active section for a predetermined duration. The degree of the delay for each of the first through n-th delay signals DES 1 , DES 2 , . . . , DESn is different, and thus active sections of the first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . , COMPn have different durations.  
         [0066]    The controlling portion  150  receives the input signals INCK and the first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . , COMPn, compares the input signals INCK with the first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . , COMPn, and generates first through n-th operation control signals OPCON 1 , OPCON 2 , . . . , OPCONn for controlling an AC-timing parameter.  
         [0067]    The controlling portion  150  includes first through n-th operation-controlling parts  151 ,  152 , and  153 . The first operation-controlling part  151  receives the input signals INCK and the corresponding first comparison pulse signal COMP 1 , compares the duration of an active section of each of the input signals INCK with the duration of an active section of the corresponding first comparison pulse signal COMP 1 , and generates the first operation control signal OPCON 1  for controlling an AC-timing parameter. The second operation controlling part  152  receives the input signals INCK and the corresponding second comparison pulse signal COMP 2 , compares the duration of an active section of each of the input signals INCK with the duration of an active section of the corresponding second comparison pulse signal COMP 2 , and generates the second operation control signal OPCON 2  for controlling the AC-timing parameter. Similarly, the n-th operation-controlling part  153  receives the input signals INCK and the corresponding n-th comparison pulse signal COMPn, compares the duration of an active section of each of the input signals INCK with the duration of an active section of the corresponding n-th comparison pulse signal COMPn, and generates the n-th operation control signal OPCONn for controlling the AC-timing parameter.  
         [0068]    Here, the first through n-th operation control signals OPCON 1 , OPCON 2 , . . ., OPCONn represent whether the active section of each of the input signals INCK is longer or shorter than that of the corresponding first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . , COMPn, depending on the logic level of the corresponding first through n-th operation control signals OPCON 1 , OPCON 2 , . . . , OPCONn. That is, the first through n-th operation-controlling parts  151 ,  152 , and  153  compare the first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . , COMPn, respectively, with the beginning of the next period of input signals INCK.  
         [0069]    Since the delay times of the first through n-th delay devices  111 ,  112 , and  113  are known, the durations of sections in which the first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . , COMPn are enabled can be known. Thus it can be known whether the active section of each of the input signals INCK is longer or shorter than that of the corresponding first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . , COMPn, depending on whether the corresponding first through n-th operation control signals OPCON 1 , OPCON 2 , . . . , OPCONn are output at a high level or a low level.  
         [0070]    Thus by using the first through n-th operation control signals OPCON 1 , OPCON 2 , . . . , OPCONn, if it is determined that the active sections of the input signals INCK are longer than the time required for a predetermined operation of a semiconductor memory device, the semiconductor memory device performs a first operation, and if it is determined that the active sections of the input signals INCK are shorter than the time required for a predetermined operation of the semiconductor memory device, a circuit for performing a second operation is mounted in the semiconductor memory device, thereby controlling the operation of the semiconductor memory device.  
         [0071]    Control circuit  100  may further include an operation-determining portion  160 , which receives the input signals INCK and the operation-enabling signal OPES. OPES determines whether or not the operation input signals OUTCK are transferred to the delay time defining portion  110 . That is, in a case where there is no need to use control circuit  100  to control an AC-timing parameter, the operation-enabling signal OPES is applied to the operation-determining portion  160  such that the input signals INCK are not applied to the delay-time-defining portion  110 , and control circuit  100  does not operate. The operation-determining portion  160  may also control the comparing portion  130  or the controlling portion  150  to control operation of control circuit  100  control.  
         [0072]    Here, the operation-enabling signal OPES may be generated by a MRS. That is, if the semiconductor memory device meets predetermined conditions by adjusting the MRS, the operation-enabling signal OPES is generated so as to disable control circuit  100 . The operation enabling signal OPES may also be generated by an external command or an internal signal other than the MRS.  
         [0073]    [0073]FIG. 2 is a flow chart illustrating a method for controlling an AC timing parameter of a semiconductor memory device according to the first embodiment of the present invention. This method is described with reference to FIGS. 1 and 2.  
         [0074]    In the method, which is capable of recognizing an AC-timing parameter and controlling the operation of a semiconductor memory device, in step  210 , the first through n-th (n is a natural number) delay signals DES 1 , DES 2 , . . . , DESn are generated by delaying input signals INCK by a predetermined delay time. More specifically, in step  210 , an input signal INCK is received and delayed by a predetermined delay time, thereby generating the first delay signal DES 1 . The first delay signal DES 1  is used to generate the second delay signal DES 2  and a first comparison pulse signal COMP 1  to be described later. The first delay signal DES 1  is received and delayed by a predetermined delay time, thereby generating the second delay signal DES 2 . In this way, an (n−1)-th delay signal DESn−1 is received and delayed by a predetermined delay time, thereby generating the n-th delay signal DESn.  
         [0075]    Here, the predetermined delay times for delaying the input signals INCK are different. Thus, the first through n-th delay signals DES 1 , DES 2 , . . . , DESn have different delay times. However, times for delaying the input signals may be equalized depending on a method for forming a circuit that operates according to the method ( 200 ) for controlling an AC-timing parameter of a semiconductor memory device.  
         [0076]    The input signals INCK may be semiconductor memory device clock signals or commands. For example, if the method ( 200 ) for controlling an AC-timing parameter recognizes the cycle of the semiconductor memory device reference clock signal of, and thereby controls the specific operation of the semiconductor memory device, the reference clock signal may be used for the input signals INCK. If the method ( 200 ) recognizes a row address strobe (RAS) time (usually marked tRAS), and thereby controls the specific operation of the semiconductor memory device, a row active (RA) signal may be used for the input signals INCK. Here, the RAS time is the time required from when the RA signal is enabled to when a row precharge (RP) signal is enabled.  
         [0077]    In addition, an operation-enabling signal OPES can determine whether or not the input signals are applied. Thus, in a case where there is no need to use the method ( 200 ) for controlling an AC-timing parameter of a semiconductor memory device, the operation-enabling signal OPES is generated such that the input signals are not applied to control circuit  100 , and control circuit  100  does not operate. The operation-enabling signal may be generated by a MRS. That is, if the semiconductor memory device meets predetermined conditions by adjusting the MRS, the operation-enabling signal is generated so as to not use the method ( 200 ) for controlling an AC-timing parameter. The operation-enabling signal may also be generated by an external command or an internal signal other than the MRS.  
         [0078]    In step  220 , the input signals INCK and the first through n-th delay signals DES 1 , DES 2 , . . . , DESn are received, and the first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . , COMPn, each having an active section for a predetermined duration, are generated. More specifically, in step  220 , the input signals and the corresponding first delay signal DES 1  are received and used to generate the first comparison pulse signal COMP 1  having an active section with predetermined duration. In the same way, the second through n-th comparison pulse signals COMP 2 , . . . , COMPn, are generated. The input signals are compared with the first through n-th delay signals DES 1 , DES 2 , . . . , DESn, which are generated by delaying the input signals INCK, and the first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . , COMPn, are generated, each having a pulse shape. In addition, the degree of the delay for the first through n-th delay signals DES 1 , DES 2 , . . . , DESn is different, and thus active sections of the first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . COMPn, have different durations.  
         [0079]    In step  230 , the input signals INCK and the first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . COMPn are received, the input signals INCK are compared with the first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . COMPn, and the first through n-th operation control signals OPCON 1 , OPCON 2 , . . . , OPCONn, for controlling an AC-timing parameter of the semiconductor memory device, are generated. More specifically, in step  230 , the input signals INCK and the corresponding first comparison pulse signal COMP 1  are received, the duration of the active section of each of the input signals INCK is compared with the duration of an active section of the corresponding first comparison pulse signal COMP 1 , and the first operation control signal OPCON 1  for controlling an AC timing parameter of the semiconductor memory device is generated. In the same way, the second through n-th operation control signals OPCON 1 , OPCON 2 , . . . , OPCONn are generated.  
         [0080]    The first through n-th operation control signals OPCON 1 , OPCON 2 , . . . , OPCONn represent whether the active sections of the input signals INCK are longer or shorter than those of the first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . , COMPn, depending on the logic levels of the first through n-th operation control signals OPCON 1 , OPCON 2 , . . . , OPCONn. Since a user knows the delay times of the first through n-th delay signals OPCON 1 , OPCON 2 , . . . , OPCONn, it can be known how long the first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . , COMPn are enabled. Thus, it can be known whether the active sections of the input signals INCK are longer or shorter than those of the first through n-th comparison pulse signals COMP 1 , COMP 2 , . . . , COMPn, depending on whether the first through n-th operation control signals OPCON 1 , OPCON 2 , . . . , OPCONn are output at a high level or a low level. That is, by using the first through n-th operation control signals OPCON 1 , OPCON 2 , . . . , OPCONn, if it is determined that the active sections of the input signals INCK are longer than the time required for a predetermined operation of a semiconductor memory device, the semiconductor memory device performs a first operation, and if it is determined that the active sections of the input signals INCK are shorter than the time required for a predetermined operation of the semiconductor memory device, the semiconductor memory device performs a second operation. Thus the operation of the semiconductor memory device can be altered for different inpur signal timing patterns.  
         [0081]    [0081]FIG. 3 is a circuit diagram of a circuit for recognizing a cycle of a reference clock signal according to the first embodiment of the present invention. Referring to FIG. 3, circuit  300  includes an operation-determining portion  310 , a delay-time-defining portion  320 , a comparing portion  330 , and a controlling portion  340 .  
         [0082]    The operation-determining portion  310  receives consecutive input signals INCK and an operation-enabling signal OPES, and generates an operation-determining signal OPDS for controlling the operation of the controlling portion  340 . Here, the input signal INCK is a reference clock signal, i.e., an externally input clock signal used to operate the semiconductor memory device. The operation-determining portion  310  is a flip-flop. Flip-flop  310  receives the operation enabling signal OPES at an input terminal D, receives the input signal INCK at a clock input terminal, and outputs the operation-determining signal OPDS at an output terminal Q.  
         [0083]    The delay-time-defining portion  320  receives input signal INCK and generates first and second delay signals DES 1  and DES 2  in which the input signal INCK is delayed by a predetermined delay time. The delay-time-defining portion  320  includes an odd number of delay devices ( 321 ,  323 ,  325 ,  327 , and  329  are shown), which have predetermined delay times and are connected in series. More specifically, in this embodiment the delay devices  321 ,  323 ,  325 ,  327 , and  329  have different delay times but may be embodied to have the same delay time.  
         [0084]    The output of the third delay device  325  becomes second delay signal DES 2 . The output of the fifth delay device  329  becomes first delay signal DES 1 .  
         [0085]    The comparing portion  330  receives the first and second delay signals DES 1  and DES 2 , and generates first and second comparison pulse signals COMP 1  and COMP 2 , each having an active section for a predetermined duration. More specifically, the comparing portion  330  includes: a first comparing means  331 , which receives the input signal INCK and the corresponding first delay signal DES 1 , and generates the first comparison pulse signal COMP 1  having an active section with a predetermined duration; and a second comparing means  333 , which receives the input signal INCK and the corresponding second delay signal DES 2 , and generates the second comparison pulse signal COMP 2  having an active section with a predetermined duration. The first and second comparing means  331  and  333  may be NAND gates. The delay times of the first and second delay signals DES 1  and DES 2  are different, and thus the first and second comparison pulse signals COMP 1  and COMP 2  have active sections with different durations.  
         [0086]    The controlling portion  340  receives the operation-determining signal OPDS and the first and second comparison pulse signals COMP 1  and COMP 2 , compares the operation-determining signal OPDS with the first and second comparison pulse signals COMP 1  and COMP 2 , and generates first and second operation control signals OPCON 1  and OPCON 2  for controlling a semiconductor memory device. More specifically, the controlling portion  340  includes a first operation-controlling part  350 , which receives the operation-determining signal OPDS and the corresponding first comparison pulse signal COMP 1 , compares the duration of an active section of the operation-determining signal OPDS with the duration of an active section of the first comparison pulse signal COMP 1 , and generates the first operation control signal OPCON 1  for controlling the semiconductor memory device, and a second operation-controlling part  360 , which receives the operation-determining signal OPDS and the corresponding second comparison pulse signal COMP 2 , compares the duration of an active section of the operation-determining signal OPDS with the duration of an active section of the second comparison pulse signal COMP 2 , and generates the second operation control signal OPCON 2  for controlling the semiconductor memory device.  
         [0087]    The first and second operation control signals OPCON 1  and OPCON 2  represent whether the active section of the operation-determining signal OPDS is longer or shorter than that of the corresponding first or second comparison pulse signal COMP 1  or COMP 2 , depending on the logic level of the corresponding first or second operation control signal OPCON 1  or OPCON 2 .  
         [0088]    More specifically, the first operation-controlling part  350  includes: a first inverter  351 , which receives and inverts the operation-determining signal OPDS;  
         [0089]    a first transmission gate  352 , which transmits the first comparison pulse signal COMP 1  to a first latching unit  353  in response to the operation-determining signal OPDS and the first inverter  351  output; the first latching unit  353 , which includes a second inverter  354  for inverting the output of the first transmission gate  352  and a third inverter  355  for inverting the output of the second inverter  354  and applying the output to the second inverter  354 ; a second transmission gate  356 , which transmits the output of the first latching unit  353  to a fourth inverter  357  in response to the operation-determining signal OPDS and the first inverter  351  output; and the fourth inverter  357 , which inverts the output of the second transmission gate  356  and generates the first operation control signal OPCON 1 .  
         [0090]    The second operation-controlling part  360  is illustrated as identical to operation-controlling part  350 , but receives companion pulse signal COMP 2  and operation-determining signal OPDS, and generates second operation control signal OPCON 2 .  
         [0091]    [0091]FIG. 4 is a timing diagram illustrating the operation of circuit  300 . In order to operate the circuit  300  for recognizing a cycle of a reference clock signal, the operation-enabling signal OPES is first applied at a high level. If an n-th clock pulse of the input signal INCK is enabled at a high level, the operation-determining signal OPDS is enabled at a high level in response to the input signal INCK and the operation enabling signal OPES.  
         [0092]    The input signal INCK applied to the delay-time-defining portion  320  passes through all of the delay devices  321 ,  323 ,  325 ,  327 , and  329 , thereby generating the first delay signal DES 1 . The first delay signal DES 1  is applied to the first comparing means  331  of the comparing portion  330 . The input signal INCK passes through only three delay devices  321 ,  323 , and  325  to generate the second delay signal DES 2 . The second delay signal DES 2  is applied to the second comparing means  333  of the comparing portion  330 .  
         [0093]    The first comparing means  331  receives the first delay signal DES 1  and the input signal INCK, and generates the first comparison pulse signal COMP 1 . The second comparing means  333  receives the second delay signal DES 2  and the input signals INCK, and generates the second comparison pulse signal COMP 2 . The configurations of the delay time defining portion  320  and the comparing portion  330  are the same as that of an auto pulse generator. Thus, the first and second comparison pulse signals COMP 1  and COMP 2  have a pulse shape. If the delay time of the delay-time-defining portion  320  delay devices  321 ,  323 ,  325 ,  327 , and  329  is “T”, respectively, the first comparison pulse signal COMP 1  has a delay time of  5 T, and the second comparison pulse signal COMP 2  has a delay time of  3 T. This is clearly shown in FIG. 4.  
         [0094]    When the (n+1)-th clock pulse of the input signal INCK is input to the operation-determining portion  301 , the operation-determining signal OPDS transitions to a low level. The controlling portion  340  compares the operation-determining signal OPDS with the first and second comparison pulse signals COMP 1  and COMP 2  when the operation-determining signal OPDS returns to a low level, and generates the. first and second operation control signals OPCON 1  and OPCON 2 . The first and second operation control signals OPCON 1  and OPCON 2  have information related to whether the operation-determining signal OPDS is longer or shorter than a predetermined delay times generated by the delay-time-defining portion  320 .  
         [0095]    Here, the operation-determining signal OPDS is enabled at the rising edge of the input signal INCK clock pulse n, and is disabled from the next rising edge of the input signal INCK at clock pulse n+1, and thus has an active section of one cycle of the input signal INCK. Thus, the first and second operation control signals OPCON 1  and OPCON 2  have information related to whether a cycle of the input signal INCK is longer or shorter than a predetermined time.  
         [0096]    The operation of the controlling portion  340  will now be described in greater detail. When the operation-determining signal OPDS is applied to the first inverter  351  of the first operation-controlling part  350  at a high level, the first transmission gate  352  is turned on, and the first comparison pulse signal COMP 1  is applied to and latched in the first latching unit  353 . An NMOS transistor MN 1 , whose on or off state is controlled by a reset signal RESET, initializes the first latching unit  353  prior to OPDS assertion.  
         [0097]    When the operation-determining signal OPDS returns to a low level and is applied to the first inverter  351 , the first transmission gate  352  is turned off, and the second transmission gate  356  is turned on. Then, the first comparison pulse signal COMP 1  is output from the first latching unit  353  and is generated as the first operation control signal OPCON 1  through the fourth inverter  357 . Referring to FIG. 4, the first comparison pulse signal COMP 1  is in a low-level state when the operation-determining signal OPDS returns to a low level, and thus the first operation control signal OPCON 1  is also generated at a low level. That is, in a case where the operation-determining signal OPDS is shorter than the first comparison pulse signal COMP 1 , the first operation control signal OPCON 1  is generated at a low level.  
         [0098]    The operation of the second operation-controlling part  360  is the same as that of the first operation-controlling part  350 , and thus a detailed description thereof will be omitted. Referring to FIG. 4, the second comparison pulse signal COMP 2  is in a high-level state when the operation-determining signal OPDS is at a low level, and thus the second operation control signal OPCON 2  is also generated at a high level. That is, in a case where the operation-determining signal OPDS is longer that the second comparison pulse signal COMP 2 , the second operation control signal OPCON 2  is generated at a high level.  
         [0099]    Thus, it can be known whether the cycle of the input signal INCK is longer or shorter than a predetermined time, depending on the logic level of the first or second operation control signal OPCON 1  or OPCON 2 , and the result may be used to control the operation of the semiconductor memory device.  
         [0100]    [0100]FIG. 5 is a circuit diagram illustrating a circuit  500  that uses OPCON 1  and OPCON 2  to control device operation. The circuit  500  shown in FIG. 5 includes: an inverter  505 , for inverting a clock signal CLK; transmission gates  511 ,- 517 ,  521 , and  527 , whose on or off state is controlled in response to the output of the inverter  505 ; inverters  513 ,  515 ,  523 , and  525  for forming latches; inverters  519  and  529 , for inverting outputs of the transmission gates  517  and  527 ; a NAND gate  530 , which receives the first and second operation control signals OPCON 1  and OPCON 2  and the output of the inverter  519 , and compares the first and second operation control signals OPCON 1  and OPCON 2  with the output of the inverter  519 ; an inverter  535 , which inverts the output of the NAND gate  530  and generates the output as a first output signal OUT 1 ; a NAND gate  540 , which compares the second operation control signal OPCON 2  with the output of the inverter  529 ; and an inverter  545 , which inverts the output of the NAND gate  540  and generates the output as a second output signal OUT 2 .  
         [0101]    [0101]FIG. 6 is a timing diagram illustrating the operation of the circuit shown in FIG. 5. Specifically, FIG. 6A illustrates that an input control signal INS is not generated as the first output signal OUT 1  or the second output signal OUT 2  in a case where both the first and second operation control signals OPCON 1  and OPCON 2  are at a low level.  
         [0102]    [0102]FIG. 6B illustrates that the input control signal INS is generated as the first output signal OUT 1  in a case where both the first and second operation control signals OPCON 1  and OPCON 2  are at a high level.  
         [0103]    [0103]FIG. 6C illustrates that the input control signal INS is generated as the second output signal OUT 2  in a case where the first operation control signal OPCON 1  is at a low level and the second operation control signal OPCON 2  is at a high level.  
         [0104]    Hereinafter, the operation of the circuit  500  will be described with reference to FIGS. 5 and 6.  
         [0105]    The circuit  500  of FIG. 5 operates in response to a clock signal CLK. Here, the clock signal CLK may be an internal clock signal or a reference clock signal.  
         [0106]    The input control signal INS applied to the transmission gate  511  is a signal generated in the semiconductor memory device and controls a predetermined operation of the semiconductor memory device.  
         [0107]    The circuit  500  of FIG. 5 controls the predetermined operation of the semiconductor memory device by generating the input control signal INS as the first output signal OUT 1  or the second output signal OUT 2  depending on the logic level of the first and second operation control signals OPCON 1  and OPCON 2 , that is, depending on whether the input signal INCK cycles are longer or shorter than a predetermined delay time. In other words, the predetermined operation of the semiconductor memory device can be controlled according to the length of one cycle of the reference clock signal.  
         [0108]    When the clock signal CLK is at a high level and applied to the inverter  505 , the transmission gate  511  is turned on, and the input control signal INS is applied to a latch  516 , which is comprised of the inverters  513  and  516 . Here, an NMOS transistor MN 1  receives the reset signal RESET and initializes the latch  516 . When the clock signal CLK is at a low level and applied to the inverter  505 , the transmission gate  517  is turned on, and thus the latched input control signal INS is applied to the NAND gate  530  through the inverter  519 . In such a case, it is determined whether the input control signal INS applied to the NAND gate  530  is output as the first output signal OUT 1  or not, depending on the logic levels of the first and second operation control signals OPCON 1  and OPCON 2 .  
         [0109]    If any one of the first and second operation control signals OPCON 1  and OPCON 2  is at a low level, the input control signal INS cannot be output. In a case where both the first and second operation control signals OPCON 1  and OPCON 2  are at a high level, the input control signal INS is generated as the first output signal OUT 1 . This is clearly shown in FIG. 6B.  
         [0110]    At the next positive pulse edge of the clock signal CLK, transmission gate  521  is turned on, and the input control signal INS from the prior CLK positive pulse edge is applied to a latch  526 , which is comprised of the inverters  523  and  525 , from the inverter  519 . Here, an NMOS transistor MN 2  receives the reset signal RESET and initializes the latch  526 . When the clock signal CLK subsequently transitions back to a low level, the transmission gate  527  is turned on. Thus the latched input control signal INS, from two positive CLK edges prior is applied to the NAND gate  540  through the inverter  529 .  
         [0111]    In such a case, it is determined whether or not the input control signal INS applied to the NAND gate  540  is output as the second output signal OUT 2  or not, depending on the logic level of the second operation control signal OPCON 2 .  
         [0112]    In a case where the first operation control signal OPCON 1  is at a low level and the second operation control signal OPCON 2  is at a high level, the input control signal INS is generated as the second output signal OUT 2 . This is clearly shown in FIG. 6C. In other cases, the input control signal INS cannot be generated as the second output signal OUT 2 .  
         [0113]    That is, in a case where both the first and second operation control signals OPCON 1  and OPCON 2  are at a low level, the input control signal INS cannot be output to the outside. In a case where the first operation control signal OPCON 1  is at a low level and the second operation control signal OPCON 2  is at a high level, the input control signal INS is output to the outside after two cycles of the clock signal CLK passes. In a case where both the first and second operation control signals OPCON 1  and OPCON 2  are at a high level, the input control signal INS is output to the outside after only one cycle of the clock signal CLK has passed.  
         [0114]    In connection with the circuit  300  for recognizing a cycle of a reference clock signal shown in FIG. 3, the first operation control signal OPCON 1  is generated at a low level in a case where one cycle of the input signal INCK is shorter than the first comparison pulse signal COMP 1 , and the second operation control signal OPCON 2  is generated at a high level in a case where one cycle of the input signal INCK is longer than the second comparison pulse signal COMP 2 . Thus, if the input signal INCK, that is, one cycle of the reference clock signal, is greater than a first predetermined time (an enabling time of the second comparison pulse signal COMP 2 ) and is less than a second predetermined time (an enabling time of the first comparison pulse signal COMP 1 ), the input control signal INS is output to the outside after two cycles of the clock signal CLK passes.  
         [0115]    In the case of applying this to the circuit  500  of FIG. 5, the input control signal INS is not output to the outside when one cycle of the reference clock signal is less than the first predetermined time, the input control signal INS is output to the outside after only one cycle of the clock signal CLK passeswhen the cycle of the reference clock signal is greater than the second predetermined time, and the input control signal INS is output to the outside after two cycles of the clock signal CLK pass when the cycle of the reference clock signal is between the first predetermined time and the second predetermined time.  
         [0116]    [0116]FIG. 7 is a circuit diagram of a circuit for detecting a RAS time using the circuit for controlling an AC timing parameter of a semiconductor memory device shown in FIG. 1.  
         [0117]    Referring to FIG. 7, the circuit  700  for detecting a RAS time has a configuration similar to the circuit  300  for recognizing a cycle of a reference clock signal shown in FIG. 3. That is, the circuit  700  includes: a delay-time-defining portion  710 , which receives a row active command RA; a comparing portion  720 , which receives the output of the delay-time-defining portion  710  and the row active command RA and compares the two to generate a comparison signal COMP; and a controlling portion  730 , which compares the row active command RA with the comparison signal COMP and generates an operation control signal TRAS.  
         [0118]    The delay time defining portion  710  includes delay devices  711 ,  712 , and  713 . The comparing portion  720  is comprised of a NAND gate. And the controlling portion  730  has a configuration similar to the first or second controlling portion  350  or  360  of FIG. 3.  
         [0119]    In view of the operation of the circuit  700 , a RAS time means the time required for a precharge command to be enabled after the row active command RA is enabled. If the precharge command is enabled after the row active command RA is enabled, the row active command RA is disabled, and thus RAS time is the time required from when the row active command RA is enabled to when it is again disabled.  
         [0120]    The operation of the circuit  700  for detecting a RAS time shown in FIG. 7 is similar to that of the circuit  300  for recognizing a cycle of a reference clock signal shown in FIG. 3. That is, if the row active command RA is applied to the delay-time-defining portion  710 , the delay-time-defining portion  710  delays the row active command RA for a predetermined time and applies the row active command RA to the comparing portion  720 . The comparing portion  720  compares the output of the delay-time-defining portion  710  with the row active command RA and generates a comparison pulse signal COMP having a predetermined active section. The controlling portion  730  receives the comparison pulse signal COMP and the row active command RA, compares whether the row active command RA is longer or shorter than the comparison pulse signal COMP when the row active command RA transitions low, and thus generates the operation control signal TRAS. Thus, the operation control signal TRAS has information related to whether the row active command RA is longer or shorter than the comparison pulse signal COMP.  
         [0121]    RAS time, as described above, means the time required for the row active command RA to be enabled and then disabled. In the embodiment of FIG. 7, it is assumed that the RAS time recognizes whether the row active command RA is longer or shorter than the comparison pulse signal COMP every RC time. Here, RC time means the time required for the row active command RA is to be re-enabled after the row active command RA is enabled and disabled. Thus, as with the circuit  300  for recognizing a cycle of a reference clock signal shown in FIG. 3, there is no need to include a separate circuit for generating an operation-determining signal OPDS so as to select a time for recognizing a cycle of a reference clock signal.  
         [0122]    [0122]FIG. 8 is a block diagram of an internal voltage generator using a signal for controlling the operation of the circuit shown in FIG. 7. A conventional internal voltage generator  800  includes: a voltage generator  810 , which receives an external voltage EV and generates an internal voltage IV; a pulse generator  820 , which generates a pulse signal in response to a row active (RA) command; and a voltage generator  830 , which generates a predetermined voltage in response to the external voltage EV and output OVDRV_N of the pulse generator  820 . The internal voltage generator  800  of FIG. 8 additionally includes a pulse generator  840 , which generates a pulse signal in response to an operation control signal TRAS generated in circuit  700  of FIG. 7, and a voltage generator  850 , which generates a predetermined voltage in response to output OVDRV_S of the pulse generator  840  and the external voltage EV.  
         [0123]    [0123]FIG. 9 illustrates the operation of the internal voltage generator shown in FIG. 8.  
         [0124]    Consumption of power in a memory array is increased when the row active command RA is enabled in the semiconductor memory device, and thus the level of the internal voltage IV drops considerably. This internal voltage drop is shown as a time segment marked VDIP in FIG. 9. Thus, most semiconductor memory devices include a circuit that compensates for voltage drop of the internal voltage IV.  
         [0125]    As an example of a compensation circuit, there is a circuit for generating a short pulse signal OVDRV_N when the row active command RA is enabled, and then generating additional power in response to the short pulse signal OVDRV_N, thereby instantly increasing the driving capability of the voltage generator  810 . With this method, however, due to problems such as overshooting the driving capability of the voltage generator  810  cannot be infinitely increased.  
         [0126]    Some of the voltage drop is compensated for by a circuit that generates a pulse signal in response to the row active command RA and then generates a predetermined voltage. The remaining drop in voltage is compensated for by the normal operation of the voltage generator  810  for a RAS time. If the RAS time is sufficient, compensating for the voltage drop by using the pulse generator  820  and the voltage generator  830 , which are operated by the row active command RA, may operate effectively. But if the RAS time is decreased, the voltage generator  810  may not operate effectively, and thus it becomes difficult to compensate for the drop in the internal voltage IV.  
         [0127]    In order to solve the problem, the pulse generator  840  and the voltage generator  850 , which operate in response to the operation control signal TRAS output from circuit  700  are added to the internal voltage generator  800 . In other words, if the RAS time is shorter than a preset time, then the operation control signal TRAS is generated at a predetermined logic level, the pulse generator  840  generates the pulse signal OVDRV_S in response to the operation control signal TRAS at the predetermined logic level, and the driving capability of the voltage generator  810  is increased by the voltage generator  850 , which receives the pulse signal OVDRV_S.  
         [0128]    The internal voltage generator  800  shown in FIG. 8 generates a short pulse signal OVDRV_N in response to the row active command RA when the RAS time is long (for example, in this case, when the operation control signal TRAS is at a low level), and increases the driving capability of the voltage generator  810  by a voltage, that is generated in the voltage generator  830 . When the RAS time is short (for example, in this case, when the operation control signal TRAS is at a high level), the pulse generator  840  generates the short pulse signal OVDRV_S by receiving the operation control signal TRAS having a high level from circuit  700 . Voltage generator  850  responds to OVDRV.S by further increasing the driving capability of the voltage generator  810 . The pulse signal OVDRV_N, which is generated when the pulse generator  820  responds to the row active command RA, and the pulse signal OVDRV_S, which is generated when the pulse generator  840  responds to the operation control signal TRAS, are shown in FIG. 9. In FIG. 9, the level of the internal voltage IV improves when the pulse signal is generated.  
         [0129]    [0129]FIG. 10 is a circuit diagram of a circuit for detecting a RC time using the circuit for AC-timing-parameter control circuit shown in FIG. 1.  
         [0130]    [0130]FIG. 11 illustrates a circuit for generating a control signal having information related to a RC time.  
         [0131]    [0131]FIG. 12 is a timing diagram illustrating the operation of the circuits shown in FIGS. 10 and 11.  
         [0132]    The circuit  900  for detecting a RC time shown in FIG. 10 is different from the circuit  300  for recognizing a cycle of a reference clock signal shown in FIG. 3 in that: e.g., a toggle flip-flop  910  generates an operation-determining signal OPDS, which is inverted at every rising edge of the row active command RA, a NOR gate instead of a NAND gate is used in one of two comparing portions.  
         [0133]    The operation of the circuit  900  for detecting a RC time will be described with reference to FIGS. 10, 11, and  12 .  
         [0134]    The RC time tRC means the time required for the row active command RA to be enabled again after the row active command RA is enabled and disabled.  
         [0135]    The circuit  900  for detecting a RC time shown in FIG. 10 includes two delay-time-defining portions  920  and  950 , two comparing portions  930  and  960 , and two controlling portions  940  and  970 , so as to detect the RC time tRC at every rising edge of the row active command RA.  
         [0136]    In order to detect the RC time tRC at every rising edge of the row active command RA, the toggle flip-flop  910  generates an operation-determining signal OPDS signal, that is inverted at every rising edge of the row active command RA.  
         [0137]    The operation-determining signal OPDS is applied to the delay-time-determining portion  920  at a rising edge of the operation-determining signal OPDS, and a first comparison pulse signal COMP 1  is generated in the comparing portion  930  to have a predetermined active wodth. Controlling portion  940  generates a first operation control signal OPCON 1 , which is latched by comparing the first comparison pulse signal COMP 1  with the operation-determining signal OPDS at the next falling edge of the operation-determining signal OPDS. Referring to FIG. 12, the active section of the operation-determining signal OPDS is shorter than that of the first comparison pulse signal COMP 1 , and in such a case, the first operation control signal OPCON 1  is generated at a high level.  
         [0138]    The operation-determining signal OPDS is applied to the delay-time-defining portion  950  at a falling edge of the operation-determining signal OPDS, and a second comparison pulse signal COMP 2  is generated in the comparing portion  960  to have a predetermined active section. A signal, which is latched by comparing the second comparison pulse signal COMP 2  with the operation-determining signal OPDS at the next rising edge of the operation-determining signal OPDS, is generated in the controlling portion  940  as a second operation control signal OPCON 2 . Referring to FIG. 12, the second comparison pulse signal COMP 2  is at a low level at the rising edge of the operation-determining signal OPDS, and in such a case, the second operation control signal OPCON 2  is generated at a low level.  
         [0139]    Likewise, the RC time tRC is recognized at every rising edge of the row active command RA, that is, at every rising edge and falling edge of the operation-determining signal OPDS, and thus the circuit  900  for detecting a RC time shown in FIG. 10 can recognize the consecutive RC time tRC.  
         [0140]    The circuit  980  shown in FIG. 11 alternately outputs the first operation control signal OPCON 1  and the second operation control signal OPCON 2  at every rising edge and falling edge of the operation-determining signal OPDS. That is, the first operation control signal OPCON 1  is output as a control signal TRC_S at the falling edge of the operation-determining signal OPDS, and the second operation control signal OPCON 2  is output as the control signal TRC_S at the rising edge of the operation-determining signal OPDS.  
         [0141]    The control signal TRC_S has information related to the RC time tRC in the previous step at every rising edge of the row active command RA, that is, information related to whether the RC time tRC is longer or shorter than a preset predetermined time, is generated by the operation.  
         [0142]    The control signal TRC_S may be used in an application circuit for controlling an internal operation of a semiconductor memory device.  
         [0143]    As described above, an AC-timing-parameter control circuit for a semiconductor memory device, and operating method thereof according to the present invention, can recognize a variation in an AC timing parameter of the semiconductor memory device and can control the operation of the semiconductor memory device suitable for the AC-timing parameter.  
         [0144]    While this invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.