Abstract:
In a signal processing apparatus, an analog signal inputted from, for example, a sensor is amplified by a amplifying circuit and is supplied to N comparing circuits (N is an integer equal to or more than 2). Each of the N comparing circuits is associated with a reference voltage and generates a comparison resultant signal based on the reference voltage in response to the amplified analog signal. N pulse generating circuits are provided for the N comparing circuits, respectively, and each of the N pulse generating circuits generates first and second pulse signals which indicate level transitions of the comparison resultant signal with respect to the corresponding reference voltage. A digital signal generating circuit composed of a flip-flop circuit generates a digital signal in response to the first and second pulse signals from each of the N pulse generating circuits.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a method and signal processing apparatus for generating a digital signal based on an analog signal which is supplied from an external device, and more particularly, to a method and signal processing apparatus for generating a digital signal based on an alternating current (AC) signal component contained in an analog signal. 
     2. Description of the Related Art 
     Conventionally, various sensors are used in various apparatuses. Generally, the sensor detects a predetermined a physical or chemical change of an object and converts this into an analog signal to outputs it. 
     On the other hand, the development of digital signal processing technique in recent years is remarkable. Because a digitized signal is suitable for processing by a computer, the digital signal processing technique tends to be adopted in a signal processing field, in order to realize an advanced process function. 
     To convert an analog signal obtained from a sensor into a digital signal, it is necessary to digitize the analog signal. As the apparatus for digitizing an analog signal from the sensor, a signal processing apparatus as shown in, for example, FIG. 1 is conventionally known. The signal processing apparatus is composed of an amplifying circuit 50 for amplifying an analog signal a from a sensor (not shown), a reference voltage generating circuit 51 for generating a reference voltage V ref , and a comparing circuit 52 for comparing an analog signal A from amplifying circuit 50 and the reference voltage V ref  from the reference voltage generating circuit 51. Each of the amplifying circuit 50 and the comparing circuit 52 is composed of an operational amplifier. Also, the reference voltage generating circuit 51 is a resistor division circuit which is composed of a resistor R10 and a resistor R11 which are provided between a power supply voltage V cc  and a ground voltage GND. The reference voltage V ref  is generated from the connection point between both the resistors. 
     In such a signal processing apparatus, the analog signal a from the sensor is supplied to one of terminals of the amplifying circuit 50 as a first stage. The other terminal of the amplifying circuit 50 is grounded. The analog signal A obtained by amplifying the analog signal a by the amplifying circuit 50 is supplied to one of input terminals of the comparing circuit 52. Also, the reference voltage V ref  generated by the reference voltage generating circuit 51 is supplied to the other input terminal of the comparing circuit 52. The comparing circuit 52 outputs a signal D of a high level (hereinafter, to be referred to as &#34;the H level&#34;), when the amplitude of the analog signal A is larger than the reference voltage V ref , and outputs the signal D of a low level (hereinafter, to be referred to as &#34;the L level&#34;), otherwise. By this, the analog signal a from the sensor is converted into the digital signal D, as shown in FIGS. 2A and 2B. 
     By the way, a DC component is generally contained in the analog signal a obtained from the sensor, in addition to an AC component. In the conventional signal processing apparatus, because the DC offset is not considered, there is a problem in that the above-mentioned conventional signal processing apparatus is inferior in point of the ability to detect a signal. For example, there is no problem if the amplitude of the AC component is sufficiently larger than the DC offset, like an analog signal a1 of FIG. 3. However, if the amplitude is smaller than the DC offset, like an analog signal a2, the analog signal a2 does not cross the reference voltage V ref . In this case, the change of the analog signal a2 can not be detected. 
     In order to solve a problem as described above, the amplitude of the AC component of the analog signal a obtained from the sensor should be made large. For this purpose, if the analog signal a obtained from the sensor is simply amplified by the amplifier, the amplitude of the analog signals a1 and a2 becomes large, as shown in FIG. 4. However, because the DC offset is also amplified when the analog signal is simply amplified, the amplified analog signal A2 does not still cross the reference voltage V ref . When a signal is actually amplified by the amplifier, a situation is more aggravated, because a DC offset of amplifier itself is also superposed on the amplified signal. 
     For this reason, conventionally, after a signal processing apparatus is manufactured, adjustment, i.e. trimming is performed in which an analog signal is actually inputted to the signal processing apparatus for measurement of a DC offset, and the reference voltage V ref  is set to an optimal value based on the measurement result. Thus, there is a problem in that the adjustment is very troublesome and high cost adjustment facilities are necessary. 
     In order to eliminate the problem caused by the DC offset, a signal processing apparatus as shown in, for example, FIG. 5 is developed. The signal processing apparatus is composed of an amplifying circuit 50 for amplifying an analog signal a from a sensor (not shown), an integrating circuit 53 for smoothing the output signal of the amplifying circuit 50, a buffer circuit 54 for outputting the output signal from the integrating circuit 53 as the reference voltage V ref , and a comparing circuit 52 for comparing an analog signal A from the amplifying circuit 50 and the reference voltage V ref  from the buffer circuit 54. Note that the same components as those shown in FIG. 1 are allocated with the same reference numerals. Each of the amplifying circuit 50, the buffer circuit 54, and the comparing circuit 52 is composed of an operational amplifier. Also, the integrating circuit 53 includes a CR integrating circuit which is composed of a resistor R12 and a capacitor C10. 
     In this signal processing apparatus, the analog signal a from the sensor is supplied to the amplifying circuit 50. Then, an analog signal A obtained by amplifying the analog signal a by the amplifying circuit 50 is supplied to one of input terminals of the comparing circuit 52 and the integrating circuits 53. The integrating circuit 53 integrates the analog signal A and supplies the integrating result to the buffer circuit 54. The output of the buffer circuit 54 is supplied to the other input terminal of the comparing circuit 52 as the reference voltage V ref . The operation of the comparing circuit 52 is the same as that of the above-mentioned comparing circuit 52 shown in FIG. 1. By this, the analog signal a from the sensor is converted into a digital signal D, as shown in FIGS. 6A and 6B. 
     According to this signal processing apparatus, since the reference voltage V ref  is generated from the AC component of the analog signal A to be compared, the analog signal A and the reference voltage V ref  can be compared irrespective of the DC offset which is contained in the analog signal A. In accordance with, the problems caused by the above-mentioned DC offset can be solved. 
     However, the capacity of the capacitor C10 used for the integrating circuit 53 must be made large such that the signal processing apparatus can function correctly even when the AC component of the analog signal A has a low frequency. For example, when a physical quantity of a rotating section in a car is detected by the sensor, the minimum frequency of the AC component of the analog signal which is obtained from the sensor becomes several Hz. In this case, because the capacity of the capacitor C10 of several μF and tens of μF is necessary, the cost has become high. Also, it is difficult to form a large capacity of capacitor in the integrated circuit. Therefore, it is difficult to manufacture the signal processing apparatus as the integrated circuit. 
     Further, in order to eliminate the problem caused by the above-mentioned DC offset, for example, the other signal processing apparatus as shown in FIG. 7 is developed. In the signal processing apparatus, a highpass filter 55 is inserted between the amplifying circuit 50 and the comparing circuits 52 to amplify an analog signal a from the sensor as shown in FIG. 1. Note that the same components as those shown in FIG. 1 are allocated with the same reference numerals. The highpass filter 55 takes out only the AC component contained in the analog signal A, and supplies only the taken AC component to the comparing circuit 52. 
     According to this signal processing apparatus, since the reference voltage V ref  is compared only with the AC component in the analog signal A, the problem caused by the above-mentioned DC offset is eliminated. However, the large capacity of capacitor is necessary for the capacitor C11 which is used for the highpass filter 55. Therefore, there is the same problem as in the signal processing apparatus as shown in FIG. 5. 
     SUMMARY OF THE INVENTION 
     A present invention is accomplished in the light of the above circumstances. Therefore, an object of the present invention is to provide a method of processing a signal and a signal processing apparatus for the same, in which a digital signal can be generated from an analog signal supplied from a sensor and so on without any adjustment after the manufacture. 
     Another object of the present invention is to provide a signal processing apparatus which can be manufactured with low cost and is suitable for an integrated circuit. 
     Still another object of the present invention is to provide a method of generating a digital signal from an analog signal without any influence of noise and a signal processing apparatus for the same. 
     In order to achieve an aspect of the present invention, a signal processing apparatus includes N comparing circuits (N is an integer equal to or more than 2) respectively associated with reference voltages, wherein each of the comprising circuits generates a comparison resultant signal based on the associated reference voltage in response to input of a first analog signal, N pulse generating circuits respectively provided for the N comparing circuits, wherein each of the N pulse generating circuits generates first and second pulse signals based on the corresponding comparison resultant signal supplied from the corresponding comparing circuit, the first and second pulse signals indicating signal level transitions of the corresponding comparison resultant signal with respect to the associated reference voltage, and a digital signal generating circuit for generating a digital signal in response to the first and second pulse signals of each of the N pulse generating circuits. The signal processing apparatus may further include an amplifying circuit for amplifying an inputted second analog signal to supply to the N comparing circuits as the first analog signal. 
     In this case, the second analog signal includes a DC offset, and a voltage difference Vd between adjacent two of the reference voltages associated with the N comparing circuits satisfies: 
     
         Vd≦αγ and Vd≧βγ/N 
    
     where α is an amplitude of a component of the second analog signal other than the DC off set, β is the DC offset of the second analog signal, γ is an amplification of the amplifying circuit. Each of the N comparing circuits may have a hysteresis characteristic. 
     Also, each of the N pulse generating circuits may include a prevention circuit section for preventing an erroneous operation due to a pulse-like noise. In this case, each of the N pulse generating circuits includes a first pulse generating circuit for generating the first pulse signal which indicates a first level transition of the corresponding comparison resultant signal with respect to the associated reference voltage into a first direction, and a second pulse generating circuit for generating the second pulse signal which indicates a second level transition of the corresponding comparison resultant signal with respect to the associated reference voltage into a second direction which is opposite to the first direction. Each of the first and second pulse generating circuits includes an integrating circuit. More particularly, the first pulse generating circuit generates the first pulse signal simultaneously with the first level transition of the corresponding comparison resultant signal into the first direction, and the second pulse generating circuit generates second pulse signal simultaneously with the second level transition of the corresponding comparison resultant signal into the second direction. The N comparing circuits, the N pulse generating circuits, the digital signal generating circuit, and the amplifying circuit are formed in a same semiconductor chip. 
     In order to achieve another aspect of the present invention, a method of generating a digital signal from an analog signal containing a DC offset, includes the steps of: 
     amplifying a first analog signal containing a DC offset to produce a second analog signal; 
     comparing the second analog signal with each of a plurality of reference voltages to generate a plurality of comparison resultant signals; 
     generating a first pulse signal in response to a first level transition of each of the plurality of comparison resultant signals from a first level region to a second level region; 
     generating a second pulse signal in response to a second level transition of each of the plurality of comparison resultant signals from the second level region to the first level region; and 
     generating a digital signal set in response to the plurality of first pulse signals and rest in response to the plurality of second pulse signals. 
     In order to achieve still another aspect of the present invention, a signal processing apparatus includes a reference voltage generating circuit for generating N reference voltages (N is an integer equal to or more than 2), N comparing circuits respectively provided for the N reference voltages, wherein each of the N comparing circuits compares a first analog signal with the corresponding reference voltage to output a comparison resultant signal in accordance with the comparing result, and the comparison resultant signal has a first level when an amplitude of the first analog signal is larger than the corresponding reference voltage, and a second level when the amplitude of the first analog signal is not larger than the corresponding reference voltage, and a digital signal generating section for generating a digital signal set when either of the N comparison resultant signals which are outputted from the N comparing circuits changes from the second level into the first level and reset when either of the N comparison resultant signals changes from the first level into the second level. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram illustrating the structure of a first conventional signal processing apparatus to generate a digital signal from an analog signal; 
     FIGS. 2A and 2B are timing charts to explain the operation of the first conventional signal processing apparatus; 
     FIG. 3 is a timing chart to explain a problem of the first conventional signal processing apparatus; 
     FIG. 4 is a timing chart to explain the problem of the first conventional signal processing apparatus; 
     FIG. 5 is a circuit diagram illustrating the structure of a second conventional signal processing apparatus to generate a digital signal from an analog signal; 
     FIGS. 6A and 6B are timing charts to explain the operation of the second conventional signal processing apparatus; 
     FIG. 7 is a circuit diagram illustrating the structure of a third conventional signal processing apparatus to generate a digital signal from an analog signal; 
     FIG. 8 is a block diagram illustrating the structure of the signal processing apparatus according to an embodiment of the present invention; 
     FIG. 9 is a circuit diagram illustrating a structure example of a rising edge detecting circuit shown in FIG. 8; 
     FIG. 10 is a circuit diagram illustrating a structure example of a falling edge detecting circuit shown in FIG. 8; 
     FIG. 11 is a circuit diagram illustrating a structure example of a flip to flop circuit shown in FIG. 8; 
     FIGS. 12A to 12F are timing charts to explain the operations of an amplifying circuit and comparing circuit in the signal processing apparatus according to the embodiment of the present invention; 
     FIGS. 13A to 13D are timing charts to explain the operation of the rising edge detecting circuit in the signal processing apparatus according to the embodiment of the present invention; 
     FIGS. 14A to 14D are timing charts to explain the operation of the falling edge detecting circuit in the signal processing apparatus according to the embodiment of the present invention; 
     FIGS. 15A to 15D are timing charts to explain the operations of the rising edge detecting circuit, falling edge detecting circuit and flip to flop circuit in the signal processing apparatus according to the embodiment of the present invention; 
     FIGS. 16A to 16F are timing charts to explain the operations of the amplifying circuit and comparing circuit in the signal processing apparatus according to the embodiment of the present invention; and 
     FIGS. 17A to 17G are timing charts to explain the operations of the rising edge detecting circuit, falling edge detecting circuit and flip to flop circuit in the signal processing apparatus according to the embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A signal processing apparatus of the present invention will be described below in detail with reference to the accompanying drawings. 
     FIG. 8 is a block diagram illustrating the structure of the signal processing apparatus according to an embodiment of the present invention. The signal processing apparatus is composed of an amplifying circuit 10, reference voltage generating circuit 11 1  to 11 5 , comparing circuit 12 1  to 12 5 , rising edge detecting circuit 13 1a  to 13 5a , falling edge detecting circuit 13 1b  to 13 5b , and a flip-flop circuit 14. In the signal processing apparatus in this embodiment, five kinds of reference voltage V ref  is used. These are +400 mV, +200 mV, 0 V, -200 mV and -400 mV. In the following description, when the whole of circuit sections are referred to, a representative circuit section will be described with a suffix of &#34;i&#34;. 
     The reference voltage generating circuit 11 1  to 11 5  generates the reference voltage of +400 mV, +200 mV, 0 V, -200 mV and -400 mV as the reference voltages V ref1 , V ref2 , V ref3 , V ref4 , V ref5 , respectively. The reference voltage generating circuit 11 1  is possible to be constructed of the resistor dividing circuit as shown in, for example, FIG. 1. The resistor dividing circuit is composed of resistors which are connected between a positive/negative power supply voltage and a ground potential or the positive and negative power supply voltages, as described in the conventional technique. In the embodiment, the positive and negative power supply voltages are used for the reference voltage generating circuit 11 i . The reference voltage V refi  from the reference voltage generating circuit 11 i  is supplied to one of input terminals of the comparing circuit 12 i . 
     An analog signal a from an external device, e.g., a sensor element is supplied to one of input terminals of the amplifying circuit 10. The other input terminal of the amplifying circuit is connected to a predetermined voltage, e.g., the ground potential. The amplifying circuit 10 is composed of an operational amplifier. The amplifying circuit 10 is not limited to the operational amplifier. For example, the amplifying circuit made from transistors and so on, and the other well-known amplifying circuit can be used. An analog signal A is obtained as a result of amplification by the amplifying circuit 10 and is supplied to &#34;+&#34; input terminal of the comparing circuit 12 i . 
     The comparing circuit 12 i  compares the analog signal A supplied from the amplifying circuit 10 and the reference voltage V refi  supplied from the reference voltage generating circuit 11 i  and outputs the comparing result. Each of the comparing circuits 12 1  to 12 5  is composed of an operational amplifier. Each of the comparing circuit 12 1  to 12 5  is not limited to the operational amplifier. For example, the comparing circuit may be constructed by a transistor circuit and so on, or may be another well known comparing circuit. The comparing circuit 12 i  compares the analog signal A supplied from the amplifying circuit 10 and the reference voltage V refi  supplied from the reference voltage generating circuit 11 i . The comparing circuit 12 i  outputs the comparison resultant signal C i  of the H level, when the analog signal A is larger than the reference voltage V refi . The comparing circuit 12 i  outputs the comparison resultant signal C i  of the L level, when the analog signal A is equal to or smaller than the reference voltage V refi . The comparison resultant signal C i  outputted from the comparing circuit 12 i  is supplied to the rising edge detecting circuit 13 ia  and falling edge detecting circuit 13 ib . 
     The rising edge detecting circuit 13 ia  detects the rising edge of the comparison resultant signal C i  from the comparing circuit 12 i . A detection result is outputted as a pulse signal. The detailed structure of the rising edge detecting circuit 13 ia  is shown in FIG. 9. The rising edge detecting circuit 13 ia  is composed of an integrating circuit 20, an inverter 21 and a 2-input NAND gate 22. The integrating circuit 20 is compose of a resistor R1 and a capacitor C1, and functions as a delay circuit. Also, the integrating circuit functions as the circuit to prevent an erroneous operation due to pulse-like noise. 
     A comparison resultant signal C i  from the comparing circuit 12 i  is supplied to one of the input terminals of the NAND gate 22 and the integrating circuit 20. A signal E i  delayed by the integrating circuit 20 is inverted by the inverter 21 and is supplied to the other input terminal of the NAND gate 22 as a signal F i . Then, the logic product of signal C i  and the signal F i  is calculated by the NAND gate 22 and then is inverted. The inverted logic product is outputted as a rising detection signal SS i . By this, when the comparison resultant signal C i  from the comparing circuit 12 i  changes from the L level to the H level, the pulse signal SS i  having a width of the delay time dependant on the integrating circuit 20 is generated and is outputted. The output signals SS 1  to SS 5  from the rising edge detecting circuits 13 1a  to 13 5a  are supplied to set terminals S 1  to S 5  of the flip-flop circuit 14, respectively. The operation of the rising edge detecting circuit 13 ia  will be described later in detail with reference to the timing charts of FIGS. 13A to 13D. 
     The falling edge detecting circuit 13 ib  detects the falling edge of the comparison resultant signal C i  from the comparing circuit 12 i . A detection result is outputted as a pulse signal SR i . The detailed structure of the falling edge detecting circuit 13 ib  is shown in FIG. 10. The falling edge detecting circuit 13 ib  is composed of an inverter 30, an integrating circuit 31, and a 2-input NAND gate 32. The integrating circuit 31 is composed of a resistor R2 and a capacitor C2, and has a signal delay function and a function to prevent an erroneous operation due to pulse-like noise. The comparison resultant signal C i  from the comparing circuit 12, is inverted by the inverter 30 to produce a signal G i  which is supplied to one of the input terminals of the NAND gate 32. Also, the comparison resultant signal C i  is delayed by the integrating circuit 31 and is supplied to the other input terminal of the NAND gate 32 as a signal H i . Then, the logic product of the signal G i  and the signal H i  is calculated by the NAND gate 22 and then is inverted. The inverted logic product is outputted as a falling edge detection signal SR i . By this, when the comparison resultant signal C i  from the comparing circuit 12 i  changes from the H level to the L level, the pulse signal SR i  having a width of for the delay time is generated and outputted depending on the integrating circuit 31. The output signals SR 1  to SR 5  from the falling edge detecting circuits 13 1b  to 13 5b  are supplied to the reset terminals R 1  to R 5  of the flip-flop circuit 14, respectively. The operation of the falling edge detecting circuit 13 ib  will be described in detail with reference to the timing charts of FIGS. 14A to 14D. 
     It is sufficient that the integrating circuits 20 and 31 in the above rising edge detecting circuit 13 ia  and falling edge detecting circuit 13 ib  can delay the inputted comparison resultant signal C i  by the pulse width necessary to set or reset the flip-flop circuit 14. Therefore, the capacity of the capacitors C 1  and C 2  in the integrating circuit 20 and 31 is sufficient to be about 0.1. In accordance with, because such a capacitor can be formed in the integrated circuit, the signal processing apparatus can be easily manufactured as an integrated circuit on a same semiconductor chip. Also, the integrating circuit 20 and 31 may be substituted by another delay means. For example, a gating circuit of one stage to a few stages can be used to realize the delay function of the integrating circuit 20 and 31. In this case, the delay time is determined by the signal transfer time of the gating circuit. 
     The flip-flop circuit 14 is set when the set signal SS i  of the L level is inputted to any of the set terminals S 1  to S 5 , and outputs the digital signal R of the H level. On the other hand, the flip-flop is reset when the reset signal SR i  of the L level is inputted to any one of the reset terminals R 1  to R 5 , and outputs the digital signal R of the L level. The detail of the flip-flop circuit 14 is shown in FIG. 11. The flip-flop circuit 14 is composed of 6-input NAND gates 40 and 41 to form a 5-input SR type of flip-flop. The digital signal R is outputted from the flip-flop circuit 14 to the outside. 
     Next, the operation of the signal processing apparatus having the above-mentioned structure will be described with reference to the timing charts shown in FIGS. 12A to 17G. 
     Now, it is supposed that the peak-to-peak amplitude of an AC component of an analog signal supplied from an external device, e.g., a sensor element is 10 mV P-P , a DC offset is 13 mV, and the amplification of the amplifying circuit 10 is 20 times. 
     The amplifying circuit 10 amplifies the inputted analog signal a, and outputs the analog signal A having the AC component 200 mV P-P  and the DC offset of 260 mV, as shown in FIG. 12A. Accordingly, the analog signal A crosses only the reference voltage of +200 mV, as shown in FIG. 12A. Accordingly, the comparing circuit 12 i  inputs the analog signal A amplified by the amplifying circuit 10 and always outputs the comparison resultant signal C 1  of the L level, because the analog signal A is smaller than the reference voltage of +400 mV, as shown in FIG. 12B. The comparing circuit 12 2  outputs the comparison resultant signal C 2  of the H level when the analog signal A is larger than the reference voltage of +200 mV, and outputs the comparison resultant signal C 2  of the L level when the analog signal A is smaller than the reference voltage of +200 mV, as shown in FIG. 12C. The comparing circuits 12 3  to 12 5  always outputs the comparison resultant signals C 3 , C 4 , C 5  of the H level, because the analog signal A is larger than either of the reference voltages of 0 V, -200 mV and -400 mV, as shown in FIGS. 12D to 12F. 
     The operation of the rising edge detecting circuit 13 2a  which inputs the comparison resultant signal C 2  from the comparing circuit 12 2  is shown in FIGS. 13A to 13D. The comparison resultant signal C 2  shown in FIG. 13A is supplied to one of the input terminals of the NAND gate 22 and is supplied to the integrating circuit 20. The integrating circuit 20 makes the change of the rising and falling edges of the inputted comparison resultant signal C 2  gentle, as shown in FIG. 13B. The output E 2  of the integrating circuit 20 is inverted by the inverter 21 and is supplied to the other input terminal of the NAND gate as the signal F 2 , as shown in FIG. 13C. The NAND gate 22 carries out an operation of the logic product of the inputted comparison resultant signal C 2  and the signal F 2  from the inverter 21 and inverts to outputs the calculation result as the rising edge detection signal SS 2 , as shown in FIG. 13D. Because the logic product has a meaning only for the time delayed by the integrating circuit 20, the NAND gate 22 outputs a pulse signal SS 2  of the L level only for a predetermined delay time from the rising edge of comparison resultant signal C 2 . 
     Also, the operation of 13 2b  of the falling edge detecting circuits which input the comparison resultant signal C 2  from the comparing circuit 12 2  is shown FIGS. 14A to 14D. The inputted comparison resultant signal C 2  is inverted by the inverter 21 and is supplied to one of the input terminals of the NAND gate 22 as the signal G 2 , as shown in FIG. 14B. Also, the comparison resultant signal C 2  is supplied to the integrating circuit 20. The integrating circuit 20 makes the change of the rising and falling edges of the inputted comparison resultant signal C 2  gentle, as shown in FIG. 14C, and supplies to the other input terminal at the NAND gate as the signal H 2 . The NAND gate 22 carries out an operation of the logic product in the output signal H 2  of the integrating circuit 31 and the output signal G 2  from the inverter 21, and inverts the calculation result to output as the falling edge detection signal SR 2 , as shown in FIG. 14D. Because a logic product can be taken only for the time delayed by the integrating circuit 20, the NAND gate 22 outputs the pulse signal SR 2  of the L level only for a predetermined delayed time from the falling edge of the comparison resultant signal C 2 . 
     In this case, since the comparison resultant signals C 1 , C 3 , C 4  and C 5  which are respectively inputted to the rising edge detecting circuits 13 1a , 13 3a , 13 4a  and 13 5a  do not change, the signals SS 1 , SS 3 , SS 4 , SS 5  of the H level are always outputted from these circuits. Similarly, since the comparison resultant signals C 1 , C 3 , C 4  and C 5  which are respectively inputted to the falling edge detecting circuits 13 1b , 13 3b , 13 4b  and 13 5b  do not change too, the signals SR 1 , SR 3 , SR 4  and SR 5  of the H level are always output from these circuits. 
     Since the signal SS 2  from the rising edge detecting circuits 13 2a  is supplied to the set terminal S2 of the flip-flop circuit 14 and the signal SR 2  from the falling edge detecting circuit 13 2b  is supplied to the reset terminal R 2  of the flip-flop circuit 14, the flip-flop circuit 14 is set and reset in accordance with the change of the signal C 2  outputted from the comparing circuit 12 2 , as shown in FIGS. 15A to 15D. The digital signal R is outputted from the flip-flop circuit 14 to an external device. 
     Next, the case where the AC component of the analog signal a from the external device, e.g., the sensor element is 15 mV P-P , the DC offset is 14 mV will be described below. In this case, it is supposed that the reference voltages generated by the reference voltage generating circuit 11 1  to 11 5  and the amplification of the amplifying circuit 10 are the same as the above example. 
     The amplifying circuit 10 amplifies the inputted analog signal a, and outputs the analog signal A having the peak to peak amplitude of 300 mV P-P  in the AC component and the DC offset of 280 mV. Accordingly, the analog signal A crosses both of the reference voltages of +200 mV and +400 mV, as shown in FIG. 16A. In accordance with, the comparing circuit 12 1  inputs the analog signal A from the amplifying circuit 10 and outputs the comparison resultant signal C 1  of the H level for the time interval when the analog signal A is larger than the reference voltage of +400 mV, and of the L level, otherwise, as shown in FIG. 16B. Similarly, the comparing circuit 12 2  outputs the comparison resultant signal C 2  of the H level for the time interval when the analog signal A is larger than the reference voltage of +200 mV, and of the L level for the other time interval, as shown in FIG. 16C. The comparing circuits 12 3  to 12 5  always outputs the comparison resultant signals C 3 , C 4  and C 5  of the H level, because the analog signal A is larger than either of the reference voltages of 0 V, -200 mV and -400 mV. 
     The rising edge detecting circuits 13 1a  inputs the comparison resultant signal C 1  from the comparing circuit 12 1 , and outputs the pulse signal SS 1  of the L level only for a predetermined time interval from the rising edge of the inputted comparison resultant signal C 1 , as shown in FIG. 17C. Similarly, the rising edge detecting circuit 13 2a  inputs the comparison resultant signal C 2  from the comparing circuit 12 2  and outputs the pulse signal SS 2  of the L level only for a predetermined time interval from the rising edge of the inputted comparison resultant signal C 2 , as shown in FIG. 17D. 
     Also, the falling edge detecting circuit 13 1b  inputs the comparison resultant signal C 1  from the comparing circuit 12 1  and outputs the pulse signal SR 1  of the L level only for a predetermined delay time from the falling edge of the inputted comparison resultant signal C 1 , as shown in FIG. 17E. Similarly, the falling edge detecting circuit 13 2b  inputs the comparison resultant signal C 2  from the comparing circuit 12 2  of the L level only for a predetermined delay time from the falling edge of the inputted comparison resultant signal C 2 , and outputs the pulse signal SR 2 , as shown in FIG. 17F. In this case, because the comparison resultant signals C 3 , C 4  and C 5  which are respectively inputted to the rising edge detecting circuits 13 3a , 13 4a  and 13 5a  do not change in level, the signals SS 3a , SS 4a  and SS 5a  of the H level are always outputted from these circuit. Similarly, because the comparison resultant signals C 3 , C 4  and C 5  which are respectively inputted to the falling edge detecting circuits 13 3b , 13 4b  and 13 5b  do not change, the signals SR 3 , SR 4  and SR 5  of the H level are always outputted from these circuits. 
     The signals SS 1  and SS 2  are outputted from the rising edge detecting circuit 13 1a  and 13 2a  to the set terminals S 1  and S 2  of the flip-flop circuit 14, and the signal SR 1  and SR 2  are outputted from the falling edge detecting circuits 13 1b  and 13 2b  to the reset terminals R 1  and R 2  of the flip-flop circuit 14, respectively. Therefore, the flip-flop circuit 14 changes the state, as shown in FIG. 17G. The digital signal R is output from the flip-flop circuit 14 to the external device. 
     The above-mentioned description was given to the examples when the AC component of the analog signal A crosses two reference voltages. However, when the AC component of the analog signal A crosses equal to or more than three reference voltages, too, the desired digital signal R can be obtained in the same manner. 
     Note that the comparing circuit 12 i  in the above embodiments may be constructed to positively feed back the output signal. According to such a structure, the comparing circuit 12 i  has a hysteresis and is superior in noise endurance. 
     Also, in the above embodiments, it is supposed that the amplification of the amplifying circuit 10 is 20 times, the amplitude of the AC component of the inputted analog signal is 10 mV P-P , the DC offset is 50 mV in maximum, the potential difference between the adjacent reference voltages is 200 mV, and the number of reference voltages is 5. However, each of these parameters can be arbitrarily determined. That is, when the amplitude of the AC component of the inputted analog signal is α, the DC offset is β in maximum, and the amplification of the amplifying circuit 10 is γ, each of the above parameters can be determined to meet the following condition: 
     (the potential difference between adjacent reference voltages)≦α×γ, and 
     (the potential difference between adjacent reference voltages)×(the number of reference voltages)≧β×γ. 
     If the above condition is satisfied, then each of the operational amplifiers used as the amplifying circuit 10 and the comparing circuits 12 1  to 12 5  does not necessarily have high precision. 
     As described above in detail, according to the present invention, the signal processing apparatus can be provided without needing any adjustment and with low cost. Moreover, the signal processing apparatus is suitable for an integrated circuit.