Abstract:
A current controlled ring oscillator use a plurality of serial amplifier stages with the output of the last stage connected to the input of the first stage. The ring oscillator maintains a linear output frequency over the control range by using a control circuit to compensate for variation in gate-source voltage of output clamping transistors. Moreover, switching nonlinearities can be removed by increasing the minimum value and decreasing the maximum value of the output waveform of each amplifier stage so as to compensate for time lost during the transition of the deadzone.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates in general to oscillators and, more particularly, to a current controlled ring oscillator having a linear output frequency over the control range. 
     Current controlled ring oscillators are commonly used in electronic circuit design, for example in phased lock loops, for providing an adjustable output frequency operating in the range of say 150 megahertz (Mhz). A common design for ring oscillators uses an odd number of serially connected differential amplifier stages with the differential outputs of one stage connected (+/+ and -/-) to the differential inputs of a subsequent stage. The differential outputs of the final stage are crossed-coupled (+/- and -/+) back to the inputs of the first stage. Thus, a three stage ring oscillator would have 60° of phase shift per amplifier stage followed by 180° due to the cross coupling between the output of the final stage back to the input of the first stage for providing 360° of total phase shift to cause the circuit to oscillate. 
     To adjust the output frequency, the ring oscillator often utilizes a current control feature in the amplifier stages. More current increases the frequency of the amplifier by charging internal capacitive nodes faster and increasing the transition rate of the amplifier stage. The higher the control current, the faster each amplifier stage transitions and the higher the output frequency of the ring oscillator. 
     Maintaining a linear output frequency over the current control range is important for accuracy and stability in applications such as phase lock loops. Unfortunately, conventional ring oscillators typically exhibit poor linearity in response to the control current. The current controlled gain of each amplifier stage, defined as the rate of change in frequency with respect to control current (df/di), can vary by as much as 60% over the control range. Ideally the rate of change in output frequency should remain constant over the control current range. Any non-linearity in the output frequency of the ring oscillator degrades the phase lock loop system performance. 
     Hence, a need exists for an improved current controlled ring oscillator with a linear output frequency as a function of control current. 
     SUMMARY OF THE INVENTION 
     Briefly stated, the invention comprises an oscillator circuit including a plurality of differential amplifier stages serially coupled output to input with a differential output of a last differential amplifier stage cross-coupled to a differential input of a first differential amplifier stage, and a control circuit having first and second outputs coupled to said plurality of differential amplifier stages for adjusting an output frequency of the oscillator circuit while maintaining linear operation of said output frequency over a control range. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a simplified block diagram illustrating a current controlled ring oscillator; 
     FIG. 2 is a schematic diagram illustrating an amplifier of FIG. 1 with control circuit; and 
     FIGS. 3-4 are waveform plots useful in the explanation of the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 1, a current controlled ring oscillator circuit 10 is shown suitable for manufacturing as an integrated circuit using conventional integrated circuit processes. Differential amplifiers 12, 14 and 16 are serially coupled output to input with the differential outputs of amplifier 16 cross-coupled to the differential inputs of amplifier 12. Amplifiers 12, 14 and 16 each produce 60° of phase shift which, in combination with the 180° of phase shift achieved by crossing the outputs of amplifier 16 back to the inputs of amplifier 12, produces a full 360° phase shift causing circuit 10 to oscillate. Control circuit 18 provides current control to amplifiers 12-16 for adjusting the gain and output frequency of ring oscillator circuit 10. By properly controlling the gain of amplifiers 12-16, the rate of frequency change of the differential output oscillator signal OSC OUT remains linear over the control range. The differential oscillator signal OSC OUT may be taken at nodes 20 and 22. 
     Further detail of amplifier 12 is shown in FIG. 2 where nodes 20 and 22 provide a differential input voltage V IN  at the gates of transistors 24 and 26. For amplifier 12, the differential input signal V IN  is the oscillator signal OSC OUT. The drains of transistors 24 and 26 are coupled to the drains of transistors 30 and 32, respectively, while the sources of transistors 30 and 32 are coupled to power supply conductor 34 operating at a positive power supply potential such a V DD  (5.0 volts). The sources of transistors 24 and 26 are coupled together to the drain of current source transistor 36 having a source coupled to power supply conductor 40 operating at ground potential. The drain of transistor 24 is also coupled through capacitor 42 to power supply conductor 40, and to the sources of transistors 44 and 46 at node 48. The drains of transistors 44 and 46 are coupled to power supply conductors 40 and 34, respectively. 
     In a similar manner, the drain of transistor 26 is coupled through capacitor 50 to power supply conductor 40, and to the sources of transistors 52 and 54 at node 58. The drains of transistors 52 and 54 are coupled to power supply conductors 40 and 34, respectively. Nodes 48 and 58 provide the differential outputs of amplifier 12 coupled to the differential inputs of amplifier 14. Amplifiers 14 and 16 follow a similar construction as described above for amplifier 12. 
     As part of the present invention, control circuit 18 provides control signals to amplifiers 12, 14 and 16. Differential amplifier 62 receives reference potential V REF1  at its non-inverting input. The output of amplifier 62 is coupled to the gates of transistors 46, 54 and 64 at node 66. Transistor 64 also includes a drain coupled to power supply conductor 34, and a source coupled to the inverting input of amplifier 62 and to the drain of transistor 70. The gates of transistors 36 and 70 receive control signal V CNTL1  applied at input 72. The drain of transistor 70 is coupled to power supply conductor 40. Control circuit 18 also includes differential amplifier 76 receiving reference potential V REF2  at its non-inverting input. The output of amplifier 76 is coupled to the gates of transistors 44, 52 and 78 at node 80. The drain of transistor 78 is coupled to power supply conductor 40 while its source is coupled to the inverting input of amplifier 76 and to the source of transistor 84. The gates of transistors 30, 32 and 84 receive control signal V CNTL2  applied at input 88. The drain of transistor 84 is coupled to power supply conductor 34. Transistors 70 and 84 operate as current source in response to control signals V CNTL1  and V CNTL2 , respectively. 
     The operation of oscillator circuit 10 proceeds as follows. Transistors 24 and 26 of amplifier 12 form a differential pair operating in response to the differential input signal V IN  from nodes 20-22. The gain of amplifier 12, and accordingly the output frequency of the differential oscillator signal OSC OUT, is controlled by control signals V CNTL1  and V CNTL2  applied at the gates of transistor 36 and transistors 30-32, respectively. Control signal V CNTL2  sets the current flow through transistors 30-32 (I 30  =I 32 ), while control signal V CNTL1  biases current source transistor 36 to conduct current I 36  =I 30  +I 32 . Larger control signals V CNTL1  and V CNTL2  increase currents I 30 , I 32 , and I 36  thereby charging and discharging nodes 48-50 at a faster rate with more gain in amplifiers 12-16 which increases the transitions times and output frequency of oscillator 10. 
     When the voltage at node 20 is less than the voltage at node 22, transistor 24 is off and capacitor 42 charges with current I 30  from transistor 30. Ideally, the voltage at node 48 increases with the rate dV 48  /dt=I 30  /C 42 , where C 42  is the value of capacitor 42. As capacitor 42 charges, transistor 44 begins to sink current I 30  to limit the maximum voltage at node 48 to V 48MAX  =V 80  +V GS44 , where V 80  is the voltage at node 80 and V GS44  is the gate-source voltage of transistor 44. The higher voltage at node 22 turns on transistor 26 which sinks current I 36 . Current I 32  provides half of the current sunk by transistors 26 and 36 while the remainder is sunk from capacitor 50. Therefore, the voltage at node 58 decreases at a rate dV 58  /dt=-I 32  /C 50 , where C 50  is the value of capacitor 50. As capacitor 50 discharges, transistor 54 supplies a clamping current to limit the minimum voltage at node 58 to V 58MIN  =V 66  -V GS54 , where V 66  is the voltage at node 66 and V GS54  is the gate-source voltage of transistor 54. 
     Conversely, when the voltage at node 20 is greater than the voltage at node 22, transistor 26 is off and capacitor 50 charges with current I 32  from transistor 32. The voltage at node 58 increases at a rate dV 58  /dt=I 32  /C 50 . As capacitor 50 charges, transistor 52 begins to sink current I 32  to limit the maximum voltage at node 58 to V 58MAX  =V 80  +V GS52 , where V GS52  is the gate-source voltage of transistor 52. The higher voltage at node 20 turns on transistor 24 which conducts current I 36 . Current I 30  and the discharge of capacitor 50 provide current for transistors 24 and 36. The voltage at node 48 decreases with the rate dV 48  /dt=-I 30  /C 42 . As capacitor 42 discharges, transistor 46 supplies a clamping current to limit the minimum voltage at node 48 to V 48MIN  =V 66  -V GS46 , where V GS46  is the gate-source voltage of transistor 46. 
     The output waveform of amplifier 12 is shown in FIG. 3 as the difference between the voltages at nodes 48 and 58, V 48  -V 58 . Clamping transistors 46 and 54 limit the minimum voltages at nodes 48 and 58 to V 66  -V GS46  and V 66  -V GS54 , respectively. Likewise, clamping transistors 44 and 52 limit the maximum voltages at nodes 48 and 58 to V 80  +V GS44  and V 80  +V GS52 , respectively. When transistor 26 is conducting, V MAX  =V 48MAX  -V 58MIN , and when transistor 24 is conducting, V MIN  =V 48MIN  -V 58MAX , see FlG. 3. 
     The gain of amplifier 12 may be expressed as: ##EQU1## where F is frequency of the differential signal across nodes 48 and 58, I may be either currents I 30  or I 32 , A is a constant, C is the value of capacitor 42 or 50, V MAX  is the maximum differential voltage across nodes 48 and 58, and V MIN  is minimum differential voltage across nodes 48 and 58. 
     Amplifier 12 has two inherent sources of non-linear operation. First, when the output frequency changes with the control currents I 30 , I 32 , and I 36  via control signals V CNTL1  and V CNTL2 , the clamping currents conducted by transistors 44, 46, 52 and 54 also change proportionally which increases or decreases their gate-source voltages. Variation in V GS  of transistors 44, 46, 52 and 54 due to control current changes the gain by equation (1) which adversely effects the linearity of the output frequency of amplifier 12. 
     The gate-source voltage of an MOS transistor is given as V GS  =V T  +V SAT  (I), where V T  is the threshold voltage and V SAT  (I) is the additional voltage needed to conduct current I. As part of the present invention, control circuit 18 provides control signals at nodes 66 add 80 for transistors 44, 46, 52 and 54 to compensate for the non-linear gain changes by maintaining V MAX  and V MIN  constant as per equation (1). 
     Transistor 70 operating in response to control signal V CNTL1  conducts a current through transistor 64 proportional to current I 30  or I 32 . Therefore, the gate-source voltage of transistor 64 (V GS64 ) is also proportional to the gate-source voltage of transistors 46 and 54 when the latter transistors clamp. Likewise, transistor 84 operating in response to control signal V CNTL2  conducts a current through transistor 78 equal to current I 30  or I 32 . The gate-source voltage of transistor 78 is thus maintained the same as the gate-source voltage of transistors 44 and 52 when the latter transistors clamp. 
     The following values of V 66  and V 80  keep V MAX  and V MIN  constant: 
     
         V.sub.66 =V.sub.REF1 +V.sub.T +V.sub.SAT (I.sub.54)=V.sub.REF1 +V.sub.T +V.sub.SAT (B*I.sub.32)                                   (2) 
    
     
         V.sub.80 =V.sub.REF2 -V.sub.T -V.sub.SAT (I.sub.52)=V.sub.REF2 -V.sub.T -V.sub.SAT (B*I.sub.32)                                   (3) 
    
     where B=proportionality constant less than unity between currents I 32  and I 54 . 
     For example, assume control signals V CNTL1  and V CNTL2  are increased for a higher output frequency of oscillator 10. The gate-source voltages of transistors 44, 46, 52 and 54 increase because each must supply a greater clamping current for the larger current I 36 . The currents through transistors 70 and 84 increase by the same control signals V CNTL1  and V CNTL2  such that transistors 64 and 78 develop similar gate-source voltage as transistors 44 and 46, and transistors 52 and 54, respectively. Differential amplifier 62 senses the increase in voltage at its inverting input and increases its output voltage accordingly. The voltage V 66  increases to compensate for the larger gate-source voltages of transistors 46 and 54. Likewise, differential amplifier 76 senses an increase in voltage at its inverting input and decreases its output voltage accordingly. The voltage V 80  decreases to compensate for the larger gate-source voltages of transistors 44 and 52. Thus, by controlling V 66  and V 80  at the proper levels, V MAX  and V MIN  are held at constant values over the range of gain control currents I 30 , I 32  and I 36  to maintain linear operation for the output frequency of amplifier 12. 
     A second source of non-linearity operation occurs during the short switching time when transistors 24 and 26 both conduct simultaneously causing small currents to flow through capacitors 42 and 50. FIG. 4 represents the current flow into capacitors 42 or 50 as function of the differential input voltage V IN . However, the desired current values of +I/-I cannot be reached for small values of V IN . Since the voltage across a capacitor is determined by integrating the capacitive load current, the same charging/discharging times for capacitors 42 and 50 may be achieved by currents following the dashed line in FIG. 4, given the same areas under solid and dashed lines. This simplified model allows analysis of the circuit in terms of a hypothetical `dead zone` during which no current is delivered to the load, and the remaining time, when capacitors 42 and 50 are charged/discharged with +I/-I. 
     The dead zone is proportional to the input voltage overdrive needed to completely switch the differential transistor pair 24-26. The overdrive voltage depends upon the control current expressed as V DEAD  =K*Vsat(I 36 ), where K is constant, and Vsat(I 36 ) is excess voltage of transistors 24-26 while conducting current I 36 . The dead zone time can be compensated for by increasing V 48MIN  and V 58MIN  by V DEAD  which is a function of control current I 36 . 
     To achieve the V DEAD  offset for V 48MIN  and V 58MIN , the size of transistor 70 is increased such that the same magnitude of control voltage V CNTL1  causes transistor 70 to conduct proportionally more current than transistors 30-32 by a predetermined factor X. Accordingly, V GS64  is proportionally greater than V GS46  and V GS54 . Differential amplifier 62 drives the gate of transistor 64 higher to maintain the voltage at the source of transistor 64 substantially equal to V REF1 . Thus, V 66  increases by the change in V GS64 , whereby: ##EQU2## 
     The previous discussion where V GS64  is made proportional to V GS46  and V GS54  is now more completely understood in that the minimum voltage at nodes 48 and 58 with the V DEAD  offset (V 48MIN  +, V 58MIN  +) increases by the difference of V GS64  -V GS46  and V GS64  -V GS54 , respectively, due to the difference in device size between transistor 70 and transistors 30-32. The predetermined factor X by which the size of transistor 70 is increased is chosen such that V GS64  -V GS46  =K*V SAT  (I 36 )=V DEAD . V 48MAX  and V 58MAX  as derived from V 80  remain unchanged. Accordingly as shown in FIG. 3: ##EQU3## 
     To further illustrate how increasing the minimum amplitude and decreasing the maximum amplitude of the output waveform improves linearity, consider the following equations where the frequency of the oscillator signal OSC OUT is given as: ##EQU4## where ΔV=V MAX  +-V MIN  +. The ratio I/C represents the slope of the output waveform (T=1/ƒ=ΔVC/I). The factor of six follows from the two passes through the three amplifier stages necessary for one complete cycle of oscillator circuit 10. Recall that V DEAD  is a function of control current I 36 . Thus, the goal is to eliminate V DEAD  from equation (8) to cancel the non-linear effect of control current and maintain the output frequency linear over the control range. ##EQU5## 
     Taking the derivation of equation (10) yields equation (1), where A=1/3. Hence, the ultimate effect is to eliminate the non-linearities introduced by switching overlap of transistors 24-26 during transitions by increasing the V MIN  level and reducing the V MAX  level. Each amplifier stage receives an input waveform sufficiently offset to compensate for time lost during the transition of the deadzone. 
     While specific embodiments of the present invention have been shown and described, further modifications and improvements will occur to those skilled in the art. It is understood that the invention is not limited to the particular forms shown and it is intended for the appended claims to cover all modifications which do not depart from the spirit and scope of this invention.