Abstract:
An exemplary method for fabricating a polysilicon layer ( 208 ) includes the following steps. A substrate ( 200 ) is provided, and a first amorphous silicon layer ( 203 ) is formed over the substrate. Portions of the first amorphous silicon layer are removed through a photolithograph process to form a plurality of crystallization seeds ( 205 ). A second amorphous silicon layer ( 206 ) is formed over the substrate and the crystallization seeds. A laser annealing process is conducted to crystallize the amorphous silicon layer into a polysilicon layer.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to methods for fabricating polysilicon layers, and particularly to a method for fabricating a polysilicon layer with large and uniform grains. 
       BACKGROUND 
       [0002]    At present, liquid crystal displays (LCDs) are the most common type of displays used in products such as notebook computers, game centers, and the like. 
         [0003]    The principal driving devices for an LCD are thin film transistors (TFTs). Because the amorphous silicon layer in amorphous silicon TFTs can be made at a relatively low temperature (between 200° C. and 300° C.), amorphous silicon TFTs are frequently used in LCDs. However, the electron mobility of amorphous silicon is lower than 1 cm 2 /V.S. (one square centimeter per volt second). Hence, amorphous silicon TFTs cannot provide the speeds required of an LCD in certain high-speed devices. On the other hand, the polycrystalline silicon (or polysilicon) TFT has electron mobility as high as 200 cm 2 /V.S. Therefore polysilicon TFTs are more suitable for high-speed operations. However, the process of transforming an amorphous silicon layer into a polysilicon layer often requires an annealing temperature in excess of 600° C. Under that temperature, the glass substrate supporting the TFTs is liable to be distorted. Thus, a number of methods for fabricating a polysilicon layer at a reduced temperature have been developed. Among such methods, the excimer laser annealing (ELA) method is the most prominent. Because the temperature of the ELA method is under 500° C., the polysilicon layers fabricated using such low temperature process are often called low temperature polysilicon layers. 
         [0004]      FIGS. 9-12  are schematic, side cross-sectional views of part of a treated substrate, showing sequential stages of fabricating a polysilicon layer by a conventional ELA process. 
         [0005]    In step  1 , referring to  FIG. 9 , a substrate  100  is provided. The substrate  100  can be made of glass. Then a buffer layer  101  is formed on the substrate  100 . The buffer layer  101  can be a silicon oxide layer. 
         [0006]    In step  2 , referring to  FIG. 10 , an amorphous silicon layer  103  is formed on the buffer layer  101 . 
         [0007]    In step  3 , referring to  FIG. 11 , an ELA process is conducted. The amount of radiation energy incident on the amorphous silicon layer  103  provided by the excimer laser is carefully controlled, such that the entire amorphous silicon layer  103  is almost completely melted. Hence, only a few particles of the original amorphous silicon layer  103  remain on top of the buffer layer  101 . The particles serve as crystallization seeds. Thereafter, the melted silicon starts to crystallize from the crystallization seeds, eventually forming a polysilicon layer  104 . The polysilicon layer  104  contains a plurality of non-uniformly distributed crystal grains  106 , grain boundaries  107 , and protrusions  108  formed at the corresponding grains boundaries  107 . 
         [0008]    In step  4 , referring to  FIG. 12 , the protrusions  108  are removed by a plasma etching process to planarize the polysilicon layer  104 . 
         [0009]    In the above-described ELA process, the crystallization seeds are randomly formed at various positions on the buffer layer  101 . Therefore, the fabricated polysilicon layer  104  has a plurality of non-uniform polysilicon grains grown from the crystallization seeds. Moreover, it is hard to precisely control the radiation energy applied to the amorphous silicon layer  103 . If the radiation energy provided to the amorphous silicon layer  103  exceeds a super lateral growth (SLG) point, a density distribution of the crystallization seeds may drop to a very low value within a transient interval. The sudden loss of crystallization seeds may lead to the production of a lot of small and highly non-uniform grains. The polysilicon layer  104  having small and non-uniform grains has relatively low electron mobility. 
         [0010]    Accordingly, what is needed is a method for fabricating a polysilicon layer that can overcome the above-described deficiencies. 
       SUMMARY 
       [0011]    In one preferred embodiment, a method for fabricating a polysilicon layer includes the following steps: providing a substrate, and forming a first amorphous silicon layer over the substrate; removing portions of the first amorphous silicon layer to form a plurality of crystallization seeds through a photolithograph process; forming a second amorphous silicon layer over the substrate, the second amorphous silicon layer covering the crystallization seeds; and conducting a laser annealing process to crystallize the amorphous silicon layer into a polysilicon layer. 
         [0012]    In an alternative embodiment, a method for fabricating a polysilicon layer includes the following steps: providing a substrate, and forming a first amorphous silicon layer on the substrate; etching the first amorphous silicon layer to form a plurality of silicon particles; forming a second amorphous silicon layer over the substrate, the second amorphous silicon layer covering the silicon particles; and melting the second amorphous silicon layer and crystallizing the melted silicon into a polysilicon layer with the silicon particles as crystallization seeds. 
         [0013]    Other novel features and advantages will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]      FIG. 1  is a flowchart summarizing a method for fabricating a polysilicon layer according a preferred embodiment of the present invention. 
           [0015]      FIGS. 2 to 8  are schematic, side cross-sectional views of part of a treated substrate, showing sequential stages of the preferred method for fabricating a polysilicon layer. 
           [0016]      FIG. 9 to 12  are schematic, side cross-sectional views of part of a treated substrate, showing sequential stages of fabricating a polysilicon layer by a conventional ELA process. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0017]      FIG. 1  is a flowchart summarizing a method for fabricating a polysilicon layer according a preferred embodiment of the present invention. The method includes: step S 21 , providing a substrate and forming a buffer layer; step S 22 , forming a first amorphous silicon layer; step  23 , forming a plurality of crystallization seeds; step  24 , forming a second amorphous silicon layer; step  25 , forming a polysilicon layer; and step  26 , planarizing the polysilicon layer. 
         [0018]    In step S 21 , referring to  FIG. 2 , a substrate  200  is provided. The substrate  200  can be a glass substrate. Then a buffer layer  201  is formed on the substrate  200 . The buffer layer  201  is used for preventing impurities in the substrate  200  from diffusing into the silicon layers formed in subsequent steps. Thereby, the quality of a polysilicon layer eventually produced can be optimized. The buffer layer  201  can be a silicon oxide layer, a silicon nitride layer, or a multilayer structure having at least one silicon nitride layer and at least one silicon oxide layer. 
         [0019]    In step S 22 , referring to  FIG. 3 , a first amorphous silicon layer  203  is formed on the buffer layer  201 . The first amorphous silicon layer  203  may have a thickness of 50-100 nanometers (nm). The first amorphous silicon layer  203  can be made using a method such as vacuum evaporation, sputtering, plasma enhanced chemical vapor phase deposition (PECVD), low pressure chemical vapor phase deposition (LPCVD), and the like. 
         [0020]    In step S 23 , referring to  FIG. 4 , a photo-resist layer (not shown) is formed on the first amorphous silicon layer  203 . The photo-resist layer is then exposed and developed, thereby forming a photo-resist pattern  204 . The photo-resist pattern  204  covers predetermined points of the amorphous silicon layer  203  in a uniform pattern. 
         [0021]    Referring also to  FIG. 5 , using the photo-resist pattern  204  as a mask, a portion of the first amorphous silicon layer  203  that is not covered by the photo-resist pattern  204  is etched away by means of a dry etching method. Then the photo-resist pattern  204  is removed by an acetone solution. Thereby, the remaining uniformly spaced-apart points of the first amorphous silicon layer  203  serve as crystallization seeds  205 . A distance between each two adjacent crystallization seeds  205  is in a range of 0.5-3 micrometers (pan), and preferably 2 μm. An etchant of the dry etching method is a mixture of sulfur hexafluoride (SF 6 ) and carbon tetrafluoride (CF 4 ). 
         [0022]    The etching method can also be a wet etching method. An etchant of the wet etching method is an aqueous solution of nitric acid (HNO 3 ) and ammonium fluoride (NH 4 F). A preferred volume ratio of HNO 3 :NH 4 F:H 2 O can for example be 64:3:33. 
         [0023]    In step  24 , referring  FIG. 6 , a second amorphous silicon layer  206  is formed on the buffer layer  201 . The second amorphous silicon layer  206  completely covers the crystallization seeds  205 . The second amorphous silicon layer  206  can be made using a method such as vacuum evaporation, sputtering, plasma enhanced chemical vapor phase deposition (PECVD), low pressure chemical vapor phase deposition (LPCVD), and the like. Thereafter, superfluous hydrogen in the second amorphous silicon layer  206  is removed, in order to avoid hydrogen explosion in a subsequent ELA process. 
         [0024]    In step  25 , referring to  FIG. 7 , an ELA process is conduced to change the second amorphous silicon layer  206  into a polysilicon layer. During the ELA process, an excimer laser beam irradiates the second amorphous silicon layer  206 . Then the second amorphous silicon layer  206  is completely melted. Because the crystallization seeds  205  are made from the first amorphous silicon layer  203  and are under the second amorphous silicon layer  206 , the crystallization seeds  205  have a lower temperature than that of the second amorphous silicon layer  206 . Therefore, the crystallization seeds  205  are not melted. Thereafter, the temperature of the melted silicon decreases. The melted silicon starts crystallizing from the crystallization seeds  205  to form a plurality of crystal grains  207 . The crystal grains  207  grow and meet each other at corresponding boundaries  209 . The crystal grains  207  press on each other, thereby forming a plurality of protrusions  210 . Thus, a polysilicon layer  208  is formed. Because the crystallization seeds  205  are uniformly spread on the buffer layer  201  a predetermined distance apart from one another, the crystal grains  207  grow to have large and uniform sizes. 
         [0025]    In the above-described step of forming a polysilicon layer from the second amorphous silicon layer  206 , the thermal energy of the excimer laser is carefully controlled, in order that the buffer layer  201  and the substrate  200  have high and homogenous thermal distribution. This prolongs the growing time of the crystal grains  207  and facilitates forming of a polysilicon layer  208  having large and uniform grains. 
         [0026]    In step S 26 , referring to  FIG. 8 , the protrusions  210  of the polysilicon layer  208  are removed so that the polysilicon layer  208  becomes planar. The planarizing method can for example be a plasma etching method, a chemical mechanical polishing method, a chemical wet etching method, or an excimer laser annealing method. 
         [0027]    In the above-described preferred method, the crystallization seeds  205  are formed by the first amorphous silicon layer  203  through a photolithographic process. The positions of the crystallization seeds  205  and a distribution density of the crystallization seeds  205  are controllable. This ensures that the crystallization seeds  205  can be formed exactly where required. Thus the crystal grains  207  growing from the crystallization seeds  203  are uniformly distributed, the crystal grains  207  have larger crystal sizes, and there are fewer grain boundaries  209 . Accordingly, the polysilicon layer  208  having large and uniform grains is formed. The polysilicon layer  208  fabricated according to the above-described method has high electron mobility. The high electron mobility improves the quality of TFTs subsequently formed from the polysilicon layer. 
         [0028]    It is to be further understood that even though numerous characteristics and advantages of various embodiments have been set forth in the foregoing description, together with details of the related structures and functions of the embodiments, the disclosure is illustrative only, and changes may be made in detail to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.