Abstract:
There is a problem in related-art semiconductor devices that the chip size of a semiconductor device having an active Miller clamp function cannot be reduced. According to one embodiment, a semiconductor device is configured to, when a power device is turned on or off, monitor a gate voltage Vg of the power device, set a predetermined range within a transition range, the transition range being a range within which the gate voltage Vg changes, change, when the gate voltage Vg is within the predetermined range, the gate voltage Vg of the power device by using a predetermined number of constant-current circuits, and change, when the gate voltage Vg is outside the predetermined range, the gate voltage Vg by using a larger number of constant-current circuits than the number of constant-current circuits that are used when the gate voltage Vg is within the predetermined range.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is based upon and claims the benefit of priority from Japanese patent application No. 2016-074187, filed on Apr. 1, 2016, the disclosure of which is incorporated herein in its entirety by reference. 
       BACKGROUND 
       [0002]    The present invention relates to a semiconductor device. For example, the present invention relates to a semiconductor device in which a control signal supplied to a gate of a power device is controlled based on slew-rate control. 
         [0003]    A motor that drives a vehicle or the like requires large electric power in order to obtain a large output. Therefore, an inverter circuit that drives such a high-power motor is formed by using power devices such as IGBTs (Insulated Gate Bipolar Transistors) that can withstand a high voltage and a large current. Further, a gate of such a power device has a large parasitic capacitance. Therefore, to operate a power device, a gate driver capable of driving the gate of the power device is used. Japanese Unexamined Patent Application Publication No. H10-70878 discloses an example of such a gate driver. 
         [0004]    In the technique disclosed in Japanese Unexamined Patent Application Publication No. H10-70878, a gate drive circuit is formed by using an isolation circuit, a command selecting circuit, a plurality of transistors, gate resistors for an on-state, gate resistors for an off-state, and a gate power supply. An externally-commanded selection signal and a command signal are input to the command selecting circuit through the isolation circuit, and one of the gate resistors for an on-state and one of the gate resistors for an off-state are selected. Further, transistors corresponding to the selected gate resistor for an on-state and the gate resistor for an off-state are alternately turned on/off based on the command signal. 
       SUMMARY 
       [0005]    The present inventors have found the following problem. When a system using a power device is constructed, it is necessary to equip the system with a clamp circuit that maintains the gate of the power device at a high or low level in order to prevent the power device from malfunctioning due to a Miller capacitance. One example of the clamp circuit is an active Miller clamp circuit, which is formed by disposing a transistor having a small on-state resistance between the power device and a ground line. However, the active Miller clamp circuit requires a larger circuit size in order to reduce the resistance as much as possible and needs to be disposed separately from a gate drive circuit that provides the main function of the active Miller clamp circuit. Therefore, there is a problem that the chip size of a gate driver using an active Miller clamp circuit is large. 
         [0006]    Other objects and novel features will be more apparent from the following description in the specification and the accompanying drawings. 
         [0007]    According to one embodiment, a semiconductor device is configured to: when a power device is turned on or off, monitor a gate voltage of the power device; set a predetermined range within a transition range, the transition range being a range within which the gate voltage changes; change, when the gate voltage is within the predetermined range, the gate voltage of the power device by using a predetermined number of constant-current circuits; and change, when the gate voltage is outside the predetermined range, the gate voltage by using a larger number of constant-current circuits than the number of constant-current circuits that are used when the gate voltage is within the predetermined range. 
         [0008]    According to the above-described embodiment, it is possible to realize a semiconductor chip having a malfunction prevention mechanism equivalent to the active Miller clamp circuit with a small chip size. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The above and other aspects, advantages and features will be more apparent from the following description of certain embodiments taken in conjunction with the accompanying drawings, in which: 
           [0010]      FIG. 1  is a block diagram of an inverter circuit including a semiconductor device according to a first embodiment; 
           [0011]      FIG. 2  is a block diagram of the semiconductor device according to the first embodiment; 
           [0012]      FIG. 3  is a timing chart for explaining an operation of the semiconductor device according to the first embodiment; and 
           [0013]      FIG. 4  is a block diagram of a semiconductor device according to a second embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]    For clarifying the explanation, the following descriptions and the drawings may be partially omitted and simplified as appropriate. Further, the same symbols are assigned to the same components throughout the drawings and duplicated explanations are omitted as required. 
       First Embodiment 
       [0015]    A semiconductor device according to a first embodiment is a gate driver that drives a gate of a power device used in an inverter circuit that drives a load circuit requiring large electric power such as a high-power motor. Note that the power device may be any component having a low on-resistance and a high withstand voltage. Further, the circuit in which the power device is used is not limited to the inverter circuit. 
         [0016]      FIG. 1  shows a block diagram of an inverter circuit including a semiconductor device according to the first embodiment. In the block diagram shown in  FIG. 1 , a motor is shown as a load circuit of the inverter circuit. The motor is a three-phase drive type motor. Therefore, the inverter circuit according to the first embodiment is a three-arm type circuit. 
         [0017]    As shown in  FIG. 1 , the inverter circuit  1  according to the first embodiment includes a control unit  2 , isolation devices  3   b ,  3   d  and  3   f , gate drivers  4   a  to  4   f , and power devices  5   a  to  5   f . The control unit  2  outputs gate control signals (hereinafter referred to as “power device control signals”) that are supplied to the gates of the power devices  5   a  to  5   f . The power device control signals are PWM (Pulse Width Modulation) signals in the inverter circuit  1  according to the first embodiment. Further, the control unit  2  is, for example, a microcontroller (an MCU: Micro Controller Unit) in which an arithmetic circuit that executes a program, a memory that stores the program and the like, and peripheral circuits such as an analog-digital conversion circuit and a timer are disposed in one semiconductor package. 
         [0018]    The isolation devices  3   b ,  3   d  and  3   f  transfer the power device control signals output from the control unit  2  to the gate drivers  4   b ,  4   d  and  4   f , respectively, which operate in a voltage range different from that of the control unit  2 . That is, the isolation devices  3   b ,  3   d  and  3   f  convert the reference level of the power device control signals. 
         [0019]    The gate drivers  4   a  to  4   f  charge or discharge the gates of the power devices  5   a  to  5   f , respectively, based on the logical level of the power device control signals. Further, the gate drivers  4   a  to  4   f  control the rate (or the speed) of the charging/discharging of the gates of the power devices  5   a  to  5   f , respectively, based on the gate voltages of the power devices  5   a  to  5   f , respectively. Details of the gate drivers  4   a  to  4   f  will be explained later. 
         [0020]    Each of the power devices  5   a  to  5   f  includes a power transistor PTr and a diode D. The anode of the diode D is connected to the emitter of the power transistor PTr and the cathode of the diode D is connected to the collector of the power transistor PTr. Further, each of the power devices  5   a  to  5   f  includes a first terminal (e.g., an emitter terminal Te), a second terminal (e.g., a collector terminal Tc), and a control terminal (e.g., a gate terminal Tg). Note that the power transistor PTr is, for example, an IGBT (Insulated Gate Bipolar Transistor) component. 
         [0021]    In the inverter circuit  1 , the power devices  5   a  and  5   b  are connected in series between a power supply line VDD and a ground line VSS, and thereby form a first arm. The power devices  5   c  and  5   d  are connected in series between the power supply line VDD and the ground line VSS, and thereby form a second arm. The power devices  5   e  and  5   f  are connected in series between the power supply line VDD and the ground line VSS, and thereby form a third arm. 
         [0022]    Note that one of the features of the inverter circuit  1  according to the first embodiment lies in the gate drivers  4   a  to  4   f . The gate drivers  4   a  to  4   f  have the same configuration. Therefore, the gate drivers according to the first embodiment are explained hereinafter by using only the gate driver  4   a  as an example. Accordingly,  FIG. 2  shows a block diagram of the gate driver  4   a  according to the first embodiment. Note that  FIG. 2  shows the power device  5   a  in order to explain a connection relation between circuits in the gate driver  4   a  and the power device  5   a.    
         [0023]    As shown in  FIG. 2 , the gate driver  4   a  according to the first embodiment includes a constant-current circuit selecting circuit (e.g., a transistor selecting circuit  10 ), a gate mode setting circuit  11 , a first comparator  12 , a second comparator  13 , a first threshold voltage switching part (e.g., a first threshold voltage switch  14 ), a second threshold voltage switching part (e.g., a second threshold voltage switch  15 ), first constant-current circuits  161  to  16   m  (m is an integer), second constant-current circuits  171  to  17   m , and a gate line Wg. Further, the gate driver  4   a  according to the first embodiment operates based on an internal power supply voltage that is supplied to an internal power supply line VDDi and is different from and lower than a power supply voltage for the inverter circuit  1 . In the following explanation, the internal power supply line VDDi is simply referred to as a “power supply line VDDi”. 
         [0024]    The transistor selecting circuit  10  selects a constant-current circuit(s) to be activated from among the first constant-current circuits  161  to  16   m  and the second constant-current circuits  171  to  17   m  and outputs an activation instruction signal(s) to the selected constant-current circuit(s). The transistor selecting circuit  10  outputs activation signals SCPs 1  to SCPsm and activation signals SCNs 1  to SCNsm as activation signals. The activation signals SCPs 1  to SCPsm and activation signals SCNs 1  to SCNsm correspond to the first constant-current circuits  161  to  16   m  and the second constant-current circuits  171  to  17   m , respectively. 
         [0025]    The gate mode setting circuit  11  controls an on/off-state(s) of the constant-current circuit(s) selected by the transistor selecting circuit  10  based on a gate control signal (e.g., a power device control signal) for controlling an on/off-state of a power device, the activation signals SCPs 1  to SCPsm, the activation signals SCNs 1  to SCNsm, a first voltage detection signal, and a second voltage detection signal. The first voltage detection signal is an output signal of the first comparator  12 . The second voltage detection signal is an output signal of the second comparator  13 . 
         [0026]    More specifically, the gate mode setting circuit  11  controls the on/off-state of the constant-current circuit(s) selected by the transistor selecting circuit  10  in a period in which the first and second voltage detection signals have different logical levels. Further, the gate mode setting circuit  11  increases the number of constant-current circuits that are controlled to an on-state in a period in which the first and second voltage detection signals have the same logical level compared to the number of constant-current circuits controlled in the period in which the first and second voltage detection signals have different logical levels. 
         [0027]    The first comparator  12  changes the logical level of the first voltage detection signal from a first logical level (e.g., a low level) to a second logical level (e.g., a high level) when a voltage at the gate terminal Tg becomes higher than a first threshold voltage. The voltage at the gate terminal Tg (e.g., a gate voltage Vg) is input to a non-inverting input terminal of the first comparator  12 . The first threshold voltage selected by the first threshold voltage switch  14  is input to an inverting input terminal of the first comparator  12 . 
         [0028]    In the gate driver  4   a  according to the first embodiment, a first pre-boost threshold voltage Vt 1  and a first clamp threshold voltage Vt 2  lower than the first pre-boost threshold voltage Vt 1  are used as the first threshold voltages. The first threshold voltage switch  14  selects the first pre-boost threshold voltage Vt 1  in a period in which the power device control signal has a high level, and selects the first clamp threshold voltage Vt 2  in a period in which the power device control signal has a low level. Further, the first threshold voltage switch  14  supplies the selected threshold voltage to the first comparator  12 . 
         [0029]    The second comparator  13  changes the logical level of the second voltage detection signal from a low level to a high level when the voltage at the gate terminal Tg becomes higher than a second threshold voltage. The gate voltage Vg is input to a non-inverting input terminal of the second comparator  13 . The second threshold voltage selected by the second threshold voltage switch  15  is input to an inverting input terminal of the second comparator  13 . 
         [0030]    In the gate driver  4   a  according to the first embodiment, a second clamp threshold voltage Vt 3  and a second pre-boost threshold voltage Vt 4  lower than the second clamp threshold voltage Vt 3  are used as the second threshold voltages. The second threshold voltage switch  15  selects the second clamp threshold voltage Vt 3  in a period in which the power device control signal has a high level, and selects the second pre-boost threshold voltage Vt 4  in a period in which the power device control signal has a low level. Further, the second threshold voltage switch  15  supplies the selected threshold voltage to the second comparator  13 . 
         [0031]    Note that the first pre-boost threshold voltage Vt 1 , the first clamp threshold voltage Vt 2 , the second clamp threshold voltage Vt 3 , and the second pre-boost threshold voltage Vt 4  have a voltage relation “Vt 2 &lt;Vt 1 &lt;Vt 4 &lt;Vt 3 ”. 
         [0032]    The first constant-current circuits  161  to  16   m  are connected between the gate line Wg and the power supply line VDDi. The first constant-current circuits  161  to  16   m  include first constant-current sources Isp 1  to Ispm, respectively, and first switches SWp 1  to SWpm, respectively. One ends of the first constant-current sources Isp 1  to Ispm are connected to the power supply line. The first switches SWp 1  to SWpm are connected between the other ends of the first constant-current sources Isp 1  to Ispm and the gate line Wg, and their open/close states are switched by the gate mode setting circuit  11 . 
         [0033]    The second constant-current circuits  171  to  17   m  are connected between the gate line Wg and the ground line. The second constant-current circuits  171  to  17   m  include second constant-current sources Isn 1  to Isnm, respectively, and second switches SWn 1  to SWnm, respectively. One ends of the second constant-current sources Isn 1  to Isnm are connected to the ground line. The second switches SWn 1  to SWnm are connected between the other ends of the second constant-current sources Isn 1  to Isnm and the gate line Wg, and their open/close states are switched by the gate mode setting circuit  11 . 
         [0034]    Note that the gate mode setting circuit  11  outputs switch control signals Sswp 1  to Sswpm as signals for controlling the open/close states of the first switches SWp 1  to SWpm, respectively. Further, the gate mode setting circuit  11  outputs switch control signals Sswn 1  to Sswnm as signals for controlling the open/close states of the second switches SWn 1  to SWnm, respectively. The switch control signals bring the first and second switches into an opened state (an on-state) when they have a high level, and bring the first and second switches into a closed state (an off-state) when they have a low level. 
         [0035]    Next, an operation of the gate driver  4   a  according to the first embodiment is explained. Therefore,  FIG. 3  shows a timing chart for explaining the operation of the gate driver  4   a  according to the first embodiment. Note that in the example shown in  FIG. 3 , the transistor selecting circuit  10  selects only the first constant-current circuit  161  and the second constant-current circuit  171  as circuits to be activated. 
         [0036]    In the example shown in  FIG. 3 , the level of the power device control signal changes from a high level to a low level at a timing T 1 . As a result, the first threshold voltage switch  14  selects the first clamp threshold voltage Vt 2  and the second threshold voltage switch  15  selects the second pre-boost threshold voltage Vt 4 . 
         [0037]    Then, the gate mode setting circuit  11  changes the levels of the switch control signals Sswp 1  to Sswpm from a high level to a low level. Further, the gate mode setting circuit  11  changes the level of the switch control signal Sswn 1  from a low level to a high level. 
         [0038]    Further, the timing T 1  is a point of time (hereinafter also referred to as a “time point”) at which an electric charge starts to be pulled out from the gate of the power device  5   a  and the gate voltage Vg of the power device  5   a  is higher than the second pre-boost threshold voltage vt 4  and the first clamp threshold voltage Vt 2 . Therefore, the levels of both of the first and second voltage detection signals output from the first and second comparators  12  and  13 , respectively, become a high level. As a result, the gate mode setting circuit  11  changes the levels of the switch control signals Sswn 2  to Sswnm to a high level at the timing T 1 . That is, at the timing T 1 , all of the second constant-current circuits  171  to  17   m  become an active state and hence an electric charge is pulled out from the gate of the power device  5   a  by the second constant-current circuits  171  to  17   m.    
         [0039]    Next, at a timing T 2 , the gate voltage Vg of the power device  5   a  falls and becomes lower than the second pre-boost threshold voltage Vt 4 . As a result, the second comparator  13  changes the level of the second voltage detection signal from the high level to a low level. Then, in response to the fall of the second voltage detection signal to the low level, the gate mode setting circuit  11  changes the levels of the switch control signals Sswn 2  to Sswnm to a low level. Therefore, from the timing T 2  to a timing T 3 , the gate driver  4   a  performs slew-rate control in which an electric charge is pulled out from the gate of the power device  5   a  only by the second constant-current circuit  171 , which the transistor selecting circuit  10  has instructed to activate. 
         [0040]    Next, at the timing T 3 , the gate voltage Vg of the power device  5   a  further falls and becomes lower than the first clamp threshold voltage Vt 2 . As a result, the first comparator  12  changes the level of the first voltage detection signal from a high level to a low level. Then, in response to the fall of the first voltage detection signal to the low level, the gate mode setting circuit  11  changes the levels of the switch control signals Sswn 2  to Sswnm to a high level again. Therefore, at and after the timing T 3 , the gate driver  4   a  performs clamp control in which the gate of the power device  5   a  is maintained at the low level by the second constant-current circuits  171  to  17   m  irrespective of whether the transistor selecting circuit  10  has instructed them to activate or not. 
         [0041]    Next, in the example shown in  FIG. 3 , the level of the power device control signal changes from the low level to a high level at a timing T 4 . As a result, the first threshold voltage switch  14  selects the first pre-boost threshold voltage Vt 1  and the second threshold voltage switch  15  selects the second clamp threshold voltage Vt 3 . 
         [0042]    Then, the gate mode setting circuit  11  changes the levels of the switch control signals Sswn 1  to Sswnm from the high level to a low level. Further, the gate mode setting circuit  11  changes the level of the switch control signal Sswp 1  from the low level to a high level. 
         [0043]    Further, the timing T 4  is a time point at which an electric charge starts to be charged into (i.e., accumulated in) the gate of the power device  5   a  and the gate voltage Vg of the power device  5   a  is lower than the first pre-boost threshold voltage vt 1  and the second clamp threshold voltage Vt 3 . Therefore, the levels of both of the first and second voltage detection signals output from the first and second comparators  12  and  13 , respectively, become a low level. As a result, the gate mode setting circuit  11  changes the levels of the switch control signals Sswp 2  to Sswpm to a high level at the timing T 4 . That is, at the timing T 4 , all of the first constant-current circuits  161  to  16   m  become an active state and hence an electric charge is charged into the gate of the power device  5   a  by the first constant-current circuits  161  to  16   m.    
         [0044]    Next, at a timing T 5 , the gate voltage Vg of the power device  5   a  rises and becomes higher than the first pre-boost threshold voltage Vt 1 . As a result, the first comparator  12  changes the level of the first voltage detection signal from the low level to a high level. Then, in response to the rise of the second voltage detection signal to the high level, the gate mode setting circuit  11  changes the levels of the switch control signals Sswp 2  to Sswpm to a low level. Therefore, from the timing T 5  to a timing T 6 , the gate driver  4   a  performs slew-rate control in which an electric charge is charged into the gate of the power device  5   a  only by the first constant-current circuit  161 , which the transistor selecting circuit  10  has instructed to activate. 
         [0045]    Next, at the timing T 6 , the gate voltage Vg of the power device  5   a  further rises and becomes higher than the second clamp threshold voltage Vt 3 . As a result, the second comparator  13  changes the level of the second voltage detection signal from the low level to a high level. Then, in response to the rise of the second voltage detection signal to the high level, the gate mode setting circuit  11  changes the levels of the switch control signals Sswp 2  to Sswpm to a high level again. Therefore, at and after the timing T 6 , the gate driver  4   a  performs clamp control in which the gate of the power device  5   a  is maintained at the high level by the first constant-current circuits  161  to  16   m  irrespective of whether the transistor selecting circuit  10  has instructed them to activate or not. 
         [0046]    As explained above, in the gate driver  4   a  according to the first embodiment, by monitoring the gate voltage Vg of the power device  5   a  by using the first and second comparators  12  and  13 , a pre-boost operation can be performed at the start of the transition of the gate voltage Vg and, after the gate voltage Vg becomes equal to or higher than a specific voltage while reducing the transition time of the gate voltage Vg, slew-rate control can be performed. 
         [0047]    Further, in the gate driver  4   a  according to the first embodiment, by monitoring the gate voltage Vg of the power device  5   a , after the gate voltage Vg has sufficiently changed, clamp control for maintaining the gate voltage Vg of the power device  5   a  is performed by using a larger number of constant-current circuits than the number of constant-current circuits used in the slew-rate control period. That is, the gate driver  4   a  according to the first embodiment can realize functions equivalent to those of an active Miller clamp circuit without requiring transistors for the active Miller clamp circuit separately from those in the circuit used for the slew-rate control. Further, it is possible to reduce (or eliminate) the area for transistors used for the active Miller clamp circuit from the semiconductor chip and hence to reduce the size of the semiconductor chip. 
         [0048]    Further, in the gate driver  4   a  according to the first embodiment, the threshold voltages supplied to the first and second comparators  12  and  13  are changed depending on whether the power device  5   a  is in an on-state or in an off-state by using the first and second threshold voltage switches  14  and  15 . In this way, the gate driver  4   a  according to the first embodiment can reduce the number of comparators that are used to monitor the gate voltage Vg. Further, by reducing the number of comparators, the size of the semiconductor chip can be reduced. 
       Second Embodiment 
       [0049]    In a second embodiment, specific examples of the gate mode setting circuit  11  and other embodiments of the first constant-current circuits  161  to  16   m  and the second constant-current circuits  171  to  17   m  are explained. Therefore,  FIG. 4  shows a block diagram of a semiconductor device according to the second embodiment. Note that in the explanation of the second embodiment, the same symbols as those in the first embodiment are assigned to the same components as those in the first embodiment and their explanations are omitted. 
         [0050]    As shown in  FIG. 4 , a gate driver  4   a  according to the second embodiment uses groups of logical circuits (hereinafter referred to as “logical circuit groups”)  111  to  11   m  as the gate mode setting circuit  11 . Further, PMOS transistors MP 1  to MPm are used as the first constant-current circuits  161  to  16   m  and NMOS transistors MN 1  to MNm are used as the second constant-current circuits  171  to  17   m . The logical circuit groups  111  to  11   m  are provided so as to correspond to the PMOS transistors MP 1  to MPm, respectively, and to the NMOS transistors MN 1  to MNm, respectively. Further, the logical circuit groups  111  to  11   m  output gate voltages Vgp 1  to Vgpm, respectively, and gate voltages Vgn 1  to Vgnm, respectively, as signals for switching on/off-states of the PMOS transistors MP 1  to MPm, respectively, and on/off-states of the NMOS transistors MN 1  to MNm, respectively. Note that the logical levels of the gate voltages Vgp 1  to Vgpm are opposite to those of the switch control signals Sswp 1  to Sswpm explained in the first embodiment. 
         [0051]    The logical circuit groups  111  to  11   m  have the same configuration. Therefore, they are explained hereinafter by using the logical circuit group  111  as an example. As shown in  FIG. 4 , the logical circuit group  111  includes NOT circuits  21 ,  24  and  26 , a first logical multiplication circuit (e.g., an AND circuit  22 ), a second logical multiplication circuit (e.g., an AND circuit  23 ), a first logical sum circuit (e.g., an OR circuit  25 ), a second logical sum circuit (e.g., an OR circuit  27 ), a third logical sum circuit (e.g., an OR circuit  28 ), and a third logical multiplication circuit (e.g., an AND circuit  29 ). 
         [0052]    The AND circuit  22  calculates the logical multiplication of a corresponding activation signal SCPs 1  and a first voltage detection signal. The AND circuit  23  calculates the logical multiplication of an output value of the AND circuit  22  and a second voltage detection signal. The second voltage detection signal, which is input to the AND circuit  23 , is a second voltage detection signal inverted by the NOT circuit  24 . The OR circuit  25  calculates the logical sum of an output value of the AND circuit  23  and an inverted signal of a power device control signal and outputs the calculated value to a corresponding first constant-current circuit (e.g., a PMOS transistor MP 1 ). The power device control signal, which is input to the OR circuit  25 , is a power device control signal inverted by the NOT circuit  21 . 
         [0053]    The OR circuit  27  calculates the logical sum of a corresponding activation signal SCNs 1  and an inverted signal of the first voltage detection signal. The first voltage detection signal, which is input to the OR circuit  27 , is a first voltage detection signal inverted by the NOT circuit  26 . The OR circuit  28  calculates the logical sum of an output value of the OR circuit  27  and the second voltage detection signal. The AND circuit  29  calculates the logical multiplication of an output value of the OR circuit  28  and an inverted signal of the power device control signal and outputs the calculated value to a corresponding second constant-current circuit (e.g., an NMOS transistor MN 1 ). The power device control signal, which is input to the AND circuit  29 , is the power device control signal inverted by the NOT circuit  21 . 
         [0054]    As explained above, the gate driver  4   a  according to the second embodiment can realize the logical circuit groups  111  to  11   m , which are formed by simple logical circuits, as the gate mode setting circuit  11 . 
         [0055]    The present invention made by the inventors has been explained above in a specific manner based on embodiments. However, the present invention is not limited to the above-described embodiments, and needless to say, various modifications can be made without departing from the spirit and scope of the present invention. 
         [0056]    For example, the gate driver  4   a  or the like explained in the above-described embodiments can be also applied to power devices other than the IGBTs. 
         [0057]    While the invention has been described in terms of several embodiments, those skilled in the art will recognize that the invention can be practiced with various modifications within the spirit and scope of the appended claims and the invention is not limited to the examples described above. 
         [0058]    Further, the scope of the claims is not limited by the embodiments described above. 
         [0059]    Furthermore, it is noted that, Applicant&#39;s intent is to encompass equivalents of all claim elements, even if amended later during prosecution. 
         [0060]    The first and second embodiments can be combined as desirable by one of ordinary skill in the art.