Abstract:
A re-programmable logic array includes at least one input and at least one output. An input capacitive device is coupled to the at least one input. Internal gating devices are coupled to the input capacitive device, and an output capacitive device is coupled to the internal gating devices and the at least one output. Signal generating circuitry for controlling the internal gating devices is further provided. The internal gating devices are designed to be controlled to establish a connection between one of the at least one input and one of the at least one output.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to circuitry, and more particularly, to programmable logic array circuitry that enables flexible programming and re-programming. 
     2. Description of the Related Art 
     In some control units, random logic combinational circuits are often required to generate control signals. To implement such functions, PLAs (programmable logic arrays) become a general solution. Traditional PLAs, such as PLA  10  of FIG. 1, are defined as a matrix that includes inverter (INV) arrays  12 , AND arrays  14 , OR arrays  16 , and the like. In such example, the logic gates are electrically connected to one another. 
     The programming rule is hard-wired by blowing (e.g., burning) fuses  18 . The concept and implementation of PLAs are therefore quite straightforward. However, once programming is executed, the PLA can no longer be modified. In other words, it lacks re-programming capability. This drawback therefore introduces a costly inconvenience to both end users as well as system designers. Designers will thus be forced to purchase new hardware to implement a new design change or accommodate some unanticipated use by a customer. 
     In view of the foregoing, there is a need for a logic array circuitry that can easily be re-programmed to account for changes in design or end-user implementation. 
     SUMMARY OF THE INVENTION 
     Broadly speaking, the present invention fills this need by providing programmable logic array circuitry that can easily be re-programmed. The re-programmability of the logic array provides for more flexible design options and reduces the cost of hardware and re-engineering. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, a system, or a device. Several inventive embodiments of the present invention are described below. 
     In one embodiment, a logic array is provided. The logic array at least one input and at least one output. An input capacitive device is coupled to the at least one input. Internal gating devices are coupled to the input capacitive device, and an output capacitive device is coupled to the internal gating devices and the at least one output. Signal generating circuitry for controlling the internal gating devices is further provided. The internal gating devices are designed to be controlled to establish a connection between one of the at least one input and one of the at least one output. 
     In another embodiment, a re-programmable logic array (RPLA) is provided. The RPLA includes at least one input and a plurality of outputs. An input capacitive device is coupled to the at least one input. Internal gating devices are coupled to the input capacitive device. A plurality of output capacitive devices is further provided. Each output capacitive device is coupled to one of the internal gating devices and one of the plurality of outputs. Signal generating circuitry is provided for controlling the internal gating devices. The internal gating devices are controlled to establish a connection between one input and one of the plurality of outputs. 
     In yet another embodiment, a re-programmable logic array (RPLA) is provided. The RPLA includes an input and an output. An input capacitive device is coupled to the input. A plurality of selectable logic blocks is provided. Each selectable logic block is coupled to the input capacitive device. A plurality of internal gating devices is provided, and each of the internal gating devices is coupled to respective ones of the plurality of selectable logic blocks. Further included in the RPLA is an output capacitive device. The output capacitive device is coupled to each of the internal gating devices and the output. Signal generating circuitry for controlling the internal gating devices is provided. The internal gating devices are controlled to establish a connection between the input, one of the selectable logic blocks, and the output. 
     The advantages of the present invention are numerous. Most notably, however, is that the RPLA of the present invention is more flexible that prior art PLA&#39;s that require the blowing of fuses to complete programming designs. By providing the sample and hold (S/H) circuitry of the present invention, generated control signals enable fast and efficient programming of the RPLA. The S/H circuitry, as will be understood by one skilled in the art, will enable synchronization with the system clock (CK) and application to a pipeline system. Furthermore, the RPLA can be re-utilized, which makes hardware circuitry reusable and beneficially enables a reduction in system hardware cost. 
    
    
     Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, and like reference numerals designate like structural elements. 
     FIG. 1 illustrates a conventional PLA, which is hardwired and not re-programmable. 
     FIG. 2 is a high level illustration of an example interconnection between a memory device and multiple processors. 
     FIG. 3 illustrates in more detail exemplary circuitry for enabling the re-programmable logic array. 
     FIG. 4 is a circuit diagram of a signal generator, in accordance with one embodiment of the present invention. 
     FIG. 5 shows an alternative implementation of the RPLA to interconnect a selected logic block between one input and one output. 
     FIG. 6 shows yet another alternative implementation of the RPLA to interconnect one of multiple inputs to one of multiple outputs. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     An invention is described for programmable logic array circuitry that can easily be re-programmed. Specific details of several embodiments of the present invention are described below. It will be obvious to one skilled in the art, however, that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail to avoid obscuring the present invention unnecessarily. 
     FIG. 2 illustrates a flash memory  22  being coupled to a re-programmable logic array (RPLA)  24 . RPLA  24  is configured to receive a clock CK, signals A, B, and C. PLA  24  is further coupled to a number of central processing units (CPUs), such as CPU 1 , CPU 2  and CPU 3 . RPLA  24  is shown providing more than one CPU access to a single memory (i.e., flash memory  22 ). Thus, RPLA  24  is required to control which CPU executes the accessing operation to the memory, and such control results in different consequences depending on timing. In one embodiment, the RPLA  24  is able to be re-programmed in response to various programming control signals, which are applied at appropriate times. In contrast, the prior art PLA  10  of FIG. 1 is not able to be re-programmed, and thus cannot provide the functionality that is provided by RPLA  24 . 
     In accordance with one aspect of the present invention, the RPLA  24  is designed with specialized sample and hold (S/H) circuitry. The S/H circuitry is configured to be synchronized with the system clock (CK) of a particular design. Such circuitry is also well suited to be applied to a pipeline system. 
     FIG. 3 illustrates a circuit diagram of a re-programmable logic array (RPLA), in accordance with one embodiment of the present invention. The RPLA  24  is coupled to the flash memory  22  via a bus  31 . Bus  31  is coupled to an AND gate  32 . The AND gate  32  is connected to a terminal of transistor  34 , which functions as an enabling transistor. Transistor  34  has its gate connected to φ 1 . Transistor  34  has its other terminal connected to a node  36 . Node  36  is connected to a capacitor C 1 , which is further coupled to ground. Capacitor C 1  will thus function as a temporary storage. Node  36  is also coupled to a terminal of each of transistors  38 ,  40 , and  39 . Transistor  38  has its gate coupled to φ 2 , transistor  40  has its gate coupled to φ 3 , and transistor  39  has its gate coupled to φ 4 . 
     Each of φ 1 , φ 2 , φ 3 , and φ 4  is defined as a control signal and is provided by circuitry of a signal generator  52 . As shown, signal generator  52  is configured to receive signals φ 1 , A, B, and C. The other terminals of transistors  38 ,  40 , and  39  are coupled respectively to nodes  42 ,  44 , and  46 . Node  42  is coupled to a capacitor C a , node  44  is coupled to a capacitor C b , and node  46  is coupled to a capacitor C c . Each of capacitors C a , C b , and C c  is thus a capacitor for temporary storage. Nodes  42 ,  44 , and  46  are thus provided as inputs to OR gates  48 ,  49 , and  50 , respectively. The outputs of OR gates  48 ,  49 , and  50  will therefore couple to some other devices, or in this specific example, central processing units (CPUs)  1 ,  2 , and  3 , respectively. 
     With continuing reference to FIG. 3, the architecture diagram of the RPLA  24  is provided with the aforementioned S/H circuitry. In operation, when data is to be sent to a designated CPU (e.g., CPU 1 , CPU 2 , CPU 3 ) by flash memory  22 , φ 1  is logic 1. As defined herein, therefore, φ 1  is an enabling signal. In this state, data will be stored in C 1 , while φ 2 , φ 3 , φ 4  are logic 0. On the other hand, when φ 1  is logic 0, data is sent to one of the CPUs depending on which one of φ 2 , φ 3 , and φ 4  is logic 1. In this manner, the destination address of data can be flexibly determined. Similarly, when data is to be sent to flash memory  22  by one of CPUs, the CPU allowed to communicate such data to the flash memory is determined based on which of φ 2 , φ 3 , or φ 4  is logic 1. 
     FIG. 4 illustrates a more detailed diagram of the signal generator  52  of FIG. 3, in one embodiment of the present invention. As shown, φ 1 , A, B, and C are provided as inputs to the signal generator  52 . Each of signal inputs A, B, and C is passed through inverters  54 ,  56 , and  58 , respectively. The inverted signals are then provided as inputs to NOR gates  60 ,  62 , and  64 . The second input to the NOR gates  60  is provided as control signal φ 1 . In this manner, NOR gate  60  will generate an output φ 2 , NOR gate  62  will produce an output φ 3 , and NOR gate  64  will produce an output φ 4 . Accordingly, the outputs φ 2 , φ 3 , and φ 4  are provided to the respective transistors as illustrated and discussed with reference to FIG.  3 . 
     Still referring to FIG. 4, the signal generator  52  is provided to enable efficient generation of control signals φ 2 , φ 3 , φ 4 . As a result, the inputs provided on φ 1 , A, B, and C will determine what control signals φ 2 , φ 3 , and φ 4  are activated. As mentioned above, the control signals φ 2 , φ 3 , and φ 4  will in turn transfer the appropriate programming to the logic arrays. This flexible programming capability will therefore eliminate the need to replace hardware logic arrays to enable new operating schemes or to simply allow for more flexible interfacing with multiple inputs, multiple outputs, or combinations of multiple inputs and outputs as will be discussed with reference to FIGS. 5 and 6. 
     FIG. 5 illustrates an alternative embodiment in which one of logic blocks (LB)  1 ,  2 , or  3  is connected between an input (IN) and an output (OUT). As shown, the input is provided to AND gate  66  which provides its output to a terminal of transistor  68 . The gate of transistor  68  is coupled to φ 1 . The other terminal of transistor  68  is coupled to node  70 . A capacitor C 1  is coupled to node  70 . Node  70  is likewise connected to each of logic blocks LB 1   72 , LB 2   74 , and LB 3   76 . 
     The output of LB 1   72  is connected to a terminal of transistor  78 , which has its gate connected to φ 2 . The other terminal of transistor  78  is coupled to node  84 . The output of LB 2   74  is connected to a terminal of transistor  80 . The gate of transistor  80  is connected to φ 3 , and the other terminal of transistor  80  is connected to node  84 . The output of LB 3   76  is connected to a terminal of transistor  82 . Transistor  82  has its gate connected to φ 4 . The other terminal of transistor  82  is then connected to node  84 . Accordingly, a terminal of each of transistors  78 ,  80 , and  82  is connected to node  84 , which is also coupled to a capacitor C 2 . Node  84  further defines the input to an OR gate  86 , which then provides the output (OUT). In this example, therefore, it is possible to connect one input to one output, while programmably connecting to a desired one of multiple logic blocks (LBs). 
     FIG. 6 illustrates yet another embodiment in accordance with the present invention. In this embodiment, connection is selected from one of the inputs (e.g., IN 1 , IN 2 , or IN 3 ) to one of the outputs (e.g., OUT 1 , OUT 2 , or OUT 3 ). As illustrated, input IN 1 , is connected to an AND gate  92 . The output of AND gate  92  is coupled to a terminal of transistor  98 . The gate of transistor  98  is connected to φ 2 . The input IN 1  is shown connected to AND gate  94 , which has its output connected to a terminal of transistor  100 . Transistor  100  has its gate connected to φ 2 . The input IN 3  is shown connected to AND gate  96 , which has its output connected to a terminal of transistor  102 . Transistor  102  has its gate connected to φ 3 . A node  104  is thus connected to the remaining terminal of each of transistors  98 ,  100 , and  102 . Node  104  is further shown connected to logic block  108 , and a capacitor C 1  is coupled to node  104 . 
     A node  110  is coupled to the output of logic block (LB)  108 . Node  110  is thus connected to a terminal of each of transistors  112 ,  114 , and  116 . The gates of transistors  112 ,  114 ,  116  are respectively coupled to φ 4 , φ 5 , and φ 6 . The remaining terminals of transistors  112 ,  144 , and  116 , are coupled respectively to nodes  113 ,  115 , and  117 . Node  113  is coupled to a capacitor C a . Node  113  further defines the input to OR gate  118  that defines output (OUT 1 ). Node  115  is further shown coupled to a capacitor C b . Node  115  defines the input of OR gate  120  that outputs OUT 2 . Finally, node  117  is connected to a capacitor C c . Node  117  defines the input to OR gate  122  that defines OUT 3 . In this manner, by controlling the signals provided to φ 1  through φ 6 , it is possible to define a programmable connection between one of the inputs IN 1 -IN 3 , to one of the outputs OUT 1 -OUT 3 . 
     From the described embodiments, it is evident that the RPLA of the present invention is very flexible in establishing controlled re-programmed states. These re-programmed states therefore enable precision interconnection with selected inputs and selected outputs, while the S/H circuitry enables synchronization with the system clock (CK), and application to a pipeline system. The re-utilization of the RPLA circuitry for different implementations thus beneficially enables a reduction in system hardware cost. 
     The invention may employ various computer-implemented operations involving data stored in computer systems. These operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in connection or interface with the RPLA circuitry defined herein. Further, the manipulations performed are often referred to in terms, such as producing, identifying, determining, or comparing. 
     Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.