Abstract:
A semiconductor device is provided wherein a current mirror circuit controlled by a pulse input voltage is utilized and a load is driven in such a manner that the output current of the current mirror circuit becomes a substantially constant current. Further, the output voltage of the current mirror circuit can be compared with a predetermined reference voltage by a comparator, with the current mirror circuit being controlled by the output voltage of the comparator in accordance with the result of comparison. The driver circuit can be used for driving the data lines of a dynamic random access memory or an external capacitance load. With these techniques, power consumption and peak current are reduced.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a semiconductor device and more particularly to a driver circuit which is suitable for reducing a peak current or for controlling the output voltage. 
     Conventionally, there has been the problem in that a peak current becomes excessively great when a large load capacitance is charged and discharged at a high speed. In a dynamic random access memory (hereinafter called &#34;DRAM&#34;) using dynamic memory cells, for example, an excessively large peak current that develops when a large number of data lines are altogether charged and discharged has been the problem. To cope with this problem, a voltage limiter circuit system such as one described in &#34;&#39;86 International Conference On Solid State Devices and Materials&#34;, Digest, pp. 307-310, has been proposed. 
     SUMMARY OF THE INVENTION 
     In the prior art system described above, the data lines are charged by an internal power source voltage which is obtained by reducing an external power source voltage on a chip. Therefore, though the current is reduced by effectively reducing the power source voltage, charge is left as such. 
     In addition, there is an inevitable limit to the reduction of the current because the prior art system does not employ any positive means for controlling the change of a charge peak current that varies in response to the change of drivability of MOS transistor resulting from the fluctuation of its gate length or threshold voltage due to the fluctuation of the fabrication process. 
     The present invention contemplates to improve the prior art technique described above. 
     The object of the invention described above can be accomplished by using a current mirror circuit as a driver whose output current can be made constant in response to a constant current source inside the current mirror circuit. 
     Furthermore, the present invention reduces the peak current by controlling the current value of the constant current source inside the current mirror circuit by a power source voltage and by the gate length Lg and threshold voltage V t  of an MOS transistor. 
     The current mirror circuit is not affected so easily by the fluctuation of process conditions and can therefore reduce the peak current. 
     Since a voltage limiter is employed, a low constant voltage can be obtained and power consumption can be reduced. 
     Since the current value of the constant current source inside the current mittor circuit can be controlled by the gate length L g  and threshold voltage V t  of the MOS transistor, the peak current can be reduced. 
     Accordingly, it is an object of the present invention to provide a driver circuit which effects charge and discharge of a load capacitance by an arbitrary predetermined constant current. 
     It is another object of the present invention to provide a semiconductor device which can reduce a peak current irrespective of the fluctuation of fabrication process. 
     It is still another object of the present invention to provide a semiconductor device which can reduce a peak current and power consumption through the combination with a voltage limiter circuit. 
     It is still another object of the present invention to provide a constant current source whose current value does not change so easily due to the fluctuation of fabrication process or to the change of a power source voltage. 
    
    
     These and other objects and many of the attendant advantages of this invention will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing the first, embodiment of the present invention; 
     FIGS. 2 and 3 is a diagram useful for explaining a specific operation of the present invention; 
     FIGS. 4 and 5 are explanatory views of the second embodiment of the present invention; and 
     FIGS. 6 through 21 are explanatory views useful for explaining the third through fifteenth embodiments of the present invention, respectively. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Hereinafter, some preferred embodiments of the present invention will be described in detail. 
     Embodiments Nos. 1 to 9 illustrate the embodiments of driving circuits using a current mirror circuit while Embodiments Nos. 10 to 15 relate to the improvement in a constant current source in the current mirror circuit. Therefore, any of the constant current circuits disclosed in Embodiments Nos. 10 to 15 can be applied as the constant current source in the current mirror circuits disclosed in Embodiments Nos. 1 to 9. 
     [Embodiment 1] 
     The first embodiment of the present invention and its waveform will be explained with reference to FIGS. 1 and 2, respectively. 
     In DRAM, one of memory cells MC (each consisting of one MOST and one capacitor, for example) disposed at the point of intersections between a word line W and a data line pair D o , D o  is selected and the data line pair is amplified by a well known sense amplifier SA consisting of p-MOST in accordance with this read-out information. In the case of the latest 1-mega bit DRAM, 1024 pairs of data lines must be charged simultaneously at a high speed. The total capacitance of 
     these data lines is as great as 500˜1,000 pF and hence a peak current becomes a problem. This charging operation is made by a driver circuit DRV connected to a common driving line CL1 of a flip-flop as the sense amplifier constituted by p-MOST. This embodiment is characterized in that the driver circuit DRV consists of a current mirror circuit and a comparator CMP. The current mirror circuit is controlled by a kind of inverter consisting of MOS transistors Q 1  and Q 2 . When the MOS transistor Q 2  is ON and Q 1  is OFF, the current mirror circuit is formed between an MOS transistor Q 3 , a constant current source S (i/n) and an output driver MOS transistor Q D . When the MOS transistor Q 2  is OFF and the MOS transistor Q 1  is ON, on the other hand, the output driver MOS transistor Q D  is OFF. The ON current of this transistor Q D  becomes a constant current i if the current of the current source S in the current mirror circuit is i s  =i/n, the gate width of the MOS transistor Q 3  is w/n and the gate width of the output driver MOS transistor Q D  is W. The driving current of Q D  can be kept substantially constant by keeping constant the current i s  =i/n of the constant current source S, even when the gate width w and gate length and the threshold voltage of the transistor vary due to fluctuation of fabrication process. Here, the reason why the current i s  of the constant current source is set to i/n and the gate width of the MOS transistor Q 3  is set to w/n is for the purpose of reducing the consumed current as well as the occupying area, and the value n is preferably greater. Here, symbol n represents the current ratio of the current mirror circuit and is given by n=i/i s . 
     The comparator CMP is disposed in order to compare a predetermined internal power source voltage V CL  (e.g. 4V) with the output voltage V o . If V CL  &gt;V o , the output of the comparator CMP becomes a high voltage and if V CL  &lt;V o , on the contrary, it becomes a low voltage. Incidentally, V CL  may be generated from V DD  (externally supplied power source voltage) inside the chip. 
     Under the preparation described above, the operation will now be explained. 
     Ordinary DRAMs are of the type wherein the data line pair is set to a value almost the half of V CL  during the stand-by operation, or of the so-called &#34;half precharge type&#34;. Therefore, the common driving line CL1 or all the data line pairs are precharged to V CL  /2. When a pulse is applied to the selected word line W under this state, read signals having a small difference appear on each data line pair D o , D o  ˜D 1023 , D 1023 . This state is illustrated typically in FIG. 2 by the data line pair D o , D o  arranged symmetrically with each other. Thereafter, the lower voltage side is discharged to 0 V by the sense amplifier SA consisting of n-MOST and p-MOST while the high voltage side is charged to V CL . Discharge is effected by applying a low voltage pulse to the common driving line CL2 of each n-MOST. However, the following description will deal only the case where charge is made by the pulse applied to the common driving line CL1 of p-MOST. 
     CL1 is driven when the input pulse φ is applied to the AND gate. When the input pulse φ is ON (the high voltage is inputted), the output voltage of the control circuit AND becomes the high voltage, the gate voltage V G  of Q D  becomes the output voltage V S  of the constant current source S and Q D  drives the load by a constant current i. As a result, the voltage V o  of the load rises from V CL  /2 at a predetermined rate but when it exceeds V CL , the comparator CMP operates and the output of the control circuit AND becomes the low voltage so that Q 1  is ON, Q 2  is OFF, Q D  is OFF and V o  is clamped substantially to V CL . Therefore, one of the data lines of each data line pair is charged substantially from V CL  /2 to V CL . 
     According to the embodiment described above, the data lines can be charged by a substantially constant current so that they can be charged at a high speed without the increase of the peak current. In addition, the influence of the fluctuation of the power source voltage V cc  and fabrication process can be minimized by keeping constant the current i s  of the constant current source. Furthermore, since the data line voltage is kept at a low level, consumed power can be reduced, as well. 
     As described above, the data lines can be charged by a substantially constant current by the driver circuit using the current mirror circuit. In order to obtain a constant current from this current mirror circuit, it is preferred that the driver MOS transistor Q D  be driven in the saturation region (|V o  -V cc  |≧|V s  -V cc  -V T  |). 
     As shown in FIG. 3, however, there is the case where this condition cannot be satisfied with the passage of time depending on the operation conditions, or the like. In other words, when the potential of V o  rises from V CL  /2 and becomes higher than the voltage V s  -|V T  | (where VT is the threshold voltage of Q D  and has generally a negative value because it is of a p-channel type), the following relation is established: 
     
         |V.sub.o -V.sub.cc |&lt;|V.sub.s -V.sub.cc -V.sub.T | 
    
     Accordingly, MOS Q D  operates in the non-saturation region. As a result, the current i becomes small and the time before V o  reaches V CL  (4 V) becomes long. Even if the driver MOS transistor Q D  operates in the saturation region, the problem similar to the one described above will occur when the channel length becomes shorter and shorter in future because the dependence of the drain current on the drain-source voltage becomes remarkable. 
     [Embodiment 2] 
     FIG. 4 shows the second embodiment of the present invention which solves the problem described above and can accomplish better constant current charging. 
     In this embodiment, m (here, m=4, by way of example) driver MOS transistors Q D  are disposed to constitute a current mirror circuit and are sequentially ON with the passage of time to provide a constant current. As shown in FIG. 5 which shows the waveforms of the circuit, the gates of Q D1  ˜Q D4  are sequentially connected to V s  by AND 1  ˜AND 4  and SW 1  ˜SW 4  consisting of a kind of CMOS inverter by applying sequentially φ 1  ˜φ 4  so as to drive the driver MOS transistors QD 1  ˜QD 4 . In this manner, drivability is increased with the passage of time to provide a constant current. Thereafter, the comparator CMP detects the arrival of V o  at V CL  in the same way as in FIG. 1 and the driver MOS transistors QD 1  ˜QD 4  are turned OFF to stop the operation. In this manner, the data line voltage is set substantially to V CL . 
     According to this embodiment, the current i can be kept substantially constant during the entire period of operation by selecting a suitable gate width value for each of the driver MOS transistors Q D1  ˜Q D4 . Incidentally each driver MOS transistor Q D1  ˜Q D4  has originally the current mirror structure, the output current it can be kept constant and the influence of the fluctuation of fabrication process, and the like, can be minimized. 
     [Embodiment 3] 
     FIG. 6 shows the third embodiment of the present invention which is further suitable for keeping constant the current i. In this embodiment, the operation is made by the internally supplied voltage obtained by converting an externally supplied power source voltage V cc , e.g. 5 V, to a predetermined voltage, e.g., V cc2  of 4.5 V, by use of a voltage converter disposed inside the chip. 
     The voltage convertor VPS of this embodiment is constituted by the circuit described, for example, in Papers of Institute of Electronics, Information and Communication Engineers of Japan, Div. 2, item 244. This circuit is characterized by including a comparator CMP2 for comparing the output voltage V cc2  with a comparison voltage V CL2  (4.5 V) so that the current flowing through an MOS transistor Q v  can be controlled by applying the output voltage of the comparator CMP2 to the gate of this transistor Q v  and negative feedback is effected in order to keep the output voltage V cc2  equal to V CL2 . Incidentally, the current source S v  represented by dash line in the drawing is a bias current for keeping accurately constant the output voltage V cc2  even when DRV is OFF and the output current of VPS is zero. This may be disposed or need not be disposed, depending on the intended application. It is also possible to employ the system wherein the current iv is caused to flow in synchronism with the operation of DRV when DRV is OFF, for example, and is made zero when DRV is ON. 
     In accordance with this embodiment, since DRV operates always at the constant current V cc2 , the output current of DRV can be kept constant irrespective of the fluctuation of the power source voltage. Various modifications can be made for the VPS circuit besides the circuit shown in this embodiment, and the voltage convertors disclosed, for example, in JPA Nos. 58-70482, 59-111514, U.S. Pat. No. 4,482,985, and the like, can be used as such. Therefore, refer to these prior art references for the detail of the VPS circuit. 
     [Embodiment 4] 
     FIG. 7 shows the fourth embodiment of the present invention wherein the embodiment shown in FIG. 6 is applied to the embodiment shown in FIG. 4. This embodiment can keep constant the output current i irrespective of the fluctuation of the power source voltage V cc  and without any influences of the fluctuation of the operation region of the MOS transistors. 
     [Embodiment 5] 
     FIG. 8 shows the fifth embodiment of the present invention. In the embodiment shown in FIG. 6, V cc2  is set to a desired data line voltage, e.g. 4 V, in this embodiment so that the function of DRV as the voltage limiter is borne by VPS and DRV is caused to operate only as the current limiter. Therefore, the components or portions inside DRV necessary for voltage setting such as the voltage comparator (CMP 1 in FIG. 7) are removed. 
     In accordance with this embodiment, the data line voltage and the current at the time of charging are controlled by VPS and DRV, respectively. For this reason, this embodiment can keep constant the output current i without any influence of the fluctuation of the power source voltage V cc  in the same way as the third embodiment shown in FIG. 6 but by use of the more simplified circuit construction. 
     [Embodiment 6] 
     FIG. 9 shows the sixth embodiment of the present invention. In the fourth embodiment of the invention shown in FIG. 7, V cc  is set to a desired data line voltage, e.g. 4 V, in this embodiment and the voltage is limited by VPS to remove the voltage limiter function of DRV in the same way as the fifth embodiment described above. This embodiment, too, can keep the output current constant without being affected by the influences of the power source voltage and the operation region of the MOS transistors by the more simplified circuit in the same way as in the embodiment described above. 
     [Embodiment 7] 
     Next, the seventh embodiment of the invention, which is suitable for turning ON and OFF the current mirror circuits shown in FIGS. 1, 4 and 6 to 9 at a high speed, will be explained with reference to FIG. 10. 
     As described already, the data line capacitance to be charged is as great as from 500 to 1,000 pF in a 1-mega bit DRAM, for example. Therefore, the gate 17 width of MOS Q D  (shown in FIGS. 1, 6, 8) or Q D1  ˜Q D4  (shown in FIGS. 4, 7, 9) becomes extremely great. If the gates of these MOS transistors are connected directly to the constant current source, the excessive discharge current of the gate capacitance of each MOS flows into the constant current source and the normal operation becomes difficult because the value V s   fluctuates drastically. 
     To solve this problem, the embodiment shown in FIG. 10 is equipped with a current amplification circuit consisting of p-channel MOS transistors Q 4  through Q 6 . 
     In the drawing, the transistor Q 4  inserted between Q o  and the constant current source generates a voltage V s  -|V T  | and the value V s  is outputted to the source of Q 5  using this voltage as the gate voltage. Here, the transistor Q 6  provides the operation current of Q 5 . The source voltage of Q 5  is applied to the gates of the MOS transistors Q D1  through Q D4  through the CMOS invertor. In other words, V cc  is applied to the gates of Q D1  ˜Q D4  when φ 1  ˜φ 4  are at the low potential and the transistors are OFF. When φ 1  is at the high potential, Q 11  is OFF while Q 21  is ON, so that V s  is applied to Q D1  through Q 21 . As a result, Q D1  is turned ON and the charging operation of the data lines is started. Though the discharge current of the gate capacitance C G1  of Q D1   flows into Q 5  at this moment, the fluctuation of the source voltage or the fluctuation of V s  can be reduced by setting the gate width of Q 5  to a large value. Q D2  ˜Q D4  are actuated in the same way. According to this embodiment, the current mirror circuit can be actuated at a high speed without affecting at all the constant current source. Since the current I G  flows only at the time of discharge of C G1 , consumed power can be reduced, too, by designing the current i s  of the constant current source and the current flowing through Q 6  to small values. Incidentally, in order to further improve controllability of the fluctuation of the fabrication condition, it is possible to employ a construction wherein a plurality of MOS transistors Q 3  are further connected in series in the current mirror circuit. 
     The embodiment described above illustrates an example for obtaining the constant current by the combination with the voltage limiter using the comparator. When the voltage limiter is not used (where the output loop of the comparator does not exist), too, control of the mirror circuit can be made by use of the input pulse φ such as the DRV in the embodiments shown in FIGS. 8 and 9 so that the constant current can be obtained, too. A circuit using known bipolar transistors can be used suitably as the constant current source. It is of course possible to use the later-appearing improved constant circuit. Since the output V o  can be brought closer unlimitedly to V CL  with a faster response time of the output V o , it is possible from time to time to constitute the comparator by use of those bipolar transistors which are suitable for a high speed operation. A circuit such as DRV2 shown in FIG. 11 can be used for driving the common drive line Cl2 of the sense amplifier consisting of nMOSTs. In this manner, the charge waveform and the discharge waveform can be controlled arbitrarily. If both waveforms are made completely complementary to each other, the noise coupled from the data lines to other conductors (e.g. the Si substrate, the word lines, etc.) can be offset completely and a memory having a broad operation margin can be designed. 
     [Embodiment 8] 
     The application of the present invention is not particularly limited to the application of the data line charge circuit of DRAM but can be employed effectively as the counter-measure for the peak current when applied to the data output portion of all the memories having a multi-bit structure (where a plurality of data outputs are produced from one chip) where the peak current becomes a particular problem or to the address output portion or data output portion of microcomputers, and the like. FIG. 11 shows an example of such an application, wherein the load capacitance CL outside the chip is driven at a constant voltage and a constant current to reduce the peak current. Namely, the voltage and current are limited by use of VPS and DRV shown in FIG. 8 at the rise of the output, while the current is limited by DRV2 having exactly the complementary voltage relation inside DRV and complementary MOS transistors at the fall of the output. This DRV2, too, operates in exactly the same way as DRV1 with the exception that the potential relationship is opposite. In other words, Q 32  and Q D2  together constitute a current mirror circuit and this current mirror circuit is controlled by a kind of inverter consisting of transistors Q p2  and Q n2  in the same way as described already. When Q p2  is ON and Q n2  is OFF, the current mirror circuit is formed between the transistor Q 32 , the constant current source S 2  (i 2  /n 2 ) and the output driving transistor Q.sub. D and when Q pl  is OFF and Q n1  is ON, Q D2  is OFF. The ON current of Q D2  becomes a constant current i 2  if the current value of the current source inside the current mirror circuit is i 2  /n 2 , the gate width of MOST is w 2  /n 2  and the gate width of Q D2  is W 2 . Even when the value w 2  or the gate length or the threshold voltage of the transistor changes due to the fluctuation of the fabrication process, the driving current of Q D2  becomes substantially constant if the ratio i 2  /n 2  is kept constant. Here, the constant current source is set to i 2  /n 2 , w 2  /n 2  in order to reduce consumed current and the occupying area. Preferably, n 2  has a large value. 
     In VPS of this embodiment, V CL3  is 3.3 V and the output V cc3  is 3.3 V, too, for the following reason. Namely, assuming the case where IC or LSI of the next stage which operates using, as its input, the outputs Out 1˜Out k of the chip operates at the known TTL interface level, these voltages are set to substantially the lowest level which is permissible as the highest potential level, in order to restrict the charge/discharge current of the load capacitance. Therefore, the values should be set in accordance with the intended application and should not be limited to this embodiment, in particular. 
     In this embodiment, when φ generated by the circuit inside the chip is at the high potential, DRV1 is ON and DRV2 is OFF and when φ is at the low potential, DRV1 is OFF and DRV2 is ON so that the constant current i 2  flows from the load towards the ground inside the chip. Therefore, when φ changes from the low potential to the high potential (as represented by solid line in the drawing), DRV1 is ON and CL is charged by the constant current i 1  and when the high potential of the output reaches 3.3 V, i 1  becomes 0. When φ changes from the high potential to the low potential (as represented by dash line in the drawing), DRV2 is ON and CL is discharged from 3.3 V towards 0 V by the constant current i 2 . 
     In accordance with this embodiment, charge/discharge of the load capacitance is effected by the constant current so that CU can be driven at a high speed without increasing the peak current 
     In this embodiment, driver circuits DRV1 and DRV2 of the foregoing embodiments can be employed properly in accordance with the intended applications For example, it is possible to accomplish further a constant current by use of a system which drives by a multi-layered pulse such as shown in FIGS. 4, 7 and 9. Though V cc3  is set to 3.3 V in VPS, it can be set to other arbitrary values. Alternatively, it is possible to directly drive VPS by V cc  to increase the output voltage. 
     The peak current can be reduced further by disposing a circuit similar to VPS on the low potential side to increase the low potential of the output above 0 V and to reduce the output amplitude. Moreover, the relation of the operation voltage of each circuit inside the chip can be set arbitrarily. For example, it is possible to operate each circuit inside the chip and the output stage at the same low voltage V cc3  in order to reduce the power and the peak current, as well. Alternatively, it is possible to operate only the output stage at the low voltage so as to reduce the charge/discharge current of the output load capacitance. It may be possible further to operate the internal circuit by V cc2  and the output stage by V cc  in the manner quite opposite to the above. 
     Though this embodiment employs the circuit construction wherein DRV1 and DRV2 are operated by the same pulse and any one of them is always ON. However, it is also possible to drive them by separate pulses, respectively, so as to turn one of them ON and to output a high or low potential output, or to employ a so-called &#34;3-level output type&#34; driver circuit wherein both of them are turned OFF and the output is under the floating condition. Though this embodiment explains the case where the external load capacitance is driven, it can be applied as such to the case where a large load capacitance inside the chip is driven. Though this embodiment represents the case where constant current driving is effected for both charge and discharge, only one of them can be driven by the constant current. Though DRV1 or DRV2 is constituted primarily by MOS transistors in this embodiment, it is possible to constitute the current mirror circuit by use of bipolar transistors. In such a case, it is possible to obtain better constant current characteristics and high speed driving characteristics. 
     [Embodiment 9] 
     FIG. 12 shows the ninth embodiment of the present invention wherein the transistor constituting the current mirror consists of a plurality of MOS transistors Q 3  and Q 4 . Since this embodiment can reduce the gate voltage of Q D , a higher output power current can be produced by reducing the size of Q D . 
     FIG. 13 shows a definite example of the constant current source S. This example consists of NPN bipolar transistors Q B1 , Q B2  and resistors R 1  to R 4 , and its operation will be explained. The base-emitter voltage V BE  (ordinarily, 0.8 V) of Q B2  appears at the node 11 and this voltage and R 3  determines the current flowing through R 2  and the voltage value at the node 10, as well. The voltage drop of V BE  at the node 10 appears at the node 12 and this voltage and R 4  determines the current is It will now be assumed that R 1  =10 Kohms, R 2  =4 Kohms, R 3  =8 Kohms and R 4  =4 Kohms. Then, V BE  =0.8 V appears at the node 11. The current flowing through R 2  and R 3  becomes 0.8 V/8 Kohms=0.1 mA and the voltage value at the node 10 is 0.8 V +4 Kohms ×0.1 mA=1.2 V. The voltage at the node 12 is 1.2 V-0.8 V=0.4 V and the current is 0.4 V/4 Kohms=0.1 mA. 
     [Embodiment 10] 
     Since the ninth embodiment of the invention described above can utilize V BE  of the bipolar transistors which hardly fluctuate between wafers and between lots, the influences of the fabrication process and the change of the power source voltage V cc  are small. Since the voltage at the node 10 is determined by the ratio of resistance between R 2  and R 3 , the constant current source becomes extremely stable without being affected by the fluctuation of the fabrication process. Even in the current mirror circuits incorporating therein such an extremely stable constant current source, MOST Q D  shown in FIGS. 1 and 2 is preferably operated in the saturation region (|V o  -V cc  |&gt;|V s  -V cc  -V T  |) in order to charge the data lines by the constant current. However, as shown in FIG. 3, this requirement cannot be satisfied with the passage of time depending on the operation conditions. In other words, if the potential of V o  rises from V CL  /2 and becomes higher than the voltage V s  -V T . (where V T  is the threshold voltage of Q D  and has generally a negative value because Q D  is of the P-channel type), the relation becomes as |V o  -V cc  |&lt;|V s  -V cc  -V T  | and the MOS Q D  operates in the non-saturation region. As a result, the current i becomes small and the time necessary for V o  to reach V DL  (4 V) becomes long. This tendency becomes all the more remarkable when the power source voltage V cc  is as low as 4.4 V, the channel length L g  of Q D  is greater than the standard value and V t  is high. If the power source voltage V cc  is high, the channel length L g  is smaller than the standard value and the threshold voltage V t  is low, Q D  operates in the saturation region but the time becomes faster than the necessary time and the peak current increases due to the drain-source voltage dependence of the drain current, and the like. This problem is likely to develop particularly in the embodiment shown in FIG. 12. Therefore, the current value i.sub. of the current source S is increased when the channel length L g  is greater than the standard value and the threshold voltage V t  is high, and is decreased when L g  is smaller and V t   is low, as shown in FIG. 14. The problem described above can be solved by further making a control in such a fashion that the current value becomes smaller with the higher power source voltage V cc . 
     FIG. 15 shows an example of such an embodiment. It consists of a detection circuit VD for detecting the power source voltage V cc , the channel length L g  and the threshold voltage V t  and a current source CS which receives the output signal 100 of the detection circuit VD and outputs the current i s . When the power source voltage V cc , the channel length L g  and the threshold voltage V t  change, the detection circuit VD for them controls the voltage value or current value of its output 100 to control CS and hence, i s . When, for example, the power source voltage V cc  is high, the channel length L g  is smaller than the standard value and the threshold voltage V t  becomes low, the voltage or current value of the output 100 is reduced to reduce i s , and i s  is increased when the condition is contrary. 
     According to this embodiment, it is possible to charge the data lines by the optimum current in conformity with the change of the power source voltage V cc  or the fluctuation of the fabrication process of the channel length L g  or the threshold voltage. Therefore, it is possible to reduce the peak current or to speed up the operation at the same peak current. 
     [Embodiment 11] 
     FIG. 16 shows the eleventh embodiment of the present invention. This embodiment comprises VD consisting of a constant voltage circuit V L , a P-channel MOS Q 100  and an N-channel MOS Q 101  and CS consisting of an NPN bipolar transistor Q B10  and a resistor R 10 . The constant voltage circuit VL is of the type which uses the afore-mentioned voltage limiter circuit system and provides a constant output voltage V DL  even when the power source voltage changes. Its operation is as follows. The ratio of drivability between Q 100  and Q 101  determines the voltage value of the node 100 and the balance between this voltage and the base emitter voltage V BE  (0.8 V) of Q B10  appears at the anode 101. This value and R 10  determines the current i s . Assuming that V cc  =V CL  =4 V and the ratio of drivability of Q100 and Q101 is 1:1, the node 100 is 2 V and the node is 2 V-0.8 V=1.2 V. If R 10  is Kohms, i s  =1.2 V/12 Kohms=0.1 mA. 
     Under such a circuit connection, if the power source voltage V cc  changes, the gate voltage of Q 101  changes, too, and drivability changes. When V cc  becomes high, drivability becomes high and the voltage value at the node 100 drops. When V cc  drops, drivability of Q 101  drops and the voltage at the node 100 becomes high. As a result, when V cc  is high, it is possible to reduce i s  and when the former is low, the latter can be increased. 
     According to this embodiment, the value of the current i s  can be set freely by the ratio of drivability between Q 100  and Q 101  and the resistance value of R 10  Furthermore, when the power source voltage is high, the current value of i s  can be reduced and when the former is low, the latter can be increased. As a result, it is possible to prevent the charging time of the data lines from becoming unnecessarily fast and the peak current from increasing. 
     FIG. 17 shows the embodiment which illustrates definitely the constant voltage circuit VL shown in FIG. 16. VL consists of a P-channel MOS Q 102  and NPN bipolar transistors Q B11  ˜Q B15 . The operation of this circuit is as follows. When V cc  is supplied and the voltage rises, V CL  rises, too, through Q 102 . When the voltage value of V CL  reaches 0.8 V×5 (V BE  of Q B11  ˜Q B15 )=4 V, Q B11  ˜Q B15  become conductive and the rise of V CL  stops and limited to the constant voltage 4 V. The other operations are the same as those of FIG. 16. 
     This embodiment illustrates definitely the constant voltage circuit. 
     [Embodiment 12] 
     FIG. 18 shows the twelfth embodiment of the present invention when is formed by adding P-channel MOS Q 103 , NPN bipolar transistors Q B1  ˜Q B2  and resistors R 1  ˜R 4  to the circuit shown in FIG. 16. The circuit constituted by Q B1 , Q B2  and R 1  ˜R 4  is the same constant current power source circuit as one shown in FIG. 13 and its operation is also the same. In this embodiment, the voltage value of the node 102 is determined by drivability of Q 103  and the current of the constant current source. Since the current of the constant current source does not have V cc  dependence, this voltage value changes while following up V cc . Furthermore, it can be changed by the fluctuation of the fabrication process of L g  and V t  of Q 102 . In other words, when L g  is smaller than the standard value and V t  is low, drivability of Q 103  becomes great and the voltage value of the node 102 becomes high. It becomes low in the opposite case. The voltage of this node 102 is inputted to the gate of Q 101  and operates in the same way as in FIG. 17. 
     This embodiment can control not only the current value i s  with the change of the power source voltage in the same way as in FIG. 16 but can control also the current i s  with respect to the fluctuation of the fabrication process of L g  and V t , and the data lines can therefore be charged more stably. 
     [Embodiment 13] 
     FIG. 13 shows the thirteenth embodiment of the present invention. This embodiment comprises VD consisting of a constant voltage circuit VL and MOS Q 100  ˜Q 106 , Q B16  and R 11 , and CS consisting of Q 107 . The operations of VL, Q 100 , Q 101 , Q B10  and R 11  are the same as those of FIG. 17. In other words, when the power source voltage V cc  becomes high, the value of the current flowing through the node 103 becomes small and when the former becomes low, the latter becomes great. The current source and transistors Q 104 , Q 105  together constitute the current mirror circuit and a current which is the product of the current flowing through the node 103 by drivability of Q 105  (effective gate width/effective gate length)/drivability of Q 104  flows through the node 100. The output current i s  is controlled by the second current mirror circuit consisting of Q 106  and Q 107 . In this case, if the channel length L g  of Q 105  is designed to such a great level that the fluctuation of the fabrication process can be neglected, it is possible to reflect the fluctuation of the fabrication process of Q 104  on the current value flowing through the node 100. In other words, if L g  of Q 104  is small and V t  is low, drivability of Q 104  becomes great and the voltage of the node 103 becomes high. If L g  is smaller than the standard value and V t  is high, on the contrary, the voltage of the node 103 becomes low. Since the gate length of Q 105  is designed to a level at which the fluctuation of their fabrication process can be neglated, the current of the node 100 is small in the former case and great in the latter and the same effect as FIG. 18 can be obtained. Needless to say, the same effect can be obtained likewise by increasing the gate length of Q 107 . 
     This embodiment provides the same effect as in FIGS. 15 and 18. 
     [Embodiment 14] 
     FIG. 20 shows the fourteenth embodiment of the present invention wherein Q 108 , Q B17 , Q 110  and R 10  are added in place of Q 106  and Q 107  of FIG. 19. Only the other difference from FIG. 19 is that L g  of Q 105  is equal to that of Q 104 . The voltage of the node 100 is determined by V t  of Q 108 , V BE  of Q B17  and drivability of Q 105 . It will be assumed hereby that both L g  and V t  are the standard values and V cc , too, is the standard value of 5 V. Then, the ratio of drivability of Q 105 , Q 108  and Q B17  is determined so that only the sum voltage of V t  of Q 108  and V BE  of Q B17  is outputted to the node 100 at this time. The voltage of the node 101 in this case is V t  of Q 108  because V BE  is cancelled, and this V.sub. t and R 10  determine i s . When the power source voltage V cc  drops, for example, the current flowing through the node 103 becomes great as described in the tenth embodiment and the current flowing through Q 105  forming the current mirror circuit becomes great, too. As a result, the voltage of the node 100 becomes high and i s  becomes great. When V cc  becomes high, is becomes small, on the contrary. The fluctuation of the fabrication process of V t  of Q 108  becomes as such the voltage of the node 101. Namely, the current i s  becomes small when the value L g  is smaller than the standard value and V t  is low, and becomes great in the opposite case. 
     This embodiment provides the same effect as the effect shown in FIG. 19. 
     [Embodiment 15] 
     FIG. 21 shows the fifteenth embodiment of the present invention, wherein the circuits consisting of MOS transistors Q AA , Q BB , Q CC  and Q DD  are connected subsidiary to one another in three stages. The transistor constant of each stage is designed to be the same. The circuit operation is as follows. First of all, a very small predetermined current i 1 , which slightly turns ON the four series P-channel MOS transistors, is caused to flow. Then, the drain source of each MOS transistor is biased to a voltage approximate to its threshold voltage Since the gate length of Q CC1  is set to the same value as that of the output transistor Q D  of the current mirror, the threshold voltage, too, becomes equal to the threshold voltage V t  of Q D . Therefore, an about 4 V voltage is applied across the gate and source of the P-channel MOS transistor Q AA2 . Since the gate length is set to a great value in the same way as in Q AA2  and Q AA1  in order to reduce the change of characteristics due to the fluctuation of the fabrication process, the current i 2  of Q AA2  is dependent on V t . In other words, when V t  is high, i 2  becomes great and when V t  is low, the current i 2  becomes small, too. This current i 2  is transmitted, as the current i 2  &#39; of the series transistor Q CC2  of the next stage, by the current mirror circuit consisting of N-channel transistors Q BB2  and Q DD2 , and the same operation as described above is repeated Accordingly, V t  dependence of the current i.sub. becomes further great. This current is transmitted to the output terminal by the current mirror circuit consisting of Q BB3  and Q DD3 . As a result, when the threshold voltage V t  of the output transistor becomes high, the current i s  becomes great and when V t  drops, on the contrary, the current i s  becomes small, thereby providing desired current characteristics. In this manner, the problem of the drop of the output current i in the operation region of MOS transistors can be mitigated. 
     The foregoing embodiments illustrate the embodiments wherein the current is made constant by the combination with the voltage limiter using the comparator. However, when the voltage limiter is not used (where the output loop of the comparator does not exist), the mirror circuit can be controlled by the input pulse φ so that the current can be made constant Since the output voltage V o  can be made unlimitedly close to V CL  by making the response time of the comparator faster than that of the output V o , the comparator can be constituted by use of bipolar transistors suitable for a high speed operation, depending upon the intended application. The concept of the present invention can be applied to driving of the common driving line CL2 of the sense amplifier constituted by n-MOS transistors, and the charging waveform and discharging waveform can be controlled arbitrarily by so doing. If both of these waveforms are made completely complementary to each other, the noise coupling with other conductors (such as the Si substrate and the word lines) from the data lines can be offset completely and a memory having a broad operation margin can be designed. 
     Furthermore, the present invention is not particularly limited to the application to the data line charge circuit of DRAM but can be used effectively as the counter-measure for the peak current when applied to the data output portions of all the memories having a multi-bit structure (the structure wherein a plurality of data outputs are outputted from one chip) or the address output portion of microcomputers where the peak current becomes a problem, in particular. 
     The charge/discharge current, that has been left as such conventionally, can be controlled arbitrarily in accordance with the present invention by controlling the current value of the constant current source of the current mirror circuit as described above. Therefore, the noise inside the LSI chip can be reduced, chip design can be made more easily and the noise from the chip mounted actually onto a card can be reduced on the user side so that card design can be made more easily, too. Since the output pulse of a low and constant voltage can be obtained, the consumed power of the chip can be reduced, too. 
     It is further understood by those skilled in the art that the foregoing description is the preferred embodiments of the disclosed invention and that various changes and modifications may be made in the invention without departing from the spirit and scope thereof.