Abstract:
A built in self test (BIST) system for a storage controller comprises a processor, a test access port (TAP) controller that communicates with a TAP interface that is external to the storage controller, and a BIST controller that selectively performs a BIST based on information received from each of the processor and the TAP controller.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is a continuation Application of U.S. patent application Ser. No. 10/983,944 filed on Nov. 8, 2004. The disclosure of the above application is incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention relates to integrated circuits, and more particularly, to conducting built in self-test “BIST” operations for memory modules.  
       BACKGROUND  
       [0003]     Conventional computer systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and storage devices (for example, tape drives, disk drives; referred to herein as a “storage device”).  
         [0004]     In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system.  
         [0005]     The storage device is coupled to the host system via a storage device controller that handles complex details of interfacing the storage device(s) to the host system. Communications between the host system and the controller is usually provided using one of a variety of standard input/output (“I/O”) bus interfaces.  
         [0006]     Storage controllers are coupled using various standards, for example, the fibre channel standard incorporated herein by reference in its entirety.  
         [0007]     Storage controllers use various processors and memory units (or modules) for storing data/program instructions. For efficient and reliable transfer of data it is important to perform a BIST operation for memory units. Typically, a memory BIST controller is used to perform the BIST. A test access port (“TAP”) controller described below may be used to initiate the memory BIST controller itself.  
         [0008]     An industry standard, IEEE 11491.1 and 11491A (referred to as the JTAG standard) is often used for testing integrated circuits after assembly onto a printed circuit board. The JTAG standard is incorporated herein by reference in its entirety. Testing is performed using pins/interface associated with a test access port.  
         [0009]     Testing of memory modules within a storage controller becomes a problem when the storage controller is mounted on a dense printed circuit board and there may not be enough room for a TAP interface. Even if there is room for a TAP interface, adding a TAP interface increases the overall board cost.  
         [0010]     This problem is further magnified, when the storage controller is placed inside a rack or an enclosed environment. In this case getting access to the TAP interface is difficult without altering or tampering the enclosed environment.  
         [0011]     Therefore, there is a need for a method and system for efficiently performing BIST for memory units in a storage controller or other similar environments.  
       SUMMARY OF THE INVENTION  
       [0012]     In one aspect of the present invention, a method for initiating a built in self test (“BIST”) operation for memory modules is provided. The method includes, determining if a test access port (“TAP”) controller instruction or an internal register control bit are to be used for initiating the BIST operation; sending the internal register control bit to a memory BIST controller for initiating the BIST operation; and setting a status bit in the internal register after the BIST operation is complete.  
         [0013]     The method also includes sending the TAP instruction to the memory BIST controller; and providing access to a BIST operation result via a TAP interface. The internal register is also used to set a bit that selects between the TAP instruction and the internal register control bit for initiating the BIST operation.  
         [0014]     In yet another aspect of the present invention, a system for initiating a BIST operation for memory modules is provided. The system includes, an internal register for setting a control bit for initiating a BIST operation; a TAP controller for sending an instruction to a memory BIST controller to initiate a BIST operation; and a multiplexer for selecting between the control bit and the instruction for initiating the BIST operation.  
         [0015]     If the control bit is used to initiate the BIST operation then a status bit is set in the internal register notifying a processor that the BIST operation is complete; and if the instruction is used to initiate the BIST operation, then a test result is accessible via a TAP interface.  
         [0016]     In yet another aspect of the present invention, a storage controller for initiating a BIST operation for memory modules is provided. The storage controller includes an internal register for setting a control bit for initiating a BIST operation; a TAP controller for sending an instruction to a memory BIST controller to initiate a BIST operation; and a multiplexer for selecting between the control bit and the instruction for initiating the BIST operation.  
         [0017]     This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof in connection with the attached drawings.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]     The foregoing features and other features of the present invention will now be described with reference to the drawings of a preferred embodiment. In the drawings, the same components have the same reference numerals. The illustrated embodiment is intended to illustrate, but not to limit the invention. The drawings include the following Figures:  
         [0019]      FIG. 1A  is a block diagram of a controller, used according to one aspect of the present invention;  
         [0020]      FIG. 1B  shows a block diagram where a TAP controller controls the BIST operation;  
         [0021]      FIG. 2  shows a dual mode BIST control block diagram, according to one aspect of the present invention; and  
         [0022]      FIG. 3  shows a process flow diagram for conducting a BIST, according to one aspect of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0023]     To facilitate an understanding of the preferred embodiment, the general architecture and operation of a controller will initially be described. The specific architecture and operation of the preferred embodiment will then be described with reference to the general architecture.  
         [0024]     System  100 A of  FIG. 1A  is an example of a storage system controller, included (or coupled to) in a computer system. The host computer (not shown) and a storage device  115  communicate via port  113 . In an alternate embodiment (not shown), the storage device  115  is an external storage device, which is connected to the host computer via a data bus. Those skilled in the art will appreciate that various communication buses known in the art can be used to transfer data between the drive and the host system.  
         [0025]     As shown in  FIG. 1A , the system includes controller  101 , which is coupled to fibre channel ports  102  and  103 , buffer memory  114  and microprocessor  100 . Interface  116  serves to couple microprocessor bus  107  to microprocessor  100 . A read only memory (“ROM”) omitted from the drawing is used to store firmware code executed by microprocessor  100 .  
         [0026]     Controller  101  can be an integrated circuit (IC) that comprises of various functional modules, which provide for the writing and reading of data stored on storage device  115  or to other devices through fibre channel ports  102  and  103 .  
         [0027]     Microprocessor  100  is coupled to controller  101  via interface  116  to facilitate transfer of data, address, timing and control information. Buffer memory  114  is coupled to controller  101  via ports to facilitate transfer of data, timing and address information.  
         [0028]     Data flow controller  117  is connected to microprocessor bus  107  and to buffer controller  118 . Disk formatter  110  formats data that is flowing through system  100 A, either from storage device  115  or from fibre channel ports  102 / 103 .  
         [0029]     Fibre channel controllers (“A”)  104  and (“B”)  108  include programmable registers and state machine sequencers that interface with ports  102  and  103 . The fibre channel controllers  104  and  108  provide fibre channel control for ports  102  and  103 .  
         [0030]     Microcontrollers (“A”)  105  and (“B”)  106  allow customization of fibre channel sequences and control Fibre channel controllers  104  and  108  through a microcontroller interface module (not shown). ECC engine  111  provides error correction for system  100 A.  
         [0031]     Various memory modules exists in controller  101 , for example, memory  105 A,  106 A and  118 A.  
         [0032]     TAP controller  119 , described in more detail below, is used to control the BIST operation for various memory modules. Information from TAP controller  119  maybe sent via TAP interface (“TAP I/F”)  120  and accessed outside system  100 A. As discussed above, in some systems TAP I/F  120  may not be available and hence it becomes difficult to perform the BIST tests.  
         [0033]     The adaptive aspects of the present invention, allow storage controller  101  to perform the BIST in dual modes. In a first mode, as shown in  FIG. 1B , if the TAP I/F  120  is present and detected by controller  101 , the BIST may be performed so that BIST results are accessible via TAP I/F  120 . In another mode, as shown in  FIG. 2 , internal register bits are used to initiate the BIST operation and the results are accessible to processor  100  via register reads. The modes may be programmed by firmware using an internal configuration register  116 A.  
         [0034]      FIG. 1B  shows tap controller  119  coupled to a memory controller  105 B that controls the BIST operation for memory  105 A. Instructions  116 G from TAP controller  119  are sent to memory BIST controller  105 B and after the test is performed, the results  116 H are sent to TAP controller  119 . The results  116 H may be accessed by a system external to storage controller  101  via TAP I/F  120 .  
         [0035]      FIG. 2  shows a block diagram where the BIST operation is initiated by using internal register commands. Internal register  116 B includes control bits that are used to trigger a BIST operation. Processor  100  may set the control bits. Control bits  116 F (also shown as  116 D) are sent to BIST controller  105 B via a multiplexer (“Mux”)  116 C. Mux  116 C also receives instructions  116 G from TAP controller  119 . Instructions  116 G may be selected to initiate a BIST operation (as shown in  FIG. 1B ) based on firmware programming.  
         [0036]     Memory BIST controller  105 B starts and controls the BIST operation for memory  105 A. The results  116 H are sent to register  116 A with status bits  116 E. The status bits  116 E may be used to generate an interrupt for processor  100 . This notifies processor  100  that BIST results are available. Results  116 H may also be made available via TAP interface  120 .  
         [0037]     It is noteworthy that although  FIG. 2  shows two registers  116 A and  116 B, only a single register may be used to initiate the BIST operation described above with respect to  FIG. 2  and below with respect to  FIG. 3 .  
         [0038]      FIG. 3  shows a process flow diagram for conducting a BIST operation, according to one aspect of the present invention. Turning in detail to  FIG. 3 , in step S 300 , the BIST process is started. In step S 302 , the process determines whether to use the TAP controller  119  (as shown in  FIG. 1B ) or an internal register value, as shown in  FIG. 2 , to initiate the BIST operation.  
         [0039]     If the TAP controller  119  is used, then in step S 310 , standard TAP controller  119  instructions ( 116 G) are used to initiate the BIST operation. The test results may be accessed in step S 312  using TAP interface  120 .  
         [0040]     If register control bits are used (step S 302 ), then in step S 304 , control bits are set in internal register  116 B. In step S 306 , control bits  116 F are used to activate memory BIST controller  105 B (shown as  116 D via Mux  116 C). In step S 308 , after the test is completed status bits  116 E are set in register  116 A so that processor  100  may be notified of test completion and provide access to the test results.  
         [0041]     In one aspect of the present invention, a user can use the internal register technique to initiate a BIST operation and hence no TAP Interface  120  is required. In another aspect of the present invention, a user has the flexibility of initiating a BIST operation either by using TAP controller instructions or internal register control bits.  
         [0042]     Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and not limiting. Many other applications and embodiments of the present invention will be apparent in light of this disclosure.