Abstract:
A device includes a first dielectric layer having at least one conductive feature embedded therein. A first plurality of conductive lines are embedded in a second dielectric layer disposed above the first dielectric layer. A first conductive line in the first plurality of conductive lines contacts the conductive feature and includes a conductive via portion and a recessed line portion. A second plurality of conductive lines are embedded in a third dielectric layer disposed above the second dielectric layer. A second conductive line in the second plurality of conductive lines contacts the conductive via portion and the conductive via portion has a first cross-sectional dimension corresponding to a width of the first conductive line and a second cross-sectional dimension corresponding to a width of the second conductive line.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present disclosure generally relates to the fabrication of semiconductor devices, and, more particularly, to a self-aligned process flow for forming vias. 
         [0003]    2. Description of the Related Art 
         [0004]    In modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby steadily increasing performance of these circuits in terms of speed and/or power consumption and/or diversity of circuit functions. As the size of the individual circuit elements is significantly reduced, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines and the spaces between the metal lines have to be reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit area. 
         [0005]    In such modern integrated circuits, a limiting factor of device performance is the signal propagation delay caused by the switching speed of the transistor elements. As the channel length of these transistor elements has now reached 50 nm and less, the signal propagation delay is no longer limited by the field effect transistors. Rather, the signal propagation delay is limited, owing to the increased circuit density, by the interconnect lines, since the line-to-line capacitance (C) is increased and also the resistance (R) of the lines is increased due to their reduced cross-sectional area. The parasitic RC time constants and the capacitive coupling between neighboring metal lines, therefore, require the introduction of a new type of material for forming the metallization layers. 
         [0006]    Traditionally, metallization layers, i.e., the wiring layers including metal lines and vias for providing the electrical connection of the circuit elements according to a specified circuit layout, are formed by embedding copper lines and vias in a dielectric layer stack. For highly sophisticated applications, in addition to using copper and/or copper alloys, the well-established and well-known dielectric materials silicon dioxide (k≈4.2) and silicon nitride (k&gt;7) may increasingly be replaced by so-called low-k dielectric materials having a relative permittivity of approximately 3.0 and less. 
         [0007]    In addition, the continuous reduction of the feature sizes with gate lengths of approximately 40 nm and less may demand for even more reduced dielectric constants of the corresponding dielectric materials. For this reason, it has been proposed to introduce “air gaps,” at least at critical device areas, since air or similar gases may have a dielectric constant of approximately 1.0. 
         [0008]    Process flows for forming air gaps and multiple metallization layers are complex. The formation of the multiple metallization layers often requires the use of cap layers, such as silicon nitride, between the layers. Since the cap layer material has a dielectric constant higher than the low-k dielectric layer, the overall capacitance of the stack is increased, thereby reducing the maximum achievable switching speed. 
         [0009]    The present disclosure is directed to various methods for forming vias and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above. 
       SUMMARY OF THE INVENTION 
       [0010]    The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later. 
         [0011]    Generally, the present disclosure is directed to an interconnect structure. One illustrative device includes, among other things, a first dielectric layer having at least one conductive feature embedded therein. A first plurality of conductive lines are embedded in a second dielectric layer disposed above the first dielectric layer. A first conductive line in the first plurality of conductive lines contacts the conductive feature and includes a conductive via portion and a recessed line portion. A second plurality of conductive lines are embedded in a third dielectric layer disposed above the second dielectric layer. A second conductive line in the second plurality of conductive lines contacts the conductive via portion and the conductive via portion has a first cross-sectional dimension corresponding to a width of the first conductive line and a second cross-sectional dimension corresponding to a width of the second conductive line. 
         [0012]    Another illustrative device includes, among other things, a first plurality of conductive lines embedded in a first dielectric layer. A first conductive line in the first plurality of conductive lines includes a conductive via portion and a recessed line portion. A second plurality of conductive lines are embedded in a second dielectric layer disposed above the first dielectric layer. A second conductive line in the second plurality of conductive lines contacts the conductive via portion and the conductive via portion has a first cross-sectional dimension corresponding to a width of the first conductive line and a second cross-sectional dimension corresponding to a width of the second conductive line. 
         [0013]    Yet another illustrative device includes, among other things, a first dielectric layer having at least one conductive feature embedded therein. A first plurality of conductive lines are embedded in a second low-k dielectric layer disposed above the first dielectric layer. A first conductive line in the first plurality of conductive lines contacts the conductive feature and includes a conductive via portion and a recessed line portion. A second plurality of conductive lines are embedded in a third low-k dielectric layer disposed above the second low-k dielectric layer. The first plurality of conductive lines are perpendicular to the second plurality of conductive lines. A second conductive line in the second plurality of conductive lines contacts the conductive via portion and the conductive via portion has a first cross-sectional dimension corresponding to a width of the first conductive line and a second cross-sectional dimension corresponding to a width of the second conductive line. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]    The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which: 
           [0015]      FIGS. 1A-1M  are cross-sectional views of a device depicting methods disclosed herein for forming vias; and 
           [0016]      FIGS. 2A-2M  are top views of the device corresponding to  FIGS. 1A-1M . 
       
    
    
       [0017]    While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. 
       DETAILED DESCRIPTION 
       [0018]    Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers&#39; specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure. 
         [0019]    The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase. 
         [0020]    The present disclosure generally relates to various methods of forming via structures and the resulting semiconductor devices. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail. 
         [0021]      FIGS. 1A-1M and 2A-2M  illustrate a method for forming vias in a device  100  using a self-aligned process.  FIGS. 1A-1M  show cross-sectional views of the device  100  and  FIGS. 2A-2M  show corresponding top views of the device  100 . The orientation of  FIG. 1A  is indicated by the center line in  FIG. 2A . The device  100  includes a substrate  105 . A dielectric layer  110  is formed above the substrate  105 . The dielectric layer  110  may be part of a device layer  115  in which semiconductor-based circuit elements may be provided. For convenience, any such circuit elements are not shown in  FIG. 1A . The substrate  105  may also include any appropriate microstructure features, such as micromechanical components, optoelectronic components and the like, wherein at least some of these components may require an interconnect structure formed in a metallization system. The device layer  115  includes a simplistically depicted conductive feature  120  (e.g., a contact) formed in the dielectric layer  110  for contacting underlying devices, such as the source/drain regions or the gate structure of a transistor (not shown). In the case of a gate contact, the conductive feature  120  would not extend all the way to the substrate  105 . A dielectric layer  125  is formed above the device layer  115  (e.g., in a Metal 1 (M1) layer). The dielectric layer  125  may be a low-k dielectric material having a dielectric constant of approximately 3.0 or lower or an ultra-low-k (ULK) material having a dielectric constant of approximately 2.5 or lower. In some embodiments, the dielectric layer  125  may be SiOC. Sacrificial lines  130  (e.g., amorphous silicon) with a cap layer  135  (e.g., silicon nitride) are formed in the dielectric layer  125 . The sacrificial lines  130  may be formed by patterning a layer of material (e.g., amorphous silicon) using a patterning process (e.g., self-aligned double patterning (SADP), self-aligned quad patterning (SAQP), or directed self-assembly material patterning), the specifics of which are known to those of ordinary skill in the art. The dielectric layer  125  may be deposited over the sacrificial lines  130  and planarized using the cap layer  135  as an etch stop layer. Due to the aspect ratio of the openings defined between the sacrificial lines  130 , the dielectric layer  125  may not completely fill the openings, resulting in air gaps  137  being formed between the sacrificial lines  130 . 
         [0022]      FIGS. 1B and 2B  illustrate the device  100  after several processes were performed to replace the sacrificial lines  130  with conductive material to define conductive lines  140 . First, one or more etch processes were performed to remove the cap layer  135  and the sacrificial lines  130 , resulting in the formation of recesses or openings in the dielectric layer  125 . Next, one or more deposition processes were performed so as to over-fill the recesses with a conductive material. Then, a planarization process was performed to remove excess conductive material positioned above the dielectric layer  125 . The conductive material may include multiple layers, such as one or more barrier layers (e.g., Ta, TaN, TiN, etc.) (not separately shown) to prevent migration of any metal in the conductive lines  140  into the dielectric layer  125 , a metal seed layer (e.g., copper), and a metal fill material (e.g., copper). 
         [0023]      FIGS. 1C and 2C  illustrate the device  100  after a cap layer  145  (e.g., silicon nitride) was formed above the dielectric layer  125 .  FIGS. 1D and 2D  illustrate the device  100  after several processes were performed to form a hard mask layer  150  (e.g., spin-on hard mask (SOH)) above the cap layer  145  and to pattern the hard mask layer  150  to define an opening  155 . This scheme allows for a dense pattern using a sequence of successive lithography/etch processes into layer  150  using conventional lithography, thereby avoiding the need for more complicated processes, such as EUV lithography. 
         [0024]      FIGS. 1E and 2E  illustrate the device  100  after a sacrificial material  160  (e.g., amorphous carbon, DUO™ (offered commercially by Honeywell, Inc.), or any other material that can be selectively stripped from the material of the conductive lines  140 ) was formed in the opening  155  and the hard mask layer  150  was removed. Although the sacrificial material  160  is illustrated as having completely filled the opening  155 , in some embodiments, the sacrificial material  160  may line the opening  155  without completely filling it. For example, a layer of the sacrificial material may be deposited and anisotropically etched to define spacers on sidewalls of the opening  155  and a bottom layer covering a bottom surface of the opening  155  (as denoted by feature  165  in  FIG. 1E ). 
         [0025]      FIGS. 1F and 2F  illustrate the device  100  after the cap layer  145  is etched using the sacrificial material  160  as an etch mask.  FIGS. 1G and 2G  illustrate the device  100  after a first removal process (e.g., etching or ashing) was performed to remove the sacrificial material  160  and an etch process was performed with the cap layer  145  in position to define recessed conductive lines  140 R and a conductive via portion  140 V. One of the recessed conductive lines  140 A interfaces with the conductive via portion  140 V. The cap layer  145  prevents recessing of the covered portion of the conductive line  140 A thereby resulting in the formation of the conductive via portion  140 V. The lateral width, D 1 , of the conductive via portion  140 V is determined by the width of the sacrificial line  130  and its length is determined by the patterned length of the cap layer  145 . 
         [0026]      FIGS. 1H and 2H  illustrate the device after several processes were performed to form additional dielectric material, such as additional material of the dielectric layer  125 , to cover the recessed conductive lines  140 R,  140 A. For example, a deposition process may be performed, followed by a planarizing process or an etch process to expose the conductive via portion  140 V. This process operation removes the cap layer  145 . 
         [0027]      FIGS. 1I and 2I  illustrate the device  100  after performing a plurality of processes so as to form a second set of sacrificial lines  165  with a cap layer  170  formed thereabove. The orientation of  FIG. 1I  is indicated by the center line in  FIG. 2I . The sacrificial lines  165  are oriented perpendicularly with respect to the sacrificial lines  130  illustrated in  FIG. 1A . The sacrificial lines  165  may be formed by patterning a layer of material (e.g., amorphous silicon) using a patterning process (e.g., self-aligned double patterning (SADP), self-aligned quad patterning (SAQD), or directed self-assembly material patterning), the specifics of which are known to those of ordinary skill in the art. 
         [0028]      FIGS. 1J and 2J  illustrate the device  100  after performing a recess etch on the exposed portions of the conductive via portion  140 V using the sacrificial lines  165  as an etch mask. The recess etch reduces the length, D 2 , of the conductive via portion  140 V corresponding to the width of the sacrificial line  165 . Thus, the horizontal cross-sectional dimensions of the conductive via portion  140 V are defined by the respective widths of the sacrificial line  130  (see  FIG. 1F ) and the perpendicularly orientated sacrificial line  165 . The etching processes for forming the conductive via portion  140 V are self-aligned based on the sacrificial lines  130 ,  165 . 
         [0029]      FIGS. 1K and 2K  illustrate the device  100  after performing an optional recess etch of the dielectric layer  125  using the sacrificial lines  165  as an etch mask. The dielectric recess etch exposes the recessed metal features  140 R and  140 A. In some embodiments, the dielectric recess etch may be performed prior to the conductive material recess etch described in  FIGS. 1J and 2J . In such an embodiment, further recessing of the recessed metal features  140 R would occur in portions not covered by the sacrificial lines  165  during the conductive material recess etch, as they would already be exposed. In some embodiments, the same etch process may be used to recess the conductive via portion  140 V and the dielectric layer  125 , where the etch process is not selective to the conductive material  140  compared to the dielectric layer  125 . 
         [0030]      FIGS. 1L and 2L  illustrate the device  100  after performing a plurality of processes to form a second dielectric layer  175  (e.g., in a Metal 2 (M2) layer). The dielectric layer  175  may be deposited to extend above the sacrificial lines  165  and a planarization process or a recess etch may be performed to remove the portion extending above the sacrificial lines  165 . Due to the aspect ratio of the openings defined between the sacrificial lines  165 , the dielectric layer  175  may not completely fill the openings, resulting in air gaps  180  between the sacrificial lines  165 . The air gaps  180  reduce the capacitance of the device  100 , thereby increasing switching speed, and as a result, performance. The use of the dielectric etch process illustrated in  FIGS. 1K and 2K  increases the size of the air gaps  180 . 
         [0031]      FIGS. 1M and 2M  illustrate the device  100  after several processes were performed to replace the sacrificial lines  165  with conductive material to define conductive lines  185 . First, one or more etch processes were performed to remove the cap layer  170  and the sacrificial lines  165 , resulting in recesses. Next, one or more deposition processes were performed so as to over-fill the recesses with a conductive material. Then, a planarization process was performed to remove excess conductive material. The conductive lines  185  may include multiple layers, such as one or more barrier layers (e.g., Ta, TaN, TiN, etc.) to prevent migration of any metal in the conductive lines  185  into the dielectric layer  175 , a metal seed layer (e.g., copper), and a metal fill material (e.g., copper). One of the conductive lines  185 A interfaces with the conductive via portion  140 V. Thus, the conductive via portion  140 V connects the conductive line  140 A in the M1 layer to the conductive line  185 A in the M2 layer. 
         [0032]    Subsequent processes may be performed to complete the fabrication of the device  100 , such as forming additional metallization layers, die singulation, and packaging. The use of the illustrated process provides self-aligned control of the via formation process. The use of the sacrificial lines  130 ,  165  prevents via misalignment in both the x and y directions. The use of the sacrificial material  160  to pattern the cap layer  145  allows the cap layer  145  to be completely removed from between the first and second dielectric layers  125 ,  175 , thereby reducing the capacitance of the device  100 . 
         [0033]    The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Note that the use of terms, such as “first,” “second,” “third” or “fourth” to describe various processes or structures in this specification and in the attached claims is only used as a shorthand reference to such steps/structures and does not necessarily imply that such steps/structures are performed/formed in that ordered sequence. Of course, depending upon the exact claim language, an ordered sequence of such processes may or may not be required. Accordingly, the protection sought herein is as set forth in the claims below.