Abstract:
An inspection apparatus includes an interface connector, an inspection mechanism, and a monitor. The interface connector connects the inspection apparatus with an external device. The inspection mechanism inspects an inspection board using primary data sent by the external device by the interface connector, and informs the external device by the interface connector about an inspection result obtained based on secondary data corresponding to the primary data. The monitor is connected with the interface connector on a primary signal line and monitors the primary and secondary data executed concurrently with an inspecting operation of the inspection mechanism, acquires the primary and secondary data, and transmits the primary and secondary data directly to the external device by the interface connector executed concurrently with an informing operation of the inspection mechanism.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     The present patent document claims priority under 35 U.S.C. § 119 to Japanese Patent Application No. 2003-350858, filed on Oct. 9, 2003, in the Japanese Patent Office, the entire contents of which are hereby incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention generally relates to a method and apparatus for circuit board inspection. In particular, the present invention relates to a method and apparatus for circuit board inspection capable of effectively monitoring inspection signals by using a signal monitor incorporated in the apparatus during inspection operations.  
         [0004]     2. Discussion of the Background  
         [0005]     Background inspection apparatuses for inspecting circuit boards compare reference data of a nondefective circuit board and a test circuit board to verify the functional accuracy of the test circuit board.  
         [0006]     A background inspection apparatus stores measured data values of a nondefective circuit board as reference data values in a memory of the background inspection apparatus. When a test circuit board is inspected, its data values are measured and compared with the reference data values to verify the functional accuracy of the test circuit board.  
         [0007]     In this application, statuses of signals from the nondefective circuit board may need to be monitored to determine more accurately whether the measured data values of the nondefective circuit board are correct. However, the background inspection apparatus does not have a function to monitor conditions of the signals.  
         [0008]     Another background inspection apparatus uses a detection unit to detect a difference in a digital form between reference response pattern data obtained from a nondefective circuit board and response pattern data obtained from a test circuit board, and obtains results of comparison of these circuit boards.  
         [0009]     Statuses of signals from the nondefective circuit board may also be needed to be monitored to determine more accurately whether the reference response pattern data of the nondefective circuit board is correct. However, the background inspection apparatus does not have a function to monitor conditions of the signals in common with the previously described background inspection apparatus.  
         [0010]     To monitor the signals for searching defects of the above-described circuit boards and checking conditions of signals thereof, an external detection device, such as an oscilloscope and a logic analyzer, has been used. Based on signals of the circuit boards of a target product acquired with the external detection device by using probes, waveforms, logical values and times are studied to specify a position of a defect and to examine the conditions of signals. When the probes of the external detection device make contact with the test circuit board, a load of the probes&#39; capacitor may deform the waveforms. The deformed waveforms may be different from the waveforms actually obtained in an adequate environment in which the actual external detection device is used to examine the conditions of the signals of the circuit boards. Therefore, the background inspection apparatus may have difficulty in verifying functional accuracy of the test circuit boards.  
       SUMMARY OF THE INVENTION  
       [0011]     The present invention has been made in view of the above-described circumstances.  
         [0012]     An object of the present invention is to provide an inspection apparatus capable of effectively monitoring inspection signals by using a signal monitor incorporated in the apparatus during inspection operations so that monitor signals may directly be transmitted to an external device.  
         [0013]     Another object of the present invention is to provide an inspection apparatus capable of effectively monitoring inspection signals by using a signal monitor incorporated in the apparatus during inspection operations so that monitor signals may be transmitted to an external device through at least one counter or a memory.  
         [0014]     Another object of the present invention is to provide a remote inspection system capable of monitoring an inspection result transmitted by an inspection apparatus connected to a device to a different device remotely connected to the device by a network.  
         [0015]     A novel image inspection apparatus of the present invention includes an interface, an inspection mechanism, and a signal buffer mechanism. The interface is configured to interface with an external device providing at least one source signal. The inspection mechanism is configured to perform an inspection of a circuit board externally connected to the inspection mechanism using the at least one source signal sent from the external device by the interface and at least one response signal returned from the circuit board. The signal buffer mechanism is configured to monitor and store the at least one source and response signals at points of respective connection lines between the inspection mechanism and the circuit board.  
         [0016]     The inspection mechanism may receive the at least one source signal from the external device by the interface, output the at least one source signal to the circuit board, receive the at least one response signal from the circuit board, and verify functional accuracy of the circuit board based on the at least one source and response signals.  
         [0017]     The inspection mechanism may further be configured to transmit a result of the inspection to the external device by the interface. The signal buffer mechanism may further be configured to transmit the at least one source and response signals to the external device by the interface.  
         [0018]     The novel inspection apparatus may further include a counter configured to repeatedly count up to a predetermined number, to receive at least one of the at least one source and response signals selectively sent from the signal buffer mechanism, and to transmit the at least one of the at least one source and response signals to the external device by the interface each time the counter counts up to the predetermined number.  
         [0019]     The novel inspection apparatus may further include a plurality of counters, each configured to repeatedly count up to a predetermined number, to receive at least one of the at least one source and response signals selectively sent from the signal buffer mechanism, and to transmit the at least one of the at least one source and response signals to the external device by the interface each time the counter counts up to the predetermined number.  
         [0020]     The novel inspection apparatus may further include a first counter configured to count during a predetermined time period a time length of a high-level signal in one of the at least one source and response signals selectively sent from the signal buffer mechanism and to transmit the time length of the high-level signal counted by the first counter to the external device by the interface, and a second counter configured to count during the predetermined time period a time length of a low-level signal in the one of the at least one source and response signals selectively sent from the signal buffer mechanism and to transmit the time length of the low-level signal counted by the first counter to the external device by the interface.  
         [0021]     The novel inspection apparatus may further include a memory configured to receive signals representing the time length of the high-level signal output from the first counter and the time length of the low-level signal output from the second counter and at least one of the at least one source and response signals sent from the signal buffer mechanism, and to transmit the received signals in a predetermined screen frame to the external device by the interface.  
         [0022]     The interface may comply with at least one of interface protocols of peripheral component interconnect, Internet security and acceleration, and personal computer memory card international association.  
         [0023]     In one exemplary embodiment, a novel method of board inspecting includes receiving at least one source signal from an external device with an interface, performing an inspection of a circuit board using the at least one source signal originated by the external device and at least one response signal sent back from the circuit board, monitoring the at least one source and response signals, and storing the at least one source and response signals monitored by the monitoring.  
         [0024]     The performing may include outputting the at least one source signal to the circuit board, receiving the at least one response signal from the circuit board, and verifying functional accuracy of the circuit board.  
         [0025]     The novel method may further include transmitting a result of the inspection performed by the performing to the external device by the interface, and sending the at least one source and response signals to the external device by the interface.  
         [0026]     The novel method may further include counting up to a predetermined number, and transmitting the at least one of the at least one source and response signals to the external device by the interface each time the counting performs counting up to the predetermined number.  
         [0027]     The novel method may further include counting up to a predetermined number, and transmitting at least two of the at least one source and response signals to the external device by the interface each time the counting performs counts up to the predetermined number.  
         [0028]     The novel method may further include counting during a predetermined time period a time length of a high-level signal in one of the at least one source and response signals and a time length of a low-level signal in the one of the at least one source and response signals, and transmitting signals representing the time lengths of the high-level and the low-level signals counted by the counting to the external device by the interface.  
         [0029]     The novel method may further include receiving signals representing the time lengths of the high-level and low-level signals output from the counting and the corresponding one of the at least one source and response signals, and sending the received signals in a predetermined screen frame to the external device by the interface.  
         [0030]     In one exemplary embodiment, a novel remote inspection system includes a first data terminal connected to a network, a second data terminal connected to the network and originating at least one source signal, and an inspection apparatus connected to the second data terminal. The inspection apparatus includes an interface configured to interface with a second data terminal originating at least one source signal, an inspection mechanism configured to perform an inspection of a circuit board externally connected to the inspection mechanism using the at least one source signal sent from the second data terminal by the interface and at least one response signal returned from the circuit board, and a signal buffer mechanism configured to monitor and store the at least one source and response signals at points of respective connection lines between the inspection mechanism and the circuit board.  
         [0031]     The inspection mechanism may receive the at least one source signal from the second data terminal by the interface, output the at least one source signal to the circuit board, receive the at least one response signal from the circuit board, and verify functional accuracy of the circuit board based on the at least one source and response signals.  
         [0032]     The inspection mechanism may further be configured to transmit a result of the inspection to the second data terminal by the interface. The signal buffer mechanism may further be configured to transmit the at least one source and response signals to the second data terminal by the interface.  
         [0033]     The inspection apparatus may further include a counter configured to repeatedly count up to a predetermined number, to receive at least one of the at least one source and response signals selectively sent from the signal buffer mechanism, and to transmit the at least one of the at least one source and response signals to the second data terminal by the interface each time the counter counts up to the predetermined number.  
         [0034]     The inspection apparatus may further include a plurality of counters, each configured to repeatedly count up to a predetermined number, to receive at least one of the at least one source and response signals selectively sent from the signal buffer mechanism, and to transmit the at least one of the at least one source and response signals to the second data terminal by the interface each time the counter counts up to the predetermined number.  
         [0035]     The inspection apparatus may further include a first counter configured to count during a predetermined time period a time length of a high-level signal in one of the at least one source and response signals selectively sent from the signal buffer mechanism and to transmit the time length of the high-level signal counted by the first counter to the second data terminal by the interface, and a second counter configured to count during the predetermined time period a time length of a low-level signal in the one of the at least one source and response signals selectively sent from the signal buffer mechanism and to transmit the time length of the low-level signal counted by the first counter to the second data terminal by the interface.  
         [0036]     The inspection apparatus may further include a memory configured to receive signals representing the time length of the high-level signal output from the first counter and the time length of the low-level signal output from the second counter and at least one of the at least one source and response signals sent from the signal buffer mechanism, and to transmit the received signals in a predetermined screen frame to the second data terminal by the interface.  
         [0037]     In one exemplary embodiment, a novel method of remote board inspection includes connecting a first data terminal providing a request, to a network, connecting a second data terminal providing at least one source signal in accordance with the request from the first data terminal, to the network, providing an inspection apparatus connected to the second data terminal, receiving the at least one source signal from the second data terminal with an interface, performing an inspection of a circuit board using the at least one source signal originated by the second data terminal and at least one response signal sent back from the circuit board, monitoring the at least one source and response signals, and storing the at least one source and response signals monitored by the monitoring.  
         [0038]     The performing may include outputting the at least one source signal to the circuit board, receiving the at least one response signal from the circuit board, and verifying functional accuracy of the circuit board.  
         [0039]     The novel method of remote board inspection may further include transmitting a result of the inspection performed by the performing to the second data terminal by the interface, and sending the at least one source and response signals to the second data terminal by the interface.  
         [0040]     The novel method of remote board inspection may further include counting up to a predetermined number, and transmitting the at least one of the at least one source and response signals to the second data terminal by the interface each time the counting performs counting up to the predetermined number.  
         [0041]     The transmitting may transmit at least two of the at least one source and response signals to the second data terminal by the interface each time the counting performs counting up to the predetermined number.  
         [0042]     The novel method of remote board inspection may further include counting during a predetermined time period a time length of a high-level signal in one of the at least one source and response signals and a time length of a low-level signal in the one of the at least one source and response signals, and transmitting signals representing the time lengths of the high-level and the low-level signals counted by the counting to the second data terminal by the interface.  
         [0043]     The novel remote board inspection may further include receiving signals representing the time lengths of the high-level and low-level signals output from the counting and the corresponding one of the at least one source and response signals, and sending the received signals in a predetermined screen frame to the second data terminal by the interface. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0044]     A more complete appreciation of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:  
         [0045]      FIG. 1  is an illustration of a structure of an inspection apparatus incorporating a signal monitor according to an exemplary embodiment of the present invention;  
         [0046]      FIG. 2  is an illustration of another structure of an inspection apparatus incorporating a signal monitor according to another exemplary embodiment of the present invention;  
         [0047]      FIG. 3  is an illustration of another structure of an inspection apparatus incorporating a signal monitor according to another exemplary embodiment of the present invention;  
         [0048]      FIG. 4  is an illustration of another structure of an inspection apparatus incorporating a signal monitor according to another exemplary embodiment of the present invention;  
         [0049]      FIG. 5  is an illustration of another structure of an inspection apparatus incorporating a signal monitor according to another exemplary embodiment of the present invention; and  
         [0050]      FIG. 6  is an illustration of a structure of a remote inspection system according to an exemplary embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0051]     Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views.  
         [0052]     In describing preferred embodiments illustrated in the drawings, specific terminology is employed for the sake of clarity. However, the disclosure of the present invention is not intended to be limited to the specific terminology so selected, and it is to be understood that each specific element includes all technical equivalents that operate in a similar manner.  
         [0053]     Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views, preferred embodiments of the present invention are described.  
         [0054]     Referring to  FIG. 1 , a block diagram of a system structure of an inspection apparatus  10  according to an exemplary embodiment of the present invention is described.  
         [0055]     In  FIG. 1 , the inspection apparatus  10  includes a peripheral component interconnect (PCI) interface connector  1 , a board inspection module  2 , an external output terminal  3 , an external input terminal  4 , a buffer selector  5 , and signal lines  6   a ,  6   b ,  7   a ,  7   b , and  8   a.    
         [0056]     The peripheral component interconnect (PCI) interface connector  1 , which is hereinafter referred to as a “PCI interface  1 ”, is an interface connector complying with a protocol under a peripheral component interconnect (PCI). Other interface connectors complying with different protocols, such as Internet security and acceleration (ISA) and personal computer memory card international association (PCMCIA), as non-limiting examples, are also available and could be utilized.  
         [0057]     The board inspection module  2  works as an inspection mechanism. The board inspection module  2  communicates with external devices including an external personal computer (PC) (not shown) by the PCI interface  1  and with circuit boards including a test circuit board (not shown) connected on the signal lines  6   a  and  6   b  by the external output and input terminals  3  and  4 , respectively, and verifies functional accuracy of the test circuit board. Each of the external output and input terminals  3  and  4  is a bundle of signal lines and can transmit a plurality of signals.  
         [0058]     The external output terminal  3  is used to output test data sent from the board inspection module  2  on the signal line  6   a.    
         [0059]     The external input terminal  4  is used to input response data, which is processed by the test circuit board based on the test data, to the board inspection module  2  on the signal line  6   b.    
         [0060]     The buffer selector  5  works as a monitor of the inspection apparatus  10  and is incorporated in the inspection apparatus  10 . The buffer selector  5  monitors a series of signals of the test data and the response data, acquires these signals as monitor signals, and transmits these signals to the external PC by the PCI interface  1 .  
         [0061]     Operations of the inspection apparatus  10  of  FIG. 1  are described below.  
         [0062]     When the external PC sends test data for inspection of the test circuit board, the board inspection module  2  of the inspection apparatus  10  receives the test data by the PCI interface  1 . The board inspection module  2  then outputs the test data to the test circuit board by the external output terminal  3  on the signal line  6   a . The test circuit board operates according to the test data, and replies response data to the board inspection module  2  on the signal line  6   b  by the external input terminal  4 . When the board inspection module  2  receives the response data from the test circuit board by the external input terminal  4 , the board inspection module  2  verifies, according to the response data, whether the test circuit board accurately functions or not.  
         [0063]     While the board inspection module  2  performs data transmission with the test circuit board by the external output and input terminals  3  and  4  on the signal lines  6   a  and  6   b , respectively, the buffer selector  5  keeps monitoring the above-described data transmission, acquires a series of signals of the test data at the external output terminal  3  on the signal line  7   a  and a series of signals of the response data at the external input terminal  4  on the signal line  7   b , and directly transmits these signals as monitor signals on the signal line  8   a  to the external PC by the PCI interface  1 .  
         [0064]     After receiving the monitor signals, the external PC runs a predetermined software to display conditions of the monitor signals on a screen (not shown) of a display unit (not shown) of the external PC, for example. By doing so, the conditions of the monitor signals become visible on the screen, and users including an examiner may determine whether the test data output to the test circuit board by the board inspection module  2  of the inspection apparatus  1  is correct or not.  
         [0065]     When obtaining a determination result that the test circuit board has a defect, the board inspection module  2  transmits the above-described determination result to the external PC by the PCI interface  1 . At the same time, the buffer selector  5  incorporated in the inspection apparatus  10  monitors conditions of the monitor signals input from the test circuit board to the board inspection module  2  on the signal line  6   b  by the external input terminal  4 , acquires the monitor signals at the external input terminal  4  by bypassing with the signal line  7   b , and directly transmits the monitor signals to the external PC by the PCI interface  1 . By directly transmitting the monitor signals from the buffer selector  5 , the external PC may show the conditions of the monitor signals on the screen and the examiner may easily find out details of the defect.  
         [0066]     The buffer selector  5  can constantly monitor the signals on the external output and input terminals  3  and  4 , regardless of whether the operations of the board inspection module  2  are stopped. That is, when the operations of the board inspection module  2  are stopped during, for example, the data transmission between the board inspection module  2  and the test circuit board by the external output and input terminals  3  and  4 , the buffer selector  5  monitors the conditions of the signals on the external output terminal  3  and the response signals on the external input terminal  4 . The buffer selector  5  then transmits these signals directly to the external PC by the PCI interface  1  so that the conditions of the monitor signals may be displayed on the screen of the external PC. By displaying the monitor signals on the screen of the external PC, the examiner may monitor the conditions of the monitor signals.  
         [0067]     With the above-described structure, the inspection apparatus  10  may monitor the signals in inoperable conditions such as a malfunction and stall of the test circuit board, without using external detection devices. That is, with the buffer selector  5  incorporated in the inspection apparatus  10 , the inspection apparatus  10  may test the signals without using probes connected to the detection device, thereby preventing unnecessary deformation of waveforms caused by a load of the probes&#39; capacitor.  
         [0068]     Referring to  FIG. 2 , a block diagram of a system structure of an inspection apparatus  20  according to another exemplary embodiment of the present invention is described.  
         [0069]     In  FIG. 2 , the inspection apparatus  20  includes the peripheral component interconnect interface connector (PCI interface)  1 , the board inspection module  2 , the external output terminal  3 , the external input terminal  4 , the buffer selector  5 , the signal lines  6   a ,  6   b ,  7   a ,  7   b ,  8   a , signal lines  9   a  and  9   b , and a counter  26 .  
         [0070]     The above-described components of the inspection apparatus  20 , shown in  FIG. 2 , are similar to the components of the inspection apparatus  10 , shown in  FIG. 1 , with the exception of the counter  26  and the signal lines  9   a  and  9   b.    
         [0071]     The counter  26  operates between the PCI interface  1  and the buffer selector  5 . The signal lines  9   a  and  9   b  are provided in addition to the signal line  8   a  that directly connects the buffer selector  5  with the PCI interface  1  of  FIG. 1 .  
         [0072]     Operations of the inspection apparatus  20  shown in  FIG. 2  are also similar to those of the inspection apparatus  10  shown in  FIG. 1  except for a series of operations related to the counter  26  and the signal lines  9   a  and  9   b.    
         [0073]     After acquiring the monitor signals including the test data and the response data, the buffer selector  5  sequentially transmits the monitor signals to the external PC by the PCI interface  1  on the signal lines  8   a  and  9   a . The monitor signals on the signal line  8   a  are directly transmitted to the external PC by the PCI interface  1 . For the monitor signals on the signal line  9   a , the counter  26  counts the monitor signals at intervals of a predetermined number of counts, and outputs the monitor signals to the external PC by the PCI interface  1 .  
         [0074]     By controlling transmission of the monitor signals as described above, it is determined whether the monitor signals are dynamic or static. The monitor signals include a dynamic signal and a static signal. When the monitor signals are dynamic, that is when the monitor signals repeat a high level condition and a low level condition, it is determined that the test circuit board functions well. When the monitor signals are static, that is when the monitor signals stay in one of the high level condition and low level condition, it is determined that the test circuit board may have a problem.  
         [0075]     With the above-described structure of  FIG. 2 , in addition to the operations performed in the inspection apparatus  10  of  FIG. 1 , the inspection apparatus  20  having a monitoring function therein may have the counter  26  count the monitor signals at intervals of the predetermined number of counts so that it is determined whether the monitor signals repeat a high level condition and a low level condition, thereby facilitating debugging and analyzing the test circuit board.  
         [0076]     Referring to  FIG. 3 , a block diagram of a system structure of an inspection apparatus  30  according to another exemplary embodiment of the present invention is described.  
         [0077]     In  FIG. 3 , the inspection apparatus  30  includes the peripheral component interconnect interface connector (PCI interface)  1 , the board inspection module  2 , the external output terminal  3 , the external input terminal  4 , the buffer selector  5 , a plurality of counters including counters  36   a  and  36   b , signal lines  6   a ,  6   b ,  7   a ,  7   b  and  8   a , and different signal lines  39   a ,  39   b ,  39   c  and  39   d.    
         [0078]     The above-described components of the inspection apparatus  30 , shown in  FIG. 3 , are similar to the components of the inspection apparatus  10 , shown in  FIG. 1 , with the exception of the plurality of counters including the counters  36   a  and  36   b , and the signal lines  39   a ,  39   b ,  39   c  and  39   d . Since the plurality of counters have similar structures to each other, the following descriptions will be made focusing on the counters  36   a  and  36   b.    
         [0079]     The counters  36   a  and  36   b  operate between the PCI interface  1  and the buffer selector  5  on the respective signal lines  39   a ,  39   b ,  39   c  and  39   d . The respective signal lines  39   a ,  39   b ,  39   c  and  39   d  are provided in addition to the previously provided signal lines  6   a ,  6   b ,  7   a ,  7   b  and  8   a.    
         [0080]     Operations of the inspection apparatus  30  shown in  FIG. 3  are also similar to those of the inspection apparatus  10  shown in  FIG. 1 , except for a series of operations related to the counters  36   a  and  36   b , and the signal lines  39   a ,  39   b ,  39   c  and  39   d.    
         [0081]     After acquiring the monitor signals including the test data and the response data, the buffer selector  5  sequentially transmits the monitor signals to the external PC by the PCI interface  1 . The counters  36   a  and  36   b  count the monitor signals from the buffer selector  5  at intervals of a predetermined number of counts, and output the respective monitor signals to the external PC by the PCI interface  1 .  
         [0082]     As previously described, the counters  36   a  and  36   b  have similar structures, thereby simultaneously performing operations identical to each other. By providing the plurality of counters for simultaneously performing identical operations, a plurality of monitor signals can be monitored and latched. When the plurality of monitor signals are transmitted to the external PC by the PCI interface  1 , the external PC can effectively determine whether any of the plurality of monitor signals are delayed.  
         [0083]     With the above-described structure of  FIG. 3 , in addition to the operations performed in the inspection apparatus  10  of  FIG. 1 , the inspection apparatus  30  having a monitoring function therein may effectively determine occurrence of signal delay of the monitor signals transmitted from the buffer selector  5 .  
         [0084]     Referring to  FIG. 4 , a block diagram of a system structure of an inspection apparatus  40  according to another exemplary embodiment of the present invention is described.  
         [0085]     In  FIG. 4 , the inspection apparatus  40  includes the peripheral component interconnect interface connector (PCI interface)  1 , the board inspection module  2 , the external output terminal  3 , the external input terminal  4 , the buffer selector  5 , a first counter  46   a  and a second counter  46   b , the signal lines  6   a ,  6   b ,  7   a ,  7   b  and  8   a , and different signal lines  49   a ,  49   b ,  49   c  and  49   d.    
         [0086]     The above-described components of the inspection apparatus  40 , shown in  FIG. 4 , are similar to the components of the inspection apparatus  10 , shown in  FIG. 1 , with the exception of the first and second counters  46   a  and  46   b , and the signal lines  49   a ,  49   b ,  49   c  and  49   d.    
         [0087]     The first and second counters  46   a  and  46   b  operate between the PCI interface  1  and the buffer selector  5 . The signal lines  49   a ,  49   b ,  49   c  and  49   d  are provided in addition to the signal line  8   a  that directly connects the buffer selector  5  with the PCI interface  1  of  FIG. 1 . The signal lines  49   a  and  49   b  are originally one signal line that has been divided into two signal lines branched between the buffer selector  5  and the first and second counters  46   a  and  46   b , and the signal lines  49   c  and  49   d  are extended to the PCI interface  1 .  
         [0088]     Operations of the inspection apparatus  40  shown in  FIG. 4  are also similar to those of the inspection apparatus  10  shown in  FIG. 1 , except for a series of operations related to the first and second counters  46   a  and  46   b , and the signal lines  49   a ,  49   b ,  49   c  and  49   d.    
         [0089]     After acquiring the monitor signals including the test data and the response data, the buffer selector  5  sequentially transmits the monitor signals to the external PC by the PCI interface  1  on the signal lines  8   a ,  49   a  and  49   b . The monitor signals on the signal line  8   a  are directly transmitted to the external PC by the PCI interface  1 . For the monitor signals on the signal lines  49   a  and  49   b , the first and second counters  46   a  and  46   b  respectively count the monitor signals, and output the monitor signals to the external PC by the PCI interface  1 . The first counter  46   a  counts high-level signals having a value “1”, increments the number of high-level signals among the monitor signals that are output from the buffer selector  5  during a predetermined period of time, and provides a result of the counting to the external PC by the PCI interface  1 . The second counter  46   b  counts low-level signals having a value “2”, increments the number of low-level signals among the monitor signals that are output from the buffer selector  5  during a predetermined period of time, and provides a result of the counting to the external PC by the PCI interface  1 .  
         [0090]     By providing the first and second counters  46   a  and  46   b , a plurality of monitor signals may be monitored. In addition, the external PC may obtain each duty of the high-level signals and the low-level signals acquired by the buffer selector  5 . When the duties of the high- and low-level signals of the monitor signals are transmitted to the external PC by the PCI interface  1 , the external PC may effectively determine the duties of the monitor signals acquired by the buffer selector  5 .  
         [0091]     With the above-described structure of  FIG. 4 , in addition to the operations performed in the inspection apparatus  10  of  FIG. 1 , the inspection apparatus  40  having a monitoring function therein may effectively monitor the plurality of monitor signals and determine the duties of the high-level and low-level signals of the monitor signals that are acquired by the buffer selector  5 .  
         [0092]     Referring to  FIG. 5 , a block diagram of a system structure of an inspection apparatus  50  according to another exemplary embodiment of the present invention is described.  
         [0093]     In  FIG. 5 , the inspection apparatus  50  includes the peripheral component interconnect interface connector (PCI interface)  1 , the board inspection module  2 , the external output terminal  3 , the external input terminal  4 , the buffer selector  5 , the first counter  46   a , the second counter  46   b , a memory  57 , the signal lines  6   a ,  6   b ,  7   a ,  7   b ,  49   a  and  49   b , and different signal lines  59   a ,  59   b ,  59   c  and  59   d.    
         [0094]     The above-described components of the inspection apparatus  50 , shown in  FIG. 5 , are similar to the components of the inspection apparatus  40 , shown in  FIG. 4 , with the exception of the memory  57 , and the signal lines  59   a ,  59   b ,  59   c  and  59   d.    
         [0095]     The memory  57  operates between the PCI interface  1  and the buffer selector  5  and the first and second counters  46   a  and  46   b . The signal lines  59   a ,  59   b ,  59   c  and  59   d  are provided for signal transmission with respect to the memory  57 . The memory  57  receives the monitor signals from the buffer selector  5  on the signal line  59   c , from the counter  46   a  on the signal line  59   a , and from the counter  46   b  on the signal line  59   b , and transmits the monitor signals to the PCI interface  1  on the signal line  59   d.    
         [0096]     Operations of the inspection apparatus  50  shown in  FIG. 5  are also similar to those of the inspection apparatus  40  shown in  FIG. 4 , except for a series of operations related to the memory  57  using the signal lines  59   a ,  59   b ,  59   c  and  59   d.    
         [0097]     The memory  57  receives respective monitor signals from the first counter  46   a , the second counter  46   b  and the buffer selector  5  on the respective signal lines  59   a ,  59   b  and  59   c  therebetween, so as to store the respective monitor signals. The memory  57  then transmits a predetermined amount of monitor signals stored therein on the signal line  59   d  connected with the PCI interface  1 , to the external PC.  
         [0098]     Detailed operations of the memory  57  are as follows. The memory  57  samples the monitor signals of the first and second counters  46   a  and  46   b  based on clock pulses, for example, and stores a predetermined amount of data of the thus sampled monitor signals to a first-in first-out (FIFO) buffer of the buffer selector  5 . When the predetermined amount of data is 64 bit, for example, according to a fact that the memory  57  has a length of 64 bit per line, the memory  57  obtains the sampled monitor signals and temporarily stores up to the 64 bit data of the sampled monitor signals as one line, to the FIFO buffer. The memory  57  repeats the above-described serial operations. Further, at the moment the lines of data stored in the FIFO buffer become equal to a predetermined amount and ready for a burst transmission, the memory  57  transmits a request to the external PC to write the data of the sampled monitor signals, and repeats the operation for a previously set period of time.  
         [0099]     By providing the memory  57  after the buffer selector  5  and the first and second counters  46   a  and  46   b , the data separately obtained from the buffer selector  55  and the first and second counters  46   a  and  46   b  may be stored in the memory  57  together and transmitted by a predetermined amount to the external PC by the PCI interface  1 .  
         [0100]     With the above-described structure of  FIG. 5 , in addition to the operations performed in the inspection apparatus  10  of  FIG. 1 , the inspection apparatus  50  having a monitoring function therein may transmit the data of the conditions of the monitor signals stored in the memory  57  to the external PC so that the external PC can show the data of its time base on the screen, for example, to perform as a signal monitor and a logic tracer.  
         [0101]     Referring to  FIG. 6 , a block diagram of a system structure of a remote inspection system  600  according to an exemplary embodiment of the present invention is described.  
         [0102]     In  FIG. 6 , the remote inspection system  600  generally includes a local personal computer (PC)  601 , a network  602 , and a remote personal computer (PC)  603 .  
         [0103]     The local PC  601  has functions identical to those described in the embodiments with reference  FIGS. 1 through 5 . The local PC  601  is connected with an inspection apparatus  60  with a monitor function incorporated therein, by an interfacing device, such as a device complying with an interface protocol, such as peripheral component interconnect (PCI), Internet security and acceleration (ISA) and personal computer memory card international association (PCMCIA) as well as a wireless local area network (LAN) interface and an infrared communication interface. The inspection apparatus  60  inspecting a test circuit board  62  has functions identical to the inspection apparatuses  10  through  50  described in the embodiments with reference to  FIGS. 1 through 5 , respectively.  
         [0104]     The network  602  is a network, such as a LAN, a wide area network (WAN), etc., connecting the local PC  601  with the remote PC  603  in  FIG. 6 .  
         [0105]     The remote PC  603  may be located at a site different from the local PC  601 . The remote PC  603 , however, is connected with the local PC  601  by the network  602  as described above, and issues instructions to the local PC  601  through the network  602 .  
         [0106]     Operations of the remote inspection system  600  of  FIG. 6  are described below.  
         [0107]     In  FIG. 6 , the local PC  601  is located at a site and the remote PC  603  is located at a different site, and the local PC  601  and the remote PC  603  are connected with each other by the network  602 . When the remote PC  603  sends test data corresponding to the test circuit board  62  to the local PC  601  by the network  602 , the local PC  601  receives and downloads the test data to the inspection apparatus  60  so that the inspection apparatus  60  may perform inspections on the test circuit board  62 .  
         [0108]     Further, the inspection apparatus  60  performs a monitoring operation of conditions of monitor signals, and transmits result data obtained through the monitoring operation to the remote PC  603  by the network  602 .  
         [0109]     With the above-described system structure of  FIG. 6 , the remote inspection system  600  may control inspections of the test circuit board  62  from the remote PC  603  by issuing instructions therefrom to the local PC  601  connected by the network  602 . The remote inspection system  600  further makes it possible that the remote PC  603  can remotely monitor the conditions of the monitor signals obtained between the inspection apparatus  60  and the test circuit board  62 .  
         [0110]     The present invention is not restricted to only those systems described above. For example, it would be possible to add the memory  57  to the inspection apparatus  10  of  FIG. 1  or the inspection apparatus  20  of  FIG. 2  so that the inspection apparatus  50  of  FIG. 5  would be configured.  
         [0111]     Additionally, the signal line directly connecting the PCI interface  1  with the buffer selector  5  of the inspection apparatus  20  of  FIG. 2  may be omitted. This applies not only to the signal line  8   a  of the inspection apparatus  20  of  FIG. 2 , but also to that of the inspection apparatus  30  of  FIG. 3  and the inspection apparatus  40  of  FIG. 4 . Further, those inspection apparatuses  20 ,  30  and  40  may be applied as the inspection apparatus  60  included in the remote inspection system  600  of  FIG. 6 .  
         [0112]     Additionally, the PCI interface  1  of the inspection apparatus  10  of  FIG. 1  may be a wireless interface connector connecting with personal computers on the wireless LAN. This applies not only to the inspection apparatus  10  of  FIG. 1  but also to the inspection apparatuses  20 ,  30 ,  40  and  50  of  FIGS. 2, 3 ,  4  and  5 , respectively.  
         [0113]     Numerous additional modifications and variations are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the disclosure of this patent specification may be practiced otherwise than as specifically described herein.