Abstract:
Binary coded signals present on N input lines are decoded by means of N differential current switches. Each current switch is connected to a different one of the input lines and produces a group of 2.sup.(N-1) outputs in-phase with its input and a group of 2.sup.(N-1) outputs out-of-phase with its input. 2 N  conductors interconnect the outputs of the N switches to produce 2 N  decoded outputs, each of which represents a unique combination of the binary signals on the N input lines.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to decoding circuits for converting coded information into an uncoded format. 
     In many digital systems (e.g. memories, computers, etc.) information is encoded to reduce the number of signal carrying lines and to provide a compact and efficient way of routing information from one section of a system to another section or from one system to another. For example, using the Binary Coded Decimal (BCD) code, N lines carrying binary coded information include 2 N  unique combinations of the signals on the N lines. Thus, only N lines are needed to carry 2 N  different commands. However, at some point it is necessary to decode the information on the N lines. For example, this may occur where the data on the N lines is to be used for uniquely selecting one of many word or bit lines of a memory array. 
     The binary information contained on the N lines must then be separated to produce 2 N  unique outputs, with each output representing a particular combination of the N binary inputs signals, and with each output being excited (e.g. logic &#34;1&#34;) for only one particular combination of the N input signals. To optimize the benefits of decoding, it is important that the decoding circuitry be compact, use few components and consume small amounts of power. 
     SUMMARY OF THE INVENTION 
     Circuits embodying the invention include &#34;N&#34; differential current switches, each connected to a different one of N input lines for decoding the signals on the N lines. Each current switch produces 2.sup.(N-1), separate, in-phase output signals, and 2.sup.(N-1), separate, out-of-phase output signals in response to its input signal. 2 N  conductors interconnect the outputs of the N current switches to produce 2 N  unique combinations of the N input signals applied to the current switches. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the accompanying drawing like reference characters denote like components; and 
     FIG. 1 is a semi-schematic, semi-block diagram of a circuit embodying the invention; 
     FIG. 2 is a schematic diagram of a differential current switch which may be used to practice the invention; 
     FIG. 3 is a cross sectional diagram of a transistor suitable for use in the current switch of FIG. 2; and 
     FIG. 4 is a schematic diagram of another current switch which may be used to practice the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The circuit of FIG. 1 includes differential current switches 10a, 10b and 10c, to which are applied input signals A i0 , A i1 , and A i2 , respectively. A type of differential current switch suitable for use in the circuit of FIG. 1 is detailed in FIG. 2. Two NPN bipolar multi-collector transistors (T 1 , T 2 ) are connected at their emitters to the collector of an NPN bipolar transistor T 3 . The emitter of transistor T 3  is connected to circuit ground and a fixed voltage is applied to its base, by a voltage source 11. As a result, a substantially constant current I flows in the collector of T 3 . 
     A reference signal [V REF  ] is applied to the base 14 of transistor T 2 , and an input signal (V IN ) which varies in amplitude about V REF  is applied to the base 12 of transistor T 1 . Those values of V IN  less positive than V REF  are, arbitrarily, defined as &#34;low&#34; or logic &#34;0&#34; and those value of V IN  more positive than V REF  are defined as &#34;high&#34; or logic &#34;1.&#34; 
     Transistors T 1  and T 2  have multi-collectors to produce multiple outputs on different, separate, lines. In practice the number of collectors per transistor is determined by the number of input variables to be decoded. Each differentially connected transistor (T 1 , T 2 ) has 2.sup.(N-1) collectors for decoding N input variables, where N is the number of variables (on the input lines of FIG. 1) to be decoded and is an integer greater than one (1). 
     The output voltage signals (V O ) produced at the collectors of T 1  are out-of-phase (i.e. the inverse) with the input (V IN ), while the output voltage signals (V O ) produced at the collectors of T 2  are in-phase with the input (V IN ). The V O  outputs of the differential switch are not the same electrical signals as the input V IN , but any V O  output at the collectors of T 2  is logically equal to V IN  and any V O  output at the collectors of T 1  is logically the inverse (or complement) of V IN . Hence, in the discussion to follow the input variable (V IN ) is used interchangeably with the in-phase output (V O ). 
     For V IN  more positive than V REF , transistor T 1  is turned on and can conduct (draw or sink) via each one of its collectors a current (I O ) which is at most equal to one fourth (I/4) of the source current I. Transistor T2 is turned-off and draws or sinks substantially no current (except for leakage) via its collectors. For V IN  less positive than V REF , transistor T 1  is turned off and draws no collector currents while transistor T 2  is turned on and each one of its collectors can sink a current (I O ) which is at most equal to I/4. 
     The differential current switch thus enables the production of 2.sup.(N-1) in-phase outputs and 2.sup.(N-1) out-of-phase outputs efficiently and within one propagation delay of the application of an input signal to the switch. 
     Transistors T 1  and T 2  are illustrated as Schottky-clamped transistors and each may be formed as shown in FIG. 3. 
     The emitter (e) is formed by an N-type doped region 31 diffused into a P-doped region 33 forming the base (b). The base in turn is diffused into an N-doped collector region 35. A multiplicity of self-isolating collector contacts (C1, C2, C3, C4) are formed by making separate metal contacts (37, 39, 41, 43) to the collector region. The metal contacts form Schottky barrier diodes, whereby each collector contact is isolated or decoupled from the others by a normally reverse biased diode. Thus, utilizing Schottky barrier contacts to form the collectors of the differential current mode switch transistors results in an extremely small area being required for the transistors. 
     Returning to the circuit of FIG. 1, recall that the 3 input variables (A i0 , A i1 , A i2 ) are applied, respectively, to the three current mode switches, 10a, 10b, 10c. Each current switch has four in-phase outputs (A 0 , A 1 , A 2 ) and four out-of-phase outputs (A 0 , A 1 , A 2 ). As noted above, the in-phase outputs of a switch are the logical equivalent of its input variable and the out-of-phase outputs of a switch are the logical inverse of its input variable. 
     The number of in-phase outputs (four) and the number of out-of-phase outputs (four) per current switch are equal to each other and to 2.sup.(N-1), where N represents the total number (N=3) of input variables to be decoded. 
     For the 3 input variables there are 2 N  =8 unique combinations as listed in the first three columns of the Truth Table below. The minterm expression for each combination is set forth in the fourth column of the table. The minterm expression is mechanized in FIG. 1 by providing eight output lines (Z 0  . . . Z 7 ), each corresponding to a different combination of the 3 input variables. Each output line is connected to one output from each of the three current switches (10a, 10b, 10c) to satisfy the minterm equations of column 4 for each output line. Connecting one output from each of the three differential switches to one of the output lines performs the logic &#34;AND&#34; functions of the three outputs. 
     
                                           TRUTH TABLE__________________________________________________________________________ Interconnection of Current Switch          W.sub.0             W.sub.1                W.sub.2                   W.sub.3                      W.sub.4                         W.sub.5                            W.sub.6                               W.sub.7A.sub.2  A.sub.1    A.sub.0 Outputs  Z.sub.0             Z.sub.1                Z.sub.2                   Z.sub.3                      Z.sub.4                         Z.sub.5                            Z.sub.6                               Z.sub.7__________________________________________________________________________0 0 0 Z.sub.0 = A.sub.0 . A.sub.1 . A.sub.2          1  0  0  0  0  0  0  00 0 1 Z.sub.1 = A.sub.0 . A.sub.1 . A.sub.2          0  1  0  0  0  0  0  00 1 0 Z.sub.2 = A.sub.0 . A.sub.1 . A.sub.2          0  0  1  0  0  0  0  00 1 1 Z.sub.3 = A.sub.0 . A.sub.1  . A.sub.2          0  0  0  1  0  0  0  01 0 0 Z.sub.4 = A.sub.0 . A.sub.1 . A.sub.2          0  0  0  0  1  0  0  01 0 1 Z.sub.5 = A.sub.0 . A.sub.1 . A.sub.2          0  0  0  0  0  1  0  01 1 0 Z.sub.6 = A.sub.0 . A.sub.1 . A.sub.2          0  0  0  0  0  0  1  01 1 1 Z.sub.7 = A.sub.0 . A.sub.1 . A.sub.2          0  0  0  0  0  0  0  1__________________________________________________________________________ 
    
     Connected to each one of the output lines (Z 0  . . . Z 7 ) is a respective loading network (120 . . . 127) comprised of: (1) a resistor R L  connected between the output line and a positive source of operating potential +V DD . The value of R L  is selected such that if one fourth of the source current (i.e. I/4) generated by current source transistor T 3  flows through R L , a voltage drop of approximately one V BE  (e.g. 0.7 volts) is developed across R L . In the description below, a current (I/4) equal to one fourth of the current source current is defined as a unit of current. (2) a transistor T L , connected as a diode in parallel with R L , for clamping the voltage on the output line to V BE  volts below V DD  ; and (3) an output transistor T 0  connected at its base to the output line, at its collector to +V DD , and at its emitter to a word line (W 0  . . . W 7 ). The output transistor T 0  functions as an emitter follower which level shifts down, by one V BE , the voltage at its base. 
     Depending on the values of input variables A i0 , A i1 , and A i2 , zero, one, two or three units of current can flow through each load network. When one unit of current flows through a load network it flows through its R L . When more than one unit of current flows through a load network, the current in excess of one unit flows through the diode connected transistor in parallel with R L . Each load network establishes the voltage level on its corresponding output line as a function of the load current. For zero current through the load network the output line is at, or close to, +V DD  volts which is defined as logic &#34;1.&#34; For one or more units of current through a load network the voltage on its output line is held at, or close to, [V DD  - V BE  ] volts which is defined as logic &#34;0.&#34; Thus, in the instant example, the selected value of R L  and the presence of T L  set the threshold between logic &#34;0&#34;  and logic &#34;1&#34; at one (1) unit of current. 
     In the discussion above, the leakage currents drawn by the current switches and the base current into T 0  are neglected. For the condition of V DD  and V DD  -V BE  on the output lines, the voltages at the emitter of the corresponding T 0  are [V DD  -V BE  ] volts and [V DD  -2V BE  ]  volts, respectively, which are defined as logic &#34;1&#34; and logic &#34;0,&#34; respectively. 
     The emitters of the several transistors T 0  are connected to word lines W 0  . . . W 7 , respectively. Any one of these lines may be, for example, part of a memory array (not shown), with portions (word lines) of the memory array selected in accordance with the values of the input variables. 
     The differential current mode switch used to practice the invention may also be of the type shown in FIG. 4. Here, two transistor, Ta, Tb, each with separate collectors are differentially connected to produce, in response to a signal V IN , a plurality of signals 41 in phase with V IN  and a like plurality of signals 43 out-of-phase with V IN . Note that the differential transistors need not be Schottky types. 
     It should be evident that a decoder embodying the invention employs very few devices, which is of critical importance in fabricating low cost, reliable, bipolar memory devices. In addition, the signal propagation path delay has been reduced to that of a single &#34;gate&#34; delay, considerably improving the speed performance of the decoder. This is very important in reducing the access times of memory or other devices incorporating the decoder.