Abstract:
In the sense amplifier layout method of a semiconductor memory device, a plurality of bit lines and bit bar lines are alternately aligned in parallel. One bit line and one bit bar line form a bit line pair. A plurality of MOS transistors for a sense amplifier extend over a predetermined number of bit line pairs in a longitudinal direction of the bit line pairs. Gates of the MOS transistors are formed over at least a portion the predetermined number of bit line pairs.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a sense amplifier layout method of a semiconductor memory device, and in particular to a layout structure of NMOS transistors of a sense amplifier. 
     2. Description of the Background Art 
     A sense amplifier of a semiconductor memory device consists of a pull-up device using a PMOS transistor and a pull-down device using an NMOS transistor. The sense amplifier amplifies a data voltage applied to a bit line BL and a bit bar line /BL, and outputs the amplified voltage to a data bus. 
     FIG. 1 illustrates the sense amplifier of the semiconductor memory device. Referring to FIG. 1, the sense amplifier includes: a first sense amp unit  10  for sensing data of a bit bar line /BL 0  and a bit line BL 0 ; and a second sense amp unit  20  for sensing data of a bit bar line /BL 1  and a bit line BL 1 . In the first sense amp unit  10 , a PMOS transistor P 1  and an NMOS transistor N 1  are connected in series between a power supply voltage VDD and a ground VSS, and a PMOS transistor P 2  and an NMOS transistor N 2  are connected in series between the power supply voltage VDD and the ground VSS. The PMOS transistor P 1  and the NMOS transistor N 1  have their drains connected to the bit bar line /BL 0  and their gates connected to the bit line BL 0 . In addition, the PMOS transistor P 2  and the NMOS transistor N 2  have their drains connected to the bit line BL 0  and their gates connected to the bit bar line /BL 0 . 
     In the second sense amp unit  20 , a PMOS transistor P 3  and an NMOS transistor N 3  are connected in series between the power supply voltage VDD and the ground VSS, and a PMOS transistor P 4  and an NMOS transistor N 4  are connected in series between the power supply voltage VDD and the ground VSS. The PMOS transistor P 3  and the NMOS transistor N 3  have their drains connected to the bit bar line /BL 1  and their gates connected to the bit line BL 1 . In addition, the PMOS transistor P 4  and the NMOS transistor N 4  have their drains connected to the bit line BL 1  and their gates connected to the bit bar line /BL 1 . 
     At an initial stage of the operation, the bit line BL 0 , the bit bar line /BL 0 , the bit line BL 1  and the bit bar line /BL 1  are precharged with half a power supply voltage ½ VDD, which is maintained as it is or slightly increased due to a voltage level of a data signal from a memory cell. A voltage increase ratio of the bit lines due to the voltage of the data signal is very small because of operation speed and size of the capacitor. Accordingly, the sense amplifier of the semiconductor memory device requires high sensitivity. 
     FIG. 2A is a layout diagram illustrating a conventional NMOS transistor unit of the first and second sense amp units  10 ,  20 . As illustrated in FIG. 2A, the bit line BL 0 , the bit bar line /BL 0 , the bit line BL 1  and the bit bar line /BL 1  are formed in parallel in a longitudinal direction at predetermined intervals. The NMOS transistor (N 1 )  40  of the first sense amp unit  10  is formed at the upper portion of the bit line BL 0  and the bit bar line /BL 0 , and the NMOS transistor (N 2 )  42  of the first sense amp unit  10  is formed at the lower portion thereof. The NMOS transistor (N 4 )  44  of the second sense amp unit  20  is formed at the upper portion of the bit line BL 1  and the bit bar line /BL 1 , and the NMOS transistor (N 3 )  46  of the second sense amp unit  20  is formed at the lower portion thereof. 
     On the other hand, the ground line VSS is vertically formed at the left portion of the bit line BL 0  in the NMOS transistor region  40  of the first sense amp unit  10 , vertically formed at the right portion of the bit bar line /BL 1  in the NMOS transistor region  44  of the second sense amp unit  20 , and formed between the bit bar line /BL 0  and the bit line BL 1 . 
     In the NMOS transistor region  40  of the first sense amp unit  10 , a first gate contact G 1  is formed on the bit line BL 0 , a first drain contact D 1  is formed on the bit bar line /BL 0 , and a first source contact S 1  is formed on the ground line VSS vertically formed at the left portion of the bit line BL 0 . In the NMOS transistor region  42  of the first sense amp unit  10 , a second drain contact D 2  is formed on the bit line BL 0 , a second gate contact G 2  is formed on the bit bar line /BL 0 , and a second source contact S 2  is formed on the ground line VSS vertically formed between the bit line BL 0  and the bit bar line /BL 0 . 
     In the NMOS transistor region  44  of the second sense amp unit  20 , a third drain contact D 3  is formed on the bit line BL 1 , a third gate contact G 3  is formed on the bit bar line /BL 1 , and a third source contact S 3  is formed on the ground line VSS vertically formed at the right portion of the bit bar line /BL 1 . In the NMOS transistor region  46  of the second sense amp unit  20 , a fourth gate contact G 4  is formed on the bit line BL 1 , a fourth drain contact D 4  is formed on the bit bar line /BL 1 , and a fourth source contact S 4  is formed on the ground line VSS vertically formed between the bit line BL 0  and the bit bar line /BL 0 . 
     FIG. 2B is a cross-sectional diagram taken along line II—II of FIG.  2 A. As shown in FIG. 2B, a p-type active region  52  is formed on a silicon wafer  51 , and three n+ impurity regions  53 ,  54 ,  55  are formed in the active region  52 . On the active region  52 , a first gate  56  (electrode over gate insulator) is formed between the first impurity region  53  and the second impurity region  54 , and a second gate  57  is formed between the second impurity region  54  and the third impurity region  55 . An interlayer insulating film  58  is formed over the resultant structure having the first and second gates  56 ,  57 . Contact holes (not shown) are formed to partially expose the first to third impurity regions  53 ,  54 ,  55 . A conductive material formed over the resultant structure including the contact holes is partially patterned to form first to third conducting lines  59 ,  60 ,  61 . The second drain contact D 2  is formed between the conducting line  59  and the region  53 . The second source contact S 2  and the fourth source contact S 4  are formed between the conducting line  60  and the region  54 . And the fourth drain contact D 4  is formed between the conducting line  61  and the region  55 . 
     In the conventional sense amplifier layout method, as illustrated in FIG. 2A, the upper and lower portions of one bit line pitch L respectively have one NMOS transistor. Accordingly, one NMOS transistor is provided in one sense amp pitch L. As further shown in FIGS. 2A and 2B, the drain and source contacts of each NMOS transistor lie in a line (e.g., line II—II) perpendicular to the longitudinal direction of the bit and bit bar lines. As extra material is needed when making a contact, the NMOS transistors extend beyond the sense amp pitch L, thereby increasing a layout area of the sense amplifier and decreasing a process margin. Moreover, a gate interconnection is used due to a deficient interconnection area, and thus the sense amplifier is influenced by a gate interconnection resistance, which reduces an operation speed or causes a mis-operation. 
     SUMMARY OF THE INVENTION 
     Therefore, it is an object of the present invention to provide a sense amplifier layout method of a semiconductor memory device which can decrease a layout area of a sense amplifier and increase a process margin. 
     Another object of the present invention is to provide a sense amplifier layout method of a semiconductor memory device which can increase an interconnection area, without requiring a gate interconnection. 
     In order to achieve the above-described objects of the present invention, there is provided an improved sense amplifier layout method of a semiconductor memory device. Firstly, a plurality of bit lines and bit bar lines are alternately aligned in parallel. One bit line and one bit bar line form a bit line pair. Only one MOS transistor for configuring a sense amplifier is disposed over a predetermined number of bit line pairs in the width direction, and a predetermined number of the MOS transistors are disposed over the bit line pairs in the longitudinal direction. The gates of the MOS transistors are formed over at least a portion of the plurality of bit line pairs in the width direction. Preferably, the gates of the MOS transistors are formed in a ring or rectangle shape. 
     Especially, the MOS transistors are extended over the two bit line pairs. The two bit line pairs include a first bit line, a first bit bar line, a second bit line and a second bit bar line. The first to fourth MOS transistors are aligned on the two bit line pairs in the longitudinal direction. The first and second MOS transistors compose one cross-coupled MOS, and the third and fourth MOS transistors compose the other cross-coupled MOS. 
     In the first MOS transistor, a first gate contact is formed on the first bit line, a first drain contact is formed on the first bit bar line, and a first source contact is formed on a ground line formed between the first bit line and the first bit bar line. In the second MOS transistor, a second drain contact is formed on the first bit line, a second gate contact is formed on the first bit bar line, and a second source contact is formed on the ground line formed between the first bit line and the first bit bar line. In the third MOS transistor, a third gate contact is formed on the second bit line, a third drain contact is formed on the second bit bar line, and a third source contact is formed on a ground line formed between the second bit line and the second bit bar line. In the fourth MOS transistor, a fourth drain contact is formed on the second bit line, a fourth gate contact is formed on the second bit bar line, and a fourth source contact is formed on the ground line formed between the second bit line and the second bit bar line. 
     According to the above-mentioned configuration, only one NMOS transistor is arranged on two bit line pitches (2L), thereby reducing a layout area of the sense amplifier and increasing a process margin. In addition, an interconnection area is increased by aligning one NMOS transistor at the upper and lower portions of the two bit line pitches (2L), and thus a gate interconnection is not required. It is therefore possible to improve an unstable operation of the sense amplifier resulting from a gate interconnection resistance. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become better understood with reference to the accompanying drawings which are given only by way of illustration and thus are not limitative of the present invention, wherein: 
     FIG. 1 is a circuit diagram illustrating a conventional sense amp structure of a semiconductor memory device; 
     FIG. 2A is a layout diagram illustrating a conventional NMOS transistor unit of a sense amplifier of FIG. 1; 
     FIG. 2B is a cross-sectional diagram taken along line II—II of FIG. 2A; 
     FIG. 3A is a layout diagram illustrating the NMOS transistor unit of the sense amplifier of FIG. 1 in accordance with the present invention; and 
     FIG. 3B is a cross-sectional diagram taken along line III—III of FIG.  3 A. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A sense amplifier layout method and a semiconductor memory device using the same in accordance with a preferred embodiment of the present invention Will now be described in detail with reference to the accompanying drawings. In the following description, same drawing reference numerals are used for the same elements even in different drawings, and detailed explanations thereof are omitted. 
     FIG. 3A is a layout diagram illustrating an NMOS transistor unit of a sense amplifier of FIG. 1 in accordance with the present invention. Referring to FIG. 3A, a bit line BL 0 , a bit bar line /BL 0 , a bit line BL 1  and a bit bar line /BL 1  are formed in parallel in a longitudinal direction at predetermined intervals. Here, when it is presumed that a lateral (or width direction) length of the bit line BL 0 , the bit bar line /BL 0 , the bit line BL 1  and the bit bar line /BL 1 , namely the two bit line pairs is ‘D’, D is twice as long as a bit line pitch L of FIG.  2 A. Also, the bit and bit bar lines BL 0 , /BL 0 , BL 1  and /BL 1  have a staggered step structure to provide space for forming the source and drain contacts (described below) for the NMOS transistors (also described below). 
     The NMOS transistor N 3  of a second sense amp unit  20  of FIG. 1 is aligned at the upper portions of the bit line BL 0 , the bit bar line /BL 0 , the bit line BL 1  and the bit bar line /BL 1  having the pitch D ( 400 ), and an NMOS transistor N 4  of the second sense amp unit  20  is aligned at the lower portions thereof ( 500 ). An NMOS transistor N 1  of a first sense amp unit  10  is positioned below the region where the NMOS transistor N 4  is aligned ( 200 ), and an NMOS transistor N 2  of the first sense amp unit  10  is positioned there below ( 300 ). The NMOS transistors N 1 , N 2 , N 3 , N 4  of the first and second sense amp units  10 ,  20  have one ring-shaped gate, respectively. The two pairs of two gates are aligned at the upper and lower portions of the bit line BL 0 , the bit bar line /BL 0 , the bit line BL 1  and the bit bar line /BL 1 . 
     The sense amplifier layout structure in accordance with the present invention will now be explained in detail with reference to FIG.  3 A. In the NMOS transistor region  400  of the second sense amp unit  20 , a gate contact G 13  is formed on the bit line BL 1 , a drain contact D 13  is formed on the bit bar line /BL 1 , and a source contact S 13  is formed on a ground line VSS vertically formed between the bit line BL 1  and the bit bar line /BL 1 . The gate  120  of the NMOS transistor N 3  connected to the bit line BL 1  is formed in a rectangle or ring shape on the whole upper portion of the bit line BL 0 , the bit bar line /BL 0 , the bit line BL 1  and the bit bar line /BL 1 . In the NMOS transistor region  500  of the second sense amp unit  20 , a drain contact D 14  is formed on the bit line BL 1 , a gate contact G 14  is formed on the bit bar line /BL 1 , and a source contact S 14  is formed on the ground line VSS vertically formed between the bit line BL 1  and the bit bar line /BL 1 . The gate  130  of the NMOS transistor N 4  connected to the bit bar line /BL 1  is formed in a rectangle or ring shape on the whole upper portion of the bit line BL 0 , the bit bar line /BL 0 , the bit line BL 1  and the bit bar line /BL 1 . 
     In the NMOS transistor region  200  of the first sense amp unit  20 , a gate contact G 11  is formed on the bit line BL 0 , a drain contact D 11  is formed on the bit bar line /BL 0 , and a source contact S 11  is formed on the ground line VSS vertically formed between the bit line BL 0  and the bit bar line /BL 0 . The gate  100  of the NMOS transistor N 1  connected to the bit line BL 0  is formed in a rectangle or ring shape on the whole upper portion of the bit line BL 0 , the bit bar line /BL 0 , the bit line BL 1  and the bit bar line /BL 1 . In the NMOS transistor region  300  of the first sense amp unit  10 , a drain contact D 12  is formed on the bit line BL 0 , a gate contact G 12  is formed on the bit bar line /BL 0 , and a source contact S 12  is formed on the ground line VSS vertically formed between the bit line BL 0  and the bit bar line /BL 0 . The gate  110  of the NMOS transistor N 2  connected to the bit line BL 0  is formed in a rectangle or ring shape on the whole upper portion of the bit line BL 0 , the bit bar line /BL 0 , the bit line BL 1  and the bit bar line /BL 1 . Here, the respective ring-shaped gates  100 ,  110 ,  120 ,  130  composing the NMOS transistors N 1 , N 2 , N 3 , N 4  of the first and second sense amp units  10 ,  20  are designed to share drains and gates. 
     Unlike the conventional art, the source and drain of each NMOS transistor are not arranged in a line (e.g., line III—III), perpendicular to a longitudinal direction of the bit and bit bar lines. Instead, the source and drain of each NMOS transistor lies along a line in the longitudinal direction of the bit and bit bar lines. As described above, this is made possible in part by the staggered step structure of the bit and bit bar lines as shown in FIG.  3 A. 
     FIG. 3B is a cross-sectional diagram taken along line III—III of FIG.  3 A. As shown in FIG. 3B, a p-type active region  152  is formed on a silicon wafer  151 , and three n+ impurity regions  153 ,  154 ,  155  are formed in the active region  152 . On the active region  152 , a first gate  156  (electrode over gate insulator) is formed between the first impurity region  153  and the second impurity region  154 , and a second gate  157  is formed between the second impurity region  154  and the third impurity region  155 . An interlayer insulating film  158  is formed over the resultant structure having the first and second gates  156 ,  157 . A contact hole (not shown) is formed to partially expose the second impurity region  154 . A conductive material formed over the resultant structure including the contact hole is partially patterned to form two bit line pairs  160 ,  161 ,  162  and  163  (BL 0 , /BL 0 , BL 1  and /BL 1  of FIG. 3A, respectively). 
     As discussed earlier, as compared with the conventional sense amplifier layout structure having one NMOS transistor in one bit line pitch, the present invention embodies one NMOS transistor in the two bit line pitches (2L), thereby reducing a layout area of the sense amplifier and increasing a process margin. In addition, an interconnection area is increased by aligning one NMOS transistor at the upper and lower portions of the two bit line pitches (2L), and thus a gate interconnection is not required. It is therefore possible to improve an unstable operation of the sense amplifier resulting from a gate interconnection resistance. 
     As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiment is not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are intended to be embraced by the appended claims. The above-described embodiment of the present invention relates mostly to the sense amplifier layout method of the semiconductor memory device, but the semiconductor memory device using the same is also included in the scope of the present invention.