Abstract:
A memory device is provided. The memory device includes a first control gate, a second control gate, a plurality of first charge storage elements, a plurality of second charge storage elements and a semiconductor. The plurality of first charge storage elements is beside the first control gate, and each of the first charge storage elements is located on the different side of the first control gate. The plurality of second charge storage elements is beside the second control gate. The semiconductor is located between the first and second control gates.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This is a continuation application of and claims priority benefit of patent application Ser. No. 11/760,646, filed on Jun. 8, 2007. The entirety of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification. 
    
    
     FIELD 
     This invention relates generally to memory devices. 
     BACKGROUND 
     Memory devices have seen explosive growth with the advancement of electronic applications, such as memory cards, portable electronic devices, cell phones, MP3 players, digital and video cameras, and other consumer electronics. Application requirements for low cost, power consumption and high performance are driving memory design to different architectures. Floating gate structures continue to dominate non-volatile memory technology. These structures typically use polysilicon floating gates as the storage node and are arranged in various memory arrays to achieve architectures such as NAND flash and NOR flash memory. To program and erase the memory cell, electron tunneling methods are used to place or remove electrons from the floating gate. 
       FIG. 1  shows a prior art flash memory structure  100  having a 1-bit memory cell. The memory structure  100  includes a P-type substrate  102  having N+ dopant diffused areas  103 . A tunnel oxide layer  104  is formed on P-type substrate  102  above the N+ dopant areas that function as a drain and source  103 A and  103 B, respectively. A first polysilicon layer  105  is formed on the tunnel oxide layer  104  that functions as a floating gate (floating gate  105 ). A dielectric layer  106  is formed on the floating gate layer  105  with a second polysilicon layer  107  formed on the dielectric layer  106  that functions as a control gate (control gate  107 ). Depending on the voltage applied to the control gate  107 , electron tunneling through the tunnel oxide layer  104  will place or remove electrons in the floating gate  105  to store 1-bit of data. This type of prior memory structure only stores 1-bit of data per memory cell. Because of increased density requirements in consumer electronics, there is a need for memory devices to have more than 1-bit of data per memory cell. 
     SUMMARY 
     A memory device in accordance with the present invention includes a first control gate, a second control gate, a plurality of first charge storage elements, a plurality of second charge storage elements and a semiconductor. The plurality of first charge storage elements is beside the first control gate, and each of the first charge storage elements is located on the different side of the first control gate. The plurality of second charge storage elements is beside the second control gate. The semiconductor is located between the first and second control gates. 
     According to an embodiment of the invention, each of the second charge storage elements is located on the different side of the second control gate. 
     According to an embodiment of the invention, the memory device further includes a channel region located in the semiconductor between the first and second control gates. 
     According to an embodiment of the invention, the plurality of first charge storage elements are located above the channel region and the plurality of second charge storage elements are located below the channel region. 
     According to an embodiment of the invention, the memory device further includes a dielectric layer located between the channel region and the plurality of first charge storage elements and the first control gate. 
     According to an embodiment of the invention, the memory device further includes another dielectric layer located between the channel region and the plurality of second charge storage elements and the second control gate. 
     According to an embodiment of the invention, the memory device further includes source and drain regions are located in the semiconductor beside the first control gate and the second control gate. 
     According to an embodiment of the invention, one of the source and regions partially overlaps one of the plurality of first charge storage elements and one of the plurality of second charge storage elements. 
     According to an embodiment of the invention, the first control gate is opposite to the second control gate. 
     According to an embodiment of the invention, the plurality of second charge storage elements and the second control gate are embedded in a substrate. 
     Another memory device in accordance with the present invention includes source and drain regions, a channel region between the source and drain regions, a first conductive line beside a first side of the channel region, a second conductive line beside a second side of the channel region, the second side of the channel region opposite to the first side of the channel region, a first data storage element located beside a first side of the second conductive line, and a second data storage element located beside a second side of the second conductive line, the second side of the second conductive line opposite to the first side of the second conductive line. 
     According to an embodiment of the invention, the plurality of first data storage elements are located above the channel region and the plurality of second data storage elements are located below the channel region. 
     According to an embodiment of the invention, the memory device further includes a dielectric layer located between the channel region and the plurality of first data storage elements and the first conductive line. 
     According to an embodiment of the invention, the memory device further includes another dielectric layer located between the channel region and the plurality of second data storage elements and the second conductive line. 
     According to an embodiment of the invention, one of the source and regions partially overlaps one of the plurality of first data storage elements and one of the plurality of second data storage elements. 
     According to an embodiment of the invention, the first conductive line is opposite to the second conductive line. 
     According to an embodiment of the invention, the plurality of second data storage elements and the second conductive line are embedded in a substrate. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are incorporated in and constitute part of this specification, illustrate examples and exemplary embodiments of the invention, and together with the description, serve to explain the principles of the invention. In the drawings, 
         FIG. 1  illustrates a prior art memory structure having a 1-bit memory cell. 
         FIG. 2  illustrates one example of a memory structure having a 4-bit memory cell. 
         FIGS. 3A-3D  illustrate examples of a memory device for programming each bit of a 4-bit memory cell. 
         FIGS. 4A-4D  illustrate examples of a memory device for erasing each bit of a 4-bit memory cell. 
         FIGS. 5A-5D  illustrate examples of a memory device for reading each bit of a 4-bit memory cell. 
         FIGS. 6A-6O  illustrate one example of a process method for making a memory device having a 4-bit memory cell. 
     
    
    
     DETAILED DESCRIPTION 
     Reference will now be made in detail to the exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same. The following examples disclose a memory device that increases memory density by using multi-bits per memory cell. According to one example, a non-volatile memory device includes at least one memory cell. Each memory cell is configured to store multiple bits, wherein each bit is stored in a polysilicon storage layer. In another example, the memory device includes a double gate structure that can store 4-bits per cell. Examples of such non-volatile memory devices include electrically erasable programmable read only memory EEPROM or flash memory. 
       FIG. 2  illustrates one example of a memory structure  200  having a 4-bit memory cell. The memory structure  200  includes a P-type substrate  202  with a tunnel channel layer  204 , and adjacent N+ type dopant diffused areas formed therein, which functions as a source  203 A and a drain  203 B. A first dielectric layer  206 A is formed on the tunnel channel layer  204  and source  203 A and drain  203 B. A first and second polysilicon layer are formed on the first dielectric layer  206 A, which functions as first and second floating gates  215 A and  215 B, respectively. The first and second floating gates  215 A and  215 B can store a respective 1st bit and a 2nd bit. Under the tunnel channel layer  204 , a third and fourth polysilicon layers are formed, which functions as third and fourth floating gates  205 A and  205 B, respectively. The third and second floating gates  205   a  and  205   b  can store respective 3rd bit and 4th bit. The polysilicon layer of the each of first through forth floating gates ( 215 A-B and  205 A-B) thus acts as a polysilicon charge storage layer. The first and second floating gates ( 215 A-B) are separated from the first control gate  217  by a first dielectric layer  206 A. The third and fourth floating gates ( 205 A-B) are separated by the second control gate  207  by the second dielectric layers  206 B. Examples of the dielectric layer  206 A and  206 B can include any oxide layer such as SiO2, which acts as a protection layer. 
     In operation, for programming and erasing functions, different voltage levels can be applied to the first and second control gates  217  and  207  such that electron tunneling occurs in the tunnel channel layer  204  to place or remove electrons from the first through fourth floating gates  215 A-B and  205 A-B. In this example, there are 24=16 different combinations of bits that can be stored in the memory cell. The multiple bits are thus controlled by the double control gate structure, which are formed above and below the tunnel channel layer  204  from polysilicon layer. For example, in this double control gate structure, the first control gate  217  controls the data bits stored as the 1st and 2nd bits, and the second control gate  207  controls the data bits stored as the 3rd and 4th bits. By having multi-bits per memory cell, the memory device can maximize data storage area for the memory device, which can lower costs per bit and improve scalability. 
     Various operations for the memory device having a 4-bit memory cell will now be described.  FIGS. 3A-3D  illustrate examples of a memory device for programming each bit of a 4-bit memory cell. Referring to  FIG. 3A , in this example, the 1st data bit is programmed in the first floating gate  315 A (FG 1 ) by applying a first control gate  317  (CG 1 ) voltage Vcg 1 =10V and a second control gate  307  (CG 2 ) voltage Vcg 2 =0V, along with a source  303 A voltage Vs=5V and a drain  303 B voltage Vd=0V. In this way, electrons (“e−”) move from the drain  303 B area of the memory structure to the first floating gate  315 A (FG 1 ) by channel hot electron tunneling through the tunnel channel  304  region. Referring to  FIG. 3B , in this example, the 2 nd  data bit is programmed in the second floating gate  315 B (FG 2 ) by applying a first control gate  317  (CG 1 ) voltage Vcg 1 =10V and a second control gate  307  (CG 2 ) voltage Vcg 2 =0V, along with a source  303 A voltage Vs=0V and a drain  303 B voltage Vd=5V. Electrons e− move from the source  303 A area to the second floating gate  315 B (FG 2 ) by channel hot electron tunneling through the tunnel channel  304  region. 
     Referring to  FIG. 3C , in this example, the 3rd data bit is programmed in the third floating gate  305 A (FG 3 ) by applying 0V to the first control gate  317  (CG 1 ) and 10V to the second control gate  307  (CG 2 ), along with a source  303 A voltage Vs of 5V and a drain  303 B voltage of 0V. Electrons (“e−”) move from the drain  303 B area of the memory structure to the third floating gate  305 A (FG 3 ) by channel hot electron tunneling through tunnel channel  304  region. Referring to  FIG. 3D , in this example, the 4th data bit is programmed in the fourth floating gate  305 B (FG 4 ) by applying 0V the first control gate  317  (CG 1 ) and 10V to the second control gate  307  (CG 2 ), along with a source voltage Vs  303 A of 0V and a drain voltage Vd  303 B of 5V. Electrons e− move from the source  303 A area to the fourth floating gate  305 B (FG 4 ) by channel hot electron tunneling through the tunnel channel  304  region. 
       FIGS. 4A-4D  illustrate examples of a memory device for erasing each bit of a 4-bit memory cell. Referring to  FIG. 4A , in this example, the 1st data bit is erased in the first floating gate  415 A (FG 1 ) by applying a first control gate  417  (CG 1 ) voltage Vcg 1 =−20V and a second control gate  407  (CG 2 ) voltage Vcg 2 =0V, along with a source  403 A voltage Vs=5V and a drain  403 B voltage Vd=0V. In this way, holes (“H+”) move from the source  403 A area of the memory structure to the first floating gate  415 A (FG 1 ) by band to band hot hole tunneling through the tunnel channel  404  region. The holes H+ remove electron e− charges from the first floating gate  415 A in order to erase the 1st data bit. Referring to  FIG. 4B , in this example, the 2nd data bit is erased in the second floating gate  415 B (FG 2 ) by applying a first control gate  417  (CG 1 ) voltage Vcg 1 =−20V and a second control gate  407  (CG 2 ) voltage Vcg 2 =0V, along with a source  403 A voltage Vs=0V and a drain  403 B voltage Vd=5V. Holes (“H+”) then move from the drain  403 B area of the memory structure to the second floating gate  415 B (FG 2 ) by band to band hot hole tunneling through the tunnel channel  404  region. The holes H+ remove electron e− charges from the second floating gate  415 B in order to erase the 2nd data bit. 
     Referring to  FIG. 4C , in this example, the 3rd data bit is erased in the third floating gate  405 A (FG 3 ) by applying a first control gate  417  (CG 1 ) voltage Vcg 1 =0V and a second control gate  407  (CG 2 ) voltage Vcg 2 =−20V, along with a source  403 A voltage Vs=5V and a drain  403 B voltage Vd=0V. In this way, holes (“H+”) move from the source  403 A area of the memory structure to the third floating gate  405 A (FG 3 ) by band to band hot hole tunneling through the tunnel channel  404  region. The holes H+ remove electron e− charges from the third floating gate  405 A in order to erase the 3rd data bit. Referring to  FIG. 4D , in this example, the 4th data bit is erased in the fourth floating gate  405 B (FG 4 ) by applying a first control gate  417  (CG 1 ) voltage Vcg 1 =0V and a second control gate  407  (CG 2 ) voltage Vcg 2 =−20V, along with a source  403 A voltage Vs=0V and a drain  403 B voltage Vd=5V. Holes (“H+”) then move from the drain  403 B area of the memory structure to the fourth floating gate  405 B (FG 4 ) by band to band hot hole tunneling through the tunnel channel  404  region. The holes H+ remove electron e− charges from the fourth floating gate  405 B in order to erase the 4th data bit. 
       FIGS. 5A-5D  illustrate examples of a memory device for reading each bit of a 4-bit memory cell. Referring to  FIG. 5A , in this example, the 1st data bit stored in the first floating gate  515 A (FG 1 ) is read by applying a first control gate  517  (CG 1 ) voltage Vcg 1 =6.6V and a second control gate  507  (CG 2 ) voltage Vcg 2 =0V, along with a source  503 A voltage Vs=0V and a drain  503 B voltage Vd=1.6V. In this way, the data stored in the 1st data bit of the first floating gate  515 A can be sensed or read from a bit line connected to the first floating gate  515 A (FG 1 ). Referring to  FIG. 5B , in this example, the 2nd data bit stored in the second floating gate  515 B (FG 2 ) is read by applying a first control gate  517  (CG 1 ) voltage Vcg 1 =6.6V and a second control gate  507  (CG 2 ) voltage Vcg 2 =0V, along with a source  503 A voltage Vs=1.6V and a drain  503 B voltage Vd=0V. The data stored in the 2nd data bit of the second floating gate  515 B can be sensed or read from a bit line connected to the second floating gate  515 B (FG 2 ). 
     Referring to  FIG. 5C , in this example, the 3rd data bit stored in the third floating gate  505 A (FG 3 ) is read by applying a first control gate  517  (CG 1 ) voltage Vcg 1 =0V and a second control gate  507  (CG 2 ) voltage Vcg 2 =6.6V, along with a source  503 A voltage Vs=0V and a drain  503 B voltage Vd=1.6V. In this way, the data stored in the 3rd data bit of the third floating gate  505 A can be sensed or read from a bit line connected to the third floating gate  505 A (FG 3 ). Referring to  FIG. 5D , in this example, the 4th data bit stored in the fourth floating gate  505 B (FG 4 ) is read by applying a first control gate  517  (CG 1 ) voltage Vcg 1 =0V and a second control gate  507  (CG 2 ) voltage Vcg 2 =6.6V, along with a source  503 A voltage Vs=1.6V and a drain  503 B voltage Vd=0V. The data stored in the 4th data bit of the fourth floating gate  505 B can be sensed or read from a bit line connected to the fourth floating gate  505 B (FG 4 ). 
     For the above examples of  FIGS. 3A-3D ,  4 A- 4 D, and  5 A- 5 D, a non-volatile memory can include millions of memory cells arranged in arrays and blocks, along with word lines to access rows of memory cells and bit lines to access the floating and control gates during the program, erase, and read operations. Furthermore, other circuitry and logic (not shown) can be implemented with the above described memory structure to perform such operations. 
     The process of making a non-volatile memory with multi-bits will now be described.  FIGS. 6A-6B  illustrate one example of a process method for making a memory device having a 4-bit memory cell. Referring to  FIG. 6A , a substrate  602  is provided, which can be a silicon Si substrate. The substrate  602  is etched such that the substrate  602  defines a cavity  601  shown in  FIG. 6B . Next, referring to  FIG. 6C , an oxide layer  606 B is deposited over the substrate  602  and cavity  601 . Then, portions of the oxide layer  606 B are removed by using a chemical mechanical polish technique such that the oxide layer  606 B is formed along the surface of the substrate  602  defining the cavity  601  as shown in  FIG. 6D . 
     Referring to  FIG. 6E , a polysilicon layer  627  is formed over the oxide layer  606   b  and substrate  602 . The polysilicon layer  627  is flattened or smoothed by a chemical mechanical polish process as shown in  FIG. 6F . Next, referring to  FIG. 6G , the polysilicon layer  627  is etched to form three separate areas of polysilicon, which are identified as  605 A,  607 , and  605 B and will eventually form a bottom pair of floating gates and a bottom control gates. Referring to  FIG. 611 , an oxide layer  626  is formed over the three separate areas of polysilicon  605 A,  607 , and  605 B where the oxide layer  626  forms in between areas  607  and  605 A and  607  and  605 B. The oxide layer  626  is then etched to the polysilicon areas  605 A,  607 , and  605 B, leaving sidewalls as shown in  FIG. 6I . 
     Referring to  FIG. 6J , an oxide layer  636  is formed in between oxide layer  626  over the polysilicon layer areas  605 A,  607 , and  605 B. Next, a silicon layer  604  is grown on the oxide layer  636  using an epitaxial lateral overgrowth process as shown in  FIG. 6K . The silicon layer  604  is a crystalline material, which can form a tunnel channel region for the memory device. Referring to  FIG. 6L , an oxide layer  606 A is formed over the silicon layer  604  and oxide layer  626  and a polysilicon layer  647  is formed over the oxide layer  606 A. Both the lateral edges of the oxide layer  606 A and polysilicon layer  647  are then etched as shown in  FIG. 6M . Next, material such as N+ dopants are diffused into the silicon layer  604  by ion implantation to form the source  603 A area and drain  603 B area as shown in  FIG. 6N . Referring to  FIG. 6O , the polysilicon layer  647  and oxide layer  606 A are etched to form the memory device. This memory device includes a top and bottom control gate  617  (CG 1 ) and  607  (CG 2 ), respectively, with top first and second floating gates  615 A-B (FG 1  and FG 2 ) and bottom third and fourth floating gates  605 A-B (FG 3  and FG 4 ). Separating the top gates is a first oxide layer  606 A and separating the bottom gates is a second oxide layer  606 B. Between the top and bottom gates is the tunnel channel  604  area having a source  603 A and drain  603 B areas adjacent to it. This memory device can perform the operations as described in  FIGS. 3A-3D ,  4 A- 4 D, and  5 A- 5 D. 
     Thus, a non-volatile memory with a multi-bit memory cell and a method for fabricating the same have been described. The above examples disclose a double control gate structure (top and bottom control gates) to control data bits stored in the polysilicon storage layers of the first, second, third, and fourth floating gates. The above examples, however, can be modified such that the polysilicon layer can be subdivided into any number of sections to provide additional data bit storage areas, all of which made from the polysilicon layer. In the foregoing specification, the invention has been described with reference to specific examples and embodiments. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.