Abstract:
An SRAM array local clock generator has variable delay settings that are programmable via level scan bits. Program bits from the level scan operation are decoded and used to adjust the number of delay elements in the local clock generator path.

Description:
RELATED APPLICATIONS 
   This application is related to the following patent applications filed of even dated herewith, assigned to the assignee of this application, and incorporated by reference herein: Cache Late Select Circuit, Ser. No. 10/844,296; Output Driver With Pulse to Static Converter, Ser. No. 10/844,298; Programmable Sense Amplifier Timing Generator, Ser. No. 10/844,301. 

   FIELD OF THE INVENTION 
   This invention relates to an improved programmable local clock generator for use with CMOS static RAM (SRAM), and more particularly to a local clock generator programmable with level scan bits that has a fast response to an external clock signal and high output drive power. 
   BACKGROUND 
   High speed SRAM is usually designed so that it is synchronized in its operation. That is, its read write operations are triggered and controlled by clock timing. The local clock generator for the SRAM array is, therefore, a critical part in the SRAM design. High performance SRAM requires an ability to adjust certain timing functions in place in order to allow early mode/late mode timing adjustments, and to adjust internal timing adjustments, which allow high performance with minimum timing margins. In the prior art, such timing adjustments have been implement via fuse links or EPROM. 
   SUMMARY OF THE INVENTION 
   An object of this invention is the provision of an SRAM programmable local clock generator that can be easily programmed in place, provides low delay from system clock input to local clock output, and provides high driving power. 
   Another object of the invention is the provision of an SRAM programmable local clock generator that provides a clock chopper function with variable delay settings to allow for early mode/late mode timing adjustments and also provides variable chopped width pulses to optimize internal SRAM array timing operations. 
   Briefly, this invention contemplates the provision of an SRAM array local clock generator in which variable delay settings are programmed in place via level SCAN bits. Program bits from the level SCAN operation are decoded and adjust the number of delay elements in the local clock generator path in order to adjust the timing of the leading and trailing edges of the local clock and the width of the local clock pulse. 
   These and other improvements are set forth in the following detailed description. For a better understanding of the invention with its advantages and features, refer to the description and the drawings. 

   
     DESCRIPTIONS OF THE DRAWINGS 
       FIG. 1  is a functional block diagram illustrating a state of the art SRAM system employing L1/L2 level SCANS. 
       FIG. 2  is a block diagram of a programmable SRAM local clock generator in accordance with the teachings of this invention. 
       FIG. 3  is schematic diagram of one embodiment of the generator shown in FIG.  3 . 
       FIG. 4  shows idealized waveforms illustrating timing path options for critical timing functions in an SRAM employing a programmable local clock generator in accordance with the teachings of this invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1  shows a simplified functional diagram of a CMOS SRAM with L1/L2 cycle boundary latches and a local array clock generation (Clkl GEN). In a high performance SRAM array of the type contemplated by this invention, array peripheral circuits, such as addressing, decoding, reading and writing, are designed for operation in response to dynamic pulse signals. The array local clock generator has an external clock, or so called global clock signal, from which internal dynamic timing signals are generated to drive circuits such as an address True-Complement Generator (TCG) and bit and word DEC coders. 
   Referring now  FIG. 2 , the SRAM local clock generator in accordance with this invention has a global clock input (clkg) and a local clock output (clkl_out). It also has a scan enable input (scan_enable), which enables and disables the local clock generation function for system mode or SCAN mode operation. The local clock generator variable timing is controlled from two sets of steady state logic inputs: one is the set 0 _set 3  inputs and the other is the pw 0 —pw 3  inputs. Inputs set 0 _set 3  provide four different delay settings on the clkl_out. Inputs pw 0 _pw 3  determine the output pulse width of clkl_out. It also has four adjustments. The set 0 _set 3  inputs to the clock generator are derived from a 4:1 decoder that has as its inputs mode bit  2  and mode bit  3 . Similarly, the pw 0 _pw 3  inputs to the clock generator are derived from another 4:1 decoder that has as its inputs mode bit mode bit  0  and mode bit  1 . The mode bit inputs to these decoders are provided respectively four scan only latches (not shown). It will be appreciated that the local clock generator is therefore fully programmable by means of a scan-in initialization process during a power on IPL sequence. 
   Referring now to  FIG. 3 , it shows a schematic of a specific embodiment of the array local clock generator shown in block form in FIG.  2 . The circuit is comprised of three main sections. A forward path section controls the delay from the external clock input (clkg) to the local clock output (clkl) in response to the inputs set 0 _set 3 . A trailing path section controls the pulse width of the output clock clkl in response to the inputs pw 1 _pw 3 . And a high power output section drives the output clock signal clkl. Here it should be noted the pw 3  input disables the clock chopper function and the input labeled enable_n is a scan enable function disables the local clock generator, forcing the output clkl to stay at an inactive level. 
   It should be noted that delay in the forward and trailing delay paths is generated by the switching delay of the invertors formed by complementary pFET-nFET pairs in the active signal paths and the total delay is a function of the number of invertors in the path. In the forward path, the upper most path is the default path (set 0 ) path and it has one delay element in the path between the external input clock clkg and the driver of the output clock clkl. An input to set 1 , set 2 , or set 3  activates the path to which the set is connected, which establishes a logic level at node U that disables the inverter in the default path until the input clock signal propagates through the delay elements of the selected path, thus introducing the selected delay, which is determined by the number of delay elements in the path. 
   The external clock input clkg is connected to the trailing path, as are the outputs of the set 1 , set 2  and set 3  paths. The upper most string of delay elements in the delay path is the default or nominal path, so that the number of delay elements in this path determines the nominal pulse width. If set 1 , set 2 , or set 3  path is active the logic level at the output of that path blocks propagation of the clock through the trailing path via the FET chain at the external clock input trailing path. When the external clock propagates through an active set 1 , set 2 , or set 3  active path renders the trailing path input FET chain conducting and allow the external clock signal to propagate along the trailing path. The delay introduced in the trailing path may be increased or may decreased from the nominal value by introducing additional delay elements in the delay path or reducing the number of delay elements in the delay path. In this exemplary embodiment of the invention, pw 0 , establishes the fastest delay path and thus the narrowest local clock pulse width. If pw 1  is set, the number of delay elements is increased by 2 stages and the pulse width is widen as compared to its narrowest value. If pw 2  is set, the pulse width is further increased by another four stages. 
   The output of the trailing path is coupled to node U, causing the local clock output to change from its low active state to a high inactive state until the next transition of the external input clock signal transition from high to low. The output driver stage of the local clock generator consists of large pull down NFET devices n 39 -n 40  which are driven from node W of the leading edge path. The pull up driver consists of parallel connected PFET devices p 39  and p 40 -p 41 . P 39  is driven from node W, hence is responsive to the forward path switching. Its device size is chosen to be smaller than that of p 40 -p 41 , so that it reduces loading on node w to ensure faster forward path switching. The parallel PFET devices p 40 -p 41  are much larger than p 39 , they serve as the main pull up driver. They are driven from node X, which is a parallel path to node W. This combination of parallel path pull up driver enables the clkl output to handle very large load without degrading switching performance. 
   As will be appreciated by those skilled in the art, the period of the external clock signal is much grater than pulse width of the local clock output.  FIG. 4  illustrates the range of possible variation in timing of critical timing paths possible with the programmable clock generator of this invention. 
   While the preferred embodiment of the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described herein.