Abstract:
An apparatus for detecting an edge timing of an input signal and operating on the basis of the edge timing while power consumption thereof is reduced. The apparatus includes an edge detecting circuit that detects edges of an input signal to generate an edge timing representing signal representative of edge timings of the edges, a signal processing circuit responsive to the edge timing representing signal. The edge detection circuit outputs an enable signal to enable the signal processing circuit to operate when the edge detection circuit finds one of the edges. The signal processing circuit executes a signal processing of the edge timing representing signal in response to the enable signal.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to an apparatus. More particularly, the present invention relates to an apparatus for detecting edges of an input signal to executes signal processing on the basis of edge timings.  
           [0003]    2. Description of the Related Art  
           [0004]    Edge detecting circuits are widely used for various signal processing. An edge detecting circuit is disclosed in Japanese Laid Open Patent Application (JP-A-2001 136157). The entire disclosure of the corresponding U.S. patent application Ser. No. 09/699,245, filed Oct. 27, 2000 is hereby incorporated herein in its entirety by reference. The edge detecting circuit is used in a clock signal reproducing apparatus. The clock signal reproducing apparatus is composed of a detecting circuit and a clock signal outputting circuit. The detecting circuit detects edge timings of an input signal at which the input signal is inverted. The detecting circuit quantizes the detected edge timings to a predetermined number of states. The clock signal outputting circuit outputs an outputted clock signal. A phase of the outputted clock signal is established based on the edge timings.  
           [0005]    Another edge detecting circuit for surely detecting edges of signals is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 1-260915). As shown in FIG. 1, the conventional apparatus includes flip-flop circuits  101 - 104 , inverters  105 ,  106 , delay circuits  107 - 110 , XOR gates  111 - 114 , an OR gate  115  and an address decoder  116 . The conventional apparatus detects that address signals  120 ,  121  are changed from the High level to the Low level or from the Low level to the High level.  
           [0006]    When the address signal  120  is changed from the Low level to the High level as shown in FIG. 2, the flip-flop circuit  101  detects the change to generate an output pulse. Next, when the address signal  120  is changed from the High level to the Low level, the flip-flop circuit  102  detects the change. In the conventional edge detecting circuit, even if the change to the High level from the Low level is done in the time shorter than the predetermined delay time T W , a sure edge detection signal is inputted to an enable terminal of the address decoder  116  without any separation of the output pulse.  
           [0007]    However, the conventional edge detecting circuit does not output a signal indicating edge timings of the address signals  120 ,  121 . The conventional edge detecting circuit merely detects that the address signals  120 ,  121  are changed from the High level to the Low level, or from the Low level to the High level, and only sets the address decoder  116  enable.  
           [0008]    Also, a synchronizing circuit including an edge detecting circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 4-13325). The synchronizing circuit receives a data signal, synchronizes an interior clock signal with the data signal, and samples the data signal with the synchronized clock signal. In detail, the synchronizing circuit includes a data signal edge detecting circuit, a clock signal edge detecting circuit, a synchronization judging circuit, and a clock signal selecting circuit. The data signal edge detecting circuit outputs a data signal edge detection pulse when detecting an edge of the data signal. The clock signal edge detecting circuit outputs a clock signal edge detection pulse when detecting an edge of the clock signal. The synchronization judging circuit superposes the data signal edge detection pulse and the clock signal edge detection pulse to output an asynchronous state detection pulse. The clock signal is responsive to asynchronous state detection pulse for selecting one of clock signals having different phases to output it as the interior clock signal. However, the edge timing of the data signal is not detected in the synchronizing circuit and the operation of the synchronizing circuit is not based on the edge timing.  
         SUMMARY OF THE INVENTION  
         [0009]    An object of the present invention is to provide an apparatus for detecting an edge timing and operating on the basis of the edge timing while power consumption thereof is reduced.  
           [0010]    Another object of the present invention is to provide an apparatus for detecting an edge timing and operating on the basis of the edge timing while the operation thereof is stabilized.  
           [0011]    In order to achieve an aspect of the present invention, an apparatus includes an edge detecting circuit that detects edges of an input signal to generate an edge timing representing signal representative of edge timings of the edges, a signal processing circuit responsive to the edge timing representing signal. The edge detection circuit outputs an enable signal to enable the signal processing circuit to operate when the edge detection circuit finds one of the edges. The signal processing circuit executes a signal processing of the edge timing representing signal in response to the enable signal.  
           [0012]    The edge detecting circuit preferably quantizes the edge timings to represent the edge timings in the edge timing representing signal.  
           [0013]    The enable signal preferably consists of rectangular pulses having a pulse width larger than a predetermined value.  
           [0014]    The edge detection circuit preferably detects the edges in synchronization with a clock signal, and the pulse width is larger than a cycle of the clock signal.  
           [0015]    The edge detection circuit preferably generates the enable signal based on the edge timing representing signal.  
           [0016]    The edge detection circuit preferably changes a state of the edge timing representing signal is changed only when the edge detection detects the edges.  
           [0017]    The edge detecting circuit preferably includes a plurality of sampling circuits each of which is responsive to one of clock signals for sampling the input signal in synchronization with the one of the clock signals to generate a sample signal, the clock signals having different phases each other, and an edge timing determining circuit generates the edge timing representing signal based on the sample signals received from the plurality of sampling circuits, the edge timing determining circuit determining the edge timings on the basis of whether or not two of the sample signals indicate different values.  
           [0018]    In order to achieve another aspect of the present invention, a clock signal reproducing circuit includes an edge detecting circuit which detects edges of an input signal to generate an edge timing representing signal representative of edge timings of the edges, a clock signal outputting circuit responsive to the edge timing representing signal for generating another clock signal synchronized with the input signal. The edge detection circuit outputs an enable signal to enable the clock signal outputting circuit to operate when the edge detection circuit finds one of the edges.  
           [0019]    The clock signal outputting circuit preferably selects one of a plurality of clock signals having different phases each other on the basis of the edge timing representing signal and output the one of the plurality of clock signals as the another clock signal.  
           [0020]    In the case when the edges have a present edge which is latest of the edges, and a past edge detected before the present edge, the clock signal outputting circuit preferably includes a memorizing circuit memorizing a past edge timing of the past edge, the another clock signal is outputted on the basis of edge timings of the present edge and the past edge.  
           [0021]    In order to achieve still another aspect of the present invention, a signal reproducing circuit includes an edge detecting circuit which detects edges of an input signal to generate an edge timing representing signal representative of edge timings of the edges, a clock signal outputting circuit responsive to the edge timing representing signal for generating another clock signal synchronized with the input signal, and a reproduced signal outputting circuit sampling the input signal with the another clock signal to output a reproduced signal. The edge detection circuit outputs an enable signal to enable the clock signal outputting circuit to operate when the edge detection circuit finds one of the edges.  
           [0022]    In order to achieve yet still aspect of the present invention, a method of operating an apparatus includes:  
           [0023]    detecting edges of an input signal;  
           [0024]    outputting an edge timing representing signal representative of edge timings of the edges;  
           [0025]    outputting an enable signal when one of the edges is detected; and  
           [0026]    enabling a circuit to operate in response to the edge timing representing signal.  
           [0027]    The circuit preferably outputs a clock signal synchronized with the input signal on the basis of the edge timings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0028]    [0028]FIG. 1 shows a configuration of a conventional edge detection circuit;  
         [0029]    [0029]FIG. 2 is a timing chart showing an operation of the conventional edge detection circuit;  
         [0030]    [0030]FIG. 3 shows a configuration of an apparatus of a first embodiment according to the present invention;  
         [0031]    [0031]FIG. 4 shows a configuration of a sampling circuit  1 ;  
         [0032]    [0032]FIG. 5 shows a configuration of a leading edge position detection circuit  2   1 ;  
         [0033]    [0033]FIG. 6 shows a configuration of a trailing edge position detection circuit  2   2 ;  
         [0034]    [0034]FIG. 7 is a timing chart showing the operations of the sampling circuit  1 , the leading edge position detection circuit  2   1  and the trailing edge position detection circuit  2   2 ;  
         [0035]    [0035]FIG. 8 shows the configurations of an optimized leading edge position calculator  4   1  and an optimized trailing edge position calculator  4   2 ;  
         [0036]    [0036]FIG. 9 shows a configuration of a second embodiment according to the present invention;  
         [0037]    [0037]FIG. 10 shows a configuration of a leading edge position detection circuit  7   1 ; and  
         [0038]    [0038]FIG. 11 shows a configuration of a trailing edge position detection circuit  7   2 . 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0039]    Embodiments according to the present invention will be described below with reference to the attached drawings.  
       First Embodiment  
       [0040]    An apparatus in a first embodiment is a clock signal reproducing apparatus. The apparatus generates a clock signal synchronous with an input signal which has waveform thereof distorted through a communication link. The apparatus also samples the input signal at the clock signal, and reproduces the waveform of the input signal. The configuration of the apparatus will be described below.  
         [0041]    [0041]FIG. 3 shows the apparatus in the first embodiment. The apparatus includes a sampling circuit  1 , a leading edge timing detector  2   1  and a trailing edge timing detector  2   2 .  
         [0042]    The sampling circuit  1  is triggered by n clock signals CLK 0 -CLK n−1  having different phases to sample an input signal a. In the embodiment, n=8. The sampling circuit  1  outputs sample data signals b 0 -b n−1  which is representative of the data of input signal a and synchronous to the clock signals CLK 0 -CLK n−1 .  
         [0043]    The leading edge timing detector  2   1  detects a leading edge timing of the input signal a, on the basis of the sample data signals b 0 -b n−1  to generate leading edge timing signals c 0 -c n−1  indicative of the detected leading edge timing. Moreover, the leading edge timing detector  2   1  detects an leading edge of the input signal a on the basis of the sample data signals b 0 -b n−1  to set an edge detection signal e 1  to the High level for a certain time.  
         [0044]    The trailing edge timing detector  2   2  carries out the operation similar to that of the leading edge timing detector  2   1  except the operation for detecting the trailing edge timing of the input signal a. The trailing edge timing detector  2   2  detects the trailing edge timing of the input signal a on the basis of the sample data signals b 0 -b n−1  to generate leading edge timing signals d 0 -d n−1  indicative of the detected leading edge timing. Moreover, the leading edge timing detector  2   1  detects the trailing edge of the input signal a to set an edge detection signal e 2  to the High level for a certain time.  
         [0045]    The leading edge timing signals c 0 -c n−1  the trailing edge timing signals d 0 -d n−1  and the edge detection signals e 1 , e 2  are outputted to a signal reproducing circuit  3 .  
         [0046]    The signal reproducing circuit  3  is enabled by the edge detection signals e 1 , and captures the leading edge timing signals c 0 -c n−1  when the edge detection signal e 1  is changed from the Low level to the High level. Moreover, the signal reproducing circuit  3  is enabled by the edge detection signal e 2 , and captures the trailing edge timing signals d 0 -d n−1  when the edge detection signal e 2  is changed from the Low level to the High level. The signal reproducing circuit  3  selects a clock signal which is in the most synchronous state with the input signal a from the clock signals CLK 0 -CLK n−1  on the basis of the leading edge timing of the input signal a indicated by the leading edge timing signals c 0 -c n−1  and the trailing edge timing of the input signal a indicated by the trailing edge timing signals d 0 -d n−1 . Then the signal reproducing circuit  3  outputs the selected clock signal as a selection clock signal f. Moreover, the signal reproducing circuit  3  outputs one of the sample data signals b 0  to b n−1  as a data reproduction signal g, which corresponds to a signal generated by sampling the input signal a with the selection clock signal f.  
         [0047]    In the apparatus, the signal reproducing circuit  3  is enabled by the edge detection signals e 1 , e 2  when the leading edge and the trailing edge of the input signal a are detected. When the leading edge and the trailing edge in the input signal a are detected, the signal reproducing circuit  3  is enabled to operate. When the leading edge and the trailing edge in the input signal a are not detected, the signal reproducing circuit  3  does not operate. This suppresses the consumption of the electric power of the apparatus.  
         [0048]    The apparatus of the embodiment will be described below in detail.  
         [0049]    The clock signals CLK 0  to CLK n−1 , are inputted to the sampling circuit  1 . The clock signals CLK 0  to CLK n−1  have the same cycle T and the same pulse width T W  while their phases are different from each other. The phase of the clock signal CLK 1  is delayed by 2πi/n from the clock signals CLK 0 . Here, i is an integer between 0 and n−1. The sampling circuit  1  uses the clock signals CLK 0 -CLK n−1  for sampling the input signals a.  
         [0050]    In this specification, the phase is defined as 0 at a time when the clock signal CLK 0  rises from the Low level to the High level. According to this definition, the clock signal CLK i , whose phase is delayed by 2πi/n from the clock signal CLK 0 , is pulled from the Low level up to the High level at a time when the phase is at 2πi/n.  
         [0051]    [0051]FIG. 4 shows the configuration of the sampling circuit  1 . The sampling circuit  1  includes D-flip-flops  1   0 - 1   n−1 . The input signal a is inputted to each of the D-flip-flops  1   0 - 1   n−1 . Moreover, the clock signals CLK 0  to CLK n−1  are inputted to the D-flip-flops  1   0 - 1   n−1 , respectively. The D-flip-flops  1   0 - 1   n−1  respectively use the clock signals CLK 0 -CLK n−1  for sampling the input signal a, and then output the sample signals b 0 -b n−1 , respectively. The sample signals b 0 -b n−1  are outputted to the leading edge timing detector  2   1  and the trailing edge timing detector  2   2 .  
         [0052]    As mentioned above, the leading edge timing detector  2   1  detects the leading edge timings of the input signal a, on the basis of the sample signals b 0  to b n−1 .  
         [0053]    The leading edge timings detected by the leading edge timing detector  2   1  are quantized to n states and represented by the integer between 0 and n−1. Here, the fact that the leading edge timing of the input signal a is at i implies that the input signal a is pulled up to the High level between a time when the phase is at 2πi/n and a time when the phase is at 2π(i+1)/n. Here, i is the integer between 0 and n−1. For example, let us suppose a case of i=0. The fact that the leading edge timing is at 0 implies that the input signal a rises between a time when the phase is at 0 and a time when the phase is at 2π/n. Similarly, the fact that the leading edge timing is at 1 implies that the input signal a rises between a time when the phase is at 2π/n and a time when the phase is at 2π×2/n. Here, the fact that the phase is at 2π×n/n is equivalent to the fact that the phase is at 0. That is, the fact that the leading edge timing is at n−1 implies that the input signal a rises between a time when the phase is at 2π×n−1/n and a time when the phase is at 0.  
         [0054]    The state that the leading edge timing signal c 1  is at the High level indicates the leading edge timing is at i. Here, i is the integer between 0 and n−1. That is, the leading edge timing signals c 0 -c n−1  outputted by the leading edge timing detector  2   1  indicate the leading edge timing of the input signal a. The leading edge timing signals c 0 -c n−1  are allowed to have a state that all of them are at the Low level or a state that only one of them is at the High level.  
         [0055]    [0055]FIG. 5 shows the leading edge timing detector  2   1  for generating the leading edge timing signals c 0 -c n−1 . The leading edge timing detector  2   1  is provided with AND gates  21   0 - 21   n−1 , D-flip-flops  22   0 - 22   n−1 , an OR gate  23 , and inverters  24   1 ,  24   2 .  
         [0056]    The sample signal b i+1  and an inverse of the sample signal b i  are inputted to the AND gate  21   i . Here, i is the integer between 0 and n−1. For example, for i being 0, the sample signal b 1  and the inverse of the sample signal b 0  are inputted to the AND gate  21   0 . However, it should be understood that the sample signal b n  means the sample signal b 0 . That is, the sample signal b 0  and the inverse of the sample signal b n−1  are inputted to the AND gate  21   n−1 . The output of the AND gate  21   1  becomes at the High level when the input signal a rises from the Low level to the High level between a time when the phase is at 2πi/n and a time when the phase is at 2π(i+1)/n. The outputs of the AND gates  21   0 - 21   n−1  are connected to data terminals D of the D-flip-flops  22   0 - 22   n−1 , respectively.  
         [0057]    The clock signals CLK 0 -CLK n−1  are inputted to clock terminals CLK of the D-flip-flops  22   0 - 22   n−1 , respectively. The D-flip-flops  22   0 - 22   n−1  respectively latch the outputs the AND gates  21   0 - 21   n−1  in synchronization with the leading edge of the clock signals CLK 0  to CLK n−1 , respectively.  
         [0058]    Each of the leading edge timing signals c 0 -c n−1  is outputted from an output terminal Q of each of the D-flip-flops  22   0  to  22   n−1 . The leading edge timing signal c i  is pulled up to the High level when the input signal a is pulled up to the High level between a time when the phase becomes at 2πi/n and a time when the phase becomes at 2π(i+1)/n.  
         [0059]    The output terminals Q of the D-flip-flops  22   0 - 22   n−1  are connected to an input of the OR gate  23 . An output of the OR gate  23  is connected to an input of the inverter  24   1 . An output of the inverter  24   1  is connected to an input of the inverter  24   2 . An edge detection signal e 1  is outputted from an output of the inverter  24   2 . The edge detection signal e 1  is pulled up to the High level when any one of the leading edge timing signals c 0 -c n−1  is at the High level. That is, the edge detection signal e 1  indicates that the input signal a is pulled up to the High level.  
         [0060]    On the other hand, the trailing edge timing detector  2   2  detects the trailing edge timings of the input signal a on the basis of the sample signals b 0 -b n−1 . The trailing edge timings are also quantized to n states and represented by the integer between 0 and n−1. The fact that the trailing edge timing of the input signal a is at i implies that the input signal a trails between a time when the phase is at 2πi/n and a time when the phase is at 2π(i+1)/n. The fact that the leading edge timing is at i is indicated by the fact that the leading edge timing signal d i  is at the High level.  
         [0061]    [0061]FIG. 6 shows the configuration of the trailing edge timing detector  2   2  for generating the trailing edge timing signals d 0 -d n−1 . The trailing edge timing detector  2   2  has the configuration similar to that of the leading edge timing detector  2   1 . The trailing edge timing detector  2   2  includes AND gates  25   0 - 25   n−1 , D-flip-flops  26   0 - 26   n−1 , an OR gate  27  and inverters  28   1 ,  28   2 .  
         [0062]    The sample signals b i  and an inverse of the sample signal b n+1  are inputted to the AND gates  25   1 . Here, i is the integer between 0 and n−1. For example, in a case of i=0, the sample signal b 0  and the inverse of the sample signal b 1  are inputted to the AND gate  25   0 . It should be understood that the sample signal b n  means the sample signal b 0 . That is, the sample signal b n−1  and the inverse of the sample signal b 0  are inputted to the AND gate  25   n−1 . The output of the AND gate  25   i  is pulled up to the High level when the input signal a is pulled down from the High level to the Low level between a time when the phase is at 2πi/n and a time when the phase is at 2π(i+1)/n. The outputs of the AND gates  25   0 - 25   n−1  are connected to data terminals D of the D-flip-flops  26   0 - 26   n−1 , respectively.  
         [0063]    The D-flip-flops  26   0 - 26   n−1  respectively latch the outputs of the AND gates  25   0 - 25   n−1  to output the trailing edge timing signals d 0 -d n−1  respectively, in synchronization with the leading edge of the clock signals CLK 0  to CLK n−1 , respectively.  
         [0064]    The trailing edge timing signals d 0 -d n−1  are respectively outputted from the output terminals Q of the D-flip-flops  26   0 - 26   n−1 . The trailing edge timing signal d i  among the trailing edge timing signals d 0 -d n−1  is pulled up to the High level when the input signal a is pulled down from the High level to the Low level between a time when the phase becomes at 2πi/n and a time when the phase becomes at 2π(i+1)/n.  
         [0065]    The output terminals Q of the D-flip-flops  26   0 - 26   n−1  are connected to an input of the OR gate  27 . An output of the OR gate  27  is connected to an input of the inverter  28   1 . An output of the inverter  28   1  is connected to an input of the inverter  28   2 . An edge detection signal e 2  is outputted from an output of the inverter  28   2 . The edge detection signal e 2  becomes at the High level while any one of the trailing edge timing signals d 0 -d n−1  becomes at the High level. That is, the edge detection signal e 2  indicates that the input signal a is pulled down from the Low level to the High level.  
         [0066]    The operations of the sampling circuit  1 , the leading edge timing detector  2   1  and the trailing edge timing detector  2   2  will be described below with reference to FIG. 7. In FIG. 7, n is assumed to be 8, therefore the clock signals CLK 0  to CLK n−1  are noted as the clock signals CLK 0  to CLK 7 . The sample signals b 0 -b n−1 , the leading edge timing signals c 0 -c n−1  and the trailing edge timing signals d 0 -d n−1  are similarly noted as the sample signals b 0 -b 7 , the leading edge timing signals c 0 -c 7  and the trailing edge timing signals d 0 -d 7 , respectively.  
         [0067]    At a time t&lt;t 1 , the input signal a is at the Low level. All of the sample signals b 0 -b 7  are at the Low level. While t&lt;t 1 , the input signal a does not have both the leading edge and the trailing edge. Thus, the leading edge timing signals c 0 -c 7 , the trailing edge timing signals d 0 -d 7  and the edge detection signals e 1 , e 2  are all kept at the Low level.  
         [0068]    At the time t 1 , the input signal a rises from the Low level to the High level. The time t 1  is the time between a time when the clock signal CLK 7  rises and a time when the clock signal CLK 0  rises. That is, the time t 1  is the time between a time when the phase is at 2π×7/8(=2π(n−1)/n) and a time when the phase is at 0. The leading edge timing of the input signal a is detected as 7(=n−1) by the sampling circuit  1  and the leading edge timing detector  2   1 . The process of the detection will be described below.  
         [0069]    The sampling circuit  1  samples the input signal a for each rise of the clock signals CLK 0 -CLK 7  to output the sample signals b 0 -b 7 . The sample signals b 0 -b 7  is pulled up from the Low level to the High level for rises of the clock signals CLK 0 -CLK 7 , respectively.  
         [0070]    Whether the leading edge timing signals c 0 -c n−1  become at the High level or the Low level is determined for each rise of the clock signals CLK 0 -CLK 7 . In detail, whether the leading edge timing signal c i  becomes at the High level or the Low level after the rise of the clock signal CLK i  is determined on the basis of the sample signals b i , b i+1  immediately before the rise of the clock signal CLK i . Here, i is the integer between 0 and 7(=n−1).  
         [0071]    Immediately before the rise of the clock signal CLK 0 , the sample signals b 0 , b 1  are both at the Low level. The leading edge timing signal c 0  indicates the AND of an inverse of the sample signal b 0  and the sample signal b 1 , and After the clock signal CLK 0  is pulled up to the High level, the leading edge timing signal c 0  is kept at the Low level.  
         [0072]    Similarly, the leading edge timing signals c 1 -c 6  are kept at the Low level after the rises of the respective clock signals CLK 1  to CLK 6 .  
         [0073]    On the other hand, immediately before the rise of the clock signal CLK 7 , the sample signals b 7 , b 0  are at the Low level and the High level, respectively. The leading edge timing signal c 7  indicates the AND of the sample signal b 0  and an inverse of the sample signal b 7 . Thus, the leading edge timing signal c 7  is changed from the Low level to the High level at the time of the rise of the clock signal CLK 7 .  
         [0074]    In this way, the leading edge timing signals c 0 -c 6  become at the Low level, and the leading edge timing signal c 7  becomes at the High level. This implies that the leading edge timing of the input signal a is detected as 7. In this way, the leading edge timing of the input signal a is detected as 7(=n−1) by the sampling circuit  1  and the leading edge timing detector  2   1 .  
         [0075]    The data detection signal e 1 , which indicates the OR of the leading edge timing signals c 0 -c 7 , is pulled up to the High level, in response to the pull-up of the leading edge timing signal c 7 . The timing when the data detection signal e 1  is pulled up to the High level is delayed by a certain time. This delay time is caused by the OR gate  23  and the inverters  24   1 ,  24   2  shown in FIG. 5. The inverters  24   1 ,  24   2  are used for generating the delay time.  
         [0076]    The delay time optimizes the timing when the data detection signal e 1  is pulled up to the High level for the capture of the leading edge timing signals c 0 -c 7 . As described later, the signal reproducing circuit  3  captures the leading edge timing signals c 0 -c 7  when the data detection signal e 1  is changed to the High level. The delay in the data detection signal e 1  ensures the capture of the leading edge timing signals c 0 -c 7 .  
         [0077]    The data detection signal e 1  is designed not to return to the Low level within at least a time shorter than the period T of the clock signals CLK 0  to CLK 7  once the data detection signal e 1  is pulled up to the High level. That is, a pulse width of a rectangular pulse contained in the data detection signal e 1  is always equal to or longer than the period T of the clock signals CLK 0  to CLK 7 . The reason is as follows. The leading edge timing signals c 0 -c 7  on which the data detection signal e 1  is generated, are never changed to the Low level within the time equal to the period T of the clock signals CLK 0 -CLK 7 , once the leading edge timing signals c 0 -c 7  are changed to the High level. The states of the leading edge timing signals c 0 -c 7  are changed only for the respective rises of the clock signals CLK 0  to CLK 7 . Thus, once the leading edge timing signals c 0 -c 7  are changed to the High level, the leading edge timing signals c 0 -c 7  are never pulled down to the Low level within the time shorter than the period T of the clock signals CLK 0  to CLK 7 .  
         [0078]    The pulse width equal to or longer than the period T of the clock signals CLK 0 -CLK 7  contributes to the stable operation of the apparatus in the embodiment.  
         [0079]    As shown in FIG. 7, it is assumed that the input signal a, which rises from the Low level to the High level at the time t 1 , is pulled down to the Low level at a time t 2 . The time t 2  is the time between the time when the clock signal CLK 7  rises and the time when the clock signal CLK 0  rises. That is, the time t 2  is the time between the time when the phase is at 2π×7/8(=2π(n−1)/n) and the time when the phase is at 0. The trailing edge timing of the input signal a is detected as 7(=n−1) by the sampling circuit  1  and the trailing edge timing detector  2   2 . The process of the detection of the trailing edge timing is equal to the above-mentioned process in which the leading edge timing of the input signal a is detected as 7(=n−1).  
         [0080]    The trailing edge timing detector  2   2  keeps the trailing edge timing signals d 0 -d 6  at the Low level, and pulls the trailing edge timing signal d 7  up to the High level when the clock signal CLK 7  rises. That is, the trailing edge timing detector  2   2  detects the trailing edge timing of the input signal a as 7(=n−1).  
         [0081]    Moreover, the trailing edge timing detector  2   2  pulls up a data detection signal e 2  to the High level at a timing that is delayed by a certain delay time from a timing when the trailing edge timing signal d 7  is changed to the High level. The pulse width of the data detection signal e 2  is equal to or longer than the period T of the clock signals CLK 0  to CLK 7  from the same reason of the data detection signal e 1 .  
         [0082]    The leading edge timing signals c 0 -c n−1 , the edge detection signal e 1 , the trailing edge timing signals d 0 -d n−1 , and the edge detection signal e 2  are inputted to the signal reproducing circuit  3 .  
         [0083]    As shown in FIG. 3, the signal reproducing circuit  3  includes a most likely leading edge timing calculator  4   1 , a most likely trailing edge timing calculator  4   2 , a clock selection circuit  5  and an output circuit  6 . The most likely leading edge timing calculator  4   1  includes an edge timing comparator  41   1  and an edge memory circuit  42   1 . The most likely trailing edge timing calculator  4   2  includes an edge timing comparator  41   2  and an edge memory circuit  42   2 .  
         [0084]    The most likely leading edge timing calculator  4   1  determines the most likely edge timing which is most likely for the leading edge timing of the input signal a, on the basis of the latest leading edge timing detected by the leading edge timing detector  2   1 .  
         [0085]    The latest leading edge timing detected by the leading edge timing detector  2   1  is easily affected by noise and jitter on the input signal a. Even if the leading edge timing detector  2   1  detects the rapid change in the leading edge timing, it may result from the noise and the jitter.  
         [0086]    In order to reduce the influence of the noise and the jitter, the most likely leading edge timing calculator  4   1  carries out the following operation. The most likely leading edge timing of the input signal a is stored in the edge memory circuit  42   1 . The edge timing comparator  41   1  compares the stored most likely leading edge timing with the latest leading edge timing detected by the leading edge timing detector  2   1 . Then, the most likely leading edge timing is gradually adjusted. The most likely leading edge timing is sent to the clock selection circuit  5  by using a most likely leading edge timing signal h 1 .  
         [0087]    The most likely leading edge timing calculator  4   1  determines the most likely leading edge timing only when the edge detection signal e 1  is changed from the Low level to the High level. That is, the most likely leading edge timing calculator  4   1  determines the most likely leading edge timing only when the leading edge is detected from the input signal a. Such the operation suppresses the consumption of the electric power in the most likely leading edge timing calculator  4   1 .  
         [0088]    [0088]FIG. 8 shows the configuration of the most likely leading edge timing calculator  4   1 . As mentioned above, the most likely leading edge timing calculator  4   1  includes the edge timing comparator  41   1  and the edge timing memorizing circuit  42   1 . The edge timing comparator  41   1  includes a comparator  43   1 , an addition circuit  44   1 , a register  45   1  and a most likely edge timing adjusting circuit  46   1 .  
         [0089]    As mentioned above, the edge timing memorizing circuit  42   1  stores the most likely leading edge timing. The most likely leading edge timing is also quantized to n states in the same way that the leading edge timing detected by the leading edge timing detector  2   1  is quantized. The most likely leading edge timing is represented by an integer between 0 and n−1.  
         [0090]    The register  45   1  stores an integer value C. The integer value C is deviated larger apart from 0 as a period while the most likely leading edge timing and the detected leading edge timing are different from each other is longer. A positive or negative value of the integer value C indicates whether the detected leading edge timing is temporally located before or after the most likely leading edge timing. The integer value C is referred when the most likely leading edge timing is adjusted.  
         [0091]    The leading edge timing signals c 0 -c n−1  indicative of the leading edge timing detected by the leading edge timing detector  2   1  and a most likely leading edge timing signal j 1  indicative of the most likely leading edge timing are inputted to the comparator  43   1 . The comparator  43   1  compares the leading edge timing with the most likely leading edge timing.  
         [0092]    The comparator  43   1  outputs a comparison output value A on the basis of the compared result. When the leading edge timing is defined as i 1  and the most likely leading edge timing is defined as i 2 , the comparison output value A is determined as follows. If i 1 &lt;i 2 , the comparator  43   1  outputs −1 as the comparison output value A. If i 1 =i 2 , the comparator  43   1  outputs 0 as the comparison output value A. And, if i 1 &gt;i 2 , the comparator  43   1  outputs +1 as the comparison output value A.  
         [0093]    The addition circuit  44   1  adds the comparison output value A and the integer value C held by the register  45   1  to output an addition value B to the register  45   1 . The register  45   1  captures the addition value B to replace the integer value C held therein to the addition value B when the edge detection signal e 1  is pulled up to the High level. The register  45   1  outputs the integer value C to the most likely edge timing adjusting circuit  46   1 .  
         [0094]    The most likely edge timing adjusting circuit  46   1  outputs an adjustment instruction signal k 1  for instructing to adjust the most likely leading edge timing to the edge timing memorizing circuit  42   1  in response to the integer value C. When the integer value C reaches a predetermined upper limit, the most likely edge timing adjusting circuit  46   1  outputs an adjustment instruction signal k 1  for instructing to increase the most likely leading edge timing by 1 to the edge timing memorizing circuit  42   1 . Also, when the integer value C reaches a predetermined lower limit, the most likely edge timing adjusting circuit  46   1  outputs the adjustment instruction signal k 1  for instructing to decrease the most likely leading edge timing by 1.  
         [0095]    The edge timing memorizing circuit  42   1  increase or decrease to adjust the most likely leading edge timing stored therein on the basis of the adjustment instruction signal k 1 .  
         [0096]    From the above-mentioned processes, the most likely leading edge timing calculator  4   1  determines the most likely leading edge of the input signal a, while reducing the influence of the noise and the jitter of the input signal a.  
         [0097]    Also, the most likely trailing edge timing calculator  4   2  determines the most likely trailing edge timing which is most likely for the trailing edge timing of the input signal a on the basis of the latest trailing edge timing detected by the trailing edge timing detector  2   2 .  
         [0098]    The most likely trailing edge timing is also quantized to n states in the same way that the trailing edge timing detected by the trailing edge timing detector  2   2  is quantized, and represented by the integer between 0 and n−1.  
         [0099]    The most likely trailing edge timing calculator  4   2  carries out the following operation. The most likely trailing edge timing is stored in the edge timing memorizing circuit  42   2 . The edge comparator  43   2  compares the most likely trailing edge timing with the latest trailing edge timing detected by the trailing edge timing detector  2   2 . The most likely trailing edge timing is gradually adjusted.  
         [0100]    The most likely trailing edge timing calculator  4   2  includes an edge timing comparator  41   2  and an edge timing memorizing circuit  42   2 , as shown in FIG. 8. The edge timing comparator  41   2  includes a comparator  43   2 , an addition circuit  44   2 , a register  45   2  and an most likely edge timing adjusting circuit  46   2 . As shown in FIG. 8, the circuit configuration of the most likely trailing edge timing calculator  4   2  is identical to that of the most likely leading edge timing calculator  4   1  except for the signals which are inputted to and outputted from the most likely trailing edge timing calculator  4   2 . Also, the operation of the most likely trailing edge timing calculator  4   2  is identical to that of the most likely leading edge timing calculator  4   1  except for the signals which are inputted to and outputted from the most likely trailing edge timing calculator  4   2 . Instead of the input of the leading edge timing signals c 0 -c n−1 , the trailing edge timing signals d 0 -d n−1  are inputted to the most likely trailing edge timing calculator  4   2 . The most likely trailing edge timing calculator  4   2  adjusts the most likely trailing edge timing stored in the edge timing memorizing circuit  42   2 , on the basis of the trailing edge timing signals d 0 -d n−1 .  
         [0101]    The most likely leading edge timing and the most likely trailing edge timing, which are stored in the edge timing memory circuits  42   1 ,  42   2 , respectively, are sent to the clock selection circuit  5  on the most likely leading edge timing signal h 1  and the most likely trailing edge timing signal h 2 , respectively.  
         [0102]    The clock selection circuit  5  selects the most suitable one for the sampling operation of the input signal a, from among the clock signals CLK 0 -CLK n−1  on the basis of the most likely leading edge timing and the most likely trailing edge timing. The clock selection circuit  5  selects the one clock signal from the clock signals CLK 0 -CLK n−1  such that the leading edge timing of the selected clock signal is the closest to the middle between the most likely leading edge timing and the most likely trailing edge timing.  
         [0103]    Let us suppose that the selected clock signal is a clock signal CLK x ,  
         [0104]    if k 1 ≧k 2  x=[(k 1 +k 2 +n)/2],  
         [0105]    if k 1 &lt;k 2 , x=[(k 1 +k 2 )/2],  
         [0106]    where k 1  is the most likely leading edge timing, and k 2  is the most likely trailing edge timing, and [X] is the Gauss&#39; notation, which implies the maximum integer that does not exceed X.  
         [0107]    The clock selection circuit  5  selects one of the clock signals CLK 0 -CLk n−1  to output a clock selection signal  1  indicative of the selected clock signal CLK x  to the output circuit  6 .  
         [0108]    The output circuit  6  outputs the selected clock signal CLK x  as a selection clock signal f. Moreover, the output circuit  6  outputs one of the sample signals b 0  to b n−1  as a data reproduction signal g on the basis of the selection clock signal f. The data reproduction signal g is substantially identical to a signal generated by sampling the input signal a with the selected clock signal. That is, let us suppose that the selected clock is the clock signal CLK x . The output circuit  6  outputs a sample signal b x  among the sample signals b 0  to b n−1 , as the data reproduction signal g. The data reproduction signal g is the signal synchronous with the clock signal CLK x , in which the original waveform of the input signal a is reproduced.  
         [0109]    As mentioned above, the apparatus in the embodiment generates the clock signal f synchronous with the input signal a. Moreover, the apparatus samples the input signal a on the basis of the clock signal f, and reproduces the waveform of the input signal a.  
         [0110]    In this embodiment, the signal reproducing circuit  3  is operated only when the leading edge and the trailing edge are detected in the input signal a. When the leading edge and the trailing edge are not detected from the input signal a, the signal reproducing circuit  3  is not operated. Thus, the consumption of the electric power is suppressed in the apparatus.  
       Second Embodiment  
       [0111]    [0111]FIG. 9 shows an apparatus in a second embodiment according to the present invention. The configuration of the apparatus in the second embodiment is identical to that of the apparatus in the first embodiment except for that the leading edge timing detector  2   1  and the trailing edge timing detector  2   2  are respectively replaced by a leading edge timing detector  7   1  and a trailing edge timing detector  7   2 .  
         [0112]    The leading edge timing detector  7   1  detects the leading edge timing of the input signal a to output leading edge timing detection signals c 0 ′-c n−1 ′ indicative of the leading edge timing of the input signal a.  
         [0113]    The leading edge timing detection signals c 0 ′-c n−1 ′ outputted by the leading edge timing detector  7   1  are different from the leading edge timing signals c 0 -c n−1  in the first embodiment. The leading edge timing detection signals c 0 ′-c n−1 ′ are kept unchanged unless the input signal a rises from the Low level to the High level. That is, the leading edge timing detection signals c 0 -c n−1  outputted by the leading edge timing detector  2   1  return back to the Low level in synchronization with the clock signals CLK 0 -CLK n−1  when the input signal a returns back to the Low level. On the other hand, the states of the leading edge timing detection signals c 0 ′-c n−1 ′ outputted by the leading edge timing detector  7   1  are not changed unless the leading edge is detected from the input signal a. This increases the margin of the operational timing of the signal reproducing circuit  3  for capturing and processing the leading edge timing detection signals c 0 ′-c n−1 ′, and thereby stabilizes the operation of the signal reproducing circuit  3 .  
         [0114]    [0114]FIG. 10 shows the leading edge timing detector  7   1 . The leading edge timing detector  7   1  includes AND gates  71   0 - 71   n−1 , D-flip-flops  72   0 - 72   n−1 , an OR gate  73 , inverters  74   1 ,  74   2 , D-flip-flops  75   0 - 75   n−1  and inverters  76   1 ,  76   2 .  
         [0115]    An inverse of the sample signal b i  and the sample signal b i+1 , which are outputted by the sampling circuit  1 , are inputted to the AND gate  71   i . Here, i is the integer between 0 and n−1. For example, in a case of i=0, the sample signal b 1  and the inverse of the sample signal b 0  are inputted to the AND gate  71   0 . It should be understood that the sample signal b n  means the sample signal b 0 . That is, the sample signal b 0  and the inverse of the sample signal b n−1  are inputted to the AND gate  71   n−1 . The outputs of the AND gates  71   0 - 71   n−1  are connected to data terminals D of the D-flip-flops  72   0 - 72   n−1 , respectively.  
         [0116]    The clock signals CLK 0 -CLK n−1  are inputted to clock terminals CLK of the D-flip-flops  72   0 - 72   n−1 , respectively. The D-flip-flops  72   0 - 72   n−1  respectively latch the outputs the AND gates  71   0 - 71   n−1  in synchronization with the leading edge of the clock signals CLK 0 -CLK n−1  respectively.  
         [0117]    Output terminals Q of the D-flip-flops  72   0 - 72   n−1  are connected to inputs of the OR gate  73 . An output of the OR gate  73  is connected to an input of the inverter  74   1 . An output of the inverter  74   1  is connected to an input of the inverter  74   2 . An output of the inverter  74   2  is connected to clock terminals CLK of the D-flip-flops  75   0 - 75   n−1 .  
         [0118]    The inverters  74   1 ,  74   2  delay the signal outputted by the OR gate  73  by a certain delay time so that the D-flip-flops  75   0 - 75   n−1  latch the signals outputted from the output terminals Q of the D-flip-flops  72   0 - 72   n−1  at proper timings.  
         [0119]    The data terminals D of the D-flip-flops  75   0 - 75   n−1  are connected to the output terminals Q of the D-flip-flops  72   0 - 72   n−1 , respectively. The D-flip-flops  75   0 - 75   n−1  output the leading edge timing detection signals c 0 , to c n−1 , from the output terminals Q.  
         [0120]    An output of the inverter  74   2  is connected to an input of the inverter  76   1 . An output of the inverter  76   1  is connected to an input of the inverter  76   2 . An edge detection signal e 1 ′ is outputted from an output of the inverter  76   2 .  
         [0121]    The inverters  76   1 ,  76   2  delay the signal outputted from the inverter  74   2  by a certain delay time so that the signal reproducing circuit  3  latches the leading edge timing detection signals c 0 ′-c n−1 ′ at proper timings.  
         [0122]    The leading edge timing detection signals c 0 ′-c n−1 ′, which is indicative of the leading edge timing of the input signal a, are outputted to the signal reproducing circuit  3 .  
         [0123]    On the other hand, FIG. 11 shows the configuration of the trailing edge timing detector  7   2 . The trailing edge timing detector  7   2  includes AND gates  81   0 - 81   n−1 , D-flip-flops  82   0 - 82   n−1 , an OR gate  83 , inverters  84   1 ,  84   2 , D-flip-flops  85   0 - 85   n−1  and inverters  86   1 ,  86   2 .  
         [0124]    The trailing edge timing detector  7   2  has the configuration identical to that of the leading edge timing detector  7   1  and carries out the operation identical to the respectively except for that the trailing edge timing detector  7   2  detects the trailing edge timing of the input signal a to generate the trailing edge timing signals d 0 ′-d n−1 ′ indicative of the trailing edge timing. The detailed explanation of the trailing edge timing detector  7   2  is not provided in the following.  
         [0125]    In the apparatus in the second embodiment, the consumption of the electric power is suppressed similarly to the apparatus in the first embodiment. Moreover, the apparatus in the second embodiment is higher in operational stableness than the apparatus in the first embodiment.  
         [0126]    As described, the present invention reduces the consumptive electric power of the apparatus that carries out the operation based on the edge timing.  
         [0127]    Also, the present invention stabilizes the operation of the apparatus that carries out the operation based on the edge timing.  
         [0128]    Although the invention has been described in its preferred form with a certain degree of particularity, it is understood that the present disclosure of the preferred form has been changed in the details of construction and the combination and arrangement of parts may be resorted to without departing from the spirit and the scope of the invention as hereinafter claimed.