Abstract:
A system and method for controlling a digital pulse-width modulated power converter achieves a fast large-signal transient response while maintaining a slow response near the steady-state operating point in order to assure stability and to reduce the system&#39;s susceptibility to noise. Digital output error samples are processed through a gain scheduling block that applies a non-linear gain function to produce a weak loop response when the system is near its steady-state equilibrium point and a strong loop response when large transients are encountered. The resulting system maintains a fast transient response to large error signals while reducing noise and loop jittering and assuring loop stability.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The invention relates generally to the field of power converters controlled through digital pulse-width modulation (PWM). More particularly, the invention relates to a digital control scheme for PWM converters that uses non-linear gain scheduling to achieve a fast transient response while maintaining a slow response near the equilibrium point to ensure stability and reduce sensitivity to noise. 
         [0003]    2. Description of Related Art 
         [0004]    The use of digital pulse width modulation (DPWM) to control the output of a switching power converter is well known in the art. For example,  FIG. 1  depicts a block diagram of a typical power conversion system in which the output  104  of a power stage  102  is controlled by a DPWM module  114 . An error circuit  108  computes a difference between the output  104  of the power stage and a reference voltage  106 . The error signal is digitized by an analog-to-digital converter (ADC)  110 . The ADC output is filtered by a compensator circuit  112  that generally has a proportional-integral-differential (PID) character. The output of the compensator filter  112  then drives a digital pulse width modulator  114  that controls the switching cycles of the power stage  102 . 
         [0005]    One of the challenges faced by power converter designers is providing a fast response time while maintaining system stability against oscillation and minimizing overshoot. To address this issue, some designers employ non-linear methods. For example,  FIG. 2  illustrates a non-linear control approach taken by some designers that comprises introducing a window comparator circuit  202  in parallel with the compensator filter  112 . For small transients, the output of the compensator filter passes essentially unmodified to the DPWM for normal linear control operation. But when a large transient occurs, the window comparator  202  will notify the DPWM controller  114 , which may make a decision to respond immediately before the end of the current switching cycle. While such a method may provide a fast transient response, it is essentially a hysteretic control approach, which makes it susceptible to stability problems. Accordingly, it would be desirable to provide a non-linear control approach that maintains a fast transient response while also suppressing oscillation and jittering around the steady state operating point. 
       SUMMARY OF THE INVENTION 
       [0006]    An embodiment of a digital pulse-width modulation (DPWM) control system in accordance with the present invention includes a power stage comprising an input voltage port, an output voltage port, and an input control port configured to receive a DPWM control waveform. The voltage output from the output voltage port of the power stage is routed to an error sampling block that comprises an analog-to-digital converter (ADC) and an error comparison circuit. The output of the error sampling block is a digital error signal that is related to the difference between the power stage output voltage and a reference voltage. The digital error signal is then routed to a gain scheduling block that applies a non-linear gain function to the digital error signal. Non-linearity of the gain function means that the gain response as a function of the amplitude of the input digital error signal cannot be described by a straight line having a single, constant slope. In one embodiment, the non-linear gain function has a profile that increases slowly as a function of input amplitude for error signal magnitudes that are small. It then increases quickly (with a steeper slope) as a function of input amplitude for error magnitudes that lie in a medium range. It then increases slowly (with a shallower slope) with input amplitude for error magnitudes that are relatively large. 
         [0007]    Upon exiting the gain scheduling block, the gain-scheduled error signal is routed to a compensator filter. The compensator filter preferably has a proportional-integral-differential (PID) characteristic, although filters having other characteristics would also fall within the scope and spirit of the present invention. The filtered signal is then used to drive a DPWM module that synthesizes a DPWM control waveform that is operatively coupled to the input control port of the power stage. The closed-loop DPWM control system thus acts to maintain the output voltage of the power stage near the reference voltage. 
         [0008]    In one embodiment of a DPWM control system in accordance with the present invention, the error sampling block is configured to first digitize the output voltage of the power stage in the ADC and then to subtract a digital reference voltage sample to create the digital error signal. In another embodiment, the error sampling block is configured to first subtract an analog reference voltage from the output voltage of the power stage to create a difference voltage. The difference voltage is then digitized by the analog-to-digital converter to create a digital error signal. Other methods of preparing digital error samples that are related to the difference between the power stage output and a reference voltage are possible and would also fall within the scope and spirit of the present invention. 
         [0009]    The power stage is preferably a switching power converter such as a buck converter or a boost converter, having an internal switching element such as a field-effect transistor (FET), and an output filter that generally comprises at least one capacitor and at least one inductor. The internal switching element operates to selectively connect the input voltage port to the output filter to produce an output voltage that is related to the duty cycle of the switching element. However, other types of power stages that can be controlled using pulse width modulation may also be used and would similarly fall within the scope and spirit of the present invention. 
         [0010]    In one embodiment of a DPWM control system in accordance with the present invention, the gain scheduling block is configured to apply a non-linear gain function that is a piece-wise linear function of input amplitude. The piece-wise linear function includes a first linear portion having a slope of α 1  for input amplitudes less than a 1 , where α 1  and a 1  are real numbers. For input amplitudes between and including a 1  and a 2 , where a 2  is greater than a 1 , the piece-wise linear function has a slope of α 2 . Then for input amplitudes greater than a 2 , the piece-wise linear function has a slope of a 3 . Both slopes α 1  and α 3  are less than slope α 2 . 
         [0011]    In another embodiment of a DPWM control system in accordance with the present invention, the gain scheduling block is configured to apply a piece-wise linear gain function that applies a gain of zero for input amplitudes less than a 1  and a gain with a slope of α 1  for input amplitudes greater than or equal to a 1 . 
         [0012]    In still another embodiment, the gain scheduling block is configured to apply a piece-wise linear gain function that applies a gain with a slope of α 1  for input amplitudes less than a 1  and a flat (zero-slope) gain of α 1 *a 1  for input amplitudes greater than or equal to a 1 . 
         [0013]    In some embodiments, the compensator filter is configured to have a response function given by d[n]=d[n−1]+b 0 *e[n]−b 1 *e[n−1]+b 2 *e[n−2], where d[n] is an output of the compensator filter at a current sample time t; d[n−1] is the output of the compensator filter at the sample time t−1; e[n] is the gain-scheduled error signal at the current sample time t; e[n−1] is the gain-scheduled error signal at the sample time t−1; e[n−2] is the gain-scheduled error signal at a sample time t−2; and b 0 , b 1 , and b 2  are filter coefficients. In some embodiments, the filter coefficients may be programmable. 
         [0014]    Those skilled in the art will realize other applications and benefits of the invention described herein by a study of the detailed description below and the attached drawings, which will first be described briefly. Reference designators that appear in more than one drawing refer to common elements that appear in more than one drawing. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  is a block diagram of a typical power converter of the prior art controlled by digital PWM circuit; 
           [0016]      FIG. 2  is a block diagram of a non-linear control approach of the prior art that employs a window comparator; 
           [0017]      FIGS. 3   a  and  3   b  are a block diagrams of power converters controlled by digital PWM circuits wherein the system employs non-linear gain scheduling in accordance with alternative embodiments of the present invention; 
           [0018]      FIG. 4  is a plot of output gain as a function of input signal amplitude for a gain scheduling block in accordance with an embodiment of the present invention; 
           [0019]      FIG. 5  is a plot of output gain as a function of input signal amplitude for a gain scheduling block in accordance with an alternative embodiment of the present invention 
           [0020]      FIG. 6  is a plot representing an alternative embodiment of a gain scheduling block in accordance with the present invention; 
           [0021]      FIG. 7  is a plot of normalized gain as a function of input signal amplitude for the gain scheduling block embodiment illustrated in  FIG. 6 ; 
           [0022]      FIG. 8  is a plot representing another alternative embodiment of a gain scheduling block in accordance with the present invention; 
           [0023]      FIG. 9  is a plot of normalized gain as a function of input signal amplitude for the gain scheduling block embodiment illustrated in  FIG. 8 ; 
           [0024]      FIG. 10  is a plot representing yet another alternative embodiment of a gain scheduling block in accordance with the present invention; 
           [0025]      FIG. 11  is a plot of normalized gain as a function of input signal amplitude for the gain scheduling block embodiment illustrated in  FIG. 10 ; 
           [0026]      FIG. 12  is a block diagram of a digital pulse-width modulated power converter in accordance with an embodiment of the present invention; and 
           [0027]      FIG. 13   a  is a plot of the measured transient response of an exemplary power converter system employing no gain scheduling; and 
           [0028]      FIG. 13   b  is a plot of the measured transient response of an exemplary power converter system employing gain scheduling in accordance with an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0029]    An embodiment of a digital PWM control system in accordance with the present invention is illustrated in  FIG. 3   a  and introduces a non-linear gain scheduling block (GSB)  302  into the control loop. The output  104  of the power stage  102  is fed into an error comparison circuit  108  that calculates an error signal based on the difference between the power stage output  104  and a reference voltage  106 . The error signal is digitized by an ADC  110  to create a digital error signal  316 . The combination of the error comparison signal  108  and the ADC  110  is identified as the error sampling block  350 . The digital error signal  316  is then fed to a gain scheduling block  302  that applies a non-linear input-to-output characteristic, described in further detail below, to the digitized error signal. The processed error signal is then fed through a compensator filter  112 , which may have a standard PID character, that in turn drives a digital PWM controller  114  that controls the switching of the power stage  102 . 
         [0030]    In one embodiment of a digital PWM control system in accordance with the present invention, the compensator filter  112  has a response function that is described as follows: 
         [0000]        d[n]=d[n− 1]+ b 0* e[n]−b 1* e[n− 1]+ b 2* e[n− 2], 
         [0000]    where d[n] refers to an output sample from the compensator filter, e[n] refers to an input sample to the compensator filter, and b 0 , b 1 , and b 2  are filter coefficients that are selected depending on the particular performance requirements of the system. In some embodiments, the filter coefficients may be programmable in order to add design flexibility. 
         [0031]    Of course, other topologies of the PWM control loop are also possible and would fall within the scope and spirit of the present invention. For example,  FIG. 3   b  illustrates an alternative embodiment of a PWM control system in accordance with the present invention that performs the error subtraction operation in the digital domain. In this embodiment, the error sampling block  360  comprises an ADC  312  and a digital error comparison circuit  310 . The output  104  of the power stage is digitized by the ADC  312 , and the digital output of the ADC is then compared with a digital reference  314  in the digital error comparison circuit  310  to create a digital error signal  316  that is then processed by the gain scheduling block  302 . The combination of the error comparison block  310  and the ADC  312  is referred to herein as the error sampling block and may be configured as shown in  FIG. 3   a , wherein the error term is calculated in the analog domain, or as shown in  FIG. 3   b , wherein the error term is calculated in the digital domain. Other variations of the control loop topology should be readily apparent to one skilled in the art and would similarly fall within the scope and spirit of the present invention. 
         [0032]      FIG. 4  depicts the general response character of an embodiment of the gain scheduling block in accordance with the present invention. The input level to the gain scheduling block is shown along horizontal axis  402 , while the output level is shown along the vertical axis  404 . The gain response curve  406  has a non-linear character with a low gain in the region  408  around the steady-state operating point and a large gain in the regions  410  that are further away from the steady-state operating point. Essentially, the gain increases slowly with amplitude for low signal amplitudes, increases quickly with amplitude for medium-range amplitudes, and then increases slowly again for large signal amplitudes. The small gain near the operating point assures the stability of the system and minimizes its susceptibility to oscillations and noise-induced jittering, while the large gain at medium amplitudes out provides a fast response time. The gain roll-off at large signal amplitudes simulates gain saturation. 
         [0033]    A practical implementation of a response curve for a gain scheduling block in accordance with an embodiment of the present invention is depicted in  FIG. 5 . In this implementation, a piecewise linear response curve  502  is provided that has the general characteristics of the curve depicted in  FIG. 4  but is also simple to implement in a digital system. Response curve  502  is described by three different slopes: α 1 , depicted at  504 , α 2 , depicted at  506 , and α 3 , depicted at  508 . The response function, f(e), can be described in terms of error input amplitude, e, as follows: 
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         [0000]    where a 1 , b 1 , a 2 , and b 2  are the Cartesian coordinates of the points at which the slope changes, as indicated in  FIG. 5 . The slope α 1  is chosen to provide small gain when the output of the ADC is near the steady-state operating point. As the ADC output moves further away from the equilibrium point, the slope increases to α 2  and then flattens out again to α 3 . 
         [0034]    Referring to  FIG. 3   a , we may use small signal analysis and assume a sinusoidal signal at the input to the ADC  110  to calculate an expression for the gain, G(a), through the gain scheduling block  302  as a function of the input signal amplitude, a. Using the gain scheduling curve depicted in  FIG. 5 , the gain can be expressed as follows for the three regions comprising a≦a 1 , a 1 ≦a≦a 2 , and a 2 ≦a. 
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         [0035]      FIG. 6  is a simplified gain scheduling scheme in accordance with another embodiment of the present invention. Input to the gain scheduling block is plotted along horizontal axis  602 , and output is plotted along vertical axis  604 . In this embodiment, gain curve  608  provides no sensitivity in the range extending from −a 1  to +a 1  and thus models the zero-error bin effect. Beyond input magnitudes of a 1 , the slope of the gain curve  608  increases to a 2 , as indicated at  606 , providing a normal transient response in the case of large transients. 
         [0036]      FIG. 7  is a plot of the gain produced by the gain scheduling scheme of  FIG. 6  as a function of input amplitude. The input amplitude, normalized to a 1 , the point at which the gain slope switches to a 2 , is plotted along horizontal axis  702 . The gain, normalized to a 2 , is plotted along vertical axis  704 . The gain curve  706  illustrates very low gain in the zero-error bin, rising rapidly to a 2  at amplitudes beyond a 1 . 
         [0037]      FIG. 8  is a second simplified gain scheduling scheme in accordance with another embodiment of the present invention. Input to the gain scheduling block is plotted along horizontal axis  802 , and output is plotted along vertical axis  804 . The gain scheduling curve  808  has a slope of α 1 , indicated at  806 , in the region between amplitude inputs of −a 2  and +a 2 , and then flattens to a slope of zero beyond a 2 . This scheme models the gain saturation effect inherent in most digital systems. 
         [0038]      FIG. 9  is a plot of the gain produced by the gain scheduling scheme of  FIG. 8 . Input amplitude, normalized to a 2 , is plotted along horizontal axis  902 , while gain, normalized to at is plotted along vertical axis  904 . Gain curve  906  shows a constant gain of α 1  out to amplitudes of a 2 , and then decays quickly beyond a 2 , exhibiting the saturation effect. 
         [0039]      FIG. 10  depicts a gain scheduling scheme in accordance with an embodiment of the present invention that exhibits a saturation effect while also introducing a reduced gain scheduling region near the steady-state operating point. In this embodiment, gain scheduling curve  1002  has a slope of 1, indicated at  1004 , in the region between −a 1  and +a 1 . The slope then increases to 2 between a 1  and a 2 , as indicated at  1006 , and then flattens off to zero beyond a 2 . This embodiment produces a slow response around the steady-state point to make the closed loop less sensitive to noise and to guarantee stability. At larger amplitudes, the higher gain provides large corrective action, making the transient response to large-magnitude variations significantly faster. 
         [0040]      FIG. 11  is a gain plot of the gain scheduling scheme depicted in  FIG. 10 . Input amplitude, normalized to a 1 , is plotted along horizontal axis  1102 , and gain is plotted along vertical axis  1104 . In this particular plot, the ratio of a 2  to a 1  is taken to be 16, but other ratios may be used, depending on the desired response characteristic. The gain curve  1106  shows a flat gain of one up to a 1 , then a rapidly rising gain that approaches two as the amplitude approaches a 2 . The gain then decays at amplitudes beyond a 2 , illustrating the effects of saturation. It can be seen that gain curve  1106  exhibits a relatively low gain response near the steady-state point at small error amplitudes but that it increases for larger error amplitudes, providing a faster transient response. 
         [0041]      FIG. 12  illustrates a digital PWM control circuit in accordance with an embodiment of the present invention that was constructed using a field-programmable gate array (FPGA) to control a buck converter. The power stage  1202  was designed as a switching converter having switch elements  1220  and  1221  and a filter element comprising inductor  1222  and capacitor  1224 . The switching converter was designed to deliver 2 volts output from a 12 volt input supply. In this embodiment, inductor  1222  has a value of L=1.4 μH and capacitor  1224  has a value of C=630 μF. The error signal, calculated at block  1208  from the difference of output voltage  1204  and reference voltage  1206 , was digitized in an ADC  1210  having 9 bits of resolution and a least-significant bit size of 0.5 mV. The gain scheduling scheme  1214  and compensator filter  1216  were implemented in an FPGA  1226  to control a digital PWM control circuit  1218  clocked at 200 MHz and having a switching frequency of 500 kHz. The digital compensator  1216  was implemented to have the following response function: 
         [0000]    
       
         
           
             
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         [0042]      FIG. 13   a  illustrates the transient response of this system when no gain scheduling scheme is employed.  FIG. 13   b  illustrates the transient response when the gain scheduling scheme is employed in the manner illustrated in  FIG. 10 . It can be seen that the size of the transient spike  1302  in the case with no gain scheduling is significantly larger than the transient spike  1304  when gain scheduling is employed. 
         [0043]    From the analysis of the gain scheduling schemes presented previously, it is clear that the gain through the scheduling block can be very small when there is a saturation effect or zero-error bin effect. In fact, the saturation effect almost always exists inherently in digitally controlled PWM systems. For example, the digital PWM controller itself is limited to duty cycles between 0% and 100%. This saturation effect introduces a small gain into the closed-loop system that must be taken into account during stability analysis. The following simulation was undertaken to demonstrate this analysis. 
         [0044]    A digitally controlled boost converter was simulated with parameters including L=5 μH, C=60 μF, Vin=5 V, and Vout=10 V, with a switching frequency of 500 kHz and a load resistance of 11.6Ω. The compensator filter was designed to have the following response function: 
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         [0045]    With this gain function, the system is stable. Modeling this system using Simulink reveals a gain margin of 8.46 dB and a phase margin of 20 degrees, indicating stability. However, if the gain term is decreased, the system becomes unstable due to the small gain introduced by the saturation of the DPWM. For example, a system was simulated having the following smaller gain: 
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         [0046]    The simulation of this system showed a gain margin of −16.8 dB and a phase margin of −16.8 degrees, indicating that it was not stable. Thus, it is important to address the stability problem when small gains are involved. 
         [0047]    In summary, the foregoing description of several embodiments of a digital PWM control system achieves a number of advantages over the prior art. For example, a non-linear response function can be achieved without the need for a window comparator. Several practical piecewise-linear implementations of the gain scheduling scheme are illustrated that are easily implemented in the digital domain and introduce nonlinearity into the DPWM system naturally. The gain scheduling method enables a slow response around the steady-state point, which makes the loop less sensitive to noise and guarantees stability. At the same time, it enables high gain at larger amplitudes such that a large corrective response is applied to large transients, making the transient response significantly faster. Other advantages and applications of the present invention will be clear to those skilled in the art and would also fall within the scope and spirit of the present invention. The invention is solely defined by the following claims.