Abstract:
Disclosed is a magnetic recording-playback apparatus suitable for recording and reproducing a signal including a broad-band composite video signal and a method therefor. The broad-band signal is time-sliced into signals in two channels, and each divided signal is expanded on the time axis so that it is converted into a lower-band signal before being recorded on a magnetic tape. In the time axis expansion process, the vertical blanking signal and/or horizontal blanking signal is not expanded, whereby the divided video signals have a still lower frequency band.

Description:
This application is a continuation of application Ser. No. 033,265, filed Apr. 2, 1987, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates to a magnetic recording-playback apparatus, and particularly to a video signal time axis altering circuit used in a magnetic recording-playback apparatus suitable for recording a broad-band video signal after dividing it into signals in multiple channels on a magnetic recording medium and a method therefor. 
     The development is under way for the so-called &#34;high quality television system&#34; which reproduces pictures in quality, particularly in fineness, incomparably higher than the conventional NTSC television system. The new system involves more image information and thus necessitates wider frequency band by several times than the conventional system. 
     A key subject to bring the high quality television system into practice is the achievement of a magnetic recording-playback apparatus, i.e., VTR, capable of recording a broad-band video signal and reproducing high quality pictures properly. A test-model VTR used for the high quality television system is described in the technical report of The Institute of Television Engineers of Japan, entitled &#34;VTR for high quality television&#34;, by Oketani, Tateno and Tsujikawa, Vo. 8, No. 33, published in Nov. 1984. The VTR, which is oriented mainly to television broadcasting studios, employs a head drum in large diameter so as to deal with broad-band frequencies and records a video signal in a divided form on four-channel tracks on the magnetic tape. 
     In order for the high quality television system to prevail as a household appliance, the VTR used for the system must be compact, inexpensive, and capable of long-time recording on a small cassette tape. To meet these requirements, the head drum must be small in size, the magnetic heads and signal channels must be small in number, and the associated circuits must be as simple as possible. However, a greater amount of image information to be recorded on the magnetic tape results in an increased recording density on the tape, which imposes technical difficulties in practicing the VTR oriented to the high quality television system. 
     SUMMARY OF THE INVENTION 
     An object of this invention is to provide a video signal time axis altering circuit for magnetic recording-playback apparatus and a method, in which a broad-band video signal is converted into narrow-band signals in multiple channels, the signals are recorded on the respective tracks of a magnetic tape, and the recorded signals are picked up on the tape and converted back to the original broad-band signal. 
     A primary signal carrying a composite video signal including a vertical blanking signal and horizontal blanking signal is segmented on a time-slice basis in a certain period into signals of N channels, with each signal being expanded on the time axis by N-fold, and consequently each signal has a band width narrowed to 1/N of that of the original signal. Each of the converted signals in multiple channels has a narrow band and therefore can be recorded less densely on a magnetic tape with a magnetic recorder without difficulty. 
     By the N-fold expansion process on the time axis for the divided signals, the vertical and horizontal blanking signals are also expanded. For the vertical and horizontal blanking signals having a summed period, i.e., redundant time, of τ in one field period of T V , the expanded blanking signals have a summed period, i.e., redundant time, of N×τ. The video signal is not included in this period of time N×τ, and therefore the redundant time is desirably as short as possible. Reduction of the redundant time enables further expansion of the video signal on the time axis included in each divided signal. In consequence, the signals recorded on the magnetic tape can have a band width rendered still narrower than 1/N of the original. 
     The present invention resides in a control circuit and method which much expands the video signal on the time axis without expanding the period of the vertical and/or horizontal blanking signal. The control circuit and method reduces the redundant time by temporarily halting the signal writing to the memory. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of the magnetic recording-playback apparatus in which the time axis altering circuit of this invention is used; 
     FIG. 2a is a waveform diagram showing the luminance signal in one vertical period produced by the inventive circuit; 
     FIG. 2b is a waveform diagram showing the luminance signal in two horizontal periods produced by the inventive circuit; 
     FIG. 3 is a waveform diagram showing the chrominance signal in two horizontal periods produced by the inventive circuit; 
     FIGS. 4a and 4b are diagrams showing in pattern the format of the 2-channel luminance signals Y 1  and Y 2  and the chrominance signal C o  recorded on the magnetic tape with the VTR incorporating the inventive circuit; 
     FIG. 5 is a diagram showing line-sequential chrominance signals retrieved from the memory; 
     FIG. 6 is a diagram showing the disposition of the magnetic heads in the VTR incorporating the inventive circuit; 
     FIG. 7 is a waveform diagram showing a signal in one vertical period recorded suitably with the magnetic heads shown in FIG. 6; 
     FIG. 8 is a waveform diagram showing time-slot multiplexing for the luminance and chrominance signals; and 
     FIG. 9 is a block diagram showing the circuit for removing the vertical and horizontal redundant portions from a video signal. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     An embodiment of this invention will now be described with reference to FIG. 1. Among a broad-band video signal, a luminance signal (Y) is divided into signals in two channels (N=2) to be recorded on the first and second tracks of a magnetic tape, while two chrominance signals (C 1  and C 2 ) are converted into line sequential signals to be recorded on the third track of the tape. Namely, this embodiment is oriented to a magnetic recording-playback apparatus of the type of 3-channel division rotary head. 
     The video signal to be recorded consists of three primary-color video signals, i.e., red (R), green (G) and blue (B), and they are received on terminals 1a, 1b and 1c, respectively. The primary-color video signals R, G, B are converted into a luminance signal Y 0  and two chrominance signals C 01  and C 02  through the matrix operation by an encoder 10. The luminance signal Y 0  produced by the encoder 10 is confined to a band BW by a low-pass filter 11 so that a luminance signal Y 0  is produced. The chrominance signals C 01  and C 02  from the encoder 10 are also made to have a confined band by respective low-pass filters 12 and 13. The filters 12 and 13 each comprise a low-band filter as a horizontal band-limiting circuit and further include a vertical band limiting circuit. The vertical band-limiting circuit includes a delay circuit and an adding circuit, and operates to limit the band of the chrominance signals C 01  and C 02  by summing chrominance signals for more than one different raster. The vertical band-limiting circuit is effective for eliminating the foldover distortion in the vertical direction created in converted line-sequential chrominance signals. As a result, two chrominance signals C 1  and C 2  confined to a band BW&#39; are produced at the outputs of the filters 12 and 13, respectively. 
     A block 100 shown by the dashed line stands for a time axis alternating circuit, which divides the luminance signal Y into 2-channel signals and implements time axis expansion so that the redundant portion included in the signal Y becomes minimum, and transforms the two chrominance signals C 1  and C 2  into a line-sequential signal of one channel and implements time axis expansion so that the redundant portion included in the signals becomes minimum. 
     The operation of the time axis altering circuit 100 will be described in connection with the waveform diagrams of FIGS. 2a and 2b. FIG. 2a shows by (a1) the luminance signal Y derived from the input video signal in one field period T V  provided by the filter 11. The hatched section represents the vertical blanking period τ V  included in the input video signal. Of the vertical blanking period τ V , a period τ 10  is the minimum necessity of operation and a remaining portion τ 1  (will be termed &#34;vertical redundant period&#34;) is not indispensable. FIG. 2b shows by (a2) the waveform of the input video signal in two horizontal scanning periods T H  ×2, which includes in each T H  a horizontal blanking period τ H  indicated by hatching. Of the horizontal blanking period τ H , a period τ 20  is the minimum necessity of operation and a remaining portion τ 2  (will be termed &#34;horizontal redundant period&#34;) is not indispensable. 
     The present invention is intended to narrow the band occupied by each channel by removing one or both of the vertical redundant period τ 1  and horizontal redundant period τ H  and by expanding the signal on the time axis for recording. The following describes the operation of the inventive video signal time-axis altering circuit by taking an example of the case where the luminance signal Y is divided into two channels and both of the redundant periods τ 1  and τ 2  are removed. 
     In the time-axis altering circuit 100 in FIG. 1, the luminance signal Y (shown by (a1) in FIG. 2a and (a2) in FIG. 2b) supplied from the filter 11 is sampled in response to a sampling clock signal CSY with frequency f 1  and converted into a digital signal by means of an A/D converting circuit 101. The sampling clock signal CSY (not shown) may be included in the input video signal, or may be produced from the sync signal in the input video signal. A memory 103 is a RAM chip module for example. The A/D converting circuit 101 has its output signal written alternately in area I and area II of the memory 103 in every horizontal scanning period T H  in response to the write clock signal CWY with frequency f 1  produced from the sampling clock signal CSY by an address control circuit 300. During the vertical redundant period τ 1  and horizontal redundant period τ 2 , the writing of the signal to the memory 103 is halted by a write-halt control circuit 350 connected to the address control circuit 300. More specifically, among the luminance signal Y shown by (2a) in FIG. 2b, luminance signal Y 2n-1  of the odd-numbered (2n-1) line is written in the area I of the memory 103, luminance signal Y 2n  of the subsequent even-numbered (2n) line is written in the area II of the memory 103, and writing to the memory 103 is halted by the write-halt control circuit 350 during the horizontal redundant period τ 2  of each line. Consequently, the memory 103 has its area I storing signal Y&#39; 2n-1  which is the signal Y 2n-  1 with the horizontal redundant period τ 2  being eliminated as shown by (b2) in FIG. 2b, while its area II storing signal Y&#39; 2n  which is the signal Y 2n  with the horizontal redundant period τ 2  being eliminated as shown by (c2) in FIG. 2b. Writing to the memory 103 is halted by the write-halt control circuit 350 also during the vertical redundant period τ 1  in FIG. 2a, and therefore the memory 103 has its areas I and II storing signals Y 1  and Y 2  each with the vertical redundant period τ 1  being eliminated as shown by (b1) and (c1) in FIG. 2a, respectively. Since the memory areas I and II are written alternately for every line, as mentioned above, the remaining period τ 10  of the signal after the vertical redundant period τ 1  has been removed is expanded virtually in an even proportion, as shown by hatching by (bl) and (cl) in FIG. 2a, and written in the areas I and II of the memory 103. 
     FIG. 9 shows an example of a means for eliminating the signal portions in the vertical redundant period τ 1  and horizontal period τ 2  when the signal is written in the memory 103. A reset pulse generating circuit 510 detects the horizontal blanking period τ H  shown by (a2) in FIG. 2b using the horizontal sync signal received on terminal 502, and produces a reset pulse having a pulse width equal to the horizontal redundant period τ 2  by counting the write clock signal CWY received on terminal 501. The preset pulse produced by the reset pulse generating circuit 510 is fed to the reset input terminal R of the address counter 520, and the write clock signal CWY on the terminal 501 is supplied to the clock input terminal CK of the address counter 520. The address counter 520 counts the write clock signal CWY received on its terminal CK and produces an address signal which is dependent on the count value. The address signal is supplied as the pixel write address to the memory 103 by way of the terminal 504 so that pixel data is written in the areas I and II of the memory 103 in response to the advancement of the address signal. 
     The address counter 520 is cleared by the reset pulse which is sent from the reset pulse generating circuit 510 and received on terminal R, and counting of the write lock signal CWY, i.e., write address advancement, is halted during the period equivalent to the horizontal redundant period τ 2 . Consequently, the memory 103 has its areas I and II written signals being rid of a signal portion in the horizontal redundant period τ 2  included in the horizontal blanking period τ H  on each line shown by (a2) in FIG. 2. 
     Another reset pulse generating circuit 530 detects the vertical blanking period τ V  shown by (a1) in FIG. 2a using the vertical sync signal received on terminal 503, and produces a reset pulse having a pulse width equal to the vertical redundant period τ 1  included in the vertical blanking period τ V  by counting the horizontal sync signal received on terminal 502. A line counter 540 counts the horizontal sync signal sent from the terminal 502 to its terminal CK, and produces a line address signal which is dependent on the count value. The line address signal is supplied together with the write address signal from the address counter 520 to the memory 103 by way of the terminal 504. Consequently, lines are written in the areas I and II of the memory 103 in response to the advancement of the line address signal. Of the line address signal, address signal A for the lowest-order count output of the line counter 540 is used to switch the writing to the memory areas I and II at every line. Specifically, during a period when the lowest-order line address signal A 0  is &#34;low&#34;, an odd-numbered 2n-1) line in the input video signal is written in the area I of the memory 103, while during a period when the line address signal A 0  is &#34;high&#34;, an even-numbered (2n) line is written in the area II of the memory 103. The line counter 540 is cleared by the reset pulse which is sent from the reset pulse generating circuit 530 to its terminal R, and counting of the horizontal sync signal, i.e., line address advancement, is halted during the period equivalent to the vertical redundant period τ 1 . Consequently, the memory 103 has its areas I and II written signals being rid of a signal portion in the vertical redundant period τ 1  included in the vertical blanking period τ V  in each field shown by (a1) in FIG. 2A. 
     The signals Y 1  and Y 2  written in the memory 103 are read out sequentially by a read clock signal CRY produced from the sampling clock signal CSY by the address control circuit 300. 
     The read clock signal has its frequency f 2  determined properly to meet the operating condition. In this embodiment, the frequency f 2  of the read clock signal CRY is determined such that the 1-field period T V  &#39; (shown in FIG. 2a) of the signals Y 1  and Y 2  read out of the memory 103 is equal to the 1-field period T V  of the primary signal Y, as follows. 
     
         T.sub.V &#39;=T.sub.V                                          (1) 
    
     Since the primary signal Y has its 1-field period T V  being rid of the signal portion in the vertical redundant period τ 1  and the signal Y is divided into signals Y 1  and Y 2  in two channels, the number L of lines of signals included in the 1-field period T V  &#39; of the signals Y 1  and Y 2  is given by the following equation. 
     
         L=(T.sub.V -τ.sub.1)/(2×T.sub.H)                 (2) 
    
     Choosing the horizontal scanning period of the signals Y 1  and Y 2  to be T H  &#39; (will be termed &#34;fundamental period&#34;) results. 
     
         T.sub.V &#39;=L×T.sub.H &#39;                                (3) 
    
     From the above equations (1), (2) and (3), the following equation results. 
     
         T.sub.H &#39;=2×T.sub.H /(1-τ.sub.j /T.sub.V)        (4) 
    
     The primary signal Y is rid of the horizontal redundant period τ 2  from one horizontal scanning period T H  and a signal portion in the remaining period (T H  -τ 2 ) is expanded to a time length T H  &#39; on the time axis for each line, as mentioned above, and therefore the time axis expansion ratio M is given as follows. 
     
         M=T.sub.H &#39;/(T.sub.H -τ.sub.2)                         (5) 
    
     The above equations (4) and (5) yield the following equation. 
     
         M=2/(1-τ.sub.1 /T.sub.V)×(1-τ.sub.2 /T.sub.H)(6) 
    
     Namely, by setting the frequency f 0  of the read clock signal CRY in relation to the frequency f 1  of the sampling clock signal CSY as, 
     
         f.sub.0 =f.sub.1 /M                                        (7) 
    
     the memory 103 provides two signals Y 1  and Y 2  derived from the primary signal Y with its vertical redundant period τ 1  and horizontal redundant period τ 2  being removed, with it entirety being divided into two channels, and with its time axis being expanded by M-fold, as shown by (b1) and (c1) in FIG. 2a and by (b2) and (c2) in FIG. 2b. 
     The signals Y 1  and Y 2  read out of the memory 103 appended with certain synchronizing information by means of synchronizing information inserting circuits 111 and 112, and the resulting output signals are converted to analog signals by D/A converting circuits 121 and 122, respectively. The two luminance signals Y 1  and Y 2  provided by the D/A converting circuits 121 and 122 are versions of the luminance signal Y with occupied band BW from the filter 11, with its time axis being expanded by M-fold, as will be appreciated from the foregoing, and therefore the signals Y 1  and Y 2  have their occupied band reduced to BW/M. The two luminance signals Y 1  and y2 with occupied band BW/M provided by the D/A converting circuits 121 and 122 in the time axis altering circuit 100 are subjected to pre-emphasizing and frequency modulation (FM) by respective video signal processing circuits 31 and 32, and supplied by way of a recording amplifier 40 to rotary magnetic heads 50. The luminance signal Y 1  is recorded as a signal of channel 1 in the first area on the magnetic tape 3, and the luminance signal Y 2  is recorded as a signal of channel 2 in the second area on the magnetic tape 3. 
     Although in the above description the primary signal Y is divided into signals in two channels, when in general the primary signal Y is divided into N channels (where N is an integer larger than 2), the time axis expansion ratio M is given by the following equation. 
     
         M=N/(1-τ.sub.1 /T.sub.V)×(1-τ.sub.2 /T.sub.H)(8) 
    
     Accordingly, the larger the values of redundant periods τ 1  and τ 2 , the larger time axis expansion ratio M and more reduction of occupied band (BW/M) of each channel signal result. In addition, the larger the number N of channel division, the greater band reduction effect (value of M-N) based on the redundant periods τ 1  and τ 2  results. In contrast, if the primary signal Y is simply divided into N channels without the elimination for the redundant periods τ 1  and τ 2 , i.e., a case of τ 1  =0 and τ 2  =0 in equation (8), the occupied band of each channel is BW/N. Generally, the following relation is met. 
     
         M&gt;N                                                        (9) 
    
     Accordingly, the occupied band BW/M achieved by the inventive circuit is narrower than the occupied band of the conventional system. 
     When the signals are frequency-modulated (FM) and recorded magnetically, the S/N ratio of reproduced signals at a constant head-to-tape speed is expressed in terms of the signal occupancy band B, FM modulation index α, recording wavelength λ, and recording track width T as follows. 
     
         S/N∝α√Tλ/B                      (10) 
    
     Since the modulation index α and recording wave length λ are virtually in inverse proportion to the signal occupancy band B, the above equation (10) can be approximated as follows. 
     
         S/N∝√T/B.sup.2                               (11) 
    
     As a specific example, when the redundancy (τ 1  /T V ) of the vertical redundant period τ 1  is 7% and the redundancy (τ 2  /T H ) of the horizontal redundant period τ 2  is 9%, the above equation (8) at N=2 yields, 
     
         M≈2.36                                             (12) 
    
     Accordingly, the inventive circuit achieves the occupied band (BW/M) which is reduced (i.e., band compression) as compared with the occupied band (BW/N)of the conventional system to, 
     
         N/M≈1/1.18                                         (13) 
    
     This band compression effect: by the inventive circuit is approximately 3 dB improvement in terms of the S/N ratio based on equation (11) as compared with the conventional circuit when the track width T on the magnetic tape is constant. As implied by equation (11), the S/N ratio is proportional to the square root of the track width T, and virtually the same S/N ratio as of the conventional circuit is accomplished by the inventive circuit even if the track width is halved to T/2. Namely, for the achievement of the same S/N ratio, the inventive circuit enables the track width to be halved and thus the tape recording density to be doubled, whereby the recording time length can also be double relative to the case of the conventional circuit. 
     The synchronizing information inserting circuits 111 and 112 insert certain vertical synchronizing information, e.g., a vertical sync signal VS with negative polarity shown by (d1) in FIG. 2A, in the remaining blanking period τ V  &#39; after removal of the vertical redundant period τ 1  of the signals Y 1  and Y 2 , as shown by hatching by (bl) and (cl) in FIG. 2A, read out of the memory 103 in its area I and area II, respectively. In case the input primary signal Y includes in its remaining blanking period after removal of the vertical redundant period τ 1 , i.e., the period τ V  -1 shown by hatching by (a1) in FIG. 2a, certain vertical synchronizing information, e.g., a vertical sync signal with negative polarity, the vertical synchronizing information is written in both of the memory areas I and II, and therefore the vertical synchronizing information is available in both of the memory output signals Y 1  and Y 2 . Accordingly, the above-mentioned means of generating and inserting the vertical synchronizing information by the circuits 111 and 112 is rendered unnecessary. 
     The synchronizing information inserting circuits 111 and 112 further insert certain horizontal synchronizing information, e.g., a horizontal sync signal HS with negative polarity and a cluster of burst signal BS cycling at a certain frequency shown by (d2) in FIG. 2b, in the remaining blanking period τ H  &#39; after removal of the horizontal redundant period τ 2  of the signals Y L  and Y 2 , as shown by hatching by (b2) and (c2) in FIG. 2b, read out of the memory 103. In case the input primary signal Y includes in its remaining blanking period after removal of the horizontal redundant period τ 2 , i.e., the period τ H  -τ 2  shown by hatching by (a2) in FIG. 2b, certain horizontal synchronizing information, e.g., a horizontal sync signal with negative polarity and a cluster of burst signal, they are available in both of the memory output signals Y 1  and Y 2 , and accordingly the means of generating and inserting the horizontal synchronizing information by the circuits 111 and 112 is rendered unnecessary. 
     Next, the function of the time axis altering circuit for the two chrominance signals C 1  and C 2  will be described with reference to the waveform diagram of FIG. 3. FIG. 3 shows by (a) and (b) the input primary chrominance signals C 1  and C 2  in one horizontal scanning period T H  provided by the filters 12 and 13, respectively. The period τ H  shown by hatching is the same horizontal blanking period as in the aforementioned luminance signal Y, and the period τ 2  is also the same horizontal redundant period. The input primary chrominance signals c 1  and C 2  actually include the same vertical blanking period τ V  and vertical redundant period τ 1  as in the luminance signal Y, although these are not shown in FIG. 3. The present invention is also intended to reduce the occupied band of the chrominance signals C 1  and C 2  by eliminating one or both of the vertical redundant period τ 1  and horizontal redundant period τ 2 . The chrominance signals C 1   and C 2  in two channels are transformed into a line-sequential 1-channel chrominance signal C 0  having an occupied band virtually equal to the occupied band (BW/M) of each of the 2-channel luminance signals Y 1  and y 2 . 
     In FIG. 1, the two chrominance signals C 1  and C 2  with occupied band BW&#39; provided by the filters 12 and 13, respectively, are fed to terminals a and b of a switching circuit 105 which operates in every horizontal scanning period T H  to select an input. Consequently, the circuit 105 selects a signal of C 1  group for an odd numbered (2 n-1 ) line to provide a signal C 1 ,2n-1, and subsequently selects a signal of C 2  group for an even numbered (2n) line to provide a signal C 2 ,2n, as shown by (c) in FIG. 3. 
     The chrominance signal C 3  converted in the line sequential form by the switching circuit 105 is sampled by the sampling clock signal CSC with frequency f 1  &#39; and converted into a digital signal by means of an A/D converting circuit 102. The sampling clock signal CSC may be included in the input primary video signal, or may be produced from other synchronizing information included in the input signal, as in the case of the sampling clock signal CSY. Alternatively, the sampling clock signal CSC may be generated in synchronism with the sampling clock signal CSY. 
     The output signal from the A/D converting circuit 102 is written sequentially into the memory 104 in each horizontal scanning period T H  in response to the write clock signal CWC with frequency f 1  &#39; produced from the sampling clock signal CSC by the address control circuit 300. Of the line-sequential chrominance signal C 3 , writing of the memory 104 for a signal C 1 ,2n-1 on an odd-numbered (2n-1) line is halted during the horizontal redundant period τ 2  in the horizontal blanking period τ H  and writing of the memory 104 for a signal C 2 ,2n on the subsequent even-numbered (2n) line is halted during the horizontal blanking period τ H  by the operation of the write-halt circuit 350 connected to the address control circuit 300. 
     As a result of the above writing control, the memory 104 stores a signal C&#39; 1 ,2n-1 which is the signal C 1 ,2n-1 with its horizontal redundant period τ 2  being removed and subsequently a signal C&#39; 2 ,2n which is the signal C 2 ,2n with its horizontal blanking period τ H  being removed, as shown by (d) in FIG. 3. Needless to say, the vertical redundant period τ 1  is also removed in the stored signal C 0 . The signal C 0  stored in the memory 104 ((d) in FIG. 3) is read out sequentially by the address control circuit 300 in response to the read clock signal CRC with frequency f 0  &#39; produced from the sampling clock signal CSC. The frequency of the read clock signal CRC is determined properly depending on the operating condition. In this embodiment, the frequency of the read clock signal CRC is determined such that the fundamental period T H  (shown by (d) in FIG. 3) of the signal c 0  in every two line read out of the memory 104 meets equation (4). 
     As will be appreciated from the foregoing, the signal with the remaining period (2T H  -τ 2  -τ H ) after removal of the horizontal redundant period τ 2  and horizontal blanking period τ H  from the 2-line period 2T H  of the input primary signal C 3  is extended on the time axis to the time length T H  &#39;, and therefore the time axis expansion ratio M&#39; is given by the following equation. 
     
         M&#39;=T.sub.H &#39;/(2T.sub.H -τ.sub.2 -τ.sub.H)          (14) 
    
     The above equations (4) and (14) yield the following equation. ##EQU1## Accordingly, in order to attain the time axis expansion (M&#39;&gt;1), the frequency f 0 , of the read clock signal CRC is determined in relation with the frequency f 1  &#39; of the sampling clock signal CSC as follows. 
     
         f.sub.0 &#39;=f.sub.1 &#39;/M&#39;                                     (16) 
    
     The signal C 0  read out of the memory 104 is appended by a synchronizing information inserting circuit 113 with certain synchronizing information as in the case of the luminance signals Y 1  and Y 2 , e.g., one or both of horizontal synchronizing information including a horizontal sync signal HS with negative polarity and burst signal BS, as shown by (e) in FIG. 3, and vertical synchronizing information including a vertical sync signal with negative polarity, and the resulting signal is converted into an analog signal by a D/A converting circuit 123. The chrominance signal C 0  ((e) in FIG. 3) provided by the D/A converting circuit 123 has its time axis expanded by M&#39;-fold from that of the primary chrominance signal C 3  confined to the band BW&#39; by the filters 12 and 13, and therefore the new occupied band is reduced to BW&#39;/M&#39;. In contrast, the conventional circuit which simply transforms 2-channel simultaneous chrominance signal into a 1-channel, line-sequential chrominance signal without removing the redundant periods τ 1  and τ 2  (equivalent to the case of M&#39;=1 in equation (16)) presents an occupied band of BW&#39; for the signal. Since M&#39; is larger than unity, the inventive circuit achieves a narrower occupied band as compared with the conventional circuit. 
     The chrominance signal C 0  with occupied band BW&#39;/M provided by the D/A converting circuit 123 in the time axis altering circuit 100 is subjected to preemphasizing and frequency-modulation (FM) by a video record signal processing circuit 33, and the resulting signal is fed through the recording amplifier 40 to the rotary magnetic heads 50 and recorded as a signal of channel 3 in the third area different from the areas where the luminance signals Y 1  and Y 2  are recorded on the magnetic tape 3. 
     By choosing the signal pass bands BW and BW&#39;  of the filters 11, 12 and 13 to meet the following relation, 
     
         BW/M≈MW&#39;/M&#39;                                        (17) 
    
     the signals Y 1 , Y 2  and C 0  to be recorded in the first, second and third areas can have a virtually equal occupied band. Therefore, the signal band is not excessive nor lacking among the channels, and the signals can be recorded and reproduced efficiently. 
     FIGS. 4a and 4b shows examples of the track pattern formed by recording on the magnetic tape 3 using the rotary-head magnetic recording-playback apparatus shown in FIG. 1. In the figures, the first area indicated by Y 1  is for recording the luminance signal Y 1 , the second area indicated by Y 2  is for recording the luminance signal Y 2 , and the area indicated by C 0  is for recording the chrominance signal C 0 . FIG. 4a is the case where the magnetic track is divided in the track traversing direction into three channels (Y 1 , Y 2  and C 0 ) for recording the respective signals, while FIG. 4b is the case where the magnetic track is divided in the track longitudinal direction into two channels (Y 1  and C 0 , or Y 2  and C 0 ) and further divided in the track traversing direction into two channels (Y 1  and Y 2 ) for recording the respective signals. 
     Next, the signal reproducing function of the inventive time axis altering circuit will be described. The signals which have been recorded dividedly in multiple channels, i.e., three channels for signals Y 1 , Y 2  and C 0 , on the magnetic tape 3 are picked up sequentially for each channel using multiple magnetic heads 60 arranged in correspondence to the recording magnetic heads 50. After being amplified by a playback amplifier 70, the luminance signals Y 1  and Y 2  and the chrominance signal C 0  picked up from the first, second and third areas of tracks, respectively, are subjected to demodulation from FM and then de-emphasizing by respective video playback signal processing circuits 81, 82 and 83, and the resulting signals Y 1 , Y 2  and C 0  are fed to respective A/D converting circuits 201, 202 and 203 in a time axis reverse-altering circuit 200. 
     The luminance signal Y 1  outputted from the circuit 81 is converted into a digital signal by the A/D converting circuit 201 in response to the sampling clock signal CSY 1  with frequency f 0  which is given by equation (7), and the resulting signal is written sequentially into area I of a memory 204 by an address control circuit 400 which provides the write clock signal with frequency f 0  produced from the sampling clock signal CSY 1 . The sampling clock signal CSY 1  is generated on the basis of the aforementioned synchronizing information superimposed on the luminance signal Y 1  in its blanking period at recording, i.e., specifically it is generated in synchronism with the burst signal BS. 
     Similarly, the luminance signal Y 2  outputted from the circuit 82 is converted into a digital signal by an A/D converting circuit 202 in response to the sampling clock signal CSY 2  with frequency f 0 , and the resulting signal is written sequentially by the address control circuit 400 in response to the write clock signal with frequency f 0  produced from the sampling clock CSY 2 . The sampling clock signal CSY 2  is generated on the basis of the synchronizing information included in the luminance signal Y 2 , which is specifically the burst signal BS. 
     The chrominance signal C 0  outputted from the circuit 83 is converted into a digital signal by an A/D converting circuit 203 in response to the sampling clock signal with frequency f 0  &#39; which is given by equation (16), and the resulting signal is written sequentially into a memory 205 by the address control circuit 400 in response to the write clock signal with frequency f 0  &#39; produced from the sampling clock signal CSC 0 . The sampling clock signal CSC 0  is generated on the basis of the synchronizing information included in the chrominance signal C 0 , i.e., specifically it is generated in synchronism with the burst signal BS. 
     As a result of the above writing operation to the memory 204, its area I stores a luminance signal Y&#39; 2n-1  for an odd-numbered (2n-1) line as shown by (b1) and (b2) in FIGS. 2a and 2b, and the area II stores a luminance signal Y&#39; 2n  for an even-numbered (2n) line as shown by (c1) and (c2) in FIGS. 2a and 2b. 
     The luminance signals Y&#39; 2n  and Y&#39; 2n  which have been written in the areas I and II of the memory 204 are read out alternately in a period of T H  for each line by the address control circuit 400 in response to the read clock signal CRY&#39; with frequency M×f 0 , and reading of the memory 104 for its areas I and II is halted by a read-halt control circuit 450 during a time period τ 2  equal to the horizontal redundant period in each horizontal scanning period T H  and a time period τ 1  equal to the vertical redundant period in each vertical scanning period T V . Subsequently, the luminance signals (Y&#39; 2n-1  and Y&#39; 2n ) read out of the memory areas I and II alternately are switched by a switching circuit 211 in every horizontal scanning period TH, and the selected output is converted into an analog signal by a D/A converting circuit 221. 
     As will be appreciated from the foregoing, the reproduced luminance signals Y 1  and Y 2  are compressed on their time axis by a factor of M-fold depending on the ratio M of the write clock frequency to the read clock frequency for the memory 204. Since the value of M is given by equation (5), the luminance signals (Y 1  and Y 2 ) with the horizontal scanning period T H  are compressed on the time axis to T H  -τ 2  for each line and reading of the memory 204 is halted for a duration of τ 2  cyclically in each period T H , and the luminance signal Y&#39; outputted by the D/A converting circuit 221 has the same waveform as shown previously by (a2) in FIG. 2, in which the horizontal redundant period τ 2  which has been removed at recording is restored. Similarly, reading of the memory 204 is halted by the read-halt control circuit 450 for a duration of τ 1  in each vertical scanning period T V , and consequently the luminance signal Y&#39; outputted by the D/A converting circuit 221 has the same waveform as shown by (a1) in FIG. 2A, in which the vertical redundant period τ 1  which has been removed at recording is restored. 
     Also for the chrominance signal c 0  written in the memory 205, the horizontal redundant period τ 2  and vertical redundant period τ 1  which have been removed at recording are restored, the line-sequential chrominance signal is converted into parallel signals, and they are outputted as two chrominance signals C&#39; 1  and C&#39; 2  from the D/A converting circuits 222 and 223, respectively. Specifically, the chrominance signal C 0  which has been written in the memory 205 by the write clock signal with frequency f&#39; 0  is read out sequentially in each horizontal scanning period T H  in response to the read clock signal CRC&#39; with frequency M&#39;×f&#39; 0 . Reading for the chrominance signal C&#39; 1 ,2n-1 for the odd-numbered (2n-1) line equivalent to C&#39; 1 ,2n-1 shown by ((d) in FIG. 3) is halted for the duration τ 2  periodically, and thereafter the signal is read out for the period T H  τ 2  by the address control circuit 400. Reading for the chrominance signal C&#39;.sub. 2,2n for the even-numbered (2n) line (equivalent to C&#39; 2 ,2n shown by (d) in FIG. 3) is halted periodically, and thereafter the signal is read out for the period T H  -ρ H . Similarly, reading of the memory 205 is halted by the read-halt control circuit 450 for a duration of τ 1  in each vertical scanning period T V . 
     Through the above successive read-halt operation, the line-sequential chrominance signal provided by the memory 205 has the same data structure as shown by (c) in FIG. 3. The reproduced chrominance signal C 0  is compressed on the time axis to an extent of M&#39;-fold. 
     For the chrominance signal C&#39; 1 ,2n-1 for the odd-numbered 2n-1) line, the horizontal redundant period τ 2  which has been removed at recording is restored (equivalent to C 1 ,2n-1 shown by (c) in FIG. 3). For the chrominance signal C&#39; 2 ,2n for the even-numbered (2n) line, the horizontal blanking period τ H  which has been removed at recording is restored (equivalent to C 2 ,2n shown by (c) in FIG. 3). Furthermore, the vertical redundant period τ 1  is also restored in the chrominance signal. Accordingly, a line-sequential chrominance signal C&#39; 0  having a normal vertical blanking period τ V  and normal horizontal blanking period τ H  on every line is retrieved from the memory 205. The line-sequential chrominance signal C&#39; 0  is transformed into two chrominance signals by a converting circuit 212. 
     The operation of the converting circuit 212 will be described with reference to the waveform diagram of FIG. 5. FIG. 5 shows by (a) the line-sequential chrominance signal C&#39; 0  retrieved from the memory 205. It should be noted that the horizontal blanking period τ H  and vertical blanking period τ V  are omitted in FIG. 5. 
     The chrominance signal C&#39; 0  from the memory 205 is divided into two signals C&#39; 1  and C&#39; 2 , as shown by (b) and (c) in FIG. 5, by the converting circuit 212. One signal C&#39; 1  ((b) of FIG. 5) is obtained by extracting chrominance signals C 11 , C 13 , C 15 , C 17  and so on of odd-numbered lines in such a duplicate manner for each line as C 11  --C 11 , C 13  --C 13 , C 15  --C 15  and so on from the line-sequential chrominance signal C&#39; 0  ((a) of FIG. 5). Similarly, another signal C&#39; 2  ((c) of FIG. 5) is obtained by extracting chrominance signals C 22 , C 24 , C 26 , C 28  and so on of even-numbered lines in such a duplicate manner for each line as C 22  --C 22 , C 24  --C 24 , C 26  --C 26  and so on from the line-sequential chrominance signal C&#39; 0  ((a) of FIG. 5). The divided chrominance signals C&#39; 1  and C&#39; 2  derived from the line-sequential chrominance signal C&#39; 0  are fed to respective D/A converting circuits 222 and 223, and converted into analog signals. 
     By the operation of the time axis reverse-altering circuit 200, the chrominance signals C&#39; 1  and C&#39; 2  are converted into signals having the normal time axis. The luminance signal Y&#39; and chrominance signals C&#39; 1  and C&#39; 2  from the respective D/A converting circuits 221, 222 and 223 are filtered by respective low-pass filters 21, 22 and 23 so that unwanted signal components are eliminated. Thereafter, the three signals are subjected to matrix demodulation by a decoder circuit 20, and primary color signals of red (R), green (G) and blue (B) corresponding to the original three primary color signals are obtained at the output terminals 2a, 2b and 2c of the decoder circuit 20. 
     FIG. 6 shows an example of the head drum which mounts recording magnetic heads 50 and playback magnetic heads 60 shown in FIG. 1. In the figure, magnetic heads 1a and 1b are mounted on a concentric circle on the head drum 4 with a 180° spacing between the heads. Magnetic head pairs 2a-2b and 3a-3b are each mounted in the same fashion with a 180° spacing from each other on the same concentric circle when seen on the plan view of FIG. 6. The magnetic heads 1a, 2a and 3a are located closely with a vertical offset being made between them, while the magnetic heads 2a, 2b and 2c are located closely with a vertical offset being made between them. A magnetic tape 3 is wound on the head drum 4 to cover an angular range slightly in excess of 180° so as to confront at least half of the magnetic heads 1a, 2a, 3a, 1b, 2b and 3b at any time. 
     The head drum 4 arranged as described above rotates to create a recording track pattern on the magnetic tape 3 as shown in FIG. 4a. The magnetic heads 1a and 1b work alternately to record the signal of channel 1 (i.e., luminance signal Y 1 ) on a track Y 1 , the magnetic heads 2a and 2b work alternately to record the signal of channel 2 (i.e., luminance signal Y 2 ) on a track Y 2 , and the magnetic heads 3a and 3b work alternately to record the signal of channel 3 (i.e., chrominance signal C 0 ) on a track C 0 . 
     FIG. 7 shows the timing relationship of the time axis altering process implemented by the time axis altering circuit 100 in recording mode in which the head drum 4 shown in FIG. 6 is brought to a high-speed rotation. In the operation shown in FIG. 7, the rotational period of the head drum 4 is set equal to the field period T V  of the primary video signal to be recorded (shown by (a) in FIG. 7). Shown by (e) is a head switching signal SW produced in synchronism with the rotation of the head drum 4, and accordingly it has a period equal to T V . During the period with a &#34;high&#34; head switching signal SW, the magnetic heads 1a, 2a and 3a are in contact with the magnetic tape 3, while during the period with a &#34;low&#34; SW, the magnetic heads 1b, 2b and 3b are in contact with the tape 3 for signal recording or reproduction. The group of magnetic heads 1a, 2a and 3a and the group of magnetic heads 1b, 2b and 3b are switched at the rising and falling edges of the head switching signal SW. 
     The inventive circuit arrangement is capable of completely eliminating for all channels the time axis errors, such as &#34;skew&#34; at a signal linkage portion, occurring at the switching of heads due to extension or contraction of the magnetic tape. The following describes the basis of this ability according to the present invention. 
     As described above, the inventive circuit operates to record a video signal on the magnetic tape after removing the redundant periods (τ 1 , τ 2 ) included in one or both of the vertical blanking period (τ V ) and horizontal blanking period (τ H ) so that only minimum necessary blanking periods (τ V  -τ 1 , τ H  -τ 2 ) are left. Moreover, the inventive circuit allows part or all of the redundant periods to be used for the time axis altering process or other purposes such as recording a signal other than the video signal. 
     FIG. 7 shows the signals of the case where part of the redundant periods is used for another purpose. Specifically, in order to modify the signal time axis following the head switching in recording mode, part of the redundant periods is allotted to the head switching section. Shown by (a) in FIG. 7 is the waveform of one field period T V  of the primary video signal to be recorded, and the redundant period τ included in the field is indicated by cross-hatching. 
     Generally, the redundant period τ is given in terms of the vertical redundant period τ 1  and horizontal redundant period τ 2  by the following expression. ##EQU2## where l is the number of lines in a field of the primary video signal. Using the period τ, the former equation (8) is reduced to as follows. 
     
         M=N/(1-τ/T.sub.V)                                      (19) 
    
     FIG. 7 shows by (b), (c) and (d) the luminance signals Y 1  and Y 2  and chrominance signal C 0  provided at the outputs of the D/A converting circuits 121, 122 and 123 following the time axis process by the time axis altering circuit 100. In the circuit 100, the head switching signal SW is supplied to a circuit (not shown) for controlling the reading of the memories 103 and 104, so that reading of the memories 103 and 104 commences at a timing in synchronism with the rising and falling edges of the SW signal. The reading operation for the memories 103 and 104 takes place following the above commencement for a certain duration on the basis of line count for example. Through the above memory read control, the video signal is recorded by being accompanied by part (periods τ a  and τ b ) of the redundant period τ at the front and end of the head switching portion (i.e., inphase with the rising and falling edges of the head switching signal SW), as shown by cross-hatching by (b), (c) and (d) in FIG. 7. 
     With the intention of eliminating the residual redundant periods but the partial ones τ a  and τ b , the time axis expansion ratio M is set in the circuit 100 (the section for the luminance signal) to meet the following equation. ##EQU3## where N is set to 2 in this embodiment as mentioned previously. In consequence, the residual redundant periods but τ a  and τ b  are removed, and the redundant periods τ a  and τ b  are formed at positions shown by hatching in FIG. 4a. 
     In reproducing the luminance signals Y 1  and Y 2  and chrominance signal C 0  which have been recorded through the foregoing process, the magnetic heads are switched invariably within the redundant periods τ a  and τ b  formed as described above, and therefore dropout of reproduced signal does not occur, nor occurs a signal dropout due to extension or contraction of the magnetic tape, provided that the value of τ a  and τ b  is set greater than the possible time axis error (skew) caused by extension or contraction of the magnetic tape. In addition, as will be appreciated from the description in connection with FIG. 1, the time axis reverse-altering circuit 200 also serves to eliminate time axis errors included in the reproduced signals Y 1 , Y 2  and C 0  owing to the time buffering effect of the memories 204 and 205, and therefore the above-mentioned skew can also be eliminated completely. Moreover, since the redundant periods τ a  and τ b  are formed without fluctuation at invariable positions on the magnetic tape 3 in synchronism with the head drum rotation, the head switching can take place invariably within the period τ a  or τ b , which significantly improves the interchangeability of the recording-playback apparatus. This property facilitates the recording of a video signal in multiple segments for each field, and from another viewpoint this facilitates recording using a smaller head drum rotating at a higher speed and consequently fosters reduction in the size and weight of the magnetic tape recording-playback apparatus. 
     FIG. 8 shows by (a), (b) and (c) a luminance signal Y (equivalent to the Y in FIG. 2) and two chrominance signals C 1  and C 2  (equivalent to the C 1  and C 2  in FIG. 3) in a primary video signal. Shown by (d) and (e) are 2-channel signals S 1  and S 2  resulting from the time axis process and time-slot multiplexing within the fundamental period T H  &#39; for the signals shown by (a), (b) and (c). The signal S 1  of one channel includes a signal Y 2n-1  on an odd-numbered line in the luminance signal Y and a signal C 1 ,2n-1 on the odd-numbered line in the chrominance signal C 1  in a time-slot multiplexed formation for each line, while the signal S 2  of another channel includes a signal Y 2n  on an even-numbered line in the luminance signal Y and a signal C 2 ,2n on the even numbered line in the chrominance signal C 2  in a timeslot multiplexed formation for each line. The two signals S 1  and S.sub. 2 have their fundamental period T H  &#39; given by the previous equation (4), and for a general case of N-channel division it is given by the following equation. ##EQU4## On this account, the fundamental period T H  &#39; takes a value larger than N times the horizontal scanning period T H  of the primary video signal, i.e., T H  &#39;&gt;N×T H ), and therefore the longer signal fundamental period can more reduce the signal occupancy band as compared with the conventional case where the signal is simply divided into N channels (equivalently the case of τ 1  =0 in equation (21)). 
     Although illustrated in FIG. 8 is the time-slot multiplexing for a line of luminance signal and a line of chrominance signal within the fundamental period T H , an arbitrary number of lines of signals may be multiplexed within the T H  &#39;. Increasing the number of lines of signals included in the fundamental period T H  &#39; can reduce the total horizontal blanking period (τ H ) of these lines. In the example shown by (d) in FIG. 3, the entire horizontal blanking period τ H  for the signal C&#39; 2 ,2n can be eliminated, or in the example shown by (d) and (e) in FIG. 8, the entire horizontal blanking periods τ H  for the signals Y&#39; 2n-1  and Y&#39; 2n  can be eliminated, resulting in a further reduction of the signal occupancy band. 
     As described above, the inventive circuit operates to record a broad-band video signal on the magnetic tape by minimizing the redundancy of the signal and dividing the signal into multiple channels with a minimal occupied band. The consequent reduced signal recording density on each channel enables the use of a smaller head drum, whereby the high-quality television signal having a broad frequency band can be recorded and reproduced relatively easily.