Abstract:
A set of class AB output stages are cascaded to provide a class AB device circuit which utilizes relatively small transistors, low power, and virtually eliminates crossover distortion. The input may be powered by a voltage or a current source.

Description:
TECHNICAL FIELD  
         [0001]    This invention relates to high voltage and power output circuits, and more particularly, to an improved cascaded configuration for a class AB MOS output stage.  
         BACKGROUND AND SUMMARY OF THE INVENTION  
         [0002]    High voltage and high power output circuits may be manufactured from bipolar output stages or MOS structures. A typical class AB output stage utilizing MOS structures is shown in FIG. 1.  
           [0003]    Usually, there are several important parameters relevant to the design of a output stage. Crossover distortion should be minimized in order to provide an accurate noise-free output signal. Additionally, it is desirable to reduce static power consumption of the output stage.  
           [0004]    Over the years, numerous variations of cascaded class AB configurations have been developed. With respect to the large number of available such configurations, each has its own advantages and/or disadvantages. Several such prior art examples are discussed below.  
           [0005]    [0005]FIG. 1 depicts a cascaded class AB buffer utilizing bipolar transistors and several diodes as shown. Notably, there are four static current paths  201 - 204 , leading to increased power consumption. As stated above, minimization of power consumption is a goal in class AB output stages. Thus, the arrangement of FIG. 1 is suboptimal.  
           [0006]    [0006]FIG. 2 shows a class C Darlington output stage with biasing resistors utilizing FET technology. The arrangement of FIG. 2 would appear to consume less power than that of FIG. 1, owing to the fact that there are less current paths. It is noted however, that in the arrangement of FIG. 2, transistors M 3  and M 4  see the load through biasing resistors R 1  and R 2 . For purely capacitive loads, transistors M 3  and M 4  must be sized properly to prevent slowing down of the circuit. Often, this means utilizing larger transistors, with higher power consumption, than desirable. Thus, the larger transistors can make up for the reduction in current paths, and a relatively high power consuming device still results.  
           [0007]    In addition to the foregoing power consumption problem, another problem in output stages is that of crossover distortion. A prior art known technique of minimizing crossover distortion is to utilize a feedback loop to cancel such distortion. However, the implementation of such a feedback loop also results in added power consumption.  
           [0008]    In view of the above, there exists a need in the art for an improved circuit for minimizing required current and thus power consumption of the Class AB output stage while at the same time eliminating crossover distortion.  
           [0009]    The above and other problems with the prior art are overcome in accordance with the present invention. The present invention includes a circuit having cascaded output stages utilizing three sets of FET devices. Of the three sets of FET devices, in a preferred embodiment, a first set includes four FETs, a second set includes a different four FETs, and a third set includes two FETs. Two of the transistors from the second set and the two transistors from the third set comprise one class AB stage, and the remaining two transistors from the second set and all four transistors from the first set comprise the second class AB stage. The two stages are cascaded in a manner that reduces the required size for the transistors as well as eliminating crossover distortion. The arrangement avoids such crossover distortion without the need for a feedback loop, thereby eliminating the additional components that would otherwise be required and also minimizing power dissipation.  
           [0010]    The circuit has the further advantage of minimizing current paths, and thus power consumption, while permitting smaller size transistors to be used, even to drive relatively highly capacitive output loads.  
           [0011]    Further advantages of the present invention will become clear from the following detailed description and drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]    [0012]FIG. 1 shows a exemplary prior art arrangement;  
         [0013]    [0013]FIG. 2 depicts an additional prior art arrangement having the drawback of relatively high power consumption; and  
         [0014]    [0014]FIG. 3 shows an exemplary embodiment of the present invention utilizing ten FET devices.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0015]    [0015]FIG. 3 shows an exemplary embodiment of the present invention utilizing ten FET devices. It is understood that the particular transistors utilized are not critical to the present invention, and that other types of active devices may be utilized.  
         [0016]    The exemplary embodiment of FIG. 3 comprises four FET devices  601 - 604  connected to the input power source. The source of FET  601  is connected as shown to the gate of FET  605 , and the drain of FET  604  is connected to the gate of FET  608  as also shown. FETs  608 ,  605  and  601 - 604  constitute the equivalent af a single stage of a class AB output circuit. The remaining FETs  606 ,  607 ,  609  and  610  constitute a second output stage. The two output stages are connected at a junction between FET  605  and  606 , and are also connected at the junction between FETs  607  and  608 .  
         [0017]    By driving the gates of FETs  606 , 607 ,  609  and  610  from a common source as shown, the aforementioned four transistors act as a single output stage. Moreover, since FETs  605  and  608  have their respective gates tied to the gates of FETs  601  and  604  respectively, FETs  605  and  608  are part of the first stage.  
         [0018]    Note also that in the first stage, the gates of FETs  605 ,  601  and  602  are connected but the gates of the remaining FETs are connected in common to a second point. In the second stage however, the gates of all of the transistors of the stage are tied to a single common point. In summary, of the ten transistors shown, six constitute a first class AB output stage, and the remaining four constitute a second outputs stage connected in a cascaded fashion.  
         [0019]    In operation, the power is provided to the system from source  600  through series FET devices  601 - 604 . The signal to be amplified amplified is provided at point  615  as shown. The signal is then amplified through the consecutive AB stages and an output is seen at point  616 .  
         [0020]    Notably, unlike the prior art arrangement of FIG. 3C, FETs  605  and  608  do not see the output through biasing resistors, since the connection  305  in FIG. 3 is not present in FIG. 4. Accordingly, the arrangement of FIG. 4 permits smaller transistors utilized in the prior art arrangements or circuits with the same response times. The use of such smaller transistors provides for reduced input capacitance and thus, lower delay.  
         [0021]    Additionally, the circuit does not generate significant crossover distortion, thereby eliminating the need for a feedback loop in most applications. This mode of operation thus reduces power consumption. It is also noted that the system has at most three current paths, unlike some prior art arrangements that include at least four such paths.  
         [0022]    It is understood that the above describes only the preferred embodiments and is for exemplary purposes only. Other types of active devices may be utilized, and the invention is not limited to the embodiments disclosed herein. The device may be powered by a voltage source or a current source.