Abstract:
A port indicating circuit for a hard disk backplane of a server system includes a port circuit and an indicating circuit. The port circuit includes a control microchip and at least one selecting microchip. The hard disk backplane includes a number of ports. The server system includes a number of servers connected to some of the ports. The selecting microchip is connected to the control microchip and the remaining ports. If the control microchip detects that one or more standby servers form part of the server system, the control microchip selects the one or more standby server to connect to the remaining ports. If the control microchip does not detect that the one or more standby servers form part of the server system, the control microchip selects the servers to connect to the remaining ports. The indicating circuit indicates operating status of hard disks on the hard disk backplane.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is related to a commonly-assigned application having application Ser. No. 13/523877, entitled “PORT CIRCUIT FOR HARD DISK BACKPLANE AND SERVER SYSTEM”, and filed on Jun.  14 ,  2012 . Disclosure of the above-identified application is incorporated herein by reference. 
     
    
     FIELD 
       [0002]    The present disclosure relates to hardware circuits for computers, and particularly to a port indicating circuit for a hard disk backplane and a server system using the port circuit. 
       BACKGROUND 
       [0003]    A 2U server system is a server system with at least 2 servers. A 4-in-1 2U server system includes four servers sharing a hard disk backplane. Commonly, each server can provide six groups of serial advanced technology attachment (SATA) signals to the hard disk backplane to support hard disks installed on the hard disk backplane. Each hard disk backplane usually includes twelve ports configured for inserting twelve hard disks. Therefore, to control the twelve hard disks, each server outputs three groups of SATA signals to control three hard disks of the total twelve hard disks. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]    Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. 
           [0005]      FIG. 1  is a circuit diagram of an embodiment of a port circuit of a port indicating circuit for a hard disk backplane of a server system of the present disclosure. 
           [0006]      FIG. 2  is a circuit diagram of an indicating circuit of the port indicating circuit of the embodiment in  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0007]    The disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean “at least one.” The reference “a plurality of” means “at least two.” 
         [0008]      FIG. 1  and  FIG. 2  show an embodiment of a port indicating circuit  1  for a hard disk backplane of a server system. The port indicating circuit  1  can comprise a port circuit  100  shown in  FIG. 1  and an indicating circuit  300  shown in  FIG. 2 . 
         [0009]    The server system can be a 2U server system, in this embodiment, the port circuit  100  is applied to the 2U server system as an example. The 2U server system can include two servers S 1 , S 2  and two standby servers S 3 , S 4 . The two servers S 1 , S 2  form part of the 2U server system and the two standby servers S 3 , S 4  can selectively form part of the 2U server system. The term “form part” means that the servers are electronically connected in the appropriate connection for a 2U server configuration. 
         [0010]    The port circuit  100  can be installed on the hard disk backplane  200 . The hard disk backplane  200  can include twelve ports Port 1 -Port 12  configured for inserting hard disks. The port circuit  100  can include a control microchip  10  and two selecting microchips  30 ,  50 . 
         [0011]    The server S 1  can include a group of SATA signal output terminals S 1 - 1 , S 1 - 2 , S 1 - 3 , S 1 - 4 , S 1 - 5 , and S 1 - 6 . The SATA signal output terminals S 1 - 1 , S 1 - 2 , and S 1 - 3  are respectively connected to the ports Port 1 -Port 3  of the hard disk backplane  200  and respectively output SATA signals S 11 , S 12  and S 13  to the ports Port 1 -Port 3 . The SATA signal output terminals S 1 - 4 , S 1 - 5 , and S 1 - 6  are electrically connected to the selecting microchip  30  and respectively output SATA signal S 14 , S 15 , and S 16  to the selecting microchip  30 . 
         [0012]    The structure of the server S 2  is substantially similar to the server S 1  and includes a group of SATA signal output terminals S 2 - 1 , S 2 - 2 , S 2 - 3 , S 2 - 4 , S 2 - 5  and S 2 - 6 . The SATA signal output terminals S 2 - 1 , S 2 - 2 , and S 2 - 3  are respectively connected to the ports Port 4 -Port 6  of the hard disk backplane  200  and respectively output SATA signals S 21 , S 22  and S 23  to the ports Port 4 -Port 6  of the hard disk backplane  200 . The SATA signal output terminals S 2 - 4 , S 2 - 5  and S 2 - 6  are electrically connected to the selecting microchip  50  and respectively output SATA signal S 24 , S 25 , and S 26  to the selecting microchip  50 . 
         [0013]    The standby server S 3  includes a group of SATA signal output terminals S 3 - 1 , S 3 - 2 , S 3 - 3  and a triggering terminal PRE 3 . When the standby server S 3  forms part of the 2U server system, the SATA signal output terminals S 3 - 1 , S 3 - 2 , and S 3 - 3  are electrically connected to the selecting microchip  30  and respectively output SATA signals S 31 , S 32  and S 33  to the selecting microchip  30 , and the triggering terminal PRE 3  is electrically connected to the control microchip  10  through a hard disk bridging plate (not shown). In addition, a triggering signal is sent which denotes the standby server S 3  having already formed part of the 2U server system to the control microchip  10 . 
         [0014]    The structure of the standby server S 4  is substantially similar to the standby server S 3  and includes a group of SATA signal output terminals S 4 - 1 , S 4 - 2 , S 4 - 3  and a triggering terminal PRE 4 . When the standby server S 4  forms part of the 2U server system, The SATA signal output terminals S 4 - 1 , S 4 - 2 , and S 4 - 3  are electrically connected to the selecting microchip  50  and respectively output SATA signals S 51 , S 52 , and S 53  to the selecting microchip  50 , and the triggering terminal PRE 4  is electrically connected to the control microchip  10  through a hard disk bridging plate (not shown) and sends the triggering signal which denotes the standby server S 4  having already formed part of the 2U sever system to the control microchip  10 . 
         [0015]    The control microchip  10  includes two detecting terminals IN 1 , IN 2  and two output terminals O 1 , O 2 . The two detecting terminals IN 1 , IN 2  are respectively connected to the triggering terminal PRE 3 , PRE 4  to receive the triggering signals. The two output terminals O 1 , O 2  are respectively connected to the selecting microchips  30 ,  50 . 
         [0016]    When the detecting terminal IN 1  receives the triggering signal from the standby server S 3 , which means the standby server S 3  has already formed part of the 2U server system, the output terminal O 1  outputs a first control signal, which may be a high level signal (logic 1) to the selecting microchip  30 . Otherwise, the detecting terminal IN 1  does not receive the triggering signal. That is the standby server S 3  is not installed to the 2U server system, the output terminal O 1  outputs a second control signal, which may be a low level signal (logic 0) to the selecting microchip  30 . 
         [0017]    Similarly, when the detecting terminal IN 2  receives the triggering signal from the standby server S 4 , which means the standby server S 4  has already formed part of the 2U server system, the output terminal O 2  outputs the first control signal, which may be a logic 1 signal to the selecting microchip  30 . Otherwise, the detecting terminal IN 2  does not receive the triggering signal, which means the standby server S 4  does not form part of the 2U server system, the output terminal O 2  outputs a second control signal, which may be a logic 0 signal to the selecting microchip  30 . 
         [0018]    The selecting microchip  30  includes three data receiving terminals TX 0 , TX 1 , and TX 2 , three data input terminals D 0 , D 1 , and D 2 , three data output terminals BP 0 , BP 1 , and BP 2 , and a selecting terminal SEL. 
         [0019]    The data receiving terminal TX 0 , TX 1 , and TX 2  are respectively connected to the SATA signal output terminals S 1 - 4 , S 1 - 5 , and S 1 - 6  and receive the SATA signals S 14 , S 15 , and S 16 . The three data input terminals D 0 , D 1 , and D 2  are connected to the SATA signal output terminals S 3 - 1 , S 3 - 2 , and S 3 - 3  and receive the SATA signals S 31 , S 32 , and S 33 . The data output terminals BP 0 , BP 1 , and BP 2  are respectively connected to the ports Port 7 -Port 9 . The selecting terminal SEL is electrically connected to the output terminal O 1 . 
         [0020]    When the selecting terminal SEL receives the first control signal, the data input terminals D 0 , D 1 , and D 2  are selected and switched to be connected to the data output terminals BP 0 , BP 1 , and BP 2 . The SATA signals S 31 , S 32 , and S 33  from the standby severs S 3  can be transmitted to the ports Port 7 -Port 9 . When the selecting terminal SEL receives the second control signal, the data receiving terminals TX 0 , TX 1 , TX 3  are selected and switched to connect to the data output terminals BP 0 , BP 1 , and BP 3 , and the SATA signals S 14 , S 15 , and S 16  from the severs S 1  are transmitted to the ports Port 7 -Port 9 . 
         [0021]    The structure of the selecting microchip  50  is substantially similar to the selecting microchip  30  and includes three data receiving terminals TX 0 , TX 1 , and TX 3 , three data input terminals D 0 , D 1 , and D 2 , three data output terminals BP 0 , BP 1  and BP 2  and a selecting terminal SEL. The differences are the data receiving terminals TX 0 , TX 1 , and TX 3  of the selecting microchip  50  are connected to the SATA signal output terminals S 2 - 4 , S 2 - 5 , and S 2 - 6 . The three data input terminals D 0 , D 1 , and D 2  are connected to the SATA signal output terminals S 4 - 1 , S 4 - 2 , and S 4 - 3 . The data output terminals BP 0 , BP 1 , and BP 2  are respectively connected to the ports Port 10 -Port 12 , and the selecting terminal SEL is electrically connected to the output terminal O 1 . 
         [0022]    The indicating circuit  300  can comprise an indicating chip  40 , twelve light-emitting diodes (LEDs) D 1 -D 12 , and twelve resistors R 1 -R 12 . The indicating chip  40  is connected to the servers S 1 , S 2  and the standby severs S 3 , S 4 . Input pins I 1 , I 2 , I 3 , and I 4  of the indicating chip  40  are connected to output pins  11 ,  12 ,  13 , and  14  of the server S 1  respectively. Input pins I 5 , I 6 , I 7 , and I 8  of the indicating chip  40  are connected to output pins  21 ,  22 ,  23 , and  24  of the server S 2  respectively. Input pins I 9 , I 10 , I 11 , and I 12  of the indicating chip  40  are connected to output pins  31 ,  32 ,  33 , and  34  of the standby server S 3  respectively. Input pins I 13 , I 14 , I 15 , and I 16  of the indicating chip  40  are connected to output pins  41 ,  42 ,  43 , and  44  of the standby server S 4  respectively. Output pins L 1 -L 12  of the indicating chip  40  are connected to cathodes of the LED D 1 -D 12  respectively. Anodes of the LED D 1 -D 12  are coupled to a power terminal P 5 V through resistors R 1 -R 12  respectively. 
         [0023]    In use, the two servers S 1 , S 2  form part of the 2U server system. The ports Port 1 -Port 3  receive the SATA signals S 11 , S 12 , S 13  from the server S 1 , and the ports Port 4 -Port 6  receive the SATA signals S 21 , S 22 , S 23  from the server S 2 . The server S 1  outputs a logic 0 signal, to the input pin I 1  of the indicating chip  40 . The server S 2  outputs a logic 0 signal to the input pin I 5  of the indicating chip  40 . The indicating chip  40  determines that the server S 1  and the server S 2  form part of the 2U server system. The indicating chip  40  receives signals of operating information of the inserting hard disks of the servers S 1  and S 2  from the output pins  12 ,  13 , and  14  of the server S 1  and the output pins  22 ,  23 , and  24  of the server S 2 . 
         [0024]    When the standby server S 3  forms part of the 2U server system, the triggering terminal PRE 3  outputs the triggering signal to the detecting terminal IN 1  and the output terminal O 1  outputs the first control signal to the selecting terminal SEL. The data input terminals D 0 , D 1 , and D 2  are switched to connect to the data output terminals BP 0 , BP 1 , and BP 2  and the SATA signals S 31 , S 32 , and S 33  from the standby severs S 3  can be transmitted to the ports Port 7 -Port 9 . The standby server S 3  outputs a logic 0 signal to an input pin  19  of the indicating chip  40 . The indicating chip  40  receives signals of operating information of the inserting hard disks of the standby server S 3  from the output pins  32 ,  33 , and  34  of the standby server S 3 . 
         [0025]    When the selecting terminal SEL receives the second control signal, the data receiving terminals TX 0 , TX 1 , TX 3  are switched to connect to the data output terminals BP 0 , BP 1 , and BP 3 , and the SATA signals S 14 , S 15 , and S 16  from the severs S 1  are transmitted to the ports Port 7 -Port 9 . Therefore, whether the standby server S 3  forms part of the 2U server system or not, the ports Port 7 - Port 9  can be used. 
         [0026]    The operation principle of the selecting microchip  50  is substantially similar to the selecting microchip  30 , thus detail description of the selecting microchip  50  is omitted. Similarly, no matter if the standby server S 4  forms part of the 2U server system or not, the ports Port 10 -Port 12  can be used. 
         [0027]    The LEDs D 1 -D 12  are used to indicate operating status of the inserting hard disks connected to the port 1 -port 12  respectively. When the indicating chip determines an inserting hard disk is operating abnormally, the indicating outputs a logic 0 signal through a pin corresponding to the inserting hard disk. An LED is lit correspondingly to indicate the inserting hard disk is operating abnormally. 
         [0028]    While the disclosure has been described by way of example and in terms of an embodiment, it is to be understood that the disclosure is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the range of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.