Abstract:
A voltage regulation process, as well as a voltage regulation system, are discussed. A first voltage present at an input of the voltage regulation system is converted into a second, essentially constant voltage, which can be tapped at an output of the voltage regulation system. The voltage regulation system is provided with an additional device for assessing the efficiency of components connected to the second voltage. If it is determined that the efficiency of the components connected to the second voltage falls below a critical limit indicating the assessed efficiency, the second voltage can be increased.

Description:
CLAIM FOR PRIORITY 
   This application claims priority to German Application No. 10 2004 004 775.8, filed Jan. 30, 2004, which is incorporated herein, in its entirety, by reference. 
   TECHNICAL FILED OF THE INVENTION 
   The invention relates to a voltage regulation system and a voltage regulation process. 
   BACKGROUND OF THE INVENTION 
   In semi-conductor components, more particularly memory components such as DRAMs (DRAM=Dynamic Ransom Access Memory and/or dynamic read/write memory) an internal voltage level VINT used inside the component may differ from an external voltage supply (supply voltage level) VDD made available to the semi-conductor component. 
   In particular the internally used voltage level VINT may be lower than the level VDD of the supply voltage—for instance the internally used voltage level VINT may amount to 1.5 V, and the supply voltage level VDD for instance to between 1.5 V and 2.5 V, etc. 
   An internal voltage level VINT that is lower than the supply voltage level VDD has the advantage of allowing power dissipation inside the semi-conductor component to be reduced. 
   In addition, the voltage level VDD of the external voltage supply may be subject to relatively strong fluctuations. Therefore in order for the component to operate in as fault-free a manner and/or as reliably as possible, the supply voltage is generally converted—by means of a voltage regulator—to an internal voltage VINT (which is subject only to relatively minor fluctuations and regulated to a certain constant lower level). 
   Conventional voltage regulators (for instance corresponding down-converters) may for instance contain a differential amplifier and a p field effect transistor. The gate of the field effect transistor can be connected to an output of the differential amplifier and the source of the field effect transistor for instance to the external voltage supply. 
   A reference voltage VREF—subject only to relatively minor fluctuations—is applied to the negative input of the differential amplifier. The voltage emitted at the drain of the field effect transistor can then be directly back connected to the positive input of the differential amplifier, or for instance with a voltage splitter interposed. 
   The differential amplifier regulates the voltage present at the gate connection of the field effect transistor to such an extent that the (back-connected) drain voltage—and therefore the voltage emitted by the voltage regulator—remains constant and at the same time level as the reference voltage, or for instance higher by a particular factor. 
   In order to generate the above reference voltage VREF, an appropriate conventional reference voltage generating device, for instance a band-gap reference voltage generator can be used, which can—for instance by means of one or more diodes—generate a signal VBGR at a constant voltage level from the supply voltage (exhibiting the above relatively high supply voltage level VDD and occasionally possibly subject to relatively strong voltage fluctuations). 
   The signal at the constant voltage level VGBR can be fed to a buffer circuit, where it is (temporarily) retained, and then relayed further—in the form of signals at the above reference voltage level VREF—(for instance to the above voltage regulator (and/or the negative input of the corresponding voltage regulator differential amplifier) and/or further devices provided on the semi-conductor component, for instance further voltage regulators)). 
   The level of the internal voltage VINT emitted by each voltage regulator must be pre-set at such a low level that—taking into account all possible manufacturing faults such as inaccuracies and/or deviations—the semi-conductor component can be reliably operated under all conditions (for instance even with the briefest possible gate length of the transistors, connected to the internal voltage). 
   With—for instance—longer (actual) gate lengths, etc. the internal voltage VINT selected in the above manner is lower than it could be, which leads to losses in performance. 
   SUMMARY OF THE INVENTION 
   The invention is aimed at providing a voltage regulation system, and a novel voltage regulation process. 
   In one embodiment of the invention, there is a voltage regulation system with which a first voltage (VDD), present at an input of the voltage regulation system, is converted into a second, essentially constant voltage (VINT), which can be tapped at an output of the voltage regulation system where
         the voltage regulation system is additionally provided with a device for assessing the efficiency of components to be connected to the second voltage (VINT).       

   In case it is determined—by means of the (additional) device—that the efficiency of the components to be connected to the second voltage (VINT) has fallen below a critical limit (IDSATnom) characterizing the assessed efficiency, the second voltage (VINT) can be increased, thereby improving the efficiency of the components to be connected to the second voltage (VINT). 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention is described below in more detail with reference to exemplary embodiments and drawings, in which: 
       FIG. 1  shows a voltage regulation system according to an embodiment example of the invention. 
       FIG. 2  shows a buffer circuit that can be used in the voltage regulation system represented in  FIG. 1 . 
       FIG. 3  shows a voltage regulator that can be used in the voltage regulation system represented in  FIG. 1 . 
       FIG. 4  shows the level of the output voltage of the voltage regulation system shown in  FIG. 1 , in relation to the level of the saturation current (in both an activated and a non-activated state of the comparator circuit). 
       FIG. 5  shows a critical-limit subtraction circuit that can be used in the voltage regulation system represented in  FIG. 1 . 
       FIG. 6  shows a detailed representation of a process monitoring circuit that can be used in the voltage regulation system represented in  FIG. 1 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1  shows a schematic representation of a voltage regulation system  1 —arranged on a corresponding semi-conductor component—in terms of an embodiment example of the invention. 
   The semi-conductor component may for instance be a corresponding integrated (analog and/or digital) computer circuit, and/or a semi-conductor memory component such as a function memory component (PLA, PAL, etc.) and/or a table memory component (for instance a ROM or RAM), in particular an SRAM or DRAM. 
   The voltage regulation system  1  includes a reference voltage generating device  12  (for instance a band-gap reference voltage generator), a buffer circuit  13 , and one or more voltage regulators  14  (for instance corresponding down-converters). 
   As is apparent from  FIG. 1 , the reference voltage generating device  12  is supplied with an external voltage supply made available to the semi-conductor component—for instance corresponding lines  15   a,    15   b,    16   a,    17  and  19   b.    
   The supply voltage is at a relatively high voltage level VDD, which may—on occasion—be subject to relatively strong fluctuations. 
   The level of the supply voltage may for instance lie between 1.5 V and 2.5 V, for instance approximately between 1.6 V and 2.0 V (1.8 V±0.2 V). 
   From the supply voltage the reference voltage-generating device  12  generates a signal—for instance by means of one or more diodes—carrying a constant voltage level VBGR. 
   The signal carrying the constant voltage level VBGR is then relayed via a corresponding line  18  to the above buffer circuit  13  where it is (temporarily) retained, and further distributed—in the shape of a corresponding signal carrying a similarly constant voltage level VREF 1 —and for instance—via a line  19   a —to the above voltage regulator  14 , (and/or—for instance to a further voltage regulator, etc. for instance via corresponding further facilities provided on the semi-conductor component—not shown here). 
   The signal—carrying the constant voltage level VBGR—generated by the reference voltage generating device  12 —can be additionally used to generate a reference signal carrying a constant current IREF and emitted to a line  117 . 
     FIG. 2  shows a schematic detail representation of a buffer circuit  13  to be used in the voltage regulation system  1  shown in  FIG. 1 . 
   The buffer circuit  13  includes a differential amplifier  20  with a positive input  21   a  and a negative input  21   b,  and a field effect transistor  22  (here: a p-channel MOSFET). 
   One output of the differential amplifier  20  is connected to a gate connection of the field effect transistor  22  via a line  23 . 
   As is further shown in  FIG. 2 , the source of the field effect transistor  22  is connected via a line  16   b  (which—in terms of FIG.  1 —is connected to the above lines  16   a,    17 ) to the above supply voltage, which is carrying the above relatively high voltage level VDD. 
   As is apparent from  FIG. 2 , the above signal carrying the relatively constant voltage level VBGR and relayed via line  18  from the reference voltage generating device  12 , is present at the negative input  21   b  of the differential amplifier  20 . 
   The signal emitted at the drain of the field effect transistor  22  and carrying the above relatively constant voltage level VREF 1 , is back connected via a line  24 , and a line  25  connected to it, to the positive input  21   a  of the differential amplifier  20 , and—via line  19   a  connected to line  24 —further distributed to the above voltage regulator  14  (and/or—for instance via corresponding further lines not shown here—to the above further voltage regulator; etc.). 
     FIG. 3  shows a schematic detailed representation of a voltage regulator  14  to be used in the voltage regulation system  2  shown in  FIG. 1 . 
   The voltage regulator  14  has a differential amplifier  28  with a positive input  32  and a negative input  31 , and a field effect transistor  29  (here: a p-channel MOSFET). 
   One output of the differential amplifier  28  is connected to a gate connection of the field effect transistor  29  via a line  29   a.    
   As is further shown in  FIG. 3 , the source of the field effect transistor  29  is connected—via a line  19   b  ( and—as per FIG.  1 —the line  17  connected to it) to the supply voltage, which is at the above relatively high voltage level VDD. 
   The above (referenced signal—carrying the relatively constant voltage level VREF 1  and relayed by the buffer circuit  13  via line  19   a,  and a line  27  connected to it—is available at the negative input  32  of the differential amplifier  28 —and so on occasion (as is more closely described below and apparent from  FIG. 1 ) is a (further)(reference) signal, made additionally available by the comparator circuit  33 —connected in parallel to the above buffer circuit  13 —(which signal—as is more closely described below—carries a voltage level VREF 2 , and is relayed by the comparator circuit  33  to the voltage regulator  14  via a line  26  and a line  27  connected to it). 
   In a first embodiment of the voltage regulator  14 , the voltage (VINT) emitted at the drain of the field effect transistor  29  is directly back connected to the differential amplifier  28 ; for this the drain of the field effect transistor  29  can be (directly) connected via a line  19   c  (and another line connected to it but not shown here) to the positive input  31  of the differential amplifier  28  (the back-connected voltage (VINT_FB) present at the positive input  31  of the differential amplifier  28  is then as high as the drain voltage (VINT)). 
   In a contrasting alternative embodiment, the voltage (VINT) emitted at the drain of the field effect transistor  29  is back connected to the differential amplifier  28  via an interposed voltage splitter (not shown here), i.e. in divided form. For this, the drain of the field effect transistor  29  can be connected via the line  19   c  (and a line connected to it but not shown here) to a first resistance R 2  (not shown here) of the voltage splitter, which is on the one hand connected to the earth potential (via a further voltage splitter resistance R 1  (also not shown here)), and on the other to the positive input  31  of the differential amplifier  28 : the back-connected voltage (VINT_FB) present at the positive input  31  of the differential amplifier  28  will then be lower than the drain voltage (VINT)) by a given factor. 
   The differential amplifier  28  regulates the voltage present at the gate connection of the field effect transistor  29  in the above first embodiment of the voltage regulator  14  (which is directly back connected to the drain voltage (VINT)) in such a way that the (back-connected) drain voltage (VINT) is just as high as the reference voltage present at the positive input  32  of the differential amplifier  28  (i.e. VREF 1  (where VREF 1  is higher than VREF 2 ), and/or VREF 2  (where VREF 2  is higher than VREF 1 ) (see below)). 
   In the above second, alternative embodiment of the voltage regulator  14 —in which the drain voltage (VINT) is not directly back connected, but rather via the above voltage splitter—the voltage present at the gate connection of the field effect transistor  29  is regulated in such a way that the following applies:
 
 VINT=VREF ×(1+( R   2   /R   1 )
 
(or more accurately, as is more closely described below: VINT=VREF 1 ×(1+(R 2 /R 1 )), where VREF 1 &gt;VREF 2 , and/or VINT=VREF 2 ×(1+(R 2 /R 1 )), where VREF 2 &gt;VREF 1 )
 
   The voltage (VINT) emitted at the drain of the field effect transistor  29  (i.e. by the voltage regulator  14 ) to line  19   c,  represents the output voltage of the voltage regulation system  1  (with which for instance numerous devices provided on the semi-conductor chip, in particular circuitry such as transistors, etc. can be supplied with voltage). 
   The above regulation helps to ensure that the output voltage (VINT) of the voltage regulation system  1 —as illustrated in FIG.  4 —in contrast to the supply voltage (VDD)—which can be subject to relatively strong fluctuations—carries a constant value VINTnom, for instance 1.5 V, pre-set for example by means of appropriate fuses during a corresponding wafer test, in particular a wafer trimming process (but only when—as is more closely described above—the above component circuit  33 ) has not been activated, or—in the event that the corresponding transistors—and/or more accurately: through corresponding transistors used as reference transistors—which are connected to the internal voltage VINT—is actually stronger than, or at least as strong as the actually foreseen nominal saturation current (IDSATnom), and/or a corresponding nominal value (as is also more closely described below)). 
   In conventional voltage regulation systems the level of the internal voltage VINT emitted by each voltage regulator must be pre-set at a sufficiently a low level (for instance at the above value VINTnom), so that—taking into consideration any possible manufacturing inaccuracies and/or deviations—the semi-conductor component is able to be reliably operated under all circumstances (for instance even with the shortest possible gate length of the transistors connected to the internal voltage VINT). 
   Therefore in conventional voltage regulation systems—with longer (actual) gate lengths for instance (and thereby also accompanying lower saturation currents, etc.)—the internal voltage VINT selected in the above manner may be lower than it might otherwise have seen, which leads to performance losses. 
   With the voltage regulation system shown in  FIG. 1  on the other hand, when the efficiency of the components—transistors in particular—connected to the internal voltage VINT is lower than it might be (for instance as a result of correspondingly longer gate lengths, a corresponding higher critical limit voltage, etc.—and a consequently lower saturation current IDSAT (and/or a low nominal value IDSAT indicating this)—) at an internal voltage VINT of (say) the above level VINTnom, the voltage regulation system  1  generates an internal voltage VINT, which is correspondingly higher than the—actually foreseen—level VINTnom of the internal voltage. 
   In the present embodiment example it is determined by the above voltage increase detection circuit  36 —including the above comparator circuit  33 , a manufacturer&#39;s process monitor circuit  34 , and a critical limit subtraction circuit  35 —whether the efficiency of the transistors connected to the internal voltage VINT is lower than it might be at an internal voltage VINT of (say) the above level VINTnom (for instance due to correspondingly longer gate lengths, correspondingly high critical limit voltages, etc.—and therefore lower accompanying saturation currents IDSAT (in particular lower than a saturation current (IDSAT) which is lower than the nominal saturation current (IDSATnom)—)) (and therefore whether the internal voltage VINT—actually used—should be increased (for instance from VINTnom to VINT′, cf.  FIG. 4 )). 
   If—as is more closely described above—the voltage increase detection circuit  36  determines that the efficiency of the transistors connected to the internal voltage VINT is lower than it might be (for instance due to corresponding long gate lengths, etc.) at an internal voltage VINT of (say) above levels VINTnom, a signal VREF 2 , at a higher voltage level than that of the signal VREF 1  emitted by the buffer circuit  13  to line  19   a,  is emitted by the above comparator circuit  33  of the voltage increase detection circuit  36  to the above line  26 . 
   The level of the voltage VINT emitted by the voltage regulator  14  is then—as already indicated above—correspondingly increased (and in fact for instance—as also already indicated above—for instance from VINT=VINTnom=VREF 1  to VINT=VREF 2  (and/or from VINT=VIONTnom=VREF 1 ×(1+(R 2 /R 1 ) to VINT=VREF 2 ×(1+(R 2 /R 1 )). 
   Thereby the efficiency of the transistors connected to the internal voltage VINT is correspondingly increased—while still ensuring the further reliable operation of the semi-conductor components. 
   In order to assess the efficiency of the transistors connected to the internal voltage VINT (and thereby to answer the question of whether the voltage VINT should be increased) a nominal figure and/or nominal value (IDSAT) is used in the present embodiment example, which value is generated from the sum of the (simple) total of the saturation currents of a corresponding n-channel field effect (reference) transistor (IDSAT(n)), and double the total of the saturation currents of a corresponding p-channel field effect (reference) transistor (IDSAT(p)); i.e. a nominal saturation current value IDSAT, which is determined as follows:
 
 IDSAT=IDSAT ( n )+2× IDSAT ( p )
 
(Cf. also the process monitor current  34  as described in more detail below).
 
   This factor “2” for the p-channel field effect transistor arises from the fact that the saturation current driven by the p-channel field effect transistor is (at most) half as high as the saturation current driven by the n-channel field effect transistor. 
   In  FIG. 5  a schematic detailed representation of the above critical limit subtraction circuit  35  is shown. 
   It contains an n-channel field effect transistor  118 , as well as a high-impedance resistance  119  (or alternatively for instance a transistor in a corresponding high-impedance condition). 
   As is apparent from  FIG. 5 , the drain of the n-channel field effect transistor  118  is connected—via a line  111 —to the above internal voltage VINT (provided by the voltage regulator  14 ). 
   The gate of the n-channel field effect transistor  118  is connected—via a line  112 —to the line  111 , i.e.—in similar fashion—to the above internal voltage VINT (and to the drain of the field effect transistor  118 ). 
   The source of the n-channel field effect transistor  118  is connected—via a line  113 —to the high-impedance resistance  119 , which is earthed—via a line  114 —to (ground) potential. 
   In addition the source of the n-channel effect transistor  118  is connected—via a line  115 —(and as is also apparent from  FIG. 1 ) to the positive input of the comparator circuit  33 . 
   In the critical limit subtraction circuit  35 , with the help of the field effect transistor  118  and of the high-impedance resistance  119 , the level of the signal VINT_MINUS_VTH emitted at the source of the field effect transistor  118 —and relayed via the line  115  to the positive input of the comparator circuit  33 —is kept at a level that lies below that of the above internal voltage VINT by approximately the critical limit voltage VTH of the field effect transistor  118 . 
     FIG. 6  shows a schematic detailed representation of the process monitor circuit  34  used in the voltage regulation system  1  shown in  FIG. 1 . 
   It contains three n-channel field effect transistors  121 ,  122 ,  123 , and a p-channel field effect transistor  124  (with which the actual physical characteristics of the circuitry connected to the internal voltage VINT—in particular transistors—is to be simulated (by representation)), as well as a constant current source  125 . 
   With the help of the constant current source  125 , a constant current of the value IREFSAT is generated—for instance from the constant current of the value IREF created by the reference voltage generating device  12  and emitted to line  117 —to be of the same value as that of the above (ideally provided) nominal saturation current (IDSATnom)—actually foreseen for the transistors provided on the semi-conductor component 
   As is apparent from  FIG. 6 , the sources of the first, second and third n-channel field effect transistors  121 ,  122 ,  123 —are grounded—via corresponding lines  126 ,  127 ,  128 —to earth potential. 
   The gate of the first n-channel field effect transistor  121  is connected—via a line  129 —to the above internal voltage VINT (provided by the voltage regulator  14 ). 
   The gates of the second and third n-channel field effect transistors  122 ,  123  are connected to each other via a line  130  and—via a line  131  connected to it—to the drain of the third n-channel field effect transistor  123 . 
   As is further apparent from  FIG. 6 , the drain of the p-channel field effect transistor  124  is connected via a line  132  to the drain of the third n-channel field effect transistor  123 , and via the lines  131 ,  130  to the gates of the second and third n-channel field effect transistors  122 ,  123  via a line  132 . 
   In addition, the gate of the p channel field effect transistor  124  is grounded (to earth potential) via a line  133 . 
   The source of the p channel field effect transistor  124  is connected—via a line  134 —to the above internal voltage VINT (provided by the voltage regulator  14 ). 
   The drains of the first and second n-channel field effect transistors  121 ,  122  are connected to one another via a line  135 , as well as—via a line  136 —to the above constant current source  125 A—which drives the above constant current of the value IREFSAT through the n-channel field effect transistors  121 ,  122 . 
   In addition (and as is apparent from  FIG. 1 ), the drains of the first and second n-channel field effect transistors  121 ,  122  are connected—via the above line  135 , and a line  120  connected to it—to the negative input of the comparator circuit  33  (so that a signal VREFSUM emitted to the drains of the first and second n-channel field effect transistors  121 ,  122  is relayed to the negative input of the comparator circuit  33 ). 
   As is apparent from  FIG. 1 , the above comparator circuit  33  (and thereby the entire voltage increase detection circuit  36  carrying—in addition to the comparator circuit  33 —the above process monitoring circuit  34 , and the critical limit subtraction circuit  35 ) can be activated and deactivated by means of a corresponding signal (ENABLE signal) relayed via a line  135  of the comparator circuit  33 . 
   Advantageously the comparator circuit  33  (and thereby the entire voltage increase detection circuit  36 ) is at first left in a deactivated state—at least during the above test process, in particular the above wafer trimming process—and activated only later—in particular for instance during the actual operation of the semi-conductor components. 
   The n-channel field effect transistor  121 , and the p channel field effect transistor  124  (both being used as “reference transistors”) each always displays a gate length corresponding to a normal gate length—which length is also incorporated in the remaining transistors of the semi-conductor components—(whereby—as illustrated above—the actual gate length of the transistors  121 ,  124  (and correspondingly also of the remaining transistors) may rise above or fall below the nominal gate length value, due to manufacturing inaccuracies and/or deviations). 
   The width W of the n-channel field effect transistor  121  has been selected (corresponding to the above formula for the nominal saturation current value IDSAT (IDSAT=IDSAT(n)+2×IDSAT(p)) to be half the size of the width 2W of the p-channel field effect transistor  124 . 
   Due to the signal emitted by comparator circuit  33 —as per FIG.  1 —carrying the above voltage level VREF 2 , the voltage regulator  14  is adjusted in such a way that it makes available an internal voltage VINT, which is high enough to ensure that the (reference) transistors—shown in FIG.  6 —(i.e. the n-channel field effect transistor  121  and the p-channel field effect transistor  124 , and thereby also the other transistors provided on the semiconductor component) are operated in the saturation range. 
   By ensuring that the corresponding transistors can be operated in the saturation range, performance clearly exceeding that of state of the art components can be achieved—in particular when the gate lengths and/or critical limit voltages of the corresponding transistors fall below the (actually foreseen) nominal value. 
   As is apparent from  FIG. 6 , the above saturation current IDSAT(n) flows through the n-channel field effect transistor  121  (and thereby via line  126 , connected to the earth potential), as long as the level of the voltage VREFSUM present at the drain of the n-channel field effect transistor  121  a higher than the level of the internal voltage VINT, minus the critical limit voltage VTH—i.e., higher than VINT-VTH (which is determined by the above critical limit subtraction circuit  35 , and the comparator circuit  33 , and which is correspondingly secured by counter-adjustment (changing the internal voltage VINT) was added. 
   The n-channel field effect transistor  123  is do dimensioned that the p-channel field effect transistor  124  is—also—operated in the saturation current region. 
   The saturation current IDSAT(p) flowing through the p-channel field effect transistor is diverted via the n-channel field effect transistor  123  and the line  128  to ground potential (GND). 
   Because—as is described above, the width W of the n-channel field effect transistor  121  is one half of the width 2W of the p channel field effect transistor  124 , the current—flowing in total through the n-channel field effect transistor  121  and the p-channel field effect transistor  124  (i.e. the lines  126  and  127 )—therefore equates with the above saturation current nominal value IDSAT=IDSAT(n)+2×IDSAT(p). 
   As already described above, the above constant current source  125 —via line  136  connected to the transistors  121 ,  122 —causes a current flow at the level of nominal saturation current (IDSATnom) to take place. 
   Therefore the level voltage VREFSUM, present at the drain of the n-channel field effect transistor  121 , lies either above or below the level of the internal voltage VINT minus the critical limit voltage VTH—depending on whether the total current IDSAT(actual) flowing through both the transistors  121 ,  124 ), lies below or above the critical value of the above current IDSAT. 
   In other words, by means of the comparison—performed by the comparator circuit  33 —between the level of the voltage VREFSUM present on line  120  and the level of the voltage VINT_MINUS_VTH present on line  115 , it can be determined whether the efficiency of the transistor connected to the internal voltage VINT is sufficiently high, or whether—by increasing the internal voltage VINT—it can be increased. 
   In this case—as already described above—the comparator circuit  33  emits a signal VREF 2  via line  26  to the voltage increase detection circuit  36 , which signal indicates a higher voltage level than that of the signal VREF 1 , emitted by the buffer circuit  13  onto line  19   a.    
   The level of the voltage VINT emitted by the voltage regulator  14  is then—as already described above—correspondingly increased (and in fact—as also described already—for instance from VINT=VINTnom=VREF 1  to VINT=VREF 2  (and/or from VINT=VINTnom=VREF×(1+(R 1 /R 1 )) to VINT=VREF 2 ×(1+(R 2 /R 1 )).