Abstract:
A DC to DC converter is described having a bridge circuit coupled to the secondary windings of a transformer, the transformer supplying power to a capacitor and a constant current load source. The circuit parameters are chosen to provide a circuit that has quasi-resonant characteristics close to the frequency of the signal providing power to the transformer, but at a higher value. Other constraints on the circuit parameters are discussed. The resulting circuit provides an efficient transfer of energy from the source power supply to the load.

Description:
This is a continuation of co-pending application Ser. No. 07/158,117 filed on Feb. 16, 1988, which was a continuation of application Ser. No. 06/892,595 filed on Aug. 1, 1986 now abandoned. 
    
    
     RELATED PUBLICATIONS AND U.S. PATENTS 
     The following publications and U.S. Patents are related to the instant invention: 
     200-KHz Power FET Technology in New Modular Power Supplies, by Richard Myers and Robert D. Peck, Hewlett Packard Journal, Aug. 1981, pages 3 to 10. 
     A Practical Resonant Converter Using High Speed Power Darlington Transistors, by Sridhar R. Babu, PCI Mar. 1982 Proceedings, pages 122 to 141. 
     High Frequency Power Conversion with FET-Controlled Resonant Charge Transfer, by R. H. Baker, PCI Apr. 1983 Proceedings, pages 130 to 139. 
     Electronic Control System for Efficient Transfer of Power Through Resonant Circuits, invented by Francise Carol Schwarz, having U.S. Pat. No. 3,953,779, issued on Apr. 27, 1976. 
     DC To DC Converter, invented by David Harry Simmons and Paul Calvin Launderville, having U.S. Pat. No. 4,017,784, issued on Apr. 12, 1977. 
     Inverter For Supplying A Regulated Voltage, invented by Thomas M. Corry, having U.S. Pat. No. 4,024,453, issued on May 17, 1977. 
     Resonant Switching Converter, invented by Edward J. Miller, having U.S. Pat. No. 4,138,715, issued on Feb. 6, 1979. 
     DC To DC Converter, invented by David H. Simmons and Alfredo A. Panelo, having U.S. Pat. No. 4,158,881, issued on Jun. 19, 1979. 
     High Frequency Switching Circuit Having Preselected Parameters To Reduce Power Dissipation Therein, invented by Toshihiro Onodera, Youichi Masuda and Akira Nakajima, having U.S. Pat. No. 4,318,164, issued on Mar. 2, 1982. 
     Forward Converter Switching at Zero Current, invented by Patrizio Vinciarelli, having U.S. Pat. No. 4,415,959, issued on Nov. 15, 1983. 
     Optimal Resetting of the Transformer&#39;s Core in Single Ended Forward Converters, invented by Patrizio Vinciarelli, having U.S. Pat. No. 4,441,146, issued on Apr. 3, 1984. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to power supplies, and more particularly, to the type of power supply that converts an input DC voltage to an output DC voltage having a different magnitude. 
     2. Description of the Related Art 
     DC to DC converters have the property that a constant input voltage level can be converted to a constant output voltage level having a different magnitude, i.e. a DC input voltage can be converted to a higher DC output voltage or to a lower DC output voltage. In addition, the output voltage can be electrically isolated from the input voltage. 
     The present invention generally has application in converting higher DC voltage, applied to the DC to DC converter from the power distribution source, to a lower DC voltage. In particular, in a data processing system, the distribution of power at higher voltage levels reduces the I 2  R losses and reduces the effect of contact resistances of the distributing conducting path on the voltage level reaching the local power source. The lower DC voltage level from the DC to DC converter is compatible with the requirements of the circuit elements used in the data processing system. 
     One implementation technique for prior DC to DC converters involves the use of sinusoidal primary and sinusoidal secondary voltages and is referred to as a resonant DC to DC converter. Resonant converter circuits require an inductor, a capacitor and very fast diode clamps in the primary circuit (elements that are not required in the quasi-resonant DC to DC converter circuits described below). The resonant converter circuit has the advantage that the sinusoidal voltages reduce the switching losses in the field effect transistors and that the operation is consistent with high frequency operation. The high frequency operation environment permits the use of physically small transformer components and secondary filter circuit components. However, the high frequency operation also induces high dV/dt transients into the switching circuit causing the field effect transistors to experience gate drive problems. Furthermore, the primary switch device must handle larger than necessary switch currents. The circuit may require a Schottky diode in series with the field effect transistor as well as a high voltage 30 ns, 3 ampere diode in parallel with the Schottky diode and series field effect transistor. The use of resonant circuits can also result in a lack of stability when a high Q circuit is used (i.e. to minimize energy losses.) Finally the use of resonant circuits, with the inherent transfer of energy between components of the tank circuit, is fundamentally inconsistent with the unidirectional delivery of power to the components energized by the DC to DC converter. 
     More recently, Vinciarelli, in U.S. Pat. No. 4,415,959 and in U.S. Pat. No. 4,441,146 has described a quasi-resonant circuit. In the quasi-resonant circuit configuration, the leakage inductance of the transformer coupling the input and output portions of the converter forms, in combination with an external high Q capacitor, a resonant circuit. A capacitor between the leakage inductance of the transformer and the external capacitor, prevents the actual resonance of the circuit. The resonant frequency of the circuit is typically not the frequency at which the input terminals of the transformer are being activated. In addition, the circuits described in U.S. Patents by Vinciarelli have a single ended configuration, i.e. a single rectifying element in the secondary circuit of the transformer, and consequently operates at reduced power level. In U.S. Pat. No. 4,441,146, a circuit is described that resets the magnetic flux in the transformer arising from the single-ended implementation. 
     A need has therefore been felt for a DC to DC converter circuit that provides the advantages of the quasi-resonant DC to DC converter without the limitations of the prior devices. 
     FEATURES OF THE INVENTION 
     It is an object of the present invention to provide an improved DC to DC converter circuit. 
     It is a feature of the present invention to provide an improved DC to DC converter having a bridge circuit coupled to the secondary winding of a transformer circuit. 
     It is still another feature of the present invention to provide a circuit coupled to the secondary windings of a transformer that is tuned in accordance with frequency applied to the primary circuit of the transformer. 
     It is yet another feature of the present invention to provide an improved quasi-resonant DC to DC converter. 
     SUMMARY OF THE INVENTION 
     The aforementioned and other features are obtained, according to the present invention, by a DC to DC converter having switching elements providing pulsed activation for the primary terminals of a transformer. Coupled to the secondary terminals of the transformer is a bridge network applying voltage to a capacitor and supplying current to a constant current source load. The capacitor and the leakage inductance of the transformer have values chosen to provide a resonant circuit at a frequency related to the frequency of the pulsed activation of the primary windings of the transformer. Other parameters for the transformer and the capacitor are selected to provide improved circuit operation. 
     These and other features of the present invention will be understood upon reading of the following description along with the drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic block diagram of the components on the primary portion of the transformer in a DC to DC converter of the present invention. 
     FIG. 2 is a schematic block diagram of the components on the secondary portion of the transformer in a DC to DC converter of the present invention. 
     FIG. 3 is a diagram illustrating the amplitude of the current through diode D1, shown in FIG. 2, as a function of time. 
     FIG. 4 is a diagram illustrating the amplitude of the current through diode D2, shown in FIG. 2, as a function of time. 
     FIG. 5 is a diagram illustrating the amplitude of the voltage across capacitor C3, shown in FIG. 2, as a function of time. 
     FIG. 6 is a diagram illustrating the activation of the primary terminals of the transformer by the control circuit as a function of time. 
     FIG. 7 is a schematic block diagram of the circuit components coupled to the secondary terminals of the transformer when I1 is positive. 
     FIG. 8 is a schematic block diagram of the circuit components coupled to the secondary terminals of the transformer when transistor Q1 and transistor Q2 are not conducting. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     1. Detailed Description of the Figures 
     Referring now to FIG. 1, a block diagram of the circuit components coupled to the primary winding of a transformer TR1 is shown. A first terminal of V SUPPLY  is coupled to a drain terminal of a field effect transistor Q1 and to a first terminal of capacitor C1. A second terminal of V SUPPLY  is coupled to a source terminal of a field effect transistor Q2 and to a first terminal of capacitor C2. The drain terminal of transistor Q2 and the source terminal of transistor Q1 are coupled to a first primary winding terminal of transformer TR1, while a second primary winding terminal of transformer TR1 is coupled to second terminals of capacitors C1 and C2. The gate terminals of transistors Q1 and Q2 receive control signals from a control circuit. 
     Referring next to FIG. 2, a block diagram of the circuit components coupled to the secondary windings of transformer TR1 are shown. A first terminal of the secondary transformer TR1 winding is coupled to an anode terminal of diode D1, while a second terminal of the secondary transformer TR1 winding is coupled to an anode terminal of diode D2. A cathode terminal of diode D1 and a cathode terminal of diode D2 are coupled to a first terminal of capacitor C3 and to a first terminal of inductor L2. A second terminal of inductor L2 is coupled to a first terminal of capacitor C4, to a first V LOAD  terminal and to control circuit 21. A third (center-tapped) terminal of the secondary transformer winding is coupled to a second terminal of capacitor C3, to a second terminal of capacitor C4, to a second V LOAD  terminal and to control circuit 21. Control circuit 21 is coupled to the gate terminals of transistors Q1 and Q2. 
     Referring to FIG. 3, the current in diode D1 and the voltages applying the pulsed activation to the transistors Q1 and Q2 are shown as a function of time. At time TO, transistor Q1 has an activation voltage applied thereto and begins conduction. At time T2, during the activation of the transistor Q1, the current in diode D1 reaches a maximum value. At time T3, prior to the removal of the activation voltage from transistor Q1, conduction in diode D1 is terminated. And at time T4, the transistor Q1 has the activation voltage removed therefrom and ceases conduction. Current is also conducted through diode D1 between the activation of transistor Q1 and the activation of Q2. 
     Referring to FIG. 4, the current in diode D2 and the activation voltages for transistors Q1 and Q2 are shown as a function of time. In response to the activation voltage, transistor Q1 begins conduction at time TO and terminates conduction at time T4. (At time T1, the conduction in diode D2 is halted when the current through diode D1 (c.f. FIG. 3) becomes sufficiently large.) The current through diode D2 reaches a maximum during the activation period of transistor Q2, and ceases conduction prior to the end of the activation period of transistor Q2. Current is also conducted in diode D2 between the activation of the transistor Q1 and the activation of transistor Q2. 
     Referring next to FIG. 5, the voltage across capacitor C3 is shown for the same time interval as illustrated in FIG. 3 and FIG. 4. Capacitor C3 is charged by the current through diode D1 and through diode D2 minus the charge flowing through inductor L2. At time T5, the voltage across capacitor C3 falls below zero and diodes D1 and D2 enter a free-wheeling (undriven) mode of conduction. At time T6, the transistor Q2 begins conduction resulting in the deposition of charge through diode D2 on capacitor C3. 
     Referring to FIG. 6, the technique used by the control circuit 21 to regulate the energy applied to the primary terminals of the transformer is illustrated. The transistors Q1 and Q2, as a result of signals from control circuit 21, are conducting for fixed intervals. The time between the conducting periods of the transistors is variable. That is, to increase the power to the constant current source load 70, the time between conducting states of the transistors is shortened. To decrease the power to the load 70, the time between conducting state of the transistors Q1 and Q2 is lengthened. The determination of the period between conducting states of transistors Q1 and Q2 is determined by the load current applied to constant current source load 70. 
     Referring next to FIG. 7, the equivalent circuit of the secondary transformer TR1 circuit portion is shown for the time period when the current I1 through diode D1 is positive. A voltage determined by the characteristics of transistor Q1, in the conducting state, and the characteristics of the transformer TR1 is applied between the first and the center-tap terminal of the transformer TR1 secondary windings. The voltage causes current to flow through diode D1, through internal transformer resistance R1 and through the transformer leakage inductance L1. The current charges capacitor C3 which in turn provides current Ir to constant current source load 70. 
     Referring to FIG. 8, the equivalent circuit present when the primary terminals of the transformer TR1 are not energized (the recovery interval) is shown. Diodes D1 and D2 are shown in parallel for purposes of analysis. During this recovery interval, the inductor L2 (FIG. 2) maintains the flow of current to the constant current source load 70. This current continuation can discharge the capacitor C3 to the extent that the voltage across the capacitor C3 becomes negative. The negative voltage across the capacitor C3 causes current to flow through the transformer TR1 (and the equivalent resistor R1 and equivalent inductor L1E associated therewith) and through the diodes D1 and D2. 
     2. Operation of the Preferred Embodiment 
     The operation of the quasi-resonant circuit of the present invention can be understood in the following manner. Prior to the activation of transistor Q1, capacitor C3 has a negative voltage across the terminals and the output diodes D1 and D2 conduct equal currents in a non-driven (i.e. free-wheeling) mode of operation. At time T0, transistor Q1 is driven to the conducting state by application of signals from control circuit 21 and the transformer TR1 has approximately output voltage of V SUPPLY  applied to the first primary terminal. The second primary terminal, coupled to capacitors C1 and C2, is approximately at one half the output voltage of V SUPPLY  or 150 volts. The current in diode D1 begins to increase while the current in diode D2 decreases in accordance with the resonance frequency of the transformer leakage inductance L1 and capacitor C3. The sum of diode currents in diodes D1 and D2 charge the capacitor C3 and consequently supply current to the (approximately) constant current source load 70. At time T1, diode D2 no longer conducts current because of the increased voltage across the capacitor C3 as a result of the charging current through diode D1. At time T2, the current in diode D1 reaches a maximum value. At time T3, the current in diode D1 can no longer flow because of the relative values of the voltage across capacitor C3 and the voltage between the center-tapped terminal of transformer TR1 and the terminal of transformer TR1 to which diode D1 is coupled. At time T4, transistor Q1 ceases conduction because of the termination of the activation signal from control circuit 21. At time T5, capacitor C3 has discharged through inductor L2 to such an extent that the voltage across capacitor C3 is negative, forcing diodes D1 and D2 into conduction in a recovery mode of operation. 
     The control circuit 21 operates on a fixed time on and a variable time off mode of operation for the conduction of transistors Q1 and Q2, thereby controlling the power delivered to the constant current source load 70. Therefore regulation by the DC to DC converter is accomplished by controlling the time interval between activation pulses, i.e. the frequency of the activation pulses. 
     To repeat the cycle, transistor Q2 is activated at time T6 and the first primary terminal is essentially coupled to the negative terminal of V SUPPLY . The current in diode D2 increases as the current in diode D1 decreases again in accordance with the equivalent impedances of the transformer TR1 and the impedance of capacitor C3. Thus, the power source V SUPPLY  delivers power to the transformer each time that one of the transistors conducts current. Defining the following terms, 
     V1=the bipolar square wave equal to the voltage of the power bus divided by the transformer turns ratio N1, the power pulse time period being equal to the transistor Q1 period of conduction. 
     Ir=constant current load (approximation). 
     L1=transformer leakage inductance with 1/2 the secondary shorted 2.5 inches from the transformer. 
     L1E=transformer leakage inductance with the full secondary shorted 2.5 inches from the transformer. 
     V D1  =forward diode voltage drop. 
     V C3  =voltage across resonant capacitor C3. 
     I1=current through inductance L1. 
     Then 
     
         V1(t)=V.sub.D1 +R1*I1+L1*dI1/dT+V.sub.C3                   (1) 
    
     
         if I1&gt;0 and 
    
     
         for TO&gt;t&gt;T3 
    
     
         I1=C3*dV.sub.C3 /dT+Ir                                     (2) 
    
     
         if I1&gt;0 and 
    
     
         for T0&gt;t&gt;T3 
    
     Substituting equation 2 into equation 1 and neglecting the voltage drop across diode D1; 
     
         V1(t)=R1*C3*dV.sub.C3 /dT+Ir*R1+V.sub.C3 +L1*C3*d.sup.2 V.sub.C3 /dT.sup.2( 3) 
    
     Equation (3) is a second order differential equation that has the following properties; 
     
         Resonant Frequency=1/6.28*(L1*C3).sup.1/2 
    
     
         and 
    
     
         Damping Coefficient=R1/2*(L1/C3).sup.1/2 
    
     In the time interval T3&lt;t&lt;T5, diode D1 is back-biased (i.e. nonconducting) while the voltage, V C3 , across capacitor C3 is decreasing. At time T5, both diodes, D1 and D2, become conducting as the voltage across the resonance capacitor C3 becomes negative. With both diodes conducting and the transformer output voltage having a negative value, the transformer output is virtually short-circuited across the full winding. Therefore, the equivalent inductance of the transformer is L1E. Theoretically, the inductance L1E should be 1/4 L1 because the turns ratio for the operative embodiment is 1/2. As a practical matter, L1E is 40% of the inductance L1. In the time interval T5&lt;t&lt;T6, the system is defined by the equation: 
     
         d.sup.2 V.sub.C3 /dt.sup.2+{ R/L1E}*dV.sub.C3 /dt+V.sub.C3 /L1E*C3+Ir*R/L1E*C3=0                                     (4) 
    
     Note that the voltage across resonant capacitor C3 rings (resonates) at a higher frequency because L1E is smaller than L1. More than one cycle resonance is possible because of the high Q of the circuit. This phenomenon can cause slight jumps in the average output voltage as the repetition rate is varied. 
     As pointed out above, the regulation of the output signal is maintained by controlling the time between power pulses. The load is assumed, as an approximation, to be a constant current load. Because the DC resistance of the output choke inductor, L2, is negligible, the average voltage across the capacitor C3 can be considered to be approximately equal to the average output voltage. 
     At the time T6, the transistor Q2 becomes conducting, and the cycle is repeated. 
     In order to optimize the circuit design, the component values are chosen in the following manner. The transformer TR1 turns ratio is selected to be the same as would be required in a fixed frequency pulse width modulator design as a first approximation. At low line voltage and full load power consumption, the DC to DC converter is operating at maximum operating frequency and the voltage across the resonant capacitor C3 is nearly sinusoidal in shape. The minimum value of the voltage across the resonance capacitor C3 is approximately -5.0 volts, while the peak voltage value across the resonance capacitor is equal to the bus voltage divided by the turns ratio N1. The peak voltage across a high Q resonant circuit is twice the DC excitation. However, the DC voltage seen by the transformer TR1 is divided by two because of the presence of the two capacitors C1 and C2, so that these two factors cancel. The ratio of the output load impedance divided by the converter surge impedance should be approximately 1.0 to maintain sinusoidal transformer currents. (The converter surge impedance is defined as one half the square root of the transformer output leakage inductance L1 divided by the resonance capacitor C3). The transformer leakage inductance must be controlled to a±15% tolerance and have a tank frequency with capacitor C3 of 1.15 times the maximum permitted drive frequency. Capacitor C3 is selected to be a polyproplylene film capacitor. This capacitor should have an internal resonant frequency at least four times the resonant frequency of the secondary transformer circuit and be able to accommodate an RMS current of 41% of the output load current at the circuit resonant frequency. Selection of the component values in this manner permits the charging of the capacitor C3 within the time period of the transistor (Q1 or Q2) activation. These values also permit discharging of the capacitor C3 during the period when neither transistor Q1 or transistor Q2 is conducting. 
     The foregoing description is included to illustrate the operation of the preferred embodiment and is not meant to limit the scope of the invention. The scope of the invention is to be limited only by the following claims. From the foregoing description, many variations will be apparent to those skilled in the art that would yet be encompassed by the spirit and scope of the invention.