Abstract:
An improved Class D amplifier which does not utilize a clock, is self-oscillating, and reduces switching errors and distortions. The amplifier includes positive and negative switches which are selectively activated to reduce errors in gain in the analog signal produced by the amplifier.

Description:
FIELD OF THE INVENTION 
     This invention pertains to amplifiers. 
     More particularly, the invention pertains to an improved Class D amplifier which does not utilize a clock, which is self-oscillating, and which reduces switching errors and distortions. 
     BACKGROUND OF THE INVENTION 
     Conventional Class D amplifiers are each comprised of an integrator summed with a fixed frequency triangle wave and inputted into the switch control. The switching waveform is filtered through a Low Pass Filter (LPF) and outputted to the speaker or other load. Such amplifiers are illustrated in FIGS. 1 to 3 of U.S. Pat. No. 4,415,863, and have certain disadvantages. 
     First, the clock frequency in the amplifiers is fixed, resulting in a constant, large, high frequency component that can potentially create noise in FM tuners, switching power supplies, or other parts of an audio system. 
     Second, the clock frequency is generally selected to optimize operation under heavy load conditions. As a result, when an audio signal input is not applied, poor signal to noise ratio measurements are produced. 
     Third, the feedback is such prior art systems is taken prior to the low pass filter. This makes it difficult to control the speaker because a nonlinear generation of the sine wave is produced as the load of the speaker changes impedance. This causes poor total harmonic distortion and poor noise and damping factor measurements. 
     Accordingly, it would be highly desirable to provide an improved Class D amplifier which would compensate for problems caused by a fixed clock frequency and which would yield better speaker control. 
     Therefore, it is a principal object of the invention to provide an improved Class D amplifier. 
     A further object of the instant invention is to provide an improved Class D amplifier which reduces the likelihood that excess noise will be created in remaining portions of an audio system used in combination with the Class D amplifier. 
     Another object of the invention is to provide an improved Class D amplifier which enables better control of a speaker receiving an analog signal from the amplifier. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other, further and more specific objects and advantages of the invention will be apparent to those skilled in the art from the following detailed description thereof, taken in conjunction with the drawings, in which: 
     FIG. 1 is a block diagram illustrating a Class D amplifier constructed in accordance with the principles of the invention; 
     FIG. 2 is a circuit diagram illustrating the amplifier of FIG. 1; and, 
     FIG. 3 is a Spice diagram illustrating the analog signal produced by the Class D amplifier superimposed on the square wave generated in the amplifier prior to production of the analog signal. 
    
    
     SUMMARY OF THE INVENTION 
     Briefly, in accordance with the invention, I provide an improved self-oscillating audio Class D amplifier for an input signal. The amplifier includes a detector for receiving a control signal and producing a digital waveform switching signal to activate one of a pair including a positive switch and a negative switch to correct gain produced by the Class D amplifier; an output stage including a positive switch and a negative switch, the output stage receiving the switching signal and activating one of the switches to produce a digital driving signal; an output filter to receive the digital driving signal, remove switching noise and provide an amplified audio analog output signal to drive a load; and, an error detection amplifier circuit to receive the amplified analog output signal and compare the output signal to the input audio signal for gain-correction purposes, and to produce the control signal. 
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Turning now to the drawings, which depict the presently preferred embodiments of the invention for the purpose of illustrating the practice thereof and not by way of limitation of the scope of the invention, and in which like reference characters refer to corresponding elements throughout the several views, FIG. 1 illustrates a Class D amplifier constructed in accordance with the principles of the invention and including error amplifier circuit  14 , zero cross detector  15 , output stage  16 , output filter  19 , feedback signal  21 , and speaker  20  or another load. Circuit  14  produces an ADJ OUT control signal  17 . Detector  15  produces a DIG OUT signal  18 . 
     In the circuit diagram of FIG. 2, the error amplifier circuit  14  includes resistors R 1 , R 2 , R 3  and amplifier A. The zero crossing detector  15  includes VCC+20V, includes resistors R 4 , R 5 , includes current source C 2 , and includes transistors T 1 , and T 2 . The output stage  16  includes MOSFET switches M 1  and M 2 , the driver circuitry MC 1  for MOSFET switch M 1 , the driver circuitry MC 2  for MOSFET switch M 2 , power supply VCC, power supply VEE, transistors T 3  and T 4 , current source C 1 , and resistors R 6  and R 7 . The output filter  19  includes inductor L, capacitor C, and AMP OUT. 
     In operation, an audio analog input signal  12  is fed into an error amplifier circuit  14  that adjusts the signal and produces a digital ADJ OUT signal  17 . The ADJ OUT control signal  17  is a step response PWM waveform. 
     The signal ADJ OUT control  17  is received by zero crossing detector  15  and transformed into a high frequency digital DIG OUT signal  18 . In this respect, zero crossing detector  15  functions as a pulse width modulator. 
     The zero crossing detector  15  also separates out positive and negative signals and determines whether the high side MOSFET switch M 1  is turned on or whether the low side MOSFET switch M 2  is turned on. MOSFET switch M 1  is connected to the positive rail. MOSFET switch M 2  is connected to the negative rail. Consequently, if the voltage is positive, detector  15  turns on the high side positive switch M 1 . If the voltage is negative, detector  15  turns on the low side negative switch M 2 . While the circuit is operating, switches M 1  and M 2  toggle back and forth continuously. Zero crossing detector  15  alternates between the M 1  and M 2  switches but does not allow both switches to be on at the same time. 
     The output of the zero crossing detector  15  controls the switches M 1  and M 2  in the output stage  16 . 
     The high frequency digital signal (DGI OUT)  18  is received by the output stage  16 . When signal  18  activates positive switch M 1 , switch M 1  is connected to summing point S and is pulled up to VCC. When signal  18  activates negative switch M 2 , switch M 2  is connected to summing point S and is pulled down to VEE. VCC is a positive power supply which produces, by way of example and not limitation, 50 volts to 100 volts. VEE is a negative power supply which produces, by way of example and not limitation, minus 50 to minus 100 volts. 
     The analog signal coming out of the output filter  19  is a sine wave  32 . In FIG. 3 sine wave  32  is superimposed on the switching square wave  33 . Square wave  33  represents the switching between MOSFET switches M 1  and M 2 . The width of a pulse in square wave  33  is the length of the horizontal portion at the top or bottom of the pulse. Consequently, the width of the pulse when sine wave  32  output is at about 50V (as indicated by point  34 ) is, in FIG. 3, much longer than the width of the pulse when the sine wave output is at about 0 V (as indicated by point  35 ). 
     The signal from the output stage  16  is received by the output filter  19 . 
     The output filter  19  removes high frequency components (include switching noise) having frequencies in the range of about 10 KiloHertz to 250 KiloHertz. The resulting low frequency sine wave signal which leaves filter  19  typically has a frequency in the range of about 20 Hertz to 200 Hertz. Filter  19  also converts the digital signal from stage  16  back into an analog signal capable of driving an external load like speaker  20 . The output signal from filter  19  is an amplified version of the audio input signal. The output signal from filter  19  typically has a gain in the range of five to fifteen, although the gain can vary as desired. 
     Feedback  21  is taken from the signal produced by output filter  19 . The feedback  21  is returned to a difference amplifier in the error amplifier circuit  14 . The difference amplifier compares the amplitudes and phase relationships of the feedback  21  and of the audio in signal  12 . Resistors R 1  and R 2  function to compensate for the gain in the feedback signal such that the feedback signal is divided down by resistors R 1  and R 2  and then passes into the difference amplifier, and such that the divided down feedback signal has an amplitude and phase which ideally is identical to the amplitude and phase of the audio in signal  12 . 
     If the amplitude of the divided down feedback signal is not equivalent to that of the audio in signal, then the error amplifier circuit  14  sends a counter pulse or control signal  17  to compensate. For example, if the feedback signal  21  (after being divided down by resistors R 1  and R 2 ) indicates that the positive voltage is too low (i.e., the gain with respect to the audio signal  12  input to circuit  14  is 9.9 to 1.0 instead of a desired 10.0 to 1.0, or, in other words the voltage output from output filter  19  for a point along sine wave  32  is not as great as desired) then the counter pulse from circuit  14  activates transistors T 1  and T 4  to hold switch M 1  on or closed until the feedback signal indicates that the gain is at least 10.0 (or greater than 10.0) to 1.0. 
     If the feedback signal  21  (after being divided down by resistors R 1  and R 2 ) indicates that the positive voltage is too high (i.e., the gain with respect to the audio signal  12  input to circuit  14  is 10.1 to 1.0 instead of a desired 10.0 to 1.0, or, in other words the voltage output from output filter  19  for a point along sine wave  32  is greater than desired) then the counter pulse from circuit  14  activates transistors T 2  and T 3  to hold switch M 2  on or closed until the feedback signal indicates that the gain is at least 10.0 (or less than 10.0) to 1.0. 
     If the feedback signal  21  indicates that the negative voltage is too high (i.e., the gain is 10.1 to 1.0 instead of 10.0 to 1.0), then the counter pulse from circuit  14  activates transistors T 1  and T 4  to hold switch M 1  on or closed until the feedback signal indicates that the gain is 10.0 (or less than 10.0) to 1.0. 
     If the feedback signal  21  indicates that the negative voltage is too low (i.e., the gain is 9.8 to 1.0 instead of 10.0 to 1.0), then the counter pulse from circuit  14  activates transistors T 2  and T 3  to hold switch M 2  on or closed until the feedback signal indicates that the gain is 10.0 (or greater than 10.0) to 1.0. 
     If the error is small, i.e. if the gain is 10.0 or is close to 10.0, then width of pulses in the square wave signal  33  leaving the output stage  16  is small and the pulses leave stage  16  at a higher frequency. 
     If the error is large, i.e. if the gain is not close to 10.0 (but is, for example 10.3), then the width of pulses in the square wave signal  33  leaving the output stage  16  is larger and the pulses leave stage  16  at a lower frequency. 
     By way of further example, if after comparing the feedback signal  21  to the input signal  12 , the error amplifier circuit  14  determines that at point  31  on the sine wave  32  the voltage is 50 volts instead of the desired 51 volts, circuit  14  compensates by turning on switch M 1  until the voltage on sine wave  32  increases to a desired level. 
     By way of further example, if after comparing the feedback signal  21  to the input signal  12 , the error amplifier circuit  14  determines that at point  30  on the sine wave  32  the voltage is at minus 41 volts instead of the desired minus 39 volts, the circuit  14  compensates by turning on switch M 1  until the voltage on sine wave  32  “decreases” from minus 41 volts to the desired minus 39 volts. 
     By way of further example, if power supply VCC produces 100 volts, if the signal produced by filter  19  is producing positive voltage with a gain of nine with respect to input signal  12 , and if a gain often is desired, then circuit  14  produces a positive signal to turn on switch M 1  until the gain increases to ten. If the gain happens to increase past ten to, for example, 10.1, then circuit  14  produces a negative signal to turn on switch M 2  until the gain for the positive voltage decreases back to ten. This automatic “self oscillating” or “hunting” pattern eventually typically results in there only being a small error between the actual gain in the signal leaving filter  19 . 
     A classic Class D amplifier has a built in clock and constantly switches. 
     One primary advantage of the Class D amplifier of the invention is that it does not utilize or require a clock and does not require the additional parts necessary to produce a clock signal. 
     As would be appreciated by those of skill in the art, constant currents sources C 1  and C 2  constantly deliver current for the availability of other electronic components. 
     When it is desired to turn on MOSFET switch M 1 , error amplifier circuit  14  produces a positive signal which turns on transistor T 1  and pulls current through resistor R 4  and transistor T 4  resutling in current sourced to resistor R 6  generating a voltage for the buffer MC 1 . 
     When it is desired to turn on MOSFET switch M 2 , error amplifier circuit  14  produces a negative signal which turns on transistor T 2  and pulls current through resistor R 5  and transistor T 3  resulting in current sourced to resistor R 7  generating a voltage for the buffer MC 2 . 
     A buffer or any other desired circuitry can be utilized in MC 1  and MC 2  to drive switches M 1  and M 2 . If desired a transistor, IGBL or other switch can be utilized in place of switches M 1  and M 2 . A transformer or other switch activation means can be utilized in place of transistors T 1  to T 4 . 
     Filter  19  can be a two pole filter, four pole filter, six pole filter, or any other filter means which performs the function of removing high frequencies and producing an analog signal for a speaker or other load. 
     As the magnitude of the error between the desired gain produced by the amplifier of the invention increases, operation of the amplifier circuit slows. In particular, when a switch M 1 , M 2  is held open to compensate for an error, current ramps up through inductor L, voltage ramps up through capacitor C, and voltage ramps up at the AMP OUT intermediate the inductor L and capacitor C. The time required to ramp up current or voltage, as the case may be, slows operation of the circuit and facilitates large error corrections. Slowing down the operation of the circuit also improves the efficiency of the circuit by not forcing the circuit to continually switch, which generates additional switching losses. 
     When switching is occurring and is producing the square wave pattern shown in FIG. 3, the amplifier circuit of the invention allows the output stage  16  to latch to the power supply rail, reducing the frequency of operation so that it equals the frequency of operation of the input. Such latching minimizes switching dissipation and maximizes the possible output of the system. 
     When the magnitude of the error between the desired gain and gain actually produced in the signal exiting filter  19  is at a minimum, the frequency of switching increases and the width of each pulse decreases due to the minimal amount of correction necessary to maintain proper output. This “speeding up” helps maintain low noise performance when little or no signal is applied. This increase in noise performance is a by-product of the increased switching speed being filtered more efficiently by the output filter.