Abstract:
Circuit architecture of an x-y addressable image sensor, in particular to that of a Complementary Metal Oxide Semiconductor (CMOS) active pixel sensor (APS). A substrate having an area divided into a plurality of pixel areas arranged in a series of rows and columns, having at least one control area separate from the pixel areas; a pinned photodiode formed in at least one of the pixel areas of the substrate; a readout transistor integrated on the pixel area of the substrate and operatively coupled to the pinned photodiode through a transfer gate and a charge to voltage converter; a row selection circuit having at least one selection transistor integrated on the substrate in the area for selecting the pixel area; a column selection circuit for selecting a group of pixels, the selection circuit formed in one of the control areas separate from the pixel areas, the selection circuit further comprising a column readout circuit including a double delta sampling circuit formed from a process that is compatible with CMOS technology; and a reset mechanism for resetting the floating diffusion. The present invention further comprises the use of overlapping gates to reduce the overall size requirements.

Description:
CROSS REFERENCE TO RELATED APPLICATION: 
     Reference is made to and priority claimed from U.S. Provisional Application Serial No. 60/006,261, filed Nov. 7, 1995, entitled A CMOS ACTIVE PIXEL SENSOR USING A PINNED PHOTODIODE. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates generally to the field of active pixel sensors, and more particularly to the architecture control circuits for active pixel sensors. More specifically, the invention relates to CMOS control circuits for active pixel sensors. 
     2. Description of the pior Art 
     Prior art active pixel sensors made from a CMOS process have used source/drain implants to form a photodiode, and polysilicon to form photogates as the light sensing elements. These light sensing elements have suffered from poor quantum efficiency, lag, and noise. 
     In order to overcome these problems, integration of a pinned photodiode in an active pixel sensor light sensing element was disclosed by Lee et al in U.S. Patent Application No. 08/421,173 to facilitate a pinned photo diode light sensing element within the architecture of an active pixel sensor. There is a shortcoming within this prior art device in that it does not show the manner in which the pixels are controlled by the control circuitry. 
     Prior art devices have numerous problems in integrating a camera system on a chip using CMOS process technology. These problems include column fixed pattern noise and the inability to fit the selection circuitry with the corresponding output amplifiers into a desired pixel pitch. 
     As can be seen by the foregoing discussion, there remains a need within the art for a method and apparatus of incorporating a pinned photodiode based image sensor within a CMOS device to alleviate fixed pattern noise, reduce the overall size of the device to achieve the desired pixel pitch, and to provide for a means to compensate for threshold voltage variation. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to overcoming one or more of the problems set forth above. This invention relates to the circuit architecture of an x-y addressable image sensor, in particular to that of a Complementary Metal Oxide Semiconductor (CMOS) active pixel sensor (APS) array. The invention describes elements of circuits and their embodiments to operate an APS which has a Pinned Photo Diode as its image sensing element. 
     An active pixel sensor incorporating a pinned photo diode offers advantages over conventional photogate or photodiode based APS by having high quantum efficiency, low dark current, no image lag, and low reset noise. This invention summary describes the circuitry building blocks, architecture, and circuit elements used in building this sensor. 
     Briefly summarized, one aspect of the present invention, describes an active pixel sensor comprising: a substrate having an area divided into a plurality of pixel areas arranged in a series of row and columns, having at least one control area separate from the pixel areas; a pinned photodiode formed in at least one of the pixel areas of the substrate; a readout transistor integrated on the pixel area of the substrate and operatively coupled to the pinned photodiode through a transfer gate and a charge to voltage conversion means; at least one selection transistor integrated on the substrate that is capable of selecting one row of the pixel areas; a column selection circuit capable of selecting a group of pixels formed within the substrate in one of the control areas separate from the pixel areas, the selection circuit further comprising a column readout circuit including a double delta sampling circuit formed from a process that is compatible with CMOS technology; and a reset circuit. The present invention further comprises the use of overlapping gates to reduce the overall size requirements. 
     These and other aspects, objects, features, and advantages of the present invention will be more clearly understood and appreciated from a review of the following detailed description of the preferred embodiments and appended claims, and by reference to the accompanying drawings. 
     ADVANTAGEOUS EFFECT OF THE INVENTION 
     The present invention has the following advantages listed below: 
     Integrates the pinned photo diode light sensing element with specific control and readout circuitry to improve noise and spectral response characteristics; 
     Allows for integration of a camera system on a single chip using a CMOS process to provide reduced size and lower noise; 
     Provides a control and readout circuit having low noise with an active pixel sensor array having a pinned photodiode light sensing element; and 
     Improves the fixed pattern noise characteristics of a CMOS active pixel sensor. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows the row and column addressing of a pixel array; 
     FIG. 2 shows a cross sectional view of eight transistors with overlapping polysilicon used to form a NAND gate; 
     FIG. 3 shows a schematic of the column control logic of the present invention; 
     FIG. 4 shows a schematic of the row timing and control; 
     FIG. 5 shows a schematic of the row timing and control; 
     FIG. 6 shows a pinned photodiode APS pixel; 
     FIG. 7 shows a layout of the FIG. 6 schematic; 
     FIG. 8 shows a timing diagram of the operation; and 
     FIG. 9 shows a layer level diagram of the chip showing the layers including the lens and color filter array layers. 
    
    
     To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. 
     DETAILED DESCRIPTION OF THE INVENTION 
     This invention relates to the circuit architecture of an x-y addressable image sensor, in particular to that of a Complementary Metal Oxide Semiconductor (CMOS) active pixel sensor (APS) array. An example pixel array size of the present invention is 256×256 pixels and the overall chip size is 1.2×1.2 cm with a 40 pin pad frame. All of the row and column circuitry is designed with a 40 μm pitch to match the pixel size using a 2 micron design rule. The chip is designed to operate at 5 Volt CMOS voltage levels. Additional power supply voltages of 5, 2.5, and 1.25 Volt Direct Current power supplies may be used to enhance the performance. 
     Referring to FIG. 1, which is a block diagram of an active pixel sensor as envisioned by the present invention. The active pixel sensor  5  comprises an array of pixels  10  that are arranged in rows and columns. The rows of the sensor  5  are provided with a global control logic block, generally referred to as row decoder  12  that has individual control circuits  22  for each of the rows within sensor  5 . Global column addressing decoder  16  decodes column addresses for the column signal processing section  14  has individual control circuits  24  for each of the columns within sensor  5 . 
     Referring to FIG. 2, the row and column addressing of the 256×256 pixel array is preferably carried out using 8-input NAND gate  100 , or the functional equivalent thereof. FIG. 2 shows the cross-section of the 8 n-channel transistors  110 - 117  in series to form the 8-input NAND gate  100 . For row addressing, the inputs to n-channel transistors 110-117 are generally referred to as a 0 -a 7 , and for column addressing, the inputs to the n-channel transistors  110 - 117  are generally referred to as b 0 -b 7 . 
     The eight series n-channel transistors  110 - 117  in the 8-input NAND gate  100  were implemented using overlaid poly1-poly2 gates. As seen in FIG. 2, there is a diffusion  120  between the third gate  112  and the fourth gate  113 , as well as diffusion  122  between the sixth gate  115  and seventh gate  116 . These gates having diffusions  120 ,  122  between them are separated by a spacing of 2 μm to allow room for the diffusions  120 ,  122 . 
     These transistors each have a gate length of 2 μm with 2 μm overlap of the poly1-poly2 gates of the adjacent transistors. Accordingly, the gate of transistor  110  overlaps gate  11  by 2 μm, for example. The center gate  111  is overlapped by 2 μm on each side, by gates  110 ,  112 . This transistor formation, including overlapping poly gates, is similar to the formation that is used in charge coupled device (CCD) technology. 
     FIG. 2 shows the layout implementation of the 8 series n-channel transistors  110 - 117  with overlapping gates for the 8-bit NAND gate  100 . 
     The schematic of the column control logic which generates the column selection signal SEL j  is shown in FIG.  3 . The column selection signal is used with the crowbar signal to perform the fixed pattern noise reduction operation. The column control logic also controls the serial readout of the data as will be explained. 
     Still referring to FIG. 3, a first bank of column selection transistors  300  are connected to create a negative input OR gate. If any of the column inputs (b 0  to b 7 ) are active (low), the corresponding transistor turns on and supplies V+ voltage to NAND gate  100 . When all of the inputs b 0  to b 7  are inactive (high), an inactivity signal  302  is provided. This inactivity signal  302  is buffered by buffer circuit  304  and level adjusted and combined with the SEL signal by the level shifting AND gate circuit  306  to form the selection signals SEL j , which are produced between pixel sampling interval. The SEL signal is used as described herein to reduce fixed pattern noise. OR gate  300  preferably uses transistors having a width to length ratio of 9/2, and a NAND gate  100  having a width to length ratio of 22/2. 
     The column readout circuit is shown in FIG.  4 . The elements within pixel region  400 , are contained in each pixel of the array. Included within region  400  are pinned photodiode  402 , transfer gate  404 , and floating diffusion  406 . The photodiode used herein, is preferably a pinned photodiode  402  which yields improved blue response and without image lag problems. The pinned photodiode  402  is preferably not overcoated by polysilicon or other interconnect material, thereby enhancing blue response. 
     Also included within region  400  is reset transistor  410  which operates to reset the floating diffusion  406  by clamping it to a zeroing voltage shown as V+. Source follower  412  receives and buffers the potential on floating diffusion  406 . 
     Row decoder transistor  414  is turned on to enable the voltage on source follower  412  to be passed to the column processing circuitry. 
     The pinned photodiode  402  and the controlling devices, including gates and transistors, are preferably made with any technology that is compatible with CMOS, such as NMOS 
     Elements to the left of common chip region  420 , and to the right of region  400  are the column circuitry  405  provided for each column of pixels. 
     Column circuitry  405  includes stacked capacitors  422 , each formed by a MOS capacitor  424  underneath a poly1-poly2 capacitor  426 . This capacitor bank forms a high capacitance low kTC noise capacitor. 
     It is preferred that these devices also be made using a CMOS compatible process. Column circuitry  405  is used as the sample and hold capacitor to increase the capacitance and reduce the kTC noise on this capacitor. 
     In operation, the reset level of the floating diffusion is first sampled during any readout cycle by turning on the sample and hold reset transistor  430 , to transfer the reset charge level on the floating diffusion to the reset capacitor bank  432 . At the end of the light integration period, the photo-generated charge in the photodiode  402  is transferred by transfer gate  404  to floating diffusion  406 . This photocharge adds to the reset level already present in the floating diffusion  406 . The total is sampled by turning on the sample and hold transistor  434 , thereby transferring the charge to capacitors  424  and  426 . Each reset level for each pixel is subtracted from each signal level for the same pixel using off-chip circuitry. This correlation of the values effectively minimizes the Johnson noise within the pixel. 
     Crowbar switch  428  is used to reduce the fixed pattern noise by effecting a clamped reset. 
     This process is called “double delta sampling” (DDS). The crowbar switch  428  is activated at the same time the SEL signal is active, and selectively shorts the signal and reset level sample and hold capacitors  424 ,  426  together to reduce the fixed pattern noise generated by threshold voltage offsets in the p-channel column source followers. The signal and reset level of each pixel is read out, which allows for off-chip correlated double sampling (CDS) to reduce noise generated within each pixel 
     The crowbar  428  is then released, and the reset and sample values are respectively applied to the capacitors  424 ,  426 . Each of the sampled values that are applied to the capacitor effectively change the amount of charge on the capacitors. This change is measured. Since only the change is important in this circuit, the absolute threshold variations of the transistors are canceled out. This circuit and operation hence cancels the fixed pattern noise that would otherwise be generated by threshold voltage offsets in the p-channel column source followers. 
     Circuits to the right of dashed line LL, indicated as region  420 , are common to the entire chip. These circuits are readout transistor devices and are also preferably CMOS compatible. 
     FIG. 5, seen in conjunction with FIGS. 1-4 and also with FIG. 6, shows the schematic of the horizontal control logic. The horizontal control signals generated for the individual rows within sensor  5  are transfer gate TX i , reset RST i , and row select ROW i . The voltage level of the TX i  and RST i  signals can be set independently of the rest of the logic circuits. To transfer charge accumulated beneath the pinned photodiode  402 , the transfer gate  404  is clocked by TX i  to transfer the signal charge to the floating diffusion node  406 . The high and low levels for the transfer gate are set using the V − TX and V + TX inputs to the chip as shown in FIG.  5 . 
     In a similar fashion the reset transistor  410  is driven by signal RSTi. The high and low levels for the reset transistor  410  are set using V-RST and V + RST inputs to the chip. Since these gate thresholds can be adjusted, different effects and tolerances can be obtained. This adjustable gate threshold, for example, may make it possible to adjust for charge capacity and antiblooming control tolerances, or provide special effects in the acquired image. Buffer circuit  504  and level shifting circuit  506  perform functions similar to the equivalent circuits,  304  and  306 , previously discussed in FIG.  3 . 
     In addition, the reset level of the floating diffusion node  406  can be set using the input RSTLVL to the chip, which forms the value VDD that is used as the reset. 
     The frame reset signal F-RST is an inverted signal (active low) that when low switches on the reset transistors of the entire array, setting the floating diffusion node to RSTLVL, but does not empty the signal charge in the pinned photodiode. 
     FIG. 6 shows a potential energy diagram of a cross-section of the pixel region  400  with the pinned photodiode  402 , transfer gate  404 , and floating diffusion  406 . In addition, each pixel region  400  contains reset, source follower input, and row selection transistors which are not shown. Also shown is a potential energy diagram showing the collection of photo-generated electrons in the pinned photo diode region. 
     The layout of the pixel region  400 , as shown in FIG.  7  and viewed in conjunction with FIG. 6, has a pixel size of 40 μm×40. This pixel size is for the preferred embodiment disclosed, herein. It should be readily apparent to those skilled in the art that other pixel sizes and configurations may equally apply the concepts of the present invention. The pixel overlaps the poly2 reset signal line with the poly1 row selection line to maximize the optical fill factor. The L-shaped pinned photodiode region  402  is used to maximize the photoactive area. The resultant optical fill factor is approximately 30%. 
     Anti-blooming is achieved by setting the transfer gate  404  and reset transistor  410  to a low level of 2.5 V to act as a lateral anti-blooming drain. A buried channel transfer gate is used to allow for complete charge transfer from the photodiode with a transfer gate high level of 5 V. 
     The reset gate low level is set to 1.25 V so that charge levels beyond this point will bleed off into the charge sink  606  (as shown in FIG.  6 ), which is biased at VDD. Hence, this acts as a lateral antiblooming drain. A buried channel transfer gate  404  is used to allow for complete charge transfer from the pinned photodiode  402  with a transfer gate high level of 5 V. A threshold adjustment may be used to facilitate in charge transfer to the floating diffusion. 
     The array is preferably read out one row at a time. The transfer gate  404  transfers a row at a time. Each pinned photodiode  402 , in the row being transferred, transfers its stored charge to its respective floating diffusion  406 . The reset and signal level from each pixel in the selected row are loaded to sample and hold capacitors at the bottom of each column. The column selection transistors  300  provide that the data from each column is then read out serially as pixel signal out  610 . 
     The resultant voltage level timing diagram is shown in FIG.  8 . Preferably, all clocks run at TTL levels. The high voltage level of the transfer gate may need to be shifted to achieve complete transfer of signal charge from the pinned photodiode  402  to the floating diffusion node  406 . 
     Now referring to FIG. 8 in conjunction with FIG. 4, the operation proceeds as follows: 
     First, the reset transistor  410  is switched on at  800 , setting the potential of the floating diffusion node  406  to VDD; in this embodiment, approximately 3.5 V. 
     After the reset transistor  410  has completed its switching, the reset sample and hold transistor  430  is switched on at  802 , storing the reset level of each pixel on the associated reset level sample and hold capacitor bank  432 . 
     Time  804  represents the end of the photo integration period. Transfer gate  404  is pulsed to transfer the signal charge from the pinned photodiode  402  to the floating diffusion node  406 . 
     The signal sample and hold transistor  434  is switched on at  806  to store the signal level of each pixel on the signal level sample and hold capacitor bank  430 / 432 . 
     The column is then read out at  808  by switching on the clamping transistors  442 ,  450  and storing the signal sample and reset levels of that column across the AC coupling sampling and reset capacitors  444 ,  446 . 
     Next, the clamped reset voltage is turned off, and the “crowbar” switch  428  is turned on at  810 . The clamped reset voltage Vcl, is controlled by lowering the voltage CL that drives the clamping transistors  442  and  450 . When crowbar switch  428  is turned on, the inputs to the p-channel source-followers are shorted together. This averages the charge and also captures the offset in the p-channel source followers in the column being read out. 
     The final output signal is the signal level subtracted from the reset level. 
     Switching on the “crowbar” switch in the output circuitry suppresses the offset in the p-channel column source-follower. The clamped reset and AC coupling capacitors subtract out the offset from the p-channel source-follower and minimizes the fixed pattern noise contribution. 
     FIG. 9 shows a layer diagram illustrating the substance  900 , with photodiode area  902 . Two pixels,  910  and  920 , are shown. Pixel  910  is covered by a color filter layer  912  that passes only a single color of light. Pixel  920  is covered by a different color filter  922 . In this way adjacent pixels receive information indicative of the light content of different colors. Each pixel is preferably covered by microlens  930 , which refracts at least a portion of the incoming light to the photodiode area  902 . 
     The invention has been described with reference to a preferred embodiment; However, it will be appreciated that variations and modifications can be effected by a person of ordinary skill in the art without departing from the scope of the invention. 
     PARTS LIST: 
       5  sensor 
       10  pixel array 
       12  row decoder 
       14  column signal processing 
       16  column addressing decoder 
       22  individual row control circuits 
       24  individual column control 
       100   8 -input nand gate 
       110  nand gate input 
       111  nand gate input 
       112  nand gate input 
       113  nand gate input 
       114  nand gate input 
       115  nand gate input 
       116  nand gate input 
       117  nand gate input 
       120  diffusion 
       122  diffusion 
       300  column selection transistors 
       302  inactivity signal 
       304  buffer circuit 
       306  level shifting and gate 
       400  pixel region 
       402  pinned photodiode 
       404  transfer gate 
       405  column circuitry 
       406  floating diffusion 
       410  reset transistor 
       412  source follower 
       414  row decode transistor 
       420  common chip region 
       422  stacked capacitors (cs) 
       424  mos capacitor 
       426  polyl-poly 2  capacitor 
       428  crowbar switch(cb) 
       430  sample and hold reset transistor 
       432  reset capacitor bank 
       434  sample and hold transistor 
       442  clamping transistor 
       444  sample capacitance (cos) 
       446  rest capacitance (cor) 
       450  clamping transistor 
       504  buffer circuit 
       506  level shifting and gate circuit 
       606  charge sink 
       610  pixel signal out 
       800  switch on period 
       802  sample and hold switch on 
       804  end of the photo integration period 
       806  signal sample and hold transistor on 
       808  selection transistors on 
       810  crowbar switch on 
       900  substance 
       902  photodiode area 
       910  pixel 
       912  color filter layer 
       920  pixel 
       922  color filter layer 
       930  microlens 
     SEL global select 
     RSTLVL reset level 
     SEL  j  column select 
     SF source follower transistor 
     V+positive power supply 
     V−negative power supply