Abstract:
Methods and circuits for extracting a true mean of two signals are provided. A first amplifier input stage (e.g., an n-type stage) is operated when a mean of the two signals approaches an upper rail voltage. A second amplifier input stage (e.g., a p-type stage) is operated when the mean of the two signals approaches a lower rail voltage. A transitioning circuit controls how much each of the first and the second amplifier input stages contributes to an input of a high-gain amplifier output stage, when the mean of the two signal does not approach either of the rail voltages. An output of the high-gain amplifier output stage is fed back to both the first and second amplifier input stages via a feedback stage, which can be a matched buffer stage.

Description:
PRIORITY CLAIM 
     This application is a continuation of U.S. patent application Ser. No. 10/733,710, filed Dec. 11, 2003 now U.S. Pat. No. 6,867,643, which claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 60/463,070, filed Apr. 15, 2003, each of which are incorporated herein by reference, which is incorporated herein by reference. 
     FIELD OF THE INVENTION 
     The present invention relates to operational amplifiers, and more particularly to the use of an operational amplifier to extract the common mode voltage from two inputs. 
     BACKGROUND OF THE INVENTION 
     Transmission systems often use a twisted pair to carry signal information as a difference signal. In such systems, it is useful to generate a mean (i.e., common mode) of the voltages that can vary from rail-to-rail, with a difference signal that can vary independently, but is bounded. The impedance presented to the inputs should be high, e.g., greater than 1 MΩ. Additionally, the speed of response should be high, e.g., much greater than a 10 MHz bandwidth. 
     SUMMARY OF PRESENT INVENTION 
     Embodiments of the present invention relate to operational amplifiers that include rail-to-rail input stages, and more generally to rail-to-rail operational amplifiers. More specifically, embodiments of the present invention relate to rail-to-rail operational amplifiers that extract a true mean of two signals (e.g., of a differential signal). 
     In accordance with an embodiment, an amplifier circuit includes an n-type buffer input stage that receives the two signals and produces a first offset common mode output signal therefrom. An n-type amplifier input stage receives both the first offset common mode output signal and a first feedback signal, and produces a first differential error signal therefrom. The amplifier circuit also includes a p-type buffer input stage that receives the two signals and produces a second offset common mode signal therefrom. A p-type amplifier input stage receives both the second offset common mode output signal and a second feedback signal, and produces a second differential error signal therefrom. A differential input high-gain amplifier output stage receives the first and second differential error signals and produces a true common mode output signal that is substantially equal to the true mean of the two signals. A feedback stage receives the true common mode output signal and produces the first and second feedback signals therefrom, which are provided to the amplifier input stages. A transitioning stage controls how much the first differential error signal (from the n-type amplifier input stage) and the second differential signal (from the p-type amplifier input stage) contribute to the differential input of the high-gain amplifier output stage. 
     In accordance with an embodiment of the present invention, the first and second differential signals are summed together at the differential input of the high-gain amplifier input stage. The transitioning circuit controls how much the first differential error signal and the second differential error signal contribute to the differential input of the high-gain amplifier output stage by controlling how a drive current is split between the n-type amplifier input stage and the p-type amplifier input stage. For example, a first portion of the drive current, which is provided to the n-type amplifier input stage, effects a magnitude of the first differential error signal. Similarly, a second portion of the drive current, which is provided to the p-type amplifier input stage, effects a magnitude of the second differential error signal. 
     Further embodiments, and the features, aspects, and advantages of the present invention will become more apparent from the detailed description set forth below, the drawings and the claims. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         FIG. 1  shows an operational amplifier circuit that allows the input voltages to approach the upper rail voltage, but not the lower rail voltage. 
         FIG. 2A  shows an operational amplifier circuit, according to an embodiment of the present invention, that allows the input voltages to approach both the upper rail voltage and the lower rail voltage. 
         FIG. 2B  shows an embodiment of the present invention that is similar to the embodiment of  FIG. 2A , except CMOS transistors are used in place of bipolar transistors. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  shows a circuit  100  for an operational amplifier. The circuit  100  is shown as including an input buffer stage  102 , and amplifier input stage  104  and a high-gain rail-to-rail output stage  106 . The input buffer stage  102  is shown as including a pair of NPN transistors Q 1  and Q 2  that are used to accept inputs V 1  and V 2 , e.g., from a twisted pair cable (not shown). More specifically, a first input voltage V 1  is applied to the base of transistor Q 1 , and a second input voltage V 2  is applied to the base of transistor Q 2 . The collectors of transistors Q 1  and Q 2  are both connected to the upper (i.e., high) rail. The emitter of transistor Q 1  is connected through a pair of resistors (each labeled R) to the emitter of transistor Q 2 . The emitter of transistor Q 1  is also connected to a current source I 1 . The emitter of transistor Q 2  is also connected to another current source I 1 , which is matched with the other current sources I 1 . The currents sources I 1  and I provide biasing currents. 
     The input voltages V 1  and V 2  are each dropped by one Vbe (the voltage drop from the base to emitter) in transistors Q 1  and Q 2 . More specifically, the voltage at the emitter of transistor Q 1  is equal to V 1 −Vbe, and the voltage at the emitter of transistor Q 2  is equal to V 2 −Vbe. If transistors Q 1  and Q 2  have substantially similar characteristics (i.e., are matched), and the biasing current sources I 1  are matched, then the two emitter base voltage drops (Vbe) are matched (i.e., equal). A typical value for Vbe is approximately 0.75 to 0.80 Volts. Assuming the resistors R are matched, this results in the voltage at the midpoint  108  of the resistors R being equal to the average of V 1  and V 2 , less one emitter base voltage drop (Vbe). This is because the voltage at the emitter of transistor Q 1  is V 1 −Vbe, and the voltage at the emitter of transistor Q 2  is V 2 −Vbe. The offset average of these two voltages, produced at the midpoint between the two resistors R, is
 
(( V 1 −Vbe )+( V 2 −Vbe ))/2
 
=( V 1 +V 2)/2−2 Vbe /2
 
=( V 1 +V 2)/2 −Vbe. 
 
This voltage, also referred to herein as the offset common mode voltage, is applied to the base of transistor Q 3 , as shown in  FIG. 1 . It should also be noted that transistors Q 1  and Q 2  boost the impedance presented by averaging resistors R to the input terminals providing voltages V 1  and V 2 .
 
     Transistors Q 3  and Q 4  form the input stage  104  of a high-gain amplifier. The rest of the gain stage is represented by the amplifier  106 , which is a conventional high-gain rail-to-rail output stage, which is well known in the art. The collector of transistor Q 4  is coupled to the input of (and thereby provides an input to) the high-gain rail-to-rail output stage  106 . The output  110  of the high-gain rail-to-rail output stage  106  is fed back to the base of a transistor Q 5 . When in equilibrium, the base voltage of transistors Q 4  will be brought within a small error (i.e., difference) of the base voltage of transistor Q 3 , through the operation of the high-gain amplifier  106 . The small difference between the voltages at the bases of transistors Q 4  and Q 3  is amplified by the transistors Q 4  and Q 3 , with the amplified difference being provided at the collector of transistor Q 4  to the input of the high-gain amplifier  106 . 
     Ignoring for now the resistor (labeled R/ 2 ) between the base of transistor Q 4  and the emitter of transistor Q 5 , it can be appreciated the base of transistor Q 5  would be one voltage emitter drop (Vbe) greater than the base of transistor Q 4 , and thus substantially equal to (V 1 +V 2 )/2, which is the desired mean (i.e., true common mode) of signals V 1  and V 2 . 
     The emitters of transistors Q 3  and Q 4  are both connected to a current source I. The collectors of transistors Q 3  and Q 4  are each connected (optionally through load resistors) to the upper rail. These loads (which need not be resistors in actual implementation) are used to pass the output of stage  104  to stage  106 . The base of transistor Q 4  is connected through a resistor R/ 2  to the emitter of transistor Q 5 , as mentioned above. The collector of transistor Q 5  is connected to the high rail. The base of transistor Q 5  is connected to the output  110  of the high-gain rail-to-rail output stage  106 . Transistor Q 5  and resistor R/ 2  of the feedback circuit are preferably matched to the input receiving transistors Q 1  and Q 2 , and the resistors R, respectively, to ensure that the feedback circuit will add the Vbe drop (and any voltage dropped across the resistor R due to the base current in transistor Q 3 ) onto the voltage at the base of transistor Q 4 , to thereby recover a true average (i.e., true common mode voltage). 
     Even though bipolar transistors are shown in  FIG. 1 , this circuit can alternatively include CMOS transistors. However, when using bipolar transistors (as shown) there are currents that will flow out of the bases of transistors Q 3  and Q 4 . To effectively compensate for the base current that flows out of transistor Q 3  (and into the two resistors R in the buffer input stage  102 ), the resistor R/ 2  is included between the base of transistor Q 4  and the emitter of transistor Q 5 , as explained above. The resistor R/ 2  is not necessary in a CMOS equivalent circuit. It is also noted that a design parameter of circuit  100  is that the maximum differential signal (i.e., |V 1 −V 2 |) is I 1 *2*R. 
     Circuit  100  works very well when the input voltages V 1  and V 2  are positive. More specifically, the output  110  will provide the true average (i.e., true common mode) of inputs V 1  and V 2 , even if V 1  and/or V 2  are equal to the upper rail voltage. This is because transistors Q 1  and Q 2  reduce the inputs V 1  and V 2  by Vbe, causing the maximum inputs voltages at the bases of transistors Q 3  and Q 4  to be the upper rail voltage less one Vbe, thus allowing for the signal swing required for proper transistor operation. However, when V 1  and/or V 2  are taken down close to the lower rail voltage, then there is no longer any room for circuit  100  to operate properly. More specifically, as the voltages on the emitters of transistors Q 1  and Q 2  come down, there is eventually no voltage left to allow the current sources I 1  to function, nor is there any voltage left for the current source I (providing a current to the emitters of transistors Q 3  and Q 4 ) to function. In other words, when V 1  and/or V 2  is close to the lower rail voltage, the current source I and/or the current sources I 1  enter saturation. So, while circuit  100  will provide full common mode extraction for the upper half (e.g., positive half) of the input range, circuit  100  only works properly when remaining about 2 or 3 Volts above the lower rail voltage. 
     Based on the above description, it can be appreciated that circuit  100  includes a rail-to-rail amplifier output stage  106 , but not a rail-to-rail amplifier input stage. In accordance with embodiments of the present invention, an amplifier input stage is provided that can operate from rail-to-rail. 
     Referring now to  FIG. 2A , a circuit  200 A of an operational amplifier, according to an embodiment of the present invention, is shown. The circuit  200 A is shown as including an n-type input buffer stage  202   n , a p-type input buffer stage  202   p , an n-type amplifier input stage  204   n , a p-type amplifier input stage  204   p , a current mirror  212 , and a rail-to-rail high-gain output stage  206 . More specifically, output stage  206  can be a conventional high-gain, differential input, trans-impedance amplifier, which receives a differential current input and provides a voltage output. Circuit  200 A is also shown as including folded cascode transistors Qp 6 , Qn 6 , Qp 7 , Qn 7  and a transitioning transistor Qref, each of which receives a biasing voltage (Vbp, Vbn or Vref). Current sources I, I 1 , I 2  and I 3  provide biasing currents. The transitioning transistor Qref is part of a transitioning stage. Circuit  200 A also includes a matched feedback buffer stage  214 . 
     The circuit  200 A is designed such that the n-type amplifier input stage  204   n  operates and provides the differential input to the high-gain output stage  206  while (V 1 +V 2 )/2 is near the high rail voltage, the p-type amplifier input stage  204   p  operates and provides the differential input to the high-gain output stage  206  while the (V 1 +V 2 )/2 is near the lower rail voltage, and both n-type and p-type input amplifier stages  204   n  and  204   p  operate and contribute to the differential input to the high-gain output stage  206  when (V 1 +V 2 )/2 is generally in the middle of the upper and lower rail voltages. The voltage Vref specifies when the n-type amplifier input stage  204   n  and the p-type amplifier input stage  204   p  begin to swap roles. Thus, Vref can be set at the mid point (i.e., mean) of the upper and lower rails (also referred to as a mid-rail voltage). However, because the n-type amplifier input stage  204   n  generally operates better than the p-type amplifier input stage  204   p , Vref can be set below the mid-rail (so long as it&#39;s set about 2 or 3 Volts above the low rail), in accordance with an embodiment of the present invention, so that the n-type amplifier input stage  204   n  operates over a wider range than the p-type amplifier input stage  204   p.    
     Each input to the n-type input buffer stage  202   n  is tied to the corresponding input to the p-type input buffer stage  202   p . More specifically, in accordance with an embodiment of the present invention, the bases of transistors Qn 1  and Qp 1  are connected together, as are the bases of transistors Qn 2  and Qp 2 . 
     The collector of transistor Qn 4  is shown as being connected to a first differential input (e.g., the positive input) of the high-gain amplifier output stage  206  through folded cascode transistor Qp 6 . Similarly, the collector of transistor Qp 4  is shown as being connected to the first differential input of the high-gain amplifier output stage  206  through folded cascode transistor Qn 6 . The collector of transistor Qn 3  is shown as being connected to a second differential input (e.g., the negative input) of the high-gain amplifier output stage  206  through folded cascode transistor Qp 7 . Similarly, the collector of transistor Qp 3  is shown as being connected to the second differential input of the high-gain amplifier output stage  206  through folded cascode transistor Qn 7 . Through this arrangement, the collectors of transistors Qn 4  and Qn 3  provide a first differential error signal to the differential input of the high-gain amplifier output stage  206 , and the collectors of transistors Qp 4  and Qp 3  provide a further differential input signal to the differential input of the high-gain amplifier output stage  206 . These differential error signals are added at the differential input of the high-gain amplifier output stage  206 . A true common mode output signal (substantially equal to the true mean of input voltage signals V 1  and V 2 ) is then provided at the output  210  of the high-gain amplifier output stage  206 . Feedback stage  214 , which is preferably a matched buffer stage, receives the common mode output signal and provides feedback signals to the n-type amplifier input stage  204   n  and the p-type amplifier input stage  204   p.    
     For reasons similar to those discussed above with reference to  FIG. 1  (and discussed in more detail below), when the n-type amplifier input stage  204   n  is fully operating, the voltage at the output  210  of the high-gain amplifier stage  206  (and also, at the base of transistor Qn 5 ) will be substantially equal to the true mean (i.e., true average) of inputs V 1  and V 2 . In other words, the base of transistor Qn 5  will equal the common mode voltage for inputs V 1  and V 2 . Similarly, when the p-type amplifier input stage  204   p  is fully operating, the output  210  of the high-gain amplifier output stage  206  (and also, at the base of transistor Qp 5 ) will equal the common mode voltage for inputs V 1  and V 2 . When the n-type amplifier input stage  204   n  and the p-type amplifier input stage  204   p  are both operating, the currents from the collectors of transistors Qn 4  and Qp 4  are summed (after passing thorough transistors Qp 6  and Qn 6 , respectively) at the first differential input of the high-gain amplifier output stage  206 , and the currents from the collectors of transistors Qn 3  and Qp 3  are summed (after passing thorough transistors Qp 7  and Qn 7 , respectively) at the other differential input of the high-gain amplifier output stage  206 , causing the output of the output stage  206  to be the true common mode voltage. Together, the n-type and p-type amplifier input stages  204   n  and  204   p  provide a rail-to-rail input stage for the operation amplifier circuit  200 A. This is explained in more detail below. The output  210  of the high-gain amplifier output stage  206  is then fed back to both the n-type buffer input stage  204   n  and the p-type buffer input stage  204   p , via the matched buffer feedback stage  214 . 
     When the voltages at the bases of transistors Qn 3  and Qn 4  are high enough above Vref, the emitters of transistors Qn 3  and Qn 4  pull up on the emitter of transistor Qref, turning off transistor Qref. This causes all biasing current I (from the current source I) to pass into the n-type amplifier input-stage  204   n , powering stage  204   n . Meanwhile, when transistor Qref is turned off, no current flows through the current mirror  212 , and thus no current is provided to power the transistors Qp 3  and Qp 4  of the p-type amplifier input stage  204   p . In other words, the p-type amplifier input stage  204   p  is cut-off. 
     As the voltages at the bases of transistors Qn 3  and Qn 4  approach Vref, some of the current from the current source I is diverted up through transistor Qref. This reduces the current to the n-type amplifier input stage  204   n , and introduces some current that gets mirrored around by current mirror  212  into transistors Qp 3  and Qp 4  of p-type amplifier input stage  204   p . The closer the voltages at the bases of transistors Qn 3  and Qn 4  are to Vref, the more evenly the current is divided between the n-type amplifier input stage  204   n  and the p-type amplifier input stage  204   p . Then, if the voltages at the bases of transistors Qn 3  and Qn 4  fall below Vref, more current will be provided to the p-type amplifier input stage  204   p  than to the n-type amplifier input stage  204   n , causing the p-type amplifier input stage  204   p  to contribute more to the differential input to the high-gain rail-to-rail output stage  206 . If the voltages at the bases of transistors Qn 3  and Qn 4  fall low enough below Vref, then all the current from the current source I will be provided to the p-type amplifier input stage  204   p  (cutting off the n-type amplifier input stage  204   n ), causing only the p-type amplifier input stage  204   p  to contribute to the differential input to the high-gain rail-to-rail output stage  206 . The above described transition between the n-type and p-type stages can be referred to as a soft transition. The above described circuit provides a soft transition that is both smooth and continuous. More generally, the above described circuit provides for smooth and continuous rail-to-rail operation. 
     Circuit  200 A has been described as including bipolar type transistors. One of ordinary skill in the art will appreciate that other types of transistors, such as, but not limited to complimentary-metal-oxide-semiconductor (CMOS) type transistors (i.e., NMOS and PMOS), can alternatively be used. For example, NMOS transistors can be used for n-type stages, and PMOS transistors can be used for p-type stages. Circuit  200 B in  FIG. 2B  illustrates an embodiment of the present invention that uses CMOS transistors in place of bipolar transistors. As shown in  FIG. 2B , the resistors in current mirror  212  are not necessary, but can be included if desired. For best performance, resistors R are included in circuit  200 B. Resistors R/ 2  are not necessary when using CMOS transistors. The operation of circuit  200 B is essentially equivalent to the operation of circuit  200 A, and therefore need not be described in additional detail. 
     It is noted that there may be some uses where resistors R can be removed, and the CMOS transistors are appropriately sized. In such a case, the current sources I 1  in the n-type input buffer stage  202   n  would be merged to provide one current source providing a current value of twice I 1  (i.e., 2×I 1 ). The current sources I 1  in the p-type input buffer stage  202   p  would be similarly merged. 
     The forgoing description is of the preferred embodiments of the present invention. These embodiments have been provided for the purposes of illustration and description, but are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations will be apparent to a practitioner skilled in the art. Embodiments were chosen and described in order to best describe the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention. Slight modifications and variations are believed to be within the spirit and scope of the present invention. It is intended that the scope of the invention be defined by the following claims and their equivalents.