Abstract:
A multiplex circuit includes: a plurality of input transistors that correspondingly receive a plurality of input signals of different switching points, the switching points beginning with edges of symbol periods of the plurality of input signals; one of a common base transistor that is connected to a collector of the input transistor, and a common gate transistor that is connected to a drain of the input transistor; and an output end that is connected to one of the collector of the common base transistor and the drain of the common gate transistor, and to which a signal that is obtained by combining the plurality of input signals is output.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2012-269493, filed on Dec. 10, 2012, the entire contents of which are incorporated herein by reference. 
       FIELD 
       [0002]    The embodiments discussed herein are related to a multiplex circuit and a drive unit using the multiplex circuit, and for example, related to a drive unit that generates a drive signal that drives a light-emitting element by using a multiplex circuit. 
       BACKGROUND 
       [0003]    With a high transmission speed and a large capacity in a network, a method of transmitting and receiving a signal using an optical transmission path has been spread in place of existing electrical wiring. 
         [0004]    In order to perform optical transmission at a high speed, a light-emitting element such as a vertical cavity surface emitting laser (VCSEL) is driven at a high speed. A high-frequency signal is attenuated at a transmission path and the waveform is deteriorated, so that a pre-emphasis method of compensating for the signal on the transmission side beforehand has been used. 
         [0005]    As a pre-emphasis type drive circuit, there has been proposed a circuit that combines a drive signal and the delayed signal and generates a drive waveform of the VCSEL (For example, see  FIG. 11  of Japanese Laid-open Patent Publication No. 2012-080061). A pre-emphasis generation circuit that is used in such a drive circuit generates a pre-emphasis waveform that directly modulates the VCSEL at a high speed by using analog delay (variable delay). The generated pre-emphasis waveforms (a waveform that corresponds to an input drive signal and a waveform that corresponds to the delayed signal) are combined and a VCSEL drive signal is output. In a multiplex circuit, the collector of a transistor to which a drive signal is input and the collector of a transistor to which the delayed signal is input are connected to the common current source, and a synthetic drive signal is obtained from a common output end. 
         [0006]    In the above-described multiplex circuit, there is a problem of variation in jitter of input waveforms. The jitter variation is attributed to the occurrence of a crosstalk between inputs of the multiplex circuit and variation in collector potentials because the collector ends of the transistors are connected to the common current source. This is a problem specific to a drive circuit that processes a high-speed signal. 
       SUMMARY 
       [0007]    According to an aspect of the embodiment, a multiplex circuit includes: a plurality of input transistors that correspondingly receive a plurality of input signals of different switching points, the switching points beginning with edges of symbol periods of the plurality of input signals; one of a common base transistor that is connected to a collector of the input transistor, and a common gate transistor that is connected to a drain of the input transistor; and an output end that is connected to one of the collector of the common base transistor and the drain of the common gate transistor, and to which a signal that is obtained by combining the plurality of input signals is output. 
         [0008]    The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
         [0009]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0010]      FIG. 1  is a diagram illustrating a configuration of a light-emitting element drive circuit using delay synthesis; 
           [0011]      FIGS. 2A and 2B  are diagrams illustrating generation of a pre-emphasis waveform that is used in the light-emitting element drive circuit; 
           [0012]      FIGS. 3A and 3B  are diagrams illustrating a crosstalk between taps and jitter when analog delay is performed; 
           [0013]      FIG. 4  is a diagram illustrating definition of a crosstalk between inputs; 
           [0014]      FIG. 5  is a diagram illustrating a configuration example of a multiplex circuit according to a first embodiment; 
           [0015]      FIGS. 6A and 6B  are diagrams illustrating a current-voltage characteristic of a common base transistor that is used in the multiplex circuit of  FIG. 5 ; 
           [0016]      FIGS. 7A and 7B  are diagrams illustrating a crosstalk reduction effect when the multiplex circuit of  FIG. 5  is used; 
           [0017]      FIG. 8  is a diagram illustrating a configuration example of a drive circuit that employs the multiplex circuit of  FIG. 5 ; 
           [0018]      FIG. 9  is a diagram illustrating a configuration example of a drive circuit according to a second embodiment; 
           [0019]      FIGS. 10A and 10B  are diagrams illustrating a current-voltage characteristic of a common base transistor that is used in the drive circuit according to the second embodiment; 
           [0020]      FIG. 11  is a diagram illustrating a configuration example of a drive circuit according to a third embodiment; and 
           [0021]      FIG. 12  is a diagram illustrating a configuration example of a drive circuit according to a fourth embodiment. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0022]    First, the technical problem in the drive circuit in the related art, which is found by the inventor is described. 
         [0023]      FIGS. 1 ,  2 A, and  2 B are diagrams illustrating a crosstalk between input signals of a multiplex circuit. For an input drive signal, a pre-emphasis generation circuit  1120  of a drive unit  1000  assigns a delay time t 1  at a delay circuit  1121 , assigns a delay time t 2  at a delay circuit  1122 , and outputs three types of differential signals. A first differential signal is input to a first differential amplifier unit DA 1  of a multiplex circuit  1130 , a second differential signal is input to a second differential amplifier unit DA 2  of the multiplex circuit  1130 , a third differential signal is input to a third differential amplifier unit DA 3  of the multiplex circuit  1130 , and these signals are combined with each other. 
         [0024]    As illustrated in  FIG. 2A , in a general pre-emphasis generation circuit that is used for loss correction and the like of an electrical signal, delay τ is set to an integer multiple of a phase (1 bit time). Therefore, all of input without delay (in 1 ), delay input (in 2 ), and output (out) are switched at the same point in time. 
         [0025]    In addition, as illustrated in  FIG. 2B , in a VCSEL characteristic, a signal is not sufficiently compensated by general integer bit delay, so that analogue delay is used in this case. For example, when the delay τ is set to a decimal multiple of a phase, a switching point of the signal is different between the input without delay (in 1 ) and the delay input (in 2 ). 
         [0026]      FIGS. 3A and 3B  illustrate monitor waveforms of voltage signals Vin 1 , Vin 2 , and Vin 3  that are respectively applied to input transistors Q 1 , Q 2 , and Q 3  of the multiplex circuit  1130  when the delay times t 1  and t 2  are changed not in an integer-bit fashion but in an analog fashion by the drive circuit in  FIG. 1 .  FIG. 3A  illustrates a case in which the delay time t 1  is set at 14 ps, and the delay time t 2  is set at 33 ps, and  FIG. 3B  illustrates a case in which the delay time t 1  is set at 7 ps, and the delay time t 2  is set at 15 ps. 
         [0027]    Ideally, each of the waveforms is not to be changed even when the delay times t 1  and t 2  are changed. However, practically, the appearance of jitter is change. It is conceivable that this is why signals the switching points of which are shifted at the taps are input to the multiplex circuit  1130  (“in 1 ”, “in 2 ”, and “in 3 ”), and a crosstalk occurs between the inputs. 
         [0028]      FIG. 4  is a diagram illustrating definition of a crosstalk between inputs. In differential amplifier units DA 1 , DA 2 , and DA 3  of the multiplex circuit  1130 , the potential of the collector end of base-to-collector parasitic capacitance C BC  in each of input transistors Q 1   p,  Q 1   n,  Q 2   p,  Q 2   n,  Q 3   p,  and Q 3   n  is shaken by a signal of another tap. As described above, mutual influence of high-speed signals through the base-to-collector parasitic capacitance C BC  of the input transistor Q is referred to as “crosstalk between inputs”. 
         [0029]    For example, when there is no signal at “in 1 ” and “in 3 ”, and a signal is input at “in 2 ” (for convenience, a positive-phase signal and a negative-phase signal are collectively described), a current signal that flows through the transistor Q 2  is converted into a voltage signal by a resistor RL, and the potential of the output end out is shaken. Between the transistors Q 1 , Q 2 , and Q 3 , the collector end (drain end in a case of a field-effect transistor (FET)) and the output end are shared, so that a high-speed component of the voltage signal of the output end out is leaked into “in 1 ” and “in 3 ” through the parasitic capacitance C BC . As a result, current that flows through the transistors Q 1  and Q 3  is not to be changed, however the potential is shaken by the signal that is input to “in 2 ” undesirably. 
         [0030]    In the case of general integer bit delay (see  FIG. 2A ), switching points of signals of the respective tap are matched with each other, so that the impact on the final synthetic waveform is small even when a crosstalk between inputs occurs. However, when signals of switching points that are different due to analog delay are combined as in the light-emitting element drive circuit, the signals appear as variation in jitter as illustrated in  FIGS. 3A and 3B , depending on a delay amount. 
         [0031]    Therefore, in the embodiments, a configuration is proposed in which the collector (drain) potential of the input transistor is stabilized, that is, a crosstalk between the taps may be avoided without the impact from another input. For example, a common base transistor is arranged between the output end and the collector end of each of the input transistors Q 1  to Q 3  of the taps to which a drive signal and the delayed signal are input to suppress variation in collector potentials of the input transistors. When an FET is used, a common gate transistor is arranged between the output end and the drain end of each of the input transistors T 1  to T 3  to suppress variation in drain potentials of the input transistors. 
         [0032]    Specific configuration examples of the embodiments are described below with reference to accompanying drawings. 
         [0033]      FIG. 5  is a diagram illustrating a configuration example of a multiplex circuit  30  according to a first embodiment. The multiplex circuit  30  includes a cascode stage  70  that is inserted between the output ends out/outx and the collector end of input transistors Q 1   p,  Q 1   n,  Q 2   p,  Q 2   n,  Q 3   p,  and Q 3   n  (hereinafter collectively referred to as “input transistor Q” or “input transistors Q 1 , Q 2 , and Q 3 ”). In the cascode stage  70 , common base transistors Qc 1   p,  Qc 1   n,  Qc 2   p,  Qc 2   n,  Qc 3   p,  and Qc 3   n  (hereinafter collectively referred to as “common base transistor Qc”) are respectively connected to the corresponding input transistors Q in series. The bases of common base transistors Qc are connected to a potential Vb in common. The potential Vb is potential that is desired to pass the same amount of current through each of the common base transistors Qc when current flows through each of the input transistors Q. 
         [0034]    By arranging the common base transistor Qc between the collector end of the input transistor Q and the output end, variation in potentials Vc of the collector ends of the input transistors may be suppressed. 
         [0035]    The multiplex circuit  30  includes a first differential amplifier unit  40  that performs differential amplification on a drive signal, a second differential amplifier unit  50  that performs differential amplification on the first delayed signal, and a third differential amplifier unit  60  that performs differential amplification on the second delayed signal. 
         [0036]    From a pre-emphasis generation circuit that is described later, a positive-phase signal of a drive signal is input to the input transistor Q 1   p  of the first differential amplifier unit  40  (in 1   p ), and a negative-phase signal of the drive signal is input to the input transistor Q 1   n  of the first differential amplifier unit  40  (in 1   n ). The emitter of the input transistor Q 1   p  and the emitter of the input transistor Q 1   n  are connected to a current source  41 . The other end of the current source  41  is grounded. The collector of the input transistor Q 1   p  is connected to the emitter of the cascode transistor (common base transistor) Qc 1   p,  and the collector of the input transistor Q 1   n  is connected to the emitter of the cascode transistor (common base transistor) Qc 1   p.  The collector of the common base transistor Qc 1   p  is connected to a resistor RLp and the output end out. The collector of the common base transistor Qc 1   n  is connected to a resistor RLn and the output end outx. 
         [0037]    A positive-phase signal of the first delayed signal that is obtained by delaying the drive signal by a time t 1  is input to the input transistor Q 2   p  of the second differential amplifier unit  50  (in 2   p ), and a negative-phase signal of the first delayed signal is input to the input transistor Q 2n  of the second differential amplifier unit  50  (in 2   n ). The emitter of the input transistor Q 2   p  and the emitter of the input transistor Q 2   n  are connected to a current source  51 . The other end of the current source  51  is grounded. The collector of the input transistor Q 2   p  is connected to the emitter of the cascode transistor (common base transistor) Qc 2 , and the collector of the input transistor Q 2   n  is connected to the emitter of the cascode transistor (common base transistor) Qc 2   p.  The collector of the common base transistor Qc 2   p  is connected to the resistor RLp and the output end out. The collector of the common base transistor Qc 2   n  is connected to the resistor RLn and the output end outx. 
         [0038]    A positive-phase signal of the second delayed signal that is obtained by delaying the drive signal by a time t 2  is input to the input transistor Q 3   p  of the third differential amplifier unit  60  (in 3   p ), and a negative-phase signal of the second delayed signal is input to the input transistor Q 3   n  of the third differential amplifier unit  60  (in 3   n ). The emitter of the input transistor Q 3   p  and the emitter of the input transistor Q 3   n  are connected to a current source  61 . The other end of the current source  61  is grounded. The collector of the input transistor Q 3   p  is connected to the emitter of the cascode transistor (common base transistor) Qc 3   p,  and the collector of the input transistor Q 3   n  is connected to the emitter of the cascode transistor (common base transistor) Qc 3   p.  The collector of the common base transistor Qc 3   p  is connected to the resistor RLp and the output end out. The collector of the common base transistor Qc 2   n  is connected to the resistor RLn and the output end outx. 
         [0039]    When a base-emitter potential difference of the common base transistor Qc is represented as “V BE ”, a collector potential Vc of the input transistor is represented by “Vc=Vb−V BE ”. “Vb” is invariable, and base-emitter voltage V BE  of each of the common base transistor Qc is also substantially invariable, so that the collector potential Vc of the input transistor is stabilized. 
         [0040]      FIGS. 6A and 6B  are diagrams illustrating a current-voltage characteristic of the common base transistor Qc that is used in  FIG. 5 , and a relationship between current I CE  and voltage V CE  in the common base transistor Qc. The horizontal axis indicates the collector-emitter voltage V CE  of the transistor Qc, and the vertical axis indicates the collector-emitter current I CE  of the transistor Qc. With an increase in the voltage V CE  due to the early effect, the current I CE  slightly increases without hard saturation. Therefore, when the potential of the output end (out/outx) of the multiplex circuit  30 , that is, the collector potential of the common base transistor (cascode transistor) Qc is changed, the current that flows through the common base transistor Qc is slightly changed. When the current “I CE ” is slightly changed in accordance with the transistor characteristic of  FIG. 6 , the collector potential Vc of the input transistor Q is slightly shaken, so that a crosstalk between inputs is not removed completely. However, the crosstalk is sufficiently suppressed as compared with the circuit configuration in the related art. 
         [0041]      FIGS. 7A and 7B  are diagrams illustrating jitter suppression effect of the circuit of  FIG. 5 .  FIG. 7A  illustrates a case in which the delay time t 1  is set at 14 ps, and the delay time t 2  is set at 33 ps similar to  FIG. 3A , and  FIG. 7B  illustrates a case in which the delay time t 1  is set at 7 ps, and the delay time t 2  is set at 15 ps similar to  FIG. 3B . As compared with  FIGS. 3A and 3B , variation in jitter is suppressed in all input waveforms Vin 1 , Vin 2 , and Vin 3  of the input transistors Q 1 , Q 2 , and Q 3  of the multiplex circuit  30  even when the delay time is changed. 
         [0042]      FIG. 8  is a diagram illustrating a configuration example of a drive unit  10 A in which a multiplex circuit  30 A that is similar to the multiplex circuit  30  in  FIG. 5  is used. The drive unit  10 A includes a pre-emphasis generation circuit  20 , the multiplex circuit  30 A, and a dummy load  80 . One output (positive-phase signal) of the multiplex circuit  30 A is connected to a VCSEL through an output end out. The other output (negative-phase signal) is connected to the dummy load  80 . 
         [0043]    A cascode stage  70 A is inserted between an output end and the collectors of input transistors Q of the multiplex circuit  30 A. The collectors of common base transistors Qc 1   p,  Qc 2   p,  and Qc 3   p  of the cascode stage  70 A are connected to the output end out in common, and connected to a bias current source  91  through a resistor RLp and an inductor L 1   p.  The collectors of common base transistors Qc 1   n,  Qc 2   n,  and Qc 3   n  are connected to the dummy load  80  in common, and connected to a bias current source  93  through a resistor RLn and an inductor L 1   n.    
         [0044]    A resistor R 4  is connected to a node between the resistor RLp and the inductor L 1   p,  a resistor R 3  is connected to a node between the resistor RLn and the inductor L 1   n,  and the resistor R 3  and the resistor R 4  are connected to each other in series. A node between the resistors R 3  and R 4  is connected to a bias current source  92 . The bias current source  92  changes bias current and controls current that flows through the VCSEL and the dummy load. The dummy load  80  has a characteristic that is similar to that of the VCSEL, and a connection point between the resistors R 3  and R 4  may be regarded as a virtual ground point, so that, by using the resistors R 3  and R 4 , and the resistors RLn and RLp, output impedance of the drive unit  10 A is matched with input impedance of the VCSEL and input impedance of the dummy load  80 . 
         [0045]    The pre-emphasis generation circuit  20  includes a first delay circuit  21 , a second delay circuit  22 , a first amplifier  23 , a second amplifier  24 , and a third amplifier  25 . The first delay circuit  21  delays an input drive signal by “t 1 ” and outputs the first delayed signal. The second delay circuit  22  further delays the output first delay circuit  21  and outputs the second delayed signal that includes the delay amount t 2 . 
         [0046]    The first amplifier  23  generates differential signals on the basis of the input drive signal and inputs differential signals in 1   p  and in 1   n  to the input transistors Q 1   p  and Q 1   n  of the first differential amplifier unit  40 A of the multiplex circuit  30 A, respectively. The second amplifier  24  generates differential signals on the basis of the first delayed signal and inputs differential signals in 2   p  and in 2   n  to the input transistors Q 2   p  and Q 2   n  of the second differential amplifier unit  50 A, respectively. The third amplifier  25  generates differential signals on the basis of the second delayed signal and inputs differential signals in 3   p  and in 3   n  to the input transistors Q 3   p  and Q 3   n  of the third differential amplifier unit  60 A, respectively. 
         [0047]    When the signals to which the delay differences are given in the pre-emphasis generation circuit  20  are combined in the multiplex circuit  30 A, output of a VCSEL drive signal is performed in a state in which the rise and fall of the drive signal are corrected (emphasized or suppressed) beforehand. 
         [0048]    In the drive unit  10 A, by arranging the common base transistor between the output end and the collector of the input transistor Q of the multiplex circuit  30 A, variation in collector potentials of the input transistors Q is reduced. 
         [0049]      FIG. 9  is a diagram illustrating a configuration example of a drive unit  10 B according to a second embodiment. The drive unit  10 B includes a multiplex circuit  30 B. The illustration of a pre-emphasis generation circuit  20  that generates a differential input signal is omitted from the multiplex circuit  30 B, however the circuit that is similar to the pre-emphasis generation circuit  20  in  FIG. 8  is connected to the multiplex circuit  30 B. 
         [0050]    In the multiplex circuit  30 B according to the second embodiment, a cascode stage  70 B that is used in common is arranged between the collector ends and the output ends of input transistors Q 1 , Q 2 , and Q 3 . 
         [0051]    The collectors of the input transistors Q 1   p,  Q 2   p,  and Q 3   p  are connected to the emitter of a common base transistor Qcp in common. The collectors of the input transistors Q 1   n,  Q 2   n,  and Q 3   n  are connected to the emitter of the common base transistor Qcn in common. 
         [0052]    The emitter of the common base transistor (cascode transistor) Qc is shared among the plurality of taps, so that the sizes of the common base transistors Qcp and Qcn that are connected to the output ends may be reduced. The parasitic capacitance when viewed from the output end becomes small, thereby being advantageous to a high-speed operation. 
         [0053]      FIG. 10A  is a diagram illustrating a characteristic of the common base transistor Qc in  FIG. 9 . In  FIG. 10B , the horizontal axis indicates base-emitter voltage V BE  of the common base transistor Qc, and the vertical axis indicates collector-emitter current I CE  of the common base transistor Qc. When a signal is input to the input end of the input transistor Q, a combined current signal I CE  flows though the common base transistor Qc. A change amount ΔV BE  of V BE  is negligibly small as compared with a change amount ΔI CE  of I CE , so that variation in potentials of common collector ends of the input transistors Q is small even when a current signal flows through the common base transistor Qc. 
         [0054]      FIG. 11  is a diagram illustrating a configuration of a drive unit  10 C according to a third embodiment. The drive unit  10 C includes a multiplex circuit  30 C. The illustration of a pre-emphasis generation circuit  20  that generates a differential input signal is omitted from to the multiplex circuit  30 C, however the circuit that is similar to the pre-emphasis generation circuit  20  in  FIG. 8  is connected to the multiplex circuit  30 C. 
         [0055]    The multiplex circuit  30 C according to the third embodiment uses an FET instead of a bipolar transistor. The multiplex circuit  30 C includes a first differential amplifier unit  40 C, a second differential amplifier unit  50 C, and a third differential amplifier unit  60 C. A differential signal of an input drive signal is input to the first differential amplifier unit  40 C (in 1   p  and in 1   n ). A differential signal of the first delayed signal is input to the second differential amplifier unit  50 C (in 2   p  and in 2   n ). A differential signal of the second delayed signal is input to the third differential amplifier unit  60 C (in 3   p  and in 3   n ). 
         [0056]    The multiplex circuit  30 C includes a cascode stage  70 C that is inserted between the output ends out/outx and the collector ends of input transistors T 1   n,  T 1   p,  T 1   n,  T 2   p,  T 2   n,  T 3   p,  and T 3   n  (hereinafter collectively referred to as “input transistor T” or “input transistors T 1 , T 2 , and T 3 ”). In the cascode stage  70 C, common gate transistors Tc 1   p,  Tc 1   n,  Tc 2   p,  Tc 2   n,  Tc 3   p,  and Tc 3   n  (hereinafter collectively referred to as “common gate transistor Tc”) are respectively connected to the corresponding input transistors T in series. The gates of the common gate transistors Tc are connected to a potential Vg in common. The potential Vg is potential that is desired to pass the same amount of current through the common gate transistors Tc when current flows through the input transistors T. 
         [0057]    By connecting the common gate transistor Tc between the drain of the input transistor Q and the output end, variation in potentials V D  of the drain ends of the input transistors is suppressed. 
         [0058]    When gate-to-source threshold voltage of the common gate transistor Tc is represented as Vth, the drain potential V D  of the input transistor may be represented by “V D =Vg−Vth”. “V D ” is invariable, and the gate-to-source voltage Vth of each of the common gate transistors Qc is also substantially invariable, so that the drain potential V D  of the input transistor is stabilized. 
         [0059]      FIG. 12  is a diagram illustrating a configuration of a drive unit  10 D according to a fourth embodiment. The drive unit  10 D includes a multiplex circuit  30 D. The illustration of a pre-emphasis generation circuit  20  that generates a differential input signal is omitted from to the multiplex circuit  30 D, however the circuit that is similar to the pre-emphasis generation circuit  20  in  FIG. 8  is connected to the multiplex circuit  30 D. The drive unit  10 D is an emitter follower type output drive unit. 
         [0060]    The collectors of input transistors Q 1   p,  Q 2   p,  and Q 3   p  are respectively connected to the emitters of the corresponding common base transistors Qc 1   p,  Qc 2   p,  and Qc 3   p.  The collectors of the common base transistors Qc 1   p,  Qc 2   p,  and Qc 3   p  are connected to one end side of a resistor RLP, and connected to the base of a transistor Q 4  in common. The other end of the resistor RLP is connected to a current source  82  and the collector of the transistor Q 4 . 
         [0061]    The collectors of input transistors Q 1   n,  Q 2   n,  and Q 3   n  are respectively connected to the emitters of the corresponding common base transistors Qc 1   n,  Qc 2   n,  and Qc 3   n.  The collectors of common base transistors Qc 1   n,  Qc 2   n,  and Qc 3   n  are connected to one end side of a resistor RLn. The other end of the resistor RLn is connected to the current source  82  and the collector of the transistor Q 4 . 
         [0062]    The collector of the transistor Q 4  is connected to a reference potential Vcc through a capacity  81 . When a synthetic signal of outputs of the input transistors Q 1  to Q 3  is input to the base of the transistor Q 4 , a signal that reflects directly the amplitude of the base is output from the emitter of the transistor Q 4 . As described above, the transistor Q 4  functions as an emitter follower. The emitter output of the transistor Q 4  drives the VCSEL that is connected to the output end out. 
         [0063]    Such a configuration does not desire a dummy load, so that redundant current (current that flows through the dummy load) does not occur. 
         [0064]    The capacity of the current source  82  is not seen from the output end out, thereby being advantageous to the speedup. In the configuration in  FIG. 8 , the bias current source  91  is connected to the output end out through the resistor RL and the inductor L 1 . The bias current source is constituted by the FET and it appears that the parasitic capacitance is hanging in the output end out. On the contrary, in the fourth embodiment, the transistor Q 4  functions as a buffer, so that the capacity of the current source  82  is lighten up and the high-speed drive may be performed. 
         [0065]    In such a configuration, the cascode connection of the common base transistor Qc is performed on the collector of the input transistor Q, so that the collector potentials of the input transistors Q are stabilized. 
         [0066]    In the drive unit of the above-described embodiments, even when signals that are obtained by performing analog delay (variable delay adjustment) are combined in order to achieve high-speed drive of the VCSEL, a crosstalk between input signals may be reduced and variation in jitter may be suppressed. 
         [0067]    In the first embodiment to the fourth embodiment, the pre-emphasis generation circuit  20  that includes three taps is employed, and the number of taps is not limited as long as the pre-emphasis generation circuit  20  includes a plurality of taps. The light-emitting element is not limited to the VCSEL, and the drive unit may drive any light-emitting element that oscillates at high speed. Any combination of the first embodiment to the fourth embodiment may be performed. 
         [0068]    All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.