Abstract:
An apparatus configured to read and write data in a plurality of memories. The plurality of memories may be configured to store and present the data in response to (i) a write data path and (ii) a read data path. One of the plurality of memories may be configured to control the remainder of the plurality of memories in response to one or more write signals and (ii) one or more read signals.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     The present application may relate to application Ser. No. 09/406,042, filed Sep. 27, 1999, which is hereby incorporated by reference in its entirety. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to multi-queue storage devices generally and, more particularly, to a method and/or architecture of width and depth expansion in a high speed multi queue system. 
     BACKGROUND OF THE INVENTION 
     Referring to FIG. 1 a block diagram of a conventional circuit  10  for width expansion of a first-in first-out (FIFO) device is shown. The circuit  10  comprises a FIFO  12 , a FIFO  14 , a bus WDATA[ 79 : 0 ] and a bus RDATA[ 79 : 0 ]. The 80-bit bus WDATA[ 79 : 0 ] writes data to the FIFOs  12  and  14  through a 40-bit bus [ 39 : 0 ] and a 40-bit bus [ 79 : 40 ]. The 80-bit bus RDATA[ 79 : 0 ] reads the data from the FIFOs  12  and  14  through a 40-bit bus [ 39 : 0 ] and a 40-bit bus [ 79 : 40 ]. The FIFOS  12  and  14  each communicate through the 40-bit data busses [ 39 : 0 ] and [ 79 : 0 ] creating an 80-bit width circuit  10 . The bus WDATA[ 79 : 0 ] and the bus RDATA[ 79 : 0 ] create point-to-point connections between (i) the FIFOs  12  and  14  and (ii) various reading and writing devices (not shown). 
     A write clock signal WCLK is presented to an input  16  of the FIFO  12  and to an input  18  of the FIFO  14 . A write enable signal WEN is presented to an input  20  of the FIFO  12  and to an input  22  of the FIFO  14 . A read clock signal RCLK is presented to an input  24  of the FIFO  12  and to an input  26  of the FIFO  14 . A read enable signal REN is presented to an input  28  of the FIFO  12  and to an input  30  of the FIFO  14 . Data is written to the FIFO  12  and/or  14  on a rising edge of the clock signal WRLK when the enable signal WEN is active (or asserted). The data is read from the FIFO  12  and/or  14  on a rising edge of a read clock signal RCLK when the read enable signal REN is active. 
     The circuit  10  additionally comprises a full flag logic block  29  and an empty flag logic block  31 . The full flag logic block  29  generates full flags in response to the fullness of the FIFOs  12  and  14 . An output  34  of the FIFO  12  is connected to an input  32  of the full flag logic block  29 . An output  38  of the FIFO  14  is connected to an input  36  of the full flag logic block  29 . The empty flag logic block  31  generates empty flags in response to the emptiness of the FIFOs  12  and  14 . An output  42  of the FIFO  12  is connected to an input  40  of the empty flag logic block  31 . An output  46  of the FIFO  14  is connected to an input  44  of the empty flag logic block  31 . Logic flags for the circuit  10  are generated in response to the emptiness/fullness of the FIFOs  12  and  14 . 
     The circuit  10  cannot deal with multi-queue configuration, status information, queue selection, queue reset operation and/or multicast/broadcast support functions. As the spread (i.e., the number of FIFOs) of the circuit  10  increases, the write enable signal WEN and the read enable signal REN require point-to-multipoint additional circuitry to avoid bus contention at the read interface. 
     Referring to FIG. 2 a block diagram of a conventional circuit  50  for depth expansion of FIFOs is shown. The circuit  50  comprises a FIFO  52 , a FIFO  54 , a bus WDATA[ 39 : 0 ] and a bus RDATA[ 39 : 0 ]. The 40-bit bus WDATA[ 39 : 0 ] is connected to an input  56  of the FIFO  52  and to an input  58  of the FIFO  54 . The 40-bit bus RDATA[ 39 : 0 ] is connected to an output  60  of the FIFO  52  and an output  62  of the FIFO  54 . The 40-bit bus WDATA[ 39 : 0 ] and the 40-bit bus RDATA[ 39 : 0 ] are each connected in parallel with the FIFOs  52  and  54 . The parallel buses WDATA[ 39 : 0 ] and RDATA[ 39 : 0 ] create a FIFO having twice the depth of either the FIFO  52  or  54 . 
     Data is written into the FIFO  52  and/or  54  through the bus WDATA[ 39 : 0 ]. The data is read from the FIFO  52  and/or  54  through the bus RDATA[ 39 : 0 ]. The busses WDATA[ 39 : 0 ] and RDATA[ 39 : 0 ] are point-to-multipoint connections between (i) the FIFOs  52  and  54  and (ii) various reading and writing devices (not shown). 
     A write clock signal WCLK is presented to an input  64  of the FIFO  52  and to an input  66  of the FIFO  54 . A write enable signal WEN is presented to an input  68  of the FIFO  52  and an input  70  of the FIFO  54 . A read clock signal RCLK is presented to an input  72  of the FIFO  52  and to an input  74  of the FIFO  54 . A read enable signal REN is presented to an input  76  of the FIFO  52  and an input  78  of the FIFO  54 . Data is written to the FIFO  52  and/or  54  on a rising edge of the clock signal WRLK when the enable signal WEN is active. The data is read from the FIFO  52  and/or  54  on a rising edge of a read clock signal RCLK when the read enable signal REN is active. 
     The circuit  50  additionally comprises a full flag logic block  80  and an empty flag logic block  81 . The full flag logic block  80  generates full flags in response to the fullness of the FIFOs  52  and  54 . An output  83  of the FIFO  52  is connected to an input  82  of the full flag logic block  80 . An output  85  of the FIFO  54  is connected to an input  84  of the full flag logic block  80 . The empty flag logic block  81  generates empty flags in response to the emptiness of the FIFOs  52  and  54 . An output  87  of the FIFO  52  is connected to an input  86  of the empty flag logic block  81 . An output  89  of the FIFO  54  is connected to an input  88  of the empty flag logic block  81 . Logic flags for the circuit  50  are generated in response to the emptiness/fullness of the FIFOs  52  and  54 . 
     The circuit  50  requires additional circuitry for depth expansion. The FIFOs  52  and  54  are connected in a daisy chain type configuration. A write token pin WTI  90  of the FIFO  54  is connected to a write token pin WTO  91  of the FIFO  52 . A read token pin RTI  92  of the FIFO  54  is connected to a read token pin WTO  93  of the FIFO  52 . A write token pin WTO  95  of the FIFO  54  is connected to a write token pin WTI  94  of the FIFO  52 . A read token pin WTO  97  of the FIFO  54  is connected to a read token pin RTI  96  of the FIFO  52 . The write token pins WTI  90 , WTO  91 , WTI  94  and WTO  95  are used to implement write depth expansion. The read token pins RTI  92 , RTO  93 , RTI  96  and RTO  97  are used to implement read depth expansion. 
     The FIFO  52  passes a write token to the pin WTI  90  during a full condition. The write token forces a next data packet to be written in the FIFO  54 . The FIFO  54  passes the write token back to the pin  94  of the FIFO  52  during a full condition. In a case where both the FIFOs  52  and  54  are full, the full flag logic block  80  will assert a full flag. The read tokens of the FIFOs  52  and  54  operate similarity to the write tokens and are passed between the two FIFOs  52  and  54 . 
     The circuit  50  cannot implement a delayed queue select write operation. The delay queue select write operation cannot be implemented because each of the FIFOs  52  and  54  need to know a queue address before determining whether the write token is present. In order for delayed queue selection write operation to be implemented, the FIFOs  52  and/or  54  need to store data from the start-of-packet. 
     The delay queue selection write operation requires a point-to-multipoint data interface. The point-to-multipoint interface requires additional circuitry and in some cases, may even be impossible as the frequency of operation increases. The management interface further requires additional circuitry and in some cases, may even be impossible as the frequency of operation increases. 
     The delay queue select operation requires additional external logic to determine the flag status of each queue that is presented on the pin. For example, if 16 flags are presented on the pins for full and empty flags simultaneously, 32 external flag detection logic circuits would be required. The delay queue select further requires complicated end of packet (EOP) logic communication between chips. Additionally, the delay queue selection operation requires logic to avoid bus contention at the read interface. 
     SUMMARY OF THE INVENTION 
     The present invention concerns an apparatus configured to read and write data in a plurality of memories. The plurality of memories may be configured to store and present the data in response to (i) a write data path and (ii) a read data path. One of the plurality of memories may be configured to control the remainder of the plurality of memories in response to one or more write signals and (ii) one or more read signals. 
     The objects, features and advantages of the present invention include providing a circuit for multi-queue storage that may implement (i) a width expansion scheme allowing multi-queue configuration, status information, queue selection, queue reset operation and multicast/broadcast support functions, (ii) high speed point-to-multipoint connections, (iii) a delayed queue select write operation, (iv) point-to-multipoint data interfaces that may not have a need for additional circuitry, (v) a flag status scheme that may not require external logic to determine the flag status of each queue that is presented on the pin, (vi) communication between chips that may not require complicated end of packet logic and/or (vii) a read interface that may not require additional logic to avoid bus contention at the read interface. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the pended claims and drawings in which: 
     FIG. 1 is a detailed block diagram of a convention circuit for width expansion; 
     FIG. 2 is a detailed block diagram of a conventional circuit for depth expansion FIG. 3 ( a )-( b ) are block diagrams illustrating differences between single queue and multi-queue devices; 
     FIG. 4 is a block diagram of a preferred embodiment of the present invention illustrating width expansion; 
     FIG. 5 is a block diagram of the present invention illustrating d expansion; 
     FIG. 6 is a lock diagram illustrating an example of the management interfaces; and 
     FIG. 7 is a block diagram of an example of an expansion interface. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 3 a , a block diagram of a circuit  100  is shown illustrating a single queue FIFO  100 . The FIFO  100  may receive a clock signal (e.g., WCLK) at an input  102 , a bus (e.g., WD[ 39 : 0 ]) at an input  104 , a signal (e.g., WEN) at an input  106 , a clock signal (e.g., RCLK) at an input  110 , and a signal (e.g., REN) at an input  112 . The FIFO  100  may be connected to an interface (e.g., WRITE MANAGEMENT) at a connection  108  and an interface (e.g., READ MANAGEMENT) at a connection  114 . The FIFO  100  may present data to a bus (e.g., RD[ 39 : 0 ]) from an output  116 . 
     The write bus WD[ 39 : 0 ] may write to the FIFO  100  in response to the clock signal WCLK and the enable signal WEN. The read bus RD[ 39 : 0 ] may read from the FIFO  100  in response to the clock signal RCLK and the enable signal REN. 
     The FIFO  100  may comprise a memory section  120 , an interface block (or circuit)  122  and an interface block (or circuit)  124 . The interface circuit  122  may be implemented as a write interface circuit and the interface circuit  124  may be implemented as a read interface circuit. The write interface circuit  122  may be bi-directionally connected between a connection  126  of the memory section  120  and a connection  128 . The read interface circuit  124  may be bi-directionally connected between a connection  130  of the memory section  120  and a connection  132 . The memory section  120  may comprise a queue  138 . The FIFO  100  may write information to the queue  138  in response to the clock signal WCLK, the enable signal WEN, the write bus WD[ 39 : 0 ] and the interface WRITE MANAGEMENT. The FIFO  100  may read from the queue  138  in response to the clock signal RCLK, the enable signal REN, the read bus RD[ 39 : 0 ] and the interface READ MANAGEMENT. 
     Referring to FIG. 3 b  an example of a multi-queue circuit  100  is shown. The circuit  100  may be implemented as a multi-queue FIFO. The memory section  120  is generally capable of storing data in independently variable size queues  138   a - 138   n , where N is an integer. In one example, the maximum number of queues may be 64. However, a greater number of queues  138   a - 138   n  may be implemented accordingly to meet the design criteria of a particular implementation. Each of the queues  138   a - 138   n  may be independently configured from a minimum depth of 0 blocks to the maximum depth of the FIFO  100 . 
     The multi-queue FIFO  100  may write to the queues  138   a - 138   n  in response to the clock signal WCLK, the enable signal WEN, the write bus WD[ 39 : 0 ] and the interface WRITE MANAGEMENT. The multi-queue FIFO  100  may read from the queues  138   a - 138   n  in response to the clock signal RCLK, the enable signal REN, the read bus RD[ 39 : 0 ] and the interface READ MANAGEMENT. The multi-queue FIFO  100  may be implemented in network switch fabric systems that support quality of service (QoS) or virtual output queuing (VOQ) (to be discussed later in connection with FIG.  4 ). An example of such a multi-queue FIFO  100  may be found in co-pending application, Ser. No. 09/347,046, which is hereby incorporated by reference in its entirety. The multi-queue FIFO  100  may require additional methods and/or circuitry that may select one of the queues  138   a - 138   n  for reading and writing of data. The memory section  120  may additionally comprise a select block (or circuit)  140  and a select block (or circuit)  142 . The select blocks  140  and  142  may select a queue  138   a - 138   n  to write data to and/or read data from. 
     The queues  138   a - 138   n  may require a read and write management interface (to be discussed later in connection with FIG.  4 ). Outside multi-queue devices (not shown) may require width expansion of the multi-queue FIFO  100 . Width expansion may require the read and write management interfaces to become point-tomultipoint interfaces. The read and write management interfaces may be required to run at wire speed (e.g., the speed of a data interface). The read and write management interfaces may be required to access flag status data of the queues  138   a - 138   n  while performing other real time functions. The flag status for each queue  138   a - 138   n  is generally updated once a block is written into or extracted from the particular queue  138   a - 138   n.    
     Referring to FIG. 4, a block diagram of circuit  200  is shown illustrating width expansion in accordance with a preferred embodiment of the present invention. The circuit  200  may implement N number of FIFOs  100 , where N is an integer. The FIFOs  100   a - 100   n  may be implemented as multi-queue FIFOs. The circuit  200  may comprise a classifier block (or circuit)  202 , a scheduler block (or circuit)  204  and a switch fabric block (or circuit)  206 . The classifier  202  may be implemented as a queue classifier. In one example, the circuit  200  may implement the FIFO  100   a  as a master FIFO and the remaining FIFOs  100   b -- 100   n  as slave FIFOS. 
     The interface WRITE MANAGEMENT may be connected between the connection  108   a  of the master FIFO  100   a  and a connection  208  of the classifier  202 . The master FIFO  100   a  may communicate with the queue classifier  202  through the interface WRITE MANAGEMENT with a point-to-point connection. The interface READ MANAGEMENT may be connected between the connection  114   a  of the master FIFO  100   a  and a connection  210  of the scheduler  204 . The master FIFO  100   a  may communicate with the scheduler  204  through the interface READ MANAGEMENT with a point-to-point connection. 
     The enable signal WEN may be generated at an output  207  of the classifier  202 . The enable signal WEN may be presented to the input  106   a  of the FIFO  100   a . The clock signal WCLK may be generated at an output  209  of the classifier  202 . The clock signal WCLK may be presented to the inputs  102   a - 102   n  of the FIFOs  100   a - 100   n . The enable signal REN may be generated at an output  213  of the scheduler  204 . The enable signal REN may be presented to the input  112   a  of the FIFO  100   a . The clock signal RCLK may be generated at a output  215  of the scheduler  204 . The clock signal RCLK may be presented to the inputs  110   a - 110   n  of the FIFOs  100   a - 100   n.    
     The circuit  200  may additionally comprise a bus (e.g., WD[ 159 : 0 ]) and a bus (e.g., RD[ 159 : 0 ]). The bus WD[ 159 : 0 ] may be implemented, in one example, as a 160-bit write data bus. The bus RD[ 159 : 0 ] may be implemented, in one example, as a 160-bit read data bus. However, the particular bit-widths of the busses WD[ 159 : 0 ] and RD[ 159 : 0 ] may be adjusted accordingly to meet the criteria of a particular implementation. The 160-bit bus WD[ 159 : 0 ] may communicate between a connection  104   a - 104   n  of the FIFOs  100   a - 100   n  and a connection  211  of the classifier  202 . The FIFOs  100   a - 100   n  and the classifier  202  may communicate through the 40-bit busses WD[ 39 : 0 ] , WD[ 79 : 40 ], WD[ 119 : 80 ] and WD[ 159 : 120 ] (not all are shown). One of the 40-bit buses WD[ 39 : 0 ], WD[ 79 : 40 ], WD[ 119 : 80 ] and WD[ 159 : 120 ] may be connected to the FIFOs  100   a  - 100   n  at the connection  104   a - 104   n , respectively. For example, the 40-bit bus WD[ 39 : 0 ] may be connected to the input  104   a  of the FIFO  100   a.    
     The master FIFO  100   a  may communicate with the slave FIFOs  100   b - 100   n  through an interface (e.g., WRITE EXPANSION) and an interface (e.g., READ EXPANSION). The interface WRITE EXPANSION may be connected between an output  212  of the master FIFO  100   a  and a number of inputs  214   a - 214   n  of the slave FIFOs  100   b - 100   n . The interface READ EXPANSION may be connected between an output  216  of the master FIFO  100   a  and a number of inputs  218   a - 218   n  of the slave FIFOs  100   b - 100   n.    
     Communication over the interface WRITE MANAGEMENT may be classified into two categories (i) configuration information and (ii) real time information. The classifier  202  may configure the FIFOs  100   a - 100   n  by writing configuration information into the master FIFO  100   a . The master FIFO  100   a  may download the configuration information into the slave FIFOs  100   b - 100   n , allowing the FIFOs  100   a - 100   n  to be width expanded. The width expanded FIFOs  100   a - 100   n  may generate essentially identical status information. The status information may allow for an absence of communication across the interfaces WRITE EXPANSION and READ EXPANSION. The status information may be directly communicated between the master FIFO  100   a  and the classifier  202  through the interface WRITE MANAGEMENT. 
     Multicast port information may not have to be communicated to the slave FIFOs  100   b - 100   n . The scheduler  204  generally communicates to the master FIFO  100   a  through the interface READ MANAGEMENT. The scheduler  204  is generally able to receive the multicast port information from the master FIFO  100   a . The master FIFO  100   a  and the slave FIFOs  100   b - 100   n  may communicate through the interfaces WRITE EXPANSION and READ EXPANSION in real time. The information generally communicated between the master FIFO  100   a  and slave FIFOs  100   b - 100   n  is queue selection information, reset information and flush commands for multicast queues. 
     The 160-bit bus RD[ 159 : 0 ] may communicate between the FIFOs  100   a - 100   n  and the switch fabric circuit  206  through the 40-bit busses RD[ 39 : 0 ], RD[ 79 : 40 ], RD[ 119 : 80 ] and RD[ 159 : 120 ] of the FIFOs  100   a - 100   n  (not all are shown) . One of the 40-bit busses RD[ 39 : 0 ] , RD[ 79 : 40 ], RD[ 119 : 80 ] and RD[ 159 : 120 ] may be connected to the outputs  116   a - 116   n  of the FIFOs  100   a - 100   n , respectively. For example, the 40-bit bus RD[ 39 : 0 ] may be connected from the output  116   a  of the FIFO  100   a.    
     The FIFOs  100   a - 100   n  may be programmable FIFOs with features that require configuration. The FIFOs  100   a - 100   n  may require additional methods of selection. The methods of selection may be configured to select a queue of the multiple queues  138   a - 138   n  of FIG. 3 b  to read and/or write data. The queue classifier  202  may control writing to the FIFOs  100   a - 100   n . The scheduler  204  may control reading from the FIFOs  100   a - 100   n.    
     Referring to FIG. 5, a more detailed block diagram of the circuit  200  is shown illustrating an example of depth expansion. The example of the circuit  200  in FIG. 5 may eliminate the point-to-multipoint connection by implementing a bus (e.g., RD[ 39 : 0 ]) and a bus (e.g., WD[ 39 : 0 ]). The bus RD[ 39 : 0 ] may be implemented, in one example, as a 40-bit read bus. The bus WD[ 39 : 0 ] may be implemented, in one example, as 40-bit write bus. 
     The circuit  200  may implement depth expansion by implementing a special case of width expansion with bus matching. The circuit  200  may be implemented, in one example, as a 40-bit wide multi-queue circuit. The circuit  200  may be implemented as a device twice as deep as the FIFO  100   a . The circuit  200  is generally configured by bus matching, enabling only half of the input interface of the circuit  200 . In such an implementation, half a word is generally written to each of the FIFOs  100   a - 100   b.    
     The circuit  200  may allow point-to-point data interface of the same width, but with double depth. The classifier  202  and scheduler  204  may control reading and writing of the circuit  200 . The classifier  202  and scheduler  204  may operate similar to point-to-point width expansion. 
     Referring to FIG. 6, a block diagram of the circuit  200  illustrating an example of the management interfaces. The circuit  200  may be a detailed example of the interfaces WRITE MANAGEMENT and READ MANAGEMENT. 
     An output  252  of the classifier  202  may present a signal (e.g., R/WC) to an input  250  of the master FIFO  100   a . A connection  256  of the classifier  202  may be connected through an interface (e.g., WMD[ 15 : 0 ]) to a connection  254  of the FIFO  100   a . An output  260  of the classifier  202 ′ may present a clock signal (e.g., WCEN) to an input  258  of the FIFO  100   a . An output  264  of the classifier  202  may be connected though an interface (e.g., WA[ 4 : 0 ]) to an input  262  of the FIFO  100   a . A connection  268  of the classifier  202  may be connected through an interface (e.g., WM[ 1 : 0 ]) to a connection  266  of the FIFO  100   a . An output  272  of the master FIFO  100   a  may present a signal (e.g., WBUSY) to an input  270  of the classifier  202 . The particular polarities (e.g., active high or active low) and the bit-width of the signals R/WC, WMD[ 15 : 0 ], WCEN, WAC[ 4 : 0 ], WM[ 1 : 0 ] and WBUSY may be adjusted accordingly in order to meet the criteria of a particular implementation. The signals R/WC, WMD[ 15 : 0 ], WCEN, WAC[ 4 : 0 ], WM[ 1 : 0 ] and WBUSY may be management interface signals that may be used to write to and/or read from the circuit  200 . 
     An output  273  of the scheduler  204  may present a signal (e.g., R/WS) to an input  271  of the master FIFO  100   a . A connection  276  of the scheduler  204  may be connected through an interface (e.g., RMD[ 15 : 0 ]) to a connection  274  of the FIFO  100   a . An output  280  of the scheduler  204  may present a clock signal (e.g., RCEN) to an input  278  of the FIFO  100   a . An output  284  of the scheduler  204  may be connected though an interface (e.g., RA[ 4 : 0 ]) to an input  282  of the FIFO  100   a . An output  288  of the master FIFO  100   a  may present a signal (e.g., RBUSY) to an input  286  of the scheduler  204 . A connection of the master FIFO  100   a  may be connected through an interface (e.g., RM[ 1 : 0 ]) to a connection  290  of the FIFO  100   a . The particular polarities (e.g., active high or active low) and the bit-width of the signals R/WS, RMD[ 15 : 0 ], RCEN, RA[ 4 : 0 ], RBUSY and RM[ 1 : 0 ] may be adjusted accordingly in order to meet the criteria of a particular implementation. The signals R/WS, RMD[ 15 : 0 ], RCEN, RA[ 4 : 0 ], RBUSY and RM[ 1 : 0 ] may be management interface signals that may be used to write to and/or read from the circuit  200 . 
     The interfaces WMD[ 15 : 0 ] and RMD[ 15 : 0 ] may be implemented as write data interfaces, read data interfaces or any other type appropriate interface to meet the criteria of a particular implementation. The interfaces WM[ 1 : 0 ] and RM[ 1 : 0 ] may carry end-of-packet (EOP), start-of-packet (SOP) or any other tag information necessary to meet the design criteria of a particular implementation. The signal WBUSY and the signal RBUSY may be implemented to communicate to external devices connected to the circuit  200  that the operations on the current queue are in progress and the status or stats information may not be current. 
     Referring to FIG. 7, a block diagram of a circuit  300  is shown illustrating an example of an expansion interface. The circuit  300  may implement N number of the FIFOs  100 , where N is an integer. The FIFOs  100  may be implemented as multi-queue FIFOS. In one example, the circuit  300  may implement the FIFO  100   a  as a master FIFO and the remaining FIFOs  100   b - 100   n  as slave FIFOs. 
     The master FIFO  100   a  may present a clock signal (e.g., RSCLK 4 ) at an output  302 , an enable signal (e.g., RSEN[ 2 : 0 ]) at an output  304 , a signal (e.g., REOP[ 2 : 0 ]) at an output  306 , a signal (e.g., REA[ 7 : 0 ]) at an output  308  and a signal (e.g., RED[ 7 : 0 ]) at an output  310 . 
     The master FIFO  100   a  may present a clock signal (e.g., WSCLK 4 ) at an output  312 , an enable signal (e.g., WSEN[ 2 : 0 ]) at an output  314 , a signal (e.g., WEOP[ 2 : 0 ]) at an output  316 , a signal (e.g., WEA[ 7 : 0 ]) at an output  318  and a signal (e.g., WED[ 7 : 0 ]) at an output  320 . 
     The slave FIFOs  100   b - 100   n  may each receive the clock signal RSCLK 4  at an input  322   a - 322   n , the enable signal RSEN[ 2 : 0 ] at an input  324   a - 324   n , the signal REOP[ 2 : 0 ] at an input  326   a - 326   n , the signal REA[ 7 : 0 ] at an input  328   a - 328   n  and the enable signal RED[ 7 : 0 ] at an input  330   a - 330   n.    
     The slave FIFOs  100   b - 100   n  may each additionally receive the clock signal WSCLK 4  at an input  332   a - 332   n , the enable signal WSEN[ 2 : 0 ] at an input  34   a - 334   n , the signal WEOP[ 2 : 0 ] at an input  336   a - 336   n , the signal WEA[ 7 : 0 ] at an input  338   a - 338   n  and the enable signal WED[ 7 : 0 ] at an input  340   a - 340   n.    
     The master FIFO  100   a  may generate data on the expansion data busses WED[ 7 : 0 ] and RED[ 7 : 0 ]. The signal WEA[ 7 : 0 ] and the signal RED[ 7 : 0 ] may determine whether the data on the data bus is queue select information or queue reset information. The clock signal WSCLK 4  and RSCLK 4  may be implemented as expansion clocks. The expansion clocks WSCLK 4  and RSCLK 4  may synchronize the queue select information or the queue reset information from the master FIFO  100   a  to the slave FIFOS  100   b - 100   n . The clocks WSCLK 4  and RSCLK 4  may be implemented as having, in one example, a frequency equal to one quarter of the management interface frequency. The signals WEOP[ 2 : 0 ] and REOP[ 2 : 0 ] may comprise end-of-packet information and enable signals for configuration of the slave FIFOS  100   b - 100   n . The signals WEOP[ 2 : 0 ] and REOP[ 2 : 0 ] may toggle at the same frequency as the management interface, but are generally provided as point-to-point connections for the slave FIFOs  100   b - 100   n . The signals WEOP[ 2 : 0 ] and REOP[ 2 : 0 ] may eliminate a need for any external logic for signals. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.