Abstract:
A telemetry system for use with implantable medical devices is disclosed which utilizes both in-phase and quadrature data components, and frequency modulates both data components into a single transmitted sinusoidal signal which varies in frequency between two selected frequencies. The signal is received and decoded, preferably by a coherent decoder, into in-phase and quadrature components, which are then integrated and sampled to produce the two transmitted in-phase and quadrature data components, which may then be recombined to produce the transmitted data. The system requires only low power, and is capable of operating at a relatively high data rate while retaining a high degree of accuracy due to the splitting of the signal into the in-phase and quadrature data components.

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates generally to a telemetry system for use in medical devices of various types and for various purposes implantable within the human body, and more particularly to a telemetry system which will transmit data at a relatively high rate in both directions while retaining a high degree of accuracy. 
     With the ever-shrinking size of electronic circuitry, the implantation into the human body of electronic medical devices has become more and more common. Although the most commonly known of such devices is the cardiac pacemaker, there are a variety of devices which are implanted into the human body, including devices for the stimulation or tenting, or both, of the brain, nerves, the spinal cord, muscles, bones, glands, or other body organs or tissues. 
     It will be appreciated by those skilled in the art that such implantable devices are becoming increasingly complex, and that more functions can be crammed into a relatively smaller electronic chip or circuit. Implantable medical devices have used bidirectional telemetry for a number of years. Information transmitted between the implanted device and an external transceiver may include, for example, device identification information, biological data, current operational parameters of the device, technical information regarding proper operation of the device, battery charge condition, revised operational parameters (programming information) for the device, and verification of information transmitted between the implanted device and the external transceiver. 
     With an ever-increasing amount of data being processed and available within the implantable device, there has been a corresponding increase in the need to transmit more data from the implanted device to the external transceiver for analysis, reprogramming of the implantable device, or other purposes. The need for more data to be transmitted in both directions has increased tremendously the amount of time required both to interrogate the implanted device and to reprogram the implanted device. An upper limit on the amount of data flowing between the implanted device and the external transceiver has therefore become directly proportional to the amount of time which may reasonably be taken to interrogate and reprogram the implanted device. 
     Accordingly, it is desirable to achieve a higher rate of data transfer between the implanted device and the external transceiver to eliminate this artificial impediment and to maximize the communication between the implanted device and the external transceiver. Of course, an increase in the rate of data exchange may not be obtained at the expense of accuracy in a medical device, particularly if the device is a life-sustaining device such as a pacemaker. Absolute accuracy is required, and it is apparent that an increase in the rate of data transfer will be nullified by an increase in the amount of time spent to verify data to ensure the degree of accuracy required. 
     The recent development of LSI circuits incorporating low current analog-to-digital converters has made the use of such converters in implantable devices possible. There are, of course, limitations surrounding the design of new implantable systems or portions thereof, the most limiting of which is the consumption of energy by the system. Implanted systems are customarily powered by a long-lasting non-replaceable internal battery, and the current consumption of a telemetry sub-system thus becomes perhaps the most important design factor to be considered. 
     Previously known devices have established various methods of communicating non-invasively through the skin. For example, U.S. Pat. No. 4,223,679, to Schulman et al., which patent is assigned to the assignee of the present invention, shows an implanted device which uses little or no current to transmit information by relying on reflected impedance of an internal L-C circuit. Internal modulation circuits in the implanted device transmit digital or analog data by modulating the reflected impedance, and the external transceiver utilizes an oscillator having varying frequency and amplitude outputs determined by a coupled RF magnetic field carrier to an L-C circuit in the external transceiver. This system works well, but, unfortunately, has speed limitations making it unsuitable for transmitting the amount of information contemplated herein. 
     Another type of device uses an active type transmitter, with the transmitted energy being taken from the implantable device battery. This type of device, which is illustrated in U.S. Pat. No. 4,281,664, to Duggan, has a data rate which is limited to approximately 100 BPS (bits per second). Another device which utilizes an active type transmitter is shown in U.S. Pat. No. 4,453,162, to Money et al. The Money et al. device can not achieve more than 0.25 to 0.05 bps/carrier cycle, a rate too low for the applications contemplated herein. 
     Those skilled in the art will also appreciate that it is not practical to increase the carrier frequency above approximately eight kHz, since the metal enclosure of the implanted device will experience eddy currents great enough to attenuate the signal significantly. In addition, increasing the carrier frequency makes electromagnetic interference from video display terminals, which are generally approximately 16 kHz, a significant problem. Consequently, techniques requiring a number of carrier cycles for each signal bit will be capable of achieving a speed only two to four kBPS. 
     It will therefore be appreciated that there exists a substantial need for a telemetry system which is capable of accurately transmitting and receiving data at a rate enabling the substantial amounts of data used by current implantable systems to be conveniently sent in a relatively short period of time. The amount of power required by the implanted portion of the system must be minimal, so as not to adversely affect battery life. Finally, the system should be compact so as to not add significantly to the space required by the implanted device. 
     SUMMARY OF THE INVENTION 
     The disadvantages and limitations of the background art discussed above are overcome by the present invention. With this invention, a circuit using an active transmitter can achieve a bit rate equal to or higher than the carrier frequency, thereby achieving a practical speed of about eight kBPS. Also, the circuit of the present invention uses a drive circuit which achieves high power efficiency. 
     In accordance with the present invention an inductor in the implantable device is used to generate a magnetic field through which information may be transmitted to an external receiver. The inductor is then tuned to one of two frequencies by using either one or two capacitors connected in parallel across the inductor. While transmitting data, one of the capacitors is permanently connected in parallel across the inductor, and determines the first resonant frequency of the system. 
     One side of the second capacitor is connected to one side of the parallel first capacitor and inductor combination; the other side of the second capacitor is connected to one side of a switch, the other side of which switch is connected to the other side of the parallel first capacitor and inductor combination. Whenever the switch is closed, the second capacitor will be connected in parallel together with the first capacitor and the inductor, and the resulting tuned circuit will resonate at a second frequency. 
     The external transceiver will contain means for decoding the first and second frequency carriers and for recovering the original data which was coded and transmitted. It will be understood that the process may be reversed to transmit data from the external transceiver to the implanted device. 
     In the preferred embodiment, the second frequency is selected to be equal to the first frequency minus half the signaling bit rate. The switch is controlled such that it is open when a &#34;0&#34; is to be transmitted, and closed when a &#34;1&#34; is to be transmitted, with the switch position being changed at the bit boundaries. The tuned circuit is energized for a short period of time each time its voltage reaches a positive or a negative peak by connecting it at the right polarity to the implanted device power source. The bit rate is chosen such that during a bit interval the tuned circuit voltage has an excursion of an integer number of peak-to-peak voltages. 
     By energizing the tuned circuit while its voltage passes through positive and negative peaks, as opposed to energizing it during only one polarity peak, sine wave distortion is reduced and the higher harmonic content, which is synonymous with lost energy, is reduced, thereby increasing transmitter power efficiency. In addition, as will become apparent from the following description, the method of switching between the first and second frequencies allows a constant amplitude carrier to be transmitted, as opposed to pulsing a carrier on and off, or abruptly changing the carrier phase. 
     The system of the present invention thereby achieves a reliable transmission at a higher signal to noise ratio, and at an implicitly lower average transmitter power, which features are very important for an implantable device. Also, by avoiding sharp amplitude and phase changes, the signal may be received by using only a relatively small bandwidth, which in turn both reduces the noise and permits operation of the transmitter at lower power. The maximum bit rate may therefore be equal to the first frequency. This was not possible in prior art systems, for in order to detect an amplitude modulated signal it requires more than one period (typically more than four periods) of the carrier. 
     Similarly, phase modulation as illustrated in Money et al. reference cited above will not achieve a bit rate equal to the first frequency. Thus, by energizing the tuned circuit during both positive and negative voltage excursions and by having the two tuning capacitors connected to the inductor, a maximum speed of approximately eight kBPS may be achieved. The system of the present invention is thereby capable of accurately transmitting and receiving data at a rate which enables the substantial amounts of data used by current implantable systems to be conveniently sent in a relatively short period of time. The amount of power required by the implanted portion of the system is minimal, thereby extending battery life. The system of the present invention is also quite compact, thereby fitting conveniently in the small space afforded by the implanted device. All of the above advantages are obtained without an relative disadvantage, making the system of the present invention a highly desirable improvement to the art. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     These and other advantages of the present invention are best understood with reference to the drawings, in which: 
     FIG. 1 is an electrical schematic of the implanted transceiver driver circuit of the present invention; 
     FIG. 2 is a timing diagram of control and output signals for the circuit shown in FIG. 1; 
     FIG. 3 is an electrical schematic of a circuit which may be used to generate the control signals shown in FIG. 2; 
     FIG. 4 is a functional schematic of the external transceiver for use with the implanted transceiver shown in FIG. 1; 
     FIG. 5 is a functional schematic of a coherent decoder which may be used in the circuit of FIG. 4; 
     FIG. 6 is a diagram showing the data and output signals generated and transmitted by the implanted transceiver shown in FIG. 1; and 
     FIG. 7 is a diagram of signals generated by the coherent decoder of FIG. 5 which are used to decode the received signal of FIG. 6. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The preferred embodiment utilizes the circuit illustrated in FIG. 1 in the implanted device to transmit and receive information to and from an external device (not shown in FIG. 1). An inductor or coil 10 is tuned to a first frequency f 1  by a first capacitor 12 which is connected on one side thereof to one side of the inductor 10, and on the other side thereof to one side of a semiconductor switch 14. The other side of the semiconductor switch 14 is connected to the other side of the inductor 10, and it will be appreciated that when the switch 14 is closed, the first capacitor 12 will be connected in parallel with the inductor 10. The circuit will resonate at the first frequency f 1  in an essentially sinusoidal fashion, with a slowly decaying sinusoidal voltage V L  across the inductor 10. The semiconductor switch 14 may be a transmission gate type device. 
     During transmission of data from the implanted device to the external device, the switch 14 is turned on or closed controlled by an input signal which is of high or true logic value, and which indicated that data is to be transmitted from the internal device to the external device. When data is to be received by the implanted device from the external device, the switch 14 will be turned off or opened. 
     The device may be tuned to a second frequency f 2  which is lower than the first frequency f 1  and which may be realized by installing a second capacitor 16 in parallel across the first capacitor 12 and the inductor 10. One side of the second capacator 16 is connected to the one side of the inductor 10, and the other side of the second capacitor 16 is connected to a second switch 18. The other side of the second switch 18 is connected to the other side of the inductor 10. The second switch 18 may be opened and closed to transmit binary data; in the embodiment discussed herein, for example, the second switch 18 will be turned on or closed when the data is to be serially transmitted is a logical &#34;1&#34;, and turned off or opened when the data to be serially transmitted is a logical &#34;0&#34;. When the second switch 18 is closed, the circuit will resonate at the second frequency f 2  in an essentially sinusoidal fashion, also with a slowly decaying sinusoidal voltage V L  across the inductor 10. The semiconductor switch 18 may also be a transmission gate type device. 
     Four semiconductor switches are connected as a bridge circuit to a power source 20, which is typically the battery powering the implanted device. A first bridge switch 22 is connected on one side thereof to one side of the power source 20, and on the other side thereof to the other side of the inductor 10. A second bridge switch 24 is connected on one side thereof to the one side of the power source 20, and on the other side thereof to the one side of the inductor 10. A third bridge switch 26 is connected on one side thereof to the other side of the power source 20, and on the other side thereof to the other side of the inductor 10. Finally, a fourth bridge switch 28 is connected on one side thereof to other side of the power source 20, and on the other side thereof to the one side of the inductor 10. 
     It will be appreciated that the four bridge switches 22, 24, 26, and 28 are turned off or opened most of the time. The four bridge switches 22, 24, 26, and 28 are operated by control signals A, B, C, and D, respectively. For short periods of time approximately coinciding with positive peaks of coil voltage V L  as oriented in FIG. 1, the first and fourth switches 22 and 28 are briefly closed. Similarly, when V L  approximately reaches negative peaks, the second and third switches 24 and 26 are briefly closed. In this way, a permanent oscillation of the tuned circuit at virtually constant amplitude is maintained. 
     For example, the first and second switches 22 and 24 may be P-MOS transistors, and the third and fourth switches 26 and 28 may be N-MOS transistors. The first and second switches 22 and 24 are then open when their relative control signals A and B are a logical &#34;1&#34; and closed when their relative control signals are a logical &#34;0&#34;. The third and fourth switches 26 and 28 are open when their relative control signals C and D are a logical &#34;0&#34; and closed when their relative control signals are a logical &#34;1&#34;. 
     Referring now to FIG. 2 in conjunction with FIG. 1, it is apparent that the signal V L  has a constant frequency, either the first frequency f 1  or the second frequency f 2 , during each bit internal. In the preferred embodiment the first frequency f 1  is 8192 Hz and the second frequency f 2  is 4096 Hz. Their difference, 8192 Hz minus 4096 Hz, is 4096 Hz, which is half the bit rate of 8192 BPS. 
     In the preferred embodiment, the second frequency is selected to be equal to the first frequency minus half the signaling bit rate f R , which is the reciprocal of the bit duration T. By selecting these frequencies, during each bit interval the voltage V L  on the inductor 10 will start and stop on a peak value. The average current drawn from the power source 20 is very small, since during each supplying pulse the tuned circuit amplitude has to be increased only slightly to compensate for the natural decay in amplitude due to the limited quality factor (Q) of the coil. 
     The supply of electrical energy to the circuit in brief pulses during both positive and negative voltage peaks, as opposed to a supply in pulse mode during only either positive or negative peaks, has the advantage of reducing distortion of the fundamental 8192 Hz or 4096 Hz sine waves. Lower distortion of course yields higher power efficiency, since the distortion is comprised of harmonics which will be discarded by the receiver (not shown in FIGS. 1 or 2). 
     While a data &#34;0&#34; is transmitted by the implanted device, the second capacitor 16 is disconnected by the second switch 18. However, the charge (or voltage) is stored on the second capacitor 16, and is reused when the next data &#34;1&#34; is transmitted because the V L  polarity at the beginning of a bit to the beginning of the next consecutive bit never changes if a data &#34;0&#34; is transmitted. This important characteristic of the driving circuit provides that the circuit does not draw additional energy due to the transition in transmission from data &#34;0&#34; to data &#34;1&#34; and from data &#34;1&#34; to data &#34;0&#34;. 
     The implanted device can also receive information from an external device which inductively couples signal into the inductor 10. During receiving, the &#34;DATA&#34; input control to the second switch 18 is turned low, opening the second switch 18, and the T/R input control to the switch 14 is turned low, opening the switch 14 and closing the first bridge switch 22 (see FIG. 1, and also FIG. 3, signal A). This configuration couples the inductor 10 to an implanted receiver 30, whose output is a binary signal available to be used to decode the information received from the external device. 
     Optionally, a switch 32 will provide power to the receiver 30 only during periods when the receive function is being implemented. The control signal G, generated by the circuit of FIG. 3, is provided to control the switch 32. It should be noted that the T/R signal must be switched high and low only immediately before bit transition times. This ensures that no change on the first capacitor 12 or on the second capacitor 16 is lost, since after a receive period the transmit period will start with the same V L  polarity as that left from the prior transmission period. Beyond this, the circuit of FIG. 3 does not require further explanation as it is common for those skilled in the art and may be implemented in a number of different ways. 
     FIG. 3 illustrates one possible example of a circuit which may be used to generate the control signals A, B, C, and D, and also to generate an additional control signal G. Inputs to the circuit of FIG. 3 are the transmit/receive line T/R which is also the input for the switch 14, the data line DATA which is also the input for the second switch 18, and three clock signals at 32768 Hz, 16384 Hz, and 8192 Hz. The source of the 32768 Hz signal may be derived from the crystal oscillator which is usually an integral part of implantable devices, as are the divided down frequencies of 16384 Hz, 8192 Hz, and 4096 Hz (used in FIG. 5). The control signal G is used to operate a receiver in the implanted device, and will be discussed below. 
     The transmit/receive line T/R is the input for a first inverter 40, the output of which is the control signal G. The control signal G is also supplied as an input to a first two input NOR gate 42, to a first three input NOR gate 44, to a second three input NOR gate 46, and to a second two input NOR gate 48. The DATA line and the 8192 Hz clock signal are the inputs for an AND gate 50, the output of which is an input for the first two input NOR gate 42. The output of the first two input NOR gate 42 is supplied as an input to both the J and K lines of a JK flip-flop 52, and the 16384 Hz clock signal is supplied to the JK flip-flop 52 as the clock signal. 
     The Q output of the JK flip-flop 52, which is shown in the timing charts of FIG. 2 as the control signal F, is supplied as an input to the D line of a D flip-flop 54, and as an input to a two input EXOR gate 56 and to the first three input NOR gate 44. The Q output of the JK flip-flop 52 is supplied as an input to the second three input NOR gate 46. The 32768 Hz clock signal is supplied as the clock signal to the D flip-flop 54, and the Q output of the D flip-flop 54 is supplied as an input to the two input EXOR gate 56. 
     The output of the two input EXOR gate 56, which is shown in the timing charts of FIG. 2 as the control signal E, is supplied as an input to the first three input NOR gate 44 and to the second three input NOR gate 46. The output of the first three input NOR gate 44 is the control signal D, and this output is supplied as an input to the second two input NOR gate 48. The output of the second two input NOR gate 48 is the control signal A. The output of the second three input NOR gate 46 is the control signal C, and this output is supplied as an input to a second inverter 58. The output of the second inverter 58 is the control signal B. 
     The external transceiver used to receive data transmitted from the implanted device and to transmit data to the implanted device may now be discussed in conjunction with FIG. 4. A coil or inductor 60 is applied to the surface of the skin over the location of the inductor 10 of the implanted device. The two inductors 10 and 60 are constructed so that they will magnetically couple to each other. They may be regarded as two coils of a transformer having a low coupling coefficient. 
     A double pole, double throw switch is utilized in the external transceiver to switch between transmit and receive functions. Such a switch, which may be achieved either mechanically or electronically, is shown in FIG. 4 in schematic form as a first double pole switch 62 which is mechanically connected to and operating with a second double pole switch 64. Each of the double pole switches 62 and 64 has a switching contact a which is electrically connected to a contact b when the switches 62 and 64 are in a first position, and which is electrically connected to a contact c when the double pole switches 62 and 64 are in a second position. 
     The contact c of the first double pole switch 62 is connected to one side of the inductor 60. The contact b of the first double pole switch 62 and the contact c of the second double pole switch 64 are connected to the other side of the inductor 60. The contact b of the second double pole switch 64 is not used. The contact a of the first double pole switch 62 is connected to an input amplifier 66, the output of which is filtered by a bandpass filter 68 and then supplied to a decoder 70. 
     The contact c of the second double pole switch 64 is connected to the output of a wave generator 72, which has as its input information supplied from an encoder 74. Information to be transmitted from the external transceiver to the implanted device is supplied to the encoder 74, which encodes the information and supplied it to the wave generator 72. The wave generator 72 then supplies a waveform containing the encoded information. It will be appreciated by those skilled in the art that the wave generator 72 may function as does the circuit of FIG. 1 taught in this specification, or in other suitable ways known in the art. When the double pole switches 62 and 64 are in the second position, information may be transmitted from the external transceiver using the inductor 60, which will be connected to the wave generator 72 when the double pole switches 62 and 64 are in the second position. 
     When the double pole switches 62 and 64 are in the first position, the inductor 60 will be connected to the amplifier 66, and the external transceiver will act as a receiver. The voltage on the inductor 60 will be a replica of the signal V L  on the inductor 10 of the implanted device (FIG. 1), but with a lower voltage amplitude due to the low coupling coefficient between the inductor 10 and the inductor 60. After this signal is amplified by the amplifier 66 and goes through the bandpass filter 68, it goes into the decoder 70, which looks at the signal morphology for the presence of the first or second frequencies f 1  or f 2 , thereby deciding whether each bit interval of the transmission is a zero or a one. 
     Decoder circuits may be categorized as either coherent decoders or noncoherent decoders. Coherent decoders typically utilize phase locked loops or similar circuits to regenerate the two transmitted frequencies, and perform a correlation between these two frequencies and the received signal to decode the received signal. Noncoherent decoders are simpler, as they do not require a regeneration of the two transmitted frequencies. However, they require a higher signal-to-noise ratio in the received signal, which in turn requires higher implanted device transmitted power which is less desirable for use with a battery-powered implanted device. For the same transmitted power a coherent receiver will also provide a greater range, thereby allowing a larger distance between implanted and external inductor coils. A discussion of the coherent decoder is found in &#34;Coherent Demodulation of Frequency shift Keying With Low Deviation Ratio,&#34; R. DeBuda, IEEE Transactions on Communication, June 1972. 
     An example of a coherent decoder is shown in FIG. 5, which has as its input the amplified and filtered signal received from the implanted device. It is useful to discuss the operation of the coherent decoder in conjunction with an example of the transmission and receiving of data, and such an example is shown in FIGS. 6 and 7. In FIG. 6, a sample stream of data to be transmitted by the implanted device shown in FIG. 1 to the external transceiver shown in FIG. 4 is illustrated as DATA IN. This data may be thought of as the result of adding two streams of data, one with odd bits d I  and the other with even bits d Q . 
     The implanted device will transmit trains of two frequencies f 1  and f 2 , as described above in conjunction with FIG. 1. The trains of frequencies f 1  and f 2  may be analytically viewed as a simultaneous transmission of two quadrature carriers (carriers having a 90 degree relative phase shift), with each binary phase being shift keyed or modulated by the data to be transmitted. The odd bits d I  will modulate one carrier and the even bits d Q  will modulate the other carrier. 
     As described above, in the preferred embodiment the second frequency f 2  is selected to be equal to the first frequency f 1  minus half the signaling bit rate f R , which is the reciprocal of the bit duration T. The signaling bit rate f R  of the preferred embodiment is 8192 BPS, the first frequency f 1  is 8192 Hz, and the second frequency f 2  is 4096 Hz, with the difference between f 1  and f 2  being 4096 Hz, which is half the signaling bit rate f R  of 8192 BPS. 
     The frequency of the two carriers f 1  and f 2  can be trigonometrically demonstrated to be the arithmetic f 1  and f 2  average, which in this case is 6144 Hz. The advantage of this method lies in the fact that each bit now lasts 2T and the receiver has twice the time to make a decision whether the bit transmitted was a 0 or a 1, and as such is able to reject more noise. The transmitter need not be implemented as a two quadrature component system; only the receiver must be so constructed. FIG. 6 demonstrates how the two modulated 6144 Hz carriers I and Q are together equivalent to the f 1  /f 2  train. The I (in-phase) and Q (quadrature) signals are also amplitude modulated with a maximum in the middle of each odd bit d I  or even bit d Q . 
     Referring again to FIG. 5, in conjunction with FIG. 7, the amplified and filtered f 1  /f 2  signal received by the external transceiver is supplied to a hard limiter 76, the operation of which is known to those skilled in the art. Its output, the hard limited f 1  /f 2  signal, has two binary states, positive or negative, according to polarity of the amplified and filtered f 1  /f 2  signal. This hard limited f 1  /f 2  signal is supplied to two multipliers, namely an I multiplier 78, and a Q multiplier 80. The function of the I multiplier 78 is to isolate the I (in-phase) component of the hard limited f 1  /f 2  signal, and the function of the Q multiplier 80 is to isolate the Q (Quadrature) component of the hard limited f 1  /f 2  signal. 
     The hard limited f 1  /f 2  signal is also supplied to a phase-locked-loop circuit 82, where it is used to synchronize the clock signals provided as outputs from the phase-locked-loop circuit 82. The phase-locked-loop circuit 82 looks at the zero crossings of hard limited f 1  /f 2  signal and adjusts the phase of its 4096 Hz, 8192 Hz, and 16384 Hz outputs to match the phase relationship of the received f 1  /f 2  received by the external transceiver. The phase-locked-loop circuit 84 is not difficult to implement due to the special relations selected between the first frequency f 1 , the second frequency f 2 , and the signaling bit rate f R  which is the reciprocal of the bit duration T, namely that the second frequency f 2  is one-half the first frequency f 1 , and that the first frequency f 1  equal to the bit signaling rate f R . The f and i signals have to be generated by the receiver. 
     Two modulated recovered carriers are generated by adding and subtracting the 8192 Hz and the 4096 Hz outputs from the phase-locked-loop circuit 82 together. A first summer 84 adds the 8192 Hz and the 4096 Hz outputs from the phase-locked-loop circuit 82 together to produce the modulated recovered I carrier f, which is shown in FIG. 7 together with the sinusoidal I carrier labeled as g for comparison. Similarly, a second summer 86 subtracts the 8192 Hz output of the phase-locked-loop circuit 82 from the 4096 Hz output of the phase-locked-loop circuit 82 to produce the modulated recovered Q carrier i, which is shown in FIG. 7 together with the sinusoidal Q carrier labeled as j for comparison. 
     It should be noted that the signals f and i are approximations to the exact sinusoidal signals g and j, respectively. However, any performance degradation resulting from this approximation is negligible, and does not require further complicating the circuit of FIG. 5 with filters to smooth the f and i signals into closer approximations of the g and j signals, respectively. 
     The I multiplier 78 multiplies the hard-limited f 1  /f 2  signal by the modulated recovered I carrier f to isolate the I (in-phase) component of the hard limited f 1  /f 2  signal. When the hard-limited f 1  /f 2  signal is multiplied by the modulated recovered I carrier f in the I multiplier 78, the sign of the modulated recovered I carrier f is either changed if the hard-limited f 1  /f 2  signal is negative or unchanged if the hard-limited f 1  /f 2  signal is positive. The resulting signal which is supplied as the output of the I multiplier 78 is the signal k, shown in FIG. 7, which signal k is supplied to an integrate-and-dump device 88. 
     Similarly, the Q multiplier 80 multiplies the hard-limited f 1  /f 2  signal by the modulated recovered Q carrier i to isolate the Q (quadrature) component of the hard limited f 1  /f 2  signal. When the hard-limited f 1  /f 2  signal is multiplied by the modulated recovered Q carrier i in the Q multiplier 80, the sign of the modulated recovered Q carrier i is either changed if the hard-limited f 1  /f 2  signal is negative or unchanged if the hard-limited f 1  /f 2  signal is positive. The resulting signal which is supplied as the output of the Q multiplier 80 is the signal m, shown in FIG. 7, which signal m is supplied to an integrate-and-dump device 90. 
     The 4096 Hz clock output of the phase-locked-loop circuit 82 is supplied as an input to the D line on a D flip-flop 92. The 16384 Hz clock output of the phase-locked-loop circuit 82 is supplied as the clock input to the D flip-flop 92 to regenerate the data bit clock thereof. The Q and Q outputs of the D flip-flop 92 are therefore a series of alternating 1&#39;s and 0&#39;s, with the period in which one 1 and one 0 occurs being 2T. The D flip-flop 92 may be seen as a sort of steering circuit, which alternately causes signals from the in-phase side and the quadrature side of the circuit of FIG. 5 to be combined to produce a single consolidated output. 
     The Q output of the D flip-flop 92 is connected to one side of a capacitor 94, the other side of which is connected to the integrate-and-dump device 88. A resistor 96 is connected on one side to ground, and on the other side to the other side of the capacitor 94. The capacitor 94 and the resistor 96 provide to the integrate-and-dump device 88 a series of pulses which occur shortly after the rising edges of the Q output of the D flip-flop 92. The integrate-and dump device 88 integrates the k signal, and at the occurrence of each pulse occurring after a rising edge of the Q output of the D flip-flop 92, the integrate-and-dump device 88 is reset. 
     The Q output of the D flip-flop 92 is connected to one side of a capacitor 98, the other side of which is connected to the integrate-and-dump device 90. A resistor 100 is connected on one side to ground, and on the other side to the other side of the capacitor 98. The capacitor 98 and the resistor 100 provide to the integrate-and-dump device 90 a series of pulses which occur shortly after the rising edges of the Q output of the D flip-flop 92. The integrate-and-dump device 90 integrates the m signal, and at the occurrence of each pulse occurring after a rising edge of the Q output of the D flip-flop 92, the integrate-and-dump device 90 is reset. 
     The integrate-and-dump devices 88 and 90 will produce an output reflecting the inputs thereto. If for the majority of the 2T period the input to one of the integrate-and-dump devices 88 and 90 is high, the output from that device at the end of the 2T period will be high. Similarly, if for the majority of the 2T period the input to one of the integrate-and-dump devices 88 and 90 is low, the output from that device at the end of the 2T period will be low. The integrate-and-dump devices 88 and 90 may thus be viewed as low-pass filters. 
     The output from the integrate-and-dump device 88 is supplied as an input to the D line on a D flip-flop 102, which has as its clock input the Q output from the D flip-flop 92. The output from the integrate-and-dump device 88 is therefore sampled by the D flip-flop 102 after each period of time of 2T and at the rising edge of the Q output of the D flip-flop 92, which period is that determined by the D flip-flop 92. The Q output from the D flip-flop 102 is the signal 1 shown in FIG. 7. 
     Likewise, the output from the integrate-and-dump device 90 is supplied as an input to the D line on a D flip-flop 104, which has as its clock input the Q output from the D flip-flop 92. The output from the integrate-and-dump device 90 is therefore sampled by the D flip-flop 104 after each period of time of 2T and at the rising edge of the Q output of the D flip-flop 92, which period is that determined by the D flip-flop 92. The Q output from the D flip-flop 104 is the signal n shown in FIG. 7. 
     It will be appreciated that the integrate and dump cycles of the integrate-and-dump device 88 and the integrate-and-dump device 90 and the flip-flop samples of the D flip-flop 102 and the D flip-flop 104 are alternating, and must be interleaved to produce a single output from the external transceiver reflecting the input from the implanted device. Accordingly, the Q output 1 from the D flip-flop 102 and the Q output n from the D flip-flop 104 are supplied as inputs to a two input EXOR gate 106, the output of which is the desired received data. It will be appreciated that the data output from the two input EXOR gate 106 shown in FIG. 7 will be time delayed by a period of 2T from the data input shown in FIG. 6. This delay is caused by the sampling of the integrate-and-dump devices 88 and 90 by the D flip-flops 102 and 104, respectively, once every period of 2T. 
     Alternatively to the coherent decoder of FIG. 5, a noncoherent decoder could be used to decode the f 1  /f 2  signal. Noncoherent decoders, which are essentially envelope detectors, are well known in the art, but they would not work as well as coherent decoders at the relatively data frequency used herein. Because a coherent decoder has two parallel paths, and each path has a two bit interval (2T) to integrate the signal, a coherent decoder will necessarily have a better performance than the noncoherent decoder, and will be significantly more resistant to noise. 
     It will be appreciated by those skilled in the art that the system of the present invention achieves a reliable high rate of data transmission at a high signal to noise ratio, while requiring only low transmitter power, features which are very important for an implantable device. The signal is received using only a relatively small bandwidth, thereby both reducing noise and permitting operation of the transmitter at lower power. The maximum bit rate may be equal to the first frequency, a feature not possible in prior art systems, since in such systems in order to detect an amplitude modulated signal it required more than one period (typically more than four periods) of the carrier. 
     Also, by energizing the tuned circuit during both positive and negative voltage excursions and by having the two tuning capacitors connected to the inductor, a maximum speed of approximately eight kBPS may be achieved. The system of the present invention is capable of accurately transmitting and receiving data at a rate which enables the substantial amounts of data used by current implantable systems to be conveniently sent in a relatively short period of time. The amount of power required by the implanted portion of the system is minimal, thereby extending battery life, and the system of the present invention is quite compact. While attaining these advantages and features, no relative disadvantage is incurred. 
     Although an exemplary embodiment of the present invention has been shown and described, it will be apparent to those having ordinary skill in the art that a number of changes, modifications, or alterations to the invention as described herein may be made, none of which depart from the spirit of the present invention. All such changes, modifications, and alterations should therefore be seen as within the scope of the present invention.