Abstract:
To provide an imaging device capable of reducing the amount of data with a simple method. An imaging device includes: a plurality of sensor elements which is arranged in a matrix shape and each of which generates a photoelectric conversion voltage in accordance with an input light level; and a read circuit which is coupled to bit lines provided while being associated with respective columns of the sensor elements, and amplifies and reads the photoelectric conversion voltages generated in the sensor elements by being exposed at predetermined timing. The read circuit outputs differential data of the read photoelectric conversion voltages generated in the respective sensor elements that are adjacent to each other in the same row or column.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The disclosure of Japanese Patent Application No. 2016-132670 filed on Jul. 4, 2016 including the specification, drawings and abstract is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    The disclosure relates to an imaging device. 
         [0003]    An image sensor is used as a sensor to convert optical image information captured from the outside into an electric signal in a television camera or the like, and has a configuration in which a plurality of pixels is arranged on a plane in a matrix shape. The image sensor has a photodiode or a phototransistor, and peripheral circuits thereof are pixel circuits configured using MOS-type transistors. The various types of image sensors have been proposed (Japanese Unexamined Patent Application Publication No. 2000-175107). 
       SUMMARY 
       [0004]    On the other hand, in the case where a plurality of pixels is arranged, the amount of data tends to be increased because date is obtained on a pixel basis. 
         [0005]    The disclosure has been made to solve the above-described problem, and an object thereof is to provide an imaging device capable of reducing the amount of data with a simple method. 
         [0006]    The other objects and novel features will become apparent from the description of the specification and the accompanying drawings. 
         [0007]    According to an embodiment, an imaging device includes: a plurality of sensor elements which is arranged in a matrix shape and each of which generates a photoelectric conversion voltage in accordance with an input light level; and a read circuit which is coupled to bit lines provided while being associated with respective columns of the sensor elements, and amplifies and reads the photoelectric conversion voltages generated in the sensor elements by being exposed at predetermined timing. The read circuit outputs differential data of the read photoelectric conversion voltages generated in the respective sensor elements that are adjacent to each other in the same row or column. 
         [0008]    According to the embodiment, it is possible to provide an imaging device capable of reducing the amount of data with a simple method. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  is a diagram for explaining a configuration of an imaging device  1  on the basis of a first embodiment; 
           [0010]      FIG. 2  is a diagram for explaining a configuration of each unit pixel; 
           [0011]      FIG. 3  is a diagram for explaining a timing chart of the imaging device  1  on the basis of the first embodiment; 
           [0012]      FIG. 4  is a diagram for explaining an image on the basis of image data imaged by the imaging device  1  on the basis of the first embodiment; 
           [0013]      FIG. 5  is a schematic view in the case where differential data on the basis of the first embodiment is output; 
           [0014]      FIG. 6  is a diagram for explaining another timing chart of the imaging device  1  on the basis of the first embodiment; 
           [0015]      FIG. 7  is a diagram for explaining an image on the basis of different image data imaged by the imaging device  1  on the basis of the first embodiment; 
           [0016]      FIG. 8  is a functional block diagram for showing an entire configuration of an imaging device  1 # on the basis of a second embodiment; 
           [0017]      FIG. 9  shows an example of images that can be displayed on a display unit  9  on the basis of image data stored in a memory  8  on the basis of the second embodiment; 
           [0018]      FIG. 10  is a flowchart for explaining a compression method of image data on the basis of the second embodiment; and 
           [0019]      FIG. 11  is a diagram for explaining a configuration of a unit pixel on the basis of a modified example. 
       
    
    
     DETAILED DESCRIPTION 
       [0020]    Embodiments will be described in detail with reference to the drawings. It should be noted that the same or corresponding parts will be followed by the same signs in the drawings, and the explanation thereof will not be repeated. 
       First Embodiment 
     &lt;A. Configuration of Imaging Device&gt; 
       [0021]      FIG. 1  is a diagram for explaining a configuration of an imaging device  1  on the basis of a first embodiment. 
         [0022]    As shown in  FIG. 1 , the imaging device  1  includes a pixel array unit  2 , a horizontal driving unit  3 , a control unit  4 , a vertical driving unit  5 , and an amplifier  30 . 
         [0023]    In the pixel array unit  2 , unit pixels P (sensor elements) are arranged in a matrix shape. Each of the unit pixels includes a photoelectric conversion area in which incident light is converted into electricity and an electric charge in accordance with the incident light is accumulated. 
         [0024]    The pixel array unit  2  includes a word line and a reset line provided for each row of the unit pixels P. Further, the pixel array unit  2  includes a bit line provided for each column of the unit pixels P. 
         [0025]    In the example, four unit pixels P 1  to P 4  (hereinafter, generally referred to as a unit pixel P in some cases) are arranged in a matrix shape. 
         [0026]    Further, a word line WL and a reset line RST are provided for each row. The example shows a case in which word lines WL 0  and WL 1  and reset lines RST 0  and RST 1  are provided. 
         [0027]    Further, a bit line BL is provided for each column. The example shows a case in which bit lines BL 0  and BL 1  are provided. 
         [0028]    The horizontal driving unit  3  drives the word line WL and the reset line RST provided in the pixel array unit  2 . 
         [0029]    The horizontal driving unit  3  includes a row scan shift register  23  and a row driver  25 . 
         [0030]    The row scan shift register  23  generates a row address that is sequentially shifted from a head address in the vertical direction in accordance with a timing signal from a clock control circuit  26 , and supplies the same to the row driver  25 . The row driver  25  drives the reset line RST and the word line WL corresponding to the row address in the pixel array unit  2  in accordance with the row address. 
         [0031]    The control unit  4  generates and outputs various control signals for controlling the horizontal driving unit  3  and the vertical driving unit  5  on the basis of an input address. 
         [0032]    The control unit  4  includes an address decoder  22  and the clock control circuit  26 . 
         [0033]    The clock control circuit  26  outputs a timing signal for controlling each circuit in accordance with inputting of a clock from the outside. 
         [0034]    The address decoder  22  generates head addresses in the vertical direction and the horizontal direction in accordance with an address signal from the outside, and supplies the same to the row scan shift register  23  and a column scan shift register  24 . 
         [0035]    The vertical driving unit  5  drives the bit line BL provided in the pixel array unit  2 . 
         [0036]    The vertical driving unit  5  includes the column scan shift register  24  and a column selection circuit  27 . 
         [0037]    The column scan shift register  24  generates a column address that is sequentially shifted from a head address in the horizontal direction in accordance with the timing signal from the clock control circuit  26 , and drives the bit line BL corresponding to the column address in the pixel array unit  2 . 
         [0038]    The column selection circuit  27  includes a data line DL, transistors RS 0  and RS 1 , transistors YS 0  and YS 1  (referred to as a transistor YS in some cases), and capacitors C 0  and C 1  (generally referred to as a capacitor C in some cases). 
         [0039]    The transistors RS 0  and YS 0  are coupled to each other in series between the bit line BL 0  and the data line DL. 
         [0040]    The transistors RS 1  and YS 1  are coupled to each other in parallel with the transistors RS 0  and YS 0  and are coupled to each other in series between the bit line BL 1  and the data line DL. 
         [0041]    The capacitor C 0  is provided between a fixed voltage and a coupling node that is provided between the transistors RS 0  and YS 0 . 
         [0042]    The capacitor C 1  is provided between a fixed voltage and a coupling node that is provided between the transistors RS 1  and YS 1 . 
         [0043]    The transistors RS 0  and RS 1  become conductive in accordance with inputting of a control signal RS, and electrically couple the bit lines BL 0  and BL 1  to the capacitors C 0  and C 1 , respectively. Accordingly, electric charges on the basis of photoelectric conversion voltages are accumulated into the capacitors C 0  and C 1  through the bit lines BL 0  and BL 1 . 
         [0044]    The transistor YS 0  becomes conductive in accordance with inputting of a column selection signal YST 0 , and electrically couples the capacitor C 0  to the data line DL. 
         [0045]    The transistor YS 1  becomes conductive in accordance with inputting of a column selection signal YST 1 , and electrically couples the capacitor C 1  to the data line DL. 
         [0046]    The column scan shift register  24  sequentially activates and shifts the column selection signal YST. Accordingly, the voltage on the basis of the electric charge of the capacitor C accumulated in accordance with the photoelectric conversion voltage of the unit pixel P is output to the data line DL. 
         [0047]    Reset signals RST 0  and RST 1  are sequentially supplied from the row driver  25  in the beginning of an operation cycle, so that photodiodes are charged in the unit pixels P 1  to P 4 . Next, exposure is performed by turning off the reset signals, and each word line WL is sequentially supplied after an arbitrary period of time, so that the amplified photoelectric conversion voltage of the unit pixel P is output to the bit lines BL 0  and BL 1 . Further, the transistors RS 0  and RS 1  are turned on by supplying the control signal RS, so that the signal voltages of the bit lines BL 0  and BL 1  are held in capacitors C 0  and C 1 , respectively. 
         [0048]    Next, the transistors RS 0  and RS 1  are turned off, and the transistors YS 0  and YS 1  are turned on by supplying the column selection signals YST 0  and YST 1 , so that the signal voltages held in the capacitors C 0  and C 1  are sequentially output. 
         [0049]    The amplifier  30  amplifies and outputs the voltage of the data line DL. 
         [0050]      FIG. 2  is a diagram for explaining a configuration of each unit pixel. 
         [0051]    As shown in  FIG. 2 , a configuration of the unit pixel P (sensor element) is shown. 
         [0052]    In the example, the unit pixel P is configured using an N-channel transistor. 
         [0053]    The unit pixel P in the example includes a transistor  11  for resetting, a transistor  12  for amplifying, a transistor  13  for outputting to the bit line, a photodiode  14 , and a current source  15 . In the example, the transistor  12  and the transistor  13  are enhancement-type transistors. However, the transistor  11  is a depression-type transistor. 
         [0054]    The transistor  11  is coupled between a power supply voltage VDD and the photodiode  14 . The gate of the transistor  11  is coupled to the reset line RST. 
         [0055]    The transistors  12  and  13  are coupled to each other in series between the power supply voltage and the bit line BL. 
         [0056]    The gate of the transistor  12  is coupled to an inner node between the transistor  11  and the photodiode  14 . 
         [0057]    The gate of the transistor  13  is coupled to the word line WL. 
         [0058]    When the reset line RST becomes the “H” level, the transistor  11  supplies the power supply voltage VDD to the photodiode  14 , and thus resets to a beginning state of the photoelectric conversion operation. 
         [0059]    The transistor  12  forms a source follower together with the current source  15 , and amplifies the photoelectric conversion voltage of the photodiode  14 . 
         [0060]    When the word line WL becomes the “H” level, the transistor  13  is turned on, and allows the transistor  12  to be coupled to the current source  15  through the bit line BL. The photodiode  14  generates a photoelectric conversion voltage in accordance with a light input level. Further, when the transistor  13  is turned on, the current source  15  supplies a current to the transistor  12  to operate as a source follower. 
         [0061]    An operation of the unit pixel P in the example will be described. 
         [0062]    In an unexposed state, the transistor  11  is activated in accordance with the reset line RST, and the photodiode  14  is initialized by being charged to the power supply voltage VDD. Then, the exposure of the photodiode  14  is started. 
         [0063]    The photoelectric conversion voltage generated in the photodiode  14  in accordance with an input light level by the photoelectric effect of the photodiode  14  on the basis of inputting of light is amplified by the transistor  12  forming a source follower in accordance with the transconductance thereof. Then, the word line WL is activated after an arbitrary period of time to allow the transistor  13  to become conductive. 
         [0064]    Then, the signal amplified by the transistor  12  is output to the bit line BL. 
       B. Explanation of Operation&gt; 
       [0065]      FIG. 3  is a diagram for explaining a timing chart of the imaging device  1  on the basis of the first embodiment. 
         [0066]    In the example, the unit pixel P 1  will be described. 
         [0067]    As shown in  FIG. 3 , the word line WL 0  is selected (“H” level) at time T 0 . Accordingly, each unit pixel corresponding to the word line WL 0  is selected. Then, the photoelectric conversion voltage generated in the unit pixel P 1  corresponding to the word line WL 0  is output to the bit line. 
         [0068]    Further, the control signal RS is set at the “H” level, and the photoelectric conversion voltage is stored into the capacitor C. 
         [0069]    A photoelectric conversion voltage Vsig stored in the capacitor C is output after being amplified by the amplifier  30  through the data line DL. 
         [0070]    The control signal RS is set at the “L” level at time T 1 , and a transistor RS provided between the bit line BL and the capacitor becomes a non-conductive state. 
         [0071]    The reset line RST 0  is activated to the “H” level at time T 2 . Accordingly, the unit pixel corresponding to each word line WL 0  is reset to a beginning state of the photoelectric conversion operation. 
         [0072]    The control signal RS is set at the “H” level at time T 3 . Further, the word line WL 0  is in the selected state at time T 3 . Thus, the electric charge in a beginning state of the photoelectric conversion operation immediately after reset is stored into the capacitor C. 
         [0073]    A photoelectric conversion voltage Vref stored in the capacitor C is output after being amplified by the amplifier  30  through the data line DL. 
         [0074]    Then, the photoelectric conversion voltages Vsig and Vref are processed in the subsequent circuits. The process is a noise removal process. As an example of the noise removal process, a CDS (Correlated Double Sampling) process is performed. 
         [0075]    The control signal RS is set at the “L” level at time T 4 . Further, the word line WL 0  becomes the unselected state (“L” level). 
         [0076]    The subsequent processes are the same. 
         [0077]    Signals on the basis of the photoelectric conversion voltages generated in the unit pixels of the same row can be obtained by the process. 
         [0078]    It should be noted that detailed explanation of the operation of the column scan shift register  24  is omitted in the example. However, the column selection signal YST is sequentially activated, and is shifted in the column direction, so that the photoelectric conversion voltage of each unit pixel is read. 
         [0079]      FIG. 4  is a diagram for explaining an image on the basis of image data imaged by the imaging device  1  on the basis of the first embodiment. 
         [0080]      FIG. 4  shows an example of an image displayed on a display unit (not shown) as an example. 
         [0081]    Specifically,  FIG. 4  shows a case in which first image data on the basis of the photoelectric conversion voltage generated in each unit pixel of the pixel array unit  2  is stored into the memory, and is displayed on the display unit. A portrait image is shown as an example. The first image data is based on data of all the unit pixels of the pixel array unit  2 . 
         [0082]    On the other hand, the imaging device  1  in the first embodiment outputs second image data that is different from the first image data. Specifically, the imaging device  1  outputs differential data between the unit pixels that are adjacent to each other. 
         [0083]      FIG. 5  is a schematic view in the case where the differential data on the basis of the first embodiment is output. 
         [0084]    As shown in  FIG. 5 , the differential data of the photoelectric conversion voltages between the unit pixels P 1  and P 3  that are adjacent to each other in the same column is output in the example. 
         [0085]      FIG. 6  is a diagram for explaining another timing chart of the imaging device  1  on the basis of the first embodiment. 
         [0086]    In the example, the unit pixels P 1  and P 3  will be described. 
         [0087]    As shown in  FIG. 6 , the word line WL 1  is selected (“H” level) at time T 10 . Accordingly, each unit pixel corresponding to the word line WL 1  is selected. Then, the photoelectric conversion voltage generated in the unit pixel P 3  corresponding to the word line WL 1  is output to the bit line. 
         [0088]    Further, the control signal RS is set at the “H” level, and the photoelectric conversion voltage is stored into the capacitor C. 
         [0089]    A photoelectric conversion voltage Vsig 1  stored in the capacitor C is output after being amplified by the amplifier  30  through the data line DL. 
         [0090]    The control signal RS is set at the “L” level at time T 11 , and the transistor RS provided between the bit line BL and the capacitor becomes a non-conductive state. 
         [0091]    The reset line RST 1  is activated to the “H” level at time T 12 . Accordingly, each unit pixel corresponding to the word line WL 1  is reset to a beginning state of the photoelectric conversion operation. 
         [0092]    The word line WL 0  is selected (“H” level) at time T 13 . Accordingly, the photoelectric conversion voltage generated in the unit pixel P 1  corresponding to the word line WL 0  is output to the bit line. 
         [0093]    Further, the control signal RS is set at the “H” level, and the photoelectric conversion voltage is stored into the capacitor C. 
         [0094]    A photoelectric conversion voltage Vsig 0  stored in the capacitor C is output after being amplified by the amplifier  30  through the data line DL. 
         [0095]    Then, the photoelectric conversion voltages Vsig 1  and Vsig 0  are processed in the subsequent circuits in accordance with the method same as above. Data obtained by the process is the differential data between the unit pixels that are adjacent to each other. 
         [0096]    The control signal RS is set at the “L” level at time T 14 . Further, the word line WL 0  becomes the unselected state (“L” level). 
         [0097]    The subsequent processes are the same. 
         [0098]    The differential data of the photoelectric conversion voltages generated in the unit pixels that are adjacent to each other in the same column can be obtained by the process. 
         [0099]    It should be noted that detailed explanation of the operation of the column scan shift register  24  is omitted in the example. However, the column selection signal YST is sequentially activated, and is shifted in the column direction, so that the data can be obtained in accordance with the same method. 
         [0100]      FIG. 7  is a diagram for explaining an image on the basis of different image data imaged by the imaging device  1  on the basis of the first embodiment. 
         [0101]      FIG. 7  shows an example of an image displayed on a display unit (not shown) as an example. 
         [0102]    Specifically,  FIG. 7  shows a case in which second image data on the basis of the photoelectric conversion voltages generated among the unit pixels of the pixel array unit  2  is stored into the memory  8 , and is displayed on the display unit. Outline parts of contrast of a portrait image is shown as an example. The second image data is differential data of the photoelectric conversion voltages generated between the unit pixels that are adjacent to each other in the same column in the pixel array unit  2 . In the case where the photoelectric conversion voltages of the unit pixels that are adjacent to each other are compared with each other, data at a position where the contrast largely differs can be obtained as the differential data. 
         [0103]    Unlike the first image data on the basis of the photoelectric conversion voltages generated in all the unit pixels of the pixel array unit  2 , the second image data that is the differential data on the basis of a comparison result of the photoelectric conversion voltages of the unit pixels that are adjacent to each other in the same column can be generated by the method on the basis of the first embodiment. In addition, the image data stored into the memory can be significantly compressed by storing the second image data into the memory. 
         [0104]    It should be noted that the differential data representing the outline parts of contrast of the portrait image can be used to recognize a person by a well-known image process, and the processing load of an application (application for image verification or the like) to be used can be reduced. 
         [0105]    It should be noted that the second image data is generated on the basis of the differential data between the unit pixels that are adjacent to each other in the same column in the above description. However, the embodiment is not particularly limited to this, but the second image data can be generated on the basis of the differential data between the unit pixels that are adjacent to each other in the same row. 
         [0106]    The image data stored into the memory can be significantly compressed by the method. 
       Second Embodiment 
       [0107]    In a second embodiment, a method of compressing image data of a plurality of frames will be described. Specifically, the number of frames of image data is counted up, and a process is switched in accordance with the number of frames in the second embodiment. 
         [0108]      FIG. 8  is a functional block diagram for showing an entire configuration of an imaging device  1 # on the basis of the second embodiment. 
         [0109]    As shown in  FIG. 8 , the imaging device  1 # on the basis of the second embodiment is different from the imaging device  1  described using  FIG. 1  in that functional blocks of a read unit  6 , a memory  8 , an output control unit  7 , and a display unit  9  are further added to the functional blocks of the imaging device  1 . 
         [0110]    The read unit  6  includes an amplifier  30 , and stores image data read from the pixel array unit  2  into the memory  8 . 
         [0111]    The output control unit  7  reads the image data stored in the memory  8  in accordance with an instruction from the control unit  4 , and outputs the same to the display unit  9 . 
         [0112]    The control unit  4  counts the number of frames of the image data read from the pixel array unit  2 , and executes a predetermined image process on the basis of the count result. 
         [0113]    Specifically, the image data of a predetermined frame number is stored into the memory  8 , as it is, as first image data, and the image data up to a predetermined frame number is stored into the memory  8  as compressed second image data. 
         [0114]    For example, the image data of the first frame is stored, as it is, into the memory  8  as the first image data. In the case of the image data of the second to fourth frames, the second image data that is differential data is stored into the memory  8 . Further, the image data of the fifth frame may be stored, as it is, into the memory  8  as the first image data. Thereafter, the image data is stored in accordance with the same method. 
         [0115]      FIG. 9  shows an example of images that can be displayed on the display unit  9  on the basis of the image data stored in the memory  8  on the basis of the second embodiment. 
         [0116]    As shown in  FIG. 9 , in the case of a first frame M 1 , the first image data on the basis of the photoelectric conversion voltages generated in the unit pixels of the pixel array unit  2  is stored into the memory  8 . As an example, a portrait image is shown. The first image data is based on the data of all the unit pixels of the pixel array unit  2 . In the case of a second frame M 2 , the second image data on the basis of the differential data of the photoelectric conversion voltages generated in the unit pixels that are adjacent to each other in the pixel array unit  2  is stored into the memory  8 . In the case of a third frame M 3 , the second image data on the basis of the differential data of the photoelectric conversion voltages generated in the unit pixels that are adjacent to each other in the pixel array unit  2  is stored into the memory  8 . In the case of a fourth frame M 4 , the second image data on the basis of the differential data of the photoelectric conversion voltages generated in the unit pixels that are adjacent to each other in the pixel array unit  2  is stored into the memory  8 . In the case of a fifth frame M 5 , the first image data on the basis of the photoelectric conversion voltages generated in the unit pixels of the pixel array unit  2  is stored into the memory  8 . As an example, a portrait image is shown. 
         [0117]    The compressed data can be stored into the memory  8  by the method because the image data of the second to fourth frames is the differential data. 
         [0118]    Thus, the image data stored into the memory  8  can be significantly compressed. 
         [0119]    Further, the deterioration of the images can be suppressed by storing the first image data into the memory  8 , as it is, on a predetermined frame number basis. 
         [0120]      FIG. 10  is a flowchart for explaining a compression method of image data on the basis of the second embodiment. 
         [0121]      FIG. 10  shows a process mainly performed by the control unit  4 . 
         [0122]    As shown in  FIG. 10 , the control unit  4  determines whether or not an imaging process is performed (Step S 0 ). 
         [0123]    In the case where it is determined that the imaging process is performed in Step S 0  (YES in Step S 0 ), the number of frames is counted up (Step S 1 ). It is assumed that a counter (not shown) that counts the number of frames is provided. The initial value is 0. 
         [0124]    Next, the control unit  4  confirms the number of frames in Step S 1  (Step S 2 ). The control unit  4  confirms the count value of the counter. 
         [0125]    Next, the control unit  4  determines whether or not the image data is of a predetermined frame number (Step S 4 ). In the description of the example, the predetermined frame number is set at 1. The control unit  4  confirms the count value of the counter, and determines whether or not the frame number of the image data read from the pixel array unit  2  is 1. It should be noted that the value of the predetermined frame number can be set at an arbitrary value. 
         [0126]    Next, in the case where it is determined that the image data is of the predetermined frame number, the control unit  4  instructs to output full image data to the memory  8  (Step S 6 ). In the case where it is determined that the image data is of the first frame, the control unit  4  executes the read process in accordance with the method described in  FIG. 3 , and outputs the full image data from the read unit  6  to the memory  8 . 
         [0127]    Next, the control unit  4  determines whether or not the process has been completed (Step S 8 ). 
         [0128]    In the case where the control unit  4  determines that the process has been completed in Step S 8  (YES in Step S 8 ), the process is finished (end). 
         [0129]    On the other hand, in the case where the control unit  4  determines that the process has not been completed in Step S 8  (NO in Step S 8 ), the flow returns to Step S 0  to repeat the above-described process. 
         [0130]    In the case where it is determined that the image data is of not the predetermined frame number in Step S 4  (NO in Step S 4 ), the control unit  4  instructs to output differential image data (Step S 10 ). In the case where it is determined that the image data is of not the predetermined frame number, the control unit  4  executes the read process in accordance with the method described in  FIG. 6 , and outputs the differential data of the photoelectric conversion voltages generated in the unit pixels that are adjacent to each other from the read unit  6  to the memory  8 . 
         [0131]    Next, the control unit  4  determines whether or not the frame number is equal to or larger than P (Step S 12 ). As an example, P is set at 4 in the example. 
         [0132]    In the case where it is determined that the frame number is equal to or larger than P in Step S 12  (YES in Step S 12 ), the control unit  4  resets the value of the counter (Step S 14 ). The value is set at 0 as the initial value. 
         [0133]    Then, the flow proceeds to Step S 8 . 
         [0134]    On the other hand, in the case where it is determined that the frame number is smaller than P in Step S 12  (NO in Step S 12 ), the control unit  4  does not reset the value of the counter, and the flow process to Step S 8 . Then, the above-described process is repeated. 
         [0135]    As the image data of the first frame, the full image data is stored into the memory  8  by the process. On the other hand, as the image data of the second to fourth frames, the differential image data is stored into the memory  8 . After the image data of the fourth frame, the value of the frame number is set at 0. As the image data of the next frame number, the full image data is stored into the memory  8 . The above-described process is repeated. 
         [0136]    Thus, the image data of a plurality of frames to be stored into the memory  8  can be significantly compressed. It should be noted that the process can be applied to both of the image data of a still image and the image data of a video. 
       Modified Example 
       [0137]      FIG. 11  is a diagram for explaining a configuration of a unit pixel on the basis of a modified example. 
         [0138]    As shown in  FIG. 11 , the configuration of the unit pixel on the basis of the modified example is different from that of the unit pixel in  FIG. 2  in that a transistor  16  is added. The transistor  16  is coupled between the photodiode  14  and the transistor  11 , and the gate thereof accepts an input of a control signal TG. The other configurations are the same as those described in  FIG. 2 , and thus the detailed explanation thereof will not be repeated. 
         [0139]    The transistor  16  always separates the photodiode  14  from a coupling point between the source of the transistor  11  and the gate of the transistor  12 . When a gate signal TG becomes the high level, the transistor  16  is turned on, and couples the photodiode  14  to the coupling point. 
         [0140]    An operation of the unit pixel in the example will be described. 
         [0141]    In an unexposed state, the transistor  11  is activated by the reset signal RST, and the transistor  16  is activated by the gate signal TG. The photodiode  14  is initialized by being charged to the power supply voltage VDD. Then, the exposure of the photodiode  14  is started in a state where the photodiode  14  is separated from the source of the transistor  11  by turning off the gate signal TG. After an arbitrary period of time, the transistor  16  is activated again by the gate signal TG, and the photoelectric conversion voltage generated in the photodiode  14  in accordance with an input light level by the photoelectric effect of the photodiode  14  on the basis of inputting of light is read to a temporary memory unit  17  formed by the gate capacity of the transistor  12 . Then, the photodiode  14  is separated from the temporary memory unit  17  by turning off the gate signal TG. Then, the voltage held in the temporary memory unit  17  is amplified by the transistor  12  forming a source follower in accordance with the transconductance gm thereof. Then, the signal amplified by the transistor  12  is output to the bit line BL by activating the transistor  13  in accordance with the word line WL. 
         [0142]    The configuration same as above can be realized even in the unit pixel. It is obvious that the configuration of the unit pixel is not limited to the above-described configuration, but the other configurations can be employed. 
         [0143]    The disclosure has been described above in detail on the basis of the embodiments. However, it is obvious that the disclosure is not limited to the embodiments, but can be variously changed without departing from the scope thereof.