Abstract:
The present invention reveals a method for manufacturing identification codes of integrated circuit. A number of the test machine, a serial number and a period of time ahead of loading a test pattern are written into an integrated circuit in the process of testing as the identification code. Thus, the identification codes of each integrated circuit of normal lot, re-testing lot and quality control lot is distinct to avoid the problems caused by repetitive identification codes.

Description:
BACKGROUND OF THE INVENTION 
     A. Field of the Invention 
     The present invention relates to a method for manufacturing identification codes of integrated circuits, and more specifically, to an automatic method for manufacturing identification codes of integrated circuits. 
     B. Description of Related Art 
     Almost all of the integrated circuits (ICs), such as those applied in a hard disk, a portable flash disk and a handset, etc., contain their own identification codes. If two hard disks or portable flash disks with the same identification code are simultaneously plugged into a personal computer, they will confuse the central processor unit (CPU) and cause a crash. Further, if the identification codes on the SIM cards of two handsets are the same, it will also result in communication problems. 
     Generally, writing an identification code into an IC is manually done with a module or a writer. This step alone takes more than 10 seconds for each IC, which is a waste of time and labor, and also may easily cause an inattentive error. 
     A normal wafer testing process is shown in FIG.  1 . After testing for a whole lot of normal wafers, the passed wafers are sample-tested with the following quality control (QC) test and shipped out afterward, so as to prevent un-inspected defective products from the normal lot testing or improper locations of wafers deposited by people. The wafers that do not pass the testing will be re-tested, among which the passed ones will go through the same process before shipping, and the rest will be scrapped. The conventional manner of the use of serial numbers for writing ICs would not cause any problem for the employment of normal lot testing along, i.e., each IC has its own identification code (serial number). But, if wafers of a lot are conducted with a re-testing or a QC test, the serial number is reset to zero at the initialization of the lot testing, and the serial numbers written on the ICs are possibly repeated, causing the problems of repetitive identification codes. 
     SUMMARY OF THE INVENTION 
     The object of the present invention is to prevent each IC from having the same identification code and causing confusion during the IC operation and even resulting in a tool crash or system paralysis. Moreover, the present invention can be automated to avoid manual inattention and reduce labor cost. 
     The present invention uses a test machine to write the number of test machine, a period of time ahead of loading a test pattern and a serial number into each IC. The present invention can ensure that the written identification code of each IC is distinct to avoid the identification problems. 
     The manufacturing method of identification codes for ICs of a preferred embodiment according to the present invention includes the following steps: (a) a first pattern is produced, which comprises the data of the number of a test machine for testing ICs and a period of time ahead of loading a testing pattern into the test machine; (b) a second pattern is produced, which comprises the data of serial numbers and their corresponding addresses; (c) a serial number of the second pattern for one of the ICs is extracted based on the corresponding address; and (d) the number of the test machine, the period of time ahead of loading the testing pattern and the serial number are written into the IC specified by the corresponding address as the identification code. 
     The above-mentioned first pattern for being extracted by the test machine and written into the ICs can be formed in the way of extracting and converting the number of the test machine and the time by a program, such as a perl language. The second pattern can be one large enough for supplying all the serial numbers required by the ICs of a whole lot of wafers to save the time of repetitive pattern loading for each of the ICs. Before the testing of each lot of wafers or the testing of the same lot of wafers for the normal lots, re-testing lots and quality control lots, the serial numbers of them need to be reset to zero. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a known wafer testing process; 
     FIG. 2 illustrates the method for manufacturing identification codes of integrated circuits in accordance with the present invention; and 
     FIG. 3 illustrates the serial number pattern in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     If two test machines conduct IC testings simultaneously, the period of time ahead of loading a test pattern and the serial number of the IC for each test machine might be repeated, but the number of the test machine of that is definitely different. Referring back to FIG. 1, on a same test machine and in a same testing block (i.e. the normal lot testing, re-testing or QC testing), the written machine number and the period of time ahead of loading a test pattern of each IC are the same, but the serial number of that is different. And among different testing blocks, the number of the test machine and the serial number written into an IC might be the same, but the period of time ahead of loading a test pattern of that is definitely different. Thus, the present invention employs the writing the number of the test machine, the period of time ahead of loading a test pattern and the serial number as the identification code for an IC, so that it can effectively prevent repetition of the identification codes of ICs. 
     Referring to FIG. 2, the embodiment employs the perl language to convert the number of the test machine  21  and a period of time ahead of loading a test pattern  22  into a first pattern  24  containing the number of the test machine  21  and the period of time ahead of loading the test pattern  22 . Furthermore, a second pattern  25  containing serial numbers  23  is produced. Then, the first pattern  24  can be loaded into a test machine  26  together with the second pattern  25  and the test pattern (not shown), providing the test machine  26  to extract the data of the number of the test machine  21 , the time  22  and the serial numbers  23  and to be written into the ICs as the identification codes and for IC testing. The error between the time ahead of loading the test pattern  22  and the real loading time of the first pattern  24  converted from that is less than 0.5 second, which can almost be neglected. The format of the period of time ahead of loading a test pattern  22  may use the difference between the time ahead of loading the test pattern (i.e. the absolute time) and a time reference, for example at 00:00, Jan. 1, 2001, such that the number of minutes passed is used as the time data for the following produced patterns. Therefore, the number of bits required for storing the time data in the pattern is smaller, which can effectively save the resource. 
     Referring to FIG. 3, the writing method of the serial numbers  23  can use a large serial number pattern  31  as the second pattern  25  for the use of ICs in a whole lot of wafers in order to prevent re-loading patterns during writing each IC and waste of time. The embodiment stores serial numbers in the data field with each row in 8-bit capacity. The serial numbers for count — 1 to count — 4 (differentiated by the data in the address field) are zero, and the serial numbers for count — 5 to count — 8 are 1, and the serial numbers for count — 9 to count — 12 are 2, and so on. A main program is used to control the extraction for the serial numbers based on the address. For example, the serial numbers for count — 1 to count — 4 are written into the first IC, the serial numbers for count — 5 to count — 8 are written into the second IC, the serial numbers for count — 9 to count — 12 are written into the third IC, and so on. In addition to saving the loading time, the large serial number pattern  31  of the present invention can effectively control the required written block by using a main program to control the variables of a start address and a stop address of the counts of the block. For example, the number of required serial numbers of a lot of 25 wafers, each wafer comprises more than 300 dies, is approximately 7,500 to 10,000. The large serial number pattern  31  in this example can provide a capacity of four 8-bit for the counts to each IC (32 bits in total), which is obviously sufficient for the requirement of the whole lot of wafers and also quite enough to be applied in a larger, 12-inch wafer. 
     Moreover, in the practical application, some test machines of the same brand are connected with each other and use the same first pattern  24 . These test machines are set to re-extract the first pattern  24  in the operation. Thus, if one of the test machines is under testing, another test machine connected therewith conducts the testing afterward so as to change the first pattern  24 . The first test machine may use the first pattern  24  produced from the second test machine, so that it will result in the same identification codes being written into the ICs, respectively. To solve the problem, it may provide the first pattern  24  with a machine number related name whenever the first pattern  24  is generated. For example, the first pattern  24  generated by the No.1 test machine is named “test1-pattern” and the first pattern  24  generated by the No.2 test machine is named “test2-pattern.” Then a program is employed to control the selection of “test1-pattern” for the testing of the No.1 test machine and “test2-pattern” for the testing of the No.2 test machine to prevent generating the repetitive identification codes caused by extracting the machine number non-related to the test machine. 
     The present invention can use a main program for automatic operation to simultaneously control the making of the first pattern and the second pattern of the normal lots, re-testing lots and QC lots and write the data of an identification code into each IC, respectively, reducing the labor cost and manual defects. 
     The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the scope of the following claims.