Abstract:
Synchronous programs give increased sampling rates of AC signals and provide AC phasors yielding fast response to undesired conditions.

Description:
This application claims the priority date of provisional patent application Ser. No. 60/089,271 filed on Jun. 15, 1998. 
    
    
     BACKGROUND OF THE INVENTION 
     It is the present practice of a Beckwith Electric Company line of generator and transformer protective relays to sample alternating current (AC) voltage and current waves some small number of times, such as 16 per cycle, and then use Fourier transforms to compute phasor quantities representing fundamental components of the waves. 
     Reference is made to the following book and articles on the present related state of the art: 
     [1] Phadke, A. G. and J. S. Thorp, Computer Relaying for Power Systems, John Wiley and Sons, New York, 1988, pp. 123-129. 
     [2] Hector J., Altuve F., Ismael Diaz V. and Ernesto Vazquez M., “Fourier and Walsh digital filtering algorithms for distance protection”, IEEE Transactions on Power, vol. 11, No. 1, February 1996, pp. 457-462. 
     [3] Harlow, J. H., “A multifunction protective relay for the cogeneration industry”, IEEE Computer Application in Power, vol.3, No.4, 1990, pp.25-30. 
     [4] Yalla, Murty V. V. S., “A digital multifunction protective relay”, IEEE Transactions on Power Delivery, vol.7, No.1, 1992, pp.193-201. 
     Making use of inventions as found in U.S. Pat. No. 5,224,011, MULTIFUNCTION PROTECTIVE RELAY, one typical product, model M-4320 manufactured by the Beckwith Electric Company, uses a digital signal processor (DSP) running at some 80 megabits per second, to compute Fourier transforms of the waves as digital samples are taken. The results are fed to a dual ported random access memory where they are available to a host processor. The host processor, operating at 10 megabits per second, uses the results to compute the existence of electrical fault conditions and to output commands for tripping circuit breakers so as to quickly remove electric power feeding faults. 
     In the M-4320 it is necessary to use analog component anti-aliasing filters to prevent errors due to problems introduced by the use of a small number of digital samples of the AC wave. Since the electronic circuit is connected to earth ground, transformers must be used for all current and voltage inputs. 
     Another Beckwith Electric Company product line makes use of inventions contained in U.S. Pat. No. 4,310,771 METHODS FOR TRANSFERRING POWER IN A SYNCHRONOUS MODE TO A MOTOR BUS, U.S. Pat. No. 4,256,972 POWER TRANSFER RELAY and U.S. Pat. No. 4,311,919 TRANSFER LOGIC CONTROL CIRCUITRY. 
     In products based on the above referenced U.S. Pat. Nos. 4,310,771, 4,256,972 and 4,311,919 a first analog device is used to develop information useable for the transfer of a motor bus from a first source to a second source, not necessarily in phase with the first, in a sequence of criteria. A second combined analog and digital device uses the information to effect the transfer. Use of these devices results in a large and expensive combination of equipment. 
     The transfer of motor busses is sometimes made manually for operating reasons. At other times the transfer may be initiated automatically due to the failure of a bus presently in use. 
     The first criterion used is called the “fast transfer” and operates if calculations indicate that the transfer can be completed while the phase angle between the two sources is within a selected phase angle window. The second criterion first separates the motors from the first source and then makes a synchronous transfer when the isolated motor bus falls behind the second source by 360 degrees. The third criterion of transfer is used if the motor bus voltage falls below a selected value before the 360 degree point is reached. 
     While a bus transfer device does not have the requirement to trip a circuit breaker in order to interrupt a fault current, it is classified herein as a protective device since proper operation does protect equipment from damage. In addition, as in protective relays that detect fault conditions, its operation likewise depends on a cycle by cycle measurement of voltage and current waves. 
     In making improvements over the present art, use is made herein of the following inventions, all by the present inventor, Robert W. Beckwith. 
     A) U.S. Pat. No. 5,315,527, METHOD AND APPARATUS PROVIDING HALF-CYCLE DIGITIZATION OF AC SIGNALS BY AN ANALOG-TO-DIGITAL CONVERTER, describes apparatus and methods for sensing positive half cycles of AC signals. 
     B) U.S. Pat. No. 5,544,064, APPARATUS AND METHOD FOR SAMPLING SIGNALS SYNCHRONOUS WITH ANALOG-TO-DIGITAL CONVERTER, describes apparatus and methods useful for obtaining digital samples of AC waves synchronous with free running analog to digital converters (ADCs). 
     C) U.S. Pat. No. 5,774,366, A METHOD FOR OBTAINING THE FUNDAMENTAL AND ODD HARMONIC COMPONENTS OF AC SIGNALS, describes methods for obtaining the fundamental component and odd harmonics of half wave AC signals. 
     D) U.S. patent application Ser. No. 710,816, TWO WAY PACKET RADIO INCLUDING SMART DATA BUFFER AND PACKET RATE CONVERSION, the inventer herein, filed on Sep. 23, 1996 describes apparatus and methods of communicating synchronously with the power frequency as useful in the present invention. 
     The present invention combines use of the half wave technology of U.S. Pat. No. 5,315,527 together with the synchronous linear technology of U.S. Pat. No. 5,544,064 and methods for obtaining the fundamental component and odd harmonics of a half wave AC signal of U.S. Pat. No. 5,774,366 in reducing the hardware and software requirements while at the same time increasing the operating speed of devices useful in AC electric power apparatus. Means of communicating between devices using the present invention and any of the many protocols in use at the time of writing of this application are provided by the inventive means and methods by reference U.S. patent application Ser. No. 710,816. 
     U.S. Pat. No&#39;s. 5,315,527, 5,544,064, 5,774,366 and U.S. patent application Ser. No. 710,816 are incorporated herein by reference. 
     SUMMARY OF THE INVENTION 
     This invention utilizes tables of sine and cosine functions multiplied by digital samples of AC waves to obtain, by cross correlation, the values of phasors for the waves, thus eliminating the need for Fourier transform calculations required in many prior art devices. These phasors are obtained one or more times per cycle of AC voltage and current waves in order to determine output requirements, generally in the form of operation of solid state switches. 
     In a first microprocessor, linear programs, using fixed operating time loops, operate synchronously with microprocessor ADCs. These ADCs produce digital samples in matching loops and require no ongoing instructions from the linear programs. A second microprocessor obtains the phasor information via a high speed synchronous data bus from the first microprocessor and computes results such as fault clearing and motor bus transfer conditions. Use of linear programs loops matching those of the first microprocessor avoids data clashes between the two microprocessors. Both microprocessor programs run continuously without the use of interrupts. 
     Functions of the two microprocessors are combined into one microprocessor for protection of single phase equipment and for motor bus transfer. 
     Examples are given for use of the invention. 
    
    
     BRIEF DESCRIPTIONS OF THE DRAWINGS 
     FIG. 1 shows relations between four quadrants of phasors. 
     FIG. 2 shows combination of monopolar ADC inputs with logic inputs to determine four quadrant phasors. 
     FIGS. 3 a  and  3   b  illustrates a basic circuit for three phase protective relays having three voltage and three current inputs. 
     FIG. 4 illustrates a circuit with three voltage inputs useful for motor bus transfer applications. 
     FIG. 5 shows single phase inventive protective relay circuitry using “smart” three terminal fuses to interrupt currents. 
     FIG. 6 shows single phase inventive protective relay circuits using small ground currents to cause ground fault circuit breakers to interrupt currents. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The invention is described hereinunder using presently available semiconductor devices. General principles are first demonstrated and then examples of applications are shown in which selectable designer choices are illustrated. It is anticipated, however, that the general principles of the invention will be applicable using future devices not available at the time of writing of this document. 
     The invention is illustrated using selected Motorola microcontrollers, MC 1  of FIG. 3 a  and MC 100  of FIG. 3 b,  consisting of microprocessors having onboard analog to digital converters (ADC)s. References hereinunder to microprocessors MP means all of MC 1  or MC 100  except for the ADC portions. MC 1  operates synchronously along with MC 100 . MC 100  need not have an ADC, however it is the same device as MC 1  in the illustrative circuits of FIGS. 3 a  and  3   b  since a matching MC without an ADC is not currently available from Motorola. 
     Alternating current (AC) waves, voltage E and current I of FIG. 2, are rectified, shown as AN in FIG. 2, and fed to inputs AN 0  through AN 5  of an ADC preferably located on a microcontroller  1  (MC), see FIG. 3 a.  Further use is made of the nature of a unipolar ADC to act as a nearly perfect rectifier as in described in reference U.S. Pat. No. 5,315,527. A problem introduced by the full wave rectifier is that the polarities of the original E and I waves are lost, as illustrated by wave AN of FIG.  2 . To overcome this loss and to form a true four quadrant phasor detector from the single unipolar ADC input, a squared wave, F in FIG. 2, is created at MC 1  binary inputs F 1  through F 6  of FIG. 3 a.  The square wave identifies positive and negative half cycles of the rectified AC waves. 
     Programs are used in MC 1  based on the inventions contained in U.S. Pat. No. 5,544,064 referenced above. Floating point arithmetic is not used. These programs run continuously using no interrupts. By adding do-nothing steps in program loops written in assembly language, the loop is completed just in time to find a new ADC result in the result register of MC 1 . This provides the highest possible digital sampling rate along with the longest possible computation time between digital samples using any selected MC. 
     The process is illustrated using a Motorola MC68HC16Z1 microcontroller (a microprocessor having an ADC). In reference to the Motorola M68HC16 Family User&#39;s Manual MC68HC16Z1UM/AD, which is incorporated herein by reference, one finds: (The page references below are in the aforesaid Manual.) 
     a) The maximum system clock for the MC68HC16Z1 is 16.78 MHz. Either a crystal (nominal frequency: 32.768 kHz) or an externally generated signal can be used. (Page 1—1). 
     b) The analog-to-digital converter module (ADC) is a unipolar, successive-approximation converter with eight modes of operation. It has selectable 8- or 10- bit resolution. (8- is used in the illustration contained herein). (Page 6.1). 
     The system clock must be divided by an integer number of at least 8 to obtain an ADC clock frequency of 2,097,500 cycles per second. (Rounded off to 2.1 MHz on page 6-14 and elsewhere of said referenced manual MC68HC16Z1UM/AD.) 
     c) As seen on page 6-15 of the referenced manual, an ADC resolution of 8 bits is obtainable using 16 ADC clock cycles conversion time per sample. 
     Note that in reference U.S. Pat. No. 5,315,527, it was found that greater than 8 bit resolution is obtainable from the averaging of errors in the type of ADC used in this selected microcontroller. Eight bit resolution is therefore chosen in the illustrated examples of the inventive concepts given below. 
     d) As seen on page 6-11 of the referenced manual, when the ADC is configured in Mode 6, continuous conversions are performed on each of four sequential input channels. 
     Note that mode 6 is useful when four or less ADC inputs are required. 
     e) As seen on page 6-11 of the referenced manual, when the ADC is configured in Mode 7, continuous conversions are performed on each of eight sequential input channels. 
     Note that mode 7 is useful when from five to eight ADC inputs are required. 
     In Mode 6, conversions in each channel occurs every 16×4 or 64 clock cycles. At a clock frequency of 2.1 MHz the period is 1/2.1 or 0.476 microseconds which multiplied by 64 gives a conversion every 30.5 microseconds. Since a 60 Hz wave has a period of 16,666.6 microseconds, a sample can be made every 16,666.6/30.5=547 digital samples per power frequency cycle. 
     In mode 7 a similar computation gives one half the rate for Mode 6 or 273 digital samples per power frequency cycle. 
     In applications using every ADC result, the microprocessor portion of the MC has 16×8=128 cycles, for addressing the ADC result register and making phasor computations. Selectively, by a designers choice, this number can be increased by a multiplier of 3, giving 384 clock cycles for the sampling and computing time, for applications requiring additional computing time. Increasing by a factor of three causes the digital samples to precess among the inputs so that all are accessed in sequence with intervening digital samples ignored. A factor of five may also be used, further increasing the available computing time but further reducing the number of digital samples per power frequency cycle. 
     Do-nothing steps are added to computation times to make them synchronous with the ADC conversions. 
     The identity of the ADC channels used in the computation is thus inherent in the writing of the microprocessor  1  program and no further addressing means are required. It is necessary, however, to initialize the program so as to identify a chosen channel as a starting point. As a first initializing alternative a clock on board MC 1  is used to reinitialize the computation, say every second, in order to assure proper identity of the digital samples. 
     As a second initializing alternative the computation is reset by the first program after every four channels are computed when in Mode 6 and after every eight channels are computed when in Mode 7. In theory the time taken to reset the program may cause an error in the time sequencing of the digital samples, however the reset is accomplished at the highest MP 1  clock frequency and is so short as to greatly minimize the error. The advantage of this second alternative is that accidental program interruptions by electrical transients are more quickly corrected. 
     The ADC of MC 1  of FIG. 3 a  operates by charging a sampling capacitor to the analog input for two cycles of the ADC clock. At the highest ADC clock frequency of 2.1 MHz this sampling time is approximately two microseconds. This is unchanged by the increase in computation time by use of the aforementioned multipliers of three or five. The response time of potential transformers and current transformers providing the E and I waves must be such that a wave will not change more than the desired amplitude resolution during 2 microseconds. 
     Square waves, F, fed to MC 1  terminals F 1  through F 6 , are high when the corresponding wave is positive and low when they are negative. The sign of any digital sample is determined by sensing the appropriate F input just before a digital sample conversion starts. For example, binary input F 1  is read just before a conversation starts for an input at AN 0 . 
     The Use of Cross Correlation 
     Cross correlations are made between selected digital samples and tables of sine and cosine functions to measure magnitudes of fundamental components of waves and phasors components of related harmonics, said phasors using said fundamental components as phase references. 
     Cross correlation is defined as: 
     
       
           C =(Σ a×b ) ½ /(Σ a   2   +Σb   2 ) ½   
       
     
     Where C is a correlation number and “a” and “b” are functions each represented by a series of digital values. Each sum, Σ, is computed over the range of the values of “a” and “b”. It is generally required that “a” and “b” have the same number of sample values. In the general case “a” is any monotonic function of a variable such as time and “b” is another monotonic function of the same variable. The cross correlation gives the similarity of the two functions for whatever reason. 
     As used herein, functions “a” and “b” are limited to the case of sine waves in time with related harmonics. The denominator is generally not used in this application. 
     In order to minimize the computation time by MP 1  and thereby maximizing the number of samples per cycle, phasor component magnitudes are passed to MC 2  as sums of products. The square roots of these sums are computed in MC 2  producing the real and imaginary components of phasors. Selectively these components are converted to polar form by computing the square root of the squares of the real and reactive terms as the magnitude with an angle whose sine is real component/reactive component. 
     Phasor calculations for various protective relay and motor bus transfer applications are well known and will not be further described herein. Higher level languages may selectively be used in MC 100 , FIG. 3 b.    
     Integrals of digital samples multiplied by sine and cosine functions represented by binary values stored in tables are formed in a sequence lasting 360° of an AC input wave at its nominal frequency. The signs of these integrals determine the polarity of the phasor components. A sum is calculated for one per unit voltage or current sine waves and entered as constants in the program. Division of measured integrals by these constants produces phasors normalized in magnitude to per unit terms. 
     FIG. 3 a  gives examples of circuits used to process three voltage waves along with examples of circuits used to process three current waves. 
     The voltages are shown having a common neutral (N) input connection. External potential transformers (PTs) are used as required for some inputs so as to input to this common connection N. Selectively printed circuit boards for the circuit of FIG. 3 a  use foils largely covering the outer sides of the boards. These are connected together by plated holes and connected externally to neutral. This effectively shields circuitry carried on inner layers of the boards having four or more layers. 
     Digital wave samples are processed by first multiplying each of a series of samples by numbers from a table corresponding to values of a sine function from zero to 360°. The resultant products are summed just following computation. This gives a first sum value with its sign related to the real or P component of a phasor. A second sum is formed in a similar manner using numbers representing 360° of a cosine function and gives a result related to the imaginary or Q component of a phasor. Phasors are thus located in one of the four quadrants of FIG.  1 . 
     It may be most convenient for a programmer to provide a table of alternating sine and cosine values so as to enable computation of the P and Q results in less computation cycles. 
     In some applications, measurement of the third and fifth harmonics of the power frequency may be required. This is provided by multiplying the digital samples by stored tables of the harmonic and summing the result as covered in more detail in reference U.S. Pat. No. 5,774,366. As described in this patent, use of first one and then a second table gives harmonic components 90° apart, thus providing phasors for the harmonics. 
     These phasors are produced in a first MC 1  at a rate of one set for each cycle of the power frequency. These sets of phasors are transferred over the high speed synchronous busses provided by port E of the MC68HC16Z1 as the sums are completed to a second MC 100 , see FIG. 3 b.  This is preferably from the same family of devices as MC 1  except that MC 100  need have no ADC. In practice, however, it is most convenient to use the same device, such as the MC8HC16Z1, for both MC 1  and MC 100 . 
     A program in a second microprocessor contained in MC 100  makes computations using the phasors as inputs so as to determine the desired overall device response to changes in the phasors. Selectively programs for devices  1  and  100  are held in programmable read only memory (ROM) on board each device. Alternatively programs are held in flash memory requiring additional chips and having the advantage of being reprogrammable through communication ports. 
     Local communications is not shown but is furnished using means such as insulated RS232 ports  102  of FIG. 3 b  connectable to portable computers for program entry and for modification and setting of setpoints as required. One alternate method of communications is by two way infra red ports. A second alternate method of communications is by radio as described in U.S. patent application Ser. No. 710,816 referenced above. Any of the three methods provide desirable isolation of the communications inputs and the input connections N. Minimal communications as to the status of devices containing MC 1  and MC 100  is provided by light emitting diodes (LEDs) D 100  through D 101  as selectively activated by input pushbutton switches PB 1  connected from MC 1  binary inputs to neutral Ns (See FIG. 3 b ). 
     It is well known from applications of reference U.S. Pat. No. 5,315,527 that approximately four bits of added resolution in the magnitude of phasor components will be obtained when summing a large number of ADC samples due to cancelling of the errors in the sizes of the capacitors used in the ADC conversion process. With the ADC set for 8 bits resolution, 12 bits resolution are obtained. 
     The resolution is further extended for current waves, if necessary, by program switching of CT burdens R 8  and R 9  using switches  7  and  8  of FIG. 3 a  as driven by binary outputs PC 1  and PC 0  of MC 1 . Additional burdens are selectively included and switched as required by application conditions. Alternatively programmable gain amplifiers (As shown in reference prior art U.S. Pat. No. 5,224,011) can be used in the current signal paths to the ADC with the amplifier gain set by outputs from MC 1 . 
     In order to make most efficient use of the 16 bit processing with the microprocessor used for illustration, the ADC may preferably be set for 8 bit resolution and tables used having 8 bit numbers. This produces 16 bit products most efficiently handled by the 16 bit processor. Multiplying the conversion time of 16 ADC microprocessor clock cycles by the difference of 8 gives 8 * 16 or 128 cycles of computation cycles as the available length of each computation time between digital samples. 
     While phasor results once per cycle may be adequate for selected applications, additional sets may be produced by selectively starting sums at points during computation of the first sum described above. For example, a second set of sums started midway during the computation of the first set of sums provides recognition of phasor changes in one half cycle of the AC waves. Four sets of sums started at quarter cycle intervals provides recognition of phasor changes in one quarter cycle of the AC wave. 
     Power for the circuitry of FIG. 3 a  and FIG. 3 b  is shown as supplied from a 12 Vdc bus with negative terminal common to the equipment neutral bus. Selectively this is a 12 volt lead acid battery with charger. Alternate voltages are 24 and 48 VDC. Alternatively 5 VDC is input from DC/DC converters from station batteries or secure AC control power sources. In such cases, regulator  2  is not used. 
     The inventive protection provides a reduction in size and a reduction in cost over the present art. 
     FIGS. 3 a  and  3   b  illustrate a circuit useful for power generator protection. Details for a device protective of rotating three phase generators follow hereinunder. 
     In FIG. 3 a,  MC 1  has a 5 Vdc power input VDD and return VSS connected to neutral input connection N, binary inputs F 1 , F 2 , F 3 ,F 4 , F 5 , F 6  and F 7 , ADC outputs ANO, AN 1 , AN 2 , AN 3 , AN 4  and AN 5 , binary inputs PC 0 , PC 1 , PC 2 , PC 3 , PC 4  and PC 5 , crystal (XTAL) connections XTAL and EXTAL, clock out (CLK OUT), together with two high speed synchronous data connections DATA. Input direct current power 12 VDC connects to voltage regulator  2  supplying 5 VDC to VDD. Upper ADC voltage limit VRH is provided by precision regulator  3  and lower ADC limit VRH is provided by connection to neutral N. 
     Three phase AC voltages EA, EB and EC each connect to identical signal conditioning circuitry only one of which will be described in detail. EA connects to neutral N via resistors R 2  and R 3  producing signal E of FIG.  2 . Signal E is a voltage chosen not to exceed the linear range of ADC input AN 0 . Resistor R 1  supplies current through diode D 1  sufficiently low as not to effect the regulator  2  output voltage during the positive portion of the cycle of voltage E and through diode D 2  to neutral during the negative portion of the cycle. This produces a square wave voltage into MC input F 1  further sharpened in squareness by the binary nature of the MC 1  input so as to be accurately read by the first synchronous program within MC 1 . Transistors Q 1  and Q 2  form a double emitter follower and gate  13  for positive going analog voltage inputs. One input to this and gate, f+, is formed during the positive portions of voltage E by Resistor R 25  and Diode D 3 . A second input, f−, is from an analog polarity inverter consisting of operational amplifier  10  and resistors R 4  and R 5  forming positive inputs to AN 0  during the negative going portions of voltage E. Circuitry  5  and  6  having inputs EB and EC respectively are exact duplicates of the circuitry having inputs EA and will not be described in further detail. 
     Three phase AC currents IA, IB and IC each connect to identical signal conditioning circuitry only one of which will be described in detail. Currents IA flow through primaries of current transformers (CT) T 1 , entering as current IA and leaving as current IA′. CT T 1  output currents I 1  and I 2  flow serially through resistors R 10  and R 11  with center points of said resistors connected to neutral N. Transistors Q 3  and Q 4  form a double emitter follower “and” gate  13  for positive going analog current inputs AN (of FIG. 2) connected to ADC input AN 3 . Positive portions of currents I 1  flow from neutral N through diodes D 11  and through resistors R 10  forming voltage inputs f+to and gates  13 . Positive portions of currents I 2  flow from neutral N through diodes D 10  and through resistors R 11  forming providing inputs f− to gates  13 . When current I 1  flows through diode D 10  the voltage drop switches the output of operational amplifier  9  from low to high voltage quickly driving binary input F 4  to a high state thus providing an accurate detection of zero crossings of current IA for reading by programs contained in MC 1 . Circuitry  10  and  11  having inputs IB and IC respectively are exact duplicates of the circuitry having inputs IA and will not be described in further detail. 
     Synchronous two way communications is established between MC 1  and MC 100  as shown on FIGS. 3 a  and  3   b.  Since the first program in MC 1  is written by the programmer with full knowledge of the second program which the programmer writes for MC 100 , the programmer plans the programs using a two way communications protocol that avoids data clashes between communications traffic in the two directions. 
     The crystal  12  used to establish the clock rate for MC 1  also provides a CLK OUT signal connected to MC 100  to establish the clock in MC 100  in synchronism with the MC 1  clock. 
     Typical Applications 
     The inventive apparatus and programming methods are useful in three phase protection of rotating generators and power transformers. Because of the lower cost of equipment using the invention, however, typical applications are more likely found in areas not presently served by present practice. Several such uses are described in greater detail hereinunder. 
     Motor Bus Transfer 
     Many motor bus applications, especially at industrial sites, do not justify the higher costs of prior art equipment using U.S. Pat. Nos. 4,310,771, 4,256,972 and 4,311,919 cited hereinabove and simplified inventive devices are applicable. 
     Three sets of voltage inputs are used, one to a motor bus and one each for two alternate sources of power. These two supply busses are referred to as the present bus, “P”, and the next bus, “N”. In general the role of the two supply busses alternates between P and N with each power transfer. 
     Initiation of a motor bus transfer may be manual or may be from the detection of a problem on the P bus. In either case, breakers are opened removing the motors from the P bus. 
     While three phase protective relays require measuring full cycles of voltage and current waves, motor bus transfer relays do not involve determination of fault currents but are initiated by the detection and interruption of motor bus faults and other motor related problems by other equipment. This other equipment then initiates a bus transfer. 
     Costs are reduced by combining phasor measurements in positive half cycles of voltage waves with transfer calculations during negative half cycles. FIG. 4 illustrates a circuit useful in transferring motor busses from one supply to another. 
     The voltage magnitudes of inputs EP (present bus voltage), EM (motor bus voltage) and EN (next bus voltage) are measured during positive half cycles using apparatus and methods described by reference U.S. Pat. No. 5,315,527. The relative times between the three inputs is determined by microprocessor counters measuring times from the first non-zero sample of one wave to the first nonzero sample of another wave. 
     The difference between EP and EM is expected to be zero until a binary signal at IT, from an external protective device, signals initiation of a transfer. This is generally a contact from said protective device which also trips a circuit breaker between the motor bus and the present bus. The change in time between EP and EM is compared to the time between the EP and EN and the time of synchronism of the motor bus and new bus is predicted so as to initiate closing of a breaker between the motor and new bus at an advance time equal to the closing time of the breaker about to be closed. These time predictions are made with use of a model of the nonlinear change in the motor bus speed with time. This type of close is known as “synchronous transfer”. 
     If the determination of EP−EB just after receiving IT is less than a selectable amount, the breaker is closed immediately in what is known as “fast transfer”. 
     The magnitude of the motor bus voltage is continuously compared to a selectable undervoltage limit and the breaker between the motor and the new bus is closed immediately if the undervoltge limit is met. This is known as “undervoltage closing” and has the advantage that the motor bus in-rush current is then less than the motors bus starting current if the motors had been allowed to come to a complete stop. 
     In FIG. 4 device power is supplied by an external 12 volt battery connected from terminal marked “12 Vdc” to N (neutral). This device power can be as simple as an automobile battery with charger. Selectively the supply is any other source of dc voltage such as 24, 48 and 120 volt batteries. Further selectively, regulator  2  obtains input power from a capacitor fed with positive charge through three diodes connected to EP, EM and EN (these components not shown). Power is thus available when any of the three inputs EP, EB or EN is powered. Regulator  2  converts the input dc voltage to 5 Vdc. The 5 Vdc supplies microprocessor  300  (hereinafter known as MP 300 ) supply terminal VDD and upper voltage reference terminal VRH along with collector of transistors  302 ,  303  and  304  (hereinafter referred to as TR 302 , TR 303  and TR 304  respectively). Terminal EP brings voltage waves from the present bus to a voltage divider consisting of resistors  305  and  311 . Divided voltage is fed through resistor  308  to the base of TR 302 . Diode  317  is connected from TR 302  base to neutral effectively limiting the negative half cycle of AC voltages to approximately−0.7 volts from TR 302  base to emitter. TR 302  emitter draws current through resistor  314  during positive AC half cycles and provides positive half cycles of voltage waves to MP 300  analog to digital converter (ADC) input AN 0 . Terminal EM brings voltage waves from the motor bus to a voltage divider consisting of resistors  306  and  312 . Divided voltage is fed through resistor  309  to the base of TR 303 . Diode  318  is connected from TR 303  base to neutral effectively limiting the negative half cycle of AC voltages to approximately −0.7 volts from TR 303  base to emitter. TR 303  emitter draws current through resistor  315  during positive AC half cycles and provides positive half cycles of voltage waves to ADC input AN 1 . Terminal EN brings voltage waves from the new bus to a voltage divider consisting of resistors  307  and  313 . Divided voltage is fed through resistor  310  to the base of TR 304 . Diode  319  is connected from TR 304  base to neutral effectively limiting the negative half cycle of AC voltages to approximately −0.7 volts from TR 304  base to emitter. TR 304  emitter draws current through resistor  316  during positive AC half cycles and provides positive half cycles of voltage waves to ADC input AN 2 . Crystal  12  is connected to MP 300  terminals XTAL and EXTAL providing control of the MP 300  bit rate. MP 300  binary output BO closes a contact in output circuit  301  using well known circuitry not otherwise shown in detail. Negative supply N is connected to MP terminal VSS as is the ADC voltage reference low, VRL. 
     While FIG. 4 illustrates a most economical use of a single microprocessor it is to be understood that additional microprocessors may be required to accommodate other than the most simple conditions for motor bus transfer. 
     Dispersed Generation (DG) 
     The following single phase devices use a single microprocessor for both phasor measurement and phasor computation for abnormal condition determination. This is accomplished by measuring phasors during positive half cycles of input AC waves and determining abnormal conditions during times where both voltage and current waves negative. This results in greater numbers of digital samples of waves being taken during said positive half cycles thus yielding greater accuracy of phasor components. All computation is done in the negative half cycles. 
     An inventive device, not shown in detail herein, provides backup disconnection of electronic generators intended to supply power to improve power quality. Such generators may furnish power during the first part of each cycle when many phase controlled loads have not yet turned on. They may also furnish power during voltage dips or power interruptions of, for example up to one second duration. Using capacitors for energy storage, such devices are incapable of handling the magnitude of fault currents deliverable from rotating synchronous generators. These generators may have internal means for disconnection upon determining factors indicating such a disconnection is necessary. For safety reasons however, some users require said backup devices duplicating the protective disconnection contained in the power quality generator. 
     Dispersed solar and other small sources of electrical energy are used in increasing numbers in homes and small businesses. These are generally single phase, supplying some but not always all of the buildings requirements. 
     A safety requirement may be for devices disconnecting such sources so as to permit maintenance work on nearby outside lines when these lines become disconnected from an electric power system. 
     Fuses are being developed that will blow in normal fashion with through current. They will also blow with the injection of a small current into a third terminal. They are not unlike ground fault circuit breakers except for requiring replacement once blown. The three terminal fuses have the advantage of being of selectable current rating for use in a common receptacle. In addition devices such as described hereinunder may be installed outside of buildings under the control of line maintenance personnel for their protective use. 
     FIG. 5 illustrates a circuit for sensing a single phase voltage from hot AC input, H, to neutral, N, and AC dispersed generation current input DG. Three terminal fuse  202  is as described in the previous paragraph. Microprocessor  200  computes voltage magnitudes during positive half cycles and current phasors using the voltage as reference. Current DG is connected so as to generally be in phase with the voltage H leaving time for tripping calculation when both voltage and current waves are negative. When a trip condition is determined MP 200  binary output F 1  turns off transistor Q 10  permitting resistor R 13  to feed a small current into terminal  203  of three terminal fuse  202  causing said fuse to blow interrupting power to DG. Said fuse also blows normally upon excessive DG current. 
     Input AC current DG creates an AC voltage across current transformer T 1  secondary burden R 8 . This voltage is fed to ADC input AN 1  through an emitter follower circuit using transistor Q 3  and resistors R 200  and R 12 . This acts as a zero crossing detector to place a rather perfect positive voltage half wave at input AN 1 . 
     Resistors R 2  and R 3  divide AC voltages from H to N and provide an input for emitter follower consisting of R 6 , R 7  and transistor Q 2  with output connected to microprocessor  200  ADC input AN 0 . Diodes D 3  and D 200  suppress negative voltage half cycles thus protecting transistors Q 2  and Q 3 . 
     Power supply  201  converts AC voltages from HI to N to 5 vdc for MP 200  and transistors Q 2  and Q 3 . 
     Tripping conditions may include: 
     1) Reverse power flow. 
     2) Under/over frequency. 
     3) Under/over voltage. 
     FIG. 6 illustrates a circuit similar to that of FIG. 5 except that a ground fault circuit breaker (not shown) is used to interrupt dispersed generation current. Voltage for said DG devices are connected to an AC source H to neutral (not shown but generally externally connected to ground GND). MP  200  output F 1  drives transistor Q 10  causing tripping ground current through resistor R 13  to terminal GND upon determination of tripping conditions. All other components function as described under FIG. 5, above. 
     Tripping conditions include those itemized under FIG.  5 . 
     Advantages of this invention include: 
     1) Eliminates the need for dual ported RAMs and high speed DSPs for determining and analyzing phasors of AC waves. 
     2) Higher speed tripping of circuit breakers to clear faults. 
     3) Accurate measurement of the fundamental and harmonic phasors of each cycle of an AC wave. 
     4) Matching and exceeding capabilities of analog circuitry for analyzing AC waves. 
     5) Providing easy user programmability of devices using the inventive technology. 
     6) Lower cost apparatus for high speed clearing of AC power fault conditions. 
     (7) Low cost means for preventing low energy single phase dispersed generators from backfeeding dangerous voltages to power lines when the lines become disconnected from power networks.