Abstract:
A static type semiconductor RAM device comprising a latch circuit at every column which detects, amplifies and temporarily memorizes a read-out signal from each of the memory cells in the corresponding column and which has a large drive capacity. In the static type RAM device according to the present invention, each of the memory cells is used as an element which only holds information, and data bus lines are driven by the latch circuits having a large drive capacity, so that the slow down of the read-out speed and the decrease of reliability of read-out data of the static type RAM device having a large memory capacity is prevented.

Description:
BACKGROUND OF THE INVENTION 
     (1) Field of the Invention 
     The present invention relates to a semiconductor RAM (Random Access Memory) device, more particularly to a static type RAM device which has a high read-out speed and a high reliability of read-out data. 
     (2) Description of the Prior Art 
     In recent years, the memory capacity and thus the integration, density of semiconductor memory devices has become very large. This is because it has become possible to make a great number of elements of very small size on one chip, due to recent technical developments in integrated circuitry. In a semiconductor memory device such as a static-type semiconductor RAM device having flip-flop type memory cells, the size of each of the memory cells has become very small so that the memory capacity has become very large. 
     However, in a conventional static type RAM device in which each of the memory cells drives a sense amplifier directly through bit lines and data bus lines, one disadvantage is that the read-out speed of the RAM device is decreased and the reliability of read-out data is decreased. This is due to the increase of the integration degree of the semiconductor memory device, where the chip size of each of the memory cells is small and, especially in a case of a static type memory cell, the size of the driver transistors included in each of the memory cells is small and hence the drive capacity of each of the memory cells decreases. Moreover, the stray capacitance of the bit lines and the data bus lines, which are driven by the memory cells and which form load circuits of the memory cells, does not decrease in accordance with the increase of the integration density of the RAM device. Therefore, the amplitude of a read-out signal from each of the memory cells becomes small, and the reliability of the read-out data is decreased. Thus, the time necessary to change the potential on each of the bit lines and the data bus lines becomes large, because it takes a long time to charge or discharge the stray capacitance of these lines by a memory cell having a small drive capacity. Therefore, the read-out time of the RAM device increases according to the increase in the integration density of the RAM device. 
     SUMMARY OF THE INVENTION 
     It is the principal object of the present invention to increase the read-out speed of the static RAM device having a large memory capacity. 
     It is another object of the present invention to improve the reliability of the read-out data from a static RAM device having a large memory capacity. 
     According to the present invention, there is provided a static type semiconductor RAM device comprising a latch circuit at every column which detects, amplifies and temporarily holds a read-out signal from each of the memory cells in the corresponding column and which has a large drive capacity. In the static type RAM device according to the present invention, each of the memory cells is used as an element to only hold information. The data bus lines are driven by the latch circuits having a large drive capacity, so that the slow down of the read-out speed of the static type RAM device having a large memory capacity is prevented. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block circuit diagram of a static type semiconductor RAM device according to the present invention; 
     FIG. 2 is a circuit diagram of a memory cell used in the RAM device of FIG. 1; 
     FIG. 3 is a block circuit diagram of a gate signal generator used in the RAM device of FIG. 1; 
     FIG. 4 is a timing diagram illustrating the signals appearing in the circuits of FIGS. 1 and 3; 
     FIG. 5 is a circuit diagram of a sense amplifier used in the RAM device of FIG. 1. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 illustrates a static type semiconductor RAM device in accordance with an embodiment of the present invention. In FIG. 1, memory cells MC 00  through MC NN  are disposed in a matrix of N rows by N columns and each of the memory cells comprises a flip-flop, which will be explained later in detail. Word lines W 0  through W N  are connected to X address (or row address) decoders XD 0  through XD N  respectively, and each of the word lines W 0  through W N  is selected by corresponding one of the output signals X 0  through X N  from the X address decoders XD 0  through XD N . A plurality of bit line pairs B 0 , B 0  through B N , B N  are crossed with a plurality of the word lines W 0  through W N  to form the matrix. At each cross position of the matrix, each of the memory cells MC 00  through MC NN  is connected between a bit line pair and a word line. These bit line pairs B 0  , B 0  through B N , B N  are connected to latch circuits or amplifier circuits RA 0  through RA N  respectively, according to the present invention. All the latch circuits RA 0  through RA N  have the same structure, and therefore only the latch circuit RA 0  will be explained hereinafter. The latch circuit RA 0  comprises load transistors Q 1  and Q 2 , and driver transistors Q 3  and Q 4  which comprise a flip-flop. The latch circuit RA 0  further comprises gate transistors Q 5  and Q 6  connected between the bit line pair B 0 , B 0  and the flip-flop, and a switching transistor Q 7 . The switching transistor Q 7  and the load transistors Q 1  and Q 2  are turned on and off by a signal Y 0D  which is a delayed signal of an output signal Y 0  from a Y address (or column address) decoder, not shown in the drawing. The gate transistors Q 5  and Q 6  are turned on and off by a delayed gate signal WDD produced in a gate signal generator, which will be explained later. Therefore, the latch circuits RA 0  through RA N  are selected by the delayed gate signal WDD and the delayed output signals Y 0D  through Y ND  of the output signals Y 0  through Y N  from the Y address decoders, not shown in the drawing. The flip-flop of each of the above-mentioned latch circuits RA 0  through RA N  has the same structure as that of each of the memory cells MC 00  through MC NN , which will be explained later. However, it should be noted that the drive capacity of the driver transistors Q 3  and Q 4  of each of the latch circuits is larger than that of the driver transistors of the flip-flop contained in each of the memory cells MC 00  through MC NN . Therefore, for example, the size of the driver transistors Q 3  and Q 4  of each of the latch circuits is larger than that of the driver transistors of each of the memory cells MC 00  through MC NN . 
     FIG. 2 illustrates, as an example, the memory cell MC 00 , used in the circuit of FIG. 1. The memory cell MC 00  comprises load transistors Q 21 , Q 22  and driver transistors Q 23 , Q 24  which comprise a flip-flop, and gate transistors Q 25 , Q 26  which are turned on and off by for example, the output signal from the X address decoder XD 0 , i.e., decoded address signal X 0 . When a read-out or a write-in of information is effected, the gate transistors Q 25  and Q 26  are turned on due to the supply of a decoded address signal X 0  of high potential level, and thus transfer of information between the bit lines B 0 , B 0  and the flip-flop of the memory cell MC 00  is effected. 
     FIG. 3 illustrates a gate signal generator which produces a delayed gate signal WDD. This generator comprises a detector circuit DXD including trigger pulse generators TG 01 , TG 02 , . . . , TG M1 , TG M2 , OR gates OG 0 , . . . , OG M , OG 00  and an inverter INV, and, a delay circuit TD. Each of the trigger pulse generators TG 01  through TG M2  detects potential changes, i.e. the leading edge or trailing edge, of the respective buffered address signals A 0 , A 0 , . . . , A M , A M  and generates respective trigger pulses T 0 , T 0  &#39;, . . . , T M , T M  &#39; when the potential change is detected. OR gates OG 0  through OG M  and an OR gate OG 00  effect the logical &#34;or&#34; operation of the trigger pulses T 0 , T 0  &#39;, . . . , T M , T M  &#39;. The inverter INV inverts an output signal from the OR gate OG 00  and produces a gate signal T. A delay circuit TD delays the gate signal T for a predetermined time period and produces the delayed gate signal WDD, which was mentioned before. The delay time of the delay circuit TD is approximately the time it takes the output signal X 0 , . . . , X N-1  or X N  respectively to propagate from the X address decoder XD 0 , . . . , XD N-1  or XD N  to the farthest end of the word line W 0 , . . . , W N-1  or W N , i.e., a portion of the word line to which the memory cell MC ON , . . . , MC N-1  N or MC NN  is connected in the embodiment of FIG. 1. Therefore, the delay circuit TD can be constructed by using a dummy word line which has approximately the same length as that of each of the word lines W 0  through W N  and which is disposed parallel to the word lines W 0   through W N . In the above-mentioned detector circuit, each of the trigger pulse generators TG 01  through TG M2  can be constructed by using, for example, a differentiation circuit and a wave shaping circuit. 
     With reference to FIG. 4, the operation of the memory device according to the present invention will now be explained. When the read-out of information from a memory cell of the memory device is effected, input address signals A 0 , A 1 , . . . , A M  designating the memory cell are applied to address buffer circuits, which are not shown in the drawings. The address buffer circuits produce buffered address signal pairs A 0 , A 0 , . . . , A M , A M  containing non-inverted signals and inverted signals of the input address signals. Some of the address signals A 0 , A 0 , . . . , A M , A M  are applied to the X address decorders XD 0  through XD N  and some of the address signals are applied to Y address decoders, which are not shown in the drawings. When the memory cell, for example, MC 00  is selected, the output X 0  from the X address decorder XD 0  becomes high and the output Y 0  from the Y address decoder becomes high. Before the output X 0  and the output Y 0  become high, at least two of the address signal pairs A 0 , A 0 , . . . , A M , A M  (i.e., at least a pair of the address signals including non-inverted and inverted address signals) change their potential level, as illustrated by A of FIG. 4. This change of the potential level may be a potential rise or a potential fall. In response to the change of the potential level of at least one address signal, the detector circuit DXD (FIG. 3) generates a gate signal T as illustrated in FIG. 4. The delay circuit TD (FIG. 3) delays the gate signal T and produces the delayed gate signal WDD, as illustrated in FIG. 4. The delayed gate signal WDD is applied to the gate electrodes of the transistors Q 5  and Q 6  of the latch circuits RA 0  through RA N  of FIG. 1. Before the delayed gate signal WDD is generated, the potential of all portions of the selected word line W 0  rises to a high level. Therefore, the information from the memory cell MC 00 , which is disposed at the position nearest the X address decoder XD 0  of FIG. 1, has already been read out to the bit line pair B 0 , B 0 . That is, the potentials of the point A and the point B (FIG. 2) in the memory cell MC 00  are already transferred to the bit lines B 0  and B 0  respectively. In such a condition, the gate transistors Q 5  and Q 6  are turned on by the delayed gate signal WDD and the information of the memory cell MC 00 , i.e. the potentials of the point A and the point B of the memory cell MC 00 , is applied to the latch circuit RA 0  through the gate transistors Q 5  and Q 6 . After the delayed gate signal WDD is applied to the gate transistors Q 5  and Q 6 , the delayed Y decoder signal Y 0D  is applied to the gate electrodes of the switching transistor Q 7  and of the load transistors Q 1  and Q 2  of the latch circuit R 0 . Thus, the latch circuit RA 0  is activated due to the supply of an operating voltage. Therefore, the latch circuit RA 0  is set to a condition determined by the input potentials, i.e. the potentials of the bit lines B 0  and B 0 , so that the transferring of information to the latch circuit RA 0  is effected. In this case, stray capacitance existing between the input circuit portion of the latch circuit RA 0  and the ground are charged by the potentials of the bit lines B 0  and B 0 . Therefore, even if the delayed Y decoder signal Y 0D  is applied to the latch circuit RA 0  a short time after the delayed gate signal WDD has changed from high potential to low potential, as illustrated in FIG. 4, it is possible to set the latch circuit RA 0  to a condition determined by the potentials of the bit lines B 0  and B 0 . It should be noted that the delayed gate signal WDD and the delayed Y decoder signal Y 0D  are needed in order to prevent the destruction of data in the memory cell MC 00 . If the gate transistors Q 5  and Q 6  are always turned on, due to the supply of DC voltage of high potential instead of the delayed gate signal WDD, or if the latch circuit RA 0  is activated by the Y decoder signal Y 0 , instead of the delayed Y decoder signal Y 0D , the memory cell MC 00  having a small drive capacity is written-in by the potentials of the bit lines B 0  and B 0  which are determined by a condition of the latch circuit RA 0  at the time the memory cell MC 00  is selected. Therefore, there is a possibility of the destruction of the data stored in the memory cell, for example, MC 00 . In order to prevent the destruction of the data stored in each of the memory cells, it is necessary to use the delayed gate signal WDD and the delayed Y decoder signal Y 0D , as mentioned before, so that the potentials of the bit lines are determined by the selected memory cell and the latch circuit is set to the condition determined by the potentials of the bit lines due to the supplied potentials of the bit lines. 
     FIG. 5 illustrates an example of a sense amplifier SA which is used in the memory device of FIG. 1. The sense amplifier SA comprises a pair of transistors Q 50  and Q 51  forming a differential amplifier, a pair of load transistors Q 52  and Q 53 , and a transistor Q 54  forming a constant current source. The gate electrodes of the transistors Q 50  and Q 51  are respectively connected to the output terminals of the latch circuits RA 0  through RA N  through data bus lines which are not shown in the drawings. Therefore, the output signals D and D of the latch circuit, for example, RA 0  are respectively applied to the gate electrodes of the transistors Q 50  and Q 51 , and amplified by the sense amplifier SA. The sense amplifier SA provides output signals O and O as the read-out signals from the memory device. 
     According to the present invention, the bit lines, the data bus lines and the sense amplifier are driven by the latch circuits, whose driver transistors are big in size, so as to obtain a large drive capacity, to increase the read-out speed and to improve the reliability of the read-out data of the static type RAM device. Therefore, it is not necessary to use memory cells having big sizes. Also, a latch circuit is provided for every column so that the integration density of the RAM device is not greatly decreased.