Abstract:
This disclosure relates to permuting transistors to compensate for offsets generated by transient variations of the transistors&#39; parameters.

Description:
BACKGROUND 
       [0001]    This application relates to maintaining threshold stability when switching transistors at high frequencies, and more specifically to maintaining threshold stability of comparators having transient variations of its transistor parameters. 
         [0002]    The physical limitations of the conventional silicon dioxide as a gate dielectric in transistors have reached the point where dioxide films thicknesses are only a few atomic layers thick. Below the physical thickness of 15A, the gate leakage current exceeds the specifications (e.g. 1 A/cm 2 ). To overcome this critical problem, highly resistive dielectrics have been introduced into the transistor as hafnium-based, zirconium, aluminum oxides. In fact, while keeping the equivalent oxide thickness constant, highly resistant dielectrics allow increasing in the physical thickness of the transistor&#39;s gate stack. Hence gate leakage is reduced by 2 to 3 orders of magnitude. Although a large amount of effort has been invested toward highly resistive gate dielectrics, many critical problems still remain. 
         [0003]    One of the challenges for the integration of highly resistive dielectrics is maintaining the transistors threshold voltage stability during operation. In addition to static mismatch transient variation come, transient variations of transistor parameters (e.g. V T , μ . . . ) in advanced CMOS technologies are caused by effects such as charge trapping, self heating or floating body effects. These effects appear when switching electronic devices using the advance CMOS technologies at high frequencies. In addition, well known static mismatch effects can appear and can degrade the performance of mixed-signal circuits significantly. 
         [0004]    Voltage or current comparators contain these transient variations. If the comparator is overdriven at its input, the threshold on the gate to trigger the transistor of a differential input pair is shifted asymmetrically. When one transistor of the pair of transistors receives a higher gate to source voltage than the other, a time dependent offset is introduced. If the comparator is no longer being overdriven and provides input voltages closer to its original threshold levels (the level where the threshold of the transistor pair are equal), a threshold offset voltage of several mV appears at this input stage. This offset voltage may be due to the transient variations of the transistor&#39;s parameters. This threshold offset voltage decreases with time constants in the range of μs. The accuracy of an analog to digital converter which is using such a comparator is limited to this several mV offset. 
         [0005]    Shown in  FIG. 1  is a comparator  100  used to detect zero voltage crossings of a signal. Comparator  100  includes comparator circuits  101  and  102 . Circuits  101  and  102  include transistors  103  and  104 , coupled via load  106  and  108  and via sample and hold circuit  110  to output terminals  112  and  114 . Transistors  103  and  104  include source terminals  116  and  118 , gate terminals  120  and  122  and drain terminals  124  and  126 , respectively. Source terminals  116  and  118  are connected to load  106  and  108 , respectively. Gate terminals  120  and  122  are connected to input terminals  130  and  132 , and the input terminals receive a respective input signal. The drain terminals  124  and  126  are connected to current source  136 . Upon receiving an input signal having a level to saturate gate terminals  120  or  122 , transistors  103  and  104  respectively pass current from current source  136  via load  106  and  108  to sample and hold circuit  110 . Sample and hold circuit  110  receives a clock signal (designated as “fClock”) on line  140  to hold its output at fixed voltage level for the duration of an fClock period. 
         [0006]    Normally the accuracy of the comparator is only needed near the zero voltage crossing (across the gate and drain terminal) or transistor bias level. In certain analog to digital converters, for example, the conversion is done in a successive way. First, a rough estimation of the analog voltage level which has to be converted to a digital signal is done at a first stage of a conversion cycle. 
         [0007]    This estimation is then elaborated step by step. Only errors at the last stage of the conversion cycle affect the result. This results in a comparator which can have large errors at the beginning of the conversion cycle and no errors at the last conversion cycle. But due to the transient variations of transistor parameters caused by the overdrive at the first conversion cycle, the error only disappears at the last cycle if the conversion speed is much less than the time constant of this transient variations of transistor parameters. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference numbers in different instances in the description and the figures may indicate similar or identical items. 
           [0009]      FIG. 1  is simplified schematic diagram of a prior art comparator circuit. 
           [0010]      FIG. 2  is simplified schematic diagram of a comparator circuit incorporating a permuting circuit. 
           [0011]      FIG. 3  is simplified schematic diagram of a load circuit shown in  FIG. 2 . 
           [0012]      FIG. 4  is a timing diagram to permute the comparator circuit in accordance with the invention. 
           [0013]      FIG. 5  is a flow diagram of an exemplary process for permuting the comparator circuit in accordance with the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]    The accuracy of a comparator can be increased by using two comparator circuits. One comparator circuit takes the first rough decision by triggering when an input signal exceeds a threshold voltage of the circuit. The input to the second comparator circuit is held during this first decision in a symmetric bias point. In a subsequent cycle, the second comparator fed the estimated input signal at a level closer to the zero crossing level, and is triggered when the estimated input signal crosses the zero voltage crossing level. The error introduced by transient variations of transistor parameters at the subsequent decision cycle is small because the second comparator is fed the estimated input signal closer to the zero voltage crossing level of the comparator and sees no high overdrive. 
         [0015]    More than two comparators can be used for this scheme. The whole comparator does not have to be built twice but only these transistors of the comparator which are stressed and which affect the comparator decision are used. These transistors have to be replicated and one of the transistors has to be held in a symmetric bias condition during the first conversion cycle. The transistors output is then used at the subsequent decision cycle. 
         [0016]    Disclosed herein are techniques for switching transistors during the aforementioned process. Each of the input pairs of transistors in a typical comparator is replaced by at least two transistors. Due to the voltages applied to the terminals of the transistors the threshold voltage varies with time. To reduce the threshold voltage variation, the transistors are exchanged. 
         [0017]    In one implementation, a comparator having a first and second input stage to respectively receive a first and a second input signal is described. Each stage has an input, a current source connection and an output. The input stages include a first circuit and second circuit, the first and second circuits is connected with the input stage&#39;s input, output and current source connection. The second circuit selectively disconnects from the first input stage&#39;s output and connects to the second stage&#39;s output. The second circuit selectively disconnects from the first input stage&#39;s input and connects to the second stage&#39;s input. The output stage generates a signal corresponding to a level of a signal on one of the output thus improving the accuracy of the comparator. 
         [0018]    According to another implementation, a method is provided for receiving with a circuit, that includes a first and a second input stage, and a first and a second input signal. The first input signal is received with a first and a second circuit disposed in the first input stage. The second input signal is received with a third and a fourth circuit disposed in the second input stage. In response to the first input signal, a first output signal generated by the first circuit and a second output signal generated by the second circuit is fed to a first output terminal. In response to the second input signal, a third output signal generated by the third circuit and fourth output signal generated by the fourth circuit is fed to a second output terminal. The second output signal generated by the second circuit is periodically fed to the second output and the fourth output signal generated by the fourth circuit is fed to the first output. The second output signal from the second output terminal is periodically removed and the second output signal is fed to the first output. The fourth output signal is periodically removed from the first output and the fourth output signal is fed to the second output. 
         [0019]    The techniques described herein may be implemented in a number of ways. One example environment and context is provided below with reference to the included figures and on going discussion. 
         [0020]    Exemplary Systems 
         [0021]      FIG. 2  illustrates one implementation of the comparator circuit  200  that includes input stages  202  and  203 . Input stage  202  has an input terminal  202   i , an output terminal  202   o  and a current source connection  202   c . Input stage  203  has an input terminal  203   i , an output terminal  203   o  and a current source connection  203   c . The inputs of input stages  202  and  203  are respectively connected to input terminals  204  and  205 . Input stage  202  includes transistors  206  and  208 , and input stage  203  includes transistors  210  and  212 . The outputs of input stages  202  and  203  are coupled via load  213  and sample and hold circuit  220  to output terminals  222  and  224  respectively. Sample and hold circuit  220  receives a clock signal (designated as “fClock”) generated by clock generation circuit  225 . The output of the Sample-and-hold circuit  220  is maintained at fixed level for the duration of at least on fClock period. 
         [0022]    Load  213  includes load stages or load circuits  214  and  216 , which respectively connect input stages  202  and  203  to sample and hold circuit  220 . 
         [0023]    Transistors  206 - 212  include source terminals  206   s - 212   s , gate terminals  206   g - 212   g  and drain terminals  206   d - 212   d  respectively. Source terminal  206   s  is connected to load  214 , and source terminals  208   s  and  210   s  are selectively connected to load  214 . Source terminal  212   s  is connected to load stage  216 , and source terminals  208   s  and  210   s  are selectively connected to load stage  216 . Gate terminal  206   g  is connected to input terminal  204 , and gate terminals  208   g  and  210   g  are selectively connected to input terminal  204 . Gate terminal  212   g  is connected to input terminal  205 , and gate terminals  208   g  and  210   g  are selectively connected to input terminal  205 . Input terminals  204  and  205  receive input signals. The drain terminals  206   d - 212   d  are connected via the current source connection of the input stages  202  and  203  to current source  228 . 
         [0024]    Switches  230  and  232  respectively connect to source terminal  206   s  and source terminal  212   s . Switch  230 , in response to an fClock/2 signal, selectively connects source terminal  206   s  to either source terminal  208   s  or source terminal  210   s . Switch  232  selectively connects source terminal  212   s  to either source terminal  208   s  or source terminal  210   s . Switches  234  and  236  are connected to drain terminal  206   d , drain terminal  208   d  and drain terminal  210   d . Switch  234  selectively connects drain terminal  206   d  to either drain terminal  208   d  or drain terminal  210   d . Switch  236  selectively connects drain terminal  212   d  to either drain terminal  208   d  or drain terminal  210   d . The clock fClock/2 signal is fed to switches  230 - 236 . In one implementation, fClock/2 is generated by circuit  225  and is synchronized with, and has a frequency that is half of, the frequency of the fClock. Further switches  230 - 236  respond to the clock signal by connecting and removing one terminal to another terminal as the level of the fClock/2 clock signal changes. 
         [0025]    In operation, one of input stages  202  or  203  is stressed by the input voltage level of its input signal while the other of input stages  203  or  202  is not. For example, the input voltage level of the input signal provided on input terminal  204  overdrives input stage  202 , while the input signal provided on input terminal  205  does not overdrive input stage  203 . During a first fClock clock cycle, due to this overdrive resulting from the input signal, the threshold voltage of the gate terminals  206   g  and  208   g  of input stage  202  rises, whereas the threshold voltage of the gate terminals  210   g  and  212   g  of input stage  203  declines. On a subsequent fClock clock cycle, switches  230 - 236  are switched resulting in transistor  208  on input stage  202  being exchanged with transistor  210  of stage  203  to restores the symmetry in the circuit. Thus, the offset generated by the transient variations of transistor parameters is compensated by permuting the comparators&#39; transistors. In one implementation, all the switches  230 - 236  switch simultaneously in response to the fClock/2 signal. 
         [0026]      FIG. 3  shows the load  213  depicted in  FIG. 2 . Load  213  includes load circuit  300  comprising load circuit  302  and load circuit  304 . Load circuit  302  includes transistors  306 - 308 , and load circuit  304  includes transistors  310 - 312 . Transistors  306 - 312  include source terminals  306   s - 312   s , gate terminals  306   g - 312   g  and drain terminals  306   d - 312   d , respectively. Source terminal  306   s  is connected via sample and hold circuit  220  to output terminal  222 , and source terminals  208   s  and  210   s  are selectively connected via sample and hold circuit  220  to output terminal  222 . Source terminal  312   s  is connected via sample and hold circuit  220  to output terminal  224 , and source terminals  308   s  and  310   s  are selectively connected via sample and hold circuit  220  to output terminal  224 . Gate terminals  306   g - 312   g  are respectively connected to drain terminals  306   d - 312   d  and the output of input stages  202  and  203  ( FIG. 2 ). 
         [0027]    Switch  330  is connected to source terminal  306   s  source terminal  308   s  and source terminal  310   s . Switch  332  is connected to source terminal  308   s , source terminal  310   s , and source terminal  312   s . Switch  330  selectively connects source terminal  306   s  to either source terminal  308   s  or source terminal  310   s . Switch  332  selectively connects source terminal  312   s  to either source terminal  308   s  or source terminal  310   s . Switch  334  selectively connects drain terminal  306   d  to either drain terminal  308   d  and to drain terminal  310   d . Switch  336  selectively connects drain terminal  306   d  to either drain terminal  308   d  or to drain terminal  310   d . Clock signal fClock/2 is fed to switches  330 - 336 . In one implementation, switches  330 - 336  respond to the clock signal fClock/2 by switching from one terminal to another in response to the voltage level of the clock signal changing. 
         [0028]    In operation, one load circuit  302  is fed the output signal of input stage  202  while the other load circuit  303  is not. For example, the input voltage level of the output signal from stage  202  is provided on input terminal  304  and drives load circuit  302 , while the output signal from stage  203  drives load circuit  304 . During a first fClock clock cycle, the threshold voltage of the gate terminals  306   g  and  308   g  in load circuit  302  rises, whereas the threshold voltage of the gate terminals  310   g  and  312   g  of load circuit  304  declines. On a all subsequent fClock clock cycles, switches  330 - 336  are switched resulting in transistor  308  on load circuit  302  being exchanged with transistor  310  of  303  to restore the symmetry in the load circuit. 
         [0029]      FIG. 4  shows a timing diagram for the circuit depicted in  FIG. 2 . The timing diagram illustrates the relationship over time between the first and second input signals respectively fed to input terminals  204  and  205 , and the output signals on output terminal  222  and  224  in response to the fClock and fClock/2. Prior to time t 0 , input signals are provided to the first stage  202  and second stage  203  via input terminals  204  and  205 . The fClock and fClock/2 signals are fed to the sample and hold circuit  220  and switches  230 - 236 . In response to the fClock signal, switches  230 - 236  change their terminal&#39;s connection. The input signals on terminals  204  and  205  are respectively fed via stages  202  and  203 , and load  213  to the input of sample and hold circuit  220 . At time t 1 , in response to the fClock signal, switches  230 - 236  switch their terminals. In response to fClock/2 the input signal on the input terminals of sample and hold circuit  220  is propagated to the output terminals as the output signal. Subsequently at time t 2 , in response to the fClock signal, the switches  230 - 236  switch from one terminal to another. The input signal is again propagated via stages  202  and  203 , and load  213  to the input of sample and hold circuit  220 . At time t 3 , in response to the negative edge of fClock/2, the input of the sample and hold circuit  220  is propagated to the output terminals  222  and  224  as the output signal. 
         [0030]    This scheme of exchanging stressed devices can be used with every symmetrical circuit. If for example the load resistors are built by transistors, the transient variations of these transistor parameters can be compensated in the same way. 
         [0031]    Although the two stages are shown as one example, this implementation is meant to serve only as a non-limiting example and multiple stages may be used having multiple transistors. 
         [0032]    Exemplary Process 
         [0033]      FIG. 5  shows one example implementation of a process  500  for using a comparator to handle transient variations of transistor parameters. The system in  FIG. 2  may be used for reference in describing one aspect of providing a comparator circuit  200  including switches permuting input stage  202  and input stage  203 . 
         [0034]    At block  502 , the input signals, i.e., the fClock/2 and fClock signal, are received at the input stages. The switches and the transistor circuits are disposed within the input stages. 
         [0035]    At block  504 , the transistors in the input stages  202  and  203  generate output signals. The output signal varies as a function of the threshold voltage level between the gate and the drain in the transistors  206 - 212 . 
         [0036]    At block  506 , the output signals are fed to the sample and hold circuit  220  via the load  213 . 
         [0037]    At block  508 , the output signals fed to the to the sample and hold circuit  220  are sampled by the sample and hold circuit  220  and held for one fClock cycle before being fed to the comparator&#39;s output terminals  222  and  224 . 
         [0038]    At block  510 , in response to the fClock/2 signal, an output signal from one circuit in input stages  202  and  203  and the load stages  214  and  216  is switched and fed to another output terminal of another one of input stages  202  and  203 . The switched output signals are fed via the load  213  to the sample and hold circuit  220 . 
         [0039]    At block  512 , the switched output signals fed to the to the sample and hold circuit  220  are sampled by the sample and hold circuit  220  and are held for one fClock cycle before being fed to the comparator&#39;s output. 
         [0040]    At block  514 , in response to the fClock/2 signal, the output signal from one circuit in the input stages  202  and  203  and load stage  213  is switched back and fed to the original output of the input stage. 
         [0041]    At block  516 , the switched output signals fed to and sampled by the sample and hold circuit  220  and are held for one fClock cycle before being fed to output terminals  222  and  224 . This process then begins again at block  502 , where the input signals, the fClock/2 and fClock signal are received at the input stages  202  and  203 . 
         [0042]    Specifics of exemplary methods are described below. However, it should be understood that certain acts need not be performed in the order described, and may be modified, and/or may be omitted entirely, depending on the circumstances. Moreover, the acts described may be implemented by a computer, processor or other computing device based on instructions stored on one or more computer-readable media. The computer-readable media can be any available media that can be accessed by a computing device to implement the instructions stored thereon. 
       CONCLUSION 
       [0043]    Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as preferred forms of implementing the claims.