Abstract:
A charge control circuit for controlling charging of a plurality of batteries includes switching elements respectively connected in parallel to the batteries, and a charge control device for reducing charging current to the respective batteries. The charge control device converts voltages of the respective batteries into multiple converted battery voltages based on a predetermined reference voltage as a reference on the basis of voltages at both ends of the respective batteries, generates an offset battery voltage obtained by adding a predetermined offset voltage to the converted battery voltages, compares each converted battery voltage with the offset battery voltage, and reduces charging current to the corresponding battery by turning on the switching element connected in parallel to the corresponding battery when the each converted battery voltage is higher than the offset voltage.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The present application claims priority to Japanese Patent Application No. 2012-057685 filed Mar. 14, 2012 to the Japan Patent Office, the entire content of which is incorporated herein by reference in its entirety. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a charge control circuit for controlling charging to a battery circuit including a plurality of battery cells (hereinafter referred to as cells) connected in series and a battery device including the charge control circuit. 
         [0004]    2. Description of the Related Art 
         [0005]    In a protection IC for a multi-cell Li ion secondary battery, cell voltages of a plurality of cells easily become unbalanced, and a function to balance the plurality of cell voltages is required. In general, a balancing method that turns on a transistor connected to cells in parallel when each cell voltage becomes equal to or higher than a certain voltage has already been in place. 
         [0006]    In addition, in Japanese Patent Application Publication No. 2009-254008, for example, in order to provide a charge/discharge control circuit and a battery device which can better prevent shortage in charging of a battery, detection of a cell balance (CB) period is performed before charging of each battery is stopped, i.e., after controlling of CB, and charging of each battery is stopped, even if overcharge detection voltage of a certain charge/discharge control circuit falls below a CB period detection voltage due to variations in manufacturing during mass production of charge/discharge control circuits. This has the operation and effect that can better prevent shortage in charging of each battery. 
         [0007]      FIG. 1  is a circuit diagram showing a configuration of a charge control circuit of a conventional technique and a peripheral circuit thereof. In  FIG. 1 , the circuit is configured to include a protection IC circuit  100  including cells C 1  to C 5  connected to each other in series, resistors R 101  to R 105  for a bypass current, MOS transistors M 101  to M 105  for reducing charging current, and comparators COMP 101  to COMP  105 . 
         [0008]    In  FIG. 1 , a charger  200  charges the cell C 1 , the cell C 2 , the cell C 3 , the cell C 4 , and the cell C 5  at 110 mA, for example. Here, it is assumed that a turnover voltage of the comparator COMP 101 , the comparator COMP 102 , the comparator COMP 103 , the comparator COMP 104 , and the comparator COMP 105  is 4.15V. For example, when a voltage of the cell C 1  increases and exceeds 4.15V, the comparator COMP 101  is turned over and voltage CB 1  goes to high level. This turns on the MOS transistor M 101 , and current of 4.15V/40Ω=104 mA runs through the resistor R 101 . Then, current running through the cell C 1  is 110 mA−104 mA=6 mA. With this, charging current to the cell C 1  can be reduced. 
         [0009]    For the cell C 2 , in  FIG. 1 , since the cell voltage is 4.2V, the comparator COMP 102  is turned over and voltage CB 2  goes to high level. This turns on the MOS transistor M 102 , and current of 4.2V/40Ω=105 mA runs through the resistor R 102 . Then, current running through the cell C 2  is 110 mA−105 mA=5 mA. With this, charging current to the cell C 2  can be reduced. 
         [0010]    For the cell C 3 , the cell C 4 , and the cell C 5 , in  FIG. 1 , since the cell voltage is 3.8V, the comparator COMP 103 , the comparator COMP 104 , and the comparator COMP 105  are not turned over, and voltages CB 3 , CB 4 , and CB 5  are at low level. With this, the MOS transistors M 103 , M 104 , and M 105  are not turned on, charging current of 110 mA runs through the cell C 3 , the cell C 4 , and the cell C 5 , and the charging current can be supplied to the cell C 3 , the cell C 4 , and the cell C 5 , rather than the cell C 1  and the cell C 2 . With the above, for any cell which exceeds the turnover voltage (i.e., balance voltage of cell voltage) of the comparator COMP 101 , the comparator COMP 102 , the comparator COMP 103 , the comparator COMP 104 , and the comparator COMP 105 , the charging current can be reduced and cell voltage increasing speed due to charging can be lowered. Consequently, charging can be performed and completed while a reduced voltage difference with cells which do not exceed the turnover voltage (i.e., balance voltage of cell voltage) of the comparator COMP 101 , the comparator COMP 102 , the comparator COMP 103 , the comparator COMP 104 , and the comparator COMP 105 . 
         [0011]    However, the cell voltage balancing method of the conventional technique has a problem that batteries are charged without balancing a cell voltage when the cell voltage is low. Specifically, there is a problem as follows: batteries are charged with the cell voltage unbalanced, and a transistor connected in parallel to cells turns on to attempt to balance the cell voltage when a battery voltage exceeds a certain voltage. However, when the cell voltage is low, the cell voltage is unbalance, and thus cannot be balanced. When one cell voltage exceeds an overcharge detection voltage, charging is disabled and completed with the battery voltage remaining unbalanced. 
         [0012]    In addition, the charge control device disclosed in Japanese Patent Application Publication No. 2009-254008 has the balancing method of the conventional technique described above, wherein a relation of balance voltage of cell voltage and overcharge detection voltage is normally as follows: the balance voltage of cell voltage &lt;overcharge detection voltage. However, control of the charge control circuit is such that balancing of the cell voltage takes precedence even when the relation of the balance voltage of cell voltage and the overcharge detection voltage is reversed due to variations between chips. While this makes it easier to balance the cell voltage, it cannot entirely overcome the problem described above. 
       SUMMARY OF THE INVENTION 
       [0013]    An object of the present invention is to solve the problem described above and to provide a charge control circuit capable of balancing cell voltages without relying on the cell voltages and charging a battery till voltages of all cells are close to a full charge state, and a battery device provided therewith. 
         [0014]    To accomplish the above-described object, a charge control circuit according to an embodiment of the present invention is a charge control circuit for controlling charging of a plurality of batteries included in a battery circuit and connected in series when the battery circuit is charged by a charger at both ends of the battery circuit, the charge control circuit including: a plurality of switching elements respectively connected in parallel to the plurality of batteries; and a charge control device for reducing charging current to the respective batteries. 
         [0015]    The charge control device includes one of: 
         [0000]    (A) a first control device which converts voltages of the respective batteries into a plurality of converted battery voltages based on a predetermined reference voltage as a reference on the basis of voltages at both ends of the respective batteries, generates an offset battery voltage obtained by adding a predetermined offset voltage to the plurality of converted battery voltages, compares each of the plurality of converted battery voltages with the offset battery voltage, and reduces charging current to the corresponding battery by turning on the switching element connected in parallel to the corresponding battery when the each converted battery voltage is higher than the offset voltage;
 
(B) a second control device which converts voltages of the respective batteries into a plurality of converted battery voltages based on a predetermined reference voltage as a reference on the basis of voltages at both ends of the respective batteries, generates a battery mean voltage of the respective battery voltages which is a mean voltage of the respective voltages based on the predetermined reference voltage as a reference, compares each of the plurality of converted battery voltages with the battery mean voltage, and reduces charging current to the corresponding battery by turning on the switching element connected in parallel to the corresponding battery when the each converted battery voltage is higher than the battery mean voltage; and
 
(C) a third control device which generates a pair of offset battery voltages obtained by adding and subtracting a predetermined offset voltage to/from a mean voltage of a pair of mutually adjacent batteries of the plurality of batteries on the basis of voltages at both ends of the respective batteries, compares the pair of offset battery voltages with the voltage of one battery of the pair of mutually adjacent batteries to thereby determine a battery with a higher battery voltage of the pair of batteries when the pair of offset battery voltages are higher than the voltage of the one battery of the pair of mutually adjacent batteries, and reduces charging current to the corresponding battery by turning on the switching element connected in parallel to the battery whose battery voltage is determined to be higher.
 
         [0016]    A battery device according to another embodiment of the present invention includes: a battery circuit including a plurality of batteries connected in series; and the charge control circuit described above. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]      FIG. 1  is a circuit diagram showing a configuration of a charge control circuit of a conventional technique and a peripheral circuit thereof. 
           [0018]      FIG. 2  is a circuit diagram showing a configuration of a charge control circuit according to a first embodiment and a peripheral circuit thereof. 
           [0019]      FIG. 3  is a circuit diagram showing a configuration of a logic circuit  30  of  FIG. 2 . 
           [0020]      FIG. 4  is a circuit diagram showing a configuration of a charge control circuit according to a second embodiment and a peripheral circuit thereof. 
           [0021]      FIG. 5  is a circuit diagram showing a configuration of a logic circuit  31  of  FIG. 4 . 
           [0022]      FIG. 6  is a circuit diagram showing a configuration of a charge control circuit according to a modification of the second embodiment and a peripheral circuit thereof. 
           [0023]      FIG. 7  is a circuit diagram showing a configuration of a charge control circuit according to a third embodiment and a peripheral circuit thereof. 
           [0024]      FIG. 8  is a circuit diagram showing configuration of a logic circuit  32  of  FIG. 7 . 
           [0025]      FIG. 9  is a circuit diagram showing a configuration of a charge control circuit according to a modification of the third embodiment and a peripheral circuit thereof. 
           [0026]      FIG. 10  is a circuit diagram showing configurations of logic circuits  32 - 1 ,  32 - 2  of  FIG. 9 . 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0027]    In the following, embodiments according to the present invention will be described with reference to the drawings. Note that same symbols are assigned to similar components throughout the following embodiments. 
       First Embodiment 
       [0028]      FIG. 2  is a circuit diagram showing a configuration of a charge control circuit according to a first embodiment and a peripheral circuit thereof. In  FIG. 2 , charging current Ichg is supplied from a charger  200  to a battery circuit of three cells C 1 , C 2 , C 3 , which are secondary batteries connected in series to each other, via charging terminals  202 ,  201 , Here, a protection IC circuit  1  for charge control is connected to the battery circuit. The protection IC circuit  1  is configured to include a voltage subtraction and conversion circuit  10 , an offset voltage addition circuit  20 , and a logic circuit  30 . In addition, for each of the cells C 1  to C 3 , a protection resistor Rvc or Rvss, a bypass current resistor Rcb, and a MOS transistor (switching element) M 1 , M 2 , or M 3  connected thereto for reducing charging current are connected between the battery circuit and the protection IC circuit  1 . In one example of the embodiment, when a maximum voltage of each of the cells C 1  to C 3 =4.3V and the charging current Ichg=2 mA, Rcb=100Ω and Rvss=Rvc=0Ω, for example. Note that a voltage of the cell C 1  is expressed by VC 1 , a voltage of the cell C 2  is expressed by VC 2 , and a voltage of the cell C 3  is expressed by VC 3 . Also note that gate voltages (cell balance period voltages) to be applied to the gates of the respective MOS transistors M 1 , M 2 , and M 3  are represented by CB 1 , CB 2 , and CB 3 , respectively. 
         [0029]    The voltage subtraction and conversion circuit  10  is configured to include: 
         [0000]    (a) a voltage subtraction and conversion unit  10   a  configured to include four resistors R and an operational amplifier  11 , computing a difference between two voltages to be inputted, converting it into a converted battery voltage with a ground potential VSS as a reference, and then outputting it;
 
(b) a voltage subtraction and conversion unit  10   b  configured to include four resistors R and an operational amplifier  12 , computing a difference between two voltages to be inputted, converting it into a converted battery voltage with the ground potential VSS as a reference, and then outputting it; and
 
(c) a voltage subtraction and conversion unit  10   c  configured to include four resistors R and an operational amplifier  13 , computing a difference between two voltages to be inputted, converting it into a converted battery voltage with the ground potential VSS as a reference, and then outputting it.
 
         [0030]    In the voltage subtraction and conversion circuit  10 , the voltage subtraction and conversion unit  10   a  computes voltages VC 1 −VC 2 , and converts the voltage VC 1  of the cell C 1  into the converted battery voltage VC 1  (VSS standard) of the ground potential VSS standard (hereinafter expressed as VC 1 (VSS), which also applies to other voltages. Specifically, (VSS) expresses the voltage of the ground potential VSS standard), and outputs it. The voltage subtraction and conversion unit  10   b  computes voltages VC 2 −VC 3 , converts the voltage VC 2  of the cell C 2  into the converted battery voltage VC 2 (VSS) of the ground potential VSS standard, and outputs it. The voltage subtraction and conversion unit  10   c  computes voltages VC 3 −VSS, converts the voltage VC 3  of the cell C 3  into the converted battery voltage VC 3 (VSS) of the ground potential VSS standard, and outputs it. 
         [0031]    The offset voltage addition circuit  20  is configured to include: 
         [0000]    (a) an offset voltage adder  20   a  configured to include four resistors R 1 , a voltage source  51  of an offset voltage Vos, and an operational amplifier  14 , adding two voltages to be inputted, and generating and outputting an offset battery voltage to which the offset voltage Vos is added;
 
(b) an offset voltage adder  20   b  configured to include four resistors R 1 , a voltage source  52  of the offset voltage Vos, and an operational amplifier  15 , adding two voltages to be inputted, and generating and outputting an offset battery voltage to which the offset voltage Yes is added;
 
(c) an offset voltage adder  20   c  configured to include four resistors R 1 , a voltage source  53  of the offset voltage Vos, and an operational amplifier  16 , adding two voltages to be inputted, and generating and outputting an offset battery voltage to which the offset voltage Vos is added.
 
         [0032]    In the offset voltage addition circuit  20 , the offset voltage adder  20   a  generates an offset battery voltage VC 1 (VSS)+Vos obtained by adding the offset voltage Vos (60 mV, for example) to the voltage VC 1 (VSS). The offset voltage adder  20   b  generates an offset battery voltage VC 2 (VSS)+Vos obtained by adding the offset voltage Vos (60 mV, for example) to the voltage VC 2 (VSS). The offset voltage adder  20   c  generates an offset battery voltage VC 3 (VSS)+Vos obtained by adding the offset voltage Vos (60 mV, for example) to the voltage VC 1 (VSS). 
         [0033]      FIG. 3  is a circuit diagram showing configuration of the logic circuit  30  of  FIG. 2 . In  FIG. 3 , the logic circuit  30  is configured to include six comparators COMP 1  to COMP 6 , three NOR gates NOR 1  to NOR 3 , and three inverters INV 1  to INV 3 . In  FIG. 3 , the voltage VC 1 (VSS), the voltage VC 2 (VSS), the voltage VC 3 (VSS), the voltage VC 1 (VSS)+Vos, the voltage VC 2 (VSS)+Vos, and the voltage VC 3 (VSS)+Vos are inputted into the logic circuit  30 . Comparing the voltage VC 1 (VSS) with the voltage VC 2 (VSS)+Vos, the comparator COMP 1  outputs a binary signal, which is a result of the comparison, to the inverter INV 1  via the NOR gate NOR 1 . Comparing the voltage VC 1 (VSS) with the voltage VC 3 (VSS)+Vos, the comparator COMP 2  outputs a binary signal, which is a result of the comparison, to the inverter INV 1  via the NOR gate NOR 1 . Comparing the voltage VC 2 (VSS) with the voltage VC 1 (VSS)+Vos, the comparator COMP 3  outputs a binary signal, which is a result of the comparison, to the inverter INV 2  via the NOR gate NOR 2 . Comparing the voltage VC 2 (VSS) with the voltage VC 3 (VSS)+Vos, the comparator COMP 4  outputs a binary signal, which is a result of the comparison, to the inverter INV 2  via the NOR gate NOR 2 . Comparing the voltage VC 3 (VSS) with the voltage VC 1 (VSS)+Vos, the comparator COMP 5  outputs a binary signal, which is a result of the comparison, to the inverter INV 3  via the NOR gate NOR 3 . Comparing the voltage VC 3 (VSS) with the voltage VC 2 (VSS)+Vos, the comparator COMP 6  outputs a binary signal, which is a result of the comparison, to the inverter INV 3  via the NOR gate NOR 3 . 
         [0034]    The logic circuit  30  outputs a high-level cell balance period voltage CB 1  to a gate of the MOS transistor M 1   
         [0000]    (a) when the voltage VC 1 (VSS) is higher than the voltage VC 2 (VSS)+Vos; or
 
(b) when the voltage VC 1 (VSS) is higher than the voltage VC 3 (VSS)+Vos. This turns on the MOS transistor M 1  and bypasses the charging current running through the cell C 1 . In addition, the logic circuit  30  outputs a high-level cell balance period voltage CB 2  to a gate of the MOS transistor M 2 
 
(a) when the voltage VC 2 (VSS) is higher than the voltage VC 1 (VSS)+Vos; or
 
(b) when the voltage VC 2 (VSS) is higher than the voltage VC 3 (VSS)+Vos. This turns on the MOS transistor M 2  and bypasses the charging current running through the cell C 2 . Furthermore, the logic circuit  30  outputs a high-level cell balance period voltage CB 3  to a gate of the MOS transistor M 3 
 
(a) when the voltage VC 3 (VSS) is higher than the voltage VC 1 (VSS)+Vos; or
 
(b) when the voltage VC 3 (VSS) is higher than the voltage VC 2 (VSS)+Vos. This turns on the MOS transistor M 3  and bypasses the charging current running through the cell C 3 .
 
         [0035]    With the operations described above, when a potential difference between respective pairs of the cell C 1 , the cell C 2 , and the cell C 3  exceeds Vos (60 mV, for example), balancing of the respective cell voltages can be achieved by bypassing charging current which runs through the cell of a higher potential of the pair of cells. 
         [0036]    In the charge control circuit according to the embodiment, charging is possible while balancing cell voltages among the cell C 1 , the cell C 2 , and the cell C 3 . 
       Second Embodiment 
       [0037]      FIG. 4  is a circuit diagram showing a configuration of a charge control circuit according to a second embodiment and a peripheral circuit thereof. In comparison with the charge control circuit according to the first embodiment in  FIG. 2 , the charge control circuit according to the second embodiment in  FIG. 4 : 
         [0000]    (1) includes a resistive voltage division circuit  21 , in place of the offset voltage addition circuit  20 ; and
 
(2) includes a logic circuit  31 , in place of the logic circuit  30 . In the following, the differences will be described.
 
         [0038]    In  FIG. 4 , the resistive voltage division circuit  21  is configured by three resistors R 2  having an identical resistance value and connected in series. To balance cell voltages for three cells, for example, by resistively dividing voltages (VC 1 −VSS) between the voltage VC 1  and the voltage VSS using the three resistors R 2 , the circuit generates a cell mean voltage (battery mean voltage) VCA(VSS) of the three cell voltages expressed by the following expression and outputs it to the logic circuit  31 . 
         [0000]    
       
         
           
             
               
                 
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                           VCA 
                            
                           
                             ( 
                             VSS 
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                          
                         
                           
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         [0039]    Note that the voltage VC 1 (VSS), the voltage VC 2 (VSS), and the voltage VC 3 (VSS) from the voltage subtraction and conversion circuit  10  are inputted into the logic circuit  31 . 
         [0040]      FIG. 5  is a circuit diagram showing a configuration of the logic circuit  31  of  FIG. 4 . In  FIG. 5 , the logic circuit  31  is configured to include three comparators COMP 1  to COMP 3 , three inverters INV 1  to INV 3 , and three inverters INV 4  to INV 6  each of which is inverted to a value of a supply voltage VDD level. 
         [0041]    In  FIG. 5 , comparing the voltage VCA(VSS) with the cell mean voltage VCA(VSS), the comparator COMP 1  outputs a binary signal, a result of the comparison, via the inverters INV 1 , INV 4 , and the cell balance period voltage CB 1 , to the gate of the MOS transistor M 1 . Comparing the voltage VC 2 (VSS) with the cell mean voltage VCA(VSS), the comparator COMP 2  outputs a binary signal, a result of the comparison, via the inverters INV 2 , INV 5 , and the cell balance period voltage CB 2 , to the gate of the MOS transistor M 2 . Comparing the voltage VC 3 (VSS) with the cell mean voltage VCA(VSS), the comparator COMP 3  outputs a binary signal, a result of the comparison, via the inverters INV 3 , INV 6 , and the cell balance period voltage CB 3 , to the gate of the MOS transistor M 3 . 
         [0042]    When the voltage VC 1 (VSS) is higher than the cell mean voltage VCA(VSS), the logic circuit  31  generates a high level cell balance period voltage CB 1  and outputs it to the gate of the MOS transistor M 1  to turn on the MOS transistor M 1 , and bypasses charging current running through the cell C 1 . In addition, when the voltage VC 2 (VSS) is higher than the cell mean voltage VCA(VSS), the logic circuit  31  generates a high level cell balance period voltage CB 2  and outputs it to the gate of the MOS transistor M 2  to turn on the MOS transistor M 2 , and bypasses charging current running through the cell C 2 . In addition, when the voltage VC 3 (VSS) is higher than the cell mean voltage VCA(VSS), the logic circuit  31  generates a high level cell balance period voltage CB 3  and outputs it to the gate of the MOS transistor M 3  to turn on the MOS transistor M 3 , and bypasses charging current running through the cell C 3 . 
         [0043]    With the above operations, when any one of the respective cell voltages VC 1 , VC 2 , and VC 3  of the cell C 1 , the cell C 2 , and the cell C 3  is higher than the cell mean voltage VCA (any of them is a VSS standard voltage), balancing of the intercell voltages is achieved by bypassing charging current running through the cell whose voltage goes high. This enables charging while balancing the cell voltages among the cell C 1 , the cell C 2 , and the cell C 3 . 
       Modification of the Second Embodiment 
       [0044]      FIG. 6  is a circuit diagram showing a configuration of a charge control circuit according to a modification of the second embodiment and a peripheral circuit thereof. Two protection IC circuits of  FIG. 4  are cascaded (vertically stacked) (hereinafter, symbols of the two protection IC circuits are  2 - 1 ,  2 - 2 ) to control charging of more than three cells. In comparison with the protection IC circuit  2  in  FIG. 4 , each of the protection IC circuits  2 - 1 ,  2 - 2  of  FIG. 6  further includes: 
         [0000]    (1) a buffer circuit  17 B formed of a voltage follower circuit using an operational amplifier  17  configured to feed back an output voltage to an inverting terminal;
 
(2) a buffer circuit  18 B formed of a voltage follower circuit using an operational amplifier  18  configured to feed back an output voltage to an inverting terminal;
 
(3) a voltage subtraction and conversion circuit  19 A including four resistors R 3  and an operational amplifier  19 , and generating and outputting a cell mean voltage VCA(VSS), to be described below, by adding two input voltages and voltage converting into a ground potential VSS standard;
 
(4) a CAS terminal to be grounded, for example, when it is the lowest protection IC circuit, while the voltage VC 1  (high level) is applied, for example, when it is the highest protection IC circuit;
 
(5) an inverter INV 31  inverting a signal voltage of the CAS terminal to generate an XCAS signal;
 
(6) a MOS transistor M 11 , which does not connect the voltage VC 1  to an upper side potential terminal of a resistive voltage division circuit  21  on the basis of a high level XCAS signal, while connecting the voltage VC 1  to the upper potential terminal of the resistive voltage division circuit  21  on the basis of a low level XCAS signal; and
 
(7) a MOS transistor M 12  which does not connect the voltage VSS to a lower potential terminal of the resistive voltage division circuit  21  when the CAS terminal is at high level, while connecting the voltage VSS to the lower potential terminal of the resistive voltage division circuit  21  when the CAS terminal is grounded at low level.
 
         [0045]    In  FIG. 6 , the CAS signal of the protection IC circuit  2 - 2  goes to low level by grounding the CAS terminal of the protection IC circuit  2 - 2 , and the MOS transistor M 11  is turned off. In addition, the XCAS signal becomes a high level signal, and the MOS transistor M 12  is turned on. A VC 1  level (high level) voltage is inputted into the CAS terminal of the protection IC circuit. With this, the CAS signal in the protection IC circuit  1 - 1  goes to high level, and the MOS transistor M 11  is turned on. The XCAS signal goes to high level, and the MOS transistor M 12  is turned off, With this, a voltage of the CBU terminal in the protection IC circuit  2 - 1  becomes voltage the voltage VC 1 , and the CBL terminal of the protection IC circuit  2 - 1  becomes the ground potential VSS. In addition, since the MOS transistor M 12  of the protection IC circuit  2 - 1  is turned off, the VSS terminal and the CBL terminal of the protection IC circuit  2 - 1  are in an open state. Since the MOS transistor M 11  of the protection IC circuit  2 - 2  is turned off, the terminal of the voltage VC 1  and the CBU terminal of the protection IC circuit  2 - 2  enter an open state. Note that the CBL terminal of the protection IC circuit  2 - 1  and the CBU terminal of the protection IC circuit  2 - 2  are connected. 
         [0046]    In the charge control circuit configured as described above, after dividing a voltage between the voltage VC 1  of the cell C 1  and the voltage VSS of the cell C 3  with the three resistors R 2 , the resistive voltage division circuit  21 , the buffer circuits  17 B,  18 B, and the voltage subtraction and conversion circuit  10 A perform voltage buffering, subtraction and conversion into the ground potential VSS standard to generate a cell mean voltage VCA(VSS). For example, when balancing of cell voltages for six cells is achieved, the cell mean voltage VCA(VSS) is expressed by the following expression, wherein the VSS is the ground potential VSS of the protection IC circuit  2 - 2 . 
         [0000]      [Expression 2] 
         [0000]        VCA ( VSS )=( VC 1 −VSS )×(1 R )/(6 R )=( VC 1 −VSS )/6  (2)
 
         [0047]    Specifically, a value obtained by dividing a total voltage for the six cells by 6 is the cell mean voltage VCA (VSS). The buffer circuits  17 B,  18 B perform buffering of the respective voltage values. After computing a difference in two voltages from the respective buffering circuits  17 B,  18 B, the voltage subtraction and conversion circuit  19 A performs the conversion into the ground potential VSS standard to generate the cell mean voltage VCA(VSS). With the above, the cell mean voltage VCA(VSS) can be accurately generated even when the protection IC circuits  2 - 1 ,  2 - 2  are cascaded. Furthermore, similar to the cases in  FIG. 4  and  FIG. 5 , the logic circuit  31  compares the voltages VC 1 (VSS), VC 2 (VSS), and VC 3 (VSS) with the cell mean voltage VCA(VSS), generates predetermined cell balance period voltages CB 2 , CB 2 , and CB 3 , and turns on or off the MOS transistors M 1 , M 2 , and M 3  on the basis of them, thereby achieving balancing of the respective cell voltages. 
       Third Embodiment 
       [0048]      FIG. 7  is a circuit diagram showing a configuration of a charge control circuit according to a third embodiment and a peripheral circuit thereof. In comparison with the charge control circuit of  FIG. 2 , the charge control circuit of  FIG. 7  is characterized in that it includes resistive voltage division circuits  22 ,  23 , a comparator circuit  24 , and a logic circuit  32 , in place of the voltage subtraction and conversion circuit  10 , the offset voltage addition circuit  20 , and the logic circuit  30 . In the following, the differences will be described. 
         [0049]    In the resistive voltage division circuit  22 , a resistor R 11 , a resistor R 1 H, and a resistor R 11  are connected in series, wherein resistance values of the resistor R 11  and the resistor R 12  are set to a same value, and the resistor R 1 H is set to a resistance value ( 1/100, for example, to generate an offset voltage which is sufficiently smaller than a cell voltage) which is sufficiently smaller than the resistance value of the resistor R 11  or the resistor R 12 . The resistive voltage division of the resistive voltage circuit  22  generates: 
         [0000]    (1) a voltage VA obtained by adding a positive offset voltage to a mean voltage of the voltage VC 1  of the cell C 1  and the voltage VC 2  of the cell C 2 ; and
 
(2) a voltage VB obtained by adding a negative offset voltage to the mean voltage of the voltage VC 1  of the cell C 1  and the voltage VC 2  of the cell C 2 .
 
         [0050]    In the resistive voltage division circuit  23 , a resistor R 21 , a resistor R 2 H, and a resistor R 21  are connected in series, wherein resistance values of the resistor R 21  and the resistor R 22  are set to a same value, and the resistor R 2 H is set to a resistance value ( 1/100, for example, to generate an offset voltage which is sufficiently smaller than a cell voltage) which is sufficiently smaller than the resistance value of the resistor R 21  or the resistor R 22 . The resistive voltage division of the resistive voltage circuit  23  generates: 
         [0000]    (a) a voltage VC obtained by adding a predetermined positive offset voltage to a mean voltage of the voltage VC 2  of the cell C 2  and the voltage VC 3  of the cell C 3 ; and
 
(b) a voltage VD obtained by adding a predetermined negative offset voltage to the mean voltage of the voltage VC 2  of the cell VC 2  and the voltage VC 3  of the cell C 3 .
 
         [0051]    The voltages VA, VB, VC, VD generated as described above are expressed by the following expressions: 
         [0000]      [Expression 3] 
         [0000]        VA =( VC 1 −VC 3)×( R 1 H+R 12)/( R 11 +R 1 H+R 12)  (3)
 
         [0000]      [Expression 4] 
         [0000]        VB =( VC 1 −VC 3)×( R 12)/( R 11 +R 1 H+R 12)  (4)
 
         [0000]      [Expression 5] 
         [0000]        VC =( VC 2 −VSS )×( R 22 +R 2 H )/( R 21 +R 2 H+R 22)  (5)
 
         [0000]      [Expression 6] 
         [0000]        VD =( VC 2 −VSS )×( R 22)/( R 21 +R 2 H+R 22)  (6)
 
         [0052]    Next, when the comparator COMP 1  of the comparator circuit  22  compares the voltage VC 2  with the voltage VA, and the voltage VC 2  is higher than the voltage VA, the comparator COMP 1  outputs a high level comparison result signal comp  12   a  to the logic circuit  32 . Here, the voltage VA is a voltage obtained by adding the predetermined positive offset voltage to the mean voltage of the voltage VC 1  of the cell C 1  and the voltage VC 2  of the cell C 2 . Thus, if the voltage VC 2  and the voltage VA are compared and the voltage VC 2  is higher, it can be determined that the voltage VC 2  of the cell C 2  is higher than the voltage VC 1  of the cell C 1 . When the comparator COMP 2  compares the voltage VB with the voltage VC 2  and the voltage VC 2  is lower than the voltage VB, the comparator COMP 2  outputs a high level comparison result signal comp 12   b  to the logic circuit  32 . Here, the voltage VB is a voltage obtained by adding the predetermined negative offset voltage to the mean voltage of the voltage VC 1  of the cell C 1  and the voltage VC 2  of the cell C 2 . Thus, if the voltage VB and the voltage VC 2  are compared and the voltage VC 2  is lower, it can be determined that the voltage VC 1  of the cell C 1  is higher than the voltage VC 2  of the cell C 2 . When the comparator COMP 3  compares the voltage VC 3  with the voltage VC and the voltage VC 3  is higher than the voltage VC, the comparator COMP 3  outputs a high level comparison result signal comp 23   a  to the logic circuit  32 . Here, the voltage VC is a voltage obtained by adding the predetermined positive offset voltage to the mean voltage of the voltage VC 2  of the cell C 2  and the voltage VC 3  of the cell C 3 . Thus, if the voltage VC 3  and the voltage VC are compared and the voltage VC 3  is higher, it can be determined that the voltage VC 3  of the cell C 3  is higher than the voltage VC 2  of the cell C 2 . When the comparator COMP 4  compares the voltage VD with the voltage VC 3  and the voltage VC 3  is lower than the voltage VD, the comparator COMP 4  outputs a high level comparison result signal comp 23   b  to the logic circuit  32 . Here, the voltage VD is a voltage obtained by adding the predetermined negative offset voltage to the mean voltage of the voltage VC 2  of the cell C 2  and the voltage VC 3  of the cell C 3 . Thus, if the voltage VD and the voltage VC 3  are compared and the voltage VC 3  is lower, it can be determined that the voltage VC 2  of the cell C 2  is higher than the voltage VC 3  of the cell C 3 . 
         [0053]      FIG. 8  is a circuit diagram showing a configuration of the logic circuit  32  of  FIG. 7 . The logic circuit  32  in  FIG. 8  is configured to include one NOR gate NOR 11  and five inverters INV 11  to INV 15 . When the comparison result signal comp 12   b  is at high level, the logic circuit  32  outputs the high level cell balance period voltage CB 1  and turns on the MOS transistor M 1  to bypass charging current of the cell C 1 . When the comparison result signal comp 12   a  is at high level or when the comparison result signal comp 23   b  is at high level, the logic circuit  32  outputs the high level cell balance period voltage CB 2  and turns on the MOS transistor M 2  to bypass charging current of the cell C 2 . Furthermore, when the comparison result signal comp 23   a  is at high level, the logic circuit  32  outputs the high level cell balance period voltage CB 3  and turns on the MOS transistor M 3  to bypass charging current of the cell C 3 . With the above, charging is possible while balancing cell voltages among the cell C 1 , the cell C 2 , and the cell C 3 . 
       Modification of the Third Embodiment 
       [0054]      FIG. 9  is a circuit diagram showing a configuration of a charge control circuit according to a modification of the third embodiment and a peripheral circuit thereof. Specifically,  FIG. 9  shows the case in which the two protection IC circuits of  FIG. 7  (which are hereinafter assigned symbols  3 - 1 ,  3 - 2 ) are cascaded, wherein in comparison with the protection IC circuit  3  of  FIG. 7 , 
         [0000]    (1) the protection IC circuit  3 - 1  has three resistors R 01 , R 0 H, R 02  connected in series, and further includes a resistive voltage division circuit  25  which generates resistive voltage division voltages VI, VJ, a comparator circuit  26  having comparators COMP 9 , COMP 10 , a comparator circuit  61  which forcibly controls comparison result signals comp 01   a , comp 01   b  of the comparators COMP 9 , COMP 10  to low level when a potential difference between a voltage of a terminal VCU 1  and voltage VC 1  is 0.5V or less, and a connecting line  50  connecting the terminal VCU 1  with the terminal of the voltage VC 1 ,
 
(2) the protection IC circuit  3 - 2  has three resistors R 01 , R 0 H, R 02  connected in series, and further includes the resistive voltage division circuit  25  which generates resistive voltage division voltages VK, VL, a comparator circuit  27  having comparators COMP 11 , COMP 12 , and a comparator  62  which forcibly controls comparison result signals comp 34   a , comp 34   b  of the comparators COMP 11 , COMP 12  to low level when a potential difference between a voltage of a terminal VCU 2  and the voltage VC 4  is 0.5V or less.
 
         [0055]    Here, in the protection IC circuit  3 - 2 , in order to clearly describe a difference in operation from the protection IC circuit  3 - 1 , the symbols have been changed as shown below. Specifically, 
         [0000]    (1) output voltages of the resistive voltage division circuit  22  are VE, VF;
 
(2) output voltages of the resistive voltage division circuit  23  are VG, VH;
 
(3) comparators of the comparator circuit  24  are COMP 5  to COMP 8 , and their comparison result signals are comp 45   a , comp 45   b , comp 56   a , comp 56   b;  
 
(4) cell balance period voltages from the logic circuit  32 - 2  are CB 4 , CB 5 , CB 6 ; and
 
(5) cell symbols are C 4 , C 5 , and C 6 .
 
         [0056]    In addition, a positive electrode of the cell C 3  is connected to the terminal VCU 2  of the protection IC circuit  3 - 2 , the terminal CRL 1  of the protection IC circuit  3 - 1  is connected to the terminal CBL 2  of the protection IC circuit  3 - 2 , and the terminal CBL 2  of the protection IC circuit  3 - 2  is grounded. In addition, resistance values of the resistors R 01 , R 0 H, and R 02  in the resistive voltage division circuits  25 ,  26  are set similar to the resistive voltage division circuits  22 ,  23 . Note that the protection IC circuit  3 - 1  has the terminal VCU 1  for upper level connection and the ground terminal VSS 1 , and the protection IC circuit  3 - 2  has the terminal VCU 2  for upper level connection and the ground terminal VSS 2 . 
         [0057]    Resistive voltage division of the resistive voltage division circuit  25  of the protection IC circuit  3 - 1  generates the voltage V 1  obtained by adding the predetermined positive offset voltage to the mean voltage of the voltage VC 1  of the cell C 1  and the voltage VC 2  of the cell C 2 , and the voltage VJ obtained by adding the predetermined negative offset voltage to the mean voltage of the voltage VC 1  of the cell C 1  and the voltage VC 2  of the cell C 2 . In the protection IC circuit  3 - 1 , the voltages VA to VD are generated similar to  FIG. 7 . Resistive voltage division of the resistive voltage division circuit  25  of the protection IC circuit  3 - 2  generates the voltage VK obtained by adding the predetermined positive offset voltage to the mean voltage of the voltage VC 3  of the cell C 3  and the voltage VC 4  of the cell C 4 , and the voltage VL obtained by adding the predetermined negative offset voltage to the mean voltage of the voltage VC 3  of the cell C 3  and the voltage VC 4  of the cell C 4 . In the protection IC circuit  3 - 2 , the voltages VE to VH are generated similar to the voltages VA to VD in  FIG. 7 . Therefore, the voltages VA to VL are expressed by the following expressions: 
         [0000]      [Expression 7] 
         [0000]        VA =( VC 1 −VC 3)×( R 1 H+R 12)/( R 11 +R 1 H+R 12)  (7)
 
         [0000]      [Expression 8] 
         [0000]        VB =( VC 1 −VC 3)×( R 12)/( R 11 +R 1 H+R 12)  (8)
 
         [0000]      [Expression 9] 
         [0000]        VC =( VC 2 −VSS 1)×( R 22 +R 2 H )/( R 21 +R 2 H+R 22)  (9)
 
         [0000]      [Expression 10] 
         [0000]        VD =( VC 2 −VSS 1)×( R 22)/( R 21 +R 2 H+R 22)  (10)
 
         [0000]      [Expression 11] 
         [0000]        VE =( VC 4 −VC 6)×( R 1 H+R 12)/( R 11 +R 1 H+R 12)  (11)
 
         [0000]      [Expression 12] 
         [0000]        VF =( VC 4 −VC 6)×( R 12)/( R 11 +R 1 H+R 12)
 
         [0000]      [Expression 13] 
         [0000]        VG =( VC 5 −VSS 2)×( R 22 +R 2 H )/( R 21 +R 2 H+R 22)  (13)
 
         [0000]      [Expression 14] 
         [0000]        VH =( VC 5 −VSS 2)×( R 22)/( R 21 +R 2 H+R 22)  (14)
 
         [0000]      [Expression 15] 
         [0000]        VI =( VCU 1 −VC 2)×( R 01 +R 0 H )/( R 01 +R 0 H+R 02)  (15)
 
         [0000]      [Expression 16] 
         [0000]        VJ =( VCU 1 −VC 2)×( R 01)/( R 01 +R 0 H+R 02)  (16)
 
         [0000]      [Expression 17] 
         [0000]        VK =( VCU 2 −VC 5)×( R 01 +R 0 H )/( R 01 +R 0 H+R 02)  (17)
 
         [0000]      [Expression 18] 
         [0000]        VL =( VCU 2 −VC 5)×( R 01)/( R 01 +R 0 H+R 02)  (18)
 
         [0058]    The comparators COMP 1  to COMP 4  of the comparator circuit  24  in the protection IC circuit  3 - 1  respectively operate similarly to  FIG. 7 , and output the comparison result signals comp 12   a , comp 12   b , comp 23   a , comp 23   b  to the logic circuit  32 - 1 . In addition, the comparators COMP 5  to COMP 5  of the comparator circuit  24  in the protection IC circuit  3 - 2  respectively operate similarly to the comparators COMP 1  to COMP 2  in  FIG. 7 , and output the comparison result signals comp 45   a , comp 45   b , comp 56   a , comp 56   b  to the logic circuit  32 - 1 . 
         [0059]    When the comparator COMP 9  of the comparator circuit  26  compares the voltage VC 1  with the voltage V 1 , and the voltage VC 1  is higher than the voltage V 1 , the comparator COMP 9  outputs a high level comparison result signal comp 01   a  to the logic circuit  32 - 1 . However, when a voltage difference between the voltage of the terminal VCU 1  and the voltage VC 1  is 0.5V or less, the comparator COMP 9  forcibly sets the comparison result signal comp 01   a  to low level. In  FIG. 9 , since VCU 1 =VC 1 , the comparison result signal comp 01   a  is at low level. When the comparator COMP 10  compares the voltage VJ with the voltage VC 1  and the voltage VC 1  is lower than the voltage V 1 , the comparator COMP 10  outputs a high level comparison result signal comp 01   b  to the logic circuit  32 - 1 . However, when a voltage difference between the voltage of the terminal VCU 1  and the voltage VC 1  is 0.5V or less, the comparator COMP 10  forcibly sets the comparison result signal comp 01   b  to low level. In  FIG. 9 , since VCU 1 =VC 1 , the comparison result signal comp 01   b  is at low level. 
         [0060]    When the comparator COMP 11  of the comparator circuit  27  compares the voltage VC 4  with the voltage VK, and the voltage VC 1  is higher than the voltage VK, the comparison result signal comp 34   a  is at high level. The voltage VK is a voltage obtained by adding the predetermined positive offset voltage to the mean voltage of the voltage VC 3  of the cell C 3  and the voltage VC 4  of the cell C 4 . Thus, if the voltage VC 4  and the voltage VK are compared and the voltage VC 4  is higher, it can be determined that the voltage VC 4  of the cell C 4  is higher than the voltage VC 3  of the cell C 3 . When the comparator COMP 12  compares the voltage VL with the voltage VC 4 , and the voltage VC 1  is higher than the voltage VL, the comparison result signal comp 34   b  is at high level. The voltage VL is a voltage obtained by adding the predetermined negative offset voltage to the mean voltage of the voltage VC 5  of the cell C 5  and the voltage VC 6  of the cell C 6 . Thus, if the voltage VL and the voltage VC 4  are compared and if the voltage VC 4  is lower when the voltage VC 1  is higher than the voltage VL, it can be determined that the voltage VC 3  of the cell C 3  is higher than the voltage VC 4  of the cell C 4 . 
         [0061]      FIG. 10  is a circuit diagram showing configurations of the logic circuits  32 - 1 ,  3 - 2  of  FIG. 9 . The logic circuit  32 - 1  in  FIG. 10  is configured to include three NOR gates NOR 11 , NOR 21 , and NOR 22  and five inverters INV 12 , INV 13 , INV 15 , INV 21 , and INV 22 . The logic circuit  32 - 2  is configured to include three NOR gates NOR 11 , NOR 21 , and NOR 22 , and five inverters INV 12 , INV 13 , INV 15 , INV 21 , and INV 22 . 
         [0062]    When the comparison result signal comp 01   a  is at high level or when the comparison result signal comp  126  is at high level, the logic circuit  32 - 1  outputs the high level cell balance period voltage CB 1 , which turns on the MOS transistor M 2  to bypass charging current of the cell C 1 . When the comparison result signal comp 12   a  is at high level or when the comparison result signal comp 23   b  is at high level, the logic circuit  32 - 1  outputs the high level cell balance period voltage CB 2 , which turns on the MOS transistor M 2  to bypass charging current of the cell C 2 . When the comparison result signal comp 23   a  is at high level or when the voltage of the terminal CRL 1  (which is an output voltage of the inverter  22  of the logic circuit  32 - 2  and the comparison result signal  34   b ) is at high level, the logic circuit  32 - 1  outputs the high level cell balance period voltage CB 3 , which turns on the MOS transistor M 3  to bypass charging current of the cell C 3 . 
         [0063]    When the comparison result signal comp 34   a  is at high level or when the comparison result signal comp 45   b  is at high level, the logic circuit  32 - 2  outputs the high level cell balance period voltage CB 4 , which turns on the MOS transistor M 4  to bypass charging current of the cell C 4 . When the comparison result signal comp 45   a  is at high level or when the comparison result signal comp 56   b  is at high level, the logic circuit  32 - 2  outputs the high level cell balance period voltage CB 5 , which turns on the MOS transistor M 5  to bypass charging current of the cell C 5 . When the comparison result signal comp 56   a  is at high level and the voltage of the terminal CBL 2  (which is a ground potential in the embodiment) is at high level, the logic circuit  32 - 2  outputs the high level cell balance period voltage CB 5 , which turns on the MOS transistor M 6  to bypass charging current of the cell C 6 . 
         [0064]    With the above, charging is possible while balancing cell voltages among the cells C 1  to C 6 . 
         [0065]    As described above, with the charge control circuit according to the present invention and the battery device provided therewith, balancing of cell voltages is easier to achieve than the conventional technique, and charging of voltages of all cells close to full charge becomes easier. In addition, the charge control circuit and the battery device provided therewith can be configured with simple circuits and provided at low cost. 
         [0066]    Although the modifications of the embodiments described above describe the case of six cells, the present invention is not limited to this, and cascading of two or more protection IC circuits enables charge control of eight or more cells. In addition, although the embodiments describe the case of three cells, the present invention is not limited to these embodiments, and a similar configuration is possible even in the case of two cells. 
       INDUSTRIAL APPLICABILITY 
       [0067]    As described above in detail, with the charge control circuit according to the present invention and the battery device provided therewith, balancing of cell voltages is easier to achieve than the conventional technique, and charging of voltages of all cells close to full charge becomes easier. In addition, the charge control circuit and the battery device provided therewith can be configured with simple circuits and provided at low cost. 
         [0068]    Although the preferred embodiments of the present invention have been described, it should be understood that the present invention is not limited to these embodiments, various modifications and changes can be made to the embodiments.