Abstract:
In generating first and second voltages (VPP and WLL) for respectively activating and deactivating transistors of a DRAM array that transfer charge to cells of the DRAM array, the second voltage can be lowered to compensate for a threshold voltage (Vt) that is lower than a nominal threshold voltage value (Vt NOM ). Furthermore, the first voltage is tracked together with the second voltage in order to maintain a generally constant voltage swing (V sw ) therebetween.

Description:
FIELD OF THE INVENTION 
     The invention relates generally to generation of VPP and WLL voltages for a DRAM array and, more particularly, to generation of such voltages for use with a lower-than-nominal array threshold voltage. 
     BACKGROUND OF THE INVENTION 
     In conventional DRAM arrays, information is stored in a given DRAM cell by driving a wordline WL appropriately to activate a transfer transistor (whose gate is connected to the wordline) and thereby transfer charge into the cell capacitor. In general, the retention time of the cell, and thus the performance thereof, increases with the amount of charge transferred to the cell. The transfer transistor of a given cell is activated for transferring charge into the cell by application of a voltage VPP to the wordline, and the transfer transistor is switched off by application of a voltage WLL (wordline low) to the wordline. This is illustrated generally in FIG.  1 . 
     In order to transfer the maximum possible charge to the cell, a large VPP must be applied to the gate of the transfer transistor via wordline WL. More specifically, VPP must be much greater than the threshold voltage Vt of the transfer transistor. Due to performance (i.e., speed) requirements, the time available to transfer the charge into the cell is limited, and is typically reduced with each new generation of DRAM arrays. Increases in the VPP voltage permit reductions in the charge transfer time. However, due to reliability concerns, the maximum VPP is limited due to the maximum allowable electric field across the gate oxide of the transfer transistor. 
     Due to normal process variations, the threshold voltage Vt of the transfer transistor can be higher than the nominal threshold voltage Vt NOM , which reduces the voltage difference VPP−Vt (also referred to as the overdrive), thereby reducing the charge transfer to the cell. This disadvantageously impacts the cell&#39;s retention capability and thus the product yield. 
     Conventional DRAM array chips include VPP tracking circuits that basically measure the threshold voltage Vt of one (or several) transfer transistors, and then increase the VPP voltage, if required, to maintain a desired overdrive (VPP−Vt), thereby insuring that the maximum charge is always transferred to the cell. Although such VPP tracking can be used to compensate for a higher-than-normal Vt, nevertheless the maximum value of VPP is limited by the aforementioned gate oxide reliability considerations. In fact, due to the thinner gate oxides used in the latest DRAM technologies, the nominal VPP value is approaching the reliability limit of the gate oxide, so the aforementioned VPP tracking is no longer a viable option because the VPP voltage typically cannot be increased beyond its nominal value. 
     When a DRAM array has a lower-than-nominal threshold voltage, the WLL voltage may not completely shut off the transfer transistor, in which case the charge can leak out of the cell capacitor, thereby disadvantageously reducing the cell retention time and disadvantageously impacting the product yield. Conventional DRAMs typically use a grounded WL scheme, wherein the WLL voltage is fixed and cannot be lowered below 0V. Thus, with the grounded WL scheme, a lower-than-nominal threshold voltage cannot be compensated for by reducing the WLL voltage. 
     It is therefore desirable to provide compensation for lower-than-nominal threshold voltage in a DRAM array, thereby improving the cell retention time and the product yield. 
     The present invention utilizes a negative wordline low (NWLL) scheme that permits lowering WLL to compensate for a lower-than-nominal threshold voltage. Further according to the invention, VPP is tracked together with WLL in order to maintain a generally constant voltage swing therebetween, thereby advantageously avoiding damage to the gate oxides in the wordline driver circuits. After determining a desired overdrive voltage (VPP−Vt) and a desired voltage swing between VPP and WLL, VPP can be tracked with the lower-than-nominal threshold voltage to maintain the desired overdrive voltage, and WLL can be tracked with VPP to maintain the desired voltage swing between VPP and WLL. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a conventional arrangement for applying VPP and WLL voltages to the gate of a transfer transistor that transfers charge to a capacitor of a DRAM array. 
     FIG. 2 diagrammatically illustrates exemplary embodiments of a voltage tracking circuit which tracks VPP and WLL with a lower-than-nominal Vt according to the invention. 
     FIG. 3 illustrates exemplary operations which can be performed by the voltage tracking circuit of FIG.  2 . 
     FIG. 4 graphically illustrates the operation of the voltage tracking circuit of FIG.  2 . 
    
    
     DETAILED DESCRIPTION 
     The present invention recognizes that a lower-than-nominal DRAM array threshold voltage can be compensated for by using a negative wordline low (NWLL) scheme and appropriately lowering WLL advantageously to compensate for the lower-than-nominal threshold voltage. However, and as can be seen from FIG. 1, lowering the WLL voltage while maintaining a fixed VPP voltage will undesirably increase the voltage across the gate oxides of the wordline driver transistors  11  and  12 . Therefore, according to the invention, the WLL voltage in a NWLL scheme can be lowered to compensate for a lower-than-nominal threshold voltage, and VPP can advantageously track together with WLL in order to maintain a generally constant voltage swing between VPP and WLL and thus a generally constant voltage across the gate oxides of the driver transistors  11  and  12 . 
     FIG. 2 diagrammatically illustrates exemplary embodiments of a voltage tracking circuit which permits VPP and WLL to be tracked together with a lower-than-nominal array threshold voltage Vt. In FIG. 2, a single transfer transistor  21  of a DRAM array is used as a test transistor. The test transistor  21  is specially wired to a known impedance l so that the drive current of the test transistor  21  can be measured, and a signal (e.g., a voltage)  23  indicative of the drive current can be provided to a comparator/operational amplifier circuit  22 . The circuit  22  includes another input  24  which is coupled to receive a target signal analogous to the signal  23 , but indicative of the drive current that the test transistor  21  would be expected to produce under nominal threshold voltage conditions. Thus, the target signal  24  corresponds to the nominal threshold voltage Vt  NOM . 
     The comparator/operational amplifier circuit  22  is responsive to the input signals  23  and  24  for determining whether the actual threshold voltage Vt  ACT  (represented by signal  23 ) of the DRAM array is less than the nominal threshold voltage Vt  NOM  (represented by signal  24 ). If the circuit  22  determines that the actual threshold voltage is below the nominal threshold voltage, then an output  25  from the circuit  22  signals a VPP and WLL voltage generator  26  to reduce its WLL output accordingly to compensate for the lower-than-nominal threshold voltage. The generator  26  also reduces its VPP output to maintain a generally constant voltage swing between VPP and WLL. 
     The generator  26  initially sets VPP and WLL to respective nominal values. The nominal value of VPP can be determined, for example, by adding the desired overdrive voltage to the nominal threshold voltage. Thus, for a nominal array threshold voltage, the nominal VPP applied to the gate of the test transistor  21  will produce the desired overdrive and a corresponding expected drive current through the impedance I. However, a lower-than-nominal threshold voltage will produce a higher-than-desired overdrive and thus a larger than expected drive current through the impedance I. The comparator/operational amplifier circuit  22  will detect this condition and respond by outputting at  25  to generator  26  a signal indicative of how much the actual threshold voltage differs from the nominal threshold voltage. The generator  26  responds to this signal by decreasing the value of VPP until the desired overdrive is achieved and circuit  22  signals at  25  that the expected current is produced through the impedance I. The generator  26  also adjusts WLL in conjunction with VPP to maintain the desired constant voltage swing between VPP and WLL. 
     On the other hand, if the current through the impedance I is less than or equal to the current that is expected with the nominal value of VPP applied to the gate of test transistor  21 , this indicates that the array threshold voltage is greater than or equal to the nominal threshold voltage, so the comparator/operational amplifier circuit  22  signals the generator  26  to maintain VPP and WLL at their respective nominal levels. 
     FIG. 3 illustrates exemplary operations which can be performed by the voltage tracking circuit of FIG. 2, typically at the time that the DRAM array is powered up. At  31 , VPP is set to its nominal value, VPP NOM , by adding the desired overdrive voltage V OD  to the nominal threshold voltage Vt NOM . Also at  31 , WLL is set to its nominal value, WLL NOM , by subtracting from VPP NOM  the value of the voltage swing V SW  desired between VPP and WLL. It is then determined at  32  whether the actual threshold voltage VtAcT is less than the nominal threshold voltage Vt NOM . If not, then operations are completed and the nominal values VPP NOM  and WLL NOM  will be used. On the other hand, if the actual threshold voltage is less than the nominal threshold voltage, then a new VPP, VPP NEW , is generated as the sum of the desired overdrive voltage V OD  and the actual threshold voltage Vt  ACT . At  34 , a new WLL, WLL NEW , is generated by subtracting from VPP NEW  the value of the desired voltage swing V SW . 
     The exemplary voltage tracking operations described above with respect to FIGS. 2 and 3 are illustrated by a graphic example in FIG.  4 . As described above, WLL can be advantageously lowered to compensate for a lower-than-nominal threshold voltage, while still advantageously maintaining an approximately constant voltage swing (V SW ) between VPP and WLL, and an approximately constant overdrive voltage V OD . 
     Although exemplary embodiments of the invention are described above in detail, this does not limit the scope of the invention, which can be practiced in a variety of embodiments.