Abstract:
An offset cancellation scheme for sense amplification is described. The scheme consists of group of transistors which are selectively coupled to high and low voltage levels via multi-phase timing. This results in a voltage level on nodes of interest which are a function of transistor mismatch. The resulting voltage levels act to compensates for the transistor mismatch, thereby improving the reliability of the sense amplifier in the presence of process non-idealities. The offset cancellation scheme is applicable to numerous types of sense amplifiers.

Description:
[0001]    An offset cancellation scheme for sense amplification is described. The offset cancellation scheme is applicable to numerous types of sense amplifiers and is enabled with a multi-phase timing scheme. This application claims the benefit of priority of U.S. Provisional Patent Application No. 61/202,805 filed Apr. 8, 2009 which is incorporated herein by reference in its entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    Embedded memories are critical blocks in modern system-on-chip (SOC) integrated circuit. On many modern integrated circuits embedded memory arrays consume more than half of the die area. The penalty in terms of latency resulting from an off-chip memory access makes it desirable to include on-chip caches which are as large as possible. As CMOS technology scale deep into the nanometric regime the density of bitcells has significantly increased, resulting in much larger embedded memory for the same die area. 
         [0003]    While embedded memories are important performance enablers, they come with many challenges. The difficulties in integrating large, dense embedded memories are primarily related to manufacturing. The scaling of CMOS has brought with it an increase in the process variability which designers must contend with. While variability used to be primarily systematic, as feature sizes scale below 100 nm random variability has become increasingly problematic. Systematic variability causes circuits to vary from die to die or wafer to wafer, while random variability can cause variations in the properties of adjacent transistors. There are numerous causes of random variability, including sub-wavelength lithography, random dopant fluctuations, line edge roughness and negative bias temperature instability (NBTI). Increasingly large embedded memories are being integrated into ICs, and as such the variability over the entire array can be very large. If sufficiently large design margins are not used in the design phase, variability can result in failures. 
         [0004]    An SRAM array consists of a number of SRAM bitcells which are organized in multiple rows and columns in a plurality of blocks, as shown in  FIG. 1 . Each bitcell stores one bit of data; a logic value of zero or one. An bitcell usually has a control terminal wordline and a pair of data terminal called bitlines. During the read operation, the wordline becomes active and the cell draws a current from either one of the bitlines depending on the logic value stored in the cell. Voltage or current sense amplifiers are used to sense which one of the bitlines are affected by the cell current to detect the logic value that is stored in the cell. In order to save area, the sense amplifiers may be shared among a plurality of columns through multiplexer switches. 
         [0005]    Sense amplifiers are important peripheral circuits in an SRAM array. Sense amplifiers are intrinsically amplifiers, and as such they operate by taking a input signal and amplifying it. In the case of a sense amplifier the goal is to take the differential signals which exist on the bitlines and output a full-swing signal which represents the state of the selected bitcell. If the amplifier has an intrinsic offset due to process variability then the size of the input signal will need to be large enough to compensate for that offset, or else an incorrect decision will be made. Transistor mismatch in the symmetric circuits that construct a sense amplifier play a key role in the creation of static offset for the sense amplifier. 
       SUMMARY OF THE INVENTION 
       [0006]    A sense amplifier scheme which allows for the compensation of offsets. Compensating for offsets in sense amplifier circuits offers higher sensitivity to the SRAM cell current. Hence, the sense amplifier scheme allows for a shorter cell access time which results in a higher data stability and faster operation. 
         [0007]    In accordance with one aspect of the present invention there is provided a pair of nodes connected to a pair of transistors. Also provided are a pair of levels, one high and one low. The nodes are precharged to an identical initial level. The nodes are connected to the complementary level through the pair of transistors such that the new level on the nodes will be a function of any difference between the pair of transistors. 
         [0008]    The SRAM read operation takes place and the difference in the levels on the pair of nodes acts against to compensate for the intrinsic offset in the sense amplifier. 
         [0009]    In accordance with an aspect of the present invention there is provided a . . . 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    An embodiment of the present invention will now be described by way of example only with reference to the following drawings in which: 
           [0011]      FIG. 1  shows a typical SRAM architecture (the prior art) 
           [0012]      FIG. 2  shows an embodiment of a proposed scheme for offset cancellation 
           [0013]      FIG. 3  shows another embodiment of a proposed scheme for offset cancellation 
           [0014]      FIG. 4  shows how the proposed scheme will be connected to an SRAM column 
           [0015]      FIG. 5  shows an embodiment connecting the proposed scheme to the column pre-charge circuit. 
           [0016]      FIG. 6  shows a typical timing scheme associated with the proposed scheme shown in 
           [0017]      FIG. 7  shows another embodiment of a sense amplifier with the proposed scheme 
           [0018]      FIG. 8  shows an embodiment showing a sense amplifier with proposed scheme 
           [0019]      FIG. 9  a typical timing scheme associated with the proposed scheme shown in  FIG. 8   
           [0020]      FIG. 10  shows another embodiment showing a sense amplifier with proposed scheme 
           [0021]      FIG. 11  shows an embodiment showing a sense amplifier with proposed scheme 
           [0022]      FIG. 12  shows another embodiment showing a sense amplifier with proposed scheme 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0023]    For convenience, like structures in drawings will be referenced by like numerals in the description. 
         [0024]      FIG. 2  illustrates the invention by way of a circuit diagram and associated waveforms to illustrate the operation of the scheme. The transistors of interest are NMOS transistors labelled M 1  and M 2 . As the voltage at the gate of these transistors is at a high voltage level the transistors are considered to be on. When signal ctrl_ 1  is activated the associated switches close and the nodes nodeA and nodeB are connected to the low voltage level. When signal ctrl_ 2  is activated the associated switches close and the nodes nodeA and nodeB are connected to the high voltage level through the NMOS transistors M 1  and M 2 . An NMOS transistor is not able to fully pass a high voltage level, and as such the final voltage on the nodes nodeA and nodeB are less than the high voltage level. Moreover the final voltages level on nodeA will be a function of the transistor M 1  and the final voltage level on nodeB will be a function of the transistor M 2 . 
         [0025]    As an example, if the threshold voltage of transistor M 1  is higher than the threshold voltage of transistor M 2 , the final voltage on nodeA will be less than the final voltage on nodeB. The difference in the voltage level on nodeA compared with nodeB will be proportional to the difference in the threshold voltage between transistors M 1  and M 2 . 
         [0026]      FIG. 3  illustrates the invention by way of a circuit diagram and associated waveforms to illustrate the operation of the scheme. The transistors of interest are PMOS transistors labelled M 1  and M 2 . As the voltage at the gate of these transistors is at a low voltage level the transistors are considered to be on. When signal ctrl_ 1  is activated the associated switches close and the nodes nodeA and nodeB are connected to the high voltage level. When signal ctrl_ 2  is activated the associated switches close and the nodes nodeA and nodeB are connected to the low voltage level through the PMOS transistors M 1  and M 2 . An PMOS transistor is not able to fully pass a low voltage level, and as such the final voltages on the nodes nodeA and nodeB are higher than the low voltage level. Moreover the final voltage level on nodeA will be a function of the transistor M 1  and the final voltage level on nodeB will be a function of the transistor M 2 . 
         [0027]    As an example, if the threshold voltage of transistor M 1  is higher than the threshold voltage of transistor M 2 , the final voltage on nodeA will be higher than the final voltage on nodeB. The difference in the voltage level on nodeA compared with nodeB will be proportional to the difference in the threshold voltage between transistors M 1  and M 2 . 
         [0028]    The invention can be applied to various sense amplifier architectures. To illustrate the implementation of this scheme several embodiments are provided using both current sense amplifier architectures and voltage sense amplifier architectures. 
         [0029]      FIG. 4  is a conceptual diagram showing one possible embodiment of the invention where the offset cancellation scheme is utilized in conjunction with a current sense amplifier. The transistors of interest as labelled M 1  and M 2 . In this scheme the transistors of interest also function as multiplexing transistors. This is a current sense amplifier as the sense amplifier senses the current through the transistors M 1  and M 2 . When the signal ctrl_ 1  is enabled the nodes nodeA and nodeB are connected to a low voltage level. When the signal ctrl_ 2  is enabled the nodes nodeA and nodeB are connected to a high voltage level through the NMOS transistors M 1  and M 2 . After this the read operation begins with an SRAM cell being enabled via a control signal. 
         [0030]      FIG. 5  is a circuit diagram showing the details of the embodiment  400 . In this configuration the nodes nodeA and nodeB are commonly referred to as bitlines. 
         [0031]      FIG. 6  shows the associated waveforms for the embodiment  400 . During the read operation the bitlines develop a differential voltage. After a period of time the sense amplifier is enabled via a control signal SAE. Once the signal SAE is enabled the current sense amplifier turns on and amplifies the differential voltage on the bitlines to full swing. 
         [0032]      FIG. 7  is a conceptual diagram showing one possible implementation where the offset cancellation scheme is utilized in conjunction with a voltage sense amplifier. The transistors of interest as labelled M 1  and M 2  and in this embodiment are NMOS transistors. This is a voltage sense amplifier as the sense amplifier senses the voltage at the gates of the transistors M 1  and M 2 . During the offset cancellation stage the input to the transistors M 1  and M 2  is held at a high voltage level in order that they remain on. During the offset cancellation stage the transistors M 3  and M 4  are off in order to isolate the sense amplifier from the bitlines. When the signal ctrl_ 1  is enabled the nodes nodeA and nodeB are connected to a low voltage level through the transistors M 1  and M 2 . M 1  and M 2  are NMOS transistors and as such nodes nodeA and nodeB are able to reach the low voltage level. When the signal ctrl_ 2  is enabled the nodes nodeA and nodeB are connected to a high voltage level through the NMOS transistors M 1  and M 2 . After this the transistors M 1  and M 2  will be connected to the SRAM cell via multiplexing transistors M 3  and M 4  and the sense amplifier circuitry is enabled. 
         [0033]      FIG. 8  is a circuit diagram showing one embodiment of the scheme  700  and it is denoted by the number  800 . In this configuration the nodes nodeA and nodeB are also the output nodes of the sense amplifier. Transistors M 3  and M 4  are multiplexing transistors which connect the sense amplifier to the SRAM cells via complementary signals known as bitlines (BL and BLB). 
         [0034]    The gates of the NMOS transistors M 1  and M 2  need to remain at a high voltage level during the offset cancellation stage. The sense amplifier enable signal SAE is used to control the voltage level at the gates of transistors M 1  and M 2 . During the offset cancellation stage the signal SAE is low and as such the input signals to the transistors M 1  and M 2  are held at a high voltage level via transistors M 5  and M 6 . Moreover, the signal SAE is low thus transistors M 3  and M 4  are off, blocking the signals BL and BLB. During the offset cancellation stage first the signal ctrl_ 1  is enabled. This turns on transistors M 7  and M 8 , thus connecting nodes nodeA and nodeB to a low voltage level through transistors M 1  and M 2 . As transistors M 1  and M 2  are NMOS transistors, nodes nodeA and nodeB are able to fully reach the low voltage level. Next the signal ctrl_ 1  is disabled and the signal ctrl_ 2  is enabled. This turns off transistors M 7  and M 8  and turns on transistors M 9  and M 10 . With transistors M 9  and M 10  on, nodes nodeA and nodeB are connected to a high voltage level through transistors M 1  and M 2 . As transistors M 1  and M 2  are NMOS transistors, nodes nodeA and nodeB are unable to fully reach the high voltage level. Moreover, when signal ctrl_ 2  is disabled the voltage level on nodeA will be a function of the transistor M 1  and the voltage level on nodeB will be a function of the transistor M 2 . 
         [0035]    Next the sense amplification stage begins when the signal SAE is enabled, turning on transistors M 3 , M 4  and M 11  and turning off the transistors M 5  and M 6 . This connects the signals BL and BLB to the transistors M 1  and M 2 . Also, turning on transistor M 11  enables the sense amplifier circuitry. 
         [0036]      FIG. 9  shows the associated waveforms for 800. After the offset cancellation stage completes the bitlines develop a differential voltage. The bitlines are isolated from the sense amplifier until the signal SAE is enabled. Once the signal SAE is enabled the voltage sense amplifier turns on and amplifies the differential voltage on the bitlines to full swing. 
         [0037]      FIG. 10  is a circuit diagram showing a second embodiment of the scheme  700  and it is denoted by the number  1000 . In this configuration the nodes nodeA and nodeB are also the output nodes of the sense amplifier. Transistors M 3  and M 4  are multiplexing transistors which connect the sense amplifier to the SRAM cells via complementary signals known as bitlines (BL and BLB). 
         [0038]    The gates of the NMOS transistors M 1  and M 2  need to remain at a high voltage level during the offset cancellation stage. The sense amplifier enable signal SAE is used to control the voltage level at the gates of transistors M 1  and M 2 . During the offset cancellation stage the signal SAE is low and as such the input signals to the transistors M 1  and M 2  are held at a high voltage level via transistors M 5  and M 6 . Moreover, the signal SAE is low thus transistors M 3  and M 4  are off, blocking the signals BL and BLB. During the offset cancellation stage first the signal ctrl_ 1  is enabled. This turns on transistors M 7  and M 8 , thus connecting nodes nodeA and nodeB to a low voltage level through transistors M 1  and M 2 . As transistors M 1  and M 2  are NMOS transistors nodes nodeA and nodeB are able to fully reach the low voltage level. Next the signal ctrl_ 1  is disabled and the signal ctrl_ 2  is enabled. This turns off transistors M 7  and M 8  and turns on transistors M 9  and M 10 . With transistors M 9  and M 10  on, nodes nodeA and nodeB are connected to a high voltage level through transistors M 1  and M 2 . As transistors M 1  and M 2  are NMOS transistors, nodes nodeA and nodeB are unable to fully reach the high voltage level. Moreover, when signal ctrl_ 2  is disabled the voltage level on nodeA will be a function of the transistor M 1  and the voltage level on nodeB will be a function of the transistor M 2 . 
         [0039]    Next, the sense amplification stage begins the signal SAE is enabled, turning on transistors M 3 , M 4  and M 11  and turning off the transistors M 5  and M 6 . This connects the signals BL and BLB to the transistors M 1  and M 2 . Also, turning on transistor M 11  enables the sense amplifier circuitry. 
         [0040]    The waveforms in  FIG. 9  are also applicable to embodiment  1000 . 
         [0041]      FIG. 11  is a conceptual diagram denoted by the number  1100  showing one possible implementation where the offset cancellation scheme is utilized in conjunction with a voltage sense amplifier. The transistors of interest as labelled M 1  and M 2  and in this embodiment are PMOS transistors. This is a voltage sense amplifier as the sense amplifier senses the voltage at the gates of the transistors M 1  and M 2 . During the offset cancellation stage the input to the transistors M 1  and M 2  is held at a low voltage level in order that they remain on. During the offset cancellation stage the transistors M 3  and M 4  are off in order to isolate the sense amplifier from the bitlines. When the signal ctrl_ 1  is enabled the nodes nodeA and nodeB are connected to a high voltage level through the transistors M 1  and M 2 . M 1  and M 2  are PMOS transistors and as such nodes nodeA and nodeB are able to reach the high voltage level. When the signal ctrl_ 2  is enabled the nodes nodeA and nodeB are connected to a low voltage level through the PMOS transistors M 1  and M 2 . After this the transistors M 1  and M 2  will be connected to the SRAM cell via multiplexing transistors M 3  and M 4  and the sense amplifier circuitry is enabled. 
         [0042]      FIG. 12  is a circuit diagram showing one embodiment of the scheme  1100  and it is denoted by the number  1200 . In this configuration the nodes nodeA and nodeB are also the output nodes of the sense amplifier. Transistors M 3  and M 4  are multiplexing transistors which connect the sense amplifier to the SRAM cells via complementary signals known as bitlines (BL and BLB). 
         [0043]    The gates of the PMOS transistors M 1  and M 2  need to remain at a low voltage level during the offset cancellation stage. The sense amplifier enable signal SAE is used to control the voltage level at the gates of transistors M 1  and M 2 . During the offset cancellation stage the signal SAE is low and as such the input signals to the transistors M 1  and M 2  are held at a low voltage level via transistors M 5  and M 6 . Moreover, the signal SAE is low thus transistors M 3  and M 4  are off, blocking the signals BL and BLB. During the offset cancellation stage first the signal ctrl_ 1  is enabled. This turns on transistors M 7  and M 8 , thus connecting nodes nodeA and nodeB to a high voltage level through transistors M 1  and M 2 . As transistors M 1  and M 2  are PMOS transistors, nodes nodeA and nodeB are able to fully reach the high voltage level. Next the signal ctrl_ 1  is disabled and the signal ctrl_ 2  is enabled. This turns off transistors M 7  and M 8  and turns on transistors M 9  and M 10 . With transistors M 9  and M 10  on, nodes nodeA and nodeB are connected to a low voltage level through transistors M 1  and M 2 . As transistors M 1  and M 2  are PMOS transistors, nodes nodeA and nodeB are unable to fully reach the low voltage level. Moreover, when signal ctrl_ 2  is disabled the voltage level on nodeA will be a function of the transistor M 1  and the voltage level on nodeB will be a function of the transistor M 2 . 
         [0044]    Next the sense amplification stage begins the signal SAE is enabled, turning on transistors M 3 , M 4  and M 11  and turning off the transistors M 5  and M 6 . This connects the signals BL and BLB to the transistors M 1  and M 2 . Also, turning on transistor M 11  enables the sense amplifier circuitry. 
         [0045]    The waveforms in  FIG. 9  are also applicable to embodiment  1200 .