Abstract:
An information transmission network in which a plurality of information processing stations are connected in parallel to a bus line is disclosed. Each station has a communication control means and an information processor. Each control means is capable of establishing command over the bus line to the exclusion of all other stations. While command is established, the commanding station can communicate with all other stations. After one sequence of communication, command is transferred. If the station presently in command fails, the failure to transfer command in a predetermined time will be noted and another station with highest priority will assume command. If the station to which command is transferred is not operating properly, the station presently in command will detect a failure of the former station to respond to transfer of command and will thereupon transfer command to another station.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to an information transmission system wherein a plurality of information processing apparatuses distributed over a wide area are connected in parallel with each other via a commonly provided information transmitting bus line, and information is arbitrarily transmitted between these information processing apparatuses. 
     In the case where a plurality of information processing apparatuses are distributed over a comparatively wide area so that each of the apparatuses is separated from others by comparatively long distances, interconnection of all the information processing apparatuses through separate transmission lines is not economical because such an arrangement not only requires a greater amount of transmission lines but also requires the provision of a plurality of information transmitting devices in each apparatus. To eliminate the latter disadvantage of the above described arrangement, there has been proposed an information transmitting system of the type shown in FIG. 1, wherein a plurality of information processing apparatuses, 1 through N, are connected in parallel with a common information transmitting bus line CL. Under the control of a bus line control device LC, information transmission between these apparatuses is arbitrarily carried out over the bus line CL. 
     However, such an information transmitting system requires a bus line control device, LC, capable of supervising and controlling the bus line against duplicate use of the bus line, and any trouble in the bus line control device, LC, tends to cause a total failure of the information transmitting system. For this reason, the bus line control device LC is made of high precision circuits operable in a multiplex manner, thus requiring a high cost of manufacture. 
     SUMMARY OF THE INVENTION 
     The object of the present invention is to provide a novel information transmitting system wherein a common information transmitting bus line is used without requiring a costly bus line control device, information transmission can be achieved between any of the plurality of information processing apparatuses, and any possibility of causing total failure of the system by a single error can be eliminated. 
     For the achievement of the above-mentioned object, the information transmission system according to this invention is characterized in that each of the information processing apparatuses is provided with means capable of establishing a command over the information transmitting bus line. Under such command information is transmitted between the same information processing apparatus, now establishing command, and another information processing apparatus. After the termination of the information transmission, the command of the information transmitting bus line is sequentially transferred from the apparatus having established command over the information transmitting bus line to other information processing apparatuses. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing the construction of a conventional information transmission system; 
     FIG. 2 is a block diagram showing the construction of the information transmission system according to the present invention; 
     FIG. 3a is a time chart showing signals present on the bus line when station 1 in FIG. 2 has established command; 
     FIG. 3b is a time chart showing the signals present on the bus line when station 2 in FIG. 2 has established command; 
     FIG. 3c is a time chart showing signals present on the bus line when station 3 in FIG. 2 has established command; and 
     FIG. 4 is a block diagram showing a concrete example of the information processing apparatus according to this invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 2 is a block diagram showing the basic construction of the invention. In the figure, 1 through N designate information processing apparatuses comprising respectively communication controls TR1 through TRN, each having a bi-directional communication function, and information processing portions A 1  through A N . The apparatuses are connected in parallel through the communication controls TR 1  through TR N  with a commonly provided information transmitting bus line CL. The communication control TR or each information processing apparatus functions not only to transmit information between the information processing portion A and the bus line CL, but also to establish command over the bus line. When the communication control means TR establishes command over the bus line CL, it delivers, by the request of information processing portion A, an information transmitting instruction toward another information processing apparatus, and actively operates to transmit and receive information for the information processing portion A. When the communication control means TR does not establish command over the bus line, it obeys the instruction from another information processing apparatus which establishes command over the bus line and passively operates in transmitting and receiving information for the information processing portion A. The information processing apparatuses are assigned with their own addresses 1 through N, respectively, and when a communication control means TR transmits information over the bus line CL, an address designating the destined information processing apparatus is added to the information. When the communication control TR receives information from the bus line CL, it selectively receives information having an address assigned to it. 
     One example of the information transmitting procedure in the system according to this invention is indicated in FIG. 3. 
     It is first assumed that the communication control means TR 1  of the No. 1 information processing apparatus 1 establishes command over the bus line CL. This is realized by a command establishing signal ELS 1  delivered from the communication control means TR 1  over the bus line as shown in FIG. 3a. The communication control means TR of the other information processing apparatuses reset their own command establishing devices thereby to prevent duplicated establishment of command over the bus line. In the case where the information processing portion A 1  of the information processing apparatus 1 has data DT 2  to be transmitted to the information processing apparatus 2, the communication control means TR 1  delivers a transmission request signal SEQ 2  including the address 2 of the information processing apparatus 2. Upon receiving the transmission request signal SEQ 2 , the communication control means TR 2  of the information processing apparatus 2 detects that the signal is directed to its own apparatus 2, and when the apparatus 2 is in a receivable state, the communication control means TR 2  delivers a reception ready signal ACK 2  over the bus line. When the communication control means TR 1  receives the reception ready signal ACK 2  from TR 2 , it reads out the data DT 2  from the information processing portion A 1  and transmits the same through the bus line to the information processing apparatus 2. The communication control TR 2  of the apparatus 2 receives the data DT 2  and checks for errors to confirm the correctness of the received data. When the confirmed data is written into the information processing portion A 2  of the apparatus 2, the communication control means TR 2  delivers a reception completion signal RAK 2  over the bus line CL. When the communication control TR 1  receives the reception completion signal RAK 2 , a series of data transmission procedures terminates. The communication control means TR 1  thus terminates the data transmission, then transfers the command of the bus line in accordance with a predetermined sequential order or utterly arbitrarily to, for instance, the information processing apparatus 2 by sending a command transferring signal SEL 2 . Simultaneously, the command establishing device in the communication control means TR 1  is reset. 
     The communication control means TR 2  of the apparatus 2, upon reception of the command transferring signal SEL 2 , sets the command establishing device and then delivers a command establishing signal ELS 2  as shown in FIG. 3b over the bus line CL. The command of the bus line by the communication control means TR 2  is thus established. However, if there is no demand for data transmission in the information processing apparatus 2, the communication control means TR 2  immediately delivers a command transfer signal SEL 3  to the communication control means TR 3  of the apparatus 3. 
     Upon reception of the command transfer signal SEL 3 , the communication control means TR 3  sets the command establishing device and delivers a command establishing signal ELS 3  as shown in FIG. 3c over the bus line CL. When the apparatus 3 has a demand to read out the data in the information processing apparatus N, the communication control TR 3  delivers a reception request signal REQ N  directed to the communication control TR N  of the apparatus N over the bus line. When the apparatus N is in a transmissible state, the communication control means TR N  which has received the reception request signal REQ N , immediately reads out the data DT N  stored in the information processing portion A N  and transmits the same to the communication control means TR 3 . The communication control means TR 3  receives the data DT N , checks for error, and if any error is found, delivers a reception reclaiming signal ARQ N  toward the communication control means TR N . The communication control means TR N  thus retransmits the data DT N , and when the data DT N  is correctly received by the communication control means TR 3 , the data is transferred into the information processing portion A 3 , and the series of data transmitting operations terminates. The communication control means TR 3  resets its own command establishing device and delivers a command transferring signal SEL 4  toward the subsequent information processing apparatus 4. 
     From the above description, it will be apparent that information transmission can be carried out between any arbitrary pair of information processing apparatuses by repeating the above described procedures. 
     In FIG. 4, an example of the communication control means included in each information processing apparatus is indicated in block diagram form, where each block represents a known device. In the drawing, CL designates the commonly provided information transmitting bus line, A the information processing portion, and TR the communication control means connected with the information processing portion A through data lines D 5  and D 6  and control lines G 1  through G 4 . The communication control TR has a receiver RED and a transmitter SED both connected directly to the common bus line CL. When it is required, the receiver RED and the transmitter SED can modulate and demodulate the related signals. The output side of the receiver RED is connected with a receiving register RD 1  made of a shift register for the series-parallel conversion of the output signal. More specifically, when the register RD 1  stores one word or one block of information having a predetermined number of bits, it delivers a buffer-full signal BF R  toward a reception control device C 1  thereby to report the reception of information. Upon reception of the buffer-full signal BF R , the reception control device C 1  reads out the data stored in the register RD 1  in parallel, and carries out interpretation and error check operations on the data. The reception control device C 1  further generates various control signals depending on the results of such operations, and sends these signals to a command establishing device M, timers T 1  and T 2 , a transmission control device C 2 , and a received data buffer register RD 2  . 
     The transmission control device C 2  delivers various control data in accordance with the control signals from the reception control device C 1 , command establishing device M, timers T 1  and T 2 , and adds an address of destination to the data read out of a transmission data buffer register, the resultant data being delivered in parallel to a transmitting register SD 1  which is made of a shift register to effectuate parallel-series conversion on the resultant data. When the data is stored in the transmitting register SD 1 , the same register delivers a buffer-full signal BF S  causing the transmitter SED to read out the data bit by bit in series from the register SD 1  and to transmit the data over the bus line CL. 
     Furthermore, AD 1  designates an own address setting device, and AD 2  designates a subsequent address setting device which sets the address of an information processing apparatus to which the command for controlling the bus line is to be transferred. The times T 1  and T 2  are provided for supervising the bus line for the purpose of preventing interruption of data transmission due to the fault of the communication control presently having command or the communication control to which the command is to be transferred. 
     The operation of the communication control is as follows. 
     When a command transfer signal SEL is delivered to the bus line CL from the communication control means of the apparatus presently having command over the bus line, receivers RED in the communication control means TR of all the information processing apparatuses receive the command transfer signal SEL and store the same in their receiving registers RD 1 . When the receiving register RD 1  stores a predetermined number of bits of the signal, a buffer-full signal BF R  is delivered to the reception control device C 1 . Upon reception of the buffer-full signal, the reception control device C 1  starts to operate to read out the data stored in the register RD 1 , to interpret the control signals included in the data, and to compare the address attached to the data with its own address. As a result, the reception control device C 1  in the communication control means whose address coincides with the address attached to the data SEL delivers a command setting signal S 1  to the input of the command establishing device M. The command establishing device M is thereby set, and the communication control means TR of the information processing apparatus establishes command over the bus line. 
     Setting of the command establishing device M causes it to deliver a signal S 2  toward the transmission control device C 2  thereby to instruct the transmission of a command establishing signal ELS, having its own address attached thereto, which is given by the own address setting device AD 1 . The transmission control device C 2  effectuates the address attaching operation, and the resultant signal is sent through the data line D 3  to the transmission register SD 1  under the condition of the register SD 1  being still vacant. When the signal is stored in the transmission register SD 1  and a buffer-full signal BF S  is delivered to the transmitter SED, the latter starts to operate thereby transmitting the signal stored in the register SD 1  bit by bit in series over the information transmitting bus line CL. By the transmission of the signal ELS attached with the address of the information processing apparatus, the fact that the communication control means TR has established command over the bus line CL is reported to the communication control means TR of all the other information processing apparatuses. 
     When the command establishing signal ELS from the communication control TR of the information processing apparatus now establishing command over the bus line is received in all the remaining information processing apparatuses through the receiver RED and the receiving register RD 1 , the reception control device C 1  delivers a signal S 3  to reset the command establishing device M because the address attached to the signal ELS does not coincide with its own address. At this time, in the communication control TR means of the information processing apparatus now having established command, the reception control device C 1  does not deliver the signal S 3  and the command establishing device M is held in the set state. Thus, the communication control TR from which the command establishing signal ELS is delivered acquires the command of the transmission bus line CL and can operate actively to control the bus line. 
     After the transmission of the command establishing signal ELS from the communication control means TR, the transmission register SD 1 , now in a vacant state, delivers a buffer empty signal BE S . Upon reception of the buffer empty signal BE S , the transmission control device C 2  surveys the existence or nonexistence of data in a transmitting data buffer register SD 2  depending on the state of a data existence indicating signal S 10 . In the transmitting data buffer register SD 2 , data from the information processing portion A, when such a demand exists in the portion A, has been sent through a data line D 6  together with the address of the destined information processing apparatus and stored therein. When the data buffer register SD 2  stores such data, it delivers the signal S 10  in the &#34;1&#34; state, and when it does not store such data it delivers the signal S 10  in the &#34;0&#34; state. Now it is assumed that data from the information processing portion A is stored in the buffer register SD 2 , and the signal S 10  is in the &#34;1&#34; state. The transmission control device C 2  knows of the existence of such data from the &#34;1&#34; state of the signal S 10  and instantaneously reads out the address of the destined information processing apparatus stored in the buffer register SD 2  together with the data to be transmitted. The control device C 2  further attaches this address to a transmission request signal SEQ and sends out the resultant signal to the transmission register SD 1  through the data line D 3 . The transmitter SED transmits the signal in the transmission register SD 1  over the transmission bus line CL. 
     The reception control device C 1  in the communication control means TR in the other information processing apparatuses which have received the transmission request signal SEQ interpret the signal SEQ and simultaneously therewith compare the address attached to the signal with their own address. When the two addresses coincide, the reception control device C 1  operates as indicated by the signal SEQ. That is, the device C 1  surveys the existence or nonexistence of data in the received data buffer register RD 2  from the condition of the data existence indicating signal S 11 . The received data buffer register RD 2  temporarily stores data received and transfers the data under the control of the reception control device C 1  to the information processing portion A through the data line D 5 . When data is stored in the buffer register RD 2 , the latter delivers the signal S 11  in the &#34;1&#34; state, and when no data is stored, it delivers the signal S 11  in the &#34;0&#34; state. 
     When the signal S 11  is in &#34;0&#34; state indicating a vacancy of the buffer register RD 2 , the reception control device C 1  sends out a response instruction signal S 4  in &#34;1&#34; state to the transmission control device C 2 , and when the signal S 11  is in &#34;1&#34; state indicating the buffer register RD 2  is not vacant, the device C 1  sends out the response instruction signal S 4  in &#34;0&#34; state to the transmission control device C 2 . The transmission control device C 2  generates a reception ready response signal ACK when the signal S 4  is &#34;1&#34;, and a reception not ready response signal NAK when the signal S 4  is &#34;0&#34;, and sends the signal ACK or NAK to the transmission register SD 1 . The transmitter SED sends out the response signal ACK or NAK over the transmission bus line CL to the source of the transmission request signal SEQ, that is, the apparatus now establishing command over the bus line CL. 
     In the information processing apparatus now establishing command, when the communication control means TR interprets that the response signal sent from the communication control means in the destined aparatus is the reception ready signal ACK, the reception control device C 1  delivers a data transmission instruction signal S 5  to the transmission control device C 2  in the same TR. The transmission control device C 2  thus reads out the data attached with the address of the destination apparatus stored in the buffer register SD 2 , and sends the data to the transmission register SD 1 . The transmitter SED in turn sends out the data attached with the address of the destination over the bus line CL. 
     In the communication control TR of the destination apparatus, the data thus transmitted over the bus line CL is received through the receiver RED and reception register RD 1 . When the reception control device C 1  judges that the address attached to the data now received coincides with its own address, the data in the reception register RD 1  is transferred through the data line D 2  to the reception buffer register RD 2 . When a data transmission termination signal ETX from the transmitting apparatus is received in the TR of the destination apparatus, the reception control device C 1  carries out error check on the data stored in the buffer register RD 2 , and depending on whether error is found or not found, the control device C 1  delivers a reception response instruction signal S 6  in &#34;0&#34; or &#34;1&#34; state, respectively, toward the transmission control device C 2 . The device C 2  thus sends out through the transmitter SED a reception completion signal RAK when the instruction signal S 6  is in &#34;1&#34; state, and a reception incorrect signal RNK when the instruction signal S 6  is in &#34;0&#34; state, over the transmission bus line CL. 
     When the communication control TR in the information processing apparatus now establishing command receives the reception completion signal RAK or the reception incorrect signal RNK sent from the TR of the destination apparatus after the former control TR has transmitted the data, it operates as follows. The reception control device C 1  in the communication control TR interprets the content of the signal received through the receiver RED and stored in the reception register RD 1 , and if it finds out that the signal is the reception completion signal RAK, a transmission completion instruction signals S 7  is sent from the device C 1  to the transmission control device C 2 . The transmission control device C 2  thus detects that the series of data transmission has terminated, and sends out a reset signal S 12  to the tranmission buffer register SD 2  to reset the same, and also another reset signal S 8  to the command establishing device M to reset the same device for releasing the establishment of the command. Simultaneous therewith, the transmission control device C 2  delivers a command establishing signal ELS attached with an address beforehand set in the subsequent address setting device AD 2  to be sent out through the transmitter SED over the transmission bus line CL. 
     On the contrary, when the reception control device C 1  judges that the content of the response signal is the reception incorrect signal RNK, the reception control device C 1  delivers the data transmission instruction signal S 5  toward the transmission control device C 2 . The transmission control device C 2  thus reads out the data stored in the transmission buffer register SD 2  and carries out the retransmission of the same data. In the case where the reception completion signal RAK cannot be obtained from the destination apparatus even after repetition of the retransmission procedure for a predetermined number of times, the transmission control device C 2  sends a signal C 1  to the information processing portion A thereby to inform the portion A of the fact that the transmission of the data was unsuccessful, and also sends a reset signal S 8  to the command establishing register M to release the establishment of the command. Simultaneous therewith, the transmission control device C 2  generates a command establishing signal ELS and attaches thereto an address beforehand set in the subsequent address setting device AD 2  and sends out the resultant signal through the transmitter SED to the transmission bus line CL. 
     The communication control means TR operates as described during the period from the establishment of the command to the release of the same. In the case where command is established in the communication control means TR but the information processing portion A has no demand to transmit data, and in the case where after transmission of the transmission request signal SEQ a reception not ready signal NAK is received from the destination apparatus, the reception control device C 1  in the communication control TR immediately delivers a command releasing signal S 3  to the command establishing register M. The command is thus released and transferred to the subsequent information processing apparatus as described hereinbefore. Furthermore, the communication control may be so constructed that when it receives a data reception request signal REQ from the communication control TR of other information processing apparatus establishing command, it reads out the data stored in the transmission data buffer register SD 2  and sends the data toward the communication control TR of the information processing apparatus now establishing command. When so constructed, the communication control TR of an information processing apparatus establishing command can operate in both of requesting data transmission to any other apparatus and requesting data reception from any other apparatus. 
     The communication control TR of an information processing apparatus thus aquires the command by the command transferring action of the information processing apparatus establishing command, and once the first information processing apparatus aquires the command, it can operate actively in requesting other apparatus to transmit and receive data. When there is no demand to transmit or receive data in its own apparatus or when a series of data transmission operations based on the demand has terminated, the communication control means TR operates immediately in transferring the command to another information processing apparatus in a predetermined sequence. Thus it is apparent that every individual information processing apparatus indicated in FIG. 2 can transmit its data under the above described operation of the communication control of the apparatus with the command over the transmission bus line transferred in a predetermined sequence. 
     All the above described operations of the information processing apparatuses are based on the assumption that the communication control of each information processing apparatus has no fault and therefore can operate normally. However, if a fault occurs in any of the communication control means of these apparatuses, there is a possibility of the command transferring action becoming impossible, as will be mentioned below. 
     Firstly, when a fault occurs in the communication control of an information processing apparatus presently in command, the command transferring signal SEL for transferring the command to the subsequent apparatus cannot be issued from the faulty communication control which makes it impossible to transfer the command. Secondly, when a fault occurs in the communication control means in the information processing apparatus to which the command is to be transferred, the command establishing signal ELS will not be received and acted upon thus also making it impossible to transfer the command. When the transfer of command is made impossible as described above, the information processing apparatus having command disappears and the transmission of data between the information processing apparatuses is interrupted, thus causing the total failure of the system. 
     In order to prevent the total failure of the system caused by the faults in the communication controls of the information processing apparatuses, timers T 1  and T 2  constituting a watch mechanism are provided as shown in FIG. 4 in the communication control means. 
     The timer T 1  in the communication control TR is set to a time length Ta slightly longer than that of one word or one block of words used in each of the information processing apparatuses. The time length Ta is varied depending on the priority for transferring the command to the information processing apparatus. More specifically, the time length Ta is made shorter when the command transferring priority of the given information processing apparatus is high. The timer T 1  is started by S 1  or S 3 . After the termination of the time length Ta of the timer T 1 , a signal ST 1  is delivered from the timer T 1 . However, the timer T 1  may be restarted before the termination of the time period Ta if a reset or restart signal is applied thereto, and in this case the time counting operation of the timer T 1  is restarted from zero. The S 1  delivered from the reception control device C 1  when it receives command transferring signal SEL destined for itself and the signal S 3  also delivered from the reception control device C 1  when the latter receives a command establishing signal ELS from any other apparatus are used for the timer reset signal. The output signal ST 1  from the timer T 1  is applied to the command establishing device M as a set signal. 
     On the other hand, the timer T 2  is set to have a time length Tb slightly longer than that required for receiving the command establishing signal ELS from another information processing apparatus after the command transferring signal SEL has been sent. The timer T 2  operates in such a manner that it starts its time counting operation from the instant when the transmission control device C 2  delivers a timer set signal S 9  simultaneous with the delivery of the command transferring signal SEL. It delivers a time output signal ST 2  at the termination of the preset time length Tb. However, if the timer T 2  receives a reset signal from the reception control device C 1  during its time counting operation, the timer T 2  is reset thereby to stop the time counting operation. The output signal ST 2  from the timer T 2  is applied to the transmission control device C 2  as an instruction signal for the jumped transfer of the command. When the transmission control device C 2  receives the signal ST 2  from the timer T 2 , it operates to transmit a command transferring signal SEL attached with an address beforehand set in the subsequent address setting device AD 2  plus one. 
     When all the communication controls of the information processing apparatuses are operating in normal manner, the reception control device C 1  in the communication control of each of the information processing apparatuses receives the command transferring signal SEL or the command establishing signal ELS within a shorter period than the time period Ta set in the timer T 1 , a reset signal S 3  or a set signal S 1  for the command establishing device M is delivered in correspondence therewith, and either one of the signals is applied to the reset input of the timer T 1 , whereby the timer T 1  has no possibility of generating the output signal ST 1 , and the command establishing device M is never set by the timer T 1 . 
     However, if a fault occurs in the communication control means TR of the information processing apparatus now establishing command, and no command transferring signal SEL is delivered from the communication control TR toward the information processing apparatus to which the command is to be transferred subsequently within the due time, no command transferring signal is emitted from any of the information processing apparatuses. In this situation, timers T 1  in the communication controls TR of the information processing apparatuses successively arrive at the ends of their time periods Ta set therein. However, the timer within the communication control TR of an information processing apparatus having the highest priority delivers firstly the output signal ST 1  and the command establishing device M in the communication control TR is thereby set to establish command by the same information processing apparatus. Thus the command establishing signal ELS is immediately delivered from the communication control means of the same information processing apparatus, and since the communication control means of other information processing apparatuses receive the command establishing signal ELS before the termination of the time periods Ta set in their timers T 1 , the timer T.sub. 1 in these communication control means are all reset. Thus it is apparent that when the transfer of command becomes impossible by a fault in the communication control TR in the information apparatus now establishing command, the command is automatically transferred to one of the normally operating information processing apparatuses having the highest priority, the subsequent operations being carried out as described hereinbefore. 
     When a fault occurs in the communication control TR in an information processing apparatus to which command is subsequently to be transferred, command is transferred jumping over the faulty communication control means TR to another information processing apparatus to which the command is to be transferred. That is, in the communication control means TR which delivers the command transferring signal SEL to the information processing apparatus set in the subsequent address setting device AD 2 , the transmission control device C 2  delivers simultaneous therewith a set signal S 9  to the timer T 2  thereby to set the timer into its time counting operation. If no signal for establishing command ELS is received in the communication control means TR from the information processing apparatus set in the subsequent address setting device AD 2  because of a fault in the communication control means TR of the latter apparatus within the time period Tb, the timer T 2  will deliver an output signal ST 2  to the transmission control device C 2 . Upon reception of the signal ST 2 , the transmission control device C 2  adds one to the address set in the subsequent address setting device AD 2 , and acts to transmit again another command transferring signal SEL attached with the address thus added with one over the transmission bus line CL, thereby to transfer command in jumping over the information processing apparatus set in the subsequent address setting device AD 2  to the second subsequent information processing apparatus. Thus, it is apparent that even in the case of a fault in the communication control means TR to which the command is to be transferred, command is transferred by the operation of the timer T 2  in jumping manner to the second subsequent information processing apparatus without causing any interruption of the data transmission. 
     The data transferring operation between the communication control means TR and the information processing portion A, both included in the same information processing apparatus, will now be described somewhat in detail. 
     In the data transmitting operation, the information processing portion A detects a signal G 2  indicating the vacancy of the buffer register SD 2 , and when the signal G 2  is in the state showing the vacancy, the portion A sets the data into the transmission buffer register SD 2 . The register SD 2  sends the signal S 10  in the state &#34;1&#34; showing the possession of data to the transmission control device C 2  when the data setting operation of the portion A terminates. The transmission control device C 2  sends a reset signal S 12  to the register SD 2  when the data transmission of the data set in the register SD 2  completes thereby to reset the buffer register SD 2  to prepare for the subsequent data. 
     In the data reception operation, when received data is taken into the reception buffer register RD 2 , the register RD 2  sends out a reception completion signal G 3  to the information processing portion A. Upon reception of the signal G 3 , the information processing portion A reads out the data through the data line D 5 , and when the reading operation completes, the information processing portion A sends a reset signal G 4  to the buffer register RD 2  for preparing the register to store the subsequent data. 
     As will be apparent from the above description, according to this invention, a plurality of information processing apparatuses are connected in parallel with a commonly provided transmission bus line, and data are transmitted and received between these information processing apparatuses in a manner such that each of the information processing apparatuses sequentially establishes the command of the transmission bus line and carries out transmission of data with other information processing apparatuses. Thus, the requirement of a commonly provided bus line control device in the conventional arrangement is obviated and the cost for the entire information transmission system can be economized. Furthermore, when any fault occurs in the information processing apparatus, the command for the bus line is established in a manner jumping over the faulty information processing apparatus, and data can be transmitted and received between the remaining information processing apparatuses. 
     Although C 1  and C 2  are shown as single blocks, respectively, it will be appreciated by anyone of ordinary skill in the art that the latter the blocks may consist of several individual commonly used elements for carrying out the conventional functions ascribed to C 1  and C 2 , e.g. decoding a given signal and outputing a certain S pulse in response thereto, responding to a given S pulse by generating a preset pulse code, etc.