Abstract:
An electrically non conducting material disposed within one or more of the voids of a probe card between a substrate thereof and a tester interface to reinforce the substrate against flexing, bending, and warpage.

Description:
FIELD 
     This invention relates to the fabrication of integrated circuits. More particularly, this invention relates to integrated circuit testing. 
     BACKGROUND 
     In the manufacture of integrated circuits, such as semiconductor devices, the integrated circuits are typically formed on a substrate, such as a silicon wafer. During and after the fabrication process, the integrated circuit is tested to evaluate the electrical characteristics of the integrated circuit. One test method for flip-chip integrated circuits involves the use of probe cards having probes pins configured to align with contact pads of the integrated circuit. Probe cards generally include an electrically non conducting substrate having electrical traces that are in electrical communication with the probe pins, which are disposed one side of the substrate. A plurality of solder balls are typically disposed on the opposite side of the substrate for electrical communication with the tester. 
     The probe card is brought into contact with the integrated circuit using a probe station, or prober, with the probe pins contacting the electrical connections on the integrated circuit. The prober aligns the probe pins of the probe card with the electrical connections of the integrated circuit and applies force to the probe pins to obtain good electrical contact between the probe pins and the electrical connections of the integrated circuit, which are typically solder bumps. The probe pins are repeatedly pushed against integrated circuits during testing operations. The repeated force applied to the probe card during such testing tends to deform or warp the substrate of the probe card. Over time, this deformation of the planarity of the probe card substrate tends to inhibit the probe pins from making good electrical contact with the integrated circuits being tested. 
     What is needed, therefore, is a method for fabricating probe cards so that their substrates are more resistant to deformation, as compared to the substrates of conventional probe cards. 
     SUMMARY 
     The above and other needs are met a probe card for testing an integrated circuit having electrical contacts. An interface member connects the probe card to a test station. An electrically non conducting substrate is provided with a first side, a second side, and electrically conducting traces. A plurality of electrically conducting probes are disposed adjacent the second side of the substrate. The probes make electrical connections with the traces, and the probes are also for making forceful contact and electrical connection with the electrical contacts of the integrated circuit. 
     Electrically conducting members are disposed between the first side of the substrate and the interface member. The electrically conducting members make electrical connection between the traces of the substrate and the interface member, and are disposed such that at least one void is formed between the first side of the substrate and the interface member. An electrically non conducting material is disposed within the at least one void, so as to substantially fill the at least one void. The electrically non conducting material reinforces the substrate against deformation during testing of the integrated circuit, when forceful contact is made between the probes and the electrical contacts of the integrated circuit. 
     Disposing electrically non-conducting material in the voids of the substrate in accordance with the present invention tends to substantially decrease the degree to which the substrate deforms during use. This results in improved testing and reduced costs. 
     In various preferred embodiments of the invention, the substrate is a glass filed plastic, and the electrically conducting members are solder bumps. The at least one void are then areas between the solder bumps. Preferably the electrically non conducting material within the .void is either an epoxy or a spacer, most preferably made of the same material as the substrate. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Further advantages of the invention are apparent by reference to the detailed description when considered in conjunction with the figures, which are not to scale so as to more clearly show the details, wherein like reference numbers indicate like elements throughout the several views, and wherein: 
     FIG. 1 is a cross sectional view depicting a probe card in accordance with a preferred embodiment of the invention, and 
     FIG. 2 is a partial cross sectional view of a prior art probe card, showing deformation of the probe card substrate. 
    
    
     DETAILED DESCRIPTION 
     The invention enables the fabrication of probe cards for integrated circuit testing having improved construction and function. FIG. 1 depicts a probe card  10  that has been fabricated in accordance with the invention. The probe card  10  is used for testing an integrated circuit  12 , such as a flipchip integrated circuit on a silicon chip, with a plurality of electrical contacts, such as solder bumps  8 . 
     The probe card  10  includes a tester interface member  18  for electrically connecting the card  10  to test circuitry. A plurality of solder balls  2  are located between side  22  of the member  18  and side  24  of a substrate  26 . The substrate  26  is preferably an electrically non conducting substrate, such as a glass filled plastic, having electrical traces that are in electrical communication with solder bumps  4 , disposed adjacent the opposite side  30  of the substrate  26 . The solder bumps  4  are electrically connected to a plurality of pin-like probes  6  extending in a direction generally perpendicular to and away from side  30  of the substrate  26 . The probes  6  are preferably arranged to line up with the bumps  8  of the integrated circuit  12 . The probes  6  are preferably made from an electrically conducting material such as tungsten, beryllium, copper, or alloys of these and other electrically conducting materials such as gold, silver, palladium, platinum, zinc, and the like. An encapsulant  34  preferably provides an exterior seal around the substrate  26 . 
     One or more voids  36  are formed between the substrate  26  and the side  22  of the interface member, in locations that are not occupied by the solder bumps  2 . The voids  36  of the probe card  10  are preferably substantially filled with an electrically non-conducting fill material  42 . The fill material  42  is preferably an epoxy that is applied during fabrication of the probe card  10 , so as to substantially fill all areas between the substrate  26  and the member  18  that are not occupied by a solid member, such as one of the solder bumps  2 . In the alternative, a spacer  44  may be positioned in the voids  36 . The spacer  44  is preferably an electrically non conducting or insulating solid material configured to fit within one of the voids  36 . Preferably, each spacer  44  is made of the same material as the substrate  26 . 
     In yet another embodiment, a combination of filler material  42  and one or more spacers  44  are used to fill the voids. In one embodiment, only the voids  36  that oppose the probes  6  are filled with the filler material  42  or the spacers  44 . However, in alternate embodiments all of the voids  36  are filled with either the filler material  42  or the spacers  44 . In yet a further embodiment, the voids  36  that oppose the probes  6  are only filled with the filler material  42  or the spacer  44  to that extent which is necessary to inhibit the deformation of the probe card  10  under normal use. 
     During testing of the integrated circuit  12 , the probes  6  are aligned with the bumps  8  and an external force is applied to urge the probes  6  against the bumps  8  to obtain good electrical contact between the probes  6  and the bumps  8 . The probes  6  are preferably repeatedly urged against the bumps  8  repeatedly during testing. As represented in FIG. 2, in the absence of the spacer  44  or the filler material  42 , the repeated force applied to substrate  26  by forcing the probes  6  against the bumps  8  during testing tends to deform the substrate  26 . This disruption of the planarity of the substrate  26  would result in many of the probes  6  failing to make good electrical contact with the bumps  8 . 
     Substantially occupying the voids  36  between the tester interface  18  and the substrate  26  with an electrically non-conducting material in accordance with the invention tends to substantially decrease the incidence of deformation of the substrate  26 . 
     It is appreciated that the materials described above, while providing an especially preferred application of the invention, are by way of example only, and that other materials are compatible with the materials, structures, and processes of integrated circuit processing are also generally applicable to the invention as disclosed herein. 
     The foregoing embodiments of this invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise form disclosed. Obvious modifications or variations are possible in light of the above teachings. The embodiments are chosen and described in an effort to provide illustrations of the principles of the invention and its practical application, and to thereby enable one of ordinary skill in the art to utilize the invention in various embodiments and with various modifications as is suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.