Abstract:
In a pixel array, each column of the pixel array is coupled to one of a plurality of first and second channels of a driver. A first and second control signals are generated. Polarities of the first channels are inversed when a logic level of the first control signal changes and polarities of the second channels are inversed when a logic level of the second control signal changes. Only the logic level of one of the first and second control signals changes in response to each transition of scan periods.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a method and circuit for driving a display. More particularly, the present invention relates to a method and circuit for driving an LCD (liquid crystal display) panel using a new inversion scheme. 
         [0003]    2. Description of the Related Art 
         [0004]      FIG. 1  shows a physical structure  100  of an LCD driving system using COG (chip-on-glass) and WOA (wire-on-array) technology. The structure  100  includes a glass substrate  102  having a pixel array  104  thereon, source drivers  106  mounted on the substrate  102 , a PCB (printed circuit board)  112 , a system circuit  108  mounted on the PCB  112  and a FPC (flexible printed circuit) board  110  bonded to the PCB  112  and the substrate  102 . The system circuit  108  provides power supply voltages, image data and control signals to the source driver circuits  106  through wire lines (not shown) formed on the PCB  108 , FPC board  110  and substrate  102 . 
         [0005]      FIG. 2  shows a conventional dot inversion scheme for driving the pixel array  104  in  FIG. 1 . For simplicity, only a 4×4 array is shown. Within one single frame, the polarities of any two adjacent pixels are opposite to each other. Moreover, the polarities of each pixel in two adjacent frames are also opposite to each other. 
         [0006]      FIG. 3  shows the timing of the control signals in response to which the source driver circuits  106  perform the polarity inversion in the conventional dot inversion scheme. The signal TP has pulses upon every transition of scan periods. The logic level of the signal POL changes upon the rising edges of the signal TP. The source driver circuits  106  inverses the polarities of all their channels in response to the change of the logic level of the signal POL. Thus, a large peak current is drawn from the power supply upon transitions of any two scan periods. Due to limited number of wire lines for power transmission in the structure as shown in  FIG. 1 , this large current results in a significant variation of the ground level of the driving system. Such a variation of the ground level will lead to errors in logic levels and therefore malfunction of the driving system. 
       SUMMARY OF THE INVENTION 
       [0007]    It is therefore an objective of the present invention to provide a voltage polarity controlling method and a circuit to control the voltage polarities of pixel structures in a flat panel display. 
         [0008]    It is another objective of the present invention to provide a voltage polarity control method and circuit to stabilize the ground level in a flat panel display. 
         [0009]    According to one preferred embodiment, in a pixel array, each column of the pixel array is coupled to one of a plurality of first and second channels of a driver. A first and second control signals are generated. Polarities of the first channels are inversed when a logic level of the first control signal changes and polarities of the second channels are inversed when a logic level of the second control signal changes. Only the logic level of one of the first and second control signals changes in response to each transition of scan periods. 
         [0010]    According to another preferred embodiment, a pixel array has a plurality of first and second channels coupled to each column of the pixel array. The circuit comprises means for generating a first and second control signals; and means for inversing polarities of the first channels when a logic level of the first control signal changes and inversing polarities of the second channels when a logic level of the second control signal changes. Only the logic level of one of the first and second control signals changes in response to each transition of scan periods. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims and accompanying drawings, where: 
           [0012]      FIG. 1  shows a physical structure  100  of an LCD driving system using COG (chip-on-glass) and WOA (wire-on-array) technology; 
           [0013]      FIG. 2  shows a conventional dot inversion scheme for driving the pixel array  104  in  FIG. 1 ; 
           [0014]      FIG. 3  shows the timing of the control signals in response to which the source driver circuits  106  perform the polarity inversion in the conventional dot inversion scheme; 
           [0015]      FIG. 4  shows an inversion scheme for driving the pixel array of an LCD according to one embodiment of the invention; 
           [0016]      FIG. 5  shows the timing of the control signals in response to which the source driver circuits perform the polarity inversion in the inversion scheme shown in  FIG. 4 ; 
           [0017]      FIG. 6  shows a circuit for generation of the control signals POLA and POLB shown in  FIG. 5 ; and 
           [0018]      FIG. 7  shows an alternative circuit for generation of the control signals POLA and POLB shown in  FIG. 5 . 
       
    
    
     DETAILED DESCRIPTION 
       [0019]    Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
         [0020]      FIG. 4  shows an inversion scheme for driving the pixel array of an LCD according to one embodiment of the invention. For simplicity, only a 4×4 array is shown. Within one single frame, only the polarities of the pixels of some columns in one row are opposite to the polarities of the pixels of those columns in an adjacent row. More specifically, within one single frame, the polarities of the pixels of the (4n−3) th  and (4n−2) th  columns in the (2m−1) th  row are opposite to the polarities of the pixels of the (4n−3) th  and (4n−4n−2) th  columns in the (2m) th  row while the polarities of the pixels of the (4n−1) th  and (4n) th  columns in the (2m−1) th  row are the same as the polarities of the pixels of the (4n−1) th  and (4n) th  columns in the (2m) th  row, and the polarities of the pixels of the (4n−3) th  and (4n−2) th  columns in the (2m) th  row are the same as the polarities of the pixels of the (4n−3) th  and (4n−2) th  columns in the (2 m+1) th  row while the polarities of the pixels of the (4n−1) th  and (4n) th  columns in the (2m) th  row are opposite to the polarities of the pixels of the (4n−1) th  and (4n) th  columns in the (2 m+1) th  row, wherein n and m are natural numbers. 
         [0021]    For example, the polarities of the pixels of the 1st and 2nd columns  402   a  and  402   b  in the 1st row  404   a  are opposite to the polarities of the pixels of the same columns in the 2nd row  404   b  while the polarities of the pixels of the 3 rd  and 4 th  columns  402   c  and  402   d  in the 1 st row  404   a  are the same as the polarities of the pixels of the 3 rd  and 4 th  columns  402   c  and  402   d  in the 2nd row  404   b , and the polarities of the pixels of the 1st and 2nd columns  402   a  and  402   b  in the 2nd row  404   b  are the same as the polarities of the pixels of the same columns in the 3 rd  row  404   c  while the polarities of the pixels of the 3 rd  and 4 th  columns  402   c  and  402   d  in the 2nd row  404   b  are opposite to the polarities of the pixels of the 3 rd  and 4 th  columns  402   c  and  402   d  in the 3 rd  row  404   c.    
         [0022]    Moreover, in the previously described inversion scheme, the polarities of each pixel in two adjacent frames are also opposite to each other. 
         [0023]      FIG. 5  shows the timing of the control signals in response to which the source driver circuits perform the polarity inversion in the inversion scheme shown in  FIG. 4 . The signal TP has pulses upon every transition of scan periods. The logic level of the signal POL changes upon the rising edges of the signal TP. The logic level of the signal POLA changes upon the falling edges of the signal POL while the logic level of the signal POLB changes upon the rising edges of the signal POL. All the source driver circuits inverse the polarities of the channels coupled to the pixels of the (4n−3) th  and (4n−2) th  columns in response to the change of the logic level of the signal POLA while they inverse the polarities of the channels coupled to the pixels of the (4n−1) th  and (4n) th  columns in response to the change of the logic level of the signal POLB. For example, all the source driver circuits inverse the polarities of the channels coupled to the pixels of the 1st and 2nd columns in response to the change of the logic level of the signal POLA while they inverse the polarities of the channels coupled to the pixels of the 3 rd  and 4 th  columns in response to the change of the logic level of the signal POLB. 
         [0024]    Moreover, the logic level of the signal POLA changes in response to the transition of the (2m−1) th  and (2m) th  scan periods while the logic level of the signal POLB changes in response to the transition of the (2m) th  and (2m+1) th  scan periods, wherein m is a natural number. For example, the logic level of the signal POLA changes in response to the transition of the 1st and 2nd scan periods while the logic level of the signal POLB changes in response to the transition of the 2nd and 3 rd  scan periods. Thus, the logic levels of signals POLA and POLB do not change simultaneously so that, in response to each transition of scan periods, the source driver circuits do not inverse the polarities of all their channels, which reduces the peak current resulting from the polarity inversion. 
         [0025]      FIG. 6  shows a circuit for generation of the control signals POLA and POLB shown in  FIG. 5 . The circuit includes a phase shifter  602 , frequency reducers  604   a  and  604   b , a phase shifter  604 , and multiplexers  606   a  and  606   b . The phase shifter  602  receives the signal POL and outputs a signal POL′ which is delayed by one scan period. The frequency reducers  604   a  and  604   b  receive the signal POL and delayed signal POL′, and output the signals POLA and POLB whose frequencies are half of the frequency of the signals POL and POL′, respectively. The multiplexer  606   a  receives the signals POL and POLA, and selectively outputs one of them in response to a selection signal SEL. The multiplexer  606   b  receives the signals POL and POLB, and selectively outputs one of them in response to the selection signal SEL. Thus, when the selection signal is asserted (or de-asserted), the signals POLA and POLB are transmitted to the source driver circuits, activating the inversion scheme shown in  FIG. 4 . When the selection signal is de-asserted (or asserted), only the signal is transmitted to the source driver circuits, activating the conventional dot inversion scheme. 
         [0026]      FIG. 7  shows an alternative circuit for generation of the control signals POLA and POLB shown in  FIG. 5 . The circuit includes a frequency reducer  704 , a phase shifter  702 , and multiplexers  706   a  and  706   b . The frequency reducer  704  receives the signals POL and output a frequency-reduced signal POL′ whose frequencies ares half of the frequency of the signals POL. The phase shifter  702  receives and delays the signal POL by one scan period to generate the signal POLB. The multiplexer  706   a  receives the signals POL and POLA (i.e. POL′), and selectively outputs one of them in response to a selection signal SEL. The multiplexer  706   b  receives the signals POL and POLB, and selectively outputs one of them in response to the selection signal SEL. 
         [0027]    It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.