Abstract:
A self-arming, prescaling frequency counter system comprises an armable frequency counter, an envelope detector, a prescaling pulse-shaper, and a delaying means. The envelope detector detects occurrence of an oscillating signal to be frequency measured and transmits an arming signal to arm the frequency counter for the duration of the oscillating signal. The prescaling pulse-shaper is coupled to receive the oscillating signal burst and generate a pulsed test signal of frequency an integer fraction of the oscillating signal frequency. The delaying means couples the test signal to the armable frequency counter input, delaying receipt of the pulsed signal burst until after the counter is armed, and delaying termination of the pulsed signal until after counter is disarmed. To minimize the width of the smallest signal burst which can be measured, the delay time is set approximately equal to the sum of the counter arming delay time, the counter disarming delay time and one cycle period of the lowest frequency signal to be measured by the counter.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates in general to armable frequency counters for measuring the frequency of an oscillating electrical signal burst and in particular to a frequency counter system which generates its own arming signal derived from the signal burst being measured. 
     Frequency counters typically determine the frequency of a pulsed signal in two ways. In the first method, the counter counts the number of reference clock events (which may be pulses) of known frequency that occur between successive input signal events. The signal frequency is then computed by dividing the known frequency of the reference signal by the number of counted reference events. In the second method, the counter counts input signal events occurring during a known reference period. The frequency of the input signal is then computed by dividing the number of counted input events by the known reference period. In either case the result may be used to drive a digital display, the display being updated at the end of each count cycle. In prescaled frequency counters, the signal to be measured is first applied to a frequency divider which outputs a pulse to the counter input upon receipt of every Nth signal event where N is a selected integer. Prescaling an input signal to a frequency counter permits higher frequency signal bursts to be measured by slower frequency counters. 
     Armable frequency counters typically begin operating only after receiving an arming signal from external circuits. As long as a counter is armed it will continue to count input or reference events, computing the signal frequency and updating the display at the end of each count cycle. After the arming signal is turned off, the counter will typically count until the next input signal event occurs and then stop counting until it is rearmed. 
     To minimize the length of the shortest signal burst which can be measured by an armable frequency counter, the counter should be armed before the signal burst begins. It is also important that the arming signal end before occurrence of the last input signal event. This insures the frequency computed by the counter provides a true reading and is not altered by events occurring after the end of the signal burst. In the prior art, short signal bursts were difficult to frequency measure unless a variable width pulse properly synchronized with the signal burst happened to be available for use as an arming signal. However such a useful variable width pulse was not always present. If the signal burst occurred at regular intervals and was of regular length, an arming signal of proper length and timing could sometimes be generated by adjusting a squarewave signal generator while comparing the signal burst and the arming signal on a dual trace oscilloscope. However, this method is difficult and time consuming. Finally, the method of the prior art is of no use when a frequency counter is to be armed for a single, non-reoccurring signal burst of indeterminate starting and ending time. 
     Therefore what is needed is a self-arming frequency counter system for measuring the frequency of a prescaled or non-prescaled signal burst wherein counter arming and disarming anticipates the beginning and end of the signal being tested. 
     SUMMARY OF THE INVENTION 
     The present invention comprises a prescaling, self-arming frequency counter including in part an armable frequency counter which may operate in either of two modes. In the first mode, the counter counts the number of reference clock events of known frequency occurring between successive input signal events, computing the signal frequency by dividing the known frequency of the reference signal by the reference event count. In the second mode, the counter counts input signal events occurring during a known reference period, computing the signal frequency by dividing the number of counted input events by the known reference period. In either case, counter operation begins on receipt of an arming signal and terminates with the first input event following termination of the arming signal. 
     The present invention further comprises a buffer, a prescaling pulse-shaper, an envelope detector, and a delay line. The buffer is coupled to receive an oscillating signal to be frequency measured and to generate a similar oscillating signal offset by an applied offset voltage. The offset prevents low magnitude noise on the signal input from causing a false counter reading. 
     The pulse-shaper converts the offset oscillating signal into a pulsed signal of the same frequency which can be measured by the armable frequency counter. Optionally, the pulse-shaper may also prescale the pulsed signal such that the frequency of the oscillating input signal is an integer multiple of the prescaled, pulsed output signal to permit measurement of higher frequency signals by a slower operating frequency counter. 
     The envelope detector is coupled to detect the beginning and end of the oscillating signal burst to be frequency measured and to transmit an arming signal to the armable frequency counter. Actual counter arming begins shortly after the start of the oscillating signal burst and ends shortly after the end of the signal burst. The arming and disarming delays are due to the switching times and the capacitor charging and discharging times of components in the arming circuit, and to delays inherent in the armable counter itself. 
     To insure that signals of the minimal burst width are frequency measured by the counter, a delay line, coupling the pulse signal output of the signal shaper to the input of the armable counter, delays the arrival of the pulsed signal to the counter until after the envelope detector has armed the counter. More specifically, the signal delay time associated with the delay line is set approximately equal to the sum of the prescaling integer divided by the frequency of the lowest frequency signal to be measured plus the counter arming on and off delay times. This signal delay time permits frequency measurement of signals of minimum burst width and prevents alteration of the frequency count by events following the measured burst. 
     It is therefore an object of the present invention to provide a new and improved self-arming frequency counter wherein counter arming is derived from the signal to be frequency measured. 
     It is another object of the present invention to provide such a new and improved self-arming frequency counter as may be adjusted to minimize the burstwidth of an input signal of a given frequency which can still be reliably measured by the frequency counter. 
     It is another object of the present invention to provide such a new and self-arming frequency counter as will frequency measure signal bursts of indeterminate beginning or ending time or of arbitrarily long burst width. 
     It is another object of the present invention to provide such a new and self-arming frequency counter wherein the signal input to the frequency counter is delayed to insure that the counter is armed prior to counter receipt of the input signal and disarmed prior to termination of the input signal. 
     Still further objects of the present invention are to provide such a new and self-arming frequency counter wherein the signal to be measured is buffered to avoid false measurement due to low level noise and prescaled to allow measurement of higher frequency signals by slower counting circuits. 
     The invention resides in the combination, construction, arrangement and disposition of the various component parts and elements incorporated in a self-arming frequency counter constructed in accordance with the principles of this invention. The present invention will be better understood and objects and important features other than those specifically enumerated above will become apparent when consideration is given to the following details and description, which when taken in conjunction with the annexed drawings describe, disclose, illustrate, and show a preferred embodiment or modification of the present invention and what is presently considered and believed to be the best mode of practicing the principles thereof. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a combination block and circuit diagram of the preferred embodiment of the present invention, and 
     FIG. 2 is a diagram depicting timing relations between signals appearing at various points in the circuit of FIG. 1 during an input signal burst of minimum frequency and burst width. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 is a diagram of the present invention comprising a prescaling, self-arming frequency counter system generally noted by reference character 10, including prescaling pulse-shaper 100, delaying means 200, envelope detector 300, armable frequency counter 400 and input buffer 600. 
     Buffer 600 is a differential amplifier for generating an output signal proportional to the difference between two input signals. The oscillating signal to be frequency measured V in  is applied to the non-inverting input of buffer 600 and a constant reference voltage V min  is applied to the inverting input. The output of buffer 600, V i , is similar to V in  except that it has a negative offset equal to V min  wherein V min  is selected to insure that low amplitude noise signals on input line 610 do not cause V i  to rise above zero voltage and to trigger false counter operation. 
     The V i  signal output of buffer 600 is applied to the input of prescaling pulse-shaper 100. Prescaling pulse-shaper 100 is a &#34;divide by N&#34; type circuit wherein oscillating input signal V i  of frequency F i  results in a pulsed output signal V o  of frequency F i  /N where N is a selected integer. Devices suitable for use as buffer 600 and for use as prescaling pulse-shaper 100 are common in the art and readily available and therefore detailed embodiments of these devices are not discussed herein. 
     Pulse-shaper 100 output signal V o  is applied to delaying means 200. Delaying means 200 is a circuit wherein a pulsed input signal, in this case V o , results in an identical output signal, V d , except that V d  lags V o  by a selected delay time. Delaying means 200 may comprise a network consisting of parallel capacitances and series inductors as commonly used to delay low frequency signals. For use with higher frequency signals, a length of conductor may be used as delaying means 200, the delay time being equal to the length of the line divided by the speed of propagation of a signal in the line. 
     The V i  signal output of buffer 600 is also coupled to envelope detector 300 comprising rectifier 320, capacitor 330, resistor 340, and comparator 350. Rectifier 320 rectifies V i  and applies the rectified signal, V b , to the input of comparator 350 and to the grounded parallel combination of capacitor 330 and resistor 340. When V i  rises above zero, V b  rises above zero, charging capacitor 330. When V b  rises above bias voltage V bias  applied to the negative input of comparator 350, the comparator outputs counter arming signal V a . When V i  falls below the capacitor voltage, capacitor 330 discharges through resistor 340 and when the voltage on capacitor 330 falls below V bias , comparator 350 terminates arming signal V a . However, if resistor 340 is suitably large, capacitor 330 discharge time is slow. A subsequent V i  pulse, occurring shortly after the first, will cause buffer 600 to recharge capacitor 330 before the capacitor voltage can fall below V bias . Thus comparator 350 output V a  will remain high during an oscillating V i  signal burst as long as successive V i  positive swings are of sufficient magnitude and not too infrequent. 
     Frequency counter 400 may determine the frequency of an input signal V d  in either of two ways. In a reference count mode, the counter counts the number of reference clock events of known frequency occurring between successive V d  signal pulses, computing the signal frequency by dividing the known frequency of the reference signal by the reference event count. In a signal count mode, the counter counts V d  signal pulses occurring during a known reference period, computing the signal frequency by dividing the number of counted V d  pulses by the known reference period. Frequency counter 400 may include provisions for displaying the computed signal frequency on digital display 500, the display being updated at the end of each measurement cycle. 
     Frequency counter 400 begins operating only after receiving arming signal V a  and will continue to count input or reference events, computing the signal frequency and updating the display at the end of each count cycle as long as V a  remains high. After arming signal V a  is turned off, counter 400, in the reference count mode, will continue to count reference events until the next signal pulse is received. In the signal count mode, counter 400 counts the first signal pulse after counter disarming and then stops counting. In either case if the end of a count cycle occurs after disarming but with or before receipt of the next V d  pulse, counter 400 will compute the frequency associated with the last counting period and update the display. Otherwise the display will remain fixed at the frequency computed from the last full counting cycle. Devices suitable for use as armable frequency counter 400 are known in the art and readily available and therefore a detailed embodiment of this component of the present invention is not discussed herein. 
     Due to the delays associated with the charging time of capacitor 330, with the switching time of comparator 350 and with such delay mechanisms as may be inherent in the counter itself, arming of counter 400 will not occur until some time after start of a V i  signal burst. Likewise, after the V i  signal burst ends, disarming of the counter is delayed by the capacitor 330 discharge time, by comparator 350 switching time, and by delays in counter 400 internal circuits. Thus the period during which frequency counter 400 is armed is delayed in time from the period during which the signal burst V i  actually occurs. To operate in either the reference count mode or the signal count mode, counter 400 must receive at least two pulses after arming begins. In order for frequency counter 400 to operate with the shortest V i  signal burst possible for a given minimum input signal frequency, F im , the first V d  pulse should not reach the counter prior to counter arming. Consequently, delay means 200 is provided and its delay time is adjusted to delay V d  so that it is properly synchronized with the arming signal generated by envelope detector 300. 
     It is important in choosing the delay time associated with delaying means 200 that the last V d  pulse is delayed until after termination of arming signal V a , since the first V d  pulse occurring after disarming stops counter operation in either mode. If the last V d  pulse occurs before counter disarming, the counter may generate incorrect frequency counts, improperly replacing the display of the frequency of the last correctly computed V d  burst count cycle. In the signal count mode, with no signal pulses occurring after counter disarming, counter 400 will incorrectly set the displayed frequency to zero. In the reference count mode, the counter will continue to count reference clock pulses until a noise pulse or a subsequent signal burst pulse occurs at the counter input and the counter would then replace the displayed frequency with some nonmeaningful value. 
     The most appropriate choice for the delay time associated with delaying means 200 depends on the frequency and the burst width of the signals to be measured. A longer delay time permits measurement of lower frequency signals while a shorter delay time will decrease the width of the shortest signal burst which can be measured by the counter. 
     FIG. 2 is a timing diagram showing pulse sequence relations for various signals in the circuit of FIG. 1. For simplicity, in the particular case shown, V in  is depicted as a square-wave of frequency F im . However, the circuit of FIG. 1 will operate with other forms of oscillating input signal. Assuming prescaling pulse-shaper 100 divides V in  input pulses by a factor of four (N=4), a V o  pulse will begin on every second V in  pulse and will end on every fourth V in  pulse. 
     Counter 400 arming is delayed after the start of the V in  signal burst by t on , the sum of the delays in envelope detector 300 and the arming delays internal to counter 400. Counter disarming is delayed by t off , the sum of the turn off delays in detector 300 and counter 400. In order for counter 400 to operate properly it must receive at least one V d  pulse leading edge (positive going) before disarming and one V d  pulse leading edge after disarming. Thus the V in  signal burst must be long enough to generate at least two V d  pulses with the last V d  pulse beginning after counter arming ends. 
     V d  signal pulses are delayed from V o  signal pulses by t d , the delay time associated with delay line 200. Delay time t d  is selected as follows: 
     
         t.sub.d =t.sub.on +N/F.sub.im +t.sub.off                   (1) 
    
     With this selected delay time, as shown in FIG. 2, the first leading edge of V d  can occur no later than the moment of counter disarming. In this &#34;worst case&#34; situation, prescaling pulse-shaper 100 is initially in the state wherein V o  is high and two V in  pulses are required to drive V o  low. Also, in the particular case shown, V in  begins on a negative rather than a positive swing. If pulse shaper 100 had been in any other state when it received the first V i  pulse, the first V d  pulse would have occurred earlier, before counter disarming. If delay line 200 delay time t d  were longer than as shown, then it is possible that the first V d  leading edge could occur after counter disarming. Also, if another V i  signal burst of a lower frequency than F im  as shown were to be measured, it is possible that the first V d  leading edge would occur after counter disarming. However, the first leading edge of a V in  signal burst of frequency higher than F im  would always occur before counter disarming. 
     Also, with the delay time t d  adjusted as in equation (1) above, the last leading edge in the V d  signal must always occur after counter disarming. The first V d  leading edge could occur as much as one V d  cycle earlier than depicted in FIG. 2 if V in  initially includes a positive swing and if the first V in  leading edge forces prescaling pulse-shaper 100 to generate a V o  positive edge. In this situation, the second leading edge of V d  would occur just as the counter disarms. If t on  is very small compared to the period of V o , then the second leading edge of V d  would be the last. Thus if t d  were chosen smaller than as indicated in equation (1), the last V d  leading edge associated with a short signal burst could occur before counter disarming. Therefore, optimal measurement reliability for input signals of frequency F im  or greater is obtained when the delay time of delay line 200 is adjusted approximately as indicated in equation (1). 
     In addition to the minimum frequency constraint on an input signal, to insure that counter disarming does not occur before the leading edge of the V d  signal, an input signal of any frequency must have a minimum burst width (MBW) as follows: 
     
         MBW =t.sub.d +N/F.sub.im =t.sub.on +2N/F.sub.im +t.sub.off (2) 
    
     In the design of self-arming counter system 10 of the present invention, where it is desirable to measure signals of low frequency (F im  small), delay line 200 may be made very long so that delay time t d  is large, satisfying equation (1). However, in doing so, the minimum burst width for all input signals to be measured must be large, according to equation (2). Conversely where it is desirable to frequency measure very short signal bursts, a short delay line may be used to obtain a small delay t d  and therefore a small MBW according to equation (2). However, according to equation (1), with such a small delay, only high frequency signals (F im  large) can be reliably frequency measured. The delay time chosen therefore represents a tradeoff between minimum frequency and minimum bandwidth constraints on the signal to be measured. 
     The self-arming frequency counter system of the present invention thus anticipates the beginning and end of the signal to be measured to allow reliable measurement of signal bursts of minimal burstwidth and frequency, and of indeterminate beginning or ending times. The present invention also operates with a prescaling pulse-shaper permitting measurement of high frequency signals with lower speed counters and incorporates a buffer to prevent low magnitude input noise from causing false counter operation. 
     While a preferred embodiment of the present invention has been described, it will be apparent to those skilled in the art that many changes and modifications may be made without departing from the invention in its broader aspects. The appended claims are therefore intended to cover all such changes and modifications as fall within the true spirit and scope of the present invention.