Abstract:
In order to increase channel capacity of a processing engine in a telecommunication network, separate telecommunication signals are multiplexed in pairs to produce at least one multiplexed signal. This signal is transmitted to the processing engine to create a processed multiplexed signal. The processed multiplexed signal from the processing engine is then demultiplexed to produce separate processed telecommunication signals.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims the benefit under 35 USC 119(e) of prior U.S. provisional application Ser. No. 60/515,658 filed on Oct. 31, 2003, the contents of which are herein incorporated by reference. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention relates to System-on-a-Chip (SoC) implementation of a variety of communication systems. More specifically, the invention relates to a method of increasing the channel capacity of Inverse Fast Fourier Transform (IFFT) and the Fast Fourier Transform (FFT) engines without increasing die size of the chip.  
         [0003]     In the first and last mile connections of telecommunication networks, various Digital Subscriber Line (xDSL) and wireless technologies play a dominate role. These technologies are usually based on a common fundamental technology: Discrete multitone (DMT) in xDSL or Orthogonal Frequency-Division Multiplexing (OFDM) in wireless. DMT and OFDM both use many narrow-band carriers all being transmitted simultaneously. Each narrow band or frequency bin carries part of the total information. Each of these narrow-bands is independently modulated—with a carrier frequency corresponding to the centre frequency of that bin—all bins are processed in parallel.  
         [0004]     The centre of the DMT/OFDM technology is the IFFT and the FFT which perform the independent modulations and demodulations. In a SoC implementation of the xDSL or wireless modem, about 80-90% of the gates are for the implementation of the IFFT and FFT.  
         [0005]     The customers of the first and last mile connections of a telecommunication network are end consumers, and they are very sensitive to pricing. Therefore, the first and last mile connection equipment must be manufactured to keep the lowest production cost possible in order to result in a reasonable profit on their sales.  
         [0006]     In the semiconductor manufacture business, the cost of wafers is a major item in calculating the Bill of Material (BOM) cost. If a wafer can be divided into more dies during the semiconductor fabrication process, the per die BOM will be reduced. If a die can host more channels without increasing its size, the per channel BOM will also be reduced.  
         [0007]     As the majority of the SoC die size is dedicated to the IFFT and FFT engines for the above applications, the per channel die size can be reduced by almost 50% if the channel capacity of the IFFT and FFT engines with the same clock rate and the same semiconductor fabrication process can be doubled.  
       SUMMARY OF THE INVENTION  
       [0008]     The present invention relates to the System-on-a-Chip (SoC) implementation of a variety of communication systems, such as Very-high-bit-rate Digital Subscriber Line (VDSL), Asymmetric Digital Subscriber Line (ADSL) Transceivers family and any other systems employing Discrete multitone (DMT) or Orthogonal frequency-division multiplexing (OFDM) technology in base band.  
         [0009]     Specifically, a method to increase, and in particular, double the channel capacity of the IFFT and FFT engines with the same clock rate and a similar number of gates on the silicon is disclosed. By using linear and symmetric properties of the FFT and IFFT, only one IFFT and one FFT engine is required to process two separate signals. Therefore, the per channel die size of the engine implementations in a SoC is cut by half.  
         [0010]     Thus, according to one aspect, the invention provides a method of increasing channel capacity of a processing engine in a telecommunication network, the method comprising the steps of multiplexing separate telecommunication signals in pairs to produce at least one multiplexed signal; transmitting the multiplexed signal to the processing engine to create a processed multiplexed signal; and demultiplexing the processed multiplexed signal from the processing engine to produce separate processed telecommunication signals.  
         [0011]     Another aspect of the invention provides a transmitter for a multi-carrier communications system comprising first and second input ports for respective first and second data streams; a multiplexer for combining said first and second data streams into a common data stream; a common inverse transform engine for performing an inverse transform operation on said common data stream; a demultiplexer for separating said common data stream into first and second output data streams; and first and second output ports for transmitting said output data streams on respective physical channels.  
         [0012]     In yet another aspect the invention provides a receiver for a multi-carrier communications system comprising first and second input ports for receiving first and second input signals on respective physical channels; a multiplexer for combining said first and second input signals into a common data stream; a common transform engine for performing an transform operation on said common data stream; a demultiplexer for separating said transformed data stream into first and second output data streams; and first and second output ports for outputting said data streams.  
         [0013]     Other aspects and advantages of embodiments of the invention will be readily apparent to those ordinarily skilled in the art upon a review of the following description. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]     The invention will now be described in more detail, by way of example only, with reference to the accompanying drawings, in which:— 
         [0015]      FIG. 1  is a schematic illustration of a prior art DMT/OFDM transmitter;  
         [0016]      FIG. 2  is a schematic illustration of a prior art DMT/OFDM receiver;  
         [0017]      FIG. 3  is a schematic illustration of a DMT/OFDM transmitter in accordance with principles of the present invention;  
         [0018]      FIG. 4  is a schematic illustration showing how two independent signals can be combined, processed by one single IFFT engine and separated into two channels at the transmitter side;  
         [0019]      FIG. 5  is a schematic illustration showing of a DMT/OFDM receiver in accordance with principles of the present invention; and  
         [0020]      FIG. 6  is a schematic illustration showing how two independent signals can be combined, processed by one single FFT engine and separated at the receiver side. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0021]     The invention makes use of the linear and symmetric properties of the FFT and IFFT.  
         [0022]     Let {x 1 (k)} and {x 2 (k)} be two 2N×1 real vectors, where N is an integer, and 
 
{ x ( k )}={ x ( k )}+ j{x   2 ( k )}  (Equation 1) 
 
 Further let 
 
{ x ( n )}= FFT{x ( k )}  (Equation 2) 
 
 then  
                     {     X   ⁡     (   n   )       }     =     FFT   ⁡     (       {       x   1     ⁡     (   k   )       }     +     j   ⁢     {       x   2     ⁡     (   k   )       }         )                   =       FFT   ⁢     {       x   1     ⁡     (   k   )       }       +     j   ⁢           ⁢   FFT   ⁢     {       x   2     ⁡     (   k   )       }                     =       {       X   1     ⁡     (   n   )       }     +     j   ⁢     {       X   2     ⁡     (   n   )       }                       (     Equation   ⁢           ⁢   3     )                       {       X   1     ⁡     (   n   )       }     =       FFT   ⁢     {       x   1     ⁡     (   k   )       }       +     FFT   ⁢     {     Re   ⁢     {       x             ⁡     (   k   )       }       }                     =       1   2     ⁡     [       {     X   ⁡     (   n   )       }     +     {       X   *     ⁡     (     N   -   n     )       }       ]                 and               (     Equation   ⁢           ⁢   4     )                       {       X   2     ⁡     (   n   )       }     =       FFT   ⁢     {       x   2     ⁡     (   k   )       }       +     FFT   ⁢     {     Im   ⁢     {       x             ⁡     (   k   )       }       }                       =       1     2   ⁢   j       ⁡     [       {     X   ⁡     (   n   )       }     -     {       X   *     ⁡     (     N   -   n     )       }       ]         ,                 (     Equation   ⁢           ⁢   5     )             
 
 where X*(n) is the complex conjugate of X(n). 
 
         [0023]     Using the above linear property, in accordance with the principles of the invention in the transmitter side two separate signals are combined before being sent to a single IFFT engine. The single output of the IFFT engine is separated and transmitted to two physical channels. Because only one IFFT engine is required to process two separate signals to be transmitted as opposed to two IFFT engines in the prior art, the per-channel die size of IFFT engine implementation in a SoC is cut by half.  
         [0024]     Similarly, by using the above symmetric property of FFT, in the receiver side, two separate signals received from two physical channels are combined before being sent to a single FFT engine for demodulation. The output of the FFT engine is separated and demapped to restore the two independent data streams. Because only one FFT engine is required to process two signals received from two separate physical channels as opposed to two FFT engines in the prior art, the per-channel die size of FFT engine implementation in a SoC is cut by half.  
         [0025]     Referring to  FIG. 1 , there is shown a schematic illustration of a prior art DMT/OFDM transmitter  10 . The transmitter  10  requires two IFFT engines  12  and  14  to modulate two data streams  16  and  18  transmitted to two separate physical channels from QAM mappers  20  and  22 . Normally, DMT completes the modulation process by performing IFFT operations on complex vectors { X   1 (n)}, and {X 2 (n)}, and two real vectors {x 1 (k)} and {x 2 (k)} are generated. These two real vectors are then sent to digital to analog converters (DACs) in ports  24  and  26  before being sent out on two separate physical channels  25 ,  27 .  
         [0026]     Let {X′ 1 (n)} be an N×1 complex vector of such a batch of the complex numbers from channel  1  and {X′ 2 (n)} be another N×1 complex vector of such a batch of the complex numbers from channel  2 . {X′(n)} and {X′ 2 (n)} are expanded to 2N×1 complex vectors {X 1 (n)} and {X 2 (n)} as follows:  
                 X   i     ⁡     (   n   )       =     {                   X   i   ′     ⁡     (   n   )               n   =   0     ,           ⁢   …   ⁢           ,     N   -   1                   X   i   ′     ⁡     (       2   ⁢   N     -   n     )               n   =   N     ,           ⁢   …   ⁢           ,       2   ⁢   N     -   1             ⁢           ⁢     
     ⁢           ⁢   i     =   1     ,   2               (     Equation   ⁢           ⁢   6     )             
 
         [0027]     In the prior art, shown in  FIG. 1 , the DMT completes the modulation process by performing IFFT operations on {X(n)} and {X 2 (n)} and two real 2N×1 real vectors {x 1 (k)} and {x 2 (k)} are generated 
 
 {x   1 ( k )}= Re{IFFT{X   1 ( n )}}  (Equation 7) 
 
{x 2 ( k )}= Re{IFFT{X   2 ( n )}}  (Equation 8) 
 
         [0028]     These two real vectors are then sent to digital to analog converters in ports  24 ,  26  before being sent to the two separate physical channels. Two separate IFFT operations are required and hence two IFFT engines need to be implemented in a SoC silicon if the SoC is to process two channels.  
         [0029]     In the above process, two IFFT operations are required and hence two IFFT engines need to be implemented in a SoC silicon if the SoC is to process two channels. If the channel size is to be increased, the die size must also be increased accordingly.  
         [0030]      FIG. 3  is a schematic illustration showing a DMT/OFDM transmitter  50  with only one IFFT engine  52  to modulate two data streams before being transmitted to two separate physical channels  68 ,  70 .  
         [0031]     Using the linear properties outlined above in the transmitter side  50  two separate signals  18  and  16  sent from QAM mappers  20  and  22  are combined by Tx Port Mux  54  before being sent to a single IFFT engine  52 . The single output  64  of the IFFT engine  52  is separated by Tx Port Demux  66  and transmitted to the digital-to-analog converters (DAC) of Ports  24 ,  26 , and then to the two physical channels  25  and  27 .  
         [0032]     The incoming data stream is mapped to a sequence of complex numbers according to the constellation diagrams. The sequence of the complex numbers is then divided into batches of N=2 M  in length, where M is an integer.  
         [0033]     In accordance with the principles of the invention {X 1 (n)} and {X 2 (n)} are combined into one 2N×1 complex vector {X(n)} as follows: 
 
 {X ( n )}={ X   1 ( n )}+ j{X   2 ( n )}  (Equation 9) 
 
 and the resulting 2N×1 complex vector {X(n)} is sent to one single IFFT engine  52 . Equation 9 is the mathematical function performed in the Tx Port Mux module  62 . The output of this single IFFT engine  52  is a complex 2N×1 complex vector {x(k)}, 
 
{ x ( k )}= IFFT{X ( n )}.  (Equation 10) 
 
         [0034]     Two real 2N×1 real vectors {x 1 (k)} and {x 2 (k)} are generated by 
 
{ x ( k )}= Re{x ( k )}  (Equation 11) 
 
 {x   2 (k)}= Im{x ( k )}  (Equation 12) 
 
 in the Tx Port Demux module  66  and are then sent to digital to analog converters in ports  24 ,  26  before being sent to two separate physical channels  68 ,  70 . 
 
         [0035]      FIG. 4  is a schematic illustration showing how the two independent signals  16  and  18  from port mappers  20 ,  22  are combined, processed by one single IFFT engine  52  and separated into two channels  68  and  70  at the transmitter side  50 . The output of QAM port mappers  20 ,  22  are sent respectively to RAMs  70 ,  72 . The real and imaginary parts from the RAMs  70 ,  72  are added in respective adders  76 ,  78  and passed to IFFT  52  before being input to the DACs of ports  22 ,  24 . In  FIG. 4  the demux  66  is presumed to be included in the IFFT block  52 .  
         [0036]     In further embodiments, there could be other system specific functional blocks, such as Peak to Average Ratio reducers, between IFFT output port and DACs.  
         [0037]     Because only one IFFT engine  52  is required to process two separate signals to be transmitted as opposed to two IFFT engines in the prior art, the per-channel die size of IFFT engine implementation in a SoC is cut by half.  
         [0038]      FIG. 2  shows a schematic illustration of a prior art DMT/OFDM receiver  30  requiring two FFT engines  32  and  34  to demodulate two signals  36  and  38  received from two separate physical channels  41 ,  43 . In this system, real vectors {x(k)} and {x 2 (k)} are fed from analog to digital converters (ADCs)  42  and  44  to two separate FFT engines  32  and  34 , and two complex vectors {X 1 (n)} and {X 2 (n)} are generated. The first halves of {X(n)} and {X 2 (n)} are sent to QAM demappers in ports  46  and  48  to de-modulate and restore the data streams transmitted from two independent sources.  
         [0039]     Let {x(k)} be a 2N×1 real vector of such a batch of the digital signal from channel  1  and {x 2 (k)} be another 2N×1 real vector of such a batch of the digital signal from channel  2 . In the prior art {x(k)} and {x 2 (k)} were fed to two separate FFT engines as shown in  FIG. 2  and two 2N×1 complex vectors {X(n)} and {X 2 (n)} were generated as follows: 
 
 {X   1 ( n )}= FFT{x   1 ( k )}  (Equation 13) 
 
{ X   2 ( n )}= FFT{x   2 ( k )}.  (Equation 14) 
 
         [0040]     The first halves of {X 1 (n)} and {X 2 (n)} were sent to QAM demappers in ports  46 ,  48  to de-modulate and restore the data streams transmitted from two independent sources. If the channel size is to be increased, the die size must also be increased accordingly.  
         [0041]      FIG. 5  is a schematic illustration showing that in accordance with the principles of the present invention a DMT/OFDM receiver  80  requires only one FFT engine  82  to demodulate two signals  36  and  38  received from two separate physical channels  41 ,  43 . By using the above symmetric property of FFT, in the receiver side, two separate signals  36  and  38  received from two physical channels are combined by Rx Port Mux  81  before being sent to the single FFT engine  82  for demodulation. The output  90  of the FFT engine  82  is separated by Rx Port Demux  92  and demapped at QAM demappers  46  and  48  to restore the two independent data streams.  
         [0042]     In accordance with the principles of the invention {x 1 (k)} and {x 2 (k)} are combined to create a 2N×1 complex vector {x(k)}: 
 
 {x ( k )}={ x   1 ( k )}+ j{x   2 ( k )}  (Equation 15) 
 
 in the Rx Port Mux module  81  as shown in  FIG. 5  and this {x(k)} is sent to the single FFT engine  82  resulting in a 2N×1 complex vector {X(n)} as follows: 
 
 {X ( n )}= FFT{x ( k )}  (Equation 16) 
 
 From {X(n)}, two N×1 vectors {X′ 1 (n)} and {X′ 2 (n)} are created with their elements being  
                 X   1   ′     ⁡     (   n   )       =     
     ⁢           ⁢     {             1   2     ⁡     [       X   ⁡     (   0   )       +       X   *     ⁡     (   0   )         ]             n   =   0                 1   2     ⁡     [       X   ⁡     (   n   )       +       X   *     ⁡     (       2   ⁢   N     -   n     )         ]               n   =   1     ,           ⁢   …   ⁢           ,     N   -   1                       (     Equation   ⁢           ⁢   17     )                   X   2   ′     ⁡     (   n   )       =     
     ⁢           ⁢     {             1     2   ⁢   j       ⁡     [       X   ⁡     (   0   )       -       X   *     ⁡     (   0   )         ]             n   =   0                 1     2   ⁢   j       ⁡     [       X   ⁡     (   n   )       -       X   *     ⁡     (       2   ⁢   N     -   n     )         ]               n   =   1     ,           ⁢   …   ⁢           ,     N   -   1                       (     Equation   ⁢           ⁢   18     )             
 
         [0043]     Equations 17 and 18 are the mathematical functions performed in the Rx Port Demux module  92 . {X′(n)} and {X′ 2 (n)} are sent to QAM demappers in ports  46 ,  48  to de-modulate and restore the data streams transmitted from two independent sources.  
         [0044]      FIG. 6  is a schematic illustration showing how two independent signals can be combined, processed by one single FFT engine  82  and separated at the receiver side. The signals from ports  42 ,  44  are passed through RAM  100  to FFT  82 , which generates real and imaginary parts  100 ,  102 . The output of the FFT is also applied to Reoorder and Conjugate RAM  104 . The real and imaginary outputs from FFT  82  and RAM  104  are applied to respective adders  106 ,  108  and input to RAM  110 , which divider  112  that provides the output to port  46 .  
         [0045]     The real and imaginary outputs from FFT  82  and RAM  104  are also applied to adders  114 ,  116  whose outputs are applied to RAM  118 , which supplies the data stream to port  48  through divider  120 .  
         [0046]     The analog signals from two separate channels  41 ,  43  are converted to digital signals by the Analog to Digital Converters (ADC) in ports  42 ,  44 . The digital signals are then divided into batches of 2N=2 M+1  in length.  
         [0047]     It will be seen that in the above embodiment only one FFT engine is required to de-modulate signals from two separate channels.  
         [0048]     Numerous modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.