Abstract:
A phase locked loop (PLL) circuit includes a phase comparator that compares the phases of an input signal and a feedback signal and generates UP and DOWN pulses that are related to the phase difference. A charge pump receives the UP and DOWN pulses from the phase comparator and either charges or discharges the tuning voltage of a loop filter. The voltage controlled oscillator (VCO) provides an output signal that has a frequency that is related to the tuning voltage. A frequency divider then divides the frequency of the VCO output by a factor of N and provides the output as the feedback signal to the phase comparator. The PLL includes pre-lock circuitry that responds to an active state of a pre-lock input signal by narrowing the dynamic range of the VCO to a pre-lock range that is centered around a predetermined final frequency and that deactivates upon achieving the pre-lock range.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of Invention 
     The present invention relates to voltage controlled oscillators (VCO) used in phase locked loop (PLL) circuits and, in particular, to methods and circuitry for reducing the required gain in the VCO to make the loop more stable and less susceptible to noise. 
     2. Discussion of the Related Art 
     PLL&#39;s have found many applications in the electronics industry. Among their uses are frequency modulated (FM) signal generation and decoding, clock recovery in digital communications, and clock multiplication in digital circuits. It is the latter of these three applications to which the present invention is directed. 
     FIG. 1 shows a block diagram of a typical PLL 100. The PLL is a feedback control system where the phase and frequency of an incoming signal (clk) is compared to a generated feedback signal (ffb). In the clock multiplication application, the phase comparator (PFD) 102 will generate pulses that tell the charge pump 104 whether the input signal (clk) is faster or slower than the feedback signal (ffb). If the input signal is faster, then the phase comparator 102 will generate an &#34;UP&#34; pulse that is proportional in width to the difference in phase between the signals. Likewise, if the input signal is slower, then the phase comparator 102 will generate a &#34;DOWN&#34; pulse that is proportional in width to the phase difference. These pulses are fed to the charge pump 104, which either charges or discharges the loop filter 106. The amount of charge or discharge is proportional to the phase difference since it is controlled by the pulse width of the UP or DOWN signal received by the charge pump 104. The voltage on the loop filter 106 controls the VCO 108. The VCO 108 produces a frequency that is proportional to the voltage at it&#39;s input. That frequency (fvco) is then fed back through a divider 110 to the phase comparator 102 as the generated feedback signal (ffb). 
     The purpose of the divider 110 in the feedback path is to multiply the clock up. This is by virtue of the fact that the phase comparator 102 will attempt to match the frequencies of the signals at it&#39;s inputs. For this to happen, the VCO 108 must be running N times faster than the incoming signal, since the VCO output gets divided by N before it gets compared to the incoming signal. The result is that the output of VCO 108 is equal to N times the input frequency and, hence, provides a clock multiplier. 
     A common problem in PLL&#39;s used for clock multiplication is that the gain in the VCO is extremely high. As stated earlier, the VCO is a circuit that will generate a frequency that is proportional to the voltage at it&#39;s input. The gain of the VCO is a measure of the change in the output frequency for a given change in the input voltage, and is given in Hz per Volt. It is desired to keep this gain term as low as possible to reduce the sensitivity of the VCO to noise on the tune node, and to keep the loop gain down. If there is too much gain in the loop, then it is difficult to attenuate the gain and achieve reasonable phase margin at the gain crossover point without using very large components in the filter. Three major sources of this high gain are lower power supplies, higher frequencies, and wide environmental variations. 
     A common goal in digital circuits is to reduce power consumption by lowering the supply voltage. By doing so, the gain goes up due to the reduced compliance range on the input of the VCO. As an example, assume a VCO must cover a 200 MHz range and the input to the VCO has a range from 0.5V above ground to 0.5V below the power supply. In a 5 volt system, the gain of the VCO would be 50 MHz/V (i.e. 200 MHz/(5-0.5)-(0+0.5)). However, if the power supply is lowered to 3.3 volts, the gain goes up to 87 MHz/V (i.e. 200 MHz/(3.3-0.5)-(0+0.5)). Higher frequencies also play a role in this. If a VCO must cover a 2× range of frequencies, the gain is doubled if that range is from 200 MHz to 400 MHz (i.e. 200 MHz range) rather than from 100 MHz to 200 MHz (i.e. 100 MHz range). Environmental variations are always present in integrated circuits and must be compensated for in the VCO. Even if the only frequency of interest is 100 MHz, the final VCO will likely need to cover a wide range of frequencies at typical conditions in order to cover variations in temperature, voltage and process. For instance, it may be that the VCO will need to cover a range of 50 MHz to 200 MHz at typical conditions so that, whether the circuit is running at hot or cold temperature, high or low voltage, or at the fast or slow process corner, the VCO will still have the 100 MHz desired frequency in it&#39;s operating range. 
     The problem with the implementation in FIG. 1 is that it makes no attempt to reduce the gain of the VCO 108. Although the loop will function (if designed correctly), it will be more susceptible to noise on the tune node, and will require larger components in the loop filter in order to attenuate the loop gain. 
     SUMMARY OF THE INVENTION 
     The preferred embodiment of the present invention provides a phase locked loop (PLL) circuit that includes preconditioning of the voltage controlled oscillator (VCO) to reduce the frequency range and the gain of the VCO. The PLL includes a phase comparator that compares the phases of an input signal and a feedback signal and, if the input signal is faster than the feedback signal, generates an UP pulse that is related to the phase difference and, if the input signal is slower than the feedback signal, generates a DOWN pulse that is related to the phase difference. A charge pump receives the UP and DOWN pulses from the phase comparator and either charges or discharges the tuning voltage output of the loop filter. The amount of tuning charge or discharge is related to the UP and DOWN pulses, respectively. The loop&#39;s voltage controlled oscillator (VCO) responds to the tuning voltage by providing an output signal that has a frequency that is related to the tuning voltage. The frequency divider then decreases the frequency of the VCO output by a factor of N and provides the output as the feedback signal to the phase comparator. In accordance with the invention, the PLL includes pre-lock circuitry that asserts a pre-lock signal upon startup of the device. The asserted pre-lock signal causes pre-lock circuitry to adjust the voltage controlled oscillator such that the center frequency of the VCO matches the frequency of the input signal multiplied by N. Since this action is done at startup of the device, it is possible to shrink the range over which the VCO must operate to cover variations in temperature and voltage. Variations in process are compensated for by centering the range around the frequency of interest (i.e. the pre-lock). This is where the reduction in gain in the VCO is realized. Since process variations are already compensated for by the pre-lock, the operating range of the VCO does not need to compensate for process variations. Hence, the range of the VCO can be smaller and the gain can be lower. Once the pre-lock condition is achieved, the pre-lock circuitry deasserts the pre-lock signal, which allows the tuning voltage of the loop filter to be controlled by the charge pump. 
     In the preferred embodiment, the pre-lock circuitry includes pre-lock control logic that controls the pre-lock signal by asserting it when the device starts up, and deasserting it once pre-lock is achieved. A digital phase detector responds to the active state of the pre-lock signal by providing an UP output signal if the input signal is faster than the feedback signal and a DOWN output signal if the input signal is slower than the feedback signal. A digital control element responds to the UP and DOWN output signals provided by the digital phase detector by providing a digital control signal to the VCO that corresponds to the cumulative total of the UP and DOWN pulses received by the control element. The value of the digital control signal controls the amount of static current in the reference current generator of the VCO. While the pre-lock signal is asserted, the charge pump responds by forcing the tuning voltage to mid-rail. While the pre-lock signal is deasserted, the charge pump forces the tuning voltage to a value according to the UP and DOWN pulses received from the phase detector and the state of the digital control signal to the VCO is locked in and does not change. 
     In a typical application, the pre-lock will only occur once when the device is started up. If it is desired to pre-lock the PLL a second time without halting the operation of the device, this can be done by running two PLL&#39;s, each with pre-lock capabilities, on the device. At all times, one of the PLL&#39;s will be supplying the desired output frequency while the other attains the next pre-lock state. If the environment that the device is operating in drifted enough to warrant switching to the other PLL, this can be done seamlessly. Once the switch is made and the new PLL is supplying the desired output frequency, then the PLL that was originally supplying the desired output frequency can be pre-locked again to attain the next pre-lock state. This allows an even smaller frequency range over which the VCO must operate since variations in temperature and voltage can be compensated for on the fly by switching between the two PLL&#39;s. Since the range of the VCO is lower, the gain will also be lower resulting in even better loop stability and immunity to noise on the tune node. 
    
    
     A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram illustrating a conventional phase locked loops circuit. 
     FIG. 2 is a block diagram illustrating an embodiment of a phase locked loop circuit in accordance with the present invention. 
     FIG. 3 is a schematic diagram illustrating an embodiment of a charge pump circuit utilizable in the FIG. 2 phase locked loop circuit. 
     FIG. 4 is a block diagram illustrating an embodiment of a voltage controlled oscillator utilizable in the FIG. 2 phase locked loop circuit. 
     FIG. 5a is a schematic diagram illustrating a current mirror utilizable in a conventional PLL. 
     FIG. 5b is a schematic diagram illustrating an embodiment of a current mirror utilizable in the FIG. 4 VCO. 
     FIG. 6 is a schematic diagram illustrating a configuration where two PLL&#39;s are used to allow switching from one pre-lock condition to the next. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     When a PLL is used in digital circuits to multiply the incoming clock frequency up, the frequency at which the VCO is oscillating and the frequency at which the incoming signal is oscillating will typically not change while the circuit is active. In this application, it might be said that the VCO needs to maintain a particular frequency over variations in process, temperature and voltage. Since both frequencies are known, and they will not change, it would be nice to center the VCO operating range around this point. Doing so minimizes the range over which the VCO needs to operate by reducing the effect of process variations. This can be accomplished by breaking the locking process into two steps. The first step is to adjust the VCO so that it&#39;s center frequency matches the incoming frequency multiplied by N. This compensates for variations in process. This step in the locking process will be termed the &#34;pre-lock.&#34; The second step is to close the loop and allow the input to the VCO to be controlled by the phase detector and charge pump. Note that after performing the pre-lock, the only variables left in the loop that can change are temperature and voltage. This will drastically reduce the range over which the VCO will need to operate. 
     Note that the pre-lock needn&#39;t be exact. This step is only a rough tuning of the VCO. If the center of the operating range is not exactly obtained, it will not necessarily ruin the operation of the loop. It does mean that the VCO will have to cover a wider range of frequencies, resulting in a higher gain VCO. Therefore, the closer one can get to the center frequency, the narrower one can make the frequency range of the VCO, and the resulting gain of the VCO will be lower. Error in the center frequency means only that the gain cannot be gotten optimally low. 
     One drawback of this approach is that once the system has switched from pre-lock mode to normal operation, it cannot go back without halting the operation of the chip. If temperature and voltage variations cause the PLL to reach the compliance limit on the input of the VCO and the system wanted to go back and pre-lock the loop again, the loop would have to be opened and would become unlocked. All timing relationships between the reference frequency and the VCO output would be lost until the loop was able to re-lock. 
     One way around this problem is to have two PLL&#39;s running simultaneously. Both would be locked onto the reference frequency, but they would be pre-locked to different center frequencies. That way, when the compliance limit of one PLL is reached, one could seamlessly switch to the other PLL since they are both locked. FIG. 6 shows this implementation. Note that there are many ways to implement this. For example, one could have the second PLL continuously in pre-lock while the first is supplying the desired output frequency. In this embodiment, the tune node voltage of the first PLL is monitored. If the tune node is approaching a compliance limit on the input of the VCO, the pre-lock inputs to the VCO of the second PLL are adjusted to take the next pre-lock state that would move the tune node voltage more towards the center of the compliance range. Once the second PLL has made that change and achieved analog lock, the mux at the outputs of the PLL&#39;s can be switched so that the output of the second PLL is used. Note that when the switch is made, both PLL&#39;s are in analog lock with the input frequency. Since they are both in analog lock, both of their outputs must meet jitter and phase noise specs, and this is why switching between the two can be seamless without violating jitter and phase noise specs. At this point, the first PLL can be adjusted to occupy the next pre-lock state so that if the tune node of the second PLL begins to approach a compliance limit on the input of the VCO, the mux can be switched back to the first PLL to keep the tune node in the compliance range. 
     The &#34;pre-lock&#34; can be accomplished in a variety of ways. One way is to simply vary the number of stages in the VCO by muxing. Another way is to change the device sizes or the loads of each stage in the oscillator. It is intended that the concept of the present invention cover all implementations of a pre-lock PLL. 
     In the preferred embodiment of the invention, a VCO is used wherein the pre-lock is performed by digitally programming a static current in the reference current generator of the VCO. This static current is an offset that will set the center frequency of the VCO. In the locked state, this current will be constant and will always be flowing. 
     FIG. 2 shows this PLL implementation 200. It is similar to the implementation shown in FIG. 1, but has three extra blocks and extra signals running to the charge pump 204 and the VCO 208. The first new feature to be discussed is the pre-lock signal. This signal controls whether the loop is in pre-lock mode, or in analog lock mode. When the signal is high, the loop is in pre-lock; low means analog lock. The logic controlling this signal is contained in the pre-lock control block (PLCNTL) of FIG. 2. Once again there are many ways to implement this block of logic. The simplest way would be to use a counter that would be programmed to assert the pre-lock signal on startup and count a pre-determined number of clock cycles before deasserting the pre-lock signal. Note that the number of clock cycles counted would need to be enough to guarantee that pre-lock will be achieved under all process, temperature and voltage variations. In this embodiment, the pre-lock control block will start by forcing the pre-lock output high when the chip is started up. After that, it will monitor the UP and DOWN pulses being emitted by the DPFD. Once the pattern of one UP pulse, followed by one DOWN pulse, followed by one UP pulse, and finally followed by a DOWN pulse is detected, the pre-lock control block will force the prelock output low. This pattern of UP-DOWN-UP-DOWN indicates that the pre-lock circuitry has centered the VCO as close as possible to the input frequency. This block provides the automatic control of the pre-lock circuitry. 
     An embodiment of the charge pump circuit 204 is shown in detail in FIG. 3. It is configured such that when the prelock signal is high, it forces the tune node (VTUNE) to approximately mid-rail. This is done by turning on both the pull-up device 302 and the pull-down device 304 in the charge pump. In the standard PLL charge pump, the prelock signal does not exist and the pull-up and pull-down devices (302, 304) being driven by the prelock signal are not present. Forcing the tune node to mid-rail dictates that the center frequency of the VCO 208 will appear at the output. With the tune node in this state, the VCO 208 can now be adjusted to obtain the desired center frequency. 
     Referring back to FIG. 2, one of the added blocks is the digital phase detector (DPFD) 212. When the PLL 200 is in pre-lock, this phase detector 212 is active and samples the input frequency and the feedback frequency (ffb) much the same as the PFD 202. However, in this case, it is not important for the UP and DOWN pulses to be proportional to the phase difference, and the DPFD will sample 10 cycles at its fref or ffb inputs in order to determine whether to emit an UP or a DOWN pulse. 
     The reason that the pulses need not be proportional to the phase difference is that they are only going to be used to control an UP/DOWN counter in the digital control block 214, which is described in greater detail below. An UP pulse will only cause the counter to count up 1, and a DOWN pulse will only cause the counter to count down 1. 
     The reason for sampling more than one cycle at the inputs of the DPFD 212 is to eliminate the chance that the loop will oscillate in the pre-lock mode. By implementing the pre-lock, a whole new feedback control system has been created, with it&#39;s own loop equation and gain terms. This new system must be characterized just like the loop in the analog state. By sampling 10 cycles, the DPFD allows the VCO to settle to it&#39;s new state before making a decision on whether to emit an UP or DOWN pulse. 
     As stated above, the digital control block 214 is simply an UP/DOWN counter. It is enabled by the prelock input. When prelock is high, a pulse at the UP input causes the counter to increment by 1; and a pulse on the DOWN input causes the counter to decrement by 1. When the prelock input is low, the counter will hold it&#39;s present state and ignore any pulses at the UP and DOWN inputs. What this does is set the state of the DCN0-DCN3 inputs to the VCO 208. The state of these nodes controls the amount of static current. 
     FIG. 4 shows the VCO 208. This is virtually the same VCO that is used in the PLL 100 of FIG. 1 except that the current mirror (CURMIR) block 402 receives the four digital inputs DCN0-DCN3. The current mirror used in the standard PLL 100 of FIG. 1 is shown in FIG. 5a; the current mirror 402 used in the pre-lock PLL 200 of FIG. 2 is shown in FIG. 5b. The way the FIG. 5b circuit 402 operates is that the current flowing through the PMOS device 502 in the upper left of the schematic (designated &#34;IREF&#34;) is the reference current. The current flowing through each stage of the oscillator will match that reference current. More current implies that each stage of the oscillator will switch faster and the frequency of the oscillation will be faster; less current implies slower switching and a slower oscillation. Hence, controlling the current through that PMOS device 502 will control the speed at which the oscillator is oscillating. 
     In the standard current mirror (FIG. 5a), all of the current through the PMOS device 502 is controlled by the analog input (VCOIN). The range of that current must be sufficient to allow the oscillator to cover the range of frequencies needed. This includes compensating for variations in process, temperature and voltage. 
     In the digitally programmable current mirror 402 shown in FIG. 5b, the current through the PMOS device 502 is controlled by both the digital inputs (DCN0-DCN3) received from the digital control logic 214, and by the analog input (VCOIN). This is where the digital programming comes in to set the static current. In the pre-lock state, the DCN0-DCN3 inputs are programmed to set up a static current through the PMOS device 502 and, once out of pre-lock, those inputs will not change. That leaves the VCOIN input to control the current through the PMOS device 502. In this case, the range of current that must be forced through the PMOS device 502 is smaller because the digital inputs have been used to program the static current to compensate for variations in process and the analog input need only cover a range to compensate for temperature and voltage variations. 
     It should be understood that various alternatives to the embodiment of the invention described herein may be employed in practicing the invention. Thus, it is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.