Abstract:
A reset circuit comprising: a first depletion mode device having a first terminal coupled to a node at a reset voltage and a second terminal for providing a reset signal to at least one device; and a control circuit arranged to switch the first depletion mode device into a high impedance state after a first predetermined period.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to a reset generator. 
       BACKGROUND OF THE INVENTION 
       [0002]    Reset generators are used to apply a reset signal to processors and other circuits. Such a signal may be provided shortly after a circuit has powered up so as to ensure that it is in a known state. They may also be used to supply a reset signal in the event of power supply “brown out” or if a processor gets “hung” or otherwise stalled such that it is probable that its operation has become compromised. 
         [0003]    It is well recognised that an important aspect of the “reset” function is to avoid giving false reset signals to the processor. As a result the reset generator is generally designed to be robust in the presence of noisy supplies. 
         [0004]    A particularly difficult case is the state or evolution of the reset signal itself on initial power up of the reset circuit, especially when this coincides with device power up. 
       SUMMARY OF THE INVENTION 
       [0005]    According to a first aspect of the present invention there is provided a reset circuit comprising:
       a depletion mode device having a first terminal coupled to a node at a reset voltage and a second terminal for providing a reset signal to at least one device; and   a control circuit arranged to switch the depletion mode device into a high impedance state after a first predetermined period.       
 
         [0008]    It is thus possible, by use of a depletion mode device, to provide a reset circuit in which a low impedance path is immediately established between a reset voltage source and a reset terminal even during power up of the reset generator itself. 
         [0009]    In an exemplary embodiment of the invention the reset signal is an active low signal. Consequently the first terminal of the depletion mode device, which may be a transistor, is preferably coupled to a local ground. Advantageously the first terminal of the transistor is a source terminal and the second terminal of the transistor is a drain terminal. 
         [0010]    Advantageously the control circuit includes a drive arrangement connected to a gate of the transistor such that a drive signal is applied to the transistor to force it into a more conducting state prior to the end of the first predetermined period, and then to switch the transistor into a non-conducting state after the end of the first predetermined period. Advantageously the duration of the first predetermined period may be set by a timer, such as a resistor-capacitor timer. Such a timer may be implemented as a mono-stable. 
         [0011]    Advantageously a bias arrangement, such as a resistor connected to a supply rail, is provided to bias the reset signal to an inactive state when the transistor is not conducting. 
         [0012]    According to a second aspect of the present invention there is provided an electrical device having a processor or other computing element in combination with a reset circuit constituting an embodiment of the first aspect of the present invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    The present invention will now be described by way of non-limiting example only with reference to the accompanying drawings, in which: 
           [0014]      FIG. 1  schematically illustrates the idealised operation of a reset generator during application of a supply voltage to a circuit; 
           [0015]      FIG. 2  schematically illustrates a prior art reset generator; 
           [0016]      FIG. 3  schematically illustrates a potential evolution with respect to time of the reset voltage during power up; 
           [0017]      FIG. 4  schematically illustrates a reset generator constituting a first exemplary embodiment of the present invention; 
           [0018]      FIG. 5  is a circuit diagram of a reset generator constituting a second exemplary embodiment of the present invention; and 
           [0019]      FIGS. 6   a  and  6   b  compare the evolution of the supply voltage with a control voltage at a gate of the output field effect transistor in the circuit shown in  FIG. 5 . 
       
    
    
     DESCRIPTION OF EXEMPLARY EMBODIMENTS 
       [0020]      FIG. 1  shows the evolution with respect to time of the voltage supplied to a circuit at a switch on event, which will also be referred to as “power up”. It has been assumed, for simplicity, that the supply is made via an electrically controllable switch such that undesirable features such as contact bounce have been eliminated. Connection to the supply is initiated at time T 0 . However due to the finite impedance of the voltage supply and the inclusion of capacitive components in the circuit, the supply does not rise instantaneously to its final voltage Vs but instead ramps up during a period spanning T 0  to T 1 . The ramp has been drawn as linear although it may in practice have a non-linear component. After T 1  the supply voltage can be assumed to be stabilised. 
         [0021]    Electronic circuits including digital processors may power up in an undefined state. This may result in undesirable control signals being issued to components controlled by the processor. It is therefore known to provide a reset generator whose function is to hold a reset pin of a digital circuit in its reset state for a predetermined time period after initiation of the power up sequence, such that the supply to the processor or other digital components can be assumed to have become stable. 
         [0022]    In the idealised arrangement shown in  FIG. 1  the reset signal is active low, i.e.  reset , and the signal  reset  remains at zero volts until the time T 2  where it gets released thereby allowing the processor to commence operation. 
         [0023]    Such a power on reset has hitherto been provided by a circuit similar to that shown in  FIG. 2 . The circuit shown in  FIG. 2  comprises a timer  10  connected to the power supply line  11 . The timer typically comprises a resistor-capacitor circuit optionally in a mono-stable such that the output of the timer switches abruptly as the voltage across capacitor within the timer rises. Such a circuit is known to the person skilled in the art. The timer starts with its output “high” and at the end of the timer period the output of the timer goes “low”. The timer  10  is connected to a series combination of a pull down transistor  12  and pull up transistor  14 . The transistor technology may be field effect or bipolar. An output node  16  is connected to the interface between the transistor  12  and transistor  14 . Consequently, when the pull down transistor is conducting, because the timer is still counting out its timer period, then the transistor  12  pulls node  16  down to the local ground. However, once the timer reaches the end of its timer period, the output of the timer goes low switching pull down transistor  12  into a non-conducting state, and the pull up transistor  14  on. Thus the pull up transistor  14  now pulls node  16  high, thereby releasing the reset signal. 
         [0024]    A potential issue is that the timer may itself not come up cleanly upon restoration of power. During the period where the power supply is ramping up between zero and Vs, parasitic capacitances within the timer or other circuits connected to the reset node  16  may cause the voltage at the reset node  16  to fluctuate as schematically illustrated in  FIG. 3 . A microprocessor may have many gates, each exhibiting a capacitance, connected to its reset terminal. Consequently the capacitive load in the microprocessor may be quite large, and “plates” of these capacitors may drift upwardly in voltage as the supply becomes established. Furthermore, it will take a short time for the voltages within the reset circuit to establish such that the pull down transistor  12  is definitely on, and the pull up transistor is definitely off. Here the voltage at the reset node fluctuates between time periods T 0  and T 2 . 
         [0025]      FIG. 4  is a circuit diagram showing a first reset generator constituting an embodiment of the present invention. The reset generator which is generally designated  20 , is responsive to a timer, for example of the type shown in  FIG. 2  and designated  10 . 
         [0026]    The reset generator circuit comprises a depletion mode transistor  30  having its drain  32  connected to the  reset  output node  16 . A source  34  of the transistor  30  is connected to the local ground which, in battery powered equipment, is typically connected to the negative terminal of the battery. A gate  36  of the transistor  30  is connected to ground via a resistor  40 . The function of the resistor is to ensure that the gate voltage of the transistor  30  is well defined during the initial stage of application of the power supply to the circuit containing both the processor that needs to be reset and the reset generator  20 . 
         [0027]    Because the field effect transistor  30  is a depletion mode device, the transistor is conducting immediately, and the “pull down” strength of the  reset  node  16  to ground is determined by the size of the FET and its characteristics at V GS =0. 
         [0028]    The reset circuit also contains a charge pump  42  responsive to the timer  10  and connected to the gate  36  of the transistor  30 . The resistor  40  holds the gate of the transistor at ground whilst the charge pump remains off. The construction and operation of charge pumps is well known to the person skilled in the art but by way of a reminder they operate by the selective connection and disconnection of capacitor terminals between supply voltages in response to a switching signal. This means that the charge pump will not become operative until the supply voltage to it and/or system clocks used by the charge pump to control the switching therein have become sufficiently established in order to cause the clocks to operate. Consequently there is no risk of the charge pump  42  becoming accidentally operative during the period T 0  to T 1  shown in  FIG. 1  and then the charge pump remains disabled because of the operation of the timer  10  until such time as the timer  10  times out. Once the timer  10  expires, and asserts its signal (for example by transitioning from “low” to high), the charge pump  42  becomes enabled thereby generating a negative voltage which pulls the gate electrode of the transistor  36  below ground, creating a voltage that is less than the negative voltage threshold of the depletion mode field effect transistor. This shuts the field effect transistor  30  off such that it is no longer conducting and allows the  reset  node to be pulled up by other means (such as a PMOS transistor or resistor to the positive supply rail), without incurring any power penalty due to the size of the field effect transistor. 
         [0029]    Because the resistor  40  is substantially only loaded by the gate capacitance of the transistor  30 , it can be made large and hence even when the charge pump is operating the combined power required to operate the charge pump and the dissipation resulting from current flow through resistor  40  can be made very low. 
         [0030]    In the arrangement shown in  FIG. 4 , the strength of the “pull down” is substantially invariant, and remains largely independent of the supply voltage. Put another way, the resistance presented between node  16  and ground  34  is solely that dictated by the transistor when V GS =0 and does not become modified as the supply becomes established. However the transistor could be made more conducting (less resistive) if the gate voltage was made more positive as the power supply became established until such time as it is desired to release the reset by turning the charge pump  42  on. 
         [0031]      FIG. 5  shows the circuit diagram for a second exemplary embodiment of the present invention. It represents a modification of the circuit shown in  FIG. 4 , and like parts are represented with like reference numerals. The field effect transistor  30  can now be regarded as being the first field effect transistor in the circuit, and it is joined by a second field effect transistor  50  in series combination with a resistor  52  and a third field effect transistor  54 . The second field effect transistor  50  is a depletion mode device having its drain connected to the positive supply rail and its source connected to a first terminal of the resistor  52 . The second terminal of the resistor  52  is connected to a first terminal of the resistor  40  and a drain of the third transistor  54 . A source of the third transistor  54  is connected to ground. A gate of the second transistor  50  is connected to ground via a resistor  60 . A gate of the third transistor  54 , which is an enhancement mode device, is connected to receive the control signal generated by the timer  10 . 
         [0032]    Whilst the timer is counting out its time period and its output (in this example) is low, the third transistor  54  is switched off. Starting from T 0  when the supply is initiated, as shown in  FIG. 6 , the supply voltage ramps upwardly towards V S  at time T 1 . This corresponds to the arrangement shown in  FIG. 1 . During this time, the voltage at the source of the second transistor  50  also ramps upwardly, effectively following the supply voltage, until such time as V GS  for the second transistor  50  becomes sufficiently small to start to turn the transistor off. At this time the voltage at its source becomes effectively stable, as designated by time T 3  in  FIG. 6   b . Thus the voltage supplied to the gate of the first field effect transistor  30  has now risen above zero volts and become clamped from T 3  onward. The results in the first transistor  30  being driven further on, thereby having a lower on resistance between node  16  and ground. This enhanced conductivity continues until such time as the timer  10  times out and asserts its signal, its output going high, thereby switching the negative charge pump  42  on, and also switching the third field effect transistor  54  on. At this point the third field effect transistor  54  pulls the voltage at a node  56  between the first resistor  40  and the second resistor  52  down to ground, thereby causing the voltage applied to the gate of the transistor  30  to reduce. Near simultaneously, the charge pump  42  starts to become active supplying a negative voltage to the gate of the transistor  30  thereby dragging it below its voltage threshold and turning the transistor off. 
         [0033]    It should be noted that until such time as the third transistor  54  is turned on there is no current in the resistor  52 , and hence this is a very low power circuit. When transistor  54  is turned on, current passes through the resistor  52 , thereby dissipating power equal to the voltage squared over the value of the resistor  52 . This dissipated power can be kept low if resistor  52  is large. It will be observed that the third transistor  54  could be omitted and that the charge pump  42  could be used on its own to switch transistor  30  off. This would however increase the voltage difference across the resistor chain formed by resistors  40  and  52  potentially requiring use of a larger charge pump. 
         [0034]    It should be noted that, if desired, a further stage comprising components arranged in a configuration similar to the second transistor  50 , the resistor  52  and the third transistor  54  can be connected to the second resistor  60  in place of the ground terminal. Indeed, the input stages could be cascaded time and time again. 
         [0035]    Turning to  FIG. 6 , it can be seen that once the timer expires the gate voltage at the gate of the first field effect transistor  30  goes negative at time T 2  thereby causing the reset signal to be inhibited. 
         [0036]    Although so far the timer has been shown as the only device capable of inhibiting or disabling the generation of the reset signal, other reset devices, such as watch dog timers, may be provided. As shown in  FIG. 5 , the control terminal to the charge pump  42  may also be connected to other reset triggers. This also applies to the arrangement shown in  FIG. 4 . 
         [0037]    Although the embodiments have been described with the transistor  30  being a N type depletion mode device, it should be appreciated that P-type devices can also be used with a suitably modified drive circuit. 
         [0038]    This application has been drafted for filing at the United States Patent and Trade Mark Office where single dependency claims are the norm. For other jurisdictions where multiple dependencies are allowed it is to be assumed that any dependent claim is dependent upon any preceding claim sharing the same independent claim, unless such a dependency is clearly technically not feasible.