Abstract:
A microcontroller-based device according to the present invention provides a watchdog timer having an emulator support mode for disabling and reconfiguring time-outs. When the watchdog timer is placed in the emulator support mode, the watchdog timer is inhibited from counting. In a disclosed embodiment, the watchdog timer is inhibited from counting by deasserting a count enable signal. A watchdog time-out is thus prevented from occurring during the emulator support mode. Also, during the emulator support mode, the watchdog timer control register is writable, allowing the emulator to disable a watchdog timer, enable the timer, or program a new time-out value for the timer. The watchdog timer control register is writable regardless of the state of the enable bit of the timer. Further, in the emulator support mode, a watchdog timer current count becomes readable and writable at a predetermined register address above the watchdog timer control register subsequent to a write of a write key sequence to the watchdog timer control register. By writing and reading the predetermined register address location, the emulator is able to define and monitor a condition as the watchdog timer is approaching its timeout value. By monitoring a condition as the watchdog timer approaches its timeout value, a software debugger may better predict and appreciate the behavior of a microcontroller-based device prior to a watchdog time-out. In a disclosed embodiment, the watchdog timer current count is readable and writable through a watchdog timer count high register and a watchdog timer count low register.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to emulator support for microcontrollers, and more particularly to an emulator support mode for disabling and reconfiguring time-outs of a watchdog timer. 
     2. Description of the Related Art 
     A traditional method of debugging an embedded system or other microcontroller-based device is to use an in-circuit emulator. An in-circuit emulator is primarily used in addressing problems such as signal synchronization, clock frequency, and trace bandwidth. To facilitate in-circuit emulation of code in a microcontroller-based device, breakpoints are commonly set throughout user or application code to be executed on the microcontroller. At each breakpoint, emulator code takes over and is run on the microcontroller in the place of user code. For numerous applications, a watchdog timer is enabled during code execution. Once enabled, a watchdog timer becomes read-only and may not be disabled or reconfigured. After the programmed time-out period, the watchdog timer generates a watchdog time-out unless the timer is refreshed or reset. A watchdog time-out event is an event indicating that software is behaving in a faulty and unexpected way. The occurrence of a watchdog time-out which indicates that a watchdog time-out event has occurred desirably generates a non-maskable interrupt or a reset of the microcontroller or the microcontroller-based device as recovery from the software malfunction. The occurrence of a watchdog time-out which does not indicate that a watchdog time-out event has occurred, however, disrupts code execution. A watchdog time-out is particularly undesirable during an emulation mode of a microcontroller-based device since the state of the device during an emulation mode is ill-suited to processing a watchdog time-out. 
     Conventional watchdog timers have required repetitive and periodic refreshing during watchdog timer code execution and emulator code execution to prevent a watchdog time-out. During watchdog timer code execution, each refresh of the watchdog timer has been performed by watchdog timer code, and during execution of emulator code, each refresh of a watchdog timer has been performed by the emulator. Generating invasive resets of a watchdog timer within emulator code at each of the appropriate times has been highly difficult. The use of emulators for the debug of watchdog timer code has thus been correspondingly difficult. 
     Emulator code is designed to interact with watchdog timer code such that following a breakpoint, the user is unable to determine when emulator code is being executed and when watchdog timer code is being executed. Refreshing of a watchdog timer by emulator code undesirably masks to the user whether the watchdog timer code is refreshing the watchdog timer with sufficient frequency to prevent a watchdog time-out. The resets to the watchdog timer defined within the watchdog timer code may not occur or may occur prematurely depending on the location of breakpoints within the watchdog timer code and the duration of the execution of emulator code following the breakpoints. 
     In an effort to predict how a microcontroller-based device may behave prior to a watchdog time-out, a user has typically set a watchdog timer for a short time-out period and then observed the effect upon the device. The user then extrapolates that effect in an attempt to predict how the device might react prior to the watchdog time-out. This approach yields significant inaccuracies that pose a high degree of software debug uncertainty. 
     SUMMARY OF THE INVENTION 
     Briefly, a microcontroller-based device according to the present invention provides a watchdog timer having an emulator support mode for disabling and reconfiguring time-outs. When the watchdog timer is placed in the emulator support mode, the watchdog timer is inhibited from counting. In a disclosed embodiment, the watchdog timer is inhibited from counting by deasserting a count enable signal. A watchdog time-out is thus prevented from occurring during the emulator support mode. 
     Also, during the emulator support mode, a watchdog timer control register is writable, allowing the emulator to disable the watchdog timer, enable the timer, or program a new time-out value for the timer. The watchdog timer control register is writable regardless of the state of the enable bit of the timer. 
     Further, in the emulator support mode, a watchdog timer current count becomes readable and writable at a predetermined register address above the watchdog timer control register subsequent to a write of a write key to the watchdog timer control register. By writing and reading the predetermined register address location, the emulator is able to define and monitor a condition as the watchdog timer is approaching its time-out value. 
     By monitoring a condition as the watchdog timer approaches its time-out value, a software debugger may better predict and appreciate the behavior of a microcontroller-based device prior to a watchdog time-out. In a disclosed embodiment, the watchdog timer current count is readable and writable through a watchdog timer count high register and a watchdog timer count low register. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A better understanding of the present invention can be obtained when the following detailed description of the preferred embodiment is considered in conjunction with the following drawings, in which: 
     FIG. 1 is a block diagram of a microcontroller including a watchdog timer core and associated cores in accordance with the present invention; and 
     FIG. 2 is a schematic diagram of the watchdog timer core of FIG. 1. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Turning now to the drawings, FIG. 1 depicts a block diagram of a microcontroller C including a watchdog timer 10 of the present invention. The microcontroller C may be used to provide a variety of control functions for a processor-based device. The watchdog timer 10 is used to regain control of the processor-based device if software run by the microcontroller C fails to respond or behave as expected. When the watchdog timer 10 is active, a repetitive software function is required to access the timer 10 and reset the timer 10 at a rate that is faster than the time-out value of the timer 10. If the timer 10 is not reset before the duration of the watchdog timer time-out interval, the timer 10 generates a reset of the microcontroller C, a reset of the processor-based device, or a non-maskable interrupt (NMI). A reset of the processor-based device is provided as a RST signal by the timer 10 to various internal cores 22 of the microcontroller C. Examples of internal cores 22 which may receive the RST signal include a DMA controller, a microprocessor core 19, timers, counters, an interrupt controller, a universal serial bus (USB) controller, a bus interface unit, an execution unit 18, a chip-select unit, a peripheral control block (PCB) bus controller 12, and miscellaneous logic. The RST signal is also provided to I/O pads logic 20 to latch the state of various input pins of the microcontroller C when an externally generated reset occurs. If a watchdog timer NMI event occurs rather than a reset, then the timer 10 provides an ANY --  NMI signal to the execution unit 18. 
     Various signals are provided between the watchdog timer 10 and the I/O pads logic 20. The watchdog timer 10 provides a RST --  WEAKPULL signal and a CO --  RESOUT signal to the I/O pads logic 20. The RST --  WEAKPULL signal is asserted when either a CI --  URST --  L signal is asserted or the RST signal is asserted. The RST --  WEAKPULL signal is used by the I/O pads logic 20 to enable a pull-up at an I/O pad 21. A pull-up ensures that an input path is properly terminated during an externally generated reset or a reset due to a watchdog timer time-out. The RST --  WEAKPULL signal may also be used to enable a pull-down termination in an I/O pad 21. The CI --  URST --  L signal is provided by the I/O pads logic 20 to the watchdog timer 10. This signal is asserted in response to an externally generated reset. A CI --  LNMI signal is also provided by the I/O pads logic 20 to the watchdog timer 10. The CI --  LNMI signal is driven from the external NMI pin and is ORed together with the time-out NMI source to generate the ANY --  NMI output signal. During a watchdog timer reset, the CO --  RESOUT signal is held for multiple cycles to provide a signal of sufficient duration to ensure reset of various components which may exist on a board housing the watchdog timer 10. 
     The input signals provided by the PCB bus controller 12 to the watchdog timer 10 include a PCB --  AD signal, a PCB --  WR --  DATA signal, a PCB --  RD signal, a PCB --  WR signal, and a WDT --  BLOCK --  SEL signal. In the disclosed embodiment, the PCB --  AD signal consists of 2 bits, and the PCB --  WR --  DATA signal consists of 16 bits. The PCB --  AD signal represents a PCB address bus used in conjunction with the WDT --  BLOCK --  SEL signal to decode accesses to registers in the watchdog timer 10. The PCB --  WR --  DATA signal represents a PCB write data bus containing data to be written to PCB registers in the watchdog timer 10. The PCB --  RD signal indicates a read cycle from the PCB bus controller 12, and the PCB --  WR signal indicates a write cycle from the PCB bus controller 12. The WDT --  BLOCK --  SEL signal is used to select PCB registers in the timer 10. The PCB --  RD --  DATA signal provided by the timer 10 to the PCB bus controller 12 represents a PCB read data bus containing data read from the PCB registers in the timer 10. In the disclosed embodiment, the PCB --  RD --  DATA signal consists of 16 bits. 
     The clock drivers 14 and scan control core 16 also provide signals to the watchdog timer 10. The clock drivers 14 provide a PH1 signal representing one system clock and a PH2 signal representing a second system clock. The scan control core 16 provides a SCAN --  MODE signal for enabling a scan mode. Use and operation of a scan mode is known in the art. The scan control core 16 also provides a TEST --  RESET --  L signal that is multiplexed with the RST signal for resetting scan blocks. A table including each of the signals discussed above is provided below: 
     
         ______________________________________Signal Name  Description______________________________________PCB.sub.-- AD(2:1)        PCB address bus from the PCB bus controller        used in conjunction with the        WDT.sub.-- BLOCK.sub.-- SEL input to decode the        WDT register accesses.PCB.sub.-- WR.sub.-- DATA(15:0)        PCB Write Data bus contains the data to be        written to the PCB registers.PCB.sub.-- RD.sub.-- DATA(15:0)        PCB Read Data bus contains the data read from        the PCB registers.PCB.sub.-- RD        PCB read indicates a read cycle from the PCB        bus controller.PCB.sub.-- WR        PCB write indicates a write cycle from the PCB        bus controller.WDT.sub.-- BLOCK.sub.-- SEL        Select for WDT block PCB registers.PH1          PH1 one system clock.PH2          PH2 two system clock.ANY.sub.-- NMI        Non-maskable interrupt indication to the        execution unit. This signal is asserted as a        result of the watchdog timer NMI event or        when the CI.sub.-- LNMI input is asserted.CI.sub.-- LNMI        External NMI request from the I/O pad logic.        Asserted when an external NMI is asserted high        and synchronized.CI.sub.-- URST.sub.-- L        Externally generate Reset input from the Reset        I/O PAD logic.RST.sub.-- WEAKPULL        Reset Pull Up Control. This signal is used to        enable the weak pullups and pulldowns in the        pads.RST          This is the primary reset for all internal cores.        RST is asserted when CI.sub.-- URST.sub.-- L (external        reset) is asserted or when a WDT reset event        occurs.CO.sub.-- RESOUT        This the external reset signal provided by the        part to the board.SCAN.sub.-- MODE        Scan mode enable.TEST.sub.-- RESET.sub.-- L        The WDT muxes the value of        TEST.sub.-- RESET.sub.-- L with RST to allow for a        reset of the scan blocks.______________________________________ 
    
     It should be understood that the microcontroller C may integrate a variety of functions in addition to the functions of the watchdog timer 10. These other functions may for example include interrupt control, DMA control, synchronous serial port control, bus control, memory control, peripheral control, programmable I/O control, address control, and clock control. A wide variety of microcontrollers could be used instead of the disclosed microcontroller C without detracting from the spirit of the invention. Further, although the term microcontroller is sometimes used to denote a processor with memory implemented on a single integrated circuit, here the term more broadly includes embedded controllers, microprocessors, digital signal processors (DSPs) and the like. 
     Turning to FIG. 2, a schematic diagram of the watchdog timer 10 is shown. The watchdog timer 10 includes a key detect block wdt --  keydet 42, a register control block wdt --  regs 24, a reset block wdt --  reset 44, and a counter block wdt --  counter 48. 
     KEY DETECT BLOCK 
     The watchdog timer 10 supports two unique keyed sequences which are recognized by the key detect block wdt --  keydet 42. In the disclosed embodiment, 3333h followed by CCCCh serves as a write key, and AAAAh followed by 5555H serves as a count-clear key. Any number of processor cycles, including memory and I/O reads and writes, may be inserted between the first data pattern of a key and the second data pattern of a key. 
     The write key is used to open a WDTCON register in the register control block wdt --  regs 24. The WDTCON register includes a watchdog timer enable bit ENA. When the ENA bit is set to `1`, the watchdog timer 10 is enabled. The ENA is set to `1` when the write key is detected. When the ENA bit is set to `0`, the watchdog timer 10 is disabled. The key detect block wdt --  keydet 42 provides a reg --  write --  all signal and a reg --  write --  flags signal to the WDTCON register. The watchdog timer register block wdt --  regs 24 uses these signals to determine which bits are to be updated during a write. If a write has been previously detected which sets the ENA bit, the reg --  write --  flags signal is asserted. If a write bit has not been detected which sets the ENA bit since the last reset, the signal reg --  write --  all signal is asserted when the write key is detected. If neither the reg --  write --  all signal nor the reg --  write flags signal is asserted, then no bits in the WDTCON register are updated. If the reg --  write --  flags signal is asserted, only an NMIFLAG bit and a RSTFLAG bit in the WDTCON register may be updated. In an emulator support mode according to the present invention, ICE MODE, if the reg --  write --  all signal is asserted, all the bits of the WDTCON register are open to updating. In the ICE MODE, the reg --  write --  all signal is deasserted on a next access to the WDTCON register. Also, in the ICE MODE, access to all bits of the WDTCON register is provided by assertion of the reg --  write --  all signal regardless of whether there is a previous enabling write. 
     Register select signals are generated by the wdt --  regs block 24 and provided to the wdt --  keydet block 42. Each register select signal is used to indicate when a particular register is visible based on the mode of operation of the watchdog timer 10. A key --  WDTCON --  wrsel signal corresponds to the watchdog timer control register WDTCON. A key --  WDTCNTL --  wrsel signal corresponds to the watchdog timer count low register. A key --  WDTCNTH --  wrsel signal corresponds to a watchdog timer count high register. A key --  WDTRCNT --  wrsel signal corresponds to a watchdog timer reset count register. The signals PCB --  WR, PCB --  AD, PCB --  WR --  DATA, and WDT --  BLOCK --  SEL are provided by the PCB bus controller 12 to the wdt --  keydet block 42. The wdt --  keydet block 42 is thereby used to control access to registers within the wdt --  regs block 24. 
     The microcontroller C includes a system configuration (SYSCON) register 52 for setting an internal test mode, TEST MODE, or an emulator support mode according to the present invention, ICE MODE, for the watchdog timer 10. The SYSCON register 52 is shown in broken line to indicate that the SYSCON register 52 is external to the watchdog timer 10. The SYSCON register 52 includes a TEST --  MODE bit 54 for providing a TEST --  MODE signal to the wdt --  keydet block 42. TEST MODE is set by asserting the TEST --  MODE signal and deasserted by deasserting the TEST --  MODE signal. The SYSCON register 52 also includes an ICE --  MODE bit 56 for providing an ICE --  MODE signal to the wdt --  keydet block 42. ICE MODE is set or triggered by asserting the ICE --  MODE signal and exited by deasserting the ICE --  MODE signal. The ICE --  MODE bit 56 may only be written if an external pin of the microcontroller C is pulled during a reset. In this way, the integrity of the watchdog timer 10 is maintained. 
     WATCHDOG REGISTER BLOCK 
     The watchdog timer 10 provides a normal operational mode, an internal test mode, and an emulator support mode according to the present invention. In the normal operational mode, the watchdog register block wdt --  regs 24 uses the reg --  write --  all and the reg --  write --  flags signals to grant write access to the WDTCON register. In the emulator support mode, the reg --  write --  all signal is asserted when the write key is detected. The reg --  write --  flags signal is not asserted during the emulator support mode. 
     
         __________________________________________________________________________WatchDog Timer Control Register (WDTCON).15     14  13    12    11                    10                      9 8   7  6  5  4  3  2  1  0__________________________________________________________________________Bit ENA  WRST      RSTFLAG            NMIFLAG                  RES   EXRST                            ESR/W R/W  R/W R/W(0)            R/W(0)                  R R R R/W R/W                               R/W                                  R/W                                     R/W                                        R/W                                           R/W                                              R/W                                                 R/WDefault    1  1   0     0     0 0 0 1   1  0  0  0  0  0  0  0__________________________________________________________________________ 
    
     In the disclosed embodiment, the watchdog timer control register WDTCON is a 16-bit register. Bit 15 is defined as the watchdog timer enable bit ENA. The ENA bit is a read/write bit having a default value of `1.` When the ENA bit is set to `1,` the watchdog timer 10 is enabled. When the ENA bit is set to `0`, the watchdog timer 10 is disabled. Bit 14 is defined as a watchdog request signal WRST. The WRST bit is a read/write bit having a default value of `1.` When the WRST bit is set to `1,` the watchdog timer 10 generates a system reset when a watchdog timer time-out occurs. When the WRST bit is set to `0` and the NMIflag bit is set to `0,` the watchdog timer 10 generates an NMI when a watchdog timer time-out occurs. Bit 13 is defined as a reset flag bit RSTFLAG. The RSTFLAG bit is a read/write bit having a default value of `0.` When the RSTFLAG bit is set to `1,` a watchdog timer reset event has occurred. When the RSTFLAG bit is set to `0,` a watchdog timer reset event has not occurred. Further, the RSTFLAG bit may be cleared by software. 
     Bit 12 is defined as a NMIFLAG bit. The NMIFLAG bit is a read/write bit having a default value of `0.` When the NMIFLAG bit is set to `1,` a watchdog timer NMI event has occurred. If a watchdog timer time-out event occurs while the NMIFLAG bit is set, the watchdog timer 10 generates a system reset regardless of the setting of the WRST bit. When the NMIFLAG bit is set to `0,` a watchdog timer NMI event has not occurred. The NMIflag bit also may be cleared by software. In the disclosed embodiment, bits 11 through 9 are reserved. Bit 8 is defined as an external reset enable bit EXRST. The EXRST bit is a read/write bit having a default value of `1.` When the EXRST bit is set to `1,` the watchdog timer 10 generates an external reset signal whenever a watchdog timer reset event occurs. When the EXRST bit is set to `0,` an external signal has not been generated during watchdog timer resets. The EXRST bit is set by an externally generated reset and is not changed by a watchdog timer reset. Bits 7 through 0 are defined as an exponent select field ES. The ES bits are read/write bits. Bit 7 of the ES bits has a default value of `1` and bits 6 through 0 of the ES bits have a default value of `0.` The exponent select field ES determines the duration of the watchdog timer time-out interval. The watchdog timer exponent selections table provided below represents how different bit combinations of the exponent select field ES result in different time-out intervals. 
     
         ______________________________________Bit 7Bit 6   Bit 5  Bit 4                    Bit 3                         Bit 2                              Bit 1 Bit 0                                         Exponent______________________________________0    0       0      0    0    0    0     0    N/AX    X       X      X    X    X    X     1    10X    X       X      X    X    X    1     0    20X    X       X      X    X    1    0     0    21X    X       X      X    1    0    0     0    22X    X       X      1    0    0    0     0    23X    X       1      0    0    0    0     0    24X    1       0      0    0    0    0     0    251    0       0      0    0    0    0     0    26______________________________________ 
    
     The time-out duration is a function of an exponent and a frequency of a central processing unit core in the microcontroller C. The equation for calculating the time-out duration follows: 
     
         Time-out Duration=2.sup.Exponent / CPU frequency. 
    
     With this equation, time-out duration is the time-out period for the watchdog timer 10 in seconds. Exponent is the value given from the table above, and CPU frequency is the operating speed of the CPU in Hertz (Hz). 
     WATCHDOG COUNTER BLOCK 
     Various signals are provided between the watchdog counter block wdt --  counter 48 and the watchdog register block wdt --  regs 24. A cnt --  enable signal is provided from the register block wdt --  regs 24 to the counter block wdt --  counter 48. The cnt --  enable signal is asserted when the ENA bit in the WDTCON register is set and the ICE --  MODE bit 56 of the SYSCON register 52 is not set. The cnt --  enable signal is used by the counter block wdt --  counter 48 to enable a watchdog timer current counter WDTCNT 50. The watchdog timer current counter 50 represents the current count of the watchdog timer 10. The current count is increased once for every PH1 clock cycle while the cnt-enable signal is asserted. The current count is cleared if a cnt --  reset signal is asserted indicating that the count clear key has been detected or that a write which enabled the timer 10 has just occurred. The current count is also cleared if the counter 50 matches a compare value and a rst --  timeout signal provided by the counter block wdt --  counter 48 to the reset block wdt --  reset 44 is asserted. The rst --  timeout signal is generated when a bit is set in the watchdog timer current counter WDTCNT 50 that is also set in the ES field of the WDTCON register. Multiple cnt --  exp signals are used to pass the value of the ES field and the WDTCON register to the counter block 48 wdt --  counter. An additional event causing the current count to be cleared is the assertion of the RST signal. The current count is provided from the counter block 48 to the register block wdt --  regs 24 as a reg --  count signal. 
     A cnt --  newcount bus for containing a new count is provided from the register block 24 to the counter block 48 wdt --  counter. In the disclosed embodiment, the cnt --  new count bus is 16 bits. A cnt --  load --  count --  low signal is used to load data from the cnt --  new count bus into the lower 16 bits of the watchdog timer current counter WDTCNT 50. The cnt --  load --  count --  high signal is used to load data from the cnt --  new --  count bus into bits 26:16 of the watchdog timer current counter WDTCNT 50. 
     
         ______________________________________WatchDog Timer Count Low Register (WDTCNTL).______________________________________15         14     13     12    11   10   9    8______________________________________Bit     COUNTLR/W     R/W    R/W    R/W  R/W   R/W  R/W  R/W  R/WDefault 0      0      0    0     0    0    0    0______________________________________   7      6      5    4     3    2    1    0______________________________________Bit     COUNTLR/W     R/W    R/W    R/W  R/W   R/W  R/W  R/W  R/WDefault 0      0      0    0     0    0    0    0______________________________________ 
    
     The watchdog timer 10 is readable and writable through the watchdog timer count low register WDTCNTL and the watchdog timer count high register WDTCNTH. In the disclosed embodiment, the watchdog timer count low register WDTCNTL is a 16-bit register defining a COUNTL field. Also, in the disclosed embodiment, the COUNTL field is the 16 least significant bits of the watchdog timer current counter WDTCNT 50. If the ICE --  MODE bit 56 is set, the WDTCNTL register is available. The WDTCNTL register may only be written following a write key to the WDTCON register. The value of the COUNTL field is automatically reset when the watchdog timer 10 is enabled. The COUNTL field is reset by writing a write key to the WDTCON register. 
     
         ______________________________________WatchDog Timer Count High Register (WDTCNTH).______________________________________15         14     13     12    11   10   9    8______________________________________BIT     RESERVEDR/W     R      R      R    R     R    R/W  R/W  R/WDefault 0      0      0    0     0    0    0    0______________________________________   7      6      5    4     3    2    1    0______________________________________BIT     COUNTLR/W     R/W    R/W    R/W  R/W   R/W  R/W  R/W  R/WDefault 0      0      0    0     0    0    0    0______________________________________ 
    
     In the disclosed embodiment, the watchdog timer count high register WDTCNTH is a 16-bit register. Bits 11 through 15, which are read-only, are preferably reserved. Bits 0 through 10 represent the COUNTH field. The bits within the COUNTH field are readable and writable. The default value for each bit within the COUNTH field is `0.` If the ICE --  MODE bit 56 is set, the WDTCNTH register is available. The WDTCNTH register may only be written following a write of the write key to the WDTCON register. The value of the COUNTH field is automatically reset when the watchdog timer 10 is enabled. In a normal operation mode, the COUNTH field is reset by writing a write key to the WDTCON register. In the disclosed embodiment, the COUNTH field is the eleven most significant bits of the watchdog timer current counter WDTCNT 50. 
     
         ______________________________________WatchDog Timer Reset Count Register (WDTRCNT).______________________________________  7   6       5     4     3   2     1   0______________________________________Bit      RCOUNTR/W      W     W       W   W     W   W     W   WDefault  0     0       0   0     0   0     0   0______________________________________    15    14      13  12    11  10    9   8______________________________________Bit      RCOUNTR/W      W     W       W   W     W   W     W   WDefault  0     0       0   0     0   0     0   0______________________________________ 
    
     In the disclosed embodiment, the watchdog timer reset count register WDTRCNT is a 16-bit register. Each bit of the WDTRCNT register is writable and has a default value of `0.` Bits 15 through 0 of the WDTRCNT register define the RCOUNT field. In the disclosed embodiment, the RCOUNT field contains the one&#39;s compliment of the number of processor clocks for which the RST signal should be asserted during a watchdog timer reset. 
     WATCHDOG RESET CONTROL BLOCK 
     Various signals are provided between the watchdog register block wdt --  regs 24 and the watchdog reset control block wdt --  reset 44. A reg --  setnmi signal and a reg --  setrst signal are provided from the reset block wdt --  reset 44 to the register block wdt --  regs 24. The reg --  setnmi signal is asserted to indicate that a watchdog timer NMI has occurred. The reg --  setnmi signal causes the NMIFLAG bit to be set. The reg --  setrst signal is asserted to indicate that a watchdog timer reset event has occurred. The reg --  setrst signal causes the RSTFLAG bit to be set. 
     When reg --  setrst signal is not asserted and the RST signal is asserted, each bit of the WDTCON register is placed in a reset condition. When both the RST signal and reg --  setrst signal are asserted, each bit of the WDTCON register except the RSTFLAG and EXRST bits is placed in a reset condition. A rst --  do --  reset signal is provided from the register block wdt --  regs 24 to the reset block wdt --  reset 44. The rst --  do --  reset signal is asserted when the WRST bit of the WDTCON register is set or when the NMIFLAG bit of the WDTCON register is set. When the rst --  do --  reset signal is asserted, the reset control block wdt --  regs 24 performs a reset, rather than an NMI when the watchdog timer 10 times out. The watchdog reset block 44 also receives the signal rst --  timeout signal from the watchdog counter block wdt --  counter 48. The rst --  timeout signal indicates to the wdt --  reset block 44 that a watchdog timer time-out has occurred. The wdt --  rst block 44 includes a wdt --  rst --  counter sub-block 46. The wdt --  rst --  counter sub-block 46 contains a counter used to time the duration of a watchdog timer reset. 
     A traditional method of debugging an embedded system or other microcontroller-based device is to use an in-circuit emulator. To facilitate in-circuit emulation of code in a microcontroller-based device, breakpoints are commonly set throughout watchdog timer code to be executed on the microcontroller. Once enabled, a conventional watchdog timer became read-only and could not be disabled or reconfigured. The occurrence of a watchdog time-out which does not indicate that a watchdog time-out event has occurred disrupts code execution. A watchdog time-out is particularly undesirable during an emulation mode of a microcontroller-based device since the state of the device during an emulation mode is ill-suited to processing a watchdog time-out. Further, refreshing of a watchdog timer by emulator code undesirably masks to the user whether the watchdog timer code is refreshing the watchdog timer with sufficient frequency to prevent a watchdog time-out. The resets to the watchdog timer defined within the watchdog timer code have not occurred or have occurred prematurely depending on the location of breakpoints within the watchdog timer code and the duration of the execution of emulator code following the breakpoints. 
     A system according to the present invention eliminates the need to reset a watchdog timer with emulator code by decoupling the timing of the watchdog timer 10 from emulator code execution. An emulator support mode in accordance with the present invention causes all bits of the WDTCON register to be writable regardless of whether the ENA bit has been set by software, allowing an emulator to disable the watchdog timer 10 if desired. The present invention thus allows an in-circuit emulator to be effectively used with watchdog timer code. 
     In an effort to predict how a microcontroller-based device may behave prior to a watchdog time-out, a user has typically set a watchdog timer for a short time-out period and then observed the effect upon the device. The user then extrapolates that effect in an attempt to predict how the device might react prior to the watchdog time-out. This conventional approach has yielded significant inaccuracies that pose a high degree of software debug uncertainty. 
     A system according to the present invention provides an improved approach for testing a device&#39;s handling of watchdog time-outs. In an emulator support mode in accordance with the present invention, the WDTCNTL and WDTCNTH registers become readable and writable, allowing an emulator to read the current count and to set it to a specific value for use in testing handling of watchdog time-outs by the microcontroller-based device. In a conventional watchdog timer, it has not been possible to read a current count. 
     The foregoing disclosure and description of the invention are illustrative and explanatory thereof, and various changes in the size, shape, materials, components, circuit elements, wiring connections and contacts, as well as in the details of the illustrated circuitry and construction and method of operation may be made without departing from the spirit of the invention.