Abstract:
A level conversion circuit includes an input section configured to receive a first signal of a first signal level and a correction signal and generates a second signal of a second signal level from the first signal and the correction signal. A level converting section converts the second signal into an output signal of a third signal level, and a duty correcting section generates the correction signal corresponding to a duty ratio of the output signal and outputs the correction signal to the input section.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a level conversion circuit, and in particular, relates to duty correction in level conversion of a clock signal. 
     2. Description of the Prior Art 
     Semiconductor integrated circuits are required to respond to a high speed operation and a multi-function. With the advancement of the semiconductor technology, a large number of circuit blocks are formed on a single chip, and optimum circuits are constituted for functions to be provided. For this reason, multiple signal levels are often present in the semiconductor integrated circuit. With the high speed operation, in particular, differential interfaces or unbalance interfaces are used for signal transmission. Since a signal of a single end type is usually used in a logic circuit section, a signal level conversion circuit is required in interface between circuit blocks. 
     Logic circuits often include synchronous circuits, and a clock signal is especially important as the reference of signal timing. Therefore, duty degradation needs to be controlled. However, the duty degradation is caused by relative variations of process level and characteristics, and has great effect on performance degradation of the synchronous circuits. Particularly, there is a possibility that the duty degradation is greater in a long clock line and so on. Therefore, it is desired to perform duty correction in a last stage and to use a clock signal with the duty ratio close to 50% in the synchronous circuits. 
     In high-speed circuits that transmission rate exceeds the order of GHz, a CML (Current Mode Logic) signals as small-amplitude differential signals with high noise tolerance, are often used in a long clock line and so on. A CML level clock signal is level-converted into a CMOS logic level signal in the last stage, and is used in synchronous circuits of a CMOS configuration in many cases. Level conversion circuits becomes complex in circuit configuration, and are easy to cause duty degradation because of the influence of the relative variations of the process level and characteristics compared with circuits for the small-amplitude differential signals. 
     A level conversion circuit for clock signals is disclosed in Japanese Laid Open Patent Application (JP-P2000-305528A), for example. The conventional level conversion circuit is provided with a level converting section  21  and a cross-point correction section  22 , as shown in  FIG. 1 . The level converting section  21  performs level conversion, converting a clock signal of a first signal level (e.g., the level of a CML signal as a small-amplitude differential signal) into a clock signal of a second signal level (e.g. the CMOS logic level). The clock signal of the second signal level is supplied to the cross-point correcting section  22  for cross-point correction. The cross-point correcting section  22  is provided with inverters  25  to  28 , and performs the cross-point correction such that the duty ratio of two-phase clock signals of the second signal level is 50 percent. 
       FIGS. 2A to 2E  show examples of signal waveforms at nodes N 1  and N 2  to which input signals of the first signal level are applied, at output nodes N 7  and N 8  of the level converting section  21 , and at output nodes N 9  and N 10  of the cross-point correction section  22 . As shown in  FIG. 2A , differential signals of sine waveforms are supplied to the input nodes N 1  and N 2 . When the characteristics of the level converting section  21  match with positive phase and reverse phase signals, the output of the level converting section  21  (the nodes N 7  and N 8 ) is a clock signal with the duty ratio of 50%, as shown in  FIG. 2B . As a result, the clock signal with the duty ratio of 50% is also outputted to the nodes N 9  and N 10  as well. 
     When the second signal level is a signal level in which variations are liable to occur in rising and falling characteristics of signals, as in case of the CMOS logic level, signals at the nodes N 7  and N 8  may have the duty ratio of (50±α)% as shown in  FIG. 2C . In this case, the duty ratio is 50% at a voltage where the signals of the nodes N 7  and N 8  intersect, and the duty correction is then performed by the cross-point correction section  22 , and signals with the duty ratio of 50% are supplied to the nodes N 9  and N 10 . 
     However, when a normal mode offset occurs to input signals as shown in  FIG. 2D , signal waveforms at the nodes N 7  and N 8  do not show the duty ratio of 50% even at cross points in many cases. In these cases, improvement of the duty ratio is not possible even when the cross-point correction is performed by the cross-point correction section  22 , where signals at the nodes N 9  and N 10  show the duty ratios of (50±β)%, as shown in  FIG. 2E . 
     The duty correction is thus possible by utilizing a reverse-phase signal, when the cause of duty degradation affects a common mode in differential signals. However, when a normal mode is affected, namely when the differential signals are imbalanced, the duty correction is not possible even by utilizing the reverse-phase signal. 
     In conjunction with the above description, Japanese Laid Open Patent Application (JP-P2001-156597A) discloses a technique to adjust a duty ratio of output of a voltage controlled oscillator circuit. A duty correcting circuit inputs a reverse output and a non-reverse output from a voltage controlled oscillator circuit. The duty correcting circuit is provided with an output adjustment section. The output adjustment section outputs output waveform signals in which a low level pulse width for a pulse period of the reverse output and a high level pulse width for a pulse period of the non-reverse output are equal. This output adjustment section is an RS flip-flop to input the reverse output and the non-reverse output of the voltage controlled oscillator circuit. 
     SUMMARY OF THE INVENTION 
     In an aspect of the present invention, a level conversion circuit includes an input section configured to receive a first signal of a first signal level and a correction signal and generates a second signal of a second signal level from the first signal and the correction signal. A level converting section converts the second signal into an output signal of a third signal level, and a duty correcting section generates the correction signal corresponding to a duty ratio of the output signal and outputs the correction signal to the input section. 
     Here, the duty correcting section may include an integrating circuit configured to measure the duty ratio of the output signal. 
     Also, the duty correcting section may include a constant current source; a current mirror circuit section configured to supply a current corresponding to a current supplied from the constant current source; and a capacitive element connected to the current mirror circuit section and configured to carry out charging and discharging operations by using the corresponding current based on the output signal. The duty ratio may be measured based on a voltage across the capacitive element. 
     In this case, the duty correcting section may generate the correction signal such that a time of the charging operation of the capacitive element is equal to that of the discharging operation of the capacitive element. 
     Also, the first signal of the first signal level may be a clock signal of a CML (Current Mode Logic) level as a small amplitude differential signal, and the output signal of the third signal level may be a differential clock signal of a CMOS logical level. 
     Also, the level converting section may include a cross-point correcting circuit configured to correct a cross-point of the output signal to a threshold of the CMOS logical level. 
     Also, the cross-point correcting circuit may include a pair of CMOS inverters connected in parallel in opposing directions, the level converting section has two output terminals, and the parallel connection of the CMOS inverters is connected between the two output terminals. 
     Also, the duty correcting section may include a constant current source; a current mirror circuit section configured to supply a current corresponding to a current supplied from the constant current source; and a capacitive element connected to the current mirror circuit section and configured to carry out charging and discharging operations by using the corresponding current based on the output signal. The duty ratio may be measured based on a voltage across the capacitive element. 
     Also, the duty correcting section may generate the correction signal such that a time of the charging operation of the capacitive element is equal to that of the discharging operation of the capacitive element. 
     Also, the input section may include an input section differential transistor pair, and the duty correcting section may include a correcting section differential transistor pair connected in parallel with the input section differential transistor pair. The second input signal may be generated through current addition of a drain current of the input section differential transistor pair and a drain current of the correcting section differential transistor pair. 
     Also, in another aspect of the present invention, a method of converting a signal level of a signal may be achieved by amplifying a first signal of a first signal level; by calculating an addition of the amplification result and a correction amount to generates a second signal of a second signal level; by converting the second signal into an output signal of a third signal level; and by feeding back the correction amount corresponding to a duty ratio of the output signal. 
     Here, the feeding back may be achieved by supplying a constant current; by supplying a current corresponding to the constant current; by carrying out charging and discharging operations of a capacitive element by using the corresponding current based on the output signal, and by determining the duty ratio based on a voltage across the capacitive element. 
     Also, the feeding back may be achieved by determining the correction amount such that a time of the charging operation of the capacitive element is equal to that of the discharging operation of the capacitive element. 
     Also, the first signal of the first signal level may be a clock signal of a CML (Current Mode Logic) level as a small amplitude differential signal, and the output signal of the third signal level may be a differential clock signal of a CMOS logical level. 
     Also, the converting may be achieved by correcting a cross-point of the output signal to a threshold of the CMOS logical level. 
     Also, the correcting may be achieved by a pair of CMOS inverters connected in parallel in opposing directions. 
     Also, the feeding back may be achieved by supplying a constant current; by supplying a current corresponding to the constant current; by carrying out charging and discharging operations of a capacitive element by using the corresponding current based on the output signal; and by determining the duty ratio based on a voltage across the capacitive element. 
     Also, the feeding back may be achieved by determining the correction amount such that a time of the charging operation of the capacitive element is equal to that of the discharging operation of the capacitive element. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram showing a configuration of a conventional level conversion circuit; 
         FIGS. 2A to 2E  are timing charts showing signal waveforms at each section in the conventional level conversion circuit; 
         FIG. 3  is a block diagram showing the configuration of a level conversion circuit according to an embodiment of the present invention; 
         FIG. 4  is a circuit diagram showing the configuration of a differential buffer section according to the embodiment of the present invention; 
         FIG. 5  is a circuit diagram showing the configuration of a level converting section according to the embodiment of the present invention; 
         FIG. 6  is a circuit diagram showing the configuration of a duty correcting section according to the embodiment of the present invention; 
         FIGS. 7A to 7D  are timing charts showing of signal waveforms at each section in the level conversion circuit according to the embodiment of the present invention; and 
         FIGS. 8A to 8F  are timing charts showing a duty measuring operation in the duty correcting section according to the embodiment of the present invention. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Hereinafter, a level conversion circuit of the present invention will be described in detail with reference to the attached drawings. In the following description, the level conversion circuit carries out level conversion of an input clock signal of a CML level as a small amplitude differential signal into a clock signal of a CMOS logic level. 
       FIG. 3  is a block diagram showing a configuration of a level conversion circuit according to an embodiment of the present invention. The level conversion circuit  10  is provided with a CML differential buffer section  11 , a level converting section  12 , and a duty correcting section  13 . The CML differential buffer section  11  as an input section has input signals of the CML level applied to nodes N 1  and N 2 . Output signals of the CML differential buffer section  11  and those of the duty correcting section  13  are supplied to nodes N 3  and N 4  and are subjected to current addition therein, and the current addition resultant signals are outputted to the level converting section  12 . The level converting section  12  outputs signals converted to have the CMOS logic level to nodes N 5  and N 6 . The signals outputted to the nodes N 5  and N 6  are then supplied to the duty correcting section  13 , and are also supplied to a circuit in the next stage as the output of the level conversion circuit  10 . In other words, the duty correcting section  13  is provided in a feedback loop to a differential signal line where the CML differential buffer section  11  and the level converting section  12  are cascade-connected, and the feedback loop is provided from the output of the level converting section  12  to the input thereof. 
       FIG. 4  is a circuit diagram showing the CML differential buffer section  11 . Referring to  FIG. 4 , the CML differential buffer section  11  is a basic differential buffer which is provided with N-channel MOS transistors MN 1  and MN 2  for a differential transistor pair, resistors R 1  and R 2 , and a constant current source I 1 . The constant current source I 1  is connected to common sources of the N-channel MOS transistors MN 1  and MN 2 , and the resistors R 1  and R 2  having the same resistance are connected to drains of these transistors as loads. The other ends of the resistors R 1  and R 2  are connected to a power supply VDD. Connection nodes N 3  and N 4  between the resistor R 2  and the N-channel MOS transistor MN 2  and between the resistor R 1  and the N-channel MOS transistor MN 1  respectively, serve as output nodes of the CML differential buffer section  11 . 
     Input differential signals of the CML level are applied to the nodes N 1  and N 2 , and amplified signals are outputted from the nodes N 3  and N 4 . Additionally, N-channel MOS transistors MN 22  and MN 21  to be described later are connected to the nodes N 3  and N 4  in parallel with the N-channel MOS transistors MN 1  and MN 2 . Therefore, the currents flowing through the resistors R 1  and R 2  are additions of the currents flowing through the N-channel MOS transistors MN 1  and MN 2  and the currents flowing through the N-channel MOS transistors MN 22  and MN 21 , respectively. That is, by voltage drops caused by the currents flowing through the N-channel MOS transistors MN 22  and MN 21 , voltages in the nodes N 3  and N 4  are lower than voltage lower from the power supply voltage (VDD) by voltages generated in response to the input differential signals. Consequently, the voltage in the nodes N 3  and N 4  are controlled by the duty correcting section  13 . 
       FIG. 5  is a circuit diagram showing the level converting section  12 . Referring to  FIG. 5 , the level converting section  12  is provided with N-channel MOS transistors MN 23  to MN 28 , P-channel MOS transistors MP 14  to MP 19 , a constant current source I 4 , and inverters  16  and  17  for a cross-point correcting section  15 . Here, an operation of the level converting section  12  will be described under the assumption that the N-channel MOS transistors MN 23  and MN 24 , the N-channel MOS transistors MN 25  to MN 28 , and the P-channel MOS transistors MP 14  to MP  19  have the same size. When the sizes of transistors are compared in the following description, the transistors have the same gate length L and have different gate widths. 
     The N-channel MOS transistors MN 23  and MN 24  form a differential transistor pair and their gates are connected to the nodes N 3  and N 4  respectively. Common sources of the N-channel MOS transistors MN 23  and MN 24  are connected to a ground through a constant current source I 4 . The P-channel MOS transistor  14  is connected as a load between a drain of the N-channel MOS transistor MN 23  and a power supply VDD. Common sources of the P-channel MOS transistors MP 14 , MP 15 , and MP 16  are connected to the power supply VDD, and respective gates of the P-channel MOS transistors MP 14 , MP 15 , and MP 16  are connected to a drain of the P-channel MOS transistors MP 14 , to form current mirror circuits. Drain currents flowing through the P-channel MOS transistors MP 15  and MP 16  are equal to a drain current flowing through the P-channel MOS transistor MP 14 . The N-channel MOS transistor MN 27  is connected between the drain of the P-channel MOS transistor MP 15  and the ground. Common sources of the N-channel MOS transistors MN 27  and MN 28  are connected to the ground and respective gates of the N-channel MOS transistors MN 27  and MN 28  are connected to a drain of the N-channel MOS transistor MN 27 , to form a current mirror circuit. A drain current flowing through the N-channel MOS transistor MN 28  is equal to a drain current through the N-channel MOS transistor MN 27 . 
     The P-channel MOS transistor MP 17  is connected as a load between a drain of the N-channel MOS transistor MN 24  and the power supply VDD. Common sources of the P-channel MOS transistors MP 17 , MP 18 , and MP 19  are connected to the power supply VDD and respective gates of the P-channel MOS transistors MP 17 , MP 18 , and MP 19  are connected to a drain of the P-channel MOS transistor MP 17 , to form current mirror circuits. Drain currents flowing through the P-channel MOS transistors MP 18  and MP 19  are equal to a drain current flowing through the P-channel MOS transistor MP 17 . The N-channel MOS transistor MN 25  is connected between a drain of the P-channel MOS transistor MP 18  and the ground. Common sources of the N-channel MOS transistors MN 25  and MN 26  are connected to the ground and respective gates of the N-channel MOS transistors MN 25  and MN 26  are connected to a drain of the N-channel MOS transistor MN 25 , to form a current mirror circuit. A drain current flowing through the N-channel MOS transistor MN 26  is equal to a drain current flowing through the N-channel MOS transistor MN 25 . 
     With the above differential transistors pair and current mirror circuits, a CMOS circuit as load capacitance connected to nodes N 5  and N 6  is charged up to a VDD level or discharged down to a ground level with a current corresponding to a voltage difference between differential signals applied to the nodes N 3  and N 4 . Therefore, input differential signals of the CML level are converted into differential signals of the CMOS logic level. 
     Further, the cross-point correcting circuit  15  is connected between the nodes N 5  and N 6  and an input of the CMOS inverter  16  and an output of the CMOS inverter  17 , and an output of the CMOS inverter  16  and an input of the CMOS inverter  17  are connected. When a cross point of the differential signals of the CMOS logic level outputted to the nodes N 5  and N 6  deviates from a threshold (Vth) of the CMOS logic level (see  FIG. 2C ), the cross-point correcting circuit  15  corrects the cross point approximately to the threshold value (Vth) of the CMOS logic level (see  FIG. 2B ). As a result, improvement in duty correction performance is expected. The configuration of the level converting section  12  is not limited to the above configuration. 
       FIG. 6  is a circuit diagram showing the duty correcting section  13 . Referring to  FIG. 6 , the duty correcting section  13  is provided with N-channel MOS transistors MN 11 , MN 12 , MN 17  to MN 19 , MN 21 , and MN 22 , P-channel MOS transistors MP 11  to MP 13 , capacitive elements C 1  and C 2 , and constant current sources I 2  and I 3 . The N-channel MOS transistors MN 11  and MN 12  form a differential transistor pair, and their gates are connected to nodes N 5  and N 6 , respectively. Common sources of the N-channel MOS transistors MN 11  and MN 12  are connected to a drain of the N-channel MOS transistor MN 19 . Drains of the N-channel MOS transistors MN 11  and MN 12  are connected to nodes Nc 1  and Nc 2 , respectively. One end of the capacitive element C 1  and a gate of the N-channel MOS transistor MN 21  are connected to the node Nc 1 . In the same way, one end of the capacitive element C 2  and a gate of the N-channel MOS transistor MN 22  are connected to the node Nc 2 . The other respective ends of the capacitive elements C 1  and C 2  are connected to the ground. A source of the N-channel MOS transistor MN 19  is connected to the ground. 
     The N-channel MOS transistors MN 17 , MN 18 , and MN 19  form current mirror circuits and their gates are connected to a drain of the N-channel MOS transistor MN 17 . The constant current source I 2  is connected between the drain of the N-channel MOS transistor MN 17  and the power supply VDD, to supply a drain current of the N-channel MOS transistor MN 17 . Sources of the N-channel MOS transistors MN 17  and MN 18  are connected to the ground. 
     The P-channel MOS transistor MP 13  is connected between a drain of the N-channel MOS transistor MN 18  and the power supply VDD. Common sources of the P-channel MOS transistors MP 13 , MP 12 , and MP 11  are connected to the power supply VDD and respective gates of the P-channel MOS transistors MP 13 , MP 12 , and MP 11  are connected to a drain of the P-channel MOS transistor MP 13 , to form current mirror circuits. The size of the P-channel MOS transistor MP 13  is two times as large as the sizes of the P-channel MOS transistors MP 12  and MP 11 . A drain current flowing through the N-channel MOS transistor MN 18  is equal to a value of current supplied by the constant current source I 2 . Therefore, the P-channel MOS transistors MP 12  and MP 11  function as constant current sources, each of which supplies a half current of the current supplied by the constant current source I 2 . Drain currents through the P-channel MOS transistors MP 11  and MP 12  flow through the N-channel MOS transistors MN 11  and MN 12 , when the N-channel MOS transistors MN 11  and MN 12  are in the ON state. On the other hand, when the N-channel MOS transistors MN 11  and MN 12  are in the OFF state, the drain currents flowing through the P-channel MOS transistors MP 11  and MP 12  flow through the capacitive elements C 1  and C 2  to charge the capacitive elements C 1  and C 2 . 
     Since the capacitive element C 1  and the gate of the N-channel MOS transistor MN 21 , and the capacitive element C 2  and the gate of the N-channel MOS transistor MN 22 , are connected to the nodes Nc 1  and Nc 2 , respectively, drain currents flowing through the N-channel MOS transistors MN 21  and MN 22  are controlled in accordance with voltages at which the capacitive elements C 1  and C 2  are charged and discharged. The constant current source I 3  is connected between the ground and common sources of the N-channel MOS transistors MN 21  and MN 22  of a differential transistor pair. Drains of the N-channel MOS transistors MN 21  and MN 22  are connected to nodes N 4  and N 3  respectively. That is, the N-channel MOS transistors MN 21  and MN 22  are connected in parallel with the differential transistor pair (MN 1  and MN 2 ) of the CML differential buffer section  11 , where drain currents are added. 
     When the N-channel MOS transistors MN 11  and MN 12  are in the OFF state, the capacitive elements C 1  and C 2  are charged with the drain currents of the P-channel MOS transistors MP 11  and MP 12  to increase the voltages at the nodes Nc 1  and Nc 2 . When the N-channel MOS transistors MN 11  and MN 12  are turned ON, discharge current flows out from the capacitive elements C 1  and C 2  through the N-channel MOS transistors MN 11  and MN 12  in the ON state, to lower the voltages at the nodes Nc 1  and Nc 2 . Charge currents are supplied by the current mirror circuit which includes the P-channel MOS transistors MP 11  to MP 13 , while being kept constant. On the other hand, discharge currents are supplied by the current mirror circuit which includes the N-channel MOS transistors MN 17  to MN 19 , while being kept constant. The drain current flowing through the N-channel MOS transistor MN 19  is the same as the current supplied by the constant current source I 2 . At the same time, discharge currents of the capacitive elements C 1  and C 2  are equal to the drain currents of the P-channel MOS transistors MP 11  and MP 12 , respectively, being the half of the current supplied by the constant current source I 2 . Therefore, the voltages at the nodes Nc 1  and Nc 2  are increased and decreased in correspondence to charge and discharge time. 
     Description is given on operation of the level conversion circuit  10  with reference to  FIGS. 7A to 7D . Signals are applied to the input nodes N 3  and N 4  of the level converting section  12 . As shown in  FIG. 7A , offsets occur to the plus side and minus side in case of the nodes N 3  and N 4  due to relative variations of element characteristics and so on, respectively. If being processed only by the level converting section  12 , the above signals become signals with deteriorated a duty as mentioned above. The duty ratio is (50±β)%, as shown in  FIG. 7B . More specifically, a signal of the CMOS logic level appears at the node N 5  in such a manner that the duty is (50+β)% in a high level period and the duty is (50−β)% in a low level period. On the other hand, a signal of the CMOS logic level appears at the node N 6  in such a manner that the duty is (50−β)% in the high level period and the duty is (50+β)% in the low level period. 
     In the duty correcting section  13 , the N-channel MOS transistors MN 11  and MN 12  are in the ON state when the nodes N 5  and N 6  take the high level, and the OFF state when the nodes N 5  and N 6  take the low level, respectively. Therefore, the N-channel MOS transistor MN 11  takes the ON state during the duty period of the (50+β)% in one cycle and the OFF state during the duty period of (50−β)%, as shown in  FIG. 8A . In other words, the capacitive elements C 1  is discharged during a period Tdsc when the N-channel MOS transistor MN 11  takes the ON state, and charged during a period Tchg when the N-channel MOS transistor MN 11  takes the OFF state. Since the discharge period Tdsc is longer than the charge period Tchg, the voltage at the node Nc 1  is gradually decreased as the capacitive element C 1  is repeatedly charged and discharged, as shown in  FIG. 8B . 
     On the other hand, the N-channel MOS transistor MN 12  takes the ON state during the duty period of (50−β)% in one cycle and the OFF state during the duty period of (50+β)%, as shown in  FIG. 8E . That is, the capacitive element C 2  is discharged during a period Tdsc when the N-channel MOS transistor MN 12  takes the ON state, and charged during a period Tchg when the N-channel MOS transistor MN 12  takes the OFF state. Since the discharge period Tdsc is shorter than the charge period Tchg, the voltage at the node Nc 2  is gradually increased as the capacitive element C 2  is repeatedly charged and discharged, as shown in  FIG. 8F . 
     With the decrease and increase in the voltages at the nodes Nc 1  and Nc 2 , drain currents through the N-channel MOS transistors MN 21  and MN 22  are decreased and increased. Since the drains of the N-channel MOS transistors MN 21  and MN 22  are connected to the nodes N 4  and N 3 , respectively, the drain currents flow through the resistors R 1  and R 2  of the CML differential buffer section  11 . When the current flowing through the node N 3  is increased, the voltage at the node N 3  is decreased. On the other hand, when current flowing through the node N 4  is decreased, the voltage at the node N 4  is increased. However, the voltage at the node N 4  is lower than the original voltage at the node N 4 , since the N-channel MOS transistor MN 21  is provided and the drain current flows. In other words, as shown in  FIG. 7C , a decrease in the voltage at the node N 3  for an original input signal N 3 ′ is larger than a decrease in the voltage at the node N 4  for an original input signal N 4 ′. 
     As stated above, as the gate voltages at the N-channel MOS transistors MN 21  and MN 22  are controlled, the high level period of the node N 3  becomes shorter and the high level period of the node N 4  becomes longer. When the duty ratio is 50%, the charge period Tchg and the discharge period Tdsc are equal as shown in  FIG. 8C . In other words, the voltages at the nodes Nc 1  and Nc 2  are balanced in a certain range, as shown in  FIG. 8D . The range of the voltage change can be set based on the capacitance values of the capacitive elements C 1  and C 2  and charge and discharge current values (current value of the constant current source I 2  in this example). Therefore, output signals at the nodes N 5  and N 6  are signals of the CMOS logic level with the duty ratio 50%, as shown in  FIG. 7D . 
     As mentioned above, it is possible to automatically correct the duty ratio of differential output signals of the CMOS logic level to 50% without an increase in delay time of level conversion, when the duty of clock signals of the CML level as small-amplitude differential input signals of the nodes N 1  and N 2  are degraded and when the duty is degraded in the CML differential buffer section and the level converting section. 
     In the embodiments, circuits shown in  FIGS. 4 ,  5 , and  6  are exemplified as the CML differential buffer section  11 , the level converting section  12 , and the duty correcting section  13  respectively. However, the CML differential buffer section  11 , the level converting section  12 , and the duty correcting section  13  are not limited to the above circuits. 
     According to the present invention, it is possible to provide a level conversion circuit capable of correcting a duty ratio to 50% even when the cause of duty degradation affects the common mode and normal mode. 
     Also, according to the present invention, it is also possible to provide a level conversion circuit for performing duty correction without an increase in delay time in the level conversion circuit.