Abstract:
The invention relates to a compensation circuit ( 1–6 ) to compensate nonlinear distortions of an A/D converter comprising a signal input and a compensation system. In order to avoid the high costs related to the complex analog design of the A/D converter and/or the high energy consumption in this converter and compensation system, it is proposed that a compensation circuit be used that is composed of digital circuit elements that are connected following the A/D converter and which has a nonlinearly distorted output signal of the A/D converter supplied to it to compensate the nonlinear distortion. Adaptive coefficients are preferably employed here for the compensation.

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to the field of analog-to-digital signal conversion, and in particular to a compensation circuit to compensate nonlinear distortions of an analog-to-digital (A/D) converter. 
     A/D converters are a critical component in integrated circuits having mixed signal processing (i.e., analog and digital signal processing). Requirements related to the linearity of the A/D converter are quite difficult to achieve given the usual tolerances for analog components. The measures required for this purpose in the area of analog design entail high cost and/or high current consumption by the circuit. 
     In order to prevent nonlinear distortions in the analog-to-digital conversion process of the A/D converter, compensation circuits are employed to compensate for these nonlinear distortions of the A/D converter. The compensation circuits have an analog signal input, and are typically located on the input side of the A/D converter. 
     There is a need for a compensation circuit that compensates for nonlinear distortions of an A/D converter, and requires a simplified overall analog design together with, preferably, reduced current consumption. 
     SUMMARY OF THE INVENTION 
     A compensation circuit to compensate for nonlinear distortions of an A/D converter may include a signal input and a compensation circuit composed of digital circuit elements to digitally compensate for the nonlinear distortions, the signal input as the compensation input being a digital signal input to supply a signal outputted in distorted form by the A/D converter. Implementation is thus in the form of an output-side digital compensation or distortion correction of the nonlinear distortions from an input-side A/D converter. The digital circuit elements required for this purpose are inexpensive and readily available based on a simple digital circuit design. Advantageously, it is no longer necessary to incur high costs or have increased current consumption based on a compensation circuit added on the input-side of, or integrated into, the A/D converter. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram illustration of a compensation circuit to compensate for nonlinear distortions of an A/D converter; 
         FIG. 2  is a block diagram illustration of a circuit to determine a test signal; 
         FIG. 3  is a block diagram illustration of a circuit for the iterative calculation of correction coefficients; and 
         FIG. 4  is a block diagram illustration of an alternative circuit for the iterative calculation of correction coefficients using a look-up table. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 1  is a block diagram illustration of a compensation circuit to compensate for nonlinear distortions of an A/D converter. The compensation circuit in the example is composed of an analog section, shown at left, and a digital section shown on the right. An analog input signal x(t) is supplied to an A/D converter (ADC)  1 , which provides a digital sequence x n  corresponding to the analog input signal x(t). When a conventional ADC  1  is used, the digital sequence x n  from this converter exhibits nonlinear distortion. The index n represents the sequence of sampling values x n , n=0, 1, 2, . . . . 
     The A/D-converted sequence x n  is input of a compensation circuit  2 , which compensates or corrects the nonlinear distortion created by the ADC  1 . The compensation circuit  2  provides compensated digital data y n . 
     The compensation circuit  2  receives coefficients c 1 , c 2 , . . . c K , c 0  that have been determined or calculated based on the nonlinear distortion response of the ADC  1 . The index k=1, 2, . . . , K here functions as the consecutive index for the coefficients c k  of compensation. 
     The circuit of this design includes an ADC  1  together with the compensation circuit  2  to which a set of coefficients c 1 , . . . c K  is supplied offers a simple design which enables an analog-to-digital conversion of an analog signal x(t) to form a sequence of compensated digital data y n  which does not suffer from nonlinear distortion. 
     A coefficient computation unit  100  determines the coefficients c 1 , . . . c K . These additional components are advantageously active only during a configuration phase. As an alternative to the circuit described below, it is also possible to employ a memory in which a set of coefficients c 1 , . . . c K , determined previously only once, is stored which may be applied generally for the compensation. However, the preferred approach is the circuit design described below which provides an adjustment of the coefficients c 1 , . . . c K  to the actual and/or instantaneous conditions. 
     Referring to  FIG. 1 , a test signal s(t) is generated by a test signal generator  3  and applied during the configuration phase to the input of the ADC converter  1 . The test signal generator  3  also provides either the parameters s n  to generate the analog test signal s(t) or a sequence of digital test signal data S n  corresponding to this analog test signal s(t). These parameters s n  or test signal data S n  are fed to a coefficient determination system  5  and/or to a test signal check device  4 . 
     The coefficient determination system  5  determines the coefficients c 1 , . . . c K  to be used by the compensation circuit  2 . The coefficient determination system  5  receives the digital data x n  from the ADC  1 . The coefficient determination system  5  also receives distortion data or difference data D n  on a line  102 . The difference data D n  are provided by a subtracter  6  to which the sequence of the compensated digital data y n  is fed from the output of the compensation circuit  2 . The subtracter  6  also receives a sequence of digital signal data S n  either directly or indirectly through the test signal check device  4 . The sequence of digital signal data S n  corresponds in the configuration phase to a signal map of the test signal, whereby, after appropriate determination of coefficients has been effected, this signal map is as undistorted as possible, or ideally is completely undistorted. 
     During the configuration phase, the analog test signal s(t) is generated and fed to the ADC  1 , which provides the sequence of digital data x n  to the compensation circuit  2  and the coefficient determination circuit  5 . If the set of coefficients c 1 , . . . c K  is not available, the compensation circuit  2  outputs the sequence of digital data x n  as the sequence of compensated digital data y n (i.e., y n =x n ). This data is fed to the subtracter  6 , which is also supplied with a corresponding sequence of digital test signal data S n  matching an undistorted data set. After subtraction of the two sequences of data (y n −S n ), the data sequence of the difference signal D n  on a line  102  is supplied to the coefficient determination system  5 . According to a preferred embodiment, a test signal s(t) is subsequently sent by the test signal generator  3 , which may also be composed of a memory with an analog test signal s(t) and a corresponding digital parameter set s n , to the ADC  1 . The sequence of digital data x n  generated by the ADC  1  is subsequently compensated by the compensation circuit  2  in accordance with this supplied set of coefficients c 1 , . . . c K , such that the sequence of compensated digital data y n  is output, ideally with already optimized coefficients c 1 , . . . c K , without nonlinear distortion. The sequence of compensated digital data y n  is in turn fed to the subtracter  6  in which, after subtraction using the corresponding values of the sequence of digital test signal data S n , the sequence of data D n  of the difference signal is again generated. This difference data D n  is again fed to the coefficient determination system  5  which, in the event the difference data D n  does not equal zero or exceeds predetermined threshold values, implements another, or preferably, an iteratively improved determination of coefficients to provide improved coefficients c 1 , . . . c K . 
     After a sufficiently distortion-corrected or compensated set of coefficients c 1 , . . . c K  has been determined, the configuration phase ends, after which the circuit composed of the ADC  1  and the compensation circuit  2  implements a conversion and compensation of the analog signal x(t) to form a sequence of compensated digital data y n . 
     A configuration phase is initiated at regular intervals to check the set of coefficients used, c 1 , . . . c K  in terms of their current validity. In this way drifting nonlinear distortions caused for example by the circuit heating up or other interfering effects from the environment can be compensated. 
     The configuration phase is turned on and off as needed so that any slow changes in nonlinear distortions can be detected early enough and then compensated. It is, of course, in principle also possible to implement a predetermination and consideration of anticipated additional degradations or improvements related to the generation of distortions. 
     A control device  104  is advantageously employed to control the compensation circuit, the control device  104  being connected to a time-monitoring device, specifically, a timer  106 . In addition to turning the configuration phase on and off, the control device  104  also controls the individual components through, for example, a bus  7 . 
     In particular, it is possible to provide different types of test signals s(t), S n  for different application areas of the circuit so that coefficients c 1 , . . . c K  may, for example, be optimally adjusted for a low-frequency or high-frequency analog signal x(t). 
     The following discussion examines in more detail the circuit components and the operational sequences of the method with reference to the mathematical background. 
     The configuration phase starts with an analog test signal s(t), 
     to which the theoretical uncorrupted sampling values 
                 S   n     =     s   ⁡     (     n   Fs     )         ,         
correspond after analog-to-digital conversion, without nonlinear distortion, which values are in turn to be output after optimal compensation from the compensation circuit  2  as the sequence of compensated digital data y n . Here n is a consecutive index of the set of natural numbers, while F s  is the sampling frequency of the ADC  1 .
 
     After analog-to-digital conversion has been performed on the analog test signal s(t) the sequence of digital data x n  is supplied to its output based according to the expression
 
 x   n   =s   n   +d   n .
 
The sequence of digital data x n  thus corresponds to the summation of correct theoretical and uncorrupted sampling values s n , and the respective distortion data value d n  which matches the corresponding distortion by the A/D converter  1 .
 
     The digital compensation circuit  2  which uses the coefficients c 1 , . . . C K  to generate the sequence of compensated digital signals y n  that are ultimately to be output must therefore perform a compensation having the characteristic that may be described by a K th -order polynomial: 
                     y   n     =         ∑     k   =   l     K     ⁢       c   k     ·     x   n   k         =         v   ·     s   n       +     D   n       =       S   n     +       D   n     .                   (   1   )               
Here the coefficient values c k  with k=1, 2, . . . K are adaptive coefficients, that is, coefficients which may be adjusted as necessary. The output signal, or sequence of outputted compensated digital data y n  contains a map of the test signal or of the sequence of the digital test signal data S n  plus a possible change ν, specifically, amplification or attenuation. The sequence of the compensated digital data S n  is thus the product of a distortion factor ν and the sequence of the digital test signal data S n  which may be described by
   S   n   =v·s   n , 
where the effective distortions of the switching sequence of the ADC  1  and, in the event of insufficient compensation, of the compensation circuit  2  may be described by the sequence of difference data D n  according to the expression
   D   n   =y   n   −S   n .  (2) 
     Since the parameters s n  of the test signal are known, the sequence of output signal data S n  may be extracted from the sequence of the compensated digital data y n  by the test signal check device  4  to enable the actual distortion data or difference data D n  in data y n  to be calculated at the output of the compensation circuit  2 . In addition, the gradients of the rms distortion may be calculated using the expression 
                 ∂     D   n   2         ∂     c   k         =       2   ·     (       y   n     -     S   n       )     ·     x   n   k       =     2   ·     D   n     ·       x   n   k     .               
The use of an iterative method allows the set of coefficients c k  to converge. To this end, the formulation
   c   k   n+1   =c   k   n   −G·D   n   ·x   n   k   (3) 
may be selected so as ultimately to minimize the rms distortion or output. A parameter G is introduced in equation (3) as a stability criterion, which parameter at the same time provides for the highest possible convergence rate. The term c k   n  describes the value of the coefficients c k  in the n th  iteration step, the coefficient of compensation c k  again having the consecutive index k=1, . . . , K. The iteration steps are preferably counted from the value zero, so that n=0, 1, . . . .
 
     In an especially preferred embodiment, a sinusoidal test signal s(t)=sin[2πt] is preferably used as the test signal to perform the nonlinear compensation since it is then simpler for the A/D converter  1  to determine the structure of the distortions, and is possibly simpler for the compensation circuit  2  to determine additional distortions. A nonlinearly distorting ADC  1  having a sinusoidal input signal at a frequency F t  produces harmonics on frequencies p·F t , which may be folded back by sampling to form 
               f   k     =     {               (     p   ·     F   t       )       mod   ⁢           ⁢   Fs                 (     p   ·     F   t       )         mod   ⁢           ⁢   Fs     ⁢           ≤       ⁢           ⁢       F   s     2                   F   s     -       (     p   ·     F   t       )       mod   ⁢           ⁢   Fs                   (     p   ·     F   t       )         mod   ⁢           ⁢   Fs     ⁢           ≥       ⁢           ⁢       F   s     2             .             
Here p=2, 3, . . . , M is the consecutive index of the frequency calculation.
 
     If the first harmonics are significant, specifically, if p=2, . . . , M applies, the test frequency F t  should be selected such that the frequency band 2B is maximized around the fundamental where none of the first M harmonics fold back according to the expression 
     
       
         
           
             
               
                 
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     The extraction of the test signal or sequence of the output signal data S n  may be implemented using a known method of carrier processing. Another factor which must be taken into account is that the test signal s(t) or the sequence of the output signal data S n  assigned to this signal are amplitude-conforming. 
     To this end, a circuit may be used that is based on an I/Q demodulator (I: in-phase, Q: quadrature phase) and a Cordic circuit  43 , and calculates the phase and amplitude of the input sequence of the digital data y n .  FIG. 2  provides an example of this circuit. 
     Frequency, amplitude and direct current (DC) are recovered by feedback using the method known from automatic control engineering. A proportional and integral (PI) control is employed to determine the frequency. To determine amplitude and direct current, a PI-control is used in which only the proportional components are employed. The control parameters used are the P-component of the amplitude control C a , the P-component for the DC components C dc , and the P-component and I-component of the frequency control C p  or C i , which components are intended at the same time to meet the stability criterion for a control loop and to ensure the fastest possible transient. 
     The supplied sequence of the digital data y n  is input to multipliers  41   a ,  41   b . A sinusoidal signal sin[2πt] as the signal sequence to be multiplied is fed to the first of the multipliers  41   a  by a sinusoidal tone generator  41 . Analogously, a cosine signal sequence cos[2πt] is supplied by the sinusoidal tone generator to the second multiplier  41   b . After multiplication, the two data sequences are each fed to an associated filter  42   a ,  42   b , respectively, with undersampling P. After filtering, the I-separated and Q-separated signal components are supplied to a Cordic circuit  43  which determines, a corresponding amplitude and corresponding phase that are supplied through two outputs. 
     The sequence representing the amplitude is input to a subtractor  44   a , which also receives a feedback signal on a line  202 . The subtractor  44   a  provides a difference signal to multiplier  44   b , which multiplies the difference signal by a coefficient value C a , and the resultant product is output to a summer  44   c . The summer  44   c  sums the product with the past value. The summer  44   c  provides a signal sequence to a delay element  44   d , which provides an output signal to a multiplier  44   e . The multiplier  44   e  also receives a cosine signal cos[2πt] and provides the resultant product on a line  204 . This system is ultimately used to determine the sequence of the output signal data S n  that is then supplied to the difference-forming subtracter  6 , which in turn has the sequence of the digital data y n  applied to it through the second input. 
     The Cordic circuit  43  also outputs a corresponding phase or sequence of phase data on a line  206 . This data is also fed to a circuit composed of a plurality of components  45 . In the embodiment shown, this circuit is composed of two parallel multipliers  45   b ,  45   a  to which additionally a coefficient value C p  or a coefficient value C i  is supplied. The output signal of the multiplier  45   a  is fed to an adder  45   c , the output signal of which is supplied both to an inverter (z −1 )  45   d  and to a second adder  45   e . The output signal of the inverter  45   d  is fed to the second input of the adder  45   c . Through another input, the second adder  45   e  receives data from the multiplier  45   b  in which coefficient value C p  is up-multiplied for the phase data. The output data from this adder  45   e  are fed on line  208  to another adder  45   f  which has two additional inputs. A frequency ratio F t /F s  including the test frequency F t  of the ADC  1  and the sampling frequency is supplied through the first additional input. An output value of the delay (z −1 )  45   g  connected after the adder  45   f  is fed through the second input. Output values of this delay  45   g  are supplied as the timing variable t to an input of the sinusoidal tone generator  41 . 
     In addition, a DC component DC n  is filtered out and extracted from the sequence of digital compensated data y n  outputted from the compensation circuit  2 . To this end, the digital compensated data y n  are supplied to a circuit  46  composed of a subtracter  46   a , a multiplier  46   b , a adder  46   c , and delay (z −1 )  46   d . A control parameter C dc  is applied through the second input to the multiplier  46   b . The control parameter C dc  determines the rate of the transient. The output data sequence from the delay  46   d  is supplied to the inputs of the subtracter  46   a  and the adder  46   c , as well as to the subtracter  6  generating the difference data D n . 
     Referring to  FIG. 2 , the frequency F t  is thus derived using a phase-locked loop (PLL). The input signal corresponding to the sequence of compensated digital data y n  is split into I-component and Q-component that are then filtered by the low-pass filters  42   a  and  b  of critical frequency B and undersampled. From the filtered I-component and Q-component, the Cordic circuit  43  then computes the amplitude and phase between input signal y n  and the locally generated sinusoidal tone from the sinusoidal tone generator  41 . The phase is passed to the PI control as the error signal. After a settling time, the sinusoidal tone generator  41  generates in its cosine branch a signal synchronized with the test tone. The coefficients C p  and C i , and test frequency F t  as the known parameters determine the PI control. The amplitude is derived iteratively from the amplitude output of the Cordic circuit  43  using the control parameter C a . The DC components are filtered and extracted from the output signal using the control parameter C dc . The complete circuit composed of the test signal check device  4  ( FIG. 1 ) and following the subtracter  6  ( FIG. 1 ) finally generates a sequence of difference data D n  according to equation (3) proportional to the nonlinear distortions. 
     Advantageously, available carrier-processing systems and carrier-processing methods may be utilized for the purpose of implementing this circuit. What must be added are the circuits for the amplitude and DC components. 
     An especially preferred embodiment of the compensation circuit  2  is constructed segment-by-segment, as shown in  FIG. 3 . 
     The data sequence x n  outputted by the ADC  1  is input to the compensation circuit  2  to a parallel system of multipliers  21 . At the same time, the same input signal, i.e., once again the corresponding data value of the data sequence x n , is fed to the second input of first multiplier  21   2  so that a squaring is effected. The output of this first multiplier  21   2  is supplied to the input of the second multiplier  21   3 , and so on, such that at each subsequent stage the exponent is increased by the value one up to a value x n   K . 
     As a result, an exponentiation is effected, where each exponentiation step has an output so that values for digital data with exponentiations x n   1 , x n   2 , . . . , x n   K  are output from the input and the field of the multipliers  21 . These are then fed to another field of multipliers  22 , whereby a multiplication is performed with one each of the corresponding coefficients c k (m) where k=1, 2, . . . , K. What is described is thus a multi-element system with the coefficients c k (m) of the compensation in the m th  segment with m=0, 1, 2, . . . , N−1 as the m th  segment of the amplitude range. Accordingly, the nonexponentiated value or nonexponentiated data sequence x n   1  as well as the coefficient c 1 (m) are entered in the first multiplier  22   1  of the second multiplication field  22 . The once exponentiated data value x n   2  and the second coefficient c 2 (m) are entered in the second multiplier  22   2 , etc. The output values of the multipliers  22   1 ,  22   2 , . . . ,  22   K  of second multiplication field  22  are fed to an adder  23  which performs an addition of all input values, and also of the zero th  coefficient c 0 (m), then outputs the sequence of compensated digital data y n . 
     The sequence of digital data x n  output by the ADC  1  is also fed to the coefficient determination system  5 , where a rounding operation is performed in an index determination device  51 , taking into account the N segments during the determination of the index m. Here the sequence of the digital data x n  with its respective value increased by one is divided by two, then multiplied by the number of segments N. The thus generated segment index m on a line  302  is fed to a coefficient memory system  52  that is composed of a plurality of m parallel memory components  52   0 ,  52   1 , . . . ,  52   N−1 . The respective coefficients c 1 (m), c 2 (m), . . . , c K (m) und c 0 (m) are stored in the individual segments of this coefficient memory system  52 . For each stored index m, there is an output to an adder  53   1 ,  53   2 , . . . ,  53   K ,  53   0 , the output of which in turn is fed back to the same segment of coefficient memory system  52 . The result from a multiplier  54   1 ,  54   2 , . . . ,  54   K  is entered in the second input of the adders  53   1 , . . . . Each correspondingly exponentiated value of the sequence of digital data x n   1 , x n   2 , . . . , x n   K  is fed to the inputs of the multipliers  54   1 ,  54   2 , . . . ,  54   K . Supplied to each second input of the multipliers  54   1 ,  54   2 , . . . ,  54   K  is the result of a multiplier  55  to which both the corresponding values for difference data D n  and the negative parameter −G serving as the stability criterion are supplied. Only the value for the difference data D n , multiplied by the negative parameter −G, is supplied to the adder  53   0  at the adder&#39;s second input. 
     Using a circuit of this type, the compensation circuit  2  may be implemented on a segment-by-segment basis. The range of input data values, that is, the sequence of digital data x n , from the ADC  1  with data values from −1 to +1 is, uniformly distributed among N segments according to the expression 
                   -   1     +       2   N     ⁢   m       ≤     x   n     ≤       -   1     +       2   N     ⁢     (     m   +   1     )           ,         
where the segment index m lies between 0 and N−1. As a result, one coefficient set {c 0 (m), c 1 (m), . . . , c K (m)} is assigned to each segment. Based on segmental interpolation of the characteristic, zero th  coefficients c 0 (m) are added in, so that for the sequence of compensated digital data y n  outputted from the compensation circuit  2  the following expression applies:
 
                       y   n     =         ∑     k   =   0     k     ⁢           c   k     ⁡     (   m   )       ·     x   n   k       ⁢           ⁢   where   ⁢           ⁢   m       =     ⌊     N   ·         x   n     +   1     2       ⌋         ,           (   5   )               
where └┘ represents the rounding operation.
 
     The equation (5) for compensation in the compensation circuit  2 , and the iterative calculation of coefficients according to equation (3) may be effectively implemented together, as  FIG. 3  illustrates. In a memory of size N×(K+1), here the coefficient memory system  52 , N sets of K+1 coefficients each c 1 (m), c 2 (m), . . . , c K (m), and c 0 (m) are stored for the respective m=0, 1, 2, . . . , N−1. For each sampling instant, the index m is derived according to equation (5) from the input signal, i.e., from the applied value for the sequence of digital data x n , and assigned to the corresponding coefficient set  52   0 ,  52   1 , . . . ,  52   N−1 , then applied accordingly within the compensation circuit  2 . Also in this procedure, the stored value for each coefficient is iteratively improved according to equation (3) and stored in the same memory location. 
     As shown in  FIG. 4 , in a certain case the method with segmental interpolation may be simplified with N=2 B . For this purpose, it is necessary that the number N of segments agree with the resolution of the signal or the sequence of digital data x n , i.e., N=2 B  applies, where B is the number of bits per sampling value given a signal range between −2 B−1  and 2 B−1 −1 and only one coefficient per segment, i.e., K=0. 
     The circuit of  FIG. 3  is thereby reduced to the circuit of  FIG. 4  which has, following the index determination device  51  for determining the index m, a look-up table with 2 B  adaptive coefficients c 0 (m) in memory fields  52   0 , . . . ,  52   N−1 . In this arrangement, all the multipliers  54  are eliminated so that only the first addition stage with adders  53   1 , . . . remains, as described above. 
     Initial synthetic calculations using a sinusoidal tone as the test signal s(t) and a mathematical model of the analog-to-digital characteristic with frequencies F s =40.5 MHz, F t =1.84 MHz, the A/D model with coefficients for the calculation based on 0.9895x+0.0028x 2 +0.024x 3 −0.0064x 4  and for compensation N=1 segments, and a maximum running index of m with K=4, produced significant improvements. After analog-to-digital conversion, the initial value was −60.3 dB, and after compensation the value was 80.9 dB—yielding a significant improvement of 20.5 dB. In the case of one measurement (K3), the improvement found was −47.2 dB after A/D conversion, as compared with −56.3 dB after compensation, giving an improvement of 9.1 dB. The ratio of distortions to outputs after A/D conversion was −46.8 dB, as compared with −55.3 dB after compensation—producing an improvement of 8.4 dB. 
     In place of a plurality of individual components, as described above, an implementation is also possible in an analogously capable computer chip, or in a monolithically fabricated semiconductor device in the form of an integrated circuit or the like. 
     Although the present invention has been shown and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.