Abstract:
A driving IC for a display device that reduces the number of circuits included in a source driver, thereby decreasing the entire chip area of the driving IC. The driving IC drives a panel including a plurality of pixels whose respective gradations are represented by M-bit gradation data, and includes a memory storing gradation data for representing respective gradations of the plurality of pixels, a multiplexer unit receiving the gradation data from the memory and transmitting the M-bit gradation data through L transmission lines, where L is less than M, and a source driver serially receiving the gradation data through the L transmission lines and sequentially processing the serially received gradation data.

Description:
CROSS-REFERENCE TO RELATED PATENT APPLICATION  
       [0001]     This application claims the benefit of Korean Patent Application No. 10-2005-0122552, filed on Dec. 13, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein its entirety by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Technical Field  
         [0003]     The present disclosure relates to a driving IC for a display device, and more particularly, to a driving IC for a display device that reduces the number of circuits included in a source driver, thus decreasing the entire chip area of the driving IC.  
         [0004]     2. Discussion of the Related Art  
         [0005]     A liquid crystal display (LCD) is widely used as a display device for notebook computers, monitors and so on. The LCD has a panel for displaying images, and the panel includes a plurality of pixels. The plurality of pixels are respectively formed at intersections of a plurality of scan lines transferring a gate select signal and a plurality of data lines transferring color data, that is, gradation data.  
         [0006]     A driving IC for driving a display device such as an LCD can be designed such that a scan driver for driving scan lines and a source driver for driving data lines are integrated in a single chip. A conventional driving IC for a display device will now be explained with reference to  FIG. 1 .  
         [0007]      FIG. 1  is a block diagram of a conventional driving IC for a display device. The driving IC includes a memory  10  and a source driver  20 . The memory  10  stores gradation data corresponding to frames of images to be displayed on a panel. The gradation data is transmitted to the source driver  20  through a scan port of the memory  10 . In this example, all the gradation data bits are respectively transmitted in parallel thorough transmission lines.  
         [0008]     The size of the memory  10  decreases as the driving IC becomes more highly integrated. There is a limitation in reducing the size of the source driver  20 , however, because a voltage applied to the source driver  20  is restricted. Thus, a routing space between the memory and the source driver  20  is remarkably increased due to a mismatch between the pitch of the memory  10  and the pitch of the source driver  20 . Furthermore, in the case where the gradation data transmitted in parallel to the source driver  20  is processed for inversion or for black and white display, more circuits are required in the source driver  20  to simultaneously process the gradation data.  
         [0009]     Accordingly, there is a limitation on how much the degree of integration of the conventional driving IC for a display device can be improved.  
       SUMMARY OF THE INVENTION  
       [0010]     Exemplary embodiments of the present invention provide a driving IC for a display device, that can solve the problem that there is a limitation in improving IC the degree of integration of a driving IC due to an increase in routing space between the memory and the source driver and an increase in the circuit size of the source driver.  
         [0011]     According to an exemplary embodiment of the present invention, there is provided a driving IC for a display device including a plurality of pixels whose respective gradations are represented by M-bit gradation data. The driving IC comprises a memory storing gradation data for representing gradations of the plurality of pixels, a multiplexer unit receiving the gradation data from the memory and transmitting the M-bit gradation data through L transmission lines, where L is less than M, and a source driver serially receiving the gradation data through the L transmission lines and sequentially processing the serially received gradation data.  
         [0012]     The multiplexer unit may comprise at least one M/L-to-1 multiplexers, where M/L is an integer. The M/L-to-1 multiplexer may receive M/L-bit gradation data and sequentially output the M/L-bit gradation data bits through a single transmission line.  
         [0013]     The source driver may comprise at least one data processor that sequentially processes the gradation data serially input through a transmission line. The source driver may further comprise at least one latch unit connected to the data processor.  
         [0014]     The latch unit serially receives the M/L-bit gradation data processed by the data processor from the data processor, latches the received M/L-bit gradation data, and outputs the latched M/L-bit gradation data in parallel.  
         [0015]     According to an exemplary embodiment of the present invention, there is provided a driving IC for a display device including a plurality of pixels whose respective gradation are represented by M-bit gradation data. The driving IC comprises a memory storing gradation data for representing gradation of the plurality of pixels, a multiplexer unit comprising at least one M/L-to-1 multiplexer, where M/L is an integer, receiving the gradation data from the memory, and transmitting the M-bit gradation data through L transmission lines, where L is less than M, a source driver comprising at least one data processor connected to the M/L-to-1 multiplexer and serially receiving M/L-bit gradation data from the M/L-to-1 multiplexer, and a control signal generator generating a control signal for controlling the M/L-to-1 multiplexer to sequentially output the M/L-bit gradation data bits.  
         [0016]     According to an exemplary embodiment of the present invention, there is provided a driving IC for a display device including a plurality of pixels, the gradation of each of the plurality of pixels being represented by M-bit gradation data. The driving IC comprises a memory storing gradation data for representing gradations of the plurality of pixels, a multiplexer unit receiving the gradation data from the memory and transmitting the M-bit gradation data through L transmission lines, where L is less than M, and a source driver serially receiving the gradation data through the L transmission lines and sequentially processing the serially received gradation data. The source driver comprises at least one first latch unit connected to the multiplexer unit through a transmission line to receive and latch the gradation data, and at least one data processor receiving the gradation data serially output from the first latch unit and sequentially processing the gradation data.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]     Exemplary embodiments of the present invention will be understood in more detail from the following detailed descriptions taken in conjunction with the attached drawings in which:  
         [0018]      FIG. 1  is a block diagram of a conventional driving IC for a display device that includes a memory and a source driver;  
         [0019]      FIG. 2  is a block diagram of a driving IC for a display device according to an exemplary embodiment of the present invention;  
         [0020]      FIG. 3  is a circuit diagram of a multiplexer used in the system shown in  FIG. 2 ;  
         [0021]      FIG. 4  is a circuit diagram of a data processor used in the system shown in  FIG. 2 ;  
         [0022]      FIG. 5  is a circuit diagram of a latch unit used in the system shown in  FIG. 2 ;  
         [0023]      FIG. 6  is a waveform diagram of control signals for driving the driving IC shown in  FIG. 2 ;  
         [0024]      FIG. 7  is a block diagram of a driving IC for a display device according to an exemplary embodiment of the present invention; and  
         [0025]      FIG. 8  is a waveform diagram of control signals for driving the driving IC shown in  FIG. 7 . 
     
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS  
       [0026]     The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. Throughout the drawings, like reference numerals refer to like elements.  
         [0027]      FIG. 2  is a block diagram of a driving IC for a display device according to an exemplary embodiment of the present invention. Referring to  FIG. 2 , the driving IC for a display device includes a memory  100 , a source driver  200  and a multiplexer unit. The driving IC further includes a control signal generator  400  that generates control signals for controlling the source driver  200  and the multiplexer unit.  
         [0028]     The source driver  200  receives gradation data from the memory  100 , converts the gradation data into an analog signal and transmits the analog signal to a panel (not shown) for display. The source driver  200  includes at least one data processor  210 , at least one latch unit  220 , at least one level shifter  230 , at least one decoder  240  and at least one butter amplifier  250 .  
         [0029]     The memory  100  stores the gradation data corresponding to frames of images to be displayed on the panel. The panel includes a plurality of pixels. M-bit gradation data is applied to each of the plurality of pixels to form an image. The M-bit gradation data consists of N-bit red data, N-bit green data and N-bit blue data.  FIG. 2  illustrates 6-bit red data, R 0  through R 5 , and 6-bit green data, G 0  through G 5 , (6-bit blue data not shown) among 18-bit gradation data representing the gradation of a single pixel.  
         [0030]     The gradation data stored in the memory  100  is read and transmitted to the multiplexer unit through a scan port included in the memory  100 . The multiplexer unit includes at least one multiplexer  300 .  
         [0031]     The multiplexer unit receives M-bit gradation data and transmits the M-bit gradation data through L transmission lines (L is less than M). To transmit the M-bit gradation data through the L transmission lines, the multiplexer unit may use an M/L-to-1 multiplexer. In  FIG. 2 , gradation data representing the gradation of a single pixel has 18 bits and the multiplexer unit uses a 6-to-1 multiplexer that receives 6-bit gradation data for each color and sequentially outputs the 6-bit gradation data bits for each color. Here, the 6-to-1 multiplexer serially transmits the 6-bit gradation data bits over a single line in response to a predetermined control signal Ctrl_mux[5:0] from the control signal generator  400 .  
         [0032]     While a conventional driving IC transmits gradation data of each pixel in parallel through M transmission lines, the driving IC according to an exemplary embodiment of the present invention serially gradation data between the memory  100  and the source driver  200  through L transmission lines (L is less than M). Accordingly, the number of transmission lines connected between the memory  100  and the source driver  200  and the routing space between the memory  100  and the source driver  200  can be reduced.  
         [0033]     The gradation data serially output from each multiplexer  300  of the multiplexer unit is input to each data processor  210  of the source driver  200 . The data processor  210  receives the gradation data and sequentially processes it for inversion or for black and white display. Accordingly, the number of data processors  210  required for processing the gradation data can be reduced compared to the case where bits of gradation data input in parallel are simultaneously processed. In the case of the system shown in  FIG. 2 , each data processor  210  serially receives 6-bit gradation data and sequentially processes the 6-bit gradation data, and, thus, three data processors are needed for the 18 bits of gradation data for a single pixel.  
         [0034]     The source driver  200  may further include a plurality of latch units  220  each being connected to each data processor  210 . The latch unit  220  serially receives M/L-bit gradation data processed by the data processor  210  from the data processor  210 . In the system shown in  FIG. 2 , the latch unit  220  serially receives the 6-bit gradation data, and the serially input gradation data is latched by the latch unit  220  and output to the corresponding level shifter  230 . The latch unit  220  latches the gradation data serially input thereto in response to a predetermined control signal Ctrl_latch[5:0] from the control signal generator  400  and outputs the latched gradation data to the level shifter  230  through respective lines.  
         [0035]     The gradation data output from the latch unit  220  is transmitted to the pixels included in the panel (not shown) via the level shifter  230 , the decoder  240  and the buffer amplifier  250  through a plurality of data lines. The panel displays an image with gradations corresponding to the R, G and B data transmitted thereto.  
         [0036]     The driving IC for a display device according to an exemplary embodiment of the present invention may further include the control signal generator  400 . The control signal generator  400  generates the control signal Ctrl_mux[5:0] for controlling the multiplexer  300 . The control signal Ctrl_mux[5:0] may be identical to the control signal Ctrl_latch[5:0] for controlling the latch unit  220 , so that a period in which the multiplexer  300  outputs the gradation data corresponds to a period in which the latch  220  receives the gradation data.  
         [0037]     Furthermore, the control signal generator  400  receives K predetermined input signals C 1  through CK and generates the control Ctrl_mux[5:0] in synchronization with the input signals C 1  through CK in order to correctly transmit the gradation data from the multiplexer  300  in response to the control signal Ctrl_mux[5:0]. When 18-bit gradation data is transmitted through three transmission lines from three multiplexers  300 , for example, the control signal Ctrl_mux[5:0] consists of six signals. In this case, three input signals are needed.  
         [0038]      FIG. 3  is a circuit diagram of the multiplexer  300  used in the system shown in  FIG. 2 . When the multiplexer unit serially transmits M gradation data through L transmission lines, the multiplexer unit includes at least one M/L-to-1 multiplexer. For example, the M/L-to-1 multiplexer  300  receives 6-bit gradation data R 0  through R 5  and sequentially outputs the 6-bit gradation data bits. The M/L-to-1 multiplexer  300  includes a plurality of transfer gates T 0  through T 5 , to which the gradation data bits are respectively input.  
         [0039]     The plurality of transfer gates T 0  through T 5  are controlled by the predetermined control signal ctrl_mux[5:0] and an inverted control signal ctrl_muxB[5:0]. The control signal ctrl_mux[5:0] can be generated by the control signal generator  400  of  FIG. 2 , as described above, and the inverted control signal ctrl_muxB[5:0] can be obtained by inverting the control signal ctrl_mux[5:0].  
         [0040]     As described above, the multiplexer  300  receives the 6-bit gradation data R 0  through R 5  and sequentially outputs the 6-bit gradation data bits. The control signal ctrl_mux[5:0] includes six signals ctrl_mux[0] through ctrl_mux[5] (not shown) that are respectively input to the plurality of transfer gates T 0  through T 5  through different control signal lines. The gradation data R 0  through R 5  respectively input to the transfer gates T 0  through T 5  can be sequentially output by sequentially enabling the control signals ctrl_mux[0] through ctrl_mux[5].  
         [0041]     The multiplexer  300  can further include a latch (not shown) for holding the 6-bit gradation data to simultaneously input the 6-bit gradation data to the transfer gates T 0  through T 5 .  
         [0042]      FIG. 4  is a circuit diagram of the data processor  210  used in the system shown in  FIG. 2 . Referring to  FIG. 4 , the data processor  200  includes a NOR gate N 1 , an inverter I 1  and a multiplexer MUX. The data processor  210  sequentially processes gradation data serially input thereto for inversion or for black and black and white display.  FIG. 4  illustrates that the data processor  210  processes gradation data R 0 .  
         [0043]     The gradation data R 0  and a black and white display signal B/W_DSP are respectively input to two input terminals of the NOR gate N 1 . When the black and white display signal B/W_DSP is enabled, the signal output from the data processor  210  a logic “1” or “0”, depending on the design of the circuit, irrespective of the logic level of gradation data input to the data processor  210 .  
         [0044]     When the black and white display signal B/W_DSP is disabled, the NOR gate N 1  inverts the gradation data R 0 . The inverted gradation data R 0  is further inverted by the inverter I 1  and then input to one input terminal D 0  of the multiplexer MUX. The inverted gradation data R 0  output from the NOR gate N 1  is also input to the other input terminal D 1  of the multiplexer MUX. A predetermined control signal inv is input to a control input terminal S of the multiplexer MUX and the gradation data R 0  and the inverted gradation data RD are selectively output through an output terminal Y of the multiplexer MUX, in response to the control signal inv, thereby performing an inversion operation.  
         [0045]     The data processor  210  processes the input gradation data R 0  for inversion and for black and white display and then processes gradation data R 1  input thereto following the gradation data R 0 . In this manner, the data processing operation is sequentially performed on gradation data R 0  through R 5  so as to reduce the number of data processors included in the source driver  200  by a factor of 6. As shown in  FIG. 4 , each data processor  210  can include a single NOR gate, a single inverter and a single multiplexer. The size of the source driver  200  can be reduced by decreasing the number of data processors that are required.  
         [0046]      FIG. 5  is a circuit diagram of the latch unit  220  of  FIG. 2 . Referring to  FIG. 5 , the latch unit  220  serially receives the gradation data output from the data processor  210  and latches the received gradation data. The latch unit  220  is connected to the output terminal Y of the multiplexer MUX included in the data processor  210  (illustrated in  FIG. 4 ) and receives the gradation data R 0  through R 5 .  
         [0047]     The latch unit  220  includes a plurality of transfer gates, for example, six transfer gates T 10  through T 15 . The transfer gates T 10  through T 15  are controlled by a predetermined control signal ctrl_latch[5:0] from the control signal generator  400  and an inverted control signal ctrl_latchB[5:0]. It is preferable that the control signal ctrl_latch[5:0] be identical to the control signal ctrl_mux[5:0] for the controlling the multiplexer  300 , as described above. The inverted control signal ctrl_latchB[5:0] can be obtained by inverting the control signal ctrl_latch[5:0 ].  
         [0048]     The control signal ctrl_latch[5:0] includes six signals ctrl_latch[0] through ctrl_latch[5] (not shown) that are respectively applied to the transfer gates T 10  through T 15  through different control signal lines.  
         [0049]     The latch unit  220  can further include a latch that is connected to each of the transfer gates T 10  through T 15  to latch one-bit gradation data input from each of the transfer gates T 10  through T 15 .  FIG. 5  shows six latches L 10  through L 15  respectively connected to the six transfer gates T 10  through T 15 .  
         [0050]     The serially input gradation data R 0  through R 5  can be respectively input to the transfer gates T 10  through T 15  by sequentially enabling the control signals ctrl_latch[0] through ctrl_latch[5]. More specifically, the control signal ctrl_latch[0] and gradation data R 0  are enabled so that the gradation data R 0  is transferred to the latch L 10  thorough the transfer gate T 10 . Then, the control signal ctrl_latch[1] and the gradation data R 1  are enabled such that the gradation data R 1  is transferred to the latch L 11  through the transfer gate T 11 . In this manner, the serially input gradation data R 0  through R 5  are respectively transferred to the latches L 10  through L 15 .  
         [0051]     The gradation data R 0  through R 5  transferred to the latches L 10  through L 15  are output to the level shifter  230  used in the system shown in  FIG. 2  through respective lines and then converted into analog signals by the decoder  240  and the buffer amplifier  250  and transmitted to a panel (not shown).  
         [0052]     The operation of the diagram IC for a display device according to an exemplary embodiment of the present invention will now be explained in detail.  
         [0053]      FIG. 6  is a waveform diagram of the control signals input to the driving IC of  FIG. 2 . In particular,  FIG. 6  illustrates the waveforms of the control signals input to the driving IC of  FIG. 2  when the multiplexer  300  of  FIG. 2  is a 6-to-1 multiplexer.  
         [0054]     When a signal HSYNC representing a data signal input period of a single row of the matrix on the panel (not shown) is enabled, the control signals ctrl_mux[5:0] and ctrl_latch2[5:0] are enabled. It is preferable that the control signal ctrl_mux[5:0] be identical to the control signal ctrl_latch[5:0].  
         [0055]     The control signal ctrl_mux[0] is enabled, and thus the gradation data R 0  is transferred from the multiplexer  300  to the data processor  210  through a single transmission line. The data processor  210  processes the gradation data R 0  for inversion or black/white display if required and outputs the processed gradation data R 0 . The gradation data R 0  output from the data processor  210  is input to the latch unit  220 . In this case, the gradation data R 0  is transferred to the latch L 10  through the transfer gate T 10  because the control signal ctrl_latch[1] is enabled.  
         [0056]     Then, the control signals ctrl_mux[1] and ctrl_latch[1] are enabled and, thus, the gradation data R 1  is transferred from the multiplexer  300  to the data processor  210  through a transmission line. The gradation data R 1  processed by the data processor  210  is transferred to the late L 11  through the transfer gate T 11  of the latch unit  220 . In this manner, the gradation data R 0  though R 5  are latched by the latches L 10  through L 15  and output to the level shifter  230 .  
         [0057]     The data processor  210  is composed of logic gates. A period in which the multiplexer  300  is not operated may exist between enabled periods of the control signals ctrl_mux[0] through ctrl_mux[5], as illustrated in  FIG. 6 . In this period in which the multiplexer  300  is not operated, the input terminal of the data processor  210  may be left floating, which increases leakage current. To solve this problem, the driving IC for a display device according to an exemplary embodiment of the present invention can be constructed as follows.  
         [0058]      FIG. 7  is a block diagram of a driving IC for a display device according to an exemplary embodiment of the present invention. Detailed explanations of the components of the driving IC of  FIG. 7  are omitted because they are identical to those of the driving IC of  FIG. 2 .  
         [0059]     Referring to  FIG. 7 , the driving IC includes a memory  100 , a source driver  500  and a multiplexer unit. The source driver  500  receives gradation data from the memory  100 , converts the gradation data into an analog signal and transmits the analog signal to a panel (not shown). The source driver  500  includes at least one first latch unit  510 , at least one data processor  520 , at least one second latch unit  530 , at least one level shifter  540 , at least one decoder  550  and at least one buffer amplifier  560 . The multiplexer unit includes at least one multiplexer  300 .  
         [0060]     The driving IC may further include a control signal generator (not shown) that generates the control signals for controlling the source driver  500  and the multiplexer unit. The multiplexer unit and the second latch unit  530  of the source driver  500  are controlled by control signals generated by the control signal generator as in the system shown in  FIG. 2 . The first latch unit  510  is controlled by a control signal generated by the control signal generator or by a separate control signal.  
         [0061]      FIG. 8  is a waveform diagram of the control signals for driving the driving IC of  FIG. 7 . Each multiplexer  300  included in the multiplexer unit is controlled by a control signal ctrl_mux[5:0] output from the control signal generator. It is preferable that a control signal ctrl_latch2[5:0] for controlling the second latch unit  530  be identical to the control signal ctrl_mux[5]. In  FIG. 8 , an example of a control signal ctrl_latch1 input to the first latch unit  510  is illustrated.  
         [0062]     When a signal HSYNC representing a data signal input period of a single row of the matrix of the panel (not shown) is enabled, the control signal ctrl_latch1 for controlling the first latch unit  510  is enabled and the control signals ctrl_mux[0] through ctrl_mux[5] are sequentially enabled during the enabled period of the control signal ctrl_latch1.  
         [0063]     The control signal ctrl_mux[0] is enabled and thus one bit of gradation data (R 0 , for example) is transferred from the multiplexer  300  to the first latch unit  510 . The gradation data R 0  transferred to the first latch unit  510  is transmitted to the data processor  520 . The gradation data R 0  is processed by the data processor  520  and then sent to the second latch unit  520 . In this manner, 6-bit gradation data is serially transferred from the multiplexer  300  to the second latch unit  530 . The second latch unit  530  latches the 6-bit gradation data and outputs the latched 6-bit gradation data to the level shifter  540 .  
         [0064]     Then, the next control signal ctrl_mux[1] is enabled and the gradation data R 1  is subjected to the aforementioned process. Subsequently, the control signals ctrl_mux[2], ctrl_mux[3], ctrl_mux[4] and ctrl_mux[5] are sequentially enabled and, thus, the gradation data R 2 , R 3 , R 4  and R 5  are subjected to the aforementioned process. A period “d” in which the control signals ctrl_mux[0] through ctrl_mux[5] are disabled such that the multiplexer  300  is not operating occurs between the period in which the control signal ctrl_mux[5] is enabled to transmit the gradation data R 5  and the period in which the control signal ctrl_mux[0] is enabled to transmit the gradation data R 0 . In this case, the input terminal of the data processor  520  composed of logic gates is left floating, which increases leakage current. In an exemplary embodiment of the present invention, however, the first latch unit  510  latches the gradation data R 5  and transfers the gradation data R 5  to the input terminal of the data processor  520  during the period “d” in which the multiplexer  300  is not operated, and thus the problem caused by the leak-age current can be solved.  
         [0065]     The control signals ctrl_mux[5:0] and ctrl_latch[5:0] shown in  FIG. 6 , instead of the control signals ctrl_mux[5:0], and ctrl_latch2[5:0], can be applied to the driving IC of  FIG. 7 . In this case, a period in which the multiplexer  300  is not operating occurs between the control signals, for example, between ctrl_mux[0] and ctrl_mux[1] and between ctrl_mux[1] and ctrl_mux[2]. The first latch unit  510  latches the gradation data right before the period in which the multiplexer  300  is not operating and transfers the latched gradation data to the input terminal of the data processor  520 . Accordingly, the aforementioned problem caused by the leakage current can be solved.  
         [0066]     The present invention is not limited to just the transmission of 18-bit gradation data by three 6-to-1 multiplexers through three transmission lines, as in the above-described exemplary embodiments. For example, the 18-bit gradation data can be transmitted using two 9-to-1 multiplexers through two transmission lines. Furthermore, when gradation data for representing the gradation of one pixel has a number of bits other than 18, a multiplexer having a different multiplexing characteristic can be used to transmit the gradation data.  
         [0067]     According to exemplary embodiments of the present invention, gradation data stored in a memory is serially transmitted to a source driver and the serially transmitted gradation data is sequentially processed, so that a routing space between the memory and the source driver and the number of circuits included in the source driver can be reduced. Accordingly, the degree of integration of the driving IC can be improved.  
         [0068]     While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.