Abstract:
When the operating speed of a switched capacitor circuit is accelerated, the timing of the clock signals regulating switched capacitor circuit operation can be disrupted by the effects of variation introduced by the manufacturing process as well as parasitic resistance and parasitic capacitance on signal traces. A control signal generating unit adjusts the timing of the bottom plate sampling period and non-overlapping period of the clock signals supplied to operate the switched capacitor circuit, thus avoiding disrupting the control signal timing and affording a switched capacitor circuit without increasing the area of the logic devices that set the bottom plate sampling period and non-overlapping period.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of Invention  
         [0002]     The present invention relates generally to technology for operating an operational amplifier using a switched capacitor circuit, and relates more particularly to technology for a clock signal generating device, generating method, and signal processing device for supplying clock signals to a switched capacitor circuit.  
         [0003]     2. Description of Related Art  
         [0004]     Switched capacitor circuits that provide high speed operation and occupy little space are needed for such applications as use in the amplifier stage of a pipeline A/D converter. As operating speed increases and device size decreases, the timing requirements of the clock signal used to operate the switched capacitor circuit become increasingly critical.  
         [0005]      FIG. 8  is a circuit diagram of a common clock signal generating circuit for generating the clock signals φ 1   p,  φ 1 Pp, φ 2   p,  φ 2 Pp for operating an operational amplifier using a switched capacitor circuit. This clock signal generating circuit includes NAND circuits  1   ap,    1   bp,    1   cp,    1   dp,  and a plurality of logic devices rendered by inverters  2   ap,    2   bp,    2   cp,    2   dp,    2   ep,    2   fp,    2   gp,    2   hp,    2   ip,    2   jp,    2   kp,    2   lp,    2   mp,    2   np.    
         [0006]      FIG. 9  is a timing chart of clock signals φ 1   p,  φ 1 Pp, φ 2   p,  φ 2 Pp.  
         [0007]     A bottom plate sampling period and a non-overlapping period are provided in a switched capacitor circuit to prevent the adverse effects of charge accumulation in the parasitic capacitance when the switch switches. An arrangement according to the related art for generating these periods is described next.  
         [0008]     The timing of the bottom plate sampling period T 1 Lp required at the falling edge of clock signal φ 1 Pp and the falling edge of clock signal φ 1   p  is determined by the total delay of logic devices  2   bp,    2   cp,    2   dp.    
         [0009]     The timing of the non-overlapping period T 2 Np required at the falling edge of clock signal φ 1   p  and the rising edge of clock signal φ 2   p  is determined by the total delay of logic devices  2   ep,    2   fp,    2   gp.    
         [0010]     Likewise, the timing of the bottom plate sampling period T 2 Lp required at the falling edge of clock signal φ 2 Pp and the falling edge of clock signal φ 2   p  is determined by the total delay of logic devices  2   ip,    2   jp,    2   kp.    
         [0011]     The timing of the non-overlapping period T 1 Np required at the failing edge of clock signal φ 2   p  and the rising edge of clock signal φ 1   p  is determined by the total delay of logic devices  2   lp,    2   mp,    2   np.    
         [0012]     The clock signals CLKp and ICLKp input from input pins  3   ap,    3   bp  are thus processed and output from output pins  4   ap,    4   bp,    4   cp,    4   dp  at the timing of clock signals φ 1 Pp, φ 1   p,  φ 2 Pp, φ 2   p,  respectively.  
         [0013]     The arrangement of the logic devices  2   bp,    2   cp,    2   dp,    2   ep,    2   fp,    2   gp,    2   ip,    2   jp,    2   kp,    2   lp,    2   mp,    2   np  for setting the bottom plate sampling periods T 1 Lp and T 2 Lp and non-overlapping periods T 1 Np and T 2 Np is shown in  FIG. 10 . This is a common inverter circuit, and the transistors  7   dp,    8   bp  rendering the inverter pass operating current between power supply node  3   cp  and ground node  3   dp,  take a clock signal input to node  3   ep  and output a clock signal from node  4   ep.  If the transistors are large, more operating current passes through the circuit, the response rate is faster, and the delay per logic device is shorter. Conversely, if the transistors are small, less operating current passes the circuit, the response rate is slower, and the delay per logic device is longer. The required bottom plate sampling periods T 1 LP and T 2 Lp and non-overlapping periods T 1 Np and T 2 Np can therefore be set by adjusting the size of the transistors.  
         [0014]     The circuit shown in  FIG. 8  uses three logic devices each to set the timing between clock signal φ 1 Pp and clock signal φ 1   p,  the timing between clock signal φ 1   p  and φ 2   p,  the timing between clock signal φ 2 Pp and clock signal φ 2   p,  and the timing between clock signal φ 2   p  and clock signal φ 1   p.  The required bottom plate sampling periods T 1 Lp and T 2 Lp and non-overlapping periods T 1 Np and T 2 Np can also be set by increasing the number of stages of these three element logic devices.  
         [0015]     See, for example, U.S. Patent Application Publication No. 2005/0018061 (corresponding to Japanese Unexamined Patent Application Publication No. 2005-45786).  
         [0016]     When the switched capacitor circuit and the clock signal generating circuit such as shown in  FIG. 8  are provided on the same circuit board, variation in the logic devices and the parasitic resistance and parasitic capacitance components on the clock traces result in variation in the bottom plate sampling period and non-overlapping period. When a switched capacitor circuit is accelerated, the clock period is shorter and the effect of such variations is extremely great. This disrupts the timing of the bottom plate sampling period and non-overlapping period, and causes a signal offset in the operation of the switched capacitor circuit.  
         [0017]     Furthermore, when the required bottom plate sampling period and non-overlapping period are set by adjusting the transistor size or increasing the number of logic device stages, depending upon the length of the required bottom plate sampling period and non-overlapping period, the area occupied by the logic devices for setting the bottom plate sampling period and non-overlapping period on the circuit board increases and could require using a larger circuit board.  
       SUMMARY OF THE INVENTION  
       [0018]     A clock signal generating device according to a first aspect of the invention for supplying four clock signals with a repeating first edge and second edge to a switched capacitor circuit has a common mode delayed clock signal generator operable to generate a common mode delayed clock signal having a first edge delayed a first variable discharge delay from the first edge of a common mode reference clock signal; an opposite phase delayed clock signal generator operable to generate an opposite phase delayed clock signal with a first edge delayed a second variable discharge delay from the first edge of an opposite phase reference clock signal; a common mode reference clock signal generator operable to generate a common mode reference clock signal having a second edge delayed a first variable non-superimposed delay from the first edge of the opposite phase delayed clock signal; and an opposite phase reference clock signal generator operable to generate the opposite phase reference clock signal having a second edge delayed a second variable non-superimposed delay from the first edge of the common mode delayed clock signal. The common mode delayed clock signal generator generates the common mode delayed clock signal with a second edge delayed substantially the first variable non-superimposed delay from the first edge of the opposite phase delayed clock signal, and the opposite phase delayed clock signal generator generates the opposite phase delayed clock signal with a second edge delayed substantially the second variable non-superimposed delay from the first edge of the common mode delayed clock signal.  
         [0019]     A clock signal generating method according to another aspect of the invention for supplying four clock signals with a repeating first edge and second edge to a switched capacitor circuit has generating a common mode delayed clock signal having a first edge delayed a first variable discharge delay from the first edge of a common mode reference clock signal; generating an opposite phase delayed clock signal with a first edge delayed a second variable discharge delay from the first edge of an opposite phase reference clock signal; generating a common mode reference clock signal having a second edge delayed a first variable non-superimposed delay from the first edge of the opposite phase delayed clock signal; and generating the opposite phase reference clock signal having a second edge delayed a second variable non-superimposed delay from the first edge of the common mode delayed clock signal. The generating the common mode delayed clock signal generates the common mode delayed clock signal with a second edge delayed substantially the first variable non-superimposed delay from the first edge of the opposite phase delayed clock signal, and the generating the opposite phase delayed clock signal generates the opposite phase delayed clock signal with a second edge delayed substantially the second variable non-superimposed delay from the first edge of the common mode delayed clock signal.  
         [0020]     A signal processing device according to another aspect of the invention has a switched capacitor circuit; a clock signal generating device operable to supply four clock signals with a repeating first edge and second edge to the switched capacitor circuit; and a control signal adjustment arrangement operable to adjust the first edge and second edge of the clock signals based on signals that are signal processed by the switched capacitor circuit. The clock signal generating device has a common mode delayed clock signal generator operable to generate a common mode delayed clock signal having a first edge delayed a first variable discharge delay from the first edge of a common mode reference clock signal; an opposite phase delayed clock signal generator operable to generate an opposite phase delayed clock signal having a first edge delayed a second variable discharge delay from the first edge of an opposite phase reference clock signal; a common mode reference clock signal generator operable to generate a common mode reference clock signal having a second edge delayed a first variable non-superimposed delay from the first edge of the opposite phase delayed clock signal; and an opposite phase reference clock signal generator operable to generate the opposite phase reference clock signal having a second edge delayed a second variable non-superimposed delay from the first edge of the common mode delayed clock signal. The common mode delayed clock signal generator generates the common mode delayed clock signal with a second edge delayed substantially the first variable non-superimposed delay from the first edge of the opposite phase delayed clock signal, and the opposite phase delayed clock signal generator generates the opposite phase delayed clock signal with a second edge delayed substantially the second variable non-superimposed delay from the first edge of the common mode delayed clock signal.  
         [0021]     As described above, the invention enables precisely adjusting the timing of the bottom plate sampling period and non-overlapping period required in a switched capacitor circuit. Disruption of the timing of the bottom plate sampling period and non-overlapping period can thus be avoided when accelerating the switched capacitor circuit even if there is a parasitic resistance and parasitic capacitance on the signal traces or manufacturing variations in the operational amplifier using the switched capacitor circuit. The timing can also be adjusted precisely by adjusting the current flow to the logic devices that set the delay of the bottom plate sampling period and non-overlapping period. The required bottom plate sampling period and non-overlapping period can therefore be set without adjusting the transistor size or increasing the number of logic device stages. A small circuit board can therefore be used because the switched capacitor circuit can be rendered without increasing the area of the logic devices used to set the bottom plate sampling period and non-overlapping period delay.  
         [0022]     Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0023]      FIG. 1  is a circuit diagram of a clock signal generating device according to a first embodiment of the invention.  
         [0024]      FIG. 2  is a timing chart describing operation of the clock signal generating device of the first embodiment of the invention.  
         [0025]      FIG. 3  is a circuit diagram showing the arrangement of logic devices according to a second embodiment of the invention.  
         [0026]      FIG. 4  is a block diagram of a signal generating device using a clock signal generating device according to a third embodiment of the invention.  
         [0027]      FIG. 5  is a block diagram of a signal generating device using a clock signal generating device according to a fourth embodiment of the invention.  
         [0028]      FIG. 6  is a block diagram showing a first example of a switched capacitor circuit that operates according to a clock signal from the clock signal generating device.  
         [0029]      FIG. 7  is a block diagram showing a second example of a switched capacitor circuit that operates according to a clock signal from the clock signal generating device.  
         [0030]      FIG. 8  is a circuit diagram of a clock signal generating circuit according to the related art.  
         [0031]      FIG. 9  is a timing chart of a clock signal generating circuit according to the related art.  
         [0032]      FIG. 10  is a circuit diagram of a logic device used in the clock signal generating circuit according to the related art. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0033]     Preferred embodiments of a motor drive device according to the present invention are described below with reference to the accompanying figures. The numbers used in the following description of the invention are used by way of example only to describe the invention in detail, and the invention is not limited to these values.  
       First Embodiment  
       [0034]      FIG. 1  is a circuit diagram showing the arrangement of a clock signal generating device  11  according to a first embodiment of the invention. The clock signal generating device  11  shown in  FIG. 1  includes a clock signal output unit  3  for outputting clock signal CLK and clock signal ICLK, which is clock signal CLK inverted (opposite phase), a control signal generating unit  6  for generating control signals  6   a  and  6   b,  and clock signal generating circuit  11   a.    
         [0035]     The clock signal generating circuit  11   a  includes NAND circuits  1   a,    1   b,    1   c,    1   d,  inverter circuits  2   a,    2   b,    2   d,    2   e,    2   g,    2   h,    2   i,    2   k,    2   l,    2   n,  input pin  3   a  for inputting clock signal CLK, input pin  3   b  for inputting clock signal ICLK, output pin  4   a  for outputting clock signal φ 1 P, output pin  4   b  for outputting clock signal φ 1 , output pin  4   c  for outputting clock signal φ 2 P, output pin  4   d  for outputting clock signal φ 2 , and logic devices  5   a,    5   b,    5   c  with an inverter circuit function for varying the clock signal delay based on control signals  6   a  and control signal  6   b.    
         [0036]     Inverter circuits  2   b  and  2   d  and logic device  5   a  render variable discharge delay circuit D 1 L.  
         [0037]     Inverter circuits  2   l  and  2   n  and logic device  5   c  render variable non-superimposed delay circuit D 1 N.  
         [0038]     Inverter circuits  2   i  and  2   k  and logic device  5   d  render variable discharge delay circuit D 2 L.  
         [0039]     Inverter circuits  2   e  and  2   g  and logic device  5   b  render variable non-superimposed delay circuit D 2 N.  
         [0040]     Variable non-superimposed delay circuit D 1 N, NAND circuit  1   a,  and inverter circuit  2   a  render a common mode reference clock signal generating unit.  
         [0041]     Variable non-superimposed delay circuit D 2 N, NAND circuit  1   c,  and inverter circuit  2   h  render an opposite phase reference clock signal generating unit.  
         [0042]     The common mode reference clock signal generating unit, variable discharge delay circuit D 1 L, and NAND circuit  1   b  render a common mode delayed clock signal generating unit.  
         [0043]     The opposite phase reference clock signal generating unit, variable discharge delay circuit D 2 L, and NAND circuit  1   d  render an opposite phase delayed clock signal generating unit.  
         [0044]     The clock signal CLK is also called a common mode clock signal, and clock signal ICLK is also called an opposite phase clock signal.  
         [0045]     Clock signal φ 1 P is also called a common mode reference clock signal and clock signal φ 2 P is also called an opposite phase reference clock signal.  
         [0046]     Clock signal φ 1  is also called a common mode delayed clock signal, and clock signal φ 2  is also called an opposite phase delayed clock signal.  
         [0047]     Control signal  6   a  is also called a discharge control signal, and control signal  6   b  is also called a non-superimposed control signal.  
         [0048]     Based on common mode clock signal CLK and opposite phase clock signal ICLK, the clock signal generating device  11  generates common mode reference clock signal φ 1 P and opposite phase delayed clock signal φ 1  that are the same phase and delayed to the common mode clock signal CLK, and generates opposite phase reference clock signal φ 2 P and opposite phase delayed clock signal φ 2  that are the same phase and delayed to opposite phase clock signal ICLK. The delay of common mode reference clock signal φ 1 P and common mode delayed clock signal φ 1  to common mode clock signal CLK, and the delay of opposite phase reference clock signal φ 2 P and opposite phase delayed clock signal φ 2  to opposite phase clock signal ICLK are less than half the clock signal CLK, ICLK period.  
         [0049]     The common mode reference clock signal generating unit generates the common mode reference clock signal φ 1 P based on common mode clock signal CLK and opposite phase delayed clock signal φ 2 .  
         [0050]     The opposite phase reference clock signal generating unit generates the opposite phase reference clock signal φ 2 P based on the opposite phase clock signal ICLK and the common mode delayed clock signal φ 1 .  
         [0051]     The common mode delayed clock signal generating unit generates the common mode delayed clock signal φ 1  that is related to the common mode reference clock signal φ 1 P based on the common mode clock signal CLK and opposite phase delayed clock signal φ 2 .  
         [0052]     The opposite phase delayed clock signal generating unit generates the opposite phase delayed clock signal φ 2  related to the opposite phase reference clock signal φ 2 P based on the opposite phase clock signal ICLK and the common mode delayed clock signal φ 1 .  
         [0053]      FIG. 2  is a timing chart describing the operation of the clock signal generating device  11  according to this first embodiment of the invention.  
         [0054]     Operation of the clock signal generating device  11  is described next with reference to  FIG. 1  and  FIG. 2 .  
         [0055]     The clock signal generating device  11  generates four clock signals φ 1 P, φ 1 , φ 2 P, and φ 2  with repeating falling edges and rising edges. Clock signal B is opposite phase (i.e., same phase as the clock signal CLK) and delayed to clock signal φ 2 . Clock signal φ 1 P is derived from clock signal A (clock signal CLK) and clock signal B where φ 1 P=A*B.  
         [0056]     Because clock signal A is HIGH at the rising edge of clock signal B, φ 1 P=1 (HIGH), and at the falling edge of clock signal A (more precisely, after the combined delay T 1 B of NAND  1   a  and inverter  2   a ), φ 1 P=0 (goes LOW). Clock signal B at this time is the clock signal φ 2  inverted and delayed. The total of this delay and delay T 1 B is also called the variable non-superimposed delay T 1 N, and can be adjusted by the logic device  5   c  according to control signal  6   b.  More specifically, the rising edge of clock signal φ 1 P is delayed variable non-superimposed delay T 1 N from the falling edge of clock signal φ 2 .  
         [0057]     Clock signal φ 1  is likewise derived from clock signal C and clock signal D and is the inverse of φ 1 =C*D, and at the falling edge of clock signal D, which precedes clock signal C, φ 1 =1. The rising edge of clock signal φ 1  is therefore delayed approximately variable non-superimposed delay T 1 N from the rising edge of clock signal φ 2 . At the rising edge of clock signal C, which is delayed more than clock signal D, φ 1 =0. Clock signal C at this time is the delayed inverted clock signal φ 1 P. This delay T 1 L is also called the variable discharge delay T 1 L, and can be adjusted by the logic device  5   a  according to control signal  6   a.  More specifically, the falling edge of clock signal φ 1  is delayed variable discharge delay T 1 L from the falling edge of clock signal φ 1 P.  
         [0058]     Clock signal φ 2 P is derived from clock signal E and clock signal F (clock signal ICLK), and φ 2 P=E*F. At the rising edge of clock signal E, φ 2 P=1, and at the falling edge of clock signal F (more precisely after the combined delay T 2 B of NAND  1   c  and inverter  2   h ) φ 2 P=0. Clock signal E is the clock signal φ 1  inverted and delayed. The total of this delay and delay T 2 B is also called variable non-superimposed delay T 2 N, and can be adjusted by the logic device  5   b  according to control signal  6   b.  More specifically, the rising edge of clock signal φ 2 P is delayed variable non-superimposed delay T 2 N from the rising edge of clock signal φ 1 .  
         [0059]     Clock signal φ 2  is likewise derived from clock signal G and clock signal H and is the inverse of φ 1 =G*H, and at the falling edge of clock signal G φ 2 =1. The rising edge of clock signal φ 2  is therefore delayed approximately variable non-superimposed delay T 2 N from the falling edge of clock signal φ 1 . At the rising edge of clock signal H, φ 2 =0. Clock signal H at this time is the delayed inverted clock signal φ 2 P. This delay T 2 L is also called the variable discharge delay T 2 L, and can be adjusted by the logic device  5   d  according to control signal  6   a.  More specifically, the falling edge of clock signal φ 2  is delayed variable discharge delay T 2 L from the falling edge of clock signal φ 2 P.  
         [0060]     The period between the falling edge of clock signal φ 2  and the rising edge of clock signal φ 1 P, that is, the non-overlapping period T 1 N of clock signal φ 2  and clock signal φ 1 P, can be adjusted by the timing of control signal  6   b.    
         [0061]     The period between the falling edge of clock signal φ 1 P and the falling edge of clock signal φ 1 , that is, the bottom plate sampling period T 1 L of clock signal φ 1 P and clock signal φ 1 , can be adjusted by the timing of control signal  6   a.    
         [0062]     The period between the falling edge of clock signal φ 1  and the rising edge of clock signal φ 2 P, that is, non-overlapping period T 2 N of clock signal φ 1  and clock signal φ 2 P, can be adjusted by the timing of control signal  6   b.    
         [0063]     The period between the falling edge of clock signal φ 2 P and the falling edge of clock signal φ 2 , that is, the bottom plate sampling period T 2 L of clock signal φ 2 P and clock signal φ 2 , can be adjusted by the timing of control signal  6   a.    
         [0064]     The common mode delayed clock signal generating unit is controlled based on the discharge control signal  6   a  and adjusts variable discharge delay T 1 L.  
         [0065]     The common mode reference clock signal generating unit is controlled based on non-superimposed control signal  6   b  and adjusts variable non-superimposed delay T 1 N.  
         [0066]     The opposite phase delayed clock signal generating unit is controlled based on discharge control signal  6   a  and adjusts variable discharge delay T 1 L.  
         [0067]     The opposite phase reference clock signal generating unit is controlled based on non-superimposed control signal  6   b  and adjusts variable non-superimposed delay T 2 N.  
         [0068]      FIG. 6  shows an operational amplifier using a switched capacitor circuit operated by the clock signal generating device  11 . An operational amplifier using a switched capacitor circuit is also called simply a switched capacitor circuit. This switched capacitor circuit is composed of switches  25   a,    25   b,    25   d  that switch on/off according to clock signal φ 1  input over signal path a, switch  25   c  that switches on/off according to clock signal φ 1 P input over signal path b, switches  25   e  and  25   f  that switch on/off according to clock signal φ 2  input over signal path c, capacitors  26   a  and  26   b,  and operational amplifier  24 .  
         [0069]     Signal Vin input from input pin  3   f  charges capacitors  26   a  and  26   b  when switches  25   a,    25   b  go on when clock signal φ 1  goes HIGH. Switch  25   d  also goes on when clock signal φ 1  goes HIGH, and the bias voltage Vb 2  input from input pin  3   h  resets the output signal Vout of operational amplifier  24 . Switch  25   c  goes on when clock signal φ 1 P goes HIGH, and shorts the two inputs to operational amplifier  24 . Switches  25   e  and  25   f  go off when clock signal φ 2  goes LOW.  
         [0070]     Switch  25   c  then goes off when clock signal φ 1  goes LOW, and capacitors  26   a  and  26   b  proceed with bottom plate sampling. When the switch goes from on to off, the charge accumulated in the parasitic capacitance of the switch discharges (leaks). The leaked charge accumulates in the signal sampling capacitors and causes a signal offset. Bottom plate sampling is a method of preventing this signal offset. In a switched capacitor circuit this bottom plate sampling period T 1 L is extremely important.  
         [0071]     When clock signal φ 1  goes LOW, switches  25   a,    25   b,    25   d  turn off and capacitors  26   a  and  26   b  stop signal sampling. When clock signal φ 2  goes HIGH, switches  25   e  and  25   f  turn on, capacitor  26   b  is shorted to bias voltage Vb 1  from input pin  3   g,  and capacitor  26   a  is shorted to output signal Vout of operational amplifier  24 . As a result, input signal Vin is amplified and the amplified output signal Vout is output from output pin  4   f.    
         [0072]     A time when all switches are off (non-overlapping period T 2 N) is required until switches  25   a,    25   b,    25   d  turn off when clock signal φ 1  goes LOW and switches  25   e  and  25   f  turn on when clock signal φ 2  goes HIGH.  
         [0073]     This is because variation in the timing results in error in the amplified output signal Vout because clock signal φ 2  goes on and the charge sampled by capacitors  26   a  and  26   b  is discharged before switches  25   a,    25   b,    25   d  are turned off by clock signal φ 1 . To prevent this, non-overlapping period T 2 N is important in a switched capacitor circuit.  
         [0074]     If the capacitance of capacitors  26   a  and  26   b  is equal, this sequence of operations yields a switched capacitor circuit that produces output signal Vout based on signal Vin and bias voltage Vb 1  where Vout=2*Vin−Vb 1 .  
         [0075]      FIG. 7  shows a plurality of the switched capacitor circuits shown in  FIG. 6  connected in series similarly to a pipeline A/D converter. These switched capacitor circuits operate in the same way based on clock signals φ 1 , φ 1 P, φ 2 , φ 2 P, and further description thereof is omitted.  
         [0076]     The non-overlapping period and bottom plate sampling period can be adjusted as desired by driving the switched capacitor circuits shown in  FIG. 6  and  FIG. 7  by the clock signal generating device  11  according to this embodiment of the invention. Disruption of the timing of the bottom plate sampling period and non-overlapping period can thus be avoided when accelerating the switched capacitor circuit even if there is a parasitic resistance and parasitic capacitance on the signal traces or manufacturing variations in the switched capacitor circuit.  
         [0077]     Only two control signals  6   a  and  6   b  are used in this embodiment as shown in  FIG. 1 , i.e. the control signals  6   a  and  6   b  are generated substantially at the same timing. But four different control signals can be generated so that a discrete control signal is separately applied to each of the logic devices  5   a,    5   b,    5   c,    5   d.    
         [0078]     Furthermore, two variable discharge delays T 1 L and T 2 L are also defined, but variable discharge delay T 1 L and variable discharge delay T 2 L can be equal.  
         [0079]     Furthermore, two variable non-superimposed delays T 1 N and T 2 N are also defined, but variable non-superimposed delay T 1 N and variable non-superimposed delay T 2 N can be equal.  
         [0080]     Furthermore, the above description of the falling edge and rising edge times is reversed if switches  25   a,    25   b,    25   c,    25   d,    25   e,  and  25   f  turn on when the clock signals φ 1 , φ 1 P, φ 2 , φ 2 P go LOW.  
       Second Embodiment  
       [0081]     A second embodiment of the invention is described below focusing on the differences between the second embodiment and the first embodiment. Other aspects of the arrangement, operation, and effect of this embodiment are the same as in the first embodiment, and further description thereof is omitted below.  
         [0082]     The logic device  5   a  that receives the control signal and adjusts the delay in this second embodiment of the invention is described with reference to  FIG. 3 . This logic device  5   a  includes p-MOS transistors  7   a,    7   b,    7   c,    7   d,  n-MOS transistors  8   a,    8   b,    8   c,  and variable current source  9  that adjusts the current supply based on control signal  6   c.    
         [0083]     MOS transistors  7   d  and  8   b  operate based on the clock signal input from input pin  3   e.  The operating current of transistors  7   d  and  8   b  is controlled by the variable current source  9  at this time because transistor  7   a  and transistors  7   b  and  7   c,  or transistor  8   a  and transistor  8   c  are in a current mirror configuration. Because the variable current source  9  is controlled by control signal  6   c,  the delay of the output clock signal from clock output pin  4   e  varies according to control signal  6   a.    
         [0084]     Logic devices  5   b,    5   c,    5   d  are configured identically to logic device  5   a  as shown in  FIG. 3 , and the delay of logic devices  5   b,    5   c,    5   d  is controlled by control signals  6   a,    6   b,  and  6   a,  respectively. Logic device  5   a,    5   b,    5   c,    5   d  are also called active circuits. Active circuits  5   a,    5   b,    5   c,    5   d  are included in the common mode delayed clock signal generating unit, common mode reference clock signal generating unit, the opposite phase reference clock signal generating unit, and the opposite phase delayed clock signal generating unit, respectively.  
         [0085]     More specifically, the common mode delayed clock signal generating unit includes active circuit  5   a  that changes the variable discharge delay T 1 L by changing the operating current based on discharge control signal  6   a.    
         [0086]     The common mode reference clock signal generating unit includes active circuit  5   c  that changes the variable non-superimposed delay T 1 N by changing the operating current based on non-superimposed control signal  6   b.    
         [0087]     The opposite phase reference clock signal generating unit includes active circuit  5   d  that changes the variable discharge delay T 2 L by changing the operating current based on discharge control signal  6   a.    
         [0088]     The opposite phase delayed clock signal generating unit includes active circuit  5   b  that changes the variable non-superimposed delay T 2 N by changing the operating current based on non-superimposed control signal  6   b.    
         [0089]     If the arrangement of these logic devices  5   a,    5   b,    5   c,    5   d  is applied to the clock signal generating device  11  ( FIG. 1 ) described in the first embodiment, the timing of non-overlapping period T 1 N of clock signal φ 2  and clock signal φ 1 P can be adjusted by control signal  6   b,  the timing of bottom plate sampling period T 1 L of clock signal φ 1 P and clock signal φ 1  can be adjusted by control signal  6   a,  the timing of non-overlapping period T 2 N of clock signal φ 1  and clock signal φ 2 P can be adjusted by control signal  6   b,  and the timing of bottom plate sampling period T 2 L of clock signal φ 2 P and clock signal φ 2  can be adjusted by control signal  6   a.    
         [0090]     The non-overlapping period and bottom plate sampling period can thus be adjusted by supplying the clock signals generated by the clock signal generating device  11  using logic devices  5   a,    5   b,    5   c,    5   d  according to this second embodiment of the invention to the switched capacitor circuit shown in  FIG. 6  and  FIG. 7 . Disruption of the timing of the bottom plate sampling period and non-overlapping period can thus be avoided when accelerating the switched capacitor circuit even if there is a parasitic resistance and parasitic capacitance on the signal traces or manufacturing variations in the switched capacitor circuit. The timing can also be precisely adjusted by adjusting the current supply to the logic devices that set the bottom plate sampling period and non-overlapping period delay. More particularly, the required bottom plate sampling period and non-overlapping period can be desirably set without adjusting the transistor size or increasing the number of logic device stages. A small circuit board can therefore be used because the switched capacitor circuit can be rendered without increasing the area of the logic devices used to set the bottom plate sampling period and non-overlapping period delay.  
         [0091]     Only two control signals  6   a  and  6   b  shown in  FIG. 1  are used in this second embodiment of the invention, but four different control signals can be generated and applied separately to logic devices  5   a,    5   b,    5   c,    5   d.    
       Third Embodiment  
       [0092]     A third embodiment of the invention is described below focusing on the differences between the third embodiment and the first and second embodiments. Other aspects of the arrangement, operation, and effect of this embodiment are the same as in the first and second embodiments, and further description thereof is omitted below.  
         [0093]      FIG. 4  shows the arrangement of a signal processing device  13  using a clock signal generating device according to this third embodiment of the invention. As shown in  FIG. 4  the signal processing device  13  includes a clock signal generating device  11 , a switched capacitor circuit  10  such as described in  FIG. 6  and  FIG. 7 , and an internal system  12  that operates independently of the switched capacitor circuit  10  and clock signal generating device  11 . This internal system  12  is also called a control signal adjustment unit.  
         [0094]     The operation of the signal processing device  13  according to this third embodiment of the invention is described next.  
         [0095]     The internal system  12  first applies an analog input signal  14  to the switched capacitor circuit  10 . The switched capacitor circuit  10  operates based on the clock signals φ 1 , φ 1   p,  φ 2 , φ 2 P received from the clock signal generating device  11 , signal processes the applied analog input signal  14 , and outputs output signal  15 .  
         [0096]     The internal system  12  determines if the lengths of the bottom plate sampling period and non-overlapping period are appropriate based on the waveform of the output signal  15 . More specifically, the internal system  12  determines if an excessive offset is imposed on the signal waveform because the periods are short, or if the periods are too long. As a result, the internal system  12  outputs a period adjustment signal  16  containing information for adjusting the periods to a more appropriate length to the control signal generating unit  6  of the clock signal generating device  11 . Based on this period adjustment signal  16 , the control signal generating unit  6  supplies the control signals  6   a  and  6   b.    
         [0097]     The signal processing device  13  can therefore set the timing that minimizes the offset created by a disruption in the timing of the bottom plate sampling period and non-overlapping period. As a result, disruption of the timing of the bottom plate sampling period and non-overlapping period can thus be avoided when accelerating the switched capacitor circuit even if there is a parasitic resistance and parasitic capacitance on the signal traces or manufacturing variations in the operational amplifier using the switched capacitor circuit.  
       Fourth Embodiment  
       [0098]     A fourth embodiment of the invention is described below focusing on the differences between the fourth embodiment and the first embodiment. Other aspects of the arrangement, operation, and effect of this embodiment are the same as in the first embodiment, and further description thereof is omitted below.  
         [0099]      FIG. 5  shows the arrangement of a signal processing device  13   a  using a clock signal generating device according to this fourth embodiment of the invention. As shown in  FIG. 5  the signal processing device  13   a  includes a clock signal generating circuit  11   a,  a switched capacitor circuit  10 , an external system  17  that includes the switched capacitor circuit  10  and clock signal generating circuit  11   a,  an internal wiring pad  18  for connecting the switched capacitor circuit  10  and clock signal generating circuit  11  a by wire, external wiring pad  19 , wire  20  connecting the external wiring pad  19  and internal wiring pad  18 , external analog signal source  22 , bias voltage sources  21   a  and  21   b,  and clock signal sources  23   a  and  23   b.    
         [0100]     An analog input signal from the external analog signal source  22  is input to the switched capacitor circuit  10  through the external wiring pad  19 , wire  20 , and internal wiring pad  18 . Control signals  6   a  and  6   b  for controlling the logic device  5   a,    5   b,    5   c,    5   d  in the clock signal generating circuit  11  a and adjusting the bottom plate sampling period and non-overlapping period timing are input from bias voltage sources  21   a  and  21   b,  respectively. Clock signals CLK and ICLK for operating the clock signal generating circuit  11   a  are applied by clock signal sources  23   a  and  23   b,  respectively.  
         [0101]     The bias voltage source  21   a  is also called a discharge voltage source, and bias voltage source  21   b  is also called a non-superimposed voltage source.  
         [0102]     More specifically, the control signal generating unit  6  includes discharge voltage source  21   a  for generating and supplying discharge control signal  6   a  over a trace to the common mode delayed clock signal generating unit, a non-superimposed voltage source  21   b  for generating and supplying non-superimposed control signal  6   b  over a trace to the common mode reference clock signal generating unit, a discharge voltage source  21   a  for generating and supplying discharge control signal  6   a  over a trace to the opposite phase delayed clock signal generating unit, and a non-superimposed voltage source  21   b  for generating and supplying non-superimposed control signal  6   b  to the opposite phase reference clock signal generating unit.  
         [0103]     If the timing of the bottom plate sampling period and non-overlapping period of the clock signal generating circuit  11   a  is set in the manufacturing process, the required timing characteristic of the clock signal generating circuit  11   a  can be fixed by connecting specific bias voltage sources  21   a  and  21   b  by wire  20  as shown in this fourth embodiment. The bottom plate sampling period and non-overlapping period timing that is best for the switched capacitor circuit  10  can therefore be achieved.  
         [0104]     As described above, disruption of the timing of the bottom plate sampling period and non-overlapping period can thus be avoided when accelerating the switched capacitor circuit even if there is a parasitic resistance and parasitic capacitance on the signal traces or manufacturing variations in the operational amplifier using the switched capacitor circuit. The required bottom plate sampling period and non-overlapping period can also be set without adjusting the transistor size or increasing the number of logic device stages. A small circuit board can therefore be used because the switched capacitor circuit can be rendered without increasing the area of the logic devices used to set the bottom plate sampling period and non-overlapping period delay.  
         [0105]     Although the present invention has been described in connection with the preferred embodiments thereof with reference to the accompanying drawings, it is to be noted that various changes and modifications will be apparent to those skilled in the art. Such changes and modifications are to be understood as included within the scope of the present invention as defined by the appended claims, unless they depart therefrom.