Abstract:
In a data processing apparatus, a receiver receives pause control data signals from other data processing apparatuses. Each of the pause control data signals includes identification data of one of the other data processing apparatuses and a transmission interrupting time period. The identification data associated with the transmission interrupting time period is stored in a memory. Also, when a time corresponding to the transmission interrupting time period has passed, the identification data is removed from the memory. Transmission of data to one of the other data processing apparatuses having the identification data stored in the memory is interrupted.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a data processing apparatus such as a local area network (LAN) connection apparatus used in a full duplex Ethernet LAN system. 
     2. Description of the Related Art 
     In a full duplex Ethernet LAN system where a plurality of LAN connection apparatuses (units) are connected by LANs, congestion preventing means is provided in each of the LAN connection units (see: IEEE P802.3X, “Specification for 802.3 Full Duplex Operation”, pp. 100-116, Jun. 4, 1996). That is, when congestion occurs in one LAN connection unit, this LAN connection unit generates a pause packet and transmits it to the other LAN connection units. Then, the other LAN connection units interrupt the transmission of data for a pause time period indicated by the pause packet. As a result, the congestion of the above-mentioned LAN connection unit can be dissolved. This will be explained later in detail. 
     In the above-described prior art LAN system, however, when one LAN connection unit transmits a pause packet simultaneously to a plurality of other LAN connection units, the transmission of packets is interrupted in the plurality of LAN connection units. In this case, the transmission of packets having destinations to the LAN connection units where congestion does not occur may be interrupted, which retards the entire communication of the LAN system. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to dissolve the congestion state of a data processing apparatus without retarding the entire communication of a data processing system. 
     According to the present invention, in a data processing apparatus, a receiver receives pause control data signals from other data processing apparatuses. Each of the pause control data signals includes identification data of one of the other data processing apparatuses and a transmission interrupting time period. The identification data associated with the transmission interrupting time period is stored in a memory. Also, when a time corresponding to the transmission interrupting time period has passed, the identification data is removed from the memory. Transmission of data to one of the other data processing apparatuses having the identification data stored in the memory is interrupted. 
     Thus, the transmission of data only for the data processing apparatus where congestion occurs is interrupted. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more clearly understood from the description as set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein: 
     FIG. 1 is a block circuit diagram illustrating a prior art data processing system; 
     FIG. 2 is a detailed block circuit diagram of the data processing unit of FIG. 1; 
     FIG. 3 is a flowchart for explaining the operation of the pause processing section of FIG. 2; 
     FIG. 4 is a block circuit diagram of the data processing apparatus according to the present invention; 
     FIG. 5 is a structure diagram of the pause control CAM of FIG. 4; 
     FIGS. 6 and 7 are flowcharts for explaining the operation of the pause processing section of FIG. 4; and 
     FIG. 8 is a flowchart for explaining the operation of the transmitting MAC section of FIG.  4 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Before the description of the preferred embodiment, a prior art data processing system will be explained with reference to FIGS. 1,  2  and  3 . 
     In FIG. 1, which illustrates a prior art LAN system as a data processing system, a plurality of LAN connection units  1 - 1 ,  1 - 2 , . . . as data processing units are connected by LANs  2 - 1 ,  2 - 2 , . . . as communication networks to a LAN concentration unit. 
     In FIG. 2, which is a detailed block circuit diagram of the LAN connection unit  1 - 1  of FIG. 1, reference numeral  11  designates a transmitter for transmitting various packets to the other LAN connection units, and  12  designates a receiver for receiving various packets from the other LAN connection units. 
     The receiver  12  is connected to a transmission interruption requesting circuit (not shown). That is, when congestion occurs in the receiver  12 , the transmission interruption requesting circuit generates a pause control packet including a pause timer value. The pause control packet is transmitted by the transmitter  11  to all the other LAN connection units. 
     The receiver  12  is connected via a receiving medium access control (MAC) section  13 , a pause processing section  14  and a receiving buffer supervising section  15  including a first-in first-out (FIFO)  15   a  to a system bus  16 . The pause processing section  14  has a pause packet detector  14   a,  a pause timer  14   b  and a status indicator  14   c.    
     Also, a content addressable memory (CAM)  17  for storing multicast addresses is connected between the system bus  16  and the receiving MAC section  13 . 
     Further, a host processor  18  and a random access memory (RAM)  19  are connected to the system bus  16 . The RAM  19  temporarily stores transmitting packets. The host processor  18  transmits the packets stored in the RAM  19  to a transmitting buffer supervising section  20  including a FIFO  20   a  in accordance with the value of the status indicator  14   c  of the pause processing section  14 . Then, the transmitting buffer supervising section  20  transmits the packets via a transmitting MAC section  21  to the transmitter  11 . 
     In addition, a control/sequence section  22  is connected to the receiving MAC section  13 , the receiving buffer supervising section  15 , the system bus  16 , the transmitting buffer supervising section  20  and the transmitting MAC section  21 . 
     The operation of the pause processing section  14  of FIG. 2 will be explained next with reference to a flowchart as shown in FIG.  3 . The pause processing routine of FIG. 3 is started when the pause packet detector  14   a  detects a pause packet. 
     First, at step  301 , it is determined whether or not a packet is currently being transmitted from the LAN connection unit  1 - 1 . Note that the pause processing section  14  can carry out the determination at step  301  by sending a query via the receiving MAC section  13  to the control/sequence section  22 . As a result, if a packet is not currently being transmitted, the control proceeds to step  302 . Otherwise, the control waits for the transmission of the packet to complete. 
     Next, at step  302 , it is determined whether or not a destination address set in the detected pause packet is one of the multiaddresses stored in the CAM  17 . Note that the pause processing section  14  can recognize the multiaddress stored in the CAM  17  via the receiving MAC section  13 . Only if the destination address is one of the multiaddresses stored in the CAM  17 , i.e., the CAM  17  is hit by the destination address, does the control proceed to step  303 . Otherwise, the control proceeds directly to step  305 . 
     At step  303 , the pause processing section  14  sets a pause timer value included in the detected pause packet in the pause timer  14   b  which is in this case a down counter. Then, the pause timer  14   b  is operated. 
     At step  304 , the pause processing section  14  sets the status indicator  14   c.  That is, the output of the status indicator  14   c  is caused to be “1”. 
     Then, the routine of FIG. 3 is completed by step  305 . 
     When a time corresponding to the pause timer value has passed, the pause timer  14   b  generates a carry signal and transmits it to the status indicator  14   c.  As a result, the status indicator  14   c  is reset, i.e., the output of the status indicator  14   c  is caused to be “0”. 
     Thus, the output of the status indicator  14   c  is maintained at “1” for the pause time set in the pause packet. 
     The host processor  18  monitors the status indicator  14   c.  As a result, when the output of the status indicator  14   c  is “1”, the host processor  18  interrupts the transmission of packets from the RAM  19  to the transmitting buffer supervising section  20 . Therefore, the transmission of packets is temporarily interrupted, congestion in a LAN connection unit such as  1 - 2  can be dissolved. Then, after the output of the status indicator  14   c  is “0”, the host processor restarts the transmission of packets from the RAM  19  to the transmitting buffer supervising section  20   a.    
     Note that, if the output of the status indicator  14   c  is “1”, the host processor  18  can directly stop the operation of the transmitting buffer supervising section  20 . 
     In the LAN system of FIGS. 1,  2  and  3 , however, when one LAN connection unit such as  1 - 2  transmits a pause packet simultaneously to a plurality of other LAN connection units, the transmission of packets is interrupted in the plurality of LAN connection units. In this case, the transmission of packets having destinations to even the LAN connection units where congestion does not occur may be interrupted, which retards the entire communication of the LAN system. 
     In FIG. 4, which illustrates an embodiment of the present invention, the pause processing section  14  of FIG. 2 is replaced by a pause processing section  14 ′. The pause processing section  14 ′ includes a timer memory  14   d  instead of the pause timer  14   b  and the status indicator  14   c  of FIG.  2 . The timer memory  14   d  has registered communication addresses ADD 1 , ADD 2 , . . . , ADDn of the other LAN connection units connected to the LAN concentration unit  3  associated with pause timer value storing areas. Also, a pause control CAM  23  is connected between the pause processing section  14 ′ and the transmitting MAC section  21 . 
     As shown in FIG. 5, the pause control CAM  23  has pause requesting origination address storing areas. In this case, the number of the pause requesting origination address storing areas is the number of the other LAN connection units connected to the LAN concentration unit  3 , i.e., the number of the registered communication addresses ADD 1 , ADD 2 , . . . , ADDn of the timer memory  14   d.    
     The operation of the pause processing section  14 ′ of FIG. 4 will be explained next with reference to a flowchart as shown in FIG.  6 . The pause processing routine of FIG. 6 is started when the pause packet detector  14   a  detects a pause packet. 
     First, at step  601 , it is determined whether or not a packet is currently being transmitted from the LAN connection unit  1 - 1 . Note that the pause processing section  14 ′ can carry out the determination at step  601  by sending a query via the receiving MAC section  13  to the control/sequence section  22 . As a result, if a packet is not currently being transmitted, the control proceeds to step  602 . Otherwise, the control waits for the transmission of the packet to complete. 
     Next, at step  602 , it is determined whether or not a destination address set in the detected pause packet is one of the multiaddresses stored in the CAM  17 . Note that the pause processing section  14 ′ can recognize the multiaddress stored in the CAM  17  via the receiving MAC section  13 . Only if the destination address is one of the multiaddresses stored in the CAM  17 , i.e., the CAM  17  is hit by the destination address, does the control proceed to step  603 . Otherwise, the control proceeds directly to step  605 . 
     At step  603 , the pause processing section  14 ′ stores a pause timer value included in the detected pause packet in the pause timer memory  14   d.  In this case, the pause timer value is stored in one of the pause timer value storing areas indicated by the communication address included in the detected pause packet. 
     Note that all the contents of the pause timer value storing areas are decremented by 1 for every predetermined time period. Therefore, when the content of one of the pause timer value storing areas becomes negative, the pause timer memory  14   d  generates a carry signal. 
     Next, at step  604 , the pause processing section  14 ′ stores the communication address included in the detected pause packet in the pause control CAM  23 . 
     Then, the routine of FIG. 6 is completed by step  605 . 
     When the pause timer memory  14   d  generates a carry signal, the pause processing section  14 ′ carries out an interrupt operation as shown in FIG.  7 . That is, at step  701 , the pause processing section  14 ′ removes the communication address corresponding to the pause timer value storing area that has issued the carry signal. Then, the routine of FIG. 7 is completed by step  702 . 
     The operation of the transmitting MAC section  21  of FIG. 4 will be explained next with reference to a flowchart as shown in FIG.  8 . 
     First, at step  801 , it is determined whether there is a packet to be transmitted from the LAN connection unit  1 - 1 . Only if there is such a packet, does the control proceed to step  802 . Otherwise, the control proceeds directly to step  802 . 
     At step  802 , it is determined whether or not a destination communication address included in the packet to be transmitted exists in the pause control CAM  23 , i.e., whether the pause control CAM  23  is hit or mishit by the destination communication address. As a result, only if the pause control CAM  23  is mishit, does the control proceed to step  803  which transmits the packet to the transmitter  11 . Otherwise, the control waits for the pause control CAM  23  to be mishit by the destination communication address. 
     Then, the routine of FIG. 8 is completed by step  804 . 
     Thus, the transmission of packets having destinations to only LAN connection units where congestion occurs is temporarily interrupted. In other words, when one of the LAN connection units issues a pause control packet, transmission of packets to the one of the LAN connection units is interrupted, while transmission of packets to the other LAN connection units is not interrupted. This enhances the communication of the entire LAN system. 
     As explained hereinabove, according to the present invention, since transmission of packets only for LAN connection units where congestion occurs is interrupted, the communication of an entire data processing (LAN) system can be enhanced.