Abstract:
A driving circuit for a power MOSFET includes a first switch, a second switch, a third switch and a fourth switch. The first switch is connected to a first node, a second node and a first power end. The first power end supplies a first voltage. The second switch is connected to the first node, the second node and a first ground end. The third switch is connected to the second node, a third node and the first power end. The fourth switch is connected to the second node, the third node and a second ground end. The power MOSFET is connected to the third node and a PWM signal is inputted into the first node. The PWM signal has a second voltage lower than the first voltage.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The invention relates to a driving circuit for a power metal-oxide-semiconductor field-effect transistor (MOSFET) and, more particularly, to a driving circuit capable of reducing conduction loss and switching loss of a power MOSFET. 
         [0003]    2. Description of the Prior Art 
         [0004]    Referring to  FIG. 1 ,  FIG. 1  is a schematic diagram illustrating a boost circuit  1  of the prior art. The boost circuit  1  comprises an inductor  10  a Schottky diode  12 , a loading  14  a pulse width modulation (PWM) signal generating unit  16  and a power MOSFET  18 . It should be noted that the connecting relation between the aforesaid components is shown in  FIG. 1  and the principle thereof can be achieved by one skilled in the art, so it will not be depicted here again. 
         [0005]    As shown in  FIG. 1 , when the loading  14  is overload, the power MOSFET  18  should be able to be adapted to high power, so as to supply high voltage for driving the overload. However, since the power MOSFET  18  can endure high voltage, a drain-source on-state resistance (Rds(on)) and a parasitic capacitance of the power MOSFET  18  will be large, so that conduction loss and switching loss will get large during power conversion. Consequently, the efficiency of power conversion will get worse while the power loss increase. 
         [0006]    Furthermore, U.S. Pat. No. 7,459,945 (hereinafter &#39;945 patent) discloses a gate driving circuit disposed between a power MOSFET and a PWM signal and used for improving driving capability of the power MOSFET and reducing loss. The gate driving circuit of &#39;945 patent comprises a switching control circuit, four switches, four Schottky diodes and an inductor. &#39;945 patent utilizes the switching control circuit to control the four switches so as to charge/discharge the inductor. In other words, the switching control circuit, which is used for timing control, and the inductor, which is used for storing power, are necessary for &#39;945 patent to improve the efficiency of power conversion of the power MOSFET. However, the switching control circuit and the inductor will increase circuit size and the inductor will cause electromagnetic interference (EMI) while being charged or discharged. 
       SUMMARY OF THE INVENTION 
       [0007]    Therefore, one objective of the invention is to provide a driving circuit for a power MOSFET. The driving circuit is disposed between a PWM signal generating unit and the power MOSFET. The driving circuit is capable of reducing conduction loss and switching loss of the power MOSFET, so as to solve the aforesaid problems. 
         [0008]    According to one embodiment, the driving circuit of the invention comprises a first switch, a second switch, a third switch and a fourth switch. The first switch is connected to a first node, a second node and a first power end, and the first power end supplies a first voltage. The second switch is connected to the first node, the second node and a first ground end. The third switch is connected to the second node, a third node and the first power end. The fourth switch is connected to the second node, the third node and a second ground end. 
         [0009]    In this embodiment, a power MOSFET is connected to the third node and a PWM signal is inputted into the first node. The PWM signal has a second voltage lower than the first voltage. When the PWM signal is high, the first and fourth switches are turned off and the second and third switches are turned on, so that the first voltage is outputted to the third node through the third switch, so as to turn on the power MOSFET. On the other hand, when the PWM signal is low, the first and fourth switches are turned on and the second and third switches are turned off, so that the power MOSFET discharges through the fourth switch and the second ground end. 
         [0010]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a schematic diagram illustrating a boost circuit of the prior art. 
           [0012]      FIG. 2  is a schematic diagram illustrating a driving circuit according to one embodiment of the invention. 
           [0013]      FIG. 3  is a timing diagram illustrating waveforms of each signal within the driving circuit. 
           [0014]      FIG. 4  is a simulation waveform diagram illustrating the pulse signal at the gate of the power MOSFET. 
           [0015]      FIG. 5  is a schematic diagram illustrating the driving circuit of the invention applied to a boost circuit. 
           [0016]      FIG. 6  is a schematic diagram illustrating the driving circuit of the invention applied to an LED backlight driving circuit. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    Referring to  FIG. 2 ,  FIG. 2  is a schematic diagram illustrating a driving circuit  30  according to one embodiment of the invention. As shown in  FIG. 2 , the driving circuit  30  is connected between a PWM signal generating unit  32  and a power MOSFET  34 . The driving circuit  30  comprises a first switch  300 , a second switch  302 , a third switch  304  and a fourth switch  306 . In this embodiment, the first and third switches  300  and  304  can be P-type transistors and the second and fourth switches  302  and  306  can be N-type transistors. In other words, an inverter consists of the first and second switches  300  and  302  and another inverter consists of the third and fourth switches  304  and  306 . 
         [0018]    The first switch  300  has a gate G 1  connected to a first node N 1 , a source S 1  connected to a second node N 2 , and a drain D 1  connected to a first power end VDD. The second switch  302  has a gate G 2  connected to the first node N 1 , a drain D 2  connected to the second node N 2 , and a S 2  source connected to a first ground end GND 1 . The third switch  304  has a gate G 3  connected to the second node N 2 , a source S 3  connected to a third node N 3 , and a drain D 3  connected to the first power end VDD. The fourth switch  306  has a gate G 4  connected to the second node N 2 , a drain D 4  connected to the third node N 3 , and a source S 4  connected to a second ground end GND 2 . 
         [0019]    In this embodiment, the power MOSFET  34  is also an N-type transistor. The power MOSFET  34  has a gate G 5  connected to the third node N 3 , a drain D 5  connected to a second power end VCC, and a source S 5  connected to a third ground end GND 3 . Furthermore, the PWM signal generating unit  32  is connected to the first node N 1 , so a PWM signal generated by the PWM signal generating unit  32  can be inputted from the first node N 1  to the driving circuit  30 . 
         [0020]    Referring to  FIG. 3 ,  FIG. 3  is a timing diagram illustrating waveforms of each signal within the driving circuit  30 . At time t 1  to t 2 , the PWM signal is high at the first node N 1 , so the first switch  300  is turned off and the second switch  302  is turned on, so that the PWM signal is converted from high to low at the second node N 2 . Since the second node N 2  is low, the third switch  304  is turned on and the fourth switch  306  is turned off, so that the PWM signal is converted from low to high at the third node N 3 . At this time, the first voltage supplied by the first power end VDD will be outputted to turn on the power MOSFET  34  through the third switch  304  and the third node N 3 . 
         [0021]    In this embodiment, the first voltage (e.g. 5V) supplied by the first power end VDD is larger than a second voltage (e.g. 3.3V) of the PWM signal. Accordingly, the driving circuit  30  of the invention can amplify the pulse of the PWM signal so as to amplify a gate-to-source voltage (V GS ) of the power MOSFET  34 . Therefore, the number of charge carriers of the power MOSFET  34  will increase (i.e. the number of channel counts will increase), so as to increase conductance or reduce resistance. Consequently, the conduction loss is reduced and the efficiency of power conversion is enhanced. It should be noted that the first voltage has to be larger than the second voltage but the first and second voltages are not limited to the aforesaid 5V and 3.3V. The first and second voltages can be determined based on practical applications. 
         [0022]    At time t 2  to t 3 , the PWM signal is low at the first node N 1 , so the first switch  300  is turned on and the second switch  302  is turned off, so that the PWM signal is converted from low to high at the second node N 2 . Since the second node N 2  is high, the third switch  304  is turned off and the fourth switch  306  is turned on, so that the PWM signal is converted from high to low at the third node N 3 . At this time, the power MOSFET  34  can discharge through the fourth switch  306  and the second ground end GND 2 . 
         [0023]    The principle of the invention is depicted in detail in the above when the PWM signal is high or low during one operating cycle and the follow-up procedure can be obtained by the same manner. Therefore, it will not be depicted here again. 
         [0024]    Referring to  FIG. 4 ,  FIG. 4  is a simulation waveform diagram illustrating the pulse signal at the gate G 5  of the power MOSFET  34 . As shown in  FIG. 4 , the real line A represents a simulation waveform after using the driving circuit  30  of the invention, and the broken line B represents another simulation waveform before using the driving circuit  30  of the invention. It is obvious that the driving circuit  30  of the invention can reduce charging/discharging time of the parasitic capacitance within the power MOSFET  34 , wherein the power MOSFET  34  discharges through the fourth switch  306  and the second ground end GND 2 . Therefore, the switching loss can be reduced and then a square waveform of the pulse signal will be obtained at the gate G 5  of the power MOSFET  34 , as the real line A shown in  FIG. 4 . 
         [0025]    Referring to  FIG. 5 ,  FIG. 5  is a schematic diagram illustrating the driving circuit  30  of the invention applied to a boost circuit  3 . The boost circuit  3  comprises the driving circuit  30 , the PWM signal generating unit  32 , the power MOSFET  34 , an inductor  36  a Shottky diode  38  and a loading  40 , wherein the loading is overload. As shown in  FIG. 5 , the driving circuit  30  is connected between the PWM signal generating unit  32  and the power MOSFET  34 . The principle of the driving circuit  30  is mentioned in the above and will not be depicted here again. Furthermore, the connecting relation between the aforesaid components is shown in  FIG. 5  and the principle thereof can be achieved by one skilled in the art, so it will not be depicted here again. 
         [0026]    Referring to  FIG. 6 ,  FIG. 6  is a schematic diagram illustrating the driving circuit  30  of the invention applied to an LED backlight driving circuit  5 . The LED backlight driving circuit  5  comprises the driving circuit  30 , the PWM signal generating unit  32 , the power MOSFET  34 , the inductor  36 , the Schottky diode  38 , a plurality of LED backlight modules  50  and a current matching unit  52 , wherein the LED backlight modules  50  are connected with each other in series and in parallel and equivalent to the loading  40  shown in  FIG. 5 . As shown in  FIG. 6 , the driving circuit  30  is connected between the PWM signal generating unit  32  and the power MOSFET  34 . The principle of the driving circuit  30  is mentioned in the above and will not be depicted here again. Furthermore, the connecting relation between the aforesaid components is shown in  FIG. 6  and the principle thereof can be achieved by one skilled in the art, so it will not be depicted here again. 
         [0027]    Though the driving circuit  30  shown in  FIG. 2  utilizes two inverters to reduce the conduction loss and switching loss of the power MOSFET  34 , the invention is not limited to two inverters. If the frequency of the PWM signal gets high or the aforesaid first, second, third and/or fourth switch(es)  300 - 306  are/is not ideal, the invention can install more than two inverters (e.g. four, six and so on) in the driving circuit  30 , so as to reduce the conduction loss and switching loss of the power MOSFET  34  more effectively and then obtain a square waveform at the gate G 5  of the power MOSFET  34 . 
         [0028]    Compared to the prior art, the driving circuit of the invention consists of four switches and utilizes the PWM signal to control the four switches immediately, so as to reduce the conduction loss and switching loss of the power MOSFET effectively. The structure of the driving circuit of the invention is simple and the circuit size will not increase too much. 
         [0029]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.