Abstract:
Surface dimension and footprint dimension values are determined by scanning a printed circuit board with a laser. Exposed substrate parts of the printed circuit board fluoresce significantly, emitting detectable luminance, while conductors do not. Conductors reflect the laser light much more strongly than the exposed substrate, especially at the substantially flat part of the top surface. Luminescence and reflectivity collectors provide signals indicative of the footprint and surface dimensions. This cross-sectional information is used in making adjustment determinations in the manufacturing process, and also decisions relating to repair or discard operations.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application claims the benefit of U.S. Provisional Application No. 60/237,803, filed Oct. 4, 2000. Application Ser. No. 60/237,803 is incorporated herein by reference in its entirety. 
     
    
     
       FIELD OF THE INVENTION  
         [0002]    This description generally relates to the field of electrical circuit inspection. More particularly, the field of interest involves systems and methods for fabricating and inspecting electrical circuit conductors in electrical circuits.  
         BACKGROUND OF THE INVENTION  
         [0003]    The production of printed circuit boards is an expensive undertaking, and many extraordinary measures are routinely taken to ensure the highest possible production quality. Automated optical inspection (AOI) harnesses the power, speed, and reliability of computer technology to assist with the task of inspection of printed circuit boards for defects. Existing automated optical inspection (AOI) systems, such as the PC-14 Micro™ and Blaser™ AOI systems, are available from Orbotech of Yavne, Israel.  
           [0004]    Existing AOI systems that just inspect conductor width, however, do not provide information for evaluating the cross-section of the conductors.  
           [0005]    As used herein, the term “printed circuit board” will be understood to refer in general to any electrical circuit on any substrate, including printed circuit boards, multi-chip modules, ball grid array substrates, integrated circuits and other suitable electrical circuits.  
         SUMMARY OF THE INVENTION  
         [0006]    A general aspect of the present invention relates to employing a combination of inspection inputs or attributes for the width of a conductor along a top surface and for the width of a conductor along a bottom surface thereof to determine an inspection attribute that may indicate the presence of a defect in a conductor or in a manufacturing process used to fabricate an electrical circuit.  
           [0007]    A more particular aspect of the present invention relates to an automated optical inspection system operative to inspect electrical circuits to determine the width of a top surface of conductors forming the circuit at a multiplicity of locations, the width of a bottom surface of conductors forming the circuit at a multiplicity of locations, and the slope of the side walls of conductors, or other defects in the shape of conductor side walls, forming the circuit at a multiplicity of locations.  
           [0008]    Another more particular aspect of the present invention relates to a system and method for optically inspecting electrical circuits and calculating therefrom impedance values for conductors forming the electrical circuit.  
           [0009]    Another more particular aspect of the present invention relates to a method of producing printed circuit boards, whereby production and/or fabrication process control decisions (such as whether a defect exists in a conductor or in a manufacturing process) are based on inspection outputs indicative of the conductor dimension along the top surface and bottom surface respectively, or the slope of the sides of conductors.  
           [0010]    The above and other aspects of the invention are achieved by a system, described in detail below, in which a laser scanner is provided to scan a laser beam across an electrical circuit being inspected. The laser produces a beam which has sufficient energy to cause fluorescence (also referred to herein as luminescence) of the substrate on which conductors are formed. In addition, the beam is reflected by copper conductors which typically have a higher work function than the substrate and do not fluoresce under illumination of the laser beam. The reflected and fluorescent light is collected and the respective intensities of the reflective and fluorescent light are analyzed. Fluorescent light provides an indication of the width of a conductor along its bottom surface, while the reflected light (another attribute) provides an indication of the width of the conductor along its top surface. Comparison of the respective widths of the bottom surfaces and top surfaces of the conductors provides an indication of the slope of the side-walls of a conductor.  
           [0011]    The top and bottom dimensions can be used in combination to provide an inspection attribute for a single point or at various sampling points along the length of conductors, and can be used for various analyses of characteristics of the electrical circuit. For example, information about the slope of the side walls of conductors may be used to calculate a cross sectional dimension of an electrical circuit at various sampling points which can be used to derive an impedance value for a conductor. Additionally, statistical information about uniformity in the respect widths of conductors along their top and bottom surfaces may be used to indicate various flaws in etching processes.  
           [0012]    The above and other aspects of the invention will be more fully understood and appreciated when read in the light of the detailed description provided below, and the enclosed drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    [0013]FIG. 1 is a functional block diagram of an automated optical inspection system operative to inspect electrical circuits for defects in accordance with a preferred embodiment of the present invention.  
         [0014]    [0014]FIG. 2 is a simplified representation of a conductor on a substrate, shown in cross-section.  
         [0015]    [0015]FIG. 3 shows a signal generated in correspondence to an amount of detected luminescent light generated when the conductor and substrate of FIG. 2 are scanned with a laser.  
         [0016]    [0016]FIG. 4 shows a signal generated in correspondence to an amount of detected reflective light generated as in FIG. 3.  
         [0017]    [0017]FIG. 5 is a report of distribution of top surface and bottom surface dimension of conductors in an electrical circuit in accordance with a preferred embodiment of the present invention.  
         [0018]    [0018]FIG. 6 shows, in highly simplified schematic form, a system for manufacturing electrical circuits according to an embodiment of the invention.  
         [0019]    [0019]FIG. 7 is a flow diagram for explaining the processing of the system shown in FIG. 6.  
         [0020]    [0020]FIG. 8 shows, in highly simplified schematic form, another system for manufacturing electrical circuits according to an embodiment of the invention.  
         [0021]    [0021]FIG. 9 is a flow diagram for explaining the processing of the system shown in FIG. 8. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0022]    Using the above-identified figures, the invention will now be described with respect to various embodiments of the invention. Although many specificities will be mentioned, it must be emphasized that the scope of the invention is not be taken to be that of only the embodiments described herein, but should be construed in accordance with the claims appended below.  
         [0023]    In FIG. 1, automated optical inspection system  10  is operative to inspect electrical circuits for defects in accordance with an embodiment of the present invention.  
         [0024]    AOI system  10  suitably is a V- 300  automated optical inspection system available from Orbotech Ltd., of Yavne Israel. In FIG. 1, reference numeral  12  indicates a source of radiant energy; reference numeral  14  indicates a beam of radiant energy; reference numeral  16  indicates a portion of a printed circuit board substrate under inspection; reference numeral  18  indicates a conductor; reference numeral  20  indicates a substrate on which the conductor  18  is disposed; reference numeral  22  indicates a device such as a rotating polygonal mirror that scans the beam  14  across the printed circuit board  16 ; reference numeral  24  indicates a luminescence (also referred to herein as fluorescence) collector; and reference numeral  34  indicates a reflectance collector.  
         [0025]    Operation of certain aspects of system  10  are described in U.S. Pat. No. 5,216,479, and are readily grasped by those familiar with this field. Thus, a highly detailed description of the operation of AOI system  10  is omitted here in favor of a brief overview.  
         [0026]    The source of radiant energy  12  may be a laser, such as any suitable CW or solid state laser, and preferably is a He:Cd laser, available from Kimmon Electric Company of Japan, producing coherent light in the blue spectrum, at about 442 nm. Substrate  20  may, e.g., be a fiberglass or organic substrate.  
         [0027]    The beam  14  is scanned across the circuit portion  16 , and the collectors  24  and  34  are kept operationally positioned to collect their respective types of light at the point at which the beam  14  impinges on the circuit portion  16 . To this end, it is convenient if the collectors  24  and  34  are linear in a main scanning direction of the beam  14 , although this is not essential. The collectors  24  and  34  are shown in FIG. 1, in highly simplified form, as point collectors instead of linear collectors for the sake of ease of illustration.  
         [0028]    It will be appreciated that the collectors, sensors, and processors mentioned above may together be thought of as an inspection functionality.  
         [0029]    [0029]FIG. 2 shows a cross section of a conductor  18  on a substrate  20 . Reference numeral  35  indicates an upper, substantially flat surface of conductor  18 . The upper surface  35  of conductor  18  has shoulders  19  on either side of it, sloping down in some shape to the substrate  20 . Reference numeral  17  indicates a lower, bottom surface of conductor  18 .  
         [0030]    The width of conductor  18  at its top surface  35  may be referred to hereinafter as a top surface width, or top width, or also a surface dimension.  
         [0031]    The width of conductor  18  at its bottom surface  17  may be referred to hereinafter as a bottom surface width, or bottom width, or also as a footprint dimension.  
         [0032]    When the spot of beam  14  impinges on the substrate  20  at a location free of conductor  18 , a localized part of the substrate fluoresces, giving off luminescent light collected by luminescence collector  24  and sensed by luminescence sensor  26 . At such a location, the reflected light given off by substrate  20  is very low because substrate  20  tends to diffuse the light, and a substantially zero value is output by reflectance sensor  36 .  
         [0033]    When the spot of beam  14  impinges on the substrate  20  at a location where a conductor  18  is present, the conductor does not fluoresce because the work function of the conductor  18  is greater than required to release a photon, due to the quantum effect of illumination by beam  14 . Thus, luminescence sensor  26  outputs a substantially zero value. Conductor  18 , however, is relatively reflective. Reflectance collector  34  therefore collects reflectance and reflectance sensor  36  outputs a value above zero at such a point.  
         [0034]    [0034]FIG. 3 shows a luminescence signal  30  produced by luminescence sensor  26 , indicative of an amount of luminescence emitted by the surface as a beam spot scans over the cross-section of conductor  18  shown. When the beam spot is over the substrate only, the luminescence has a non-zero value. As the spot begins to cross from the exposed substrate to the shoulder portion  19  of the conductor  18 , the detected luminescence decreases rapidly. It will be appreciated that, in the example shown, the beam spot has a finite width, and so as it moves to the shoulder portion  19  from the exposed substrate, the amount of exposed substrate being impinged upon by the beam spot decreases to zero, as does the amount of detectable luminescence. It will also be appreciated that the inspection is not strictly limited to only the conductor itself, but includes also the exposed substrate in the area. The conductor and the exposed substrate in the area may be referred to, for linguistic convenience, as a “conductor location, ” and a conductor location may comprise several pixels in the digital map  31 .  
         [0035]    [0035]FIG. 4 shows a reflectance signal  40  output by reflectance sensor  36 , indicative of an amount of reflectance emitted by the surface as a beam spot scans over the cross-section of conductor  18  shown. When the beam spot is over the substrate only, the reflectance has a substantially zero value. As the spot begins to cross from the exposed substrate to the shoulder portion  19  of the conductor  18 , the detected reflectance increases. Depending on the angle of incidence, the reflectance may reach a maximum value when the spot is impinging on only the top surface  35 , as shown in FIG. 4. When the spot begins to move from the top surface  35  to the shoulder portion  19 , the amount of reflectance that is collected by the reflectance collector  34  decreases quickly, but is greater than zero. This is because the angle of the shoulder portion  19  tends to reflect some of the light in a direction away from the reflectance collector  34 .  
         [0036]    In operation, the sensor  26  may include analogue to digital circuitry processing luminance signal  30  to produce a digital image or map  31  (FIG. 1) of luminance values at selected locations on the surface of substrate  20 . Digital image  31  is supplied to bottom width processor  28 . Likewise, the reflectance sensor  36  may include analogue to digital circuitry processing reflectance signal  40 , to produce a digital image or map  41  (FIG. 1) of reflectance values at selected locations on the surface of substrate  20 .  
         [0037]    The bottom width processor  28  calculates a footprint dimension of one or more conductors  18  at selected conductor locations therealong. This footprint dimension, as can be seen from FIG. 1, is based on the luminance signal  30 . The top width processor  38  calculates a top surface dimension of one or more conductors  18  at selected conductor locations therealong. This top surface dimension, as can be seen from FIG. 1, is based on the reflectance signal  30 .  
         [0038]    The respective outputs of bottom width processor  28  and top width processor  38  may be thought of as different attributes of the conductor, and are provided to an analyzer  42 , which may be operative on several modes. In one mode of operation, analyzer  42  calculates a cross section configuration of conductors based on the respective width dimensions measured for the top surface  35  and bottom surface  32  respectively of conductors  18 . Analyzer  42  may also be thought of as an attribute analyzer  
         [0039]    In another mode of operation, analyzer  42  derives the slope of side walls of conductors  18 , at one or more locations along a conductor, from the respective top surface width and bottom surface widths of conductors  18  at those locations.  
         [0040]    In another mode of operation, analyzer  42  analyzes a distribution of top surface widths and of bottom surface widths of conductors disposed along all or part of the surface of substrate  20 . Analysis of the distribution of top widths and bottom widths provides information which can be used to control etching processes. In a system configuration enabling this mode of operation, a histogram generator  44  may be included in cross section configuration analyzer  42 . Reference is made to FIG. 5 which is a pictorial illustration of a report of the distribution of top surface and bottom surface dimensions of conductors in an electrical circuit in accordance with an embodiment of the present invention.  
         [0041]    As seen in FIG. 5, histogram generator  44  produces a statistical report of the respective width distribution of top surfaces and bottom surfaces for predetermined sampling points along selected conductors. From the histogram, an average top surface width and an average bottom surface width may be determined, along with other useful statistical calculations. These calculations, and the difference between the top and bottom dimensions, are indicative of a shape of conductors, including a slope of conductor side walls. It will be appreciated that information relating to the shape of conductors is useful for understanding and improving photo-lithography and/or etching processes that are employed in manufacturing printed circuit boards.  
         [0042]    Moreover, information relating to the shape of conductors may be employed, for example, to calculate a nominal impedance of conductors. The nominal impedance may be calculated in a manner that will be readily grasped, since impedance is a function of the cross sectional dimension of a conductor.  
         [0043]    The cross sectional shape of the conductor can be approximated in various ways, once the surface and footprint dimensions have been determined. For example, it could be assumed that the shoulders were constituted by straight lines, and that the cross sectional shape was a trapezoid. Thus, the cross sectional area of the conductor (and hence, impedance) could be computed in a simplified manner.  
         [0044]    Another use of information relating to the cross sectional shape of conductors is to control photolithography and/or etching processes in order to obtain conductors having an optimized shape. Ideally, the top surface dimension  35  of conductors  18  should be slightly smaller than the bottom surface dimension  17  in order to maximize the usage of space along the surface of a printed circuit board substrate  20 . Thus if the distribution of top surface width dimensions is too small relative to the distribution of bottom surface width dimensions, then impedance problems are likely to occur since statistically some portions of conductors are likely to have an insufficient volume for efficiently carrying charge. Conversely, if the distribution of top surface width dimensions of conductors is too close relative to the distribution of bottom surface width dimensions, then shoulders  19  (FIG. 2) will typically be bowed inwardly in an exaggerated manner and there will be a high likelihood of cuts along conductors.  
         [0045]    It is thus appreciated that analysis of a width distribution report of top width dimensions and bottom width dimensions, as seen in FIG. 5, is useful in adjusting photolithography and/or etching processes in order to optimize the relative dimensions of top and bottom surfaces of conductors  18 .  
         [0046]    It will be appreciated that the report shown in FIG. 5 is just one possible example of a report  46  that may be generated by the cross section configuration analyzer  42 . For example, a report  46  may include an indication of top and bottom width dimensions of conductors at various locations along a conductor.  
         [0047]    [0047]FIG. 6 shows a fabrication and inspection system, in which a controller  1  controls fabrication activities  9  that produce a printed circuit board  16  from input materials  6 . The printed circuit board  16  is input to the inspection system  10 . The report  46  is provided in a feedback loop to the controller  1 . The report  46  may include surface dimension information, and footprint dimension information. The surface dimension information and footprint dimension information may be thought of as a kind of cross-section information. Based on the cross-section information provided to the controller, the controller may, through an automatic or manual process, adjust the assembly activities  9  in response thereto. That is to say, the controller may cause equipment used during fabrication activities  9  to be adjusted, so that the assembly activities are performed in a manner that is projected to produce another printed circuit board  16  with more desirable inspection results.  
         [0048]    [0048]FIG. 7 shows a flow diagram that illustrates the steps just described. In particular, in step  100 , a conductor is formed on a substrate. At least one conductor is formed, but as many as necessary are formed during assembly activities  9  to produce the desired printed circuit board  16 . The printed circuit board  16  is provided to the inspection system  10 . In step  110 , the printed circuit board  16  is inspected to determine the cross-section information (i.e., the surface dimension and the footprint dimension, and any other cross-section information that may be desired).  
         [0049]    The report  46  is produced, containing cross-section information, and provided to the controller  1  in step  120 . In step  130 , the controller determines whether the cross-section information is acceptable. That is to say, the controller determines whether the cross-section information indicates a problem that needs correction, or does not indicate such a problem. If there is a problem that needs correction, processing continues from step  130  to step  140 , in which the controller adjusts the assembly activities based on the cross-section information prior to resuming production at step  100 . If there is not a problem that needs correction, processing may continue from step  130  to step  100 , and production may continue as before.  
         [0050]    [0050]FIG. 8 shows another method of manufacturing electrical circuits, and is similar in many ways to the method illustrated in FIG. 6 except that the report  46  provided by the inspection system  10  is used to determine whether to undertake repair activities, to discard the printed circuit board, or to approve the printed circuit board. It will be appreciated that in this mode of operation, inspection system  10  typically provides an inspection report  47  containing inspection data correlated to specific locations on an inspected printed circuit board substrate  20 . This enables a decision making process that facilitates further automatic or manual inspection of defective locations, and ultimately the repair of those defective portions of the printed circuit board substrate  20  which are deemed repairable.  
         [0051]    [0051]FIG. 9 is a flow diagram that illustrates the steps just mentioned. In particular, steps  100 - 120  are the same as mentioned above with respect to FIG. 7. In step  130 , however, if the cross-section information is acceptable, the printed circuit board  16  is approved. On the other hand, if the cross-section information is not deemed to be acceptable in step  130 , processing continues to step  230  in which it is determined whether repair can or cannot be performed. If it is determined that repair can be performed, then processing continues with the printed circuit board  16  being repaired in the step indicated as “repair conductor”. If it is determined that repair cannot be performed, then the printed circuit board  16  is discarded.  
         [0052]    Another way of saying this, is that the circuit is discarded or repaired in response to a determination based on the cross sectional information.  
         [0053]    It will be appreciated by persons skilled in the art that the present invention is not limited by what has been particularly shown and described hereinabove. Rather the scope of the present invention includes both combinations and subcombinations of the features described hereinabove as well as modifications and variations thereof which would occur to a person of skill in the art upon reading the foregoing description and which are not in the prior art.