Abstract:
A CMOS device is formed in an FDSOI integrated circuit die. By retrieving the MOS functionality for gate voltage levels higher than its stress limits, second gate availability in these devices is being used, and hence removing the additional circuitry that would have been used for protecting the devices from such stress. Implementation in an inverter includes a PMOS transistor and an NMOS transistor. The PMOS and NMOS transistors each include a first gate coupled to the respective source terminal of the transistor. The PMOS and NMOS transistors each include a back gate coupled to the input of the inverter.

Description:
[0001]    This application is a divisional of U.S. application Ser. No. 14/216,701 filed Mar. 17, 2014. 
     
    
     BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The present disclosure is related to the field of integrated circuit dies. The present disclosure is related more particularly to integrated circuits having higher voltage range operations. 
         [0004]    2. Description of the Related Art 
         [0005]    As integrated circuit die technology advances to further and further technology nodes, the gate oxide thickness of MOS transistors continues to shrink. As the gate oxide thickness of MOS transistors shrinks, so does the maximum voltage which can appear across the terminals of the transistors. At or below the 32 nm technology node, CMOS transistors typically cannot tolerate greater than 2 V across any two of the terminals, except bulk. If too high a voltage is applied between the terminals of CMOS transistor, the functionality of the transistor can be destroyed. Various protection schemes are commonly implemented within circuits in order to avoid the possibility that the voltage overload occurs across the terminals of sensitive CMOS transistors. 
         [0006]      FIG. 1  is a schematic diagram of a known inverter circuit implemented at the 32 nm node or smaller in bulk technologies, as well as at the 28 nm FDSOI technology node. The inverter circuit includes a PMOS transistor P 1  and an NMOS transistor N 1 . The PMOS transistor P 1  has a source terminal and a bulk terminal connected to VDD. The NMOS transistor N 1  has a source and a bulk terminal connected to ground. The drains of the transistors N 1  and P 1  are connected to each other at the output Out of the circuit. Due to the thinness of the gate oxide of the transistors N 1  and P 1 , it is important to protect the transistors P 1  and N 1  from receiving a gate voltage higher than its stress limits. To this end, the inverter  20  includes a first protection circuit  22   a  and a second protection circuit  22   b . The first protection circuit  22   a  is coupled between the input In of the inverter and the gate of the transistor P 1 . The protection circuit  22   a  includes a PMOS transistor P 2  and a PMOS transistor P 3 . The gate of the PMOS transistor P 2  is coupled to the input In. The source of the transistor P 2  is coupled to a reference voltage Vref. The level of Vref is lower than or equal to the stress limit of the MOS devices. The drain of the transistor P 2  is coupled to the gate of the transistor P 1 . The gate of the transistor P 3  is coupled to the reference voltage Vref. The drain of the transistor P 3  is coupled to the input In. The source of the transistor P 3  is coupled to the gate of the transistor P 1 . 
         [0007]    The second protection circuit  22   b  is similar to the first protection circuit  22   a . The second protection circuit  22   b  is coupled between the input In of the inverter  20  and the gate of the transistor N 1 . The protection circuit  22   b  includes an NMOS transistor N 2  and an NMOS transistor N 3 . The gate of the NMOS transistor N 2  is coupled to the input In. The source of the transistor N 2  is coupled to a reference voltage Vref. The drain of the transistor N 2  is coupled to the gate of the transistor N 1 . The gate of the transistor N 3  is coupled to the reference voltage Vref. The drain of the transistor N 3  is coupled to the input In. The source of the transistor N 3  is coupled to the gate of the transistor N 1 . The protection circuits  22   a ,  22   b  help to limit the gate voltage on the transistors P 1  and N 1  to the stress ceiling of the device. 
         [0008]    When the input In is high the transistor P 2  is turned off. The transistor P 3  is conducting because the gate of the transistor P 3  is tied to the lower reference voltage. The gate of the transistor P 1  therefore receives the high voltage from the input In and is rendered non-conducting. But because the transistor P 1  is not conducting, the output Out is blocked from the voltage VDD. While the input In is high, the transistor N 2  is rendered conducting. The Vref is therefore applied to the gate of the transistor N 1 . The transistor N 1  is therefore conducting. The output Out is connected to the ground voltage GND. When the input In is low, the transistor N 2  is turned off, thereby shielding the transistor N 1  from the high reference voltage. The transistor N 3  is conducting and the gate of the transistor N 1  receives the low voltage of In on its gate terminal. The transistor N 1  is therefore turned off and the output Out is disconnected from ground. While the input In is low, the transistor P 2  is turned on. The gate of the transistor P 1  receives the Vref through the transistor P 2 . The Vref for the P-channel transistors may or may not be the same as the Vref for the N-channel transistors. Thus one may be low Vref and the other high Vref. The protection circuit  22   a  ensures that the gate of the transistor P 1  does not receive a voltage lower than the low reference voltage. The protection circuit  22   b  ensures that the gate of the transistor N 1  does not receive a voltage higher than the high reference voltage. 
         [0009]      FIG. 2  is a schematic diagram of a known inverter  20  implemented in a circuit in which a supply voltage V DD  is equal to or higher than the stress limit of the MOS devices, e.g. 3.3 V. The known inverter  20   FIG. 2  is essentially identical to the inverter  20  of  FIG. 1  except that the PMOS transistor P 4  is coupled between the transistor P 1  and the output Out. An NMOS transistor N 4  is coupled between the transistor N 1  and the output Out. The transistor P 4  receives on its gate the low reference voltage. The transistor N 4  receives on its gate the high reference voltage. The transistors P 4  and N 4  are always on. 
         [0010]    The inverters of  FIGS. 1 and 2  have the drawback that they must be protected from high voltages by the protection circuits  22   a ,  22   b . Protection circuits  22   a ,  22   b  introduce four additional transistors into the inverter  20 . Thus the inverters of  FIGS. 1 and 2  consume a large amount of area of the semiconductor substrate in order to accommodate the additional transistors of the protection circuits  22   a ,  22   b . Even with the presence of these two protection circuits  22   a ,  22   b , it is still possible for the transistors P 1  and N 1  to be damaged by excessive gate voltages when spikes appear in the prior art supply voltage. 
       BRIEF SUMMARY 
       [0011]    One embodiment is an inverter implemented in FDSOI technology. The inverter includes a PMOS transistor and an NMOS transistor coupled together. The PMOS and NMOS transistors each include a first gate coupled to the respective source terminals of the transistors. The PMOS and NMOS transistors each include a back gate connected together at the input of the inverter. The drains of the transistors are connected to each other at the output of the inverter. 
         [0012]    In one embodiment, the channel region of the transistors are formed in a first semiconductor layer. The first gates are separated from the channel regions of the transistors by a thin gate dielectric according to typical practices. The back gates are formed in a second semiconductor layer separated from the first semiconductor layer by buried oxide layer. The buried oxide layers thicker than the gate dielectric. The buried oxide layer serves as a second gate dielectric separating the back gates from the respective channel regions. 
         [0013]    By applying an input voltage to the back gates of the transistors, the output voltage having complementary level is output at the drains of the transistors. Because the buried oxide is thicker than a standard gate dielectric, the transistors can withstand higher voltages being applied on the back gates. In one embodiment, additional protection circuits are not present because the back gates of the transistors can withstand higher voltages. Thus, due to the presence of the back gates, the inverter according to one embodiment takes up less area and can withstand higher voltages than conventional inverters. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0014]    In the drawings, identical reference numbers identify similar elements or acts. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. 
           [0015]      FIG. 1  is a schematic diagram of a known inverter. 
           [0016]      FIG. 2  is a schematic diagram of a known inverter. 
           [0017]      FIG. 3  is an inverter according to an embodiment as described herein. 
           [0018]      FIG. 4  is an inverter according to an embodiment as described herein. 
           [0019]      FIG. 5  is a cross section of an integrated circuit die including an inverter according to an embodiment as described herein. 
           [0020]      FIG. 6  is a graph of in input and output of an inverter according to an embodiment as described herein. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]      FIG. 3  is a schematic diagram of an inverter  24  according to one embodiment. The inverter  24  includes a PMOS transistor P 5  and an NMOS transistor N 5 . The gate of the transistor P 5  is connected to the source of the transistor P 5 . The gate of the transistor N 5  is connected to the source of the transistor N 5 . The source of the transistor P 5  is connected to VDD. The source of the transistor N 5  is connected to ground. The transistors P 5  and N 5  of the inverter  24  are implemented in FDSOI technology. Because the transistors P 5  and N 5  are implemented in FDSOI technology, the transistors P 5  and N 5  each include a back gate. The back gates of the transistors P 5  and N 5  are connected to the input In of the inverter  24 . The drain terminals of the transistors P 5  and N 5  are connected to the output Out of the inverter  24 . 
         [0022]    As will be described in more detail below in relation to  FIG. 5 , the FDSOI technology allows for the transistors N 5  and P 5  to include back gates. The channel regions of the transistors N 5  and N 5 P 5  are positioned in a first semiconductor layer. In some embodiments, this channel semiconductor is thin. The gate electrodes of the transistors N 5  and P 5  are separated from the channel region by a thin gate dielectric. The back gates of the transistors P 5  and N 5  are implemented in a second semiconductor layer separated from the first semiconductor layer by a buried oxide layer. The buried oxide layer acts as a second gate dielectric separating the channel region from the back gates in the second semiconductor layer. Because the first semiconductor layer is so thin, the channel regions include substantially the entire thickness of the first semiconductor layer in the respective positions. The back gates of the transistors N 5  and P 5  correspond to heavily doped regions of the second semiconductor layer which are rendered conductive by the heavy doping. When a voltage is applied to the back gates, the transistors N 5  and P 5  can be rendered conductive in a similar manner as standard single gate devices. However, because the buried oxide layer is far thicker than a typical gate dielectric, higher voltages can be applied to the back gates of the transistors P 5  and N 5  without damaging the device. Hence, the protection devices  22   a ,  22   b  of  FIGS. 1 and 2  may be excluded from the inverter  24  without adversely affecting the functionality of the inverter  24 . 
         [0023]    The back gates of the transistors P 5  and N 5  are used as the primary gates of the transistors. The standard gates of the transistors P 5  and N 5  are connected as bulk connections would be in typical bulk CMOS devices. Most commonly in bulk CMOS devices, the bulk terminal of a PMOS device is connected to the source of the PMOS device. Most commonly in bulk CMOS devices, the bulk terminal of an NMOS device is connected to the source of the NMOS device. In this fashion, the gates of the transistors P 5  and N 5  are connected to the respective source terminals as bulk terminals would be in standard CMOS devices. The back gates of the transistors P 5  and N 5  act as the primary gates. 
         [0024]    In one embodiment, VDD for the inverter  24  of  FIG. 3  is 1.8 V. Because the supply voltage VDD is relatively low, only two transistors are present in the inverter  24  of  FIG. 3 . 
         [0025]    When the input In receives a high voltage, the PMOS transistor P 5  is rendered non-conducting. The NMOS transistor N 5  is rendered conducting. Thus the transistors P 5  and N 5  of  FIG. 3  behave in a similar manner to standard CMOS transistors in that a high voltage to the back gate turns off the transistor P 5  and a high voltage to the back gate turns on the transistor N 5 . With the transistor P 5  rendered non-conducting, the output Out is electrically isolated from VDD. With the transistor N 5  rendered conducting, the output Out is electrically connected to ground through the transistor N 5 . Thus, a high voltage on the input In will cause the inverter  24  to output a low voltage at the output Out. 
         [0026]    When the input In receives a low voltage, the PMOS transistor P 5  is rendered conducting. The NMOS transistor N 5  is rendered non-conducting. Thus the transistors P 5  and N 5  of  FIG. 3  behave in a similar manner to standard CMOS transistors in that a low voltage on the back gate turns on the transistor P 5  and a low voltage on the back gate turns off the transistor N 5 . With the transistor P 5  rendered conducting, the output Out is electrically connected to VDD through the transistor P 5 . With the transistor N 5  rendered non-conducting, the output Out is electrically isolated from ground. Thus, a low voltage on the input In will cause the inverter  24  to output a high voltage at the output Out. Because the buried oxide layer, which acts as a gate dielectric for the back gates of the transistors P 5  and N 5 , is much thicker than the gate dielectric for the standard gate electrodes of the transistors P 5  and N 5 , the transistors P 5  and N 5  can withstand much higher voltages across the terminals. The inverter  24  of  FIG. 3  therefore includes four fewer transistors than the inverter  20  of  FIG. 2 . 
         [0027]      FIG. 4  is a schematic diagram of an inverter  24  according to one embodiment. The inverter  24  of  FIG. 4  is similar to the inverter  20  of  FIG. 2  in that it can be used at a higher supply voltage VDD, for example 3.3 V or higher. The inverter  24  of  FIG. 4  includes transistors P 5  and N 5  as described previously with respect to  FIG. 3 . The inverter  24  of  FIG. 4  further includes a PMOS transistor P 6  and an NMOS transistor N 6  coupled between the transistors P 5  and N 5 . The transistors P 6  and N 6  are coupled together at their drains to provide the output Out of the inverter  24 . The source of the transistor P 6  is coupled to the drain of the transistor P 5 . The source of the transistor N 6  is coupled to the drain of the transistor N 5 . The transistors P 6  and N 6  each include standard front side transistor gates connected to respective reference voltages. The standard front side gate of the transistor P 6  is connected to a low reference voltage. The standard front side gate of the transistor N 6  is connected to a high reference voltage. The value Vref for the P and N channel transistors may be the same, but they are usually different, the P being lower and the N being high in some cases. The back gates of the transistors P 6  and N 6  are connected to the input In of the inverter  24 . As described previously, the standard gate of the transistor P 5  is connected to the source of the transistor P 5 . The standard gate of the transistor N 5  is connected to the source of the transistor N 5 . 
         [0028]    The presence of the transistors P 6  and N 6  also provides some protection to the inverter  24  against the higher voltages that may be present in the inverter  24 . The transistor P 6  ensures that a voltage smaller than the low-reference voltage will not appear across the terminals of the transistor P 5 . The presence of the transistor N 6  ensures that a voltage greater than the high-voltage reference will not appear across the terminals of the transistor N 5 . 
         [0029]    As described previously, the back gates of the transistors P 5 , P 6 , N 5 , N 6  are separated from the respective channel regions by the buried oxide layer, which is much thicker than the standard gate dielectric. For this reason, higher voltages can be applied to the transistors P 5 , P 6 , N 5 , N 6  without the need of the protection circuits  22   a ,  22   b  of  FIG. 2 . 
         [0030]    The inverter  24  of  FIG. 4  functions in substantially the same manner as the inverter  24  of  FIG. 3 . When a low voltage is applied to the input In, the low voltage on the back gates of the transistors P 5 , P 6  render the transistors P 5 , P 6  conducting, thereby electrically connecting the output Out to VDD. The low voltage on the back gates of the transistors N 5 , N 6  renders the transistors N 5 , N 6  non-conducting, thereby isolating the output Out from ground. A low voltage on the input In therefore results in a high voltage on the output Out. 
         [0031]    When a high voltage is applied to the input In, the high voltage on the back gates of the transistors P 5 , P 6  render the transistors P 5 , P 6  non-conducting, thereby electrically isolating the output Out from VDD. The high voltage on the back gates of the transistors N 5 , N 6  renders the transistors N 5 , N 6  conducting, thereby electrically connecting the output Out to ground. A high voltage on the input In therefore results in a low voltage on the output Out. 
         [0032]      FIG. 5  is a cross-section of an integrated circuit die  30  including the inverter  24  of  FIG. 3 . The integrated circuit die  30  includes a first semiconductor layer  32 . The first semiconductor layer is for example between 2 and 10 nm thick. The first semiconductor layer  32  is positioned on a buried dielectric layer  34 . The buried dielectric layer  34  is for example about 25 nm thick. The second semiconductor layer  36  is positioned below the buried dielectric layer  34 . The second semiconductor layer  36  includes a heavily doped region  35  and an un-doped or lightly doped region  37 . 
         [0033]    The semiconductor layer  32  includes the channel region  42   a  of the transistor P 5  and the channel region  42   b  of the transistor N 5 , source regions  44   a ,  44   b  of the transistors P 5 , N 5  and the drain regions  46   a ,  46   b  of the transistors P 5 , N 5  are also positioned in the first semiconductor layer  32 . The gate electrode  38   a  of the transistor P 5  is separated from the channel region  42   a  by the gate dielectric, which is for example 3 nm thick or less. The gate electrode  38   b  of the transistor N 6  is also separated from the channel region  42   b  by the gate dielectric. The gate electrode  38   a  of the transistor P 5  is connected to the source terminal  44   a  of the transistor P 5 . The gate electrode  38   b  of the transistor N 5  is connected to the source terminal  44   b  of the transistor N 5 . The source electrode  44   a  of the transistor P 5  is coupled to VDD. The drain electrode  46   a  of the transistor P 5  is coupled to the drain electrode  46   b  of the transistor N 5 . The source electrode  44   b  of the transistor N 5  is connected to ground. 
         [0034]    The heavily doped region  35  of the second semiconductor layer  36  includes the back gate of the transistors P 5  and N 6 . The back gate of the transistor P 6  and N 6  are each coupled to the input In by the second gate contacts  48   a ,  48   b  respectively. The second gates in the heavily doped region  35  of the second semiconductor layer  36  are isolated from each other by trench isolations. The second gates are separated from the channel regions  42   a ,  42   b  by the buried oxide layer  34 . The buried oxide layer  34  therefore acts as a second gate dielectric layer separating the channel regions  42   a ,  42   b  from the second gates. 
         [0035]    The transistors P 5  and N 5  are implemented in FDSOI technology as stated previously. The channel regions  42   a ,  42   b  of the transistors P 6  and N 6  are fully depleted. This is in contrast to standard bulk MOS transistors or standard partially depleted SOI transistors. 
         [0036]    In a standard bulk transistor, the semiconductor layer in which the channel region is located can be hundreds of nanometers thick. A charge depleted region forms below the channel region between the source and drain of the standard transistor. The channel region and the charge depleted region below it are typically only a few nanometers thick. Below the charge depleted region is an undepleted bulk semiconductor portion of the semiconductor layer. The bulk semiconductor portion below the channel region is typically at an unknown floating voltage. 
         [0037]    A partially depleted SOI transistor differs from a bulk MOS transistor in that there exists a buried oxide (BOX) layer between the channel region and a bulk silicon substrate. A depletion region, depleted of charge, that forms below the channel region, between the source and drain regions, is bounded below by the BOX. The presence of the BOX prevents the substrate voltage from electrically influencing the channel. Otherwise, the extent of the depletion region depends on the relative dimensions of the various layers, as well as source and drain doping profiles. In the case of the partially depleted SOI device shown in the depletion region does not fill all of the material between the source and the drain, wherein an undepleted portion remains at an undetermined floating electric potential. The presence of the undepleted portion is generally undesirable because it is not well controlled, and yet the associated floating electric potential can electrically influence the channel and degrade the transistor performance. 
         [0038]    A fully-depleted SOI (FDSOI) transistor such as P 5  and N 5  in  FIG. 5  also has a BOX layer  34 . However, the source and drain regions  44   a ,  44   b ,  46   a ,  46   b  of the FDSOI transistors P 6  and N 6  respectively, are shallower than the source and drain regions of a partially depleted SOI device. As a result, the doping profiles are effectively vertical, and the charge characteristics of the channel regions  42   a ,  42   b  can be set by the doping concentrations such that a fully charge-depleted region forms between the source and drain  44   a ,  44   b ,  46   a ,  46   b , bounded below by the BOX  34 , in response to application of a bias voltage to the gate  38   a ,  38   b . Because all of the material between the source and drain is charge-depleted, the undepleted portion has been eliminated as a possible cause of transistor degradation. 
         [0039]    As described previously with respect to  FIG. 3 , when the input In is low, the low voltage is applied to the back gates in the heavily doped region  35  of the second semiconductor layer  36  via the back gate contacts  48   a ,  48   b . The back gates in the heavily doped semiconductor region  35  cause an electric field to affect the channel regions  42   a ,  42   b  of the transistors P 5 , N 5 . The low voltage on the input renders the channel region  42   a  of the PMOS transistor P 5  conducting. This causes the output Out to be electrically connected to VDD through the transistor P 5 . The low voltage on the input In renders the channel region  42   b  of the NMOS transistor N 5  non-conducting. This causes the output Out to be electrically isolated from ground. 
         [0040]    As described previously with respect to  FIG. 3 , when the input In is high, the high voltage is applied to the back gates in the heavily doped region  35  of the second semiconductor layer  36  via the back gate contacts  48   a ,  48   b . The back gates in the heavily doped semiconductor region  35  cause an electric field to affect the channel regions  42   a ,  42   b  of the transistors P 5 , N 5 . The low voltage on the input renders the channel region  42   a  of the PMOS transistor P 5  non-conducting. This causes the output Out to be electrically isolated from VDD. The high voltage on the input In renders the channel region  42   b  of the NMOS transistor N 5  conducting. This causes the output Out to be electrically connected to ground through the source  44   b  of the transistor N 5 . 
         [0041]    Because the buried oxide layer  34  is much thicker than the gate dielectric separating the gate electrodes  38   a ,  38   b  from the channel regions  42   a ,  42   b , the transistors P 5 , N 5  can withstand much higher voltages on the back gates. This can allow for the exclusion of the protection circuits  22   a ,  22   b  of  FIG. 1 . 
         [0042]    While not shown in the figures, the inverter  24  of  FIG. 4  can be implemented in the integrated circuit die  30  in a substantially similar manner as the inverter  24  in the cross section of  FIG. 5 . In particular the transistors P 6 , N 6  will be positioned between the transistors P 5  and N 5 . Channel regions and sources and drains of the transistors P 6 , N 6  would be implemented in the first semiconductor layer  32  in substantially the same manner as the channel regions  42   a ,  42   b , source regions  44   a ,  44   b , and drain regions  46   a ,  46   b  of the transistors P 5 , N 5 . The back gates of the transistors P 6 , N 6  would be implemented in the highly doped region  35  of the semiconductor layer  36  in substantially the same manner as the back gates of the transistors P 5 , N 5 . 
         [0043]    Those of skill in the art will understand that the transistors of the inverter  24  can be implemented in the FDSOI integrated circuit die  30  in a large variety of configurations in accordance with principles of the present disclosure. All such configurations fall within the scope of the present disclosure. 
         [0044]      FIG. 6  is a graph of the voltages on the input In of the inverter  24  and the output Out of the inverter  24  of  FIG. 3  according to one embodiment with V DD  as 1.8 V. When the input voltage is at the high voltage of 3.3 V, the output voltage is 0 V. When the input voltage goes low, the output voltage slews high to 1.8 V. When the input voltage goes high again, the output voltage goes to ground. As can be seen from the graph of  FIG. 6 , when the output voltage goes from low to high, the slew rate is slightly lower than the ideal inverter shown in dashed lines. Nevertheless, the inverter  24  functions very well as an inverter and can withstand higher voltages on the back gates. 
         [0045]    The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments. 
         [0046]    These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.