Abstract:
A clock extraction circuit for PCM NRZ signals which delivers substantially constant power and comprising at least one energy storage device charged by a constant current and discharged into a full wave amplifying circuit, the amplifying circuit delivering power to a filter which filters out the clock signal. This arrangement uses a passive tank circuit and ensures the clock signal from the NRZ data does not die out during periods of little or no clock content in the data stream.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to clock extraction from a PCM (pulse code modulation) signal particularly but not exclusively for use in repeaters for submerged transmission systems. 
     Where the clock extraction circuit has a passive tank or resonator circuit which is driven by a clock signal extracted from the incoming digital data stream, and where the data signal is a non-return-to-zero signal (NRZ), with the kind of bit patterns likely to be received in, for example, a submerged digital data system, the clock signal may tend to die out. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a clock extraction circuit for a NRZ signal to overcome the above-mentioned problem. 
     A feature of the present invention is the provision of a clock extraction circuit for a pulse code modulation non-return-to-zero signal delivering substantially constant power comprising at least one energy storage device charged by a constant current and discharged by the signal; a full wave amplifier circuit coupled to the one storage device into which the one storage device is discharged; and a filter coupled to the amplifier circuit to receive power therefrom and to provide the clock. 
     Preferably a second storage device is employed which causes the amplifier circuit to be self-limiting. In a preferred embodiment an input transformer is provided having a balanced output winding connected so as to drive in push-pull fashion the full wave amplifying circuit. Preferably the full wave amplifying circuit operates under class C condition. 
     A convenient form of filter for filtering the clock signal is a surface acoustic wave (SAW) filter. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     Above-mentioned and other features and objects of this invention will become more apparent by reference to the following description taken in conjunction with the accompanying drawing, in which: 
     FIG. 1 is a block schematic diagram of a repeater for a submerged transmission system according to the principles of the present invention; 
     FIG. 2 is a schematic diagram of the clock or timing extraction circuit of the repeater of FIG. 1; and 
     FIG. 3 is a set of waveforms occurring at various points in the circuit of FIG. 2. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 1, a block diagram of one regenerator module for a repeater for one transmission direction (left to right) is shown. There would be another such module for the opposite transmission direction (not shown). 
     The regenerator modules are powered from a constant line current source at the terminal. 
     Received light is detected by detector 10, which may be a silicon avalanche photodiode biased to give an electrical output varying linearly with the received light level. The signal is pre-amplified by pre-amplifier 11, amplified by amplfier 12 and equalized by equalizer 13. Retiming information is derived by circuit 15 from the data stream and is based on the use of a clock extraction from the data stream, in this embodiment 320 MHZ. AGC circuit 14 ensures a fixed level data signal at the output of amplifier 12. A decision and retiming circuit 16 compares the data pulse with a reference voltage at the rising edge of each clock pulse and interprets the data pulse as 0 or 1, and retimes the regenerated data. 
     A gallium aluminium arsenide laser 17 operating at 1.3 μm is used as a transmitter and modulated by modulator 18 with non-return-to-zero (NRZ) data. 
     Similarly the received data is NRZ data. 
     The timing or clock extraction circuit 15 extracts timing or clock information from the received data stream which is used to drive a passive tank circuit. With the kind of bit patterns used in this system the clock content is going to vary by 16 to 18 dB (decibel) yet a clock accuracy of 1 in 10 11  is required. Because the clock content is varying over this wide range the passive clock generator driven by the extracted clock signal may tend to die out in amplitude. Thus, with a NRZ signal the clock content of the received data varies with the pattern, e.g. 10101010,10101010 is a signal with maximum clock content and 11111111,00000000 is a signal with very much less clock content. The timing (clock) extraction circuit 15 extracts the clock content from such various signals and delivers almost constant power to a filter which actually selects the clock frequency signal. The clock extraction circuit 15 is illustrated in more detail in FIG. 2. 
     Referring to FIG. 2 the signal from main amplifier 12 (FIG. 1) is largely terminated in a 50 ohm resistor R 1 , but capacitor C 1  and the transformer T 1  causes differentiation and &#34;push-pull&#34; operation of transistors TR1 and TR2 so that each transition of the input signal causes a an output pulse and acts as a full wave amplifying circuit. With the input signal removed the voltage v stabilized by two or more diodes D 1  and D 2  causes a small bias current i to forward bias both bases of transistors TR1 and TR2 via resistor R 2 . 
     In its quiescent state the no a.c. present both transistors TR1 and TR2 will be drawing small currents defined by th constant current i and the tail resistor R 3 . 
     A half wave arrangement could also be devised. 
     With input data applied, the shaped positive pulses partly discharge storage capacitor C 2  round the base circuits of transistors TR1 and TR2 and the resulting collector pulses partly discharge storage capacitor C 3  into the filter. Prior to this event C 2  is charged by the constant current i through R 2  and so the accumulated charge is proportional to the time between clock pulses. Capacitor C 2  discharges through either transistor TR1 and the associated transformer winding portion of transistor TR2 and its associated winding portion. A large proportion of the charge on C 3  is discharged into the filter providing a substantially constant power clock signal. The filter F is preferably an SAW filter but it could be an RC filter or an active filter. 
     For a particular clock frequency, e.g. 320 Mc/s, values of capacitors C 1 , C 2  and C 3  and resistor R 2  and the construction of transformer R 1  can be selected to achieve the following. 
     Data with high clock content (101010 etc.) causes C 2  to be discharged every 3 ns (nanoseconds) (in the case of a 320 Mc/s clock). If 11001100 etc. occurs the discharge current tends to be twice as big and so on. Like other peak current circuits, stray resistances and inductance cause loss of efficiency at the higher peak currents, so that 11111111,00000000 results in a clock output about 1 dB down. (Instead of the theoretical 18 dB if no compensation occurred). In the latter case there are 8 bit periods (24 ns) between pulses but these pulses are correspondingly more powerful. 
     The values of capacitors C 1 , C 2  and C 3  and resistor R 2  can be found which yield a compromise of least jitter, best signal to noise and least dependance of filter output or clock content or pattern. 
     The narrow-band filter rings and fills in the gaps between pulses depending on its effective Q value. 
     The filter output is fed to the decision and retiming circuit 16 of FIG. 1. 
     Referring to FIG. 3, the waveform 1 represents an ideal NRZ signal whereas waveform 2 shows in practice the form of NRZ signal which may be received in a submerged digital system, such as at point 2 in FIG. 2. Waveforms 3 and 4 show the signal after differentiation at point 3 of FIG. 2 and rectification a point 4 of FIG. 2 although at point 4 the wave has been largely turned into a sine-wave by the Q of filter F. The tank signal 5 which appears in a partly filtered form at the output of the SAW filter F in FIG. 2 and the phase shifted tank signal 6 will be generated in the retiming circuit of FIG. 1 and the decision circuit of FIG. 1 will regenerate the retimed NRZ signal of waveform 7. 
     While we have described above the principles of our invention in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation to the scope of our invention as set forth in the objects thereof and in the accompanying claim.