Abstract:
A semiconductor package having an impedance matching device is disclosed, which is especially applicable to conventional system-in-package structures and system packaging design with high-density I/O design. The impedance matching device achieves impedance matching between a semiconductor chip and a signal transmission wiring on the substrate or between different systems integrated in the semiconductor package by employment of a vertical conductive line or combination of a vertical conductive line and a stub transmission line. The vertical conductive line is electrically connected with the signal transmission wiring on the substrate at one end thereof, and the stub transmission line may be further connected to the other end of the vertical conductive line. This impedance matching device helps to effectively reduce the wiring area of an impedance matching network of the semiconductor package and enhance the flexibility and interchangeability in layout of the wiring.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a semiconductor package, and particularly to a semiconductor package having an impedance matching device for achieving impedance matching between different systems integrated in the semiconductor package by means of a vertical conductive line or combination of a vertical conductive line and a stub transmission line. 
         [0003]    2. Description of Prior Art 
         [0004]    In the current electronic industry, electronic products, such as mobile phones, bluetooth systems, personal digital assistances and digital cameras, are increasingly required to be lightweight, thin, compact and multifunctional. Consequently, both electronic components and wiring in these electronic products have been increasing in number and reducing in size. This necessitates the introduction of system packaging technology so that subsystems, for example, microprocessors and memory units can be integrated in a semiconductor chip to obtain a compact size. 
         [0005]    System-in-package (SiP) is now the fastest growing system-packaging technology since it is a cost-effective solution to high-density system integration in a single package. In a system-in-package structure, more than one semiconductor chips are stacked in three dimensions and passive components are integrated in the same package to reduce the size. When high quality electrical signals are required, decoupling capacitors are generally embedded in the package so as to provide low-loss electrical signal propagation. Therefore, by integration of embedded components at the substrate level, the system-in-package approach provides the advantage of significant area reduction on a printed circuit board. A system-in-package structure generally includes a multilayer substrate having metal wirings arranged thereon to provide high connection density, low cross-talk and good electromagnetic compatibility (EMC) capabilities, whereby the integrity of electrical signal can be maintained when the metal wirings are connected. As this integral electrical signal is able to meet the performance and reliability requirements for the package, maximum power transfer becomes the first consideration. 
         [0006]    In the subsystems of a conventional system-in-package structure, besides resistors, reactive elements, such as capacitors and inductors, are also included. Therefore, to attain the maximum power transfer for ensuring the package performance and reliability, a conjugate match of all reactance of subsystems of the package as well as equal resistance of the subsystems is required. As reception and transmission of the electrical signals between various subsystems are accomplished by the metal wirings on the substrate, specific high frequency matching network is needed to reduce signal loss during signal reception and transmission. Generally, passive components, such as an inductor-capacitor (LC), are additionally added to the substrate to constitute such a matching network for impedance matching of the subsystems. However, this method results in increased cost and reduction of available space on the substrate. Further, the wiring area of the matching network is reduced, and flexibility and interchangeability in layout of the wiring is limited. 
         [0007]    Hence, it is necessary to provide a semiconductor package having an impedance matching device that is able to achieve impedance matching between different systems integrated in the semiconductor package. The impedance matching device also helps to effectively reduce the wiring area of an impedance matching network of the semiconductor package and enhance the flexibility and interchangeability in layout of the wiring. 
       SUMMARY OF THE INVENTION 
       [0008]    An object of the present invention is to provide a semiconductor package having an impedance matching device for achieving impedance matching between a semiconductor chip mounted on a substrate of the semiconductor package and a signal transmission wiring on the substrate or between different systems integrated in the semiconductor package. This impedance matching is accomplished by means of a vertical conductive line or combination of a vertical conductive line and a stub transmission line. 
         [0009]    To achieve the above object, in one embodiment of the present invention, a semiconductor package includes a substrate having a metal wiring extending in a horizontal direction for transmitting an electrical signal, a semiconductor chip electrically connected with the substrate through the metal wiring, and a conductive line formed in the substrate in a direction substantially perpendicular to the metal wiring. The conductive line is electrically connected with the metal wiring to achieve impedance matching to the semiconductor chip. 
         [0010]    A semiconductor package in accordance with another embodiment of the present invention includes a substrate having a metal wiring extending in a horizontal direction for transmitting an electrical signal, a plurality of semiconductor chips electrically connected with the substrate through the corresponding metal wiring, respectively, and at least one conductive line formed in the substrate in a direction substantially perpendicular to the metal wiring. The conductive line is electrically connected with the metal wiring to achieve impedance matching to the semiconductor chips. 
         [0011]    The semiconductor package constructed according to the present invention comprises an impedance matching device to effectively achieve impedance matching between different systems integrated in the semiconductor package. The impedance matching device also helps to effectively reduce the wiring area of an impedance matching network of the semiconductor package and enhance the flexibility and interchangeability in layout of the wiring. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    The present invention may be best understood through the following description with reference to the accompanying drawings, in which: 
           [0013]      FIGS. 1A to 1C  are schematic representations of a semiconductor package having an impedance matching device according to a first embodiment of the present invention; 
           [0014]      FIGS. 2A to 2C  are schematic representations of a semiconductor package having an impedance matching device according to a first embodiment of the present invention; and 
           [0015]      FIGS. 3A to 3C  are schematic representations of a semiconductor package having an impedance matching device according to a first embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0016]    Referring to  FIGS. 1A to 1C , a substrate  101  of a semiconductor package having an impedance matching device according to a first embodiment of the present invention is schematically shown. The substrate  101 , in an exemplary form of a system in package, has a multilayer substrate including a first substrate unit  106  and a second substrate unit  107  stacked over each other using conventional laminating technology. In the drawings of all embodiments of the present invention, the first and second substrate units  106  and  107  are shown, in an exaggerated manner, to be separated from each other for clear illustration purpose. The substrate  101  as shown is also only a portion of the whole semiconductor package in order to clearly show the impedance matching device thereof. The remaining portion of the whole semiconductor package is not shown for simplicity and clarity purposes for it forms no novel part of the present invention. Thus, a detailed description hereinafter is given to the impedance matching device of the present invention. As shown in  FIGS. 1A to 1C , the substrate  101  has a metal wiring  102  provided in at least one insulation layer (unlabeled) of the first substrate unit  106  (or provided on a surface of at least one insulation layer of the first substrate unit  106 ), and above the second substrate unit  107 . The metal wiring  102  extends in a horizontal direction for transmitting an electrical signal and electrically connects the first and second substrate units  106 ,  107  with a semiconductor chip (not shown) of the substrate  101 . Except for the metal wiring  102 , insulation layers of the first and second substrate units  106 ,  107  may be optionally provided with other metal wiring layers (not shown) thereon/therein for constituting a multilayer structure of the substrate  101 . However, the multilayer structure of the substrate  101  as described above is traditional and not the feature of the present invention, so that related figure and detailed description thereof will be omitted hereinafter. 
         [0017]    To match the impedance of the metal wiring  102  with that of the semiconductor chip, a vertical conductive line  103  is employed in accordance with the first embodiment. The impedance of the semiconductor chip is first calculated, and the dimension of the vertical conductive line  103  is correspondingly adjusted to obtain an impedance matching that of the semiconductor chip. The vertical conductive line  103  is received in vertically aligned first and second vias  108  and  109  of the respective first and second substrate units  106  and  107 . The vertical conductive line  103  is made of electrically conductive metal materials such as copper and gold. The vertical conductive line  103  is electrically connected in parallel with the metal wiring  102  at a predetermined position for impedance matching. 
         [0018]    Referring to  FIG. 1B , which is a top view of  FIG. 1A , the vertical conductive line  103  is arranged in the substrate  101  in a manner that is substantially parallel to the metal wiring  102  when viewed from this angle. 
         [0019]    Further referring to  FIG. 1C , which is a side view of  FIG. 1A , the vertical conductive line  103  is electrically connected with the metal wiring  102  at an upper end thereof for impedance matching, and extends from the first substrate unit  106  to the second substrate unit  107 . Thus, when viewed from this angle, the vertical conductive line  103  is arranged in the substrate to be substantially perpendicular to the horizontal metal wiring  102 . 
         [0020]    Reference is now directed to  FIGS. 2A to 2C , which schematically represent a substrate  201  having an impedance matching device according to a second embodiment of the present invention. In this embodiment, a vertical conductive line and a stub transmission line are employed for impedance matching. As shown in  FIG. 2A , the substrate  201  has a substrate including a first substrate unit  206  and a second substrate unit  207 , and a metal wiring  202  provided in at least one insulation layer (unlabeled) of the first substrate unit  206  (or provided on a surface of at least one insulation layer of the first substrate unit  206 ), and above the second substrate unit  207 . The metal wiring  202  extends in a horizontal direction for transmitting an electrical signal and electrically connects the first and second substrate units  206 ,  207  with a semiconductor chip (not shown) of the substrate  201 . 
         [0021]    To match the impedance of the metal wiring  202  with that of the semiconductor chip, a vertical conductive line  203  and a horizontal stub transmission line  204  are employed in accordance with the second embodiment. The impedance of the semiconductor chip is first calculated, and the dimension of the vertical conductive line  203  is correspondingly adjusted to obtain a desired impedance. In case that the desired impedance of the vertical conductive line  203  matching that of the semiconductor chip can not be obtained by dimension adjustment, a stub transmission line  204  with a selected dimension can be further added to electrically connect in parallel with one end of the vertical conductive line  203 . Thus, a combined impedance of the vertical conductive line  203  and the stub transmission line  204  matching that of the semiconductor chip can be obtained to achieve the impedance matching purpose. The vertical conductive line  203  is received in vertically aligned first and second vias  208  and  209  of the respective first and second substrate units  206  and  207 , and the stub transmission line  204  is provided in the second substrate unit  207  and extends in the horizontal direction. Both the vertical conductive line  203  and the stub transmission line  204  are made of electrically conductive metal materials such as copper and gold. The other end of the vertical conductive line  203 , opposite to that connecting with the stub transmission line  204 , is electrically connected in parallel with the metal wiring  202  at a predetermined position for impedance matching. 
         [0022]    Referring to  FIG. 2B , which is a top view of  FIG. 2A , the combination of the vertical conductive line  203  and the stub transmission line  204  are arranged in the substrate  201  in a manner that it is substantially parallel to the metal wiring  202  when viewed from this angle. 
         [0023]    Further referring to  FIG. 2C , which is a side view of  FIG. 2A , the vertical conductive line  203  is electrically connected in parallel with the metal wiring  202  and the stub transmission line  204  at respective opposite ends thereof, and extends from the first substrate unit  206  to the second substrate unit  207 . Thus, when viewed from this angle, the vertical conductive line  203  is arranged in the first and second substrate units  206  and  207  to be substantially perpendicular to the metal wiring  202  and the stub transmission line  204 , and the stub transmission line  204  is arranged in the second substrate unit  207  and substantially parallel to the metal wiring  202 . 
         [0024]    Reference is now directed to  FIGS. 3A to 3C , which schematically represent a substrate  301  having an impedance matching device according to a third embodiment of the present invention. In this embodiment, a plurality of vertical conductive lines (two shown) and a plurality of stub transmission lines (two shown) are employed for impedance matching. As shown in  FIG. 3A , the substrate  301  has a substrate including a first substrate unit  306  and a second substrate unit  307 , and a metal wiring  302  provided in at least one insulation layer (unlabeled) of the first substrate unit  306  (or provided on a surface of at least one insulation layer of the first substrate unit  306 ), and above the second substrate unit  307 . The metal wiring  302  extends in a horizontal direction for transmitting an electrical signal and electrically connects the first and second substrate units  306 ,  307  with a plurality of semiconductor chips (not shown) of the substrate  301 . 
         [0025]    To match the impedance of the metal wiring  302  with that of the semiconductor chips, first and second vertical conductive lines  303   a ,  303   b  and first and second stub transmission lines  304   a ,  304   b  are exemplarily employed in the third embodiment. The second vertical conductive line  303   b  and the second stub transmission line  304   b  are additionally adopted when the combined impedance of the first vertical conductive line  303   a  and the first stub transmission line  304   a  still can not match the impedance of the semiconductor chip. The first vertical conductive line  303   a  is received in vertically aligned vias  308   a  and  309   a  in the respective first and second substrate units  306  and  307 , and similarly, the second vertical conductive line  303   b  is received in vertically aligned vias  308   b  and  309   b  in the respective first and second substrate units  306  and  307 . The first and second stub transmission lines  304   a ,  304   b  are provided in the second substrate unit  307  and extend in the horizontal direction. The first and second vertical conductive lines  303   a ,  303   b  and the first and second stub transmission lines  304   a ,  304   b  are all made of electrically conductive metal materials such as copper and gold. One end of each first and second vertical conductive lines  303   a ,  303   b  is electrically connected in parallel with a corresponding first and second stub transmission line  304   a ,  304   b , and the other end thereof is electrically connected in series with the metal wiring  302  at a predetermined position for impedance matching. 
         [0026]    Referring to  FIG. 3B , which is a top view of  FIG. 3A , the combination of the first vertical conductive line  303   a  and the first stub transmission line  304   a  and the combination of the second vertical conductive line  303   b  and the second stub transmission line  304   b  are each arranged in the substrate  301  in a manner that they are substantially parallel to the metal wiring  302  when viewed from this angle. 
         [0027]    Further referring to  FIG. 3C , which is a side view of  FIG. 3A , each first and second vertical conductive line  303   a ,  303   b  is electrically connected in parallel with the metal wiring  302  and a corresponding first and second stub transmission line  304   a ,  304   b  at respective opposite ends thereof, and extends from the first substrate unit  306  to the second substrate unit  307 . Thus, when viewed from this angle, the first and second vertical conductive lines  303   a ,  303   b  are arranged in the first and second substrate units  306  and  307  to be substantially perpendicular to the metal wiring  302  and the first and second stub transmission lines  304   a ,  304   b , and the first and second stub transmission lines  304   a ,  304   b  are arranged in the second substrate unit  307  to be substantially parallel to the metal wiring  302 . 
         [0028]    In comparison with the prior art, the semiconductor package constructed according to the present invention comprises an impedance matching device to effectively achieve impedance matching between a semiconductor chip and a signal transmission wiring or between different systems integrated in the semiconductor package in a simple manner. Impedance matching is accomplished by means of a vertical conductive line or combination of a vertical conductive line and a stub transmission line that is disposed in the substrate. The impedance matching device as constructed helps to effectively reduce the wiring area of an impedance matching network of the semiconductor package and enhance the flexibility and interchangeability in layout of the wiring. 
         [0029]    It should be understood that, although in the above embodiments, the vertical conductive line is disclosed to be electrically connected with the metal wiring and the stub transmission line in parallel, the present invention is not so limited. A series electrical connection therebetween is also practicable so long as the impedance matching purpose can be achieved. 
         [0030]    It is to be understood, however, that even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and function of the invention, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.