Abstract:
An input/output (I/O) circuit or cell associated with a pin of a programmable logic circuit allows the pin to be configured as for bidirectional input and output operations, without requiring a second one-bit register to be configured from the configurable logic elements of the programmable logic circuit. The I/O cell can be used in parallel-to-serial, serial-to-parallel and shift register operations.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an input/output (I/O) circuit for a programmable logic circuit (e.g., a field programmable gate array or a complex programmable logic device, known to those skilled in the art). In particular, the present invention relates to an I/O circuit with bidirectional input and output, and shift register capabilities. 
     2. Description of the Related Art 
     In a programmable logic circuit, the I/O pins of the integrated circuit are each associated with an I/O circuit or cell, which is used to either receive an input signal from the associated pin, or to drive an output signal onto the associated pin. One example of an I/O cell in the prior art is described in U.S. Pat. No. 6,034,541, entitled “In-system Programmable Interconnect Circuit” to Kopec et al., filed on Apr. 7, 1997, issued on Mar. 7, 2000, which is assigned to Lattice Semiconductor Corporation, also the Assignee of the present application. The disclosure of U.S. Pat. No. 6,034,541 is hereby incorporated by reference in its entirety to provide background information. 
     Typically an I/O cell provides only a single flip-flop which is configurable to either latch the input signal, or to provide a registered output signal. In order to provide bidirectional operations using the I/O circuit, a 1-bit output register is configured from the general-purpose configurable logic circuits in the programmable logic circuit. Not only is this arrangement cumbersome, providing an output register in this manner results in a circuit that does not meet performance requirements typical of many telecommunication or data communication applications. 
     SUMMARY OF THE INVENTION 
     An input/output (I/O) circuit or cell associated with a pin of a programmable logic circuit allows the pin to be configured as for bidirectional input and output operations, without requiring a second one-bit register to be configured from the configurable logic elements of the programmable logic circuit. The I/O cell can be used in parallel-to-serial, serial-to-parallel and shift register operations. 
     In one embodiment of the present invention, the input/output (I/O) circuit includes input and output flip-flops for capturing an input signal and for providing an output signal, respectively, and multiplexers for routing signals between the input and output flip-flops. Additional multiplexers and routing resources can be provided to route the input signal, the output signal and other signals to other portions of the programmable logic circuit and other I/O circuits. In one implementation, the routing resource provides additional input signals, global clocks and other control signals. 
     By suitably configuring the input flip-flop, the output flip-flop and various multiplexers, the present invention allows a group of I/O circuits to provide serial-to-parallel, parallel-to-serial and shift register operations. 
     In one embodiment, a control flip-flop is provided in the I/O circuit to provide a registered control signal (e.g., an output enable signal). 
     By providing input, output and bidirectional operations without calling on configurable logic elements in the programmable logic circuit, the I/O circuits of the present invention meet high performance requirements of telecommunication and data communication applications. 
     The present invention is better understood upon consideration of the detailed description below and the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows, schematically, an input/output circuit or cell  100 , according to one embodiment of the present invention. 
     FIG. 2 summarizes the values of various control signals into the selection terminals of multiplexers  104 - 107 , 118  and  110 - 111  for each of the operating modes of I/O cell  100 . 
     FIG. 3 illustrates the various serial-to-parallel modes of I/O cell  100  in implementation  300 , according to one embodiment of the present invention. 
     FIG. 4 illustrates the various parallel-to-serial modes of I/O cell  100  in implementation  300 , according to one embodiment of the present invention. 
     To facilitate comparison among the figures, like elements in these figures are provided like reference numerals. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows, schematically, an input/output (I/O) circuit or cell  100 , according to one embodiment of the present invention. As shown in FIG. 1, output-enable (OE) flip-flop  101 , output flip-flop  102  and input flip-flop  103  are provided in I/O circuit  100 . I/O circuit  100  receives data signal (e.g., data signal “drive” at terminal  121 ) and a number of control signals (e.g., “input clock” signal at terminal  115 ) from routing resource  205 . Multiplexer  104  (“B”) selects an OE signal between the registered output of OE flip-flop  101  and its complement, and an unregistered OE control signal from a source within the programmable logic circuit outside of I/O cell  100  and its complement. The selected signal of multiplexer  104  is output at terminal  113 , and is selectable by multiplexer  105  (“G”) to control tristate buffer  108 . Multiplexer  105  can also render tristate buffer  108  always “on” or always “off” by selecting a “1” value or “0” value, respectively, as indicated in FIG.  1 . Tristate buffer  108  drives pin  117  of the programmable logic circuit. 
     Output flip-flop  102  receives an output signal from multiplexer  111  (“A”), which receives the signal at terminal  112  from a neighboring I/O cell, and a signal routed into I/O circuit  100  from terminal  121 . A data signal received into I/O cell  100  can be routed (e.g., at terminal  119 ) to other parts of the programmable logic circuit via routing resource  205 . Multiplexer  111  also selects between the registered and the unregistered output signals of multiplexer  107  (“D”). The value selected by multiplexer  111  is provided as an output value of output flip-flop  102  at terminal  120 . Multiplexer  118  (“C”) selects between this output value at terminal  120  (and its complement) and an input signal (and its complement) received from another portion of the programmable logic (e.g., from an global routing pool) to provide an output value at terminal  114 . Terminal  114  is coupled to terminal  112  of a neighboring I/O circuit, so that terminal  112 , multiplexer  111 , output flip-flop  102 , multiplexer  118  and terminal  114  forms a serial shift path through I/O circuit  100 . Multiplexer  106  (“F”) selects between the signal at terminal  114  and the registered output of input flip-flop  103  to provide a signal to be driven by tristate buffer  108  out of pin  117 . 
     When I/O circuit  100  is configured to receive an input signal at pin  117  under an input or a bidirectional mode, input buffer  109  provides the input signal to multiplexer  107 , which can also select the signal at terminal  114 . The output value of multiplexer  107  is provided to input flip-flop  103 . Multiplexer  110  (“E”) selects between the output value of input flip-flop  103  (i.e., the registered value of the output value of multiplexer  107 ), the unregistered output value of multiplexer  107  and the value at terminal  114  to provide a signal at terminal  119 , which can be routed outside of I/O cell  100  as a logic signal to any part of the programmable logic circuit. Various reset signal, clock signals and other control signals are also provided to I/O circuit  100 , as shown in FIG.  1 . 
     I/O cell  100  can be configured to be used for input, output, bidirectional, serial-to-parallel, parallel-to-serial, and shift register operations. Under input mode and bidirectional mode, the input signal can be received into the programmable logic circuit unregistered, and made registered by input flip-flop  103 . Similarly, under output mode and bidirectional mode, the output signal can be output on pin  117  registered or unregistered. In addition, as described above, the output enable signal applied to output buffer  108  for driving a signal onto pin  117  can also be registered or unregistered. The serial-to-parallel and the parallel-to-serial operations can be double-buffered (i.e., delayed by two clock periods). The values of various control signals into the selection terminals of multiplexers  104 - 107 ,  118  and  110 - 111  for operating under each of these modes are summarized in FIG.  2 . 
     FIG. 3 illustrates the various serial-to-parallel modes of I/O cell  100  in implementation  300 , according to one embodiment of the present invention. In implementation  300 , routing resource  205  is provided for routing signals into and out of I/O cell  100 . As shown, routing resource  205  includes clock bus portion  211  for routing four global clock signals, reset portion  212  for routing a global reset signal, adjacent I/O portion  213  for routing  4  signals from adjacent I/O circuits, and select portion  214  for routing two common selection signals for controlling multiplexer  210 , which provides the signal at terminal  121 . Multiplexer  210  selects one of the four signals routed from neighboring I/O cells and the four signals from elsewhere in the programmable logic circuit (e.g., from a global routing pool). 
     Implementation  300  accepts a number of different input voltages at the pins, under multiple input voltage standards. As shown in FIG. 3, level converter circuit  201  provides signal level conversion for the input signal received at multiplexer  107 . Various programmable termination circuits and programmable delay circuits are provided to adjust signal quality and noise immunity, as are known in the art. In implementation  300 , multiplexers  202 - 204  each select one of a multiplicity of clock signals to a respective one of flip-flops  101 - 103 . In a serial-to-parallel operation, serial input data are provided on line  301 , which is latched one bit at a time into output flip-flop  102 . In single buffer mode, the output value of output flip-flop  102  is provided to pin  117  through multiplexers  118 ,  106  and tristate buffer  108 . As data is shifted out of output flip-flop  102  onto terminal  114  through multiplexer  118 , the data is captured into output flip-flop  102  of an adjacent I/O cell from the corresponding shift-in terminal  112 . Under double-buffer mode, rather than providing pin  117  the output value of multiplexer  118 , input flip-flop  103  captures the value at terminal  114  (selected by multiplexer  107 ) and provides an output value, one clock period later, at terminal  122 . Under double-buffer mode, multiplexer  106  provides the value at terminal  122  as parallel output data at pin  117 . 
     FIG. 4 illustrates the various parallel-to-serial modes of I/O cell  100  in implementation  300 , according to one embodiment of the present invention. In a parallel-to-serial operation, the parallel data are provided on the respective input pins of a number of I/O circuits. Each bit of the parallel data is selected by multiplexer  107  of each I/O circuit and latched into input flip-flop  103  of each I/O circuit from terminal  123 . The value captured in input flip-flop  103  is captured by output flip-flop  102  in the next clock period. Multiplexer  111  coupled to the data input terminal of flip-flip  102  can be dynamically switched to facilitate a load or shift function by changing the control signal  127  from routing resource  205 . The data in output flip-flop  102  is then shifted from I/O circuit to I/O circuit along the serial path formed by terminals  114  and  112  in each I/O circuit. Under single buffer mode, the output value of the last output flip-flop  102  is routed through terminal  124  as serial output at terminal  119 . Under double-buffer mode, rather than routing the output signal through terminal  124 , input flip-flop  103  of the last I/O circuit captures the value at terminal  114  and provides an output value, one clock period later, at terminal  122 . Under double-buffer mode, multiplexer  110  provides the value at terminal  122  as serial output. 
     The above detailed description is provided to illustrate the embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is set forth in the accompanying claims.