Abstract:
A voltage driving circuit for use in a semiconductor memory device. The voltage driving circuit includes a generator which generates a first voltage for an operating mode of the device, a generator which generates a second voltage for a standby mode, and a pair of switches connected between the voltage generators and an operating circuit, for selectively supplying the first and second voltages thereto. The first and second switches each have a control terminal, both of which are commonly coupled to a mode signal, for allowing external control of the voltage selection. The first and second voltages are preferably set relative to each other so as to reduce the subthreshold leakage current consumed by the semiconductor memory during a standby mode, while maintaining a desired operating speed during an operating mode.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a voltage driving circuit for use in a semiconductor memory device, and more particularly, to a circuit capable of selectively driving different voltages according to different modes of the device. 
     2. Description of the Related Art 
     In general, to guarantee the reliability of MOS transistors used in semiconductor memory devices, the power supply voltage of the device is kept as low as possible. Likewise, to operate MOS transistors at high speed, their threshold voltage should also be kept low. In particular, the threshold voltage of MOS transistors should be below 1/4 V CC  to prevent their operating speeds from being too low. For example, when the power supply voltage is 1.5 V, the MOS transistor threshold voltage should be below 0.4 V. 
     Conversely, to eliminate subthreshold leakage current in a MOS transistor, its threshold voltage should be set above 0.7 V. For example, when a low power supply voltage, i.e., 1.5 V, is used, a leakage current of more than 10 2  -10 5  times that of a MOS transistor using a power supply voltage of 5 V is generated. The leakage current increases the amount of standby current consumed by the high density semiconductor memory device during its standby mode. 
     SUMMARY OF THE INVENTION 
     Therefore, it is an object of the invention to provide a voltage driving circuit capable of selectively providing voltages of different potential according to selected modes in a high density semiconductor memory device. 
     It is another object of the invention to provide a voltage driving circuit which is capable of eliminating subthreshold leakage current generated by MOS transistors in high density semiconductor memory devices. 
     It is still another object of the invention to provide a voltage driving circuit which is capable of ensuring high speed memory operations of MOS transistors in high density semiconductor memory devices. 
     In order to achieve these objects and others, a voltage driving circuit according to the present invention includes a generator which generates a first voltage for an operating mode of the device, a generator which generates a second voltage for a standby mode, and a pair of switches connected between the voltage generators and an operating circuit, for selectively supplying the first and second voltages thereto. The first and second switches each have a control terminal, both of which are commonly coupled to a mode signal, for allowing external control of the voltage selection. The first and second voltages are preferably set relative to each other so as to reduce the subthreshold leakage current consumed by the semiconductor memory during a standby mode, while maintaining a desired operating speed during an operating mode. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects, advantages and features of the present invention will be more apparent from the following detailed description taken together with the attached drawings in which: 
     FIG. 1A shows the symbol of a MOS transistor and FIGS. 1B and 1C illustrate characteristics between current I DS  and voltage V GS  in the MOS transistor shown in FIG. 1A; 
     FIG. 2A is a diagram illustrating one construction of a first voltage driving circuit according to the present invention, FIG. 2B a second voltage driving circuit, and FIG. 2C a third voltage driving circuit; 
     FIG. 3 is a circuit diagram showing one embodiment of the first voltage driving circuit shown in FIG. 2A; and 
     FIG. 4 is a waveform diagram illustrating operation characteristics of the first voltage driving circuit shown in FIG. 3. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1A shows the symbol of an NMOS type of MOS transistor. The reference numerals indicate a drain electrode 1, a gate electrode 2, a source electrode 3, and a substrate 4. FIGS. 1B and 1C illustrate a relationship between the current I 13  flowing into the source electrode from the drain electrode, and the voltage V 23  between the gate electrode and the source electrode in the NMOS transistor, wherein FIG. 1B is shown in a linear scale and FIG. 1C in a logarithmic scale. 
     In accordance with the current and voltage characteristics shown in FIGS. 1B and 1C, the threshold voltage V TH  of the MOS transistor can be given by the following equation (1). ##EQU1## 
     In equation (1), V THO  is the threshold voltage of a long channel, γ is a body effect coefficient, Φ F  denotes a quasi fermi potential, and ΔV 13  indicates a drain-induced-barrier lowering coefficient. 
     In an NMOS transistor such as depicted by FIG. 1A, assuming that the V CC  is equal to V 1 , V SS  is equal to V 4 , and that V 3  is changed to V SS2  from V SS1 , the corresponding change in threshold voltage is given by the following equation (2). ##EQU2## 
     Similarly, in a PMOS transistor, assuming that the V SS  is equal to V 3 , V CC  is equal to V 4 , and that V 1  is changed to V CC2  from V CC1 , the corresponding change in threshold voltage is given as an equation (3). ##EQU3## 
     In the above equations (2) and (3), V CC , V SS , V CC1 , V SS1 , V CC2 , and V SS2  can represent any voltage level. Therefore, it is possible to reduce the leakage current by changing the threshold voltages of the NMOS and PMOS transistors according to the relationship of these voltages. 
     As discussed above, by controlling the voltages provided to the semiconductor memory transistors according to a plurality of voltage modes, the leakage current of the transistors can be reduced. FIG. 2A shows one construction of a first voltage driving circuit according to the present invention. In the voltage driving circuit such as that shown in FIG. 2A, a first power supply voltage generator 11 generates a first power supply voltage V CC1 , and a second power supply voltage generator 12 generates the second power supply voltage V CC2  which is lower than the first power supply voltage V CC1 . If the first power supply voltage V CC1  is established as external power supply voltage V CC , the second power supply voltage V CC2  can be established as internal power supply voltage. If the first power supply voltage V CC1  is established as the internal power supply voltage, the second power supply voltage V CC2  can be established as any voltage lower than the internal power supply voltage. That is, the first power supply voltage V CC1  can have a power supply voltage of more than V HT  +α and the second power supply voltage V CC2  can have any level greater than that of V TH  which is capable of maintaining the logic state of a circuit 14. 
     The first power supply voltage V CC1  output from the first power voltage generator 11 and the second power supply voltage V CC2  from the second power voltage generator 12 are both input to a switch circuit 13. A mode control signal φ is input to the terminals of the switch circuit 13, and according to the modes selected thereby, the first and second power supply voltages V CC1  and V CC2  are selected and then output to the circuit 14. 
     FIG. 3 shows one embodiment of the first voltage driving circuit shown in FIG. 2A and FIG. 4 is a waveform diagram illustrating operational characteristics of the circuit FIG. 3. Reference numeral 411 indicates the mode control signal φ which is defined as a signal for selecting either a standby mode or a normal mode. For example, the signal φ can use a row address strobe RAS in a dynamic random access memory device, a chip selection signal CS in a static random access memory device, or a chip enable signal CE in a nonvolatile memory device. The first and second power supply voltages V CC1  and V CC2 , as mentioned above, are generated by the first and second power supply voltage generators 11 and 12. A PMOS transistor 31 whose gate electrode is coupled with the mode control signal φ is connected between the first power supply voltage V CC1  and the circuit 14. An inverter 34 inverts and outputs the inverted mode control signal φ. A PMOS transistor 32 whose gate electrode is coupled with an output terminal of the inverter 34 is connected between the second power supply voltage V CC2  and the circuit 14. An NMOS transistor 33 whose gate electrode is coupled with the mode control signal φ is connected between the second power supply voltage V CC2  and the circuit 14. 
     The above construction corresponds to the switch circuit 13 of FIG. 2A. Therefore, if the mode control signal φ representing an operating mode in FIG. 4 is inputted at the logic &#34;low&#34; level, the PMOS transistor 31 is turned on and the NMOS transistor 33 is turned off. Further, the PMOS transistor 32 is turned off by the inverter 34. Thus, if the PMOS transistor 31 is turned on, the first power supply voltage V CC1  output from the first power supply voltage generator 11 is provided to the circuit 14, as shown by the reference numeral 412 in FIG. 4. When the PMOS transistor 32 and the NMOS transistor 33 are turned off, a path of the second power supply voltage V CC2  is blocked. Accordingly, during the operating mode, the circuit 14 inputs the first power supply voltage V CC1  as an operating power supply voltage to perform its function. 
     Thereafter, if the mode control signal φ is changed to the logic &#34;high&#34; level, the PMOS transistor 31 is turned off and the NMOS transistor 33 is turned on. Further, the PMOS transistor 32 is turned on by the inverter 34. Hence, when the PMOS transistor 32 and the NMOS transistor 33 are turned on, the second power supply voltage V CC2  output from the second power supply voltage generator 12 is provided to the circuit 14, as shown by the reference numeral 412 in FIG. 4. Because the PMOS transistor 31 is turned off, a path of the first power supply voltage V CC1  is blocked. Accordingly, during the standby mode, the circuit 14 inputs the second power supply voltage V CC2  as an operating power supply voltage to thereby maintain a corresponding state. 
     FIG. 2B shows construction of a second voltage driving circuit according to the present invention. A first ground voltage generator 15 generates a first ground voltage V SS1 . A second ground voltage generator 16 generates a second ground voltage V SS2  which is higher than the first ground voltage V SS1 . If the first ground voltage V SS1  is established as external ground voltage V SS , the second ground voltage V SS2  can be established as internal ground voltage V SS . On the other hand, if the first ground voltage V SS1  is established as the internal ground voltage V SS , the second ground voltage V SS2  can be established as any voltage higher than the internal ground voltage V SS . That is, the first ground voltage V SS1  can have a voltage of 0 V and the second ground voltage V SS2  can have a voltage greater than V CC  -V TH  -α. The first ground voltage V SS1  output from the first ground voltage generator 15 and the second ground supply voltage V SS2  from the second ground voltage generator 16 are both input to the switch circuit 17. The mode control signal is input to the terminals of the switch circuit 17, and according to the modes selected thereby, the first and second ground supply voltages V SS1  and V SS2  are selected and then output to the circuit 14. 
     FIG. 2C shows construction of a third voltage driving circuit using the first and second power supply voltages V CC1  and V CC2  of FIG. 2A and the first and second ground voltages V SS1  and V SS2  of FIG. 2B. Here, for example, the first power supply voltage V CC1  can have a power supply voltage greater than that of an internal power supply voltage, the second power supply voltage V CC2  a power supply voltage of 3/2(V TH  +α), the first ground voltage V SS1  a voltage of 0 V, and the second ground voltage V SS2  a voltage of 1/2(V TH  +α). 
     As mentioned in the foregoing description, the present invention is designed to efficiently provide optimal voltages according to the selected mode of the semiconductor memory device. Further, since the present invention selectively drives appropriate voltages to operate the circuit, it is possible to prevent the subthreshold leakage current and to prevent current from being unnecessarily consumed in the standby mode. 
     Although the present invention has been described above with reference to the preferred embodiment, it will be appreciated by those skilled in the art that various substitutions and modifications can be made without departing from the spirit and scope of the invention as set forth in the appended claims.