Abstract:
Method and related apparatus for digital/analog converter are disclosed. The invention is based on M switch elements with each capable of selectively providing a positive or a negative electricity. While generating an analog signal output corresponding to a digital input of value D, the invention calculates two values Pa and Na according to these two equations: Pa−Na=D; Pa+Na=M, (M−1) or (M+1), and then Pa switch elements are made to respectively provide positive electricity with Na switch elements respectively providing negative electricity, such that the analog signal output is synthesized. Because the invention can perform error shaping for imbalance positive/negative electricity within each switch element, and for mismatch between the switch elements, the invention works well for over-sampling A/D converter system.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     The application claims the benefit of U.S. Provisional Application No. 60/593,825, filed Feb. 17, 2005, and included herein by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The invention provides a method and related apparatus for digital-analog conversion, and more particularly, a digital-analog conversion system for achieving better dynamic element matching in an over-sampling D/A converter.  
         [0004]     2. Description of the Prior Art  
         [0005]     Due to the advancing techniques of semiconductor, a variety of information, data, characters, and audio data are capable of being processed and delivered quickly. Various electrical circuits for signal processing become essential hardware of today&#39;s information society. Digital-analog converter systems capable of converting digital signals into analog signals have found a myriad of applications in many electrical circuits produced for communication, audiovisuals, and hi-fi equipment uses.  
         [0006]     D/A converter systems are divided into two classes: Nyquist sampling rate D/A converter systems and over-sampling D/A converter systems. As known, an ideal sampling rate (Nyquist sampling rate) is at least greater than twice the signal frequency when sampling. This is the so-called sampling law. A D/A converter system designed based on this sampling rate is called a Nyquist D/A converter system. However, sigma-delta converters, which are developing quickly recently, is an over-sampling D/A converter system. In this kind of system, a sampling rate is further greater than that in the Nyquist sampling rate D/A converter system.  
         [0007]     Generally speaking, a D/A converter system includes a core digital-analog circuit and related converter control logic for generating a corresponding analog output according to a digital input. The digital-analog circuit includes a plurality of switch elements capable of selectively supplying a unit of electricity or not. While generating a corresponding analog output, the numbers of switch elements which are turned on are determined according to the digital input. For example, if the digital input is a binary 011 (which equals three), then three switch elements are turned on and the others are turned off to supply three units of electricity as the analog output of the digital-analog circuit.  
         [0008]     In some digital-analog applications, the value of digital input is positive or negative. Correspondingly, in such digital-analog applications, each switch element is capable of selectively supplying a unit of positive electricity or a unit of negative electricity or neither to represent the digital value of +1, −1, or 0 respectively. In the prior art, if the digital input is +4, the digital-analog circuit turns on four switch elements for supplying a total of four units of positive electricity; if the digital input is −2, the digital-analog circuit turns on two switch elements for supplying a total of two units of negative electricity. The switch elements are called three-level switch elements due to being capable of selectively supplying a unit of positive electricity or a unit of negative electricity or no electricity.  
         [0009]     Three-level switch elements are realized practically by using switch capacitors or positive/negative current source techniques. In the switch capacitor technique, the switch elements include a capacitor for selectively supplying a unit of positive electricity or a unit of negative electricity or no electricity. In the positive/negative current source technique, the switch elements include two current sources for supplying a two-way current. One current source is connected and the other is disconnected for selectively supplying a unit of positive electricity or a unit of negative electricity, and both current sources are connected or disconnected for supplying no electricity. However, no matter what technique is applied in such digital-analog circuits, there are still mismatches between switch elements. Each switch element in the digital-analog circuit supplies a unit of positive electricity or negative electricity in an ideal condition, but different switch elements practically supply different electricity causing mismatch due to manufacturing differences. For example, in actuality one switch element may supply 1.05 units of electricity and another may supply 0.98 units of electricity, making the electricity of the compound analog output unequal to the ideal value and thus causing a mismatch.  
         [0010]     Besides mismatch error, the switch elements still have gain error. Generally speaking, there is mismatch between the positive and negative electricity provided by each three-level switch element. Ideally, each three-level switch element is capable of selectively supplying a unit of positive electricity or a unit of negative electricity. But in practice, even the positive or negative electricity provided by the same switch element are marginally different. For example, one three-level switch element supplies 1.02 units of positive electricity but merely supplies 0.96 units of negative electricity, thus causing gain error. When the switch element supplies 1.02 units of positive electricity according to the digital input value of +1, the gain error is 1.02/1; but when the switch element supplies 0.96 units of negative electricity according to the digital input value of −1, the gain error is 0.96/1. This represents that the switch element has gain error when supplying electricity according to positive or negative digital input. In the positive/negative current source technique, the three-level switch elements have bigger gain error. Because the positive and negative current sources are realized with different type of transistors (NMOS and PMOS) in the same switch element, it is difficult to reach a balance and match the positive and negative current sources.  
         [0011]     With regard to the mismatch between the switch elements, some prior art already lower the effects. For example, when using an over-sampling D/A converter system, a known D/A converter circuit uses different switch elements to generate an analog output for reducing the mismatch effect between switch elements, which is so called dynamic element matching technique.  
         [0012]     However, the prior art does not readily lower the gain error caused by the imbalance of each switch element&#39;s positive and negative electricity. Most D/A converter systems lower the mismatch between switch elements, but are unable to solve the gain error. This reduces the immunity against errors, so known digital-analog converter systems are unable to get a better signal-noise ratio (SNR).  
       SUMMARY OF THE INVENTION  
       [0013]     The present invention provides a digital-analog converter system, including a common mode adjustment module, a pre-processing module, a digital-analog converter circuit and an assignment module. The common mode adjustment module determines a first value S according to a digital input D. The pre-processing module connects to the common mode adjustment module for determining number of positive units which are turned on (Pa) and number of negative units which are turned on (Na) according to the first value S and the digital input D. The digital-analog converter circuit includes M three-level switch elements, wherein each three-level switch element has a positive unit capable of supplying a unit of positive electricity and a negative unit capable of supplying a unit of negative electricity, the digital-analog converter circuit generates a corresponding analog output according to Pa and Na. The assignment module is connected to the pre-processing module and the digital-analog converter circuit for controlling the M three-level switch elements to supply positive or negative electricity in a predetermined order according to the first value S.  
         [0014]     The present invention further provides a digital-analog converting method in a digital-analog converter system including M three-level switch elements. Each three-level switch element has a positive unit capable of supplying a unit of positive electricity and a negative unit capable of supplying a unit of negative electricity. The method includes the following steps. First, determining a first value S according to a digital input D. Then, determining number of positive units which are turned on (Pa) and number of negative units which are turned on (Na) according to the first value S and the digital input D. Next, controlling the M three-level switch elements to supply positive or negative electricity in a predetermined order according to the first value S. Finally, generating a corresponding analog output according to Pa and Na.  
         [0015]     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]      FIG. 1  is a block diagram of a typical digital-analog converter system.  
         [0017]      FIG. 2  shows a diagram illustrating the system of  FIG. 1  processing typical dynamic element matching.  
         [0018]      FIG. 3  is a block diagram of a digital-analog converter system according to an embodiment of the present invention.  
         [0019]      FIG. 4  shows a diagram of synthesizing various analog output signals with an amount of positive and negative electricity according to an embodiment of the present invention.  
         [0020]      FIG. 5  shows a diagram illustrating a system of  FIG. 3  converting a series of digital inputs into analog outputs sequentially.  
         [0021]      FIG. 6  shows a diagram of realizing an over-sampling D/A converter system of  FIG. 3 . 
     
    
     DETAILED DESCRIPTION  
       [0022]     Please refer to  FIG. 1 .  FIG. 1  is a diagram illustrating a digital-analog converter system  10 . The digital-analog converter system  10  includes an input circuit  12 , an assignment circuit  14 , and a D/A circuit  16 . The D/A circuit  16  includes M three-level switch elements Q 1  to QM capable of selectively supplying a unit of positive electricity or negative electricity or no electricity. The input circuit  12  supplies a digital input. The assignment circuit  14  is a controlling logic of D/A converting for generating a corresponding analog output according to the digital input of the input circuit  12 .  
         [0023]     As mentioned, a dynamic element matching technique is used to generate analog outputs for lowering the mismatch between three-level switch elements. Please refer to  FIG. 2 .  FIG. 2  illustrates two types of typical dynamic element matching techniques of the digital-analog converter system  10 . The vertical axis in  FIG. 2  is time, and there are eight three-level switch elements Q 1  to Q 8 . When generating analog outputs according to corresponding digital inputs, switch elements for supplying positive electricity are shown as single-hatched blocks, those for supplying negative electricity are shown as cross-hatched blocks, and those for supplying no electricity are shown as white blocks.  
         [0024]     The left portion of  FIG. 2  illustrates a double-index averaging (DIA) dynamic element matching technique. The method uses two independent queues to assign which switch elements supply positive electricity and which switch elements supply negative electricity. As shown in the left portion of  FIG. 2 , when the digital input is −4, the assignment circuit  14  appoints switch elements Q 1 -Q 4  to supply negative electricity at time t 0 . At time t 1 , when the digital input is −3, the assignment circuit  14  appoints switch elements Q 5 -Q 7  substituted for switch elements Q 1 -Q 4  to supply negative electricity. At time t 2 , when the digital input is −2, the sequential switch elements Q 8  and Q 1  are appointed to supply negative electricity. At time t 3 , when the digital input is −1, the sequential switch element Q 2  is appointed to supply negative electricity.  
         [0025]     At time t 5 , when the digital input is 1, one switch element is appointed to supply positive electricity. Due to DIA dynamic element matching arranging the switch elements for supplying positive and negative electricity independently, the switch element Q 1  is appointed to supply positive electricity at time t 5 . At time t 6 , when the digital input is 2, the sequential switch elements Q 2 -Q 3  are appointed to supply positive electricity. At time t 7 , when the digital input is 3, the sequential switch elements Q 4 -Q 6  are appointed to supply positive electricity.  
         [0026]     In other words, if the preceding digital input D is a negative value and the DIA dynamic element matching arranges some switch elements to supply negative electricity, on a next negative digital input D the DIA dynamic element matching arranges other switch elements to substitute for the former to supply negative electricity alternately. If the preceding digital input D is a positive value and the DIA dynamic element matching arranges some switch elements to supply positive electricity, on a next positive digital input D the DIA dynamic element matching arranges other switch elements to substitute for the former to supply positive electricity alternately.  
         [0027]     The right portion of  FIG. 2  illustrates the practicality of differential data weight averaging (DDWA). The dynamic element matching method arranges the rotation of switch elements for supplying positive and negative electricity in different directions. The switch elements for supplying positive electricity alternate by increasing index progressively, such as the sequence Q 1 , Q 2 , and Q 3 . The switch elements for supplying negative electricity alternate by decreasing index progressively, such as the sequence Q 8 , Q 7 , and Q 6 . As shown in the right portion of  FIG. 2 , when the digital input is −4, the DDWA dynamic element matching arranges switch elements Q 8 -Q 5  to supply negative electricity at time t 0 . At time t 1 , when the digital input is −3, the sequential switch elements Q 4 -Q 2  are appointed to supply negative electricity by decreasing index progressively. At time t 2 , when the digital input is a negative number, −2, the sequential switch elements Q 8  and Q 1  are appointed to supply negative electricity.  
         [0028]     At time t 5 , when the digital input is a positive number +1, the DDWA dynamic element matching arranges switch element Q 7  to supply positive electricity in place of switch element Q 6  by increasing index progressively. At time t 6 , when the digital input is +2, the DDWA dynamic element matching arranges switch elements Q 8  and Q 1  to supply positive electricity. At time t 7 , when the digital input is still a positive number, the sequential switch elements Q 2 -Q 4  are appointed to supply positive electricity.  
         [0029]     As shown in  FIG. 2 , the corresponding analog outputs are generated by different switch elements even though the digital input values are the same at different times. In  FIG. 2 , both the digital input values are 3 at time t 7  and t 9 , but the corresponding analog outputs are generated by different switch elements whether in DIA or DDWA. Analog outputs are generated with different switch elements when processing a series of digital inputs, which lowers the mismatch between switch elements. In an over-sampling digital-analog converter system, dynamic element matching transforms the mismatch into high-frequency noise for lowering the effect of mismatch.  
         [0030]     As mentioned before, besides the mismatch between switch elements, there are still gain errors between switch elements. Gain errors are difficult to be reduced by the dynamic element matching technology of  FIG. 2 , because that technology does not consider the balance of no electricity. Assume that a switch element is capable of supplying positive electricity of Ip and negative electricity of −In. The ideal balance of positive and negative electricity is 0 when Ip equals In. In fact, even in the same switch element, the positive electricity and negative electricity do not match completely. The balance electricity (Ip−In)/2 is not equal to no electricity, that is, 0. If the positive electricity Ip is 1 and the negative electricity −In is −1, then the value between +1 and −1 is represented by (Ip−In)/2. In  FIG. 2 , these two typical technologies have no solution to gain error.  
         [0031]     Please refer to  FIG. 3 .  FIG. 3  is block diagram showing an embodiment of a digital-analog converter system  20  of the present invention. The digital-analog converter system  20  includes an input circuit  22  and a D/A circuit  32 . The input circuit  22  supplies a digital input being a positive or negative value. The D/A circuit  32  includes M three-level switch elements E 1 -EM. In the embodiment of the present invention, each switch element Em is capable of selectively supplying or not supplying one unit of positive or negative electricity. As shown in  FIG. 3 , the switch element Em is equivalent to a positive unit Ep(m) for supplying or not supplying a unit of positive electricity, and a negative unit En(m) for supplying or not supplying a unit of negative electricity. Turning on or off the positive unit Ep(m) and negative unit En(m) individually make the switch element Em supply a unit of positive electricity of +1, a unit negative electricity of −1, enable common-mode electricity of 0, or disable common-mode electricity of 0. The switch elements are realized with positive and negative current sources. All electricity of switch elements E 1 -EM are combined to generate an analog output.  
         [0032]     The digital-analog converter system  20  further includes a common mode adjustment module  24 , a pre-processing module  26 , and an assignment module  28 , wherein the common mode adjustment module  24  and the pre-processing module  26  synthesize an adjustment circuit. When converting a digital input D into an analog output, the common mode adjustment module  24  determines a first value S according to D. The pre-processing module  26  calculates the values of Pa and Na according to these two equations: Pa+Na=S, Pa−Na=D. Pa represents the number of positive units which is turned on for supplying Pa units of positive electricity, and Na represents the number of negative units which is turned on for supplying Na units of negative electricity. Because Pa−Na=D, Pa units of positive electricity are combined with Na units of negative electricity to generate a corresponding analog output.  
         [0033]     As mentioned before, Pa−Na=D is a requirement for generating an analog output according to a digital input D. S=Pa+Na has some flexibility. Please refer to  FIG. 3 , and assume that M is an even number. When D is even, S=M; and when D is odd, S=(M−1) or (M+1). When converting a series of digital inputs into analog outputs, if a preceding digital input D is an odd number and the first value S is M−1, on a next odd digital input D the first value S is M+1; or if the preceding digital input D is an odd number and the first value S is M+1, on a next odd digital input D the first value S is M−1. Alternately choosing S=M−1 and S=M+1 for consecutive odd values of input D to supply no electricity makes the value 0 equal the balance electricity for lowering the gain error.  
         [0034]     After the pre-processing module  26  determines the value of Pa and Na according to the values of D and S, the assignment module  28  decides which Pa positive units and which Na negative units to turn on. In the embodiment of  FIG. 3 , the assignment module  28  includes two independent assignment circuits  30   p  and  30   n . The assignment circuit  30   p  turns on or turns off the positive units in a pre-determined order for supplying positive electricity while converting a series of digital inputs into analog outputs; and the assignment circuit  30   n  turns on or turns off the negative units in a pre-determined order for supplying negative electricity while converting a series of digital inputs into analog outputs.  
         [0035]     In other words, the assignment circuit  30   p  and  30   n  use different positive units and negative units to supply electricity for lowering the effect of the mismatch between switch elements. The common mode adjustment module  24  reduces the gain error caused by the mismatch between positive units and negative units. The present invention is capable of lowering the effects of mismatch and gain error.  
         [0036]     Take M=8, for example. Please refer to  FIG. 4  and  FIG. 5 .  FIG. 4  illustrates using eight switch elements to determine the values Pa and Na according to the digital input D.  FIG. 5  shows an example to describe the operation of turning on and turning off these eight positive and negative units. The vertical axis of  FIG. 5  is time.  
         [0037]     As shown in  FIG. 4 , when the digital input D is an even number 8, (Pa,Na)=(8,0) generates a corresponding analog output. When the digital input is 6, (Pa,Na)=(7,1) generates a corresponding analog output. The values Pa and Na are calculated from Pa+Na=8. By contrast, when the digital input is an odd number, there are two combinations for (Pa,Na): Pa+Na=M=1 and Pa+Na=M−1. When the digital input is 7, (Pa,Na) is (8,1) or (7,0); and when the digital input is −3, (Pa,Na) is (3,6) or (2,5).  
         [0038]     In  FIG. 5 , each switch element E 1 -E 8  is represented by one grid element representing the positive unit and another grid element representing the negative unit. When generating analog outputs, switch elements for supplying positive electricity are single-hatched, those for supplying negative electricity are cross-hatched, and those for supplying no electricity are white. As shown in  FIG. 5 , at time t 0 , when the digital input is −4, (Pa,Na)=(2,6) turns on two positive units and six negative units for generating a corresponding analog output. The assignment circuit  30   p  appoints switch elements E 1  and E 2  to supply positive electricity, and the assignment circuit  30   n  appoints switch elements E 3 -E 8  to supply negative electricity. At time t 1 , when the digital input is an odd number, −3, the pre-processing module  26  sets (Pa,Na)=(2,5) according S=M−1. In the embodiment of  FIG. 5 , the assignment circuit  30   p  appoints switch elements E 3 -E 4  to supply positive electricity by increasing index progressively, and the assignment circuit  30   n  appoints switch elements E 2 , E 1 , E 8 , E 7  and E 6  to supply negative electricity by decreasing index progressively.  
         [0039]     At time t 2 , when the digital input is −2, the pre-processing module  26  sets (Pa,Na)=(3,5) according to S=M. The assignment circuit  30   p  appoints switch elements E 5 -E 7  to supply positive electricity by increasing index progressively, and the assignment circuit  30   n  appoints switch elements E 5 -E 1  to supply negative electricity by decreasing index progressively. At time t 3 , the digital input is an odd number −1, and the pre-processing module  26  sets (Pa,Na)=(4,5) according to S=M+1 due to the preceding odd digital input D being the first value S=M−1. Then, the assignment circuit  30   p  appoints switch elements E 8 , E 1 , E 2 , and E 3  to supply positive electricity by increasing index progressively, and the assignment circuit  30   n  appoints switch elements E 8 -E 4  to supply negative electricity by decreasing index progressively.  
         [0040]     As shown in  FIG. 5 , every time processing an odd input, the present invention exchanges S=M−1 or S=M+1 alternately. At time t 11  and t 12 , the digital inputs are both +1. At time t 11 , (Pa,Na)=(5,4) according to S=M+1; but at time t 12 , (Pa,Na)=(4,3) according to S=M−1. In conclusion, some three-level switch elements supply units of positive electricity and other three-level switch elements supply units of negative electricity at the same time, however, the sum of units of positive electricity and units of negative electricity is equal to the corresponding digital input D in different time.  
         [0041]     When one unit of positive electricity Ip mismatches one unit of negative electricity −In, the balance electricity (Ip−In)/2 represents the value 0. Switch elements only provide the enable common-mode electricity (Ip−In) or the disable common-mode electricity 0 as the value 0. For lowering the gain error, the enable common-mode electricity or the disable common-mode electricity is used as the value 0 alternately. In the embodiment of  FIG. 5 , the present invention is capable of balancing the apparent frequency of the enable common-mode electricity and the disable common-mode electricity. For example, at time t 0 , when the digital input is −4, all switch elements supply a unit of electricity only, and no switch elements supply the enable common-mode electricity or the disable common-mode electricity. At time t 2 , when the digital input is −2, the switch element E 8  turns off both positive and negative units for supplying the disable common-mode electricity as the value 0, and the switch element E 5  turns on both positive and negative units for supplying the enable common-mode electricity as the value 0.  
         [0042]     If the digital input is odd, a long-term average is used to balance the enable common-mode electricity and the disable common-mode electricity. At time t 1 , when the digital input is an odd number, −3, the switch element E 5  uses disable common-mode electricity as value 0; but at time t 3 , when the digital input is a next odd number, the switch element E 8  uses enable common-mode electricity as value 0 for balancing the preceding disable common-mode electricity. At time t 5 , when the digital input is an odd number, 1, the switch element E 4  uses disable common-mode electricity as value 0; but at time t 7 , when the digital input is a next odd number, the switch element E 1  uses enable common-mode electricity as value 0 for balancing the preceding disable common-mode electricity. For lowering the gain error, the enable common-mode electricity or the disable common-mode electricity is used as the value 0, alternately.  
         [0043]     The present invention works well in an over-sampling digital-analog converter system. In an over-sampling digital-analog converter system, the sampling rate of a signal is much higher than the frequency of the signal. Alternating the disable common-mode electricity and the enable common-mode electricity with a high sampling rate converts the gain error into high-frequency noise, which is out of the bandwidth of the signal. The assignment circuit  30   p  and  30   n  appoint different switch elements to supply electricity. Then, the mismatch between switch elements is converted into high-frequency noise. Therefore, the present invention works well in a digital-analog converter system for raising the SNR and lowering the effect caused by gain error and mismatch.  
         [0044]     Please refer to  FIG. 6  and  FIG. 5 .  FIG. 6  is a diagram that shows a realization of the over-sampling D/A converter system  20  in  FIG. 5 . As shown in  FIG. 6 , the input circuit  22  is a sigma-delta converter, including two processing modules  34  and  36 , and a quantizer  38 . The processing module  34  is a loop filter, such as an integrator; and the processing module  36  is a gain adjustment circuit or other essential circuit. Inside the input circuit  22 , the output signal Y of the quantizer  38  is fed back via the processing module  36  and then subtracted from the signal X. The result of the subtraction is accumulated with the processing module  34 . The signal Y is compensated through the feedback path for tracking the variation of the signal X continually. The signal Y is a digital input of the digital-analog circuit  32 .  FIG. 6  shows an embodiment of a digital-analog converter circuit. Each switch element E 1 -En includes a positive current source, a negative current source, and two transistors Kp and Kn as switches. The positive current source supplies a current Ip through Kp to the node N 0  as positive electricity, and the negative current source supplies a reverse current In through Kn to the node N 0  as negative electricity. Turning on or off the transistors Kp and Kn supplies positive electricity, supplies negative electricity, enables common-mode electricity, or disables common-mode electricity. The output circuit  40  is an operational amplifier for collecting all electricity to generating analog outputs.  
         [0045]     According to further data analysis, the signal-noise ratio in the present invention is improved 20 to 30 dB in comparison to the prior art. The present invention is capable of reducing the gain error and mismatch error to first-order error for lowering the effects of the errors. The so-called first-order error is that the present invention makes the gain error and mismatch error become 9 dB/octave high-frequency noise in a double-exponential power spectrum. The gain error and the mismatch error are transformed into high frequency errors, distributed apart from the bandwidth of signal, resulting in a better signal-noise ratio and an increased linearity of D/A converting. Furthermore, the present invention is realized by a simple circuit that increases the capability of the digital-analog converter system with lower cost. The assignment circuits  30   p  and  30   n  in  FIG. 3  follow the assignment circuit of DDWA. Each function block in  FIG. 3  is realized with hardware or firmware. For example, the common-mode adjustment module  24  is a simple register. When the digital input is odd, +1 and −1 are interchanged as S=M+1 or S=M−1. The pre-processing module  26  for determining the value of (Pa,Na) is realized with a look-up table, that is, the corresponding (Pa,Na) are recorded as a table such as in  FIG. 4 . Furthermore, M is assumed even in  FIG. 3 - FIG. 5 . If M is an odd number, when the digital input D is odd, S=M; but when the digital input D is even, S=(M+1) or S=(M−1).  
         [0046]     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.