Abstract:
A received signal strength indicator (RSSI) receives an input voltage. The input voltage is amplified by a cascade of voltage amplifiers. The output of each amplifier is squared by a squarer. The output of each squarer is then compared to an array of fixed values from a strictly monotonic sequence. The comparators outputs are fed to a digital thermometer decoder, the outputs of which represent the binary coded, arbitrarily shaped RSSI. The squarer can be implemented using two MOS transistors, and has a current output. The comparators can be implemented using multiple current mirrors.

Description:
BACKGROUND 
     This invention relates to the field of electronic signal processing, and more specifically to a received signal strength indicator (RSSI) with an arbitrarily shaped transfer function. 
     An RSSI circuit measures the instantaneous power of a time-varying electrical signal, usually a voltage. 
     RSSI circuits usually comprise a voltage squarer, followed by a low-pass filter which removes the spectral content located at twice the modulating frequency and above. The output of the RSSI is usually a voltage, proportional to the instantaneous power of the input signal. Hence, these circuits provide a linear relationship between the output and the power of the input signal. In many applications, it is however desirable to obtain a non-linear such relationship. In the art logarithmic amplifiers are known, which shape the input power by a logarithmic transfer function, which is a particular case of a non-linear function. It is desirable to create a circuit which shapes the power of the input signal according to an arbitrary monotonic function. A conventional solution uses an A/D converter which digitizes the linear RSSI, and then applies to it an arbitrary transfer function in the digital domain. This solution has the drawback of complexity and high power consumption, since both the analog RSSI circuit and the A/D must have a full-scale high enough to handle signals covering the entire required dynamic range, and a resolution such that it is able to discriminate the smallest difference required by the transfer function. 
     It would be desirable, therefore, to create an arbitrarily shaped RSSI circuit which does not require a high-resolution ADC and uses low power. 
     SUMMARY 
     Aspects of the invention include a circuit comprising a cascade of voltage amplifiers. A cascade of RSSI blocks, each RSSI block being connected to the output of one of the voltage amplifiers. The output of each RSSI block is a current which is further compared to each current from a range of currents. The results of these comparisons are digital signals which are fed into a digital thermometer decoder. The output of the digital thermometer decoder represents binary code of the arbitrarily shaped RSSI. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing aspects and advantages of the present invention will become better understood upon reading the following detailed description and upon reference to the drawings where: 
         FIG. 1  shows the block diagram of an arbitrarily shaped RSSI circuit, according to some embodiments of the invention. 
         FIG. 2  shows the schematic of a voltage squarer, according to some embodiments of the invention. 
         FIG. 3  shows the schematic of an array of current comparators, according to some embodiments of the invention. 
         FIG. 4  shows the schematic of an array of current comparators, comprising a low-pass filter coupled to the input current, according to some embodiments of the invention. 
         FIG. 5  shows the schematic of an array of current comparators, comprising a low-pass filter coupled to a current mirror mirroring the input current, according to some embodiments of the invention. 
         FIG. 6  shows the transfer function of the binary coded, arbitrarily shaped RSSI circuit. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The following description illustrates the present invention by way of example and not necessarily by way of limitation. Any reference to an element is understood to refer to at least one element. A set of elements is understood to include one or more elements. Any recited connection is understood to encompass a direct operative connection or an indirect operative connection through intermediary structure(s). 
       FIG. 1  shows the block diagram of an arbitrarily shaped RSSI circuit. The input voltage  101  is amplified by a cascade of n voltage amplifiers ( 102 ,  103 ,  104 ), each voltage amplifier having a gain voltage Gi. The output of each voltage amplifier is applied to a squarer circuit ( 105 ,  106 ,  107 ). The squarers must be responsive only to the AC content of the input, hence the signals coming from the amplifiers must be DC-blocked ( 122 ,  123 ,  124 ). The output of each of the squarer circuits is a signal S ( 114 ,  115 ,  116 ), which can be a current or a voltage. If the instantaneous voltage at the input of a squarer is Vin, then the output of the squarer is: S=SConstant+Prop*Vin*Vin, where SConstant and Prop are constants depending upon the particular implementation of the squarer. The output of each squarer is applied to a comparing block, the i-th comparing block comprising an array of mi individual comparators, wherein in the j-th said individual comparator of the i-th comparing block, the input signal S is compared to a fixed value Sij. The Sij fixed values are strictly increasingly monotonic within each comparing block, and from one comparing block to the next right comparing block. This can be expressed mathematically:
 
S 11 &lt;S 12 &lt; . . . &lt;S 1,m     1   &lt;S 21 &lt;S 22 &lt; . . . &lt;S 2,m     1   &lt; . . . &lt;S n1 &lt;S n2 &lt; . . . &lt;S n,m     j    
 
The outputs of the comparing blocks are digital signals. These outputs of the comparing blocks are applied to a digital thermometer decoder. The output of the thermometer decoder is therefore a digital, binary-coded representation of the arbitrarily shaped RSSI circuit.
 
     In the art, a digital thermometer decoder is a digital block having an array of inputs and an array of outputs. It is required that the signals presented at the array of inputs must be all logic one up to a certain index, and then all zero. The output of the thermometer decoder then indicates the highest index of an input which is a logic one. For example, if the input is 000011111, then the output is 0101. 
     Also referring to  FIG. 1 , the fixed values Sij are chosen such that the numbers (Sij−Sconstant)/Gi/Gi approximate the desired transfer function of the arbitrarily shaped RSSI target curve. The said numbers (Sij−Sconstant)/Gi/Gi must be adjusted accordingly if the n squarers are not identical. 
     Also referring to  FIG. 1 , it will be clear to an artisan that the squarers  105 ,  106 ,  107  will provide an accurate and useful representation of the power of the input signal only if the said input signal is a “baseband” one, in the sense of not being modulated in amplitude. If the input signal is modulated in amplitude and the circuit is desired to output the RSSI of the modulating signal (“envelope”), then a low-pass filter must be included between each squarer and each comparing block connected to the said squarer. 
     Also referring to  FIG. 1 , it will be clear to an artisan that the squarers  105 ,  106 ,  107  must be accurate only in the range of outputs Si 1  to Si,mi. However, the said squarers must be monotonic over the entire range of the input signal. 
     Also referring to  FIG. 1 , in some embodiments the voltage amplifiers  102 ,  103 ,  104  will be differential (having a differential input and a differential output) and the squarers  105 ,  106 ,  107  will have a differential input. 
       FIG. 2  shows the schematic of a squarer. In this embodiment, the squarer is implemented using NMOS transistors. A similar embodiment is using PMOS transistors instead. The differential input voltage between pins  201 ,  202  is AC-coupled to the gates of  210 ,  211 . Transistors  210  and  211  are DC-biased into the saturation zone, hence exhibiting an instantaneous drain current which is substantially a quadratic function of its gate voltage. The instantaneous output current  205  can then be described by: Iout=IConstant+Prop*Vin*Vin. 
       FIG. 3  shows the schematic of a comparing block. The input current  301  is mirrored m times by transistors  303 ,  304 ,  305  using unitary mirroring coefficients. A reference current  310  is mirrored m times by transistors  312 ,  313 ,  314  using mirroring coefficients (a 1 , a 2 , an) proportional to Si 1 , Si 2 , . . . Si,mi (for the i-th comparing block). In  FIG. 3 , the mirroring coefficients are obtained by designing accordingly the dimensions (width and length) of the mirroring transistors. In other embodiments, multiple mirroring or other techniques known in the art may be used. 
     Also referring to  FIG. 3 , the drain currents flowing from each transistor  303 ,  304 ,  305  copying the input current are compared to the drain current from a transistor  312 ,  313 ,  314  mirroring the reference current. A current comparator is thus implemented, having as output the common voltage of the two drains. The digital outputs  341 ,  342 ,  343  are obtained after the inverters  333 ,  334 ,  335 . 
     Also referring to  FIG. 3 , it is clear that the current mirrors can be cascoded, or realized with other techniques known in the art. 
     If the input signal  101  is amplitude-modulated and it is desired to determine the RSSI of the modulating signal, then the input current  301  of  FIG. 3  must be averaged. In one embodiment shown in  FIG. 4 , the current  401  is passed through the low-pass filter  451 . In another embodiment shown in  FIG. 5 , since it is sometimes difficult to design a current low-pass filter, the low-pass filter  551  can be applied to the voltage of the gate of the transistor  502 . The disadvantage of the solution from  FIG. 5  is that the currents mirrored by transistors  503 ,  504 ,  505 , are no longer exact representations of the average of the input current  501 ; however, in many applications the error such made can be tolerable. 
     It will be clear to a skilled artisan that the inventions disclosed in  FIGS. 2-5  can be implemented using complementary type transistors (PMOS instead of NMOS, and NMOS instead of PMOS). 
       FIG. 6  shows the transfer function of the binary coded, arbitrarily shaped RSSI circuit disclosed in  FIG. 1 . The x axis ( 601 ) depicts the squared voltage of the input signal if the said input signal is not-amplitude modulated (“baseband”), or the squared voltage of the amplitude-modulating signal (“envelope”) otherwise. On the y axis the toggling thresholds of the digital outputs of the n comparing blocks are shown ( 602 ). The binary coded output  603  is also shown. The staircase transfer function  604  is an approximation of the desired, arbitrarily shaped function  605 . 
     It will be clear to one skilled in the art that the above embodiments may be altered in many ways without departing from the scope of the invention. Accordingly, the scope of the invention should be determined by the following claims and their legal equivalents.