Abstract:
A single-path enhanced-algorithm digital automatic gain control (SDAGC) integrated receiver is presented. The SDAGC has a front-end RF/IF reception/processing block and associated RF/IF AGC, which outputs to a single ADC. Output from the ADC is split into two TDM and one COFDM signal pathways, each with a respective DAGC. The TDM DAGCs are controlled according to TDM post-power signals, while the COFDM, DAGC is controlled according to COFDM post- and pre-power signals. An IF Gain Decision block determines the RF/IF gain based upon the respective gains of the TDM and COFDM DAGCs. A Gain Distributor block then distributes the total gain of the system across the RF/IF AGC and the various DAGCs. To save power, the COFDM pathways may be disabled if the COFDM pre-power signal falls below a threshold value.

Description:
FIELD OF THE INVENTION 
   The present invention is generally directed to digital radio service reception and enhancement, and more particularly to a method and apparatus for a single-path enhanced-algorithm digital automatic gain control integrated receiver for receiving non-ionizing radiation waves in the electromagnetic spectrum. 
   BACKGROUND OF THE INVENTION 
     FIGS. 1 and 2  taken together illustrate in block diagram format the current structure of a car&#39;s audio receiver found in a Sirius™ Satellite Digital Audio Radio Service (SDARS) system (operating in the radio frequency (RF) spectrum 2.3-GHz “Short wave” S band, from 2320 to 2345 MHz). The SDARS system has two separate front end RF signal receiving paths, one acting as a time division multiplexing (TDM) receiver (shown in  FIG. 1 ) and the other acting as a coded orthogonal frequency division multiplexing (COFDM) receiver (shown in  FIG. 2 ). Thus the current system requires two separate automatic gain control (AGC) controllers, a TDM AGC and a COFDM AGC, to maintain for independent demodulation the received RF signal&#39;s corresponding signal levels (respectively referred to hereinafter as “SetPoint_TDM_dB_LSB” and “SetPoint_OFDM_dB_LSB”). 
   Referring now specifically to  FIG. 1 , the TDM integrated receiver  1  of the SDARS is constructed of well-known electronic circuitry devices. RF signals (consisting of multiple digital signals or analog signals carrying digital data) are received by the TDM antenna  2  and routed to an antenna RF processing circuit  3  and an RF/IF processing circuit  4  where decoding of the radio signals begins. Input control of the automatic gain control of both the RF signals and intermediate frequency (IF) signals is handled by the TDM AGC controller  5 . TDM AGC covers a dynamic power range for the TDM received RF signal of up to 75 dB. The TDM receiver signal path has a signal set-point value level defined as SetPoint_TDM_dB_LSB=(9.2+1.2) dB and this allows enough headroom to avoid any saturation happening at a 10-bit analog to digital converter (ADC)  6 , which converts the RF signals to discrete digital numbers, even during TDM on-channel blocking. 
   After analog to digital conversion, the TDM received RF signal is routed to a digital down converter (DDC)  7  where it is split into two separate signals labeled as TDM 1  and TDM 2  as shown. The two signals are then separately demodulated by TDM 1  demodulator  8  and TDM 2  demodulator  9 , respectively. The TDM received RF demodulated signal, indicated on  FIG. 1  by reference labels TDM 1  post-power and TDM 2  post-power, are routed to the maximal function  10 , which selects the maximal post power of TDM 1  and TDM 2  for output. 
   Hence, as can be seen for the TDM AGC, computation of the AGC gains required for the respective RF and IF processing circuits  3  and  4  are based solely upon the post-power level of TDM received RF signal after the maximal function  10 . 
   With regard to control of the RF AGC gain in the TDM integrated receiver  1  of the SDARS, three rfstates (−1, 0, 1) are implemented with the initial state of the rfstates being set to 0. Any change of the rfstates depends on the information of the RF detector/direction sent from RF processing circuit  3 . Additionally the step-size is 10 dB, and this means the RF AGC gain may be −10 dB, 0 dB or +10 dB. The IF AGC gain, on the other hand, ranges from −27.5 dB to +27.5 dB in 1 dB step-size. A Least Mean Square (LMS) algorithm is implemented to update the IF AGC gain. Both the RF AGC gain and the IF AGC gain are updated at 100 Hz normally, however, the updating frequency of the RF/IF AGC gains is reduced to 50 Hz to avoid problems associated with overshooting when the RF AGC gain changes. 
   Referring now specifically to  FIG. 2 , the COFDM integrated receiver  11  of the SDARS is likewise constructed of well-known electronic circuitry devices. After receipt of the COFDM RF signal (consisting of broadcast digital audio and/or video signals (DAB and DVB-T)) from the COFDM antenna  12 , the antenna RF processing circuit  13 , RF/IF processing circuit  14 , 10-bit ADC  16 , DDC  17  and COFDM demodulator  18  all operate similarly to their cousins in the TDM integrated receiver, albeit with the COFDM demodulator  18  utilizing Fast Fourier Transform implementations for integration purposes. COFDM AGC, however, covers a dynamic power range for the COFDM received RF signal of up to 131 dB, and the set-point values in COFDM pre-power and post-power are (32.2+3.0+10=45.2 dB) and (32.2+3.0=35.2 dB), respectively. The pre-power, which includes the power of un-used tones, interference noise and others, is set to 10 dB higher than the post-power. 
   Hence, as can be seen for the COFDM AGC, computation for the COFDM AGC controller  15  to adjust the gain levels in RF and IF processing circuits  13  and  14  require both pre-power input from the DDC  17  and post-power input from COFDM demodulator  18 . 
   With regard to control of the RF AGC gain in the COFDM integrated receiver  11  of the SDARS, five rfstates (1, 2, 3, 4, 5) are implemented with the initial state of the rfstates being set to 3. Any change of rfstates depends on the information of RF detector/direction from RF processing circuit  13 . Additionally the step-size is 15 dB, and this means the RF AGC gain may be −30 dB, −15 dB, 0 dB, +15 dB or +30 dB. The IF AGC gain, on the other hand, ranges from −35.5 dB to +35.5 dB with a 1 dB step-size. An LMS algorithm is implemented to update the IF AGC gain. Both RF AGC gain and IF AGC gain are updated at 100 Hz normally, however, the updating frequency for the RF/IF AGC gains is reduced to 50 Hz to avoid overshooting problem while the RF AGC gain changes. 
   As can be seen then, two independent ADC controllers are needed by the SDARS system to complete the signal processing and maintain adequate performance over a range of input signal levels. Power consumption by the system, relatively speaking, is high, and operational specifications indicate there is room for increased performance. The next generation SDARS systems will need to provide better performance with lower power consumption characteristics at reduced costs. 
   SUMMARY OF THE INVENTION 
   Accordingly, the present invention addresses these problems by employing a new single-path enhanced-algorithm digital automatic gain control (SDAGC) integrated receiver circuit. 
   The SDAGC circuit has a digital automatic gain control (DAGC) circuit that has a single-path circuit architecture, thereby eliminating the need for dual Antenna RF Processors, dual RF/IF Processors and dual ADCs, and which thereby leads to lower manufacturing costs and reduced power consumption. In addition, the SDAGC circuit also has an enhanced algorithm for gain control computation in the AGC controllers (which allows for XM satellite radio channel interference handling while boosting XS satellite radio channel reception), thus leading to improved system performance, and has a power estimation algorithm to allow for the enabling/disabling of the COFDM receiver for power consumption purposes. 
   The present invention, including its features and advantages, will become more apparent from the following detailed description with reference to the accompanying drawings. 

   
     DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is an illustration in block diagram of a time division multiplexing RF front end signal path for a Satellite Digital Audio Radio Service, according to the prior art. 
       FIG. 2  is an illustration in block diagram of a coded orthogonal frequency-division multiplexing RF front end signal path for a Satellite Digital Audio Radio Service, according to the prior art. 
       FIG. 3  is an illustration in block diagram of the architecture of a single path digital automatic gain control circuit, according to an embodiment of the present invention. 
       FIG. 4  is an illustration of a flowchart of the enhanced algorithm methodology utilizing by a single path digital automatic gain control circuit, according to an embodiment of the present invention. 
   

   DETAILED DESCRIPTION 
     FIGS. 3 and 4  illustrate the device architecture and corresponding software algorithm flowcharts of a single-path enhanced-algorithm digital automatic gain control (SDAGC) circuit for a next generation SDARS system that has improved system performance, a lower power consumption and a lower manufacturing cost than the current systems. 
   As can be seen from a comparison of the architecture shown in  FIG. 3  with the combined architecture of  FIGS. 1 and 2 , the SDAGC circuit has fewer electronic device components at the front end of the processing circuit. That is, the chips required by the prior art for the antenna, antenna RF processing and RF/IF processing of the COFDM system are eliminated. 
   Additionally, the SDAGC circuit has only one ADC to handle both the TDM RF and COFDM RF signal paths. The resultant single path circuit architecture of the DAGC in the next-generation SDARS system is accomplished by the use of enhanced algorithms implemented in software, in either an ASIC or C programming language (or the like), in 32-bit advanced RISC machine (ARM) processors, or any other suitable processor. The ARM performs AGC control by monitoring signal levels at several points in the system, executing a gain control algorithm, and then applying the resulting gain settings to the RF and IF ASICs. Multiple processors allow for the algorithms to be run in parallel, thus taking advantage of the circuit architecture (i.e., allowing for several processors to work on the differing algorithms at the same time, and even divide information amongst themselves into more symmetrical or asymmetrical sub-problems to combine the results back together at one end). Accordingly, AGC control for the TDM and COFDM signal paths may be performed independently, despite the presence of a single front-end for both the TDM and COFDM pathways. 
   Referring now specifically to  FIGS. 3 and 4 , operation of the SDAGC circuit  1000  and the processing algorithms  2000  will now be detailed. To maintain the full dynamic range of a combined signal of TDM 1 /TDM 2  and COFDM, the circuitry will be simplified as the RF and IF AGC have +/−10 dB and +/−35.5 dB ranges respectively. 
   RF processing begins at the output of the combined TDM/COFDM antenna  30 , which is capable of receiving satellite (TDM) pickup and terrestrial (COFDM) pickup. The antenna output is fed to the antenna RF processing circuit  31  where each of the TDM and COFDM signals are passed through a low noise amplifier (LNA) and RF filter. The LNA is AGC controlled. 
   Control of the RF AGC gain is implemented upon initialization of the algorithm in step  100 . Therein three rfstates (−1, 0, 1) are implemented to control RF AGC gain, with the initial state of the rfstates being set to 0. Change of rfstates depends on the information of the RF detector/direction sent from the RF processing block  31 . As accomplished by the algorithm below, the RF AGC gain is checked in step  130  and updated in step  160 .
         Step  100 : Set initial value: Rfstate_current=0.   Steps  130  and  160 :       

   
     
       
         
           Rfstate_next 
           = 
           
             { 
             
               
                 
                   
                     
                       
                         Rfstate_current 
                         ++ 
                       
                     
                     
                       
                         
                           if 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           direction 
                         
                         == 
                         1 
                       
                     
                   
                   
                     
                       
                         Rfstate_current 
                         -- 
                       
                     
                     
                       
                         
                           if 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           direction 
                         
                         == 
                         
                           - 
                           1 
                         
                       
                     
                   
                 
                 ⁢ 
                 
                   
 
                 
                 ⁢ 
                 Rfstate_next 
               
               = 
               
                 { 
                 
                   
                     
                       1 
                     
                     
                       
                         
                           if 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           Rfstate_next 
                         
                         ≥ 
                         1 
                       
                     
                   
                   
                     
                       
                         - 
                         1 
                       
                     
                     
                       
                         
                           if 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           Rfstate_next 
                         
                         ≤ 
                         
                           - 
                           1 
                         
                       
                     
                   
                 
               
             
           
         
       
     
       
       
         
           Rfstate_current=Rfstate_next for the next updating. 
         
       
     
  
           Rfgain   =     {           10   ⁢           ⁢   dB             if   ⁢           ⁢   Rfstate_current     ==   1               0   ⁢           ⁢   dB             if   ⁢           ⁢   Rfstate_current     ==   0                 -   10     ⁢           ⁢   dB             if   ⁢           ⁢   Rfstate_current     ==     -   1                     
As shown, the step-size is 10 dB, and this means the RF AGC gain may be −10 dB, 0 dB or +10 dB. At this point in the RF processing the signals are at a first IF of 315 MHz.
 
   IF processing begins as each amplified and filtered signal is then sent to the RF/IF processing circuit  32 . The signals are passed through an IF AGC amplifier, IF filter, and first down-converter to a final IF of 75 MHz. The IF AGC gain ranges from −35.5 dB to +35.5 dB with 1 dB step-sizes. The IF filters for the COFDM signal will have a narrower bandwidth than the IF filters for the TDM path allowing reception of the COFDM signal in a harsher interference environment than the TDM signals. The COFDM filter bandwidths can be on the order of 4.2 MHz, while the TDM filters must have a 12.5 MHz bandwidth in order to pass both TDM signals. 
   The TDM and COFDM signals, having been band-pass filtered and AGC amplified, are applied to the 10-bit ADC  33 . Here the signals are converted to a 10-bit digital signal sampled at 60 MHz. It is to be understood, of course, that a 12-bit resolution ADC may also be used. As the TDM signal has been separated into its two components (TDM 1 , TDM 2 ), three digital AGCs (DAGC)  34 ,  35  and  36  are used to adjust the now three input signals (TDM 1 , TDM 2  and COFDM) to the required levels for the corresponding TDM 1 , TDM 2  and COFDM systems. The DAGCs are actually multipliers. 
   Thereafter the two signals TDM 1  and TDM 2  are passed through TDM DDC  40  and the COFDM signal is passed through COFDM DDC  41 . Each of the two DDCs separates the two TDM sub-bands and COFDM, respectively, from the full 12.5 MHz Sirius™ Satellite Radio signal bandwidth. In other words, each pass band signal is brought to a base band signal so that the three signals can be applied to the appropriate digital receiver processing chain. Such conversion is accomplished through a combination of Hilbert transformation, band-shifting, fixed decimation, and controlled variable re-sampling. 
   Each signal, having passed through their respective DDC, is passed to a demodulator. TDM 1  is passed through TDM 1  Demodulator  42 , TDM 2  is passed through TDM 2  Demodulator  43 , and the COFDM signal is passed through COFDM Demodulator  44 . The front end of the TDM demodulator  42 ,  43  is a matched filter, which is a symmetrical root-raised cosine filter, while the COFDM demodulator  44  is an FFT-based receiver. 
   The TDM demodulators  42  and  43  extract soft QPSK symbols in (I,Q) format from the input sample stream using a synchronous receiver. In so doing, it accomplishes the major functions common to most such demodulators by performing: matched filtering; timing error detection; frame synchronization; carrier synchronization; decision feedback equalization; and timing and framing acquisition. 
   The COFDM demodulator  44  extracts soft QPSK symbols in (I,Q) format from the input sample stream using an FFT-based receiver. Sub-functions employed in the basic demodulation process are: timing error detection; frequency offset detection (gross and fine); frequency offset compensation; Fourier transformation with time and frequency pruning; carrier synchronization and differential demodulation; frequency de-interleaving; and QPSK phase correction. 
   Processing DAGC control by TDM 1  DAGC controller  50 , TDM 2  DAGC controller  51 , and COFDM DAGC controller  52  is discussed next. These DAGC controllers update the gains of the TDM 1 , TDM 2  and COFDM single paths to achieve the input signal of the corresponding path to the respective reference level. Both TDM 1  and TDM 2  only use a same reference level for the post-power. The COFDM path uses pre-power and post-power reference levels to monitor its pre-power and post-power signals. 
   TDM DAGC processing control occurs in the TDM 1  DAGC controller  50  and the TDM 2  DAGC controller  51  in parallel processing in steps  200 - 250 . In steps  200  and  210  the lockflag is detected through the following algorithm: 
   
     
       
             
           
         
             
                 
             
           
           
             
               Initial value: LockFlag = 0. 
             
             
               The value of LockFlag in other state is updated in the following steps: 
             
             
               InSignal = InputPower − TDMSetPoint 
             
             
               InSignal = ((InSignal &gt; 0) ? − InSignal : InSignal) 
             
             
               if (LockFlag == FALSE) 
             
             
                if (InSignal &gt; LIMIT_OUT_OF_LOCK) 
             
             
                 LockFlag = TRUE 
             
             
               else 
             
             
                if (InSignal &lt; LIMIT_IN_LOCK) 
             
             
                 LockFlag = FALSE 
             
             
                 
             
           
        
       
     
   
   In steps  220  and  230 , a TDM 1 /TDM 2  GainBoost routine is run to generate the value of the step-size in order to update, in steps  240  and  250 , the TDM 1 /TDM 2  Gain Routine for changing the total gain of TDM  1  and TDM 2 . The GainBoost routines, in steps  220  and  230 , bases upon the information of TDM 1 /TDM 2  post-power changes to classify the AGC system to be one of acquisition, transition or steady states. Each state of acquisition, transition and steady states generates its own specific step-size for AGC routine to update the AGC gain. Of course, the step-size of acquisition state will be higher than that of steady state. 
   COFDM DAGC processing control occurs in the COFDM controller  52  in processing steps  300 - 330 . In step  300  the lockflag is detected through the following algorithm: 
   
     
       
             
           
         
             
                 
             
           
           
             
               Initial value: LockFlag = 0. 
             
             
               The value of LockFlag in other state is updated in the following steps: 
             
             
               InSignal = InputPower − COFDMSetPoint 
             
             
               If (fabs(InSignal) &lt; 20.0) 
             
             
                LockFlag = 1 
             
             
               else 
             
             
                LockFlag = 0 
             
             
                 
             
           
        
       
     
   
   In steps  310  and  320 , COFDM GainBoost routine is run to generate the value of the step-size in order to update, in step  330 , the COFDM Gain Routine for changing the total gain of COFDM. 
   The main TDM DAGC control circuit  53  determines the necessary gain for the IF AGC to reach an high overall performance for the TDM system. The decision is based upon input of the XM interference factor, TDM 1  gain and TDM 2  gain. 
   In step  260 , an algorithm is run that determines the value for the gain of the IF AGC based upon the total gains of TDM 1  and TDM 2  in conjunction with the information of XM interference at TDM 2 . The algorithm for such is shown in the following: 
   
     
       
             
           
         
             
                 
             
           
           
             
               if (( ftdm1DagcUpdate − ftdm2DagcUpdate ) &lt; JT _INT ) { 
             
             
                if ( ftdm1DagcUpdate &gt; ftdm2DagcUpdate ) 
             
             
                 max ftdmDagcUpdate = ftdm2DagcUpdate 
             
             
               } 
             
             
               else if (( ftdm1DagcUpdate − ftdm2DagcUpdate ) &lt; M2JT _INT ) { 
             
             
                max ftdmDagcUpdate = ( ftdm1DagcUpdate + ftdm2DagcUpdate ) / 2 
             
             
               } 
             
             
               else { 
             
             
                max ftdmDagcUpdate = ftdm1DagcUpdate + M2JTADJUST _INT 
             
             
               } 
             
             
                 
             
           
        
       
     
   
   With the TDM IF gain and COFDM IF gain derived from the above algorithms, the IF gain decision circuit  60  will decide what value of the actual IF gain will be allocated to the IF AGC. After the actual IF gain is determined, the gain distributor circuit  61  is responsible for distributing the remaining gain of the TDM 1 , TDM 2  and COFDM signal paths into their corresponding DAGC  34 ,  35  and  36 . At the same time, the gain distributor circuit  61  also determines whether or not to turn off the COFDM path based upon the COFDM gain. A similar concept can be applied to the TDM system too. Thus, the TDM system can be turned off in a strong COFDM area. 
   In step  400 , the following algorithm distributes the total gain of each path (TDM  1 , TDM 2  and COFDM) into one IF gain and its corresponding DAGC, and, at the same time, also determine whether or not to turn off the operation of COFDM system based upon the total gain of the COFDM: 
   
     
       
             
             
           
         
             
                 
                 
             
           
           
             
                 
               if (Cofdm PrePower≧EnableCofdmThreshhold) { 
             
             
                 
                PowerManagementEnable=0 
             
             
                 
               } 
             
             
                 
               else { 
             
             
                 
                PowerManagementEnable=1 
             
             
                 
               } 
             
             
                 
               if(PowerManagementEnable=0) { 
             
             
                 
                If ( fcofdmDagcUpdate≦ COFDM _GAIN_THRESHOLD\) { 
             
             
                 
                 IF_Gain=max ftdmDagcUpdate 
             
             
                 
                } 
             
             
                 
               else if (COFDM_GAIN_THRESHOLD\&lt; 
             
             
                 
                 fcofdmDagcUpdate≦COFDM_GAIN_THRESHOLD2) 
             
             
                 
                 IF_Gain=(maxftdmDagcUpdate+ fcofdmDagcUpdate)/2 
             
             
                 
               else 
             
             
                 
                 IF_Gain=fcofdmDagcUpdate 
             
             
                 
                cofdmDagcUpdate = fcofdmDagcUpdate − IF _Gain 
             
             
                 
                tdm1DagcUpdate = ftdm1DagcUpdate − IF _Gain 
             
             
                 
                tdm2DagcUpdate = ftdm2DagcUpdate − IF _Gain 
             
             
                 
               } 
             
             
                 
               else { 
             
             
                 
                IF _Gain = max ftdmDagcUpdate 
             
             
                 
                tdm1DagcUpdate = ftdm1DagcUpdate − IF _Gain 
             
             
                 
                tdm2DagcUpdate = ftdm2DagcUpdate − IF _Gain 
             
             
                 
               } 
             
             
                 
                 
             
           
        
       
     
   
   Thus, as can be seen from the above disclosure, the present invention clearly and conclusively improves system performance, has a lower power consumption and a lower manufacturing cost than the current systems. 
   In the foregoing description, the method and apparatus of the present invention have been described with reference to a specific example. It is to be understood and expected that variations in the principles of the method and apparatus herein disclosed may be made by one skilled in the art and it is intended that such modifications, changes, and substitutions are to be included within the scope of the present invention as set forth in the appended claims. The specification and the drawings are accordingly to be regarded in an illustrative rather than in a restrictive sense.