Abstract:
A high voltage CMOS output buffer is constructed from low voltage CMOS transistors. The output buffer employs a series of unique CMOS inverter stages, each of which contains a switched PMOS transistor, one or more voltage drop blocks, and a switched NMOS transistor. The voltage drop blocks are composed of stacked PMOS transistors that are diode-connected—i.e., the PMOS gate terminal is connected to the PMOS drain terminal, and the PMOS body (N-well) terminal is connected to the PMOS source terminal. The diode-connected PMOS transistors reduce the voltage across the transistor gate oxide to a safe value, for all internal PMOS/NMOS transistors inside the CMOS output buffer.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to CMOS output buffers, and more particularly, to a high voltage CMOS output buffer that is constructed from low voltage CMOS transistors. 
         [0003]    2. Description of the Related Art. 
         [0004]    CMOS processing rules are being continually scaled downward, producing smaller and faster transistors that have shorter channel lengths and lower threshold voltages. CMOS device scaling also offers other important advantages, including shorter interconnect wires that have lower capacitance, and the use of lower VDD voltages. 
         [0005]    The use of lower VDD voltages is extremely important, because it significantly decreases PWR DIG , the digital power dissipation inside the core of a CMOS chip. The formula for calculating PWR DIG  is shown in EQ. 1. 
         [0000]        PWR   DIG   =C*VDD   INT   2   *F    EQ. 1 
         [0000]    where C represents the average gate plus interconnect capacitance, VDD INT  represents the internal (digital core) power supply voltage, and F represents the average operating frequency of the logic gates inside the digital core. 
         [0006]    Referring to EQ. 1, it can be seen that CMOS device scaling reduces PWR DIG  in two ways. First of all, it lowers PWR DIG  by lowering the average gate plus interconnect capacitance C. Secondly, it again lowers PWR DIG  by allowing a lower VDD INT  voltage to be employed. Of course, because PWR DIG  depends upon the square of VDD INT , lowering VDD INT  makes the largest contribution to decreasing the power dissipation inside the digital core of a chip. 
         [0007]    Furthermore, since CMOS device scaling has been progressing at a very rapid rate, VDD INT  has also been decreasing at a very rapid rate. For example, in recent years, VDD INT  has progressed from 5V to 3.3V, from 3.3V to 2.5V, from 2.5V to 1V—and even lower. 
         [0008]    A basic problem, however, is that the standard system power supply voltage VDD SYS  has been decreasing at a much slower rate than VDD INT . For example, in current systems, the most widely used VDD SYS  voltages are still 5V and 3.3V. Because of this VDD disparity, CMOS I/O buffers must operate from the higher VDD SYS  voltage, while the CMOS logic gates inside the digital core must operate from the lower VDD INT  voltage. 
         [0009]    With regard to CMOS output buffers, the above VDD disparity can be resolved in two ways. In a first approach, only the system power supply voltage VDD SYS  is distributed to a CMOS chip. This approach is illustrated in  FIG. 1A , which shows a block diagram of a prior-art CMOS chip  100 . As shown in  FIG. 1A , since CMOS chip  100  only receives the system power supply voltage VDD SYS , CMOS chip  100  must contain an on-chip voltage regulator  110 . 
         [0010]    In this example, voltage regulator  110  is used to reduce the system power supply voltage VDD SYS  to the lower internal power supply voltage VDD INT . Furthermore, the internal power supply voltage VDD INT  is fed to a digital core  112 , which only contains low voltage CMOS transistors. In addition, the system power supply voltage VDD SYS  is also fed to an output buffer block  114 . Moreover, VDD SYS  and VDD INT  are both fed to a level shift-down block  116 , and to a level shift-up block  118 . As shown in  FIG. 1A , these level shift blocks act as voltage translators for the signals that go to and from digital core  112 . 
         [0011]    In a second approach, the higher system power supply voltage VDD SYS  and the lower internal power supply voltage VDD INT  are both distributed to a CMOS chip. This approach is illustrated in  FIG. 1B , which shows a block diagram of a prior-art CMOS chip  150 . As shown in  FIG. 1B , CMOS chip  150  receives the system power supply voltage VDD SYS  and the internal power supply voltage VDD INT . Therefore, CMOS chip  150  does not need an on-chip voltage regulator. In this example, the internal power supply voltage VDD INT  is directly fed to a digital core  152 , and the system power supply voltage VDD SYS  is directly fed to an output buffer block  154 . Furthermore, the VDD SYS  and VDD INT  voltages are both fed to a level shift-down block  156 , and to a level shift-up block  158 . 
         [0012]    The two approaches described above both require that the CMOS output buffers  114 / 154  operate from the higher VDD SYS  voltage. Thus, using prior art, this requirement is often satisfied by employing two transistor types: low voltage (low threshold) PMOS/NMOS transistors operating from VDD INT , and high voltage (high threshold) PMOS/NMOS transistors operating from VDD SYS . Referring to  FIGS. 1A and 1B , the low voltage transistors are used inside the digital core  112 / 152 , and the high voltage transistors are used inside the I/O cells  114 / 154 . 
         [0013]    Of course, fabricating low voltage CMOS transistors and high voltage CMOS transistors on the same chip increases CMOS processing complexity, which increases chip fabrication cost. Therefore, if the high voltage transistors could be eliminated, the chip fabrication cost could be substantially reduced. 
         [0014]    Furthermore, if the high voltage transistors could be eliminated, shift-up blocks  118 / 158  and shift-down blocks  116 / 156  could also be eliminated, further reducing the chip fabrication cost. Therefore, there is an obvious need for a method of implementing high voltage CMOS output buffers using only low voltage CMOS transistors. Two examples of this need include the ability to implement 5V output buffers using 3.3V transistors, and the ability to implement 3.3V output buffers using 2.5V transistors. 
         [0015]    CMOS transistors have four terminals: a gate terminal, a drain terminal, a source terminal, and a body (or substrate) terminal. In most CMOS processes, the NMOS transistors are not fabricated inside of wells. Therefore, the bodies of the NMOS transistors are formed by the p-substrate, which is usually grounded. 
         [0016]    Furthermore, in all CMOS processes, the PMOS transistors are always fabricated inside of N-wells, and the bodies of the PMOS transistors are formed by these N-wells. Thus, in order to avoid forward biasing the PMOS source/drain diodes, the PMOS N-wells are usually connected to the most positive voltage available, VDD. Since this connection is not mandatory, it is often permissible to connect the body (N-well) of a PMOS transistor to its own source terminal. 
         [0017]      FIGS. 2A-2B  show schematic diagrams that illustrate a prior-art PMOS transistor  200 , and a prior-art NMOS transistor  250 . As shown in  FIGS. 2A-2B , both transistors contain a gate terminal G, a drain terminal D, a source terminal S, and a body terminal B. As a result, there are six possible terminal-to-terminal voltages for PMOS transistor  200  and NMOS transistor  250 . The six possible terminal-to-terminal voltages include a drain-to-gate voltage V DG , a drain-to-source voltage V DS , a drain-to-body voltage V DB , a gate-to-source voltage V GS , a gate-to-body voltage V GB , and a source-to-body voltage V SB . 
         [0018]    Furthermore, when two or more of the transistor terminals are electrically connected together in an meaningful way, the number of transistor terminals will be reduced from four terminals to three terminals, or from four terminals to two terminals. As a result, the possible number of terminal-to-terminal voltage pairs will be reduced from six terminal pairs to three terminal pairs, or from six terminal pairs to one terminal pair. 
         [0019]    The reduction in the number of terminal-to-terminal voltage pairs is illustrated in  FIGS. 3A-3D  and  4 A- 4 D.  FIGS. 3A and 4A  show schematic diagrams that illustrate prior-art PMOS transistor  200  and NMOS transistor  250 , with the body connected to the source. In this case, the source-to-body voltage V SB  is zero, the gate-to-source voltage V GS  and the gate-to-body voltage V GB  are the same, and the drain-to-source voltage V DS  and the drain-to-body voltage V DB  are also the same. 
         [0020]      FIGS. 3B and 4B  show schematic diagrams that illustrate prior-art PMOS transistor  200  and NMOS transistor  250 , with the gate connected to the drain. In this case, the gate-to-drain voltage V GD  is zero, the drain-to-source voltage V DS  and the gate-to-source voltage V GS  are the same, and the drain-to-body voltage V DB  and the gate-to-body voltage V GB  are also the same. 
         [0021]      FIGS. 3C and 4C  show schematic diagrams that illustrate prior-art PMOS transistor  200  and NMOS transistor  250 , with the body connected to the source and the gate connected to the drain. In this case, the source-to-body voltage V SB  is zero, the gate-to-source voltage V GS  and the gate-to-body voltage V GB  are the same, and the drain-to-source voltage V DS  and the drain-to-body voltage V DB  are also the same. In addition, the gate-to-drain voltage V GD  is zero, and the drain-to-body voltage V DB  and the gate-to-body voltage V GB  are the same. As a result, only one unique terminal-to-terminal voltage is present. 
         [0022]      FIGS. 3D and 4D  show schematic diagrams that illustrate prior-art PMOS transistor  200  and NMOS transistor  250 , with the body connected to the source and the drain. In this case, the source-to-body voltage V SB , the drain-to-source voltage V DS , and the drain-to-body voltage V DB  are all equal to zero, and the gate-to-source voltage V GS , the gate-to-body voltage V GB , and the gate-to-drain voltage V GD  are all the same. As a result, only one unique terminal-to-terminal voltage is present. 
         [0023]    During normal transistor operation, all of the terminal-to-terminal voltages shown in  FIGS. 2 ,  3  and  4  must be kept below a maximum value, which is usually determined by the breakdown voltage of the gate oxide. (This assumes that the PN junction breakdown voltage is greater than the gate oxide breakdown voltage, which is usually the case). 
         [0024]    Furthermore, the maximum breakdown voltage of the gate oxide has two values: a DC value and a transient value. The DC value is always lower than the transient value, mainly because the DC value causes the maximum cumulative stress on the oxide. In contrast, the transient breakdown voltage of the gate oxide is always higher than the DC value, mainly because the transient value stresses the gate oxide for a smaller percentage of the time, resulting in less cumulative stress on the oxide. 
         [0025]      FIG. 5A  shows a schematic diagram that illustrates an example of a prior-art non-inverting tristate output buffer  500 . In addition,  FIG. 5B  shows a schematic diagram that illustrates an example of a second prior-art non-inverting tristate output buffer  550 . 
         [0026]    Referring to  FIG. 5A , buffer  500  employs a single NMOS transistor N 1  and a single PMOS transistor P 1 , to drive the buffer output VOUT. In contrast, referring to  FIG. 5B , buffer  550  employs two stacked PMOS transistors P 1  and P 2 , and two stacked NMOS transistors N 1  and N 2 , to drive the buffer output VOUT. Because of this, PMOS transistors P 1  and P 2  in  FIG. 5B  must be made approximately twice as large (wide) as PMOS transistor P 1  in  FIG. 5A . Similarly, NMOS transistors N 1  and N 2  in  FIG. 5B  must be made approximately twice as large (wide) as NMOS transistor N 1  in  FIG. 5A . 
         [0027]    Nevertheless, output buffer  500  contains 18 transistors, whereas output buffer  550  only contains 8 transistors. Therefore, both buffers can be made comparable, in terms of circuit performance and circuit area. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0028]      FIG. 1A  is a block diagram illustrating an example of a prior-art CMOS chip  100 . 
           [0029]      FIG. 1B  is a block diagram illustrating an example of a prior-art CMOS chip  150 . 
           [0030]      FIGS. 2A-2B  are schematic diagrams illustrating a prior-art PMOS transistor  200  and a prior-art NMOS transistor  250 , respectively. 
           [0031]      FIGS. 3A and 4A  are schematic diagrams illustrating PMOS transistor  200  and NMOS transistor  250 , with the body connected to the source. 
           [0032]      FIGS. 3B and 4B  are schematic diagrams illustrating PMOS transistor  200  and NMOS transistor  250 , with the gate connected to the drain. 
           [0033]      FIGS. 3C and 4C  are schematic diagrams illustrating PMOS transistor  200  and NMOS transistor  250 , with the body connected to the source and the gate connected to the drain. 
           [0034]      FIGS. 3D and 4D  are schematic diagrams illustrating PMOS transistor  200  and NMOS transistor  250 , with the body connected to the source and the drain. 
           [0035]      FIG. 5A  is a schematic diagram illustrating an example of a prior-art non-inverting tristateable output buffer  500 . 
           [0036]      FIG. 5B  is a schematic diagram illustrating an example of a prior-art non-inverting tristateable output buffer  550 . 
           [0037]      FIG. 6  is a schematic diagram illustrating an example of a high voltage output buffer  600 , in accordance with the present invention. 
           [0038]      FIG. 7  is a schematic diagram illustrating an example of a voltage drop block VDB 1 , in accordance with the present invention. 
           [0039]      FIG. 8A  is a schematic diagram illustrating a PMOS transistor P 2  being turned off by a PMOS transistor P 32 , in accordance with the present invention. 
           [0040]      FIG. 8B  is a schematic diagram illustrating a PMOS transistor P 2  being turned off by a PMOS transistor P 42 , in accordance with the present invention. 
           [0041]      FIG. 9  is a schematic diagram illustrating an example of a high voltage output buffer  900 , in accordance with the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0042]    In accordance with the present invention,  FIG. 6  shows a schematic diagram that illustrates an example of a high voltage output buffer  600 . As described in greater detail below, output buffer  600  can supply a high voltage output swing using only low voltage CMOS transistors. For example, output buffer  600  can supply a 5V output swing using only 3.3V CMOS transistors, or a 3.3V output swing using only 2.5V CMOS transistors. 
         [0043]    As shown in  FIG. 6 , output buffer  600  includes an inverter  610  that inverts a low voltage input data signal DIN to generate a low voltage data output signal DINZ. Moreover, inverter  610  includes a PMOS transistor P 22  and an NMOS transistor N 8 . Furthermore, PMOS transistor P 22  has a gate connected to receive the low voltage input data signal DIN, a drain connected to an intermediate node ND 1 , and a source and substrate connected to an internal power supply line  612 , which is connected to an internal power supply voltage VDD INT . In addition, NMOS transistor N 8  has a gate connected to receive the low voltage input data signal DIN, a drain connected to intermediate node ND 1 , and a source and substrate connected to ground. 
         [0044]    As further shown in  FIG. 6 , output buffer  600  includes an inverting output driver  614  that inverts the low voltage input data signal DINZ, to generate a high voltage output signal DOUT. Moreover, output driver  614  and inverter  610  only employ low voltage CMOS transistors. In addition, inverting output driver  614  is composed of a series of inverter stages SG 1 -SGn which, in the present example, includes stages SG 1 , SG 2 , SG 3 , SG 4  and SG 5 . 
         [0045]    Referring to  FIG. 6 , inverter stage SG 1  includes a PMOS transistor P 1  and a PMOS transistor P 12 . PMOS transistor P 1  has a gate connected to an intermediate node ND 2 , a drain connected to an intermediate node ND 3 , and a source and body connected to a system power supply line  616 , which is connected to a system power supply voltage VDD SYS . Furthermore, PMOS transistor P 12  has a gate connected to receive a reference voltage Vref, a drain connected to the output node DOUT of buffer  600 , and a source and body connected to intermediate node ND 3 . 
         [0046]    In addition, inverter stage SG 1  also includes an NMOS transistor N 5  and an NMOS transistor N 6 . NMOS transistor N 5  has a gate connected to internal power supply line  612 , a drain connected to the output node DOUT of buffer  600 , a source connected to an intermediate node ND 4 , and a body connected to ground. Furthermore, NMOS transistor N 6  has a gate connected to intermediate node ND 1 , a drain connected to intermediate node ND 4 , and a source and body connected to ground. 
         [0047]    Referring to  FIG. 6 , inverter stage SG 2  includes a PMOS transistor P 2 , a voltage drop block VDB 1 , and an NMOS transistor N 4 . PMOS transistor P 2  has a gate connected to an intermediate node ND 5 , a drain connected to the gate of PMOS transistor P 1 , and a source and body connected to system power supply line  616 . 
         [0048]    In the present example, voltage drop block VDB 1  is implemented with three PMOS transistors P 13 , P 14  and P 15 , but it can also be implemented with other devices, including devices that can collectively produce a total voltage drop equal to three PMOS thresholds. In addition, PMOS transistor P 13  has a gate and a drain connected together, and a source and a body connected to the drain of PMOS transistor P 2 . Furthermore, PMOS transistor P 14  has a gate and a drain connected together, and a source and a body connected to the drain of PMOS transistor P 13 . Moreover, PMOS transistor P 15  has a gate and a drain connected together, and a source and a body connected to the drain of PMOS transistor P 14 . Finally, NMOS transistor N 4  has a gate connected to receive the input data signal DIN, a drain connected to the drain of PMOS transistor P 15 , and a source and body connected to ground. 
         [0049]    Referring to  FIG. 6 , inverter stage SG 3  includes a voltage drop block VDB 2 , a PMOS transistor P 4 , a voltage drop block VDB 3 , and an NMOS transistor N 3 . In the present example, voltage drop block VDB 2  is implemented with PMOS transistor P 3 , but it can also be implemented with other devices, including devices that can collectively produce a total voltage drop equal to one PMOS threshold. 
         [0050]    As shown in  FIG. 6 , PMOS transistor P 3  has a gate and a drain connected together, and a source and body connected to system power supply line  616 . Furthermore, PMOS transistor P 4  has a gate connected to an intermediate node ND 6 , a drain connected to the gate of PMOS transistor P 2 , and a source and body connected to the drain of PMOS transistor P 3 . 
         [0051]    In the present example, voltage drop block VDB 3  is implemented with PMOS transistors P 16 , P 17  and P 18 , but it can also be implemented with other devices, including devices that can collectively produce a total voltage drop equal to three PMOS thresholds. In addition, PMOS transistor P 16  has a gate and a drain connected together, and a source and body connected to the drain of PMOS transistor P 4 . Furthermore, PMOS transistor P 17  has a gate and a drain connected together, and a source and body connected to the drain of PMOS transistor P 16 . Moreover, PMOS transistor P 18  has a gate and a drain connected together, and a source and body connected to the drain of PMOS transistor P 17 . Finally, NMOS transistor N 3  has a gate connected to intermediate node ND 1 , a drain connected to the drain of PMOS transistor P 18 , and a source and body connected to ground. 
         [0052]    Referring to  FIG. 6 , inverter stage SG 4  includes a voltage drop block VDB 4 , a PMOS transistor P 7 , a voltage drop block VDB 5 , and an NMOS transistor N 2 . In the present example, voltage drop block VDB 4  is implemented with PMOS transistors P 5  and P 6 , but it can also be implemented with other devices, including devices that can collectively produce a total voltage drop equal to two PMOS thresholds. 
         [0053]    As shown in  FIG. 6 , PMOS transistor P 5  has a gate and a drain connected together, and a source and body connected to system power supply line  616 . In addition, PMOS transistor P 6  has a gate and a drain connected together, and a source and body connected to the drain of PMOS transistor P 5 . Furthermore, PMOS transistor P 7  has a gate connected to an intermediate node ND 7 , a drain connected to the gate of PMOS transistor P 4 , and a source and body connected to the drain of PMOS transistor P 6 . 
         [0054]    In the present example, voltage drop block VDB 5  is implemented with PMOS transistors P 19  and P 20 , but it can also be implemented with other devices, including devices that can collectively produce a total voltage drop equal to two PMOS thresholds. In addition, PMOS transistor P 19  has a gate and a drain connected together, and a source and body connected to the drain of PMOS transistor P 7 . Furthermore, PMOS transistor P 20  has a gate and a drain connected together, and a source and body connected to the drain of PMOS transistor P 19 . Finally, NMOS transistor N 2  has a gate connected to receive the input data signal DIN, a drain connected to the drain of PMOS transistor P 20 , and a source and body connected to ground. 
         [0055]    Referring to  FIG. 6 , inverter stage SG 5  includes a voltage drop block VDB 6 , a PMOS transistor P 11 , a voltage drop block VDB 7 , and an NMOS transistor N 1 . In the present example, voltage drop block VDB 6  is implemented with PMOS transistors P 8 , P 9  and P 10 , but it can also be implemented with other devices, including devices that can collectively produce a total voltage drop equal to three PMOS thresholds. 
         [0056]    As shown in  FIG. 6 , PMOS transistor P 8  has a gate and a drain connected together, and a source and body connected to system power supply line  616 . In addition, PMOS transistor P 9  has a gate and a drain connected together, and a source and body connected to the drain of PMOS transistor P 8 . Furthermore, PMOS transistor P 10  has a gate and a drain connected together, and a source and body connected to the drain of PMOS transistor P 9 . Moreover, PMOS transistor P 11  has a gate connected to intermediate node ND 1 , a drain connected to the gate of PMOS transistor P 7 , and a source and body connected to the drain of PMOS transistor P 10 . 
         [0057]    In the present example, voltage drop block VDB 7  is implemented with PMOS transistor P 21 , but it can also be implemented with other devices, including devices that can collectively produce a total voltage drop equal to one PMOS threshold. In addition, PMOS transistor P 21  has a gate and a drain connected together, and a source and body connected to the drain of PMOS transistor P 11 . Moreover, NMOS transistor N 1  has a gate connected to intermediate node ND 1 , a drain connected to the drain of PMOS transistor P 21 , and a source and body connected to ground. 
         [0058]    During normal circuit operation, the active high input data signal DIN, and its complement DINZ, can both switch from ground (OV) to the internal power supply voltage VDD INT , and vice versa. Thus, when the input data signal DIN is a logic high (VDD INT ) and its complement DINZ is a logic low (0V), PMOS transistor P 22  will be turned off, and NMOS transistors N 8 , N 2  and N 4  will be turned on. Furthermore, PMOS transistor P 11  will be turned on, and NMOS transistors N 1 , N 3  and N 6  will be turned off. Moreover, because PMOS transistor P 11  is turned on and NMOS transistor N 1  is turned off, PMOS transistor P 11  will charge up the gate of PMOS transistor P 7 , turning transistor P 7  off. 
         [0059]    In addition, when PMOS transistor P 7  is turned off and NMOS transistor N 2  is turned on, NMOS transistor N 2  will discharge the gate of PMOS transistor P 4 , turning on PMOS transistor P 4 . As a result, PMOS transistor P 4  will charge up the gate of PMOS transistor P 2 , turning transistor P 2  off. 
         [0060]    Moreover, when PMOS transistor P 2  is turned off and NMOS transistor N 4  is turned on, NMOS transistor N 4  will discharge the gate of PMOS transistor P 1 , turning on PMOS transistor P 1 . Thus, because PMOS transistor P 1  is turned on, and PMOS transistor P 12  is permanently turned on, and NMOS transistor N 6  is turned off, PMOS transistor P 1  will charge up the buffer output node DOUT to the system power supply voltage VDD SYS . 
         [0061]    Conversely, during normal circuit operation, when the input data signal DIN is a logic low (OV) and its complement DINZ is a logic high (VDD INT ), PMOS transistor P 22  will be turned on, and NMOS transistors N 8 , N 2  and N 4  will be turned off. Furthermore, PMOS transistor P 11  will be turned off, and NMOS transistors N 1 , N 3  and N 6  will be turned on. Moreover, because PMOS transistor P 11  is turned off and NMOS transistor N 1  is turned on, NMOS transistor N 1  will discharge the gate of PMOS transistor P 7 , turning transistor P 7  on. 
         [0062]    In addition, when PMOS transistor P 7  is turned on and NMOS transistor N 2  is turned off, PMOS transistor P 7  will charge up the gate of PMOS transistor P 4 , turning off PMOS transistor P 4 . As a result, NMOS transistor N 3  will discharge the gate of PMOS transistor P 2 , turning transistor P 2  on. 
         [0063]    Moreover, when PMOS transistor P 2  is turned on and NMOS transistor N 4  is turned off, PMOS transistor P 2  will charge up the gate of PMOS transistor P 1 , turning off PMOS transistor P 1 . Therefore, because PMOS transistor P 1  is turned off and NMOS transistor N 6  is turned on, and NMOS transistor N 5  is permanently turned on, NMOS transistor N 6  will discharge the buffer output node DOUT to the logic low level (0V). 
         [0064]    In accordance with the present invention, the highest voltage applied to the gate of PMOS transistor P 1  occurs when PMOS transistor P 2  is turned on and NMOS transistor N 4  is turned off. In this case, PMOS transistor P 2  will charge up the gate of transistor P 1  to the system power supply voltage VDD SYS . Therefore, the gate-to-source voltage V GS  of PMOS transistor P 1  will be equal to VDD SYS −VDD SYS =0V. As a result, transistor P 1  will be fully turned off and it will have very low leakage current. 
         [0065]    Conversely, and in accordance with the present invention, the lowest voltage applied to the gate of PMOS transistor P 1  occurs when PMOS transistor P 2  is turned off and NMOS transistor N 4  is turned on, causing the drain-to-source voltage of transistor N 4  to equal 0V. As a result, NMOS transistor N 4  will discharge the gate of PMOS transistor P 1  to its lowest voltage level, which is defined by the voltage across voltage drop block VDB 1 . 
         [0066]    In accordance with the present invention,  FIG. 7  shows a schematic diagram that illustrates an example of voltage drop block VDB 1 . As shown in  FIG. 7 , each one of the three PMOS transistors P 13 , P 14  and P 15  is connected as a two terminal “diode”. In other words, the transistor source is connected to the transistor body (N-well) to form a first terminal, and the transistor gate is connected to the transistor drain to form a second terminal. Furthermore, because these “diode-connected” PMOS transistors have their gates connected to their drains, all of these transistors are operating in saturated mode. 
         [0067]    Moreover, because the sources of PMOS transistors P 13 , P 14 , and P 15  are connected to their bodies, these transistors will not have any body effect. In other words, all three PMOS transistors will have the same threshold voltage, V TP . Because of this, the voltage drop across each PMOS transistor will be equal to the PMOS threshold voltage, V TP . Therefore, as shown in  FIG. 7 , the voltage at Node  1  is equal to V TP , the voltage at Node  2  is equal to 2V TP , and the voltage at Node  3  is equal to 3V TP . 
         [0068]    Thus, again referring to  FIG. 6 , when PMOS transistor P 2  is turned off and NMOS transistor N 4  is turned on, the lowest voltage on the gate of PMOS transistor P 1  will be equal to 3V TP , which is the sum of the threshold voltages of PMOS transistors P 13 , P 14  and P 15 . As a result, the lowest gate-to-source voltage V GS  of PMOS transistor P 1  will be equal to 3V TP −VDD SYS . 
         [0069]    Assuming that the system power supply voltage VDD SYS  is equal to 5V, and that P 1  is a 3.3V transistor, and that P 1  has a threshold voltage V TP  of 0.6V, the gate-to-source voltage of P 1  will be equal to 1.8V−5V=−3.2V. Therefore, even though PMOS transistor P 1  is connected to the 5V system power supply voltage VDD SYS , the largest gate-to-source voltage V GS  across transistor P 1  is equal −3.2V. Furthermore, since a V GS  of −3.2V is approximately equal to 5 PMOS thresholds (3.2V÷0.6V≈5), PMOS transistor P 1  will be strongly turned on. In addition, since P 1  is a 3.3V transistor, its gate oxide will not be damaged by a V GS  of −3.2V. 
         [0070]    Alternatively, assuming that the system power supply voltage VDD SYS  is equal to 3.3V, and that P 1  is a 2.5V transistor, and that P 1  has a threshold voltage V TP  of 0.4V, the gate-to-source voltage of P 1  will be equal to 1.2V−3.3V=−2.1V. Therefore, even though PMOS transistor P 1  is connected to the 3.3V system power supply voltage VDD SYS , the largest gate-to-source voltage V GS  across transistor P 1  is equal −2.1V. Furthermore, since a V GS  of −2.1V is approximately equal to 5 PMOS thresholds (2.1V÷0.4V≈5), PMOS transistor P 1  will be strongly turned on. In addition, since P 1  is a 2.5V transistor, its gate oxide will not be damaged by a V GS  of −2.1V. 
         [0071]    Referring to  FIG. 6 , the voltage on the output node DOUT of buffer  600  can be equal to 0V, or it can be equal to the system power supply voltage VDD SYS . Therefore, it is not possible to use only one low voltage PMOS transistor, or only one low voltage NMOS transistor, in stage SG 1  of output buffer  600 . In other words, since the PMOS and NMOS transistors in stage SG 1  are low voltage transistors, they cannot withstand the full system power supply voltage VDD SYS  across their gate-to-source, gate-to-drain or drain-to-source terminals. Therefore, in order to avoid a transistor overvoltage condition, two cascoded low voltage PMOS transistors (P 1  and P 12 ) and two cascoded low voltage NMOS transistors (N 5  and N 6 ) are used in stage SG 1  of buffer  600 . 
         [0072]    As shown in  FIG. 6 , a reference voltage Vref is placed on the gate of PMOS transistor P 12 , so that PMOS transistor P 12  is always on. Thus, when PMOS transistor P 1  is turned on, the drain-to source voltage of P 12  will be equal to 0V, and, as required, the voltage on output node DOUT will be equal to the system power supply voltage VDD SYS . As a result, the gate-to-drain voltage V DG  (and the gate-to-source voltage V GS ) of transistor P 12  will be equal to Vref−VDD SYS . Therefore, in order to keep the V DG  and V GS  voltages of P 12  within acceptable limits, the value of the reference voltage Vref must be properly chosen. 
         [0073]    For example, assuming that VDD SYS  is equal to 5V, and that VDD INT  is equal to 3.3V, and that 3.3V transistors are being used, Vref could be set equal to 1.75V. In this case, the worst case V GS  and V GD  voltages for transistor P 12  are both equal to 1.75V−5V=−3.25V, which is within the acceptable limits for 3.3V transistors. 
         [0074]    Alternatively, assuming that VDD SYS  is equal to 3.3V, and that VDD INT  is equal to 2.5V, and that 2.5V transistors are being used, Vref could be set equal to 1.4V. In this case, the worst case V GS  and V GD  voltages for transistor P 12  are both equal to 1.4V−2.5V=−1.1V, which is within the acceptable limits for 2.5V transistors. In addition, because the reference voltage Vref does not have to supply any current, the Vref voltage can be easily generated by an on-chip resistive voltage divider. 
         [0075]    As shown in  FIG. 6 , the internal power supply voltage VDD INT  is placed on the gate of NMOS transistor N 5 , so that NMOS transistor N 5  is always on. Furthermore, when NMOS transistor N 6  is turned off, the voltage on the output node DOUT of buffer  600  will be equal to the system power supply voltage VDD SYS . Therefore, the gate-to-drain voltage V GD  Of transistor N 5  will be equal to VDD INT −VDD SYS . Furthermore, the gate-to-source voltage of transistor N 5  will be equal to VDD INT −V TN , where V TN  is equal to the NMOS transistor threshold voltage. 
         [0076]    For example, assuming that VDD SYS  is equal to 5V, and that VDD INT  is equal to 3.3V, and that 3.3V transistors with a V TN  (NMOS threshold) of 0.5V are being used, the gate-to-drain voltage V GD  of transistor N 5  will be equal to 3.3V−5V=−1.7V, which is within the acceptable limits for 3.3V transistors. Furthermore, when transistor N 6  is turned off, the gate-to-source voltage of transistor N 5  will be equal to 3.3V−0.5V=2.8V. Therefore, since a V GS  of 2.8V is approximately equal to 6 NMOS thresholds (2.8V÷0.5V≈6), NMOS transistor N 5  will be strongly turned on. In addition, since N 5  is a 3.3V transistor, its gate oxide will not be damaged by a V GS  of 2.8V. 
         [0077]    Alternatively, assuming that VDD SYS  is equal to 3.3V, and that VDD INT  is equal to 2.5V, and that 2.5V transistors with a V TN  (NMOS threshold) of 0.3V are being used, the gate-to-drain voltage V GD  of transistor N 5  will be equal to 2.5V−3.3V=−0.8V, which is within the acceptable limits for 2.5V transistors. Furthermore, when transistor N 6  is turned off, the gate-to-source voltage of transistor N 5  will be equal to 2.5V−0.3V=2.2V. Therefore, since a V GS  of 2.2V is approximately equal to 7 NMOS thresholds (2.2V÷0.3V≈7), NMOS transistor N 5  will be strongly turned on. In addition, since N 5  is a 2.5V transistor, its gate oxide will not be damaged by a V GS  of 2.2V. 
         [0078]    Referring to  FIG. 6 , the highest gate voltage of NMOS transistor N 6  occurs when PMOS transistor P 22  is turned on and NMOS transistor N 8  is turned off. In this case, PMOS transistor P 22  charges up the gate of transistor N 6  to the internal power supply voltage VDD INT . As a result, the highest gate-to-source voltage V GS  of transistor N 6  is equal to VDD INT −0=VDD INT , which is within the acceptable limits for a 3.3V transistor, or a 2.5V transistor. 
         [0079]    Furthermore, the highest drain-to-gate voltage of transistor N 6  will occur when transistor N 6  is turned off. In this case, the drain-to-gate voltage will be equal to VDD INT −V TN , which is within the acceptable limits for a 3.3V transistor, or a 2.5V transistor. 
         [0080]    As noted above, transistors P 12  and N 5  both have DC voltages (Vref and VDD INT  respectively) connected to their gates. Therefore, ideally speaking, these lower voltages should be applied to the chip before the higher system power supply voltage VDD SYS  is applied. However, when this is not possible, the Vref and VDD INT  voltages can be applied at the same time that VDD SYS  is being applied. Alternatively, when this is not possible, the Vref and VDD INT  voltages can be applied within a few milliseconds after VDD SYS  has been applied. In this case, if VDD SYS  and VDD INT  are not too far apart, the output transistors will be stressed for only a few milliseconds, each time that power is applied to the chip. Thus, even if the chip is powered up many thousands of times during its lifetime, the cumulative stress on the gate oxide of the output transistors will not be significant. 
         [0081]    In summary, and in accordance with the present invention, when the transistors in stage SG 1  are 3.3V transistors and the system power supply voltage VDD SYS  is equal to 5V, the maximum voltage across the gate oxide will be within acceptable limits for 3.3V transistors. Alternatively, when the transistors in stage SG 1  are 2.5V transistors and the system power supply voltage VDD SYS  is equal to 3.3V, the maximum voltage across the gate oxide will be within acceptable limits for 2.5V transistors. As a result, all of the transistors in stage SG 1  can be implemented as low voltage transistors. 
         [0082]    With regard to stage SG 2 , the highest gate voltage on PMOS transistor P 2  occurs when PMOS transistor P 4  is turned on and NMOS transistor N 3  is turned off. In this case, PMOS transistor P 4  will charge up the gate of PMOS transistor P 2  to the system power supply voltage VDD SYS  minus the voltage across voltage drop block VDB 2 . Furthermore, in the present example, the voltage across voltage drop block VDB 2  is simply equal to the threshold voltage V TP  of PMOS transistor P 3 . Therefore, the highest voltage on the gate of transistor P 2  will be equal to VDD SYS −V TP . As a result, when the highest gate voltage on transistor P 2  is present, the gate-to-source voltage V GS  of P 2  will be equal to (VDD SYS −V TP )−VDD SYS =−V TP . Furthermore, in accordance with the present invention, and as illustrated in  FIGS. 8A-8B , a gate-to-source voltage equal to −V TP  is sufficient to turn off PMOS transistor P 2 . 
         [0083]    In accordance with the present invention,  FIG. 8A  shows a schematic diagram that illustrates PMOS transistor P 2  being turned off by a PMOS transistor P 32 . As shown in  FIG. 8A , PMOS transistors P 2  and P 32  both have their source and body terminals connected to the system power supply voltage VDD SYS . Furthermore, since the gate of PMOS transistor P 32  is grounded, PMOS transistor P 32  will be strongly on and its drain-to-source voltage will be equal to 0V. Because of this, the gate voltage of PMOS transistor P 2  will be equal to the system power supply voltage VDD SYS . Therefore, the gate-to-source voltage of PMOS transistor P 2  will be equal to 0V, and PMOS transistor P 2  will be turned off. 
         [0084]    In accordance with the present invention,  FIG. 8B  shows a schematic diagram that illustrates PMOS transistor P 2  being turned off by a PMOS transistor P 42 . As shown in  FIG. 8B , PMOS transistors P 2  and P 42  both have their source and body terminals connected to the system power supply voltage VDD SYS . However, in contrast to the circuit shown in  FIG. 8A , the gate of PMOS transistor P 42  is not grounded in  FIG. 8B , but is instead connected to the drain of PMOS transistor P 42 . Therefore, PMOS transistor P 2  is connected as a diode. As a result, the voltage that is present on the gate of PMOS transistor P 2  is equal to VDD SYS −V TP . Therefore, the gate-to-source voltage of PMOS transistor P 2  will be equal to (VDD SYS −V TP )−VDD SYS =−V TP . Thus, except for a minuscule amount of sub-threshold leakage current, PMOS transistor P 2  will be turned off. 
         [0085]    Furthermore, when the chip temperature is changed, the threshold voltages of PMOS transistors P 2  and P 42  will both change. However, since P 2  and P 42  are both PMOS transistors, their thresholds will change by the same amount. In other words, the threshold voltages of P 2  and P 42  will track each other as the temperature is changed. As a consequence of this, transistor P 2  will remain turned off under all circuit conditions. 
         [0086]    Again referring to  FIG. 6 , the lowest voltage applied to the gate of PMOS transistor P 2  occurs when PMOS transistor P 4  is turned off and NMOS transistor N 3  is turned on. In this case, NMOS transistor N 3  will pull down the voltage on the gate of PMOS transistor P 2 . As a result, the lowest voltage on the gate of PMOS transistor P 2  is defined by the voltage across voltage drop block VDB 3 . Furthermore, in the present example, the voltage across voltage drop block VDB 3  is equal −3V TP , which is equal to the sum of the threshold voltages V TP  of the three PMOS transistors P 16 , P 17  and P 18 . Therefore, the lowest voltage on the gate of PMOS transistor P 2  will be equal to 3V TP . As a result, when the lowest gate voltage on P 2  is present, the gate-to-source voltage V GS  of P 2  will be equal to 3V TP −VDD SYS . 
         [0087]    A gate-to-source voltage of 3V TP −VDD SYS  is high enough to turn on PMOS transistor P 2 , but not high enough to damage the gate oxide of P 2 . For example, assuming that VDD SYS  is equal to 5V, and that 3.3V transistors with a V TP  (PMOS threshold) of 0.6V are being used, the gate-to-source voltage V GS  of transistor P 2  will be equal to 1.8V−5V=−3.2V. Furthermore, since a V GS  of −3.2V is approximately equal to 5 PMOS thresholds (2.3V÷0.6V≈5), PMOS transistor P 2  will be strongly turned on. In addition, since P 2  is a 3.3V transistor, its gate oxide will not be damaged by a V GS  of −3.2V. 
         [0088]    Alternatively, assuming that VDD SYS  is equal to 3.3V, and that 2.5V transistors with a V TP  (PMOS threshold) of 0.4V are being used, the gate-to-source voltage V GS  of transistor P 2  will be equal to 1.2V−3.3V=−2.1V. Furthermore, since a V GS  of −2.1V is approximately equal to 5 PMOS thresholds (2.1V÷0.4V≈5), PMOS transistor P 2  will be strongly turned on. In addition, since P 2  is a 2.5V transistor, its gate oxide will not be damaged by a V GS  of −2.1V. 
         [0089]    With regard to the diode connected PMOS transistors P 13 , P 14  and P 15  in voltage drop block VDB 1 , these transistors never conduct DC current. As a result, the maximum voltage drop across each diode connected transistor will be equal to one PMOS threshold voltage, V TP . Therefore, each of the PMOS transistors P 13 , P 14  and P 15  can be implemented as a low voltage PMOS transistor. 
         [0090]    As shown in  FIG. 6 , the data input signal DIN is connected to the gate terminal of NMOS transistor N 4 . Thus, when DIN is low (0V), the gate voltage of transistor N 4  will be equal to 0V, and transistor N 4  will be turned off. Furthermore, when transistor N 4  is turned off and transistor P 2  is turned on, the voltage on the drain of NMOS transistor N 4  will be equal to the system power supply voltage VDD SYS  minus the voltage across voltage drop block VDB 1 . Therefore, since the voltage across voltage drop block VDB 1  is equal to 3V TP , the highest drain-to-gate voltage V DG  of N 4  will be equal to VDD SYS −3V TP . 
         [0091]    Assuming that VDD SYS  is equal to 5V, and that 3.3V transistors with a V TP  (PMOS threshold) of 0.6V are being used, the drain-to-gate voltage V DG  of transistor N 4  will be equal to 5V−1.8V=2.3V. This is within acceptable limits for 3.3V transistors. Alternatively, assuming that VDD SYS  is equal to 3.3V, and that 2.5V transistors with a V TP  (PMOS threshold) of 0.4V are being used, the drain-to-gate voltage V DG  of transistor N 4  will be equal to 3.3V−1.2V=2.1V. This is also within acceptable limits for 3.3V transistors. 
         [0092]    In summary, when the transistors in stage SG 2  are 3.3V transistors and the system power supply voltage VDD SYS  is equal to 5V, the voltage across the gate oxide will remain within acceptable limits. Furthermore, when the transistors in stage SG 2  are 2.5V transistors and the system power supply voltage VDD SYS  is equal to 3.3V, the voltage across the gate oxide will also remain within acceptable limits. As a result, all of the transistors in stage SG 2  can be implemented as low voltage transistors. 
         [0093]    With regard to stage SG 3 , the highest gate voltage on PMOS transistor P 4  occurs when PMOS transistor P 7  is turned on and NMOS transistor N 2  is turned off. In this case, PMOS transistor P 7  will charge up the gate of PMOS transistor P 4  to the system power supply voltage VDD SYS  minus the voltage across voltage drop block VDB 4 . Furthermore, in the present example, the voltage across voltage drop block VDB 4  is equal to the threshold voltages V TP  of PMOS transistors P 5  and P 6 . Therefore, the highest voltage on the gate of transistor P 4  will be equal to VDD SYS −2V TP . As a result, when the highest gate voltage on transistor P 4  is present, the gate-to-source voltage V GS  of PMOS transistor P 4  will be equal to (VDD SYS −2V TP )−(VDD SYS −V TP )=−V TP . Furthermore, as previously described, and in accordance with the present invention, a gate-to-source voltage of −V TP  is sufficient to turn off PMOS transistor P 4 . 
         [0094]    Again referring to  FIG. 6 , the lowest gate voltage on PMOS transistor P 4  occurs when PMOS transistor P 7  is turned off and NMOS transistor N 2  is turned on. In this case, NMOS transistor N 2  will pull down the voltage on the gate of PMOS transistor P 4 . As a result, the lowest voltage on the gate of PMOS transistor P 4  is defined by the voltage across voltage drop block VDB 5 . Furthermore, in the present example, the voltage across voltage drop block VDB 5  is equal to the sum of the threshold voltages V TP  of two PMOS transistors P 19  and P 20 . Therefore, the lowest voltage on the gate of PMOS transistor P 4  will be equal to 2V TP . As a result, when the lowest gate voltage on P 4  is present, the gate-to-source voltage V GS  of P 4  will be equal to 2V TP −(VDD SYS −V TP )=3V TP −VDD SYS . 
         [0095]    A gate-to-source voltage of 3V TP −VDD SYS  is high enough to turn on PMOS transistor P 4 , but not high enough to damage the gate oxide of P 4 . For example, assuming that VDD SYS  is equal to 5V, and that 3.3V transistors with a V TP  (PMOS threshold) of 0.6V are being used, the gate-to-source voltage V GS  of transistor P 4  will be equal to 1.8V−5V=−3.2V. Furthermore, since a V GS  of −3.2V is approximately equal to 5 PMOS thresholds (2.3V÷0.6V≈5), PMOS transistor P 4  will be strongly turned on. In addition, since P 4  is a 3.3V transistor, its gate oxide will not be damaged by a V GS  of −3.2V. 
         [0096]    Alternatively, assuming that VDD SYS  is equal to 3.3V, and that 2.5V transistors with a V TP  (PMOS threshold) of 0.4V are being used, the gate-to-source voltage V GS  of transistor P 4  will be equal to 1.2V−3.3V=−2.1V. Furthermore, since a V GS  of −2.1V is approximately equal to 5 PMOS thresholds (2.1V+0.4V≈5), PMOS transistor P 4  will be strongly turned on. In addition, since P 4  is a 2.5V transistor, its gate oxide will not be damaged by a V GS  of −2.1V. 
         [0097]    With regard to the diode connected PMOS transistors P 16 , P 17  and P 18  in voltage drop block VDB 3 , these transistors never conduct DC current. As a result, the maximum voltage drop across each diode connected transistor will be equal to one PMOS threshold drop, V TP . Therefore, each one of the PMOS transistors P 16 , P 17  and P 18  can be implemented as a low voltage PMOS transistor. 
         [0098]    As shown in  FIG. 6 , the data input signal DINZ is connected to the gate terminal of NMOS transistor N 3 . Thus, when DINZ is low (0V), the gate voltage of transistor N 3  will be equal to 0V, and transistor N 3  will be turned off. Furthermore, when transistor N 3  is turned off and transistor P 4  is turned on, the voltage on the drain of NMOS transistor N 3  will be equal to the system power supply voltage VDD SYS  minus the voltage across voltage drop block VDB 2 , minus the voltage across voltage drop block VDB 3 . Therefore, since the total voltage across voltage drop blocks VDB 2  and VDB 3  is equal to V TP +3V TP =4V TP , the highest drain-to-gate voltage V DG  of N 3  will be equal to VDD SYS −4V TP . 
         [0099]    Assuming that VDD SYS  is equal to 5V, and that 3.3V transistors with a V TP  (PMOS threshold) of 0.6V are being used, the drain-to-gate voltage V DG  of transistor N 3  will be equal to 5V−2.4V=2.6V. This is within acceptable limits for 3.3V transistors. Alternatively, assuming that VDD SYS  is equal to 3.3V, and that 2.5V transistors with a V TP  (PMOS threshold) of 0.4V are being used, the drain-to-gate voltage V DG  of transistor N 3  will be equal to 3.3V−1.6V=1.7V. This is also within acceptable limits for 3.3V transistors. 
         [0100]    In summary, when the transistors in stage SG 3  are 3.3V transistors and the system power supply voltage VDD SYS  is equal to 5V, the voltage across the gate oxide will remain within acceptable limits. Furthermore, when the transistors in stage SG 3  are 2.5V transistors and the system power supply voltage VDD SYS  is equal to 3.3V, the voltage across the gate oxide will also remain within acceptable limits. As a result, all of the transistors in stage SG 3  can be implemented as low voltage transistors. 
         [0101]    With regard to stage SG 4 , the highest gate voltage on PMOS transistor P 7  occurs when PMOS transistor P 11  is turned on and NMOS transistor N 1  is turned off. In this case, PMOS transistor P 11  will charge up the gate of PMOS transistor P 7  to the system power supply voltage VDD SYS  minus the voltage across voltage drop block VDB 6 . Furthermore, in the present example, the voltage across voltage drop block VDB 6  is equal to the threshold voltages V TP  of PMOS transistors P 8 , P 9  and P 10 . Therefore, the highest voltage on the gate of transistor P 7  will be equal to VDD SYS −3V TP . As a result, when the highest gate voltage on transistor P 7  is present, the gate-to-source voltage V GS  of PMOS transistor P 7  will be equal to (VDD SYS −3V TP )−(VDD SYS −2V TP )=−V TP . Furthermore, as previously described, and in accordance with the present invention, a gate-to-source voltage of −V TP  is sufficient to turn off PMOS transistor P 7 . 
         [0102]    Again referring to  FIG. 6 , the lowest gate voltage on PMOS transistor P 7  occurs when PMOS transistor P 11  is turned off and NMOS transistor N 1  is turned on. In this case, NMOS transistor N 1  will pull down the voltage on the gate of PMOS transistor P 7 . As a result, the lowest voltage on the gate of PMOS transistor P 7  is defined by the voltage across voltage drop block VDB 7 . Furthermore, in the present example, the voltage across voltage drop block VDB 7  is simply equal to the threshold voltage V TP  of PMOS transistor P 21 . Therefore, the lowest voltage on the gate of PMOS transistor P 7  will be equal to V TP . As a result, when the lowest gate voltage on P 7  is present, the gate-to-source voltage V GS  of P 7  will be equal to V TP −(VDD SYS −2V TP )=3V TP −VDD SYS . 
         [0103]    A gate-to-source voltage of 3V TP −VDD SYS  is high enough to turn on PMOS transistor P 7 , but not high enough to damage the gate oxide of P 7 . For example, assuming that VDD SYS  is equal to 5V, and that 3.3V transistors with a V TP  (PMOS threshold) of 0.6V are being used, the gate-to-source voltage V GS  of transistor P 7  will be equal to 1.8V−5V=−3.2V. Furthermore, since a V GS  of −3.2V is approximately equal to 5 PMOS thresholds (3.2V÷0.6V≈5), PMOS transistor P 7  will be strongly turned on. In addition, since P 7  is a 3.3V transistor, its gate oxide will not be damaged by a V GS  of −3.2V. 
         [0104]    Alternatively, assuming that VDD SYS  is equal to 3.3V, and that 2.5V transistors with a V TP  (PMOS threshold) of 0.4V are being used, the gate-to-source voltage V GS  of transistor P 7  will be equal to 1.2V−3.3V=−2.1V. Furthermore, since a V GS  of −2.1V is approximately equal to 5 PMOS thresholds (2.1V÷0.4V≈5), PMOS transistor P 7  will be strongly turned on. In addition, since P 7  is a 2.5V transistor, its gate oxide will not be damaged by a V GS  of −2.1V. 
         [0105]    With regard to the diode connected PMOS transistors in voltage drop blocks VDB 4  and VDB 5 , these transistors never conduct DC current. As a result, the maximum voltage drop across each diode connected transistor will be equal to one PMOS threshold drop, V TP . Therefore, each one of the PMOS transistors in voltage drop blocks VDB 4  and VDB 5  can be implemented as a low voltage PMOS transistor. 
         [0106]    As shown in  FIG. 6 , the data input signal DIN is connected to the gate terminal of NMOS transistor N 2 . Thus, when DIN is low (0V), the gate voltage of transistor N 2  will be equal to 0V, and transistor N 2  will be turned off. Furthermore, when transistor N 2  is turned off and transistor P 7  is turned on, the voltage on the drain of NMOS transistor N 2  will be equal to the system power supply voltage VDD SYS  minus the voltage across voltage drop block VDB 4 , minus the voltage across voltage drop block VDB 5 . Therefore, since the voltage across voltage these voltage drop blocks is equal to 2V TP +2V TP =4V TP , the highest drain-to-gate voltage V DG  of N 4  will be equal to VDD SYS −4V TP . 
         [0107]    Assuming that VDD SYS  is equal to 5V, and that 3.3V transistors with a V TP  (PMOS threshold) of 0.6V are being used, the drain-to-gate voltage V DG  of transistor N 2  will be equal to 5V−2.4V=2.6V. This is within acceptable limits for 3.3V transistors. Alternatively, assuming that VDD SYS  is equal to 3.3V, and that 2.5V transistors with a V TP  (PMOS threshold) of 0.4V are being used, the drain-to-gate voltage V DG  of transistor N 2  will be equal to 3.3V−1.6V=1.7V. This is also within acceptable limits for 3.3V transistors. 
         [0108]    In summary, when the transistors in stage SG 4  are 3.3V transistors and the system power supply voltage VDD SYS  is equal to 5V, the voltage across the gate oxide will remain within acceptable limits. Furthermore, when the transistors in stage SG 4  are 2.5V transistors and the system power supply voltage VDD SYS  is equal to 3.3V, the voltage across the gate oxide will also remain within acceptable limits. As a result, all of the transistors in stage SG 4  can be implemented as low voltage transistors. 
         [0109]    With regard to stage SG 5 , the highest gate voltage on PMOS transistor P 11  occurs when PMOS transistor P 22  is turned on and NMOS transistor N 1  is turned off. In this case, PMOS transistor P 22  will charge up the gate of PMOS transistor P 11  to the internal power supply voltage VDD INT . Therefore, the highest voltage on the gate of transistor P 11  will be equal to VDD INT . Furthermore, the source voltage of PMOS transistor P 11  is defined by the VDD SYS  voltage minus the voltage across voltage drop block VDB 6 . However, in the present example, the voltage across voltage drop block VDB 6  is equal to the threshold voltages V TP  of PMOS transistors P 8 , P 9  and P 10 . As a result, the source voltage of PMOS transistor P 11  will be equal to VDD SYS −3V TP . Thus, when the highest gate voltage on transistor P 11  is present, the gate-to-source voltage V GS  of PMOS transistor P 11  will be equal to VDD INT −(VDD SYS −3V TP )=−VDD SYS +VDD INT +3V TP . 
         [0110]    Assuming that VDD SYS  is equal to 5V, and that 3.3V transistors with a V TP  (PMOS threshold) of 0.6V are being used, the highest gate-to-source voltage V GS  of transistor P 11  will be equal to −5V+3.3V+1.8V=+0.1V. Since this gate-to-source voltage has a positive value, it will strongly turn off PMOS transistor P 11 . 
         [0111]    Alternatively, assuming that VDD SYS  is equal to 3.3V, and that 2.5V transistors with a V TP  (PMOS threshold) of 0.4V are being used, the gate-to-source voltage V GS  of transistor P 11  will be equal to −3.3V+2.5V+1.2V=+0.4V. Since this gate-to-source voltage has a positive value, it will strongly turn off PMOS transistor P 11 . 
         [0112]    Again referring to  FIG. 6 , the lowest gate voltage on PMOS transistor P 11  occurs when PMOS transistor P 22  is turned off and NMOS transistor N 8  is turned on. In this case, NMOS transistor N 8  will pull down the voltage on the gate of PMOS transistor P 11  to 0V (GND). Furthermore, the source voltage on PMOS transistor P 11  is defined by the VDD SYS  voltage minus the voltage across voltage drop block VDB 6 . However, in the present example, the voltage across voltage drop block VDB 6  is equal to the threshold voltages V TP  of PMOS transistors P 8 , P 9  and P 10 . As a result, the source voltage of PMOS transistor P 11  will be equal to VDD SYS −3V TP . Thus, when the lowest gate voltage on transistor P 11  is present, the gate-to-source voltage V GS  of PMOS transistor P 11  will be equal to 0V−(VDD SYS −3V TP )=3V TP −VDD SYS . 
         [0113]    A gate-to-source voltage of 3V TP −VDD SYS  is high enough to turn on PMOS transistor P 11 , but not high enough to damage the gate oxide of P 11 . For example, assuming that VDD SYS  is equal to 5V, and that 3.3V transistors with a V TP  (PMOS threshold) of 0.6V are being used, the gate-to-source voltage V GS  of transistor P 11  will be equal to 1.8V−5V=−3.2V. Furthermore, since a V GS  of −3.2V is approximately equal to 5 PMOS thresholds (2.3V÷0.6V≈5), PMOS transistor P 11  will be strongly turned on. In addition, since P 11  is a 3.3V transistor, its gate oxide will not be damaged by a V GS  of −3.2V. 
         [0114]    Alternatively, assuming that VDD SYS  is equal to 3.3V, and that 2.5V transistors with a V TP  (PMOS threshold) of 0.4V are being used, the gate-to-source voltage V GS  of transistor P 11  will be equal to 1.2V−3.3V=−2.1V. Furthermore, since a V GS  of −2.1V is approximately equal to 5 PMOS thresholds (2.1V÷0.4V≈5), PMOS transistor P 11  will be strongly turned on. In addition, since P 11  is a 2.5V transistor, its gate oxide will not be damaged by a V GS  of −2.1V. 
         [0115]    With regard to the diode connected PMOS transistors P 8 , P 9  and P 10  in voltage drop block VDB 6 , these transistors never conduct DC current. As a result, the maximum voltage drop across each diode connected transistor will be equal to one PMOS threshold drop, V TP . Therefore, each one of the PMOS transistors P 8 , P 9  and P 10  can be implemented as a low voltage PMOS transistor. 
         [0116]    As shown in  FIG. 6 , the data input signal DINZ is connected to the gate terminal of NMOS transistor N 1 . Thus, when DINZ is low (0V), the gate voltage of transistor N 1  will be equal to 0V, and transistor N 1  will be turned off. Furthermore, when transistor N 1  is turned off and transistor Pll is turned on, the voltage on the drain of NMOS transistor N 1  will be equal to the system power supply voltage VDD SYS  minus the voltage across voltage drop block VDB 6 , minus the voltage across voltage drop block VDB 7 . Therefore, since the voltage across voltage these voltage drop blocks is equal to 3V TP +1V TP =4V TP , the highest drain-to-gate voltage V DG  of N 1  will be equal to VDD SYS −4V TP . 
         [0117]    Assuming that VDD SYS  is equal to 5V, and that 3.3V transistors with a V TP  (PMOS threshold) of 0.6V are being used, the drain-to-gate voltage V DG  of transistor N 1  will be equal to 5V−2.4V=2.6V. This is within acceptable limits for 3.3V transistors. Alternatively, assuming that VDD SYS  is equal to 3.3V, and that 2.5V transistors with a V TP  (PMOS threshold) of 0.4V are being used, the drain-to-gate voltage V DG  of transistor N 1  will be equal to 3.3V−1.6V=1.7V. This is also within acceptable limits for 3.3V transistors. 
         [0118]    In summary, when the transistors in stage SG 5  are 3.3V transistors and the system power supply voltage VDD SYS  is equal to 5V, the voltage across the gate oxide will remain within acceptable limits. Furthermore, when the transistors in stage SG 5  are 2.5V transistors and the system power supply voltage VDD SYS  is equal to 3.3V, the voltage across the gate oxide will also remain within acceptable limits. As a result, all of the transistors in stage SG 5  can be implemented as low voltage transistors. 
         [0119]    As shown in  FIG. 6 , each stage SG 1 -SGn includes only one PMOS transistor and one NMOS transistor that can be fully switched on/off. For example, the fully switched PMOS transistors in stages SG 1 -SG 5  include P 1 , P 2 , P 4 , P 7  and P 11 , respectively. In addition, the fully switched NMOS transistors in stages SG 1 -SG 5  include N 6 , N 4 , N 3 , N 2  and N 1 , respectively. Furthermore, both of the fully switched PMOS and NMOS transistors in any given stage cannot be in a turned-on state at the same time. Using stage SG 2  as an example, if PMOS transistor P 2  is turned off, NMOS transistor N 4  will be turned on, and vice versa. 
         [0120]    Again using stage SG 2  as an example, if PMOS transistor P 2  remains turned off for a very long time, NMOS transistor N 4  will remain turned on for very a long time. Therefore, under this circuit condition, the exceedingly small DC leakage current through PMOS transistors P 13 , P 14  and P 15  could eventually discharge the gate of PMOS transistor P 1  to ground (0V). Moreover, if this condition were to occur, the gate-to-source voltage V GS  of transistor P 1  would eventually become equal to VDD SYS , exceeding the maximum allowed V GS  for P 1 . Thus, in order to prevent this circuit condition from occurring, a high value resistor R 2  can be connected from the drain of transistor P 2  to a reference voltage such as VDD INT , as shown in  FIG. 9 . 
         [0121]    In accordance with the present invention,  FIG. 9  shows a schematic diagram that illustrates an example of a high voltage output buffer  900 . Buffer  900  is similar to buffer  600 , and as a result, utilizes the same reference numerals to designate the structures that are common to both buffers. Comparing buffer  900  in  FIG. 9  to buffer  600  in  FIG. 6 , it can be seen that both figures are identical, except that high value resistors R 2 , R 4 , R 7  and R 11  have been added to  FIG. 9 . 
         [0122]    Referring to  FIG. 9 , the purpose of high value resistor R 2 , which is connected between the internal power supply voltage VDD INT  and the drain of transistor P 2 , is to cancel out the leakage current at the drain of PMOS transistor P 2 . In other words, this leakage current cancellation will cause the drain voltage of PMOS transistor P 2  to remain at a voltage level of 3V TP  above ground, even when PMOS transistor P 2  remains turned off for a very long time, and NMOS transistor N 4  remains turned on for a very long time. 
         [0123]    Similarly, high value resistor R 4 , which is connected between the internal power supply voltage VDD INT  and the drain of transistor P 4 , is used to cancel out the leakage current at the drain of PMOS transistor P 4 . Furthermore, high value resistor R 7 , which is connected between the internal power supply voltage VDD INT  and the drain of transistor P 7 , is used to cancel out the leakage current at the drain of PMOS transistor P 7 . In addition, high value resistor R 11 , which is connected between the internal power supply voltage VDD INT  and the drain of transistor P 11 , is used to cancel out the leakage current at the drain of PMOS transistor P 11 . Moreover, since resistors R 2 , R 4 , R 7  and R 11  have a high value in comparison to the equivalent turned-on resistances of PMOS transistors P 2 , P 4 , P 7  and P 11 , resistors R 2 , R 4 , R 7  and R 11  will not affect the drain voltages of PMOS transistors P 2 , P 4 , P 7  and P 11 , when these PMOS transistors are in a turned-on state. 
         [0124]    Furthermore, the average power dissipation in resistors R 2 , R 4 , R 7  and R 11  will be very low for two reasons. First of all, these resistors only dissipate power when NMOS transistors N 4 , N 3 , N 2  and N 1  are in a turned-on state. Secondly, when power is being dissipated, it will be exceedingly low because resistors R 2 , R 4 , R 7  and R 11  are high in value. 
         [0125]    Table 1 below enumerates the gate-to-source operating conditions for the PMOS transistors that can be switched on/off in stages SG 2 -SG 5  of  FIGS. 6 and 9 . As previously described, these PMOS transistors include P 2 , P 4 , P 7  and P 11 , respectively. Referring to Table 1, the source voltage (V S ), the gate voltage (V G ) and the gate-to-source voltage V GS  (V GS =V G −V S ) are tabulated for each of these PMOS transistors. 
         [0126]    As shown in Table 1, when the switched PMOS transistors in stages SG 2 -SG 5  are turned on, their gate-to-source voltage V GS  will be the same: 3V TP −VDD SYS . For example, assuming that VDD SYS  is equal to 5V, and that 3.3V transistors with a V TP  (PMOS threshold) of 0.6V are being used, the V GS  “on” voltage of transistors P 2 , P 4 , P 7  and P 11  will be equal to 1.8V−5V=−3.2V. Moreover, since a V GS  “on” voltage of −3.2V is approximately equal to 5 PMOS thresholds (2.3V÷0.6V≈5), PMOS transistors P 2 , P 4 , P 7  and P 11  will be strongly turned on. Furthermore, since these transistors are 3.3V transistors, their gate oxide will not be damaged by a V GS  of −3.2V. 
         [0127]    Alternatively, assuming that VDD SYS  is equal to 3.3V, and that 2.5V transistors with a V TP  (PMOS threshold) of 0.4V are being used, the V GS  “on” voltage of transistors P 2 , P 4 , P 7  and P 11  will be equal to 1.2V−3.3V=−2.1V. Moreover, since a V GS  “on” voltage of −2.1V is approximately equal to 5 PMOS thresholds (2.1V÷0.4V≈5), PMOS transistors P 2 , P 4 , P 7  and P 11  will be strongly turned on. Furthermore, since these transistors are 2.5V transistors, their gate oxide will not be damaged by a V GS  of −2.1V. 
         [0128]    Referring to Table 1, when the switched PMOS transistors P 2 , P 4  and P 7  in stages SG 2 -SG 4  are turned off, their gate-to-source voltage V GS  will be the same: −V TP . Therefore, as described above, this voltage level is adequate to turn off these transistors. 
         [0129]    Again referring to Table 1, when switched PMOS transistor P 11  in stage SG 5  is turned off, its “off” gate-to-source voltage V GS  will be equal to VDD INT +3V TP −VDD SYS . Thus, assuming that VDD SYS  is equal to 5V, and that VDD INT  is equal to 3.3V, and that 3.3V transistors with a V TP  (PMOS threshold) of 0.6V are being used, the “off” V GS  voltage of transistor P 11  will be equal to 3.3V+1.8V−5V=+0.1V. Since this V GS  voltage is positive, transistor P 11  will be strongly turned off. 
         [0130]    Alternatively, assuming that VDD SYS  is equal to 3.3V, and that VDD INT  is equal to 2.5V, and that 2.5V transistors with a V TP  (PMOS threshold) of 0.4V are being used, the “off” V GS  voltage of transistor P 11  will be equal to 2.5V+1.2V−3.3V=+0.4V. Since this V GS  voltage is positive, transistor P 11  will be strongly turned off. 
         [0000]    
       
         
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                   
                 Gate 
                 Source 
                 Gate to Source 
               
               
                 Stage/ 
                 Voltage 
                 Voltage 
                 Voltage 
               
               
                 PMOS Transistor 
                 V G   
                 V S   
                 V GS  = V G  − V S   
               
               
                   
               
             
             
               
                 Stage SG2, P2 on 
                 3 V TP   
                 VDD SYS   
                 3 V TP  − VDD SYS   
               
               
                 Stage SG2, P2 off 
                 VDD SYS  − V TP   
                 VDD SYS   
                 −V TP   
               
               
                 Stage SG3, P4 on 
                 2 V TP   
                 VDD SYS  − V TP   
                 3 V TP  − VDD SYS   
               
               
                 Stage SG3, P4 off 
                 VDD SYS  − 2 V TP   
                 VDD SYS  − V TP   
                 −V TP   
               
               
                 Stage SG4, P7 on 
                 V TP   
                 VDD SYS  − 2 V TP   
                 3 V TP  − VDD SYS   
               
               
                 Stage SG4, P7 off 
                 VDD SYS  − 3 V TP   
                 VDD SYS  − 2 V TP   
                 −V TP   
               
               
                 Stage SG5, P11 on 
                 0 
                 VDD SYS  − 3 V TP   
                 3 V TP  − VDD SYS   
               
               
                 Stage SG5, P11 off 
                 VDD INT   
                 VDD SYS  − 3 V TP   
                 VDD INT  + 3 V TP  − VDD SYS   
               
               
                   
               
             
          
         
       
     
         [0131]    In summary, the on/off gate-to-source voltages V GS  of the switched PMOS transistors in stages SG 2 -SG 5  will adequately turn these transistors on/off, and the maximum gate-to-source voltages V GS  will remain within acceptable limits. 
         [0132]    Table 2 below enumerates the source-to-drain operating conditions for the PMOS transistors that can be switched on/off in stages SG 2 -SG 5  of  FIGS. 6 and 9 . As previously described, these PMOS transistors include P 2 , P 4 , P 7  and P 11 , respectively. Referring to Table  2 , the source voltage (V S ), the drain voltage (V D ) and the source-to-drain voltage V SD  (V SD =V S −V D ) are tabulated for each of these PMOS transistors. 
         [0133]    As shown in Table 2, when the switched PMOS transistors in stages SG 2 -SG 5  are turned on, their source-to-drain voltages V SD  will be equal to 0V. Therefore, their source-to-drain voltages will remain within acceptable limits for 3.3V transistors operating from a VDD SYS  of 5V, and for 2.5V transistors operating from a VDD SYS  of 3.3V. 
         [0134]    As further shown in Table 2, when switched PMOS transistor P 2  in stage SG 2  is turned off, its “off” source-to-drain voltage V SD  will be equal to VDD SYS −3V TP . Thus, assuming that VDD SYS  is equal to 5V, and that 3.3V transistors with a V TP  (PMOS threshold) of 0.6V are being used, the “off” V SD  voltage of transistor P 2  will be equal to 5V−1.8V=+2.3V. Therefore, the V SD  voltage of transistor P 2  is within acceptable limits for a 3.3V transistor. 
         [0135]    Alternatively, assuming that VDD SYS  is equal to 3.3V, and that 2.5V transistors with a V TP  (PMOS threshold) of 0.4V are being used, the “off” V SD  voltage of transistor P 2  will be equal to 3.3V−1.2V=+2.1V. Therefore, the V SD  voltage of transistor P 2  is within acceptable limits for a 2.5V transistor. 
         [0136]    Again referring to Table 2, when switched PMOS transistors P 4 , P 7  and P 11  in stages SG 3 -SG 5  are turned off, their “off” source-to-drain voltage V SD  will be equal to VDD SYS −4V TP . Thus, assuming that VDD SYS  is equal to 5V, and that 3.3V transistors with a V TP  (PMOS threshold) of 0.6V are being used, the “off” V SD  voltage of transistors P 4 , P 7  and P 11  will be equal to 5V−2.4V=+2.6V. Therefore, the V SD  voltages of transistors P 4 , P 7  and P 11  are within acceptable limits for 3.3V transistors. 
         [0137]    Alternatively, assuming that VDD SYS  is equal to 3.3V, and that VDD INT  is equal to 2.5V, and that 2.5V transistors with a V TP  (PMOS threshold) of 0.4V are being used, the “off” V SD  voltage of transistors P 4 , P 7  and P 11  will be equal to 3.3V−1.6V=+1.7V. Therefore, the V SD  voltages of transistors P 4 , P 7  and P 11  are within acceptable limits for 2.5V transistors. 
         [0000]    
       
         
               
               
               
               
             
           
               
                 TABLE 2 
               
               
                   
               
               
                   
                 Source 
                   
                   
               
               
                 Stage/ 
                 Voltage 
                 Drain Voltage 
                 Source to Drain Voltage 
               
               
                 PMOS Transistor 
                 V S   
                 V D   
                 V SD  = V S  − V D   
               
               
                   
               
             
             
               
                 Stage SG2, P2 on 
                 VDD SYS   
                 VDD SYS   
                 0 
               
               
                 Stage SG2, P2 off 
                 VDD SYS   
                 3 V TP   
                 VDD SYS  − 3 V TP   
               
               
                 Stage SG3, P4 on 
                 VDD SYS  − V TP   
                 VDD SYS  − V TP   
                 0 
               
               
                 Stage SG3, P4 off 
                 VDD SYS  − V TP   
                 3 V TP   
                 VDD SYS  − 4 V TP   
               
               
                 Stage SG4, P7 on 
                 VDD SYS  − 2 V TP   
                 VDD SYS  − 2 V TP   
                 0 
               
               
                 Stage SG4, P7 off 
                 VDD SYS  − 2 V TP   
                 2 V TP   
                 VDD SYS  − 4 V TP   
               
               
                 Stage SG5, P11 on 
                 VDD SYS  − 3 V TP   
                 VDD SYS  − 3 V TP   
                 0 
               
               
                 Stage SG5, P11 off 
                 VDD SYS  − 3 V TP   
                 V TP   
                 VDD SYS  − 4 V TP   
               
               
                   
               
             
          
         
       
     
         [0138]    In summary, the on/off source-to-drain voltages V SD  of the switched PMOS transistors in stages SG 2 -SG 5  will remain within acceptable limits, under all circuit conditions. 
         [0139]    Table 3 below enumerates the drain-to-gate operating conditions for the PMOS transistors that can be switched on/off in stages SG 2 -SG 5  of  FIGS. 6 and 9 . As previously described, these PMOS transistors include P 2 , P 4 , P 7  and P 11 , respectively. Referring to Table 3, the drain voltage (V D ), the gate voltage (V G ) and the drain-to-gate voltage V DG  (V DG =V D −V G ) are tabulated for each of these PMOS transistors. 
         [0140]    As shown in Table 3, when the switched PMOS transistors in stages SG 2 -SG 5  are turned on, their drain-to-gate voltages V DG  will be the same: VDD SYS −3V TP . For example, assuming that VDD SYS  is equal to 5V, and that 3.3V transistors with a V TP  (PMOS threshold) of 0.6V are being used, the V DG  voltage of transistors P 2 , P 4 , P 7  and P 11  will be equal to 5V−1.8V=2.3V. Therefore, since these transistors are 3.3V transistors, their gate oxide will not be damaged by a V DG  of 2.3V. 
         [0141]    Alternatively, assuming that VDD SYS  is equal to 3.3V, and that 2.5V transistors with a V TP  (PMOS threshold) of 0.4V are being used, the V DG  of transistors P 2 , P 4 , P 7  and P 11  will be equal to 3.3V−1.2V=2.1V. Therefore, since these transistors are 2.5V transistors, their gate oxide will not be damaged by a V DG  of 2.1V. 
         [0142]    As further shown in Table 3, when switched PMOS transistor P 2  in stage SG 2  is turned off, its “off” drain-to-gate voltage V DG  will be equal to 4V TP −VDD SYS . Thus, assuming that VDD SYS  is equal to 5V, and that 3.3V transistors with a V TP  (PMOS threshold) of 0.6V are being used, the “off” V DG  voltage of transistor P 2  will be equal to 2.4V−5V=−2.6V. Therefore, the V DG  voltage of transistor P 2  is within acceptable limits for a 3.3V transistor. 
         [0143]    Alternatively, assuming that VDD SYS  is equal to 3.3V, and that 2.5V transistors with a V TP  (PMOS threshold) of 0.4V are being used, the “off” V DG  voltage of transistor P 2  will be equal to 1.6V−3.3V=−1.7V. Therefore, the V DG  voltage of transistor P 2  is within acceptable limits for a 2.5V transistor. 
         [0144]    Again referring to Table 3, when switched PMOS transistors P 4  and P 7  in stages SG 3 -SG 4  are turned off, their “off” drain-to-gate voltage V DG  will be equal to 5V TP −VDD SYS . Thus, assuming that VDD SYS  is equal to 5V, and that 3.3V transistors with a V TP  (PMOS threshold) of 0.6V are being used, the “off” V DG  voltage of transistors P 4  and P 7  will be equal to 3V−5V=−2V. Therefore, the V DG  voltages of transistors P 4  and P 7  are within acceptable limits for 3.3V transistors. 
         [0145]    Alternatively, assuming that VDD SYS  is equal to 3.3V, and that VDD INT  is equal to 2.5V, and that 2.5V transistors with a V TP  (PMOS threshold) of 0.4V are being used, the “off” V DG  voltage of transistors P 4  and P 7  will be equal to 2V−3.3V=−1.3V. Therefore, the V DG  voltages of transistors P 4  and P 7  are within acceptable limits for 2.5V transistors. 
         [0146]    As shown in Table 3, when switched PMOS transistor P 11  in stage SG 5  is turned off, its “off” drain-to-gate voltage V DG  will be equal to V TP −VDD INT . Furthermore, since this expression only contains low voltage parameters (i.e. the low voltage PMOS transistor threshold V TP , and the low voltage power supply voltage VDD INT ), the resulting “off” V DG  voltage of transistor P 11  will always remain within acceptable limits for 3.3V transistors, and for 2.5V transistors. For example, assuming that VDD SYS  is equal to 5V, and that VDD INT  is equal to 3.3V, and that 3.3V transistors with a V TP  (PMOS threshold) of 0.6V are being used, the “off” V DG  voltage of transistor P 11  will be equal to 0.6V−3.3V=−2.7V. Therefore, the V DG  voltage of transistor P 11  is within acceptable limits for a 3.3V transistor. 
         [0147]    Alternatively, assuming that VDD SYS  is equal to 3.3V, and that VDD INT  is equal to 2.5V, and that 2.5V transistors with a V TP  (PMOS threshold) of 0.4V are being used, the “off” V DG  voltage of transistor P 11  will be equal to 0.4V−2.5V=−2.1V. Therefore, the V DG  voltage of transistor P 11  is within acceptable limits for a 2.5V transistor. 
         [0000]    
       
         
               
               
               
               
             
           
               
                 TABLE 3 
               
               
                   
               
               
                   
                 Drain 
                 Gate 
                   
               
               
                   
                 Voltage 
                 Voltage 
                 Drain to Gate Voltage 
               
               
                 Stage/PMOS Transistor 
                 V D   
                 V G   
                 V DG  = V D  − V G   
               
               
                   
               
             
             
               
                 Stage SG2, P2 on 
                 VDD SYS   
                 3 V TP   
                 VDD SYS  − 3 V TP   
               
               
                 Stage SG2, P2 off 
                 3 V TP   
                 VDD SYS  − V TP   
                 4 V TP  − VDD SYS   
               
               
                 Stage SG3, P4 on 
                 VDD SYS  − V TP   
                 2 V TP   
                 VDD SYS  − 3 V TP   
               
               
                 Stage SG3, P4 off 
                 3 V TP   
                 VDD SYS  − 2 V TP   
                 5V TP  − VDD SYS   
               
               
                 Stage SG4, P7 on 
                 VDD SYS  − 2 V TP   
                 V TP   
                 VDD SYS  − 3 V TP   
               
               
                 Stage SG4, P7 off 
                 2 V TP   
                 VDD SYS  − 3 V TP   
                 5V TP  − VDD SYS   
               
               
                 Stage SG5, P11 on 
                 VDD SYS  − 3 V TP   
                 0 
                 VDD SYS  − 3 V TP   
               
               
                 Stage SG5, P11 off 
                 V TP   
                 VDD INT   
                 V TP  − VDD INT   
               
               
                   
               
             
          
         
       
     
         [0148]    In summary, the on/off drain-to-gate voltages V DG  of the switched PMOS transistors in stages SG 2 -SG 5  will remain within acceptable limits, under all circuit conditions. 
         [0149]    In addition, although the examples shown above have been limited to VDD voltages of 5V, 3.3V, and 2.5V, the invention can be utilized with other VDD voltages. Furthermore, in accordance with the invention, as the VDD SYS  and VDD INT  voltages become further apart, additional diode-connected PMOS transistors may be required, and additional buffer stages may also be required. 
         [0150]    It should be understood that the above descriptions are examples of the invention, and that various alternatives of the invention described herein may be employed in practicing the invention. Therefore, it is intended that the following claims define the scope of the invention, and that structures and methods within the scope of these claims and their equivalents be covered thereby.