Abstract:
Method for generating a time-limited signal.  
     In the previously known methods, the circuit arrangements for generating a time-limited signal continue to draw current even after the signal has been generated.  
     With the new method, the circuit arrangement draws no current after the time-limited signal has been generated.

Description:
BACKGROUND  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a method for generating a time-limited signal, in accordance with the preamble of claim  1 .  
           [0003]    2. Description of the Related Technology  
           [0004]    A method of this kind is known from the publication DE 100 24 980.9. After providing a supply voltage, an initialization signal (Power-on-Reset) is generated for a following circuit arrangement. A disadvantage is that the method calls for an elaborate circuit arrangement that requires a large chip surface and that the circuit arrangement continues to consume electric current after the reset signal has been generated.  
           [0005]    In general, methods for generating a time-limited signal are used in particular by so-called “reset” or initialization signals” in order to set defined electrical parameters or initial states in circuit arrangements after applying a supply voltage. Another important application of signals of limited duration is the change of states while an electrical circuit arrangement is in operation. Furthermore, it is important to develop methods for circuit arrangements that should have a low operating current or consume little current in the quiescent state in order, for instance, to keep the discharge rate of a battery low. In particular in applications in motor vehicles with the 42 volt vehicle electrical system, it is important for these arrangements to consume little current even where there are high supply voltages.  
         SUMMARY OF THE INVENTION  
         [0006]    The object of the present invention is to specify a method for generating a time-limited signal that reduces the current consumption in a circuit arrangement. Another object of the invention is to specify a circuit arrangement for performing the method that can be produced by simple means and at low cost.  
           [0007]    The first of these objects is solved by the features of claim 1 while the solution for the second of these objects is demonstrated by the features of claim 12. Favorable modifications to the design are given in Subclaims.  
           [0008]    Accordingly, the essence of the invention is to generate a time-limited signal in a circuit arrangement by means of a capacitive voltage divider and to reduce the flow of current in the circuit arrangement to zero after the signal has been generated. For this purpose, in order to generate a time-limited signal, at at least one signal output of a circuit arrangement, that has at least one first switching unit and one second switching unit each having an output and an input and a capacitive voltage divider with a first divider junction and a second divider junction, the circuit arrangement is put into a current-carrying state for just a limited period of time by applying the supply voltage and within this period of time a time-limited signal is fed to a signal output of the circuit arrangement. After applying the supply voltage, current flows from the first divider junction to the input of the first switching unit thereby discharging the first divider junction and during the discharging time the input of the second switching unit is activated by the output of the first switching unit and the second divider junction is charged by means of the output of the second switching unit and the time-limited signal is taken from a circuit junction within the circuit arrangement. The time-limited signal is determined here by the discharging time of the first divider junction and/or by the charging time of the second divider junction.  
           [0009]    One advantage of the method is that the circuit arrangement consumes no further current after the time-limited signal has been generated. This allows a time-limited signal to be provided for further switching units without the initialization circuit increasing the current flow in the overall system after generation of the time-limited signal. The period over which current is input to the circuit arrangement is determined by the discharging times and the size of the capacitances of the capacitive voltage divider. Furthermore, within the period in which current is flowing in the circuit arrangement, it is possible to determine by the electrical parameters of the switching units the duration and rise behavior of the output signal. In addition, the duration of the output signal depends on the point at which the time-limited signal is output. Studies made by the applicant have shown that the method can be applied over a wide range of supply voltages, for instance between 3 and 60 volts, the maximum voltage depending on the electric strength of the components used in the circuit arrangement. Also, by disconnecting and reconnecting the circuit arrangement to the supply voltage, it is possible to generate several time-limited signals in succession. Moreover, by means of the voltage thresholds in the respective switching units, the time-limited signal can be generated reliably even at low supply voltages of, for example, 5 volts and lower and also when the supply voltage builds up slowly.  
           [0010]    In a further development of the method, the second switching unit is activated by means of current from the first switching unit. This current is limited by a negative-feedback element in order to suppress overshoot and too rapid charging of the second divider junction. The limitation of the output current of the first switching unit can be performed either with a current source circuit or with a passive component such as a resistor  
           [0011]    In another development of the method, the voltage at the second divider junction that is pulled towards the supply voltage level by the charging current of the second circuit arrangement is limited to a preset potential by means of a voltage-limiting element. With high supply voltages in particular, for instance voltages above 60 volts, capacitors with a much lower electric strength can be used between the first divider junction and the second divider junction. In this case, it is advantageous to limit the voltage by means of a diode structure, preferably by means of a Zener diode  
           [0012]    In a further development of the method, current is caused to flow through a first current-controlled switch by means of the first divider junction within the first switching unit and current is caused to flow through a second divider junction by means of a second current-controlled switch within the second switching unit. In this case, it is advantageous to limit the output current of the second switch by a resistor Studies made by the applicant have shown that it is advantageous to feed out the time-limited signal by means of an additional driver transistor in order to avoid influencing the charging or discharging process between the two divider junctions. The driver transistor generates, for example, a time-limited current which can be transformed into a voltage signal by means of a resistor.  
           [0013]    In another further development of the method, current is caused to flow through a first current mirror from the first divider junction within the first switching unit and current is caused to flow through the second divider junction by means of a second current mirror within the second switching unit. An advantage of the current mirror circuit is that, as opposed to the current-controlled switches, it has no passive components and in particular for small capacitances of the voltage divider it can be produced in a small size and at low cost. Furthermore, studies made by the applicant have shown that it is advantageous for one of the mirror circuits to be extended by means of an additional transistor to form a current bank in order to feed out the time-limited signal. In particular when using MOS transistors here, the current in the current mirrors is influenced only slightly. Furthermore, in a development of the method, the current mirror circuit can be combined with the circuit of the current-controlled switch.  
           [0014]    Other studies made by the applicant have shown that it is of advantage when the capacitor between the reference potential and the first divider junction and the capacitor between the supply voltage and the second divider junction are formed by the parasitic capacitors at the input and the output respectively of the switching units. Since only the capacitor between the first divider junction and the second divider junction is provided in the form of a passive component, the circuit arrangement can be produced with a small surface area and at low cost.  
           [0015]    In a further development of the invention, the time-limited signal is fed out preferably at the second divider junction by means of a capacitive element, such as a capacitor for example. In this case, the current consumption of the circuit arrangement can be reduced and the additional driver transistor for driving the output is omitted.  
       
    
    
     BRIEF DESCRIPTION OF THE FIGURES  
       [0016]    The method according to the invention will now be explained with reference to several schematic examples of embodiment in conjunction with the drawings. The drawings show:  
         [0017]    [0017]FIG. 1 a  a circuit arrangement with a capacitive circuit divider and two switching units, and  
         [0018]    [0018]FIG. 1 b  the relationship between the rise in voltage at the input of the circuit arrangement and the time-limited signal at the output of the circuit arrangement of FIG. 1 a , and  
         [0019]    [0019]FIG. 2 a voltage-limiting element for protecting the circuit arrangement against overvoltage, and  
         [0020]    [0020]FIG. 3 an embodiment of the circuit arrangement with two current-controlled switches in the switching unit, and  
         [0021]    [0021]FIG. 4 an embodiment of the circuit arrangement with two current mirrors in the switching units, and  
         [0022]    [0022]FIG. 5 an embodiment of the circuit arrangement in which the input and output capacitance respectively of the current mirrors form a part of the capacitive voltage divider. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0023]    The circuit arrangement SA shown in FIG. 1 a  generates a time-limited signal S 1  at an output A 1  by applying a supply voltage VS. After applying this supply voltage, a current IE 1  flows through the circuit arrangement SA over a period of time ZG in which the time-limited signal S 1  is fed in the output A 1 . After signal S 1  has been generated, the circuit arrangement SA consumes no further current The relationship in terms of time between the applying of the supply voltage VS and the rise of voltage UE 1  at the input E 1 , as well as the current IE flowing into the input E 1  and the signal S 1  is shown schematically in FIG. 1 b  in a voltage/time chart and in a current/time chart.  
         [0024]    Here follows an explanation of the design of the circuit arrangement SA. The circuit arrangement SA has an input E 1  to which a supply voltage VS is applied. The input E 1  is connected to a series circuit comprising a capacitor C 3 , a capacitor C 2  and a capacitor C 1  which is connected to the reference potential. The series circuit of capacitors C 1  to C 3  forms a capacitive voltage divider with a first divider junction K 1  between the capacitor C 1  and the capacitor C 2  and a second divider junction K 2  between the capacitor C 2  and the capacitor C 3 . Furthermore, the circuit arrangement SA has a first switching unit SE 1  which is connected to the reference potential and a second switching unit SE 2  which is connected to the input E 1 . Additionally, the first divider junction K 1  is connected to an input STE 1  of the first switching unit SE 1  Also, the first switching unit SE 1  has an output STA 1  which is connected to an input STE 2  of the second switching unit SE 2  via a current-limiting element IB 1  that is connected in series. In addition, the switching unit SE 2  has an output STA 2  which is connected to the second divider junction K 2 . Moreover, the first switching unit SE 1  is connected to the output A 1  by means of a signal output.  
         [0025]    In the following, the mode of operation of the circuit arrangement SA will be explained with reference to the charts shown in FIG. 1 b . After the supply voltage VS has been applied, the supply voltage UE 1  at input E 1  of the circuit arrangement SA rises slowly up to the level of the supply voltage VS, as shown in FIG. 1 b , the difference in time between the level of the supply voltage VS and the rise of voltage UE 1  being mainly due to parasitic resistances and inductances. Current then flows through the capacitive voltage divider and the capacitors C 1  to C 3  and the divider junctions K 1  and K 2  are charged. Via the divider junction K 1 , current flows at the input of the switching unit SE 1  while the divider junction K 1  is discharged. Subsequently, current flows from the switching unit SE 1  through the input STE 2  of the switching unit SE 2  via the current-limiting element IB 1 , while the switching unit SE 2  causes current to flow via the output STA 2  to the divider junction K 2 , which then charges. Because of the current flowing through the circuit arrangement SA, the signal S 1  is fed to the output A 1  for a time Z 1 , as shown in FIG. 1 b , after a time Z 0  which is determined primarily by the divider ratios of the voltage divider and the voltage threshold values of the switching unit SE 1 . After a further time Z 2 , in which the signal S 1  is no longer fed to the output A 1 , current ceases to flow through the circuit arrangement SA. The time ZG, in which current flows through the switching unit SE 1 , is determined primarily by the discharge time of the divider junction K 1 . This discharge time is dependent on the magnitude of the further charging of the divider junction K 2  and the current flowing through the input STE 1  or alternatively by voltage thresholds within the switching unit SE 1 .  
         [0026]    An advantage of the circuit arrangement SA is that the circuit arrangement SA draws current only within the period of time ZG. The time ZG is determined here by the effective RC times of the circuit arrangement SA and the magnitudes of the currents that flow through the two divider junctions K 1  and K 2 . Furthermore, either a resistor or a current source can be used as negative-feedback element IB 1  in the circuit arrangement SA in order to limit the current.  
         [0027]    In the circuit arrangement SA for generating the time-limited signal S 1 , as shown in FIG. 2, the voltage at the divider junction K 2  is limited by means of a voltage-limiting element VB 1  which is connected to the reference potential. Furthermore, the circuit arrangement SA has another output A 2  at which a time-limited signal S 2  can be fed out, for instance by means of a capacitive element, preferably a capacitor.  
         [0028]    The explanations given below are in addition to what has been said with reference to the drawings of FIG. 2. Furthermore, above the voltage threshold of the voltage-limiting element VB 1 , which takes the form of a Zener diode for example, the current is diverted from the divider junction K 2  and flows to the reference potential, which means that further charging of the divider junction K 2  is suppressed. Once charging of the divider junction K 2  has been completed, the divider junction K 1  is no longer charged by the divider junction K 2  and is therefore discharged faster by the switching unit SE 1 . Consequently, the time needed for the switching unit SE 1  to trigger the switching unit SE 2  is reduced. As a result, the time Z 2  in particular and the time ZG, in which a time-limited signal S 1  is fed to the output A 1  and in which the current IE flows through the circuit arrangement SA, is reduced  
         [0029]    An advantage of the voltage-limiting element VB 1  is that, especially at high supply voltages, the capacitor C 2  need have only a low electric strength. Furthermore, the time ZG, in which the current IE flows through the circuit arrangement, can be changed by the voltage threshold of the voltage-limiting element VB 1 , the time ZG being proportional to the level of the voltage threshold of the voltage-limiting element VB 1 . Furthermore, when the time-limited signal S 2  is fed out at output A 2 , the output A 1  on the switching unit SE 1  can be omitted.  
         [0030]    In the circuit arrangement SA shown in FIG. 3, the time-limited signal S 1  is generated by the two switching units SE 1  and SE 2  by means of a first current-controlled switch IS 1  and a second current-controlled switch IS 2 . Here, the output A 1  is triggered with the signal S 1  from switch IS 1  by means of a driver transistor T 7 , provided the output A 1  is connected via a resistance element to a potential that is above the reference potential. In addition, the output current of the switch IS 2  is limited by means of an element IB 2 .  
         [0031]    The circuit arrangement in the two switching units SE 1  and SE 2  will now be described in more detail. The input STE 1  is connected to a resistor R 1  that is connected to the reference potential, and to the control input of a transistor T 6 , and to the control input of the driver transistor T 7 . Also, the source of the transistor T 6  and the source of the transistor T 7  are each connected to the reference potential. The drain of the transistor T 6  is connected to the output STA 1  of the switching unit SE 1  Furthermore, in the second switching unit SE 2  the input STE 2  is connected to a resistor R 2 , that is connected to the power supply VS, and to the control input of the transistor T 8 . The source of the transistor T 8  is connected to the input E 1 . The drain of the transistor T 8  is connected to the output STA 2  via the current-limiting element IB 2  which is provided, for example, in the form of a resistor.  
         [0032]    The mode of operation of the two current-controlled switches IS 1  and IS 2  will now be explained below. After the supply voltage VS has been applied to the input E 1 , current flows through the resistor R 1  in accordance with the potential at the divider junction K 1 , and consequently the transistor T 6  or T 7  respectively becomes conductive above the relevant threshold voltage due to the voltage drop across the resistor R 1 . Subsequently, current flows from transistor T 7  to the output A 1  Furthermore, current flows from the input E 1  via the resistor R 2 . If the magnitude of the voltage drop across the resistor R 2  is greater than the threshold voltage at transistor T 8 , current flows at the junction K 2  via the output STA 2 . When the voltage at resistor R 1  drops below the threshold voltage of the transistor T 6  or T 7  respectively, no current flows through the resistor R 2  and at output A 1 , i.e. the junction K 2  is no longer charged via the output STA 2 .  
         [0033]    An advantage of the particular design of the circuit arrangement SA is that in place of the first switch IS 1  the second switch IS 2  can also be connected to the output A 1  via an additional driver transistor in order to thereby provide a time-limited signal for a following circuit stage.  
         [0034]    In FIG. 4, the time-limited signal S 1  is generated by the two switching units SE 1  and SE 2  by means of a first current mirror SPI and a second current mirror SP 2 . Signal S 1  is sent here to the output A 1  in the circuit arrangement SA from the current mirror SP 1  via a driver transistor T 3 , provided a potential that is greater than the reference potential has been placed on output A 1  via a resistance element. Furthermore, to limit the voltage at the capacitor C 2 , the divider junction K 2  is connected to the voltage-limiting element VB 1 . The circuit arrangement in the two switching units SE 1  and SE 2  will now be described below.  
         [0035]    The input of the first switching unit SE 1  is connected to a NMOS transistor T 1  that is connected as a diode, i.e. the drain and the gate of the transistor T 1  are connected together. The source of the transistor T 1  is connected to the reference potential and to the source of a NMOS transistor T 2  and to the source of a NMOS transistor T 3 . The gate of the transistor T 1  is connected to the gate of the transistor T 2  and to the gate of the transistor T 3 . Furthermore, the drain of the transistor T 2  is connected to the output STA 1  of the switching unit. Also, the drain of the transistor T 3  is connected to the output A 1 . In the switching unit SE 2 , the source of a NMOS transistor T 4  and the source of a PMOS transistor T 5  are connected to the input E 1 . Furthermore, the drain of the transistor T 5  is connected to the output STA 2  of the switching unit SE 2 . Also, the gate of the transistor T 5  is connected to the gate of the transistor T 4 , to the drain of the transistor T 4 , and to the input STE 2  of the switching unit SE 2 .  
         [0036]    The mode of operation of the circuit arrangement SA will now be described below. After the supply voltage VS has been applied to the input E 1 , the transistor T 1  becomes conductive. If the voltage at the gate of the transistor T 1  rises above the threshold voltage of the transistor T 2  or of transistor T 3  respectively, both transistors T 2  and T 3  respectively become conductive. Subsequently, current flows from the transistor T 3  to the output A 1  Furthermore, the current IE flows from the input E 1  through the transistor T 2  and the transistor T 4 . If the magnitude of the voltage drop across the transistor T 4  is greater than the threshold voltage at the transistor T 5 , the junction K 2  receives current via the output STA 2 . If the voltage at the transistor T 1  drops below the threshold voltage of the transistor T 2  or T 3  respectively, current ceases to flow at the output A 1  and through the transistor T 4 , i.e. the junction K 2  is no longer charged via the output STA 2 .  
         [0037]    An advantage of the current mirror arrangement is that this design of the circuit arrangement SA requires only a small chip surface and can be manufactured at an especially low cost. Furthermore, the circuit arrangement SA draws little current on account of the two current mirror circuits, the transistors of which can be activated, for example, in the subthreshold range. Together with small capacitances in the voltage divider, it is possible here to generate long time-limited signals.  
         [0038]    In FIG. 5, the time-limited signal S 2  is generated by the two switching units SE 1  and SE 2  by means of the two current mirrors SP 1  and SP 2 . The capacitors C 1  and C 3  are replaced here by the input capacitances and output capacitances respectively of the two switching units SE 1  and SE 2  and hence by the two current mirrors SP 1  and SP 2 . In the following, reference will be made to the explanations concerning the drawings relating to FIG. 4, although in contrast to the circuit arrangement shown in FIG. 4 the voltage-limiting element VB 1  is connected to the divider junction K 2  and, by feeding out the signal S 2  at the output A 2 , both the output A 1  and the transistor T 3  are omitted.  
         [0039]    The mode of operation will now be explained. Because of the design of the capacitive circuit divider using the input capacitance of the switching unit SE 1  and the output capacitance of the switching unit SE 2 , the total capacitance within the circuit arrangement is small and the current that flows in the input E 1  after the supply voltage VS has been applied is very small since the charging and discharging currents are also small. In addition, the surface area of the transistors can be reduced considerably. In total, the chip area is reduced. Furthermore, due to the voltage-limiting element VB 1  the demands with respect to electric strength are reduced. In particular with high supply voltages and technologies that provide only capacitors with a low specific capacitance, the integration capability of the circuit arrangement is enhanced.  
         [0040]    An advantage of the method is that the circuit arrangement can be designed with both bipolar and MOS transistors. In addition, the method and the circuit arrangement can be applied over a wide range of supply voltages. Furthermore, by disconnecting from the supply voltage and then reconnecting to it, several successive time-limited signals can be generated, while the circuit arrangement draws no current after the time-limited signal has been generated.