Abstract:
A voltage level shifter is disclosed that includes low voltage devices. In some implementations, a voltage level shifter having a differential structure includes low voltage, complementary N-channel metal oxide semiconductor (NMOS) input transistors and low voltage, complementary cross-coupled P-channel metal oxide semiconductor (PMOS) output transistors. One or more complementary NMOS/PMOS series intermediate transistor pairs are interposed between respective drains of the NMOS transistors and PMOS transistors to limit high voltage drops across the NMOS input transistors and PMOS output transistors. In some implementations, each intermediate transistor pair is biased by a single intermediate voltage. The sources of the low voltage devices are connect to a bulk/substrate. The complementary outputs of the level shifter can be taken from the drains of the NMOS/PMOS series intermediate transistor pairs.

Description:
TECHNICAL FIELD 
       [0001]    This subject matter relates generally to electronic circuits, and more particularly to voltage level shifters for use in flash memories and other devices which require high voltage management. 
       BACKGROUND 
       [0002]    Conventional flash memories use high voltage devices to manage a high supply voltage. The circuitry of the flash memories includes charge pump circuits and level shifters. The charge pump circuits and level shifters often include high voltage transistors that require additional masks during fabrication. The additional masks can add additional costs to the manufacturing process. 
       SUMMARY 
       [0003]    A voltage level shifter is disclosed that includes low voltage devices. In some implementations, a voltage level shifter having a differential structure includes low voltage, complementary N-channel metal oxide semiconductor (NMOS) input transistors and low voltage, complementary cross-coupled P-channel metal oxide semiconductor (PMOS) output transistors. One or more complementary NMOS/PMOS series intermediate transistor pairs are interposed between respective drains of the NMOS transistors and PMOS transistors to limit high voltage drops across the NMOS input transistors and PMOS output transistors. In some implementations, each intermediate transistor pair is biased by a single intermediate voltage. The sources of the low voltage devices are connect to a bulk/substrate. The complementary outputs of the level shifter can be taken from the drains of the NMOS/PMOS series intermediate transistor pairs. The basic level shifter circuit described above can be replicated and added to output stages to create additional level shifter circuits that are capable of providing higher voltage differences. 
         [0004]    Advantages of the disclosed voltage level shifters with low voltage devices include, but are not limited, reduced fabrication costs through the use of standard process devices and the elimination of additional masks associated with high voltage device fabrication. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]      FIG. 1  is a schematic diagram of an example conventional level shifter circuit including high voltage devices. 
           [0006]      FIG. 2  is a schematic diagram of an example 2VDD level shifter circuit with low voltage devices. 
           [0007]      FIG. 3  is a schematic diagram of an example 3VDD level shifter circuit with low voltage devices. 
           [0008]      FIG. 4  is a schematic diagram of an example 4VDD level shifter circuit with low voltage devices. 
           [0009]      FIG. 5  is a schematic diagram of an example 5VDD level shifter circuit with low voltage devices. 
           [0010]      FIG. 6  is block diagram illustrating how a 4VDD level shifter can be extended to (N)VDD. 
       
    
    
     DETAILED DESCRIPTION 
     Example Voltage Level Shifter with High Voltage Devices 
       [0011]      FIG. 1  is a schematic diagram of an example conventional level shifter circuit  100  with high voltage (HV) devices. For  FIGS. 1-6 , the annotation V 1 /V 2  shown at a node of a level shifter circuit is interpreted as follows: V 1  is a voltage given by a logic input and V 2  is a voltage given by the complementary logic input. In  FIG. 1 , for example, if V 1 =3 volts, then V 2 =0 volts. To perform read, program and erase operations in embedded flash memory, it is often necessary to apply high voltages (e.g., higher than a typical control logic voltage supply) to the flash cell. A voltage level shifter takes a low voltage supply VDD and shifts it to a higher voltage, such as 2*VDD, 3*VDD, 4*VDD, and so forth. 
         [0012]    The conventional voltage level shifter circuit  100  shown in  FIG. 1  has a differential structure and uses complementary, cross-coupled PMOS output transistors P 1 , P 2 , and complimentary NMOS input transistors N 1 , N 2 , respectively. The gates of the input transistors N 1 , N 2  receive complementary input voltages IN and IN_N (e.g., 3/0V, 0/3V) and the drains of the output transistors P 1 , P 2  provide complementary, level-shifted output voltages (0V/HV, HV/0V). 
         [0013]    The transistors P 1 , P 2 , N 1  and N 2  are all high voltage devices. In the voltage level shifter circuit  100 , the maximum voltage difference between the nodes of transistors P 1 , P 2 , N 1 , N 2  is the voltage applied on HV, which can be higher than 15V. The high voltage transistors P 1 , P 2 , N 1 , N 2  must be processed to sustain HV if HV exceeds the break down voltage of the transistors P 1 , P 2 , N 1 , N 2  (e.g., Max 5V for 70A transistor). Such processes increase complexity and cost through the use of additional masks and process steps. 
       Example Voltage Level Shifters with Low Voltage Devices 
       [0014]      FIG. 2  is a schematic diagram of an example 2VDD level shifter circuit  200  with low voltage devices. A first branch (left branch) of the voltage level shifter circuit  200  includes a PMOS transistor P 1  coupled in series with a PMOS/NMOS series intermediate transistor pair P 3 , N 3 , where “P” indicates a PMOS device and “N” indicates an NMOS device. The intermediate transistor pair P 3 , N 3  is interposed between the drains of output transistor P 1  and input transistor N 1 . A second branch (right branch) of the voltage level shifter circuit  200  includes an output transistor P 2  coupled in series with a PMOS/NMOS series intermediate transistor pair P 4 , N 4 . The intermediate transistor pair P 4 , N 4  is interposed between the drains of output transistor P 2  and input transistor N 2 . 
         [0015]    The output transistors P 1 , P 2  are cross-coupled. The gates of input transistors N 1 , N 2  receive complementary input voltages. The gates of the intermediate transistor pair P 3 , N 3  are coupled to an intermediate bias voltage (e.g., 3V). In a shared-bias configuration, the gates of the intermediate transistor pair P 4 , N 4  are also coupled to the intermediate bias voltage. The voltage source can be provided by, for example, a low voltage charge pump circuit. In some implementations, the intermediate transistor pairs can be configured in a split-bias configuration, where the PMOS transistor in the intermediate transistor pair is biased by a first bias voltage and the NMOS transistor in the intermediate transistor pair is biased by a second bias voltage. 
         [0016]    In the voltage level shifter circuit  200 , the maximum voltage difference has been reduced due to bias voltages applied to the intermediate transistor pairs. The source of each of the low voltage transistors used in the voltage level shifter circuit  200 , including the transistors used in the intermediate transistor pairs is connected to the bulk or substrate to avoid voltage drops between bulk-drain, bulk-source and bulk-gate. A triple well process can be used to form these bulk connections. 
         [0017]    The intermediate transistor pairs effectively limit a high voltage drop on the input transistors N 1 , N 2  and output transistors P 1  and P 2  by maintaining their gates at a specified bias voltage (e.g., 3V). For example, if IN=3V, the source of transistor N 3  is set to 0V by transistor N 1  and the drain of transistor P 3  is set to 0V by transistor N 3 . The transistor P 3  prevents the voltage level on the drain of P 1  from dropping to 0V which could damage transistor P 1 . Transistor P 3  allows discharge of the drain of transistor P 1  until the gate voltage of transistor P 3  (e.g., 3V) is reached (the transistor is OFF; vgs=0V). The use of transistor N 3  in the intermediate transistor pair can be explained by applying IN=0V. With this input voltage, transistor N 3  prevents the voltage level on the drain of transistor N 1  from being set higher than the gate voltage of transistor N 3  (3V instead of 6V). The output voltages can be tapped from the drains of the transistors of the intermediate transistor pairs. For example, 6/0V output voltages can be tapped from the drains of transistors P 4 , N 4 , which have been coupled together. 
         [0018]    The basic level shifter circuit  200  can be replicated and combined with output stages to create additional voltage level shifter circuits with higher voltage differences, as described in reference to  FIGS. 3-6 . 
         [0019]      FIG. 3  is a schematic diagram of an example 3VDD level shifter circuit  300  with low voltage devices. In a first branch (left branch) two intermediate transistor pairs P 3 , P 5  and N 3 , N 5  are interposed between the drains of output transistor P 1  and input transistor N 1 . The gates of P 3  and N 5  are coupled to first intermediate bias voltage (e.g., 6V). The gates of P 5  and N 3  are coupled to a second intermediate bias voltage (e.g., 3V). The source of all transistors is connected to the bulk. An output stage is added to generate an output voltage at 9V or 0V because this combination of voltages is not directly available on the core circuit. On each of the branches the maximum voltage drop is equal to VDD. 
         [0020]    In some implementations, the output stage is a single branch that includes transistors P 7 , P 8 , P 9 , N 9 , N 8  and N 7  coupled in series. The gate of P 7  is coupled to the gate of transistor P 2 . The gates of transistors P 9  and N 9  are coupled to the sources of transistors P 6  and N 6 . The gate transistor P 8  is coupled to a 6V intermediate bias voltage and the gate of N 8  is coupled to a 3V intermediate bias voltage. The output voltage can be tapped from the drains of P 9  and N 9 , which are coupled together. 
         [0021]      FIG. 4  is a schematic diagram of an example 4VDD level shifter circuit  400  with low voltage devices. The level shifter circuit  400  uses the same output stage as the level shifter circuit  300 . The sources of all transistors used in circuit  400  are connected to the bulk. 
         [0022]    A first branch (left branch) includes output transistor P 1  and input transistor N 1  with intermediate transistor pairs P 3 /N 7 , P 5 /N 5  and P 7 /N 3  interposed between the drains of transistor P 1  and transistor N 1 . A second branch (right branch) includes output transistor P 2  and input N 2  with intermediate transistor pairs P 4 /N 8 , P 6 /N 6 , and P 8 /N 4  interposed between the drains of output transistor P 2  and input transistor N 2 . 
         [0023]    The output stage includes a single branch with series coupled transistors P 9 , P 10 , P 11 , P 12 , N 12 , N 11 , N 10  and N 9 . The gate of transistor P 9  is coupled to the gate of transistor P 2 , the gate of transistor P 11  is coupled to the sources of transistors N 8  and P 6 , the gates of transistors P 12  and N 12  are coupled to the sources of transistors P 6  and N 6 . An output voltage can be tapped from the drains of transistors P 12 , N 12  in the output stage. All of the transistors in circuit  400  have their sources connected to the bulk. 
         [0024]      FIG. 5  is a schematic diagram of an example 5VDD level shifter circuit  500  with low voltage devices. In circuit  500 , the previous 4VDD stage is used to control the output gate voltage. A first branch (left branch) includes output transistor P 1  and input N 1  with intermediate transistor pairs P 3 /N 9 , P 5 /N 7 , P 7 /N 5 , P 9 /N 3 , interposed between the drains of output transistor P 1  and input N 1 . A second branch (right branch) includes output transistor P 2  and input transistor N 2  with intermediate transistor pairs P 4 /N 10 , P 6 /N 8 , P 8 /N 6 , P 10 /N 4  interposed between the drains of output transistor P 2  and input transistor N 2 . The sources of all transistors in circuit  500  are coupled to the bulk. An output voltage (e.g., 15/0V) can be tapped from the drains of transistors P 15 , N 11 . 
         [0025]    The output stage includes a single branch of series coupled transistors P 11 , P 12 , P 13 , P 14 , P 15 , N 11 , N 12 , N 13 , N 14  and N 15 . The gate of transistor P 11  is coupled to the gate of output transistor P 2 . The gate of transistor P 13  is coupled to the sources of transistors P 6  and N 10 , which are coupled together. The gate of transistor N 12  is coupled to the drains of transistors P 8  and N 6 , which are coupled together. The gate of transistor N 13  is coupled to the sources of transistors N 6  and P 10 , which are coupled together. 
         [0026]    In circuit  500 , a command voltage 12V/3V is applied on the gates of transistors P 15  and N 11 . This command voltage can be generated by the 4VDD level shifter circuit  400 , described in reference to  FIG. 4 . The circuit  400  can be used in a cascade to create additional level shifter circuits with higher voltage drops, such as 6VDD, 7VDD, 8VDD and so forth. 
         [0027]      FIG. 6  is block diagram illustrating how the 4VDD level shifter circuit  400  can be extended to (N)VDD. An output voltage of the 4VDD level shifter circuit  400  can be used as a command voltage in 5VDD, 6VDD . . . (N)VDD level shifter circuits. Similarly, an output voltage of the 5VDD level shifter circuit  500  can be used as a command voltage in the 6VDD . . . (N)VDD level shifter circuits and so forth. 
         [0028]    The impact on the structure size of the level shifter circuits due to the intermediate transistor pairs is balanced by the reduced size of the standard devices compared to high voltage devices used in the conventional level shifter circuit  100  of  FIG. 1 . The limitation of the structure is the drop voltage between the well and the substrate if the voltage is increased too much. Extending this approach to the overall high voltage management of flash memory would result in noticeable embedded flash process cost savings, and simplified integration into base line CMOS processes. Moreover, the use of this structure is not limited only to flash memories but is also applicable to any circuit that requires high voltage management.