Abstract:
A DC-DC converter includes efficiency reporting circuitry having an output that is a measure of efficiency. In an example, the DC-DC converter has an input voltage, an output voltage, and a switching circuit converting the input voltage to an intermediate voltage, and the efficiency reporting circuitry determines the ratio between the output voltage and the intermediate voltage.

Description:
BACKGROUND 
     A DC-DC converter is an electronic circuit that converts a source of direct current (DC) from one voltage to another. For example, DC-DC converters are widely used in portable devices to provide power from a battery. DC-DC converters may also regulate the output voltage, compensating for varying load current and variations in the input voltage. 
       FIG. 1A  illustrates one common type of DC-DC converter. The DC-DC converter circuit  100  in  FIG. 1A  (simplified to facilitate illustration and description) is a switching step-down converter (the input voltage is higher than the output voltage), and the basic design is called a Buck converter. In  FIG. 1A , a power source  102  provides direct current at an input voltage V IN . The circuit  100  provides direct current to a load (R LOAD ) at an output voltage V OUT . Two electronic switches (SW 1 , SW 2 ) are controlled by a switch control circuit  106  and driver  108 . At most only one switch is closed at any one time. When SW 1  is closed, current from the source  102  flows into R LOAD  and a filter capacitor (C), and V OUT  rises linearly. In addition, when SW 1  is closed, energy is stored in L and C. When SW 2  is closed, current flows from stored energy in C and from stored energy in L, and V OUT  decreases linearly. A comparator  104  compares V OUT  to a reference voltage V REF , and the switch control circuit  106  adjusts the duty cycle of SW 1  in response to the output of comparator  104 . 
     There are many variations in topology and control of DC-DC converters. The circuit illustrated in  FIG. 1A  has a single inductor. There are variations, for example, LLC, with multiple inductor resonant circuits. The circuit illustrated in  FIG. 1A  uses output voltage feedback. Some circuits use current feedback. Some circuits have multiple feedback loops. 
     In general, there is a need to verify operation of a DC-DC converter (design testing, production testing, and system testing), and, in general, there is a need for improving efficiency. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a block diagram illustrating an example prior art embodiment of a DC-DC converter. 
         FIG. 1B  is a block diagram illustrating additional detail for part of the DC-DC converter of  FIG. 1A . 
         FIG. 2  is a block diagram illustrating an example embodiment of a DC-DC converter generating a voltage needed for a measure of efficiency. 
         FIG. 3  is a block diagram illustrating an example embodiment of a DC-DC converter having an output that is a measure of efficiency. 
         FIG. 4  is a block diagram illustrating an example embodiment of an analog-to-digital converter. 
         FIG. 5  is a block diagram illustrating an analog-to-digital converter configured to generate a measure of efficiency. 
         FIG. 6  is a block diagram illustrating an example embodiment of a flash analog-to-digital converter configured to determine a voltage ratio for a measure of efficiency. 
         FIG. 7A  is a block diagram illustrating an alternative example embodiment of a dual-slope integrating analog-to-digital converter configured to determine a voltage ratio for a measure of efficiency. 
         FIG. 7B  is an example timing diagram for the example embodiment of  FIG. 7A . 
         FIG. 7C  is a block diagram illustrating additional detail for part of the example embodiment of  FIG. 7A . 
         FIG. 7D  is a block diagram illustrating additional detail for an alternative example embodiment of a dual-slope integrating analog-to-digital converter configured to determine a voltage ratio for a measure of efficiency. 
         FIG. 8  is a block diagram of additional detail for an example embodiment of part of the DC-DC converter of  FIG. 3 . 
         FIG. 9  is a flow chart illustrating an example embodiment of a method for generating a measure of efficiency for a DC-DC converter. 
     
    
    
     DETAILED DESCRIPTION 
     Power supplies need to be designed for efficiency, the efficiency of systems needs to be verified during operation, and loads may need to be adjusted to improve power supply efficiency. Accordingly, there is a need for a DC-DC converter that provides a measure of efficiency as an output. 
     The power efficiency E of the circuit  100  of  FIG. 1A  is output power divided by input power (where V OUT , I OUT , V IN  and I IN  are all DC values): 
     
       
         
           
             E 
             = 
             
               
                 
                   V 
                   OUT 
                 
                 * 
                 
                   I 
                   OUT 
                 
               
               
                 
                   V 
                   IN 
                 
                 * 
                 
                   I 
                   IN 
                 
               
             
           
         
       
     
     In general, measuring currents (I IN  and l OUT ) adds complexity, and computing the products and division adds complexity. There is a need for a more straightforward way to measure efficiency. 
     The switches SW 1  and SW 2  in  FIG. 1A  switch at a duty cycle of D. That is, SW 1  is closed D percent of the time. Assuming ideal switches (that is, assuming no power loss in the switches), the DC switched node voltage V SW =D*V IN . The DC output current I OUT =I IN /D. Substituting D*I OUT  for I IN  in the above efficiency equation, efficiency E is: 
     
       
         
           
             E 
             = 
             
               
                 
                   
                     V 
                     OUT 
                   
                   * 
                   
                     I 
                     OUT 
                   
                 
                 
                   
                     V 
                     IN 
                   
                   * 
                   
                     ( 
                     
                       D 
                       * 
                       
                         I 
                         OUT 
                       
                     
                     ) 
                   
                 
               
               = 
               
                 
                   V 
                   OUT 
                 
                 
                   D 
                   * 
                   
                     V 
                     IN 
                   
                 
               
             
           
         
       
     
     Accordingly, for an ideal circuit, efficiency is V OUT /V SW . However, as discussed below, for an actual circuit, V SW  is less than D*V IN  because of switching and conduction losses in the switches. In general, there are multiple power losses that reduce efficiency. There are switching losses in the active switching circuitry, and in the circuitry driving the switches, and in the feedback circuitry. There are also conduction losses, such as switching transistor effective resistance, diode forward voltage drops, inductor winding resistance, and capacitor equivalent series resistance. In general, switching losses are insignificant except during very light load conditions. For heavy loads, efficiency is reduced primarily by conduction losses. 
       FIG. 1B  illustrates additional detail for part of the DC-DC converter of  FIG. 1A  specifically illustrating effective resistances that contribute to conduction losses. In  FIG. 1B , R SW1  depicts the effective on-resistance of switch SW 1 , R SW2  depicts the effective on-resistance of switch SW 2 , R L  depicts the winding resistance of inductor L, and R C  depicts the equivalent series resistance of capacitor C. In  FIG. 1B , the DC switched node voltage V SW  is less than D*V IN  because of conductive losses in R SW1  and R SW2 , and V OUT  is less than V SW  because of conductive losses in R L  and R C . The efficiency equation given above is still valid, but what is needed is a way to measure D*V IN , which is an ideal value and not an actual voltage that can be measured in the circuit of  FIGS. 1A and 1B  because of the losses in the switches SW 1  and SW 2 . 
     One example way to measure D*V IN  is to build a switching circuit with an input of V IN  and a duty cycle of D, but with negligible switching and conductive losses in the switches. In general, for MOSFET switches, switching losses are proportional to switching frequency and proportional to the values of parasitic capacitances. As the physical size of the MOSFET increases, parasitic capacitances also increase. Accordingly, switching losses can be made negligible by using very small transistors. Conductive losses can be made negligible by making the current through the switches negligible. 
       FIG. 2  illustrates a DC-DC converter circuit that generates D*V IN . In the circuit of  FIG. 2 , two additional switches (SW 3 , SW 4 ) have been added to the circuit of  FIG. 1A . In the example of  FIG. 2 , driver  108  drives switch SW 3  at the same time as SW 1 , and drives switch SW 4  at the same time as SW 2 . Therefore, the duty cycle D for switches SW 3  and SW 4  is the same as for switches SW 1  and SW 2 . SW 3  and SW 4  are physically very small to minimize switching losses. SW 3  and SW 4  drive an open circuit so that load current is negligible, therefore making conductive losses negligible. Since there are negligible losses, the DC output of the switches SW 3  and SW 4  is substantially equal to the ideal D*V IN . The DC value may be obtained, for example, by low pass filtering or integrating the pulse modulated waveform. 
     For efficiency measurement, given D*V IN , the ratio of V OUT  to D*V IN  needs to be determined.  FIG. 3  illustrates a DC-DC converter  300  having a digital efficiency output of E ( 308 ) (where E=V OUT /(D*V IN )). In  FIG. 3 , block  302  depicts switching circuitry, low-pass filtering, and feedback circuitry, which may be as illustrated in  FIG. 1A  but may also be other switching DC-DC converter configurations (for example, LLC). In  FIG. 3 , block  304  depicts circuitry to generate D*V IN , which may be as illustrated in  FIG. 2 . Finally, block  306  depicts efficiency measurement circuitry to generate a digital value of efficiency E ( 308 ). Efficiency measurement circuit  306  may comprise analog-to-digital conversion of V OUT  and analog-to-digital conversion of D*V IN  followed by digital computation of the ratio. However, in the following discussion, the digital value of the ratio is directly generated. Alternatively, or in addition to, efficiency measurement circuit  306  may generate an analog value of efficiency E A  ( 310 ), which will be discussed in more detail in conjunction with  FIG. 8 . 
       FIG. 4  is a simplified block diagram of an analog-to-digital converter (ADC). V REFADC  is a reference voltage that corresponds to the full-scale range of the ADC. Assuming “n” bits of resolution for the digital code output, the output is: 
     
       
         
           
             
               
                 Digital 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 Code 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 Output 
               
               = 
               
                 
                   V 
                   INADC 
                 
                 * 
                 
                   
                     2 
                     n 
                   
                   
                     V 
                     REFADC 
                   
                 
               
             
             ; 
             
               
                 where 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 
                   V 
                   INADC 
                 
               
               ≤ 
               
                 
                   V 
                   REFADC 
                 
                 . 
               
             
           
         
       
     
     In typical usage of an ADC, V REFADC  is fixed, and may or may not be an external input. However, for purposes of computing a voltage ratio for efficiency, V REFADC  may be a variable input. That is, if V OUT  in  FIG. 3  is coupled to V INADC  in  FIG. 4 , and if D*V IN  in  FIG. 3  is coupled to V REFADC  in  FIG. 4 , then: 
     
       
         
           
             
               Digital 
               ⁢ 
               
                   
               
               ⁢ 
               Code 
               ⁢ 
               
                   
               
               ⁢ 
               Output 
             
             = 
             
               
                 V 
                 OUT 
               
               * 
               
                 
                   2 
                   n 
                 
                 
                   D 
                   * 
                   
                     V 
                     IN 
                   
                 
               
             
           
         
       
     
     Accordingly, by making V REFADC  a variable input, an ADC can be used to directly provide a digital value of the voltage ratio that is a measure of efficiency.  FIG. 5  illustrates D*V IN  and V OUT  coupled to an ADC  500  to generate a digital measure of efficiency signal E. In  FIG. 5 , D*V IN  passes through signal conditioning circuitry  502 , and V OUT  passes through signal conditioning circuitry  504 , which will be explained in more detail below in conjunction with  FIGS. 7C and 7D . 
       FIG. 6  illustrates an example of an ADC configured to generate a digital measure of efficiency. In  FIG. 6 , ADC  600  is a flash ADC, simplified for purposes of illustration. In  FIG. 6 , V REFADC  (coupled to D*V IN ) is divided into thirds by a resistor ladder  602 . Comparators  604  and  606  compare fractions of D*V IN  to V OUT . The output of comparator  604  is a “one” if V OUT  is greater than or equal to ⅓*D*V IN . The output of comparator  606  is a “one” if V OUT  is greater than or equal to ⅔*D*V IN . An actual flash ADC has additional digital logic, and the resistor ladder may be different, but  FIG. 6  illustrates how V REFADC  may be a variable input, and how an ADC can provide a digital output of the ratio of V OUT /(D*V IN ). 
       FIG. 7A  illustrates an alternative example of an ADC configured to generate a digital measure of efficiency. In  FIG. 7A , ADC  700  is a dual-slope integrating ADC, simplified for purposes of illustration. A dual-slope integrating ADC is typically used to measure an unknown input voltage, for example in a voltmeter. In the typical usage, an unknown input voltage is applied to the input of an integrator, and the integrator is allowed to ramp up for a fixed amount of time. Then, a known reference voltage of the opposite polarity is applied to the input of the integrator, and the integrator is allowed to ramp down for a variable amount of time until the integrator output returns to zero. The unknown input voltage is determined by the product of the known input voltage times the ratio of two times. However, the dual-slope integrating ADC  700  illustrated in  FIG. 7A  is being used in a novel atypical manner. For the dual-slope integrating ADC of  FIG. 7A , both input voltages may be unknown, and the output is the digital value of the voltage ratio, which is a measure of efficiency. 
       FIG. 7B  illustrates example timing for the circuit of  FIG. 7A . In  FIG. 7A , a switch  702  connects one of two input voltages to an integrating operational amplifier  704 . In  FIGS. 7A and 7B , the two input voltages V OUT  and D*V IN  are assumed to be of opposite polarity. Assume that during time t 1 , switch  702  connects integrating amplifier  704  to V OUT , and assume that V OUT  is negative. The integrator is inverting, so the output V O  of the integrator increases linearly. Assume that during time t 2 , switch  702  connects integrating amplifier  704  to D*V IN , and assume that D*V IN  is positive. The output V O  of the inverting integrator decreases linearly. Time t 1  is a fixed predetermined amount of time. Time t 2  is variable, and ends when a comparator (not illustrated) determines that V O  has returned to zero. A counter (not illustrated) counts clock cycles during the time periods t 1  and t 2 . 
     The output voltage V O  during time t 1  is: 
     
       
         
           
             
               V 
               O 
             
             = 
             
               
                 - 
                 
                   
                     V 
                     OUT 
                   
                   RC 
                 
               
               ⁢ 
               t 
             
           
         
       
     
     The output voltage V O  during time t 2  is: 
     
       
         
           
             
               V 
               O 
             
             = 
             
               
                 - 
                 
                   
                     D 
                     * 
                     
                       V 
                       IN 
                     
                   
                   RC 
                 
               
               ⁢ 
               t 
             
           
         
       
     
     Output voltage Vo changes by the same magnitude over time periods t 1  and t 2 . Accordingly: 
     
       
         
           
             
               
                 
                   V 
                   OUT 
                 
                 RC 
               
               ⁢ 
               t 
               ⁢ 
               
                   
               
               ⁢ 
               1 
             
             = 
             
               
                 
                   D 
                   * 
                   
                     V 
                     IN 
                   
                 
                 RC 
               
               ⁢ 
               t 
               ⁢ 
               
                   
               
               ⁢ 
               2 
             
           
         
       
       
         
           
             
               
                 V 
                 OUT 
               
               
                 D 
                 * 
                 
                   V 
                   IN 
                 
               
             
             = 
             
               
                 t 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 2 
               
               
                 t 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 1 
               
             
           
         
       
     
     The digital efficiency E is the count of clock cycles during time period t 2 . Time period t 1  is predetermined and known, so it can be set to a convenient number of clock cycles. For example, if t 1  is 100 clock cycles, then the number of clock cycles during time period t 2  directly expresses the efficiency without scaling. If t 1  is, for example, 1,000 clock cycles, then the number of clock cycles during time period t 2  must be scaled down by a factor of 10, and so forth. 
     In  FIG. 5 , the input voltages to the ADC  500  are modified by signal conditioning circuitry  502  and  504 . As discussed above, for the example of  FIG. 7A , the input voltages need to be of opposite polarity, so one of V OUT  or D*V IN  needs to be amplified by a gain of minus one. In addition, D*V IN  is a pulse-width-modulated signal. Accordingly, for the examples of  FIGS. 6 and 7A , it may be preferable to pass D*V IN  through a low-pass filter before going to the ADC. In addition, D*V IN  and V OUT  may equal or exceed the power supply voltage of the ADC. Accordingly, D*V IN  and V OUT  may need to be attenuated before conversion. If, for example, the ADC is powered by the output voltage of the DC-DC converter (V OUT ), then both V 2  and V OUT  need to be attenuated by equal amounts before conversion. For example, the inputs may be attenuated by a factor of 2, and if both are attenuated equally the ratio will not be affected. 
       FIG. 7C  illustrates an example embodiment of additional detail for an efficiency circuit  306  in  FIG. 3 , using the dual-slope ADC  700  of  FIG. 7A , and the example signal modifications discussed above. In  FIG. 7C , as an example of signal modification  504  in  FIG. 5 , V OUT  is amplified by a gain of minus one by an inverting amplifier  702 . In  FIG. 7C , as an example of signal modification  502  in  FIG. 5 , D*V IN  is filtered by a low-pass filter  704 . A simple single-stage R-C filter is illustrated, but multiple-stage or other low-pass filter configurations may be used. D*V IN  and V OUT  may also need to be attenuated (not illustrated). A counter  706  counts clock cycles from a clock  708  during time periods t 1  and t 2  ( FIG. 7B ), and the digital efficiency signal E ( FIG. 3 ,  308 ) is the number of clock cycles during time period t 2 . 
     The example embodiment of  FIG. 7A  assumes that the integrating operational amplifier  704  is powered by both positive and negative voltages, and accordingly one of the input voltages is amplified by a gain of minus one. In a DC-DC converter, the integrating operational amplifier ( FIG. 7A ,  704 ) may need to be powered by a single voltage, for example, the output of the DC-DC converter (V OUT ).  FIG. 7D  illustrates an example alternative embodiment for a dual-slope integrating ADC  710  for the case in which the integrating operational amplifier is powered by a single voltage. The example of  FIG. 7D  is a switched-capacitor dual-slope integrating ADC. For the example of  FIG. 7D , there is a two-phased clock signal (Ø 1 , Ø 2 ) and an UP/DOWN control signal. Capacitor C 1  is a switched capacitor, which may be much smaller than the integration capacitor C 2 . Initially, the UP/DOWN signal is set to UP. During the UP period, during clock phase Ø 1 , switches SW 1  and SW 3  connect one side of capacitor C 1  to V OUT  and switches SW 5  and SW 6  connect the other side of C 1  to ground. Capacitor C 1  then charges to V OUT . Then, during clock phase Ø 2 , switch SW 4  switches one side of C 1  to ground and switches SW 11  and SW 12  connect the other side of C 1  to C 2  and the operational amplifier  712 . The side of C 1  connected to C 2  is then −V OUT . During clock phase Ø 2 , the charge on C 1  is transferred to C 2  as the operational amplifier drives its input to ground, and V O  increases by an incremental amount proportional to V OUT . This is repeated for known fixed number of clock cycles, for example, 128 cycles for a 6-bit digital output. After the known fixed number of clock cycles the UP/DOWN signal is changed to DOWN. During the DOWN period, during clock phase Ø 1 , switches SW 2  and SW 3  connect one side of capacitor C 1  to D*V IN  and switches SW 9  and SW 10  connect the other side of capacitor C 1  to C 2  and the input of the operational amplifier  712 . During clock phase Ø 1 , an amount of charge is transferred from C 2  to C 1  as the operational amplifier drives its input to ground and C 2  is charged to D*V IN , and V O  decreases by an incremental amount proportional to D*V IN . During clock phase Ø 2 , both sides of capacitor C 1  are grounded (switches SW 4 , SW 7 , SW 8 ) so C 1  is discharged. This is repeated for an unknown variable number of clock cycles until V O  is zero. The number of clock cycles required to return V O  to zero is the digital output. Switch SW 13  and signal RESET provide a reset function. The example of  FIG. 7D  eliminates the need for an inverting input signal amplifier as in amplifier  702  in  FIG. 7C . Again, V OUT  and D*V IN  may need to be attenuated (not illustrated) and/or low-pass filtered (not illustrated) and/or buffered (not illustrated). 
     In the examples of  FIGS. 3 ,  5 , and  7 C, the efficiency signal E ( 308 ) is a digital value. This value may be, for example, communicated over a bus to a test system or to a system controller. Alternatively, an analog efficiency signal may be provided, for example, as a voltage. In  FIG. 8 , the digital efficiency signal E ( 308 ) (from, for example  FIG. 3 ,  5 , or  7 C) is converted by a digital-to-analog converter  800  to an analog voltage efficiency signal E A  ( 310 ). 
       FIG. 9  illustrates a method  900  for generating a measure of efficiency by a DC-DC converter. At step  902 , the DC-DC converter determines a measure of efficiency of the DC-DC converter. At step  904 , the DC-DC converter outputs the measure of efficiency. 
     While certain embodiments of a DC-DC converter have been described in detail herein, it will be obvious to those skilled in the art, after reading this disclosure, that a DC-DC converter may be variously otherwise embodied within the scope of the claims. The appended claims are to be construed to cover such alternative embodiments, except to the extent limited by the prior art.