Abstract:
A method for fabricating capacitor is disclosed. The method includes the steps of: providing a material layer; forming a first conductive layer, a first dielectric layer, and a second conductive layer on the material layer; patterning the first dielectric layer and the second conductive layer to form a patterned first dielectric layer and a middle electrode; forming a second dielectric layer on the first conductive layer and the middle electrode; removing part of the second dielectric layer to form a patterned second dielectric layer; forming a third conductive layer on the first conductive layer and the patterned second dielectric layer, wherein the third conductive layer contacts the first conductive layer directly; and removing part of the third conductive layer to expose part of the patterned second dielectric layer.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The invention relates to capacitor and fabrication method thereof, and more particularly, to a metal-insulator-metal (MIM) capacitor and fabrication method thereof. 
         [0003]    2. Description of the Prior Art 
         [0004]    In semiconductor manufacturing processes, metal capacitors formed of metal-insulator-metal (MIM) are widely used in the design of ultra large scale integrations (ULSI). Because a MIM capacitor has low resistance and low parasitic capacitance, and has no problems in shifts of depletion induced voltage, MIM capacitors have become the main structure used for metal capacitors. It is therefore important to develop a MIM capacitor that comprises copper electrodes with low resistance. 
         [0005]    With the increasing complexity of integrated circuits, the multilevel interconnect process has become the typical method used in semiconductor integrated circuit fabrication. To satisfy the requirements for high integration and high speed in integrated circuits (ICs), especially in a deep sub-micro (&lt;0.18 μm) semiconductor process, a copper (Cu) dual damascene process is becoming more widely used as a standard process in forming an interconnection line within the inter-metal dielectric layer of low dielectric constant (low k) materials. Since copper has both a low resistance and a low electro-migration resistance, the low k materials are useful in improving the RC delay effect of a metal interconnection. Consequently, how to integrate copper fabrication processes to fabricate MIM capacitors and internal metal wires with low resistance has become a key research topic in this field. 
       SUMMARY OF THE INVENTION 
       [0006]    According to a preferred embodiment of the present invention, a method for fabricating capacitor is disclosed. The method includes the steps of: providing a material layer; forming a first conductive layer, a first dielectric layer, and a second conductive layer on the material layer; patterning the first dielectric layer and the second conductive layer to form a patterned first dielectric layer and a middle electrode; forming a second dielectric layer on the first conductive layer and the middle electrode; removing part of the second dielectric layer to form a patterned second dielectric layer; forming a third conductive layer on the first conductive layer and the patterned second dielectric layer, wherein the third conductive layer contacts the first conductive layer directly; and removing part of the third conductive layer to expose part of the patterned second dielectric layer. 
         [0007]    According to another aspect of the present invention, a capacitor is disclosed. The capacitor includes: a bottom electrode; a middle electrode on the bottom electrode; a patterned first dielectric layer between the bottom electrode and the middle electrode; a top electrode on the bottom electrode and the middle electrode, wherein the top electrode contacts the bottom electrode directly; and a patterned second dielectric layer between the middle electrode and the top electrode. 
         [0008]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  illustrates a 3D structural view of a capacitor device according to a preferred embodiment of the present invention. 
           [0010]      FIG. 2  illustrates cross-sectional views of  FIG. 1   
           [0011]      FIGS. 3-5  illustrate top views of a capacitor according to other embodiments of the present invention. 
           [0012]      FIGS. 6-10  illustrate a method for fabricating the capacitor shown in  FIG. 1  according to a preferred embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0013]    Referring to  FIGS. 1-2 ,  FIG. 1  illustrates a 3D structural view of a capacitor device according to a preferred embodiment of the present invention, the right portion of  FIG. 2  illustrates a cross-sectional view of  FIG. 1  along the sectional line AA′, the middle portion of  FIG. 2  illustrates a cross-sectional view of  FIG. 1  along the sectional line BB′, and the left portion of  FIG. 2  illustrates a cross-sectional view of  FIG. 1  along the sectional line CC′. For simplicity reason, it is to be noted that contact plugs and material layer surrounding the contact plugs are only revealed in  FIG. 2  and omitted in  FIG. 1 . As shown in  FIG. 1 , the capacitor of the present invention preferably includes a bottom electrode  12 , two middle electrodes  14  disposed on the bottom electrode  12 , a first capacitor dielectric layer  16  disposed between the bottom electrode  12  and the middle electrodes  14 , a top electrode  18  disposed on the bottom electrode  12  and middle electrodes  14 , and a second capacitor dielectric layer  20  disposed between the middle electrodes  14  and the top electrode  18 . 
         [0014]    It should be noted that even though the middle electrodes  14  disclosed in this embodiment do not contact each other and only two middle electrodes  14  are disclosed in this embodiment, the shape an quantity of the middle electrodes  14  are not limited to the ones disclosed in this embodiment, but could be adjusted according to the demand of the product. For instance, each of the middle electrodes  14  could be physically connected to each other, and the connected portion could be exposed or covered by the second capacitor dielectric layer  20  and top electrode  18 . In addition, the top electrode  18  is preferably disposed on the middle electrodes  14  while contacting part of the bottom electrode  12  at the same time, the top electrode  18  only covers part of the middle electrodes  14 , or at least one edge of the top electrode  18  is aligned to an edge of the bottom. electrode  12 . As shown in  FIG. 1 , the top electrode  18  is in physical contact with the bottom electrode  12  and three edges of the top electrode  18  are aligned with three edges of the bottom electrode  12  at the same time. 
         [0015]    In this embodiment, the bottom electrode  12  could be disposed on a material layer  22  and another material layer  24  could be disposed on the top electrode  18 , in which the material layer  22  and  24  could be composed of same insulating material or different insulating material. According to an embodiment of the present invention, the material layer  22  could be a semiconductor substrate or an interlayer dielectric (ILD) layer or inter-metal dielectric (IMD) layer on the semiconductor substrate, and the material layer  24  is preferably an IMD layer, but not limited thereto. A plurality of contact plugs could be formed in the material layer  22  and  24 , in which the contact plugs  26  disposed in the material layer  24  are electrically connected and physically contacting the top electrode  18 , the contact plugs  28  disposed in the material layer  24  are electrically connected and physically contacting the middle electrodes  14 , and the contact plugs  30  disposed in the material layer  22  are electrically connected and physically contacting the bottom electrode  12 . It should be noted that the quantity of the contact plugs  30  is not limited to the embodiment shown in  FIG. 2 . For instance, it would also be desirable to form only one single contact plug  30  in the material layer  22  to electrically and physically connected to the bottom electrode  12 , which is also within the scope of the present invention. 
         [0016]    Referring to  FIGS. 3-5 ,  FIGS. 3-5  illustrate top views of a capacitor according to other embodiments of the present invention. As shown in  FIG. 3 , the middle electrode  14  is preferably composed of a connecting portion and multiple finger-shaped branches, the top electrode  18  is disposed on the branches of the middle electrode  14  but not on the connecting portion, and the second capacitor dielectric layer  20  is disposed on the connecting portion of the middle electrode  14 . In contrast to  FIG. 3 , the top electrode  18  shown in  FIG. 4  is preferably covering the connecting portion and part of the branches of the middle electrode  14 , and the second capacitor dielectric layer  20  only covers part of the branches of the middle electrode  14 . In the embodiment shown in  FIG. 5 , the middle electrode  14  is preferably S-shaped, the top electrode  18  is disposed on the central portion of the middle electrode  14 , and two ends of the middle electrode  14  are disposed on both left and right sides of the top electrode  18 . 
         [0017]    Referring to  FIGS. 6-10 ,  FIGS. 6-10  illustrate a method for fabricating the capacitor shown in  FIG. 1  according to a preferred embodiment of the present invention. As shown in  FIG. 6 , a material layer  22 , such as a semiconductor substrate composed of silicon or a dielectric layer disposed on the semiconductor substrate is provided, and devices such as metal-oxide semiconductor (MOS) transistors, oxide-semiconductor field-effect-transistors (OS FETs), CMOS transistors, FinFETs, or other active devices could be disposed on the semiconductor substrate. The dielectric layer could be a ILD layer or a IMD layer covering active devices, in which metal interconnections could be formed within the dielectric layer to electrically connect to the active devices on the semiconductor substrate. 
         [0018]    Next, a first conductive layer  32 , a first dielectric layer  34 , and a second conductive layer  36  are sequentially formed on the material layer  22 , in which the first conductive layer  32  is preferably used to form the aforementioned bottom electrode  12  and the second conductive layer  36  is used to form the aforementioned middle electrodes  14 . In this embodiment, the first conductive layer  32  and second conductive layer  36  could be composed of same material or different material, in which the conductive layers  32  and  36  could be selected from the group consisting of W, Ti, TiN, Ta, TaN, and Al. The first dielectric layer  34  is preferably composed of dielectric material having low current leakage characteristics. For instance, the first dielectric layer  34  could be selected from the group consisting of oxide-nitride-oxide (ONO), silicon nitride, silicon oxide, and silicon oxynitride. 
         [0019]    According to an embodiment of the present invention, the first dielectric layer  34  could also include a high-k dielectric layer having dielectric constant (k value) larger than  4 . For instance, the high-k dielectric layer may be selected from hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (A 1   2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), strontium titanate oxide (SrTiO 3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuth tantalate (SrBi 2 Ta 2 O 9 , SBT), lead zirconate titanate (PbZr x Ti 1−x O 3 , PZT), barium strontium titanate (Ba x Sr 1−x TiO 3 , BST) or a combination thereof. 
         [0020]    Next, as shown in  FIG. 7 , the second conductive layer  36  and first dielectric layer  34  are patterned to form a patterned second conductive layer and a patterned first dielectric layer, in which the patterned second conductive layer preferably being the middle electrodes  14  shown in  FIG. 1  while the patterned first dielectric layer being the capacitor dielectric layer  16  shown in  FIG. 1 . In this embodiment, the patterning of the second conductive layer  36  and first dielectric layer  34  could be accomplished by a photo-etching process. For instance, a patterned mask (not shown) could be formed on the second conductive layer  36 , and an etching process is conducted to remove part of the second conductive layer  36  and part of first dielectric layer  34  not covered by the patterned mask to form strip-shaped middle electrodes  14  on the first conductive layer  32  and first capacitor dielectric layer  16  between the first conductive layer  32  and middle electrodes  14 . 
         [0021]    Next, as shown in  FIG. 8 , a second dielectric layer  38  is formed on the first conductive layer  32  and middle electrodes  14  and contact the first capacitor dielectric layer  16 . In this embodiment, the second dielectric layer  38  and the first dielectric layer  34  could be composed of same material or different material. For instance, the second dielectric layer  38  could be composed of aforementioned dielectric material having low current leakage or high-k dielectric layer having high dielectric constant. It should be noted that since the second dielectric layer  38  covers the first conductive layer  32  and middle electrodes  14  at the same time, the second dielectric layer  38  preferably covers the top surface, front and back sidewalls, and left and right sidewalls of the middle electrodes  14  and all the top surface of first conductive layer  32  outside the middle electrodes  14 . 
         [0022]    Next, as shown in  FIG. 9 , an etching process is conducted to remove part of the second dielectric layer  38  to form a patterned second dielectric layer or the second capacitor dielectric layer  20  and expose part of the top surface of first conductive layer  32  at the same time. A third conductive layer  40  is then formed on the first conductive layer  32  and second capacitor dielectric layer  20 , in which the third conductive layer  40  is preferably used to form the top electrode  18  shown in  FIG. 1 . It should be noted that since part of the top surface of first conductive layer  32  is exposed during the patterning of second dielectric layer  38 , the deposited third conductive layer  40  preferably contacts the exposed top surface of the first conductive layer  32 . 
         [0023]    In this embodiment, the material of the third conductive layer  40  could be the same as or different the second conductive layer  36  and/or first conductive layer  32 . For instance, the third conductive layer  40  could be selected from the group consisting of W, Ti, TiN, Ta, TaN, and Al, but not limited thereto. 
         [0024]    Next, as shown in  FIG. 10 , a photo-etching process is conducted to remove part of the third conductive layer  40  and expose part of the second capacitor dielectric layer  20 , or more specifically, as shown in  FIG. 1 , part of the second capacitor dielectric layer  20  and part of middle electrodes  14  that were embedded within the third conductive layer  40  are exposed after the photo-etching process. 
         [0025]    Next, the third conductive layer  40  and first conductive layer  32  are patterned by conducting another photo-etching process to remove part of the third conductive layer  40  and part of the first conductive layer  32  for defining the size of the capacitor. This forms the top electrode  18  and bottom electrode  12  shown in  FIG. 1  and completes the fabrication of a capacitor according to a preferred embodiment of the present invention. 
         [0026]    Next, as shown in  FIG. 2 , another material layer  24  is formed on the material layer  22  and covering the entire capacitor, in which the material layer  24  could be a IMD layer or dielectric layer composed of any other dielectric material. Next, contact plugs  26  and  28  are formed in the material layer  24  to electrically connect and physically contact the top electrode  18  and middle electrodes  14 . The bottom electrode  12  is electrically connected to the contact plugs  30  that were already formed in the material layer  22 . It should be noted since the top electrode  18  and bottom electrode  12  were already contacting each other, it would be desirable to form only the contact plug connected to the top electrode  18  or only the contact plug connected to the bottom electrode  12  in addition to the contact plug  20  connected to the middle electrodes. 
         [0027]    Overall, the present invention first forms a first conductive layer, a first dielectric layer, and a second conductive layer on a material layer, patterns the first dielectric layer and second conductive layer to forma first capacitor dielectric layer and middle electrode, forms a second capacitor dielectric layer on the middle electrode, forms a third conductive layer on the first conductive layer and middle electrode so that the third conductive layer contacts the first conductive layer directly, and finally patterns the third conductive layer and first conductive layer to form a  3 -dimensional capacitor having high density. Preferably, the 3D capacitor of the present invention not only possesses much greater capacitor density compare to conventional capacitor, but could also be integrated to random access memory (RAM) devices with oxide semiconductor FETs to achieve much smaller volume and lower current leakage. 
         [0028]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.