Abstract:
A new logic circuit construction in which gates are formed by appropriate interconnections of complementary current-mirror cells. With a signal applied, the resulting logic circuit draws a current drain which rises with power supply voltage, as does the speed of the circuit. With no signal the current drain of the circuit is small. Clocked circuits using this logic can use one clock line. With three states available in the clock line, a non-overlapping two-phase clock is automatically obtained with a simple oscillating signal. This logic circuit is also capable of providing a weighted input or output, enabling threshold logic (&#34;multiple-valued logic&#34;) to be performed.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates generally to the design of digital logic circuits and in particular it provides the basis for a new family of logic circuits which operate upon current signals rather than voltage signals. Logic circuits according to the invention may be designed to perform binary and higher order multiple-valued logic functions. 
     Binary logic circuits are the basis of present-day digital computing. There are many competing families of such circuits. Most use voltage levels (as distinct from current levels) at the input and output to describe the operation of the circuit. Such families include ECL (Emitter - Coupled Logic), TTL (Transistor - Transistor Logic), I 2  L (Integrated - Injection Logic), NMOS (N-channel MOS) and CMOS (complementary MOS). These families have been listed in a rough order of power consumption and speed, with ECL consuming most power but also operating at the highest speed. 
     References to prior art logic families are available in S. M. Sze (ed.), &#34;VLS1 Technology&#34;, New York: McGraw-Hill, 1983 and W. P. M. Solomon, &#34;A Comparison of Semiconductor Devices for High-Speed Logic&#34;, Proc. IEEE, Volume 70, 1982, pages 489-509. References to both prior art logic families and to multi-valued logic and its implementation may be found in Stanley L. Hurst, &#34;Multiple-Valued Logic--Its Status and Its Future&#34;, IEEE Transactions on Computers, Vol. C-33, No. 12, December 1984, pages 1160 to 1179. 
     SUMMARY OF THE INVENTION 
     The present invention consists in an electronic digital logic circuit comprising at least one positive current source, at least one negative current source and an output, each positive current source producing a positive current and each negative current source producing a negative current and the respective positive and negative currents being summed algebraically to produce an output current at the output of the logic circuit. 
     The present invention provides the basis for a family of logic circuits which can act as a replacement for all of the prior art logic families referred to above. When operated at high voltage logic devices using the present invention behave like ECL, and when operated at low voltage these devices behave somewhat like the CMOS Logic family. When implemented using bipolar junction transistor technology, logic in accordance with the present invention utilises current levels rather than voltage levels to describe the state of the logic elements. This is similar to another high-speed logic family, CML (Current Mode Logic), a variant of ECL. Unlike CML, however, in logic families according to the present invention, which are hereinafter referred to as Complementary Current Mirror Logic (CCML), the input and output currents can have variable weights. Combined with analog summation of currents at the input node of a gate, this new logic circuit permits simplification of gate designs. It may even allow correlation between digital words to be performed in a simpler fashion than is possible with prior art binary gate logic. 
     The logic circuit of the invention has some similarities with many types of digital logic circuits. It is similar to &#34;Folded Collector Integrated Injection Logic&#34; (e.g. M. I. Elmasry, IEEE Journal of Solid-State Circuits, Volume SC-11, No. 5, October 1976, pages 644-647), with two changes: firstly the integrated injector, although possibly useful, is not a necessary component of the new logic: Secondly, a complementary image of the basic inverter cell is used as a load in the present invention, replacing the integrated injector to the following stage. (&#34;In this context, Complementary&#34; is used to signify that PNP devices replace NPN devices, and vice-versa). 
     The logic according to the invention is also similar to circuits described in &#34;A New Complementary Bipolar Transistor Structure&#34; (S. C. Su and J. D. Meindl, IEEE Journal of Solid-State Circuits, Volume SC-7, No. 5, October 1972, pages 351-357) and in &#34;Bipolar Complementary Logic (CTL)&#34; (S. K. Wiedmann and H. H. Berger, in Proceedings of the First European Solid-State Circuits Conference, Canterbury, U.K. September 1975, pages 36-39, referred to by P. M. Solomon, &#34;A Comparison of Semiconductor Devices for High-Speed Logic&#34;, Proceedings of the IEEE, Volume 70, No. 5, May 1982, pages 489-509, page 505). The similarity lies in the use of complementary bipolar transistors to perform logic functions: The dissimilarity rests in the &#34;Folded Collector&#34; (terminology of Elmasry, above) or &#34;Current Mirror&#34; configuration of the complementary elements. Without the current mirror element of the present invention the complementary bipolar stage becomes excessively dependent on power supply voltage due to uncontrolled collector current levels. 
     The most familiar description of the present invention would be in terms of the current mirrors used by analog amplifier designers: here we are employing complementary current mirror elements in configurations designed to provide logic inputs and outputs. 
     We will see that logical operations can be performed using weighted summations of both positive and negative signals feeding into one input node; This capability is unavailable in any of the logic forms reviewed by Hurst (&#34;Multiple-Valued Logic . . . ,&#34; above), with a single exception. The &#34;Two collector transistor for binary full-addition&#34; (R. F. Rutz, IBM Journal of research and Development, Volume 1, pages 212 to 223 1957) is capable of processing a weighted summation of input signals of any polarity. However that device requires external resistors and buffering devices, and does not resemble the Complementary Current Mirror Logic (CCML) of the present invention in form or function. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates the various components which are used as the basis of a logic circuit in accordance with an embodiment of the present invention, together with their schematic representation. FIG. 1(a) illustrates a pull up cell, FIG. 1(b) illustrates a schematic symbol for the pull up cell of FIG. 1(a), FIG. 1(c) illustrates a pull-down cell, FIG. 1(d) illustrates a schematic symbol for the pull-down cell of FIG. 1(c), FIG. 1(e) illustrates a positive current source, FIG. 1(f) illustrates a negative current source (current sink), FIG. 1(g) illustrates a schematic symbol for a resistor, and FIG. 1(h) illustrates another way to implement current scaling by replacing Q2 or Q4 of FIGS. 1(a) and 1(c) with two output transistors connected in parallel; 
     FIG. 2 schematically illustrates three inverter configurations in accordance with the invention, 
     FIG. 2(a) illustrating a normalized inverter, FIG. 2(b) illustrating an un-normalized inverter, and FIG. 2(c) illustrating an inverter with a current gain of two inverters; 
     FIG. 3 graphically illustrates the power/delay curve for devices according to the invention, and compares this to power/delay characteristics of prior art logic families; 
     FIG. 4 illustrates (a) a pull-up cell including a Schottky diode, (b) the schematic symbol for the cell of FIG. 4(a), (c) a pull-down cell including a Schottky diode, and (d) the schematic symbol for the cell of FIG. 4(c); 
     FIGS. 5(a) &amp; (b) illustrate alternative bipolar circuits for implementing the pull-down cell of FIG. 1(a), FIG. 5(c) illustrates an alternative MOS field-effect transistor (MOSFET) circuit for implementing the pull down cell of FIG. 1(a), 
     FIG. 6 schematically illustrates a full adder implemented in accordance with the present invention; 
     FIG. 7(a) schematically illustrates a shift register implemented in accordance with the present invention, and FIG. 7(b) and (c) schematically illustrate two possible output buffers for the circuit of FIG. 7(a); and 
     FIG. 8 graphically illustrates a clock waveform used with the shift register circuit of FIG. 7(a), as a function of time. 
    
    
     DETAILED DESCRIPTION 
     The elements making up an embodiment of the present invention are shown in FIG. 1. In FIG. 1(a), Q 2  performs as a pull-up transistor, controlled by the diode-connected transistor Q 1 . An input current I in  into Q 1  is reflected into an output current I out  in the output transistor Q 2  having the same magnitude and polarity. This is the well-known &#34;current mirror&#34; action used extensively in analogue integrated circuits and even in multiple-valued digital integrated circuits based on the I 2  L logic family (see K. Hart, A. Slob, &#34;Integrated injection logic--A new approach to LSI,&#34; IEEE Journal of Solid State Circuits, vol. SC-7, October 1972, pages 346-351; and T. T. Dao, &#34;Threshold I 2  L and its application in binary symmetric functions and multi-valued logic&#34;, IEEE Journal of Solid State Circuits, Vol SC-12, October 1977, pages 463-475). There are however two differences between the above I 2  L circuits and the logic of the present invention; firstly I 2  L requires that every gate input have an &#34;Integrated Injection&#34; of current, and secondly the logic of the present invention utilises two polarities of basic cell, the first cell which is illustrated in FIG. 1(a) employing Q 1  and Q 2  to perform an inverting pull-up function, and the second cell which is illustrated in FIG. 1(c) employing Q 3  and Q 4  to perform an inverting pull-down function. No commonly used bipolar logic uses this complementary cell design. CMOS is in some respects similar, with its use of complementary N-and P-channel field effect transistors. The schematic symbols for the basic elements of FIG. 1(a) &amp; (c) are illustrated in FIGS. 1(b) &amp; (d) respectively. 
     One final circuit element is needed: a current source or a resistor, either of which serve to set the circuit current level. These are illustrated schematically in FIG. 1(e), (f) and (g). 
     If the elements of FIG. 1 are combined to make an inverter capable of pull-up and pull-down functions, two possibilities arise: firstly the &#34;normalized inverter&#34; of FIG. 2(a) with a resistor at its input. This inverter will accept any input drive capable of either sinking the input to the negative power line (-V) or sourcing to the positive power line (+V). The resultant input current is then determined by the resistor, the power supply voltage, and the voltage drop at the gate input (which is typically 0.6 V for silicon devices). The output current available from the inverter, if all transistors are matched in size, is roughly equal to this input current. 
     The &#34;normalized&#34; inverter stage of FIG. 2(a) is capable of driving other logic elements. For example the &#34;inverter&#34; shown in FIG. 2(b) may be driven by the &#34;normalized inverter&#34; and the output currents available will be equal to the input currents provided that the transistor current gains are high and that all transistors are well matched. 
     If transistor area ratios are scaled such that the emitter area of Q2 (in FIG. 1(a)) is double that of Q1, and that of Q4 in FIG. 1(c) is double that of Q3, then an &#34;inverter with current gain&#34; is possible. Another way of implementing this scaling is to replace output transistor Q 2  or Q 4  of FIGS. 1(a) and (c) with two output transistors connected in parallel as shown in FIG. 1(h). In each case, a current gain of approximately two is available, and an example this situation is shown schematically in the FIG. 2(c). 
     Chains of logic elements with known gains can be interconnected to perform logic operations, and provided that all devices are well matched in characteristics, very few &#34;renormalizations&#34; of current need be performed. However, as a practical matter such good matching is only available over small chip areas, and good design practice renormalizes currents frequently, especially where multiple - valued logic elements are used. 
     FIG. 3 shows experimental results obtained by connecting discrete NPN and PNP devices in a &#34;CCML&#34; logic configuration according to the present invention. 
     The measured values used to derive the &#34;CCML&#34; curve of FIG. 3 are listed in Table 1. 
     
                       TABLE 1______________________________________POWER/DELAY CHARACTERISTICS FOR CCML LOGICPOWER (mW)     DELAY (ns)______________________________________0.279          81.30.355          56.30.525          37.50.695          31.31.133          17.51.57           10.05.8            1.8818.9           1.25______________________________________ 
    
     The transistors in the circuit used to derive the CCML characteristic of FIG. 3 were: 
     PNP: 2N5771 
     NPN: 2N5772 
     and the power supply voltage range (V +  -V - ) used for these measurements was from 0.795 volts (Low Speed &amp; Low Power) to 1.505 volts (High Speed &amp; High Power). However, full current will only flow when an input current is applied. 
     In comparison to the values given in Table 1, the Power and Delay characteristics for various prior art logic families are given in Table 2. 
     
                       TABLE 2______________________________________POWER/DELAY CHARACTERISTICSFOR PRIOR ART LOGIC FAMILIESLOGIC FAMILY   POWER (mW)  DELAY (ns)______________________________________10K ECL        50          2STTL           20          4LSTTL           4          10FAST            4          3______________________________________ 
    
     It will be seen that the CCML inverter delay and power drain are lower than the prior art integrated circuit logic families shown, and that both very low power drain (at low power supply voltage) and very high speed (at high power supply voltage) are possible. This high speed performance is derived from the non-saturating operation of the current mirror elements; bipolar transistors are fastest when held out of saturation. 
     A second embodiment of this invention is shown in FIG. 4. The cells shown here differ from those shown in FIG. 1 by the inclusion of Schottky clamp diodes D1 and D2. This type of diode is used in logic families such as &#34;Schottky Transistor-Transistor Logic&#34; (STTL) to prevent a transistor collector-emitter voltage from falling much below its base-emitter voltage; by preventing transistor saturation the speed of the logic is increased. In the present &#34;CCML&#34; logic family, such clamping is only necessary when Q 12  or Q 14  (in FIGS. 4(a) &amp; (c)) are required to drive a normalizing input containing a resistor or other current-limiting device. Otherwise the Schottky device is strictly not necessary. 
     Other embodiments of the invention may make use of different current mirror designs and FIGS. 5(a), (b) and (c) illustrate some possible current mirror designs. FIGS. 5(a) and (b) illustrate some popular current mirror configurations using NPN transistors. These are capable of providing logic functions similar to the preceding designs, when combined with complementary (PNP) transistor current mirrors. FIG. 5(a) illustrates a bipolar current mirror circuit which is less dependent upon transistor gain than the circuit of FIG. 1(a) while FIG. 5(b) illustrates a circuit which is less output voltage dependent than that of FIG. 1(a). FIG. 5 (c) illustrates one possible current mirror circuit using N-Channel enhancement MOS field effect transistors (MOSFETs). When combined with p-channel current mirror cells this arrangement is also suitable for use in embodiments of &#34;CCML&#34; logic in accordance with the invention. The resistor shown in FIG. 5(c) provides a current return path for the input signal. Bipolar embodiments are preferred in CCML Logic however, since they require lower operating voltages, and have lower signal swing voltages. 
     A full adder implementation using the principles of the present invention is illustrated in FIG. 6. The circuit works on summation of current: These currents can add or subtract to yield a net upward or downward signal swing at the output. 
     The adder of FIG. 6 has normalized sum and carry output buffers 10 and 11 and the transfer function of the adder is given in the Truth Table in Table 3. It will be noted that inputs A, B and C are interchangeable. 
     
                       TABLE 3______________________________________TRUTH TABLE FOR FULL ADDERINPUTS            OUTPUTSA        B     C          SUM   CARRY______________________________________0        0     0          0     01        0     0          1     01        1     0          0     11        1     1          1     1______________________________________ 
    
     An embodiment of a shift register is illustrated in FIG. 7(a), wherein stage 2 can be regarded as the &#34;slave&#34; element for a &#34;Master&#34; Stage 1 latch. It will be noted that storage is fully static and that the clock line in this implementation provides two-phase non-overlapping functions on one wire. A graphical representation of the clock signal with time is given in FIG. 8. Other configurations are of course possible. This simple implementation has the disadvantage of requiring a relatively high voltage and current drive on the clock line. Two possible methods of obtaining output voltages from the shift register cells are illustrated in FIGS. 7 (b) and (c). 
     It will be recognised by persons skilled in the art that other known logic forms (such as a programmable logic array) can also be readily devised using this CCML logic system.