Abstract:
In the disclosed coded telephone ringing signal method and circuitry, audibly distinguishable ringing codes are generated by alternately shifting between at least a pair of single frequency tones at different modulation rates. Other distinguishable ringing codes are generated by changing both the modulation rates and tone frequencies utilized.

Description:
TECHNICAL FIELD 
     This invention relates to ring signaling and more particularly, to a method and circuitry for encoding telephone ringing signals. 
     BACKGROUND OF THE INVENTION 
     Telephone users often find it desirable to have information about the origin and/or destination of a received call prior to the call being answered. Some telephone communication systems now provide users with call origin information using a distinctive ringing signal which identifies whether the received call is an external (central office), an internal (intercom), or a priority call. 
     In other telephone communication systems, users are provided with call destination information using a personalized ringing signal. Personalized ringing enables each user to determine whether he or she is the intended recipient of an incoming call by listening to and decoding the ring signal. These distinctive and/or personalized ringing features are provided in communication systems using a coded ringing signal. 
     In one prior coded ringing circuit, each ringing code is comprised of a different pair of single frequency tones which are alternately enabled at a predetermined modulation rate during the ringing cycle. In such a circuit, however, the ability of the listener to discriminate between different frequency pairs limits the number of frequency pairs that can be utilized. Undesirably, this results in a small number of distinguishable ringing codes. 
     SUMMARY OF THE INVENTION 
     A method and circuitry are disclosed for providing coded ringing signals for a communication system. According to the present invention, during the existence of a received ringing signal different ringing codes are locally generated for the user from at least one pair of single frequency tones by utilizing different modulation rates to alternately enable the two tones. Each modulation rate is selected to assure easy listener discrimination from the other modulation rates utilized. 
     Additional ringing codes are generated by changing both the modulation rate and the tone frequencies utilized. The result is that the perceived distinction between two codes using different frequency pairs is enhanced by utilizing a different modulation rate for each frequency pair. That is, the combination of two auditory dimensions, frequency and modulation rate, yields an inter-ring discriminability that is greater than the discriminability produced by frequency or modulation rate differences alone. Thus, for example, a ringing code using frequency pair FA at modulation rate MA is auditorally distinguishable from a ringing code using frequency pair FB at modulation rate MB even though neither the frequency pairs nor the modulation rates are themselves distinguishable. Similarly, while listeners may not be able to distinguish two ringing codes which use the same frequency pairs FA and which differ only in the modulation rate MA and MB utilized, changing the frequency pair utilized with the one of the codes results in listener discrimination between the two ringing codes. 
     The combination of these two different auditory dimensions (frequency and modulation rate) results in a larger number of distinguishable ringing codes than is possible by utilizing only one auditory dimension to distinguish the various ringing codes. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The characteristics and operation of the present invention will be more apparent from the following detailed description taken in conjunction with the drawing in which: 
     FIG. 1 is a simplified block diagram of a telephone ringing circuit useful in describing the present invention; 
     FIG. 2 shows typical signals into and out of the ring signal comparator circuit; 
     FIG. 3 shows a table of valid ringing codes according to the present invention; 
     FIG. 4 shows a schematic of the frequency oscillator and modulation oscillator in accordance with the present invention; and 
     FIG. 5 shows a schematic of logic circuits used in the modulation rate circuit, tone control circuit and ring detector circuit of the present invention. 
    
    
     GENERAL DESCRIPTION 
     This patent application is being filed concurrently with D. M. Embree-D. C. Goldthorp-H. H. Longenecker-D. R. Vogelpohl, filed on Feb. 28, 1983, Ser. No. 470,150. 
     FIG. 1 shows a block diagram of a telephone ringing circuit utilizing the present invention. Input Circuit 103 is ac coupled to telephone line T,R via a series resistor 102 and capacitor 101. Input Circuit 103 includes standard full-wave bridge rectifier, voltage divider, surge protection circuit and power supply circuits. The voltage divided rectified ring signal, VMAG, from Input Circuit 103 connects to Ring Signal Magnitude Comparator 104. Magnitude comparator 104 compares VMAG against a bandgap reference voltage VBG from Reference Generating Circuit 108. The output, MAG, from Magnitude Comparator 104 provides an input to the Ring Detector Circuit 105. The signal MAG is a digital logic signal which is logic 1 during the time when signal VMAG exceeds VBG and is logic 0 during the time when VBG exceeds VMAG. Shown in FIG. 2 are typical MAG signals which are generated by the Comparator Circuit 104 in response to a VMAG ringing signal 201 and dial pulse transient signal 202. 
     An output voltage VB of Input Circuit 103 connects to Bridge Loading Circuit 106 which provides a nonlinear load to signals appearing on telephone line T,R. Loading Circuit 106 provides a high impedance for low voltage voice signals and an appropriately low impedance for higher voltage ringing signals. Loading Circuit 106 attenuates the signals on the output of Input Circuit 103 such that the output MAG of Magnitude Comparator 104 is high, on the average, for a predominantly longer period of time for valid ringing signals, and is low, on the average, for a longer period of time for dial pulse transients (see FIG. 2). 
     Loading Circuit 106 enables the Ring Detector Circuit 105 to distinguish valid from invalid ringing signals as described in a later paragraph. The operation relies on the principle that since dial pulse or switchhook transients represent reverse emf inductive energy, they are dissipated and attenuated on a time average basis to a greater degree than the minimum central office ringing voltage when subjected to a low impedance load. Loading Circuit 106 also provides an output lead, LED, which provides a constant current to operate a light-emitting-diode (LED) or other output device during the time when a ringing signal exists on line T,R, as determined by valid ring signal RDET from Ringing Detector Circuit 105. Signal RDET also removes the low impedance of Loading Circuit 106 from across the line T,R once a valid ringing signal is detected. 
     The voltage VS from Input Circuit 103 connects to diode 107 and Reference Voltage and Current Generating Circuit 108. The voltage VBG is used as a reference by various circuits of the Telephone Ringing Circuit (FIG. 1). Diode 107 provides a capability for using an external dc voltage VEXT to power the Telephone Ringing Circuit when no ringing signals are present on the line T,R. This feature is utilized, for example, during paging signaling. 
     Reference Circuit 108 receives dc voltage VS from Input Circuit 103 and provides, in a standard manner, reference voltages V1-V4 and current I1 to other circuits of FIG. 1. Reference Circuit 108 also provides a power-up reset signal, RESET, for initializing Ring Detector Circuit 105. Modulation Oscillator 109 which operates at 28.8 KHz is divided down by a factor of 60 by counter 110. The output of counter 110 is used to provide a 480 Hz clock signal CLK which is used by Ring Detector 105 and Modulation Rate Circuit 111. 
     Ring Detector Circuit 105 uses the magnitude signal, MAG, to enable an up/down counter which counts clock signals, CLK, to determine if the signal on the line T,R is a ringing signal or a dialing transient. The reset signal, RESET, initializes Ring Detector Circuit 105 when power is first applied to Telephone Ringing Circuit, FIG. 1. The ring detected signal, RDET, is utilized by the Bridge Loading Circuit 106, as previously noted, and also enables Output Switch 114. 
     Frequency Oscillator 112 can be switched to provide any one of four different frequencies under external control via leads F1, F2. The logic signals on leads F1, F2 are either manually selected by the user using switches (not shown), or selected under control of other circuitry (not shown). The selected frequency is outputted on lead TO from Frequency Oscillator 112 to Tone Control Circuit 113. 
     Modulation Rate Circuit 111 receives clock signal CLK which is counted down to provide one of four possible modulation rates to Tone Control Circuit 113 via lead MOD. The selected modulation rate is determined via leads M1, M2 which can be controlled by the telephone user via switches (not shown) or can be selected under control of other circuitry (not shown). An external modulation disable lead, MDIS, disables Modulation Rate Circuit 111 and causes a logic 1 signal on lead MOD to Tone Control Circuit 113. 
     Tone Control Circuit 113 receives the modulation rate control signal over lead MOD. With the Modulation Rate Circuit 111 disabled MOD is at logic 1 and Tone Control Circuit 113 outputs a single frequency tone on lead TONE to Output Switch 114. When a frequency shift (i.e., frequency modulated) signal is desired then lead MOD provides a signal at the desired modulation rate. A frequency shift circuit in Tone Control Circuit 113 modulates between two frequencies having a frequency ratio of 1.25. These frequencies are generated from the frequency received over lead TO. While Tone Control Circuit 113 is described as modulating between two frequencies it is contemplated that more than two frequencies can be utilized. 
     An external input AM is used to select either the frequency shift or amplitude modulation (AM) mode of operation for Tone Control Circuit 113. In the AM mode a single frequency is switched on and off at the modulation rate on lead MOD. 
     Additionally, Tone Logic Circuit 113 includes a duty cycle circuit incorporated into a divide by seven counter. This provides a tone output which is high for 28 percent of the time of each tone period. The signal on lead TONE has a 28 percent duty cycle to efficiently drive an electromagnetic transducer (not shown) via lead VOUT. Obviously, for other types of transducers or speakers a different duty cycle may be utilized. 
     Output Switch 114, a standard logic circuit, gates TONE lead signal to Output Amplifier 115 as a function of leads RDET, TEN and RINH. External lead ring inhibit RINH is used to inhibit ringing when the circuit is powered from central office ringing. A tone enable lead TEN allows the generation of audible output when the telephone ringing circuit is powered from an external dc voltage supply applied via lead VEXT. External diode 107 is used to decouple this voltage supply from central office ringing voltages on lead VS. When Telephone Ringing Circuit, FIG. 1, is powered from the central office ringing signal, lead RDET enables an audible output from Output Switch 114 only after the Ring Detector Circuit 105 detects a valid ringing signal. 
     The standard Output Amplifier 115 can drive, via lead VOUT, either a piezoelectric capacitive type transducer or an electromagnetic inductive transducer. The amplifier output can be externally controlled via volume control leads VC1 and VC2. 
     The table shown in FIG. 3 illustrates the effect of adding modulation rate as an auditory dimension to distinguish ringing codes. In FIG. 3 columns FA through FD represent the frequency pairs generated by using the four binary combinations of leads F1, F2 of Frequency (Tone) Oscillator 112. The rows MA through MD represent the modulation rates generated by using the 4 binary combinations possible using the modulation select leads M1, M2 is Modulation Rate circuit 111. 
     Using only frequency modulation (or shifting) as an auditory dimension to distinguish ringing codes results in using, for example, only frequency pairs FA and FC at modulation rate MA. These codes are shown as 1 and 2 in the table shown in FIG. 3. This assumes that frequency pair FB is not distinguishable from pair FA or FC. If a change is made to another auditory dimension, i.e., modulation rate, then frequency pair FA and FC at modulation rate MC (i.e., codes 3 and 4) can be distinguished both from each other and from frequency pair FA and FC at modulation rate MA (i.e., codes 1 and 2). This assumes that the difference in modulation rate between MA and MC are distinguishable while MB is not distinguishable from MA or MC. 
     Moreover, as previously noted, when both frequency shifting and modulation rate are utilized as auditory dimensions to distinguish ringing codes, then new frequency pairs and modulation rates can be added to the ringing code repertoire. These new ringing code are distinguishable from existing codes in two auditory dimensions. For example, ringing code 5 while not easily humanly distinguishable from codes 1, 2, 3, 4 on either a frequency shifting basis alone, or a modulation rate basis alone, is easily distinguishable on the combined frequency shifting and modulation rate basis. Thus, code 5 using frequency pair FB at modulation rate MB differs from the nearby codes 1, 2, 3, and 4 in both the frequency shifting and modulation rate audible dimensions. Similarly, each of the ringing codes 6, 7, 8 differs from their neighbor codes in two audible dimensions and are hence easily distinguished therefrom. 
     In the table of FIG. 3, one illustrative group of frequencies generated by Tone oscillator 112 which are designated f1 through f4 of frequency pairs FA through FD are, respectively, 750 Hz, 900 Hz, 967 Hz and 1200 Hz. In a two frequency group the preferred frequencies are 750 Hz and 1200 Hz or other frequencies having a frequency ratio in the range 1.6 to 2.0 to 1. In the table of FIG. 3, one illustrative group of modulation rates generated by Modulation Rate Circuit 111 and designated as MA through MD are, respectively, 7.5, 10, 15, and 20 Hz. In a two modulation rate group are preferred modulation rates are 7.5 Hz and 20 Hz or other rates having a modulation rate ratio in the range 2.6-3.0 to 1. 
     DETAILED DESCRIPTION 
     In one embodiment Modulation Oscillator 109 and Tone Oscillator 112 are implemented as ring oscillators on a common integrated circuit chip. A schematic diagram of such an arrangement 40 is shown in FIG. 4. With reference to FIG. 4, the current on lead I1 flows through adjustable resistor R402 and transistor 417 which along with resistor R401 forms a temperature dependent reference current source 41. The particular temperature dependence characteristic is determined by the base emitter voltage VBE of transistor 417 and the particular values and types selected for adjustable resistors R401 and R402. The temperature coeffficient of reference current source 41 cancels the inherent temperature coefficient of ring oscillators 109 and 112. This reference current feeds current divider 42 formed by transistors 411 through 416. The current in each leg (i.e., 43 and 44) of current divider 42 and thus the frequency of oscillators 109 and 112, is determined by trimming resistors R401 and R402 and the multiple emitters of transistors 412. The emitter trimming of transistor 412, via metal links X1 through X4, determines the ratio of current in each leg (43 and 44) of current divider 42. Transistors 418 and 419 provide the bias reference voltage for transistors 420 through 422. 
     Transistor 413 through 415 of current mirror 42 feed transistors 420 through 430 and 435 which form the switchable ratio current mirror leg 43 for Tone Oscillator 112. Transistor 416 performs a base current helper function for current divider 42. Transistors 426 and 427 form a Darlington helper function for current mirror 43. The collector current of transistor 415 is passed through the multiple emitter buffer transistor 422 to the switchable NPN current mirror reference set up by transistors 423 through 427. The frequency control input leads F1 and F2 determine whether transistors 423 and 424 are part of the current mirror reference for 43. If lead F1 is pulled low (logic 0) and lead F2 is open (logic 1) then transistor 420 is off and the reference current in the collector of transistor 415 is divided appropriately between transistors 423 and 425. This effectively increases the emitter ratio of the setup transistor in the mirror and reduces the currents in the rest of the mirror output transistors. With F2 open transistor 421 is &#34;on&#34; which reverse biases the emitter of transistor 422 that is connected to the collector of transistor 421. This removes transistor 424 from the current mirror set up. If both F1 and F2 are low then transistors 423 through 425 form the reference transistor for the current mirror 43 and the lowest valued current source is generated in the remainder of the mirror. This condition yields the lowest frequency from the Tone oscillator (112 of FIG. 1). 
     The relationship between the selected frequencies is controlled by appropriately scaling the emitter sizes of transistor 423 through 425. Transistors 431 through 433 with capacitors C403 and C404 form a conventional ring oscillator whose frequency is contolled by the current sources in transistors 428 through 430. Transistor 435 provides a bias current path for Darlington helper transistors 426 and 427. Transistor 434 forms an interface between Tone oscillator 112 and the connected Tone Control Circuit 113 of FIG. 1. 
     The Modulation oscillator (109) functions similarly, except that the current in leg 44 of the current mirror is not switchable. Transistors 408, 409 and 436 perform the same function in 44 as transistors 426, 427 and 435, respectively did in 43. However, the frequency of the modulation oscillator can be adjusted by trimming the metal links X5 and X6 of the emitters of transistor 410 which adjusts the current mirror ratio. In Modulation Oscillator 109, transistors 405 through 407 form the current sources which determine the frequency of the ring oscillator formed by transistors 401 through 403 and capacitors C401 and C402. Transistor 404 forms an interface between the Modulation Oscillator 109 and Counter 110 of FIG. 1. 
     Referring to FIG. 5, there is illustrated a detailed block diagram of Modulation Rate Circuit 111, Tone Control Circuit 113 and Ring Detector 105. The illustrated function blocks of FIG. 5 are implemented using well-known standard logic circuits. In FIG. 5, the Output Modulation Oscillator 109 is divided by 60 by counter 110 to generate the clock signal CLK for Ring Detector circuit 105 and the Modulation Rate circuit 111. Modulation Rate Circuit 111 controls the rate at which Tone Control Circuit 113 switches (modulates) between the two tones generated by a signal TO. In Modulation Rate Circuit 111, the clock CLK is divided by four, by counter 501, and further divided by eight, six, four, or three, by Selectable Counter 502, depending on the status of external modulation rate control signal inputs M1 and M2. Selectable counter 502, in one implementation, comprises a divide by eight counter whose outputs are decoded and fed back to control the output division of the counter as a function of inputs M1 and M2. With both inputs M1 and M2 open (logic 1) a divide by three is selected. With both M1 and M2 inputs pulled low (logic 0) a divide by eight is selected. The output of Counter 502 is divided by two by counter 503, resulting in a 50 percent duty cycle output at lead MOD at a modulation rate of 7.5 Hz, 10 Hz, 15 Hz or 20 Hz depending on the state of inputs M1 and M2. It is in accordance with the invention that the signals on leads M1 and M2 can be coordinated with the signals on leads F1 and F2 of Tone Oscillator 112 to provide a first group of frequencies. The MDIS input disables Modulation Rate Circuit 111 and makes the MOD output high (logic 1). 
     It is in accordance with the invention that to provide both modulation rate and frequency modulation changes in an encoded ringing signal requires that both signals on leads M1 and M2 and leads F1 and F2 (of Tone Oscillator 112) be changed concurrently. Thus, one control signal selects a first modulation rate by controlling the signals on leads M1 and M2 while concurrently selecting a first group of frequencies by controlling the signals on the leads F1 and F2. A second control signal defines an audibly distinguishable set of codes by selecting a second modulation rate using signals on leads M1 and M2 for a second group of frequencies as selected via leads F1 and F2. 
     Controllable counter 504 of Tone Control Circuit 113 receives the tone oscillator input TO and divides it by five or four at the modulation rate MOD. When lead MOD is high a divide by five is selected, and when MOD is low a divide by four is selected. Counter 504 enables Tone Control Circuit 113 to modulate between two single frequency tones having a ratio of 1.25. In one embodiment, Counter 504 is a programmable counter which operates under control of lead MOD. It should be obvious that Controllable Counter 504 could be arranged to provide any plurality of frequencies which can be selectively enabled by signal MOD. 
     The output of Counter 504 is divided by seven in counter 505 resulting in output, TONE, that is high for two pulses out of seven (i.e., a 28 percent duty cycle for the output TONE). The AM input, at logic 0, into counter 505 changes the type of modulation of Tone Control Circuit 113 from frequency shift modulation to amplitude modulation. In the amplitude modulation mode, the divide by 4 output from Counter 504 is inhibited and only the divide by 5 output of Counter 504 is counted down by counter 505. The resultant amplitude modulated TONE output is produced at the tone oscillator frequency (TO) divided by 35 which is switched on and off at the modulation rate MOD. 
     Ring Detector Circuit 105 is designed to detect valid ringing signals and to generate a ring detect signal RDET from the detected envelope of the ringing signal. Thus, when a valid ringing signal is present on line T,R control signal RDET is at logic 1, and when no ringing signal is present RDET is at a logic 0. This RDET signal is used as an enable or more generally a binary (on-off) amplitude control signal for Output Switch 114. 
     Ring Detector circuit 105 uses the CLK, MAG, and RESET inputs to implement a digital ring signal detection scheme to distinguish valid from invalid ringing signals. As previously described, Ring Detector 105 functions in coordination with the Bridge Loading circuit 106 and Magnitude Comparative 104. With reference to FIG. 2, Ring Detector 105 distinguishes valid ringing signals (201) from dial pulse relay transients (202) by counting the number of clock pulses which occur during the time when signal MAG is at logic 1 and subtracting the number of clock pulses when signal MAG is at logic 0 on a continuous basis. Since signal MAG is logic 1 for a greater percentage of time when a valid ringing signal (201) is received, the counter reaches a prescribed upper limit which is not reached during dial pulse relay transients (202). 
     With reference to FIG. 5, when either HYST or the RESET input is high (logic 1) gates 507 and 508 reset flip-flop 509 causing the RDET output to be held low. The RESET input also presets D-type flip-flop 510 and its Q output clears the up/down counter 511 via the CL input lead. Referring to FIG. 1, the RESET lead goes low when the line T,R supplied input voltage is sufficient to power the telephone ringing circuit. At this time the RESET signal to the D input of flip-flop 510 in FIG. 5 is low and, since flip-flop 510 is positive edge triggered, on the first positive edge of the signal Up/Down, flip-flop 510 is reset and output Q goes high enabling Counter 511 to start counting up. The Up/Down signal is derived from lead MAG by clocking MAG into D flip-flop 512 on the positive edge of the clock signal CLK. Clock disable circuit 513 disables the clock signal from reaching Up/Down counter 511 when either the Up/Down signal is high and counter 511 is at the top of its count (OFL high), or when the Up/Down signal is low and counter 511 is at the bottom of its count (NEG high). Count decoder 514 decodes outputs QA, QA, QB, QB, QC, QD, and QD of counter 511 to define a lower bound for up/down counter 511 (NEG), an upper bound and ring detect state for the counter 511 (OFL), and a state which resets the ring detect output RDET after ringing ceases (HYST). Count decoder 514 creates a bounded count and prevents rollover in counter 511. 
     As previously noted, for a valid ringing signal on line T,R the MAG signal has a duty cycle greater than 50 percent as shown in FIG. 2. Such a MAG signal causes up/down counter 511 to eventually reach the top of its count which generates a high signal on lead OFL. On the positive edge of the clock CLK the OFL sets flip-flop 515 and sets flip-flop 509 causing RDET signal to be high. When the ringing signal is removed from line T,R, the MAG signal goes low and the counter 511 counts down. When counter 511 reaches a preset count, lead HYST goes high which resets flip-flop 509 causing RDET to go low. The timing of Ring Detector 105 is set so that the counter 511 does not generate a HYST signal, causing RDET to go low, during the low interval of MAG signal for normal ringing signals. However, Ring Detector 105 causes RDET to go low thereby terminating the output tone on lead VOUT a short time after ringing is removed from line T,R to provide a sharp turn off characteristic for the tone. 
     Signal RDET causes the Output Switch, 114 of FIG. 1, to switch on and off thereby encoding the amplitude of output signal VOUT to follow the on-off sequence of the ringing signal received on line T,R. Therefore, the disclosed Telephone Ringing Circuit (FIG. 1) is essentially transparent to a binary (on-off) amplitude encoded ringing signals received over line T,R. Moreover, the Telephone Ringing Circuit (FIG. 1) can add frequency modulation and modulation rate encoding to provide a second type of encoding to the ringing signal. Thus, for example, in the output signal VOUT of Telephone Ringing Circuit the received on-off amplitude encoding of the ringing signal can represent call origin information while the modulation rate and frequency modulation encoding can represent call destination information. Additionally, it should be recognized that if the received ringing signal on line T,R is not encoded, a locally generated amplitude control signal can be ANDED (not shown) with RDET to provide an amplitude control signal for the RDET input of Output Switch 114. 
     While the ringing circuit shown in FIG. 1 is described for use in a telephone ringing circuit it can be utilized in other audible signaling or communication circuits without deviating from the teaching of this invention. Moreover, the method and circuitry of the present invention can be embodied in discrete components, integrated circuits, large scale integrated circuits or as part of a microprocessor embodiment of a station set or other communication device. Thus, what has been described is merely illustrative of the application of the principles of the present invention. Other methods and circuits can be implemented by those skilled in the art without departing from the spirit and scope of the present invention.