Abstract:
In a data processing system, a flexible cable includes a pattern of transmission lines formed thereon, the lines having a predetermined width. On the transmission lines are formed a first set of lands each for connecting a connection pin of an RJ45 connector and a second set of lands each for connecting a connection pin of a transmission line connector—each land being wider than a transmission line. A transition region is provided in each transmission line in the vicinity of the land, the width of the transition region increasing gradually from the line width to the land width as the transmission line approaches the pin.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to a signal transmission line connector, a signal transmission line, a signal transmission cable and a data processing system and more particularly to a signal transmission line connector, a signal transmission line, a signal transmission cable and a data processing system for use in a transmission line network such as an Ethernet network. 
     BACKGROUND OF THE INVENTION 
     When designing an Ethernet network, the design must conform to the ANSI IEEE Standard 802.3 1993, which regulates the design including that of the transmission circuit for each network adapter so as to assure correct operation of the network. 
     To provide a lap-top personal computer (PC) with Ethernet functions using a mini-PCI type network card of, for example, the Type III model, therefore, the PC includes a transmission line so as to correspond to the Ethernet. 
     However, in case the lap-top PC must be provided with a port replication function at an RJ45 port at such an extended unit side used as, for example, a docking station and/or in case a mechanically efficient transmission line is disposed in the lap-top PC, a transmission line connector other than the RJ45 connector must be used unavoidably on the transmission line network, although the use of such a nonstandard connector should be avoided originally. 
     When such a nonstandard transmission line connector is used, a return loss occurs at the connection area due to impedance mismatching. Consequently, a stationary wave is generated, thereby attenuating the signal. This disables the subject data communication, resulting in a communication error. 
     In such a case, a transmission line connector that satisfies the characteristics required for the Ethernet Standard should be used. Otherwise, it would be difficult to develop a new transmission line connector that agrees to the design requirement each time a system is developed when the number of processes and the cost are taken into consideration. 
     Japanese Published Unexamined Patent Application No. 9-51209, the contents of which are incorporated herein by reference, discloses a technique for preventing such impedance mismatching by changing both the permittivity of the substrate material and the width of the transmission line pattern. This technique, which unavoidably changes the permittivity of the substrate material gives rise to an increase in manufacturing cost. 
     Under such circumstances, it is an object of the present invention to provide a signal transmission line connector, a signal transmission line, and a substrate that can prevent the whole subject transmission line network from degradation of the transmission characteristics even when the network uses a transmission line connector whose characteristic impedance differs from that required for the transmission lines. 
     SUMMARY OF THE INVENTION 
     In order to attain the above object, the transmission line connector of the present invention enables a signal transmission line to be connected to a terminal area in an transition region. The transmission line is formed at a predetermined width so as to transmit a signal and the terminal area is formed at a specific width differently from the predetermined width so as to input/output a signal to be transmitted by the signal transmission line. The transition region is formed around the terminal area so that the predetermined width of the signal transmission line is changed gradually to the specific width of the terminal area in the transition region as the line goes towards the terminal area. 
     And, a plurality of such signal transmission lines are also formed on, for example, a flexible cable at a predetermined width therebetween and those transmission lines are used, for example, for communications among computers via a network. At an end or at a middle point of each of those transmission lines is formed a terminal area used to input/output a signal. This terminal area can be formed not only on the flexible cable, but also another type of substrate such as a printed circuit board. The terminal area has a specific width, which is different from that of the signal transmission line. Consequently, the impedance differs between the signal transmission line and the terminal area. 
     Consequently, in the present invention, the transition region is formed so that the predetermined width of the signal transmission line is changed gradually to the specific width of the terminal area therein as the line goes towards the terminal area and the transmission line is connected to the terminal area therein. And, because the width of the signal transmission line is changed gradually around the terminal area, the impedance around the terminal area can be prevented from an abrupt change even when the impedance differs between the signal transmission line and the terminal area. Consequently, a return loss to be expected around the terminal area can be reduced, thereby the attenuation of the signal can be prevented so as to assure normal communications. 
     The length of the transition region, that is, the length of the section in which the width of the signal transmission line is changed gradually, can be decided as follows, for example. At first, an impedance is found from an equalizing circuit of the signal transmission line system including the signal transmission line and the terminal area, then the area of the transition region, which is equivalent to the impedance, is found. This area can be found in accordance with the required impedance from the inductance and capacitance characteristics of the material of the signal transmission line. When the area of the transition region is decided, the length of the transition region can be found easily from the area, the predetermined width of the signal transmission line, and the specific width of the terminal area. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic block diagram of an example computer system in which the present embodiment is employed; 
     FIG. 2 is a perspective external view of a lap-top PC; 
     FIG. 3 is a perspective external view of the lap-top PC and a docking station; 
     FIG. 4 is a schematic view of a network adapter and a flexible cable; 
     FIG. 5 is a view showing wiring patterns on the flexible cable; 
     FIG. 6 is a top view of a transmission line pattern; 
     FIG. 7 is a circuit diagram of an equalizing circuit of a transmission line system; and 
     FIG. 8 is a line graph for describing the relationship between a signal frequency and an attenuation. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Hereunder, the preferred embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 shows a hardware block diagram of a computer system  10  configured by a typical personal computer (PC) preferred to realize the present invention. The computer system  10  is divided into subsystems in the explanatory view shown FIG.  1 . 
     An example of a PC embodying the present invention is a lap-top PC  12  (see FIG. 2) that conforms to the OADG (PC Open Architecture Developer&#39;s Group) specifications and includes Windows98 or NT operating system (OS) from Microsoft Corp installed therein. Hereinafter, each component of the computer system  10  will be described. 
     A CPU  14  that functions as the brain of the computer system  10  executes various programs under the control of the OS. The CPU  14  may be one of the family of Pentium CPU chips (e.g.“Pentium”, “Pentium MMX”, “Pentium Pro” and successors) sold by Intel Corporation. The CPU  14  may alternatively be a CPU from such other companies as AMD Inc or may be the “PowerPC” from IBM Corporation. The CPU  14  is configured so as to include an L 2  (level  2 ) cache, which is a fast operation memory used to reduce the time of the total access to a main memory  16  by saving some codes and data items that are accessed frequently. Generally, the L 2  cache is configured by an SRAM (Static RAM) chip. 
     The CPU  14  is connected to each of the hardware components via one or more buses of a three-layer bus configured by an FS (Front Side) bus  18 , which is connected directly to the external pins of the processor (CPU  14 ); a PCI (Peripheral Component Interconnect) bus  20  used for fast I/O devices; and an ISA (Industry Standard Architecture) bus  22  used for slow I/O devices. 
     The FS bus  18  and the PCI bus  20  are connected to each other via a CPU bridge (host-PCI bridge)  24  referred to generally as a memory/PCI control chip. The CPU bridge  24  in this embodiment includes a memory controller function for controlling access to the main memory  16 , a data buffer for absorbing a difference in the data transfer rate between the FS bus  18  and the PCI bus  20 . For example, a  440 BX (from Intel Corporation) can be used as the CPU bridge  24 . 
     The main memory  16  is a writable memory used as an area in which an execution program of the CPU  14  is read or as a work area in which data processed by the execution program is written. The main memory  16  is configured by, for example, a plurality of DRAM (Dynamic RAM) chips. 
     The execution program mentioned here is, for example, any of various device drivers for operating peripheral devices, application programs dedicated to specific business works, and such firmware programs as the BIOS stored in the flash ROM  72 . 
     The PCI bus  20  is of a type enabled to transfer data comparatively fast and the PCI bus  20  is connected to such PCI devices as a card bus controller  30 . The PCI architecture was originally proposed by Intel Corporation and is used to realize the so-called PnP (Plug and Play) function. 
     The video subsystem  26  is used to execute video-related functions. The subsystem  26  includes a video controller that processes each graphic instruction from the CPU  14 , writes the processed graphic information in the video memory (VRAM) once, and reads graphic information from the VRAM so as to display it on a liquid crystal display (LCD)  28  (see FIG. 2) as graphical data. The video controller can also convert digital video signals to analog video signals using the digital-analog converter (DAC) provided therein. The analog video signals are output to a CRT port (not illustrated) via a signal line. 
     The PCI bus  20  is connected to a card bus controller  30 , an audio subsystem  32 , a docking station interface (Dock I/F)  34 , and a mini-PCI slot  36  respectively. The card bus controller  30  is used exclusively to connect the bus signal of the PCI bus  20  directly to the interface connector (card bus) of a PCI card bus slot  38 . The card bus slot  38  is disposed, for example, on the wall surface of the PC  12  body and enabled to load a PC card  40  conforming to the specifications (ex., “PC Card Standard 95”) regulated by PCMCIA (Personal Computer Memory Association)/(JEIDA (Japan Electric Industry Development Association). 
     The dock I/F  34  is a hardware component used to connect the PC  12  to the docking station  96  (also see FIG.  3 ). When a connector (not illustrated) of the PC  12  is connected to the connector  98  of the docking station  96  shown in FIG. 3, the PCI-PCI bridge of the docking station  96  is connected to the dock I/F  34 . 
     The mini-PCI slot  36  is connected to a network adapter  42  used to connect the computer system  10  to a network (e.g. a LAN such as an Ethernet). The Ethernet adapter  42  is connected to an RJ45 connector  102  located on the rear portion of the PC  12  as shown in FIG. 3 via a flexible cable  100  (to be described later). 
     The PCI bus  20  and the ISA bus  22  are connected to each other via a PCI-ISA bridge  44 . The PCI-ISA bridge  44  is provided with a bridging function used between the PCI bus  20  and the ISA bus  22 ; a DMA controller function; a programmable interrupt controller (PCI) function; a programmable interval timer (PIT) function; an IDE (Integrated Drive Electronics) interface function; a USB (Universal Serial Bus) function; and an SMB (System Management Bus) interface function. The PCI-ISA bridge  44  has a built-in real time clock (RTC). For example, a PIIX 4  chip from Intel Corporation can be used as the PCI-ISA bridge  44 . 
     The DMA controller function transfers data between a peripheral device (e.g. FDD) and the main memory  16  independently of the CPU  14 . The PCI function enables a predetermined program (interrupt handler) to be executed in response to an interrupt request (IRQ) from a peripheral device. The PIT function generates a timer signal in programmable predetermined cycles. 
     The IDE interface realized by the IDE interface function is connected to an IDE hard disk drive (HDD)  46  and to the IDE CD-ROM drive  48  via an ATAPI (AT Attachment Packet Interface). 
     The PCI-ISA bridge  44  is provided with a USB port connected to a USB connector  50  provided, for example, on the wall surface of the PC  12  body. USB supports hot plugging for connecting and disconnecting a USB peripheral device while the PC  12  is powered and plug-and-play for recognizing a newly connected peripheral device automatically, thereby resetting the system configuration. 
     Furthermore, the PCI-ISA bridge  44  is connected to an EEPROM  94  via the SM bus. The EEPROM  94  is a non-volatile memory used to hold information such as the password registered by each user and a supervisor password, a product serial number, etc. The data in the memory  94  can be rewritten electrically. 
     The PCI-ISA bridge  44  is also connected to an electric power circuit  54  via shut-down reset logic  52 . Inside the core chip that configures the PCI-ISA bridge  44  is provided power management capability for managing the electric power state of the computer system  10 . The electric power circuit  54  controls the supply of the electric power to the computer system  10  according to an instruction from the power management of the PCI-ISA bridge  44 . 
     The ISA bus  22  has a data transfer rate slower than that of the PCI bus  20 . The ISA bus  22  is connected to comparatively slow peripheral devices (not illustrated), such as a flash ROM configured by a super I/O controller  70 , an EEPROM, etc.; a CMOS  74 ; and a keyboard/mouse controller. 
     The super I/O controller  70  is connected to an I/O port  78 . The super I/O controller  70  controls the driving of the floppy disk drive (FDD), the input/output of parallel data via a parallel port (PIO), and the input/output of serial data via a serial port (SIO). 
     The flash ROM  72  is a non-volatile memory used to hold various BIOS programs. The data stored in this ROM  72  can be rewritten electrically. The CMOS  74  is a non-volatile semiconductor memory connected to a backup electric power source. It functions as a fast storage device. 
     In addition to those shown in FIG. 1, many more electrical circuits are required to configure the computer system  10 . However, because those electrical circuits are already known to those of skill in the art and they are not relevant to an understanding of the present invention, they will be omitted in this specification. It will also be noted that only some of the connections between hardware blocks in the drawings are shown in order to simplify the description. 
     Next, a description will be made of a transmission line pattern formed on the flexible cable  100  connected to an Ethernet adapter  42 . 
     The Ethernet adapter  42  is connected to the flexible cable  100  as shown in FIG.  4 . On the flexible cable  100  is formed an Ethernet pattern of signal transmission lines, connected to the RJ45 connector  102  located at the rear portion of the PC  12  as shown in FIG.  3 . 
     And, as shown in FIG. 4, the flexible cable  100  is provided with a transmission line connector (board to board connector)  106  used to connect the Ethernet pattern to the main board  104  of the PC  12  so as to connect the docking station  96 . This transmission line connector  106  is connected to the main board  104  so as to connect the docking station  96  to the network adapter  42  via the main board  104 . 
     FIG. 5 shows an expanded view of the flexible cable  100  in the region of the transmission line connector  106 . As shown in FIG. 5, a pattern of transmission lines  108  is formed on the flexible cable  100 . 
     On the transmission lines  108  are formed lands  112  (terminal areas) for connecting pins  110  of the RJ45 connector  102 ; and lands  116  for connecting pins  114  of the transmission line connector  106 . Each land  112  is connected to a pin  110  of the RJ45 connector  102  and each land  116  is connected to a pin  114  of the transmission line connector  106  by soldering. 
     The differential impedance of a line pattern of a transmission line network is required to be 100Ω, which is a design target value in an Ethernet transmission line network. Consequently, each transmission line  108  formed on the flexible cable  100  is designed so as to have a differential impedance of 100 Ω. 
     However, the specific impedance of the transmission line connector  106  is, for example, 65Ω. The connector  106  is used to connect the transmission lines  108  formed on the flexible cable  100  used in the transmission line network to a pattern on the main board  104 . 
     In accordance with the present invention, the width of a transmission line  108  is changed gradually in the vicinity of connection pin  114  of the transmission line connector  106  as the transmission line reaches the corresponding connection pin  114  as shown in FIGS. 5 and 6. This is to minimize the influences of a return loss, etc. caused at a connector boundary, that is, around the transmission line connector  106  due to a difference between the impedance of the transmission line  108  formed on the flexible cable  100  and the impedance of the transmission line connector  106 . 
     Thereby, because no abrupt impedance change occurs, a return loss otherwise to be expected in the connection area can be suppressed, thereby minimizing the influence of the impedance mismatch around the connector  106 . 
     In the same way, the width of the transmission line  108  can be changed gradually in the vicinity of the connection pin  110  of the RJ45 connector  102  as the transmission line  108  goes towards the corresponding connection pin  110 . 
     Next, a description will be made as to how to calculate a length of the section where the width of a transmission line  108  is changed. 
     At first, an equivalent circuit (connector lumped constant model) as shown in FIG. 7 is created by taking the flexible cable  100  and the transmission line connector  106  into consideration so as to calculate the above length on the assumption that the flexible cable  100  having a characteristic impedance of 100Ω and the transmission line connector  106  having a characteristic impedance of 65Ω is united into one. Then, an approximate expression is defined as shown below for finding an impedance Z of this equivalent circuit.              Z   =         L   c       C   /     (       CP   1     +     CP   2       )                   (   1   )                                
     And, according to the impedance Z obtained from the expression (1), the area S of a necessary pattern for the target characteristic impedance can be calculated from each of the values R (resistance), L c  (inductance), C (capacitance). Those R, L c , and C values are determined by the material of the transmission line pattern  108  of the flexible cable  100 . 
     Then, the length L and the inclination of the section in which the width W is changed gradually can be found naturally from this found area S, the width W of the transmission line pattern  108 , and the diameter K of the land  116  as shown in FIG.  6 . The width W of the transmission line pattern  108  and the diameter K of the land  116  are decided by the specifications of the PC  12 . 
     As an example, it is assumed that the target impedance Z is 100Ω, the width W of the transmission line pattern  108  is 0.3 mm, and the diameter K of the land  116  is 1.5 mm respectively, the length L found as described above becomes 6.5 mm. FIG. 8 shows a measurement result of the attenuation that occurs in the transmission line system. As shown in FIG. 8, the attenuation increases more for higher frequencies when the conventional technique is employed, that is, when the transmission line pattern is not changed gradually around the connector. However, when the transmission line pattern is changed gradually around the connector in accordance with the present invention, no abrupt impedance change occurs around the connector, thereby preventing a return loss. Consequently, the attenuation does not increase so much even when at high frequency. As shown in FIG. 8, for example, the attenuation is about 2.2 dB for a frequency of 98.9 MHz. The attenuation is within the target value ±10% and thus would satisfy the required performance. As compared with the conventional technique within a range of frequencies between 10 MHz to 100 MHz, it has been confirmed that the attenuation is reduced more significantly in the present invention. 
     While, in the embodiment described above, the transmission line connector  106  is formed on the flexible cable  100 , the present invention is not limited thereto; the transmission line connector may be formed on an ordinary printed board. 
     As described above, according to the present invention, because an transition is formed around a terminal area so that a signal transmission line is connected to a terminal area in the transition region where the predetermined width of the signal transmission line is changed gradually to the specific width of the terminal area as the line goes towards the terminal area, no abrupt impedance change occurs around the terminal area even when the impedance differs between the signal transmission line and the terminal area. Consequently, the return loss to be expected around the terminal area can be reduced, thereby the signal is prevented from attenuation so as to assure normal communications.