Abstract:
An analog to digital converter for the conversion of an analog input voltage to a digital output voltage signal of n bits has a plurality of voltage sources (Voltage Reference Generator) that divide the total range of voltage of the conversion input into increments of voltage equal to the smallest increment of resolution. The n bits of digital output are divided into an upper segment or Most Significant Bits (MSB) and a lower segment or Least Significant Bits (LSB). The Most Significant bits are encoded from a set of digital signals from a plurality of comparators (Coarse Subrange Comparators) that compare the voltage input with a subset of Voltage Reference Generator representing the coarse range. The Coarse Subrange Comparator outputs are used to determine the placement of a plurality of Embedded Subrange Comparators that are used to detect any error in the codes of the Coarse Subrange Comparators. The output of the Coarse and Embedded Subrange Comparators are now used to determine the connection of a plurality of Fine Subrange Comparators to the Voltage Reference Generator in the section of the Coarse Subrange to accurately determine the smallest increment of resolution for the Analog to Digital Converter. The codes from the Coarse, Embedded, and Fine Subrange Comparators become the input to an encoder to determine the output digital voltage that represent the input voltage.

Description:
BACKGROUND OF INVENTION 
     1. Field of the Invention 
     The present invention relates generally to Analog to Digital (A/D) converters and converting methods, and more particularly to two stage parallel type converters which use the first stage of conversion to determine the coarse range of the input voltage and a second stage to resolve the fine increment of the input voltage. The present invention has applicability to video and digital signal processing. 
     2. Description of the Background Art 
     The application of digital processing and transmission methods to analog information requires a technique for the conversion of signals from their analog form to a digital representation. Well known types of A/D converters include the Successive Approximation type which produces a digital output using a digital to analog converter to create successive trial and error approximations of the input, and the parallel comparator type or FLASH converter, which compares multiple voltage references to the input voltage and outputs from the encoding logic the digital code representing the voltage reference closest to the input voltage in one operation. FIG. 1 shows a representation of the FLASH type of A/D Converter. Typically the output is a binary code that is constructed in the Encoder Logic 30 thus providing an n bit resolution of the input signal. This structure typically requires 2 n  voltage references 10 and 2 n  comparators 20. As the resolution of this type of converter is improved (the number of output bits increases), the design becomes unwieldy. 
     In order to simplify the design of the FLASH A/D Converter, two techniques are known. In beth techniques multiple stages of conversion are used accomplish the A/D conversion. In the first technique, as shown in U.S. Pat. No. 5,302,869 (issued Apr. 12, 1994 to Hosotani et al. for a &#34;Voltage Comparator and Subranging A/D Converter Including Such Voltage Comparator&#34;), U.S. Pat. No. 5,389,929 (issued Feb. 14, 1995 to Nayebi et al. for a &#34;Two-Step Subranging Analog-To-Digital Converter&#34;), U.S. Pat. No. 5,353,027 (issued Oct. 4, 1994 to Vorenkamp et al. for a &#34;Multistep Analog-To-Digital Converter With Error Correction&#34;), U.S. Pat. No. 5,369,309 (issued Nov. 29, 1994 to Bacrania et al. for an &#34;Analog-To-Digital Converter and Method of Fabrication&#34;), and U.S. Pat. No. 5,387,914 (issued Feb. 7, 1995 to Mangelsdorf for a &#34;Correction Range Technique for Multi-Range A/D Converter&#34;), the first stage is a coarse resolution FLASH A/D conversion and the second stage, with a Digital to Analog Converter, adjusts the voltage references of the voltage comparators to form a fine resolution conversion. The results of the two conversions are encoded to form the digital output word representing the magnitude of the analog input voltage. In the second technique, as shown in U.S. Pat. No. 5,291,198 (issued Mar. 1, 1994 to Dingwall et al. for an &#34;Averaging Flash Analog-To-Digital Converter&#34;), U.S. Pat. No. 5,223,836 (issued Jun. 29, 1993 to Komatsu for a &#34;Subranging Analog-To-Digital Converter With Priority Weighted Correction for the M.S.B. Group&#34;), U.S. Pat. No. 5,400,029 (issued to Kobayashi for an &#34;Analog-Digital Converter Circuit Device and Analog-Digital Conversion Method&#34;), U.S. Pat. No. 4,733,217 (issued Mar. 22, 1988 to Dingwall for a &#34;Subranging Analog-To-Digital Converter&#34;), U.S. Pat. No. 5,349,354 (issued Sep. 20, 1994 to Ho et al. for an &#34;A/D Converter And Converting Method Having Coarse Comparison And Fine Comparison Periods&#34;), there will be multiple conversion stages with voltage references being appropriately switch to each stage by decision logic based on the results of the previous comparison stages. 
     As an example of the second techniques of multiple stage conversion, see in FIG. 2., which is a schematic diagram of U.S. Pat. No. 4,903,028 (issued Feb. 20, 1990 to N. Fukashima for an &#34;Analog to Digital Converter&#34;), that by creating a set of voltage sources 1 that have incrementally increasing values from V REFBOT  (the lowest value) to V REFTOP  (the highest value) establishes the range of conversion of the voltage input (V in ). A set of Coarse Subranging Comparators 2 are connected to the voltage input and to the set of voltage reference at discrete intervals establishing the course subranges 1a,1b of V in . The output of the Coarse Subrange Comparators 5 is the input to a Steering Logic and Switch Unit 3 that places a set of Fine Subrange Comparators 4 at the appropriate Subrange of the Voltage Reference Set 1. The set of Voltage References 1a are divided into fine increments establishing the maximum resolution of the conversion of V in  to Digital Output {D0, D1, D2, . . . , Dn}. As V in  changes the value of the output codes or the Coarse Subrange Comparators 5 change and the Steering Logic and Switch Unit 3 moves the Fine Subrange Comparators 4 to the next subrange (from 1a to 1b). 
     Due to the tolerances in component selection and process variation, the Output Codes 5 of the Coarse Subrange Comparators 2 may be in error. To detect this error, there will be Extra Fine Subrange Comparators 4a&amp;4b that will be placed above and below the subrange 1a or 1b determined by V in . The output of the Extra Fine Comparators 4a&amp;4b form an error code 7. The output codes for Fine Subrange Comparators 6, the set of error codes 7, and the set of Coarse Subrange Codes 5 are interpreted by the Output Encoding Logic 8 to determine the output digital representation {D0, D1, D2, . . . , Dn}. of the voltage input V in . 
     SUMMARY OF THE INVENTION 
     In the foregoing there are two sets of error detection circuits. The error correction function is stimulated on only one side of the Coarse Subrange on each comparison cycle of the Fine Subrange comparators. This type of configuration consumes additional power and adds additional complexity to the physical implementation. To reduce the number of extra comparators and simplify the complexity of the physical structure, the present invention (FIG. 3) uses a set of Embedded Coarse Subrange Comparators 140. The reference codes generated by the Embedded Coarse Comparators determine the proper reference range for the Fine Subrange Comparators 160. The codes from the Coarse Subrange Comparators 170, the Embedded Coarse Subrange Comparators 180, and the Fine Subrange Comparators 190 are encoded to form the output digital code. The selection to the placement of the Embedded Coarse Subrange Comparators 140 input references 131 are determined by the Embedded Coarse Subrange Selection Logic and Switches 130 from the input codes of the Coarse Subrange Comparators 170. The placement of the Fine Subrange Comparators References 151 are determined by the Fine Subrange Selection Logic and Switches 150 with input from the Coarse Subrange Comparators 170 and the Embedded Coarse Comparators 180. 
    
    
     DESCRIPTION OF DRAWINGS 
     FIG. 1 is drawing illustrating the prior art of parallel or FLASH A/D Converters. 
     FIG. 2 is a schematic of the prior art found in U.S. Pat. No. 4,903,028 illustrating a two stage Flash A/D Converter. 
     FIG. 3 is a schematic diagram of the structure of the A/D converter described in this invention. 
     FIG. 4 is a diagram describing the decision process structure of this invention. 
     FIG. 5 is a diagram describing the algorithm for the placement of Fine Subrange Comparators in this invention. 
     FIG. 6 is a timing diagram of a conversion cycle for the present invention. 
     FIG. 7 is a schematic diagram of the preferred embodiment of the Embedded Subrange Selection Logic and Switches. 
     FIGS. 8a and 8b are schematic diagrams of the preferred embodiment of the Fine Subrange Selection Logic and Switches. 
     FIG. 9 is a schematic diagram of the preferred embodiment of the Digital Output Word Assembly Logic. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 3, Voltage Reference Generator 100 is a structure that can create a set of reference voltages that incrementally increase from the value of V REFBOT  100a to V REFTOP  100b. The number of incremen3ts is dependent on the number of desired bits of output digital code {DB0, DB1, DB2, . . . , Dbn}. For instance, if the digital code were n and each bit represented a binary digit then the function for the number of voltage references would be 2 n  (As an example if n were 8, the number of references would be 2 8  or 256 voltage references). 
     The number of Coarse Subrange Comparators 200 is determined by the number of bits that is desired to segment the output word into sections called the Most Significant Bits (MSB) and the Least Significant Bits (LSB). The MSB&#39;s translates into the Coarse Representation of the Analog Input Voltage (V in ). If the digital code were n bits as above and the coarse subrange was to be 1/2 of the number of digits, then the number of Coarse Subrange Comparators 200 would be 2 n/2  (as an example if n=8, the number of Coarse Subrange Comparators 200 would be 2 8/2  or 16 comparators). The Coarse Subrange Comparators 200 would be connected permanently to the Voltage Reference Generator 100 at discrete increments {V REFBOT-N , . . . V RM , . . . , V REFTOP+N  }. This interval being dependent on the conversion function of the V in  to the digital output {DB0, DB1, DB2, . . . , Dbn} (for example if n=8 and the range of interest of V in  were from 0 volts to 1 volt then LSB of each binary number would be represent 1/256 volt. If the number of MSB&#39;s were determined to be 4 then the Coarse Subrange Comparators would be place at and interval of 16 binary counts or every 1/16 Volt). The Input Voltage (V in ) is sampled periodically by the Sample and Hold Circuit 110 and presented to as V ain  to the Coarse Subrange Comparators 200 to be compared to the Voltage References 100c. The output of the Comparators will switch to the desired logic level if the V in  is greater than or less than the voltage references 100c (for example the comparators may output a voltage level representing a logical 1 for an input greater than V REF  and the voltage level representing a logical 0 for an input less than V REF ). 
     The digital outputs of the Coarse Subrange Comparators are connected as input to the Embedded Coarse Subrange Selection Logic and Switch Circuitry 130. Each coarse subrange of the Voltage Reference Generator 100 is divided by the number of the Embedded Coarse Subrange Comparators 140. 
     The number of Embedded Coarse Subrange Comparators 140 is arbitrary and is chosen to simplify the Embedded Coarse Subrange Selection Logic and Switch Circuitry 130 and to establish an appropriate error correction range. (For example if the number of the Embedded Coarse Subrange Comparators 140 is chosen to be three and the number of fine increments in a coarse subrange is 16 then first, eighth, and sixteenth voltage references to be connected to the Embedded Coarse Subrange Comparators to cover the range). Depending on the value of the codes of the Coarse Subrange Comparators 170 the appropriate subrange is selected and switched and the references are connected to the Embedded Coarse Subrange Comparators 140 to be compared with the Input Voltage V ain . In an embodiment shown in FIG. 7, the outputs of the Coarse Subrange Comparators 170 form a first set of thermometer codes (a binary code that is formed by each successive digit of the code changing to a &#34;1&#34; as the code increases, for example: 
     
         ______________________________________0000          the lowest value of the code0001001101111111          the highest value of the code)______________________________________ 
    
     that determines the coarse value of the input voltage Vain from FIG. 3. The thermometer codes 172 are the inputs to the Selection Logic Array 132. The output of the Selection logic Array 132 sets the Steering Switches 134a, 134b, 134c to connect the correct Voltage Reference of the Voltage Reference Generator 100 to the Embedded Coarse Subrange Comparators 140. In FIG. 3, the output of the Embedded Coarse Subrange Comparators 180 form a second thermometer code which, when combined logically with the output of the Coarse Subrange Comparators 170 in the Fine Subrange Selection Logic and Switches 150 determines the placement of the finest increments of the Voltage Reference Generator 100 to the Fine Subrange Comparators 160. The output of the Fine Subrange Comparators 160 form a third set of thermometer codes that define the finest increment of the input voltage Vain. 
     The first thermometer code outputs of the Coarse Subrange Comparators 170, the second thermometer code outputs of the Embedded Coarse Subrange Comparators 180, and the third thermometer code of the Fine Subrange Comparators 190 form the input to Data Encoding Logic 200. The logic translate the inputs into digital output representation of the voltage input V in . 
     Referring to FIG. 4. the process enabled by the circuitry is the sampling of the input voltage 300 and presenting it to the Coarse Comparators. The output of the Coarse Comparators are then decoded 310. This decoded information is used to set the switches that place the Embedded Coarse Subrange Comparators in their appropriate subrange of the voltage reference 320. The output of the Coarse Subrange Comparators and the Embedded Coarse Subrange Comparators are further decoded 330 and the switches set to connect the Fine Subrange Comparators to the appropriate region of the subrange of the voltage references 340. The outputs of the Coarse Subrange, the Embedded Coarse Subrange, and Fine Subrange Comparators are then encoded to form the digital output code of the circuitry 350. The next cycle of conversion will then be started. 
     Referring to FIG. 5 the range of the Voltage Reference Generator 100 is shown with two segments of the coarse subrange shown {V RM-1  -V RM  -V RM+1  }. If the output of comparators 120a and 120b have a digital value of 1 and comparator 120c has a digital value of 0 then the Embedded Coarse Subrange Comparators 130 will be placed in the range between V RM  and V Rm+1 . The output thermometer codes of the Embedded Coarse Subrange Comparators 130 determine the placement of the Fine Subrange Comparators 140. If the Embedded Coarse Subrange Comparators 130 are all zeroes 150a then the Fine Subrange Comparators will be placed at the lower section of the Voltage Reference Range and if it has a code as in 150b then the placement will be higher on the Voltage Reference Range. Each additional logical 1 to the code as in 150c and 150d will set the placement of the Fine Comparators at higher sections. 
     Referring to FIG. 6, the input analog signal will be sampled 502 at Clock 1 500. The Coarse Subrange Comparator Outputs will be latched during the second half of Clock 1 period 506. During Clock 1 period 505 the Embedded Coarse Subrange Comparators are decoded and the Fine Subrange Comparators are placed and their outputs are determined in Clock 2 period 510. During Clock 3 period 515, the codes of the Coarse, the Embedded Coarse Subrange, and Fine Comparators are encoded 526 and the valid data is on the Converter output during Clock 3 period 520. 
     Referring to FIG. 7 the preferred embodiment of the Voltage Reference Generator 100 of FIG. 3. is implemented as set of resistive elements r 1  600, r 11  622, r 12  626, r 2  630, r 21  632, r 22  636, r n  640, r n1  642, r n2  646 are connected to voltages Vrb 600 and Vrt 610 to form a voltage divider that establishes the plurality of voltage references for the Coarse Subrange Comparators 120 of FIG. 3 and the Embedded Subrange Comparators 130 of FIG. 3. Referring to FIG. 7., the Coarse Subrange Comparators 685 output codes form a set of thermometer codes 687 that are the inputs to the Switch Selection Logic 689. The outputs of the Switch Selection Logic 689 {S 1 , S 2 , . . . , S n  } 690 are uniquely selected to activate a single set of the switches S 11  652, S 12  656, S 13  658, or S 21  662, S 22  666, S 23  668, or . . . , or S n1  672, S n2  676, S n3  678. These switches connect the inputs 682,684,686 of the Embedded Coarse Subrange Comparator 680 to the Voltage References generated by the resistor divider network. For example if S 2  660 selected, then node X 21  661 would be connected to input m1 682, node X 22  665 would be connected to input m2 684, and node X 23  667 would be connected to input m3 686. 
     Referring to FIGS. 8a and 8b., an example of the preferred embodiment for the Fine Subrange Selection Logic and Switches is shown. The Voltage Reference Generator 1000 is comprised of a plurality of resistive elements r1 1030, r11 1032, r12 1034, r13 1036, r14 1038, r2 1040, r21 1042, r22 1044, r23 1046, r24 1048, r3 1050, r31 1052, r32 1054, r33 1056, r34 1056, r4 1060, r41 1062, r42 1054, r43 1066, r44 1068, r5 1070 connected in a series parallel network to form a voltage divider. The voltages formed at the connection of each resistor {V 1  1090, V 2  1092, V 3  1054, V 4  1096, V 5  1098} form the inputs to the Coarse Subrange Comparators 1100. The outputs of the Coarse Subrange Comparators 1100 is a set of thermometer codes 1110 that are the inputs to the Embedded Coarse Subrange Switch Selection Logic 1120. The output of the Embedded Coarse Subrange Switch Selection Logic 1120 activates the appropriate switch of the switches S 1  1231, S 2  1232, . . . , S 8  1238, S 9  1239, to chose the position within a coarse subrange of the Voltage Reference Generator 1000 to place the Embedded Coarse Subrange Comparators 1120. As an example if the analog input voltage Vain in FIG. 3., was larger than V 4  1096 and V 5  1098, but smaller than V 3  1094, V 2  1092, and V 1  1090, the thermometer code could be 00011. This would cause the output {S1, S2, . . . , Sn} 1140 of the Embedded Coarse Subrange Switch Selection Logic 1120 to activate switches S 5  1236, S 6  1236, and S 7  1237 and connect the voltages of the Voltage Reference Generator 1200 as inputs M 1 , M 2 , M 3  1230 to the Embedded Coarse Subrange Comparators 1200 are the set of thermometer codes that are input to the Combinatorial Logic 1210. The output of the Combinatorial Logic 1210 and the output of the Embedded Coarse Subrange Switch Selection Logic 1120 form the inputs to the Fine Subrange Switch Selection Logic 1130. To continue the example, if the Input Voltage Vain of FIG. 3. is larger than V 4  1096 and smaller than V 35  1095 and V 3  1094, then the Fine Subrange Switch Selection Logic 1300 would select line RF1 of the set of output lines {RF1, RF2, RF3, RF4} 1310. The RF1 line will activate switches S 71  1463, S 72  1464, S 81  1465, and S 82  1466 connecting voltages V 4  1096, V 43  1097a, V 45  1097b, and V 47  1097c, to the Fine Subrange Comparators. As the voltage input Vain of FIG. 3. changes, the Fine Subrange Switch Selection Logic 1300 will select the output of the set of outputs {RF1, RF2, RF3, RF4} 1310. The switches will be activated according to the patterns defined by RF1 1320, RF2 1330, RF3 1340, and RF4 1350. 
     Referring to FIG. 9. the output of the Coarse Subrange Comparators 1500 which forms the First Set of Thermometer Codes is the input to the Coarse Subrange Boundary Logic 1560, The Coarse Subrange Logic 1560 calculates the &#34;1&#34; to &#34;0&#34; boundary in the First Set of Thermometer Codes and then chooses one of a set of lines that will select the entry of the MSB Code Table 1600 that represents the coarse magnitude of the input analog voltage Vain in FIG. 3. The MSB Code 1620 is then one of the inputs to the Digital Output Word Assembly Logic 1640. The output of the Fine Subrange Comparators 1510 form the third thermometer codes which forms the input to the Fine Subrange Boundary Logic 1570. The Fine Subrange Boundary Logic 1570 calculates the &#34;1&#34; to &#34;0&#34; boundary of the Second Set of Thermometer Codes and then chooses one of a set of lines that will select the entry of the LSB Code Table 1610 that represents the fine adjustment of the magnitude of the input analog voltage Vain in FIG. 3. The LSB Code 1630 is then one of the inputs to the Digital Output Word Assembly Logic 1640. The Embedded Coarse Subrange Comparators forms the Second Thermometer Code 1550 which is a third input to the Digital Output Word Assembly Logic 1640. The MSB Code 1620, the LSB Code 1630. and the Second Thermometer Code 1550 are logically manipulated to form the Digital Output Word 1650 which represents the code for the magnitude of the input analog voltage Vain of FIG. 3.