Abstract:
A program method of a flash memory device having first and-second bitlines connected with a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The program method includes programming memory cells, connected to a selected row and first or second bitlines, with multi-bit data; and reprogramming programmed memory cells connected to a row disposed directly below the selected row and the first bitlines or the second bitlines, whereby increasing a read margin between adjacent states reduced due to high temperature stress (HTS).

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   Embodiments of the invention relate to a flash memory system. More particularly, embodiments of the invention relate to a flash memory system capable of compensating for reduced read margins between memory cell program states. 
   This U.S. non-provisional patent application claims priority under 35 U.S.C § 119 of Korean Patent Application 2006-07420 filed on Jan. 24, 2006, the entire contents of which are hereby incorporated by reference. 
   2. Discussion of Related Art 
   In recent years, storage devices such as volatile memory devices and non-volatile memory devices have been increasingly applied to MP3 players and mobile appliances such as, for example, portable multimedia players (PMPs), cellular phones, notebook computers, and personal digital assistances (PDAs). The MP3 players and the mobile appliances require mass storage devices for offering various functions (e.g., moving picture playback). Many efforts have been made for meeting the requirement. One of these efforts is to propose a multi-bit memory device where at least 2-bit data are stored in one memory cell. Exemplary multi-bit memory devices are disclosed, for example, in U.S. Pat. Nos. 6,122,188; 6,075,734; and 5,923,587 which are incorporated herein by reference. 
   When 1-bit data is stored in one memory cell, the memory cell has a threshold voltage belonging to one of two threshold voltage distributions, i.e., the memory cell has one of two states indicating data “0” and data “1”. On the other hand, when 2-bit data is stored in one memory cell, the memory cell has a threshold voltage belonging to one of four threshold voltage distributions, i.e., the memory cell has one of four states indicating data “11”, data “10”, data “00”, and data “01”. Threshold voltage distributions corresponding to four states are illustrated in  FIG. 1 . 
   Threshold voltage distributions corresponding to four states should be carefully controlled such that each of the threshold voltage distributions exists within a determined threshold voltage window. In order to achieve this, a programming method using an increment step pulse programming (ISPP) scheme has been suggested. In the ISPP scheme, a threshold voltage shifts by the increment of a program voltage according to the repetition of program loops. By setting the increment of a program voltage to a small value, threshold voltage distributions may be minutely controlled to secure a sufficient margin between states. Unfortunately, this leads to increase of time required for programming a memory cell to reach a desired state. Accordingly, the increment of the program voltage may be determined based on the programming time. 
   In spite of such an ISPP scheme, a threshold voltage distribution of each state is generated to be wider than a desired window due to various causes. For example, as indicated by dotted lines  10 ,  11 ,  12 , and  13  of  FIG. 1 , a threshold voltage distribution is widened due to a coupling between adjacent memory cells in a programming operation. Such a coupling is called an “electric field coupling” or “F-poly coupling”. For example, as illustrated in  FIG. 2 , assuming that a memory cell MCA is a cell programmed to have one of four states and a memory cell MCB is a cell programmed to have one of four states, charges are accumulated in a floating gate (FG) as the memory cell MCB is programmed. When memory cell MCB is programmed, a voltage of floating gate FG of adjacent memory cell MCA rises due to a coupling between floating gates FG of the memory cells MCA and MCB. The rising threshold voltage is maintained due to a coupling between floating gates even after programming memory cell MCB. The memory cell MCB includes memory cells arranged in a wordline direction and/or a bitline direction relative to the memory cell MCA. Due to such a coupling, the threshold voltage of the programmed memory cell MCA rises and the threshold voltage distributions are widened as indicated by the dotted lines  10 ,  11 ,  12 , and  12  of  FIG. 1 . Accordingly, a margin between states is reduced, as illustrated in  FIG. 1  which is a reduction of the read margin (difference in voltage in determining the presence of a “1” or a “0”). 
   One conventional technique for preventing a threshold voltage distribution from being widened due to a coupling is disclosed in U.S. Pat. No. 5,867,429. 
   Not only an electric field coupling/F-poly coupling but also a read margin between states is reduced as threshold voltages of memory cells drop with the lapse of time, which will be hereinafter referred to as “hot temperature stress (HTS)”. HTS means that charges accumulated in a floating gate of a memory cell are drained to a substrate. As the charges of the floating gate are reduced, threshold voltages of memory cells in respective states drop, as indicated by dotted lines  20 ,  21 , and  22  of  FIG. 3 . Accordingly, a threshold voltage increases due to an electric field coupling/F-poly coupling and a threshold voltage decreases due to HTS which makes it difficult to secure a read margin between states. In particular, it is difficult to know a state of the programmed memory cell. This problem becomes severe with the recent trend toward more complex semiconductor fabrication processes. 
   Accordingly, there is a need for securing a read margin between states even if a threshold voltage increases due to an electric field coupling/F-poly coupling and a threshold voltage decreases due to HTS. 
   SUMMARY OF THE INVENTION 
   Exemplary embodiments of the present invention are directed to a program method of a flash memory device having first and second bitlines connected with a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. In exemplary embodiment, the program method may include programming memory cells, connected to a selected row and first or second bitlines, with multi-bit data; and reprogramming programmed memory cells connected to a row disposed directly below the selected row and the first bitlines or the second bitlines, whereby increasing a read margin between adjacent states reduced due to high temperature stress (HTS). 
   In another exemplary embodiment, the program method may include programming memory cells, connected to a selected row and the first bitlines, with multi-bit data and reprogramming programmed memory cells connected to a row disposed directly below the selected row and the first bitlines, wherein the reprogramming increases a read margin between adjacent states of the plurality of states where a threshold voltage associated with the memory cells was decreased due to high temperature stress (HTS). 
   In another exemplary embodiment, the program method may include programming memory cells, connected to a selected wordline and the second bitlines, with multi-bit data and reprogramming programmed memory cells connected to a row disposed directly below the selected row and the first bitlines, wherein the reprogramming increases a read margin between adjacent states of the plurality of states where a threshold voltage associated with the memory cells was decreased due to high temperature stress (HTS). 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  illustrates that threshold voltage distributions are widened due to an electric field coupling/F-poly coupling. 
       FIG. 2  illustrates an electric field coupling/F-poly coupling generated between memory cells. 
       FIG. 3  illustrates that threshold voltage distributions are widened due to high temperature stress (HTS). 
       FIG. 4  is a block diagram of a flash memory device according to the present invention. 
       FIG. 5  is a circuit diagram of a memory cell array illustrated in  FIG. 4 . 
       FIG. 6A  and  FIG. 6B  illustrate a multi-bit program operation according to the present invention. 
       FIG. 7  is a flowchart illustrating a program method of a flash memory device according to an embodiment of the present invention. 
       FIGS. 8A and 8B  are flowcharts illustrating a secondary program method illustrated in  FIG. 7 . 
       FIG. 9  illustrates verify voltages when a program operation of a flash memory device according to the present invention is executed. 
       FIG. 10  illustrates threshold voltage distributions after executing a program operation of a flash memory device according to the present invention. 
       FIG. 11  and  FIG. 12  are flowcharts illustrating program methods of flash memory devices according to alternative embodiments of the present invention. 
   

   DESCRIPTION OF EMBODIMENTS 
   The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention, however, may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, like numbers refer to like elements throughout. 
     FIG. 4  is a block diagram of a flash memory device according to an embodiment of the present invention which comprises a memory cell array  100  for storing data information. The memory cell array  100  includes a plurality of memory blocks each having a memory cell configuration illustrated in  FIG. 5 . 
     FIG. 5  is a circuit diagram of the memory cell array illustrated in  FIG. 4  comprising a memory block MB which includes a plurality of strings  101  each having a string select transistor SST, a ground select transistor GST, and memory cells MC 31 -MC 0 . The string selection transistor SST is controlled by a string select line SSL and has a drain connected to a corresponding bitline. The memory cells MC 31 -MC 0  are serially coupled between a source of the string select transistor SST and a drain of the ground select transistor GST and controlled by corresponding wordlines WL 31 -WL 0 , respectively. It will be understood by those skilled in the art that the number of wordlines is not limited thereto. Each memory cell will be comprised of a floating gate transistor. 
   Returning to  FIG. 4 , a row selector circuit (X-SEL)  100  is controlled by control logic  150 . The row selector circuit  100  selects one of the memory blocks in response to an address ADD provided through an input/output (I/O) interface  140  which controls rows (including wordlines and select lines) of the selected memory block. A register block  120  is controlled by the control logic  150  and functions as a sense amplifier or a write driver according to an operation mode. Although not illustrated in this figure, the register block  120  may be comprised of page buffers. Each of the page buffers is electrically connected to one bitline or one of a pair of bitlines and reads data from a memory cell or stores data in the memory cell through a bitline. 
   A column selector circuit (Y-SEL)  130  is controlled by control logic  150  and outputs data stored in register block  120  to I/O interface  140  or control logic  150  in response to the address ADD provided through I/O interface  140 . For example, in a normal read operation, column selector circuit  130  outputs data stored in register block  120  to I/O interface  140 . In a verify normal read operation, column selector circuit  130  outputs data stored in register block  120  to control logic  150  and control logic  150  judges whether the data provided from column selector circuit  130  is pass data. During a data loading period of a program operation, the selector circuit  130  outputs program data transferred through I/O interface  140  to register block  120 . The control logic  150  is configured to control general operations of the flash memory device. A voltage generator  160  is controlled by control logic  150  and configured to generate voltages (e.g., a wordline voltage, a bulk voltage, a read voltage, a pass voltage, etc.) required for program/erase/read operations. 
   As described below, a flash memory device according to an aspect of the invention adopts a novel program technology for sufficiently securing a read margin between states even if memory cells are subjected to an electric field coupling/F-poly coupling and HTS. In accordance with the programming of the present invention, 2-bit data is stored in respective memory cells of a selected page so that memory cells are programmed using target threshold voltages of respective desired states. This is hereinafter referred to as a “primary program operation”. After the primary program operation is completed, read operations are executed to detect memory cells arranged within a predetermined threshold voltage region among the memory cells of the respective states. The detected memory cells are programmed to have a higher threshold voltage than target threshold voltages of the respective states. This is hereinafter referred to as a “secondary program operation”. 
   The primary program operation for storing 2-bit data varies with the configuration of the register block  120 . For example, after loading both LSB and MSB data bits on the register block  120 , the primary program operation may be executed. Alternatively, programming MSB data bit (hereinafter referred to as “MSB program operation”) may be followed by programming LSB data bit (hereinafter referred to as “LSB program operation”). The latter program method, as an exemplary program method, will now be described in brief with reference to  FIG. 6A  and  FIG. 6B . 
   One memory cell is programmed to have one of “11”, “10”, “00”, and “01” states. For the convenience of description, it is assumed that the “11”, “10”, “00”, and “01” states correspond to ST 0 , ST 1 , ST 2 , and ST 3 , respectively. A memory cell having the “11” state is an erased memory cell and a threshold voltage of a memory cell having the “10” state is higher than that of the memory cell having the “11” state. A threshold voltage of a memory cell having the “00” state is higher than that of a memory cell having the “10” state. Further, a threshold voltage of a memory cell having the “01” state is higher than that of a memory cell having the “00” state. If an LSB program operation is executed under the foregoing condition, a memory cell has an erased state or a “10” state, as illustrated in  FIG. 6A . If an MSB program operation is executed following the LSB program operation, a memory cell having the “11” state has an erased state or a “01” state while a memory cell having the “10” state has a “10” or “00” state, as illustrated in  FIG. 6B . 
   In the present invention, two program operations are executed when any wordline is selected. More specifically, a program operation for memory cells connected to the selected wordline and even-number bitlines BLe 0 -BLe(n- 1 ) is followed by a program operation for memory cells connected to the selected wordline and odd-number bitlines BLo 0 -BLo(n- 1 ). For the convenience of description, a program operation according to the invention will be described according to the above order. However, it will be understood by those skilled in the art that a program operation for memory cells connected to the selected wordline and odd-number bitlines BLo 0 -BLo(n- 1 ) may be followed by a program operation for memory cells connected to the selected wordline and even-number bitlines BLe 0 -BLe(n- 1 ). 
     FIG. 7  is a flowchart illustrating a programming method of a flash memory device in accordance with an embodiment of the present invention. When a program operation starts, control logic  150  determines, in step S 100 , whether even-number bitlines BLe 0 -BLe(n- 1 ) on a wordline (e.g., Nth wordline) are selected. This determination is done based on address information provided through I/O interface  140 . When the even-number bitlines BLe 0 -BLe(n- 1 ) are selected, the primary program operation for memory cells connected with the selected wordline WLn and the even-number bitlines BLe 0 -BLe(n- 1 ) is executed by control logic  150  at step S 110 . The primary program operation is executed according to the program method described with reference to  FIG. 6A  and  FIG. 6B . While the primary program operation is executed, the selected memory cells are programmed to one of states ST 1 , ST 2 , and ST 3  shown in  FIG. 9 , respectively. Based on verify voltages Vvfy 11 , Vvfy 12 , and Vvfy 13  corresponding to the states ST 1 , ST 2 , and ST 3 , it is determined whether the memory cells are programmed to the respective states. For example, the verify voltage Vvfy 11  is used to determine whether a memory cell is programmed to the state ST 1 ; the verify voltage Vvfy 12  is used to determine whether a memory cell is programmed to the state ST 2 ; and the verify voltage Vvfy 13  is used to determine whether a memory cell is programmed to the state ST 3 . Once these states are verified the primary program procedure ends. 
   When the odd-number bitlines BLo 0 -BLo(n- 1 ) are selected, as determined at step S 100 , the primary program operation for memory cells connected with the selected wordline WLn and the odd-number bitlines BLo 0 -BLo(n- 1 ) is executed by control logic  150  at step S 120 . The primary program operation is executed as described above. Once the program operation for a wordline WL(n- 1 ) connected with the selected wordline WLn and odd-number bitlines BLo 0 -BLo(n- 1 ) ends, a program operation (i.e., secondary program operation) for the wordline WL(n- 1 ) disposed directly below the selected wordline WLn is executed at step S 140 . First, a secondary program operation (or reprogram operation) is executed for memory cells connected with the wordline WL(n- 1 ) and even-number bitlines BLe 0 -BLe(n- 1 ) at step S 160 . Thereafter, a secondary program operation (or reprogram operation) is executed for memory cells connected with the wordline WL(n- 1 ) and the odd-number bitlines BLo 0 -BLo(n- 1 ) at step S 180 . As will be described later, memory cells arranged within a predetermined region among threshold voltage regions of the respective states are reprogrammed by the secondary program operation to have a higher threshold voltage. Unlike the description with reference to  FIG. 7 , the secondary program operation for memory cells connected with the wordline WL(n- 1 ) and the odd-number bitlines BLo 0 -BLo(n- 1 ) may be followed by the secondary program operation for memory cells connected with the wordline WL(n- 1 ) and the even-number bitlines BLe 0 -BLe(n- 1 ). 
     FIG. 8  is a flowchart illustrating the secondary program operation of a flash memory device in accordance with the present invention.  FIG. 9  illustrates the verify voltages when executing a program operation of the flash memory device according to the present invention. 
   As described with reference to  FIG. 7 , after a first program operation for 2-bit data is ended and a currently selected wordline WLn is not the last wordline, a secondary program operation is executed for memory cells connected with a wordline WL(n- 1 ) disposed directly below the selected wordline WLn. Now, a secondary program operation for programmed memory cells connected with a wordline WL(n- 1 ) and even-number bitlines BLo 0 -BLo(n- 1 ) will be described below. 
   While a verify voltage Vvfy 11  (or read voltage Vread 1 ) is applied to a selected wordline WL(n- 1 ), a read operation is executed through register block  120  at step S 200  shown in  FIG. 8A . Thereafter, while a verify voltage Vvfy 12 , higher than the verify voltage Vvfy 11 , is applied to the selected wordline WL(n- 1 ), a read operation is executed through register block  120  at step S 210 . By executing the read operation twice, memory cells having threshold voltages between verify voltages Vvfy 11  and Vvfy 12  (or a read voltage Vread 1  and the verify voltage Vvfy 12 ) (see  FIG. 9 ) are detected. It will be understood by those skilled in the art that the method of detecting memory cells having threshold voltages between verify voltages Vvfy 11  and Vvfy 12  (or a read voltage Vread 1  and the verify voltage Vvfy 12 ) may vary with the configuration of the register block  120 . 
   If the memory cells having the threshold voltages between the verify voltages Vvfy 11  and Vvfy 12  (or the read voltage Vread 1  and the verify voltage Vvfy 12 ) are detected, a program operation (i.e., secondary program operation) is executed to the detected memory cells at step S 220 . After the program operation is executed, a verify read operation is executed while the verify voltage Vvfy 12  acting as a read voltage is applied to the selected wordline WL(n- 1 ) at step S 230 . It is determined whether the detected memory cells are programmed to have a threshold voltage corresponding to the verify voltage Vvfy 12  at step S 240 . A determination is made at step S 240  whether the detected memory cells are not programmed with a required threshold voltage, a program voltage to be applied to the selected wordline WL(n- 1 ) increases by a predetermined increment at step S 250  and the routine returns to step S 220 . The program loop from step S 220  to step S 250  repeats either a predetermined number of times or until all detected memory cells are programmed. 
   When the determination result is that all the detected memory cells are programmed with a required threshold voltage, the answer to step S 240  is yes and the program proceeds to step S 260  where a read operation is executed through register block  120  while a verify voltage Vvfy 21  (or a read voltage Vread 2 ) is applied to the selected wordline WN(n- 1 ). Thereafter, a read operation is executed through register block  120  while a verify voltage vfy 22  higher than the verify voltage Vvfy 21  is applied to the selected wordline WL(n- 1 ) at step S 270 . By executing the read operation twice at steps S 260  and S 270 , memory cells having threshold voltages between the verify voltages Vvfy 21  and Vvfy 22  (or the read voltage Vread 2  and the verify voltage Vvfy 22 ) (see  FIG. 9 ) are detected. If the memory cells having threshold voltages between the verify voltages Vvfy 21  and Vvfy 22  (or the read voltage Vread 2  and the verify voltage Vvfy 22 ) (see  FIG. 9 ) are detected, a program operation (i.e., secondary program operation) is executed for the detected memory cells at step S 280 . After the program operation is executed, step S 290  executes, a verify read operation is executed while the verify voltage Vvfy 22  acting as a read voltage is applied to the selected wordline WL(n- 1 ) at step S 290 . A determination is made at step S 300 , whether the detected memory cells are programmed to have a threshold voltage corresponding to the verify voltage Vvfy 22 . When the determination result is that all the detected memory cells are not programmed with a required threshold voltage, a program voltage to be applied to a selected wordline increases by a predetermined increment (S 310 ). This routine returns to step S 280 , which is repeated until the program loop comprising the S 280 -S 310  runs a predetermined number of times or the memory cells are all programmed with the required threshold voltage. 
   When the determination result is that all the detected memory cells are programmed with a required threshold voltage, a read operation is executed at step S 320  through register block  120  while a verify voltage Vvfy 31  (or a read voltage Vread 3 ) is applied to the selected wordline WL(n- 1 ) at step S 320 . Thereafter, a read operation is executed through register block  120  while a verify voltage Vvfy 32  higher than the verify voltage Vvfy 31  is applied to the selected wordline WL(n- 1 ) (S 330 ). By executing the read operation twice at steps S 320  and S 330 , memory cells having threshold voltages between the verify voltages Vvfy 31  and Vvfy 32  (or the read voltage Vread 3  and the verify voltage Vvfy 32 ) (see  FIG. 9 ) are detected. If the memory cells having threshold voltages between the verify voltages Vvfy 31  and Vvfy 32  (or the read voltage Vread 3  and the verify voltage Vvfy 32 ) (see  FIG. 9 ) are detected, step S 340  executes a program operation (i.e., secondary program operation) for the detected memory cells. After the program operation executes, a verify read operation is executed while the verify voltage Vvfy 32  acting as a read voltage is applied to the selected wordline WL(n- 1 ) at step S 350 . A determination is made at step S 360  whether the detected memory cells are programmed to have a threshold voltage corresponding to the verify voltage Vvfy 32 . When the determination result is that all the detected memory cells are not programmed with a required threshold voltage, step S 370  increases a program voltage to a selected wordline by a predetermined increment. This routine proceeds to step S 340 , which is repeated until the program loop defined by steps S 340 -S 370  are repeated a predetermined number of times or the memory cells are all programmed. 
   When the determination result is that all the detected memory cells are programmed with the required threshold voltage, a secondary program operation is executed for programmed memory cells connected with the wordline WL(n- 1 ) and odd-number bitlines BLo 0 -BLo(n- 1 ), as illustrated in  FIG. 7 . This secondary program operation is identical to that described above. 
     FIG. 10  illustrates threshold voltage distributions after executing a program operation of a flash memory device according to the present invention. In a threshold voltage distribution corresponding to a state ST 1 , memory cells between verify voltages Vvfy 11  and Vvfy 12  (or a read voltage Vread 1  and the verify voltage Vvfy 12 ) are programmed to have the verify voltage Vvfy 12  or a voltage higher than the verify voltage Vvfy 12 . As can be seen in  FIG. 10  and  FIG. 3 , a margin between states ST 0  and ST 1  increases. In a threshold voltage corresponding to a state ST 2 , verify voltages Vvfy 21  and Vvfy 22  (or a read voltage Vread 2  and the verify voltage Vvfy 22 ) are programmed to have the verify voltage Vvfy 22  or a voltage higher than the verify voltage Vvfy 22 . As can be seen in  FIG. 10  and  FIG. 3 , a margin between states ST 1  and ST 2  increases. Similarly, in a threshold voltage distribution corresponding to a state ST 3 , memory cells between verify voltages Vvyf 31  and Vvfy 32  (or read and verify voltages Vread 3  and Vvfy 32 ) are programmed to have the verify voltage Vvfy 32  or a voltage higher than the verify voltage Vvfy 32 . As can be seen in  FIG. 9  and  FIG. 3 , a margin between states ST 2  and ST 3  increases. Namely, a read margin between adjacent states more increases more than a read margin illustrated in  FIG. 3 . Thus, although a threshold voltage distribution is widened due to an electric field coupling/F-poly coupling and HTS, a read margin between adjacent states may be sufficiently secured using the program method according to the present invention. 
   The secondary program operation is not limited to the embodiment of the present invention and many modifications and changes thereof may be made. For example, states ST 1 , ST 2 , and ST 3  may be programmed simultaneously during a second program operation. Alternatively, a part of the states ST 1 , ST 2 , and ST 3  may be programmed simultaneously/individually. 
     FIG. 11  is a flowchart illustrating a program method of a flash memory device according to another embodiment of the present invention. It is assumed that execution of a program operation for memory cells connected with even-number bitlines BLe 0 -BLe(n- 1 ) belonging to a selected wordline (e.g., WLn) is required. Under this assumption, a primary program operation is executed for the memory cells connected with the selected wordline WLn and the even-number bitlines BLe 0 -BLe(n- 1 ), as illustrated in  FIG. 11  at steo S 400 . The primary program operation is executed using the same method as described above. Afterwards, a secondary program operation is executed for programmed memory cells connected to a wordline WL(n- 10  disposed directly below the selected wordline WLn and the even-number bitlines BLe 0 -BLe(n- 1 ) at step S 420 . The secondary program operation is executed using the same method as described above. If the second program operation is completed, the program procedure ends. 
     FIG. 12  is a flowchart illustrating a program method of a flash memory device in accordance with another embodiment of the present invention. It is assumed that execution of a program operation for memory cells connected with odd-number bitlines BLo 0 -BLo(n- 1 ) belonging to a selected wordline (e.g., WLn) is required. Under this assumption, the primary program operation is executed for the memory cells connected with the selected wordline WLn and the odd-number bitlines BLo 0 -BLo(n- 1 ), as illustrated in  FIG. 12  at step S 500 . The primary program operation is executed using the same method as described above. The secondary program operation is then executed for programmed memory cells connected to a wordline WL(n- 10  disposed directly below the selected wordline WLn and the odd-number bitlines BLo 0 -BLo(n- 1 ) at step S 520 . The secondary program operation is executed using the same method as described above. If the second program operation is completed, the program procedure ends. 
   In  FIG. 11  and  FIG. 12 , after executing primary and secondary program operations for even-number bitlines, primary and secondary program operations for odd-number bitlines are executed. According to the present invention, voltages required for reading data of programmed memory cells are set to the same value as read voltages used to execute only a primary program operation. 
   In a flash memory device according to the present invention, each of the memory cells connected with a selected wordline stores 2-bit data. The stored 2-bit data may comprise LSB page data and MSB page data which means that two-page data are stored in the memory cells connected with even/odd-number bitlines. Alternatively, 2-bit data stored in each memory cell may comprise one-page data which means that one-page data is stored in the memory cells connected with even/odd-number bitlines. 
   After being subjected to a primary program operation, memory cells arranged within a specific region of respective states are subjected to a secondary program operation to have a threshold voltage equivalent to or higher than a verify voltage of the primary program operation. Thus,.although a threshold voltage distribution is widened due to an electric field coupling/F-poly coupling and HTS, a read margin between adjacent states may be sufficiently secured using the program method according to the present invention. 
   Although the present invention has been described in connection with the embodiment of the present invention illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those skilled in the art that various substitution, modifications and changes may be thereto without departing from the scope and spirit of the invention.