Abstract:
A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input ( 60, 62 ) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.

Description:
[0001]    This is a division of U.S. Ser. No. 10/973,365 filed Oct. 26, 2004. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to computer processors including dynamic hardware logic. In particular, it relates to a method and respective system for operating a digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage. 
         [0004]    2. Description and Disadvantages of Prior Art 
         [0005]    It is a general task for microprocessor development to make computing increasingly faster from one microprocessor generation to the next one. Additionally, there is quite a large sector of computing devices, wherein a second requirement is basically rated equally important to the computing performance, which is a low power consumption. This is specifically true for all portable devices, as for example notebooks, mobile phones, FDA devices, etc. 
         [0006]    Adder circuits, to which the present invention is focused, occupy a critical path in many areas of microprocessor operation. Their important role for microprocessor operation is due to the fact that adder devices are present in microprocessor operation in order to operate ADD/SUB units in arithmetic logic units, for memory address generation and for floating point calculations. Thus, it is key to the cycle time, to reach a minimum delay for those adder units. In particular in CMOS hardware logic the microprocessor implementing such adder units can be clocked very high and further architectural efforts can be undertaken, in order to reach said minimum time delay and thus to increase processing speed. But by virtue of the before-mentioned second requirement, a reduced power consumption, it is worth while thinking about a useful compromise between performance and power consumption. This is specifically true when developing adder architecture as they play an important role, as stated above, and because the add operation per se is a very complicated and time-consuming operation, compared to other operations, due to the enormous carry network of an adder device. The key role for adders is even more increasing, the more important larger address spaces are needed and the longer operands are, compared, for example, to 16-bit operands to be added with two 64-bit operands to be added. The computing time needed for the 64-bit operands is basically 30% higher. 
         [0007]    with reference back to the task of finding a good compromise between performance and power consumption so-called static CMOS logic in 64-bit ADD/SUB units can reach a delay of about 10 FO4 at some moderate power consumption. With dynamic CMOS logic the same adder can achieve a delay (latency) of about 6 fanout of 4 (FO4) inverter delays, but at about 4 times the power consumption of the above-mentioned static solution. This is specifically true for the so-called DOMINO-TYPE dynamic logic. 
         [0008]    In prior art adder architecture the developers of adder units decide if the adder should be implemented in static logic or in dynamic logic. A static adder is slower but needs less power, whereas a dynamic adder unit is quicker, but has significantly higher power consumption. Thus, disadvantageously, prior art does not offer to find a good compromise between power consumption and adder speed other than by reducing speed in order to obtain a moderate power consumption. 
         [0009]    A promising approach to combine static logic with dynamic logic was offered by R. Montoye et. al., “A Double precision Floating Point Multiply”, ISSCC 2003, Vol. 46, pp. 336, Digest of technical papers, Visuals Supplement, pp. 270. 
         [0010]    In this publication a first trial is offered to implement a latch at particular locations, in order to avoid the regular switching frequency to be expected in dynamic logic and thus to save power by avoiding some power consumption due to precharging the precharge nodes necessary in each cycle. 
         [0011]    With reference to  FIG. 1  (prior art), the precharge problem of prior art is shortly described next below, as it stands in a close context to the intentional approach disclosed in here. 
         [0012]    In prior art it is known to apply so-called “keeper-devices” and/or “bleeder-devices”, which try to supply charge to a precharge node temporarily or continuously, respectively. This reduces the voltage drop caused by charge sharing, but also slows down the switching of the circuit. Keeper and Bleeder devices charge the precharge node, which slows down the discharge of this node in case the logical function forces a discharge said node. 
         [0013]    In particular, in  FIG. 1  the node  40  is the above-mentioned precharge node. During the so-called reset phase it is precharged to a certain voltage level, e.g. the supply voltage Vdd. This is done by the control of the reset transistor  12 , which when switched to “pass”, connects the precharge node to the voltage source Vdd. 
         [0014]    During the evaluation phase of the circuit, when some input setting is connected to the control inputs of the NFETs controlled by the input lines A i , and B i , these transistors remove this charge to ground, if the logic condition as defined by the value of the logic input variables A, B turns “ON”, ie, to pass mode, all transistors on the path depicted between the precharged node  40  and ground terminal. If only a part of said transistors are turned “ON” without opening up a connection between the precharged node and ground, then the node has to keep its charge but must share its charge with those active transistors. 
         [0015]    Thus, basically the bleeder device  46  and a foot transistor device, which is not depicted in  FIG. 1 , but which resides at the “foot” of each transistor stack (the vertical paths in  FIG. 1 ) cooperate, in order to provide a proper precharging independent of the actual input setting of the evaluation transistor stacks. 
         [0016]    The promising approach according to above mentioned “Montoye et al.”, however, can not be transferred to 4-bit carry groups (or more) of adder units, because of the general, architectural constraint, to limit the evaluation transistor stacks of N-FET devices to a maximum number of 4 including said above mentioned foot transistor device, as the stacks would have at least 5 transistors in at least some paths of the carry network of the adder. 
         [0017]    Thus, this hopeful approach could maybe used for 2-bit carry groups of adders, but not for 4-bit groups, which leads to a very limited applicability of this prior art static/dynamic logic combination. 
       OBJECTS OF THE INVENTION 
       [0018]    It is thus an objective of the present invention to provide an adder unit, which is able to implement a better compromise between power consumption and processing speed. 
       SUMMARY AND ADVANTAGES OF THE INVENTION 
       [0019]    The objective of the invention is achieved by the features stated in enclosed independent claims. Further advantageous arrangements and embodiments of the invention are set forth in the respective subclaims. Reference should now be made to the appended claims. 
         [0020]    According to the broadest aspect of the invention, a method is disclosed for operating a digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage, which is characterized by the steps of:
   a) operating at least one logic stage of relatively high switching activity implemented in static hardware logic and at least one logic stage of relatively low switching activity implemented in dynamic hardware logic,   b) operating a predetermined stage with an input directly obtained from a stage being positioned earlier than a preceding bypass stage preceding said predetermined stage, in order to avoid input from said earlier stage into said bypass stage.   
 
         [0023]    As each switching activity requires a subsequent precharge of the dynamic input node of respective dynamic hardware logic subcircuits, this enables for remarkable power reduction of the adder circuit at remarkably increased adder speed. 
         [0024]    When this basic method further comprises the step of:
   operating 4-bit groups of subsequent bit positions in the operands bit representation separately in a respective dedicated subcircuit, in which a footing device is used for enabling for efficient precharging of said dynamic hardware logic, wherein said 4-bit groups subcircuits are implemented in dynamic hardware logic using a parallel switching of stacks of CMOS N-FET transistors, wherein said stacks include a maximum of four stack members switched in series, wherein a stack member may be implemented as a single N-FET transistors or a parallel switching of at least two N-FET transistors, then this adjusts the inventional concept to the general technology convention, not to use higher stacks in said single dynamic hardware logic subcircuits than having a maximum of four members switched in series.   
 
         [0026]    When this basic method further comprises the step of:
   operating a latch at the output of said bypass stage for driving a subsequent stage, then a protection against crosstalk is provided.   
 
         [0028]    According to an inventive principle, which is reflected in the claims, in the adder unit improved by the present invention, a combination of static hardware logic and dynamic hardware logic is implemented in an adder structure, which was already known from former ECL logic, namely the LING adder structure in a slight modification. As a person skilled in the art will appreciate the LING adder structure being based on the LING formula as described below can now be used for the objective underlying the present invention with some inventional adjustment reflecting the particular implementation difficulties in stage  2  of the total of 4 stages of the LING adder structure. First, the LING formula for the output of the 4 adder stages H 1 , H 2 , H 3  and H 4  of a LING adder structure implemented as a 4-bit adder having i=0 as most significant bit (MSB) is as follows: 
         [0000]        H   i   =G   i   +G   i+1   *P   i+1   +G   i+2   *P   i+1   *P   i+2   +G   i+3   *P   i+1   *P   i+2   *P   i+3   (1) 
         [0000]        G   i   =A   i   *B   i   (2A) 
         [0000]        P   i   =A   i   +B   i   (2B) 
         [0000]        H 4 =A 0 *B 0 +A 1 *B 1*( A 1 +B 1)+ A 2 *B 2*( A 1 +B 1)+ A 3 *B 3*( A 2 +B 2)*( A 1 +B 1)  (3) 
         [0029]    According to a basic approach of the present invention, beyond said combination between dynamic and static logic an inventional adder circuit is characterised by implementing the above formula modified in a particular way, which results in a simplification of H 2  formula. In particular, the H 1  output produced in stage  1  is not fed to stage  2 , as it would be suggested by applying prior art, but instead it is directly fed to the input of stage  3  and thus bypassing stage  2  of the carry network of the LING adder. 
         [0030]    A preferred embodiment of the invention in form of a 64-bit adder device being composed of 4 logic stages in the carry generation logic comprises further advantageously so-called LSDL latches, see for reference “J. Silbermann, et al., “A 1.0 GHz Single-Issue 64-Bit Power PC Integer Processor,” IEEE J. of Solid State Circuits, Vol. 33, No. 11, November 1998”, which are incorporated to reduce further the switching activities due to precharging, as it was mentioned above. This further advantageous feature is based on the following consideration: 
         [0031]    A latch changes its state only if the input signal switches. The first two logic stages of the adder according to LING count for about 44.8% of the logic gates of the complete adder, and about 57% of the carry logic only which may correspond to a number of 59 500 transistors having a width in the micrometer range. Stages  3  and  4  count for 44 200 transistors and stage  5  for 28 941 transistors including the result latch. Due to this distribution stage  1  and stage  2  will cause the most power consumption, when implemented in dynamic logic. Thus, it is worthwhile selecting either stage  1  or stage  2  to be implemented in static logic in order to reduce the switching activity compared to a fully dynamic adder. As it will be seen later, a preferred embodiment of the present invention implements stage  1  in static hardware and stage  2 ,  3 ,  4  and  5 , which composes the sum, in dynamic hardware logic. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0032]    The present invention is illustrated by way of example and is not limited by the shape of the figures of the drawings in which: 
           [0033]      FIG. 1  is a schematic circuit diagram illustrating a H 4 -gate according to the above-given LING formula and representing prior art; 
           [0034]      FIG. 2  is a schematic circuit diagram illustrating the H 1 -gate of stage  1  of an adder circuit according to a particular, preferred embodiment of the present invention; 
           [0035]      FIG. 3  illustrates the I 1 -gate of stage  1 , 
           [0036]      FIG. 4A  illustrates the H 2 -gate for stage  2 ; 
           [0037]      FIG. 4B  illustrates the H 2 -gate for stage  2  with an LSDL latch according to a specific inventional feature; 
           [0038]      FIG. 5A  illustrates the I 2 -gate of stage  2 ; 
           [0039]      FIG. 5B  illustrates the I 2 -gate of stage  2  with an LSDL latch according to a specific inventional feature; 
           [0040]      FIG. 6  illustrates the H 3 -gate of stage  3 ; 
           [0041]      FIG. 7  illustrates the H 4 -gate of stage  4 , wherein  FIGS. 2 to 7  all referred to the same, preferred embodiment, 
           [0042]      FIG. 8A  is a table-like representation of the logic functions for generating the carries for an inventional 64-bit adder device; 
           [0043]      FIG. 8B  is a continuation of  FIG. 8A , 
           [0044]      FIG. 9A  is a schematic representation of a so-called parallel prefix graph of the first two levels of the inventional adder structure according to a specific embodiment thereof; and 
           [0045]      FIG. 9B  is a continuation of  FIG. 9A . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0046]    In the preferred embodiment described next with reference to  FIGS. 2 to 7  the 4 stages of the carry generation path are described with a formula for H 1   i , I 1   i , H 2   i , I 2   i , H 3   i , I 3   i  and H 4   i , I 4   i  according to the LING formula given above, but modified according to the invention. In this preferred embodiment an inverter is implemented at the output of each stage. 
         [0047]    Next, some formulae will be introduced. As a legend therefore, the following is valid:
   + means a logic OR,   no operator between variables, e.g. A, B, I and H, means a logic AND between them,   the variables I, H, etc. are written with indices ij, such that   Iij (i=1, 2, 3, 4 j=is a bitindex from 0 to 64)   and Hij (i=1, 2, 3, 4 i=bitindex 0 bis 64).   
 
         [0053]    With particular reference to  FIG. 2  the formula (4A) for stage  1  is implemented in a AOI-gate: 
         [0000]        H 1 i =    g   i +g   i+1 =    A   i   B   i   +A   i+1   B   i+1     (4A) 
         [0054]    The input variables A 0 , A 1  and B 0 , B 1  are switched according to above-formula 4A, and H 1  results at the output of the circuit as: H 1 =not (A 0 *B 0 +A 1 *B 1 ). 
         [0055]    According to this preferred embodiment this first stage is implemented in static CMOS logic. 
         [0056]    With reference to  FIG. 3  the I 1 -gate of stage  1  implements the formula 4B: 
         [0000]        I 1 i =    p   i−1   p     i =(    A   i−1 +B i−1 )( A   i   +B   i       A   i−1 +B i−1 )( A   i   +B   i   )  (4B) 
         [0057]    This OAI (OR-AND-Inverted) implements I 1 =not ((A 0 +B 0 ) (A 1 +B 1 )), also in static logic. 
         [0058]    With further reference to  FIG. 4  the H 2 -gate for stage  2  is implemented according to the formula 5A: 
         [0000]        H 2 i =    H 1 i   +H 1 i+2   I 1 i+1   +H 1 i+4   I 1 i+1   I 1 i+3   +H 1 i+6   I 1 i+1   I 1 i+3   I 1 i+5     (5A) 
         [0059]    With reference to  FIG. 5  the I 2 -gate of stage  2  is implemented according to the formula 5B: 
         [0000]        I 2 i =    I 1 i   +I 1 i+2   +I 1 i+4   +I 1 i+6     (5B) 
         [0060]    The stage  2  is implemented as a complex dynamic logic of the DOMINO-TYPS with a LSDL latch ( 4 ) generating H 2 . 
         [0061]    As the output signals from the previous stage  1  are inverted, the inverted signals have to be used in the formula (5A′): 
         [0000]    
       
         
           
             
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         [0062]    after some modification you get: 
         [0000]        H 2 i   =H 1 i   I 1 i+1   +H 1 i   H 1 i+2   I 1 i+3   +H 1 i   H 1 i+2   H 1 i+4   I 1 i+5   +H 1 i   H 1 i+2   H 1 i+4   H 1 i+6   
         [0063]    As the output signals from the previous stage  1  are inverted, the inverted signals have to be used in the formula (5B′): 
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         [0064]    According to the above-mentioned inventional feature to reduce the complexity of stage  2  and to increase the stability of the circuit for H 2  the function is reduced by the term H 1   i  to the following function and the H 1   i -term is carried from stage  1  directly to stage  3 . This function is given by the following formula 5A″: 
         [0000]    
       
         
           
             
               
                 
                   
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         [0065]    A preferred implementation thereof is given in  FIGS. 4A  and B, without and comprising a LSDL latch, respectively.  FIG. 4A  shows a preferred dynamic logic implementation of formula 5A″ with a dynamic node  40 , which is precharged according to prior art. Further, a foot device  42  is implemented without building a transistor stack consisting of more than 4 transistors connected in series. The 4-transistor stack is encircled by rectangle  44  depicted in dotted lines. According to the invention the transistor stack  44  can be delimited to a maximum length of 4 transistors due to the fact that the H 1   i  input variables from stage  1  are not processed in stage  2 , depicted in  FIG. 4 , but instead are processed in stage  3 , which will be illustrated with reference to  FIG. 6  further below. 
         [0066]    Further, a bleeder device  46  is provided in order to feed the dynamic node  40  with the required amount of electrical charge. The clock signal depicted in the left upper portion of  FIG. 4  resets a precharge transistor  48  which co-operates with the bleeder device  46 , wherein transistor  48  and bleeder device  46  and foot device  42  are dimensioned in a suited way according to prior art, in order to implement a suited precharge mechanism. With reference to the input variables H 1 _N i  and I 1 _N i  it should be noted that _N denotes the inversion of H 1   i  and I 1   i  respectively. 
         [0067]    With reference to  FIG. 4B  a LSDL latch is provided additionally relative to  FIG. 4A  and is depicted in a frame  98 . The latch is situated at the output of the bypass stage for driving the subsequent stage, here the subsequent stage  3 . 
         [0068]    First, the latch  98  is protected for stability by output transistors against crosstalk incoming via the output line. Further, the precharge node  40  is provided as usual in dynamic logic at the input of said H 1 -I 1  input data processing logic. In order to avoid a switching of the latch caused by a transition from precharge to evaluate phase, the timing control of transistor  14  (T 14 ) is controlled in a particular way described further below. According to an advantageous feature of the present invention the time control of a switching transistor device  114  is implemented such that it stabilizes the bit value present on the latch input node  132  in such a way, that said transistor  114  protects the actual value of node  132 , until said dynamic node  40  has a stable value during the evaluation phase. It is thus avoided, that the precharge value of said precharge node  40  can cause a switching on said latch input node  32 , as transistors ( 114 ) and  115  are activated before the complex logic has reached a stable state. As a skilled person appreciates, the switching stability for the stages subsequent to this stage  2  (bypass stage) is improved. 
         [0069]    With reference to  FIG. 5A  the above-mentioned formula 5B′ is implemented for the I 2 -gate of stage  2 . Also here, a respective precharge mechanism is provided by a precharge transistor  48 , a bleeder device  46  and a foot device  42 , all implemented as N-transistor devices. 
         [0070]    With reference to  FIG. 5B  a LSDL latch is provided additionally relative to  FIG. 4A  and is depicted in a frame  99 . The latch is situated at the output of the stage  2  out of similar reasons as described before. 
         [0071]    With further reference to  FIG. 6  a preferred implementation of stage  3  is depicted in a schematic way implementing in fully dynamic DOMINO-logic the H 1 -terms from stage  1  and H 2 - and I 2 -terms from stage  2  generating H 3  and I 3  according to the following formulae 6A and 6B, respectively. 
         [0000]        H 3 i   =H 1 i   +H 2 i   +H 1 i+8   I 2 i+1   +H 2 i+8   I 2 i+1   
         [0000]      =( H 1 i   +H 2 i )+( H 1 i+8   +H 2 i+8 ) I 2 i+1   (6A) 
         [0000]        I 3 i   =I 2 i   I 2 i+8   (6B) 
         [0072]    In  FIG. 6  the H 1  input terms are denoted with reference signs  60  and  62 , respectively. Thus, it yields that stage  2  is completely bypassed for those H 1 -terms. Also here, a respective precharge mechanism is provided by pre-charge transistor  48 , bleeder device  46  and foot device  42 . As reveals from  FIG. 6  the largest transistor stack comprises not more than a number of 4 transistors including the foot device, which is indicated by the dotted line rectangle  64 . 
         [0073]    The H 4 -gate of stage  4  is implemented according to formula 7 and depicted in a schematic way in  FIG. 7 . Also these gates are implemented in fully dynamic DOMINO hardware logic. 
         [0000]        H 4 i =( H 3 i   +H 3 i+16   I 3 i+1   +H 3 i+32   I 3 i+1   I 3 i+17   +H 3 i+48   I 3 i+1   I 3 i+17   I 3 i+33 ) p   i   (7) 
         [0074]    In this stage  4  blocks of 16 bits are put together in order to form the final carries for the sum generation in stage  5 , not depicted separately. The terms H i  together with the terms I i , which is actually the propagate term of bit position I(p i ) is the so-called hot carry into the next respective bit position to generate the sum Also in this stage  4  a respective precharge mechanism is implemented according to the above-described earlier stages. 
         [0075]    Stage  5  of the carry generation network is not depicted in a drawing as it corresponds completely to prior art. In stage  5  the result sum i, the carry into bit position i and the half sum HSUM i  are logically connected by an XOR-gate. Thus, the following formula 8 yields: 
         [0000]      SUM i   =H 4 i−1 ⊕HSUM i   (8) 
         [0076]    For sake of increased completeness and clarity of the inventive approach the logic functions to generate the carries for the inventional adder structure in an example for a 64-bit adder is given in  FIG. 8A  and  FIG. 8B , which both show a table-like representation for the functions H i  and I i  and the respective carries generated. The carries for bits  57  to  64  are completely done with the functions H 2  and H 1 . Also in this representation the H 1 -terms marked with an arrow are moved to the stage H 3 . Thus, the complex gate for the H 2 -function can be supplied with a foot device, not exceeding the limit of stacking up N-devices for a heap higher than 4. AS it is shown in  FIG. 8B  the carries for bits  49  to  56  are completely done with function H 3 . The function H 1 (i) terms—denoted underligned in  FIGS. 8A and 8B  are connected directly from stage  1  to stage  3  thus bypassing stage  2 . 
         [0077]    Further, and with reference to  FIG. 9A  and  FIG. 9B , which is a continuation of  FIG. 9A  a parallel prefix graph of the first two levels of the inventional adder structure according to a specific embodiment thereof is shown. In fact, only the logical connections are illustrated as the actual implementation in silicon is different. From this schematic representation should reveal which input bits are processed in a respective stage of the carry network. In  FIG. 9A  the first stage of the carry network is depicted at the top portion and the second stage is depicted in the rest of the figure. In order to increase clarity the connections are shown only for the h-terms. The i-terms connections are given by the above formulae. This structure repeats itself for all 8-bit groups starting from 0 to 64. 
         [0078]    As  FIG. 9B  shows there is a direct connection from stage  1  to stage  3 , which is marked by arrows in the drawing.