Abstract:
The circuit characteristics of an intermediate layer between an uppermost layer and a lowermost layer of a ceramic multilayer substrate with substrates laminated can be evaluated. A method for evaluating the characteristics of the intermediate layer circuit is provided. The intermediate layer circuit is installed on the intermediate layer of the multilayer substrate and has a wiring and a grounding pad, holding grounding potential, formed in the vicinity of the wiring. The method includes steps of: irradiating a region of the upper layer substrate located above the grounding pad of the intermediate layer with laser to scrape to a predetermined thickness; polishing the upper layer substrate scraped to the predetermined thickness with a hard polishing tool to expose the wiring and/or grounding pad; and bringing a probe needle in contact with the exposed wiring and/or grounding pad to evaluate characteristics of the intermediate layer circuit.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to an evaluation of wiring patterns of multilayer ceramic substrates.  
           [0003]    2. Description of Background Art  
           [0004]    [0004]FIG. 1 is a perspective view showing a configuration of a conventional ceramic multilayer substrate  50 . Ceramic multilayer substrate  50  has the third layer  53 , the second layer  52 , and the first layer  51  laminated successively from the bottom, and lastly cap  55  is attached. The figure shows the configuration of the top layer (first layer)  51  before cap  55  is attached. The first layer  51  has the top wiring and chip part  54  arranged. The same thing can be said of the second layer  52  and the third layer  53 .  
           [0005]    [0005]FIG. 2 is a cross-sectional view of ceramic multilayer substrate  50  cut in the direction perpendicular to each layer. Wiring  64  of the first layer  51  (FIG. 1), wiring  65  of the second layer  52  (FIG. 1), and inner wiring  66  of the third layer  53  (FIG. 1) are circuit wiring of power supply circuit, RF wiring, connection wiring between circuits, etc., respectively. The power supply circuit of the first layer  51  (FIG. 1) is formed using chip parts of resistance R, capacitance C, impedance L, and others. Electrical connections of wiring of each layer are secured by via-holes (for example, via-hole  68 ).  
           [0006]    At the center of ceramic multilayer substrate  50 , one or more holes are provided in advance so that semiconductor element  61  is arranged. More precisely, since the profile of semiconductor element  61 , position of via-holes, and other physical conditions differ layer by layer, specified holes must be provided in advance in assembling ceramic multilayer substrate  50 . Consequently, before hardening by quenching, wiring is put between ceramic materials of, for example, clay, and the holes at the center section and via-holes are formed. Each ceramic layer thus formed is built by quenching. When each ceramic layer is laminated, semiconductor element  61  arranged at the hole is connected to the specified layer (for example, wiring  65  of the second layer  52  (FIG. 1)) by wire  62 .  
           [0007]    On a surface exposed to the outside of the third layer  53  (FIG. 1), that is, the surface on the side opposite to cap  55 , wiring  67  and terminal  69  are mounted. Wiring  67  is grounding wiring  67  for multilayer substrate  50  to secure grounding. Terminal  69  is terminal  69 , for example, for outputting electric power to secure electrical connections between ceramic multilayer substrate  50  and the outside.  
           [0008]    Because in ceramic multilayer substrate  50 , wiring is inspected only from wiring  64  on the uppermost layer, the characteristics of intermediate wiring are unable to be directly confirmed and mutual influences between circuits are unable to be evaluated. The reasons are described as follows. Firstly, in ceramic multilayer substrate  50 , it is difficult to bore holes to the intermediate layer hardened after quenching and process holes without cutting wiring on intermediate layers. Secondly, because if wiring is inspected from wiring  64  on the uppermost layer where a probe needle is brought in contact with the wiring, measurement errors increase and the S parameter is unable to be measured, evaluation cannot be made unless bonding is made on the special-purpose substrate in the module condition. Furthermore, from wiring  64  on the uppermost layer, only direct current characteristics can be evaluated.  
         SUMMARY OF THE INVENTION  
         [0009]    It is an object of the present invention to directly evaluate circuit characteristics of intermediate layers of a ceramic multilayer substrate.  
           [0010]    The method according to the present invention can be used for evaluate characteristics of an intermediate layer circuit located between an uppermost layer and a lowermost layer of a multilayer substrate with multiple substrates laminated. The intermediate layer circuit includes a wiring and a grounding pad, having grounding potential, formed in the vicinity of the wiring. The method includes: irradiating a region of an upper layer substrate located above the grounding pad of the intermediate layer with laser to scrape to a predetermined thickness; polishing the upper layer substrate scraped to the predetermined thickness with a hard polishing tool to expose at least one of the wiring and the grounding pad; and bringing a probe needle in contact with the at least one of the exposed wiring and the exposed grounding pad to evaluate characteristics of the intermediate layer circuit.  
           [0011]    According to the present invention, because the top substrate is scraped using laser and hard polishing tool to bore holes to the intermediate layer, it is possible to expose wiring, pads, etc. on the intermediate layer without damaging them. Furthermore, because it is possible to bring a probe needle for evaluation directly in contact with wiring, etc. of the exposed intermediate layer through the hole, circuit characteristics can be evaluated reliably and easily.  
           [0012]    On the top substrate, the predetermined circuit may be provided on the upper layer substrate, and the predetermined circuit may be arranged with care to avoid a region of the upper layer substrate located above the grounding pad of the intermediate layer. That is, to the region of the top layer substrate to which laser is applied, no circuit is arranged. Therefore, holes can be bored to the intermediate layer without damaging circuit elements of the top layer circuit.  
           [0013]    After exposing the wiring and the grounding pad by the exposing step, the method may further include a step of electrically connecting the exposed wiring and the exposed grounding pad using a circuit element. The wiring may include two wiring elements isolated from each other, which are exposed by the exposing step. The method may further includes a step of electrically connecting the exposed two wiring elements using a circuit element. By electrically connecting the exposed wiring and grounding pad or exposed two wiring elements using circuit elements, it is possible to form, for example, a new circuit with the intermediate circuit adjusted.  
           [0014]    The laser may be excimer laser. Therefore, it is possible to eliminate detrimental effects of heat on intermediate layer substrates and top layer substrate, and to achieve subtle processing.  
           [0015]    The polishing tool may be a diamond bar. Therefore, it is possible to reliably polish ceramic substrates. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]    This and other objects and features of the present invention will become clear from the subsequent description of a preferred embodiment thereof made with reference to the accompanying drawings, in which like parts are designated by like reference numerals and in which:  
         [0017]    [0017]FIG. 1 is a perspective view of a conventional ceramic multilayer substrate;  
         [0018]    [0018]FIG. 2 is a cross-sectional view of a ceramic multilayer substrate cut in the direction perpendicular to each layer;  
         [0019]    [0019]FIG. 3 is a perspective view of ceramic multilayer substrate according to the present invention;  
         [0020]    [0020]FIG. 4 is a perspective view of a specific configuration of the intermediate layer;  
         [0021]    [0021]FIG. 5A is a diagram which shows a process for boring hole using laser;  
         [0022]    [0022]FIG. 5B is a diagram which shows a process for scraping wiring by diamond bar;  
         [0023]    [0023]FIG. 5C is a diagram which shows an inspection process with a probe needle applied; and  
         [0024]    [0024]FIGS. 6A and 6B are schematic representations explaining a circuit that can be formed on the intermediate layer. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0025]    Referring now to the drawings attached, the preferred embodiments of the present invention will be described. FIG. 3 is a perspective view showing the configuration of ceramic multilayer substrate  10  according to the present invention. Ceramic multilayer substrate  10  achieves the specified functions, for example, functions as a power module for controlling the electric power supplied to the outside, in accordance with motions of semiconductor elements (not illustrated) mounted inside.  
         [0026]    Ceramic multilayer substrate  50  illustrated includes three layer. To the uppermost layer of the figure, grounding metal wiring  17  which grounds ceramic multilayer substrate  10  is installed. To the uppermost layer, wiring, terminal, element, etc. other than grounding metal wiring  17  can be provided, and to the lowermost layer, required wiring, terminal, element, etc. can be mounted, but nothing particular is specified in the figure.  
         [0027]    To intermediate layer  11  located between the uppermost layer and the lowermost layer, signal wiring  15  and grounding pads  12  to  14  mounted on both sides of signal wiring  15  are provided. Then, FIG. 4 is a perspective view showing a specific configuration of intermediate layer  11 . Signal wirings  15 - 1 ,  15 - 2  are conductors that can transmit signals of the circuit formed, for example, wiring about 100 μm wide formed with aluminum. A plurality of grounding pads  12  to  14  are terminals about 100 μm square formed by aluminum which are the same as signal wiring  15 . Each grounding pad is connected to the grounding wiring (not illustrated) of still lower layer by via-holes (not illustrated) to maintain grounding potential. As clear from the figure, grounding pads  12  and  13  are mounted in the vicinity of wiring cut halfway of the central portion of intermediate layer  11 . In addition, grounding pad  14  is mounted on the substrate edge of signal wiring  15 . Signal wirings  15 - 1 ,  15 - 2  are not electrically connected as shown in region  21 .  
         [0028]    Now, principal features of the present invention will be described. The present invention relates to processing of inspecting the intermediate layer of a ceramic multilayer substrate with ceramic substrates laminated. In the present embodiment, a hole is bored in a substrate (hereinafter called the “upper layer substrate”) located above intermediate layer  11  of the ceramic multilayer substrate, and from the hole, intermediate layer  11  is inspected. Consequently, in intermediate layer  11 , grounding pads required for inspection are provided. In addition, because a hole is bored in the upper layer substrate of intermediate layer  11 , signal wiring and chip parts, and other circuit elements are arranged with care to avoid the region where a hole is bored. Because in a conventional ceramic multilayer substrate  50  (FIGS. 1 and 2), the intermediate layer (intermediate layer  52  in FIG. 1) of the conventional ceramic multilayer substrate is unable to be directly inspected, needless to say, no grounding pad existed. In addition, since no hole is bored in the upper layer substrate of the intermediate layer, from the viewpoint of circuit element layout, the intermediate layer substrate and the upper layer substrate are designed independently.  
         [0029]    The reasons for inspecting the intermediate layer are explained as follows. When the wiring is connected to the element that forms the circuit, it becomes a problem how much impedance is deviated. Depending on the impedance, there exists the oscillating frequency. The RF terminal of modules, etc. is designed to achieve, for example, about 50 ohm at the time of operation. This “50 ohm” means the center of the Smith chart that expresses impedance. However, even if wiring is designed to achieve 50 ohm impedance by connecting elements and wiring by simulation, when circuits are fabricated actually, impedance frequently deviates. This deviation increases particularly in the intermediate layer. Consequently, in the present invention, the intermediate layer is subject to the inspection.  
         [0030]    [0030]FIGS. 5A through 5C are diagrams showing the inspection technique of the intermediate layer by the present embodiment. To be more specific, FIG. 5A is a diagram showing a process for boring hole by laser  31 . FIG. 5B is a diagram showing a process for scraping wiring  15  by diamond bar  32 . FIG. 5C is a diagram showing a process of inspection with a probe needle applied. First of all, referring to FIG. 5A, excimer laser  31  is applied to the region of the upper layer substrate located above the grounding pad of intermediate layer  11 , or region  21  (FIG. 4) and the upper layer substrate is scraped right before signal wiring  15  of intermediate layer  11 . The term “right before” referred to herein means to the thickness that allows signal wiring  15  of intermediate layer  11  to be observed faintly, for example, 0.5 mm. As described above, to the relevant region to which laser is applied, it is designed not to allow circuit elements such as signal wirings and chip parts to exist. The reason why excimer laser  31  is used is because it can eliminate detrimental effects of heat on substrate and enables subtle processing. To be more specific, it is possible to process the substrate without damaging chip parts and other signal wiring on the upper layer substrate.  
         [0031]    Referring now to FIG. 5B, for intermediate layer  11  scraped by excimer laser  31 , using diamond bar  32  with a diamond mounted to the head end, which is a hard polishing tool, the upper layer substrate is polished until grounding pad  14  or signal wiring  15  of intermediate layer  11  appears, and a hole is bored. That is, the upper layer substrate is further scraped to bore a hole. For example, if the needle tip width of probe needle is 250 μm, a hole about 400 μm square or about 400 μm in diameter is bored. FIG. 5C shows hole  33  bored in this way. For example, it is understood that grounding pad  14  and signal wiring  15  existing between pads are exposed. As shown in the drawing, a plurality of holes may be bored simultaneously or successively. Because a hole is bored in the upper layer substrate using not only excimer laser  31  but also diamond bar  32 , fine processing is definitely carried out and consequently, disconnection of signal wiring  15  of intermediate layer  11  would not result.  
         [0032]    By bringing probe needle  34  in contact with grounding pads  12  through  14  and/or signal wiring  15  through the hole in the upper layer substrate bored as described above, characteristics, etc. of grounding pads  12  through  14  and signal wiring  15  and across circuits can be inspected by using microwave, for example. Note that, in the figure, probe needle  34  is drawn in a form of a bar tapered at the head end, but the known probe needle has three needles aligned in one row at specified intervals. Of these, needles on both ends are grounding needles and the needle at the center is the needle for wiring which is brought in contact with the wiring to be inspected. Since the known probe needle is configured in this way, grounding pads must be installed on both sides of signal wiring  15 . As a result, characteristics of signal wiring  15  (for example, S parameter) and effects of wiring of semiconductor element can be evaluated.  
         [0033]    To exemplify the evaluation procedure, first of all, prepare two probe needles and connect each probe needle to two RF connection terminals of the network analyzer, which is an S parameter measuring apparatus. Secondly, of the probe needles connected, bring the wiring needle at the center to wiring and grounding needles on both ends to grounding pads on both side of wiring. Thirdly, transmit wide-band frequency signals from the network analyzer and measure such as S parameter characteristics.  
         [0034]    “S parameter” is used for evaluating circuit characteristics of high-frequency region. In general, in the high frequency, it is extremely difficult to measure voltage and current as in the case of low frequency. For example, bringing probes to wiring for voltage measurement causes the probe to function like a stab and changes the circuit configuration. Even if they are not brought in contact, bringing a substance which is located around the wiring pattern close to wiring and would disturb the electromagnetic field around the wiring pattern disturbs the characteristics of the circuit proper. Because even in the high-frequency region, the stably and accurately measurable amount is electric power, the circuit network can be treated as a black box even in the high frequency if the electric power entered in the circuit can be related to the electric power outputted. Therefore, it is useful to find the scattering matrix (S matrix) which specifies circuit characteristics in accord with the size and the phase of waves related to electric power inputted and outputted to and from each terminal pair (ports) of the circuit. And each element of S matrix is the S parameter referred to herein. Using the S parameter, it is possible to fabricate the specified circuit and adjust the S parameter to achieve the optimum characteristics of elements that compose the circuit.  
         [0035]    After evaluating the characteristics of signal wiring  15  of intermediate layer  11 , a circuit can be newly formed on ceramic multilayer substrate  10  with a hole bored in the upper layer substrate. FIG. 6A and FIG. 6B are schematic representations explaining circuits that can be formed on intermediate layer  11 . Referring to FIG. 6A, no electric continuity exists across signal wiring  15 - 1  and  15 - 2  because they are cut at region  21 . That is, signal wiring  15 - 1  and  15 - 2  are isolated. However, no-resistant 0-ohm chip  41  or chip parts of resistance R, capacitance C, impedance L, etc. are mounted on region  21  so that they come in contact with both signal wiring  15 - 1  and  15 - 2 . Therefore, signal wiring  15 - 1  and  15 - 2  may be able to function as one signal wiring. On the other hand, referring now to FIG. 6B, signal wiring  15  not cut may be connected to grounding pad  12 . That is, non-resistance chip  42  or C.R.L chips may be provided on region  43  so that they connect to both of signal wiring  15  and grounding pad  12 . Note that, in the example shown in FIG. 6A, grounding pad  12  and signal wiring  15 - 1  may be connected by chip  41 . By mounting grounding pads in the vicinity of signal wiring of intermediate layer  11  in this way, new chips, etc. can be arranged and a circuit can be formed. For example, since parts with oscillation measures taken, parts for impedance adjustment, etc. can be added, the characteristics obtained by evaluation can be still more upgraded.  
         [0036]    After completion of the evaluation of intermediate layer wiring as described above and forming a new circuit by the above-mentioned technique, if necessary, a cap is attached to the ceramic multilayer substrate to complete a semiconductor module. For the cap, cap  55  shown in FIGS. 1 and 2 can be used as in conventional cases.  
         [0037]    The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the cope of the following claims.