Abstract:
Redundancy circuits for accessing the stored data in the memory banks are provided in a semiconductor memory. First and second memory banks, each has 2N number of redundancy lines. Only N number of redundancy lines in each memory bank is utilized during normal operations. During normal operations, a first redundancy control block provides N number of redundancy signals to the first memory bank. A second redundancy control block provides N number of redundancy signals to the second memory bank. An address signal switching unit receives memory bank failure signals. During normal operations, the address signal switching unit multiplexes the N number of redundancy signals from the redundancy control block to the N number of redundancy lines of the corresponding memory bank. Upon failure of a memory bank, the address signal switching unit multiplexes the N number of the redundancy signals corresponding to the failed memory bank to the other operational memory bank so that the operational memory bank utilize a total of 2N number of redundancy lines.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates generally to a redundancy efficiency increasing circuit of semiconductor memory device and, more particularly, to a redundancy efficiency increasing circuit of semiconductor memory device which can increase efficiency of redundancy twice by using unused fuse having a block fail when a block fail is generated, thereby only a half of chip is used. 
   2. Description of the Related Art 
     FIG. 1  shows generally the column redundancy structure in a conventional semiconductor memory device. In  FIG. 1 , only two memory banks, labeled as Bank i and Bank k, are used in describing the conventional column redundancy structure although more than two memory banks may be used. Each memory bank (either Bank i or Bank k) includes four memory blocks, one of which is shown with a reference label  10  in FIG.  1 . Further, in each memory bank Bank i or Bank k, there are two column redundancy lines RYS 0  and RYS 1 . Up to two column fails (occurring, for example, while accessing the data in the memory block) are recoverable in any one of the memory blocks  10  by allowing one of the two column redundancy lines RYS 0  or RYS 1  to substitute for the other column redundancy line. The same operations of column redundancy line substitutions in the event of a column fail is also performed in the other remaining memory blocks  10  in the same memory bank, Bank i or Bank k. According to this conventional column redundancy structure, only up to two column fails are recoverable in any one conventional memory bank, Bank i or Bank k. 
   Associated with each bank, Bank i or Bank k, a redundancy control block  30  having a Y fuse  20  is provided to control and oversee the column fail recovery operation in each memory bank Bank i or Bank k. The column fail recovery operations for the column line substitution operations are performed based at least on the signals for comparing the Y address, AY&lt;0:m&gt;, the signals for bank coding BAi, and the signals for X block coding Bxi&lt;0:n&gt; that are inputted to redundancy control block  30  as shown in FIG.  1 . However, in the event of an unrecoverable block fail in a memory bank (e.g., Bank k) due to, for example, more than two unrecoverable column fails generated in a memory bank, the other bank, Bank i, could only be used. As already discussed above, recovering from more than two column fails in one memory bank  10  of a conventional column redundancy structure as shown  FIG. 1  is not possible. Therefore, the Y fuse of a failed memory bank (for example, of the Bank k) cannot be used for any other operational memory bank(s) such as the Bank i in FIG.  1 . 
   SUMMARY OF THE INVENTION 
   Therefore, the present invention has been made to solve the above-mentioned problems and a primary objective of the present invention is to provide a redundancy efficiency increasing circuit of semiconductor memory device which can increase efficiency of redundancy by using unused fuse in a redundancy of another bank when a block fail is generated in one bank and it is impossible to improve the fail. 
   In order to accomplish the above object, the present invention comprises 2 N banks having 2M redundancy lines-(2n−1)th bank and (2n)th bank have a corresponding relation, and n is a natural number in the range of 1 to N—and a fuse circuit, including: 2N redundancy control blocks for enabling redundancy lines of corresponding bank in the banks according to received address signal; and an address signal switch unit for receiving a first control signal, a second control signal and an address signal to provide a bank address signal selecting (2n−1)th bank to corresponding redundancy control block of (2n−1)th bank and (2n)th bank when only the first control signal is enabled, provide a bank address signal selecting (2n)th bank to corresponding redundancy control block of (2n−1)th bank and (2n)th bank when only the second control signal is enabled and provide a bank address signal selecting (2n−1)th bank to corresponding redundancy control block of (2n−1)th bank an a bank address signal selecting (2n)th bank to corresponding redundancy control block of (2n)th bank when both the first control signal and the second control signal are enabled. 
   In the 2M redundancy lines, M redundancy lines are operated to improve fails of the bank and another M redundancy lines are operated to improve fails of the corresponding bank. The first control signal and the second control signal are generated by bonding option. The redundancy line is a column redundancy line. 
   The redundancy efficiency increasing circuit of semiconductor memory device according to the present invention can increase redundancy efficiency twice by using a first to a third multiplexers to use the fuse of bank having the block fail when a block fail is generated and it is impossible to improve. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a drawing showing the arrangement of a column redundancy circuit structure according to a conventional semiconductor memory device. 
       FIG. 2  is a block diagram of a redundancy efficiency increasing circuit of semiconductor memory device according to an embodiment of the present invention. 
       FIG. 3  is a circuit diagram of a first multiplexer shown in FIG.  2 . 
       FIG. 4  is a circuit diagram of a second multiplexer shown in FIG.  2 . 
       FIG. 5  is a circuit diagram of a third multiplexer shown in FIG.  2 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The above objects, and other features and advantages of the present invention will become more apparent after reading the following detailed description when taken in conjunction with the drawings. 
   As already discussed in the Background section of this disclosure, in case of a memory block fail in a conventional memory bank (which may be caused by more than two column fails), the Y fuse of the of the failed memory bank cannot be used for the any other operational memory bank for column fail recovery purposes. The present invention solves this and other problems associated with the conventional memory devices. In particular, the present invention (which will be described hereinbelow in more detail) allows the Y fuse of a failed memory bank caused by an unrecoverable block fail condition to be available for use by the other operational memory bank(s). 
     FIG. 2  is a block diagram of a semiconductor memory device generally showing the structure according to an embodiment of the present invention. Referring to  FIG. 2 , the semiconductor memory device  2000  according to an embodiment of the present invention comprises four memory banks: Bank i  210 , Bank j  210 , Bank k  230 , Bank l  240 . An address signal switch unit  250  is provided to this set of four memory banks  210 ,  220 ,  230 ,  240 . 
   The address signal switch unit  250  comprises a first multiplexer  200 , a second multiplexer  300 , and a third multiplexer  400 . Although four memory banks  210 ,  220 ,  230 ,  240  are shown in  FIG. 2 , an embodiment of the present invention is described with respect to Bank i  210  and Bank k  230 . However, it should be readily apparent to those skilled in the art that similar operations and effects are equally applicable to the other pair of memory banks Bank j  220  and Bank l  240 . 
   As shown in  FIG. 2 , there are four memory blocks (although only one is labeled as  100  in  FIG. 2 ) in each memory bank  210 ,  220 ,  230 , or  240 . And, there are four column redundancy lines RYS 0 , RYS 1 , RYS 2 , RYS 3  for each memory block  100 . The two column redundancy lines RYS 0 , RYS 1  are column redundancy lines generally for use during the normal operation of each memory bank, and the other two column redundancy lines RYS 2 , RYS 3  are for use in the event when an unrecoverably failed memory bank is present in either pair of memory banks (for example, Bank i  210  and Bank j  220  grouped as one pair, and Bank j  230  and Bank l  240  grouped as another pair). The column redundancy lines RYS 2 , RYS 3  are designed to allow the two column redundancy lines of the failed memory bank to be utilized in the other operational memory banks. Generally, the memory banks are paired for operational purposes, and the pairing is generally determined by the input/output structure(s) of the memory banks. As already explained, Banks i and j  210 ,  220  are paired and Banks k and l  230 ,  240  are paired for, for example, their input/output operations in an embodiment of the present invention; however, it should readily apparent to those skilled in the art that other combinations may be used to pair up the memory banks. 
   These column redundancy lines RYS 0 , RYS 1 , RYS 2 , RYS 3  are arranged to the blocks in each memory bank by first, second, and third multiplexers  200 ,  300 ,  400  in the address switching unit  250 . Further, a Y Fuse  500  is provided for each memory bank  210 ,  220 ,  230 ,  240  for column fail recovery operations. For example, in Bank i  210  in  FIG. 2 , the column redundancy signals RYS 0 , RYS 1  are generated based on an AY&lt;0:m&gt; signal, which is for comparing the Y address(es), a BAi signal for providing the bank coding, and a Bxi&lt;0:n&gt; signal for providing the X block coding that are inputted to the redundancy control block  600  having the Y fuse  500 . 
   The first multiplexer  200  can be understood for providing the switching operations for the bank coding based on the following inputted signals: the bank coding signals BAi, BAk; the X block coding signals BXi&lt;0:n&gt; and BXk&lt;0:n&gt;; and the signals BONDij and BONDkl that are inputted to the multiplexer  200  through an bonding option. Based on these inputted signals for example, the first multiplexer  200  outputs the BAi and BXi&lt;0:n&gt; signals to the redundancy control block  600  for the Bank i  210  and outputs the BAk and BXk&lt;0:n&gt; signals to the redundancy control block  600  for the Bank k  230 . 
   The BONDij and BONDkl signals are applied in the event that a bank failure condition is detected during the test after manufacturing the device. For example, in the event that a fail condition is detected in either Bank i  210  or Bank j  220 , the BONDij signal is held to a low level and the BONDkl signal is held to a high level through a bonding option. More specifically with respect to the bonding option, the high or low level for each BONDij and BONDkl signal is determined by connecting (or not connecting) the selected one of the bonding pads (that are also connected to the circuits for generating the BONDij or BONDkl signals) to a voltage Vss. 
   In the similar manner, the BONDij signal is held to a high level and BONkl signal is held to a low level through the bonding option, in the event a fail condition is detected in either Bank k  230  or Bank l  240 . 
   The second multiplexer  300  receives the BOND ij signal and the RYSi 0  or RYSi 1  signals from the redundancy control block  600  for Bank i  210 . Likewise, the third multiplexer  400  receives the BOND kl signal and the RYSk 0  or RYSk 1  signals from the redundancy control block  600  for Bank k  230 . 
   With respect to the column redundancy lines RYS 0 , RYS 1 , RYS 2 , RYS 3  for Bank i  210 , and in the event that the BOND ij signal is at high and BOND kl is low, the second multiplexer  300  would provide the RYSi 0  and RYSi 1  signals to the RYS 0  and RYS 1  column redundancy lines, and the third multiplexer  400  would provide the RYSk 0  and RYSk 1  signals to the RYS 2  and RYS 3  column redundancy lines. 
   With respect to the column redundancy lines RYS 0 , RYS 1 , RYS 2 , RYS 3  for Bank k  230 , and in the event that BOND kl signal is held to a high level, the third multiplexer  400  would provide the RYSk 0  and RYSk 1  signals to the RYS 0  and RYS 1  column redundancy lines for the Bank k  230 , and the second multiplexer  300  would provide its RYSi 0  and RYSi 1  signals to the RYS 2  and RYS 3  column redundancy lines. 
   Each bank is connected to a Y Fuse  500  as shown in  FIG. 2 , and the redundancy control block  600  that includes the Y Fuse  500  is utilized for recovering from the column fails in the associated column bank. For example in relation to Bank i  210 , the AY&lt;0:m&gt; signal for comparing the Y address(es), the BAi signal for the bank coding, and the BXi&lt;0:n&gt; signal for the X block coding are inputted to the redundancy control block  600  that has the Y fuse  500 , and the redundancy control block  600  thereby generates the column redundancy select signals RYSi 0 , RYSi 1  based on these inputted signals. 
     FIG. 3  is a circuit diagram to further explain the operations of the first multiplexer  200  in FIG.  2 . As shown in the drawing, the first multiplexer  200  comprises four groups  2100 ,  2200 ,  2300 ,  2400  of the identical circuit. Each circuit of the groups  2100 ,  2200 ,  2300 ,  2400  has an inverter INV, a first NAND gate N 1 , a second NAND gate N 2 , and a third NAND gate N 3 .  200 . 
   In each group  2100 ,  2200 ,  2300 , or  2400 , a first multiplexer input signal and a second multiplexer input signal is inputted to the first NAND gate N 1 , and a third multiplexer input signal is inputted to the third NAND gate N 3  as shown in FIG.  3 . 
   The inverter INV in each of the four groups inverts the first multiplexer input signal. The inverted signal outputted from the inverter INV is then inputted into the third NAND gate N 3  together with the third multiplexer input signal. The outputs of the first and third NAND gates, N 1 , N 3  are inputted to the second NAND gate N 2 . The output of the second NAND gate N 2  (also referred to as the fourth multiplexer output signal) is then inputted to the redundancy control block  600  having the Y Fuse  500  as shown in FIG.  2 . 
   In the first group  2100 , the first multiplexer input signal is the BONDij signal, the second multiplexer input signal is the BAi signal, the third multiplexer input signal is the BAk signal, and the fourth multiplexer output signal is the BAi signal that is inputted to the redundancy control block  600 . 
   In the second group  2200 , the first multiplexer input signal is the BONDij signal, the second multiplexer input signal is the BXi&lt;0:n&gt; signal, the third multiplexer input signal is the BXk&lt;0:n&gt; signal, and the fourth multiplexer output signal is the BXi&lt;0:n&gt; signal that is inputted to the redundancy control block  600 . 
   In the third group  2300 , the first multiplexer input signal is the BONDkl signal, the second multiplexer input signal the BAk signal, the third multiplexer input signal is the BAi signal, and the fourth multiplexer input signal is the BAk signal that is inputted to the redundancy control block  600 . 
   In the fourth group  2400 , the first multiplexer input signal is the BONDkl signal, the second multiplexer input signal is the BXk&lt;0:n&gt; signal, the third multiplexer input signal is the BXi&lt;0:n&gt; signal, and the fourth multiplexer input signal is the BXk&lt;0:n&gt; signal that is inputted to the redundancy control block  600 . 
   The operations for these four groups  2100 ,  2200 ,  2300 ,  2400  of the multiplexer  200  as shown in  FIG. 3  are described as follows. 
   In the case when an unrecoverable failure condition is present in the Bank k  230  or Bank l  240 , the BONDij signal would be in a high level and the BONDkl signal would be in a low level. In this case for the first group  2100 , the second multiplexer input signal of BAi would be inputted to the second NAND gate N 2  and also outputted as the fourth output signal BAi in the first group  2100 , independent of the third multiplexer input signal BAk. In the case of the third group  2300 , the fourth output signal of the second NAND gate N 2  would be BAi regardless of the the second multiplexer input signal BAk, which is inputted to the first NAND gate N 1  in the group  2300 . Therefore, the coding information of the Bank i is inputted to the redundancy control block  600  of the Bank k, thereby it is possible to be controlled by the Bank i. 
   In the same manner for the second group  2200 , the fourth multiplexer output would be the BXi&lt;0:n&gt; signal (which is the block coding of the X (row) type). The fourth group  2400  would also output the BXi&lt;0:n&gt; signal as the fourth multiplexer output, regardless of the state of the BXk&lt;0:n&gt; signal. Therefore, the coding of Bank i is inputted to the redundancy control block  600  for the Bank k. 
     FIGS. 4 and 5  are circuit diagrams of the second multiplexer  300  and the third multiplexer  400 . Each of the second and third multiplexers  300 ,  400  comprises one inverter INV and a first and a second transmission gates  310 ,  320 .  FIG. 4  shows two groups  350 ,  370  for the second multiplexer  300  where each group has identical circuit structure, but different inputs. Likewise,  FIG. 5  shows two groups  450 ,  470  where each group has identical circuit structure for the third multiplexer  400 . 
   Now referring to  FIG. 4 , the group  350  receives the BONDij signal and the column redundancy select signal RYSi 0 . The signal RYSi 0  is an output signal of the redundancy control block  600  having the Y fuse  500  as shown in FIG.  2 . Referring back to  FIG. 4 , the circuit in the group  350  includes an inverter INV, which receives and inverts the BONDij signal; a first transmission gate  310  receives the BONDij signal and the inverted signal outputted from the inverter INV. The transmission gate  310  transmits the RYSi 0  signal to the column redundancy line RYS 0  of the Bank i. A second transmission gate  320  receives the BONDij signal and the inverted signal from the inverter INV and transmits the RYSi 0  signal to the column redundancy line RYS 2  of the Bank k. 
   The group  370  of  FIG. 4  receives the BONDij signal and the column redundancy select signal RYSi 1 . The signal RYSi 1  is an output signal of the redundancy control block  600  having the Y fuse  500  as shown in  FIG. 2 , Referring back to  FIG. 4 , the circuit in the group  370  (which is of course identical to the circuit in the group  350 ) includes an inverter INV for inverting the BONDij signal. A first transmission gate  310  receives the BONDij signal and the inverted signal outputted from the inverter INV. The transmission gate  310  transmits the RYSi 1  signal to the column redundancy line RYS 1  of the Bank k. A second transmission gate  320  receives the BONDij signal and the inverted signal from the inverter INV and transmits the RYSi 1  signal to the column redundancy line RYS 3  of the Bank k. 
   Referring to  FIG. 5 , shown therein is the third multiplexer  400 , which is illustrated with two groups  450 ,  470  of the same circuit structure to illustrate the operation based on different combination of input signals. The group  450  of the third multiplexer  400  receives the BONDkl signal and the column redundancy select signal RYSk 0 . The RYSk 0  signal is the output signal of the redundancy control block  600  having the Y fuse  500  as shown in FIG.  2 . Referring back to  FIG. 5 , the circuit in the group  450  includes an inverter INV for inverting the BONDkl signal; a first transmission gate  410  for receiving the BONDkl signal and the inverted signal outputted from the inverter INV. The transmission gate  410  transmits the RYSk 0  signal to the column redundancy line RYS 0  of the Bank k. A second transmission gate  420  receives the BONDkl signal and the inverted signal from the inverter INV and transmits the RYSk 1  signal to the column redundancy line RYS 3  of the Bank i. 
   When all banks are normally operating, the BONDij and BONDkl signals are enabled to a ‘high’ level. Therefore, the RYSi 0  signal, which is the column redundancy select signal in the second multiplexer  300 , is loaded on the column redundancy line RYS 0  of the Bank i. Likewise, the RYSi 1  signal is also loaded on the column redundancy line RYS 1  of the Bank i. Similarly, the RYSk 0  signal, which is the column redundancy select signal in the third multiplexer  400 , is loaded on the column redundancy line RYS 0  of the Bank k, and the RYSk 1  signal is loaded on the column redundancy line RYS 1  of the Bank k. 
   When a plurality of fails are generated in the Bank i or Bank j and when the BONDij signal becomes a ‘low’ level, the RYSi 0  signal is loaded on the column redundancy line RYS 2  of the Bank k in the second multiplexer  300 , and the RYSi 1  signal is loaded on the column redundancy line RYS 3  of the Bank k. As a result, two column redundancy lines are added to the Bank k. 
   And, when a plurality of fails are generated in the Bank k or Bank l and when the BONDkl signal becomes a ‘low’ level, the RYSk 0  signal is then loaded on the column redundancy line RYS 2  of the Bank i in the third multiplexer  400 , and the RYSk 1  signal is loaded on the column redundancy line RYS 3  of the Bank I. As a result, two column redundancy lines are added to the Bank i. 
   That is, the number of total column redundancy lines in the present invention is, for example, more than just two as in the case of a conventional system, but four: RYS 0 , RYS 1 , RYS 2 , RYS 3  according to an embodiment of the present invention. This makes it possible to improve the column fail recovery operations as up to four column fails in a block  100  (as shown in  FIG. 2 ) are recoverable. As a result, the present invention allows improved production yield of wafers since the present invention allows the devices to tolerate and recover 3 or 4 column fails that were conventionally considered as unrecoverable. 
   According to an embodiment of the present invention, one pair of banks can use four redundancy lines, while using two redundancy lines in a normal operation. However, it is also possible to use 2n number of redundancy lines, in which n redundancy lines are utilized in each bank in a normal operation. 
   And, the present invention can also be applied to row redundancy lines in a similar manner to improve the production yield of wafers which may have the number of row fails that were considered as unrecoverable according to the conventional techniques. 
   Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.