Abstract:
The invention provides a test apparatus for testing a circuit unit to be tested. In one embodiment, a circuit unit incorporating aspects of the invention includes a data memory bank ( 106 ) for storing test mode data which are fed via an address control terminal ( 201 ) and with which the circuit unit ( 101 ) to be tested can be tested, provision being made of at least one test mode bank ( 104   a - 104   n ) for providing at least one test mode data set ( 204   a - 204   n ) and at least one activation signal ( 205   a - 205   n ), at least one register bank ( 103   a - 103   n ) and a transfer device for transferring a test mode data set ( 204   a - 204   n ) from a register bank ( 103   a - 103   n ) to the data memory bank ( 106 ) in a manner dependent on the activation signal ( 205   a - 205   n ).

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application claims priority to German Patent Application no. 10 2004 001 653.4, filed Jan. 12, 2004. 
   FIELD OF THE INVENTION 
   The present invention relates generally to test arrangements for testing electronic circuit units, in particular memory chips, and relates in particular to a test apparatus for testing a circuit unit to be tested. 
   BACKGROUND 
   Circuit units to be tested, in particular memory chips have internal registers for storing test topologies. Different topologies are necessary in order to simulate “worst case” conditions in a memory array. Registers of this type store test topologies which are used in a subsequent circuit test of the circuit unit to be tested. 
   It is usually the case that different test topologies are used for testing a circuit unit to be tested, so that it is necessary to change over between different test topologies. In order to change over between different test topologies, it has been proposed:
     (i) in each case to reload the content of a register by means of a test mode, or   (ii) to change over between different registers.   

   The abovementioned concept (i) has the advantage that only one register is required, but has the disadvantage that a pattern sequence (test pattern sequence) has to be interrupted when the register content is being reloaded. 
   The abovementioned concept (ii) has the advantage that it is possible to switch over during the run time of a test mode, i.e. “on the fly”, but is associated with the disadvantage that it is necessary to use additional external terminal pins for addressing the registers. Furthermore, the disadvantage arises that continual reloading of registers takes up a greater deal of test time such that test costs have increased. 
   The test costs when testing circuit units to be tested result from the number of circuit units to be tested which can be tested in a specific time, i.e. as a result of the throughput rate. In order to lower test costs, it is possible either to reduce the test times or to increase the number of circuit units to be tested which can be tested in parallel in a test apparatus. 
     FIG. 2  shows elements of a circuit unit to be tested in a schematic block diagram. A data register R contains various memory units YA, YB, XWR and XRD, four memory units usually being used in the prior art. 
   These memory units are activated by means of a test mode and in each case loaded with a specific register content. The activation of the test mode and the transfer of the register content are carried out by means of an address and control line A/K, test mode data being input at a test mode data terminal T. 
   The loading—shown in FIG.  2 —of test mode data into a data register R of the circuit unit to be tested has the essential disadvantage that the individual registers YA, YB, XWR and XRD can only be loaded sequentially with the corresponding register contents since, in a register drive unit A, a test mode unit TM can only drive individual register drive units Y 1 , Y 2 , X 1  and X 2  sequentially. The test times and thus the test costs increase in this way since the test mode data for different test topologies always have to be newly loaded sequentially into the data register R. 
   Therefore, it is an object of the present invention to develop a test apparatus in such a way that a test time when testing circuit units to be tested is reduced. 
   An essential concept of the invention consists in providing, besides a data register, additional register banks (at least two) in which test mode data sets can be stored beforehand. In the event of a changeover of test topologies, it is then merely necessary for a complete test mode data set to be transferred in parallel from the at least one additional register bank into the data register. 
   SUMMARY 
   The present invention is directed to a circuit unit including a data register bank for storing a test mode data set. Thus, in accordance with one embodiment of the present invention, a circuit unit may be provided with, besides a data register, an additional register bank in which test mode data sets can be stored beforehand. In the event of a changeover of test topologies, it is then merely necessary for a complete test mode data set to be transferred in parallel from the at least one additional register bank into the data register. 
   Consequently, the invention affords the advantage that a waiting time which occurs during a sequential reloading of memory units in the data register is obviated. 
   A further advantage of the method according to the invention and of the test apparatus according to the invention consists in the fact that, when a plurality of register banks are used, the effect achieved is that all the memory units of a data register can be unloaded with the aid of a single test mode call with different test mode data. 
   In particular when memory units of the data register have to be multiply reloaded during a testing of the circuit unit to be tested, this can be effected in accordance with the method according to the invention by means of a call of different register banks, only a single test mode call being necessary in each case. 
   One embodiment of a circuit unit incorporating a test apparatus according to the invention for testing a circuit unit to be tested has:
     a) an address control terminal, via which test mode data, for example in the form of test mode data sets, provided in the test apparatus can be fed to the circuit unit to be tested; and   b) a data memory bank, which has a number m of data memory units, for storing the test mode data which is fed via the address control terminal and with which the circuit unit to be tested can be tested, the circuit unit to be tested furthermore having at least one test mode bank for providing at least one test mode data set and at least one activation signal, at least one register bank, the register bank being fed in each case a test mode data set and in each case an activation signal, and a transfer device for transferring a test mode data set from a register bank to the data memory bank in a manner dependent on the activation signal.   

   Furthermore, one embodiment of a test method according to the invention for testing a circuit unit to be tested has the following steps:
     a) feeding of test mode data, which are provided in the test apparatus, to the circuit unit to be tested via an address control terminal; and   b) storage of the test mode data which are fed via the address control terminal, and with which the circuit unit to be tested is tested, in a data memory bank having a number m of data memory units,   c) at least one test mode data set and at least one activation signal being provided by means of at least one test mode bank;   d) in each case a test mode data set and in each case an activation signal being fed to at least one register bank provided in the circuit unit to be tested; and   e) in each case a test mode data set is transferred from a register bank to the data memory bank in a manner dependent on the activation signal by means of a transfer device.   

   Advantageous developments and improvements of the respective subject matter of the invention are found in the subclaims. 
   In accordance with one preferred development of the present invention, the at least one register bank in each case has a number m of register units corresponding to the number m of data memory units. 
   In accordance with a further preferred development of the present invention, the transfer device comprises a number m of transfer lines corresponding to the number m of data memory units. 
   In accordance with yet another preferred development of the present invention, provision is made of a test mode bank for providing at least one test mode data set and at least one activation signal for each of a number of n register banks. 
   In accordance with yet another preferred development of the present invention, a test mode data set is transferred from register units of a register bank in parallel to the data memory units of the data memory bank. 
   In accordance with yet another preferred development of the present invention, a test mode data set is transferred from register units of a register bank to the data memory units of the data memory bank after an activation signal has been fed to the corresponding register bank. 
   Exemplary embodiments of the invention are illustrated in the drawings and are explained in more detail in the description below. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings: 
       FIG. 1  shows a test apparatus in a circuit unit to be tested as a block diagram, in accordance with a preferred exemplary embodiment of the present invention; and 
       FIG. 2  shows a test apparatus in a circuit unit to be tested according to the prior art. 
   

   In the figures, identical reference symbols designate identical or functionally identical components or steps. 
   DETAILED DESCRIPTION 
     FIG. 1  shows a test apparatus for testing a circuit unit  101  to be tested in accordance with a preferred exemplary embodiment of the present invention. In the circuit unit  101  to be tested, a data memory bank  106  has a number m of data memory units  105   a - 105   m . Data memory units  105   a - 105   m  of this type comprise registers YA, YB, XWR and XRD, by way of example. It should be pointed out that the test apparatus according to the invention is designed for an arbitrary number m of data memory units  105   a - 105   m.    
   The circuit components for carrying out the method according to the invention are illustrated above the data memory bank  106  in  FIG. 1 . The circuit components illustrated by the reference symbols  301 ,  302  and  303   a - 303   n  correspond to a conventional test arrangement for testing the circuit unit  101  to be tested. 
   In this case, a reference symbol  301  designates a serial test mode data input device for inputting test mode data via a serial address control terminal  302 . In the serial test mode data input device  301 , the test mode data are fed serially via serial transfer lines  303   a - 303   m  to the data memory units  105   a - 105   m  of the data memory bank  106 . 
   It should be pointed out that the number of serial transfer lines  303   a - 303   m  preferably corresponds to the number m of data memory units  105   a - 105   m  provided in the data memory bank  106 . By means of the serial test mode data input device  301 , it is possible to load test data sets into the data memory units  105   a - 105   m  in a serial manner. 
   In order to reduce a test time and thus in order to reduce test costs, use is made of the method according to the invention, which can be carried out with the circuit components illustrated in the upper part of  FIG. 1 . 
   In order to carry out the method according to the invention, at least two register banks  103   a - 103   n  are provided in the circuit unit  101  to be tested. Different test mode data sets can be stored in the register banks  103   a - 103   n , as will be described in more detail below. If different test topologies based on at least two different test mode data sets are to be applied to the circuit unit to be tested, then it is possible to obtain an advantage when testing a circuit unit  101  to be tested in accordance with the method according to the invention already when using two register banks  103   a ,  103   b.    
   It should be pointed out that the method according to the invention can be carried out with an arbitrary number n of register banks  103   a - 103   n , provided that the circuit unit  101  to be tested makes such a number of register banks available. Preferably, each register bank  103   a - 103   n  has in each case a number m of register units  102   a - 102   m , the number m corresponding to the number m of data memory units  105   a - 105   m  of the data memory bank  106 . 
   The register banks  103   a - 103   n  are connected to the data memory bank  106  via a transfer device  108 . More specifically, the transfer device  108  has a number m of transfer lines  107   a - 107   m , the number m of transfer lines corresponding to the number m of register units  102   a - 102   m  of the register bank  103   a - 103   n , on the one hand, and to the number of data memory units  105   a - 105   m  of the data memory bank  106 , on the other hand. 
   The invention involves the feeding of test mode data sets  204   a - 204   n  and a corresponding addressing signal  203  via an address control terminal  201  from the test apparatus. In this case, an address control line  202  is connected to an input terminal of test mode data banks  104   a - 104   n . The test mode data banks  104   a - 104   n  are preferably provided in a number n corresponding to the number of register banks  103   a - 103   n , namely in a number n. The test mode banks  104   a - 104   n  provide at least one test mode data set  204   a - 204   n  and at least one activation signal  205   a - 205   n  from the addressing and test signals fed to them. 
   The test mode data set  204   a - 204   n  and the activation signal  205   a - 205   n  are fed to the corresponding register bank  103   a - 103   n , in accordance with the numbering “a” to “n”. 
   It should be pointed out that the lower case letters succeeding the reference symbols in each case relate to signals or a test mode bank of a specific register bank. 
   By means of the test apparatus according to the invention, it is now possible to load test mode data sets  204   a - 204   n  into corresponding register banks  103   a - 103   n  beforehand, in such a way that different test topologies that can be defined beforehand can be incremented. An activation of a corresponding register bank  103   a - 103   n  and a transfer of its data content are effected in a manner dependent on the corresponding activation signal  205   a - 205   n.    
   If one of the register banks  103   a - 103   n  is fed an activation signal  205   a - 205   n , then contents of all the register units  102   a - 102   m  of the relevant register bank  103   a - 103   n  are transferred to the corresponding data memory units  105   a - 105   m  of the data memory bank  105 . It should be pointed out that such a transfer of data is effected in a parallel manner, in such a way that a test sequence (test pattern sequence) is not interrupted. 
   Each of the register banks  103   a - 103   n  is addressed by means of two different test modes, i.e.
     (i) a definition of the content of the register units  102   a - 102   m  of the relevant register bank  103   a - 103   n ; and   (ii) a transfer of the contents of the register units  102   a - 102   m  of the relevant register bank  103   a - 103   n  to the data memory units  105   a - 105   m  of the data memory bank  106  via the transfer lines  107   a - 107   m  of the transfer device  108 .   

   The test apparatus according to the invention and the associated test method achieve the advantage, in particular, that the data memory units  105   a - 105   m  can be supplied with a corresponding test mode data set  204   a - 204   n  in a simple manner, in parallel and at high speed with contents of register units  102   a - 102   m  of an activated register bank  103   a - 103   n.    
   In this way, a test time is reduced without having to reduce a number of circuit units to be tested in parallel. This leads to an increase in the throughput rate when testing circuit units to be tested, in such a way that test costs are expediently lowered. 
   With regard to the conventional test apparatus for testing circuit units to be tested as illustrated in  FIG. 2 , reference is made to the introduction to the description. 
   Although the present invention has been described above on the basis of preferred exemplary embodiments, it is not restricted thereto, but rather can be modified in diverse ways. 
   Moreover, the invention is not restricted to the application possibilities mentioned.