Abstract:
The invention relates to a power semiconductor device and a preparation method, particularly relates to preparation of stacked dual-chip packaging structure of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using flip chip technology with two interconnecting plates. The first chip is flipped and attached on the base such that the first chip is overlapped with the third pin; the back metal layer of the first chip is connected to the bonding strip of the first pin through a first interconnecting plate; the second chip is flipped and attached on a main plate portion of the first interconnecting plate such that the second chip is overlapped with the fourth pin; and the back metal layer of the second chip is connected to the bonding strip of the second pin through the second interconnecting plate.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This Patent Application is a Continuation in Part (CIP) Application of a co-pending application Ser. No. 12/819,111 filed on Jun. 18, 2010 by a common inventor of this Application. The Disclosure made in the patent application Ser. No. 12/819,111 is hereby incorporated by reference. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The invention relates to a power semiconductor device and a preparation method, particularly relates to preparation of a stacked Dual-chip packaging structure of MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) using flip chip technology and two additional interconnecting plates. 
       DESCRIPTION OF THE RELATED ART 
       [0003]    With the trend of reducing chip size in the semiconductor device, the thermal conductivity of the semiconductor device plays a role in improving semiconductor technology and device performance. It is a challenge for semiconductor industry how to make a minimum size semiconductor package with a maximum size chip. Especially, for certain chips with large power consumption, such as DC-DC device, N type high-side and low-side transistors are packaged into a same package. 
         [0004]      FIG. 1  and  FIGS. 2A-2E  are schematic diagrams of a stacked dual-chip package of the prior art.  FIG. 1  is a top view diagram of a package  10 .  FIG. 2A  is a cross-sectional structure diagram of a package  10  along A-A line in  FIG. 1 .  FIG. 2B  is a cross-sectional structure diagram of the package  10  along B-B line in  FIG. 1 , and  FIG. 2C  is a cross-sectional structure diagram of the package  10  along C-C line in  FIG. 1 . As shown in  FIG. 1  and  FIGS. 2A-2C , top metal sheets  11   a  and  11   b  are electrically connected with electrodes at the front side of a first chip  15  and can be used as electrode leading-out terminal and also for heat dissipation. Metal sheets  12   a  and  12   b  in  FIGS. 2B-2C  are located below the first chip  15  and are electrically connected to electrodes at the back side of the first chip  15  and electrodes at the front side of a second chip  16 . The electrode at the back side of the second chip  16  is attached on a metal sheet  13  served as a terminal for connecting the electrode at the back side of the chip  16  to the outside circuit and also served as a heat sink.  FIG. 2E  is a bottom view diagram of the package  10 . Pins  13   a,    13   b,    13   c  and  13   d  are formed around the metal sheet  13  with the pin  13   a  connected with the metal sheet  13 . As shown in  FIG. 2C , pins  13   b  and  13   d  are attached to the metal sheets  11   a  and  11   b  through extending parts  13   e  and  13   f  extending upwards to the plane of the metal sheet  12   a.  For the sake of simplicity, the bonding materials for attaching the electrode of the first chip  15  to the metal sheets  11   a,    11   b  and  12   a  and attaching the electrode of the second chip  16  to the metal sheets  12   a,    12   b  and  13   a  are not shown in  FIGS. 2A-2C . 
         [0005]    In addition, the metal sheet  11   a  is higher than the metal sheet  11   b  such that the metal sheet  11   a  and the metal sheet  11   b  are not located in the same plane. Therefore, in a top view diagram of the package  10  shown in  FIG. 2D , the metal sheet  11   b  is encapsulated inside the package  10 , while the top surface of the metal sheet  11   a  exposes outside the plastic package body of the package  10 . In  FIG. 2B , the metal sheet  12   b  is lower than the metal sheet  12   a  to avoid the metal sheet  12   b  from contacting the back side of the first chip  15 . 
         [0006]    However, a lead frame used for stacking two chips as shown in FIGS.  1  and  2 A- 2 E is complicated and a large amount of metal sheets is required. Therefore, the preparation process is difficult to achieve and the reliability is extremely low, and the volume of the final package is also very large. 
         [0007]    Based on these problems, various embodiments of the invention are proposed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    As shown in attached drawings, the embodiment of the invention is more sufficiently described. However, the attached drawings are only used for explaining and illustrating rather than limiting the scope of the invention. 
           [0009]      FIG. 1  to  FIG. 2E  are schematic diagrams of stacked dual—chip semiconductor device of the prior art. 
           [0010]      FIG. 3A  to  FIG. 3E  are schematic diagrams illustrating of a process of forming stacked dual—chip semiconductor device in the invention. 
           [0011]      FIG. 3F  and  FIG. 3G  are schematic diagrams illustrating the alternative structure of the lead frame and the corresponding stacked dual-ship packaging structure. 
           [0012]      FIG. 4A  to  FIG. 4C  are schematic diagrams illustrating the first chip with and without the interconnection structures or the plastic package layer. 
           [0013]      FIG. 4D  to  FIG. 4E  are schematic diagrams illustrating the second chip with and without the interconnection structures or the plastic package layer. 
           [0014]      FIG. 4F-1  to  FIG. 4F-2  shows a technique of forming a long interconnection structure on the fourth electrode at the front surface of the second chip. 
           [0015]      FIG. 5A  to  FIG. 5C  are schematic diagrams illustrating an alternative process of preparing the stacked dual—chip semiconductor device. 
           [0016]      FIG. 5D  and  FIG. 5E  are schematic diagrams illustrating the alternative structure of the lead frame and the corresponding stacked dual-ship packaging structure. 
           [0017]      FIG. 6A  to  FIG. 6B  are schematic diagrams of the second chip with the interconnection structures and the plastic package layer. 
           [0018]      FIG. 7A  to  FIG. 8B  are schematic diagrams illustrating preparation methods of stacked dual-chip semiconductor device with alternative first and second interconnecting plates and the first and second pins including V-shaped groove. 
           [0019]      FIG. 9  is a cross-sectional diagram of a complete package of the stacked dual-chip semiconductor device of  FIG. 3E . 
           [0020]      FIG. 10A  is a cross-sectional diagram of a complete package of the stacked dual-chip semiconductor device of  FIG. 7B . 
           [0021]      FIG. 10B  is a bottom view of the complete package shown in  FIG. 10A . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0022]    As shown in  FIG. 3A , the lead frame  100  includes a rectangular base  105 , a first pin  101 , a second pin  102 , a third pin  103  and a fourth pin  104  arranged close to the base  105 , where the first pin  101  and the second pin  102  are arranged at two opposite sides, referred at left and right sides, of the base respectively and the third pin  103  and the fourth pin  104  are arranged at one side, referred as a rear side, of the base  105 . For convenience of description, an X-Y-Z Cartesian coordinates with X-Y plane parallel to the major base plane and Z-axis pointing upwards (not shown) is adopted. Specifically, as shown in  FIG. 3B , X axis represents transverse direction and Y axis represents longitudinal direction. The ‘front direction’ is positive direction of the Y axis and the ‘rear direction’ is the negative direction of the Y axis. In  FIG. 3A  and  FIG. 3B , the first pin  101  includes a bonding strip  101   a  extending along the direction parallel to the left side edge of the base  105  and a plurality of pin parts  101   b  connecting to the bonding strip  101   a.  Each pin part  101   b  bends down and then extends horizontally to form an outer pin  101 ′ b,  therefore, the bonding strip  101   a  is in a plane higher than that of the outer pin  101 ′ b.  The second pin  102  has a similar structure as the first pin  101 , which includes a bonding strip  102   a  and a plurality of pin parts  102   b  connecting to the bonding strip  101   a,  each of which bends down and then extends horizontally to form an outer pin  102 ′ b.  The first and second pins  101  and  102  can be formed by stamping or pressing a metal plate. 
         [0023]    The third pin  103  includes an outer pin  103   b  and an inner pin  103   a  transversely extending along the direction parallel to the rear side edge of the base  105 , where the inner pin  103   a  is thinner than the outer pin  103   b.  Similarly, the fourth pin  104  includes an outer pin  104   b  and an inner pin  104   a  transversely extending along the direction parallel to the rear side edge of the base  105 , where the inner pin  104   a  is thinner than the outer pin  104   b.  The inner pin  103   a  of the third pin  103  and the inner pin  104   a  of the fourth pin  104  extended toward each other through the center line between the left side and the right side of the base with the top surfaces of the inner pins  103   a  and  104   a  being coplanar with the front surface of the base  105 . In  FIGS. 3A and 3B , the outer pins  101 ′ b  and the outer pin  103   b  are arranged in parallel, and the outer pin  104   b  and the outer pins  102 ′ b  are arranged in parallel, where the outer pins  101 ′ b,    103   b,    104   b  and  102 ′ b  and the base  105  are located in the same plane. 
         [0024]    Referring to  FIG. 3B , the first chip  106  is flipped and attached on the base  105  such that the first chip  106  extends over an edge of the rectangular base  105  adjacent to the third pin  103  and fourth pin  104  and is partially overlapped with the inner pin  103   a  of the third pin  103  defining an overlapping area  1060  in the first chip  106  but is not overlapped with the fourth pin  104 . 
         [0025]    An example structure of the first chip  106  is shown in  FIGS. 4A-4C . In this embodiment, the first chip  106  is a vertical MOSFET with the current flows from the front side to the back side of the chip or vice versa. As shown in  FIG. 4A , the first chip  106  includes a first electrode  106   a,  as a source electrode, and a second electrode, as a gate electrode, on its front surface. The first electrode  106   a  has to carry larger current, so it has larger contact area than that of the second electrode. In one preferred embodiment, a plurality of interconnection structures  106 ′ a  are formed on the first electrode  106   a  at the front surface of the first chip  106 , and one interconnection structure  106 ′ b  is formed on the second electrode  106   b.  Then, a plastic package layer  106   d  is formed at the front surface of the first chip  106 . The plastic package layer  106   d  is only covered around the side wall of the interconnection structures  106 ′ a  and  106 ′ b,  so that both the interconnection structures  106 ′ a  and  106 ′ b  expose out of the plastic package layer  106   d  as the contact terminals. A back metal layer  106   c,  as a drain electrode, is formed at the back surface of the first chip  106 . In  FIG. 4C , there is no plastic package layer formed at the front surface of the first chip  106 . The plastic package layer  106   d  supports mechanical strength for the wafer so that the wafer can be ground thinner in the grinding step at the wafer level to reduce substrate resistance Rdson. In the alternative embodiments, the interconnection structures  106 ′ a,    106 ′ b,    106 ″ a  and  106 ″ b  can be cylindrical, spherical or wedge-shaped metal bump (such as Au and Cu), or common solder balls and the like. 
         [0026]    Referring back to  FIG. 3B , after the first chip  106  is flip-chip mounted on the base  105 , the second electrode  106   b  at the front surface of the overlapping area  1060  therefore is attached to front surface of the inner pin  103   a  such that the interconnection structure  106 ′ b  ( FIG. 4B ) or  106 ″ b  ( FIG. 4C ) formed on the second electrode  106   b  is aligned with and attached to the inner pin  103   a,  while the plurality of interconnection structures  106 ′ a  ( FIG. 4B ) or  106 ″ a  ( FIG. 4C ) formed on the first electrode  106   a  are attached on the front surface of the base  105 . If the interconnection structures are made of solder-like materials containing tin and lead, the interconnection structures can be directly attached on the inner pin  103   a  and the base  105  by heating. If the interconnection structures are made of non-solder type metal bumps, the interconnection structures are electrically and mechanically connected to the inner pin  103   a  and the base  105  using a binder (not shown), such as auxiliary conductive silver paste or solder paste. 
         [0027]    Referring to  FIG. 3C , a binder, such as a conductive adhesive, is coated on the top surface of the bonding strip  101   a  of the first pin  101  and the back metal layer  106   c  of the first chip  106 , and then a first interconnecting plate  107  is attached to the back metal layer  106   c  and the bonding strip  101   a.  A binder  115  is shown in  FIG. 9 . The first interconnecting plate  107  includes a bridge portion  107   c,  and a main plate portion  107   a  and a sub-plate portion  107   b  located at the two sides of the bridge portion  107   c,  where the main plate portion  107   a  is attached on the first chip  106  with the bottom surface of the main plate portion  107   a  attached to the back metal layer  106   c  through the binder, while the sub-plate portion  107   b  is attached on the bonding strip  101   a  with the bottom surface of the sub-plate portion  107   b  is attached on the top surface of the bonding strip  101   a  through the binder. The main plate portion  107   a  and the sub-plate portion  107   b  with the bridge portion  107   c  form the step structures in order to attach to the first chip  106  and the bonding strip  101   a  respectively. Preferably the free end of the main plate portion  107   a  opposite the sub-plate portion  107   b  extends beyond the edge of the first chip  106  opposite the bonding strip  101   a.    
         [0028]    Referring to  FIG. 3D , the second chip  108  is flipped and attached on the main plate portion  107   a  of the first interconnecting plate  107  such that the second chip  108  extends over edges of the rectangular base  105  and the first interconnecting plate  107  adjacent to the third pin  103  and fourth pin  104  and is partially overlapped with the inner pin  104   a  of the fourth pin  104  defining an overlapping area  1080  in the second chip  108 . 
         [0029]    An example structure of the second chip  108  is shown in  FIGS. 4D-4E . The second chip  108  is also a vertical MOSFET referred as a high-side MOSFET, while the first chip  106  is referred as a low-side MOSFET in the switching circuits such as a synchronous buck converter or half-bridge inverter and the like. As shown in  FIG. 4D , the second chip  108  includes a third electrode  108   a  formed at its front surface of the second chip  108  as a source electrode having larger contact area, a fourth electrode  108   b  formed at its front surface as a gate electrode having a smaller contact area, and a back metal layer  108   c  as a drain electrode formed at the back surface of the second chip  108 . In one embodiment, a plurality of interconnection structures  108 ″ a  are formed on the third electrode  108   a,  and one interconnection structure  108 ′″ b  is formed on the fourth electrode  108   b.  Referring to  FIGS. 3D and 4E , as the top surface of the inner pin  104   a  of the fourth pin  104  is coplanar with the front surface of the base  105 , the fourth electrode  108   b  located at the front surface of the overlapping area  1080  is not directly connected to the top surface of the inner pin  104   a  because there is gap between them. Therefore, for electrically connecting the fourth electrode  108   b  and the inner pin  104   a,  an interconnection structure  108 ′″ b  is formed along the vertical direction which must be longer than the interconnection structure  108 ″ a  ( FIG. 4E ). 
         [0030]    In  FIG. 3D , after the second chip  108  is flipped and attached on the main plate portion  107   a  of the interconnecting plate  107 , the fourth electrode  108   b  is located at the front surface of the overlapping area  1080  of the second chip  108 , and the interconnection structure  108 ′″ b  is positioned between the fourth electrode  108   b  and the inner pin  104   a  of the fourth pin  104  for connecting the fourth electrode  108   b  and the inner pin  104   a.  The plurality of interconnection structures  108 ″ a  ( FIG. 4E ) formed on the third electrode  108   a  are connected on the top surface of the main plate portion  107   a  of the interconnecting plate  107 . 
         [0031]      FIGS. 4F-1  to  4 F- 2  show a method of forming the interconnection structure  108 ′″ b  by ball bonding techniques. Firstly, a metal wire  160  is fed in to a capillary  150 . The metal wire is melted at the tip of the capillary  150 , for example by oxy-hydrogen flame or a high-voltage electric charge, thus the tip of the wire forms into a ball because of the surface tension of the molten metal. The ball is quickly solidified as a standard metal ball  181  and is released on a bonding pad  170  (such as third electrode and fourth electrode of the chip). As shown in  FIG. 4F-2 , the long interconnection structure  108 ′″ b  is formed as a second metal ball  180  is formed and stacked on the first metal ball  181 .  FIG. 4F-2  shows an example of forming an interconnection structure  108 ′″ b  with only two metal balls formed. However, there are more than 2 metal balls maybe needed depending on the height of the interconnection structure  108 ′″ b,  which can be adjusted by number of the metal balls stacked and the diameter of each metal ball. The height of the interconnection structure is approximately equal to number N of ball×diameter Φ of ball, and moreover, the diameter Φ of ball can be further adjusted by the diameter r of the metal wire  160 . 
         [0032]    The metal ball  181  can be used as the interconnection structure  108 ″ a  formed in the third electrode  108   a  as shown in  FIG. 4E  and a stack of metal balls  181  can be used as the interconnection structure  108 ′″ b  formed on the fourth electrode  108   b.  The interconnection structure  108 ″ a  and the interconnection structure  108 ′″ b  with different height can be made with the bonding ball technique as described above at the same time if the interconnection structures  108 ″ a  and  108 ′″ b  are made of the same material. Alternatively, the interconnection structure  108 ′″ b  can be a cylindrical bump, which is longer than the interconnection structure  108 ″ a,  directly formed on the fourth electrode  108   b.    
         [0033]    The interconnection structure  108 ′″ b  is relatively long, therefore if it is made of solder material containing lead and tin, it is easily broken causing the disconnection of the current path. Therefore, the interconnection structures  108 ″ a  and  108 ′″ b  are preferably made of copper or gold and the like, and the interconnection structures  108 ′″ b  and  108 ″ a  are attached on the inner pin  104   a  and the main plate portion  107   a  by a binder coated on the top surface of the inner pin  104   a  and the main plate portion  107   a  respectively. 
         [0034]    Referring to  FIG. 3E , a binder (not shown) is coated on the top surface of the bonding strip  102   a  of the second pin  102  and the back metal layer  108   c  of the second chip  108 , and then a second interconnecting plate  109  is attached on the back metal layer  108   c  and the bonding strip  102   a.  The second interconnecting plate  109  includes a bridge portion  109   c,  and a main plate portion  109   a  and a sub-plate portion  109   b  located at the two opposite longer sides of the bridge portion  109   c,  where the main plate portion  109   a  is attached on the second chip  108  with the bottom surface of the main plate portion  109   a  connected to the back metal layer  108   c  through the binder and the sub-plate portion  109   b  is attached on the bonding strip  102   a  with the bottom surface of the sub-plate portion  109   b  connected to the top surface of the bonding strip  102   a  through the binder. The main plate portion  109   a  and the sub-plate portion  109   b  with the bridge portion  109   c  form the step structures in order to attach to the second chip  108  and the bonding strip  102   a  respectively. 
         [0035]    In the embodiment shown in  FIGS. 3A-3E , both the third pin and the fourth pin are arranged at the rear side of the base and extend along the direction parallel to the rear side edge of the base in two opposite sides of the center line of the base respectively. In an alternative embodiment, as shown in  FIGS. 3F and 3G , the third pin  103  is arranged at the rear side and extends along the direction parallel to rear side of the base and the fourth pin  104  is arranged at the front side and extends along the direction parallel to the front side of the base respectively in two opposite sides of the center line of the base respectively. 
         [0036]    Referring to  FIG. 5A , the lead frame  100 ′ has a similar structure as the lead frame  100  of  FIG. 3A  excepting the structure of the fourth pin  104 . The fourth pin  1040  of the lead frame  100 ′ includes an outer pin  1040   b  and an inner pin  1040   a  that transversely extends along the rear side edge of the base  105  toward the third pin  103 . The inner pin  1040   a  is located in a plane higher than that of the outer pin  1040   b  so that the top surfaces of the inner pin  1040   a  and the main plate portion  107   a  of the first interconnecting plate  107  are coplanar after the first interconnecting plate  107  is attached on the second chip  106  as shown in  FIG. 5B . As a result, the interconnection structures  108 ′ b  and  108 ″ b  with same length are formed on the third and fourth electrodes  108   a,    108   b  of the second chip  108  as shown in  FIGS. 6A and 6B . In  FIG. 5C , after the second chip  108  is flipped and attached on the interconnecting plate  107 , the fourth electrode  108  is overlapped with the inner pin  1040   a  defining the overlapping area  1080  in the second chip  108 . 
         [0037]    In the embodiment shown in  FIGS. 5A-5C , both the third pin and the fourth pin are arranged at the rear side of the base and extend along the direction parallel to the rear side edge of the base in two opposite sides of the center line of the base respectively. In an alternative embodiment, as shown in  FIG. 5D and 5E , the third pin  103  is arranged at the rear side and extends along the direction parallel to rear side of the base and the fourth pin  1040  is arranged at the front side and extends along the direction parallel to the front side of the base respectively in two opposite sides of the center line of the base respectively. 
         [0038]    In  FIG. 6A , the plurality of interconnection structures  108 ′ a  are formed on the third electrode  108   a  at the front surface of the second chip  108  and one interconnection structure  108 ′ b  is formed on the fourth electrode  108   b.  A plastic package layer  108   d  is formed at the front surface of the second chip  108  and only surrounds the side wall of the interconnection structures  108 ′ a  and  108 ′ b  but not covers them completely so that both the interconnection structures  108 ′ a  and  108 ′ b  expose out from the plastic package layer  108   d  as the contact terminals. Alternatively, in  FIG. 6B , the plurality of interconnection structures  108 ″ a  are formed on the third electrode  108   a  and interconnection structure  108 ″ b  is formed on the fourth electrode  108   b,  and there is no plastic package layer formed at the front surface of the second chip  108 . The interconnection structures  108 ′ a,    108 ′ b,    108 ″ a  and  108 ″ b  can be cylindrical, spherical or wedge-shaped metal bumps (such as Au and Cu), or common solder balls and the like. 
         [0039]    Referring to  FIG. 7A , the lead frame  200  has a similar structure as the lead frame  100  shown in  FIG. 3A  excepting that the bonding strip  201   a  and the outer pin  201   b  of the first pin  201  are coplanar, and the bonding strip  202   a  and the outer pin  202   b  of the second pin  202  are also coplanar. In addition, a groove  201   a - 1  extending along the direction parallel to the left side edge of the base  205  is formed on the top surface of the bonding strip  201   a,  and a groove  202   a - 1  extending along the direction parallel to the right side edge of the base  205  is also formed on the top surface of the bonding strip  202   a.  In one embodiment, the grooves  201   a - 1  and  202   a - 1  are V-shaped. 
         [0040]    In some embodiments, grooves  202   c  for locking molding are etched or pressed on the lower surface of the bonding strip  202   a  of the second pin  202  as shown in  FIG. 7A  and divide the lower surface of the bonding strip  202   a  into a plurality of separated areas  202   a - 2  in the same number as the external pins  202   b  (as shown in  FIG. 10B ). The grooves  202   c  may be formed in areas between the outer pin  202   b  so that each area  202   a - 2  is fused with the lower surface of the outer pin  202   b  into one surface. As shown in  FIG. 10B , the first pin  201  may have the similar structure as well. In  FIG. 7B , the difference between the first interconnecting plate  207  and the first interconnecting plate  107  in  FIG. 3E  is that the main plate portion  207   a  of the first interconnecting plate  207  is connected with a holding plate  207   b  slanting downward with one end of the holding plate  207   b  being connected to one end of the main plate portion  207   a  and another end of the holding plate  207   b  being embedded into the groove  201   a - 1  of the bonding strip  201   a.  Similarly, the difference between the second interconnecting plate  209  and the second interconnecting plate  109  in  FIG. 3E  is that the main plate portion  209   a  of the second interconnecting plate  209  is connected with a holding plate  209   b  slanting downward with one end of the holding plate  209   b  being connected to one end of the main plate portion  209   a  and another end of the holding plate  209   b  being embedded into the groove  202   a - 1  of the bonding strip  202   a.  Typically, conductive binders are filled into the grooves  201   a - 1  and  202   a - 1  to increase the conductive capability and mechanical connection strength between the first interconnecting plate  207  and the bonding strip  201   a  and between the second interconnecting plate  209  and the bonding strip  202   a  respectively. 
         [0041]    Referring to  FIG. 8A , the main difference between the lead frame  200 ′ and the lead frame  200  as shown in  FIG. 7A  is that the structure of the fourth pin  2040  of the lead frame  200 ′ includes an outer pin  2040   b  and an inner pin  2040   a,  where the inner pin  2040   a  transversely extends along the direction parallel to the rear side edge of the base  205 . The plane of inner pin  2040   a  is higher than that of the outer pin  2040   b  so that the top surface of the inner pin  2040   a  is coplanar with the top surface of the main plate portion  207   a  of the first interconnecting plate  207  after the first interconnecting plate  207  is attached on the first chip  106 . In  FIG. 8B , after the second chip  108  is flipped and attached on the main plate portion  207   a  of the first interconnecting plate  207 , the second chip  108  is partially overlapped with and connected to the inner pin  2040   a  of the fourth pin  2040  defining an overlapping area  1080  in the second chip  108 . 
         [0042]      FIG. 9  is a cross-sectional diagram illustrating a package structure of the device shown in  FIG. 3E . As shown in  FIG. 9 , a plastic package body  120  is formed to encapsulate the first chip  106 , the second chip  108 , the first interconnecting plate  107 , the second interconnecting plate  109 , interconnection structures  106 ″ a,    106 ″ b,    108 ″ a  and  108 ″ b  and a portion of lead frame  100 . The plastic package body also covers portions of the first pin  101 , the second pin  102 , the third pin  103 , the fourth pin  104  and the base  105  with the back surface of the base  105  and the bottom surface of the outer pin  101 ′ b,    103   b,    104   b  and  102 ′ b  exposing out from the plastic package body  120 . If the plastic package layer  106   d  is previously formed to cover the front of the first chip  106  (as shown  FIG. 4B ), plastic package layer  106   d  will cover the interconnection structures  106 ′ a  and  106 ′ b.  Similarly, if the plastic package layer  108   d  is previously formed to cover the front of the second chip  108  (as shown in  FIG. 6A ) and second chip  108  is flipped and attached on the top surface of the inner pin  1040   a  of the lead frame  100 ′ as shown in  FIG. 5C , plastic package layer  108   d  will cover the interconnection structures  108 ′ a  and  108 ′ b.    
         [0043]      FIG. 10A  is a cross-sectional diagram of a package structure of the device shown in  FIG. 7B , and  FIG. 10B  is a bottom view of the package structure of  FIG. 10A . As shown in  FIG. 10A , a plastic package body  220  is formed to encapsulating the first chip  106 , the second chip  108 , the first interconnecting plate  207 , the second interconnecting plate  209 , the interconnection structures  106 ″ a,    106 ″ b,    108 ″ a  and  108 ″ b  and a portion of lead frame  200 . The plastic package body also covers a portion of the first pin  201 , the second pin  202 , the third pin  203 , the fourth pin  204  and the base  205  with the back surface of the base  205 , the bottom surface of the outer pin  201   b,    203   b,    204   b  and  202   b,  and the area  202   a - 2  on the bottom surface of the bonding strip  202   a  and the area  201   a - 2  on the bottom surface of the bonding strip  201   a  exposing out from the plastic package body  220 . Optionally, the upper surface of the main plate portion  209   a  of the second interconnecting plate  209  can also expose out form the plastic package material  220  for heat dissipation. 
         [0044]    The above detailed descriptions are provided to illustrate specific embodiments of the present invention and are not intended to be limiting. Numerous modifications and variations within the scope of the present invention are possible. The present invention is defined by the appended claims.