Abstract:
A CCD background subtractor having a first charge storage arrangement for detecting, during periodic sampling intervals, the peak value of an applied input signal, and a second charge storage arrangement into which charge representative of said peak value is periodically transferred and held. A third charge storage arrangement also receives the applied input signal and is controlled as a function of the charge held in the second charge storage arrangement such that the output signal from the third charge storage arrangement is representative of the difference between the applied input signal and the peak value thereof sampled during a prior sampling interval.

Description:
BACKGROUND OF THE INVENTION 
     This invention is in the field of background signal subtractors using CCD principles. 
     In many applications it is desirable to delete the DC components of an applied signal, while passing AC signals which have encoded thereon the information to be processed. For example, in imaging systems the DC background signal comprises a large portion of the output signal from the imaging sensor while the useful imaging information is contained in the relatively small, high frequency, portion of the sensor&#39;s output signal. In such applications, economy and efficiency of signal processing may be realized by removing the background signal during an early stage of the signal processing operations. 
     Background subtractors in general are known in the art, such is for example, those which include AC couplers that make use of capacitors and the like. However, the prior art does not include CCD type background subtractors for transferring the AC portion of a signal which may contain DC components; and as compared to CCD devices, commonly used background subtractors are bulky, heavy and expensive. Also, conventional background subtractors or capacitors have the disadvantage of being limited to a fixed or predetermined transfer characteristics. 
     SUMMARY OF THE INVENTION 
     A major objective of this invention is to provide by means of charge coupled device background subtractors which reject DC (or low frequency) signal components present in an input signal while passing the AC (higher frequency) signal components. 
     Briefly, according to the invention, a background subtractor is mechanized by utilizing a semiconductor substrate with an overlying electrically insulating film, wherein diffusions are present in the substrate and gating electrodes are provided within the overlying insulating film. 
     Unlike the prior art, CCD background signal subtractors in accordance with the present invention have the desirable characteristics of a variable roll off frequency (the three decibel attenuation point of the subtractor&#39;s frequency response curve). Hence such CCD type of background subtractors may be more readily tailored to design parameters of the system in which they are used. 
     Background subtractor&#39;s in accordance with the present invention include a peak value detector and a sample and hold circuit. The peak value detector (first charge storage arrangement) consists of a diffusion in the substrate and several gates embedded in the overlying insulating layer together with the voltages applied to the respective diffusion and gates. Such peak value detection circuit feeds the sample and hold circuit (second charge storage arrangement) which consists of another diffusion element in the substrate and several gates in the insulating layer. The output of the sample and hold circuit provides a voltage to the non-inverting input gate within the insulating layer, wherein such gate voltage controls the amount of charge in a charge well directly below such gate. 
     The peak positive value of an applied input signal is detected within the peak value detector as the minimum charge level in a first charge well which is initially precharged by an externally connected power source. Potential barriers are provided on either side of the well, so that if the voltage input to the peak value detector is more positive than the initial input voltage to such peak detector, then one of the potential barriers will drop, and charge will drain out over such dropped barrier into an adjacent storage area. Draining of the well continues until the charge remaining in the well is at a potential equal to the potential of the dropped barrier. 
     The charge in said first storage well is transferred to, held and monitored by a diffusion in the substrate (second charge storage arrangement), which diffusion provides a reference voltage to a non-inverting input of a differential amplifying circuit (third charge storage arrangement). 
     In the third charge storage arrangement the reference voltage is fed to a gate electrode above a third storage well within the film. Also fed to the third charge storage arrangement is the applied input signal and the third charge storage arrangement responds thereto so as to produce an output signal which is indicative of the difference between the applied input signal and the reference voltage developed during a prior peak detector interval. The background subtractor thereby reduces DC and low frequency components present in the applied input signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a plan view of a CCD device in accordance with the invention. 
     FIG. 2 is a cross-section view taken at plane 2--2 of FIG. 1 showing details of the device structure. 
     FIG. 2a is a potential profile diagram of the cross-section view portion of FIG. 2. 
     FIG. 3 is a cross-section view taken at plane 3--3 of FIG. 1 showing further structural details of the CCD device. 
     FIG. 3a is a potential profile diagram of the cross-section view portion of FIG. 3. 
     FIG. 4 is a block diagram showing the various DC and clock voltages fed to the CCD device. 
     FIGS. 5 and 5a are waveform diagrams showing the various clock, reference, output and input voltages at various portions of the CCD device. 
     FIGS. 6 and 6a constitute a cross-section view of a portion of the CCD device connected to external circuitry and a potential profile thereof respectively to comprise a functional diagram so as to enable the operation of such device to be better understood. 
    
    
     DETAILED DESCRIPTION 
     Referring to FIGS. 1, 2, 2a, 3, 3a, 4, 5 and 5a a charge transfer (sometimes referred to as a charge coupled) device 10 is provided for subtracting out a background signal from an applied analog signal voltage v in . A section of device 10, designated at 50 in FIG. 6 functions as a CCD input charge modulator of device 10. 
     Device 10 has a semiconductor body 12, generally of silicon, however other semiconductor materials such as germanium may be utilized as body 12. Body 12 is shown as a P+ conductivity doped silicon material, however it is understood that other conductivity type materials such as N types may be used. 
     Diffusion 16 is partially embedded within body 12 and is connected to and fed by DC voltage source 60 (FIG. 4) with respect to ground potential 61. One output from source 60 is designated V ddl , and it gives rise to potential charge area 152 (FIG. 2a) with a surface potential (φ s ) shown by level 154. 
     It should be noted that potential area 152 is not a charge well because charge cannot be stored thereat and such an area is essentially a charge drain or sink. This is also true for areas 100, 200 and 270 which are charge drains or sinks. 
     Conductor 13 is connected to substrate semiconductor body 12 which is interconnected to and fed by DC voltage -V s  from power source 60, with the positive side of battery V s  being a ground potential, thus providing a negative bias to substrate 12. 
     Diffusion 14 is partially embedded within body 12 and is interconnected to and fed by clock voltage source φ c  from power source 60. The clock waveform φ c  is indicated by waveform D in FIG. 5 and provides a periodice input charge source by alternating the levels of area 100 between surface potential levels 102 and 110. 
     Diffusion 15 is partially embedded within body 12 and provides analog voltage V ref  to gate 40 in the form of waveform G. 
     Diffusion 17 is partially embedded within body 12 and is connected to and fed by clock voltage φ a  from power source 60. The clock waveform of φ a  is indicated by waveform B in FIG. 5 and provides a periodic input charge by alternating the levels of area 200 between surface potential levels 202 and 210. 
     An electrically insulating film 32 of SiO 2  is deposited over layer 12 and forms an interface 22 with layer 12 and the upper surfaces of each of diffusions 14, 15, 16, 17, 18 and 19. It is understood that other types of insulating films may be used. 
     Gate electrode 33 is embedded in film 32 and is connected to external input signal v in , which is typified by waveform A as shown in FIG. 5, v in  giving rise to barrier 106 at potential level 108. 
     Electrode 34 is adjacent to electrode 33, embedded in film 32 and is connected to and fed by a DC voltage V l  from source 60, which voltage V l  gives rise to potential well 116 at level 120. 
     Electrode 35, which is adjacent to electrode 34, is embedded in film 32 and is connected to a source of clock voltage φ d  from power source 60. Said power source provides clocking waveform E, shown in FIG. 5, to electrode 35 giving rise to potential level 126 when waveform E is at a zero voltage level, and giving rise to level 128 when waveform E is at a positive voltage level, therefore creating barrier 124. 
     Gate electrode 36 is adjacent to gate electrode 35 and is embedded in film 32 and connected to and fed by DC voltage V 5  from source 60 giving rise to surface potential 136 of a charge in sense area 134. Diffusion 15 senses surface potential 138 of the charge in area 134. 
     Gate electrode 37 is adjacent to electrode 36 and is embedded in film 32 and is powered by φ rstl  of power source 60. The voltage waveform F constitutes φ rstl , and consists of a series of rectangular pulses which provide a reset function to device 10, giving rise to surface potential barrier 140 at level 142 when φ rstl  is at zero voltage and to surface potential level 48 when φ rstl  is at a positive voltage level. 
     Gate electrode 38 is adjacent to diffusion 17 and is embedded in film 32 and connected to and fed by voltage source v in , which gives rise to surface potential barrier 206 at level 208. 
     Gate electrode 39 is adjacent to gate electrode 38 and is embedded in film 32 and connected to and fed by DC voltage V 2  from source 60, giving rise to potential well 224 at level 226. 
     Gate electrode 40 is adjacent to gate electrode 39 and is embedded in film 32 and connected to and fed by diffusion 15 giving rise to well 216 at level 220. 
     Gate electrode 41 is adjacent to gate electrode 40 and is embedded in film 32 and is connected to a clock voltage φ b  from power source 60. Said power source provides clocking waveform C to such electrode 41 giving rise to potential level 232 when waveform C is at zero volts, and to level 234 when waveform C is at a positive voltage level and therefore creating potential barrier 230. 
     Adjacent to electrode 41 is diffusion 18 partially embedded within body 12 to provide analog output voltage V out  as exemplified by waveform H. 
     Gate electrode 42 is adjacent to diffusion 18 and is embedded in film 32 and is connected to terminal φ rst2  of power source 60. The voltage at φ rst2  is illustrated by waveform J and consists of a series of rectangular pulses which provide a reset function to device 10. Such voltage φ rst2  gives rise to surface potential barrier 260 at level 262 when φrst2 is a zero voltage, and to surface potential level 264 when φ rst2  is at a positive voltage level. 
     Diffusion 19 is adjacent to gate electrode 42 and is partially embedded within body 12 and is connected to and fed by DC voltage V dd2  from power source 60 giving rise to potential charge area 270 with a surface potential (φ s ) having level 272 at semiconductor interface 22. 
     Referring to FIG. 5a, such figure is drawn to a longer time base than FIG. 5, showing some of the principle functions provided by this subtractor in more gross form. 
     Waveform A&#39; shows that the subtractor input V in  accepts an AC signal riding on a DC base. Corresponding clock D&#39; has a lower repetitive rate than clock waveform D in FIG. 5. The clock rate for waveform B&#39; is the same as its rate shown in FIG. 5. The FIG. 5a rate ratio of φ a  /φ c  &gt;&gt;1, compared to the same ratio of FIG. 5 waveforms. Accordingly, the subtractor&#39;s low frequency response is a function of φ c , φ d , φ rst1  as in FIG. 5. Hence, the longer the time duration between φ c  pulses, the lower the low frequency 3 db. point roll off frequency. 
     In FIG. 5a, input voltage v in  is shown in waveform A&#39; as having an AC signal with a DC off-set, and the output voltage V out  is shown as waveform H&#39; being devoid of such input DC component. Consequently, more repetitions of the CCD output of this subtractor is observed by viewing FIG. 5a is compared to FIG. 5. 
     Referring also to FIGS. 6 and 6a, it is to be noted that this background subtractor has inherently embodied a differential amplifier denoted at 50 in FIG. 6. Such differential amplifying function is obtained by virtue a signal v in  being applied as an inverting input thereof to input gate 38. The other input to the device for obtaining the differential amplifying function is the non-inverting input V ref  fed to input gate 40 from the sample and hold circuit. V ref  is created by gates 35, 36 and 37 and the signals applied thereto as well as diffusion 15. Voltage V ref  is applied from diffusion 15 to gate 40. When functioning as a background subtractor, this device also rejects the DC component in any signal applied to gates 38 and 40. Thus the DC component does not appear as part of the charge in well 216, and consequently in the output voltage V out . Thus the signals applied to gates 38 and 40 modulate the charge in well 216. 
     The DC component of the input signal is computed by the peak detector and sample and hold circuit during a substantial operating period of the device, and subsequently that peak value is applied as a voltage to gate 40. 
     At time t o , φ rst1 , represented by waveform F, makes a transition from zero to a positive potential, moving barrier 140 from level 142 to level 148 and causing any charge in well 134 to flow to charge area 152 according to charge direction flow arrow 150. Also at time t o , clock φ b  represented by waveform C makes a transition from a positive potential to zero level, moving barrier 230 from level 234 to level 232. 
     At time t 1 , voltage φ rst1 , represented by waveform F, makes a transition from a positive to zero potential causing barrier 140 to change from level 148 to level 142 and making well 134 ready to subsequently receive a charge. At such time period, clock voltage φ d  represented by waveform E, makes a transition from zero to a positive potential, causing barrier 124 to change from level 126 to level 128 and allowing charge in well 116 to flow into well 134 as shown by charge direction flow arrow 132, and providing a potential level 138 of the charge in well 134. This charge is sensed and appears as voltage V ref  depicted by waveform G. The charge level is maintained according to waveform G from t 1  to t 15  so that the reference voltage V ref  is likewise maintained during that period. 
     At time t 2 , as shown by waveform E, clock voltage φ d  makes a transition from a positive potential to zero, moving barrier 124 from level 128 to level 126. In subsequent excursions of v in  and clock voltage φ c  the charge in well 134 will not be affected until clock voltage φ d  again makes a transition from zero to a positive potential. 
     At time t 3 , clock φ c  represented by waveform D makes a transition from a positive potential to zero, moving charge in area 100 from level 102 to level 110 and thus allowing a substantial charge quantity to flow over potential barrier 106 into well 116 in direction flow of arrow 112. In a like manner clock voltage φ a  represented by waveform B makes a transition from a positive to zero potential level, moving charge in area 200 from level 202 to level 210 and thus allowing a substantial quantity of charge to flow over potential barrier 206 into well 216 as shown by direction flow arrow 212. Reset clock voltage φ rst2  represented by waveform J, makes a transition from 0 to a positive potential, moving potential barrier 260 from level 262 to level 264 and allowing charge in well 250 to flow into charge drain area 270 which is maintained at charge level 272. Direction of charge flow is shown by arrow 256. When the charge in well 250 is drained off the charge potential therein will shift to level 254, and V out  depicted by waveform H will exhibit a transition from a specific potential level to a more positive potential. 
     At time t 4  clock voltage φ rst2  represented by waveform J, makes a transition from a positive to zero potential moving potential barrier 260 from level 264 to level 262. At the same time clock voltage φ c  represented by waveform D, makes a transition from zero to a positive potential thereby moving charge in area 100 from level 110 to level 102. Charge flow arrow 114 depicts such charge movement direction. Well 116 is charged to level 118, which level 118 is equal to potential barrier level 108. It should be noted that well 116 will not be drained of charge until several subsequent clock cycles have elapsed. From t 4  to such later time, the charge will spill over barrier 106 into area 100, caused by the applied voltage v in  as represented by waveform A. Any transition more positive than applied at time t 4  will cause charge to spill over from well 116 into area 100 thereby computing the peak signal as denoted in FIG. 6 during such subsequent perturbation of signal v in . Also at time t 4  clock voltage φ a  represented by waveform B, makes a transition from zero to a positive potential, moving charge in source area 200 from level 210 to level 202. The charge level in well 216 will be moved to level 218, which is equal to level 208, and excess charge will flow over barrier 206. Charge direction flow arrow 214 denotes charge travel. It should be noted that well 216 and barrier 206, created by voltage v in  at gate 38 and barrier 220 created by voltage V ref  at gate 40, constitute a differential charge modulator, the functions performed thereby being shown in FIGS. 6 and 6a. The charge thus generated may be observed at device output as a voltage V out . The reference signal V ref  is a DC voltage generated by diffusion 15 which is connected to gate 40. Diffusion 15 is the means by which the charge in well 134 is sensed. New DC reference voltages are established at time t 1  and t 16 . Such new DC reference voltage are maintained until the device is reset. Hence, for example, the new reference voltage that was established at t 1  is reset at t 15  . It should be noted that charge in well 134 during times t 1  to t 15  was created by a peak detector comprising gates 33 and 34, well 116 and diffusion 14 during a period previous to t 1 . 
     It should be further noted that during period t 4  to t 16  the peak detector circuit computes the peak value of charge to be transferred to sense area 134 at time t 16 . Sense area 134 is also a well for storing charge therein. 
     At time t 5  clock voltage φ B  represented by waveform C, makes a transition from a zero to positive potential thus moving potential barrier 230 from level 232 to level 234 and allowing the differential signal charge in well 216 to transfer into output sense area 250 as denoted by charge direction flow arrow 240. This charge is now observed as an output voltage V out  depicted by waveform H. Like transitions occur at times t 9 , t 14  and t 20 . 
     At time t 6  voltage v in  is shown to have a less positive going transition. Clock voltage φ b  as shown in waveform C, makes a transition from a positive to a zero potential, thus moving potential barrier 230 from level 234 to 232. Like transitions also occur at time t o , t 11 , t 15 , t 21  and at subsequent time periods not shown in FIG. 5. 
     At time t 7  clock reset voltage φ rst2  depicted by waveform J, makes a transition from a zero to a positive potential thereby moving potential barrier 260 from level 262 to level 264 and allowing an output signal to transfer out of output sense area 250 into charge sink area 270 as denoted by charge direction flow arrow 256. This charge transfer causes V out  signal as depicted by waveform H, to shift to a more positive potential. It should be noted that this resetting operation occurs at times t 3  -t 4 , t 7  -t 8 , t 12  -t 13 , t 18  -t 19  and t 22  -t 23 .