Abstract:
The present disclosure discloses a decoding apparatus for a semiconductor memory device and an enable method therefor which can remove unnecessary delay between an address inputted to a decoder and a decoder control signal by enabling the decoder in response to the decoder control signal generated by combining an address latch control signal and an internal address according to an output signal from an address latch. The decoding apparatus for the semiconductor memory device includes an address latch to output first and second latch addresses and an internal address by latching an input address in response to an address latch control signal, an address transition detector to generate a decoder control signal by operating the address latch control signal and the internal address according to the first and second latch addresses, and a decoder enabled according to the decoder control signal.

Description:
TECHNICAL FIELD 
     The present disclosure relates to a decoding apparatus for a semiconductor memory device, and more particularly, to an improved decoding apparatus configured to decode an address in the DRAM. 
     BACKGROUND 
     A semiconductor memory device includes an address latch and a decoder. One example of improving a driving operation between the address latch and the decoder has been disclosed in Japanese Patent Laid-Open 11-16362 ‘Memory data read circuit’ for controlling driving of an address decoding unit by using a built-in pulse generating circuit. 
     The address latch and the decoder are controlled to guarantee validity of addresses input to the decoder. FIGS. 1 and 2 are block diagrams illustrating a conventional decoding apparatus for a semiconductor memory device. 
     Referring to FIG. 1, the conventional decoding apparatus includes an address latch  10  enabled according to an address latch control signal XAE for transmitting inputted addresses ADD&lt;0-N&gt; to a special bank, a delay unit  11  for delaying the address latch control signal XAE and generating a decoder control signal XAED, and a decoder  12  enabled according to the decoder control signal XAED for decoding latch addresses BXAZ&lt;0-N&gt; of the address latch  10 . As illustrated in FIG. 2, the decoder  12  can be divided into a predecoder  13  and a main decoder  14 . 
     Still referring to FIG. 1, when the address latch  10  receives an active command, it latches the inputted address ADD&lt;0-N&gt; in response to the address latch control signal XAE of the selected bank. Even if the inputted address ADD&lt;0-N&gt; is varied, the address latch  10  constantly maintains the output BXAZ&lt;0-N&gt; until it receives a precharge command. 
     As described above, the conventional decoding apparatus enables the decoder  12  by using the decoder control signal XAED obtained by delaying the address latch control signal XAE. That is, in order to guarantee validity of the addresses BXAZ&lt;0-N&gt; input to the decoder  12  (or predecoder  13 ), the decoder control signal XAED is generated by delaying the address latch control signal XAE for a predetermined time. 
     However, the state of the output signal is varied due to variations of the process, temperature and voltage, and thus the address latch control signal XAE must be sufficiently delayed with a margin in order to generate the decoder control signal XAED. When the delay time is deficient, a glitch is generated in the output of the decoder  12 , thereby increasing current consumption or generating a mis-operation. 
     As a result, the conventional decoding apparatus for the semiconductor memory device generates signal transmission delay between the address latch and the decoder, and thus fails to improve an operation speed. 
     SUMMARY OF THE DISCLOSURE 
     A decoding apparatus configured to remove unnecessary delay between an address input to a decoder and a decoder control signal by enabling the decoder in response to the decoder control signal generated by logically combining an address latch control signal and an internal address according to an output signal from an address latch is disclosed herein. 
     The decoding apparatus for a semiconductor memory device includes: an address latch to output first and second latch addresses and an internal address by latching an input address in response to an address latch control signal; an address transition detector to generate a decoder control signal by logically operating the address latch control signal and the internal address according to the first and second latch addresses; and a decoder enabled according to the decoder control signal. 
     An enable method of a decoding apparatus for a semiconductor memory device includes the steps of: generating first and second latch addresses and an internal address by latching an input address in response to an address latch control signal; generating a decoder control signal by logically operating the address latch control signal and the internal address according to the first and second latch addresses; and enabling a decoder in response to the decoder control signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The disclosure will be described in terms of several embodiments to illustrate its broad teachings. Reference is also made to the attached drawings. 
     FIGS. 1 and 2 are block diagrams respectively illustrating a conventional decoding apparatus for a semiconductor memory device; 
     FIGS. 3 and 4 are block diagrams respectively illustrating a decoding apparatus for a semiconductor memory device in accordance with a preferred embodiment of the present disclosure; 
     FIG. 5 is a circuit diagram illustrating an address latch of FIGS. 3 and 4; 
     FIG. 6 is a circuit diagram illustrating an address transition detector of FIGS. 3 and 4; 
     FIGS. 7 a  and  7   b  are circuit diagrams respectively illustrating an XOR logic circuit of FIG. 6; 
     FIG. 8 is a truth table of the XOR logic circuit of FIGS. 7 a  and  7   b;    
     FIG. 9 is a circuit diagram illustrating a decoder of FIG. 3; and 
     FIGS. 10 to  13  are layout diagrams respectively illustrating the decoding apparatus for the semiconductor memory device in accordance with the preferred embodiment of the present disclosure. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present disclosure will be described in detail with reference to the accompanying drawings. In accordance with the present disclosure, when an address latch is enabled to latch a valid address according to an address latch control signal, an address transition detector detects that the latched valid address is output according to the address latch control signal, thereby generating a decoder control signal to enable a decoder. 
     FIGS. 3 and 4 are block diagrams respectively illustrating the decoding apparatus for the semiconductor memory device in accordance with a preferred embodiment of the present disclosure. In FIGS. 3 and 4, ADD&lt;0-N&gt; denotes external input addresses inputted to a chip according to a chip operation mode, and ADDLT&lt;0&gt; denotes an internal address obtained by latching the input address. BXA&lt;0&gt; and BXAZ&lt;0&gt; denote latch addresses generated in the chip. XAE is an address latch control signal to enable or disable an address latch  20 , and latch a valid address in a specific time. XPDEN denotes a decoder control signal to enable or disable a decoder  40  (or predecoder  50 ). 
     Referring to FIG. 3, the decoding apparatus includes the address latch  20 , the address transition detector  30  and the decoder  40 . The address latch  20  includes address latches &lt;0&gt; and &lt;1-N&gt;. 
     The address latch &lt;0&gt; is enabled according to the address latch control signal XAE, to latch the address ADD&lt;0&gt; and generate the latch addresses BXA&lt;0&gt; and BXAZ&lt;0&gt; and the internal address ADDLT&lt;0&gt;. The address latch &lt;1-N&gt; is enabled according to the address latch control signal XAE, to latch the address ADD&lt;1-N&gt; and generate a latch address BXAZ&lt;1-N&gt;. The address transition detector  30  logically operates the address latch signal XAE and the internal address ADDLT&lt;0&gt; in response to the latch addresses BXA&lt;0&gt; and BXAZ&lt;0&gt;, and generates the decoder control signal XPDEN. The decoder  40  is enabled according to the decoder control signal XPDEN. 
     Here, when the address latch &lt;0&gt; is disabled in response to the address latch control signal XAE, the address latch &lt;0&gt; constantly maintains the latch address BXAZ&lt;0&gt; regardless of the input address ADD&lt;0&gt;. Conversely, when the address latch &lt;0&gt; is enabled in response to the address latch control signal XAE, the address latch &lt;0&gt; maintains the latch address BXAZ&lt;0&gt; corresponding to the address ADD&lt;0&gt; inputted in an enable time. The address latch &lt;1-N&gt; is operated in the same manner as the address latch &lt;0&gt;. 
     When the decoder  40  is enabled in response to the decoder control signal XPDEN, the output corresponding to the inputted address BXAZ&lt;0-N&gt; is determined. Conversely, when the decoder  40  is disabled in response to the decoder control signal XPDEN, all the outputs are maintained in the same state regardless of the inputted address BXAZ&lt;0-N&gt;. 
     FIG. 5 is a circuit diagram illustrating the address latch &lt;0&gt; of FIGS. 3 and 4. The address latch &lt;1-N&gt; has the same structure as the address latch &lt;0&gt;. 
     In the address latch &lt;0&gt;, an inverter IV 0  inverts the address latch control signal XAE, and an inverter IV 1  inverts the output signal from the inverter IV 0 . A transmission gate TG 1  transmits the inputted address ADD&lt;0&gt; to a latch circuit LT 1  according to the output signals from the inverters IV 0  and IV 1 . The latch circuit LT 1  latches the output signal from the transmission gate TG 1 . A NOR gate NR 1  NORs the output signal from the inverter IV 0  and the internal address ADDLT&lt;0&gt; which is the output from the latch circuit LT 1 , and outputs the latch address BXA&lt;0&gt;. An inverter IV 4  inverts the latch address BXA&lt;0&gt;, and outputs the latch address BXAZ&lt;0&gt;. 
     Here, when the address latch control signal XAE has a low level, the address latch &lt;0&gt; is disabled. That is, since a node CN 1  has a high level and a node CN 2  has a low level, the transmission gate TG 1  is turned on to transmit the inputted address ADD&lt;0&gt; to the latch circuit LT 1 . However, the latch circuit LT 1  cannot perform the latch function because an inverter IV 3  is disabled. Therefore, the output signal from the NOR gate NR 1  maintains a low level regardless of a level of the inputted address ADD&lt;0&gt;. 
     Thereafter, when the valid address ADD&lt;0&gt; is inputted to enable the address latch control signal XAE in a high level, the address latch &lt;0&gt; is enabled. Since the node CN 1  has a low level and the node CN 2  has a high level, the transmission gate TG 1  is turned off. However, the inverter IV 3  is enabled to activate the latch circuit LT 1 , and thus a level of a node CN 3  and a level of a node CN 4  are fixed. The node CN 1  has a low level, and thus a level of the output signal from the NOR gate NR 1 , namely a level of the latch address BXA&lt;0&gt; is determined according to the inputted address ADD&lt;0&gt;. The latch address BXAZ&lt;0&gt; is generated by inverting the latch address BXA&lt;0&gt;, and inputted to the decoder  40  or predecoder  50 . 
     FIG. 6 is a circuit diagram illustrating the address transition detector  30  of FIGS. 3 and 4. The address transition detector  30  includes a phase controller  31  to control a phase of the address in response to the internal address ADDLT&lt;0&gt; and the address latch control signal XAE, and a phase transmitter  32  to receive the output signal from the phase controller  31  and generate the decoder control signal XPDEN according to the latch addresses BXA&lt;0&gt; and BXAX&lt;0&gt;. 
     The phase controller  31  includes a NAND gate ND 0  to NAND the internal address ADDLT&lt;0&gt; and the address latch control signal XAE. The phase transmitter  32  has an XOR logic circuit  33  to transmit an inverted signal of the output signal from the phase controller  31  according to the latch addresses BXA&lt;0&gt; and BXAZ&lt;0&gt;, and an inverter IV 6  to invert the output signal from the XOR logic circuit  33 , and output the decoder control signal XPDEN. 
     The XOR logic circuit  33  includes a transmission gate TG 2  to transmit an inverted signal of the output signal from the phase controller  31  according to the latch addresses BXA&lt;0&gt; and BXAZ&lt;0&gt;, and a transmission gate TG 3  to transmit the output signal from the phase controller  31  according to the latch addresses BXA&lt;0&gt; and BXAZ&lt;0&gt;. 
     Here, when the address latch control signal XAE has a low level, the latch address BXA&lt;0&gt; maintains a low level and the latch address BXAZ&lt;0&gt; maintains a high level regardless of the internal address ADDLT&lt;0&gt;. The internal address ADDLT&lt;0&gt; is not associated with the latch addresses BXA&lt;0&gt; and BXAZ&lt;0&gt;. However, when the address latch control signal XAE has a high level, the internal address ADDLT&lt;0&gt; and the latch address BXA&lt;0&gt; always have inversion relation. 
     As described above, when the address latch control signal XAE has a low level, the latch address BXA&lt;0&gt; maintains a low level and the latch address BXAZ&lt;0&gt; maintains a high level. The transmission gates TG 2  and TG 3  are controlled in this way to maintain the decoder control signal XPDEN in a low level. The NAND gate ND 0  receives the internal address ADDLT&lt;0&gt; and the address latch control signal XAE to maintain the decoder control signal XPDEN in a low level. The NAND gate ND 0  is added to maintain the output signal of the phase controller  31  at a high level. 
     Conversely, when the address latch control signal XAE has a high level, the output signal from the phase controller  31  and the latch address BXA&lt;0&gt; always have the same phase. Accordingly, the XOR logic circuit  33  that receives the latch addresses BXA&lt;0&gt; and BXAZ&lt;0&gt; and the output signal from the phase controller  31  is configured so that the internal address ADDLT&lt;0&gt; and the latch address BXA&lt;0&gt; can always have inversion relation. 
     FIGS. 7 a  and  7   b  are circuit diagrams respectively illustrating the XOR logic circuit  33 , and FIG. 8 is a truth table of the phase transmitter  32 . FIG. 7 a  shows an XOR logic circuit using a logic gate, and FIG. 7 b  shows an XOR logic gate using a transmission gate. In FIGS. 7 a  and  7   b , A denotes the latch address BXA&lt;0&gt;, B denotes the output signal from the phase controller  31 , and F denotes the output signal from the XOR logic circuit  33 . 
     As depicted in FIG. 7 a , the XOR logic circuit includes an inverter IV 20  to invert the signal A, an inverter IV 21  to invert the signal B, a NAND gate ND 1  to NAND the output signal from the inverter IV 20  and the signal B, a NAND gate ND 2  to NAND the signal A and the output signal from the inverter IV 21 , and a NOR gate NR 2  to NOR the output signals from the NAND gates ND 1  and ND 2 . 
     As shown in FIG. 7 b , the XOR logic circuit includes an inverter IV 22  to invert the signal A, an inverter IV 23  to invert the signal B, a transmission gate TG 4  to transmit the signal B according to the signal A and the output signal from the inverter IV 22 , and a transmission gate TG 5  to transmit the output signal from the inverter IV 23  according to the signal A and the output signal from the inverter IV 22 . 
     Here, when the address latch control signal XAE has a low level, the latch address BXA&lt;0&gt; (signal A) and the output signal (signal B) from the phase controller  31  have the opposite phases as shown in FIG.  8 . Accordingly, the output signal (signal F) from the XOR logic circuit  33  has a high level, and the decoder control signal XPDEN has a low level, thereby disabling the decoder  40 . When the address latch control signal XAE has a high level, the latch address BXA&lt;0&gt; (signal A) and the output signal (signal B) from the phase controller  31  have the same phase. Therefore, the output signal (signal F) from the XOR logic circuit has a low level, and the decoder control signal XPDEN has a high level, thereby enabling the decoder  40 . 
     FIG. 9 is a circuit diagram illustrating the decoder  40  of FIG.  3 . The decoder  40  is enabled according to the decoder control signal XPDEN, to decode a latch address BAX&lt;i&gt; and output decoded addresses BAX&lt;j&gt; and BAX&lt;k&gt;. 
     In the decoder  40 , an inverter IV 24  inverts a latch address BAXZ&lt;i&gt;, and a NAND gate ND 3  NANDs the decoder control signal XPDEN and the latch address BAXZ&lt;i&gt;. A NAND gate ND 4  NANDs the output signal from the inverter IV 24  and the decoder control signal XPDEN. An inverter IV 25  inverts the output signal from the NAND gate ND 3  and outputs the decoded address BAX&lt;j&gt;, and an inverter IV 26  inverts the output signal from the NAND gate ND 4  and outputs the decoded address BAX&lt;k&gt;. 
     Here, when a valid address is transmitted to a node CN 20  and a node CN 21 , the decoder control signal XPDEN is transited from a low to high level. The NAND gate ND 3  and the NAND gate ND 4  output an operation result of the node CND 20 , the node CN 21  and the decoder control signal XPDEN. 
     FIGS. 10 to  13  are layout diagrams respectively illustrating the address latch  20 , the address transition detector  30  and the decoder  40 . FIG. 10 shows a layout of the plurality of address latches  20 , one address transition detector  30  and one decoder  40 . 
     Referring to FIG. 10, one address transition detector  30  is positioned to correspond to the address latch &lt;0&gt;. The address transition detector  30  generates one decoder control signal XPDEN to control the decoder  40 . One decoder  40  is installed to correspond to the plurality of address latches &lt;0-N&gt;. 
     FIG. 11 shows a layout of the plurality of address latches  20 , one address transition detector  30  and a plurality of decoders  40 . As illustrated in FIG. 11, one address transition detector  30  is positioned to correspond to the address latch &lt;0&gt;. The address transition detector  30  generates one decoder control signal XPDEN to control the decoders  40 . In addition, the plurality of address latches  20  are grouped in a predetermined number, and the plurality of decoders  40  are installed to correspond to each group. 
     FIG. 12 shows a layout of the plurality of address latches  20 , the plurality of address transition detectors  30  and the plurality of decoders  40 . As depicted in FIG. 12, the address transition detectors  30  for at least one address are respectively positioned in the decoders  40 . The address transition detectors  30  of the decoders  40  respectively generate the decoder control signals and control the decoders  40 . 
     The circuit illustrated in FIG. 13 generates the decoder control signal and controls each decoder according to combinations of FIG.  11  and FIG.  12 . As described above, the address transition detector  30  can be positioned in the address latch or decoder and a path of the address latch or decoder. As discussed earlier, in accordance with the present disclosure, the decoder control signal is generated by detecting that the valid address is outputted from the address latch, and the decoder is enabled in response to the decoder control signal, thereby removing unnecessary delay between the address inputted to the decoder and the decoder control signal. Therefore, the semiconductor memory device has an improved operation speed. 
     In addition, the decoder is enabled in response to the decoder control signal generated by detecting that the valid address is outputted from the address latch, thereby preventing a glitch in the output from the decoder due to mis-matching between the address and the decoder control signal due to variations of the process, temperature and voltage. Accordingly, unnecessary toggling is removed from the output from the decoder, to reduce power consumption and prevent mis-operation of the decoder. 
     Many changes and modifications to the embodiments described herein could be made. The scope of some changes is discussed above. The scope of others will become apparent from the appended claims.