Abstract:
Embodiments of the invention include a method of cleaning a semiconductor substrate of a device structure and a method of forming a silicide layer on a semiconductor substrate of a device structure. Embodiments include steps of converting a top portion of the substrate into an oxide layer and removing the oxide layer to expose a contaminant-free surface of the substrate.

Description:
BACKGROUND 
       [0001]    The present invention generally relates to the fabrication of semiconductor devices, and particularly to the cleaning of semiconductor substrate surfaces. 
         [0002]    The fabrication of semiconductor devices frequently requires the production of a uniform substrate surface for future processing. Contaminants on the surface of a substrate may undermine device performance by causing defects in device features formed adjacent to the substrate. Removal of these contaminants may therefore lead to increased device performance and reliability. As the features of microelectronic devices are reduced in size and increase in aspect ratio, it may be increasingly difficult to effectively clean some substrate surfaces quickly and without causing damage to the surrounding area. For example, silicide contacts are often formed on substrate surfaces to reduce resistance between the substrate and subsequent layers. Contaminants on the surface of the substrate where silicide is to be formed can cause defects or gaps in the formed silicide layer, increasing resistance and decreasing product yield due to insufficient contact areas. Removing these contaminants before forming the silicide layer can increase uniformity and therefore improve device efficiency and reliability as well as product yield. 
       BRIEF SUMMARY 
       [0003]    The present invention relates to the cleaning of a substrate. One embodiment of the invention may include, first, converting a top portion of the substrate into an oxide layer and, second, removing the oxide layer to expose a contaminant free surface of the substrate. 
         [0004]    Another embodiment of the invention may include forming a silicide layer on a substrate. The embodiment may include converting a top portion of the substrate into an oxide layer, removing the oxide layer to expose a contaminant-free surface of the substrate, and forming a silicide layer on the contaminant-free surface of the substrate. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0005]      FIG. 1A  depicts an exemplary semiconductor structure including transistor devices. 
           [0006]      FIG. 1B  depicts the exemplary semiconductor structure of  FIG. 1A  after a trench has been etched in the region between the transistor devices. 
           [0007]      FIG. 1C  depicts an expanded view of the trench region of  FIG. 1B . 
           [0008]      FIG. 2  depicts implanting oxygen in the region depicted in  FIG. 1C  using a gas cluster ionization beam. 
           [0009]      FIG. 3  depicts the oxide layer formed in  FIG. 2 . 
           [0010]      FIG. 4  depicts the exemplary trench region of  FIG. 3  after the oxide layer has been removed. 
           [0011]      FIG. 5  depicts a nickel layer deposited on the uniform substrate surface of  FIG. 4 . 
           [0012]      FIG. 6  depicts a silicide layer formed on the uniform substrate surface of  FIG. 4 . 
       
    
    
       [0013]    The drawings are not necessarily to scale and are not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements. 
       DETAILED DESCRIPTION 
       [0014]      FIG. 1A  depicts an exemplary semiconductor structure  100  having transistors  101   a - 101   d  on a semiconductor substrate  170 . In one embodiment, substrate  170  may be made of silicon. In other embodiments, substrate  170  may be made of other materials including, but not limited to, silicon-germanium alloys or silicon-carbon alloys. Each transistor  101  includes a metal gate  120 . The metal gate may include a first functional metal layer  130  and a second functional metal layer  140 . In one embodiment, first functional metal layer  130  may be made of titanium. The second metal functional layer  140  may be in contact with the first functional metal layer  130  and be made of titanium-aluminum. A stress liner  150  may cover the exposed surface of the substrate  170 , the functional metal layers  130 ,  140 , and the metal gates  120 . In one embodiment, stress liner  150  may be made of silicon nitride. Interlevel dielectric (ILD) layer  160  fills the regions between the metal gates  120 . The top surface of the interlevel dielectric layer  160  and the stress liner  150 , if not covered by ILD layer  160 , is covered by a hard mask layer  110 . The structure and material composition of structure  100 , and the mentioned components thereof, is presented for illustrative purposes only and may vary without departing from spirit of the invention. 
         [0015]      FIG. 1B  depicts the exemplary semiconductor structure  100  of  FIG. 1A  after a trench  180  has been formed in the region, for example, between the transistors  101   b  and  101   c.  In one embodiment, trench  180  may be formed or created by patterning and then etching, using a reactive ion etching process, through the hard mask  110 , interlevel dielectric layer  160 , and stress liner  150  to expose surface  171  of the substrate  170 .  FIG. 1C  depicts an expanded view of region A of  FIG. 1B  and more clearly illustrates the boundaries of trench  180 . In the embodiment of  FIG. 1B , trench  180  is bounded on each side by, from top to bottom, hard mask  110 , interlevel dielectric layer  160 , and stress liner  150  and on the bottom by surface  171  of the substrate  170 . During the course of creating trench  180 , certain contaminants may remain or exist or be caused to exist at the surface  171  of the substrate  170 . For example, contaminants  190  may be present on the surface  171 . Contaminants  190  may include, for example, silicon oxide and/or silicon nitride, which may be residue from a reactive ion etching process used to form trench  180 . 
         [0016]      FIGS. 2-6  depict a method for forming a silicide layer in trench  180 , according to one embodiment of the invention. As depicted in  FIG. 2 , oxygen may be implanted in the trench  180  using a gas cluster ion beam (GCIB). The oxygen gas clusters  210  are depicted on  FIG. 2  as O 2 , though the gas clusters may consist of thousands or hundreds of thousands of oxygen atoms depending on conditions. Preferably, the GCIB has an energy range of about 5 to about 10 keV, with a cluster dose of about 1E13 ions/cm 2  or higher. This process results in the formation of an oxide layer  310  on substrate  170 , as depicted in  FIG. 3 . Contaminants  190  (shown in  FIGS. 1B and 1C ) are consumed by oxide layer  310  during its formation. The oxide layer  310  in this embodiment has a thickness in the range of approximately 3-10 nanometers (nm), typically about 5 nm. The actual thickness of the oxide layer  310  may be depending on the quantity and depth of the contaminants  190 . During the above-described process, oxygen will also be implanted or deposited in hard mask layer  110 , forming oxidized mask layer  320 . In embodiments where the hard mask layer  110  is made of silicon nitride, oxidized mask layer  320  may be made of silicon oxynitride. Because the GCIB process is anisotropic, oxygen will only be substantially deposited in surfaces perpendicular to the direction of the beam, having minimal impact on parallel surfaces such as the stress liner  150  and interlayer dielectric  160 . 
         [0017]    As depicted in  FIG. 4 , the oxide layer  310  (shown in  FIG. 3 ) is then removed, exposing a uniform surface  410  of the substrate  170 . In one embodiment, the oxide layer  310  is removed by an oxide etch process such as a wet chemical (e.g. dilute hydrofluoric acid) or a dry etch process. In the case of applying a dry etching process, the etch is preferably performed in situ, i.e. no break in vacuum such that the etch process may be transferred directly to a subsequent metal deposition process. For example, the in situ Siconi Preclean process from Applied Materials, Inc is desirable because of its selectivity of silicon oxide to other substances including, for example, silicon and silicon nitride. The Siconi oxide etch target needs to be at least as much as the thickness of the oxide layer  310  (shown in  FIG. 3 ) created by the cluster implant process depicted in  FIG. 2  (e.g., a minimum of 5 nm etch is used for a cluster implant process that created a silicon oxide layer  310  that is 5 nm thick). As further illustrated in  FIG. 4 , the etch process may also remove oxidized nitride layer  320  (shown in  FIG. 3 ). 
         [0018]    As depicted in  FIGS. 5-6 , a silicide layer may then be formed on the uniform surface of the substrate. In  FIG. 5 , a metal layer  510  is deposited on the top surface of the structure  100 . The metal layer  510  may be deposited by any thin film deposition technique available in the industry including, but not limited to, physical vapor deposition (i.e. sputter deposition) or chemical vapor deposition or evaporation. The metal layer  510  may be made of materials including, for example, nickel, platinum, titanium, cobalt or some combination thereof. The structure  100  is then annealed (not shown) to cause reaction of the metal layer  510  with the underlying substrate  170  in order to form a low resistance uniform silicide layer  610  (shown in  FIG. 6 ). The annealing process may typically be performed by a rapid thermal annealing (RTA) process at peak temperatures ranging from about 300 to about 900 degrees Celsius, depending on the silicide material. After removal of any remaining unreacted metal material (not shown), the uniform silicide layer  610  remains directly in contact with substrate  170 , as shown in  FIG. 6 . 
         [0019]    While the present invention has been particularly shown and described with respect to preferred embodiments, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated but fall within the scope of the appended claims.