Abstract:
A signal translator for converting an input voltage (V I ) into an output voltage (V O ) at a different level contains a primary element stack (10) and a similarly-configured image element stack (12), both coupled between the sources of a potentially first variable supply voltage (V CC ) and a normally constant second supply voltage (V EE ). A reference voltage (V R ) is supplied to both a primary-stack transistor (Q2) which provides the output voltage and an image-stack transistor (Q4) which provides a feedback signal (V F ). A feedback circuit (14) formed with an amplifier (16) and a shifting circuit (18) response to the feedback signal to supply the reference voltage at such a value as to compensate the output voltage for changes in the first supply relative to the second supply voltage is particularly useful for CTL-to-TTL logic.

Description:
FIELD OF USE 
     This invention relates generally to signal translators suitable for semiconductor integrated circuits and more particularly to such a translator that converts an input voltage at a given voltage level into an output voltage at a different voltage level. 
     BACKGROUND ART 
     In some conventional signal translators, an element stack having two or more bipolar transistors serially coupled to one another between a first voltage supply and a lower-value second voltage supply is used to perform voltage translation. S. Platt et al disclose such a translator in U.S. Pat. No. 3,778,640, &#34;Signal Voltage Level Translating Circuit&#34;. In this translator, an input voltage supplied to the base of a first NPN transistor in a primary stack is converted into an output voltage at a lower voltage level taken from the collector of a second NPN transistor in the stack. A first resistor is connected between the emitter of the first transistor and the collector of the second transistor. The collector of the first transistor is tied to the first voltage supply, while the emitter of the second transistor is tied to the second voltage supply. 
     A reference current source supplies a first reference voltage to the base of the second transistor to control the amount of downward voltage translation. The reference source contains an image stack consisting of a third NPN transistor, a second resistor, and a fourth NPN transistor connected to one another in the same manner as the first transistor, the first resistor, and the second transistor, respectively. A second reference voltage is supplied to the base of the third transistor. The collector of the fourth transistor is tied back to its base from which the first reference voltage is provided. The resistors have substantially the same resistance. 
     During operation, all of the transistors are conductive. When the input voltage equals the second reference voltage, the output voltage is at a selected nominal value below the input voltage. Because the bases of the second and fourth transistors are connected together and their emitters are tied directly to the second voltage supply, the current through the second transistor equals the current through the fourth transistor. Accordingly, a change in the input voltage above or below the second reference voltage results in the same change in the output voltage. 
     This translator provides linear voltage translation. However, the first reference voltage does not vary with the first supply voltage since it does not affect the base-to-emitter voltage of the fourth transistor. As a consequence, the output voltage changes as the first supply voltage varies. This is undesirable in some applications. 
     DISCLOSURE OF THE INVENTION 
     In accordance with the invention, a signal translator which converts an input voltage signal into an output voltage signal at a different voltage level and which is coupled between a source of a first supply voltage that may vary and a source of a second supply voltage that is normally substantially constant provides compensation in the output signal for changes in the first supply voltage. 
     In one aspect of the invention, the translator contains a pair of element stacks individually coupled between the supply voltage sources. The stacks are referred to as the primary stack and the image stack. The primary stack has a plurality of serially coupled primary elements, each of which is a transistor or an impedance element such as a resistor. One primary element is a first transistor that receives the input signal. Another primary element is a second transistor that receives a reference voltage and provides the output signal. The image stack has a group of image elements corresponding to the primary elements and configured in the same manner. The image transistor corresponding to the second transistor also receives the reference voltage. A feedback circuit responsive to a feedback signal provided from the image transistor supplies the reference voltage at such a value as to compensate for changes in the first supply voltage. 
     In another aspect of the invention, each transistor is a bipolar device. The input signal is provided to the base of the first transistor. Its emitter is coupled to the first supply voltage source. The collector of the second transistor provides the output signal and is coupled through a first impedance element in the primary stack to the emitter of the first transistor. The polarity of these two transistors is the same. A second impedance element is coupled between the emitter of the second transistor and the second supply voltage source. In this aspect of the invention, the translator has a reference circuit for providing the reference voltage to the base of the second transistor so as to achieve the specified voltage compensation. 
     The reference circuit in the second aspect preferably contains the image stack and the feedback circuit. The image stack contains a third transistor whose collector is coupled to the first supply voltage source. The image transistor is a fourth transistor whose base receives the reference voltage and whose collector provides the feedback voltage. The transistors in the image stack are of the same polarity as those in the primary stack. A third impedance element is coupled between the emitter of the third transistor and the collector of the fourth transistor. A fourth impedance element is coupled between the emitter of the fourth transistor and the second supply voltage source. The feedback circuit varies the reference voltage in the same direction as the first supply voltage varies. 
     The feedback circuit optimally contains an amplifier which generates an internal signal from the feedback signal. In particular, the amplifier is a differential amplifier which amplifies the difference between the feedback signal and another reference voltage to generate the internal signal. A shifting circuit then adjusts the voltage of the internal signal to convert it into the first reference voltage. 
     Each element in the image stack is desirably identical to the corresponding element in the primary stack. By use of this matching in combination with an appropriate choice of values for the feedback elements, the variance in the output signal from its nominal voltage at a given input signal is less than 1 percent of the variance in the first supply voltage from its nominal value over the temperature range of -55° C. to 125° C. 
     None of the transistors normally go into saturation. Because of this and the nature of the feedback, the present translator has a relatively fast switching speed. The translator characteristics are also stable over temperature. 
     In a typical application, the input voltage is at one of the binary levels for current tree logic (CTL) which is similar to emitter-coupled logic (ECL) but runs with different voltage levels and swings. CTL uses a swing of 1V BE  referenced to the first supply voltage, where V BE  is the standard base-to-emitter voltage for a bipolar transistor when its base-emitter junction is conductively forward biased. The output voltage is at one of the binary levels for transistor-transistor logic (TTL). 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a circuit diagram of an embodiment of a signal translator in accordance with the invention. 
     FIG. 2 is a circuit diagram of a feedback circuit alternatively employable in the embodiment of FIG. 1. 
     Like reference symbols are employed in the drawing and in the description of the preferred embodiments to represent the same or very similar item or items. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to the drawing, FIG. 1 illustrates an embodiment of a CTL-to-TTL bipolar signal translator that operates between a source of a high supply voltage V CC  and a source of a low supply voltage V EE . Supply voltage V CC  has a nominal value V CC0  of 5.0 volts but may vary from 4.5 volts to 5.5 volts. Supply voltage V EE  is ground reference (0 volt) and does not vary to any significant degree. 
     This translator has a primary element stack 10 containing an always-on NPN transistor Q1 whose base receives a CTL input voltage signal V I  and an always-on NPN transistor Q2 whose collector supplies a TTL output voltage signal V O  at a different voltage level. The switching point for input voltage V I  is V CC  -0.5 V BE  where V BE  is about 0.8 volt for an NPN transistor at room temperature. The nominal logical &#34;1&#34; value for voltage V I  is V CC . The nominal V I  logical &#34;0&#34; value lies in the range of V CC  -2 V BE  to V CC  -V BE  and typically is V CC  -1.5 V BE . The corresponding switching point for output voltage V O  is 3 V BE . The nominal V O  logical &#34;1&#34; level is 3.5 V BE , while the nominal V O  logical &#34;0&#34; level lies in the range of 1.5  V BE  to 2.5 V BE  and typically is 2 V BE . 
     The collector of transistor Q1 is connected to the V CC  supply at the top of stack 10 which also contains resistors R1 and R2. Resistor R1 is connected between the emitter of transistor Q1 and the collector of transistor Q2. Resistor R2 is connected between the emitter of transistor Q2 and the V EE  supply. Resistors R1 and R2 are 4,000 ohms and 500 ohms, respectively. 
     A voltage reference circuit supplies a reference voltage V R  to the base of transistor Q2. The nominal V R  level is 1.5 V BE . As supply voltage V CC  changes, voltage V R  likewise changes in the same (positive/negative) direction by an appropriate amount to compensate for the V CC  change so as to keep voltage V O  relatively constant. For either the nominal V O  logical &#34;1&#34; or &#34;0&#34; value, the variance in voltage V O  from its nominal value is less than 1% of the variance in voltage V CC  from its nominal value over the temperature range of -55° C. to 125° C. 
     The reference circuit contains an image element stack 12 and a feedback circuit 14 that supplies voltage V R  to both stacks 10 and 12 in response to a feedback voltage V F  supplied from image stack 12. Always-on NPN transistors Q3 and Q4 and resistors R3 and R4 form stack 12 and are serially connected to one another between the V CC  and V EE  supplies in the same manner as transistors Q1 and Q2 and resistors R1 and R2 are respectively connected to one another in stack 10. In addition, each element Q3, Q4, R3, or R4 in stack 12 is substantially identical to the corresponding element Q1, Q2, R1, or R2 in stack 10. Transistor Q3 is arranged as a diode with its base connected to the V CC  supply. Resistor R4 in combination with sister resistor R2 provides the voltage drop that enables voltage V R  to be at its nominal level above 1 V BE . Voltage V F  is taken from the collector of transistor Q4 whose base is connected to the base of transistor Q2 so as to receive voltage V R . 
     Feedback circuit 14 consists of a differential amplifier 16 responsive to voltage V F  for generating an internal voltage signal V W  and a level shifting circuit 18 for converting voltage V W  into voltage V R . Differential amplifier 16 includes a pair of always-on NPN transistors Q5 and Q6 whose emitters are connected to each other and through a resistor R5 to the V EE  supply. The current gain (beta) of each transistor Q5 or Q6 is 60, while resistor R5 is 1,500 ohms. Voltage V F  is supplied to the base of transistor Q5 whose collector is tied to V CC  supply. A reference voltage V D  of 3.5 V BE  is supplied to the base of transistor Q6. The collector of transistor Q6 is coupled through a resistor R6 and a PN diode J1 to the V CC  supply. Resistor R6 is 2,400 ohms. Diode J1 acts to keep the gain of amplifier 16 at the desired level. The collector of transistor Q6 is also connected through a resistor R7 and a Schottky diode S1 to the V EE  supply. Resistor R7 is 20,000 ohms. Voltage V W  is taken from the common junction of resistor R7 and diode S1 which together act to control the gain in the feedback loop at high frequency. 
     Shifting circuit 18 contains always-on NPN transistors Q7 and Q8 whose base-emitter junctions are serially coupled between the collector of transistor Q6 by way of resistor R7 on one hand and the bases of transistors Q2 and Q4 on the other hand so as to shift voltage V W  about 2 V BE  downward into voltage V R . Although the collectors of transistors Q7 and Q8 are tied to the V CC  supply, they basically act as diodes. Their collectors could alternatively be tied back to their respective bases. 
     Primary stack 10 interacts with image stack 12 and feedback circuit 14 as follows. Any changes in stack 10 caused by a V CC  change are duplicated in stack 12 because it is identical to stack 10. The changes in stack 12 appear in voltage V F  which corresponds to voltage V O . Circuit 14 responds to the change in voltage V F  from its nominal value at voltage V D  by suitably adjusting voltage V R  so as to return voltage V F  to its nominal V D  value. The V R  value needed to maintain voltage V F  at its nominal value is the same as that needed to maintain voltage V O  at its nominal &#34;1&#34; or &#34;0&#34; value. Thus, the feedback to stabilize stack 12 against V CC  changes also serves to stabilize stack 10 against V CC  changes. 
     More particularly, it is assumed that the current through transistor Q4 does not change at the instant that voltage V CC  first changes from its nominal value V CC0  to a new value V CC0  +ΔV CC  where ΔV CC  may be positive or negative. Feedback voltage V F  then initially changes by the same amount ΔV CC . This unbalances amplifier 16 and causes voltage V W  to change by a much greater amount ΔV W  determined by the differential amplifier gain which is a function of the change in current through transistor Q6 multiplied by the R6/R5 resistance ratio. When ΔV CC  is positive, ΔV W  is positive; likewise, when ΔV CC  is negative, ΔV W  is negative. Circuit 18 then shifts voltage V W  downward by 2 V BE  so that voltage V R  changes by an amount ΔV W  which, again, is in the same direction as ΔV CC . 
     The ΔV W  change in voltage V R  then causes the currents through transistors Q2 and Q4 to increase or decrease depending on whether ΔV CC  is positive or negative. If ΔV CC  is positive, transistor Q4 becomes more conductive. The collector-to-emitter voltage of transistor Q4 decreases by an amount greater than the amount by which the voltage across resistor R4 increases due to the greater current through transistor Q4. This brings voltage V F  back down to its nominal level. The opposite occur when ΔV CC  is negative; transistor Q4 becomes less conductive so as to force voltage V F  back up to its nominal level. Substantially the same changes occur in stack 10 so as to stabilize voltage V O  at its nominal &#34;1&#34; or &#34;0&#34; value. 
     Turning to FIG. 2, it shows an embodiment of a feedback circuit 15 alternatively employable in the translator of FIG. 1. Circuit 15 consists of a differential amplifier 17 and a shifting circuit 19. Amplifier 17 has elements Q5, Q6, R5, R6, and J1 all configured the same as in amplifier 16 of FIG. 1. The difference between circuits 14 and 15 is that elements R7 and S1 are absent in amplifier 17 and transistor Q8 is absent in shifting circuit 19. Instead, the collector of transistor Q6 is directly connected to the base of transistor Q7 whose emitter is coupled through a resistor R8 to provide voltage V R  to the bases of transistors Q2 and Q4. The value of resistor R8 is optimally chosen to provide a voltage drop of 1 V BE  so that shifting circuit 19 shifts voltage V W  about 2 V BE  downward into voltage V R . Resistor R8 acts to control the gain in the feedback loop at high frequency. 
     Returning to FIG. 1, output voltage V O  is supplied to an always-on buffer NPN transistor Q9 in a buffer circuit 20 of the translator. The collector of transistor Q9 is tied to the V CC  supply. A 3,000-ohm resistor R9 and a Schottky diode S2 in circuit 20 are serially connected between the V EE  supply and the emitter of transistor Q9. Its emitter provides a further translator TTL output voltage signal V X  which is shifted down 1 V BE  from voltage V O . 
     Voltage V X  is then supplied to the base of a phase-splitting NPN transistor Q10 in a TTL output stage 22 partly shown in FIG. 1. The emitter of switching transistor Q10 supplies a voltage V Y  and is coupled through a 500-ohm resistor R10 and a Schottky diode S3 in stage 22 to the V EE  supply. The collector of transistor Q10 supplies a voltage V Z  and is connected through a 2,500-ohm resistor R11 in stage 22 to the V CC  supply. A PN diode J2 and a Schottky diode S4 in stage 22 are serially connected in the forward direction between the base of transistor Q9 and the collector of transistor Q10. In operation, diode J2 is conductive when voltage V O  is at logical &#34;1&#34;. A 1 V BE  voltage drop then occurs across both diode J2 and the base-emitter junction of transistor Q9. Insofar as transistor Q10 is concerned, these two 1 V BE  drops cancel each other, so that diode S4 is effectively connected between the base and collector of transistor Q10. That is, the combination of transistor Q9 and diodes J2 and S4 effectively acts to Schottky clamp transistor Q10 so as to keep it out of deep saturation. This is advantageous since it increases switching speed. The remaining unshown portion of stage 22 operates on voltages V Y  and V Z  in a generally conventional manner and is of a conventional totem pole design. 
     Methods for manufacturing the various elements of the present translator are well known in the semiconductor art. The translator is preferably manufactured as a monolithic integrated circuit according to conventional planar processing techniques using oxide isolation to separate active regions on a semiconductor wafer. 
     While the invention has been described with reference to particular embodiments, this description is solely for the purpose of illustration and is not to be construed as limiting the scope of the invention claimed below. For example, semiconductor elements of opposite polarity to those described above may be employed to accomplish the same results except that most of the Schottky diodes would be deleted or replaced with appropriate PN diodes; in this case, V BE  is negative in value. Some or all of the transistors might be field-effect transistors (FET&#39;s) such as insulated-gate FET&#39;s or junction FET&#39;s. Thus, various modifications, changes, and applications may be made by those skilled in the art without departing from the true scope and spirit of the invention as defined by the appended claims.