Abstract:
Systems including a processor and a memory device in communication with the processor include an array of non-volatile memory cells configured in a NAND architecture. The array includes a plurality of series-coupled first non-volatile memory cells, each first non-volatile memory cell curving around a first curved side of a substantially vertical pillar and terminating at an isolation region, and a plurality of series-coupled second non-volatile memory cells, each second non-volatile memory cell curving around a second curved side of the substantially vertical pillar and terminating at the isolation region. Respective ones of the first non-volatile memory cells are respectively at same vertical levels as respective ones of the second non-volatile memory cells.

Description:
RELATED APPLICATIONS 
       [0001]    This application is a continuation of U.S. application Ser. No. 15/246,847, filed Aug. 25, 2016 (allowed), which is a continuation of U.S. application Ser. No. 14/820,027, filed Aug. 6, 2015 and issued as U.S. Pat. No. 9,455,266 on Sep. 27, 2016, which is a continuation of U.S. application Ser. No. 13/676,407, filed Nov. 14, 2012 and issued as U.S. Pat. No. 9,147,693 on Sep. 29, 2015, which is a continuation of U.S. application Ser. No. 13/047,215, filed Mar. 14, 2011 and issued as U.S. Pat. No. 8,329,513 on Dec. 11, 2012, which is a divisional of U.S. application Ser. No. 12/047,414, filed Mar. 13, 2008 and issued as U.S. Pat. No. 7,906,818 on Mar. 15, 2011, all of which applications are commonly assigned and incorporated entirely herein by reference. 
     
    
     FIELD 
       [0002]    The present disclosure relates generally to memory arrays and in particular at least one embodiment of the present disclosure relates to a memory array with a pair of memory-cell strings to a single conductive pillar. 
       BACKGROUND 
       [0003]    Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory. 
         [0004]    Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Non-volatile memory is memory that can retain its data values for some extended period without the application of power. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of charge storage nodes, such as floating gates or trapping layers or other physical phenomena, determine the data value of each cell. By defining two or more ranges of threshold voltages to correspond to individual data values, one or more bits of information may be stored on each cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones and removable memory modules, and the uses for non-volatile memory continue to expand. 
         [0005]    Flash memory typically utilizes one of two basic architectures known as NOR flash and NAND flash. The designation is derived from the logic used to read the devices. In NOR flash architecture, a column of memory cells are coupled in parallel with each memory cell coupled to a bit line. In NAND flash architecture, a column of memory cells are coupled in series with only the first memory cell of the column coupled to a bit line. 
         [0006]    One common type of flash memory is a nitride read only memory (NROM), sometimes referred to as semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory. Such devices generally include silicon nitride (Si 3 N 4 ) as a charge-trapping node, although other dielectric materials may be utilized. By accumulating charge in, or discharging, the charge-trapping node within a memory cell, the threshold voltage of that memory cell may be altered. 
         [0007]    In order for memory manufacturers to remain competitive, memory designers are constantly trying to increase the density of memory devices. Increasing the density of a flash memory device generally requires reducing spacing between memory cells and/or making memory cells smaller. Smaller dimensions of many device elements may cause operational problems with the cell. For example, the channel between the source/drain regions becomes shorter, possibly causing severe short channel effects. 
         [0008]    One way of increasing the density of memory devices is to form multi-layered memory arrays, e.g., often referred to as three-dimensional memory arrays. For example, one type of three-dimensional memory array includes a plurality of horizontal layers of traditional two-dimensional arrays, such as NAND or NOR memory arrays, stacked vertically one atop the other, with the memory cells of each memory array being silicon-on-sapphire transistors, silicon-on-insulator transistors, thin film transistors, thermoelectric polymer transistors, semiconductor-oxide-nitride-oxide-semiconductor transistors, etc. Another type of three-dimensional memory array includes pillars of stacked memory elements, such as vertical NAND strings that pass vertically through multi-stacked layers of electrode material, where each memory element is a semiconductor-oxide-nitride-oxide-semiconductor transistor, for example. 
         [0009]    For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative three-dimensional memory arrays. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]      FIG. 1  is a simplified block diagram of an embodiment of a NAND flash memory device, according to an embodiment of the disclosure. 
           [0011]      FIGS. 2A-2C  are cross-sectional views of a portion of a memory array at various stages of fabrication in accordance with another embodiment of the disclosure. 
           [0012]      FIG. 3  is an enlarged view of region  300  of  FIG. 2B , according to another embodiment of the disclosure. 
           [0013]      FIG. 4  is a top view of the structure of  FIG. 2B , according to another embodiment of the disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]    In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments. In the drawings, like numerals describe substantially similar components throughout the several views. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. Use the following if applicable: The term wafer or substrate used in the following description includes any base semiconductor structure. Both are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and terms wafer or substrate include the underlying layers containing such regions/junctions. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present disclosure is defined only by the appended claims and equivalents thereof. 
         [0015]      FIG. 1  is a simplified block diagram of a NAND flash memory device  100  in communication with a processor  130  as part of an electronic system, according to an embodiment. The processor  130  may be a memory controller or other external host device. Memory device  100  includes an array of memory cells  104  formed in accordance with embodiments of the disclosure. A row decoder  108  and a column decoder  110  are provided to decode address signals. Address signals are received and decoded to access memory array  104 . 
         [0016]    Memory device  100  also includes input/output (I/O) control circuitry  112  to manage input of commands, addresses and data to the memory device  100  as well as output of data and status information from the memory device  100 . An address register  114  is in communication with I/O control circuitry  112 , and row decoder  108  and column decoder  110  to latch the address signals prior to decoding. A command register  124  is in communication with I/O control circuitry  112  and control logic  116  to latch incoming commands. Control logic  116  controls access to the memory array  104  in response to the commands and generates status information for the external processor  130 . The control logic  116  is in communication with row decoder  108  and column decoder  110  to control the row decoder  108  and column decoder  110  in response to the addresses. 
         [0017]    Control logic  116  is also in communication with a cache register  118 . Cache register  118  latches data, either incoming or outgoing, as directed by control logic  116  to temporarily store data while the memory array  104  is busy writing or reading, respectively, other data. For one embodiment, control logic  116  may include one or more circuits adapted to produce a particular and predictable outcome or set of outcomes in response to one or more input events. During a write operation, data is passed from the cache register  118  to data register  120  for transfer to the memory array  104 ; then new data is latched in the cache register  118  from the I/O control circuitry  112 . During a read operation, data is passed from the cache register  118  to the I/O control circuitry  112  for output to the external processor  130 ; then new data is passed from the data register  120  to the cache register  118 . A status register  122  is in communication with I/O control circuitry  112  and control logic  116  to latch the status information for output to the processor  130 . 
         [0018]    Memory device  100  receives control signals at control logic  116  from processor  130  over a control link  132 . The control signals may include at least chip enable CE#, a command latch enable CLE, an address latch enable ALE, and a write enable WE#. Memory device  100  receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from processor  130  over a multiplexed input/output (I/O) bus  134  and outputs data to processor  130  over I/O bus  134 . 
         [0019]    For example, the commands are received over input/output (I/O) pins [7:0] of I/O bus  134  at I/O control circuitry  112  and are written into command register  124 . The addresses are received over input/output (I/O) pins [7:0] of bus  134  at I/O control circuitry  112  and are written into address register  114 . The data are received over input/output (I/O)-pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device at I/O control circuitry  112  and are written into cache register  118 . The data are subsequently written into data register  120  for programming memory array  104 . For another embodiment, cache register  118  may be omitted, and the data are written directly into data register  120 . Data are also output over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O pins [15:0] for a 16-bit device. 
         [0020]    It will be appreciated by those skilled in the art that additional circuitry and signals can be provided, and that the memory device of  FIG. 1  has been simplified. It should be recognized that the functionality of the various block components described with reference to  FIG. 1  may not be segregated to distinct components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device could be adapted to perform the functionality of more than one block component of  FIG. 1 . Alternatively, one or more components or component portions of an integrated circuit device could be combined to perform the functionality of a single block component of  FIG. 1 . 
         [0021]    Additionally, while specific I/O pins are described in accordance with popular conventions for receipt and output of the various signals, it is noted that other combinations or numbers of I/O pins may be used in the various embodiments. 
         [0022]      FIGS. 2A-2C  are cross sectional views of a portion of a memory array, such as memory array  104  of  FIG. 1 , during various stages of fabrication, according to an embodiment.  FIG. 2A  shows a cross-section of a source-select-gate portion  201  of the memory array after several processing steps have been performed. In general, the formation of the structure of  FIG. 2A  may include forming a dielectric layer  202  overlying a semiconductor substrate  200 , such as a silicon-containing substrate, e.g., a P-type monocrystalline silicon substrate, as shown in  FIG. 2A . For one embodiment, semiconductor substrate  200  forms a source line  200  of the memory array. Dielectric layer  202  may be an oxide-nitride-oxide (ONO) layer, with a first oxide layer in contact with source line  200 , the nitride layer overlying and in contact with the first oxide layer, and a second oxide layer overlying and in contact with the nitride layer. 
         [0023]    A conductive layer  204  is formed overlying dielectric layer  202 . Conductive layer  204  may be of polysilicon, such as conductively doped P-type polysilicon, as shown in  FIG. 2A . Alternatively, conductive layer  204  may be a metal-containing layer, such as a refractory metal silicide layer. The metals of chromium (Cr), cobalt (Co), hafnium (Hf), molybdenum (Mo), niobium (Nb), tantalum (Ta), titanium (Ti), tungsten (W), vanadium (V) and zirconium (Zr) are generally recognized as refractory metals. 
         [0024]    A dielectric layer  206 , such as a pad oxide layer, e.g., a thermal oxide layer or a deposited silicon dioxide (SiO 2 ) layer, is formed overlying conductive layer  204 . A cap  208 , such as a nitride cap, e.g., of silicon nitride, is formed overlying dielectric layer  206 . 
         [0025]    After forming cap  208 , holes  210  are formed passing through cap  208 , dielectric layer  206 , conductive layer  204 , and dielectric layer  202 , stopping substantially on source line  200 . Holes  210  may be formed by patterning cap layer  208  and removing portions of cap layer  208 , dielectric layer  206 , conductive layer  204 , and dielectric layer  202  corresponding to the holes  210  exposed by the patterned cap layer  208  by etching, for example. Note that each of holes  210  exposes an edge of cap layer  208 , dielectric layer  206 , conductive layer cap layer  204 , and dielectric layer  202  and portion of source line  200 . Each of holes  210  is then lined with a dielectric layer  212 , such as an oxide layer, e.g., using low pressure chemical vapor deposition (LPCVD). For example, dielectric layer  212  is formed on the exposed edges of cap  208 , dielectric layer  206 , conductive layer  204 , and dielectric layer  202 . The remaining portion of each of holes  210  is then filled with a conductive layer, e.g., a conductive pillar, such as a plug,  214 , e.g., of polysilicon, that overlies dielectric layer  212 . 
         [0026]    For one embodiment, conductive pillar  214  is conductively doped to an n −  conductivity type. Then, for example, ion implantation at a first power setting may be used to convert a portion of conductive pillar  214  at the level of dielectric layer  202  to an n +  conductivity type, as shown in  FIG. 2A . Ion implantation at a second power setting may be used to convert a portion of conductive pillar  214  at the level of cap layer  208  to an n +  conductivity type, for example, as shown in  FIG. 2A . 
         [0027]    A source select transistor  216 , such as a field effect transistor (FET), is formed at each intersection of a conductive pillar  214  and conductive layer  204 , where conductive layer  204 , dielectric layer  212 , and conductive pillar  214  respectively form the control gate (which can also be referred to as a select gate), gate dielectric, and channel, of each select transistor  216 . In other words, each source select transistor  216  has a gate dielectric  212  on a conductive pillar  214  and a select gate  204  on the gate dielectric  212 . Each select gate  204  forms a portion of a source select line extending substantially perpendicularly into the plane of  FIG. 2A  (not shown). 
         [0028]    In  FIG. 2B , a memory cell portion  220  of the memory array is formed overlying the source-select-gate portion  201  of  FIG. 2A . Memory cell portion  220  may be formed by forming a dielectric layer  222 , e.g., dielectric layer  222   1 , such as a pad oxide layer, e.g., a thermal oxide layer or a deposited silicon dioxide (SiO 2 ) layer, overlying cap layer  208 . A conductive layer  224 , e.g., conductive layer  224   1 , is formed overlying dielectric layer  222   1 . Conductive layer  224  may be of polysilicon, such as conductively doped P-type polysilicon. Alternatively, conductive layer  224  may be a metal-containing layer, such as a refractory metal silicide layer. Another dielectric layer  222 , e.g., dielectric layer  222   2 , is formed overlying conductive layer  224   1 , and another conductive layer  224 , e.g., conductive layer  224   2 , is formed overlying dielectric layer  222   2 , as shown in  FIG. 2B . For one embodiment, dielectric layers  222  and conductive layers  224  may alternate, as shown in  FIG. 2B , until memory cell portion  220  includes up to a certain number, e.g., N, where N is generally some power of two, such as 8, 16, 32, 64, etc., of alternating dielectric layers  222  and conductive layers  224  overlying source-select-gate portion  201 . 
         [0029]    Holes  226  are formed passing through dielectric layers  222  and conductive layers  224 , stopping substantially on an upper surface of source-select-gate portion  201  so that holes  226  are substantially aligned with conductive pillars  214 , as shown in  FIG. 2B . For example, holes  226  may stop at an upper surface of conductive pillars  214 . Holes  226  may be formed by patterning the uppermost conductive layer  224 , e.g., conductive layer  224   2  in  FIG. 2B , and removing portions of dielectric layers  222  and conductive layers  224  corresponding to the holes  226  exposed by the patterned conductive layer  224  by etching, for example. Note that each of holes  226  exposes an edge of each dielectric layer  222  and each conductive layer  224  and an upper surface of a conductive pillar  214 . 
         [0030]    Each of holes  226  may be lined with a charge trapping layer  228 , e.g., using low pressure chemical vapor deposition (LPCVD). For example, charge trapping layer  228  is formed on the exposed edges of each conductive layer  224  and each dielectric layer  222 . The remaining portion of each of holes  226  is then filled with a conductive layer, e.g., a conductive pillar, such as a plug,  230 , e.g., of polysilicon, that overlies charge trapping layer  228  so that each conductive pillar  230  contacts a respective one of conductive pillars  214 , as shown in  FIG. 2B . 
         [0031]      FIG. 3  is an enlarged view of region  300  of  FIG. 2B , illustrating the structure of charge trapping layer  228 , according to another embodiment. For one embodiment, conductive pillar  230 , charge trapping layer  228 , and conductive layer  224  form a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) structure. For example, charge trapping layer  228  may include an oxide layer  232  formed on conductive layer  224 , a nitride layer  234  formed on oxide layer  232 , and an oxide layer  236  formed on nitride layer  234 , as shown in  FIG. 3 . Therefore, lining each hole  226  includes forming oxide layer  232  on the sidewalls of each hole  226 , e.g., using LPCVD, forming nitride layer  234  on oxide layer  232 , e.g., using LPCVD, and forming oxide layer  236  on nitride layer  234 , e.g., using LPCVD. Conductive pillar  230  is then formed on oxide layer  236  so as to fill the remainder of each hole  226 . 
         [0032]      FIG. 4  is a top view of the structure of  FIG. 2B . In other words,  FIG. 2B  is a cross-section viewed along line  2 B- 2 B of  FIG. 4 . For one embodiment, slots  410  are formed passing through dielectric layers  222  and conductive layers  224  in a direction substantially parallel to holes  226 , stopping substantially on the upper surface of source-select-gate portion  201  so that slots  410  extend to substantially the same level below the upper surface of memory cell portion  220  as do holes  226 . For example, slots  410  stop at an upper surface of conductive pillars  214  and an upper surface of cap layer  208 . Each slot  410  is then filled with a dielectric material  415 , such as a high-density-plasma (HDP) oxide, spin-on dielectric material, e.g., hydrogen silsesquioxane (HSQ), hexamethyldisiloxane, octamethyltrisiloxane, etc., to form an isolation region  420   
         [0033]    Isolation regions  420  cut each conductive layer  224  into electrically isolated activation lines, such as word lines,  424 , as shown in  FIGS. 2B and 4 , that extend substantially perpendicularly into the plane of  FIG. 2B . For example, isolation regions  420  divide conductive layer  224   2  into a plurality of isolated word lines  424   2,1 ,  424   2,2 ,  424   2,3 , and  424   2,4 . Each isolation region  420  extends between conductive pillars  230  in a direction transverse to the depth of that isolation region  420 , e.g., in a direction substantially parallel to the word-line direction indicated by arrows  430 . 
         [0034]    Each isolation region  420  cuts through at least a portion of the charge trapping layers  228  overlying the conductive pillars  230  between which that isolation region  420  extends so that the each charge trapping layer  228  is not contiguous in a direction around a perimeter of the respective one of the filled holes  226 , as shown in  FIG. 4 . Each isolation region  420  forms a pair of charge traps  229  from each of the charge trapping layers  228 , with a charge trap  229  interposed between a side of a conductive pillar  230  and a word line  424 , as shown in  FIGS. 2B and 4 . For example, an isolation region  420  may cut through oxide layer  232 , nitride layer  234 , and oxide layer  236 , as shown in  FIG. 4 . Alternatively, an isolation region  420  may cut through oxide layer  232  and nitride layer  234  of a charge trap  228 . Although holes  226  are shown to have circular cross-sections in  FIG. 4 , holes  226  may have oval or substantially square or rectangular cross-sections or the like. 
         [0035]    Cutting a charge trapping layer  228  with an isolation region  420  forms a pair of isolated memory cells  450   1,2 ,  450   2,2 , with memory cell  450   1,2  occurring at an intersection between a first side of a pillar  230  and word line  424   2,2 , and memory cell  450   2,2  occurring at an intersection between a second side, opposite the first side, of that pillar  230  and word line  424   2,3 , as shown in  FIGS. 2B and 4 . At each intersection between a side of a conductive pillar and a word line  424 , the word line forms a control gate of the memory cell  450  at that intersection. As shown in  FIG. 2B , memory cells  450   1,1  and  450   1,2  are respectively formed at the intersection of a first side of a pillar  230  and word lines  424   1,2  and  424   2,2  form a first serially-coupled string, e.g., a first NAND string, of memory cells on the first side of that pillar  230 , and memory cells  450   2,1  and  450   2,2  are respectively formed at the intersection of the second side of that pillar  230  and word lines  424   1,3  and  424   2,3  form a second serially-coupled string, e.g., a second NAND string, of memory cells on the second side of that pillar  230 . Alternatively, memory cells of a serially-coupled string may alternate on opposing sides of a pillar  230 . For example, memory cells  450   1,1  and  450   2,2  respectively formed at the intersection of a first side of a pillar  230  and word line  424   1,2  and at the intersection of a second side of that pillar  230  and word line  424   2,3  may form a first serially-coupled string, e.g., a first NAND string, of memory cells on alternating sides of that pillar  230 , and memory cells  450   2,1  and  450   1,2  respectively formed at the intersection of the second side of that pillar  230  and word lines  424   1,3  and at the intersection of the first side of that pillar  230  and word line  424   2,3  may form a second serially-coupled string, e.g., a second NAND string, of memory cells on alternating sides of that pillar  230 . For one embodiment, each memory cell  450  may be a non-volatile SONOS flash memory cell that includes a portion of a word line  424  that forms a control gate of the memory cell  450 , a charge trap  228 , including an oxide layer  232  formed on the word line  424 , a nitride layer  234  formed on the oxide layer  232 , an oxide layer  236  formed on the nitride layer  234 , and a portion of a conductive pillar  230  formed on the oxide layer  236 . 
         [0036]    In  FIG. 2C , a drain-select-gate portion  250  of the memory array is formed overlying the memory cell portion  220  of  FIG. 2B , according to an embodiment. Drain-select-gate portion  250  may be formed by forming a dielectric layer  252 , such as a pad oxide layer, e.g., a thermal oxide layer or a deposited silicon dioxide (SiO 2 ) layer, overlying the uppermost word lines  424 , e.g., word lines  424   2,1 ,  424   2,2 ,  424   2,3 , and  424   2,4 , the isolation region  420  between the uppermost word lines  424 , and conductive pillars  230 , as shown in  FIG. 2C . 
         [0037]    A dielectric layer  254 , such as a nitride layer, e.g., a layer of silicon nitride, is formed overlying dielectric layer  252 . A dielectric layer  256 , e.g., similar to dielectric layer  252 , is formed overlying dielectric layer  254 . A conductive layer  258 , e.g., similar to conductive layer  204  as described above in conjunction with  FIG. 2A , is formed overlying dielectric layer  256 . A dielectric layer  260 , e.g., similar to dielectric layer  252 , is formed overlying conductive layer  258 . A dielectric layer  262 , e.g., similar to dielectric layer  254 , is formed overlying dielectric layer  260 . A dielectric layer  264 , e.g., similar to dielectric layer  252 , is formed overlying dielectric layer  262 . 
         [0038]    After forming dielectric layer  264 , holes  266  are formed passing through dielectric layer  264 , dielectric layer  262 , dielectric layer  260 , conductive layer  258 , dielectric layer  254 , and dielectric layer  252 , e.g., stopping substantially on conductive pillars  230 . For example holes  266  may be aligned with conductive pillars  230 , as shown in  FIG. 2C . Holes  266  may be formed by patterning dielectric layer  264  and removing portions of dielectric layer  264 , dielectric layer  262 , dielectric layer  260 , conductive layer  258 , dielectric layer  256 , dielectric layer  254 , and dielectric layer  252  corresponding to the holes  266  exposed by the patterned dielectric layer  264  by etching, for example. Note that each of holes  266  exposes an edge of dielectric layer  264 , dielectric layer  262 , dielectric layer  260 , conductive layer  258 , dielectric layer  254 , and dielectric layer  252  and an upper surface of a conductive pillar  230 . Each of holes  266  is then lined with a dielectric layer  268 , such as an oxide layer, e.g., using low pressure chemical vapor deposition (LPCVD). For example, dielectric layer  268  is formed on the exposed edges of dielectric layer  264 , dielectric layer  262 , dielectric layer  260 , conductive layer  258 , dielectric layer  254 , and dielectric layer  252 . The remaining portion of each of holes  266  is then filled with a conductive layer, e.g., a conductive pillar, such as a plug,  270 , e.g., of polysilicon, that overlies dielectric layer  268 . 
         [0039]    For one embodiment, conductive pillar  270  is conductively doped to an n −  conductivity type. Then, for example, ion implantation at a first power setting may be used to convert a portion of conductive pillar  270  at the level of dielectric layers  252 ,  254 , and  256  to an n +  conductivity type, as shown in  FIG. 2C . Ion implantation at a second power setting may be used to convert a portion of conductive pillar  270  at the level of dielectric layers  260 ,  262 , and  264  to an n +  conductivity type, for example, as shown in  FIG. 2C . 
         [0040]    For one embodiment, trenches  274  are formed passing through dielectric layer  264 , dielectric layer  262 , dielectric layer  260 , conductive layer  258 , dielectric layer  256 , dielectric layer  254 , and dielectric layer  252 , stopping substantially on the uppermost word lines  424 , e.g., word lines  424   2,1 ,  424   2,2 ,  424   2,3 , and  424   2,4  of  FIG. 2C . Trenches  274  may be formed by patterning dielectric layer  264  and removing portions of dielectric layer  264 , dielectric layer  262 , dielectric layer  260 , conductive layer  258 , dielectric layer  256 , dielectric layer  254 , and dielectric layer  252  corresponding to the trenches  274  exposed by the patterned dielectric layer  264  by etching, for example. Each trench  274  is then filled with a dielectric material  276 , such as a high-density-plasma (HDP) oxide, spin-on dielectric material, e.g., hydrogen silsesquioxane (HSQ), hexamethyldisiloxane, octamethyltrisiloxane, etc., to form isolation regions  278 . Isolation regions  278  define a control gate, such as a select gate  279 , at each intersection of the remaining portions of conductive layer  258  and a conductive pillar  270 , as shown in  FIG. 2C . 
         [0041]    A drain select transistor  280 , such as a field effect transistor (FET), is formed at each intersection of a conductive pillar  270  and conductive layer  258 , where conductive layer  258 , dielectric layer  268 , and conductive pillar  270  respectively form the select gate, gate dielectric, and channel, of each drain select transistor  280 . In other words, each drain select transistor  280  has a gate dielectric  268  on a conductive pillar  270  and a select gate  279  on the gate dielectric  268 . Each select gate  279  forms a portion of a drain select line  282 , indicated by a dashed line in  FIG. 4 . Each drain select line  282  overlies and is substantially parallel to a dielectric-filled slot  410 , as shown in  FIG. 4 . 
         [0042]    A conductive layer  286 , e.g., a metal layer, such as aluminum, is formed overlying an upper surface of each isolation region  278 , an upper surface of dielectric layer  264 , and an upper surface of each conductive pillar  270 , as shown in  FIG. 2C . Conductive layer  286  is patterned, etched, and processed, e.g., using standard processing, to produce individual data lines, such as bit lines  290 , shown as dashed lines in  FIG. 4 , therefrom. Bit lines  290  are substantially orthogonal to select lines  282  and dielectric-filled slots  410 , as shown in  FIG. 4 . 
         [0043]    Note that the memory cells  450  on each side of a conductive pillar  230  and dielectric-filled slot  410  ( FIG. 4 ) form a serially-coupled string of memory cells  450  interposed between a source select transistor  216  and a drain select transistor  280 . For example,  FIG. 2C  shows a serially-coupled string of memory cells  450   1,1  and  450   1,2  located on one side of a conductive pillar  230  and interposed between source select transistor  216  and a drain select transistor  280 , and a serially-coupled string of memory cells  450   2,1  and  450   2,2 , located on the opposite side of that conductive pillar  230  and interposed between source select transistor  216  and a drain select transistor  280 . The common pillar  230  couples the memory cells  450   1,1  and  450   1,2  in series and the memory cells  450   2,1  and  450   2,2  in series. For some embodiments, the number of memory cells in a serially-coupled string of memory cells may be some power of 2, such as 8, 16, 32, 64, etc. 
         [0044]    A source select transistor  216  is coupled to each serially-coupled string of memory cells through a conductive pillar  214 , and a drain select transistor  280  is coupled to each serially-coupled string of memory cells through a conductive pillar  270 , as shown in  FIG. 2C . Each source select transistor  216  selectively couples the lower end of each conductive pillar  230  and thus the serially-coupled string of memory cells on either side of that conductive pillar  230  to source line  200 , as shown in  FIG. 2C . Each drain select transistor  280  selectively couples the upper end of each conductive pillar  230  and thus the serially-coupled string of memory cells on either side of that conductive pillar  230  to a bit line  290 . 
       Conclusion 
       [0045]    Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the embodiments will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the embodiments. It is manifestly intended that the embodiments be limited only by the following claims and equivalents thereof.