Abstract:
An apparatus including a low voltage differential signaling (LVDS) driver circuit with on-resistance cancellation, includes a current steering circuit having an on-resistance. In order to cancel the on-resistance of the current steering circuit, the LVDS driver circuit also includes a current proportional to absolute temperature current source, a transistor having an on-resistance proportional to the on-resistance of the current steering circuit, and a voltage-to-current conversion circuit coupled to the transistor, wherein the voltage-to-current conversion circuit converts the drain-to-source voltage of the transistor into a current proportional to an output current of the LVDS driver circuit. A first resistive circuit receives the current proportional to absolute temperature and the current proportional to an output current of the LVDS driver circuit and in accordance therewith provides a first reference signal. This first reference signal is received by a voltage generating circuit which generates two reference voltage signals that are supplied to the current steering circuit.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to low voltage differential swing driver circuits and more particularly, to cancellation of R ON  resistance for a switching transistor in LVDS driver circuits. 
     2. Description of the Related Art 
     The constant need to transfer more information faster, accompanied by increases in data processing capability, has necessitated an expansion to data transfer rates considerably higher than what was previously possible. As a consequence, a protocol referred to as 100 Base-T was developed for extending IEEE Standard 802.3 to accommodate data moving at an effective transfer rate of 100 Mbps through twisted-pair cables. Under the 100 Base-T protocol, certain control bits are incorporated into the data before it is placed on a twisted-pair cable. The result is that the data and control signals actually move through a twisted-pair cable at 125 Mbps. 
     One type of data transmission is differential data transmission in which the difference in voltage levels between two signal lines form the transmitted signal. Differential data transmission is commonly used for data transmission rates greater than 100 Mbps over long distances. Noise signals shift the ground level voltage and appear as common mode voltages. Thus, the deleterious effects of noise are substantially reduced. 
     To standardize such data transmission various standards have been promulgated. For example, one such standard is the recommended standard 422, RS422, which is defined by the Electronics Industry of America, EIA. This standard permits data rates up to 10 million baud over a twisted pair of signal lines. Driver circuits place signals on the lines. These drivers circuits must be capable of transmitting a minimum differential signal in the range of two to three volts on the twisted pair line which typically terminates in 100 ohms of resistance. 
     One problem with RS422 is that the twisted line pair is often used as a bus to which multiple driver circuits, sources of signals, are attached. In one type of conventional circuit, when multiple drivers are connected to a common bus, only one driver may transmit data at a time. The remaining drivers should be in a high impedance state so as to not load the bus. Since large positive and negative common mode signals may appear at the driver output terminals connected to a bus system, the maintenance of a high impedance over a wide common mode voltage range independent of whether the driver is powered or not, is desirable. 
     An example of a conventional low voltage differential swing (LVDS) driver circuit 100 is shown in FIG.  1 . The difference in voltage between the output signals OUT+, OUT− on the output terminals  103 ,  105  form the pair of differential signals. A pair of differential signals means two signals whose current waveforms are out of phase with one another. The individual signals of a pair of differential signals are indicated by reference symbols respectively ending with “+” and “−” notation, e.g., S+ and S−. The composite notation “+/−” is employed to indicate both differential signals using a single reference symbol, e.g., S+/−. 
     The LVDS driver circuit  100  includes a resistor R 1  coupled to a reference voltage VREF, four n-channel metal oxide semiconductor (NMOS) switches M 11 -M 14 , and a resistor R 2  coupled between the common node COM and voltage supply VSS. The four transistor switches M 11 -M 14  are controlled by input voltage signals VIN 1 , VIN 2  and direct current through load resistor RL as indicated by arrows A and B. The input voltage signals VIN 1 , VIN 2  are typically rail-to-rail voltage swings. 
     The gates of NMOS switches M 11  and M 14  are coupled together to receive input voltage signal VIN 1 . Similarly, the gates of NMOS switches M 12  and M 13  are coupled together to receive input voltage signal VIN 2 . 
     Operation of the LVDS driver circuit  100  is explained as follows. Two of the four NMOS switches M 11 -M 14  turn on at a time to steer current from resistor R 1  to generate a voltage across resistive load RL. To steer current through resistive load RL in the direction indicated by arrow A, input signal VIN 1  goes high turning ON NMOS switches M 11  and M 14 . When input signal VIN 1  goes high, input signal VIN 2  goes low to keep NMOS switches M 12  and M 13  OFF during the time NMOS switches M 11  and M 14  are ON. Conversely, to steer current through resistive load RL in the direction indicated by arrow B, input signal VIN 2  goes high and is applied to transistor switches M 12  and M 13  to make them conduct. Input signal VIN 1  goes low to keep NMOS switches M 11  and M 14  OFF during this time. As a result, a full differential output voltage swing can be achieved. 
     When MOS transistors are used as switches in semiconductor manufacturing, such as in LVDS driver circuit  100 , the on resistance R ON of the transistor becomes a significant factor. The on resistance of a MOS transistor is determined by:              RON   =     VDS   ID             (   1   )                                
     where VDS is the drain to source voltage and ID is the drain current of the MOS transistor. In addition,                VDS   ID     =     1       KP        (     W   L     )            (     VGS   -   VT   -     VDS   2       )                 (   2   )                                
     where KP is a constant, W/L is the ratio of the width (W) and length (L) of the MOS transistor, VGS is the gate-to-source voltage of the MOS transistor, and VT is the threshold voltage needed to turn the MOS transistor ON. This equation is approximately equal to (assume VGS−VT&gt;&gt;VDS/2):                VDS   ID     ≈     1       KP        (     W   L     )            (     VGS   -   VT     )                 (   3   )                                
     Thus, the on resistance R ON  of MOS transistor depends upon KP and VT which are both process sensitive, and VGS which depends upon the supply voltage VDD and is, thus, application dependent. 
     Referring again to FIG. 1, the current IL through resistor RL is:              IL   =     VREF     RON1   +   RON2   +   R1   +   R2   +   RL               (   4   )                                
     where R ON1  is the on resistance of one of the MOS transistors M 11  or M 12 , depending upon which of the two transistors M 11 , M 12  is ON; where R ON2  is the resistance of one of the MOS transistors M 13  or M 14  depending upon which of the two transistors M 13 , M 14  is ON; and where R 1 , R 2  and RL are the resistance of resistors R 1 , R 2 , and RL respectively. Reference voltage VREF can be generated from bandgap voltage such that it is process and temperature independent. Based on equation (4), it can be seen that current IL depends on resistances R ON , R 1 , R 2  and RL. 
     The use of resistances R 1  and R 2  can result in less variation in current IL due to the on-resistance R ON  of MOS transistors. However, the values of resistors R 1  and R 2  become dominant variables since they can vary in a range of +/−20% typically in semiconductor manufacturing. 
     Therefore, a need exists for a circuit that can make the current IL through resistor RL independent of the on-resistance R ON  of MOS transistors. 
     SUMMARY OF INVENTION 
     A low voltage differential signaling (“LVDS”) driver circuit with on-resistance cancellation in accordance with the present invention includes a current steering circuit, an on-resistance cancellation bias circuit and a first resistive circuit. The on-resistance cancellation bias circuit includes a current proportional to absolute temperature current source, a transistor having an on-resistance proportional to the on-resistance of the current steering circuit, a voltage-to current conversion circuit which converts the drain-to-source voltage across the transistor to a current proportional to an output current of the LVDS driver circuit, and a second resistive circuit that receives the current proportional to absolute temperature and the current proportional to an output current of the LVDS driver circuit and in accordance therewith provides a first reference signal. This first reference signal is received by the voltage generating circuit which generates two reference voltage signals that are supplied to the current steering circuit. 
     In an embodiment of the present invention, the voltage-to-current conversion circuit includes a resistive circuit coupled between the outputs of two buffer circuits and a current source coupled to the resistive circuit, such that the voltage drop across the resistive circuit is equivalent to the voltage drop across the transistor. 
     In an alternate embodiment of the present invention first and second buffer circuits couple to the first resistive circuit at first and second nodes having a resistance therebetween, and a third buffer circuit couples between the second resistive circuit of the voltage-to-current conversion circuit and the first resistive circuit. The configuration of the present invention eliminates resistors R 1  and R 2  of the conventional LVDS driver circuit which can vary markedly. In addition, the output voltage signal of the present invention does not depend upon the on-resistance of the switching circuit or on the resistive load, which can also vary markedly. Thus, with the configuration of the present invention the output voltage Vout of the LVDS driver circuit with on-resistance cancellation remains constant even if there are variations in the value of resistive load RL, in the supply voltage, temperature, or fabrication process parameters. 
     These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a conventional low voltage differential swing circuit. 
     FIG. 2 illustrates a low voltage differential signal driver circuit in accordance with one embodiment of the present invention. 
     FIG. 3 illustrates a switching circuit of a low voltage differential signal driver circuit in accordance with another embodiment of the present invention. 
     FIG. 4 illustrates a buffer circuit of a low voltage differential signal driver circuit in accordance with still another embodiment of the present invention. 
     FIG. 5 illustrates a R ON  cancellation circuit of a low voltage differential signal driver circuit in accordance with yet another embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In accordance with an illustrative embodiment of the invention, FIG. 2 illustrates an LVDS driver with R ON  cancellation circuit  200 . As shown, the LVDS driver circuit  200  includes a switching circuit  201 , three operational amplifiers OPAMP 21 -OPAMP 23 , and an R ON  cancellation bias circuit  203  to generate a differential voltage swing across a resistive load RL, typically external to the chip on which is the LVDS driver with R ON  cancellation circuit  200 . 
     It will be appreciated that operational amplifiers OPAMP 21 -OPAMP 23  are buffers and although they are desirable, they are not necessary for the intended operation on the LVDS driver with R ON  cancellation circuit  200  in accordance with the present invention. These operational amplifiers OPAMP 21 -OPAMP 23  are shown in the figures and discussed below for exemplary purposes only. 
     Referring again to FIG. 2, operational amplifier OPAMP 21  couples to switching circuit  201  and to R ON  cancellation circuit  203  to provide a reference voltage VREF 1  to switching circuit  201  and to provide current IL/k 3  to R ON  cancellation circuit  203 , where k 3  is a constant and where current IL/k 3  is a fraction of the output current IL through resistive load RL. 
     A more detailed schematic of switching circuit  201  is illustrated in FIG.  3 . The circuit  201  has a modified typical H-bridge configuration coupled between a first reference voltage VREF 1  and a second reference voltage VREF 2 , rather than between resistors coupled to voltage supplies VDD and GND as in conventional LVDS driver circuit  100  illustrated in FIG. 1. A load segment LO extends horizontally and contains resistive load RL. This load segment LO couples between end nodes  303 ,  305 . Vertical segment V 1  extends between left end node  303  and node ND 31 . Connected between left end node  303  and common node COM is vertical segment V 3 . Vertical segment V 2  extends between right end node  305  and node ND 31 , while vertical segment V 4  extends between right end node  305  and common node COM. The reference to “vertical” and “horizontal” orientations of the segments of the modified H-bridge circuit  201  are, of course, merely for descriptive purposes and do not necessarily describe the actual layout of the circuit  201 . Each of the vertical segments V 1 , V 2 , V 3 , V 4  contains a respective NMOS switch M 31 , M 32 , M 33 , M 34 . 
     The switches M 31 -M 34  are controlled by input signals IN+, IN− from signal generator  205  illustrated in FIG.  2 . These input signals IN+, IN− are complementary rail to rail voltage levels so the signal is either “high” or “low.” In operation, these voltage signals IN+, IN− are applied to the gates of transistors M 31 -M 34 , to direct current from reference voltage VREF 1  through resistive load RL as indicated by arrows A and B. As used herein, the term “gate” broadly encompasses any form of control lead for changing the switching state of a device. As such, the term “gate” is intended to be synonymous with the “base” of a bipolar transistor, for example. 
     To steer the current from reference voltage VREF 1  through load resistor RL in the direction indicated by arrow A, a high voltage level from voltage signal IN+ is applied to MOS switches M 31  and M 34  to turn these switches on, while a low voltage level from voltage signal IN− is applied to MOS switches M 32  and M 33  to keep these switches off during this time. When switching circuit  201  steers the current in this direction, the voltage at output node  305  is pulled low and the voltage at the output node  303  is pulled high. Thus, since output transistor M 31  is ON, the high output voltage VOH is the voltage at output node  303  and the output low voltage VOL is the voltage at output node  305 . 
     Conversely, to direct current through resistive load RL in the direction indicated by arrow B, a high voltage level from voltage signal IN− is applied to MOS switches M 32  and M 33  to make them conduct, while the other switches M 31  and M 34  are kept off during this time. When switching circuit  201  steers the current in this direction, the voltage at output node  305  is pulled high and the voltage at the output node  303  is pulled low. Thus, since output transistor M 33  is ON, the high output voltage VOH is the voltage at output node  305  and output low voltage VOL is the voltage at output node  303 . 
     By using a configuration that eliminates resistors R 11  and R 12  of LVDS driver circuit  100  there is no dependency on the resistance of such resistors to cause variations in the driver circuit. Thus, the current IL through resistive load RL is:                I   L     =         V   REF1     -     V   REF2           R   ON1     +     R   ON2     +     R   L                 (   5   )                                
     where R ON1  is the on resistance of one of the MOS transistors M 31  or M 32 , depending upon which of the two transistors M 31 , M 32  is ON; where R ON2  is the on resistance of one of the MOS transistors M 33  or M 34  depending upon which of the two transistors M 33 , M 34  is ON; and where RL is the resistance of resistive load RL. Combining the on resistances R ON1  and R ON2  of the two MOS transistors that are on, equation (5) simplifies to:                I   L     =         V   REF1     -     V   REF2           R   ON     +     R   L                 (   6   )                                
     where R ON  equals a sum of on resistances R ON1  and R ON2 . 
     Since the transistors may be subject to a different voltage supply VDD and variations in temperature and semiconductor chip processing parameters, the on resistance of different transistors may vary significantly. The result of the varying on resistances of the driver transistors M 31 -M 34  is that the output voltage of LVDS circuit  200  is poorly defined, resulting in a degradation in performance of the LVDS circuit  200 . 
     Thus, referring to equation (6), it is desirable to make the current IL independent of the on resistance of MOS transistors M 31 -M 34 . If the difference between reference voltages VREF 1  and VREF 2  is set to be proportional to two components, one being a fixed reference (bandgap reference) and the other being proportional to R ON I L , then the following equation is obtained: 
     
       
           V   REF1   −V   REF2   =k   1   Vbg+k   2   R   ON   I   L   (7) 
       
     
     where k 1  and k 2  are constants; where the first component (k 1 Vbg) is a bandgap reference voltage; and where the second component (k 2 R ON I L ) is the combined drain-to-source voltage Vds of the two switching transistors that are on. Then, substituting equation (7) into equation (6) provides:                I   L     =           k   1        Vbg     +       k   2          R   ON          I   L             R   ON     +     R   L                 (   8   )                                
     Simplifying equation (8) yields: 
     
       
           I   L ( R   ON   +R   L )= k   1   Vbg+k   2   R   ON   I   L   
       
     
     
       
           I   L ( R   ON   +R   L   −k   2   R   ON )= k   1   Vbg   
       
     
     
       
         
           
             
               
                 
                   
                     I 
                     L 
                   
                   = 
                   
                     
                       
                         k 
                         1 
                       
                        
                       Vbg 
                     
                     
                       
                         
                           R 
                           ON 
                         
                          
                         
                           ( 
                           
                             1 
                             - 
                             
                               k 
                               2 
                             
                           
                           ) 
                         
                       
                       + 
                       
                         R 
                         L 
                       
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
                 
         
             
         
      
     
     If constant k 2  in equation (9) is set equal to 1, then equation (9) simplifies to:                I   L     =         k   1        Vbg       R   L               (   10   )                                
     Since the output voltage Vout is equal to IL*RL, then: 
     
       
           V out =IL*RL=k   1   *Vbg   (11) 
       
     
     Equation (11) shows the output voltage Vout has the dependency on constant k 1  and bandgap reference voltage Vbg. Since output voltage Vout has no dependency on voltage supply VDD, temperature, resistive load RL, or fabrication process parameters, a stable output voltage Vout can be expected. 
     In order to achieve equation (11), the second component k 2 R ON I L  of equation (7) must be canceled, i.e., referring to equation (9), constant k2 should equal “1.” Referring again to FIG. 2, the circuit configuration of LVDS driver with R ON  cancellation circuit  200  is designed to cancel this second component. Thus, compared to the conventional LVDS driver circuit  100  which minimizes effects from the on resistance of the LVDS driver circuit  100  by using resistances R 1  and R 2 , LVDS driver with R ON  cancellation circuit  200  eliminates the on resistance R ON . 
     As FIG. 2 illustrates, reference voltage VREF 1  is provided by operational amplifier OPAMP 21 . A more detailed discussion of operational amplifier OPAMP 21  will be explained with reference to FIG.  4 . Operational amplifier OPAMP is a general operational amplifier without an output stage. Transistors M 41  and M 43  make up the output driver stage of the operational amplifier OPAMP 21  illustrated in FIG.  2 . As can be seen, in FIG. 4, reference voltage VREF 1  is the non-inverting input and the output is feed back to the inverting input of operational amplifier OPAMP within operational amplifier OPAMP 21  of FIG.  2 . Thus, the voltage at node N 41  in FIG. 4 would follow reference voltage VREF 1 . Included in operational amplifier OPAMP 21  illustrated in FIG. 2 are P-channel MOS (PMOS) transistors M 41 -M 42  and N-channel MOS (NMOS) transistors M 43 -M 44 . 
     The two PMOS transistors M 41  and M 42  have their sources coupled to voltage supply VDD, their gates coupled to receive a bias signal BIAS 1  from operational amplifier OPAMP and their drains coupled to node N 41  and node N 42 , respectively. The two NMOS transistors M 43  and M 44  have their sources coupled to circuit ground, their gates coupled to receive a bias signal BIAS 2  from operational amplifier OPAMP and their drains coupled to node N 41  and node N 42 , respectively. Transistors M 41  and M 42  have a size ratio of k 3 :1, where k 3  is a constant. Similarly, the size ratio of transistor M 43  to transistor M 44  is k 3 :1. Typically, constant k 3  is large, such as 50, to lower the overall operating current. 
     With this buffer configuration, output current IL can sink more current coming from transistor M 41 . Transistors M 42  and M 44  are used to generate current based on the output current IL for use in the cancellation of the R ON I L  term in equation (7), which is also the combined drain-to-source voltage VDS of two active switching transistors M 31 -M 34  in switching circuit  201 . 
     In this exemplary embodiment it is preferable to copy a fraction of current IL rather than the entire current IL, to avoid burning extra current and degrading power dissipation of LVDS driver circuit  200 . The current IL/k 3  is then used to generate the cancellation voltage k 2 R ON I L  as utilized in equation (7). 
     Referring again to operational amplifier OPAMP 21  illustrated in FIG. 2, it can be seen that current IL/k 3  is supplied to R ON  cancellation bias circuit  203 . A more detailed schematic diagram of R ON  cancellation bias circuit  203  is illustrated in FIG.  5 . Included in this circuit  203  are transistor MR ON  which is a fraction of the size of switching transistors M 31  and M 34  combined, and which tracks the on resistance of switching transistors M 31 -M 34 . Thus, the voltage drop across transistor MR ON  or the drain-to-source voltage of transistor MR ON , is the same as the voltage drop across switching transistors M 31 -M 34 . In the exemplary embodiment illustrated in FIG. 5, transistor MR ON  is 1/k 3  the size of switching transistors M 31  and M 34  (and M 32  and M 33 ) combined. 
     R ON  cancellation bias circuit  203  also includes transistor MCM. The non-inverting input of operational amplifier OPAMP 51  couples to the drain of transistor MR ON  while the inverting input of operational amplifier OPAMP 51  couples to node ND 51  between resistor Ra and transistor M 51 . The non-inverting input of operational amplifier OPAMP 52  couples to the source of transistor MR ON  while the inverting input and the output couple together and to resistor Ra at node ND 52 . Current source CS 51  mirrors current IRa to provide current IRON, which is proportional to current IL/k 3 . In this way, operational amplifier OPAMP 51 , transistor M 51 , resistor Ra, operational amplifier OPAMP 52 , and current source CS 51  operate as a voltage-to-current conversion circuit to convert the drain-to-source voltage VDS of transistor MR ON  into a current IRON which is proportional to the current IL/k 3 . In particular, operational amplifiers OPAMP 51  and OPAMP 52  operate as buffers to maintain a voltage across resistor Ra equivalent to the voltage drop across transistor MR ON . Current source CS 51  then mirrors the current IRa through transistor M 51  and resistor Ra to provide an output current IRON. 
     The drain-to-source voltage VDS of transistor MR ON  is determined as follows: 
     
       
           V   DS(MRON)   =k   5   V   DS(M31+M34)   (12) 
       
     
     where k5 is a constant and VDS(M 31 +M 34 ) is the combined drain-to-source voltage of transistors M 31  plus M 34 . Since the resistance of transistors M 31  plus M 34  is resistance R ON  and the current through transistors M 31  and M 34  is current IL, 
     
       
           V   DS(M31+M34)   =I   L   R   ON   (13) 
       
     
     Substituting equation (13) into equation (12) provides: 
       V   DS(MRON)   =k   5 I L   R   ON   (14) 
     Transistors M 52  and M 53  form current mirror current source CS 51 . The size ratio of transistor M 52  to transistor M 53  is 1:k 4 , where k 4  is a constant. In this way, output current IRON mirrors the current IRa. 
     Current IRON is determined by:                I   RON     =       k   4          (       V     DS        (   MRON   )         Ra     )               (   15   )                                
     where Ra is the resistance of resistor Ra. Using equation (14) for the drain-to-source voltage VDS(MR ON ) of transistor MR ON , provides:                I   RON     =       k   4            k   5          (         R   ON          I   L       Ra     )                 (   16   )                                
     Referring again to FIG. 5, the voltage VRb across resistor Rb is: 
     
       
           V   Rb   =I   RON   R   b   (17) 
       
     
     where Rb is the resistance of resistor Rb. Thus, substituting equation (16) in for current IRON provides:                V   Rb     =         I   RON        Rb     =       k   4            k   5          (     Rb   Ra     )            R   ON          I   L                 (   18   )                                
     Since k 4 , k 5 , and Rb/Ra are all geometrical ratios, it can be seen from equation (18) that voltage VRb is proportional to the product of resistance R ON  and current IL. 
     In order to establish a reference voltage VREF at node ND 53 , a current Proportional To Absolute Temperature (IPTAT) current source couples between voltage supply VDD and node ND 53  as illustrated in FIG.  5 . In this way, both current IPTAT and current IRON provide current to node ND 53  to establish a reference voltage VREF there. In the exemplary embodiment illustrated in FIG. 5, a pnp transistor Q 51  couples between resistor Rb and circuit ground. 
     Referring again to R ON  cancellation circuit  203  illustrated in FIG. 2, it can be seen that a voltage generating circuit uses the reference voltage VREF to generate two reference signals VREF 1  and VREF 2 . In the exemplary embodiment illustrated in FIG. 2, such voltage generating circuit includes OPAMP 21 -OPAM 23  and resistors R 21 -R 23 . 
     To generate reference signals VREF 1 , VREF 2 , reference voltage VREF is applied to operational amplifier OPAMP 22 . The reference voltage VREF is applied to the non-inverting input, while the inverting input and output of the operational amplifier OPAMP 22  couple together and to a first resistor R 21 . A second resistor R 22  couples in series to resistor R 21 , and a third resistor R 23  couples in series to R 22 . A first reference voltage VREF 1  is established at node ND 21  between resistors R 21  and R 22 , and a second reference voltage VREF 2  is established at node ND 22  between resistors R 22  and R 23 . These two reference voltages VREF 1  and VREF 2  are then applied to operational amplifiers OPAMP 21  and OPAMP 23 , respectively, which buffer the reference voltages VREF 1 , VREF 2  before they are applied to switching circuit  201 . 
     Referring again to R ON  cancellation circuit  203  illustrated in FIG. 5, reference voltage VREF applied to operational amplifier OPAMP 22  is determined as follows: 
     
       
           VREF =( I   PTAT   Rb+V   BE )+ I   RON   Rb   (19) 
       
     
     where VBE is the base-emitter voltage of transistor Q 51 . Knowing that the first term on the right side of equation (19) is equal to Vbg, i.e., 
     
       
           Vbg=I   PTAT   Rb+V   BE   (20) 
       
     
     and substituting equation (18) in for I RON , provides:              VREF   =     Vbg   +       (       k   4          k   5          Rb   Ra       )          I   L          R   ON                 (   21   )                                
     Referring again to FIG. 2, the difference between reference voltages VREF 1  and VREF 2  is:                VREF1   -   VREF2     =         R   22         R   21     +     R   22     +     R   23            VREF             (   22   )                                
     Substituting equation (21) for voltage VREF:                VREF1   -   VREF2     =           R   22         R   21     +     R   22     +     R   23            Vbg     +         R   22         R   21     +     R   22     +     R   23              (       k   4          k   5          Rb   Ra       )          I   L          R   ON                 (   23   )                                
     Referring again to equation (7) where: 
     
       
           V   REF1   −V   REF2   =k   1   Vbg+k   2   R   ON   I   L   (7) 
       
     
     it can be seen tat                k   1     =         R   22         R   21     +     R   22     +     R   23                       and             (   24   )                 k   2     =         R   22         R   21     +     R   22     +     R   23              (       k   4          k   5          Rb   Ra       )               (   25   )                                
     Then, setting variable k 2  equal to 1 by selecting values of R 21 , R 22 , R 23 , Ra, and Rb, provides complete cancellation. Referring to equation (6) again,                I   L     =         V   REF1     -     V   REF2           R   ON     +     R   L                 (   6   )                                
     gives: 
       I   L ( R   ON   +R   L )= V   REF1   −V   REF2   (26) 
     Then, equating equation (7) and equation (26): 
     
       
           I   L ( R   ON   +R   L ) =k   1   Vbg+k   2   R   ON   I   L   (27) 
       
     
     Equation (27) can be simplified to: 
     
       
           V out= I   L   R   L   =k   1   Vbg+ ( k   2 −1) R   ON   I   L   (28) 
       
     
     Then, if variable k 2  is selected to be 1, by setting appropriate values in equation (25), then equation can be simplified as equation (11): 
     
       
           V out= IL*RL=k   1   *Vbg   (11) 
       
     
     Substituting equation (24) in for k 1  provides:              Vout   =         I   L          R   L       =         R   22         R   21     +     R   22     +     R   23            Vbg               (   27   )                                
     Output voltage Vout is neither dependent upon resistive load RL nor resistors R 1  and R 2  in conventional LVDS driver circuit  100 . Thus, output voltage Vout remains constant even if there are variations in the value of resistive load RL, in supply voltage VDD, temperature, or fabrication process parameters. 
     Various other modifications and alterations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and spirit of this invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments.