Abstract:
Provided is an inverter circuit including a switching device which performs a switching operation corresponding to a gate control signal input to a gate terminal, converts an input DC to an AC, and outputs the AC; an HVIC which inputs the gate control signal to the gate terminal of the switching device; a controller which inputs to the HVIC a control signal for enabling the HVIC to generate the gate control signal; a bootstrap circuit which transmits energy to a high-side region of the HVIC; and an impedance cell which is located between the HVIC and one terminal of the switching device to reduce voltage drop of the high-side HVIC.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
         [0001]    This application claims the priority to Korean Patent Application No. 2003-18304, filed on Mar. 24, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to an inverter circuit, and more specifically, an inverter circuit with a switching device, in which a gate is driven by a high-voltage integrated circuit.  
           [0004]    2. Description of the Related Art  
           [0005]    With the broader use of low-power Insulated Gate Bipolar Transistor (IGBT) inverters of about 3.7 Kw or lower even in household appliances, more attention is being given to providing high efficiency and low electro-magnetic interference (EMI) noise and minimizing the cost, the size, and the weight of the inverters. Also, a high-voltage integrated circuit (HVIC) for a high-voltage gate driver is increasingly being used with the IGBT inverters. The HVIC enables not only reliable control of pulse width modulation (PWM) but also simplifies circuit construction and reduces costs.  
           [0006]    However, a gate driver implemented as an HVIC may generate latched gate output signals, which potentially could destroy the entire system. This is because a reference voltage, which is applied to the HVIC used for driving a gate, is floated and fluctuates at every moment an IGBT is switched. Such a latch phenomenon may occur due to an inverter power circuit and its parameters, a gate driving circuit and its parameters, the switching characteristics of the IGBT, the operating conditions of an inverter, and the like.  
           [0007]    [0007]FIG. 1 is a schematic diagram of a conventional, previously developed inverter circuit. FIG. 2 is a timing diagram showing an input signal and output signals of an HVIC at the inverter circuit of FIG. 1, wherein the output signals are generated when latch-on and latch-up occur, respectively.  
           [0008]    Referring to FIG. 1, an output terminal O of an HVIC  110  is connected to a gate terminal of an IGBT  130 , which is a switching device, through a gate series resistor R g . A gate control signal V g  is output through the output terminal O of the HVIC  110 . A capacitor  170 , which generates an input DC-link voltage V DC , is connected to a collector terminal of the IGBT  130  through a switch S 1    172 . Also, an inductive load L load    164  is connected to a node D, which is connected to an emitter terminal of the IGBT  130 . A stray inductor  161  having an inductance L stray , a diode  162 , and a shunt resistor  163  having a resistance R shunt  are connected in series to the node D. The node D is also connected to a node S, which is both an output terminal of the HVIC  110  and a terminal of a bootstrap circuit.  
           [0009]    The HVIC  110  includes two input terminals IN and C. The HVIC  110  receives a control input signal V in  from a controller  120  through the input terminal IN and receives an integrated circuit driving voltage V CC  through the input terminal C. A level-shift MOS transistor  155 , which is located inside the HVIC  110 , transmits to an edge triggering block  111  the control input signal V in , which is input from the input terminal IN, through a switching operation. The edge triggering block  111  senses a falling edge of the received control input signal V in  and maintains the control input signal IN until the next signal is input. The signal maintained by the edge triggering block  111  is input to the gate terminal of the IGBT  130  through a buffer  112  and the gate output terminal O.  
           [0010]    The HVIC  110  is connected to the bootstrap circuit, which includes a capacitor  151 , a bootstrap resistor  152 , a bootstrap diode  153 , and a bootstrap capacitor  154 , which are connected in series. The capacitor  151  transmits energy to a secondary power source of the HVIC  110 , i.e., the bootstrap capacitor  154 . The bootstrap resistor  152  prevents rapid charging of the bootstrap capacitor  154 . The bootstrap diode  153  protects the HVIC  110  and low-voltage devices from high voltage when the IGBT  130  is switched off. The bootstrap capacitor  154  functions as the secondary power source of the HVIC  110  and is connected to terminals B and S of the HVIC  110 .  
           [0011]    In the foregoing conventional inverter circuit, if a latch phenomenon occurs in the IGBT  130 , the gate control signal V g  output from the output terminal O of the HVIC  110  is not affected by the control input signal V in  output from the controller  120 . Thus, the IGBT  130  does not perform appropriate switching operations. That is, even if the HVIC  110  receives the control input signal V in  from the controller  120  as shown in (a) of FIG. 2, at time t6 where latch-on occurs, the gate control signal V g  output from the output terminal O of the HVIC  110  is not held in an off-signal state and abnormally generates an on-signal, as shown in (b) of FIG. 2. Also, at time t4 where latch-up occurs, the gate control signal Vg output from the output terminal O of the HVIC  110  is held in an off-signal state without generating an on-signal, as shown in (c) of FIG. 2. Therefore, the IGBT  130  is abnormally switched on at time t6 even though it should be switched off when the latch-on occurs, and is abnormally switched off at time t4 even though it should be switched on when the latch-up occurs.  
           [0012]    [0012]FIGS. 3A and 3B are signal diagrams showing an input signal waveform of an HVIC and a collector current of an IGBT when latch-up and latch-on occur, respectively.  
           [0013]    Referring to FIG. 3A, even if a control input signal Vin corresponding to switching-on data is input to an HVIC  110  at time t4, the collector current IC of an IGBT  130  does not increase. As is known, such latch-up occurs because a very high steady-state reverse voltage is generated at terminal S of the HVIC  110  due to a voltage drop caused by freewheeling current IFW flowing through diode  162  and a shunt resistor  163  between times t3 and t4.  
           [0014]    Referring to FIG. 3B, even if a control input signal Vin corresponding to switching-off data is input to the HVIC  110  at time t 6 , the collector current IC of the IGBT  130  decreases instantly and thereafter starts increasing again. As is known, such latch-on occurs due to forward conduction of parasitic diodes inside the HVIC  110  in an over-stress condition, such as no-load or rapid charging of the bootstrap capacitor  154 . In the over-stress condition, current flows through an internal Electro Static Discharge (ESD) diode located between two terminals B and S of the HVIC  110 , and the high-side IGBT  130  is turned on due to the current.  
           [0015]    Therefore, latch-on or latch-up may prevent steady switching operations of an inverter circuit, in which an IGBT  130  is switched by an HVIC  110 , thus potentially destroying elements of the inverter device.  
         SUMMARY OF THE INVENTION  
         [0016]    The present invention, in one embodiment, provides an inverter circuit having a switching device with a gate driven by a high-voltage integrated circuit (HVIC), the inverter circuit being capable of preventing latch-on and latch-up.  
           [0017]    In accordance with an aspect of the present invention, there is provided an inverter circuit comprising a switching device which performs a switching operation corresponding to a gate control signal input to a gate terminal, converts an input DC to an alternating current (AC), and outputs the AC; an HVIC which inputs the gate control signal to the gate terminal of the switching device; a controller which inputs to the HVIC a control signal for enabling the HVIC to generate the gate control signal; a bootstrap circuit which transmits energy to a high-side region of the HVIC; and an impedance cell which is located between the HVIC and one terminal of the switching device to reduce voltage drop of the high-side HVIC.  
           [0018]    The switching device is preferably an insulated gate bipolar transistor (IGBT). A collector terminal of the IGBT is connected to a DC input power source, and an emitter terminal thereof is connected to an output terminal.  
           [0019]    Herein, the impedance cell is preferably located between the HVIC and the emitter terminal of the IGBT.  
           [0020]    Preferably, the bootstrap circuit includes a power source; a bootstrap resistor connected in series to the power source; a bootstrap diode having an anode terminal connected in series to the bootstrap resistor and having a cathode terminal located in the opposite direction of the bootstrap resistor; and a bootstrap capacitor which is connected to both the cathode terminal of the bootstrap diode and a node that is commonly connected to the HVIC and the impedance cell.  
           [0021]    Preferably, the impedance cell includes a resistor.  
           [0022]    The impedance cell may include a resistor and a diode, which are connected in parallel to each other.  
           [0023]    Herein, the diode may be located such that an anode terminal of the diode is connected to the switching device and a cathode terminal thereof is connected to the HVIC or such that the anode terminal of the diode is connected to the HVIC and the cathode terminal thereof is connected to the switching device.  
           [0024]    The impedance cell may include a first resistor, a second resistor that is connected to the first resistor in parallel, and a diode connected to the first resistor in parallel and to the second resistor in series.  
           [0025]    Herein, the diode may be located such that an anode terminal of the diode is connected to the switching device and a cathode terminal thereof is connected to the HVIC through the second resistor or such that the anode terminal of the diode is connected to the HVIC through the second resistor and the cathode terminal thereof is connected to the switching device.  
           [0026]    Important technical advantages of the present invention are readily apparent to one skilled in the art from the following figures, descriptions, and claims. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0027]    For a more complete understanding of the present invention and for further features and advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:  
         [0028]    [0028]FIG. 1A is a schematic diagram of a conventional inverter circuit;  
         [0029]    [0029]FIG. 2 is a timing diagram showing an input signal and output signals of an HVIC for the conventional inverter circuit, wherein the output signals are generated when latch-on and latch-up occur, respectively;  
         [0030]    [0030]FIG. 3A is a signal diagram showing an input signal waveform of an HVIC and a collector current of an IGBT when latch-up occurs;  
         [0031]    [0031]FIG. 3B is a signal diagram showing an input signal waveform of an HVIC and a collector current of an IGBT when latch-on occurs;  
         [0032]    [0032]FIG. 4 is a schematic diagram of an inverter circuit according to an embodiment of the present invention;  
         [0033]    [0033]FIG. 5 is a table showing various exemplary implementations of an impedance cell shown in FIG. 4 and their equivalent resistances;  
         [0034]    [0034]FIG. 6 is an equivalent circuit schematic diagram when an IGBT is turned off in the inverter circuit shown in FIG. 4;  
         [0035]    [0035]FIG. 7 is a diagram showing turn-off switching signal waveforms in the equivalent circuit shown in FIG. 6;  
         [0036]    [0036]FIG. 8 is a schematic diagram showing an initial charging operation of the inverter circuit shown in FIG. 4;  
         [0037]    [0037]FIG. 9A is a signal diagram showing waveforms for measured terminal voltage of the HVIC and collector current of the IGBT at turn-off when there is variation in input capacitor voltage in the conventional inverter circuit shown in FIG. 1;  
         [0038]    [0038]FIG. 9B is a signal diagram showing waveforms for measured terminal voltage of the HVIC and collector current of the IGBT at turn-off when there is variation in input bias voltage in the conventional inverter circuit shown in FIG. 1;  
         [0039]    [0039]FIG. 9C is a signal diagram showing waveforms for measured terminal voltage of the HVIC and collector current of the IGBT at turn-off when there is variation in collector current in the conventional inverter circuit shown in FIG. 1;  
         [0040]    [0040]FIG. 9D is a signal diagram showing waveforms for maximum turn-off current, which does not cause latch-on, in the conventional inverter circuit shown in FIG. 1;  
         [0041]    [0041]FIGS. 10A through 10C are signal diagrams showing waveforms for measured terminal voltage of the HVIC and collector current of the IGBT at turn-off when there is variation in resistance and collector current in an inverter circuit using a Type B impedance cell, shown in FIG. 5, according to an embodiment of the present invention;  
         [0042]    [0042]FIGS. 11A through 11C are signal diagrams showing waveforms for measured terminal voltage of the HVIC and collector current of the IGBT at turn-off when there is variation in operating condition and collector current in the inverter circuit of FIG. 4 according to an embodiment of the present invention;  
         [0043]    [0043]FIG. 12A is a signal diagram showing waveforms for measured collector-emitter voltage, collector current, and energy loss of the IGBT at turn-off in the conventional inverter circuit shown in FIG. 1;  
         [0044]    [0044]FIG. 12B is a signal diagram showing waveforms for measured collector-emitter voltage, collector current, and energy loss of the IGBT at turn-off in the inverter using the Type B impedance cell shown in FIG. 5, according to an embodiment of the present invention;  
         [0045]    [0045]FIG. 13A is a signal diagram showing waveforms for measured collector-emitter voltage of the IGBT at turn-off under the condition of collector current variation in the conventional inverter circuit shown in FIG. 1;  
         [0046]    [0046]FIG. 13B is a signal diagram showing waveforms for collector current variation of the IGBT at turn-off in the conventional inverter circuit shown in FIG. 1;  
         [0047]    [0047]FIG. 14A is a signal diagram showing waveforms for measured collector-emitter voltage of the IGBT at turn-off when there is variation in collector current in the inverter circuit using the Type B impedance cell shown in FIG. 5, according to an embodiment of the present invention;  
         [0048]    [0048]FIG. 14B is a signal diagram showing waveforms for measured collector current of the IGBT at turn-off in the inverter circuit using the Type B impedance cell, shown in FIG. 5, according to an embodiment of the present invention;  
         [0049]    [0049]FIG. 15A is a diagram showing measured turn-off energy loss when there is variation of collector current in the IGBT at turn-off in the conventional inverter circuit and the inverter circuit using the Type B impedance cell shown in FIG. 5, according to an embodiment of the present invention;  
         [0050]    [0050]FIG. 15B is a showing measured dv/dt when there is variation in collector current of the IGBT at turn-off in the conventional inverter circuit and the inverter circuit using the Type B impedance cell shown in FIG. 5, according to an embodiment of the present invention;  
         [0051]    [0051]FIG. 16A is a signal diagram showing waveforms for measured collector-emitter voltage V CE , collector current I C , and energy loss E loss  of the IGBT at turn-on when there is low dv/dt control in the inverter circuit using a Type C impedance cell shown in FIG. 5, according to an embodiment of the present invention;  
         [0052]    [0052]FIG. 16B is a signal diagram showing waveforms for measured collector-emitter voltage V CE , collector current I C , and energy loss E loss  of the IGBT at turn-on when there is low dv/dt control in the conventional inverter circuit shown in FIG. 1;  
         [0053]    [0053]FIG. 17A is a signal diagram showing waveforms for measured collector-emitter voltage of the IGBT at low turn-on current when there is variation in resistance of the impedance cell in the inverter circuit using the Type C impedance cell, shown in FIG. 5, according to an embodiment of the present invention;  
         [0054]    [0054]FIG. 17B is a signal diagram showing measured collector current of the IGBT at low turn-on current when there is variation in resistance of the impedance cell in the inverter circuit using the Type C impedance cell shown in FIG. 5, according to an embodiment of the present invention;  
         [0055]    [0055]FIG. 18A is a signal diagram showing waveforms for measured collector-emitter voltage of the IGBT at high turn-on current when there is variation in resistance of the impedance cell in the inverter circuit using the Type C impedance cell, shown in FIG. 5, according to the present invention;  
         [0056]    [0056]FIG. 18B is a signal waveform diagram showing waveforms for measured collector current of the IGBT at high turn-on current when there is variation in resistance of the impedance cell in the inverter circuit using the Type C impedance cell shown in FIG. 5, according to an embodiment of the present invention;  
         [0057]    [0057]FIG. 19A is a diagram showing turn-on energy loss when there is variation in resistance of the impedance cell in the inverter circuit using the Type C impedance cell shown in FIG. 5, according to an embodiment of the present invention;  
         [0058]    [0058]FIG. 19B is a diagram showing dv/dt when there is variation in resistance of the impedance cell in the inverter circuit using the Type C impedance cell shown in FIG. 5, according to an embodiment of the present invention;  
         [0059]    [0059]FIG. 20A is a signal diagram showing measured collector-emitter voltage of the IGBT at low turn-off current when there is variation in resistance of the impedance cell in the inverter circuit using the Type B impedance cell shown in FIG. 5, according to an embodiment of the present invention;  
         [0060]    [0060]FIG. 20B is a signal diagram showing measured collector current of the IGBT at low turn-on current when there is variation in resistance of the impedance cell in the inverter circuit using the Type B impedance cell shown in FIG. 5, according to an embodiment of the present invention;  
         [0061]    [0061]FIG. 21A is a signal diagram showing measured collector-emitter voltage of the IGBT at high turn-off current when there is variation in resistance of the impedance cell in the inverter circuit using the Type B impedance cell shown in FIG. 5, according to an embodiment of the present invention;  
         [0062]    [0062]FIG. 21B is a signal diagram showing measured collector current of the IGBT at high turn-off current when there is variation in resistance of the impedance cell in the inverter circuit using the Type B impedance cell shown in FIG. 5, according to an embodiment of the present invention;  
         [0063]    [0063]FIG. 22A is a diagram showing turn-off energy loss when there is variation in resistance of impedance cell in the inverter circuit using the Type B impedance cell shown in FIG. 5, according to an embodiment of the present invention;  
         [0064]    [0064]FIG. 22B is a graph showing dv/dt when there is variation in resistance of the impedance cell in the inverter circuit using the Type B impedance cell, shown in FIG. 5, according to the present invention;  
         [0065]    [0065]FIG. 23 is a schematic diagram of the inverter circuit according to an embodiment of the present invention when a ground-short occurs;  
         [0066]    [0066]FIG. 24A is a signal diagram showing waveforms for an input control signal and collector current in the conventional inverter circuit when a ground-short occurs; and  
         [0067]    [0067]FIG. 24B is a signal diagram showing waveforms for an input control signal and collector current in the inverter circuit according to an embodiment of the present invention, when a ground-short occurs. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0068]    The present invention will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein.  
         [0069]    [0069]FIG. 4 is a schematic diagram of an inverter circuit according to an embodiment the present invention, and FIG. 5 is a table showing various exemplary implementations of an impedance cell shown in FIG. 4 and their equivalent resistances.  
         [0070]    Referring to FIG. 4, an output terminal O′ of an HVIC  410  is connected to a gate terminal of an IGBT  430 , which is a switching device, through a gate series resistor  431 . A capacitor  470  for generating an input DC-link voltage VDC is connected to a collector terminal of the IGBT  430 . An inductive load  464  is connected to an emitter terminal of the IGBT  430 . The emitter terminal of the IGBT  430  is connected in series to a stray inductor  461 , a diode  462 , and a shunt resistor  463 , which are connected in parallel to the inductive load  464 . Also, the emitter terminal of the IGBT  430  is connected to the HVIC  410  and a bootstrap circuit (comprising capacitor  451 , resistor  452 , diode  453 , and capacitor  454 ) through an impedance cell  440 .  
         [0071]    The HVIC  410  includes two input terminals IN′ and C′. The HVIC  110  receives a control input signal V in  from a controller  420  through the input terminal IN′ and receives an integrated circuit driving voltage V CC  through the input terminal C′. Although not shown in the drawings, HVIC  410  may comprise a level-shift MOS transistor, an edge triggering block, and a buffer. The level-shift MOS transistor transmits to the edge triggering block the control input signal V in , which is input from the input terminal IN′ through a switching operation. The edge triggering block senses a falling edge of the received input control signal V in  and maintains the input control signal V in  until the next signal is input. The signal maintained by the edge triggering block is input to the gate terminal of the IGBT  430  through the buffer and the gate output terminal O′.  
         [0072]    The HVIC  410  is connected to the bootstrap circuit, which includes a capacitor  451 , the bootstrap resistor  452 , the bootstrap diode  453 , and the bootstrap capacitor  454 , connected in series. As described above, the capacitor  451  transmits energy to a secondary power source of the HVIC  410 , i.e., the bootstrap capacitor  454 . The bootstrap resistor  452  prevents rapid charging of the bootstrap capacitor  454 . The bootstrap diode  453  protects the HVIC  410  and low-voltage devices from high voltage when the IGBT  430  is switched off. The bootstrap capacitor  454  functions as the secondary power source of the HVIC  410  and is connected to terminals B′ and S′ of the HVIC  410 .  
         [0073]    The impedance cell  440 , which is connected between the emitter terminal of the IGBT  430  and the output terminal S′ of the HVIC  410 , generally functions to suppress latch-up and latch-on in the HVIC  410 . Here, the terminal S′ of the HVIC  410  can be both a high-voltage floating ground terminal and a secondary ground terminal floated at a ground terminal of a primary input signal. The impedance cell  440  may include one or more resistors and diode.  
         [0074]    [0074]FIG. 5 shows various exemplary implementations for the impedance cell  440 . An Type A impedance cell  440  (hereinafter, type A) includes a resistor  431   a  having resistance R E(H) . A Type B impedance cell  440  (hereinafter, type B) includes a resistor  431   b  having resistance R E(H)  and a diode  432   b , which are connected in parallel. In type B, an anode terminal of the diode  432   b  is situated to connect to an emitter terminal of an IGBT  430 , and a cathode terminal thereof is an HVIC  410 . Like in type B, a Type C impedance cell  440  (hereinafter, type C) includes a resistor  431   c  having resistance R E(H)  and a diode  432   c , which are connected in parallel. However, unlike in type B, an anode terminal of the diode  432   c  is situated to connect to an HVIC  410 , and a cathode terminal thereof is situated to connect to an emitter terminal of an IGBT  430 . In a Type D impedance cell  440  (hereinafter, type D), a diode  432   d  and a resistor  433   d  having resistance Rs are connected in series. The diode  432   d  and the resistor  433   d  are connected in parallel to a resistor  431   d  having resistance R E(H) . In type D, an anode terminal of the diode  432   d  is situated to connect to an emitter terminal of an IGBT  430 , and a cathode terminal thereof connects to the resistor  433   d . Like in type D, an E-type impedance cell  440  (hereinafter type E) includes a diode  432   e  and a resistor  433   e  having resistance Rs, which are connected in a series. The diode  432   e  and the resistor  433   e  are connected in parallel to the resistor  431   e  having resistance R E(H) . However, an anode terminal of the diode  432   e  connects to the resistor  433   e , and a cathode terminal thereof situated to connect to an emitter terminal of an IGBT  430 .  
         [0075]    When an IGBT  430  is switched on and off, the equivalent resistances of the foregoing various impedance cells  440  are as follows. In type A, switching-on equivalent resistance Ron,eq is the resistance R E(H)  of the resistor  431   a  and equal to switching-off equivalent resistance Roff,eq. In type B, the switching-on equivalent resistance Ron,eq is 0, while switching-off equivalent resistance Roff,eq is the resistance R E(H)  of the resistor  431   b . In type C, switching-on equivalent resistance Ron,eq is the resistance RE(H) of the resistor  431   c , while switching-off equivalent resistance Roff,eq is 0. In type D, switching-on equivalent resistance Ron,eq is the sum of the resistances of the resistor  431   d  and the resistor  433   d , which are connected in parallel, i.e., resistance R E(H) //Rs. Switching-off equivalent resistance Roff,eq is the resistance R E(H)  of the resistor  431   d . In type E, switching-on equivalent resistance Ron,eq is the resistance R E(H)  of the resistor  431   e , and switching-off equivalent resistance Roff,eq is the sum of the resistances of the resistor  431   e  and the resistor  433   e , which are connected in parallel, i.e., the resistance R E(H) //Rs.  
         [0076]    The following Table 1 shows the various characteristics of the impedance cells  440 .  
                                         TABLE 1                                       Characteristics                        Control of latch       Type   On dv/dt control   Off dv/dt control   occurrence               A   Δ   Δ   Δ       B   X   ◯   ◯       C   ◯   X   X       D   ◯   ◯   ◯       E   ◯   ◯   ◯                  
 
         [0077]    Here, ◯ denotes the most optimal characteristic, X denotes the least optimal characteristic, and Δ denotes an intermediate characteristic.  
         [0078]    As shown in Table 1, various impedance cells  440  have different characteristics. Thus, the type of impedance cell  440  can be selected depending on system requirements. For example, type B and type C have only one of the equivalent resistances R on,eq  and R off,eq  and thus can be selected according to switching operations. By contrast, type A, type D, and type E have both the switching-on equivalent resistance R on,eq  and switching-off equivalent resistance R off,eq . Among them, type A has the simplest construction and thus can be selected when it is expected that there will be limited use of a target system. However, since resistance is the only design parameter, type A may not have optimum characteristics. Since type D and type E have independent resistances unlike type A, they may provide improved switching-on and switching-off characteristics.  
         [0079]    In comparison to latch-up, latch-on is a more severe and difficult problem because it is related to voltage drop in the stray inductor  461  and the current falling time at turn-off. The latch-up problem can be managed in the circuit design by considering maximum current level, shunt resistor value, and diode voltage drop at steady-state condition. For this reason, a mechanism where the latch-on is controlled by the impedance cell  440  will be chiefly described hereinafter. Nevertheless, the impedance cell  440  of the present invention can also be used for preventing the latch-up problem because the circuit basically has an effect on reducing the reverse voltage.  
         [0080]    [0080]FIG. 6 is an equivalent circuit schematic diagram when an IGBT is turned off in the inverter circuit shown in FIG. 4, and FIG. 7 is a diagram showing turn-off switching signal waveforms in the equivalent circuit shown in FIG. 6.  
         [0081]    To begin, as shown in FIG. 6, when the IGBT  430  is turned off, a gate series resistor  431  and the impedance cell  440  having turn-off equivalent resistance are connected in parallel between a node S′ connected to the HVIC  410  and a node D′, and, as shown in FIG. 4, a terminal voltage V GE  between a gate and an emitter of the IGBT  430  is connected as a voltage source between the gate series resistor  431  and the impedance cell  440 . In this equivalent circuit diagram, a terminal voltage at a node B′ is expressed as shown in Equation (1).  
           V   B   =V   RE(H)   +V   BS   −V   r,inst    (1)  
         [0082]    Here, V RE(H)  is a voltage drop in the impedance cell  440 .  
         [0083]    The instantaneous voltage V r,inst  is the sum of voltages applied to both terminals of a stray inductor  461 , a diode  462 , and, a shunt resistor  463  and is expressed as shown in Equation (2).  
               V     r   ,   inst       =         V     R   ,   shunt       +     V   D2     +     V   stray       =         I   FW          R   shunt       +     V   D2     +       L   stray                 I   FW            t                     (   2   )                               
 
         [0084]    Here, V R,shunt  is a voltage applied to both terminals of the shunt resistor  463 , V D2  is a voltage applied to both terminals of the diode  462 , and V stray  is a voltage applied to both terminals of the stray inductor  461 . Thus, turn-off equivalent voltage drop V Roff,eq  is expressed as shown in Equation (3).  
               V     Roff   ,   eq       =             R   g     //     R     off   ,   eq               R   BS     +     R   g       //     R     off   ,   eq           ×     V     r   ,   inst         +         R     off   ,   eq           R   g     +     R     off   ,   eq           ×   VGE               (   3   )                               
 
         [0085]    When the high-side IGBT  430  is turned off, the instantaneous voltage V r,inst  shown in Equation (2) is induced by freewheeling current IFW through the diode  462 , thereby causing the voltage drop at the node B′. That is, the voltage drop decreases by the amount of the turn-off equivalent voltage drop V Roff,eq  shown in Equation (3). As shown in FIG. 7, Equations 2 and 3 are applied after the timing t2 because the bootstrap diode  453  and the diode  462  do not conduct and also the instantaneous voltage V r,inst  is 0 between time t1 and t2. The turn-off equivalent resistance R off,eq  is experimentally selected to the minimum value of equivalent impedance which does not cause the latch-on problem.  
         [0086]    The equivalent resistor can be designed for controlling the turn-on switching can control dv/dt. When the voltage of the high-side IGBT  430  is decreased at turn-on, the parasitic capacitance of the HVIC  410  is charged through the equivalent resistance at the same time. The increased equivalent resistance compared to the conventional inverter circuit makes the transition slow and allows the dv/dt to be controlled. Because the HVIC  410  inherently has limited dv/dt rating at the node S′, the controllability of dv/dt also provides more safe operation of the HVIC  410 .  
         [0087]    [0087]FIG. 8 is a schematic diagram showing an initial charging operation of the inverter circuit shown in FIG. 4.  
         [0088]    As shown in FIG. 8, the high-side IGBT G 1  is connected to other elements like in the inverter circuit shown in FIG. 4. Thus, a gate of the high-side IGBT G 1  is controlled by the HVIC  810 . This circuit of FIG. 8 also includes a low-side IGBT G 2 . The gate of the low-side IGBT G 2 , is connected to and controlled by a driving IC  820 . An impedance cell  840  having turn-off equivalent resistance R off,eq  affects an initial charging mode of a bootstrap circuit. As illustrated with a bold line in the schematic, this is because when the low-side IGBT G 2  is turned on, a bootstrap capacitor  854  is charged through the impedance cell  840  having the turn-off equivalent resistance R off,eq . In this case, the gate-emitter voltage V GE  and an initial charging condition of the IGBT G 1  can be expressed as shown in Equations (4) and (5), respectively.  
               V   GE     =           R     off   ,   eq           R   BS     +     R     off   ,   eq                (       V   CC     -     V   DBS     -     V   G2       )       -     V     hvic   ,   diode                 (   4   )                 V   GE     ≺     V     Th   ,   min               (   5   )                               
 
         [0089]    Here, V DBS  is the forward voltage drop in the bootstrap diode  853 , V G2  is the forward voltage drop of the low-side IGBT G 2 , and V hvic,diode  is the forward voltage drop in the internal buffer of the HVIC.  
         [0090]    If the gate-emitter voltage V GE  of the IGBT G 1  reaches the threshold voltage level of the high-side IGBT G 1 , the IGBT G 1  is turned on and shoot-through occurs even though it is a very short time. Accordingly, the gate-emitter voltage V GE  of the high-side IGBT G 1  may need to be limited to a smaller value than the minimum threshold voltage V Th,min  of the IGBT G 1 .  
         [0091]    Meanwhile, capacitance QBS of the bootstrap capacitor  854  can be obtained using Equations (6) and (7).  
               Q   BS     ≥       2        Q   g       +       I     QBS   ,   max         f   sw       +     Q   ls     +       I     CBS   ,   lk         f   sw                 (   6   )                 C   BS     ≥     15   ×       2        Q   BS         Δ                 V                 (   7   )                               
 
         [0092]    Here, Q g  is gate charge of the high-side IGBT, I QBS,max  is the maximum quiescent current for the HVIC G 1 , I CBS,1k  is the leakage current of the bootstrap capacitor  854 , Q 1s  is level-shift charge required per cycle, and ΔV is the ripple voltage in the V BS .  
         [0093]    In the inverter circuit according to an embodiment of the present invention, power ratings of the components are varied depending on the type of the impedance cell ( 440  of FIG. 4). For example, in a cell of type B of FIG. 5, when the high-side IGBT  430  is turned on, the bootstrap capacitor  454  charges gate-emitter capacitance of the IGBT  430 . Thus, as shown in the following Equation (8), power dissipation in the equivalent resistor when the IGBT  430  is turned on can be obtained from the maximum capacitor energy C ge , which is divided by the gate series resistances R g  and the resistances R g  and R E(H)  of the impedance cell  440 .  
               P       RE        (   H   )       ,   on       =           R     E        (   H   )         ×     C   ge         2        (       R   g     +     R     E        (   H   )           )              V   ge   2     ×     (     1   -          t       R   t          C   ge             )     ×     f   sw               (   8   )                               
 
         [0094]    Here, t is 3R t C ge , R t  is the sum of R g  and R E(H) , and f SW  is switching frequency.  
         [0095]    Meanwhile, when the high-side IGBT  430  is turned off, the discharging of the gate voltage of the IGBT  430  and the charging of the bootstrap capacitor  454  occur simultaneously. Thus, when the IGBT  430  is turned off, power dissipation P RE(H), off in the equivalent resistor of the impedance cell  440  and power dissipation P RBS,off  in the bootstrap resistor  452  coupled with switching frequency can be expressed as shown in Equations (9) and (10), respectively.  
               P       RE        (   H   )       ,   off       =       f   sw     ×       ∫   0   off              V     R     E        (   H   )         2       R     E        (   H   )                   t                   (   9   )                 P     RBS   ,   off       =           R   BS          C   BS         2        (       R   BS     +     R     E        (   H   )                        (     Δ                   V   BS       )     2     ×     (     1   -          t       R   T          C   BS             )     ×     f   sw               (   10   )                               
 
         [0096]    Here, t is 3R T C BS , and R T  is the sum of R BS  and R E(H) .  
         [0097]    Accordingly, the total power dissipation in the equivalent resistor and bootstrap resistor can be expressed as shown in Equations (11) and (12), respectively  
           P   RE(H)   =P   RE(H),on   +P   RE(H),off    (11)  
         P RBS =P RBS,off    (12)  
         [0098]    Hereinafter, when an inverter circuit according to an embodiment of the present invention is used in practical applications, its various characteristics will be described with reference to graphs. In one example, the inverter circuit is used in an air conditioner, which generally requires high operating current in a condition where a switching frequency is low. In this inverter circuit, an impedance cell  440  is can be a Type B impedance cell of FIG. 5. However, even if other types of impedance cells of FIG. 5 are applied, similar results can be obtained. In this example, the following design parameters are used: input DC-link voltage V DC  is 200-450 V, integrated circuit driving power source V CC  is 13-18 V, maximum shut resistance R shunt,max  is 6.8 mΩ, limited maximum load current is 30 A, and switching frequency F SW  is 3 kHZ. Also, a low-speed type of the IGBT with the rating of 600V/10 A is used in the test.  
         [0099]    [0099]FIGS. 9A through 9C are signal diagrams showing waveforms for measured terminal voltage V B  of an HVIC  110  and collector current I C  of the IGBT  130  at turn-off when there are variations in system parameters V DC , V CC , and I C  in the conventional inverter circuit shown in FIG. 1. Also, FIG. 9D is a waveform diagram showing a waveform for maximum turn-off current, which does not cause latch-on, in the conventional inverter circuit shown in FIG. 1.  
         [0100]    In FIG. 9A, reference numerals  910   a ,  910   b , and  910   c  denote the terminal voltage V B  of the HVIC  110  when the DC-link voltage V DC  is 200V, 300V, and 400V, respectively. Reference numerals  920   a ,  920   b ,  920   c  denote the collector current I C  of the IGBT  130  when the DC-link voltage V DC  is 200V, 300V, and 400V, respectively. As shown in FIG. 9A, when the DC-link voltage V DC  is lowest, the terminal voltage a V B  of the HVIC  110 , i.e., voltage drop at a node B is lowest ( 910   a ) because of the fastest current falling time.  
         [0101]    Next, in FIG. 9B, reference numerals  930   a ,  930   b , and  930   c  denote the terminal voltages V B  of the HVIC  110  when the integrated circuit driving power source V CC  is 13V, 15V, and 18V, respectively. Reference numerals  940   a ,  940   b , and  940   c  denote the collector current I C  of the IGBT  130  when the integrated circuit driving power source V CC  is 13V, 15V, and 18V, respectively. As shown in FIG. 9B, when the integrated circuit driving power source V CC  is lowest (i.e., 13V), the terminal voltage V B  of the HVIC  110  (i.e., voltage drop at a node B′) is lowest ( 930   a ).  
         [0102]    Next, in FIG. 9C, reference numerals  950   a ,  950   b , and  950   c  denote the terminal voltage V B  of the HVIC  110  when the turn-off collector current I C  of the IGBT  130  is 5 A, 15 A, and 30 A, respectively. Reference numerals  960   a ,  960   b , and  960   c  denote waveforms of the collector current I C  of the IGBT  130  when the turn-off collector current I C  of the IGBT  130  is 5 A, 15 A, and 30 A, respectively. As shown in FIG. 9C, latch-on occurs at the largest collector current I C  of  30  A ( 960   c ) and the voltage drop of terminal voltage V B  is getting larger ( 950   c ) as the current is increased due to the faster current falling.  
         [0103]    Next, in FIG. 9D, reference character  970  denotes the terminal voltage V B  of the HVIC  110  under the worst condition where the DC-link voltage V DC  is 200 V and the integrated circuit driving power source V CC  is 13 V. Reference character  980   b  denotes the collector current I C  of the IGBT  130  under the worst condition where the DC-link voltage V DC  is 200 V and the integrated circuit driving power source V CC  is 13 V. As shown in FIG. 9D, the latch-on does not occur at a current level of 13 A, which is somewhat higher than the rated current of 10 A. At this time, the terminal voltage V B  becomes about −8 V.  
         [0104]    [0104]FIGS. 10A through 10C are signal diagrams showing waveforms for measured terminal voltage V B  of an HVIC  410  and collector current I C  of an IGBT  430  at turn-off when there is variation in the collector current I C  in an inverter circuit using a Type B impedance cell, shown in FIG. 5, according to the present invention, in a state where the resistance R BS  of a bootstrap resistor  452  and the equivalent resistance R E(H)  of an impedance cell  440  differ.  
         [0105]    In FIG. 10A, the resistance R BS  of the bootstrap resistor  452  is 75Ω and the equivalent resistance R E(H)  of the impedance cell  440  is 30Ω. Reference character  1010   a ,  1010   b , and  1010   c  denote the terminal voltage V B  of the HVIC  410  when the collector current I C  of the IGBT  430  are 5 A, 15 A, and 30 A, respectively. Reference numerals  1020   a ,  1020   b , and  1020   c  denote variation in the collector current I C  of the IGBT  430  when the collector current I C  of the IGBT  430  is 5 A, 15 A, and 30 A, respectively.  
         [0106]    In FIG. 10B, the resistance R BS  of the bootstrap resistor  452  is 100Ω and the equivalent resistance R E(H)  of the impedance cell  440  is 40Ω. Reference numerals  1030   a ,  1030   b , and  1030   c  denote the terminal voltage V B  of the HVIC  410  when the collector current I C  of the IGBT  430  is 5 A, 15 A, and 30 A, respectively. Reference numerals  1040   a ,  1040   b , and  1040   c  denote variation in the collector current I C  of the IGBT  430  when the collector current I C  of the IGBT  430  is 5 A, 15 A, and 30 A, respectively.  
         [0107]    In FIG. 10C, the resistance R BS  of the bootstrap resistor  452  is 125Ω and the equivalent resistance R E(H)  of the impedance cell  440  is 51Ω. Reference numerals  1050   a ,  1050   b , and  1050   c  denote the terminal voltage V B  of the HVIC  410  when the collector current I C  of the IGBT  430  is 5 A, 15 A, and 30 A, respectively. Reference numerals  1060   a ,  1060   b , and  1060   c  denote variation in the collector current I C  of the IGBT  430  when the collector current I C  of the IGBT  430  is 5 A, 15 A, and 30 A, respectively.  
         [0108]    The three cases as shown in FIGS. 10A through 10C are in the worst condition where the DC-link voltage V DC  is 200 V and the integrated circuit driving power source V CC  is 13 V. As shown in FIGS. 10A through 10C, the latch-on does not occur in any of these cases. As the equivalent resistance R E(H)  of the impedance cell  440  becomes higher, the negative level of the terminal voltage V B  becomes smaller. In particular, unlike in the conventional inverter circuit, the terminal voltage V B  has the minimum value in the current range of about 15 A. This is because larger blocking voltage across the equivalent resistance R E(H)  corresponding to larger negative voltage affects the gate voltage and makes the turn-off falling time slower. As a result, it can be inferred that the equivalent resistance R E(H)  of the impedance cell  440  may be selected to be 40Ω because it always holds the terminal voltage V B  positive.  
         [0109]    [0109]FIGS. 11A through 11C are signal diagrams showing waveforms for measured terminal voltage V B  of an HVIC  410  and collector current I C  of the IGBT  430  at turn-off when there are variations in operating condition and collector current I C  in the inverter circuit of FIG. 4 according to embodiments of the present invention.  
         [0110]    In FIG. 11A, operating temperature is −40° C. and the layout of a printed circuit board (PCB) is loose. Reference character  1110   a ,  1110   b , and  1110   c  denote the terminal voltage V B  of the HVIC  410  when the collector current I C  of the IGBT  430  is 5 A, 15 A, and 30 A, respectively. Reference numerals  1120   a ,  1120   b , and  1120   c  denote variation in collector current I C  of the IGBT  430  when the collector current I C  of the IGBT  430  is 5 A, 15 A, and 30 A, respectively.  
         [0111]    In FIG. 11B, operating temperature is −40° C. and the layout of a printed circuit board is tight. Reference character  1130   a ,  1130   b , and  1130   c  denote the terminal voltage V B  of the HVIC  410  when the collector current I C  of the IGBT  430  is 5 A, 15 A, and 30 A, respectively. Reference numerals  1140   a ,  1140   b , and  1140   c  denote variation in collector current I C  of the IGBT  430  when the collector current I C  of the IGBT  430  is 5 A, 15 A, and 30 A, respectively.  
         [0112]    In FIG. 11C, operating temperature is 25° C. and the layout of a printed circuit board is loose. Reference character  1150   a ,  1150   b , and  1150   c  denote the terminal voltage V B  of the HVIC  410  when the collector current I C  of the IGBT  430  is 5 A, 15 A, and 30 A, respectively. Reference numerals  1160   a ,  1160   b , and  1160   c  denote variation in collector current I C  of the IGBT  430  when the collector current I C  of the IGBT  430  is 5 A, 15 A, and 30 A, respectively.  
         [0113]    In the three cases as shown in FIGS. 11A through 11C, the resistance R BS  of the bootstrap resistor  452  is 75Ω, the equivalent resistance R E(H)  of the impedance cell  440  is 30Ω, the DC-link voltage V DC  is 200 V, and the integrated circuit driving power source V CC  is 13 V. As shown in FIGS. 11A through 11C, although the transient times of the current failings become different by the variation of operating temperature and the PCB layout, the undershoot levels are not changed. In particular, in FIG. 11B where the PCB layout is very tight, current falling time is shorter compared to FIG. 11A where the PCB layout is looser.  
         [0114]    [0114]FIG. 12A is a signal diagram showing waveforms for collector-emitter voltage V CE , collector current I C , and energy loss E loss  of the IGBT  130  in the conventional inverter circuit shown in FIG. 1. FIG. 12B is a signal waveform diagram showing collector-emitter voltage V CE , collector current I C , and energy loss E loss  of the IGBT  430  in the inverter using the Type B impedance cell, shown in FIG. 5, according to an embodiments of the present invention.  
         [0115]    In FIG. 12A, the resistance R BS  of the bootstrap resistor  152  and the gate series resistor R g  are 100Ω and 51Ω, respectively. In FIG. 12B, the resistance R BS  of the bootstrap resistor  452  and the equivalent resistance of the impedance cell  440  are 100Ω and 40Ω, respectively. In both cases, the DC-link voltage V DC  is 300 V, the integrated circuit driving power source V CC  is 15 V, and the collector current I C  is 10 A. As shown in FIGS. 12A and 12B, in two cases, the waveforms of the collector-emitter voltage V CE  and collector current I C  are similar, and thus the waveform of the energy loss E loss  is also similar.  
         [0116]    [0116]FIGS. 13A and 13B are signal diagrams showing waveforms for measured collector-emitter voltage V CE  and collector current I C , respectively, of the IGBT  130  at turn-off when there is variation in collector current I C  in the conventional inverter circuit shown in FIG. 1.  
         [0117]    In FIGS. 13A and 13B, the resistance R BS  of the bootstrap resistor  152  is 100Ω, the DC-link voltage V DC  is 300 V, and the integrated circuit driving power source V CC  is 15 V. In FIG. 13A, reference numerals  1310   a ,  1320   a ,  1330   a ,  1340   a , and  1350   a  denote the collector-emitter voltage V CE  of the IGBT  130  when the collector current I C  is 5 A, 10 A, 15 A, 20 A, and 30 A, respectively. In FIG. 13B, reference numerals  1310   b ,  1320   b ,  1330   b ,  1340   b , and  1350   b  denote the variation in the collector current I C  at turn-off when the collector current IC is 5 A, 10 A, 15 A, 20 A, and 30 A, respectively.  
         [0118]    As shown in FIGS. 13A and 13B, with an increase in current level, turn-off dv/dt increases and current falling time decreases. This result shows general switching characteristics of an IGBT. Accordingly, the over-voltage level is increased by the turn-off current value, resulting in greater potential for latch-on problem due to larger voltage drop at terminal voltage V B .  
         [0119]    [0119]FIGS. 14A and 14B are signal diagrams showing waveforms for collector-emitter voltage V CE  and collector current I C , respectively, of the IGBT  430  at turn-off when there is variation in collector current I C  in the inverter circuit using the Type B impedance cell, shown in FIG. 5, according to an embodiment of the present invention.  
         [0120]    In FIGS. 14A and 14B, in both cases, the resistance R BS  of the bootstrap resistor  452  and the equivalent resistance R E(H)  of the impedance cell  440  are 100Ω and 40Ω, respectively. Also, the DC-link voltage V DC  is 300 V and the integrated circuit driving power source V CC  is 15 V. In FIG. 14A, reference numerals  1410   a ,  1420   a ,  1430   a ,  1440   a , and  1450   a  denote the collector-voltage voltage V CE  of the IGBT  430  when the collector current I C  is 5 A, 10 A, 15 A, 20 A, and 30 A, respectively. In FIG. 14B, reference numerals  1410   b ,  1420   b ,  1430   b ,  1440   b , and  1450   b  denote the collector-voltage voltage V CE  of the IGBT  430  when the collector current I C  is 5 A, 10 A, 15 A, 20 A, and 30 A, respectively.  
         [0121]    As shown in FIGS. 14A and 14B, when the equivalent resistance R E(H)  of 40Ω is used, it is observed that the voltage rising and current falling times are almost unchanged. That is, dv/dt and di/dt can be actively controlled during turn-off transients by using the equivalent resistance R E(H)  of the impedance cell  440 . Thus, the desired latch-on immunity control can be also achieved even at large current operating conditions.  
         [0122]    [0122]FIGS. 15A and 15B are diagrams showing turn-off energy loss E loss  and dv/dt, respectively, of the IGBT  430  at turn-off when there is variation in collector current I C  in the inverter circuit using the Type B impedance cell, shown in FIG. 5, according to an embodiment of the present invention.  
         [0123]    In FIGS. 15A and 15B, reference numerals  1510   a  and  1520   a  denote energy loss Eloss and dv/dt, respectively, when the equivalent resistance R E(H)  of the impedance cell is 0Ω in the conventional inverter circuit. Also, reference numerals  1510   b  and  1520   b  denote energy loss E loss  and dv/dt, respectively, when the equivalent resistance R E(H)  of the impedance cell  440  is 40Ω in the inverter circuit of the present invention. As shown in FIGS. 15A and 15B, in a low operating current area, which is considered as less than the rated current level of around 10 A, even if dv/dt in the inverter circuit of the present invention is much slower, the turn-off energy loss E loss  is almost the same. However, in a high current area, the turn-off energy loss E loss  becomes larger due to much slower dv/dt and di/dt compared to the conventional inverter circuit.  
         [0124]    Hereinafter, the characteristics of the inverter circuit according to an embodiment of the present invention applied in high-performance water pump system with power rating of 300 W will be described with reference to graphs. The inverter circuit included in the high-performance water pump system requires low power and high switching speed. Accordingly, since a latch phenomenon does not occur due to low load current, dv/dt control is an importance consideration in this high-performance water pump. In this inverter circuit, an impedance cell  440  can be implemented as a Type B impedance cell of FIG. 5. However, even if other impedance cells of FIG. 5 are used, similar results can be obtained. In this example, the following design parameters are used. That is, input DC-link voltage V DC  is 200-400 V, integrated circuit driving power source V CC  is 13-15 V, maximum shut resistance R shunt,max  is 200 mΩ, limited maximum load current is 4 A, and switching frequency F SW  is 18 kHZ. Also, a high-speed IGBT having a rating of 3 A is used.  
         [0125]    [0125]FIG. 16A is a signal diagram showing waveforms for measured collector-emitter voltage V CE , collector current I C , and energy loss E loss  of the IGBT  430  at turn-on when there is low dv/dt control in the inverter circuit using a Type C impedance cell, shown in FIG. 5, according to an embodiment of the present invention, and FIG. 16B is a signal diagram showing waveforms for measured collector-emitter voltage V CE , collector current I C , and energy loss E loss  of the IGBT  130  at turn-on when there is low dv/dt control in the conventional inverter circuit shown in FIG. 1.  
         [0126]    In FIG. 16A, the resistance R BS  of the bootstrap resistor  452 , the gate series resistance R g , and the equivalent resistance R E(H)  of the impedance cell  440  are 51Ω, 51Ω, and 20Ω, respectively. In FIG. 16B, the resistance RBS of the bootstrap resistor  152  and the gate series resistance R g  are 51Ω and 560Ω, respectively. Also, in FIGS. 16A and 16B, reference numerals  1610   a  and  1610   b  denote the collector-emitter voltage V CE , and  1620   a  and  1620   b  denote the collector current I C . As shown in FIG. 16A, while the inverter circuit according to an embodiment of the present invention suffers energy loss of about 105 μJ, the conventional inverter circuit suffers energy loss of about 155 μJ. Therefore, despite the similar dv/dt slopes, the turn-on switching energy loss in the inverter circuit of one embodiment of the present invention is smaller by about 47% than in the conventional inverter circuit. As a result, in the inverter circuit of one embodiment of the present invention, di/dv is faster at turn-on, and over current caused by reverse-recovery of the freewheeling diode ( 462  of FIG. 4) decreases. In addition, propagation delay time taken for controlling pulse width modulation (PWM) is shorter.  
         [0127]    [0127]FIGS. 17A and 17B are signal diagrams showing waveforms for measured collector-emitter voltage V CE  and collector current I C , respectively, of the IGBT  430  at low turn-on current when there is variation of equivalent resistance R E(H)  of the impedance cell  440  in the inverter circuit using the Type C impedance cell, shown in FIG. 5, according to an embodiment of the present invention. FIGS. 18A and 18B are signal diagrams showing waveforms for collector-emitter voltage V CE  and collector current I C , respectively, of the IGBT  430  at high turn-on current when there is variation in equivalent resistance R E(H)  of the impedance cell  440  in the inverter circuit using the Type C impedance cell, shown in FIG. 5, according to an embodiment of the present invention.  
         [0128]    In FIGS. 17A and 17B, both signal waveforms are obtained under the low turn-on current condition, input DC-link voltage V DC  is 300 V, and integrated circuit driving power source V CC  is 15 V. In FIG. 17A, reference numerals  1710   a ,  1720   a ,  1730   a ,  1740   a , and  1750   a  denote the collector-emitter voltage V CE  when the equivalent resistance R E(H)  of the impedance cell  440  is 0Ω, 10Ω, 20Ω, 30Ω, and 40Ω, respectively. Likewise, in FIG. 17B, reference numerals  1710   b ,  1720   b ,  1730   b ,  1740   b , and  1750   b  denote the collector current I C  when the equivalent resistance R E(H)  of the impedance cell  440  is 0Ω, 10Ω, 20Ω, 30Ω, and 40Ω, respectively. In particular, when the equivalent resistance R E(H)  of the impedance cell  440  is 0Ω, the conventional inverter circuit without the impedance cell  440  can be used.  
         [0129]    In FIGS. 18A and 18B, both signal waveforms are obtained on the high turn-on current condition, input DC-link voltage V DC  is 300 V, and integrated circuit driving power source V CC  is 15 V. In FIG. 18A, reference numerals  1810   a ,  1820   a ,  1830   a ,  1840   a , and  1850   a  denote the collector-emitter voltage V CE  when the equivalent resistance R E(H)  of the impedance cell  440  is 0Ω, 10Ω, 20Ω, 30Ω, and 40Ω, respectively. Likewise, in FIG. 18B, reference numerals  1810   b ,  1820   b ,  1830   b ,  1840   b , and  1850   b  denote the collector current I C  when the equivalent resistance R E(H)  of the impedance cell  440  is 0Ω, 10Ω, 20Ω, 30Ω, and 40Ω, respectively. In particular, when the equivalent resistance R E(H)  of the impedance cell  440  is 0Ω, the conventional inverter circuit without the impedance cell  440  can be used.  
         [0130]    As shown in FIGS. 17A and 17B and FIGS. 18A and 18B, as the equivalent resistance R E(H)  of the impedance cell  440  increases, dv/dt is significantly reduced to about 2, for example, kV/μs or lower. When the IGBT  430  is turned on, dv/dt in a condition where a turn-on current is low (FIGS. 17A and 17B) is higher than that in a condition where a turn-on current is high (FIGS. 18A and 18B). By adjusting the equivalent resistance R E(H)  of the impedance cell  440 , the maximum turn-on current can be reduced but the turn-on di/dv slope is not affected. This is because the equivalent resistance R E(H)  of the impedance cell  440  is not higher than the gate resistance and thus the turn-on energy loss and the propagation delay time decrease to the minimum.  
         [0131]    [0131]FIGS. 19A and 19B are diagrams showing turn-on energy loss and dv/dt, respectively, when there is variation in equivalent resistance R E(H)  of the impedance cell  440  in the inverter circuit using the Type C impedance cell, shown in FIG. 5, according to an embodiment of the present invention.  
         [0132]    In FIGS. 19A and 19B, input DC-link voltage V DC  is 300 V, integrated circuit driving power source V CC  is 15 V, and operating temperature TC is 25° C. In FIG. 19A, reference numerals  1910   a  and  1910   b  denote the energy loss when the collector current I C  is 1 A and 3 A, respectively. Likewise, in FIG. 19B, reference numerals  1920   a  and  1920   b  denote dv/dt when the collector current I C  is 1 A and 3 A, respectively. As shown in FIGS. 19A and 19B, when the equivalent resistance R E(H)  of the impedance cell  440  is 10Ω or less, the dv/dt is almost constantly held. For example, when the equivalent resistance R E(H)  of the impedance cell  440  is about 20Ω, the turn-on dv/dt is about 2.5 kV/μs irrespective of current.  
         [0133]    When the IGBT is turned off, high current generates a high turn-off dv/dt, which is contrary to when the IGBT is turned on. Thus, turn-off dv/dt at a low current causes no problem to the IGBT inverter but high current is a consideration.  
         [0134]    [0134]FIGS. 20A and 20B are signal diagrams showing waveforms for collector-emitter voltage V CE  and collector current I C , respectively, of the IGBT  430  at low turn-off current when there is variation in equivalent resistance R E(H)  of the impedance cell  440  in the inverter circuit using the Type B impedance cell, shown in FIG. 5, according to an embodiment of the present invention. Also, FIGS. 21A and 21B are signal diagrams showing waveforms for collector-emitter voltage V CE  and collector current I C , respectively, of the IGBT at high turn-off current when there is variation in equivalent resistance R E(H)  of the impedance cell  440  in the inverter circuit using the Type B impedance cell, shown in FIG. 5, according to an embodiment of the present invention. Also, FIGS. 22A and 22B are diagrams showing turn-off energy loss and dv/dt, respectively, when there is variation in equivalent resistance R E(H)  of impedance cell  440  in the inverter circuit using the Type B impedance cell, shown in FIG. 5, according to an embodiment of the present invention.  
         [0135]    In FIGS. 20A and 20B, the both signal waveforms are obtained in a condition where turn-on current is as low as 1 A, input DC-link voltage V DC  is 300 V, and integrated circuit driving power source V CC  is 15 V. In FIG. 20A, reference numerals  2010   a ,  2020   a ,  2030   a , and  2040   a  denote the collector-emitter voltage V CE  when the equivalent resistance R E(H)  of the impedance cell  440  is 0Ω, 20Ω, 40Ω, and 68Ω, respectively. Likewise, in FIG. 20B, reference numerals  2010   b ,  2020   b ,  2030   b , and  2040   b  denote the collector current I C  when the equivalent resistance R E(H)  of the impedance cell  440  is 0 Ω, 20 Ω, 40Ω, and 68Ω, respectively. In particular, when the equivalent resistance R E(H)  of the impedance cell  440  is 0Ω, the conventional inverter circuit without the impedance cell  440  can be used.  
         [0136]    In FIGS. 21A and 21B, the both signal waveforms are obtained in a condition where turn-on current is as low as 4 A, input DC-link voltage V DC  is 300 V, and integrated circuit driving power source V CC  is 15 V. In FIG. 21A, reference numerals  2110   a ,  2120   a ,  2130   a , and  2140   a  denote the collector-emitter voltage V CE  when the equivalent resistance R E(H)  of the impedance cell  440  is 0 Ω, 20 Ω, 40Ω, and 68Ω, respectively. Likewise, in FIG. 21B, reference numerals  21   10   b ,  2120   b ,  2130   b , and  2140   b  denote the collector current IC when the equivalent resistance R E(H)  of the impedance cell  440  is 0Ω, 20Ω, 40Ω, and 68Ω, respectively. In particular, when the equivalent resistance R E(H)  of the impedance cell  440  is 0Ω, the conventional inverter circuit without the impedance cell  440  can be used.  
         [0137]    Next, in FIGS. 22A and 22B, input DC-link voltage V DC  is 300 V, integrated circuit driving power source V CC  is 15 V, and operating temperature TC is 25° C. In FIG. 22A, reference numerals  2210   a  and  2210   b  denote the energy loss when the collector current I C  is 1 A and 4 A, respectively. Likewise, in FIG. 22B, reference numerals  2220   a  and  2220   b  denote dv/dt when the collector current I C  is 1 A and 4 A, respectively.  
         [0138]    As shown in FIGS. 20A and 20B and FIGS. 22A and 22B, when the turn-off current is as low as 1 A, the equivalent resistance R E(H)  of the impedance cell  440  does not affect the dv/dt control. In practical use, the dv/dt of about 1.5 kV/μs or less is negligible. Also, as shown in FIGS. 21A and 21B, when the turn-off current is as high as 4 A and the equivalent resistance R E(H)  of the impedance cell  440  is about 20Ω or higher, the turn-off dv/dt is reduced.  
         [0139]    In typical applications such as a servo-driving system, detecting output current in an inverter is required in order to control current and protect a ground-short. If a ground-short occurs, an induced high current may latch on an HVIC at turn-off, thereby damaging the entire system.  
         [0140]    [0140]FIG. 23 is a schematic diagram of an example of the inverter circuit according to an embodiment of the present invention. Specifically, FIG. 23 is a circuit diagram of the inverter circuit using the Type A impedance cell  440  when a ground-short occurs. In FIG. 23, the same reference numerals as in FIG. 4 denote the same elements. Also, FIG. 24A is a signal diagram showing waveforms for an input control signal IN and collector current I C  in the conventional inverter circuit when a ground-short occurs, and FIG. 24B is a signal diagram showing waveforms for an input control signal IN and collector current I C  in the inverter circuit according to an embodiment of the present invention when a ground-short occurs.  
         [0141]    As shown in FIG. 23, if a ground-short denoted by “A” occurs, an emitter terminal of the IGBT  430  (or one terminal of the impedance cell  440 ) is grounded. Then, as shown in FIG. 24A, when the equivalent resistance R E(H)  of the impedance cell  440  is about 0Ω in the conventional inverter circuit, high di/dt occurs due to a high negative voltage drop at node B. Thus, latch-on occurs while the IGBT  430  is being turned off. However, as shown in FIGS. 24B, when the equivalent resistance R E(H)  of the impedance cell  440  is about 40Ω in the inverter circuit of one embodiment of the present invention, the latch-on does not occur. In the two cases, while the IGBT is being turned off, maximum current level is similar but current falling time differs.  
         [0142]    As explained herein, the inverter circuit of some embodiments of the present invention includes an IGBT as a switching device, in which an impedance cell is located between an output terminal of an HVIC for generating a gate control signal and an emitter terminal of the IGBT. Thus, the voltage drop is reduced at one output terminal of the HVIC. As a result, both the latch-on and the latch-up can be suppressed and the dv/dt can be effectively controlled.  
         [0143]    While the present invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims. For example, a metal oxide semiconductor field effect transistor (MOSFET) can be used as a switching device in place of an IGBT. In this case, a drain and a source of the MOSFET can take place of a collector and an emitter of the IGBT.