Abstract:
An electronically controlled fuel injection system in which terminating fuel injection is improved is disclosed. A reference position detector is adapted to generate a synchronizing signal at the predetermined angular position of an engine. A first computing circuit is connected to compute the required fuel injection interval in response to the synchronizing signal and a second computing circuit is connected to compute the rotation interval between two synchronizing signals successively generated. A further computing circuit is connected to compute the time interval which is equal to the difference between the rotation interval and the injection interval. The fuel injection is started when the time interval computed by the further computing circuit has passed after the generation of the synchronizing signal and is attained during the computed injection interval, whereby the fuel injection is terminated at the same position as the predetermined angular position.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to electronically controlled fuel injection systems for internal combustion engines which are designed so that the amount of fuel injected is controlled by the duration of fuel injection, and more particularly the invention relates to such fuel injection system wherein the time of fuel injection ending is improved to be substantially synchronized with a predetermined rotational angle of the engine. 
     2. Description of the Prior Art 
     In the past, there have been electronically controlled fuel injection systems in which the amount of fuel supplied to an internal combustion engine is controlled in accordance with the duration of fuel injection by the opening of fuel injectors, and in a system of this type the beginning of fuel injection is synchronized with a predetermined rotational angle of the engine crankshaft. Thus, if, for example, the beginning of fuel injection is synchronized with the beginning of the suction stroke in the case of a four-cycle internal combustion engine, the injection time per stroke will be reduced at high engine rotational speeds with the resulting danger of causing the fuel injection to extend over part of the following compression stroke. Thus, particularly in the case of an engine in which fuel is fed directly into the engine, there is a disadvantage that the high cylinder pressure causes insufficient injection of fuel. Also, in the case of a two-cycle internal combustion engine, there is a disadvantage that since the suction stroke and the scavenging stroke overlap each other, the injection of the fuel is continued even during the scavenging process, thus causing the emission of unburned gases. 
     SUMMARY OF THE INVENTION 
     With a view to overcoming the foregoing deficiencies, it is the object of this invention to provide an electronically controlled fuel injection system for internal combustion engines wherein the moment at which fuel injection is commenced is determined in accordance with the time required for the engine crankshaft to rotate through a predetermined angle and the duration of the fuel injection into the engine, and the fuel is injected and supplied for the required period of time, thus causing the injection of the fuel to end at a predetermined angular position of the crankshaft. 
     The system of this invention has among its great advantages the fact that since the injection of fuel can be caused to and at a desired rotational angle of the crankshaft, by suitably adjusting this crankshaft angular position, it is possible to especially effectively effect the injection of fuel into the cylinders of an internal combustion engine as well as the injection of fuel into the two-cycle internal combustion engines, and it is also possible to effectively effect the injection of fuel in the four-cycle internal combustion engines as well as the rotary-type internal combustion engines wherein the injection of the fuel is effected before a predetermined crank angle. 
     The above and other objects and many of the attendant advantages of this invention will be apparent from the following description taken in connection with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing the general construction of an embodiment of this invention. 
     FIG. 2 is a wiring diagram showing a detailed construction of the embodiment shown in FIG. 1. 
     FIG. 3 is a signal waveform diagram useful in explaining the operation of the system of this invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The present invention will now be described with reference to the embodiment shown in the accompanying drawings. Referring to FIG. 1 showing the general construction of the embodiment, numeral 100 designates a reference position detector for generating a pulse signal or synchronizing signal per 1/2 revolution of the crankshaft in synchronism with predetermined angular positions of the crankshaft of a two-cylinder, two-cycle internal combustion engine which is not shown, 110 a pulse reshaping circuit for reshaping the waveform of the pulse signals generated from the reference position detector 100 and generating a pulse signal per 1/2 revolution of the crankshaft, 120 an oscillator circuit for generating clock pulses of a fixed frequency. Numeral 130 designates a D/A converter circuit for generating a voltage proportional to the number of pulses generated from the oscillator circuit 120, 140 an intake air amount detector disposed in the intake pipe of the engine to generate a voltage proportional to the amount of intake air Q, 150 a comparator circuit for comparing the voltage generated from the D/A converter circuit 130 with the voltage generated from the intake air amount detector 140 to generate a pulse signal having a time duration proportional to the amount of intake air Q per 1/2 crankshaft revolution, and the comparator circuit 150 generates such pulse signal for every 1/2 crankshaft revolution. Numeral 160 designates a constant value setting circuit for setting a constant K, 170 a first computing circuit for performing the binary multiplication of the output value of the constant value setting circuit 160 and the output value of the comparator circuit 150 to generate a binary coded output proportional to the value K × Q, 180 a second computing circuit for computing the rotational speed N from the pulse signals generated by the pulse reshaping circuit 110 and performing the binary multiplication between the reciprocal 1/N of the rotational speed and the output value K × Q of the first computing circuit 170 to generate a binary coded signal, and the binary coded output generated from the second computing circuit 180 represents the product K × Q/N. Numeral 200 designates a trigger pulse generating circuit for subtracting the output value K × Q/N of the second computing circuit 180 from the interval of the 1/2 crankshaft revolutions computed from the pulse signals from the pulse reshaping circuit 110 to generate a trigger signal. Numeral 300 designates an injection control circuit whereby in synchronism with the trigger signal from the trigger signal generating circuit 200 the output value K × Q/N of the second computing circuit 180 is proportionally converted into a pulse signal having a time duration to thereby control the fuel injection duration, 400 a power amplifier circuit for amplifying the pulse signal generated from the injection control circuit 300 and having a time duration indicative of the amount of fuel to be injected into the proper cylinder. Numerals 10 and 20 designate electromagnetically operated fuel injectors disposed for the respective cylinders. 
     Next, the detailed construction and operation of the individual circuits shown in FIG. 1 will be described with reference to FIGS. 2 and 3. Although not shown in detail, the reference position detector 100 may for example comprise a permanent magnet fixedly mounted on the rotary member of the ignition system distributor and a pair of winding cores arranged around the rotary member at equal intervals, whereby the pulse signals shown in (A 1 ) and (A 2 ) of FIG. 3 are generated at intervals of 1/2 crankshaft revolution. The synchronizing pulse signals A 1  and A 2  are respectively synchronized with the bottom dead center (BDC) of the crank of the first and second cylinders. 
     The pulse reshaping circuit 110 comprises pulse generating circuits 110a and 110b and an OR gate 111, and the pulse generating circuit 110a comprises a DC amplifier 112 (e.g., the Motorola IC MC3302P), a buffer 113, a resistor 114, a capacitor 115, an inverter 116 and a NOR gate 117. The other pulse generating circuit 110b is identical in construction with the pulse generating circuit 110a. The pulse signals A 1  and A 2  are amplified and reshaped by the pulse reshaping circuit 110 which in turn generates the pulse signals B 1  and B 2  shown in (B 1 ) and (B 2 ) of FIG. 3 and the reset signal R 0  shown in (R 0 ) of FIG. 3. 
     Although not shown in detail, the oscillator circuit 120 may comprise a known type of oscillator circuit employing a crystal unit so as to generate clock signals of a fixed frequency. The oscillator circuit 120 includes four frequency dividers so as to provide clock signals of four different frequencies. 
     The D/A converter circuit 130 comprises a binary counter 131 and a ladder-type resistor network of resistors having resistance values R 1  and R 2 , respectively, whereby each time the binary counter 131 is reset by the reset signal R 0  generated by the pulse reshaping circuit 110, the binary counter 131 counts the clock signals applied from the oscillator circuit 120 and its count value is converted into a voltage by the ladder-type resistor network. Consequently, the D/A converter circuit 130 generates at its output terminal C a sawtooth voltage proportional to the time as shown in (C) of FIG. 3. 
     The comparator circuit 150 comprises a voltage comparator 151, an R-S flip-flop 152 and a NOR gate 153, and the comparator 151 compares the sawtooth voltage with the voltage V Q  generated from the intake air amount detector 140 so that when the sawtooth voltage becomes higher than the voltage V Q  proportional to the intake air amount Q, a &#34;1&#34; signal is generated and the R-S flip-flop 152 is set. In response to the reset signal R 0  and the Q output signal of the R-S flip-flop 152, the NOR gate 153 generates at its output terminal D the pulse signal D shown in (D) of FIG. 3. More specifically, this pulse signal D has a time duration T Q  which is proportional to the intake air amount Q. 
     Although not shown in detail, the constant value setting circuit 160 is designed so that as for example, a constant for determining the air-fuel ratio and the rate of increase of the fuel injection amount corresponding to the engine cooling water temperature or the rate of increase of the fuel injection amount for acceleration or idling operation are computed to generate a binary coded output value &#34;I 10 , --- ---, I 1  &#34; corresponding to a constant K. Here, I n  indicates the binary digit at the n-th digit position, and all binary coded values will hereinafter be indicated in the similar manner. 
     The first computing circuit 170 comprises a parallel adder 171 (e.g., the RCA IC CD4008), memories 172 and 173 (e.g., the RCA IC CD4035), an AND gate 174 and a decade divider/counter 175 (e.g., the RCA IC CD4017), and the memory 172 has its outputs &#34;L 18 , ---, L 1  &#34; feedback coupled to provide inputs &#34;J 18 , ---, J 1  &#34; to the parallel adder 171. The constant value setting circuit 160 applies its outputs &#34;I 10 , ---, I 1  &#34; to inputs &#34;K 10 , ---, K 1  &#34; of the parallel adder 171, and the decade divider/counter 175 is so designed that when it receives six clock signals, the counting of further clock signals is inhibited. Thus, when the pulse signal D having the time duration T Q  is applied from the comparator circuit 150 to the AND gate 174, n clock signals from the oscillator circuit 120 are passed to an output terminal G of the AND gate 174 in proportion to the time duration T Q  as shown in (G) of FIG. 3. After the output signal of the comparator circuit 150 has gone to &#34; 0&#34;, the decade divider/counter 175 counts the clock signals so that a &#34;1&#34; signal is generated at terminals G 2 , G 4  and G 6 , respectively, as shown in (G 2 ), (G 4 ) and (G 6 ) of FIG. 3 when the counter 175 counts the second, fourth and sixth clock signals, respectively. When the counter 175 counts the fourth clock signal, the memory 172 is reset and its outputs &#34;L 18 , ---, L 1  &#34; are reset to &#34;0, ---, 0&#34;. Thereafter, in response to the application from the AND gate 174 of the clock signals shown in (G) of FIG. 3, the output &#34;L 18 , ---, L 1  &#34; of the memory 172 change to &#34;I 10 , ---, I 1  &#34;, 2 × &#34;I 10 , ---, I 1 ,&#34; n × &#34;I 10 , ---, I 1 .&#34;  On the other hand, when the counter 175 counts the second clock signal, the memory 173 stores the higher ten digits of the output n × &#34;I 10 , ---, I 1  &#34; as &#34;M 10 , ---, M 1 .&#34;  In this case, since the number of clock pulses n is a value proportional to the intake air amount Q and the output &#34;I 10 , ---, I 1  &#34; represents a binary code indicative of the constant K, the first computing circuit 170 generates a binary coded output indicative of the product K × Q. 
     The second computing circuit 180 is identical in construction with the first computing circuit 170 except that it additionally includes an R-S flip-flop 186. The R-S flip-flop 186 is designed so that it generates at its Q output terminal a pulse signal having a time duration T N  which is inversely proportional to the engine rotational speed N, and the application of the clock signals to a memory 182 through an AND gate 184 is inhibited in response to the occurrence of an input signal to a memory 183. With this second computing circuit 180, the output &#34;M 10 , ---, M 1  &#34; is added up as many times as the number of clock pulses m generated from the oscillator circuit 120 during the time duration T N  corresponding to the reciprocal 1/N of the rotational speed N, and a binary coded output &#34;N 10 , ---, N 1  &#34; indicative of m × &#34;M 10 , ---, M 1  &#34; is generated as its output. Namely, the second computing circuit 180 performs multiplication K × Q/N. 
     The trigger pulse generating circuit 200 comprises a reference position pulse period counting circuit 210, a subtracting circuit 220, a first converter circuit 230, a second converter circuit 250, and decade dividers/counters 260 and 270. The reference position pulse period counting circuit 210 comprises a binary counter 201, a counter 203 which is identical in circuit construction with the decade divider/counter 185, an R-S flip-flop 204, an AND gate 202 and a memory 205, and the reference position pulse period corresponds to the time duration T N  corresponding to the reciprocal of the engine rotational speed N. Each time the binary counter 201 is reset by the reset pulse R generated from the decade divider/counter 203 and shown in (R) of FIG. 3, the binary counter 201 counts the clock pulses applied from the oscillator circuit 120 through the AND gate 202 and its count value is generated as a binary coded output &#34;C 10 , ---, C 1  &#34; and stored in the memory 205 which in turn generates a binary coded output &#34;D 10 , ---, D 1 .&#34; This binary coded output &#34;D 10 , ---, D 1  &#34; is inversely proportional to the engine rotational speed N since the AND gate 202 is allowed to pass the clock pulses during a predetermined constant interval. The subtracting circuit 220 comprises a parallel inverter 221 and a parallel adder 222, whereby the output value &#34;N 10 , ---, N 1  &#34; (the binary code corresponding to K × Q/N) of the second computing circuit 180 is applied through the inverter 221 to inputs &#34;B 10 , ---, B 1  &#34; of the parallel adder 222 and the output value &#34;D 10 , ---, D 1  &#34; (the binary code corresponding to T N ) of the reference position pulse period counting circuit 210 is applied to inputs &#34;A 10 , ---, A 1  &#34; of the parallel adder 222. The parallel adder 222 performs the subtraction (T N  - K × Q/N) and generates a binary coded output &#34;P 10 , ---, P 1  &#34; indicative of the subtraction result. The first converter circuit 230 comprises a binary counter 231, EXCLUSIVE OR gates 232 to 241, a NOR gate 242 and an R-S flip-flop 243. After the binary counter 231 and the R-S flip-flop 243 have been reset by the pulse signal B 1  from the pulse reshaping circuit 110, the binary counter 231 counts the clock pulses applied from the oscillator circuit 120. When the count value of the binary counter 231 becomes equal to the binary coded output &#34;P 10 , ---, P 1  &#34; of the subtracting circuit 220, the R-S flip-flop 243 is set. The R-S flip-flop 243 generates the pulse signal P 1  shown in (P 1 ) of FIG. 3 during the period from the time it is reset until it is set, and this time duration is proportional to the binary coded output or the difference value (T N  - K × Q/N) from the subtracting circuit 220. The second converter circuit 250 is identical in circuit construction with the first converter circuit 230, and the pulse signal B 2  is applied from the pulse reshaping circuit 110 to the second converter circuit 250 thus causing it to generate the pulse signal P 2  shown in (P 2 ) of FIG. 3. The time duration of this pulse signal P 2  is also proportional to the output of the subtracting circuit 220. The decade divider/counter 260 is designed so that each time three clock signals are counted the counting of further clock signals is inhibited, and the trigger pulse signal F 1  shown in (F 1 ) of FIG. 3 is generated in response to the first clock signal applied after the counter 260 has been reset by the pulse signal P 1  from the first converter circuit 230. The decade divider/counter 270 is identical in circuit construction with the counter 260, and the trigger pulse signal F 2  shown in (F 2 ) of FIG. 3 is generated in response to the first clock signal applied after the counter 270 has been reset by the pulse signal P 2  from the second converter circuit 250. 
     The injection control circuit 300 comprises a third converter circuit 310 and a fourth converter circuit 320. The third converter circuit 310 is identical in circuit construction with the first converter circuit 230, and it receives as its reset signal the trigger pulse signal F 1  generated from the counter 260 and shown in (F 1 ) of FIG. 3 and as its binary coded input signal the binary coded output &#34;N 10 , ---, N 1  &#34; of the second computing circuit 180. Thus, the third converter circuit 310 generates as shown in (S 1 ) of FIG. 3 a pulse signal S 1  having a time duration τ 1  in synchronism with the trigger pulse signal F 1 . This time duration τ 1  is proportional to the binary coded output &#34;N 10 , ---, N 1  &#34; or the output value K × Q/N of the second computing circuit 180, and this time duration determines the fuel injection duration τ 1  for the first cylinder. The fourth converter circuit 320 is identical in circuit construction with the third converter circuit 310, and it receives as its reset signal the trigger pulse signal F 2  generated by the counter 270 and shown in (F 2 ) of FIG. 3 and as its binary coded input the binary coded output of the second computing circuit 180. Thus, the fourth converter circuit 320 generates as shown in (S 2 ) of FIG. 3 a pulse signal S 2  having a time duration τ 2  in synchronism with the trigger pulse signal F 2 . This time duration τ 2  is also proportional to the output value K × Q/N of the second computing circuit 180 and it determines the fuel injection duration τ 2  for the second cylinder. 
     The power amplifier circuit 400 is of a known type which amplifies the output pulse signals S 1  and S 2  of the injection control circuit 300, whereby through the power amplifier circuit 400, the fuel injector 10 for the first cylinder is opened for the duration τ 1  of the injection signal S 1  shown in (S 1 ) of FIG. 3, and the fuel injector 20 for the second cylinder is opened for the duration τ 2  of the injection signal S 2  shown in (S 2 ) of FIG. 3, thus injecting and supplying fuel under pressure to the engine which is not shown. 
     In the above-described operation, the pulse signals B 1  and B 2  respectively synchronized with the pulse signals A 1  and A 2  are respectively generated once every crankshaft revolution with a phase difference of a half period therebetween, and the reset signal R 0  is generated once every 1/2 crank-shaft revolution. However, the periods T N  of the succeeding reset signals R 0  do not differ much from each other and remain practically the same. Thus, since the trigger pulse generating circuit 200 generates a trigger pulse signal at the expiration of a time corresponding to one period T N  of the reset signals R 0  minus the fuel injection time τ after the generation of the reset pulse R 0 , if the injection of fuel is commenced after the generation of the trigger pulse, the injection of the fuel can be ended practically at a predetermined crankshaft angular position. While the above-described embodiment is designed to compute digitally, the objects of the present invention can also be accomplished by one which computes analogically.