Abstract:
A laminated substrate structure composed of a plurality of dielectric layers and a plurality of circuit layers stacked with each other. Each of the dielectric layers has a plurality of via studs, and the circuit layers are electrically coupled with each other through the via studs. The laminated substrate structure of the present invention is characterized by adopting the embedded structure landless design that provides high reliability and better adherence. The present invention also provides a laminated substrate manufacture method. The dielectric layers having the patterned circuit and the dielectric layers having the via holes are formed first, and after the dielectric layers having the patterned circuit and the dielectric layers having the via holes are formed, they are aligned and laminated synchronously to complete the manufacture of the laminated substrate.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
         [0001]    This application claims the priority benefit of Taiwan application serial no. 91111329, filed May 28, 2002.  
         BACKGROUND OF INVENTION  
         [0002]    1. Field of Invention  
           [0003]    The present invention generally relates to a laminated substrate structure and the manufacture method thereof, and more particularly, to a package substrate or Printed Circuit Board (PCB) structure and the manufacture method thereof.  
           [0004]    2. Description of Related Art  
           [0005]    In line with fast growth and the high demand for electronic technology, the development of electronic products tends towards miniaturization and high density integration. In the packaging field, the development of the Ball Grid Array (BGA) and Chip Scale Package (CSP) is targeted at the market requirements for miniaturization and high-density integration. For the Printed Circuit Board (PCB), in order to minimize the circuit area used, the technology of the multi-layered structure is applied. However, the substrate used in BGA, CSP and the manufacture of PCB all uses vias that are made of conductive material to connect between layer circuits. Therefore, the fine trace circuit on the laminated substrate and the small dimension vias can improve the package density and the PCB integration.  
           [0006]    The conventional laminated substrate manufacture method is mainly divided into two categories: lamination process and build up process. The lamination process provides a plurality of isolation layers first, then forms a circuit layer on the surface of the isolation layers, and performs the drill, plate, and hole plugging process on each isolation layer to form a plating through hole (PTH), so that the circuit layer on the surface of the isolation layer is electrically coupled by the plating through hole formed by the via process. After the via is formed in each isolation layer, the conductive circuit is subsequently formed on the laminated surface copper layer. Afterwards, the substrate or the circuit board is made by repeatedly performing a process that comprises aligning a determined number of the isolation layers to the surface copper layer, laminating them into a laminated substrate, and forming a conductive circuit.  
           [0007]    When the laminated substrate is made by using the conventional lamination process, the via forming, plating through hole and the isolation material hole plugging operations must be performed on the isolation layer, and the process is rather sophisticated and time consuming. Moreover, the process difficulty and unit cost significantly increase accordingly when the isolation layer via dimension approaches 100 micrometers or below. When the via dimension is less than 100 micrometers or below, there is as yet no mass production product provided by vendors. Therefore, there is a mass production technology bottleneck problem when the plating through hole is less than 100 micrometers.  
           [0008]    Besides the lamination process, the build up process is also broadly adopted by vendors. The build up process mainly forms the dielectric layer, the inter-layer via in the dielectric layer, and the circuit layer on the surface of the dielectric layer sequentially from bottom to over both sides of the laminated core substrate. The dielectric layer in the laminated substrate is mainly formed by using the lamination or coating method. After the dielectric layer is formed, an opening is formed in the dielectric layer by using the image forming/etching process or the laser/plasma etch method, and the inter-layer via is formed by filling the conductive material into the opening or by using the plating method. After the inter-layer via is formed, a sophisticated chemical surface process is performed and the circuit layer is formed on the surface of the dielectric layer. The laminated substrate is formed by repeatedly performing the sophisticated and difficult manufacture steps of the dielectric layer, inter-layer via, chemical surface process, and forming the circuit layer.  
           [0009]    In the substrate formed by the build up process, each dielectric layer and circuit layer has to be formed sequentially, so that the whole process is too lengthy. Moreover, the quality of forming each dielectric layer and circuit layer directly impacts the yield of the whole building substrate, thus it is not easy to control the process yield. When the substrate is formed by the build up process, besides the problem of the lengthy process and the low process yield, it also has the problems of high process cost and big equipment investment cost, or the reliability deteriorates due to the process not being easy to control.  
           [0010]    [0010]FIG. 1 schematically shows a sketch view of the contact position of the circuit layer and the via in the conventional laminated substrate structure, wherein the contact position has a via land. Referring to FIG. 1, a circuit  100   a  and a via land  102   a  are isolated from a circuit  100   b  and a via land  102   b  by a dielectric layer (not shown). The dimensions of the via land  102   a ,  102   b  are usually designed to be wider than the linewidth of the circuit  100   a ,  100   b , so as to assure that two circuit layers are electrically coupled by the via  104  in the dielectric layer. However, the via land  102   a  and the via land  102   b  usually reduce the layout space of the circuit layer, so that the circuit density in the laminated substrate cannot be efficiently improved.  
         SUMMARY OF INVENTION  
         [0011]    Therefore, the object of the present invention is to provide a laminated substrate structure, in which a landless design is applied onto the contact position of its circuit layer and its via to improve the circuit density in the laminated substrate.  
           [0012]    Another object of the present invention is to provide a laminated substrate structure, wherein the structure has good electrical performance and good thermal performance.  
           [0013]    Another object of the present invention is to provide a laminated substrate manufacture method, wherein the manufacture method is characterized by high process yield, high production capacity, ease of manufacture, high density and low manufacture cost.  
           [0014]    In order to achieve the objects of the present invention mentioned above, a laminated substrate structure is provided. The laminated substrate structure is composed of a plurality of dielectric layers and a plurality of circuit layers stacked with each other. A plurality of vias exists in the dielectric layer, and the circuit layers are electrically coupled to each other through the vias in the dielectric layer. The laminated substrate structure of the present invention is characterized by the circuit layer pattern between the dielectric layers being a landless design. The landless design circuit layer pattern can efficiently improve the circuit integration in the laminated substrate.  
           [0015]    The laminated substrate structure of the present invention further comprises at least a via opening layer arranged on the two most exterior dielectric layers. The via opening layer has a plurality of openings corresponding to two vias in the most exterior of the dielectric layers. Moreover, this most exterior dielectric layer or a solder mask layer may be applied or may not be applied to the via opening layer depending on the requirement.  
           [0016]    In order to achieve the objectives of the present invention mentioned above, a laminated substrate manufacture method is provided. There are two groups divided as forming of the dielectric layer having a patterned circuit and the dielectric layer having a via are performed first. After the forming of the dielectric layer having the patterned circuit and the dielectric layer having the via finishes, the alignment is performed onto them, and finally laminates them to form the laminated substrate. The dielectric layer having the patterned circuit and the dielectric layer having the via are laminated by using the method such as the vacuum thermal lamination. Moreover, after the alignment and lamination of the dielectric layer having the patterned circuit and the dielectric layer having the via, a curing step is performed to cure the dielectric material in the dielectric layer having the patterned circuit and the dielectric layer having the via.  
           [0017]    In order to achieve the objectives of the present invention mentioned above, a laminated substrate manufacture method is provided. The forming of the dielectric layer having a patterned circuit, the dielectric layer having a via, and the via opening layer optionally applied are performed first. After the forming of the dielectric layer having the patterned circuit, the dielectric layer having the via, and the via opening layer, the alignment is performed onto them, finally laminating them to form the laminated substrate. The dielectric layer having the patterned circuit and the dielectric layer having the via are laminated by using a method such as the vacuum thermal lamination. Moreover, after the alignment and lamination of the dielectric layer having the patterned circuit and the dielectric layer having the via, a curing step is performed to cure the dielectric material in the dielectric layer having the patterned circuit and the dielectric layer having the via, and form the electrical connection at appropriate via circuit position.  
           [0018]    The present invention provides a first supporter first, a patterned circuit is subsequently formed on the first supporter, and a first dielectric layer is formed on the first supporter finally to cover the patterned circuit. Therefore, a dielectric layer having the patterned circuit can be formed on the first supporter.  
           [0019]    The present invention provides a second supporter first, a plurality of via studs subsequently formed on the second supporter, and finally a second dielectric layer is formed on the second supporter, wherein the via studs extrude from the surface of the second dielectric layer. Therefore, a dielectric layer having via studs can be formed on the second supporter.  
           [0020]    The patterned circuit of the present invention is formed by using the method such as the metal etching, pattern plating, semi-additive, or full-additive. Moreover, the first dielectric layer and the second dielectric layer are formed by using film, or by the coating, spray coating, or agglutinate method.  
           [0021]    The opening in the via opening layer of the present invention is formed by using the mechanical drilling, laser drilling, or hole punch method. 
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0022]    The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention, and together with the description, serve to explain the principles of the invention. In the drawings,  
         [0023]    [0023]FIG. 1 schematically shows a sketch map of the contact position of the circuit layer and the via in the conventional laminated substrate structure, wherein the contact position has a via land;  
         [0024]    FIGS.  2 A- 2 D schematically shows a sectional sketch map of the manufacture process of a dielectric layer that has a patterned circuit in the laminated substrate of the first embodiment according to the present invention;  
         [0025]    FIGS.  3 A- 3 D schematically shows a sectional sketch map of the manufacture process of a dielectric layer that has a via in the laminated substrate of the first embodiment according to the present invention;  
         [0026]    [0026]FIG. 4A and FIG. 4B schematically show the sectional sketch maps of the manufacture process of the via opening layer in the laminated substrate of the first embodiment according to the present invention;  
         [0027]    [0027]FIG. 5A and FIG. 5B schematically show the sectional sketch maps of the lamination process performed onto the laminated substrate of the first embodiment according to the present invention;  
         [0028]    FIGS.  6 A- 6 D schematically shows a sectional sketch map of the manufacture process of a dielectric layer that has a patterned circuit in the laminated substrate of the second embodiment according to the present invention; and  
         [0029]    [0029]FIG. 7 schematically shows a sketch map of the contact position of the circuit layer and the via in the laminated substrate structure of the first embodiment and the second embodiment according to the present invention, wherein the contact position has a landless design. 
     
    
     DETAILED DESCRIPTION  
       [0030]    The First Embodiment  
         [0031]    FIGS.  2 A- 2 D schematically show a sectional sketch views of the manufacture process of the circuit parts that have a patterned circuit in the laminated substrate of the first embodiment according to the present invention. The patterned circuit in the laminated substrate of the present invention is formed by using a method such as metal etching, pattern plating, semi-additive, or full-additive. Metal etching is used in the present embodiment for description. Referring to FIG. 2A first, a supporter  202  is provided, and a conductive layer  204  is subsequently formed on the supporter  202 . The conductive layer  204  is made of material such as copper, and the conductive layer  204  is formed on the supporter  202  by using a method such as sputtering, lamination adherence or deposition.  
         [0032]    Referring to both FIG. 2B and FIG. 2C simultaneously, a patterned photoresist  206  is subsequently formed on the conductive layer  204 , the patterned photoresist  206  is used to define the pattern of the conductive layer  204  below it. The patterned photoresist  206  is formed on the conductive layer  204  through the steps of the photoresist coating, exposure, and developing. After the patterned photoresist  206  is formed, the patterned photoresist  206  is used as a mask to etch the conductive layer  204  below it, so that a portion of the conductive layer  204  that is not covered by the patterned photoresist  206  is removed to form the patterned circuit  204   a . Afterwards, the patterned photoresist  206  is stripped from the conductive layer  204  surface.  
         [0033]    Then, referring to FIG. 2D, after the patterned circuit  204   a  is formed, a dielectric layer  208  is subsequently formed on the supporter  202  covering the patterned circuit  204   a . The patterned circuit  204   a  and the dielectric layer  208  constitute a part  200  having embedded patterned circuits.  
         [0034]    FIGS.  3 A- 3 D schematically shows a sectional sketch map of the manufacture process of parts containing via and via pad in the laminated substrate of the first embodiment according to the present invention. Referring to FIG. 3A first, a supporter  302  is provided, and a conductive layer  304  is subsequently formed over the supporter  302 , which is peelable from the conductive metal and the dielectric regions. Wherein, the conductive layer  304  is made of a material such as copper, and the conductive layer  304  is formed over the supporter  302  by using a method such as sputtering, lamination adherence or deposition.  
         [0035]    Referring to both FIG. 3B and FIG. 3C simultaneously, a patterned photoresist  306  is subsequently formed on the conductive layer  304 , the patterned photoresist  306  is used to define the pattern of the conductive layer  304  below it. The patterned photoresist  306  is formed on the conductive layer  304  through the steps of the photoresist coating, exposure, and developing. After the patterned photoresist  306  is formed, the patterned photoresist  306  is used as a mask to etch the conductive layer  304  below it, so that a portion of the conductive layer  304  that is not covered by the patterned photoresist  306  is removed to form the via studs  304   a . Afterwards, the patterned photoresistor  306  is stripped from the conductive layer  304 .  
         [0036]    Referring to FIG. 3D, after the via stud  304   a  is formed, a dielectric layer  308  is subsequently formed on the supporter  302  to cover the via studs  304   a . The via studs  304   a  and the dielectric layer  308  constitute a part  300  having via studs. FIG. 3D shows that the dimension of the via studs  304   a  can vary depending on the process requirement.  
         [0037]    [0037]FIG. 4A and FIG. 4B schematically show the sectional sketch views of the manufacture process of the via opening layer in the laminated substrate of the first embodiment according to the present invention. Referring to both FIG. 4A and FIG. 4B simultaneously, a supporting layer  400  is provided first, and an opening  402  is formed in the supporting layer  400  to form a via opening layer  400   a . The opening  402  in the via opening layer  400   a  could be formed by using mechanical drilling, laser drilling, or hole punch method.  
         [0038]    [0038]FIG. 5A and FIG. 5B schematically show the sectional sketch views of the lamination process performed onto the laminated substrate of the first embodiment according to the present invention. Referring to both FIG. 5A and FIG. 5B simultaneously, first aligning a plurality of dielectric layers  200  having patterned circuits with a plurality of dielectric layers  300  having via studs and a plurality of via opening layer  400   a  as shown in FIG. 5A. After the alignment, the dielectric layers  200  having patterned circuits, dielectric layers  300  having via studs, and the via opening layer  400   a  are laminated together to complete the forming of the laminated substrate. The dielectric layers  200  having patterned circuits, the dielectric layer  300  having via studs, and the via opening layers  400   a  are laminated by using the vacuum thermal lamination method.  
         [0039]    Referring to FIG. 5A and FIG. 5B, in the manufacture process of the laminated substrate, the via opening layer  400   a  is an optional component. In other words, the present invention may align and laminate the plurality of parts  200  having patterned circuits with a plurality of parts  300  having via studs only. Therefore, the via opening layer  400   a  can be saved in the manufacture process of the laminated substrate, so that the whole process can be further simplified.  
         [0040]    The Second Embodiment  
         [0041]    The present embodiment is the same as the first embodiment in forming the dielectric layer having the via studs and the via opening layer. The difference between the present embodiment and the first embodiment is in the manufacture method of the dielectric layer having the patterned circuit.  
         [0042]    FIGS.  6 A- 6 D schematically shows sectional sketch views of the manufacture process of the dielectric layer that has a patterned circuit in the laminated substrate of the second embodiment according to the present invention. Referring to FIG. 6A first, a supporter  602  is provided, and a conductive layer  604  is subsequently formed on the supporter  602 . The conductive layer  604  is made of material such as copper, and the conductive layer  604  is formed on the supporter  602  by using a method such as sputtering, lamination adherence or deposition.  
         [0043]    Then, referring to both FIG. 6B and FIG. 6C simultaneously, a patterned photoresist  606  is subsequently formed on the conductive layer  604 , and the patterned photoresist  606  has a plurality of openings  607 . The patterned photoresist  606  is formed on the conductive layer  604  through the steps of the photoresist coating, exposure, and developing. After the patterned photoresist  606  is formed, the conductive layer  608  is filled into the opening  607  of the patterned photoresist  606 . Since the opening  607  has a specific pattern, the conductive layer  608  filled into the opening  607  is consistent with the specific pattern mentioned above. Afterwards, the patterned photoresist  606  is stripped from the conductive layer  604  to expose the conductive layer  604  below it.  
         [0044]    Referring to FIG. 6C and FIG. 6D, after the patterned photoresistor  606  is stripped from the conductive layer  604 , a non-optional step of micro etching is subsequently performed to remove the conductive layer  604 . In the process of removing the conductive layer  604 , a portion of the conductive layer  608  thickness is etched to form a patterned circuit  608   a . After the patterned circuit  608   a  is formed, a dielectric layer  610  is subsequently formed on the supporter  602  covering the patterned circuit  608   a . The patterned circuit  608   a  and the dielectric layer  610  constitute parts  600  having a patterned circuit.  
         [0045]    In the manufacture process of FIG. 6A to FIG. 6D mentioned above, a thin trace circuit can be formed in the laminated substrate. The fine trace circuit manufacture process (FIG. 6A to FIG. 6D) efficiently improves the circuit density in the laminated substrate, and is also helpful to the layout flexibility of the circuit layer in the laminated substrate.  
         [0046]    [0046]FIG. 7 schematically shows a sketch view of the contact position of the circuit layer and the via in the laminated substrate structure of the first embodiment and the second embodiment according to the present invention, wherein the contact position has a landless design. Referring to FIG. 7, the circuit  700   a  is isolated from the circuit  700   b  by a dielectric layer (not shown), and the circuit  700   a  is electrically coupled to the circuit  700   b  by a via hole  702 .  
         [0047]    Referring to both FIG. 1 and FIG. 7 simultaneously, in the present embodiment, the circuit  700   a  and circuit  700   b  are electrically coupled to the via stud  702  directly without the help of the conventional via land  102   a  and  102   b  (as shown in FIG. 1). Therefore, the layout space of the circuit layer in the present embodiment is not reduced by the limitation of the via land  102   a  and  102   b.    
         [0048]    In summary, the laminated substrate structure of the present invention and the manufacture method thereof at least has the following advantages:  
         [0049]    1. In the laminated substrate structure of the present invention, the contact position of the circuit layer and the via adopts a landless design, so that the circuit integration in the laminated substrate is significantly improved.  
         [0050]    2. In the laminated substrate structure of the present invention, the via stud adopts a solid via design to give it good electrical performance and good thermal performance.  
         [0051]    3. In the laminated substrate structure of the present invention, the laminated substrate is formed by using the methods of pattern process and simutaneous lamination, so that the manufacture time can be efficiently reduced, and the productivity is further improved.  
         [0052]    4. In the laminated substrate structure of the present invention, the laminated substrate is formed by using the method of pattern process and synchronous lamination, so that the conventional investment in other equipment can be saved.  
         [0053]    5. In the laminated substrate structure of the present invention, before each layer (the dielectric layer having the patterned circuit, the dielectric layer having the via stud, and the via opening layer) is laminated, the confirmation of acceptable quality can be made onto each layer respectively, so that the yield of the laminated substrate can be easily controlled and the manufacture cost can be efficiently reduced.  
         [0054]    Although the invention has been described with reference to a particular embodiment thereof, it will be apparent to one of the ordinary skill in the art that modifications to the described embodiment may be made without departing from the spirit of the invention. Accordingly, the scope of the invention will be defined by the attached claims not by the above detailed description.