Abstract:
A CMP method for performing a chemical mechanical polishing process wherein an edge of a wafer formed with a conductive layer is uniformly polished is provided. The CMP method includes preparing a wafer, forming a chip pattern in effective dies of the wafer and ineffective dies on edges of the wafer, depositing an insulating layer on the wafer, forming a trench and via hole in a portion of the insulating layer deposited on the effective die, forming a conductive layer on the wafer, and performing a CMP process on the wafer until a portion of the conductive layer formed on the ineffective die is removed.

Description:
RELATED APPLICATION  
       [0001]     This application is based upon and claims the benefit of priority to Korean Application No. 10-2005-0133179, filed on Dec. 29, 2005, the entire contents of which are incorporated herein by reference.  
       BACKGROUND  
       [0002]     1. Technical Field  
         [0003]     The present invention relates to a CMP (Chemical Mechanical Polishing) method, and more particularly to a CMP method wherein an edge of a wafer formed with a conductive layer can be uniformly polished.  
         [0004]     2. Description of the Related Art  
         [0005]     As semiconductor devices become more highly integrated, a technology for planarizing a lower semiconductor structure in order to secure a margin in a photo process and to minimize the length of an interconnection is required.  
         [0006]     Conventional methods for planarizing a lower semiconductor structure includes BPSG (borophosphosilicate glass) reflow, aluminum reflow, spin on glass (SOG), etch-back, CMP (Chemical Mechanical Polishing) processes and the like.  
         [0007]     Among these processes, the CMP process is a process capable of effectively planarizing wafers, in which slurry is inserted between a wafer and a polishing pad such that the wafer is polished. Since the method can accomplish global planarization in a broad space and at low-temperatures, which cannot be accomplished through a reflow or etch-back process, the method has been spotlighted as a leading planarization technology for next-generation devices.  
         [0008]     The CMP process is used in a case where, after etching a trench, an insulating layer is filled in the trench and planarization is then accomplished in a trench device isolation method rather than a device isolation method through existing thermal oxidation; in a damascene process in which, when forming lines and spaces, a reverse pattern is formed, a conductive material is filled in the lines and spaces, and planarization and line isolation are then accomplished; or in a process of planarizing an interlayer dielectric layer. Accordingly, the CMP process can accomplish planarization while reducing thermal budget.  
         [0009]     In order to use an insulating layer as a polishing stop layer, a polishing compound used in a CMP process for a metal layer is generally prepared to have a high polishing speed for a metallic material and to have a low polishing speed for an insulating layer.  
         [0010]      FIG. 1  is a view showing a conventional wafer.  
         [0011]     As shown in  FIG. 1 , the conventional wafer has a plurality of pattern areas  11   a  in each of which a pattern is formed and a plurality of non-pattern area  11   b  in each of which a pattern is not formed.  
         [0012]     Here, each of pattern areas  11   a  corresponds to an area adjacent to non-pattern area  11   b  among effective dies, and each of non-pattern areas  11   b  corresponds to an ineffective die corresponding to an edge of a wafer. The effective die is a die on which a desired chip pattern is formed by a user, and the ineffective die is a die on which a chip pattern is not formed.  
         [0013]     Meanwhile, a plurality of metal patterns and an insulating layer for insulating between metal patterns are formed in each of the pattern areas  11   a,  and insulating layer is formed in each of non-pattern areas  11   b.    
         [0014]     At this time, the metal patterns are not formed in each of non-pattern areas  11   b  because non-pattern areas  11   b  are ineffective dies. Since an insulating layer which is not required for a photolithography process is formed on the entire surface of the wafer, the insulating layer is also formed in non-pattern areas  11   b  except the pattern areas  11   a.    
         [0015]     However, since devices are not formed on non-pattern areas  11   b , the aforementioned metal patterns are not formed in each of non-pattern areas  11   b.    
         [0016]     Accordingly, since the thickness of an insulating layer formed in pattern areas  11   a  is different from that of the insulating layer formed in non-pattern areas  11   b , a step difference occurs.  
         [0017]     Copper is typically used as a material of the metal pattern due to demands for a faster response speed of devices and is typically formed using a dual damascene technique. Accordingly, interconnections are formed after the CMP process. At this time, since copper is not removed sufficiently in the CMP process due to the aforementioned step difference between pattern and non-pattern areas  11   a  and  11   b , the copper remains on the insulating layer, resulting in an electric leakage of the interconnections.  
         [0018]     This will be described below in more detailed manner.  
         [0019]      FIGS. 2   a  and  2   b  are sectional views taken along line I-I in  FIG. 1 .  
         [0020]     First, a wafer  11  having pattern and non-pattern areas  11   a  and  11   b  are prepared, and a transistor is formed in each of pattern areas  11   a  of wafer  11 . Further, an insulating layer  51  is formed on the entire surface of wafer  11 .  
         [0021]     Then, a trench and a via hole, which have a dual damascene structure, are formed in the insulating layer  51 , and an anti-diffusion layer  52 , a copper seed layer  53  and a copper metal layer  54  are sequentially formed on the entire surface of wafer  11  including the trench and via hole.  
         [0022]     At this time, since a transistor is formed in pattern area  11   a  and a transistor is not formed in the non-pattern area  11   b , insulating layer  51  formed on the entire surface of wafer  11  has a different thickness in each of the areas.  
         [0023]     That is, the thickness of insulating layer  51  in the pattern area  11   a  is thicker than that of insulating layer  51  in non-pattern area  11   b.    
         [0024]     Then, if copper metal layer  54  is polished using a CMP process, a copper interconnection layer  55  is formed in the trench and via hole as shown in  FIG. 2   b . At this time, a copper metal layer  56  is not completely removed and remains in non-pattern area  11   b  due to the step difference of insulating layer  51 .  
         [0025]     The remaining copper metal layer  56  (a copper residue) may penetrate through a rear surface of the pattern area  11   a  or wafer  11  in following processes such that copper metal layer  56  causes an electric leakage of interconnections.  
       BRIEF SUMMARY  
       [0026]     The present invention addresses the above problem occurring in the prior art, and provides a CMP method wherein the same pattern is formed in pattern and non-pattern areas, thereby minimizing a step difference of an insulating layer, so that copper residues can be removed.  
         [0027]     Consistent with the present invention, there is provided a method for performing a CMP (Chemical Mechanical Polishing) process, comprising: preparing a wafer; dividing the wafer into pattern areas serving as effective dies and non-pattern areas serving as ineffective dies; forming a transistor in the pattern and non-pattern areas; forming an insulating layer on the wafer; forming a trench and a via hole at a portion of the insulating layer positioned in the pattern areas; forming an anti-diffusion layer on the wafer; forming a conductive layer on the semiconductor wafer; and planarizing the conductive layer by using a CMP process.  
         [0028]     The non-pattern area may be an edge area of the semiconductor wafer, and the pattern area may be an effective die adjacent to the non-pattern area.  
         [0029]     The CMP process is performed until the conductive layer on the non-pattern area is removed.  
         [0030]     Further consistent with the present invention, there is provided a method for performing a CMP method on a wafer, which includes: preparing a wafer; forming a chip pattern in effective dies of the wafer and ineffective dies on edges of the wafer; depositing an insulating layer on the wafer; forming a trench and via hole in a portion of the insulating layer deposited on the effective die; forming a conductive layer on the wafer; and performing a CMP process on the wafer until a portion of the conductive layer formed on the ineffective die is removed. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0031]      FIG. 1  is a view showing a conventional wafer;  
         [0032]      FIGS. 2   a  and  2   b  are sectional views taken along line I-I in  FIG. 1 ;  
         [0033]      FIG. 3  is a view showing a wafer consistent with the present invention;  
         [0034]      FIGS. 4   a  to  4   g  are sectional views illustrating a CMP method consistent with the present invention; and  
         [0035]      FIGS. 5   a  and  5   b  are sectional views illustrating a method of forming a copper interconnection on the wafer shown in  FIG. 4   g.   
     
    
     DETAILED DESCRIPTION  
       [0036]     Hereinafter, a CMP method according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings.  
         [0037]      FIG. 3  is a view showing a wafer consistent with the present invention. As shown in this figure, the same pattern is formed in both pattern and non-pattern areas  110   a  and  110   b  of a wafer  110 . Here, each of pattern areas  110   a  corresponds to an area adjacent to non-pattern area  110   b  among effective dies, and each of non-pattern areas  110   b  corresponds to an ineffective die corresponding to an edge of wafer  110 . The effective die is a die on which a desired chip pattern is formed by a user, and the ineffective die is a die on which a chip pattern is not formed. Here, the chip pattern may be a transistor that is a semiconductor device, or the like.  
         [0038]     At this time, it is possible to form the pattern in non-pattern area  110   b  adjacent to pattern area  110   a  or to form the pattern in all the respective non-pattern areas  110   b.  Here, the pattern may be a transistor. This will be described below in detail.  
         [0039]      FIGS. 4   a  to  4   g  are sectional views illustrating a CMP method consistent with the present invention.  
         [0040]     Referring to  FIG. 4   a , a pad oxide layer  112  and a pad nitride layer  114  are sequentially formed on the entire surface of a semiconductor wafer  110  for forming an isolation region in the following process.  
         [0041]     Referring to  FIG. 4   b , a photoresist is deposited on the entire surface of the semiconductor wafer  110  having pad oxide layer  112  and pad nitride layer  114 , and an exposure process using a photomask is then performed, thereby forming a photoresist pattern  116 . Subsequently, an STI (Shallow Trench Isolation) process is performed by using photoresist pattern  116  as an ISO mask, thereby forming isolation layers  118 . At this time, semiconductor wafer  110  is divided into an active area and a non-active area (i.e., an isolation layer area) by isolation layer  118 .  
         [0042]     Referring to  FIG. 4   c,  after removing photoresist pattern  116  by performing a stripping process, a predetermined washing process is performed, thereby sequentially removing pad nitride layer  114  and pad oxide layer  112 . Subsequently, a well ion implantation process is performed by using a mask for well ion implantation, thereby forming a well area  120  in semiconductor wafer  110 .  
         [0043]     Referring to  FIG. 4   d,  a thermal oxidation or rapid heat treatment process is performed on the entire surface of semiconductor wafer  110 , thereby forming a gate oxide layer  122 .  
         [0044]     Subsequently, a poly-silicon layer  124  for gate electrodes is formed on the entire surface of semiconductor wafer  110  formed with the gate oxide layer  122 .  
         [0045]     Referring to  FIG. 4   e,  a photolithography process is performed by using a mask for a gate electrode pattern such that poly-silicon layer  124  and gate oxide layer  122  are sequentially etched, thereby forming a gate electrode  126 . Subsequently, a low-density ion implantation process for forming a shallow junction area is performed in the active area of semiconductor wafer  110 , thereby forming a low-density junction area (P− or N−)  128 .  
         [0046]     Referring to  FIG. 4   f,  predetermined deposition and etching processes are sequentially performed, thereby forming spacers  130  for LDD (Lightly Doped Drain) HLD (High temperature Low pressure Dielectric) on both sidewalls of gate electrode  126 . Subsequently, a high-density ion implantation process is performed, thereby forming a high-density junction area (P+ or N+)  132 . Accordingly, gate electrode  126  is doped with predetermined ions through a low-density ion implantation process. Further, source/drain areas  134  each having low-density and high-density junction areas  128  and  132  are formed.  
         [0047]     Meanwhile, if an edge of isolation layer  118  is etched in a process of forming spacer  130 , the thickness of isolation layer  118  at an edge portion is reduced. Therefore, there occurs a step difference between isolation layer  118  and source/drain area  134 . At this time, source/drain area  134  is exposed at a boundary between source/drain area  134  and isolation layer  118  due to step difference.  
         [0048]     Referring to  FIG. 4   g,  a salicide (self align silicide)  136  is formed on high-density junction area  132  and gate electrode  126 .  
         [0049]     As such, a transistor is formed in each of pattern and non-pattern areas  110   a  and  110   b.    
         [0050]     Next, a method of forming copper interconnections on semiconductor wafer  110  formed with such transistors will be described below.  
         [0051]      FIGS. 5   a  and  5   b  are sectional views illustrating a method of forming a copper interconnection on wafer  110  shown in  FIG. 4   g,  and  FIGS. 5   a  and  5   b  illustrate sectional views taken along line II-II in  FIG. 3 .  
         [0052]     First, as shown in  FIG. 5   a , an insulating layer  501  is formed on the entire surface of semiconductor wafer  110 .  
         [0053]     At this time, since transistors have been formed in both pattern and non-pattern areas  110   a  and  110   b  as described above, the thickness of insulating layer  501  in pattern area  110   a  is identical to that of insulating layer  501  in non-pattern area  110   b.    
         [0054]     Then, insulating layer  501  of pattern area  110   a  is patterned, thereby forming a trench and a via hole. Subsequently, an anti-diffusion layer  502  and a conductive layer are formed on the entire surface of semiconductor wafer  110  including the trench and the via hole. Here, the conductive layer includes a copper seed layer  503  and a copper metal layer  504 .  
         [0055]     Then, if anti-diffusion layer  502 , copper seed layer  503  and copper metal layer  504  are polished through a CMP process until a surface of the insulating layer  501  is exposed, a copper interconnection layer  505  is formed in the trench and the via hole as shown in  FIG. 5   b.    
         [0056]     At this time, since insulating layers  501  of both pattern and non-pattern areas  110   a  and  110   b  have the same thickness, copper metal layer  504  on insulating layer  501  is completely removed.  
         [0057]     That is, according to the CMP method of the present invention, copper residues are not produced.  
         [0058]     Meanwhile, the trench and the via hole and the copper interconnection layer, which are formed in pattern area  110   a , may also be formed in non-pattern area  110   b.    
         [0059]     As described above, the same pattern is formed in pattern and non-pattern areas so that there can be reduced a step difference between insulating layers formed in the pattern and non-pattern areas.  
         [0060]     That is, consistent with the present invention, a predetermined dummy pattern is formed even in a non-pattern area that is an edge of a wafer, and an exposure process is then performed.  
         [0061]     Accordingly, an insulating layer deposited on the entire surface of the wafer after forming the dummy pattern can be uniformly deposited on the wafer. Thus, it is less likely that there occur a step difference between a non-pattern area and a pattern area adjacent thereto.  
         [0062]     Therefore, copper residues can be prevented from being produced in a CMP process.  
         [0063]     The present invention may remove a step difference between a non-pattern area corresponding to an edge of a wafer and a pattern area adjacent thereto. Accordingly, a conductive layer can be prevented from remaining in a non-pattern area in a case where a CMP process is performed.  
         [0064]     It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention. Thus, it is intended that the present invention covers the modifications and variations thereof within the scope of the appended claims.