Abstract:
A charge pump circuit includes feedback level shifters for providing threshold voltage cancellation and feedforward level shifters for providing boosted clocking signals to generate a high pumped output voltage from a low supply voltage. The charge pump circuit includes plurality of switching circuits each including first and second signal terminals and a control terminal adapted to receive a control signal. Each switching circuit couples its first signal terminal to its second signal terminal responsive to the control signal. The signal terminals of the plurality of switching circuits are connected in series between an input voltage node and an output voltage node. A plurality of energy storage circuits each have a first terminal coupled to a respective voltage node formed by the interconnection between adjacent switching circuits and a second terminal adapted to receive a clocking signal. At least one feedback level shifting circuit is coupled between a selected one of the voltage nodes and the control terminal of a switching circuit between the selected voltage node the input node, each feedback level shifting circuit applying the voltage on the voltage node to the control terminal responsive to a clock signal. At least one feedforward level shifting circuit is coupled between a selected one of the voltage nodes and the second terminal of one of the energy storage circuits coupled to a voltage node between the selected voltage node and the output node. Each feedforward level shifting circuit applies the voltage on the voltage node to the second terminal responsive to a clock signal.

Description:
This application is a Divisional application of 09/259,234 filed on Mar. 1, 1999, now U.S. Pat. No. 6,160,723. 
    
    
     TECHNICAL FIELD 
     The present invention relates to voltage generating circuits, and, more particularly, to a method and circuit for regulating a charge pump circuit to minimize the ripple and the power consumption of the charge pump circuit. 
     BACKGROUND OF THE INVENTION 
     In many electronic circuits, charge pump circuits are utilized to generate a positive pumped voltage having an amplitude greater than that of a positive supply voltage, or to generate a negative pumped voltage from the positive supply voltage, as understood by those skilled in the art. For example, in a conventional dynamic random access memory (“DRAM”), a charge pump circuit may be utilized to generate a boosted word line voltage V CCP  having an amplitude greater than the amplitude of a positive supply voltage V CC , and a negative voltage pump circuit may be utilized to generate a negative substrate or back-bias voltage V bb  that is applied to the bodies of NMOS transistors in the DRAM. Another typical application of a charge pump circuit is the generation of a high voltage utilized to erase data stored in blocks of memory cells or to program data into memory cells in non-volatile electrically block-erasable or “FLASH” memories, as will be understood by those skilled in the art. 
     FIG. 1 is a schematic of a conventional two-stage charge pump circuit  100  that generates a pumped output voltage V P  having an amplitude greater than the amplitude of a supply voltage source V CC  in response to complementary clock signals CLK and {overscore (CLK)}, as will be described in more detail below. The charge pump circuit  100  includes two voltage-boosting stages  102  and  104  connected in series between an input voltage node  106  and an output voltage node  108 . The voltage-boosting stage  102  includes a capacitor  110  receiving the clock signal CLK on a first terminal and having a second terminal coupled to the input node  106 . A diode-coupled transistor  112  is coupled between the input voltage node  106  and a voltage node  114 , and operates as a unidirectional switch to transfer charge stored on the capacitor  110  to a capacitor  116  in the second voltage-boosting stage  104 . The capacitor  116  is clocked by the complementary clock signal {overscore (CLK)}. A transistor  118  transfers charge stored on the capacitor  116  to a load capacitor C L  when the transistor  118  is activated. A threshold voltage cancellation circuit  122  generates a boosted gate signal V BG  responsive to the CLK and {overscore (CLK)} signals, and applies the signal V BG  to control activation of the transistor  118 . When the CLK and {overscore (CLK)} signals are high and low, respectively, the circuit  122  drives the signal V BG  low to turn OFF the transistor  118 , and when the CLK and {overscore (CLK)} signals are low and high, respectively, the circuit  122  drives the signal V BG  high to turn ON the transistor  118 . The cancellation circuit  122  may be formed from conventional circuitry that is understood by those skilled in the art. The charge pump circuit  100  further includes a diode-coupled transistor  120  coupled between the supply voltage source V CC  and node  106 . The diode-coupled transistor  120  operates as a unidirectional switch to transfer charge from the supply voltage source V CC  to the capacitor  110 . 
     A ring oscillator  124  generates an oscillator clock signal OCLK that is applied to a switching circuit  126  coupled between the ring oscillator  124  and a clocking-latching circuit  128 . The switching circuit  126  receives a regulation output signal REGOUT from external control circuitry (not shown in FIG.  1 ), and when the REGOUT signal is inactive low, the switching circuit  126  presents a low impedance and thereby applies the OCLK signal to the clocking-latching circuit  128 . When the REGOUT signal is active high, the switching circuit  126  presents a high impedance, which isolates or removes the OCLK signal from the clocking-latching circuit  128 . The clocking-latching circuit  128  latches the applied OCLK signal and generates the complementary clock signals CLK and {overscore (CLK)} responsive to the latched OCLK signal. The CLK and {overscore (CLK)} signals have the same frequency as the OCLK signal, and are complementary signals so there is a phase shift of 180° between these signals. 
     The operation of the conventional charge pump circuit  100  will now be described in more detail with reference to the timing diagram of FIG. 2, which illustrates the voltages at various points in the charge pump circuit  100  during operation. In operation, the charge pump circuit  100  operates in two modes, a normal mode and a power-savings mode. During both the normal and power-savings modes of operation, the ring oscillator  124  continuously generates the OCLK signal. The charge pump circuit  100  operates in the normal mode when the pumped output voltage V P  is less than a desired pumped output voltage V PD . When V P &lt;V PD , the external control circuitry drives the REGOUT signal inactive low causing the switching circuit  126  to apply the OCLK signal to the clocking-latching circuit  128 . In response to the applied OCLK signal, the clocking-latching circuit  128  latches the OCLK and clocks the stages  102  and  104  with the CLK and {overscore (CLK)} signals generated in response to the latched OCLK signal. 
     At just before a time t 0 , the CLK signal is low having a voltage of approximately 0 volts and the {overscore (CLK)} signal is high having a voltage of approximately the supply voltage V CC , and each of the voltages on the nodes  106 ,  114 , and  108  and the have assumed values as shown for the sake of example. Also, before the time t 0  the REGOUT signal is inactive low and the circuit  122  drives the boosted gate signal V BG  high responsive to the CLK and {overscore (CLK)} signals being low and high, respectively. When the CLK signal is low, the terminal of the capacitor  110  is accordingly at approximately ground and the voltage at the node  106  is sufficiently low to turn ON the diode-coupled transistor  120 , transferring charge from the supply voltage source VCC through the transistor  120  to charge the capacitor  110 . As shown in FIG. 2, the voltage at the node  106  (i.e., the voltage across the capacitor  110 ) is increasing just before the time to as the capacitor  110  is being charged. Also just before the time t 0 , the voltage at the node  114  equals the high voltage of the {overscore (CLK)} signal plus the voltage stored across the capacitor  116  (V 116 ). This bootstrapped voltage on the node  114  is sufficiently greater than the voltage V P  on the output voltage node  108  to turn ON the transistor  118 , transferring charge from the capacitor  116  through the transistor  118  to the load capacitor C L . As shown, the voltage at node  114  is decreasing and the voltage V P  increasing just before the time t 0  as charge is being transferred through the transistor  118 . 
     At the time t 0 , the CLK signal goes high, driving the voltage on the node  106  to the high voltage (V CC ) of the CLK signal plus the voltage stored across the capacitor  110  (V 110 ). At this point, the voltage on the node  106  is sufficiently high to turn OFF the transistor  120 , isolating the node  106  from the supply voltage source V CC . Also at the time t 0 , the {overscore (CLK)} signal goes low (to ground), causing the voltage on the node  114  to equal the voltage V 116  stored across the capacitor  116 . The voltage on the node  106  is now sufficiently greater than the voltage on the node  114  to turn ON the transistor  112 , transferring charge from the capacitor  110  through the transistor  112  to the capacitor  116 . As shown in FIG. 2, between the time t 0  and a time t 1 , which corresponds to the interval the CLK signal is high and {overscore (CLK)} signal is low, the voltage at the node  106  decreases and the voltage at the node  114  increases as charge is pumped or transferred through the transistor  112 . It should be noted that during this time, the transistor  118  is turned OFF because the voltage V P  is sufficiently greater than the voltage at the node  114  during normal operation of the charge pump circuit  100 . 
     At the time t 1 , the CLK and {overscore (CLK)} signals go low and high, respectively, and the charge pump circuit  100  operates in the same manner as previously described for just before the time t 0 . In other words, the transistor  112  turns OFF and transistors  118  and  120  turn ON, and charge is transferred from the supply voltage source V CC  through the transistor  120  to the capacitor  110  and charge is transferred from the capacitor  116  through the transistor  118  to the load capacitor C L . As seen in FIG. 2, from the time t 1  to a time t 2  the voltage at the node  106  increases as the capacitor  110  is charging and the voltages on nodes  114  and  108  decrease and increase, respectively, as charge is transferred from the capacitor  116  to the load capacitor C L . At the time t 2 , the CLK and {overscore (CLK)} signals again go high and low, respectively, and the charge pump circuit  100  operates as previously described at the time t 0 . 
     The charge pump circuit  100  continues operating in this manner during the normal mode, pumping charge from the supply voltage source V CC  to the successive capacitors  110 ,  116 , and C L  to develop the desired pumped voltage V PD  across the capacitor C L . When the pumped output voltage V P  becomes greater than the desired voltage V PD , the charge pump circuit  100  commences operation in the power-savings mode of operation, which occurs at a time t 3  in FIG.  2 . In response to the pumped output voltage V P  becoming greater than the desired voltage V PD , the external control circuit drives the REGOUT signal active high, causing the switching circuit  126  to present a high impedance so that the OCLK signal no longer clocks the clocking-latching circuit  128  which, in turn, no longer clocks the voltage-boosting stages  102  and  104 . As a result, the CLK and {overscore (CLK)} signals remain in their previous latched states until the pumped output voltage V P  is less than V PD . This is seen in the example of FIG. 2 at a time t 4  when, although the OCLK signal goes high, the CLK and {overscore (CLK)} signals remain low and high, respectively, since OCLK signal is not applied to the clocking-latching circuit  128 . 
     Once the pumped output voltage V P  becomes less than V PD , the control circuit drives the REGOUT signal inactive low and the charge pump circuit  100  again commences operation in the normal mode. As will be understood by those skilled in the art, the switching circuit  126  enables the charge pump circuit  100  to very quickly switch into the normal mode of operation since the ring oscillator  124  continually generates the OCLK signal. In other words, since the ring oscillator  124  continuously generates the OCLK signal, transition from the power-savings to normal mode is delayed only by the switching time of the circuit  126 , which is very fast. In contrast, if the ring oscillator  124  was turned ON and OFF responsive to the REGOUT signal, the settling time (i.e., the time for the CLK, {overscore (CLK)} signals to stabilize) of the oscillator when turned back ON is much greater than the switching time of the circuit  126 . As a result, in this situation the voltage V P  could continue to decrease during this settling time, thereby increasing the ripple of the voltage V P . 
     The power-savings mode of operation reduces the overall power consumption of the circuit  100  since the CLK and {overscore (CLK)} signals do not clock the stages  102  and  104  when the voltage V P  is greater than the desired voltage V PD . Although the overall power consumption of the circuit  100  is reduced and the switching circuit  126  alleviates some of the ripple introduced by switching between modes, operation in the power-savings mode introduces additional ripple of the pumped output voltage V P  due to the transistor  118  in the final voltage-boosting stage  104  remaining turned ON during this mode of operation. More specifically, when the charge pump circuit  100  enters the power savings mode of operation the CLK and {overscore (CLK)} signals have one of two states. If the CLK and {overscore (CLK)} signals are high and low, respectively, when the REGOUT signal goes active to enter the power-savings mode, then the boosted gate signal V BG  remains low during this mode and the transistor  118  is turned OFF. In this situation, the turned OFF transistor  118  isolates the output node  108  and the voltage V P  is not affected by the voltage on the node  114 . 
     In contrast, if the CLK and {overscore (CLK)} signals are low and high, respectively, when the REGOUT signal goes active, the transistor  118  may remain turned ON during the power-savings mode thereby coupling the output node  108  to the node  114 . As a result, the voltage on the node  114  affects the pumped output voltage V P  in this situation. For example, as illustrated in FIG. 2, it is seen that when the REGOUT signal goes high at the time t 3  the CLK and {overscore (CLK)} signals are low and high, respectively, so the signal V BG  is high turning ON the transistor  118 . As seen after the time t 3 , the pumped output voltage V P  continues to increase as charge is transferred from the capacitor  116  through the transistor  118  to the load capacitor C L . Thus, the pumped voltage V P  undesirably increases after time t 3  even though it is already greater than the desired voltage V PD , thereby increasing the ripple of the pumped output voltage. 
     There is a need for a charge pump circuit having a low power consumption and a reduced ripple of the generated pumped output voltage. 
     SUMMARY OF THE INVENTION 
     According to one aspect of the present invention, a charge pump circuit includes a plurality of charge pump stages coupled in series, each including an input terminal, an output terminal, a clock terminal, a capacitor, and a switch. The capacitor of each charge pump stage is coupled between the clock terminal and the input terminal, and the switch of each charge pump stage is coupled between the input terminal and the output terminal. The input terminal of a first charge pump stage in the series is coupled to a voltage source and the output terminal of a last charge pump stage in the series is coupled to a pumped voltage output terminal. The switches of all charge pump stages but the last charge pump stage are selectively closed to allow current to flow in a first direction and selectively opened to prevent current flow in a second direction that is opposite the first direction. The switch of the last charge pump stage has a control input that is coupled to a control terminal. A clocking circuit applies first and second complementary digital signals to the clock terminals of the respective charge pump stages with the charge pump stages that receive the first digital signal alternating with the charge pump stages that receive the second digital signal. A control circuit applies a control signal to the control terminal to allow current to flow in the first direction when the absolute value of a pumped voltage at the pumped voltage output terminal has a magnitude that is less than a predetermined value and to prevent current from flowing in the first direction when the absolute value of the pumped voltage at the pumped voltage output terminal has a magnitude that is greater than the predetermined value. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic of a conventional charge pump circuit. 
     FIG. 2 is a signal diagram illustrating the operation of the charge pump circuit of FIG.  1 . 
     FIG. 3 is a schematic illustrating a charge pump circuit according to one embodiment of the present invention. 
     FIG. 4 is a functional block diagram of a memory device including the charge pump circuit of FIG.  3 . 
     FIG. 5 is a functional block diagram of a computer system including the memory device of FIG.  4 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 3 is a schematic of a charge pump circuit  300  including an isolation circuit  302  according to one embodiment of the present invention. The charge pump circuit  300  includes two voltage-boosting stages  304  and  306  connected in series between an input node  308  and an output node  310 . In operation, the isolation circuit  302  operates during a power-savings mode to turn OFF the final voltage-boosting stage  306  when a pumped output voltage V P  on the node  310  exceeds a desired value. By turning OFF the final voltage-boosting stage  306 , the isolation circuit  302  isolates the output node  310  so that the final voltage-boosting stage  306  does not increase the ripple of the pumped output voltage V P  during the power-savings mode, as will be explained in more detail below. 
     In the charge pump circuit  300 , the voltage-boosting stage  304  includes a capacitor  312  receiving a clock signal CLK on a first terminal and having a second terminal coupled to the input node  308 . An NMOS diode-coupled transistor  314  is coupled between the input node  308  and a voltage node  316 , and operates as a unidirectional switch to transfer charge stored on the capacitor  312  to a capacitor  318  in the final voltage-boosting stage  306 . The capacitor  318  receives a complementary clock signal {overscore (CLK)}, and charge stored on the capacitor  318  is transferred through an NMOS transistor  320  to a load capacitor C L  when the transistor  320  is activated. A threshold voltage cancellation circuit  322  generates a boosted gate signal V BG  responsive to the CLK and {overscore (CLK)} signals, and applies the signal V BG  to control activation of the transistor  320 . When the CLK and {overscore (CLK)} signals are high and low, respectively, the cancellation circuit  322  drives the signal V BG  low turning OFF the transistor  320 , and when the CLK and {overscore (CLK)} signals are low and high, respectively, the circuit  322  drives the signal V BG  high turning ON the transistor  320 . The charge pump circuit  300  further includes a diode-coupled transistor  324  coupled between a supply voltage source V CC  and the input node  308 . The diode-coupled transistor  324  operates as a unidirectional switch, transferring charge from the supply voltage source V CC  to the capacitor  312 . Transistors  324  and  314  are not necessarily in diode-coupled configuration. The gate voltage of these transistors can be generated from other threshold voltage cancellation circuit. 
     A ring oscillator  326  generates an oscillator clock signal OCLK that is applied to a switching circuit  328  coupled between the ring oscillator  326  and a clocking-latching circuit  330 . The switching circuit  328  receives a regulation output signal REGOUT from a feedback control circuit  332 . The ring oscillator  326 , switching circuit  328 , and clocking-latching circuit  330  operate identically to the corresponding components previously described with reference to FIG. 1, and thus, for the sake of brevity, their operation will not again be described in detail. Moreover, one skilled in the art will understand circuitry that performs the required functions of the ring oscillator  326  and circuits  328  and  330 . For example, the switching circuit  328  may be a conventional transmission gate, the clocking-latching circuit  330  may include a conventional RS flip-flop circuit and buffer circuitry, and the ring oscillator  326  may be formed from a plurality of inverters connected in series with the output from the last inverter being applied to the input of the first inverter, as will be understood by those skilled in the art. 
     The feedback control circuit  332  generates the REGOUT signal in response to the pumped output voltage V P  generated on the output node  310 . When the voltage V P  is greater than a desired value, the feedback control circuit  332  drives the REGOUT signal active high, causing the switching circuit  328  to isolate the OCLK signal from the clocking-latching circuit  330 . In contrast, when the pumped output voltage V P  is less than the desired value, the feedback control circuit  332  drives the REGOUT signal inactive low, causing the switching circuit  328  to apply the OCLK signal to the clocking-latching circuit  330 . In the embodiment of FIG. 3, the feedback control circuit  332  includes a ratio circuit  334  that generates a ratio voltage V RP  having a value that is equal to the actual pumped output voltage V P  times a gain M. The gain M of the ratio circuit  334  is defined by the value of a reference voltage V R  divided by the desired value of the pumped output voltage on the node  310 , which is designated V PD . The gain M of the ratio circuit  334  functions to scale the pumped output voltage V P  such that when the pumped output voltage has the desired value V PD , the ratio voltage V RP  equals the reference voltage V R . One skilled in the art will understand circuitry that can be used to form the ratio circuit  334 , such as two resisters connected in a voltage divider with a capacitor in parallel with each resistor. 
     A comparator  336  then compares the ratio voltage V RP  from the ratio circuit  334  to the reference voltage V R  and generates an output in response to this comparison. During operation of the charge pump circuit  300 , the actual pumped output voltage V P  typically has a value that is either less than or greater than the desired pumped output voltage V PD . As a result, the ratio voltage V RP  will be either less than or greater than the reference voltage V R . The ratio voltage V RP  is greater than the reference voltage when the pumped voltage V P  is greater than the desired voltage V PD , causing the comparator  336  to drive its output active high. In contrast, when the ratio voltage V RP  is less than the reference voltage V R , indicating the pumped voltage V P  is less than the desired voltage V PD , the comparator  336  drives its output inactive low. The output of the comparator  336  is applied through an amplifier  338  to a buffer  340  that generates the REGOUT signal responsive to the amplified output from the amplifier  338 . When the output from the comparator  336  is active high, the buffer  340  receives this amplified output from the amplifier  338  and drives the REGOUT signal active high. If the output from the comparator  336  is inactive low, the buffer  340  receives this amplified output from the amplifier  338  and drives the REGOUT signal inactive low. 
     In the charge pump circuit  300 , the REGOUT signal from the feedback control circuit  332  is further applied to the isolation circuit  302 . The isolation circuit  302  is coupled to the gate of the transistor  320  in the final voltage-boosting stage  306 . When the REGOUT signal is inactive low, the isolation circuit  302  presents a high impedance to the gate of the transistor  320  and thus the voltage on the gate is determined by the boosted gate signal V BG  from the cancellation circuit  322 . When the REGOUT signal is active high, the isolation circuit  302  turns ON, coupling the gate of the transistor  320  to approximately ground to thereby turn OFF the transistor  320 . In the embodiment of FIG. 3, the isolation circuit  302  includes a load transistor  342  and an enable transistor  344  connected in series between the gate of the transistor  320  and ground as shown. The enable transistor  344  receives the REGOUT signal from the feedback control circuit  332 , turning ON and OFF when the REGOUT signal is high and low, respectively. 
     In operation, the charge pump circuit  300  operates in two modes, a normal mode and a power-savings mode. During both the normal and powersavings modes of operation, the ring oscillator  326  continuously generates the OCLK signal. In the following description, the means by which each of the voltage-boosting stages  304  and  306  boosts the corresponding voltage is substantially the same as in the charge pump circuit  100  previously described with reference to FIG. 1, and thus for the sake of brevity will not be described in more detail. Instead, the following description will explain the operation of the feedback control circuit  332  and isolation circuit  302  in reducing the voltage ripple of the pumped output voltage V P  generated by the charge pump circuit  300 . 
     The charge pump circuit  300  operates in the normal mode when the pumped output voltage V P  is less than the desired pumped output voltage V PD . When the actual pumped output voltage V P  is less than the desired voltage V PD , the ratio circuit  334  develops the ratio voltage V RP  having a value that is less than the reference voltage V R , causing the comparator  336  to drive its output inactive low. In response to the low output from the comparator  336 , the amplifier  338  applies the amplified low output to the buffer  340  which, in turn, drives the REGOUT signal inactive low. In response to the low REGOUT signal, the transistor  344  turns OFF causing the isolation circuit  302  to present a very high impedance to the gate of the transistor  320 . In this situation, the value of the boosted gate signal V BG  from the cancellation circuit  322  controls the operation of the transistor  320 . The low REGOUT signal also causes the switching circuit  328  to present a low impedance, thereby applying the OCLK signal from the ring oscillator  326  to the clocking-latching circuit  330  which, in turn, clocks the voltage-boosting stages  304  and  306  with the CLK and {overscore (CLK)} signals, respectively. The CLK and {overscore (CLK)} signals also clock the cancellation circuit  322  during the normal mode of operation. Thus, during the normal mode of operation, the voltage-boosting stages  304  and  306  and the cancellation circuit  322  operate in response to the CLK and {overscore (CLK)} signals to generate the pumped output voltage V P  on the output node  310  in the same manner as previously described with reference to FIG.  1 . 
     When the pumped output voltage V P  becomes greater than the desired voltage V PD , the charge pump circuit  300  commences operation in the power-savings mode of operation. In response to the pumped output voltage V P  becoming greater than the desired voltage V PD , the ratio circuit  334  generates the ratio voltage V RP  having a value that is greater than the reference voltage V R . When the ratio voltage V RP  is greater than the reference voltage V R , the comparator  336  drives its output active high and this high output is applied through the amplifier  338  to the buffer circuit  340 . In response to the amplified high output of the comparator  336 , the buffer  340  drives the REGOUT signal active high. In response to the high REGOUT signal, the switching circuit  328  presents a high impedance so that the OCLK signal no longer clocks the clocking-latching circuit  330 . As a result, the clocking-latching circuit  330  no longer generates the CLK and {overscore (CLK)} signals to clock the voltage-boosting stages  304  and  306 . At this point, the CLK and {overscore (CLK)} signals remain in their previous latched states. 
     During the power-savings mode of operation, the active high REGOUT signal turns ON the transistor  344  coupling the gate of the transistor  320  to approximately ground through the load transistor  342  and activated transistor  344 . As a result, in the charge pump circuit  300  the transistor  320  in the final voltage-boosting stage  306  is turned OFF during the power-savings mode of operation regardless of the level of the boosted gate signal V BG  from the cancellation circuit  322 , as will now be described in more detail. As previously described, the cancellation circuit  322  generates the boosted gate signal V BG  responsive to the CLK and {overscore (CLK)} signals. Thus, the level of the signal V BG  is determined by the latched state of the CLK and {overscore (CLK)} signals when the charge pump circuit  300  enters the power-savings mode of operation responsive to the REGOUT signal going active high. More specifically, if the CLK and {overscore (CLK)} signals are latched high and low, respectively, then the boosted gate signal V BG  remains low during the power-savings mode. In this situation, the transistor  320  would normally be turned OFF, but this is now ensured by the isolation circuit  302  driving the gate of the transistor  320  to ground and thereby isolating the output node  310  so that the ripple of the pumped output voltage V P  is not affected by the voltage on the node  316 . 
     If the CLK and {overscore (CLK)} signals are latched low and high, respectively, upon entering the power-savings mode, the cancellation circuit  322  attempts to drive the boosted gate signal V BG  high. In the charge pump circuit  300 , however, the isolation circuit  302  is turned ON in the power-savings mode responsive to the active high REGOUT signal. More specifically, the transistor  344  turns ON and the isolation circuit  302  presents approximately the resistance of the load transistor  342  between the gate of the transistor  320  and ground. The relatively small resistance of the load transistor  342  presents a large load on the output of the cancellation circuit  322 , thereby driving the output of the cancellation circuit  322  and thus the gate of the transistor  320  low. Therefore, although the cancellation circuit  322  would normally apply a high signal V BG  to turn ON the transistor  320  in this situation, the isolation circuit  302  drives the gate of the transistor  320  low to ensure that the transistor is turned OFF. 
     In the charge pump circuit  300 , the isolation circuit  302  turns OFF the transistor  320  isolating the output node  310  from the node  316  so that the pumped output voltage V P  is unaffected by the voltage on the node  316  independent of the state of the latched CLK and {overscore (CLK)} signals when the power-savings mode is entered. In this way, the voltage on the node  316  does not increase the ripple of the pumped output voltage V P  during the power-savings mode. Thus, relative to conventional charge pump circuits, the charge pump circuit  300  may operate with a lower power consumption and a lower voltage ripple of the voltage V P  during the power savings mode of operation. In the charge pump circuit  300 , the isolation circuit  302  controls the final voltage-boosting stage  306  to reduce the ripple of the voltage V P . One skilled in the art will realize, however, a separate isolation circuit could be utilized to isolate the output node  310  from the final voltage-boosting stage. For example, the final voltage-boosting stage could include a diode-coupled transistor and a separate isolation circuit could then be coupled between the output of this final stage and the node  310  and operate responsive to the REGOUT signal. 
     Once the pumped output voltage V P  becomes less than the desired voltage V PD , the feedback control circuit  332  drives the REGOUT signal inactive low and the charge pump circuit  300  once again commences operation in the normal mode. Note that when the REGOUT signal goes inactive low, the transistor  344  turns OFF causing the isolation circuit  302  to present a high impedance to the gate of the transistor  320  so that the level of the boosted gate signal V BG  from the cancellation circuit  322  controls the operation of the transistor  320  during the normal mode. 
     FIG. 4 is a block diagram of a dynamic random access memory (“DRAM”)  500  including the charge pump circuit  300  of FIG.  3 . The DRAM  500  includes an address decoder  502 , control circuit  504 , and read/write circuitry  506  coupled to a memory-cell array  508 , all of these components being conventional. In addition, the address decoder  502  is coupled to an address bus, the control circuit  504  is coupled to a control bus, and the read/write circuitry  506  is coupled to a data bus. The pumped output voltage V P  generated by the charge pump circuit  300  may be applied to number of components within the DRAM  500 , as understood by those skilled in the art. In the DRAM  500 , the charge pump circuit  300  applies the pumped output voltage V P  to the read/write circuitry  506  that may utilize this voltage in a data buffer (not shown) to enable that buffer to transmit or receive full logic level signals on the data bus. The charge pump circuit  300  also applies the pumped output voltage V P  to the address decoder  502  which, in turn, may utilize this voltage to apply boosted word line voltages to the array  508 . In operation, external circuitry, such as a processor or memory controller, applies address, data, and control signals on the respective busses to transfer data to and from the DRAM  500 . 
     Although the charge pump circuit  300  is shown in the DRAM  500 , one skilled in the art will realize the charge pump circuit  300  may be utilized in any type of integrated circuit requiring a pumped voltage, including other types of nonvolatile and volatile memory devices such as FLASH memories as well as SDRAMs, SRAMS, and packetized memory devices like SLDRAMs. When contained in a FLASH memory, the charge pump circuit  300  would typically receive an external programming voltage V PP  and generate a boosted programming voltage that is utilized to erase the data stored in blocks of nonvolatile memory cells contained in the array  508 , as will be understood by one skilled in the art. 
     FIG. 5 is a block diagram of a computer system  600  including computing circuitry  602  that contains the memory device  500  of FIG.  4 . The computing circuitry  602  performs various computing functions, such as executing specific software to perform specific calculations or tasks. In addition, the computer system  600  includes one or more input devices  604 , such as a keyboard or a mouse, coupled to the computer circuitry  602  to allow an operator to interface with the computer system. Typically, the computer system  600  also includes one or more output devices  606  coupled to the computer circuitry  602 , such output devices typically being a printer or a video terminal. One or more data storage devices  608  are also typically coupled to the computer circuitry  602  to store data or retrieve data from external storage media (not shown). Examples of typical storage devices  608  include hard and floppy disks, tape cassettes, and compact disc read-only memories (CD-ROMs). The computer circuitry  602  is typically coupled to the memory device  500  through appropriate address, data, and control busses to provide for writing data to and reading data from the memory device. 
     It is to be understood that even though various embodiments and advantages of the present invention have been set forth in the foregoing description, the above disclosure is illustrative only, and changes may be made in detail, and yet remain within the broad principles of the invention. For example, some of the components described above may be implemented using either digital or analog circuitry, or a combination of both, and also, where appropriate, may be realized through software executing on suitable processing circuitry. Therefore, the present invention is to be limited only by the appended claims.