Abstract:
A driving apparatus for a display panel capable of reducing a circuit scale while suppressing the drop of a contrast includes a scan driver having a first power source for generating a first voltage, generating a scan pulse for bringing the capacitive light emission device to either one of an ON state and an OFF state based on the first voltage, and applying the scan pulse to the row electrode, a sustain driver having a second power source for generating a second voltage, generating a sustain pulse for allowing the capacitive light emission device set to the ON state to emit light based on the second voltage, and applying the scan pulse to the row electrode, and a reset driver generating a reset pulse for initializing the state of the capacitive light emission device based on the sum of the first voltage generated by the first power source and the second voltage generated by the second power source, and applying the reset pulse to the row electrode. This circuit construction can eliminate the necessity of a dedicated power source for generating the reset pulse. In another aspect of the invention, a reset pulse having a waveform having a sharp level shift at a front edge thereof and a gentle level shift at a portion succeeding the front edge is generated based on a voltage generated by connecting in series a power source for generating a sustain discharge pulse and a power source for generating a scan pulse. This circuit construction can eliminate the necessity for a dedicated power source for generating the reset pulse and can lower light emission brightness resulting from reset discharge induced in accordance with the reset pulse.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    This invention relates to a driving apparatus of a display panel having capacitive light emitting devices arranged in matrix form.  
           [0003]    2. Description of the Related Art  
           [0004]    A display apparatus having a plasma display panel mounted thereto is now commercially available as the display panel described above (for example, Japanese Patent Kokai No. 2000-155557 (Patent Reference 1)).  
           [0005]    [0005]FIG. 1 schematically shows the construction of such a display apparatus.  
           [0006]    Referring to FIG. 1, row electrodes Y 1  to Y n  and row electrodes X 1  to X n  are shown to be formed in a PDP 1  as the plasma display panel, whereby each pair of X and Y constitute a row electrode pair corresponding to each row (first to nth rows) of one screen. Column electrodes D 1  to D m  respectively constituting column electrodes corresponding to columns (first to nth columns) of one screen are further formed in such a way as to intersect these row electrode pairs and to sandwich a dielectric layer and discharge spaces, not shown in the drawing. In this case, each discharge cell as a capacitive light emitting device is formed at each point of intersection between each row electrode pair and each column electrode. An address driver  2  converts pixel data of each pixel based on an image signal to a pixel data pulse having a voltage value corresponding to a logic level of the data and applies this pixel data pulse to the column electrodes D 1  to D m  for each row. An X row electrode driver  3  generates a reset pulse for initializing a residual wall charge amount of each discharge cell and a sustain discharge pulse for keeping a discharge light emission state of the discharge cell set to an ON mode which will be explained later, and applies these pulses to the row electrodes X 1  to X n . A Y row-electrode driver  4  generates a reset pulse for initializing the. residual wall charge amount of each discharge cell and a sustain discharge pulse for keeping the discharge light emission state of the discharge cell in the same way as the X row electrode driver  3 , and applies these pulses to the row electrodes Y 1  to Y n . The Y row electrode driver  4  further generates a priming pulse for re-forming charge particles inside the discharge cell and a scan pulse SP for forming a charge amount corresponding to the pixel data pulse for each discharge cell and setting each discharge cell to either the ON mode or the OFF mode, and applies these pulses to the row electrodes Y 1  to Y n .  
           [0007]    [0007]FIG. 2 shows an internal construction of the X row electrode driver  3  and the Y row electrode driver  4 . Incidentally, an electrode X j  in FIG. 2 represents an electrode of a jth row among the electrodes X 1  to X n , and an electrode Y j  represents an electrode of the jth row among the electrodes Y 1  to Y n .  
           [0008]    The X row electrode driver  3  has two power sources B 101  and B 102 . The power source B 101  outputs a voltage Vs 1  (for example, 170 V) and the power source B 102  outputs a voltage Vr 1  (for example, 190 V). A positive terminal of the power source B 101  is connected to a connection line  111  of the electrode X j  through a switching device S 103  and its negative terminal is grounded. A switching device S 104  is interposed between the connection line  111  and the ground. A series circuit including a switching device S 101 , a diode D 101  and a coil L 101  and a series circuit including a coil L 102 , a diode D 102  and a switching device S 102  are connected to the ground through a capacitor C 101  in common. The diode D 101  has its anode on the side of the capacitor C 101  and the diode D 102  has its cathode on the side of the capacitor C 101 . A positive terminal of the power source B 102  is connected to the connection line  111  through a switching device S 108  and a resistor R 101  and its negative terminal is connected to the ground. The Y row electrode driver  4  has four power sources B 103  to B 106 . The power source B 103  outputs the voltage Vs 1  (for example, 170 V). The power source B 104  outputs the voltage Vr 1  (for example 190 V). The power source B 105  outputs a voltage V off  (for example, 140 V) and the power source B 106  outputs a voltage V h  (for example, 160 V, V h &gt;V off ). A positive terminal of the power source B 103  is connected to a connection line  112  to a switching device S 115  through a switching device S 113  and its negative terminal is grounded. A switching device S 114  is interposed between the connection line  112  and the ground. A series circuit including a switching device S 111 , a diode D 103  and a coil L 104  and a series circuit including a coil L 104 , a diode D 104  and a switching device S 112  are connected to the ground through a capacitor C 102  in common. The diode D 103  has its anode on the side of the capacitor C 102  and the diode D 104  has its cathode on the side of the capacitor C 102 . The connection line  112  is connected to a connection line  113  of a positive terminal of the power source B 106  through a switching device S 115 . A positive terminal of the power source B 104  is connected to the ground and its negative terminal is connected to the connection line  113  through a switching device S 116  and a resistor R 102 . A positive terminal of the power source B 105  is connected to the connection line  113  through a switching device S 117  and its negative terminal is grounded. The connection line  113  is connected to a connection line  114  to the electrode Y j  through a switching device S 121 . A negative terminal of the power source B 106  is connected to the connection line  114  through a switching device S 122 . A diode D 105  is connected between the connection lines  113  and  114  and a series circuit of a switching device S 123  and a diode D 106  is connected to the diode D 105 . The diode D 105  has its anode on the side of the connection line  114  and the diode D 106  has its cathode on the side of the connection line  114 .  
           [0009]    Here, a control circuit, not shown in the drawing, controls ON/OFF switching of the switching devices S 101  to S 104 , S 111  to S 117  and S 121  to S 123 .  
           [0010]    Incidentally, the power source B 103 , the switching devices S 111  to S 115 , the coils L 103  and L 104 , the diodes D 103  and D 104  and the capacitor C 102  inside the Y row electrode driver  4  constitute a sustain driver part. The power source B 104 , the resistor R 102  and the switching device S 116  constitute a reset driver part. The remaining power sources B 105  and B 106 , switching devices S 113 , S 117 , S 121  and S 122  and diodes D 105  and D 106  constitute a scan driver part.  
           [0011]    Next, the operation in the construction described above will be explained with reference to a timing chart of FIG. 3.  
           [0012]    As shown in FIG. 3, driving of the PDP  1  is conducted dividedly in a reset period, an address period and a sustain period.  
           [0013]    First of all, in the reset period, the switching device S 123  of the Y row electrode driver  4  turns ON. The switching device S 123  remains ON in the reset period and the sustain period. At the same time, the switching device S 108  of the X row electrode driver  3  turns ON and the switching device S 116  of the Y row electrode driver  4  turns ON. Other switching devices remain OFF. When the switching device S 108  is turned ON, a current flows from the positive terminal of the power source B 102  to the electrode X j  through the switching device S 108  and the resistor R 101 . When the switching device S 116  is turned ON, a current flows from the electrode Y j  into the negative terminal of the power source B 104  through the diode D 106 , the resistor R 102  and the switching device S 116 . In this case, the potential on the electrode X j  gradually rises due to the time constant of the load capacitance Co and the resistor R 101  of the PDP  1 , generating the reset pulse RP x  as shown in FIG. 3. On the other hand, the potential of the electrode Y j  gradually lowers due to the time constant of the load capacitance C 0  and the resistor R 102 , generating the reset pulse RP y  as shown in FIG. 3. The reset pulse RP x  is simultaneously applied to all electrodes X 1  to X n  and the reset pulse RP y  is simultaneously applied to all electrodes Y 1  to Y n . As these reset pulses RP 1  and RP y  are simultaneously applied, reset discharge is induced inside all discharge cells of the PDP  1 . After the finish of this discharge, wall charge of a predetermined amount is uniformly generated in the dielectric layer of all discharge cells. Such reset discharge initializes all discharge cells to the ON mode. After the levels of the reset pulses RP x  and RP y  get into saturation, the switching devices S 108  and S 116  turn OFF before the termination of the reset period. At this point, the switching devices S 104 , S 114  and S 115  are turned ON and both electrodes X j  and Y j  are grounded. In consequence, the reset pulses RP x  and RP y  disappear.  
           [0014]    Next, in the address period, the switching devices S 114  and S 115  turn OFF, the switching device S 123  turns OFF, the switching device S 117  turns ON and at the same time, the switching device S 122  turns ON. As the switching device S 117  is turned ON, the power source B 105  and the power source B 106  are connected in series, and a negative potential representing the difference between the voltages V h  and V off  appears at the negative terminal of the power source B 106  and is applied to the electrode Y j . In this address period, the address driver  2  converts the pixel data for each pixel based on the image signal to pixel data pulses DP 1  to DP n  having a voltage value corresponding to the logic level of the image data and serially applies these data pulses to the column electrodes D 1  to D m . As shown in FIG. 3, the image data pulses DP j  and DP j+1  are applied to the electrodes Y and Y j+1 . In the mean time, the Y row electrode driver  4  serially applies the priming pulse PP of the positive voltage to the row electrodes Y 1  to Y n , and also applies serially the scan pulse SP of the negative voltage to the row electrode Y 1  to Y n  in synchronism with each timing of the pixel data pulse group DP 1  to DP n  immediately after the application of each priming pulse PP. Explanation will be given on the electrode Y j . When generating the priming pulse PP, the switching device S 121  turns ON and the switching device S 122  turns OFF. The switching device S 117  remains ON. In consequence, the potential V off  of the positive terminal of the power source B 105  is applied as the priming pulse PP to the electrode Y j  through the switching device S 117  and then through the switching device S 121 . After the application of this priming pulse PP, the switching device S 121  turns OFF while the switching device S 122  turns ON in synchronism with the application of the pixel data pulse DP j  from the address driver  2 . In consequence, a negative potential representing the difference between the voltage V h  of the negative terminal of the power source B 106  and the V off  is applied as the scan pulse SP to the electrode Y j . In synchronism with the stop of the application of the pixel data pulse DP j  from the address driver  2 , the switching device S 121  turns ON and the switching device S 122  turns OFF. The potential V off  of the positive terminal of the power source B 105  is applied to the electrode Y j  through the switching device S 117  and then through the switching device S 121 . As to the electrode Y j+1 , too, the priming pulse PP is thereafter applied in the same way as the electrode Y j  as shown in FIG. 3 and the scan pulse SP is applied in synchronism with the application of the pixel data pulse DP j+1  from the address driver  2 . Discharge develops in the discharge cells to which the pixel data pulse of the positive voltage is further applied simultaneously among the discharge cells belonging to the row electrodes to which the scan pulse SP is applied, and the wall charge is mostly lost. On the other hand, discharge does not develop in the discharge cells to which the scan pulse SP is applied but the pixel data pulse of the positive voltage is not applied, and the wall charge remains as such. In this case, the discharge cells the wall charge of which disappears are set to the OFF mode and the discharge cells the wall charge of which remains are set to the ON mode. When the address period shifts to the sustain period, the switching devices S 117  and S 121  turn OFF and the switching devices S 114  and S 115  turn ON instead. The ON state of the switching device S 104  is continued.  
           [0015]    In the sustain period, the switching device S 104  of the X row electrode driver  3  is turned ON and consequently, the potential of the electrode X j  reaches the ground potential that is substantially 0 V. Next, when the switching device S 104  is turned OFF and the switching device S 101  is turned ON, a current resulting from the charge stored in the capacitor C 1  flows into the electrode X j  through the coil L 101 , the diode D 101  and the switching device S 101  and charges the load capacitance C 0  of the PDP  1 . In this process, the potential of the electrode X j  gradually moves up due to the time constant of the coil L 101  and the load capacitance C 0  as shown in FIG. 3. Next, the switching device S 101  turns OFF and the switching device S 103  turns ON. In consequence, the potential V s1  of the positive terminal of the power source B 101  is applied to the electrode X j . The switching device S 103  is thereafter turned OFF, the switching device S 102  is turned ON and a current resulting from the charge stored in the load capacitance C 0  flows from the electrode X j  into the capacitor C 101  through the coil L 102 , the diode D 102  and then through the switching device S 102 . In this case, the potential of the electrode X j  gradually lowers due to the time constant of the coil L 102  and the capacitor C 101  as shown in FIG. 3. When the potential of the electrode X j  reaches substantially 0 V, the switching device S 102  turns OFF and the switching device S 104  turns ON. Due to this operation, the X row electrode driver  3  applies the sustain discharge pulse IP x  of the positive voltage such as shown in FIG. 3 to the electrode X j . At the time of turn-ON of the switching device S 104  at which the sustain discharge pulse IP x  disappears, the switching device S 111  of the Y row electrode driver  4  turns ON while the switching device S 114  turns OFF. When the switching device S 114  is ON, the potential of the electrode Y j  is at the ground potential that is substantially 0 V. When the switching device S 114  is turned OFF and the switching device S 111  is turned ON, however, a current resulting from the charge stored in the capacitor C 102  flows into the electrode Y j  through the coil L 103 , the diode D 103 , the switching devices S 111 , S 115  and S 113  and the diode D 106 , and charges the load capacitance C 0  of the PDP 1 . In this case, the potential of the electrode Y j  gradually moves up due to the time constant of the coil L 103  and the load capacitance C 0  as shown in FIG. 3. Next, the switching device S 111  turns OFF and the switching device S 113  turns ON. Consequently, the potential V s1  of the positive terminal of the power source B 103  is applied to the electrode Y j . Thereafter, the switching device S 113  is turned OFF, the switching device S 112  is turned ON and a current resulting from the charge stored in the load capacitor C 0  flows from the electrode Y j  to the capacitor C 102  through diode D 105 , the switching device S 115 , the coil L 104 , the diode D 104  and then the switching device S 112 . In this case, the potential of the electrode Y j  gradually lowers due to the time constant of the coil L 104  and the capacitor C 102  as shown in FIG. 3. When the potential of the electrode Y j  reaches substantially 0 V, the switching device S 112  turns OFF and the switching device S 114  turns ON. By this operation, the Y row electrode driver  4  applies the sustain discharge pulse IP y  of the positive voltage such as shown in FIG. 3 to the electrode Y j .  
           [0016]    As described above, the sustain discharge pulse IP x  and the sustain discharge pulse IP y  are alternately applied to the electrodes X 1  to X n  and to the electrodes Y 1  to Y n  in the sustain period. Therefore, only the discharge cells the wall charge of which remains, that is, only the discharge cells set to the ON mode, repeat discharge light emission and keep the light emission state.  
           [0017]    Incidentally, reset discharge induced so as to initialize altogether the wall charge amounts inside all discharge cells during the reset period must be relatively strong discharge. Therefore, the pulse voltage (−Vr 1 ) of the reset pulse RP y  is set to a voltage level higher than the pulse voltage of the sustain discharge pulse IP y . For this purpose, the power source B 104  (voltage Vr 1 ) for generating the voltage higher than the voltage Vs 1  of the power source B 103  for generating the sustain discharge pulse IPy is disposed, and results in the increase of the circuit scale. In addition, the voltage values of the power sources B 103  and B 104  are mutually different and the switching devices S 113 , S 115  and S 116  interposed between these power sources B 103  and B 104  are the semiconductor switches, so that the possibility exists that the reverse current flows between the power sources B 103  and B 104 . Furthermore, light emission with reset discharge does not at all participate in the display image, the lowering of contrast occurs.  
           [0018]    The invention is completed to solve the problems described above and aims at providing a driving apparatus of a display panel that can reduce the scale of the circuit.  
           [0019]    It is another object of the invention to provide a driving apparatus of a display panel that can reduce a circuit scale while suppressing the drop of contrast.  
         SUMMARY OF THE INVENTION  
         [0020]    According to a first aspect of the invention, there is provided a driving apparatus for driving a display panel having a plurality of row electrodes, a plurality of column electrodes so arranged as to intersect the row electrodes and a capacitive light emission device formed at each intersection of the row electrode and the column electrode, comprising a scan driver having a first power source for generating a first voltage, generating a scan pulse for bringing the capacitive light emission device to either one of an ON state and an OFF state based on the first voltage, and applying the scan pulse to said row electrode, a sustain driver having a second power source for generating a second voltage, generating a sustain discharge pulse for allowing the capacitive light emission device set to the ON state to emit light based on the second voltage, and applying the scan pulse to the row electrode, and a reset driver generating a reset pulse for initializing the state of the capacitive light emission device based on the sum of the first voltage generated by the first power source and the second voltage generated by the second power source, and applying the reset pulse to the row electrode.  
           [0021]    According to another aspect of the invention, there is provided a driving apparatus for driving a display panel having a plurality of row electrodes, a plurality of column electrodes so arranged as to intersect the row electrodes and a capacitive light emission device formed at each intersection of the row electrode and the column electrode, comprising a scan driver having a first power source for generating a first voltage, generating a scan pulse for bringing the capacitive light emission device to either one of an ON state and an OFF state based on the first voltage, and applying the scan pulse to the row electrode, a sustain driver having a second power source for generating a second voltage, generating a sustain discharge pulse for allowing the capacitive light emission device set to the ON state to emit light based on the second voltage, and applying the scan discharge pulse to the row electrode, and a reset driver generating a reset pulse for initializing the state of the capacitive light emission device based on the sum of the first voltage generated by the first power source and the second voltage generated by the second power source, and applying the reset pulse to the row electrode, wherein the reset driver generates a pulse signal having a waveform exhibiting a sharp level shift at a front edge thereof and a gentle level shift at a portion succeeding the front edge. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]    [0022]FIG. 1 is a view schematically showing the construction of a plasma display apparatus;  
         [0023]    [0023]FIG. 2 is a view showing an internal construction of an X row electrode driver  3  and a Y row electrode driver  4  of the plasma display apparatus shown in FIG. 1;  
         [0024]    [0024]FIG. 3 is a time chart showing operations of the X row electrode driver  3  and the Y row electrode driver  4 ;  
         [0025]    [0025]FIG. 4 is a view schematically showing the construction of a plasma display apparatus according to the invention;  
         [0026]    [0026]FIG. 5 is a view showing a schematic driving format based on a sub-field method;  
         [0027]    [0027]FIG. 6 is a view showing an internal construction of an X row electrode driver  30  and a Y row electrode driver  40  of the plasma display apparatus shown in FIG. 4;  
         [0028]    [0028]FIG. 7 is a time chart showing operations of the X row electrode driver  30  and the Y row electrode driver  40 ;  
         [0029]    [0029]FIG. 8 is a view showing an internal construction of an X row electrode driver  30 ′ and a Y row electrode driver  40 ′ according to a second embodiment;  
         [0030]    [0030]FIG. 9 is a time chart showing operations of the X row electrode driver  30 ′ and the Y row electrode driver  40 ′ shown in FIG. 8;  
         [0031]    [0031]FIG. 10 is a view showing an internal construction of the X row electrode driver  30  and a Y row electrode driver  40 ″ according to a third embodiment; and  
         [0032]    [0032]FIG. 11 is a time chart showing operations of the X row electrode driver  30  and the Y row electrode driver  40 ″ shown in FIG. 10. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0033]    Embodiments of the invention will be hereinafter explained in detail with reference to the accompanying drawings.  
         [0034]    [0034]FIG. 4 is a view schematically showing the construction of a plasma display apparatus having mounted thereto a PDP as a display panel.  
         [0035]    Referring to FIG. 4, the PDP  10  as a plasma display panel includes row electrodes Y 1  to Y n  and X 1  to X n  that constitute row electrode pairs each corresponding to each display line (first to nth display lines) of one screen. The PDP  10  further includes column electrodes D 1  to D m  that intersect at right angles the row electrode pairs and correspond to each column (first to mth columns) of one screen while sandwiching a dielectric layer and a discharge space not shown in the drawing. Incidentally, a discharge cell as a capacitive light-emitting device is formed at the point of intersection between one row electrode pair (X, Y) and one column electrode D.  
         [0036]    A driving control circuit  50  converts an input image signal to pixel data for each pixel and divides this pixel data to each bit digit to acquire a pixel data bit. The driving control circuit  50  supplies the pixel data bits for each display line (m) to the address driver  20  at the same bit digit. Further, the driving control circuit  50  supplies various kinds of switching signals SW (to be later described) to each of the X row electrode driver  30  and the Y row electrode driver  40  in order to drive the PDP 10  in accordance with the light emission drive format based on the sub-field method as shown in FIG. 5. Incidentally, the sub-field method divides each field in the image signal to N sub-fields SF 1  to SF(N) shown in FIG. 5 and drives each pixel for each sub-field for light emission to express intermediate brightness.  
         [0037]    [0037]FIG. 6 shows an internal construction of each of the X row electrode driver  30  and the Y row electrode driver  40 .  
         [0038]    As shown in FIG. 6, one of the ends of a capacitor C 1  of the X row electrode driver  30  is grounded to a PDP ground potential as the ground potential of the PDP  10 . A switching device S 1  remains OFF while a switching signal SW 1  of a logic level 0 is supplied from the driving control circuit  50 . When the logic level of the switching signal SW 1  is 1, on the other hand, the switching device S 1  is turned ON and applies a potential occurring at the other end of the capacitor C 1  to the row electrode X of the PDP  10  through a coil L 1  and a diode D 1 . A switching device S 2  remains OFF while a switching signal SW 2  of the logic level 0 is supplied from the driving control circuit  50 . When the logic level of the switching signal SW 2  is 1, on the other hand, the switching device S 2  is turned ON and applies a potential of the row electrode X to the other end of the capacitor C 1  through a coil L 2  and a diode D 2 . In this case, the potential of the row electrode X charges the capacitor C 1 . A switching device S 3  remains OFF while a switching signal SW 3  of the logic level 0 is supplied from the driving control circuit  50 . When the logic level of the switching signal SW 3  is 1, on the other hand, the switching device S 3  is turned ON and applies a voltage V s  generated by a power source B 1  to the row electrode X. Incidentally, the voltage V s  is a pulse voltage of a sustain discharge pulse IP x  to be later described. In other words, the power source B 1  is the power source that generates the voltage V s  as the pulse voltage value of the sustain discharge pulse IP x . A switching device S 4  remains OFF while a switching signal SW 4  of a logic level 0 is supplied from the driving control circuit  50 . When the logic level of the switching signal SW 4  is 1, on the other hand, the switching device S 4  is turned ON and brings the potential of the row electrode X to the PDP ground potential.  
         [0039]    The Y row electrode driver  40  includes a sustain driver part SUD, a reset driver part RSD and a scan driver part SCD as shown in FIG. 6.  
         [0040]    One of the ends of a capacitor C 2  in the sustain driver part SUD is grounded to the PDP ground potential as the ground potential of the PDP  10 . A switching device S 11  remains OFF while a switching signal SW 11  of the logic level 0 is supplied from the driving control circuit  50 . When the logic level of the switching signal SW 11  is 1, on the other hand, the switching device S 11  is turned ON and applies a potential occurring at the other end of the capacitor C 2  to a connection line  12  through a coil L 3  and a diode D 3 . A switching device S 12  remains OFF while a switching signal SW 12  of the logic level 0 is supplied from the driving control circuit  50 . When the logic level of the switching signal SW 12  is 1, on the other hand, the switching device S 12  is turned ON and applies a potential of the connection line  12  to the other end of the capacitor C 2  through a coil L 4  and a diode D 4 . In this case, the potential of this connection line  12  charges the capacitor C 2 . A switching device S 13  remains OFF while a switching signal SW 13  of the logic level 0 is supplied from the driving control circuit  50 . When the logic level of the switching signal SW 13  is 1, on the other hand, the switching device S 13  is turned ON and applies a voltage V s  generated by a power source B 3  to the connection line  12 . Incidentally, the voltage V s  is a pulse voltage of a sustain discharge pulse IP y  to be later described. In other words, the power source B 1  is the power source that generates the voltage V s  as the pulse voltage value of the sustain discharge pulse IP y . A switching device S 14  remains OFF while a switching signal SW 14  of the logic level 0 is supplied from the driving control circuit  50 . When the logic level of the switching signal SW 14  is 1, on the other hand, the switching device S 14  is turned ON and brings the potential of the connection line  12  to the PDP ground potential. A switching device S 15  remains ON while a switching signal SW 15  supplied from the driving control circuit  50  has a logic level 1 and connects the connection line  12  to the later-appearing connection line  13 .  
         [0041]    A switching device S 17  in the reset drive part RSD remains OFF while a switching signal SW 17  of the logic level 0 is supplied from the driving control circuit  50 . When the logic level of the switching signal SW 17  is 1, on the other hand, the switching device S 17  is turned ON and connects a positive terminal of the power source B 3  to a connection line  13  through a resistor R 1 . In other words, the switching device S 17  applies the voltage V s  generated by the power source B 3  to the connection line  13  through the resistor R 1  in accordance with the switching signal SW 17 . A switching device S 18  remains OFF while a switching signal SW 18  of the logic level 0 is supplied from the driving control circuit  50 . When the logic level of the switching signal SW 18  is 1, on the other hand, the switching device S 18  is turned ON and grounds the connection line  13  through a resistor R 2  and a diode D 7 .  
         [0042]    Switching devices S 19  and S 20  in the scan driver part SCD remain OFF while switching signals SW 19  and SW 20  of the logic level 0 are supplied from the driving control circuit  50 . When the logic level of both of the switching signals SW 19  and SW 20  is 1, on the other hand, both switching devices S 19  and S 20  are turned ON and apply a negative voltage (−V off ) generated by the power source B 3  to a connection line  13  through a resistor R 3 . Incidentally, the voltage (−V off ) is the one that bears a pulse voltage value of the later-appearing scan pulse SP. In other words, the power source B 5  is a power source that generates the voltage (−V off ) as the pulse voltage value of the scan pulse SP. A switching device S 21  remains ON only while a switching signal SW 21  supplied from the driving control circuit  50  has the logic level 1 and connects a positive terminal of a power source B 6  to the row electrode Y. In other words, the switching device S 21  applies the potential of the positive terminal of the power source B 6  to the row electrode Y in accordance with the switching signal SW 21 . A switching device S 22  remains ON while a switching signal SW 22  supplied from the driving control circuit  50  has the logic level 1 and connects a negative terminal of a power source B 6  to the row electrode Y. In other words, the switching device S 22  applies the potential of the connection line  13  connected to the negative terminal of the power source B 6  to the row electrode Y. The power source B 6  is the one that generates a voltage V h  for fixing the voltage on all the row electrodes Y 1  to Y n  to a voltage of positive polarity during an address period to be later described. In this case, the voltage V h  forms a part of the pulse voltage in the scan pulse SP. In other words, the power source B 6  is the one that generates the voltage V h  forming a part of the pulse voltage in the scanning pulse SP.  
         [0043]    Next, the operation of the construction described above will be explained with reference to the timing chart of FIG. 7. Incidentally, FIG. 7 shows in extraction the operation inside the leading sub-field SF 1  shown in FIG. 5. As shown in FIG. 7, the sub-field SF 1  has a reset period, an address period and a sustain period.  
         [0044]    First of all, in the reset period, the driving control circuit  50  switches the switching devices S 17  and S 21  in the reset driver part RSD from the OFF state to the ON state. Consequently, a current flows into the discharge cells through a current path (represented by CR 1  in FIG. 6) including the power source B 3 , the switching device S 17 , the resistor R 1 , the power source B 6 , the switching device S 21  and the row electrode Y. In this case, the voltage on the row electrode Y gradually rises as shown in FIG. 7 in accordance with a time constant of a load capacitance C 0  and the resistor R 1  of the PDP  10 . When the voltage on the row electrode Y reaches a voltage (V s +V h ) created by the series connection of the power source B 3  and the power source B 6 , the driving control circuit  50  switches the switching devices S 17  and S 21  to the OFF state and the switching devices S 18  and S 22  to the ON state. In consequence, a current path (represented by CR 2  in FIG. 6) including the switching devices S 22  and S 18 , the resistor R 2  and the diode D 7  is formed, and the potential on the row electrode Y gradually lowers as shown in FIG. 7. Due to the operation described above, a reset pulse RP y  having pulse voltage (V s +V h ) shown in FIG. 7 and exhibiting a gentle rise and fall shift is created and is simultaneously applied to all the row electrodes Y 1  to Y n  of the PDP  10 . In this case, first reset discharge (write discharge) is generated inside all the discharge cells of the PDP  10  at the rise of the reset pulse RP y . After this discharge is completed, a predetermined amount of wall charge is uniformly generated in the dielectric layers of all the discharge cells. Second reset discharge (erase discharge) is generated inside all the discharge cells at the fall of the reset pulse RP y  and the wall charge described above disappears from inside all the discharge cells. In other words, the wall charge formation state inside all the discharge cells is initialized in accordance with first and second reset discharges generated in response to the application of the reset pulse RP y .  
         [0045]    Next, in the address period, the driving control circuit  50  switches the switching devices S 19  to S 21  in the scan driver part SCD from the ON state to the OFF state. Consequently, the voltage on the row electrode Y is kept at the voltage V h  of the positive polarity generated by the power source B 3  as shown in FIG. 7. The driving control circuit  50  serially switches the switching device S 21  corresponding to each of the first to nth display lines to the OFF state for a predetermined period and serially switches the switching device S 22  corresponding to each of the first to nth display lines to the ON state for a predetermined period. Then, while the switching device S 21  is OFF and the switching device S 22  is ON, the potential of each of the row electrodes Y 1  to Y n  serially shifts from the positive voltage V h  to the negative voltage −V off , thereby creating the scanning pulse SP. In the mean time, the address driver  2  applies the pixel data pulse DP corresponding to the pixel data for each pixel based on the image signal to the column electrode D 1  to D m  for one display line (m). Consequently, write discharge selectively occurs inside the discharge cell to which the high-voltage pixel data pulse DP is applied simultaneously with the scanning pulse SP described above, and wall discharge is generated after this discharge is completed. On the other hand, write discharge does not occur inside the discharge cells to which the scan pulse SP is applied but the high-voltage pixel data pulse is not, and wall discharge is not generated, either. In this address period, the discharge cell in which the wall discharge is generated is set to the cell ON state and the discharge cells in which the wall discharge disappears are set to the OFF cell state.  
         [0046]    In the sustain period, the driving control circuit  50  first switches the switching device S 14  of the sustain driver part SUD from the OFF state to the ON state and after the passage of a predetermined period, switches the switching device S 15  of the sustain driver part SUD from the OFF state to the ON state. The driving control circuit  50  executes repeatedly switching setting SSY for each of the switching devices S 11  to S 14  of the sustain driver part SUD as shown in FIG. 7. Further, the driving control circuit- 50  executes repeatedly switching setting SSX for each of the switching devices S 1  to S 4  of the X row electrode driver  30  as shown in FIG. 7.  
         [0047]    In other words, in switching setting SSX, only S 1  of the switching devices S 1  to S 4  is first turned ON and the current resulting from the charge stored in the capacitor C 1  flows into the discharge cells through the coil L 1 , the diode D 1  and the row electrodes X. In consequence, the voltage on the row electrode X gradually rises as shown in FIG. 7. Next, the switching device S 3  is turned ON with S 1  and the voltage V s  by the power source B 1  is as such applied to the row electrode X. The voltage on the row electrode X is fixed at the voltage V s . Next, only S 2  of the switching devices S 1  to S 4  is turned ON and the current resulting from the charge stored in the load capacitance Co between the row electrodes X and Y flows into the capacitor C 1  through the row electrode X, the coil L 2  and the diode D 2 . In consequence, the voltage on the row electrode X gradually drops as shown in FIG. 7. As switching setting SSX described above is interruptedly executed, the sustain discharge pulse IP x  with the voltage Vs as the pulse voltage is created as shown in FIG. 7 and is repeatedly applied to the row electrode X.  
         [0048]    In switching setting SSY, on the other hand, only S 11  of the switching devices S 11  to S 14  and S 17  to S 22  is first turned ON and the current resulting from the charge stored in the capacitor C 2  flows into the discharge cells through the coil L 3 , the diode D 3 , the switching device S 15 , the switching device S 22  and the row electrode Y. In consequence, the voltage of the row electrode Y gradually rises as shown in FIG. 7. Next, the switching device S 13  is turned ON with S 11  and the voltage V s  by the power source B 3  is applied to the row electrode Y through the switching devices S 15  and S 22 . The voltage on the row electrode Y is fixed at the voltage V s  as shown in FIG. 7. Next, only S 12  of the switching devices S 11  to S 14  and only S 22  of the switching devices S 17  to S 22  are turned ON and the current resulting from the charge stored in the load capacitance Co between the row electrodes X and Y flows into the capacitor C 1  through the row electrode Y, the switching devices S 22  and S 15 , the coil L 4  and the diode D 4 . In consequence, the voltage on the row electrode Y gradually drops as shown in FIG. 7. As switching setting SSY described above is interruptedly executed, the sustain discharge pulse IP y  with the voltage Vs as the pulse voltage is created as shown in FIG. 7 and is repeatedly applied to the row electrode Y.  
         [0049]    In the sustain period, only the discharge cell in which the wall charge exists, that is, only the discharge cell set to the ON cell state, causes discharge (sustain discharge) whenever the sustain discharge pulses IP x  and IP y  are applied, and repeats emission of light with the discharge.  
         [0050]    As described above, in the Y row electrode driver  40  shown in FIG. 6, the switching devices  17  and  21  are turned ON when the reset pulse RP y  is generated. Consequently, the power source B 3  for generating the sustain discharge pulse IP y  and the power source B 6  for generating the scan pulse SP are connected in series and the voltage (V s +V h ) as the sum of both voltages is generated as the pulse voltage of the reset pulse RP. In other words, the reset pulse having a pulse voltage of a relatively high voltage can be generated without disposing a dedicated power source for generating the reset pulse. In this case, since the dedicated power source for generating the reset pulse is not necessary, a reverse current to the power source B 3  for generating the sustain discharge pulse IP y  does not occur. In other words, because a reverse current prevention circuit and a dedicated power source for generating the reset pulse are not necessary, a circuit scale can be reduced.  
         [0051]    The wave form of the reset pulse PRY is not limited to that shown in FIG. 7. It is also possible to apply the reset pulse simultaneously to the row electrodes X and the row electrodes Y, so that the first reset discharge described above is generated.  
         [0052]    [0052]FIG. 8 shows the internal structure of each of an X-row electrode driver  30 ′ and a Y-row electrode driver  40 ′ in another embodiment of the present invention which is constructed in view of the points described above.  
         [0053]    The driver shown in FIG. 8 features that a reset drive part RSD y  is adopted instead of the reset driver RSD, and a reset-driver part RSD x  is provided in the X-row electrode driver  30 ′. The remaining circuit structure is the same as those shown in FIG. 6.  
         [0054]    One of the electric terminals of each of resistors R 11  and R 12  provided in the reset driver RSD y  is connected to the connection line  13 . The other electric terminal of the resistor  12  is connected to one of the electric terminals of the capacitor C 11 , and the other electric terminal of the capacitor C 11  is connected to the other electric terminal of the resistor R 11  described above. In other words, a series circuit made up of the resistor R 12  and the capacitor C 11  is connected in parallel with the resistor R 11 , across its two electric terminals. The resistance of the resistor R 11  is higher than that of the resistor R 12 . The switching element S 17  remains OFF when the switching signal SW 17  has a logical 0 level, and is turned ON to apply the voltage V s  at the positive terminal of the above-described power source B 3  to the connection line  13  via the circuit made up of the resistors R 11  and R 12  when the signal SW 17  has a logical “1” level. The switching element S 18  remains OFF when the switching signal SW 18  has the logical 0 level, and is turned ON to connect the connection line  13  to the ground via the resistor R 2  and the diode D 7  when the the switching signal SW 18  has the logical 1 level.  
         [0055]    One of the electric terminals of each of the resistors R 41  and R 42  in the reset driver part RSD x  is respectively connected to the row electrode X. The other electric terminal of the resistor R 41  is connected to one of the electric terminals of the capacitor C 4 , and the other electric terminal of the capacitor C 4  is connected to the other electric terminal of the above-described resistor R 42 . In other words, a series circuit made up of the resistor R 41  and the capacitor C 4  is connected in parallel with the resistor R 42  across its two electric terminals. The resistor R 42  has a resistance higher than that of the resistor R 41 . The switching element S 5  remains OFF when the switching signal SW 5  has the logical 0 level, and is turned ON to apply the voltage (−Vr) at the negative terminal of the power source B 7  to the row electrodes X via the circuit made up of the above-described capacitor C 4 , resistors R 41  and  42  when the the switching signal SW 5  has the logical 1 level.  
         [0056]    The operation of the circuit having the structure described above will be explained with reference to the timing chart shown in FIG. 9.  
         [0057]    [0057]FIG. 9 is an extract diagram that shows the operations in the head subfield shown in FIG. 5, of which the operations in the periods excluding the reset period (address period and the sustain period) are the same as those shown in FIG. 7.  
         [0058]    In the reset period shown in FIG. 9, the drive control circuit  50  sets the switching element S 17  in the reset driver part RSD Y  in the Y row electrode driver  40  to the ON state, and set the switching element S 22  in the scan driver part SCD to the ON state. With this setting, the voltage Vs of the power source B 3  in the sustain driver part SUD is applied to the row electrodes Y via the capacitor C 11 , resistor R 12 , connection line  13 , and the switching element S 22 . Consequently, the voltage at the row electrodes Y gradually goes up from 0 volt as shown in FIG. 9. In this process, when the voltage at the row electrodes Y reaches the voltage Vs upon the lapse of a predetermined period after the switching element S 17  has been set to the ON state, the drive control circuit  50  sets the switching device S 22  to the OFF state, and the switching device S 21  to the ON state respectively. As a result, a current route CR 1  through the power source B 3 , switching element S 17 , capacitor C 11 , resistor R 12 , power source B 6 , switching element S 21 , and row electrodes Y is formed, so that a voltage formed by adding the voltage Vh of the power source B 6  on the above-described voltage Vs is applied to the row electrodes Y. In this state, the voltage at the row electrodes goes up at a rate slower than the rate before the voltage of the row electrodes reaches the voltage Vs, as shown in FIG. 9. When the voltage at the row electrodes Y reaches a voltage (Vs+Vh), the drive control circuit  50  turns OFF the switching elements S 17  and S 21  and turns ON the switching elements S 18  and S 22 , respectively. As a result, a current route CR 2  which includes the switching elements S 22 , S 18 , resistor R 2 , and diode D 7  is formed, so that the voltage at the row electrodes Y gradually decreases as shown in FIG. 9.  
         [0059]    By the sequential operations described above, a reset pulse RP Y  having a waveform illustrated in FIG. 9 is generated. Specifically, the voltage of the reset pulse PR Y  gradually goes up from 0 volt, the rate of the rise of the voltage becomes slower after the lapse of a predetermined period, and finally the voltage reaches the maximum voltage (Vs+Vh). The reset pulse having this waveform is applied to all of the row electrodes Y 1  through Yn.  
         [0060]    Furthermore, in the reset period shown in FIG. 9, during the period in which the switching element S 17  is set to the ON state, the drive control circuit  50  sets the switching element S 5  in the reset driver section RSD X  in the X row electrode driver  30  to the ON state. With this setting, the voltage (−Vr) at the negative terminal of the power source B 7  is applied to the row electrode X through the circuit made up of the switching element S 5 , capacitor C 4 , resistors R 41  and R 42 . In this process, the voltage at the row electrodes X gradually lowers from 0 volt as illustrated in FIG. 9. When the voltage at the row electrodes X reaches the above-described voltage (−Vr), the drive control circuit  50  turns OFF the switching element S 5 .  
         [0061]    By the sequential operations described above, the reset pulse RPx having the waveform shown in FIG. 9 is generated. Specifically, the voltage of the reset pulse RPx gradually lowers from 0 volt and reaches a minimum voltage (−Vr). The reset pulse RPx is applied to all of the row electrodes X 1  to X n .  
         [0062]    By the simultaneous application of the reset pulse RP Y  of the positive polarity and the reset pulse RP x  of the negative polarity, the reset discharge is generated in all of the discharge cells.  
         [0063]    In this process, owing to the application of the reset pulse RP Y  having the waveform shown in FIG. 9, a weak reset discharge having a low light emission intensity is repetitively generated even if the pulse voltage level is at a relatively low voltage level. By the repetitive generation of the reset discharge, it is possible to accumulate a sufficient amount of the wall charge in each of the discharge cells. Consequently, it is possible to use a driver of a low voltage resistance having a relatively low price as the driver for generating the reset pulse.  
         [0064]    In the embodiment shown in FIG. 9, the waveform of the falling edge of the reset pulse RP Y  is moderate. It is, however, possible to employ a reset pulse having a steep falling edge. For instance, instead of setting the switching element S 18  to the ON state, it is possible to set both of the switching elements S 14  and S 15  to the ON state. In this case, the waveform of the falling edge of the reset pulse RP Y  becomes such a waveform that it steeply varies to 0 volt from the maximum voltage (Vs+Vh).  
         [0065]    Next, the third embodiment of the invention will be explained with reference to the drawings.  
         [0066]    [0066]FIG. 10 shows an internal construction of each of an X row electrode driver  30  and a Y row electrode driver  40 ″ in the second embodiment. This construction is the same as the construction shown in FIG. 6 with the exception of the reset driver part RSD of the Y row electrode driver  40 ″, and the explanation will not be repeated.  
         [0067]    A switching device S 23  is disposed in the reset driver part RSD in addition to the switching device S 17 . The switching device  23  remains OFF while the driving control circuit  50  supplies thereto a switching signal SW 23  of the logic level 0. When the switching signal SW 23  has the logic level 1, on the other hand, the switching device S 23  is turned ON and connects the positive terminal of the power source B 3  to the connection line  13  through the resistor R 4 . In other words, the switching device S 23  applies the voltage Vs generated by the power source B 3  in accordance with the switching signal SW 23  to the connection line  13  through the resistor R 4 . Incidentally, the resistor R 4  has a resistance value higher than that of the resistor R 1 .  
         [0068]    Next, the operation in the construction described above will be explained with reference to a timing chart of FIG. 11. The sub-field SF 1  has a reset period, an address period and a sustain period in the same way as in FIG. 7. Only the reset period is different from FIG. 7. In the reset period, the driving control circuit  50  turns OFF the switching device S 14  of the sustain driver part SUD and turns ON the switching device S 15 . In this reset period, the driving control circuit  50  executes a first waveform generation step RS 1  for generating a leading edge portion of a reset pulse and a second waveform generation step RS 2  for generating a main body portion of the reset pulse. In the first waveform generation step RS 1 , the switching device S 23  of the reset driver part RSD is set to the OFF state and the switching device S 17 , to the ON state. In the second waveform generation step RS 2 , the switching device S 23  of the reset driver part RSD is set to the ON state and the switching device S 17 , to the OFF state. Further, in the first and second waveform generation steps RS 1  and RS 2 , the switching device S 21  of the scan driver part SCD is set to the ON state and the switching device S 22 , to the OFF state. Therefore, while the first and second waveform generation steps RS 1  and RS 2  are executed, the voltage V h  of the power source B 6  of the scan driver part SCD is applied to the row electrode Y and the current from the power source B 3  of the sustain driver part SUD flows into the discharge cells through the current path represented by CR 1  in FIG. 10.  
         [0069]    In this case, in the first waveform generation step RS 1 , the current from the power source B 3  flows into the discharge cells through the switching device S 17  and the resistor R 1 . Therefore, the voltage on the row electrode Y set to the voltage V h  gradually increases with inclination shown in FIG. 11 in accordance with the time constant (C 0 , R 1 ) of the PDP  10  determined by the load capacitance C 0  and the resistor R 1 . When the voltage of the row electrode Y exceeds the predetermined voltage Vc, the driving control circuit  50  shifts to the execution of the second waveform generation step RS 2 . Incidentally, the predetermined voltage Vc is a voltage slightly lower than the discharge start voltage of the discharge cells in the PDP  10 . In the second waveform generation step RS 2 , the current from the power source B 3  flows into the discharge cells through a current path of the switching device S 23  and the resistor R 4  instead of the switching device S 17  and the resistor R 1  described above. Consequently, the voltage on the row electrode Y gradually increases with inclination shown in FIG. 11 in accordance with the time constant (C 0 , R 2 ) of the PDP  10  determined by the load capacitance C 0  and the resistor R 2 . Since the resistor R 4  is higher than the resistor R 1  in this case, the rise of the voltage in the first waveform generation step RS 1  is sharper than the rise of the voltage in the second waveform generation circuit as shown in FIG. 11. When the voltage on the row electrode Y reaches the voltage (V s +V h ) generated by the series connection of the power source B 3  and the power source B 6 , the driving control circuit  50  switches both the switching devices S 23  and S 21  to the OFF state and the switching device S 22  to the ON state. Consequently, a current path of the switching devices S 22 , S 15  and S 14  (represented by CR 2  in FIG. 10) is formed, and the voltage on the row electrode Y immediately changes to 0 volt. When the first and second waveform generation steps RS 1  and RS 2  are executed, a reset pulse RP Y  the voltage level of which rises relatively sharply at the leading edge-and relatively gently thereafter and which reaches the highest pulse voltage value (V s +V h ) is generated, and this voltage is applied to all the row electrodes Y. In this process, when the voltage of the reset pulse RP y  exceeds the predetermined voltage Vc shown in FIG. 11, a first reset discharge (write discharge) is generated inside each discharge cell. Due to this first reset discharge, charge particles are generated inside the discharge space of each discharge cell and a predetermined amount of the wall charge is generated in the dielectric layer. Second reset discharge (erase discharge) is generated in all the discharge cells at the fall of the reset pulse RP y , and the wall charge disappears from inside all the discharge cells. In other words, all the discharge cells are initialized to the OFF mode due to the first and second reset discharges induced in accordance with the application of the reset pulse RP y .  
         [0070]    Taking variance of the discharge start voltage of each discharge cell formed in the PDP  10  into account, this embodiment generates the reset discharge by use of the reset pulse RP y  the voltage level of which changes gradually as shown in FIG. 11 and suppresses light emission brightness resulting from the reset discharge. In other words, when the reset pulse RP y  shown in FIG. 11 is applied, the voltage level on the row electrode Y gradually rises. In the execution period of the second waveform generation step RS 2 , the reset discharge is generated gradually from the discharge cell having a low discharge start voltage to the discharge cell having a high discharge start voltage. Therefore, in comparison with the case where all the discharge cells execute all at once the reset discharge, light emission brightness resulting from the reset discharge becomes lower. In this invention, the voltage level at the front edge of the reset pulse RP y , that is, the portion at which the voltage level exceeds the predetermined voltage Vc in FIG. 7 (first waveform generation step RS 1 ) shifts at this time more sharply than in the subsequent portion (second waveform generation portion RS 2 ). In other words, the level shift at the front edge of the reset pulse RP y  is sharp, the time till its voltage level reaches a voltage (predetermined voltage Vc) slightly lower than the lowest discharge start voltage that can be used as the discharge start voltage of each discharge cell can be shortened.  
         [0071]    Accordingly, the execution period of the second waveform generation step RS 2  can be elongated without expanding the pulse width of the reset pulse and the timing of the reset discharge induced in each discharge cell can be dispersed. Because the number of the reset discharge induced at the same timing can be reduced and light emission brightness resulting from the reset discharge can be lowered, the contrast of the screen can be enhanced.  
         [0072]    This application is based on Japanese Patent Applications Nos. 2002-310140, 2003-77872 and 2003-197005 which are herein incorporated by reference.