Abstract:
A charge pump includes first and second pairs of differential transistors. Each transistor includes control, first, and second terminals. First and second charge pump drivers communicate with the control terminal of one of the first pair of differential transistors and one of the second pair of differential transistors, respectively. Third and fourth charge pump drivers communicate with the control terminal of the other of the first pair of differential transistors and the other of the second pair of differential transistors, respectively. The first through fourth charge pump drivers include respective pairs of differential transistors that receive control signals from respective control circuits.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application claims the benefit of U.S. Provisional Application No. 60/470,745, filed on May 14, 2003, which is hereby incorporated by reference in its entirety. 

   FIELD OF THE INVENTION 
   The present invention relates to a phase-lock loops, and more particularly to charge pump drivers for phase-lock loops. 
   BACKGROUND OF THE INVENTION 
   High speed data communications channels typically lock onto a phase of a received data stream. The receiving device typically includes a phase-lock loop (PLL) circuit that locks onto the phase of the received data stream. For example, radio frequency (RF) communications channels are established by wireless communications devices in a wireless network. 
   Referring now to  FIG. 1 , an exemplary PLL  10  includes a phase detector (PD)  12 , a charge pump  14 , a loop filter  16 , a voltage controlled oscillator (VCO)  18 , and a frequency divider  20 . The VCO  18  generates an output signal that is divided by the frequency divider  20  and fed back to the PD  12 . The PD  12  detects a phase difference between a reference frequency signal  22  (such as the received data stream) and the feedback or divided output signal  24 . The PD  12  generates one or more phase difference signals  26 , for example signals  30  and  32 , that drive the charge pump  14 , as will be described below. 
   The charge pump  14  receives the phase difference signals  26  and generates an output signal that is used to adjust the output of the VCO  18 . The output signal may be a pulse width modulated current signal. Performance of the charge pump  14  is typically characterized by switching speed and phase offset. Phase offset refers to the voltage generated by the charge pump  14  when the phase of the reference signal  22  and the feedback signal  24  are the same. Ideally the phase offset of the charge pump  14  is zero. 
   The output of the charge pump  14  is filtered by the optional loop filter  16 . The loop filter  16  may include a capacitor-based integrating circuit, although other types of filters may be used. The desired frequency for the output signal  28  of the VCO  18  may be different than the frequency of the reference signal  22 . The frequency divider  20  adjusts the frequency of the output signal  28  based on the ratio of the desired output frequency to the reference frequency. 
   In some approaches, the phase difference signals  30  and  32  that are generated by the PD  12  are UP and DOWN signals, respectively. UP signals indicate positive differences between the reference signal and the output signal and DOWN signals represent negative differences. Additional details can be found in “Voltage Controlled Oscillator Formed of Two Differential Transconductors”, U.S. Pat. No. 5,635,879, to Sutardja et al., which is commonly assigned and which is hereby incorporated by reference in its entirety. 
   Referring now to  FIG. 2 , one exemplary charge pump  14  includes a first current source  40  and a second current source  42 . One end of the first current source  40  is connected to a first power supply  44  or V dd  and an opposite end is connected to transistors  46  and  48 . The transistor  46  selectively connects the first current source  40  to a reference node  50 . The transistor  48  selectively connects the first current source  40  to an output node  52 . The UP signal is applied to an inverter  70 , which has an output that communicates with a gate  84  of the transistor  46 . An inverted UP signal is applied to an inverter  72 , which has an output that communicates with a gate  86  of the transistor  48 . 
   A transistor  58  selectively connects the second current source  42  to the reference node  50 . A transistor  60  selectively connects the second current source  42  to the output node  52 . An inverted DOWN signal is applied to an inverter  74 , which has an output that communicates with a gate  88  of the transistor  58 . The DOWN signal is applied to an inverter  76 , which has an output that communicates with a gate  90  of the transistor  60 . The transistors  46  and  48  are switched in response to the UP and inverted UP signals. The transistors  58  and  60  are switched in response to the DOWN and the inverted DOWN signals. Typically, the inverters  70 ,  72 ,  74 , and  76  are biased between ground  80  and a supply voltage  82 . In this circuit, the gates  84 ,  86 ,  88 , and  90  are switched from rail to rail, which tends to increase charge injection and phase offset. 
   An alternative embodiment for driving a charge pump circuit is shown in  FIG. 3 . Inverters  100 ,  102 ,  104 , and  106  are biased between a fixed low voltage  108  and a fixed high voltage  110  rather than between supply voltage and ground. For example, the inverters  100 ,  102 ,  104 , and  106  may be biased by a fixed low voltage such as 1.0 volt and a fixed high voltage such as 1.5 volts for a voltage swing of 0.5 volts. 
   The circuit arrangement in  FIG. 3  reduces charge injection. However, the inverters  100 ,  102 ,  104 , and  106  do not receive the full range of the voltage supply, which reduces the switching speed of transistors  46 ,  48 ,  58 , and  60 . The switching speed is reduced because the PMOS transistors  46  and  48  do not have sufficient overdrive voltage to quickly charge the gate when switching to V high . Likewise, the NMOS transistors  58  and  60  typically do not have sufficient overdrive voltage to quickly discharge the gate to switch to V low . 
   SUMMARY OF THE INVENTION 
   A charge pump driver according to the present invention includes a first transistor with a control terminal and first and second terminals. A second transistor includes a control terminal and first and second terminals. The second terminal of the first transistor communicates with the first terminal of the second transistor. An AC coupling circuit has an output that communicates with the control terminals of the first and second transistors. A bias circuit biases the control terminals of the first and second transistors. 
   In other features, an inverter includes an input and an output. The output of the inverter communicates with an input of the AC coupling circuit. The AC coupling circuit includes a first capacitor having one end that communicates with the output of the inverter and an opposite end that communicates with the control terminal of the first transistor. A second capacitor has one end that communicates with the output of the inverter and an opposite end that communicates with the control terminal of the second transistor. 
   In other features, the first transistor is a PMOS transistor and the second transistor is an NMOS transistor. The inverter is biased by a first voltage potential and a ground potential. 
   In other features, a system comprises the charge pump driver and further comprises a charge pump including a third transistor having a control terminal that communicates with the second terminal of the first transistor and the first terminal of the second transistor. 
   In other features, the first terminal of the first transistor communicates with a first voltage potential and the second terminal of the second transistor communicates with a second voltage potential. 
   A charge pump according to the present invention includes a charge pump driver with an inverter that has an input and an output. The inverter is biased by a supply voltage potential and a ground potential. An overdrive circuit produces an overdrive voltage. A charge pump includes a first transistor having a control terminal that receives the overdrive voltage and first and second terminals. The overdrive voltage of the overdrive circuit is equal to a supply voltage minus a threshold voltage of the first transistor. 
   In other features, the overdrive circuit includes a second transistor including a control terminal and first and second terminals. A third transistor includes a control terminal and first and second terminals. The second terminal of the first transistor communicates with the first terminal of the second transistor. An AC coupling circuit has an input that communicates with the output of the inverter and an output that communicates with the control terminals of the second and third transistors. 
   In other features, a bias circuit biases the control terminals of the second and third transistors. The AC coupling circuit includes a first capacitor having one end that communicates with the output of the inverter and an opposite end that communicates with the control terminal of the second transistor. A second capacitor has one end that communicates with the output of the inverter and an opposite end that communicates with the control terminal of the third transistor. The second transistor is a PMOS transistor and the third transistor is an NMOS transistor. 
   A charge pump driver according to the present invention includes an AC coupling circuit and a pre-driver circuit that communicates with an output of the AC coupling circuit. A bias circuit biases first and second inputs of the pre-driver circuit. 
   In other features, the pre-driver circuit includes a first transistor including a control terminal and first and second terminals. A second transistor includes a control terminal and first and second terminals. The second terminal of the first transistor communicates with the first terminal of the second transistor. 
   In other features, an output of the AC coupling circuit communicates with the control terminals of the first and second transistors. An inverter has an output that communicates with an input of the AC coupling circuit. The AC coupling circuit includes a first capacitor having one end that communicates with the output of the inverter and an opposite end that communicates with a first input of the pre-driver circuit. A second capacitor has one end that communicates with the output of the inverter and an opposite end that communicates with a second input of the pre-driver circuit. 
   In other features, the first transistor is a PMOS transistor and the second transistor is an NMOS transistor. The inverter is biased by a first voltage potential and a ground potential. 
   Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein: 
       FIG. 1  is a functional block diagram of an exemplary phase-locked loop that includes a charge pump according to the prior art; 
       FIG. 2  is an electrical schematic of an exemplary charge pump that is driven by inverters that are biased by supply voltage and ground according to the prior art; 
       FIG. 3  is an electrical schematic of an alternative charge pump that is driven by inverters that are biased by high and low voltage potentials according to the prior art; 
       FIG. 4  is a functional block diagram of a charge pump driver according to the present invention; 
       FIGS. 5A and 5B  are electrical schematics of a charge pump driver according to the present invention in further detail; 
       FIG. 6  is a functional block diagram and electrical schematic of a charge pump including the charge pump drivers of  FIGS. 5A and 5B ; and 
       FIG. 7  is a functional block diagram of a wireless network device including a PLL circuit with a charge pump according to the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. 
   A charge pump driver according to the present invention provides improved switching speed with low phase offset. The charge pump driver uses a bootstrapping approach that increases the overdrive voltage without a corresponding increase in phase offset. Drive voltage is AC-coupled or “boot-strapped” to a transistor in the driver such that the gate voltage of the transistor can be higher than the supply voltage for the NMOS transistors in the charge pump. Also, the gate voltage can be lower than ground for the PMOS transistors in the charge pump. 
   Referring now to  FIG. 4 , a charge pump driver  130  according to the present invention includes an inverter  132  having an input that receives a phase difference signal. An output of the inverter  132  is input to an AC coupling circuit  134 . First and second outputs of the AC coupling circuit are input to a first and second inputs of a pre-driver or overdrive circuit  136 . A bias circuit  138  provides a bias signal to the first and second inputs of the pre-driver circuit  136 . The charge pump  130  increases the overdrive voltage output by the pre-driver circuit  136  to improve switching speed without increasing phase offset. 
   Referring now to  FIG. 5A , a charge pump driver  130 - 1  for PMOS transistors includes the inverter  132 , the AC coupling circuit  134  including a first capacitor  164  and a second capacitor  166 , the pre-driver  136  including a PMOS transistor  168  and an NMOS transistor  170 , and the bias circuit  138 . The inverter  132  receives one of the phase difference output signals at input  174  from the PD  12 . The inverter  132  is biased by ground  176  and a source voltage  178 . The inverter  132  generates a drive voltage  180  that is based on the phase difference signals  174 . 
   The drive voltage  180  is output to one end of the first capacitor  164  and one end of the second capacitor  166 . An opposite second end of the first capacitor  164  communicates with a gate  182  of the PMOS transistor  168 . An opposite end of the second capacitor  166  communicates with a gate  184  of the NMOS transistor  170 . A first output  186  of the bias circuit  138  communicates with the second end of the first capacitor  164  and the gate  182  of the PMOS transistor  168 . A second output  188  of the bias circuit  138  communicates with the second end of the second capacitor  166  and the gate  184  of the NMOS transistor  170 . The bias circuit  138  biases the gates  182  and  184  of the transistors  168  and  170 , respectively. The bias circuit sets the voltages of the transistors so that during operation, the switching on/off of the transistor is enabled. 
   A source terminal  190  of the PMOS transistor  168  communicates with voltage supply V p,high . A source terminal  192  of the NMOS transistor  170  communicates with voltage supply V p,low . A drain terminal  194  of the PMOS transistor  168  and a drain terminal  196  of the NMOS transistor  170  communicate with each other and with an output node  198 . In  FIG. 5B , a charge pump driver  130 - 2  for NMOS transistors is shown. The charge pump drivers  130 - 1  and  130 - 2  are similar except for biasing. The source  194  of the PMOS transistor  168  is biased by V n,high  and the source of the NMOS transistor  170  is biased by V n,low  instead of V p,high  and V p,low , respectively. Typical values for V n,high , V n,low , V p,high  and V p,low  will depend upon the process that is used. 
   Referring now to  FIG. 6 , a charge pump  220  includes the transistors  46  and  48 , the transistors  58  and  60 , the charge pump drivers  130 - 1 A and  130 - 1 B of  FIG. 5A , and the charge pump drivers  130 - 2 A and  130 - 2 B of  FIG. 5B . The charge pump driver  130 - 1 A AC-couples a drive voltage to the gate  84  of the PMOS transistor  46 . The charge pump driver  130 - 1 B AC-couples a drive voltage to the gate  86  of the transistor  48 . The charge pump driver  130 - 2 A AC-couples a drive voltage to the gate  88  of the transistor  58 . The charge pump driver  130 - 2 B AC-couples a drive voltage to the gate  90  of the NMOS transistor  60 . 
   A gate voltage of the transistors  58  and  60  can be higher than the supply voltage V dd . A gate voltage of the PMOS transistors  46  and  48  can be lower than ground. The overdrive voltage is given by V od =V dd −V th  for both the PMOS transistors  46  and  48  and the transistors  58  and  60 . V od  is the overdrive voltage, V dd  is the supply voltage, and V th  is a threshold voltage. The resulting increase in overdrive voltage decreases the rise and fall times of the transistors while limiting phase offset. The phase offset is not adversely impacted because the charge pump devices are switched with smaller voltages than the N-type switching device. Only the overdrive voltage to the switching devices are increased. 
   In the charge pump driver of  FIG. 3 , the overdrive voltage is given by:
 
 V   od,p   =V   high   −V   th,p ; and
 
 V   od,n   =V   supply   −V   low   −V   th,n .
 
In the charge pump driver of  FIGS. 4 ,  5  and  6 , the overdrive voltage V od =V supply −V th  for both the PMOS and NMOS transistors. Using typical values of V supply =3.0V, V high =1.8V (for PMOS) and V low =1.30V (for PMOS), the circuit in  FIG. 3  operates with the following overdrive voltages:
 
 V   od,p =1.8V−0.8V=1.0V for PMOS; and
 
 V   od,n =3.0V−1.00V−0.8V=1.2V for NMOS.
 
Using the approach depicted in  FIGS. 4 ,  5  and  6  and described above, the charge pump operates with significantly higher overdrive voltage:
 
 V   od,p =3.0V−0.8V=2.2V for PMOS; and
 
 V   od,n =3.0V−0.8V=2.2V for NMOS.
 
The increased overdrive voltage improves switching speed without a corresponding increase in phase offset. While MOS transistors are shown, skilled artisans will appreciate that other transistor types can be used without departing from the invention.
 
   Referring now to  FIG. 7 , the charge pump  220  with the charge pump drivers according to the present invention are implemented in a PLL circuit  250  of a wireless network device  260 . The wireless network device  260  is compliant with IEEE sections 802.11, 802.11a, 802.11b, 802.11g, 802.11n, 802.16, and/or other existing or future wireless standards. IEEE sections 802.11, 802.11a, 802.11b, 802.11g, 802.11n, 802.16 are hereby incorporated by reference in their entirety. 
   Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.