Abstract:
A battery equalization circuit for equalizing charge between at least first and second series-connected batteries, where each battery has a positive end and a negative end, with the positive end of the second battery coupled to the negative end of the first battery at a common node, and using: a switching circuit connectable to the positive end of the first battery at a positive node and the negative end of the second battery at a negative node; a transformer having first and second magnetically coupled windings, each with a first end defining a polarity of the winding and a second opposing end; and a transformer reset circuit coupled from the windings of the transformer to the positive and negative nodes. The switching circuit acts to simultaneously couple the first and second windings in parallel with the first and second batteries, respectively, in the same polarity such that a charge is transferred between the first and second batteries as a function of a charge imbalance therebetween. The transformer reset circuit couples one of the first and second windings in parallel with one of the first and second batteries in an opposite polarity to direct reset current from the transformer to that battery to decrease the charge imbalance therebetween.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to battery equalization techniques and, more particularly, to magnetically-coupled battery equalization apparatus suitable for autonomous connection to batteries. 
     2. Related Art 
     To generate higher voltage than available from a single battery, plural batteries are typically connected in series such that a relatively large total voltage is available to drive a load. As it is desirable to utilize rechargeable batteries, battery charger circuits have been developed which charge all of the batteries in a series string at one time. 
     Care must be taken to fully charge each battery in the series string without one battery being at a higher state of charge than another battery. If a difference exists between a relatively low charge on one battery with respect to the other batteries in the series, the total effective capacity of the series string of batteries is reduced to the capacity of the battery having the low state of charge. 
     Battery equalization circuits have been developed to ensure that all batteries in a series string attain substantially the same state of charge. U.S. Pat. No. 5,479,083 to Brainard illustrates a conventional battery equalization circuit which includes a pair of series-coupled transistors connected across a pair of series-coupled batteries. An inductor L is connected between the pair of transistors and the batteries. An oscillator produces gate drive signals to the transistors such that they are alternately biased on and off for substantially equal durations. The inductor operates as a non-dissipative shunt that is alternately switched in parallel with each battery such that excessive charge on one battery is transferred to the other battery. Unfortunately, component tolerances within the Brainard equalization circuit will effect the degree of equalization achieved between the batteries, particularly tolerances which effect the duty cycle of the oscillator and the resultant duty cycle presented by the transistors to the batteries. Therefore, in order to obtain satisfactory equalization, measurements of the charge on each battery must be obtained and fed-back to the oscillator to change the duty cycle as necessary (see FIG. 3 of the Brainard patent). 
     U.S. Pat. No. 5,710,504 to Pascual discloses a battery equalization circuit which does not require a feedback mechanism from each battery to achieve adequate equalization. However, the circuit of the Pascual patent requires that all switching devices within the circuit be synchronized, no matter how many batteries are in the series combination. When the number of series-coupled batteries is relatively high and results in a high terminal voltage from the uppermost battery to the lowermost battery, the topology of the Pascual circuit may result in undesirable fault conditions. 
     Turning to FIG. 1 of the Pascual patent, a plurality of series-coupled batteries are shown; all switches 16 are synchronized via control lines 18 and control unit 12. Assuming that the total voltage from the uppermost battery to the lowermost battery is substantially large (e.g., 600 volts), a practical circuit must be designed to withstand a fault from the uppermost battery terminal to the lowermost battery terminal through the wiring of the equalization circuit. Often, the series coupled batteries may deliver many amps (approaching 1000 amps or more) making it difficult to design for surviving a fault and not damaging any of the batteries. 
     U.S. Pat. No. 5,821,729 to Schmidt discloses a method and apparatus for exchanging charge between a plurality of batteries, where transformer windings are connected in parallel with each battery at predetermined time intervals. Each battery is simultaneously connected to a respective one of the windings in the same winding sense. Unfortunately, the Schmidt apparatus requires precise timing of switching elements which connect the windings to the respective batteries. Indeed, if the timing of the switching elements is not tightly controlled, the common magnetic core of the transformer windings will saturate. 
     Accordingly, there is a need in the art for a new battery equalization circuit which is capable of autonomous operation (i.e., not requiring synchronization with other equalization circuits servicing the series-coupled batteries) and does not require closed loop compensation or overly complex control circuitry to achieve satisfactory equalization. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, to overcome the disadvantages of the prior art, a battery equalization circuit is provided for equalizing charge between at least first and second series-connected batteries, with each battery including a positive end and a negative end, where the positive end of the second battery is coupled to the negative end of the first battery at a common node. The battery equalization circuit of the present invention comprises: a switching circuit connectable to (i) the positive end of the first battery at a positive node, and (ii) the negative end of the second battery at a negative node; a transformer having first and second magnetically coupled windings, each winding having a first end defining a polarity of the winding and a second opposing end; and a transformer reset circuit coupled from the windings of the transformer to the positive and negative nodes, the switching circuit being operable to simultaneously couple the first and second windings in parallel with the first and second batteries, respectively, in the same polarity such that a charge is transferred between the first and second batteries as a function of a charge imbalance therebetween, and the transformer reset circuit being operable to couple one of the first and second windings in parallel with one of the first and second batteries in an opposite polarity to direct reset current from the transformer to that battery to decrease the charge imbalance therebetween. 
     According to another aspect of the invention, the battery equalization circuit includes a first switching transistor connectable at one end to the positive end of the first battery at a positive node; a second switching transistor connectable at one end to the negative end of the second battery at a negative node; a transformer having first and second magnetically coupled windings, each winding having a first end defining a polarity of the winding and a second opposing end such that: (i) the first end of the first winding is coupled to an opposing end of the first switching transistor, (ii) the second end of the second winding is coupled to an opposing end of the second switching transistor, and (iii) the second end of the first winding is coupled to the first end of the second winding; a first diode having an anode coupled to the second end of the second winding and a cathode coupled to the positive node; a second diode having an anode coupled from the negative node and a cathode coupled to the first end of the first winding; and a drive circuit operable to bias the switching transistors ON and OFF substantially simultaneously at ON and OFF times, respectively, and at a duty cycle of less than about 50%. 
     The invention further provides a method of equalizing charge between the first and second series connected batteries, by using the steps of: simultaneously connecting a different one of first and second magnetically coupled windings of a transformer in parallel with an associated one of the first and second batteries, respectively, in the same polarity such that that one of the first and second batteries having greater charge drives a current into a corresponding one of the first and second windings, to cause an induced current to flow out of the other of the first and second windings and into the other one of the first and second batteries having a lesser charge, such that charge between the first and second batteries tends to equalize; simultaneously disconnecting the first and second windings of the transformer from the first and second batteries; and providing a current path for a reset current to flow through the corresponding one of the first and second windings and into the other of the first and second batteries having lesser charge such that charge between the first and second batteries tends to equalize. 
     According to still another aspect of the invention, the battery equalization circuit includes: a transformer having first and second magnetically coupled windings, each winding having a first end defining a polarity of the winding and a second opposing end; a first capacitor; a transformer reset circuit coupled from the first winding of the transformer to the positive node; and a switching circuit operable during ON times to (i) simultaneously couple the first and second windings in parallel with the first and second batteries, respectively, in the same polarity; and (ii) couple the first capacitor in parallel with the first winding. 
     According to a further aspect of the invention, the battery equalization circuit includes: a transformer having first and second magnetically coupled windings, each winding having a first end defining a polarity of the winding and a second opposing end; a first capacitor; a second capacitor coupled from the positive node to the common node; a transformer reset circuit coupled from the first winding of the transformer to the positive node; and a switching circuit operable during ON times to (i) simultaneously couple the first and second windings in parallel with the first and second batteries, respectively, in the same polarity; and (ii) couple the first capacitor in parallel with the first winding. 
    
    
     Other objects, features, and advantages of the present invention will now become apparent to those skilled in the art upon reading the teachings herein, when taken in conjunction with the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For the purposes of illustrating the invention, there are shown in drawing forms which are presently preferred, it being understood, however, that the present invention is not limited to the precise arrangements and instrumentalities shown. 
     FIG. 1 is a battery equalization circuit schematic according to one aspect of the present invention; 
     FIG. 2 is a more detailed schematic of the charge equalization circuit of FIG. 1; 
     FIG. 3 is a battery equalization circuit schematic according to another aspect of the present invention; 
     FIG. 4 is a graph illustrating comparisons of equalization current magnitudes which are achievable in the circuits of FIGS. 1 and 3; 
     FIG. 5 is an alternative embodiment of the battery equalization circuit of FIG. 3; and 
     FIG. 6 is a more detailed schematic of the charge equalization circuit of FIG.  5 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     With reference to the accompanying drawing, wherein like numerals indicate like elements, there is shown in FIG. 1 a circuit diagram illustrating a charge equalization circuit  100  according to one aspect of the present invention. 
     The charge equalization circuit  100  is operable to equalize the charge contained on respective series-coupled batteries  102  and  104 . Battery  102  includes a positive end coupled to positive node  106  and a negative end coupled to a common node  110 . Battery  104  includes a positive end coupled to common node  110  and a negative end coupled to negative node  108 . 
     Those skilled in the art will appreciate that the charge equalization circuit  100  of the present invention need not operate with two completely-independent batteries, such as separate batteries  102  and  104 , but may also operate with the individual cells within a particular single battery unit. In such a case, battery  102  and battery  104  may be thought of as individual series-coupled cells within one battery unit. 
     The charge equalization circuit  100  according to the present invention includes a switching circuit  112  connectable to the series coupled batteries  102 ,  104  by way of the positive node  106  and the negative node  108 . The charge equalization circuit  100  also includes a transformer T 1 , a transformer-reset circuit  114 , and a gate drive circuit  116 . The transformer T 1  includes an upper winding  118  and a lower winding  120  wound on a common core. Each winding  118 ,  120  includes an end shown with a dot to indicate the polarity (or sense) associated with that winding. 
     The switching circuit  112  preferably includes upper and lower switching transistors Q 1 , Q 2  each having a controlled-conduction circuit (e.g. the source-drain circuit) coupled series with an associated one of the upper and lower windings  118 ,  120  of transformer T 1 . Transistors Q 1 , Q 2  are preferably MOSFET devices; however, those skilled in the art will understand that other types of switching transistors may be utilized without departing from the scope of the invention. A drain of transistor Q 1  is connected to positive node  106 , while a source of transistor Q 1  is connected to one end of upper winding  118 . A source of transistor Q 2  is coupled to negative node  108 , while a drain of transistor Q 2  is coupled to a lower end of lower winding  120 . Upper and lower windings  118 ,  120  are connected together at common nod  110 . 
     The gate drive circuit  116  includes two outputs, each output for biasing a respective one of transistors Q 1  and Q 2  on and off at a selected duty cycle. It is preferred that this duty cycle be less than about 50% to ensure that transformer TI will not saturate. Indeed, the circuit is fully operational for any duty cycle of less than 50% (e.g. duty cycles of 10%, 20% or 49% are all usable). 
     The transformer reset circuit  114  is coupled from the windings  118 ,  120  of the transformer TI to the positive and negative nodes  106 ,  108 . Reset circuit  114  preferably includes a pair of diodes D 1 , D 2 . The anode of diode D 1  is connected to the junction of lower winding  120  and the drain of switching transistor Q 2 , while its cathode is connected to positive node  106 . The anode of diode D 2  is coupled to negative node  108 , and its cathode is connected to the junction of the source of transistor Q 1  and upper winding  118 . 
     The switching circuit  112  is preferably operable to substantially simultaneously couple the upper and lower windings  118 ,  120  in parallel with the upper and lower batteries  102 ,  104 , respectively, in the same polarity (i.e., with the dot of each winding connected to a positive end of the respective battery). In other words, gate drive circuit  116  simultaneously turns on transistors Q 1  and Q 2 : conduction of transistor Q 1  causes upper winding  118  to be connected in parallel with upper battery  102  such that the dot end of upper winding  118  is connected to the positive end of upper battery  102 ; and, substantially simultaneously, conduction of transistor Q 2  causes lower winding  120  to be connected in parallel with lower battery  104  with the dot end of lower winding  120  connected to the positive end of lower battery  104 . 
     When transistors Q 1  and Q 2  are ON (i.e., during an ON time), upper battery  102  and lower battery  104  respectively attempt to drive current into upper winding  118  and lower winding  120 , respectively. Assuming, for example, upper battery  102  has a higher charge (i.e., a higher voltage potential), a current will flow from the positive end of upper battery  102 , through transistor Q 1 , into upper winding  118 , and back into the negative end of upper battery  102 . Lower battery  104 , therefore, will not be able to oppose an induced current flowing out of the dot end of lower winding  120  and into the positive end of lower battery  104 . This effectively transfers charge from upper battery  102  to lower battery  104  during,ON times. Those skilled in the art will appreciate that if lower battery  104  had a greater charge than upper battery  102 , then the current flow directions would be opposite in upper and lower windings  118 ,  120  of transformer T 1  and an induced current would flow into the positive terminal of upper battery  102  in response to a drive current flowing out of the positive end of lower battery  104  into the dot end of lower winding  120 . 
     Assuming, again, that upper battery  102  has a greater charge than lower battery  104 , during the ON times of switching circuit  112 , the drive current flowing from battery  102  into the dot end of upper winding  118  charges the magnetizing inductance of transformer T 1 , thereby storing energy in transformer T 1 . When the gate drive circuit  116  biases transistors Q 1  and Q 2  OFF (i.e., during OFF times), the transformer reset circuit  114  is preferably operable to directly reset current (i.e., current induced by a collapsing magnetic field in the core of transformer T 1 ) to the battery having a lower charge, here, lower battery  104 . In particular, reset current will flow out of the lower end of upper winding  118  of transformer T 1  into the positive end of lower battery  104 , through diode D 2  and back into the dot end of upper winding  118 . In effect, during the OFF time, the transformer reset circuit  114  is operable to couple the lower battery  104  in parallel with upper winding  118  in an opposite polarity than during the ON time. Advantageously, the reset current is used to equalize charge between upper battery  102  and lower battery  104  during OFF times. 
     Those skilled in the art will appreciate that reset current will be directed into each of upper and lower batteries  102  and  104  via diode D 1  and D 2  when upper and lower batteries  102  and  104  have substantially the same charge (i.e., when they are equalized). 
     Reference is now made to FIG. 2 which is a more detailed schematic of the charge equalization circuit  100  of FIG.  1 . Those skilled in the art will appreciate that the particular components of FIG. 2 are shown by way of example only and that many other modifications and variations may be made in the circuit without departing from the scope of the invention. 
     Reference is now made to FIG. 3, which illustrates a charge equalization circuit  200  in accordance with another aspect of the present invention. The charge equalization circuit  200  is connectable to a series-coupled pair of batteries including an upper battery  202  and a lower battery  204  at positive, negative, and common nodes  206 ,  208 , and  210 , respectively. The charge equalization circuit includes a switching circuit  212 , a transformer T 1 , a transformer reset circuit  214 , and a gate drive circuit  216 . 
     Each of upper and lower windings  218 ,  220  of transformer T 1  are shown with a parasitic leakage inductance (L leak ) connected in series therewith. Those skilled in the art will appreciate that, in a practical transformer, any leakage inductance is a non-ideal circuit element and generally results in reduced circuit performance. In the case of charge equalization circuits utilizing transformers, leakage inductance generally limits the magnitude of current and charge which may be drawn from one battery and delivered to another battery. Indeed, the drive current from the battery having greater charge is limited by the combined impedance of that battery, the transformer winding, the switching circuit, and impedance of other circuit components reflected by way of transformer action. 
     Unfortunately, the parasitic leakage inductance cannot be reduced without corresponding negative effects in the transformer, such as reducing the magnetizing inductance and increasing magnetizing energy. Prior art methods of reducing leakage inductance without corresponding reductions in magnetizing inductance (and increases in magnetizing energy) have focused on improving the magnetizing inductance-to-leakage inductance ratio of the transformer by complex winding configurations, such as the use of coaxial windings. 
     The switching circuit  212  preferably includes upper and lower switching transistors Q 1 , Q 2  coupled in series with the upper and lower windings  218 ,  220  of transformer T 1 . Transistors Q 1 , Q 2  are preferably MOSFET devices; however, those skilled in the art will understand that other types of switching transistors may be utilized without departing from the scope of the invention. The switching circuit  212  is preferably operable to simultaneously couple the upper and lower windings  218 ,  220  (and associated leakage inductances) in parallel with the upper and lower batteries  202 ,  204 , respectively in the same polarity. Transistor Q 2  is connected in substantially the same way to transformer T 1  and lower battery  204  as in the equalization circuit  100  of FIG.  1 . Transistor Q 1 , however, is connected between upper and lower windings  218 ,  220  with the drain connected to a lower end of upper winding  218  and the source coupled toward the dot end of lower winding  220 , it being understood that the leakage inductance is distributed throughout the lower winding  220 . The dot end of upper winding  218  is coupled to the positive node  206 , and to the positive end of upper battery  202  when upper battery  202  is connected to the equalization circuit  200 . 
     An upper capacitor C 1  is connected from the positive node  206  to the junction of: (i) the source of transistor Q 1 ; (ii) the dot end of lower winding  220 ; and (iii) the common node  210 . Those skilled in the art will appreciate that upper capacitor C 1  is effectively connected in parallel with upper battery  202 . A lower capacitor C 2  is connected from the junction of upper winding  218  and the drain of transistor Q 1  to the junction of lower winding  220  and the drain of transistor Q 2 . 
     Preferably, the transformer reset circuit  214  includes a diode D 1  having an anode connected to the junction of lower winding  220 , capacitor C 2  and the drain of transistor Q 2 . The diode D 1  also includes a cathode coupled to positive node  206 . 
     The gate drive circuit  216  is preferably operable to bias transistors Q 1  and Q 2  (i) ON substantially simultaneously during ON times; and (ii) OFF substantially simultaneously during OFF times. When transistors Q 1  and Q 2  are ON, the upper and lower windings  218 ,  220  are coupled in parallel with upper and lower batteries  202 ,  204 , respectively. Further, lower capacitor C 2  is coupled in parallel with lower battery  204 . Thus, upper capacitor C 1  and lower capacitor C 2  will charge or discharge such that their terminal voltages match the respective voltages of batteries  202  and  204 . When transistors Q 1  and Q 2  are ON (i.e., during an ON time), upper battery  202  and lower battery  204  attempt to drive current into upper winding  218  and lower winding  220 , respectively. Assuming, for example, upper battery  202  has a higher charge (i.e., a higher voltage potential thereacross), a current will flow from the positive end of upper battery  202 , into upper winding  218 , through transistor Q 1 , and back into a negative end of upper battery  202 . Lower battery  204 , therefore, will not be able to oppose an induced current flowing out of the dot end of lower winding  220  and into the positive end of lower battery  204 . This effectively transfers charge from upper battery  202  to lower battery  204  during ON times. Those skilled in the art will appreciate that if lower battery  204  had a greater charge than upper battery  202 , then the current flow directions would be opposite in upper and lower windings  218 ,  220  of transformer T 1  and an induced current would flow into the positive terminal of upper battery  202  in response to a drive current flowing out of the positive end of lower battery  204  into the dot end of lower winding  220 . 
     Assuming that the upper battery  202  has a greater charge than the lower battery  204 , the respective magnitudes of the current driven by upper battery  202  into upper winding  218  is a function of: (i) the combined impedances of upper battery  202 , upper winding  218  (including leakage inductance), and the impedance of transistor Q 1 ; and (ii) the reflected parallel combination of impedances of lower battery  204 , lower winding  220 , and lower capacitor C 2 . Advantageously, lower capacitor C 2  is effectively in parallel with lower winding  220  (and its leakage inductance) during the ON times of the switching circuit  212  and, therefore, reduces the impedance reflected to upper winding  218 . Consequently, the magnitude of the drive current from upper battery  202  into upper winding  218  is higher than it would be without lower capacitor C 2 . 
     Again, assuming upper battery  202  has a higher charge than lower battery  204 , when the gate drive circuit  216  substantially simultaneously disconnects upper and lower windings  218 ,  220  from upper and lower batteries  202 ,  204 , respectively (i.e., during OFF times), the transformer reset circuit  214  is preferably operable to provide a current path for a reset current to flow into the dot end of upper winding  218 , through capacitor C 2 , and through diode D 1 . This charges capacitor C 2  with the energy stored in the transformer T 1  during the ON time. Thus, when gate drive circuit  216  turns ON transistors Q 1  and Q 2 , thereby coupling capacitor C 2  in parallel with lower battery  204 , the elevated charge on capacitor C 2  from the reset current charges lower battery  204 , thereby tending to equalize batteries  202  and  204 . 
     When lower battery  204  has a greater charge than upper battery  202 , during ON times lower battery  204  drives current into the dot end of lower winding  220  such that an induced current flows out of the dot end of upper winding  218  and into at least one of: (i) upper capacitor C 1 ; and (ii) upper battery  202 , thereby tending to equalize the charge on upper and lower batteries  202 ,  204 . 
     When the switching circuit  216  turns transistors Q 1  and Q 2  OFF, the transformer reset circuit  214  is preferably operable to provide a current path for a reset current to flow into the dot end of lower winding  220 , through diode D 1  and into at least one of: (i) capacitor C 1 ; and (ii) upper battery  202 , thereby tending to equalize the charges on upper and lower batteries  202  and  204  during OFF times. Those skilled in the art will appreciate that any charge transferred to upper capacitor C 1  via the reset current would eventually be transferred to upper battery  202  to the extent that the terminal voltage across upper capacitor C 1  exceeded the voltage of upper battery  202 . 
     Referring now to FIG. 4, the magnitude of the equalizing current versus voltage differences between upper and lower batteries  202 ,  204  is shown under the following conditions: (i) without leakage inductance (i.e., an ideal condition); (ii) with leakage inductance and no compensating circuitry (i.e., the circuit of FIG.  1 ); and (iii) with leakage inductance and the circuit of FIG.  3 . Advantageously, the magnitude of equalizing currents flowing in the circuit of FIG.  3 . are substantially greater than those flowing in the circuit of FIG.  1 . Therefore, equalization as between upper and lower batteries  202 ,  204  may be more quickly achieved using the circuit of FIG.  3 . 
     Referring now to FIG. 5, an alternative embodiment of the equalizer circuit  200  of FIG. 3, is shown. The equalizer circuit  200  of FIG. 5 is substantially similar to the circuit of FIG. 3 with the exception that upper capacitor C 1  is not utilized. The operation of the circuit of FIG. 5 is substantially similar to the operation of the circuit of FIG. 3 except that neither induced currents, reset currents, nor charging currents flow through capacitor C 1 . The charging and/or discharging of capacitor C 2 , however, is the same as in the circuit of FIG.  3 . 
     Reference is now made to FIG. 6, in which is illustrated a more detailed schematic diagram for implementing the equalization circuit  200  of FIG.  5 . Those skilled in the art will appreciate that the particular circuit components and configurations are shown by way of example only and that many modifications and variations may be made without departing from the scope of the invention. 
     It is most preferred that the charge equalization circuit of the present invention be implemented on a circuit card which is disposed proximate to batteries  102  and  104 . When the number of batteries exceeds 2, for example, 3, 4, 5, 6 etc., one charge equalization circuit  300  may be employed for each pair of batteries. 
     Advantageously, no synchronization or other control signals need be shared between charge equalization circuits for other pairs of batteries (i.e., each charge equalization circuit is autonomous). The charge equalization circuits are thus distributed at the batteries for most convenient and safe operation. 
     Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.