Abstract:
A semiconductor memory comprises a p-type silicon substrate including a first diffused layer and a second diffused layer, and a gate insulation film in which carries are trapped in different areas. A first voltage and a second voltage are applied to the p-type silicon substrate and the gate electrode, respectively, to allow tunnel current to flow between the p-type silicon substrate and the gate electrode so that the tunnel current may eliminate the carries trapped in the gate insulation film. This allows all the electrons captured in the central portion of the channel area to disappear, resulting in more reliable data erasure.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]    This is a continuation of Application PCT/JP00/03467, filed May 30, 2000, now abandoned. 
     
    
     
       TECHNICAL FIELD  
         [0002]    The present invention relates to a semiconductor memory and its usage and it is more useful in recording 2-bit information in one memory cell in a nonvolatile semiconductor memory.  
         BACKGROUND ART  
         [0003]    In recent years, the nonvolatile semiconductor memory capable of recording 2-bit information in one memory cell by arranging the carrier injection position have been studied and developed. This nonvolatile semiconductor memory is so characterized that carriers are trapped in a gate insulation film formed below the gate. The direction of a voltage applied between a source and a drain is reversed depending upon a write or read mode of information. Electrons are therefore independently captured, in the gate insulation film, at positions corresponding to the two ends of a channel area. Accordingly, the 2-bit information can be recorded depending on whether electrons are captured or not at the two ends.  
           [0004]    For example, International Patent Laid-Open No. WO 99/07000 discloses a nonvolatile semiconductor memory having this structure. The structure of and the data write/erase processing in a nonvolatile semiconductor memory taught in this document will be briefly described with reference to FIGS. 5A to  5 D.  
           [0005]    As shown in FIGS. 5A to  5 D, a nonvolatile semiconductor memory  100  comprises first and second diffused layers  102  and  103  functioning as a source drain formed in the surface area of a p-type silicon substrate  101 , a gate insulation film  104  including a carrier trap area  104   a  formed on the p-type silicon substrate  101  almost between the first and second diffused layers  102  and  103 , and a gate electrode  105  formed on the gate insulation film  104 . The carrier trap area  104   a  includes a silicon nitride film or the like, and exhibits a higher carrier trap characteristic than that of the other areas within the gate insulation film  104 .  
           [0006]    In this nonvolatile semiconductor memory  100 , electrons are captured independently at areas  106  and  107  which correspond to two ends of the channel area in the gate insulation film  104 , so that a 2-bit information can be finally recorded.  
           [0007]    [0007]FIG. 5A shows a state wherein the electrons are not captured yet in the gate insulation film  104 . This state of the memory cell (threshold voltage: V th )defines a “Erase State”. When 0 (zero) V to the first diffused layer  102 , nearly 5 V to the diffused second layer, and 10 V to the gate electrode  105  in this memory cell are applied respectively, hot electrons are generated near the second diffused layer  103 , the electrons are captured in the area  106  in the gate insulation film  104  near the second diffused layer  103 , and the memory cell shift to a programmed state.  
           [0008]    To capture electrons in the other area  107 , the programming voltages applied to the first and second diffused layers  102  and  103  are switched; or 5 V to the first diffused layer  102 , 0 (zero) V to the second diffused layer  103 , and 10 V to the gate electrode  105  are applied respectively. Then, the electrons are captured in both areas  106  and  107 , as shown in FIG. 5B.  
           [0009]    To electrically return the state (programmed state) wherein electrons are locally captured in the areas  106  and  107 , as shown in FIG. 5B, to the erase state shown in FIG. 5A, +5 V to the first and second diffused layers  102  and  103  and −5 V to the gate electrode  105  are applied, respectively. In this case, electrons captured in the gate insulation film  104  near the first and second diffused layers  102  and  103  are neutralized by hot holes locally generated near the first and second diffused layers  102  and  103 . Thus, the stored data in the programmed state can be erased.  
           [0010]    However, if the electrons captured in the gate insulation film  104  diffusely exist in the lateral direction (along the first and second diffused layers  102  and  103  in FIG. 5C) due to repulsion against each other, disturbance in the read mode, as shown in FIG. 5C, it is difficult to completely erase the electrons in all the area. Especially when the write and read modes are repeated, the electrons remain at the center of the channel area in the gate insulation film  104  and they are gradually accumulated.  
           [0011]    In the erase processing under the above-described voltage conditions, only electrons captured near the first and second diffused layers  102  and  103  may be neutralized, because the captured electrons are neutralized by injecting into the gate insulation film  104  hot holes generated near the first and second diffused layers  102  and  103 . Therefore, in the erase processing under the above-described voltage conditions, the electrons remained near the center of the channel cannot be neutralized nor erased.  
           [0012]    The electrons, which cannot be erased and remained near the center of the channel in the gate insulation film  104 , causes an increase of the threshold voltage (V) for the memory cell, so the memory cell state shown in FIG. 5B cannot be discriminated against that shown in FIG. 5D. In the memory cell state shown in FIG. 5D, the capture state of the electrons in the area  106  or  107  can not be confirmed to thereby lower the writing reliability.  
           [0013]    The present invention has been made to overcome the conventional drawbacks, and has as its object to provide a semiconductor memory capable of reliably erasing captured electrons even when the electrons captured in a gate insulation film of a memory cell diffuse laterally, and its usage based on a characteristic erase algorithm for erasing captured electrons to thereby increase the data write/erase reliability.  
         SUMMARY OF THE INVENTION  
         [0014]    According to the present invention, there is provided a semiconductor memory which has a pair of impurity-diffused layers formed in a surface area of a semiconductor substrate, and a gate electrode formed on a gate insulation film on the semiconductor substrate between the pair of impurity-diffused layers, to thereby traps carriers at different positions in the gate insulation film by applying a predetermined voltage to the gate electrode, and wherein a tunnel current is supplied between the semiconductor substrate and the gate electrode by applying a first voltage to the semiconductor substrate including the pair of impurity-diffused layers and applying a second voltage to the gate electrode, and the tunnel current erases the carriers trapped in the gate insulation film.  
           [0015]    According to the present invention, there is provided a usage of a semiconductor memory which has a pair of impurity-diffused layers formed in a surface area of a semiconductor substrate, and a gate electrode formed on a gate insulation film on the semiconductor substrate between the pair of impurity-diffused layers, to thereby trap carriers at different positions in the gate insulation film by applying a predetermined voltage to the gate electrode, comprising the steps of: supplying a tunnel current between the semiconductor substrate and the gate electrode by applying a first voltage to the semiconductor substrate including the pair of impurity-diffused layers and applying a second voltage to the gate electrode, and erasing the carriers trapped in the gate insulation film by the tunnel current.  
           [0016]    The present invention is realized by the above technique. By supplying a tunnel current between the semiconductor substrate and the gate electrode, electrons in the entire area of the gate insulation film can be reliably erased regardless of the position where electrons are captured in the gate insulation film. Hence, electrons remaining near the center of the channel area, which are particularly difficult to erase, can be reliably erased.  
           [0017]    The present invention can surely erase electrons without leaving them near the center of the channel area in a semiconductor memory in which electrons are captured in an insulation film having a carrier trap area. The present invention can therefore provide a semiconductor memory which increases the reliability by reliably erasing electrons. 
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0018]    [0018]FIGS. 1A and 1B are schematic views showing the planar arrangement of a semiconductor memory according to first and second embodiments of the present invention;  
         [0019]    [0019]FIGS. 2A to  2 C are schematic sectional views showing the structure of each memory cell in the semiconductor memory according to the first embodiment of the present invention;  
         [0020]    [0020]FIG. 3 is a flow chart showing the procedures of erasing electrons accumulated in the memory cell of the semiconductor memory according to each embodiment of the present invention;  
         [0021]    [0021]FIGS. 4A to  4 C are schematic sectional views showing the structure of each memory cell in the semiconductor memory according to the second embodiment of the present invention; and  
         [0022]    [0022]FIGS. 5A to  5 D are schematic sectional views showing the structure of a memory cell in a conventional semiconductor memory.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0023]    (First Embodiment)  
         [0024]    A first embodiment of the present invention will be described with reference to the accompanying drawings. FIGS. 1A and 1B are schematic views showing the planar arrangement of a semiconductor memory according to the first embodiment. FIGS. 2A to  2 C are schematic sectional views showing the structure of each memory cell in the semiconductor memory according to the first embodiment.  
         [0025]    As shown in FIG. 1A, the semiconductor memory of the first embodiment has a cell array  1 , control gates  2  each connected to the memory cells aligned in the cell array  1 , and a control circuit  3  including an erase circuit connected to the control gates  2 .  
         [0026]    [0026]FIG. 1B is a schematic view of four memory cells  4   a  to  4   d  in the cell array  1  for an explanatory purpose of the circuit arrangement. The memory cells  4   a  to  4   d  each are connected to control gates  2   a  and  2   b , wherein the memory cells  4   a  and  4   b  are connected to the control gate  2   a , whereas the memory cells  4   c  and  4   d  are connected to the control gate  2   b.    
         [0027]    The memory cells  4   a  to  4   d  are connected to source/drain (S/D) lines  5   a  to  5   d  which run in the column direction. The memory cells  4   a  and  4   c  are connected to the source/drain (S/D) lines  5   a  and  5   b , while the memory cells  4   b  and  4   d  are connected to the source/drain (S/D) lines  5   c  and  5   d.    
         [0028]    The primary structure of each of the memory cells  4   a  to  4   d  in the first embodiment is the same as that of the memory cells in the conventional semiconductor memory described with reference to FIGS. 5A to  5 D. FIGS. 2A to  2 C typically show the structure of the memory cell  4   a  out of the memory cells  4   a  to  4   d . The remaining memory cells are also the same in arrangement as the memory cell  4   a . The memory cell  4   a  comprises first and second diffused layers  12  and  13  formed in the surface area of a p-type silicon substrate  11 , a gate insulation film  14  including a carrier trap area  14   a  formed on the p-type silicon substrate  11 , and the control gate  2   a  formed on the gate insulation film  14 .  
         [0029]    As shown in FIG. 1A, the control gate  2   a  is connected to the control circuit  3 . The first and second diffused layers  12  and  13  are respectively connected to the source/drain lines  5   a  and  5   b  shown FIG. 1A.  
         [0030]    [0030]FIG. 2A shows a state (erase state) wherein no electron is captured in the gate insulation film  14  including a carrier trap area  14   a . This state is the same as the state shown in FIG. 5A.  
         [0031]    [0031]FIG. 2B shows the same state as that in FIG. 5C. More specifically, FIG. 2B shows a state wherein electrons, which are captured in the gate insulation film  14  and localized near the first and second diffused layers  12  and  13 , diffuse laterally owing to their repulsion, disturbance in the read mode, or the like.  
         [0032]    The semiconductor memory of this embodiment has two erase circuits in order to erase captured electrons shown in FIG. 2B and then return to the state shown in FIG. 2A.  
         [0033]    The first erase circuit employs the same process as that described with reference to FIGS. 5A to  5 D. The nearly +5 V (third voltage) is applied to the first and second diffused layers  12  and  13  via the source/drain lines  5   a  and  5   b , and the nearly −5 V (fourth voltage) is applied from the control circuit  3  to the control gate  2   a . Electrons captured in the gate insulation film  14  near the first and second diffused layers  12  and  13  are neutralized by hot holes generated near the first and second diffused layers  12  and  13 . Accordingly, data written in the memory cell  4   a  can be erased.  
         [0034]    As the second erase circuit, the source/drain lines  5   a  to  5   d  and the p-type silicon substrate  11  are set at 0 (zero) V (first voltage). The control circuit  3  shown in FIG. 1A supplies an erase circuit control signal and block selection signal, thereby setting the potential of the control gate  2   a  in a block subjected to erase to about −15 V (second voltage). The control gate  2   a  becomes lower in potential than the p-type silicon substrate  11  and the first and second diffused layers  12  and  13 . In addition, the control gate  2   a  is set to a negative potential of about −15 V. Thus, a tunnel current flows between the control gate  2   a  and the p-type silicon substrate  11 . This tunnel current almost completely removes electrons in the gate insulation film  14 .  
         [0035]    In erase by the second erase circuit, all the source/drain lines  5   a  to  5   d  are set at 0 (zero) V, and the p-type silicon substrate  11  is also set at 0 (zero) V. Data in all the memory cells connected to the control gate  2   a  which receives −15 V are erased. In the example of FIG. 1B, electrons in all the memory cells in block  2  are erased.  
         [0036]    An erase algorithm of erasing captured electrons from the state shown in FIG. 2B and returning to the state shown in FIG. 2A will be explained with reference to the flow chart of FIG. 3.  
         [0037]    In step S 10 , whether data has completely been erased is verified. More specifically, verification is done on the basis of whether the thresholds of all the memory cells included in a target block are lower than the threshold of an erase verification comparison cell (reference cell). If the thresholds of all the memory cells are lower than the threshold of the erase verification comparison cell, the flow advances to step S 11  to end erase operation. If even one of the memory cells included in the target erase block has a threshold higher than that of the erase verification comparison cell, erase verification fails, a counter A is counted up, and the flow shifts to step S 12 . The counter A counts the number of failures in erase verification.  
         [0038]    In step S 12 , the count of the counter A is confirmed. If the count of the counter A is smaller than M, the flow shifts to step S 13 . The count M is a predetermined count.  
         [0039]    In step S 13 , the first erase circuit performs erase. To erase data in the memory cell  4   a  shown in FIG. 1B, a voltage of 5 V is applied to the source/drain line  5   a , and 0 (zero) V is applied to the source/drain lines  5   b  to  5   d . The control circuit  3  shown in FIG. 1A changes the voltage of the control gate  2   a  to −5 V.  
         [0040]    Then, the control gate  2   a  becomes lower in potential than the first diffused layer  12  connected to the source/drain line  5   a . Hot holes are injected from the first diffused layer  12  to the insulation film  14 , and electrons captured in the carrier trap area  14   a  in the gate insulation film  14  are erased. Then, the flow advances to step S 14 .  
         [0041]    In erase by the first erase circuit, a voltage of 5 V may be applied to both the source/drain lines  5   a  and  5   b . In this case, hot holes are injected from both the first and second diffused layers  12  and  13  to the gate insulation film  14 , and electrons captured at the two ends of the carrier trap area  14   a  in the gate insulation film  14  are erased.  
         [0042]    [0042]FIG. 2C shows a state wherein the first erase circuit erases electrons captured in the memory cell in the state shown in FIG. 2B. In erase by the first erase circuit, electrons near the first diffused layer  12  can be erased by injecting hot holes from the first diffused layer  12 , but electrons at the center of the carrier trap area  4   a , i.e., electrons at the middle position between the first and second diffused layers  12  and  13  cannot be erased. Even if 0 (zero) V, 5 V, and −5 V are respectively applied to the first diffused layer  12 , second diffused layer  13 , and control gate  2 , only electrons near the second diffused layer  13  are erased, but electrons at the middle position between the first and second diffused layers  12  and  13  remain unerased. Hence, such electrons which are difficult to erase by the first erase circuit must be reliably erased.  
         [0043]    In step S 14 , the erase count is confirmed by a counter B. If the count is smaller than N, the flow returns to step S 10  to check whether data has completely been erased. The counter B counts the number of operations of executing the first erase circuit. The count N is a predetermined count, and satisfies M&gt;N where M is the predetermined count used in the counter A. More specifically, if the first erase circuit is executed N times but data has not completely been erased, it is assumed that data is difficult to completely erase by only erase of the first erase circuit. Thus, the flow advances to step S 15  to erase by the second erase circuit.  
         [0044]    In erase by the second erase circuit, the source/drain lines  5   a  and  5   b  and the p-type silicon substrate  11  are set at 0 (zero) V. An erase circuit control signal and block selection signal are supplied to the control circuit  3 . Then, the control circuit  3  sets the potential of the control gate  2   a  to about −15 V, which is lower than the potential used in the first erase circuit.  
         [0045]    The control gate  2   a  becomes lower in potential than the p-type silicon substrate  11  and the first and second diffused layers  12  and  13 , and is set as low as −15 V. Thus, a tunnel current flows between the control gate  2   a  and the p-type silicon substrate  11 . This enables almost completely removing electrons in the gate insulation film  14 . Even when electrons are not completely erased by the first erase circuit and remain unerased near the center of the channel, as shown in FIG. 2C, the residual electrons can be reliably erased by flowing a tunnel current between the control gate  2   a  and the p-type silicon substrate  11  by using the second erase circuit.  
         [0046]    After erase by the second erase circuit, the flow returns to step S 10  to check again whether data have completely been erased in all the memory cells. If data have completely been erased, the flow shifts to step S 11  to end erase operation.  
         [0047]    If it is determined in step S 10  that data have not completely been erased, the flow shifts to step S 12  to repeat the above-described procedures. If the count of the counter A is M or more in step S 12 , the flow is hanged in step S 16  in order to prevent the flow from forming an infinite loop. Then, the flow advances to step S 17  to forcibly end erase operation.  
         [0048]    As described above, according to the first embodiment of the present invention, a voltage lower than that of the p-type silicon substrate  11  is applied to the control gate  2   a  to generate a large potential difference between the control gate  2   a  and the p-type silicon substrate  11  and supply a tunnel current between them. This tunnel current can reliably erase electrons remaining at the middle position between the first and second diffused layers  12  and  13 , which are difficult to erase by the first erase circuit. Even if carriers captured in the gate insulation film  14  diffuse in the gate insulation film  14 , electrons are prevented from remaining at the middle position between the first and second diffused layers  12  and  13  and can be reliably erased. The second erase circuit is used only when electrons are first erased by the first erase circuit but are not completely erased. This can minimize application of a high voltage to the control gate  2   a  and p-type silicon substrate  11 .  
         [0049]    (Second Embodiment)  
         [0050]    The second embodiment of the present invention will be described with reference to the accompanying drawings. FIGS. 4A to  4 C show the structure of each memory cell in a semiconductor memory according to the second embodiment. The structure of the semiconductor memory according to the second embodiment will be explained with reference to FIGS. 4A to  4 C. The planar arrangement of the semiconductor memory according to the second embodiment is the same as that according to the first embodiment shown in FIG. 1. FIGS. 4A to  4 C show the structure of the memory cell  4   a  shown in FIG. 1B. In FIGS. 4A to  4 C, the same reference numerals as in the first embodiment shown in FIGS. 2A to  2 C denote the same parts.  
         [0051]    The active area of a memory cell in the semiconductor memory of the second embodiment is designed in a p-well  16  in an n-well  15  formed in a p-type silicon substrate  11 . The memory cell in the second embodiment is formed by first and second diffused layers  12  and  13  formed apart from each other by a predetermined distance in the p-well  16 , a gate insulation film  14  having a carrier trap area  14   a  formed on the first and second diffused layers  12  and  13 , and a control gate  2   a  formed on the gate insulation film  14 . The first and second diffused layers  12  and  13  of the memory cell  4   a  are respectively connected to source/drain lines  5   a  and  5   b  shown in FIG. 1B. The memory cell state shown in FIG. 4A is an initial state (erase state) wherein no charge is captured.  
         [0052]    The semiconductor memory in the second embodiment also comprises two, first and second erase circuits, similar to the first embodiment. The first erase circuit is the same as that of the first embodiment. The second erase circuit uses an application voltage different from that of the first embodiment.  
         [0053]    [0053]FIG. 4B shows a state wherein electrons are captured in the gate insulation film  14  near the first and second diffused layers  12  and  13  in the memory cell of the second embodiment. In this case, electrons can be erased by the first erase circuit described in the first embodiment.  
         [0054]    [0054]FIG. 4C shows a state wherein electrons captured in the gate insulation film  14  near the first and second diffused layers  12  and  13  exist in the gate insulation film  14  near the center of the channel. In this case, electrons are erased by the following second erase circuit.  
         [0055]    For example, the control gate  2   a  of a block subjected to erase is set at 0 (zero) V (second voltage) by supplying an erase circuit control signal and block selection signal to a control circuit  3 . A voltage of 20 V (first voltage) is applied to the p-well  16  and n-well  15  to generate a large potential difference between the control gate  2   a  and the p-well  16  and supply a tunnel current between them. As a result, electrons captured in the gate insulation film  14  near the center of the channel can be neutralized, similar to the second erase circuit described in the first embodiment. The state in FIG. 4C can be returned to the state in FIG. 4A.  
         [0056]    Since the second embodiment applies a relatively large positive voltage to the p-well  16  in erase by the second erase circuit, the n-well  15  is formed between the p-type silicon substrate  11  and the p-well  16 . The n-well  15  can surely separate the p-type silicon substrate  11  from the p-well  16 .  
         [0057]    As another example of the second erase circuit according to the second embodiment, voltages of −10 V (second voltage) and 10 V (first voltage) may be respectively applied to the p-well  16  and n-well  15 .  
         [0058]    Erase operation can be executed using the second erase circuit in the second embodiment by the same algorithm as that of the first embodiment shown in FIG. 3.  
         [0059]    As described above, according to the second embodiment of the present invention, the n-well  15  surrounds the p-well  16  of the p-type silicon substrate  11  which receives a high voltage. The n-well  15  can reliably separate the p-type silicon substrate  11  from the p-well  16 , and can increase the breakdown voltage of the p-well  16  and p-type silicon substrate  11 . The control gate  2   a  and p-well  16  can be given a larger potential difference in comparison with the first embodiment, and electrons captured in the gate insulation film  14  can be reliably erased. When both the p-well  16  and n-well  15  are set at 10 V and the control gate  2   a  is set at - 10  V, a circuit for supplying a voltage to the p-well  16  and n-well  15  and a circuit for supplying a voltage to the control gate  2   a  can be simultaneously operated independently of each other. Desired voltage conditions can be easily, rapidly obtained, compared to a case wherein the p-well  16  and n-well  15 , or the control gate  2   a  is set to ground level, and a high positive or negative voltage is applied to the other. Since no charge flows into the p-type silicon substrate  11  in the second embodiment, adverse effects on a peripheral circuit can be minimized.  
         [0060]    The above-described embodiments have exemplified a semiconductor memory having both the first and second erase circuits, but the semiconductor memory may comprise only the second erase circuit.  
       Industrial Applicability  
       [0061]    As has been described above, the present invention relates to a semiconductor memory which comprises a pair of impurity-diffused layers formed in the surface area of a semiconductor substrate and a gate electrode formed on a gate insulation film on the semiconductor substrate between the pair of impurity-diffused layers, and traps carriers at different positions in the gate insulation film by applying a predetermined voltage to the gate electrode. The first voltage is applied to the semiconductor substrate including the pair of impurity-diffused layers, and the second voltage is applied to the gate electrode. Accordingly, a tunnel current flows between the semiconductor substrate and the gate electrode to erase carriers trapped in the gate insulation film. Electrons can be reliably erased without leaving them near the center of the channel area. The present invention provides a semiconductor memory which increases the reliability by surely erasing electrons.