Abstract:
This invention relates to a speed control circuit of a d.c. motor having a frequency generator. To the conventional method in which a rotation detection signal is delayed by a monostable multivibrator circuit and this delayed signal and the rotation detection signal are gated to obtain a speed error signal, a new time-voltage converter circuit is added, whereby even if the detected frequency of the generator is low, a stable speed control is possible. Because of no error synchronization, the present speed control circuit is suited to an apparatus which requires speed switching, and also to semiconductor integration.

Description:
FIELD OF THE INVENTION 
     This invention relates to a speed control circuit of a d.c. motor having a frequency generator, and more particularly to a speed control circuit suited to an apparatus which requires speed switching, and to semiconductor integration. 
     Background and preferred embodiments of this invention will be explained hereinafter with reference to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a constitution of a prior art speed control method in a block diagram. 
     FIG. 2 shows the waveform at each part. 
     FIG. 3 is a block diagram showing the constitution of another prior art speed control method. 
     FIG. 4 shows the waveform at each part. 
     FIG. 5 shows a variation of the transfer characteristic with the width of a sampling pulse in the prior art method shown in FIG. 3. 
     FIG. 6 is a block diagram showing a fundamental constitution of this invention. 
     FIG. 7 shows the waveform at each part. 
     FIG. 8 shows a prior art monostable multivibrator circuit. 
     FIG. 9 shows a novel monostable multivibrator used in this invention. 
     FIG. 10 shows a circuit diagram of a trigger pulse generating circuit which is a constituent element of this invention. 
     FIG. 11 shows the waveform at each part. 
     FIG. 12 shows a circuit diagram of a prior art sample-hold circuit. 
     FIG. 13 shows its equivalent circuit. 
     FIG. 14 shows a concrete circuit diagram of a novel sample-hold circuit which is a constituent element of this invention. 
     FIG. 15A and FIG. 15B show prior art switching circuits used in the sample-hold circuit according to this invention. 
     FIG. 16 is a concrete circuit diagram showing a novel switching circuit of a sample-hold circuit which is a constituent element of this invention. 
    
    
     PRIOR ART OF THE INVENTION 
     In order to understand the present invention, an explanation of the prior art will be made. 
     In the prior art speed control of a d.c. motor, a pulse width comparison method using a frequency generator as shown in FIG. 1 has been used. In FIG. 1, the output signal of a frequency generator 2 directly coupled to a d.c. motor 1 is amplified and shaped by an amplifier 3. A monostable multivibrator circuit 4 using a prescribed metastable period is triggered by a front edge of the above output signal (see FIG. 2(a)). The resulting signal (FIG. 2(b)) is supplied to an input of an AND gate circuit 5. 
     Further, the output signal (FIG. 2(c)) of the amplifier 3 is inverted by an inverter amplifier 6, and applied to another input of the AND gate circuit 5. The AND gate circuit performs an AND operation of the two input signals and yields a speed error signal having a pulse shape (FIG. 2(d)). 
     When the d.c. motor starts, the period of the output signal of the frequency generator 2 is longer than the metastable period of the output signal of the monostable multivibrator circuit (MM) 4. Hence, the AND gate circuit provides no output. However, when the RPM of the d.c. motor increases and reaches a prescribed value, the rear edge of the output signal of the frequency generator 2 appears in the metastable period of the output signal of the monostable multivibrator circuit 4, and hence the AND gate circuit 5 provides an output signal having a pulse shape. 
     The output signal of the AND gate circuit is smoothed by a low pass filter 7. The output signal of the low pass filter 7 (FIG. 2(e)) is amplified by a motor driving circuit 8 to drive the d.c. motor 1. The motor driving circuit 8 accelerates the d.c. motor 1 when its input level is low, and decelerates it when its input level is high. By the formation of such a closed loop as described above, the RPM of the d.c. motor 1 can be adjusted at a constant value corresponding to a monostable period set by the monostable multivibrator circuit 4. FIG. 2 shows the waveform at each part of FIG. 1. 
     In the above method, since the output of the speed comparison error signal is a pulse signal, a low pass filter is used to smooth it and also to compensate the speed control loop. However, the characteristic of the low pass filter for an optimum compensation of the loop does not agree with that of the low pass filter for suppressing the rotation irregularity of the d.c. motor arising from ripples after smoothing. 
     Furthermore, if the output frequency of the frequency generator at a prescribed RPM of the d.c. motor is low, it was necessary to make the cut-off frequency of the low pass filter sufficiently low in order to reduce the rotation irregularity. In this case, the time required for the motor to reach a constant speed from start becomes long due to a deterioration of the transient response of the low pass filter. So, the method has a defect of long pull-in time. 
     Next, explanation will be made of an example of another prior art apparatus which improves the above defect. In this speed control circuit shown in FIG. 3, the output signal of a frequency generator 10 directly coupled to a d.c. motor 9 is amplified and shaped by an amplifier 11. A monostable multivibrator circuit 12 having a prescribed metastable period is triggered by a front edge of the above output signal (FIG. 4(a)). The output signal (FIG. 4(b)) of the MM circuit 12 is supplied to a sample pulse shaper circuit 13 to form a sample pulse (FIG. 4(d)), which is supplied to a sample-hold circuit 14. The output signal of the amplifier 11 is supplied also to a trapezoid waveform shaper circuit 15 to form a trapezoid wave (FIG. 4(c)). Sampling is done by the above sample pulse and the sample-hold circuit 14 to obtain a d.c. voltage output (FIG. 4(e)) as a speed error signal. 
     When the d.c. motor 9 starts, the period of the output signal of the frequency generator 10 is longer than the metastable period of the output of MM circuit 12. Hence, the output of the sample-hold circuit 14 is &#34;L&#34;. When the RPM of the d.c. motor 9 increases and reaches a prescribed value, the trapezoid waveform formed by a read edge of the output signal of the frequency generator 10 appears in a metastable period of MM circuit 12 so that the sample-hold circuit 14 provides a d.c. voltage depending on the RPM as its output signal. Thus, in the speed controlled state, a stable voltage with little ripple is obtained. This signal is amplified by a motor driving circuit 17 through a control compensating low pass filter 16 to drive the d.c. motor 9. 
     In this second prior art speed control circuit, ripple is less than in the first prior art circuit. The control compensation low pass filter 16 can be designed more freely. Further, it is possible to fully reduce the pull-in time of the motor. However, if the control circuit is to be made as an integrated semiconductor, it is necessary to reduce the externally fixed components and the number of pins as much as possible, and a sampling pulse shaper circuit for sampling free from the necessity of pins is desired. It is extremely difficult to obtain such a pulse shaper circuit having a pulse width stable against temperature, with small variation in pulse width and no need for a number of pins. Moreover, it is not possible to realize a transfer characteristic of the sample-hold circuit 14 without any deterioration at all the frequencies of the frequency generator 10. FIG. 5 shows the transfer characteristic with a variation of a sample pulse width and a transfer function of the sample-hold circuit given by 
     
         H(S)=1/S(1-e.sup.-ST). 
    
     In FIG. 5, curve a shows the transfer characteristic with a wide sample pulse width, while curves b and c show transfer characteristics with a narrower and narrowest sample pulse width respectively. As apparent from this figure, the transfer characteristic becomes worse as the sample pulse width becomes narrower. In the sampling method, considering a case when the speed is switched to a half value, by providing an additional flip-flop circuit, the RPM can be switched depending on whether the output of the amplifier 11 has passed through the flip-flop circuit or not. The sampling pulse is formed at a rear edge of the MM circuit 12 and supplied to the sample-hold circuit 14 at a constant position with respect to the input signal. Therefore, when the rotation speed is switched, the frequency of the trapezoid wave varies. So, it happens that all the voltages of the trapezoid wave are sampled till a set speed is reached. Therefore, the defect of the above method is an error synchronization at a value other than the set one. 
     SUMMARY OF THE INVENTION 
     An object of this invention is to provide a stable speed control circuit for reducing the ripples of a speed error signal. 
     Another object of this invention is to provide a speed control circuit which constitutes a control system without any change of a sample pulse hold output and particularly is conveniently integrated. 
     A further object of this invention is to provide a speed control circuit for removing error synchronization at the time of switching speed. 
     In the present invention a rotation detection signal of a rotating body is delayed by a monostable multivibrator circuit, and the delayed signal and the rotation detection signal are gated to obtain a speed error signal, and as the speed error signal is converted to a d.c. voltage by a time-voltage converter circuit, a voltage having very little ripple is obtained as the speed error signal. Accordingly, a low pass filter for loop compensation can be made optimum, and the rotation of a d.c. motor is stabilized because of little ripple and no rotation irregularity occurs. And, as such a signal nearly equal to a d.c. voltage is obtained as the speed error signal, the output frequency of a frequency generator can be lowered, and it is very effective for controlling a motor of slow speed rotation. 
     Furthermore, since sampling to obtain the speed error signal is performed over the whole width of the upper end portion of the output signal of the time-voltage converter circuit, the sampling does not depend on the frequency of an input frequency generator. And, when the control circuit is formed as an integrated circuit, as dispersion of a sample pulse width does not occur, a very good transmission characteristic can be theoretically ensured. Accordingly, very stable speed control of a d.c. motor can be realized. 
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The constitution of a speed control circuit of this invention will be explained with reference to FIGS. 6 and 7. 
     The output signal from a frequency generator 19 directly coupled to a motor 18 is amplified and shaped by an amplifier 20. The output signal FIG. 7(a) of the amplifier 20 triggers an MM circuit 21 having a prescribed metastable period. An AND gate circuit 22 is AND gated by the output signal (FIG. 7(b)) of the MM circuit and an output signal (FIG. 7(c)) of an inverter amplifier 46 which is obtained by inverting the output signal of the amplifier 20. The output signal of the AND gate circuit is a pulse shaped speed error signal (FIG. 7(d)). The signal is supplied to a time-voltage converter circuit 23, which charges a constant current in a condenser during the appearance of the speed error pulse, to obtain a trapezoid wave (FIG. 7(h)). A pulse with a narrow width (FIG. 7(f)) is generated at a front edge of the output signal (FIG. 7(b)) of the MM circuit 21 by a trigger pulse generating circuit 24. The output signal (FIG. 7(f)) of the trigger pulse generating circuit 24 is supplied to a set terminal of flip-flop circuit (FF) 25 having set and reset terminals. The output signal (FIG. 7(c)) of the inverter amplifier 46 is supplied to the reset terminal of the FF circuit 25. The time voltage converter circuit 23 is reset by the output signal (FIG. 7(g)) of the FF circuit 25. The output signal (FIG. 7(h)) of a time-voltage converter circuit 23 is supplied to a sample-hold circuit 26. The sampling pulse of the sample-hold circuit 26 is the output signal (FIG. 7(i)) of a NOR gate circuit 27 which is gated by the output signal (FIG. 7(d)) of the AND gate circuit 22 and the output signal (FIG. 7(b)) of the MM circuit 21. In the sample-hold circuit 26, the output signal (FIG. 7(h)) of the time-voltage converter circuit 23 is sampled by the output signal (FIG. 7(i)) of the NOR gate 27, and this voltage is held. The output signal (FIG. 7(j)) of the sample-hold circuit 26 is a d.c. voltage related to the rotation of the d.c. motor 18 which is stable with little ripple under the condition of controlled speed. The speed error signal, or the output signal of the sample-hold circuit 26 is amplified by a motor driving circuit 29 through a control compensating low pass filter 28 to drive the d.c. motor 18, as in the prior art. 
     Here, the sampling pulse is obtained by NOR gating the output signal of the MM circuit 21 and the output signal of the AND gate 22. The reason for this is to form a pulse signal having a sampling pulse width always in the period of the upper end portion of the output signal of the time-voltage converter circuit 23, even if the transmission delay time of the operation of each circuit section is large. In the case of integrating the above speed control circuit by semiconductors with a fast transistor switching speed, a small internal distribution capacitance and a negligibly small signal transmission delay time, if the period of &#34;LOW&#34; voltage of the output signal (FIG. 7(b)) of the MM circuit 21 and the period of the beginning end portion of the trapezoid wave of the output signal (FIG. 7(h)) of the time voltage converter circuit 23 coincide with each other, the NOR gate 27 can be omitted and the circuit can be simplified by using the &#34;Low&#34; period of the output signal of the MM circuit 21 as the sampling pulse. 
     Next, explanation will be made of a monostable multivibrator (MM) circuit which is a constituent element of this invention. FIG. 8 shows an MM circuit using a differential detection circuit as has been customarily employed. When a signal to be delayed is supplied to a terminal 30 and provided to the base of a transistor T 1 , the transistor T 1  turns &#34;off&#34; during the width of the pulse. Then, a current is charged in a capacitor C 1  through a resistor R 1  connected to a power supply V cc . The waveform at the collector of the transistor T 1  has an integrated form. This signal is supplied to a differential detection circuit 31 and a delayed output is obtained. In the differential detection circuit 31, the d.c. voltage source V cc  is connected through a resistor R 2  to the base and the collector of a transistor T 2 , and the emitter of the transistor T 2  is grounded through a resistor R 3 . The emitter of a transistor T 3  whose base is connected to the base of the transistor T 2  is grounded through a resistor R 4 , while the collector of the transistor T 3  is connected to the emitters of transistors T 4  and T 5  commonly connected. The collector of the transistor T 4  is connected to the voltage source V cc  through a resistor R 5 , while its collector is connected to the base of a transistor T 6  whose collector is grounded through a resistor R 6 . The collector of the transistor T 5  is connected to the voltage source V cc . The above-mentioned integrated signal is applied to the base of the transistor T 4 . A d.c. voltage V TH  divided by resistors R 7  and R 8  is applied to the base of the transistor T 5 . In this arrangement, a delayed signal is derived at a connection point between the collector of the transistor T 6  and the resistor R 6 . 
     The operation of the circuit will be explained now on the assumption that the d.c. voltages applied to the bases of transistors T 4  and T 5  are equal. Then, the emitter voltage V a  of the transistor T 3  becomes ##EQU1## The current flowing through the resistor R 4  is given by ##EQU2## Thus, the collector voltage V b  of the transistor T 4  becomes ##EQU3## The level swing of V b  is given by the integrated input times the a.c. differential gain A v  which is usually expressed by 
     
         A.sub.v =g.sub.m ·R.sub.5 /2 
    
     The mutual conductance g m  is given by 
     
         g.sub.m =I.sub.1 2·V.sub.T, 
    
     where by definition V T  =K·T/q, K is the Boltzmann constant (1.38×10 -23  W·S/°C.), T is the absolute temperature (°K.), and q is the electronic charge (1.6×10 -19  coulomb). At a room temperature 300° K. (=27° C.), the thermal voltage V T  becomes 26 mV. So, we have 
     
         A.sub.v =I.sub.1 ·R.sub.5 /4×26[mV]         (4) 
    
     The collector output of the transistor T 4  is switched by the transistor T 6 , at the collector of which a rectangular waveform is obtained. It is only with difficulty that the variation of V BE  due to a temperature variation of the transistor T 6  coincides with that of the collector voltage V b  of the transistor T 4  due to a temperature variation. Furthermore, since the a.c. gain varies with temperature, it is unavoidable that the width of the pulse obtained at the collector of the transistor T 6  has a temperature variation. 
     In a monostable multivibrator circuit according to this invention, a differential detection circuit free from the above defects is used. Explanation of the circuit will be explained next with reference to FIG. 9, where the base and the collector of a transistor T 7  are connected to a d.c. voltage source V cc  through a resistor R 7  and its emitter is connected to the emitter of a transistor T 8  whose collector and base are grounded. To a connection point between the resistor R 7  and the base of a transistor T 7  is connected the base of the transistor T 9  whose emitter is grounded through an emitter resistor R 8  and collector is connected to a connection point of the emitters of the transistors T 10  and T 11 . The collector of the transistor T 10  is connected to the voltage source V cc  through a resistor R 9 . To a connection point between the collector of the transistor T 10  and the resistor R 9  is connected the base of a transistor T 12  whose emitter is connected to the voltage source V cc  and collector is grounded through a resistor R 10 . The collector of a transistor T 11  is connected to V cc . An integrated signal is applied to the base of the transistor T 10 . A d.c. voltage V TH  divided by resistors R 11  and R 12  is applied to the base of the transistor T 11 . An output is derived from a connection point between the collector of the transistor T 12  and the resistor R 10 . 
     The operation of the circuit will be explained now on the assumption that the d.c. voltages applied to the transistors T 10  and T 11  are equal. Then, the emitter voltage V c  of the transistor T 9  becomes ##EQU4## where T 7  and T 9  are the same type NPN transistors. The current I 2  is given by ##EQU5## Thus, the collector voltage V d  of the transistor T 10  becomes ##EQU6## The voltage swing of V d  becomes the integrated signal input times the a.c. gain A v , which is given by ##EQU7## In the above arrangement, if it is set such that 
     
         R.sub.9 :R.sub.8 =2:1                                      (9) 
    
     from the equation (8) the collector voltage V d  becomes ##EQU8## Namely, since V d  is always equal to the switching voltage of the transistor T 12 , and the transistors T 12  and T 8  are chosen to be the same type PNP transistors, the waveform shaping can be made at a zero crossing point even with a temperature variation. Due to the shaping at the zero crossing point, the delayed output is independent of a.c. gain and temperature variations and thus becomes stable. 
     Next, explanation will be made of a trigger pulse generating circuit which is a constituent element of this invention. 
     When a trigger pulse with a relatively large width is generated in a semiconductor integrated circuit, it was necessary to connect a CR differentiation circuit externally. The problem was that an increase of external terminals raises the manufacturing cost. 
     This invention solves this problem and provides a trigger pulse generating circuit which can generate a delayed pulse by an input pulse signal with a relatively large pulse width. 
     First of all, an embodiment of the inventive trigger pulse generating circuit will be explained with reference to FIGS. 10 and 11. Resistors R 13  and R 14  and a transistor T 13  constitute an inverter circuit section, while resistors R 15 , R 16  and R 17  and a transistor T 14  constitute a constant current source. This constant current source and transistors T 15  and T 16  constitute a waveform converter circuit section, and a resistor R 18  and a transistor T 17  constitute an emitter follower. Resistors R 19  and R 20  and a transistor T 18  constitute a gate circuit section which gates a waveform inverted output appearing at the emitter of the transistor T 17  by the input pulse signal. Resistors R 21  and R 22  and a transistor T 19  constitute a detection circuit section which shapes the waveform of the output of the gate circuit. 
     Next, explanation of the operation of the above detection circuit will be explained. When an input pulse signal (FIG. 11(a)) is applied at one terminal of resistors R 13  and R 19  and the base of the transistor T 13  changes from Low level (≅GND) to High level (higher than V BE ), transistors T 13 , T 15  and T 16  turn on and the emitter of the transistor T 16  rises rapidly from Low level to High level (V cc  -V BE  (T 16 )). This state is maintained during the period when the input pulse signal is at High level. In this case, the emitter potential of the transistor T 17  is V cc  -2V BE . Next, when the input pulse signal changes from High level to Low level, the transistor T 13  turns off and the emitter potential (≈V cc  -V BE  (T 16 )) of transistor T 16  begins to drop with a given discharge time. If the emitter potential V 1  of transistor T 14  is lower than V BE , the emitter potential of the transistor T 17  drops from V cc  -2V BE  (T 16 , T 17 ) to Low level (≅GND) with a discharge time constant τ. 
     If hFE&#39;s of transistors T 16  and T 17  are sufficiently large, the discharge time τ is given by 
     
         τ=(V.sub.cc -2V.sub.BE (T.sub.16, T.sub.17))·C.sub.T /i.sub.b 
    
     where C T  is the capacitance between the base and the collector of the transistor T 15 . The base current i b  of the transistor T 16  becomes 
     
         i.sub.b ≈i.sub.c /h.sub.FE (T.sub.16), 
    
     and the collector current i c  of the transistor T 14  is given by ##EQU9## When the input signal becomes High level (higher than V BE ) and stays at the level, the transistor T 18  turns on. Since the waveform converted output (FIG. 11(b)) of the transistor T 17  is gated by the input pulse signal, the collector of the transistor T 14  yields a gate output (FIG. 11(d)) which decreases from (V cc  -2V BE ) with the discharge time τ. Here, it is assumed that the value of the resistor 21 is sufficiently larger than that of the resistor 20. 
     The transistor T 19  and the resistors R 21  and R 22  constitute the detection circuit section. Only when the gate output obtained at the collector of the transistor T 18  is above V BE  (T 19 ), does the transistor T 19  turn on. Namely, the collector potential of the transistor T 19  becomes Low level (≅GND) and a shaped output with a pulse width τ 1  (FIG. 11(e)) is obtained from the collector of the transistor T 19 , where τ 1  is given by 
     
         τ.sub.1 ≈(V.sub.cc -3V.sub.BE (T.sub.16, T.sub.17, T.sub.19)·C.sub.T /i.sub.b. 
    
     In the trigger pulse generating circuit of the inventive type, since the current i b  flowing out can be decreased easily even if the base-collector capacitance C T  of the transistor T 15  is small, a relatively long delayed pulse output can be obtained. Furthermore, by changing the emitter potential of the transistor T 14  in the constant current circuit, the width of the delayed pulse output can be easily varied. 
     Next, explanation will be made of a sample-hold circuit which is a constituent element of this invention. 
     FIG. 12 shows an example of a prior art sample-hold circuit, where a sample pulse 33 is applied through a resistor R 34  to the base of a transistor T 35  and a voltage 36 to be sampled is applied to the collector of the transistor T 35  through an emitter follower stage of a transistor T 36 . During the presence of the sample pulse, the transistor T 35  is conducting and a holding capacitor C 36  is charged or discharged. The voltage at the capacitor C 36  is held during the period without the sample pulse. A sample-hold output is derived through the transistors T 37  and T 38 . FIG. 13 shows an equivalent circuit of FIG. 12. In FIG. 13, a signal 39 to be sampled is applied through a signal source resistor γ i  to a switching transistor T 35  represented by a conduction resistor γ ON  and a switch 42. Only when a sample pulse appears at the base of the transistor T 35 , the transistor T 35  becomes conductive and hence the switch is closed, and a holding capacitor C 43  is charged through the resistor γ ON . A resistor R 44  is a load resistor satisfying a relation R 44  &gt;&gt;γ i  +γ ON . Consider that a sample pulse is applied at the base of the transistor T 35  and the switch 42 is closed. If the voltage charged in the capacitor C 43  is lower than the sampled voltage, electric charge flows to the capacitor C 43  from the sampled voltage side through resistors γ i  and γ ON . In the opposite case, electric charge in the capacitor C 43  is discharged through the resistors γ i  and γ ON . In this case, since the width of the sample pulse is limited, it is desirable to make τ=C 43  (γ i  +γ ON ) negligibly smaller than the period of the sample pulse in order to speed up charging and discharging of the capacitor C 43 . To reduce the value of the capacitor C 43  is not desirable because discharge through the resistor R 44  in the absence of the sample pulse decreases the held voltage and makes the holding error large. In FIG. 12, charging of the capacitor C 36  happens easily, while discharge occurring through the resistor R 45  deteriorates the response. Furthermore, since the output of the sampled voltage is derived through the transistors T 36 , T 37  and T 38 , it is shifted by a d.c. voltage of about 3 V BE  due to the base-emitter voltage (V BE ) of each transistor. In other words, the output has a temperature dependence of 3 V BE . Usually, since V BE  is temperature dependent in the order of -2 mV/°C., the output variation with a temperature change of 50° C. becomes 300 mV. So, if the circuit is used in a PLL circuit, a phase shift occurs. Especially, the semiconductor integration of the above sample-hold circuit results in an undesirable variation in the sample-hold output because a temperature increase of the tip in time of switch-on of a power source causes a difference  from an ambient temperature. 
     A sample-hold circuit according to this invention is constituted to avoid this shortcoming. Explanation of the circuit will be made next with reference to FIG. 14, where a voltage 47 to be sampled is formed by a constant current source 48, switches 49 and 50 and a capacitor C 51 . The voltage is received by a complementary connection of an NPN transistor T 52  and a PNP transistor T 53  and supplied from the emitter of the transistor T 52  to the collector of a switching transistor T 54  as a low output impedance signal. A resistor R 55  connected to the emitter of the NPN transistor T 52  is an emitter follower resistor. A part of the sampled voltage 47 is also received by a complementary connection of an NPN transistor T 56  and a PNP transistor T 57 . The PNP transistor T 58  whose base and collector are connected causes a level shift to a lower level by V BE . The voltage level is divided by resistors R 59  and R 60  and applied to the base of a PNP transistor T 61 . The resistor R 59  has a value much smaller than that of the resistor R 60 . The emitter of the PNP transistor T 61  is connected to the collector of the switching transistor T 54 . When a sample pulse is applied to the base of the transistor T 54 , the transistor T 54  becomes conducting and a holding capacitor C 63  either charges or discharges. Even in the absence of the sample pulse, the voltage held by the capacitor C 63  is received by a complementary connection of a PNP transistor T 65  and an NPN transistor T 66 . A transistor T 67  whose base and collector are connected causes a level shift to a higher level by V BE . The output of the sample-hold circuit is derived from the emitter of an emitter follower formed by an NPN transistor T 68 . A resistor R 69  is an emitter resistor and a resistor R 70  is a base resistor of the emitter follower. 
     Since the voltage 47 to be sampled is received by a high impedance circuit of a composite transistor of complementary connection, it is free from any influence of the sample-switch circuit. 
     Consider a case when a sample pulse 64 is applied to the base of the transistor T 54  and the transistor T 54  becomes conducting. In this case, if the sampled voltage at the emitter of the transistor T 52  is higher than the voltage at the holding capacitor C 63 , a current flows from the emitter of the transistor T 52  toward the transistor T 54  to charge the capacitor C 63 . On the other hand, if the voltage at the capacitor C 63  is higher than the emitter voltage of the transistor T 52 , the electric charge in the holding capacitor C 63  is discharged through the transistor T 54 , the resistor R 62  and the transistor T 61 . 
     In any case, since the signal source impedance of the sampled voltage at the emitter of the transistor T 52  is extremely small, charging and discharging of the holding capacitor C 63  occur very quickly. Hence, the sample error is extremely small. When the transistor T 54  becomes non-conducting, the electric charge in the holding capacitor C 63  is discharged through a load resistor, which is nearly equal to the product of the current amplification factors of the transistors T 65  and T 66  and the value of the resistor R 70 . Since the value of the load resistor becomes very large, the holding error is extremely small. 
     The d.c. level of the sampled voltage is derived, after being shifted to a lower level by V BE  at the emitter of the transistor T 52  of complementary connection of the transistors T 52  and T 53 , shifted to a higher level by V BE  by a composite transistor of transistors T 65  and T 66 , shifted to a higher level by V BE  by the transistor T 67 , and shifted to a lower level by V BE  by the emitter follower of the transistor T 68 . The d.c. level of a part of the sampled voltage 47 is shifted to a lower level by V BE  at the emitter of the transistor T 56 , shifted to a lower level by V BE  by the transistor T 58 , and shifted to a higher level by V BE  by the transistor T 61 , and, therefore, equal to the level obtained by the path through the transistor T 52  and T 53 . Further, if V BE  of the composite transistor of the transistors T 52  and T 53  is equal to V BE  of the composite transistor of the transistors T 65  and T 66  and if V BE  of the transistor T 67  is equal to V BE  of the transistor T 68 , the sampled voltage source 47 becomes equal to the sample-hold output so that the temperature dependence is extremely small. 
     Next, consider the case when the input terminal continues to have no input, that is, when both the switches 49 and 50 are off and the switching transistor T 54  continues to be conducting. The first complementary connection stage of the transistors T 56  and T 57  and the second complementary connection stage of the transistors T 52  and T 53  are circuits of emitter follower type of an NPN transistor. The capacitor C 51  is not charged at all. The base potential of the PNP transistor T 61  is kept at a low level by the resistor R 60  and its emitter potential becomes V BE . The base potential is kept also at a low level through the conducting switching transistor T 54   and the emitter potential becomes 2 V BE . The d.c. potential is shifted to a higher level by V BE  by the transistor T 67  and to a lower level by the transistor T 68 . As a result, the output voltage of the sample-hold circuit becomes 2 V BE , namely an extremely low potential is derived. 
     Therefore, in the application of the circuit to a motor speed control system, even under the continual condition without input at the input terminal, the present sample-hold circuit, being kept at a low level of 2 V BE , does not give any high voltage during the stop period of the motor. This enables the start of the motor. 
     As described above, the sample-hold circuit of this invention has a good response and hence a small sample error. Furthermore, since the load resistance is large, the discharge of the electric charge from the holding capacitor during the non-conductive period of the sample-switch transistor is extremely small and hence the holding voltage error is extremely small. Since the level shift of the sampled voltage is given by V BE  of the transistors, the sample-hold output has an extremely small temperature dependence. Even under the condition that the sample-hold circuit has no input of a voltage to be sampled, the output voltage can maintain a low value. 
     Next, explanation will be made of a sample switch circuit used in the sample-hold circuit which is a constituent element of this invention. 
     FIG. 15A and FIG. 15B show sample switch circuits that have been used in the sample-hold circuit. It is so arranged that a sample pulse 71 is applied to the base of a transistor 73 through a resistor R 72 , a sampled voltage source 74 is connected to the collector (FIG. 15A) or the emitter (FIG. 15B), and a sample output is derived from a capacitor 75 connected to the emitter or the collector. In this construction, in the absence of the sample pulse the base of the transistor T 73  is grounded through a resistor R 72 . Namely, since the base potential of the transistor T 73  is zero, the potential between the base and the emitter of the transistor T 73  is reversely biased by the holding voltage of the capacitor C 75  in the circuit of FIG. 15A, while reversely biased by the sampled voltage 74 in the circuit of FIG. 15B. 
     This fact is a large problem in the case of integrating the sample circuit. Usually, the reverse breakdown voltage between the base and the emitter of a transistor is about 7 V. So, the sampled voltage and the holding voltage should be less than 7 V. The dynamic range of the sample-hold circuit is therefore limited. 
     The current amplification factor when a current flows from the collector to the emitter of a transistor is large, while it is extremely small when the current flows from the emitter to the collector. In FIG. 15A, charging of the capacitor C 75  occurs rapidly by discharging takes a long time. 
     The aim of a sample switch circuit used in this invention is to increase the dynamic range of sample-hold and decrease the resistance of a switching transistor in time of conduction thereby to ensure an accurate sample-hold. 
     In FIG. 16, a sample pulse 76 is applied to the base of a first transistor T 80  through a resistor R 77  and diodes D 78  and D 79  connected in parallel with opposite polarity, to the base of a second transistor T 83  through a resistor R 81  and a diode D 82 , to the base of a third transistor T 86  through a resistor R 84  and a diode D 85 , and to the base of a fourth transistor T 90  through a resistor R 87  and diodes D 88  and D 89  connected in parallel with opposite polarity. A sampled voltage source 91 is connected to the collector of the transistor T 80  and the emitter of the transistor T 86 . A holding capacitor C 92  is connected to the emitter of the transistor T 83  and the collector of the transistor T 90 . Furthermore, the emitter of the transistor T 80  is connected to the collector of the transistor T 83 , while the collector of the transistor T 86  is connected to the emitter of the transistor T 90 . 
     When a sample pulse is applied to the base of each transistor, each transistor becomes conducting. In the case when the holding capacitor C 92  is charged from a sampled voltage source 91, electric charge moves through the transistors T 80  and T 83 . In the case when the holding capacitor C 92  discharges toward the sampled voltage source 91, an electric charge moves through the transistors T 90  and T 86 . Both charging and discharging occur rapidly. 
     Next, in the absence of the sample pulse since the transistor T 83  and the diode D 82  are reversely biased by the holding voltage of the capacitor C 92 , the allowed voltage for the capacitor C 92  becomes twice the reverse breakdown voltage between the base and the emitter, i.e about 14 V. Likewise, the allowed voltage for the sampled voltage becomes about 14 V by the transistor T 86  and the diode D 85 . If a plurarity of diodes are connected to the base, the allowed voltage can be made larger. 
     At the instant when the sample pulse disappears, the bases of the transistors T 80  and T 90  are grounded through the diodes and resistors and these transistors become nonconducting. Therefore, the sampled voltage does not influence the voltage of the holding capacitor during the period when no sample pulse appears. The transistors T 80  can be used satisfactorily with the emitter-collector breakdown voltage of the transistor T 83  and the base-emitter breakdown voltage of the transistor T 80 . The transistor T 86  can be used satisfactorily with the emitter-collector breakdown voltage of the transistor T 90  and the base-emitter break-down voltage of the transistor T 86 . 
     As described above, the sample-hold circuit of this invention has advantages of an extended dynamic range of sample-hold, a reduction of the resistance γ ON  of the switch circuit during conducting time, and improved insulation during non-conducting time.