Abstract:
According to one aspect, the subject matter described herein includes a method for validating a long term evolution (LTE) transport data block and code blocks within the data block. The method includes steps occurring at an LTE traffic simulator configured to simulate plural user equipment (UE) devices. The steps include receiving, from an evolved nodeB under test, an LTE transport block including a plurality of code blocks. The steps also include decoding the code blocks and verifying a cyclic redundancy check (CRC) code for each of the code blocks. The steps further include while decoding the code blocks and verifying the CRC codes for the code blocks, verifying a CRC code for the transport block.

Description:
TECHNICAL FIELD 
     The subject matter described herein relates to validating long term evolution (LTE) code blocks and transport blocks. More specifically, the subject matter relates to methods, traffic simulators, and computer readable media for validating LTE code blocks and transport blocks. 
     BACKGROUND 
     As cellular communication technology evolves, providers are able to more effectively utilize their allocated spectrum. Enhanced protocols such as those specified by the 3rd generation partnership project&#39;s (3GPP) long term evolution (LTE) standards are enabling providers to increase the speed and capacity of their wireless networks. These enhanced protocols, however, are significantly more complex than their predecessors and require the design, integration, and support of new hardware, such as mobile base stations, within a provider&#39;s network. The successful implementation of such hardware often requires multiple iterations of testing and refinements in order to meet the specified performance requirements. Testing such hardware, however, is also becoming an increasingly complex task. As the number of user equipment (UE) nodes supported by a base station and the individual resource utilization of such UEs increases, testing hardware must be optimized to effectively simulate such demands. 
     Accordingly, a need exists for methods, traffic simulators, and computer readable media for validating LTE code blocks and transport blocks. 
     SUMMARY 
     According to one aspect, the subject matter described herein includes a method for validating an LTE transport data block and code blocks within the data block. The method includes steps occurring at an LTE traffic simulator configured to simulate plural UE devices. The steps include receiving, from an evolved nodeB under test, an LTE transport block including a plurality of code blocks. The steps also include decoding the code blocks and verifying a cyclic redundancy check (CRC) code for each of the code blocks. The steps further include while decoding the code blocks and verifying the CRC codes for the code blocks, verifying a CRC code for the transport block. 
     According to another aspect, the subject matter described herein includes an LTE traffic simulator configured to simulate plural UE devices and validate an LTE transport data block and code blocks within the data block. The traffic simulator includes a communication interface configured to receive, from an evolved nodeB under test, an LTE transport block including a plurality of code blocks. The traffic simulator also includes a channel decoder. The channel decoder is configured to decode the code blocks and verify a CRC code for each of the code blocks. The channel decoder is also configured to, while decoding the code blocks and verifying the CRC codes for the code blocks, verify a CRC code for the transport block. 
     As used herein, the term “node” refers to a physical computing platform including one or more processors and memory. 
     As used herein, the term “module” refers to software in combination with hardware (such as a processor) and/or firmware for implementing features described herein. 
     The subject matter described herein can be implemented in software in combination with hardware and/or firmware. For example, the subject matter described herein may be implemented in software executed by one or more processors. In one exemplary implementation, the subject matter described herein may be implemented using a non-transitory computer readable medium having stored thereon computer executable instructions that when executed by the processor of a computer control the computer to perform steps. Exemplary computer readable media suitable for implementing the subject matter described herein include non-transitory computer readable media, such as disk memory devices, chip memory devices, programmable logic devices, and application specific integrated circuits. In addition, a computer readable medium that implements the subject matter described herein may be located on a single device or computing platform or may be distributed across multiple devices or computing platforms. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The subject matter described herein will now be explained with reference to the accompanying drawings of which: 
         FIG. 1  is a network diagram of an exemplary system for validating an LTE transport data block and code blocks within the data block in accordance with embodiments of the subject matter described herein; 
         FIG. 2  is a flow diagram illustrating an exemplary sequence for validating an LTE transport data block and code blocks within the data block in accordance with embodiments of the subject matter described herein; 
         FIG. 3  is a block diagram illustrating an exemplary transport data block for validating an LTE transport data block and code blocks within the data block in accordance with embodiments of the subject matter described herein; 
         FIGS. 4A ,  4 B, and  4 C are respectively first, second, and third portions of a flow diagram illustrating an exemplary channel decoder for validating an LTE transport data block and code blocks within the data block in accordance with embodiments of the subject matter described herein; and 
         FIG. 5  is a flow chart illustrating an exemplary process for validating an LTE transport data block and code blocks within the data block in accordance with embodiments of the subject matter described herein. 
     
    
    
     DETAILED DESCRIPTION 
     Methods, traffic simulators, and computer readable media for validating LTE code blocks and transport blocks are provided.  FIG. 1  is a network diagram of an exemplary system for validating an LTE transport data block and code blocks within the data block in accordance with embodiments of the subject matter described herein. Referring to  FIG. 1 , network environment  100  may include network node  102  and LTE multi-UE simulator  104 . Network node  102  may be a base station node for a cellular network, for example, network node  102  may be an evolved nodeB (eNodeB). LTE multi-UE simulator  104  may be a computing platform for simulating the functionality of plural UE devices to test the functionality of network node  102 . LTE multi-UE simulator  104  may be operatively associated with or include radio input/output (I/O) module  106  for communicating with network node  102  over a wireless or radio interface. 
     LTE multi-UE simulator  104  may be configured to generate network traffic to simulate plural LTE UE devices. LTE multi-UE simulator  104  may include radio link control (RLC)/medium access control (MAC) module  108  for performing higher layer processing. Radio I/O module  106  interfaces with common public radio interface (CPRI) module  114 . CPRI module  114  receives data in the downlink direction for further processing and sends data in the uplink direction to radio I/O module  106 . Downlink signal chain processing (DL-SC) module  116  receives downlink data from CPRI module  114 . DL-SC processing module  116  forwards the received downlink data to control digital signal processor (DSP)  110 . Control DSP  110  controls the overall operation of LTE multi-UE simulator  104  for simulating the LTE physical layer. Control DSP  110  processes control information and directs data intended for upper layers in RLC/MAC module  108 . Control DSP  110  processes the downlink control information and provides the DL-SC processing module  116  with the information required to process the downlink data. DL-SC processing module  116  sends the downlink data to channel decoder  118 . Channel decoder  118  sends the decoded data to RLC/MAC module  108 . On the uplink side, uplink signal chain (UL-SC) processing module  112  formulates uplink transport blocks, sends the blocks to CPRI module  114 , which sends the transport blocks to radio I/O module  106  for transmission to network node  102 . 
     In accordance with embodiments of the subject matter described herein, channel decoder  118  may validate an LTE transport data block and code blocks within the data block. 
       FIG. 2  is a flow diagram illustrating an exemplary sequence for validating an LTE transport data block and code blocks within the data block in accordance with embodiments of the subject matter described herein. Referring to  FIG. 2 , at step  1 , network node  102  may transmit a transport data block to radio I/O module  106 . For example, network node  102  may be an eNodeB being tested by LTE multi-UE simulator  104  and the transport data block may be a physical downlink shared channel (PDSCH) transport code block. Radio I/O module  106  may receive the transport data block from network node  102  and, at step  2 , radio I/O module  106  may communicate the transport data block to LTE multi-UE simulator  104  via CPRI module  114 . At step  3 , CPRI module  114  may communicate the transport data block to DL-SC processing module  116 . The transport data block may be encoded and/or may require CRC calculation/verification. For example, the transport data block may have been encoded in accordance with a Viterbi algorithm or schema and may contain one or more CRC codes. At step  4 , DL-SC processing module  116  may communicate the transport data block to channel decoder  118  for decoding and/or CRC calculation/verification. 
     In accordance with embodiments of the subject matter described herein, channel decoder  118  may be configured to perform decoding and CRC calculation/verification contemporaneously. In some embodiments, channel decoder  118  may be configured to perform decoding and CRC calculation/verification simultaneously. Performing decoding and CRC calculation/verification contemporaneously reduces the overall time required for processing the transport data block. For example, if the transport data block were decoded and then a CRC calculation/verification was performed for the transport data block, the data within the transport data block would be parsed two separate times. A first pass of the data would be made during the decoding phase and then an additional pass of the data would be performed in calculating/verifying the CRC code. By decoding the transport data block and calculating/verifying the CRC code contemporaneously, channel decoder  118  need only parse the data contained in the transport data block once, thereby reducing the time required to process the transport data block. 
     At step  5 , channel decoder  118  may contemporaneously decode the transport data block and perform CRC calculation/verification for the transport data block. For example, channel decoder  118  may include a convolutional encoder/decoder and one or more linear feedback shift registers. Channel decoder  118  may parse the data contained in the transport data block, running each bit through both the convolutional encoder/decoder and one or more of the linear feedback shift registers. As the data contained within the transport data block is parsed, and run through each of the convolutional encoder/decoder and the one or more linear feedback shift registers, the convolutional encoder/decoder may decode the data and the linear feedback shift register(s) may adjust their state to reflect each additional bit processed. After the final bit in the transport data block has been parsed and passed through each of the convolutional encoded/decoder and the linear feedback shift register(s), the data block will have been decoded and the linear feedback shift register(s) will contain one or more CRC values which may be verified. Thus, channel decoder  118  will have decoded the transport data block and contemporaneously performed CRC calculation/verification for the transport data block, having only been required to parse the transport data block a single time. Having decoded the transport data block and contemporaneously performed CRC calculation/verification for the transport data block, at step  6 , channel decoder  118  may communicate the data contained within the transport data block to RLC/MAC module  108  for further processing. 
       FIG. 3  is a block diagram illustrating an exemplary transport data block for validating an LTE transport data block and code blocks within the data block in accordance with embodiments of the subject matter described herein. Referring to  FIG. 3 , transport data block  300  may include one or more code data blocks. For example, transport data block  300  includes code data blocks  302 ,  304 ,  306 ,  308 ,  310 ,  312 , and  314 . Transport data block  300  may also include a CRC code portion containing a CRC code value that corresponds to the data contained within transport data block  300 . For example, transport data block  300  includes CRC code portion  316 . Each of the code data blocks contained within transport data block  300  may include a data portion and a CRC code portion corresponding to the data contained within the data portion. For example, code data block  302  may include data portion  318  and CRC code portion  320 . Similarly, code data block  304  may include data portion  322  and CRC code portion  324 , code data block  306  may include data portion  326  and CRC code portion  328 , code data block  308  may include data portion  330  and CRC code portion  332 , code data block  310  may include data portion  334  and CRC code portion  336 , code data block  312  may include data portion  338  and CRC code portion  340 , and code data block  314  may include data portion  342  and CRC code portion  344 . 
       FIGS. 4A ,  4 B, and  4 C are respectively first, second, and third portions of a flow diagram illustrating an exemplary channel decoder for validating an LTE transport data block and code blocks within the data block in accordance with embodiments of the subject matter described herein. Referring to  FIG. 4A , channel decoder  118  may include encode/decode module  400  for decoding transport data block  300 . Encode/decode module  400  may be, for example, a convolutional encoder/decoder. Channel decoder  118  may also include code block CRC module  402  for calculating/verifying CRC codes for each of the code data blocks contained within transport data block  300 , such as, code data blocks  302 ,  304 ,  306 ,  308 ,  310 ,  312 , and  314 . Code block CRC module  402  may be, for example, a linear feedback shift register. Channel decoder  118  may further include transport block CRC module  404  for calculating/verifying a CRC code for transport data block  300 . Transport block CRC module  404  may be, for example, a linear feedback shift register. 
     At step  1 , channel decoder  118  may begin to process transport data block  300  with code data block  302 . Channel decoder  118  may parse data portion  318  of code data block  302 , passing each bit through encode/decode module  400 , code block CRC module  402 , and transport block CRC module  404 . After the last bit of data portion  318  of code data block  302  has been processed, code block CRC module  402  may compare its state value to a CRC value stored in CRC code portion  320  of code data block  302 . At step  2 , code block CRC module  402  may reset its state value to prepare to process a new code data block. Referring to  FIG. 4B , at step  3 , channel decoder  118  may continue to process transport data block  300  by beginning to process code data block  304 . Channel decoder  118  may parse data portion  322  of code data block  304 , passing each bit through encode/decode module  400 , code block CRC module  402 , and transport block CRC module  404 . After the last bit of data portion  322  of code data block  304  has been processed, code block CRC module  402  may compare its state value to a CRC value stored in CRC code portion  324  of code data block  304 . At step  4 , code block CRC module  402  may reset its state value to prepare to process a new code data block. This process may be repeated for each code data block within transport data block  300 . Referring to  FIG. 4C , at step  5 , channel decoder  118  may continue to process transport data block  300  by beginning to process code data block  314 , the final code data block of transport data block  300 . Channel decoder  118  may parse data portion  342  of code data block  314 , passing each bit through encode/decode module  400 , code block CRC module  402 , and transport block CRC module  404 . After the last bit of data portion  342  of code data block  314  has been processed, code block CRC module  402  may compare its state value to a CRC value stored in CRC code portion  344  of code data block  314 . At step  6 , code block CRC module  402  may reset its state value to prepare to process a new code block, namely the first code block of the next transport data block. Having processed the final code data block of transport data block  300 , transport block CRC module  404  may compare its state value to a CRC value stored in CRC code portion  316  of transport data block  300 . At step  7 , transport block CRC module  404  may reset its state value to prepare to process the next transport data block 
       FIG. 5  is a flow chart illustrating an exemplary process for validating an LTE transport data block and code blocks within the data block in accordance with embodiments of the subject matter described herein. Referring to  FIG. 5 , in step  500 , an LTE transport block including a plurality of code blocks is received from an evolved nodeB. For example, transport data block  300  may be received from network node  102 . In step  502 , the code blocks are decoded and a CRC code for each of the code blocks is verified. For example, code data blocks  302 ,  304 ,  306 ,  308 ,  310 ,  312 , and  314  may be decoded and CRC codes stored in CRC portions  320 ,  324 ,  328 ,  332 ,  336 ,  340 , and  344  may be verified. In step  504 , while decoding the code blocks and verifying the CRC codes for the code blocks, a CRC code for the transport block is verified. For example, a CRC code for transport data block  300  stored in CRC portion  316  may be verified. 
     It will be understood that various details of the subject matter described herein may be changed without departing from the scope of the subject matter described herein. Furthermore, the foregoing description is for the purpose of illustration only, and not for the purpose of limitation, as the subject matter described herein is defined by the claims as set forth hereinafter.