Abstract:
Stress is eliminated between a dielectrically passivated silicon wafer and a thick polycrystalline silicon layer by depositing a low melting transition layer such as a doped silica glass over the passivated silicon wafer.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to the elimination of stress between a dielectrically passivated substrate and an overlying semiconductor material. More specifically, this invention relates to the elimination of stress between a dielectrically passivated silicon wafer and a thick polycrystalline silicon layer which is deposited on the silicon wafer. 
     One of the main processing steps associated with dielectric isolation technology is the deposition of a thick polycrystalline silicon layer onto an oxidized surface of a silicon wafer. During this deposition, the polysilicon film tends to densify, which in turn generates a substantial residual stress between the polysilicon film and the dielectrically passivated silicon wafer. FIG. 1 illustrates the structure of the prior art which consists of a silicon substrate 10, a passivation layer 20, typically of silicon dioxide and polysilicon layer 60. In this structure, substantial residual stress is formed between layers 60 and 20. 
     This residual stress is harmful to final semiconductor products built from such starting materials because of the possibility that the stress can cause warping of the wafer which is one of the main causes of reduced yield during production. Additionally, microcracks and voids in device patterns, difficulties in subsequent mask alignment and degradation of the electrical parameters of semiconductor devices are all caused in part by excessive stress existing between the polysilicon film and the underlying wafer. 
     By reducing the ill effects of the stress thus formed it is possible to substantially improve the detrimental effects on final device yield. 
     It has been previously known that the significant stress which is created between a polysilicon film and the dielectrically passivated semiconductor wafer is detrimental to final device fabrication. This has been described in several publications including U. S. Davidson and F. Lee, &#34;Dielectric-Isolated Integrated Circuit Substrate Process&#34;, Proc. IEEE, Volume 57, 1532 (1969) and T. Suzuki, et al., &#34;Deformation in Dielectric Isolated Substrates and Its Control by a Multilayer Polysilicon Support Structure&#34;, J. Electrochem. Soc., Volume 127, 1573 (1980). 
     The relatively low softening temperature of a heavily doped silicon dioxide, e.g. phospho-silica glass or boro silica glass is known as was discribed in S. K. Gandhi, &#34;VLSI Fabrication Principles&#34; (1983), J. Wiley and Sons, Inc., Page 66. Because of the relatively low softening temperature of such glasses, the phospho-silica glass has been used in VLSI Technology to form tapered via holes. This use of phospho-silica glass is disclosed in W. Kern and R. S. Rosler, J. Vac. Sci. and Tech., Volume 14, 1082 (1977). 
     SUMMARY OF THE INVENTION 
     In order to overcome the difficulties associated with the stress causing junction between a semiconductor wafer and a polysilicon film, it has become necessary to find a simple and inexpensive method for permitting high quality and high yield semiconductor processing. According to the present invention, the stress existing between the passivated wafer and polysilicon film can be minimized by depositing a heavily doped silicon dioxide film onto the dielectrically passivated silicon wafer surface prior to deposition of the polysilicon film. Unrestricted densification of the polysilicon can then occur without damage to device integrity because the heavily doped oxide acts as a &#34;Pseudo-Liquid&#34; interface between the polysilicon and the undoped oxide layer on the substrate. In this manner the doped oxide film allows contraction of the polysilicon layer without causing any mechanical stress in the silicon wafer. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a cross sectional view of the structure of the prior art. 
     FIG. 2 is a cross sectional view of a stress free dielectrically isolated structure made in accordance with the invention. 
     FIG. 3 is a cross sectional view of an intermediate stage in the formation of a dielectrically isolated semiconductor product. 
     FIG. 4 a , 4 b , 4 c  is an illustration showing the various process stages of the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention is illustrated in a general sense in FIG. 2 where a stress free, multilayer structure is shown. A substrate 10 is provided, preferably of silicon having a (100) orientation, but recognizing that any crystalline material or orientation intended for use in a dielectrically isolated product can benefit from this invention. Typically, this substrate 10 will be approximately 500 μm thick. A dielectrically passivating layer 30 is provided on the substrate. In the preferred practice of the invention, the substrate is silicon, thus, a silicon dioxide passivating layer 30 can be formed by thermal oxidation at a temperature range of 1000°-1200° C. In a preferred process, the dielectrically passivating layer will be between about 1 and 3 micrometers thick. A transition layer 23, preferably of doped silica glass having a low softening temperature, is provided on said dielectrically passivating layer and a polycrystalline layer 60 preferably of silicon is deposited on the transition layer 23 at a temperature above the softening temperature of the transition layer 23. It is desired that the transition layer have a softening temperature substantially lower than the deposition temperature of the subsequently applied poly-crystalline silicon layer 60 to permit densification during the deposition process without creating stress between the transition layer 23 and the densifying polycrystalline layer 60. 
     An example of a structure which is subject to the stresses caused by application of a polysilicon layer on a silicon substrate is illustrated in FIG. 3 wherein an intermediate step in the formation of dielectrically isolated islands is shown. A silicon substrate 10 having grooves 40 is shown with a dielectrically passivating layer 20 covering the substrate, including the grooves 40 to provide a complete dielectric coating over the substrate. The region 45 in the substrate which is between the grooves 40 40 will eventually become the dielectrically isolated islands. 
     Next, a transition layer 23 of highly doped silica glass is provided, preferably by chemical vapor deposition. A suitable doped glass comprises phospho-silica glass containing approximately 10% phosphorous. This glass can be deposited by chemical vapor deposition at a temperature range of 300°-500° C. A layer of between about 500 and 10,000 Angstroms is formed in approximately 10 minutes and will provide a suitable transition layer. Directly on this layer, a polysilicon layer 60 is deposited by chemical vapor deposition at a temperature above 1100° C. At this temperature the transition layer is softened thus allowing for crystal formation and growth in the polysilicon layer without creating any substantial interlayer stress at the interface with the transition layer. During the crystal formation in the polysilicon, there is densification of the polycrystalline material resulting in shrinkage of the polycrystalline layer. Previously, when the polysilicon was applied directly to the dielectrically passivating layer, this densification created substantial interlayer stress and resulted in bending or warping of the final wafer. Upon coating of the polysilicon layer, the transition layer hardens and a stress free interface remains. 
     Referring now to FIGS. 4 a  -4 g  the preferred manner of forming dielectrically isolated islands in a DI wafer is described. As shown in FIG. 4 a , a silicon wafer 10 preferably having a (100) orientation is selected and an oxide 20 is grown by thermal oxidation, preferably to a thickness of about 2 micrometers. Typically, the silicon wafer will have a thickness of about 500 micrometers. FIG. 4 b  illustrates the structure formed as described above and further shows apertures 30 where the oxide has been removed. The apertures 30 are formed by a photolithographic process followed by a conventional wet etch. As shown in FIG. 4 c , grooves 40 are formed in the silicon wafer at the locations of apertures 30. In this manner, it is possible to obtain uniform groove depth. Following groove formation the remaining oxide 20 is stripped and as shown in FIG. 4 d , the substrate 10 has a plurality of grooves 40 which define regions 45 in the substrate betwen the grooves and above the depth of the grooves as shown by dashed line 41. 
     FIG. 4 e  shows the N+ layer 42 formed along the entire exposed surface of substrate and the oxide layer 21 which is grown by thermal oxidation along the entire substrate surface, including the surface of grooves 40. Preferably the N+ layer is formed by diffusion and will form a buried layer. The oxide layer 21 is a dielectric passivating layer. Acceptable alternative to the use of silicon oxide as the dielectric passivating layer include silicon nitride and aluminum oxide, but any other dielectric material could be used. A transition layer 23 of highly doped silica glass is deposited by chemical vapor deposition on the dielectric passivating layer 21 as shown in FIG. 4 f . The transition layer may contain any dopant which substantially reduces the melting temperature of silica glass without causing excessive migration or diffusion of dopants into the substrate. Acceptable alternatives to the previously described phospho-silica glass include boro-silica and arseno-silica glass. In each case, it is the reduced melting temperature imparted to the glass which renders these dopants desirable. Then, at a temperature above the softening temperature of the transition layer 23, a layer 60 of polycrystalline silicon is deposited by chemical vapor deposition. The polysilicon layer 60 is deposited at a temperature of between about 1100° C. and 1250° C. At this temperature, the transition layer 23 of phospho-silica glass, containing approximately 10% phosphorous, is in a pseudo-liquid state. This permits unrestricted densification of the polysilicon without the creation of any substantial stress between the silicon wafer 10 and the polysilicon layer 60. The polysilicon layer 60 may preferably be formed with a thickness of about 500 micrometers and the transition layer is optionally between about 0.05 micrometers and 1 micrometer thick. 
     The structure so formed is then inverted for subsequent processing as shown in FIG. 4 g . The surface is ground and polished along dashed line 41 to expose the &#34;bottoms&#34; of the grooves 40. As shown, it is typically easier to slightly exceed the depth necessary to reach the line 41 and this insures that the dielectric material of each groove is exposed. It is at this step that the prior bending and warping of DI wafers presented the most severe problem. If the wafer is sufficiently non-planar due to interlayer stresses, the grinding and polishing steps would not consistently result in the exposure of every groove. Thus, rather than forming isolated islands 70 as shown in FIG. 4 g , non-isolated regions 75 result as shown in FIG. 5. 
     Every attempt is made to reduce the variations from planarity prior to the grinding and polishing step, thus, it has been found that some slight variations can be overcome by securing the wafers to a vacuum chuck during the grinding and polishing steps. 
     In some instance, the dopant contained in the transition layer may not be sufficiently masked from the silicon islands by the 2 micrometer thick dielectrically passivating layer. Particularly, this may occur when the dopant is phosphorous and the dielectrically passivating layer is silicon dioxide. The masking properties of the oxide will be particularly suspect during high temperature processing. To avoid any detrimental effects of dopant diffusion during high temperature processing, an additional mask layers for instance of silicon nitride, may be deposited on the dielectric layer to mask against diffusion at the dopants contained in the transition layer.