Abstract:
A method of testing a plurality of registers in a RAMDAC, each of the registers having a plurality of bits. First, the bits of the registers are all reset to a first logic state. Then, one logic pattern is written to the registers so as to convert one bit of one of the registers into a second logic state and immediately read out. If the read logic pattern differs from the written logic pattern, an error message will be prompted. The steps are repeated until the testing of each of the bits of the registers is completed.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a technology of computer manufacturing, particularly to a method of testing RAMDAC. 
     2. Description of the Related Art 
     Computer display units use analog signals, whereas computer systems process mainly digital data. Hence, a digital-to-analog (thereafter, DAC) is found in a display control system for converting digital data into analog signals and driving the display units to display images. The digital data inputted into the DAC are from RAM, and are also referred as RAMDAC. 
     Referring to FIG. 1, a block diagram illustrates a conventional display control system. As shown in FIG. 1, the display control system  1  comprises: a display controller  10 , RAMDAC  20 , and a display memory (commonly known as video random access memory, or VRAM)  30 . The display controller  10 , RAMDAC  20  and the display memory  30  can be integrated into a single circuit board as a display adapter and coupled to the computer motherboard through an expansion slot. Moreover, the display controller  10 , RAMDAC  20  and the memory display  30  may be built into the computer motherboard. 
     The display controller  10  serves as an interface between a central processing unit (CPU)  2  and the display control system  1 . In FIG. 1, the display controller  10  communicates data through a system bus  3  with the CPU  2 , and outputs horizontal synchronous signals HSYNC and vertical synchronous signals VSYNC for synchronic control of a display unit  4 . Moreover, the data to be displayed onto the display unit  4  (thereafter, display data) are saved in the display memory  30  by the display controller  10 . The display unit  4  can be a cathode ray tube (CRT) display or a flat panel display. 
     Referring to FIG. 2, a block diagram illustrates the detailed RAMDAC  20  of FIG.  1 . In FIG. 2, the RAMDAC  20  comprises an address decoder  21 , a color lookup table  22  composed of several registers, and three DACs  23 - 25 . The display data on the address bus A (normally 8-bit data) are decoded by the address decoder  21  and utilized to select the color value stored in a corresponding register of the lookup table  22 . The selected color value is converted into R, G, B video signals by the DACs  23 - 25  to be displayed onto the display unit  4 . For example, 256 registers will be required for the color lookup table  22  to support the 320×200 pixels in 256 colors mode in VGA specification. 
     Normally, the three primary colors of R, G, and B are each represented in six bits; therefore, each register has a total of 18 bits. The color value stored in each register are provided by the CPU  2  and written therein through a data bus D. Conversely, the color values stored in the registers can be read out through the data bus D. The reading and writing operations are performed by the display controller  10  with a read/write control signal R/W (as shown in FIG.  1 ). 
     However, two requirements have yet to be met for the display control system  1  to display the correct colors. Firstly, the registers have to correctly read, write and save the color values in the color lookup table  22 . And secondly, the DACs  23 - 25  have to correctly convert the digital color values into analog R, G, and B video signals. 
     SUMMARY OF THE INVENTION 
     Therefore, the present invention provides a RAMDAC testing method, capable of testing whether registers correctly read, write and save color values and rendering even R, G, and B color layers for visual inspection whether the RAMDACs correctly convert digital color values into analog R, G, and B video signals. 
     To achieve the above objects, the present invention provides a method of testing a plurality of registers in a RAMDAC, each of the registers having a plurality of bits. First, the bits of the registers are all reset to a first logic state. Then, one logic pattern is written to the registers so as to convert one bit of one of the registers into a second logic state and immediately read out. If the read logic pattern differs from the written logic pattern, an error message will be prompted. The steps are repeated until the testing of each of the bits of the registers is completed. 
     Moreover, the present invention provides a method for testing digital/analog converters in a RAMDAC. First, a display area of a display unit is divided into three display zones. Then, digital color data are converted by the digital/analog converters into analog video signals where digital color data are sequentially changed. Next, R, G, and B color layers are displayed responsive to the analog video signals in the display zones, respectively. Finally, it is determined whether the display unit displays the R, G, and B color layers evenly. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The aforementioned objects, features and advantages of the present invention will become apparent by referring to the following detailed description of a preferred embodiment with reference to the accompanying drawings, wherein: 
     FIG. 1 is a block diagram illustrating a conventional computer display control system; 
     FIG. 2 is a block diagram illustrating the details of RAMDAC  20  of FIG. 1; 
     FIGS. 3A-3G are flowcharts illustrating the register testing method in accordance with a first preferred embodiment of the present invention; 
     FIGS. 4A-4G are flowcharts illustrating the testing method of registers in accordance with a second preferred embodiment of the present invention; and 
     FIG. 5 is a flowchart illustrating the display method of even layers of R, G, B colors in accordance with one preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The correct display of colors for a control display system  1  is contingent upon the correct read, write and save of registers in the color lookup table  22  and the correct conversion of digital color value into analog R, G, and B video signals. Therefore, the RAMDAC testing method of the present invention is basically divided into two aspects: register testing method and displaying method of even R, G, and B color layers. The former method detects whether registers can correctly read, write, and save color values; while the latter prompts for visually inspecting whether the RAMDACs correctly convert digital color data into analog R, G, and B video signals through even display of R, G, and B color layers. 
     Referring to FIGS. 3A-3G, flowcharts illustrating the register testing method in accordance with a first preferred embodiment of the present invention. This embodiment is specified with examples of R, G, B color layers represented in six bits. 
     Referring to FIG. 3A, first the color value in each register of the RAMDAC is reset to 0 in step S 1 . Next, the initial values of N and I are respectively set to 1 in steps S 2  and S 3 . Further (I, 0, 0) is written into the R, G, and B color values in the register N (R N ,G N ,B N ) in step S 4 . Furthermore, the initial value of J is set to 1 in step S 5 ; and the R, G, and B colorvalues (R J ,G J ,B J ) are read from the register J in step S 6 ; followed by step S 7 , wherein it is determined whether J is equal to N. 
     Referring to FIG. 3B, if it is known that J equals N in step S 7 , then proceed to step S 8  to further determine whether the color values of the register J (R J ,G J ,B J ) equal (I,0,0). If not, then proceed to step S 9  to display an error message. If in step S 7 , it is known that J does not equal N, then proceed to step S 10  to determine whether the R, G, and B color values of the register J (R J , G J , B J ) equal (0,0,0); if not, an error message is displayed in step S 9 . If it is known in steps S 8  and S 10  that the color values of the register J (R J ,G J ,B J ) equal to (I, 0, 0) or (0,0,0), respectively, then proceed to step S 11 , wherein it is determined whether J is greater than 255. If J is smaller than or equal to 255, then proceed to step S 12  to increase the value of J by one, and return to step S 6 . If J is greater than 255, then proceed to step S 13 , wherein it is determined whether I is greater than 32; if not, then return to step S 4  after making the value of I shift left by one bit in step S 14  (that is, multiplying the value of I by 2). 
     Next, in step S 13 , if it is known that I is greater than 32, then proceed to step S 15 , as shown in FIG. 3C, to reset the color values of each register of the RAMDAC into 0. Then in step S 16 , the initial value of I is set to 1, followed by step S 17 , wherein (0, I, 0) are written into the R, G, and B color values of the register N (R N ,G N ,B N ). Further in step S 18 , the initial value of J is set to 1, followed by the step S 19 , wherein the R, G, and B color values (R J ,G J ,B J ) are read from the register J. Next, step S 20 , it is determined whether J is equal to N. 
     Referring to FIG. 3D, if in step S 20 , it is known that J equals N, then proceed to step S 21  to determine whether the R, G, and B color values (R J ,G J ,B J ) equal (0,I,0); if not, then proceed to step S 22  to display an error message. If in step S 20 , it is known that J does not equal N, then proceed to step S 23  to determine whether the R, G, and B color values (R J ,G J ,B J ) equal (0,0,0). If not, then proceed to step S 22  to display an error message. If in steps S 21  or S 23 , the R, G, and B color values (R J ,G J ,B J ) are known to equal (0,I,0) or (0,0,0) respectively, then proceed to step S 24  to determine whether J 10 is greater than 255. If J is smaller than or equal to 255, then proceed to step S 25  to increase the value of J by one and return to step S 19 . If J is greater than 255, then proceed to step S 26  to determine whether I is greater than 32; if not, then return to step S 17  after making the value of I shift left by one bit in step S 27  (that is, multiplying the value of I by 2). 
     Next, in step S 26 , if it is known that I is greater than 32, as shown in FIG. 3E, then proceed to step S 28  to reset the color values of each register of the RAMDAC to 0. Then in step S 29 , the initial value of I is set to 1, followed by step S 30 , wherein (0,0,I) are written into the R, G, and B color values of the register N (R N ,G N ,B N ). Further in step S 31 , the initial value of J is set to 1, followed by the step S 32 , wherein the R, G, and B color values (R J ,G J ,B J ) are read from the register J. Next, step S 33 , it is determined whether J is equal to N. 
     Referring to FIG. 3F, if in step S 33 , it is known that J equals N, then proceed to step S 34  to determine whether the R, G, and B color values (R J ,G J ,B J ) equal (0,0,I); if not, then proceed to step S 35  to display an error message. If in step S 33 , it is known that J does not equal N, then proceed to step S 36  to determine whether the R, G, and B color values (R J ,G J ,B J ) equal (0,0,0). If not, then proceed to step S 35  to display an error message. If in steps S 34  or S 36 , the R, G, and B color values (R J ,G J ,B J ) are known to equal (0, 0, I) or (0,0,0) respectively, then proceed to step S 37  to determine whether J is greater than 255. If J is smaller than or equal to 255, then proceed to step S 38  to increase the value of J by one and return to step S 32 . If J is greater than 255, then proceed to step S 39  to determine whether I is greater than 32; if not, then return to step S 30  after making the value of I shift left by one bit in step S 40  (that is, multiplying the value of I by 2). 
     Referring to FIG. 3G, if in step S 39 , if it is known that I is greater than 32, then proceed to step S 41  to determine whether N is greater than 255. If not, then increase the value of N by one in step S 42  and then return to step S 3 . If N is greater than 255, then the register testing method is thereby completed. 
     Briefly, the testing method as specified in FIGS. 3A-3G resets every bit of each register to 0, then proceeds to perform reading operation after sequentially writing 1 into every bit of the registers. For example, the color values (R, G, B) being sequentially written are set to (000001,000000,000000) B , (000010,000000,000000) B , . . . , (100000,000000,000000) B , (000000,000001,000000) B , (000000,000010,000000) B , . . . , (000000,100000,000000) B , (000000,000000,000001) B , (000000,000000,000010) B , . . . , (000000,000000,100000) B  and so forth. Data will be read after being written for matching the written data with the read data and for obtaining whether registers correctly read, write, and save color values. 
     Referring to FIGS. 4A-4G, flowcharts illustrating the register testing method in accordance with a second preferred embodiment of the present invention. This embodiment is specified with examples of R, G, B color layers represented in six bits. 
     Referring to FIG. 4A, first the color values in each register of the RAMDAC are reset to 1 in step S 51 . Next, the initial values of N and I are respectively set to 1 in steps S 52  and S 53 . Further (X,3F,3F), is written into the R, G, and B color value in the register N (R N ,G N ,B N ) in step S 54 , where X represents the 1&#39;s-complement of binary value I. Further, the initial value of J is set to 1 in step S 55 ; and the R, G, and B color values (R J ,G J ,B J ) are read from the register J in step S 56 ; followed by step S 57 , wherein it is determined whether J is equal to N. 
     Referring to FIG. 4B, if in step S 57 , it is known that J equals N, then proceed to step S 58  to further determine whether the color values of the register J (R J ,G J ,B J ) equal (X,3F,3F) H . If not, then an error message is displayed in step S 59 . If it is known in step S 57  that J does not equal N, then proceed to step S 60  to determine whether the R, G, and B color values of the register J (R J ,G J ,B J ) equal (3F,3F,3F) H . If not, then proceed to step S 59  to display an error message. If it is known in steps S 58  and S 60  that the color values of the register J (R J ,G J ,B J ) equal to (X,3F,3F) H  or (3F,3F,3F) H  respectively, then proceed to step S 61 , wherein it is determined whether J is greater than 255. If J is smaller than or equal to 255, then proceed to step S 62  to increase the value of J by one and return to step S 56 . If J is greater than 255, then proceed to step S 63 , wherein it is determined whether I is greater than 32. If not, then return to step S 54  after making the value of I shift left by one bit in step S 64  (that is, multiplying the value of I by 2). 
     Next, in step S 63 , if it is known that I is greater than 32, as shown in FIG. 4C, then proceed to step S 65  to reset the color values of each register of the RAMDAC into 1. Then in step S 66 , the initial value of I is set to 1, followed by step S 67 , wherein (3F,X,3F) H  are written into the R, G, and B color values of the register N (R N , G N , B N ), where X is the 1&#39;s-complement representation of I. Further in step S 68 , the initial value of J is set to 1, followed by the step S 69 , wherein the R, G, and B color values (R J ,G J ,B J ) are read from the register J. Next, step S 70 , it is determined whether J is equal to N. 
     Referring to FIG. 4D, if in step S 70 , it is known that J equals N, then proceed to step S 71  to determine whether the R, G, and B color values (R J ,G J ,B J ) equal (3F,X,3F) H ; if not, then proceed to step S 72  to display an error message. If in step S 70 , it is known that J does not equal N, then proceed to step S 73  to determine whether the R, G, and B color values (R J ,G J ,B J ) equal (3F,3F,3F) H . If not, then proceed to step S 72  to display an error message. If in steps S 71  or S 73 , the R, G, and B color values (R J ,G J ,B J ) are known to equal (3F,X,3F) H  or (3F,3F,3F) H  respectively, then proceed to step S 74  to determine whether J is greater than 255. If J is smaller than or equal to 255, then proceed to step S 75  to increase the value of J by one and return to step S 69 . If J is greater than 255, then proceed to step S 76  to determine whether I is greater than 32; if not, then return to step S 67  after making the value of I shift left by one bit in step S 77  (that is, multiplying the value of I by 2). 
     Next, in step S 76 , if it is known that I is greater than 32, as shown in FIG. 4E, then proceed to step S 78  to reset the color values of each register of the RAMDAC into 1. Then in step S 79 , the initial value of I is set to 1, followed by step S 80 , wherein the 1&#39;s-complement of I is taken to make the X value and (3F,3F,X) H  are written into the R, G, and B color values of the register N (R N ,G N ,B N ). Further in step S 81 , the initial value of J is set to 1, followed by the step S 82 , wherein the R, G, and B color values (R J , G J , B J ) are read from the register J. Next, step S 83 , it is determined whether J is equal to N. 
     Referring to FIG. 4F, if in step S 83 , it is known that J equals N, then proceed to step S 84  to determine whether the R, G, and B color values (R J , G J , B J ) equal (3F,3F,X) H ; if not, then proceed to step S 85  to display an error message; If in step S 83 , it is known that J does not equal N, then proceed to step S 86  to determine whether the R, G, and B color values (R J ,G J ,B J ) equal (3F,3F,3F) H . If not, then proceed to step S 85  to display an error message. If in steps S 84  or S 86 , the R, G, and B color values (R J ,G J ,B J ) are known to equal (3F,3F,X) H  or (3F,3F,3F) H  respectively, then proceed to step S 87  to determine whether J is greater than 255. If J is smaller than or equal to 255, then proceed to step S 88  to increase the value of J by one and return to step S 82 . If J is greater than 255, then proceed to step S 89  to determine whether I is greater than 32; if not, then return to step S 80  after making the value of I shift left by one bit in step S 90  (that is, multiplying the value of I by 2). 
     Referring to FIG. 4G, if in step S 89 , if it is known that I is greater than 32, then proceed to step S 91  to determine whether N is greater than 255. If not, then increase the value of N by one in step S 92  and then return to step S 53 . If N is greater than 255, then the register testing method is thereby completed. 
     Briefly, the testing method as specified in FIGS. 4A-4G resets every bit of each register to 1, then proceed to perform reading operation after sequentially writing 0 into every bit of the registers. For example, the color values (R, G, B) being sequentially written are set to (111110,111111,111111) B , (111101,111111,111111) B , . . . , (011111,111111,111111) B , (111111,111110,111111) B , (111111,111101,111111) B , . . . , (111111,011111,111111) B , (111111,111111,111110) B, ( 111111,111111,111101) B , . . . , (111111,111111,011111) B  and so forth. Data will be read after being written for matching the written data with the read data and for obtaining whether registers correctly read, write, and save color values. 
     Referring to FIG. 5, a flowchart illustrating the method of displaying even layers of R, G, B colors in accordance with a preferred embodiment of the present invention. In this case, a 256 color mode is given. 
     As shown in FIG. 5, first in step S 101 , the display area is divided into three, namely, R, G, and B zones. Then, the Color values are reset to 1 in step S 102 , and the color values of the registers (R,G,B) are set to (Color,Color,Color) in step S 103 . Further, in step S 104  the Color values are determined to be greater than  63  or not; if not, then proceed to step S 105  to increase the Color value by one, and proceed then to step S 106  to display the current Color values for three seconds, and return finally to step S 103 . If in step S 104 , the Color value is known to be greater than  63 , then proceed to step S 107  of visually inspecting whether the display is normal. If the display unit does not demonstrate even changes from darkness to brightness, then it means an error might have occurred when the digital color values are converted into analog R, G, and B video signals. Hence in step S 108 , it can be determined that the digital/analog converter might be corrupted. 
     Therefore, the RAMDAC testing method of the present invention can detect whether the registers can correctly read, write, and save color values; then display even R, G, and B color layers for visually inspecting whether the RAMDACs correctly convert digital color data into analog R, G, and B video signals through even display of R, G, and B color layers. 
     Although the present invention has been described in its preferred embodiment, it is not intended to limit the invention to the precise embodiment disclosed herein. Those who are skilled in this technology can still make various alterations and modifications without departing from the scope and spirit of the present invention. Therefore, the scope of the present invention shall be defined and protected by the following claims and their equivalents.