Abstract:
A zero-detection circuit is provided. The zero-detection circuit includes a plurality of transistor stacks. Each transistor stack includes an input transistor and a clocked transistor. Each of the plurality of input transistors receives a data input. An intermediate node is connected to the input transistor stacks. An output stage is coupled to the intermediate node providing an output. The output stage includes a bit selection control circuit receiving a bit selection signal. The bit selection control circuit provides a zero level output of the output stage responsive to a predefined bit selection signal. The transistor stacks comprise silicon-on-insulator (SOI) transistors.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a high speed microprocessor zero detection circuit with 32-bit and 64-bit modes. 
     DESCRIPTION OF THE RELATED ART 
     Silicon-on-insulator (SOI) technology is an enhanced silicon technology currently being utilized to increase the performance of digital logic circuits. Utilizing SOI technology designers can increase the speed of digital logic integrated circuits while reducing their overall power consumption. These advances in technology will lead to the development of more complex and faster computer integrated circuits that operate with less power. 
     As shown in FIG. 1, SOI semiconductors include a thin layer of silicon placed on top of an insulator, such as silicon dioxide (SiO 2 ) or glass, and a MOS transistor built on top of this structure. The main advantage of constructing the MOS transistor on top of an insulator layer is to reduce the internal capacitance of the transistor. This is accomplished by placing the insulator oxide layer between the silicon substrate and the impurities required for the device to operate as a transistor. Reducing the internal capacitance of the transistor increases its operating speed. With SOI technology faster MOS transistors can be manufactured resulting in higher performance semiconductors for faster electronic devices. 
     Referring to FIGS. 1 and 2, there is shown the SOI FET and the parasitic bipolar device. With SOI FETs, by placing a MOS transistor on top of a SOI layer, the MOS transistor is actually placed in parallel with a bipolar junction transistor, as illustrated in FIG.  2 . If enough current is passed through the MOS transistor, the parasitic bipolar transistor will turn on. The parasitic bipolar transistor has a small current gain. 
     Normally, parasitic bipolar action does not manifest itself in conventional, bulk, NMOS transistors because the base of the bipolar transistor is always kept at ground potential, keeping the bipolar transistor turned off. In conventional, bulk, PMOS transistors the body of the PFET is tied to a supply rail Vdd. In the SOI FET, the body (B) of the MOS FET device, or base of the bipolar transistor, is floating and can be charged high by junction leakages induced when both drain (D) and source (S) terminals of the MOS FET are at a high potential. Subsequently, if the source (S) is pulled to a low potential, the trapped charge in the base area (B) is available as parasitic base current. The parasitic base current activates the bipolar transistor and generates a collector current at the drain terminal of the MOS FET. 
     In Arithmetic Logic Units (ALUs) it is necessary to set a condition code register after an arithmetic operation to specify whether or not the result of the operation was zero. The circuits that accomplish this are typically critical timing paths of the microprocessor. A complication is that the ALU must support not only 64-bit data, but also 32-bit data in order to maintain backward compatibility with previous generations of microprocessors. 
     FIG. 3 shows a typical Domino circuit that would be used as part of a large circuit implementing this function. If zero detection on only 32 bits of the 64-bit datum is desired, the MODE 64  signal will be set to 0 on some instances of this circuit, thus disabling the other 32-bits that are not to be included in the computation. This feature is also very important in improving the testability of the Zero-Detection circuit. It is very difficult to make this circuit work with Silicon-on-Insulator (SOI) technology because the bipolar discharge problem associated with SOI technology is very severe for this particular topology. 
     The 32/64-bit selection has to be included in the NFET tree via transistors T 0  to TN, which introduces the bipolar discharge problem because the bodies of transistors N 0  through NN can now be charged to the power supply. The number of NMOS transistor stacks, N in FIG. 3, must be large because when the entire circuit is put together it must cover all 64 bits of the datum. N will be anywhere from 4 to 16, which makes the bipolar discharge problem severe, and because the transistors in the stack must be very large to meet the timing requirements, the problem is even more severe. The resulting error from the bipolar discharge is that node PRE may be accidentally discharged, thus giving an incorrect result in the machine. 
     SUMMARY OF THE INVENTION 
     A principal object of the present invention is to provide a zero-detection circuit. Other objects are to provide such a zero-detection circuit substantially without negative effects and that overcomes many of the disadvantages of prior art arrangements. 
     In brief, a zero-detection circuit is provided. The zero-detection circuit includes a plurality of transistor stacks. Each transistor stack includes an input transistor and a clocked transistor. Each of the plurality of input transistors receives a data input. An intermediate node is connected to the input transistor stacks. An output stage is coupled to the intermediate node providing an output. The output stage includes a bit selection control circuit receiving a bit selection signal. The bit selection control circuit provides a zero level output of the output stage responsive to a predefined bit selection signal. 
     In accordance with features of the invention, the transistor stacks comprise silicon-on-insulator (SOI) transistors. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein: 
     FIG. 1 is a cross sectional view illustrating a conventional silicon-on-insulator (SOI) N-channel field effect transistor (NFET); 
     FIG. 2 is a schematic diagram illustrating the conventional silicon-on-insulator (SOI) N-channel field effect transistor (NFET) of FIG. 1 including a bipolar junction transistor; 
     FIG. 3 is a schematic diagram illustrating a prior art Domino circuit used in a zero detection circuit; and 
     FIGS. 4A and 4B together provide a schematic diagram illustrating a silicon-on-insulator (SOI) zero detection circuit of the preferred embodiment. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIGS. 4A and 4B, there is shown a high speed microprocessor zero-detection circuit generally designated by the reference character  100  of the preferred embodiment. In accordance with features of the invention, high speed microprocessor zero-detection circuit  100  integrates the 32/64-bit selection into the output stage of the domino gate. A significant advantage is that the bipolar discharge problem is eliminated completely while maintaining the required high-speed circuit operation at the same time. Because the bipolar discharge effect is eliminated, N may be as large as necessary allowing the designer more flexibility in selecting it, and also the NMOS transistors may be sized as large as needed to meet the timing requirements. An additional benefit is the NMOS stack height is now two instead of the three in the prior art arrangement of FIG. 3, so some more speed is gained. A novel weak feedback scheme is also implemented for correct operation at any clock frequency. 
     In FIGS. 4A and 4B, high speed microprocessor zero-detection circuit  100  is shown as two stages of 8-wide Domino OR gates; so N has been chosen to be 8 for purposes of example in a first stage generally designated as  100 A. It should be understood that the zero-detection circuit  100  could consist of a first stage that is 4-wide and a second stage that is 16-wide, as another example. The 32/64-bit selection has been incorporated into an output of the first stage  100 A. Respective data  0 - 7  are applied to a gate input of silicon-on-insulator (SOI) N-channel field effect transistors NFETs N 0 -N 7 ,  102 ,  104 ,  106 ,  108 ,  110 ,  112 ,  114  and  116 . A clock input CLK is applied to a gate of silicon-on-insulator (SOI) NFETs  118 ,  120 ,  122 ,  124 ,  126 ,  128 ,  130  and  132  that are connected in a stack with NFETs N 0 -N 7 ,  102 ,  104 ,  106 ,  108 ,  110 ,  112 ,  114  and  116 . A clock input CLK is applied to a gate of silicon-on-insulator (SOI) P-channel field effect transistor PFET  134  that is connected between a supply voltage VDD and an intermediate node PRE_LEV 1  and to the drain of NFETs N 0 -N 7 ,  102 ,  104 ,  106 ,  108 ,  110 ,  112 ,  114  and  116 . A pair of silicon-on-insulator (SOI) PFETs P 0 , P 1 ,  136  and  138  are connected between the supply voltage VDD and intermediate node PRE_LEV 1 . A first inverter  140  receives MODE 64  input and provides an output MODE 64 _L applied to the gate of PFET  136 , P 0  and applied to a second inverter  142 . An output VMODE  64  of inverter  142  is applied to a source of PFET  144 , P 9  that is connected to the drains of NFETs  146  and  148 , N 9 , N 8  at an output node OUT LEV 1 . The gate of PFET P 1 ,  138  is connected to node OUT LEV 1 . The gate of PFET  144 , P 9  is connected to the gate of NFET  146 , N 9  at intermediate node PRE LEV 1 . Reducing the stack height to two in this stage  100 A completely eliminates the bipolar discharge problem because the bodies of NFETs N 0 -N 7 ,  102 ,  104 ,  106 ,  108 ,  110 ,  112 ,  114  and  116  can never be charged very high, as CLK is turning on every cycle. The function of microprocessor zero-detection circuit  100  of FIGS. 4A and 4B is still the same as in FIG.  3 . If MODE 64 =0 then the first stage  100 A is disabled because MODE 64 _L is a 1 and NFET  148 , N 8  forces the output of the first stage, OUT_LEV 1 , to a 0. Inverter  142  prevents any contention between PFET  144 , P 9  and NFET N 8 ,  148  because VMODE 64  will be a 0, and PFET  144 , P 9  is not powered at its source. Thus, even if PRE_LEV 1  is pulled low by one or more of the DATA pins, PFET  144 , P 9  will not fight NFET N 8 ,  148 , and the correct value of 0 is generated on OUT_LEV 1 . Then circuit  100 A is disabled from taking part in the zero detection, DATA  0  to  7  are ignored. 
     If MODE 64 =1, then MODE 64 _L is a 0, VMODE 64  is a 1, PFET  144 , P 9  is now powered at its source, the weak feedback branch consisting of PFETS, P 0 , P 1   136 ,  138  is enabled, NFET N 8 ,  148  is OFF, and the circuit  100 A operates as a standard Domino circuit. If any of the DATA pins are high, then PRE_LEV 1  is pulled low during the Evaluate phase, OUT_LEV 1  is pulled high by PFET  144 , P 9  and the PMOS transistor in inverter  142 , and the weak feedback branch is disabled by PFET  138 , P 1 . This case is the regular evaluation of a Domino circuit. If all of the DATA pins are low, then PRE_LEV 1  remains high, OUT_LEV 1  remains low, and the weak feedback branch maintains this circuit in this state no matter how low the clock frequency is. Thus, whether or not the circuit  100 A evaluates, it is taking part in the zero detection, with DATA  0  to  7  involved in the computation, and zero-detection circuit  100 A is producing the correct result for both cases. 
     PFET  136 , P 0  is required to prevent possible contention, and the ensuing wasted power, between PFET  138 , P 1  and any of the NMOS stacks when one or more of the DATA pins are high, and the circuit should be disabled. Setting MODE 64 =0 will cause NFET  148 , N 8  to pull OUT_LEV 1  down, which, if the source of PFET  138 , P 1  were connected to the supply Vdd, would cause both P 1  and one or more of the NFET stacks to be on at the same time, causing the wasted power. 
     Referring to FIG. 4B, there is shown a second stage generally designated as  100 B in accordance with the preferred embodiment. OUT LEV 1  is applied to a gate of a silicon-on-insulator (SOI) NFET  150  connected between a node PRE_LEV 2  and ground. Additional silicon-on-insulator (SOI) NFETs  152 ,  154 ,  156 ,  158 ,  160 ,  162  and  164  are gated by respective outputs of seven identical zero-detection circuits  100 A. A clocked PFET  166  is connected between the supply voltage and node PRE_LEV 2 . A PFET  168  is connected between the supply voltage and node PRE_LEV 2 . An inverter  170  is connected at its input to node PRE_LEV 2  and provides an output RESULT_IS_ZERO_L. The output of inverter  170  is applied to the gate of PFET  168 . 
     While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing, these details are not intended to limit the scope of the invention as claimed in the appended claims.