Abstract:
A distortion compensated differential circuit. One embodiment of the circuit includes a differential follower stage comprising first (T 1 ) and second (T 1 ) transistors having their respective collectors connected to a supply voltage source (V cc ). The bases of these transistors receive a first (V 1 ) and a second (V 2 ) input signal and their emitters are coupled together by a first impedance (Z) and are further connected to a first (I 1 ) and a second (I 1 ) current source, respectively. The connections between the emitters of the first and the second transistors and the first and the second current sources, respectively, are made via the base-emitter paths of third (T 11 ) and fourth (T 12 ) transistors, respectively. The collectors of the third (T 11 ) and the fourth (T 12 ) transistors are connected to the bases of the fourth (T 12 ) and the third (T 11 ) transistors, respectively. The emitters of the third (T 12 ) and the fourth (T 12 ) transistors are coupled to one another by at least a second impedance (Z&#39;) of a nominal value which is less than that of the first impedance.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a distortion-compensated differential circuit which comprises a differential stage comprising a first and a second transistor whose emitters are coupled by a first impedance, and input terminals for an input signal source, and which also comprises a distortion compensation circuit comprising in series between the emitter of the first transistor and a first current source, a first diode as well as the main current path of a third transistor, and also comprising, in series between the emitter of the second transistor and a second current source, a second diode as well as the main current path of a fourth transistor, which third and fourth transistors have their respective bases and collectors interconnected and have their emitters coupled by a second impedance. 
     Such a differential circuit is known from U.S. Pat. No. 4,682,098 in the form of a voltage-current converter comprising a voltage source V, the first impedance being constituted by a resistor which converts said voltage into a current which is amplified by a translinear circuit comprising four transistors. The first and the second transistor have their collectors as well as their bases interconnected. In order to compensate for conversion non-linearity caused by the non-linearity of the emitter resistance of the first and the second transistor, U.S. Pat. No. 4,682,098 couples a resistor of the same value as the first resistor between the emitters of the third and the fourth transistor. 
     This compensation provides very remarkable results in the case of small signals. 
     However, in particular in the case of flash-type fold and interpolation analog-to-digital converters, there is a need to provide compensation over a very wide dynamic range, up to levels of several volts at the output of a differential amplifier. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to provide such a compensation. 
     To this end the second impedance has a nominal value smaller than that of the first impedance. 
     As will be demonstrated hereinafter, this very simple modification enables the distortion figures to be improved by providing compensation for the base currents of the third and the fourth transistor, at least to a specific degree. 
     In a preferred embodiment the circuit is characterized in that the ratio between the second impedance and the first impedance is within the range of values from 0.65 to 0.85. 
     In a first modification, derived from said U.S. Pat. No. 4,468,098, the differential stage is adapted to form a voltage-current converter, said input terminals being arranged in series with the first impedance. 
     In a second modification the differential stage is adapted to form a differential follower, the bases of the first and the second transistor forming said input terminals. 
     The invention also relates to a multiple follower circuit, in particular for use in flash-type folding and interpolation analog-to-digital converters. 
     Such a multiple follower circuit comprises a plurality of differential follower circuits as defined above, the first, the second, the third and the fourth transistor of the differential follower circuit of the rank i being denominated T i   A , T i   A , T i   c  and T i   c  respectively. This multiple follower circuit, comprises first impedances connected between the emitters of at least some of the transistors of a first group comprising the first and the second transistor, the admittance of said first impedances being designated Y followed by two indexes corresponding to those of the two transistors of said first group between whose emitters said impedance is connected, and second impedances connected between the emitters of at least some of the transistors of a second group comprising the third and the fourth transistor, the admittance of said second impedances being designated Y&#39; followed by two indexes corresponding to those of the two transistors of said second group between whose emitters said impedance is connected, and regardless of i, j, i and j the following is valid 
     
         Y.sub.ij =Y.sub.j -&gt;Y&#39;.sub.ij =Y&#39;.sub.j - 
    
     
         Y.sub.ij =Y.sub.j -&gt;Y&#39;.sub.ij =Y&#39;- 
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will now be described in more detail, by way of non-limitative example, with reference to the accompanying drawings, in which: 
     FIG. 1 shows a voltage-current converter in accordance with U.S. Pat. No. 4,682,098, 
     FIG. 2 shows a prior-art differential follower circuit, 
     FIG. 3 shows a preferred embodiment of a differential follower circuit in accordance the invention, 
     FIGS. 4 and 5 are curves illustrating the optimisation of the distortion, 
     FIG. 6 shows a multiple follower circuit in accordance with the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In FIG. 1 a voltage-current converter comprises a source I&#39; 1  of current (value 2 I o ) coupled to a terminal 1, which is at a reference potential, by means of a diode-connected transistor Q 1  and to a terminal 2 by means of a diode-connected transistor Q 2 . The bases of the transistors Q 3  and Q 4  are connected to the terminals 1 and 2, respectively. The emitters of the transistors Q 3  and Q 4  are coupled to a source I&#39; 2  of current (value 2I x ). A voltage source V and a resistor R 1  are arranged in series between the terminals 1 and 2, the resistor R 1  producing a voltage-to-current conversion. The current is amplified by the translinear circuit (Q 1 , Q 2 , Q 3  and Q 4 ) and is supplied to the output by the transistors T 9  and T 10 . A compensation circuit 5 provides correction for the non-linearity of the emitter resistance R e  Q 1  and R e   Q   2  of the transistors Q 1  and Q 2  respectively. 
     Between the terminal 1 and a source I&#39; 3  of current (value I 0 ) this circuit comprises the series arrangement of a diode-connected transistor Q 7  and the main current path of a transistor Q 5 . Between the terminal 2 and a source I&#39; 4  of current (value I 0 ) this circuit further comprises the series arrangement of a diode-connected transistor Q 8  and the main current path of a transistor Q 6 . 
     The transistors Q 5  and Q 6  have their respective bases and collectors interconnected. 
     To provide compensation for the emitter resistances R e  Q 1  and R e  Q 2 , a resistor R&#39; 2  of the same value R as the resistor R&#39; 1  is connected between the emitters of the transistors Q 5  and Q 6 . 
     As will be shown, in order to provide compensation for the emitter resistances of the differential followers in accordance with the present invention, it is only necessary to reduce the resistance value of R&#39; 2  so that R&#39; 2  /R&#39; 1  is in the range of values between 0.65 to 0.85. 
     A prior-art differential follower circuit (FIG. 2) comprises transistors T 1  and T1, in the present case each is of the npn type, whose collectors are connected to a supply voltage source V cc , whose bases are adapted to receive a differential input signal V 1  and V 2 , and whose emitters are interconnected by a series arrangement of resistors R, R&#39;, R&#34;. Two current sources of the same value I 1  and I 1  are connected to the emitters of the transistors T 1  and T 1  respectively. The nodes between the resistors R and R&#39; and between the resistors R&#39; and R&#34; form the outputs S 1  and S 2 , which are at intermediate voltages between the voltages V 1  and V 2 . Such intermediate voltages are employed in folding and interpolation analog-to-digital converters. 
     Such converters are described in, for example, the document by Rudy J. van de Plassche &#34;High Speed and High Resolution A/D and D/A converters&#34;, Ph. D. Thesis University of Technology (Delft, The Netherlands, published Oct. 1989). In this case the intermediate signals are the coder signals which are interpolated starting from the folding signals. Such converters require high voltage levels (for example, of several volts) with a satisfactory linearity, which is essential for the correct performance of said converters. 
     The currents in the collector-emitter path of the transistors T 1  and T 1  are I 1  -ΔI and I 1  +ΔI respectively, ΔI being the current flowing from the emitter of T 1  to the emitter of T 1  through the resistors R, R&#39; and R&#34;. As a result of this, the signals V 1  and V 2  can be reproduced correctly on the emitters of T 1  and T 1  (signals W 1  and W 2 ) only if I 1  is much larger than ΔI. Moreover, as the currents through T 1  and T 1  vary, the base currents drawn under dynamic conditions may be large except if I 1  is larger than ΔI. 
     The distortion (its absolute value) D 1  of this arrangement is: ##EQU1## where R B  and R B  are the base and emitter lead resistances, β is the current gain of said transistors, and V T  =26 mV. 
     In FIG. 3 two transistors T 11  and T 12  have their base-emitter paths arranged between the emitters of the transistors T 1  and T 1  and the current sources I 1  and I 1  respectively and their bases and collectors cross-coupled, i.e. the collector of T 11  is connected to the base of T 12  and the collector of T 12  is connected to the base of T 11 . The emitters of the transistors T 1  and T 1  are connected by an impedance Z and those of the transistors T 11  and T 12  are connected by an impedance Z&#39;, which in accordance with the teaching of U.S. Pat. No. 4,682,098 should have the same value as Z. The impedance Z may be, for example, a chain of resistors, such as the resistors R, R&#39; and R&#34; in FIG. 2. The diodes T 21  and T 22  are arranged in series with the main current paths (collector-emitter paths) of the transistors T 11  and T 12 , respectively. 
     The emitters of the transistors T 1  and T 1  should always maintain the same current I 1 . This results in a reduction of the base currents drawn from T 1  and from T 1  under dynamic conditions. Moreover, since I 1  should no longer be substantially larger than ΔI it is possible to use transistors T 1  and T 1  of smaller dimensions, which additionally reduces the current drained from the inputs under dynamic conditions. However, such a compensation only performs satisfactorily for signals of comparatively small amplitude. 
     In FIG. 3 the two transistors T 22  and T 21 , connected as diodes by a base-collector short-circuit, are arranged between the emitter of the transistor T 1  and the base of the transistor T 11  and between the emitter of the transistor T 1  and the base of the transistor T 11 . When T 21 , T 11 , T 22  and T 12  have the same dimensions (the same base-emitter voltage for the same current), the accumulated base-emitter voltage drops in T 21  and T 11  and in T 22  and T 12  are the same (the influence of the base currents being ignored), so that the distortion is reduced. 
     Let D 3  be the distortion (absolute value) of this arrangement. 
     
         D.sub.3 =(V.sub.1 -V.sub.2)-(W.sub.1 -W.sub.2). 
    
     It is assumed that: 
     
         E-(W.sub.1 -W.sub.2)-(X.sub.1 -X.sub.2) 
    
     and 
     
         D.sub.4 =(V.sub.1 -V.sub.2)-(X.sub.1 -X.sub.2)=D.sub.3 +E. 
    
     It is assumed that ΔI&#39;=the current through the resistance Z&#39;, ΔI again being the current through the resistance Z, and the current sources I 1  and I 1  having the same intensity I. 
     The current through the emitter of T 11  is equal to I 1  +ΔI 1   &#39; , so that its base current is ##EQU2## and its collector current is (I 1  +ΔI&#39;)+  where β is the current gain or a transistor. 
     The current through the emitter of T 12  is equal to I 1  -ΔI&#39;, so that its base current is ##EQU3## and its collector current is (I 1  -ΔI&#39;) ##EQU4## assuming that T 11  and T 12  are identical. 
     Consequently, the current I 21  through the diode-connected transistor T 21  is equal to: ##EQU5## Therefore, the current I 22  through the diode-connected transistor T 22  is: ##EQU6## This means that: ##EQU7## This yields ##EQU8## When it is assumed that D 3  0 (zero distortion) it follows that: ##EQU9## so that: ##EQU10## Thus it is possible to eliminate the distortion for a given value of ΔV (E depends on ΔV). The formula shows that R 2  is smaller than R 0 , so that it is possible to achieve compensation by adding a resistor in parallel as already indicated. 
     EXAMPLE: ##EQU11## This maximum value of 0.3% corresponds to a precision better than 0.25 bit for a 6-bit converter stage used in an 8-bit folding and interpolation converter. 
     With R 2  =R 0  the maximum distortion would have been more than 0.7%. In practice, the calculation of the ratio R 2  /R 0  requires computations up to the 5th order and makes it also necessary to allow for the variation of the current gain β of the transistors as a function of the current and of the Early effect. 
     This ratio can be adjusted by plotting the curves D 3  as function of ΔV for different values of the ratio R 2  /R 0  either with a test circuit or with a simulator. Suitable software for the last-mentioned case is available in the public-domain program SPICE II of the Berkeley University &#34;General Purpose Electronic Simulator&#34;. The values of the ratio R 2  /R 0  which can be used in practice are generally in the range between 0.65 and 0.85. A satisfactory criterion is to adjust the ratio R 2  /R 0  in such a way that the positive and negative maximum values of the distortion D 3  have equal absolute values. For circuits operating in a specific frequency range adjustment is preferably effected at the maximum operating frequency. 
     It is to be noted that in integrated circuit technology the ratios between resistors are very precise. With current technology this means that the difference between two resistors of the same nominal value is less than 1%. However, the precision on the absolute values is substantially smaller. An advantage of this compensation is that it is the ratio between R 2  and R 0  which counts. 
     FIGS. 4 and 5 show ΔV (=V 1  -V 2 ), W 1  -W 2 , X 1-X   2 , D 3  and D 4  plotted along the Y-axis as a function of ΔV=V 1  -V 2  (along the X-axis) expressed in per cent of the maximum amplitude of ΔV. D 3  and D 4  have been scaled down along the Y-axis to show the variations more clearly. 
     In the situation shown in FIG. 4 R 2  =R 0 . The distortion D 3  increases regularly as a function of ΔV. 
     In the situation shown in FIG. 5 R 2  &lt;R 0 . The distortion D 3  (solid curve for R 2  /R 0  =0.95) is initially slightly negative, is then eliminated for a given ΔV (see formula above), and the maximum distortion is smaller than before. The distortion D 4  is larger than in the situation of FIG. 4. The broken-line curve shows D 3  for a value of R 2  smaller than before and in the above example it includes R 2  /R 0  =0.8. For small values of ΔV the curve D 3  is more oriented towards the negative values. D 3  passes through the value 0 for a value of ΔV larger than before and the distortion for ΔV=100% of the scale is smaller than before. 
     In practice it is thus possible to choose a value for R 2  by means of which the distortion D 3  can be optimized in accordance with a selected criterion, for example a (positive or negative) maximum distortion below a given value or rather a positive distortion below a given mid-scale value, the curves and the value of R 2  being preferably obtained by simulation. 
     FIG. 6 shows a circuit arrangement combining a plurality of elementary circuits as defined above and in which the admittances can be arranged between the emitters of all the transistors (i.e. not only those of the same pair). It is assumed that: ##EQU12## are the transistor pairs receiving the same input signals. Y 12  is an admittance arranged between the emitters of the transistors T 1   A  and T.sub. 2   A . 
     Y 12  is an admittance arranged between the emitters of the transistors T 1   A  and T 2   A   
     In more general terms: 
     Y ij  or Y ji , regardless of the values of i and j, represents the admittance of an impedance (or of a network) arranged between the emitters of the transistors T i   A  and T J   A . 
     Y ij  or Y ji , regardless of the values of i and j, represents the admittance of an impedance (or of a network) arranged between the emitters of the transistors T i   A  and T j   A . 
     It is assumed that: ##EQU13##  are the diode-connected compensation transistors associated with the aforementioned transistors bearing the same index numeral. 
     Finally, it is assumed that: ##EQU14##  are the transistor pairs with cross-coupled base-collector interconnections associated with the preceding pairs having two similar index numerals. 
     Y&#39; 12  is the admittance of an impedance or of a network arranged between the emitters of the transistors T 1   c  and T 2   c   
     Y&#39; 12  is the admittance of an impedance or a network arranged between the emitters of the transistors T 1   c  and T 2   c   
     Y&#39; ij  or Y&#39; ji  (regardless of i, j) is the admittance of an impedance or a network arranged between the emitters of the transistors T i   c  and T j   c   
     Y&#39; ij  or Y&#39; ji  (regardless of i, j) is the admittance of an impedance or a network arranged between the emitters of the transistors T i   C  and T j   c   
     If it is assumed that the input signals driving the input transistors (T 1   A  . . . T j   A ) differential signals having the same common-mode voltage, an optimum operation is obtained if the following requirements are met: 
     
         Y.sub.i&#39;J =Y.sub.J&#39;J 
    
     
         Y.sub.i&#39;J =Y.sub.i&#39;J 
    
     which ensures an equilibrium of the currents. This also holds for the admittances Y&#39;: 
     
         Y&#39;.sub.i,J =Y&#39;.sub.i&#39;J 
    
     
         Y&#39;.sub.i,J =Y&#39;.sub.i,J 
    
     The admittances Y&#39; ij  (i.e. arranged between the emitters of the same pair) have a nominal value smaller than the admittances Y i ,ij.