Abstract:
The invention relates to a structure comprising an n-type substrate ( 1 ) having a bottom surface ( 10 ) and a top surface ( 11 ), a drain (D) contacting the bottom surface ( 10 ) of the substrate ( 1 ), a first n-type semiconductor region ( 2 ) having a top surface ( 21 ) provided with a contact area ( 210 ), a source (S) contacting the contact area ( 210 ), and a second p-type semiconductor region ( 3 ) arranged inside the first semiconductor region ( 2 ) and defining first and second conduction channels (C 1,  C 2 ) between the drain and the source, characterized in that said structure comprises first and second metal gratings (G 1,  G 2 ), each of which has a portion ( 40, 71 ) contacting the first semiconductor region ( 2 ) so as to form a Schottky junction.

Description:
TECHNICAL FIELD 
       [0001]    The invention relates to a semiconducting structure for an electronic power switch as well as to an electronic power switch including a plurality of such semiconducting structures. 
       BRIEF DESCRIPTION OF RELATED ART 
       [0002]    A semiconducting structure of an electronic power switch known from the state of the art, notably from document U.S. Pat. No. 6,459,108, includes: 
         [0003]    a substrate of a first type of conductivity, having a lower face and an upper face, 
         [0004]    a drain electrode in contact with the lower face of the substrate, 
         [0005]    a first semiconducting region of the first type of conductivity, having a lower surface laid out on the upper face of the substrate, and an upper surface provided with a contact area, 
         [0006]    a source electrode in contact with the contact area of the first semiconducting region, 
         [0007]    a second semiconducting region of a second type of conductivity, laid out inside the first semiconducting region, under the contact area so as to delimit a first vertical conduction channel of the first type of conductivity and a second lateral conduction channel of the first type of conductivity between the drain electrode and the source electrode, the first and the second semiconducting region forming a first junction of the p-n type, 
         [0008]    a third semiconducting region, of the second type of conductivity, laid out on the upper surface of the first semiconducting region and at a distance from the contact area, the first and the third semiconducting region forming a second junction of the p-n type, 
         [0009]    a gate electrode in contact with the third semiconducting region. 
         [0010]    Such a semiconducting structure from the state of the art is a structure of a transistor of the JFET (acronym for Junction Field Effect Transistor) type with which an electronic power switch may be obtained. Subsequently, for the sake of simplicity, the terms of &lt;&lt;drain&gt;&gt;, &lt;&lt;source&gt;&gt; and &lt;&lt;gate&gt;&gt; may respectively be substituted for the expressions of drain electrode, source electrode and gate electrode. 
         [0011]    When the bias voltage between the drain and the source, noted as V DS , is negative, in particular less than or equal to −3 V, the diode formed by the source, the gate and the second p-n junction provides a parasitic bipolar current altering the electric performances of the semiconducting structure. In this respect, because of the presence of the second p-n junction, the current flowing between the drain and the source, noted as I DS , is strongly limited while the current flowing between the gate and the source, noted as I GS , is sufficiently great for being able to damage the semiconducting structure. 
       BRIEF SUMMARY 
       [0012]    The present invention aims at finding entirely or partly a remedy to the aforementioned drawbacks and relates to a semiconducting structure for an electronic power switch, including: 
         [0013]    a substrate of a first type of conductivity, having a lower face and an upper face, 
         [0014]    a drain electrode in contact with the lower face of the substrate, 
         [0015]    a first semiconducting region, of the first type of conductivity, having a lower surface laid out on the upper face of the substrate, and an upper surface provided with a contact area, 
         [0016]    a source electrode in contact with the contact area of the first semiconducting region, 
         [0017]    a second semiconducting region, of a second type of conductivity, laid out inside the first semiconducting region, under the contact area, so as to delimit a first and a second conduction channel of the first type of conductivity between the drain electrode and the source electrode, 
         [0018]    the semiconducting structure being remarkable in that it includes: 
         [0019]    a first metal gate electrode having at least one first portion in contact with the second semiconducting region, and at least one second portion in contact with the first semiconducting region so as to form a first junction of the Schottky type, and 
         [0020]    a second metal gate electrode having at least one first portion in contact with the upper surface of the first semiconducting region so as to form a second junction of the Schottky type, the second gate electrode being laid out at a distance from the contact area. 
         [0021]    Thus, such a semiconducting structure according to the invention gives the possibility of doing without a second junction of the p-n type and thereby without a diode providing a parasitic bipolar current when V DS  is negative. 
         [0022]    The first gate, the source and the first junction of the Schottky type form a first diode of the Schottky type providing a unipolar current of majority carriers allowing, when V DS  is negative, reduction of I GS  (current flowing between the first gate and the source) in order to protect at best the first gate and the semiconducting structure. 
         [0023]    Also, the second gate, the source and the second junction of the Schottky type form a second diode of the Schottky type providing a unipolar current of majority carriers allowing, when V DS  is negative, reduction of I GS  (current flowing between the second gate and the source) in order to protect at best the second gate and the semiconducting structure. 
         [0024]    The aforementioned first and second diodes of the Schottky type moreover allow an increase in I DS  in order to improve the performances of the semiconducting structure in terms of electric conduction. 
         [0025]    Moreover, such a semiconducting structure includes two gates, instead of a single one, for controlling the power switch, with which it is possible to contemplate an increase in the switching rate of the switch. This increase in the switching rate is possible by the reduction of the charge stored in such a structure because of unipolar conduction. 
         [0026]    In an embodiment, the second semiconducting region includes at least one box, of the second type of conductivity, laid out under the second portion of the first gate electrode so as to delimit a first junction of the Schottky type on either side of said or each box. 
         [0027]    Thus, said box(es) and the first junctions of the Schottky type are interdigitated so as to form with the first gate and the source, a diode of the JBS (acronym for Junction Barrier Schottky) type. Such a JBS diode allows reduction of I GS  (current flowing between the first gate electrode and the source electrode) and an increase of I DS  relatively to a p-n diode of the state of the art formed by the source, the gate and the second p-n junction. 
         [0028]    Advantageously, each box has a doping level of the second type of conductivity suitable for forming an ohmic contact with the first gate electrode. 
         [0029]    Such thereby formed ohmic contacts allow reduction in the electric field applied to each first junction of the Schottky type in order to reduce the risks of rapid degradation of each first junction of the Schottky type. 
         [0030]    In an embodiment, the upper face of the first semiconducting region includes at least one box, of the second type of conductivity, laid out under the first portion of the second gate electrodes so as to delimit a second junction of the Schottky type on either side of said or each box. 
         [0031]    Thus, the box(es) and the second junctions of the Schottky type are interdigitated so as to form with the second gate and the source, a diode of the JBS type. Such a JBS diode allows reduction of I GS  (current flowing between the second gate electrode and the source electrode) and increase of I DS  relatively to a p-n diode of the state of the art formed by the source, the gate and the second p-n junction. 
         [0032]    Advantageously, each box has a doping level of the second type of conductivity suitable for forming an ohmic contact with the second gate electrode. 
         [0033]    Such thereby formed ohmic contacts allow reduction in the electric field applied to each second junction of the Schottky type in order to reduce the risks of rapid degradation of each second junction of the Schottky type. 
         [0034]    In an embodiment, the semiconducting structure includes a dielectric layer, preferably made in silica, laid out on the upper face of the first semiconducting region, and the second gate electrode has at least one second portion surmounting the dielectric layer. 
         [0035]    Thus, the presence of a dielectric layer allows reduction in the leakage currents through said or each second portion of the second gate. 
         [0036]    Advantageously, the contact area has a doping level of the first type of conductivity suitable for forming an ohmic contact with the source electrode. 
         [0037]    Advantageously, the substrate has a doping level of the first type of conductivity suitable for forming an ohmic contact with the drain electrode. 
         [0038]    Advantageously, the second semiconducting region has a doping level of the second type of conductivity suitable for forming an ohmic contact with the first gate electrode. 
         [0039]    According to an embodiment, the second conduction channel extends along a second substantially vertical direction and the first conduction channel extends along a first direction substantially perpendicular to the second direction. 
         [0040]    In an embodiment, the semiconducting structure includes at least one protection layer of the second type of conductivity laid out at the periphery of a junction between the first and the second semiconducting region, the protection layer having a doping level suitable for optimizing the voltage strength of the semiconducting structure. 
         [0041]    Thus, the presence of such a layer gives the possibility of obtaining a peripheral protection of the JTE (acronym for Junction Termination Extension) type of a junction between the first and second semiconducting region. 
         [0042]    Advantageously, the substrate, the first and the second semiconducting regions are made in a material selected from the group including silicon carbide, gallium nitride and diamond, and preferably silicon carbide. 
         [0043]    Thus, such a semiconducting structure may be integrated in a monolithic way. 
         [0044]    Further, as the semiconducting structure has to support operating voltages notably above 1,000 V, the materials of the group have to have a wide forbidden band, i.e. a forbidden band width of more than 1.7 eV. 
         [0045]    The present invention also relates to an electronic power switch including a plurality of semiconducting structures according to the invention. 
         [0046]    In an embodiment, the plurality of semiconducting structures is laid out so as to delimit at least one first substantially regular hexagonal pattern and/or at least one second pattern with interdigitated bands. 
         [0047]    Advantageously, the electronic power switch includes a cell for protecting the first gate electrode substantially laid out at the center of each first pattern and/or laid out between two interdigitated bands of each second pattern. 
         [0048]    Thus, with such an arrangement of the protection cells, it is possible to uniformize the protection of the first gate for a large size component forming an electronic power switch. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0049]    Other features and advantages will become apparent in the description which follows of three embodiments of a semiconducting structure for an electronic power switch according to the invention, given as non-limiting examples, with reference to the appended drawings wherein: 
           [0050]      FIG. 1  is a schematic cross-sectional view of a semiconducting structure according to a first embodiment, 
           [0051]      FIG. 2  is a schematic cross-sectional view of a semiconducting structure according to a second embodiment, 
           [0052]      FIG. 3  is a schematic cross-sectional view of a semiconducting structure according to a third embodiment, 
           [0053]      FIG. 4  is a graph illustrating I DS , in surface density, versus V DS  for a semiconducting structure according to the invention (curve C) and for a semiconducting structure of the state of the art (curve D), 
           [0054]      FIG. 5  is a graph representing I GS , in surface density, versus V DS  for a semiconducting structure according to the invention (curve A) and for a semiconducting structure of the state of the art (curve B), 
           [0055]      FIG. 6  is a schematic partial top view of an electronic power switch according to a first embodiment, 
           [0056]      FIG. 7  is a schematic partial top view of an electronic power switch according to a second embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0057]    For the different embodiments, the same references will be used for identical elements or ensuring the same functions, for the sake of simplification of the description. 
         [0058]    The semiconducting structure illustrated in  FIG. 1  includes: 
         [0059]    a substrate  1  of conductivity of the n type (i.e. electron conductor), having a lower face  10  and an upper face  11 , 
         [0060]    a drain electrode Din contact with the lower face  10  of the substrate  1 , 
         [0061]    a first semiconducting region  2 , with conductivity of type n, having a lower surface  20  laid out on the upper face  11  of the substrate  1 , and an upper surface  21  provided with a contact area  210 , 
         [0062]    a source electrode S in contact with the contact area  210  of the first semiconducting region  2 , 
         [0063]    a second semiconducting region  3  of conductivity of type p (i.e. whole conductor), laid out inside the first semiconducting region  2 , under the contact area  210 , so as to delimit a first lateral conduction channel C 1  and a second vertical conduction channel C 2  between the drain electrode D and the source electrode S. The first and second conduction channels C 1 , C 2  are of conductivity of type n, 
         [0064]    a first metal gate electrode G 1  having first portions  70  in contact with the second semiconducting region  3  and a second portion  71  in contact with the first semiconducting region  2  so as to form a first junction of the Schottky type. 
         [0065]    a second metal gate electrode G 2  having a first portion  40  in contact with the upper surface  21  of the first semiconducting region  2  so as to form a second junction of the Schottky type, the second gate electrode G 2  being laid out at a distance from the contact area  210 . 
         [0066]    The substrate  1 , for example of the wafer type, has a doping level of type n suitable for formic an ohmic contact with the drain electrode D. In this respect the substrate  1  has a resistivity preferably comprised between 0.015 and 0.03 ohm.cm. 
         [0067]    The first semiconducting region  2  has a first semiconducting area  22  of conductivity of type n laid out above the second semiconducting region  3 . The first semiconducting area  22  defines the height W 1  of the first conduction channel C 1 . The height W 1  of the first conduction channel C 1  is of the order of 3 μm. 
         [0068]    The first semiconducting region  2  has a second semiconducting area  23  of conductivity of type n laid out laterally to the second semiconducting region  3 . The second semiconducting area  23  defines the width W 2  of the second conducting channel C 2 . The width W 2  of the second conduction channel C 2  is of the order of 3 μm. 
         [0069]    The first semiconducting region  2  has a third semiconducting area  24  with a conductivity of type n laid out below the second semiconducting region  3 . The thickness W 3  of the third semiconducting area  24  is of the order of 40 μm. The third semiconducting area  24  has a doping level of type n of the order of 10 15  at.cm −3  much lower than the doping level of type n of the first and the second semiconducting area  22 ,  23 . Indeed, the doping level of type n of the first and of the second semiconducting area  22 ,  23  is of the order of 10 16  at.cm −3 . 
         [0070]    The contact area  210 , with a conductivity of type n, is made at the upper surface  21  of the first semiconducting region  2 . The contact area  210  has a doping level of type n suitable for forming an ohmic contact with the source electrode S. For this purpose, the contact area  210  has a doping level of type n of the order of 10 19  at.cm −3  much greater than the doping level of type n of the first and of the second semiconducting area  23 ,  24 . The thickness W 4  of the contact area  210  is of the order of 0.2 μm. 
         [0071]    The second semiconducting region  3  has a doping level of type p suitable for forming an ohmic contact with the first gate electrode G 1 . For this purpose, the second semiconducting region  3  has a doping level of type p of the order of 10 19  at.cm −3  The thickness W 5  of the second semiconducting region  3  is of the order of 0.5 μm. 
         [0072]    The semiconducting structure further includes a dielectric layer  5 , which may be made in silica, laid out on the upper face  21  of the first semiconducting region  2 . The thickness of the dielectric layer  5  is of the order of 40 nm. 
         [0073]    The second gate electrode G 2  has a second portion  41  surmounting the dielectric layer  5 . The second portion  41  of the second gate electrode G 2  has a width L 2  of the order of 5 μm. The first portion  40  of the second gate electrode G 2  has a width L 1  of the order of 5 μm. 
         [0074]    The second portion  71  of the first gate electrode G 1  in contact with the first semiconducting region  2  forms a first junction of the Schottky type, i.e. a metal/type n semiconductor junction. 
         [0075]    The first portion  40  of the second gate electrode G 2  in contact with the upper surface  21  of the first semiconducting region  2  forms a second junction of the Schottky type, i.e. a metal/type n semiconductor junction. 
         [0076]    The first gate electrode G 1 , the source electrode S and the first junction of the Schottky type form a first diode of the Schottky type providing a unipolar current of majority carriers (electrons). 
         [0077]    Also, the second gate electrode G 2 , the source electrode S and the second junction of the Schottky type form a second diode of the Schottky type providing a unipolar current of majority carriers (electrons). 
         [0078]    As illustrated in  FIGS. 4 and 5 , when the bias voltage between the drain electrode D and the source electrode S, noted as V DS , is negative, each aforementioned diode of the Schottky type gives the possibility, relatively to a diode of the p-n type of the state of the art, of: 
         [0079]    reducing the current in absolute value flowing between the corresponding gate electrode and the source electrode S, noted as I GS , (see curve A relatively to curve B of  FIG. 5 ) in order to protect at best the corresponding gate electrode and the semiconducting structure, and 
         [0080]    increasing the current, in absolute value, flowing between the drain electrode D and the source electrode S, noted as I DS , (see curve C relatively to curve D of  FIG. 4 ) in order to improve the performances of the semiconducting structure in terms of electric conduction. 
         [0081]    Additionally, the first diode of the Schottky type allows an increase in the starting voltage of the second gate electrode G 2 , in absolute value, i.e. the voltage for causing conduction of the second gate electrode G 2  (see the curve A relatively to curve B of  FIG. 5 ). In  FIG. 5 , as an example, the starting voltage has passed from −2.8V to −3.6V. 
         [0082]    The substrate  1 , the first and the second semiconducting region  2 ,  3  are made in silicon carbide. The substrate  1 , the first and the second semiconducting region  2 ,  3  may also be made in gallium nitride or in diamond. 
         [0083]    A method for manufacturing such a semiconducting structure includes the steps of: 
         [0084]    a) providing the substrate  1 , 
         [0085]    b) causing growth of the third semiconducting area  24  of the first semiconducting region  2  on the upper face  11  of the substrate  1 , preferably by epitaxy, 
         [0086]    c) causing growth of the second semiconducting area  23  of the first semiconducting region  2  on the third semiconducting area  24 , preferably by epitaxy, 
         [0087]    d) implanting, preferably by ion implantation, the second semiconducting region  3  inside the second semiconducting area  23 , 
         [0088]    e) causing growth of the first semiconducting area  22  of the first semiconducting region  2  on the second semiconducting area  23 , preferably be epitaxy, 
         [0089]    f) implanting, preferably by ion implantation, the contact area  210  inside the first semiconducting area  22 , 
         [0090]    g) etching the upper portion of the first semiconducting area  22  until the second semiconducting region  3  is attained, 
         [0091]    h) depositing the dielectric layer  5  on the first semiconducting area  22 , 
         [0092]    i) depositing a metallization layer on the lower face  10  of the substrate  1  so as to form the drain electrode D, 
         [0093]    j) depositing a metallization layer on the second semiconducting region  3  so as to form the first gate electrode G 1 , 
         [0094]    k) depositing a metallization layer on the contact area  210  so as to form the source electrode S, 
         [0095]    l) depositing a metallization layer on the first semiconducting area  22  and on the dielectric layer  5  so as to respectively form the first and the second portion  40 ,  41  of the second gate electrode G 2 . 
         [0096]    According to an embodiment illustrated in  FIG. 2 , the semiconducting structure differs from the semiconducting structure illustrated in  FIG. 1  in that the second semiconducting region  3  includes a plurality of boxes  30 , of conductivity of type p, laid out under the second portion  71  of the first gate electrode G 1  so as to delimit a first junction of the Schottky type on either side of each box  30 . Thus, such a plurality of boxes  30  delimits a plurality of first junctions of the Schottky type. The boxes  30  and the first junctions of the Schottky type are interdigitated so as to form with the first gate electrode G 1  and the source electrode S, a diode of the JBS type. Such a JBS diode allows reduction of I GS  and increase of I DS  relatively to a diode of the p-n type of the state of the art. Further, the spacing between the boxes  30  determines the starting voltage of the second gate electrode G 2 . 
         [0097]    Each box  30  has a doping level of type p suitable for forming an ohmic contact with the first gate electrode G 1 . For this purpose, each box  30  has a doping level of type p preferably comprised between 10 19  at.cm −3  and 4*10 19  at.cm −3 . 
         [0098]    According to an embodiment illustrated in  FIG. 3 , the semiconducting structure differs from the semiconducting structure illustrated in  FIG. 1  in that it includes a protection layer  6  of conductivity of type p. 
         [0099]    The protection layer  6  is laid out at the periphery of the junction of the p-n type between the third semiconducting area  24  of the first semiconducting region  2  and the second semiconducting region  3 . The length L 3  of the protection layer  6  is of the order of 120 μm. The protection layer  6  has a doping level of type p suitable for optimizing the voltage strength of the semiconducting structure. To do this, the dose of dopants of type p is of the order of 10 13  at.cm −2 . 
         [0100]    The electronic power switch schematized in  FIG. 6  includes: 
         [0101]    a plurality of semiconducting structures SC according to the invention laid out so as to delimit first substantially regular hexagonal patterns M of the honeycomb type, 
         [0102]    a protection cell P of the first gate electrode G 1  (not shown) substantially laid out at the center of each first pattern M. 
         [0103]    The electronic power switch schematized in  FIG. 7  differs from the electronic power switch schematized in  FIG. 6 , in that: 
         [0104]    the plurality of semiconducting structures SC is laid out so as to delimit second patterns in interdigitated bands BI, 
         [0105]    a protection cell P is laid out between two interdigitated bands BI of each second pattern. 
         [0106]    Of course, the embodiments of the invention described above do not have any limiting nature. Details and improvements may be brought thereto in other alternative embodiments without however departing from the scope of the invention.