Abstract:
Devices including stacking faults in sources, or sources and drains, of TFETs are disclosed to improve tunneling efficiency. Embodiments may include a tunneling field-effect transistor comprising a substrate; a source and a drain within the substrate; a gate between the source and the drain; and a stacking fault within the source.

Description:
RELATED APPLICATIONS 
       [0001]    The present application is a Divisional Application claiming priority to application Ser. No. 13/931,211, filed on Jun. 28, 2013, which is incorporated herein by reference in its entirety. 
     
    
     TECHNICAL FIELD 
       [0002]    The present disclosure relates to tunneling field-effect transistors (TFETs). The present disclosure is particularly applicable to forming TFETs for the 20 nanometer (nm) technology node and beyond. 
       BACKGROUND 
       [0003]    To avoid the 60 millivolt (mV) per decade sub-threshold slope limit, carriers within a field-effect transistor (FET) must not go over the P/N junction barrier. Band-to-band (BTB) tunneling that occurs in TFETs is not subjected to this limit because the carriers do not flow over a potential barrier. Rather, the carriers tunnel through the barrier. However, TFETs suffer from low drive current as a result of poor tunneling efficiency. 
         [0004]    A need therefore exists for a method of providing improved tunneling efficiency in TFETs, and the resulting device. 
       SUMMARY 
       [0005]    An aspect of the present disclosure is a method of forming stacking faults in sources, or sources and drains, of TFETs to improve tunneling efficiency. 
         [0006]    Another aspect of the present disclosure is TFETs with increased tunneling efficiency based on stacking faults in sources, or sources and drains. 
         [0007]    Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims. 
         [0008]    According to the present disclosure, some technical effects may be achieved in part by a method including designating areas within a substrate that will subsequently correspond to a source region and a drain region, selectively forming a stacking fault within the substrate corresponding to the source region, and forming a tunneling field-effect transistor incorporating the source region and the drain region. 
         [0009]    An aspect of the present disclosure includes forming another stacking fault within the substrate corresponding to the drain region. Another aspect of the disclosure includes creating tensile stress within the substrate to form the stacking fault. Yet an additional aspect of the disclosure includes selectively forming an amorphization implant mask above the substrate exposing the source region to form the stacking fault. A further aspect includes, where the substrate is formed of silicon, forming a transition between an amorphous state and a crystalline state of the silicon to form the stacking fault. Additional aspects include doping the source region and the drain region to form a source and a drain, respectively, of the TFET, and forming an inversely doped pocket in the source. Another aspect includes forming the inversely doped pocket above the stacking fault and underneath a gate of the TFET. Yet another aspect includes forming the stacking fault across substantially an entire thickness of the source region. 
         [0010]    Another aspect of the present disclosure is a device including: TFET including: a substrate, a source and a drain within the substrate, a gate between the source and the drain, and a stacking fault within the source. 
         [0011]    An aspect includes the TFET including a stacking fault within the drain. Another aspect includes the stacking fault within the source being tensile stress within the substrate. Another aspect includes the stacking fault being is formed using an amorphization implant mask to selectively expose the source. Additional aspects include the substrate being formed of silicon, and the stacking fault formed as a transition between an amorphous state and a crystalline state of the silicon. Yet another aspect includes an inversely doped pocket in the source. Still another aspect includes the inversely doped pocket being formed above the stacking fault and underneath the gate. An additional aspect includes the stacking fault extending across substantially an entire thickness of the source. 
         [0012]    According to the present disclosure, additional technical effects may be achieved in part by a method including: forming a stacking fault in a region of a silicon substrate, doping the region of the silicon substrate, forming a source, doping another region of the silicon substrate, forming a drain, and forming a TFET incorporating the source and the drain. 
         [0013]    Further aspects of the present disclosure include selectively forming the stacking fault in the region by forming an amorphization implant mask above the region of the silicon substrate. Yet another aspect of the present disclosure includes forming a transition between an amorphous state and a crystalline state of the silicon substrate to form the stacking fault. Still another aspect of the present disclosure includes forming an inversely doped pocket in the source above the stacking fault and underneath the gate of the tunneling field-effect transistor. 
         [0014]    Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which: 
           [0016]      FIGS. 1 through 2B  illustrate a method for forming TFETs with stacking faults in the source, or source and drain, regions, in accordance with an exemplary embodiment; and 
           [0017]      FIGS. 3A through 3G  illustrate a specific method for forming stacking faults in the source, or source and drain, regions in TFETs, in accordance with an exemplary embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0018]    In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.” 
         [0019]    The present disclosure addresses and solves the current problem of low drive current attendant upon TFETs. In accordance with embodiments of the present disclosure, stacking faults are formed in the source, or the source and drain, regions of the TFETs to effectively narrow the silicon (Si) band gap to enhance BTB tunneling efficiency. 
         [0020]    Methodology in accordance with an embodiment of the present disclosure includes designating an area within a substrate that will subsequently correspond to a source region, or areas within a substrate that will subsequently correspond to a source region and a drain region. Stacking faults are then selectively formed in the source region, or the source and drain regions, causing tensile stress within the substrate. The stacking fault may be a transition between an amorphous state and a crystalline state of the substrate, such as Si, that narrows the Si band gap and reduces the drive current. 
         [0021]    Adverting to  FIG. 1 , a method for forming stacking faults in sources, or sources and drains, of TFETs to improve tunneling efficiency, according to an exemplary embodiment, begins with an n-type TFET (NTFET)  100   a  and a p-type TFET (PTFET)  100   b.  Although illustrated as being discontinuous, the NTFET  100   a  and the PTFET  100   b  may be formed within a single, continuous substrate. The NTFET  100   a  is formed of a semiconductor substrate  101   a , which may include any semiconductor material such as Si, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon-on-insulator (SOI), or SiGe-on-insulator (SGOI). The substrate  101   a  may include a lightly n-doped region  103   a,  a source region  105   a,  and a drain region  107   a.  The source region  105   a  may be p-doped and the drain region  107   a  may be n-doped. However, the source region  105   a  and the drain region  107   a  may merely be regions designated within the substrate  101   a  that are later doped to form sources and drains, such that the regions are not necessarily already doped. 
         [0022]    Further, the NTFET  100   a  includes a gate stack formed of an oxide layer  109   a  and a gate layer  111   a  above the substrate  101   a.  The gate oxide layer  109   a  may be formed of any gate oxide material, such as silicon dioxide (SiO 2 ), and the gate layer  111   a  may be formed of any type of gate material. Although not shown (for illustrative convenience), the gate stack may instead be formed of a dummy gate, such as of polysilicon (poly-Si), for subsequent removal and formation of a replacement metal gate. Below the gate stack and between the source region  105   a  and the drain region  107   a  is a channel  113   a.    
         [0023]    The PTFET  100   b  is formed of a semiconductor substrate  101   b,  which may include any semiconductor material such as Si, Ge, SiGe, SiC, SOI, or SGOI. The substrate  101   b  may include a lightly n-doped region  103   b,  a p-well region  103   c,  a source region  105   b  and a drain region  107   b.  The source region  105   b  may be n-doped and the drain region  107   b  may be p-doped. However, the source region  105   b  and the drain region  107   b  may merely be regions within the substrate  101   a  that are later doped such that, as illustrated in  FIG. 1 , the regions are not necessarily pre-doped. 
         [0024]    Further, the PTFET  100   b  includes a gate stack formed of an oxide layer  109   b  and a gate layer  111   b  above the substrate  101   b.  The gate oxide layer  109   b  may be formed of any gate oxide material, such as SiO 2 , and the gate layer  111   b  may be formed of any type of gate material. Although not shown (for illustrative convenience), the gate stack may instead be formed of a dummy gate, such as of poly-Si, for subsequent removal and formation of a replacement metal gate. Below the gate stack and between the source region  105   b  and the drain region  107   b  is a channel  113   b.    
         [0025]    Although not required, the source regions  105   a  and  105   b  may have pocket regions  115   a  and  115   b,  respectively, to further improve a surface tunneling junction between the source regions  105   a  and  105   b  and the channels  113   a  and  113   b,  respectively. The pocket regions  115   a  and  115   b  may be above subsequently formed stacking faults  201  and below the gate stacks. Within the source region  105   a  the pocket region  115   a  is n-doped, and within the source region  105   b  the pocket region  115   b  is p-doped. The pocket regions  115   a  and  115   b  improve the junction between the source regions  105   a  and  105   b  and the channels  113   a  and  113   b , respectively, for the NTFET  100   a  and PTFET  100   b.    
         [0026]    Adverting to  FIG. 2A , the NTFET  100   a  and the PTFET  100   b  are subsequently processed to form stacking faults  201   a  and  201   b  in the source regions  105   a  and  105   b,  respectively. Alternatively, as illustrated in  FIG. 2B , the NTFET  100   a  and the PTFET  100   b  are subsequently processed to also form stacking faults  203   a  and  203   b  in the drain regions  107   a  and  107   b , respectively, in addition to the source regions  105   a  and  105   b.  The stacking faults  201   a  and  201   b  (as well as stacking faults  203   a  and  203   b,  if present) can be transitions between an amorphous state and a crystalline state of a silicon substrate. The stacking faults  201   a  and  201   b  improve tunneling efficiency by effectively narrowing down the Si band gap as a result of the tensile stress within the Si caused by the stacking faults  201   a  and  201   b  near the junction between the source regions  105   a  and  105   b  and the channels  113   a  and  113   b,  respectively. The narrowing of the Si band gap induces high BTB tunneling or gate-induced drain leakage (GIDL), causing higher orders of junction leakage. Specifically, at the p-doped source region  105   a  in the NTFET  100   a,  the stacking fault  201   a  narrows down the Si band gap at the P+/N tunneling junction between the source region  105   a  and the channel  113   a.  At the n-doped source region  105   b  in the PTFET  100   b,  the stacking fault  201   b  narrows down the Si band gap at the N+/P tunneling junction between the source region  105   b  and the channel  113   b.    
         [0027]    The stacking faults may be formed in the source regions  105   a  and  105   b  and the drain regions  107   a  and  107   b  according to any stress memorization technique that forms stress, such as tensile stress, in the substrate  101   a  and  101   b.    FIGS. 3A through 3G  illustrate a specific method for forming the stacking faults according to one stress memorization technique. As illustrated in  FIG. 3A , a pre-amorphization implantation mask  301  is formed over the NTFET  100   a  and PTFET  100   b  illustrated in  FIG. 1 . The pre-amorphization implantation mask  301  may be conformally formed over the NTFET  100   a  and PTFET  100   b.  The pre-amorphization implantation mask  301  is used to selectively form openings  303   a  and  303   b  corresponding to the respective locations where the stacking faults  201   a  and  201   b  are formed in the NTFET  100   a  and the PTFET  100   b.  To form the stacking faults  203   a  and  203   b,  corresponding openings may be made in the pre-amorphization implantation mask  301  (not shown for illustrative convenience). 
         [0028]    Next, an oxide layer  305  is formed over the pre-amorphization implantation mask  301 , as illustrated in  FIG. 3B . The oxide layer  305  may be formed of any oxide, such as SiO 2 , to a thickness of for example 40 Å. The oxide layer  305  may be formed according to various techniques, such as conformally depositing the oxide layer  305  over the pre-amorphization implantation mask  301 . The oxide layer  305  fills the openings  303  in the pre-amorphization implantation mask  301  and comes into contact with the substrates  101   a  and  101   b.    
         [0029]    A silicon nitride (SiN) layer  307  is then formed over the oxide layer  305 , as illustrated in  FIG. 3C . The SiN layer  307  may be formed to a thickness of for example 400 Å, and may be conformally deposited over the oxide layer  305 , such as by plasma enhanced chemical vapor deposition (PECVD). 
         [0030]    After forming the SiN layer  307 , the resulting structures are heated at for example 650° C., for 10 minutes, for example, in an inert atmosphere, such as in the presence of nitrogen gas (N 2 ). The resulting structure and heat treatment causes stacking faults to form in the substrates  101   a  and  101   b  corresponding to the openings  303   a  and  303   b  in the pre-amorphization implantation mask  301  as a result of tensile and compressive stress within the substrates  101   a  and  101   b,  as illustrated in  FIG. 3D . 
         [0031]    Subsequently, the SiN layer  307  is then removed, as illustrated in  FIG. 3E . The SiN layer  307  may be removed by the application of a layer of hot phosphorous. The oxide layer  305  is then removed, as illustrated in  FIG. 3F . The oxide layer  305  may be removed by the application of a layer of dilute hydrofluoric acid (dHF). Subsequently, the pre-amorphization implantation mask  301  is stripped according to any conventional technique, as illustrated in  FIG. 3G . The result is a NTFET  100   a  and a PTFET  100   b  (as illustrated in  FIG. 2A ). Subsequent processing may then proceed in further forming the NTFET  100   a  and the PTFET  100   b,  such as forming raised sources and drains, implanting the source regions  105   a  and  105   b  and the drain regions  107   a  and  107   b  and forming replacement metal gates. Accordingly, the method described above with respect to  FIGS. 3A through 3G  can be implemented in forming any Si complementary metal-oxide-semiconductor (CMOS) in the formation of TFETs. 
         [0032]    The embodiments of the present disclosure achieve several technical effects, including effectively narrowing down the Si band gap to enhance BTB tunneling efficiency while being fully compatible with current Si CMOS technology without adding extra process complexity. As discussed above, the embodiments of the present disclosure can be further optimized with other improvements to TFETs, such as junction design or hetero-structures to even further increase tunneling efficiency. The present disclosure enjoys industrial applicability associated with the designing and manufacturing of any of various types of highly integrated semiconductor devices used in microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure therefore enjoys industrial applicability in any of various types of semiconductor devices, particularly in the 20 nm technology node and beyond. 
         [0033]    In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.