Abstract:
A temperature sensor includes a proportional to absolute temperature (PTAT) current generator configured to generate a first current proportional to temperature, a first complementary to absolute temperature (CTAT) current generator configured to generate a second current inversely proportional to temperature, a second CTAT current generator configured to generate a third current inversely proportional to temperature, and a temperature sensing unit configured to convert the first current, the second current, and the third current into a signal related to the temperature.

Description:
CROSS-REFERENCE TO RELATED PATENT APPLICATION 
   This application claims the benefit of Korean Patent Application No. 10-2005-0073397, filed on Aug. 10, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. 
   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   This disclosure relates to a semiconductor memory device, and more particularly, to an on-chip temperature detector linearly detecting a sensed temperature, a temperature detecting method thereof, and a refresh control method using the same. 
   2. Description of the Related Art 
   In general, a semiconductor device has operating characteristics that depend on temperature. As shown in  FIG. 1 , typical operating characteristics of the semiconductor device include a supply current IDD and an access time tACCESS. The access time increases (A) as temperature increases, and the supply current IDD increases (B) as temperature decreases. 
   Temperature dependent characteristics such as these are important for volatile memory devices such as DRAMs. Leakage currents in DRAMs increases as temperature increases. This deteriorates a data sustain characteristic, reducing a data sustain time tST. Accordingly, as temperature increases the DRAM requires more frequent refresh operations. 
   The development of electronic technologies has enabled the design and cost-effective manufacture of portable electronic devices. Such portable electronic devices include pagers, cellular phones, music players, calculators, lap-top computers, PDAs, and so on. The portable electronic devices generally require DC power, and thus, one or more batteries are used as an energy source to supply the DC power to the portable electronic devices. 
   In a battery-operated system, it is important to reduce the power consumption. To achieve this, circuit components included in the system are turned off during a sleep mode used for power saving. However, a DRAM included in the system should continuously refresh data stored in DRAM cells in order to preserve the data. 
   One of the attempts to reduce power consumed in the DRAM is to vary a refresh period with temperature. In  FIG. 1 , when the refresh period is increased to reduce a refresh clock frequency in a low temperature region where consumption current is increased power consumption is decreased. Accordingly, a temperature detector for detecting the internal temperature of the DRAM is required. 
     FIG. 2  is a circuit diagram of a conventional temperature detector  200 . Referring to  FIG. 2 , the temperature detector  200  includes a proportional to absolute temperature current generator (referred to as “PTAT current generator” hereinafter)  210 , a complementary to absolute temperature current generator (referred to as “CTAT current generator” hereinafter)  220 , and a comparator  230 . 
   The PTAT current generator  210  includes first and second PMOS transistors MP 1  and MP 2 , first and second NMOS transistors MN 1  and MN 2 , a resistor R, and first and second diodes D 1  and D 2 . The first and second PMOS transistors MP 1  and MP 2  have the same size and form a first current mirror. The first and second NMOS transistors MN 1  and MN 2  have the same size and form a second current mirror. The sizes of the first and second diodes D 1  and D 2  have the ratio of 1:M. 
   Since the input and the output of the first current mirror formed by the first and second PMOS transistors MP 1  and MP 2  and the output and the input of the second current mirror formed by the first and second NMOS transistors MN 1  and MN 2  are respectively connected to each other, a current Ia 1  and a current Ia 2  are identical to each other. The ratio of Ia 1  to Ia 2  is 1:1. 
   In general, a turn-on current ID of a diode is as follows.
 
 ID=Is *( e   VD/VT −1)≈ Is *( e   VD/VT )  [Equation 1]
 
   Is represents reverse saturation current of the diode, VD is a diode voltage, and VT is a temperature voltage represented by kT/q. Where T is the temperature, k is a constant and q is the change of an electron. Accordingly, the current Ia 1  flowing through the first diode D 1  is as follows:
 
 Ia 1 =Is *( e   VD1/VT )  [Equation 2]
 
The first diode voltage VD 1  is as follows:
 
 VD 1= VT* ln( Ia 1 /Is )  [Equation 3]
 
The second diode voltage VD 2  is as follows:
 
 VD 2= VT* ln( Ia 2/( Is*M ))  [Equation 4]
 
   Since the current Ia 1  and the current Ia 2  are identical to each other, the first diode voltage VD 1  and current temperature voltage NOC 0  becomes almost identical to each other. Accordingly, the following equation is obtained:
 
 V ( NOC 0)= VD 1= VD 2 +Ia 2* R   [Equation 5]
 
   When VD 1  and VD 2  of Equation 5 are replaced with Equations 3 and 4, respectively, the following equation is obtained:
 
 VT * ln( Ia 1 /Is )= VT* ln( Ia 2/( Is*M ))+ Ia 2 *R   [Equation 6]
 
   Accordingly, the current Ia 1  is as follows.
 
 Ia 2= VT* ln( M )/ R   [Equation 7]
 
   Thus, the current Ia 1  is proportional to temperature. That is, the PTAT current generator  210  generates the current Ia 1  proportional to the temperature of the PTAT current generator  210 . 
   The CTAT current generator  220  includes a third PMOS transistor MP 3 , a third NMOS transistor MN 3 , a plurality of resistors Raa, RU 1  through RU 5 , and RD 1  through RD 5 , and a plurality of switching transistors TU 1  through TU 5  and TD 1  through TD 5 . 
   The switching transistors TU 1  through TU 5  and TD 1  through TD 5  are selectively turned on/off in response to trip temperature control signals AU 1  through AU 5  and AD 1  through AD 5 . 
   The resistors RU 1  through RU 5  and RD 1  through RD 5  are respectively connected to the switching transistors TU 1  through TU 5  and TD 1  through TD 5  Accordingly, any switching transistors TU 1  through TU 5  and TD 1  through TD 5  that are turned on short circuit the respective resistors PU 1  through RU 5  and RD 1  through RD 5 . 
   If the current Ia 1  and current Ia 2  are almost identical to one another, a VA node voltage and VB node voltage of the PTAT current generator  210 , and a VC node voltage of the CTAT current generator  220  become almost identical to one another. In Equations 3 and 4, the voltage VT is increased as temperature is increased. However, the current Is is also increased. As a result, the diode voltage is reduced as temperature is increased and hence the node voltages VA and VC are decreased. Accordingly, the current Ib flowing through the resistors Raa, RU 1  through RU 5  and RD 1  through RD 5  is decreased as temperature is increased. Thus, the CTAT current generator  220  generates a current that varies inversely proportional to temperature. 
   The comparator  230  compares the current temperature voltage NOC 0  to a sensed temperature voltage NOC 1 . The current temperature voltage NOC 0  and sensed temperature voltage NOC 1  are determined by the current Ia 1  and current Ib 1 , respectively. When the point at which the current Ia 1  becomes identical to the current Ib 1  is found, as shown in  FIG. 3 , based on the current temperature voltage NOC 0  and sensed temperature voltage NOC 1 , the temperature detector  200  detects the current temperature. 
   Referring to  FIG. 3 , consider a target temperature of the temperature detector  200  of 45° C. When the current Ib is smaller than the current Ia 1 , the trip temperature control signals AU 1  through AU 5  and AD 1  through AD 5  of the CTAT current generator  220  are selectively enabled to decrease the resistance value of the CTAT current generator  220  such that the current Ib is increased, as shown by direction (C), to make the current Ia 1  identical to the current Ib. In contrast, when the current Ib is larger than the current Ia 1 , the trip temperature control signals AU 1  through AU 5  and AD 1  through AD 5  of the CTAT current generator  220  are selectively disabled to increase the resistance value of the CTAT current generator  220  such that the current Ib is decreased, as shown by direction (D), to make the current Ia 1  identical to the current Ib. 
   When the current Ia 1  becomes identical to the current Ib at the target temperature, 45° C., the comparator  230  outputs a signal having alternating logic levels of high-low-high-low. Accordingly, the temperature detector  200  detects the current temperature, 45° C. 
   The temperature detector  200  controls the trip temperature control signals AU 1  through AU 5  and AD 1  through AD 5  to adjust the resistance value of the resistor branch of the CTAT current generator  220  to change the sensed temperature, that is, the current Ib. When the resistance value is controlled, a gradient of the sensed temperature is not uniform due to the variation of the resistance value. Accordingly, the gradient of the sensed temperature is non-linear. Furthermore, the temperature detector  200  detects the current temperature of a chip based on a single target temperature, and thus the target temperature is fixed to one value. 
   SUMMARY OF THE INVENTION 
   An embodiment includes a temperature sensor including a proportional to absolute temperature (PTAT) current generator configured to generate a first current proportional to temperature, a first complementary to absolute temperature (CTAT) current generator configured to generate a second current inversely proportional to temperature, a second CTAT current generator configured to generate a third current inversely proportional to temperature, and a temperature sensing unit configured to convert the first current, the second current, and the third current into a signal related to the temperature. 
   Another embodiment includes a temperature detection method for a semiconductor device including generating a first current proportional to temperature, generating a second current inversely proportional to temperature, generating a third current inversely proportional to temperature, and converting the first current, the second current, and the third current into a signal related to the temperature. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other features and advantages of the invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: 
       FIG. 1  is a graph showing temperature characteristic of a semiconductor device; 
       FIG. 2  is a circuit diagram of a conventional temperature detector; 
       FIG. 3  is a graph for explaining characteristic of the temperature detector of  FIG. 2 ; 
       FIG. 4  is a block diagram of a temperature detector according to an embodiment; 
       FIG. 5  is a block diagram of a temperature sensor of  FIG. 4 ; 
       FIG. 6  is a circuit diagram of a PTAT current generator and first and second CTAT current generators of  FIG. 5 ; 
       FIG. 7  is a graph showing temperature characteristics of the PTAT current generator and the first and second CTAT current generators shown in  FIG. 6 ; 
       FIG. 8  is a circuit diagram of a current mixer, a first current multiplier, a second current multiplier and a current comparator of  FIG. 5 ; 
       FIG. 9  is a circuit diagram of a diffierential amplifier of  FIG. 5 ; 
       FIG. 10  is a circuit diagram of a latch of  FIG. 5 ; 
       FIG. 11  is a circuit diagram of a power generator of  FIG. 4 ; 
       FIGS. 12 ,  13  and  14  are graphs for explaining the operations of the current mixer, the first current multiplier, the second current multiplier and the current comparator of  FIG. 8  in connection with the graph of  FIG. 7 ; 
       FIGS. 15   a ,  15   b  and  15   c  are flow charts showing the operation of the temperature sensor of  FIG. 5 ; 
       FIG. 16  is a flow chart showing a method of controlling a self refresh period after self refresh is started, using the temperature sensor of  FIG. 5 ; 
       FIG. 17  is a timing diagram for explaining a self refresh control method using the temperature sensor of  FIG. 5 ; and 
       FIG. 18  is a graph showing a result of simulation of a sensed temperature in response to a variation in a tracking code Pcode[0:4] using the temperature sensor of  FIG. 5 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Embodiments will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art, Throughout the drawings, like reference numerals refer to like elements. 
     FIG. 4  is a block diagram of a temperature detector  400  according to an embodiment. Referring to  FIG. 4 , the temperature detector  400  includes a temperature sensor  410 , a power generator  420  dedicated to the temperature sensor  410 , and a tracking code generator  430 . The temperature detector  400  detects the current temperature of a chip using a two-corner test using a high temperature and a low temperature. The high temperature may be set to 100° C., for example, and the low temperature may be set to 0° C., for example. The dedicated power generator  420  provides a power supply voltage V T/S  dedicated to the temperature sensor  410 . The tracking code generator  430  varies a tracking code Pcode[0:n]. The tracking code Pcode[0:n] may change by ±1 in one example. 
   The temperature sensor  410  generates a temperature detection signal Tdet in response to a temperature sensor enable signal EN and the tracking code Pcode[0:n]. The tracking code Pcode[0:n] may have 5 bits where n=4, for example. Such a tracking code Peode[0:n] with 5 bits may be referred to as a tracking code Pcode[0:4]. The tracking code Pcode[0:4] may be initially set to “11111”. If using high and low temperatures of 100° C. and 0° C., respectively, the tracking code “11111” is a reference code used to represent an actual temperature of 100° C. Similarly, “00000” is a reference code used to represent an actual temperature of 0° C. 
   The temperature sensor  410  generates the temperature detection signal Tdet in response to the temperature sensor enable signal EN. The temperature detection signal Tdet corresponds to the result of comparison of the current temperature of the chip including the temperature detector  400  and the temperature sensed by the temperature sensor  410 . The temperature detection signal Tdet at a logic low or high level. 
   Assuming that the current tracking code Pcode[0:n] is “11101”, when the temperature detection signal Tdet is at a logic high level, that is, when the temperature sensed by the temperature sensor  410  is lower than the current temperature of the chip, the tracking code Pcode[0:n] is increased by 1 to be set to “11110” to increase the sensed temperature of the temperature sensor  410 . The temperature sensor  410  generates the temperature detection signal Tdet in response to the tracking code “11110”. This operation is repeated until the temperature detection signal Tdet is output as a logic low signal. At that point, the temperature sensor  410  stores the tracking code Pcode[0:4]. If using a 100° C. temperature range as described above, the sensed temperature of the temperature sensor  410  is increased by 
             100       2   5     -   1       ⁢           ⁢   °   ⁢           ⁢     C   .           
whenever the tracking code Pcode[0:4] is increased by 1.
 
   Alternatively, when the temperature detection signal Tdet of the temperature sensor  410  is at a logic low level, that is, when the sensed temperature of the temperature sensor  410  is higher than the current temperature of the chip, a first temperature code Pcode[0:4] is decreased by 1. For example, if the tracking code Pcode[0:4] stored in the temperature sensor  410  is “10001”, the tracking code Pcode[0:4] will be set to “10000”. The temperature sensor  410  generates the temperature detection signal in response to the new tracking code “10000”. This operation is repeated until the temperature detection signal Tdet is output as a logic high level. At that point, the temperature sensor  410  stores the tracking code Pcode[0:n]. If using a 100° C. temperature range as described above, the sensed temperature of the temperature sensor  410  is decreased by 
             100       2   5     -   1       ⁢           ⁢   °   ⁢           ⁢     C   .           
whenever the tracking code Pcode[0:n] is decreased by 1.
 
     FIG. 5  is a block diagram of the temperature sensor  410  of  FIG. 4 . Referring to  FIG. 5 , the temperature sensor  410  includes a PTAT current generator  510 , first and second CTAT current generators  520  and  530 , a current mixer  540 , a first current multiplier  550 , a second current multiplier  560 , a current comparator  570 , a differential amplifier  580 , and a latch  590 . 
   The PTAT current generator  510  generates a current Ia proportional to temperature. The first CTAT current generator  520  generates a current Ib inversely proportional to temperature. The second CTAT current generator  530  generates a current Ic having a gradient corresponding to the inverse of the gradient of current Ia. The current mixer  540  sums up the current Ia and current Ic to generate a current Id. The first current multiplier  550  multiplies the current Id by α to generate a current Ie in response to a test code Ncode[0:4]. 
   The second current multiplier  560  multiplies the current Ie by β to generate a current If in response to the tracking code Pcode[0:n]. The current comparator  570  compares the current Ia to the current Ib using the current If to generate a first differential input voltage OIFB 1  and a second differential input voltage DIF 1 . The differential amplifier  580  compares and amplifies the first and second differential input voltages DIFB 1  and DIF 1 , to generate a differential output signal T 1 . The latch  590  latches the differential output signal T 1  to generate the temperature detection signal Tdet. 
     FIG. 6  is a circuit diagram of the PTAT current generator  510  and the first and second CTAT current generators  520  and  530  of  FIG. 5 . Referring to  FIG. 6 , the PTAT current generator  510  is identical to the PTAT current generator  210  of  FIG. 2 . The PTAT current generator  510  generates the current Ia proportional to temperature and generates a first node voltage NA at the gate and drain of the first PMOS transistor MP 1  according to the current Ia. Detailed explanation for the PTAT current generator  51   0  is omitted because it is identical to the PTAT current generator  210  of  FIG. 2 . 
   The first CTAT current generator  520  includes a PMOS transistor  621 , an NMOS transistor  622 , a resistor  623 , and a resistor branch  624  serially coupled between a power supply voltage V T/S  and a ground voltage Vss. The PMOS transistor  621  has a gate and a drain, coupled to each other. The resistor branch  624  has a resistance value varied by transistors turned on in response to first control signals TUBA 0  through TUBA 5  and TDBA 0  through TDBA 5 . The first CTAT current generator  520  generates the current Ib inversely proportional to temperature, and generates a second node voltage NB at the gate and drain of the PMOS transistor  621  according to the current Ib. 
   The second CTAT current generator  530  includes a PMOS transistor  631 , an NMOS transistor  632 , a resistor  633  and a resistor branch  634  serially coupled between the power supply voltage V T/S  and the ground voltage Vss. The PMOS transistor  631  has a gate and a drain coupled to each other. The resistor branch  634  has a resistance value varied by transistors turned on in response to second control signals TUBB 0  through TUBB 5  and TDBB 0  through TDBB 5 . The second CTAT current generator  530  controls the resistance value of the resistor branch  634  to generate the current Ic having a gradient versus temperature corresponding to the inverse of the gradient of the current Ia versus temperature. 
     FIG. 7  is a graph showing temperature characteristics of the PTAT current generator  510  and the first and second CTAT current generators  520  and  530  shown in  FIG. 6 . Referring to  FIG. 7 , the current Ia is proportional to temperature and the current Ib is inversely proportional to temperature. 
   The current Ib can be identical to, smaller than or larger than the current Ia when the current temperature is 100° C. When the current Ib is smaller than the current Ia, the first control signals TUBA 0  through TUBA 5  and TDBA 0  through TDBA 5  are selectively enabled to short-circuit corresponding resistors of the resistor branch  624 . Accordingly, the resistance value of the resistor branch  624  is decreased, and thus the current Ib is increased ( 701 ). This operation is repeated to detect the point at which the current Ib becomes identical to the current Ia. 
   When the current Ib is larger than the current Ia, the first control signals TUBA 0  through TUBA 5  and TDBA 0  through TDBA 5  are selectively disabled to increase the resistance value of the resistor branch  624 . Accordingly, the current Ib is decreased ( 702 ). This operation is repeated to detect the point at which the current Ib becomes identical to the current Ia. 
   The state of first control signals TUBA 0  through TUBA 5  and TDBA 0  through TDBA 5  that makes Ib equal to Ia is stored in a first mode register. Alternatively, the resistor branch  624  can be selectively fuse-trimmed to set the state of the first control signals TUBA 0  through TUBA 5  and TDBA 0  through TDBA 5 . 
   The current Ic has the gradient versus temperature corresponding to the inverse of the gradient of the current Ia versus temperature. The current mixer  540  sums up the current Ia and the current Ic to generate the current Id. The current Id has a specific value with respect to temperature. In other words, the current Id is independent of a temperature variation. The temperature sensor  410  detects a sensed signal using the current Id. Preferably, the current Id may be measured from the outside of the chip. 
     FIG. 8  is a circuit diagram of the current mixer  540 , the first current multiplier  550 , the second current multiplier  560  and the current comparator  570  of  FIG. 5 . Referring to  FIG. 8 , the current mixer  540  includes a first PMOS transistor  841  having a source coupled to the power supply voltage V T/S  and a gate coupled to the first node voltage NA, a second PMOS transistor  842  having a source coupled to the power supply voltage V T/S  and a gate coupled to a third node voltage NC, and an NMOS transistor  843  having a gate and a drain, which are coupled to the drains of the first and second PMOS transistors  841  and  842 , and a source coupled to the ground voltage Vss. 
   The first PMOS transistor  841  forms a current mirror with the first PMOS transistor MP 1  of the PTAT current generator  510 . The current Ia flows through the first PMOS transistor  841 . The second PMOS transistor  842  forms a current mirror with the PMOS transistor  631  of the second CTAT current generator  630 . The current Ic flows through the second PMOS transistor  842 . The current Id corresponding to the sum of the current Ia and current Ic flows to the NMOS transistor  843 . The current Id generates a fourth node voltage NN at the gate and drain of the NMOS transistor  843 . 
   The first current multiplier  550  includes a PMOS transistor  851  having a source coupled to the power supply voltage V T/S , a gate and a drain coupled to each other, and a first current controller  852  that is coupled between the drain of the PMOS transistor  851  and the ground voltage Vss and controls the current Ie in response to the test code Ncode[0:4]. 
   The first current controller  852  includes multiple current paths between the drain of the PMOS transistor  851  and the ground voltage Vss. A first current path includes a first NMOS transistor  800  having a gate to receive the fourth node voltage NN. The first NMOS transistor  800  forms a current mirror with the NMOS transistor  843  of the current mixer  540  such that a current Id&#39; corresponds to the current Id multiplied by a predetermined factor. 
   The second current path includes a second NMOS transistor  801  having a gate to receive the fourth node voltage NN and a third NMOS transistor  811  having a gate to receive a code Ncode 0 . The second NMOS transistor  801  forms a current mirror with the NMOS transistor  843  of the current mixer  540  such that a current one times the current Id&#39; flows through the second NMOS transistor  801 . 
   The third current path includes a fourth NMOS transistor  802  having a gate to receive the fourth node voltage NN and a fifth NMOS transistor  812  having a gate to receive a code Ncode 1 . The fourth NMOS transistor  802  forms a current mirror with the NMOS transistor  843  of the current mixer  540  such that a current two times the current Id&#39; flows through the fourth NMOS transistor  802 . 
   The fourth current path includes a sixth NMOS transistor  803  having a gate to receive the fourth node voltage NN and a seventh NMOS transistor  813  having a gate to receive a code Ncode 2 . The sixth NMOS transistor  803  forms a current mirror with the NMOS transistor  843  of the current mixer  540  such that a current four times the current Id&#39; flows through the sixth NMOS transistor  803 . 
   The fifth current path includes an eighth NMOS transistor  804  having a gate to receive the fourth node voltage NN and a ninth NMOS transistor  814  having a gate to receive a code Ncode 3 . The eighth NMOS transistor  804  forms a current mirror with the NMOS transistor  843  of the current mixer  540  such that a current eight time the current Id&#39; flows through the eighth NMOS transistor  804 . 
   The sixth current path includes of a tenth NMOS transistor  805  having a gate to receive the fourth node voltage NN and an eleventh NMOS transistor  815  having a gate to receive a code Ncode 4 . The tenth NMOS transistor  805  forms a current mirror with the NMOS transistor  843  of the current mixer  540  such that a current sixteen times the current Id&#39; flows through the tenth NMOS transistor  805 . 
   The currents flow through the NMOS transistors  801 ,  802 ,  803 ,  804  and  805  if the corresponding NMOS transistors  811 ,  812 ,  813 ,  814  and  815  are turned on by the test code Ncode[0:4]. Accordingly, the current Ie corresponds to the sum of the currents flowing through the NMOS transistors  800 ,  801 ,  802 ,  803 ,  804 , and  805  in response to the test code Ncode[4.0]. The current Ie flows through the PMOS transistor  851 , generating a fifth node voltage NP at the gate and drain of the PMOS transistor  851 . 
   In the first current multiplier  550 , the sum of the widths of the NMOS transistors  801 ,  802 ,  803 ,  804  and  805 , through which current flows changes in response to the test code Ncode[0:4]. As the test code Ncode[0:4] increases, the sum of the width of the NMOS transistors  801 ,  802 ,  803 ,  804 , and  805  on through which current flow increases, and thus the current Ie is increased. Similarly, as the test code Ncode[0:4] decreases, the sum of the widths of the NMOS transistors  801 ,  802 ,  803 ,  804 , and  805  through which current flows decreases, and thus the current Ie is decreased. Although the test code Ncode[0:4] has been described as having 5 bits in this embodiment, the number of bits is not limited to 5 and may be more or less as desired. 
   The second current multiplier  560  includes a second current controller  860  controlling the current If in response to the tracking code Pcode[0:4] and an NMOS transistor  861 , which are coupled between the power supply voltage V T/S  and the ground voltage Vss. 
   The second current controller  860  has multiple current paths similarly to the first current controller  852  of the first current multiplier  550 . A first current path includes a first PMOS transistor  821  having a gate to receive the fifth node voltage NP and a second PMOS transistor  831  having a gate to receive a tracking code Pcode 0 . The first PMOS transistor  821  forms a current mirror with the PMOS transistor  851  of the first current multiplier  550  such that a current one times the current Ie flows through the first PMOS transistor  821 . 
   A second current path includes a third PMOS transistor  822  having a gate to receive the fifth node voltage NP and a fourth PMOS transistor  832  having a gate to receive a tracking code Pcode 1 . The third PMOS transistor  822  forms a current mirror with the PMOS transistor  851  of the first current multiplier  550  such that a current two times the current Ie flows through the third PMOS transistor  822 . 
   A third current path includes a fifth PMOS transistor  823  having a gate to receive the fifth node voltage NP and a sixth PMOS transistor  833  having a gate to receive a tracking code Pcode 2 . The fifth PMOS transistor  823  forms a current mirror with the PMOS transistor  851  of the first current multiplier  550  such that a current four times the current Ie flows through the fifth PMOS transistor  823 . 
   A fourth current path includes a seventh PMOS transistor  824  having a gate to receive the fifth node voltage NP and an eighth PMOS transistor  834  having a gate to receive a tracking code Pcode 3 . The seventh PMOS transistor  824  forms a current mirror with the PMOS transistor  851  of the first current multiplier  550  such that a current eight times the current Ie flows through the seventh PMOS transistor  824 . 
   A fifth current path includes a ninth PMOS transistor  825  having a gate to receive the fifth node voltage NP and a tenth PMOS transistor  835  having a gate to receive a tracking code Pcode 4 . The ninth PMOS transistor  825  forms a current mirror with the PMOS transistor  851  of the first current multiplier  550  such that a current sixteen times the current Ie flows through the ninth PMOS transistor  825 . 
   The currents flow through the PMOS transistors  821 ,  822 ,  823 ,  824 , and  825 , if the corresponding PMOS transistors  831 ,  832 ,  833 ,  834  and  835  are turned on by the test code Pcode[0:4]. Accordingly, the current If corresponds to the sum of the currents flowing through the PMOS transistors  821 , 822 ,  823 ,  824 , and  825 , in response to the test code Pcode[4.0]. The current If flows through the NMOS transistor  861 , generating a fifth node voltage NP at the gate and drain of the NMOS transistor  861 . 
   In the second current multiplier  560 , the sum of the widths of the PMOS transistors  821 ,  822 ,  823 ,  824 , and  825 , through which current flows changes in response to the test code Pcode[0:4] as the test code Pcode[0:4] increases, the sum of the width of the PMOS transistors  821 ,  822 ,  823 ,  824 , and  825 , on through which current flow increases, and thus the current If increases. Similarly, as the test code Pcode[0:4] decreases, the sum of the widths of the PMOS transistors  821 ,  822 ,  823 ,  824 , and  825 , through which current flows decreases, and thus the current If decreases. Although the test code Pcode[0:4] has been described as having 5 bits in this embodiment, the number of bits is not limited to 5. 
   In one example, in the second current multiplier  560 , the tracking code Pcode[0:4] may be set to “11111” when the temperature is 100° C. Thus, the current If does not flow when temperature is 100° C. In contrast if the tracking code Pcode[0:4] is set to “00000” the maximum If current If_max flows at 0° C. 
   The current comparator  570  includes a first comparator  571  to compare the current Ia and current Ib−If to each other and a second comparator  572  to compare the current Ib and current Ia+If to each other. The first comparator  571  includes first and second PMOS transistors  871  and  872  and first, second, and third NMOS transistors  873 ,  874  and  875 . 
   The first PMOS transistor  871  has a source coupled to the power supply voltage V T/S  and a gate coupled to the first node voltage NA. The first PMOS transistor  871  forms a current mirror with the first PMOS transistor MP 1  of the PTAT current generator  510 . The current Ia flows through the first PMOS transistor  871 . 
   The second PMOS transistor  872  has a source coupled to the power supply voltage V T/S  and a gate coupled to the second node voltage NB. The second PMOS transistor  872  forms a current mirror with the PMOS transistor  621  of the first CTAT current generator  520 . The current Ib flows through the second PMOS transistor  872 . 
   The first NMOS transistor  873  has a drain coupled to the drain of the first PMOS transistor  871 , a gate coupled to the gate of the second NMOS transistor  874 , and a source coupled to the ground voltage Vss. The second NMOS transistor  874  has a drain and a gate which are coupled to the drain of the second PMOS transistor  872 , and a source coupled to the ground voltage Vss. The first and second NMOS transistors  873  and  874  form a current mirror such that the current of the first NMOS transistor  873  flows according to the current of the second NMOS transistor  874 . 
   The third NMOS transistor  875  has a drain coupled to the drain of the second NMOS transistor  874 , a gate coupled to the gate of the NMOS transistor  861  of the second current multiplier  560 , and a source coupled to the ground voltage Vss. The third NMOS transistor  875  forms a current mirror with the NMOS transistor  861  of the second current multiplier  560 . The current If flows through the third NMOS transistor  875 . The current obtained by subtracting the current If from the current Ib, that is, Ib−If, flows through the second NMOS transistor  874 . 
   The first comparator  571  compares the current Ia provided through the first PMOS transistor  871  to the current Ib−If flowing through the second NMOS transistor  874  to generate a first comparison signal DIFB 1 . 
   The second comparator  572  includes first and second PMOS transistors  876  and  877 , first and second NMOS transistors  878  and  879 , third and fourth PMOS transistors  880  and  881 , and a third NMOS transistor  882 . The first PMOS transistor  876  has a source coupled to the power supply voltage V T/S  and a gate coupled to the second node voltage NB. The first PMOS transistor  876  forms a current mirror with the PMOS transistor  621  of the first CTAT current generator  520 . The current Ib flows through the first PMOS transistor  876 . 
   The second PMOS transistor  877  has a source coupled to the power supply voltage V T/S  and a gate coupled to the first node voltage NA. The second PMOS transistor  877  forms a current mirror with the PMOS transistor MP 1  of the PTAT current generator  510 . The current Ia flows through the second PMOS transistor  877 . 
   The first NMOS transistor  878  has a drain coupled to the drain of the first PMOS transistor  876 , a gate coupled to the gate of the second NMOS transistor  879 , and a source coupled to the ground voltage Vss. The second NMOS transistor  879  has a drain and a gate, which are coupled to the drain of the second PMOS transistor  877 , and a source coupled to the ground voltage Vss. The first and second NMOS transistors  878  and  879  form a current mirror such that the current of the first NMOS transistor  878  flows according to the current of the second NMOS transistor  879 . 
   The third PMOS transistor  880  has a source coupled to the power supply voltage V T/S , a gate coupled to the gate of the fourth PMOS transistor  881 , and a drain coupled to the drains of the second PMOS transistor  877  and the second NMOS transistor  879 . The fourth PMOS transistor  881  has a source coupled to the power supply voltage V T/S , and a gate and a drain coupled to each other. The third and fourth PMOS transistors  880  and  881  form a current mirror such that the current of the third PMOS transistor  880  flows according to the current of the fourth PMOS transistor  881 . 
   The third NMOS transistor  882  has a drain coupled to the drain of the fourth PMOS transistor  881 , a gate coupled to the gate of the NMOS transistor  861  of the second current multiplier  560 , and a source coupled to the ground voltage Vss. The third NMOS transistor  882  forms a current mirror with the NMOS transistor  861  of the second current multiplier  560 . The current If flows through the third NMOS transistor  882 . 
   The current If flows through the fourth PMOS transistor  881  according to the current If of the third NMOS transistor  882 . The current If flows through the third PMOS transistor  880  according to the current If of the fourth PMOS transistor  881 . The current Ia+If corresponding to the sum of the current Ia of the second PMOS transistor  877  and the current If of the third PMOS transistor  880  flows through the second NMOS transistor  879 . 
   The second comparator  572  compares the current Ib provided through the first PMOS transistor  871  to the current Ia+If flowing through the second NMOS transistor  879  to generate a second comparison signal DIF 1 . 
     FIG. 9  is a circuit diagram of the differential amplifier  580  of  FIG. 5 . Referring to  FIG. 9 , the differential amplifier  580  includes a first PMOS transistor  901  having a source coupled to the power supply voltage V T/S  and a gate receiving a complementary temperature sensor enable signal ENB. The drain of the first PMOS transistor  901  is coupled to the sources of second and third PMOS transistors  902  and  903 . The gate and drain of the second PMOS transistor  902  are coupled to each other. The gates of the second and third PMOS transistors  902  and  903  are coupled to each other. 
   The drains of the second and third PMOS transistors  902  and  903  are respectively coupled to the drains of first and second NMOS transistors  904  and  905 . The gate of the first NMOS transistor  904  is to receive the second comparison signal DIF 1  and the gate of the second NMOS transistor  905  is to receive the First comparison signal DIFB 1 . The sources of the first and second NMOS transistors  904  and  905  are coupled to the drain of a third NMOS transistor  906 . The third NMOS transistor  906  has a gate coupled to the power supply voltage V T/S  and a source coupled to the ground voltage Vss. 
   A fourth PMOS transistor  907  has a source coupled to the power supply voltage V T/S , a gate to receive a temperature sensor enable signal EN, and a drain coupled to the drains of the second PMOS transistor  902  and the first NMOS transistor  904 . A fifth PMOS transistor  908  having a gate to receive the temperature sensor enable signal EN is coupled between the drain of the second PMOS transistor  902  and the drain of the third PMOS transistor  903 . 
   A fourth NMOS transistor  909  is coupled between the second comparison signal DIF 1  and the ground voltage Vss and has a gate to receive the complementary temperature sensor enable signal ENB. A fifth NMOS transistor  910  is coupled between the first comparison signal DIFB 1  and the ground voltage Vss and has a gate to receive the complementary temperature sensor enable signal ENB. 
   The drains of the third PMOS transistor  903  and the second NMOS transistor  905  are coupled to the input of a first inverter  911 . The output of the first inverter  911  passes through second and third inverters  912  and  913  to be output as a first output signal T 1 . 
     FIG. 10  is a circuit diagram of the latch  590  of  FIG. 5 . Referring to  FIG. 10 , the latch  590  includes an inverter  1001 , a first transfer part  1002 , a first latch  1003 , a second transfer part  1004 , and a second latch  1005 . The inverter  1001  receives the temperature sensor enable signal EN and outputs the complementary temperature sensor enable signal ENB. The first transfer part  1002  transfers the differential output signal T 1  of the differential amplifier  580  to the first latch  1003  in response to the temperature sensor enable signal EN at a logic high level and the complementary temperature sensor enable signal ENB at a logic low level. The first latch  1003  latches the differential output signal T 1  transferred through the first transfer part  1002 . The second transfer part  1004  transfers data stored in the first latch  1003  to the second latch  1005  in response to the temperature sensor enable signal EN at a logic low level and the complementary temperature sensor enable signal ENB at a logic high level. The second latch  1005  latches the differential output signal T 1  transferred through the second transfer part  1004  and outputs the temperature detection signal Tdet. 
   The operations of the current comparator  570  of  FIG. 8 , the differential amplifier  580  of  FIG. 9 , and the latch  590  of  FIG. 10  will now be explained. 
   The current comparator  570  generates the first comparison signal DIFB 1  at a logic high level when the current Ib−If is smaller than the current Ia and generates the second comparison signal DIF 1  at a logic low level when the current Ia+If is larger than the current Ib. The differential amplifier  580  compares the first comparison signal DIFB 1  at a logic high level to the second comparison signal DIF 1  at a logic low level to generate the differential output signal T 1  at a logic high level. The latch  590  latches the differential output signal T 1  at a logic high level in response to the temperature enable signal EN and outputs the temperature detection signal Tdet at a logic high level. 
   The current comparator  570  generates the first comparison signal DIFB 1  at a logic low level when the current Ib−If is larger than the current Ia and generates the second comparison signal DIF 1  at a logic high level when the current Ia+If is smaller than the current Ib. The differential amplifier  580  compares the first comparison signal DIFB 1  at a logic low level to the second comparison signal DIF 1  at a logic high level to generate the differential output signal T 1  at a logic low level. The latch  590  latches the differential output signal T 1  at a logic low level in response to the temperature enable signal EN and outputs the temperature detection signal Tdet at a logic low level. 
     FIG. 11  is a circuit diagram of the power generator of  FIG. 4 . Referring to  FIG. 11 , the power generator  410  includes a comparator  1101  to compare a reference voltage V REF  to the power supply voltage V T/S  of the temperature sensor, and a PMOS transistor  1102  generating the temperature sensor power supply voltage V T/S  from a chip power supply voltage VDD in response to the output of the comparator  1101 . Here, the reference voltage V REF  is set such that it is identical to the desired temperature sensor power supply voltage V T/S . 
   When the temperature sensor power supply voltage V T/S  is lower than the reference voltage V REF , the comparator  1101  generates a logic low signal. The PMOS transistor  1102  is turned on in response to the logic low signal output from the comparator  1101 , and thus the temperature sensor power supply voltage V T/S  is increased. When the temperature sensor power supply voltage V T/S  is higher than the reference voltage V REF , the comparator  1101  generates a logic high signal. The PMOS transistor  1102  is turned off in response to the logic high signal output from the comparator  1101 . This operation is repeated such that the power generator  420  generates the power supply voltage V T/S  that is identical to the reference voltage V REF . 
     FIGS. 12 ,  13  and  14  are graphs for explaining the operations of the current mixer  540 , the first current multiplier  550 , the second current multiplier  560  and the current comparator  570  of  FIG. 8  and the operation of the differential amplifier  580  of  FIG. 9  in connection with the temperature characteristic graph of  FIG. 7 . 
   Referring to  FIG. 12 , when the temperature sensor  410  is placed at a temperature of 0° C. and the tracking code Pcode[0:4] is set to “00000”, the maximum If current If_max flows through the second current multiplier  560 . The first comparator  571  of the current comparator  570  compares the current Ia and current Ib−If_max to each other. When the cross point of the current Ia and current Ib−If_max is located lower than 0° C., it means that the temperature sensed by the temperature sensor  410  is lower than the chip&#39;s current temperature 0° C. Here, the temperature detection signal Tdet of the temperature sensor  410  is at a logic high level. 
   The first current multiplier  550  decreases the current Ie by reducing the test code Ncode[0:4] by 1. Accordingly, the current If_max is decreased, and thus the current Ib−If_max is increased ( 1201 ). This operation is repeated until the cross point of the current Ia and the current Ib−If_max corresponds to 0° C., that is, the sensed temperature of the temperature sensor  410  represents the current temperature 0° C. Here, the temperature detection signal Tdet of the temperature sensor  410  changes from a logic high to a logic low level. 
   When the cross point of the current Ia and the current Ib−If_max is located higher than 0° C., it means that the sensed temperature of the temperature sensor  410  is higher than the chip&#39;s current temperature 0° C. Here, the temperature detection signal Tdet of the temperature sensor  410  is at a logic low level. 
   The first current multiplier  550  increases the current Ie by increasing the test code Ncode[0:4] by 1. Accordingly, the current If_max is increased, and thus the current Ib−If_max is decreased ( 1202 ). This operation is repeated until cross point of the current Ia and the current Ib−If_max corresponds to 0° C. to make the sensed temperature of the temperature sensor  410  represents the current temperature 0° C. 
   Referring to  FIG. 13 , the second comparator  572  of the current comparator  570  compares the current Ib and current Ia+If_max to each other. When the cross point of the current Ib and current Ia+If_max is lower than 0° C., it means that the sensed temperature of the temperature sensor  410  is lower than the chip&#39;s current temperature 0° C. Here, the temperature detection signal Tdet of the temperature sensor  410  is at a logic high level. 
   The first current multiplier  550  decreases the current Ie by reducing the test code Ncode[0:4] by 1. Accordingly, the current If_max is decreased, and thus the current Ia+If_max is decreased ( 1301 ). This operation is repeated until the cross point of the current Ib and the current Ia+If_max corresponds to 0° C., that is, the sensed temperature of the temperature sensor  410  represents the current temperature 0° C. Here, the temperature detection signal Tdet of the temperature sensor  410  changes from logic high to a logic low level. 
   When the cross point of the current Ib and the current Ia+If_max is higher than 0° C., it means that the sensed temperature of the temperature sensor  410  is higher than the chip&#39;s current temperature 0° C. Here, the temperature detection signal Tdet of the temperature sensor  410  is at a logic low level. 
   The first current multiplier  550  increases the current Ie by increasing the test code Ncode[0:4] by 1. Accordingly, the current If_max is increased, and thus the current Ia+IF_max is increased ( 1302 ). This operation is repeated until the cross point of the current Ib and the current Ia+If_max corresponds to 0° C. to make the sensed temperature of the temperature sensor  410  become identical to the current temperature 0° C. Here, the temperature detection signal Tdet of the temperature sensor  410  changes from a logic low to a logic high level. 
   When the sensed temperature of the temperature sensor  410  is identical to the current temperature 0° C., the state of the test code Ncode[0:4] obtained in response to the operation of the first comparator  571  is identical to the state of the test code Ncode[0:4] obtained in response to the operation of the second comparator  572 . The state of the test code Ncode[0:4] is selectively stored in a third mode register. The NMOS transistors  811 ,  812 ,  813 ,  814  and  815  of the first current controller  852  may be fuse-trimmed to be enabled according to the state of the test code Ncode[0:4]. 
   Referring to  FIG. 14 , the current mixer  540  measures the current Id when the temperature of the temperature sensor  410  is 100° C. At this temperature, the current mixer  540  measures the current Id for each the states of the second control signals TUBB 0  through TUBB 5  and TDBB 0  through TDBB 5  of the second CTAT current generator  530  ( 1401 ). Similarly, the current mixer  540  measures the current Id for each of the states of the second control signals TUBB 0  through TUBB 5  and TDBB 0  through TDBB 5  when the temperature is 0° C. ( 1402 ). 
   The difference between the current Id at 100° C. and the current Id at 0° C. for each of the states of the second control signals TUBB 0  through TUBB 5  and TDBB 0  through TDBB 5  is obtained. When the absolute value of the difference has the smallest value, the state of the second control signals TUBB 0  through TUBB 5  and TDBB 0  through TDBB 5  is stored in a second mode register. Alternatively, the resistor branch  624  of the second CTAT current generator  530  can be selectively fuse-cut according to the state of the second control signals TUBB 0  through TUBB 5  and TDBB 0  through TDBB 5 . 
     FIGS. 15   a ,  15   b  and  15   c  are flow charts showing the operation of the temperature detector  400 . Referring to  FIG. 15   a , the tracking code Pcode is set to “11111” and the current temperature of the chip including the temperature detector  400  is set to 100° C. in  1501 . 
   The temperature sensor  410  is operated to compare the temperature sensed by the temperature sensor  410  to the current temperature of the chip, 100° C., to generate and store the differential output signal T 1 . After the temperature sensor  410  is disabled, the temperature detection signal Tdet latched in the latch  590  is output in  1502 . 
   It is determined whether the temperature detection signal Tdet is at a logic high level in  1503 . If the temperature detection signal Tdet is at a logic high level, the sensed temperature of the temperature sensor  410  is lower than the current temperature of the chip. To increase the sensed temperature of the temperature sensor  410 , the first CTAT current generator  520  selectively enables the first control signals TUBA 0  through TUBA 5  and TDBA 0  through TDBA 5  to reduce the resistance value of the resistor branch  624 . Accordingly, the current Ib is increased, increasing the temperature crossing of the current Ib and the current Ia, and thus the sensed temperature of the temperature sensor  410  is increased in  1504 . 
   The temperature sensor  410  is operated again to compare the sensed temperature of the temperature sensor  410  to the current temperature of the chip to generate and store the differential output signal T 1 . After the temperature sensor  410  is disabled, the temperature detection signal Tdet latched in the latch  590  is output in  1505 . 
   The current output and the previous output of the temperature detection signal Tdet are compared to each other to judge whether they are opposite to each other in  1506 . When they are identical to each other, it means the sensed temperature of the temperature sensor  410  is lower than the current temperature of the chip. Thus,  1504  and  1505  are repeated. When the current output and the previous output of the temperature detection signal Tdet are opposite to each other, the resistance value of the resistor branch  624  is stored by storing the state of the first control signals TUBA 0  through TUBA 5  and TDBA 0  through TDBA 5  in the first mode register in  1507 . 
   Alternatively, if the temperature detection signal Tdet is at a logic low level in  1503 , the sensed temperature of the temperature sensor  410  is higher than the current temperature of the chip. To decrease the sensed temperature of the temperature sensor  410 , the first CTAT current generator  520  selectively enables the first control signals TUBA 0  through TUBA 5  and TDBA 0  through TDBA 5  to increase the resistance value of the resistor branch  624 . Accordingly, the current Ib is reduced, decreasing the temperature crossing of the current Ib and the current Ia, and thus the sensed temperature of the temperature sensor  410  is decreased in  1508 . 
   The temperature sensor  410  is operated to compare the sensed temperature of the temperature sensor  410  to the current temperature of the chip to generate and store the differential output signal T 1 . After the temperature sensor  410  is disabled, the temperature detection signal Tdet latched in the latch  590  is output in  1509 . 
   The current output and the previous output of the temperature detection signal Tdet are compared to each other to judge whether they are opposite to each other in  1510 . When they are identical to each other, it means the sensed temperature of the temperature sensor  410  is still higher than the current temperature of the chip. Thus,  1504  and  1505  are repeated. When they are opposite to each other, the resistance value of the resistor branch  624  is stored by storing the state of the first control signals TUBA 0  through TUBA 5  and TDBA 0  through TDBA 5  in the first mode register in  1507 . 
   Referring to  FIG. 15   b , the resistor branch  634  is set to a particular value while the current temperature of the chip is maintained at 100° C. in  1511 . The temperature sensor  410  is operated in  1512 , the current Ia+Ic=Id is measured and stored in  1513 , and the temperature sensor  410  is disabled in  1514 . These operations are repeated to store the values of the current Id for varying resistance values according to the second control signals TUBB 0  through TUBB 5  and TDBB 0  through TDBB 5  while the current temperature of the chip is 100° C. 
   The current temperature of the chip is changed to 0° C. in  1515  and  1511 ,  1512 ,  1513  and  1514  are repeated to store the values of the current Id for varying resistance values according to the second control signals TUBB 0  through TUBB 5  and TDBB 0  through TDBB 5 . 
   The resistance value of the resistor branch  624  is stored by storing the state of the first control signals TUBA 0  through TUBA 5  and TDBA 0  through TDBA 5  in the first mode register in the  1516 . 
   A state of the first control signals TUBA 0  through TUBA 5  and TDBA 0  through TDBA 5  is found where the difference between the current Id at 100° C. and the current Id at 0° C. is zero, meaning the currents are identical, or difference is a minimum. The resistance value of the resistor branch  634  in this state is stored by storing the second control signals TUBB 0  through TUBB 5  and TDBB 0  through TDBB 5  in the second mode register in  1516 . In other words, the state of the second control signals TUBB 0  through TUBB 5  and TDBB 0  through TDBB 5  is stored in the second mode register when the absolute value of the current difference has the smallest value. 
   Subsequently, the tracking code Pcode[0:4] is set to “00000” in  1517 . 
   Referring to  FIG. 15   c , the temperature sensor  410  is operated to compare the temperature sensed by the temperature sensor  410  to the current temperature of the chip, 0° C., to generate and store the differential output signal T 1 . Alter the temperature sensor  410  is disabled and the temperature detection signal Tdet is latched in the latch  590  and output in  1518 . 
   If the temperature detection signal Tdet is at a logic high level in  1519 , the sensed temperature of the temperature sensor  410  is lower than the current temperature of the chip. To increase the sensed temperature of the temperature sensor  410 , the first current multiplier  550  reduces the current Ie in response to the test code Ncode[0:4] decreasing by 1 to. That is, the sum of the widths of the NMOS transistors  801 ,  802 ,  803 ,  804  and  805  that are conducting as the test code Ncode[0:4] is decreased is reduced, and thus the current Ie is decreased. When the current Ie decreases, the current If_max reduces, and thus the current Ib−If_max is increased. Accordingly, the sensed temperature of the temperature sensor  410  is increased in  1520 . 
   The temperature sensor  410  is operated again to compare the sensed temperature of the temperature sensor  410  to the current temperature of the chip to generate and store the differential output signal T 1 . After the temperature sensor  410  is disabled, the temperature detection signal Tdet is latched in the latch  590  output in  1521 . 
   The current output and the previous output of the temperature detection signal Tdet are compared to each other to judge whether they are opposite to each other in  1522 . When they are identical to each other, it means the sensed temperature of the temperature sensor  410  is lower than the current temperature of the chip. Thus,  1520  and  1521  are repeated. When the current output and the previous output of the temperature detection signal Tdet are opposite to each other, the sum of the widths of the NMOS transistors  811 ,  812 ,  813 ,  814 , and  815  that are conducting is stored by storing the test code Ncode[0:4] in the third mode register in  1523 . 
   Alternatively, when the temperature detection signal Tdet is at a logic low level in  1519 , the sensed temperature of the temperature sensor  410  is higher than the current temperature of the chip. To decrease the sensed temperature of the temperature sensor  410 , the first current multiplier  550  increases the test code Ncode[0:4] by 1 to reduce the current Ie. That is, the sum of the widths of the NMOS transistors  801 ,  802 ,  803 ,  804 , and  805  turned on is increased as the test code Ncode[0:4] is increased, and thus the current Ie is increased. The current If_max is increased, and thus the current Ib−If_max is decreased. Accordingly, the sensed temperature of the temperature sensor  410  is decreased in  1524 , 
   The temperature sensor  410  is operated again to compare the sensed temperature of the temperature sensor  410  to the current temperature of the chip to generate and store the differential output signal T 1 . After the temperature sensor  410  is disabled, the temperature detection signal Tdet is latched in the latch  590  and output in  1525 . 
   The current output and the previous output of the temperature detection signal Tdet are compared to each other to judge whether they are opposite to each other in  1526 . When they are identical to each other, the sensed temperature of the temperature sensor  410  is still higher than the current temperature of the chip. Thus,  1524  and  1525  are repeated. When they are opposite to each other, the sum of the widths of the NMOS transistors  811 ,  812 ,  813 ,  814 , and  815  that are conducting is stored by storing the test code Ncode[0:4] in the third mode register in  1523 . 
   The states stored in the mode registers described above may be set by fuse trimming appropriate fuses. Fuse trimming of the resistor branch  624  is performed according to the resistance value of the first CTAT current generator  520  stored in the first mode register. Fuse trimming of the resistor branch  634  is performed according to the resistance value of the second CTAT current generated  530  stored in the second mode register. Fuse trimming of the NMOS transistors  811 ,  812 ,  813 ,  814  and  815  is carried out according to the size (sum of widths) of the NMOS transistors  811 ,  812 ,  813 ,  814  and  815  of the first current multiplier  550 , stored in the third mode register in  1527 . 
     FIG. 16  is a flow chart showing a method of controlling a self refresh period after self refresh is started, using the temperature sensor  410  of  FIG. 5 . Referring to  FIG. 16 , the tracking code Pcode[0:4] is set to “11111” in  1601 . The temperature sensor enable signal EN is activated to operate the temperature sensor  410  in  1602 . 
   The temperature sensor  410  compares the temperature sensed by the temperature sensor  410  to the current temperature of the chip to generate and store the differential output signal T 1 . After the temperature sensor  410  is disabled, the latch  590  latches the temperature detection signal Tdet in  1603 . 
   It is determined whether the temperature detection signal Tdet is at a logic high level in  1604 . If the temperature detection signal Tdet is at a logic high level, it means that the sensed temperature of the temperature sensor  410  is lower than the current temperature of the chip. To increase the sensed temperature of the temperature sensor  410 , the tracking code Pcode[0:4] is increased by 1 in  1605 . 
   The sum of the widths of the PMOS transistors  831 ,  832 ,  833 ,  834  and  835  that are conducting in the second current multiplier  560  is decreased as the tracking code Pcode[0:4] is increased, and thus the current If is reduced. Accordingly, the sensed temperature of the temperature sensor  410  is increased by 
   
     
       
         
           
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   Returning to  1602 , the temperature sensor  410  is operated to compare the sensed temperature of the temperature sensor  410 , increased by one step to the current temperature of the chip to generate the temperature detection signal Tdet in  1603 . This operation is repeated until the temperature detection signal Tdet becomes a logic low level. When the temperature detection signal Tdet becomes a logic low level, it means that the sensed temperature of the temperature sensor  410  becomes identical to the current temperature of the chip. The change to a logic low level is detected in  1608 . Accordingly, the self refresh period is determined by the current tracking code Pcode[0:4] in  1607 . 
   Returning to  1604 , when the temperature detection signal Tdet is initially at a logic low level, it means that the sensed temperature of the temperature sensor  410  is higher than the current temperature of the chip. To decrease the sensed temperature of the temperature sensor  410 , the tracking code Pcode[0:4] is decreased by 1 in  1606 . The sum of the widths of the PMOS transistors  831 ,  832 ,  833 ,  834  and  835  that are conducting in the second current multiplier  560  is increased as the tracking code Pcode[0:4] is decreased, and thus the current If is increased. Accordingly, the sensed temperature of the temperature sensor  410  is decreased by 
   
     
       
         
           
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   The temperature sensor  410  is again operated to compare the sensed temperature of the temperature sensor  410  to the current temperature of the chip to generate the temperature detection signal Tdet in  1602 . This operation is repeated until the temperature detection signal Tdet becomes a logic high level. When the temperature detection signal Tdet becomes a logic high level, it means that the sensed temperature of the temperature sensor  410  becomes identical to the current temperature of the chip. The change to a logic high level is detected in  1608 . Accordingly, the self refresh period is determined by the current tracking code Pcode[0:4] in  1607 . 
     FIG. 17  is a timing diagram for explaining a self refresh control method using the temperature sensor  410  of  FIG. 5 . Referring to  FIG. 17 , the temperature sensor  410  is enabled maximum of 2 5  times in order to detect the tracking code Pcode[0:4] where the sensed temperature of the temperature sensor  410  represents the current temperature of the chip according to the routine of  FIG. 16 . A period for changing the tracking code Pcode[0:4] may be as short as tens of microseconds, or less. 
   The tracking code Pcode[0:4] when the sensed temperature of the temperature sensor  410  becomes the current temperature of the chip is detected by linearly varying the sensed temperature of the temperature sensor  410  by 
             100       2   5     -   1       ⁢           ⁢   °   ⁢           ⁢   C   ⁢       .     .           
The self refresh period is set-up according to the detected tracking code Pcode[0:4]. This search operation may require a period of hundreds of milliseconds.
 
   Thereafter, the tracking code Pcode[0:4] is updated by increasing or decreasing it by 1 every several milliseconds. 
     FIG. 18  is a graph showing a result of simulation of the sensed temperature in response to a variation in the tracking code Peode[0:4] using the temperature sensor  410  according to an embodiment. It can be seen from  FIG. 18  that the temperature sensor  410  linearly outputs the sensed temperature in unit of 
             100       2   5     -   1       ⁢           ⁢   °   ⁢           ⁢     C   .           
over a variation in the tracking code Pcode[0:4].
 
   Although storing a state of control signals has been described as storing in a mode register, such control signals may be alternately or additionally stored through fuse trimming appropriate fuses. 
   Although high and low temperatures of 100° C. and 0° C. have been described, one of ordinary skill in the art will understand that the temperature ranges may be selected as desired. Accordingly, the high and low temperatures will change, as will the temperature size of one unit of a sensed temperature. For example, if a high and a low temperature are 125° C. and −55° C., respectively, a unit of the sensed temperature may be 
   
     
       
         
           
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   Although currents may have been described as identical or equal in particular states, one of ordinary skill in the art will understand that such currents may also be substantially equal. For example, when setting two currents to be equal to each other at a particular temperature using discrete control signals, a situation may arise where no state of the control signals will make the two currents exactly identical. However, a state of the control signals may exist where the difference between the two currents is a minimum. Such a state makes the currents substantially equal and may be referred to as making the currents equal. Similarly, any such current or value determined by discrete control signals may be referred to as equal or substantially equal to a target value at a particular state where the controlled value is closest to the target value. 
   While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the following claims.