Abstract:
A field effect transistor having operating characteristics based on the control and modulation of the punch through phenomenon. The channel region between the source and the drain regions is appropriately doped such that the source and drain depletion regions overlap when no potential is applied between source and drain. The overlapped region in the absence of a gate field has a potential barrier. A gate voltage modulates the barrier to below the kT/q parameter. The source-to-drain fields also modulate the barrier.

Description:
This application is a continuation of application Ser. No. 06/656.045 filed Sept. 28, 1984, now abandoned which in turn is a continuation of application Ser. No. 96/463,787 filed Feb. 4, 1983, now abandoned, which in turn is a continuation-in-part of application Ser. No. 06/203,037 filed Nov. 3, 1980 now abandoned. 
    
    
     DESCRIPTION 
     1. Technical Field 
     The field of the invention is in very small dimension active semiconductor devices of the field effect transistor (FET) type wherein conduction occurs in a channel between source and drain electrodes under the influence of a signal applied to a gate positioned over the channel. 
     2. Background Art 
     One type of progress in both increased performance and in increased integrated circuit density in FET devices has been achieved by making the channel shorter. There is, however, a limitation to the ability to do this in that a depletion region is present in the semiconductor crystal adjacent to a heavily doped region such as the source and drain electrodes and when the channel length becomes as short as twice the width of that depletion region, the source and drain depletion regions touch and a condition known as punch through is established causing the device performance to be radically changed. 
     Generally, the depletion region width in moderate doping is in the order of thousands of angstroms, and for the material silicon using the modern electron beam lithography, for example, devices can be built with a channel length less than 1000Å so that punch through is now becoming a serious limiting factor. 
     U.S. Pat. Nos. 4,091,405 and 4,132,998 describe devices where, in order to get reduced channel lengths while avoiding punch through, heavy doping of the channel is employed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1 and 2 are cross-sectional views of a field effect transistor (FET) according to the invention. 
     FIGS. 3, 4 and 5 are dimensionally correlated graphical representations of electron energy distributions in the structure of an FET according to the invention. 
     FIG. 6 is a graphical representation of the current-potential output characteristics of the device of the invention. 
    
    
     DISCLOSURE OF THE INVENTION 
     The invention is a structure and operation of a field effect transistor in a modulated punch through mode so that response is achieved equivalent to shorter channel lengths than punch through will permit in ordinary operation and greater control of performance is achieved as a result of fields in the channel produced by both gate voltage and source to drain voltage. 
     In the device of the invention the depletion regions associated with the source and drain electrodes overlap over a region that is a significant portion of the channel length and a barrier present in the overlap region is changed in response to gate, source and drain potential levels. In the device of the invention, the source to drain current is in the bulk of the channel. 
     The structure of the invention differs from a standard FET by the fact that the depletion regions overlap in the channel to such an extent that there is a region that is a significant portion of the channel length in which a barrier can be modulated. 
     The structure of the invention is built so that the depletion regions associated with the source and drain regions overlap in an unbiased condition. Such a structure would be in a permanent punch through condition. While the position in the channel of an FET of the depletion region associated with the source and drain electrodes can be moved by the potential applied between source and drain, the use of such a potential introduces a threshold potential, results in higher potential levels and contributes to higher power dissipation, an important consideration in high density integrated circuits. The structure of the invention, by having the depletion regions overlap for a significant portion of the channel at no bias, avoids the excessive threshold. 
     The device is a solid state equivalent of a triode electron tube. 
     In accordance with the invention the overlapping depletion regions cover a significant portion of the channel and contain a barrier which can be modulated by a potential on the gate that operates to overcome that barrier in the overlapped depletion region. The gate potential polarity operates to overcome the barrier in the overlapped depletion region portion of the channel and by variation of source and drain voltage, differences are produced in the linear or longitudinal field in the channel which are available for control. 
     For a given gate voltage or potential, there exists a source-drain threshold voltage which can be referred to as V TH   d , above which the source-drain conduction commences according to the space charge limited conditions. This V TH   d  threshold voltage, as shown in FIG. 3, can be modulated by gate voltage as shown in FIG. 4 resulting in the device having I drain  -V drain  performance characteristics as shown in FIG. 6. It is this V TH   d  modulation by gate voltage V G  that makes the device behave as described and makes it useful as an active switching element. 
     The structure of the invention is also preferably equipped with means to prevent parasitic current flow between the source and drain in parallel with the channel so that more positive modulation and the absence of a current between source and drain in the off condition is achieved. 
     BEST MODE FOR CARRYING OUT THE INVENTION 
     In order to provide one skilled in the art with a starting place in practicing the invention, consider the semiconductor material 1 to be silicon, and the polarity chosen for illustration is to be &#34;n&#34; for the source and drain regions and &#34;p&#34; for the channel, however, it will be apparent to one skilled in the art that other semiconductor materials and conductivity types may be employed. 
     For purposes of definition, the conductivity type n or p is the predominance of one type of carrier over another whereas the conductivity which is the reciprocal of the resistivity is a measure of the net doping density in the semiconductor. 
     Referring to FIG. 1 in a p conductivity type semiconductor material body 1, a source electrode region 2 and a drain electrode region 3 that are heavily doped and have high conductivity, shown as n +   are equipped with the external connections 4 and 5. The source 2 and drain 3 are separated by a channel 6. A parasitic current control, buried region 7, such as would be produced by ion p + , region 7, such as would be produced by ion implantation, is provided under the channel 6 and a gate 8 electrode with an external contact 9 is positioned in current flow influencing proximity over the channel 6 separated by an insulator 10. The semiconductor parameters of semiconductor material type, doping concentration and spacing of source to drain are maintained so that the depletion regions associated with the source and drain regions overlap for a significant portion of the channel when there is no potential applied between source and drain. 
     The overlap is shown in FIG. 1 as a dotted line 11 representing the extent of the depletion region associated with the source electrode 2 which is from the surface under the gate 8 to and along the region 7 and then further into the substrate essentially parallel to the source region 2. Similarly, the depletion region associated with the drain region 3 follows the same general path in the opposite direction as shown by the dotted line 12. The result is that a significant portion of the channel contains a barrier that can be modulated by a signal on the gate. The overlap region is labelled 13 in the channel 6. The boundaries 11 and 12 will be modified according to Poisson&#39;s equation and the potential inside the overlapping regions will be modified accordingly. 
     Referring to FIG. 2, an alternate structure is provided where the parasitic current control means is achieved by making the active device region an epitaxial film of, for example, silicon on an opposite conductivity type, high resistivity or insulating substrate 14 such as Al 2  O 3  (sapphire). In the structure of FIG. 2 all other elements are as in FIG. 1 with the same reference numerals. The overlapping depletion region 11 extending from the source 2 and region 12 extending from the drain 3 are essentially along a vertical line from the gate 8 surface to the substrate interface with a slight curvature at the substrate interface. 
     The structures of FIGS. 1 and 2 are constructed so that the overlap region 13 is a significant portion of the channel length and is present at conditions of no bias between source and drain. The overlap region 13 is achieved as set forth in Expression 1 wherein the combined depletion regions associated with the source and drain electrodes is greater than half the channel length. ##EQU1## where φ b  is the diffusion potential between the source 2 or drain 3 electrode and the region 7 or 14. For the material silicon this is about 1 volt. 
     L is the channel length between source 2 and drain 3. 
     N a  is the doping density of the region 7 or 14, and 
     K S  is the dielectric constant of the region 6. 
     Under conditions in the material silicon where the channel length L is 1 micrometer and the value of N a  is &lt;5.3×10 15  per cm 3  then the degree of overlapping will be how much N a  is less than the value of expression 2. ##EQU2## where φ b  is the diffusion potential defined previously. 
     In accordance with the invention where the overlap region is a significant portion of the channel length a barrier to carrier flow in the channel will be present and this barrier is responsive to a potential signal on the gate and a linear field between source and drain. 
     A positive potential applied to the gate 8 operates to reduce the height of the electron barrier in the overlap region 13. For p conductivity type in the channel 6 the gate voltage polarity would be positive (+). A variation in potential across the channel between source and drain changes the shape and distribution of the barrier. The performance of the device of the invention thus is controllable by both gate and source to drain signal levels. 
     Referring to FIGS. 3, 4 and 5, the barrier and the modulation thereof in accordance with the invention is illustrated. The FIGS. 3, 4 and 5 are dimensionally correlated with FIGS. 1 and 2, illustrating the relative potentials in the channel 6 and in the depletion region overlap 13. Each line is an equipotential line. Five are shown in essentially equal incremental distances with depth away from the gate 8. 
     FIG. 3 shows the barrier to electron current flow between source and drain in the overlap region 13. The preferred structure is to arrange the doping so that the overlap region is a significant portion of the order of one-fourth to all of the channel length under the conditions of no potential between source and drain. 
     A potential between source and drain will change the extent of the depletion regions 11 and 12 but due to the fact that the depletion regions are constructed to overlap of the order of one-fourth or greater of the channel at no potential between source and drain, there will be minimal threshold in the output characteristics. 
     The barrier in FIG. 3 increases from a level outside the overlap region 13 to a higher level in the region 13 to a lower level again outside the overlap region and is greater progressively farther from the heavily doped buried region 7 or the insulating substrate 14. The barrier is also affected by the work function of the gate 8 material. Where the gate material 8 is aluminum, a higher work function is present. The barrier height is determined by channel 6 length and doping. 
     In FIG. 4 an illustration is provided of the modulation of the barrier under the gate with constant source and drain signal levels. 
     In FIG. 4 a potential is applied to the gate 8 with respect to source 2 which operates to progressively reduce the barrier toward the gate and to permit current flow. In FIG. 4 for an illustrative value of gate voltage in one equipotential line adjacent the gate the barrier is removed. The barrier can be modulated to below the well known physical limitation ##EQU3## this value for the material silicon is about 26×10 -3  volts at room temperature. 
     It will be apparent to one skilled in the art that with sufficient signal strength on the gate 8 the entire barrier to current flow through the channel 6 can be removed and that the drain threshold voltage, which is the threshold voltage needed to turn on the device, decreases with gate voltage as shown in FIG. 6. 
     The device of the invention is also subject to control by a change in signal level at the source and drain 3. The change produces a different longitudinal or linear field in the channel region 6 and the field changes the barrier in the overlap region 13. 
     Referring to FIG. 5, the effect of the source to drain potential levels in the overlap region 13 of the channel 6 is shown. In this figure, for a given bias, a larger variation in barrier distortion is seen with greater distance from the gate interface. Other potentials between source and drain operate to introduce a threshold into the output characteristics. 
     The device of the invention is thus controllable both by gate voltage and by source to drain voltage. 
     It is seen from these figures that two limiting factors enter into the current flow under the conditions described. Namely, the emission limited current and space charge limited current in the channel 6 and near the gate 8 interface, respectively. The emission limited current is a strong function of the barrier height, φ B , varying ˜ exp (-φ B  kT). As φ B  /kT decreases due to the applied gate or drain potentials, space charge in the channel will limit the current. The space charge limited current i is a strong function of the drain voltage V d  and the channel length L in the case of scattering limited as shown in Expression 3 
     
         Expression 3 i ˜ V.sub.d.sup.2 /L.sup.3  and as shown in Expression 4 
    
     
         Expression 4 i˜V.sub.d.sup.3 /L.sup.2 
    
     in the case of ballistic transport for an extremely short channel where channel length is smaller than the mean free path of an electron in the channel 6. 
     In order to provide a starting place for one skilled in the art to practice the invention, the following example specifications for the structure of FIG. 1 are set forth. 
     
         ______________________________________Semiconductor 1    siliconSource 2 and Drain 3              n.sup.+  doped to 10.sup.20 /ccChannel 6          p doped to 2 × 10.sup.15 /ccRegion 7           p.sup.+  doped to 10.sup.18 /ccSpace Charge Overlap              about 0.82 μm longRegion 13          out of an approx.              1 μm channel.______________________________________ 
    
     The potential barrier in the overlap region 13 is described by Expression 5. ##EQU4## Since the thermal energy ##EQU5## is 0.026 electron volts at room temperature, the barrier φ b  in region 13 is sufficient to prevent substantial thermionic emission from the source 2 over the barrier. 
     A new class of device is realized. The transfer I-V characteristics are shown schematically in FIG. 6. The device of the invention has considerably larger current gain than a conventional inversion layer FET, especially for a small channel length owing to its larger channel depth and higher electron mobility in the bulk. 
     Referring to FIG. 6, the drain current is the ordinate and the drain voltage is the abscissa. A conventional load line is shown with the curves representing performance at progressively larger values of gate voltage with the device being off at value 1. The parasitic current control means, the buried region 7 of FIG. 1 and the insulating substrate of FIG. 2 operate to keep the drain current &#34;off,&#34; otherwise all the V G  curves of FIG. 6 would converge on some finite current representing the parasitic current rather than on the V drain axis. 
     What has been described is a field effect transistor that operates by modulating a punch through condition.