Abstract:
Disclosed is a method of fabricating a high density PCB. Electric properties of a high frequency package product are reduced due to an increased length of a circuit even though the increased length of the circuit is necessary to maintain physical strength in the course of fabricating the PCB. Accordingly, a core insulating layer is removed, thereby providing a method of fabricating a slim PCB having a short wiring length.

Description:
INCORPORATION BY REFERENCE  
       [0001]     The present application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2004-93182 filed on Nov. 15, 2004. The content of the application is incorporated herein by reference in its entirety.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a method of fabricating a high density printed circuit board (PCB). More particularly, the present invention pertains to a method of fabricating a slim PCB having a short wiring length. In the method, a core insulating layer is removed, thereby avoiding reduced electric properties of a high frequency package product due to an increased length of a circuit even though the increased length of the circuit is necessary to maintain physical strength in the course of fabricating the PCB.  
         [0004]     2. Description of the Prior Art  
         [0005]     Recently, it has been believed that reduction of the thickness of a substrate is essential to reduce thicknesses of parts constituting informatization devices, such as mobile phones. Furthermore, in current SiP (system in package) fields, it is known as the most sophisticated technology to reduce a thickness of a chip while not bending a wafer and to employ a small space.  
         [0006]     In accordance with the trend of multi-functionalization and miniaturization of PCBs, demand for highly dense and miniaturized PCBs having a high speed is growing.  
         [0007]      FIGS. 1   a  to  1   m  are sectional views stepwisely illustrating the fabrication of a six-layered PCB in the conventional build-up manner. In the specification of the present invention, the term “build-up manner” means a process which comprises forming internal layers and layering external layers one by one on the internal layers.  
         [0008]      FIG. 1   a  is a sectional view of an unprocessed copper clad laminate (CCL)  101 . Copper foils  102  are applied onto an insulating layer  103 . Generally, the copper clad laminate acts as a substrate of a PCB, and means a thin laminate consisting of the insulating layer onto which copper is thinly applied.  
         [0009]     The copper clad laminate is classified into a glass/epoxy CCL, a heat-resistant resin CCL, a paper/phenol CCL, a high-frequency CCL, a flexible CCL (polyimide film), a complex CCL and the like, in accordance with its use. Of them, the glass/epoxy CCL is most frequently used to fabricate double-sided PCBs and multilayer PCBs.  
         [0010]     The glass/epoxy CCL consists of a reinforcing base substance in which an epoxy resin (combination of a resin and a hardening agent) is penetrated into a glass fiber, and a copper foil. The glass/epoxy CCL is graded FR-1 to FR-5, as prescribed by the National Electrical Manufacturers Association (NEMA), in accordance with the kind of reinforcing base substance and heat resistance. Traditionally, the FR-4 grade of glass/epoxy CCL is most frequently used, but recently, the demand for the FR-5 grade of glass/epoxy CCL, which has improved glass transition temperature (Tg), is growing.  
         [0011]     In  FIG. 1   b,  the copper clad laminate  101  is drilled to form a via hole  104  for interlayer connection.  
         [0012]     In  FIG. 1   c,  electroless copper plating and electrolytic copper plating processes are conducted. In this regard, the electroless copper plating process is conducted before the electrolytic copper plating process. The reason that the electroless copper plating process is conducted before the electrolytic copper plating process is that the electrolytic copper plating process using electricity is not possible on the insulating layer. In other words, the electroless copper plating process is conducted as a pretreatment process to form a thin conductive film needed to conduct the electrolytic copper plating process. Since it is difficult to conduct the electroless copper plating process and to assure economic efficiency, it is preferable that a conductive part of a circuit pattern be formed using the electrolytic copper plating process.  
         [0013]     Subsequently, a paste  106  is packed in the via hole  104  so as to protect electroless and electrolytic copper plating layers  105  formed on a wall of the via hole  104 . The paste is generally made of an insulating ink material, but may be made of a conductive paste according to the intended use of the PCB. The conductive paste includes a mixture of any one metal, which is selected from Cu, Ag, Au, Sn, Pb, or an alloy thereof and acts as a main component, and an organic adhesive. However, the plugging process of the via hole  104  using the paste may be omitted according to the purpose of the PCB.  
         [0014]     In  FIG. 1   c,  for convenience of understanding, the electroless and electrolytic copper plating layers  105  are illustrated as one layer without distinguishing two layers from each other.  
         [0015]     In  FIG. 1   d,  an etching resist pattern  107  is constructed to form a circuit pattern for an internal circuit.  
         [0016]     A circuit pattern, which is printed on an artwork film, must be transcribed on the substrate so as to form the resist pattern. The transcription may be conducted through various methods, but the most frequently used method is to transcribe a circuit pattern, which is printed on an artwork film, onto a photosensitive dry film using ultraviolet rays. Recently, a liquid photo resist (LPR) is sometimes used instead of the dry film.  
         [0017]     The dry film or LPR to which the circuit pattern is transferred acts as the etching resist  107 , and when the substrate is dipped in an etching liquid as shown in  FIG. 1   e , the circuit pattern is formed.  
         [0018]     After the formation of the circuit pattern, the appearance of the circuit pattern is observed using an automatic optical inspection (AOI) device so as to evaluate whether an internal circuit is correctly formed or not, and the resulting substrate is subjected to a surface treatment, such as a black oxide treatment.  
         [0019]     The AOI device is used to automatically inspect the appearance of a PCB. The device automatically inspects the appearance of the PCB employing an image sensor and a pattern recognition technology using a computer. After reading information regarding the pattern of an objective circuit using the image sensor, the AOI device compares the information to reference data to evaluate whether defects have occurred or not.  
         [0020]     The minimum value of an annular ring of a land (a portion of the PCB on which parts are to be mounted) and a ground state of a power source can be inspected by use of the AOI device. Furthermore, the width of the circuit pattern can be measured and the omission of a hole can be detected. However, it is impossible to inspect the internal state of a hole.  
         [0021]     The black oxide treatment is conducted so as to improve adhesion strength and heat resistance before an internal layer having the circuit pattern is attached to an external layer.  
         [0022]     In  FIG. 1   f,  resin-coated copper (RCC) is applied to both sides of the resulting substrate. The RCC consists of a substrate in which a copper foil  109  is formed on only one side of a resin layer  108 , and the resin layer  108  acts as an insulator between the circuit layers.  
         [0023]     In  FIG. 1   g,  a blind via hole  110  is formed to electrically connect the internal and external layers to each other. The blind via hole may be mechanically drilled. However, it is necessary to more precisely conduct the drilling in comparison with processing of a through hole, and thus, it is preferable to use an yttrium aluminum garnet (YAG) laser or a CO 2  laser. The YAG laser can drill both a copper foil and an insulating layer, but the CO 2  laser can drill only the insulating layer.  
         [0024]     In  FIG. 1   h,  an external layer  111  is laminated according to a plating process.  
         [0025]     In  FIG. 1   i,  the external layer  111  formed as shown in  FIG. 1   h  is patterned according to the same procedure as the formation of the circuit pattern of the internal layer. The patterned external layer  111  is then inspected in terms of the circuit and subjected to a surface treatment, as in the case of the circuit pattern of the internal layer.  
         [0026]     In  FIG. 1   j,  additional RCC is applied to both sides of the resulting substrate. This RCC includes a resin layer  112  and a copper foil  113  coated on one side of the resin layer  112 , and the resin layer  112  acts as an insulator.  
         [0027]     In  FIG. 1   k,  a blind via hole  114  is formed to electrically connect the external layers to each other using the laser as described above.  
         [0028]     In  FIG. 1   l , the additional external layer  115  is laminated according to a plating process.  
         [0029]     In  FIG. 1   m , the additional external layer  115  is patterned according to the same procedure as the external layer  111 , and the circuits of the patterned external layer  115  are then inspected and the layer is subjected to a surface treatment.  
         [0030]     The number of layers constituting the multilayer PCB may be continuously increased by repeating the lamination of layers, the construction of the circuit patterns, the inspection of the circuit patterns, and the surface treatment of the resulting structure.  
         [0031]     Subsequently, a photo-solder resist and an Ni/Au layer are formed on the resulting circuit pattern, thereby creating a six-layered PCB.  
         [0032]     The conventional build-up manner cannot meet recent demands because of a limit in reducing a thickness of a substrate. In other words, a conventional CCL including an insulating core, in which a resin is incorporated in a glass fiber, inevitably has some thickness. However, even though the insulating core of the CCL serves to maintain strength during the fabrication process, electric properties are reduced due to an increased length of a circuit.  
         [0033]     With respect to this, U.S. Pat. No. 6,696,764 discloses a method of fabricating two PCBs by cutting a central part of the PCB through a mechanical process after construction of the PCB. However, since the cutting is mechanically conducted, it has a limit to be applied to the fabrication of a precise PCB. Additionally, a core insulating layer remains after the cutting, making the PCB thick. Accordingly, a more fundamental alternative proposal is needed to reduce a thickness of the PCB.  
       SUMMARY OF THE INVENTION  
       [0034]     Therefore, the present invention has been made keeping in mind the above disadvantages of a conventional method of fabricating a PCB, and an object of the present invention is to provide a novel method of fabricating a PCB, in which it is possible to remove an insulating core having an undesired thickness.  
         [0035]     The above object can be accomplished by providing a method of fabricating a high density PCB. The method comprises applying an insulator, which is capable of being patterned by ultraviolet rays, on one side of a copper foil; patterning the insulator using the ultraviolet rays; forming a first circuit pattern on the insulator by electrolytic plating; laminating an insulating layer on the first circuit pattern; and forming via holes and second circuit patterns on the insulating layer and the other side of the copper foil.  
         [0036]     Additionally, the present invention provides a method of fabricating a high density PCB. The method comprises applying an insulator, which is capable of being patterned by ultraviolet rays, on one side of a copper foil; patterning the insulator using the ultraviolet rays; forming a first circuit pattern on the insulator by electrolytic plating; forming a second circuit pattern on the copper foil; laminating insulating layers on both sides of a resulting structure; and forming via holes and third circuit patterns on the insulating layers and the other side of the copper foil.  
         [0037]     Furthermore, the present invention provides a high density PCB, which comprises an insulator which is patterned by ultraviolet rays and has first circuit patterns formed on both sides thereof. A plurality of insulating layers is laminated on the insulator, and a plurality of first via holes is formed through the insulating layers. Circuit layers are interposed between the plurality of insulating layers, and a plurality of second via holes and second circuit patterns are formed in the circuit layers. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0038]     The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:  
         [0039]      FIGS. 1   a  to  1   m  are sectional views stepwisely illustrating the fabrication of a six-layered PCB in the conventional build-up manner;  
         [0040]      FIGS. 2   a  to  2   n  illustrate the fabrication of a PCB according to the first embodiment of the present invention;  
         [0041]      FIGS. 3   a  to  3   m  illustrate the fabrication of a PCB according to the second embodiment of the present invention; and  
         [0042]      FIGS. 4   a  to  4   f  illustrate the fabrication of a PCB according to the third embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0043]     Hereinafter, the present invention will be described in detail with reference to the drawings.  
         [0044]      FIGS. 2   a  to  2   n  illustrate the fabrication of a PCB according to the first embodiment of the present invention.  
         [0045]      FIG. 2   a  illustrates a sectional view of a copper foil  201 . The copper foil  201  is the same as a copper foil which is laminated on a typical CCL, and it is preferable that a thickness of the copper foil  201  be about 9-12 μm.  
         [0046]     In  FIG. 2   b , an insulator  202 , which is capable of being patterned by ultraviolet rays, is applied on one side of the copper foil  201 . Capable of being patterned by ultraviolet rays, the insulator is a polymer which contains an acrylic group and thus has a property in which it is hardened through a polymerization reaction by the irradiation of ultraviolet rays. Preferably, examples of a material having the above property include benzocyclobutene (BCB) as an ultraviolet sensitive polymer or SU-8 as a negative photoresist. Furthermore, it is preferable that the insulator  202  have chemical resistance and heat resistance so as to withstand subsequent chemical and heat treatments.  
         [0047]     In  FIG. 2   c , a glass mask  203 , on which a predetermined pattern is formed, is applied to the insulator  202 , and ultraviolet rays are then irradiated to achieve development of the pattern.  
         [0048]     As shown in  FIG. 2   d , ultraviolet rays are not passed through a portion of the insulator  202 , which corresponds in position to a black portion of the glass mask  203 , and thus does not harden the portion of the insulator. However, the other portion of the insulator  202 , which corresponds in position to a transparent portion of the glass mask  203 , is polymerized by ultraviolet rays and thus hardened.  
         [0049]     After the patterning is conducted, baking may be selectively conducted to assure desired stiffness of the insulator  202 .  
         [0050]     In  FIG. 2   e,  if an unhardened portion of the insulator  202  is selectively removed, the insulator is patterned. The resulting substrate is immersed in a developing liquid to remove the unhardened portion of the insulator  202 .  
         [0051]     In  FIG. 2   f,  a plating layer  204  is formed on the insulator  202  through an electroless plating process or a sputtering process. The plating layer  204  acts as a seed layer for subsequent electrolytic plating.  
         [0052]     In  FIG. 2   g,  a plating resist  205  is applied on both sides of the substrate, and a portion of the plating resist  205 , which is applied on the patterned insulator  202 , is exposed and developed to be patterned. A dry film may be used as the plating resist  205 .  
         [0053]     In  FIG. 2   h,  a circuit pattern  206  is formed while spaces between walls of a pattern of the insulator  202  are filled by electrolytic plating. For convenience of understanding, the plating layer  204  for the seed layer is not shown in  FIGS. 2   h  to  2   n.    
         [0054]     In  FIG. 2   i,  the plating resist  205  is stripped. If the plating resist  205  is the dry film, the stripping may be conducted using NaOH or KOH.  
         [0055]     Subsequently, the circuit pattern may be selectively subjected to a surface treatment process.  
         [0056]     In  FIG. 2   j,  an insulating layer  207  is laminated so as to assure interlayer insulation for additional lamination. A prepreg, which is used as an insulating layer in a typical process of fabricating a multilayered PCB, may be used as the insulating layer  207 .  
         [0057]     In  FIG. 2   k,  the insulating layer  207  is drilled by a laser to form a blind via hole  208  at a predetermined position thereof.  
         [0058]     In  FIG. 2   l , after a seed layer is formed on the insulating layer  207  through an electroless plating process, the via hole  208  is filled by electrolytic plating, and thus, a circuit pattern  209  is formed.  
         [0059]     Next, as shown in  FIG. 2   m , lamination of the insulating layer and formation of the circuit pattern are repeated to form the desired number of circuit layers. The total number of circuit layers depends on the insulating layer and the circuit pattern.  
         [0060]     As shown in  FIG. 2   n , a circuit pattern is formed on the other side  210  of the copper foil, thereby creating a 6-layered PCB. Formation of the circuit pattern is achieved by conducting the etching after an etching resist is applied and patterned.  
         [0061]     In the method of fabricating a PCB according to the present invention, a central layer of the PCB consists of the insulating layer  207 , such as prepreg, instead of a core insulating layer interposed between copper foils of a conventional CCL unlike a conventional multilayered PCB.  
         [0062]     The core insulating layer constituting the conventional CCL is at least 60 μm or more in thickness, but the insulating layer  207 , such as prepreg, is normally about 30 μm in thickness. Hence, the PCB of the present invention is much thinner than the conventional PCB.  
         [0063]      FIGS. 3   a  to  3   m  illustrate the fabrication of a PCB according to the second embodiment of the present invention.  
         [0064]     The procedure of  FIGS. 3   a  to  3   i  is the same as that of  FIGS. 2   a  to  2   i . In  FIGS. 3   a  to  3   i , reference numerals  301  to  306  correspond to reference numerals  201  to  206  of  FIGS. 2   a  to  2   f . For convenience of the understanding, a plating layer  304  for a seed layer is not shown in  FIGS. 3   h  to  3   m.    
         [0065]     In  FIG. 3   j , a circuit pattern is formed on a copper foil  301 . Formation of the circuit pattern may be achieved by etching a substrate after a predetermined etching resist pattern is formed.  
         [0066]     In  FIG. 3   k , an insulating layer  307  is laminated so as to assure interlayer insulation for additional lamination. A prepreg, which is used as an insulating layer in a typical process of fabricating a multilayered PCB, may be used as the insulating layer  307 .  
         [0067]     In  FIG. 3   l , the insulating layer  307  is drilled by a laser to form a via hole  308  at a predetermined position thereof. It is possible to form the via hole through a mechanical drilling process, if necessary.  
         [0068]     In  FIG. 3   m , after a seed layer is formed on the insulating layer  307  through an electroless plating process, the via hole  308  is filled by electrolytic plating, and thus, a circuit pattern  309  is formed.  
         [0069]     Unlike in  FIG. 2   n , in a sectional view of the PCB of  FIG. 3   m , the insulating layers and the circuit layers are laminated on both sides of a central insulator  302  which is capable of being patterned by ultraviolet rays.  
         [0070]     Lamination of the insulating layer and formation of the circuit pattern may be repeated to form the desired number of circuit layers. After the formation of the circuit pattern, it is preferable to conduct predetermined inspection and surface treatment processes.  
         [0071]      FIGS. 4   a  to  4   f  illustrate the fabrication of a PCB according to the third embodiment of the present invention.  
         [0072]     As shown in  FIG. 4   a , insulators  402   a ,  402   b , which are capable of being patterned by ultraviolet rays, are laminated on copper foils  401   a ,  401   b , and the resulting structures are then attached to both sides of a double-sided adhesive sheet  403  so that the copper foils  401   a ,  401   b  face each other. The double-sided adhesive sheet  403  must be capable of being released or separated from the copper foils  401   a ,  401   b  using ultraviolet rays or heat.  
         [0073]     In  FIG. 4   b , after the insulators  402  are exposed and developed by ultraviolet rays using a predetermined mask and thus patterned, a seed layer is formed by electroless plating, and a circuit pattern  404  is formed while spaces between walls of a pattern of the insulator  402  are filled by electrolytic plating.  
         [0074]     In  FIG. 4   c , an insulating layer  405  is laminated so as to assure interlayer insulation for additional lamination, and drilled through laser or mechanical drilling processes to form a via hole  406 .  
         [0075]     In  FIG. 4   d , after a seed layer is formed on the insulating layer  405  by electroless plating, the via hole  406  is filled by electrolytic plating, and thus, a circuit pattern  407  is formed.  
         [0076]     Next, lamination of the insulating layer and formation of the circuit pattern are repeated to form the desired number of circuit layers.  
         [0077]     In  FIG. 4   e , the double-side adhesive sheet  403  is released from the copper foils  401   a ,  401   b  by applying ultraviolet rays or heat to the central part of the PCB.  
         [0078]     As shown in  FIG. 4   f , the PCB is divided into two by the application of ultraviolet rays or heat, and the exposed copper foils  401   a ,  401   b  are subjected to an etching process and the like to form circuit patterns, thereby creating two PCBs that are the same as the PCB formed through a procedure of  FIGS. 2   a  to  2   n.    
         [0079]     Unlike a conventional multilayered PCB, a central layer of the PCB according to the present invention consists of the insulating layer  405 , such as prepreg, instead of a core insulating layer interposed between copper foils of a conventional CCL. Hence, the PCB of the present invention is much thinner than the conventional PCB.  
         [0080]     As described above, the present invention provides a method of fabricating a high density PCB, in which a core insulating layer is removed, resulting in a very thin PCB.  
         [0081]     Furthermore, in the method of fabricating the high density PCB according to the present invention, the core insulating layer is completely removed through exposure using ultraviolet rays instead of a mechanical cutting process, thereby reducing the thickness of the final PCB.  
         [0082]     The present invention has been described in an illustrative manner, and it is to be understood that the terminology used is intended to be in the nature of description rather than of limitation. Many modifications and variations of the present invention are possible in light of the above teachings. Therefore, it is to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described.