Abstract:
The invention relates to a circuit for a computerized photoflash control which is supplied, preferably with the aid of a photographic element, with a current corresponding to the reflected light during the flash, from which an electrical quantity terminating the flash is derived. The invention consists in that the circuit contains a comparator, with a voltage derived from the current supplied at one of its inputs, while the other input of the comparator is supplied with an adjustable reference voltage. Connected to the output of the comparator is a switching path which is actuated by the comparator upon signal output, thereby terminating the flash.

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to a circuit for a computerized photoflash control which is supplied with a current of a certain magnitude and from which an electrical quantity terminating the flash is derived. 
     Computerized photoflash circuits are known in which the reflected light is measured, and a dimension is derived from this light measurement, with the help of which the flash is terminated automatically or in an adjustable manner. 
     It is an object of the invention to provide an integratable circuit for a computerized photoflash control by means of which several operating functions can be fulfilled and which comprises a simple voltage supply with as little power consumption as possible. For example, there must be the possibility of adjusting varying lens stops or film sensitivities and of enabling switch-over to manual operation or to operation with fixedly adjustable flash times. 
     SUMMARY OF THE INVENTION 
     According to the Invention there is provided a circuit comprising a comparator, at one input of which there is a voltage derived from the current supplied, while an adjustable reference voltage is fed to the other input of the comparator, and a switch path activated by the switch-over operation of the comparator is connected to the output of the comparator. 
     The flash is terminated via the above-mentioned circuit path actuated by the comparator output, for example, by deriving current from the flashlight electrolytic capacitor or by interrupting the current flow between the flashlight electrolytic capacitor and the flash lamp. The aforementioned current of a certain magnitude may be determined with the help of a selectable fixed resistor for setting a fixed flash time. Automatic flash control is acquired if the current supplied is generated in a photographic receiver, in which case this current serves as a measure of the reflected flash light. 
     The computerized photoflash circuit preferably contains a constant current source in the form of a current amplifier resp. a current mirror whose output current circuit comprises a potentiometer. The reference voltage is generated at this potentiometer in dependence upon the set output current of the current amplifier. It is preferable to use a further potentiometer in the input current circuit of the current amplifier for setting the above-mentioned current. For receiving the reflected flash light a photodiode is preferably used whose diode current serves, with the aid of a following current amplifier, in amplified form, to charge a capacitor. The capacitor voltage is simultaneously applied to one comparator input. This current amplifier which serves the purpose of amplifying the photo current also preferably takes the form of a current mirror. 
     In an advantageous embodiment of the invention, the computerized photoflash circuit contains a so-called standby unit for generating the stabilized internal supply voltage for the comparator, the current amplifiers and the current sources in order to reduce the power consumption. This unit is only activated when a flash pulse is triggered, whereas during the times between successive flashes this same unit ensures a safe discharge of the capacitor which was previously charged by the photo current. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention and its further advantageous development are described hereinafter in greater detail, with reference to examples of embodiments. 
     FIG. 1 shows a block circuit diagram of the integrated semiconductor circuit according to the invention with its external connecting points and the components provided for connection to the integrated circuit. 
     FIG. 2 shows an external circuitry of the integrated circuit for setting varying operating lens stops. 
     FIG. 3 shows an external circuitry by means of which both varying operating lens stops and the film sensitivities can be set. 
     FIG. 4 finally also shows the detailed circuitry of the integrated circuit. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows the block circuit diagram of the integrated circuit CB for the computerized photoflash control. Voltage supply is provided via a high-impedance resistor R V  directly from the flashlight electrolytic capacitor. An internal zener diode Z 1  stabilizes the supply voltage U S  at a supply current of, for example, 100 μA to, for example 17.8 V. The zener diode Z 1  actually consists of a series circuit of individual zener diodes and diodes which are operated in flow direction, with the number of diodes being chosen such that the desired supply voltage U S  is available at point 8. The charged capacitor C V  which is connected to the series resistor R V  supplies the circuit CB during active operation. In order to reduce current input, the internal voltage supply is switched off at point A during standby operation. Simultaneously, it is ensured that the integration capacitor C I  connected to the output point 4 cannot charge itself, so that outside light cannot have a disturbing effect. When the flash unit is switched on, the circuit CB is switched to standby operation via the undervoltage recognition circuit UE. This is done with the help of a settable and resettable storage cell FF which is set with the flash pulse at the input 2, thus causing activation of the connected standby unit for generating the internal supply voltage. The starting pulse at the input 2 of the circuit is generated upon the actuation of the flash and is made available at the input 2 as a positive voltage jump. 
     If the external supply voltage decreases when a flash is terminated, owing to the discharge of the capacitor C V , and drops below a defined voltage value, the undervoltage recognition circuit UE resets the storage cell FF, which causes the standby circuit to switch off the internal supply voltage and the capacitor C I  to be discharged. 
     The reflected light during the flash hits the photographic receiver FD at the connection point 3 of the circuit CB. This photographic receiver can be a photodiode, a phototransistor or a photoresistor. In the photodiode, a current is generated proportional to the light, which then is amplified by the current amplifier V, and charges the capacitor C I  in this amplified form. The integration voltage occurring at C 1  is fed to the + input of the comparator K. At the - input of the comparator K the reference voltage which is determined by the potentiometers R REF  and R AB  at the circuit connection points 5 and 6 is applied. The aligning resistor R AB  is located in the input circuit and the resistor R REF  is located in the output circuit of a current amplifier which is designated Q in FIG. 1. The current flowing out of the connection point 5 is set to a defined value by means of the aligning resistor R AB  at the connection point 6. The adjustable reference voltage is determined by this defined current and the value of the reference resistor R REF . This reference voltage may, for example, be adjusted by changing the resistor R REF  within the limits of 0.2 V to 10.5 V, which results in an alteration of the operating lens stop. 
     The comparator output is connected to an output transistor T which supplies a current pulse by means of which, for example, a following cancelling thyristor Thy is triggered. The flash is then terminated, with the help of this triggered thyristor path, in the manner described above. In the connecting-through phase of the transistor T, the supply capacitor C V  is quickly discharged, causing the undervoltage recognition circuit UE to respond, which then sets the integrated circuit into standby operation with switched-off internal supply voltage following the resetting of the storage element FF. The capacitor C I  then discharges via the standby circuit and is kept in this discharged condition until a further flash pulse occurs. The supply capacitor C V  is once again charged to its supply voltage which is defined by the zener diode path Z 1 . 
     The operating lens stops may be adjusted by varying the storage capacitor C 1  or by varying the reference resistor R REF . FIG. 2 shows a circuit for setting several operating lens stops by varying the reference resistor. Here, the reference resistor R REF  has been replaced by the fixed resistors R 1  through R 6 , with one resistor each being connected to the connection point 5 of the integrated circuit CB via the switch S. The fixed resistor corresponding to an operating lens stop is always twice the size of the resistor corresponding to the preceding operating lens stop. 
     Manual operation is possible if the connection point 4 is grounded by bridging the capacitor C I  and the resistor R X . This results in the blocking of the comparator and the flash no longer being switched off. In the embodiment shown in FIG. 2, a maximum of 6 operating lens stops can be set if a voltage range of between 0.2 and 6.4 V can be used for reference voltage at the - input of the comparator. The setting of smaller reference voltages is difficult because of the S/N ratio which would then be too low. 
     If the photodiode FD at the connection point 3 is replaced by a fixed resistor, the integration capacitor C I  is charged with a constant current. This enables fixed flash times to be set. 
     In FIG. 3, a circuit with setting possibilities for 6 operating lens stops with 6 integration capacitors and 16 DIN film insensitivities with 16 programming resistors is shown. Of the 6 integration capacitors C 1  &#39; to C 6  &#39;, one each is connected to the connection point 4 of the integrated circuit CB via the switch S 1  in accordance with the operating lens stop selected. The film sensitivity is selected by means of the switch S 2  via which one of the resistors R 7  to R 22  corresponding to one film sensitivity, respectively, is connected to the connection point 5 of the integrated circuit. 
     The interior set-up of the integrated circuit CB is apparent from FIG. 4. 
     The external supply voltage is stabilized--as mentioned above--with the help of the zener diode path Z 1  at a defined value, for example, at 17.8 V, at the connection point 8. The current amplifier consisting of the transistors T 1  and T 2  together with the zener diode path Z 2  and the resistors R 23 , R 24  as well as the transistor T 3  forms the undervoltage recognition circuit. 
     The undervoltage at which this circuit responds is defined by means of the zener diode Z 2  in a collector branch of the multi-collector transistor T 2 . At voltages above 12 V at the connection point 8, for example, a voltage driving the transistor T 3  drops at the resistor R 24  so that the following transistor T 4  remains blocked and the storage flip-flop circuit consisting of transistors T 6 , T 5  and of the resistors R 26 , R 27  can remain in its set condition. If, however, the voltage amount defined by the zener diode Z 2  is no longer reached, a voltage is available at resistor R 24  which no longer suffices for driving the transistor T 3 . Since transistor T 3  is blocked in this case and the transistor T 4  is driven by the collector current derived from the transistor T 2 , the storage flip-flop circuit is reset since the base electrode of the transistor T 5  is put on reference potential via the connected-through transistor T 4 . 
     With no current at transistors T 5 , transistor T 6  also can no longer be supplied with sufficient base current so that both current paths formed by the storage cell are switched off and no current can be picked up at the output point C of the storage flip-flop circuit. Transistor T 11  which is connected to the output point C consequently blocks so that the current of this current branch which, in turn, is derived from a collector of the multi-collector transistor T 2  opens the following transistors T 8 , T 10  and T 35  via the series resistors R 35 , R 36  and R 37 . The input potential at the transistor T 9  thus practically drops to reference potential so that the zener diode path Z 3  remains without current. The emitter of the transistor T 9  which also constitutes the output connection A of the standby circuit is also put on reference potential via the opened transistor T 10  so that the internal supply voltage is switched off. The capacitor at connection point 4, if charged, is then quickly discharged via the diode path of the transistor T 21 . 
     When the supply voltage at the connection point 8 once again reaches its nominal value through charging of the capacitor connected at that point, transistor T 3  is switched-through and transistor T 4  is thus blocked, however nothing changes at first with respect to the stable storage condition of the storage flip-flop circuit, since a positive pulse which is generated during flash activation is required at the circuit connection point 2 for setting the storage flip-flop circuit. 
     The transistor T 14  is first connected to the connection point 2 and forms a protective diode against negative voltages. These negative voltages are directed off via the transistor T 14  which is connected as a diode. A zener diode T 15  which is connected to the connection point 2 via the resistor R 30  limits the voltage to a defined value and thus serves as overvoltage protection. This limited voltage is then fed via the voltage divider R 31 , R 32  to the base connection of transistor T 16  which is driven so that the capacitor C 3  can reverse its charge and a base current briefly opens transistor T 18  during this charge reversal phase. The transistor T 17  which is also connected to the capacitor C 3  forms a zener diode and limits the voltage at the capacitor to a maximum value which this capacitor accepts in the blocked state of the transistor T 16 . Through the opening of the transistor T 18 , the base electrode of the transistor T 5  in the storage flip-flop circuit receives a triggering pulse which becomes active simultaneously on account of the blocking of the transistor T 4  and opens the transistor T 5 . The transistor T 6  is also opened because of the voltage drop at the resistor R 26  so that current can be picked up at the output point C of the storage flip-flop circuit. The storage flip-flop circuit is thus set in a stable state and a current flows which opens the transistors T 11  and T 12 . The transistors T 8 , T 10  and T 35 , however, no longer get sufficient drive current, which causes them to block. A current therefore flows from the current supply capacitor at the connection point 8 through the resistor R 40  and the transistor T 7 , resulting in a voltage build-up at the zener diode path Z 3 . This voltage is also fed to the connection point A, however, it is reduced by a base emitter voltage. The internal supply voltage is therefore available to the remaining circuit components. The current flow via the zener diode path Z 3  is enabled by the transistors T 12  and T 13  being opened owing to the output current of the storage flip-flop circuit so that the voltage drop at resistor R 41  is sufficient for driving the transistor T 7 . 
     Since the internal supply voltage at the connection point A of the circuit is also available upon flash actuation, the current sources Q 1 , Q 2 , Q 3 , Q 4 , Q 5  and Q 6  can provide the respective output current resulting from the special design of these current sources. The same applies to the current amplifier comprised of the transistors T 19 , T 20  and T 32  and T 33 , respectively. 
     The photographic receiver is connected to the connection point 3 of the integrated circuit. In this photographic receiver there flows a current corresponding to the light reflected as input current into the collector of the transistor T 20 . Since this transistor takes the form of a current amplifier, an output current flows via output collectors of this transistor T 20  into the capacitor C I  which is connected to the connection point 4. By dimensioning the surfaces of the different collectors of the transistor T 20  it is, for example, possible to set a current amplification ratio of 3.5. The capacitor voltage which is to be compared to the reference voltage therefore builds up at the base electrode of the transistor T 23 . The reference voltage is defined and set with the help of the current amplifier comprised of the transistors T 32 , T 33  and the resistors at the connection points 5 and 6. It is applied to the base connection of transistor T 28 . 
     As long as the reference voltage is greater than the voltage at the base connection of transistor T 23 , the current determined by the current source Q 3  flows through the transistor T 25 . The transistor T 26  is blocked so that the transistors T 30  and T 29  also receive no base current. These two transistors are therefore similarly blocked so that the current flowing through the transistor T 25  reaches the base electrode of the transistor T 34  which it opens. The current delivered by the current source Q 6  therefore flows via the transistor T 34  since the transistor T 35  is blocked. 
     When the voltage at the capacitor at the connection point 4 exceeds the reference voltage at the base connection of the transistor T 28 , the transistor T 26  of the comparator becomes conductive and opens the transistors T 29  and T 30 . The transistor T 34  of the output gate consequently no longer receives any base current, causing this transistor to block, with the current delivered by the current source Q 6  flowing to the base connection of the output transistor T 36  which it connects through. The output transistor is constructed as a Darlington transistor with the transistors T 36 , T 37  and T 38  with the respective base leak resistors R 45 , R 46  and R 47  so that all these transistors are connected through, owing to the output signal of the comparator comprised by the transistors T 23  to T 28 . The output stage which is connected through triggers further switching processes which take the current away from the flash lamp so that the flash is terminated. Simultaneously, the capacitor C V  which is connected to the connection point 8 of the circuit quickly discharges via the transistors T 36  to T 38 , causing the undervoltage recognition circuit to respond in the manner described and the storage flip-flop circuit with the transistors T 5  and T 6  to be set back into the current-less state. The internal supply voltage at the connection point A is thereby switched off again and the capacitor at the connection point 4 can discharge to reference potential via the diode path of the transistor T 21 . 
     At very low reference voltages, the capacitor at the connection point 4 may only be charged up to a very low voltage in order to terminate the flash. In such cases, this low voltage may drop immediately after the build-up of the internal supply voltage because of parasitic transistor capacities at the base electrode of the transistor T 23 , so that no flash occurs at all. In order to prevent this from happening, the capacitor C 2  provided is first charged during the voltage rise of the internal supply voltage. During the charging time which is selected to be of short duration, the transistor T 22  connected to the capacitor C 2  is open so that the base connection point of the transistor T 23  is sure to be kept at reference potential. Only after the capacitor C 2  is charged, does the transistor T 22  block, and the capacitor C I  connected to the connection point 4 of the circuit can be charged by the output current of the current amplifier T 20 . By dimensioning the capacitor C 2  and the resistor R 43 , this switch-on phase is selected to be so short that it will be of no significance during the flash. This measure does, however, ensure that a flash definitely occurs even when extremely short flash times are set. 
     The comparator comprised of transistors T 23  to T 28  is set up in the manner of a differential amplifier with series stages. The transistors T 34  and T 35  form an output gate via which the output signal of the comparator is coupled out and then directed to the final stage consisting of the transistors T 36  to T 38 . The current sources Q 1  to Q 6  preferably also take the form of current amplifiers in the conventional manner. Insofar as not already described, the linking of the individual circuit components is apparent from FIG. 4. This Figure also shows which transistors are of the positive-negative-positive line type and which are of the negative-positive-negative line type.