Abstract:
A bandpass analog to digital converter includes M single channel delta sigma modulators having N-bit quantizer outputs arranged in a parallel configuration and operated at a predetermined sample frequency (f s ). The modulator outputs are time interleaved and digitally combined in a manner that provides performance characteristics comparable to a modulator with a sample frequency of Mf s . Thus, bandpass center frequencies that are much higher than conventional single channel architectures are achievable. Single channel first order modulator bandpass center frequencies are restricted to f c =f s /4. However, a range of center frequencies approaching Mf s /2 is supported. This increased frequency capability is obtained while maintaining the delta sigma noise shaping near the higher bandpass center frequencies to reduce the effects of quantization noise. This results in a high signal to noise ratio with a corresponding high resolution at the much higher center frequencies.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application No. 60/257,614 filed Dec. 21, 2000, which is incorporated herein by reference. 
    
    
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
     The present invention was made with Government support under contract F33615-00-C-1638 awarded by the Department of Defense. The Government has certain rights in the invention. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates in general to analog to digital converters, and in is particular to analog to digital converters comprising a parallel, time-interleaved delta sigma modulator architecture. 
     Digital circuitry has become increasingly prevalent in a wide variety of electronic devices including telecommunications, audio, video, portable/mobile communication transmitters and receivers, and other consumer products. One reason for the popularity of digital circuitry is that digital signal processing can be used to replace large numbers of analog components. Eliminating analog components from a device can lead to a reduction in the size, weight, and power requirements, while increasing flexibility and reliability of the device. 
     Analog-to-digital converters (ADCS) provide a link between the analog and digital domains. The ADC must be capable of converting analog data to digital data in an accurate manner, appropriate to the bandwidth and resolution needs of a given application. One type of ADC that is commonly used for analog to digital conversion is the oversampling ADC based on delta sigma (ΔΣ) modulation. Oversampling ADCs are used in applications requiring high-resolution analog to digital conversion because this approach permits high resolution without the need for extremely tight tolerances for analog components. ΔΣ modulation may be implemented using a mix of analog and digital circuitry, and is comprised generally of an input sampler, a filter, a quantizer, and a feedback path to sum the quantizer output back into the input to the filter. The quantizer output signal also defines the ΔΣ modulator output signal. A clock signal supplied to the ΔΣ modulator determines the sampling frequency, or the frequency at which the modulator output is updated. 
     Oversampling ADCs use an oversampling ratio (OSR) that is the ratio of the sampling frequency of the ΔΣ modulator to twice the bandwidth (Nyquist Frequency) of the input signal. The oversampling ratio is typically greater than one, and is often twenty-five or more. For conventional first order ΔΣ modulators, the signal to quantization noise (S/N) ratio increases by approximately 9db (1.5 bits) for each doubling of the OSR. Thus, better resolution is achieved by implementing a higher OSR, that is, by using a sampling frequency that is much higher than the Nyquist Frequency. However, circuit components that operate at higher frequencies are difficult to realize and if realizable, cost more than those that operate at lower frequencies. 
     For example, when designing mixed signal circuits based upon clocked systems, the maximum clock frequency is usually determined by the slowest component in the system. In ΔΣ modulation circuits, it is usually the settling of the key analog component of the modulator that takes the longest time, and thus the bandwidth of an analog signal converted to digital information by a delta sigma modulator is limited by the maximum achievable clocking rate of the modulator. 
     Accordingly, despite the advantages of ΔΣ modulation ADC circuits, the need to oversample the input signal by the modulator renders ΔΣ modulation impractical for certain higher frequency applications. Many applications require a bandpass ADC, where the analog input signal frequency is centered at a high frequency and confined to some bandwidth. For example, the trend in modern receiver design is to move the analog-to-digital interface as close as possible to the antenna or sensor. Having the analog-to-digital conversion closer to the antenna in the signal path (higher frequency) eliminates multiple stages of down conversion to lower frequencies and the associated components such as analog filtering. However, moving the analog to digital interface to higher frequencies requires bandpass ADCs with high center frequencies and good resolution. The center frequencies may range from hundreds of Megahertz to tens of Gigahertz with bandwidths that are relatively small compared to the center frequencies. 
     Accordingly, there is a need for bandpass ΔΣ modulation analog to digital conversion circuits that are capable of converting analog signals having very high center frequencies and having high resolution within a given bandwidth. 
     SUMMARY OF THE INVENTION 
     The present invention overcomes the disadvantages of previously known delta sigma analog to digital converters by providing a time-interleaved delta sigma modulator architecture that allows the conversion of relatively high frequency signals with a relatively low sample frequency. 
     In accordance with one embodiment of the present invention, a bandpass time interleaved delta sigma modulator analog to digital conversion architecture comprises an analog input signal that is coupled in parallel, to a plurality of modulators. The output of each modulator is coupled to a respective input of a multiplexer, and the multiplexer output is coupled to a bandpass filter and decimation circuitry to provide the analog to digital conversion circuit output. Each modulator is clocked by a signal that operates at a predetermined sample frequency, and is time phase shifted such that each modulator samples the analog input signal in a time-interleaved manner. Also, the multiplexer includes an input control that is synchronized with the various time-interleaved clock signals such that the output of the multiplexer is updated to reflect the output of each of the plurality of modulators once per cycle of the sample frequency. 
     For example, M single channel delta sigma modulators having N-bit quantizer outputs are arranged in a parallel configuration and operated at a predetermined sample frequency (f s ). The modulator outputs are time interleaved and digitally combined in a manner that provides performance characteristics comparable to a modulator with a sample frequency of Mf s . Thus, bandpass center frequencies that are much higher than conventional single channel architectures are achievable. Typical single channel first order modulator bandpass center frequencies are restricted to f c =f s /4. However, the present invention supports a range of center frequencies approaching Mf s /2. This increased frequency capability is obtained while maintaining the delta sigma noise shaping near the higher bandpass center frequencies to reduce the effects of quantization noise. This results in a high signal to noise ratio with a corresponding high resolution at the much higher center frequencies. 
     Accordingly, it is an object of the present invention to provide a delta sigma modulator analog to digital converter architecture that allows the conversion of relatively high frequency signals with a relatively low sample frequency clock. 
     It is an object of the present invention to provide a bandpass delta sigma modulator analog to digital conversion architecture that can convert signals having an increased center frequency over single delta sigma modulator architectures. 
     Other objects of the present invention will be apparent in light of the description of the invention embodied herein. 
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
     The following detailed description of the preferred embodiments of the present invention can be best understood when read in conjunction with the following drawings, where like structure is indicated with like reference numerals, and in which: 
     FIG. 1 is a schematic illustration of a time-interleaved analog to digital converter according to one embodiment of the present invention; 
     FIG. 2 is an illustration of a timing diagram according to one aspect of the present invention where M total modulators are implemented in a parallel time interleaved fashion; 
     FIG. 3 is a schematic illustration of a portion of the circuit of FIG. 1, where each modulator is implemented as a first order band pass delta sigma modulator; and, 
     FIG. 4 is a schematic illustration of a portion of the circuit of FIG. 1, where each modulator is implemented as a first order low pass delta sigma modulator. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration, and not by way of limitation, specific preferred embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and that logical and electrical changes may be made without departing from the spirit and scope of the present invention. 
     Bandpass Parallel Time Interleaved ΔΣ Modulator ADC 
     Referring to FIG. 1, a parallel time interleaved ΔΣ modulator ADC circuit  100  according to one embodiment of the present invention comprises a plurality of modulators  102 , a multiplexer  104 , and a filter or other processing circuitry  106 . Each modulator  102  comprises a modulator input  108 , a clock input  110 , and a modulator output  112 . An analog input signal u(n)  114 , an input voltage V in  as illustrated, is coupled in parallel to each modulator input  108 . Each modulator  102  is configured to produce an N-bit digital output where N is the number of quantization bits of the modulator outputs  112 . 
     The multiplexer  104  comprises a plurality of multiplexer inputs  116 , a multiplexer input control  118 , and a multiplexer output  120 . Each modulator output  112  is coupled to a respective one of the multiplexer inputs  116 . The multiplexer input control  118  is configured to select between the various N-bit modulator outputs  112  such that at any given time, the multiplexer output  120  comprises a select one of the modulator outputs  112 . Accordingly, the multiplexer output  120  also comprises a digital N-bit word. The multiplexer output  120 ,or first output signal (Y 1 ), is coupled to additional digital processing circuitry  106  as the application dictates. For example, processing circuitry  106  may comprise a filter and decimation circuit. Under this arrangement, the first output signal (Y 1 ) or multiplexer output  120  is coupled to a filter that implements a lowpass or bandpass filtering function. The signal then couples to a decimation circuit to produce a second output signal (Y 2 ), also referred to herein as the ADC output  122 . The ADC output  122  comprises a multi-bit digital word output. The number of bits (K) in the ADC output  122  will depend upon the application in which the parallel time interleaved ΔΣ modulator ADC circuit  100  is being used. 
     As shown in FIG. 1, there are a total of M modulators  102 . Each modulator  102  defines a channel of the parallel time interleaved ΔΣ modulator ADC circuit  100 , and comprises a first order, or higher order ΔΣ modulator. The number of ΔΣ modulators  102  employed, the type and order of each ΔΣ modulator  102 , and the number of quantization bits of each ΔΣ modulator output  112  will depend upon the sampling requirements of the application to which the parallel time interleaved ΔΣ modulator ADC circuit  100  is being used. 
     Each ΔΣ modulator clock input  110  is arranged to receive a clock signal  124 - 132  that operates at a predetermined sample frequency f s . Each ΔΣ modulator  102  samples the analog input signal  114  once every cycle of the sample frequency f s . However, each clock signal  124 - 132  applied to an associated one of each ΔΣ modulators  102  is time phase shifted such that each ΔΣ modulator  102  samples the analog input signal  114  at a different time, or in a time-interleaved fashion. Preferably, each ΔΣ modulator output  112  is updated in a time-phased manner that corresponds to the sampling of the input signal  114  at the corresponding ΔΣ modulator input  108 . Accordingly, the ΔΣ modulator outputs  112  are also updated in a time-interleaved fashion. 
     A timing diagram illustrating the time phase relationship between clock signals  124 - 132  supplied to the ΔΣ modulator clock inputs  110  is illustrated in FIG.  2 . There are M distinct clock signals  124 - 132 , each clock signal having a period of        τ   =     1     f   s                              
     where f s  is the sampling frequency. As illustrated, the rising edge of the first one of the clock signals CLK (1)    124  occurs at time t=0. Each successive clock signal CLK (2) -CLK (M)   126 - 132  is time phased shifted by an amount defined by the equation,          Δ                 t     =       1     Mf   s       .                            
     Accordingly, each ΔΣ modulator receives an associated one of the clock signals  124 - 132  that operates at a frequency that is equal to the sampling frequency f s , and time phased an amount equal to          t   m     =       (     m   -   1     )       Mf   s                              
     where m is the m th  ΔΣ modulator of M total ΔΣ modulators. 
     Referring back to FIG. 1, according to one aspect of the present invention, the analog input signal  114  comprises an input voltage V in . Thus, each sample taken at a select one of the ΔΣ modulator inputs  108  is expressed as          V   m     =         V   in          (     t   -       m   -   1       Mf   s         )       .                            
     Because each ΔΣ modulator  102  samples at the sample frequency f s  and is time shifted such that the input signal  114  is sampled in a time-interleaved manner, the analog input signal  114  is effectively sampled at a rate of Mf s  for M total ΔΣ modulators  102 . Likewise, where each ΔΣ modulator output  112  is time shifted similar to its respective input  108 , the digital representation of the analog input signal  114  is effectively updated at a rate of Mf s  for M total ΔΣ modulators  102 . 
     The multiplexer  104  comprises a MUX, switch or other device that performs an M to 1 switching of an N-bit digital word. The multiplexer  104  thus provides an N-bit multiplexer output  120  that represents the N-bit modulator output  112  of a select one of the plurality of ΔΣ modulators  102  at a given time. Preferably, the multiplexer output  120  is updated at a frequency of Mf s  to reflect the value of the next successive one of the ΔΣ modulators  102 , thus the N-bit multiplexer output  120  (Y 1 ) changes at a rate of Mf s  to synchronously select each time interleaved ΔΣ modulator output  112 . For example, as illustrated, the multiplexer input control  118  comprises one or more input selection control signal inputs of the multiplexer  104  that are preferably synchronized with the sample frequency clock signals  124 - 132  coupled to the ΔΣ modulator clock inputs  110 . 
     Bandpass ΔΣ Architecture Using Bandpass Modulators 
     Referring to FIG. 3 each ΔΣ modulator  102  may be implemented as a first order bandpass ΔΣ modulator. The ΔΣ modulator  102  comprises a first summing node  140  having first and second inputs  142 ,  144 , and an output  146 , a second summing node  148  having first and second inputs  150 ,  152  and an output  154 , first, second, and third delay elements  156 ,  158 ,  160 , a comparator or quantizer  162 , a first feedback path  164 , a second feedback path  166  and a digital to analog converter  168 . The analog input signal V in    114  is coupled to the first input  142  of the first summing node  140 . The output  146  of the first summing node  140  is coupled to the first input  150  of the second summing node  148 . The output  154  of the second summing node  148  is coupled to the first delay element  156 . The output of the first delay element  156  is coupled to the second delay element  158  via the first feedback path  164 , and the output of the second delay element  158  is coupled to the second input  152  of the second summing node  148 . As illustrated, the output of the second delay element  158  at the second input  152  of the second summing node  148  is subtracted from the input signal at the first input  150  of the second summing node  148  to provide the proper noise shaping function. 
     The output of the first delay element  156  is also coupled to the third delay element  160 , and the output of the third delay element  160  is coupled to the quantizer  162 . The quantizer  162  provides modulator output  112 , which comprises an N-bit digital word Y(z). The modular output  112  is coupled to a select one of the multiplexer inputs  116 . Additionally, the N-bit digital word output of the quantizer  162  is coupled via the second feedback path  166  to the digital to analog converter  168 , and the analog version of the quantizer output is coupled to a second input  144  of the first summing node  140  such that the analog version of the quantizer output is added to the analog input signal  114  to provide the desired noise shaping characteristics. As illustrated, the bandpass ΔΣ modulator  102  implements the function          H        (   z   )       =         z     -   2         1   +     z     -   2           .                            
     For each ΔΣ modulator  102  or channel, the N-bit output of the quantizer  162  is expressed as the sum of a signal component (S TF ) and a quantization noise component (N TF ) and can be expressed by the formula:          Y        (   z   )       =         S   TF          u        (   z   )         +       N   TF          E        (   z   )                       where   :     S   TF       =           H        (   z   )         1   -     H        (   z   )                         and                   N   TF       =     1     1   -     H        (   z   )               ,   thus             S   TF     =         z     -   2                     and                        N   TF            =            1   +     z     -   2              =     2        cos        (       2      π                 f       f   s       )                                    
     The input signal is propagated with only a delay, and the quantization noise is attenuated at frequencies in the vicinity of fs/4. For linear system approximations, the quantization noise is approximated as additive random noise shaped by a notch filter characteristic of the noise transfer function. The actual noise is likely deterministic and dependent upon the input. However, linear approximations are sufficient to model the embodiments of the present invention described herein. 
     Referring back to FIG. 1, according to one embodiment of the present invention, the filter and other processing circuitry  106  comprises a bandpass filter. It will be observed that if a single, conventional, ΔΣ bandpass modulator output is coupled to the bandpass filter  106 , and the bandpass center frequency is tuned to a frequency of f s /4, then a signal with a bandwidth f Δ will be passed, and the quantization noise is reduced by the noise shaping in the bandwidth of interest. The theoretical maximum in-band signal to noise ratio of the first order ΔΣ bandpass modulator output is given by:          S   /     N        (   db   )         =       6.02      N     -   6.42   +     30        log        (       f   s       f   Δ       )                                  
     where f Δ is the bandwidth of the analog input signal centered at f c . This expression assumes that the analog input signal  114  comprises a sine wave having an amplitude set to the maximum value (V ref ) and the quantization noise has a spectral density that is uniform over the frequency range f s , but provides a convenient reference for comparison as will be explained more fully herein. 
     Approximately 6db of signal to noise ratio is achieved for each bit of resolution. Also, higher signal-to-noise ratios (higher resolution) is obtained by restricting the bandwidth f Δ to small values relative to f s . For a single channel of the bandpass ΔΣ modulator  102 , the signal to noise ratio increases by the factor  30  log        (       f   s       f   Δ       )                          
     where the ratio        (       f   s       f   Δ       )                          
     is called the oversampling ratio. The larger the oversampling ratio, the larger the signal-to-noise ratio and the better the resolution. 
     However, the maximum in-band S/N ratio obtained by the parallel time interleaved ΔΣ modulator ADC  100  comprising M bandpass ΔΣ modulators  102  is:          S   /     N        (   db   )         =       6.02      N     -   6.42   +     30        log        (       f   s       f   Δ       )         +     10                 log                 M                              
     Thus the signal to noise ratio of the parallel time interleaved ΔΣ modulator ADC  100  is substantially the same as that defined above for a single channel of the bandpass ΔΣ modulator, except that the quantization noise at the output of the multiplexer is distributed over a frequency range of Mf s . As such, the signal to noise ratio is increased by the ΔΣ modulation noise shaping          (     30                   log        (       f   s       f   Δ       )         )     ,                          
     and the signal to noise ratio is further increased over a single bandpass ΔΣ modulator by the frequency spreading term 10logM. 
     It will be appreciated that the center frequency of the bandpass filter will depend upon the noise shaping function of the individual ΔΣ modulators  102 . The noise shaping function for a single channel bandpass ΔΣ modulator has a value of zero at:          f   c     =         (       2      n     -   1     )          f   s       4                            
     where n is an integer equal to or greater than zero. Limiting the range of center frequencies based upon the Nyquist theorem, the center frequency f c  of the bandpass filter is preferably chosen as              f   c     &lt;         Mf   s     2                   or                   f   c         =       f   s     4       ,       3        f   s       4     ,         5        f   s       4                   …                ,     (         Mf   s     2     -       f   s     4       )                            
     in order to diminish the quantization noise by the noise shaping function of the individual bandpass ΔΣ modulators operating at a frequency of f s . 
     Accordingly, the center frequency of the parallel time interleaved ΔΣ modulator ADC  100  according to FIGS. 1-3 can be extended to frequencies much higher than a single bandpass ΔΣ modulator operating at a frequency of f s , which is limited to f s /4, while obtaining the required S/N ratio for high resolution. The parallel time interleaved ΔΣ modulator ADC  100  uses M single channel ΔΣ modulators  102  in parallel to dramatically increase the range of bandpass center frequencies that can be used while retaining and improving the advantages of the ΔΣ noise shaping of the individual modulators. 
     As an example, assume the parallel time interleaved ΔΣ modulator ADC  100  comprises a total of 8 bandpass ΔΣ modulators  102  or channels, each having a 4 bit quantized modulator output  112 , wherein the respective clock signal inputs  110  are coupled to time interleaved clock signals as described herein, with sampling frequency f s =100MHz. The effective sampling frequency is Mf s =800MHz. The multiplexer  104  comprises an 8-to-1 multiplexer having a 4 bit multiplexer output  120 . The center frequency of the bandpass ADC is preferably selected to be any one of the following: f s /4, 3f s /4, 5f s /4, 7f s /4, 9f s /4, 11f s /4, 13f s /4, or 15f s /4, that is, the center frequency for the 8 channel parallel architecture is preferably chosen to be one of 25 MHz, 75 MHz, 125 MHz, 175 MHz, 225 MHz, 275 MHz, 325 MHz and 375 MHz in the above example. 
     If each ΔΣ modulator comprises a bandwidth f Δ =1.6MHz, then the S/N ratio of the parallel time interleaved ΔΣ modulator ADC  100  is approximatey 80.5db (about 13 bits). 
     In comparison, for a conventional single channel bandpass ΔΣ modulator having a sampling frequency of 100Mhz and a bandwidth of 1.6Mhz as per the above example, the center frequency is restricted to f s /4. Using a sampling frequency of 100 Mhz, the center frequency is limited to 25 MHZ. Also, using the above stated equation for the signal to noise ratio of a first order bandpass ΔΣ modulator, the conversational ΔΣ modulator has a S/N ratio of approximately 71.5 db (about 12 bits). This example clearly demonstrates that the present invention dramatically increases the range of possible center frequencies that can be obtained with individual ΔΣ modulators operating at relative low sample frequencies, f s . This example further illustrates the improvement in signal to noise ratio introduced by the frequency spreading term 10logM. 
     The above discussion is based upon single order ΔΣ modulators. However, higher order ΔΣ modulators may also be used in the present invention. Certain advantages such as higher signal to noise ratio are realized by using such higher order ΔΣ modulators. For example, by replacing the ΔΣ modulators  102  schematically illustrated in FIG. 3 with second order ΔΣ modulators, the ΔΣ modulation noise shaping component of the signal to noise ratio increases to          (     50                   log        (       f   s       f   Δ       )         )     .                          
     Bandpass ΔΣ Architecture Using Lowpass Modulators 
     Referring to FIG. 4, each of the ΔΣ modulators  102  may also be implemented as a first order low pass ΔΣ modulator. Each lowpass ΔΣ modulator comprises a first summing node  172  having first and second inputs  174 ,  176  and an output  178 , a second summing node  180  having first and second inputs  182 ,  184  and an output  186 , a delay element  188 , a comparator or quantizer  190 , first and second feedback paths  192 , 194 , and a digital to analog converter  196 . The analog input signal  114  u(n) is coupled to the first input  174  of the first summing node  172 . The output  178  of the first summing node  172  is coupled to a first input  182  of the second summing node  180 , and the output  186  of the second summing node  180  is coupled to the delay element  188 . 
     The output of the delay element  188  is fed back via the first feedback path  192  and coupled to the second input  184  of the second summing node  180  such that the output of the delay element  188  is subtracted from the first input  182  to the second summing node  180 . The output of the delay element  188  is also coupled to the quantizer  190 . The output of the quantizer  190  defines the ΔΣ modulator output  112 , and is also fed back via the second feedback path  194  and the digital to analog converter  196  to the second input  176  of the first summing node  172 . The output of the quantizer  190  is subtracted from the analog input signal at the first summing node to keep the output bounded. As illustrated, the lowpass ΔΣ modulator  102  implements the function          H        (   z   )       =       1     z   -   1       .                            
     The quantizer output  112  comprises discrete comparator decisions represented by N-bits, where N comprises at least one bit. For example, for a one-bit quantizer  112 , the comparator decision takes a value approximately equal to either the positive rail (+V ref ) or the negative rail (−V ref ) of the comparator supply voltages. 
     The quantizer output  112  is the sum of a signal component (S TF ) and a quantization noise component (N TF ) and can be expressed by the formula:          Y        (   z   )       =           S   TF          U        (   z   )         +       N   TF          E        (   z   )                       where   :     
          S   TF           =           H        (   z   )         1   +     H        (   z   )                         and                   N   TF       =       1     1   +     H        (   z   )                         thus                   S   TF     =         z     -   1                     and                   N   TF       =         (     1   -     z     -   1         )                   with                        N   TF            =     2      sin                   πf     f   s                                    
     The input signal is propagated with a delay, while the quantization noise is attenuated at low frequencies by the noise shaping of the discrete integrator. The integrator is schematically illustrated as the second summing node  180  coupled to the delay element  188  including the unity gain first feedback path  192  coupling the output of the delay element  188  back to the second input  184  of the second summing node  180 . 
     The theoretical maximum in-band signal to noise ratio of each lowpass ΔΣ modulator is:          S   /     N        (   db   )         =       6.02      N     -   3.41   +     30                   log        (       f   s       2        f   0         )                                  
     As with the bandpass ΔΣ modulator discussed above with reference to FIG. 3, this expression assumes that the analog input signal comprises a sine wave having an amplitude set to the maximum value (V ref ) and the quantization noise has a spectral density that is uniform over the frequency range f s . N represents the number of bits of the quantizer output. For a one bit quantizer, N=1. The oversampling ratio is defined as:        OSR   =       f   s       2        f   0                                
     where f 0 =the bandwidth of the input signal. 
     It will be appreciated that the lowpass ΔΣ modulator schematically illustrated in FIG. 4 comprises a first order lowpass ΔΣ modulator. However, the present invention may also be implemented with higher order lowpass ΔΣ modulators. Higher order ΔΣ modulators result in a quantization noise transfer function N TF =(1−z −1 ) L where L is the order of the ΔΣ modulator. The magnitude of the N TF  is given by                 N   TF          (   f   )            =         [     2      sin          π                 f       f   s         ]     L     .                            
     Thus, higher order lowpass ΔΣ modulators yield an increased attenuation of the quantization noise at low frequencies. 
     Referring back to FIG. 1, assume that the filter  106  is implemented as a bandpass filter. The center frequency f c  of the bandpass filter  106  depends upon the desired noise shaping functions of the individual ΔΣ modulators. The noise shaping function of the low pass ΔΣ modulators  102  have a magnitude of               N   TF          =     2      sin            π                 f       f   s       .                              
     Thus the noise function has a value of zero at          f   c     =       nf   s     &lt;       Mf   s     2                              
     where n is greater than or equal to zero, thus            f   c     =   0     ,     f   s     ,     2        f   s       ,     …                     (         Mf   s     2     -     f   s       )     .                              
     It will be appreciated that a center frequency below the Nyquist frequency will result in the quantization noise being diminished by the noise shaping function of the ΔΣ modulators operating at a frequency of f s . 
     The signal to noise ratio of the parallel time interleaved lowpass ΔΣ modulator ADC is:          S   /     N        (   db   )         =       6.02      N     -   3.41   +     30        log        (       f   s       f   Δ       )         +     10                 log                 M                              
     where f Δ is the bandwidth centered at frequency f c . The lowpass modulators see an input signal that ranges in frequency from          f   c     -       f   Δ     2                            
     to          f   c     +         f   Δ     2     .                            
     Thus the modulations are subsampling the input signals, and the quantized sampled data outputs of each modulator is a low frequency alias of the input. For example, if f s =100 MHz and f c =100 MHz, then an input signal of 102 Mhz would result in a 2 MHz quantitized sampled data output signal from each modulator. Similarily, a 98 MHz input signal would again result in a 2 MHz quantitized sampled data output, but would be phase reversed compared to the 102 MHz signal. With the multiple time interleaved channels, the sampled data output signal in the frequency range of          f   c     -       f   Δ     2                            
     to          f   c     +       f   Δ     2                            
     can be reconstructed by multiplexing the modulator outputs. Thus the noise shaping is like a notch filter centered at F c  and the signal to noise ratio at the output of the bandpass filter is the same as that obtained for the bandpass modulator. This results in the signal to noise ratio increasing by approximately 6 db when compared to the signal low pass modulator with the same bandwidth. In addition, the signal to noise ratio is increased by 10logM over the signal low pass ΔΣ modulator design because the quantization noise at the output of the modulator is distrubuted over a frequency of Mf s . 
     For example, assume each ΔΣ modulator comprises a lowpass ΔΣ modulator having a 4-bit quantizer output, and that the sample frequency f s =100 MHz. If M=8 (there are a total of 8 lowpass ΔΣ modulators) then the effective sampling rate is 800 Mhz and the bandpass center frequency is preferably selected at any one of 100 MHz, 200 MHz or300 MHz          (       f   c     &lt;       Mf   s     2       )     .                          
     The output of the multiplexer  104  is updated at a frequency Mf s =800 MHz. If the bandpass filter has a bandwidth f Δ =1.6 Hz, then the signal to noise ratio S/N =80.5 db (or 13 bits of resolution). If the bandwidth (f Δ ) of the bandpass filter is decreased, the effective oversampling ratio (f s /2f Δ ) is increased, resulting in a higher S/N ratio. 
     Notably, again, the present invention dramatically increases the range of possible center frequencies that can be obtained with individual ΔΣ modulators operating at relative low sample frequencies, f s . Further, signal to noise ratios are increased by the ΔΣ modulation noise shaping        (     30                   log        (       f   s       f   Δ       )         )                          
     and by the frequency spreading term (10 logM). Again by replacing the first order ΔΣ modulators  102  schematically represented in FIG. 4 with second order modulators, the signal to noise ratio increases by          (     50                 log                   (       f   s       f   Δ       )       )     .                          
     Having described the invention in detail and by reference to preferred embodiments thereof, it will be apparent that modifications and variations are possible without departing from the scope of the invention defined in the appended claims.