Abstract:
The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. The present disclosure relates to a method of forming a strain inducing layer or cap layer at the RPG (replacement poly silicon gate) stage of a finFET device formation process. In some embodiments, the strain inducing layer is doped to reduce the external resistance.

Description:
REFERENCE TO RELATED APPLICATION 
       [0001]    This Application is a Divisional of U.S. application Ser. No. 14/100,263 filed on Dec. 9, 2013, the contents of which is hereby incorporated by reference in its entirety. 
     
    
     BACKGROUND 
       [0002]    With the scaling of integrated circuits, more devices are put into a chip. This not only requires the shrinkage of the device size, but it also requires an improvement in the manufacturing techniques. Fin field-effect transistors (Fin FETs) have increased drive currents and hence faster switching speed over planar transistors. As devices continue to get smaller, precise control of gate lengths also becomes critical to assure performance. Strain engineering is employed in semiconductor manufacturing to enhance device performance. Performance benefits are achieved by modulating strain in the transistor channel, which enhances electron mobility (or hole mobility) and thereby conductivity through the channel. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0003]      FIG. 1  illustrates a flow diagram of some embodiments of a method for forming a strain-inducing layer over a transistor channel at a replacement poly-silicon gate (RPG) stage of a fin field-effect transistor (finFET) formation process. 
           [0004]      FIGS. 2A-2F  illustrate 3-dimensional images of some embodiments of the present disclosure and their corresponding cross sections along two perpendicular directions. 
           [0005]      FIG. 3  illustrates a flow diagram of some embodiments of a method for forming a strain-inducing layer over a recessed fin of a finFET device. 
           [0006]      FIGS. 4A and 4B  illustrate cross sectional images along two perpendicular planes of a finFET device comprising a strain-inducing layer over a recessed fin. 
           [0007]      FIG. 5  illustrates a flow diagram of some embodiments of a method comprising forming a pair of spacers after the formation of a strain-inducing layer. 
           [0008]      FIGS. 6A and 6B  illustrate cross sectional images along two perpendicular planes of a finFET device comprising a strain-inducing layer and second pair of spacers. 
           [0009]      FIGS. 7A and 7B  illustrate cross sectional images along two perpendicular planes of a finFET device comprising a strain-inducing layer over a recessed fin and, a second pair of spacers. 
           [0010]      FIG. 8  illustrates a flow diagram of some embodiments of a method comprising tilt implantation in the LDD regions after formation of a strain-inducing layer. 
           [0011]      FIG. 9  illustrate a cross sectional image of a finFET device with an open gate region during tilt implantation. 
           [0012]      FIG. 10  illustrates a flow diagram of some embodiments of a method of forming a dual capping layer comprising a doped low resistance layer and an undoped strain-inducing layer. 
           [0013]      FIG. 11  illustrate a cross sectional image of a finFET device comprising a doped low resistance layer and an undoped strain-inducing layer. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]    The description herein is made with reference to the drawings, wherein like reference numerals are generally utilized to refer to like elements throughout, and wherein the various structures are not necessarily drawn to scale. In the following description, for purposes of explanation, numerous specific details are set forth in order to facilitate understanding. It may be evident, however, to one skilled in the art, that one or more aspects described herein may be practiced with a lesser degree of these specific details. In other instances, known structures and devices are shown in block diagram form to facilitate understanding. 
         [0015]    Strain engineering is employed in semiconductor manufacturing to enhance device performance. Strained silicon is a layer of silicon in which the silicon atoms are stretched beyond their normal inter atomic distance. This can be accomplished by putting the layer of silicon over a substrate of silicon germanium (SiGe), for example. As the atoms in the silicon layer align with the atoms of the underlying silicon germanium layer, which are arranged farther apart with respect to those of a bulk silicon crystal, the links between the silicon atoms become stretched thereby leading to strained silicon. At the atomic level, it is easier for carriers to pass through on appropriately strained lattice compared to an unstrained lattice, leading to faster switching times for transistor. 
         [0016]    In CMOS technologies, PMOS and NMOS respond differently to different types of strain. Specifically, PMOS performance is best served by applying compressive strain to the channel, whereas NMOS receives benefit from tensile strain. SiGe (Si 1-x Ge x ), consisting of any molar ratio of silicon and germanium, is commonly used as a semiconductor material in integrated circuits (ICs) as a strain-inducing layer for strained silicon in CMOS transistors. The larger lattice constant of the SiGe film provides uniaxial strain to the Si channel. The higher the Ge concentration, the larger the strain and thus better performance. However, sequential processes and thermal steps during the formation of a field effect transistor tend to relax the stress of the strain-inducing layer and constrain upper limit of Ge concentration. Doping the SiGe strain-inducing or cap layer is not a flexible option to boost the device performance. 
         [0017]    Accordingly, the present disclosure relates to a method of forming a SiGe strain-inducing layer or cap layer at a later stage of formation of a fin field effect transistor (finFET) device, specifically at a replacement polysilicon gate (RPG) stage of an RPG process, so that a higher Ge concentration can be utilized which leads to better carrier confinement and greater doping flexibility. An RPG process helps in controlling gate length and preventing metal migration during elevated temperature operations. In an RPG process, a dummy gate is formed of silicon dioxide or a polymer such as photoresist. After the high temperature processes involved in device formation are completed, the dummy gate is removed leaving a gate opening and the desired gate material is deposited in to the gate opening. 
         [0018]      FIG. 1  illustrates a flow diagram of some embodiments of a method  100  for forming a strain-inducing layer over a transistor channel at a replacement poly-silicon gate (RPG) stage of a fin field-effect transistor (finFET) formation process. 
         [0019]    While disclosed method  100  (and other methods described herein) is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. 
         [0020]    At  102 , a dummy gate electrode layer is formed over a semiconductor fin. In some embodiments, the dummy gate electrode layer is composed of poly silicon having a thickness ranging from approximately 100 nm to 300 nm. 
         [0021]    At  104 , the dummy gate electrode layer is patterned using photolithography and anisotropically etched to form a dummy gate having sidewalls. 
         [0022]    At  106 , spacers are formed on either side of the dummy gate. In some embodiments, the spacers are preferably composed of silicon dioxide (SiO 2 ), silicon oxynitride (Si x  O y  N Z ), composite (SiO 2 /Si 3  N 4 ), or most preferably silicon nitride (Si 3  N 4 ). They can be formed by a blanket deposition and isotropic etch back. The spacers preferably have a thickness ranging between 1 nm and 5 nm. 
         [0023]    At  108 , impurity ions are implanted into the fin structure to form highly doped source and drain regions and/or lightly doped source and drain extensions using the dummy gate as an implant mask. 
         [0024]    At  109 , a blanket dielectric layer is formed over the dummy gate and the substrate structure. 
         [0025]    Reference numeral  110  represents some embodiments of the replacement gate stage of the RPG process. 
         [0026]    At  110   a,  the blanket dielectric layer is planarized using a chemical mechanical polishing (CMP) process. 
         [0027]    At  110   b,  the dummy gate is removed, thereby forming a gate opening. 
         [0028]    At  110   c,  a strain-inducing layer is deposited in the gate opening covering the channel. In some embodiments, the strain-inducing layer comprises SiGe. 
         [0029]    At  110   d,  an interfacial layer and a high-k dielectric are deposited over the strain-inducing layer or capping layer. 
         [0030]    At  110   e,  metal gate electrode layer is formed in the gate opening. The gate electrode layer is planarized to form a metal gate, stopping on the blanket dielectric layer. 
         [0031]    At  112  metal contacts are formed at the desired positions over the device. In some embodiments contacts are formed at the source and drain regions by patterning the blanket dielectric layer to form contact openings and filling the contact openings with conductive plugs. The conductive plugs are preferably composed of tungsten. A metal layer is formed over the blanket dielectric layer and the conductive plugs and patterned to form device interconnections. 
         [0032]      FIGS. 2 a -2 e    illustrate 3-dimensional (3D) images of some embodiments of the present disclosure and their corresponding cross sections along two perpendicular directions. 
         [0033]      FIG. 2 a    illustrates a 3D view  200   a  of an embodiment of a finFET device comprising a dummy gate over a semiconductor fin. A semiconductor body  200  has a semiconductor fin  202  disposed along a first direction. The semiconductor body  200  comprises alternating zones of active regions (for e.g. silicon) and isolation regions (for e.g. oxide). A dummy gate  204  comprising polysilicon is disposed in a second direction (which is perpendicular to the first direction) over the semiconductor fin  202  at a location that is approximately the midpoint of the fin  202 . In some embodiments a dummy gate oxide layer (not shown) is deposited along the second direction before depositing the dummy gate electrode layer over it. The dummy gate oxide layer can be formed by chemical vapor deposition or more preferably can be thermally grown. The dummy gate oxide layer is preferably formed to a thickness of between about 2 nm and 30 nm.  FIG. 2 a    also shows cross sections along plane AA′ and BB′ of  200   a.    
         [0034]      FIG. 2 b    illustrates a 3D view  200   b  of an embodiment of a finFET device comprising spacers  206   a  and  206   b  on either side of a dummy gate  204  and dopants diffused inside the fin. In some embodiments, the spacers  206   a  and  206   b  are preferably composed of silicon dioxide (SiO 2 ), silicon oxynitride (Si x  O y  N Z ), composite (SiO 2 /Si 3  N 4 ), or most preferably silicon nitride (Si 3  N 4 ). Impurity ions are implanted into the fin structure to form highly doped source region  208   a  and drain region  208   b  and lightly doped source and drain extentions (not shown). In some embodiments for an N-type device, the implanted ions can be As or P. A blanket dielectric layer  207  is formed entirely over substrate structure. Cross sections along plane AA′ and BB′ of  200   b  are also shown. 
         [0035]      FIG. 2 c    illustrates a 3D view  200   c  of an embodiment of a finFET device after a planarizing step. Here, the blanket dielectric layer  207  the dummy gate  204 , and the spacers  206   a  and  206   b  are planarized using a chemical mechanical polishing (CMP) process. Cross sections along plane AA′ and BB′ of  200   c  are also illustrated. 
         [0036]    It is duly specified that from the next image onwards, the blanket dielectric layer  207  is not shown in the 3D images to provide clarity to other features. 
         [0037]      FIG. 2 d    illustrates a 3D view  200   d  of an embodiment of a finFET device wherein the dummy gate  204  has been removed leaving a gate opening. In some embodiments, the dummy gate  204  is removed using a selective etch such as a plasma etch using chlorine as a reactant to etch the polysilicon of the dummy gate electrode  204  selectively to the silicon dioxide of the blanket dielectric layer  207 . The dummy gate oxide (not shown) can be removed in-situ using a CHF 3 /CF 4  etch chemistry, thereby exposing the substrate structure in the gate opening. Cross sections along plane AA′ and BB′ of  200   d  are also shown. 
         [0038]      FIG. 2 e    illustrates a 3D view  200   e  of an embodiment of a finFET device after depositing a strain-inducing layer or cap layer  210  in the gate opening. In some embodiments, the strain-inducing layer comprises SiGe. In this figure, spacer  206   a  is made transparent to get a clear view of the strain inducing layer  210  over the channel. Cross sections along plane AA′ and BB′ of  200   e  are also shown. 
         [0039]      FIG. 2 f    illustrates a 3D view  200   f  of an embodiment of a finFET device after the deposition of a gate stack  212  over the strain inducing layer  210  in the gate opening. In some embodiments, the gate stack  212  comprises an interfacial layer, a high-k dielectric layer and a gate electrode. Here again, spacer  206   a  is made transparent to get a clear view of the gate stack  212  and the strain inducing layer  210 . Also, cross sections along plane AA′ and BB′ of  200   e  are also shown. 
         [0040]    Accordingly, as the strain-inducing layer  210  is deposited after the elevated temperature processes or after removing the dummy gate  204  in the RPG process, better carrier confinement and doping flexibility is achieved. Forming the gate stack  212  comprising the metal gate after the high temperature processes, prevents metal migration. 
         [0041]      FIG. 3  illustrates a flow diagram of some embodiments of a method  300  for forming a strain-inducing layer over a recessed fin of a finFET device. Method  300  corresponds to step  110   b  of method  100  in the RPG stage process flow. 
         [0042]    At  302 , a dummy gate is removed forming a gate opening. 
         [0043]    At  304 , semiconductor fin in the gate region is recessed using isotropic etching. A recessed fin provides effective stress to the fin channel and enhances device performance. In some embodiments, the recess may be etched using suitable etching technology such as dry etching, plasma etching, wet etching, etc. In another embodiment, one or more photolithography processes are used to form masking elements such that the remaining regions of the substrate are protected from the etching process. 
         [0044]    At  306 , a strain inducing layer is formed over the recessed fin in the gate opening. 
         [0045]    At  308 , an interfacial layer (IL) and a high-k dielectric layer (HK) are deposited above the strain inducing or capping layer. 
         [0046]    At  310 , a metal gate (MG) is deposited over the high-k dielectric layer forming a gate electrode. 
         [0047]      FIGS. 4 a  and 4 b    illustrate cross sectional images along two perpendicular planes of a finFET device comprising a strain-inducing layer over a recessed fin. 
         [0048]    It is duly specified that, in all the following cross sectional images, the blanket dielectric layer  207  is not shown for clarity and simplicity. 
         [0049]      FIG. 4 a    illustrates a cross sectional image  400   a  of a finfet device formed according to method  300 . The cross section is along a plane which is parallel to the fin  202  and passes through the center of it (e.g. plane A-A′ in  FIG. 2 f   ). Semiconductor fin  202  is recessed in the gate region making the strain inducing layer  210  reside above and close to channel  209  but below the level of a bottom surface of side wall spacers  206   a  and  206   b.  A gate stack  212  resides above the strain inducing layer  210 . The gate stack comprises an interfacial layer  212   a,  a high-k dielectric layer  212   b  above the interfacial layer  212   a  and a gate metal  212   c  above the high-k dielectric layer  212   c.  In some embodiments spacers  206   a  and  206   b  may be doped or undoped. Doping the spacers would reduce the dielectric constant of gate spacers, and hence reduce the external resistance between the source and the drain regions. In some embodiments, the side wall spacers are subjected to dopants like Boron [B] at a concentration ranging from approximately 1e20 cm −3  to 1e22 cm −3 . The width  213  of the spacers  206   a  and  206   b  range from approximately 1 nm to 5 nm. Within the fin, lightly doped source and drain (LDD) regions  207   a  and  207   b  or highly doped source and drain extensions  208   a  and  208   b  are present. 
         [0050]      FIG. 4 b    illustrates  400   b,  which is a cross sectional image along a plane which is perpendicular to the fin  202  and which passes through the center of the gate stack  212 . The strain inducing layer  210  is seen to reside within the width of the fin  202 . Over the semiconductor body  200 , enveloping the capping layer  210 , resides the gate stack  212  which comprises an interfacial layer  212   a,  a high-k dielectric layer  212   b  and a gate metal  212   c.    
         [0051]      FIG. 5  illustrates a flow diagram of some embodiments of a method  500  comprising forming a pair of spacers after the formation of a strain inducing layer. 
         [0052]    At  502 , a first pair of spacers is formed on either side of a dummy gate. In some embodiments, the spacers are preferably composed of silicon dioxide (SiO 2 ), silicon oxynitride (Si x  O y  N Z ), composite (SiO 2 /Si 3  N 4 ), or most preferably silicon nitride (Si 3  N 4 ). They can be formed by a blanket deposition and isotropic etch back. The spacers preferably have a thickness of between about 1 nm and 5 nm. 
         [0053]    At  504 , the dummy gate is removed. 
         [0054]    At  506 , a strain inducing layer is formed over the fin in the gate opening. 
         [0055]    At  508 , a second pair of spacers is formed over the strain inducing layer vertically above the LDD regions (overlapped by the strain inducing layer) in order to reduce capacitive coupling between the LDD regions and the gate electrode. 
         [0056]    At  510 , an interfacial layer (IL) and a high-k dielectric layer (HK) are deposited above the strain inducing or capping layer. 
         [0057]    At  512 , a metal gate (MG) is deposited over the high-k dielectric layer forming a gate electrode. 
         [0058]      FIGS. 6 a  and 6 b    illustrate cross sectional images along two perpendicular planes of a finFET device comprising a strain inducing layer and second pair of spacers. 
         [0059]      FIG. 6 a    illustrates  600   a,  which is a cross sectional image of a finFET device formed according to method  500 . The cross section is along a plane which is parallel to the fin  202  and passes through the center of it. Semiconductor fin  202  comprises LDD regions  207   a  and  207   b , source region  208   a,  drain region  208   b  and a carrier channel  209  disposed within the fin. Strain inducing layer  210  resides above the channel  209  and part of the LDD regions. A first pair of spacers  206   a  and  206   b  reside on either side of the cap layer above the distal ends of the LDD regions  207   a  and  207   b.  A second pair of spacers  214   a  and  214   b  reside above the strain inducing layer  210  at two end locations vertically above the LDD regions that are overlapped by the strain inducing layer. This is to reduce capacitive coupling between the LDD regions and the gate electrode. A gate stack  212  resides above the strain inducing layer  210  within the second pair of spacers  214   a  and  214   b.  In some embodiments, spacers  206   a,    206   b  are undoped and spacers  214   a  and  214   b  are doped. Doping the spacers would reduce the dielectric constant of gate spacers, and hence reduce the external resistance between the source and the drain regions. In some embodiments, the second pair of spacers  214   a  and  214   b  is subjected to dopants like Boron [B] at a concentration ranging between approximately 1e20 cm −3  to 1e22 cm −3 . The width of the spacers ranges from approximately 1 to 5 nm. 
         [0060]      FIG. 6 b    illustrates  600   b,  which is a cross sectional image along a plane which is perpendicular to the fin  202  and which passes through the center of the gate stack  212 . In this case the strain inducing layer  210  resides outside the width of the fin  202  unlike the recessed fin case. Above the semiconductor body  200 , resides the gate stack  212  which encompasses the strain inducing layer  210  and comprises an interfacial layer, a high-k dielectric layer and a gate metal. 
         [0061]      FIG. 7 a    illustrates an image  700   a,  which is a cross sectional image of a slightly different embodiment. The cross section is along a plane which is parallel to the fin  202  and passes through the center of it. In this embodiment, the device comprises two pairs of spacers similar to that illustrated in  FIG. 6 a   , but they differ by the fact that  700   a  has a recessed fin in the gate region. Hence, the strain inducing layer  210  resides below the level of the bottom surface of all the spacers. The rest of the features are similar to that illustrated in  FIG. 6   a.    
         [0062]      FIG. 7 b    illustrates a cross sectional image  700   b  which is a cross section along a plane perpendicular to the fin  202 . Even though this embodiment illustrates a case with two pairs of spacers and a recessed fin, the cross section along this plane perpendicular to the fin  202 , looks exactly the same as that illustrated in  FIG. 4   b.    
         [0063]      FIG. 8  illustrates a flow diagram of some embodiments of a method  800  comprising tilt implantation in the LDD regions after formation of a strain inducing layer. 
         [0064]    At  802 , the dummy gate is removed leaving a gate opening. This step corresponds to step  110   b  of method  100 . 
         [0065]    At  804 , a strain-inducing layer is formed over the fin in the gate opening. 
         [0066]    At  806 , extra dopants are implanted in the LDD regions using tilt implantation. Thermal processes taking place after formation of the source, drain and LDD regions tend to affect the dopant concentration in those regions, especially the lightly doped source and drain regions. This will affect the coupling between the gate and the channel established by the source and the drain regions or increase the source drain resistance. Tilt implantation in the LDD regions during the RPG stage, after formation of the strain inducing layer will help decrease the source drain resistance or external resistance. Thus, the extra dopants will help enhance device performance. 
         [0067]    At  808 , an interfacial layer (IL) and a high-k dielectric layer (HK) are deposited above the strain inducing or capping layer. 
         [0068]    At  810 , a metal gate (MG) is deposited over the high-k dielectric layer forming a gate electrode. 
         [0069]      FIG. 9  illustrates a cross sectional image  900  of a device formed according to method  800 . The cross section is along a plane which is parallel to the fin  202 . Dopant ions  120  are implanted in a tilted angle directing toward the LDD regions  207   a  and  207   b.  In some embodiments, dopants like boron [B] or difluroboron [BF2] at doses ranging between 1e14-2e15 cm −2  are implanted in the LDD regions. The tilt angle and the energy of the implant ranges between T3-T45 and 0.5 KeV-10 KeV respectively. Source region  208   a,  drain region  208   b  and the carrier channel  209  are disposed within the semiconductor fin  202 . The strain inducing layer  210  resides above the channel  209  in the gate region. Side wall spacers  206   a  and  206   b  resides on either side of the strain inducing layer  210  above the LDD regions  207   a  and  207   b.  The spacers  206   a  and  206   b  may be doped or undoped. 
         [0070]      FIG. 10  illustrates a flow diagram of some embodiments of a method  1000  for forming a dual capping layer comprising a doped strain inducing layer and an undoped strain-inducing layer. 
         [0071]    At  1002 , a first pair of spacers is formed on either side of a dummy gate. 
         [0072]    At  1004 , the dummy gate is removed forming a gate opening. 
         [0073]    At  1006 , a doped strain inducing layer is deposited in the gate opening. In some embodiments, the doped strain inducing layer comprises [B] dopant concentration ranging from 1e18 cm −3 -5e21 cm −3 . The thickness of the doped strain inducing layer ranges from approximately 1 nm-10 nm. The doped strain inducing layer above the LDD regions helps reduce the source drain external resistance. 
         [0074]    At  1008 , a second pair of spacers is formed above the doped strain inducing layer vertically above the LDD regions. 
         [0075]    At  1010 , the doped strain inducing layer is removed from the gate opening. In some embodiments this is done using dry etching or plasma etching. 
         [0076]    At  1012 , an undoped strain inducing layer is deposited in the gate opening. In some embodiments, the thickness of the undoped strain inducing layer ranges from approximately 1 nm-10 nm. 
         [0077]    At  1108 , an interfacial layer (IL) and a high-k dielectric layer (HK) are deposited above the undoped strain inducing layer. 
         [0078]    At  1110 , a metal gate (MG) is deposited over the high-k dielectric layer forming a gate electrode. 
         [0079]      FIG. 11  illustrates an image  1100 , which is a cross section along a plane parallel to the fin of a device, formed according to method  1000 . Doped strain inducing regions  216   a  and  216   b  are seen under the second pair of spacers  214   a  and  214   b.  In this embodiment, both the first and second pairs of spacers are undoped. The rest of the features are the same as that illustrated in  FIG. 6   a.    
         [0080]    It will be appreciated that while reference is made throughout this document to exemplary structures in discussing aspects of methodologies described herein that those methodologies are not to be limited by the corresponding structures presented. Rather, the methodologies (and structures) are to be considered independent of one another and able to stand alone and be practiced without regard to any of the particular aspects depicted in the Figs. Additionally, layers described herein, can be formed in any suitable manner, such as with spin on, sputtering, growth and/or deposition techniques, etc. 
         [0081]    Also, equivalent alterations and/or modifications may occur to those skilled in the art based upon a reading and/or understanding of the specification and annexed drawings. The disclosure herein includes all such modifications and alterations and is generally not intended to be limited thereby. For example, although the figures provided herein, are illustrated and described to have a particular doping type, it will be appreciated that alternative doping types may be utilized as will be appreciated by one of ordinary skill in the art. 
         [0082]    In addition, while a particular feature or aspect may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features and/or aspects of other implementations as may be desired. Furthermore, to the extent that the terms “includes”, “having”, “has”, “with”, and/or variants thereof are used herein such terms are intended to be inclusive in meaning—like “comprising.” Also, “exemplary” is merely meant to mean an example, rather than the best. It is also to be appreciated that features, layers and/or elements depicted herein are illustrated with particular dimensions and/or orientations relative to one another for purposes of simplicity and ease of understanding, and that the actual dimensions and/or orientations may differ substantially from that illustrated herein 
         [0083]    The present disclosure relates to a method of forming a strain inducing layer or cap layer at the RPG stage of a finFET device formation process. This will prevent relaxation of the strain inducing layer because by this stage, the high temperature processes that cause the relaxation would be completed. Different types of doping techniques that helps in reducing the external resistance are also discussed in this disclosure. 
         [0084]    In some embodiments, the present disclosure relates to a method of forming a strain inducing layer overlaying a channel in a finFET (fin field-effect transistor) device, comprising, forming a dummy gate over a channel in a fin of the finFET device, removing the dummy gate during a replacement polysilicon gate (RPG) stage and depositing a strain inducing layer over the channel, after removing the dummy gate. 
         [0085]    In another embodiment, the present disclosure relates to a method of forming a SiGe (silicon germanium) strain inducing layer overlaying a channel in a finFET (fin field-effect transistor) device, comprising, forming a dummy gate comprising silicon dioxide or a polymer, forming a first pair of spacers on either side of the dummy gate, forming source/drain (S/D) and lightly doped drain (LDD) regions within a fin of the finFET device, removing the dummy gate leaving a gate opening, depositing a SiGe strain inducing layer over a channel region within the fin, depositing an interfacial layer and a high-k dielectric layer above the SiGe strain inducing layer; and, depositing a gate metal above the high-k dielectric layer. 
         [0086]    In yet another embodiment, the present disclosure relates to a fin field-effect transistor (finFET) device comprising, a semiconductor fin above a semiconductor substrate, a source and a drain region within the semiconductor fin, lightly doped regions (LDD) within the semiconductor fin, that abuts side walls of the source and the drain regions that face each other, a carrier channel that connects the two LDD regions, a strain inducing layer over a top surface of the carrier channel, one or more pairs of spacers above the LDD regions, and a gate stack abutting a top surface of the strain inducing layer.