Abstract:
A high frequency module is provided with a resistor array layer with interconnections, in which a plurality of resistor elements having a prescribed resistance value are formed as an array, and in which an interconnection pattern for providing electrical connection to each resistor element is formed in advance. Additionally, a capacitor array layer with interconnection in which a plurality of capacitor elements having a prescribed capacitance value are formed as an array and an interconnection pattern for providing electrical connection to each capacitor element is also formed in advance for later use. A desired circuit constant is obtained by providing interconnections among the plurality of resistor elements and among the plurality of capacitor elements, respectively, in any given combination by simply modifying the respective interconnection patterns instead of the entire module. With this configuration, a high frequency module of a more compact and lighter type which facilitates design modification is provided at a low cost.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a high frequency module suitable for a cellular phone and the like. 
     2. Description of the Background Art 
     In a conventional high frequency module, a strip line including a microstrip line is formed using a one-sided substrate, a double-sided substrate, or even a stacked layer substrate according to its purpose, and a resistor, a capacitor, and also a semiconductor component required for the circuitry are mounted on the top layer. 
     One example of a conventional high frequency module is shown in a schematic perspective view of FIG.  8 . The conventional high frequency module has a configuration in which, as shown in FIG. 8 from the bottom, an underside shield layer  105 , a substrate layer  104  in which a strip line for a resonator is formed, a ground layer  103 , a top layer  102  in which a so-called chip component (a resistor, a capacitor, and other semiconductor component) is mounted, and a metal cap shield case  101  are stacked. 
     Due to such a configuration, the size and the thickness of the conventional high frequency module is determined by the shapes of these components. According to market demand, component manufacturers concentrate their efforts on reducing the size and the thickness of these chip components. 
     On the other hand, assembly manufacturers proceed with their circuit design effort by introducing special facilities and a variety of simulators in order to effect high density mounting. Under such circumstances, more compact, thinner, and lighter types of a variety of cellular phones, PDA (Personal Digital Assistants) and the like are needed. In order to meet the need, the miniaturization of the module has become indispensable. 
     For the conventional module, the transition is being made from the chip size of 1608 (1.6 mm×0.8 mm) to the chip size of 1005 (1.0 mm×0.5 mm), and in some cases, even the chip size of 0603 (0.06 mm×0.3 mm) is adopted. The transition from the 1005 size chip to the 0603 size chip would involve an exponentially greater number of problems related to the unit cost of components, mounting, mounting facilities, yield, and so on. 
     The background art, however, is not fully prepared to achieve the compactness, the lightness in weight, and the low cost as demanded by the market as described above. Moreover, once the process technology for the 0603 size chip is established, the novel miniaturization technology to be applied to the process technology must be considered. The above-described background art would prove insufficient for such application to the process technology. 
     SUMMARY OF THE INVENTION 
     The present invention is made to solve the above problem, and its object is to provide a compact, light-weight, low cost high frequency module that facilitates design modification. 
     To achieve the above object, the high frequency module according to the present invention is provided with a first passive element array layer with interconnection including a plurality of first passive elements formed in an array and a first passive element interconnection pattern for providing electrical connection among the plurality of first passive elements, and a second passive element array layer with interconnection including a plurality of second passive elements formed in an array and a second passive element interconnection pattern for providing electrical connection among the plurality of second passive elements. The configuration of the present invention is characterized in that a desired circuit constant can be obtained by providing interconnections among the plurality of first passive elements or among the plurality of second passive elements in any given combination simply by modifying the first or the second passive element interconnection pattern. 
     One of a resistor element, a capacitor element, and an inductor element corresponds to the above first passive element. Similarly, one of a resistor element, a capacitor element, and an inductor element corresponds to the above second passive element. 
     In the high frequency module according to the present invention, the first passive element array layer with interconnection and the second passive element array layer with interconnection, for instance, are formed on different surfaces of the substrate or both on the same surface of the substrate. In either case, the first passive element interconnection pattern and the second passive element interconnection pattern are electrically connected by the interconnection that lies between the first passive element array layer with interconnection and second passive element array layer with interconnection. 
     When the first passive element array layer with interconnection and the second passive element array layer with interconnection are respectively formed on the top surface and the back surface of one substrate, the electrical connection between the first passive element interconnection pattern and the second passive element interconnection pattern is provided by a conductive layer formed in a through hole provided through the substrate. 
     According to the present invention, with the above-described configuration, resistor elements, capacitor elements, or inductor elements may be formed in an array of elements having a prescribed resistance value, capacitance value, or inductance value that is predetermined irrespective of the specific use to which the high frequency module is applied, and the circuit constant required for a desired use can be obtained by combining these elements by the modification of the interconnection pattern alone. Such a high module can be applied to a wide variety of uses so that it can be designed as a standard high frequency module that meets a variety of demands. This results in mass production that achieves a significant reduction in the production cost. 
     In addition, upon design modification, only the modification of the interconnection pattern of each array layer is required besides the modification of the circuit design so that the development time as well as the development cost can be reduced. 
     The formation of a resistor array, a capacitor array, or an inductor array as a passive element array for the high frequency module according to the present invention using such techniques as printing, evaporation, photo etching, and selective plating improves precision, so that a module having a desired performance characteristic can be formed, which is industrially significant. 
     Moreover, since a passive element in the form of a chip component is not used, there no longer is the need to handle an extremely small chip component such as the conventional 0603 size chip. Thus, expensive equipments such as a mounter become unnecessary. 
     Furthermore, according to the present invention, a great number of passive components can be built inside by forming them on a main surface of a substrate layer to be stacked so that only the semiconductor components that are the active components need to be mounted, on the top layer in an upper portion of the stacked body, for instance. This can be sufficiently managed by the conventional facilities. 
     In one preferred example of the high frequency module according to the present invention, at least one of a strip line and an active electronic component is arranged above or below, or both above and below the first passive element array layer with interconnection. 
     The high frequency module according to the present invention can be configured such that all of either the plurality of first passive elements or the plurality of second passive elements have the same resistance value, capacitance value, or inductance value. In addition, either the plurality of first passive elements or the plurality of second passive elements may be divided into a plurality of groups, and all the passive elements forming each group may be set with the same resistance value, capacitance value, or inductance value. 
     The above-described configuration becomes possible since a desired circuit constant can be obtained by providing interconnections among the plurality of first passive elements or among the plurality of second passive elements in any given combination by simply modifying only the first or second passive element interconnection pattern. 
     The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A-1D is a cross sectional view of a main portion showing a schematic structure of a high frequency module according to an embodiment of the present invention. 
     FIG. 2 is a schematic perspective view showing the concept of the high frequency module according to the embodiment of the present invention. 
     FIGS. 3A to  3 C are diagrams showing a structure produced in advance and stored for later use in a stage prior to forming the specific circuit of Example 1, with FIG. 3A showing a plan view, FIG. 3B showing a cross sectional view taken along the line IIIB—IIIB of FIG. 3A, and FIG. 3C showing a bottom plan view, respectively. 
     FIGS. 4A to  4 C are diagrams representing the structure after forming the specific circuit of Example 1, with FIG. 4A showing a plan view, FIG. 4B showing a cross sectional view taken along the line IVB—IVB of FIG. 4A, and FIG. 4C showing a bottom plan view, respectively. 
     FIG. 5 is a cross sectional view showing the structure in which the circuit of example 1 shown in FIGS. 4A to  4 C are arranged in three rows in the lateral direction. 
     FIGS. 6A and 6B are diagrams showing a structure produced in advance and stored for later use in a stage prior to forming a specific circuit of Example 2. 
     FIG. 7A is a layout plan view showing the structure after forming the specific circuit of example 2, and 
     FIG. 7B is an equivalent circuit diagram of the same. 
     FIG. 8 is a perspective view of a main portion showing a schematic structure of a conventional high frequency module. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The embodiment of the present invention will be described below in relation to the drawings. 
     FIGS. 1A to  1 D are cross sectional views of the main portion showing the schematic structure of a high frequency module of the present embodiment in which four substrate layers are stacked, where each substrate layer is shown in isolation so as to indicate the boundaries between the substrate layers more clearly. The high frequency module is formed in stacked layers, from the top, of a first substrate layer  1  as a top substrate layer (FIG.  1 A), a second substrate layer  2  (FIG.  1 B), a third substrate layer  3  (FIG.  1 C), and a fourth substrate layer  4  (FIG.  1 D). Of these substrate layers, the third substrate layer  3  shown in FIG. 1C characterizes the present embodiment. Therefore, the description of third substrate layer  3  will be provided first. 
     In third substrate layer  3 , a capacitor array layer with interconnection  3   a  including a capacitor element  31  arranged in an array and interconnection pattern layers  32   a  and  32   b  is formed on an upper surface of an insulating substrate  30  of third substrate layer  3 . In addition, a resistor array layer with interconnection  3   c  including a resistor film  34  arranged in an array and an interconnection pattern  35  is formed on an underside of insulating substrate  30 . Moreover, a via hole  36  is formed in insulating substrate  30 , and resistor array layer with interconnection  3   c  and capacitor array layer with interconnection  3   a  are electrically connected via a conductor embedded in via hole  36 . Therefore, insulating substrate  30  corresponds to an interconnection layer  3   b.    
     In capacitor array layer with interconnection  3   a  on the upper surface of insulating substrate  30 , interconnection patterns  32   a  and  32   b  including an electrode and an interconnection formed by a conductive material such as Al and Cu are formed such that interconnection patterns  32   a  and  32   b  sandwich a TaO 2  (tantalum oxide) thin film  31   a  that is to form a dielectric film for a capacitor  31 , thereby forming capacitor element  31 . An insulating film  33  formed of a resin material or the like is provided on interconnection patterns  32   a  and  32   b  except for a portion (contact portion) that is electrically connected to second substrate layer  2  arranged above. 
     In addition, in resistor array layer with interconnection  3   c  below insulating substrate  30 , an interconnection pattern  35  including an electrode and an interconnection formed by a conductive material such as Al and Cu is formed such that resistor film  34  formed of a resistance material such as W is surrounded from both sides in the horizontal direction of the diagram by interconnection pattern  35 . 
     A portion of interconnection patterns  32   a  and  32   b  of capacitor array layer with interconnection  3   a  and a portion of interconnection pattern  35  of resistor array layer with interconnection  3   c  are electrically connected by via hole  36  formed within insulating substrate  30  so that insulating substrate  30  functions as interconnection layer  3   b.    
     Although only a single capacitor element and a single resistor element are shown in FIG. 1C, in practice, they are provided in plurality and formed in arrays. 
     The present embodiment being thus configured, for capacitor array layer with interconnection  3   a  a capacitance value as a constant required for the circuit can be obtained from a combination of these capacitor elements that is created by selectively providing interconnection lines to capacitor elements according to the desired circuit design by patterning interconnection pattern  32 . 
     Moreover, for resistor array layer with interconnection  3   c , a resistance value as a constant required for the circuit can be obtained from a combination of these resistance elements that is created by selectively providing interconnections to the resistance elements according to the desired circuit design by patterning interconnection pattern  35 . 
     Second substrate layer  2  is stacked on third substrate layer  3 . Second substrate layer  2  has a ground conduction layer  23  and a connecting terminal  24  for connection with third substrate layer  3  both formed under an insulating substrate  20 . Connecting terminal  24  is electrically connected to a portion of interconnection pattern  32  of capacitor array layer with interconnection  3   a  of third substrate layer  3  in a region where insulating film  33  is not formed. 
     On insulating substrate  20 , a connecting terminal  21  that is electrically connected to connecting terminal  24  via a through hole  22  formed within insulating substrate  20  and that provides electrical connection with first substrate layer  1  is formed. 
     First substrate layer  1  (top substrate layer) is stacked on second substrate layer  2 . First substrate layer  1  has a strip line  14  and a connecting terminal  15  for connection with second substrate layer  2  both formed under an insulating substrate  10 . Connecting terminal  15  is electrically connected to connecting terminal  21  of second substrate layer  2 . 
     Active electronic components  11  and an interconnection pattern  12  for active electronic components  11  are formed above insulating substrate  10 . A portion of interconnection pattern  12  is electrically connected to connecting terminal  15  via a through hole  13  formed within insulating substrate  10 . 
     Moreover, fourth substrate layer  4  is stacked below the above-described third substrate layer  3 . In fourth substrate layer  4 , a connecting terminal  41  electrically connected to a portion of interconnection pattern  35  of resistor array layer with interconnection  3   c  of third substrate layer  3  is formed above an insulating substrate  40 . 
     A ground plane  43  and a connecting terminal  44  electrically connected to connecting terminal  41  via a through hole  42  formed within insulating substrate  40  are formed below insulating substrate  40 . 
     Interconnection patterns, connecting terminals and connecting portions, through holes, via holes, etc. in FIGS. 1A-1D are shown to represent the concept and in no way limit the present invention. Interconnection lines and the like are provided as required. 
     Now, the high frequency module according to the present embodiment will be described in relation to FIG. 2 which is a schematic representation showing the concept of this high frequency module. 
     Resistor array  56  is a plurality of resistor elements arranged in an array, and an interconnection pattern for resistors  55  is an interconnection pattern for this resistor array  56 . Resistor array  56  and interconnection pattern for resistors  55  correspond to resistor array layer with interconnection  3  of third substrate layer  3  of FIG.  1 C. Capacitor array  54  is a plurality of capacitor elements arranged in an array, and interconnection patterns  53   a  and  53   b  are interconnection patterns for capacitor array  54 . Capacitor array  54  and interconnection patterns for capacitors  53   a  and  53   b  correspond to capacitor array layer with interconnection in FIG.  1 C. In FIG. 2, for clarity, interconnection patterns  55 ,  53   a , and  53   b  are shown as layers separate from capacitor array  54  and resistor array  56 . An interconnection layer  58  corresponding to interconnection layer  3   b  shown in FIG. 1C resides between interconnection pattern for capacitor array  53   a  and interconnection pattern for resistor ray  55 . 
     According to the present embodiment thus configured, for instance, resistor array  56  and capacitor array  54  respectively formed by resistor elements and capacitor elements can be the arrays of elements having a constant resistance value and a constant capacitance value, respectively, and a constant required for the circuit can be obtained from a combination of these elements. A module for specific use normally can be provided by changing the circuit constant so that a variety of needs can be met by simply modifying interconnection patterns  55 ,  53   a , and  53   b.    
     On interconnection pattern for capacitors  53   b , a strip line  52  (corresponding to strip line  14  of first substrate  1  in FIG. 1A) is arranged, and thereon an upper surface shield substrate  51  (not shown in FIG. 1A) is provided. An underside shield layer  57  (corresponding to ground plane  43  of the fourth substrate layer  4  in FIG. 1D) is arranged under resistor array  56 . 
     Moreover, in the above-described present embodiment, either the capacitance values of the plurality of capacitor elements forming capacitor array layer with interconnection  3   a  in FIG. 1C or forming capacitor array  54  in FIG. 2, or the resistance values of the plurality of resistor elements forming resistor array layer with interconnection  3   c  in FIG. 1C or forming resistor array  56  in FIG. 2 may be all set to the same value. In addition, if required by the design, the plurality of capacitor elements or the plurality of resistor elements forming an array may be divided into some groups, each group being set with a different capacitance value or a different resistance value. Thus, even when the constant of an element (a capacitance value, a resistance value, inductance and the like) is already set, it may be adjusted to the constant required for the designed circuit, basically by simply selecting the interconnection patterns. 
     In the above present embodiment, capacitor array layer with interconnection  3   a  and resistor array layer with interconnection  3   c  are formed on either side of one insulating substrate  30  as in third substrate layer  3  of FIG.  1 C. According to the desired circuit scale, however, these arrays can be formed on one side of the substrate. In this case, a resistor array, a capacitor array, and their interconnection patterns should be formed within the same surface, and then, interconnections should be provided. This is effective when the circuit scale does not require such a high degree of integration of the resistor array and the capacitor array, and here, the number of stacked layers can be reduced. 
     Further, although the description of the present embodiment is given above with respect to the selectivity provided by the interconnection pattern of capacitor elements or the resistor elements, the approach of selectively providing interconnections to inductors formed by strip line  14  of first substrate layer  1  in FIG. 1A or by strip line  52  in FIG. 2 as a circuit element is also conceivable as a matter of course. 
     Furthermore, as a method of forming the capacitor array or the resistor array of the present embodiment, the lithography technique, the vacuum evaporation technique, and a technique such as one of forming a thicker interconnection layer by plating that are frequently utilized in the IC (Integrated Circuit) field as well as the printing technique employed in the hybrid IC technology are utilized. 
     In comparison with the conventional high frequency module shown in FIG. 8 that involves mounting of chip components, the high frequency module of the present embodiment can be made extremely thin such that the chip height is in the order of the film thickness. 
     In addition, since the precision of the interconnections at masking level and the dimensional precision of a capacitor or a resistor are improved, a characteristic closer to the design value can be achieved, while at the same time, a more compact module can be produced. Moreover, the high frequency module according to the present embodiment can be formed using a process employed for an IC so that it is fit for mass production and can easily accommodate modification with minor changes such as the change of interconnection masks. 
     As seen from the above, according to the present invention, the high frequency module of a thinner and more compact type can be produced, and the reduction in facilities and even in the development time can be easily achieved. 
     Now, two examples of third substrate layer  3  of the present embodiment, one example involving the versatile structure that can be produced in advance and stored for later use and another example involving the structure after having modified the interconnection pattern to form the desired specific circuit, will be described below based on FIGS. 3A to  7 B. 
     EXAMPLE 1 
     First, as example 1, the structure in which, in application of the concept of the present invention, a capacitor array  31  and interconnection patterns for capacitors  32   a  and  32   b  are formed on insulating substrate  30  while a resistor array  34  and an interconnection pattern for resistors  35  are formed under insulating substrate  30  will be described in relation to FIGS. 3A to  5 . 
     FIGS. 3A to  3 C illustrate the structure that can be produced in advance and stored for later use in a stage prior to forming a specific circuit of the present example. In this state, a TaO 2  thin film  31   a  that is to form a dielectric film of capacitor array  31  and, of the two interconnection patterns  32   a  and  32   b  formed sandwiching TaO 2  thin film  31   a  in the vertical direction of the diagram, only interconnection pattern  32   a  that is closer to the lower layer is formed on insulating substrate  30 . In addition, only a resistor film  34   a  forming resistor array  34  is formed on the underside of insulating substrate  30 . 
     Upon the structure thus prepared in advance, an interconnection pattern  32   b  corresponding to the desired circuit is formed (see FIGS. 4A and 4B) on an upper surface of insulating substrate  30  from the top surface of TaO 2  thin film  31   a  across to via hole  36 , and an interconnection pattern  35  corresponding to the desired circuit is formed on the underside of insulating substrate  30  such that interconnection pattern  35  surrounds resistor film  34   a  from both sides in the horizontal direction, whereby the structure shown in FIGS. 4A to  4 C is obtained. 
     The structure shown in FIGS. 4A to  4 C is only a part of the circuit that is formed. In practice, a circuit is formed in which a plurality of such structures are formed lengthwise and crosswise when seen from above and which has a cross sectional structure as the one shown in FIG. 5, for instance. 
     EXAMPLE 2 
     Now, as example 2, the structure in which, in application of the concept of the present invention, capacitor array  31  and interconnection patterns for capacitors  32   a  and  32   b , and resistor array  34  and interconnection pattern for resistors  35  are both formed on an upper surface of insulating substrate  30  will be described in relation to FIGS. 6A to  7 B. 
     FIGS. 6A and 6B represent the structure that can be produced in advance and stored for later use in a stage prior to forming the specific circuit of the present example. In this state, TaO 2  thin film  31   a  that is to form a dielectric film of capacitor array  31  is formed on an upper surface of insulating substrate  30 , and interconnection patterns  32   a  and  32   b  are formed over and only in the vicinity of TaO 2  thin film  31   a  such that they sandwich TaO 2  thin film  31   a  in the vertical direction of the diagram. Moreover, in the present example, resistor film  34   a  forming resistor array  34  and interconnection pattern  35 , which is formed only in the vicinity of each resistor film  34   a  such that interconnection pattern  35  surrounds resistor film  34   a  from both sides in the horizontal direction, are formed on the upper surface of the insulating substrate. In addition, a conductive film  37  is formed on the inner peripheral surface of a via hole provided through insulating substrate  30  and on both the upper surface and the underside of the insulating substrate in the vicinity of the via hole. 
     To the structure thus prepared in advance, an interconnection pattern  38  corresponding to the desired circuit is additionally provided on an upper surface of insulating substrate  30  such that particular ones of interconnection patterns  32   a ,  32   b ,  35 , and  37  are electrically connected, whereby the structure shown in FIGS. 7A and 7B is obtained. 
     Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.