Abstract:
A video imaging apparatus includes a cathode-ray tube including a focus electrode. A source of a first parabolic signal at a frequency related to a deflection frequency, selected from a plurality of frequencies, has an amplitude determined in accordance with the selected frequency. A control circuit has an input coupled to the source of the first parabolic signal for generating an output signal. The output signal is for maintaining the amplitude of the first parabolic signal for the plurality of deflection frequencies. An amplifier, that is responsive to the output signal, is coupled to the focus electrode for amplifying the parabolic signal to generate a dynamic focus voltage at the focus electrode.

Description:
The invention relates to a beam landing distortion correction arrangement. 
     BACKGROUND 
     An image displayed on a cathode ray tube (CRT) may suffer from imperfections or distortions such as defocusing or nonlinearity that is incident to the scanning of the beam on the CRT. Such imperfections or distortions occur because the distance from the electron gun of the CRT to the faceplate varies markedly as the beam is deflected, for example, in the horizontal direction. Reducing the defocusing that occurs as the beam is deflected in the horizontal direction, for example, may be obtained by developing a dynamic focus voltage having a parabolic voltage component at the horizontal rate and applying the dynamic focus voltage to a focus electrode of the CRT for dynamically varying the focus voltage. It is known to derive the parabolic voltage component at the horizontal rate from an S-correction voltage developed in an S-shaping capacitor of a horizontal deflection output stage. 
     A television receiver, computer or monitor may have the capability of selectively displaying picture information in the same CRT using a deflection current at different horizontal scan frequencies. When displaying the picture information of a television signal defined according to a broadcasting standard, it may be more economical to utilize a horizontal deflection current at a rate of approximately 16 KHz, referred to as the 1f H  rate. Whereas, when displaying the picture information of a high definition television signal or a display monitor data signal, the rate of the horizontal deflection current may be equal to or greater than 32 KHz. The higher rate is referred to as 2nF h . The value n is equal to or greater than 1. 
     In the horizontal deflection circuit output stage of a video display monitor capable of operating at multi-scan rates, it is known to vary the number of in-circuit S-capacitors using switched S-capacitors. The selection of the S-capacitors is made automatically via selectable switches, in accordance with the selected horizontal deflection frequency. 
     When a non-switched retrace capacitor is employed, the length of the horizontal retrace interval is the same at different horizontal frequencies. As a result, the required amplitudes of the S-correction voltage at the different frequencies may be different. In a dynamic focus system, it is desirable to maintain the horizontal parabola amplitude constant during the vertical period. It is also desirable to keep the horizontal parabola amplitude constant as the horizontal frequency changes with the scan mode. 
     In carrying out an inventive feature, a parabolic horizontal rate voltage is developed in the S-shaping capacitor. The parabolic voltage is attenuated through a controlled variable voltage divider. The output of the voltage divider is coupled to an input of a differential amplifier that compares and adjusts the peak-to-peak amplitude of the parabolic voltage to be equal to a voltage reference. The horizontal parabola amplitude is kept constant during the vertical period by comparing the peak to peak amplitude of the parabola to the reference voltage and then the parabola amplitude is adjusted to be equal to the reference via a feedback amplifier and controlled attenuator. 
     In carrying out an inventive feature, a gain control loop removes unwanted low frequency pin correction modulation from the input voltage from the S capacitor. This modulation, if not removed, can disadvantageously make the horizontal dynamic focus correction too large at the center of the picture. By compensating via the gain control loop, phase error is not introduced. 
     A further inventive feature is that the high frequency roll off of the focus high voltage amplifier is compensated. The parabola is passed through a low pass filter with roll off similar to the amplifier. The parabola thus attenuated is set equal to the reference. The parabola signal that drives the amplifier is taken ahead of the filter. This signal is boosted at the high frequencies properly to provide a constant amplitude at the amplifier output. 
     A video imaging apparatus, embodying an inventive feature, includes a cathode-ray tube including a focus electrode. A source of a first parabolic signal at a frequency related to a deflection frequency, selected from a plurality of frequencies, has an amplitude determined in accordance with the selected frequency. A control circuit has an input coupled to the source of the first parabolic signal for generating an output signal. The output signal is for maintaining the amplitude of the first parabolic signal for the plurality of deflection frequencies. An amplifier, that is responsive to the output signal, is coupled to the focus electrode for amplifying the parabolic signal to generate a dynamic focus voltage at the focus electrode. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A illustrates a horizontal deflection circuit output stage. 
     FIG. 1B illustrates an automatic gain circuit for controlling a horizontal parabola amplitude in accordance with an inventive feature. 
     FIG. 1C illustrates a focus high voltage amplifier. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1A illustrates a horizontal deflection circuit output stage  101  of a television receiver having multi-scan frequency capability. Stage  101  is energized by a regulated power supply  100  that generates a supply voltage B+. A conventional driver stage  103  is responsive to an input signal  107   a  at the selected horizontal scanning frequency nf h . Driver stage  103  generates a drive control signal  103   a  to control the switching operation in a switching transistor  104  of output stage  101 . By way of example, a value of n=1 may represent the horizontal frequency of a television signal according to a given standard such as a broadcasting standard. The collector of transistor  104  is coupled to a terminal T 0 A of a primary winding T 0 W 1  of a flyback transformer T 0 . The collector of transistor  104  is also coupled to a non-switched retrace capacitor  105 . The collector of transistor  104  is additionally coupled to a horizontal deflection winding LY to form a retrace resonant circuit. The collector of transistor  104  is also coupled to a conventional damper diode  108 . Winding LY is coupled in series with a linearity inductor LIN and a non-switched trace or S-capacitor CS 1 . Capacitor CS 1  is coupled between a terminal  25  and a reference potential, or ground GND such that terminal  25  is interposed between inductor LIN and S-capacitor CS 1 . 
     Output stage  101  is capable of producing a deflection current iy. Deflection current iy has substantially the same predetermined amplitude for any selected horizontal scan frequency of signal  103   a  selected from a range of 2f h  to 2.4f h  and for a selected horizontal frequency of 1f h . Controlling the amplitude of deflection current iy is accomplished by automatically increasing voltage B+ when the horizontal frequency increases, and vice versa, so as to maintain constant amplitude of deflection current iy. Voltage B+ is controlled by a conventional regulated power supply  100  operating in a closed-loop configuration via a feedback winding T 0 W 0  of transformer T 0 . The magnitude of voltage B+ is established, in accordance with a rectified, feedback flyback pulse signal FB having a magnitude that is indicative of the amplitude of current iy. A vertical rate parabola signal E-W is generated in a conventional way, not shown. Signal E-W is conventionally coupled to power supply  100  for producing a vertical rate parabola component of voltage B+ to provide for East-West distortion correction. 
     A switching circuit  60  is used for correcting a beam landing error such as linearity. Circuit  60  selectively couples none, only one or both of a trace or S-capacitor CS 2  and a trace or S-capacitor CS 3  in parallel with trace capacitor CS 1 . The selective coupling is determined as a function of the range of frequencies from which the horizontal scan frequency is selected. In switching circuit  60 , capacitor CS 2  is coupled between terminal  25  and a drain electrode of a field effect transistor (FET) switch Q 2 . A source electrode of transistor Q 2  is coupled to ground GND. A protection resistor R 2  that prevents excessive voltage across transistor Q 2  is coupled across transistor Q 2 . 
     A register  201  applies switch control signals  60   a  and  60   b . Control signal  60   a  is coupled via a buffer  98  to a gate electrode of transistor Q 2 . When control signal  60   a  is at a first selectable level, transistor Q 2  is turned off. On the other hand, when control signal  60   a  is at a second selectable level, transistor Q 2  is turned on. Buffer  98  provides the required level shifting of signal  60   a  to accomplish the above mentioned switching operation, in a conventional manner. 
     In switching circuit  60 , capacitor CS 3  is coupled between terminal  25  and a drain electrode of a FET switch Q 2 ′. FET switch Q 2 ′ is controlled by control signal  60   b  in a similar way that FET switch Q 2  is controlled by control signal  60   a . Thus, a buffer  98 ′ performs a similar function as buffer  98 . 
     A microprocessor  208  is responsive to a data signal  209   a  generated in a frequency-to-data signal converter  209 . Signal  209   b  has a numerical value that is indicative of the frequency of a synchronizing signal HORZ-SYNC or deflection current iy. Converter  209  includes, for example, a counter that counts the number of clock pulses, during a given period of signal HORZ-SYNC and generates word signal  209   b  in accordance with the number of clock pulses that occur in the given period. Microprocessor  208  generates a control data signal  208   a  that is coupled to an input of register  201 . The value of signal  208   a  is determined in accordance with the horizontal rate of signal HORZ-SYNC. Register  201  generates, in accordance with data signal  208   a , control signals  60   a  and  60   b  at levels determined by signal  208   a , in accordance with the frequency of signal HORZ-SYNC. Alternatively, the value of signal  208   a  may be determined by a signal  109   b  that is provided by a keyboard, not shown. 
     When the frequency of horizontal deflection current iy is  1 f H , transistors Q 2  and Q 2 ′ are turned on. The result is that both S-capacitors CS 2  and CS 3  are in-circuit S-capacitors that are coupled in parallel with non-switched S-capacitor CS 1  and establish a maximum S-capacitance value. When the frequency of horizontal deflection current iy is equal to or greater than 2 f h  and less than 2.14 f h , transistor Q 2  is turned off and transistor Q 2 ′ is turned on. The result is that S-capacitor CS 2  is decoupled from non-switched S-capacitor CS 1  and S-capacitor CS 3  is coupled to S-capacitor CS 1  to establish an intermediate S-capacitance value. When the frequency of horizontal deflection current iy is equal to or greater than 2.14 f h , transistors Q 2  and Q 2 ′ are turned off. The result is that S-capacitors CS 2  and CS 3  are decoupled from non-switched S-capacitor CS 1  and establish a minimum S-capacitance value. Deflection current iy in capacitor CS 1 , CS 2  or CS 3  produces an S-shaping parabolic voltage V 5 . 
     The total retrace capacitance formed by capacitor  105  does not change at the different scan frequencies. Therefore, the retrace interval has the same length at the different scan frequencies. The values of capacitors CS 1 , CS 2  and CS 3  are selected to produce parabolic voltage V 5  at different amplitudes at different scan frequencies. The different amplitudes of voltage V 5  are required because the retrace interval length is constant. 
     FIG. 1B illustrates an automatic gain circuit for controlling the horizontal parabola amplitude, embodying an inventive feature. Similar symbols and numerals in FIGS. 1A and 1B indicates similar items or functions. Voltage V 5  of FIG. 1A has negative going retrace peaks. The peak to peak amplitude of parabolic voltage V 5  is about 60 V at 16 KHz or 1f h , 80 V at 2f h  and 125 V at 2.4f h . Parabola voltage V 5  is capacitively coupled via a capacitor C 4  to a resistor R 16 . 
     FIG. 1B shows the automatic gain circuit that controls the horizontal parabola amplitude, in accordance with an inventive feature. S-shaping parabolic voltage V 5  is AC coupled through capacitor C 4  and clamped at its negative peak to 12 volts by diode D 6 . At the cathode of diode D 6 , the parabola voltage is always positive with respect to 11.4 volts. Transistor Q 11  has a constant 11.4 volts at its base and a constant 12 volt at its emitter. 
     The positive parabola voltage across resistor R 16  provides a proportional parabola current to the emitters of Q  11  and Q 12 . Assuming transistor Q 12  is not conducting, then this current passes through transistor Q 11  and produces a voltage across resistor R 4 . This voltage is then buffered by emitter follower Q 50  and appears at the output OUT. 
     The output voltage is also coupled through a low pass filter consisting of resistor R 55  and capacitor C 54 . The values of resistor R 55  and capacitor C 54  are selected so that the low pass filtered voltage across capacitor C 54  proportionally tracks the low pass response inherent in the focus high voltage amplifier (FHVA)  97  that is connected to output OUT. 
     The voltage across capacitor C 54  is AC coupled through capacitor C 53  and then negative peak clamped to ground by diode D 53 . 
     The differential amplifier pair consisting of transistors Q 53  and Q 54  acts as a voltage comparator that conducts current through transistor Q 53  only when the base voltage of transistor Q 53  exceeds the base voltage of Q 54  which is a constant reference voltage of 3 volts. Current flow through transistor Q 53  charges capacitor C 52  until transistor Q 12  conducts. Transistor Q 12  then conducts a percentage of the parabola current flowing into node A to ground. The same percentage of the current into node A is conducted through transistor Q 12  for all amplitudes of this current, therefore, the current in transistor Q 11  is linearly reduced in magnitude. 
     The voltage across resistor R 4  is reduced in amplitude without distortion of its parabola shape. As outlined above, a processed replica of the reduced voltage across resistor R 4  also appears at the base of transistor Q 53 . This completes a voltage amplitude maintaining feedback loop. When this voltage at the base of transistor Q 53  is reduced in amplitude sufficiently that transistor Q 53  only conducts minimally to maintain a balance in the feedback loop, the amplitude of the voltage at the base of transistor Q 53  will be only slightly greater than 3 volts and will be maintained nearly constant by the gain in the feedback loop. 
     The low pass filter consisting of resistor R 55  and capacitor C 54  is part of the loop. It will cause parabolas of higher frequencies such as those at 31 KHz or 38 KHz to be attenuated at the transistor Q 53  base and amplified at the output OUT in such a manner that the high frequency attenuation inherent in amplifier FHVA  97  is compensated and a constant output from amplifier FHVA  97  is achieved for parabolas in all the different scan modes from 15 KHz to 38 Khz. 
     As shown in FIG. 1C, capacitor C 23  provides capacitive coupling for the horizontal parabola to the Focus High Voltage Amplifier  97 . A capacitor C 10  capacitively couples a vertical parabola V 8 , produced in a conventional manner, not shown, to terminal  121 . The direct current operating point of focus amplifier  97  is determined by a resistor R 5  and not by the parabolic signals, because the capacitive coupling eliminates a direct current component. Capacitor C 24  corrects a phase delay caused by a stray input capacitance, not shown, of amplifier  97  so that the horizontal focus correction is properly timed. 
     Referring to FIG. 1C, in amplifier  97 , a transistor Q 5  and a transistor Q 6  are coupled to each other to form a differential input stage. These transistors have very high collector current-to-base current ratio, referred to as beta, to increase the input impedance at terminal  121 . The base-emitter junction voltages of transistors Q 5  and Q 6  compensate each other and reduce direct current bias drift with temperature changes. Resistor R 11  and resistor R 12  form a voltage divider that is applied to a supply voltage V10 at +12 V for biasing the base voltage of transistor Q 6  at about +3 V. The value of an emitter resistor R 10  that is coupled to the emitters of transistors Q 5  and Q 6  is selected to conduct a maximum current of about 6 mA. This protects a high voltage transistor Q 20 . Transistor Q 20  is coupled to transistor Q 5  in a cascode configuration. Transistor Q 20  needs to be protected from being over-driven because transistor Q 20  can tolerate only up to 10 mA collector current. This is accomplished because amplifier  97  has high transconductance at a collector current of up to 6 mA and lower transconductance above 6 mA. The cascode configuration of transistors Q 20  and Q 5  isolates the Miller capacitance, not shown, across the collector-base junction of transistor Q 20 , thereby the bandwidth is increased. The cascode configuration also makes the amplifier gain independent of the low beta of high voltage transistor Q 20 . 
     A winding T 0 W 3  of transformer T 0  of FIG. 1A produces a stepped-up retrace voltage that is rectified in a diode D 12  and filtered in a capacitor C 13  to produce a supply voltage VSU for energizing dynamic focus voltage generator  99  of FIG.  1 B. An active pull up transistor Q 1  has a collector coupled to supply voltage VSU. A base pull-up resistor R 1  of transistor Q 1  is coupled to voltage VSU via a bootstrap or boosting arrangement that includes a diode D 7  and a capacitor C 26 . A diode D 5  is coupled in series with resistor R 1  and is coupled to the collector of transistor Q 20 . A diode D 4  is coupled between the emitter of transistor Q 1  at terminal  97   a  and the collector of transistor Q 20 . 
     During the negative peaks of the output waveform at terminal  97   a , diode D 7  clamps an end terminal of capacitor C 26  at the cathode of diode D 7  to the+1600 V supply voltage VSU and transistor Q 20  pulls the other end terminal of capacitor C 16  to near ground potential. Transistor Q 1  is held off by the actions of diodes D 4  and D 5 . As the voltage at terminal  97   a  rises, the energy stored in capacitor C 26  is fed through resistor R 1  to the base of transistor Q 1 . The voltage across resistor R 1  is maintained high, and base current in transistor Q 1  also is maintained, even as the collector-to-emitter voltage across transistor Q 1  approaches zero. Therefore, transistor Q 1  emitter current is maintained. The output positive peak at terminal  97   a  can then be very near the +1600 V supply voltage VSU without distortion. 
     A capacitance C 1  represents the sum of the stray capacitance of focus electrode  17  and of the wiring. Active pull-up transistor Q 1  is capable of sourcing a current from terminal  97   a  to charge stray capacitance C 1 . Pull-down transistor Q 20  is capable of sinking current via diode D 4  from capacitance C 1 . Advantageously, the active pull up arrangement is used to obtain fast response time with lowered power dissipation. Amplifier  97  uses shunt feedback for the output at terminal  97   a  via a feedback resistor R 2 . Resistors R 17  and R 2  are selected to produce 1000 V peak to peak horizontal rate voltage at terminal  97   a . As a result, the voltage gain of amplifier  97  is several hundred. 
     Dynamic focus voltage components at the horizontal rate produced by voltage V 5  and at the vertical rate produced by voltage V 8  are capacitively coupled via a direct current blocking capacitor C 22  to a focus electrode  17  of a CRT  10  to develop a dynamic focus voltage FV. A direct current voltage component of voltage FV, developed by a voltage divider formed by a resistor R 28  and a resistor R 29 , is equal to 8 KV.