Abstract:
A hypersensitive semiconductor die structure is disclosed, in which flip-chip packaging is used in conjunction with a modified SOI die in which a thick silicon support substrate has been removed to increase sensitivity of the sensing device. Rather than being located beneath layers of interconnects and dielectric, the disclosed structure places the sensing devices close to the surface, more closely exposed to the environment in which sensing is to occur. The structure also allows for the placement of sensing films on nearer to the sensing devices and/or an oxide layer overlying the sensing devices.

Description:
RELATED APPLICATION 
       [0001]    This application claims priority to U.S. Provisional Application No. 60/980,346, “SOI On Package Hypersensitive Intrusion Amplifier,” the entirety of which is incorporated by reference herein. 
     
    
     FIELD OF THE INVENTION 
       [0002]    This invention relates to an SOI flip-chip interconnected semiconductor structure that enhances sensitivity for sensor applications and allows for the placement of additional circuit patterns at very close proximity to the semiconductor elements without disturbing interconnectivity with the chip package. 
       BACKGROUND OF INVENTION 
       [0003]    Batch wafer semiconductor process technologies have been heavily exploited not only to produce large scale integrated circuits, but a vast assortment of sensors and actuators as well. These include chemical sensors, photo detectors, radiation sensors, pressure transducers, temperature sensors, accelerometers, magnetic sensors, micro capillaries, micro mechanical devices, and many others. As semiconductor technologies advance and include increasing numbers of elements in a single “chip”, increasing numbers of layers of interconnect and their associated isolation dielectrics and passivation have become more common. In 150 nm generation technologies, 6-8 layers of copper, aluminum, or tungsten interconnect separated by low-capacitance dielectrics are not uncommon. 
         [0004]      FIG. 1  is a cross-sectional view of such technology  100 , showing a thick support silicon  102 , a plurality of semiconductor devices (e.g. field-effect transistors)  104 , an interconnect and dielectric stack  106 , a protective passivation dielectric  108 , and pads  110 . The illustrated technology  100  of  FIG. 1  is a simplified representation only and is intended to show relative placement. Additional or fewer features, layers, and or interconnects will likely be included in an actual device and/or wafer. 
         [0005]    Complex semiconductor devices such as memory chips or microprocessors typically have many electrical connections (power, ground, input and output and bidirectional signals, extrinsic passive components, etc). With few exceptions, these electrical connections (signals) are brought to the “outside world” through a protective package, and connections between the semiconductor chip and the package are made through holes in the protective passivation to relatively large (2-6 mils) features on the top metal layer called “pads” (e.g. pads  110  in  FIG. 1 ). At present there are two dominant methods for connecting the exposed top interconnect of these devices to the package. The first, illustrated in  FIG. 2 , is referred to as “wirebond” packaging. Wirebond packaging refers to attaching very thin conductive wires  202  between the metal pads  110  of the chip  100  and their appropriate conductive connections  204  in the package  206 . In the case of wirebond the mechanical connection to the package is made from the bottom  208  of the semiconductor chip  100 , while the electrical connections to the package are made from the top side  210  of the chip  100 . The second, illustrated in  FIG. 3 , is referred to as “flip-chip” packaging. Flip-chip packaging refers to forming conducting bumps  302  on the exposed pads  110 , flipping the chip  100  upside down, and placing those bumps  302  in direct connection with their associated conductive connections  304  in the package  306 . Often an appropriate thermal process is used to partially melt the bumps  302  during the die attach step, so that the bumps  302  form good conductive and mechanical connection to their associated connections  304  in the package  306 . A mechanical underfill or adhesive  308  may also be used to fill in the gaps between bumps  302 . In the case of flip-chip packaging, mechanical and electrical connections to the package are made from the same side—the inverted top side  210  of the chip  100 . 
         [0006]    Wirebond has been the dominant approach to integrated circuit packaging until recently. Flip-chip is rapidly gaining acceptance for at least four reasons. 1) The relatively high inductance of bond wires introduces crosstalk, noise, and signal integrity issues. 2) Flip-chip affords more options for getting heat (generated as the semiconductor devices burn power) out of the package. 3) Wirebond necessitates that the electrical connections to the chip be organized in a ring around the chip&#39;s perimeter, while flip-chip affords the flexibility of making these electrical connections almost anywhere in the die, vastly increasing the number of possible electrical connections and the chip-design flexibility in where they may be placed. 4) Elimination of ball bonds, wires, and the package lid allows the overall thickness of the completed, packaged product to be reduced. 
         [0007]    Regardless of whether flip-chip or wirebond is used, the presence of increasing numbers of layers of interconnect with increased pattern density is, in some cases, making it more difficult to use the underlying semiconductor elements in sensing applications. In addition, the ability in these fine-feature manufacturing technologies to incorporate additional films close to the underlying semiconductor devices suitable for sensing applications is limited by the complexity and sensitivity of the interconnect and isolation materials and structures. 
         [0008]    Needed is a structure where the semiconductor devices are exposed for sensing applications, while the associated interconnect structures and their final connection to the package remain protected. Such a structure should be suitable for depositing additional films for the purpose of sensing without having to disturb the semiconductor, interconnect, passivation, or electrical package connection features. 
       SUMMARY 
       [0009]    A hypersensitive semiconductor die structure is disclosed, in which flip-chip packaging is used in conjunction with a modified SOI die in which a thick silicon support substrate has been removed to increase sensitivity of the sensing device. Rather than being located beneath layers of interconnects and dielectric, the disclosed structure places the sensing devices close to the surface, more closely exposed to the environment in which sensing is to occur. The structure also allows for the placement of sensing films on nearer to the sensing devices and/or an oxide layer overlying the sensing devices. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0010]      FIG. 1  is a simplified cross-sectional diagram showing a 150 nm-generation semiconductor chip. 
           [0011]      FIG. 2  is a simplified cross-sectional diagram showing a wirebond technique for packaging a semiconductor chip. 
           [0012]      FIG. 3  is a simplified cross-sectional diagram showing a flip-chip technique for packaging a semiconductor chip. 
           [0013]      FIG. 4  is a simplified cross-sectional diagram showing a SOI On Package Hypersensitive Sensor structure in accordance with an embodiment of the present invention. 
           [0014]      FIG. 5  is a simplified cross-sectional diagram showing a SOI On Package Hypersensitive Sensor structure in accordance with an alternative embodiment of the present invention. 
           [0015]      FIG. 6  is a flow diagram illustrated a process for fabricating a SOI On Package Hypersensitive Sensor structure in accordance with a first embodiment of the present invention. 
           [0016]      FIG. 7  is a flow diagram illustrated a process for fabricating a SOI On Package Hypersensitive Sensor structure in accordance with an alternative embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    SOI (Silicon On Insulator) is an implementation of batch wafer semiconductor process technology where the thin top silicon (0.01 um to 10 um thick) in which the semiconductor devices will be formed is isolated from the vast majority of the rest of the thickness of the wafer (5-40 mils thick, referred to here as the “substrate”) by a dielectric layer (referred to as “buried oxide” or “BOX”). While SOI in various forms has been around for many years, most recently it is gaining acceptance in CMOS technologies. In the specific case of CMOS, SOI is desirable because it affords increased circuit density (the device spacings associated with junction isolation go away), improved circuit speed (due to reduced junction and interconnect capacitances), and reduced circuit power consumption (for the same reason). In accordance with various embodiments of the present invention, the buried oxide is exploited as an enabling fabrication feature rather than an electrical feature. 
         [0018]    The presence of the buried oxide in SOI affords a level of fabrication flexibility not present in bulk. In accordance with embodiments of the invention, the buried oxide can serve as a highly selective “etch stop,” allowing the bottom thick support wafer to be removed. The thin silicon, buried oxide, and associated interconnect features are aggregately quite thin (less than 1 mil) and likely require mechanical support. In addition, electrical connections are made to the metal pads of the device. 
         [0019]    The proposed structure in accordance with preferred embodiments of the present invention is shown in  FIG. 4 .  FIG. 4  is a simplified cross-sectional diagram showing a SOI On Package Hypersensitive Sensing Device structure  400  in accordance with an embodiment of the present invention. The structure  400  includes an SOI semiconductor chip  402  packaged using flip-chip technology (see the discussion associated with  FIG. 3 , above), with the thick bottom “substrate” support removed. This structure  400  may be referred to as a Silicon-on-insulator on-Package Hypersensitive Sensor structure. From top to bottom (with “top” referring to the portion of the chip  402  opposite the package  418 ), the structure  400  includes the buried oxide  404 , the electrical device semiconductor layers  406 , the interconnect and dielectric stack  408 , passivation dielectric  410  (with pad openings), pads  412 , conductive bumps  414 , and optional mechanical underfill or adhesive  416  between bumps. The chip  402  is electrically connected to associated conductive connections  416  on the flip-chip package  418 . 
         [0020]    The structure  400  may be employed to particular advantage in sensor applications, such as those involving light or radiation sensors. The structure  400  may be used to cause the devices fabricated in the thin semiconductor layer to be far more exposed to what they are intended to detect than they otherwise would be if they were “shielded” by either the interconnect and passivation layers (formerly on the top, with respect to the semiconductor device layer) or the thick semiconductor substrate (formerly on the bottom, with respect to the semiconductor device layer). Furthermore, with the thick support silicon removed and the interconnect system and associated electrical package connections on the bottom (closest to the package), and the semiconductor devices exposed on top (opposite the package) it is now practical to deposit one or more layers (e.g. treated films, such as organic or biological films for environmental or biological applications) in very close proximity to the semiconductor devices formed in the thin semiconductor layer without interfering with the device construction or interconnect stack. 
         [0021]    From a fabrication standpoint, for some applications, it may be favorable to remove the bottom thick silicon substrate and deposit (in close proximity to the semiconductor devices) any layers that may be required for sensing while the chip  400  is still in wafer form (i.e. before sawing the wafer into individual chips and placing the chips in packages). This is particularly true if any of the additional deposited layers need to be patterned. In this case, as shown in  FIG. 5 , a mechanical support structure  500  may be attached (such as by adhesive  502 ) to what was once the top of the wafer (the portion closest to where the chip will attached to the package  418 ) prior to removal of the thick silicon substrate portion. To provide the electrical connection between the pads  412  on the chip  400  and the conducting connections  506  in the package, holes  504  are cut in this mechanical support structure. Such holes  504  could be cut either before or after attaching to the device wafer. At some point prior to packaging, these holes  504  are filled with a conducting material. The mechanical carrier cannot practically be removed and will remain through packaging. Thus, regardless of the specifics of fabrication the structure changes, as shown in  FIG. 5 . The primary difference between the structures of  FIGS. 4 and 5  is the presence of the mechanical support structure in  FIG. 5 . 
         [0022]    Depending upon what the final device is intended to sense and whether or not it requires the deposition of additional films in close proximity to the semiconductor devices, many variations may be made to the general device structures described above. For example, the structure may take the form of the structures shown in  FIGS. 4 and 5 , but with the buried oxide patterned, removed, or thinned, such as by an etch process. As another example, the structure may take the form of the structures shown in  FIGS. 4 and 5 , where one or more additional layers (such as sensing layers) have been deposited on top of the “buried oxide,” possibly treated and/or possibly patterned. As yet another example, the structure may take the form of the structures shown in  FIGS. 4 and 5 , with the buried oxide patterned, removed, or thinned, where one or more additional layers have been deposited on top of the “buried oxide” (opposite the device layer) or device silicon, possibly treated and/or possibly patterned. The particular coatings and/or patterning will depend on the particular sensing application. 
         [0023]      FIGS. 6 and 7  are flow diagrams illustrating general process flows that may be used to fabricate the devices described above.  FIG. 6  shows a process that may be used to fabricate the structure shown in  FIG. 4 , while  FIG. 7  shows a process that may be used to fabricate the structure shown in  FIG. 5 . Other processes besides those shown in  FIGS. 6 and 7  may be used, depending on the particular sensing application and stability of the sensing layers (if any) to be applied. The goal is for the resulting device structure to be a silicon based sensor mounted on a flip-chip package with backside silicon removed and optionally some or all of the buried oxide removed and optionally with one or more additional sensing-related films deposited in very close proximity (i.e. where the backside silicon and buried oxide previously resided) to the device silicon layer. 
         [0024]    The process  600  of  FIG. 6  includes the following steps. At least one sensor device is formed in a silicon device layer in an SOI wafer (having a thick silicon support substrate, a buried insulator layer, and a silicon device layer), as shown in block  602 . In block  604 , an interconnect stack is formed over the silicon device layer opposite the buried insulator in the SOI wafer. In block  606 , a passivation layer is formed over the interconnect stack and conductive pads and conductive bumps are formed, for eventually connection to the flip-chip package. In block  608 , the wafer is sawed into individual dies, which are assembled into flip-chip packages, with the conductive bumps forming the electrical connections between the conductive pads and conductive connections in the package. In block  610 , the thick silicon substrate is removed, such as by etching, or a combination of mechanical and chemical processing. In block  612 , any additional sensing films (e.g. treated films) necessary for the particular sensing application are deposited and possibly patterned. Steps  602 - 612  may be performed in an order other than as illustrated, according to some embodiments. 
         [0025]    Blocks  702 - 706  of the process  700  of  FIG. 7  are similar to blocks  602 - 606  of the process  600  of  FIG. 6 . In block  708 , a mechanical support layer, such as a donor wafer, is adhered to the passivation layer by an adhesive. The mechanical support layer has holes mapped to the underlying conductive pads, so that electrical contact may be made to the conductive pads. The holes may be formed either before or after the mechanical support layer is adhered. A conductive material is placed in the holes to make the eventual electrical connection. Blocks  710 - 714  are similar to blocks  608 - 612  in the process  600 . 
         [0026]    Steps  702 - 714  of process  700  may be performed in an order other than as illustrated, according to some embodiments. For example, while block  712  of the process  700  describes applying/patterning any additional sensing films before sawing and assembly into flip-chip packages (block  714 ) takes place, this may not be possible if the additional sensing film(s) would not be stable in the subsequent sawing and assembly. This may be the case, for example, for some organic or biological films for certain environmental or medical sensing applications. In such a case, the sensing film(s) would likely be applied after sawing and assembly of the die into the flip-chip package. Similarly, removal of the thick support substrate could be performed after sawing and assembly, although the mechanical support layer adhered in block  708  is intended to make removal of the thick support substrate possible. 
         [0027]    The specific processes one would use are standard processes. For example, selective silicon removal using Potassium Hydroxide (KOH) may be used to remove the thick silicon substrate, similar to silicon is removed to create diaphragms in pressure transducers. Standard flip-chip manufacturing techniques may be used for bumping and die attachment. Attachment of mechanical support “donor” wafers may be accomplished using known techniques, in order to provide the mechanical support structure  500  shown in  FIG. 5 . U.S. patent application Ser. No. 12/135,787, titled “Neutron Detection Structure,” sets forth additional details on some of the processes that may be used to arrive at the structure described above, and is incorporated by reference herein in its entirety. 
         [0028]    An SOI on flip-chip structure with the thick bottom silicon substrate removed has been described. The resulting structure promotes the hyper-sensitizing of the semiconductor elements in sensor applications. In addition, the structures serves as an enabling platform for placing additional films in very close proximity to the semiconductor elements while not disturbing the interconnect and package technology.