Abstract:
A BIST circuit for testing both an analog-to-digital converter and a phase lock loop includes a controllable delay circuit, a NAND gate, a dividing circuit, a NOR gate and a charge/discharge circuit. The invention reduces the period of the signal under test, converts its pulse width to voltage and measures the output via an ADC. The clock jitter becomes sensitive through a delay cancellation method, thus, the accuracy is improved. The invention further comprises all testing procedure for period jitters of a PLL and static characteristics of an ADC. The test error caused by process variation can be corrected by a controllable delay circuit such that the error determination of the test result is prevented.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The invention relates to a circuit, and more particularly to a built-in self test (BIST) circuit for testing not only the differential non-linearity(DNL) error and the integral non-linearity(INL) error of an analog-to-digital converter(ADC) but also the period jitters of a clock signal. The clock signal can be outputs of an oscillator or a phase lock loop. 
         [0003]    2. Description of the Related Art 
         [0004]    A phase lock loop (PLL) is widely used in frequency synthesization, clock correction, clock distribution and phase demodulation. Frequency synthesization, clock correction, clock distribution and phase demodulation are generally used in optical fiber links, radio phones and computers. Clock variations such as period jitters of the phase lock loop circuit may degrade performance and limit applications of the phase lock loop circuit. Thus, for high-speed applications, precise and cost effective measurement on clock variation and period jitter is required. 
         [0005]      FIG. 1A  is a block diagram showing a conventional BIST for measuring period jitters as disclosed in U.S. Pat. No. 6,937,106. A conventional BIST circuit uses time-to-digital converter  2  to measure period jitters and divided by n (1/n) 1 prior to time-to-digital converter  2  is used to enlarge the period jitters of a signal under test to enhance test precision.  FIG. 1B  is a detailed schematic view showing a conventional time-to-digital converter  2 . The test resolution of the circuit shown in  FIG. 1A  is limited by the delay of the component in  FIG. 1B . Thus, the resolution of the signal under test that is not divided by 1/n divider 1 is within limits. 
         [0006]      FIG. 2  is a block diagram showing another conventional BIST circuit  20  for measuring period jitters comprising control signal generator  21 , period to voltage converter  22  and ADC  23 . Two output signals Q 1  and Q 2  are generated by control signal generator  21  according to a test signal T to control the charge time of comparator  26  from period to voltage  22 . Charge pump  25  converts the charge time to voltage and stores the voltage in capacitor  24 . Then, ADC  23  converts the load voltages to digital value. Output value of BIST  20  depends on resolution of ADC  23 . 
         [0007]    High precision period jitter of PLL is measured through the combination of BIST circuit  20  shown in  FIG. 2  and high resolution ADC  23 . Note that a defective ADC  23  may cause errors when measuring. Typically, using the ADC of current technologies is very difficult to detect the jitter less than 10 ps under the period of 1 ns˜100 ns. 
       BRIEF SUMMARY OF INVENTION 
       [0008]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
         [0009]    The invention provides a BIST circuit for testing an ADC and a PLL, comprising a controllable delay circuit, a calculating logic and a charge-discharge circuit. The controllable delay circuit has a first input terminal for receiving a test signal and adjusting a delay of the test signal according to a first control signal and outputting a delay signal at a first output terminal. The calculating logic calculates a difference between a signal under test and the delay signal to generate a clock width which is further used to control the charge-discharge circuit and output a charge-discharge signal to the ADC to measure the clock width. Due to large clock width, the precision of the method described in  FIG. 2  may be affected. The invention only measures the clock width of the difference between the signal under test and the delay signal to improve measuring precision. Further, the charge-discharge circuit can be applied to test the ADC and the PLL. The delay can be adjusted by using the controllable delay circuit to calibrate the measured results. As a result, the calibrated results are not be affected by process variation. 
         [0010]    The invention further provides a method for measuring the static performances of an ADC, which consists of delaying the test signal to obtain a delay signal, wherein the delay signal has a predetermined delay compared with the test signal; obtaining a charge-discharge signal according to the test signal and the delay signal; inputting the charge-discharge signal to the ADC; adjusting a period of the test signal and the predetermined delay and obtaining different output codes at an output terminal of the analog-to-digital; obtaining code periods corresponding to each output code according to a probability of two adjacent output codes occurring in a predetermined number of samples times; obtaining code voltages corresponding to each output code according to the RC curve and its code period; and finally obtaining the DNL and the INL of the ADC. 
         [0011]    In addition, the invention provides a period jitter measuring method for a test signal and an ADC comprising: delaying the test signal to obtain a delay signal, wherein the delay signal and the test signal having a predetermined delay; obtaining a charge-discharge signal according to the test signal and the delay signal; inputting the charge-discharge signal to the ADC and outputting different output codes at an output terminal of the ADC; obtaining code voltages corresponding to each output code; obtaining code period corresponding to each output code according to an RC curve and each code voltage; obtaining probabilities of each output code according to a number of times each output code occurs in a predetermined number of samples; and finally obtaining the period jitter of the clock signal under test. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0012]    The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0013]      FIG. 1A  is a schematic block diagram showing a conventional BIST circuit for measuring period jitters. 
           [0014]      FIG. 1B  is a schematic block diagram showing a time-to-digital circuit. 
           [0015]      FIG. 2  is a schematic block diagram of a conventional BIST circuit for measuring period jitters. 
           [0016]      FIG. 3A  is a block diagram showing a BIST circuit according to an embodiment of the invention. 
           [0017]      FIG. 3B  is timing diagram showing the operating waveform of the BIST circuit according to an embodiment of the invention. 
           [0018]      FIG. 4  shows the flowchart of testing the static characteristics of the ADC according to an embodiment of the invention. 
           [0019]      FIG. 5  is a schematic view showing the voltage drop and its corresponding RC curve under various process variations. 
           [0020]      FIG. 6  shows the probability of adjacent output codes occurring in a predetermined number of samples. 
           [0021]      FIG. 7  shows the flowchart of testing the period jitters of the PLL according to an embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF INVENTION 
       [0022]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0023]      FIG. 3A  shows a BIST circuit  30 , according to an embodiment of the invention, for testing performance of ADC  31  and period jitters of the phase lock loop. BIST circuit  30  comprises controllable delay circuit  32 , NAND gate  33 , dividing circuit  34 , NOR gate  35  and charge-discharge circuit  36 . [ 0021 ] Controllable delay circuit  32  has a first input terminal for receiving a test signal A. The delay from test signal A to delay signal B is adjusted by controllable delay circuit  32  according to a first control signal SI which may be the digital bus, and delay signal B is output from a first output terminal  322 . Test signal A and delay signal B are received by NAND gate  33  which performs NAND logic operation and outputs first logic signal C. Dividing circuit  34  is coupled to first input terminal  321  for increasing the period of test signal A and to output period-increased signal Q and inverse period-increased signal Q′. Period-increased signal Q and first logic signal C are received by NOR gate  35  which performs NOR logic operation and outputs second logic signal D. Charge-discharge circuit  36  outputs charge-discharge signal ADCin to ADC  31  according to inverse period-increased signal Q′ and second logic signal D. 
         [0024]    Two switched inverters  323  and  324  coupled in series shown in the  FIG.3A  are only the symbols of Controllable delay circuit  32 , not the actual circuits. The function of Controllable delay circuit  32  can only be implemented by other circuits. Dividing circuit  34  comprises D-type flip-flop  341  and inverter  342 . Inverse period-increased signal Q′ and test signal A is received by D-type flip-flop  341  to output period-increased signal Q. Period-increased signal Q is received by inverter  342  coupled to D-type flip-flop  341  to output inverse period-increased signal Q′. Charge-discharge circuit  36  comprises PMOS  361 , NMOS  362  and capacitor  363 . PMOS  361  has a first gate to receive inverse period-increased signal Q′, a first drain coupled to voltage source VDD, and a first source coupled to node N 1 . NMOS  362  has a second gate to receive second logic signal D, a second source coupled to node N 1 , a second drain coupled to ground VSS. Capacitor  363  is coupled between node N 1  and ground VSS. 
         [0025]      FIG. 3A  shows BIST circuit  30  according to an embodiment of the invention comprises first multiplexer  37  and clock divider  38 . First multiplexer  37  selectively outputs an ideal reference clock signal R 1  of a PLL outputted signal R 2  according to second control signal S 2 . Clock divider  38  divides the output signal of first multiplexer  37  according to divisor control signal S 4  to generate test signal A. Thus the precision of the period jitter measurement can be enhanced. In this embodiment, first multiplexer  37  outputs ideal reference clock signal R 1  when second control signal S 2 =0 (in digital-to-analog converter test mode), while first multiplexer  37  outputs PLL outputted signal R 2  when second control signal S 2 =1 (in PLL test mode). 
         [0026]    As shown in  FIG. 3A , BIST circuit  30  according to the invention further comprises second multiplexer  39 . Second multiplexer  39  selectively outputs a charge-discharge signal ADCin or output signal K of the standard circuit to ADC  31  according to third control signal S 3 . In this embodiment, second multiplexer  38  outputs charge-discharge signal ADCin when third control signal S 3 =0 (in standard mode), while second multiplexer  37  outputs output signal K of the standard circuit when third control signal S 3 =1 (in test mode). 
         [0027]      FIG. 3B  shows wave forms of BIST circuit  30  according to an embodiment of the invention, wherein test signal A is an original clock signal under test, delay signal B is the signal output from controllable delay circuit  32  after the clock signal passes through. The invention takes advantage of the control of intra logic to generate clock signal C which is equal to a signal under-test subtracting a predetermined delay. The predetermined delay is equal to the delay of the controllable delay circuit. Dividing circuit  34  doubles the frequency of the original signal under test to pre-charge capacitor  363  in a half period and to evaluate the period jitters in another half period. The maximum value (assuming 16-bit, FFFF) of the ADC can be measured after pre-charging. Jitter  1  can be measured when first logic signal C discharges, Jitter  2  can be measured after second pre-charging, and so on. 
         [0028]      FIG. 4  shows the flowchart  400  of testing the static characteristics of ADC  31  using BIST circuit  30 . In this embodiment, ADC  31  is a 3-bit ADC. 
         [0029]    First, simulation of various voltage drops and corresponding RC curves (referring to  FIG. 5 ) under various process variations according to the architecture of BIST circuit  30  is required before testing the static characteristic of ADC  31  (S 41 ). Performing multipoint testing on an integrated circuit (IC) to obtain an RC value RCx, and selecting an RC curve in  FIG. 5  closest to RCx (S 42 ). In this embodiment, take curve RC 2  for example. Note that process variation only affects the RC curve selected for each IC not the testing result. 
         [0030]    Then, third control signal is set to S 3 =1, second control signal to S 2 =0 and divisor control signal to S 4 =1 (S 43 ). Note that, divisor control signal S 4  is only used to bypass ideal reference clock signal R 1  to controllable delay circuit  32  in ADC mode. At this time, test signal A is ideal reference clock signal R 1 . Different output codes  0001 ˜ 111  can be obtained at the output terminal of ADC  31  according to different periods of test signal A and first control signal S 1 .  FIG. 6  shows each output code i and it&#39;s corresponding code period Ti obtained according to the probability of adjacent output codes i and i+1 occurring in a predetermined sampling times (S 44 ). In this embodiment of the invention, test signal A is tested 100 times in a 10 ns period, code  2  occurs 10 times, code  3  occurs 40 times, code  4  occurs 40 times and code  5  occurs 10 times, such that code period T 3  corresponding to code  3  is 10 ns. Code voltage V 0 ˜V 7  corresponding to output code  000 ˜ 111  is obtained according to code period T 0 ˜T 7  and curve RC 2  (S 45 ). The static characteristics of INLi and DNLi can be generated according to code voltage Vi corresponding to output code i (S 46 ). The performance of ADC is tradictionally defined as 
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         [0031]      FIG. 7  shows the flowchart  700  of testing the period jitters of the clock signal from an oscillator or a PLL in an IC by BIST circuit  30 . First, third control signal is set to S 3 =1, second control signal to S 2 =1 and divisor control signal to S 4 =1 (S 71 ). Then, an RC curve is selected. Note that, RC 2  is a multiple of the selected RC curve (S 72 ). Note that, for high sensitivity, selecting the RC curve with an RC value less than a predetermined value is preferred when testing the period jitter of the PLL, such as selecting an RC curve with RC value= 1/10*RC 2 , while electing the RC curve with an RC value exceeding another predetermined value is preferred when testing the static characteristics of ADC  31 . In this embodiment, take curve RC 3  for example. First control signal S 1  is set according to the average value of first control signal S 1  obtained from code period T 0 ˜T 7  and test signal A (S 73 ). 
         [0032]    Another RC curve with smaller RC value than curve RC 3  is selected when the output terminal of ADC  31  can not measure all output codes  0 ˜ 7 , until all output codes  0 ˜ 7  are measured at the output terminal of ADC  31 . If the RC value of an RC curve can not be reduced, the value of divisor control signal S 4  is enlarged until all output codes  0 ˜ 7  are measured at output terminal of ADC  31  (S 77 ). Each code period T 0 ∫T 7  corresponding to each code  0 ˜ 7  can be obtained according to curve RC 3  and each code voltage V 0 ˜V 7  when all output codes  0 ˜ 7  are measured at the output terminal of ADC  31  (S 74 ). 
         [0033]    The probability Pi of output code i can be obtained according to the number of times code i occurring in a predetermined number of samples (S 75 ). The period jitter of the PLL can be obtained according to the period T of test signal A, each code period Ti corresponding to each output code i, and the probability Pi of each output code I (S 76 ). The function to calculate period jitter is 
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         [0034]    The purpose of the invention is to reduce the pulse width of test signal A to the second logic signal D, then to convert the pulse width of second logic signal D to voltage and to output the digital signal which is inversely proportional to the period of test signal A. A test signal A with a larger period results in larger pulse width of the second logic signal D, longer discharge time and smaller digital output value measured at the output terminal of ADC  31 . Compared with the traditional method to measure the period of test signal A directly, the smaller pulse width of the second logic signal D can get higher resolution measurement results. The precision of the measuring method described in the invention can also be improved by using BIST circuit  30 . Moreover, in the invention, both ADC and PLL can be tested accurately. The value of first control signal S 1  can be adjusted by simulating the RC curves and by testing the characteristic curve of ADC  31 . Therefore, the BIST circuit  30  can be used to calibrate the errors due to process variation to make the measurement results more accurate. 
         [0035]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.