Abstract:
A reference voltage circuit includes a first current-voltage converting circuit consisting of a first diode element; a second current-voltage converting circuit consisting of first and second resistances and a second diode element; a third resistance; a first current mirror circuit configured to supply the third resistance with a current which is proportional to a current flowing through the first current-voltage converting circuit or the second current-voltage converting circuit, to generate a reference voltage; and a control section configured to equalize a voltage of the first current-voltage converting circuit and a voltage of the second current-voltage converting circuit. The second diode element and the first resistance are connected in series, and the second resistance is connected in parallel to the series connection of the first resistance and the second diode element.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a semiconductor CMOS reference voltage circuit.  
         [0003]     2. Description of the Related Art  
         [0004]     A conventional CMOS reference voltage circuit is disclosed in detail in Japanese Laid Open Patent Application (JP-A-Heisei, 11-45125, corresponding to U.S. Pat. No. 6,160,391: first conventional example). Since this reference voltage circuit of the first conventional example obtains a reference voltage through current-voltage conversion, this is similar to a further conventional reference voltage circuit of this type, in which a temperature dependency is canceled. However, in this reference voltage circuit of the first conventional example, it is difficult to attain the reference voltage circuit of a small chip area.  
         [0005]     In the further conventional reference voltage circuit, a reference current with a positive temperature dependency is converted into a voltage by an output circuit composed of a resistor and a diode (or a transistor that is diode-connected). A voltage drop across the resistor has a positive temperature dependency, and a forward voltage of the diode (or the transistor that is diode-connected) has a negative temperature dependency. Thus, a reference voltage of about ±1.2V was obtained in which the temperature dependencies are canceled by adding both of them.  
         [0006]     On the other hand, the reference voltage circuit disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 11-45125) generates a reference current that does not substantially have a temperature dependency, and the reference current is converted into a reference voltage of any voltage value by an output circuit composed of only resistors. Thus, the reference voltage circuit of this conventional example is excellent in that it can operates under the power supply voltage of 1.2V or less and the temperature dependency is canceled. The inventor of the present application reports it as [Current Mode Type Reference Voltage Circuit] in [Analog Circuit Design Technique for CMOS Circuit in Mobile Radio Terminal] (Triceps Corporation, 1999), as soon as this reference voltage circuit is laid open, and describes the detailed circuit analysis. Here, the operation of the reference voltage circuit disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 11-45125) will be described in accordance with the report.  
         [0007]     In  FIG. 1 , an operational amplifier DA1 controls common gate voltages of transistors P 1 , P 2  so as to attain V A =V B . Thus, 
 
V A =V B    (1) 
 
I 1 =I 2    (2) 
 
 Also, the current I 1  is separated into a current I 1A  flowing through a diode D 1  and a current I 1B  flowing through a resistor R 4 . Similarly, the current I 2  is separated into a current I 2A  commonly flowing through a series connection of a resistor R 1  and N diodes D 2  which are connected in parallel and a current I 2B  flowing through a resistor R 2 . 
 
Here, assuming R 2 =R 4    (3) 
 
I 1A =I 2A    (4) 
 
and 
 
I 1B =I 2B    (5) 
 
Also, 
 
V A =V F1    (6) 
 
 V   B   =V   F2   +ΔV   F    (7) 
 
Thus, Δ V   F   =V   F1   −V   F2    (8) 
 
 Since the voltage drop across R 1  is ΔV F , 
 
 I   2A   =ΔV   F   /R   1    (9) 
 
 I   1B   =I   2B   =ΔV   F   /R   2    ( 10) 
 
Here, Δ V   F   =V   T ln( N )   (11) 
 
 In this case, V T  is a thermal voltage, and represented below. 
 
 V   T =kT/q   (12) 
 
 where T is an absolute temperature [K], k is a Boltzmann&#39;s constant, and q is a unit electron charge. 
 
         [0008]     Thus, I 3  (=I 2 ) is converted into a voltage by the resistor R 3 , and the voltage is represented as shown below.  
                     V   REF     =       ⁢       R   3     *     I   3                   =       ⁢       R   3     ⁢     {         V   F1     /     R   2       +       (       V   T     ⁢     ln   ⁡     (   N   )         )     /   R1       }                   =       ⁢       (       R   3     /     R   2       )     ⁢     {       V   F1     +       (       R   2     /     R   1       )     ⁢     (       V   T     ⁢     ln   ⁡     (   N   )         )         }                     (   13   )             
 
 Here, {V F1 +(R 2 /R 1 )(V T ln(N))} is a voltage value of about ±1.2V in which the temperature dependency is canceled. Specifically, the voltage V F1  has the negative temperature dependency of about −1.9 mV/° C., and the voltage V T  has the positive temperature dependency of 0.0853 mV/° C. Thus, in order to cancel the temperature dependency, the value of (R 2 /R 1 )ln(N) must be 22.3. Also, since the thermal voltage V T  is 26 mV at the room temperature, (R 2 /R 1 ) (V T ln(N)) is about 580 mV at the room temperature. Thus, when the voltage V F1  is assumed to be 620 mV at the room temperature, {V F1 +(R 2 /R 1 )(V T ln(N))} is about 1.2V. 
 
         [0009]     Also, since the resistor ratio (R 3 /R 2 ) does not have the temperature dependency, the outputted reference voltage V REF  is also the voltage that does not have the temperature dependency. Here, the resistor ratio (R 3 /R 2 ) can be arbitrarily set. When 1&lt;(R 3 /R 2 ) is set, the voltage V REF  is a voltage higher than 1.2V, and when 1&gt;(R 3 /R 2 ) is set, the voltage V REF  is a voltage lower than 1.2V.  
         [0010]     In the reference voltage circuit, the ratio between a density of the current flowing through the diode D 1  and a density of the current flowing through the diode D 2  is desired to be large. That is, the difference between the voltage drop by the diode D 1  and the voltage drop by the diodes D 2  is desired to be large. For this reason, the reference voltage circuit disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 11-45125) is designed in such a manner that the diode D 2  is composed of many (for example, N) diodes, and the current densities of the respective diodes D 2  are reduced to make the voltage drop across the diode D 2  small. As a specific value of N, N=10 is described. However, when the circuit is actually realized (IEEE Symposium on VLSI circuits 1998, May), N=100 is used. Miniaturization in the CMOS process has been advanced to reduce a MOS transistor in size. However, the size of the diode using a parasitic bipolar element is incomparably large as compared with the MOS transistor. Also, the ratio N of the diodes D 1  and D 2  is required to be large, such as one digit or two digits. Thus, the chip area becomes huge.  
       SUMMARY OF THE INVENTION  
       [0011]     In an aspect of the present invention, a reference voltage circuit includes a first current-voltage converting circuit consisting of a first diode element; a second current-voltage converting circuit consisting of first and second resistances and a second diode element; a third resistance; a first current mirror circuit configured to supply the third resistance with a current which is proportional to a current flowing through the first current-voltage converting circuit or the second current-voltage converting circuit, to generate a reference voltage; and a control section configured to equalize a voltage of the first current-voltage converting circuit and a voltage of the second current-voltage converting circuit. The second diode element and the first resistance are connected in series, and the second resistance is connected in parallel to the series connection of the first resistance and the second diode element.  
         [0012]     Here, the first diode element may be a first diode or and a first bipolar transistor which is connected to form a diode, and the second diode element may be a second diode or and a second bipolar transistor which is connected to form a diode.  
         [0013]     Also, the control section may include a differential amplifier or an operational amplifier.  
         [0014]     Also, the control section may include a current mirror circuit containing the first current mirror circuit; and a second current mirror circuit self-biased by the current mirror circuit.  
         [0015]     Also, the control section compares the current flowing through the first current-voltage converting circuit with the current flowing through the second current-voltage converting circuit by a second current mirror circuit, and equalizes the voltage of the first current-voltage converting circuit and the voltage of the second current-voltage converting circuit by biasing a third current mirror circuit by a comparing result of the second current mirror circuit.  
         [0016]     Also, the control section may include a second current mirror circuit self-biased by an inverse Widlar current mirror circuit which may include the first current mirror circuit.  
         [0017]     In another aspect of the present invention, a reference voltage circuit includes a first current-voltage converting circuit consisting of a first diode element; a second current-voltage converting circuit consisting of first and second resistances and a second diode element; a third resistance; a first current mirror circuit configured to supply the third resistance with a current which is proportional to a current flowing through the first current-voltage converting circuit or the second current-voltage converting circuit, to generate a reference voltage; and a control section configured to equalize a voltage of the first current-voltage converting circuit and a voltage of the second current-voltage converting circuit. The second resistance is connected with the second diode element in parallel, and the second resistance is connected in series with a parallel connection of the first resistance and the second diode element.  
         [0018]     Here, the first diode element may be a first diode or and a first bipolar transistor which is connected to form a diode, and the second diode element may be a second diode or and a second bipolar transistor which is connected to form a diode.  
         [0019]     Also, the control section may include a differential amplifier or an operational amplifier.  
         [0020]     Also, the control section may include a current mirror circuit containing the first current mirror circuit; and a second current mirror circuit self-biased by the current mirror circuit.  
         [0021]     Also, the control section compares the current flowing through the first current-voltage converting circuit with the current flowing through the second current-voltage converting circuit by a second current mirror circuit, and equalizes the voltage of the first current-voltage converting circuit and the voltage of the second current-voltage converting circuit by biasing a third current mirror circuit by a comparing result of the second current mirror circuit.  
         [0022]     Also, the control section may include a second current mirror circuit self-biased by an inverse Widlar current mirror circuit which may include the first current mirror circuit.  
         [0023]     In another aspect of the present invention, a reference voltage circuit includes a first current-voltage converting circuit consisting of a first bipolar transistor; a second current-voltage converting circuit consisting of first and second resistances and a second bipolar transistor which is connected to form a diode; a third resistance; a control section configured to equalize a voltage of the first current-voltage converting circuit and a voltage of the second current-voltage converting circuit; a first current mirror circuit configured to supply the third resistance with a current which is proportional to a current flowing through the first current-voltage converting circuit or the second current-voltage converting circuit, to generate a reference voltage; and a third bipolar transistor whose base is connected to an output of the first current-voltage converting circuit, and whose collector drives the first current mirror circuit. The second bipolar transistor is connected in series with the first resistance, and the second resistance is connected in parallel to the series connection of the first resistance and the second bipolar transistor.  
         [0024]     In another aspect of the present invention, a reference voltage circuit includes a first current-voltage converting circuit consisting of a first bipolar transistor; a second current-voltage converting circuit consisting of first and second resistances and a second bipolar transistor which is connected to form a diode; a third resistance; a control section configured to equalize a voltage of the first current-voltage converting circuit and a voltage of the second current-voltage converting circuit; a first current mirror circuit configured to supply the third resistance with a current which is proportional to a current flowing through the first current-voltage converting circuit or the second current-voltage converting circuit, to generate a reference voltage; and a third bipolar transistor whose base is connected to an output of the first current-voltage converting circuit, and whose collector drives the first current mirror circuit. The first resistance is connected in parallel with the second bipolar transistor, and the second resistance is connected in series with the parallel connection of the first resistance and the second bipolar transistor.  
         [0025]     In another aspect of the present invention, a reference voltage circuit includes a first current-voltage converting circuit consisting of a first resistance and a first diode element; a second current-voltage converting circuit consisting of second and third resistances and a second diode element; a fourth resistance; a control section configured to equalize a voltage of the first current-voltage converting circuit and a voltage of the second current-voltage converting circuit; and a first current mirror circuit configured to supply the fourth resistance with a current which is proportional to a current flowing through the first current-voltage converting circuit or the second current-voltage converting circuit, to generate a reference voltage. The first resistance and the first diode element are connected with each other in parallel, and the second resistance is connected in series with the second diode element, and the third resistance is connected in parallel with the series connection of the first resistance and the second diode element. Also, the control section compares the current flowing through the first current-voltage converting circuit and the current flowing through the second current-voltage converting circuit by a second current mirror circuit, and equalize the voltage of the first current-voltage converting circuit and the voltage of the second current-voltage converting circuit, by biasing a third current mirror circuit based on the comparing result of the second current mirror circuit.  
         [0026]     Here, the first diode element may be a first diode or and a first bipolar transistor which is connected to form a diode, and the second diode element may be a second diode or and a second bipolar transistor which is connected to form a diode.  
         [0027]     In another aspect of the present invention, a reference voltage circuit includes a first current-voltage converting circuit consisting of a first resistance and a first diode element; a second current-voltage converting circuit consisting of second an third resistances and a second diode element; a fourth resistance; a control section configured to equalize a voltage of the first current-voltage converting circuit and a voltage of the second current-voltage converting circuit; and a first current mirror circuit configured to supply the fourth resistance with a current which is proportional to a current flowing through the first current-voltage converting circuit or the second current-voltage converting circuit, to generate a reference voltage. The first resistance and the first diode element are connected with each other in parallel, and the second resistance is connected in series with the second diode element, and the third resistance is connected in parallel with the series connection of the first resistance and the second diode element. The control section may include a second current mirror circuit which is self-biased by an inverse Widlar current mirror circuit which contains the first current mirror circuit.  
         [0028]     Here, the first diode element may be a first diode or and a first bipolar transistor which is connected to form a diode, and the second diode element may be a second diode or and a second bipolar transistor which is connected to form a diode. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0029]      FIG. 1  is a circuit diagram showing the configuration of a conventional reference voltage circuit;  
         [0030]      FIG. 2  is a circuit diagram showing the configuration of a reference voltage circuit according to a first embodiment of the present invention;  
         [0031]      FIG. 3  is a circuit diagram showing the configuration of the reference voltage circuit according to a second embodiment of the present invention;  
         [0032]      FIG. 4  is a circuit diagram showing the configuration of the reference voltage circuit according to a third embodiment of the present invention;  
         [0033]      FIG. 5  is a circuit diagram showing the configuration of the reference voltage circuit according to a fourth embodiment of the present invention;  
         [0034]      FIG. 6  is a circuit diagram showing the configuration of the reference voltage circuit according to a fifth embodiment of the present invention;  
         [0035]      FIG. 7  is a circuit diagram showing the configuration of the reference voltage circuit according to a sixth embodiment of the present invention;  
         [0036]      FIG. 8  is a circuit diagram showing the configuration of the reference voltage circuit according to a seventh embodiment of the present invention;  
         [0037]      FIG. 9  is a circuit diagram showing the configuration of the reference voltage circuit according to an eighth embodiment of the present invention;  
         [0038]      FIG. 10  is a circuit diagram showing the configuration of the reference voltage circuit according to a ninth embodiment of the present invention;  
         [0039]      FIG. 11  is a circuit diagram showing the configuration of the reference voltage circuit according to a tenth embodiment of the present invention;  
         [0040]      FIG. 12  is a circuit diagram showing the configuration of a circuit when a self-biasing method shown in  FIGS. 6 and 7  is applied to the circuit shown in  FIG. 1 ; and  
         [0041]      FIG. 13  is a circuit diagram showing the configuration of a circuit when a self-biasing method shown in  FIGS. 8 and 9  is applied to the circuit shown in  FIG. 1 . 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0042]     Hereinafter, a reference voltage circuit of the present invention will be described in detail, with reference to the attached drawings.  
         [0043]      FIG. 2  is a circuit diagram showing the configuration of a CMOS reference voltage circuit according to the first embodiment of the present invention. With reference to  FIG. 2 , the CMOS reference voltage circuit in the first embodiment contains an operational amplifier AP 1 , P-channel CMOS transistors MP 1  to MP 3 , diodes D 1  and D 2  and resistors R 1  to R 3 . Each of the diodes D 1  and D 2  are single and may be a bipolar transistor that is diode-connected. Hereafter, unless being specifically referred, the diode includes the bipolar transistor that is diode-connected.  
         [0044]     The P-channel MOS transistors MP 1  to MP 3  whose sources are connected to a power supply voltage V DD  configure a current mirror circuit. The diode D 1  is provided between the drain of the CMOS transistor MP 1  and a ground (GND). The diode D 1  constitutes a first current-voltage converter  13 . A series circuit of the resistor R 1  and the diode D 2  and the resistor R 2  connected to the series circuit in parallel are connected between the drain of the MOS transistor MP 2  and the ground. The circuit composed of the resistor R 1 , the diode D 2  and the resistor R 2  configures a second current-voltage converter  15 . A node N 1  between the MOS transistor MP 1  and the first current-voltage converter  13  is connected to an inversion input terminal of the operational amplifier AP 1 . A node N 2  between the MOS transistor MP 2  and the second current-voltage converter  15  is connected to a non-inversion input terminal of the operational amplifier AP 1 . An output terminal of the operational amplifier AP 1  is connected to the gates of the MOS transistors MP 1  to MP 3 . The resistor R 3 is connected between the drain of the MOS transistor MP 3  and the ground, and a reference output voltage V REF  is outputted from a node N 3  between the MOS transistor MP 3  and the resistor R 3 .  
         [0045]     A gate voltage common to the MOS transistors MP 1  to MP 3  is controlled by the operational amplifier AP 1  so that the two input terminal voltages of the operational amplifier AP 1  become equal, and thereby the current flowing through each of the MOS transistors MP 1  to MP 3  is controlled.  
         [0046]     Assuming that forward voltages of the diodes D 1  and D 2  are V F1  and V F2  and the currents flowing through the MOS transistors MP 2  and MP 3  are equal, the following equation (14) is met.  
                     I   2     =     I   3                 =         V   F1     /     R   2       +       (       V   F1     -     V   F2       )     /     R   1                     =       {       V   F1     +       (       R   2     /     R   1       )     ⁢   Δ   ⁢           ⁢     V   F         }     /     R   2                     (   14   )             
 
 Here, the voltage V F1  has the temperature dependency of about −1.9 mV/° C. Also, the voltage V F2  has the temperature dependency of about −1.9 mV/° C. 
 
         [0047]     Assuming that both of the diodes D 1  and D 2  are the unit diodes, the following equation (15) is met. 
 
Δ V   F   =V   T ln{ I   1 /( I   2   −V   F1   /R   2 )}  (15) 
 
 Here, assuming that I 1 =I 2 , a relation of I 1 &gt;(I 2 −V F1 /R 2 ) is met and a relation of I 1 /(I 2 −V F1 /R 2 )&gt;1 is met. Therefore, the ln item of the equation (15) is understood to be always positive (&gt;0). That is, the voltage ΔV F  has a positive temperature dependency even in this circuit, as well known. Thus, this temperature dependency is approximately proportional to a thermal voltage V T  (its temperature dependency is 0.00853 mv/° C). That is, the temperature dependency of the item of {V F1 +(R 2 /R 1 )ΔV F }/R 2  in the equation (14) can be substantially canceled by setting the resistor ratio (R 2 /R 1 ) and carrying out a weight addition of the voltage V F1  having the negative temperature dependency and the voltage ΔV F  having the positive temperature dependency. 
 
         [0048]     Here, if temperature dependency of the item of {V F1 +(R 2 /R 1 )ΔV F }/R 2  in the equation (14) can be canceled, the currents I 2  and I 3  do not substantially have any temperature dependency except the temperature dependency caused by the resistor R 2 . The operational condition of the second current-voltage converter driven by the current I 2  is same as the operational condition of the conventional technique. Here, the diodes D 1  and D 2  are the unit diodes and their current densities are naturally different, and the current density of the diode D 2  is reduced by a current flowing through the resistor R 2 . Thus, as mentioned above, even in case of I 1 =I 2 , a relation of V F1 &gt;V F2  is always met.  
         [0049]     The reference voltage V REF  outputted at this time is represented as shown below.  
                     V   REF     =       R   3     *     I   3                   =       (       R   3     /     R   2       )     *     {       V   F1     +       (       R   2     /     R   1       )     ⁢   Δ   ⁢           ⁢     V   F         }                     (   16   )             
 
 where assuming that the voltage VF 2  is about 580 mV at the room temperature, the voltage V F1  is 620 mV at the room temperature, and it could be understood that {V F1 +(R 3 /R 1 )ΔV F } is about 1.2V, similarly to the explanation of the conventional examples. Also, since the resistor ratio (R 3 /R 2 ) does not have the temperature dependency, the output reference voltage V REF  becomes a voltage in which the temperature dependencies are canceled. 
 
         [0050]     Here, the resistor ratio (R 3 /R 2 ) can be optionally set. If 1&lt;(R 3 /R 2 ) is set, the V REF  is the voltage higher than 1.2V. If 1&gt;(R 3 /R 2 ) is set, the reference voltage V REF  is a voltage lower than 1.2V, similar to the conventional examples. In particular, if 1&gt;(R 3 /R 2 ) is set such that the V REF  is lower than 1.2V, the power supply voltage is decreased. For example, if V REF =1.0 V is set, the reference voltage circuit can operate from the power supply voltage of about 1.2V.  
         [0051]     By the way, in order to realize the nonlinear temperature characteristic of the forward voltage V F  of the diode, for example, the slightly convex characteristic obtained by correcting the characteristic in which the dull property in the temperature change to a lower temperature, that is, the characteristic which has a peak at the room temperature and is slightly dropped on the lower and higher temperature side, the current ratio of the current mirror circuit composed of the MOS transistors MP 1  and MP 2  is sometimes required to be slightly changed from 1:1. Or, in order to make the current densities of the diodes D 1  and D 2  largely different, the transistor size of the MOS transistor MP 1  is set to be greater than the transistor size of the MOS transistor MP 2 . Of course, the method of connecting the N D 2  unit diodes in parallel and making the current densities of D 1  and D 2  greatly different is still effective. However, in this case, the current larger than the current flowing through the diode D 2  originally flows through the diode D 1 . Therefore, it is sufficient that this N value is not in a range of 10 to 100 but may be a small natural number. Also, since the resistor connected in parallel to the diode D 1  can be omitted, the chip area can be reduced.  
         [0052]     To simplify the operation explanation, the simple current mirror circuit is used in the above, in  FIG. 2 . However, in recent years, the fine structure of the CMOS process has been remarkably advanced, which results in the easy introduction of the influence of a channel length modulation in a transistor. For example, in the circuit of  FIG. 2 , the MOS transistors MP 1  and MP 2  have a same drain-source voltage. However, their drain-source voltages differ from that of the MOS transistor MP 3 . In particular, at the time of the temperature variation, the drain-source voltages of the transistors MP 1 , MP 2  and MP 3  are varied due to the variations caused by the temperature dependencies of the forward voltages of the diodes. Thus, there is the influence of the channel length modulation of the transistor, although it is very small, from the viewpoint of the strict consideration. Therefore, use of a cascade current mirror circuit and the like as the current mirror circuit is usually adopted to reduce this influence.  
         [0053]     A reference voltage circuit according to the second embodiment of the present invention will be described below. Although the second embodiment is similar to the first embodiment, a second current-voltage converter  15 A is used instead of the second current-voltage converter  15  in the first embodiment, as shown in  FIG. 3 . In the second current-voltage converter  15 A, the resistor R 2  is connected in parallel to the diode D 2  and the parallel circuit is connected in series to the resistor R 1 . Here, assuming that the both of the diodes D 1  and D 2  are the unit diodes, the MOS transistors MP 1  and MP 2  are controlled by the operational amplifier AP 1  so that the two input terminal voltages are equal. If the currents of the MOS transistors MP 2  and MP 3  are equal, the following equation is met.  
                     I   2     =     I   3                 =       (       V   F1     -     V   F2       )     /     R   1                   =     Δ   ⁢           ⁢       V   F     /     R   1                       (   17   )             
 
 The voltage V F1  has a temperature dependency of about −1.9 mV/° C., and the voltage V F2  also has a temperature dependency of about −1.9 mV/° C. 
 
         [0054]     In this case, assuming that the both of the diodes D 1  and D 2  are the unit diodes, the following equation is met. 
 
Δ V   F   =V   T ln{ T   1 /( I   2   −V   F2   /R   2 )}  (18) 
 
 If I 1 =I 2 , a relation I 1 &gt;(I 2 −V F2 /R 2 ) is always met. Thus, a relation I 1 /(I 2 −V F2 /R 2 )}&gt;1 is met, and the 1n item of the equation (18) is always positive (&gt;0). That is, the following equation is met. 
 
Δ V   F   =V   T ln[1/{1− V   F2 /( I   2   R   2 )}]  (18′) 
 
 The equation (17) is different in form from the equation (14). The voltage difference ΔV F  indicated in the equation (18)′ does not have the positive temperature dependency. The reason that the voltage difference ΔV F  does not substantially have the temperature dependency will be described below. 
 
         [0055]     In the equation (18′), the thermal voltage V T  has the positive temperature dependency (+0.0853 mV/° C.) proportional to the temperature. Also, the voltage V F2  in [] has the negative temperature dependency of about −1.9 mV/° C. For the easy explanation, if the temperature dependency of the resistor R 2  is small to an ignoble extent, since R 2 &gt;&gt;R 1 , the product of I 2 R 2  is a value exceeding the voltage V F2  (namely, I 2 R 2 &gt;V F2 ). Thus, when the value of 1/{1−V F2 /(I 2 R 2 )} takes a value greater than 1, for example, the value takes 2 (in case of I 2 R 2 =0.5V F2 ) or 3 (in case of I 2 R 2 =0.667V F2 ), the temperature is assumed to be changed with the thus-set value as the center. In this case, ln[1/(1−V F2 /(I 2 R 2 )}] is also varied. This variation region lies in the region where the inclination is relatively large in the function of ln[1/{1−V F2 /(I 2 R 2 )}]. For example, even if the desirable current I 2  does not have the temperature dependency, the temperature dependency of the voltage V F2  changes {1−V F2 /(I 2 R 2 )} depending on the temperature. That is, due to this temperature dependency, [1/{1−V F2 /(I 2 R 2 )}] has the negative temperature dependency. Therefore, {1−V F2 /(I 2 R 2 )} also has the negative temperature dependency, and becomes large as the temperature is decreased and becomes small as the temperature is increased.  
         [0056]     The current I 2  is a sum of the current flowing through the unit diode D 2  and the current flowing through the resistor R 2  connected in parallel to the unit diode D 2 . The control is carried out in such a manner that the current I 1  flowing through the unit diode D 1  and this current I 2  are equal to each other. Thus, the current I 2  does not substantially have the temperature dependency because the temperature dependency of the current flowing through the resistor R 2  (the negative temperature dependency based on the voltage V F2  having the negative temperature dependency) and the temperature dependency of the current flowing through the resistor R 2  (the positive temperature dependency opposite to the voltage V F2 ) are canceled. At this time, the temperature dependencies are substantially canceled. Then, the value [1/{1−V F2 /(I 2 R 2 )}] in [] of ln[1/{1−V F2 /(I 2 R 2 )}] becomes greater as the temperature becomes lower, and becomes smaller as the temperature becomes higher. Here, by properly setting the values of the resistors R 1  and R 2 , it is possible to absorb the variation caused by the temperature dependency of the ln[] item so as to substantially cancel the positive temperature dependency (the temperature dependency is 0.0853 mV/° C.) of the thermal voltage V T . That is, the voltage difference ΔV F  does not have the temperature dependency. The reference voltage V REF  outputted at this time is represented as shown below.  
                     V   REF     =       R   3     *     I   3                   =       (       R   3     /     R   1       )     ⁢   Δ   ⁢           ⁢     V   F                     (   19   )             
 
 Also, since the resistor ratio (R 3 /R 1 ) does not have the temperature dependency, the reference voltage V REF  is also a voltage where the temperature dependencies are canceled. Here, the resistor ratio (R 3 /R 1 ) can be optionally set, and the voltage difference ΔV F  is a voltage from about several 10 mV to one hundred and several 10 mV. Thus, by setting (R 3 /R 1 )&gt;1((R 3 /R 1 )&gt;1), the reference voltage V REF  can be set to a voltage lower than 1.0 V. In this case, the power supply voltage can be decreased. For example, when V REF =1.0V is set, the reference voltage circuit can operate in the power supply voltage of about 1.2V. 
 
         [0057]     The reference voltage circuit according to the third embodiment of the present invention will be described below. In the reference voltage circuit according to the third embodiment in which a topology (D 1 , {(R 1 −D 2 )//R2}) is used in which the diode D 1  is used and the second current-voltage converter in which the resistor R 2  is connected in parallel to a series connection of the diode D 2  and the resistor R 1 , the operational amplifier AP 1  is omitted through a self-biasing method.  
         [0058]      FIG. 4  shows one example of the reference voltage circuit using the self-biasing method according to the third embodiment. However, for the simple description, a start-up circuit is omitted. In  FIG. 4 , the operational amplifier AP 1  is omitted, and N-channel MOS transistors MN 1  and MN 2  are added. In the P-channel transistors MP 1  to MP 3  whose sources are connected to the power supply V DD , their gates are commonly connected, and the gate and drain of the transistor MP 2  are commonly connected. The gates of the N-channel MOS transistors MN 1  and MN 2  are commonly connected. The gate and drain of the transistor MN 1  are commonly connected. The drain of the N-channel MOS transistor MN 1  is connected to the drain of the P-channel MOS transistor MP 1 , and the source of the N-channel MOS transistor MN 1  is connected to the first current-voltage converter  13 . The drain of the N-channel MOS transistor MN 2  is connected to the drain of the P-channel MOS transistor MP 1 , and the source of the N-channel MOS transistor MN 1  is connected to the second current-voltage converter  15 .  
         [0059]     Thus, the P-channel transistors MP 1  and MP 2  and the N-channel transistors MN 1  and MN 2  constitute the current mirror circuits, respectively. The current mirror circuit composed of the P-channel transistors MP 1  and MP 2  self-biases the current mirror circuit composed of the N-channel transistors MN 1  and MN 2 . Consequently, the currents flowing through the N-channel transistors MN 1  and MN 2  are proportional to each other. When the transistor sizes of the N-channel transistors MN 1  and MN 2  are equal and the transistor sizes of the P-channel transistors MP 1  and MP 2  are equal, the currents flowing through the N-channel transistors MN 1  and MN 2  become equal to each other. In any event, since they are self-biased, the voltages between the gates and the sources of the respective N-channel transistors MN 1  and MN 2  become equal to each other. The voltage applied to the first current-voltage converter  13 , namely, the diode D 1  is equal to the voltage applied to the second current-voltage converter  15 , namely, the circuit {(R 1 −D 2 )//R 2 } in which the resistor R 1  is connected in series to a parallel circuit of the diode D 2  and the resistor R 2 . Thus, the same operation condition as in the foregoing operational amplifier can be attained in (D 1 , {(R 1 −D 2 )//R 2 }). Thus, the characteristics are obtained which is similar to the reference voltage circuit in the first embodiment shown in  FIG. 2 . It should be noted that the diode D 1  and the circuit {(R 1 −D 2 )//R 2 } may be driven by any of the N-channel transistors MN 1  and MN 2 .  
         [0060]     The reference voltage circuit according to the fourth embodiment of the present invention will be described below. In the reference voltage circuit according to the fourth embodiment, the circuit topology (D 1 , {R 1 −(D 2 //R2)}) in which the first current-voltage converter  13  has the diode D 1  and the second current-voltage converter  15 A has a series circuit of the resistor R 1  and a parallel circuit of the diode D 2  and the resistor R 2  is self-biased. Thus, the operational amplifier can be omitted as shown in  FIG. 5 .  
         [0061]     In the P-channel transistors MP 1  to MP 3  whose sources are connected to the power supply V DD , their gates are commonly connected, and the gate and drain of the transistor MP 2  are commonly connected. The gates of the N-channel MOS transistors MN 1  and MN 2  are commonly connected. The gate and drain of the transistor MN 1  are commonly connected. The drain of the N-channel MOS transistor MN 1  is connected to the drain of the P-channel MOS transistor MP 1 , and the source of the N-channel MOS transistor MN 1  is connected to the first current-voltage converter  13 . The drain of the N-channel MOS transistor MN 2  is connected to the drain of the P-channel MOS transistor MP 1 , and the source of the N-channel MOS transistor MN 1  is connected to the second current-voltage converter  15 A. Thus, the P-channel transistors MP 1  and MP 2  and the N-channel transistors MN 1  and MN 2  constitute the current mirror circuits, respectively. The current mirror circuit composed of the P-channel transistors MP 1  and MP 2  self-biases the current mirror circuit composed of the N-channel transistors MN 1  and MN 2 . Consequently, the currents flowing through the N-channel transistors MN 1  and MN 2  are proportional to each other. When the transistor sizes of the N-channel transistors MN 1  and MN 2  are equal and the transistor sizes of the P-channel transistors MP 1  and MP 2  are equal, the currents flowing through the N-channel transistors MN 1  and MN 2  become equal to each other. In any event, since self-bias is carried out, the voltages between the gates and the sources of the respective N-channel transistors MN 1  and MN 2  become equal to each other. The voltage applied to the first current-voltage converter  13 , namely, the diode D 1  is equal to the voltage applied to the second current-voltage converter  15 A, namely, the circuit {(R 1 −D 2 )//R 2 } in which the resistor R 1  is connected in series to the parallel circuit of the diode D 2  and the resistor R 2 . The same operation condition as in use of the foregoing operational amplifier can be attained in (D 1 , {(R 1 −D 2 )//R 2 }). Thus, the characteristics are obtained which are similar to the reference voltage circuit in the first embodiment shown in  FIG. 3 . It should be noted that the diode D 1  and the circuit {(R 1 −D 2 )//R 2 } may be driven by any of the N-channel transistors MN 1  and MN 2 . The influence of the channel length modulation of the transistor easily appears in the reference voltage circuit shown in  FIGS. 4 and 5 .  
         [0062]     The reference voltage circuits according to the fifth embodiment and the sixth embodiment of the present invention will be described below, with reference to  FIGS. 6 and 7 . In those embodiments, the influence of the channel length modulation is reduced. Here, the start-up circuit is omitted for the simple explanation.  
         [0063]     With reference to  FIG. 6 , the P-channel transistors MP 1  to MP 3  whose sources are connected to the power supply V DD  constitute the current mirror circuit, and the gate of the P-channel transistor MP 2  is connected to the drain thereof. The P-channel transistors MP 4  and MP 5  constitute the current mirror circuit, the sources of the transistors MP 4  and MP 5  are connected to the power supply V DD , the gate of the transistors MP 4  and MP 5  are commonly connected, and the gate of the transistor MP 4  is connected to the drain thereof. The drains of the N-channel transistors MN 2  and MN 1  are connected to the drains of the transistors MP 2  and MP 4 , and the gates of the N-channel transistors MN 2  and MN 1  are commonly connected. The second current-voltage converter  15  and first current-voltage converter  13  in the first embodiment are connected to the sources of the N-channel transistors MN 2  and MN 1 , respectively. The drains of the N-channel transistors MN 4  and MN 3  are connected to the drains of the transistors MP 1  and MP 5 , respectively. The gates of the N-channel transistors MN 4  and MN 3  are commonly connected. The gate of the transistor MN 3  is connected to the drain thereof, and the drain of the transistor MN 4  is connected to the gates of the transistors MN 1  and MN 2 . Diodes D 4  and D 3  are connected between the sources of the N-channel transistors MN 4  and MN 3  and the ground, respectively. The transistor MP 3  is similar to the foregoing embodiment.  
         [0064]     The currents flowing through the respective N-channel transistors MN 1  and MN 2  are current-compared by the current mirror circuit composed of the N-channel transistors MN 3  and MN 4 , through the current mirror circuit composed of the P-channel transistors MP 4  and MP 5  and the current mirror circuit composed of the P-channel transistors MP 1  and MP 2 . Thus, the common gate voltage of the N-channel transistors MN 1  and MN 2  is controlled such that the currents flowing through the respective N-channel transistors MN 1  and MN 2  are equal to each other. Thus, the voltages between the respective gates and sources of the N-channel transistors MN 1  and MN 2  become equal to each other. Therefore, the voltage applied to the diode D 1  is equal to the voltage applied to the second current-voltage converter {(R1−D2)//R2}  15  in which the resistor R 2  is connected in parallel to the series connection of the diode D 2  and the resistor R 1 . The same operation condition in a case of using the foregoing operational amplifier can be attained in (D1, {(R1−D2)//R2}). Thus, the characteristics similar to  FIG. 2  can be obtained and the reference voltage circuit is realized. Here, the diodes D 3  and the D 4  are inserted so as to equalize the drain voltages of the N-channel transistors MN 3  and MN 4 . It should be noted that the diode D 1  and {(R1−D2)//R2} may be driven by any of the N-channel transistors MP 1  and MP 2 .  
         [0065]      FIG. 7  shows the reference voltage circuit according to the sixth embodiment. The reference voltage circuit according to the sixth embodiment is similar to the reference voltage circuit according to the fifth embodiment. However, this is different in that the second current-voltage converter  15  is changed to the second current-voltage converter  15 A.  
         [0066]     The currents flowing through the respective N-channel transistors MN 1  and MN 2  are current-compared by the current mirror circuit composed of the N-channel transistors MN 3  and MN 4 , through the current mirror circuit composed of the P-channel transistors MP 1  and MP 2  and the current mirror circuit composed of the P-channel transistors MP 4  and MP 5 . The common gate voltage of the N-channel transistors MN 1  and MN 2  is controlled such that the currents flowing through the respective N-channel transistors MN 1  and MN 2  are equal to each other. Thus, the voltages between the respective gates and sources of the N-channel transistors MN 1  and MN 2  become equal to each other. Then, the voltage applied to the diode D 1  of the first current-voltage converter  13  is equal to the voltage applied to the circuit {R1−(D2//R2)} in which the resistor R 1  is connected in series to the parallel connection of the diode D 2  and resistor R 2  in the second current-voltage converter  15 A. The same operation condition as in a case of using the foregoing operational amplifier can be attained in {R1−(D2//R2) }). Thus, the characteristics similar to  FIG. 3  can be obtained and the reference voltage circuit is realized. Here, the diodes D 3  and D 4  are inserted so as to equalize the drain voltages of the N-channel transistors MN 3  and MN 4 . It should be noted that the D 1  and {R1−(D2//R2)} may be driven by any of the N-channel transistors MN 1  and MP 2 .  
         [0067]     The reference voltage circuits according to the seventh embodiment and the eighth embodiment of the present invention will be described below, with reference to  FIGS. 8 and 9 . In those embodiments, the influence of the channel length modulation is reduced. Here, the start-up circuit is omitted for the simple explanation.  
         [0068]     With reference to  FIG. 8 , in the reference voltage circuit according to the seventh embodiment of the present invention, the gates of the P-channel transistors MP 1  to MP 3  are commonly connected. A resistor R 4  is connected between the source of the P-channel transistor MP 2  and the power supply V DD , and the gate of the transistor MP 2  is connected to the drain. The sources of the P-channel transistors MP 1  and MP 3  and MP 5  are connected to the power supply V DD . The drains of the P-channel transistors MP 2  and MP 1  and MP 5  are connected to the drains of the N-channel transistors MN 2  and MN 1  and MN 3 , respectively. The gate of the transistor MP 5  is connected to the drain of the transistor MP 1 . The gate of the transistor MN 3  is connected to the drain thereof and connected to the gates of the transistors MN 1  and MN 2 . The source of the transistor MN 3  is connected through the diode D 3  to the ground. The other connections are similar to those of the first embodiment.  
         [0069]     Since the gate voltages of the P-channel transistors MP 1  to MP 3  are common, the transistor size of the P-channel transistor MP 2  is set to be larger than the transistor size of the P-channel transistor MP 1  so that the same current can be supplied. Here, the current mirror circuit composed of the P-channel transistors MP 2  and MP 1  constitutes the inverse Widlar current mirror circuit. Thus, when the current flowing through the N-channel transistor MN 2  is increased, the current flowing through the P-channel transistor MP 2  is increased by the increase. However, since the current flowing through the P-channel transistor MP 1  becomes larger than it, the increased current cannot flow through the N-channel transistor MN 1 . Thus, the drain voltage of the P-channel transistor MP 1  becomes higher, and the current flowing through the P-channel transistor MP 5  whose gate is connected to the drain of the P-channel transistor MP 1  is decreased. Therefore, the current flowing through the N-channel transistor MN 3  whose drain current is common is also decreased. The N-channel transistor MN 3  and the N-channel transistor MN 1  constitute the current mirror circuit, and the gate voltage is common in the N-channel transistor MN 1  and the N-channel transistor MN 2 . Thus, the common gate voltage of the N-channel transistors MN 1  to MN 3  is decreased, thereby decreasing the current flowing through the N-channel transistor MN 2 . That is, the current loop composed of the N-channel transistors MN 1  to MN 3  and the P-channel transistors MP 1  to MP 3  and MP 5  constitute the negative feedback circuit. Thus, the common gate voltage of the N-channel transistors MN 1  and MN 2  is controlled such that the currents of the N-channel transistor MN 1  and the N-channel transistor MN 2  become predetermined values (in this example, they are equal to each other) through the opposite wide current mirror circuit.  
         [0070]     Thus, the voltages between the respective gates and sources of the N-channel transistors MN 1  and MN 2  become equal to each other. Also, the voltage applied to the first current-voltage converter  13  having the diode D 1  is equal to the voltage applied to the second current-voltage converter  15  {(R1−D2)//R2} in which the resistor R 2  is connected in parallel to the series connection of the diode D 2  and the resistor R 1 . The same operation condition as in case of using the foregoing operational amplifier can be attained in (D1, {(R1−D2)//R2}). Thus, the characteristics similar to  FIG. 2  can be obtained and the reference voltage circuit is realized. Here, the diode D 3  is inserted such that the gate voltage of the N-channel transistor MN 3  is equal to the gate voltages of the N-channel transistors MN 1  and MN 2 . It should be noted that the diode D 1  and {(R1−D2)//R2} may be driven by any of the N-channel transistors MN 1  and MN 2 .  
         [0071]     Next, the reference voltage circuit according to the eighth embodiment will be described below with reference to  FIG. 9 . The configuration of the reference voltage circuit in the eighth embodiment is similar to that of the reference voltage circuit according to the seventh embodiment. The difference lies in the configuration that the second current-voltage converter  15  is replaced by the second current-voltage converter  15 A. The resistor R 4  is inserted between the source of the P-channel transistor MP 2  and the power supply V DD , and has the gate voltage common to the P-channel transistor MP 1 . Thus, in order to supply the same current, the transistor size of the P-channel transistor MP 2  is set to be larger than the transistor size of the P-channel transistor MP 1 . Here, the current mirror circuit composed of the P-channel transistors MP 2  and MP 1  constitutes the inverse Widlar current mirror circuit. Thus, when the current flowing through the N-channel transistor MN 2  is increased, the current flowing through the P-channel transistor MP 2  is increased in correspondence to that increase. However, since the current flowing through the P-channel transistor MP 1  becomes larger than it, the increased current cannot flow through the N-channel transistor MN 1 . Thus, the drain voltage of the P-channel transistor MP 1  becomes higher, and the current flowing through the P-channel transistor MP 5  whose gate is connected to the drain of the P-channel transistor MP 1  is decreased. Therefore, the current flowing through the N-channel transistor MN 3  whose drain current is common is also decreased. Here, the N-channel transistor MN 3  and the N-channel transistor MN 1  constitute the current mirror circuit, and the gate voltage is common in the N-channel transistor MN 1  and the N-channel transistor MN 2 . Thus, the common gate voltage of the MN 1  to MN 3  is decreased, thereby decreasing the current flowing through the N-channel transistor MN 2 . That is, the current loop composed of the N-channel transistors MN 1  to MN 3  and the P-channel transistors MP 1  to MP 3  and MP 5  constitute the negative feedback circuit. In this case, the common gate voltage of the N-channel transistors MN 1  and MN 2  is controlled such that the currents of the N-channel transistor MN 1  and MN 2  become predetermined values (in this example, they are equal to each other), through the inverse Widlar current mirror circuit. Thus, the voltages between the respective gates and sources of the N-channel transistors MN 1  and MN 2  become equal. Then, the voltage applied to the diode D 1  of the first current-voltage converter  13  is equal to the voltage applied to the circuit {R1−(D2//R2)} having the resistor R 1  connected in series to the parallel connection of the diode D 1  and resistor R 2  of the second current-voltage converter  15 A. The operation condition equal to the case of using the foregoing operational amplifier can be attained in (D1, {R1−(D2//R2)}). Thus, the property similar to  FIG. 3  can be obtained to attain the reference voltage circuit. Here, the diode D 3  is inserted such that the gate voltage of the N-channel transistor MN 3  is equal to the gate voltages of the N-channel transistors MN 1  and MN 2 . It should be noted that the D 1  and {R1−(D2//R2)} may be driven by any of the N-channel transistors MN 1  and MN 2 .  
         [0072]     The reference voltage circuits in the ninth embodiment and the tenth embodiment of the present invention will be described below with reference to  FIGS. 10 and 11 . The lower voltage operation is attained by replacing the diodes in the foregoing embodiments with bipolar transistors. The start-up circuit is omitted for the simple description.  
         [0073]     With reference to  FIG. 10 , in the reference voltage circuit according to the ninth embodiment of the present invention, sources of P-channel transistors MP 1 ′, MP 2 ′, MP 3 ′, MP 6 ′. MP 7  and MP 8 ′ are connected to the power supply V DD , and gates of the transistors except the transistor MP 7  are connected to each other. Drains of the P-channel transistors MP 1 ′, MP 2 ′, MP 3 ′, MP 6 ′ and MP 8 ′ are connected to sources of P-channel transistors MP 1 , MP 2 , MP 3 , MP 6  and MP 8 , respectively. Gates of the P-channel transistors MP 1 , MP 2 , MP 3 , MP 6 , MP 7  and MP 8  are commonly connected. The gate of the transistor MP 7  is connected to the drain thereof, and the drain of the transistor MP 6  is connected to the gate of the transistor MP 6 ′. The drains of the N-channel transistors MN 3  and MN 4  are connected to the drains of the transistors MP 7  and MP 8 , respectively. The gates of the transistors MN 3  and MN 4  are connected to each other and also connected to the drain of the transistor MN 3 . The sources of the transistors MN 3  and MN 4  are grounded. The drain of the transistor MP 6  is connected to a connector of a transistor Q 3 , and an emitter of the transistor Q 3  is grounded. The drain of the transistor MP 1  is connected to a base of the transistor Q 3  and a first current-voltage converter  13 B. The drain of the transistor MP 2  is connected to a second current-voltage converter  15 B. The first current-voltage converter  13 B has a bipolar transistor Q 1  having a grounded emitter and a collector connected to the drain of the transistor MP 1 . The second current-voltage converter  15 B has a bipolar transistor Q 2  and resistors R 1  and R 2 . A collector of the bipolar transistor Q 2  is connected to the drain of the transistor MP 2  and also grounded through the resistor R 2 . Also, an emitter of the bipolar transistor Q 2  is grounded through the resistor R 1 . A base of the transistor Q 2  is connected to the collector thereof and also connected to the base of the bipolar transistor Q 1 . The drain of the transistor MP 3  is grounded through a resistor R 3 .  
         [0074]     In  FIG. 10 , the bipolar transistor Q 2  and the bipolar transistor Q 1  constitute an inverse Widlar current mirror circuit, and a resistor R 2  is inserted between the common base and the ground (GND). Thus, as the current flowing through the cascade-connected transistors MP 2 ′ and MP 2  is increased, the current flowing through the Q 2  is increased, and the current flowing through the resistor R 2  is increased, which absorbs the increase in the current. Here, since R 2 &gt;&gt;R 1 , the increase in the voltage drop across the resistor R 1  is small, and the rise in the voltage between the terminals of the resistor R 2  is small. However, the increase in the voltage drop of the resistor R 2  becomes naturally the voltage between the base and the emitter of the bipolar transistor Q 1 , and the increase in the current flowing through the bipolar transistor Q 1  becomes the great value. Since the current flowing through the cascade transistors MP 1  and MP 1 ′ at this time is equal to the current flowing through the cascade transistors MP 2  and MP 2 ′, the current supplied to the bipolar transistor Q 1  becomes short, which decreases the collector voltage of the bipolar transistor Q 1 . Here, since a base of a bipolar transistor Q 3  is connected to the collector of the bipolar transistor Q 1 , the current flowing through the bipolar transistor Q 3  is decreased. Here, the bipolar transistor Q 3  drives the self-biased cascade current mirror circuit. Thus, the current flowing through the cascade transistors MP 2  and MP 2 ′ is decreased and settled to a predetermined current value. That is, the negative current loop is formed between the bipolar transistors Q 1  to Q 3  and the cascade current mirror circuit constituting the self-bias circuit.  
         [0075]     Assuming that the current flowing through the cascade transistors MP 2  and MP 2 ′ at this time is equal to a current I OUT  flowing through the cascade transistors MP 3  and MP 3 ′, the following equation is met.  
                     I   OUT     =         V   BE1     /     R   2       +       (       V   BE1     -     V   BE2       )     /     R   1                     =       {       V   BE1     +       (       R   2     /     R   1       )     ⁢   Δ   ⁢           ⁢     V   BE         }     /     R   2                     (   20   )             
 
 Here, the voltage V BE1  has a temperature dependency of about −1.9 mV/° C. Also, the voltage V BE2  has a temperature dependency of about −1.9 mV/° C. Assuming that both of the transistors Q 1  and Q 3  are the unit transistors, the following equation is met. 
 
Δ V   BE   =V   T ln{ I   C1 /( I   C2   −V   BE1   /R   2 )}  (21) 
 
 Here, if I C1 =I C2 , since the relation of IC1&gt;(I C2 −V BE1 /R 2 ) is always met, I C1 /(I C2 −V BE1 /R 2 )}&gt;1 is met. Also, the ln item of the equation (21) is always positive (&gt;0). That is, ΔV BE  has the positive temperature dependency even in this equation, as well known. Thus, this temperature dependency is substantially proportional to the thermal voltage V T  (its temperature dependency is 0.0853 mV/° C.). That is, the temperature dependency of the item of {V BE1 +(R 2 /R 1 )ΔV BE } in the equation (20) can be substantially canceled by setting the resistor ratio (R 2 /R 1 ) to the voltage V BE1  having the negative temperature dependency and the ΔV BE  having the positive temperature dependency and then performing the weight addition. 
 
         [0076]     Here, assuming that the temperature dependency of the item of {V BE1 +(R 2 /R 1 )ΔV BE } in the equation (20) can be canceled, the currents I C2  and I OUT  are the currents without any substantial temperature dependency except the temperature dependency caused by the resistor R 2 . At this time, the reference voltage V REF  is expressed as shown below.  
                     V   REF     =       R   3     *     I   OUT                   =       (       R   3     /     R   2       )     ⁢     {       V   BE1     +       (       R   2     /     R   1       )     ⁢   Δ   ⁢           ⁢     V   BE         }                     (   22   )             
 
 Here, assuming that the voltage V BE2  is 580 mV at the room temperature, it could be understood that the voltage V BE1  is 620 mV at the room temperature and {V BE1 +(R 3 /R 1 )ΔV BE } is similarly about 1.2V. Also, since the resistor ratio (R 3 /R 2 ) does not have the temperature dependency, the reference voltage V REF  is also the voltage where the temperature dependencies are canceled. Here, since the resistor ratio (R 3 /R 2 ) can be optionally set, if 1&lt;(R 3 /R 2 ) is set, the reference voltage V REF  becomes the voltage higher than 1.2V. If 1&gt;(R 3 /R 2 ) is set, the reference voltage V REF  becomes the voltage lower than 1.2V. Those facts are similar to the case of the conventional technique. In particular, in the case of setting 1&gt;(R 3 /R 2 ) where the reference voltage V REF  is the voltage lower than 1.2V, the power supply voltage is reduced. For example, when V REF =0.8V is set, since the cascade current mirror circuit is used to bias, the power supply voltage becomes slightly higher. Thus, it can be operated from the power supply voltage of about 1.2V. 
 
         [0077]     Next, with reference to  FIG. 11 , the reference voltage circuit according to the tenth embodiment of the present invention is similar to the reference voltage circuit according to the ninth embodiment. The difference lies in the configuration where the second current-voltage converter  15 B is replaced by a second current-voltage converter  1 C. In the second current-voltage converter  1 C, one end of a resistor R 1  is connected to a drain of a P-channel transistor MP 2  and a base of a transistor Q 1 . The other end of the resistor R 1  is grounded through a resistor R 2  and also connected to a collector of a transistor Q 2 . A base of the transistor Q 2  is connected to a collector, and an emitter is grounded.  
         [0078]     In  FIG. 11 , the bipolar transistor Q 2  and the bipolar transistor Q 1  constitute an inverse Widlar current mirror circuit, and the resistor R 2  is inserted between the base of the bipolar transistor Q 2  and the ground (GND). Thus, as the current flowing through the cascade transistors MP 2  and MP 2 ′ is increased, the current flowing through the Q 2  is increased, and the current flowing through the resistor R 2  is increased, which absorbs the increase in the current. Here, since R 2 &gt;&gt;R 1 , the increase in the voltage drop of the resistor R 1  is small. Also, since the voltage between the base and the emitter of the bipolar transistor Q 2  is logarithmically compressed with respect to the flowing current, the voltage between the terminals of the resistor R 2  is not substantially increased. However, the increase in the voltage drop of the resistor R 2  becomes naturally the voltage between the base and the emitter of the bipolar transistor Q 1 , and the increase in the current flowing through the bipolar transistor Q 1  becomes the great value. Since the current flowing through the cascade transistors MP 1 , MP 1 ′ at this time is equal to the current flowing through the cascade transistors MP 2  and MP 2 ′, the current supplied to the bipolar transistor Q 1  becomes short, which decreases the collector voltage of the bipolar transistor Q 1 . Here, since a base of a bipolar transistor Q 3  is connected to the collector of the bipolar transistor Q 1 , the current flowing through the bipolar transistor Q 3  is decreased. Here, the bipolar transistor Q 3  drives the self-biased cascade current mirror circuit. Thus, the current flowing through the cascade transistors MP 2  and MP 2 ′ is decreased and settled to a predetermined current value. That is, the negative current loop is formed between the bipolar transistors Q 1  to Q 3  and the cascade current mirror circuit constituting the self-bias circuit.  
         [0079]     At this time, assuming that the current flowing through the cascade transistors MP 2  and MP 2 ′ is equal to a current I OUT  flowing through the cascade transistors MP 3  and MP 3 ′, the following equation is met.  
                     I   OUT     =       (       V   BE1     -     V   BE2       )     /     R   1                   =     Δ   ⁢           ⁢       V   BE     /     R   1                       (   23   )             
 
 Here, the voltage V BE1  has a temperature dependency of about −1.9 mV/° C. Also, the voltage V BE2  has a temperature dependency of about −1.9 mV/° C. Here, assuming that both of the Q 1  and Q 2  are the unit transistors, the following equation is met. 
 
Δ V   BE   =V   T ln{I C1 /( I   C2   −V   BE1   /R   2 )}  (24) 
 
 Here, if I C1 =I C2 , since always I C1 &gt;(I C2 −V BE2 /R 2 ), I C1 /(I C2 −V BE2 /R 2 )}&gt;1 is established. Also, the ln item of the equation (24) is always positive (&gt;0). That is, the following equation is met. 
 
Δ V   BE   =V   T ln[1/{1− V   BE2 /( I   C2   R   2  )}]  (24′) 
 
 The equation (23) is different in form from the equation (20). The voltage difference ΔV BE  shown in the equation (24′) does not have the positive temperature dependency. Here, the fact that the voltage difference ΔV BE  does not substantially have the temperature dependency will be described. 
 
         [0080]     In the equation (24′), the thermal voltage V T  has the positive temperature dependency (+0.0853 mV/° C.) proportional to the temperature. Also, the voltage V BE2  in [] of the equation (24′) has the negative temperature dependency of about −1.9 mV/° C. For the easy explanation, assuming that the temperature dependency of the resistor R 2  is small to an ignorable extent, the product of I C2 R 2  becomes the value exceeding the V BE2  (I C2 R 2 &gt;V BE2 ) since R 2 &gt;&gt;R 1 . Thus, ln[1/{1−V BE2 /(I C2 R 2 )}] becomes the value that the value of 1/{1−V BE2 /(I C2 R 2 )} is greater than 1, for example, 2 (in case of I C2 R 2 =0.5V BE2 ) or 3 (in case of I C2 R 2 =667V BE2 ). Then, when the temperature is changed with the thus-set value as the center, it is varied. This variation region lies in the region where the inclination is relatively large in the function of ln[1/{1−V BE2 /(I C2 R 2 )}]. For example, even if the desirable current I C2  does not have the temperature dependency, the temperature dependency of the voltage V BE2  changes {1−V BE2 /(I C2 R 2 )} depending on the temperature. That is, with this temperature dependency, [1−V BE2 /(I C2 R 2 )}] has the negative temperature dependency. Therefore, ln[1/{1−V BE2 /(I C2 R 2 )}] also has the negative temperature dependency. Thus, as the temperature is decreased, it becomes large, and as the temperature is increased, it becomes small.  
         [0081]     Here, the current I C2  is a sum of the current flowing through the unit diode D 2  and the current flowing through the resistor R 2  connected in parallel to the unit transistor Q 2 . Thus, since the current I C1  flowing through the unit transistor Q 1  and the current I C2  are controlled to be equal to each other, the temperature dependency of the I C2  does not substantially have the temperature dependency because the temperature dependency of the current flowing through the resistor R 2  (the negative temperature dependency based on the voltage V BE2  having the negative temperature dependency) and the temperature dependency of the current flowing through the resistor R 2  (the positive temperature dependency opposite to the voltage V BE2 ) are canceled. At this time, the temperature dependencies are substantially canceled. Thus, the value [1/{1−V BE2 /(I C2 R 2 )}] in [] of ln[1/{1−V BE2 /(I C2 R 2 )}] becomes greater as the temperature becomes lower, and it becomes smaller as the temperature becomes higher. Here, by setting the values of the resistors R 1  and R 2 , it is possible to absorb the variation caused by the temperature of the ln[] so as to substantially cancel the positive temperature dependency (the temperature dependency is 0.0853 mV/° C.) of the thermal voltage V T . That is, the voltage difference ΔV BE  becomes the voltage that the temperature dependencies are substantially canceled.  
         [0082]     At this time, the reference voltage V REF  is represented as shown below.  
                     V   REF     =       R   3     *     I   OUT                   =       (       R   3     /     R   1       )     ⁢   Δ   ⁢           ⁢     V   F                     (   25   )             
 
 Also, since the resistor ratio (R 3 /R 1 ) does not have the temperature dependency, the reference voltage V REF  is also the voltage that the temperature dependencies are canceled. Here, the resistor ratio (R 3 /R 1 ) can be optionally set, and the voltage difference ΔV BE  is the voltage from about several 10 mV to one hundred and several 10 mV. In such a case, by setting (R 3 /R 1 )&gt;1 ((R 3 /R 1 )&gt;1), the reference voltage V REF  can be set to the voltage lower than 1.0V. In this case, the power supply voltage can be dropped. For example, when the reference voltage V REF =1.0V is set, the reference voltage circuit can operate from the power supply voltage of about 1.2V. 
 
         [0083]     As mentioned above, the circuits shown in  FIGS. 10 and 11  have the intention of suppressing the influence of the channel length modulation, and show the case of the self-biasing in the cascade current mirror circuit. Of course, the method of using the above-mentioned cascade current mirror circuit can be applied to all of the reference voltage circuits as explained above. Also, they correspond to the case of bi-CMOS where the N-channel transistors and the P-channel transistors are used. However, they can be attained even by the bipolar process if the PNP transistors can be formed in addition to the NPN transistors.  
         [0084]     Finally, the operational amplifier can be omitted when the self-biasing method is applied to the circuit of the conventional example shown in  FIG. 1 . However, in order to make the current densities between the diodes different, about 10 to 100 diodes D 2  are required to be connected in parallel. Thus, there is no advantage in a chip area. However, the self-biasing method shown in  FIGS. 4 and 5  is known because it is described in the technical seminar distribution information (March 2002) written by this inventor, or, in Design Wave Magazine 2002 August (pp. 153-158).  
         [0085]     The circuit shown in  FIG. 12  is configured when the self-biasing method shown in  FIGS. 6 and 7  is applied to the circuit of the conventional example shown in  FIG. 1 . Similarly to the operation of the circuits shown in  FIGS. 6 and 7 , the source voltages of the MOS transistors MP 1  and MP 2  are controlled so as to be equal to each other, even in  FIG. 12 , and the equation (13) is obtained, and the reference voltage circuit can be attained. Moreover, the circuit shown in  FIG. 13  is configured when the self-biasing method shown in  FIGS. 8 and 9  is applied. Similarly to the operation explanations of the circuits shown in  FIGS. 8 and 9 , with the self-biasing through the opposite wide current mirror circuit, even in  FIG. 13 , the source voltages of the MOS transistors MP 1  and MP 2  are controlled so as to be equal to each other, and the equation (13) is obtained, and the reference voltage circuit can be attained.  
         [0086]     According to the present invention, the chip area can be reduced. This is because even the use of only two diodes can constitute the circuit.  
         [0087]     Also, according to the present invention, it can be operated at the low voltage. This is because the output voltage can be set to any voltage value of 2V or less.