Abstract:
An infrared reflectance densitometer (IRD) sensor which utilizes four blocks each of which generates an element of a given equation and a fifth block which generates an output voltage based on the given equation. The IRD sensor eliminates a problem known as hunting.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to an infrared reflectance densitometer (IRD) sensor, and more particularly, to an IRD sensor which is used in a xerographic copying or printing system. The IRD sensor of this invention eliminates noise and hunting problem associated with prior art IRD sensors. 
     Referring to FIG. 1, there is shown a prior art xerographic Infrared Reflectance Densitometer (IRD) sensor 10. The IRD sensor 10 is utilized to measure the density of toner deposited on a photoconductor 12 of a xerographic copying or printing system. For the purpose of simplicity, hereinafter, a &#34;xerographic copying or printing system&#34; will be referred to as &#34;xerographic system&#34;. Typically, a latent image is created on the surface of the photoconductor 12 by a raster output scanner (not shown). After the latent image is created, it has to be developed. Developing a latent image is defined as depositing toner on the latent image. The IRD sensor 10 measures the density of the toner deposited on the photoconductor. 
     The prior art IRD sensor 10 comprises a Light Emitting Diode (LED) light source 14, a photodiode 16, an automatic Gain Control (AGC) 18, an adder 20, a buffer 22, a comparator 24, a sample and hold switch 26 and a capacitor 28. The LED 14 emits a light beam 30 and shines it on the photoconductor 12. Depending on if the surface of the photoconductor 12 is bare (no toner) or it has toner, the light beam 30 will be reflected or partially absorbed and partially reflected onto the photodiode 16 respectively. It should be noted that when the photoconductor 12 is bare, majority of the light beam will be reflected onto the photodiode 16 and a minimal percentage of the light beam might be scattered. However, for the purpose of this discussion, hereinafter, it will be assumed that when the photoconductor 12 is bare, it will reflect all the light beam onto the photodiode 16. 
     When the surface of the photoconductor 12 has toner, depending on the amount of toner, the light beam will be absorbed at a different rate and therefore the intensity of the light beam reflected onto the photodiode 16 varies with the amount of toner. 
     The IRD sensor 10 converts the intensity of the light beam received through the photodiode 16 into an output voltage V OUT  to be compared against a lookup table to indicate the density of toner on the photoconductor. 
     The photodiode 16 creates a current I PD  based on the received light beam. The current I PD  will be sent to the AGC 18 via line 32. The AGC 18 which contains a current to voltage converter, amplifies the I PD  current to signal current I SIG  and converts the signal current I SIG  into a voltage V SIG . Since the IRD sensor 10 has to measure a wide range of toner density, the signal current I SIG  and therefore the voltage V SIG  will have a wide dynamic range. The AGC 18 while generating V SIG , compresses V SIG  in order to reduce the size of the voltage V SIG  while covering a wide dynamic range. The voltage V SIG  is transferred to adder 20 via connection line 34, therefrom to buffer 22 via connection line 36 and eventually to the output of the buffer 22 as output voltage V OUT . Referring to FIG. 2, the output voltage V OUT  has a transfer curve 40 as shown by dashed lines with respect to I SIG . However, this transfer curve 40 is not a curve to be used to determine the density of the toner. The curve 42, shown by solid line, is a reference curve that is used to determine the density of the toner. 
     Therefore, referring to both FIGS. 1 and 2, the IRD sensor 10 has to be calibrated to move the transfer curve 40 of the output voltage V OUT  to match the reference curve 42. In order to calibrate the IRD sensor 10, it is necessary to adjust the driving current of the LED 14 and the gain of the AGC 18 to move the starting point a of the curve 40 to reference voltage V REF  and the ending point b of the curve 40 to maximum voltage V MAX . The reference voltage V REF  is a given voltage which is the starting voltage on the reference curve 42 and the maximum voltage V MAX  is a predetermined voltage which is the maximum voltage (end point) on the reference curve 42. Both the reference voltage V REF  and the maximum voltage V MAX  are determined by the requirements of the xerographic system. 
     The first step of the calibration is to turn Off the light source 14. While there is no light (dark) the photodiode has a leakage current I DARK . The leakage current will be converted by the AGC 18 to voltage V SIG  and will be transferred to the output voltage V OUT . 
     The output voltage is sent to the comparator 24 via line 23. The comparator 24 also receives a reference voltage V REF . The comparator 24, compares the output voltage V OUT  with the reference voltage V REF  and sends out a signal V DIF . Depending on if the Output voltage is higher or lower, V DIF  will have a negative value or a positive value respectively. The sample and hold switch 26 has to be closed for this step of calibration. Since the sample and hold switch is closed, V DIF  will be transferred to the adder 20 and also will be stored in the capacitor 28. The adder 22 will add or subtract the V DIF  to/from the output of the AGC 18 depending on if V DIF  is positive or negative respectively. The result will then be sent to the buffer 22 and onto the output voltage V OUT . Loop A, which comprises comparator 24, sample and hold switch 26, adder 20 and buffer 22, will force the output to be substantially equal to the reference voltage V REF . This step of the calibration moves the starting point a of the transfer curve 40 to V REF . 
     For the next step in calibration, the sample and hold switch 26 is opened, the LED 14 is turned On and the driving current of the LED 14 is increased to increase the intensity of the light beam 30. The driving current of the LED 14 is increased by counter 44 which is controlled by comparator 46. Comparator 46 receives V OUT  via line 48 and V COARSE  from a voltage source via line 50. If V OUT  is less than V COARSE , comparator 46 will send out a &#34;0&#34; and if V OUT  is equal or higher than V COARSE , comparator 46 will send out a &#34;1&#34;. The output of comparator 46 is connected to counter 52 via line 54 and to counter 44 through an inverter 56. Every time calibration is required, counter 44 is activated by a calibration pulse Cal which is originated in a microprocessor (not shown) and is delivered via line 58. Counter 44, which is connected to the driver circuit of the LED 14 via line 60, gradually increases the current of the LED 14 as its count increases. 
     It should be noted that during the calibration, the photoconductor 12 is bare and therefore the light beam 30 will be reflected onto the photodiode 16. During this step, as the intensity of the light beam 30 is increased, the current generated by the photodiode 16 is also increased causing the compressed V SIG  and as a result the output voltage V OUT  to increase. 
     It should be noted that during this step and during the normal operation of the IRD sensor 10, the value V DIF  (from the previous step), stored in the capacitor 28, is always added to the to compressed V SIG  from AGC 18. 
     As the current of the LED 14 is increased, the output voltage V OUT  will be increased. Once the output voltage V OUT  reaches V COARSE , the output of comparator 46 changes to &#34;1&#34; which stops the counter 44 and starts counter 52. V COARSE  is the voltage of a point on the reference curve 42. V COARSE  is selected to have a value which is between V REF  and a predetermined maximum output voltage V MAX . V COARSE  is selected to allow large adjustments of calibration to be performed by increasing the driving current of the LED 14 and fine adjustments of calibration to be performed by increasing the gain of AGC 18. 
     Once the counter 44 is stopped, the current of the LED 14 will be fixed and once the counter 52 is started, the gain of the AGC 18 will be increased until the output voltage V OUT  reaches the maximum output voltage V MAX . When V OUT  reaches V MAX , counter 52 will be stopped by comparator 62 which receives V OUT  via line 64 and V MAX  from a voltage source via line 66. Comparator 62 is connected to counter 52 through inverter 68. If V OUT  is less than V MAX , comparator 62 will send out a &#34;0&#34; and if V OUT  is equal or higher than V MAX , comparator 62 will send out a &#34;1&#34;. As a result, during the time that V OUT  is less than V MAX , the counter 52 receives a &#34;1&#34; and when V OUT  reaches V MAX , the counter receives a &#34;0&#34; as a stop signal. 
     This step of the calibration (having a fixed LED current and increasing the gain of AGC 18 until V OUT  reaches V MAX ) moves the ending point b of the transfer curve 40 to V MAX . Once V OUT  reaches V MAX , the IRD sensor is calibrated. After the IRD sensor 10 is calibrated, the driving current of the light source and the gain of the AGC 18 will be fixed for normal operation. Therefore, during the normal operation of the IRD sensor 10, the driving current of the light source 14 and the gain of the AGC 18 will be kept fixed at the values of the calibration. It should be noted that once the driving current of the light source is fixed, the intensity of the light beam is also fixed. 
     During normal operation, the output voltage V OUT  of the calibrated IRD sensor 10 creates an output voltage V OUT  with a transfer curve similar to reference curve 42. The transfer curve of the output voltage V OUT  is utilized to be compared against a lookup table to determine the density of the toner on the photoconductor 12. The reference curve 42 of FIG. 2 is based on the following equation: 
     
         V.sub.OUT =V.sub.REF +K (I.sub.SIG +I.sub.DARK).sup.1/2 -(I.sub.DARK).sup.1/2 !.                                  (1) 
    
     Where K is a gain factor of AGC 18. 
     The IRD sensor 10 of FIG. 1 has several problems. One problem is the noise that is introduced into the circuit through the sample and hold switch 26. By closing and opening the sample and hold switch 26 during the calibration, the noise caused by opening switch 26 will disturb the calibration of the starting point V REF . Therefore, the IRD sensor 10 of FIG. 1 does not have a precise calibration. 
     Another problem is that the output voltage V OUT  is dependent on I DARK , the leakage current of the photodiode 16, which significantly varies during the normal operation of the IRD sensor 10. Therefore, due to the variations of I DARK , the output voltage V OUT  varies. 
     However, the major problem of the IRD sensor 10 of FIG. 1 is a phenomenon known as &#34;hunting&#34;. Hunting occurs during the power up calibration and also during self calibration. The IRD sensor 10 occasionally performs a self calibration in order to compensate for the performance deterioration due to dirt contamination and other factors. During each calibration, the IRD sensor 10 tries to adjust the starting point and as it adjusts the staring point, the maximum voltage V MAX  will be disturbed and as the sensor tries to adjust the maximum voltage V MAX , the starting point will be disturbed. As a result, the IRD sensor 10 of FIG. 1 will fall into a loop trying to obtain a stable starting point V REF  and an ending point V MAX . This phenomenon is called &#34;hunting&#34;. 
     Hunting occurs due to the fact that during the first part of the calibration, the gain of AGC 18 is set to a certain (first) value. Therefore, V DIF  stored in capacitor 28 is generated based on the first value of the gain of AGC 18. However, in the second portion of the calibration, after the driving current of the LED is fixed, the gain of the AGC is increased. In the second portion of the calibration, the gain of AGC 18 is changing, but V DIF  which is being added to V SIG  is the V DIF  that was generated from the first value of the gain of AGC 18. Therefore, this circuit does not provide a precise calibration. 
     It is an object of this invention to furnish an IRD sensor which eliminates the hunting phenomenon, reduces noise and provides an output voltage V OUT  with a precise calibration. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, there is disclosed an infrared reflectance densitometer (IRD) sensor which eliminates a phenomenon known as hunting, reduces noise and provides an output voltage with a precise calibration. The IRD sensor of this invention has four distinct blocks each of which generates one of the elements of a given equation and a fifth block which generates an output voltage V OUT1  based on the given equation. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a prior art IRD sensor; 
     FIG. 2 shows a curve (shown by solid line) used to determine the density of the toner and a transfer curve of the output voltage (shown by dashed line) of the IRD sensor of FIG. 1; 
     FIG. 3 shows a block diagram of the IRD sensor of this invention; 
     FIG. 4 shows the circuit diagram of blocks 80 and 90 of FIG. 3; 
     FIG. 5 shows the circuit diagram of blocks 82, 84 and 86 of FIG. 3; and 
     FIG. 6 shows the circuit diagram of block 88 of FIG. 3. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 3 there is shown an IRD sensor 70 of this invention. In FIG. 3, a LED light source 72 emits a light beam 74 which is shone onto a photoconductor 76. The photoconductor 76 will reflect the light beam 74 or absorb a portion of the light beam 74 and reflect the remaining light beam 74 depending on if the photoconductor is bare or it has toner respectively. The reflected light beam will shine on a photodiode 78. 
     The IRD sensor 70 of this invention is designed to create the equation (1) 
     
         V.sub.OUT =V.sub.REF +K (I.sub.SG +I.sub.DARK).sup.1/2 -(I.sub.DARK).sup.1/2 !.                                  (1) 
    
     The IRD sensor 70 has five distinct blocks 80, 82, 84, 86 and 88 each of which generates one of the elements of the equation (1). The IRD sensor 70 of this invention also has an additional block 90 for controlling the current of the LED 72. The photodiode 78 of block 80 generates a current I PD1 . Block 80 amplifies the current I PD1  and generates I s  which is equivalent to I SIG  of the equation (1). Block 82 which does not have any connection to the photodiode 78 generates I D  which is independent of the leakage current of the photodiode 78. I D  is the equivalent of I DARK  of equation (1). Block 84 uses I S1 , a mirrored current of I S , from block 80. It should be noted that current I S1  can be equal to I S  or can be equal to amplified I S . Block 84 also uses I D1 , a mirrored current of I D  from block 82, to generate voltage V 1 . Block 86 uses I D2 , a mirrored current of I D  from block 82, to generate voltage V 2 . Currents I D1  and I D2  are equal to I D . 
     Where V 1  is: 
     
         V.sub.1 =-K.sub.1 (I.sub.S1 +I.sub.D1).sup.1/2 +V.sub.t    (2) 
    
     and V 2  is: 
     
         V.sub.2 =-K.sub.1 (I.sub.D2).sup.1/2 +Vt                   (3). 
    
     Where K 1  is the gain factor in blocks 84 and 86. The elements of equations 2 and 3 will be described in great detail hereinafter. 
     Both voltages V 1  and V 2  are used in block 88 which also receives a reference voltage V REF1  from an external source. Block 88 generates an output voltage V OUT1  which is equal to: 
     V OUT1  =V REF1  +V 2  -V 1  =V REF1  +K 1   (I S1  +I D1 ) 1/2  -(I D2 ) 1/2  !.                 (4)=(1) 
     Referring to FIG. 4, there is shown a circuit diagram of the blocks 80 and 90 of the IRD sensor 70 of this invention. Block 80, which is responsible for generating I S , receives the signal I PD1  from the photodiode 78. In block 80, the cathode of the photodiode 78 is connected to the inverting input (-) of the op-amp 100 and anode of the photodiode 78 is connected to the non-inverting input (+) of the op-amp 100 and to the inverting input of op-amp 102 through node 104. The inverting input of the op-amp 100 is also connected to the output of the op-amp 100 via resistor R 1  and the capacitor C 1  which are parallel to each other. Node 104 is connected to node 106. Node 106 is a node between two resistors R 2  and R 3 . Resistor R 2  is connected between a voltage source V S1  and node 106 and the resistor R 3  is connected between the node 106 and ground. The output of the op-amp 100 is connected to the non-inverting input of the op-amp 102 through resistor R 4 . The non-inverting output of the op-amp 102 is also connected to the drain of the transistor T 1  via line 108. The gate of transistor T 1  is connected to the output of the op-amp 102 and the source of the transistor T 1  is connected to ground. 
     In block 80, the voltage source V S1  creates a current through the resistors R 2  and R 3  which in turn create a voltage V B  at node 106 to be used as a bias voltage for op-amps 100 and 102. The bias voltage V B  is connected to the non-inverting input of op-amp 100 and to the inverting input of the op-amp 102 through node 106 which is the same as node 104. The photodiode 78 generates a current I PDI  and supplies it to the op-amp 100. The op-amp 100 generates an output voltage which is: 
     
         V.sub.01 =V.sub.B +R.sub.1 ·I.sub.PD1. 
    
     Since the non-inverting input of the op-amp 102 has a large impedance, it does not draw any current and since the op-amp 102 is in linear mode, the voltage of the non-inverting input is forced to be equal to the voltage of the inverting input (V B ). Therefore, the voltage difference across the resistor R4 is: 
     
         V.sub.01 -V.sub.B =(V.sub.B +R.sub.1 ·I.sub.PD1)-V.sub.B =R.sub.1 ·I.sub.PD1. 
    
     Thus, the current I 1  across resistor R 4  is: 
     
         I.sub.1 =(R.sub.1 /R.sub.4)·I.sub.PD1. 
    
     Therefore, the current I 1  is the amplified version of current I PD1 . 
     Since the non-inverting input of op-amp 102 does not draw any current, the acurrent I 1  across resistor R 4  will flow into the drain of the transistor T 1  via the connection line 108. The gate of the transistor T 1  is also connected to the gate of transistors T 2 . The gates of both transistors T 1  and T 2  are connected to the gate of the transistor T 3  through a switch S I  and the gate of the transistor T 3  is connect to ground through a switch S 2 . The source of both transistors T 2  and T 3  are connected to the ground and the drains of the transistors T 2  and T 3  are connected to each other at node 110. Node 110 is connected to the source of transistor T 7  of block 84 through line 112 (FIG. 5). 
     In block 80, current I 1  is mirrored by transistors T 2  and T 3 . Each one of the transistors T 2  and T 3  has a different size to amplify the mirrored current by a different factor. Depending on the required current, either transistors T 2  or both transistors T 2  and T 3  will be selected as a mirror transistor. The selection of the transistors T 2  and T 3  is done by a counter 114. 
     It should be noted that for the purpose of simplicity, in FIG. 4, only two mirror transistors T 2  and T 3  are shown. However, depending on the design requirements of IRD sensor 70, the number of mirror transistors can be increased or decreased to provide more or less flexibility in selecting gain of the mirrored current respectively. 
     Switches S 1  and S 2  are controlled by a counter 114. The output 116 of counter 114 is connected to switch S 1  directly and to switch S 2  through inverter 118. With this configuration, when transistor T 3  is needed, counter 114 causes switch S 1  to close and switch S 2  to open. This causes the gate of transistor T 3  to be connected to the gate of transistor T 2 . However, when T 3  is not needed, counter 114 will open switch S 1  and close switch S 2 . This will cause the gate of transistor T 3  to be disconnected from transistor T 2  and grounded. This in turn will cause transistor T 3  to be inactivated. 
     Counter 114 is activated by a signal from comparator 120. In block 90, comparator 120 receives V OUT1  via line 122 and V COARSE1  from a voltage source via line 124. It should be noted that in this invention, V COARSE1 , V MAX1  and V REF1  are equivalent to V COARSE , V MAX  and V REF  of prior art respectively. If V OUT1  is less than V COARSE1 , the comparator 120 will send out a &#34;0&#34; and if V OUT1  is equal or higher than V COARSE1 , the comparator 120 will send out a &#34;1&#34;. The output of the comparator 120 is connected to counter 114 via line 126 and also connected to counter 128 through an inverter 130. 
     Every time calibration is required, counter 128 is activated by a calibration pulse Ca11 which is originated in a microprocessor (not shown) and delivered via line 132. Counter 128, which is connected to the driver circuit of the LED 72 via line 134, gradually increases the current of the LED 72. As the current of the LED 72 is increased, the output voltage V OUT1  will be increased. Once the output voltage V OUT1  reaches V COARSE1 , the output of comparator 120 changes to &#34;1&#34; which stops the counter 128 and starts counter 114. 
     At this time the current of the LED 72 will be fixed and the counter 114 closes switch S 1  and opens switch S 2  to activate transistor T 3 . If the circuit has more transistors, counter 114 gradually activates one transistor at a time, as its count increases. Counter 114 keeps counting until it receives a stop signal from comparator 136. Comparator 136, which receives V OUT1  via line 138 and V MAX1  from a voltage source via line 140, is connected to counter 114 through inverter 142. If V OUT1  is less than V MAX1 , the comparator 136 will send out a &#34;0&#34; and if V OUT1  is equal or higher than V MAX1 , the comparator 136 will send out a &#34;1&#34;. As a result, during the time that V OUT1  is less than V MAX1 , the counter receives a &#34;1&#34; and when V OUT1  reaches VMAX 1 , the counter receives a &#34;0&#34; as a stop signal. 
     The mirrored current from either T 2  or T 2  and T 3  is the I S1  of equation (4) which is the same as equation (1). Transistors T 2  or T 3  create a current sink in which if only T 2  is On, I S1  will be equal to I S  and if both transistors T 2  and T 3  are On, I S1  will be equal to a amplified I S . When both transistors T 2  and T 3  are On, the current I S1  is increased by the amount of current added by transistor T 3 . 
     In this invention, the leakage current of the photodiode 78 is substantially minimized. The non-inverting input of op-amp 100 is connected to the bias voltage V B  and therefore the inverting input of op-amp 100 is also forced to be substantially equal to the bias voltage V B . As a result, both terminals (cathode and anode) of the photodiode 78 have substantially equal voltages. This will substantially reduce the leakage current of the photodiode 78 and reject the common mode noise picked up by the photodiode 78. Typically, the common mode noise is picked up by a photodiode when there is a voltage difference between its two terminals. 
     Referring to FIG. 5, there is shown a circuit diagram of blocks 82, 84 and 86. In block 82, I D  is being generated independent of the leakage current of photodiode 78. A variable resistor 150, which is connected to a voltage source V S2  and transistor T 4 , creates I D  which is equivalent to I DARK . The gate of transistor T 4  is connected to its drain and the drain of transistor T 4  is connected to the variable resistor 150 and the source of transistor T 4  is connected to ground. 
     Since I D  is needed for two different blocks 84 and 86, the I D  is duplicated by two mirror Transistors T 5  and T 6 . The gate of transistor T4 is connected to the gates of mirror transistors T5 and T6. Sources of mirror transistors T5 and T6 are both connected to ground. The drain of mirror transistor T5 is connected to the source of transistor T7 of block 84 and the drain of mirror transistor T6 is connected to the source of transistor T8 of block 86. Mirror transistor T 5  creates a current sink for block 84 and the mirror transistor creates a current sink for block 86. The mirror transistors T 5  and T 6  force the current I D1  on the connection line 152 (block 84) and the current I D2  on the connection line 154 (block 86) to be identical to the I D  from the variable resistor 150. Therefore, currents I D1  and I D2  are substantially equal. 
     In Block 84, resistor R 5  is connected between the voltage source V S2  and the gate of transistor T 7  and resistor R6 is connected between the gate of transistor T 7  and ground. The drain of transistor T 7  is connected to the voltage source V S2  and the source of the transistor T 7  is connected to the non-inverting input of op-amp 160, to the drain of mirror transistor T 5 , and to the drains of mirror transistors T 2  and T 3  of block 80 through the connection lines 162, 152 and 112 respectively. The gate of the transistor T 7  is also connected to the gate of the transistor T 8  of the block 86. The inverting input of op-amp 160 is connected to its output which is connected to block 88. 
     In block 84, the current on the connection line 112 is I S1  and the current on the connection line 152 is I D1 . Current I S1  flows into the current sink of block 80 and current I D1  flows into the current sink of block 82. Since the op-amp 160 is used as a buffer, it does not draw any current. Therefore, the current of the source (shown as the connection line 164) of the transistor T 7  is equal to: I S1  +I D1 . The gate to source voltage V GS7  of the transistor T 7  is given by: 
     
         V.sub.GS7 =K.sub.1 (I.sub.SOURCE7).sup.1/2 +V.sub.t 
    
     and since 
     
         I.sub.SOURCE7)=I.sub.S1 +I.sub.D1 
    
     and the gate voltage of the transistor T 7  is V B1  then 
     
         V.sub.GS7 =K.sub.1 (I.sub.S1 +I.sub.D1).sup.1/2 +V.sub.t. 
    
     Therefore, the source voltage of transistor T 7  is: 
     
         V.sub.S7 =- K.sub.1 (I.sub.S1 +I.sub.D1).sup.1/2 +V.sub.t !+V.sub.B1. 
    
     Where K 1  is the gain factor of transistor T 7 . 
     Since the non-inverting input of the op-amp 160 is connected to the source of the transistor T 7 , it has the same voltage as the source voltage V S7  of the transistor T 7 . Therefore, the output voltage V 1  of the op-amp 160, which is connected to the inverting input of op-amp 160 is substantially equal to the non-inverting input voltage of op-amp 160 which is equal to the source voltage of transistor T 7  : 
     
         V.sub.1 =V.sub.S7 =- K.sub.1 (I.sub.S1 +I.sub.D1).sup.1/2 +V.sub.t !+V.sub.B1. 
    
     In block 86, the drain of transistor T 8  is connected to the voltage source V S2  and its source is connected to the non-inverting input of op-amp 170 and to the drain of mirror transistor T 6 . The inverting input of op-amp 170 is connected to its output which is connected to block 88. Since the op-amp 170 is used as a buffer, it does not draw any current. Therefore, the source current of the transistor T 8  is: I SOURCE8  =I D2 . Current I D2  flows into the current sink of block 82 to be limited to current I D . The gate to source voltage of transistor T 8  is: 
     
         V.sub.GS8 =K.sub.1 (I.sub.D2).sup.1/2 +V.sub.t 
    
     and since the gate voltage of transistor T 8  is V B1  : the source voltage of transistor T 8  is: 
     
         V.sub.S8 =- K.sub.1 (I.sub.D2).sup.1/2 +V.sub.t !+V.sub.B1. 
    
     Where K 1  is the gain factor of transistor T 8 . It should be noted that the gain factor K 1  of both transistors T 7  and T 8  are equal. 
     Since the non-inverting input of the op-amp 170 is connected to the source of the transistor T 8 , it has the same voltage as the source voltage V S8 . Therefore, the output voltage V 1  of the op-amp 170, which is connected to the inverting input of op-amp 170 is substantially equal to the non-inverting input voltage of op-amp 170 which is equal to the source voltage of transistor T 8  : 
     
         V.sub.2 =V.sub.S8 =- K.sub.1 (I.sub.D2).sup.1/2 +V.sub.t! +V.sub.B1. 
    
     Referring to FIG. 6, there is shown a circuit diagram of block 88 of the IRD sensor 70 of FIG. 3. In block 88, the inverting input of op-amp 172 is connected to its output through resistor R 7  and to the output of the op-amp 160 through resistor R 8 . The non-inverting input of the op-amp 172 is connected to the output of the op-amp 170 through resistor R 9  and to a voltage source V REF1  through resistor R 10 . The voltage source V REF1  generates the reference voltage which is required by the xerographic system. Therefore, the voltage of the non-inverting input of the op-amp 172 is: V REF1  +V 2  and the voltage of the inverting input of the op-amp is: V 1 . 
     In block 88, the op-amp 172 is used as a subtractor which subtracts the non-inverting input voltage from the inverting input voltage. As a result, the output voltage of the op-amp 172 is: 
     
         V.sub.OUT1 =V.sub.REF1 +V.sub.2 -V.sub.1. 
    
     Since 
     
         V.sub.1 =V.sub.S7 =- K.sub.1 (I.sub.S1 +I.sub.D1).sup.1/2 +V.sub.t !+V.sub.B1 
    
     and 
     
         V.sub.2 =V.sub.S8 =- K.sub.1 (I.sub.D2).sup.1/2 +V.sub.t !+V.sub.B1. 
    
     Therefore, 
     
         V.sub.OUT1 =V.sub.REF1 - K.sub.1 (I.sub.D2).sup.1/2 +V.sub.t !+V.sub.B1 + K.sub.1 (I.sub.S1 +I.sub.D1).sup.1/2 +V.sub.t !-V.sub.B1 
    
     
         V.sub.OUT1 =V.sub.REF1 +K.sub.1  (I.sub.S1 +I.sub.D1).sup.1/2 -(I.sub.D2).sup.1/2 !.                                    (1) 
    
     The output voltage of the IRD sensor 70 of FIG. 3, eliminates the hunting problem and the noise problem associated with the sample and hold switch 26 of FIG. 1. The IRD sensor 70 of this invention, also creates a precise curve based on equation 1. 
     Furthermore, the curvature of the transfer curve of the output voltage generated by the IRD sensor 70 of FIG. 4 can be changed. In the IRD sensor 10, since I D1  and I D2  are generated independent of the leakage current of the photodiode 78, they can be changed. By changing I D , both I D1  and I D2  will be changed. I D  can be changed by varying the value of the variable resistor 150. Once I D  is changed, the curvature of the curve of the output voltage V OUT1  generated by the IRD sensor of this invention will be changed. This feature, allows the IRD sensor of this invention to be used with different reference curves. By adjusting the IRD, the transfer curve of the output voltage V OUT1  of the IRD sensor of this invention can be adjusted to match different reference curves. 
     It should be noted that numerous changes in details of construction and the combination and arrangement of elements may be resorted to without departing from the true spirit and scope of the invention as hereinafter claimed.