Abstract:
An electronic circuit comprising: an integrated circuit chip, the integrated circuit chip having a top face; portions of the top face of the chip being covered by a first metal layer electrically connected to the integrated circuit; and a dielectic layer formed on the top face of the chip beside and on top of said first metal layer; wherein the dielectric layer extends parallel to the top face of the chip beyond the edges of the chip, the first metal layer extending in the dielectric layer beyond the edges of the chip; and wherein portions of a top surface of the dielectric layer are covered by a second metal layer, portions of the first and second metal layers being electrically connected through the dielectric layer.

Description:
INCORPORATION BY REFERENCE 
     The present disclosure relates to U.S. Pat. No. 7,598,131 “High power-low noise microwave GaN heterojunction field effect transistor”; US2010059793 “InP BASED HETEROJUNCTION BIPOLAR TRANSISTORS WITH EMITTER-UP AND EMITTER-DOWN PROFILES ON A COMMON WAFER”; U.S. Pat. No. 6,670,653 “INP COLLECTOR INGAASSB BASE DHBT DEVICE AND METHOD OF FORMING THE SAME”; and WO0079600 “SINGLE HETEROJUNCTION InP-COLLECTOR BJT DEVICE AND METHOD”; which are hereby incorporated by reference. 
     TECHNICAL FIELD 
     The present disclosure relates to flexible electronic circuits; in particular flexible high frequency electronic circuits. 
     BACKGROUND 
     Flexible/printable electronics have received a great attention in the past decade mainly at low frequency below MHz ranges for consumer electronics such as displays, portable devices and RFIDs [see for example R. Reuss, et al “Large-Area, Flexible Macroelectronics,” Proc. IEEE, vol. 93, no. 7, pp. 1239-1256, 2005; Misra, V., “Emerging technologies in flexible electronics,” Electron Devices Meeting, pp. 437-437, 2005; or Kim, D., Moon, J., “Highly Conductive Ink Jet Printed Films for Nanosilver Particles for Printable Electronics” Electrochemical and Solid-State Letters, Vol. 8, pp. 30-34, September 2008]. 
     The main drives for the technology include low-cost manufacturing through roll-to-roll process, lightweight, mechanical reliability, and bendable for irregular surfaces. Flexible/printable electronic technology is a key enabler for many demanding electronic systems which have constraint requirement such as space, weight and power (SWaP) in addition to being low-cost. Conformal next generation phased array radar based on flexible electronics is an example for defense applications. High quality passive components can be easily fabricated on a flexible substrate; however, active devices are not easy to integrate. 
     Thin film transistor technology (TFT) based on amorphous silicon and low-temperature polysilicon semiconductor materials deposited on a flexible substrate have shown great promises for the technology at low frequency applications. Transparent oxide film such as ZnO has also been studied to fabricate TFT but still showing low cut of frequency (fT) [see for example Y. Sun, J. A. Rogers, “Inorganic Semiconductors for Flexible Electronics”, Advanced Materials, vol. 19, pp. 1897-1916, 2007]. 
     The foregoing active materials used in the flexible electronics suffer mainly from low carrier mobility due to non-single crystal epitaxial layer. Hence, they are not suitable for microwave and millimeter-wave applications. An Alternative approach such as assembling and transferring of single-crystalline nanostructures for example silicon nanowires on a flexible substrate have been investigated for RF and higher frequency ranges since they show transport properties better than a-Si or polysilicon. The drawback of these types of active devices is their low level of output current handling in addition to low cut off frequency for high performance applications. 
     TFT type GaAs MESFET was proposed in order to achieve higher cut off frequency reported fT of 1.55 GHz for 2 μm gate length [see for example J. Ahn, H. S. Kim, K. J. Lee, Z. Zhu, E. Menard, R. G. Nuzzo, and A. Rogers, “ High - Speed Mechanically Flexible Single - Crystal Silicon Thin - Film Transistors on Plastic Substrates”, IEEE Electron Device Letters , vol. 27, no. 6, pp. 460-462, 20061. 
     Recent work based-on transformable single-crystal silicon nanomembrane on SOI substrate to a flexible substrate has shown fT of 1.9 GHz for a 4 μm gate length [see for example I-I.e. Yuan and Z. Ma, “ Microwave thin - film transistors using Si nanomembranes on flexible polymer substrate”, Applied Physics Letters , vol. 89, pp. 212105, 2006; or H. C. Yuan, G. K. Celler, and Z. Ma, “7.8- GHz flexible thin - film transistors on a low - temperature plastic substrate”, Journal of Applied Physics , vol. 102, p. 034501, 2007; or Z. Ma, and L. Sun, “ Will Future RFIC Be Flexible?,” IEEE Wireless and Microwave Tech. Conf . pp. 1-5, April 2009; or Lei Sun, Guoxuan Qin, Jung-Hun Seo, George K. Celler, Weidong Zhou, and Zhenqiang Ma, “12- GHz Thin - Film Transistors on Transferrable Silicon Nanomembranes for High - Performance Flexible Electronics”, Small - journal , vol. 6, no. 22, pp. 2553-2557, 2010]. 
     However, there still exists a need for cheap, easy to manufacture flexible chips; in particular flexible chip that perform satisfactorily at high frequency. 
     SUMMARY 
     An embodiment of the present disclosure relates to an electronic circuit comprising: an integrated circuit chip, the integrated circuit chip having a top face; portions of the top face of the chip being covered by a first metal layer electrically connected to the integrated circuit; and a dielectic layer formed on the top face of the chip beside and on top of said first metal layer; wherein the dielectric layer extends parallel to the top face of the chip beyond the edges of the chip, the first metal layer extending in the dielectric layer beyond the edges of the chip; and wherein portions of a top surface of the dielectric layer are covered by a second metal layer, portions of the first and second metal layers being electrically connected through the dielectric layer. According to an embodiment of the disclosure, the dielectric layer and the first and second metal layers form a flexible layer, which can be rolled or conformed to a shape. 
     According to an embodiment of the present disclosure, the bulk of the integrated circuit chip is a semiconductor epitaxial layer. 
     According to an embodiment of the present disclosure, the integrated circuit chip comprises an integrated circuit formed in a semiconductor epitaxial layer, the epitaxial layer having been formed on a substrate; the first metal layer and the dielectric layer having been formed on the top face of the epitaxial layer; and the substrate has been etched away from the bottom of the epitaxial layer and the epitaxial layer has been etched away from the bottom of the dielectric layer, except in the vicinity of said integrated circuit. 
     According to an embodiment of the present disclosure, the electronic circuit comprises a third metal layer on the bottom face of the integrated circuit chip. 
     According to an embodiment of the present disclosure, at least a portion of the third metal layer is connected to at least a portion of the first metal layer. 
     According to an embodiment of the present disclosure, the integrated circuit chip comprises at least one signal-carrying conductor not electrically connected to the third metal layer; and the third metal layer is arranged to not overlap said at least one signal-carrying conductor. 
     According to an embodiment of the present disclosure, a portion of one of the first and second metal layers forms a signal-carrying conductor having a given shape; and a substantially identically shaped conductor, formed in the other of the one of the first and second metal layers, is connected to the ground. 
     According to an embodiment of the present disclosure, the integrated circuit is a high frequency active circuit and a portion of one of the first and second metal layers forms a passive component of a high frequency circuit. 
     An embodiment of the present disclosure comprises a circuit assembly with: a substrate having a surface; electronic passive elements and conductors formed on said substrate surface; and an electronic circuit as detailed hereabove attached to said substrate surface such that one of the first and second metal layers is electrically coupled to said conductors formed on said substrate surface. 
     An embodiment of the present disclosure comprises a method for manufacturing an electronic circuit; the method comprising: 
     a/forming up to the penultimate top metal layer of an IC chip on a semiconductor substrate; 
     b/covering the IC chip with a layer of dielectric; 
     c/forming on top of the dielectric layer the ultimate top metal layer of the IC chip, wherein portions of the penultimate top metal layer and top metal layer are electrically connected through the dielectric layer; 
     d/attaching the dielectric&#39;s top surface on a handle support; flipping the IC chip and etching back the substrate of the chip until only the portions of the substrate located around the components of the IC chip are left at the bottom surface of the dielectric layer; and
 
e/separating the dielectric&#39;s top surface from the handle support.
 
     According to an embodiment of the present disclosure, said IC chip comprises an integrated circuit formed in a semiconductor epitaxial layer grown on said substrate; said etching back the substrate of the chip until only the portions of the substrate located around the components of the IC chip are left at the bottom surface of the dielectric layer comprising etching back the substrate up to the bottom surface of the epitaxial layer. 
     According to an embodiment of the present disclosure, the method further comprises forming a third metal layer on the bottom surface of the chip after etching back the substrate of the chip. 
     According to an embodiment of the present disclosure, forming a third metal layer on the bottom surface of the chip comprises forming connections between at least a portion of the third metal layer and at least a portion of the first metal layer. 
     According to an embodiment of the present disclosure, forming a third metal layer on the bottom surface of the chip comprises forming the third metal layer such that it does not overlap at least one signal-carrying conductor of the integrated circuit chip. 
     According to an embodiment of the present disclosure, forming the first and second metal layers comprise: 
     forming a portion of one of the first and second metal layer into a signal-carrying conductor having a given shape; and 
     forming in the other of the one of the first and second metal layer a substantially identically shaped conductor connected to the ground. 
     According to an embodiment of the present disclosure, forming the IC chip comprises forming a high frequency IC chip and wherein forming the first and second metal layers comprise forming a passive component of a high frequency circuit with a portion of one of the first and second metal layers. 
     An embodiment of the present disclosure relates to a method of forming a circuit assembly comprising: 
     forming electronic passive elements and conductors on a surface of a substrate; 
     forming an electronic circuit according to the method detailed hereabove; and 
     attaching said electronic circuit to said substrate surface such that one of the first and second metal layers is electrically coupled to said conductors formed on said substrate surface. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A to 1E  illustrate manufacturing steps of a flexible electronic circuit according to the present disclosure. 
         FIG. 2  illustrates a portion of a signal line according to an embodiment of the present disclosure. 
         FIG. 3  illustrates an electronic circuit according to an embodiment of the present disclosure. 
         FIG. 4  illustrates an electronic circuit according to an embodiment of the present disclosure. 
         FIG. 5  illustrates an electronic circuit according to an embodiment of the present disclosure. 
         FIG. 6  illustrates circuit assemblies according to embodiments of the present disclosure. 
         FIG. 7  illustrates an electronic circuit according to an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, numerous specific details are set forth to clearly describe various specific embodiments disclosed herein. One skilled in the art, however, will understand that the presently claimed invention may be practiced without all of the specific details discussed below. In other instances, well known features have not been described so as not to obscure the invention. 
       FIG. 1A  shows an IC chip  10  comprising at least one active circuit  12  formed in a substrate  14 . According to an embodiment of the present disclosure, active circuit  12  is formed in an epitaxial layer  16  formed at the surface of substrate  14 . An etch stop layer  17  can be provided between the epitaxial layer  16  and the substrate  14 . According to an embodiment of the present disclosure, an active circuit  12  having predetermined operating performances is formed, until the penultimate top layer  18  of metal of active circuit  12 , using a known manufacturing process suitable for manufacturing on a substrate a non-flexible active circuit having substantially the same predetermined operating performances. 
     According to an embodiment of the present disclosure, a layer of flexible dielectric  20  is formed on top of the penultimate metal layer  18 . The top metal layer  22  of active circuit  12  is formed on top of dielectric layer  20 . Portions of top metal layer  22  can be connected to portions of the penultimate metal layer  18  with vias  24 . As shown in  FIG. 1A , conductors  26  can optionally be formed in the thickness of dielectric layer  20  in contact of top metal layer  22  or penultimate metal layer  18 , for example using a trench filled with via material. 
     According to an embodiment of the present invention, the layer of flexible dielectric  20  comprises polymide. However, the dielectric  20  can also comprise Liquid Crystal Polymer (LCP), Polyethylene Terephthalate (PET), polyethylene naphthalate (PEN); or the materials known by the commercial names of Mylar™ Kapton™, Parylene™, Dupont Pyralux™. Similarly, the metal layers  18 ,  22  can be gold, aluminum, copper, or any metal suitable for the manufacturing of an integrated circuit. According to an embodiment of the present invention, the two top layers of the active circuit  12  are separated by a layer of flexible dielectric. However, alternatively, three or more top layers of the active circuit  12  can be separated by layers of flexible dielectric to form a flexible layer if appropriate. 
     According to an embodiment of the present disclosure, active circuit  12  can be a high frequency circuit that comprises at least a InP High Electron Mobility Transistor (HEMT)/Metamorphic High Electron Mobility Transistor MHEMT, and substrate  14  is a InP or GaAs substrate. According to embodiments of the present disclosure, circuit  12  can be manufactured as disclosed in for example U.S. Pat. No. 7,598,131 “High power-low noise microwave GaN heterojunction field effect transistor”; or US2010059793 “InP BASED HETEROJUNCTION BIPOLAR TRANSISTORS WITH EMITTER-UP AND EMITTER-DOWN PROFILES ON A COMMON WAFER”; or U.S. Pat. No. 6,670,653 “INP COLLECTOR INGAASSB BASE DHBT DEVICE AND METHOD OF FORMING THE SAME”; or WO0079600 “SINGLE HETEROJUNCTION InP-COLLECTOR BJT DEVICE AND METHOD”, but for the replacement of the layer between the two top metal layers by a dielectric layer  20  and the subsequent processing detailed hereafter. 
     According to an embodiment of the present disclosure, manufacturing active circuit  12  using a known manufacturing process suitable for manufacturing high frequency circuits on a regular substrate (with the exception of replacing the last dielectric layer between the top metal layers by flexible dielectric layer  20  and subsequent processing detailed hereafter), causes active circuit  12  to have satisfactory high frequency operating performances. 
       FIG. 1B  shows IC chip  10  having been flipped and the top surface of IC chip  10  being attached to a handle support  28  using a layer of temporary adhesive  30  such as high temperature wax or the adhesive known under the commercial name CR-200™ from Brewer Science or EP29™ from MasterBond. 
       FIG. 1C  shows the bottom of the substrate  14  having been etched away down to the vicinity of active circuit  12 . Where active circuit  12  was formed in an epitaxial layer  16 , substrate  14  can be etched away down to the etch stop layer  17  separating epitaxial layer  16  from substrate  14 . According to an embodiment of the present disclosure, HCL wet etch process at room temperature with 10 micrometer/min etch rate can be used to etch a InP substrate with a InGaAs etch stop layer. According to an embodiment of the present disclosure, a GaAs substrate can be etched/removed using either Ammonium Hydroxide solution with ˜2 micrometer/min etch rate or a dry etch Chlorine-based chemistry with ˜10 micrometer/min etch rate at room temperature. 
       FIG. 1D  shows the bottom of the substrate  14  having been further etched away, down to the bottom surface of dielectric  20 , except around active circuit or component  12 , thus forming a chip  31  of substrate  14  around active circuit  12 . In the embodiment where active circuit  12  is formed in an epitaxial layer  16 , epitaxial layer  16  is etched away down to the bottom surface of dielectric  20  except around active circuit  12 , thus forming a chip  31  of epitaxial layer  16  around active circuit  12 . According to an embodiment of the present disclosure, the thickness of chip  31  can be of 0.5 micrometer. The thickness of the chip can generally be from 0.1 micron to 600 microns. According to an embodiment of the present disclosure, after etching the substrate/epitaxial layer down to the bottom surface of dielectric  20  except around chip  31 , a layer of metal  32  can be formed on the bottom surface of chip  31 . The layer of metal  32  can be used to ease removing heat from the active circuit  12  in operation. According to an embodiment of the present disclosure, the layer of metal  32  can be coupled to conductors inside active circuit  12 , or to metal layer  18 , through or on the side of chip  31 . 
     According to an embodiment of the present disclosure, the active circuit  12  comprises at least one signal-carrying conductor (not shown) that is not electrically connected to metal layer  32 , and metal layer  32  is patterned to not overlap said signal-carrying conductor. This allows reducing capacitive coupling between the signal-carrying conductor and metal layer  32 . 
       FIG. 1E  shows a completed electronic circuit  40  according to an embodiment of the present disclosure, after handle support  28  was detached from the top surface of dielectric layer  20  by removing temporary adhesive  30 . According to an embodiment of the present disclosure, electronic circuit  40  forms a flexible, conformable circuit where in particular the portions of the dielectric layer  20  and metal layers  18  and  22  extending beyond the edges of chip  31  are very thin and flexible and can be bent along a large range of angles including 0 to 350 degrees. It is noted that the portion of the electronic circuit  40  to which chip  31  is attached is also rather flexible due to the small size and thinness of chip  31 , such that electronic circuit  40  is generally rollable. As detailed hereafter, according to an embodiment of the disclosure, flexible circuit  40  can be “printable”, or attachable to a flexible substrate on which for example passive elements have been formed or attached. 
     According to an embodiment of the present disclosure, the thickness of the dielectric layer  20  is of 3 microns, but it can be comprised between 0.5 microns to 500 microns. The circuit  40  illustrated hereabove comprises two chips  31 , but it can comprise one chip  31  only, or more than two chips  31 . The chips  31  described hereabove comprise a single active circuit or component  12 , but they can also comprise one or more passive circuits or components and/or one or more active circuits or components. According to an embodiment of the present invention, passive circuits can comprise TaN or epitaxial resistors. According to an embodiment of the present invention, a circuit  40  can comprise one or more chips  31  having one or more active circuits and one or more chips  31  having one or more passive circuits. It is for example contemplated that a circuit according to an embodiment of the present disclosure can be a conformal phased array radar. It is noted that, even though  FIGS. 1A-1E  relate to an electronic circuit made using a technology for making InP HEMT/MHEMT on a InP or GaAs substrate, the present disclosure also contemplates using technologies for making InP HBT, or using SOI silicon or GaN substrates. 
     According to an embodiment of the disclosure, manufacturing chip  31  using a known technology, except for the formation of dielectric layer  20  between the two top metal layers of chip  31 , followed by an etching of the substrate/epitaxial layer down to the bottom surface of dielectric  20  except around chip  31 , allows manufacturing a electronic circuit that is flexible and that also comprises a chip  31  operating substantially as would the same chip  31  if it were manufactured entirely using said known technology. Importantly, an electronic circuit according to the present disclosure distinguishes from a known chip manufactured alone, and then assembled on a flexible substrate, at least in that the chip according to the present disclosure can be smaller and thinner; does not require contact pads that would be required for the known chip to be assemblable (and would detrimentally affect the operation of the known chip); and does not require the alignment for assembling the known chip on the flexible substrate. Similarly, the flexible dielectric layer  20  having metal layer conductors  18 ,  22  of an electronic circuit according to the present disclosure distinguishes from a known flexible substrate attached to a chip manufactured alone at least in that the dielectric layer according to the present disclosure can be smaller and thinner; does not require contact pads that would be required for assembly to the known chip (and would detrimentally affect the operation of the known chip); and does not require the alignment for assembling the known chip on the flexible substrate. 
       FIG. 2  illustrates a portion of a signal line  42  according to an embodiment of the present disclosure. Signal line  42  is for example formed in metal layer  18  between two conductor portions  44 ,  46  of metal layer  18  connected to the ground. According to an embodiment of the present disclosure a ground line  48  having substantially the same shape as signal line  42  is formed in metal layer  22  above signal line  42 . In the embodiment illustrated, ground line  48  is connected to ground conductors  44 ,  46  by vias (not shown). The inventors have noted that the above structure allows maintaining substantially constant a given impedance of the signal line (e.g. 50 Ohms) even if the distance between signal line  42  and ground conductors  44 ,  46  is too small for being manufactured accurately in a reliable manner. 
       FIG. 3  illustrates an electronic circuit  50  according to an embodiment of the present disclosure, comprising a single chip  31  having a high frequency FET transistor, wherein the top metal layer  22  forms two microstrip radial stubs  52 . 
       FIG. 4  illustrates an electronic circuit  60  according to an embodiment of the present disclosure, with a chip  31 A comprising an active high frequency InP HEMT transistor and a chip  31 B comprising a resistor, wherein the metal layer  22  or  18  form contact pads  62 ,  64 ,  66  and their respective connections to the Drain, Source and Gate of the HEMT of chip  31 A, as well as connections from a pad  68  to chip  31 B and from chip  31 B to the connection to the gate of the HEMT. According to an embodiment, dielectric layer  20  can be cut to follow substantially the shape of the circuit formed by the chips  31 , the pads and the connections between the pads and the chips. 
       FIG. 5  illustrates an electronic circuit  70  according to an embodiment of the present disclosure, comprising a plurality of HEMT transistor chips  31 A connected to a plurality of TaN resistor chips  31 B, as well as connection pads  72 . 
       FIG. 6  illustrates circuit assemblies according to embodiments of the present disclosure, comprising flexible substrates  80 ,  82 ,  84  on which passive elements  86 ,  88 ,  90 , such as antenna, were formed. Passive elements can for example be formed by sputtering, electroplating, printing. A flexible electronic circuit according to an embodiment of the present disclosure, such as the circuit  60  illustrated in  FIG. 4 , is then attached to substrates  80 ,  82 ,  84 , for example with adhesive, such that the pads of the circuit are connected to the appropriate passive elements  86 ,  88 ,  90 . The pads can be bonded or attached with conducting adhesive. 
     According to an embodiment, bottom metal layer  32  can where appropriate be contacted to passive elements  86 ,  88 ,  90  to facilitate heat evacuation from the chips  31  of circuit  60 . 
       FIG. 7  illustrates an electronic circuit  100  according to an embodiment of the present disclosure, comprising a chip  31  having a HEMT with a gate  31 G. Conductors  18 S formed in metal layer  18  are connected to the source of the HEMT and a conductor  18 G formed in metal layer  18  is connected to the gate  31 G of the HEMT. According to an embodiment of the present disclosure, conductors  32 S are formed on layer  32  on the bottom side of chip  31  and in electrical contact with conductors  18 S. According to an embodiment of the present disclosure, conductors  32 S are formed on layer  32  on the bottom side of chip  31  such that they do not overlap gate  31 G of chip  31 , so as to not couple capacitively with gate  31 G. According to an embodiment of the disclosure, conductors  32 S are formed in electrical contact with conductors  18 S. However, layer  32  can also be formed so as not to be in contact with layer  18 , for example only on the bottom side of chip  31 , or on the bottom side of chip  31  and on the bottom of layer  20  but without contact to layer  18 . 
     Applicant has made the present disclosure with respect to the current state of the art, but also contemplates advancements and that adaptations in the future may take into consideration of those advancements, namely in accordance with the then current state of the art. It is intended that the scope of the invention be defined by the Claims as written and equivalents as applicable. Reference to a claim element in the singular is not intended to mean “one and only one” unless explicitly so stated. Moreover, no element, component, nor method or process step in this disclosure is intended to be dedicated to the public regardless of whether the element, component, or step is explicitly recited in the Claims. No claim element herein is to be construed under the provisions of 35 U.S.C. Sec. 112, sixth paragraph, unless the element is expressly recited using the phrase “means for . . . ” and no method or process step herein is to be construed under those provisions unless the step, or steps, are expressly recited using the phrase “comprising the step(s) of . . . . ”