Abstract:
An exemplary dynamic random access memory includes a first transistor ( 210 ), a second transistor ( 220 ) and a comparator ( 230 ). The first transistor includes a first gate electrode ( 211 ), a first source electrode ( 213 ) and a first drain electrode ( 215 ). The second transistor includes a second gate electrode ( 221 ), a second source electrode ( 223 ) and a second drain electrode ( 225 ). The first source electrode is connected with the second source electrode. The first drain electrode is an input terminal for inputting a message. The comparator is connected to the second drain electrode, and preconfigured with a reference current. The comparator compares the reference current and a current through the second drain electrode to define a state of the current read from the comparator.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a dynamic random access memory (DRAM), and more particularly to a DRAM having a comparator and a method for accessing the DRAM. 
     2. General Background 
     Dynamic random access memories (DRAMs) with functions of write and read have become an important part for modern computers and personal digital systems. Referring to  FIG. 3 , this is a circuit diagram of a conventional DRAM. The DRAM  10  comprises a transistor  110  and a storage capacitor (Cs)  120 . Typically, the transistor  110  is a thin film transistor. The transistor  110  includes a gate electrode  111 , a source electrode  113 , and a drain electrode  115 . The Cs  120  is used for voltage access. One terminal of the Cs  120  is connected to the drain electrode  115 , and the other terminal of the Cs  120  is connected to ground. 
     When a threshold voltage is applied to the gate electrode  111  of the transistor  110 , the transistor  110  is turn on. When the transistor  110  is in the on-state, an input voltage is stored in the Cs  120  through the source electrode  113  and the drain electrode  115 . Next, when the transistor  110  returns to the on-state again, the stored input voltage in the Cs  120  is read out through a path between the source electrode  113  and the drain electrode  115 . 
     Because the transistor  110  controls the charge and discharge function for the Cs  120  as the conventional DRAM  10  is processing voltage access, a charge leakage may occur and further induce the Cs  120  and the transistor  110 . This causes a shorter refresh cycle time. Therefore the refresh process is performed more frequently, and the accumulated time of the DRAM  10  device is increased. That is, the operation speed of the DRAM  10  having a transistor/capacitor structure is far slower than that of a static random access memory (SRAM) having a combination of six transistors. Compared with the SRAM, the performance of the DRAM is very inefficient. Thus there is a need for an improved DRAM structure which obviates one or more of the above-described problems, limitations and disadvantages, and provides efficient performance. 
     SUMMARY 
     In one aspect, a dynamic random access memory includes a comparator with an reference current to define an output current state of the comparator. 
     An exemplary dynamic random access memory includes: a first transistor having a first gate electrode, a first source electrode and a first drain electrode; a second transistor having a second gate electrode, a second source electrode and a second drain electrode, wherein the second source electrode is connected to the first source electrode of the first transistor; and a comparator connected to the second drain electrode, and preconfigured with a reference current. And the reference current is comparing with a current through the drain electrode of the second transistor to define a current state which the comparator reads. 
     In another aspect, a dynamic random access memory includes: a first transistor having a first gate electrode, a first source electrode and a first drain electrode configured as a first input voltage terminal; a second transistor having a second gate electrode, a second source electrode and a second drain electrode configured as a second input voltage terminal, wherein the second source electrode is connected to the first source electrode of the first transistor; and a potential difference is formed between the second drain electrode and the second source electrode of the second transistor. Then, the potential difference generates a specific current as the second transistor is turned on. 
     In the other aspect, an access method for a dynamic random access memory having a comparator preconfigured with a reference current includes the steps of: inputting a first voltage in the first source electrode of the first transistor and the second source electrode of the second transistor through the first drain electrode of the first transistor as the first transistor is turned on; inputting a second voltage to the second drain electrode of the second transistor as the second transistor is turned off; generating a current between the second drain electrode and the second source electrode of the second transistor as the second transistor is turned on; and comparing the current and the reference current of the comparator to define an output state of the comparator. 
     The DRAM adopts the second transistor in place of the storage capacitor of a conventional DRAM. Thus, first parasitic capacitor is formed between the first gate electrode and the first source electrode and a second parasitic capacitor is formed between the first gate electrode and the first source electrode. Due to smaller capacitances of the above-mentioned parasitic capacitors, the charging time of first parasitic capacitor of the first transistor and the third parasitic capacitor of the second transistor is shorter. In another aspect, a voltage can be written and a current can be read on in the DRAM simultaneously. Thus, the parasitic capacitors are not need to discharge and the access rate of the DRAM is faster. 
     Embodiments of the present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram of a DRAM according to an exemplary embodiment of the present invention; 
         FIG. 2  is a timing diagram for “Write” and “Read” operations of the DRAM of  FIG. 1 ; and 
         FIG. 3  is a circuit diagram of a conventional DRAM. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, preferred and exemplary embodiments of the present invention will be described with the reference to the attached drawings. 
       FIG. 1  is a circuit diagram of a dynamic random access memory (DRAM) according to an exemplary embodiment of the present invention. The DRAM  20  includes a first transistor  210 , a second transistor  220 , and a comparator  230 . Typically, the first transistor  210  and the second transistor  220  are thin film transistors. The first transistor  210  includes a first gate electrode  211 , a first source electrode  213 , and a first drain electrode  215 . The second transistor  220  includes a second gate electrode  221 , a second source electrode  223 , and a second drain electrode  225 . In this embodiment, the first source electrode  213  is connected to the second source electrode  223 , and the second drain electrode  225  is connected to the comparator  230 . 
     An input voltage is written in the first source electrode  213  and the second source electrode  223  of the DRAM  20 . The comparator  230  has a predetermined reference current, which is used for comparison to a current flowing through the second drain electrode  225 . The current is defined by the following equation: 
             I   =       W   L     ⁢   μ   ⁢           ⁢     C   ox     ×     [         (       V   gs     -     V   th       )     ⁢     V   ds       -       1   2     ⁢     V   ds   2         ]             
wherein W is the width of the channel of the second transistor  220 , L is the length of the channel of the second transistor  220 , μ is the electron mobility, C ox  is a capacitance of the second gate electrode  221 , V gs  is a voltage difference between the second gate electrode  221  and the second source electrode  223 , V th  is a threshold voltage of the second transistor  220 , and V ds  is a voltage difference between the second drain electrode  225  and the second source electrode  223 .
 
     When the current flowing through the second drain electrode  225  is lower than the reference current, a read out current of the comparator  230  is defined as logic “0”. When the current flowing through the second drain electrode  225  is higher than the reference current, a read out current of the comparator  230  is defined as logic “1”. 
     Generally, in view of the physical structure of the first transistor  210 , the first gate electrode  211  might partially overlap the first source electrode  213  and the first drain electrode  215 . In such case, a first parasitic capacitor C gs1  is formed between the first gate electrode  211  and the first source electrode  213 , and a second parasitic capacitor C gd1  is formed between the first gate electrode  211  and the first drain electrode  215 . However, an area of overlap of the first gate electrode  211  and the first source electrode  213  can be different to that of the first gate electrode  211  and the first drain electrode  215 . Therefore, a capacitance of the first parasitic capacitor C gs1  can be different to that of the second parasitic capacitor C gd1 . 
     Similarly, a third parasitic capacitor C gs2  is formed between the second gate electrode  221  and the second source electrode  223 , and a fourth parasitic capacitor C gd2  is formed between the second gate electrode  221  and the second drain electrode  225 . Furthermore, an area of overlap of the second gate electrode  221  and the second source electrode  223  can be different to that of the second gate electrode  221  and the second drain electrode  225 . Therefore, the capacitance of the third parasitic capacitor C gs2  can be different to that of the fourth parasitic capacitor C gd2 . 
     Typically, the capacitance of the first parasitic capacitor C gs1  is larger than that of the second parasitic capacitor C gd1 ; and the capacitance of the third parasitic capacitor C gs2  is larger than that of the fourth parasitic capacitor C gd2 . Thus, the first parasitic capacitor C gs1  and the third parasitic capacitor C gs2  are individually kept steady voltages of the first source electrode  213  and the second source electrode  223 . In the other words, the first parasitic capacitor C gs1  and the third parasitic capacitor C gs2  retain the input voltage for a predetermined period of time. Furthermore, the input voltage of the first drain electrode  215  results in a small interference of the second parasitic capacitor C gd1 . And the current of the second drain electrode  225  read out through the comparator  230  also results in a small interference of the fourth parasitic capacitor C gd2    
     An example according to the above-mentioned structure is illustrated below. Typical access functions for the DRAM  20  include “read” and “write”. Referring also to  FIG. 2 , this is a timing diagram of “Read” and “Write” operations of the DRAM  20 . In  FIG. 2 , V g1  depicts a voltage curve of the first gate electrode  211 , V d1  depicts a voltage curve of the first drain electrode  215 , V g2  depicts a voltage curve of the second gate electrode  221 , and V d2  depicts a voltage curve of the second drain electrode  225 . 
     Operation of the DRAM  20  according to a preferred embodiment of the present invention is described below with reference to  FIGS. 1 and 2 . 
     Firstly, an operation of writing binary coded information in the DRAM  20  is as follows. The first source electrode  213  and the second source electrode  223  are written with an input voltage individually during the period t 1  to t 4 . During the period t 1  to t 2 , a pre-writing operation is performed. During the period t 2  to t 3 , a writing operation is performed for the DRAM  20 . During the period t 3  to t 4 , a pre-reading operation is performed. 
     At time t 1 , an input voltage (such as 5 volts) is applied to first drain electrode  215 . 
     At time t 2 , a starting voltage (such as 10 volts) that is not smaller than the threshold voltage required to operate the first transistor  210  is applied to the first gate electrode  211 , so that the first transistor  210  is in an on-state. Accordingly, the input voltage (such as 5 volts) is written in the first source electrode  213  and the second source electrode  223 . 
     In order to read a current from the comparator  230 , a high voltage (such as 8 volts) is applied to the second drain electrode  225  at time t 3 . 
     Then, the DRAM  20  is in a read operation during the period t 4  to t 5 . That is, a current from the comparator  230  can be read. At time t 4 , a starting voltage (such as 10 volts) is applied to the second gate electrode  221 , so that the second transistor  220  is in an on-state. Accordingly, a first potential difference (approximately 3 volts) exists between the second drain electrode  225  and the second source electrode  223 , and then a current is generated between the second drain electrode  225  and the second source electrode  223  at the moment the second transistor  220  is turned on. However, if the current is lower than the predetermined reference current of the comparator  230 , an output current of the comparator  230  is defined as logic “0”. At time t 5 , the second transistor  220  is set to be in an off-state. 
     In addition, the period t 2  to t 3  of the writing operation is used to provide enough charging time for storing the input voltage in the first parasitic capacitor C gs1  of the first transistor  210  and the third parasitic capacitor C gs2  of the second transistor  220 , so as to avoid the first parasitic capacitor C gs1  and the third parasitic capacitor C gs2  having abnormal voltage levels. In other words, the first parasitic capacitor C gs1  and the third parasitic capacitor C gs2  retain the input voltage for a predetermined period of time. The charging time takes at least a frame period T, according the preferred embodiment as shown in  FIG. 2 . 
     Furthermore, there is an upward period during which the input voltage is raised from 0 volt to 5 volts. An error current will be read from the comparator  230  during the upward period. Thus, a time period t between the time that the second transistor  220  is turned on and the time that the first transistor  210  is turned on is provided. The time period t begins shortly prior to the time the second transistor  220  is turned on, and ends at the time the second transistor  220  is turned on. The time period t is provided for the purpose of avoiding reading of an error current. Accordingly, enough time is provided for raising the input voltage applied to the second source electrode  223  to a predetermined, steady value (or level). 
     Moreover, if a time period t also can be extended for providing appropriate charging time of the first parasitic capacitor C gs1  of the first transistor  210  and the third parasitic capacitor C gs2  of the second transistor  220 , the first source electrode  213  and the second source electrode  223  can be written with an input voltage individually just during the period t 1 ′ to t 4 . That is, the first transistor  210  only turns on once in the foregoing period. In other words, an operation of writing binary coded information in the DRAM  20  is performed during only a frame period. Similarly, during the period t 1 ′ to t 2 ′, a pre-writing operation is performed. During the period t 2 ′ to t 3 , a writing operation is performed for the DRAM  20 . During the period t 3  to t 4 , a pre-reading operation is performed. 
     Next, another operation of writing binary coded information in the DRAM  20  is as follows. That is, an input voltage is written in the first source electrode  213  and the second source electrode  223  during the period t 6  to t 9 . During the period t 6  to t 7  period, the DRAM  20  is performing a pre-writing operation. During the period t 7  to t 8 , the DRAM  20  is performing a writing operation. During the period t 8  to t 9 , the DRAM  20  is performing a pre-reading operation. 
     At time t 6 , an input voltage such as 0 volt is applied to the first drain electrode  215 . 
     At time t 7 , a starting voltage such as 10 volts that is not smaller than the threshold voltage required to operate the first transistor  210  is applied to the first gate electrode  211  so that the first transistor  210  operates in an on-state. Accordingly, the input voltage such as 0 volts is written in the first source electrode  213  and the second source electrode  223 . 
     For the purpose of reading a current from the comparator  230 , a high voltage such as 8 volts is applied to the second drain electrode  225  at time t 8 . 
     Then, the DRAM  20  is in a read operation during the period t 9  to t 10 . That is, a current from the comparator  230  is read. At t 9 , a starting voltage (such as 10 volts) is applied to the second gate electrode  221 , so that the second transistor  220  is set in an on-state. Accordingly, a potential difference (approximately 8 volts) exist between the second drain electrode  225  and the second source electrode  223 , and then a current is generated between the second drain electrode  225  and the second source electrode  223  at the moment the second transistor  220  is turned on. However, if the current is higher than the predetermined reference current of the comparator  230 , an output current that can be read from the comparator  230  is defined as logic “1”. At time t 10 , the second transistor  220  operates is set to be an off-state. 
     In other words, the logic “0” and “1” of the DRAM  20  corresponds to the variation current or voltage of the second transistor  220 . 
     Obviously, the second transistor  220  of the DRAM  20  substitutes for the storage capacitor  120 . As the DRAM  20  performs in a “Write” operation, the charging time of the first parasitic capacitor C gs1  of the first transistor  210  and the third parasitic capacitor C gs2  of the second transistor  220  is shorter due to smaller capacitances of the above-mentioned storage capacitor (Cs)  120 . In another aspect, a voltage can be written and a current can be read in the DRAM  20  simultaneously. Thus, it is not necessarily to discharge the parasitic capacitors C gs1  and C gs2  and resulted in a faster access rate of the DRAM  20 . 
     In addition, the first and second transistors  210 ,  220  are preferably the same type of thin film transistor. For example, the first and second transistors  210 ,  220  both be n-type thin film transistors, and have the same threshold voltage. 
     In addition, the input voltage and the starting voltage are periodic applied to the transistor due to a steady access. That is, a refresh period of the input voltage and the starting voltage is adopted to avoid the leakage of the transistor. The period of the input voltage is same as that of the starting voltage and the periods T are both between 15 microseconds to 64 milliseconds. 
     While the above description has been by way of examples and in terms of preferred and exemplary embodiments, it is to be understood that the invention is not limited thereto. To the contrary, the above description is intended to cover various modifications and similar arrangements, including modifications and similar arrangements that would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.