Abstract:
A method of estimating delay which includes configuring a first signal path and second signal path such that the first signal path is a victim signal path and the second signal path is an aggressor signal path, calculating Miller factors between the victim signal path and the aggressor signal path for a plurality of edge combinations between a victim signal edge and an aggressor signal edge, and using the Miller factors to perform a timing analysis.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to static timing analysis, and more particularly to static timing analysis using Miller factors. 
   2. Description of the Related Art 
   It is known that static timing analysis can be used to verify timing behavior. Static timing analysis analyzes a circuit design for the earliest and latest possible signal arrival times on each logic path or node within the circuit design, regardless of what is happening along other paths within the circuit. The arrival times combined with the signal transition time (referred to as the slew) are expressed as time windows. Comparing the arrival times at a particular node in the circuit with a required arrival time provides the slack at that node in the circuit. By assuming that the earliest and latest signals as expressed by the time window can be propagated through a particular gate, static timing analysis can be independent of the logic function of the gate. 
   When performing a static timing analysis, one important consideration is the crosstalk between different signal paths. Crosstalk between signal paths affects the timing of the signal path. Active coupling to a switching node may result in additional delay or reduced delay on that node depending on the direction of switching. If both nodes are switching in the same direction, the delay on both nodes is reduced, whereas if the nodes are switching in opposite directions, the delay is increased. 
   In known static timing analysis, the effect of this crosstalk is taken into account by calculating a worst case assumption that twice the coupling capacitance is used to capture this opposite direction coupling effect, forming a decoupled version of the circuit for each node, where capacitances are replaced by their Miller equivalent. For example,  FIG. 1A , labeled prior art, shows an example of a victim and aggressor signal path. In the example of  FIG. 1A , each signal path includes a capacitance to ground (C g ) as well as a cross coupled capacitance (C c ) between the victim signal path and the aggressor signal path.  FIG. 1B , labeled prior art, shows an example of signal paths for the victim and aggressor signal in which the victim signal path and the aggressor signal path are decoupled. In the decoupled signal paths, the cross coupled capacitance of each signal path is replaced with a corresponding Miller capacitance (Miller*C c ). 
   SUMMARY OF THE INVENTION 
   In accordance with the present invention, a method of computing effective adjustments (Miller factors) to the values of the non-coupled grounded capacitances which depends on the alignment, the relative skew, and the switching directions of signals between cross coupled signal paths is disclosed. 
   In one embodiment, the invention relates to a method of estimating delay which includes configuring a first signal path and second signal path such that the first signal path is a victim signal path and the second signal path is an aggressor signal path, calculating Miller factors between the victim signal path and the aggressor signal path for a plurality of edge combinations between a victim signal edge and an aggressor signal edge, and using the Miller factors to perform a timing analysis. 
   In another embodiment, the invention relates to an apparatus for estimating delay which includes means for configuring a first signal path and second signal path such that the first signal path is a victim signal path and the second signal path is an aggressor signal path, means for calculating Miller factors between the victim signal path and the aggressor signal path for a plurality of edge combinations between a victim signal edge and an aggressor signal edge, and means for using the Miller factors to perform a timing analysis. 
   In another embodiment, the invention relates to a static timing engine which includes a delay estimation module and a Miller factor module The Miller factor module includes means for configuring a first signal path and second signal path such that the first signal path is a victim signal path and the second signal path is an aggressor signal path, and means for calculating Miller factors between the victim signal path and the aggressor signal path for a plurality of edge combinations between a victim signal edge and an aggressor signal edge. The delay estimation engine includes means to use edge-specific Miller factors in its calculations. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference number throughout the several figures designates a like or similar element. 
       FIGS. 1A and 1B , labeled prior art, show examples of a coupled signal path and a decoupled signal path having a corresponding Miller factor, respectively. 
       FIG. 2  shows a schematic block diagram of a static timing engine. 
       FIG. 3  shows a flow chart for an iterative operation of static timing analysis when including edge-specific Miller factors for delay estimation. 
       FIG. 4  shows a flow chart of the operation of a calculating Miller factors for use in delay estimation. 
   

   DETAILED DESCRIPTION 
   Referring to  FIG. 2 , a schematic block diagram of a static timing engine  200  is shown. The static timing engine  200  is a timing tool that performs static timing analysis of a circuit design. The static timing engine  200  includes a command interpreter  210 , a data model  212  and a timing engine portion  214 . The static timing engine  200  receives inputs from a netlist file  220 , a constraints file  222 , a timing model file  224  and a parasitics file  226 . The timing engine portion includes an edge specific delay estimation module  240 . 
   The netlist file  220  is a structural representation of a circuit design. The structural representation may be generated from a processed data model of the circuit design. In one embodiment, the netlist file  220  may be a Verilog netlist. 
   The timing model file  224  provides the static timing engine with information regarding cell delay and slew characteristics. The cell time model is generated via a pre-characterization process. Each path (input port to output port) of a cell is simulated under a variety of input transition times and output loads and the results are provided as the cell delay and slew characteristics of a cell. The timing model file  224  also includes setup and hold constraints for a particular cell which define the earliest and latest times that a signal can arrive at a cell relative to another signal. The timing model file  224  also includes constraints on the slew and load capacitance for each port of a cell. 
   The parasitics file  226  may include detailed parasitics information or reduced parasitics information. The reduced parasitics information includes a realizable driving point pi model for cell delay calculation for each net input and poles and residues transfer response data for each net sink point. The detailed parasitics data further includes all wire resistances, all grounded capacitances, and all coupled capacitors. 
   In operation, a Miller factor adjustment is applied to the capacitance of a net that is being influenced by crosstalk noise (i.e., a victim net). The amount of the adjustment depends on the alignment of the victim net signal with other signals on different nets (i.e., aggressor nets) that are parasitically coupled to the victim. The magnitude of the adjustment depends on the relative slew rates of the signals on the victim and aggressor nets. Separate adjustments are performed for both rising and falling victim signals with respect to both rising and falling aggressor signals. Hence, a particular victim/aggressor pair will have 4 adjustments ((victim/aggressor)=(rising/rising, rising/falling, falling/rising, falling/falling)). 
   Referring to  FIG. 3 , a flow chart for iterative operation of static timing analysis when including edge-specific Miller factors during delay estimation. The overall flow begins at step  302  with the static timing engine  200  reading in the data from the various files  220 ,  22 ,  224  and  226 . At this time, the Miller factors are initially set to two (2) (an extremely pessimistic value) for all nets. 
   Next, an initial static timing analysis is performed at step  304 . These results are then fed into step  306  where new Miller factors are computed for each pair of victim/aggressor nets. 
   After completing incremental timing analysis at step  308  (which uses the new Miller factors), a check is made to determine whether the Miller factors have converged or if the iteration limit has been reached at step  310 . 
   If neither condition is satisfied, the program returns to step  306  to re-compute Miller factors based upon the results of the incremental timing analysis at step  308  and then performs an new incremental timing analysis at step  308 . 
   If either condition is satisfied, the program exits. 
   Referring to  FIG. 4 , a flow chart for the operation of a Miller factor module  306  for calculating edge-specific Miller factors is shown. First, a victim net is selected at step  402  and a Timing Window (W victim,dir,mode ) and Transition Time (T victim,dir,mode )for the victim net are computed at step  404 ; dir is the direction (rise or fall) of the victim signal, and mode is early or late. 
   Similarly, an aggressor net is identified at step  406  and a Timing Window (W aggressor,dir,mode ) and Transition Time (T aggressor,dir,mode ) for the aggressor net are computed at step  408 . Again, dir is the direction (rise or fall) of the aggressor signal, and mode is early or late. 
   For late mode timing analysis, only aggressor transitions with the opposite direction from the victim are considered, and for early mode timing analysis, only aggressor transitions with the same direction as the victim are considered. 
   The miller factor module  306  the proceeds with computing the four (4) edge-specific Miller factors (M late,rise , M late,fall , M early,rise , M early,fall ) for the victim net/aggressor net combination at step  410  in the following manner:
 
 M   late,rise =1 +K   late,rise  
 
 M   late,fall =1 +K   late,fall  
 
 M   early,rise =1 −K   early,rise  
 
 M   early,fall =1 −K   early,fall  
 
   Let T max   victim,rise,late  denote the maximum of the victim late mode rise times and T min   aggressor,fall,late  denote the minimum of the aggressor late mode fall times. 
   Then, if T max   victim,rise,late &lt;T min   aggressor,fall,late  i.e., when the aggressor switches slower than the victim, 
             K     late   ,   rise       =         T     victim   ,   rise   ,   late     max       T     aggressor   ,   fall   ,   late     min       ×     min   ⁡     (     1   ,       overlap   ⁡     (       W     victim   ,   rise   ,   late       ,     W     aggressor   ,   fall   ,   late         )         T     victim   ,   rise   ,   late     max         )               
If T max   victim,rise,late &gt;T min   aggressor,fall,late , i.e., when the aggressor switches faster than the victim,
 
   
     
       
         
           
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   Similar equations can be generated for K late,fall , K early,rise , and K early,fall . Note that the smallest possible value of K is 0, which occurs when the aggressor and victim timing windows do not overlap. The largest possible value of K is 2, which occurs when T aggressor  is less than or equal to 0.5*T victim  and the entire aggressor signal transition overlaps with the transition of the victim signal. 
   The Miller factor module  306  then proceeds with determining whether there are any other aggressor nets that interact with the particular victim net at step  412 . If there are other aggressor nets that interact with the particular victim net, then the Miller factor module  306  obtains the next aggressor net at step  406  and its timing window and transition time information at step  408 . If there are no other aggressor nets that interact with the particular victim net as determined by step  412 , then the Miller factor module proceeds with determining whether there are any other victim nets on which to perform an edge-specific Miller factor computation at step  414 . 
   If there are any other victim nets on which a edge-specific Miller factor computation is to be performed, then the Miller factor module  306  obtains a next victim net at step  402  and continues from there. 
   If no other victim nets on which an edge-specific Miller factor computation needs to be performed, the module  306  exits and the flow of the static timing analysis proceeds to step  308  where an incremental static timing analysis is performed using the recently computed Miller factors. 
   More specifically, the coupling capacitance between a victim and an aggressor is found. The Miller factor adjustment converts the coupling capacitance into an equivalent grounded capacitance on the victim net according to the following formula:
 
 C   grounded   =M×C   c  
 
   Note that each coupling cap is thus grounded 4 times for each of the 4 edge-specific Miller factors (M late,rise , M late,fall , M early,rise , M early,fall ) in the 4 different modes. For multiple aggressors and multiple capacitors, the adjustments are accumulated on a per-mode/direction basis. 
   OTHER EMBODIMENTS 
   The present invention is well adapted to attain the advantages mentioned as well as others inherent therein. While the present invention has been depicted, described, and is defined by reference to particular embodiments of the invention, such references do not imply a limitation on the invention, and no such limitation is to be inferred. The invention is capable of considerable modification, alteration, and equivalents in form and function, as will occur to those ordinarily skilled in the pertinent arts. The depicted and described embodiments are examples only, and are not exhaustive of the scope of the invention. 
   For example, the above-discussed embodiments include modules that perform certain tasks. The modules discussed herein may include hardware modules or software modules. The hardware modules may be implemented within application specific circuitry or via some form of programmable logic device. The software modules may include script, batch, or other executable files. The modules may be stored on a machine-readable or computer-readable storage medium such as a disk drive. Storage devices used for storing software modules in accordance with an embodiment of the invention may be magnetic floppy disks, hard disks, or optical discs such as CD-ROMs or CD-Rs, for example. A storage device used for storing firmware or hardware modules in accordance with an embodiment of the invention may also include a semiconductor-based memory, which may be permanently, removable or remotely coupled to a microprocessor/memory system. Thus, the modules may be stored within a computer system memory to configure the computer system to perform the functions of the module. Other new and various types of computer-readable storage media may be used to store the modules discussed herein. Additionally, those skilled in the art will recognize that the separation of functionality into modules is for illustrative purposes. Alternative embodiments may merge the functionality of multiple modules into a single module or may impose an alternate decomposition of functionality of modules. For example, a software module for calling sub-modules may be decomposed so that each sub-module performs its function and passes control directly to another sub-module. 
   Consequently, the invention is intended to be limited only by the spirit and scope of the appended claims, giving full cognizance to equivalents in all respects.