Abstract:
A semiconductor memory device carrying out a self-refresh operation in response to a refresh request signal. The device includes a memory cell array formed on a chip; a plurality of pseudo memory cells distributed and arranged on the chip, each having the same constitution as the memory cells in the memory cell array; a first circuit for monitoring the capacitor voltage in the pseudo memory cells; and a second circuit for generating the refresh request signal and charging each capacitor in the pseudo memory cells. When the potential of at least one of the capacitors in the pseudo cells falls below a predetermined level, the refresh request signal is generated, thereby enabling the device to lengthen a refresh interval as desired and to decrease power dissipation, while facilitating work requiring any adjustment.

Description:
This application is a continuation of application Ser. No. 117,589 filed Nov. 6, 1987 now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device which generates a refresh request signal to carry out a self-refresh when a refresh is needed. 
     2. Description of the Related Art 
     In a dynamic random access memory (DRAM) including a memory cell having a capacitor for retaining information, the information gradually fades away and vanishes due to a leakage of the charges in the capacitor as the time elapses. Accordingly, before the information vanishes, an operation by which the information is refreshed i.e., a refresh operation, must be carried out. 
     The refresh operation is based on a refresh request signal, which is usually generated by a central processing unit (CPU) provided outside the DRAM chip, or by a timer or a ring oscillator provided inside the chip. In either case, the refresh is carried out intermittently. In practice, a DRAM which can detect whether or not a refresh is needed and can carry out the refresh when the potential of the capacitor of the memory cell is changed to an extent such that a refresh is needed, has been proposed. 
     Where the DRAM carries out a self-refresh operation, the function thereof is equivalent to that of a static RAM (SRAM), from the aspect of a CPU outside the chip, although a problem of a conflict in the priority between a memory access and the refresh exists inside the chip. Accordingly, such a DRAM is referred to as a pseudo SRAM (PSRAM). 
     On the other hand, fluctuations in the time interval at which the refresh is needed are caused by the voltage, temperature, manufacturing process, e.g., amount of leakage in the capacitor, and the like. In the method where the refresh is periodically carried out, e.g., using a clock signal output by a timer, the refresh interval must be shortened (usually about 4 msec) to ensure that a destruction of the content of memory is prevented at all costs. Accordingly, the number of times a refresh operation is carried out is increased, resulting in an increase in the power dissipated and an increase in the number of times a conflict occurs between the refresh and the memory access. That is, the method where the refresh is periodically carried out irrespective of the timing at which a refresh is actually needed is not preferable. 
     Conversely, a method is known wherein the refresh is carried out at the timing at which a refresh is actually needed, based on a detection of the potential of the capacitor. In this method, the refresh interval can be lengthened as required, resulting in a decrease in the power dissipated and a decrease in the number of times a conflict occurs between the refresh and the memory access. In particular, the advantage of the former method is that it contributes to a battery back-up operation. The method of detecting the timing at which the refresh is needed is realized by an arrangement wherein a detecting capacitor having the same constitution as a capacitor of a memory cell is formed on a substrate, so that the voltage thereof can be detected, and the detecting capacitor is charged during the refresh operation, and when the voltage thereof falls below a predetermined value, the refresh request signal is generated. 
     In this case, the timing of the generation of the refresh request signal must be selected so that the correct read operation can be carried out even for a memory cell at which a leak first occurs among all of the memory cells. However, this can be changed depending on the characteristics of the substrate, i.e., the chip. Also, a problem arises in the selection of the location of the detecting capacitor on the substrate. Accordingly, conventional measurements have been taken whereby a plurality of detecting capacitors are connected via fuses and a desired capacitance is obtained by cutting the fuses by a laser beam so that a desired refresh timing is obtained in each chip. 
     However, obtaining the desired capacitance by cutting the fuses by a laser beam is difficult and cumbersome. Determining the desired value of the capacitance is also cumbersome, and further, if the same capacitance is selected for each chip, a sufficient margin must be assured. In this case, the refresh interval is shortened, and thus there is little difference between the method utilizing the detection of the potential of the capacitor and the method wherein the refresh is periodically carried out using an external clock. 
     SUMMARY OF THE INVENTION 
     A principal object of the present invention is to provide a semiconductor memory device capable of lengthening a refresh interval to the greatest extent possible, while facilitating adjustment work. 
     Another object of the present invention is to provide a semiconductor memory device capable of decreasing power dissipation. 
     The above objects are attained by providing a semiconductor memory device carrying out a self-refresh in response to a refresh request signal, the device including: a memory cell array formed on a chip and including a plurality of memory cells, each being provided at each of the intersections between a plurality of word lines and a plurality of bit lines and having a capacitor for retaining information to be refreshed by the refresh; a plurality of pseudo memory cells distributed and arranged on the chip, each having the same constitution as the memory cell in the memory cell array; a first circuit operatively connected to the plurality of pseudo memory cells for monitoring the potential of each capacitor in the pseudo memory cells and generating a detection signal when the potential of at least one of the capacitors falls below a predetermined level; and a second circuit operatively connected to the first circuit for generating the refresh request signal in response to the detection signal and temporarily charging each capacitor in the pseudo memory cells. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects and features of the present invention will be described hereinafter in detail by way of a preferred embodiment with reference to the accompanying drawings, in which: 
     FIG. 1 is a circuit diagram illustrating main parts of a semiconductor memory device as an embodiment of the present invention; 
     FIG. 2 is a plan view schematically illustrating an example of the arrangement of the sense cell array shown in FIG. 1; 
     FIGS. 3 and 3a-b are a block diagram illustrating the whole constitution of the device shown in FIG. 1; 
     FIGS. 4a to 4e are waveform diagrams for explaining the operation of the device shown in FIG. 1; 
     FIGS. 5a and 5b are graphs showing distribution characteristics in the refresh times of the real cells and pseudo cells, respectively; and 
     FIG. 6 is a graph showing a relation between the refresh time and the temperature. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A preferred embodiment of the present invention will be described hereinafter in detail with reference to FIG. 1. 
     Reference 12 denotes a memory cell array formed on a chip (not shown in FIG. 1) and including a plurality of memory cells MC. Each of the memory cells is provided at each of the intersections of a plurality of word lines WL i , WL j , ---, and a plurality of bit lines BL i , BL j , BL k , ---, and is constituted by a combination of a transistor and a capacitor. Each memory cell MC in the memory cell array 12 is referred to as a real cell, in that it is actually employed for retaining information. 
     Reference 14 denotes a sense cell array including a plurality of pseudo memory cells PMC 1  PMC 2 , PMC 3 , ---, each having the same constitution as the memory cell MC, a plurality of p-channel MOS transistors Q 1 , Q 2 , Q 3 , ---, provided for each of the pseudo memory cells, an n-channel MOS transistor Qa for the load, a power supply line V CC  having a higher voltage of 5 V, and signal lines L 1 , L 2  and L 3 . In the sense cell array 14, the gate of a transistor in each of the pseudo memory cells is connected to the gate controlling line L 1  and the connection point of the transistor, and a capacitor C 1 , C 2 , C 3 , ---, corresponding thereto is connected to the gate of the corresponding p-channel MOS transistor. The transistors Q 1 , Q 2 , Q 3 , ---, are connected in parallel between the lines L 2  and L 3 . The line L 3  is connected via a depletion type n-channel MOS transistor Qa to the power supply line V CC . 
     In the sense cell array 14, when the potential V CX  of at least one of the capacitors C 1 , C 2 , C 3 , ---, falls below a predetermined level, the corresponding p-channel MOS transistor Q 1 , Q 2 , Q 3 , ---, is turned ON, and thus the potential level on the line L 2  is raised to about the potential level on the line L 3 . Note, the potential level on the line L 3  is indicated by V CC  -V THN , where V THN  is a threshold voltage of the transistor Qa, and accordingly, the potential level on the line L 2  is indicated by V CC  -V THN  -V THP , where V THP   is a threshold voltage of each of the transistors Q 1 , Q 2 , Q 3 , ---. 
     Reference 16 denotes a leak detector including an AND gate AG, three inverters I 1 , I 2 , I 3 , and an n-channel MOS transistor Qb. In the detector 16, the line L 2  is directly connected to one input end of the gate AG, is connected to another input end thereof via the inverter I 3 , and is grounded via the MOS transistor Qb. The output end of the AND gate AG is connected to the line L 1 , the inverter I 1 , and a peripheral circuit 18. The output end of the inverter I 1  is connected via the inverter I 2  to the gate of the transistor Qb. Each inverter I 1  ˜I 3  functions to delay the propagation of a signal. 
     Therefore, in the detector 16, when the signal φ s  changes from low level to high level, the output signal φ k  of the inverter I 3  remains at a high level, and thus the output signal of the AND gate AG, hereinafter referred to as a refresh request signal φ RFSH , becomes high level. The change of this signal φ RFSH  is transmitted to the gate of the transistor Qb with a predetermined delay as a signal φ p , and the transistor Qb is turned ON and OFF in accordance with the level of the signal φ p . 
     The peripheral circuit 18 selects the word lines WL i , WL j , ---, in sequence in the memory cell array 12 in response to the refresh request signal φ RFSH , as later discussed. 
     The aforementioned pseudo memory cells PMC 1 , PMC 2 , PMC 3 , ---, are employed in order to determine the refresh time interval of the real cells in the memory cell array 12 and, accordingly, should be selected so as to represent each real cell. In the present example, the sense cell array 14 including the pseudo memory cells is provided next to the left or right end of the memory cell array 12 formed on the chip 10, as shown in FIG. 2. The pseudo memory cells are constituted by memory cells corresponding to one word line. Note, since the pseudo memory cells are not employed for retaining an information, they are not controlled by a word decoder or a column decoder and are excluded from an address space. The pseudo memory cells may be constituted by memory cells corresponding to one word line provided in the center of the memory cell array 12. The pseudo memory cells also may be constituted by memory cells corresponding to every other column in one word line, resulting in a decrease in the number of cells. 
     Next, the whole constitution of the device shown in FIG. 1 and the operation thereof will be explained with reference to FIG. 3. Note, since the memory cell array 12, sense cell array 14 and leak detector 16 have been explained with reference to FIGS. 1 and 2, a description thereof is omitted. 
     Reference 21 denotes a control circuit, which generates four control signals in response to an external clock signal. Reference 22 denotes an arbiter, which, in response to a first control signal from the control circuit 21 and the refresh request signal φ RFSH  from the leak detector 16, outputs one of those two signals. Reference 23 denotes a row address buffer, which effects buffering of an external row address signal for selection of the word line and transmits the signal to an address selector 26 in response to a second control signal from the control circuit 21. Similarly, reference 24 denotes a column address buffer, which effects buffering of an external column address signal for selection of the bit line and transmits the signal to a column decoder 31 in response to a third control signal from the control circuit 21. Reference 25 denotes a timing generator, which generates two timing signals in response to a fourth control signal from the control circuit 21 and the output from the arbiter 22. 
     Reference 26 denotes an address selector which, in response to the output from the arbiter 22, selects one of the row address signal from the buffer 23 and the refresh address signal from a refresh address counter 27 and transmits the selected address signal to a row decoder 28. The counter 27 counts the refresh address in response to the refresh request signal φ RFSH  and a first timing signal from the timing generator 25. The row decoder 28 selects the word lines in sequence in response to the selected address signal from the address selector 26. 
     Reference 29 denotes a read/write control circuit, which controls the read operation or write operation in response to an external low active write enable signal WE and a second timing signal from the timing generator 25. When the write enable signal WE is high level, a data-in buffer 33 becomes active. Inversely, when the signal WE is low level, an output control circuit 32 becomes active. Reference 30 denotes a sense amplifier, which amplifies the data signal on the bit line in response to the second timing signal from the generator 25 during the read operation. The column decoder 31 selects the bit lines in sequence in response to the column address signal from the buffer 24. 
     When the signal WE is low level and an external low active output enable signal OE is high level, the output control circuit 32 outputs the data read from the memory cells to the outside of the chip in response to the second timing signal from the generator 25. On the other hand, when the signal WE is high level, the data-in buffer 33 sends the data D IN  input from outside of the chip to the memory cells in response to the second timing signal from the generator 25. 
     In the circuit constitution shown in FIG. 3, elements indicated by reference numerals 22, 25, 26, 27 and 28 correspond to the peripheral circuit 18 shown in FIG. 1. 
     Next, the operation of the circuit shown in FIG. 1 will be described with reference to the waveform diagrams shown in FIGS. 4a to 4e. 
     Initially, assume that a charge leakage occurs in one of the capacitors of the pseudo memory cells PMC 1 , PMC 2 , ---, e.g., capacitor C 1  of the cell PMC 1 . In this state, when the potential V CX  of the capacitor C 1  falls below the aforementioned predetermined level (V CX  &lt;V CC  -V THN  -V THP ), the corresponding transistor Q 1  is turned ON, so that the signal φ s  on the line L 2  is raised from low level to high level. At this time, the signal φ k  is still high level, and therefore, the refresh request signal φ RFSH  becomes high level for a short time. 
     When the refresh request signal φ RFSH  is high level, each transistor of the pseudo memory cells PMC 1 , PMC 2 , PMC 3 , ---, is turned ON, and thus each capacitor C 1 , C 2 , C 3 , ---, is charged to the V CC  level. Accordingly, each capacitor voltage V CX  is raised to the V CC  level, and thus all of the capacitors, including the leaking capacitor, are &#34;refreshed&#34;. 
     After the signal φ s  becomes high level, the signal φ k  becomes low level, and thus the refresh request signal φ RFSH  becomes low level. The signal φ RFSH  is formed, via two inverters I 1  and I 2 , into the signal φ p  as shown in FIG. 4a. 
     On the other hand, when each capacitor of the pseudo memory cells is charged to the V CC  level in response to the refresh request signal φ RFSH , each transistor Q 1 , Q 2 , Q 3 , ---, is turned OFF. In this state, the line L 2  is brought to a floating state and the signal φ s  maintains the previous high level. However, when the transistor Qb is turned ON in response to the rise in the signal φ p , the signal φ s  becomes low level, and the signal φ k  then becomes high level. 
     When the capacitor voltage V CX  in a pseudo memory cell falls below the predetermined level, the corresponding transistor Q 1 , Q 2 , Q 3 , ---, is turned ON, resulting in a rise in the signal φ s , and thus the aforementioned operation is repeated. 
     The most important points to note in relation to the self-refresh device are: 
     the device includes a sensor which accurately detects large fluctuations in the refresh time interval of the cells in accordance with the temperature, voltage, manufacturing process and the like; and, 
     the refresh interval of the pseudo memory cells is shorter than the refresh time limit value of the true memory cells under all conditions. As is known, the refresh time of the cells is different for every cell and can vary greatly, and therefore, in the present embodiment, the refresh interval of the pseudo memory cells is selected to meet the above conditions. 
     FIGS. 5a and 5b illustrate graphs of distribution characteristics in the refresh times of the real cells and pseudo cells, respectively. 
     Referring to FIG. 5a, when the temperature of the chip is 70° C., the shortest refresh interval is 30 ms and the longest is 160 ms. The most frequent refresh interval is 120 ms. The distribution curve CV 1  shifts downwards when the temperature rises, and upwards when the temperature falls. In the present embodiment, the pseudo memory cells in the sense cell array 14 are selected so as to represent the distribution shown in FIG. 5a, and the shortest refresh interval in the pseudo memory cells is selected to have shorter interval by a predetermined margin δ than the shortest refresh interval in the memory cell array 12. 
     Where the capacity of the pseudo memory cells is made smaller than that of the true memory cells, the junction area of the pseudo memory cells is made about the same as that of the true memory cells, and such pseudo memory cells are suitably distributed and arranged in the cell array 12. The distribution in the refresh times of the pseudo cells is as shown in FIG. 5b. Referring to FIG. 5b, the distribution curve CV 2  is analogous to the curve CV 1  shown in FIG. 5a and shifts downwards as a whole. The low peak value indicates that the number of cells, i.e., the capacity, is small. As shown in FIG. 5b, the shortest refresh interval is shorter by the margin δ than the shortest interval shown in FIG. 5a. 
     FIG. 6 shows a relationship between the refresh time T REF  and the temperature. The refresh time is changed in the form of an exponential function with respect to the temperature, as shown in FIG. 6. Therefore, if the refresh time of the true cells is indicated by the curve CV 1 , the curve CV 2  having a shorter interval than that of the curve CV 1  is utilized to generate the refresh request signal φ RFSH . As a result, the destruction of the information of the memory is prevented, and at the same time, it becomes possible to lengthen the refresh interval as desired. Where the sense cell array 14 is used, a refresh corresponding to curve CV 2  becomes possible because the distribution curve CV 2  shown in FIG. 5b shifts upwards or downwards in accordance with the temperature. 
     In the illustrated preferred embodiment, the memory device includes a plurality of pseudo memory cells distributed and arranged on the chip, each pseudo cell having the same constitution as a real cell. The refresh request signal is generated by selecting the pseudo memory cells to represent the distribution of each refresh interval in the real memory cells and to have shorter interval than each refresh interval. As a result, it is possible to realize a memory device carrying out a self-refresh with a long interval, while automatically adapting the refresh operation to the existing voltage, temperature, process and the like. 
     Also, the cumbersome work needed to obtain the desired capacitance by cutting the fuses with the laser beam becomes unnecessary. In the present embodiment, the same purpose is accomplished only by making the capacity of the pseudo cells smaller than that of the true cells, or suitably selecting the threshold level of the transistors Q 1 , Q 2 , ---, for detecting the capacitor voltages. 
     Although, in the illustrated preferred embodiment, the refresh request signal φ RFSH  is processed inside the chip, to carry out the refresh of the cell array 12, the present invention is not limited to this arrangement. For example, the refresh request signal may be once output outside the chip and then, via an external CPU, input inside the chip together with a refresh address signal. 
     The preferred embodiments described above are illustrative and not restrictive, the scope of the invention being indicated by the appended claims and all variations which come within the meaning of the claims are intended to be embraced therein.