Abstract:
A coincidence decision circuit includes a plurality of data inputs and at least one coincidence decision output. This circuit comprises a plurality of coincidence detection circuit each having a plurality of inputs connected to a corresponding number of data inputs selected from the data inputs of the circuit. Each of the coincidence detection circuit is selectively put in an operable condition in response to a given selection signal so as to generate an coincidence detection signal. A circuit is connected to the coincidence detection circuit to respond to a timing signal to read out the coincidence detection signal from the coincidence detection circuit put in the operable condition. Further, another circuit is connected to the read out circuit to output the coincidence detection signal at a predetermined timing.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a coincidence or identity decision circuit, and more specifically to a coincidence decision circuit composed of field effect transistors (abbreviated &#34;FETs&#34; in this specification). 
     2. Description of Related Art 
     Heretofore, the coincidence decision circuit is basically constituted of a combination of logic gates. Referring to FIG. 1, there is shown one typical coincidence decision circuit which includes three input NOR gates 10, 12 and 14 arranged to parallel to each other. One of the input NOR gates 10 is adapted to receive a first coincidence pattern selection signal S 1  and three binary data signals R 1 , R 3  and R 5 . The second input NOR gate 12 receives a second coincidence pattern selection signal S 2  and three binary data signals R 2 , R 3  and R 4 . The third input NOR gate 14 receives a third coincidence pattern selection signal S 3  and three binary data signals R 1 , R 4  and R 5 . Outputs of all the three input NOR gates are connected to an output NOR Gate 16, which generates a coincidence decision output signal &#34;O&#34;. 
     Thus, the coincidence decision circuit shown in FIG. 1 will execute the logic operation expressed by the following formula: 
     
         O=(S.sub.1 +R.sub.1 +R.sub.3 +R.sub.5)×(S.sub.2 +R.sub.2 +R.sub.3 +R.sub.4)×(S.sub.3 +R.sub.1 +R.sub.4 +R.sub.5)      (1) 
    
     where O, R i  and S j  are logic values of 1 or 0. 
     In the above coincidence decision circuit, the coincidence pattern selection signals S 1 , S 2  and S 3  are such that two or more of the control signals are never simultaneously brought into &#34;0&#34;. In this condition, if the coincidence pattern selection signal S 1  is made to &#34;0&#34;, the coincidence pattern selection signals S 2  and S 3  are then maintained at &#34;1&#34;. Therefore, the outputs of the NOR Gates 12 and 14 are kept at &#34;0&#34;. On the other hand, when the train of the data signals (R 1  to R 5 )=0, X, 0, X, 0) (where x=arbitrary value), the NOR gate 10 outputs &#34;1&#34;, with the result that the output &#34;O&#34; of the NOR gate 16 becomes &#34;0&#34;. If the data signal train assumes other combinations of signals, the ouptut of the NOR gate 10 is maintained at &#34;0&#34; and so, the output &#34;O&#34; is kept at &#34;1&#34;. Similarly, in the case of S 2  =&#34;0&#34;, the output &#34;O&#34; is brought into &#34;0&#34; only when the data signal train (R 1  to R 5 )=(X, 0, 0, 0, X). Further, in the case of S 3  =&#34;0&#34;, the output &#34;O&#34; is put at &#34;0&#34; only when the data signal train (R 1  to R 5 )=(0, X, X, 0, 0). 
     Namely, when the data signal train (R 1  to R5) is consistent with a specific pattern designated by the coincidence pattern selection signal S j  (j=1 to 3), the coincidence decision output &#34;O&#34; becomes &#34;0&#34;. Otherwise, the decision output &#34;O&#34; is maintained at &#34;1&#34;. 
     As mentioned above, conventional coincidence circuits have been constructed to peform the logical function expressed by the logical formula (1) mentioned above or similar logical functions, and have been widely used as general purpose coincidence decision circuits. Here, examining the coincidence circuit shown in FIG. 1, the number &#34;1&#34; of the specifically designated patterns is 3, and the number &#34;m&#34; of the data signals examined for coincidence decision is 3. In addition, the bit number &#34;n&#34; of the selection signals designating each specific pattern is 1. Under this condition, if the respective NOR gates shown in FIG. 1 are constituted of so-called CMOS logic gates, the number of required FETs is as follows: 
     
         2×1 (m+n+1)=2×3(3+1+1)=30 
    
     Similarly, in the case of 1=10, m=5, and n=1, if a coincidence circuit is constituted in a manner similar to that of the circuit shown in FIG. 1, the coincidence circuit needs 140 FETs. 
     As mentioned above, the conventional general purpose coincidence decision circuits require a large number of FETs, and therefore, a power consumption is large. In addition, when the circuits are assembled in integrated circuits, a large chip area is required, and interconnection wiring is complicated. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is one object of the present invention to provide a coincidence decision circuit which has dissolved the above mentioned drawbacks of the conventional circuits. 
     Another object of the present invention is to provide a coincidence decision circuit which can be constructed of a decreased number of FETs. 
     Still another object of the present invention is to provide a coincidence decision circuit which can operate with a reduced power consumption and which can be assembled in integrated circuits with a decreased chip area. 
     The above and other objects of the present invention are achieved in accordance with the present invention by a coincidence decision circuit which includes a plurality of data inputs and at least one coincidence decision output, comprising: 
     a plurality of coincidence detection means each having a plurality of inputs connected to a corresponding number of data inputs selected from the data inputs of the circuit, each of the coincidence detection means being selectively put in an operable condition in response to a given selection signal so as to generate an coincidence detection signal; 
     means connected to the coincidence detection means and responsive to a timing signal to read out the coincidence detection signal from the coincidence detection means put in the operable condition, and 
     means connected to the read out means to output the coincidence detection signal at a predetermined timing. 
     In an embodiment of the present invention, each of the coincidence detection means includes an FET array which has at least three field effect transistors connected in parallel to one another between a first common line and a second common line. One of the field effect transistors receives a given selection signal at its gate, and the remaining field effect transistors receive the selected number of data inputs, so that the first common line generates the coincidence detection signal when all the transistors are put in off condition. 
     Each of the coincidence detection means is associated with a first switching field effect transistor adapted to receive a first timing signal at its gate. One end of the first switching transistor is connected to the first common line of the associated coincidence detection means, and the other end of each first switching transistor is connected to a first voltage supply terminal. 
     Furthermore, there is provided a second switching field effect transistor adapted to receive at its gate the first timing signal so as to assume the on-off condition opposite to that of each first transistor. One end of the second transistor is connected in common to the second common lines of all the coincidence detection means, and the other end of the second switching transistor is connected to a second voltage supply terminal. 
     The read out means includes a third switching field effect transistor associated to each of the coincidence detection means and connected at its gate to the first common line of the associated coincidence detection means and having one end connected to the second voltage supply terminal; and four switching field effect transistors receiving their gates a second timing control signal which changes its condition later than the change of the first timing control signal. Each of the fourth transistors is connected at its one end to the other end of the corresponding third transistor and at its other end to the coincidence decision output. 
     In addition, the output means includes a fifth switching field effect transistor connected between the first voltage supply terminal and the coincidence decision output, the fifth transistor receiving at its gate the first timing signal to assume the same condition as that of the first transistor. 
     According to a second aspect of the present invention, there is provided a coincidence decision circuit which includes a plurality of data inputs and at least one coincidence decision output, comprising: 
     a plurality of coincidence detection circuits each including an FET array which has at least three field effect transistors connected in parallel to one another betwwen a first common line and a second common line, one of the field effect transistor receiving a given selection signal at its gate, and the remaining field effect transistors receiving the selected number of data inputs, so that the first common line generates the coincidence detection signal; 
     first switching field effect transistors adapted to receive a first timing signal at their gates, one end of each first switching transistor being connected to the first common line of a corresponding coincidence detection circuit, the other end of the first switching transistor being connected to a first voltage supply terminal; 
     a second switching field effect transistor adapted to receive at its gate the first timing signal so as to assume the on-off condition opposite to that of the first transistor, one end of the second transistor being connected in common to the second common lines of all the coincidence detection circuits, the other end of the second switching transistor being connected to a second voltage supply terminal; 
     third switching field effect transistors each connected at its gate to the first common line of one coincidence detection circuit and having one end connected to the second voltage supply terminal; four switching field effect transistors receiving their gates a second timing control signal which changes its condition later than the change of the first timing control signal, each of the fourth transistors being connected at its one end to the other end of the corresponding third transistor and at its other end to the coincidence decision output; and 
     a fifth switching field effect transistor connected between the first voltage supply terminal and the coincidence decision output, the fifth transistor receiving at its gate the first timing signal to assume the same condition as that of the first transistor. 
    
    
     The above and other objects, features and advantages of the present invention will be apparent from the following description of the preferred embodiment of the invention with reference to the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a logic circuit diagram illustrating a typical conventional coincidence decision circuit; 
     FIG. 2 is a circuit diagram of an embodiment of the coincidence decision circuit in accordance with the present invention; 
     FIG. 3 is a timing chart for explaining the operation of the circuit shown in FIG. 2; and 
     FIG. 4 is a truth table showing possible combinations of input data signals and a corresponding coincidence output in the circuits shown in FIG. 2. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 2, there is shown one embodiment of the coincidence decision circuit in accordance with the present invention. The shown circuit comprises three FET arrays T 1 , T 2  and T 3 . The first FET array T 1  includes four N-channel FETs N 11 , Q 11 , Q 21  an Q 31  which are connected in parallel to one another by common-connecting their drains and their sources, respectively. FET N 11  receives at its gate a first coincidence pattern selection signal S 1 , and FETs Q 11 , Q 21  and Q 31  receive binary data signals R 1 , R 3  and R 5  at their gates, respectively. The second FET array T 2  includes four N-channel FETs N 12 , Q 12 , Q 22  and Q 32  which are connected in parallel to one another by common-connecting their drains and their sources, respectively. FET N 12  receives at its gate a second coincidence pattern selection signal S 2 , and FETs Q 12 , Q 22  Q 32  receive binary data signals R.sub. 2, R 3  and R 4  at their gates, respectively. The third FET array T 3  includes four N-channel FETs N 13 , Q 13 , Q 23  and Q 33  which are connected in parallel to one another by common-connecting their drains and their sources, respectively. FET N 13  receives at its gate a third coincidence pattern selection signal S 3 , and FETs Q 13 , Q 23  and Q 33  receive binary data signals R 1 , R 4  and R 5  at their gates, respectively. Further, the source common lines of the respective FET arrays T 1 , T 2  and T 3  are common-connected. 
     In addition, the coincidence decision circuit includes a source-grounded N-channel FET N 1  whose gate is connected to receive a first timing control signal P and whose drain is connected to the source common line of the FET arrays T 1 , T 2  and T 3 . Further the timing control signal P is supplied to gates of three P-channel FETs P 11 , P 12  and P 13 , respectively, whose sources are connected in common to a voltage supply terminal V DD . The drains of the P-channel FETs P 11 , P 12  and P 13  are respectively connected to the drain common lines OD 1 , OD 2  and OD 3  of the three FET arrays T 1 , T 2  and T 3 . Furthermore, the respective drain common lines OD 1 , OD 2  and OD 3  of the FET arrays are connected to gates of three source-grounded N-channel FETs N 21 , N 22  and N 23 , respectively, whose drains are in turn connected to sources of another set of N-channel FETs N 31 , N 32  and N 33 . These FETs N 31 , N 32  and N 33  receive at their gates a second timing control signal L, and commonly connected at their drains to a drain of a P-channel FET P 1 . This FET P 1  receives at its gate the first timing control signal P, and is connected at its source to the voltage supply signal terminal V DD . The drain of the FET P 1  generates a decision output signal &#34;O&#34;. 
     Next, the operation will be explained with reference to FIG. 3 illustrating the time charts at various points in the circuit shown in FIG. 2. 
     As seen from FIG. 3, the first timing control signal P assumes a logical level of &#34;0&#34; during a period &#34;a&#34; and a logical level of &#34;1&#34; during periods &#34;b&#34;, &#34;c&#34;, &#34;d&#34; and &#34;e&#34;. On the other hand, the second timing control signal L assumes the logical level of &#34;1&#34; at a time lag of a sub-period &#34;b 1  &#34; from when the first control signal assumes &#34;1&#34;, and this second timing control signals L is maintained at the logical level of &#34;1&#34; during a sub-period of time &#34;b 2  &#34;. In addition, the second timing control signal L is brought into the logical level of &#34;0&#34; the time of sub-period &#34;b 3  &#34; before when the first timing control signal P is rendered &#34;O&#34;. 
     Thus, during the period &#34;a&#34;, FET N 1  is off, and so, each FET of the FET arrays T 1 , T 2  and T 3  is isolated from the ground. On the other hand, since FETs P 11 , P 12  and P 13  are on, the gates of FETs N 21 , N 22  and N 23  are charged to the supply voltage V DD . In addition, since FETs N 31 , N 32  and N 33  are off and at the same time FET P 1  is on, the drain of FET P 1  is charged to the supply voltage V DD . Accordingly, the three drain common lines OD 1 , OD 2  and OD 3  and the decision output &#34;O&#34; are brought into the supply voltage V DD , i.e., the logical level of &#34;1&#34;. 
     As seen from the above, during the above mentioned period &#34;a&#34;, the gates of FETs N 21 , N 22  and N 23  and the drain of FET P 1  are precharged so that the circuit is set at an initial condition of coincidence decision operation cycle. In this operation, FETs P 11 , P 12 , P 13 , FET N 1  and FET P 1   serve as switch mean for controlling the precharge. 
     During the period &#34;b&#34;, it is decided whether or not the train of data signals R 1  to R 5  is consistent with the specific pattern designated by the first coincidence pattern selection signal S 1 . The coincidence pattern selection signal S is supplied to the FET array T 1 , which includes the three FETs Q 11 , Q 21  and Q 31  which receive the data signal R 1 , R 3  and R 5 , respectively. Namely, the pattern (0, X, 0, X, 0) is designated by the coincidence pattern selection signals S 1 . In this situation, therefore, the coincidence pattern selection signals S 1 , S 2  and S 3  are made &#34;0&#34;, &#34;1&#34; and &#34;1&#34;, respectively. 
     Thus, in the FET arrays T 2  and T 3 , FETs N 12  and N 13  are on, and FETs P 12  and P 13  are off. In addition, FET N 1  is on. Therefore, the gates of FETs N 22  and N 23  are brought to the ground level, i.e., the logical level of &#34;0&#34;, so that FETs N 22  and N 23  are off. 
     On the other hand, in the example shown in FIG. 3, since all the data signals R 1 , R 3  and R 5  are &#34;0&#34;, all FETs included in the FET array T 1  are off, so that the gate of FET N 21  is maintained at the level which was precharged during the period &#34;a&#34;. Namely, FET N 21  is maintained in on condition. 
     Accordingly, the drain common lines OD 1  OD 2  and OD 3  are brought into &#34;1&#34;, &#34;0&#34; and &#34;0&#34;, respectively, during a first sub-period &#34;b 1  &#34;. Namely, this sub-period &#34;b 1  &#34; determines the on-off conditions of the FETs N 21 , N 22  and N 23 , thereby to determine the logical levels of the drain common lines OD 1 , OD 2  and OD 3 . 
     During the succeeding sub-period &#34;b 2  &#34;, FETs N 31 , N 32  and N 33  are turned on by the second timing control signal L. On the other hand, FET P 1  is maintained off by the first timing control signal P. Therefore, the drain of the FET P 1  is charged to the ground level through FETs N 31  and N 21 , so that the decision output &#34;O&#34; generates a logical signal of &#34;0&#34;. Thus, the sub-period &#34;b&#34; can be said to be a period for reading out the results of coincidence decisions appearing on the drain common lines OD 1 , OD 2  and OD 3 , to the decision output &#34;O&#34;. 
     During the sub-period &#34;b 3  &#34; succeeding to the sub-period &#34;b 2  &#34;, FETs N 31 , N 32  and N 33  are turned off, so that the drain of FET P 1  is maintained at the logical level charged during the sub-period &#34;b 2  &#34;, In other words, the decision output &#34;O&#34; read out during the sub-period &#34;b 2  &#34; are maintained. Thus, at any timing &#34;t b  &#34; during the sub-period &#34;b 3  &#34;, the decision output &#34;O&#34; is sampled by a circuit (not shown) associated to the coincidence decision circuit. In the period &#34;a&#34; shown in FIG. 3, the train of data signals (R 1  to R 5 ) is (0, 1, 0, 0, 0), which is consistent with the specific pattern (0, X, 0, X, 0) designated by the coincidence pattern selection signal S 1 . Therefore, the decision output &#34;O&#34; sampled at the timing &#34;t b  &#34; is &#34;0&#34; which indicates &#34;coincidence&#34;. 
     During the period &#34;a&#34; succeeding to the period &#34;b&#34;, the circuit is initialized again. Then, during the period &#34;c&#34;, it is decided whether or not the train of data signals R 1  to R 5  is consistent with the specific pattern (0, X, 0, X, 0) designated by the coincidence pattern selection signal S 1 . Therefore, during the period &#34;c&#34; the coincidence pattern selection signals S 1 , S 2  and S 3  are maintained at &#34;0&#34;, &#34;1&#34; and &#34;1&#34;, respectively, and so, FETs N 22  and N 23  are off. But, in this period &#34;c&#34; the data signal R 3  of &#34;1&#34; is applied to FET Q 21  in the FET array T 1 , and so, the FET Q 21  is turned on, with the result that the gate of FET N 21  is brought to the ground level. Therefore, FET N 21  is turned off similarly to FETs N 22  and N 23 , so that the drain of FET P 1  is maintained at the level precharged during the period &#34;a&#34; irrespectively of the on-off condition of FETs N 31 , N 32  and N 33  . Thus, the decision output &#34;O&#34; of &#34;1&#34; is read out at a timing &#34;t c  &#34; during the period &#34;c&#34;. 
     Namely, in the period &#34;c&#34; shown in FIG. 3, the train of data signals (R 1  to R 5 ) is (0, 0, 1, 0, 0), which is not consistent with the specific pattern (0, X, 0, X, 0) designated by the coincidence pattern selection signal S 1 . Therefore, the decision output &#34;O&#34; of &#34;0&#34; indicating &#34;inconsistence&#34; is sampled at the timing &#34;t c  &#34;. 
     During the next period &#34;a&#34; the circuit is initialized again, and during the succeeding period &#34;d&#34; it is decided whether or not the train of data signals R 1  to R 5  is consistent with the specific pattern designated by the coincidence pattern selection signal S 2 . The coincidence pattern selection signal S 2  is supplied to the FET array T 2  which includes the three FETs Q 12 , Q 22  and Q 32  which receive the data signal R 2 , R 3  and R 4 , respectively. Namely, the pattern (X, 0, 0, 0, X) is designated by the coincidence pattern selection signal S 2 . In this situation, therefore, the coincidence pattern selection signals S 1 , S 2  and S 3  are made &#34;1&#34;, &#34;0&#34; and &#34;1&#34;, respectively, during the period &#34;d&#34;. 
     Thus, in the FET arrays T 1  and T 3 , FETs N 11  and N 13  are on, and so, the drain common lines OD 1  and OD 3  are brought to &#34;0&#34;, with the result that FETs N 21  and N 23  are turned off. 
     In the example shown in FIG. 3, since the data signal R 4  of &#34;1&#34; is applied to the FET array T 2 , FET Q 32  is turned on. As a result, the drain common line OD 2  is also brought to &#34;0&#34;, and so, FET N 22  is also turned off. Thus, the drain of FET P 1  is maintained at the level precharged during the period &#34;a&#34; irrespectively of the on-off condition of FETs N 31 , N 32  and N 33 . Accordingly, the decision output &#34;O&#34; of &#34;1&#34; is read out at a timing &#34;t c  &#34; during the period &#34;c&#34;. 
     Namely, in the period &#34;d&#34; shown in FIG. 3, the train of data signals (R 1  to R 5 ) is (0, 0, 0, 1, 0), which is not consistent with the specific pattern (X, 0, 0, 0, X) designated by the coincidence pattern selection signal S 2 . Therefore, the decision output &#34;O&#34; of &#34;0&#34; indicating &#34;inconsistence&#34; is sampled at the timing &#34;t d  &#34;. 
     Further, during the next period &#34;a&#34; the circuit is initialized again, and then during the succeeding period &#34;e&#34; it is decided whether or not the train of data signals R 1  to R 5  is consistent with the specific pattern designated by the coincidence pattern selection signal S 3 . The FET array T 3  receiving the coincidence pattern selection signal S 3  includes the three FETs Q 13 , Q 23  and Q 33  which receive the data signal R 1 , R 4  and R 5 , respectively. Namely, the pattern (0, X, X, 0, 0) is designated by the selection signal S 3 , and the coincidence pattern selection signals S 1 , S 2  and S 3  are made &#34;1&#34;, &#34;1&#34; and &#34;0&#34;, respectively. 
     In this situation, FETs N 21  and N 22  are turned on, so that the drain common lines OD 1  and OD 2  are brought to &#34;0&#34;. In addition, in the period &#34;e&#34; of FIG. 3, since all the data signals R 1 , R 4  and R 5  are &#34;0&#34;, all FETs included in the FET array T 3  are off, so that the drain common line OD 3 , i.e., the gate of FET N 23  is maintained at the level of &#34;1&#34; which was precharged during the period &#34;a&#34;. Namely, FET N 23  is maintained in on condition. 
     Accordingly, when the second timing control signal L becomes &#34;1&#34;, FETs N 31 , N 32  and N 33  are turned on, and on the other hand, FET P 1  is maintained off by the first timing control signal P. Therefore, the drain of the FET P 1  is charged to the ground level through FETs N 33  and N 23 , so that the decision output &#34;O&#34; generates a logical signal of &#34;0&#34;. In the period &#34;e&#34; shown in FIG. 3, the train of data signals (R 1  to R 5 ) is (0, 1, 0, 0, 0), which is consistent with the specific pattern (0, X, X, 0, 0) designated by the coincidence pattern selection signal S 3 . Accordingly, the decision output &#34;O&#34; sampled at the timing &#34;t e  &#34; is &#34;0&#34; which indicates &#34;coincidence&#34;. 
     All possible combinations of input data signals and corresponding decision outputs in the embodiment shown in FIG. 2 are indicated in FIG. 4. In this figure, the values of the signals OD 1 , OD 2  and OD 3  indicate the values when the corresponding coincidence pattern selection signals S 1 , S 2  and S 3  are &#34;0&#34;. As mentioned hereinbefore, when the selection signals S j  is &#34;1&#34;, the corresponding signal OD j  assumes &#34;1&#34;. All the decision outputs &#34;O&#34; of &#34;0&#34; are surrounded by a frame, so that it can be easily notified that the result of decision indicates &#34;coincidence&#34;. Incidentally, some of possible combinations of input data signals is omitted, but the omitted combinations do not include the case in which the result of decision is &#34;coincidence&#34;. 
     In the embodiment as mentioned above, the number &#34;1&#34; of specific patterns is 3, and the number &#34;m&#34; of data signals examined for coincidence decision is 3. In addition, the bit number &#34;n&#34; of each selection signal designating one specific pattern is 1. Under this condition, the number of FETs required in the embodiment is determined as follows: 
     
         l(m+n+3)+2=3(3+1+3)+2=23 
    
     For example, in the case of l=10, m=5 and n=1, if a coincidence decision circuit is constructed similarly to the circuit shown in FIG. 2, it can be constructed of 92 FETs. In any case, even if l, m and n assume any values, the coincidence circuit can be constructed of FETs of the number less than that of FETs required in the conventional coincidence circuit. Further, the circuit shown in FIG. 2 is of negative logic in which the logic signal &#34;0&#34; indicates &#34;coincidence&#34;. But, the present invention can be applied to a positive logic coincidence decision circuit. 
     The invention has thus been shown and described with reference to specific embodiments. However, it should be noted that the invention is in no way limited to the details of the illustrated structures but changes and modifications may be made within the scope of the appended claims.