Abstract:
A method and apparatus to receive and down convert high frequency radio signals to low frequency or base band frequency is disclosed. A mixer used with a sampler produces a multi mode/multi band software enhanced radio receiver capable of supporting multiple air interfaces. The local oscillator of the disclosed mixer is harmonically related to the sampler frequency. A signal is first down converted by the mixer to a lower frequency or intermediate frequency, the signal is then sub sampled by the sub sampler, the signal is then converted to discrete time and all further processes are discrete. Successive decimation, filtering and demodulation in discrete or continuous time achieve selectivity and down conversion to base band.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     (1) Field of the Invention  
         [0002]     The present invention relates to receiver circuits and methods of down converting RF (radio frequency) signals. The present invention also relates to means and methods of down converting RF signals by first converting a radio signal to an IF (intermediate frequency) with a mixer and sampling the signal with a discrete time mixer/sampler block.  
         [0003]     (2) Description of the Related Art  
         [0004]     Several methods of down converting RF signals are known in the related art, and include: 
        (1) Super-heterodyne conversion which uses one or more lower IF to eventually reach the base band.     (2) Direct Conversion which uses a LO (local oscillator) tuned at the center frequency of the desired radio channel to bring the RF signal directly to the base band.     (3) Direct Sampling which uses a sampler at a RF, a method equivalent to the use of a LO.     (4) Sub sampling which uses a sampler operating at relatively lower frequencies.        
 
         [0009]     A block diagram of a typical super heterodyne receiver is shown in  FIG. 1 . An RF signal arriving at an antenna  25  passes through a band filter  100 , a low noise amplifier (LNA)  101  and into an image filter (IMG FLT)  102  which produces a band-limited RF signal that enters a first mixer  103  which transforms the RF signal down to an intermediate frequency (IF) by mixing the RF signal with the signal created by the first local oscillator (LO)  200 . The IF then passes through an IF filter  104  where unwanted mixer signals are removed. The signal then passes into an in phase quadrature sampler (I.Q.)  106 . A second LO  201  sends a frequency signal to an I.Q.  106 . An I.Q.  106  produces a baseband output in phase at  507   b  and quadrature out at  507   c.    
         [0010]      FIG. 2  is a block diagram of a direct sampling receiver, consider as prior art. FIGS.  1  and two are identical from antenna  25  to image filter  102 . For the direct sampling receiver of  FIG. 2 , the output of IMG FLT  102  connects to a sampler  110 . The output of a LO  200  connects to both a sampler  110  and a clock distribution  202 .  
         [0011]     The output of sampler  110  enters an input of a DTP/DSP  300 . The output from a clock distribution  202  also enters an input of a DTP/DSP  300 . The output of a DTP/DSP  300  is the baseband output at  507 .  
         [0012]     The related art fails to provide means or methods of further reducing the number of components used in RF down conversion.  
         [0013]     There is a need in the art for means to reduce the number of IF filtering components while providing sufficient image and alias rejection.  
         [0014]     The related art fails to provide support for the down conversion of several frequency bands by minimal modification to existing receiver circuits.  
         [0015]     There is thus a need in the art for new receiver circuits and new methods of down conversion of RF signals that consume less power, produce less heat, and are more economical to manufacture.  
       BRIEF SUMMARY OF THE INVENTION  
       [0016]     (1) Advantages of the Present Invention  
         [0017]     The present invention overcomes many short falls in the related art by providing extra alias rejection at the front end of the circuit, an advantage that the sub sampling architecture of the related art lacks.  
         [0018]     The present invention provides image and alias rejection while significantly reducing the number of IF filtering components, an advantage not found in the related art.  
         [0019]     The present invention overcomes a shortfall in the related art by eliminating the need for a second frequency source by use of a mixer/sampler clock frequency that is derived by division of the first LO frequency.  
         [0020]     Unlike the related art, the present invention has the ability to support several RF bands with minimal hardware changes to existing devices.  
         [0021]     (2) Summary of the Invention  
         [0022]     The invention achieves new efficiencies in component size, reduces the number of components, and reduces the use of electricity and heat generation by use of a hybrid dual down conversion design where a radio signal is first converted to an intermediate frequency by use of a mixer and is then sampled by a discrete time sampler block. The local oscillator frequency of the first mixer and the clock frequency of the intermediate frequency sampler are harmonically related. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0023]      FIG. 1  is a block diagram of a super-heterodyne receiver considered as prior art.  
         [0024]      FIG. 2  is a block diagram of a direct sampling receiver considered as prior art.  
         [0025]      FIG. 3  is a block diagram of a method, in accordance with the present invention, to down convert high frequency signals to low frequency signals with a mixer and sampler and two separate local oscillators.  
         [0026]      FIG. 4  is a block diagram of a method, in accordance with the present invention, to down convert high frequency signals to low frequency signals with a mixer, sampler and one local oscillator.  
         [0027]      FIG. 5  is a block diagram of a method, in accordance with the present invention, to down convert high frequency signals to low frequency signals with an in phase quadrature sampler (I.Q.), a LO, a mixer, a clock distribution and a DTP/DSP processor.  
         [0028]      FIG. 6  is a block diagram of a detailed view of a DTP/DSP Processor in accordance with the present invention.  
         [0029]      FIG. 7  is a block diagram of a detailed view of a clock distribution and clock interaction with the discrete-time signal processing block in accordance with the present invention.  
         [0030]      FIG. 8  is a signal path in the spectrum or frequency domain for the present invention with general n.  
         [0031]      FIG. 9  is a signal path in the spectrum or frequency domain for the present invention with n=3.  
         [0032]      FIG. 10  is a signal path in the spectrum or frequency domain for the present invention with n=4. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
     Physical Attributes, Operation, and Methods  
       [0033]    
       
         
               
             
               
               
             
           
               
                   
               
               
                   
               
               
                 Definition List 1 
               
             
          
           
               
                 Term 
                 Definition 
               
               
                   
               
               
                 RF 
                 Radio Frequency 
               
               
                 LO 
                 Local Oscillator 
               
               
                 Base Band 
                 The desired signal range obtained after use of the 
               
               
                   
                 disclosed invention. 
               
               
                 IF 
                 Intermediate Frequency 
               
               
                 TX 
                 Transmitter 
               
               
                 VCO 
                 Voltage Control Oscillator 
               
               
                 FLT 
                 Filter 
               
               
                 DT 
                 Discrete Time 
               
               
                 Aliasing 
                 An undesired folded signal 
               
               
                 ADC 
                 Analog to Digital Conversion 
               
               
                 DAC 
                 Digital to Analog Conversion 
               
               
                 ANT 
                 Antenna 
               
               
                 LNA 
                 Low Noise Amplifier 
               
               
                 F 
                 Frequency 
               
               
                 fs 
                 Sampling signal frequency 
               
               
                 n 
                 Integer 
               
               
                 L 
                 Integer 
               
               
                 K 
                 Integer 
               
               
                 IQ 
                 In phase and quadrature sampler 
               
               
                 IMG FLT 
                 Image filter 
               
               
                 BAND FLT 
                 Band filter 
               
               
                 IF FLT 
                 Intermediate frequency filter 
               
               
                 CLK Distr. 
                 Clock distribution 
               
               
                 DTP/DSP Processor 
                 Discrete time processor/discrete signal processor 
               
               
                 DT Flt 
                 Discrete time filter 
               
               
                   
               
             
          
         
       
     
         [0034]     The present invention is described though several embodiments. The preferred embodiment is described in  FIG. 5  which merely serves the purpose of facilitating the description of the principles of the present invention and in no way is meant to limit its scope. Those skilled in the art will realize that many changes and modification can readily be made to the preferred embodiment and alternative embodiments without departing from the principles of the invention.  
         [0035]    
       FIG. 3 
     
         [0036]      FIG. 3  is a block diagram of an RF receiver and down converter in accordance with the principles of the present invention.  FIG. 3  discloses methods and means to down convert high frequency RF signals to low frequency signals with a mixer  103  and two local oscillators  200  and  201 . High frequency signals enter an antenna  25  for coupling the signal into the input of a band filter  100 . The output of band filter  100  connects to the input of a low noise amplifier (LNA)  101 . The output of the LNA  101  connects to the input of image filter  102 .  
         [0037]     The output of image filter  102  connects to the input of mixer  103 . Through connection  250 , the output of the first local oscillator  200  connects to an input to mixer  103 . The output of mixer  103  connects to an input of intermediate frequency (IF) filter  104 . The output of IF filter  104  connects to the input of sampler  105 . The second local oscillator  201  connects via  290  to an input of sampler  105  and to the input of the clock distribution  202 .  
         [0038]     The output of sampler  105  connects to an input of discrete time process/discrete signal processor (DTP/DSP)  300 . Clock distribution block  202  sends output through lines  610 , 611 , and  612  into an input of DTP/DSP  300 . The output of DTP/DSP  300  exits at connection  507  as baseband output.  
         [0039]    
       FIG. 4 
     
         [0040]      FIG. 4  is a block diagram of the present invention using just one local oscillator  200 ( n ) to produce input to mixer  103 . The LO  200 ( n ) signal is divided by n and then utilized by sampler  105  and clock distribution  202 . The value of n is supplied by the clock distribution  202 .  
         [0041]     From antenna  25  to image filter  102 , the physical structure and methods of the receivers in  FIGS. 3 and 4  are identical. In  FIG. 4 , the output of image filter  102  connects to an input of mixer  103 . Local oscillator  200 ( n ) connects to an input to mixer  103  through connection  250 .  
         [0042]     The frequency of LO  200 ( n ) is divided by n from variable divider  203 . The value of n used by variable divider  203  is obtained from clock distribution  202 .  
         [0043]     An output from local oscillator  200 ( n ) is connected via connection  290  to sampler  105 . Clock distribution  202  and LO  200 ( n ) are connected.  
         [0044]     The output from mixer  103  connects to the input of IF filter  104 . The output of IF filter  104  connects to an input of sampler  105 . The output of sampler  105  connects to the input of DTP/DSP processor  300 .  
         [0045]     The output of Clock distribution  202  travels through connections  610 ,  611 , and  612  into DTP/DSP processor  300 . The output of DTP/DSP processor  300  travels through wire  507  and is low intermediate frequency output. A more detailed view of the clock distribution  202  and DTP/DSP processor  300  is found in  FIG. 6 , where the cascading format of the DTP/DSP processor is displayed.  
         [0046]    
       FIG. 5 
     
         [0047]      FIGS. 4 and 5  are identical to the point of IF FLT  104 . The output of IF FLT  104  enters the input of I.Q.  106 . The output of LO  200 ( n ) is divided by n from divider function  203 . The value of n is obtained from clock distribution  203 . After division by n of  203 , the output of LO  200 ( n ) travels through connection  275  to enter an input of I.Q.  106 .  
         [0048]     The two outputs of I.Q.  106  enter DTP/DSP blocks  320  and  321 . Clock distribution  203  sends outputs at  610 ,  611 , and  612  to DTP/DSP blocks  320  and  321  as more particularly illustrated in  FIG. 7 . The  320  portion of DTP/DSP processor produces baseband output in phase at  507   b.  The  321  portion of DTP/DSP processor produces baseband quadrature output at  507   c.    
         [0049]    
       FIG. 6 
     
         [0050]      FIG. 6  is a detailed block diagram of the DTP/DSP processor  300  and clock distribution  202  of  FIG. 4 . The clock distribution provides input to each of the blocks  301 ,  302 , and  303  or i th  blocks. The  301 ,  302 , and  303  blocks comprise a discrete time filter (DT FLT)  310  and a decimation block (M 1 )  311 . The  301 ,  302 , and  303  blocks may be cascading, are connected to one another, and each receive input  610 ,  611 , and  612 , respectively, from the clock distribution.  
         [0051]    
       FIG. 7 
     
         [0052]      FIG. 7  is a detailed block diagram of the DTP/DSP  320  and  321  blocks and clock distribution  203  of  FIG. 5 . The I.Q.  106  provides output at  506   b  and  506   c  to cascading blocks such as  301  comprising a discrete time filter (DT FLT)  310  and a decimation block (M 1 )  311 . The clock distribution  203  sends two output signals through connections  275  to I.Q.  106 .  
         [0053]     The clock distribution sends signals via  610   a,    611   a,  and  612   a  to cascading DT Filter/M ↓  blocks  301 ,  302 , and  303  respectively. There are two parallel strings  320  and  321  of cascading DT Filter/M ↓  blocks. The second string  321  of cascading DT Filter/M ↓  blocks receives timing signals through  610   b,    611   b,  and  612   b.  The final baseband outputs of cascading blocks  320  and  321  are sent to  507   b  and  507   c  respectively. The M ↓  blocks are decimation blocks which decimate every M th  sample.  
         [0054]    
       FIG. 8 
     
         [0055]      FIG. 8 a  signal path in the spectrum or frequency domain for the present invention with general n. The vertical axis denotes amplitude and the horizontal axis denotes frequency.  
         [0056]    
       FIG. 9 
     
         [0057]      FIG. 9  is a signal path in the spectrum or frequency domain for the present invention with n=3. The vertical axis denotes amplitude, and the horizontal axis denotes frequency.  
         [0058]      FIG. 10  is a signal path in the spectrum or frequency domain for the present invention with n=4. The vertical axis denotes amplitude, and the horizontal axis denotes frequency.  
         [0000]     Further Advantages and Details  
         [0059]     As shown in the included drawings, at the mixer/sampler block the signals may be processed in discrete time at a lower clock rate than a direct sampling approach would require. The disclosed invention offers two main approaches for further signal processing; 
        1. A quadrature mixing/sampling design in which the mixer/sampler is operating with 90 degree offset time clocks. Two separate real signal paths are used with this approach. Low Pass (instead of band pass) discrete-time or continuous time filters may be used. Depending upon the placement of the IF, the output of this cascade may be located either Base Band or at a low IF.     2. A cascade of discrete time stages each features a filter/decimator. By optimizing the filtering and decimation functionality, each successive stage may operate in progressively lower clock frequencies, conserving power. If desired, at some point in the cascade a quadrature demodulator may be used to convert the signal to Base Band is a similar manner as described in approach 1 above.        
 
         [0062]     This invention discloses a method and apparatus for down converting high frequency FR signals to base band though the use of a hybrid mixer/sampler with the following variations: 
        1. A mixer may operate at the same rate as the mixer/sampler (n=1) while subsequent decimation brings the processing clock down by the decimation ratio.     2. The IF placement is close but not at fS/4. By using this option a very-low-IF (VLIF) complex conversion may be employed. This alternative will address various impairments such as 1/f device noise, 2 nd  order inter-modulation effects and DC offsets.     3. The mixer/sampler may be replaced by a continuous time mixer. This results in a complete continuous time domain solution in which the RF mixer and the IF mixer LOs are related pursuant to the principles of the disclosed invention.