Abstract:
A sample and hold circuit including a sampling capacitor for storing a sample of an input signal, an output stage for outputting the sample stored on the sampling capacitor; and input circuitry for sampling the input signal and storing the sample on the sampling capacitor. The input circuitry includes an autozeroing input buffer which selectively samples the input signal during a first operating phase and holds a sample of the input signal during a second operating phase. The autozeroing input buffer cancels any offset error. The input circuitry also includes switching circuitry for selectively coupling the sampling capacitor with an input of the sample and hold circuitry during the second operating phase and to an output of the autozeroing input buffer during the first operating phase.

Description:
FIELD OF INVENTION 
   The present invention relates in general to mixed signal processing and in particular to sample and hold circuits and methods with offset error correction and systems using the same. 
   BACKGROUND OF INVENTION 
   Data acquisition systems, such as analog to digital converters (ADCs), normally include a front-end sample and hold stage for capturing an input signal. Typically, this sample and hold stage is implemented with a switched-capacitor circuit in which a sampling capacitor is switched between sampling and integrating modes. Generally, during the sampling mode, the input signal is sampled onto the sampling capacitor and during the integration phase, the charge on the sampling capacitor is transferred to an integrating capacitor. 
   In order to maintain a high dynamic range, the sampling capacitor in switched-capacitor circuits, such as sample and hold stages, must be large to minimize 
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noise. Therefore, high dynamic range sample and hold circuits require that the input signal source be capable of delivering a relatively large current for rapidly charging the large sampling capacitor. In high sampling rate applications, such as delta sigma ADCs, this current requirement becomes even more severe due to the relatively small amount of time available during each sampling event to charge the sampling capacitor. Furthermore, the sampling current is often nonlinear due to charge injection and nonlinear input impedances caused by the switching circuitry controlling the charging of the sampling capacitor, which in turn mandates severe linearity requirements on the input signal source. Finally, the sampling current must settle quickly to avoid distortion as a sequence of samples of the input signal are taken.
 
   In sum, new techniques are required for use in high dynamic range data acquisition systems. These techniques should address the problems related to the use of large sampling capacitors, especially at high sampling rates. 
   SUMMARY OF INVENTION 
   The principles of the present invention are embodied in sample and hold circuits utilizing input buffers which include automatic offset compensation capability. According to one particular embodiment of these principles, a sample and hold circuit is disclosed which includes a sampling capacitor for storing a sample of an input signal, an output stage for outputting the sample stored on the sampling capacitor, and input circuitry for sampling the input signal and storing the sample on the sampling capacitor. The input circuitry includes an autozeroing input buffer which selectively samples the input signal during a first operating phase and holds a sample of the input signal during a second operating phase. The autozeroing input buffer cancels any offset error. The input circuitry also includes switching circuitry for selectively coupling the sampling capacitor with an input of the sample and hold circuitry during the first operating phase and to an output of the autozeroing input buffer during the second operating phase. 
   The principles of the present invention realize substantial advantages over the prior art, particularly when embodied in a sample and hold stages and similar circuits operating at relatively high oversampling rates. These principles allow for a substantial reduction of the loading on the input signal source by increasing the input impedance of the embodying circuit or system. Additionally, linearity of the circuit system is improved as a result of a substantial reduction in non-linear charge drawn from a signal source. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
     For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a block diagram of an exemplary analog to digital converter (ADC) system suitable for describing the practice of the principles of the present invention; 
       FIG. 2  is an electrical schematic diagram of a conventional differential sample and hold circuit; 
       FIG. 3  is an electrical schematic diagram of an exemplary sample and hold circuit embodying the principles of the present invention; 
       FIG. 4  is a more detailed electrical schematic diagram of a representative unity gain input buffer embodying the inventive principles and suitable for utilization as the unit gain input buffers shown in  FIG. 3 ; and 
       FIG. 5  is a timing diagram illustrating an exemplary operating sequence of the sample and hold circuit shown in  FIGS. 3 and 4 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The principles of the present invention and their advantages are best understood by referring to the illustrated embodiment depicted in  FIGS. 1–5  of the drawings, in which like numbers designate like parts. 
     FIG. 1  is a high-level block diagram of a single-chip audio analog-to-digital converter (ADC)  100  suitable for practicing the principles of the present invention. For illustrative purposes, ADC  100  is a delta-sigma ADC, although the present inventive principles are applicable to other types of ADCs, as well as digital-to-analog converter (DACs) and Codecs. 
   ADC  100  includes N conversion paths  101   a, b , . . . N, of which two paths  101   a  and  101 N are shown for reference, for converting N channels of differential analog audio data respectively received at analog differential inputs AINN+/−, where N is an integer of one (1) or greater. The analog inputs AINN+/− for each channel are passed through an input sample and hold  110  and then a delta-sigma modulator  102  which performs noise shaping on the sampled input stream. 
   Each delta-sigma modulator  102  is represented in  FIG. 1  by a summer  103 , low-pass filter  104 , comparator (quantizer)  105 , and DAC  106  in the delta-sigma feedback loop. The outputs from delta-sigma modulators  102  are each passed through a digital decimation filter  107 , which reduces the sample rate, and also a low pass filter  108 . Delta sigma modulators  102  sample the corresponding analog input signals at an oversampling rate and output digital data in either single-bit or multiple-bit form, depending on the quantization, at the oversampling rate. The resulting quantization noise is shaped and generally shifted to frequencies above the audio band. 
   The resulting digital audio data are output through a single serial data port SDATA of serial output interface/clock generation circuitry  109 , timed with a serial clock (SCLK) signal and a left-right clock (sample) signal (LRCLK). In the slave mode, the SCLK and LRCLK signals are generated externally and input to ADC  100  along with the master clock (MCLK) signal generated by an external clock source  112 . In the master mode, the master clock (MCLK) signal is generated from an external crystal  111  and thereafter utilized on-chip to generate the SCLK and LRCK signals, which are then output along with the corresponding serial data. 
     FIG. 2  is an electrical schematic diagram of a conventional differential sample and hold circuit  200  including a pair of sampling capacitors (C s )  101   a  and  101   b , and an operational amplifier integrator stage including an operational amplifier  202  and integration capacitors (C i )  203   a  and  203   b . Sample and hold circuit  200  operates in two phases, labeled φ 1  and φ 2 , with a phase φ 1  having fine and rough sub-phases, respectively labeled φ 1R  and φ 1F . 
   During sampling phase φ 1 , switches  204   a  and  204   b , each couple a corresponding plate of sampling capacitors  201   a  and  201   b  to a common mode voltage V cm . Then during rough sampling sub-phase φ 1R , the input voltage across inputs V in+  and V in−  is sampled onto node A and node B through input buffers  207   a  and  207   b  through switches  208   a  and  208   b . During the subsequent fine sampling sub-phase φ 1F , switches  208   a  and  208   b  open and the charging of node A and node B is completed directly from the inputs V in+  and V in−  through switches  209   a  and  209   b.    
   During the integration phase φ 2 , switches  204   a  and  204   b  open and switches  205   a – 205   b  and  206 – 206   b  close. Consequently, the charges on nodes A and B are transferred to integrator capacitors  203   a  and  203   b  at the inverting (−) and non-inverting (+) inputs to operational amplifier  202 . 
   In the conventional circuit of  FIG. 2 , input buffers  207   a  and  207   b , which charge sampling capacitors  201   a  and  201   b  during rough sampling sub-phase φ 1R  are typically continuous time buffers having a unity gain configuration for improving the linearity of the charging operation. When buffers  207   a – 207   b  are continuous time buffers, buffers  207   a – 207   b  normally include input pairs of back-to-back P-channel and N-channel transistors to accommodate relatively large swings in the input voltage V in . These input transistor pairs introduce a signal-dependent offset component which in turn can cause distortion during the sampling operation. 
   Conventional sample and hold circuit  100  shown in  FIG. 1  also includes a pair of AC-coupling capacitors at  210   a – 210   b  in series with the source of the input signal V in . Generally, AC-coupling capacitors  210 – 210   b  act as high-pass filters which attenuate very low frequency components in the input signal and the DC offset in the input voltage V in . However, AC-coupling capacitors  210   a – 210   b  charge-share any air charge introduced by buffers  207   a – 207   b  during φ 1R  sub-phase. The result is a summation of both common mode and differential error charge on AC-coupling capacitors  210   a – 210   b . In turn, error charge summation on AC-coupling capacitors  201 – 210   b  causes severe linearity and dynamic range limitations on sample and hold circuit  100 . 
   In order to alleviate problems with error charge summation on AC-coupling capacitors  210 – 210   b , in exemplary the configuration of  FIG. 2  conventional sampler and hold circuit  200  includes a pair of shunt resistors  211   a – 211   b . Generally, shunt resistors  211   a – 211   b  are sized inversely proportional to the expected magnitude of the error introduced by buffers  207 – 207   b  in each sampling cycle to draw current from the input nodes and thereby prevent error summation. However, shunt resistors  211   a – 211   b  reduce the input impedance of sample and hold circuit  200  and further load the input signal source. 
     FIG. 3  is an electrical schematic diagram of a representative sample and hold circuit  300  according to one embodiment of the principles of the present invention. Sample and hold circuit  300  is suitable in applications such as sample and hold stages  101   a – 101   b  of ADC  100  shown in  FIG. 1 . 
   Sample and hold circuit  300  includes a pair of auto-zeroing unity gain buffers  301   a – 301   b  associated with the corresponding inputs V in+  and V in− . Auto-zeroing unity gain buffers  301   a – 301   b  will be discussed in further detail below in conjunction with  FIG. 4 . Generally, however, during the rough sampling sub-phase φ 1R , unity gain buffer  301   a  drives node A at sampling capacitor  201   a  from input V in+  while unity gain buffer  301   b  drives node B at sampling capacitor  201   b  from the input V in− . Using a double sampling scheme, during rough sub-phase φ 2R  of integration phase φ 2 , unity gain buffer  301   a  drives node B and unit gain buffer  301   b  drives node A to force the charge from sampling capacitors  201   b  and  201   a  to integration capacitors  203   b  and  203   a . During fine sub-phases φ 1F  and φ 2F  of both sampling phase φ 1  and integration phase φ 2 , unity gain buffers  301   a – 301   b  bypassed and node A and node B are driven directly from the inputs A in+  and A in− . The selective coupling of nodes A and B to the outputs of unity gain buffers  301   a – 301   b  or directly to the inputs A IN+  and A IN−  is controlled by a set of switches  302   a – 302   b ,  303   a – 303   b ,  304   a – 304   b  and  305 – 305   b  of  FIG. 3 . The preferred operation of these switches, and sample and hold circuit  300  as a whole, will be discussed further in conjunction with the timing diagram of  FIG. 5 . 
     FIG. 4  is a more detailed electrical schematic diagram of a selected one of the auto-zeroing unit gain buffers  301  shown in  FIG. 3 . Buffers  301  operate in response to two control signals labeled ROUGH and FINE. The control signal ROUGH is active during both rough sampling sub-phase φ 1R  and rough integration sub-phase φ 2R . The control signal FINE is active during both fine sampling sub-phase φ 1F  and integration fine sub-phase φ 2F . 
   One advantage of the embodiment of unit gain buffers  301   a – 301   b  shown in  FIG. 4  is its capability of self-canceling the voltage offset V OS  generated by amplifier  401 . Other auto-zeroing buffers could be used in alternate embodiments. 
   Auto-zeroing buffer  301  includes a buffer hold capacitor (C HB )  402  and a buffer sampling capacitor (C SB ) and a set of controlling switches  404 – 407  responsive to the control signals FINE and ROUGH. 
   During the buffer sample phase, the ROUGH signal is inactive and the FINE signal is active. Consequently switches  404  and  405  open and switches  406  and  407  close. In this configuration, sampling capacitor  403  charges to approximately V CSB =V IN −V OS , relative to the common mode voltage coupled to the non-inverting (+) amplifier input. Hold capacitor  402  charges to approximately V CHB =V OS −)V IN , in which)V IN  is the change in V IN  from the last sample to the current sample. The buffer output voltage V OUTB  is disregarded during this phase. 
   During the buffer hold phase, the ROUGH signal is active and the FINE signal is inactive. In this state, switches  404  and  405  are closed and switches  406  and  407  are open. As a result, the buffer output voltage V OUTB  is pulled by sampling capacitor  403 , relative to the common mode voltage, to V OUTB =V IN −V OS +V OS , such that the offset voltage V OS  is cancelled at the output of buffer  301  relative to the common mode voltage. 
   The embodiment of unity gain buffers  301  shown in  FIG. 4  realizes substantial advantages. The auto-zero error cancellation function acts to cancel both static and signal dependent offset. Any residual error component is only due to charge injection of switches  407  ( FIG. 4) and 302   a – 302   b  ( FIG. 3 ), and consequently is minimized by minimizing switch sizes. Furthermore, sampling capacitor  403  only samples changes in the input signal V IN  from sample to sample. This is particularly advantageous in over-sampled systems operating at high sampling rates since the charge provided by the signal source is substantially reduced along with the signal source loading. 
   The overall operation of sample and hold circuit  300  of  FIG. 3  is now described in further detail in conjunction with the timing diagram of  FIG. 5 . 
   At the start of the sampling phase, the φ 1A  control signal is active and the φ 2A  signal inactive, such that switches  204   a – 204   b  close and  206   a – 206   b  open to allow charge transfer on to sampling capacitors  201   a – 201   b . Next, during rough sampling phase φ 1R , switches  302   a  and  302   b  close to couple the outputs of unity gain buffers  301   a – 301   b  to node A and node B, respectively. Switches  303   a – 303   b ,  304   a – 304   b  and  305   a – 305   b  open. During the rough sampling phase φ 1R , the signal ROUGH is active and the signal FINE inactive such that unity gain buffers  301   a  and  301   b  are in the hold state. Unity gain buffers  301   a – 301   b  consequently roughly charge sampling capacitors  201   a – 201   b.    
   During sampling fine sub-phase φ 1F , switches  302   a – 302   b  open and switches  303   a – 303   b  close and the charging of sampling capacitors  201   a – 201   b  is completed directly from the signal inputs V IN+  and V IN− . After a small delay, the ROUGH control signal transitions to an inactive state and FINE transitions to active state. Sampling capacitors  403  of each unity gain buffer  301   a  and  301   b  are then updated as described above. The outputs from unity gain buffers  301   a – 301   b  are discarded during the fine sampling sub-phase. At the end of the fine sampling sub-phase φ 1F , switches  303   a  and  303   b  open. 
   During the integration phase, control signals φ 1A  and φ 2A  open switches  204   a – 204   b  and close switches  206   a – 206   b  to enable the charge to transfer from sampling capacitors  201   a – 201   b  to integrated capacitors  203   a  and  203   b . Switches  304   a  and  304   b  close in response to control signal φ 2R  to cross-couple the output of unity gain buffer  301   a  to node B and unity gain buffer  301   b  to node A to implement double sampling. After a small delay, the ROUGH control signal transitions to an active state and the FINE control signal transitions to an inactive state such that unity gain buffers  301   a – 301   b  enter the hold state for driving node B and node A respectively. 
   During the fine integration phase, switches  304   a – 304   b  re-open to disconnect unity gain buffers  301   a – 301   b  from nodes B and A. The control signal φ 2F  closes switches  305   a  and  305   b  to cross-couple the input V IN+  with node B and input V IN−  to node A. The integration phase is then completed by driving sampling capacitors  201   a – 201   b  directly from the input V IN−  and V IN+ . Concurrently, the FINE signal transitions to active state and the ROUGH signal to an active state. Unity gain buffers  301   a – 301   b  therefore update the charge on corresponding buffer sampling capacitors  403 . 
   The process illustrated in  FIG. 5 , which utilizes both fine and rough sub-phases in each of the sampling and integration phases, repeats itself to continuously sample the input signal V IN . Advantageously, both the static and signal dependent offsets in unity gain buffers  301   a – 301   b  are removed with the auto-zeroing technique described above. As previously indicated, charge injection errors are minimized by utilizing small switches to implement each unity gain buffer  301   a – 301   b . Therefore, in the ac-coupled mode, the errors introduced by unity gain buffers  301   a – 301   b  are minimized. Distortion related to error summation is also substantially reduced. Any residual error can be prevented using relatively large shunt resistors which minimize the loading on the input signal source. 
   In sum, the principles of the present invention realize substantial advantages, particularly when embodied in a sample and hold stages and similar circuits operating at relatively high oversampling rates. These principles allow for a substantial reduction of the loading on the input signal source by increasing the input impedance of the embodying circuit or system. Additionally, linearity of the system is improved as a result of a substantial reduction in non-linear charge drawn from a signal source. Actual implementation of the inventive principles requires a minimal number of external components and is completely transparent to the end user. 
   While a particular embodiment of the invention has been shown and described, changes and modifications may be made therein without departing from the invention in its broader aspects, and, therefore, the aim in the appended claims is to cover all such changes and modifications as fall within the true spirit and scope of the invention.