Abstract:
A bit line selector switch is serially connected with a data sink for detecting high speed data transmissions, typically in the gigabit-per-second range, and a backplane having a plurality of data lines. The selector switch incorporates a selector circuit that operates in one of two modes, a first “selected”, or ON, mode and a second “not selected”, or OFF, mode. The selector circuit includes one, preferably differential, input. In one embodiment, a selector switch has a plurality of selector circuits thus allowing the switch to operate in both modes simultaneously. Data coupled to a differential input of the selector circuit will, when operating in the “selected” or ON mode, transmit the data to the data sink which be, for example, a memory device, processor, or the like. In the “not selected” or OFF mode, the selector circuit will pass any data received to a positive supply rail. Regardless of the mode of operation, the selector circuit presents to the coupled data lines an impedance which matches that of the data path coupling the selector circuit to the data line. The selector switch, which typically is comprised of four or less differential inputs, and thus a corresponding number of selector circuits, may be combined with other similar switches to form a multistage switch.

Description:
FIELD OF THE INVENTION 
     The invention relates to a selector switch which may be configured as a distributed crossbar switch with redundancy or used to detect serial data at gigabit-per-second (Gb/s) rates from a selected one of a plurality of data lines. 
     BACKGROUND TO THE INVENTION 
     With the advent of the dawn of the Information Highway and the explosion of telecommunications, the quantity and speed of data transmission continues to grow. In the telecommunications industry, as well as in the computer industry, there exists a need to transmit large quantities of data from point to point such as, for example, between memory and processors in a multi-processor computer. The large number of data bits coupled with the large number of connections create an interconnect bottleneck which requires large numbers of data drivers necessitating a large amount of electrical power. To overcome this interconnect congestion large numbers of parallel bit streams can be multiplexed to higher rate serial bit streams, thus reducing the number of electrical connections that need to be made. The need for low power multiplex and demultiplex circuits capable of combining data signals at high transmission rates, from 50 Mb/s to 1 Gb/s for example, has attracted a number of commercial integrated circuit vendors. Nevertheless, the computer and communications industry continues to search for lower power solutions. 
     A technique that has been employed with some success to reduce the number of interconnections in communications switching equipment is the employment of contactless, or non-contact, backplanes (the backplanes being sets of data lines). Non-contact backplanes permit point-to-multipoint and multipoint-to-point data transmission over a passive backplane without loss of signal integrity due to the multipoint connections. With this technique, distribution of multi-Gb/s serial data is achieved through a form of AC coupling of such small proportions that the data information is contained in the data transitions. It is not uncommon for the received data at the demultiplex circuit to be considerably attenuated by using this technique. Signal levels of only 70 mV peak to peak, or even less, are not uncommon. Reliable reception of the data requires special techniques including signal amplification, wide frequency bandwidth, matched input impedance and some form of hysteresis to discriminate against unwanted noise signals. Moreover, the resultant signal may need to be restored to Non-Return to Zero (NRZ) format from a Return to Zero (RZ) format. A receiver capable of such techniques is disclosed in U.S. Pat. No. 5,852,637 issued on Dec. 22, 1998 to Brown et al; U.S. patent application Ser. No. 09/054,440 filed Apr. 3, 1998 for “A Multi-Gb/s Data Pulse Receiver”; U.S. patent application Ser. No. 09/071,117 filed on May 4, 1998 for “Method and Apparatus for Performing Data Pulse Detection”; and U.S. patent application Ser. No. 09/238,893 filed on Jan. 28, 1999 for “Data Pulse Receiver”, the contents of each of which are hereby incorporated herein by reference. 
     The application of a multi-Gb/s data pulse receiver (a “MGDP Receiver”) to enable the reception of RZ (return to zero) pulses from the AC couplers of the contactless backplane has permitted the performance of reliable point to multipoint distribution of high speed data buses in the Gb/s range. The AC coupling technique is based on directional coupling principles wherein data transfer occurs between proximate conductors. An example of one such coupling connector is described in U.S. Pat. No. 5,432,486 which issued Jul. 11, 1995 to Wong and assigned to Northern Telecom Limited. Typical bit error rate measurements per data line have been estimated to be as low as 10 −21 . 
     However, a problem with known non-contact backplane distribution systems is that they are limited to providing point to multipoint and multipoint to point applications and do not provide switching or redundancy. 
     We have recognised that it would be desirable to combine a non-contact backplane distribution system with a selector switch for selecting a data line from a plurality of data lines (hereinafter a “bit line selector switch” or “switch”). The result would be a distributed crossbar switch with redundancy (i.e. no central switch fabric) that provides multicast and linear growth capabilities. However, current bit line selector switches are ill-suited for use in such a distributed cross-bar switch as they cause spurious reflections at the interface with the data lines. These reflections would lower the signal integrity and also limit the multicast ability of the cross-bar switch as the reflections induced by the bit line selector switch will corrupt the signals transmitted on the plurality of data lines affecting other receivers downstream. 
     SUMMARY OF THE INVENTION 
     The present invention relates to a bit line selector switch connected to a backplane to form a distributed crossbar switch. The cross-bar switch, which has no central switch fabric, provides redundancy and multicast and linear growth capability. 
     A selector switch is in non-contact communication, via a form of AC coupling, with at least one of the data lines forming the backplane. In an alternative embodiment, the selector switch is in non-contact communication with several of the data lines forming the backplane. The selector switch may also be combined with a converter for converting an RZ signal to the NRZ format prior to the transmission of the data pulse to a data sink such as, for example, a memory device, another processor, or the like (in which case the data sink does not effect this conversion). 
     The selector switch presents to an incoming signal, that is, a data pulse, an impedance that matches that of the input data line regardless of whether or not the data line input to the selector switch is to be selected. This impedance matching is accomplished by having two modes of operation of the selector switch. These two modes of operation may be enabled by connecting a resistor, which matches the impedance of the input data line, connected to two grounded base amplifiers, in parallel with each other, whose emitters are both connected to the other end of the resistor. If the input to the selector switch is a differential input, this resistor and parallel amplifier configuration is repeated for each side of the differential input. 
     In the first mode of operation, the OFF or “not selected” mode, a data line is not selected for reception and transmission of the data pulse to the data sink. In this mode of operation, the signal is transmitted first through the resistor and then into one of the grounded base amplifiers which will have its collector connected to a positive power supply. In this way, any signals received in this mode will be ignored by the system. 
     In the second mode of operation, the ON or “selected” mode, a data line is selected for reception and transmission to, if incorporated, the RZ to NRZ converter, and then the data sink. In this mode an incoming signal is transmitted first through the resistor and then through the other grounded based amplifier to the converter, if incorporated, then to the data sink. 
     The selector switch&#39;s mode may be dependent upon the reference bias voltages applied to the base of the amplifiers. In the first mode of operation the bias voltage applied to the amplifier connected to the positive supply is higher than that of the second bias voltage applied to the base of the second amplifier. In the second mode of operation the opposite is true. 
     According to one aspect of the invention there is provided a combined bit line selector switch and data pulse receiving system comprising: a plurality of data lines for the propagation of data pulses; and a bit line selector switch interconnecting the plurality of data lines and the receiver. The bit line selector switch comprises: switch inputs in non-contact communication with the plurality of data lines by a plurality of data line interconnects; and a switch output in communication with the receiver. For each of the switch inputs there is a selector circuit between each of the switch inputs and the switch output which have a first mode of operation wherein data pulses detected by the selector circuit are blocked and a second mode wherein the data pulses detected by the selector circuit are transmitted; and the at least one input selector circuit matching the impedance of the data line interconnect in either the first or the second modes. 
     Another aspect of the invention is a crossbar switch comprising: N data lines for propagation of data pulses; a receiver receiving the data pulses; a bit line selector system in non-contact communication with each of the N data lines so as to interconnect the receiver and the data coupling lines. The bit line selector system is operable to transmit the data pulses from a selected one of the N data lines to the receiver and to simultaneously block data pulses on the remaining N−1 data lines. The bit line selector system has N inputs corresponding to the N data coupling lines and an output in communication with the receiver. Moreover, the selector system matches the impedance of said N data coupling lines. 
     The selector system of this crossbar may be comprised of several stages, each stage being comprised of at least one selector switch in communication with another stage which is also comprised of at least one selector switch. Each selector switch of the selector system is in non-contact communication with either the backplane or with selector switches of another stage. Each of the selector switches in this staged crossbar switch operate in either of the two modes described above and have the same impedance matching characteristic. 
     Another aspect of the invention is a method of selecting one of a plurality of high throughput data lines comprising: inputting data pulses received on a selector switch which is coupled to the plurality of data lines; selecting, in a first mode of operation of the selector switch, one of the data lines and transmitting the data pulses received by the selector switch on the selected data line to a receiver; in a second mode of operation of the selector switch transmitting data pulses from the non-selected data lines to a positive supply; and matching the impedance of input lines into the selector switch in either said first or said second modes of operation. 
     Another aspect of the invention is a selector switch comprising: an input in communication with a data line; an output; and a selector circuit interconnecting the input to the output. The selector circuit is operable in a first mode to transmit data pulses received at the input from the data line to the output and operable in a second mode to discard data pulses received at the input from the data line. The selector circuit also matches the impedance of the data line in the first and the second modes of operation. 
    
    
     Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of a specific embodiment of the invention in conjunction with the accompanying figures. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more clearly understood after reference to the following detailed specification read in conjunction with the drawings wherein: 
     FIG. 1 is schematic of a signal transmission and receiving system in accordance with one embodiment of the invention; 
     FIG. 2 is a schematic detail of a portion of FIG. 1; 
     FIG. 3 is a schematic detail of a portion of FIG. 1; and 
     FIG. 4 is a schematic detail of a second embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     To avoid deleterious reflections in an arrangement with a bit line selector switch located physically between backplane microwave couplers and a data sink requires that the data path between backplane microwave couplers and the data sink, such as, for a example, a memory device (such as random access memory, fixed or removable storage devices, processors, or the like) receiving selected data pulses have some form of transmission line with a typical characteristic impedance of, for example, 50Ω. Such a physical arrangement would require that this data path be terminated by the selector switch with a well matched termination impedance. Indeed, the characteristic impedance of the selector switch must match that of the data path whether the switch is ON or OFF; also, the parasitic capacitance of the selector switch must be low enough so as to not impair the matched impedance and so cause spurious energy reflections in the data path. If the selector switch, in the OFF position, does not terminate the data path with the data path&#39;s characteristic impedance, the selector switch will cause spurious energy to be reflected back to the contactless backplane thus lowering the backplane&#39;s signal integrity. 
     Referencing FIG. 1, a selector switch system  10  for detecting and selecting serial multi-Gb/s data pulses is illustrated. As illustrated, combination system  10  is comprised of a data pulse data sink  16 , which may be, for a example, a memory device (such as random access memory, fixed or removable storage devices) processors, or the like, in communication with a backplane  12  via a non-contact bit line selector switch Application Specific Integrated Circuit (ASIC)  14 . Backplane  12  has a plurality of, as illustrated sixteen, data lines  18 A- 18 P (generally referred to as data lines  18 ). Selector switch ASIC  14  is in communication with each of data lines  18  by a plurality of data line interconnects, which may be microwave couplers  22 . As illustrated, and, for exemplary purposes only, system  10  allows for communication between a plurality of processors (not shown) connected to backplane  12  and data sink  16  connected to selector switch ASIC  14  via data communication path  20 . 
     In operation of system  10 , data propagates from a, or a plurality of, processor(s) (not shown) through data lines  18  of backplane  12 . By operation of selector switch ASIC  14 , data is received from a data line  18  selected by selector switch ASIC  14 , through a form of AC coupling of data lines  18  and couplers  22 , and transmitted to data sink  16  over data path  20 . 
     With reference to FIG. 2, selector switch ASIC  14  is shown in further detail as being comprised of a plurality of selectable input switches  24 A- 24 D (collectively, first selector switches  24 ),  26 A- 26 D (collectively, second selector switches  26 ) on a first switching stage, and  28  on a second switching stage. Each of selectable input switches  24 ,  26  and  28  incorporate impedance matching circuitry in the form of selectable input circuit  30 A,  30 B. In the exemplary embodiment a central, or second stage, selector switch  28  is connected to two 4:1 multipoint-to-point input non-contact buses  21  and  23 . In non-contact communication with non-contact bus  21  are four selector switches  24 A,  24 B,  24 C and  24 D which are identical to selector switch  28 . Similarly, in non-contact communication with non-contact bus  23  are four selector switches  26 A,  26 B,  26 C and  26 D which are also individually equivalent to selector switch  28 . As noted above, each of the four first selector switches  24  and the four second selector switches  26  are in non-contact communication with backplane  12 . 
     In the configuration illustrated in FIG. 2, which is only exemplary of one embodiment of the invention, the interaction of selector switch  28  with selector switches  24  and  26  permits the selection of one of the sixteen data lines  18  thus forming a crossbar switch. 
     The exemplary embodiment of FIG. 2 is illustrated as having two cascading stages of selector switches (one stage formed by switches  24  and  26 , and the other stage formed by switch  28 ). However, as will be obvious to those skilled in the art, the impedance matching ability of these selector switches enables the addition of further stages of cascaded switches since reflections caused by the switches have been reduced. The addition of additional switches, either on an existing stage, or by the addition of a further stage of switches, provides for growth and, through the multiplexing of a multiple switches and/or stages of switches, the system  10  (FIG. 1) provides for multicast capability. 
     Referencing FIG. 3, selector switch  28  is illustrated in detail. As noted above, selector switches  24  and  26  are identical to selector switch  28 . Selector switch  28  comprises a selectable input circuit  30 A connected via outputs  36 ,  38  to RZ to NRZ converter  32 . Selectable input circuit  30 A operates, as described below, to preferably match the impedance of one of input non-contact buses  21  and  23  (FIG.  2 ). Similarly, selectable input circuits  30 A of selector switches  24 ,  26  operate to preferably match the impedance, in all modes of operation, of data lines  18 . 
     Selectable input circuit  30 A is also connected to a positive supply rail  34  by paths  40  and  42 . RZ to NRZ converter  32  is also in communication with a hysteresis control circuit (not shown), such as, for example, the hysteresis control circuit disclosed in the cited and incorporated references. 
     Selectable input circuit  30 A is comprised of differential inputs input 1    62  and input 2    64  in series with terminating resistors R 1 ,  58 , and R 2 ,  60 , respectively. Although a differential input, such as differential inputs  62  and  64  for is preferably, an alternative embodiment using non-differential inputs could be used. However, the use of non-differential inputs may impact performance of the circuit. Inputs  62 ,  64  of selectable input circuit  30 A are in communication with one of non-contact buses, such as, for example, non-contact bus  21 . Terminating resistors R 1   58  and R 2   60  are connected in series with grounded base amplifier transistors Q 1   54 , and Q 2   56 , respectively, which in turn are connected to outputs  36  and  38 , respectively. Connected in parallel with grounded base amplifiers Q 1 , Q 2 ,  54 ,  56 , respectively, are transistors Q 5 ,  50 , and Q 6 ,  52 , respectively, which are connected to power supply rail  34 . Applied to the base of transistors  50  and  52  is bias control voltage 1    80 . Similarly, applied to the base of grounded base amplifiers Q 1   54  and Q 2   56  is bias control voltage 2    82 . Suitable properties of these components are described in detail in U.S. Pat. No. 5,852,637 incorporated herein 
     Selectable input circuit  30 B, shown in dotted outline and constructed in the same manner as selectable input circuit  30 A, is required to select between the other of non-contact buses  21  and  23 , which, in the above example, would be non-contact bus  23 . Selectable input circuit  30 B, is also connected to power rail  34  via paths  40 B and  42 B, and to RZ to NRZ converter  32  via outputs  36 ,  38 , and has inputs  86 ,  88  and bias control voltage (BV 3 )  90  and bias control voltage (BV 4 )  92 . 
     RZ to NRZ converter  32  is comprised of a flip-flop itself comprised of transistors Q 3   66  and Q 4   68  which are in communication with a suitable hysteresis control circuit (not shown). Transistors  66  and  68  are also connected to power supply rail  34  via terminating resistors R 3   44  and R 4   46 . Output  84  of selectable switch  28  is the differential voltage measured across the data lines connecting transistors Q 3   66  and Q 4   68  to resistors R 3   44  and R 4   46  and the output is transmitted to data sink  16  via data path  20  (FIG.  1 ). Data sink  16 , upon receipt of a data pulse transmitted from converter  32 , operates in a conventional manner. 
     As noted above, for a selector switch, such as selector switch  28 , to properly operate when serially interposed between a microwave coupler, such as coupler  22 , and data sink  16 , the selector switch preferably matches the termination impedance of data path  20 . This requirement is satisfied by input matching impedance terminating resistors R 1   58  and R 2   60 . 
     Referencing FIGS. 2 and 3, the selector switch  28  may select one of two separate inputs, such as non-contact buses  21  and  23 , by the suitable operation of selectable input circuits  30 A and  30 B. As illustrated in FIG. 3, selector switch  28  is comprised of two selectable input circuits  30 A and  30 B. However, the number of selector circuits that may form part of selector switch  28  is theoretically unlimited but, for practical considerations, may be limited to four. The choice of four pairs of differential inputs (and thus four selectable input circuits) to a module incorporating selector switch  28  is suggested by the combined capacitive loading of the four input circuits at the juncture of the RZ to NRZ conversion flip-flop. Additional pairs of differential inputs may overly attenuate the minute signal current pulses at this juncture. Moreover, when using flip-chip packaging, the physical location of the four input circuits can be located on all four sides of the RZ to NRZ conversion flip-flop thus keeping the path delays from all four inputs identical and minimal. The minimal delay is important in the context of subsequent clock/data timing alignment. 
     Selectable input circuit  30 A effectively has two modes of operation: a “not selected” (or OFF) mode and a “selected” (or ON) mode. In the “not selected” mode, selectable input circuit  30 A will have bias control voltage 1    80 , which is applied to the base of transistors Q 5   50 , and Q 6   52  being greater than the reference bias voltage 2    82 , which is applied to grounded base amplifier transistors Q 1   54  and Q 2   56  (i.e. BV 1 &gt;BV 2 ). In this “not selected” mode, a data pulse current received via input resistors R 1   58  and R 2   60  will be steered to the positive supply rail  34  via transistors Q 5   50  and Q 6   52  on paths  40  and  42 . To effectively accomplish this steering, the difference between bias control voltage 1    80  and bias control voltage 2    82  may be as small as  200  mV in practice. There is, therefore, no excessive current in resistors R 1   58  and R 2   60  during the “not selected” mode. Further, when selectable input circuit  30 A is operating in the “not selected” mode, any input energy appearing at the emitters of transistors Q 1   54  and Q 2   56  is not transferred to the collectors of Q 1   54  and Q 2   56  since the bases (i.e. emitter base diodes) of these transistors are biased below the turn-on threshold. Instead, in the “not selected” mode any input data current passes through transistors Q 5   50  and Q 6   52  to supply rail  34 . Further, when operating in the “not-selected mode”, energy crosstalk between the collectors of Q 1   54  and Q 2   56  is minimized since the Miller capacitance of these transistors is connected to analog ground via the reference bias voltage  82  (BV 2 ). 
     In the “selected” mode operation of selectable input circuit  30 A, bias control voltage  80  (BV 1 ), which is applied to the base of transistors Q 5   50  and Q 6   52 , is less than bias voltage  82  (BV 2 ) applied to the base of grounded base amplifier transistors Q 1   54  and Q 2   56  (i.e. BV 1 &lt;BV 2 ). As such, the data pulse current from input resistors R 1   58  and R 2   60  will be steered through transistors Q 1   54  and Q 2   56  to the data regenerating flip-flop of transistors Q 3   66  and Q 4   68  of RZ to NRZ converter  32  via outputs  36  and  38 , respectively. To steer the data pulse current through transistors Q 1   54  and Q 2   56  the difference between bias control voltage  80  (BV 1 ) and bias control voltage  82  (BV 2 ) may be as little as −200 mV. As a result of the operation of selectable input circuit  30 A in the “selected” mode, the regenerating flip-flop of RZ to NRZ converter  32  will regenerate data in the RZ format to the NRZ format with the hysteresis control circuit (not shown) supplying a tail current to the flip-flop transistors Q 3   66  and Q 4   68 . The hysteresis control of flip-flop transistors Q 3   66  and Q 4   68  may, for example, take the form of the hysteresis control circuits described in U.S. Pat. No. 5,852,637 issued to Brown et al. 
     When selectable input switch  30 A is in the “selected mode” thereby steering a data pulse received from non-contact bus  21  through RZ to NRZ converter  32  and into data sink  16  via path  20 , selectable input circuit  30 B would be in the “not selected” mode. The reverse also applies. However, it is possible, and may also be desirable for both selectable input circuit  30 A and  30 B to be in the “not selected” mode, thereby transmitting no NRZ data pulse to data sink  16 . The same to Bias Control Voltages 1,2  be used in reverse for the second selectable input circuit  30 A (i.e. Bias Control Voltage 1  on the first input circuit would become Bias Control Voltage 2  for the second input circuit and Bias Control Voltage 2  on the first input circuit would become Bias Control Voltage 1  for the second input circuit). This arrangement ensures that at least one of the two data lines is selected if the absolute difference between the bias control voltages was greater than 200 mV. If the absolute difference between the bias control voltages is less than 200 mV than neither of the two data lines is selected. Alternatively, the bias control voltages could be controlled separately. 
     As noted in the incorporated references, RZ to NRZ converter  32  performs RZ to NRZ conversion of an input signal received from outputs  36  and  38  using flip-flop transistors Q 3   66  and Q 4   68  in combination with a hysteresis generating circuit. Both the input impedance terminating resistors R 3   44  and R 4   46  and the RZ to NRZ converter, such as RZ to NRZ converter  32 , are not materially affected by the incorporation of selectable input circuit  30 A. 
     As noted above, the selectable input circuit  30 A, which is comprised of resistors R 1   58  and R 2   60 , and transistors Q 1   54 , Q 2   56 , Q 5   50  and Q 6   52 , may be replicated any number of times, but, due to practical limitations, is typically limited to four selectable input circuits in total. Such an embodiment is illustrated in FIG.  4 . The embodiment illustrated in FIG. 4 permits the selection of one of four data lines  18  of backplane  12  (FIG.  1 ). 
     Selector switch  400  (FIG. 4) is comprised of four selectable input circuits  30 A,  30 B,  30 C and  30 D (collectively  30 ). The internal configuration of selectable input circuits  30 A,  30 B,  30 C and  30 D is identical to selectable input circuit  30 A of FIG.  3 . 
     Each selectable input circuit  30  has a differential input comprised of a first input (I 1 ) and a second input (I 2 ) and two bias control voltages (BV x  and BV x+1 ). Specifically, selectable input circuit  30 A has first input  62  (I 1 ), second input  64  (I 2 ), bias control voltage  80  (BV 1 ) and bias control voltage  82  (BV 2 ). Selectable input circuit  30 A is also in communication with power supply rail  34  via paths  40 A and  42 A and RZ to NRZ converter  32  via outputs  36  and  38 . Similarly, selectable input circuit  30 B has first input  402  (I 1 ), second input  404  (I 2 ), bias control voltage  430  (BV 3 ) and bias control voltage  432  (BV 4 ). Selectable input circuit  30 B is also in communication with power supply rail  34  via paths  40 B and  42 B and RZ to NRZ converter  32  via outputs  36  and  38 . Similarly, selectable input circuit  30 C has first input (I 1 )  406 , second input  408  (I 2 ), bias control voltage  434  (BV 5 ) and bias control voltage  436  (BV 6 ). Selectable input circuit  30 C is also in communication with power supply rail  34  via paths  40 C and  42 C and RZ to NRZ converter  32  via outputs  36  and  38 . Similarly, selectable input circuit  30 D has first input  410  (I 1 ), second input  412  (I 2 ), bias control voltage  5438  (BV 7 ) and bias control voltage  5440  (BV 8 ). Selectable input circuit  30 D is also in communication with power supply rail  34  via paths  40 D and  42 D and RZ to NRZ converter  32  via outputs  36  and  38 . As noted above, the physical location of the four selectable input circuits  30  is most effectively located on all four sides of the RZ to NRZ converter  32  (rather than in the serial fashion illustrated, for exemplary purposes only, in FIG. 4) thus keeping the path delays from all four inputs identical and minimal which is important in the context of subsequent clock/data timing alignment. 
     In operation, the embodiment of FIG. 4, the differential inputs (I 1  and I 2 ) of each selectable input circuit  30  is in communication with a data line, such as data line  18  (FIG.  1 ), by coupler  22  (FIG.  1 ). Assuming that data lines  18 A,  18 B,  18 C and  18 D are in communication with selectable input circuits  30 A,  30 B,  30 C and  30 D, respectively, a particular data line, data line  18 B for example, is selected by ensuring that selectable input circuits  30 A,  30 C and  30 D are in the “not selected” mode and  30 B is the “selected” mode. In this configuration bias control voltages 1,5 and 7  ( 80 ,  434  and  438 , respectively) are greater than bias control voltages 2,6 and 8  ( 82 ,  436  and  440  respectively). As such any signal received by selectable input circuits  30 A,  30 C or  30 D will be steered by operation of transistors Q 5   50  and Q 6   52  (in the respective selectable circuits  30 A,  30 C and  30 D) to power rail  34  via paths  40 A,  40 C,  40 D,  42 A,  42 C and  42 D. 
     Simultaneously with the operation of selectable input circuits  30 A,  30 C and  30 D in the “not selected mode”, bias control voltage 3  of selectable input circuit  30 B will be less than bias control voltage 4  and thus selectable input circuit  30 B will be in the “selected” mode of operation. The individual bias control voltages, used to select an input circuit could be controlled, for example, by signals from a switching processor circuit or the like. In the “selected” mode the differential input received on inputs ( 402  and  404 , respectively) via data line  18 B will be steered by operation of transistors Q 1   54  and Q 2   56  of selectable input circuit  30 B via outputs  36 ,  38  to RZ to NRZ converter  32 . The signal received by RZ to NRZ converter  32  will be converted from a RZ to NRZ format and the output  84  of converter  32  is then transmitted to data sink  16  via data path  20  (FIG.  1 ). Data sink  16  receives the data pulses transmitted from converter  32  and operates in a conventional manner. 
     While several embodiments of this invention have been illustrated in the accompanying drawings and described above, it will be evident to those skilled in the art that changes and modifications may be made therein without departing from the essence of this invention. All such modifications or variations are believed to be within the sphere and scope of the invention as defined by the claims appended hereto.