Abstract:
A switch capacitor summing amplifier is disclosed having a coupling means to couple desired signals to the active amplifier in response to an enable signal. The coupling is performed in synchronism to the &#34;odd&#34; phase of the sampling signals thereby improving noise, transient and DC offset performance while minimizing switch impedance sensitivity.

Description:
TECHNICAL FIELD 
     This invention relates generally to filter networks and more particularly to switched capacitor filter networks, and is more particularly directed towards an improved switch capacitor summing amplifier that may be used in conjunction with switch capacitor filters. 
     BACKGROUND ART 
     Switched capacitor filters are known. Such filters are the product of filter designing techniques to miniaturize filters, which are often reduced to integrated circuit (IC) form. A switch capacitor filter utilizes the fact that when a capacitor is switched between a signal to be sampled and ground at a frequency many times the frequency of the sampled signal, the capacitor will simulate the circuit behavior of a resistor. In the design of switched capacitor filters, summing amplifiers are frequently employed as an input section to select one or more signals to be filtered by the switch capacitor filter. Such a summing amplifier is illustrated in FIG. 1. The switch capacitor summing amplifier 100 is comprised of a plurality of input circuits 102 and a conventional switch capacitor amplifier 104. Each input section is coupled to amplifier 104, which sums any of the input voltage signals that may be present (V 1  -V n ) and provides an output signal 114. Each of the input sections 102 is comprised of two MOS transistor switches 106 and a capacitor 108. The amplifier 104 is comprised of an operational amplifier 116 having feedback capacitors 110 and 112, and has a pair of sampling switches (106) at the input and output. The OP amp (116) provides an output signal 114, which may be advantageously filtered by any suitable switched capacitor filter known in the art. As is readily understood in the art, there are commonly two phases of sampling associated with the switches 106. These are an even phase and an odd phase. Typically, these signals are of complementary phase and are easily generated using an inverter or functional equivalent. All the switches marked &#34;even&#34; are closed simultaneously, then opened followed by a closure of all the switches marked &#34;odd&#34;. 
     Frequently, the summing amplifier 100 operates as a signal selector and often has all but one of its signal sources disabled. However, the continued connection of the remaining unused inputs seriously impact performance of the summing amplifier 100. If the unused inputs are allowed to &#34;float&#34;, parasitic charge may couple across the capacitor 108 and cause shifts in the frequency response of the summing amplifier 100. Conversely, if the unused inputs are connected to an AC ground, the input noise, DC offset and switch impedance sensitivity of the amplifier 104 are severely degraded. Thus, there is a need in the art to provide a switch capacitor amplifier that operates to select various input signals without degrading the performance of the following switch capacitor filter. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide an improved switch capacitor summing amplifier. 
     It is another object of the present invention to provide a switch capacitor summing amplifier which effectively removes unused input ports from the circuit. 
     It is yet another object of the present invention to provide an improved switch capacitor summing amplifier which removes unused input ports in synchronism to the switching signals. 
     Accordingly, these and other objects are achieved by the present switch capacitor summing amplifier. 
     Briefly, according to the invention, a switch capacitor summing amplifier is provided with a coupling means to couple desired signals to an amplifier in response to a selection signal. The coupling is performed in synchronizm to one of the phases of the sampling signal thereby improving noise, transient and DC offset performance, while minimizing switch impedance sensitivity. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features of the present invention which are believed to be novel are set forth with particularity in the appended claims. The invention, together with further objects and advantages thereof, may be understood by reference to the following description, taken in conjunction with the accompanying drawings, and the several figures of which like reference numerals identify like elements, and in which: 
     FIG. 1 is a schematic diagram of a switched capacitor summing amplifier according to the prior art; 
     FIG. 2 is a schematic diagram of a switched capacitor summing amplifier according to the present invention; 
     FIG. 3a is a continuous-time equivalent circuit of the summing amplifier of FIG. 1; 
     FIG. 3b is a continuous-time equivalent circuit of the summing amplifier of FIG. 2; 
     FIG. 4 is an alternate embodiment of the summing amplifier of FIG. 2; 
     FIG. 5 is another alternate embodiment of the summing amplifier of FIG. 2; 
     FIG. 6 is a schematic diagram of a MOS implementation of one switch. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring now to FIG. 2, the switch capacitor summing amplifier of the present invention is shown. The summing amplifier 200 is comprised of a plurality of input circuits 202 each having a pair of MOS switches 206 and an input capacitor 208. The amplifier portion 204 is comprised of an operational amplifier 214 having a pair of switches at its input and output port and feedback capacitors 210 and 212. Optionally, the amplifier 204 is coupled to a gain change network 230. The value of the capacitor 212 may be changed by adding (capacitors add in parallel) one or more capacitors. For example, a capacitor 238 may be added by asserting the enable line 236. The transmission gate 232 will couple any capacitor having an asserted enable line on the next rising edge of the odd sampling signal. Of course, the same technique may be used on the capacitor 208 or 210. Moreover, this technique may be carried into any switched capacitor filter that may follow the summing amplifier 200. 
     Each of the input sections 202 is coupled to the amplifier 204 via a transmission gate 216. The transmission gate 216 is activated by a control signal 218, which is provided from a latch 220. The signal 218 is provided by the latch 220 on the first rising edge of the &#34;odd&#34; sampling clock after the assertion of the V 1  enable line 222. However, if the V 1  enable signal 222 negates (i.e., logical 0) during the odd phase of the sample signal, the transmission gate 216 will immediately remove the V 1  signal source from the circuit. Additionally, if the enable line 222 is a logical zero, the Q output of the latch 220 will provide a signal 224 to the transmission gate 226. The control signals 224 and 218 are opposite phase signals so that when the transmission gate 216 is on, the transmission gate 226 is off, and vice versa. Therefore, when the transmission gate 216 is off a connection from the capacitor 208 to ground is made by the transmission gate 226. The latch 220 synchronizes the activation and deactivation of the transmission gates 226 and 216 such that transients are not coupled into the amplifier 204 (due to the switching of the transmission gates). Thus, it is not sufficient to merely decouple the unused input stages 202. It is the synchronizing aspect of the present invention that provides the superior performance over merely decoupling the unused input ports. Additionally, it has been discovered that switching transients are a particular problem on the &#34;even&#34; phase of the sampling signal, therefore, each latch 220 is activated upon the &#34;odd&#34; phase of the sampling signal to further reduce the conducted transients. Moreover, in a broader, more general aspect of the present invention, the synchronized gain change (capacitor addition) operates to allow gain and/or bandwidth changes in the summing amplifier 200 or a switched capacitor filter (not shown). Thus, the switch capacitor amplifier 200 of the present invention completely removes, synchronously, any unused input sections from the amplifier 204 thereby minimizing noise, switch impedance sensitivity and DC offsets. 
     Referring now to FIGS. 3a and 3b, a continuous-time equivalent circuit of the prior art amplifier 100 and the present invention amplifier 200 are shown (respectively). Those skilled in the art will appreciate that an element by element analogy may be made between the circuits of FIG. 1 and FIG. 3a and the circuit of FIG. 2 and FIG. 3b. Due to the principles of virtual ground, the gain presented to the signal V 1  in FIG. 3a is: 
     
         A.sub.V1 =R.sub.f /R.sub.1                                 (1) 
    
     However, the gain provided to the equivalents noise and DC offset source 300 is: ##EQU1## 
     As an example, and not as a limitation, assume that one of five possible input sources is activated and that all of the resistors in FIG. 3a are equal. In such a case, the gain provided to the signal V 1  would be 0 dB and the gain provided to the noise and offset source 300 would be 16 dB. Referring now to FIG. 3b, assuming only V 1  of a plurality of sources is coupled to the amplifier, the remaining resistors R 2  -R N  would be completely removed due to the switches, which represent the transmission gates 226 and 216 of FIG. 2. In FIG. 3b, the gain provided to the signal V 1  is the same as equation (1), while the gain provided to the equivalent noise and offset source 300 is: 
     
         A.sub.noise =1+(R.sub.f /R.sub.1)                          (3) 
    
     Assuming the same example of 5 voltage sources (only one of which is used and all resistors being equal) the gain provided to the signal V 1  remains 0 dB. However, the gain provided to the noise and offset source 300 is reduced to 6 dB. This represents a 10 dB improvement in hum and noise performance and DC offset. 
     Referring now to FIG. 4, an alternate embodiment of the present invention is shown. The summing amplifier 400 is comprised of the same basic blocks as the invention of FIG. 2. However, the desired signal V 1  is coupled to 2 input sections 402 and 402&#39;. The primary difference between these two sections is the coupling capacitor 408 and 408&#39;. By selecting appropriate values for these capacitors, various levels of the input signal V 1  can be routed via the amplifier 404 to the switched capacitor filter via the output line 414. A first level may be selected by activating the level 1 enable line 422. Other levels may be selected by activating an appropriate enable line or combination of enable lines. Those skilled in the art will appreciate that virtually any number of input sections 402 may be provided as input sections to the amplifier 404. 
     Referring now to FIG. 5, yet another embodiment of the present invention is shown. In FIG. 5, the summing amplifier 500 routes a voice signal 501 to an input circuits 502 and 502&#39;. This operates to select different levels of the voice signal as was shown in FIG. 4. Additionally, signalling information, such as a Private Line (PL signal 503), may be summed with the voice signal through the input section 502 as is shown. Of course, additional circuits could be used to select different levels of the PL signal 503 and those skilled in the art will appreciate the varied combinations of levels and signals that are possible using the techniques of the present invention. 
     Referring now to FIG. 6, the preferred embodiment of a MOS transistor switch 600 is shown. In the preferred embodiment of the present invention, each switch 206 is implemented using metal oxide semiconductor (MOS) transistor techniques. The switch 600 is arranged in the convention SPST form having an input port 602 and an output port 604. When the enable line 614 (either the &#34;even&#34; sampling signal or the &#34;odd&#34; sampling signal) is logical 1, the transistor 612 pulls the control line 616 to logical 0, which activates the transistor 606. The transistor 608 is also activated and the switch is &#34;closed&#34;. Conversely, when the enable signal 614 is a logical 0, the transistor 610 pulls the control line 616 to logical 1 and both the transistors 606 and 608 are off and the switch 600 is &#34;open&#34;. 
     While a particular embodiment has been described and shown, it should be understood by those of ordinary skill in the art that the present application is not limited thereto since many modifications may be made. In particular, the present invention contemplates the use of any suitable temperature compensation or stability techniques as is well known in the art. Accordingly, it is therefore contemplated to cover by the present application any and all such modifications that may fail within the true spirit and scope of the basic underlying principles disclosed and claimed herein.