Abstract:
A structure and a method for forming the same. The structure includes an integrated circuit comprising N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit. The structure further includes N solder bumps corresponding to the N chip electric pads. A semiconductor interposing shield is sandwiched between the integrated circuit and the N solder bumps. The structure further includes N electric conductors (i) passing through the semiconductor interposing shield and (ii) electrically connecting the N solder bumps to the N chip electric pads.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Technical Field  
         [0002]     The present invention relates to integrated circuit packaging, and more specifically, to using alpha particle shields in integrated circuit packaging.  
         [0003]     2. Related Art  
         [0004]     In flip-chip technologies, solder bumps are typically formed on top of a semiconductor chip (i.e., integrated circuit IC). Each solder bump is formed directly on a bond pad of the chip. Then the chip is flipped face down and then aligned to a package/substrate so that the solder bumps are bonded directly, simultaneously, and one-to-one to the pads of the package/substrate (called package/substrate pads). However, for ceramic substrates, alpha particles (large subatomic fragments consisting of 2 protons and 2 neutrons) continuously emit from the substrate and enter the chip resulting in a large number of soft errors in the chip during the normal operation of the chip. Alpha particles are also generated from  210 Pb contained in the solder bumps.  
         [0005]     Therefore, there is a need for a structure (and a method for forming the same) that reduces the number of alpha particles that enter the chip.  
       SUMMARY OF THE INVENTION  
       [0006]     The present invention provides a structure, comprising (a) an integrated circuit including N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit; (b) N solder bumps corresponding to the N chip electric pads; (c) a semiconductor interposing shield sandwiched between the integrated circuit and the N solder bumps; and (d) N electric conductors (i) passing through the semiconductor interposing shield and (ii) electrically connecting the N solder bumps to the N chip electric pads.  
         [0007]     The present invention also provides a structure, comprising (a) an integrated circuit including N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit; (b) N solder bumps corresponding to the N chip electric pads; (c) a semiconductor interposing shield sandwiched between the integrated circuit and the N solder bumps, wherein the semiconductor interposing shield has a thickness of at least 50 μm; (d) N electric conductors (i) passing through the semiconductor interposing shield and (ii) electrically connecting the N solder bumps to the N chip electric pads; and (e) a ceramic substrate including N substrate pads, wherein the N solder bumps are bonded to the N substrate pads.  
         [0008]     The present invention also provides a structure fabrication method, comprising providing an integrated circuit including N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit; providing an interposing shield having a top side and a bottom side and having N electric conductors in the interposing shield, wherein the N electric conductors are exposed to a surrounding ambient at the top side but not being exposed to the surrounding ambient at the bottom side; bonding the integrated circuit to the top side of the interposing shield such that the N chip electric pads are in electrical contact with the N electric conductors; polishing the bottom side of the interposing shield so as to expose the N electric conductors to the surrounding ambient at the bottom side of the interposing shield after said bonding the integrated circuit to the top side is performed; and forming N solder bumps on the polished bottom side of the interposing shield and in electrical contact with the N electric conductors.  
         [0009]     The present invention also provides a structure fabrication method, comprising providing an integrated circuit including N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit; providing a semiconductor interposing shield having a top side and a bottom side and having N electric conductors in the semiconductor shield, wherein the N electric conductors are exposed to a surrounding ambient at the top side but not being exposed to the surrounding ambient at the bottom side; bonding the integrated circuit to the top side of the semiconductor interposing shield such that the N chip electric pads are in electrical contact with the N electric conductors; polishing the bottom side of the semiconductor interposing shield so as to expose the N electric conductors to the surrounding ambient at the bottom side of the semiconductor interposing shield after said bonding the integrated circuit to the top side is performed; forming N solder bumps on the polished bottom side of the semiconductor interposing shield and in electrical contact with the N electric conductors; after said forming the N solder bumps is performed, bonding a ceramic substrate that includes N substrate pads such that the N substrate pads are bonded to the N solder bumps, wherein the semiconductor interposing shield comprises essentially only silicon, and wherein the semiconductor interposing shield has a thickness of at least 50 μm after said polishing the bottom side is performed.  
         [0010]     The present invention provides a structure (and a method for forming the same) that reduces the number of alpha particles that enter the chip. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]      FIGS. 1-10  show the fabrication process for forming a structure, in accordance with embodiments of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0012]      FIGS. 1-10  show the fabrication process for forming a structure  700  ( FIG. 10 ), in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 1A , in one embodiment, the fabrication process starts out with an interposing shield  100  that comprises a semiconductor (e.g., silicon, germanium) layer  110 . Next, in one embodiment, annular trenches  112   a  and  112   b  are formed in the semiconductor layer  110 . Illustratively, the annular trenches  112   a  and  112   b  are formed using a photolithographic process. In one embodiment, the annular trenches  112   a  and  112   b  have a depth  113  of around 50-70 μm.  FIG. 1B  shows a perspective view of the interposing shield  100  of  FIG. 1A .  
         [0013]     Next, with reference to  FIG. 2 , in one embodiment, a dielectric film  210  is formed on exposed-to-ambient silicon surfaces of the interposing shield  100  of  FIG. 1A . As a result, the dielectric film  210  forms on, among other places, bottom walls and side walls of the annular trenches  112   a  and  112   b . Illustratively, exposed-to-ambient silicon surfaces of the interposing shield  100  of  FIG. 1  can be thermally oxidized so as to form silicon dioxide resulting in the dielectric film  210 .  
         [0014]     Next, with reference to  FIG. 3 , in one embodiment, an electrically conducting layer  310  is formed on top of the interposing shield  100  of  FIG. 2  so as to completely fill the annular trenches  112   a  and  112   b . Illustratively, the electrically conducting layer  310  comprises a metal (such as copper Cu) and is formed by CVD (chemical vapor deposition), ALD (atomic layer deposition), or electrochemical plating of the metal (i.e., Cu). It should be noted that if the metal used for the electrically conducting layer  310  is tungsten (W), a seed layer (not shown) of Ti or TiN needs to be formed first on top of the interposing shield  100  of  FIG. 2  by PVD, CVD or ALD to serve as nuclei for the ensuing growth of tungsten to form the W electrically conducting layer  310 . Likewise, it should be noted that if the metal used for the electrically conducting layer  310  is copper (Cu), a seed layer (not shown) of TaN, Ta and Cu needs to be formed first on top of the interposing shield  100  of  FIG. 2  by PVD, CVD or ALD to serve as nuclei for the ensuing growth of copper to form the Cu electrically conducting layer  310 .  
         [0015]     Next, in one embodiment, a chemical mechanical polishing (CMP) step is performed on top surfaces  320  of the interposing shield  100  of  FIG. 3  until the dielectric film  210  is exposed to the surrounding ambient. The resulting interposing shield  100  is shown in  FIG. 4  (without the top layer  420 ). What remains of the electrically conducting layer  310  after the CMP step resides in the annular trenches  112   a  and  112   b  and can be referred to as the annular electric conductors  410   a  and  410   b  ( FIG. 4 ).  
         [0016]     Next, with reference to  FIG. 4 , in one embodiment, a dielectric layer  420  is formed on top of the dielectric film  210  and in contact with the annular electric conductors  410   a  and  410   b . Illustratively, the dielectric layer  420  comprises silicon dioxide and is formed by CVD of silicon dioxide.  
         [0017]     Next, with reference to  FIG. 5 , in one embodiment, electric pads  510   a  and  510   b  are formed in the oxide layer  420  and in direct physical contact with the annular electric conductors  410   a  and  410   b , respectively. Illustratively, the electric pads  510   a  and  510   b  comprise copper and can be formed using a conventional damascene process. More specifically, the damascene process starts with etching trenches (which the electric pads  510   a  and  510   b  later occupy) in the oxide layer  420  using a conventional lithographic process. Next, copper is deposited (e.g., by electroplating) to fill the trenches. Finally, excess copper outside the trenches is removed by a CMP step resulting in the electric pads  510   a  and  510   b  as shown in  FIG. 5 .  
         [0018]     Next, in one embodiment, the oxide layer  420  is recessed so that its top surface  422  is lower than the top surfaces  512  of the electric pads  510   a  and  510   b  as shown in  FIG. 6 . In one embodiment, the oxide layer  420  is recessed by several thousand A to 0.5 μm. Illustratively, the oxide layer  420  is recessed by a wet etch using a dilute hydrofluoric acid solution (HF).  
         [0019]     Next, with reference to  FIG. 6 , in one embodiment, the interposing shield  100  is aligned with a semiconductor chip (integrated circuit IC)  600  such that the electric pads  622   a  and  622   b  of the semiconductor chip  600  are aligned with the electric pads  510   a  and  510   b  of the interposing shield  100 , respectively. In one embodiment, the semiconductor chip  600  is fabricated separately from the fabrication of the interposing shield  100 . Illustratively, the semiconductor chip  600  comprises a device region  610  and a back-end-of-line (BEOL) region  620 . The device region  610  can comprise devices such as transistors, resistors, and capacitors (not shown). The (BEOL) region  620  can comprise electrically conducting lines (not shown) running in a dielectric material so as to (i) electrically connect the devices of the device region  610  together and (ii) electrically connect the devices of the device region  610  to the electric pads  622   a  and  622   b.    
         [0020]     Next, with reference to  FIG. 7 , in one embodiment, the interposing shield  100  and the chip  600  are bonded together to form a structure  700  such that the electric pads  510   a  and  622   a  ( FIG. 6 ) merge together to form an electric pad  510   a , 622   a  and such that the electric pads  510   b  and  622   b  ( FIG. 6 ) merge together to form an electric pad  510   b , 622   b . In one embodiment, the bonding process is performed at 350-400° C.  
         [0021]     Next, with reference to  FIG. 8 , in one embodiment, the bottom side of the structure  700  is polished until the annular electric conductors  410   a  and  410   b  are exposed to the surrounding ambient. Illustratively, the bottom side of the structure  700  is mechanically ground by a mechanical grinding process only. Alternatively, the bottom side of the structure  700  is ground down by a mechanical grinding process until the annular electric conductors  410   a  and  410   b  are about to be exposed to the surrounding ambient. Then, a wet etch is performed on the bottom side of the structure  700  so as to expose the annular electric conductors  410   a  and  410   b  to the surrounding ambient.  
         [0022]     Next, with reference to  FIG. 9 , in one embodiment, solder bumps  910   a  and  910   b  are formed on bottom side of the structure  700  and in electrical contact with the annular electric conductors  410   a  and  410   b , respectively, using a conventional solder bump formation process (also known as the flip chip technologies). The resulting structure  700  is shown in  FIG. 9 . The solder bumps  910   a  and  910   b  are electrically connected to the annular electric conductors  410   a  and  410   b  via electric chip pads  920   a  and  920   b , respectively. Illustratively, the electric chip pads  920   a  and  920   b  comprises aluminum. Although not shown, between the solder bumps  910   a  and  910   b  and the aluminum chip pads  920   a  and  920   b  is a ball limiting metallurgy (BLM) (illustratively comprising TiW/CuCr/Cu). The rest of the bottom side of the structure  700  is covered by a polyimide layer  930  which is a dielectric material.  
         [0023]     Next, with reference to  FIG. 10 , in one embodiment, a ceramic substrate  1010  is bonded with the structure  700  such that substrate pads  1010   a  and  1010   b  of the ceramic substrate  1010  are bonded with the solder bumps  910   a  and  910   b , respectively. Illustratively, the substrate pads  1010   a  and  1010   b  comprises aluminum.  
         [0024]     Next, in one embodiment, the structure  700  is placed in a package (not shown) having package pins (not shown) that are electrically connected to the substrate pads  1010   a  and  1010   b  via metal lines (not shown).  
         [0025]     In summary, with reference to  FIG. 10 , the interposing shield  100  is sandwiched between the ceramic substrate  1010  and the semiconductor chip  600 . As a result, the interposing shield  100  helps reduce the alpha particles that are generated by the ceramic substrate  1010  and enter the semiconductor chip  600 . The interposing shield  100  also helps reduce the alpha particles that are generated by the solder bumps  910   a  and  910   b  (i.e. Pb).  
         [0026]     In one embodiment, the thickness  114  of the interposing shield  100  is sufficiently large such that at least a pre-specified percentage of alpha particles entering the interposing shield  100  from the ceramic substrate  1010  do not pass through the interposing shield  100  so as to reach the semiconductor chip  600 .  
         [0027]     It should be noted that the thickness  114  of the interposing shield  100  is essentially the depth  113  ( FIG. 1A ) of the annular trenches  112   a  and  112   b  of  FIG. 1A . As a result, with the depth  113  ( FIG. 1A ) of around 50-70 μm, the thickness  114  of the silicon interposing shield  100  is also around 50-70 μm and therefore is sufficiently thick to prevent most of the alpha particles generated by the ceramic substrate  1010  from entering the semiconductor chip  600 .  
         [0028]     It should also be noted that the annular electric conductors  410   a  and  410   b  provide electric paths from the solder bumps  910   a  and  910   b  to the devices (not shown) of the semiconductor chip  600  (via the electric pads  510   a , 622   a  and electric pad  510   b , 622   b , respectively). The annular shape is chosen for the electric conductors  410   a  and  410   b  so as to save metal material during the step of filling the trenches  112   a  and  112   b  ( FIG. 3 ) to form the electric conductors  410   a  and  410   b . Moreover, because the trenches  112   a  and  112   b  ( FIG. 3 ) are filled fast, the excess metal outside the trenches  112   a  and  112   b  ( FIG. 3 ) are less, and therefore, the ensuing removal of the excess metal becomes easier. In general, the trenches  112   a  and  112   b  ( FIG. 3 ) can have any shape and size.  
         [0029]     It should be noted that the solder bumps  910   a  and  910   b  may comprise a tin-lead alloy which itself generates alpha particles. Because the interposing shield  100  is sandwiched between the solder bumps  910   a  and  910   b  and the semiconductor chip  600 , the interposing shield  100  also helps reduce the alpha particles that enter the semiconductor chip  600  from the solder bumps  910   a  and  910   b.    
         [0030]     In one embodiment, the structure  700  comprises a dielectric layer (not shown) that electrically insulates the electric chip pads  920   a  and  920   b  from the silicon region of the silicon layer  110  such that there is no electrically conducting path between the electric chip pads  920   a  and  920   b  through the silicon region of the silicon layer  110 .  
         [0031]     In the embodiments above, there are two trenches  112   a  and  112   b  ( FIG. 1A ) formed. In general, there can be N trenches formed, wherein N is a positive integer. As a result, there are N solder bumps (like the solder bumps  910   a  and  910   b ) electrically connected one-to-one to N electric pads (like the electric pad  510   a , 622   a  and  510   b , 622   b ) through N electric conductors (like the electric conductors  410   a  and  410   b ).  
         [0032]     In one embodiment, with reference to  FIG. 11 , metal (e.g., copper) regions  1110   a ,  1110   b , and  1110   c  are formed in the semiconductor regions of the interposing shield  100  such that the metal regions are electrically insulated from the electric conductors  410   a  and  410   b . Because copper is better than silicon in absorbing alpha particles, the interposing shield  100  with such embedded copper regions performs better in preventing alpha particles from reaching the semiconductor chip  600 . Illustratively, the copper regions can be formed by creating trenches (not shown) similar to the trenches  112   a  and  112   b  ( FIG. 1A ) and filling these trenches with copper.  
         [0033]     In one embodiment, a metal (e.g., copper) layer  1210  ( FIG. 12 ) may be formed on the bottom side of the structure  700  of  FIG. 8 . Then, the solder bumps  910   a  and  910   b  are formed as described above. Additional conventional fabrication steps are needed after the copper layer is formed and before the solder bumps  910   a  and  910   b  are formed so that the copper layer is sandwiched between, and electrically insulated from, the electric conductors  410   a  and  410   b  and the solder bumps  910   a  and  910   b . The resulting structure  700  is shown in  FIG. 12 . Because copper is better than silicon in absorbing alpha particles, the interposing shield  100  with the copper layer performs better in preventing alpha particles from reaching the semiconductor chip  600 . It should be noted that a dielectric layer (not shown) electrically insulates the copper layer  1210  from the silicon regions of the silicon interposing shield  100 . In one embodiment, the thickness of the copper layer  1210  is about one third of the thickness of the silicon interposing shield  100 . In one embodiment, the thickness of the copper layer  1210  is less than 15 μm and the silicon interposing shield  100  has a thickness in a range of 30 μm-70 cm. If the thickness of the copper layer  1210  is increased, the thickness of the silicon interposing shield  100  can be reduced. This means that the depth  113  ( FIG. 1A ) of the trenches  112   a  and  112   b  ( FIG. 1A ) can be reduced. In one embodiment, the copper layer has a thickness in a range of 10 μm-15 μm, which is sufficient by itself in blocking alpha particles, and therefore, the thickness of the silicon interposing shield  100  can be less than 1 μm or even zero (i.e., silicon interposing shield  100  can be omitted).  
         [0034]     In one embodiment, the silicon regions of the semiconductor interposing shield  100  are doped with boron atoms (using, illustratively, ion implantation). This enhances the capability of the semiconductor interposing shield  100  in preventing cosmic thermal neutrons from passing through the semiconductor interposing shield  100  and reach the semiconductor chip  600 . The cosmic thermal neutrons undergo reactions with the B that emit &lt;2 MeV alpha particles. Therefore it is advantageous to have this B doped region on the top of the Si interposer layer (on the opposite side from the semiconductor device).  
         [0035]     While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.