Abstract:
In response to a disagreement between a previously generated check code associated with previously programmed data bits and a more recently generated check code generated in response to a read command, the comparison process is changed, between i) a value representing accessed data and ii) a reference applied to such accesses to distinguish between logical levels. For example, the ratio of resistances characterizing input circuits of a sense amplifier and/or the read bias arrangement and/or a read reference of a memory integrated circuit is/are changed.

Description:
REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a continuation-in-part of U.S. patent application Ser. No. 12/275,606, filed 21 Nov. 2008, which is a continuation-in-part of U.S. patent application Ser. No. 11/735,911, filed 16 Apr. 2007, which claims the benefit of U.S. Provisional Patent Application No. 60/746,733, filed 8 May 2006. All applications are incorporated by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The invention relates to nonvolatile memory integrated circuits generally, and more particularly to error detection and error correction of data that are read from nonvolatile memory. 
         [0004]    2. Description of Related Art 
         [0005]    The purpose of nonvolatile memory is to store data reliably, such that power loss does not affect the integrity of the stored data. To allow for unforeseen charge gain or charge loss that might affect a threshold voltage of a nonvolatile memory cell, a margin separates threshold voltage ranges that represent different logical levels. However, despite this margin, errors nevertheless occur, such that a data bit programmed as a high logical level will be read as a low logical level, or vice versa. 
         [0006]    Although error correction and error detection algorithms will address some of these errors, error correction and error detection algorithms are only designed to handle a limited number of incorrect bits. After this limit is exceeded, error correction and error detection algorithms are insufficient. Moreover, error detection will detect, but not correct, such errors. 
         [0007]    Therefore, a need exists for an improvement that makes nonvolatile memory integrated circuits more robust in the face of errors. 
       SUMMARY OF THE INVENTION 
       [0008]    One aspect of the technology is a method of reading memory. In response to a read command, the memory performs the following:
       generating a first check code based on accessing a plurality of data bits stored on the memory;   accessing a second check code stored on the memory as a plurality of check bits associated with the plurality of data bits;   checking whether the first check code and the second check code are in agreement; and   responsive to disagreement between the first check code and the second check code, changing a comparison between i) at least one value representing at least one of the plurality of data bits stored on the memory, said at least one value accessed by a read bias arrangement applied on the memory, and ii) at least one reference applied to accesses of the data bits stored on the memory, said at least one reference and the comparison distinguishing between logical levels represented by said at least one value, including:   changing the comparison by changing a ratio of a first resistance and a second resistance, the first resistance characterizing a first input circuit of a sense amplifier that receives said at least one value, the second resistance characterizing a second input circuit of the sense amplifier that receives said at least one reference.       
 
         [0014]    In some embodiments, the value of the comparison is a current representing at least one of the data bits, and/or a voltage representing said at least one of the data bits. 
         [0015]    In some embodiments, the first check code and the second check code are error correcting codes or error detecting codes. 
         [0016]    In some embodiments, changing the comparison includes changing the read bias arrangement applied on the memory; changing a word line voltage of the read bias arrangement applied on the memory; and/or changing i) said at least one reference and ii) the read bias arrangement applied on the memory. 
         [0017]    In some embodiments, after changing the comparison, based on this change of the comparison, the memory repeats one or more of:
       said generating the first check code;   said accessing the second check code; and   said checking whether the first check code and the second check code are in agreement.       
 
         [0021]    In some embodiments, after changing the comparison, based on this change of the comparison, the memory performs:
       until success results from subsequent checking whether the first check code and the second check code are in agreement, iteratively changing the comparison.       
 
         [0023]    In some embodiments, the reference of the comparison distinguishes between at least a first logical level and a second logical level of said logical levels. The value of the comparison is accessed to distinguish whether at least one of the data bits represents the first logical level or the second logical level. Changing the comparison comprises:
       widening a first range of the accessed values associated with the first logical level; and   narrowing a second range of the accessed values associated with the second logical level.       
 
         [0026]    Another aspect of the technology is a memory. The memory has a memory array and control circuitry coupled to the memory array. The control circuitry is responsive to the memory receiving a read command by performing:
       generating a first check code based on accessing a plurality of data bits stored on the memory array;   accessing a second check code stored on the memory as a plurality of check bits associated with the plurality of data bits;   checking whether the first check code and the second check code are in agreement;   responsive to disagreement between the first check code and the second check code, changing a comparison between i) at least one value representing at least one of the plurality of data bits stored on the memory array, said at least one value accessed by a read bias arrangement applied to the memory array, and ii) at least one reference applied to accesses of the data bits stored on the memory array, said at least one reference and the comparison distinguishing between logical levels represented by said at least one value, including:   changing the comparison by changing a ratio of a first resistance and a second resistance, the first resistance characterizing a first input circuit of a sense amplifier that receives said at least one value, the second resistance characterizing a second input circuit of the sense amplifier that receives said at least one reference.       
 
         [0032]    In some embodiments, at least one value of the comparison is a current representing at least one of the data bits, and/or a voltage representing said at least one of the data bits. 
         [0033]    In some embodiments, the first check code and the second check code are error correcting codes or error detecting codes. 
         [0034]    In some embodiments, the control circuitry changes the comparison by changing the read bias arrangement applied to the memory array; by changing a word line voltage of the read bias arrangement applied to the memory array; and/or by changing i) at least one reference and ii) the read bias arrangement applied to the memory array. 
         [0035]    In some embodiments, after changing the comparison, based on this change of the comparison, the control circuitry repeats one or more of:
       said generating the first check code;   said accessing the second check code; and   said checking whether the first check code and the second check code are in agreement.       
 
         [0039]    In some embodiments, after changing the comparison, the control circuitry further performs:
       until success results from subsequent checking whether the first check code and the second check code are in agreement, iteratively changing the comparison.       
 
         [0041]    In some embodiments, at least one reference of the comparison distinguishes between at least a first logical level and a second logical level of said logical levels. At least one value of the comparison is accessed to distinguish whether at least one of the data bits represents the first logical level or the second logical level. The control circuitry performs said changing the comparison by:
       widening a first range of the accessed values associated with the first logical level; and   narrowing a second range of the accessed values associated with the second logical level.       
 
         [0044]    Another aspect of the technology is a memory. The memory has a memory array means and control circuitry means coupled to the memory array means. The control circuitry means is responsive to the memory receiving a read command. The control circuitry means includes: 
         [0045]    means for generating a first check code based on accessing a plurality of data bits stored on the memory; 
         [0046]    means for accessing a second check code stored on the memory as a plurality of check bits associated with the plurality of data bits; 
         [0047]    means for checking whether the first check code and the second check code are in agreement; and 
         [0048]    means, responsive to disagreement between the first check code and the second check code, for changing a comparison between i) at least one value representing at least one of the plurality of data bits stored on the memory, said at least one value accessed by a read bias arrangement applied on the memory, and ii) at least one reference applied to accesses of the data bits stored on the memory, said at least one reference and the comparison distinguishing between logical levels represented by said at least one value, including: 
         [0049]    means for changing a ratio of a first resistance and a second resistance, the first resistance characterizing a first input circuit of a sense amplifier that receives said at least one value, the second resistance characterizing a second input circuit of the sense amplifier that receives said at least one reference. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0050]      FIG. 1  is an exemplary flow chart of a program command, showing programming of data as well as a check code based on the data. 
           [0051]      FIG. 2  is an exemplary flow chart of a read command, showing that a read reference is changed in response to a disagreement between a previously generated and programmed check code, and a new check code. 
           [0052]      FIG. 3  shows an exemplary threshold voltage algorithm. 
           [0053]      FIG. 4  shows an exemplary threshold voltage algorithm, similar to  FIG. 3  but with a changed current reference, favoring a low threshold voltage distribution in contrast with  FIG. 3 . 
           [0054]      FIG. 5  shows an exemplary threshold voltage algorithm, similar to  FIG. 3  but with another changed current reference, favoring a high threshold voltage distribution in contrast with  FIG. 3 . 
           [0055]      FIG. 6  shows an exemplary block diagram of a nonvolatile memory integrated circuit that changes a comparison of a reference and a memory array signal in response to an error, such as disagreement between check codes as disclosed herein. 
           [0056]      FIG. 7  is an exemplary flow chart of a read command, showing that a read bias arrangement is changed in response to a disagreement between a previously generated and programmed check code, and a new check code. 
           [0057]      FIG. 8  is an exemplary flow chart of a read command, showing that a read reference and a read bias arrangement are changed in response to a disagreement between a previously generated and programmed check code, and a new check code. 
           [0058]      FIG. 9  shows another exemplary threshold voltage algorithm. 
           [0059]      FIG. 10  shows an exemplary threshold voltage algorithm, similar to  FIG. 9  but with a changed read bias arrangement, favoring a low threshold voltage distribution in contrast with  FIG. 9 . 
           [0060]      FIG. 11  shows an exemplary threshold voltage algorithm, similar to  FIG. 9  but with another changed read bias arrangement, favoring a high threshold voltage distribution in contrast with  FIG. 9 . 
           [0061]      FIG. 12  shows an exemplary block diagram of sense amplifier circuitry, with variable resistance in the input circuits of both the signal from the memory array and the signal from the reference. 
           [0062]      FIG. 13  shows an exemplary block diagram of sense amplifier circuitry, with variable resistance in the input circuit of the signal from the reference. 
           [0063]      FIG. 14  shows an exemplary block diagram of sense amplifier circuitry, with variable resistance in the input circuits of the signal from the memory array. 
           [0064]      FIG. 15  is an exemplary flow chart of a read command, showing that a comparison of a memory array value and a reference is changed in response to a disagreement between a previously generated and programmed check code and a new check code, where at least the sense amplifier input circuitry resistance ratio is changed. 
           [0065]      FIG. 16  shows yet another exemplary threshold voltage algorithm. 
           [0066]      FIG. 17  shows an exemplary threshold voltage algorithm, similar to  FIG. 16  but with a changed sensing ratio, favoring a low threshold voltage distribution in contrast with  FIG. 16 . 
           [0067]      FIG. 18  shows an exemplary threshold voltage algorithm, similar to  FIG. 16  but with another changed sensing ratio, favoring a high threshold voltage distribution in contrast with  FIG. 16 . 
       
    
    
     DETAILED DESCRIPTION 
       [0068]      FIG. 1  is an exemplary flow chart of a program command, showing programming of data as well as a check code based on the data. 
         [0069]    In  100 , the nonvolatile memory integrated circuit receives a program command. In  110 , a check code is generated based on data to be programmed by the program command. In various embodiments, the check code is an error correction code or error detection code. Examples of such codes are block codes (Hamming, Reed-Solomon, Reed-Muller, Goppa, Bose-Chaudhury-Hocquenhem, low density parity check), convolutional codes (turbo, Galileo), concatenated code, and interleaved codes. Other examples are single-error-correction double-error-detection codes, single-error-correction double-error-detection single-byte-error codes, single-byte-error-correction double-byte-error-detection, and double-error-correction triple-error-detection. The ability of various embodiments to detect or correct errors is partly dependent on the code algorithm of the particular embodiment. 
         [0070]    In  120 , both the program bits and the check code bite generated in  110  are programmed to the nonvolatile memory integrated circuit. The check code written in  120  is used in a read command, for example as shown in  FIGS. 2 ,  7 ,  8 , and  15 . 
         [0071]      FIG. 2  is an exemplary flow chart of a read command, showing that a read reference is changed in response to a disagreement between a previously generated and programmed check code, and a new check code. 
         [0072]    In  200 , the nonvolatile memory integrated circuit receives a read command. In  210 , the data bits programmed to the nonvolatile memory integrated circuit during  120  of  FIG. 1  are accessed, using a reference to determine the logical levels represented by these data bits. In  220 , a first check code is generated, based on the data bits that are accessed during  210 . In  230 , a second check code is accessed. The second check code is associated with the data bits read accessed in  210 . The second check code was previously programmed to the nonvolatile memory integrated circuit in association with the programming of the data associated with the generation of the second check code, such as in  120  of  FIG. 1 . 
         [0073]    In  240 , agreement is checked, between the first check code generated in  220  and the second code accessed in  230 . If the first check code and second check code agree, then in  260  a successful read is concluded. However, if the first check code and second check code disagree, then the reference used in  210  is changed, and the flow chart loops back to  210 . In response to continued errors, the loop may repeat as many as 3 to 10 times. If the reference is a reference current used by a sense amplifier to compare against a bit line current from a memory cell, then the reference current is changed, such as by changing the gate voltage of the reference cell or changing the timing of the sense amplifier circuitry. An exemplary magnitude of current change in the reference current is about 1 uA. In various embodiments, the changed reference may be used or not be used in accessing the second check code. 
         [0074]      FIG. 7  is another exemplary flow chart of a read command, showing that a read bias arrangement is changed in response to a disagreement between a previously generated and programmed check code, and a new check code. 
         [0075]    The flow chart of  FIG. 7  is generally similar to the flow chart of  FIG. 2 . However, in  750 , in response to disagreement between the first check code and the second check code, a change is made to the read bias arrangement, such as changing the word line voltage of the read bias arrangement. This read bias arrangement is applied to the nonvolatile memory to access the previously programmed data bits. 
         [0076]      FIG. 8  is yet another exemplary flow chart of a read command, showing that a read reference and a read bias arrangement are changed in response to a disagreement between a previously generated and programmed check code, and a new check code. 
         [0077]    The flow chart of  FIG. 8  is generally similar to the flow charts of  FIGS. 2 and 7 . However, in  850 , in response to disagreement between the first check code and the second check code, a change is made by selecting one of changing the reference and changing the read bias arrangement. This changed reference is subsequently used in  810 , when the flow chart loops back to  810 . In response to continued errors, the loop may repeat as many as 3 to 10 times. If the reference is a reference current used by a sense amplifier to compare against a bit line current from a memory cell, then the reference current is changed, such as by changing the gate voltage of the reference cell or changing the timing of the sense amplifier circuitry. An exemplary magnitude of current change in the reference current is about 1 uA. In various embodiments, the changed reference may be used or not be used in accessing the second check code. 
         [0078]      FIG. 15  is an exemplary flow chart of a read command, showing that a comparison of a memory array value and a reference is changed in response to a disagreement between a previously generated and programmed check code and a new check code, where at least the sense amplifier input circuitry resistance ratio is changed. 
         [0079]    The flow chart of  FIG. 15  is generally similar to the flow charts of  FIGS. 2 ,  7 , and  8 . However, in  1550 , in response to disagreement between the first check code and the second check code, the comparison (of the memory array value and the reference) is changed, by at least changing the resistance ratio (also called sensing ratio). Examples of the ratio are shown in  FIGS. 12-14 . This changed ratio with the resulting changed sensing window (examples shown in  FIGS. 16-18 ) is subsequently used in  1510 , when the flow chart loops back to  1510 . In response to continued errors, the loop may repeat as many as 3 to 10 times. Other changes may accompany the changed ratio, such as changing the reference and the read bias arrangement. If the reference is a reference current used by a sense amplifier to compare against a bit line current from a memory cell, then the reference current is changed, such as by changing the gate voltage of the reference cell or changing the timing of the sense amplifier circuitry. An exemplary magnitude of current change in the reference current is about 1 uA. In various embodiments, the changed reference may be used or not be used in accessing the second check code. 
         [0080]    In another embodiment, the in response to disagreement between the first check code and the second check code, a change is made by both changing the reference and changing the read bias arrangement. 
         [0081]    An example of changing the read bias arrangement is changing the word line voltage of the read bias arrangement. This read bias arrangement is applied to the nonvolatile memory to access the previously programmed data bits in  810 . 
         [0082]    The flow charts of  FIGS. 1 ,  2 ,  7 ,  8 , and  15  are exemplary. In other embodiments, the steps shown are rearranged, modified, deleted, or added to. For example, the steps of accessing data bits and accessing the second check code may be combined in a single step. 
         [0083]      FIGS. 3-5  show the effect of changing the current reference in an exemplary threshold voltage algorithm 
         [0084]      FIG. 3  shows the baseline of an exemplary threshold voltage algorithm. 
         [0085]      301  is the low bound of the low threshold voltage distribution B 1 .  302  is the high bound of the low threshold voltage distribution B 2 .  305  is the low bound of the high threshold voltage distribution B 3 .  306  is the high bound of the high threshold voltage distribution B 4 . A sense amplifier will sense the memory data by using a normal_Iref  307  and have a margin D 1   310  for charge loss of high threshold voltage cells and margin D 2   311  for charge gain of low threshold voltage cells. Although only two logical levels are shown, other embodiments have four or more logical levels to represent two or more bits. 
         [0086]      FIG. 4  shows an exemplary threshold voltage algorithm, similar to  FIG. 3  but with a changed current reference, favoring a low threshold voltage distribution in contrast with  FIG. 3 . 
         [0087]    The changed current reference Changed_IRef  407  was changed in response to a disagreement between check codes, such as in  240  of  FIG. 2 . Changed_IRef  407  has a narrower sensing margin D 1 ′  410  compared to D 1   310  and a wider sensing margin D 2 ′  411  compared to D 2   311 , so Changed_IRef  407  has a smaller sensing window for high threshold voltage cells and a larger sensing window for low threshold voltage cells. In the event of excess net negative charge gain by the charge storage material of the nonvolatile memory cells, the threshold voltage will be incorrectly raised. Therefore, Changed_IRef  407  will be more likely to result in a correct determination of the represented logical level. 
         [0088]      FIG. 5  shows an exemplary threshold voltage algorithm, similar to  FIG. 3  but with another changed current reference, favoring a high threshold voltage distribution in contrast with  FIG. 3 . 
         [0089]    Similar but opposite to  FIG. 4 , Changed_IRef  507  has a wider sensing margin D 1 ″  510  compared to D 1   310  and a narrower sensing margin D 2 ″  511  compared to D 2   311 , so Changed_IRef has a smaller sensing window for low threshold voltage cells and a larger sensing window for high threshold voltage cells. In the event of excess net positive charge gain by the charge storage material of the nonvolatile memory cells, the threshold voltage will be incorrectly lowered. Therefore, Changed_IRef  507  will be more likely to result in a correct determination of the represented logical level. 
         [0090]    In another embodiment, net positive charge gain results in changing the reference to favor the lower threshold voltage cells, and net negative charge gain results in changing the reference to favor the higher threshold voltage cells. 
         [0091]      FIG. 6  shows an exemplary block diagram of a nonvolatile memory integrated circuit that changes a comparison of a reference and a memory array signal in response to an error, such as disagreement between check codes as disclosed herein. 
         [0092]    The integrated circuit  650  includes a memory array  600  of nonvolatile memory cells, on a semiconductor substrate. The memory cells of array  600  may be individual cells, interconnected in arrays, or interconnected in multiple arrays. A row decoder  601  is coupled to a plurality of word lines  602  arranged along rows in the memory array  600 . A column decoder  603  is coupled to a plurality of bit lines  604  arranged along columns in the memory array  600 . Addresses are supplied on bus  605  to column decoder  603  and row decoder  601 . Sense amplifier and data-in structures  606  are coupled to the column decoder  603  via data bus  607 . In many embodiments, the sense amplifier performs the comparison between the reference value and the stored value retrieved by applying a read bias arrangement to the memory array  600 . In some embodiments, a resistance ratio of the sense amplifier inputs is adjusted to adjust the sensing window. Data is supplied via the data-in line  611  from input/output ports on the integrated circuit  650 , or from other data sources internal or external to the integrated circuit  650 , to the data-in structures in block  606 . Data is supplied via the data-out line  615  from the sense amplifiers in block  606  to input/output ports on the integrated circuit  650 , or to other data destinations internal or external to the integrated circuit  650 . A bias arrangement state machine  609  controls the application of bias arrangement supply voltages  608 , such as for the erase verify and program verify voltages, and the arrangements for programming, erasing, and reading the memory cells. The bias arrangement state machine  609  causes the reference used by the sense amplifiers of block  606  to change in response to an error in comparison between check codes, as disclosed herein. Alternatively, the bias arrangement state machine  609  causes the read bias arrangement applied by the bias arrangement supply voltages  608  to the nonvolatile cell array  600  to change (e.g., a change to one or more word line voltages, and/or or one or more bit lines voltages) in response to an error in comparison between check codes, as disclosed herein. In yet another embodiment, both the reference used by the sense amplifiers of block  606  and the read bias arrangement applied by the bias arrangement supply voltages  608  are changed in response to an error in comparison between check codes, as disclosed herein. 
         [0093]      FIGS. 9-11  show the effect of changing the word line voltage of the read bias arrangement in an exemplary threshold voltage algorithm 
         [0094]      FIG. 9  shows the baseline exemplary threshold voltage algorithm. 
         [0095]      301  is the low bound of the low threshold voltage distribution B 1 .  302  is the high bound of the low threshold voltage distribution B 2 .  305  is the low bound of the high threshold voltage distribution B 3 .  306  is the high bound of the high threshold voltage distribution B 4 . A read bias arrangement will sense the memory data by applying a world line voltage Normal_VCell  907  and have a margin E 1   910  for charge loss of high threshold voltage cells and margin E 2   911  for charge gain of low threshold voltage cells. Although only two logical levels are shown, other embodiments have four or more logical levels to represent two or more bits. 
         [0096]      FIG. 10  shows an exemplary threshold voltage algorithm, similar to  FIG. 9  but with a changed read bias arrangement, favoring a low threshold voltage distribution in contrast with  FIG. 9 . 
         [0097]    The changed word line voltage Changed_Vcell  1007  was changed in response to a disagreement between check codes, such as in  740  of  FIG. 7  or  840  of  FIG. 8 . Changed_Vcell  1007  has a narrower read margin E 1 ′  1010  compared to E 1   910  and a wider read margin E 2 ′  1011  compared to E 2   911 , so Changed_Vcell  1007  has a smaller read window for high threshold voltage cells and a larger read window for low threshold voltage cells. In the event of excess net negative charge gain by the charge storage material of the nonvolatile memory cells, the threshold voltage will be incorrectly raised. Therefore, Changed_Vcell  1007  will be more likely to result in a correct determination of the represented logical level. 
         [0098]      FIG. 11  shows an exemplary threshold voltage algorithm, similar to  FIG. 9  but with another changed read bias arrangement, favoring a high threshold voltage distribution in contrast with  FIG. 9 . 
         [0099]    Similar but opposite to  FIG. 10 , Changed_Vcell  1107  has a wider read margin E 1 ″ 1110  compared to E 1   910  and a narrower read margin E 2 ″  1111  compared to E 2   911 , so Changed_Vcell  1107  has a smaller read window for low threshold voltage cells and a larger read window for high threshold voltage cells. In the event of excess net positive charge gain by the charge storage material of the nonvolatile memory cells, the threshold voltage will be incorrectly lowered. Therefore, Changed_Vcell  1107  will be more likely to result in a correct determination of the represented logical level. 
         [0100]    In another embodiment, net positive charge gain results in changing the reference to favor the lower threshold voltage cells, and net negative charge gain results in changing the reference to favor the higher threshold voltage cells. 
         [0101]      FIGS. 12-14  show example block diagrams of sense amplifier circuitry with variable resistance in the input circuits to change a sensing ratio. In one embodiment, a variable resistance is implemented with a transistor configured as a variable resistor. In one embodiment, such sense amplifier circuitry is included in the sense amplifier block  606  of  FIG. 6 . Example effects of changing the sensing ratio are shown in  FIGS. 16-18 . 
         [0102]      FIG. 12  shows an exemplary block diagram of sense amplifier circuitry, with variable resistance in the input circuits of both the signal from the memory array and the signal from the reference. 
         [0103]    The sense amplifier  1202  has a first input  1204  from the memory array, and a second input  1208  from the reference. The first input  1204  is part of a first input circuit including a variable resistance R ARRAY    1206 . The second input  1208  is part of a second input circuit including a variable resistance R REFERENCE    1210 . The first and second input circuits adjust the sensing window as shown in  FIGS. 16-18 , and the sensing ratio is expressed as R ARRAY /R REFERENCE . The output  1212  indicates result of the comparison of the two inputs and determines the data value stored in the memory. 
         [0104]      FIG. 13  shows an exemplary block diagram of sense amplifier circuitry, with variable resistance in the input circuit of the signal from the reference. 
         [0105]    The sense amplifier  1302  has a first input  1304  from the memory array, and a second input  1308  from the reference. The first input  1304  is part of a first input circuit including a fixed resistance R ARRAY    1306 . The second input  1308  is part of a second input circuit including a variable resistance R REFERENCE    1310 . The first and second input circuits adjust the sensing window as shown in  FIGS. 16-18 , and the sensing ratio is expressed as R ARRAY /R REFERENCE . The output  1312  indicates result of the comparison of the two inputs and determines the data value stored in the memory. 
         [0106]      FIG. 14  shows an exemplary block diagram of sense amplifier circuitry, with variable resistance in the input circuits of the signal from the memory array. 
         [0107]    The sense amplifier  1402  has a first input  1404  from the memory array, and a second input  1408  from the reference. The first input  1404  is part of a first input circuit including a variable resistance R ARRAY    1406 . The second input  1408  is part of a second input circuit including a fixed resistance R REFERENCE    1410 . The first and second input circuits adjust the sensing window as shown in  FIGS. 16-18 , and the sensing ratio is expressed as R ARRAY /R REFERENCE . The output  1412  indicates result of the comparison of the two inputs and determines the data value stored in the memory. 
         [0108]      FIGS. 16-18  show the effect of changing the sensing ratio of the sense amplifier input circuitry in an exemplary threshold voltage algorithm 
         [0109]      FIG. 16  shows yet another exemplary threshold voltage algorithm. 
         [0110]      301  is the low bound of the low threshold voltage distribution B 1 .  302  is the high bound of the low threshold voltage distribution B 2 .  305  is the low bound of the high threshold voltage distribution B 3 .  306  is the high bound of the high threshold voltage distribution B 4 . A read bias arrangement will sense the memory data by applying a world line voltage Normal Sensing Ratio R ARRAY /R REFERENCE    1607  and have a margin F 1   1610  for charge loss of high threshold voltage cells and margin F 2   1611  for charge gain of low threshold voltage cells. Although only two logical levels are shown, other embodiments have four or more logical levels to represent two or more bits. 
         [0111]      FIG. 17  shows an exemplary threshold voltage algorithm, similar to  FIG. 16  but with a changed sensing ratio, favoring a low threshold voltage distribution in contrast with  FIG. 16 . 
         [0112]    The Changed Sensing Ratio R ARRAY /R REFERENCE    1707  was changed in response to a disagreement between check codes, such as in  1540  of  FIG. 15 . Changed Sensing Ratio R ARRAY /R REFERENCE    1707  has a narrower read margin F 1 ′  1710  compared to F 1   1610  and a wider read margin F 2 ′  1711  compared to F 2   1611 , so Changed Sensing Ratio R ARRAY /R REFERENCE    1707  has a smaller read window for high threshold voltage cells and a larger read window for low threshold voltage cells. In the event of excess net negative charge gain by the charge storage material of the nonvolatile memory cells, the threshold voltage will be incorrectly raised. Therefore, Changed Sensing Ratio R ARRAY /R REFERENCE    1707  will be more likely to result in a correct determination of the represented logical level. 
         [0113]      FIG. 18  shows an exemplary threshold voltage algorithm, similar to  FIG. 16  but with another changed sensing ratio, favoring a high threshold voltage distribution in contrast with  FIG. 16 . 
         [0114]    Similar but opposite to  FIG. 17 , Changed Sensing Ratio R ARRAY /R REFERENCE    1807  has a wider read margin F 1 ″  1810  compared to F 1   1610  and a narrower read margin F 2 ″  1811  compared to F 2   1611 , so Changed Sensing Ratio R ARRAY /R REFERENCE    1807  has a smaller read window for low threshold voltage cells and a larger read window for high threshold voltage cells. In the event of excess net positive charge gain by the charge storage material of the nonvolatile memory cells, the threshold voltage will be incorrectly lowered. Therefore, Changed Sensing Ratio R ARRAY /R REFERENCE    1807  will be more likely to result in a correct determination of the represented logical level. 
         [0115]    In another embodiment, net positive charge gain results in changing the reference to favor the lower threshold voltage cells, and net negative charge gain results in changing the reference to favor the higher threshold voltage cells. 
         [0116]    While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.