Abstract:
A disclosed amplifier circuit is capable of changing a gain to amplify an input signal according to a control signal. The amplifier circuit comprises a differential amplifier circuit adapted to receive and amplify the input signal to output the amplified input signal as an output signal, a first resistance and one or more second resistances connected to the differential amplifier circuit and adapted to set the gain, and one or more gain control circuits adapted to change the gain by controlling one or more electrical couplings of the one or more second resistances according to the control signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   The present application claims priority to Japanese patent application number 2004-284856 filed on Sep. 29, 2004, which is incorporated herein by reference in its entirety. 
   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to an amplifier circuit and an input circuit, and particularly relates to an amplifier circuit and an input circuit capable of changing a gain. 
   2. Description of the Related Art 
   Apparatuses for processing video signals sometimes receive different levels of video signals depending on the type of devices connected thereto. The apparatuses therefore require input circuits for amplifying the input video signals to the level compatible with the devices and outputting the amplified signals. 
     FIG. 4  is a circuit diagram of a related-art input circuit  1 . 
   The input circuit  1  comprises first and second amplifier circuits  11  and  12  with voltage gain different from each other, and switching circuits  13  and  14 . 
   An input voltage Vin 1  from an input terminal Tin 1  is applied to the first and second amplifier circuits  11  and  12 . The first amplifier circuit  11  amplifies the input voltage Vin 1  applied from the input terminal Tin 1  at a voltage gain Gv 1 . The output of the first amplifier circuit  11  is sent out from an output terminal Tout 1  via the switching circuit  13 . 
   The second amplifier circuit  12  amplifies the input voltage Vin 1  applied from the input terminal Tin 1  at a voltage gain Gv 2 . The output of the second amplifier circuit  12  is sent out from an output terminal Tout 1  via the switching circuit  14 . 
   The switching circuit  13  is switched on/off according to a gain control signal CNTL 1 . The switching circuit  14  is switched on/off according to a signal /CNTL 1 , which is an inverted signal of the gain control signal CNTL 1 . Therefore, the switching circuit  13  is ON when the switching circuit  14  is OFF, and the switching circuit  13  is OFF when the switching circuit  14  is ON. 
   When the switching circuit  13  is ON and the switching circuit  14  is OFF, the input voltage Vin 1  of the input terminal Tin 1  is amplified by the first amplifier circuit  11  with the voltage gain Gv 1  and then output as an output voltage Vout 1  from the output terminal Tout 1 . When the switching circuit  13  is OFF and the switching circuit  14  is ON, the input voltage Vin 1  of the input terminal Tin 1  is amplified by the second amplifier circuit  12  with the voltage gain Gv 2  and then output as an output voltage Vout 2  from the output terminal Tout 1 . 
   This input circuit  1  of  FIG. 1  is not economical in power consumption, because both of the first and second amplifier circuits  11  and  12  are always driven. 
     FIG. 5  is a circuit diagram of another related-art input circuit  2 . In  FIG. 5 , elements identical to those in  FIG. 4  are denoted by the same reference numbers. 
   The input circuit  2  shown in  FIG. 5  is provided with a switching circuit  21  disposed between the first amplifier circuit  11  and a supply voltage Vcc for providing a drive voltage to the first amplifier circuit  11  in place of the switching circuit  13 , and a switching circuit  22  disposed between the second amplifier circuit  12  and a supply voltage Vcc for providing a drive voltage to the second amplifier circuit  12  in place of the switching circuit  14 . 
   The switching circuit  21  is switched on/off according to a gain control signal CNTL 2 . The switching circuit  22  is switched on/off according to a signal /CNTL 2 , which is an inverted signal of the gain control signal CNTL 2 . Therefore, the switching circuit  21  is ON when the switching circuit  22  is OFF, and the switching circuit  21  is OFF when the switching circuit  22  is ON. 
   When the switching circuit  21  is ON and the switching circuit  22  is OFF, the first amplifier circuit  11  is in an operating state and the second amplifier circuit  12  is in a suspended state. The input voltage Vint 1  input from the input terminal Tin 1  is amplified by the first amplifier circuit  11  with the voltage gain Gv 1 , and then output as an output voltage Vout 1  from the output terminal Tout 1 . On the other hand, when the switching circuit  21  is OFF and the switching circuit  22  is ON, the first amplifier circuit  11  is in the suspended state and the second amplifier circuit  12  is in the operating state. The input voltage Vint 1  input from the input terminal Tin 1  is amplified by the second amplifier circuit  12  with the voltage gain Gv 2 , and then output as an output voltage Vout 2  from the output terminal Tout 1 . 
   The input circuit  2  can reduce the power consumption, because it can suspend the operation of either one of the amplifier circuits  11  and  12  by having the switching circuit  21  disposed between the supply voltage Vcc and the first amplifier circuit  11  and the switching circuit  22  disposed between the supply voltage Vcc and the second amplifier circuit  12 . 
   However, this type of amplifier circuit needs to have plural differential amplifier circuits each having a resistance to set a specified gain, and therefore increases the size of the circuit as well as, if applied to IC chips, the chip area. 
   Also, a complicated control mechanism is required in order to operate one differential amplifier circuit and to stop the rest of the differential amplifier circuits by suspending the power supply thereto. 
   SUMMARY OF THE INVENTION 
   A general object of the present invention is to provide an amplifier circuit to overcome at least one disadvantage described above. A specific object of the present invention is to provide a simple amplifier circuit capable of changing a gain. 
   According to an aspect of the present invention, an amplifier circuit capable of changing a gain to amplify an input signal according to a control signal comprises a differential amplifier circuit adapted to receive and amplify the input signal to output the amplified input signal as an output signal, a first resistance and one or more second resistances connected to the differential amplifier circuit and adapted to set the gain, and one or more gain control circuits adapted to change the gain by controlling one or more electrical couplings of the one or more second resistances according to the control signal. 
   It is preferable that an end of the second resistance be connected to the differential amplifier circuit, and the gain control circuit be configured to switch the state of the other end of the resistance between an open state and a state where a reference voltage is applied thereto. 
   It is also preferable that the second resistances be plural resistances connected in series or in parallel, and the one or more gain control circuits be adapted to short-circuit or open an end of each of the plural second resistances. 
   According to the present invention, by switching on/off the connection of the resistances connected to the differential amplifier circuit according to the control signal, the gain of the amplifier circuit formed by the differential amplifier circuit and the resistances is changed. As such, simply having one differential amplifier circuit allows the gain control. The amplifier circuit can therefore result in a reduced chip area, if applied to an IC. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a circuit diagram of an amplifier circuit according to a first embodiment of the present invention; 
       FIG. 2  is a circuit diagram of an amplifier circuit according to a second embodiment of the present invention; 
       FIG. 3  is a circuit diagram of an amplifier circuit according to a third embodiment of the present invention; 
       FIG. 4  is a circuit diagram of a related-art input circuit; and 
       FIG. 5  is a circuit diagram of another related-art input circuit. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
   First Embodiment 
     FIG. 1  is a circuit diagram of an amplifier circuit  100  according to a first embodiment of the present invention. 
   The amplifier circuit  100  according to the first embodiment comprises a differential amplifier circuit  111 , resistances R 11  and R 12 , and a gain control circuit  112 . 
   The differential amplifier circuit  111  has a non-inverting input terminal Tin, to which a voltage Vin 11  is applied. An output terminal Tout and an inverting input terminal of the differential amplifier circuit  111  are connected through the resistance R 12 . The inverting input terminal of the differential amplifier circuit  111  is also connected to the gain control circuit  112  through the resistance R 11 . The differential amplifier circuit  111  amplifies the input voltage Vin 11  and outputs an output voltage Vout 11 . 
   An end of the resistance R 11  is connected to a connection point between the inverting input terminal of the differential amplifier circuit  111  and the resistance R 12 . An end of the resistance R 12  is connected to a connection point between the inverting input terminal of the differential amplifier circuit  111  and the end of the resistance R 11 , while the other end of the resistance R 12  is connected to the output terminal side of the differential amplifier circuit  111 . 
   The gain control circuit  112  comprises constant current sources  121  and  122 , the transistors Q 11  through Q 16 , and resistances R 21  through R 24 . The gain control circuit  112  has a gain control terminal Tcnt, from which a gain control signal CNTL 11  is provided. The gain control signal CNTL 11  from the gain control terminal Tcnt is provided to a base of the transistor Q 11  through the resistance R 21  and to a base of the transistor Q 13  through the resistance R 22 . 
   The transistor Q 11  is a NPN transistor, having a collector connected to the constant current source  121  and a grounded emitter. The transistor Q 11  is turned ON when the gain control signal CNTL 11  is low level, and is tuned OFF when the gain control signal CNTL 11  is high level. 
   The transistors Q 12  and Q 16 , each comprising a NPN transistor, form a current mirror circuit. The transistor Q 12  has a collector connected to a connection point between the constant current source  121  and the collector of the transistor Q 11  and to a base of the transistor Q 16 , and an emitter grounded through the resistance R 23 . The transistor Q 16  has a base connected to a connection point of the constant current source  121 , the collector of the transistor Q 11 , and the collector and base of the transistor Q 12 , a collector connected to the other end of the resistance R 11 , and an emitter grounded through the resistance R 24 . 
   The transistors Q 12  and Q 16  of the current mirror circuit are both turned ON when the transistor Q 11  is turned OFF, and are both turned OFF when the transistor Q 11  is turned ON. 
   The transistor Q 13  is a NPN transistor, having a base connected to the gain control terminal Tcnt through the resistance R 22 , a collector connected to the constant current source  122  and a base of the transistor Q 14 , and a grounded emitter. The transistor Q 13  is turned ON to lower the base voltage of the transistor Q 14 , when the gain control signal CNTL 11  provided to the gain control terminal Tcnt is high level. The transistor Q 13  is turned OFF to increase the base voltage of the transistor Q 14 , when the gain control signal CNTL 11  is low level. 
   The transistor Q 14  is a NPN transistor, having a base connected to a connection point between the constant current source  122  and the collector of the transistor Q 13 , an emitter connected to a base of the transistor Q 15 , and a collector to which a reference voltage Vref is applied. When the transistor Q 14  is ON, the base voltage of the transistor Q 15  is set to the reference voltage Vref. 
   The transistor Q 15  is a NPN transistor, having a base connected to the emitter of the transistor Q 14 , a collector to which a supply voltage Vcc is applied, and an emitter connected to a connection point A between the other end of the resistance R 11  and the collector of the transistor Q 16 . The transistor Q 15  is turned ON to apply the reference voltage Vref with a base-emitter voltage Vbe of the transistor Q 15  taken therefrom to the other end of the resistance R 11 , when the transistor Q 14  is turned ON. The transistor Q 15  is turned OFF to keep the other end of the resistance R 11  in an open state, when the transistor Q 14  is turned OFF. 
   [Operations] 
   When the input signal CTRL 11  is high level, the transistors Q 11  and Q 13  are turned ON. As the transistor Q 11  is turned ON, the transistors Q 12  and Q 16  are turned OFF. Also, as the transistor Q 13  is turned ON, the transistor Q 15  is turned OFF. 
   As the transistors Q 15  and the Q 16  are tuned OFF, the impedance of the connection point A to which the other end of the resistance R 11  is connected becomes high. As the impedance of the connection point A becomes high, the amplifier circuit  100  is made to have only the resistance R 12  connected to the differential amplifier circuit  111 . In this state, the voltage gain Gv of the amplifier circuit  100  is as follows.
 
Gv=0
 
   On the other hand, when the input signal CTRL 11  is low level, the transistors Q 11  and Q 13  are turned OFF. As the transistor Q 11  is turned OFF, the transistors Q 12  and Q 16  are turned ON. Also, as the transistor Q 13  is turned OFF, the transistor Q 15  is turned ON. Accordingly, the reference voltage Vref with the base-emitter voltage Vbe of the transistor Q 15  taken therefrom is applied to the connection point A through the transistors Q 14  and Q 15 . The other end of the resistance R 11  is therefore set to the reference voltage Vref with the base-emitter voltage Vbe of the transistor Q 15  taken therefrom. 
   As the other end of the resistance R 11  is set to the reference voltage Vref with the base-emitter voltage Vbe of the transistor Q 15  taken therefrom, the amplifier circuit  100  is made to have both of the resistances R 11  and R 12  connected to the differential amplifier circuit  111 . In this state, the voltage gain Gv of the amplifier circuit  100  is as follows.
 
 Gv =20 log(( R 11 +R 12/ R 11))
 
   In this way, the gain control circuit  112  switches the state of the other end of the resistance R 11  between the open state and the state where the reference voltage Vref with the base-emitter voltage Vbe of the transistor Q 15  is applied, and thus connects or disconnects a resistance to the connection point between the inverting input terminal of the differential amplifier circuit  111  and the resistance R 12 . This allows the amplifier circuit  100  to change its gain. 
   [Advantages and Effects] 
   According to this embodiment, the differential amplifier circuit  111  is switched between the state where only the resistance R 12  is connected thereto and the state where both of the resistances R 11  and R 12  are connected thereto in accordance with the gain control signal CNTL 11 , so that the voltage gain Gv of the amplifier circuit, which comprises the differential amplifier circuit  111  and the resistances R 11  and R 12 , is switched between two levels, i.e., 0 and {20 log((R 11 +R 12 )/R 11 )}. As such, having one differential amplifier circuit  111  allows the gain control, so that the voltage gain Gv is changed with such a simple configuration. The amplifier circuit can therefore have a reduced chip area, if applied to an IC. 
   Also, only the differential amplifier circuit  111  needs to be driven for either level of the gain, thereby minimizing the power consumption. 
   Second Embodiment 
     FIG. 2  is a circuit diagram of an amplifier circuit  200  according to a second embodiment of the present invention. In  FIG. 2 , elements identical to those in  FIG. 1  are denoted by the same reference numbers. 
   In the amplifier circuit  200  according to the second embodiment, a parallel circuit formed by resistances R 31  and R 32  is provided in place of the resistance R 11 . An end of the resistance R 31  is connected to the gain control circuit  112 . The gain control circuit  112  switches the state of the other end of the resistance R 31  between the open state and the state where the reference voltage Vref is applied thereto. 
   When the gain control circuit  112  sets the resistance R 31  to the open state, only the resistance R 32  is connected to a connection point between the inverting input terminal of the differential amplifier circuit  111  and the resistance R 12 . When the gain control circuit  112  sets the other end of the resistance R 31  to the state where the reference voltage Vref is applied, the parallel circuit formed by the resistances R 31  and R 32  is connected to the connection point between the inverting input terminal of the differential amplifier circuit  111  and the resistance R 12 . 
   In this way, the gain control circuit  112  switches the state of the other end of the resistance R 31  between the open state and the state where the reference voltage Vref is applied, and thus changes the resistance of the connection point between the inverting input terminal of the differential amplifier circuit  111  and the resistance R 12 . This allows the amplifier circuit  200  to change its gain. 
   Third Embodiment 
     FIG. 3  is a circuit diagram of an amplifier circuit  300  according to a third embodiment of the present invention. In  FIG. 3 , elements identical to those in  FIG. 1  are denoted by the same reference numbers. 
   In the amplifier circuit  300  according to the third embodiment, a series circuit formed by resistances R 41 , R 42  and R 43  is provided in place of the resistance R 11 . An end of the resistance R 42  is connected to a first gain control circuit  311 , and an end of the resistance R 43  is connected to a second gain control circuit  312 . 
   The first gain control circuit  311  sets the end of the resistance R 42  to a short-circuited state or the open state according to a gain control signal CNTL 21 . The second gain control circuit  312  sets the end of the resistance R 43  to the short-circuited state or the open state according to a gain control signal CNTL 31 . 
   When the first gain control circuit  311  sets the end of the resistance R 42  to the short-circuited state, only the resistance R 41  is connected to a connection point between the inverting input terminal of the differential amplifier circuit  111  and the resistance R 12 . When the first gain control circuit  311  sets the end of resistance R 42  to the open state, and the second gain control circuit  312  sets the end of the resistance R 43  to the short-circuited state, the resistances R 41  and R 42  are connected to the connection point between the inverting input terminal of the differential amplifier circuit  111  and the resistance R 12 . 
   When the first gain control circuit  311  sets the end of resistance R 42  to the open state, and the second gain control circuit  312  sets the end of resistance R 43  to the open state, the series circuit formed by the resistances R 41  through R 43  is connected to the connection point between the inverting input terminal of the differential amplifier circuit  111  and the resistance R 12 . 
   In this way, the first gain control circuit  311  and the second gain control circuit  312  connect or open the ends of the resistances R 42  and R 43 , and thus change the resistances connected to the connection point between the inverting input terminal of the differential amplifier circuit  111  and the resistance R 12 . This allows the amplifier circuit  300  to change its gain. 
   The present application is based on Japanese Priority Application No. 2004-284856 filed on Sep. 29, 2004, with the Japanese Patent Office, the entire contents of which are hereby incorporated by reference.