Abstract:
A resistive random access memory (RRAM) cell including a first electrode, a second electrode, and a plurality of repeated sets of layers is provided. Each of the sets of layers includes a resistance-changing layer, a barrier layer, and an ionic exchange layer between the resistance-changing layer and the barrier layer, wherein a thickness of each of the resistance-changing layer, the barrier layer and the ionic exchange layer exceeds a Fermi wavelength, and the thickness each of the resistance-changing layer and ionic exchange layer are less than an electron mean free path. Further, a RRAM module including the aforesaid RRAM cell and a switch is also provided.

Description:
BACKGROUND OF THE DISCLOSURE 
       [0001]    1. Field of the Disclosure 
         [0002]    The present disclosure relates to a resistive random access memory (RRAM) cell and RRAM module. More particularly, the present disclosure relates to a multilayer RRAM cell and a multilayer RRAM module. 
         [0003]    2. Description of Related Art 
         [0004]    RRAM has recently gained tremendous popularity due to its fast resistance switching while consuming low power. A key advantage of RRAM has been its ability to operate at lower operation current compared to other new nonvolatile memory candidates, such as phase-change memory (PCM). The operation current of RRAM is directly related to the cross-section area but to the input currents (I SET  and I RESET ) during the initial filament forming operation (SET operation) and the subsequent initial filament rupture operation (RESET operation). In order to reduce operation current of RRAM, the minimum resistance of the RRAM must be increased to an appropriate level. 
         [0005]      FIG. 1  is a circuit diagram illustrating an oxide-based RRAM during SET operation,  FIG. 2  is a circuit diagram illustrating an oxide-based RRAM during RESET operation. Referring to  FIG. 1 , the oxide-based RRAM  120  is electrically connected to a transistor  100 . During the SET operation, a first voltage V GH, set  is applied to turn on the transistor and a SET voltage V SET  is applied between the anode  126  and cathode  122  resulting in the displacement of oxygen ions  160  in the oxide  124 , leaving oxygen vacancies  150  behind, to generate a SET current I SET  flowing through a percolating conduction path  170  formed of such vacancies ( FIG. 1 ). During the RESET operation, a second voltage V GH, reset  is applied to turn on the transistor and a RESET voltage V RESET  is applied to generate a RESET current I RESET  flowing through the transistor and the oxide-based RRAM sequentially ( FIG. 2 ). Recombined vacancies  180  may be generated in the low current generated filament during the RESET operation. 
         [0006]      FIG. 3  is a diagram illustrating the relationship between resistance of an oxide-based RRAM and ramping voltage. It is likely that a filament generated by a low current includes a broken path fairly separated oxygen vacancies, so that during the RESET operation, the oxide between traps may actually be broken down, causing a SET operation (i.e. filament re-generation) instead of RESET operation. As shown in  FIG. 3 , this inadvertent SET operation leads to a reduction of resistance of RRAM. Owing to the fact that the filament extends over a distance (e.g. 5-10 nm) less than the electron mean free path (&gt;20 nm), the electron in the regenerated filament has ballistic transport, and therefore the filament is of low resistance (at least 1/G 0 =1/(2e 2 /h) ˜13 k-ohm, where e is the electron charge, and h is Planck&#39;s constant.). During RESET operation, the input current (I RESET ) must rise to value equal to the RESET voltage (V RESET ) divided by resistance of this filament. For this example, for a RESET voltage (V RESET ) of 1.3V, the RESET current (I RESET ) rises to ˜100 μA. Ramping the voltage further, the actual RESET process begins, to be followed by progressive breakdown at an excessive voltage (above 2 V in this case). Due to this undesired effect, the reduction of operation current of RRAM below 100 μA may not be possible when RESET operation is performed, as the RESET voltage (V RESET ) is continually ramped. 
         [0007]    In a thicker film, the mean free path may be less than the thickness, and so there is no ballistic transport. However, thicker films have generally been avoided due to their much larger forming voltage (i.e. SET voltage, V SET ). 
         [0008]    It is possible to operate RRAM at extremely low currents (&lt;μA) and consequently also very high SET state resistance. However, in this case, the SET operation may not produce well-defined filaments. As a result, simply operating RRAM by brute force ultra-low currents may not be satisfactory. 
       SUMMARY 
       [0009]    The present disclosure provides a multilayer RRAM cell and a RRAM module. 
         [0010]    The present disclosure provides a RRAM cell including a first electrode, a second electrode, and a plurality of repeated sets of layers is provided. Each of the sets of layers includes a resistance-changing layer, a barrier layer, and an ionic exchange layer between the resistance-changing layer and the barrier layer, wherein a thickness of each of the resistance-changing layer, the barrier layer and the ionic exchange layer exceeds a Fermi wavelength, and the thickness of each of the resistance-change layer and the ionic exchange layer is less than an electron mean free path. 
         [0011]    The present disclosure provides a resistive random access memory module (RRAM module) electrically coupled to a SET voltage and a RESET voltage is provided. The RRAM module includes a switch electrically coupled to the RESET voltage and the aforesaid RRAM cell, wherein the first electrode is electrically coupled to a bit line, the second electrode is electrically coupled to the switch, a resistance of the repeated sets of layers of the RRAM cell is R 1 , a resistance of the switch is R 2 , and 3≦R 1 /R 2  during RESET operation. 
         [0012]    In order to the make the aforementioned and other features and advantages of the present disclosure more comprehensible, several embodiments accompanied with figures are described in detail below. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    The accompanying drawings constituting a part of this specification are incorporated herein to provide a further understanding of the disclosure. Here, the drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. 
           [0014]      FIG. 1  is a circuit diagram illustrating an oxide-based RRAM during SET operation. 
           [0015]      FIG. 2  is a circuit diagram illustrating an oxide-based RRAM during RESET operation. 
           [0016]      FIG. 3  is a diagram illustrating the relationship between resistance of an oxide-based RRAM and ramping voltage. 
           [0017]      FIG. 4  schematically illustrates a tri-layer that may be repeated in an embodiment in the disclosure. 
           [0018]      FIG. 5  schematically illustrates another tri-layer that may be repeated in another embodiment in the disclosure. 
           [0019]      FIG. 6A  shows one embodiment in the disclosure. 
           [0020]      FIG. 6B  shows another embodiment in the disclosure. 
           [0021]      FIG. 6C  shows a third embodiment in the disclosure. 
           [0022]      FIG. 7A  shows a cross section of a fourth embodiment in the disclosure. 
           [0023]      FIG. 7B  shows a top view of a fourth embodiment in the disclosure. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0024]    In order to prevent the inadvertent SET operation described in connection with  FIG. 3 , this disclosure provides a novel structure of the RRAM cell having high resistance. Instead of increasing LRS value and lowering RESET current by reducing the SET current to form a broken filament, this disclosure stacks a plurality of repeated sets of layers to obtain the target resistance. 
         [0025]      FIG. 4  schematically illustrates a key feature of the RRAM of an embodiment in the disclosure. The RRAM of this embodiment includes a plurality of repeated sets of layers  400 . Each of the sets of layers  400  includes a resistance-changing layer  401  (e.g., HfOx), a barrier layer  403  (e.g., TiN), and an ionic exchange layer  402  (e.g., TiOx) between the resistance-changing layer  401  and the barrier layer  403 , wherein a thickness of each of the resistance-changing layer  401 , the barrier layer  403 , and the ionic exchange layer  402  exceeds the Fermi wavelength (i.e. the deBroglie wavelength corresponding to the Fermi energy). For typical metals or oxides, the Fermi energy is in the range of 7˜10 eV, and the corresponding deBroglie wavelength (Fermi wavelength) is in the range of 0.4˜0.5 nm. This prevents electron wave-functions from blurring boundaries and interfaces between layers (i.e. the resistance-changing layer  401 , the barrier layer  403  and the ionic exchange layer  402 ). 
         [0026]    Additionally, to ensure ballistic transport, the thickness of each of the resistance-changing layer  401  and the ionic exchange layer  402  is less than electron mean free path. For energies of 2 eV or less above Fermi level, the mean free path is well above 10 nm (L. C. Feldman and J. W. Mayer Fundamentals of Surface and Thin Film Analysis, p. 129). The barrier layer  403  prevents mixing of layers between each set  130  and also quantum mechanically decoheres the electron, so that the ballistic transport is only counted between the barrier layers, which also serve as intermediate electrodes. 
         [0027]    In an alternative embodiment, shown in  FIG. 5 , the barrier layer may not be a metal but a thin tunneling barrier layer  503 , such as AlOx, which can transmit a fraction of incident electrons. The thickness of this layer is less than the mean free path, to ensure ballistic transport as well. For example, the material of the resistance-changing layer  501  is HfOx and the material of the ionic exchange layer  502  is TiOx. 
         [0028]      FIGS. 6A ,  6 B, and  6 C show three different embodiments of the RRAM in this disclosure. In  FIG. 6A , the conductor barrier/ion exchange layer/resistance-change layer  400  is repeated, each repetition adding at least 1/G0 ˜13 K-ohm to the minimum resistance, where G0 is the quantum unit of conductance 2e 2 /h, where e is the electron charge, and h is Planck&#39;s constant. In a typical example of this case, the material of the resistance-changing layer  401  is HfOx, the material is the barrier layer  403  is TiNx, and the material of the ionic exchange layer  402  is TiOx, for example. In addition, the thickness of the resistance-changing layer  401  is about 1˜2 nm, the thickness of the barrier layer  403  is about 1˜2 nm, and the thickness of the ionic exchange layer  402  is about 1 nm. The total thickness of one set of layers  400  is therefore about 3˜5 nm. When the number of the repeated sets of layers  130  is 10, the total thickness of the repeated sets of layers  130  is about 30˜50 nm, which exceeds the electron mean free path. When the barrier layer  403  is a metal with well-defined Fermi level or chemical potential, the repeated sets of layers  400  allow the resistance thereof to increase above ˜130 K-ohms and the corresponding RESET current can be under 10 μA. 
         [0029]    In an embodiment, the resistance-changing layer  401  and the ionic exchange layer  402  can substantially be the same material, but with different stiochiometries. The barrier layer  403  is conductive and serves as electron reservoir. The barrier layer  403  is capable of scattering electrons due to its grain boundary and roughness. Additionally, the barrier layer  403  is capable of preventing each of the ionic exchange layers  402  from reacting with more than one resistance-changing layer  401 . Specifically, each of the ionic exchange layers  402  is sandwiched between and in contact with one resistance-changing layer  401  and one barrier layer  403 . 
         [0030]    The material of the first electrode  601  and the second electrode  610  is proposed to use relatively inert materials. In this embodiment, the material of the first electrode  601  and the second electrode  610  is TiNx, for example. It is noted that, the first electrode  601  and the second electrode  610  do not interact with the repeated sets of layers  400 . Only the internal ion exchange (e.g. oxygen vacancies of HfOx) in the resistance-changing layer  401  should be utilized for the resistance switching. 
         [0031]      FIG. 6B  schematically illustrates the RRAM of another embodiment in the disclosure. In this embodiment, the tunnel barrier/ion exchange/resistance-change layer  500  is repeated. The AlOx barrier layer  503  is capable of preventing mixture of other layers (i.e. the resistance-changing layer  501  and the ionic exchange layer  502 ). In addition, the AlOx barrier layer  134 ′ is at least partially electron transmitting. 
         [0032]    In this embodiment, the thickness of each of the resistance-changing layer  501 , the barrier layer  503  and the ionic exchange layer  502  must be less than electron mean free path but exceeds the Fermi wavelength, to preserve the ballistic transport. For example, the thickness of the resistance-changing layer  501  is about 1.5˜3 nm, the thickness of the barrier layer  503  is about 2˜4 nm, and the thickness of the ionic exchange layer  502  is about 1˜3 nm. The total thickness of one set of layers  500  is about 4.5˜10 nm, for example. When the number of the repeated sets of layers  500  is large enough, e.g., 10, the total thickness of the repeated sets of layers  500  is about 45˜100 nm, which well exceeds the electron mean free path. 
         [0033]      FIG. 6C  shows the embodiment where the repeated layers may actually be a mixture or combination of  400  and  500 . It is noted that the material of the ionic exchange layer  402  and that of the ionic exchange layer  502  may be identical or different from each other. In addition, the material of the resistance-changing layer  401  and that of the resistance-changing layer  501  may be identical or different from each other. 
         [0034]    In a fourth embodiment, shown in  FIGS. 7A and 7B , the issue of ballistic transport is avoided altogether by deliberately putting a twist in the conduction path outside the resistance-changing material  713  and ionic exchange region located in a contacting feature  714  adjacent the resistance-changing material  713 . Furthermore, this twisted path is constructed in a resistive buffer material  715 , such as Si or TiOx, whose resistance is also controlled by the voltage across it. When the voltage across the buffer is large enough, the current through the resistance-changing material is sufficient to carry out the SET or RESET operation at a reduced level. The thickness of this material is also thinner than the bulk mean free path of the material. The thickness therefore becomes the new, greatly reduced mean free path, and so the resistance of the twisted path is sufficiently high to limit the RESET current as well as the voltage applied to the resistance-changing material. The resistance is deliberately enhanced with the distance between the contacting feature  714  and substrate contact  716 , as well as between the contacting feature  714  and the contact  710  from the bit line to the top electrode  712 . 
         [0035]    In aforesaid embodiments of this disclosure, by stacking multiple pairs of resistance-changing layer/ionic exchange layer in series, the pairs of resistance-changing layer/ionic exchange layer are separated by inert, conductive, scattering barrier layers. In those aforesaid embodiments of this disclosure, not only the RESET current can be reduced, but also the forming voltage can be reduced. 
         [0036]    Although the present disclosure has been disclosed above by the embodiments, they are not intended to limit the present disclosure. Anyone skilled in the art can make some modifications and alteration without departing from the spirit and scope of the present disclosure. Therefore, the protecting range of the present disclosure falls in the appended claims.