Abstract:
A voltage divider circuit can be realized by dividing a higher than rated operating voltage across a plurality of MOS transistors. The voltage divider circuit can be used for a wide variety of ratios of low and high operating voltages. Only one gate input voltage is needed, minimizing power dissipation, heat, and hot carrier effects. The voltage divider circuit is employed in a voltage driver circuit to generate a high output voltage in response to a low voltage input while minimizing damage to the MOS transistors within the voltage driver circuit.

Description:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH  
       [0001]     This invention was at least partially made with U.S. Government support under contract DTRA01-00-C-0017 awarded by the Defense Threat Reduction Agency. Accordingly, the government may possess certain rights in the invention. 
     
    
     FIELD  
       [0002]     The present invention relates generally to integrated circuits, and more particularly, to a circuit and a method that outputs a desired voltage while minimizing higher than rated voltages across MOS transistors.  
       BACKGROUND  
       [0003]     As CMOS technology advances, device sizes and areas continue to decrease, while performance (increased speed, decreased power consumption and heat dissipation, etc.) has improved. Correspondingly, transistor operating voltages have followed this trend. An example of this can be seen in the shift from operating at 5V to 3.3V and even 2.5V.  
         [0004]     Despite the continuing trend to move to lower operating voltages, many circuit designers are still constrained to design circuits that are compatible with both high and low operating voltages. One such reason being that many established circuits, such as the ones found in standard design libraries, need to be implemented in a cost effective way. Redesigning a given circuit for a lower operating voltage may be too costly in terms of time or other financial considerations.  
         [0005]     When trying to use two circuits with different operating voltages, often times a lower voltage transistor is used and operated at higher voltages. Despite this, using higher than rated voltages (i.e. a 5V supply on a 2.5V device) can cause many problems. Too high of an operating voltage applied to an individual transistor may result in damage and, as a consequence, an entire circuit might also be damaged. Two types of damage that frequently arise when a higher than rated voltage is applied across a transistor are hot carrier effects and transistor breakdown.  
         [0006]     Although a low operating voltage transistor may be used with a higher operating voltage, it is quite difficult to produce a 5V output from a 2.5V operating voltage transistor. Circuit designers overcome this problem by employing output driver circuits. These circuits convert voltages from a low operating voltage value (2.5 V or 3.3V) to a higher operating voltage value (5V). The converted voltage can then be effectively applied to a circuit. One issue in creating these circuits, particularly when using technology that employs lower operating voltages, is that unless an output driver is designed properly, the transistors in the output driver itself are still exposed to high operating voltages which, as stated previously, may result in eventual circuit breakdown.  
         [0007]     One such structure and method of reducing the amount of applied operating voltage, disclosed by Hynes in U.S. Pat. No. 6,518,818, has been to reduce the amount of voltage applied across the source and drain terminals of a lower operating voltage FET transistor. This can be seen in  FIG. 1 . In this figure, a series of two p-FETs are tied together at their respective source and drain connections. An overall input  102  (0V or 3.3V) is received by the circuit and an output voltage  104  indicative of the overall input to the circuit is output (0V for a 0V input, 5V for a 3.3V input). An input voltage  106  (in this case from a common node of two p-FETs) is input into the gate of a p-FET  108 . If this FET could withstand a 5V drop from source to drain (as would be the case when the output  104  is at 0V and the drain voltage  105  is 5V) the second transistor  110  and the additional applied bias V REF    112 , would not be necessary. However, these components are necessary to produce a voltage, namely V REF  plus the threshold voltage V p , at node  114  in order to reduce the overall voltage drop across a single transistor. Thus, the damaging effects of too high of an operating voltage across one transistor are reduced.  
         [0008]     This method and circuit, and those similar to it, have a considerable drawback. This circuit necessitates an extra voltage source, namely V REF . V REF  is continually applied to the gate of a MOS transistor; this results in static current dissipation leading to increased power consumption and heat dissipation. Thus, it would be desirable to provide a circuit and a method that outputs a desired voltage while minimizing higher than rated voltages across MOS transistors.  
       SUMMARY  
       [0009]     One embodiment provides for a voltage divider circuit comprised of a series of stacked MOS transistors. By dividing a higher than rated operating voltage across a plurality of MOS transistors, a higher than rated operated voltage can be effectively distributed across a series of MOS transistors. Only one gate input voltage is needed, eliminating the need for additional reference voltages. The voltage divider circuit presented in this application can be used for a wide variety of ratios of low and high operating voltages. The resultant circuit minimizes static current loss and power dissipation as well as reduces hot carrier effects. The voltage divider circuit is employed in a voltage driver circuit to generate a high output voltage in response to a low voltage input.  
         [0010]     These as well as other aspects and advantages of the present invention will become apparent to those of ordinary skill in the art by reading the following detailed description, with appropriate reference to the accompanying drawings.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]     Presently preferred embodiments are described below in conjunction with the appended drawing figures, wherein like reference numerals refer to like elements in the various figures, and wherein:  
         [0012]      FIG. 1  is a schematic drawing of a prior art method for reducing a high operating voltage applied to a transistor;  
         [0013]      FIG. 2   a  is a schematic drawing of a circuit employing the method of reducing operating voltage in a p-MOS transistor in accordance with a first embodiment of the invention;  
         [0014]      FIG. 2   b  is a schematic drawing of a circuit employing the method of reducing operating voltage in an n-MOS transistor in accordance with a second embodiment of the invention;  
         [0015]      FIG. 3  is a schematic drawing of an output driver in accordance with a third embodiment of the invention; and  
         [0016]      FIG. 4  is a schematic drawing of an output driver using an inverter and a level shift inverter employing the method for reducing too high on an operating voltage across a transistor in accordance with a fourth embodiment of the invention.  
     
    
     DETAILED DESCRIPTION  
       [0017]      FIG. 2   a  is a schematic drawing of a voltage divider circuit  200   a  comprising a series of stacked p-MOS transistors. An input voltage  204  (0V or VDD 2 ) is received by the circuit  200   a  and an output voltage  206 , in response to the input  204  or additional circuitry, is output (0V or VDD 2 ). The input  204  is fed into the gates of p-FET transistors  208  and  210 . The source of p-MOS transistor  208  is connected to VDD 2   212 . If the voltage of the output  206  is at 0V, the voltage from the output  206  to VDD 2   212  is effectively distributed across both transistors. That is, the voltage at node  214  is effectively half of VDD 2  for identical p-MOS transistors. By tying both transistors together at their respective gates, an arbitrary voltage reference is not necessary to insure safe operating voltages across the transistors. Eliminating this reference voltage eliminates undesired current and heat dissipation that is typically caused by having at least one transistor always at least partially on.  
         [0018]     In essence, when the input  204  is at a voltage level about equal to VDD 2 , both transistors  208  and  210  are off and the voltage drop across both transistors is evenly distributed. When the input goes to a low voltage, both transistors are on, but the voltage drop across both transistors still remains distributed across both transistors. One additional benefit is that the reduced voltage drop also provides reduced hot carrier effects when the devices are on. Also illustrated in  FIG. 2   a  is the implementation of this configuration with existing as well as future technologies by application of Equation 1:  
             N   =     ⌈       VDD   ⁢           ⁢   2     VDD     ⌉             Eq   .           ⁢   1             
 
 For example, if transistors with a 1.7 V operating voltage are desired to be integrated with a 5V operating voltage technology, by application of the above formula, the number, N, of necessary transistors would be three. A phantom p-MOS transistor  216  is shown between the transistors  208  and  210  to exemplify this application. 
 
         [0019]      FIG. 2   b  is a schematic drawing of a voltage divider circuit  200   b  comprising a series of stacked n-MOS transistors. Similar to  FIG. 2   a , an input voltage  205  (0V or VDD) is received by the circuit and an output voltage  206 , in response to the input  205  or additional circuitry, is output (0V or VDD 2 ). Because the transistors are off when a voltage of 0V is applied to the input  205 , the input voltage does not need to be at the higher operating voltage VDD 2  to insure the transistors are off. Therefore, a level-shift inverter is not required. The input  205  is fed into the gates of n-FET transistors  209  and  211 . The source of n-MOS transistor  211  is connected to a ground or common potential  213 . If the voltage of the output  206  is at VDD 2 , the voltage from the output  206  to the common potential  213  is effectively distributed across both transistors. Again, the voltage at node  215  is effectively half of VDD 2  if the n-MOS transistors are identical. Similar to the embodiment in  FIG. 2 , an arbitrary voltage reference is not necessary to ensure safe operating voltages across the transistors. As in the previous embodiment, the elimination of the reference voltage eliminates undesired current and heat. In addition, reduced hot carrier effects are also realized. If future designs require different operating voltages, Equation 1 can also be applied to determine the number of series transistors (as illustrated by the insertion of n-MOS transistor  217 ).  
         [0020]      FIG. 3  is a schematic drawing of an output voltage driver circuit  300  comprising a series of stacked n-MOS and p-MOS transistors. An input  301 , corresponding to a low voltage input (in the range of 0V to a low operating voltage value, VDD) is input into the output voltage driver circuit  300  and is translated into a higher operating voltage at the output  206  (in the range of 0V to a high operating voltage value, VDD 2 ). That is, an input at input  301  with a voltage value of 0V will translate into a 0V output at  206  while an input of VDD will translate into a higher operating voltage output of VDD 2 .  
         [0021]     The translation is carried out as follows: the input  301  is fed into a level shift inverter  320  and an inverter  330 . The level shift inverter  320  inverts an input voltage to either 0V or VDD 2  depending on the input (i.e. 0V at input  301  results in a VDD 2  output of the level shift inverter and VDD at input  301  results in a 0V output of the level shift inverter). The output of the level shift inverter is input into the voltage divider circuit of  FIG. 2   a    200   a  at input  204 . When the gates of p-MOS transistors  208  and  210  (as well as additional transistors if determined appropriate upon calculation of Equation 1) have a low input voltage at input  204  (i.e. 0V), the voltage divider circuit  200   a  pulls the output  206  to a level of VDD 2   212 . On the other side of the circuit, the output of the inverter  330  is input into the voltage divider circuit of  FIG. 2   b    200   b  at input  205 . When the gates of n-MOS transistors  209  and  211  have an input voltage of VDD at input  205 , the voltage divider circuit  200   b  pulls the output  206  to a level of the common potential  213  (i.e. 0V). And, like the voltage divider of  FIG. 2   b , additional n-MOS transistors can be added if necessary.  
         [0022]     As mentioned above, the resultant output of the voltage divider circuits of  FIG. 2   a  and  FIG. 2   b  contribute to the resultant translation by using the respective outputs of the level shift inverter  320  as well as the inverter  330  to pull output  206  to either 0V or VDD 2 . Because of this, a voltage drop of approximately VDD 2  will always exist across either the series p-MOS transistors of the divider circuit of  FIG. 2   a  or the series n-MOS transistors of the divider circuit of  FIG. 2   b . However, each MOS transistor in the voltage divider circuits  200  and  200   b  will not be exposed to higher than operating voltages because the voltage is effectively distributed across all the transistors in each voltage divider circuit.  
         [0023]      FIG. 4  is a schematic drawing of an output voltage driver circuit  400  comprising two divider circuits  200   a  and  200   b , an inverter  330 , as well as a level shift inverter  420 . This circuit is similar and operates in a matter analogous to that of  FIG. 3   a . The input  301  is connected to the inverter  330  and the level shift inverter  420 . The output of the inverter  330  is connected to the input node  205  of circuit  200   b  and the output of the level shift inverter  420  is connected to the input node  204  of circuit  200   a  and the output is taken at node  206  of both divider circuits  200   a  and  200   b.    
         [0024]     In this embodiment, however, the level shift inverter  420  is comprised of both p-MOS and n-MOS series stacked transistors. Essentially, the level shift inverter  420  employs the same circuit of  FIG. 2   a    200   a  and  FIG. 2   b    200   b  to minimize higher than rated voltages across any given transistor. Again, these stacked p-MOS and n-MOS transistors may contain more than two transistors ( 416  and  417  respectively) depending on the minimum and maximum operating voltage of the output voltage driver circuit  400 . By distributing the VDD 2  voltage across the series of p-MOS and n-MOS stacked transistors within the level shift inverter  420 , higher than rated voltages are prevented from being applied across a single MOS transistor.  
         [0025]     This particular embodiment employs a driver circuit  440 , in order to force the output voltage  205  to a low value (0V) or a high value (VDD 2 ). It should be understood, however, that this circuit is not essential and the gates of the n-MOS transistors at node  405  could be tied to the gates of the p-MOS transistors at node  404 . For a circuit designer, it may also be advantageous to use the inverse voltage value of node  206 . This can be realized by referencing the voltage at output node  450 . Once more, this circuit can also be designed with multiple n-MOS transistors  418 .  
         [0026]     An embodiment of the present invention has been described above. Those skilled in the art will understand, however, that changes and modifications may be made to this embodiment without departing from the true scope and spirit of the present invention, which is defined by the claims.