Abstract:
A circuit for generating a reference electrical quantity, including: a first bipolar transistor and a second bipolar transistor having the base terminals connected to one another and to a common node; a first resistor connected to the emitter terminal of the second bipolar transistor; a first mirror circuit and a second mirror circuit connected to the first and second bipolar transistors, which receive, respectively, a first current and a second current and generate, respectively, a first mirrored current and a second mirrored current; a first output stage, which generates the reference electrical quantity as a function of the first and second mirrored currents; and a second resistor connected to the common node. The first current is a function of the current in the first resistor, whilst the second current is a function of the current in the second resistor.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the priority benefit of Italian patent application number TO2009A000977, filed on Dec. 11, 2009, entitled “Circuit for Generating a Reference Electrical Quantity,” which is hereby incorporated by reference to the maximum extent allowable by law. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a circuit for generating a reference electrical quantity. 
         [0004]    2. Discussion of the Related Art 
         [0005]    As is known, the majority of electronic devices requires a respective current source, which should be able to supply a reference current as constant as possible in regard to the temperature shifts and to variations in the supply voltage of the electronic devices themselves. In fact, the more the reference current supplied by a current source is stable, the more the overall performance of the electronic device that uses said reference current is stable. 
         [0006]    Likewise, it should be noted that numerous electronic devices necessitate a reference voltage, which must also be as constant as possible in regard to temperature shifts and to variations in the supply voltage. For this purpose, various types of reference-voltage sources are known, such as for instance the so-called “bandgap circuits”, which are able to deliver a reference voltage generally close to 1.22 V. 
         [0007]    In particular, circuits are known that, in order to reduce the dependence upon temperature, generate a reference current and/or a reference voltage on the basis of a current I PTAT  and a current I NTAT . In detail, the current I PTAT  is generated so as to be directly proportional to the temperature with a positive temperature coefficient, whereas the current I NTAT  is generated so as to be proportional to the temperature, but with a negative temperature coefficient. 
         [0008]    By way of example,  FIG. 1  shows a voltage and current generator circuit  1 , which enables generation of both the reference current and the reference voltage. Said voltage and current generator circuit  1  comprises a first self-biasing circuit  2  and a second self-biasing circuit  4  and moreover comprises a voltage output stage  6  and a current output stage  8 . The first self-biasing circuit  2  and the second self-biasing circuit  4 , as likewise the voltage output stage  6  and the current output stage  8 , are connected between a supply terminal N DD , which can be appropriately connected to a supply voltage V DD , and ground. 
         [0009]    In greater detail, the first self-biasing circuit  2  comprises a first biasing transistor T 1  and a second biasing transistor T 2 , of a P-channel MOS type, which are connected to form a first current mirror. In particular, the source terminals of the first and second biasing transistors T 1 , T 2  are connected to the supply terminal N DD , whilst the gate terminals of the first and second biasing transistors T 1 , T 2  are connected to one another; moreover, the second biasing transistor T 2  is diode-connected; i.e., it has its drain terminal connected to its gate terminal. In what follows, to indicate the gate terminals of the first and second biasing transistors T 1 , T 2  reference is made to the node N PTAT . 
         [0010]    The first self-biasing circuit  2  further comprises a first resistor R A  and a first bipolar transistor T bjt1  and a second bipolar transistor T bjt2 . 
         [0011]    In particular, in the example shown in  FIG. 1 , the first and second bipolar transistors T bjt1 , T bjt2  are of an npn type. The collector terminals of the first and second bipolar transistors T bjt1 , T bjt2  are connected, respectively, to the drain terminals of the first and second biasing transistors T 1 , T 2 . In addition, the base terminals of the first and second bipolar transistors T bjt1 , T bjt2  are connected to one another, and the first bipolar transistor T bjt1  is diode-connected; i.e., it has its respective base terminal connected to its respective collector terminal. Again, the emitter terminal of the first bipolar transistor T bjt1  is connected to ground, whilst the emitter terminal of the second bipolar transistor T bjt2  is connected to the first resistor R A , which is moreover connected to ground. 
         [0012]    The second self-biasing circuit  4  comprises a third biasing transistor T 3  and a fourth biasing transistor T 4  of a P-channel MOS type, which are connected to form a second current mirror. In particular, the source terminals of the third and fourth biasing transistors T 3 , T 4  are connected to the supply terminal N DD , whilst the gate terminals of the third and fourth biasing transistors T 3 , T 4  are connected to one another; moreover, the fourth biasing transistor T 4  is diode-connected. In what follows, to indicate the gate terminals of the third and fourth biasing transistors T 3 , T 4  reference is made to the node N NTAT . 
         [0013]    The second self-biasing circuit  4  further comprises a second resistor R B , a third bipolar transistor T bjt3 , and a fifth biasing transistor T 5 . In particular, the fifth biasing transistor T 5  is of an N-channel MOS type; moreover, in the example shown in  FIG. 1 , the third bipolar transistor T bjt3  is of an npn type. 
         [0014]    The drain terminal of the fifth biasing transistor T 5  is connected to the drain terminal (and hence also to the gate terminal) of the fourth biasing transistor T 4 . Instead, the gate terminal and the source terminal of the fifth biasing transistor T 5  are connected, respectively, to the drain terminal of the third biasing transistor T 3  and to the base terminal of the third bipolar transistor T bjt3 . 
         [0015]    In addition, the collector terminal of the third bipolar transistor T bjt3  is connected to the drain terminal of the third biasing transistor T 3  and hence also to the gate terminal of the fifth biasing transistor T 5 , whilst the emitter terminal of the third bipolar transistor T bjt3  is connected to ground. Finally, the second resistor R B  is connected between ground and the base terminal of the third bipolar transistor T bjt3 . 
         [0016]    The voltage output stage  6  comprises an output resistor R OUT  and a first sum transistor T s1  and a second sum transistor T s2 , both of a P-channel MOS type. The source terminals of said first and second sum transistors T s1 , T s2  are connected to the supply terminal N DD , whilst the gate terminals are connected, respectively, to the node N NTAT  and to the node N NTAT , and the drain terminals are connected to one another; consequently, the first and second sum transistors T s1 , T s2  concur to form, respectively, the aforementioned first and second current mirrors. The output resistor R OUT  is instead connected between ground and the drain terminals of the first and second sum transistors T s1 , T s2 . 
         [0017]    The current output stage  8  comprises a third sum transistor T s3  and a fourth sum transistor T s4 , both of a P-channel MOS type. The source terminals of said third and fourth sum transistors T s3 , T s4  are connected to the supply terminal N DD , whilst the gate terminals are connected, respectively, to the node N PTAT  and to the node N NTAT , and the drain terminals are connected to one another and define an output node N OUT . Consequently, the third and fourth sum transistors T s3 , T s4  concur to form, respectively, the aforementioned first and second current mirrors. 
         [0018]    In greater detail, the first, second, third and fourth biasing transistors T 1 -T 4  are the same (but for the inevitable tolerances) and hence are characterized by one and the same aspect ratio W/L, which as is known indicates, given a generic MOS transistor, the ratio between the width and the length of the corresponding channel. Instead, the first, second, third, and fourth sum transistors T s1 -T s4  are such that the aspect ratios are, respectively, γ·W/L, α·W/L, δ·W/L, and ε·W/L, where α, ε, γ, δ are mirror ratios, described hereinafter. 
         [0019]    Operatively, it may be shown that, when the supply voltage V DD  is present on the supply terminal N DD , in the collector terminal of the second bipolar transistor T bjt2  there circulates a current I C2 , which is equal to the current that circulates in the first biasing transistor T 1 . Said current I C2  is hence equal to the sum of the currents I C1 , I B1  and I B2 , which are the currents that circulate, respectively, in the collector terminal of the first bipolar transistor T bjt1 , in the base terminal of the first bipolar transistor T bjt1 , and in the base terminal of the second bipolar transistor T bjt2 . Said current I C2  functions as current I PTAT , which is substantially independent of the supply voltage V DD . In fact, assuming that the first and second bipolar transistors T bjt1 , T bjt2  have respective parameters  13  high, and hence assuming that the currents I B1  and I B2  are negligible as compared to the current I PTAT  itself, the current I PTAT  is equal to the current that flows in the emitter terminal of the second bipolar transistor T bjt2 . Consequently, we have 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     PTAT 
                   
                   = 
                   
                     
                       
                         
                           V 
                           
                             be 
                              
                             
                                 
                             
                              
                             1 
                           
                         
                         - 
                         
                           V 
                           
                             be 
                              
                             
                                 
                             
                              
                             2 
                           
                         
                       
                       
                         R 
                         rA 
                       
                     
                     = 
                     
                       
                         1 
                         
                           R 
                           rA 
                         
                       
                       · 
                       
                         kT 
                         q 
                       
                       · 
                       
                         ln 
                          
                         
                           ( 
                           
                             
                               A 
                               2 
                             
                             
                               A 
                               1 
                             
                           
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0020]    where R rA  is the resistance of the first resistor R A , V be1  is the voltage present between the base terminal and the emitter terminal of the first bipolar transistor T bjt1 , V be2  is the voltage present between the base terminal and the emitter terminal of the second bipolar transistor T bjt2 , q is the charge of the electron, k is the Boltzmann constant, T is the temperature expressed in Kelvin, and A 1  and A 2  are, respectively, the areas of the base-emitter junctions of the first and second bipolar transistors T bjt1 , T bjt2 , which are referred to for reasons of brevity also as the areas of the first and second bipolar transistors T bjt1 , T bjt2 , and for which the relation A 2 &gt;A 1  applies. 
         [0021]    A voltage V be3 , i.e., a voltage equal to the base-emitter voltage of the third bipolar transistor T bjt3 , is set up across the second resistor R B . Said voltage V be3  is imposed on the second resistor R B  by the feedback loop defined by the third bipolar transistor T bjt3  and by the fifth biasing transistor T 5 . In this way, the voltage across the second resistor R B  is substantially independent of the voltage V GS  present between the gate terminals and source terminals of the third and fourth biasing transistors T 3 , T 4 . Consequently, the voltage across the second resistor R B  is substantially independent of the supply voltage V DD . In addition, it may be shown that in the fourth and fifth biasing transistors T 4 , T 5  there circulates a current that functions as current I NTAT , which is substantially independent of the supply voltage V DD . In fact, assuming that the third bipolar transistor T bjt3  has a parameter  13  high, and hence that the current I B3  circulating in the base terminal of the third bipolar transistor T bjt3  is negligible as compared to the current I NTAT , the current I NTAT  is given by the equation 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     NTAT 
                   
                   = 
                   
                     
                       V 
                       
                         be 
                          
                         
                             
                         
                          
                         3 
                       
                     
                     
                       R 
                       rB 
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0022]    where R rB  is the value of resistance of the second resistor R B . 
         [0023]    The currents I PTAT  and I NTAT  are then added up inside the voltage output stage  6  and the current output stage  8 , respectively, with the mirror ratios γ and α, and δ and ε. 
         [0024]    It follows that, on the output resistor R OUT  of the voltage output stage  6 , there is a reference voltage V REF    
         [0000]        V   REF =(α I   NTAT   +γI   PTAT )· R   rOUT   (3)
 
         [0025]    where R rOUT  is the resistance of the output resistor R OUT . 
         [0026]    Likewise, by connecting a hypothetical load to the output node N OUT , the current output stage  8  supplies, on said hypothetical load, a reference current I REF  of 
         [0000]        I   REF   =εI   NTAT   +δI   PTAT   (4)
 
         [0027]    As mentioned previously, the temperature coefficients of the currents I PTAT  and I NTAT  are, respectively, positive and negative, as emerges from Eqs. (1) and (2). In fact, the current I PTAT  is directly proportional to the temperature T because the difference V be1 −V be2  is in turn directly proportional to the temperature T, given that the relation A 2 &gt;A 1  applies. Instead, the behaviour of the current I NTAT  with respect to the temperature T is determined by the voltage V be3 , which, as is known, varies with the temperature with a coefficient of approximately −2 mV/°K. 
         [0028]    It follows that, on the basis of Eqs. (3) and (4), it is possible to determine appropriate values of the mirror ratios α, ε, γ, δ such that the reference voltage V REF  and the reference current I REF  are, to a first approximation, constant with respect to the temperature T. 
         [0029]    In order to enable optimal operation of the voltage and current generator circuit  1 , and, in particular, in order to enable the operation described previously, recourse is usually had to a first start-up circuit and a second start-up circuit (which are not shown), connected, respectively, to the first self-biasing circuit  2  and the second self-biasing circuit  4 . In particular, the first and second start-up circuits perform the function of biasing the first self-biasing circuit  2  and the second self-biasing circuit  4  in respective points of equilibrium such that Eqs. (1) and (2), and hence also Eqs. (3) and (4), yield non-zero results. 
         [0030]    In greater detail, it may be shown that the first and second self-biasing circuits  2 ,  4  each have a pair of possible points of equilibrium. In particular, the first self-biasing circuit  2  has a respective useful point of equilibrium where the difference V be1 −V be2  is non-zero, and a respective zero point of equilibrium where the difference V be1 −V be2  is zero. Likewise, the second self-biasing circuit  4  has a respective useful point of equilibrium where the voltage V be3  is non-zero, and a respective zero point of equilibrium where the voltage V be3  is zero. 
         [0031]    Assuming connection of the supply terminal N DD  to the supply voltage V DD  at an instant t 0 , and assuming that for t&lt;t 0  the voltage and current generator circuit  1  has not been supplied, the first and second self-biasing circuits  2 ,  4  are biased, in the absence of start-up circuits, in the respective useful point of equilibrium or else in the respective zero point of equilibrium, in a way that is in itself not predictable. The function of the first and second start-up circuits is precisely that of enabling, subsequent to the instant t 0 , biasing of the first and second self-biasing circuits  2 ,  4  in the respective useful points of equilibrium. This done, the first and second start-up circuits turn off, without any longer interfering with operation of the voltage and current generator circuit  1 . 
         [0032]    Examples of start-up circuits are shown and described in “Low power startup circuits for voltage and current reference with zero steady state current”, International Symposium on Low Power Electronics and Design 2003, Aug. 25-27, Seoul, Korea. However, there is no further description of any start-up circuit herein in so far as the present invention is irrespective of the details of implementation of the start-up circuits themselves. 
         [0033]    Thanks to the use described of the currents I PTAT  and I NTAT , the voltage and current generator circuit  1  enables electrical quantities to be obtained that have a high stability in regard to temperature shifts. However, since the voltage and current generator circuit  1  comprises two self-biasing circuits, it entails the use of two start-up circuits and hence is characterized by a high circuit complexity, a considerable current consumption, and a considerable occupation of area. In particular, the latter characteristic is due not only to the presence of the third bipolar transistor T bjt3  but also to the presence of the third and fourth biasing transistors T 3 , T 4 , which usually have a large area in order to enable better mirroring the current I NTAT . In addition, the presence of two self-biasing circuits causes the voltage and current generator circuit  1  to be sensitive to the inevitable tolerances introduced by technological processes that enable formation of the first and second self-biasing circuits. Consequently, the performance of the voltage and current generator circuit  1  can be inferior to what may be theoretically expected on account of process asymmetries in the formation of components belonging to different self-biasing circuits, such as, for example, the first and third bipolar transistors T bjt1 , T bjt3 . 
       SUMMARY OF THE INVENTION 
       [0034]    An aim of the present invention is to provide a circuit for generating a reference electrical quantity that will enable at least partial solution of the drawbacks of the known art. 
         [0035]    According to at least one embodiment, there is provided a circuit for generating a reference electrical quantity, comprising a first bipolar transistor and a second bipolar transistor, the emitter terminal of the first bipolar transistor being connected to a first line at reference potential, the base terminals of the first and second bipolar transistors being connected to one another and to a common node a first resistor, connected between the emitter terminal of the second bipolar transistor and the first line at reference potential a first mirror circui, connected between a second line at reference potential and the first and second bipolar transistors and configured for receiving a first current which is a function of the current in the first resistor, and generating a first mirrored current a second mirror circuit, configured for receiving a second current and generating a second mirrored current and a first output stage, configured for generating the reference electrical quantity as a function of said first and second mirrored currents, and a second resistor connected between the first line at reference potential and the common node, said second current being a function of the current in the second resistor. 
         [0036]    According to another embodiment, the generator circuit further comprises a follower transistor of a MOS type, having a gate terminal connected to the collector terminal of the first bipolar transistor, and a first conduction terminal connected to the common node. 
         [0037]    According to another embodiment, said first mirror circuit comprises a first biasing transistor and a second biasing transistor having respective control terminals connected to one another, said first biasing transistor moreover having a first conduction terminal and a second conduction terminal, connected, respectively, to the second line at reference potential and to the collector terminal of said first bipolar transistor, said second biasing transistor moreover having a first conduction terminal and a second conduction terminal, connected, respectively, to the second line at reference potential and to the collector terminal of said second bipolar transistor, said second biasing transistor being diode-connected, the second bipolar transistor being configured so as to supply the first current through its own collector terminal. 
         [0038]    According to another embodiment, said second mirror circuit comprises a diode-connected mirror transistor having a first conduction terminal and a second conduction terminal, respectively connected to the second line at reference potential and to a second conduction terminal of the follower transistor, the follower transistor being configured so as to supply the second current through its own second conduction terminal. 
         [0039]    According to another embodiment, said first mirror circuit further comprises a first sum transistor having a control terminal and a first conduction terminal and a second conduction terminal, respectively connected to the control terminal of said second biasing transistor, to the second line at reference potential and to an output resistor, and said second mirror circuit further comprises a second sum transistor having a control terminal and a first conduction terminal and a second conduction terminal, respectively connected to the control terminal of said mirror transistor, to the second line at reference potential, and to said output resistor, in such a way that, in use, said first and second mirrored currents flow, respectively, through said first and second sum transistors. 
         [0040]    According to another embodiment, said second biasing transistor and said first sum transistor have respective dimensions such as to define a first mirror ratio, and wherein said mirror transistor and said second sum transistor have respective dimensions such as to define a second mirror ratio. 
         [0041]    According to another embodiment, said first and second bipolar transistors have, respectively, a first area and a second area, said first and second resistors having, respectively, a first resistance and a second resistance, said first and second resistances, said first and second areas, and said first and second mirror ratios being such as to reduce possible variations of a voltage present on said output resistor due to variations of said first and second currents caused by temperature shifts. 
         [0042]    According to another embodiment, said first mirror circuit further comprises a third sum transistor having a control terminal and a first conduction terminal and a second conduction terminal, respectively connected to the control terminal of said second biasing transistor, to the second line at reference potential, and to an output node, and said second mirror circuit further comprises a fourth sum transistor having a control terminal and a first conduction terminal and a second conduction terminal, respectively connected to the control terminal of said mirror transistor, to the second line at reference potential, and to said output node, in such a way that, in use, a third mirrored current and a fourth mirrored current flow, respectively, through said third and fourth sum transistors. 
         [0043]    According to another embodiment, said second biasing transistor and said third sum transistor have respective dimensions such as to define a third mirror ratio, and wherein said mirror transistor and said fourth sum transistor have respective dimensions such as to define a fourth mirror ratio. 
         [0044]    According to another embodiment, said first and second resistances, said first and second areas, and said third and fourth mirror ratios are such as to reduce possible variations of a current supplied to said output node due to variations of said first and second currents caused by temperature shifts. 
         [0045]    According to another embodiment, the generator circuit further comprises at least one from among: a first additional transistor connected in series to said first biasing transistor, a second additional transistor connected in series to said first sum transistor, a third additional transistor connected in series to said second sum transistor, a fourth additional transistor connected in series to said third sum transistor, and a fifth additional transistor connected in series to said fourth sum transistor. 
         [0046]    According to another embodiment, said second area is greater than said first area. 
         [0047]    According to another embodiment, said first mirror circuit further comprises a third sum transistor having a control terminal and a first conduction terminal and a second conduction terminal, respectively connected to the control terminal of said second biasing transistor, to the second line at reference potential and to an output node, and said second mirror circuit further comprises a fourth sum transistor having a control terminal and a first conduction terminal and a second conduction terminal, connected, respectively, to the control terminal of said mirror transistor, to the second line at reference potential, and to said output node in such a way that, in use, a first mirrored current and a second mirrored current flow, respectively, through said third and fourth sum transistors. 
         [0048]    According to another embodiment, there is provided a method for generating a reference electrical quantity, comprising the steps of providing a first bipolar transistor and a second bipolar transistor receiving a first current and generating a first mirrored current, said first current being a function of the current in a first resistor, connected to the emitter terminal of the second bipolar transistor and to a first line at reference potential, the emitter terminal of the first bipolar transistor being connected to the first line at reference potential, the base terminals of the first and second bipolar transistors being connected to one another and to a common node receiving a second current and generating a second mirrored current and generating the reference electrical quantity as a function of said first and second mirrored currents wherein said step of receiving a second current comprises receiving the current in a second resistor connected between the first line at reference potential and the common node. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0049]    For a better understanding of the invention, embodiments thereof are now described, purely by way of non-limiting example and with reference to the attached drawings, wherein: 
           [0050]      FIG. 1  shows a circuit diagram of a circuit for generating a reference current and a reference voltage according to the known art; and 
           [0051]      FIGS. 2 and 3  show circuit diagrams of embodiments of the present circuit for generating a reference electrical quantity. 
           [0052]      FIG. 2  shows a circuit for generating a reference electrical quantity, designated as a whole by  10 , and referred to hereinafter, for reasons of brevity, as the source circuit  10 . 
       
    
    
     DETAILED DESCRIPTION 
       [0053]    The source circuit  10  is described in what follows, the present description being limited to the differences alone of the source circuit  10  with respect to the voltage and current generator circuit  1  illustrated in  FIG. 1 . In addition, components of the source circuit  10  that are already present in the voltage and current generator circuit  1  are designated in the same way, except where otherwise specified. 
         [0054]    In detail, the source circuit  10  comprises the first self-biasing circuit, here designated by  12 , but does not have the second self-biasing circuit  4 . In addition, the source circuit  10  comprises at least one between the voltage output stage  6  and the current output stage  8 ; in this connection, described by way of example in what follows is one embodiment, present in which are both the voltage output stage  6  and the current output stage  8 . 
         [0055]    In greater detail, the first self-biasing circuit  12  comprises the first and second resistors R A , R B , the first and second biasing transistors T 1 , T 2 , and the first and second bipolar transistors T bjt1 , T bjt2 . In addition, the first self-biasing circuit  12  comprises a mirror transistor T m  and a follower transistor T f . 
         [0056]    In detail, the second resistor R B  is connected between ground and the base terminals of the first and second bipolar transistors T bjt1 , T bjt2 , which define a common node N C . 
         [0057]    The mirror transistor T m  is a P-channel MOS transistor. In particular, the source terminal of the mirror transistor T m  is connected to the supply terminal N DD , whilst the gate terminal defines the node N NTAT , and hence is connected to the gate terminals of the second and fourth sum transistors T s2 , T s4 . In addition, the mirror transistor T m  is diode-connected; i.e., its drain terminal is connected to its gate terminal. 
         [0058]    The follower transistor T f  is an N-channel MOS transistor. In particular, the drain terminal of the follower transistor T f  is connected to the drain terminal (and hence also to the gate terminal) of the mirror transistor T m . The gate terminal of the follower transistor T f  is connected to the drain terminal of the first biasing transistor T 1 , and hence also to the collector terminal of the first bipolar transistor T bjt1 . The source terminal of the follower transistor T f  is instead connected to the common node N C , and hence to the base terminals of the first and second bipolar transistors T bjt1 , T bjt2 , and to the second resistor R B . 
         [0059]    As regards the resistances R rA , R rB , R rouT  of the first and second resistors R A , R B  and of the output resistor R OUT , the following relations apply: 
         [0000]        R   rB   =n·R   A   , R   rOUT   =m·R   rA   (5)
 
         [0060]    with n and m not necessarily integers. 
         [0061]    Operatively, the current that flows in the follower transistor T f  functions as current I NTAT , which is mirrored by the mirror transistor T m  and by the second and fourth sum transistors T s2 , T s4 . In practice, the mirror transistor T m  functions as reading branch of the second current mirror, performing the function that in the voltage and current generator circuit  1  was performed by the fourth biasing transistor T 4 . 
         [0062]    In addition, the follower transistor T f  functions as source follower since the voltage on its own gate terminal follows the voltage on its own source terminal; consequently, in the small-signal regime, the first bipolar transistor T bjt1  is diode-connected. In other words, the follower transistor T f  enables current uncoupling of the base terminals of the first and second bipolar transistors T bjt1 , T bjt2  from the current that flows in the first biasing transistor T 1 . Again, in other words, thanks to the presence of the follower transistor T f , as well as of the first and second biasing transistors T 1 , T 2 , the currents I C1  and I C2  that flow in the collector terminals of the first and second bipolar transistors T bjt1  T bjt2  are the same, notwithstanding the fact that the second resistor R B  is connected to the base terminals of the first and second bipolar transistors T bjt1 , T bjt2  themselves. In fact, the current I NTAT  that flows in the follower transistor T f  is equal to the sum of the currents I RB , I B1 , I B2  that flow in the second resistor R B  and in the base terminals of the first and second bipolar transistors T bjt1 , T bjt2 , respectively. 
         [0063]    On the basis of what has been described, it follows that once again Eq. (1) applies, and moreover, assuming that the currents I B1 , I B2  are negligible as compared to the current I RB , the current I NTAT  is equal to the current I RB . 
         [0064]    Consequently, the following equation applies: 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     NTAT 
                   
                   = 
                   
                     
                       
                         V 
                         
                           be 
                            
                           
                               
                           
                            
                           1 
                         
                       
                       
                         R 
                         rB 
                       
                     
                     = 
                     
                       
                         V 
                         
                           be 
                            
                           
                               
                           
                            
                           1 
                         
                       
                       
                         n 
                         · 
                         
                           R 
                           rA 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
         [0065]    In particular, the resistance R rB  can be sized in such a way that the currents I B1 , I B2  are negligible as compared to the current I RB  also in the case where the first and second bipolar transistors T bjt1 , T bjt2  have parameters  13  that are not particularly high. 
         [0066]    On the basis of Eqs. (1) and (6), we moreover have 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
                           V 
                           REF 
                         
                         = 
                           
                          
                         
                           
                             ( 
                             
                               
                                 α 
                                  
                                 
                                     
                                 
                                  
                                 
                                   I 
                                   NTAT 
                                 
                               
                               + 
                               
                                 γ 
                                  
                                 
                                     
                                 
                                  
                                 
                                   I 
                                   PTAT 
                                 
                               
                             
                             ) 
                           
                           · 
                           
                             R 
                             rOUT 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           m 
                           · 
                           
                             ( 
                             
                               
                                 
                                   α 
                                   n 
                                 
                                 · 
                                 
                                   V 
                                   
                                     be 
                                      
                                     
                                         
                                     
                                      
                                     1 
                                   
                                 
                               
                               + 
                               
                                 γ 
                                 · 
                                 
                                   kT 
                                   q 
                                 
                                 · 
                                 
                                   ln 
                                    
                                   
                                     ( 
                                     
                                       
                                         A 
                                         2 
                                       
                                       
                                         A 
                                         1 
                                       
                                     
                                     ) 
                                   
                                 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       
                         
                           I 
                           REF 
                         
                         = 
                           
                          
                         
                           
                             ɛ 
                              
                             
                                 
                             
                              
                             
                               I 
                               NTAT 
                             
                           
                           + 
                           
                             δ 
                              
                             
                                 
                             
                              
                             
                               I 
                               PTAT 
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                          
                         
                           
                             1 
                             
                               R 
                               rA 
                             
                           
                           · 
                           
                             ( 
                             
                               
                                 
                                   ɛ 
                                   n 
                                 
                                 · 
                                 
                                   V 
                                   
                                     be 
                                      
                                     
                                         
                                     
                                      
                                     1 
                                   
                                 
                               
                               + 
                               
                                 δ 
                                 · 
                                 
                                   kT 
                                   q 
                                 
                                 · 
                                 
                                   ln 
                                    
                                   
                                     ( 
                                     
                                       
                                         A 
                                         2 
                                       
                                       
                                         A 
                                         1 
                                       
                                     
                                     ) 
                                   
                                 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
         [0067]    In practice, the reference voltage V REF  and the reference current I REF  depend upon the temperature T both because the temperature T itself appears explicitly in Eqs. (7) and (8) and because, as is known, the voltage V be1  varies with the temperature with a coefficient of approximately −2 mV/K. In practice, it is possible to size the source circuit  10  in such a way that the reference voltage V REF  and the reference current I REF  are constant with respect to possible temperature shifts; i.e., they have a zero temperature coefficient. For this purpose, the degrees of freedom represented by the mirror ratios α, ε, γ, δ, as well as by the coefficient n and by the areas A 1  and A 2  of the first and second bipolar transistors T bjt1 , T bjt2  are available. For example, it is possible to size appropriately the coefficient n, the mirror ratios α and γ, and the areas A 1  and A 2  of the first and second bipolar transistors T bjt1 , T bjt2  in such a way as to annul the temperature coefficient of the reference voltage V REF . Next, it is possible to size the mirror ratios ε and δ appropriately in such a way as to annul the temperature coefficient of the reference current I REF . 
         [0068]    As regards, in particular, the reference voltage V REF , it does not depend upon the absolute value of resistance of any resistor of the source circuit  10 , but rather depends upon the ratios between resistance values; consequently, it does not call for operations of calibration, nor is it affected by possible variations occurring during the technological processes of formation of the source circuit  10 . In addition, the reference voltage V REF  can be established as desired by appropriately choosing the coefficient m irrespective of the choice of the mirror ratios α, ε, γ, δ, of the coefficient n and of the areas A 1 , A 2 . In particular, the reference voltage V REF  can assume an arbitrary value comprised between ground and V DD −|V DSx |, where: 
         [0069]    −V DD &gt;V be1 +|V DS1 |+|V GSth |, where V DS1  is a (negative) voltage between the drain and source terminals of the first biasing transistor T 1  such as to keep in saturation the first biasing transistor T 1 , whilst V GSth  is a threshold voltage of the follower transistor T f ; and 
         [0070]    −V DSX  is a (negative) voltage between the drain and source terminals of the first and second sum transistors T s1 , T s2  such as to keep said first and second sum transistors T s1 , T s2  in saturation. 
         [0071]    As regards, instead, the reference current I REF , this depends upon the absolute value of the resistance R rA , which may depend upon the temperature. However, it is possible to determine the values of the mirror ratios ε, δ and the value of the coefficient n so as to compensate for the dependence upon the temperature of the resistance R rA . In addition, to eliminate the dependence of the reference current I REF  upon possible tolerances on the absolute value of the resistance R rA , and in particular upon a deviation between the nominal value and the effective value of the resistance R rA , it is possible to determine the values of the mirror ratios ε and δ, and the value of the coefficient n as a function of said tolerances, after prior measurement of the effective value of the resistance R rA . 
         [0072]    It should be moreover noted that, even though the possibility has been described of determining the mirror ratios α, ε, γ, δ and the coefficient n in such a way that the reference voltage V REF  and the reference current I REF  will have a zero temperature coefficient, it is likewise possible to determine the mirror ratios α, ε, γ, δ and the coefficient n in such a way that the reference voltage V REF  and the reference current I REF  have respective arbitrary temperature coefficients. In other words, it is possible to size the source circuit  10  in such a way that the reference voltage V REF  and the reference current I REF  have a desired dependence upon temperature. 
         [0073]    Purely by way of example, it is possible to assume A 2 /A 1 =2, n=m=1, R rA =10 kΩ, α=ε=1, γ=δ=33.4. 
         [0074]    As illustrated in  FIG. 3 , it is moreover possible to insert one or more additional transistors. Said additional transistors can be of a P-channel MOS type and have the respective gate terminals connected to an additional N+ terminal, which is in turn biased at a cascode voltage V+ by means of an appropriate additional biasing circuit (not shown). 
         [0075]    For example, it is possible to insert a first additional transistor T 1+  between the first biasing transistor T 1  and the first bipolar transistor T bjt1 . Said first additional transistor has its source and drain terminals connected, respectively, to the drain terminal of the first biasing transistor T 1  and to the collector terminal of the first bipolar transistor T bjt1 . 
         [0076]    The presence of the first additional transistor T 1+  enables optimization of the performance of the first current mirror, and hence of the first and second biasing transistors T 1 , T 2 . In fact, designating by V DS2  the voltage between the drain and source terminals of the second biasing transistor T 2 , in a way in itself known it is possible to design the additional biasing circuit in such a way that the cascode voltage V+ is a function of the supply voltage V DD . In particular, the cascode voltage V+ can be a function of the supply voltage V DD  according to a law such that the voltages V DS1 , V DS2  are the same, or at least have an equal dependence upon the supply voltage V DD . In this way, the first current mirror is of a cascode type and hence has improved behavior with respect to variations in the supply voltage V DD . 
         [0077]    In a similar way, a second additional transistor T 2+  and a third additional transistor T 3+  can be inserted between the output resistor R OUT  and, respectively, the first and second sum transistors T s1 , T s2 . Again, a fourth additional transistor T 4+  and a fifth additional transistor T 5+  can be inserted between the output node N OUT  and, respectively, the third and fourth sum transistors T s3 , T s4 . In practice, the second, third, fourth, and fifth additional transistors T 2+ -T 5+  are arranged in series with the first, second, third, and fourth sum transistors T s1 -T s4 , respectively. 
         [0078]    The advantages that the source circuit  10  affords emerge clearly from the foregoing discussion. In particular, the source circuit  10  enables the reference voltage V REF  and/or the reference current I REF  to be obtained by using just one self-biasing circuit, with evident advantages in terms of reduction of current consumption, reduction of circuit complexity, and higher integrability. The latter advantage is due to the reduction of the area occupied, obtained precisely by means of elimination of the second self-biasing circuit  4 . In addition, the presence of just one self-biasing circuit involves the use of just one start-up circuit. In this connection, the source circuit  10  can be connected to a start-up circuit of a known type. 
         [0079]    As further advantage, the reference voltage V REF  supplied by the source circuit  10  does not depend upon the absolute value of resistance of any resistor of the source circuit  10 , and can moreover be established as desired by an appropriate choice of the coefficient m, irrespective of the choice of the mirror ratios α, ε, γ, δ and of the coefficient n. 
         [0080]    Finally, it is evident that modifications and variations may be made to the source circuit  10  described and illustrated herein, without thereby departing from the sphere of protection of the present invention, as defined in the annexed claims. 
         [0081]    For example, instead of the output resistor R OUT  it is possible to use a resistive divider, i.e., a plurality of resistors connected in series, in order to generate a plurality of different reference voltages. 
         [0082]    In addition, instead of the first and second biasing transistors T 1 , T 2 , and of the first and third sum transistors T s1 , T s3 , it is possible to use different circuits, provided that they enable mirroring of the current I PTAT . Likewise, instead of the mirror transistor T m  and the second and fourth sum transistors T s2 , T s4 , it is possible to use different circuits, provided that they enable mirroring of the current I NTAT . 
         [0083]    Finally, the first and second biasing transistors T 1 , T 2 , as well as the first, second, third, and fourth sum transistors T s1 -T s4  can be of a type different from what has been described and illustrated. 
         [0084]    Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.