Abstract:
A semiconductor memory device includes a path control unit configured to activate an address transmission path corresponding to a bank address, an address providing unit configured to provide a memory address to the path control unit in response to an active signal, and a plurality of memory banks each configured to receive the memory address provided through the corresponding address transmission path of the path control unit, wherein the bank address corresponds to a memory bank of the plurality of memory banks.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application claims priority of Korean Patent Application No. 10-2011-0110468, filed on Oct. 27, 2011, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Field 
         [0003]    Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device for performing a data access operation by receiving an address. 
         [0004]    2. Description of the Related Art 
         [0005]    In general, a semiconductor memory device such as a double data rate synchronous DRAM (DDR SDRAM) performs a data access operation by receiving an address and data, which are inputted from an external controller. More specifically, the semiconductor memory device stores data in a memory cell corresponding to an address in a write operation, and the semiconductor memory device outputs the data stored in the memory cell corresponding to the address in a read operation. 
         [0006]      FIG. 1  is a block diagram illustrating a related art semiconductor memory device. 
         [0007]    Referring to  FIG. 1 , the semiconductor memory device includes a delay unit  100 , an address providing unit  110 , a bank address decoding unit  120 , first to fourth address latching units  130 _ 1 ,  130 _ 2 ,  130 _ 3 , and  130 _ 4 , and first to fourth memory banks  140 _ 1 ,  140 _ 2 ,  140 _ 3 , and  140 _ 4 . The delay unit  100  delays an active signal ACT to generate the delayed active signal D_ACT. The address providing unit  110  provides memory address signals ADD&lt;1:15&gt; to an address line L_ADD in response to the active signal ACT. The bank address decoding unit  120  decodes bank addresses BA&lt;1:2&gt; and outputs the decoded result as first to fourth enable signals EN&lt;1:4&gt; in response to the delayed active signal D_ACT. The first to fourth address latching units  130 _ 1 ,  130 _ 2 ,  130 _ 3 , and  130 _ 4  latch addresses ADD_OUT&lt;1:15&gt; provided through the address line L_ADD and output the latched address signals in response to the respective first to fourth enable signals EN&lt;1:4&gt;. The first to fourth memory banks  140 _ 1 ,  140 _ 2 ,  140 _ 3 , and  140 _ 4  receive output signals ADD_LAT 1 &lt;1:15&gt;, ADD_LAT 2 &lt;1:15&gt;, ADD_LAT 3 &lt;1:15&gt;, and ADD_LAT 1 &lt;1:15&gt; respectively inputted from the first to fourth address latching units  130 _ 1 ,  130 _ 2 ,  130 _ 3  and  130 _ 4  to perform a data access operation. 
         [0008]      FIG. 2  is a circuit diagram illustrating the address providing unit  110  of  FIG. 1 . As described above, the address providing unit  110  is used to provide the memory address signals ADD&lt;1:15&gt; in response to the active signal ACT. A circuit corresponding to one bit of the 15-bits of the memory address signals ADD&lt;1:15&gt; is representatively illustrated in  FIG. 2 . 
         [0009]    As described in  FIGS. 1 and 2 , the related art semiconductor memory device provides the memory address signals ADD&lt;1:15&gt; to the address line L_ADD in response to the active signal ACT, and the related art semiconductor memory device outputs the first to fourth enable signals EN&lt;1:4&gt; generated by decoding the bank address signals BA&lt;1:2&gt; in response to the delayed active signal D_ACT. 
         [0010]    More specifically, the first to fourth memory banks  140 _ 1 ,  140 _ 2 ,  140 _ 3 , and  140 _ 4  receive the memory address signals ADD&lt;1:15&gt; when the delayed active signal D_ACT is activated so that the first to fourth enable signals EN&lt;1:4&gt; are output from the bank address decoding unit  120 . The first to fourth memory banks  140 _ 1 ,  140 _ 2 ,  140 _ 3 , and  140 _ 4  receive the memory address signals ADD&lt;1:15&gt; and subsequently perform the data access operation. Thus, the time when the semiconductor memory device performs the data access operation is determined by a time when the delayed active signal D_ACT is activated. 
         [0011]    Additionally, the first to fourth address latching units  130 _ 1 ,  13 _ 2 ,  130 _ 3 , and  130 _ 4  output the output addresses ADD_OUT&lt;1:15&gt; of the address providing unit  110 , which are inputted in response to an activated enable signal of the first to fourth enable signals EN&lt;1:4&gt;, to any one of the latched first to fourth address signals ADD_LAT 1 &lt;1:15&gt;, ADD_LAT 2 &lt;1:15&gt;, ADD_LAT 3 &lt;1:15&gt;, and ADD_LAT 1 &lt;1:15&gt;. More specifically, the address providing unit  110  provides the memory address signals ADD&lt;1:15&gt; to each of the first to fourth address latching units  130 _ 1 ,  130 _ 2 ,  130 _ 3 , and  130 _ 4 . However, if the fourth enable signal EN&lt;4&gt; is activated so that the fourth memory bank  140 _ 4  is activated, the current used when the memory address signals ADD&lt;1:15&gt; are provided to the first to third memory banks  140 _ 1 ,  140 _ 2  and  140 _ 3  is wasted current. 
       SUMMARY 
       [0012]    An embodiment of the present invention is directed to a semiconductor memory device including a bank address signal that is directly used to activate a path along which a memory address signal is provided. 
         [0013]    In accordance with an embodiment of the present invention, a semiconductor memory device includes a path control unit configured to activate an address transmission path corresponding to a bank address; an address providing unit configured to provide a memory address to the path control unit in response to an active signal; and a plurality of memory banks each configured to receive the memory address provided through the corresponding address transmission path of the path control unit, wherein the bank address corresponds to a memory bank of the plurality of memory banks. 
         [0014]    In accordance with another embodiment of the present invention, a semiconductor memory device includes a first memory bank configured to receive an address provided through a first address transmission line; a second memory bank configured to receive an address provided through a second address transmission line separate from the first address transmission line; an address providing unit configured to provide a memory address in response to an active signal; a first address output unit configured to output an output signal of the address providing unit to the first address transmission line in response to a bank address, wherein the bank address corresponds to a memory bank; and a second address output unit configured to output the output signal of the address providing unit to the second address transmission line in response to the bank address. 
         [0015]    In accordance with yet another embodiment of the present invention, an operating method of a semiconductor memory device includes electrically connecting an address transmission path for providing a memory address to a selected memory bank; providing the memory address to the address transmission path in response to an active signal; and performing a data access operation in the selected memory bank in response to the memory address. 
         [0016]    In accordance with still another embodiment of the present invention, a semiconductor memory device includes a path control unit configured to have a plurality of address transmission paths respectively corresponding to a number of bits of a bank address and activate one of the plurality of address transmission paths in response to the bank address; and a plurality of memory banks configured to receive a memory address provided through the activated address transmission path among the plurality of address transmission paths to perform a data access operation, wherein the bank address corresponds to a memory bank of the plurality of memory banks. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]      FIG. 1  is a block diagram illustrating a related art semiconductor memory device. 
           [0018]      FIG. 2  is a circuit diagram illustrating an address providing unit of  FIG. 1 . 
           [0019]      FIG. 3  is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention. 
           [0020]      FIG. 4  is a circuit diagram illustrating a configuration of an address providing unit and a central path control unit illustrated in  FIG. 3 . 
           [0021]      FIG. 5  is a circuit diagram illustrating a configuration of a first path control unit of  FIG. 3 . 
       
    
    
     DETAILED DESCRIPTION 
       [0022]    Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. 
         [0023]      FIG. 3  is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention. 
         [0024]    Referring to  FIG. 3 , the semiconductor memory device includes an address providing unit  310 , a central path control unit  320 , first and second path control units  330  and  340 , and first to fourth memory banks  350 ,  370 ,  360 , and  380 . 
         [0025]    The address providing unit  310  provides memory address signals ADD&lt;1:15&gt; to the central path control unit  320  in response to an active signal ACT. The central path control unit  320  activates an address transmission path in response to a first bank address signal BA&lt;1&gt;, and the first and second path control units  330  and  340  activate an address transmission path in response to a second bank address signal BA&lt;2&gt;. As will be described later, the output signal of the address providing unit  310  is provided to a selected memory bank among the first to fourth memory banks  350 ,  360 ,  370 , and  380  through an address transmission path activated by the first and second bank address signals BA&lt;1:2&gt; in the central path control unit  320  and the first and second path control units  330  and  340 . Subsequently, the first to fourth memory banks  350 ,  360 ,  370 , and  380  perform a data access operation in response to the memory address signals ADD&lt;1:15&gt; provided through the address transmission path. 
         [0026]    More specifically, the central path control unit  320  provides a first output address signal ADD_OUT 13 &lt;1:15&gt; to the first path control unit  330  through a first address transmission line L 1 _ADD, and the central path control unit  320  provides a second output address signal ADD_OUT 24 &lt;1:15&gt; to the second path control unit  340  through a second address transmission line L 2 _ADD. As will be described later in  FIG. 4 , the first and second address transmission lines L 1 _ADD and L 2 _ADD are separate transmission lines. 
         [0027]      FIG. 4  is a circuit diagram illustrating a configuration of the address providing unit  310  and the central path control unit  320  illustrated in  FIG. 3 . For illustration purposes, a circuit corresponding to one bit of 15-bits of the memory address signals ADD&lt;1:15&gt; is representatively illustrated in  FIG. 4 . 
         [0028]    Referring to  FIG. 4 , the address providing unit  310  receives a memory address signal ADD in response to the active signal ACT. Additionally, the central path control unit  320  has first and second address output units  410  and  420  for activating an address transmission path in response to the first bank address BA&lt;1&gt;. Here, the first address output unit  410  outputs the output signal of the address providing unit  310  as the first output address signal ADD_OUT 13  to the first address transmission line L 1 _ADD when the first bank address signal BA&lt;1&gt; is in a logic ‘low’ state, and the second address output unit  420  outputs the output signal of the address providing unit  310  as the second output address signal ADD_OUT 24  to the second address transmission line L 2 _ADD when the first bank address signal BA&lt;1&gt; is in a logic ‘high’ state. 
         [0029]      FIG. 5  is a circuit diagram illustrating a configuration of the first path control unit  330  of  FIG. 3 . The second path control unit  340  of  FIG. 3  has a configuration similar to the first path control unit  330 , and therefore, the first path control unit  330  will be representatively described. 
         [0030]    Referring to  FIG. 5 , the first path control unit  330  includes first and second address output units  510  and  530  and first and second latching units  520  and  540 . The first and second address output units  510  and  530  activate the address transmission path in response to the second bank address signal BA&lt;2&gt;. The first and second latching units  520  and  540  latch output signals of the first and second address output units  510  and  530 . 
         [0031]    Here, the first address output unit  510  outputs the first output address signal ADD_OUT 13  to the first latching unit  520  when the second bank address signal BA&lt;2&gt; is in a logic ‘low’ state, and the first latching unit  520  latches the first output address signal and outputs the latched first output address signal as a first latched output address ADD_LAT 1 . The second address output unit  530  outputs the first output address signal ADD_OUT 13  to the second latching unit  530  when the second bank address signal BA&lt;2&gt; is in a logic ‘high’ state, and the second latching unit  540  latches the first output address signal and outputs the latched first output address signal as a third latched output address ADD_LAT 3 . Referring back to  FIG. 3 , the first latched output address ADD_LAT 1 &lt;1:15&gt; is an address signal provided to the first memory bank  350 , and the third latched output address ADD_LAT 3 &lt;1:15&gt; is an address signal provided to the third memory bank  360 . 
         [0032]    As can be seen in  FIGS. 3 to 5 , in the semiconductor memory device in accordance with the present invention, the address transmission path, along which the memory address signals ADD&lt;1:15&gt; are provided, is determined by the first and second bank address signals BA&lt;1:2&gt;. The address transmission path is activated at the time when the first and second bank address signals BA&lt;1:2&gt; are inputted. More specifically, the address transmission path corresponding to any one of the first to fourth memory banks  350 ,  370 ,  360 , and  380  is electrically connected and activated by the first and second bank address signals BA&lt;1:2&gt;, and the memory address signals ADD&lt;1:15&gt; are provided to the selected memory bank through the activated address transmission path. In this embodiment, since address transmission paths respectively corresponding to the other memory banks other than the selected memory bank are not activated, the memory address signals ADD&lt;1:15&gt; are not transmitted to the other address transmission paths, and accordingly, additional current consumption does not occur. 
         [0033]    The memory address signals ADD&lt;1:15&gt; provided by the address providing unit  310  in response to the active signal ACT are directly provided to a selected memory bank through an address transmission path corresponding to any one of the first to fourth memory banks  350 ,  370 ,  360 , and  380  so that a data access time may be reduced. 
         [0034]    As described above, in the semiconductor memory device in accordance with the embodiment of the present invention, the address transmission path along which the address signals ADD&lt;1:15&gt; are provided can be activated using the first and second bank address signals BA&lt;1:2&gt;. Accordingly, current consumption may be reduced and a faster data access time may be secured. 
         [0035]    In accordance with the exemplary embodiments of the present invention, memory address signals are provided to an address transmission path corresponding to a selected memory bank using a bank address signal so that current consumption when the memory address signals are provided may be minimized. 
         [0036]    Further, the memory address signals are directly inputted to a corresponding memory bank so that the time when a data access operation is performed may be reduced. 
         [0037]    While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims. 
         [0038]    For example, the central path control unit  320  and the first and second path control units  330  and  340 , illustrated in  FIG. 3 , in accordance with the embodiment of the present invention, have four address transmission paths corresponding to 2-bit bank address signals, and one of the four address transmission paths is activated. However, the present invention may include an embodiment where the central path control unit  320  and the first and second path control units  330  and  340  have a plurality of address transmission paths respectively corresponding to the number of bits of the bank address signals. 
         [0039]    In addition, the positions and kinds of logic gates and transistors illustrated in the aforementioned embodiments may be differently implemented depending on the polarities of signals inputted thereto.