Abstract:
A triangular waveform generator is converted to a free running oscillator controlled by a calibration code. The free running oscillator can be synchronized to an external clock signal by comparing the external clock frequency to the frequency of the triangular waveform and adjusting the calibration code until the discrepancy in frequency is minimized.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates generally to pulse width modulation (PWM) and class-D amplifiers and specifically to clock-synchronized triangular waveform generators. 
         [0003]    2. Related Art 
         [0004]    Power delivery systems such as power amplifiers, switching voltage regulators, and electric motors often employ pulse-width modulation (PWM) to convey information or deliver power in an efficient manner. For example, class-D amplifiers employing PWM are used in powered audio devices due to their advantages in power consumption and size over traditional analog amplifiers. The improved power efficiency reduces the need for bulky heat sinks or advanced packaging, making class-D amplifiers more suitable for low-cost integrated circuits. 
         [0005]    The class-D amplifier produces an output comprising a sequence of pulses. Pulse-width modulation is typically employed to encode audio information into these pulses by varying their individual widths. The average value of these pulses represents the instantaneous amplitude of the output signal. These pulses also introduce unwanted high-frequency content which may be removed by a low pass filter. 
         [0006]      FIG. 1  is a block diagram illustrating the typical architecture of a class-D amplifier  100 . The input signal is converted to pulses using modulator  102  which can be a pulse-width modulator. A common implementation of a pulse-width modulator uses a high-speed comparator to compare the input signal against a triangle wave. The modulated signal is then amplified by amplifier  104  and finally demodulated by low pass filter  106 . The demodulated signal can then be used, for example by speaker  108 . 
         [0007]      FIG. 2  shows a typical PWM generator. Input reference signal  202  is compared by comparator  206  against a repetitive modulation source, such as a sawtooth or triangular waveform generated by ramp generator  204 . When the input reference signal is greater than the modulation source, the signal level of PWM output signal  208  is high; when the input reference signal is less than the modulation source, the signal level of PWM output signal  208  is low. 
         [0008]    In communication systems using class-D audio amplifiers, PWM performance is optimized for peak amplifier linearity. For a given modulation frequency, PWM performance is improved when the modulating source is a triangular waveform instead of a sawtooth.  FIG. 3A  shows traces of the signals related to a PWM generator using a sawtooth waveform. Graph  302  shows the sawtooth modulation source superimposed on the input reference signal. Graph  304  shows the resultant PWM output signal.  FIG. 3B  shows traces of the signals related to a PWM generator using a triangular waveform. Graph  312  shows the triangular modulation source superimposed on the input reference signal. Graph  314  shows the resultant PWM output signal. Because reference information is encoded on both the rising and falling edges of PWM signal  314 , as opposed to only one edge of PWM signal  304  when a sawtooth modulating source is employed, a triangular waveform is a preferable modulation source. 
         [0009]    In a typical class-D audio amplifier system, the input audio signal is an analog waveform reconstructed from digital samples. In order to reduce spectral folding and aliasing issues, it is desirable to have the triangular waveform synchronized to a frequency related to the sampling clock. Usually the sampling clock is a divided down version of a master clock. To avoid the aforementioned issues, the triangular waveform should be synchronized to another clock that is also divided down from the same master clock. 
         [0010]    Other challenges with the design of a synchronized triangular waveform generator include drift due to the triangle wave not returning to the same voltage level after each clock cycle, synchronization where the triangle waveform frequency does not match the clock rate of a given input clock, and linearity in either the upward ramp or downward ramp of the triangle waveform. Therefore, there is a need in the industry for an inexpensive and improved clock-synchronized triangular waveform generator. 
       SUMMARY OF INVENTION 
       [0011]    In a pulse modulator, a calibrated synchronized triangular waveform generator has a triangular waveform generator, a digital pulse generator which generates a square wave clock signal with essentially the same frequency as the generated triangle waveform, and a calibration circuit. During a calibration phase, the clock signal produced by the digital pulse generator is compared with an external clock signal and the triangular waveform generator is adjusted by the calibration circuit until the generated clock signal matches as close as possible to the external clock signal. 
         [0012]    The calibrated synchronized triangular waveform generator can further include a clock selection circuit which selects the clock signal generated during calibration and the external clock signal at other times, with the selected clock signal fed back to the triangular waveform generator. One embodiment of the digital pulse generator has two comparators and an RS latch. After calibration the digital pulse generator and the calibration circuit can be deactivated to save power. The calibration circuit can have a rate comparison circuit and a successive-approximation-register (SAR) logic block for adjusting the calibration code used by the triangular waveform generator. The triangular waveform generator can have a rising sawtooth waveform generator and a falling sawtooth waveform generator with complementary switching circuits that alternatively select the rising sawtooth waveform and the falling sawtooth waveform to generate the triangular waveform. 
         [0013]    Other systems, methods, features, and advantages of the present disclosure will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present disclosure, and be protected by the accompanying claims. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0014]    Many aspects of the disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. 
           [0015]      FIG. 1  is a block diagram illustrating the typical architecture of a class-D amplifier; 
           [0016]      FIG. 2  shows a typical PWM generator; 
           [0017]      FIG. 3A  shows traces of the signals related to a PWM generator using a sawtooth modulation waveform; 
           [0018]      FIG. 3B  shows traces of the signals related to a PWM generator using a triangular modulation waveform; 
           [0019]      FIG. 4  shows a synchronized triangular waveform generator; 
           [0020]      FIG. 5  shows a relation between the modulation clock and the switch control signals in the synchronized triangular waveform generator of  FIG. 4 ; 
           [0021]      FIG. 6  shows the case of voltage drift due to circuit non-idealities; 
           [0022]      FIG. 7  shows an embodiment of a synchronized triangular waveform generator which does not have voltage drift; 
           [0023]      FIG. 8  shows the signaling of the two sawtooth generators; 
           [0024]      FIG. 9  shows the effect of process variation on the ramp signal while maintaining a nominal clock frequency; 
           [0025]      FIG. 10  shows the effect of errors between the clock frequency and the nominal ramp slope; 
           [0026]      FIG. 11  diagrams how discontinuities in the triangular waveform can result in PWM errors; 
           [0027]      FIG. 12  is a self-oscillating triangle wave generator; 
           [0028]      FIG. 13  shows an example of the signaling of a self-oscillating triangle wave generator; 
           [0029]      FIG. 14  shows an embodiment of a triangle wave generator with calibration; 
           [0030]      FIG. 15  shows an embodiment of a triangle wave generator with an example of a calibration circuit; 
           [0031]      FIG. 16  shows a flowchart of the operation of the SAR logic block; 
           [0032]      FIG. 17  shows an embodiment of a programmable triangle wave generator which can be switched to use an external clock signal; 
           [0033]      FIG. 18  shows an embodiment of the programmable triangle wave generator with calibration circuitry; 
           [0034]      FIG. 19  shows how the calibration code varies versus the on-chip resistor variation; and 
           [0035]      FIG. 20  plots the magnitude of the discontinuities normalized to ramp amplitude with and without calibration. 
       
    
    
     DETAILED DESCRIPTION 
       [0036]    A detailed description of embodiments of the present invention is presented below. While the disclosure will be described in connection with these drawings, there is no intent to limit it to the embodiment or embodiments disclosed herein. On the contrary, the intent is to cover all alternatives, modifications, and equivalents included within the spirit and scope of the disclosure. 
         [0037]      FIG. 4  shows a synchronized triangular waveform generator. Triangular waveform generator  400  comprises fixed current source  402 , fixed current source  404  and capacitor  410 . Waveform generator  400  also comprises complementary switching circuits shown in this example by switch  406  and switch  408  which are switched in a complementary fashion such that when switch  406  is open, switch  408  is closed, and vice versa. A bias voltage is applied at  412  to triangular waveform generator  400 . Switch  406  is controlled by signal SWr and switch  408  is controlled by signal SWf. As shown in  FIG. 5 , switch  406  is synchronized to a modulation clock signal such that when the clock signal is high switch  406  is closed and when the clock signal is low switch  406  is opened. Complementary switch  408  is opened when the clock signal is high and closed with the clock signal is low. 
         [0038]    When switch  406  is closed and switch  408  is open, current source  404  charges capacitor  410  linearly until the next clock transition. When the clock goes low, switch  408  closes and switch  406  opens, allowing current source  402  to discharge capacitor  410  linearly. With substantially equal charge and discharge times (i.e. the modulation clock has a 50% duty-cycle) and matched current sources (the current drawn by current source  402  is the same as the current driven by current source  404 ), the voltage at node  414  is bounded between a peak ramp voltage V RAMP     —     H  and the bias voltage V BIAS . 
         [0039]    Imperfections in clock or switch timing or current source magnitudes can result in an undesirable mismatch between the charge transferred during the “charge” and “discharge” phases. For example, a charge error generated each clock period can accumulate over time resulting in a voltage drift towards one of the power rails and an eventual saturation.  FIG. 6  shows the case where the discharging current is slightly greater than the charging current, which causes the slope of the falling phase to be slightly greater than the slope of the rising phase. The ramp voltage drifts lower over each clock period, causing the waveform&#39;s common-mode voltage to vary over time. For proper operation using this arrangement a correction scheme to manage this drift may be used. 
         [0040]      FIG. 7  shows an embodiment of a synchronized triangular waveform generator which doesn&#39;t have the drift issue described previously. Waveform generator  700  employs two circuits, a rising sawtooth generator  710  and a falling sawtooth generator  720 , to generate separate rising and falling sawtooth waveforms. Each sawtooth generator is alternately connected to output  740  through switch  714  and switch  734 , respectively, to capture the rising and falling edges to form a triangular waveform. Therefore, the voltage V RAMP  seen at output  740  is the rising voltage V RISE  at output node  716  generated by rising sawtooth generator  710  when switch  714  is closed and is the falling voltage V FALL  at output node  736  generated by falling sawtooth generator  720  when switch  734  is closed. Switch  714  is controlled by a clock signal CLK and complementary switch  734  is controlled by the inverted clock signal CLK. 
         [0041]    Rising sawtooth generator  710  comprises current source  702 , complementary switches  706  and  708 , and capacitor  712 , and is coupled to low bias voltage V BIAS     —     L  at  704 . When switch  706  is closed and switch  708  is opened, the voltage at node  716  rises linearly from the low bias voltage due to current source  702  charging capacitor  712 . This generates the linear rising portion of the triangle wave seen at output  740 . When switch  708  is closed and switch  706  is opened, capacitor  712  is pre-charged back to the bias voltage V BIAS     —     L . During this pre-charge portion of the rising sawtooth generator&#39;s cycle, node  716  is disconnected from output  740  by switch  714 . 
         [0042]    Similarly, falling sawtooth generator  720  comprises current source  722 , complementary switches  726  and  728 , and capacitor  732 , and is coupled to high bias voltage V BIAS     —     H  at  724 . When switch  726  is closed and switch  728  is opened, the voltage at node  736  falls linearly from the high bias voltage due to current source  722  discharging capacitor  732 . This generates the linear falling portion of the triangle wave seen at output  740 . When switch  728  is closed and switch  726  is opened, capacitor  732  is pre-charged back to the bias voltage V BIAS     —     H . During this pre-charge portion of the falling sawtooth generator&#39;s cycle, node  736  is disconnected from output  740  by switch  734 . 
         [0043]    While wave generator  700  does not suffer the drawback of voltage drift since the capacitors are pre-charged to fixed voltages each cycle, there may be voltage discontinuities. Unlike the voltage drift problems discussed with reference to  FIG. 4 , errors from such discontinuities in wave generator  700  do not accumulate or grow over time as it does in waveform generator  400 . 
         [0044]      FIG. 8  shows the signaling at nodes  716  (V RISE ) and  736  (V FALL ). Graph  802  shows the clock signal. Graph  804  shows the voltage trace at node  716  and graph  806  shows the voltage trace at node  736 . The voltage V RISE  rises from V BIAS     —     L  up to V R     —     END , while the voltage V FALL  falls from V BIAS     —     H  down to V F     —     END . Since it is desirable to have a triangular wave with no discontinuities at the boundary between the rising and falling phases, constraints on the ramp slope (set by current sources and capacitors) and the ramp amplitude (set by the bias voltages V BIAS     —     H  and V BIAS     —     L ) are established. Specifically V R     —     END  should equal V BIAS     —     H  and V F     —     END  should equal V BIAS     —     L . 
         [0045]    In order to set the ramp slope properly, the relationship between the ramp phases and the bias voltages is determined. During a ramp phase a capacitor is either being charged or discharged by a constant current source. The voltage change across this capacitor can be written as: 
         [0000]    
       
         
           
             
               
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                   V 
                   C 
                 
               
               = 
               
                 
                   
                     
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                       DC 
                     
                     C 
                   
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                   Δ 
                    
                   
                       
                   
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                   t 
                 
                 = 
                 
                   
                     m 
                     ramp 
                   
                    
                   Δ 
                    
                   
                       
                   
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                   t 
                 
               
             
             , 
           
         
       
     
         [0000]    where the ramp slope is defined as 
         [0000]    
       
         
           
             
               
                 m 
                 ramp 
               
               = 
               
                 
                   I 
                   DC 
                 
                 C 
               
             
             , 
           
         
       
     
         [0000]    I DC  is the current supplied by the current source, and C is the capacitance of the capacitor in each sawtooth generator. Since each charging or discharging phase lasts for half a clock period and the voltage swing is set by V BIAS     —     H  and V BIAS     —     L , the following constraint between the ramp slope and the voltage swing is derived: 
         [0000]    
       
         
           
             
               
                 V 
                 BIAS_H 
               
               - 
               
                 V 
                 BIAS_L 
               
             
             = 
             
               
                 Δ 
                  
                 
                     
                 
                  
                 
                   V 
                   C 
                 
               
               = 
               
                 
                   
                     m 
                     ramp 
                   
                    
                   
                     
                       T 
                       CLK 
                     
                     2 
                   
                 
                 = 
                 
                   
                     m 
                     ramp 
                   
                   
                     2 
                      
                     
                       f 
                       CLK 
                     
                   
                 
               
             
           
         
       
     
         [0046]    If the previous relationship holds, then there will be no discontinuities in the triangular waveform. However in practice the design variables are not perfectly controlled or fixed. For example, the clock frequency f CLK  can have a an error, or the system designer may want flexibility in setting the frequency, in which case the ramp discontinuities would increase as the clock frequency deviates from the nominally assumed value. Even if the clock frequency is fixed and ideally known, process and temperature variations in either the ramp slope or the bias voltages can cause large discontinuities. 
         [0047]    In order to generate process and temperature independent bias voltages, in one embodiment bias voltages V BIAS     —     H  and V BIAS     —     L  are created by forcing a DC current through a string of on-chip resistors. The resulting bias voltage is V BIAS =I BIAS R, where R is the resistance of the on-chip resistors. If I BIAS  is a current source that is made inversely proportional to the on-chip resistance, the resistance variations cancel out and the bias voltage can be made insensitive to process and temperature variations. Since the triangle wave oscillates between the two bias voltages, the ramp amplitude is consequently also made process and temperature independent. 
         [0048]    Previously the ramp slope was defined to be 
         [0000]    
       
         
           
             
               
                 m 
                 ramp 
               
               = 
               
                 
                   I 
                   DC 
                 
                 C 
               
             
             ; 
           
         
       
     
         [0000]    hence the ramp slope is inversely proportional to on-chip resistance (via the inverse relationship to I DC ) and the on-chip capacitor. Typical semiconductor processes will have resistors that exhibit process variations in the 20-30% range. Since on-chip capacitor variation is in general not well correlated with resistance, the process variations will not cancel one another and the ramp slope will exhibit a large variation. 
         [0049]      FIG. 9  shows an embodiment of the effect of process variation on the ramp signal while maintaining a nominal clock frequency. Trace  902  shows a nominal clock signal. Trace  904  is an ideal nominal case ramp signal while trace  906  and trace  908  are fast and slow process corners, respectively. In the fast corner, on-chip resistance is lower than nominal. Since it was previously shown that ramp slope is inversely proportional to resistance, in the fast corner the ramp slope is greater than nominal and trace  906  shows a large overshoot. In the slow corner, the resistance is larger than nominal and the resulting ramp slope is too low; this condition results in trace  908 . 
         [0050]      FIG. 10  illustrates an embodiment in which errors between the clock frequency and the ramp slope result in similar discontinuities in the triangular waveform. Trace  1002  shows a nominal clock and trace  1004  shows the resultant ramp waveform where the ramp slope is matched to the clock frequency. Trace  1012  shows a clock signal running faster than the nominal clock shown in trace  1002 , and trace  1014  is the resultant ramp waveform. Since the ramp slope was optimized for the nominal clock frequency, the slope is too low for the faster clock and the capacitor voltage won&#39;t reach the proper final voltage when the next ramp phase is initiated. This causes the voltage “jump” seen in circled region  1016 . Trace  1022  shows a clock signal running slower than the nominal clock shown in trace  1002 , and trace  1024  shows the resultant ramp waveform. In this case the ramp slope is too high and the ramp voltage overshoots the bias levels. Circled region  1026  shows a “jump” in the waveform. 
         [0051]    Ramp discontinuities can cause errors in the PWM generation, which can reduce system performance.  FIG. 11  diagrams how discontinuities in the triangular waveform can result in PWM errors. Graph  1102  shows an ideal triangular ramp waveform while graph  1104  shows a triangular ramp with a large voltage discontinuity at the ramp peaks. Graph  1106  shows the PWM signal resulting from the ideal triangular waveform and graph  1108  shows the PWM signal resulting from the triangular waveform with discontinuities which causes the PWM&#39;s rising edge to occur too soon. In applications such as class-D amplifiers where signal integrity is important across large modulation ranges (e.g., modulation indexes approaching 100%), timing errors such as these result in a dramatic loss of linearity. 
         [0052]      FIG. 12  is an embodiment of a programmable-frequency self-oscillating triangle wave generator  1200  using the basic architecture of triangle wave generator  700 . The wave generator  1200  comprises triangle wave generator  1220 , comparator  1206 , comparator  1208 , and RS latch  1210 . Triangle wave generator  1220  comprises a rising sawtooth generator  1240  and a falling sawtooth generator  1250 . Rising sawtooth generator  1240  is coupled to V BIAS     —     L  at  704  and comprises switch  706 , switch  708 , and capacitor  710 . Falling sawtooth generator  1250  is coupled to V BIAS     —     H  at  724  and comprises switch  726 , switch  728 , and capacitor  730 . The rising sawtooth generator  1240  and the falling sawtooth generator  1250  are alternatively coupled to output  740  of triangle wave generator  1220  via complementary switches  712  and  732 . Triangle wave generator  1220  differs from triangle wave generator  700  in that adjustable current source  1202  replaces current source  702  and adjustable current source  1204  replaces current source  722 . In one embodiment, the adjustable current sources are implemented using a current DAC which receives a digital value cal_code and produces a current ICAL based on the digital value. 
         [0053]    Comparators  1206  and  1208  combined with latch  1210  are essentially an exemplary embodiment of a digital pulse generator that generates a clock signal with essentially the same frequency as the triangular waveform generated at the output. Comparator  1206  compares the output voltage V RAMP  against high bias voltage V BIAS     —     H  supplied at  1214 , and comparator  1208  compares the output voltage V RAMP  against low bias voltage V BIAS     —     L  supplied at  1212 . When V RAMP  reaches V BIAS     —     H , comparator  1206  sends a high signal to the “reset” input of RS latch  1210  forcing the latch to generate a low signal. When V RAMP  falls to V BIAS     —     L , comparator  1208  sends a high signal to the “set” input of RS latch  1210  forcing the latch to generate a high signal. Output  1216  of RS latch  1210  is used as a clock to operate the switches in triangle wave generator  1220 . 
         [0054]      FIG. 13  shows an example of the signaling of self-oscillating triangle wave generator  1200 . It shows the V RAMP  signal shown as trace  1302  in relationship to the outputs of comparator  1206  (CompH OUT ) shown as trace  1304  and comparator  1208  (CompL OUT ) shown as trace  1306  as well as to the RS latch  1210  output (CLK) shown as trace  1308 . When the clock signal is high, the rising sawtooth generator  1240  causes V RAMP  to rise. When V RAMP  reaches V BIAS     —     H , CompH OUT  goes high causing RS latch  1210  to force CLK low. When the clock goes low, the switches in triangle wave generator  1220  connect the falling sawtooth generator  1250  to output  740 , causing V RAMP  to fall linearly until V RAMP  reaches V BIAS     —     L . When V RAMP  reaches V BIAS     —     L , CompL OUT  goes high causing RS latch  1210  to force CLK high. This causes the switches in triangle wave generator  1220  to connect rising sawtooth generator  1240  to output  740  and the process thus repeats. 
         [0055]    In this embodiment, self-oscillating triangle wave generator  1200  generates a triangle wave with minimal, if any, discontinuity. The slope of the rising and falling segments of the triangle waveform is directly proportional to the DC current applied to the capacitors, i.e. increasing the DC current results in the slope increasing. If the slope of V RAMP  were increased, the period between threshold crossings would decrease proportionally. Thus the frequency of the ramp and associated clock will also increase. The opposite occurs if the DC current is decreased. Lower DC current causes lower ramp slope, which results in a longer ramp period or lower frequency. Since self-oscillating triangle wave generator  1200  is effectively a programmable oscillator, I CAL  can be calibrated to the appropriate current level needed to match the wave generator&#39;s frequency to a desired incoming clock frequency. 
         [0056]      FIG. 14  shows an embodiment of a triangle wave generator with calibration. A triangle wave generator  1400  comprises self-oscillating triangle wave generator  1200  and calibration circuit  1402 . Calibration circuit  1402  receives clock signal CLK  1216  from wave generator  1200  and synchronization clock signal CLK_IN. By measuring the differences between CLK and CLK_IN, calibration circuit  1402  adjusts the frequency of wave generator  1200  to match CLK_IN by altering the DC current supplied by current sources  1202  and  1204 . In one embodiment, calibration circuit  1402  operates using a feedback mechanism that attempts to force CLK to match CLK_IN. 
         [0057]      FIG. 15  shows an embodiment of a triangle wave generator with an example calibration circuit. In this embodiment, triangle wave generator  1500  comprises a calibration circuit with rate comparison circuit  1510  and successive-approximation-register (SAR) logic  1508 . Comparison circuit  1510  comprises reference counter  1502 , comparison circuit  1504 , and ramp counter  1506 . Reference counter  1502  counts CLK_IN clock cycles and ramp counter  1506  counts CLK clock cycles. Comparison circuit  1504  in conjunction with reference counter  1502  acts as a timer to enable ramp counter  1506  for N periods of the CLK_IN signal, so that after N periods a determination can be made as to whether the CLK signal has a higher or lower frequency than the CLK_IN signal. If fewer than N cycles of the CLK signal are counted after N periods of the CLK_IN signal are counted, then the CLK signal has a lower frequency than the CLK_IN signal. Similarly, if the count determined by ramp counter  1506  is greater than N at the end of N periods of the CLK_IN signal, then CLK has a higher frequency than the CLK_IN signal. SAR logic  1508  uses this information to adjust the CLK signal. 
         [0058]    In one embodiment, SAR logic  1508  determines the calibration value “cal_code” which results in a CLK signal which most closely matches the CLK_IN signal in frequency.  FIG. 16  is a flowchart illustrating an embodiment of the operation of the SAR logic block. At step  1602 , a binary search is initialized by setting cal_code to all zeros and setting n equal to B, the number of bits in cal_code. At step  1604 , the n th  bit of cal_code is set to 1. At step  1606 , a determination is made as to whether CLK is faster than CLK_IN. This can be performed by rate comparison circuit  1510 . If true, the n th  bit of cal_code is reset to 0 at step  1608  and then step  1610  is executed. If at step  1606  the CLK signal is slower than the CLK_IN signal, the n th  bit is left high and step  1610  is executed. At step  1610 , a determination is made as to whether n is greater than 1, i.e. the process has reached the lowest bit of cal_code. If n is greater than 1, n is decremented at step  1612  and the process repeats on the next significant bit by returning to step  1604 . If at step  1610  n is not greater than 1, the calibration operation is complete and the cal_code value which yields the closest frequency match between CLK and CLK_IN has been found and is frozen by the SAR logic block at step  1614 . 
         [0059]    In order to obtain an accurate comparison, N should be greater than 2 B . To demonstrate this process, suppose cal_code is a six-bit code such that B=6. Because N should be greater than 2 6 =64, a choice of N=128 is convenient. The process begins by setting cal_code to [100000]. Assuming that this code yields a CLK frequency that is higher than CLK_IN&#39;s frequency (i.e., the output of ramp counter  1506  is greater than 128), then the highest bit is cleared, i.e. cal_code=[000000]. Note that bits in bold text designate code bits that have been determined and are fixed for the remainder of the calibration procedure. On the next iteration, the 5 th  bit is set high and cal_code=[010000]. Suppose that this code yields a CLK frequency that is lower than CLK_IN&#39;s frequency; the 5 th  bit then remains set high. On the next iteration, the 4 th  bit is set high and cal_code=[011000]. Suppose that this code also yields a CLK frequency that is lower than CLK_IN&#39;s frequency; then the 4 th  bit remains set high. On the following iteration, the 3 rd  bit is set high such that cal_code=[011100]. If this code results in a CLK frequency that is higher than CLK_IN&#39;s frequency, then the 3 rd  bit is cleared, i.e. cal_code=[011000]. Continuing to the next iteration, the 2 nd  bit is set high so cal_code=[011010]. Assuming that this code yields a CLK frequency lower than CLK_IN&#39;s frequency, then the 2 nd  bit remains set high. On the last iteration, the 1 st  bit is set high and cal_code=[011011]. If this code results in a CLK frequency that is higher than CLK_IN&#39;s frequency, then the 1 st  bit is cleared low, thus leaving the calibration code set to a final value of cal_code=[011010]. 
         [0060]    Because it is likely that the frequency of CLK_IN and the frequency of a calibrated CLK will not be exactly the same, triangle wave generator  1220  will not be precisely synchronized with CLK_IN. Even if there was no frequency error between the two clock signals, there may still be a phase shift between the two. In one embodiment, after calibration is complete, the triangle wave generator  1220  is driven with CLK_IN to synchronize the resultant triangle wave signal V RAMP  with CLK_IN while maintaining minimal discontinuities. 
         [0061]      FIG. 17  shows an embodiment of a programmable triangle wave generator that can be switched to be synchronized and driven by an external clock signal. Programmable triangle wave generator  1700  is similar to self-oscillating triangle wave generator  1200 , but further comprises selection circuitry shown in this example by multiplexer  1702 . During calibration, the multiplexer&#39;s input select is set to one and the internally generated clock signal comp clk is used to drive triangle generator  1220 . The output of the multiplexer, signal  1704 , can be sent to the calibration circuitry. After calibration is complete, multiplexer  1702  can be set to select the external clock signal CLK_IN to drive triangle wave generator  1220 , thus producing an output signal which is a triangle wave synchronized to CLK_IN. 
         [0062]      FIG. 18  shows an embodiment of the programmable triangle wave generator with calibration circuitry. The components are described previously in  FIGS. 12 ,  15 , and  17 . In addition to the cal_en signal enabling calibration and controlling which clock signal drives triangle wave generator  1220 , cal_en can also be used to indicate when calibration has completed. When the cal_en signal is in the low state, calibration is complete and the calibration circuitry as well as comparators  1206  and  1208  and latch  1210  can be disabled to save power. 
         [0063]    Simulation results of a calibration system employing a 6-bit current DAC are shown in  FIGS. 19 and 20 .  FIG. 19  shows how the calibration code varied versus the on-chip resistor variation. The plot shows that the calibration was monotonic with variation, as expected. Under nominal conditions, cal_code=32 which was at the midpoint of its range (0-63). At high positive variations, on-chip resistance is higher than nominal; thus the ramp slope is lower than ideal. The calibration then correctly determined that a higher DAC current was needed to increase the ramp slope. 
         [0064]      FIG. 20  plots the magnitude of the discontinuities normalized to ramp amplitude with and without calibration. A positive error indicates that the discontinuity is due to a ramp voltage that overshoots the bias voltages (see graph  906  of  FIG. 9  for an example). A negative error indicates that the ramp voltage was lower than the bias voltages (see graph  908  of  FIG. 9 ). The dashed trace  2002  shows how the voltage discontinuities of an uncalibrated ramp generator increase dramatically as process variation skews away from nominal. At high positive variations where the ramp slope is too low, the ramp voltage undershoots the ideal voltage by over 15%. Solid trace  2004  shows the magnitude of the discontinuities after calibration has been performed. The error is now bounded to less than 1.5% across the variation range. 
         [0065]    Additional simulations on other variations such as temperature, frequency deviation, and capacitance show similar behavior. The calibration has the added benefit that it isn&#39;t sensitive to errors in the DAC. DAC offset or non-linearity is not of vital importance since the calibration logic&#39;s binary search will always seek out the optimal DAC setting from what is available. The only constraint on the DAC is that it be monotonic, which is easily achieved in practice. 
         [0066]    The above-described embodiments are merely examples of possible implementations. Many variations and modifications may be made to the above-described embodiments without departing from the principles of the present disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the following claims.