Abstract:
A circuit including an analog-to-digital converter having a self-test capability that provides not only an indication of failure or performance degradation but also identifies the failed or degraded component or components.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure generally relates to the field of analog-to-digital converters and, more particularly, to a successive-approximation analog-to-digital converter. 
         [0003]    2. Description of the Related Art 
         [0004]    It is known that an analog-to-digital converter is a device for converting an analog signal into a digital signal represented by a determined number of bits. Specifically, it is known the successive-approximation analog-to-digital converter, wherein the bits of the digital signal are successively determined one by one, typically from the most significant bit to the least significant bit. 
         [0005]    Failures or performance degradation of the components of the analog-to-digital converter can occur. A successive-approximation analog-to-digital converter generally includes a first plurality of capacitors to convert a digital signal into an analog signal and a second plurality of capacitors to perform a self-calibration for compensating variations of capacitance values of the first plurality of capacitors, thus improving the accuracy of the analog-to-digital converter. 
         [0006]    There are known techniques for performing the test of the operation of the analog-to-digital converter by using circuits outside the analog-to-digital converter, which thus have the disadvantage of requiring a dedicated circuit for performing the test. 
         [0007]    Therefore it is necessary to guarantee a correct operation of the analog-to-digital converter, especially in applications that require high safety and reliability, such as for example in the automotive field. 
       BRIEF SUMMARY 
       [0008]    The present disclosure relates to an analog-to-digital converter in preferred embodiments thereof described herein. More particularly, the successive-approximation analog-to-digital converter according to the present disclosure can be used itself for performing a test for controlling its correct operation. This has the advantage of not requiring additional circuits external to the analog-to-digital converter and of not requiring complex modifications to the same analog-to-digital converter. Moreover, the analog-to-digital converter according to an aspect of the disclosure has the advantage of providing not only an indication of a failure or degradation of the operation of the analog-to-digital converter (for example, of a component of the converter), but also of providing the position of the failure or degradation within the analog-to-digital converter (that is which is the failed or degraded component). 
         [0009]    In accordance with the present disclosure, an analog-to-digital converter is provided that includes a first generator that generates a first analog value according to a configuration signal when the analog-to-digital converter is operating in a first phase of a test mode; a digital-to-analog converter adapted to generate a second analog value according to a control signal when the analog-to-digital converter is operating in a second phase of the test mode; a second generator that generates a digital value from the comparison of the first analog value with respect to the second analog value according to a successive-approximation algorithm when the analog-to-digital converter is operating in the second phase of the test mode; a controller adapted to receive a signal indicating the test mode, and adapted to: generate in the first phase the configuration signal, receive in the second phase the digital value and generate therefrom the control signal for controlling the generation of the second analog value according to the successive-approximation algorithm, and generate, from the digital value, an alarm signal indicating a failure within the analog-to-digital converter or indicating a degradation of the performance of the analog-to-digital converter. 
         [0010]    In accordance with another aspect of the present disclosure, an integrated circuit is provided that includes the analog-to-digital converter described above. 
         [0011]    In accordance with a further aspect of the present disclosure, an electronic system is provided that includes an analog-to-digital converter having a first generator that generates a first analog value according to a configuration signal when the analog-to-digital converter is operating in a first phase of a test mode; a digital-to-analog converter adapted to generate a second analog value according to a control signal when the analog-to-digital converter is operating in a second phase of the test mode; a second generator that generates a digital value from the comparison of the first analog value with respect to the second analog value according to a successive-approximation algorithm when the analog-to-digital converter is operating in the second phase of the test mode; a controller adapted to receive a signal indicating the test mode, and adapted to generate in the first phase the configuration signal, receive in the second phase the digital value and generate therefrom the control signal for controlling the generation of the second analog value according to the successive-approximation algorithm; generate, from the digital value, an alarm signal indicating a failure within the analog-to-digital converter or indicating a degradation of the performance of the analog-to-digital converter; and a micro-processor adapted to compare the digital value with respect to a range of values and to generate therefrom the alarm signal indicating the failure or the degradation, in case the digital value is out of the range. 
         [0012]    In accordance with still yet a further aspect of the present disclosure, a method for testing the operation of an analog-to-digital converter is provided, the method having a first phase and a second phase. The first phase includes the steps of: (a) receiving a signal indicating a test mode operation; (b) generating a configuration signal; (c) generating a first analog value according to the configuration signal; the second phase including the steps of: (d) generating a control signal; (e) generating a second analog value according to the control signal; (f) comparing the first analog value with respect to the second analog value and generating therefrom a digital value according to a successive-approximation algorithm; (g) receiving the digital value and generating therefrom the control signal for controlling the generation of the second analog value according to the successive-approximation algorithm; (h) generating, from the digital value, an alarm signal indicating a failure within the analog-to-digital converter or indicating a degradation of the performance of the analog-to-digital converter. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0013]    Further features and the advantages of the disclosure will be understood from the following description of a preferred embodiment and of its variations given in an illustrative way referring to the enclosed drawings, wherein: 
           [0014]      FIG. 1  schematically shows an analog-to-digital converter according to a first embodiment of the disclosure; 
           [0015]      FIGS. 2A ,  2 B,  2 C,  2 D schematically show several steps of a test operation mode of the analog-to-digital converter according to the first embodiment of the disclosure; 
           [0016]      FIG. 3  schematically shows a possible pattern of two signals which can be generated in the analog-to-digital converter according to the first embodiment of the disclosure; 
           [0017]      FIG. 4  schematically shows an analog-to-digital converter according to a second and third embodiments of the disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0018]    With reference to  FIG. 1 , an analog-to-digital converter is shown according to a first embodiment of the disclosure. 
         [0019]    The analog-to-digital converter  1  has a normal operation mode wherein it performs the conversion of an input analog value V in  (for example, an analog voltage value) into an output digital value S N  quantitated with N bit; the normal operation mode includes a sampling phase and a subsequent conversion phase. 
         [0020]    The analog-to-digital converter  1  further has a test operation mode wherein it performs a test of the operation of the analog-to-digital converter  1  itself. The test operation mode includes a configuration phase and a subsequent phase of execution of the successive-approximation algorithm, as will be described in more detail afterwards in the section relating to the operation of the analog-to-digital converter  1 . For example, the test operation mode can be activated when the analog-to-digital converter  1  is inactive, that is when the analog-to-digital converter  1  is not performing a conversion from analog to digital in the normal operation mode. 
         [0021]    The analog-to-digital converter  1  includes:
       a first generator  20  having an output terminal  2  and having the function of performing the sampling of the input analog value V in  when the analog-to-digital converter  1  operates in the sampling phase of the normal operation mode, and having the function of performing the conversion from the digital value S N  into an analog value when the analog-to-digital converter  1  operates in the conversion phase of the normal operation mode. Moreover, the first generator  20  is structured to generate at the output terminal  2  a first analog value (in the following referred to with V x ) as a function of a configuration signal S 3 , when the analog-to-digital converter  1  is configured to operate in the configuration phase of the test operation mode, as it will be explained more in detail afterwards in the section relating to the operation of the analog-to-digital converter  1 ;   a digital-to-analog converter  40  having an output terminal  3  for generating an analog value when the analog-to-digital converter  1  operates in normal operation mode. Moreover, the digital-to-analog converter  40  is structured to generate at the output terminal  3  a second analog value as a function of a control signal S 1  when the analog-to-digital converter  1  is configured to operate in the phase of execution of the successive-approximation algorithm of the test operation mode, as it will be explained more in detail in the following with reference to the description of the analog-to-digital converter  1  in the test mode. The digital-to-analog converter  40  is used to perform the test of the operation of components inside the analog-to-digital converter  1  (as it will be described more in detail in the following), by means of the execution of a successive-approximation algorithm on the digital-to-analog converter  40 ;   a second generator  30  that receives an analog value from the output terminal  2 , an analog value from the output terminal  3 , and generates a digital value S N  through a successive-approximation algorithm, when the analog-to-digital converter  1  is configured to operate in the conversion phase of the normal operation mode. Moreover, the second generator  30  is structured to receive the first analog value V x  from the output terminal  2  of the first generator  20 , is structured to receive the second analog value from the output terminal  3  of the digital-to-analog converter  40 , and it is structured to perform a comparison between the first analog value V x  and the second analog value. It is further structured to generate the digital value S N  corresponding to the digital conversion of the first analog value V x  by means of a successive-approximation algorithm when analog-to-digital converter  1  is configured to operate in the execution phase of the successive-approximation algorithm of the test operation mode, as it will explained more in detail hereinafter; and   a controller  50  for receiving a mode selection signal S 4  indicating the normal operation or test operation mode of the analog-to-digital converter  1  and for receiving the digital value S N  from the second generator  30 ; moreover, the controller  50  generates the control signal S 1  and provides it to the digital-to-analog converter  40  when the analog-to-digital converter  1  is configured to operate in the conversion phase of the normal operation mode and in the phase of execution of the successive-approximation algorithm of the test mode. The controller  50  is also structured to generate the configuration signal S 3  and provide it to the first generator  20  when the analog-to-digital converter  1  is configured to operate in the sampling phase of the normal operation mode and in the configuration phase of the test mode, as it will be explained more in detail hereinafter.       
 
         [0026]    It should be noted that the normal or test operation mode can be used in the same way with the analog-to-digital converter  1  or to the controller  50 ; therefore, it will be indicated as the normal or the test operation mode of the analog-to-digital converter  1  or of the controller  50 . 
         [0027]    Preferably, the first generator  20  of the first embodiment of the disclosure is implemented with a plurality of capacitors—indicated in the following with sampling capacitors— 21 ,  22 , . . .  24 ,  25  having equal capacitance values of the capacitors and having respective first terminals connected to each other in order to form a common terminal that coincides (see  FIG. 1 ) with the output terminal  2  of the first generator  20  (this common terminal will be indicated in the following with “common terminal  2 ”). The first generator  20  further includes a plurality of switches  26 ,  27 , . . .  28 ,  29  adapted to switch, as a function of the configuration signal S 3 , among a first, a second, and a third position for connecting the second terminals (that is the terminals different from the first terminals connected to each other to form the common terminal  2 ) of the plurality of sampling capacitors  21 ,  22 , . . .  24 ,  25  to the input analog value V in , or to a low reference voltage VrefL, or to a high reference voltage VrefH (higher than the low reference voltage VrefL), respectively. The plurality of sampling capacitors  21 ,  22 , . . .  24 ,  25  and the plurality of switches  26 ,  27 , . . .  28 ,  29  controlled by the configuration signal S 3  have the function of generating at the output terminal  2  the first analog value V x  at the end of the configuration phase of the test operation mode. The plurality of sampling capacitors  21 ,  22 , . . .  24 ,  25  and the plurality of switches  26 ,  27 , . . .  28 ,  29  controlled by the configuration signal S 3  also have the function of performing a digital-to-analog conversion of the digital value S N  (corresponding to the sampled input analog value V in ) when the analog-to-digital converter  1  operates during the conversion phase of the normal operation mode: therefore, in the conversion phase of the normal operation mode the plurality of sampling capacitors  21 ,  22 , . . .  24 ,  25  and the plurality of switches  26 ,  27 , . . .  28 ,  29  controlled by the configuration signal S 3  are such to operate as a capacitive-type digital-to-analog converter for converting the digital value S N  into an analog value. 
         [0028]    Preferably, the digital-to-analog converter  40  of the first embodiment of the disclosure is of a capacitive type, that is it is implemented with a plurality of capacitors—indicated in the following with reference capacitors— 41 ,  42 , . . .  44 ,  45  having equal capacitance values and having respective first terminals connected to each other in order to form a common terminal that coincides (see  FIG. 1 ) with the output terminal  3  of the digital-to-analog converter  40  (therefore such common terminal will be indicated in the following with “common terminal  3 ”). It should be noted that the plurality of reference capacitors  41 ,  42 , . . .  44 ,  45  (having equal capacitance values) is equivalent to a corresponding plurality of capacitors  41 ′,  42 ′, . . .  44 ′,  45 ′ with capacitance having half values with respect to the former capacitance, starting from capacitor  45 ′ to capacitor  41 ′, wherein the capacitor  45 ′ is associated to the most significant bit of the successive-approximation algorithm, while the capacitor  41 ′ is associated to the least significant bit of the successive-approximation algorithm; for example, the capacitance of the capacitor  44 ′ is half the capacitance of capacitor  45 ′ and the capacitance of the capacitor  41 ′ is half the capacitance of capacitor  42 ′. Moreover, the value of the capacitance of the reference capacitors  41 ,  42 , . . .  44 ,  45  is equal to the value of the capacitance of the sampling capacitors  21 ,  22 , . . .  24 ,  25 . The digital-to-analog converter  40  further includes a plurality of switches  46 ,  47 , . . .  48 ,  49  adapted to switch, as a function of the control signal S 1 , between a first and a second position for connecting the second terminals (that is the ones different from the common terminal  3 ) of the plurality of reference capacitors  41 ,  42 , . . .  44 ,  45  to a low reference voltage VrefL′ or to a high reference voltage VrefH′ (greater than the low reference voltage VrefL′) respectively, when the analog-to-digital converter  1  is configured to operate in the phase of execution of the successive-approximation algorithm of the test operation mode. Moreover, the switches  46 ,  47 , . . .  48 ,  49  are structured to be configured (by means of the control signal S 1 ) for connecting the second terminals of the plurality of reference capacitors  41 ,  42 , . . .  44 ,  45  to the low reference voltage VrefL′ or to the high reference voltage VrefH′, when the analog-to-digital converter  1  is configured to operate in the normal operation mode (for example, all the second terminals of the plurality of the reference capacitors  41 ,  42 , . . .  44 ,  45  are connected to the low reference voltage VrefL′). 
         [0029]    Preferably, the second generator  30  includes a comparator  31  having a sampling input terminal  37  that is connected to the common terminal  2 , includes a reference input terminal  38  that is connected to the common terminal  3  and includes an output terminal  39  on which is generated a logic value ‘1’ when the value on the sampling input terminal  37  is smaller than the value of reference terminal  38  and a logic value ‘0’ when the value on the sampling input terminal  37  is greater than the value of the reference terminal  38 . The second generator  30  further includes switches  35 ,  36  controlled by a switching signal S 2  and a N-bit register  32  connected to the output terminal  39  for storing the output digital value S N . 
         [0030]    According to the first embodiment of the disclosure, the controller  50  is structured to generate the configuration signal S 3  to control:
       the switches  26 ,  27 , . . .  28 ,  29  to connect the second terminals of the respective sampling capacitors  21 ,  22 , . . .  24 ,  25  to the input analog value V in , when the analog-to-digital converter  1  operates in the sampling phase of the normal operation mode;   the switches  26 ,  27 , . . .  28 ,  29  to connect the second terminals of the respective sampling capacitors  21 ,  22 , . . .  24 ,  25  to the high reference voltage VrefH or to the low reference voltage VrefL, when the analog-to-digital converter  1  operates in the conversion phase of the normal operation mode;   at least two of the switches  26 ,  27 , . . .  28 ,  29  to connect the second terminals of at least two of the respective sampling capacitors  21 ,  22 , . . .  24 ,  25  to the high reference voltage VrefH or to the low reference voltage VrefL, when the analog-to-digital converter  1  operates in the configuration phase of the test operation mode, as it will be described more in detail afterwards.       
 
         [0034]    Moreover, according to the first embodiment of the disclosure, the controller  50  generates the control signal S 1  for:
       configuring the switches  46 ,  47 , . . .  48 ,  49  to connect the second terminals of the respective reference capacitors  41 ,  42 , . . .  44 ,  45  to the high reference voltage VrefH′ and/or to the low reference voltage VrefL′ with a fixed configuration when the analog-to-digital converter  1  is configured to operate in the sampling and conversion phase of the normal operation mode;   configuring the switches  46 ,  47 , . . .  48 ,  49  to connect the second terminals of the respective reference capacitors  41 ,  42 , . . .  44 ,  45  to the high reference voltage VrefH′ and/or to the low reference voltage VrefL′ with a fixed configuration when the analog-to-digital converter  1  operates in the configuration phase of the test operation mode;   controlling the switches  46 ,  47 , . . .  48 ,  49  to connect the second terminals of the respective reference capacitors  41 ,  42 , . . .  44 ,  45  to the high reference voltage VrefH′ or to the low reference voltage VrefL′ when the analog-to-digital converter  1  to operate in the phase of execution of the successive-approximation algorithm of the test operation mode, as will be explained more in detail afterwards;   the switching signal S 2  to control the switches  35  and  36  in the closed position when the analog-to-digital converter  1  operates in the sampling phase of the normal operation mode and in the open position when the analog-to-digital converter  1  operates in the conversion phase of the normal operation mode.       
 
         [0039]    Moreover, according to the first embodiment of the disclosure, the controller  50  generates the switching signal S 2  to control the switches  35  and  36  in the closed position when the analog-to-digital converter  1  operates in steps a) and b) of the configuration phase of the test operation mode, in the open position when the analog-to-digital converter  1  operates in steps c) and d) of the configuration phase of the test operation mode, and in the open position when the analog-to-digital converter  1  operates in the phase of execution of the successive-approximation algorithm of the test operation mode, as will be explained more in detail afterwards. 
         [0040]    Switches  35  and  36  are designed to switch, depending on the switching signal S 2  generated by the controller  50 , between the closed position wherein the input terminals are connected to a common reference voltage V cm  and the open position. 
         [0041]      FIG. 3  schematically shows the pattern of the voltage signal S 6  (solid line) at the common terminal  2  and of the voltage signal S 7  (broken line) at the common terminal  3  when the analog-to-digital converter  1  operates in the test mode. 
         [0042]    It should be noted that the voltage signal S 6  is first equal to the common reference voltage V cm , then it has a variation from the value of the common reference voltage V cm  to the first voltage analog value V x  and finally is equal to the first voltage analog value V x , while the voltage signal S 7  is first equal to the common reference voltage V cm , and then it converges to the first voltage analog value V. 
         [0043]    Described hereinafter is the operation of the analog-to-digital converter  1  during the normal operation mode. 
         [0044]    In the normal operation mode, the analog-to-digital converter  1  operates first according to a sampling phase and then according to a conversion phase. 
         [0045]    Switches  46 ,  47 , . . .  48 ,  49  connect the second terminals of the reference capacitors  41 ,  42 , . . .  44 ,  45  to a fixed configuration, both during the sampling phase and during the conversion phase of the normal operation mode. For example, all the second reference terminals  41 ,  42 , . . .  44 ,  45  are connected to the low reference voltage VrefL′. 
         [0046]    Moreover, the impedance of the input sampling terminal  37  of the comparator  31  and the impedance of the input reference terminal  38  of the comparator  31  are of the capacitive type. 
         [0047]    During the sampling phase of the normal operation mode, the controller  50  generates the switching signal S 2 , which closes the switches  35 ,  36 , and generates the configuration signal S 3 , which connects switches  26 ,  27 , . . .  28 ,  29  to the input voltage V in  analog value. Consequently, the voltage at the ends of the sampling capacitors  21 ,  22 , . . .  24 ,  25  is equal to the difference between the common reference voltage V cm  and the analog value of the input voltage V in . Because in the example the switches  46 ,  47 , . . .  48 ,  49  connect the second terminals of the reference capacitors  41 ,  42 , . . .  44 ,  45  to the low reference voltage VrefL′, the voltage at the ends of the reference capacitors  41 ,  42 , . . .  44 ,  45  is equal to the difference between the common reference voltage V cm  and the low reference voltage VrefL′. 
         [0048]    During the conversion phase of the normal operation mode, the controller  50  generates a switching signal S 2 , which opens the switches  35  and  36  and carries out a successive-approximation algorithm, generating the configuration signal S 3  which connects the switches  26 ,  27  . . .  28 ,  29  to the high reference voltage VrefH or to the low reference voltage VrefL. Since this successive-approximation algorithm is known to those skilled in the art, it will not be described in detail. 
         [0049]    At the end of the conversion phase, the difference between the voltage of the common terminal  2  and the voltage of the common terminal  3  is smaller than the minimum resolution of the analog-to-digital converter. The second terminals of the sampling capacitors  21 ,  22 , . . .  24 ,  25  are connected (by means of the switches  26 ,  27 , . . .  28 ,  29 ) to the high reference voltage VrefH or to the low reference voltage VrefL, as a function of the value of the digital signal S N . Moreover, because the impedance of the reference terminal  3  of the comparator  31  is of a capacitive type, the voltage of the common terminal  3  of the plurality of reference capacitors  41 ,  42 ,  43 ,  44  is equal to the common reference voltage V cm . 
         [0050]    Therefore, at the end of the conversion the N-bit register  32  stores the N-bit digital value corresponding to the digital conversion of the input analog value V in . 
         [0051]    Described hereinafter is the operation of the analog-to-digital converter  1  during the test operation mode of the analog-to-digital converter  1  with reference to  FIGS. 2A ,  2 B,  2 C,  2 D, and  3 . 
         [0052]    As previously indicated, the analog-to-digital converter  1  in the test operation mode includes a configuration phase and a subsequent phase of execution of the successive-approximation algorithm. The configuration phase is between times t 0  and t 5  (excluded) shown in  FIG. 3 , while the phase of execution of the successive-approximation algorithm is between times t 5  and t 8 . Moreover, for a correct operation of the analog-to-digital converter  1 , it is assumed that there are no failures or degradations of components inside the analog-to-digital converter  1 . 
       Configuration Phase of the Test Operation Mode 
       [0053]    In the configuration phase of the test operation mode, the controller  50  generates a sequence of values of the configuration signal S 3  for configuring at least two of the switches  26 ,  27 , . . .  28 ,  29  in order to connect the second terminals of at least two of the respective sampling capacitors  21 ,  22 , . . .  23 ,  24  to the high reference voltage VrefH or to the low reference voltage VrefL (while the second terminals of other sampling capacitors are floating). For the sake of simplicity, consider the example wherein the controller  50  generates a sequence of values of the configuration signal S 3  for configuring the two switches  26 ,  27  in order to connect the second terminals of the two sampling capacitors  21 ,  22  to the high reference voltage VrefH or to the low reference voltage VrefL (while the second terminals of the other sampling capacitors  24 ,  25  are floating) and the controller  50  generates the sequence of values of the configuration signal S 3  according to the steps a), b), c), d) explained afterwards. 
         [0054]    In the configuration phase of the test mode, switches  46 ,  47 , . . .  48 ,  49  connect the second terminals of the reference capacitors  41 ,  42 , . . .  44 ,  45  to a fixed configuration. Advantageously, all the second terminals of the reference capacitors  41 ,  42 , . . .  44  are connected to the low reference voltage VrefL′ and the capacitor  45  to the high reference voltage VrefH′, so that in the phase of execution of the successive-approximation algorithm of the test mode it is possible to detect a variation of the voltage signal S 6  leading the voltage signal S 6  to a value both greater and smaller than the value of the voltage signal S 7 .  FIG. 3  shows the example wherein between times t 3  and t 4  of the configuration phase occurs a variation of the voltage signal S 6  leading the voltage signal S 6  to a value greater than the value of the voltage signal S 7 . 
         [0055]    The configuration phase of the test mode includes the following steps a-d. 
         [0056]    Steps a and b generate part of the sequence of values of the configuration signal S 3  to initialize the values of the voltage at the ends of the sampling capacitors  21  and  22 . 
         [0057]    Step a) 
         [0058]    Step a) is between times t 0  and t 1  (excluded) as shown in  FIG. 3 . At time t 0  the controller  50  generates the first values of the sequence of the configuration signal S 3 , which configures the switches  26  and  27  to connect the second terminal of the capacitor  21  to the high reference voltage VrefH and connecting the second terminal of the capacitor  22  to the low reference voltage VrefL, as schematically shown in  FIG. 2A . Moreover, the controller  50  generates the switching signal S 2 , which closes the switches  35  and  36  (see  FIG. 2A ). In this way the common terminal  2 , the input sampling terminal  37 , the common terminal  3 , and the input reference terminal  38  are connected to the common reference voltage V cm . Consequently, the value of the voltage signal S 6  at the common terminal  2  and the value of voltage signal S 7  at the common terminal  3  are equal to the common reference voltage V cm  (as shown in  FIG. 3  at time t 0 ). In addition, the value of voltage at the ends of the capacitor  21  is equal to the difference between the high reference voltage VrefH and the common reference voltage V cm , and the voltage value at the ends of the capacitor  22  is equal to the difference between the common reference voltage V cm  and the high reference voltage VrefL. 
         [0059]    Step b) 
         [0060]    Step b) is between times t 1  and t 2  (excluded) shown in  FIG. 3 . At time t 1  the controller  50  generates second values of the sequence of the configuration signal S 3 , which performs a first inversion of voltage of the second terminals of sampling capacitors  21 ,  22 . That is, it configures the switches  26  and  27  connecting the second terminal of the capacitor  21  to the low reference voltage VrefL and connects the second terminal of the capacitor  22  to the high reference voltage VrefH, as schematically shown in  FIG. 2B . Moreover, the controller  50  generates the switching signal S 2 , which keeps closed the switches  35  and  36  (see  FIG. 2B ). Consequently, the value of the voltage signal S 6  at the common terminal  2  and value of the voltage signal S 7  at the common terminal  3  is equal to the common reference voltage V cm  (as shown in  FIG. 3  at time t 1 ), the value of the voltage at the ends of the capacitor  21  is equal to the difference between the common reference voltage V cm , and the low reference voltage VrefL and the value of voltage at the ends of the capacitor  22  is equal to the difference between the common reference voltage V cm  and the high reference voltage VrefH. 
         [0061]    Therefore, the amount of charge Q 1  accumulated into the capacitors  21  and  22  in step b) can be expressed by the following formula (1): 
         [0000]        Q   1   =−C   22 *( VrefH−V   cm )+ C   21 *( V   cm   −VrefL )  (1)
 
         [0000]    wherein C 21  is the value of the capacitance of the capacitor  21  and C 22  is the value of the capacitance of the capacitor  22 . 
         [0062]    Step c) 
         [0063]    Step c) is between times t 2  and t 3  (excluded) shown in  FIG. 3 . At time t 2 , the controller  50  generates the switching signal S 2 , which opens the switches  35  and  36  (see  FIG. 2C ), keeping the same configuration of step b) for switches  26  and  27 . At times between t 2  and t 3  the voltage signal S 6  at the common terminal  2  and the voltage signal S 7  at the common terminal  3  keep the value of the common reference voltage V cm , as shown in  FIG. 3 . 
         [0064]    Step d) 
         [0065]    Step d) is between times t 3  and t 4  shown in  FIG. 3 . 
         [0066]    Step d) has the purpose to generate at the common terminal  2  the first analog value V x , which will be calculated afterwards. 
         [0067]    At time t 3  the controller  50  generates third values of the sequence of configuration signal S 3 , which performs a second inversion of the voltage of the second terminals of the sampling capacitors  21 ,  22 . That is, it configures switches  26  and  27  connecting the second terminal of the capacitor  21  to the high reference voltage VrefH and connecting the second terminal of the capacitor  22  to the low reference voltage VrefL, as schematically shown in  FIG. 2D . Moreover, the controller  50  generates the switching signal S 2 , which keeps open the switches  35  and  36  (see  FIG. 2D ). 
         [0068]    At times comprised between t 3  and t 4 , the voltage signal S 6  at the common terminal  2  has a variation from the value of the common reference voltage V cm  to the first voltage analog value V x  (as shown in  FIG. 3 ), while the voltage signal S 7  at the common terminal  3  keeps the value of the common reference voltage V cm  (as shown in  FIG. 3 ). 
         [0069]    Consequently, at time t 4  the voltage value at the ends of the capacitor  21  is equal to the difference between the first voltage analog value V x  (whose value will be calculated in the following) and the high reference voltage VrefH and the voltage value at the ends of the capacitor  22  is equal to the difference between the first voltage analog value V x  and the low reference voltage VrefL. 
         [0070]    Therefore the quantity of charge Q 2  accumulated into the capacitors  21  and  22  in step d) can be expressed by the following formula (2): 
         [0000]        Q   2   =−C   22 *( V   x   −VrefL )− C   21 *( VrefH−V   x )  (2)
 
         [0000]    wherein V x  is the first voltage analog value of the common terminal  2 . 
         [0071]    Because the impedance of the sampling and reference input terminals  37  and  38  of the comparator  31  are of a capacitive type and because the switches  35  and  36  are open, the charge accumulated into the capacitors  21  and  22  cannot change between step b) and step d). Therefore it is possible to calculate the first voltage analog value V x  of the terminal  2  making equal the charge Q 1  accumulated in step b) to the charge Q 2  accumulated in step d): 
         [0000]      − C   22 *( VrefH−V   cm )+ C   21 *( V   cm   −VrefL )= C   22 *( V   x   −VrefL )− C   21 *( VrefH−V   x )  (3)
 
         [0000]    from which the first voltage analog value V x  of the common terminal  2  can be obtained: 
         [0000]        V   x   =V   cm +( VrefH−VrefL )*( C   21   −C   22 )/( C   21   +C   22 )  (4)
 
         [0072]    Since in the ideal case the values of the capacitance C 21  and C 22  are equal, in the ideal case the first voltage analog value V x  is equal to the value of common reference voltage V cm . 
         [0073]    On the contrary, in the real case the values of the capacitance C 21  and C 22  have some tolerances (for example caused by the manufacturing process) and thus the values of the capacitance C 21  and C 22  are slightly different. In this case it is possible to foresee a range of possible values of the capacitance C 21  and C 22 . Consequently, in the real case and in the hypothesis of a correct operation of the analog-to-digital converter  1 , the first voltage analog value V x  can take a range of correct values between V x,min  and V x,max  and this range is centered around the common reference voltage V cm , where V x,min  and V x,max  are known values that depend on the tolerances of the values of capacitance C 21  and C 22 . 
         [0074]    Therefore at the end of the step d) of the configuration phase of the test mode, by means of the sequence of values of configuration signal S 3 , it has been generated the first voltage analog value V x  at the common terminal  2 , as shown in  FIG. 3  wherein the value of the voltage signal S 6  at the common terminal  2  at time t 4  is equal to V x . This first voltage analog value V x  is a value that will be used at the end of step e) of the phase of execution of the successive-approximation algorithm of the test mode for performing the test of the operation of the analog-to-digital converter  1 , by means of a comparison of the digital value S N  stored into register  32  with respect to one or more pre-defined values (that are known), wherein the digital value S N  corresponds to the digital conversion of the first voltage analog value V x . 
         [0075]    Therefore steps a)-d) perform the initialization and the configuration of a pair of the plurality of the sampling capacitors  21 ,  22 , . . . ,  24 ,  25 . 
         [0076]    The voltage value at the common terminal  2  remains substantially equal to the first voltage analog value V x  also in the subsequent times of the phase of execution of the successive-approximation algorithm of the test operation mode, as shown in  FIG. 3  between times t 5  and t 8 ; similarly, at the same times comprised between t 5  and t 8  the second terminals of the capacitors  21  and  22  remain connected as described in step d) (that is the second terminal of the capacitor  21  remains connected to the high reference voltage VrefH and the second terminal of the capacitor  22  remains connected to the low reference voltage VrefL). 
       Phase of Execution of the Successive-Approximation Algorithm of the Test Operation Mode 
       [0077]    Step e) 
         [0078]    The phase of execution of the successive-approximation algorithm consists of step e) between times t 5  and t 8  shown in  FIG. 3 . In the step e) a successive-approximation algorithm is carried out on the plurality of reference capacitors  41 ,  42 , . . .  44 ,  45  of the digital-to-analog converter  40 . The controller  50  generates the switching signal S 2 , which keeps open the switches  35 ,  36  and carries out (times t 5 , t 6 , t 7 , t 8 ) the successive-approximation algorithm, generating the control signal S 1  in order to connect the switches  46 ,  47 , . . .  48 ,  49  to the high reference voltage VrefH′ or to the low reference voltage VrefL′. Since such a successive-approximation algorithm is known to one skilled in the field, it will not be described in detail. It should be noted only that in case of a correct operation of the analog-to-digital converter  1 , at the end of the phase of execution of the successive-approximation algorithm of the test operation mode such successive-approximation algorithm is such that the voltage signal S 7  at common terminal  3  has a pattern converging to a second voltage analog value near the first voltage analog value V x  of the common terminal  2  (as schematically shown in  FIG. 3  between times t 7  and t 8 ), wherein V x  can take a range of possible values and this range is centered around the common reference voltage V cm  (as previously explained in the formula for calculating V x ). 
         [0079]    Moreover, supposing again a correct operation of the analog-to-digital converter  1 , at the end of the phase of execution of the successive-approximation algorithm of the test operation mode the digital value S N  stored into the register  32  corresponds to the digital conversion of the first analog value V. That is, the digital value S N  is substantially equal to the digital conversion of the common reference voltage V cm . The first analog value V x  takes correct values in a range between V x,min  and V x,max  and is centered around the common reference voltage value V cm , wherein V x,min  and V x,max  are known values depending on the tolerances of the sampling capacitors  21 ,  22 , . . . ,  24 ,  25  (as previously explained in the formula for calculating V x ). Consequently, the digital value S N  takes correct values in a range between S N,min  and S N,max , wherein S N,min  is a known value corresponding to the digital conversion of V x,min , and S N,max  is a known value corresponding to the digital conversion of V x,max . The second terminals of the reference capacitors  41 ,  42 , . . .  44 ,  45  at the end of the phase of execution of the successive-approximation algorithm of the test operation mode are connected (by means of the switches  46 ,  47 , . . .  48 ,  49 ) to the high reference voltage VrefH′ or to the low reference voltage VrefL′, as determined by the successive-approximation algorithm carried out on the plurality of reference capacitors  41 ,  42 , . . .  44 ,  45 . 
         [0080]    In the preceding description of the operation of the analog-to-digital converter  1  it has been supposed that there are no failures or degradations of the components inside the analog-to-digital converter  1 . If, on the contrary, there is a failure or a degradation of a component inside the analog-to-digital converter  1  (for example, a failure of capacitors  21  or  22 ), in the above mentioned example the first voltage analog value V x  is substantially different from the common reference voltage value V cm . That is, the first voltage analog value V x  is outside the range between V x,min  and V x,max  and is centered around the common reference voltage V cm  value. Consequently, the digital value S N  takes values that are outside the range of values between S N,min  and S N,max . 
         [0081]    Moreover, it is also possible to determine the type of failure or degradation, as it will be explained more in detail afterwards. 
         [0082]    It will be indicated in the following examples of failures that can be detected in the test operation mode of the analog-to-digital converter  1  according to the first embodiment of the disclosure by means of the configuration of the two sampling capacitors  21 ,  22  (steps a)-d)) and of the execution of the successive-approximation algorithm (step e)). 
       EXAMPLES 
     Example 1 
       [0083]    The failure is an open circuit between the sampling capacitor  22  and the high reference voltage VrefH. In this case, in step b) the voltage of the capacitor  22  is not charged to the value (VrefH−V cm ) and keeps the value (VrefL−V cm ) of step a). 
         [0084]    Therefore formula (3) becomes the following (the first voltage analog value is indicated by V x1 ); 
         [0000]      − C   22 *( VrefL−V   cm )+ C   21 *( V   cm   −VrefL )= C   22 *( V   x1   −VrefL )− C   21 *( VrefH−V   x1 )  (3a)
 
         [0085]    Therefore the formula (4) of the first voltage analog value V x1  becomes the following: 
         [0000]        V   x1   =V   cm +( VrefH−VrefL )* C   21 /( C   21   +C   22 )  (4a)
 
         [0086]    The value of V x1  in formula (4a) is different from the value V x  of the formula (4). Therefore the value V x1  will be outside the range of the correct values comprised between V x,min  and V x,max , and thus the digital value S N1  (corresponding to the digital conversion of V x1 ) will be outside the range of the correct values between S N,min  and S N,max  (wherein S N,min  is the digital conversion of V x,min  and S N,max  is the digital conversion of V x,max ). 
         [0087]    Similar considerations can be done in the case of an open circuit between capacitor  21  and the high reference voltage VrefH. 
       Example 2 
       [0088]    The failure is an open circuit between the sampling capacitor  22  and the low reference voltage VrefL. In this case, during step d) the voltage of the capacitor  21  is not charged to value (V x −VrefL) and keeps the value (V cm −VrefH) of step c). In this case, the formula (3) becomes the following (the first voltage analog value is indicated by V x2 ): 
         [0000]      − C   22 *( VrefH−V   cm )+ C   21 *( V   cm   −VrefL )= C   22 *( V   cm   −VrefH )− C   21 *( VrefH−V   x2 )  (3b)
 
         [0089]    Therefore the formula (4) of the first voltage analog value V x2  becomes the following: 
         [0000]        V   x2   =V   cm   +VrefH−VrefL   (4b)
 
         [0000]    In the hypothesis that V cm =(VrefH+VrefL)/2, the formula (4b) becomes the following: 
         [0000]        V   x2 =( VrefH+VrefL )/2 +VrefH−VrefL   (4c)
 
         [0090]    Therefore the value V x2  in the formula (4c) is different from the value V x  of the formula (4). The value V x2  will be outside the range of the correct values between V x,min  and V x,max , and thus the digital value S N2  (corresponding to the digital conversion of V x2 ) will be outside the range of the correct values between S N,min  and S N,max  (wherein S N,min  is the digital conversion of V x,min  and S N,max  is the digital conversion of V x,max ). 
         [0091]    Similar considerations can be done in the case of an open circuit between the capacitor  21  and the low reference voltage VrefL. 
       Example 3 
       [0092]    The failure is a short-circuit between the sampling capacitor  22  and the high reference voltage VrefH. In this case, during step d) the voltage of the capacitor  22  is not charged to the value (VrefL−V x3 ), but it is equal to the value (V f −V x3 ), wherein V f  is a voltage between VrefH and VrefL, whose value depends on the resistance R H  of the switch  27  between the capacitor  22  and the high reference voltage VrefH and depends on the resistance R L , of the switch  27  between the capacitor  22  and the low reference voltage VrefL, according to the following formula: 
         [0000]        V   f   =VrefH*[RL/(   RF+RL )]+ VrefL*[RH /( RH+RL )]  (5c)
 
         [0093]    In this case the formula (3) becomes the following (the first voltage analog value is indicated with V x3 ): 
         [0000]      − C   22 *( VrefH−−V   cm )+ C   21 *( V   cm   −VrefL )= C   22 *( V   x3   −V   f )− C   21 *( VrefH−V   x3 )  (3c)
 
         [0094]    Therefore the formula (4) of the first voltage analog value V x3  becomes the following: 
         [0000]        V   x3   =V   cm   +VrefH*[(   C   21   −C   22 )*( C   22   +C   21 )]+( C   22   *V   f   −C   21   *VrefL )/( C   22   +C   21 )  (4c)
 
         [0000]    In the hypothesis that the value V f  is sufficiently different from the value of the low reference voltage VrefL, the value V x3  of the formula (4c) is different from the value V x  of the formula (4). Therefore the value V x3  will be outside the range of the correct values between V x,min  and V x,max , and thus the digital value S N3  (corresponding to the digital conversion of V x3 ) will be outside the range of the correct values between S N,min  and S N,max  (wherein S N,min  is the digital conversion of V x,min  and S N,max  is the digital conversion of V x,max ). 
         [0095]    Similar considerations can be done in the case of a short-circuit between the capacitor  21  and the high reference voltage VrefH. 
       Example 4 
       [0096]    The failure is a short-circuit between the sampling capacitor  22  and the low reference voltage VrefL. In this case, in step b) the voltage of the capacitor  22  is not charged to the value (VrefH−V cm ), but it is equal to the value (V f −V cm ), wherein V f  has the value indicated in the formula (5c). 
         [0097]    In this case, the formula (3) becomes the following (the first voltage analog value is indicated with V x4 ): 
         [0000]      − C   22 *( V   f   −V   cm )+ C   21 *( V   cm   −VrefL )= C   22 *( V   x4   −VrefL )− C   21 *( VrefH−V   x4 )  (3d)
 
         [0098]    Therefore the formula (4) of the first voltage analog value V x4  becomes the following: 
         [0000]        V   x4   =V   cm   +VrefL*[(   C   22   −C   21 )*( C   22   +C   21 )]+( C   21   *VrefH−C   22   *V   f )/( C   22   +C   21 )  (4d)
 
         [0099]    In the hypothesis that the value V f  is sufficiently different from the high reference voltage VrefH value, the value V x4  in the formula (4d) is different from the value V x  of the formula (4). Therefore the value of V x4  will be outside the range of the correct values between V x,min  and V x,max , and thus the digital value S N4  (corresponding to the digital conversion of V x4 ) will be outside the range of the correct values between S N,min  and S N,max  (wherein S N,min  is the digital conversion of V x,min  and S N,max  is the digital conversion of V x,max ). 
         [0100]    Similar considerations can be done for a short-circuit between the sampling capacitor  21  and the low reference voltage VrefL. 
       Example 5 
       [0101]    The failure is an open circuit between the common terminal  2  of the sampling capacitor  22  and the sampling input terminal  37  of comparator  31 . In this case, the sampling capacitor  22  is not charged and it is necessary to consider the parasitic capacitance (indicated with C p ) seen from the sampling input terminal  37  of the comparator  31 . 
         [0102]    Therefore the formula (3) becomes the following (the first voltage analog value is indicated with V x5 ): 
         [0000]        C   p *( V   cm   −Vg )+ C   21 *( V   cm   −VrefL )= C   p *( V   x5   −Vg )− C   21 *( VrefH−V   x5 )  (3e)
 
         [0000]    wherein Vg is the reference voltage of the capacitor  22 , in that is the voltage of the second terminal of the capacitor  22  (typically equal to ground). 
         [0103]    In the hypothesis that Vg is equal to ground, the formula (4) of the first voltage analog value V x5  becomes the following: 
         [0000]        V   x5   =V   cm   +C   21 *( VrefH−VrefL )/( C   p   +C   21 )  (4e)
 
         [0104]    In the hypothesis that the parasitic capacitance value C p  is not greater than the capacitance value C 21 , the value V x5  of the formula (4e) is thus different from the value V x  of formula (4). Therefore the value V x5  will be outside the range of correct values between V x,min  and V x,max , and thus the digital value S N5  (corresponding to the digital conversion of V x5 ) will be outside the range of correct values between S N,min  and S N,max  (wherein S N,min  is the digital conversion of V x,min  and S N,max  is the digital conversion of V x,max ). 
         [0105]    Similar considerations can be done in case of an open circuit between the common terminal of the capacitor  21  and the sampling input terminal  37  of the comparator  31 . 
         [0106]    Advantageously, in the test mode of Examples 1-5, the second terminals of the sampling capacitors not used for performing the test (in the example, they are the capacitors different from  21 ,  22 ) are connected at a constant value voltage (for example, VrefL). This has the advantage of avoiding parasitic couplings between signals that can cause oscillating signals or noise, affecting the first voltage analog value V x1 -V x5 . 
         [0107]    As previously indicated, at the end of the phase of execution of the successive-approximation algorithm of the test operation mode, it is checked if there is a failure or degradation of the operation of the analog-to-digital converter  1 . 
         [0108]    This can be performed inside or outside the analog-to-digital converter  1 . 
         [0109]    In the first case, the controller  50  further includes an output terminal  51  (see FIGS.  1  and  2 A-D) for generating, as a function of the digital value S N , an alarm signal S 5  indicating the correct operation (for example, a low logic value) of the analog-to-digital converter  1  or indicating a failure (for example, a high logic value) of at least one component in the analog-to-digital converter  1  or indicating a degradation of the performance of the analog-to-digital converter  1 . Specifically, the controller  50  receives the digital value S N  stored into the register  32 , receives the values S N,min  and S N,max  (for examples, they are read from a memory connected to the controller  50  or from a memory inside the controller  50 , or such values are written at hardware level into the controller  50 ), performs a comparison between the digital value S N  and the range defined between S N,min  and S N,max , checks if the digital value S N  is in the range and generates the alarm signal S 5  (in the example, the high logic value) if the digital value S N  is outside the range. 
         [0110]    In the second case, a microprocessor is connected to the analog-to-digital converter  1  and reads the digital value stored into the register  32 , receives the values S N,min  and S N,max  (for example, they are read from a memory connected to the processor), performs a comparison between the digital value S N  and the range defined between S N,min  and S N,max , checks if the digital value S N  is comprised within the range, and generates the alarm signal S 5  (in the example, the high logic value) if the digital value S N  is outside the range. 
         [0111]    Preferably, the phase of configuration and execution of the successive-approximation algorithm of the test mode is repeated for other pairs (or for all the pairs) of the sampling capacitors, that is for pairs of the sampling capacitors different from the pair  21 ,  22  of the previous example. This enables a determination of the position of a failure of at least one of the sampling capacitors  21 ,  22 , . . .  24 ,  25 . Moreover, in the test mode the steps a)-e) performed on the first capacitor pair are independent from the steps a)-e) performed on the second capacitor pair. This has the advantage that it is possible to stop the test after completing the test on the first capacitor pair, in order to return to the normal operation mode. Subsequently, it is possible to resume the execution of the test mode on the second capacitor pair without the necessity of performing again the test mode on the first capacitor pair. 
         [0112]    Advantageously, the phase of configuration and execution of the successive-approximation algorithm of the test mode is performed for a group of sampling capacitors having an even number of sampling capacitor greater than or equal to four. This has the advantage of reducing the number of the required switches  26 ,  27 , . . . ,  28 ,  29 . 
         [0113]    With reference to  FIG. 4 , it is shown an analog-to-digital converter  101  according to a second embodiment of the disclosure. It should be noted that in  FIG. 4  blocks, components or modules identical (or similar) are indicated with the same reference numerals in the first embodiment shown in  FIG. 1 . 
         [0114]    The analog-to-digital converter  101  further includes a resistive-type digital-to-analog converter  60  implemented with a resistive divider, that is with a series connection of a plurality of resistors  61 ,  62 , . . .  64 ,  64  connected between the high reference voltage VrefH and the low reference voltage VrefL, as schematically shown in  FIG. 4 . The resistive-type digital-to-analog converter  60  includes an output terminal  63  for providing a third voltage analog value V y  comprised between the high reference voltage VrefH and the low reference voltage VrefL by means of a plurality of switches  66 ,  67 , . . .  68 ,  69  alternatively closed and connected between the resistors  61 ,  62 , . . .  64 ,  65  and the output terminal  63 . 
         [0115]    Moreover, the analog-to-digital converter  101  includes a third generator  120  (similar to the first generator  20  of the first embodiment of the disclosure) having a plurality of switches  126 ,  127 , . . .  128 ,  129  adapted to switch, as a function of the configuration signal S 3 , among a first, a second, a third, and a fourth position for connecting the second terminals of the plurality of sampling capacitors  21 ,  22 , . . .  24 ,  25  to the input analog value V in , to the low reference voltage VrefL, to the high reference voltage VrefH or to the output terminal  63  of digital-to-analog converter  60  respectively. 
         [0116]    The digital-to-analog converter  60  is structured to generate at the output terminal  63  at least the third voltage analog value V y  as a function of the configuration signal S 3 , when the analog-to-digital converter  1  is configured to operate in the configuration phase of the test operation mode, similarly to what has been explained for the sampling phase of the normal operation mode. 
         [0117]    It should be noted that  FIG. 4  shows switches  126 ,  127 , . . .  128 ,  129  having four possible positions (connection to V in , VrefL, VrefH, output terminal  63 ), but it is possible to obtain the same operation using the switches  126 ,  127 , . . .  128 ,  129  having three possible positions (connection with V in , VrefL, VrefH) and adding another switch for connecting the output terminal  63  to the terminal having the input analog value V in . 
         [0118]    The operation of the analog-to-digital converter  101  according to the second embodiment of the test mode is similar to the operation of the analog-to-digital converter  1  in the normal operation mode, with the following differences:
       the value of the voltage signal S 107  at the common terminal  3  is equal to the common reference voltage V cm ;   in the test mode the controller  50  generates the control signal S 1  for configuring the switches  46 ,  47 , . . .  48 ,  49  for connecting the second terminals of the plurality of the reference capacitors  41 ,  42 , . . .  44 ,  45  to a fixed configuration (for example, all the second terminals of the plurality of reference capacitors  41 ,  42 , . . .  44 ,  45  are connected to the low reference voltage VrefL′);   in the configuration phase of the test mode the controller  50  generates the configuration signal S 3  in order to generate at the output terminal  63  the third voltage analog value V y  between the high reference voltage VrefH and the low reference voltage VrefL, as a function of the closed switch selected among the plurality of switches  66 ,  67 , . . .  68 ,  69 ;   in the configuration phase of the test mode the third voltage analog value V y  is sampled by the plurality of sampling capacitors  21 ,  22 , . . .  24 ,  25 , that is the controller  50  generates the switching signal S 2 , which closes the switches  35 ,  36  and generates the configuration signal S 3 , which configures the switches  126 ,  127 , . . .  128 ,  129  connecting the second terminals of the capacitors  21 ,  22 , . . .  24 ,  25  to the output terminal  63  having the third voltage analog value V y ;   the phase of execution of the successive-approximation algorithm of the test mode is similar to the conversion phase of the normal operation mode. That is, the controller  50  generates a switching signal S 2 , which opens the switches  35  and  36  and carries out a successive-approximation algorithm for generating the configuration signal S 3 , which connects the switches,  126 ,  127 , . . .  128 ,  129  to the high reference voltage VrefH or to the low reference voltage VrefL, as a function of the digital signal value S N .       
 
         [0124]    Therefore in the second embodiment of the disclosure the digital value S N  stored into the register  32  at the end of the operation of the test mode corresponds to the digital conversion of the third voltage analog value V y . 
         [0125]    During a correct operation of the analog-to-digital converter  101 , at the end of the phase of execution of the successive-approximation algorithm of the test operation mode the digital value S N  stored into the register  32  corresponds to the digital conversion of the third voltage analog value V y , wherein V y  can have possible values in a range centered around an ideal value of V y  and depending on the tolerances of the resistors  61 ,  62 , . . .  64 ,  65  and on the tolerances of the sampling capacitors  21 ,  22 , . . .  24 ,  25 . The ideal value of V y  is known because is equal to the voltage value generated at output terminal  63  of the resistive-type digital-to-analog converter  60 . For example, the third analog value V y  has values in a range comprised between V y,min  and V y,max  and centered around the ideal value of V y , where V y,min  and V y,max  are known values which depend on the tolerances of the resistors  61 ,  62 , . . .  64 ,  65  and on the tolerances of the sampling capacitors (caused, for example, by the manufacturing process). Consequently, the digital value S N  has values in a range comprised between S N,min ′ and S N,max ′, wherein S N,min ′ has a known value corresponding to the digital conversion of V y,min  and S N,max ′ is a known value corresponding to the digital conversion of V y,max . The second terminals of the sampling capacitors  21 ,  22 , . . .  24 ,  25  at the end of the phase of execution of the successive-approximation algorithm of the test operation mode are connected (by means of the switches  126 ,  127 , . . .  128 ,  129 ) to the high reference voltage VrefH or to the low reference voltage VrefL, as determined by the successive-approximation algorithm. 
         [0126]    In the previous description of the operation of the analog-to-digital converter  101 , it was supposed that there are no failures or degradations of the components inside the analog-to-digital converter  1 . If, on the contrary, there was a failure or a degradation of a component in the analog-to-digital converter  101 , in the example indicated above the third voltage analog value V y  is substantially different from the ideal value of V y , that is the third voltage analog value V y  is outside the range of correct values between V y,min  and V y,max . Consequently, the digital value S N  has values that are outside the range of correct values comprised between S N,min ′ and S N,max ′. 
         [0127]    The analog-to-digital converter  101  of the second embodiment of the disclosure in the test operation mode can detect failures previously indicated in the examples 1-5, and moreover it can detect failures indicated in the following other examples 6-14. 
       Example 6 
       [0128]    The failure is a short-circuit of at least one of the resistors  61 ,  62 , . . .  64 ,  65 . In this case, each of the third voltage analog values V y  generated by the closure of the corresponding switch selected among  66 ,  67 , . . .  68 ,  69  is outside the respective range of correct values between V y,min  and V y,max . Consequently, each of the digital values S N  (corresponding to the digital conversion of the respective third voltage analog value V y ) is outside the respective range of correct values between S N,min ′ and S N,max ′ (wherein S N,min ′ is the digital conversion of the respective V y,min  and S N,max ′ is the digital conversion of the respective V y,max ). 
         [0129]    Moreover, it is possible to detect the position of a short-circuited resistor (between  61 ,  62 , . . .  64 ,  65 ) because the third voltage analog value V y  generated by the closure of the switch (selected between  66 ,  67 , . . .  68 ,  69 ) connected to a terminal of a failed resistor is equal to the third voltage analog value V y  generated by the closure of the other switch (selected between  66 ,  67 , . . .  68 ,  69 ) connected to the other terminal of the failed resistor (in the same way, in case of a short-circuit between two or more resistors). 
       Example 7 
       [0130]    The failure is an open circuit of at least one of the resistors  61 ,  62 , . . .  64 ,  65 . In this case, the third voltage analog value V y  generated by the closure of anyone of the switches  66 ,  67 , . . .  68 ,  69  that select the resistors between the failed resistor and the high reference voltage VrefH is equal to the high reference voltage value VrefH. Therefore this third voltage analog value V y =VrefH is outside the range of correct values between V y,min  and V y,max . Consequently, the digital value S N  corresponding to the digital conversion of V y =VrefH is a string of bits having a high logic value (that is, “1111 . . . 11”). Thus it is outside the range of correct values between S N,min ′ and S N,max ′ (wherein S N,min ′ is the digital conversion of V y,min  and S N,max ′ is the digital conversion of V y,max ). Moreover, the third voltage analog value V y  generated by the closure of anyone of the switches  66 ,  67 , . . .  68 ,  69  that select the resistors between the failed resistor and the low reference voltage value VrefL is equal to the low reference voltage value VrefL. Therefore this third voltage analog value V y =VrefL is outside the range of correct values between V y,min  and V y,max . Consequently, the digital value S N  corresponding to the digital conversion of V y =VrefL is a string of bits having a low logic value (that is, “0000 . . . 00”). Thus it is outside the range of correct values between S N,min ′ and S N,max ′ (wherein S N,min ′ is the digital conversion of V y,min  and S N,max ′ is the digital conversion of V y,max ). 
         [0131]    In this case it is possible to determine the position of the failed resistor between  61 ,  62 , . . .  64 ,  65  by performing several iterations of the test mode in the following way. It is supposed that the digital-to-analog converter  60  includes four resistors  61 ,  62 ,  64 ,  65  and that the open-circuited failed resistor is  62 . The following iterations of the test mode are performed, wherein the controller  50  generates the configuration signal S 3  in order to perform the sequential closure of the switches  66 ,  67 ,  68 ,  69 :
       the switch  66  connected to the resistor  61  is closed and thus the third voltage analog value V y =VrefL;   the switch  67  connected to the resistor  62  is closed and thus the third voltage analog value V y =VrefL;   the switch  68  connected to the resistor  64  is closed and thus again the third voltage analog value V y =VrefL;   the switch  69  connected to the resistor  65  is closed and thus the third voltage analog value V y =VrefL.       
 
         [0136]    Therefore there is a transition from V y =VrefH to V y =VrefL between the closure of the switch  66  connected to the resistor  62  and the closure of the switch  67  (and thus the controller  50  detects that the digital value S N  has a transition from a string of bits having a high logic value to a string of bits having a low logic value). This indicates that the open-circuited failed resistor is the resistor  62 , interposed between the switch  66  and  67 . 
       Example 8 
       [0137]    The failure is at least one of the resistors  61 ,  62 , . . .  64 ,  65  having a resistance value substantially different from the nominal value. In this case, each of the third voltage analog values V y  generated by the closure of the corresponding switch selected among  66 ,  67 , . . .  68 ,  69  is shifted of a determined value with respect to the correct value and thus it is outside the respective range of correct values between V y,min  and V y,max . Consequently, each digital values S N  (corresponding to the digital conversion of the respective voltage analog value V y ) is outside the respective range of correct values between S N,min ′ and S N,max ′ (wherein S N,min ′ is the digital conversion of the respective V y,min  and S N,max ′ is the digital conversion of the respective V y,max ). 
       Example 9 
       [0138]    The failure is a short-circuit of at least one of the plurality of switches  66 ,  67 , . . .  68 ,  69 . For example, in case of a failure its detection is possible performing the test by closing at least another switch (not a failed one) selected among  66 ,  67 , . . .  68 ,  69 , in order to form a short-circuit of one or more resistors  61 ,  62 , . . .  64 ,  65 . In this last case the third voltage analog value V y  is outside the range of correct values between V y,min  and V y,max . Consequently, the digital value S N  (corresponding to the digital conversion of the third voltage analog value V y ) is outside the range of correct values between S N,min ′ and S N,max ′ (wherein S N,min ′ is the digital conversion of the respective V y,min  and S N,max ′ is the digital conversion of the respective V y,max ). 
       Example 10 
       [0139]    The failure is an open circuit of at least one of the plurality of switches  66 ,  67 , . . .  68 ,  69 . In this case, in the test mode the sampling capacitors  21 ,  22 , . . .  24 ,  25  are not charged to the expected value when the failed open-circuited switch (of the plurality of switches  66 ,  67 , . . .  68 ,  69 ) is closed. It is possible to determine the failure (and the position) of one of the plurality of switches  66 ,  67 , . . .  68 ,  69  by performing several iterations of the test mode of the operation of the analog-to-digital converter  101  in the following way. It is supposed that the digital-to-analog converter  60  includes four resistors  61 ,  62 ,  64 ,  65  and that the failed open-circuited switch is  67 . The following iterations of the test mode are performed, wherein the controller  50  generates, for each iteration, the configuration signal S 3  for performing the sequential closure of the switches  66 ,  67 ,  68 ,  69 :
       at the first iteration the switch  66  (connected to the resistor  61 ) is closed, and thus in the configuration phase the third voltage analog value V y =V t1  is sampled by the plurality of sampling capacitors  21 ,  22 , . . .  24 ,  25 . At the end of the phase of execution of the successive-approximation algorithm of the test mode the controller  50  detects that the digital value S N1  (corresponding to the digital conversion of V y1 ) is inside the range of the correct values, thus the switch  66  is not failed;   at the second iteration the switch  67  (connected to the resistor  62 ) is closed but (due to the failure of the open-circuited switch  67 ) in the configuration phase the third voltage analog value V y1  is not sampled by the plurality of sampling capacitors  21 ,  22 , . . .  24 ,  25 . In the hypothesis wherein the sampling capacitors  21 ,  22 , . . .  24 ,  25  keep the value of the charge sampled at the first iteration, the third voltage analog value V y =V y1  and the controller  50  still detects that the digital value is S N1  (equal to the previous step wherein the switch  66  is closed) and is outside the range of the correct values: this indicated that the switch  67  is failed.       
 
         [0142]    Preferably, the following other iterations are performed:
       at the third iteration the switch  68  (connected to resistor  64 ) is closed and in the configuration phase the third voltage analog value V y =V y3  is sampled by the plurality of sampling capacitors  21 ,  22 , . . .  24 ,  25 . At the end of the phase of execution of the successive-approximation algorithm of the test mode, the controller  50  detects that the digital value S N3  (corresponding to the digital conversion of V y3 ) is within the range of the correct values, thus the switch  68  is not failed;   at the fourth iteration, switch  69  (connected to resistor  65 ) is closed and during the configuration phase the third voltage analog value V y =V y4  is sampled by the plurality of sampling capacitors  21 ,  22 , . . .  24 ,  25 . At the end of the phase of execution of the successive-approximation algorithm of the test mode the controller  50  detects that digital value S N4  (corresponding to the digital conversion of V y4 ) is within the range of correct values, thus the switch  69  is not failed.       
 
       Example 11 
       [0145]    The failure is an open-circuit of the switch  35 . In this case, in the test mode the common terminal  2  of the sampling capacitors  21 ,  22 , . . .  24 ,  25  is floating and the sampling capacitors  21 ,  22 , . . .  24 ,  25  are connected to the parasitic capacitance (indicated with C p ) of the common terminal  2 . The plurality of sampling capacitors  21 ,  22 , . . .  24 ,  25  is charged through the parasitic capacitance C p  to the value (Vin−Vg)*C s *C p /(C s +C p ), wherein C s  is the value of the capacitance of the plurality of sampling capacitors  21 ,  22 , . . .  24 ,  25 , and Vg is the voltage applied to the terminal of C p  not connected to the common terminal  2 . 
         [0146]    Therefore at the end of the configuration phase of the test mode, the voltage of the common terminal  2  will have the value (Vin−Vg)*C p /(C s +C p ), which is different from the voltage of the common reference V cm . Therefore the third voltage analog value V y  is outside the range of the correct values between V y,min  and V y,max  and, consequently, the digital value S N  (corresponding to the digital conversion of the third voltage analog value V y ) is outside the range of the correct values. 
         [0147]    In the hypothesis wherein it occurs that (for a specific switch closed among the plurality of switches  66 ,  67 , . . .  68 ,  69 ), the value (V in −Vg)*C p /(C s +C p ) of the voltage of the common terminal  2  is really equal to the voltage of the common reference V cm , it is still possible to detect the open circuit failure of the switch  35  because the voltage of the common terminal  2  depends on the input voltage V in . Several iterations are performed in the test mode wherein the switches  66 ,  67 ,  68 ,  69  are alternatively closed and it is detected that in at least one iteration the third voltage analog value V y  is outside the range of correct values between V y,min  and V y,max  and, consequently, the digital value S N  (corresponding to the digital conversion of the third voltage analog value V y ) is outside the range of the correct values. 
       Example 12 
       [0148]    The failure is a short-circuit of the switch  35 . In this case, in the test mode the voltage value of the input terminal  37  of the comparator  31  is always equal to the reference voltage V cm  and the digital signal S N  has always the same value as the selected switch among the plurality of switches  66 ,  67 , . . .  68 ,  69  changes. Therefore it is possible to detect the short-circuit of the switch  35  by performing different iterations of the test mode in which it occurs the sequential closure of the switches  66 ,  67 ,  68 ,  69  in order to generate different values of the third voltage analog value V y  and checking that the digital value S N  (corresponding to the digital value of the third voltage analog value V y ) always keeps the same value as the selected switch among the plurality of switches  66 ,  67 , . . .  68 ,  69  changes. 
       Example 13 
       [0149]    The failure is a short-circuit of at least one of the sampling capacitors  21 ,  22 , . . .  24 ,  25 . In this case, in the test mode the voltage value of the common terminal  2  (and thus of the input terminal  37  of the comparator  31 ) is equal to the high reference voltage VrefH when, during the phase of execution of the successive-approximation algorithm on the plurality of sampling capacitors  21 ,  22 , . . .  24 ,  25 , a specific bit of the digital signal S N  is evaluated. Consequently, the comparator  31  generates a low logic value for this specific bit of the digital signal S N . Moreover, the voltage value of the common terminal  2  (and thus of the input terminal  37  of the comparator  31 ) is equal to the low reference voltage VrefL when, during the phase of execution of the successive-approximation algorithm on the plurality of sampling capacitors  21 ,  22 , . . .  24 ,  25 , the other bits of the digital signal S N  are evaluated. Consequently, the comparator  31  generates a high logic value for the other bits of the digital signal S N . 
         [0150]    In the case wherein there are no failures in the sampling capacitors  21 ,  22 , . . .  24 ,  25 , as the switch closed among the plurality of switches  66 ,  67 , . . .  68 ,  69  changes, the third voltage analog value V y  changes and thus the digital value S N  (corresponding to the digital conversion of the third voltage analog value V y ) changes. For example, if different iterations of the test mode are performed by successively closing the switches  66 ,  67 , . . .  68 ,  69 , the correct digital values S N  are “000000”, “000001”, “000010”, “000011”. 
         [0151]    In case wherein there is a short-circuit failure of at least one of the sampling capacitors  21 ,  22 , . . .  24 ,  25 , as the switch closed among the plurality of switches  66 ,  67 , . . .  68 ,  69  changes, the third voltage analog value V y  does not change and thus the digital value S N  (corresponding to the digital conversion of the third voltage analog value V y ) is always the same string having a low logic value and all the other values high (for example, “111110”, or “111101” or “111011”). This indicates the short-circuit failure of at least one of the sampling capacitors  21 ,  22 , . . .  24 ,  25 . 
       Example 14 
       [0152]    The comparator  31  is failed. This affects the digital value S N , which is outside the range of correct values comprised between S N,min ′ and S N,max ′. 
         [0153]      FIG. 4  also shows a third embodiment of the disclosure. According to the third embodiment, in the configuration phase of the test mode, the digital-to-analog converter  60  generates the third voltage analog value V y  (similarly to the configuration phase of the second embodiment of the disclosure), wherein the controller  50  generates the configuration signal S 3  for selecting the closure of one of the plurality of switches  66 ,  67 , . . .  68 ,  69 . In the configuration phase of the test mode, it is also performed the sampling of the third voltage analog value V y  on the plurality of sampling capacitors  21 ,  22 , . . .  24 ,  25  (similarly to the sampling of the input analog signal V in  in the sampling phase of the normal operation mode of the first embodiment of the disclosure). That is, the controller  50  generates the configuration signal S 3  for connecting the second terminals of the plurality of sampling capacitors  21 ,  22 , . . .  24 ,  25  to the third voltage analog value V y  and the controller  50  generates the switching signal S 2  for closing the switches  35 ,  36 . 
         [0154]    In the subsequent phase of the test mode the successive-approximation algorithm is carried out on the plurality of reference capacitors  41 ,  42 , . . .  44 ,  45  (similarly to the phase of execution of the successive-approximation algorithm of the first embodiment of the disclosure) connecting the second terminals of the plurality of reference capacitors  41 ,  42 , . . .  44 ,  45  to the low reference voltage VrefL′ or to the high reference voltage VrefH′, by means of the switches  46 ,  47 , . . .  48 ,  49  and the digital value S N  (corresponding to the digital conversion of the difference between the voltage signal S 106  at the common terminal  2  and the voltage signal S 107  at the common terminal  3 ) is obtained. If the digital value S N  has values in a range between S N,min ″ and S N,max ″ (wherein S N,min ″ is a known value corresponding to the digital conversion of the difference between the minimum correct value S 106   min  of the voltage signal S 106  and the value of the voltage signal S 107  and S N,max ″ is a known value corresponding to the digital conversion of the difference between the maximum correct value S 106   max  of the voltage signal S 106  and the value of the voltage signal S 107 ), the analog-to-digital converter  101  operates correctly, otherwise there is a failure in the analog-to-digital converter  101 . 
         [0155]    The operation of the analog-to-digital converter  101  in the configuration phase of the test mode according to the third embodiment of the disclosure differs from the operation in the configuration phase of the test mode according to the first embodiment of the disclosure in that:
       at time t 0  (see  FIG. 3 ) the output terminal  63  carrying the third voltage analog value V y  is connected to the second terminals of the sampling capacitors  21 ,  22 , . . .  24 ,  25 ;   times t 1  and t 2  have no equivalent in the third embodiment and are neglected;   at time t 3  the controller  50  generates the switching signal S 2 , which opens the switches  35  and  36 ;   from t 3  to t 4  it occurs the switching of the sampling capacitors  21 , 22  . . .  24 , 25  to the configuration related to the third voltage analog value V y  generated by the resistive-type digital-to-analog converter  60 .       
 
         [0160]    In the third embodiment any value of the third voltage analog value V y  has a correspondent correct value that is the result of the conversion of the third voltage analog value V y  in the condition of no failure inside the analog-to-digital converter  101  and ideal components composing the analog-to-digital converter  101 , according to the known operation of a successive-approximation algorithm. This result is a binary value corresponding to a configuration of the third generator  120  wherein (for example) bit ‘1’ is associated to one of the sampling capacitors  21 , 22  . . .  24 , 25  connected to the high reference voltage VrefH and bit ‘0’ is associated to one of the sampling capacitors  21 , 22  . . .  24 , 25  connected to the low reference voltage VrefL, with the weight of each bit in the binary word result corresponding to the weight of the related capacitor inside the third generator  120 . 
         [0161]    From time t 3  to t 4  the controller  50  applies the correct result to the third generator  120 . 
         [0162]    At time t 5  the difference between the voltage signal S 106  and the voltage signal S 107  is evaluated on the plurality of reference capacitors  41 ,  42 , . . .  44 ,  45 . In the ideal case the change of the voltage signal S 106  with respect to the voltage signal S 107  is negligible. In the real case the change of the voltage signal S 106  with respect to the voltage signal S 107  is not negligible and depends only on the tolerance of the sampling capacitors  21 , 22  . . .  24 , 25  and on the tolerance of the resistors  61 ,  62 ,  64 ,  65 , and the difference between the voltage signal S 106  and the voltage signal S 107  is evaluated with the successive-approximation algorithm carried out on the plurality of reference capacitors  41 ,  42 , . . .  44 ,  45 . In the real case if there are no failures or degradations of the components of the analog-to-digital converter  101 , the tolerance affecting the components causes a shift of the voltage signal S 106  with respect to the voltage signal S 107  that is not negligible, but which is known in case the tolerance of the components is known: this known tolerance leads to a maximum S 106   max  and minimum S 106   min  correct values for the voltage signal S 106  (like in the first embodiment of the disclosure, even if the two values S 106   max  and S 106   min  are different from S 6   max  and S 6   min  due to different components—the resistors  61 ,  62 ,  64 ,  65 —involved in the third embodiment and the different related tolerance) and the difference between the voltage signal S 106  and the voltage signal S 107 , which is evaluated with the successive-approximation algorithm carried out on the plurality of reference capacitors  41 ,  42 , . . .  44 ,  45 , is inside the range of correct values comprised between S N,min ″ and S N,max ″. On the contrary in the real case if there is a failure or degradation of a component of the analog-to-digital converter  101 , the difference between the voltage signal S 106  and the voltage signal S 107 , which is evaluated with the successive-approximation algorithm carried out on the plurality of reference capacitors  41 ,  42 , . . .  44 ,  45 , is outside the range of correct values comprised between S N,min ″ and S N,max ″. 
         [0163]    The third embodiment of the disclosure has the advantage that the range used for checking in the test mode the correct operation of the analog-to-digital converter  101  is always the same as the third voltage analog value V y  generated by the digital-to-analog converter  60  at the output terminal  63  changes. 
         [0164]    Steps b, d, g, and h of the method can be performed by a software program running on a microprocessor (the controller  50 ), which can be a separate microprocessor or can be a microprocessor inside a specific or programmable integrated circuit (for example, a FPGA=Field Programmable Gate Array). The programming language used for the program software could be, for example, C or VHDL (Very high-speed integrated circuit Hardware Description Language) or Verilog. 
         [0165]    The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent application, foreign patents, foreign patent application and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, application and publications to provide yet further embodiments. 
         [0166]    These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.