Abstract:
A sense amplifier circuit includes a latch circuit to enhance the speed of a sensing operation and to obviate the need for a latch circuit to capture the output value of the sense amplifier circuit. In one embodiment, first and second differential amplifiers provide a differential signal to the latch circuit. The high gain in the latch circuit resolves the differential signal to a logic signal, which is then provided to an output amplifier. In one embodiment, the differential signal is provided to the latch circuit after the differential signal across the input terminals of the first and second differential amplifiers exceeds a predetermined value.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a design for a sense amplifier used in a memory circuit. In particular, the present invention relates to a design for sense amplifiers used in a memory circuit, such as a flash memory circuit.  
           [0003]    2. Discussion of the Related Art In a memory circuit, e.g., a non-volatile floating gate memory circuit (“flash” memory circuit), a sense amplifier circuit is shared by numerous memory cells for sensing their stored logic values. Typically, to sense the logic value stored in a memory cell, the output terminal of the memory cell is selectively coupled to an input terminal of the sense amplifier circuit, which amplifies the voltage received at the input terminal to provide a logic signal output that represents the stored logic value. This output logic signal is typically stored into a latch circuit external to the sense amplifier circuit. Typically, because a memory cell represents the logic value stored by the presence or the absence of a small amount of electrical charge, the memory circuit has little drive capability. Consequently, the sense amplifier circuit is required to have a high gain to allow it to amplify the signal provided by this small amount of electric charge into an output signal of conventional signal levels that can be processed in a conventional logic circuit. To achieve high performance, the output signal is required to settle rapidly. More recently, sense amplifier circuits are also designed with low power dissipation as a design goal. Thus, numerous design challenges are presented by a sense amplifier circuit.  
         SUMMARY  
         [0004]    According to the present invention, a sense amplifier receives an input signal and a reference signal to provide a latched logic output signal, thereby obviating the need for a latch circuit external to the sense amplifier, as is required in the prior art. The latched output logic signal is achieved by incorporating a high gain latch circuit which is capable of resolving an analog differential signal to a logic signal at high speed.  
           [0005]    According to one embodiment of the present invention, the sense amplifier includes first and second differential amplifiers, a latch circuit and an output amplifier. The first and second differential amplifiers each receive an input signal and a reference signal corresponding, for example, to the output signals of a selected cell in a memory array and a reference cell. From the input signal and the reference signal, the first and second differential amplifiers provide a differential signal across their respective output terminals. This differential signal represents, for example, an amplified difference in voltage across the input signal and the reference signal. The high gain in the latch circuit then resolves the differential signal to provide as output a logic signal and its complement. The output amplifier then amplifies these logic signals to the desired voltage levels.  
           [0006]    According to one implementation, the sense amplifier circuit is powered down until a sensing operation is required (e.g., during a memory read access, after an address decoder completes decoding a memory address). During the sensing operation, the first and second amplifiers are powered up before the latch circuit and the output amplifier are powered up. In one implementation, switches allow the first and second differential amplifiers to set the bias in the latch circuit as the latch circuit powers up and isolate the latch circuit from the first and second differential amplifying while the differential signal develops.  
           [0007]    The sense amplifier circuit can include a reset circuit that resets selected terminals in the latch circuit and at input terminals to predetermined voltages. In one embodiment, the reset circuit presets the selected terminals to known voltage references prior to the latch circuit powering up. By setting these selected terminals to the known voltages, transients or charge from previous sensing operations are prevented from interfering with the current sensing operation.  
           [0008]    In one embodiment, a quiescent circuit sets a quiescent voltage in the terminals receiving the input signal and the reference signal, and a switch circuit equalizes the quiescent voltages in these terminals prior to the time when the input signal and the reference signal are coupled onto the receiving terminals.  
           [0009]    In one embodiment, a bias circuit provides a bias voltage to operate the current sources in the first and second differential amplifiers. To speed up the rate at which the bias voltage is attained upon powering, a control signal and its logic complement are provided to the bias circuit with a predetermined delay between corresponding logic transitions. As the control signal and its complement control two current paths that affect the bias voltage in one implementation, the predetermined delay allows both current paths to be conducting at the same time during that delay, thereby reducing the time required for the bias voltage to reach its steady state value.  
           [0010]    The present invention is better understood upon consideration of the detailed description below and the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    [0011]FIG. 1 is a functional schematic diagram showing sense amplifier circuit  100 , in accordance with one embodiment of the present invention.  
         [0012]    [0012]FIG. 2 is a timing diagram showing transitions of selected control signals over an exemplary sensing operation, according to one embodiment of the present invention.  
         [0013]    [0013]FIGS. 3 and 4 show, respectively, differential amplifier circuits  300  and  400 , suitable for implementing either one of differential amplifier circuits  103  and  102  of FIG. 1.  
         [0014]    [0014]FIG. 5 shows bias circuit  500 , suitable for implementing bias circuit  104  of FIG. 1.  
         [0015]    [0015]FIG. 6 shows latch circuit  600 , suitable for implementing latch  109  of FIG. 1.  
         [0016]    [0016]FIG. 7 shows differential amplifier circuit  700 , suitable for implementing differential amplifier  112  of FIG. 1.  
         [0017]    [0017]FIG. 8 shows control circuits  800  and  850 , suitable for generating numerous control signals shown in FIG. 1.  
         [0018]    [0018]FIG. 9 shows quiescent circuit  900  suitable for use in adjusting a quiescent voltage on terminals  110  and  111  of FIG. 1.  
         [0019]    To facilitate cross-referencing among the figures, in these figures, like reference numerals are assigned to like features. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0020]    The present invention provides a sense amplifier circuit which is illustrated by reference to functional schematic diagram of FIG. 1. As shown in FIG. 1, sense amplifier circuit  100  receives input signals IO_SA and IO_REF at terminals  110  and  111 , respectively. Signals IO_REF and IO_SA are output signals on the bit lines of a selected memory cell and a reference cell, respectively. Typically, an address decoder circuit selects the memory cell to provide signal IO_SA at terminal  111 . Prior to a sensing operation by sense amplifier circuit  100 , quiescent circuit  113  (not shown) is turned on to provide a quiescent voltage to terminals  110  and  111 , so that the stored value in the selected memory cell may appear as a change in voltage from this quiescent voltage. To avoid any pre-existing offset voltage between terminals  110  and  111  immediately prior to the receipt of output signals of the selected memory cell and the reference cell, a transmission gate  101  is turned on momentarily.  
         [0021]    Upon coupling the output signals of the reference cell and the selected memory cell to terminals  110  and  111  respectively, a voltage difference begins to develop across signals IO_REF and IO_SA. Typically, signal IO_REF from the reference cell can develop to about 10 millivolts. Depending on the stored value in the selected memory cell, signal IO_SA may be about 0 volts or about 20 millivolts, so that that the voltage difference across terminals  110  and  111  is approximately ±10 millivolts. This voltage difference is amplified by differential amplifiers  102  and  103 , which provides a differential signal (formed by signals N OUT  and P OUT ) across terminals  114  and  115 . Typically, when fully developed, the differential signal has a magnitude of about ±80 millivolts. Differential amplifiers  102  and  103  receives bias signal COMPBIAS from bias circuit  104 , which enables (i.e., powers up) differential amplifiers  102  and  103  and sets the current level of their internal current sources. In addition, control signal EQ 1  holds the output signals at terminals  114  and  115  to ground, until shortly before latch circuit  109  powers up. In addition, control signal EQ 0  resets the internal nodes of latch circuit  109  prior to latch  109  powering up, to remove any residual charge in latch  109  from a previous sensing operation.  
         [0022]    As the differential signal across input terminals  110  and  111  develops, the differential signal across the output terminals of differential amplifiers  102  and  103  are held at ground voltage, until control signal EQ 1  is asserted, which also renders isolation transistors  105  and  106  conducting. At this time, differential signal across terminals  114  and  115  settles rapidly because signals at input terminals  110  and  111  are substantially developed, thus setting the bias for latch  109 . A short time later, when latch  109  powers up, the bias voltage across terminals  107  and  108  drive latch  109  into a definite state, thereby avoiding any undesirable transient responses that some times occur in the metastable cross-coupled circuit of latch  109 . Consequently, latch  109  can provide a differential output logic signal across terminals  116  and  117  without rapidly and without undesirable transient effects. Further, because isolation transistors  105  and  106  can have relatively large on-resistance (e.g., time constant of 3 ns), a high impedance is presented to differential amplifiers  102  and  103 , while the differential signal across terminals  114  and  115  develops. Because isolation transistors  105  and  106  are turned off between sensing operations, latch  109  retains the output value from the last sensing operation. Thus, the need for a latch circuit external to sense amplifier circuit  100  is obviated.  
         [0023]    Shortly after latch  109  is powered up, differential amplifier  112  is also powered up to amplify and to convert the differential logic signal across terminals  116  and  117  into a single-ended signal SAOUT at terminal  118 .  
         [0024]    Exemplary implementations of differential amplifiers  102  and  103 , bias circuit  104 , latch  109  and differential amplifier  112  are shown in detail in FIGS. 3-7. An exemplary sensing operation is illustrated by these implementations in conjunction with the control signals in the timing diagram of FIG. 2. FIG. 2 is a timing diagram showing transitions of selected control signals over an exemplary sensing operation, according to one embodiment of the present invention. As shown in FIG. 2, the beginning of a sensing operation is triggered by an assertion of control signal ATD (“address transition detect”) at time t 0 , whereupon enable signal SAEN 2  is deasserted. Deassertion of signal SAEN 2  results in enable signals SAEN 3  and SAEN 4 , which enable latch  109  and amplifier  112 , respectively, also being deasserted. FIG. 8 shows control circuit  800 , which can be used to generate control signals SAEN 3 , SAEN 4 , and their respective complementary signals SAEN 3 b and SAEN 4 b, using a string of inverters  801 - 805 . As shown in FIG. 8, complementary control signal pairs SAEN 3  and SAEN 3   b  and SAEN 4  and SAEN 4   b  can be made to have transitions that are offset from each other by an adjustable or programmable amount. In FIG. 8, the programmable timing offset can be achieved by selectively including optional inverters  806  and  807  in the inverter chain. FIG. 2 also shows output enable signal OUTEN which controls one or more output buffers of sense amplifier circuit  100  also being deasserted.  
         [0025]    As mentioned above, FIGS. 6 and 7 show, respectively, latch circuit  600  and differential amplifier circuit  700 , suitable for implementing latch  109  and differential amplifier  112  of FIG. 1. As shown in FIG. 6, latch circuit  600  is coupled to a power supply signal (VDD) and a ground supply signal (VSS) by PMOS transistor  601  and NMOS transistor  602 , respectively. Control signal SAEN 3  and its complement signal SAEN 3   b  control NMOS transistor  602  and PMOS transistor  601 , respectively. Thus, when control signal SAEN 3  is deasserted, latch circuit  600  is powered down. Similarly, in FIG. 7, control signal SAEN 4  and its complementary signal SAEN 4   b  control connection of differential amplifier circuit  700  with respective ground and power supply signals VSS and VDD. Thus, when control signal SAEN 4  is deasserted, differential amplifier circuit  700  is powered down  
         [0026]    Signal ATD stays asserted until time t 1 . When signal ATD is deasserted, the falling edge of signal ATD triggers a pulse in control signal EQ at time t 2 . Control signal EQ can be used to generate complementary control signals LOCEQ and LOCEQb to turn on switch  101  of FIG. 1 to equalize the quiescent voltages on, for example, terminals  110  and  111 . The quiescent voltages on terminals  110  and  111  can be set, for example, by circuit  900 . FIG. 9 shows circuit  900 , including quiescent circuits  900   a  and  900   b , suitable for setting the quiescent voltages at terminals  907   a  and  907   b , respectively. Terminals  907   b  and  907   a  are selectively coupled to output terminals of a selected memory cell and a reference cell, respectively. Operations of circuits  900   a  and  900   b  are substantially identical. Initially, complementary control signals LOCBIASb and LOCBIAS are asserted to power up circuit  900   a  by enabling connections to respective power and ground supply signals through PMOS transistor  901   a  and NMOS transistor  906   a . The relative on-resistances of NMOS transistors  902   a  and  905   a  —determined by appropriately sizing of these transistors—act as a voltage divider to provide a desired quiescent voltage at terminal  907   a . This quiescent voltage can be programmable by selectively switching on parallel transistors, such as transistors  903   a  and  904   a , to vary the effective relative resistances in the voltage divider. In one embodiment, this method is used to provide different quiescent voltages according to the magnitude of a detected supply voltage (e.g., 3 volts vs. 5 volts). Complementary control signals LOCEQ and LOCEQb render switch  908  conductive momentarily to equalize the quiescent voltages at terminals  907   a  and  907   b  before these terminals are coupled to the output terminals of the reference cell and the selected cell, respectively.  
         [0027]    Referring back to FIG. 2, the falling edge of the pulse in signal EQ at time t 3  triggers assertion of control signals SAEN 1  and EQ 0  at time t 4 . According to one embodiment, as shown in control circuit  850  of FIG. 8, complementary control signal SAEN 1 b is asserted after a predetermined delay. This predetermined delay is used in bias circuit  500  of FIG. 5 to provide bias voltage COMPBIAS, such as used in differential amplifiers  102  and  103  of FIG. 1. In FIG. 5, prior to control signal SAEN 1  being asserted, PMOS transistor  501   b  is conducting, so that transistor  501   b  pulls terminal  505  to supply voltage VDD. When control signal SAEN 1  is asserted in response, for example, to a falling edge of control signal EQ, PMOS transistor  501   b  is turned off, and NMOS transistor  502  becomes conducting, so that a current path is now formed by current source PMOS transistor  501   a , and NMOS transistors  502  and  503 . During the predetermined delay in the corresponding transitions of complementary control signals SAEN 1  and SAEN 1   b,  NMOS transistors  502  and  504  are simultaneously conducting, thus rapidly establishing bias voltage COMPBIAS.  
         [0028]    Referring to circuit  850  of FIG. 8, control signal SIGDLP, which is asserted when output terminals of the selected memory cell and the reference cell are respectively coupled to terminals  111  and  110  of FIG. 1, causes control signal EQ 0  to be asserted between times t 4  and t 5 . In the meantime, control signal EQ 1  remains at its high voltage. Referring to FIG. 3, in differential amplifier circuit  300 , the high voltage in control signal EQ 1  holds NMOS transistors  301   a  and  301   b  at a conducting state, thereby ensuring that terminals  302   a  and  302   b  in the two current paths of current source  303  (formed by PMOS transistors  303   a  and  303   b ) are equalized at ground supply voltage. The settling of bias signal COMPBIAS from the power supply voltage to the predetermined bias voltage turns on current source  303 . The current in current source  303  flows in two current paths formed respectively by PMOS transistor  304   a  and NMOS transistor  305   a , and PMOS transistor  304   b  and NMOS transistor  305   b . At time t 6 , when control signal EQ 1  goes to a low or ground voltage, the differential signal across terminals  111  and  110  modulate the relative transconductances of PMOS transistors  304   a  and  304   b , so that the output voltage at terminal  302   b  reflects the relative voltages at terminals  110  and  111 , respectively. The operation of differential amplifier circuit  400  of FIG. 4 is substantially similar to the operation of differential amplifier  300  of FIG. 3 described above, except that the relative polarity of the input differential signal of FIG. 3 is reversed from that of FIG. 4. To minimize repetition, a detailed description of the operation of differential amplifier  400  of FIG. 4 is therefore omitted.  
         [0029]    [0029]FIG. 6 shows latch circuit  600 , which is suitable for implementing latch  109  of FIG. 1 and incorporates PMOS transistors  105  and  106 . Latch circuit  600  stores a data signal in a latch formed by two cross-coupled inverters (i.e., inverters formed respectively by PMOS transistor  604   a  and NMOS transistor  605   a  and PMOS transistor  604   b  and NMOS transistor  605   b ). Referring back to circuit  850  of FIG. 8 and FIG. 2, as discussed above, signal EQ 0  is asserted between times t 4  and t 5 , thereby pulling terminals  116 ,  117  and  606  and  607  to ground supply voltage, prior to circuit  600  being powered up when control signal SAEN 3  and SAEN 3   b  are asserted at time t 8 . (Terminals  606  and  607  provides connections to power and ground supply voltages via PMOS transistor  601  and NMOS transistor  602 ). In this embodiment, while the differential output signal of latch circuit  600  at terminals  116  and  117  is developing, the output voltage of differential amplifier  112  is at a logic high voltage, because of a precharge operation.  
         [0030]    As shown in circuit  850  and FIG. 2, subsequent to control signals SIGDLP and SAEN 1  are both asserted, control signal EQ 1  goes to a low voltage at time t 6 , so that PMOS transistors  105  and  106  become conducting, while at the same time allowing a differential signal to develop across terminals  114  and  115  and across input terminals  107  and  108 . As shown in circuit  800  of FIG. 8 and FIG. 2, control signal SAEN 2  causes SAEN 3  to be asserted at time t 8 , thereby powering up latch circuit  600 . At this time, the differential signal across terminals  114  and  115  is substantially developed. As a result, the high gain of latch circuit  600  resolves the differential output signal across terminals  116  and  117  to a definite state very rapidly. Further, as differential amplifier  112  is precharged to a logic high voltage, the output voltage of differential amplifier  112  is resolved to the final logic value without undesirable transient signal fluctuations, as is common in prior art sense amplifier output signals.  
         [0031]    [0031]FIG. 7 shows differential amplifier circuit  700 , which is suitable for implementing differential amplifier  112 . Referring to FIGS. 2, 8 and  7 , at time t 9 , control signals SAEN 4  and SAEN 4 b are asserted. Thus PMOS transistor  701  and NMOS transistor  702  become conducting, thus powering up differential amplifier circuit  700 . Asserted control signal SAEN 4  also turns off PMOS transistors  705   a  and  705   b , which has precharged the output voltage at terminal  706  to the logic high voltage. As differential amplifier circuit  700  powers up, the current in PMOS transistor  701  is divided into the two current paths formed by PMOS transistor  704   b  and NMOS transistor  704   b , and PMOS transistor  704   a  and NMOS transistor  704   a . When differential amplifier circuit  700  powers up, the voltages on terminals  116  and  117 , which may not be fully developed to the logic voltage levels, provides a bias to the input terminals of differential amplifier circuit  700 . The relative magnitudes of the currents in these current paths depend on the differential voltage across terminals  116  and  117 . If the voltage at terminal  116  is higher than the voltage at terminal  117 , the output voltage at terminal  706  is pulled to logic low (i.e., ground). Conversely, the output voltage at terminal  706  remains at logic high. Inverters  707  and  708  further amplify and translate the voltage of output signal SAOUT at terminal  709  to full CMOS logic voltage levels.  
         [0032]    Accordingly, a sense amplifier of high performance and low power dissipation is achieved. The propagation of bias voltages from differential amplifiers  102  and  103  to latch  109 , and then further to differential amplifier  112  provides noise immunity and fast settling of the output signal to the final output value.  
         [0033]    The above detailed description is provided to illustrate the specific embodiments of the present invention and is not intended to be limiting. Numerous modifications and variations within the scope of the present invention are possible. The present invention is set forth in the following claims.