Abstract:
An average value calculating circuit comprises capacitors C 1  to Cn with one end of each capacitor supplied with reference voltage VSS, switching elements SW 11  to SW 1 n connected between inputs D 1  to Dn and the other ends of capacitors C 1  to Cn, respectively, common wiring COM, switching elements SW 21  to SW 2 n connected between the other ends of capacitors C 1  to Cn and common wiring COM and resetting switching element SWr with one end connected to common wiring COM and the other end supplied with reference voltage VTT. When one of a group consisting of switching elements SW 11  to SW 1 n and SWr and another group consisting of switching elements SW 21  to SW 2 n is on, the others are off, substantially.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an average value calculating circuit, and a correlation value calculating circuit, a matched filter and a communication device using the same. 
     2. Description of the Related Art 
     FIG. 8 is a schematic block diagram showing a prior art receiver for direct sequence (DS) spread spectrum communication. 
     A signal received by antenna  7  selectively passes through band-pass filter  8  and is provided to detecting circuit  9 . Detecting circuit  9  performs envelope or synchronous detection of the signal modulated according to ASK, FSK or PSK and converts it into analog or digital spread spectrum signal DIN. Matched filter  10 P calculates correlation value DOUT between spread spectrum signal DIN and a pseudorandom noise (PN). Determining circuit  11  determines the symbol duration for acquisition based on correlation value DOUT and obtains baseband data. To reduce the amount of data, if the baseband data are coded, for example, according to predictive coding, the baseband data are decoded by decoding circuit  12 . In the case of sound data, the output of decoding circuit  12  is converted into an analog value by digital-to-analog converter circuit  13 , and then, passes through low-pass filter  14  and is provided to speaker  15 . In the case of data such as image or text data, the output of the decoding circuit  12  is used as reproduction data. 
     The spread spectrum communication using such a receiver is superior to other communication schemes in interference wave excluding capability, concealability of the contents of communication and frequency use efficiency. 
     FIG. 9 shows the construction of conventional matched filter  10 P. 
     In digital or analog shift register  20 , delay elements DL 1  to DLn are cascaded. To the data input of delay element DL 1 , spread spectrum signal DIN is provided. In synchronization with clock CLK, input signals DIN and S 1  to Sn-i of delay elements DL 1  to DLn are held therein and they output delay signals S 1  to Sn. Delay elements DL 1  to DLn are flip-flops if spread spectrum signal DIN is digital, and are sample-and-hold circuits or CCDs, etc. if the spread spectrum signal DIN is analog. 
     Coincidence degrees D 1  to Dn between pseudorandom noise P 1  to Pn and delay signals S 1  to Sn are calculated by coincidence degree calculating circuits M 1  to Mn, respectively. Coincidence degree calculating circuits M 1  to Mn are, for example, multipliers if pseudorandom noise is 1 or −1, and are exclusive NOR gates if pseudorandom noise is a bit of ‘1’ or ‘0.’ Coincidence degrees D 1  to Dn are provided to adder circuit  21  and the sum total thereof is obtained as correlation value DOUT. 
     With such matched filter  10 P, correlation value DOUT is immediately obtained every clock period. 
     Pseudorandom noises vary from receiver to receiver. When the pseudorandom noise on the receiving side differ from that on the transmitting side, correlation value DOUT is always low, so that the received data cannot be decoded. 
     For example, for n=256, it is necessary to calculate the sum total of coincidence degrees D 1  to D 256  in one period of clock CLK. Consequently, construction of adder circuit  21 , the correlation value calculating circuit, the matched filter and the communication device is complicated. 
     SUMMARY OF THE INVENTION 
     Accordingly, an object of the present invention is to provide an average value calculating circuit having a simpler construction, and a correlation value calculating circuit, a matched filter and a communication device using the same. 
     In the 1st aspect of the present invention, as shown in FIG. 1 for example, there is provided an average value calculating circuit comprising: a plurality of capacitors C 1  to Cn and a switching circuit  23  for sampling and holding charges corresponding to input signals D 1  to Dn to the capacitors C 1  to Cn respectively, and for connecting the capacitors C 1  to Cn in parallel while isolating the input signals D 1  to Dn to output average value corresponding to average voltage of the capacitors C 1  to Cn connected in parallel. 
     Defining that the voltages of the capacitors C 1  to Cn are V 1  to Vn when the charges corresponding to the input signals D 1  to Dn are held at the capacitors C 1  to Cn and that the voltages of the capacitors C 1  to Cn are DOUT when the capacitors are connected in parallel, since the sum total of the charges held in the capacitors C 1  to Cn is invariant before and after the parallel connection, the following equation holds: 
     
       
         C 1 ·V 1 +C 2 ·V 2 + . . . +Cn·Vn=(C 0 +C 1 + . . . +Cn)DOUT  
       
     
     DOUT is a weighted average value of voltages V 1  to Vn corresponding to the input signals D 1  to Dn with the weights of voltages V 1  to Vn being C 1  to Cn, respectively. 
     According to the 1st aspect of the present invention, since the average value calculating circuit is constituted by capacitors C 1  to Cn and switching circuit  23 , the construction is simpler than before. Thus, the present invention contributes to reduced manufacture cost of the average value calculating circuit, and the correlation calculating circuit, the matched filter and the communication device using the same. 
     In the 2nd aspect of the present invention, there is provided an average value calculating circuit as defined in the 1st aspect, wherein one end of each of the capacitors is supplied with a first reference potential, and wherein the switching circuit comprises: a plurality of first switching elements, each connected between a corresponding one of the inputs for receiving the input signals and the other end of a corresponding one of the capacitors; a common conductor; a plurality of second switching elements each connected between the other end of the corresponding one of the capacitors and the common conductor; and a resetting switching element with its one end connected to the common conductor and its other end supplied with a second reference potential, wherein when one of a first group consisting of the first switching elements and the resetting switching element, and a second group consisting of the second switching elements is on, the other thereof is off, substantially. 
     The 2nd reference potential may be equal to the 1st reference potential. 
     In the 3rd aspect of the present invention, there is provided an average value calculating circuit as defined in the 2nd aspect, wherein the capacitors comprise: a plurality of first capacitor elements each with its one end supplied with the first reference potential, its other end thereof being the other end of one of the capacitors; a plurality of second capacitor elements each with its one end supplied with a third reference potential; and a plurality of third switching elements each connected between the other end of the corresponding one of the first capacitor elements and the other end of corresponding one of the second capacitor elements. 
     The 3rd reference potential may be equal to the 1st reference potential. 
     According to the 3rd aspect of the present invention, by controlling on/off of the 3rd switching elements, the weights of the weighted average become variable. 
     In the 4th aspect of the present invention, there is provided a correlation value calculating circuit comprising: a coincidence degree calculating circuit for calculating degrees of coincidence between a parallel signal and a pseudorandom noise; a plurality of capacitors; and a switching circuit for sampling and holding charges corresponding to the degrees of coincidence to the capacitors and for connecting the capacitors in parallel while isolating the parallel signal to output average value corresponding to average voltage of the capacitors connected in parallel. 
     In the 5th aspect of the present invention, there is provided a matched filter comprising: a shift register having a plurality of cascaded delay elements, a first stage of the delay elements receiving a spread spectrum signal, the delay elements being clocked by a clock signal to provide a parallel signal from outputs thereof; a coincidence degree calculating circuit for calculating degrees of coincidence between the parallel signal and a pseudorandom noise; a plurality of capacitors; and a switching circuit for sampling and holding charges corresponding to the degrees of coincidence to the capacitors and for connecting the capacitors in parallel while isolating the parallel signal to output average value corresponding to average voltage of the capacitors connected in parallel. 
     In the 6th aspect of the present invention, there is provided a matched filter as defined in the 5th aspect, wherein each of the delay elements is a flip-flop, and wherein the coincidence degree calculating circuit comprises exclusive OR gates or exclusive NOR gates, each receiving a bit of the parallel signal and a bit of the pseudorandom noise. 
     In the 7th aspect of the present invention, there is provided a matched filter as defined in the 5th aspect, wherein each of the delay elements is a sample-and-hold circuit, and wherein the coincidence degree calculating circuit comprises multiplier circuits each receiving a single signal of the parallel signal and a digit of the pseudorandom noise. 
     In the 8th aspect of the present invention, there is provided a matched filter comprising: a shift register having a plurality of cascaded delay elements, a first stage of the delay elements receiving a spread spectrum signal, the delay elements being clocked by a clock signal to provide a parallel signal from outputs thereof; a coincidence degree calculating circuit for calculating degrees of coincidence between the parallel signal and a pseudorandom noise; a plurality of capacitors each having one end supplied with a first reference potential; a plurality of first switching elements each connected between the output of a corresponding one of the delay elements and the other end of a corresponding one of the capacitors; a common conductor; a plurality of second switching elements connected between the other end of a corresponding one of the capacitors and the common conductor; and a resetting switching element with its one end connected to the common conductor and its other end supplied with a second reference potential; wherein the capacitors comprise: a plurality of first capacitor elements each with its one end supplied with the first reference potential the, other end thereof being the other end of a corresponding one of the capacitors; a plurality of second capacitor elements each with its one end supplied with a third reference potential; and a plurality of third switching elements each connected between the other end of a corresponding one of the first capacitor elements and its other end of a corresponding one of the second capacitor elements, wherein when one of a first group consisting of the first switching elements and the resetting switching element, and a second group consisting of the second switching elements is on, the other thereof is off, substantially, and wherein the third switching elements are controlled by weight data. 
     In the 9th aspect of the present invention, there is provided a multi-bit matched filter receiving a multi-bit stream of a spread spectrum signal and including matched filters, each of the matched filters comprising: a shift register having a plurality of cascaded delay elements, a first stage of the delay elements receiving one bit stream of the multi-bit stream, the delay elements being clocked by a clock signal to provide a parallel signal from outputs thereof; a coincidence degree calculating circuit for calculating degrees of coincidence between the parallel signal and part of a pseudorandom noise; a plurality of capacitors; and a switching circuit for sampling and holding charges corresponding to the degrees of coincidence to the capacitors and for connecting the capacitors in parallel while isolating the parallel signal to output average value corresponding to average voltage of the capacitors connected in parallel, as a correlation value from a correlation value output. 
     According to the 9th aspect of the present invention, since it is only necessary to connect the correlation output of the matched filters to a common conductor, the construction of a multi-bit matched filter can be simplified. 
     In the 10th aspect of the present invention, there is provided a multi-bit matched filter as defined in the 9th aspect, wherein a capacitance of each of the capacitors within a jth matched filter is twice a capacitance of each of the capacitors within a (j−1)th matched filter for each j of 2 to m, where 1st to mth matched filters construct the matched filters of the multi-bit matched filter, and the multi-bit matched filter further comprising a common conductor to which the correlation value outputs of the 1st to mth matched filters are connected. 
     In the 11th aspect of the present invention, there is provided a multi-bit matched filter as defined in the 9th aspect, further comprising a weighted average calculating circuit for calculating a weighted average of the correlation values output from the matched filters in such a way that a weight for a correlation value output from a jth matched filter is twice a weight for a correlation value output from a (j−1)th matched filter for each j of 2 to m, where 1st to mth matched filters construct the matched filters of the multi-bit matched filter. 
     According to the 11th aspect of the present invention, matched filters having the same construction can be used. 
     In the 12th aspect of the present invention, there is provided a multi-bit matched filter as defined in the 11th aspect, wherein the weighted averaged calculating circuit comprises: 1st to mth analog-to-digital converter circuits each connected at its input to an output a of corresponding one of the 1st to mth matched filters; 1st to (m−1)th multiplier circuits each connected to an output a of corresponding one of the 2nd to mth analog-to-digital converter circuits, the 1st to (m−1)th multiplier circuits multiplying outputs of the 2nd to mth analog-to-digital converter circuits by k 2  to km, respectively; and an adder circuit for calculating a sum total of an output of the 1st analog-to-digital converter circuit and outputs of the 2nd to mth multiplier circuits, wherein a ratio rj=kj/(resolution of a jth analog-to-digital converter circuit) is twice a ratio r(j−1) for each of j=2 to m. 
     According to the 12th aspect of the present invention, by using 2nd to mth multiplier circuits, 2nd to mth analog-to-digital converter circuits having comparatively low resolution can be used. 
     In the 13th aspect of the present invention, there is provided a communication device including a matched filter, the matched filter comprising: a shift register having a plurality of cascaded delay elements, a first stage of the delay elements receiving a spread spectrum signal, the delay elements being clocked by a clock signal to provide a parallel signal from outputs thereof; a coincidence degree calculating circuit for calculating degrees of coincidence between the parallel signal and a pseudorandom noise; a plurality of capacitors; and a switching circuit for sampling and holding charges corresponding to the degrees of coincidence to the capacitors and for connecting the capacitors in parallel while isolating the parallel signal to output average value corresponding to average voltage of the capacitors connected in parallel. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a matched filter showing a principal construction of the present invention; 
     FIG. 2 is a circuit diagram of a matched filter according to a first embodiment of the present invention; 
     FIG. 3 is a time chart showing an operation of the circuit of FIG. 1; 
     FIG. 4 is a circuit diagram of a matched filter according to a second embodiment of the present invention; 
     FIG. 5 is a circuit diagram of a matched filter according to a third embodiment of the present invention; 
     FIG. 6 is a circuit diagram of a matched filter according to a fourth embodiment of the present invention; 
     FIG. 7 is a circuit diagram of a matched filter according to a fifth embodiment of the present invention; 
     FIG. 8 is a block diagram showing a schematic construction of a conventional receiver for direct sequence spread spectrum communication; and 
     FIG. 9 is circuit diagram of a conventional matched filter. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to the drawings, wherein like reference characters designate like or corresponding parts throughout several views, preferred embodiments of the present invention are described below. 
     First Embodiment 
     FIG. 2 shows matched filter  10 A according to a first embodiment of the present invention. Matched filter  10 A is used, for example, instead of matched filter  10 P of FIG.  8 . Matched filter  10 A is a structural example of FIG.  1  and is used in the case that spread spectrum signal DIN is a bit stream. For simplicity in FIG. 2, n of FIG. 1 is equal to 5. 
     In shift register  20 A, D flip-flops DL 1 A to DL 5 A are cascaded and clocked by clock CLK. To data input D of D flip-flop DL 1 A in the first stage, spread spectrum signal DIN is provided. Outputs S 1  to S 5  of D flip-flops DL 1 A to DL 5 A are provided to one input of exclusive NOR gates M 1 A to M 5 A. To the other input of exclusive NOR gates M 1 A to M 5 A, pseudorandom noises P 1  to P 5  are provided from pseudorandom noise register  22 A. For example, if P 1 =S 1  then D 1 =1′, and if P 1 ≠S 1  then D 1 =‘0.’ Outputs D 1  to D 5  of exclusive NOR gate M 1 A to M 5 A represent degrees of coincidence of delay signals S 1  to S 5  with pseudorandom noises P 1  to P 5 . 
     Capacitors C 1  to C 5  have the same capacitance. One end of each of the capacitors C 1  to C 5  is connected to ground line GND. The other ends thereof are connected, on the one hand, through switching elements SW 11  to SW 15  to the outputs of exclusive NOR gates M 1 A to M 5 A and on the other hand, through switching elements SW 21  to SW 25  to common line COM. Between common line COM and ground line GND, switching element SWr for resetting common line potential is connected. Switching elements SW 11  to SW 15 , SW 21  to SW 25  and SWr constitute switching circuit  23  for capacitors C 1  to C 5 . 
     Switching elements SW 11  to SW 15  and SWr are on when clock *CLK is high, and are off when clock *CLK is low. Switching elements SW 21  to SW 25  are on when clock CLK which is complementary to clock *CLK is high, and are off when clock CLK is low. 
     Switching circuit  23  and capacitors C 1  to C 5  constitute an average value calculating circuit. The average value calculating circuit and exclusive NOR gates M 1 A to M 5 A constitute a correlation value calculating circuit. 
     Next, an operation of matched filter  10 A thus constructed will be described with reference to FIG.  3 . FIG. 3 shows a case where pseudorandom noise P 1  to P 5  is ‘01101’ and at time t=t 1 , spread spectrum signal DIN is ‘0’ and data of delay signals S 1  to S 4  is ‘1101.’ One cycle of clock CLK is called chip duration. Hereinafter, i of time ti will represent an odd number. 
     Spread spectrum signal DIN and delay signals S 1  to S 4  are held in flip-flops DL 1 A to DL 5 A at the rise timing (ti) of clock CLK, and the flip-flops output them as delay signals S 1  to S 5 . 
     For example, at time t=t 1 , data of delay signals S 1  to S 5  are changing to ‘01101’ and data of outputs D 1  to D 5  of exclusive NOR gates M 1 A to M 5 A are changing to ‘11111.’ At time t=t 3 , data of delay signals S 1  to S 5  are changing to ‘10110’ and data of outputs D 1  to D 5  of exclusive NOR gates M 1 A to M 5 A are changing to ‘00100.’ 
     At the rise of clock CLK, switching elements SW 11  to SW 15  and SWr are going to be turned off, and next switching elements SW 21  to SW 25  are going to be turned on. The voltages of capacitors C 1  to C 5  immediately therebefore are designated as V 1  to V 5 , respectively. Since the sum total of the charges held in capacitors C 1  to C 5  and common line COM is invariant before and after the rise of clock CLK, the equation 
     
       
         C 1 ·V 1 +C 2 ·V 2 +C 3 ·V 3 +C 4 ·V 4 +C 5 ·V 5 =(C 0 +C 1 +C 2 +C 3 +C 4 +C 5 ) DOUT   (1)  
       
     
     is satisfied, where C 0  represents the capacitance of common line COM. Assuming that capacitance C 0  is ignorable as against the sum total of the capacitances of capacitors C 1  to C 5 , correlation value DOUT is an average value of voltages V 1  to V 5  corresponding to coincidence degrees D 1  to D 5 , weighted with the capacitances of capacitors C 1  to C 5 . When capacitors C 1  to C 5  are equal to one another, correlation value DOUT is a mere average value of voltages V 1  to V 5 . That is, correlation value DOUT is an analog-converted value of the average of coincidence degrees D 1  to D 5  of one cycle before. 
     In FIG. 3, since correlation value DOUT is changing to the “maximum value” at time t=t 3  and t=13, after this change, determining circuit  11  of FIG. 8 determines that a duration from t 1  to t 11  of one cycle before is one symbol duration. The same determination is performed when correlation value DOUT is the “minimum value.” In addition, when correlation value DOUT is the “maximum value” or “minimum value”, determining circuit  11  determines that the baseband data in the one symbol duration is ‘1’ or ‘0’, respectively. In actuality, in consideration of mixing of noises and interference of received radio waves, a “value equal to or higher than a set value slightly lower than the maximum value” is used instead of the “maximum value”, and a “value equal to or lower than a set value slightly higher than the minimum value” is used instead of the “minimum value.” 
     At the rise timing (ti+1) of clock CLK, switching elements SW 21  to SW 25  are going to be turned off, and next, switching elements SW 11  to SW 15  and SWr are going to be turned on. After this, voltages corresponding to coincidence degrees D 1  to D 5  are sampled at capacitors C 1  to C 5 , respectively, and common line COM is reset to the ground potential. 
     According to the first embodiment, since an average value calculating circuit corresponding to adder circuit  21  of FIG. 9 is constituted by capacitors C 1  to C 5  and switching circuit  23 , the construction of the average value calculating circuit, and the correlation value calculating circuit, matched filter  10 A and the communication device using the same can be simpler than before. 
     Second Embodiment 
     In order to improve the capability of excluding interference waves in relation to the values of the pseudorandom noises, there is a case that each digit of the pseudorandom noise has two bits only on the receiving side. FIG. 4 shows matched filter  10 B according to a second embodiment of the present invention that takes such case into consideration. 
     In matched filter  10 B, capacitors C 1  to C 5  are connected through switching elements SW 31  to SW 35  to capacitors C 21  to C 25  in parallel, respectively. The capacitances of capacitors C 1  to C 5  and C 21  to C 25  are the same. 
     Each digit of the pseudorandom noise output from pseudorandom noise register  22 A has two bits. All the bits having the higher-order bit of each digit are provided as P 1  to P 5  to one input of exclusive NOR gates M 1 A to M 5 A, respectively, and all the bits of the lower-order bit of each digit are provided as Q 1  to Q 5  to the control input of switching elements SW 31  to SW 35 , respectively. 
     From the equation (1), correlation value DOUT is proportional to a weighted average value of coincidence degrees D 1  to D 5  and the weights are variable according to Q 1  to Q 5 . Assuming that the average value of the maximum value and the minimum value of correlation value DOUT is 0, if the digits P 1 Q 1  to P 5 Q 5  of the pseudorandom noise are ‘11’, ‘10’, ‘00’ and ‘01’, the weights are 1, 0.5, −0.5 and −1, respectively. 
     Third Embodiment 
     Spread spectrum signal DIN may be an analog voltage. FIG. 5 shows matched filter  10 C according to a third embodiment of the present invention in which filter  10 C takes this into consideration. 
     In analog shift register  20 B, sample-and-hold circuits DL 1 B to DLnB are cascaded. As the coincidence degree calculating circuits, multiplier circuits M 1 B to MnB are used. Pseudorandom noise P 1  to Pn output from pseudorandom noise holding circuit  22 B are all analog voltages corresponding to ‘1’ or ‘−1’. 
     Other features are the same as those of FIG.  2 . 
     Instead of sample-and-hold circuits DL 1 B to DLnB, CCDs may be used. 
     Fourth Embodiment 
     While spread spectrum signal DIN is a one-bit stream in the above-described embodiments, spread spectrum signal DIN may be a multi-bit stream. FIG. 6 shows matched filter  10 D according to a fourth embodiment of the present invention in which filter  10 D takes this into consideration. 
     It is assumed that spread spectrum signal DIN is a 4-bit stream of DIN 0  to DIN 3  and that DIN 0  is the least significant bit. Spread spectrum signals DIN 0  to DIN 3  are provided to matched filters  100  to  103 , respectively. Matched filters  100  to  103  all have the same construction as, for example, matched filter  10 A shown in FIG. 2, with the proviso that capacitances C of capacitors C 1  to C 5  of FIG. 2 are different among matched filters  100  to  103  and the capacitance ratio thereof is 1:2:4:8. 
     The correlation value output of matched filters  100  to  103  are all connected to the input of analog-to-digital converter circuit  24 . The input voltage of analog-to-digital converter circuit  24  is a weighted average value of the output voltages of matched filters  100  to  103  before the connection of the outputs. The weights are the above-mentioned capacitance ratio. From analog-to-digital converter circuit  24 , digital correlation value DOUT is taken out. 
     Fifth Embodiment 
     In FIG. 6, it is necessary that the capacitances of capacitors C 1  to C 5  shown in FIG. 2 in matched filter  100  for the least significant bit be a certain value or higher in consideration of a variation in parasitic capacitance. Moreover, since the capacitances of the capacitors are decided by the above-mentioned capacitance ratio, the areas occupied by the capacitors of matched filter  103  for the most significant bit increases. 
     Therefore, in matched filter  10 E according to a fifth embodiment shown in FIG. 7, the capacitances of the capacitors C 1  to C 5  shown in FIG. 2 are the same for all of matched filters  100 A to  103 A. 
     The output voltages of matched filters  100 A to  103 A are digitized by analog-to-digital converter circuits  240  to  243 , respectively. Outputs R 1  to R 3  of analog-to-digital converter circuits  241  to  243  are multiplied by k 1  to k 3  by multiplier circuits M 11  to M 13 , respectively, and are provided to adder circuit  21 A together with output RO of analog-to-digital converter circuit  240 . The sum total thereof is obtained as digital correlation value DOUT. 
     When resolutions of analog-to-digital converter circuits  240  to  243  are VDD/N 0  to VDD/N 3 , N 1 ·k 1 /N 0 =2, N 2 ·k 2 /N 0 =2 2  and N 3 ·k 3 /N 0 =2 3 . 
     The resolution of correlation value DOUT is VDD·n/(2 4  N 0 ), where n is of FIG.  1 . 
     Although preferred embodiments of the present invention have been described, it is to be understood that the invention is not limited thereto and that various changes and modifications may be made without departing from the spirit and scope of the invention. 
     For example, in FIG. 7, if multipliers k 1 , k 2  and k 3  are 2 j , without the use of multiplier circuits M 11  to M 3 , output wirings of analog-to-digital converter circuits to  243  are shifted by j bits toward the higher-order and connected to the input of adder circuit  21 A. over, an arrangement may be used in which analog-total converter circuits having reference voltage input used as circuits  240  to  243 , the multipliers k 1 , k 2  and re set so that k 1 =k 2 =k 3 =1 with appropriate reference ages, and multiplier circuits M 11  to M 13  are omitted.