Abstract:
A data buffer device that includes a write unit and a read unit, and is disposed between a first interface device and a second interface device is provided. The write unit further includes a first write buffer, a second write buffer and a write controller. The write controller controls the first write buffer and the second write buffer to receive and transmit data from the first interface device to the second interface device alternatively according to the requests of the first interface device and the second interface device. The read unit further includes a first read controller, a first read buffer and a second read buffer. The read controller controls the first read buffer and the second read buffer to receive and transmit data from the second interface device to the first interface device alternatively according to the requests of the first interface device and the second interface device.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a data buffer device, and more particularly to a data buffer device disposed between two devices each having a different interface respectively.  
         [0003]     2. Description of the Related Art  
         [0004]     Data is transmitted in a specific format and speed for different interfaces, and thus, a specific buffer is required for data transmission via different interfaces.  FIG. 1  is a schematic diagram of a conventional buffer between a bus and a DRAM. In  FIG. 1 , a state machine  12  is employed for buffering data between bus  11  and DRAM  13 . Although the buffer shown in  FIG. 1  is easily implemented and inexpensive, the performance of the buffer is inadequate and cannot deal with bi-directional data transmission such that the buffer shown in  FIG. 1  cannot process a massive amount of data in a short time.  
       BRIEF SUMMARY OF THE INVENTION  
       [0005]     The invention provides a data buffer device disposed between two devices each having a different interface, and a read/write method for the data buffer device.  
         [0006]     The invention provides a data buffer system comprising a first interface device, a second interface device, a first interface controller, a second interface controller and a data buffer device. The first interface controller has a first interface and a first common interface, wherein the first interface controller communicates with the first interface device via the first interface to process requests from the first interface device, and the first interface controller accesses data in a data buffer device via the first common interface. The second interface controller has a second interface and a second common interface, wherein the second interface controller communicates with the second interface device via the second interface to process requests from the second interface device, and the second interface controller accesses data in the data buffer device via the second common interface. The data buffer device includes a write unit and a read unit, wherein the write unit includes a first write buffer, a second write buffer and a write controller, and the read unit includes a first read buffer, a second read buffer and a read controller. The write controller directs the first write buffer and the second write buffer to alternately receive data from the first interface device in response to requests from the first interface device and the second interface device, and transmits the received data to the second interface device. The read controller directs the first read buffer and the second read buffer to alternately receive data from the second interface device in response to requests from the first interface device and the second interface device, and transmits the received data to the first interface device  
         [0007]     The invention provides a method for an access to a data buffer system between a first interface device and a second interface. The method includes the following steps. First, a first interface controller having a first interface and a first common interface is provides. The first interface controller communicates with the first interface device via the first interface, and communicates with a data buffer device via the first common interface. Next, a second interface controller having a second interface and a second common interface is provides. The second interface controller communicates with the second interface device via the second interface, and communicates with the data buffer device via the second common interface. And then, a data buffer device having a read unit and a write unit is provided, wherein the read unit includes a first read buffer, a second read buffer and a read controller, and the write unit comprises a first write buffer, a second write buffer and a write controller. The first interface device transmits data to the second interface device via the data buffer device when a write operation is applied and when the first interface device reads data from the second interface device via the data buffer device, a read operation is applied. Moreover, the write operation includes the following steps. First, a first write buffer is selected to receive data from the first interface device. Next, when the first write buffer is full, the write controller switches to the second write buffer to receive data. And then, when the first write buffer is partially full and the write operation ends, a next write operation selects the second write buffer to receive data. The read operation includes the following steps. First, a first read buffer is selected to receive data from the second interface device. Next, when the first read buffer is full, the read controller switches to the second read buffer to receive data. And then, when the first read buffer is partially full and the read operation ends, a next read operation selects the second read buffer to receive data.  
         [0008]     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]     The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:  
         [0010]      FIG. 1  is a schematic diagram of a conventional buffer between a bus and a DRAM.  
         [0011]      FIG. 2  is a block diagram of one embodiment of the data buffer device of the invention.  
         [0012]      FIG. 3  is a waveform according to an access to the data buffer device of  FIG. 2 .  
         [0013]      FIG. 4  is a timing diagram according to an access to the data buffer device of  FIG. 2 .  
         [0014]      FIG. 5  is a flowchart of data transmission from the bus to the data buffer device in  FIG. 2 .  
         [0015]      FIG. 6  is a flowchart of data transmission from the data buffer device to the DRAM in  FIG. 2 .  
         [0016]      FIG. 7  is a flowchart of data transmission between the data buffer device and the DRAM.  
         [0017]      FIG. 8  is a flowchart of data transmission between the bus and the data buffer device. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0018]     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.  
         [0019]      FIG. 2  is a block diagram of one embodiment of the data buffer device of the invention. Data is transmitted between bus  21  and DRAM  22  via a data buffer device  20 , wherein the bus  21  is a PCI bus, an ISA bus, an AMBA bus, an AHB bus, a SOC/Local bus, an ASB bus, an APB bus, a ZSB bus or a ZPB bus, and DRAM  21  is an SDRAM or a DDR RAM. The bus  21  reads the data buffer device  20  via the bus controller  28  and the data buffer device  20  accesses the DRAM  22  by the DRAM controller  29 . The data buffer device  20  communicates with the bus controller  28  via a first common interface  28 , and communicates with the DRAM controller  29  via the second common interface  29   b . The bus controller  28  communicates with the bus  21  via a bus interface  28   a  and the DRAM controller  29  communicates with the DRAM  22  via a DRAM interface  29   a . According to the described design, only the bus controller  28  or the DRAM controller needs to be changed when the bus  21  or the DRAM  22  is replaced with other type of bus or memory.  
         [0020]     The data buffer device  20  includes a write controller  23 , a read controller  24 , a first write buffer  26   a , a second write buffer  26   b , a first read buffer  27   a , a second read buffer  27   b  and multiplexers  25   a ,  25   b ,  25   c  and  25   d . The first write buffer  26   a , second write buffer  26   b , first read buffer  27   a  and second read buffer  27   b  are FIFO buffers, registers or memory.  
         [0021]     When the bus  21  performs a write operation to transmit data to the DRAM  22 , the bus  21  transmits a write request to the bus controller  28  and the write controller  23 . The write controller  23  selects one write buffer, such as the first write buffer  26   a , after receiving the write request. When the bus  21  transmits data to the data buffer device  20  via the first common interface  28   b  of the bus controller  28 , the write controller  23  controls multiplexer  25   a  to provide a transmission path and pass the data from the bus  21  to the first write buffer  26   a . When the first write buffer  26   a  is full and the write operation does not finish, the write controller  23  controls multiplexer  25   a  to provide another transmission path and pass the data from the bus  21  to the second write buffer  26   b , and the write controller  23  controls multiplexer  25   d  to transmit data from the first write buffer  26   a  to the DRAM  22  via the DRAM interface  29   a  of the DRAM controller  29 . When the first write buffer  26   a  is partially full and the write operation finishes, the write controller  23  controls multiplexer  25   d  to transmit data from the first write buffer  26   a  to the DRAM  22  via the DRAM interface  29   a  of the DRAM controller  29 . When one write operation finishes, the write controller  23  records the last used write buffer and when a next write operation begins, the write controller  23  selects any write buffer except for the last used write buffer to begin storing data. For example, the first write buffer  26   a  and the second write buffer  26   b  are the buffers for writing. If one write operation finishes and the last using write buffer is the first write buffer  26   a , a next write operation begins and selects the second write buffer  26   b  to receive data.  
         [0022]     When the bus  21  processes a read operation to access data from the DRAM  22 , the bus  21  transmits a read request to the bus controller  28  and the read controller  24 . The read controller  24  selects one read buffer, such as the first read buffer  27   a  after receiving the read request. When the bus  21  accesses data from the DRAM  22  via the data buffer device  20 , the read controller  24  controls the multiplexer  25   c  to provide a transmission path for transmitting data from the DRAM  22  to the first read buffer  27   a . When the first read buffer  27   a  is full and the read operation is not finished, the read controller  24  controls the multiplexer  25   c  to provide another transmission path for transmitting data from the DRAM  22  to the second read buffer  27   b , and the read controller  24  controls the multiplexer  25   b  to transmit data sinform the first read buffer  27   a  to the bus  21  via the bus interface  28   a  of the bus controller  28 . When the first read buffer  27   a  is partially full and the read operation is finished, the read controller  24  controls the multiplexer  25   b  to transmit data from the first read buffer  27   a  to the bus  21  via the bus interface  28   a  of the bus controller  28 . When one read operation is finished, the read controller  24  records the last used read buffer and when a next read operation begins, the read controller  24  selects one read buffer except for the last used read buffer to begin storing data. For example, the first read buffer  27   a  and the second read buffer  27   b  are the buffers for reading. If one read operation is finished and the last used read buffer is the first read buffer  27   a , a next read operation begins and the second read buffer  27   b  is selected to receive data.  
         [0023]     Furthermore, the data buffer device has a pre-read function and a post-write function with the ability of performing a write operation and a read operation simultaneously.  
         [0024]     For example, the first read buffer  27   a  and the second read buffer  27   b  are used to illustrate the pre-read function. The first read buffer  27   a  and the second read buffer  27   b  are eight double word (DW) FIFO registers, i.e. the FIFO register has 8×32 bits. When the bus  21  reads two continuous eight DW data, the read controller  24  receives and stores the first eight DW data in one read buffer, such as the first reading data buffer  27   a , and the second eight DW data in another read buffer simultaneously, such as the second read buffer  27   b . Once the bus  21  sends a read request to the read controller  24  for reading the second eight DW data, the read controller  24  controls the multiplexer  25   b  to provide a transmission path for directly transmitting data from the second read buffer  27   b  to the bus  21 , and thus, the read time can be reduced.  
         [0025]     For example, the first write buffer  26   a  and the second write buffer  26   b  are used to illustrate the post-write function. Generally speaking, a write operation finishes when the bus  21  receives an ACK signal from the write controller  23  after data is written into the DRAM  22 . In order to increase the performance of data buffer device  20 , the write controller  23  sends an ACK signal to the bus  21 , and then transmits data from the first write buffer  26   a  to the DRAM  22  when data is written into one buffer, such as the first write buffer  26 ,. At the same time, data, which is sent from bus  21 , can be stored into the second write buffer  26   b  so that the write time is reduced and the performance of the data buffer device  20  gets improved.  
         [0026]      FIG. 3  is a waveform according to an access to the data buffer device of  FIG. 2 . WB 1 , WB 2 , RB 1  and RB 2  respectively indicate access conditions of the first write buffer  26   a , the second write buffer  26   b , the first read buffer  27   a  and the second read buffer  27   b . PUSH indicates that the buffers receive data and POP indicates that the buffers output data. WB 1 _PUSH indicates that the first write buffer  26   a  receives data from the bus  21 , and WB 1 _POP indicates that the first write buffer  26   a  transmits data therein to the DRAM  22 . RB 1 _PUSH indicates that the first read buffer  27   a  receives data from the DRAM  22 , and RB 1 _POP indicates that the first read buffer  27   a  transmits data therein to the bus  21 . When the first write buffer  26   a  transmits data therein to the DRAM  22 , the second write buffer  26   b  receives data from bus  21 . Moreover, the read buffer, such as the first read buffer  27   a , and the write buffer, such as the first write buffer  26   a , can work simultaneously. According to the described operation, the data buffer device  20  utilizes two access paths, such as a writing path or a reading path, to implement the bi-directional transmission and gain performance.  
         [0027]     In a conventional data buffer device, the data length information is included in the read request or write request. In the invention, the data length is determined by the request time interval. Turning first to  FIG. 4 , a timing diagram according to an access to the data buffer device  20  of  FIG. 2  is illustrated. When the read controller  24  receives a read request, Read_Request, from the bus  21 , a read buffer, such as the first read buffer  27   a , is selected to receive data from the DRAM  22 . In the embodiment, the bus  21  reads eight DW data so that the Read_Request should be enabled for lasting an eight-clock cycle time period, T, and the RB 1 _PUSH also should be enabled for lasting an eight-clock cycle time period. When the first read buffer  27   a  is full, the RB 1 _POP is enabled and the received data is transmitted to the bus  21  for lasting an eight-clock cycle time period.  
         [0028]     When the write controller  23  receives a write request, Write_Request, from the bus  21 , a write buffer, such as the first write buffer  26   a , is selected to receive data from the bus  21 . In this embodiment, the bus  21  writes eight DW data into the DRAM  22  so that the Write_Request is enabled for lasting an eight-clock cycle time period, and the WB 1 _PUSH is also enabled for lasting an eight-clock cycle time period. When the first write buffer  26   a  is full, the WB 1 _POP is enabled and the received data is transmitted to the DRAM  22  for an eight-clock cycle time.  
         [0029]     Except for the continuous data transmission, the data buffer device  20  also can transmit data from any address segment of a buffer to the bus  21  or the DRAM  22 . For example, if the bus  21  has an eight DW data, but only from the fifth to the eighth one of the eight DW data needs to be written into the DRAM  22 , the write controller  23  transmits the eight DW data to one write buffer, but only from the fifth to the eighth one is written into the DRAM. Similarly, the bus  21  can read data from any address segment of the DRAM  22 .  
         [0030]     Turning back to  FIG. 2 , a complete write operation includes the following steps, such as writing data into the data buffer device  20  from the bus  21  and writing data into the DRAM  22  from the data buffer device  20 . To further illustrate the operation, please refer to  FIG. 5  and  FIG. 6 .  
         [0031]      FIG. 5  is a flowchart of data transmission from the bus  21  to the data buffer device  20  in  FIG. 2 . In step S 51 , the first write buffer  26   a  receives a write request, such as Write_Request. Next, the bus  21  checks whether the first write buffer  26   a  is available in step S 52 . If yes, data is transmitted from the bus  21  to the first write buffer  26   a  in step S 53 . If no, the bus  21  keeps on checking whether the first write buffer  26   a  is available in step S 52 . If the first write buffer  26   a  is still full and the write operation is not finished, the bus  21  checks whether the second write buffer  26   b  is available in step S 57 . If yes, data is transmitted from the bus  21  to the second write buffer  26   b  in step S 58 . If no, the bus  21  keeps on checking whether the second write buffer  26   b  is available in step S 57 . If the second write buffer  26   b  is still full and the write operation is not finished, the bus  21  checks whether the first write buffer  26   a  is available in step S 52 . If yes, data is transmitted from the bus  21  to the first write buffer  26   a  in step S 53 . If no, the bus  21  keeps on checking whether the first write buffer  26   a  is available in step S 52 . When the write operation is finished, the first write buffer  26   a  is selected and waits for the next action in step S 50  or the second write buffer  26   b  is selected and waits for the next action in step S 55 .  
         [0032]      FIG. 6  is a flowchart of data transmission from the data buffer device  20  to the DRAM  22  in  FIG. 2 . If the first write buffer  26   a  receives a write request for writing data into the DRAM  22  whether the first write buffer  26   a  is full in step S 62 , the data is transmitted from the first write buffer  26   a  to the DRAM  22  in step S 63 . When the data transmission is finished in step S 64 , the bus  21  checks whether the second write buffer  26   b  is empty. If yes, the second write buffer  26   b  is selected and waits for the next action in step S 65 . If no, the second write buffer  26   b  receives a write request for writing data into the DRAM  22  whether the second write buffer  26   b  is full in step S 66 . And then, the data is transmitted from the second write buffer  26   b  to the DRAM  22  in step S 67 . When the data transmission is finished in step S 68 , the first write buffer  26   a  is selected and waits for the next action in step S 61 . Furthermore, if the first write buffer  26   a  is not empty in step S 68 , the data is kept on transmitting from the first write buffer  26   a  to the DRAM  22  in step S 63 .  
         [0033]     Turning back to  FIG. 2 , a complete read operation includes the following steps, such as reading data from the DRAM  22  by the data buffer device  20  and reading data from the data buffer device  20  by the bus  21 . To further illustrate the operation, please refer to  FIG. 7  and  FIG. 8 .  
         [0034]      FIG. 7  is a flowchart of data transmission between the data buffer device  20  and the DRAM  22 . In step S 703 , the first read buffer  27   a  receives a read request, such as Read_Request. Next, the data buffer device  20  checks whether the first read buffer  27   a  is available in step S 705 . If yes, data is transmitted from the DRAM  22  to the first read buffer  27   a  in step S 707 . If no, the data buffer device  20  keeps on checking whether the first read buffer  27   a  is available in step S 705 . If the first read buffer  27   a  is fully filled with data and the data buffer device  20  enables a pre-read function whether the read operation is finished in step S 709 , the data buffer device  20  selects the second read buffer  27   b  to keep on receiving data from the DRAM  22  in step S 717 . For example, if the data buffer device  20  enables the pre-read function or the first read buffer  27   a , which is an eight DW register, doesn&#39;t have enough space to buffer the data of which length is greater than eight DWs, the data buffer device  20  selects the second read buffer  27   b  to keep on receiving data from the DRAM  22  in step S 717 . Following the step S 709 , if the first read buffer  27   a  finishes reading data from DRAM  22  and the data buffer device  20  does not enable the pre-read function in step S 711 , the second read buffer  27   b  is selected and waits for the next action in step S 713 .  
         [0035]     When the second read buffer  27   b  receives a read request, such as Read_Request in step S 715 , the data buffer device  20  checks whether the second read buffer  27   b  is available in step S 717 . If yes, data is transmitted from the DRAM  22  to the second read buffer  27   a  in step S 719 . If no, the data buffer device  20  keeps on checking whether the second read buffer  27   b  is available in step S 717 . If the second read buffer  27   a  is fully filled with data and the data buffer device  20  enables a pre-read function whether the read operation is finished in step S 721 , the data buffer device  20  selects the first read buffer  27   a  to keep on receiving data from the DRAM  22  in step S 705 . Following the step S 721 , if the second read buffer  27   b  finishes reading data from DRAM  22  and the data buffer device  20  does not enable the pre-read function in step S 723 , the first read buffer  27   a  is selected and waits for the next action in step S 701 .  
         [0036]      FIG. 8  is a flowchart of data transmission between the bus  21  and the data buffer device  20 . When the first read buffer  27   a  receives a read request from the bus  21  in step S 803 , the data buffer device  20  checks whether the pre-read function is enabled and the first read buffer  27   a  has pre-read data that is needed in step S 805 . If yes, data is transmitted from the first read buffer  27   a  to the bus  21  in step S 811 . If no, data is transmitted from the DRAM  22  to the first read buffer  27   a  in step S 807 . Following the step S 807 , when the first read buffer  27   a  is full or receives a read request in step S 809 , the data buffer device  20  transmits data from the first read buffer  27   a  to the bus  21  in step S 811 . Following the step S 811 , when the last data is transmitted from the first read buffer  27   a  to the bus  21  in step S 813 , the data buffer device  20  checks whether the read request is still issued from the bus  21  in step S 815 . If yes, the data buffer device  20  checks whether the pre-read function is enabled and the second read buffer  27   b  has pre-read data that is needed in step S 821 . If no, the second read buffer  27   b  is selected and waits for the next action in step S 817 .  
         [0037]     When the second read buffer  27   b  receives a read request from the bus  21  in step S 819 , the data buffer device  20  checks whether the pre-read function is enabled and the second read buffer  27   b  has pre-read data that is needed in step S 821 . If yes, data is transmitted from the second read buffer  27   b  to the bus  21  in step S 827 . If no, data is transmitted from the DRAM  22  to the second read buffer  27   b  in step S 823 . Following the step S 823 , when the second read buffer  27   b  is full or receives a read request in step S 825 , the data buffer device  20  transmits data from the second read buffer  27   b  to the bus  21  in step S 827 . Following the step S 827 , when the last data is transmitted from the second read buffer  27   b  to the bus  21  in step S 829 , the data buffer device  20  checks whether the read request is still issued from the bus  21  in step S 831 . If yes, the data buffer device  20  checks whether the pre-read function is enabled and the first read buffer  27   b  has pre-read data that is needed in step S 805 . If no, the first read buffer  27   a  is selected and waits for the next action in step S 801 .  
         [0038]     While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.