Abstract:
Designs of an overcurrent protection circuit Techniques are disclosed. According to one aspect of the present invention, an overcurrent protection having continuous protection thresholds is provided to efficiently protect a battery from discharging overcurrent especially in all intermediate states.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a protection circuit, more particularly to an overcurrent protection circuit of a battery. 
     2. Description of Related Art 
     It is well known that a Lithium ion battery has been broadly used as a battery cell of a battery pack, since the Lithium ion battery generates a high energy density per weight and volume, and generally provides a reduction in size and weight of a portable type apparatus. However, the Lithium ion battery has a safety problem that its performance characteristic is degraded when it is charged by an overvoltage, and what is more, it even tends to become explosive if it is operated beyond its capacity. Hence, every Lithium ion battery cell needs a protection circuit. The protection circuit commonly comprises charging overvoltage protection, discharging overvoltage protection, charging overcurrent protection, discharging overcurrent protection and short circuit protection. 
     The discharging overcurrent protection is that when the battery is discharged through a load resistor, the discharging current exceeds a related overcurrent voltage protection threshold V EDI  and this state keeps a period of time beyond a certain delay time T EDI , the battery protection circuit switches off the discharging path to prohibit discharging, thereby entering the overcurrent protection state. When the discharging current is further increased beyond a related short voltage protection threshold V SC  and this state keeps a period of time beyond a certain delay time T SC , the battery protection circuit switches off the discharging path to prohibit charging, thereby entering the short protection state. The short protection state and the overcurrent protection state are the same for a control circuit and both aim to prohibit discharging in the circuit. Exiting conditions of the two protection state are the same too and both are that the voltage drop between the VM node and the G node is less than the voltage threshold V EDI  and this state keeps a period of time beyond a certain delay time. The main difference of the two states is that the short voltage protection threshold V SC  is larger than the overcurrent voltage protection threshold V EDI , and the delay time T SC  is less than the delay time T EDI . Namely, the more the discharging overcurrent is, the shorter the delay time is. 
     In the prior art, several discharging overcurrent thresholds and one short threshold may be configured for discharging overcurrent protection. However, other overcurrent states do exist among the several protections. The conventional protection scheme can not efficiently protect the battery from discharging overcurrent especially in the intermediate states. 
     Thus, improved techniques for overcurrent protection circuit having continuous protection thresholds are desired to overcome the above disadvantages. 
     SUMMARY OF THE INVENTION 
     This section is for the purpose of summarizing some aspects of the present invention and to briefly introduce some preferred embodiments. Simplifications or omissions in this section as well as in the abstract or the title of this description may be made to avoid obscuring the purpose of this section, the abstract and the title. Such simplifications or omissions are not intended to limit the scope of the present invention. 
     An overcurrent or excess current is a situation where a larger than intended current flows through a device, leading to excessive generation of heat and the risk of damaging an infrastructure, equipment and causing fires. Possible causes for overcurrent include short circuits, excessive load, and incorrect design. Fuses, circuit breakers, temperature sensors and current limiters are commonly used protection mechanisms to control the risks of overcurrent. The present invention provides designs of an overcurrent protection circuit that may be used to prevent such an overcurrent. In particular, a protection scheme, as disclosed herein, having continuous protection thresholds may efficiently protect a battery from discharging overcurrent especially in all intermediate states. 
     Objects, features, and advantages of the present invention will become apparent upon examining the following detailed description of an embodiment thereof, taken in conjunction with the attached drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where: 
         FIG. 1  is a circuit diagram showing one conventional battery protection circuit with two stages discharging overcurrent protection; 
         FIG. 2  is a curve diagram showing a relation between a discharging overcurrent and a delay time of the battery protection circuit shown in  FIG. 1 ; 
         FIG. 3  is a circuit diagram showing another conventional battery protection circuit with three stages discharging overcurrent protection; 
         FIG. 4  is a curve diagram showing a relation between a discharging overcurrent and a delay time of the battery protection circuit shown in  FIG. 2 ; 
         FIG. 5  is a circuit diagram showing a battery protection circuit according to one embodiment of the present invention; 
         FIG. 6  is a curve diagram showing a relation between a discharging overcurrent and a delay time of the battery protection circuit shown in  FIG. 5 ; 
         FIG. 7  is a block diagram schematically showing a discharging continuous overcurrent detection circuit of the battery protection circuit shown in  FIG. 5 ; 
         FIG. 8  is a circuit diagram showing a practical implement of the discharging overcurrent detection circuit shown in  FIG. 7 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The detailed description of the present invention is presented largely in terms of procedures, steps, logic blocks, processing, or other symbolic representations that directly or indirectly resemble the operations of devices or systems contemplated in the present invention. These descriptions and representations are typically used by those skilled in the art to most effectively convey the substance of their work to others skilled in the art. 
     Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Further, the order of blocks in process flowcharts or diagrams or the use of sequence numbers representing one or more embodiments of the invention do not inherently indicate any particular order nor imply any limitations in the invention. 
     Embodiments of the present invention are discussed herein with reference to  FIGS. 1-8 . However, those skilled in the art will readily appreciate that the detailed description given herein with respect to these figures is for explanatory purposes only as the invention extends beyond these limited embodiments. 
       FIG. 1  is a circuit diagram showing a battery protection circuit with two stages discharging overcurrent protection. The protection circuit comprises an overcharge detection circuit, an overdischarge detection circuit, a charging overcurrent detection circuit, a discharging overcurrent detection circuit, a short detection circuit, a control circuit and output switches MD and MC. 
     The discharging overcurrent detection circuit is configured to determine whether there is discharging overcurrent on the battery by detecting a voltage drop on the output switches MD and MC (between a node VM and a node G) and comparing the voltage drop with a certain voltage protection threshold V EDI . Provided that the turn-on resistances of the output switches MD and MC are expressed as R ON     —     MD  and R ON     —     MC , so the overcurrent protection threshold I EDI  may be: 
     
       
         
           
             
               I 
               EDI 
             
             = 
             
               
                 V 
                 EDI 
               
               
                 
                   R 
                   
                     ON 
                     ⁢ 
                     _ 
                     ⁢ 
                     MD 
                   
                 
                 + 
                 
                   R 
                   
                     ON 
                     ⁢ 
                     _ 
                     ⁢ 
                     MC 
                   
                 
               
             
           
         
       
     
     When the discharging current increases beyond the protection current threshold I EDI  and this state keeps a period of time beyond a certain delay time T EDI , the control circuit outputs a control signal to switch off the output switches MD and MC. Thus, the discharging of the battery is prohibited and the protection circuit enters a discharging overcurrent protection state. 
     The short detection circuit is configured to determine whether there is short on the battery by detecting the voltage drop on the output switches MD and MC (between a node VM and a node G) and comparing the voltage drop with a certain voltage protection threshold V SC . Similarly, the short current protection threshold I SC  is: 
     
       
         
           
             
               I 
               SC 
             
             = 
             
               
                 V 
                 SC 
               
               
                 
                   R 
                   
                     ON 
                     ⁢ 
                     _ 
                     ⁢ 
                     MD 
                   
                 
                 + 
                 
                   R 
                   
                     ON 
                     ⁢ 
                     _ 
                     ⁢ 
                     MC 
                   
                 
               
             
           
         
       
     
     When the discharging current increases beyond the short current protection threshold I SC  and this state keeps a period of time beyond a certain delay time T SC , the control circuit outputs a control signal to switch off the output switches MD and MC. Thus, the discharging of the battery is prohibited and the protection circuit enters a short protection state. The short protection state and the overcurrent protection state are the same for the control circuit and both aim to prohibit discharging of the battery. Exiting conditions of the two protection state are the same too and both are that the voltage drop between the VM node and the G node is less than the voltage threshold V EDI  and this state keeps a period of time beyond a certain delay time. The main difference of the two states is that the short voltage protection threshold V SC  is larger than the overcurrent voltage protection threshold V EDI , and the delay time T SC  is less than the delay time T EDI . 
     For the same battery voltage, the more the discharging current is, the more the power consumption in the same time is, the more the generated heat is. A lot of electronic systems are destroyed due to overheat. Provided that the battery voltage is V B , the battery current is I B , so the caloric P generated in certain period of time T may be:
 
 P=V   B   ·I   B   ·T  
 
     Hence, the more the discharging current is, the shorter the delay time needs to be.  FIG. 2  is a curve diagram showing a relation between a discharging overcurrent and a delay time of the battery protection circuit shown in  FIG. 1 . As shown in  FIG. 2 , when the discharging current is larger than the protection threshold I EDI  and is less than the protection threshold I SC , the delay time is T EDI . When the discharging current exceeds the protection threshold I SC , T SC  is used as the delay time. Apparently, the discharging current increases gradually from I EDI  to I SC , the delay time decrease gradually from T EDI  to T SC . 
       FIG. 3  is a circuit diagram showing another battery protection circuit with three stages discharging overcurrent protection. Because other overcurrent states between I EDI  and I SC  really exists, the batter protection circuit with three stages discharging overcurrent protection is proposed for efficiently protection. Referring to  FIG. 3 , the protection circuit comprises an overcharge detection circuit, an overdischarge detection circuit, a charging overcurrent detection circuit, a first discharging overcurrent detection circuit, a second discharging overcurrent detection circuit, a short detection circuit, a control circuit and output switches MD and MC. The operation principle of the protection circuit shown in  FIG. 3  is identical with that of the protection circuit shown in  FIG. 1 . The difference is that the second discharging overcurrent diction circuit is added. The current protection threshold of the first discharging overcurrent diction circuit is I EDI1 , and the delay time of the first discharging overcurrent diction circuit is T EDI1 . The current protection threshold of the second discharging overcurrent diction circuit is I EDI2 , and the delay time of the second discharging overcurrent diction circuit is T EDI2 , wherein I EDI1 &lt;I EDI2 &lt;I SC , and T EDI1 &gt;T EDI2 &gt;T SC . As a result, one intermediate overcurrent protection state between I EDI  and I SC  are realized. 
       FIG. 4  is a curve diagram showing a relation between a discharging overcurrent and a delay time of the battery protection circuit shown in  FIG. 3 . As shown in  FIG. 4 , when the discharging current is larger than the protection threshold I EDI1  and is less than the protection threshold I EDI2 , the delay time is T EDI1 . When the discharging current is larger than the protection threshold I EDI2  and is less than the protection threshold I SC , the delay time is T EDI2 . When the discharging current exceeds the protection threshold I SC , T SC  is used as the delay time. Apparently, the discharging current increases gradually from I EDI1 , I EDI2  to I SC , the delay time decrease gradually from T EDI1 , T EDI2  to T SC . 
     Other overcurrent states really exist between I EDI1  and I EDI2  or between I EDI2  and I SC . Hence, these intermediate overcurrent state should also be protected.  FIG. 5  is a circuit diagram showing a battery protection circuit according to one embodiment of the present invention. As shown in  FIG. 5 , the protection circuit comprises an overcharge detection circuit, an overdischarge detection circuit, a charging overcurrent detection circuit, a discharging continuous overcurrent detection circuit, a control circuit and output switches MD and MC. The discharging overcurrent and the delay time follows the relationship hereafter: 
               T   EDI     =     Q     I   EDI             
where T EDI  is the delay time, I EDI  is the discharging over, Q is designed to be a constant.
 
       FIG. 6  is a curve diagram showing a relation between a discharging overcurrent and a delay time of the battery protection circuit shown in  FIG. 5 . As shown in  FIG. 6 , the delay time T EDI  is inversely proportional to the discharging current I EDI2 . As a result, it can be realized that the delay time changes along with continuous changes of the discharging current. 
       FIG. 7  is a block diagram schematically showing a discharging continuous overcurrent detection circuit of the battery protection circuit shown in  FIG. 5 . The discharging continuous overcurrent detection circuit is configured for determining whether there are discharging overcurrent on the battery by detecting a voltage drop on the output switches MD and MC (between a node VM and a node G) and comparing the voltage drop with a certain voltage protection threshold V EDI . If the voltage drop on the output switches is larger than the protection threshold V EDI  and this state keeps a period of time beyond a certain delay time T EDI , the control circuit driven by the overcurrent detection circuit outputs a control signal to switch off the output switches MD and MC, thereby the discharging to the battery is prohibited. 
     As shown in  FIG. 7 , the overcurrent detection circuit comprises an overcurrent comparator circuit, a voltage controlled oscillator circuit  700 , and a counter. 
     The overcurrent comparator circuit is configured for comparing a detected voltage representative of the discharging current with a voltage protection threshold V EDI . If the detected voltage is larger than the voltage protection threshold V EDI , the overcurrent comparator circuit output an enable signal to enable the voltage controlled oscillator circuit; otherwise, the overcurrent comparator circuit output a disable signal to disable the voltage controlled oscillator circuit. 
     The voltage controlled oscillator circuit  700  starts working after receiving the enable signal from the overcurrent comparator circuit and stop working after receiving the disable signal from the overcurrent comparator circuit. The voltage controlled oscillator circuit  700  is configured for generating an oscillation signal with a cycle depending on the detected voltage. The counter is configured for outputting a driven signal after counting a given number of oscillation signals. The control circuit generates a control signal to switch off the output switches MD and MC after receiving the driven signal, thereby the discharging to the battery is prohibited. 
     The voltage controlled oscillator circuit  700  comprises a voltage controlled current source circuit  702  and an oscillator circuit  704 . The voltage controlled current source  702  comprises a voltage controlled current source for generating a current depending on the detected voltage and a first enable circuit for receiving the enable signal from the overcurrent comparator circuit and enabling the voltage controlled current source. The oscillator circuit  704  comprises an oscillator for generating the oscillation signal with a cycle depending on the current of the voltage controlled current source and a second enable circuit for receiving the enable signal from the overcurrent comparator circuit and enabling the oscillator. In a preferred embodiment, the current generated by the voltage controlled current source is proportional to the detected voltage, and the cycle of the oscillation signal generated by the oscillator is inversely proportional to the current of the voltage controlled current source. 
       FIG. 8  is a circuit diagram showing a practical implement of the discharging overcurrent detection circuit shown in  FIG. 7 . The voltage controlled current source comprises an operation amplifier, a first transistor MP 1 , a second transistor MP 2  and a resistor R 1 . In one embodiment, the first and second transistors are p-type MOS transistors. 
     Gates of the first and second transistors MP 1  and MP 2  are coupled with each other, sources of the first and second transistors are coupled to a power supply VCC, and the gate of the first transistor MP 1  is coupled to a drain of the first transistor MP 1 . The drain of the first transistor MP 1  is connected with one terminal of the resistor R 1 , the other terminal of the resistor R 1  is connected to a ground reference. A negative input terminal of the operation amplifier as an input terminal of the voltage controlled current source is coupled to the detected voltage VM, a positive input terminal of the operation amplifier is connected to the drain of the first transistor MP 1 . An output terminal of the operation amplifier is coupled to the gate of the first transistor MP 1 . A drain of the second transistor MP 2  is regarded as an output terminal of the voltage controlled current source. 
     The first and second transistors MP 1  and MP 2  form a current mirror. The positive terminal of the operation amplifier is used for sampling a voltage drop on the resistor R 1 . The operation amplifier is configured for comparing the voltage drop V R1  on the resistor R 1  with the detected voltage VM and amplifying difference between the voltage drop and the detected voltage VM to control the first transistor MP 1 . In stabilization state, the voltage drop V R1  will be equal to the detected voltage VM, so the current I MP1  of the transistor MP 1  may be:
 
 I   MP1   =VM/R 1
 
     The current I MP2  of the second transistor MP 2  flows into the oscillator circuit  704 . The current I MP2  of the second transistor MP 2  may be equal to the current I MP1  of the first transistor MP 1 . It can be seen that the current I MP2  generated by the voltage controlled current source is proportional to the detected voltage VM. 
     A third transistor MP 3  which may be p-type serves as the first enable circuit in one embodiment. A drain of the third transistor MP 3  is coupled to the gate of the first transistor MP 1 , and a source of the third transistor MP 3  is coupled to the power supply VCC. A gate of the third transistor MP 3  is provided for receiving the enable signal or disable signal from the overcurrent comparator circuit. When the enable signal is sent to the gate of the third transistor MP 3 , the third transistor MP 3  is turned off, thereby the voltage controlled current source starts working and outputting the current I MP2  to the oscillator. When the disable signal is sent to the gate of the third transistor MP 3 , the third transistor MP 3  is turned on to disable the first transistor MP 1 , thereby the voltage controlled current source stop working and outputting the current I MP2 . 
     The oscillator comprises a capacitor C 1 , an oscillation comparator and a fourth transistor MN 1 . One terminal of the capacitor C 1  is connected to the drain of the second transistor MP 4  and further connected to a positive input terminal of the oscillation comparator, and the other terminal of the capacitor C 1  is connected to the ground reference. A negative input terminal of the oscillation comparator is connected to a reference voltage V REF . A drain of the transistor MN 1  is connected to the positive input terminal of the oscillation comparator, a source of the transistor MN 1  is connected to the ground reference, and a gate of the transistor MN 1  is connected to an output terminal of the oscillation comparator. The fourth transistor MN 1  is an n-type transistor in one embodiment. 
     In operation of the oscillator, the current I MP2  of the voltage controlled current source is used to charge the capacitor C 1  slowly. Once a voltage drop on the capacitor C 1  is larger than the reference voltage V VEF , the oscillation comparator inverts to output a discharging control signal to the gate of the transistor MN 1 . The transistor MN 1  is turned on to switch on the positive terminal of the oscillation comparator and the ground reference. Thus, the capacitor C 1  is discharged quickly by the transistor MN 1  until the voltage drop on the capacitor C 1  decreases to the ground reference. Once the voltage drop on the capacitor C 1  is less than the reference voltage V REF , the oscillation comparator inverts to output a charging control signal to the gate of the transistor MN 1 . The control signal from the oscillation comparator is delayed a period of time so that before the transistor MN 1  receives the control signal of the oscillation comparator, the capacitor C 1  has been discharged completely. When the transistor MN 1  receives the charging control signal, the transistor MN 1  is turned off to switch off the positive terminal of the oscillation comparator and the ground reference. Thus, the capacitor C 1  is slowly charged again. Repeating the above operations, the oscillation signal with a cycle in proportion to the current I MP2  is generated. 
     Provided that the current I MP1  of the transistor MP 1  is equal to the current I MP2  of the transistor MP 2  in one embodiment, the cycle T OSC  of the oscillation signal may be: 
               T   OSC     =             V   REF     ·   C     ⁢           ⁢   1       I     MP   ⁢           ⁢   2         =             V   REF     ·   R     ⁢           ⁢     1   ·   C     ⁢           ⁢   1     VM     =           V   REF     ·   R     ⁢           ⁢     1   ·   C     ⁢           ⁢   1         I   EDI     ·     (       R     ON   ⁢   _   ⁢   MD       +     R     ON   ⁢   _   ⁢   MC         )                   
The delay time T D  is N number of oscillation signal, so T D  is:
 
               T   D     =           N   ·     V   REF     ·   R     ⁢           ⁢     1   ·   C     ⁢           ⁢   1         I   EDI     ·     (       R     ON   ⁢   _   ⁢   MD       +     R     ON   ⁢   _   ⁢   MC         )         =     Q     I   EDI               
where
 
     
       
         
           
             Q 
             = 
             
               
                 
                   
                     N 
                     · 
                     
                       V 
                       REF 
                     
                     · 
                     R 
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     1 
                     · 
                     C 
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   1 
                 
                 
                   ( 
                   
                     
                       R 
                       
                         ON 
                         ⁢ 
                         _ 
                         ⁢ 
                         MD 
                       
                     
                     + 
                     
                       R 
                       
                         ON 
                         ⁢ 
                         _ 
                         ⁢ 
                         MC 
                       
                     
                   
                   ) 
                 
               
               . 
             
           
         
       
     
     It can be seen that the delay time T D  is inversely proportional to the discharging current I EDI . An inverter and a fifth transistor MN 2  which may be n-type serve as the second enable circuit in one embodiment. An output terminal of the inverter is connected to a gate of the transistor MN 2 . A source of the transistor MN 2  is connected to the ground reference, and a drain of the transistor MN 2  is connected to the positive terminal of the oscillation comparator. An input terminal of the inverter is provided for receiving the enable signal or disable signal from the overcurrent comparator circuit. When the enable signal is sent to the inverter, the firth transistor MN 2  is turned off, thereby the oscillator starts working and outputting the oscillation signal. When the disable signal is sent to the inverter, the fifth transistor MN 2  is turned on, thereby the oscillator stops outputting the oscillation signal. 
     The present invention has been described in sufficient details with a certain degree of particularity. It is understood to those skilled in the art that the present disclosure of embodiments has been made by way of examples only and that numerous changes in the arrangement and combination of parts may be resorted without departing from the spirit and scope of the invention as claimed. Accordingly, the scope of the present invention is defined by the appended claims rather than the foregoing description of embodiments.