Abstract:
A wide range single stage variable gain amplifier is provided for receiving an input signal and outputting an amplitude varied version of the received input signal. In its most basic form, the wide range single stage variable gain amplifier includes an input circuit receiving an input signal and developing an input current, a first control circuit receiving the input current, the first control circuit being selectively controllable to output an attenuated version of the received input current, a second control circuit directly connected to the first control circuit for receiving the attenuated input current therefrom, the second control circuit being selectively controllable to output a further attenuated version of the attenuated input current, and an output circuit receiving the further attenuated input current and developing an amplitude varied version of the received input signal.

Description:
FIELD OF THE INVENTION 
     The present invention is directed toward variable gain amplifiers and, more particularly, toward a wide range, single stage variable gain amplifier. 
     BACKGROUND OF THE INVENTION 
     Variable Gain Amplifiers (VGAs) are well known in the art. VGAs are generally used when the magnitude of a signal, such as an electrical current or voltage, is required to be increased or decreased. The range of gain control of a VGA is essentially defined as the difference between maximum and minimum gain. For example, if the maximum gain is +10 dB (magnification) and the minimum gain is -40 dB (attenuation), the range of gain control is 50 dB. It is understood that the maximum gain in a VGA may actually be an attenuation of the input signal. 
     In today&#39;s hand-held cellular digital radios, there is a need to control the transmitted power over a very wide control range. For IS-95 radio systems, the required control range can exceed 100 dB. Typically, two or more VGAs are cascaded in a transmitter line-up in order to achieve higher control ranges. 
     The use of multiple, or multistage as they are commonly known, VGAs has various drawbacks, such as excessive current consumption and poor noise performance. Since each VGA generally requires its own DC bias current, cascading two, three, or more VGAs will require an increase in supply current. This becomes a problem in small size, high talk time cellular phones since a large battery will be required to supply the increased supply current. Further, since each VGA stage generates noise, increasing the number of stages effectively increases the amount of noise, resulting in degraded performance. 
     The present invention is directed toward overcoming one or more of the above-mentioned problems. 
     SUMMARY OF THE INVENTION 
     A wide range single stage variable gain amplifier is provided for receiving an input signal and outputting an amplitude varied version of the received input signal. In its most basic form, the wide range single stage variable gain amplifier includes an input circuit receiving an input signal and developing an input current, a first control circuit receiving the input current, the first control circuit being selectively controllable to output an attenuated version of the received input current, a second control circuit directly connected to the first control circuit for receiving the attenuated input current therefrom, the second control circuit being selectively controllable to output a further attenuated version of the attenuated input current, and an output circuit receiving the further attenuated input current and developing an amplitude varied version of the received input signal. 
     The first control circuit includes a first switching circuit and a first pass circuit, both being selectively controllable to switch a portion of the input current through the first switching circuit. The portion of the input current flowing through the first pass circuit is output as the attenuated version of the input current. Similarly, the second control circuit includes a second switching circuit and a second pass circuit, both being selectively controllable to switch a portion of the attenuated input current, received from the first pass circuit, through the second switching circuit. The portion of the attenuated input current flowing through the second pass circuit is output as the further attenuated version of the attenuated input current. 
     The first pass circuit generally includes first and second transistors, each having input, output and control elements. The first switching circuit generally includes third and fourth transistors, each having input, output and control elements. The input current is received at the output elements of the first through fourth transistors. The control elements of the first and second transistors receive a first control voltage controlling current flow therethrough. Similarly, the control elements of the third and fourth transistors receive a second control voltage controlling current flow therethrough. 
     The second pass circuit generally includes fifth and sixth transistors, each having input, output and control elements. The second switching circuit generally includes seventh and eighth transistors, each having input, output and control elements. The attenuated input current is received from the first pass circuit at the output elements of the fifth through eighth transistors. The control elements of the fifth and sixth transistors receive a third control voltage controlling current flow therethrough. Similarly, the control elements of the seventh and eighth transistors receive a fourth control voltage controlling current flow therethrough. 
     A DC voltage source is provided and develops a DC bias current flowing through the first through eighth transistors. The transistors may include Bipolar Junction Transistors (BJTs), Field Effect Transistors (MOSFETs or MESFETs), or Heterojunction Bipolar Transistors (HBTs). 
     In a preferred form, the first and second transistors are equally sized, the third and fourth transistors are equally sized, the fifth and sixth transistors are equally sized, and the seventh and eighth transistors are equally sized. However, the transistor pairs do not need to be sized the same. 
     The output circuit generally includes first and second impedances off of which the amplitude varied version of the input signal is taken. The first and second impedances may include resistors or inductors, which themselves may have additional circuitry connected thereto. 
     It is an object of the present invention to provide a VGA having a wide control range and requiring minimum supply current. 
     It is a further object of the present invention to decrease the amount of noise introduced into a VGA having a wide control range. 
     It is yet a further object of the present invention to decrease the number of necessary stages in a VGA having a wide control range. 
     Other aspects, objects and advantages of the present invention can be obtained from a study of the application, the drawings, and the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a prior art two-stage VGA; and 
     FIG. 2 is a circuit diagram of a wide control range single stage VGA according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 illustrates a prior art two-stage VGA shown generally at 10. The two-stage VGA 10 includes first and second VGA stages 20 and 30, respectively. The first VGA stage 20 includes an input stage 40 receiving the input signal and a current switching stage 45. Similarly, the second VGA stage 30 includes an input stage 50 and a current switching stage 55. 
     The current switching stage 45 includes bipolar junction transistors Q1, Q2, Q3 and Q4. The collectors of transistors Q2 and Q3 are connected directly to a DC voltage source V CC . The collectors of transistors Q1 and Q4 are connected to the voltage source V CC  through resistors R1 and R2, respectively. 
     The input stage 40 receives an AC input signal and conventionally converts the input signal, if necessary, to an input current I signal . The input current I signal  is superimposed on an oppositely flowing DC bias current I bias  which flows from V CC  to ground through resistors R1,R2 and transistors Q1, Q2, Q3, Q4, dynamically changing the bias current I bias . Since the DC bias current I bias  will generally remain constant on average, its effect on the input current I signal  can be neglected in the following discussion. 
     The input current I signal  is received by the current switching stage 45 at the emitters of transistors Q1, Q2, Q3 and Q4. A first gain control voltage is applied, at pin 60, to the base elements of transistors Q2 and Q3, and similarly, a second gain control voltage is applied, at pin 65, to the base elements of transistors Q1 and Q4. The gain control voltages applied at pins 60 and 65 control the amount of input current I signal  permitted to flow through transistors Q1, Q2, Q3 and Q4. Some or all of the input current I signal  may be switched to flow through transistors Q2 and Q3 to V CC , which is essentially an AC ground. The portion of the input current I signal  which flows through transistors Q1 and Q4 is taken as a voltage off of resistors R1 and R2 and applied to the input stage 50 of the second VGA stage 30 through DC block capacitors C1 and C2 which block the DC components of the signal. 
     The current switching stage 55 of the second VGA stage 30 includes transistors Q5, Q6, Q7 and Q8. The collectors of transistors Q6 and Q7 are connected directly to V CC . The collectors of transistors Q5 and Q8 are connected to V CC  through resistors R3 and R4, respectively. 
     The input stage 50 receives the signal from the first VGA stage 20 and conventionally converts the signal to an input current I signal . The input current I signal  is superimposed on a DC bias current l bias2  which flows from V CC  to ground through resistors R3,R4 and transistors Q5, Q6, Q7, Q8, dynamically changing the bias current I bias2 . Since the DC bias current I bias2  will generally remain constant on average, its effect on the input current I signal  can be neglected in the following discussion. 
     The input current is received by the current switching stage 55 at the emitters of transistors Q5, Q6, Q7 and Q8. A third gain control voltage is applied, at pin 70, to the base elements of transistors Q6 and Q7, and similarly, a fourth gain control voltage is applied, at pin 75, to the base elements of transistors Q5 and Q8. The gain control voltages applied at pins 70 and 75 control the amount of input current I signal  permitted to flow through transistors Q5, Q6, Q7 and Q8. Some or all of the input current I signal  may be switched to flow through transistors Q6 and Q7 to V CC , which is essentially an AC ground. The portion of the input current i signal  which flows through transistors Q5 and Q8 is taken as a voltage off of resistors R3 and R4 and represents an amplitude varied version of the primary input signal. If more gain control is required, additional stages can be added. 
     As previously noted, the multistage VGA 10 of FIG. 1 requires excessive bias current (I bias  and I bias2 ) and has poor noise performance since noise will effectively be introduced into the multistage VGA 10 at each of the input stages 40 and 50. 
     FIG. 2 illustrates a wide control range, single stage VGA, shown generally at 80, according to the present invention. The VGA 80 includes an input circuit 90, a first gain control circuit 95, a second gain control circuit 100 and an output circuit 105. 
     The first gain control circuit 95 includes a first pass circuit including transistors Q303 and Q306 and a first switching circuit including transistors Q304 and Q305. Similarly, the second control circuit 100 includes a second pass circuit including transistors Q307 and Q310, and a second switching circuit including transistors Q308 and Q309. The output circuit 105 includes resistors R301 and R302, off of which the output signal is taken. 
     The collector elements of transistors Q304, Q305, Q308 and Q309 are connected directly to a DC voltage source V CC . The collector elements of transistors Q307 and Q310 are connected to V CC  through the output circuit 105, namely, resistors R301 and R302, respectively. The collector elements of transistors Q303 and Q306 are connected to the emitter elements of transistor pairs Q307/Q308 and Q309/Q310, respectively. The base elements of transistors Q308 and Q309 (the second switching circuit) are connected to gain control voltage pin 110. The base elements of transistors Q307 and Q310 (the second pass circuit) are connected to gain control voltage pin 115. The base elements of transistors Q304 and Q305 (the first switching circuit) are connected to gain control voltage pin 120. The base elements of transistors Q303 and Q306 (the first pass circuit) are connected to gain control voltage pin 125. 
     An input signal is received at the input stage 90. The input stage 90 conventionally converts the input signal, if necessary, to an input current I signal . The input stage 90 may be a current to current input stage, a voltage to current input stage, a transconductor cell, etc. Further, the input current I signal  developed by the input stage 90 may be a magnified or attenuated version of the signal input to the input stage 90. 
     The input current I signal  is superimposed on a DC bias current I bias  flowing from V CC  to ground through transistors Q303, Q304, Q305, Q306, Q307, Q308, Q309, Q310, and resistors R301, R302, dynamically changing the bias current I bias . Since the DC bias current I bias  will generally remain constant on average, its effect on the input current I signal  can be neglected in the following discussion. 
     The input current I signal  is received by the first gain control circuit 95 at the emitter elements of transistors Q303, Q304, Q305 and Q306. Depending upon the gain control voltages applied at gain control voltage pins 120 and 125, which are applied to the base elements of transistor pairs Q304/Q305 and Q303/Q306, respectively, the input current I signal , or portions thereof, will either flow through transistor pairs Q304/Q305 or Q303/Q306. For example, if the gain control voltage at pin 125 is greater than the gain control voltage at pin 120, more of the input current I signal  will flow through transistor pair Q303/Q306 than through transistor pair Q304/Q305. A maximum gain situation would be where all of the input current I singal  flows through transistors Q303 and Q306, while a minimum gain situation would be where all of the input current I signal  flows through transistors Q304 and Q305 to V CC , which is essentially an AC ground. The amount of input current I signal  that flows through transistor pairs Q303/Q306 and Q304/Q305 is controllable by conventionally varying the gain control voltages applied at gain control voltage pins 125 and 120. 
     The portion of the input current I signal  denoted in FIG. 2 as I pass , flowing through transistors Q303 and Q306 is received by the second gain control circuit 100 at the emitter elements of transistor pairs Q307/Q308 and Q309/Q310, respectively. Depending upon the gain control voltages applied at gain control voltage pins 110 and 115, which are applied to the base elements of transistor pairs Q308/Q309 and Q307/Q310, respectively, the current I pass , or portions thereof, will either flow through transistor pairs Q308/Q309 or Q307/Q310. For example, if the gain control voltage applied at pin 115 is greater than the gain control voltage applied at pin 110, more of the current I pass  will flow through transistor pair Q307/Q310 than through transistor pair Q308/Q309. A maximum gain situation would be where all of the current I pass  flows through transistors Q307 and Q310, while a minimum gain situation would be where all of the current I pass  flows through transistors Q308 and Q309 to V CC , which is essentially an AC ground. The amount of current I pass  that flows through transistor pairs Q307/Q310 and Q308/Q309 is controllable by conventionally varying the gain control voltages applied at gain control voltage pins 115 and 110. 
     The portion of the current I pass  flowing through resistors Q307 and Q310 is received by the output circuit 105 at resistors R301 and R302. The output signal is taken off of resistors R301 and R302 at the collector elements of transistors Q307 and Q310, respectively. The output signal may be either a voltage or current, depending upon circuit implementation, and represents an amplitude varied version of the primary input signal. It should be noted that other types of impedance elements which allow a DC current to flow therethrough, such as inductors (discrete or integrated), could be utilized in place of resistors R301 and R302. The impedance elements or resistors themselves may have additional circuitry connected thereto. 
     The novel VGA 80 reduces the amount of bias current necessary for operation, since the first and second gain control circuits 95 and 100 share the same DC bias current i bias . The novel VGA 80 is particularly useful in small size, high talk time cellular phones where battery size is a concern. Further, by reducing the number of VGA stages needed for wide range gain control, the novel VGA 80 also reduces the amount of noise affecting the input signal. 
     In a preferred embodiment, current should flow symmetrically through the novel VGA 80. That is, equal amounts of current should flow through transistors Q304/Q305, Q303/Q306, Q307/Q310 and Q308/Q309, however, the current through each of the transistor pairs does not necessarily need to be equal. Further, for symmetry reasons, typically transistors Q303 and Q306 are equally sized, transistors Q304 and Q305 are equally sized, transistors Q308 and Q309 are equally sized, and transistors Q307 and Q310 are equally sized. However, the transistor pairs do not need to be sized the same. 
     Further, while the VGA 80 is shown in FIG. 2 as including BJTs (Bipolar Junction Transistors), essentially any type of transistor may be implemented without departing from the spirit and scope of the present invention. These include, but are not limited to MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), MESFETs (Metal Semiconductor Field Effect Transistors) and HBTs (Heterojunction Bipolar Transistors). 
     The novel VGA 80 essentially achieves the same amount of gain control as a prior art 2-stage VGA 10 shown in FIG. 1, with a reduction in required DC bias current, noise and chip capacity. If further gain control is required from the novel VGA 80, various options exist. More gain control circuits (third, fourth, fifth, etc.) may be added to the novel VGA 80 between the second gain control circuit 100 and the output stage 105. Alternatively, the signal output from the novel VGA 80 may be applied to a prior art VGA stage, such as the first and second VGA stages 20 and 30 shown in FIG. 1, through conventional DC block capacitors. 
     While the invention has been described with particular reference to the drawings, it should be understood that various modifications could be made without departing from the spirit and scope of the present invention.