Abstract:
A system and method for selectively stacking and interconnecting individual integrated circuit devices to create a high density integrated circuit module. Connections between stack elements are made through carrier structures that provide inter-element connections that substantially follow an axis that is substantially perpendicular to the vertical axis of the stack. The carrier structure provides connection between elements through conductive paths disposed to provide connection between the foot of an upper IC element and the upper shoulder of the lower IC element. This leaves open to air flow most of the vertical transit section of the lower lead for cooling while creating an air gap between elements that encourages cooling airflow between the elements of the stack. A method for creating stacked integrated circuit modules according to the invention is provided.

Description:
TECHNICAL FIELD 
     The present invention relates to aggregating integrated circuits and, in particular, to stacking integrated circuits. 
     BACKGROUND OF THE INVENTION 
     A variety of techniques are used to stack integrated circuits. Some require that the circuits be encapsulated in special packages, while others use circuits in conventional packages. In some cases, the leads alone of packaged circuits have been used to create the stack and interconnect its constituent elements. In other techniques, structural elements such as rails are used to create the stack and interconnect the constituent elements. 
     Circuit boards in vertical orientations have been used to provide interconnection between stack elements. For example, in U.S. Pat. No. 5,514,907 to Moshayedi, a technique is described for creating a multi-chip module from surface-mount packaged memory chips. The devices are interconnected on their lead emergent edges through printed circuit boards oriented vertically to a carrier or motherboard that is contacted by connective sites along the bottom of the edge-placed PCBs. Japanese Patent Laid-open Publication No. Hei 6-77644 discloses vertical PCBs used as side boards to interconnect packaged circuit members of the stack. 
     Others have stacked integrated circuits without casings or carrier plates. Electrical conductors are provided at the edges of the semiconductor bodies and extended perpendicularly to the planes of the circuit bodies. Such a system is shown in U.S. Pat. No. 3,746,934 to Stein. 
     Still others have stacked packaged circuits using interconnection packages similar to the packages within which the integrated circuits of the stack are contained to route functionally similar terminal leads in non-corresponding lead positions. An example is found in U.S. Pat. No. 4,398,235 to Lutz et al. Simple piggyback stacking of DIPs has been shown in U.S. Pat. No. 4,521,828 to Fanning. 
     Some more recent methods have employed rail-like structures used to provide interconnection and structural integrity to the aggregated stack. The rails are either discrete elements that are added to the structure or are crafted from specific orientations of the leads of the constituent circuit packages. For example, in U.S. Pat. No. 5,266,834 to Nishi et al., one depicted embodiment illustrates a stack created by selective orientation of the leads of particularly configured stack elements, while in U.S. Pat. No. 5,343,075 to Nishino, a stack of semiconductor devices is created with contact plates having connective lines on inner surfaces to connect the elements of the stack. 
     More recently, sophisticated techniques have been developed for stacking integrated circuits. The assignee of the present invention has developed a variety of such techniques for stacking integrated circuits. In one such method, multiple conventional ICs are stacked and external leads are interconnected with one another by means of a rail assembly. The rails are made of flat strips of metal and the rails define apertures that receive the leads of the discrete IC packages. An example of this system is shown in U.S. Pat. No. 5,778,522 assigned to the assignee of the present invention. 
     An even more recent technique developed by the assignee of the present invention interconnects conventionally packaged ICs with flexible circuits disposed between stack elements. The flexible circuits include an array of flexible conductors supported by insulating sheets. Terminal portions of the flexible conductors are bent and positioned to interconnect appropriate leads of respective upper and lower IC packages. 
     Some of the previously described systems have required encapsulation of the constituent ICs in special packages. Still others have added rails that must be custom-fabricated for the application. Many have relied upon connections that substantially coincide with the vertical orientation of the stack and thus require more materials while often adding excessive height to the stack. Others that use PCBs have inhibited heat dissipation of the stack. Most have deficiencies that add expense or complexity or thermal inefficiency to stacked integrated circuits. What is needed therefore, is a technique and system for stacking integrated circuits that provides a thermally efficient, robust structure while not adding excessive height to the stack yet allowing production at reasonable cost with easily understood and managed materials. 
     SUMMARY OF THE INVENTION 
     The present invention provides a system and method for selectively stacking and interconnecting individual integrated circuit devices to create a high density integrated circuit module. It is principally designed for use with memory circuits, but can be employed to advantage with any integrated circuits where size conservation and use of duplicative circuitry are present considerations. 
     In a preferred embodiment, conventional TSOP memory circuits are vertically stacked one above the other. The stack consists of two packaged integrated circuits, but alternatives may employ greater numbers of ICs. 
     Connections between stack elements are made through carrier structures that provide inter-element connections that transit from one IC to another IC to conserve material and create a stack having improved air flow and consequent heat transference. This is accomplished by having the interelement connections substantially follow an axis that is substantially perpendicular to the vertical axis of the stack. The carrier structure and inter-element connections cooperate to adapt the inherent structural features of the leads of the constituent elements into a stack framework having appropriate integrity. 
     In a preferred embodiment, electronic connections between stack elements are supported by printed circuit board or other support material. The connection between elements is made by conductive paths disposed to provide connection between the feet of leads of an upper IC element and the upper shoulder of leads of a lower IC element. This leaves open to air flow, most of the transit section of the lower lead for cooling, while creating an air gap between elements that encourages cooling airflow between the elements of the stack and minimizes fabrication complexity. 
     A method for creating stacked integrated circuit modules is provided that provides reasonable cost, mass production techniques to produce modules. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 depicts a circuit module composed of a stack of two packaged integrated circuits devised in accordance with the present invention. 
     FIG. 2 is a view of a connection between two stack elements in the embodiment depicted in FIG.  1 . 
     FIG. 3 shows an alternative embodiment of a circuit module devised in accordance with the present invention. 
     FIG. 4 depicts the connection of the foot of one exemplar lead of an upper IC to an embodiment of the carrier structure of the present invention. 
     FIG. 5 depicts an upper plan view of a printed circuit board structure used in a method of the present invention. 
     FIG. 6 is a lower plan view of the PCB shown in FIG.  5 . 
     FIG. 7 shows an enlarged detail from FIG.  6 . 
     FIG. 8 depicts a sectional view of the connection structure along line C—C of FIG.  7 . 
     FIG. 9 depicts a sectional view of the connection structure along line B-C of FIG.  7 . 
     FIG. 10 depicts a sectional view of the connection structure along line A—A of FIG.  7 . 
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     FIG. 1 depicts a high density memory module  10  devised in accordance with the present invention. The present invention is adaptable to a variety of IC circuits and, in its preferred implementation, memory Circuits of a variety of capacities. Module  10  in created with upper IC  12  and lower IC  14 . Each of ICs  12  and  14  are, in the depicted preferred embodiment, plastic encapsulated memory circuits disposed in thin small outline packages known as TSOPs. Other package types may be used with the present invention as well as packaged circuits other than memories, but, as described here as preferred examples, the invention is advantageously implemented with memories in TSOP packaging. As shown in FIG. 1 as to lower IC  14 , but present in both IC  12  and  14  of module  10 , each IC has a lower surface  16 , upper surface  18  and periphery  20 . In this embodiment, there is an air gap  21  between IC  12  and IC  14  although a heat transference material may reside between the ICs. 
     As depicted in FIG. 2, emergent from package peripheral wall  20 , leads such as illustrated lead  22 , provide a connective pathway for the electronics of the circuitry chip  24  embedded within plastic casing  26  of exemplar IC  12 . Lead  22  of upper IC  12  is shown as having foot  26  and shoulder  28  and transit section  30  but similar features may be identified in lead  22  of lower IC  14 . Shoulder  28  can extend from and include the planar part of lead  22  emergent from peripheral wall  20  (i.e., the “head” of the shoulder identified by reference  31 ) to the end of the curvature into transit section  30 . As leads  22  emerge from the package periphery, a supportive shelf or plane is created or defined (respectively) by the heads of the plurality of leads on a side. These features of lead  22  are present in conventional TSOP packaged memory circuits available from most major suppliers of memories such as Samsung and Micron Technology, for example. Foot  26  is provided to allow the mounting of the TSOP IC on the surface of a printed circuit or other carrier and signal transit board. Shoulder  28  arises from providing foot  26  for surface mount connection of the IC, while transit section  30  of lead  22  connects shoulder  28  with foot  26 . In practice, lead  22  and, in particular, transit section  30  are surfaces from which heat from internal chip  24  is dissipated by local air convection. Transit section  30  is often a substantially straight path but may exhibit curvature. 
     Carrier structure  40  is shown in FIG. 2 as being interposed between shoulder  28  of lead  22  of lower IC  14  and foot  26  of lead  22  of upper IC  12 . Carrier structure  40 , in a preferred embodiment, has upper and lower substantially planar surfaces  45  and  47 , respectively. Upper surface  45  bears a row of upper connective elements  44  and lower surface  47  bears a row of lower connective elements  46 . These elements  44  and  46  may rest on surfaces  45  and  47  or be embedded into those surfaces. In the module, upper connective elements  44  are disposed beneath the feet of the leads of IC  12  and the lower surface  47  is placed along the plane of heads  31  of selected leads of lower IC  14  as shown in FIGS. 2 and 3. While being beneath the feet of the leads, it should be understood that carrier structure  40  and/or upper connective element  44  may have an extent greater or lesser as well as coincident with the feet of the leads of IC  12 . Carrier structure  40  is, in a preferred embodiment, printed circuit board material or other carrier material disposed between corresponding leads of constituent elements of module  10 . Other structures that provide connective elements in an insulative bed or carrier may be employed as carrier structure  40 . So called flex circuit, known to those of skill in the art is an example of an alternative material for carrier structure  40 . Carrier structure  40  retains upper IC  12  in orientation with lower IC  14 . Carrier structure  40  provides a horizontal structure to support electrical connection between appropriate leads of upper and lower ICs  12  and  14 . Although it provides horizontal carriage of the electrical connection, parts of the conductive path may be coincident in orientation to the main axis of module  10 . The principal orientation of the connective paths provided by carrier structure  40  is, however, perpendicular to the main vertical axis of the created module. Thus, the connective path principally follows a horizontal path. The provision of the horizontal carrier provides structural and fabrication advantages not found in simple structures used in previous stacks. For example, such a method and structure exploits the existing lead assemblage of the constituent ICs to craft a module defining cage or framework. Although the leads are provided by the TSOP manufacturer to enable surface mounting (SMT) of the TSOP, the horizontal carrier structure  40  provides advantages to the lead assemblage, namely, a low capacitance carrier for a conductive pathway that allows inter-element spacing, efficient cooling, and simple stack construction and interconnectivity with structural integrity and appropriate height. 
     Two carrier structures  40  are generally used in a two element module  10 . One structure  40  is disposed along one periphery of module  10 , while another carrier structure  40  is disposed in conjunction with an opposite periphery of the module. 
     Carrier structure  40  is preferably devised from printed circuit board. As discussed, other materials may be used as carrier structure  40 . The readily understood technology of PCBs provides, however, and allows, as will be explained below, an efficient and cost-effective method for the fabrication of modules that reflect the invention disclosed here. 
     Carrier structure  40  is soldered into place as shown by solder  42  that improves the connection of foot  26  of upper IC  12  with upper connective element  44  (in this case, a trace) of carrier structure  40 . In the embodiment shown in FIG. 2, connective elements  44  and  46  are etched traces, but other means of providing the connection are known in the art and within the scope of the invention. Solder  42  is also shown providing certain connection between lead  22  of lower IC  14  and lower connective element  46  (in this case, also a trace) of carrier structure  40 . 
     Upper and lower connective elements  44  and  46  are connected to each other in the embodiment shown in FIG. 2 through a plated through hole or via  48  that is drilled in the PCB during stack fabrication. The use of vias to connect conductive planes or traces in PCB technology is well known to those of skill in the art. When a multi-layer PCB board is used as carrier structure  40 , a “blind” via may be used in the path of connection between upper and lower connective elements  44  and  46 . In a preferred embodiment, via  48  is cut through length-wise to create a castellation-like structure. This can be done when the greater part of carrier structure  40  is, in a preferred technique for fabrication of module  10 , routed in a larger PCB board used to construct module  10 . It will be noted, however, that via  48  is shown disposed on the interior of module  10 . This provides protection against environmental hazards. Via  48  may also be disposed on the exterior of module  10 . Placement within module  10  is not essential to the invention either for via  48  or other connective structures used in the present invention to connect upper with lower connective elements  44  and  46 . Further, via  48  need not be bisected. Inside placement will, however, provide sufficient room for connective traces to be provided for efficient differential element enablement. Other connectives besides vias may be used to conduct signals between upper and lower connectives  44  and  46 . For example, a connective element may be used through the body of carrier structure  40 . Traces on the exterior vertical sides of carrier  40  may be used. Alternatively, multi-layer boards may be used to provide the connection. 
     FIG. 3 is a sectional view of a module  10  implemented according to the present invention in which a trace  50  is used to connect upper trace  44  with lower trace  46  of carrier structure  40 . FIG. 4 is a view showing lone lead of upper IC  12  emergent from periphery  20 , the lead having shoulder  28 , transit section  30  and foot  26 . Foot  26  is shown as attached to carrier structure  40 . In this embodiment, carrier structure  40  has been implemented with upper connective elements  44  and specialized upper connective element pad  52 . The use of a discrete pad such as  52  for connection to the foot of the lead is not required, but may be advantageous in embodiments where the pitch between leads allows. It will be noted that in this depiction, connection between upper connective  44  to lower connective element  46  (not shown) is on the inside edge of carrier structure  40  as disposed in place in module  10 . 
     FIG. 5 depicts an upper plan view of a part of a PCB routed and etched to provide a construction structure  59  for the creation of a circuit module of stacked integrated circuits according to an embodiment of the present invention. FIG. 6 is a lower plan view of the PCB shown in FIG.  5 . FIG. 7 shows an enlarged detail from FIG. 6 showing the trace used to provide selective enablement of the constituent elements of module  10 . 
     In FIGS. 5 and 6, orifices  54  are routed openings through a PCB  60  having upper and lower conductive surfaces. The upper and lower conductive surfaces of PCB  60  are etched to create the appropriate pattern for the upper and lower connective elements  44  and  46 , respectively. Central opening  56  provides a space through which the body of lower IC  14  is disposed to allow the shoulders of leads of lower IC  14  to contact lower connective elements (traces)  46  of each of the two carrier structures  40  which are, at this stage of fabrication, still connected to the body of PCB  60  through bridges  57 . Bridges  57  are cut after upper and lower ICs  12  and  14  are soldered into place. 
     In practice, lower IC  14  is disposed upside down (“dead bug”). coincident with central opening  56  as seen in the view of FIG.  6 . Lower IC  14  is preferably placed in position with a pick and place machine or similar precision placement mechanism to accurately dispose the IC relative to the lower connective elements (traces)  46  of the two carrier structures  40 . It will be understood that multiple iterations of construction structure  59  shown in FIGS. 5 and 6 are preferably created in one larger PCB and that the body of lower IC  14  may or may not be emergent into opening  56  depending upon the construction of ICs  12  and  14 . Once construction structure  59  is populated with lower ICs  14 , solder paste and reflow solder techniques known in the art are used to adhere lower IC  14  to the still attached to PCB  60  carrier structures  40 . In a preferred embodiment, once soldered into place, the now populated with lower ICs  14  assembly of multiple stacks in progress is positioned to allow placement of the upper ICs  12  to contact the upper conductive elements  44  shown in FIG.  5 . Again, the assembly is soldered and, after cooling, the carrier structures  40  are cut away from the PCB matrix  60  thus leaving created module(s)  10 . 
     FIG. 7 is an enlargement of area  62  shown in FIG.  6 . The particular one of lower conductive elements  46  shown identified by reference  64  makes contact with an unused no-connect lead of lower IC  14 . To enable upper IC  12 , a signal may be applied to a no connect lead of lower IC  14  that contacts connective element  64  of carrier structure  40 . That signal is conveyed from connective element  64  to the enablement trace  65  that extends from termini  66  to  68 . That connection may be by way of the corresponding upper connective element  44 . From terminus  68  of enablement trace  65 , the signal is brought by way of the appropriate upper connective element  44  to the upper IC  12  lead that receives enable signals. Enablement trace  65  is created to allow a signal applied to a no-connect lead of lower IC  14  to enable upper IC  12  by conveying that enablement signal from the unused lead of lower IC  14  to an enabling active lead of upper IC  12 . Thus, the constituent elements of module  10  may be selectively. enabled in the context of the disclosed invention. Other similar techniques for differential enablement using similar methods may be used. The placement requirements of enablement trace  65  may cause the disposition of the upper to lower connective  53  or via  48  or other connective to be on the interior of the carrier structure relative to the module. 
     FIG. 8 depicts a sectional view of the connection structure along line C—C of FIG.  7 . As shown in FIG. 8, enablement trace terminus  68  is connected through upper connective  44  of carrier structure  40  to the foot  26  of a depicted enable lead of upper IC  12  of module  10 . As shown in FIG. 8, although carrier structure  40  is disposed so as to place its lower surface  47  along the plane of heads  31  of leads  22  of lower IC  14 , there is no connection to shown lead  22  of lower IC  14  and, at this site, lower surface  47  does not touch the lead  22  of the lower IC  14 . Lower surface  47  may touch the lead  22  of lower IC  14 , however, as long as, for this particular site depicting a preferred differential enablement strategy, connection  68  does not contact this particular lead  22  of lower IC  14 . When created, module  10  will, as shown in FIG. 1, have spaced upper IC  12  from lower IC  14 . The space between upper and lower ICs may be left open to air flow or may be filled with a thermally conductive element  72  positioned with thermally conductive adhesive shown at reference  70 . The signal on enablement trace terminus  68  shown in FIG. 8 was conveyed through the body of enablement trace  65  shown in FIG. 9 which depicts FIG. 7 along line A—A. As shown, there is no connection between enablement trace  65  and either the upper or lower connective elements at this point in its transit from terminus  66  to terminus  68 . FIG. 10 is a sectional view along the line B—B of FIG.  7  and shows enablement trace terminus  66  is connected through upper connective element  44  and upper to lower connective  53  and lower connective element  46  to shoulder  28  of lower IC  14  to receive an enable signal for upper IC  12  at a no-connect lead of lower IC  14 . 
     Although the present invention has been described in detail, it will be apparent that those skilled in the art that the invention may be embodied in a variety of specific forms and that various changes, substitutions and alterations can be made without departing from the spirit and scope of the invention. The described embodiments are only illustrative and not restrictive and the scope of the invention is, therefore, indicated by the following claims.