Abstract:
A dynamic random access memory (DRAM) features an address counter strobe test mode device including a reference pulse generator, an address counter strobe test mode unit, an internal address counter unit, and an address decoding unit. The reference pulse generator receives an external clock signal and generates an internal clock signal. The address counter strobe test mode unit receives the internal clock signal and outputs an address strobe signal, wherein a pulse width and a pulse generating time of the address strobe signal are regulated in response to a plurality of control signals outputted from a mode register set. The internal address counter unit receives an external address signal and outputs an internal address signal in response to the address strobe signal. The address decoding unit decodes the internal address signal. As a result, the address counter strobe test mode device prevents mis-operations caused by mis-addressing in the DRAM.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a test mode device for monitoring an operation of an internal address counter, and more specifically, to a technique for regulating a pulse width and a pulse generating time of an address strobe signal to cope with a column fail of the dynamic random access memory (DRAM).  
           [0003]    2. Description of the Prior Art  
           [0004]    As the operating speed (e.g., clock frequency) of a DRAM increases above a threshold, operations that receive a command signal or an address signal inputted externally frequently fail.  
           [0005]    Generally, when an external clock signal of a DRAM transitions, an internal clock signal generated by the external clock signal also transitions. However, as the clock speed tCK (frequency) of the DRAM becomes higher, the internal clock signal does not transition at the same time the external clock signal transitions. As a result, the DRAM does not receive an external address properly. This event is called a column fail.  
           [0006]    Conventionally, a method for regulating a pulse width of an internal clock signal CLKP 4  generated by an external clock signal CLK is used in order to solve the column fail problem.  
           [0007]    An address strobe signal EXTYP 8  and a read/write strobe signal are generated from a pulse signal of the internal clock signal CLKP 4 .  
           [0008]    As a result, if the pulse width of the internal clock signal CLKP 4  is regulated in order to adjust the pulse width of the address strobe signal EXTYP 8 , the pulse width of the read/write strobe signal is also adjusted.  
           [0009]    If the pulse width of the address strobe signal EXTYP 8  is regulated, the pulse widths of relevant signals are simultaneously changed. As a result, there is a limit to the improvement of DRAM performanceachievable using this conventional method.  
           [0010]    [0010]FIG. 1 is a timing diagram illustrating the mis-operation of a conventional address counter circuit. If a pulse width of an internal clock signal changes, a pulse width of the address strobe signal EXTYP 8  is also adjusted, which results in the mis-operation of the conventional address counter circuit.  
           [0011]    As shown in FIG. 1, if an external clock signal CLK is inputted, an internal clock signal CLKP 4  is generated by the external clock signal CLK, and then an address strobe signal EXTYP 8  is generated. Internal addresses ADD_EV&lt;1&gt; and ADD_OD&lt;1&gt; are generated by the address strobe signal EXTYP 8 . Here, the regulated pulse width of the internal clock signal CLK is also applied to the address strobe signal EXTYP 8 .  
           [0012]    After an external address signal ADD&lt;0&gt; transitions from a high to a low level, the address strobe signal EXTYP 8  having the longer pulse width is maintained at a high level for a predetermined time and then transitions to a low level.  
           [0013]    Though the external address signal ADD&lt;0&gt; and the address strobe signal EXTYP 8  are required to be within a cycle of the external clock signal CLK, they are out of cycle with the external clock signal CLK because the pulse width of the address strobe signal EXTYP 8  is lengthened.  
           [0014]    As a result, the address strobe signal EXTYP 8  is maintained at the high level for a predetermined time (A, B, C) and transitions to the low level after the external address signal ADD&lt;0&gt; transitions from the high to low level.  
           [0015]    For the predetermined time (A, B, C), the DRAM accesses a wrong address, thereby generating a mis-operation.  
         SUMMARY OF THE INVENTION  
         [0016]    Accordingly, it is an object of the present invention to provide an address counter strobe test mode device configured to regulate a pulse width and a pulse generating time of an address strobe signal to prevent a column fail.  
           [0017]    In an embodiment, there is an address counter strobe test mode device comprising a reference pulse generator, an address counter strobe test mode unit, an internal address counter unit, and an address decoding unit. The reference pulse generator receives an external clock signal and generates an internal clock signal. The address counter strobe test mode unit receives the internal clock signal and outputs an address strobe signal, wherein a pulse width and a pulse generating time of the address strobe signal are regulated in response to a plurality of control signals outputted from a mode register set. The internal address counter unit receives an external address signal and outputs an internal address signal in response to the address strobe signal. The address decoding unit decodes the internal address signal. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]    [0018]FIG. 1 is a timing diagram illustrating a mis-operation of a conventional address counter circuit.  
         [0019]    [0019]FIG. 2 is a block diagram illustrating an address counter strobe test mode device according to an embodiment of the present invention.  
         [0020]    [0020]FIG. 3 is a circuit diagram illustrating an address counter strobe test mode unit of FIG. 2.  
         [0021]    [0021]FIG. 4 is a timing diagram illustrating the operation of the address counter strobe test mode unit of FIG. 3 when the address strobe pulse generating time is regulated.  
         [0022]    [0022]FIG. 5 is a timing diagram illustrating the operation of the address counter strobe test mode unit of FIG. 3 when the address strobe pulse width is regulated. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0023]    The present invention will be described in detail with reference to the attached drawings.  
         [0024]    [0024]FIG. 2 is a block diagram illustrating an address counter strobe test mode device according to an embodiment of the present invention.  
         [0025]    In this embodiment, the address counter strobe test mode circuit comprises a reference pulse generator  1 , an address counter strobe test mode unit  2 , an internal address counter  3 , an address decoder  4 , and a pad  5 .  
         [0026]    The reference pulse generator  1  receives an external clock signal CLK, and outputs an internal clock signal CLKP 4 .  
         [0027]    The address counter strobe test mode unit  2  receives the internal clock signal CLKP 4  from the reference pulse generator  1 , and control signals TM_FASTER, TM_DELAY, TM_WIDE and TM_NARROW from a mode register set (MRS). Then, the address counter strobe test mode unit  2  outputs an address strobe signal EXTYP 8  of which a pulse width and a pulse generating time are regulated depending on the control signals TM_FASTER, TM_DELAY, TM_WIDE and TM_NARROW.  
         [0028]    The internal address counter  3  receives external address signals ADD&lt;0&gt; and ADD&lt;1&gt; externally, and the address strobe signal EXTYP 8  outputted from the address counter strobe test mode unit  2 , and outputs internal address signals ADD_EV&lt;1&gt; and ADD_OD&lt;1&gt;.  
         [0029]    The address decoder  4  receives the internal address signals ADD_EV&lt;1&gt; and ADD_OD&lt;1&gt; to decode the internal address signals. A user judges a normal operation of the circuit by monitoring the internal address signals ADD_EV&lt;1&gt; and ADD_OD&lt;1&gt; externally by using the pad  5 .  
         [0030]    [0030]FIG. 3 is a detailed circuit diagram illustrating an embodiment of the address counter strobe test mode unit  2  of FIG. 2.  
         [0031]    The address counter strobe test mode unit  2  outputs the address strobe signal EXTYP 8  of which a pulse width and a pulse generating time are regulated depending on the control signals TM_FASTER, TM_DELAY, TM_WIDE and TM_NARROW. Here, the control signals TM_FASTER, TM_DELAY, TM_WIDE and TM_NARROW are outputted from the MRS of the DRAM.  
         [0032]    In an embodiment illustrated in FIG. 3, the address counter strobe test mode unit  2  comprises a pulse generating time controller  20  for regulating a pulse generating time of the internal clock signal CLKP 4  and a pulse width controller  30  for regulating a pulse width of the internal clock signal CLKP 4 .  
         [0033]    According to a particular embodiment illustrated in FIG. 3, the pulse generating time controller  20  comprises a decoder  21 , NAND gates NA 0 -NA 5 , delay units  22 ,  23  and  24 , an inverter I 13 , and a NOR gate NO 0 . The pulse generating time controller  20  delays the internal clock signal CLKP 4  received from the reference pulse generator  1  of FIG. 2 in response to the control signals TM_FASTER and TM_DELAY, and outputs an intermediate clock signal CLKP 5 .  
         [0034]    The decoder  21  decodes the control signals TM_FASTER and TM_DELAY, and outputs four signals into nodes N 0 -N 3 , respectively. The NAND gates NA 0 -NA 3  perform NAND operations on the four output signals from the decoder  21  and the internal clock signal CLKP 4 .  
         [0035]    Specifically, the NAND gate NA 0  performs the NAND operation on an output signal from the node N 0  and the internal clock signal CLKP 4 , and outputs to the NAND operation result to the delay unit  22 . Here, the delay unit  22  comprises inverters I 1  and I 2 .  
         [0036]    The NAND gate NA 1  performs the NAND operation on an output signal from the node N 1  and the internal clock signal CLKP 4 , and outputs the NAND operation result without delay.  
         [0037]    The NAND gate NA 2  performs the NAND operation on an output signal from the node N 2  and the internal clock signal CLKP 4 , and outputs the NAND operation result into the delay unit  23 . Here, the delay unit  23 , comprising inverters I 3 -I 6 , has a longer delay time than the delay unit  22 .  
         [0038]    The NAND gate NA 3  performs the NAND operation on an output signal from the node N 3  and the internal clock signal CLKP 4 , and outputs the NAND operation result into the delay unit  24 . Here, the delay unit  24 , comprising inverters I 7 -Il 2 , has a longer delay time than the delay unit  23 . In this way, each delay unit  22 ,  23  and  24  can control the delay time depending on the number of inverters in each unit.  
         [0039]    The NAND gate NA 4  performs the NAND operation on the output signal from the NAND gate NA 1  and an output signal from the delay unit  22 . The NAND gate NA 5  performs the NAND operation on output signals from the delay units  23  and  24 , and outputs the NAND operation result.  
         [0040]    The NOR gate NO 0  performs a NOR operation on output signals from the NAND gates NA 4  and NA 5 , and outputs an intermediate clock signal CLKP 5  through the inverter I 13 . The pulse generating time of the clock signal CLKP 4  is controlled by the delay units  22 ,  23  and  24 . The intermediate clock signal CLKP 5  is a signal having the regulated pulse generating time of the clock signal CLKP 4 .  
         [0041]    The following Table 1 shows the operation of the pulse generating time controller  20  according to an embodiment of the invention.  
                                     TABLE 1                           Truth table of the pulse generating time controller                    Selection   Selection   Number of       TM_FASTER   TM_DELAY   node   Logic means   Inverters               L   L   N0   NA0   2       H   L   N1   NA1   ×       L   H   N2   NA2   4       H   H   N3   NA3   6                  
 
         [0042]    Table 1 shows the operation of controlling the pulse generating time depending on the logic states of the control signals TM_FASTER and TM_DELAY when the internal clock signal CLKP 4  is enabled.  
         [0043]    When the control signals TM_FASTER and TM_DELAY are all at a low level, the node N 0  is set at a high level. As a result, the internal clock signal CLKP 4  received from the NAND gate NA 0  is delayed for a delay time of the inverters I 1  and I 2  in the delay unit  22 . When the control signal TM_FASTER is at the high level and the control signal TM_DELAY is at the low level, the node N 1  is set at a high level. As a result, the internal clock signal CLKP 4  received from the NAND gate NA 1  is outputted into the NAND gate NA 4  without delay.  
         [0044]    When the control signal TM_FASTER is at the low level and the control signal TM_DELAY is at the high level, the node N 2  is set at a high level. As a result, the internal clock signal CLKP 4  received from the NAND gate NA 2  is delayed for a delay time of the inverters I 3 -I 6  in the delay unit  23 . Here, the delay time of the inverters I 3 -I 6  is longer than that of the inverters I 1  and I 2 .  
         [0045]    When the control signals TM_FASTER and TM-DELAY are all at the high level, the node N 3  is set at a high level. As a result, the internal clock signal CLKP 4  received from the NAND gate NA 3  is delayed for a delay time of the inverters I 7 -Il 2  in the delay unit  24 . Here, the delay time of the delay unit  24  is longer than that of the delay unit  23 .  
         [0046]    In this way, the pulse generating time controller  20  controls the pulse generating time of the internal clock signal CLKP 4  depending on the logic states of the control signals TM_FASTER and TM_DELAY.  
         [0047]    According to a particular embodiment illustrated in FIG. 3, the pulse width controller  30  comprises NOR gates NO 1  and NO 2 , inverters I 14 -I 24 , transmission gates TG 1 -TG 4 , and a NAND gate NA 6 . The pulse width controller  30  controls the pulse width of the intermediate clock signal CLKP 5  depending on the control signals TM_WIDE and TM_NARROW.  
         [0048]    Accordingly, according to an embodiment of the invention, the pulse generating time controller  20  and the pulse width controller  30  regulate the pulse generating time and the pulse width of the clock signal CLKP 4  to output the address strobe signal EXTYP 8 .  
         [0049]    The NOR gate NO 1  performs the NOR operation on the control signals TM_WIDE and TM_NARROW. The transmission gates TG 1  and TG 2  transmits the intermediate clock signal CLKP 5  in response to an output signal from the NOR gate NO 1 .  
         [0050]    The NOR gate NO 2  performs the NOR operation on a non-delayed output signal from the transmission gate TG 2  and a signal delayed by the inverters I 15  and I 16 . An output signal from the NOR gate NO 2  is inverted by the inverter I 20 , and transmitted into the transmission gate TG 3 . Here, the transmission gate TG 3  is controlled by the control signal TM_WIDE.  
         [0051]    The NAND gate NA 6  performs the NAND operation on the non-delayed output signal from the transmission gate TG 2  and a signal delayed by the inverters I 15 -Il 8 . An output signal from the NAND gate NA 6  is inverted by the inverter I 19 , and transmitted into the transmission gate TG 4 . Here, the transmission gate TG 4  is controlled by the control signal TM_NARROW.  
         [0052]    Output signals from the transmission gates TG 1 , TG 3  and TG 4  are delayed by the inverters I 23  and I 24 , and outputted as the address strobe signal EXTYP 8 . &lt;Table 2&gt; Truth table of the transmission gate TM_WIDE TM_NARROW Selection transmission gate  
                                 TABLE 2                           Truth table of the transmission gate                        Selection                   transmission           TM_WIDE   TM_NARROW   gate                       L   L   TG1           H   L   TG2, TG3           L   H   TG2, TG4           H   H   TG2, TG3, TG4                      
 
         [0053]    Table 2 shows the operation of the transmission gates depending on the logic states of the control signals TM-WIDE and TM_NARROW.  
         [0054]    When the control signals TM_WIDE and TM_NARROW are all at a low level, the transmission gate TG 1  operates to output the address strobe signal EXTYP 8  without regulating the pulse width of the intermediate clock signal CLKP 5 .  
         [0055]    When the control signal TM_WIDE is at the high level and the control signal TM_NARROW is at the low level, the transmission gates TG 2  and TG 3  are driven. The NOR gate NO 2  performs the NOR operation on the non-delayed intermediate clock signal CLKP 5  and the delayed intermediate clock signal CLKP 5  delayed by the inverters I 15  and I 16  to widen the pulse width of the intermediate clock signal CLKP 5 . As a result, the pulse width of the address strobe signal EXTYP 8  as an output signal becomes wide.  
         [0056]    When the control signal TM_WIDE is at the low level and the control signal TM_NARROW is at the high level, the transmission gates TG 2  and TG 4  are driven and the intermediate clock signal CLKP 5  is transmitted through the transmission gate TG 2 . The NAND gate NA 6  performs the NAND operation on the non-delayed intermediate clock signal CLKP 5  and the delayed intermediate clock signal CLKP 5  by the inverters I 15 -I 18  to reduce the pulse width of the intermediate clock signal CLKP 5 . As a result, the pulse width of the address strobe signal EXTYP 8  as an output signal becomes narrow.  
         [0057]    When the control signals TM_WIDE and TM_NARROW are all at the high level, the transmission gates TG 2 , TG 3  and TG 4  operate. As a result, the pulse width of the intermediate clock signal CLKP 5  becomes wide and narrow at the same time, and the address strobe signal EXTYP 8  is outputted without regulation of the pulse width.  
         [0058]    In this way, the address strobe signal EXTYP 8  is a signal obtained by regulating the pulse width and the pulse generating time of the internal clock signal CLKP 4 .  
         [0059]    [0059]FIG. 4 is a timing diagram illustrating the operation of the address counter strobe test mode unit of the embodiment illustrated in FIG. 3 when the address strobe pulse generating time is regulated.  
         [0060]    Since the external clock signal CLK has a predetermined clock, the external address signals ADD&lt;0&gt; and ADD&lt;L&gt; have a predetermined clock, respectively. If the internal clock signal CLKP 4  is enabled, the address strobe signal EXTYP 8  is enabled.  
         [0061]    The solid line D shows the waveform of the normal address strobe signal EXTYP 8  passed through the delay unit  22  when the control signals TM_FASTER and TM_DELAY of FIG. 3 are all at the low level.  
         [0062]    The broken line E shows the waveform of the address strobe signal EXTYP 8  when the control signal TM_FASTER is at the high level and the control signal TM_DELAY is at the low level. In this case, the address strobe signal EXTYP 8  is generated earlier than in the normal state D because it does not pass through any delay unit.  
         [0063]    The dash-dot line F shows the waveform of the address strobe signal EXTYP 8  when the control signal TM_FASTER is at the low level and the control signal TM_DELAY is at the high level. In this case, the address strobe signal EXTYP 8  is generated later than in the normal state D because it passes through delay unit  23 .  
         [0064]    [0064]FIG. 5 is a timing diagram illustrating the operation of the address counter strobe test mode unit of the embodiment illustrated in FIG. 3 when the address strobe pulse width is regulated.  
         [0065]    If the internal clock signal CLKP 4  is enabled, the address strobe signal EXTYP 8  is enabled.  
         [0066]    The solid line G shows the waveform of the normal address strobe signal EXTYP 8  when the control signals TM_WIDE and TM_NARROW of FIG. 3 are all at the low level. Here, the pulse width of the address strobe signal EXTYP 8  is not regulated.  
         [0067]    The broken line H shows the waveform of the address strobe signal EXTYP 8  when the control signal TM_WIDE is at the high level and the control signal TM_NARROW is at the low level. Here, the pulse width of the address strobe signal EXTYP 8  is regulated to become wide.  
         [0068]    The dash-dot line I shows the waveform of the address strobe signal EXTYP 8  when the control signal TM_WIDE is at the low level and the control signal TM_NARROW is at the high level. Here, the pulse width of the address strobe signal EXTYP 8  is regulated to become narrow.  
         [0069]    In this way, if the pulse width and the pulse generating time of the address strobe signal EXTYP 8  are regulated, the mis-operation caused by mis-addressing in the DRAM can be prevented  
         [0070]    Accordingly, an address counter strobe test mode device according to an embodiment of the present invention can easily regulate a pulse width and a pulse generating time of the internal clock signal CLKP 4  to prevent a mis-operation caused by mis-addressing in a DRAM operation.  
         [0071]    While the present invention is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, it should be understood that the invention is not limited to the particular forms disclosed. Rather, the invention covers all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined in the appended claims.