Abstract:
A peak detector circuit which provides a direct current output voltage proportional to the peak to peak amplitude of an input signal is disclosed. The peak detector is capable of operating with a variety of input signal waveforms. The utilization of an attenuator network and negative feedback techniques permit automatic and accurate operation over a wide dynamic range of input signal amplitudes. Frequency compensation of the attenuator network is provided to permit operation with input pulses having fast rise times and/or fast fall times. The inherent error due to diode forward conduction voltage is eliminated by the use of a DC restorer network which truly clamps the input signal to ground.

Description:
BACKGROUND OF THE INVENTION 
     This is a continuation-in-part of application Ser. No. 002,086, now abandoned filed on Jan. 9, l979. 
    
    
     This invention relates to detector circuitry. More particularly, it relates to a peak detector circuit which provides a direct current (DC) output voltage that is proportional to the peak to peak amplitude of an input signal. 
     In many applications peak detector circuits are utilized in conjunction with automatic test equipment to provide an accurate reading of the amplitude of an input signal. Illustrative examples of such applications may be found in the aerospace industry. One such example pertains to automatic testing methods utilized to check the operation of sophisticated electronic systems found in modern aircraft. Illustrative of such electronic systems are the various high resolution radar systems such as, for example, ground mapping, weather avoidance and missile guidance found in many types of aircraft. 
     Typically, many radar systems utilize pulse techniques. Accordingly, it is desirable to be able to accurately measure various characteristics, including amplitude, of a pulse waveform. 
     One type of automatic test equipment which finds wide application in the avionics instrumentation field is an analyzer such as, for example, the Hewlett-Packard Series 9500, Automatic Test System. One of the many functions performed by this equipment is to provide an automatic reading of the amplitude of an input pulse signal. When utilized in this mode, the data measured by the analyzer is often acquired and processed by means of a peak detector circuit. 
     To avoid distorting the amplitude characteristics of the pulse waveform prior to its input to the analyzer, it is important that the peak detector utilized to acquire and process the input data be capable of operating over a wide dynamic range of input signal amplitudes and duty cycles. 
     It has been found, however, that many conventional peak detectors are not capable of operating over the wide dynamic range of input signal amplitudes and duty cycles experienced in practice. Similarly, it has been observed that the operational performance and accuracy of many conventional peak detectors tends to degrade over a period of time. Furthermore, many of the conventional circuits utilize a diode in the signal path to effect DC restoration. This further limits the accuracy obtainable as a result of the inherent error attributable to the forward conduction voltage of the diode. 
     Another drawback associated with many of the conventional peak detectors is the inability of the detector to respond to pulses having fast rise times and/or fast fall times. Similarly, many of the conventional peak detectors are limited to operation with pulse input signals. 
     It is accordingly an object of the invention to provide apparatus which provides a direct current output voltage proportional to the peak to peak amplitude of the input signal. More specifically, it is an object of the invention to overcome the aforementioned difficulties and drawbacks associated with conventional peak detector circuits. 
     It is a further object of the invention to provide peak detecting apparatus capable of accurately operating over a wide dynamic range of input signal amplitudes. 
     It is still another object of the invention to provide peak detecting apparatus capable of accurately operating with a variety of different input signal waveforms. 
     Other objects will be apparent in the following detailed description and the practice of the invention. 
     SUMMARY OF THE INVENTION 
     The foregoing and other objects and advantages which will be apparent in the following detailed description of the preferred embodiment, or in the practice of the invention, are achieved by the invention disclosed herein, which generally may be characterized as apparatus for providing a direct current output voltage proportional to the peak to peak amplitude of an input signal comprising: signal processing means adapted to receive said input signal; direct current restoring means operatively connected to said signal processing means; and peak detecting means responsive to said direct current restoring means. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Serving to illustrate an exemplary embodiment of the invention are the drawings of which: 
     FIG. 1 illustrates a block diagram of a peak detector, in accordance with the present invention; and 
     FIG. 2 illustrates a schematic diagram of the peak detector, in accordance with the present invention. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENT 
     In order to afford a complete understanding of the invention and an appreciation of its advantages, a description of a preferred embodiment is presented below. 
     Referring to FIG. 1, a block diagram of a preferred embodiment of the peak detector, in accordance with the present invention, is illustrated. As shown therein, the peak detector consists of a number of functional subsystems comprising an input signal processing network 100, a direct current (DC) restorer network 300 and a peak detector network 400. Input signal processing network 100 includes a compensated attenuator network 150 and a buffer network 200. The compensated attenuator network 150 provides the proper attenuation for the input signal which is AC coupled to the DC restorer network 300 via the buffer network 200. After the signal is restored to a positive level, it is detected by the peak detector network 400 and translated into a DC output voltage which is proportional to the peak to peak amplitude of the input signal. 
     A schematic diagram of the preferred embodiment of the peak detector, in accordance with the present invention, is illustrated in FIG. 2. As shown therein, an input signal is applied to the peak detector through resistor R 1 . When the input signal consists of a pulse, a conventional switch SW 1  is actuated to apply a filter network comprising resistor R 1  and capacitor C 1 . The filter network is provided to smooth out any high frequency ringing on the pulse edges. 
     If the absolute amplitude of the input signal exceeds the maximum absolute dynamic range of the peak detector, the input signal amplitude must be attenuated accordingly. Signal attenuation is achieved through a potentiometric divider network comprising precision resistors R 2 , R 3  and R 4 . The signal attenuation, in increments of 5 to 1, 2 to 1 and 1 to 1, is selected by positions 1, 2 and 3, respectively, of a conventional switch SW 2 . Frequency compensation of the attenuator network is achieved through capacitors C 2 , C 3 , C 4 , C 5  and C 6 . Preferably, capacitors C 4  and C 5  are variable capacitors which may be adjusted to optimize the high frequency response to the attenuator network. 
     A buffer network, consisting of transistors Q 1 , Q 2  and Q 3 , provides a high input impedance to the attenuated input signal and a low output impedance to the DC restorer network. Biasing resistors R 5 , R 6 , R 7 , R 8 , R 9  and R 10  and bypass capacitors C 7  and C 8  are selected in accordance with conventional circuit design techniques. 
     The output of the buffer network is AC coupled through capacitors C 9  and C 10 , in conjunction with diodes CR 1  and CR 2 , to the DC restorer network. The values of C 9  and C 10  are selected to match the frequency characteristics of the input signal. Positive input signals are AC coupled to the DC restorer network via the series path comprising capacitor C 9  and diode CR 2  and negative input signals are AC coupled to the DC restorer network via the series path comprising diode CR 1  and capacitor C 10 . 
     The DC restorer network, consisting of transistors Q 4 , Q 5  and Q 6  and voltage comparator U 1 , provides a positive DC level shift to the AC coupled input signal, i.e., the minimum amplitude of the input signal is clamped to signal ground and the maximum amplitude of the input signal is shifted positively to correspond to the peak to peak amplitude of the input signal. 
     A unique feature of the DC restorer network is that it truly clamps the input signal to ground eliminating the inherent error due to the forward conduction voltage V F , of the clamping diode which is utilized in many conventional DC restoring circuits. The accuracy of the DC restorer network is further enhanced by a negative feedback loop explained in more detail below. 
     The AC coupled output of the buffer network is applied to the DC restorer network via transistors Q 4  and Q 5  which are each configured as emitter followers. Diode CR 3  limits the amplitude of the input voltage applied to the base of transistor Q 4 . The output of the second emitter follower, Q 5 , is applied to the inverting input terminal of voltage comparator U 1  via input resistor R 16 . The non-inverting input terminal of voltage comparator U 1  is connected to ground via DC biasing resistor R 17 . Diode CR 4  limits the amplitude of the input voltage applied to voltage comparator U 1 . Biasing resistors R 11 , R 12 , R 13 , R 14 , R 15 , R 18 , R 19 , R 20 , R 21 , and R 22  and bypass capacitors C 11 , C 12 , C 13  and C 14  are selected in accordance with conventional circuit design techniques. The value of capacitor C 15  is selected in accordance with the recommendations of the manufacturer of voltage comparator U 1 . 
     When the voltage at the output of emitter follower Q 5  is positive with respect to ground, the output of voltage comparator U 1  is negative and transistor Q 6  is non-conductive. Diode CR 5  is also non-conductive and the feedback path between the output of transistor Q 6  and the input to transistor Q 4  is non-conductive. Similarly, when the voltage at the output of emitter follower Q 5  is negative with respect to ground, the output of voltage comparator U 1  is positive and transistor Q 6  is conductive. Diode CR 5  is also conductive and the series path comprising diode CR 5  and resistor R 23  provides a conductive feedback path between the output of transistor Q 6  and the input to transistor Q 4 . The effect of the positive voltage fed back to the input to transistor Q 4  in conjunction with the negative input signal coupled to transistor Q 4  from the output of the buffer network causes the combined input signal to transistor Q 4  to become less negative with respect to ground. Diode CR 5  is conductive as long as the voltage at the output of emitter follower Q 5  remains negative with respect to ground. Ultimately diode CR 5  ceases to conduct and the feedback path between the output of transistor Q 6  and the input to transistor Q 4  becomes non-conductive. The point at which this occurs corresponds to the situation where the voltage at the output of emitter follower Q 5  is clamped to ground, i.e., the minimum amplitude of the input signal is 0 volts DC. At this point the voltage at the output of emitter follower Q 5  is a positive DC restored signal. 
     The positive DC restored signal appearing at the emitter of transistor Q 5  is directly coupled to the peak detector network consisting of voltage comparator U 2 , diodes CR 7 , CR 8  and CR 9 , and buffer amplifier U 3 . The peak detector network detects the peak amplitude of the DC restored signal and provides a DC output voltage equal to that amplitude. 
     The positive DC restored signal appearing at the emitter of transistor Q 5  is applied through resistor R 24  to the non-inverting input terminal of voltage comparator U 2 . The amplitude of the input voltage applied to comparator U 2  is limited by diode CR 6 . The inverting input terminal of comparator U 2  is connected to the output of the peak detector network through a feedback path comprising resistor R 25 . Biasing resistors R 26 , R 27  and R 31  and bypass capacitors C 16 , C 17 , C 19 , and C 20  are selected in accordance with conventional circuit design techniques. Capacitor C 21  is selected to smooth out any high frequency ringing on the DC output signal. Diode CR 9  limits the amplitude of the input voltage applied to buffer amplifier U 3 . 
     As the amplitude of the DC restored signal appearing at the non-inverting input of voltage comparator U 2  increases, the output of U 2  increases causing diodes CR 7  and CR 8  to conduct. This results in storage capacitor C 18  being charged to a positive level. The positive signal at the output of comparator U 2  is coupled to buffer amplifier U 3  via limiting resistor R 30 . As illustrated, buffer amplifier U 3  is configured to provide a gain of unity. Accordingly, the voltage level appearing at the output of buffer amplifier U 3  equals the voltage level on capacitor C 18 . The output of buffer amplifier U 3  is fed back to the inverting input terminal of voltage comparator U 2  via resistor R 25 . It is apparent that the use of negative feedback ensures that capacitor C 18  is charged to a voltage level equal to the peak amplitude of the DC restored signal. 
     The effect of the voltage fed back to the inverting input of voltage comparator U 2  causes the DC output voltage to approach eventually the peak amplitude of the DC restored signal, which is applied to the non-inverting input of U 2 . During the presence of the DC restored signal within each signal period its peak amplitude is compared with the fed back voltage. If the DC output voltage is lower than the peak amplitude of the DC restored signal, the output of comparator U 2  will increase causing capacitor C18 to be charged to a higher voltage level. This in turn results in the DC output voltage increasing accordingly. During the absence of the DC restored signal within the signal period, the output of comparator U 2  will decrease because the fed back voltage is now greater than that at the non-inverting input of U 2 . As a result, Diode CR8 is back biased and becomes non-conductive. Consequently capacitor C18 begins to discharge mainly through resistor R 29  until the reoccurrence of the DC restored signal, at which time capacitor C18 begins to be charged again. As long as the amount of charge gained by capacitor C18 during the charging period is greater than the amount lost during the discharging period, the peak detector network is effective; and hence the DC output will eventually approach the peak amplitude of the DC restored signal. 
     The accuracy of the peak detector depends on the duty cycle and frequency of the input signal, i.e., a higher duty cycle and frequency would result in better accuracy. Resistor R 28  in conjunction with the Discharge terminal provides a path for the capacitor C18 to discharge quickly by external means, such as momentarily grounding the Discharge terminal. 
     Exemplary values for the various components embodied in the circuit of FIG. 2 are as follows. Unless otherwise specified, resistor wattages are 1/4 watts. 
     R 1  : 20 ohms (1/2 watt) 
     R 2  : 135 Kohms (0.1%) 
     R 3  : 80.6 Kohms (0.1%) 
     R 4  : 54.2 Kohms (0.1%) 
     R 5  : 100 Kohms 
     R 6  : 10 Kohms 
     R 7  : 22 Kohms 
     R 8  : 2.2 Kohms 
     R 9  : 1 Kohm 
     R 10  : 220 ohms 
     R 11  : 2.2 Kohms 
     R 12  : 300 Kohms 
     R 13  : 33 Kohms 
     R 14  : 270 ohms 
     R 15  : 1.5 Kohms 
     R 16  : 1 Kohm 
     R 17  : 1 Kohm R 18  : 1 Kohm 
     R 19  : 100 ohms 
     R 20  : 100 ohms 
     R 21  : 33 Kohms 
     R 22  : 1.5 Kohms 
     R 23  : 100 ohms 
     R 24  : 1 Kohm 
     R 25  : 1 Kohm 
     R 26  : 1 Kohm 
     R 27  : 22 Kohms 
     R 28  : 1 Kohm 
     R 29  : 6.2 Mohms 
     R 30  : 100 ohms 
     R 31  : 150 ohms 
     C 1  : 2200 picofarads 
     C 2  : 120 picofarads 
     C 3  : 39 picofarads 
     C 4  : 9-35 picofarads 
     C 5  : 9-35 picofarads 
     C 6  : 50 picofarads 
     C 7  : 0.01 microfarads 
     C 8  : 0.01 microfarads 
     C 9  : 10 microfarads 
     C 10  : 10 microfarads 
     C 11  : 0.01 microfarads 
     C 12  : 0.01 microfarads 
     C 13  : 0.01 microfarads 
     C 14  : 0.01 microfarads 
     C 15  : 850 picofarads 
     C 16  : 0.01 microfarads 
     C 17  : 0.01 microfarads 
     C 18  : 1.5 microfarads 
     C 19  : 0.01 microfarads 
     C 20  : 0.01 microfarads 
     C 21  : 1000 picofarads 
     CR 1  : IN 4148 
     CR 2  : IN 4148 
     CR 3  : IN 4148 
     CR 4  : IN 4148 
     CR 5  : IN 4148 
     CR 6  : IN 4148 
     CR 7  : IN 4148 
     CR 8  : IN 4148 
     CR 9  : IN 4148 
     Q 1  : 2N 2907A 
     Q 2  : 2N 2907A 
     Q 3  : 2N 2907A 
     Q 4  : 2N 2222A 
     Q 5  : 2N 2222A 
     Q 6  : 2N 2222A 
     U 1  : LM 106 
     U 2  : LM 106 
     U 3  : LH 0033 
     Although the above description is primarily in terms of an input signal comprising a pulse waveform, the operation of the peak detector of the present invention works equally as well with any type of input signal waveform. 
     It is clear that the above description of the preferred embodiment in no way limits the scope of the present invention which is defined by the following claims.