Abstract:
A new technique for Hard Disk Drive (HDD) servo-burst demodulation is provided. A 4-samples per dibit Discrete Fourier Transform (DFT) amplitude estimation is used to calculate the read-head servo-position error signal. Comparatively, the conventional method of burst demodulation—called burst integration—typically uses more than 8 samples/dibit. Consequently, the new 4-samples/dibit DFT burst-demodulation scheme requires fewer samples per dibit than does burst integration, thus reducing the disk space occupied by the burst data while increasing the performance as compared to burst integration. Furthermore, the DFT scheme does not require the samples to be synchronized to any particular points of the servo burst, and can include an averaging algorithm that further improves performance for a given Signal to Noise Ratio (SNR). Moreover, the same sample-clocking circuit that detects the Gray Code servo information can also implement the DFT burst-demodulation scheme to demodulate the servo burst.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application is related to U.S. patent application Ser. Nos. ______ (Atty. Docket No. 99-S-190 (1678-22-1)) entitled “DATA-STORAGE DISK HAVING FEW OR NO SPIN-UP WEDGES AND METHOD FOR WRITING SERVO WEDGES ONTO THE DISK,” ______ (Atty. Docket No.01-S-044 (1678-22-2)) entitled “CIRCUIT AND METHOD FOR DETECTING A SERVO WEDGE ON SPIN UP OF A DATA-STORAGE DISK”, ______ (Atty. Docket No. 01-S-047 (1678-22-3)) entitled “CIRCUIT AND METHOD FOR DETECTING A SPIN-UP WEDGE AND A CORRESPONDING SERVO WEDGE ON SPIN UP OF A DATA-STORAGE DISK”, ______ (Atty. Docket No. 01-S-023 (1678-39)) entitled “A DATA CODE AND METHOD FOR CODING DATA”, ______ (Atty. Docket No. 01-S-045 (1678-48)) entitled “CIRCUIT AND METHOD FOR DETECTING THE PHASE OF A SERVO SIGNAL”, ______ (Atty. Docket No. 01-S-054 (1678-49)) entitled “SERVO CIRCUIT HAVING A SYNCHRONOUS SERVO CHANNEL AND METHOD FOR SYNCHRONOUSLY RECOVERING SERVO DATA”, which were filed on the same day as the present application and which are incorporated by reference. 
     
    
     
       FIELD OF THE INVENTION  
         [0002]    The invention is related generally to electronic circuits, and more particularly to a circuit and method for demodulating a read-write-head position burst in a servo wedge without the need for over sampling or synchronization between the sample clock and the servo burst. Such a circuit and method often allows the position bursts to have a higher freqency, thus allowing the bursts to occupy less space on a disk. Furthermore, such a circuit and method often provide more accurate demodulation of the position burst—and thus often allow a more accurate positioning of the read-write head—because their accuracy is unaffected by disk jitter or other events that often degrade the synchronization between the sample clock and the servo signal.  
         BACKGROUND OF THE INVENTION  
         [0003]    As software applications become larger and more data intensive, disk-drive manufacturers are increasing the data-storage capacities of data-storage disks by increasing the disks&#39; data-storage densities (bits/inch). This increase in storage density typically increases the frequency of the read signal from the read-write head of the disk drive that incorporates such a disk.  
           [0004]    Unfortunately, as discussed in more detail below in conjunction with FIGS.  1 - 5 , increasing the density of the servo data, and thus increasing the frequency of the servo signal, may cause a disk drive&#39;s head-position circuit to improperly position the read-write head over a selected data track. A servo circuit typically heavily over samples or uses fewer synchronized samples of the servo signal to calculate the amplitudes of read-write head position bursts that are stored on the disk. Using these burst amplitudes, the disk drive calculates a head-position error signal, which the head-position circuit uses to position the head over the selected data track. But if the frequency of the servo signal is too high, the servo circuit may be unable to generate enough samples for over sampling or maintain synchronization between the sample clock and the servo burst, and thus may calculate inaccurate values for the burst amplitudes. Consequently, these inaccurate values may cause the disk drive to calculate an erroneous value for the head-position error signal, and thus may cause the head-position circuit to improperly position the head over the selected data track.  
           [0005]    [0005]FIG. 1 is a plan view of a conventional disk drive  10 , which includes a magnetic data-storage disk  12 , a read-write head  14 , an arm  16 , and a voice-coil motor  18 . The disk  12  is partitioned into a number—here eight—of disk sectors  20   a - 20   h , and includes a number—typically in the tens or hundreds of thousands—of concentric data tracks  22   a - 22   n . Readable-writable application data is stored in respective data sectors (not shown) within each track  22 . Under the control of the disk drive&#39;s head-position circuit (not shown in FIG. 1), the motor  18  moves the arm  16  to center the head  14  over a selected track  22 .  
           [0006]    Referring to FIG. 2, conventional data servo wedges  24 —only servo wedges  24   a - 24   c  are shown for clarity—include servo data that allows the head-position circuit (not shown in FIG. 2) of the disk drive  10  (FIG. 1) to accurately position the read-write head  14  (FIG. 1) during a data read or write operation. The servo wedges  24  are located within each track  22  at the beginning—the disk  12  spins counterclockwise in this example—of each disk sector  20 . Each servo wedge  24  includes respective servo data that indentifies the location (track  22  and sector  20 ) of the servo wedge. Thus, the head-position circuit uses this servo data to position the head  14  over the track  22  selected to be read from or written to. The manufacturer of the disk drive  10  typically writes the servo wedges  24  onto the disk  12  before shipping the disk drive to a customer; neither the disk drive nor the customer alters the servo wedges  24  thereafter. Servo wedges like the servo wedges  24  are further discussed below in conjunction with FIG. 3 and in commonly owned U.S. patent app. Ser. No. 09/783,801, filed Feb. 14, 2001, entitled “VITERBI DETECTOR AND METHOD FOR RECOVERING A BINARY SEQUENCE FROM A READ SIGNAL,” which is incorporated by reference.  
           [0007]    [0007]FIG. 3 is a diagram of the servo wedge  24   a  of FIG. 2, the other servo wedges  24  being similar. Write splices  30   a  and  30   b  respectively separate the servo wedge  24   a  from adjacent data sectors (not shown). An optional servo address mark (SAM)  32  indicates to the head-position circuit (not shown in FIG. 3) that the read-write head  14  (FIG. 1) is at the beginning of the servo wedge  24   a . A servo preamble  34  allows the servo circuit (not shown in FIG. 3) of the disk drive  10  (FIG. 1) to synchronize the sample clock to the servo signal (FIG. 5), and a servo synchronization mark (SSM)  36  identifies the beginning of a head-location identifier  38 . Once the beginning of the identifier  38  is identified, a disk-drive controller (FIG. 9) can determine the beginnings of head-position bursts A-N by counting cycles of the sample clock. The preamble  34  and SSM  36  are discussed in commonly owned U.S. patent application Ser. No. ______ (Atty. Docket No. 99-S-190 (1678-22-1)) entitled “DATA-STORAGE DISK HAVING FEW OR NO SPIN-UP WEDGES AND METHOD FOR WRITING SERVO WEDGES ONTO THE DISK,” ______ (Atty. Docket No. 01-S-044 (1678-22-2)) entitled “CIRCUIT AND METHOD FOR DETECTING A SERVO WEDGE ON SPIN UP OF A DATA-STORAGE DISK”, ______ (Atty. Docket No. 01-S-047 (1678-22-3)) entitled “CIRCUIT AND METHOD FOR DETECTING A SPIN-UP WEDGE AND A CORRESPONDING SERVO WEDGE ON SPIN UP OF A DATA-STORAGE DISK”, ______ (Atty. Docket No. 01-S-054 (1678-49)) entitled “SERVO CIRCUIT HAVING A SYNCHRONOUS SERVO CHANNEL AND METHOD FOR SYNCHRONOUSLY RECOVERING SERVO DATA”, which are incorporated by reference. The location identifier  38  allows the head-position circuit to coarsely determine and adjust the position of the head  14  with respect to the surface of the disk  12  (FIG. 1). More specifically, the location identifier  38  includes a sector identifier  40  and a track identifier  42 , which respectively identify the disk sector  20  and the data track  22 —here the sector  20   a  and the track  22   a —that contain the servo wedge  24   a . Because the head  14  may read the location identifier  38  even if the head is not centered over the track  24   a , the servo wedge  24   a  also includes the head-position bursts A-N, which allow the head-position circuit to finely determine and adjust the position of the head  14  as discussed below in conjunction with FIGS. 4 and 5.  
           [0008]    [0008]FIG. 4 is a close-up view of a portion  48  of the disk  10  (FIG. 1), the portion  48  including four sections  50 A- 50 D of head-position bursts A-D, respectively. More specifically, the portion  48  includes adjacent tracks  22   n - 22   n+7 , the illustrated portions of which include the servo wedges  24  (FIG. 3), burst sections  50 A- 50 D, and write splices  30  and/or application data. Each of the bursts in sections  50 A- 50 D is two tracks wide in a radial direction and is staggered with respect to the tracks  22  such that the boundaries  52  and  54  between adjacent bursts in the same section are aligned with the centers of respective tracks  22 . For example, the boundary  52   i+1  between adjacent bursts A j  and A j+1  and B j  and B j+1 , is aligned with the center of the track  22   n+2 . Furthermore, the bursts in each section  50 A- 50 D alternate between a logic 1 (represented by an “X”) value and a logic 0 (represented by a blank, i.e., the absence of an “X”) value, and the values of the bursts in sections  50 A and  50 C are opposite to the values of the adjacent bursts in sections  50 B and  50 D, respectively. For example, bursts A j , A j+1 , and A j+2  in section A have alternating values 0, 1, 0, respectively, and adjacent bursts A j+1  and B j+1  have opposite values logic 1 and logic 0, respectively. In one example, logic 1 represents a nonzero voltage level, and logic 0 represents a zero voltage level.  
           [0009]    In operation, the head-position circuit (not shown in FIG. 4) uses the relative magnitudes of diagonally adjacent bursts in sections  50 A and  50 B or in sections  50 C and  50 D to center the head  14  (FIG. 1) over a desired track. For example, assume that the head-position circuit is to center the head  14  over the track  22   n+2 . First using a conventional technique omitted here for clarity, the head-position circuit coarsely positions the head  14  over or near the track  22   n+2  and reads the track identifier  42  (FIG. 3) that the head  14  is over. If the read track identifer belongs to the track  22   n+2 , then the head-position circuit determines that the head  14  is close enough to the track  22   n+2  to proceed with the fine positioning of the head. Because the boundary  52   i+1  is aligned with the center of the track  22   n+2 , to center the head  14  the disk drive  10  (FIG. 1) reads and compares the magnitudes of the diagonally adjacent bursts A j+1  and B j  and calculates a position-error signal proportional to the difference between the magnitudes of A j+1  and B j . The head-position circuit uses this error signal to move the head  14  toward, and ideally over, the center of the track  22   n+2 .  
           [0010]    More specifically, the disk drive  10  (FIG. 1) and the head-position circuit (not shown in FIG. 4) operate according to Table I to center the head  14  (FIG. 1) over the track  22   n+2 , where Mag A equals the read-voltage level, i.e., magnitude, of A j+1 , and Mag B equals the read-voltage level, i.e., magnitude, of B j  (A j  and B j+1 , which are logic 0, have zero voltage levels in this example):  
                       TABLE I                           First   Mag A &gt; Mag B   To center the head over track 22n + 2 if       Scenario       the head 14 is not centered over the track               22 n+2  and is closer to the track 22 n+3 , the               head-position circuit needs to moves the               head 14 toward/to the center of the track               22 n+2  in a direction toward the center               (bottom of FIG. 4) of the disk 10.       Second   Mag A = Mag B   The head 14 is centered over the track       Scenario       22 n+2 . Therefore, the head-position circuit               does not need to move the head 14 for               track 22n + 2 centering . . .        Third   Mag A &lt; Mag B   The head 14 is not centered over the track       Scenario       22 n+2 , and is closer to the track 22 n+1 .               Therefore, the head-position circuit moves               the head 14 toward/to the center of the               track 22 n+2  in a direction toward the center               of the disk 10.                  
 
           [0011]    To illustrate the first scenario, assume that after coarse positioning, the head  14  is over the track  22   n+3  at a position R, which is a radial distance +Dr from the center M of the track  22   n+2 —the center M is aligned with the boundary  52   i+1 . When the disk  10  (FIG. 1) rotates such that the head  14  is aligned with the burst section  50 A, the burst A j+1  is directly beneath the head such that the servo-signal voltage level, Mag A, has a maximum value. Conversely, when the disk  10  rotates such that the head  14  is aligned with the burst section  50 B, the head is radially spaced +Dr from the boundary  52   i+1 , and thus from the burst B j , such that the servo-signal voltage level, Mag B, has a nonmaximum value that is less than Mag A. Because Mag A&gt;Mag B, the disk drive  10  “knows” the direction of the head-position error, i.e., that the head  14  is closer to the track  22   n+3  than to the track  22   n+1 . Furthermore, |Mag A-Mag B| is proportional to the distance Dr between the head  14  and the center of the track  22   n+2 . Therefore, Mag A and Mag B together provide the disk drive  10  with the magnitude and direction of the head-position error, and the disk drive uses this vector to generate a position-error signal. In response to the position-error signal, the head-position circuit (not shown in FIG. 4) causes the motor  18  (FIG. 1) to reduce the head-position error by moving the head  14  from the position R toward/to the center M of the track  22   n+2 .  
           [0012]    To illustrate the second scenario, assume that after coarse positioning, the head  14  is over the center M of the track  22   n+2 . When the head  14  is over the burst sections  50 A and  50 B, it is aligned with the boundary  52   i+1 . Because the boundary  52 i+1  is equidistant from the bursts A j+1  and B j  in a radial direction, Mag A=Mag B. Because Mag A=Mag B, the disk drive  10  “knows” that the head  14  is centered over the track  22   n+2 , and thus “knows” that no position correction is necessary. This follows from |Mag A-Mag B|=0, which indicates that the error distance is zero.  
           [0013]    To illustrate the third scenario, assume that after coarse positioning, the head  14  is over the track  22   n+1  at a position Q, which is a radial distance −Dq from the center M of the track  22   n+2 __ “−”indicates that Dq and Dr are in opposite directions from M. Therefore, because Mag B&gt;Mag A, the disk drive  10  “knows” that the head  14  is closer to the track  22   n+1  than to the track  22   n+3 , and thus generates a corresponding position-error signal. In response to this position-error signal, the head-position circuit that causes the motor  18  to move the head  14  from Q toward/to the center M of the track  22   n+2 .  
           [0014]    Although the servo-wedge portions (to the left of the bursts  50 A- 50 D) of the tracks  22  are shown as having the same widths as the corresponding data-sector portions (to the right of the bursts  50 A- 50 D) portions, these portions may have different widths. Where the widths are different, the boundaries  52  and  54  are aligned with the centers of the data-sector portions to accurately read the application data.  
           [0015]    [0015]FIG. 5 is a plot of a sinusoidal servo signal that the head  14  (FIG. 1) generates while reading a head-position burst, and a sample clock that is not synchronized to the burst sinusoid.  
           [0016]    According to one conventional technique, the servo circuit (not shown in FIG. 5) synchronizes the sample clock to the servo signal as the head  14  reads the preamble  34  (FIG. 3). Typically, this preamble servo signal (not shown) is a sinusoid similar or identical to the burst sinusoid, and the servo circuit aligns the edges of the sample clock to the peaks and zero crossings of the preamble sinusoid. For example, the servo circuit may align the rising edges of the servo clock with the peaks and the falling edges with the zero crossings. Unfortunately, by the time that the head  14  is over the position-burst sections  50 A- 50 D (FIG. 4), phenomena such as noise and disk jitter may cause the edges of the sample clock to become offset from the peaks and zero crossings of the burst sinusoid. For example the rising and falling edges of the sample clock may respectively lead the peaks and zero crossings of the burst sinusoid by a nonzero angle α, where it is desired that α equal zero.  
           [0017]    Unfortunately, the lack of synchronization between the sample clock and the burst sinusoid may cause the head-position circuit (not shown in FIG. 5) to improperly position the head  14  over the selected track  22  (FIG. 4) during the fine positioning of the head. Typically, the peak voltage level Y of the burst sinusoid is the magnitude (e.g., Mag A or Mag B of FIG. 4) of the postion burst. In FIG. 4 for example, |Y|&gt;0 represents a logic 1 (represented by an “X”) and Y=0 (DC signal) represents a logic 0 (represented by the absence of “X”). Furthermore, the accuracy of the algorithm that the disk drive  10  (FIG. 1) uses to demodulate, ie., calculate the magnitudes of, the position bursts is often proportional to the level of synchronization between the sample clock and the burst sinusoid. For example, assuming perfect synchronization, the samples  60  taken at the rising edges of the sample clock are of the burst-sinusoid peaks, and thus equal Y. Therefore, a simple algorithm averages a number of the samples  60  to filter out noise and calculates the burst magnitude equal to this average. But if the clock and burst sinusoid are imperfectly aligned as shown, then, ignoring noise and jitter, this algorithm yields an incorrect burst magnitude Y cosα instead of the correct burst magnitude Y. This incorrect burst magnitude may cause the disk drive  10  to calculate an inacccurate position-error signal, which may cause the motor  18  (FIG. 1) to move the head  14  to an undesired position.  
           [0018]    Still referring to FIG. 5, according to another conventional technique, one can overcome the above-described lack of synchronization by heavily oversampling the burst sinusoid. To oversample, one increases the frequency of the sample clock with respect to the burst sinusoid. But because there are often contraints on the speed of the sample clock, one typically reduces the frequency of the burst sinusoid by lengthening the bursts  50 A- 50 D (FIG. 4). To obtain accurate estimation of the burst amplitude Y, it is generally accepted that the sample clock must generate at least ten samples per cycle of the burst sinusoid, and thus must have a frequency at least five times that of the burst sinusoid. Comparitively, for the above-described synchronous technique, the sample clock generates four samples  60  and  62  per cycle and has a frequency that is twice that of the burst sinusoid as shown in FIG. 5.  
           [0019]    Unfortunately, although heavily oversampling allows one to calculate the burst amplitude Y with an unsynchronized sampling clock, it typically requires more disk space due to the above-described lengthening of the position bursts  50 A- 50 D (FIG. 4).  
         SUMMARY OF THE INVENTION  
         [0020]    In accordance with an embodiment of the invention, a circuit receives fewer than ten samples per cycle of a position burst and calculates the burst magnitude from the samples such that the accuracy of the burst magnitude is independent of the timing of the samples with respect to the burst.  
           [0021]    By using an algorithm that does not require heavy over sampling—for purposes of this application, heavy over sampling is a sampling rate more than four samples per cycle—and that is independent of the level of synchronization between the sample clock and the position bursts, such a circuit often allows shorter position bursts than a heavy-over-sampling circuit allows and calculates the burst magnitudes and the head-position-error signal more accurately than a circuit that uses a timing-dependent algorithm.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]    [0022]FIG. 1 is a plan view of a conventional disk drive.  
         [0023]    [0023]FIG. 2 is a close-up view of some tracks and servo wedges on the disk of FIG. 1.  
         [0024]    [0024]FIG. 3 is a diagram of a servo wedge of FIG. 2.  
         [0025]    [0025]FIG. 4 is a close-up view of some tracks and position bursts on the disk of FIG. 1.  
         [0026]    [0026]FIG. 5 is a plot of a conventional burst sinusoid and a conventional sample clock that is not synchronized to the burst sinusoid.  
         [0027]    [0027]FIG. 6 is a block diagram of a position-burst demodulator according to an embodiment of the invention.  
         [0028]    [0028]FIG. 7 is a phase diagram used to explain how the demodulator of FIG. 6 calculates the magnitude of a position burst according to an embodiment of the invention.  
         [0029]    [0029]FIG. 8 is a block diagram of a servo circuit that incorporates the position-burst demodulator of FIG. 6 according to an embodiment of the invention.  
         [0030]    [0030]FIG. 9 is a block diagram of a disk-drive system that incorporates the servo circuit of FIG. 8 according to an embodiment of the invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0031]    [0031]FIG. 6 is a block diagram of a position-burst demodulator  70  according to an embodiment of the invention. As discussed below in conjunction with FIG. 7, the circuit uses a variation of a known trigonometric identity to calculate the magnitude of a position burst (FIGS. 4 and 5 ) independently of the synchronization, or lack thereof, between the sample clock (FIG. 5) and the postion burst. In the embodiment discussed in conjunction with FIG. 6, the demodulator  70  is part of a servo circuit (FIG. 8) and provides a head-position-error signal to a head-position circuit (FIG. 9). Alternatively, the demodulator  70  may be part of the head-position circuit.  
         [0032]    [0032]FIG. 7 is a phase diagram of a positive half period of the burst sinusoid of FIG. 5, and illustrates how the position-burst demodulator  70  of FIG. 6 calculates a synchronization-independent value for the magnitude Y of the burst sinusoid. Specifically, samples  90  and  92  are 90° apart. Therefore, one can calculate the amplitude Y according to the following equations, which follow from the well-known trigonemetric identity Sin 2 β+Cos 2 β=1:  
         ( Y  Sin β) 2 +( Y  Cos β) 2   =Y   2  Sin 2   β+Y   2 Cos 2    β=Y   2 (Sin 2 β+Cos 2 β)= Y   2    (1)  
         Sample  90 = Y  Sin β 2    (2)  
         Sample  92 = Y  Cos β 2    (3)  
           Y   2 =(sample  90 ) 2 +(sample  92 ) 2    (4)  
           Y ={square root}{square root over ((sample  90 ) 2 +(sample  92 ))} 2    (5)  
         [0033]    Further details of this identity are discussed in commonly owned U.S. patent app. Ser. No. 09/503,949, filed Feb. 14, 2000, entitled “A CIRCUIT AND METHOD FOR CONTROLLING THE GAIN OF AN AMPLIFIER BASED ON THE SUM OF SAMPLES OF THE AMPLIFIED SIGNAL”, and U.S. patent app. Ser. No. 09/503,399, filed Feb. 14, 2000, entitled “A CIRCUIT AND METHOD FOR CONTROLLING THE GAIN OF AN AMPLIFIER”, which are incorporated by reference.  
         [0034]    Referring again to FIG. 6, in one embodiment the demodulator  70  improves upon the above-described trigonometric identity by effectively averaging the samples of the burst sinusoid of FIGS. 5 and 7 to filter out noise. For example purposes, the operation of the demodulator  70  is described where the head-position circuit (FIG. 9) is attempting to center the head  14  (FIGS. 1 and 9 ) over the track  22   n+2  (FIG. 4), it being understood that the operation of the demodulator  70  is similar when the head-position circuit attempts to center the head over another track.  
         [0035]    More specifically, referring to FIGS.  4 - 6 , an adder  72   a  sums the magnitudes of a number—for example eight—of even samples  60  of the position burst A j+1  to generate a sum E, and an adder  72   b  sums the magnitudes of the same number of odd samples  62  of the same postion burst to generate a sum O. In one embodiment, the adders  72   a  and  72   b  respectively generate the sums E and O by summing the negative of every other sample. For example, the even sample  60   a  is positive, but the next even sample  60   b  is negative. Therefore, the adder  72   a  sums the samples  60   a  and  60   c , which are positive values, with the negatives of the samples  60   b  and  60   d , these negatives also being positive values (the negative of a negative is a positive). Likewise, the adder  72   b  sums the samples  62   a  and  62   c  with the negatives of the samples  62   b  and  62   d . Although one could generate E equal to a single sample  60  and O equal to a single sample  62 , summing multiple samples  60  and  62  to respectively generate E and O averages out noise that may contaminate the burst sinusoid.  
         [0036]    The functions of the adders  72   a  and  72   b  is represented by the following equations:  
           E =(sample  60   a −sample  60   b )+(sample  60   c −sample  60   d )   (6)  
           O =(sample  62   a −sample  62   b )+(sample  62   c −sample  62   d )   (7)  
         [0037]    Next, multipliers  74   a  and  74   b  respectively square E and O and a summer  76  sums E 2  and O 2  according to equation (4), where E effectively corresponds to “sample  90  ” and  0  effectively corresponds to “sample  92  ”.  
         [0038]    Then, a root circuit  78  takes the square root of E 2 +O 2  to generate the magnitude Mag A of the burst A j+1 , and stores Mag A in a first memory  80   a.    
         [0039]    Next, the demodulator  70  calculates the magnitude Mag B of the burst B j  in a similar manner and stores Mag B in a second memory  80   b.    
         [0040]    Then, a subtractor  82  calculates the head-position-error signal equal to Mag B−Mag A. The polarity (+or −) of the signal indicates the direction of the error, and the value |Mag B−Mag A| indicates the magnitude of the error. Using the error signal, the head-position circuit (FIG. 9) finely postions the head  14  as discussed above in conjunction with FIG. 4. In other embodiments, however, the subtractor  82  may calculate the error signal equal to Mag A—Mag B, or the demodulator  70  or head-position circuit may further process the error signal before using it to finely position the head  14 .  
         [0041]    Although the demodulator  70  is described as including respective circuit blocks  72   a - 80   b , in other embodiments the demodulator may include a processor or logic circuit programmed to implement the above-described algorithm. Furthermore, the demodulator  70  may use other algorithms to calculate E 2 , O 2 , and MAG A and MAG B. For example, the circuit  70  can square an even sample  60  to generate E 2 , square the next odd sample  62  to generate O 2 , take the square root of E 2 +O 2 , and sum the resulting square roots of E 2 +O 2  over a number of samples  60  and  62  to obtain MAG A or MAG B. Other algorithms are contemplated but are omitted for brevity.  
         [0042]    [0042]FIG. 8 is block diagram of a synchronous servo circuit  100 , which includes the position-burst demodulator  70  of FIG. 6 according to an embodiment of the invention. The circuit  100  includes a gain and filter circuit  102 , which adjusts the gain and filters the servo signal from the read head  14 . An analog-to-digital converter (ADC)  104  receives the sample clock (FIG. 5) on a control bus  106  and generates digital samples, such as the samples  60  and  62  (FIG. 5), of the analog servo signal from the circuit  102 . A finite-impulse-response (FIR) filter  108  equalizes the samples from the ADC  104 , and timing and gain recovery loops  110  effectively synchronize the sample clock to the servo signal and maintain the gain of the circuit  100  at a desired level. In one embodiment, the circuit  102  and FIR filter  108  equalize the servo signal to a PR4 target, although they may equalize the servo signal to another target such as EPR4. A Viterbi detector  112  recovers servo data such as the location identifier  38  (FIG. 3) from the servo-signal samples, and a sync-mark detector  114  recovers the servo sync mark  36  (FIG. 5) from the servo signal. If the servo data is encoded, a decoder  116  decodes the recovered servo data and sync mark from the Viterbi and sync mark detectors  112  and  114 , respectively. The position-burst demodulator  70  receives the even and odd samples  60  and  62  (FIG. 5) from the FIR  108  and generates the head-position-error signal, and a processor  118  controls the components of the servo circuit  100  via the control bus  106 . A servo-data interface  120  interfaces the decoder  116 , processor  118 , and demodulator  70  to a disk-drive controller (FIG. 9).  
         [0043]    Because the demodulator  70  implements a timing-independent algorithm as discussed above, it can calculate the position-error signal without introducing additional latency into the algorithm. Specifically, the timing-recovery portion of the loops  110  synchronizes the sample clock to the servo signal by shifting the values of the samples, not by shifting the phase of the sample clock. Therefore, if the demodulator  70  required synchronized samples, it would need to receive them from a point after the timing-loop portion of the loops  110 , which would introduce significant latency into the burst-demodulation calculation. But because the burst-demodulation algorithm is timing independent, the demodulator  70  can receive the potentially unsynchronized burst samples from the FIR  108 , and thus calculate the position-error signal without the latency of the loops  110 .  
         [0044]    Still referring to FIG. 8, the circuit  102 , ADC  104 , FIR  108 , loops  110 , Viterbi detector  112 , decoder  116 , processor  118  and operation of the servo circuit  100  are further discussed in commonly owned patent applications ______ (Atty. Docket No. 99-S-190 (1678-22-1)) entitled “DATA-STORAGE DISK HAVING FEW OR NO SPIN-UP WEDGES AND METHOD FOR WRITING SERVO WEDGES ONTO THE DISK,” ______ (Atty. Docket No. 01-S-044 (1678-22-2)) entitled “CIRCUIT AND METHOD FOR DETECTING A SERVO WEDGE ON SPIN UP OF A DATA-STORAGE DISK”, ______ (Atty. Docket No. 01-S-047 (1678-22-3)) entitled “CIRCUIT AND METHOD FOR DETECTING A SPIN-UP WEDGE AND A CORRESPONDING SERVO WEDGE ON SPIN UP OF A DATA-STORAGE DISK”, ______ (Atty. Docket No. 01-S-054 (1678-49)) entitled “SERVO CIRCUIT HAVING A SYNCHRONOUS SERVO CHANNEL AND METHOD FOR SYNCHRONOUSLY RECOVERING SERVO DATA”. The timing-recovery loop of the loops  110  is further discussed in commonly owned U.S. patent app. Ser. No. 09/387,146, filed Aug. 31, 1999, entitled “DIGITAL TIMING RECOVERY USING BAUD RATE SAMPLING”, and the gain-recovery loop of the loops  110  and the Viterbi detector  112  are also discussed in commonly owned patent app. Ser. No. 09/783,801, (Atty. Docket No. 99-S-185 (1678-21)), filed Feb. 14, 2001, entitled “VITERBI DETECTOR AND METHOD FOR RECOVERING A BINARY SEQUENCE FROM A READ SIGNAL,” all of which are incorporated by reference. The sync mark detecor  114  is further discussed in commonly owned patent application ______ (Atty. Docket No. 01-S-045 (1678-48)) entitled “CIRCUIT AND METHOD FOR DETECTING THE PHASE OF A SERVO SIGNAL”, and the decoder  116  may be constructed to decode servo data that is encoded according to the scheme discussed in commonly owned U.S. patent app. Ser. Nos. 09/783,801, (Atty. Docket 99-S-185 (1678-21)), filed Feb. 14, 2001, entitled “VITERBI DETECTOR AND METHOD FOR RECOVERING A BINARY SEQUENCE FROM A READ SIGNAL”, or the scheme discussed in ______ (Atty. Docket No. 01-S-023 (1678-39)) entitled “A DATA CODE AND METHOD FOR CODING DATA”, which are incorporated by reference.  
         [0045]    [0045]FIG. 9 is a block diagram of a disk-drive system  200  that incorporates the servo circuit  100  of FIG. 8 according to an embodiment of the invention, where like numbers reference components common to FIGS. 1 and 9. The disk-drive system  200  includes a disk drive  202 , which incorporates the servo circuit  30  of FIG. 8. The disk drive  202  includes the read-write head  14 , a write channel  206  for generating and driving the head  14  with a write signal, and a write controller  208  for interfacing the write data to the write channel  206 . The disk drive  202  also includes a read channel  210  for receiving servo and application-data read signals from the head  32  and for recovering data from these read signals, and includes a read controller  212  for organizing the read data. Together, the write and read controllers  208  and  212  compose a disk-drive controller  213 . The read channel  210  includes the servo circuit  30 , which receives the servo signal from the head  14 , recovers the servo data from the servo signal, and provides the recovered servo data to a head-position circuit  214 . The disk drive  202  further includes a storage medium such as one or more disks  215 , each of which may contain data on one or both sides and which may be magnetic, optical, or another type of storage disk. For example, the disks  215  may be similar to the disk  12  of FIG. 1. The head  14  writes/reads the data stored on the disk  12 , and is connected to the movable support arm  16 . As discussed above in conjunction with FIGS.  6 - 7 , the servo circuit  100  calculates the position-error signal, and, in response to the error signal, the head-position circuit  214  provides a control signal to the voice-coil motor (VCM)  18 , which positionally maintains/radially moves the arm  16  so as to positionally maintain/radially move the head  14  over the desired data tracks on the disks  215 . A spindle motor (SPM)  220  and a SPM control circuit  222  respectively rotates the disks  215  and maintains them at the proper rotational speed.  
         [0046]    The disk-drive system  200  also includes write and read interface adapters  224  and  226  for respectively interfacing the disk-drive controller  213  to a system bus  228 , which is specific to the system used. Typical system busses include ISA, PCI, S-Bus, Nu-Bus, etc. The system  200  typically has other devices, such as a random access memory (RAM)  230  and a central processing unit (CPU)  232  coupled to the bus  228 .  
         [0047]    As discussed above, although the burst demodulator  70  (FIG. 6) is described as being part of the servo circuit  100 , it may be part of the head-position circuit  214  instead.  
         [0048]    From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention.