Abstract:
After an output signal is inverted by an inverter circuit, the resultant signal is differentiated by a differentiating circuit. The connecting states of selectors are changed so that only when the signal level of the differentiated output exceeds a predetermined threshold value, the output signal is sent through a resistor. After the output signal is buffered by a buffering circuit, the resultant signal is differentiated by a differentiating circuit. The connecting states of selectors are changed so that only when the signal level of the differentiated output exceeds a predetermined threshold value, the output signal is sent through a resistor.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an undershoot/overshoot protecting circuit, in particular, to an undershoot/overshoot a protecting circuit for removing a noise of a waveform inputting circuit. 
     2. Description of the Related Art 
     Generally, crosstalk takes place due to stray coupling of adjacent signals. The crosstalk results in noise of a waveform. The amount of noise varies depending on the level of the waveform and the amount of overshoot or undershoot. Thus, to suppress noise caused by crosstalk, overshoot and/or undershoot should be prevented. 
     In a waveform inputting circuit for use with an LSI (Large Scale Integrated circuit), to prevent overshoot and/or undershoot from taking place, a clamp diode has been used. 
     However, in the conventional circuit using such a clamp diode, the through rate of the input waveform cannot be adjusted. Thus, when a waveform with a sharp leading/trailing edge is input, crosstalk takes place between leads of the LSI. 
     As described in Japanese Patent Laid-open Publication No. Hei6-35582, ringing tends to take place in a high speed bus. So far, the drawback of the above related art has not been solved. 
     SUMMARY OF THE INVENTION 
     The present invention is made from the above-described point of view. An object of the present invention is to provide an undershoot/overshoot protecting circuit that adjusts the through rate of an input waveform and prevents crosstalk from taking place between leads of an LSI against a waveform having a sharp leading/trailing edge without an increase of delay time. 
     A first aspect of the present invention is an undershoot protecting circuit, comprising an inverter circuit for inverting an output signal, a differentiating circuit for differentiating the output signal of the inverter circuit, an undershoot suppressing device for suppressing undershoot of the output signal, and a switching circuit for changing the connecting state of an output signal line so that only when the differentiated output signal of the differentiating circuit exceeds a predetermined threshold level, the output signal is sent through the undershoot suppressing device. 
     A second aspect of the present invention is an overshoot protecting circuit, comprising a buffering circuit for buffering an output signal, a differentiating circuit for differentiating an output of the buffering circuit, an overshoot suppressing device for suppressing overshoot of the output signal, and a switching circuit for selecting a connecting state of an output signal line so that only when the signal level of the differentiated output signal exceeds a predetermined threshold value, the output signal is sent through the overshoot suppressing device. 
     The undershoot/overshoot protecting circuit according to the present invention prevents undershoot and/or overshoot from taking place. In addition, the time period until the signal level of the waveform becomes a predetermined threshold level does not vary. Thus, the undershoot/overshoot protecting circuit can suppress crosstalk noise from taking place without an increase of delay time. 
     These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of a best mode embodiment thereof, as illustrated in the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     FIG. 1 is a block diagram showing the structure of an undershoot/overshoot protecting circuit according to an embodiment of the present invention; 
     FIGS. 2 a  to  2   f  are schematic diagrams showing the operations of individual portions of the undershoot/overshoot protecting circuit shown in FIG. 1; and 
     FIG. 3 is a schematic diagram showing an example of the internal structure of a differentiating circuit of the undershoot/overshoot protecting circuit shown in FIG.  1 . 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENT 
     Next, with reference to the accompanying drawings, an embodiment of the present invention will be described. 
     FIG. 1 is a block diagram showing the structure of an undershoot/overshoot protecting circuit according to an embodiment of the present invention. In FIG. 1, an input terminal  100  is connected to a terminal  11  of a selector  1 . A terminal  12  of the selector  1  is connected to a terminal  22  of a selector  2 . 
     A terminal  13  of the selector  1  is connected to a terminal  201  of a resistor  20 . A terminal  202  of the resistor  20  is connected to a terminal  23  of the selector  2 . A terminal  21  of the selector  2  is connected to a terminal  31  of a selector  3 . A terminal  32  of the selector  3  is connected to a terminal  42  of a selector  4 . The selectors  1  to  4  are switches that change the connection states corresponding to respective control signals. Each of the selectors is composed of for example two MOS FETs. The inputs of the MOS FETs are common. A control signal is directly supplied to the control gate of one MOS FET. In addition, the control signal is supplied to the control gate of the other MOS FET through an inverter. The input signal is output from one of the two MOS FETs corresponding to the control signal. 
     A terminal  33  of the selector  3  is connected to a terminal  101  of a resistor  10 . A terminal  102  of the resistor  10  is connected to a terminal  43  of a selector  4 . 
     A terminal  41  of the selector  4  is connected to a waveform input portion  200 , an input portion of a buffering circuit BUF, and an input portion of an inverter circuit INV. 
     An output portion of the buffering circuit BUF is connected to an input portion of a differentiating circuit  12 . An output portion of the differentiating circuit  12  is connected to one terminal of a pull down resistor  40 . An output signal of the differentiating circuit  12  becomes a selector signal SELL of the selector  1  and a selector signal SEL 2  of the selector  2 . The other terminal of the pull down resistor  40  is connected to the ground. 
     An output portion of the inverter circuit INV is connected to an input portion of a differentiating circuit  11 . An output portion of the differentiating circuit  11  is connected to one terminal of a pull down resistor  30 . An output signal of the differentiating circuit  11  becomes a selector signal SEL 3  of the selector  3  and a selector signal SEL 4  of the selector  4 . The other terminal of the pull down resistor  30  is connected to the ground. 
     In this example, the delay time of the selectors  1  to  4  is represented by Ts. The delay time of the gate of the buffering circuit BUF is represented by Tb. The delay time of the gate of the inverter circuit INV is represented by Ti. The delay time of the differentiating circuits  11  and  12  is represented by Td. The threshold voltage of the buffering circuit BUF, the inverter circuit INV, and the selector signals SEL 1  to SEL 4  is represented by Vt. In this case, it is assumed that a waveform with a large amount of overshoot is input to the input terminal as shown in FIG. 2 a.    
     At this point, the output portion of the differentiating circuit  11  is connected to the ground through the pull down resistor  30 . Thus, the signal level of the output portion of the differentiating circuit  11  is low. In addition, the output portion of the differentiating circuit  12  is connected to the ground through the pull down resistor  40 . Thus, the signal level of the output portion of the differentiating circuit  12  is low. Consequently, the signal levels of the selector signal SEL 1  of the selector  1 , the selector signal SEL 2  of the selector  2 , the selector signal SEL 3  of the selector  3 , and the selector signal SEL 4  of the selector  4  are low. At this point, the waveform at the terminal  11  of the selector  1  passes through the terminal  12  of the selector  1 , the terminals  22  and  21  of the selector  2 , the terminals  31  and  32  of the selector  3 , and the terminals  42  and  41  of the selector  4 . Thus, a waveform as shown in FIG. 2 b  is input to the waveform input portion  200 , the input portion of the buffering circuit BUF, and the input portion of the inverter circuit INV. 
     The waveform that is output from the output portion of the buffering circuit BUF is input to the input portion of the differentiating circuit  12 . The waveform at the input portion of  10 . The differentiating circuit  12  is as shown in FIG. 2 c.  In addition, the waveform that is output from the output portion of the inverter circuit INV is input to the input portion of the differentiating circuit  11 . The waveform at the input portion of the differentiating circuit  11  is as shown in FIG. 2 d.    
     At this point, the waveform at the output portion of the differentiating circuit  11  is as shown in FIG. 2 e.  The waveform is input to the selectors  3  and  4  as the selector signals SEL 3  and SEL 4 , respectively. In this case, since the signal level of the waveform does not exceed the threshold voltage Vt, the selecting states of the selectors  3  and  4  do not vary. 
     The waveform at the output portion of the differentiating circuit  12  is as shown in FIG. 2 f.  The waveform at the output portion of the differentiating circuit  12  is input to the selectors  1  and  2  as the selector signals SEL 1  and SEL 2 , respectively. In this case, the signal level of the waveform exceeds the threshold voltage Vt for a time period Tds. Thus, the selecting state of the selector  1  is changed from the terminal  12  to the terminal  13  for the time period Tds. In addition, the selecting state of the selector  2  is changed from the terminal  22  to the terminal  23 . 
     Until the waveform is input to the selector  2  through the selector  1  (namely, while the terminal  13  of the selector  1  and the terminal  23  of the selector  2  are being selected), the resistor  20  causes the waveform to be dull. Thus, a waveform having a resistance against crosstalk noise is input to the waveform input portion  200 . 
     When a waveform with a trailing edge having a large amount of undershoot is input to the input terminal, likewise, the time period of the trailing edge becomes long. Thus, a waveform having a resistance against crosstalk noise is input to the waveform input portion  200 . 
     Each of the differentiating circuits  11  and  12  shown in FIG. 1 is composed of a capacitor C and a resistor R as shown in FIG.  3 . The capacitor C is connected in series to the signal line between the input portion and the output portion. The resistor R is connected between the signal line and the ground. Thus, the differentiating circuits  11  and  12  can be composed of known differentiating circuits. When time constants of the differentiating circuits  11  and  12  are properly selected, the waveforms as shown in FIGS. 2 e  and  2   f  can be obtained. 
     With only the buffering circuit BUF, the differentiating circuit  12 , the selectors  1  and  2 , and the resistor  20 , it is clear that at least overshoot can be prevented. Likewise, with only the inverter circuit INV, the differentiating circuit  11 , the selectors  3  and  4 , and the resistor  10 , it is clear that at least undershoot can be prevented. 
     In the above-described embodiment, the undershoot/overshoot protecting circuit for use with an LSI was described. However, it should be noted that the undershoot/overshoot protecting circuit can be applied to other than an LSI. 
     As described above, since undershoot and/or overshoot can be prevented without varying a time period until the signal level of a waveform becomes a threshold level, crosstalk noise can be suppressed without an increase of delay time. 
     Although the present invention has been shown and described with respect to a best mode embodiment thereof, it should be understood by those skilled in the art that the foregoing and various other changes, omissions, and additions in the form and detail thereof may be made therein without departing from the spirit and scope of the present invention.