Abstract:
A method for forming a trench capacitor is presented in the following process steps. A trench is formed on a semiconductor substrate. A first trench dielectric is deposited into the trench without reaching a full height thereof. An etch stop layer is formed on the first trench dielectric and along inner surfaces of the trench. A second trench dielectric is deposited on the etch stop layer. The second trench dielectric and the etch stop layer are removed to expose the first trench dielectric in the trench. A conductive layer is formed on the first trench dielectric in the trench, such that the conductive layer, the first trench dielectric and the semiconductor substrate function as a trench capacitor.

Description:
BACKGROUND  
       [0001]     The present invention relates generally to semiconductor processing technology, and more particularly to a method for fabricating a trench capacitor.  
         [0002]     An isolation structure is a basic structure for separating transistors and other circuit elements on an integrated circuit (IC). Shallow trench isolation (STI) and local oxidation of silicon (LOCOS) are two typical isolation structures used in ICs. An STI is formed by filling dielectric materials into a trench adjacent to a circuit element, such as a MOS transistor. A LOCOS is formed by selectively oxidizing a predetermined location in the IC. As the ICs continue to scale down, the STI becomes more popular than LOCOS, since the STI occupies less space than LOCOS, and offers better isolation performance.  
         [0003]     Capacitors are common circuit elements in an IC. While capacitors may be conveniently constructed anywhere in the IC, there are specific locations where they can be constructed efficiently. For example, it is desirable to construct them on certain locations in order to avoid parasitic reactance. In addition, since it is costly to design new processes only for the purpose of capacitor fabrication, it is also desirable to produce them, using the processes and materials that are already involved in the fabrication of other devices in the IC.  
         [0004]     It is therefore advantageous to construct capacitors in STI trenches that are close to one or more devices. For example, a dynamic random access memory (DRAM) cell typically involves a capacitor constructed close to a MOS transistor. While conventional methods provide techniques for constructing a capacitor in an STI trench, there are issues pertaining thereto. Specifically, conventional methods for constructing capacitors in STI trenches yield capacitors that have damaged silicon surfaces adjacent to the capacitor dielectric material. This may cause leakage current, thereby compromising the circuit performance.  
         [0005]     Therefore, desirable in the art of semiconductor processing technology are methods for forming high quality capacitors in the STI trenches.  
       SUMMARY  
       [0006]     The present invention discloses a method for forming a trench capacitor. In one embodiment of the invention, the method is presented in the following process steps. A trench is formed on a semiconductor substrate. A first trench dielectric is deposited into the trench without reaching a full height thereof. An etch stop layer is formed on the first trench dielectric and along inner surfaces of the trench. A second trench dielectric is deposited on the etch stop layer. The second trench dielectric and the etch stop layer are removed to expose the first trench dielectric in the trench. A conductive layer is formed on the first trench dielectric in the trench, such that the conductive layer, the first trench dielectric and the semiconductor substrate function as a trench capacitor.  
         [0007]     The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]      FIG. 1  is a circuit diagram of a one-transistor DRAM cell.  
         [0009]      FIGS. 2A-2F  illustrate cross sections of a semiconductor structure in various stages during a conventional process for constructing an STI structure.  
         [0010]      FIGS. 3A-3L  illustrate cross sections of a semiconductor structure in various stages during a process for constructing a trench capacitor in accordance with one embodiment of the present invention.  
         [0011]      FIG. 4  is a process flow for preparing an STI structure in accordance with one embodiment of the present invention.  
         [0012]      FIG. 5  is a process flow for preparing a trench capacitor based on the STI structure in accordance with another embodiment of the present invention. 
     
    
     DESCRIPTION  
       [0013]     The following provides a detailed description of a method for preparing a trench capacitor used in a one-transistor DRAM cell. It is however noted that the trench capacitor can be used together with devices other than a DRAM cell.  
         [0014]     In  FIG. 1 , a circuit diagram  100  illustrates a one-transistor DRAM cell. The cell is accessed from a bit line  102 , through a transistor  104  that is switched by a word line  106 . A signal from the bit line  102  is stored in a capacitor  108  as a measured charge. This charge stored in the capacitor  108  lasts for a short time, after which, it must be read, and then rewritten back into the same capacitor as a refreshed data bit.  
         [0015]      FIGS. 2A-2F  illustrate cross sections of a semiconductor structure in various stages during a conventional process for constructing an STI structure in preparation for construction of a capacitor later on. In  FIG. 2A , a cross section  200  shows a semiconductor substrate  202  with a photoresist layer  204  that has been patterned, a silicon nitride hard mask  206  that has been etched, and a pad oxide  208  that has been etched. The semiconductor substrate  202  is ready to be etched anisotropically.  
         [0016]     In  FIG. 2B , a cross section  210  illustrates a semiconductor structure, in which a trench  212  and a lining oxide  216  are formed. During the processes of forming such semiconductor structure, the photoresist layer  204  (shown in  FIG. 2A ) is firstly removed. An anisotropic etching process is performed using the silicon nitride hard mask  206  as a shield to form the trench  212  in the semiconductor substrate  202 . Since the etchant gas used by the anisotropic etching process is specific to silicon, no substantial damage would occur to the silicon nitride hard mask  206  and the pad oxide  208 . The exposed semiconductor surface  214  within the trench  212  is then covered by a lining oxide  216 .  
         [0017]     In  FIG. 2C , a cross section  218  illustrates a semiconductor structure, in which a trench oxide  220  is deposited to fill the trench  212 , and covers the silicon nitride hard mask  206 . In  FIG. 2D , a cross section  222  illustrates a semiconductor structure, in which trench oxide  220  has been planarized by technologies, such as overflow-dump-rinse (ODR) etching or chemical mechanical polish (CMP).  
         [0018]     In  FIG. 2E , a cross section  224  illustrates a semiconductor structure, in which the trench oxide  220  and the lining oxide  216  have been further etched. A portion of the trench oxide  220  remains in the trench  212 . In  FIG. 2F , a cross section  226  illustrates a semiconductor structure, in which the silicon nitride hard mask  206  and pad oxide  208 , shown in  2 E, are removed. This prepares the trench  212  for a further construction of a capacitor thereon.  
         [0019]     During the process of etching the planarized trench oxide  220  (shown in  FIG. 2D ), a time mode etching control scheme is used, meaning that the etching process is stop when a certain period of time has run. Due to process variation of the etching, the time mode etching control scheme may not provide the remaining trench oxides  220  (shown in  FIG. 2E ) with a consistent thickness. Moreover, the etching process may cause damage to the exposed semiconductor surface  214 . As a result, the conventional method may cause leakage current or other reliability issues to the capacitor that will be constructed on the trench oxide  220 .  
         [0020]      FIGS. 3A-3L  illustrate cross sections of a semiconductor structure in various stages during a process for constructing a trench capacitor in accordance with one embodiment of the present invention. In  FIG. 3A , a cross section  300  shows a semiconductor substrate  302  with a photoresist layer  304  that has been patterned and the first and second dielectric layers  308  and  306  that have been etched. The semiconductor substrate  302  is ready to be etched anisotropically. It is understood that the first and second dielectric layers  308  and  306  can be any dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, etc. In this embodiment, the first dielectric layer  308  can be a pad oxide layer, and the second dielectric layer  306  can be a silicon nitride hard mask.  
         [0021]     In  FIG. 3B , a cross section  310  illustrates a semiconductor structure, in which a trench  312  and a lining dielectric layer  316  are formed. During the processes of forming such semiconductor structure, the photoresist layer  304  (shown in  FIG. 3A ) is firstly removed. An anisotropic etching process is performed using the second dielectric layer  306  as a shield to form the trench  312  in the semiconductor substrate  302 . Since the etchant gas used by the anisotropic etching process is specific to silicon, no substantial damage would occur to the first and second dielectric layers  308  and  306 . The exposed semiconductor surface  314  within the trench  312  is then covered by a lining dielectric layer  316 .  
         [0022]     In  FIG. 3C , a cross section  318  illustrates a semiconductor structure, in which a first trench dielectric  320  and an etch stop layer  322  are formed. During the process of the forming such semiconductor structure, the first trench dielectric  320  is deposited on the second dielectric layer  306  and partially fills the trench  312 . The deposition is carried out by technology, such as high-density plasma chemical vapor deposition (HDPCVD), wherein the adjustment of its process parameters can balance deposition and sputter etch rates in order to avoid forming voids in the first trench dielectric  320 . The depth of the first trench dielectric  320  depends on various circuit designs. In this embodiment, the dielectric-fill progresses up to leaving a depth of about  3 , 000  A for the first trench dielectric  320 . An etch stop layer  322  (shown in the bold line) is deposited along inner surfaces of the trench  312 . This etch stop layer  322  covers the first trench dielectric  320 , the lining dielectric layer  316 , and the sidewalls of the first and second dielectric layers  308  and  306  in the trench  312 . The etch stop layer  322  will protect the lining dielectric layer  316  and the otherwise exposed semiconductor surface  314  from an etching process that will follow. It is noted that the etch stop layer  322  and the first trench dielectric  320  can be made substantially of any dielectric materials. In this embodiment, the etch stop layer  322  and the first trench dielectric  320  can be made substantially of silicon nitride and silicon oxide, respectively.  
         [0023]     In  FIG. 3D , a cross section  324  illustrates a semiconductor structure, in which a second trench dielectric  326  is deposited on the etch stop layer  322  and fills the space inside the trench  312 . This second trench dielectric  326  deposition can be carried out by HDPCVD. Again, the adjustment of process parameters can balance deposition and sputter etch rates in order to avoid the formation of voids in the second trench dielectric  326 .  
         [0024]     In  FIG. 3E , a cross section  328  illustrates a semiconductor substrate, in which the second trench dielectric  326  has been planarized by technologies such as reverse-pattern ODR etching and CMP. In  FIG. 3F , a cross section  330  illustrates a semiconductor structure, in which the second trench dielectric  326 , shown earlier in  FIG. 3E , has been etched down to the etch stop layer  322 . The first trench dielectric  320  fills the remaining depth of the trench  312  below the etch stop layer  322 . An etchant gas that is specific to removing the second trench dielectric  326  has been used. This etchant gas barely etches the etch stop layer  322 . The etch is controlled by end-point-mode, which means that the etching process is analyzed in real time and the process is ended when the second trench dielectric  326  has been etched away and the etch stop layer  322  has been fully exposed. This mode of process control is more precise and material, responsive than the conventional simple time-mode etching. Thus, the depth of the first trench dielectric  320  can be well controlled, and the surface  314  of the semiconductor substrate  302  can be well protected from damage during the etching process.  
         [0025]     In  FIG. 3G , a cross section  332  illustrates the remaining semiconductor structure after the second dielectric layer  306 , the first dielectric layer  308 , and the etch stop layer  322 , all shown in  FIG. 3F , have been removed. The first trench dielectric  320  remains in the trench  312 .  
         [0026]     To completely form a trench capacitor for a DRAM cell, the process steps for forming the same are explained by referring to a series of cross sections of the semiconductor structure shown in  FIGS. 3H-3L . In  FIG. 3H , a cross section  334  illustrates a semiconductor structure, in which a sacrificial oxide  301  is grown on the surface of the semiconductor substrate  302  that was exposed by the first trench dielectric  320  remaining in the trench  312 . The growth of the sacrificial oxide  301  consumes surface contaminants and minor surface defects, such as crystal defects and implant damage. The sacrificial oxide  301  is then etched away in order to provide a fresh surface for the construction of critical structures to follow.  
         [0027]     In  FIG. 3I , a cross section  336  illustrates a semiconductor structure  336 , in which a gate dielectric layer  303  is formed on the surface of the semiconductor substrate  302  that had been covered by the first dielectric layer  308  (shown in  FIG. 3B ), and also on its surface  314  exposed by the first trench dielectric  320  that remains in the trench  312 .  
         [0028]     In  FIG. 3J , a cross section  338  illustrates a semiconductor structure, in which a polycrystalline silicon(poly) layer  305  is deposited on the gate dielectric layer  303 . In  FIG. 3K , a cross section  340  illustrates a semiconductor structure, in which the poly-silicon layer  305  and the gate dielectric layer  303  are patterned to form an upper capacitor electrode  307 , and MOS gates  309  and  311 . The gate dielectric layer  303  also forms the capacitor dielectric under the upper capacitor electrode  307 . The lower capacitor electrode is the semiconductor substrate  302 .  
         [0029]     In  FIG. 3L , a cross section  342  illustrates a semiconductor structure, in which a functional memory cell is constructed from the semiconductor structure shown in  FIG. 3K . Low-doped drains  313  are implanted. Sidewall spacers  315  are formed on the sides of the upper capacitor electrode  307 , and the MOS gates  309  and  311 . The sources/drains  317  are implanted. Metal silicide is formed on the exposed silicon portions of the sources/drains  317  of MOS transistors  319  and  323 , and the upper capacitor electrode  307 . The MOS transistor  319  and the capacitor  321  form a one-transistor DRAM cell.  
         [0030]     As discussed above, the proposed method can protect the semiconductor adjacent to the trench from being damaged during the construction of the trench capacitor. Furthermore, it can well control the thickness of the remaining trench dielectric in the trench. As a result, the current leakage of the trench capacitor constructed by the proposed method is improved.  
         [0031]      FIG. 4  presents a process flow  400  for preparing a trench for the further construction of the trench capacitor in accordance with one embodiment of the present invention. In step  402 , a photoresist layer is patterned and first and second dielectric layers are etched, as shown in  FIG. 3A . In step  404 , a trench is etched anisotropically and a dielectric liner is formed, as shown in  FIG. 3B . In step  406 , the trench is partially filled with the first trench dielectric and an etch stop layer is deposited, as shown in  FIG. 3C . In step  408 , the remaining trench is filled with the second trench dielectric, as shown in  FIG. 3D . In step  410 , the second trench dielectric is planarized down to the second dielectric layer, as shown in  FIG. 3E . In step  412 , the second trench dielectric is etched down to the etch stop layer in the trench, as shown in  FIG. 3F . In step  414 , the second dielectric, the etch stop layer, and the first dielectric are removed, as shown in  FIG. 3G .  
         [0032]      FIG. 5  is a flow  500  for forming a trench capacitor on the trench in accordance with one embodiment of the present invention. In step  502 , a sacrificial oxide is formed inside the trench walls, as shown in  FIG. 3H , and then etched away. In step  504 , a gate dielectric layer is formed inside the trench walls, as shown in  FIG. 3I . In step  506 , a poly-silicon layer is deposited, as shown in  FIG. 3J . In step  508 , transistor gate and capacitor patterns are defined in the poly-silicon layer, as shown in  FIG. 3K . In step  510 , MOS transistor structures and capacitor with silicides are completed, as shown in  FIG. 3L .  
         [0033]     The above illustration provides many different embodiments or embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims.  
         [0034]     Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.