Abstract:
A method for comparing two signal with increased accuracy by using a reduced offset voltage comparator that has a offset zero mode and amplify mode. Additional comparators are used to indicate when the two signal are close in value. When the signal are close the reduced offset voltage comparator operation is changed from offset zero mode to amplify mode and the two signal are compared.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The benefits of filing this invention as Provisional application for patent “REDUCED OFFSET VOLTAGE COMPARATOR SYSTEM”, U.S. PTO Ser. No. 60/755,115 filed Dec. 31, 2005 by Fred Mirow are claimed. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates to differential comparator systems with offset voltage reduction. 
       BACKGROUND OF THE INVENTION 
       [0003]    A comparator, in its basic form, compares two input signals to determine which one is of higher magnitude. It outputs a high or low response depending on whether a first input is higher than a second input. Comparators have internal sources of errors that cause the output voltage level transitions to occur at a level different than when the input voltage levels transitions pass being equal. This error is referred to as the offset voltage. 
         [0004]    One current way of way of compensating for offset voltage is by trimming the device. In this method, a set of resistors is implanted on a chip. During the manufacturing process, but after the chip is made, the bias is determined and compensated for by fusing or severing the links between the resistors on the chip. On-chip trimming techniques can reduce offset voltage to a very low value. 
         [0005]    The trimming technique has a drawback in that it is one time or a single shot operation and is therefore only provides compensation for the offset at the conditions under which it was tested. For a system that may undergo a wide range of operating conditions, trimming may not be optimal. This is because the actual comparator offset voltage value is subject to deviations due to variations in input common mode voltage, temperature, and supply voltage. 
       SUMMARY OF THE INVENTION 
       [0006]    The present invention is a method for comparing two signals with increased accuracy by using a reduced offset voltage comparator. This comparator has a offset zero mode and amplify mode. Additional conventional comparators are used to indicate when the two signal are close in value. When the signals are close the reduced offset voltage comparator operation is changed from offset zero mode to amplify mode. The reduced offset voltage comparator is now used to make an accurate comparison of the two signal levels. When the conventional comparators indicate that the two signal are not close in value, the reduced offset voltage comparator operation is changed from amplify mode to offset zero mode. During the offset zero mode the reduced offset voltage comparator reduces the offset voltage is to almost zero. 
         [0007]    Mechanical stress, thermal stress, and other operating condition variations will not significantly effect performance because the reduced offset voltage comparator circuit frequently returns to the offset zero mode to keep reducing the offset voltage. Further, if the offset is stored digitally as opposed to with a capacitor, the circuit can extend periods of time between returns to the offset zero mode. 
         [0008]    The present invention solves the problem of maintaining a desired low offset voltage over a wide range of operating conditions including common mode voltage, temperature, and supply voltage even as the conditions change. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0009]      FIG. 1  is a schematic representation of a Reduced Offset Voltage Comparator System  100  in accordance with one embodiment of the present invention. 
           [0010]      FIG. 2  is a schematic representation of Amplifier System  50 A in accordance with one embodiment of the present invention. 
           [0011]      FIG. 3  is a diagram illustrating various Reduced Offset Voltage Comparator System  100  circuit waveforms. 
       
    
    
     DETAILED DESCRIPTION 
       [0012]    The Reduced Offset Voltage Comparator System  FIG. 1  consist of three comparators  17 ,  14 , and  8 . The input signal at terminal  1  is applied to line  13 . Comparators  14  has it&#39;s positive input connected to reference voltage  15  and it&#39;s negative input connected to line  13 . Comparators  17  has it&#39;s negative input connected to reference voltage  18  and it&#39;s positive input connected to line  13 . 
         [0013]    Amplifier system  50  has it&#39;s negative input connected to reference voltage  5  and it&#39;s positive input connected to line  13 . Comparators  8  has it&#39;s negative input connected to ground and it&#39;s positive input connected to the output of Amplifier system  50 . Comparators  8  output is on line  21 . Comparator  17  output is on line  20  and Comparator  14  output is on line  22 . Line  20  and  22  are connected to the inputs of NOR gate  16 . The output of NOR gate  16  on line  11  is low when either line  20  or  22  is high. Line  20  is also connected to the input of Time delay  33 . Output terminal  9  is connected by switch  19  to either the output of Comparator  8  or Time delay  33 . 
         [0014]    Reference voltage  5  is set to the same value as the input signal level that is to be detected by comparison. Reference voltage  18  is set greater than that of reference voltage  5  and Reference voltage  15  is set less than that of reference voltage  5  so that comparators  17  and  14  output signal transitions always occurs at a higher or lower input signal level than Reference voltage  5  level under all conditions including their own internal offset voltages. 
         [0015]    When the voltage level at input terminal  1 , as shown at time A in  FIG. 3 , is less than that of voltage references  15  and  18  the signal on line  22  is high, the signal on line  20  is low, and the signal on line  11  is low. Output terminal  9  is connected by switch  19  to output of Time delay  33 . The output of Time delay  33  is the same level as line  20  which is low. 
         [0016]    Amplifier system  50  has two operating modes. When line  11  is high it is in amplify mode and when line  11  is low it is in offset zero mode. Amplifier system  50  is now in offset zero mode in which the signal at input  1  is not being amplified and the offset voltage of Amplifier system  50  is being stored. 
         [0017]    When the voltage level at input terminal  1  as shown at time B in  FIG. 3  is less than that of voltage references  18  and  5  but greater than that of voltage reference  15 . The signal on lines  20  and  22  are both low and the signal on line  11  is now high. Amplifier system  50  is now in amplify mode in which the signal at input  1  is being amplified and the input offset is being compensated for. Amplifier system  50  output signal is applied to the input of Comparator  8 . Since the input signal at input  1  was multiplied by the gain of Amplifier system  50 , the effective error at input  1  caused by the offset voltage of Comparator  8  is reduced. 
         [0018]    Time delay  30  and  33  are controlled by the signal level of line  11 . When line  11  goes high, Time delay  30  and  33  have their input signals delayed by a fixed time period. The delay time of Time delay  33  is longer than that of Time delay  30  line  11  also provides a high signal level to the input of Time delay  30 . The delay time produced by Time delay  30  allows Amplifier system  50  and Comparator  8  to stabilize at their correct low output level. Time delay  33  maintains the low signal level on line  34  even though the signal at its input on line  20  has now gone high. Output terminal  9  is now connected by switch  19  to line  21 . 
         [0019]    When the voltage level at input terminal  1  as shown at time C in  FIG. 3  is less than that of voltage references  18 , but greater than that of voltage reference  15  and  5 . The signal on lines  20  and  22  are still both low and the signal on line  11  is high. Output terminal  9  is still connected by switch  19  to line  21 . Amplifier system  50  is still in amplify mode and the signal at input  1  is being amplified and then applied to the input of Comparator  8 . The output of Comparator  8  is now high and applied to output terminal  9  through switch  19 . 
         [0020]    When the voltage level at input terminal  1  increases to the level as shown at time D in  FIG. 3 , it is now greater than that of voltage references  15  and  18  the signal on line  22  is now low, the signal on line  20  becomes high, and the signal on line  11  goes low. Also when line  11  goes low the time delay of Time delay  33  and  30  are both reduced to near zero, and line  31  goes low. Switch  19  now connects Output terminal  9  to line  34  which is high. 
         [0021]    Amplifier system  50  is now placed in offset zero mode in which the signal a input  1  is not being amplified and the offset voltage of Amplifier system  50  is being stored. 
         [0022]    One implementation of Amplifier system  50 , Amplifier system  50 A is shown in  FIG. 2 . Amplifier  4  is a differential amplifier with it&#39;s negative input connected to voltage references  5  and one end of switch  3 . Amplifier  4  positive input is connected to the other end of switch  3  and one end of switch  2 . Amplifier  4  output is connected to one end of capacitor  6 . The other end on capacitor  6  is connected the input of comparator  8  and one end of switch  7 . The other end of switch  7  is connected to ground. Switches  3  and  7  are controlled by the signal level on line  11  along with the input of inverter  12 . Switch  2  is controlled by the output of inverter  12  which inverts the signal level on line  11 . 
         [0023]    When the signal level on line  11  is low Amplifier system  50 A is in offset zero mode. Switch  2  is open and switches  3  and  7  are closed. Amplifier  4  negative input and positive input are both connected to voltage references  5 . Capacitor  6  is now connected between ground and Amplifier  4  output. During this time a voltage level needed to cancel out from Amplifier  4  output signal the error caused by the offset voltage is stored in Capacitor  6 . 
         [0024]    When the signal level on line  11  is high Amplifier system  50 A is in amplify mode. Switch  2  is closed and switches  3  and  7  are open. Amplifier  4  negative input is connected to voltage references  5  and positive input is connected through switch  2  to input terminal  1 . Amplifier  4  output is applied to Comparator  8  input. Amplifier  4  output is the, (amplified combination of input terminal  1  signal plus offset voltage), minus the stored voltage on Capacitor  6 . Since the voltage on Capacitor  6  and amplified offset voltage level are nearly equal, the error caused by the offset voltage is nearly reduced to zero. 
         [0025]    Other well known methods of offset voltage reduction store the offset correction voltage digitally as opposed to with a capacitor or stores the offset correction voltage in the gate capacitance of the input stage MOSFET. These circuits have the advantage that they can withstand longer periods of time between being placed in offset zero mode. 
         [0026]    Although the above description has been directed to preferred embodiments of the invention, it will be understood and appreciated by those skilled in the art that other variations and modifications may be made without departing from the spirit and scope of the invention, and therefore the invention includes the full range of equivalents of the features and aspects set forth in the claims.