Abstract:
A liquid crystal driving device comprising: a scanning line driving circuit including, for each of scanning lines, a first series circuit having a 1st-PMOSFET/1st-NMOSFET connected in series, both ends thereof connected respectively to points of 1st-potential/2nd-potential, configured to receive at a 1st-PMOSFET&#39;s gate a binary signal having two levels not higher than 1st-potential&#39;s level and higher than 2nd-potential&#39;s level, a second series circuit having a 2nd-PMOSFET/2nd-NMOSFET connected in series, both ends thereof connected respectively to points of 3rd-potential (&gt;1st-potential)/2nd-potential, a 2nd-NMOSFET&#39;s gate connected to a connection point of the 1st-PMOSFET/1st-NMOSFET, and an output buffer circuit configured to buffer and output a voltage of a connection point of the 2nd-PMOSFET/2nd-NMOSFET, a 1st-NMOSFET&#39;s gate applied with a 1st-bias-voltage adapted such that the 2nd-NMOSFET is turned ON-or-OFF in response to the binary signal&#39;s level, a 2nd-PMOSFET&#39;s gate applied with a 2nd-bias-voltage adapted such that the 2nd-PMOSFET becomes higher in on-resistance than the 2nd-NMOSFET.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the benefit of priority to Japanese Patent Application No. 2008-064676, filed Mar. 13, 2008, of which full contents are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a liquid crystal driving device. 
         [0004]    2. Description of the Related Art 
         [0005]    As a liquid crystal driving device that drives a liquid crystal panel including a switching element such as TFT (Thin Film Transistor) corresponding to each of a plurality of pixels disposed in a matrix form, there is generally known a liquid crystal driving device including: a scanning line driving circuit that supplies row by row a signal for performing switching control of the switching element through a scanning line connected in parallel with the gates of a plurality of switching elements of the same row; and a data line driving circuit that supplies column by column a signal corresponding to the tone of each pixel through a data line connected in parallel with sources of a plurality of switching elements of the same column. As the scanning line driving circuit, there is generally known a scanning line driving circuit including for every scanning line a level shift circuit that amplifies a binary signal of a comparatively low voltage input from a microcomputer etc., which control the scanning line driving circuit, into a binary signal of a higher voltage for performing switching control of the switching element. 
         [0006]    In FIG. 11 of Japanese Patent Application Laid-Open Publication No. 2005-321457, as the level shift circuit used for the scanning line driving circuit, there is disclosed an example of a configuration where a High level amplifying unit that amplifies a binary signal having potentials of VD and VS (&lt;VD) firstly into a binary signal having potentials of VH (&gt;VD) and VS, and a Low level amplifying unit that amplifies it secondly into a binary signal having potentials of VH and VL (&lt;VS), are connected in series, for example. Furthermore, in FIG. 2 to FIG. 4 of Japanese Patent Application Laid-Open Publication No. 2005-321457, there is disclosed an example of a configuration where a first level shifter that amplifies a binary signal having potentials of VD and VS into a binary signal having potentials of VD and VL, and a second level shifter that amplifies it to a binary signal having potentials of VH and VS, are connected in parallel, for example. 
         [0007]    Thus, even when it is difficult to amplify from a binary signal of a comparatively low voltage directly to a binary signal of a higher voltage, a binary signal for performing switching control of the switching element through the scanning line can be supplied by employing the above series connection configuration or parallel connection configuration. 
         [0008]    However, the above series connection configuration or parallel connection configuration have a problem that a circuit size becomes larger, as compared with the case where a binary signal input to the level shift circuit can be amplified directly to a binary signal to be output. In particular, when the microcomputer, which controls the scanning line driving circuit etc., is driven by low voltage, there is increased the case where the difference becomes large in voltage level between a binary signal input to the scanning line driving circuit from the microcomputer and a binary signal output by the scanning line driving circuit through a scanning line, and therefore, a binary signal cannot be amplified directly. Furthermore, in the scanning line driving circuit including many scanning line outputs, the circuit size of the level shift circuit provided for every scanning line has an influence, the scale of which corresponds to the number of scanning lines, on the circuit size of the whole scanning line driving circuit. 
         [0009]    Therefore, even when it is difficult to amplify a binary signal of a comparatively low voltage directly to become a binary signal of a higher voltage, it is preferable to realize a level shift circuit with a comparatively small-scale configuration. 
       SUMMARY OF THE INVENTION 
       [0010]    A liquid crystal driving device according to an aspect of the present invention, comprises: a scanning line driving circuit employed in conjunction with a data line driving circuit, the scanning line driving circuit being configured to supply switching elements included in respective pixels corresponding respectively to intersections of a plurality of scanning lines and a plurality of data lines of a liquid crystal panel with signals for performing switching control of the switching elements through the plurality of scanning lines, the data line driving circuit being a circuit configured to supply the switching elements with signals corresponding to tones of the pixels through the plurality of data lines, the scanning line driving circuit including, for each of the plurality of scanning lines, a first series circuit having a first PMOSFET and a first NMOSFET connected in series, both ends thereof being connected respectively to a point of first potential and a point of second potential, the first series circuit being configured to receive at a gate of the first PMOSFET a binary signal having two levels not higher than a level of the first potential and higher than a level of the second potential, a second series circuit having a second PMOSFET and a second NMOSFET connected in series, both ends thereof being connected respectively to a point of third potential higher than the first potential and a point of the second potential, a gate of the second NMOSFET being connected to a connection point of the first PMOSFET and the first NMOSFET, and an output buffer circuit configured to buffer a voltage of a connection point of the second PMOSFET and the second NMOSFET, and output the buffered voltage, a gate of the first NMOSFET being applied with a first bias voltage adapted such that the second NMOSFET is turned ON or turned OFF in response to a level of the binary signal, and a gate of the second PMOSFET being applied with a second bias voltage adapted such that the second PMOSFET becomes higher in on-resistance than the second NMOSFET. 
         [0011]    Other features of the present invention will become apparent from descriptions of this specification and of the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    For more thorough understanding of the present invention and advantages thereof, the following description should be read in conjunction with the accompanying drawings, in which: 
           [0013]      FIG. 1  is a circuit block diagram showing a configuration of a level shift circuit and an output buffer circuit of a liquid crystal driving device according to a first embodiment of the present invention; 
           [0014]      FIG. 2A  is a diagram for explaining an operation of a level shift circuit and an output buffer circuit of a liquid crystal driving device according to a first embodiment of the present invention; 
           [0015]      FIG. 2B  is a diagram for explaining an operation of a level shift circuit and an output buffer circuit of a liquid crystal driving device according to a first embodiment of the present invention; 
           [0016]      FIG. 3  is a circuit block diagram showing a configuration of a level shift circuit and an output buffer circuit of a liquid crystal driving device according to a second embodiment of the present invention; 
           [0017]      FIG. 4A  is a diagram for explaining an operation of a level shift circuit and an output buffer circuit of a liquid crystal driving device according to a second embodiment of the present invention; 
           [0018]      FIG. 4B  is a diagram for explaining an operation of a level shift circuit and an output buffer circuit of a liquid crystal driving device according to a second embodiment of the present invention; 
           [0019]      FIG. 5  is a block diagram showing a schematic configuration of a whole liquid crystal driving device to which an embodiment of the present invention is applied; and 
           [0020]      FIG. 6  is a block diagram showing a schematic configuration of a gate driver  2 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0021]    At least the following details will become apparent from descriptions of this specification and of the accompanying drawings. 
       ===Schematic Configuration and Operation of Whole Liquid Crystal Driving Device=== 
       [0022]    There will hereinafter be explained a schematic configuration of a whole liquid crystal driving device to which an embodiment of the present invention is applied, with reference to  FIG. 5 . 
         [0023]    The liquid crystal driving device for driving a liquid crystal panel  1  includes a scanning line driving circuit  2 , a data line driving circuit  3 , a microcomputer  4 , and a power supply circuit  5 , for example. 
         [0024]    In the liquid crystal panel  1  to be driven, pixels are arranged in a form of matrix with an M rows and N columns, for example. Each pixel includes a capacitor (C-mn) for applying a voltage which controls transmittance of a liquid crystal element (not shown), and a switching element (T-mn) whose drain is connected to the capacitor (C-mn). Here, it is assumed that M and m are natural numbers having a relationship of 1≦m≦M while N and n are natural numbers having a relationship of 1≦n≦N, and they will hereinafter be used as such reference numerals as to be described above. 
         [0025]    The scanning line driving circuit  2  has outputs corresponding to M number of scanning lines (G- 1  to G-M), and each scanning line (G-m) is connected to the gate of N number of switching elements (T-m 1  to T-mN) of the same row. Hereinafter, the scanning line driving circuit  2  that supplies a signal to the gate of a switching element (T-mn) through a scanning line (G-m) is referred to as “a gate driver  2 ”. 
         [0026]    The data line driving circuit  3  has outputs corresponding to N number of data lines (S- 1  to S-N), and each data line (S-n) is connected to the sources of M number of switching elements (T- 1 n to T-Mn) of the same column. Hereinafter, the data line driving circuit  3  that supplies a signal to the source of a switching element (T-mn) through a data line (S-n) is referred to as “a source driver  3 ”. 
         [0027]    The microcomputer  4  controls the gate driver  2 , the source driver  3 , and the power supply circuit  5  according to a signal input from a central processing unit (not shown), etc. 
         [0028]    The power supply circuit  5  generates various kinds of voltages used in the gate driver  2  and the source driver  3 , and a counter electrode potential (VCOM) at the point connected to the capacitor (C-mn) of the liquid crystal panel  1  on the side to which the switching element (T-mn) is not connected, based on a reference voltage supplied from the outside. 
         [0029]    An operation of the whole liquid crystal driving device will then be described. 
         [0030]    Firstly, according to the control of the microcomputer  4 , the gate driver  2  selects one scanning line (G-m), supplies a signal for turning ON only to N number of switching elements (T-m 1  to T-mN) connected to the selected scanning line (G-m), and turns OFF all the switching elements connected to the scanning line which is not selected. Secondly, the source driver  3  supplies a signal corresponding to the tone of each pixel corresponding to N number of switching elements (T-m 1  to T-mN) which are turned ON by the gate driver  2 , according to the control of the microcomputer  4 . 
         [0031]    Thus, N number of switching elements (T-m 1  to T-mN) are turned ON by the gate driver  2 , and a voltage between the potential of the signal corresponding to the tone of each pixel which is supplied from the source driver  3  and the counter electrode potential (VCOM) generated in the power supply circuit  5  is applied to both ends of the capacitor (C-mn) connected to each switching element (T-mn). And then, according to the applied voltage, the transmittance of the liquid crystal element (not shown) changes and the pixels in a row are displayed. Further, the M number of scanning lines (G- 1  to G-M) are sequentially selected by the gate driver  2  and the above-mentioned display of the pixels in one row is repeated, and thus, the whole pixels with M rows and N columns of the liquid crystal panel  1  are displayed. 
       ===Schematic Configuration and Operation of Gate Driver=== 
       [0032]    Firstly, a schematic configuration of the gate driver  2  will be described with reference to  FIG. 6 . 
         [0033]    The gate driver  2  includes, for example, a gate driver control circuit  21 , level shift circuits (LS- 1  to LS-M), and output buffer circuits (BF- 1  to BF-M). 
         [0034]    The outputs of the gate driver control circuit  21  controlled by the microcomputer  4  is connected in parallel with the level shift circuits (LS- 1  to LS-M) corresponding to the M number of scanning lines (G- 1  to G-M). And then, the output of level shift circuit (LS-m) is connected in series to an output buffer circuit (BF-m), and the output of the output buffer circuit (BF-m) is connected to the scanning line (G-m) as an output of the gate driver  2 . 
         [0035]    Secondly, an operation of the gate driver  2  will be explained. 
         [0036]    The gate driver control circuit  21  sequentially selects as to the M number of scanning lines (G- 1  to G-M) with a sequential selection circuit such as a shift register, for example, about the M scanning lines (G- 1  to G-M), outputs the binary signal of a level indicating a selected state to the level shift circuit (LS-m) corresponding to the selected scanning line (G-m), and outputs the binary signal of a level indicating not-selected state to all the level shift circuits corresponding to the not-selected scanning lines. The binary signal output from the gate driver control circuit  21  is input in parallel to the level shift circuits (LS- 1  to LS-M), and is amplified to become the binary signal of a higher voltage for turning ON or OFF the switching element (T-mn), in each level shift circuit (LS-m). The binary signal of a higher voltage output from the level shift circuit (LS-m) is buffered in the output buffer circuit (BF-m), to be input to the gate of the switching element (T-mn) through the scanning line (G-m). 
         [0037]    Thus, the gate driver  2  supplies the binary signal for turning ON to the gates of N number of switching elements (T-m 1  to T-mN) connected to the scanning line (G-m) to be sequentially selected, and supplies the binary signal for turning OFF to the gates of the switching elements connected to the not-selected scanning line. 
       ===Configuration and Operation of Level Shift Circuit and Output Buffer Circuit === 
     First Embodiment 
       [0038]    Firstly, a configuration of a level shift circuit and an output buffer circuit according a first embodiment of a liquid crystal driving device of the present invention will be described with reference to  FIG. 1 . Although  FIG. 1  shows a configuration of only the level shift circuit (LS-m) and the output buffer circuit (BF-m) corresponding to one scanning line (G-m), it is assumed that configurations are the same with respect to M number of scanning lines (G- 1  to G-M). 
         [0039]    In an embodiment of the present invention, the level shift circuit (LS-m) includes PMOSFETs (P-channel Metal-Oxide Semiconductor Field-effect Transistor) (P 1 , P 2 ) and NMOSFETs (N-channel MOSFET) (N 1 , N 2 ). In an embodiment of the present invention, the output buffer circuit (BF-m) is a CMOS (Complementary MOS) inverter circuit including a PMOSFET (P 3 ) and an NMOSFET (N 3 ). In an embodiment of the present invention, for example, it is assumed that when the potentials of the binary signal input to the gate of the PMOSFET (P 1 ) are defined as VD and VS, the potential at the point connected to the source of the PMOSFET (P 1 ) is defined as VH 1 , the potential at the point connected to the sources of PMOSFETs (P 2 , P 3 ) is defined as VH 3 , and the potential at the point connected to the sources of the NMOSFETs (N 1 , N 2 , N 3 ) is defined as VL 2 , the relationship thereamong is expressed by VL 2 &lt;VS&lt;VD≦VH 1 &lt;VH 3 . 
         [0040]    The PMOSFET (P 1 ) and the NMOSFET (N 1 ) are connected in series, and both ends are connected to the points of the potentials VH 1  and VL 2 , respectively. The binary signal having potentials of VD and VS is input to the gate of the PMOSFET (P 1 ), and the gate of the NMOSFET (N 1 ) is connected to the point of a potential VB 1  so that the bias voltage (BIAS 1 ) of VB 1 -VL 2  is applied to the gate of the NMOSFET (N 1 ). 
         [0041]    The PMOSFET (P 2 ) and the NMOSFET (N 2 ) are connected in series, and both ends are connected to the points of the potentials VH 3  and VL 2 , respectively. The gate of the PMOSFET (P 2 ) is connected to the point of a potential VB 2  so that the bias voltage (BIAS 2 ) of VB 2 -VH 3  is applied to the gate of the PMOSFET (P 2 ), and the gate of the NMOSFET (N 2 ) is connected to a connection point of the PMOSFET (P 1 ) and the NMOSFET (N 1 ). The connection point of the PMOSFET (P 2 ) and the NMOSFET (N 2 ) is connected to the output buffer circuit (BF-m) as an output of the level shift circuit (LS-m). 
         [0042]    The output buffer circuit (BF-m), which is a CMOS inverter circuit, uses a voltage between potentials VH 3  and VL 2  as a power supply voltage, and the output of the level shift circuit (LS-m) is connected to the gates of the PMOSFET (P 3 ) and the NMOSFET (N 3 ). The connection point of the PMOSFET (P 3 ) and the NMOSFET (N 3 ) is connected to the scanning line (G-m) as an output of the output buffer circuit (BF-m). 
         [0043]    The bias voltage (BIAS 1 ) applied to the gate of the NMOSFET (N 1 ) is such a voltage that the NMOSFET (N 2 ) is turned OFF when the potential of the binary signal input to the gate of the PMOSFET (P 1 ) is VD which is of a high level, and NMOSFET (N 2 ) is turned ON when the potential of the binary signal input to the gate of the PMOSFET (P 1 ) is VS which is of a low level. 
         [0044]    The bias voltage (BIAS 2 ) applied to the gate of the PMOSFET (P 2 ) is such a voltage that the on-resistance of the PMOSFET (P 2 ) is higher than the on-resistance of the NMOSFET (N 2 ). 
         [0045]    Secondly, an operation of the level shift circuit and the output buffer circuit according to an embodiment of the present invention will be explained with reference to  FIG. 2A  and  FIG. 2B . 
         [0046]    The case will be described where the potential of the binary signal input to the gate of PMOSFET (P 1 ) is VD, which is of a high level, as shown in  FIG. 2A . 
         [0047]    The NMOSFET (N 1 ) is turned ON by the bias voltage (BIAS 1 ), and the PMOSFET (P 1 ) is turned OFF or ON by the voltage between gate and source of VD-VH 1 . When the PMOSFET (P 1 ) is turned OFF, the gate potential of the NMOSFET (N 2 ) connected to the connection point of the PMOSFET (P 1 ) and the NMOSFET (N 1 ) becomes equal to a source potential VL 2 , and therefore, the NMOSFET (N 2 ) is turned OFF. Even when the PMOSFET (P 1 ) is turned ON, the bias voltage (BIAS 1 ) is set such that the on-resistance of the PMOSFET (P 1 ) becomes sufficiently higher than the on-resistance of the NMOSFET (N 1 ), and the gate potential becomes close to the source potential VL 2  to such an extent that the NMOSFET (N 2 ) is turned OFF. 
         [0048]    The PMOSFET (P 2 ) is turned ON by the bias voltage (BIAS 2 ). As mentioned above, since the NMOSFET (N 2 ) is turned OFF, the output potential of the level shift circuit (LS-m) becomes equal to a source potential VH 3  of the PMOSFET (P 2 ). 
         [0049]    Since the input potential VH 3  from the level shift circuit (LS-m) to the output buffer circuit (BF-m) is equal to a power supply potential VH 3  on the side of the PMOSFET (P 3 ) of the CMOS inverter circuit, the output potential of the output buffer circuit (BF-m) becomes equal to a power supply potential VL 2  on the side of the NMOSFET (N 3 ). 
         [0050]    The case will be described where the potential of the binary signal input to the gate of the PMOSFET (P 1 ) is VS, which is of a low level, as shown in  FIG. 2B . 
         [0051]    The NMOSFET (N 1 ) is turned ON by bias voltage (BIAS 1 ), and the PMOSFET (P 1 ) is turned ON by the voltage between gate and source of VS-VH 1 . Although the on-resistance of the PMOSFET (P 1 ) may be lower or higher than the on-resistance of the NMOSFET (N 1 ), the bias voltage (BIAS 1 ) is set to such a voltage between gate and source as to obtain at least the result that the NMOSFET (N 2 ) is turned ON. 
         [0052]    The PMOSFET (P 2 ) is turned ON by the bias voltage (BIAS 2 ) Since the bias voltage (BIAS 2 ) is set such that the on-resistance of the PMOSFET (P 2 ) becomes higher than the on-resistance of the NMOSFET (N 2 ), there is obtained at least the result that the output potential of the level shift circuit (LS-m) becomes closer to the source potential VL 2  of the NMOSFET (N 2 ) than to the source potential VH 3  of the PMOSFET (P 2 ). 
         [0053]    Since the input potential from the level shift circuit (LS-m) to the output buffer circuit (BF-m) is closer to the power supply potential VL 2  on the side of the NMOSFET (N 3 ) than the power supply potential VH 3  on the side of the PMOSFET (P 3 ) of the CMOS inverter circuit, the output potential of the output buffer circuit (BF-m) becomes close to the power supply potential VH 3  on the side of the PMOSFET (P 3 ). 
         [0054]    In the output buffer circuit (BF-m), by connecting in series a plurality of stages of CMOS inverter circuits using the voltage between potentials VH 3  and VL 2  as the power supply voltage, it is possible to make the output potential equal to the power supply potential VH 3  or VL 2 . However, more preferably, the bias voltage (BIAS 2 ) is set such that the on-resistance of the PMOSFET (P 2 ) becomes sufficiently higher than the on-resistance of the NMOSFET (N 2 ), and the gate potential becomes close to the source potential VL 2  to such an extent that the NMOSFET (N 3 ) of the CMOS inverter circuit is turned OFF. In this case, the output potential of the output buffer circuit (BF-m) can be made equal to the power supply potential VH 3  on the side of the PMOSFET (P 3 ) by one stage of CMOS inverter circuit, as shown in  FIG. 2B . 
         [0055]    Thus, the level shift circuit (LS-m) and the output buffer circuit (BF-m) amplify the binary signal having potentials of VD and VS which is input from the gate driver control circuit  21  to become the binary signal of a higher voltage having the potentials of VL 2  and VH 3  for turning ON or OFF the switching element (T-mn), and output the amplified binary signal. 
       Second Embodiment 
       [0056]    Firstly, a configuration of a level shift circuit and an output buffer circuit according to a second embodiment of the liquid crystal driving device of the present invention will be described with reference to  FIG. 3 . Although  FIG. 3  shows a configuration of only the level shift circuit (LS-m) and the output buffer circuit (BF-m) corresponding to one scanning line (G-m), it is assumed that configurations are the same with respect to M number of scanning lines (G- 1  to G-M). 
         [0057]    The level shift circuit (LS-m) includes PMOSFETs (P 1 , P 2 ) and NMOSFETs (N 1 , N 2 ), and the output buffer circuit (BF-m) is a CMOS inverter circuit including a PMOSFET (P 3 ) and an NMOSFET (N 3 ), as is the case with a first embodiment of the present invention. In an embodiment of the present invention, for example, it is assumed that when the potentials of the binary signal input to the gate of the NMOSFET (N 1 ) are defined as VD and VS, the potential at the point connected to the source of the NMOSFET (N 1 ) is defined as VL 1 , the potential at the point connected to the sources of the NMOSFETs (N 2 , N 3 ) is defined as VL 3 , and the potential connected to the sources of the PMOSFETs (P 1 , P 2 , P 3 ) is defined as VH 2 , the relationship thereamong is expressed by VL 3 &lt;VL 1 ≦VS&lt;VD&lt;VH 2 . 
         [0058]    The NMOSFET (N 1 ) and the PMOSFET (P 1 ) are connected in series, and both ends are connected to the points of the potentials VL 1  and VH 2 , respectively. The binary signal having potentials of VD and VS is input to the gate of the NMOSFET (N 1 ), and the gate of the PMOSFET (P 1 ) is connected to the point of a potential VB 1  so that the bias voltage (BIAS 1 ) of VB 1 -VH 2  is applied to the gate of the PMOSFET (P 1 ). 
         [0059]    The NMOSFET (N 2 ) and the PMOSFET (P 2 ) are connected in series, and both ends are connected to the points of the potential VL 3  and VH 2 , respectively. The gate of the NMOSFET (N 2 ) is connected to the point of a potential VB 2  so that the bias voltage (BIAS 2 ) of VB 2 -VL 3  is applied to the gate of the NMOSFET (N 2 ), and the gate of the PMOSFET (P 2 ) is connected to a connection point of the NMOSFET (N 1 ) and the PMOSFET (P 1 ). The connection point of the NMOSFET (N 2 ) and the PMOSFET (P 2 ) is connected to the output buffer circuit (BF-m) as an output of the level shift circuit (LS-m). 
         [0060]    The output buffer circuit (BF-m), which is a CMOS inverter circuit, uses a voltage between potentials VH 2  and VL 3  as a power supply voltage, and the output of the level shift circuit (LS-m) is connected to the gates of the PMOSFET (P 3 ) and the NMOSFET (N 3 ). The connection point of the PMOSFET (P 3 ) and the NMOSFET (N 3 ) is connected to the scanning line (G-m) as an output of the output buffer circuit (BF-m). 
         [0061]    The bias voltage (BIAS 1 ) applied to the gate of the PMOSFET (P 1 ) is such a voltage that the PMOSFET (P 2 ) is turned OFF when the potential of the binary signal input to the gate of the NMOSFET (N 1 ) is VS, which is of a low level, and the PMOSFET (P 2 ) is turned ON when the potential of the binary signal input to the gate of the NMOSFET (N 1 ) is VD, which is of a high level. 
         [0062]    The bias voltage (BIAS 2 ) applied to the gate of the NMOSFET (N 2 ) is such a voltage that the on-resistance of the NMOSFET (N 2 ) is higher than the on-resistance of the PMOSFET (P 2 ). 
         [0063]    Secondly, an operation of the level shift circuit and the output buffer circuit according to an embodiment of the present invention will be described with reference to  FIG. 4A  and  FIG. 4B . 
         [0064]    The case will be described where the potential of the binary signal input to the gate of the NMOSFET (N 1 ) is VS, which is of a low level, as shown in  FIG. 4A . 
         [0065]    The PMOSFET (P 1 ) is turned ON by the bias voltage (BIAS 1 ), and the NMOSFET (N 1 ) is turned OFF or ON by the voltage between gate and source of VS-VL 1 . When the NMOSFET (N 1 ) is turned OFF, the gate potential of the PMOSFET (P 2 ) at the connection point of the NMOSFET (N 1 ) and the PMOSFET (P 1 ) becomes equal to a source potential VH 2 , and therefore, the PMOSFET (P 2 ) is turned OFF. Even when the NMOSFET (N 1 ) is turned ON, the bias voltage (BIAS 1 ) is set such that the on-resistance of the NMOSFET (N 1 ) becomes sufficiently higher than the on-resistance of the PMOSFET (P 1 ), and the gate potential becomes close to the source potential VH 2  to such an extent that the PMOSFET (P 2 ) is turned OFF. 
         [0066]    The NMOSFET (N 2 ) is turned ON by the bias voltage (BIAS 2 ). As mentioned above, since the PMOSFET (P 2 ) is turned OFF, the output potential of the level shift circuit (LS-m) becomes equal to a source potential VL 3  of the NMOSFET (N 2 ). 
         [0067]    Since the input potential VL 3  from the level shift circuit (LS-m) to the output buffer circuit (BF-m) is equal to a power supply potential VL 3  on the side of the NMOSFET (N 3 ) of the CMOS inverter circuit, the output potential of the output buffer circuit (BF-m) becomes equal to a power supply potential VH 2  on the side of the PMOSFET (P 3 ). 
         [0068]    The case will be described where the potential of the binary signal input to the gate of the NMOSFET (N 1 ) is VD, which is of a high level, as shown in  FIG. 4B . 
         [0069]    The PMOSFET (P 1 ) is turned ON by bias voltage (BIAS 1 ), and the NMOSFET (N 1 ) is turned ON by the voltage between gate and source of VD-VL 1 . Although the on-resistance of the NMOSFET (N 1 ) may be lower or may be higher than the on-resistance of the PMOSFET (P 1 ), the bias voltage (BIAS 1 ) is set to such a voltage between gate and source as to obtain at least the result that the PMOSFET (P 2 ) is turned ON. 
         [0070]    The NMOSFET (N 2 ) is turned ON by the bias voltage (BIAS 2 ). Since the bias voltage (BIAS 2 ) is set such that the on-resistance of the NMOSFET (N 2 ) becomes higher than the on-resistance of the PMOSFET (P 2 ), there is obtained at least the result that the output potential of the level shift circuit (LS-m) becomes closer to the source potential VH 2  of the PMOSFET (P 2 ) than to the source potential VL 3  of NMOSFET (N 2 ). 
         [0071]    Since the input potential from the level shift circuit (LS-m) to the output buffer circuit (BF-m) is closer to the power supply potential VH 2  on the side of the PMOSFET (P 3 ) than the power supply potential VL 3  on the side of the NMOSFET (N 3 ) of the CMOS inverter circuit, the output potential of the output buffer circuit (BF-m) becomes close to the power supply potential VL 3  on the side of the NMOSFET (N 3 ). 
         [0072]    In the output buffer circuit (BF-m), by connecting in series a plurality of stages of CMOS inverter circuits using the voltage between potentials VH 2  and VL 3  as the power supply voltage, it is possible to make the output potential equal to the power supply potential VH 2  or VL 3 . However, more preferably, the bias voltage (BIAS 2 ) is set such that the on-resistance of the NMOSFET (N 2 ) becomes sufficiently higher than the on-resistance of the PMOSFET (P 2 ), and the gate potential becomes close to the source potential VH 2  to such an extent that the PMOSFET (P 3 ) of the CMOS inverter circuit is turned OFF. In this case, the output potential of the output buffer circuit (BF-m) can be made equal to the power supply potential VL 3  on the side of the NMOSFET (N 3 ) by one stage of CMOS inverter circuit, as shown in  FIG. 4B . 
         [0073]    Thus, the level shift circuit (LS-m) and the output buffer circuit (BF-m) amplify the binary signal having potentials of VD and VS which is input from the gate driver control circuit  21  to become the binary signal of the higher voltage having the potentials of VL 3  and VH 2  for turning ON or OFF the switching element (T-mn), and output the amplified binary signal. 
         [0074]    As mentioned above, in the level shift circuit (LS-m) included for every scanning line (G-m) in the gate driver  2  of the liquid crystal driving device shown in  FIG. 1 : the both ends of the series connection of the PMOSFET (P 1 ) having the gate to which the binary signal having potentials of VD and VS is input, and the NMOSFET (N 1 ) having the gate to which the bias voltage (BIAS 1 ) is applied, are connected to the points of the potentials VH 1  and VL 2 , respectively; the both ends of the series connection of the PMOSFET (P 2 ) having the gate to which the bias voltage (BIAS 2 ) is applied, and the NMOSFET (N 2 ) having the gate connected to the connection point of the PMOSFET (P 1 ) and NMOSFET (N 1 ), are connected to the potentials VH 3  and VL 2 , respectively; the bias voltage (BIAS 1 ) is rendered such a voltage that the NMOSFET (N 2 ) is turned OFF when the potential of the binary signal is VD and the NMOSFET (N 2 ) is turned ON when the potential of the binary signal is VS; and the bias voltage (BIAS 2 ) is rendered such a voltage that the on-resistance of the PMOSFET (P 2 ) is higher than the on-resistance of NMOSFET (N 2 ); and thereby, there can be realized the level shift circuit (LS-m) having a comparatively small-scale configuration, so that there can be reduced the circuit size of the liquid crystal driving device including the gate driver  2 . 
         [0075]    As shown in  FIG. 3 , the level shift circuit (LS-m) has such a configuration that the polarity therein is reversed with respect to the polarity in the circuit in  FIG. 1 , and thereby, there can also be reduced the circuit size of the liquid crystal driving device including the gate driver  2 . 
         [0076]    As shown in  FIG. 1  and  FIG. 3 , the output buffer circuit (BF-m) to which the output of the level shift circuit (LS-m) is input is rendered the CMOS inverter circuit using a voltage between source potentials of the PMOSFET (P 1 ) and the NMOSFET (N 1 ) in the level shift circuit (LS-m) as a power supply voltage, and thereby, there can be realized the output buffer circuit (BF-m) having a comparatively small-scale configuration, so that there can be further reduced the circuit size of the liquid crystal driving device including the gate driver  2 . 
         [0077]    In embodiments of the present invention as mentioned above, although the liquid crystal driving device for driving the liquid crystal panel  1  includes the gate driver  2 , the source driver  3 , the microcomputer  4 , and the power supply circuit  5 , it is not limitative. Although the liquid crystal driving device according to an embodiment of the present invention includes the gate driver  2  as an essential constituent, it is arbitrary whether the source driver  3 , the microcomputer  4 , and the power supply circuit  5  are included in the liquid crystal driving device as constituents or excluded therefrom as external devices. 
         [0078]    In embodiments of the present invention as mentioned above, although the gate driver  2  includes the gate driver control circuit  21 , the level shift circuit (LS-m), and the output buffer circuit (BF-m), it is not limitative. Although the gate driver of the liquid crystal driving device according to an embodiment of the present invention includes the level shift circuit (LS-m) and the output buffer circuit (BF-m) as essential constituents, it is arbitrary whether the gate driver control circuit  21  is included in the gate driver  2  or included in the microcomputer  4 . 
         [0079]    The above embodiments of the present invention are simply for facilitating the understanding of the present invention and are not in any way to be construed as limiting the present invention. The present invention may variously be changed or altered without departing from its spirit and encompass equivalents thereof.