Abstract:
A high side circuit includes at least one power device having a first non-drivable terminal connected to a supply voltage, at least one load connected between a second non-drivable terminal of the power device and ground, and driving circuitry. The driving circuitry includes transistors which are connected to each other and to a higher voltage than the supply voltage in order to control the turning on and the turning off of the power device and to reduce or minimize the potential difference between the second non-drivable terminal and a drivable terminal of the power device during the turning off state to avoid the re-turning on of the same power device.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a high efficiency “high side” circuit. 
     2. Discussion of the Related Art 
     Different circuit configurations are known wherein a DMOS transistor can work as a switch. One configuration among these configurations is that wherein the drain terminal of the DMOS is connected to high voltages, as the supply voltage, while the source terminal is connected to a load which has the other terminal connected to ground; such circuit configuration is called “high side”. This circuit is utilized in numerous appliances as in engine control circuits or regulators, in order to drive different loads, but, particularly, inductive loads. 
     A typical high side circuit configuration, shown in FIG. 1, includes a DMOS transistor  1  which has the drain D connected to a supply voltage Vcc and the source S connected both to the cathode of a diode D 1 , and to a terminal of an inductive load  2  including an inductance L and a resistance R. Both the anode of the diode D 1  and the other terminal of the inductive load  2  are connected to ground. The gate terminal G of the DMOS transistor  1  is connected both to a terminal of a current generator  1  and to a terminal of a switch S 0 , which can be formed by a MOS or DMOS transistor and has the other terminal connected to ground. The second terminal of the current generator  1  is connected to a voltage Vboot (produced generally by a charge pump) which is higher than the supply voltage Vcc in order to drive the DMOS  1  in a resistive way. 
     With the switch S 0  open the gate terminal G of the DMOS  1  is connected to the voltage Vboot in order to turn on the transistor  1  allowing the current flow into the load  2 . Closing the switch S 0  the gate terminal of the DMOS  1  is connected to ground in order to turn off the transistor  1 . In this way the inductance L is demagnetized through the diode D 1  and the capacitance at the gate G of the DMOS is discharged to ground. 
     The aforementioned high side circuit has numerous problems. 
     First, the switch S 0  must be dimensioned so as to withstand the voltage Vboot, which is a voltage much higher than the supply voltage Vcc. 
     With the decrease in the lithography of the technologies to produce DMOS transistors and also with the reduction of the gate oxide thickness, the threshold voltage of the DMOS transistors is notably reduced so that it is actually equal or lower than 1 V. The source terminal S of the DMOS  1  by the current re-circle, with the transistor turned off, can be carried to a negative voltage which can cause the non-desired turning on of the transistor  1  and a non-controlled current peak which can damage the transistor  1  and cause an efficiency loss. 
     Also, in the aforementioned circuit, it is provided that the charge stored in the gate G is discharged to ground rather that into the load thereby causing a further efficiency loss of the circuit. 
     In view of the state of the art described, it is an object of the present invention to provide a “high side” circuit which has a higher efficiency than the known circuits and solves at least the aforementioned problems. 
     SUMMARY OF THE INVENTION 
     According to the present invention, this and other objects are attained by a high side circuit comprising at least one power device having a first non-drivable terminal connected to a supply voltage, at least one load connected between a second non-drivable terminal of the power device and ground, driving circuitry comprising transistors which are connected to each other and to a higher voltage than said supply voltage in order to control the turning on and the turning off of the power device and to reduce or minimize the potential difference between the second non-drivable terminal and a drivable terminal of the power device during the turning off state to avoid the re-turning on of the same power device. 
     As a result of the present invention it is possible to form a “high side” circuit which, as a result of a different driving circuitry of the DMOS transistor, assures high efficiency of the high side circuit in any operating state. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features and the advantages of the present invention will be made evident by the following detailed description of an embodiment thereof, illustrated as not limiting example in the annexed drawings, wherein: 
     FIG. 1 is a schematic view of a high side circuit according to the prior art; 
     FIG. 2 shows a high side circuit according to present invention; 
     FIG. 3 is a cross-sectional schematic view of a part of an integrated device wherein there are a DMOS transistor and an NMOS transistor with an epitaxial layer connected to a voltage VB; and 
     FIG. 4 shows a circuit utilizable for generating the biasing voltage VB. 
    
    
     DETAILED DESCRIPTION 
     In FIG. 1, a high side circuit according to the prior art is shown wherein a DMOS transistor  1  is driven by a switch S 0 , which is formed for example by a DMOS or MOS transistor, and it allows the current flow into the inductive load  2  schematized by an inductance L and a resistance R in series. The inductance  1  is demagnetized through the diode D 1  when the transistor  1  turns off. 
     A high side circuit configuration according to present invention is shown in FIG.  2 . In this case the driving of the DMOS transistor  1  is effected by a driving circuitry  10  comprising the NMOS transistors M 1 , M 2 , M 3  which have respective source terminals connected to the source terminal S of the DMOS  1  and respective substrate terminals connected to the source terminals. The drain terminals of the transistors M 1 , M 2 , M 3  are respectively connected to the switches S 1 , S 2 , S 3 , the switches S 1  and S 3  of which are driven by a signal IN while the switch S 2  is driven by an inverted signal IN. The other terminals of the switches S 1 , S 2 , S 3  can be connected to respective current generators Ia, Ib(=Ia), Ic connected in turn to the voltage Vboot. The gate terminals of the transistors M 1  and M 3  are connected to the drain terminal B of the transistor M 2  while the gate terminal of the transistor M 2  is connected to the drain terminal A of the transistor M 1 . The drain terminal of the transistor M 3  is also connected to the gate terminal G of the transistor DMOS  1  which has the drain terminal D connected to the supply voltage Vcc and the source terminal S connected to the inductive load  2  and to the cathode of the diode D 1  which are connected to ground. The output voltage Vout is the voltage at the source terminal S of the DMOS  1 . 
     When the signal IN causes closure of the switches S 1  and S 3  and consequent opening of the switch S 2 , with the drain terminal B of the transistor M 2  carried to a voltage Vout+Vdssat 2  where the voltage Vdssat 2  is the saturation voltage of the transistor M 2 , the transistors M 1  and M 3  are turned off while the transistor M 2  is turned on because it has the gate terminal at the voltage Vboot. The gate terminal G of the transistor DMOS  1  is connected to the voltage Vboot and therefore it is turned on by making a current Iout to flow so that the output voltage Vout is Vout=Vcc−Rond*Iout wherein Rond is the turning on resistance of the DMOS  1 . 
     When the signal IN causes the switch S 2  to close and consequently the switches S 1  and S 3  to open, with the resistance Ron 2  of the transistor M 2  suitably dimensioned so that the product Ron 2 *Ia is higher than the threshold voltage Vth 1  of the transistor M 1 , the transistor M 1  is turned on. This causes the turning off of the transistor M 2  so that the voltage at the terminal B is Vboot and the voltage at the terminal A is Vout+Vdssat 1  where Vdssat 1  is the saturation voltage of the transistor M 1 . Consequently the transistor M 3  is turned on and allows the capacity of the gate G of the DMOS  1  to discharge into the inductive load  2 . The voltage Vout successively will go to ground because there is the current re-cycle in the circuit formed by the diode D 1  and the load  2 . If the load  2  is inductive there is an under-ground re-cycle and the output voltage is Vout=−Vd where Vd is the voltage between the terminals of the diode D 1 . In this case the transistor DMOS cannot be re-turned on because the transistor M 3  is turned on. 
     When the signal IN causes the switches S 1  and S 3  to close and consequently the switch S 2  to open, with the resistance Ron 1  of the transistor M 1  in turning on state which is dimensioned so that the product Ron 1 *Ia is higher than the threshold voltage Vth 2  of the transistor M 2 , the turning on cycle of the transistor DMOS  1  will be repeated. 
     Traditionally the aforementioned NMOS and DMOS transistors are implemented by present lithography technologies on respective dopant low concentration N-type respective layers  3  and  130 , as shown in FIG.  3 . In FIG. 3, a section of a device is shown schematically which is integrated with the transistor DMOS  1 , which is, for example, a vertical DMOS transistor having the source region  20  and the bulk region  21  in contact with each other through only one source terminal S and the drain regions  22  in contact with the drain terminals D and the gate  23  in contact with the gate terminals G, and only one NMOS transistor having the source region  30  and the bulk region  31  in contact with each other through only one source terminal S 11 , the drain region  32  in contact with the drain terminal D 11  and the gate  33  in contact with the gate terminal G 11 . Preferably the epitaxial layer  3  is biased to a voltage VB which is always higher than zero but it follows always the output voltage Vout, which is the output voltage of the DMOS transistor  1  and it is even the voltage at the sources of the transistor M 1 , M 2 , M 3 . The epitaxial layer  3  must withstand the whole voltage Vboot with respect to the substrate. 
     A simple circuit which generates the voltage VB is shown in FIG. 4; a block  4 , constituted by a zener diode Dz disposed in parallel with a capacitor C, is displaced between the terminals of the output voltage Vout and the voltage VB. The terminal of the voltage VB is in turn connected to a current generator IB connected to the voltage Vboot. The capacitor C must maintain the well potential VB in the case of fast transitions. 
     It is possible to use clamp diodes disposed among the node A, B, and the terminal G and the voltage Vout in the case of fast commutation transitions of the NMOS transistors M 1 , M 2 , M 3  to avoid damaging them. 
     Also, the currents Ia, Ib, Ic can be generated to be independent from the temperature variations for reducing the variations of the commutation times with respect to the process parameters. 
     The currents Ia, Ib, Ic can be even timed to have a high value during the commutation transitions of the transistors and a low value in the static states. 
     With the high side circuit configuration according to the present invention, the high side circuit efficiency is improved or optimized. In fact the new driving circuitry of the DMOS transistor  1  allows both the circuit to operate in under-ground state for avoiding the re-turn on of the DMOS  1  to avoid dangerous current peaks, and the gate capacitance of the DMOS transistor to be discharged into the load to increase the high side efficiency. 
     Also, if the biasing voltage VB is utilized for the epitaxial well which contains the NMOS transistors M 1 , M 2 , M 3 , such transistors can be NMOS transistors for low voltages and therefore they must have smaller dimensions. If the voltage VB is higher than zero during the current recycle when the DMOS transistor is turned off and the diode D 1  is integrated, the power transistor is immune to the parasitic components of the driving circuitry. 
     The aforementioned circuit allows a different driving method of the DMOS power transistor  1 . 
     A method for driving the DMOS power transistor  1  in a high side circuit configuration. The power transistor  1  has the drain terminal connected to the supply voltage Vcc and a load  2  connected between the source terminal S of the DMOS power transistor  1  and ground. The method includes driving the power transistor  1  by a turning on step and a turning off step of the power transistor  1 . The driving provides that during the turning off state of the power transistor  1  the re-turning on thereof is avoided by reducing or minimization of the potential difference between the source terminal S and the gate terminal G of the power transistor  1  by the driving circuitry  10  described above and formed by the NMOS transistors M 1 , M 2 , M 3 . Also such driving circuitry  10  allows that during this turning off step the discharge of the capacitance associated with gate terminal G towards the load  2  is controlled. The driving circuitry  10  operates according to the previously described operation. 
     Having thus described at least one illustrative embodiment of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The invention is limited only as defined in the following claims and the equivalents thereto.