Abstract:
Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. Agate width of the second transistor is narrower than a gate width of the first transistor.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The disclosure of Japanese Patent Application No. 2014-198264 filed on Sep. 29, 2014 including the specification, drawings and abstract is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    The present disclosure relates to a semicondcutor device, and, in particular, relates to the semiconductor device which includes an ESD (Electro Static Discharge) protection element. 
         [0003]    In recent years, there has been demanded a multi-pin semiconductor device which includes I/C pins (input/output pins) of the number exceeding thousands with advancement of function and performance of the semiconductor device. Accordingly, an area of each I/O block has come to greatly influence reductions in size and cost of the entire semiconductor device. As examples of an element which is large in ratio that the area of each I/O block occupies, an electrostatic discharge protection element (ESD protection element) and a driver element of high driving power are given. 
         [0004]    In addition, since device resistance is reduced as the process generation advances and a reduction in area is promoted, it becomes important to improve the performance of the electrostatic discharge protection element (the ESD protection element) and various systems are proposed in order to improve the performance (see, for example, Japanese Unexamined Patent Publication No. 2006-121007. 
       SUMMARY OF THE INVENTION 
       [0005]    However, although the technology described in Japanese Unexamined Patent Publication No. 2006-121007 discloses the ESD protection element configured by an RC time constant and an inverter, it is necessary to set values of a resistive element R and a capacitive element C comparatively high in order to drive the inverter while an ESD current is being released. Consequently, value setting of the resistance element R and the capacitive element C is left as a subject matter to be solved in order to promote area reduction. 
         [0006]    The present disclosure has been made in view of the above-mentioned circumstance and aims to provide a semiconductor device making it possible to promote area reduction while maintaining the ESD resistance. 
         [0007]    Other subject matters and novel features of the present disclosure will be apparent from the description of the present specification and the appended drawings. 
         [0008]    According to one embodiment of the present disclosure, there is provided a semiconductor device which includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor coupled between the power wire and the ground wire, a first resistive element coupled between the power wire and the ground wire in series with the first transistor, a second transistor coupled between the power wire and the ground wire in parallel with the first transistor so as to form a current mirror circuit together with the first transistor with a gate of which a first coupling node between the first transistor and the first resistive element is coupled, a first capacitive element coupled between the power wire and the ground wire in series with the second transistor, a first inverter with which a second coupling node between the second transistor and the first capacitive element is coupled as an input node, and a protection transistor which is coupled between the power wire and the ground wire and a gate of which receives an output from the first inverter. A gate width of the second transistor is narrower than a gate width of the first transistor. 
         [0009]    According to embodiments of the present disclosure, it is possible to promote area reduction while maintaining the ESD resistance. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]      FIG. 1  is an explanatory diagram illustrating one example of the entire of a semiconductor device  1  according to a First Embodiment. 
           [0011]      FIG. 2  is an explanatory diagram illustrating one example of a circuit configuration of an I/O cell  500  according to the First Embodiment. 
           [0012]      FIG. 3  is an explanatory diagram illustrating one example of a circuit configuration of a power supply cell  600  according to the First Embodiment. 
           [0013]      FIG. 4  is an explanatory diagram illustrating one example of transition of each node and a power wire VM when the ESD current has been flown into each node and the power wire. 
           [0014]      FIG. 5A  is an explanatory diagram illustrating one example of a protection circuit of a comparative example. 
           [0015]      FIG. 5B  is an explanatory diagram illustrating one example of the protection circuit of the comparative example. 
           [0016]      FIG. 5C  is an explanatory diagram illustrating one example of the protection circuit of the comparative example. 
           [0017]      FIG. 6  is a diagram illustrating one example of comparison in layout between the protection circuit of the comparative example and the power supply cell  600  according to the First Embodiment. 
           [0018]      FIG. 7  is an explanatory diagram illustrating one example of a layout configuration of a current mirror circuit of the power supply cell  600  according to the First Embodiment. 
           [0019]      FIG. 8  is an explanatory diagram illustrating one example of a layout configuration of a resistive element of the power supply cell  600  according to the First Embodiment. 
           [0020]      FIG. 9  is an explanatory diagram illustrating one example of a circuit configuration of a power supply cell  600 A according to a modified example of the First Embodiment. 
           [0021]      FIG. 10A  is an explanatory diagram illustrating one example of a power supply cell  600 B according to a Second Embodiment. 
           [0022]      FIG. 10B  is an explanatory diagram illustrating one example of the power supply cell  600 B according to the Second Embodiment. 
           [0023]      FIG. 11A  is an explanatory diagram illustrating one example of a circuit configuration of one power supply cell according to one modified example of the Second Embodiment. 
           [0024]      FIG. 11B  is an explanatory diagram illustrating one example of a circuit configuration of another power supply cell according to another modified example of the Second Embodiment. 
           [0025]      FIG. 12A  is an explanatory diagram illustrating one example of a circuit configuration of a power supply cell according to a Third Embodiment. 
           [0026]      FIG. 12B  is an explanatory diagram illustrating one example of a circuit configuration of a power supply cell according to a modified example of the Third Embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0027]    Preferred embodiments of the present disclosure will be described in detail with reference to the drawings. Incidentally, the same numerals are assigned to the same or corresponding parts in the drawinga and the description thereof is omitted. In addition, in the embodiments of the present disclosure, the semiconductor device means any of a semiconductor wafer formed by integration of electronic circuits, each semiconductor chip formed by dicing the semiconductor wafer into chips and the one formed by packaging one semiconductor chip or a pluralitry of the semiconductor chips with resin and so forth. 
       First Embodiment  
       [0028]      FIG. 1  is an explanatory diagram illustrating one example of the entire of the semiconductor device  1  according to a First Embodiment. 
         [0029]    As illustrated in  FIG. 1 , the semiconductor device  1  includes a circumferential I/O region  4  which is provided in an outer peripheral region and a core logic region  2  which is arranged in an internal region and is configured as an ASIC (application specific integrated circuit) having a predetermined function. 
         [0030]    The circumferential I/O region  4  includes the I/O cell  500  serving as an input/output interface for a signal, the power supply cell  600  which receives an input from an external power supply and so forth. Here, a case where the power wire VM and a ground wire GM are arranged in the outer peripheral region is illustrated. A pad VP is a pad for power supply and a pad GP is a pad for grounding and the pads MP and GP are coupled with the power supply cell  600 . A pad SP is a pad for signal and is coupled with the I/O cell  500 . Incidentally, the pads VP, GP and SP are provided along an outer peripheral side of the semiconductor device  1  in  FIG. 1 . 
         [0031]      FIG. 2  is an explanatory diagram illustrating one example of a circuit configuration of the I/O cell  500  according to the First Embodiment. As illustrated in  FIG. 2 , the I/O cell  500  includes protection diodes D 1  and D 2 , a P channel MOS transistor  502 , an N channel MOS transistor  506 , drivers  504  and  508 , a resistor  510 , an input/output circuit  520  and so forth. 
         [0032]    The signal pad SP is coupled with a node N 4 . The protection diode D 1  is provided between the node N 4  and the power wire VM. The protection diode D 1  is coupled with the node N 4  on the anode side and is coupled with the power wire VM on the cathode side. Here, the signal pad SP serves as an input/output pad and it is possible for the signal pad to receive an input signal and to output an output signal. 
         [0033]    The protection diode D 2  is provided between the node N 4  and the ground wire GM. The protection diode D 2  is coupled with the ground wire GM on the anode side and is coupled with the node N 4  on the cathode side. The resistor  510  is provided between the node N 4  and an input circuit  522 . 
         [0034]    The P channel MOS transistor  502  is provided in parallel with the protection diode D 1  and is coupled in series between the node N 4  and the power wire VM via the resistor  510 . The P channel MOS transistor  502  receives an input signal from the driver  504 . Incidentally, the drivers  504  and  508  each includes an even number of later described inverters and the power is supplied to the drivers  504  and  508  respectively through the power wire VM and the ground wire GM. 
         [0035]    The N channel MOS transistor  506  is provided in parallel with the protection diode D 2  and is coupled in series between the node N 4  and the ground wire GM via the resistor  510 . The N channel MOS transistor  506  receives an input signal from the driver  508 . 
         [0036]    The input/output circuit  520  is provided between the power wire VM and the ground wire GM. The input/output circuit  520  includes an output logic circuit  521  which drives the drivers  504  and  508 , the input circuit  522  which processes the input signal which is sent from the pad SP via the resister  510  and a level shifter  523  which boosts (steps-up)/bucks (steps-down) the level of each signal. 
         [0037]    Any one of the drivers  504  and  508  operates in accordance with a signal from the output logic circuit  521 . Then, the P channel MOS transistor  502  or the N channel MOS transistor  506  conducts and the signal is output from the signal pad SP. 
         [0038]      FIG. 3  is an explanatory diagram illustrating one example of a circuit configuration of the power supply cell  600  according to the First Embodiment. As illustrated in  FIG. 3 , the power supply cell  600  includes an N channel MOS transistor  604 , an inverter  603 , resistive elements  602  and  609 , a capacitive element  610 , P channel MOS transistors  606 ,  607  and  608 , an N channel MOS transistor  611  and so forth which configure a power clamp circuit (a protection circuit). A diode  601  is a parasitic diode of the N channel MOS transistor  604 . 
         [0039]    The diode  601  is coupled with the ground wire GM on the anode side and is coupled with the power wire VM on the cathode side. 
         [0040]    The N channel MOS transistor  604  is coupled between the power wire VM and the ground wire GM and a gate of the N channel MOS transistor  604  is coupled with an output node N 2  of the inverter  603 . 
         [0041]    The P channel MOS transistor  606  is coupled between the power wire VM and the ground wire GM in series with a resistive element  609  and an N channel MOS transistor  611 . 
         [0042]    The P channel MOS transistor  606  is provided between the power wire VM and a node N 0  and a gate of the P channel MOS transistor  606  is coupled with the node N 0 . The resistive element  609  is coupled in series with the P channel MOS transistor  606 , is coupled with the node N 0  on one end side and is coupled with the N channel MOS transistor  611  on the other end side. The N channel MOS transistor  611  is coupled between the resistive element  609  and the ground wire GM and a gate of the N channel MOS transistor  611  is coupled with the output node N 2 . 
         [0043]    The P channel MOS transistor  607  is provided between the power wire VM and a node N 1  so as to form a current mirror circuit together with the P channel MOS transistor  606  and a gate of the P channel MOS transistor  607  is coupled with the node N 0 . The capacitive element  610  is coupled between the power wire VM and the ground wire GM in series with the P channel MOS transistor  607  via the node N 1 . 
         [0044]    The inverter  603  outputs an inversion signal of a signal from the node N 1  to the node N 2  by using the node N 1  as its input side. Incidentally, although a power supply of the inverter  603  is not illustrated, the power is supplied to the inverter  603  through the power wire VM and the ground wire GM and the same also applies to other embodiments. 
         [0045]    The resistive element  602  is coupled between the node N 2  and the ground wire GM. Since an output from the inverter  603  is pulled down to the ground wire GM via the resistive element  602 , it is possible to suppress a fluctuation in level of an input into a gate of the N channel MOS transistor  604  when the level of an output from the inverter  603  has undesirably fluctuated. 
         [0046]    The N channel MOS transistor  611  functions as an element which activates the current mirror circuit which is configured by the P channel MOS transistors  606  and  607 , the resistive element  609  and so forth. The current mirror circuit is activated by turning the N channel MOS transistor  611  ON. On the other hand, when the N channel MOS transistor  611  is in an OFF state, the current mirror circuit is in an inactivated state. Here, activation of the current mirror circuit means to flow current to the transistors which configure the current mirror circuit to operate the current mirror circuit and the same also applies to other embodiments. 
         [0047]    The P channel MOS transistor  608  is coupled between the power wire VM and the node N 1  in parallel with the P channel MOS transistor  607  and a gate of the P channel MOS transistor  608  is coupled with the output node N 2 . The P channel MOS transistor  608  operates complementarily to the N channel MOS transistor  611 . That is, when the N channel MOS transistor  611  is in an ON state, the P channel MOS transistor  608  is in the OFF state. On the other hand, in case of a steady state where the N channel MOS transistor  611  is in the OFF state, the P channel MOS transistor  608  is turned ON and couples the power wire VM with the node N 1  so as to make it possible to suppress undesirable level fluctuation of the node N 1 . 
         [0048]    Incidentally, although, here, the configuration of the power clamp circuit has been described as one example of the power supply cell  600 , the power supply cell  610  maybe configured as another circuit not limited to the power clamp circuit. 
         [0049]    Here, a case where the ESD current is flowed into (applied to) the pad VP will be described. In the steady state, the level (of the potential) of the output node N 2  of the inverter  603  is set to an “L” level. Accordingly, the N channel MOS transistor  604  is in the OFF state. In addition, the P channel MOS transistor  608  is in the ON state. Since the level of the output node N 2  is at the “L” level, the N channel MOS transistor  611  is in the OFF state and the current mirror circuit is in the inactivated state. 
         [0050]    On the other hand, when a high voltage generated owing to application of the ESD current is applied to the pad VP, the level of the power wire VM is directly changed following high voltage application. A potential difference (Vgs) is temporarily generated between a gate and a source of a P channel MOS transistor which configures the inverter  603  with changing the level of the power wire VM and the P channel MOS transistor is turned ON. Thereby, the level of the output node N 2  is temporarily changed from the “L” level to an “H” level. 
         [0051]    The N channel MOS transistor  604  is brought into the ON state with changing a gate potential of the output node N 2  and the high voltage in the power wire VM is released into the ground wire GM. 
         [0052]    In addition, the P channel MOS transistor  608  is turned OFF with changing the level of the output node N 2  to the “H” level. In addition, the N channel MOS transistor  611  is turned ON and the current mirror circuit comes to operate. 
         [0053]    Current flows from the power wire VM into the capacitive element  610  which is coupled with the node N 1  via the P channel MOS transistor  607  with activation of the current mirror circuit. In that occasion, the level of the node N 1  is changed and increased while being delayed in accordance with a time constant. Then, when the potential at the node N 1  has exceeded a threshold value of the inverter  603 , the N channel MOS transistor of the inverter  603  is turned ON. Thereby, the level of the output node N 2  again shifts to the “L” level. 
         [0054]    The N channel MOS transistor  604  is brought into the OFF state with changing the gate potential of the output node N 2  and current outflow from the power wire VM toward the ground wire GM is stopped. In addition, the N channel MOS transistor  611  is turned OFF and the current mirror circuit is inactivated. In addition, the P channel MOS transistor  608  is turned ON and the node N 1  and the power wire VM are electrically coupled together. Thereby, the circuit again returns to the steady state. 
         [0055]      FIG. 4  is an explanatory diagram illustrating one example of transition of each node and the power wire VM when the ESD current has been flown into each node and the power wire VM. 
         [0056]    As illustrated in  FIG. 4 , the level of the output node N 2  is temporarily changed from the “L” level to the “H” level. Thereby, the N channel MOS transistor  604  is turned ON and the ESD current flows toward the ground wire GM side. 
         [0057]    The P channel MOS transistor  608  begins turning ON at a timing PA. Thereby, the potential of the node N 1  begins gradually increasing. 
         [0058]    Then, the N channel MOS transistor  604  is gain turned OFF by changing the level of the output node N 2  to the “L” level. Thereby, a current path from the power wire VM to the ground wire GM is shut off. 
         [0059]    The protection circuit of the power supply cell  600  according to the First Embodiment is of a system that an amount of current flowing into the P channel MOS transistor  607  is adjusted by the current mirror circuit. Specifically, gate widths of the resistive element  609  and the P channel MOS transistor  607  are adjusted. As one example, the gate width of the P channel MOS transistor  607  is set to 1/N (N: 2 or more) the gate width of the P channel MOS transistor  606 . It becomes possible to set the amount of current flowing into the P channel MOS transistor  607  to 1/N the amount of current flowing into the P channel MOS transistor  606  by setting the gate width of the P channel MOS transistor  607  to 1/N the gate width of the P channel MOS transistor  606 . 
         [0060]    In the example illustrated in  FIG. 4 , the amount of current which flows through the P channel MOS transistor  606  of the current mirror circuit is adjusted and the gate width of the P channel MOS transistor  607  is adjusted on the basis of the state of the resistive element  609 , and thereby the amount of current which flows into the P channel MOS transistor  607  is adjusted. Thereby, it becomes possible to set a resistance value of the resistive element  609  small. It becomes possible to reduce an area of the circuit by setting the resistance value of the resistive element  609  small. In the following, description will be made on the above-mentioned point. 
         [0061]      FIG. 5A ,  FIG. 5B  and  FIG. 5C  are explanatory diagrams each illustrating one example of a configuration of a protection circuit according to a comparative example.  FIG. 5A  is the explanatory diagram illustrating one example of the configuration of the protection circuit. As illustrated in  FIG. 5A , a power clamp circuit (the protection circuit) of the comparative example includes an N channel MOS transistor  604 #, an inverter  603 #, resistive elements  602 # and  609 H and a capacitive element  610 #. A diode  601 # is a parasitic diode of the N channel MOS transistor  604 #. In addition, a power supply pad VP# and a ground pad GP# are respectively coupled to the power wire VM and the ground wire GM. 
         [0062]    Here, a case where the ESD current is flown into (applied to) the pad VP# will be described. In the steady state, the level of an output node N 2 # of the inverter  603 # is set to the “L” level. Accordingly, the N channel MOS transistor  604 # is in the OFF state. 
         [0063]    On the other hand, when the high voltage generated owing to application of the ESD current is applied to the pad VP#, the level of the power wire VM is directly changed following high voltage application. The potential difference (Vgs) is temporarily generated between a gate and a source of a P channel MOS transistor which configures the inverter  603 # with changing the level of the power wire VM and the P channel MOS transistor is turned ON. Thereby, the level of the output node N 2 # is temporarily changed from the “L” level to the “H” level. 
         [0064]    The N channel MOS transistor  604 # is brought into the ON state with changing the gate potential of the output node N 2 # and the high voltage in the power wire VM is released into the ground wire GM. 
         [0065]    On the other hand, current flows into the capacitive element  610 # which is coupled with a node N 1 # via the resistive element  609 #. In that occasion, the level of the N 1 # is increased while being delayed in accordance with an RC time constant of the resistive element  609 # and the capacitive element  610 #. Then, when the potential of the node N 1 # has exceeded a threshold value of the inverter  603 #, an N channel MOS transistor of the inverter  603 # is turned ON. Thereby, the level of the output node N 2 # again shifts to the “L” level. 
         [0066]    Thereby, the circuit again returns to the steady state.  FIG. 5B  is the explanatory diagram illustrating one example of a change in RC time constant. 
         [0067]    A waveform obtained when electric charge is charged into the capacitive element  610 # is illustrated in  FIG. 5B . 
         [0068]    Here, a voltage V is expressed as voltage V=VCCQ (1−e− t/Rc ). This formula is deformed to t=−1oge (V/VCCQ) *RC. Then, RC is expressed as RC=−t/1oge (V/VCCQ) . Here, for example, the threshold value of the inverter  603 # to be coupled to an RC time constant circuit is set to about 0.5*VCCQ (V/VCCQ=about 0.5 ) and a necessary time t is set to about 0.5 μs. 
         [0069]    Then, RC=−1 μs/1oge (0.5) =about 0.77*10 −6  is obtained. If a capacitance value C of the capacitive element  610 # is 1 pF, about 770 kΩ will be necessary as a resistance value R of the resistive element  609 #. 
         [0070]    Accordingly, since the capacitance value C of the capacitive element  610 # and the resistance value R of the resistive element  609 # amount to considerably high values, the layout area when designing the capacitive element  610  and the resistive element  609  is increased. 
         [0071]      FIG. 5C  schematically illustrates one example of an area ratio that the protection circuit occupies when laying out the protection circuit. 
         [0072]    Here, when the capacitive element  610 # of the capacitance value C=1 pF is to be designed with MOS capacitors, about 60 or more capacitors are necessary in case of a MOS transistor having the gate width of about 5 μm and the gate length of about 0.55 μm. 
         [0073]    In addition, when the resistive element  609 # of the resistance value R=about 770 kΩ is to be designed with polysilicon resistors, it becomes necessary to serially couple about 25 or more resistors in case of a polysilicon resistor having the gate width of about 0.4 μm and the gate length of about 24 μm respectively. Accordingly, as illustrated in  FIG. 5C , the area ratio that the capacitive element  610 # and the resistance element  609 # occupy becomes considerably high. 
         [0074]    On the other hand, the protection circuit of the power supply cell  600  according to the present First Embodiment is of the system that the amount of current flowing into the P channel MOS transistor  607  is adjusted by the current mirror circuit as described above. 
         [0075]    Here, a case where the capacitive element  610  is designed with the same capacity value as that of the capacitive element  610 # will be considered. Then, a case where the same amount of current as that of the capacitive element  610 # is supplied to the capacitive element  610  will be considered. 
         [0076]    In the configuration of the protection circuit in the comparative example, it is necessary to set the resistance value of the resistive element  609 # high so as to reduce the amount of current to be supplied to the capacitive element. While, in the system according to the present First Embodiment, it is possible to reduce the current amount by adjusting the gate width of the P channel MOS transistor  607 . 
         [0077]    Specifically, the gate width of the P channel MOS transistor  607  is set to about 1/N (N: 2 or more) the gate width of the P channel MOS transistor  606 . 
         [0078]    Accordingly, the current flowing into the P channel MOS transistor  606  of the current mirror circuit is set to N times the current flowing into the P channel MOS transistor  607 . 
         [0079]    Thereby, it is possible to set the resistance value of the resistive element  609  to be coupled to the P channel MOS transistor  607  is set to 1/N the resistance value R of the resistive element  609 #. 
         [0080]      FIG. 6  is a diagram illustrating one example of comparison in layout between the protection circuit of the comparative example and the power supply cell  600  according to the First Embodiment. 
         [0081]    As illustrated in  FIG. 6 , since it is possible to reduce the resistance value of the resistive element  609  owing to the above-mentioned configuration, it is possible to reduce the layout area of the polysilicon resistor which forms the resistive element  609  and thereby it is possible to reduce the layout area of the entire protection circuit more than the layout area of the configuration of the comparative example. 
         [0082]      FIG. 7  is an explanatory diagram illustrating one example of a layout configuration of the current mirror circuit of the power supply cell  600  according to the First Embodiment. 
         [0083]    A case where N P channel MOS transistors are adjacently provided relative to one P channel MOS transistor  607  which configures the current mirror circuit is illustrated in  FIG. 7 . 
         [0084]    Each transistor includes a gate electrode, a source electrode, a drain electrode, a diffusion layer DF and so forth. In addition, the gate electrode is provided between the source electrode and the drain electrode. 
         [0085]    The source electrode of each transistor is coupled to the power wire VM and the drain electrode of each transistor is coupled to the resistor  609 . 
         [0086]    The source electrode and the drain electrode of each transistor are formed in a metal layer M 2  which is the second layer configuring each transistor. The metal layer M 2  is coupled with the diffusion layer DF through a contact hole CT. 
         [0087]    The gate electrodes of the respective transistors are commonly coupled to a metal layer M 1  which is the first layer. Gates on the both ends of each gate electrode are dummy gates and the dummy gates are not used for formation of the transistor. 
         [0088]    The metal layer M 2  which forms the drain electrode provided between the gate which forms the transistor  607  and the dummy gate is coupled to a capacitor  610 . The dummy gate is also coupled to the power wire VM through the contact hole CT. 
         [0089]    In addition, the metal layer M 1  to be coupled with the gate electrode is coupled with the metal layer M 2  which forms the drain electrode through the contact hole CT. Incidentally, although a plurality of the contact holes CT are present in each electrode, one or two contact hole(s) is/are illustrated in  FIG. 7  and illustration of the remaining contact holes CT is omitted. 
         [0090]      FIG. 8  is an explanatory diagram illustrating one example of a layout configuration of the resistive element of the power supply cell  600  according to the First Embodiment. 
         [0091]    In  FIG. 8 , as the layout configuration of the resistive element  609  (the polysilicon resistor), sub-elements of the resistive element  609  are coupled in series with one another via the contact holes CT and the metal layers M 1  into the folded form. Here, the above-described gate width W and gate length L are illustrated. 
         [0092]    Incidentally, although in the First Embodiment, a case where the capacitive element  610  is designed with the same capacity value as that of the capacitive element  610 # has been described by way of example, the present disclosure is not limited to the case and the capacity value of the capacitive element  610  may be further reduced by adjusting the gate width of the P channel MOS transistor  607  so as to reduce the amount of current. Thereby, it is possible to further reduce the layout area of the entire protection circuit by further reducing the ratio that the MOS capacitors of the capacitive element  610  occupy. Incidentally, the same also applies to the following embodiments. 
         [0093]    Incidentally, although in the First Embodiment, the configuration that the gate width is adjusted as the size of the P channel MOS transistor  607  so as to reduce the current amount has been described, the size to be reduced is not limited to the gate width and the gate length may be adjusted so as to reduce the current amount. For example, the gate length of the P channel MOS transistor  607  is set longer than the gate length of the P channel MOS transistor  606  by way of example. It is possible to more reduce the amount of current flowing into the P channel MOS transistor  607  than the amount of current flowing into the P channel MOS transistor  606  by setting the gate length of the P channel MOS transistor  607  longer than the gate length of the P channel MOS transistor  606 . 
       MODIFIED EXAMPLE  
       [0094]      FIG. 9  is an explanatory diagram illustrating one example of a circuit configuration of a power supply cell  600 A according to a modified example of the First Embodiment. 
         [0095]    As illustrated in  FIG. 9 , the power supply cell  600 A is of a configuration that a function of controlling a back gate of the N channel MOS transistor  604  is added in comparison with the power supply cell  600 . 
         [0096]    Specifically, the power supply cell  600 A is different from the power supply cell  600  in that an inverter  603 A has been provided between the node N 1  and the back gate of the N channel MOS transistor  604  and a resistive element  602 A has been added between an output node of the inverter  603 A and the ground wire GM. Other configurations are the same as those of the First Embodiment and therefore detailed description thereof is omitted. 
         [0097]    The resistive element  602 A is coupled between the output node of the inverter  603 A and the ground wire GM. Since an output from the inverter  603 A is pulled down to the ground wire GM via the resistive element  602 A, it is possible to suppress fluctuation of an input into the back gate region (the well region) when the output from the inverter  603 A has undesirably fluctuated. 
         [0098]    A parasitic diode  605  is formed on a junction between the back gate region (the well region) and a source of the N channel MOS transistor  604 . There is the possibility that the level of a gate input when the N channel MOS transistor  604  is to be turned ON may be lowered by the amount of a forward voltage (VF) of the parasitic diode  605  due to the action of the parasitic diode  605  and it may become difficult to fully swing the gate input into the N channel MOS transistor  604 . 
         [0099]    Therefore, it becomes possible to fully swing the gate input when the N channel MOS transistor  604  is to be turned ON by preforming gate input into the N channel MOS transistor  604  and biasing of the back gate region (the well region) of the N channel MOS transistor  604  by mutually different inverters  603  and  603 A. Thereby, it is possible to promote speeding-up of ESD current discharge of the N channel MOS transistor  604 . 
         [0100]    Incidentally, in the modified example in  FIG. 9 , although the configuration that the N channel MOS transistor  611  which activates the current mirror circuit and the P channel MOS transistor  608  which operates complementarily to the N channel MOS transistor  611  are used has been described, a configuration with no provision of such transistors as mentioned above is also possible. 
       Second Embodiment  
       [0101]    In a Second Embodiment, a system configured to further improve the ESD discharge characteristic will be described. 
         [0102]      FIG. 10A  and  FIG. 10B  are explanatory diagrams each illustrating one example of a circuit configuration of a power supply cell  600 B according to the Second Embodiment.  FIG. 10A  is the explanatory diagram of one example of the circuit configuration of the power supply cell  600 B. 
         [0103]    As illustrated in  FIG. 10A , the power supply cell  600 B is different from the power supply cell  600 A in that an inverter  620  and a resistive element  621  have been further provided. 
         [0104]    The inverter  620  outputs a signal to a node N 3  with the node N 1  being used as an input node. A gate of the P channel MOS transistor  608  is coupled with the node N 3 . In addition, the N channel MOS transistor  611  is coupled with node N 3 . 
         [0105]    The resistive element  621  is coupled between the node N 3  and the ground wire GM. The power supply cell  600 B is different from the power supply cell  600 A in that the gates of the P channel MOS transistor  608  and the N channel MOS transistor  611  receive not the output from the inverter  603  but the output from the inverter  620 . 
         [0106]    Since other configurations and operations are the same as those of the power supply cell  600 A, detailed description thereof is omitted.  FIG. 10B  is the explanatory diagram illustrating one example of transition of each node and the power wire VM when the ESD current has been flown into each node and the power wire VM. 
         [0107]    As illustrated in  FIG. 10B , the level of the output node N 2  is temporarily changed from the “L” level to the “H” level. Thereby, the N channel MOS transistor  604  is turned ON and the ESD current flows toward the ground wire GM side. 
         [0108]    The P channel MOS transistor  608  beings turning ON at the timing PA and thereby the potential of the node N 1  beings gradually increasing. 
         [0109]    Then, the level of the output node N 2  is changed to the “L” level and thereby the N channel MOS transistor  604  is again turned OFF. Thereby, the current path from the power wire VM to the ground wire GM is shut off. 
         [0110]    In the example in  FIG. 4 , since the output node N 2  of the inverter  603  is coupled to the gate of the N channel MOS transistor  608 , the P channel MOS transistor  608  begins turning ON after the timing PA. Thereby, potential increasing of the node N 1  is accelerated. 
         [0111]    On the other hand, in the example illustrated in  FIG. 10B , the P channel MOS transistor  608  is turned ON at a timing PB that the potential of the node N 1  has been sufficiently increased. 
         [0112]    Accordingly, early increasing of the potential of the node N 1  is suppressed by delaying a timing that the P channel MOS transistor  608  is turned ON and thereby it is possible to delay a time that the gate potential of the N channel MOS transistor  604  is set to the “L” level. Thereby, the ON time of the N channel MOS transistor  604  is increased without increasing the values of the resistive element  609  and the capacitive element  610 , and thereby it becomes possible to further improve the ESD discharge characteristic and it becomes also possible to reduce the layout area. 
       Modified Examples of Second Embodiment  
       [0113]      FIG. 11A  and  FIG. 11B  are explanatory diagrams each illustrating one example of a circuit configuration of a power supply cell according to a modified example of the Second Embodiment. 
         [0114]      FIG. 11A  is an explanatory diagram illustrating one example of the circuit configuration of a power supply cell  600 C. As illustrated in  FIG. 11A , the power supply cell  600 C is different from the power supply cell  600 B in that a P channel MOS transistor  630  has been provided in place of the inverter  620 . Other configurations are the same as those of the power supply cell  600 B. 
         [0115]    That is, the power supply cell  600 C is of a configuration that the N channel MOS transistor which configures the inverter  620  has been deleted. The configuration is of the type that potential decreasing of the node N 3  caused by provision of the N channel MOS transistor has been eliminated. Elimination of the N channel MOS transistor makes it difficult to decrease the potential of the node N 3  and thereby it becomes possible to delay the timing that the P channel MOS transistor  608  is turned ON. 
         [0116]    Thereby, early increasing of the potential of the node N 1  is suppressed and thereby it becomes possible to delay the time that the gate potential of the N channel MOS transistor  604  is set to the “L” level. Thereby, the ON time of the N channel MOS transistor  604  is increased without increasing the values of the resistance element  609  and the capacitive element  610 , and thereby it becomes possible to further improve the ESD discharge characteristic and it becomes also possible to reduce the layout area. 
         [0117]      FIG. 11B  is the explanatory diagram illustrating one example of a circuit configuration of a power supply cell  600 D. As illustrated in  FIG. 11B , the power supply cell  600 D is different from the power supply cell  600 B in that the resistive element  621  has been deleted. Other configurations are the same as those of the power supply cell  600 B. 
         [0118]    That is, it is made difficult to decrease the potential of the node N 3  by deleting the resistive element  621  and thereby it becomes possible to delay the timing that the P channel MOS transistor  608  is turned ON. 
         [0119]    Thereby, early increasing of the potential of the node N 1  is suppressed and thereby it is possible to delay the time that the gate potential of the N channel MOS transistor  604  is set to the “L” level. Thereby, the ON time of the N channel MOS transistor  604  is increased without increasing the values of the resistance element  609  and the capacitive element  610 , and thereby it becomes possible to further improve the ESD discharge characteristic and it becomes also possible to reduce the layout area. 
       Third Embodiment  
       [0120]      FIG. 12A  and  FIG. 12B  are explanatory diagrams each illustrating one example of a circuit configuration of a power supply cell according to a Third Embodiment. 
         [0121]      FIG. 12A  is the explanatory diagram illustrating one example of a circuit configuration of a power supply cell  700 . As illustrated in  FIG. 12A , the power supply cell  700  is different from the power supply cell  600  in that the current mirror circuit is formed by N channel MOS transistors. 
         [0122]    Specifically, the power supply cell  700  is different from the power supply cell  600  in that N channel MOS transistors  706 ,  707  and  708  have been provided in place of the P channel MOS transistors  606 ,  607  and  608 , a P channel MOS transistor  711  has been provided in place of the N channel MOS transistor  611  and further an inverter  712  has been added. 
         [0123]    Specifically, the N channel MOS transistor  706  is coupled in series with the resistive element  609  and the P channel MOS transistor  711  between the power wire VM and the ground wire GM. 
         [0124]    The N channel MOS transistor  706  is provided between the ground wire GM and the node N 3  and a gate thereof is coupled with the node N 3 . The resistive element  609  is coupled in series with the N channel MOS transistor  706 , is coupled with the node N 3  on the one end side thereof and is coupled with the P channel MOS transistor  711  on the other end side thereof. The P channel MOS transistor  711  is coupled between the resistive element  609  and the power wire VM and a gate thereof is coupled with a node N 5 . 
         [0125]    The inverter  712  is coupled with the node N 4  on the input side thereof and outputs a signal to the node N 5 . The N channel MOS transistor  707  is provided between the ground wire GM and the node N 4  so as to form a current mirror circuit together with the N channel MOS transistor  706  and a gate thereof is coupled with the node N 3 . 
         [0126]    The capacitive element  610  is coupled in series with the N channel MOS transistor  707  via the node N 4  between the power wire VM and the ground wire GM. 
         [0127]    The inverter  603  outputs an inversion signal of a signal input into the node N 5  to the output node N 2  with the node N 5  being set as its input side. 
         [0128]    The P channel MOS transistor  711  functions as an element which activates the current mirror circuit configured by the N channel MOS transistors  706  and  707  and the resistive element  609 . The current mirror circuit is activated by turning the P channel MOS transistor  711  ON. On the other hand, when the P channel MOS transistor  711  is in the OFF state, the current mirror circuit is an inactivated state. 
         [0129]    The N channel MOS transistor  708  is coupled in parallel with the N channel MOS transistor  707  between the ground wire GM and the node N 4  and a gate thereof is coupled with the node N 5 . The N channel MOS transistor  708  operates complementarily to the P channel MOS transistor  711 . That is, when the P channel MOS transistor  711  is in the ON state, the N channel MOS transistor  708  is in the OFF state. On the other hand, in the steady state where the P channel MOS transistor  711  is in the OFF state, the N channel MOS transistor  708  is turned ON to couple the ground wire GM with the node N 4  to make it possible to suppress undesirable level fluctuation of the node N 4 . 
         [0130]    Incidentally, although, here, the configuration of the power clamp circuit has been described as one example of the power supply cell  700 , the power supply cell  700  is not limited to the power clamp circuit and may configure another circuit. 
         [0131]    Here, a case where the ESD current is flown into (applied to) the pad VP will be described. The level of the node N 4  is set to the “L” level in the steady state. The level of the node N 5  which is provided with the inverter  712  interposed is set to the “H” level. Accordingly, the N channel MOS transistor  708  is in the ON state. In addition, since the level of the node N 5  is set to the “H” level, the level of the output node N 2  of the inverter  603  is set to the “L” level. Accordingly, the N channel MOS transistor  604  is in the OFF state. 
         [0132]    Since the level of the node N 5  is set to the “H” level, the P channel MOS transistor  711  is in the OFF state and the current mirror circuit is in the inactivated state. 
         [0133]    On the other hand, when the high voltage generated owing to application of the ESD current is applied to the pad VP, the level of the power wire VM is directly changed following high voltage application. The potential difference (Vgs) is temporarily generated between the gate and the source of the P channel MOS transistor which configures the inverter  603  with changing the level of the power wire VM and the P channel MOS transistor is turned ON. Thereby, the level of the output node N 2  is temporarily changed from the “L” level to an “H” level. The N channel MOS transistor  604  is brought into the ON state with changing the gate potential of the output node N 2  and the high voltage in the power wire VM is released into the ground wire GM. 
         [0134]    In addition, the N channel MOS transistor  708  is turned OFF with changing the level of the output node N 5  from the “H” level to the “L” level. In addition, the P channel MOS transistor  711  is turned ON and the current mirror circuit comes to operate. 
         [0135]    Current flows from the node N 4  toward the ground wire GM via the N channel MOS transistor  707  with activation of the current mirror circuit. In that occasion, the level of the node N 1  is changed and decreased while being delayed in accordance with the time constant. Then, when the potential of the node N 4  has exceeded a threshold value of the inverter  712 , the level of the node N 5  is set to the “H” level and the N channel MOS transistor of the inverter  603  is turned ON. Thereby, the level of the potential of the output node N 2  again shifts to the “L” level. 
         [0136]    The N channel MOS transistor  604  is brought into the OFF state with changing the gate potential of the output node N 2  and current outflow from the power wire VM into the ground wire GM is stopped. In addition, the P channel MOS transistor  711  is turned OFF and the current mirror circuit is inactivated. In addition, the N channel MOS transistor  708  is turned ON and the node N 1  and the power wire VM are electrically coupled together. Thereby, the circuit again returns to the steady state. 
         [0137]    In the example illustrated in  FIG. 12A , the amount of current flowing through the N channel MOS transistor  706  of the current mirror circuit is adjusted and the gate width of the N channel MOS transistor  707  is adjusted on the basis of the state of the resistive element  609 , and thereby the amount of current flowing into the N channel MOS transistor  707  is adjusted. Thereby, it becomes possible to set the resistance value of the resistive element  609  small as described in the First Embodiment. It becomes possible to reduce the circuit area by setting the resistance value of the resistive element  609  small. 
         [0138]      FIG. 12B  is the explanatory diagram illustrating one example of a circuit configuration of a power supply cell  700 A according to a modified example of the Third Embodiment. 
         [0139]    As illustrated in  FIG. 12B , the power supply cell  700 A is of a configuration that a function of controlling the back gate of the N channel MOS transistor  604  has been added in comparison with the power supply cell  700 . 
         [0140]    Specifically, the power supply cell  700 A is different from the power supply cell  700  in that the inverter  603 A has been provided between the node N 5  and the back gate of the N channel MOS transistor  604  and the resistive element  602 A has been added between the output node of the inverter  603 A and the ground wire GM. Other configurations are the same as those of the power supply cell  700  and therefore detailed description thereof is omitted. 
         [0141]    The resistive element  602 A is coupled between the output node of the inverter  603 A and the ground wire GM. Since the output from the inverter  603 A is pulled down to the ground wire GM via the resistive element  602 A, it is possible to suppress fluctuation of an input into the back gate region (the well region) when the output from the inverter  603 A has undesirably fluctuated. 
         [0142]    The parasitic diode  605  is formed on the junction between the back gate region (the well region) and the source of the N channel MOS transistor  604 . There is the possibility that the level of the gate input when the N channel MOS transistor  604  is to be turned ON may be lowered by the amount of the forward voltage (VF) of the parasitic diode  605  due to the action of the parasitic diode  605  and it may become difficult to fully swing the gate input into the N channel MOS transistor  604 . 
         [0143]    Therefore, it is possible to fully swing the gate input when the N channel MOS transistor  604  is to be turned ON by preforming gate input into the N channel MOS transistor  604  and biasing of the back gate region (the well region) of the N channel MOS transistor  604  by mutually different inverters  603  and  603 A. Thereby, it is possible to promote speeding-up of the ESD current discharge of the N channel MOS transistor  604 . 
         [0144]    Since even when the current mirror circuit is configured by the N channel MOS transistors, it becomes possible to decrease the resistance value of the resistance element  609  as in the case in the First Embodiment, it becomes possible to more reduce the layout area of the entire protection circuit than the configuration of the comparative example by reducing the layout area of the polysilicon resistor which forms the resistive element  609 . 
         [0145]    Although, in the foregoing, the present disclosure has been described specifically on the basis of the preferred embodiments, it goes without saying that the present disclosure is not limited to the above-mentioned embodiments and may be modified in a variety of ways within a range not deviating from the gist of the present disclosure.