Abstract:
Our semiconductor memory device has row repair circuitry by which defective wordlines are substituted with redundant wordlines regardless of locations of cell array blocks, the redundant wordlines being divisionally arranged in memory blocks with the same number. The semiconductor memory device has a plurality of memory blocks each including the predetermined number of redundant wordlines, a plurality of row repair fuse boxes being divisionally arranged with the same number respective in the memory blocks, the number of the row repair fuse boxes being identical to the number of the redundant wordlines, and repair means to replace defective wordlines with the redundant wordlines.

Description:
[0001]    This application relies for priority upon Korean Patent Application No. 2001-25144, filed on May 9, 2001, the contents of which are herein incorporated by reference in their entirety.  
         BACKGROUND  
         [0002]    1. Field of Invention  
           [0003]    The inventions disclosed herein generally relate to a semiconductor memory device having a capacity of redundancy. More particularly, they relate to a semiconductor memory device having row repair circuitry in which defective wordlines are substituted with redundant wordlines regardless of locations of memory blocks. A predetermined number of the redundant wordlines is arranged in each memory block.  
         GENERAL BACKGROUND AND RELATED ART  
         [0004]    It is usual that various kinds of defects are generated throughout a manufacturing process for a semiconductor memory device (e.g., a DRAM), thereby causing the memory device to malfunction and reducing the yield of its manufacturing process. Even one defect over a cell array in the semiconductor memory device may easily interrupt normal operations such as data read-out and write-in. For this reason, it is known to substitute defective memory cells with additionally prepared memory cells (i.e., redundant or spare memory cells), thereby increasing the yield of manufacture and reliability of the memory device. When one or more defective memory cells are detected by a test operation, the defective memory cells are substituted with the redundant memory cells that are arranged in the unit of row or column in a memory cell array of the memory device, thereby allowing the memory device to be used even though it has some defective cells.  
           [0005]    [0005]FIG. 1 is a schematic representation of a DRAM. Consider a conventional 64M (64 megabits; M=2 20 ) DRAM constructed of four memory banks MB 0 , MB 1 , MB 2  and MB 3 . Each memory bank has a storage capacity of 16M and an associated peripheral block PBL in which input/output pads are arranged and which includes input/output buffers and multiplexers assigned to the input/output pads. The peripheral block PBL where pads for address and control signals are positioned includes control signal buffers and address buffers being coupled to their corresponding pads, and further a control logic unit and a command state machine. Column control logic blocks CCL 0 ˜CCL 3  each assigned to their corresponding memory banks have Y-decoders (or column decoders), drivers and data bus sense amplifiers to write data in memory cells or to read data from memory cells. Row control logic blocks assigned to their corresponding memory banks and which include X-decoders (or row decoders) and logic circuits for driving wordlines.  
           [0006]    Each memory block has the predetermined number of redundant wordlines assigned thereto exclusively. According to the configurations of redundancy in this manner, since the predetermined number of redundant wordlines restricts defective wordlines yet repairable, the device shown in FIG. 1 may have a limitation to enhance the efficiency of repairing the defective wordlines (or memory cells) and to increase an extension facility of repairing. For instance, when the number of defective memory cells is greater than that of redundant wordlines in the memory bank MB 1 , it is impossible to repair the defective wordlines in excess of the capacity of the redundant wordlines therein.  
         SUMMARY  
         [0007]    Among the various inventions described in this patent document, there is described a semiconductor memory device capable of enhancing the efficiency of repairing defective memory cells. There is also described a semiconductor memory device capable of repairing defective wordlines regardless of locations of defective wordlines.  
           [0008]    There is provided a semiconductor memory device having a row repair function, including a plurality of memory blocks each having a predetermined number of redundant wordlines, a plurality of row repair fuse boxes arranged so that the same number are associated with each memory block, the number of the fuse boxes being identical to that of the redundant wordlines, and repair means to replace defective wordlines with the redundant wordlines. The redundant wordlines corresponds to the row repair fuse boxes each by each.  
           [0009]    The inventions claimed will be better understood from the following detailed description of a presently preferred exemplary embodiment, described with reference to the accompanying drawings, and the scope of which will be set forth in the appended claims. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    A more complete appreciation of the present invention, and many of the attendant advantages thereof, will become readily apparent by reviewing the following detailed description in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein:  
         [0011]    [0011]FIG. 1 is a block diagram illustrating architecture of a general 64M synchronous DRAM;  
         [0012]    [0012]FIG. 2 is a block diagram showing a disposition of row repair fuse boxes in a memory bank according to a preferred embodiment of the invention;  
         [0013]    [0013]FIGS. 3A and 3B is a schematic diagram of circuits for performing a function of a row repair in a semiconductor memory device, including row repair fuse boxes and the peripherals thereof in accordance with the preferred embodiment of the invention;  
         [0014]    [0014]FIG. 4 is a circuit diagram of the row repair fuse box shown in FIG. 3A;  
         [0015]    [0015]FIG. 5 is a circuit diagram of a fuse summation circuit shown in FIG. 3A;  
         [0016]    [0016]FIG. 6 is a circuit diagram of a block selection circuit shown in FIG. 3A;  
         [0017]    [0017]FIG. 7 is a circuit diagram of a subwordline driver enable circuit shown in FIG. 3A;  
         [0018]    [0018]FIG. 8 is a circuit diagram of a subwordline driver shown in FIG. 3B;  
         [0019]    [0019]FIG. 9 is a circuit diagram of a wordline enable signal generator shown in FIG. 3B;  
         [0020]    [0020]FIG. 10 is a circuit diagram of a redundant main wordline driver shown in FIG. 3B. 
     
    
     DETAILED DESCRIPTION  
       [0021]    It should be understood that the description of the preferred embodiment is merely illustrative and it should not be taken in a limiting sense. In the following detailed description, several specific details are set forth in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that the present invention may be practiced without these specific details.  
         [0022]    An embodiment of the invention explained hereinafter is provided to a bank among a plurality of memory banks (e.g., four banks) arranged in a semiconductor memory device. Of course the inventions are not limited to devices having four banks. This is merely an example. Each practical circuit feature in the memory bank is the same but a address coding for bank selection.  
         [0023]    [0023]FIG. 2 is a block diagram of a fuse summation circuit  200  showing a disposition of row repair fuse boxes in a memory bank according to a preferred embodiment of the invention. A memory bank (e.g., MB 1 ) is composed of eight memory blocks UB 0 ˜UB 7  each having a capacity of 2M (merely exemplary, other capacities can be used, as is true for each of the numerics in this example). Each memory block is constituted of 512 rows and 4K (K=2 10 =1024), or, in other words, 512 wordlines and 4K bitlines, and assigned to four row repair fuse boxes (e.g., RF 00 ˜RF 04  for UBO). The address for designating the eight memory blocks is composed of three address bits axB, axA, and ax 9  (three bits can select eight blocks; 2 3=8 ). The external address bit axB is the most significant bit (MSB).  
         [0024]    Each memory block has row control logic blocks, and each row control logic block includes four row repair fuse boxes as aforementioned. That is, four row repair fuse boxes are associated with each memory block. Redundant wordlines RWLs are disposed in the memory blocks UB 0 ˜UB 7  in the same number, each by four, which individually corresponds to the numerical arrangement of the row repair fuse boxes. Thus, the total number of the redundant wordlines is 32 (thirty-two) as much as the number of the row repair fuse boxes in a memory bank.  
         [0025]    As each redundant wordline RWL corresponds to each fuse box, the row repair fuse boxes RF 00 ˜RF 73  can drive the thirty-two redundant wordlines RWLs regardless of an order at a maximum of thirty-two normal wordlines that are defective in each bank. If a specific wordline is detected as being defective, the first one of the redundant wordlines located at the most right side is conductive in a repair operation.  
         [0026]    With the redundancy constitution shown in FIG. 2 that is flexible within the 16M memory bank formed of 2M memory blocks, for instance, the four redundant wordlines arranged in the memory block UBO are driven into a repair operation by means of the row repair fuse boxes RF 00 ˜RF 04 , and the other four redundant wordlines in the memory block UB 1  are driven into a repair operation by means of their corresponding fuse boxes (e.g., RF 10 ˜RF 14 ). As same as those manners, the redundant wordlines of each memory block can be taken in a repair operation till those of the eighth memory block UB 7 .  
         [0027]    [0027]FIGS. 3A and 3B is a schematic diagram of circuits for performing a function of a row repair in a semiconductor memory device, including row repair fuse boxes and the peripherals thereof in accordance with the preferred embodiment of the invention. These figures show an embodied construction of row repair circuitry embodied in a semiconductor memory device only including the thirty-two row repair fuse boxes RF 00 ˜RF 73  and the eight memory blocks UB 0 ˜UB 7  (see FIG. 3B), which belong to a memory bank (e.g., MB 0 ). It can be understood that the other construction of the row repair circuitry has the same constitution with that shown in FIGS. 3A and 3B.  
         [0028]    The row repair circuitry of a memory bank is constructed of the eight memory blocks UB 0 ˜UB 7 , block  100  of the row repair fuse boxes RF 00 ˜RF 73 , fuse summation circuit  200 , block selection circuit group  300 , subwordline driver enable circuit  400 , subwordline driver group  500 , wordline enable signal generator group  600 , and main wordline driver group  700 .  
         [0029]    The row repair fuse boxes RF 00 ˜RF 73  in the block  100  receive row addresses BAX 01 &lt;0:3&gt;, BAX 23 &lt;0:3&gt;, BAX 45 &lt;0:3&gt;, BAX 67 &lt;0:3&gt;, and BAX 8 &lt;0:1&gt;, and block addresses BAX 9 &lt;0:1&gt;and BAXAB&lt;0:3&gt;, and then generate fuse decoding signals. The row and block addresses are generated from a pre-decoder (not shown).  
         [0030]    The fuse summation circuit  200  combines the fuse decoding signals NRDb&lt;0:32&gt;with logic gates, and then generates summation signals XSUM&lt;0:7&gt;, repair information signal XSUMb. The block selection circuit group  300  includes eight block selection circuits  310   s  corresponding respectively with the eight memory blocks. The block selection circuits  310   s  receive the repair information signal XSUMb, the block selection addresses BAX 9   i  and BAXAB&lt;i&gt;, the summation signals XSUM&lt;0:7&gt;, and block selection enable signal BSENb, and then generate block selection signals BSb&lt;0:7&gt;. The subwordline driver enable circuit  400  inputs the block selection signal BSb&lt;0:7&gt;and then generates subwordline driver enable signal PXEN&lt;0:3&gt;.  
         [0031]    The subwordline driver group  500  includes sixteen subwordline drivers  510   s . The subwordline drivers  510   s  receives the subwordline driver enable signal PXEN&lt;0:3&gt;, pre-decoded row address signals BAX 01   i , the repair information signal XSUMb, and the fuse decoding signals NRDb&lt;i&gt; and NRDb&lt;j&gt;, and then generate subwordline drive signals PXb&lt;00&gt;, PXb&lt;03&gt;, PXb&lt;10&gt;PXb&lt;13&gt;, PXb&lt;20&gt;, PXb&lt;23&gt;, and PXb&lt;30&gt;, PXb&lt;33&gt;to activate their corresponding wordlines.  
         [0032]    The wordline enable signal generator group  600  includes wordline enable signal generators  610   s  which receive the block selection signals BSb&lt;0:3&gt;and the repair information signal XSUMb and then generate normal main wordline enable signals BS&lt;0:7&gt;and redundant main wordline enable signals RMWLEN&lt;0:7&gt;. The redundant main wordline drivers group  700  includes redundant main wordline drivers  710   s  which receives driver precharge signal WLC_XDEC, the summation signals XSUM&lt;0:7&gt;, and the redundant main wordline enable signals RMWLEN&lt;0:7&gt;and then generates redundant main wordline drive signals RMWLb&lt;0:7&gt;. The thirty-two redundant wordlines RWLs bdcome conductive by decoding the subwordline drive signals PXb&lt;00&gt;PXb&lt;03&gt;, PXb&lt;10&gt;, PXb&lt;13&gt;, PXb&lt;20&gt;, PXb&lt;23&gt;, and PXb&lt;30&gt;, PXb&lt;33&gt;and the redundant main wordline drive signals RMWLb&lt;0:7&gt;.  
         [0033]    All of the fuse boxes have the same constructions. FIG. 4 is a circuit diagram of the row repair fuse box shown in FIG. 3A. The row repair fuse box (e.g., any one of RF 00 ˜RF 73 ) includes fuse decoder  110  generating fuse decoding signal NRDb&lt;i&gt;(i is one of 0˜7) in response to a state at common node CN that is dependent upon parallel fusing loops responding to the pre-decoded row and block addresses, BAX 01 &lt;0:3&gt;, BAX 8 &lt;0:1&gt;, BAX 9 &lt;0:1&gt;, and BAXAB&lt;0:3&gt;. Also, the row repair fuse box includes PMOS transistor P 0  connected between power supply voltage Vcc and the common node CN, inverter  10  reversing a logic state of the common node CN, and PMOS transistor P 1  connected between the power supply voltage Vcc and the common node CN. Gates of the PMOS transistors, P 0  and P 1 , are coupled to precharge signal WLCb and output of the inverter  10 . The PMOS transistor P 1  and the inverter  10  constitutes a latch circuit to hold a current signal level of the fuse decoding signal NRDb&lt;i&gt;.  
         [0034]    The fuse decoder  110  is constructed of a plurality of fuses F 0 F 23  with their ends connected to the common node CN, and NMOS transistors N 0 ˜N 23  connected between other ends of the fuses F 0 ˜F 23  and substrate voltage Vss (or ground voltage). Gates of the NMOS transistors N 0 ˜N 15  are coupled to the row address signals BAX 01 &lt;0:3&gt;, BAX 23 &lt;0:3&gt;, BAX 45 &lt;0:3&gt;, and BAX 67 &lt;0:3&gt;, by four in this order. Gates of the NMOS transistors N 16  and N 17  are coupled to row address signals BAX 8 &lt;0:1&gt;, respectively. Gates of the NMOS transistors N 18  and Nl 9  are coupled to block address signals BAX 9 &lt;0:1&gt;, and gates of the NMOS transistors N 20 ˜N 23  are coupled to block address signals BAXAB&lt;0:3&gt;, respectively.  
         [0035]    The precharge signal WLCb is a negative logic signal that is active with a low level to charge the common node CN by turning the PMOS transistor P 0 . The fuse decoding signal NRDb&lt;i&gt; goes to a low level when a repair operation needs to be carried out, while maintains a high level (i.e., a precharge level at SNI) when there is no occurrence of repairing. The pre-decoded row address signals BAX 01 &lt;0:3&gt;, BAX 8 &lt;0:1&gt;are internal address signals made by a pre-decoder which predecodes external address signals which are supplied into the semiconductor device in response to an activation of a row address strobe signal.  
         [0036]    In an operation of the row repair fuse box shown in FIG. 4, first, the fuses F 0 ˜F 23  are cut to be adaptable to the row address for defective wordlines after a test operation that detects defective wordlines. When the precharge signal WLCb is set on a low level, the PMOS transistor P 0  is turned on and thereby the common node CN 1  is charged up to high voltage level according to the power supply voltage Vcc. The PMOS transistor P 1  and the inverter  10  hold the common node CN at the precharge voltage of a high level. In a row active state, as the precharge signal WLCb maintains a high level, the PMOS transistor P 0  is turned off. And then, the common node maintains the high level when the row address signals BAX 01 &lt;0:3&gt;, BAX 8 &lt;0:1&gt;and the block address signals BAX 9 &lt;0:1&gt;and BAXAB&lt;0:3&gt;agree to those of a defective wordline, and thereby the fuse decoding signal NRDb&lt;I&gt; is established at a high level. On the contrary, when the row and block address signals different from those of the defective wordline makes the common node CN fall down to a low level, and thereby the fuse decoding signal NRDb&lt;i&gt; is established at a high level.  
         [0037]    [0037]FIG. 5 is a circuit diagram of a fuse summation circuit shown in FIG. 3A. The fuse summation circuit  200  combines the fuse decoding signals NRDb&lt;0:32&gt;into logic loops to make the summation signals XSUM&lt;0:7&gt;and the repair information signal XSUMb. The fuse summation circuit  200  is constructed of NAND gates ND 0 ˜ND 20 , NOR gates NR 0 ˜NR 9 , inverters I 1 ˜I 8 . The NAND gates ND 0 ˜ND 15  receive the thirty-two fuse decoding signals NRDb&lt;00&gt;, NRDb&lt;07), NRDb&lt;10&gt;, NRDb&lt;17&gt;, NRDb&lt;20&gt;, NRDb&lt;27&gt;, and NRDb&lt;30&gt;, NRDb&lt;37&gt;generated from the fuse boxes RF 00 ˜RF 73 , by two. The NOR gates NR 0 ˜NR 7  receive output signals from the NAND gates ND 0 ˜ND 15  by two. The NAND gates ND 16 ˜ND 19  receive output signals from the NOR gates NR 0 ˜NR 7  by two. The NOR gates NR 8  and NR 9  receive output signals from the NAND gates ND 16 ˜ND 19  by two. The NAND gate ND 20  receives output signals from the NOR gates NR 8  and NR 9 . The inverters  11 ˜ 18  converts the output signals of the NOR gates NR 0 ˜NR 7  into the summation signals XSUM 0 ˜XSUM 7 , while the inverter  19  converts an output signal of the NAND gate ND 20  into the repair information signal XSUMb.  
         [0038]    Each summation signal (XSUM 0 -XSUM 7 ) responds to either transition of four fuse decoding signals. For example, the summation signal XSUM&lt;0&gt; is made from logic combination with the four fuse decoding signals NRDb 00 ˜NRDb 03  each generated from the four row repair fuse boxes RF 00 ˜RF 03 , and the summation signal XSUM&lt;1&gt;is made from logic combination with the four fuse decoding signals NRDb 04 ˜NRDb 07  each generated from the four row repair fuse boxes RF 20 ˜RF 23 . The repair information signal XSUMb responds to either transition of the sixteen fuse decoding signals NRDb 00 ˜NRDb 37 . The summation signals XSUM&lt;0:7&gt;and the repair information signal XSUMb are used to set the block selection signals BSb&lt;i&gt;.  
         [0039]    [0039]FIG. 6 shows a circuit construction of the block selection circuit  310  included in the group  300 . The block selection circuit( 310 ) determines whether or not it receives the block address signals BAX 9   i  and BAXABi from monitoring the summation result of the fuse decoding signals NRDb&lt;i&gt;.  
         [0040]    The block selection operation in this embodiment is to select an alternative one among the eight memory blocks belonging to a memory bank by means of the predecoded block address signals BAX 9   i  and BAXABi which are introduced in the memory device in response to the row activation where a row address strobe signal is enabled. The present embodiment employs the flexible row repair operation in which the memory block including the redundant wordlines is forced to be active whenever there is a presence of repair in the row repair fuse boxes.  
         [0041]    The block selection circuit  310  shown in FIG. 6 activates a memory block corresponding to the block address signals BAX 9   i /BAXABi by using the repair information signal XSUMb of a high level when there is no need of repairing after monitoring the summation result of the fuse decoding signal NRDb&lt;i&gt;. On the other hand, if the repair information signal XSUMb is at a low level while the summation signal XSUM&lt;i&gt;(i=one of 0˜7) corresponding thereto is at a high level when there is a repair, responding to a transition of the fuse decoding signal NRDb&lt;i&gt;, the summation signal XSUM&lt;i&gt; makes the selection circuit  310  not be influenced from the block address signals BAX 9   i /BAXABi and then activate the memory block (e.g., UBO) including the redundant wordlines.  
         [0042]    The redundant block selection circuit  310  is constructed of inverter  110  converting the block selection enable signal BSENb into its reverse signal, PMOS transistor P 2  connected between the power supply voltage terminal Vcc and node NOD 1 , NMOS transistor N 24  connected between the nodes NOD 1  and node NOD 2 , NMOS transistor N 25  with its drain connected to the node NOD 2 , NMOS transistor N 26  connected between the source of the NMOS transistor N 25  and the ground voltage terminal, NAND gate ND 21  receiving the block address signals BAX 9   i /BAXABi, inverter  111  converting an output signal of the NAND gate ND 21  into its reverse signal, NMOS transistor N 27  connected between the node NOD 2  and the ground voltage terminal, latch circuit L 1  formed of two inverters and connected between the node NOD 1  and node NOD 3 , and inverter  114  converting an output signal of the latch circuit L 1  into the block selection signal BSb&lt;i&gt;(i=one of 0˜7). The gates of the PMOS and NMOS transistors, P 2  and N 24 , are coupled to an output of the inverter  110 . The gate of the NMOS transistor N 25  is coupled to the repair information signal XSUMb, and the gate of the NMOS transistor N 26  is coupled to an output of the inverter  111 . the gate of the NMOS transistor N 27  is coupled to XSUM&lt;i&gt;. The other block selection circuits including the group  300  have the same construction as shown in FIG. 6.  
         [0043]    With respect to an operation in the block selection circuit  310 , the block selection enable signal BSENb is set up to a low level when a corresponding memory bank is activated, while being a high level to precharge the block selection signal BSb&lt;0&gt;during a precharge mode.  
         [0044]    In a normal active mode, the block selection enable signal BSENb of a low level turns the NMOS transistor N 24  on. At this time, the repair information signal XSUMb and the block address signals BAX 9   i /BAXABi go up to high levels, so that the NMOS transistors N 25  and N 26  are turned on and thereby the block selection signal BSb&lt;0&gt;falls down to a low level. While, the summation signal XSUM&lt;i&gt; is at a low level to turn the NMOS transistor N 27  off.  
         [0045]    Next, in a repair mode, the repair information signal XSUMb is set on a low level to prevent an incoming of the block address signals BAX 9   i /BAXABi, and a high-level transition of the summation signal XSUM&lt;i&gt; causes the redundant block selection signal BSb&lt;0&gt;to be set on a low level.  
         [0046]    The subwordline driver enable circuit  400  shown in FIG. 3A includes NAND gates generating subwordline driver enable signals PXENO˜PXEN 3 . The unit of the subwordline driver enable circuit( 400 ) is made of a NAND gate ND 22 , as shown in FIG. 7, which is in charge of four subwordline drivers shared by two adjacent memory blocks. Referring to FIG. 7, the NAND gate ND 22  as the subwordline selection unit receives two block selection signals BSb&lt;i&gt; and BSb&lt;j&gt;, and then generates subwordline driver enable signal PXEN&lt;i&gt;(i=one of 0˜3). The block selection address signals BSb&lt;i&gt; and BSb&lt;j&gt; are associated with different memory blocks from each other. Thus, if either BSb&lt;i&gt; or BSb&lt;j&gt; is active with a low level, the subwordline driver enable signal PXEN&lt;i&gt; goes up to a high level to turn the corresponding four subwordline drivers on.  
         [0047]    [0047]FIG. 8 shows a circuit construction of the subwordline driver  510 , which is included in the group  500 , generating subwordline drive signal PXb&lt;ij&gt; in response to the fuse decoding signals NRDb&lt;i&gt; and NRDb&lt;j&gt;. The other subwordline drivers have the same construction as shown in FIG. 8.  
         [0048]    The subwordline driver  510  is constructed of NAND gate ND 23  receiving the pre-decoded row address signal BAX 01   i  and the repair information signal XSUMb, NAND gate ND 24  receiving the fuse decoding signals NRDb&lt;i&gt; and NRDb&lt;j&gt;, inverter  115  receiving an output signal of the NAND gate ND 24 , NAND gate ND 25  receiving output signals of the NAND gate ND 23  and the inverter  115 , NAND gate ND 26  receiving an output signal of the NAND gate ND 25  and the subwordline driver selection signal PXEN&lt;i&gt;, level shifter  511  receiving an output of the NAND gate ND 26 , and inverter  117  converting an output signal of the level shifter  511  into the subwordline drive signal PXb&lt;ij&gt;. The level shifter  511  and the inverter  117  employ a high voltage (or a pumping voltage) Vpp as a power source voltage in order to enhance drivability of the wordlines. Voltage Vpp is higher than that of the power supply voltage.  
         [0049]    As the subwordline drivers are shared by the two adjacent memory blocks, two subwordline drive signals are assigned to each memory block. For instance, the memory blocks UB 0  and UB 1  are associated with the subwordline drive signals PXb 00 , PXb 01 , PXb 02 , and PXb 03 , and the memory blocks UB 6  and UB 7  are associated with the subwordline drive signals PXb 30 , PXb 31 , PXb 32 , and PXb 33 .  
         [0050]    The subwordline drive signal PXb&lt;ij&gt; is generated dependent upon the pre-decoded row address signal BAX 10   i  or the fuse decoding signals NRDb&lt;i&gt; and NRDb&lt;j&gt; in accordance with a current operation mode. For example, the subwordline drive signal PXb&lt;ij&gt; responds to the row address signal BAX 01   i  in a normal operation mode while to the fuse decoding signals NRDb&lt;i&gt; and NRDb&lt;j&gt; in a repair operation mode.  
         [0051]    In the repair operation mode, the coding mechanisms for the sixteen subwordline drive signals PX&lt;ij&gt;(PXb&lt;00&gt;, PXb&lt;33&gt;) generated from the subwordline drivers  510   s  are figured out as follows, corresponding to the row repair fuse boxes shown in FIG. 3A each by each:  
         [0052]    NRDb 00 /NRDb 04 →PXb&lt;00&gt;, NRDb 01 /NRDb 05 →PXb&lt;01&gt; 
         [0053]    NRDb 02 /NRDb 06 →PXb&lt;02&gt;, NRDb 03 /NRDb 07 →PXb&lt;03&gt; 
         [0054]    NRDb 10 /NRDb 14 →PXb&lt;10&gt;, NRDb 11 /NRDb 15 →PXb&lt;11&gt; 
         [0055]    NRDb 12 /NRDb 16 →PXb&lt;12&gt;, NRDb 13 /NRDb 17 →PXb&lt;13&gt; 
         [0056]    NRDb 20 /NRDb 24 →PXb&lt;20&gt;, NRDb 21 /NRDb 25 →PXb&lt;21&gt; 
         [0057]    NRDb 22 /NRDb 26 →PXb&lt;22&gt;, NRDb 23 /NRDb 27 →PXb&lt;23&gt; 
         [0058]    NRDb 30 /NRDb 34 →PXb&lt;30&gt;, NRDb 31 /NRDb 35 →PXb&lt;31&gt; 
         [0059]    NRDb 32 /NRDb 36 →PXb&lt;32&gt;, NRDb 33 /NRDb 37 →PXb&lt;33&gt; 
         [0060]    Each subwordline drive signal PXb&lt;ij&gt; responds to each pre-decoded row address signal BAX 01   i  in a normal operation mode. Each subwordline subword-line drive signal PXb&lt;ij&gt; responds to each pair of the coded fuse decoding signals NRDb&lt;i&gt; and NRDb&lt;j&gt; in a repair operation mode because the repair information signal XSUMb of a low level prohibits an entrance of the row address signal BAX 10   i . The subwordline driver enable signal PXEN&lt;i&gt; goes up to a high level when the block selection signal BSb&lt;i&gt; is enabled.  
         [0061]    Now, it will be explained about a more detail procedure for generating the subwordline drive signal PXb&lt;ij&gt;.  
         [0062]    First, in the normal operation mode, as the repair information signal XSUMb is at a high level, the output signal from the NAND gate ND 23  becomes a low level in response to the pre-decoded row address signal BAXO Ii. At this time, according to the fuse decoding signals NRDb&lt;i&gt; and NRDb&lt;j&gt; of high levels, the output signal of the inverter  115  is set on a high level to make a signal path through node NOD 4  be exclusively effective to the output signal of the NAND gate ND 25  that is at a high level. When the subwordline driver enable signal PXEN&lt;i&gt; maintains a high level, the NAND gate ND 26  applies a low-leveled output signal thereof to the level shifter  511  in response to the high-leveled output signal from the NAND gate ND 25  and PXEN&lt;i&gt;of a high level. The level shifter  511  pulls a voltage level up to the high voltage Vpp at output node NOD 10  in response to the output signal of a low level from the NAND gate ND 26 . Thereby, the subwordline drive signal PXb&lt;ij&gt; is established on a low level through the inverter  117 .  
         [0063]    In the repair operation mode, as the repair information signal XSUMb is at a low level to set the node NOD 4  on normally a high level, the output signal of the NAND gate ND 25  completely responds to the fuse decoding signals NRDb&lt;i&gt; and NRDb&lt;j&gt; regardless of the row address signal BAX 01   i . When one of the fuse decoding signals NRDb&lt;i&gt; and NRDb&lt;j&gt; falls down to a low level, the nodes NOD 5 , NOD 6 , and NOD 7  are at high, low, and high levels, in sequence. As a result, the high-leveled NOD 7  and PXEN&lt;i&gt; makes the node NOD 8  become a low level, and thereby, as is in the normal mode, the subwordline drive signal PXb&lt;ij&gt; is set on a low level.  
         [0064]    A plurality of the subwordline drive signals PXb&lt;ij&gt; are used to operate the thirty-two redundant wordlines together with the redundant main wordline drive signals RMWLb&lt;i&gt;.  
         [0065]    The wordline enable signal generator group  600  shown in FIG. 3B includes redundant main wordline enable signal generator  610 . Referring to FIG. 9, the redundant main wordline enable signal generator  610  is constructed of inverter  118  converting the repair information signal XSUMb into its reverse signal, NOR gate NR 10  receiving the block selection signal BSb&lt;i&gt; and the output signal of the inverter  118 , inverter  119  reversing the output signal from the inverter  118 , NOR gate NR 11  receiving the block selection signal BSb&lt;i&gt; and an output signal of the inverter  119 , serially connected inverters  120  and  121  converting an output signal of the NOR gate NR 10  into the normal main wordline enable signal BS&lt;i&gt;, and serially connected inverters I 22 ˜I 25  converting an output signal of the NOR gate NR 11  into the redundant main wordline enable signal RMWLEN&lt;i&gt;.  
         [0066]    It can be understood that the redundant main wordline enable signal RMWLEN and the normal main wordline enable signal BS&lt;i&gt; are made by responding to the repair information signal XSUMb and the block selection signal BSb&lt;i&gt; that is assigned to a memory block (one of the memory blocks UB 0 ˜UB 7 ) including the redundant wordlines RWLs. The redundant main wordline enable signals RMWLEN&lt;i&gt; and the normal main wordline enable signals BS&lt;i&gt; activate the redundant main wordline drivers and a main decoder (not shown), respectively.  
         [0067]    With respect to an operation in the redundant main wordline enable signal generator  610 , during a normal operation mode where there is no occurrence of repairing, as the block selection signal BSb&lt;i&gt; is at a low level and the repair information signal XSUMb is at a high level, the normal main wordline enable signal BS&lt;i&gt; is enabled with a high level to make the X-decoder (i.e., row decoder) be active while the redundant main wordline enable signal RMWLEN&lt;i&gt; is disabled with a low level. During a repair operation mode, the repair information signal XSUMb is set on a low level, and thereby the normal main wordline enable signal BS&lt;i&gt; is disabled off with a low level while the redundant main wordline enable signal RMWLEN&lt;i&gt; is enabled with a high level.  
         [0068]    [0068]FIG. 10 shows a circuit construction of the redundant main wordline driver  710 , which is included in the group  700 , to control the redundant wordline RWL that is enabled by decoding the redundant main wordline drive signal RMWLb&lt;i&gt; and the subwordline drive signal PXb&lt;ij&gt;. The redundant main wordline driver  710  is constructed of PMOS transistor P 5  connected between the high voltage Vpp and node XXO, NMOS transistors N 30  and N 31  which are connected between the node XXO and the ground voltage terminal in series, PMOS transistor P 6  connected between Vpp and the node XXO, inverter  126  connected between the drain and gate of the PMOS transistor P 6 , and inverter  127  converting the output signal of the inverter  126  into the redundant main wordline drive signal RMWLb&lt;i&gt;. The PMOS transistor P 6  and the inverter  126  forms latch circuit L 2  to hold a current state at the node XX 0  therein. The gate of the PMOS transistor P 5  is coupled to precharge signal WLC_XDEC. The gates of the NMOS transistors N 30  and N 31  are coupled to the summation signal XSUM&lt;i&gt;and the redundant main wordline enable signal RMWLEN&lt;i&gt;, respectively. The gate of the PMOS transistor P 6  is coupled to node XX 1  disposed between the inverters  126  and  127 .  
         [0069]    The precharge signal WLC_XDEC is provided to the driver  710  in order to charge the node XXO up to a predetermined voltage level in advance, and is also applied to a main X-decoder (not shown). When the precharge signal WLC_XDEC is at a low level, the nodes XXO is charged up to a high level and thereby the redundant main wordline drive signal RMWLb&lt;i&gt; is pre-set on a high level.  
         [0070]    During a repair operation mode, as the redundant main wordline enable signal RMWLEN&lt;i&gt; is at a high level, the NMOS transistor N 31  is turned on and thereby the redundant main wordline drive signal RMWLb&lt;i&gt; is enabled.  
         [0071]    A plurality of the redundant main wordline drive signals RMWLb&lt;i&gt; are employed to operate the thirty-two redundant wordlines RWLs which are separately arranged in the eight memory blocks by  
         [0072]    As seen through the drawings and the description aforementioned, the row repair circuitry of present invention provides advanced repair constitutions to be able to enhance efficiency of a repair operation. The memory block including the redundant wordlines is conductive whenever there is a need of repairing, regardless of a location of a memory block having a defective wordline (or a defective memory cell). Such enhancement of the repair efficiency with flexible substitution architecture makes the product yield of semiconductor memory devices be increased, and also contributes to reduce the cost per chip (or the cost per bit) and to ensure a competitive price of a semiconductor memory device in a market.  
         [0073]    Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as described in the accompanying claims