Abstract:
A delay cell comprises a fast delay stage including a differential amplifier for connection to a differential input. A slow delay stage includes a differential amplifier connected in parallel with the fast delay stage differential amplifier and having capacitance means for setting a delay amount. A current source develops a bias current. A current switch is connected between the current source and the fast delay stage and the slow delay stage to switch the bias current between the fast delay stage and the slow delay stage. An output circuit is connected to the fast and slow delay stages for developing a differential output delayed relative to the differential input responsive to a ratio between fast delay stage current and slow delay stage current.

Description:
FIELD OF THE INVENTION 
     This invention relates to a delay cell used, for example, in a ring oscillator and, more particularly, a delay cell with controlled output amplitude. 
     BACKGROUND OF THE INVENTION 
     A ring oscillator can be formed by connecting an odd number of inversions in a ring. This creates an unstable state to produce an oscillation. The oscillation frequency depends on the delay around the ring. The output can be taken at any point in the ring. A ring oscillator made of differential 2N stages, where N is greater than zero, of which only an odd number can invert, has quadrature outputs available. If only single-ended outputs are available, then 4N stages are required. Such ring oscillators are used to generate clocks for digital systems and signals for communication systems. The building block for the ring oscillator is a delay element also known as a delay cell. 
     In bipolar technology differential amplifiers have been used as the time delay element in the ring oscillator. The differential amplifiers are connected either inverting or non-inverting. The differential amplifier comprises an emitter coupled transistor pair, with the emitters connected to a current source. The bases are connected to a differential input. The collectors are connected via load resistors to a positive voltage source. The differential output is taken across the collectors via buffer transistors. The current source is varied to control the delay. As the current is increased, the speed of the stage increases, resulting in time delay decrease and a ring oscillator frequency increase. However, the output swing is defined by source current multiplied by load resistance. Because load resistance is not variable, the output level decreases with decreases in source current. This reduces the usable frequency range because the output becomes too low to drive the next stage in the ring. The low frequency usable range is also hindered because too high of a signal swing on the internal nodes comprising the collectors of the emitter-coupled pair on the load resistors can cause the transistors of the emitter-coupled pair to leave their intended linear operating region. This makes the stage both slower and its output unsymmetrical, and requires a more complex biasing scheme to control, or even a higher supply voltage. 
     Another prior design removes output level variance on frequency. A bias current is switched between two paths. The first path is a high speed path and the second path is a lower speed path comprised of two stages. The final output frequency is determined by a current switch which sets the portion of bias current flowing through the high speed paths single stage and the second stage of the slower path. Because the high speed stage and the second stage of the slower path share the load, the output is always determined by the total bias current multiplied by the load resistance. Because both are constant, the output is constant versus frequency. However, this circuit requires an additional bias current through the first stage of the slow path. Also, such delay cell is limited by a two-stage slow path. The minimum difference between the fast and slow path is limited by the maximum speed of the first stage of the slow path. 
     The present invention is directed to overcoming the problems discussed above in a novel and simple manner. 
     SUMMARY OF THE INVENTION 
     Broadly, there is disclosed herein a delay circuit with controlled output amplitude. 
     The delay circuit comprises a fast delay stage comprising a differential amplifier for connection to a differential input. A slow delay stage comprises a differential amplifier connected in parallel with the fast delay stage differential amplifier and having capacitance means for setting a delay amount. A current source develops a bias current. A current switch is connected between the current source and the fast delay stage and the slow delay stage to switch the bias current between the fast delay stage and the slow delay stage. An output circuit is connected to the fast and slow delay stages for developing a differential output delayed relative to the differential input responsive to a ratio between fast delay stage current and slow delay stage current. 
     It is a feature of the invention that each of the differential amplifiers comprises an emitter coupled transistor pair with the differential input connected across bases of the transistors of the pair. The output circuit comprises a pair of load resistors connected between a voltage source and the collectors of the transistor pairs. The capacitance means comprises first and second capacitors connected oppositely between collectors of the slow delay stage transistor pair. 
     It is another feature of the invention that the output circuit comprises a pair of load resistors connected between a voltage source and the parallel connected fast delay stage and slow delay stage. The output circuit further comprises a cascode circuit connected between the slow delay stage and the load resistors to isolate capacitance of the slow delay stage from the fast delay stage. The cascode circuit may also be connected between the fast delay stage and the load resistors. The cascode circuit comprises cascode transistors. 
     It is a further feature of the invention that the output circuit comprises a buffer circuit including first and second emitter follower transistors. 
     It is yet another feature of the invention that the current switch comprises an emitter coupled transistor pair having the emitters connected to the current source, collectors connected to the respective fast and slow delay stages, and bases connected to a differential control input. 
     There is disclosed in accordance with another aspect of the invention a ring oscillator comprising a plurality of delay cells which control output amplitude. Each delay cell comprises a fast delay stage including a differential amplifier for connection to a differential input, and a slow delay stage including a differential amplifier connected in parallel with the fast delay stage differential amplifier and having capacitance means for setting a delay amount. A current source develops a bias current. A current switch is connected between the current source and the fast delay stage and the slow delay stage to switch the bias current between the fast delay stage and the slow delay stage, and an output circuit is connected to the fast and slow delay stages for developing a differential output delay relative to the differential input responsive to a ratio between fast delay stage current and slow delay stage current. Means are provided for connecting the plurality of delay cells to provide a ring, the connecting means connecting differential inputs of each delay cell to the differential output of another delay cell, wherein an odd number of said connections are inverted connections. Control means are connected to the current switch of each delay cell to control cell delay and thus oscillator frequency. 
     It is a feature of the invention that the oscillator generates quadrature outputs. 
     In accordance with the invention, the delay cell, when switched for fast operation, uses all of the bias current for the fast stage. Thus, the overall current consumption is lower for the same performance level as with prior delay cells. Also, the delay cell is limited to second-order effects of transistor device speed for higher average bias currents, and the speed of the slow stage can approach the speed of the fast stage. 
     Further features and advantages of the invention will be readily apparent from the specification and from the drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is an electrical schematic of a circuit used in a delay cell according to the invention; 
     FIG. 2 is a block diagram illustrating a ring oscillator using the delay cell of FIG. 1; and 
     FIGS. 3 and 4 are curves illustrating operation of the delay cell of FIG. 1 compared to prior art delay cells. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 1, an electrical schematic illustrates a circuit for a delay cell or delay element  10  in accordance with the invention. The delay cell  10  includes a fast delay stage  12  connected in parallel with a slow delay stage  14 . A current source  16  develops a bias current. A current switch  18  is connected between the current source  16  and the fast delay stage  12  and slow delay stage  14  to switch the bias current between the fast delay stage  12  and the slow delay stage  14 . An output circuit  20  is connected to the fast delay stage  12  and the slow delay stage  14 . 
     The fast delay stage  12  comprises a differential amplifier  22  connected to a differential input labeled Pin+ and Pin−. The differential amplifier  22  comprises an emitter coupled transistor pair including transistors Q 1  and Q 2 , with the differential input connected across the bases of the transistor pair. Particularly, the Pin+ input is connected to the base of the transistor Q 1  and the Pin−input is connected to the base of the transistor Q 2 . 
     The slow delay stage  14  comprises a differential amplifier  24  connected to the differential inputs Pin+ and Pin−. The differential amplifier  24  comprises an emitter coupled transistor pair including transistors Q 3  and Q 4 , with the differential input connected across the bases of the transistor pair. Particularly, the Pin+input is connected to the base of the transistor Q 4  and the Pin−input is connected to the base of the transistor Q 3 . 
     The fast delay stage  12  is constructed as a simple differential amplifier. The slow delay stage  14  has capacitance to set the delay. Particularly, a pair of capacitors C 1  and C 2  are connected oppositely across the collectors of the differential pair transistors Q 3  and Q 4 . The capacitors C 1  and C 2  create an RC delay in circuit operation. The circuit can also exhibit parasitic capacitance, represented by PC 1  and PC 2 . By connecting the capacitors C 1  and C 2  in opposite directions, the parasitic capacitance is balanced. While the illustrated circuit uses a pair of capacitors, only a single capacitor is necessary. 
     The current switch  18  comprises an emitter coupled transistor pair including transistors Q 5  and Q 6 . The collector of the transistor Q 5  is connected to the emitters of the transistors Q 1  and Q 2 . The collector of the transistor Q 6  is connected to the emitters of the transistors Q 3  and Q 4 . The transistor pair  26  is controlled by a differential control voltage applied to the bases of the transistors Q 5  and Q 6 . Particularly, Vctrl+ is applied to the base of the transistor Q 5  and Vctrl− is applied to the base of the transistor Q 6 . 
     The current source  16  is illustrated in the form of a bias current I 1  connected between the emitter of the transistors Q 5  and Q 6  and ground. The current source  16  may utilize a current mirror responsive to a bias current input. 
     The output circuit  20  includes a cascode circuit  28 . The cascode circuit  28  includes cascode transistors Q 7 , Q 8 , Q 9  and Q 10  having their emitters connected to the collectors of respective transistors Q 1 , Q 2 , Q 3  and Q 4 . The bases of the cascode transistors Q 7 -Q 10  are connected to a voltage source labeled VCC. As is apparent, the voltage source can be any suitable bias voltage, not necessarily VCC. The output circuit  20  also includes load resistors R 1  and R 2 . The resistor R 1  is connected between VCC and the collectors of the cascode transistors Q 8  and Q 9 . The second load resistor R 2  is connected between VCC and the collectors of cascode transistors Q 7  and Q 10 . 
     The collectors of the transistors Q 2  and Q 3 , via the respective cascode transistors Q 8  and Q 9 , drive the base of an output buffer transistor Q 11 . Likewise, the collectors of the transistors Q 1  and Q 4 , via the cascode transistors Q 7  and Q 10 , drive the base of a second output buffer transistor Q 12 . The collectors of the transistors Q 11  and Q 12  are connected to VCC. The emitters of the buffer transistors Q 11  and Q 12  are connected to current sources  12  and  13 . The current sources  12  and  13  may represent current mirror circuits that control a bias current input. A differential output is taken from the emitters of the transistors Q 11  and Q 12  and represented by Pout− and Pout+. 
     In operation, the delay cell  10  splits a constant bias current from the current source  16  through the fast delay stage  12  and the slow delay stage  14 . As the ratio I FAST /I SLOW  increases, the delay cell speed increases. As discussed above, the delay is provided by the capacitors C 1  and C 2 . The slow delay stage  14  is connected to the load resistors R 1  and R 2  via the cascode circuit  28 . The cascode circuit  28  isolates the added capacitance in the slow delay stage  14  from the output of the fast delay stage  12 , since the capacitance at the differential paired collectors, as well as the tail current, determines the speed. The cascode transistors Q 7  and Q 8  are optional between the fast delay stage  12  and the load resistors R 1  and R 2 . The cascode devices Q 7  and Q 8  may be utilized to keep the circuit collector-emitter voltages of the speed determining differential pairs similar such that only additional capacitance, not Early voltage effects, determines the performance difference between the stages. Thus, all bias current is directed through the load, and the output level does not depend on delay. The differential output at the load resistors R 1  and R 2  may be buffered, as shown using the transistors Q 11  and Q 12 , to maintain low minimum delay times. 
     The delay implemented by the delay cell  10  is controlled by the differential voltage Vctrl+ and Vctrl−, which controls the differential pair  26  to switch the bias current between the fast delay stage  12  and the slow delay stage  14 . 
     The delay cell  10  in accordance with the invention, when switched for fast operation, uses all of the bias current for the fast delay stage  12 . Thus, the overall current consumption is lower for the same performance level in the same technology as prior delay cell designs. Also, the difference between the fast and slow paths in the delay cell  10  is limited to second-order effects of transistor device speed for higher average bias current. Also, the speed of the slow delay stage  14  can approach the speed of the fast delay stage  12 . 
     Referring to FIG. 2, a block diagram illustrates a ring oscillator  30  using delay cells  10 - 1  and  10 - 2 . Each of the delay cells  10 - 1  and  10 - 2  utilizes the circuit of the delay cell  10  of FIG.  1 . Because of the differential nature, an odd number of inversions can be obtained using an even number of cells. Particularly, Pout+ and Pout− of the first delay cell  10 - 1  are connected to the respective Pin+ and Pin− of the second delay cell  10 - 2  to provide the inversion. Pout+ and Pout− of the second delay cell  10 - 2  are connected to Pin− and Pin+, respectively, of the first delay cell  10 - 1 . As is apparent, any number of delay cells can be used, provided an odd number of inversions is utilized. The ring oscillator  30  of FIG. 2 satisfies feedback requirements for a ring oscillator, while allowing quadrature outputs to be generated as illustrated by various outputs labeled OUT  0 , OUT  90 , OUT  180  and OUT  270 . Frequency of the ring oscillator  30  is controlled by a delay control circuit  32 , which controls the differential voltage Vctrl+ and Vctrl− to each of the delay cells  10 - 1  and  10 - 2 . The delay cells also illustrate inputs for VCC and ground, as well as biasN and biasEF. The biasN input is utilized for the current source  16 . The biasEF input is used for the bias current for the emitter follower buffer transistors Q 11  and Q 12 . 
     FIG. 3 illustrates curves comparing output amplitude versus control voltage of a ring oscillator using the delay cell  10  of the present invention compared to the results obtained using a prior art delay element in the form of a differential amplifier with a varying bias current as the delay element. The curves show that the output voltage variation over 2.3 octaves for 400 microamp bias current and 150 millivolt control voltage swing changes by only a few dB. The prior delay cell obtains only 1.8 octaves tuning range with 25 dB output voltage variation over the range. Such variation would require additional automatic level control circuitry at added device counts and power consumption. Also, the variation leads to poor yield in noise performance at the low frequency end. 
     FIG. 4 illustrates comparison curves for frequency versus control voltage. Of note is that the shape of the frequency output versus control voltage exhibits an approximately linear region when using the disclosed delay element. The constant control voltage gain factor eases control voltage design. 
     In accordance with the invention, the output stage buffers can be any type of buffer, optimally providing a high impedance at the input and a low impedance at the output. They can be emitter followers, as shown, as well as source followers, using FETs instead of bipolar devices, or even operational amplifiers. Likewise, the NPN-based buffers could be replaced with PNP-based buffers with no theoretical loss of performance. 
     Moreover, the delay cell  10  is illustrated using an NPN configuration for the transistors. As is apparent to one skilled in the art, the delay cell circuit has an equivalent PNP configuration as well as both NMOS and PMOS configurations. With the PNP or PMOS configurations, a negative voltage supply is used, as is known. 
     Thus, in accordance with the invention there is illustrated a delay with controlled output amplitude using a single bias current for fast and slow delay stages.