Abstract:
A circuit for generating a pair of quadrature output signals from a pair of quadrature input signals in which the frequency of the output signals is double that of the input. The circuit consists of two dual phase shifters, two symmetrical multipliers and a phase controller. The circuit is fabricated by conventional integrated circuit processing technology. A method of generating frequency doubled quadrature output signals is disclosed.

Description:
FIELD OF THE INVENTION 
     This invention relates to a circuit for processing quadrature signals and more particularly to a circuit, preferrably an integrated circuit capable of processing a pair of quadrature input signals so as to generate a pair of quadrature output signals having a frequency that is double the frequency of the input signals. 
     BACKGROUND OF THE INVENTION 
     Quadrature signals, i.e. signals having the same frequency but a phase difference of 90° (π/2), are used with many circuits and find particular application in circuits for fibre optic transmission systems and wireless communications. One important property of quadrature signals is that they can be multiplied to generate signals having a frequency that is double the frequency of the original signals. If the two quadrature signals are: 
     
         a=A sin (wt+φ) 
    
     and 
     
         b=A cos (wt+φ) 
    
     then by multiplying the two signals the result can be written: ##EQU1## where k is the multiplier gain. 
     The quadrature signals frequency doubler circuit of the present invention generates two quadrature output signals having a frequency equal to double the frequency of the two quadrature input signals utilizing conventional integrated circuit fabrication technology. 
     PRIOR ART 
     As discussed previously it is a property of quadrature signals that they can be multiplied to generate quadrature signals having double the frequency of the input signals. In U.S. Pat. No. 3,626,308, which issued Dec. 7, 1971 to T. O. Paine et al, a wide-band signal quadrature and second harmonic generator is disclosed. A voltage-controlled phase shifter is used to generate an output representing a phase shifted sine input signal. A photoresistor is used to control the output signal. The frequency range of this circuit is limited to the range 100 Hz to 100 kHz and includes components not compatible with integrated circuit fabrication. U.S. Pat. No. 3,676,660, which issued Jul. 11, 1972 to L. R. Miller, relates to an analog computer and a circuit that generates quadrature gating signals at both a first frequency and a second frequency equal to twice the first frequency. The circuit requires frequency doubler stages, amplifiers and filters, i.e. the circuit is very complex and not applicable to I.C. fabrication. 
     In the present invention a pair of dual phase shifters is used to generate the phase difference between signals. The use of phase shifters in related technology is known. For example, P. A. Dawson and S. P. Rogerson in the IEEE Journal of Lightwave Technology, Vol. LT-2, No. 6, pp. 926-932, December 1984, describe a phase shifter circuit consisting of two differential stages with connected outputs. The input of the second stage is delayed by φ max  which delay is generated by an off-chip, fixed delay line and accordingly a continuously variable frequency of operation can not be achieved. H. M. Rein et al at the IEEE International Solid-State Circuits Conference 1989 describe in a paper entitled &#34;A 3Gb/s Bipolar Phase Shifter and AGC Amplifier&#34;, a digital version of the circuit disclosed by Dawson at al. This circuit according to Rein et al utilizes a static master/slave flip-flop version of a frequency divider for the generation of a phase difference. The signal is halved prior to phase shifting followed by a doubling stage to get the original frequency. A wide-band low-pass filter is used to obtain continuous output signals from the phase-shifting stage. This filtering stage restricts the operable frequency range. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a circuit which is capable of generating, from a pair of quadrature input signals of a first frequency, a pair of quadrature output signals of a second frequency which preferrably is double the first frequency. 
     It is a further object of the invention to provide a circuit which can operate at any frequency from DC to the maximum operating frequency allowed by the technology used for implementation. 
     It is yet a further object of the invention to provide n circuits which can be cascaded for a multiplication factor of 2 n . 
     Therefore in accordance with a first aspect of the present invention there is provided a circuit adapted to receive a pair of quadrature input signals of a first frequency and to generate a pair of quadrature output signals of a second frequency, the second frequency being greater than the first. The circuit comprises a pair of dual phase shifters each having input means to independently receive the pair of input signals and to genereate a pair of output signals having a phase difference therebetween. Control means is connected to each of said pair of dual phase shifters, the control means having phase adjusting means to control the phase difference between the pair of output signals. A pair of symmetrical multipliers are provided, each of the pair receive the pair of output signals from the phase shifters and generate a pair of quadrature output signals having a second frequency which according to a preferred embodiment is double the frequency of the input signals. A biasing sub-circuit is provided which supplies operating voltage to each element of the main circuit. 
     According to a second aspect of the invention there is provided a method of generating a pair of quadrature output signals from a pair of quadrature input signals the output signals having a frequency which is double the frequency of the input signals. The method includes the steps of supplying the pair of quadrature input signals to a pair of dual phase shifters, each of the phase shifters having means to generate a pair of phase shifted output signals. A differential phase control signal is generated in a phase controller and this signal is supplied to each of the dual phase shifters to control the phase between the phase shifted output signals. The phase shifted output signals are supplied to a pair of symmetrical multipliers which generate the pair of quadrature output signals having a frequency which is double the frequency of the quadrature input signals. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of the frequency doubler circuit of the present invention; 
     FIG. 2 is a schematic diagram of one of the dual phase shifters; 
     FIG. 3 is a schematic diagram of the dual phase shifter controller and; 
     FIG. 4 illustrates the phase relationship between the quadrature input and output signals. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     For identification purposes the quadrature input signals will be identified as (hck,hckb) and (hckq,hckqb). The quadrature output signals are identified as (ck,ckb) and (ckq,ckqb). The phase difference between hck and hckq and between ck and ckq is 90°. All input and output signals are of differential type. 
     As shown in FIG. 1 each of the pair of quadrature input signals (hck,hckb) and (hckq,hckqb) is coupled to a pair of dual phase shifters 20, 22. Respective outputs of each of the pair of dual phase shifters are coupled to each of a pair of symmetrical multipliers 24, 26. Dual phase shifter controller 28 under control of bias voltage supplied by a power supply 29 provides phase control to each of the phase shifters 20, 22. Quadrature output signals (ck,ckb) and (ckq,ckqb) as shown in FIG. 1 are generated by multipliers 24, 26. 
     The dual phase shifter as seen in FIG. 2 comprises two multipliers each having their outputs connected as two summing amplifiers. As shown in FIG. 1 the quadrature input signals are supplied to input terminals of the phase shifters as follows: 
     
         ______________________________________input       phase shifter 20                   phase shifter 22______________________________________hck         i           iqbhckb        ib          iqhckq        i           iqhckqb       iqb         ib______________________________________ 
    
     The outputs from each dual phase shifter are identified as (y,yb) and (yd,ydb). 
     It is to be noted that the input signals are of differential type for generality. If desired they can be single ended in which case ib and iqb will be substituted with reference voltages Vref and Vrefq respectively. 
     The manner in which these signal are processed in each dual phase shifter will be described with reference to FIG. 2. As shown differential input signals (i,ib) are supplied to the bases 44, 46 of transistors 40 and 42 respectively. Differential input signals (iq,iqb) are supplied to the base 54, 56 of transistors 50, 52 respectively. Current sources 48, 58 comprising transistor 47 and resistor and transistor 57, resistor 59, respectively controlled by bias voltage (bv) supply current to respective transistors 40, 42 and 50, 52 via degeneration resistors 43, 45 and 53, 55 respectively. 
     The two current sources are shown for generality. They can be replaced with resistors if desired. 
     Emitter coupled second level transistors 60 and 70 are connected to the collector 61 of transistor 40. Transistors and 90, also emitter coupled, are connected to collector 81 of transistor 42. Similarly transistors 100 and 110 are connected to transistor 50 while transistors 120 and 130 are connected to transistor 52. Second level transistors 60, 70, 80, 90, 100, 110, 120 and 130 are controlled by differential inputs (m,mb) supplied by dual phase shifter controller 28 (FIGS. 1 and 3). 
     The operation of the dual phase shifter can be described as follows: 
     differential input signal (i,ib) is defined as Asin(wt) and; 
     (iq,iqb) as Acos(wt) where; 
     (i,ib) and (iq,iqb) are the quadrature input signals and 
     A is the voltage amplitude of the input signals. 
     Then: ##EQU2## where: I 42  =the collector current for transistor 42 
     I 0  =the current supplied by the current source 48 as controlled by DC bias voltage (bv). The total current supplied is 2I 0  ; 
     R e  =sum of resistors 43 and 45 
     also: ##EQU3## I 44  is the collector current for transistor 44. Other values as set out above. ##EQU4## where I 52  =collector current for transistor 52, I 50  =collector current for transistor 50, 
     I 0  =current supplied by current source 58 (total current is 2I 0 ) and; 
     R e  =sum of resistors 53 and 55. 
     The aforementioned collector currents are multiplied by m and (1-m) respectively, where m≦1, by the upper transistor pairs (60, 70), (80, 90), (100, 110) and (120, 130) under the DC voltage control (m,mb) as previously discussed and supplied by dual phase shifter controller 28. These multiplier circuits provide outputs (y,yb) and (yd,ydb) via summing amplifiers comprising transistors 160, 162, 164 and 166 as well as resistors 170, 172, 174 and 176. The summing amplifiers are shown for generality only. 
     The complementary output signals of each phase shifter (y,yb) and (yd,ydb) can be approximated as: ##EQU5## where: R c  =load resistors (150, 152,, 154 and 156). 
     The phase change introduced by the propagation time through the phase shifter has been neglected in as much as only the relative phase of the four output signals is of interest and not the absolute value of the phases. 
     The two output signals can be rewritten as: 
     
         (y,yb)=A.sub.1 sin (wt+φ.sub.1)and; 
    
     
         (yd,ydb)=A.sub.1 sin (wt+φ.sub.2) 
    
     where: ##EQU6## 
     The amplitude of the two output signals are the same, and the relative phases are φ 1  and φ 2 . It is possible to make φ 1  =π/8 and: 
     φ 2  =3π/8 by choosing an appropriate value of m. 
     The value of m is controlled by the phase shifter controller best seen in FIG. 3. The complementary outputs m and mb are controlled by choosing the appropriate ratio between resistor 140 and the sum of resistors 142 and 144. This ratio can be chosen depending on the relative phase difference desired. Control circuit 28 also includes current sources comprising transistor 141, resistor 143 and transistor 145, resistor 147. Transistors 146 and 148 provide outputs mb and m respectively. 
     From this analysis it is apparent that by utilizing the circuit configuration shown in FIG. 1 it is possible to generate from two differential input signals having a relative phase of π/2, four output signals having relative phases of 0, π/4, π/2, 3π/4. 
     FIG. 4 is an illustration of the input signals and their relative phases (hck, hckb and hckq, hckqb) and the dual phase shifter outputs and their relative phases. In FIG. 4 the output signals of the two phase shifters 20 and 22 (ps1 and ps2) are identified as follows: 
     ps1 outputs y,yb and yd,ydb are ps1.y, ps1.yb, ps1.yd and ps1.ydb 
     ps2 outputs y,yb and yd,ydb are ps2.y, ps2.yb, ps2.yd and ps2.ydb 
     The output set of the four signals as shown in FIG. 4 can be seen as a pair of quadrature signals having a relative phase of π/4: 
     (ps1.y, ps1.yb) and (ps2.y, ps2.yb) 
     (ps1.yd, ps1.ydb) and (ps2.yd, ps2.ydb) 
     By multiplying the quadrature signals employing the circuit of FIG. 1, a pair of output signals having a frequency equal to double of the input signals can be generated. The relative phase of the output signals is π/2. 
     The multipliers are well known in the prior art and will not be described in detail here. It is important, however that multipliers be symmetrical in order not to introduce phase errors. 
     As indicated previously the circuit can operate at any frequency from DC to the maximum frequency allowed by the technology used for implementation. An exclusive-or type circuit can be used if a digital output signal is desired. 
     Another feature of the invention is that the basic circuit as illustated in FIG. 1 may be cascaded to double the frequncy of the quadrature output signals. In the cascade configuration the output shown as (ck,ckb) and (ckq,ckqb) are supplied to a second similar circuit as inputs (hck 1 ,hckb 1 ) and (hckq 1 ,hckqb 1 ). Thus the multiplication factor for a circuit having n stages is 2 n . 
     While a specific embodiment of the invention has been disclosed it will be apparent to one skilled in the art that variations and alternatives to this embodiment can be implemented. It is to be understood, however, that such variations and alternatives will fall within the scope of the invention as defined in the appended claims.