Abstract:
A method and apparatus for converting an input step waveform signal into a smooth output waveform signal is comprised of two sample-and-hold circuits (11, 12), one for sampling each step of the input signal and the other for synchronously sampling and holding the output waveform, a circuit (17-20) for providing a signal proportonal to the difference between the samples held in the sample-and-hold circuits, and means (21-23) for integrating the difference. The output of the integrator is connected to the second sample-and-hold circuit while the step waveform to be filtered is connected to the input of the first sample-and-hold circuit. The integrator thus produces an output that is a linear signal during each clock pulse period with a slope equal the sign and amplitude of each step.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a method and apparatus for filtering step waveforms, and more particularly to a circuit for filtering a step waveform of the type which changes value in synchronism with a clock pulse, such as the step waveform output of a digital-to-analog converter. 
     In most systems which utilize a step waveform, it is necessary, or at least desirable, to filter the step waveform in order to provide a smooth analog signal. Typical examples are waveform simulators of digital-to-analog converters for servo control systems. The filter commonly used is a simple low-pass filter. The trouble with such a simple solution to the problem of smoothing a step waveform is that the low-pass filter tends to introduce high frequency harmonic distortions and undesired phase shifts in the resulting analog signal. What is desired is a filter that is more predictable and more precise for smoothing the output of waveform simulators, digital-to-analog converters, sample-and-hold circuits, CCD (charge coupled device) analog delay lines, and the like. 
     The application of the present invention to the problem of filtering the output of digital-to-analog converters per se is particularly significant. During the course of the last few years, the importance of analog-to-digital and digital-to-analog converters has increased together with the proliferation of microprocessors and small computers. The reason is that they are necessary interfacing blocks between the chiefly analog nature of the world and the realm of the digital processing that takes place in the microprocessors and small computers. 
     The digital-to-analog converters can be broadly classified into two main categories, depending on their application. One class of such converters are for use as precision reference sources where their outputs do not change rapidly with time. The other class is for converters used as reproducers of analog waveforms by successions of step functions with considerably higher harmonics in their frequency content. The usual practice is, as noted above, to smooth the outputs through a low-pass filter. However, the resulting waveforms depend on the nature of the low-pass filter, on the rate of change in one clock period which can cause distortions, such as amplitude attenuations and phase shifts, as noted hereinbefore. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, a waveform is provided for converting the voltage of each of the steps of a step waveform into a linear segment that has a slope equal to the change in voltage over the next step period, such as in smoothing a step waveform at the output of an analog-to-digital converter. The apparatus for carrying out the process is comprised of first and second sample-and-hold circuits synchronously operated in response to clock pulses. The output of the second sample-and-hold circuit is combined with the output of the first by means for producing a signal equal to the difference between the voltage signals sampled and held by the two circuits. The difference is integrated from one clock pulse to the next in an integrator circuit. The integrator output, which constitutes the filter output, is connected to the input of the second sample-and-hold circuit. In that manner, the integrator circuit will integrate the difference between two adjacent steps and thus provide as an output a linear segment during each clock pulse period with a slope equal to the sign and amplitude of each step of the step waveform, thereby smoothing the step waveform into a more ideal analog waveform with only one to two sampling periods delay. 
     The novel features that are considered characteristic of this invention are set forth with particularity in the appended claims. The invention will best be understood from the following description when read in connection with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of an exemplary embodiment of the invention. 
     FIG. 2 illustrates a sampling command signal for the circuit of FIG. 1. 
     FIG. 3 illustrates a typical step waveform to be smoothed by the circuit of FIG. 1 and the smoothed output. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     Referring now to FIG. 1 of the drawings, a filter for a step waveform is comprised of two sample-and-hold circuits 11 and 12. While such circuits may be implemented from an analog switch, a holding capacitor, and an operational amplifier, the successful practice of the invention requires a high quality circuit in which the holding capacitor charges to its final value and settles quickly, with near zero leakage current at the capacitor. The problems of circuit design are mostly with the analog switches, which must have very low coupling between the digital input and analog output. Other problems are with the operational amplifier which must have extremely low bias current, low offset drift and sufficient slew rate. A monolithic integrated circuit having an electronic analog switch isolated from the input and the output by operational amplifiers is therefore preferred. Such a monolithic circuit is commercially available from the Semiconductor Products Division of Harris Corporation (model HA-2420/2425 monolithic sample-and-hold/gated operational amplifier). The following description of the circuit 11, used as a unity gain, noninverting sample-and-hold circuit, will apply to that monolithic circuit. The circuit 12 is identical, but used as a unity gain, inverting sample-and-hold circuit. Other monolithic circuits having the same characteristics could, of course, be used. 
     An input amplifier 13 is a high performance operational amplifier with excellent slew rate, and the ability to drive a holding capacitor 14 through a series switch 15 without instability. The switch is a highly efficient bipolar transistor with extremely low leakage in the off condition. An output buffer amplifier 16 is a unity gain follower with a high impedance (MOSFET) input stage to operate with extremely low current. Any offset voltage drift of the MOSFET input stage is corrected by negative feedback from the output of the amplifier 16 to the input of the amplifier 13. While the switch 15 is turned on, the circuit functions as a conventional operational amplifier able to drive capacitive loads, and while the switch 15 is turned off, the node between the switch 15 and amplifier 13 is an almost perfect open circuit and the voltage stored in the capacitor 14 will be presented at the output of the buffer amplifier 16. The step waveform signal, V i  (t), is applied as an input at the positive input terminal of the operational amplifier 13, and is reproduced at the output terminal of the buffer amplifier 16 at every clock pulse. 
     An operational amplifier 17 is connected as a voltage adding circuit to the output of the sample-and-hold circuit 11 by a summing resistor 18. Current in a feedback resistor 19 is the algegraic sum of the current due to the voltage V 1  at the output of the sample-and-hold circuit 11 and the current due to the voltage V 2  at the output of the circuit 12 coupled to the summing junction by a resistor 20. The output voltage V 3  of the adding circuit is equal to the algebraic sum of the input voltages, times a scaling factor equal to the ratio of the feedback resistor 19 to the input resistors 18 and 20, such as 1.0 in the example illustrated. 
     The output voltage V 3  is coupled by a resistor 21 to an integrator comprised of an operational amplifier 22 and a feedback capacitor 23. The output of the integrator provides an output signal V o  (t) which is a linear voltage signal during each sample period with a slope equal to the difference in voltage between adjacent samples, as will be better appreciated from the following description of the filter operation with reference to FIGS. 2 and 3. But first it should be noted that the output signal V o  (t) is coupled to the sample-and-hold circuit 12 by a resistor 24 which, as noted hereinbefore is like the circuit 11 but connected as an inverting sample-and-hold circuit by a feedback resistor 25 to the negative input of an operational amplifier 26 to which the output signal V o  (t) is coupled. An electronic switch 27 is operated by the same clock pulses applied to the sampling switch 15 of the circuit 11. A noninverting buffer amplifier 28 thus provides the output voltage V 2  which is the sample of the output signal V o  (t), but inverted. This sample of the output is taken at the instant a new sample of the input voltage is taken, so at all times the output signal V o  (t) is the integrated difference between a new sample V 1  and the sample V 2  of the integrated output. 
     It should be recognized that connecting the circuit 12 as an inverting sample-and-hold circuit permits forming the difference V 1  -V 2  by adding the voltages +V 1  and -V 2 . It would be possible to connect the circuit 12 as a noninverting sample-and-hold circuit, and to form the difference by subtracting the voltage +V 2  from the voltage V 1  using a differential operational amplifier, but the arrangement shown is preferred because it is independent of the input common mode characteristics of the operational amplifier 17. 
     Operation of the integration filter shown in FIG. 1 will now be described with reference to FIGS. 2 and 3. In the following discussion, let all the continuous time variable parameters be designated by subscripts (t) and the DC components (within one clock period) by (tn) where n is any integer. C(t) is the sampling command (clock pulse) signal shown in FIG. 2. τ is the clock pulse period. The sampling time, t s , is very narrow compared to the holding time t h . 
     Given the time variable input voltage V i  (t), the sample-and-hold circuit 11 will store this voltage at the instant t 1 . 
     
         V.sub.1 =V.sub.i (t.sub.1)                                 (1) 
    
     At the same instant, the sample-and-hold circuit 12 will store the inverted output voltage -V o  (t i ). 
     
         V.sub.2 =-V.sub.o (t.sub.1)                                (2) 
    
     The summing amplifier 17 performs the algebraic addition of these two voltages, and inverts the sum. 
     
         V.sub.3 =-(V.sub.1 +V.sub.2)=-V.sub.i (t.sub.1)+V.sub.o (t.sub.1) (3) 
    
     The voltage V 3 , on its turn, is the input (multiplier) to the integrator 22. ##EQU1## Where RC is the integrating time constant equal to the product of the resistance and capacitance of resistor 21 and capacitor 23. ##EQU2## where V o  (t 1 ) is the output of the integrator at the instant t 1 . 
     The RC time constant of the integrator is chosen to be equal to the period τ. Therefore, at the end of one period that is at the instant t 1  +τ, the integrator will slew exactly the voltage V 3 . ##EQU3## 
     Substituting equation 3 into equation 5, 
     
         V.sub.o (t.sub.1 +τ)=+V.sub.i (t.sub.1)-V.sub.o (t.sub.1)+V.sub.o (t.sub.1)                                                 (6) 
    
     which is the same as: 
     
         V.sub.o (t.sub.1)=V.sub.i (t.sub.1 -τ)                 (7) 
    
     Equation 7 shows that at the end of one clock period, the integrator would have reached the input voltage of the previous period in the step waveform shown in FIG. 3. 
     The integration filter yields a very predictable and elegant solution to filtering any realizable step waveform. Note that the output V o  (t) follows the input V i  (t) with only predictable phase delay, which corresponds to when the clock command is applied, and no amplitude distortion from sample to sample. The feedback through the circuit 12 and resistor 20 will guarantee convergent accuracies for precision applications. That feedback tends to cancel all initial errors and subsequent drifts in the circuit. 
     The acquisition time of the sample-and-hold circuit 12 must be small compared to the clock period, τ. For first approximation, it could be made 0.001 of τ if 0.1% accuracies are to be expected for waveforms of maximum transition in one clock period. For precision, the circuit 12 may include two analog switches, with one of them used to balance out the MOSFET charge injection errors of the buffer amplifier 28 during the switching. For acquisition times below one microsecond, an ultra fast diode bridge sample-and-hold circuit might be used instead of the circuit 12 shown. 
     It should now be apparent that the present invention provides a smoothing filter for step waveform without distortion and the maximum of only two clock periods delay between the input V i  (t) and the output V o  (t). The only critical components are the resistor 21 and capacitor 23. The capacitor has to have a low dielectric absorption constant and high stability over temperature and time, such as a teflon capacitor. The time constant of those integrating components should not deviate from τ since any deviation will cause instabilities similar to normal feedback circuits. Other component deviations will cause only gain or offset changes from the desired design values. For instance, if the resistor 19 is selected to be 5K, while the resistors 18 and 20 are selected to be 10K, the voltage adding circuit will have a gain of 0.5 instead of 1.0. In some cases it may be desirable to have a gain of only 0.5 for the amplifier 17 if the sum V 1  +V 2  could be expected to saturate the amplifier 17. The loss in signal amplitude is then restored by increasing the gain of the integrator by providing an RC time constant equal to τ/2. The purpose for this is to optimize the dynamic range of the filter. Any deviation will simply change that gain factor, which will only change the gain between the input and the output. For unity gain in the inverting sample-and-hold circuit 12, the resistors 24 and 25 must be equal, such as 10K. The values of capacitance for the capacitors 14 and 29 of the sample-and-hold circuits 11 and 12 are not critical. It is only important that the capacitors be chosen to have a low dielectric constant, as noted above. The larger the values, the longer the holding period, t h , of the capacitors without excessive drift, but they must be kept small enough to be charged during the sampling periods, t s . The capacitance value must therefore be selected for the holding and sampling periods t h  and t s  of each application. Assuming t h  =1 ms, and t s  =6 μs, an optimum value for the capacitance of these holding capacitors is 1000 pF. For the component values chosen in the example of gain of operational amplifier 17 equal 0.5, RC=τ/2=500 μs. If C=10,000 pF, then R=50 kohms. 
     Althugh particular embodiments of the invention have been described and illustrated herein, it is recognized that modifications and variations may readily occur to those skilled in the art. Consequently, it is intended that the claims be interpreted to cover such modifications and equivalents.