Abstract:
A circuit that provides samples of in-phase and quadrature components of an input waveform includes an oversampling ADC that receives the input waveform and converts the input waveform to digital samples at an oversampling rate. A first digital filter, coupled to the ADC, receives the digital samples from the ADC and provides the in-phase component samples of the input waveform. A second digital filter, coupled to the ADC, receives the digital samples from the ADC and provides the quadrature component samples of the input waveform.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to an in-phase and quadrature sampling circuit and, more particularly, to an in-phase and quadrature sampling circuit including a unique digital filter. 
     BACKGROUND OF THE INVENTION 
     It is advantageous in radio, sonar and some other communications systems to develop samples of base-band in-phase and quadrature components of an input bandpass signal. A bandpass signal of center frequency f IF  can be demodulated into baseband by mixing with a complex sinusoidal signal e j2  Pπ t of frequency f IF . The resulting baseband signal is a complex signal with a real, or &#34;in-phase&#34; component represented by I, and an imaginary, or &#34;quadrature&#34;, component represented by Q. Once a bandpass signal is demodulated into its in-phase and quadrature components, various commonly used modulation schemes such as amplitude (AM), frequency (FM), single-side-band (SSB), and quadrature-amplitude-phase modulations can be extracted by simple arithmetic operations. For example, the upper side-band of a SSB modulated signal can be extracted by adding the I and Q components together. Furthermore, it is advantages especially when data communication is involved, to digitized the output to produce digital output samples of the I and Q components. 
     FIG. 1 is a block diagram showing a conventional analog circuit for demodulating the in-phase (I) in quadrature (Q) components of an input analog signal. The analog signal is received on input line 10, which is then split into in-phase line 12 and quadrature phase line 14. Cosine mixer 16 mixes the analog input signal with a cosine signal (at the center frequency of the pass-band of the input signal) and provides the mixed signal along line 18 to low pass filter (LPF) 20, which attenuates undesirable image by-products of the mixing. The filtered signal is provided along line 22 to analog-to-digital converter (ADC) 24 which converts the analog signal to in-phase samples at a sampling rate f s  and provides the in-phase samples I on bus 26. 
     Similarly, sine mixer 28 mixes the input analog waveform with a conventional sine wave and provides the mixed signal on line 30 to LPF 32. LPF 32 attenuates undesirable image by-products of the mixing and provides the filtered signal on line 34 to ADC 36. ADC 36 converts the filtered signal to digital quadrature samples at a sampling rate f s  and provides the quadrature output samples Q on bus 38. 
     The circuit of FIG. 1 has a number of drawbacks and constraints. For example, the circuit is difficult to implement. The sine and cosine waveforms must be exactly 90° out of phase with each other in order to produce accurate in-phase and quadrature samples. In data communication, mismatches in the sine and cosine phases will result in bit errors. In addition, the two mixers must have good linearity to avoid mixing in spurious frequency components. 
     FIG. 2 is a block diagram of another prior art approach which addresses some of the drawbacks and constraints of the circuit of FIG. 1. The circuit of FIG. 2 performs the out-of-phase mixing of the input waveform in the digital domain, avoiding the use of a problematic analog multipliers and providing tight control over the sine and cosine waveforms. The analog input waveform is received on line 10 and converted to a digital signal by ADC 40. The digital signal is provided on buses 44 and 45. Digital multiplier 46 multiplies the converted samples received on bus 44 with cosine-wave samples (i.e., coefficients) and provides the multiplied samples on bus 48 to decimator 50. Decimator 50 conventionally decimates, or downsamples, the cosine-multiplied samples and provides in-phase samples (I) on output bus 52. 
     Similarly, digital multiplier 54 multiplies the samples received on bus 46 by sine-wave samples and provides the multiplied samples on bus 56 to decimator 58. Decimator 58 downsamples the sine-multiplied samples and provides quadrature (Q) output samples on bus 60. Decimator 58 operates at the same rate as does decimator 50. The drawbacks of this approach are the complexity and cost of the digital-signal-processing and in the need for high-speed, high-resolution ADC. 
     FIG. 3 is a block diagram showing an improved implementation of the circuit of FIG. 2 using a sigma-delta ADC for which f s  =4×f IF  where f s  is the sampling frequency of the sigma-delta ADC and f IF  is the center frequency of the pass-band of the analog input waveform. The sigma-delta ADC provides a one-bit digital stream at an oversampling rate and performs noise-shaping such that the quantization noise power is shifted to frequencies outside of the band of interest. As will be understood by those skilled in the art, four evenly-spaced samples of a cosine signal may equal the set of values {1, 0, -1, 0}; and four corresponding evenly-spaced samples of a sine waveform, being 90° out of phase with the cosine waveform, then will have values {0, -1, 0, 1}. These sampled (i.e., coefficient) values are used, respectively, by the multipliers 46 and 54, in the prior art circuit of FIG. 3, as the cosine and sine samples which are multiplied with the input signal. Multiplication by such a limited set of coefficients (i.e., 1, 0 and -1) can be implemented simply with conventional logic, as will be appreciated by those skilled in the art. 
     While the digital circuit of FIG. 3 does provide advantages over the analog circuit of FIG. 1, in terms of increasing the simplicity and performance of the multipliers, the system suffers from a number of drawbacks. Specifically, because the frequency of the input waveform must be 1/4 that of the sampling frequency (or similarly related), the oversampling ratio (OSR) of the sigma-delta ADC is limited. This places a great demand on the anti-aliasing filter (not shown) which precedes the circuit to reduce low frequency components of the input waveform before conversion. The oversampling ratio (OSR) for a band-pass sigma-delta ADC is defined as the sampling frequency f s  divided by twice the bandwidth f BW  of the input waveform: OSR=f s  /2f BW . A typical example includes an input waveform having a center frequency IF=455, kHz having a bandwidth f BW  30 kHz, and a sigma-delta converter having a sampling rate f s  =1.8 MHz. In this example, the oversampling would be equal to approximately 30, which is quite small. As a result, the signal-to-noise ratio of the output samples is relatively low and may not be acceptable for accuracy reasons. 
     SUMMARY OF THE INVENTION 
     The aforementioned drawbacks of the prior art are overcome by a circuit that includes an oversampling ADC that receives the input waveform and converts the input waveform to digital samples at an oversampling rate; a first digital filter which receives the digital samples from the ADC directly and provides the in-phase component samples of the input waveform; and second digital filter which receives the digital samples from the ADC directly and provides the quadrature component samples of the input waveform. 
     In an exemplary embodiment of the present invention, the first and second digital filters perform the function of demodulating the I and Q components while also decimating the ADC output samples. 
     In an exemplary embodiment, each coefficient for the first digital filter include the product of a corresponding constant decimation filter coefficient value and respective a cosine wave coefficient; similarly each coefficient for the second digital filter include the product of a corresponding constant decimation filter coefficient value and a respective sine wave coefficient. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a block diagram of a prior art in-phase and quadrature sampling circuit; 
     FIG. 2 is a block diagram of another prior art in-phase and quadrature sampling circuit; 
     FIG. 3 is a block diagram of a specific implementation of the prior art in-phase and quadrature sampling circuit of FIG. 2; 
     FIG. 4 is a block diagram of an exemplary in-phase and quadrature sampling circuit according to the present invention; and 
     FIG. 5 is a detailed block diagram of an exemplary digital filter for use in the circuit of the present invention. 
    
    
     DETAILED DESCRIPTION 
     FIG. 4 is a block diagram of an illustrative embodiment of an in-phase and quadrature sampling circuit according to the present invention. The circuit of FIG. 4 receives an analog input waveform on line 10. Sigma-delta ADC 40 converts the input analog waveform to a one-bit digital stream at a sampling rate f s  and a predefined oversampling ratio. The one-bit digital stream is provided on bus 42 and to buses 44 and 46. The one-bit digital stream is filtered by digital filter 62 and in-phase samples are provided on output bus 52. Similarly, the one-bit digital stream is filtered by digital filter 64 and output quadrature samples are provided on output bus 60. 
     Digital filter 62 and digital filter 64 each perform the functions of both demodulation and decimation by the downsampling ratio. Of course, the demodulation performed by filter 62 preferably is 90° out of phase with the demodulation performed by digital filter 64. The decimation performed by digital filter 62 is identical to that performed by digital filter 64. In other words, both filters 62 and 64 downsample the samples received from the ADC by the same downsampling ratio. That downsampling ratio is equal to the oversampling ratio of the sigma-delta ADC modulator. 
     One implementation of the demodulator/decimator filter 62 is shown in the simple block diagram of FIG. 5. While the digital filter 62, as illustrated, includes a four-tap delay line filter, it should be understood by those skilled in the art that a filter with many more stages is commonplace and may be used such as, for example, a filter with 4,096 taps. 
     Filter 62 includes delay elements 66, 68, 70 and 72 connected in cascade to input bus 44. The node between each delay element is connected to a different one of four multipliers 74, 76, 78 and 80. Multipliers 74, 76, 78 and 80 have (or receive) corresponding coefficients C0, C1, C2 and C3, respectively, by which they multiply their signal inputs. The outputs from the multipliers are provided to summer 82, which provides digital output samples on bus 52. 
     Once a decimation filter function is known, the value for each of the coefficients Cx (where x=0, 1, . . . ) is equal to the product of the corresponding sampled cosine coefficient and the coefficient of the decimation filter function for that tap. For example, assuming f s  =4×f IF , and 4 sine wave sample coefficients used and four cosine wave sampled coefficients are used. In this example, 
     
         coefficient C0=cosine θ.sub.0 ×h.sub.0, 
    
     
         coefficient C1=cosine θ.sub.1 ×h.sub.1, 
    
     
         coefficient C2=cosine θ.sub.2 ×h.sub.2, and 
    
     
         coefficient C3=cosine θ.sub.3 ×h.sub.3, 
    
     where cosine θhd n represents the nth sampled cosine coefficient and h n  represents the constant conventional decimation filter coefficient for the corresponding sample. 
     As an example, assume f s  =1.82 and f IF  =455 kHz. Also assume that h 0  =1, H 1  =2, h 2  =2, h 3  =1, and cosine θ=1, cosine θ=0, cosine θ=1, and cosine θ=1. Thus, C 0  =1, C 1  =0, C 2  =2, C 3  =0. 
     The digital filter 64, corresponding to the sine wave demodulator, is identical to filter 62 shown in FIG. 5 except that the coefficients therefor are generated as a product of the corresponding sampled sine wave coefficient and the constant conventional decimator coefficient for each tap. 
     The sine wave and cosine wave sampled coefficients may be treated as remaining constant at each tap when the output samples of the filter are enabled, if the following criterion is met: f IF  =K(f s  /DSR), where K is a constant and DSR is the downsampling ratio of the decimation filter. If this criterion is met, and f s  and f IF  are known, then the filter coefficients can be computed and preprogrammed. 
     Thus, one advantage of this invention is that conventional decimation filters for a pair of non-quadrature channels can be reprogrammed with the known (computed) coefficients, to implement a dual demodulation/decimation function, and provide in-phase and quadrature sampled outputs as taught herein. 
     Additionally, simple one-bit decimation filters and one-bit sigma-delta ADCs are used in the exemplary circuit of the present invention. Such elements are very simple and inexpensive to implement. The steps of conversion, decimation, I and Q demodulation, and low-pass filtering are all performed in two very simple stages. 
     As an alternative to &#34;pre-programming&#34; the digital filter, by including or hard-wiring only a single set of the coefficients, multiple sets of coefficients also can be stored and made available to the filters, loosening the constraints on the required relationship between f IF  and f s . Particularly, if multiple different coefficients were stored, then the restriction on the operating rate of the modulator would be loosened. Particularly, the following relationship would be available: f IF  =K/b(f s  /DSR), where K/b is a fractional relationship rather than an integer relationship. This loosened criterion would allow for multiple different relationships between f s  and f IF  so long as the multiple relationships are known ahead of time and therefore the multiple different sets of coefficients could be computed and stored. 
     Alternatively, as will be understood by those skilled in the art, the coefficients could be computed dynamically. If so, then the processor 80 would be used to compute the coefficients and the memory 82 used to store them, as shown in FIG. 4. 
     While there have been shown and described what are at present considered the preferred embodiments of the present invention, which have been disclosed by way of example only, it would be obvious to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as presented above and as defined by the appended claims and equivalents thereto. Particularly, while a specific circuit has been shown for implementing the digital filters according to the present invention, other filters having different coefficient values could be used. Also, while a sigma-delta ADC has been shown and described for use with the circuit of the present invention, other oversampling converters (i.e., non-sigma-delta converters) could be used.