Abstract:
A switched-capacitor charge pump device is proposed, which is designed for integration to a circuit system, such as a PLL (phase-locked loop) circuit system, for generation of an output direct-current (DC) voltage with a wide amplitude range; and which is characterized by the utilization of two switched-capacitor circuit units in addition to the output capacitor circuit and the utilization of an output voltage comparing circuit (such as a Schmitt trigger) for comparing the end-result output DC voltage against a half-amplitude drive voltage such that when the switched-capacitor circuit units are subjected to a charging-discharging action for voltage pump-up or pump down operations, the switched-capacitor circuit units are switched between a full-amplitude drive voltage and a half-amplitude drive voltage. This feature allows the invention to provide an output DC voltage with a wider amplitude range than prior art.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   This invention relates to electronic circuit technology, and more particularly, to a switched-capacitor charge pump device which is designed for integration to a circuit system, such as a PLL (phase-locked loop) circuit system, for generation of an output direct-current (DC) voltage with a wide amplitude range. 
   2. Description of Related Art 
   In PLL (phase-locked loop) and DLL (delay-locked loop) circuitry, the charge pump is an essential circuit component which is capable of being driven by a pair of phase-difference signals (which respectively indicate the lagging or leading of the output frequency generated by the PLL or DLL circuitry with respect to a reference frequency) and responsively generating an output of a DC voltage whose amplitude is proportional to the phase difference between the output frequency and the reference frequency. Fundamentally, the lagging of the output frequency against the reference frequency will result in a negative phase-difference signal which is presented as a pump-up enable signal (UP) to the charge pump; whereas the leading of the output frequency will result in a positive phase-difference signal which is presented as a pump-down enable signal (DN) to the charge pump. The output of the charge pump is a DC voltage which is used as a control voltage for a VCO (voltage-controlled oscillation) unit in PLL circuitry or a VCDL (voltage-controlled delay line) unit in DLL circuitry for adjusting the output frequency to match in phase with the reference frequency. 
   Theoretically, the output frequency range of a PLL-VCO circuit is proportional to the amplitude range of the input control voltage, i.e., the amplitude range of the DC output of the charge pump. Accordingly, if we want to increase the PLL-VCO output frequency range, this can be achieved simply by increasing the amplitude range of the DC output of the charge pump. 
   In practice, however, traditional charge pump circuits are only capable of offering a limited amplitude range of DC output; and therefore, the PLL-VCO circuits are also only capable of offering a limited range of frequency output in proportion to the voltage output of the charge pump. For instance, the charge pump circuitry constructed using a 90 nanometer CMOS technology of nowadays can only provide an output DC voltage with an amplitude range from 0.3 V to 0.7 V, i.e., an amplitude span of only 0.4 V, at 1V supply. 
   Moreover, traditional charge bump circuits are typically constructed on a circuit architecture that includes both a PMOS-based current source and an NMOS-based current source. One drawback to the use of two different MOS types of current sources in the same charge pump circuit architecture is that it would result in a mismatch in electrical characteristics between the two different types of current sources and thus result in a poor electrical performance. 
   SUMMARY OF THE INVENTION 
   It is therefore an objective of this invention to provide a switched-capacitor charge pump device which can generate an output DC voltage with a wider amplitude range than the prior art. 
   It is another objective of this invention to provide a switched-capacitor charge pump device which can be implemented without using current sources of different MOS types for the purpose of preventing the problem of a mismatch in electrical characteristics between the two different types of current sources as in the case of prior art. 
   The switched-capacitor charge pump device according to the invention is designed for integration to a circuit system, such as a PLL (phase-locked loop) or a DLL (delay-locked loop) circuit system, for generation of an output direct-current (DC) voltage with a wide amplitude range. 
   In circuit architecture, the switched-capacitor charge pump device of the invention comprises: (A) a first frequency divider and a second frequency divider; (B) an output voltage comparing circuit; (C) a first switch control unit and a second switch control unit; (D) a first switched-capacitor circuit and a second switched-capacitor circuit; and (E) an output capacitor circuit. 
   The switched-capacitor charge pump device according to the invention is characterized by the utilization of two switched-capacitor circuit units in addition to the output capacitor circuit and the utilization of an output voltage comparing circuit (such as a Schmitt trigger) for comparing the end-result output DC voltage against a half-amplitude drive voltage such that when the switched-capacitor circuit units are subjected to a charging-discharging action for voltage pump-up or pump down operations, the switched-capacitor circuit units are switched between a full-amplitude drive voltage (V dd ) and a half-amplitude drive voltage V dd/2 . This feature allows the invention to provide an output DC voltage with a wider amplitude range than prior art. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
     The invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein: 
       FIG. 1  is a schematic diagram showing a practical application example of the switched-capacitor charge pump device of the invention; 
       FIG. 2  is a schematic diagram showing the I/O functional model of the switched-capacitor charge pump device of the invention; 
       FIG. 3  is a schematic diagram showing the circuit architecture of the switched-capacitor charge pump device of the invention; 
       FIG. 4  is a schematic diagram showing the internal circuit architecture of a first switch control unit and a second switch control unit used to construct the switched-capacitor charge pump device of the invention; 
       FIG. 5  is a schematic diagram showing the internal circuit architecture of a first switched-capacitor circuit and a second switched-capacitor circuit used to construct the switched-capacitor charge pump device of the invention; 
       FIG. 6A  is a signal diagram showing the waveforms and sequencing of a set of switch control signals under the condition of a phase lag in f VCO  against f REF ; 
       FIG. 6B  is a signal diagram showing the waveforms and sequencing of a set of switch control signals under the condition of a phase lead in f VCO  against f REF ; 
       FIG. 7A  is a graph showing a plot of V out  versus time during a charging operation which is resulted from a circuit simulation on the invention; and 
       FIG. 7B  is a graph showing a plot of V out  versus time during a discharging operation which is resulted from a circuit simulation on the invention. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   The switched-capacitor charge pump device according to the invention is disclosed in full details by way of preferred embodiments in the following with reference to the accompanying drawings. 
   APPLICATION OF THE INVENTION 
     FIG. 1  shows an application example of the switched-capacitor charge pump device of the invention  100 . As shown, in this application example, the switched-capacitor charge pump device of the invention  100  is used as a circuit component for integration to a PLL (phase-locked loop) circuit system  10  which additionally includes a phase detector  11 , a loop filter  12 , a VCO (voltage-controlled oscillation) circuit  13 , and a frequency divider  14 . Since PLL is a well known and widely used circuit technology in the electronics industry, detailed description thereof will not be given in this specification. 
   Beside the application with PLL circuit systems, the switched-capacitor charge pump device of the invention  100  can also be used for integration to a DLL (delay-locked loop) circuit system. 
   FUNCTION OF THE INVENTION 
     FIG. 2  is a schematic diagram showing the I/O (input/output) functional model of the switched-capacitor charge pump device of the invention  100 . As shown, the switched-capacitor charge pump device of the invention  100  is designed with an I/O interface having an input interface for reception of the following signals: (UP, DN) and (f VCO , f REF ); where f VCO  is a divide-by-N feedback of the output frequency signal f o  of the PLL circuit system  10 ; f REF  is a reference signal; and UP and DN are respectively a pump-up enable signal and a pump-down enable signal generated by the phase detector  11  in response to the phase difference between f VCO  and f REF . 
   In operation, the switched-capacitor charge pump device of the invention  100  is capable of responding to the input of (UP, DN) and (f VCO , f REF ) by generating an output DC voltage V out  whose amplitude will be pumped up to a higher level at the presence of the pump-up enable signal (UP) and pumped down to a lower level at the presence of the pump-down enable signal (DN). In the application with the PLL circuit system  10 , the output DC voltage V out  is transferred via the loop filter  12  to the VCO circuit  13  for use as a control voltage for the VCO circuit  13  to adjust its output oscillating signal f o  to match in phase with the reference signal f REF . 
   ARCHITECTURE OF THE INVENTION 
   As shown in  FIG. 3 , in circuit architecture, the switched-capacitor charge pump device of the invention  100  comprises: (A) a first frequency divider  111  and a second frequency divider  112 ; (B) an output voltage comparing circuit  120 ; (C) a first switch control unit  131  and a second switch control unit  132 ; (D) a first switched-capacitor circuit  141  and a second switched-capacitor circuit  142 ; and (E) an output capacitor circuit  150 . Firstly, the respective attributes and functions of these constituent circuit components of the invention are described in details in the following. 
   First Frequency Divider  111  and Second Frequency Divider  112   
   The first frequency divider  111  is capable of performing a divide-by-2 frequency dividing operation on the oscillating signal f VCO  to thereby generate an output of a half-frequency oscillating signal (which is expressed as f VCO/2 ). The output half-frequency oscillating signal f VCO/2  is then transferred to the first switch control unit  131 . 
   In a similar manner, the second frequency divider  112  is capable of performing a divide-by-2 frequency dividing operation on the reference signal f REF  to thereby generate an output of a half-frequency reference signal (which is expressed as f REF/2 ). The output half-frequency reference signal f REF/2  is then transferred to the second switch control unit  132 . 
   Output Voltage Comparing Circuit  120   
   The output voltage comparing circuit  120  is capable of comparing the output DC voltage V out  of the switched-capacitor charge pump device of the invention  100  against a half-amplitude drive voltage V dd/2 . If V out &lt;V dd/2 , the output voltage comparing circuit  120  will generate a logic-LOW voltage output (i.e., V state =LOW); and whereas if V out ≧V dd/2 , the output voltage comparing circuit  120  will generate a logic-HIGH voltage output (i.e., V state =HIGH). The output voltage V state  is used as a drive-voltage switching enable signal and concurrently transferred to both the first switch control unit  131  and the second switch control unit  132 . 
   In practice, for example, the output voltage comparing circuit  120  can be implemented with a Schmitt trigger or an analog comparator. However, since the Schmitt trigger is capable of low-noise operation, it is more preferable for use than the analog comparator. 
   First Switch Control Unit  131  and Second Switch Control Unit  132   
   The first switch control unit  131  has an input interface for reception of 3 input signals (UP, f VCO/2 , V state ) and an output interface for generation of a first set of switch control signals (V ub2 , V ub1 , V ut , V us ). These switch control signals (V ub2 , V ub1 , V ut , V us ) are then transferred to the first switched-capacitor circuit  141 . 
   In a similar manner, the second switched-capacitor circuit  142  has an input interface for reception of 3 input signals (DN, f REF/2 , V state ) and an output interface for generation of a second set of switch control signals (V db2 , V db1 , V dt , V ds ). These switch control signals (V db2 , V db1 , V dt , V ds ) are then transferred to the second switched-capacitor circuit  142 . 
   In practice, for example, as shown in  FIG. 4 , the first switch control unit  131  can be implemented with a logic circuit which is composed of three AND gates  211 ,  212 ,  213  and two inverters  214 ,  215 ; while the second switch control unit  132  can be implemented with a similar logic circuit which is also composed of three AND gates  221 ,  222 ,  223  and two inverters  224 ,  225  which are arranged in a symmetrical manner with respect to the first switch control unit  131 . 
     FIG. 6A  shows the waveforms and sequencing of (V ub2 , V ub1 , V ut , V us ) and (V db2 , V db1 , V dt , V ds ) with respect to (f VCO , f REF , V state ) under the condition of f VCO  lagging in phase against f REF ; while  FIG. 6B  shows their waveforms and sequencing under the condition of f VCO  leading in phase against f REF . 
   As shown in  FIG. 6A , it is assumed that f VCO  lags in phase against f REF  by a phase difference of ΔP. In this case, it will cause the switching control signals (V ub2 , V ub1 , V ut , V us ) to act as follows: (1) V ut  becomes a periodic pulse train with a pulse width of T 0  and a period of 2*T 0 ; (2) V us  becomes a periodic pulse train with a pulse width of ΔP and a period of 2*T 0 , and with each pulse having a rising edge in synchronization with the falling edge of one pulse in V ut ; (3) V ub2  becomes a periodic pulse train which appears only during the time period when (V state =LOW), with a pulse width of ΔP and a period of 2*T 0 , and with each pulse being in synchronization with one pulse in V us ; and (4) V ub1  becomes a periodic pulse train which appears only during the time period when (V state =HIGH), with a pulse width of ΔP and a period of 2*T 0 , and with each pulse being in synchronization with one pulse in V us . 
   Further, as also shown in  FIG. 6A , for the second set of switch control signals (V db2 , V db1 , V dt , V ds ), the lagging of f VCO  will cause V dt  to become a periodic pulse train with a pulse width of T 0  and a period of 2*T 0 , and with a phase lag of ΔP with respect to f REF . Beside V dt , all the other three switch control signals (V db2 , V db1 , V ds ) remain in logic-LOW state. 
   As further shown in  FIG. 6B , under the condition of f VCO  leading in phase against f REF , the waveforms and sequencing of (V ub2 , V ub1 , V ut , V us ) and (V db2 , V db1 , V dt , V ds ) with respect to (f VCO , f REF , V state ) are similar to that shown in  FIG. 6A  except in a reversed manner. 
   First Switched-Capacitor Circuit  141   
   As shown in  FIG. 5 , the first switched-capacitor circuit  141  is composed of a first capacitor  310  and a first switch array including a first switch  401 , a second switch  402 , a third switch  403 , a fourth switch  404 , and a fifth switch  405 . The connection and operation of each of these switches  401 ,  402 ,  403 ,  404 ,  405  are described below. 
   The first switch  401  is capable of being activated by V us  (when V us =HIGH) for performing a switching operation to connect the negative polarity (−) of the first capacitor  310  to a first current source I u , so that the first current source I u  can render a discharging operation on the first capacitor  310 . 
   The second switch  402  is capable of being activated by V ub2  (when V ub2 =HIGH) for performing a switching operation to connect the positive polarity (+) of the first capacitor  310  to a full-amplitude drive voltage V dd , so that the first capacitor  310  can be charged by V dd  from the positive polarity (+). 
   The third switch  403  is capable of being activated by V ub1  (when V ub1 =HIGH) for performing a switching operation to connect the positive polarity (+) of the first capacitor  310  to a half-amplitude drive voltage V dd/2  (i.e., the amplitude of V dd/2  is half of V dd ), so that the first capacitor  310  can be charged by V dd/2  from the positive polarity (+). 
   The fourth switch  404  is capable of being activated by V ut  (when V ut =HIGH) for performing a switching operation to connect the negative polarity (−) of the first capacitor  310  to the half-amplitude drive voltage V dd/2 , so that the first capacitor  310  can be charged by V dd/2  from the negative polarity (−). 
   The fifth switch  405  is capable of being activated by V ut  (when V ut =HIGH) for performing a switching operation to connect the positive polarity (+) of the first capacitor  310  to the output capacitor circuit  150 , so that the capacitive voltage V cp1  on the first capacitor  310  can be transferred to the output capacitor circuit  150 . 
   Second Switched-Capacitor Circuit  142   
   Furthermore, also shown in  FIG. 5 , the second switched-capacitor circuit  142  is composed of a second capacitor  320  and a second switch array including a sixth switch  406 , a seventh switch  407 , an eighth switch  408 , a ninth switch  409 , and a tenth switch  410 . The connection and operation of each of these switches  406 ,  407 ,  408 ,  409 ,  410  are described below. 
   The sixth switch  406  is capable of being activated by V ds  (when V ds =HIGH) for performing a switching operation to connect the positive polarity (+) of the second capacitor  320  to a second current source I d , so that the second current source I d  can render a discharging operation on the second capacitor  320 . 
   The seventh switch  407  is capable of being activated by V db1  (when V db1 =HIGH) for performing a switching operation to connect the negative polarity (−) of the second capacitor  320  to the full-amplitude drive voltage V dd , so that the second capacitor  320  can be charged by V dd  from the negative polarity (−). 
   The eighth switch  408  is capable of being activated by V db2  (when V db2 =HIGH) for performing a switching operation to connect the negative polarity (−) of the second capacitor  320  to the half-amplitude drive voltage V dd/2 , so that the second capacitor  320  can be charged by V dd/2  from the negative polarity (−). 
   The ninth switch  409  is capable of being activated by V dt  (when V dt =HIGH) for performing a switching operation to connect the negative polarity (−) of the second capacitor  320  to the half-amplitude drive voltage V dd/2 , so that the second capacitor  320  can be charged by V dd/2  from the negative polarity (−). 
   The tenth switch  410  is capable of being activated by V dt  (when V dt =HIGH) for performing a switching operation to connect the positive polarity (+) of the second capacitor  320  to the output capacitor circuit  150 , so that the capacitive voltage V cp2  on the second capacitor  320  can be transferred to the output capacitor circuit  150 . 
   In practice, for example, since the first current source I u  and the second current source I d  are both used for discharging purpose, i.e., the current of I u  and the current of I d  both flow to the ground GND, they can be realized by using MOS transistor circuit architectures of the same size and type, i.e., both realized by using NMOS-based circuit architecture or PMOS-based circuit architecture. This feature can be used to prevent the problem of a mismatch in electrical characteristics in conventional charge pump circuitry due to the use of both a PMOS-based current source and an NMOS-based current source in the same charge pump circuitry. 
   Output Capacitor Circuit  150   
   The output capacitor circuit  150  has one end connected to the output port (V out ) and the other end connected to the ground GND, and which operates on a switched reception of V cp1  from the first switched-capacitor circuit  141  and V cp2  from the second switched-capacitor circuit  142  to thereby generate a capacitive voltage V cp0  which is used to serve as the output DC voltage V out  of the switched-capacitor charge pump device of the invention  100 , i.e., V out =V cp0 . 
   OPERATION OF THE INVENTION 
   The following is a detailed description of a practical application example of the switched-capacitor charge pump device of the invention  100  during actual operation for providing an output DC voltage with a wider amplitude range compared to the prior art. 
   In the following example of the operation of the invention, it is assumed that f VCO  lags in phase against f REF  as illustrated in  FIG. 6A . 
   Under the condition of a phase lag in f VCO , the oscillating signal f VCO  and the reference signal f REF  are first processed respectively by the first frequency divider  111  and the second frequency divider  112  for divide-by-2 frequency dividing operation to thereby obtain f VCO/2  and f REF/2 . This operation effectively double the pulse width of the original f VCO  and f REF . The half-frequency oscillating signal f VCO/2  is then processed by the inverter  214  in the first switch control unit  131  to obtain an output of the switch control signal V ut ; and meanwhile, the half-frequency reference signal f REF/2  is processed by the inverter  224  in the second switch control unit  132  to obtain an output of the switch control signal V dt . 
   When (V ut =HIGH), it activates the fourth switch  404  and the fifth switch  405  in the first switched-capacitor circuit  141  to be switched to conductive state, thereby connecting the positive polarity (+) of the first capacitor  310  concurrently to both the full-amplitude drive voltage V dd  and the output capacitor circuit  150 . During this time, when (V dt =HIGH), it activates the ninth switch  409  and the tenth switch  410  in the second switched-capacitor circuit  142  to be switched to conductive state, thereby connecting the negative polarity (−) of the second capacitor  320  to V dd  and meanwhile connecting the positive polarity (+) to the output capacitor circuit  150 . 
   Subsequently, when (V ut =LOW), it activates the first switch control unit  131  to switch both V us  and V ub2  to logic-HIGH state. Under the condition of (V us , V ub2 )=(HIGH, HIGH), it activates a switching operation to connect the negative polarity (−) of the first capacitor  310  to the first current source I u  and meanwhile connect the positive polarity (+) of the first capacitor  310  to V dd . 
   The above switching actions result in a voltage pump-up operation on the output DC voltage V out , which will continue under the condition of (V state =LOW), i.e., V out &lt;V dd/2 , until V state  is switched to logic-HIGH state, i.e., V out ≧V dd/2 . Under the condition of (V state =HIGH), V ub2  presents no pulses; and instead, V ub1  presents a sequence of logic-HIGH pulses at a period of 2*T 0  and in synchronization with the pulses of V us . Under the condition of (V ub1 =HIGH), it activates a switching operation to connect the positive polarity (+) of the first capacitor  310  to V dd/2 . 
   The above voltage pump-up operation on the output DC voltage V out  will incessantly continue until f VCO  is matched in phase with f REF . 
   On the other hand, under the condition of a phase lead of f VCO  against f REF , a voltage pump-down operation is performed by using the switch control signals shown in  FIG. 6B  to change f VCO  into phase match with f REF . The voltage pump-down operation is performed substantially in a reversed manner as the voltage pump-up operation described above. 
   PERFORMANCE OF THE INVENTION 
     FIGS. 7A-7B  are graphs showing the output characteristics of V out  under the condition of V dd =1 V (volt) resulted from a circuit simulation on the invention; wherein  FIG. 7A  shows a characteristic plot of V out  versus time during a charging operation; while  FIG. 7B  shows a characteristic plot of V out  versus time during a discharging operation. 
   It can be seen from  FIGS. 7A-7B  that V out  can reach a maximum amplitude of about +1.1 V during the charging operation, and a minimum amplitude of about −0.1 V during the discharging operation. In other words, under the condition of V dd =1 V, the invention is capable of providing an output DC voltage V out  in the amplitude range from −0.1 V to +1.1 V, i.e., an amplitude span of 1.2 V, which is significantly larger than the amplitude span of 0.4 V provided by the prior art. The invention is therefore more advantageous to use than the prior art. 
   The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.