Abstract:
A semiconductor device has a substrate. A semiconductor die is coupled to a first surface of the substrate. An encapsulate is placed over the semiconductor die. A first plurality of lands is formed on the first surface of the substrate around the encapsulate. A second plurality of lands is formed on a second surface of the substrate. A first group of the second plurality of lands has a pitch and a second group of the second plurality of lands has a pitch of a different length.

Description:
FIELD OF THE INVENTION 
     This invention relates to semiconductor devices and, more specifically, to a semiconductor device having land patterns on the top and bottom surfaces which match such that the ball pitches between the top and bottom land pads match where there are corresponding ball pad locations. 
     BACKGROUND OF THE INVENTION 
     As electronic devices get smaller, the components within these devices must get smaller as well. Because of this, there has been an increased demand for the miniaturization of components and greater packaging density. Integrated Circuit (IC) package density is primarily limited by the area available for die mounting and the height of the package. One way of increasing the density is to stack multiple die or packages vertically in an IC package. Stacking multiple die or packages will maximize function and efficiency of the semiconductor package. 
     Stacked semiconductor packages are different from regular semiconductor packages in that they have land pads on both the top and bottom surfaces of the stacked semiconductor package. Due to the need for additional standoff height on a top surface of the stacked semiconductor package, the solder ball size, and hence pitch on the top surface needs to be rather large so that there is sufficient clearance between the stacked packages. However, the use of a large solder ball size is not feasible for the bottom surface of the stacked semiconductor package since this would lead to a solder ball count which would be fairly low. 
     Because of the above problem, present stacked packages use a ball pitch of one dimension for the top surface and a ball pitch of a second dimension for the bottom surface. The non-uniform ball pitch causes non-alignment of lands between the top surface and the bottom surface. This makes substrate design more complicated since metal traces will have more complex routings. Furthermore, non-uniform ball pitches require more complicated technologies like via-in pad to be used. 
     Therefore, a need existed to provide a device and method to overcome the above problem. 
     SUMMARY OF THE INVENTION 
     A semiconductor device has a substrate. A semiconductor die is coupled to a first surface of the substrate. An encapsulate is placed over the semiconductor die. A first plurality of lands is formed on the first surface of the substrate around the encapsulate. A second plurality of lands is formed on a second surface of the substrate. A first group of the second plurality of lands has a first pitch and a second group of the second plurality of lands has a second pitch. 
     The present invention is best understood by reference to the following detailed description when read in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a cross-sectional view of one embodiment of the semiconductor device of the present invention; 
         FIG. 2  is a top view of the semiconductor device depicted in  FIG. 1 ; 
         FIG. 3  is a cross-sectional view of another embodiment of the present invention; 
         FIG. 4  is a top view of the embodiment depicted in  FIG. 3 ; 
         FIG. 5  is a cross-sectional view of another embodiment of the present invention; and 
         FIG. 6  is a is a cross-sectional view of yet another embodiment of the present invention. 
     
    
    
     Common reference numerals are used throughout the drawings and detailed description to indicate like elements. 
     DETAILED DESCRIPTION 
     Referring to  FIGS. 1 and 2 , a semiconductor device  10  is shown. The semiconductor device  10  has a device  12 . The device  12  is coupled to a first surface of a substrate  16 . The device  12  is encapsulated with a mold compound  14 . The device  12  may be any type of device. For example, the device  12  may be a memory device, a logic device, an ASIC device, and other like elements. It should be noted that the listing of the above types of devices  12  is given as an example and should not be seen as to limit the scope of the present invention. 
     The device  12  has a semiconductor die  12 A which is placed on the first surface of the substrate  16 . An adhesive layer  18  is used to couple the semiconductor die  12 A to the substrate  16 . The adhesive layer  18  may be an adhesive film, an epoxy, or the like. The listing of the above adhesive layers  18  should not be seen as to limit the scope of the present invention. The semiconductor die  12 A is then electrically coupled to the substrate  16 . The semiconductor die  12 A may be coupled to the substrate  16  through the use of wirebonds  12 B. The wirebonds  12 B are generally coupled to bond pad  20  formed on the first surface of the substrate  16 . A mold compound  14  is then used to encapsulate the device  12 . 
     Electrical contacts  22  are coupled to a second surface of the substrate  16 . The electrical contacts  22  are used to provide an electrical connection to the stacking structure  10 . The electrical contacts  22  may be a plurality of solder balls  22 A as shown in  FIG. 1 . The solder balls  22 A will be electrically coupled to the second surface of the substrate  16  via a first plurality of lands  24 . In general, a reflow process may be used to couple the solder balls  22 A to the second surface of the substrate  16 . Alternative methods may be used to couple the solder balls  22 A to the substrate  16  without departing from the spirit and scope of the present invention. 
     The substrate  16  has a second plurality of lands  26 . The second plurality of lands  26  are formed on the first surface of the substrate  16 . The lands  26  are used for stacking a second semiconductor device  27  on the semiconductor device  10 . Electrical contacts  28  of the second semiconductor device  27  stacked on top of the semiconductor device  10  are coupled to the lands  26  on the first surface of the substrate  16 . The electrical contacts  28  are used to provide an electrical connection between the semiconductor device  10  and the second semiconductor device  27 . The electrical contacts  28  are generally a plurality of solder balls  28 A. In general, a reflow process may be used to couple the solder balls  28 A to the top surface of the substrate  16 . Alternative methods may be used to couple the solder balls  28 A to the substrate  16  without departing from the spirit and scope of the present invention. 
     In the prior art, a problem arose due to the non-uniform pitch between the lands on the top surface and the lands on the bottom surfaces of the substrate of the semiconductor stacking device. The non-uniform pitch caused non-alignment of the lands on the top surface and lands on the bottom surface of the substrate. The non-alignment of the lands make substrate design more complicated since metal traces will have more complex routings. Furthermore, non-uniform pitches require more complicated technologies like via-in pad to be used. 
     To overcome the above problems, the semiconductor device  10  employs a split pitch footprint for the lands  24  on the second surface of the substrate  16 . The lands  24  along the outer perimeter of the second surface of the substrate  16  will be directly below a corresponding land  26  and will employ the same pitch as the land  26 . In other words, the lands  26  of the first surface of the substrate  16  are aligned with a corresponding land  24  directly below. Thus, when the solder balls  28 A are placed on the lands  26 , the solder balls  28 A will have the same pitch as a corresponding solder balls  22 A located approximately directly below. The other lands  24  on the second surface of the substrate  16  which are located below the mold compound  14  will have a smaller/tighter pitch. Thus, the solder balls  22 A located below the mold compound  14  will have a smaller pitch then the solder balls  22 A that are aligned directly below the solder balls  28 A that are outside the mold compound  16 . This will allow for additional solder balls  22 A to be placed in the area below the mold compound  14  thereby increasing the number of Input/Output (I/O) contacts. 
     In the embodiment depicted in  FIG. 1 , all of the lands  26  are coupled to a corresponding land  24  located approximately directly below. The lands  26  are not coupled to the semiconductor die  12 A. This simplifies the substrate  16  by reducing the number of metal layers on the substrate  16  since connections are not required between the lands  26  and the semiconductor die  12 A. In general, vias  30  are formed through the substrate  16 . The vias  30  are used to couple the lands  26  on the first surface of the substrate  16  with a corresponding land  24  located approximately directly below. 
     The semiconductor die  12 A may also be coupled to one or more lands  24 . The semiconductor die  12 A is generally coupled to one or more bond pads  20  via a wirebond  12 B. The bond pads  20  are then coupled to a land  24  in one of several manners. First, the bond pads  20  may be coupled to a land  24  located directly below by a via  30  in a similar manner to that disclosed above. A via  30  is formed through the substrate  16  to directly couple the bond pad  20  to a land  24  located directly below. Alternatively, the bond pad  20  may be coupled to a corresponding land  24  in the following manner. Vias  30  are formed partially through the substrate  16  on both the first surface and the second surface of the substrate  16 . The vias  30  which are formed partially through the substrate  16  are then coupled to one another through another metal layer  32  formed in the substrate  16 . Thus, the metal layer  32  will couple the semiconductor die  12 A to a land  24  located below the mold compound  14 . 
     As shown in  FIGS. 1 and 2 , the semiconductor device  10  employs a split pitch footprint for the lands  24  on the second surface of the substrate  16 . The lands  24  along the outer perimeter will be directly below the lands  26  and employ the same pitch as the lands  26 . The lands  24  located below the mold compound  14  will have a smaller/tighter pitch. The split pitch footprint for the lands  24  allows the semiconductor device  10  to have a less complicate substrate  16 . The substrate  16  is less complicated since the substrate  16  will have a reduced number of metal layers in order to couple the lands  24  along the outer perimeter to the lands  26  located directly below. The split pitch footprint further allows the semiconductor device  10  to increase the number of Input/Output (I/O) contacts. Since the lands  24  located below the mold compound  14  will have a tighter pitch, additional lands  24  may be placed on the second surface of the substrate  16  thereby increasing the total number of I/O contacts on the second surface of the substrate  16 . 
     Referring now to  FIGS. 3 and 4 , another embodiment of the semiconductor device  10 ′ is shown. The semiconductor device  10 ′ is similar to that shown in  FIG. 1 , thus only the differences will be discussed. In  FIG. 3 , the lands  26  on the first surface of the substrate  16  are still aligned with a corresponding land  24  directly below. However, at least one of the lands  26  is also coupled to the semiconductor die  12 A. Metal traces  34  formed in the substrate  16  will couple one or more lands  26  on the first surface of the substrate  16  to the semiconductor die  12 A. In general, bond pads  20  are coupled to the semiconductor die  12 A through the use of wirebonds  12 B. The metal traces  34  formed in the substrate  16  will then couple the land  26  on the first surface of the substrate  16  to the bond pads  20 . As seen in  FIG. 3 , the semiconductor device  10 ′ still employs a split pitch footprint for the lands  24 . The lands  24  along the outer perimeter will be directly below lands  26  and employ the same pitch as the lands  26 . The lands  24  located below the mold compound will still have a smaller/tighter pitch. 
     Referring now to  FIG. 5 , another embodiment of the semiconductor device  10 ″ is shown. The semiconductor device  10 ″ is similar to the embodiments shown above, thus only the differences will be discussed. The main difference in the semiconductor device  10 ″ is that one or more lands  26  may not be coupled to a corresponding land  24 . Furthermore, the one or more lands  26  that may not be coupled to a corresponding land  24  may further not be coupled to the semiconductor device. 
     Referring now to  FIG. 6 , in the stacking structures of the previous embodiments, the semiconductor die  12 A is electrically coupled to the substrate  16  through the use of wirebonds  12 B. However, a semiconductor die  12 A may be a flip chip  13  in any of the above embodiments. In using a flip chip  13 , the bumps  13 A of the flip chip  13  are placed on the bond pads  20 . The stacking structure  10  is heated to make a solder connection between the bumps  13 A and the bond pads  20 . The remaining space under the flip chip  13  is then filled with an electrically non-conductive material  40 . The bond pads  20  may be coupled to a land  24  located directly below by a via  30  as disclosed above. Alternatively, bond pads  20  may be coupled to a corresponding land  24  by having vias  30  formed partially through the substrate  16  on both the first surface and the second surface of the substrate  16 . The vias  30  which are formed partially through the substrate  16  are then coupled to one another through another metal layer  32  formed in the substrate  16 . 
     This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification, such as variations in structure, dimension, type of material and manufacturing process may be implemented by one of skill in the art in view of this disclosure.