Abstract:
A driving device is disclosed, which relates to a technology for reducing consumption of a leakage current unnecessary for a driver circuit. The driving device includes: a pre-driver configured to output a drive control signal upon receiving a power-supply voltage in response to an input signal, and change a voltage level of the drive control signal in response to a control signal so as to selectively provide the changed voltage level; an output driver configured to receive the power-supply voltage in response to the drive control signal, and output the received power-supply voltage to an output terminal; and a bulk-voltage controller configured to selectively control bulk-voltage levels of the pre-driver and the output driver in response to the control signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority to Korean patent application No. 10-2013-0068827, filed on Jun. 17, 2013, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as set forth in full. 
       BACKGROUND OF THE INVENTION 
       [0002]    1) Field of the Invention 
         [0003]    Embodiments of the present invention relate to a driving device, and more particularly to a technology for reducing consumption of a leakage current unnecessary for a driver circuit. 
         [0004]    2) Description of the Related Art 
         [0005]    Generally, Integrated Circuits (ICs) include Input/Output (I/O) pins for receiving/transmitting data from/to an external part, and a data output circuit for providing data to the external part. In this case, the I/O pins are coupled to a transmission line such as a printed wiring transmission lines mounted to a substrate of IC devices. Internal data of one IC is applied to another IC through a transmission line acting as an interface. 
         [0006]      FIG. 1  is a block diagram illustrating a data output device according to the related art. 
         [0007]    Referring to  FIG. 1 , the data output device includes a pre-driver  10  and an output driver  20 . 
         [0008]    The pre-driver  10  receives power-supply voltages (VDDQ, VSSQ), and synchronizes data of a global I/O line (GIO) with a clock (DCLK), such that the pre-driver  10  outputs a pull-up signal (PU) and a pull-down signal (PD). The output driver  20  is pulled up or down in response to the pull-up signal (PU) and the pull-down signal (PD), such that the output driver  20  outputs data. The output driver  20  serving as a main driver adjusts impedance to support a high-speed operation of the IC such that the output driver  20  can be matched with impedance of a transmission channel. 
         [0009]    In this case, a voltage switching operation of the pull-up and pull-down driving actions is achieved between one power-supply voltage VDDQ and the other power-supply voltage VSSQ. If a mobile device stays in a low power-supply voltage VDD, a high-and-low level of the swing operation is set to a low level (e.g., 1.2V). 
         [0010]    As the mobile devices are configured to use a lower power-supply voltage, transistor characteristics rapidly deteriorate. In order to improve such transistor characteristics, a transistor is configured to have a very short channel length or a low threshold voltage. That is, transistors contained in an output driver IC configured to use a low power-supply voltage typically have a very small gate width. 
         [0011]    However, if the transistor is configured to have a long channel length or a low threshold voltage, an off-leakage current of the transistor gradually increases in a standby mode. That is, a leakage current occurs even when there is a small voltage difference between a source and a drain of each MOS transistor in a standby mode of the output driver. 
         [0012]    Accordingly, operation characteristics of mobile devices deviate from specification ranges such as a leakage current of IDD 2 , IDD 6 , DPD (Deep Power Down) and DQ pins. However, a leakage current generated from a MOS transistor is a very small amount of current, such that this leakage current does not greatly affect power consumption of integrated circuits (ICs) when there is a small number of output drivers. 
         [0013]    However, as the integration degree of the integrated circuits (ICs) are gradually increased, the number of output drivers is also increased in proportion to the increasing integration degree of the ICs. If the number of output drivers is increased, the amount of a leakage current is also increased, resulting in an increase in total power consumption of the ICs. 
         [0014]    In order to reduce such leakage current, the related art has used the scheme for cutting off source power of transistors. However, a larger-sized driver for facilitating the supply of source power of transistors is needed. In addition, as a frequency becomes gradually higher, the number of transistors to be driven is also increased, so that mobile devices may have difficulty in easily receiving a power source. In addition, if a leakage current of the driver increases, a DC failure unavoidably occurs, resulting in reduction of a production yield. 
         [0015]    In recent times, systems configured to use semiconductor memory devices have been rapidly developed to have smaller sizes and lower power consumption. Therefore, it is impossible for high power-consumption semiconductor memory devices to be used for small-sized or portable-sized systems, such that commercial viability thereof is greatly decreased. A leakage current encountered in products (such as mobile phones) that have low power-consumption as important elements for high product competitiveness is directly associated with such product competitiveness. 
       BRIEF SUMMARY OF THE INVENTION 
       [0016]    Various embodiments of the present invention are directed to providing a driving device that substantially obviates one or more problems due to limitations and disadvantages of the related art. 
         [0017]    The embodiment of the present invention relates to a driving device for controlling a power source of a pre-driver during a standby mode such that it can reduce a channel-off leakage current of a transistor at the last output end of a driver. 
         [0018]    In accordance with an embodiment of the present invention, a driving device includes: a pre-driver configured to output a drive control signal upon receiving a power-supply voltage in response to an input signal, and change a voltage level of the drive control signal in response to a control signal so as to selectively provide the changed voltage level; an output driver configured to receive the power-supply voltage in response to the drive control signal, and output the received power-supply voltage to an output terminal; and a bulk-voltage controller configured to selectively control bulk-voltage levels of the pre-driver and the output driver in response to the control signal. 
         [0019]    It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]    The above and other features and advantages of the present invention will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein: 
           [0021]      FIG. 1  is a block diagram illustrating a data output device according to the related art. 
           [0022]      FIG. 2  is a circuit diagram illustrating a driving device according to embodiments. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0023]    Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. 
         [0024]      FIG. 2  is a circuit diagram illustrating a driving device according to embodiments. 
         [0025]    Referring to  FIG. 2 , the driving device according to the embodiments includes a pre-driver  100 , an output driver  200 , a bulk-voltage controller  300 , and a control signal generator  400 . 
         [0026]    The pre-driver  100  receives a power-supply voltage in response to input signals (IN 1 , IN 2 ) so that the pre-driver  100  outputs a drive control signal to the output driver  200 . The output driver  200  activates data in response to the drive control signal, and outputs the resultant data to an output terminal (DQ). The bulk-voltage controller  300  controls bulk-voltage levels of the pre-driver  100  and the output driver  200  in response to control signals (PDD_DD, PDB_DD). In addition, the control signal generator  400  inverts and delays the control signal PD_DD, such that the control signal generator  400  outputs control signals (PDB_DD, PDD_DD). 
         [0027]    The pre-driver  100  includes a pull-up pre-driver  110 , a pull-down pre-driver  120 , a pull-up power controller  130 , a pull-down power controller  140 , and a pull-down controller  150 . 
         [0028]    In some embodiments, the pull-up pre-driver  110  includes a PMOS transistor P 1  and an NMOS transistor N 1 . The PMOS transistor P 1  and the NMOS transistor N 1  are coupled in series between a power-source node (VDDQUP) and a ground voltage (VSSQ) input terminal. The PMOS transistor P 1  and the NMOS transistor N 1  receive an input signal IN 1  through a common gate terminal. The PMOS transistor P 1  receives a pull-up bulk voltage (VBULK_P) through a bulk terminal, and the NMOS transistor N 1  receives a pull-down bulk voltage (VBULK_N) through a bulk terminal. The PMOS transistor P 1  and the NMOS N 1  output a pull-up drive control signal (PU) through a common drain terminal. 
         [0029]    The pull-down pre-driver  120  includes a PMOS transistor P 5  and an NMOS transistor N 2 . The PMOS transistor P 5  and the NMOS transistor N 2  are coupled in series between a power-source node (VDDQDN) and a ground node (VSSQDN). The PMOS transistor P 5  and the NMOS transistor N 2  receive an input signal IN 2  through a common gate terminal. The PMOS transistor P 5  receives a pull-up bulk voltage (VBULK_P) through a bulk terminal, and the NMOS transistor N 2  receives a pull-down bulk voltage (VBULK_N) through a bulk terminal. 
         [0030]    The pull-up power controller  130  includes a plurality of PMOS transistors P 2 ˜P 4  acting as pull-up drive elements. The PMOS transistor P 2  is coupled between a power-supply voltage (VDDQ) input terminal and a power-source node (VDDQUP), so that the PMOS transistor P 2  receives a control signal (PDD_DD) through a gate terminal. The PMOS transistor P 2  receives a pull-up bulk voltage (VBULK_P) through a bulk terminal. The PMOS transistors (P 3 , P 4 ) are coupled in series between the power-supply voltage (VDD 1 ) input terminal and the power-source node (VDDQUP). A gate terminal and a drain terminal of the PMOS transistor P 3  are commonly coupled to each other. A gate terminal of the PMOS transistor P 4  receives a control signal (PDB_DD). In addition, the PMOS transistors (P 3 , P 4 ) are configured to receive a power-supply voltage VDD 1  through a bulk terminal. 
         [0031]    The pull-down power controller  140  includes a plurality of PMOS transistors P 6 ˜P 8  acting as pull-up drive elements. The PMOS transistor P 6  is coupled between a power-supply voltage (VDDQ) input terminal and a power-source node (VDDQDN), so that the PMOS transistor P 6  receives a control signal (PDD_DD) through a gate terminal. The PMOS transistor P 6  receives a pull-up bulk voltage (VBULK_P) through a bulk terminal. The PMOS transistors (P 7 , P 8 ) are coupled in series between the power-supply voltage (VDDQ) input terminal and the power-source node (VDDQDN). A gate terminal and a drain terminal of the PMOS transistor P 7  are commonly coupled to each other. A gate terminal of the PMOS transistor P 8  receives a control signal (PDB_DD). In addition, the PMOS transistors (P 7 , P 8 ) are configured to receive a pull-up bulk voltage (VBULK_P) through a bulk terminal. 
         [0032]    The pull-down controller  150  includes NMOS transistors (N 3 , N 4 ) acting as pull-down drive elements. The NMOS transistor N 3  is coupled between a ground node (VSSQDN) and a ground voltage (VSSQ) input terminal. The NMOS transistor N 3  receives a control signal (PDB_DD) through a gate terminal. The NMOS transistor N 4  is coupled between the ground node (VSSQDN) and a back-bias voltage (VBBN) input terminal, such that the NMOS transistor N 4  receives a control signal (PDD_DD) through a gate terminal. The NMOS transistors (N 3 , N 4 ) are configured to receive a pull-down bulk voltage (VBULK_N) through a bulk terminal. 
         [0033]    In accordance with the embodiments, a channel-off leakage current in the standby mode may occur in a PMOS transistor P 9  and an NMOS transistor N 5 . In order to prevent the channel-off leakage current of the PMOS transistor P 9  and the NMOS transistor N 5 , the PMOS transistor P 9  and the NMOS transistor N 5  receive different levels of voltage from the pre-driver  100  serving as a previous stage of the output driver  200 . 
         [0034]    In addition, the output driver  200  includes a pull-up driver  210  and a pull-down driver  220 . 
         [0035]    In some embodiments, the pull-up driver  210  includes a PMOS transistor P 9  serving as a pull-up drive element. The PMOS transistor P 9  is coupled between the power-supply voltage (VDDQ) input terminal and the output terminal (DQ), and receives a pull-up drive control signal (PU) through a gate terminal. The PMOS transistor P 9  receives a pull-up bulk voltage (VBULK_P) through a bulk terminal. 
         [0036]    The pull-down driver  220  includes an NMOS transistor N 5  serving as a pull-down drive element. The NMOS transistor N 5  is coupled between the output terminal (DQ) and the ground voltage (VSSQ) input terminal, such that the NMOS transistor N 5  receives a pull-down drive control signal (PD) through a gate terminal. The NMOS transistor N 5  receives a pull-down bulk voltage (VBULK_N) through a bulk terminal. 
         [0037]    The bulk-voltage controller  300  includes a pull-up controller  310  and a pull-down bulk controller  320 . 
         [0038]    The pull-up bulk controller  310  includes PMOS transistors (P 10 , P 11 ) serving as pull-up drive elements. The PMOS transistor P 10  is coupled between the power-supply voltage (VDDQ) input terminal and the pull-up bulk voltage (VBULK_P) output terminal, such that PMOS transistor P 10  receives a control signal (PDD_DD) through a gate terminal. The PMOS transistor P 10  receives the pull-up bulk voltage (VBULK_P) through a bulk terminal. The PMOS transistor P 11  is coupled between the power-supply voltage (VDD 1 ) input terminal and the pull-up bulk voltage (VBULK_P) output terminal, such that the PMOS transistor P 11  receives a control signal (PDB_DD) through a gate terminal. The PMOS transistor P 11  receives the power-supply voltage (VDD 1 ) through a bulk terminal. 
         [0039]    The pull-down bulk controller  320  includes NMOS transistors (N 6 , N 7 ) serving as pull-down drive elements. The NMOS transistor N 6  is coupled between the pull-down bulk voltage (VBULK_N) output terminal and the ground voltage (VSSQ) input terminal, such that the NMOS transistor N 6  receives a control signal (PDB_DD) through a gate terminal. The NMOS transistor N 6  receives the pull-down bulk voltage (VBULK_N) through a bulk terminal. The NMOS transistor N 7  is coupled between the pull-down bulk voltage (VBULK_N) output terminal and the back-bias voltage (VBBN) input terminal, such that the NMOS transistor N 7  receives a control signal (PDD_DD) through a gate terminal. The NMOS transistor N 7  receives the back-bias voltage (VBBN) through a bulk terminal. 
         [0040]    The back-bias voltage pumping unit  330  is configured to pump the back-bias voltage (VBBN), such that the back-bias voltage pumping unit  330  outputs the back-bias voltage (VBBN) to a source terminal and a bulk terminal of the NMOS transistor N 7 . 
         [0041]    The control signal generator  400  includes a plurality of inverters (IV 1 , IV 2 ). The inverter IV 1  is driven in response to the power-supply voltage (VDD 1 ) and the back-bias voltage (VBBN), and inverts the control signal (PD_DD) so as to output the other control signal (PDB_DD). The inverter IV 2  is driven in response to the power-supply voltage (VDD 1 ) and the back-bias voltage (VBBN), and inverts the control signal (PDB_DD) so as to output the other control signal (PDD_DD). 
         [0042]    The operations of the above-mentioned driving device according to the embodiments will hereinafter be described in detail. 
         [0043]    In accordance with the embodiments, a power source of the pre-driver  100  is changed to another power source during a standby mode. That is, a negative bias is applied to the output driver  200  without loss of slew of the pre-driver  100 , and a bulk voltage of each of the pre-driver  100  and the output driver  200  is increased such that an off-leakage current can be reduced. 
         [0044]    If the input signals (IN 1 , IN 2 ) are at a high level during a normal operation mode, the NMOS transistor N 1  of the pull-up pre-driver  110  and the NMOS transistor N 2  of the pull-down pre-driver  120  are turned on. Accordingly, the pull-up drive control signal (PU) and the pull-down drive control signal (PD) are at a low level. 
         [0045]    As a result, the PMOS transistor P 9  of the pull-up driver  210  is turned on, and the NMOS transistor N 5  of the pull-down driver  220  is turned off. If the pull-up driver  210  starts operation, the power-supply voltage (VDDQ) is applied to the output terminal (DQ) such that the pull-up driver  210  outputs high data. 
         [0046]    In contrast, if the input signals (IN 1 , IN 2 ) are at a low level, the PMOS transistor P 1  of the pull-up pre-driver  110  and the PMOS transistor P 5  of the pull-down pre-driver  120  are turned on. Therefore, the pull-up drive control signal (PU) and the pull-down drive control signal (PD) are at a high level. 
         [0047]    As a result, the PMOS transistor P 9  of the pull-up driver  210  is turned off, and the NMOS transistor N 5  of the pull-down driver  220  is turned on. If the pull-down driver  220  starts operation, the ground voltage (VSSQ) is applied to the output terminal (DQ) such that the pull-down driver  220  outputs low data. 
         [0048]    If the above-mentioned IC driver operates in the normal operation mode, the IC driver adjusts the pull-up and pull-down slew rates of data according to whether transistors of the pull-up pre-driver  110  and the pull-down pre-driver  120  are turned on or off. If the IC driver is in the standby mode, the PMOS transistor P 9  of the pull-up driver  210  and the NMOS transistor N 5  of the pull-down driver  220  are turned off, so that no current flows in the output terminal (DQ). 
         [0049]    However, as a mobile device is configured to use a low power-supply voltage, transistor characteristics are rapidly deteriorated, such that an off-leakage current of each transistor may occur in the pull-up driver  210  and the pull-down driver  220 . In addition, assuming that each of the PMOS transistor P 9  and the NMOS transistor N 5  contained in the output driver  200  acting as the last output end has a large channel width, an off-leakage current may occur in PMOS transistor P 9  and NMOS P 5  during the standby mode. 
         [0050]    In order to reduce the off-leakage current, the embodiments may control (i.e., change) a source power of the pull-up pre-driver  110  using the pull-up power controller  130 , and may control (i.e., change) a source power of the pull-down pre-driver  120  using the pull-down power controller  140 . 
         [0051]    That is, the control signal (PD_DD) is at a low level state during the normal operation mode. The control signal (PD_DD) transitions to a high level during a power-down mode, and transitions to a low level during the normal operation mode. 
         [0052]    If the normal mode starts operation, the control signal (PD_DD) transitions to a low level. The control signal (PDB_DD) is an inversion signal of the control signal (PD_DD). As a result, during the normal operation mode, the control signal (PDB_DD) is at a high level so that the control signal (PDB_DD) has a power-supply voltage (VDD 1 ) level, and the other control signal (PDD_DD) is at a low level so that the control signal (PDD_DD) has a back-bias voltage (VBBN) level. 
         [0053]    Accordingly, during the normal operation mode, the PMOS transistor P 2  of the pull-up power controller  130  is turned on, and the PMOS transistor P 4  of the pull-up power controller  130  is turned off. As a result, a power node (VDDQUP) is at a power-supply voltage (VDDQ) level during the normal operation mode. 
         [0054]    On the other hand, the control signal (PD_DD) transitions to a high level during the standby mode. During the standby mode, the control signal (PDB_DD) is at a low level so that it has a back-bias voltage (VBBN) level, and the other control signal (PDD_DD) is at a high level so that it has a power-supply voltage (VDD 1 ) level. 
         [0055]    Accordingly, during the standby mode, the PMOS transistor P 2  of the pull-up power controller  130  is turned off, and the PMOS transistor P 4  of the pull-up power controller  130  is turned on. The PMOS transistor P 3  is configured to provide a power-supply voltage (VDD 1 T) to a power node of the PMOS transistor P 4 . The PMOS transistor P 4  is configured to provide a power-supply voltage (VDD 1 T) to a power node (VDDQUP). As a result, the power node (VDDQUP) is at the power-supply voltage (VDD 1 T) level during the standby mode. In one example, the power-supply voltage (VDD 1 T) is identical to a voltage level obtained when a threshold voltage of the PMOS transistor P 3  is subtracted from the power-supply voltage (VDD 1 ). The power-supply voltage (VDD 1 T) is higher than the other power-supply voltage (VDDQ). 
         [0056]    If the power-supply voltage (VDD 1 ) is at a very high level, a faulty operation may occur in the pull-up pre-driver  110 , such that the PMOS transistor P 3  is needed for reducing the power-supply voltage (VDD 1 ) level. Assuming that the power-supply voltage (VDD 1 ) level can be stably controlled, the driving device of the embodiments may be designed not to include the PMOS transistor P 3 . 
         [0057]    As described above, if the driving device of the embodiments operates in the normal mode, the power-supply voltage (VDDQ) is used as a source power of the pull-up pre-driver  110 . If the driving device of the embodiments operates in the standby mode, the power-supply voltage (VDD 1 T) higher than the other power-supply voltage (VDDQ) is used as a source power of the pull-up pre-driver  110 . If the voltage level of the pull-up drive control signal (PU) becomes higher, a negative bias is applied to a gate terminal of the PMOS transistor P 9 , such that an off-leakage current of the PMOS transistor P 9  can be reduced. 
         [0058]    Likewise, during the normal operation mode, the PMOS transistor P 6  of the pull-down power controller  140  is turned on, and the PMOS transistor P 8  of the pull-down power controller  140  is turned off. Accordingly, the power node (VDDQDN) is at a power-supply voltage (VDDQ) level during the normal operation mode. 
         [0059]    During the normal operation mode, the NMOS transistor N 3  of the pull-down controller  150  is turned on. Accordingly, the ground node (VSSQDN) is at a ground voltage (VSSQ) level. 
         [0060]    During the standby mode, the PMOS transistor P 6  of the pull-down power controller  140  is turned off, and the PMOS transistor P 8  of the pull-down power controller  140  is turned on. The PMOS transistor P 7  provides a power-supply voltage (VDD 1 TQ) to a node of the PMOS transistor P 8 . As a result, the power node (VDDQDN) is at a power-supply voltage (VDD 1 TQ) level during the standby mode. In this case, the power-supply voltage (VDD 1 TQ) is identical to a voltage level obtained when a threshold voltage of the PMOS transistor P 7  is subtracted from the power-supply voltage (VDDQ). The power-supply voltage (VDD 1 TQ) is lower than the other power-supply voltage (VDDQ). 
         [0061]    If the power-supply voltage (VDDQ) is at a very high level, a faulty operation may occur in the pull-down pre-driver  120 , such that the PMOS transistor P 7  is needed for reducing the power-supply voltage (VDDQ) level. Assuming that the power-supply voltage (VDDQ) level can be stably controlled, the driving device of the embodiments may be designed not to include the PMOS transistor P 7 . 
         [0062]    During the standby mode, the NMOS transistor N 4  of the pull-down controller  150  is turned on. Accordingly, the ground node (VSSQDN) is at a back-bias voltage (VBBN) level. In this case, the back-bias voltage (VBBN) is lower than the ground voltage (VSSQ). 
         [0063]    As described above, if the driving device of the embodiments operates in the normal mode, the power-supply voltage (VDDQ) is used as a source power of the pull-down pre-driver  120 . If the driving device of the embodiments operates in the standby mode, the power-supply voltage (VDD 1 TQ) lower than the other power-supply voltage (VDDQ) is used as a source power of the pull-down pre-driver  120 . In addition, if the driving device is in the standby mode, the back-bias voltage (VBBN) lower than the ground voltage (VSSQ) is used as a drain power of the pull-down pre-driver  120 . 
         [0064]    Therefore, assuming that a voltage level of the pull-down drive control signal (PD) is gradually reduced, a negative bias is applied to a gate terminal of the NMOS transistor N 5 , such that an off-leakage current of the NMOS transistor N 5  can be reduced. 
         [0065]    On the other hand, since the control signal (PDD_DD) is at a low level during the normal operation mode, the PMOS transistor P 10  of the pull-up bulk controller  310  is turned on and the PMOS transistor P 11  is turned off. As a result, the pull-up bulk voltage (VBULK_P) is at the power-supply voltage (VDDQ) level. That is, during the normal operation mode, the power-supply voltage (VDDQ) is applied to the pull-up driver  210 , and a voltage equal to the power-supply voltage (VDDQ) is applied to the bulk terminal of PMOS transistor P 9  in the form of the pull-up bulk voltage (VBULK_P). 
         [0066]    In addition, during the normal operation, the control signal (PDB_DD) is at a high level, such that the NMOS transistor N 6  of the pull-down bulk controller  320  is turned on and the NMOS transistor N 7  of the pull-down bulk controller  320  is turned off. As a result, the pull-down bulk voltage (VBULK_N) is at the ground voltage (VSSQ) level. That is, during the normal operation mode, the ground voltage (VSSQ) level applied to the pull-down driver  220 , and a voltage equal to the ground voltage (VSSQ) level is applied to the bulk terminal of the NMOS transistor N 5  in the form of the pull-down bulk voltage (VBULK_N). 
         [0067]    On the other hand, during the standby mode, the control signal (PDB_DD) is at a low level, so that the PMOS transistor P 10  of the pull-up bulk controller  310  is turned off and the PMOS transistor P 11  of the pull-up bulk controller  310  is turned on. As a result, the pull-up bulk voltage (VBULK_P) is at a power-supply voltage (VDD 1 ) level. That is, during the standby mode, the power-supply voltage (VDD 1 ) higher than the power-supply voltage (VDDQ) applied to the pull-up driver  210  is applied to the bulk terminal of the PMOS transistor P 9 . 
         [0068]    In addition, during the standby mode, since the control signal (PDD_DD) is at a high level, the NMOS transistor N 6  of the pull-down bulk controller  320  is turned off and the NMOS transistor N 7  of the pull-down bulk controller  320  is turned on. As a result, the pull-down bulk voltage (VBULK_N) is at the back-bias voltage (VBBN) level. That is, during the standby mode, the ground voltage (VSSQ) applied to the pull-down driver  220  and the low back-bias voltage (VBBN) is applied to the bulk terminal of the NMOS transistor N 5 . 
         [0069]    During the standby mode, the pull-up pre-driver  110 , the pull-down pre-driver  120 , the pull-down power controller  140 , and the pull-down controller  150  may receive the pull-up bulk voltage (VBULK_P) and the pull-down bulk voltage (VBULK_N) through bulk terminals. Therefore, during the standby mode, transistors of the pull-up pre-driver  110 , the pull-down pre-driver  120 , the pull-down power controller  140 , and the pull-down controller  150  are prevented from being unnecessarily turned on. However, the pull-up power controller  130  receives the pull-up bulk voltage (VBULK_P) through a bulk terminal of the PMOS transistor P 2 , and receives the power-supply voltage (VDD 1 ) through the PMOS transistors (P 3 , P 4 ). 
         [0070]    In accordance with the above-mentioned embodiments, currents (IDD 2 P, IDD 3 P, IDD 6 ), a current of the output terminal, or a Deep Power Down (DPD) current can be reduced. Specifically, the above-mentioned embodiments can be efficiently applied to a mobile DRAM or DDR 4  configured to use heterogeneous power-supply voltages (such as VDD 1  and VDD 2 ), or can also be efficiently applied to other devices (such as X32 and X64) having a large number of output pins 
         [0071]    As is apparent from the above description, the driving device according to the embodiments controls a power source of a pre-driver during a standby mode, such that the driving device reduces a channel-off leakage current of a transistor at the last output end of a driver. 
         [0072]    Those skilled in the art will appreciate that the present invention may be carried out in other specific ways than those set forth herein without departing from the spirit and essential characteristics of the present invention. The above exemplary embodiments are therefore to be construed in all aspects as illustrative and not restrictive. The scope of the invention should be determined by the appended claims and their legal equivalents, not by the above description, and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein. Also, it is obvious to those skilled in the art that claims that are not explicitly cited in each other in the appended claims may be presented in combination as an example embodiment of the present invention or included as a new claim by a subsequent amendment after the application is filed. 
         [0073]    Although a number of illustrative embodiments consistent with the invention have been described, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. Particularly, numerous variations and modifications are possible in the component parts and/or arrangements which are within the scope of the disclosure, the drawings and the accompanying claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.