Abstract:
Combining integrated injection logic (I 2  L) and linear circuitry permits fabrication of a highly dense analog-to-digital (A-to-D) converter. The heart of the A-to-D converter is a linear-I 2  L plurality of high density variable current sources which are proportional to each other. These variable current sources, when used in combination with I 2  L constant current sources and current sensing means, provide a highly compact A-to-D converter.

Description:
This is a continuation of application Ser. No. 836,632, filed Sept. 26, 1977 now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates, in general, to analog-to-digital converters, and more particularly, to monolithic integrated analog-to-digital converters having I 2  L-linear circuitry and method of making same. 
     Analog-to-digital (A-to-D) converters are widely used in the electronics industry for quantizing analog voltages to discrete levels thereby permitting further processing utilizing digital circuitry. In the past, this A-to-D conversion has often presented troublesome design problems, and many schemes for performing this conversion have been set forth in the electronics literature. Furthermore, these A-to-D converters, when compared with other portions of most digital processing circuitry, are generally complicated, involving several device types. As a result, an integrated A-to-D converter tends to use a large amount of semiconductor substrate area in comparison to the rest of the digital processing circuitry. 
     Therefore, it can be appreciated that an A-to-D converter which is simple in concept, requiring only a few devices, and requiring a relatively small area on a semiconductor chip is highly desirable. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of this invention to provide a method for constructing an improved integrable analog-to-digital converter which is relatively simple in concept. 
     It is also an object of this invention to provide highly compact variable current sources. 
     It is another object of this invention to provide an integrable A-to-D converter which consists of relatively few electronic devices. 
     Yet another object of this invention is to provide an integrable A-to-D converter which utilizes high density integrated injection logic (I 2  L) current sources in combination with linear circuitry. 
     It is also an object of this invention to provide an integrable A-to-D converter which requires a minimal amount of semiconductor chip area. 
     An illustrated embodiment of the invention provides a highly compact analog-to-digital converter having an analog input terminal and a plurality of binary output terminals comprising, first, a plurality of fixed current sources. In addition, a like number of variable current sources, each one coupled to one of the fixed current sources to form a fixed-variable current source pair with each of the variable current sources capable of passing current at a fixed ratio to each other. Also provided is a means for varying the current passing through each of the variable current sources in response to an analog input voltage at the analog input terminal, means for sensing the relative currents from the fixed current source and the variable current source in each of the fixed-variable current pairs, and means for indicating at the output terminals in a binary format whether the current capacity of the fixed current source is greater or less than the capacity of the variable current source in each of the fixed-variable current source pairs. 
     Also provided is a method for producing a highly compact analog-to-digital converter having an analog input terminal and a plurality of binary output terminals which comprises the steps of, first, providing a substrate into which is deposited a plurality of I 2  L gates, each gate having a fixed injection current, an input node, and at least one output node wherein the output nodes form the binary output terminals. Also deposited into the substrate is a plurality of high density variable current sources, each having a fixed current ratio with respect to each other, and each having an output node which is coupled to the input node of the I 2  L gates to selectively enable each of the I 2  L gates as determined by the current of each of the current sources. A region is deposited in the substrate comprising linear circuitry for receiving an analog input signal at the analog input terminal and for varying the current capacity of the high density variable current sources in response to the analog input signal to cause an analog-to-digital conversion of the input signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of an embodiment of an A-to-D converter; and 
     FIG. 2 is a representation of a circuit layout on a monolithic semiconductor substrate to produce the circuit shown in FIG. 1. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Now referring to FIG. 1, input terminal 10 for receiving an analog voltage is connected to the input of an analog voltage to analog current linear transformation circuit 11. For illustrative purposes, a crude linear transformation circuit 11 is shown as PNP transistor 12 and resistor 14. Input terminal 10 is connected to the base of PNP transistor 12, the emitter of which is connected to resistor 14 which, in turn, is connected to a positive DC supply voltage, V CC , at terminal 16. The collector of transistor 12 is, in turn, connected to the collector of NPN transistor 18 and also to the base of NPN transistor 20. Transistor 18 has a common base with transistors 22, 24, 26, 28, 30, 32, 34, 36, and 38, and also has an emitter in common with these transistors which is connected to ground or a reference potential. The collector of transistor 20 is connected to V CC  and the emitter is connected to the base of transistor 18. The collector of transistor 22 is connected to the collector of PNP fixed current source transistor 40 and also to the base of NPN output transistor 42. In a similar manner, the collector of transistor 24 is connected to the collector of PNP fixed current source transistor 44 and to the base of output transistor 46; the collector of transistor 26 is connected to the collector of PNP fixed current source transistor 48 and to the base of NPN output transistor 50; the collector of transistor 28 is connected to the collector of PNP fixed current source transistor 52 and the base of NPN output transistor 54; the collector of transistor 30 is connected to the collector of PNP fixed current source transistor 56 and to the base of NPN output transistor 58; the collector of transistor 32 is connected to the collector of PNP fixed current source transistor 60 and to the base of NPN output transistor 62; the collector of transistor 34 is connected to the collector of PNP fixed current source transistor 64 and to the base of NPN output transistor 66; the collector of transistor 36 is connected to the collector of PNP fixed current source transistor 68 and to the base of NPN output transistor 70; and the collector of transistor 38 is connected to the collector of PNP fixed current source transistor 72 and to the base of NPN output transistor 74. PNP fixed current source transistors 40, 44, 48, 52, 56, 60, 64, 68, and 72 have a common base which is connected to ground and a common emitter which is connected to one side of resistor 76 the other side of which is connected to the positive DC supply voltage, V CC , at terminal 16. Each of NPN output transistors 42, 46, 50, 54, 58, 62, 66, 70, and 74 have a common emitter connection which is connected to ground, and the collectors of each of the respective transistors form the nine digital output terminals of the A-to-D converter. 
     In operation, an analog voltage at input terminal 10 controls, via the linear voltage to current transformation circuit 11 which, in turn, determines the current through transistor 18, the magnitude of which is reflected into each of the variable current source transistors 22, 24, 26, 28, 30, 32, 34, 36, and 38. That is, the current in the collector of transistor 18 is mirrored in a proportional amount by each of the variable current source transistors. Transistor 20 acts as a buffer and current amplifier to provide sufficient base drive for each of the variable current source transistors and minimize loading on the collector current of transistor 18. Also, each of the variable current source transistors have a proportionate amount of current sinking capability such that if transistor 38 is sinking one unit of current, transistor 36 will have a two unit capability, transistor 34 will have a three unit capability, transistor 32 will have a four unit capability, transistor 30 will have a five unit capability, transistor 28 will have a six unit capability, transistor 26 will have a seven unit capability, transistor 24 will have an eight unit capability, and transistor 22 will have a nine unit capability. Supplying current to these variable current sources is a series of fixed current sources comprised of transistors 40, 44, 48, 52, 56, 60, 64, 68, and 72. These transistors, together with resistor 76, which determines the amount of injector current for the fixed current sources, provide a fixed current for each of the variable current sources and for output transistors 42, 46, 50, 54, 58, 62, 66, 70, and 74. Each of the fixed current sources is paired with one of the variable current source transistors to form a fixed and variable current source pair. When the current supplied by the fixed current source is greater than the current being absorbed by the variable current source by an amount sufficient to provide enough base drive to force the output transistor into saturation, then the output transistor will pull an output voltage low. However, as the variable current source capability increases to become greater than that current supplied by the fixed current source, then the output transistor will be robbed of its base drive and will be unable to sink an output load (not shown). When the analog input voltage at terminal 10 is at a high level, the output current of circuit 11 will be zero, demonstrated by the current cut off of transistor 12. Since the collector current of transistor 18 is reduced to zero, none of the variable current sources transistors will be conducting, and each of the fixed current sources will be supplying current to the base of the nine output transistors. Thus, each of output terminals 77, 78, 80, 82, 84, 86, 88, 90, and 92 will be at the low voltage state. As the analog voltage at terminal 10 decreases to, in turn increase the output current of circuit 11 by bringing transistor 12 into conduction and supply more current to the collector of transistor 18, then the variable current sources will start to conduct and at some point each of the variable current sources will be able to sink more current than that which can be supplied by the fixed current source, and the respective output transistor will be cut off thereby allowing the output terminal to go high. Since the current capability of variable current source transistor 22 is the greatest for a given collector current in transistor 18, output transistor 42 will be the first to turn off and output terminal 77 will go high before the rest of the output terminals change state. In a like manner, each of output terminals 78, 80, 82, 84, 86, 88, 90, and 92 will go to the high digital state in a domino sequence as the analog voltage at input terminal 10 varies over the range of the A-to-D converter. Thus, the A-to-D converter has a ten state capability in that a high input voltage at terminal 10 will cause all the output transistors to be conducting, and as the input voltage decreases output transistors 42, 46, 50, 54, 58, 62, 66, 70, and 74 will become nonconducting in sequence until the lower limit of the A-to-D converter is reached wherein all the output transistors will be nonconducting. 
     Thus, it is seen that the A-to-D conversion is accomplished with relatively few devices in a straightforward, uncomplicated manner. 
     FIG. 2 is a diagram of the layout on a monolithic semiconductor substrate of the circuit of FIG. 1. The diagram indicates the combination of integrated injection logic (I 2  L) together with conventional linear circuitry. On a monolithic P-type substrate an N-type epitaxial layer 93 is grown and P-type isolation regions 94 are diffused into the epitaxial layer to isolate each of the circuit types. Two areas of isolated N-region shown as regions 96 and 98 form resistors 14 and 76 of FIG. 1, respectively. The fixed current source transistors are formed in area 100 using conventional I 2  L techniques. That is, the current source transistors are lateral PNPs and the output transistors are vertical NPNs incorporated into the same area with their collectors up (i.e., the collector region is the normal emitter region of conventional vertical transistors) and operate in the inverted beta mode. Thus, the emitters of the fixed current source transistors are P diffusions 102 in region 100 and the collectors of the fixed current source transistors are a second set of P diffusion regions 104. Elongated N+ diffusion 106 is diffused into epi region 93 to form a contact with the base region of the fixed current source transistors. This base region also serves as the emitters for the output transistors. P regions 104 which form the collectors for the fixed current source transistors also function as the bases for the output transistors, and N+ regions 108 are diffused into the P regions 104 to form the collectors for the output transistors. N region 98, as a resistor, determines the amount of fixed injector current into all of the fixed current sources of region 100. This construction is conventional in the art and well known to anyone skilled in I 2  L fabrication. Similarly, input transistor 12 of FIG. 1 is a lateral PNP transistor of conventional linear circuitry and diffused in the same manner as the upper fixed current source transistors. This input transistor is formed in region 110 and fabricated in the same manner and at the same time as region 100 so that the input transistor and the fixed current source transistors have matching operating characteristics. 
     Input terminal 10 of FIG. 1 is connected to N+ diffusion region 112 and thereby to the base of transistor 12 formed in area 110. The variable current source transistors are formed in region 114, again using I 2  L fabrication techniques. That is, the collector of the transistors are up in the normal emitter position of conventional transistors and the device thus has inverse beta characteristics. However, this I 2  L construction permits the ratioing of a collector area for each of the variable current source transistors. Thus, the transistors share a common emitter, shown as elongated N+ diffusion region 116, and also a common base region of P-type material of region 118. However each of the transistors have a separate collector region which have collector-to-base contact areas in proportion to each other. Thus, the collector of transistor 38, in FIG. 1, is represented by N+ region 120 of FIG. 2. In a like manner, the collectors of transistors 36, 34, 32, 30, 28, 26, 24, and 22 of FIG. 1 are shown as N+ areas 122, 124, 126, 128, 130, 132, 134, and 136 of FIG. 2, respectively. As can be seen from the collector areas of FIG. 2, the collector-to-base contact area and, thus, the relative current carrying capability for each of the variable current source transistors is proportional to each other with area 120 being equal to one-half of area 122 of transistor 36. In a like manner, area 120 is one-third, one-fourth, one-fifth, one-sixth, one-seventh, one-eighth, and one-ninth of each of other areas 124, 126, 128, 130, 132, 134, and 136, respectively. Finally, region 138 represents transistor 20 of FIG. 1 and is a conventional NPN vertical transistor and thus provides conventional beta characteristics to supply current as base drive for each of the variable current source transistors. The collector contact of transistor 20 of FIG. 1 is comprised of N+ region 140 and the base is comprised of P diffusion 142, and the emitter of N+ diffusion 144. It is also possible to diffuse on the same substrate a linear isolation amplifier to drive input terminal 10 and to further realize the advantage of combining I 2  L and linear devices on a common substrate. 
     Since resistors 14 and 76 of FIG. 1 and 96 and 98 of FIG. 2 are formed in the same manner, they will initially have substantially the same operating characteristics and will substantially track each other over temperature. Also, PNP input transistor 12 of FIG. 1 is formed in the same manner as PNP fixed current source transistors 40, 44, 48, 52, 56, 60, 64, 68, and 72, they will have essentially identical characteristics, both initially and over temperature. Thus, the current through the variable current sources and the fixed current sources will be essentially at a fixed ratio to each other, independent of process variations and environmental changes. 
     Although in the preferred embodiment the fixed current sources each have the same current sourcing capability, it will be understood by those skilled in the art that it would be possible to also ratio the collector-to-base contact area of the fixed current source transistors to vary the current from each of these sources. 
     It will also be understood by those skilled in the art that the analog voltage to analog current linear transformation circuit 11 may be any of the various types of such circuits, and that the linear transformation circuit 11, shown as PNP transistor 12 and resistor 14 in the preferred embodiment, is by way of example only. 
     This circuit construction, using I 2  L techniques in combination with linear circuitry, results in a considerable savings of chip area on a semiconductor substrate. The variable current sources region of area 114 results in a significant savings as compared to the same variable current sources implemented using conventional transistors which ratio the emitter-to-base contact area. Also, the combination of the fixed current source transistors and the output transistors into single region 100 results in more savings of semiconductor substrate area. In addition since the N regions for both the variable and fixed current sources are grounded, they could be constructed in one common N region. 
     While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes may be made therein without departing from the teachings of the invention. Therefore, it is intended in the appended claims to cover all such equivalent variations as come within the spirit and scope of the invention.