Abstract:
An interface for a color image signal processing system is implemented with a common input/output data lines to reduce the number of pin-counts of a integrated circuit. The input control protocol is shared with the data output and selected by an &#34;Output Enable&#34; signal, which also acts as a synchronization control signal.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to an interface architecture especially an interface protocol used for analog signal image signal processor. 
     Recently, the performance progress in personal computer (PC) has been becoming more powerful in either CPU processing speed or data storage ability. Also the worldwide Internet effectively reduces the distance between people. All of these factors have created a strong demand in color image processing system, such as desktop scanners, sheet feed scanners, handy scanners, electronic cameras, bar-code readers, etc. 
     Conventionally, an imaging system controller uses a complicated serial or parallel interface protocol to control the signal processing operation. The digital image data of analog signal processor are outputted to a parallel port. The number of data output ports depends on the resolution of the analog-to-digital converter. For high resolution image processing systems, the digital data output must allocate a large number of pins of a package to translate its correlated analog image pixel signal, such that the total analog image signal processor cost is dominated by the chip size of data output pads, which are limited, and the cost of high pin-count package. 
     SUMMARY OF THE INVENTION 
     An object of this invention is to use novel interface control for analog processing to reduce number the chip size of an analog signal processor. Another object of this invention is to reduce the number of pin-counts of an image processing integrated circuit. Still another object of this invention is to simplify design interface control between system controller and the analog signal processor. 
     These objects are achieved by the use of an interface architecture between a system controller and an analog signal processor. Common input/output data terminals are shared to reduce the number of pin-counts of the imaging IC. The input/output operation is controlled by an Output Enable (OE) signal. Correlated double sampling (CDS) can abstract the signal offset error of the incoming signal. The programmable gain amplifier (PGA) adjustment can improve the color balance of the different color image signals due to uneven illumination, RGB (red, green, blue) filter mismatch, etc. An analog multiplexer selects the signal channel to be processed. A 12-bit or 10-bit analog-to-digital converter is used for different resolution processing. A digital multiplexer is used to select the digital image data output dispatch format. 
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
     FIG. 1 shows the block diagram of an image capture system of the present invention. 
     FIG. 2 shows the timing diagram of the system. 
     FIG. 3 shows the detailed pixel timing of the analog processor. 
     FIG. 4 shows the timing diagram of the Configuration Register Read/Write, Color Mode Bit Setting using Continuous Serial Clock SCLK (16-bit word). 
     FIG. 5A shows the functional block diagram; FIG. 5B shows its in assignment; FIG. 5C shows another version of the functional block. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 shows the block diagram of an interface control used in the image processing system of this invention. The system controller provides timing control to the image sensor which generates the correlated analog image signal. The analog processor translates the analog image signal into digital output data according to the resolution of the analog-to-digital converter (ADC) used. This digital image data are transferred to the system controller via a novel proposed interface. The system controller also communicates with the analog signal processor and image sensor by the same novel interface. 
     The interface used in the image processing system in this invention adopts the timing as shown in FIG. 2 as the scanning timing control, the dummy pixel and optical black pixel timing for the clamp and Sample-and-Hold control. System controller uses the OE (Output Enable) signal to distinguish the data bus input/output direction and the synchronization signal of the image sensor line. When OE signal is high, the system controller can control the analog signal processor through the data bus D0-D5, while the image sensor clears the residue analog image charge. When OE is low, the data bus D0-D5 turn into output port to output the digital image data to the system controller. Meanwhile, the image sensor starts to expose the document line and to shift out the analog pixel signal of the last exposed line to an analog signal processor by means of a charge control device (CCD). The converted digital image signal can output to the system controller line-by-line or pixel-by-pixel via control command. The converted digital image signal can also generate the required clamp signal (Clamp) and sample-Hold (S/H) signal for analog signal processor to process the incoming analog image signal. 
     Using OE as image sensor synchronization signal, together with Pixel synchronization signal (FSR), the internal clock MCLK slices the time frame for the ADC conversion time and digital image data dispatched format shown in FIG. 3 to save the pin-count of the analog signal processor and system controller by reducing the digital image data output pins. It can dispatch the high resolution ADC digital output data into 2-folds or 3-folds, which save more pin-count, and transfer these folded data between system controller and analog signal processor to save the data transfer pin-count. 
     The input control protocol can also share the data output pin count by the OE signal control. Beside the OE signal for input and output control, an additional CSB (Control for Serial Bus) signal is also used in an input communication mode as synchronization control signal of the serial bus input interface. When CSB changes state from high to low, it means that the serial clock SCLK starts to transmit control data into analog signal processor, according to the first transmitted bit state to distinguish write and read mode. The total CSB occupies 16 SCLK as a 16-bit word transfer. Meanwhile, the color mode bit can also be set by D5-D3 corresponding to b2-b0. The input register read/write control timing of the proposed interface. 
     FIG. 4 shows the timing diagram of the Configuration Register Read/Write (TR/OE), the Color Mode Bit Setting using CSB, and Continuous SCLK (16-bit Word). FIG. 4 also shows the Fast Color Mode Setting using SCB. 
     The control register listed below is an example of the application of the system: 
     Address 00H determines the line-by-line transfer or pixel transfer format, CDS mode, Line Clamp mode, S/H mode, Fast Color mode using through D5-D1 (B2-B0), etc. 
     Address 01H; Configuration Register 
     (Color Mode Bit) 
     b2, b1, b0 000=Monochrome VR (R0, R1, R2, . . . ) 
     001=Monochrome VG (G0, G1, G2, . . . ) 
     010=Monochrome VB (B0, B1, B2, . . . ) 
     011=Bayer R0, G0, R1, R2, G2, B2, . . . ) 
     100=Colormode (R0, G0, B0, R1, R2, G2, B2, . . . ) 
     b3: Data dispatch format setting. 
     Address 02H: S/H reference location setting. 
     Address 03H: S/H pixel location setting. 
     Address 04H: A/D conversion location setting. 
     Address 05H: Clamp start location. 
     Address 06H: Clamp end location. 
     Address 07H: R Gain setting. 
     Address 08H: G Gain setting. 
     Address 09H: B Gain setting. 
     Address 0AH: R Offset setting. 
     Address 0BH: G Offset setting. 
     Address 0CH: B Offset setting. 
     All these control registers can be written into and read back via the proposed novel serial interface between system controller and analog signal processor. It can reduce the needed pin-out of data transfer and save the total system cost. Also, it uses OE as input/output sharing signal and sensor synchronization signal, so as to simplify the system design timing and to increase the system efficiency. 
     FIG. 5A shows the block diagram of analog signal processor and its pin assignment. The analog image signal form the image sensor is inputted to the analog signal processor through VR (Red), VG (Green), VB (Blue) channel. The CDS circuit removes the offset voltage of each color signal. The Gain &amp; Offset Adjust Register PGA fine tunes the signal to its maximum quality. The analog multiplexer (MUX1) selects the processed signal input to the ADC according to the control register command. The high resolution ADC converts the analos input signal into digital image data. The digital multiplexer (MUX2) dispatches the digital image data into 2-folded or 3-folded one to save more pin count. The configuration register controls the operation of the analog signal processor. The control logic communicates with the system controller via the novel interface provided to command the control registers. 
     FIG. 5B shows the terminals of the interface function block. The terminals are: 
     VR, VG, VB: red, blue, green signals 
     VREF: External generated reference voltage 
     VRT: Top voltage reference of the A/D converter 
     VRB: Bottom voltage reference of the A/L) converter 
     AVDD: a positive supply voltage 
     AGND: a ground 
     DVDD: a second positive supply voltage 
     DGND: a second ground 
     MCLK: master clock 
     FSR: Pixel synchronization signal 
     OE: Output enable 
     DO/SDATA: data line #0/Serial Data Input/Output 
     D1/CSB: data line #1/Configuration register Serial Program Enable 
     D2/SCLK: data line #2/Serial Program clock 
     D3/Bo: data line #3/B0 bit setting 
     D4/1: data line #4/B1 bit setting 
     D5/B2: data line #5/B2 bit setting 
     FIG. 5C shows another version of the function block. This architecture is designed for service by line type. MUX1 selects which incoming signal is to be processed. CDS is one set. PGA block is another set but provides three sets of gain and offset registers, depending which color is serviced. The control register has the following addresses: 
     Address 01H: Configuration Register 
     (Color Mode Bit) 
     b2, b1, b0: 000=Monochrome VR (R0, R1, R2, . . . ) 
     001=Monochrmoe VG (G0, G1, G2, . . . ) 
     010=(Monochrome VB (B0, B1, B2, . . . ) 
     b3: Data dispatch format setting 
     b4: CDS mode/ S/H mode 
     b5: Line Clamp Mode 
     b6: Fast Color Mode 
     Address 02H: S/H reference location setting 
     Address 03H: S/H pixel location setting 
     Address 04H: AID conversion location setting 
     Address 05H: Clamp start 
     Address 06H: Clamp end location 
     Address 07H: R Gain setting 
     Address 08H: G Gain setting 
     Address 09H: B Gain setting 
     Address 0AH: R Offset setting 
     Address 0BH: G Offset setting 
     Address 0CH: B Offset setting 
     While the preferred embodiment of the invention has been show and described, it will be apparent to those skilled in this art that various modification may be made in the embodiment without departing from the spirit of the present invention. Such modifications are all within the scope of this invention.