Abstract:
An integrated circuit including at least one low-dropout voltage regulator (LDO) capable of delivering a regulated output voltage using a reference voltage (V REF ), comprises means for generating a substitution voltage (V RMP ) in the form of a ramp and control means capable of replacing the reference voltage (V REF ) by the substitution voltage as long as the said substitution voltage (V RMP ) is lower than the said reference voltage (V REF ).

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is based upon and claims priority from prior French Patent Application No. 04 06883, filed on Jun. 24, 2004, the entire disclosure of which is herein incorporated by reference.  
       FIELD OF THE INVENTION  
       [0002]     The present invention generally relates to low-dropout (LDO) voltage regulators and, more particularly, the control of voltage regulators in the start-up phase.  
       BACKGROUND OF THE INVENTION  
       [0003]     A voltage regulator uses a reference current source and a power supply voltage (battery) in order to deliver a regulated output voltage, in other words a voltage that is independent of the variations in the power supply voltage and of the variations in load, i.e. in the current drawn.  
         [0004]     LDO voltage regulators are particularly suitable where there are small variations in the power supply voltage. For stability, LDO voltage regulators can be connected to an external capacitor mounted in parallel with the load to be supplied by the regulated voltage. When the LDO voltage regulator is turned on, the external capacitor is generally charged up by a relatively high charge current.  
         [0005]     Now, this charge current may cause a voltage drop across the power supply battery, especially where several voltage regulators are connected together across the same power supply battery. Presently, the charge current is limited by generating a current that is the image of the charge current, then comparing this image current with a reference current. However, the limit must be high enough so as not to interfere with the operation of the voltage regulator. This drawback is accentuated by the fact that the image current is not very precise.  
         [0006]     Furthermore, if the start-up of each voltage regulator is to be staggered in order to prevent the drop in voltage of the power supply battery, it then becomes necessary to study in detail the whole circuit in order to precisely define the order in which the various regulators are to be turned on. In addition, the interconnections between the various loads may lead to the appearance of interference-causing currents due to conducting parasitic diodes associated with the various levels of the output voltages of the various regulators during their start-up phase.  
         [0007]     Accordingly, what is needed is a method and system to overcome the problems encountered in the prior art and to provide a method and system to prevent a voltage drop across a power supply during startup.  
       SUMMARY OF THE INVENTION  
       [0008]     Briefly, in accordance with the present invention is a solution overcome the problem with voltage drop across a power supply during start-up. The solution includes a method allowing the start-up phase of an LDO voltage regulator to be controlled in order to prevent a voltage drop across a power supply battery. The present invention allows the simultaneous start-up of several LDO voltage regulators connected across a same power supply battery.  
         [0009]     Accordingly, in one embodiment the present invention provides a method for controlling the operation of an LDO voltage regulator capable of delivering a regulated output voltage using a reference voltage. The method comprises a start-up phase for the regulator in which the reference voltage is replaced by a substitution voltage in the form of a ramp, as long as the value of this substitution voltage remains below the reference voltage.  
         [0010]     Also, according to the present invention, the charge current in the external capacitor can be limited by means of the slope of the substitution voltage ramp.  
         [0011]     Another aspect of the invention is an integrated circuit comprising at least one LDO voltage regulator capable of delivering a regulated output voltage using a reference voltage. This circuit advantageously comprises means for generating a substitution voltage in the form of a ramp and control means capable of replacing the reference voltage by the substitution voltage as long as the said substitution voltage is lower than the said reference voltage.  
         [0012]     According to one embodiment in which the regulator output is connected to a load across which an external capacitor is connected in parallel, the slope of the said voltage ramp can be advantageously chosen as a function of a desired current in the external capacitor during the start-up phase.  
         [0013]     According to another embodiment, in which the regulator comprises a main operational amplifier having a first input (for example the positive input), receiving the reference voltage, and an output fed back into a second input (for example the negative input) of the main operational amplifier via a control transistor, the control means comprise an auxiliary operational amplifier having a first input (for example the positive input), connected to the output of the generating means, a second input (for example the negative input) connected to the second input of the main operational amplifier and an output connected to the output of the main amplifier and to the gate of the control transistor.  
         [0014]     According to another embodiment, in which the regulator comprises a main operational amplifier having a first input (for example the positive input) receiving the reference voltage, and an output fed back into a second input (for example the negative input) of the main operational amplifier via a control transistor, the control means comprise a comparator capable of comparing the substitution voltage and the reference voltage and a switch, connected to the first input of the main operational amplifier, capable of delivering either the substitution voltage or the reference voltage, depending on the output signal delivered by the comparator.  
         [0015]     According to another embodiment in which the regulator comprises a main operational amplifier comprising a first input transistor receiving the reference voltage at its gate, the control means comprise an additional transistor mounted in parallel with the first input transistor of the main operational amplifier and receiving the substitution voltage at its gate.  
         [0016]     According to the embodiments envisaged, the main operational amplifier advantageously comprises two PMOS or NMOS input transistors.  
         [0017]     According to one embodiment, the integrated circuit comprises several regulators with their associated control means, with their outputs respectively connected to several loads, and the generation means are connected to all the regulator-control means assemblies.  
         [0018]     Thus, by controlling the regulators with the same ramp at start-up, driving parasitic diodes into conduction is avoided.  
         [0019]     The foregoing and other features and advantages of the present invention will be apparent from the following more particular description of the preferred embodiments of the invention, as illustrated in the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]     The subject matter, which is regarded as the invention, is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features, and advantages of the invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings in which:  
         [0021]      FIG. 1  shows schematically a first exemplary embodiment of a circuit according to the present invention;  
         [0022]      FIG. 2  shows schematically, but in more detail, certain parts of  FIG. 1 , according to the present invention;  
         [0023]      FIG. 3  shows schematically another exemplary embodiment of a circuit according to the present invention;  
         [0024]      FIG. 4  shows schematically a further exemplary embodiment of a circuit according to the present invention; and  
         [0025]      FIG. 5  shows schematically another exemplary embodiment of a circuit according to the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0026]     It should be understood that these embodiments are only examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily limit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others. In general, unless otherwise indicated, singular elements may be in the plural and vice versa with no loss of generality.  
         [0027]     An integrated circuit CI according to the invention is shown in  FIG. 1 .  
         [0028]     The reference LDO represents a low-dropout voltage regulator. It comprises a main operational amplifier AMP 1  receiving a reference voltage V REF  at the positive input.  
         [0029]     The regulator LDO also comprises a control transistor Mpilot connected by its gate to the output of the amplifier AMP 1 . The transistor Mpilot, and therefore the regulator LDO, is supplied with a power supply voltage V BAT  delivered by a battery (not shown). The drain of the transistor Mpilot, delivering the regulated output voltage V s , is fed back into the negative input of the main operational amplifier AMP 1 .  
         [0030]     The output of the regulator LDO is connected to a load Ch and to an external capacitor Cext.  
         [0031]     The external capacitor Cext generally has a fairly high capacitance, for example 4.7 μF. Its role is to stabilize the low-dropout voltage regulator LDO.  
         [0032]     Aside from the regulator LDO, the circuit comprises control means that here comprise an auxiliary operational amplifier AMP 2 . The auxiliary operational amplifier AMP 2  receives a substitution voltage V RMP  in the form of a ramp at its positive input. The voltage V RMP  is generated by means known per se, comprising for example a voltage source. The negative input of the auxiliary operational amplifier AMP 2  is connected to the output of the control transistor Mpilot. Thus, the output voltage Vs of the regulator LDO follows the voltage V RMP .  
         [0033]     The output of the auxiliary operational amplifier AMP 2  is connected to the main operational amplifier AMP 1  such that, during the start-up phase of the regulator LDO, the control means replace the reference voltage V REF  with the substitution voltage V RMP  as long as the substitution voltage V RMP  is lower than the reference voltage V REF . This process will be seen in more detail below.  
         [0034]     When the regulator LDO is turned on, the substitution voltage V RMP  is reset to 0 V. Subsequently, it rises according to a predetermined ramp.  
         [0035]     The charge current I charge , delivered by the control transistor Mpilot, is then proportional to the slope of the ramp of the substitution voltage V RMP . Indeed, the slope of the ramp is calculated such that the current I charge1  flowing in the external capacitor Cext is small. It can, for example, be equivalent to 10% of the charge current I charge2  flowing in the load Ch. Thus, if a current I charge2  equal to 100 mA were desired, then I charge1  would be 10 mA.  
         [0036]     I charge1  can be obtained by the equation: 
 
 I   charge1 =( C*U )/ t,  
        with C, the capacitance of the external capacitor Cext, U, the voltage across the terminals of the capacitor Cext which is equal to V S , and t, the time.        
 
         [0038]     By fixing the slope of the ramp of the substitution voltage VRMP, given by the equation I charge1 C=U/t, where U=V S , the desired current I charge1  can therefore be obtained.  
         [0039]     Thus, by choosing a suitable slope, a current I charge1  can be obtained that is low enough not to cause a voltage drop at the power supply battery.  
         [0040]      FIG. 2  describes the main and auxiliary operational amplifiers, AMP 1  and AMP 2  respectively, together with the operation of the control means, in more detail.  
         [0041]     The main operational amplifier AMP 1  comprises two input transistors M 1  and M 2  configured as a differential pair. A common node links the sources of the two transistors M 1  and M 2 . A current source I 1  is also connected to the common node.  
         [0042]     The main operational amplifier AMP 1  also has a current mirror formed by the transistors M 3  and M 4 . The gates of the transistors M 3  and M 4  are connected together. The gate of the transistor M 3  is fed back into its source. In addition, the drains of the transistors M 3  and M 4  are connected to ground and their sources are connected to the drains of the transistors of the differential pair M 1  and M 2 . The source of the transistor M 4  is also connected to the gate of the control transistor Mpilot.  
         [0043]     The auxiliary operational amplifier AMP 2  comprises a first current mirror formed by two transistors M 9  and M 10 . The drain of the transistor M 10  is connected to the gate of the control transistor Mpilot and to the output of the main operational amplifier AMP 1 . A common node links the gates of the transistors M 9  and M 10 . The gate of M 9  is also fed back into its drain.  
         [0044]     The transistors M 9  and M 10  are supplied by the power supply voltage VDD, to which they are connected via their sources.  
         [0045]     The drain of the transistor M 9  is connected to a first transistor M 8  of a first differential pair of the auxiliary operational amplifier AMP 2 . The gate of the transistor M 8  is connected to that of the second transistor M 7  of the first differential pair. Their sources are connected to ground. The gate of the transistor M 7  is also fed back into its drain.  
         [0046]     The auxiliary operational amplifier AMP 2  comprises a second differential pair composed of the transistors M 5  and M 6 . Another common node links their sources. A current source  12  is also connected to the other common node. The drain of M 5  is connected to the source of the transistor M 7  and its gate receives the substitution voltage VRMP; it corresponds to the positive input of the operational amplifier AMP 2 . The gate of the transistor M 6  is connected to the gate of the transistor M 1  of the main operational amplifier AMP 1 ; it corresponds to the negative input of the auxiliary amplifier AMP 2 .  
         [0047]     During the start-up phase of the regulator LDO, when the output voltage Vs is less than the reference voltage V REF , the transistor M 2  is off and the transistor M 4  delivers a constant current equal to that of the source  11 . The transistors M 1 , M 3  and M 4  of the main operational amplifier AMP 1  operate as a current source. The transistor M 4  delivers the necessary current to the transistor M 10  of the auxiliary operational amplifier AMP 2 .  
         [0048]     The transistors M 5 , M 6 , M 7 , M 8 , M 9  and M 10  operate as an error amplifier. The output voltage V S  of the control transistor Mpilot can then follow the substitution voltage V RMP .  
         [0049]     When the substitution voltage V RMP  reaches the value defined by the equation V RMP =V REF +V GS , with V GS  the voltage between the gate and the source of the transistor M 2 , the transistor M 2  starts to conduct the current. The output voltage Vs no longer follows the substitution voltage V RMP . During this phase where V RMP =V REF ±V GS , the two operational amplifiers, namely the main one AMP 1  and the auxiliary one AMP 2 , operate as two followers in parallel.  
         [0050]     When V RMP  becomes higher than V REF +V GS , all the current I 2  flows through the transistor M 6  and the transistors M 5 , M 7 , M 8 , M 9 , M 10  are turned off. The current delivered by M 10  is zero. Only the transistors M 1 , M 2 , M 3  and M 4  of the operational amplifier AMP 1  are active.  
         [0051]     A variant of the control device for the voltage regulator can be seen in  FIG. 3 . For this configuration, the control means comprise a switch COM and a comparator CMP.  
         [0052]     The positive input of the main operational amplifier AMP 1  is connected to the switch COM.  
         [0053]     The switch COM is controlled by the output of the comparator CMP which performs a comparison between the reference voltage V REF  and the substitution voltage V RMP .  
         [0054]     As long as the substitution voltage V RMP  is below the reference voltage V REF , the comparator CMP delivers the value “1”, and the switch COM connects the positive input of the main operational amplifier AMP 1  to the substitution voltage V RMP . Otherwise, the comparator CMP delivers the value “0” and the switch COM connects the positive input of the main operational amplifier AMP 1  to the reference voltage V REF .  
         [0055]      FIG. 4  shows another variant of the control means. Aside from the differential pair M 1 , M 2  and the current mirror M 3  and M 4 , the main operational amplifier AMP 1  comprises an additional transistor M 1 A connected in parallel with the transistor M 1  of the differential pair. This additional transistor M 1 A forms part of the control means of the regulator LDO. The additional transistor M 1 A receives the substitution voltage V RMP  at its gate. The transistor M 1  receives the reference voltage V REF  at its gate.  
         [0056]     The gate of the transistor M 2  is connected to the output of the control transistor Mpilot.  
         [0057]     When the additional transistor M 1 A is conducting, in other words when not in the phase where V RMP  is higher than V REF +V GS , then the output voltage V S  of the control transistor Mpilot follows the substitution voltage VRMP. Otherwise, the additional transistor M 1 A is turned off and the transistor M 1  conducts.  
         [0058]     The transistors used for the input transistors M 1  and M 2  of the main operational amplifier AMP 1  are PMOS transistors for the variants shown in  FIGS. 3 and 4 . Indeed, the main operational amplifier AMP 1  must be operational at the beginning of the start-up phase, when the substitution voltage V RMP  is equal to 0 V. For the configuration shown in  FIGS. 1 and 2 , the transistors M 1  and M 2  can be NMOS transistors.  
         [0059]     As illustrated in  FIG. 5 , the integrated circuit Cl can comprise several assemblies B 1 , B 2 , . . . , Bn, each comprising a regulator LDO and its associated control means. These assemblies B 1 , B 2 , . . . , Bn are respectively connected to loads C 1 , C 2 , . . . , Cn. Interconnections IN may exist between the various loads C 1 , C 2 , and Cn. The assemblies B 1 , B 2 , . . . , Bn receive the reference voltage V REF . They are all connected to the same generation means delivering the substitution voltage V RMP .  
         [0060]     The start-up phase of the various LDO voltage regulators can thus be controlled simultaneously. The output levels of the various assemblies B 1 , B 2 , . . . , Bn are therefore identical allowing the appearance of interference-causing currents, due to conducting parasitic diodes, to be avoided at the interconnections IN.  
         [0061]     Although a specific embodiment of the invention has been disclosed, it will be understood by those having skill in the art that changes can be made to this specific embodiment without departing from the spirit and scope of the invention. The scope of the invention is not to be restricted, therefore, to the specific embodiment, and it is intended that the appended claims cover any and all such applications, modifications, and embodiments within the scope of the present invention.