Abstract:
A dual slope A/D converter uses two opposite sense ramps added to its differential input. The value in a digital counter is latched at the time when the two ramps intersect. This enables a more consistent switching point, allowing the amplifier to the linear over a larger part of its range.

Description:
BACKGROUND 
   Sloped A/D converters have been used in the prior art. A sloped A/D converter may operate in conjunction with a constant current being applied to a capacitor, thereby causing the voltage on the capacitor to continually increase (or decrease). A constant voltage source may be connected across a resistance to set the constant current. 
   A continually running clock drives a counter that is indicative of the digital value related to the voltage on the capacitor at any time. The counter value is latched at the time that a comparator senses that the ramp value is the same as the sample value. This count represents a digital count of the analog voltage being sampled. 
   Sloped A/D converters include many advantages including noise independence, simple calibration, and a simple structure. 
   Other flavors of sloped A/D converters exist, including dual slope A/D converters which integrate both the signal and the reference, in order to increase the accuracy of the system. A ramp-compare ADC (also called integrating, dual-slope or multi-slope ADC) produces a saw-tooth signal that ramps up, then quickly falls to zero. When the ramp starts, a timer starts counting. When the ramp voltage matches the input, a comparator fires, which causes the timer&#39;s value to be recorded. 
   SUMMARY 
   The present application teaches a sloped A/D converter which uses two opposite sense sloped ramps. 
   Advantages of different embodiments include a more consistent switching point and consequent better linearity. 
   According to one aspect, further noise immunity, and improved settling time may be possible. Another aspect defines use in an image sensor. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other aspects will now be described in detail with reference to the accompanying drawings, wherein: 
       FIG. 1  shows an exemplary sloped A/D converter; 
       FIG. 2  shows an embodiment; and 
       FIGS. 3A-3B  show exemplary parts of the circuit and some exemplary voltages. 
   

   DETAILED DESCRIPTION 
     FIG. 1  illustrates an exemplary sloped converter. A signal  100  is applied to one input of an amplifier, here a comparator  110 . The other input of comparator  110  receives a constant current, e.g. accumulated by a capacitor  120 , through for example a resistive divider  126 . A counter  130  begins a digital count at the time that the node  124  connected to the capacitor  124  and resistive divider  126  begins accumulating value. 
   When the value on the node  124  becomes equal to the sample value  100 , the output of the comparator  110  switches. This change in value signals a sample and hold circuit  140  to latch the digital value from counter  130  as a value representing the value of the signal. 
   The inventors recognized a problem with a system that values continually integrate in the amplifier. Switching points of the amplifier are different for different input values. The comparator/amplifier  110  needs to be capable of switching anywhere within its entire range. Hence, any nonlinearity in the amplifier/comparator  110  may cause a nonlinearity in the output signal. Since the switching point can vary over that entire range, any nonlinearities can become problematic. 
   In addition, the value of the capacitor  125  is left in a charged state that could be any value. Reducing this value to a reset value (e.g., either zero or Vcc) requires a settling time which can in turn affect the overall conversion time of the circuit. 
   It is difficult and hence expensive to make a comparator which has a relatively wide range of conversion. It is similarly difficult and expensive to make a comparator that is linear across such a wide range. 
   An embodiment which addresses this issue is shown in  FIG. 2 . The embodiment is usable, for example, in an image sensor, for example an active pixel sensor. This embodiment may be used with other sensors, and in fact may be used with any application that requires A/D conversion. 
   The circuit  200  is intended for use as a column parallel read out. In such an arrangement, the circuit  200  is associated with columns in an active pixel sensor  199  whose output is being sensed. The operation proceeds as follows. 
   A first column  201  is associated with the circuit  200 . Different columns such as  202  are associated with other circuits, such as  203 . 
   In circuit  200 , a sample signal chain  210  includes a switch  211  which is closed to sample the signal value of a specified pixel. When closed, the value of the signal is sampled onto the capacitor  215 . Similarly, the reset chain  220  has a switch  221  which is closed to sample the reset value onto the capacitor  225 . 
   After both signal and reset have been sampled onto the appropriate capacitors  215 ,  225  respectively, a switch  230  is closed. This switch shorts together the two signals, producing a summed value of (signal+reset)/2 on one plate of the capacitors  215 ,  225 . 
   The capacitive coupling effect of the capacitors  215 ,  225 , changes the values  216 ,  226  that are present on the other plates of the capacitors  215 ,  225 . This causes a differential value, that is applied to a differential preamp  250 . The preamp  250  is configured into a high gain amplifier, so that it ‘rails’ to either full on or full off, depending on which of its input value is higher. 
   Some example values may help to clarify the operation. An exemplary sample value set is shown in  FIG. 3A . The signal may have a value of 1.0, produced by the signal value from the active pixel sensor&#39;s pixel. The reset value may have a value of 2.0 volts, in this example. This example also assumes that the inputs to the preamplifier/comparator  250  are a virtual ground, although that can also be modified in different embodiments. For example, the inputs to preamp  250  may be at a virtual +1 volts. 
   The switch  230  is closed momentarily, which causes the voltages to change as shown in  FIG. 3B . The capacitors will draw or source current by whatever is necessary to oppose any change across the capacitor. Accordingly,  FIG. 3B  shows how the values across the capacitors have changed. The two values at the switch side of the capacitors have been averaged by the switch&#39;s action to 1.5 v. The opposite side of the capacitors have changed. Signal branch plate  216  has changed to 1.5 v. The reset branch plate  226  of the capacitor has changed to +0.5 volts. Hence, the preamp  250  has inputs of 1.5 volts on the signal side; +0.5 volts on the reset side. The preamp  250  rails to its maximum output. 
   The output of the preamp  250  is applied to glue logic module  240  which operates to determine the digital value as described herein. 
   After closing the switch  230 , two differential, opposite sense voltage ramps are applied to the respective signal and reset chains. A negative going ramp  228  is added to the signal chain  210 . A positive going ramp  227  is added to the reset chain  220 . The ramp adds to the values—bringing the signal value down and at the same time bringing the reset value up. Using the example above—the 1.5 volt input to the preamp  230  is reduced by the ramp from  228 . At the same time, the +0.5 v input to the preamp is increased by the ramp from  227 . In the embodiment, the opposite ramps are created differentially by the same unit, and from the same clock signal (here the counter). 
   The two ramps eventually meet halfway between the signal and reset value. This produces a reversal in the output of the preamp  250 , which therefore rails to its negative most value. 
   A logic module assembly  240  is formed of a latching comparator  245 , and an SRAM  247 . The comparator is clocked by the same clock that drives the ramp generator and the counter. At the same time, the counter output is also output to SRAM  247 . The counter speed is synchronized to the slope of the differential ramps  227 , 228 . 
   When the slopes of the ramps  227 , 228  cross, the preamp  250  changes state, and triggers the comparator. The comparator triggers the SRAM to store the current value of the counter at that time when the ramps have crossed. 
   The opposite sense ramps allow reduction of the necessary switching range of the preamp  250 , which, for example, may be reduced to a relatively small range. 
   In addition, the switching point of the preamp will be consistent at (signal-reset), and this value will not change much from pixel to pixel. Hence, any nonlinearity effects of the preamp may be minimized. 
   The general structure and techniques, and more specific embodiments which can be used to effect different ways of carrying out the more general goals are described herein. 
   Although only a few embodiments have been disclosed in detail above, other embodiments are possible and the inventors intend these to be encompassed within this specification. The specification describes specific examples to accomplish a more general goal that may be accomplished in another way. This disclosure is intended to be exemplary, and the claims are intended to cover any modification or alternative which might be predictable to a person having ordinary skill in the art. For example, the preamps and comparators may be formed using different structures. Different voltages and opposite senses may be used. While this is intended for use in a column parallel active pixel sensor readout, other embodiments may use this system in other readout systems for other arrangements of image sensors and for other applications. 
   Also, the inventor(s) intend that only those claims which use the words “means for” are intended to be interpreted under 35 USC 112, sixth paragraph. Moreover, no limitations from the specification are intended to be read into any claims, unless those limitations are expressly included in the claims. 
   The active pixel sensor may be controlled by a control device, which may be a conventional controller for an image sensor, or may be a computer, e.g., an Intel (e.g., Pentium or Core 2 duo) or AMD based computer, running Windows XP or Linux, or may be a Macintosh computer. The computer may also be a handheld computer, such as a PDA, cellphone, or laptop. The programs to run the computer may be written in C, or Java, Brew or any other programming language. The programs may be resident on a storage medium, e.g., magnetic or optical, e.g. the computer hard drive, a removable disk or media such as a memory stick or SD media, or other removable medium. The programs may also be run over a network, for example, with a server or other machine sending signals to the local machine, which allows the local machine to carry out the operations described herein. 
   Where a specific numerical value is mentioned herein, it should be considered that the value may be increased or decreased by 20%, while still staying within the teachings of the present application, unless some different range is specifically mentioned.