Abstract:
In a method of generating red, green and blue color signals, the red, green and blue color signals are picked up by red, green and blue color sensors each having a horizontal read-out register, while first n-phase clock signals (φ C1 , φ C2 , φ C3 ), generated (DEL) from a pixel clock signal (f), are processed (MUX-G) to obtain second n-phase clock signals (φ C1 (G), φ C2 (G), φ C3 (G)) for the read-out register of the green color sensor in order to obtain an electronic half pixel offset for the green color signal with respect to the red and blue color signals.

Description:
BACKGROUND OF THE INVENTION 
     Description of the Related Art 
     The invention relates to a method and a device for obtaining an electronic half pixel offset, and to a camera including such a device. 
     European Patent Application EP-A-0,476,421 discloses a circuit for producing a brightness signal from an output signal of a solid-state image pick-up apparatus using spatial pixel shift. In a color camera, red, green and blue solid-state image sensors each have a number of light-receiving elements arranged in a matrix to derive red, green and blue color signals. The light-receiving elements of the green solid-state image sensor are shifted in the horizontal scanning direction with respect to those of the red and blue solid-state image sensors over a distance which is equal to a half of a pitch of the arrangement of the light-receiving elements in the horizontal scanning direction. The camera further comprises a delay circuit for delaying the sampled green color signal by a delay time which corresponds to this half pitch. 
     The presence of delay lines constitutes a problem in the case of scan reversal, as the electronic correction in the green channel then has to change its sign. 
     SUMMARY OF THE INVENTION 
     It is, inter alia, an object of the invention to provide an electronic half pixel offset without using delay lines to compensate for the half pixel offset of the green sensor with regard to the blue and red sensors. To this end, a first aspect of the invention provides a method and a device for obtaining an electronic half pixel offset. A second aspect of the invention provides a method and a camera for generating red, green and blue color signals. 
     In a method of generating red, green and blue color signals in accordance with a primary aspect of the invention, the red, green and blue color signals are picked up by means of red, green and blue color sensors each having a horizontal read-out register, while while first n-phase clock signals, generated from a pixel clock signal, are processed to obtain second n-phase clock signals for the read-out register of the green color sensor in order to obtain an electronic half pixel offset for the green color signal with respect to the red and blue color signals. A correction delay is thereby avoided. Delay correction at scan reversal is also simplified: one only needs to shift the starting instant of the pulses of the horizontal shift register over one pixel clock pulse. The invention is cheaper than the prior art solution and can more easily be cast in an integrated circuit. Moreover, the half pixel offset can be made in a more accurate manner. 
     In a preferred embodiment, the green signal is shifted in time over exactly half a pixel period by inverting the phase of the clock pulses for the green sensor with regard to the phases of the clock pulses for the red and blue sensors during shifting of the green color signal out of the horizontal shift register of the green sensor. This holds for 2 and 3-phase horizontal registers. For a 4-phase horizontal register, the pulses need to be interchanged cyclically. 
     These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings: 
     FIG. 1 shows an embodiment of a clock generation circuit in accordance with the present invention; 
     FIG. 2 shows an embodiment of a camera in accordance with the present invention; and 
     FIG. 3 shows an embodiment of a 3-phase image sensor for use in the camera embodiment of FIG.  2 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The clock generation circuit embodiment of FIG. 1 is applicable with a 3-phase image sensor as known from, for example, U.S. Pat. No. 5,517,244 (Attorneys&#39; docket PHN 13,786) and the article “Interlacing in charge-coupled imaging devices” by C. H. Séquin, IEEE Transactions on Electron Devices, Vol. ED-20, No. 6, June 1973, pp. 535-541. The IEEE article also mentions even-phase charge transfer structures. Such known image sensors do not need to be described in this disclosure. 
     A pixel clock frequency signal f=1/T is applied to a delay circuit DEL for supplying an undelayed first clock signal φ C1  a second clock signal φ C2  which has been delayed over T/3, and a third clock signal φ C3  which has been delayed over 2T/3. The three clock signals φ C1 , φ C2  and φ C3  are applied to respective 0-inputs of three multiplexer sections RB 1 , RB 2  and RB 3  of a first, non-inverting multiplexer MUX-RB to obtain three respective clock signals φ C1 (R,B), φ C2 (R,B) and φ C3 (R,B) for the red and blue image sensors RS and BS of FIG.  2 . The three clock signals φ C1 , φ C2  and φ C3  are also applied to respective 0-inputs of three multiplexer sections G 1 , G 2  and G 3  of a second, inverting multiplexer MUX-G to obtain three respective clock signals φ C1 (G), φ C2 (G) and φ C3 (G) for the green image sensor GS of FIG.  2 . The 1-inputs of the multiplexer sections RB 1  and RB 2  receive a high signal, while the 1-input of the multiplexer section RB 3  receives a low signal. The 1-inputs of the multiplexer sections G 1  and G 2  receive a low signal, while the 1-input of the multiplexer section G 3  receives a high signal. The multiplexers MUX-RB and MUX-G are controlled by a hustle signal HUSTL  0 / 1  which indicates whether the signals at the 0-inputs or the signals at the 1-inputs of the multiplexer sections are supplied at the outputs. The half pixel offset for the green channel is obtained by the fact that the outputs of the multiplexer sections of the multiplexer MUX-G are inverted outputs. 
     If the hustle signal HUSTL  0 / 1  is 1, the output clock signals are fixed as follows: all output clock signals φ C1 (R,B), φ C1 (G), φ C2 (R,B) and φ C2 (G) are high, while both output clock signals φ C3 (R,B) and φ C3 (G) are both low. This makes it possible to pass the charges in the last line of the storage part SP of a frame transfer sensor RS, GS, BS to the horizontal shift register HR of FIG.  3 . By applying the inverse of the signals applied to the 1-inputs of the non-inverting multiplexer MUX-RB to the 1-inputs of the inverting multiplexer MUX-G, it is achieved that the same (correct) charge shift from the storage part SP to the horizontal shift register HR of FIG. 3 is carried out in all of the three CCD image sensors RS, GS and BS. 
     FIG. 2 shows an embodiment of a camera in accordance with the present invention. The camera comprises a lens L, a prism P, a red image sensor RS, a green image sensor GS, and a blue image sensor BS. Color signals R, G and B picked up by the image sensors RS, GS and BS are applied to a processor PROC which furnishes a luminance signal Y and a chrominance signal C. 
     FIG. 3 shows an embodiment of a 3-phase image sensor RS, GS or BS for use in the camera embodiment of FIG.  2 . The frame transfer sensor comprises in known manner an image part IP, a covered storage part SP, and a horizontal read-out shift register HR. In accordance with the present invention, the horizontal read-out shift register HR is clocked by the output clock signals φ C1 (R,B)/(G), φ C2 (R,B)/(G) and φ C3 (R,B)/(G) of the clock signal generator of FIG.  1 . The horizontal shift register HR supplies the sensor output signal R, G or B. The image part IP is clocked by, for example, three image part clock signals φ IP.1 , φ IP.2 and φ   IP.3 . The storage part SP is clocked by, for example, three storage part clock signals φ SP.1 , φ SP.2  and φ SP.3 . The image part IP and/or the storage part SP are clocked independently of the clocking for the horizontal shift register HR. In one embodiment, the image part IP and/or the storage part SP have 4-phase clock signals, while the horizontal shift register HR has a 3-phase clock signal. As mentioned above, the horizontal shift register HR may alternatively have 2-phase clock signals with inverted phases for green, or a 4-phase clock signal with cyclically interchanged clock signals for green. 
     The charges from the horizontal shift register HR are transferred to a capacitor CP to convert these charges into voltages. Before the charge of a subsequent pixel can be transferred to the capacitor CP, the capacitor CP should be discharged by means of a reset-FET RF. The reset-FET RF is controlled by a small reset pulse RP(R,B) or RP(G) which coincides with the rising edge corresponding to the φ C1  pulse at the end of the horizontal shift register HR. 
     In FIG. 1, a cascade connection of a differentiator D-RB/D-G and a rectifier RT-RB/RT-G generates the reset pulse RP(R,B)/RP(G) in dependence on the φ C1 (R,B)/φ C1 (G) clock signal. 
     It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The invention is not limited to applications with the sensor matrix known from EP-A-0,476,421. Other matrices, like those comprising sub-arrays of 2 green, 1 red and 1 blue colored light-receiving elements, or 2 green and 1 alternatingly red or blue colored light-receiving elements, are possible as well. The invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the device claim enumerating several means, several of these means can be embodied by one and the same item of hardware.