Abstract:
A nonvolatile memory device features a serial diode cell as a cross-point cell using a nonvolatile ferroelectric capacitor and a serial diode chain. The serial diode cell comprises a ferroelectric capacitor and a serial diode switch. The ferroelectric capacitor, located where a word line and a bit line are crossed, stores values of logic data. The serial diode switch is connected between the ferroelectric capacitor and the bit line and selectively switched depending on voltages applied to the word line. The nonvolatile memory device using a serial diode cell comprises a plurality of serial diode cell arrays, a plurality of word line driving units and a plurality of sense amplifiers. Each of the plurality of serial diode cell arrays each includes a single serial diode cell where a word line and a bit line are crossed. The plurality of word line driving units selectively drive the word line. The plurality of sense amplifiers sense and amplify data transmitted through the bit line.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention generally relates to a memory device, and more specifically, to a phase change resistor cell comprising a cross-point cell using a phase change resistor and a serial diode switch, a nonvolatile memory device using the phase change resistor cell to improve the whole size  
         [0003]     2. Description of the Prior Art  
         [0004]     Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FeRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory DRAM and conserves data even after the power is turned off.  
         [0005]     The FeRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes the characteristic of a high residual polarization of the ferroelectric substance in which data is not deleted even after an electric field is eliminated.  
         [0006]     The technical contents on the above FeRAM are disclosed in the Korean Patent Application No. 2001-57275 by the same inventor of the present invention. Therefore, the basic structure and the operation on the FeRAM are not described herein.  
         [0007]     The conventional FeRAM comprises a switching device which is switched depending on a voltage of a word line and connects a nonvolatile ferroelectric capacitor to a sub bit line. The nonvolatile ferroelectric capacitor is connected to a terminal of the switching device and a plate line.  
         [0008]     Meanwhile, the conventional FeRAM comprises a switch device and a memory device for storing data. Here, the switching device of the conventional memory device is a NMOS transistor whose switching operation is controlled by a gate control signal.  
         [0009]     However, the above-described NMOS transistor requires an additional area for gate control when a cell array is embodied with a switching device, which results in increase of the whole chip size.  
       SUMMARY OF THE INVENTION  
       [0010]     Accordingly, it is a first object of the present invention to embody a phase change resistor cell comprising a serial diode switch using a Silicon On Insulator (hereinafter, referred to as “SOI”) wafer.  
         [0011]     It is a second object of the present invention to reduce the whole size of a nonvolatile memory device by embodying a cross-point cell using a PCR and a serial diode switch.  
         [0012]     It is a third object of the present invention to improve operation characteristics of a memory cell by effectively driving read/write operations in a cell array using the PCR and the serial diode switch.  
         [0013]     In an embodiment, a serial diode cell comprises a ferroelectric capacitor and a serial diode switch. The ferroelectric capacitor, located where a word line and a bit line are crossed, stores values of logic data. The serial diode switch is connected between the ferroelectric capacitor and the bit line and selectively switched depending on voltages applied to the word line.  
         [0014]     Preferably, the serial diode switch comprises a silicon layer where a P-type region and a N-type region are alternately formed on an insulating layer, the bit line and the ferroelectric capacitor are formed on the upper portion of the serial diode switch, a contact node connected to the ferroelectric capacitor is connected to a predetermined location of the serial diode switch, and the serial diode switch is divided into a PN diode switch and a PNPN diode switch on a basis of the contact node.  
         [0015]     In an embodiment, a nonvolatile memory device using a serial diode cell comprises a plurality of serial diode cell arrays, a plurality of word line driving units and a plurality of sense amplifiers. Each of the plurality of serial diode cell arrays each includes a single serial diode cell where a word line and a bit line are crossed. The plurality of word line driving units selectively drive the word line. The plurality of sense amplifiers sense and amplify data transmitted through the bit line. The nonvolatile memory device further comprises a data bus, a main amplifier, a data buffer and an input/output port. The data bus is shared by the plurality of sense amplifiers. The main amplifier amplifies data of the data bus. The data buffer buffers data inputted/outputted in the main amplifier. The input/output port, connected to the data buffer, inputs/outputs data. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]     Other aspects and advantages of the present invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:  
         [0017]      FIG. 1  is a circuit diagram of a serial diode cell according to an embodiment of the present invention;  
         [0018]      FIG. 2  is a cross-sectional diagram of the serial diode cell of  FIG. 1 ;  
         [0019]      FIG. 3  is a layout diagram of a serial diode switch of  FIG. 1 ;  
         [0020]      FIG. 4  is a layout diagram of the serial diode cell of  FIG. 1 ;  
         [0021]      FIG. 5  is a graph illustrating the operation of the serial diode switch of  FIG. 1 ;  
         [0022]      FIGS. 6   a  to  6   c  are a circuit diagram and graphs illustrating the word line/bit line voltage dependency of the serial diode cell according to an embodiment of the present invention;  
         [0023]      FIG. 7  is a block diagram of a nonvolatile memory device using a serial diode cell according to an embodiment of the present invention;  
         [0024]      FIG. 8  is a layout diagram of a cross-point cell of  FIG. 7 ;  
         [0025]      FIG. 9  is a circuit diagram of a serial diode cell array of  FIG. 7 ;  
         [0026]      FIG. 10  is a circuit diagram of a sense amplifier of  FIG. 9 ;  
         [0027]      FIG. 11  is a circuit diagram illustrating another example of the serial diode cell array of  FIG. 7 ;  
         [0028]      FIG. 12  is a circuit diagram of the sense amplifier of  FIG. 11 ;  
         [0029]      FIG. 13  is a timing diagram illustrating the read mode of the nonvolatile memory device using a serial diode cell according to an embodiment of the present invention; and  
         [0030]      FIG. 14  is a timing diagram illustrating the write mode of the nonvolatile memory device using a serial diode cell according to an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0031]     The present invention will be described in detail with reference to the accompanying drawings.  
         [0032]      FIG. 1  is a circuit diagram of a serial diode cell according to an embodiment of the present invention.  
         [0033]     In an embodiment, the serial diode cell comprises a nonvolatile ferroelectric capacitor FC and a serial diode switch  10 . Here, the serial diode switch  10  comprises a PNPN diode switch  11  and a PN diode switch  12 . The PNPN diode switch  11  and the PN diode switch  12  are connected in parallel between the nonvolatile ferroelectric capacitor FC and a bit line BL.  
         [0034]     The PNPN diode switch  11  is connected in a reverse direction between the nonvolatile ferroelectric capacitor FC and the bit line BL. The PN diode switch  12  is connected in a forward direction between the nonvolatile ferroelectric capacitor FC and the bit line BL. The nonvolatile ferroelectric capacitor FC is connected to a word line WL.  
         [0035]      FIG. 2  is a cross-sectional diagram of the serial diode cell of  FIG. 1 .  
         [0036]     An insulating layer  31  is formed on a silicon substrate  30 , and a silicon layer  32  is formed on the insulating layer  31 . A region doped with P-type impurities and a region doped with N-type impurities are alternately formed in the silicon layer  32  which is the serial diode switch  10 . Here, the insulating layer  31  is formed of SiO 2 , and the silicon layer  32  is formed of epitaxial silicon or deposition polysilicon. The serial diode switch  10  comprises a serially connected diode chain comprising the PNPN diode switch  11  and the PN diode switch  12 .  
         [0037]     The silicon layer  32  comprises a plurality of rows, and a single row separated by the insulating layer  31  comprises a diode chain comprising a PNPN diode switch  11  and a PN diode switch  12  which are connected serially.  
         [0038]     In the PNPN diode switch  11 , the P-type region and the N-type region are alternately arranged in the same layer, and the pair of the P-type region and the N-type region is connected serially. The PN diode switch  12  adjacent to the PNPN diode switch  11  comprises a plurality of the P-type region and the N-type region which are connected serially.  
         [0039]     A bit line contact node BLCN is formed on the top portion of the N-type region and the P-type region located at both end portions of the diode chain which comprises the PNPN diode switch  11  and the PN diode switch  12 . The upper portion of the node BLCN is connected to the bit line BL. A common contact node CN is formed on the top portion of the P-type region and the N-type region where the PN diode switch  12  and the PNPN diode switch  11  are contacted, and a bottom electrode  22  of the PCR is connected through the common contact node CN to the top portion of the P-type region and the N-type region.  
         [0040]     Here, the nonvolatile ferroelectric capacitor FC comprises a top electrode  20 , a ferroelectric layer  21  and a bottom electrode  22 . The top electrode  20  of the nonvolatile ferroelectric capacitor FC is connected to the word line WL.  
         [0041]      FIG. 2  is a diagram illustrating a cross-section corresponding to a portion II-II of  FIG. 4 . Here, the bit line BL is illustrated for convenience of explanation although the bit line BL is not shown in the actual cross section.  
         [0042]      FIG. 3  is a layout diagram of the serial diode switch  10  of  FIG. 1 .  
         [0043]     The serial diode switch  10  comprises a plurality of serial chains of the PNPN diode switch  11  and the PN diode switch  12  included in the silicon layer  32  as shown in  FIG. 4 . A plurality of the serial diode switches  10  are formed on the insulating layer  31  in parallel. The serial diode switch  10  is formed to have the SOI structure, and each serial diode switch  10  is separated by the insulating layer  31 .  
         [0044]      FIG. 4  is a layout diagram of the serial diode cell of  FIG. 1 .  
         [0045]     The PNPN diode switch  11  and the PN diode switch  12  which are connected serially are formed in the silicon layer  32  consisting of epitaxial silicon or polysilicon, and the top and the bottom of each serial diode switch  10  are insulated by the insulating layer  31 . The contact node CN is formed between the PN region and the PNPN region of the serial diode switch  10 . The contact node CN is contacted in common with the P-type region adjacent to the N-type region. The nonvolatile ferroelectric capacitor FC is formed on the contact node CN.  
         [0046]     The N-type region and the P-type region of both end portions of the serial diode switch  10  is connected through the bit line contact node BLCN to the bit line BL. The bit line contact node BLCN is connected in common to the bit line contact node BLCN of the adjacent serial diode cell. The contact node BLCN connected to the same bit line may be shared with the serial diode switch  10  of the adjacent cell.  
         [0047]     The word line WL is formed on the nonvolatile ferroelectric capacitor FC.  
         [0048]      FIG. 5  is a graph illustrating the operation of the serial diode switch  10  of  FIG. 1 .  
         [0049]     Although a voltage applied to the nonvolatile ferroelectric capacitor FC increases in a positive direction on a basis of the bit line BL and reaches a voltage Vo, the serial diode switch  10  is kept off by operation characteristics of the PNPN diode switch  11 . As a result, current does not flow in the nonvolatile ferroelectric capacitor FC.  
         [0050]     Thereafter, if a voltage applied to the bit line BL more increases and reaches a threshold voltage Vc, the PNPN diode switch  11  is turned on by the forward operation characteristic of the diode. As a result, the serial diode switch  10  is turned on, and the amount of current dramatically increases. Here, when the voltage applied to the bit line BL is over the threshold voltage Vc, a value of current I connected to the bit line BL is affected by resistance (not shown) connected to the PCR to serve as load.  
         [0051]     After the PNPN diode switch  11  is turned on, the large amount of current can flow although a small voltage Vs is applied to the PCR. Here, the PN diode switch  10  is kept off by the reverse operation characteristic.  
         [0052]     On the other hand, if a predetermined voltage is applied to the word line WL and the voltage applied to the nonvolatile ferroelectric capacitor FC increases toward a negative direction on the basis of the bit line BL, the serial diode switch  10  is turned on by the forward operation characteristic of the PN diode switch  10 . Then, current flows at a random operation voltage state. Here, the PNPN diode switch  11  is kept by the reverse operation characteristic.  
         [0053]      FIGS. 6   a  to  6   c  are a circuit diagram and graphs illustrating the word line WL/bit line BL voltage dependency of the serial diode cell according to an embodiment of the present invention.  
         [0054]     Referring to  FIG. 6   a , Vfc refers to a voltage flowing the nonvolatile ferroelectric capacitor FC connected between the word line WL and a node SN, and Vsw refers to a voltage flowing in the serial diode switch  10  connected between the node SN and the bit line BL.  
         [0055]      FIG. 6   b  is a diagram illustrating the word line WL voltage dependency of the serial diode cell according to an embodiment of the present invention.  
         [0056]     If a voltage of the word line WL increases while a voltage of the bit line BL is fixed at a ground voltage level, the voltage of the word line WL is distributed to the nonvolatile ferroelectric capacitor FC and the serial diode switch  10 .  
         [0057]     In other words, if the voltage of the word line WL increases while the voltage of the bit line BL is at the ground level, the PN diode switch  12  of the serial diode switch  10  is turned on at a small voltage. As a result, current flows.  
         [0058]     Here, the small voltage Vsw is distributed by the forward operation characteristic of the PN diode switch in the serial diode switch  10 . On the other hand, the voltage of the word line WL is distributed as the large voltage Vfc to the nonvolatile ferroelectric capacitor FC. Therefore, the operation characteristics of the serial diode cell are improved.  
         [0059]      FIG. 6   c  is a diagram illustrating the bit line BL voltage dependency of the serial diode cell according to an embodiment of the present invention.  
         [0060]     If a voltage of the bit line BL increases while a voltage of the word line WL is fixed at a ground voltage level, the voltage of the bit line BL is distributed to the nonvolatile ferroelectric capacitor FC and the serial diode switch  10 .  
         [0061]     In other words, if the voltage of the bit line BL increases while the voltage of the word line WL is fixed at the ground voltage level, the PNPN diode switch  11  of the serial diode switch  10  is kept off until the voltage of the bit line BL reaches a threshold voltage Vc. The PN diode switch  12  of the serial diode switch  10  is kept off by the reverse operation characteristic. As a result, most voltage of the bit line BL is distributed as the large voltage Vsw to the serial diode switch  10 .  
         [0062]     On the other hand, when the serial diode switch  10  is turned off, the voltage of the bit line BL is distributed as the small voltage Vfc to the nonvolatile ferroelectric capacitor FC. As a result, data stored in the nonvolatile ferroelectric capacitor FC are not changed.  
         [0063]     Thereafter, when the voltage of the bit line BL rises to reach over the threshold voltage Vc, the PNPN diode switch  11  of the serial diode switch  10  is turned on, and most voltage of the bit line BL is distributed to the nonvolatile ferroelectric capacitor FC, and the voltage Vfc increases. As a result, new data are written in the nonvolatile ferroelectric capacitor FC of the serial diode cell.  
         [0064]      FIG. 7  is a block diagram of a nonvolatile memory device using a serial diode cell according to an embodiment of the present invention.  
         [0065]     In an embodiment, the nonvolatile memory device comprises a plurality of serial diode cell arrays  40 , a plurality of word line driving units  50 , a plurality of sense amplifiers  60 , a data bus  70 , a main amplifier  80 , a data buffer  90  and an input/output port  100 .  
         [0066]     Each serial diode cell array  40  comprises a plurality of serial diode cells arranged in row and column directions as described in  FIG. 1 . A plurality of word lines WL arranged in the row direction are connected to the word line driving unit  50 . A plurality of bit lines BL arranged in the column direction are connected to the sense amplifier  60 .  
         [0067]     Here, one serial diode cell array  40  is correspondingly connected to one word line driving unit  50  and one sense amplifier  60 .  
         [0068]     The plurality of sense amplifiers  60  share one data bus  70 . The data bus  70  is connected to the main amplifier  80  which amplifies data applied from each sense amplifier  60  through the data bus  70 .  
         [0069]     The data buffer  90  buffers the amplified data applied from the main amplifier  80 . The input/output port  100  outputs output data applied from the data buffer  90  to the outside or applies input data applied from the outside to the data buffer  90 .  
         [0070]      FIG. 8  is a layout diagram of the serial diode cell array  40  of  FIG. 7 .  
         [0071]     The serial diode cell array  40  comprises a plurality of word lines WL arranged in the row direction and a plurality of bit lines BL arranged in the column direction. A unit cell C is located only where the word line WL and the bit line BL are crossed. That is, a cross-point cell is embodied. Since it is unnecessary to form devices in other regions, a cell can be formed in a space necessary to form the word line WL and the bit line BL without requiring an additional area.  
         [0072]     Here, the cross-point cell refers to a serial diode cell using the serial diode switch  10  comprising a nonvolatile ferroelectric capacitor FC located where a bit line BL and a word line WL are crossed. The serial diode switch  10  does not comprise a NMOS transistor using an additional word line WL or gate control signal but comprises two connection electrode node.  
         [0073]      FIG. 9  is a circuit diagram of the serial diode cell array  40  of  FIG. 7 .  
         [0074]     The serial diode cell array  40  comprises a plurality of word lines WL&lt;0&gt;˜WL&lt;n&gt; arranged in the row direction and a plurality of bit lines BL&lt;0&gt;˜BL&lt;m&gt; arranged in the column direction. A unit cell C is located only where the word line WL and the bit line BL are crossed. Here, the unit cell C comprises one nonvolatile ferroelectric capacitor FC and one serial diode switch  10 .  
         [0075]     The plurality of sense amplifiers  60  are connected one by one to the bit lines BL. Each sense amplifier  60  compares a voltage applied from the bit line BL with a reference voltage REF previously set when a sense amplifier enable signal SEN is activated, and amplifies the comparison result.  
         [0076]     A bit line pull-down device N 1  is connected to the bit line BL&lt;0&gt;, and a bit line pull-down device N 2  is connected to the bit line BL&lt;m&gt;. When a bit line pull-down signal BLPD is activated, the bit line pull-down devices N 1  and N 2  apply a ground voltage to the bit line BL and pull down the bit line BL to a ground level.  
         [0077]     The above-described serial diode cell array  40  is operated so that each nonvolatile ferroelectric capacitor FC may store one data.  
         [0078]      FIG. 10  is a circuit diagram of the sense amplifier  60  of  FIG. 9 .  
         [0079]     The sense amplifier  60  comprises an amplifying unit  61  and a column selecting switching unit  62 .  
         [0080]     Here, the amplification unit  61  comprises PMOS transistors P 1 ˜P 3  and NMOS transistors N 1 ˜N 3 . The PMOS transistor P 1 , connected between a power voltage terminal and a common source terminal of the PMOS transistors P 2  and P 3 , has a gate to receive a sense amplifier enable signal SEP. The cross-coupled PMOS transistors P 2  and P 3  latch a power voltage applied through the PMOS transistor P 1 .  
         [0081]     A NMOS transistor N 5 , connected between a ground voltage terminal and a common source terminal of NMOS transistors N 3  and N 4 , has a gate to receive a sense amplifier enable signal SEN. The cross-coupled NMOS transistors N 3  and N 4  latch a ground voltage applied through the NMOS transistor N 5 .  
         [0082]     Here, the sense amplifier enable signal SEN has a phase opposite to that of the sense amplifier enable signal SEP. When the sense amplifier enable signal SEN is activated, the amplification unit  61  is operated. One output terminal of the amplification unit  61  is connected to the bit line BL&lt;m&gt;, and the other output terminal of the amplification unit  61  is connected to a terminal to receive a reference voltage REF.  
         [0083]     The column selecting switching unit  62  comprises NMOS transistors N 6  and N 7 . The NMOS transistor N 6 , connected between the bit line BL&lt;m&gt; and the data bus  70 , has a gate to receive a column selecting signal CS&lt;n&gt;, thereby controlling input/output of the data /D. The NMOS transistor N 7 , connected to the terminal to receive the reference voltage REF and the data bus  70 , has a gate to receive the column selecting signal CS&lt;n&gt;, thereby controlling input/output of the data D.  
         [0084]      FIG. 11  is a circuit diagram illustrating another example of the serial diode cell array of  FIG. 7 .  
         [0085]     The serial diode cell array  40  comprises a plurality of word lines WL&lt;0&gt;˜WL&lt;n&gt; arranged in the row direction and a plurality of paired bit lines BL and /BL arranged in the column direction. A unit cell C is located only where the paired bit lines BL and /BL are crossed. The unit cell C comprises one nonvolatile ferroelectric capacitor FC and one serial diode switch  10 .  
         [0086]     One sense amplifier  60  is connected one by one to the paired bit lines BL and /BL. When a sense amplifier enable signal SEN is activated, each sense amplifier  60  is simultaneously operated to amplify data applied from the paired bit lines BL and /BL.  
         [0087]     A bit line pull-down device N 8  is connected to the bit line /BL&lt;0&gt;, and a bit line pull-down device N 9  is connected to the bit line BL&lt;0&gt;. As a result, when a bit line pull-down signal BLPD is activated, the bit line pull-down devices N 3  and N 4  apply a ground voltage to the paired bit lines BL and /BL, and pull down the paired bit lines BL and /BL to a ground voltage level.  
         [0088]     The above-described serial diode cell array  40  is operated so that two nonvolatile ferroelectric capacitors FC may store one data.  
         [0089]      FIG. 12  is a circuit diagram of the sense amplifier  60  of  FIG. 11 .  
         [0090]     The sense amplifier  60  comprises an amplifying unit  63  and a column selecting switching unit  64 .  
         [0091]     Here, the amplification unit  63  comprises PMOS transistors P 4 ˜P 6  and NMOS transistors N 10 ˜N 12 . The PMOS transistor P 4 , connected between a power voltage terminal and a common source terminal of the PMOS transistors P 5  and P 6 , has a gate to receive a sense amplifier enable signal SEP. The cross-coupled PMOS transistors P 5  and P 6  latch a power voltage applied through the PMOS transistor P 4 .  
         [0092]     A NMOS transistor N 12 , connected between a ground voltage terminal and a common source terminal of NMOS transistors N 10  and N 11 , has a gate to receive a sense amplifier enable signal SEN. The cross-coupled NMOS transistors N 10  and N 11  latch a ground voltage applied through the NMOS transistor N 12 .  
         [0093]     Here, the sense amplifier enable signal SEN has a phase opposite to that of the sense amplifier enable signal SEP. When the sense amplifier enable signal SEN is activated, the amplification unit  63  is operated. One output terminal of the amplification unit  63  is connected to the bit line BL&lt;m&gt;, and the other output terminal of the amplification unit  63  is connected to a terminal to receive a reference voltage REF.  
         [0094]     The column selecting switching unit  64  comprises NMOS transistors N 13  and N 14 . The NMOS transistor N 13 , connected between the bit line BL&lt;m&gt; and the data bus  70 , has a gate to receive a column selecting signal CS&lt;n&gt;, thereby controlling input/output of the data /D. The NMOS transistor N 14 , connected to the terminal to receive the reference voltage REF and the data bus  70 , has a gate to receive the column selecting signal CS&lt;n&gt;, thereby controlling input/output of the data D.  
         [0095]      FIG. 13  is a timing diagram illustrating the read mode of the nonvolatile memory device using a serial diode cell according to an embodiment of the present invention.  
         [0096]     In an interval t 0 , the bit line pull-down signal BLPD is activated, and the ground voltage is applied to the paired bit lines BL. As a result, the bit line BL is precharged to the ground level.  
         [0097]     When an interval t 1  starts, if the word line WL transits to ‘high’ and a predetermined voltage is applied to the word line WL, the PN diode  12  of the serial diode switch  10  is turned on. As a result, data of the serial diode cell are transmitted to the bit line BL. Here, the bit line pull-down signal BLPD transits to ‘low’.  
         [0098]     Next, in an interval t 2 , if the sense amplifier enable signal transits to ‘high’, the sense amplifier  60  amplifies data applied from the bit line BL. If the voltage of the bit line BL is amplified to the low level while the voltage of the word line WL is ‘high’, data “0” is restored in the serial diode cell C.  
         [0099]     Thereafter, in an interval t 3 , the voltage of the word line WL transits to a negative voltage which is less than the threshold voltage Vc. That is, a difference between the low voltage level of the bit line BL and the negative voltage level of the word line WL does not reach the level of the threshold voltage Vc to turn on the PNPN diode switch  11  of the serial diode switch  10 .  
         [0100]     However, a voltage higher than the threshold voltage Vc is applied to turn on the PNPN diode switch  11  depending on the difference between the low voltage level of the bit line BL and the negative voltage level of the word line WL. As a result, the PNPN diode switch  11  is turned on, and data “1” are restored in the serial diode cell.  
         [0101]     After the PNPN diode switch  11  is turned on, a large amount of current can flow although the small voltage Vs is applied to the bit line BL. As a result, the sufficient amount of current can flow although the voltage of the word line WL rises from the negative voltage to the low level in the interval t 3 .  
         [0102]     In the interval t 3 , if the column selecting signal transits to ‘high’, the NMOS transistors N 6  and N 7  of the column selecting switching unit  62  are turned on, and the data D and /D in the bit line BL are outputted to the data bus  70 . As a result, data stored in the serial diode cell C can be read.  
         [0103]      FIG. 14  is a timing diagram illustrating the write mode of the nonvolatile memory device using a serial diode cell according to an embodiment of the present invention.  
         [0104]     In an interval t 0 , the bit line pull-down signal BLPD is activated, and the ground voltage is applied to the paired bit lines BL. As a result, the bit line BL is pulled down to the ground level.  
         [0105]     Thereafter, when an interval t 1  starts, if the voltage of the word line WL transits to ‘high’, data of the serial diode cell are transmitted to the bit line BL. Here, the bit line pull-down signal BLPD transits to ‘low’. Then, new data D and /D to be written through the data bus  70  are inputted to the bit line BL.  
         [0106]     Next, in an interval t 2 , the sense amplifier enable signal SEN is activated, and the sense amplifier  60  amplifies data in the bit line BL. If the voltage of the bit line BL is amplified to the low level while the voltage of the word line is ‘high’, data “0” are written in the serial diode cell C.  
         [0107]     Here, if the column selecting signal CS transits to ‘high’, the NMOS transistors N 6  and N 7  of the column selecting switching unit  62  are turned on. As a result, the data D and /D inputted through the data bus  70  are applied to the bit line BL.  
         [0108]     Thereafter, in an interval t 3 , the voltage of the word line WL transits to the negative voltage. That is, a difference between the low voltage level of the bit line BL and the negative voltage level of the word line WL does not read the level of the threshold voltage Vc to turn on the PNPN diode switch  11  of the serial diode switch  10 .  
         [0109]     However, a voltage higher than the threshold voltage Vc to turn on the PNPN diode switch  11  is applied depending on the high level voltage of the bit line BL and the negative voltage level of the word line WL. As a result, the PNPN diode switch  11  is turned on, and data “1” are written in the serial diode cell.  
         [0110]     Although a nonvolatile ferroelectric memory device is described as an example of a memory device to store data herein, the present invention is not limited to the particular form disclosed. Rather, the memory device according to an embodiment of the present invention can include a DRAM device or a flash device.  
         [0111]     As discussed earlier, a nonvolatile memory device using a phase change resistor cell according to an embodiment of the present invention provides the following effects: to embody a phase change resistor cell comprising a serial diode switch using a SOI wafer; to reduce the whole size of a nonvolatile memory device by embodying a cross-point cell using a PCR and a serial diode switch; and to improve operation characteristics of a memory cell by effectively driving read/write operations in a cell array using the PCR and the serial diode switch.  
         [0112]     While the invention is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, it should be understood that the invention is not limited to the particular forms disclosed. Rather, the invention covers all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined in the appended claims.