Abstract:
A method for manufacturing a semiconductor device comprises performing a CMP process using an oxide film as an etching barrier film to maintain a polysilicon layer having a large open area. A word line pattern, a DSL pattern, and a SSL pattern that are formed by a first patterning process are not additionally blocked, and the oxide film is used as an etching barrier to obtain an accurate overlay between patterns and improve CD uniformity, thereby improving a characteristic of the device.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    Priority to Korean patent application number 10-2007-0137989, filed on Dec. 26, 2007, the disclosure of which is incorporated by reference in its entirety, is claimed. 
       BACKGROUND OF THE INVENTION 
       [0002]    The invention relates generally to a method for forming a pattern of a semiconductor device that can control a fine critical dimension and improve an overlay characteristic of the device. 
         [0003]    In the manufacturing of semiconductor devices, the resolution required in the semiconductor device has decreased beyond the minimum resolution that can be resolved using photolithography equipment. 
         [0004]    For example, if the minimum resolution is 45 nm when an exposure process is performed using photolithography equipment, the semiconductor device may require a resolution smaller than 40 nm. 
         [0005]    Due to the limit of the photolithography equipment, various patterning technologies have been proposed. Of these technologies, a patterning technique using a spacer has been widely used. 
         [0006]      FIGS. 1   a  to  1   g  are cross-sectional diagrams illustrating a conventional method for forming a pattern of a semiconductor device using spacer patterning technology (SPT). 
         [0007]    Referring to  FIG. 1   a,  a nitride film  110 , a first polysilicon layer  120 , an anti-reflective film  130 , and a first photoresist pattern  140  are formed over a semiconductor substrate  100 . 
         [0008]    The first photoresist pattern  140  is twice as wide as that of a final pattern. 
         [0009]    Referring to  FIG. 1   b,  the anti-reflective film  130  and the first polysilicon layer  120  are etched using the first photoresist pattern  140  as a mask to form an anti-reflective pattern (not shown) and a first polysilicon pattern  120   a.    
         [0010]    The anti-reflective pattern (not shown) and the first photoresist pattern  140  are then removed. 
         [0011]    Referring to  FIG. 1   c,  an oxide film (not shown) is deposited over the resulting structure including the first polysilicon pattern  120   a.  A blanket-etching process is performed to form spacers  150  at sidewalls of the first polysilicon pattern  120   a.    
         [0012]    The spacers  150  are formed to have a critical dimension (CD) that is the same as that of the first polysilicon pattern  120   a.    
         [0013]    Referring to  FIG. 1   d,  a second polysilicon layer  160  is formed over the resulting structure including the first polysilicon pattern  120   a  and the spacers  150 . 
         [0014]    The second polysilicon layer  160  reflects a step difference of the first polysilicon pattern  120   a.    
         [0015]    Referring to  FIG. 1   e,  an etch-back process is performed to expose the first polysilicon pattern  120   a,  so that the second polysilicon layer  160  remains between the spacers  150 . The etch-back process is a dry etching process. 
         [0016]    After the etch-back process is performed, the second polysilicon layer  160  remains on the sidewalls of the spacers  150 . An additional etch process is required to remove the residual second polysilicon layer  160 . 
         [0017]    The entire second polysilicon layer  160  is etched in a large open area to expose the first polysilicon pattern  120   a  during the etch-back process. As a result, a pattern cannot be formed in a peripheral circuit region and an inter-connection region during a subsequent patterning process without forming a second photoresist pattern over the cell region. 
         [0018]    Referring to  FIG. 1   f,  a second photoresist pattern  170  is formed over the resulting structure, including the second polysilicon layer  160  and the first polysilicon pattern  120   a.  The second photoresist pattern  170  may be formed over a cell region of the semiconductor substrate to allow for patterning of the peripheral circuit region and the inter-connection region. 
         [0019]    A process for forming a pattern is then performed on the peripheral circuit region and the inter-connection region (not shown). 
         [0020]    Referring to  FIG. 1   g,  the second photoresist pattern  170  is removed. 
         [0021]    The spacers  150  are removed to form a fine pattern including the first polysilicon pattern  120   a  and the second polysilicon layer  160 . 
         [0022]    In the above-described conventional method for forming a pattern of a semiconductor device, residual polysilicon remains on sidewalls of the spacer during an etch-back process performed after forming the polysilicon layer, so that a subsequent process for removing the residual polysilicon is required. The entire polysilicon layer having a large open area is etched, so that a subsequent patterning process cannot be performed without forming a second photoresist pattern over the cell region. 
       BRIEF SUMMARY OF THE INVENTION 
       [0023]    Various embodiments of the invention are directed to providing a method for forming a pattern of a semiconductor device having one or more benefits, such as controlling a fine critical dimension and improving an overlay characteristic of the device. 
         [0024]    According to an embodiment of the invention, a method for forming a pattern of a semiconductor device comprises: forming a first mask pattern over a semiconductor substrate; forming a spacer film over the resulting structure including the first mask pattern; forming a polysilicon layer over the resulting structure including the spacer film; performing a planarizing process to expose the spacer film; forming a photoresist pattern over a portion of the resulting structure including the planarized polysilicon layer, such that a part of the polysilicon layer is exposed; etching the polysilicon layer with the photoresist pattern as a mask to form a second mask pattern; removing the photoresist pattern; and removing the exposed spacer film. 
         [0025]    According to another embodiment of the invention, a method for manufacturing a semiconductor device comprises: forming a hard mask layer and a first polysilicon layer over a semiconductor substrate including a cell region, an inter-connection region, and a peripheral circuit region; etching the first polysilicon layer to form a first mask pattern; forming a spacer film over the resulting structure including the first mask pattern; forming a second polysilicon layer over the resulting structure including the spacer film; performing a planarizing process to expose the spacer film disposed over a top of the first mask pattern; forming a photoresist pattern over a portion of the resulting structure including the planarized second polysilicon layer, so that a part of the second polysilicon layer is exposed; etching the second polysilicon layer using the photoresist pattern as a mask to form a second mask pattern; removing the photoresist pattern; removing the spacer film exposed on sidewalls and the top portion of the first mask pattern; and etching the hard mask layer using the first and second mask patterns as a mask to form a hard mask pattern. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0026]    For a more complete understanding of the disclosure, reference should be made to the following detailed description and accompanying drawings. 
           [0027]      FIGS. 1   a  to  1   g  are cross-sectional diagrams illustrating a conventional method for forming a pattern of a semiconductor device. 
           [0028]      FIGS. 2   a  to  2   g  are cross-sectional diagrams illustrating a method for forming a pattern of a semiconductor device according to an embodiment of the invention. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0029]      FIGS. 2   a  to  2   g  are cross-sectional diagrams illustrating a method for forming a pattern of a semiconductor device according to an embodiment of the invention. 
         [0030]    Referring to  FIG. 2   a,  a hard mask layer is formed over a semiconductor substrate (not shown) that includes a cell region (I) including a word line, a drain select line (DSL), and a source select line (SSL); an inter-connection region (II) for interconnecting metal with a metal line; and a peripheral circuit region (III) including peripheral circuits. The hard mask layer includes one selected from an oxide film  310 , a nitride film  300 , and a combination thereof. 
         [0031]    In this embodiment, the hard mask layer includes a nitride film  300  and an oxide film  310 . 
         [0032]    A first polysilicon layer  320  is formed over the oxide film  310 . 
         [0033]    A first photoresist pattern  330  is formed over the first polysilicon layer  320 . 
         [0034]    The first photoresist pattern  330  of the cell region (I) defines a word line pattern, a drain select line (DSL) and a source select line (SSL). The first photoresist pattern  330  that defines the word line pattern may have a critical dimension (CD) smaller than that of the first photoresist pattern  330  that defines the DSL pattern and the SSL pattern. The first photoresist pattern  330  that defines the word line pattern has a pitch larger twice than that of a word line pattern which is formed later. 
         [0035]    The first photoresist pattern  330  elements formed in the inter-connection region (II) define a part of a pattern to be subsequently formed in the inter-connection region (II). The first photoresist pattern  330  elements formed in the peripheral circuit region (III) preferably define all patterns to be subsequently formed in the peripheral circuit region (III). 
         [0036]    Referring to  FIG. 2   b,  the first polysilicon layer  320  is etched using the first photoresist pattern  330  as a mask to form a first mask pattern  320   a.    
         [0037]    The first photoresist pattern  330  is then removed. 
         [0038]    Referring to  FIG. 2   c,  an oxide film  340  having a given thickness is formed over the resulting structure including the first mask pattern  320   a.    
         [0039]    The oxide film  340  can be deposited to a thickness sufficient to secure a space critical dimension (CD) of the final pattern because the thickness of the oxide film  340  determines the space CD of the final pattern. The space CD refers to the size of a region between adjacent final pattern elements. 
         [0040]    Referring to  FIG. 2   d,  a second polysilicon layer  350  is formed over the resulting structure including the oxide film  340 . A planarizing process is performed to expose the oxide film  340 . 
         [0041]    The second polysilicon layer  350  remains in the region between adjacent first mask pattern  320   a  elements including the oxide film  340 . 
         [0042]    The planarizing process is preferably a chemical mechanical polishing (CMP) process. The oxide film  340  deposited over the first mask pattern  320   a  serves as an etching barrier film for the CMP process. 
         [0043]    When the CMP process is performed using the oxide film  340  as a barrier, the entire polysilicon layer is etched, so that residual polysilicon does not remain which requires a second patterning process to remove. 
         [0044]    Referring to  FIG. 2   e,  a second photoresist pattern  360  is formed over the semiconductor substrate (not shown) including the planarized second polysilicon layer  350 . Preferably, the second photoresist pattern  360  is formed over a portion of the semiconductor substrate (not shown) including the planarized second polysilicon layer  350  so that a portion of the second polysilicon layer  350  remains exposed. 
         [0045]    The second photoresist pattern  360  is preferably formed over a local word line region of the cell region (I) and over a local pattern region, which is not defined by the first mask pattern  320   a.    
         [0046]    The second photoresist pattern  360  element formed in the inter-connection region (II) can be overlapped with the first mask pattern  320   a  element formed in the inter-connection region (II). 
         [0047]    Referring to  FIG. 2   f,  the exposed second polysilicon layer  350  is etched to form a second mask pattern  350   a.    
         [0048]    The second polysilicon layer  350  between the first mask pattern  320   a  elements that define the DSL pattern and SSL pattern of the cell region (I) is removed. A second mask pattern  350   a  is formed adjacent to the first mask pattern  320   a  element including the oxide film  340  formed in the inter-connection region (II). 
         [0049]    The second photoresist pattern  360  is then removed. 
         [0050]    Referring to  FIG. 2   g,  the exposed oxide film  340  is removed, preferably, by a dip-out process. 
         [0051]    The second mask pattern  350   a  serves as a mask, so that the oxide film  340  disposed on a bottom portion of the second mask pattern  350   a  remains after the dip-out process. 
         [0052]    An etching process is performed using the first mask pattern  320   a  and the second mask pattern  350   a  as a mask to form a fine pattern in the cell region (I), the inter-connection region (II), and the peripheral circuit region (III). For example, the first mask pattern  320   a  and the second mask pattern  350   a  may be used as a mask to form a hard mask pattern (not shown). 
         [0053]    As described above, in a method for forming a pattern of a semiconductor device according to an embodiment of the present invention, a polysilicon layer does not remain in a large open area during an etch-back process, so that a material layer that serves as a barrier in a second patterning process is not required. As a result, the method can control a fine CD required in the second patterning process and improve an overlay characteristic. 
         [0054]    The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the type of deposition, etching, polishing, and patterning steps described herein. Nor is the invention limited to any specific type of semiconductor device. For example, the present invention may be implemented in a dynamic random access memory (DRAM) device or non-volatile memory device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.