Abstract:
An operation method for controlling paged memory access attribute of the memory and its structure, particularly a control method for a low-level driver or system chipset to perform the control of read and write to partial areas of the memory, mainly by means of making use of buffer memory to configure procedures to perform operation area configuration of memory, and by means of practical operation procedures to confirm the operation mode of the said area, to further control said region in such modes as read only, write only, write once, read once, etc., to prevent programs which have been loaded into the memory and will be executed and passwords which have been verified from being intruded by illegal hacker, virus, etc, to provide a common protective design to the system safety.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to an operation method for controlling paged memory access attribute of the memory and its structure, and more particularly, to an attribute configuration for controlling operation of the paged memory, making the memory page no more comprehensively receive the storage data from CPU or hard disk, but further control and manage the data flow to provide system safety as a common protective design.  
           [0003]    2. Description of the Prior Art  
           [0004]    Whereas, dynamic random access memory (hereinafter referred to as DRAM) appears in the form of paged memory; that is, DRAM is composed of continuous memory pages or continuous storage cells, for example, the size of each paged memory is 4K Bytes, then 16M DRAM can be divided into 4000 units of memory pages (000˜FFF) of the size of 4K.  
           [0005]    CPU performs the read/write control to DRAM through the chipset. The data intended to execute in a hard disk shall be written into DRAM first, then CPU shall read the data from DRAM for processing, or after the data processing performed by CPU, the processed data shall be written into DRAM, and then the hard disk will read data back from DRAM. The operation of DRAM storage is counted in paged memory. In other words, concerning the system operation of a computer in general, DRAM provides basic actions of data storage and retrieval.  
           [0006]    As the world has gradually progressed towards computerization and digitalization, many commercial behaviors have turned to information technology application. While enjoying the efficiency, convenience and commercial opportunity brought by Internet and Intranet, computer and network safety has been gradually concerned. On the other hand, concerning computer crime, no matter in terms of technology, revision level or amount of crime, all show the tendency of skill improving and amount increasing. Therefore, most people select cryptographic system for protecting their important data. However, no matter whichever cryptographic system, the public key, the private key, or the password of the system itself or set additionally, after the cryptographic system is started, it shall be loaded in DRAM and then checked. Since DRAM is a necessary passing device of system data, and it can only receive the data conveyed from CPU or hard disk without selecting, therefore, no matter legal service of DRAM (system itself) or through intrusion of external party, all data can be easily accessed and revised. For example, a hacker may intrude into DRAM to retrieve the public key, private key and password data of the cryptographic system to change the check operation to check approval or no operation through some software (such as soft ICE), and the system can be easily accessed. Furthermore, as the virus in a floppy disk or a optical disk is loaded into DRAM, through execution of CPU to damage or revise the important parameter in a system, these parameters may cause such influences as the configuration of memory in DRAM, the division of disk driver and the access authority of a user in using the system, etc. and make the system shut down, be damaged or unable to work normally or function in an abnormal manner. The general anti-virus programs work through comparing the virus code in a floppy disk or DVD, once the user fails to update it in time, some unknown viruses still get chances to access to DRAM and make the system shut down through execution of CPU, thus the virus written into DRAM cannot be prevented, therefore, effective prevention method still cannot be provided.  
         SUMMARY OF THE INVENTION  
         [0007]    In view of this, the major object of this invention is to provide a kind of operation method for controlling the paged memory access attribute of the memory, in particular to provide a control method for low-level driver or system chipset to perform read/write operation to partial areas of the memory, mainly by means of using register configuration procedure to perform the operable region configuration of the memory, and by means of practical operation procedure to confirm the operation mode of the said region, to further control the said region for read-only, write-only, write-once, read-once, etc., to ensure the data loaded in the memory, which include the program which will be executed and the password which will be checked, etc., to be free from the intrusion from hackers, viruses, etc., and to provide a common protection for system safety.  
           [0008]    It is another object of the present invention is to provide a common protection for system safety to ensure the data loaded in the memory, which include the program which will be executed and the password which will be checked, etc., to be free from the intrusion from hackers, viruses, etc. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    [0009]FIG. 1 is a structure diagram of DRAM in accordance with the present invention;  
         [0010]    [0010]FIG. 2 is the method flow diagram in accordance with the present invention;  
         [0011]    [0011]FIG. 3 is the hardware diagram of the attribute configuration in accordance with the present invention;  
         [0012]    [0012]FIG. 4 is the Read Redirect attribute procedure flow diagram in accordance with the present invention; and  
         [0013]    [0013]FIG. 5 is the Write Redirect attribute procedure flow diagram in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0014]    Referring to FIG. 1, the DRAM structure of the present invention is shown, comprising of a DRAM module  10 , a memory controller  20 ; each DRAM module  10  includes a plurality of DRAM  11 , wherein said DRAM  11  includes a plurality of memory pages  12  (in FIG. 1, only one DRAM  11  is developed for explanation); said memory controller  20  comprises of one controller  21  which controls access to each paged memory  11 , in which a memory  22  is devised (flash memory is used in the example) to store the configuration procedure result (wherein operation method is shown as follows in detail); a static random access memory  23  (hereinafter referred to as SRAM  23 ), which stores fast page query table, and includes a plurality of instruction bits which redirect to memory page  12  is used to instruct whether said memory page  12  is conducted in normal access mode or in page operation mode (wherein operation is described in detail as follows).  
         [0015]    The said SRAM  23  may also be replaced with one register file (Fig. No. is not shown). The disadvantage of a register file lies in its larger number of the logic gates, which occupy more IC areas, and are not applicable to larger capacity, but its access is more flexible and able to be selected in view of the system requirement.  
         [0016]    The present invention performs read/write control for the partial area of DRAM  1  through low-level driver or system chipset  30  (as shown in FIG. 3) which is use to control the DRAM  11 , as shown in FIG. 2 and includes such two parts as register setting procedure A and real operation procedure B.  
         [0017]    The said register setting procedure A is to, before processing memory page  12  of DRAM  11 , set the memory page  12  area of DRAM  1 , which is desired to be under control; after starting computer system, BIOS shall be executed first, and register setting procedure A engages in configuring during this period, while since control authority is not yet handed to the operation system and CPU  40 , therefore, this register setting procedure cannot be changed after completion of configuration. The said register setting procedure includes the following steps:  
         [0018]    Step A 1 , configure the area of DRAM  11  to define the attribute of memory page  12 , including start location of the said area, end location of the said area, page number and page size, etc., to define the partial area of DRAM  11  under the direct control of the low-level driver.  
         [0019]    Step A 2 , determine the attribute of memory page  12 , and formulate a Table of Look-Aside Buffer (TLB) according to the above mentioned configuration result to point out an attribute table of a single memory page  12  (as 003, 008 shown in Table 1) or a section of a memory page (such as A02˜A08 shown in Table 1), to be saved in the Flash memory  22  of DRAM  11 .  
         [0020]    Step A 3 , according to the above mentioned configuration result, formulate a Fast Page Lookup Table (FPLT) and store it in SRAM  23  of DRAM  11 . The said FPLT is used for instructing the said memory page  12  to operate in the normal access mode or in the page attribute operation mode.  
                                                                 TABLE 1                                       Page Attribute            Page   Error   Read   Read   Read   Write   Write   Write   Read   Write       No.   Redirect   Only   Once   Twice   Only   Once   Twice   Redirect   Redirect               003   FFD   No   No   No   No   No   No   No   No       008   No   Yes   Yes   No   No   Yes   No   No   No       A02   FFE   No.   No   No   Yes   Yes   Yes   No   No                  
 
         [0021]    The said practical operation procedure B includes the following steps:  
         [0022]    Step B 1 : inspect the Fast Page Lookup Table (FPLT) stored in SRAM  23 , to confirm that memory page  12  is engaged in the normal operation mode, or in the page operation mode through configuring page attribute.  
         [0023]    Step B 2 : inspect the Table of Look-Aside Buffer (TLB) stored in flash memory  22 , to confirm the operation attribute of the said memory page  12 .  
         [0024]    Step B 3 , carry out the operation of executed attribute.  
         [0025]    Taking a 16M DRAM module for example, it can be divided into 4000 segments, each of which is a memory page of 4K(000˜FFF). SRAM  23  also has 4000 bits redirecting to the memory page  12  of each DRAM  11  respectively so as to instruct whether the said memory page  12  is carried out in the normal access mode or in the page attribute operation mode. As the SRAM  23  bit which redirects to a certain memory page  12  is “0”, it indicates the said memory page is in the normal access mode; as the SRAM 23  bit is “1”, it indicates the said memory page is in the Page Operation mode. Then the system will inspect the Table of Look-Aside Buffer (TLB) to confirm the attribute of the said page (shown as Table 2).  
         [0026]    For example, as the Fast Page Lookup Table (FPLT) of page 008 is “1”, it will inspect the Table of Look-Aside Buffer (TLB) to confirm the operation attribute of page 008. From Table 1, it is known the attribute of the said memory page  12  is configured to be read only, therefore, the memory page 008 will only provide read, but not write operation.  
                                                                                                                 TABLE 2                       Page   000   001   002   003   . . .   008   . . .   A02   A03   . . .   FFC   FFD   FFE   FFF                                FPLT   1   0   0   1       1       1   1                  
 
         [0027]    The said low-level driver mainly attempts to control the DRAM to perform such functions as read only, write only, write once, etc. The configuration and function of each attribute shall be described separately as follows:  
         [0028]    [A] Read Only  
         [0029]    As this area is configured to be read only, it performs Data Bus Mask (DQM) or masks Write Enable; in other words, it changes the sign of write cycle to read cycle, and is unable for writing any data to this area. Although any write instruction of CPU  40  shall be still in the normal operation, write operation is invalid because DQM or Write Enable is masked. Therefore, it shall not interfere the normal operation of CPU  40 . Or in write cycle, the system chip simply returns CPU  40  a ready signal, indicating the write action is complete, making the CPU  40  write cycle actually performs a no operation status, and the write instruction will not be executed.  
         [0030]    The read only function can be applied to system security. The password position where the CPU 40  read from DRAM  11  is configured to Read Only. Thus hackers will be unable to enter into the computer system through revising or changing.  
         [0031]    Take virus for another example. As the program is stored into the configured area in DRAM  11  waiting for being executed, since this area has been configured to read only, then during program execution, virus code cannot be written in and it can prevent the execution file from being contaminated. In other words, the invention blocks off the intrusion of the virus at the entrance of the execution program no matter whether the computer system has virus code or not, it will never be executed.  
         [0032]    [B] Write Only  
         [0033]    Referring to FIG. 3, the data terminal of DRAM  11  is connected to an input terminal of a switch  50  and a random generator  60  is connected to another input terminal of the switch  50 . The said switch  50  is under the control of a signal of write only control—wo.ctl. As wo.ctl is “0”, the switch  50  will connect to CPU  40 , and forward data to DRAM 11 . As wo.ctl is “1”, the switch  50  will forward the random data generated by the random generator  60  to CPU  40 . As the attribute of this area is configured to be write only, the signal wo.ctl of write only control will be configured to be “1”. At this time, the write action will have no difference with DRAM  11  in general. If data are desired to be read from this area, the switch  50  will forward random data to CPU  40  to get the invalid data; that is, any read instruction of CPU  40  is still under normal operation, but because the read data are random, it forms an invalid read operation without interference of normal operation of CPU  40 .  
         [0034]    [C] Read Once  
         [0035]    Referring to FIG. 3, as this area is configured to be read once, the said switch  50  is under the control of a time counter  70 .  
         [0036]    While carrying out the read action for the first time, it is general normal read action; while assigning a read instruction again, the time counter  70  (with configuration attribute value as “1”) shall forbid the emergence of this action and by switching the switch  50  to random generator  60 , what is read now is an invalid random number.  
         [0037]    [D] Write Once  
         [0038]    While configuring this area to be write once, the low-level driver will first inspect the starting address of the area and the terminating address of the area. If the area within is written into data, the said low-level driver will not permit data to be written in again.  
         [0039]    Referring further to FIG. 3, the said time counter  70  will make record when write action happens; once finding that it has been written once, the low-level driver will not permit data to be written into again.  
         [0040]    Besides, times can be configured through low-level driver. Thus the times of being written into the said area can be configured flexible and form an attribute of write N times (N as the configuration value) or read N times.  
         [0041]    [E] Read Redirect (Referring to FIG. 4)  
         [0042]    While configuring this area to be read redirect, at least one memory page  12  shall be configured first to serve as protection area (step a), and duplicate the memory page which saves such important data as access authority, public key, private key, etc. (hereinafter referred to as the storage area) into the protection area (step b). If write action is discovered in the storage area, the system will not immediately accept the instruction and take action, but will first inspect whether the change of the content is legal (step c). If legally, the changed storage area will be duplicated into the protection area and the system can read the data from the protection area for operation (step d). If it is discovered to be illegal write, the wrong information or a write action which should not be made, the system will redirect the data in the protection area to the storage area, making the system recover to its original status (step e) and making the write action to form an invalid one so that the important data cannot be changed.  
         [0043]    [F] Write Redirect (Referring to FIG. 5)  
         [0044]    While configuring this area to be write redirect, at least one memory page shall be configured first to serve as protection area (step a), and each information which is desired to be written into DRAM will first be saved into the protection area (step b), to judge whether data may produce damage to the system (step c). If not, the information will be transferred to the designated memory page by the system for storage (step d). If with damage, the write data will be retained continuously in the protection area without action (step e). It makes DRAM to be unable to perform a function in accordance with the revision content immediately, which provides a data re-inspecting path.  
         [0045]    Taking for example, assuming the memory page  2  serves for the storage area for access authority (or public key, private key, etc.), the content of the access right which has been revised shall be restored into the area  2 , thus the system can open proper resource to the user in accordance with the newly configured authority. In general, the revision of access authority may include such three approaches as system authorization, virus, worm planted by a hacker. A virus code or a hacker normally intrudes through the revision of the system stack, while the revised stack position may be such commands as interrupt, the inspection of the user&#39;s access authority, etc. Once it is revised and duplicated into the second memory page, the system will immediately respond and receive the new access authority, thus a hacker may become the super user to get access to any resource of the system, or to change the interrupt signal of the existing intent for accessing the hard disk data to delete the data of hard disk, or format hard disk, etc. so as to damage the completeness of hard disk data and make the system unable to operate normally.  
         [0046]    Therefore, in the attribute of read redirect in the present invention, we may put the data of the recognized user&#39;s access authority into the protection area (hereby it is explained in memory page  10 ). After the user&#39;s access authority is revised, it will be saved in the protection area of memory page  10  first to judge whether it is a legal revision (such as, the judgment that stack push-down and stack pop-up command are in balance or overflow); if it is legal, the data in the protection area of memory page  10  will be transferred to page  2 , making the computer accept the content which has been revised and operate in accordance with it, otherwise it will continuously be stored in the protection area and separate from the system to terminate the chance of any illegal revision or virus intrusion.  
         [0047]    In addition, among the above various attribute configuration, once the switch is turned to random generator  60  to forward the invalid random number to CPU, making CPU unable to perform various contrary functions of the configured attributes vs. DRAM (for example: in read only attribute, CPU cannot perform write function, etc.). In other words, during this period of time, CPU and DRAM are in segregative status, but can still perform normal access operation to other control units in the system.  
         [0048]    Concluding the above, the operation method of memory page access attributes provided by the present invention concerning memory control and its structure, can further perform attribute configuration and then confirm the memory page attribute. It can increase DRAM operation function, not receive the storage data from CPU or hard disk across-the-board any more, and further control and manage the data flow to provide a common protection for the system safety. It offers a valid solution and measures in allusion to the disadvantage of a traditional safety system that is unable to provide comprehensive protection to DRAM and actually conforms to the conditions of invention patent application.