Abstract:
A DC-to-DC converter which includes a current mode switching controller or regulator chip (which includes an oscillator producing a ramped voltage which periodically increases at a fixed ramp rate), circuitry including a current sense resistor external to the integrated circuit controller, and ramp adjustment circuitry (including at least one element external to the integrated circuit controller) which sets the effective ramp rate of the oscillator&#39;s ramped voltage. The external element of the ramp adjustment circuitry can be a resistor or a capacitor, or circuitry comprising both a resistor and capacitor. Another aspect of the invention is a DC-to-DC conversion method using a current mode switching controller or regulator chip (controller chip) including an oscillator which produces a ramped voltage, and external circuitry (coupled to the controller chip) including a current sense resistor across which a feedback voltage is developed, including the steps of operating the controller chip to switch on the power switch periodically and switch off the power switch at times determined by comparison of a feedback signal indicative of the feedback voltage and an adjustment voltage, with a reference signal indicative of the ramped voltage and a reference potential, where comparison of the feedback signal with the reference signal is effectively comparison of the feedback voltage with the difference between the reference potential and an effective ramped voltage determined by the ramped voltage and the adjustment voltage; and developing the adjustment voltage across at least one adjustment element external to the controller chip such that the adjustment voltage varies in phase with the ramped voltage and periodically increases at a fixed adjustment rate determined by the at least one adjustment element.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to switching power supply circuitry which employs current mode control to achieve output voltage regulation. More specifically, the invention relates to DC-to-DC converters which include a current mode switching controller or regulator (implemented as an integrated circuit, including an oscillator which produces a ramped voltage which periodically increases at a fixed ramp rate), circuitry (including a current sense resistor) external to the integrated circuit controller or regulator, and ramp adjustment circuitry (including an element external to the integrated circuit) which sets the effective ramp rate of the oscillator&#39;s ramped voltage. 
     2. Description of the Related Art 
     FIG. 1 is a conventional DC-to-DC converter which includes current mode switching controller  1  which is implemented as an integrated circuit (chip), and boost converter circuitry which is external to controller chip  1 . The boost converter circuitry comprises NMOS transistor N 1  (which functions as a power switch), inductor L, current sense resistor R s , Schottky diode D, capacitor C out , feedback resistor divider R F1  and R F2 , compensation resistor R c , and compensation capacitor C c , connected as shown. The FIG. 1 circuit produces a regulated DC output voltage V out  across load R o , in response to input DC voltage V in . 
     Controller chip  1  includes oscillator  2  (having a first output and a second output), comparator  8 , driver  6  which produces an output potential V DR  at pad  12  (to which the gate of switch N 1  is coupled), latch  4  (having “set” terminal coupled to oscillator  2 , “reset” terminal coupled to the output of comparator  8 , and an output coupled to the input of driver  6 ), error amplifier  10  (having a non-inverting input maintained at reference potential V ref ), and circuit  9  (having a first input coupled to the second output of oscillator  2 , a second input coupled to pad  13 , and an output coupled to the inverting input of comparator  8 ). 
     Pad  13  is at potential V c , which is determined by the output of error amplifier  10  (in turn determined by the difference between the instantaneous potential at Node A and the reference potential V ref ) and the values of external resistor R c  and capacitor C c . Reference potential V ref  is set (in a well known manner) by circuitry within chip  1 , and is normally not varied during use of the circuit. In order to set (or vary) the regulated level of the output voltage V out , resistors R F1  and R F2  with the appropriate resistance ratio R F1 /R F2  are employed. 
     Oscillator  2  asserts a clock pulse train (having fixed frequency and waveform as indicated) at its first output, and each positive-going leading edge of this pulse train sets latch  4 . Each time latch  4  is set, the potential V DR  asserted by driver  6  to the gate of transistor N 1  causes transistor N 1  to turn on, which in turn causes current I L  from the source of N 1  to increase in ramped fashion (more specifically, the current I L  increases as a ramp when transistor N 1  is on, and is zero when transistor N 1  is off. The current through diode D is zero when N 1  is on, it increases sharply when N 1  switches from on to off, then falls as a ramp while N 1  is off, and then decreases sharply to zero when N 1  switches from off to on). Although transistor N 1  turns on at times in phase with the periodic clock pulse train, it turns off at times (which depend on the relation between reference potential V ref  and the instantaneous potential at Node A) that have arbitrary phase relative to the pulses of the periodic clock pulse train. 
     Oscillator  2  asserts ramped voltage V osc  (which periodically increases at a fixed ramp rate and then decreases, with a waveform as indicated) at its second output. Circuit  9  asserts the potential V c −V osc  to the inverting input of comparator  8 . Assertion of the potential V c −V osc  (rather than V c ) to comparator  8  is necessary for stability. 
     The non-inverting input of comparator  8  is at potential V s =I L R s , which increases in ramped fashion in response to each “set” of latch  4  by oscillator  2 . When V s =V c −V osc  (after latch  4  has been set), the output of comparator  8  resets latch  4 , which in turn causes the potential V DR  asserted by driver  6  to the gate of transistor N 1  to turn off transistor N 1 . Thus, by the described use of both of the signals output from oscillator  2 , and feedback asserted to error amplifier  10  from Node A, controller chip  1  switches transistor N 1  on and off with timing that regulates the output potential V out  of the FIG. 1 circuit. 
     However, the conventional circuit of FIG. 1 has an important disadvantage. Although the ramp rate of the oscillator output V osc  is fixed, the optimal value of this rate varies from application to application and depends on the particular implementation of the circuitry external to controller chip  1  (the optimal oscillator ramp rate depends on a number of parameters including the level of input potential V in  and the inductance of inductor L). Thus, since the ramp rate of the oscillator output V osc  is fixed, it is difficult to implement the FIG. 1 circuit so as to be stable for use with a wide range of values of input potential V in , and with an acceptably wide range of characteristics of its external circuit components (such as the inductance of inductor L). 
     The inventor has recognized that it would be desirable to improve the FIG. 1 circuit so that the effective ramp rate of the oscillator output V osc  is variable. The inventor has also recognized that it would be desirable to so improve the FIG. 1 circuit without increasing the number of external pins to the controller chip of the improved circuit. 
     Other conventional DC-to-DC converters include a current mode switching controller implemented as an integrated circuit (as does the FIG. 1 circuit), but also include circuitry (e.g., buck converter circuitry) other than boost converter circuitry that is external to the controller chip. The circuitry external to the controller chip includes a current sense resistor, and the controller chip includes an oscillator which produces a ramped voltage which periodically increases at a fixed ramp rate. This class of conventional converters is also subject to the above-noted disadvantage of the FIG. 1 circuit. 
     We shall use the expression “current mode switching regulator” chip herein to denote a circuit which performs the functions of a “current mode switching controller” chip (e.g., controller  1  of FIG. 1) but which also includes an on-board power switch. In contrast, a “current mode switching controller” chip does not include an on-board power switch and must be used with an external power switch (e.g., controller chip  1  of FIG. 1 is used with NMOS transistor N 1  which is external to controller chip  1 ). 
     Another type of conventional DC-to-DC converter differs from the FIG. 1 circuit (or the above-mentioned variations thereon) in that the current mode switching controller chip is replaced by a current mode switching regulator chip. The current mode switching regulator chip in each such converter does not include a sense resistor, and instead is used with an external sense resistor (such as resistor R s  of FIG.  1 ). For example, one such converter employs a current mode switching regulator chip that differs from chip  1  of FIG. 1 in that counterparts to NMOS transistor N 1  and resistors R f1  and R f2  are implemented on-board the regulator chip. In this latter type of converter, the circuitry that is external to the regulator chip does not include an external power switch, but it does include an external sense resistor (e.g., an external sense resistor identical to resistor R s  of FIG.  1 ). This class of conventional converters is also subject to the above-noted disadvantage of the FIG. 1 circuit. 
     SUMMARY OF THE INVENTION 
     In a class of embodiments, the invention is a DC-to-DC converter which includes a current mode switching controller (implemented as an integrated circuit, and including an oscillator which produces a ramped voltage which periodically increases at a fixed ramp rate), circuitry (including a current sense resistor) external to the integrated circuit controller, and ramp adjustment circuitry (including at least one element external to the integrated circuit controller) which sets the effective ramp rate of the oscillator&#39;s ramped voltage. In some such embodiments, the external element of the ramp adjustment circuitry (the element external to the integrated circuit controller) is a resistor. In other ones of such embodiments, the external element of the ramp adjustment circuitry is a capacitor. In some embodiments, the external element of the ramp adjustment circuitry is a resistor R r  and the effective ramp rate is dV osc /dt+(d(i r )/dt)R r , where V osc  is the ramped voltage produced by the oscillator and i r  is a current determined by the ramp adjustment circuitry. In other embodiments, the external element of the ramp adjustment circuitry is a capacitor C r  and the effective ramp rate is dV osc /dt+i r /C r , where V osc  is the ramped voltage produced by the oscillator and i r  is a current determined by the ramp adjustment circuitry. In other embodiments, the external element of the ramp adjustment circuitry comprises a capacitor C r  and a resistor R r2  (having one end at potential V and another end coupled to the capacitor C r ), and the effective ramp rate is dV osc /dt+V/R r2  C r , where V osc  is the ramped voltage produced by the oscillator and i r  is a current determined by the ramp adjustment circuitry. 
     In another class of embodiments, the invention is a DC-to-DC converter which differs from the previously mentioned embodiments only in that the current mode switching controller chip is replaced by a current mode switching regulator chip (with “current mode switching regulator” denoting a circuit which performs all functions of a “current mode switching controller” but which also includes an on-board power switch, in contrast with a “current mode switching controller” chip, which does not include an on-board power switch and must be used with an external power switch). 
     For convenience, the expression “current mode switching controller” chip (integrated circuit) is used in the claims to denote an integrated circuit in a broad class of integrated circuits consisting of both “current mode switching regulators” (each including an on-board power switch) and “current mode switching controllers” (which do not include an on-board power switch, but are used with an external power switch). 
     Another aspect of the invention is a method for performing DC-to-DC conversion using a current mode switching controller chip and external circuitry coupled to the controller chip, wherein the external circuitry includes a current sense resistor across which a feedback voltage is developed and the controller chip includes an oscillator which produces a ramped voltage which periodically increases at a fixed ramp rate, the method including the steps of: 
     operating the controller chip to switch on the power switch periodically and switch off the power switch at times determined by comparison of a feedback signal, indicative of the feedback voltage and an adjustment voltage, with a reference signal indicative of the ramped voltage and a reference potential, wherein said comparison of the feedback signal with the reference signal is effectively a comparison of the feedback voltage with the difference between the reference potential and an effective ramped voltage, wherein the effective ramp voltage is determined by the ramped voltage and the adjustment voltage; and 
     developing the adjustment voltage across at least one adjustment element external to the controller chip, such that the adjustment voltage varies in ramped fashion in phase with the ramped voltage, wherein the adjustment voltage periodically increases at a fixed adjustment rate determined by at least one characteristic of said at least one adjustment element. In some such embodiments, the at least one external element is a resistor. In other ones of such embodiments, the at least one external element is a capacitor. In other ones of such embodiments, the at least one external element is a resistor and a capacitor coupled to the resistor. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a conventional DC-to-DC converter including external boost controller circuitry. 
     FIG. 2 is a schematic diagram of a preferred embodiment of the inventive DC-to-DC converter which includes a controller chip (integrated circuit  101 ), external boost controller circuitry, and ramp adjustment circuitry (including a resistor R r  external to the controller chip). 
     FIG. 2A is a schematic diagram of a variation on the FIG. 2 embodiment, in which power switch N 1  (an NMOS transistor) is incorporated within current mode switching regulator chip  101 A. 
     FIG. 3 is a simplified schematic diagram of the FIG. 2 embodiment, showing principal elements of the circuitry. 
     FIG. 4 is a simplified schematic diagram of a variation on the embodiment of FIGS. 2 and 3 in which the ramp adjustment circuitry includes a capacitor C r  external to the controller chip. 
     FIG. 5 is a simplified schematic diagram of another variation on the embodiment of FIGS. 2 and 3 in which the ramp adjustment circuitry includes a capacitor C r  and a resistor R r2  external to the controller chip. 
     FIG. 6 is a simplified schematic diagram of another preferred embodiment of the inventive DC-to-DC converter which includes a controller chip (integrated circuit  104 ), external buck controller circuitry, and ramp adjustment circuitry (including a resistor R r  external to the controller chip). 
     FIG. 7 is a simplified schematic diagram of a variation on the FIG. 6 embodiment of the invention in which the ramp adjustment circuitry includes a capacitor C r  external to the controller chip. 
     FIG. 8 is a simplified schematic diagram of another variation on the FIG. 6 embodiment of the invention in which the ramp adjustment circuitry includes a capacitor C r  and a resistor R r2  external to the controller chip. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A preferred embodiment of the inventive circuit will be described with reference to FIGS. 2 and 3. This embodiment is a DC-to-DC converter which includes a controller chip (integrated circuit  101 ), external boost controller circuitry identical to that of FIG. 1, and ramp adjustment circuitry. The ramp adjustment circuitry comprises voltage-to-current conversion circuitry  11  and NMOS transistor N 2  (connected as shown within chip  101 ) and resistor R r  (connected between pad  14  and the source of transistor N 1 , external to controller chip  101 ). Elements of the circuit of FIGS. 2 and 3 which are identical to corresponding elements of FIG. 1 are identically labeled in FIGS. 1-3, and the foregoing description of these elements will not be repeated with reference to FIGS. 2 and 3. 
     FIG. 3 is a simplified version of the circuit diagram of FIG. 2 embodiment, which omits elements  2 ,  4 ,  6 ,  8 ,  9 , and  10  of controller chip  101  for clarity. FIG. 3 shows several pins of chip  101  which are not shown in FIG.  2 : pins for connection to ground (pins “AGND” and “PGND”, where AGND denotes analog ground, a sensitive ground for analog circuitry, and PGND denotes power ground which is noisier than AGND and should be separated from AGND), a pin for connection to a supply potential (pin “V PR ”), and a pin for connection to resistor R 1  (pin “FREQ”). The pin labeled “PGND” is connected to resistor R s  in FIG.  3 . The pin “FREQ” is connected to oscillator  2  such that the fixed frequency of the clock pulse train produced by oscillator  2  is determined by the value of resistor R 1 . Chip  101  of FIGS. 2 and 3 has the same number of pins as does conventional chip  1  of FIG.  1 . 
     Controller chip  101  of FIGS. 2 and 3 differs from chip  1  of FIG. 1 in that chip  101  includes voltage-to-current conversion circuitry  11  and NMOS transistor N 2 . Transistor N 2  (whose drain is coupled to pad  14 , and whose gate is coupled to the inverted output of latch  4 ) is provided to discharge, each time transistor N 1  is switched off, any stray capacitance C p  at pad  14 . 
     In operation of the FIG. 2 circuit, when driver  6  has switched transistor N 1  on (so that the current I L  through the channel of N 1  is increasing in ramped fashion), the potential at pad  14  (and thus at the non-inverting input of comparator  8 ) is V′ s =I L R s +i r R r =V s +i r R r . The potential V′ s  increases in ramped fashion in response to each “set” of latch  4  by oscillator  2 . After latch  4  has been set, the latch  4  resets (causing driver  6  to assert a potential V DR  to the gate of transistor N 1  which turns off transistor N 1 ) when V c −V osc =V s  +i r R r . In other words, latch  4  resets and transistor N 1  switches off when V c −(V osc +i r R r )=V s . Current i r , an internal current ramp produced by circuit  11  (in response to ramped voltage V osc  produced by oscillator  2 ), has the same waveform and frequency as does the ramped voltage V osc . 
     Thus, provision of the extra elements  11 , N 2 , and R r  in the FIG. 2 embodiment results in an effective ramp rate of d(V osc +i r R r )/dt for oscillator  2 &#39;s ramped voltage. The magnitude of the added ramp compensation is [d(i r )/dt]R r , which is determined by the value of external resistor R r  and the characteristics of circuit  11 . Typically, the resistance of resistor R r  in FIG. 2 is much greater than that of resistor R s . If resistor R r  is replaced by a short circuit (i.e., if R r =0), the FIG. 2 converter will function essentially identically to the conventional FIG. 1 converter. 
     FIG. 4 is a schematic diagram of a variation on the FIG. 3 embodiment of the invention in which the ramp adjustment circuitry includes external capacitor C r  (rather than external resistor R r ) connected between the source of transistor N 1  and the drain of transistor N 2 , and voltage-to-current converter  11  (which produces a periodic ramped current i r ) is replaced by DC current source  111  (which produces a DC current i r ). Controller chip  102  of FIG. 4 is identical to chip  101  of FIG. 3, except in that voltage-to-current converter  11  of chip  101  is replaced by DC current source  111  of chip  102 . After latch  4  (within chip  102 ) has been set, the latch  4  resets (causing the driver  6  within chip  102  to assert a potential V DR  to the gate of transistor N 1  which turns off transistor N 1 ) when V s =V c −(V osc +V adj ), where V c  is the potential at the pin labeled “COMP” (as in FIG.  3 ), V s =I L R s , and V adj  is the voltage across capacitor C r  (which is a periodic ramped voltage). Thus, provision of the extra elements  111 , N 2 , and C r  in the FIG. 4 embodiment results in an effective ramp rate of d(V osc +V adj )/dt for the ramped voltage produced by the oscillator within chip  102  (the added ramp compensation is d(V adj )/dt=i r /C r ). 
     FIG. 5 is a schematic diagram of a variation on the FIG. 3 embodiment of the invention in which the ramp adjustment circuitry includes both an external capacitor C r  (connected between the source of transistor N 1  and the drain of transistor N 2 ) and a resistor R r2  (connected between a supply potential V r  and the drain of transistor N 2 ), and voltage-to-current converter  11  is omitted. Controller chip  103  of FIG. 5 is identical to chip  101  of FIG. 3, except in that voltage-to-current converter  11  of chip  101  is omitted in chip  103 . After latch  4  (within chip  103 ) has been set, the latch  4  resets (causing the driver  6  within chip  103  to assert a potential V DR  to the gate of transistor N 1  which turns off transistor N 1  ) when V s =V c −(V osc +V adj2 ), where V c  is the potential at the pin labeled “COMP” (as in FIG.  3 ), V s =I L R s , and V adj2  is the voltage across capacitor C r  (which is a periodic ramped voltage). Thus, provision of the extra elements N 2 , R r2 , and C r  in the FIG. 5 embodiment results in an effective ramp rate of d(V osc +V adj2 )/dt for the ramped voltage produced by the oscillator within chip  103 , so that the added ramp compensation is d(V adj2 )/dt=V r /R r2 C r . 
     FIG. 6 is a simplified schematic diagram of another preferred embodiment of the inventive DC-to-DC converter which includes a controller chip (integrated circuit  104 ), external buck controller circuitry, and ramp adjustment circuitry (comprising resistor R r  external to controller chip  104 , and NMOS transistor N 2  and current source  121  connected as shown within chip  104 ). The buck controller circuitry of FIG. 6 differs from the boost converter circuitry of FIGS. 1-5 in that the source of NMOS transistor N 1  is coupled through inductor L 1  to the output node (whereas in FIGS. 1-5, the drain of transistor N 1  is coupled through diode D to the output node, and inductor L is coupled between the input potential V in  and the source of N 1  ), Schottky diode D 1  is connected between ground and the source of N 1  (replacing diode D of FIGS.  1 - 5 ), sense resistor R s  is connected between the input potential V in  and the drain of N 1  (rather than between ground and the source of N 1  as in FIGS.  1 - 5 ), and boost capacitor C B  is coupled between chip  104  and the gate of transistor N 1  . The buck controller circuitry of FIG. 6 has conventional design, except in that it includes (in accordance with the present invention) resistor R r  which is connected between the drain of transistor N 1  and current source  121  of controller chip  104 . 
     Controller chip  104  includes elements  2 ,  4 ,  6 ,  8 ,  9 , and  10  of FIG. 2 (these elements are connected as shown in FIG. 2, but are not shown in FIG. 6 for simplicity). Chip  104  differs from chip  101  of FIG. 2 only in that it includes voltage-to-current converter  121  which sinks periodic ramped current i r  from resistor R r  (replacing converter  11  of FIG. 2 which sources ramped current i r  to resistor R r  of FIG.  2 ), in that it includes PMOS transistor P 1  (replacing transistor N 2  of FIG. 2) connected with its source coupled to input potential V in , its drain coupled to resistor R r , and its gate coupled to a level shifted inverted output of latch  4 , and in minor respects apparent to those of ordinary skill in the art (including in that it has a pin coupled to boost capacitor C B ). Typically, the resistance of resistor R r  in FIG. 6 is much greater than that of resistor R s . Transistor P 1  is provided to discharge, each time transistor N 1  is switched off, any stray capacitance C p  at the node connecting chip  104  with resistor R r . 
     Chip  104  of FIG. 6 functions in essentially the same manner as does chip  101  of FIG. 3, including in that it turns on transistor N 1  by setting latch  4  (in response to pulses from a clock pulse train produced by oscillator  2 ), and turns off transistor N 1  by resetting latch  4  in response to a comparison of V c −V osc  (where V osc  is a ramped voltage produced by oscillator  2  and V c  is the potential at the pin labeled “COMP”) with a feedback potential indicative of the potential at Node B (between resistor R s  and the drain of N 1 ) minus the voltage drop i r R r  across resistor R r . After latch  4  (within chip  104 ) has been set, the latch  4  resets (causing driver  6  within chip  104  to assert a potential V DR  to the gate of transistor N 1  which turns off transistor N 1 ) when V s =V c −(V osc +i r R r ), where V s  is the potential difference between V in  at the potential at Node B and i r R r  is the voltage drop across resistor R r  (which is a periodic ramped potential). Thus, provision of the elements  121 , P 1 , and R r  in the FIG. 6 embodiment results in an effective ramp rate of d(V osc +i r R r )/dt for the ramped voltage produced by the oscillator within chip  104 , so that the added ramp compensation is d(i r R r )/dt=[d(i r )/dt]R r . 
     FIG. 7 is a simplified schematic diagram of a variation on the FIG. 6 embodiment of the invention in which the ramp adjustment circuitry includes external capacitor C r  (rather than external resistor R r  ) connected between the drain of transistor N 1  and the drain of transistor P 1 , and voltage-to-current converter  121  (which produces a periodic ramped current i r ) is replaced by DC current source  131  (which produces a DC current i r ). Controller chip  105  of FIG. 7 is identical to chip  104  of FIG. 6, except in that voltage-to-current converter  121  of chip  104  is replaced by DC current source  131  of chip  105 . After latch  4  (within chip  105 ) has been set, the latch  4  resets (causing the driver  6  within chip  105  to assert a potential V DR  to the gate of transistor N 1  which turns off transistor N 1 ) when V s =V c −(V osc +V adj ), where V c  is the potential at the pin labeled “COMP” (as in FIG.  6 ), V s  is the potential at Node B, and V adj  is the voltage across capacitor C r  (which is a periodic ramped voltage). Thus, provision of the extra elements  131 , P 1 , and C r  in the FIG. 7 embodiment results in an effective ramp rate of d(V osc +V adj )/dt for the ramped voltage produced by the oscillator within chip  105 , so that the added ramp compensation is d(V adj )/dt=i r /C r . 
     FIG. 8 is a schematic diagram of a variation on the FIG. 6 embodiment of the invention in which the ramp adjustment circuitry includes both an external capacitor C r  (connected between the drain of transistor N 1  and the drain of transistor P 1 ) and a resistor R r2  (connected between ground and the drain of transistor P 1 ), and voltage-to-current converter  121  is omitted. Controller chip  106  of FIG. 8 is identical to chip  104  of FIG. 6, except in that voltage-to-current converter  121  of chip  104  is omitted in chip  106 . After latch  4  (within chip  106 ) has been set, the latch  4  resets (causing the driver  6  within chip  106  to assert a potential V DR  to the gate of transistor N 1  which turns off transistor N 1 ) when V s =V c −(V osc +V adj2 ), where V c  is the potential at the pin labeled “COMP”, V s  is the potential at Node B, and V adj2  is the voltage across capacitor C r , (which is a periodic ramped voltage). Thus, provision of the extra elements P 1 , R r2 , and C r  in the FIG. 8 embodiment results in an effective ramp rate of d(V osc +V adj2 )/dt for the ramped voltage produced by the oscillator within chip  106 , so that the added ramp compensation is d(V adj2 )/dt=V in /R r2 C r . 
     In other embodiments, the invention is a DC-to-DC converter which differs from the above-described embodiments only in that the current mode switching controller chip is replaced by a current mode switching regulator chip (with “current mode switching regulator” denoting a circuit which performs all functions of a “current mode switching controller” but which also includes an on-board power switch, in contrast with a “current mode switching controller” chip, which does not include an on-board power switch and must be used with an external power switch), and the external power switch is replaced by the power switch that is implemented on-board the regulator chip. For example, one such embodiment is that of FIG. 2A embodiment, which differs from the FIG. 2 embodiment in that current mode switching controller chip  101  (of FIG. 2) is replaced by current mode switching regulator chip  101 A which includes all elements of chip  101  and also an integrated circuit implementation of NMOS transistor N 1  (which functions as a power switch), and in which pad  12  of FIG. 2 is replaced by two pads of regulator chip  101 A that are coupled respectively to the source and drain of the integrated circuit implementation of NMOS transistor N 1 . 
     In a variation on each embodiment including transistor N 2  (which is a discharge switch), transistor N 2  is omitted, and in a variation on each embodiment including transistor P 1  (which is also a discharge switch), transistor P 1  is omitted. Such variations are useful where both the parasitic capacitance (C p ) and the resistance R r  are low enough so that the time constant R r C p  is sufficiently low that C p  can simply be discharged through resistors R r  and R s . 
     Although only a number of preferred embodiments have been described in detail herein, those having ordinary skill in the art will certainly understand that many modifications are possible without departing from the teachings hereof. All such modifications are intended to be encompassed within the following claims.