Abstract:
A neural network for an adaptive pattern recognition apparatus includes a plurality of comparators coupled to an input signal. Each comparators compares the input to a different offset voltage. The comparator output is fed to scaling multipliers and then summed to generate an output. The scaling multipliers receive weighing factors generated by using a specific equation selected to insure a fat-learning neural network.

Description:
BACKGROUND OF INVENTION 
     The present invention relates to a method and an apparatus for recognizing patterns. In particular, the present invention relates to a single input, single output network system capable of learning to respond to particular values of input. The present invention is a comparator. network. 
     To date, no one has been able to successfully build a computer system which can autonomously see, hear, feel, move avoiding collision, etc. 
     Much work has been done in the fields of image recognition, speech recognition, collision avoidance, etc., and, although much progress has been made in these fields, no system has been developed which can see, hear, or move with the diversity and grace of a human or of many other animals. It is becoming apparent therefore that computers just cannot perform certain tasks, or at the very least do not seem to be well suited for human-like performance in these areas. 
     SUMMARY OF THE INVENTION 
     Accordingly it is desirable to develop a new and improved method of processing which mimics the processing methods of the human brain. While neural network systems have been developed, none to date are capable of learning at a rapid speed. While the operation of the brain may not be fully understood, the architecture of the brain is so perfectly suited to performing these tasks, that systems should be designed to imitate this structure and match its capability. 
     In the crudest description, the brain is composed of somewhere in the order of a hundred billion neurons with many connected to thousands of its neighbors. There are somewhere around 10 14  connections in the human brain. A typical neuron has inputs from many other neurons, and a single output which is sent as input to many other neurons. Each neuron, in general, performs a fairly simple operation on its inputs, and although different neurons may perform different tasks, it is believed that the task of a particular neuron does not change with time. The connections between the neurons typically amplify or attenuate the signal received from one neuron before sending it to the next. It is the amount of amplification (or attenuation) in each connection, and the pattern of connectivity of the network of neurons that enables the brain to associate a particular set of stimuli with another or with a thought, action or concept. It is in these connections, then, where our knowledge and intelligence resides. The amplitude of each connection, called a connection weight, is variable. As the weights change, so does our knowledge and intelligence. We learn by changing connection weights, by continually updating a hundred trillion amplifier gains and constantly tweeking an incredibly complicated system until we know and understand everything we can. 
     Thus, it is a principal object of the present invention to develop a system in which the connection weights which enhance or amplify signals between neurons (comparators) and the output are rapidly varied in a circuit configuration in which the comparators are evenly distributed in a parallel configuration. This object is achieved by providing a network system, containing a level of comparators which are distributed about the space of the single input to the network. The comparators inform the network where the input is along the input space and all learning is performed by means of a feedback circuit. The feedback circuit is referred to as the update circuit and it detects and feeds any error in the output voltage through the circuitry to vary the connection weight or amplifier gain associated with each neuron or comparator. 
     It is a further object to provide a new and improved neural network using comparators in the circuitry shown in FIGS. 1 and 2 having ranges from -d to d, distribution of biases, V e , and an update function, F u . 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a fuller understanding of the nature and the object of the invention, reference should be had to the following detailed description, taken in connection with the accompanying drawings, in which: 
     FIG. 1 is the recall circuit of the present invention; 
     FIG. 2 is the update circuit of the present invention; 
     FIG. 3 is a graph of the function block F u  ; 
     FIG. 4A shows the distribution of thresholds in accordance with the teachings of the present invention; 
     FIG. 4B shows the threshold generation circuit; and 
     FIG. 5 is a block diagram of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring, now to the drawings, FIG. 1 discloses the recall circuit 1 portion of the present invention network. 
     The recall circuit 1 has an input i which is fed into a digital to analog converter 5 converting the input signal into an analog signal. 
     The recall circuit has n branches, one for each neuron. The neurons are represented by comparators formed as summers 3 and threshold circuits 4. The analog signal is fed to each of the n branches and into summer circuits 3 along with an offset voltage V.sub.θ associated with a particular comparator. V.sub.θ is a predetermined voltage value for each associated comparator and is taken from a voltage-divider, resistive circuit. Referring to FIGS. 4A and 4B, assume there is an input ranging from 0 to 7 where that input consists of integers only. The threshold would be set up as shown in FIG. 4A where the numbers in circles represent the biases (thresholds) of the neurons. Thus there are 16 neurons (comparators) with distance, d, equal to 0.5. These values are produced by the circuit of FIG. 4B. Thus V - , provides a reference bias voltage for the first comparator on branch line 9. 
     Threshold circuit 4 performs a linear threshold operation which can be realized with a simple op-amp circuit. If the input is greater than d, the output is d. If the input is less than -d, the output is -d. Otherwise, the output is the same as the input. 
     The threshold valves of +d and -d represent the distance between two adjacent comparator biases. V dl  through V dn  which are output from the summers 3 each represent the difference in voltage between the input level V in  and the bias value for the associated comparator. 
     The signal is then fed from the threshold circuit into a multiplier 6. A connection weight w associated with each comparator is also input into the corresponding branch and the product signal for each of the n branches are cumulatively summed in summer 7 and then fed to threshold circuit 8, which outputs V out . 
     FIG. 2 discloses the update circuit 10 which determines the value of the connection weights w. The update circuit 10 provides an error correction feedback signal to the recall circuit 1, rapidly varying the connection weight w based upon the voltage difference between V out  and the desired voltage, V desired  for a particular input signal. V desired is supplied from another source. FIG. 5 shows a block diagram of inputs and outputs to the present invention referred to as the Comparator Network or CompNet. 
     V learn is an enabling voltage and either enables or disables the update circuit depending upon whether or not the network is in a training mode. Thus if V-learn is 1 volt the circuit is in a training mode and learning, and V learn is 0 volts when it is not. Therefore when V-learn is 0 volts, the connection weights, w are not updated. 
     V error is the error voltage output from the summer 11 and represents the voltage difference between V out and V desired. Thus if V out=V desired, there is no error voltage, V error and no correction to the weights w. 
     V dl through V dn  are the output voltages of summers 3, representing the difference between the input voltage V in and the respective bias voltage V for each comparator. Each V d  is input into a corresponding function block 12, F u  which has the shape shown in FIG. 3. The F u  block transforms V d  in accordance with the equation: 
     
         F.sub.u (V.sub.dk)=ηSGN(V.sub.dk)e.sup.-P/dlVdkl 
    
     where 0 &lt;η≦1 is called the learning constant, SGN is the signum function and returns the sign of the argument, K ranges from 1 to n, and P is a shape constant which governs the shape of the response. P=0.63 works well. Further η can be used to slow learning. Typically, however η=1. 
     Thus, F u  plots each V d  on the weighted distribution curve of FIG. 3. 
     The function block 12 serves to evenly distribute the connection weights w l  through w n  along the curve shown on FIG.3. Thus, the product output from the function block 12 is multiplied with V error and V learn into multiplier 13, and then fed to summer 14. The previous connection weight is added to summer 14 and the corrected connection weight is then input to the recall circuit 1 as shown in FIG. 1 
     The invention thus provides a circuit for rapidly correcting the connection weights and permitting the recall circuit to be configured in parallel fashion so that there are n comparators arranged in parallel. 
     I do not limit myself to any particular details of construction set forth in this specification and illustrated in the accompanying drawings, as the same refers to and sets forth only certain embodiments of the invention, and it is observed that the same may be modified without departing from the spirit and scope of the invention.