Abstract:
A decoder for recovering data signals and clock signals from an encoded data stream includes: a delay circuit responsive to an encoded data stream for producing a delayed data stream, the delayed data stream being delayed a predetermined period of time from the encoded data stream; a D-type flip-flop responsive to the encoded data stream and to a clock signal for producing a data signal; and a phase comparator responsive to the delayed data stream and to the data signal for producing a clock signal.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a technique for recovering data and clock signals from an encoded serial data stream and more particularly relates to a decoder for decoding bi-phase and Manchester coding. 
     Bi-phase encoding of serial data for transmission over wire or fiber optic lines is commonly used because the code has a 50% duty cycle and is self-clocking. Bi-phase encoding is also known as Manchester, phase encoding, and frequency modulation. There are three versions of bi-phase encoding designated &#34;l&#34;, &#34;m&#34; and &#34;s&#34;. 
     The &#34;l&#34; or level version has transitions in the middle of the bit period and uses rising edges for a zero and falling edges for a one. The &#34;m&#34; or mark version has transitions at the beginning of every bit period and also has a transition at the middle of a one bit. The &#34;s&#34; or space version has transitions at the beginning of every bit period and also has a transition at the middle of a zero bit. The &#34;l&#34; version is usually called Manchester encoding. 
     The standard way of decoding bi-phase data is to use a Phase Locked Loop (PLL) to recover the clock and then to use the clock to recover the original NRZ (non return to zero) bit stream. Although the PLL is capable of operating at 100 megabits per second, the PLL must lock in phase with the clock signal derived from the demodulation, and there is a certain amount of settling time required for the PLL to lock in. Thus the demodulator clocked by a PLL would require a definite period of &#34;training&#34; or preamble during which the transmitted encoded signal contains only reference edges. For bi-phase this period would be a sequence of consecutive zeros to be encoded; for Manchester the sequence would be one, zero, one, zero, etc. In either case the encoded waveform for training is a series of alternately high and low levels with each having a full bit interval duration. For situations requiring transmission of bursty data at very high data rates, a preamble is required at the beginning of each burst and thus limits the data throughput. It is desirable to have a decoder that uses little or no preamble to increase data throughput. 
     A decoder that uses little or no preamble is described in Hewlett Packard&#39;s Opto-Electronics/Fiber Optics Applications Manual, Second Edition, at page 10.16. The Hewlett Packard demodulator does not require long training; it requires only one full bit interval with no edges followed by a reference edge (in bi-phase, a single encoded zero; in Manchester, a one, zero or zero, one). The reason for the rapid training is that a pair of monostable vibrators (one shots) are used. While this decoder requires little or no preamble, the problem with this encoder is that one shots are limited in speed of operation and thus the entire decoder is limited to about 10 to 20 megabits per second. 
     Therefore it is an object of the present invention to provide a bi-phase decoder that can decode bursty type data without lengthy preamble. 
     It is another object of the present invention to provide a bi-phase decoder which can decode data at the rate of 100 megabits per second or greater. 
     Additional objects, advantages and novel features of the invention will be set forth in part in the description which follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. 
     SUMMARY OF THE INVENTION 
     To achieve the foregoing and additional objects and in accordance with the purposes of the present invention, a decoder for recovering data signals and clock signals from an encoded data stream may comprise: a delay circuit responsive to an encoded data stream for producing a delayed data stream, and delayed data stream being delayed a predetermined period of time from the encoded data stream; a control means responsive to the encoded data stream and to a clock signal to provide a data signal; and a phase comparator responsive to the delayed data stream and to the data signal to provide a clock signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention is illustrated in the accompanying drawings wherein: 
     FIG. 1 is a schematic of a decoder according to the present invention; 
     FIG. 2 is a schematic of a decoder according to the present invention which decodes bi-phase and Manchester data; 
     FIGS. 3a-3h are timing charts for the signals indicated on FIG. 2; and 
     FIG. 4 is a schematic representation of an alternative decoder according to the present invention. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     Referring to FIG. 1, an encoded data stream 11 is applied simultaneously to the input of delay circuit 10 and one of the inputs of control circuit 13. Delay circuit 10 delays the encoded data stream by a predetermined amount and generates a delayed data stream which is applied to one input of phase comparator 20. Phase comparator 20 compares a data signal 16, which was generated by control circuit 13, with the delayed data stream and generates clock signal 19. Clock signal 19 is fed back into the control circuit and used to generate data signal 16. 
     Another embodiment of the present invention is shown in FIG. 2. In the embodiment of FIG. 2, D-type flip-flops and exclusive or gates are used. Referring to FIGS. 2 and 3, an encoded data stream represented by &#34;a&#34; is applied to delay line 110 which provides a delayed data stream &#34;b&#34;. In this embodiment delay line 110 delays signal &#34;a&#34; a fixed period of time &#34;t&#34; before applying it to exclusive or gate 112. The encoded data stream &#34;a&#34; is also applied to the &#34;D&#34; input or D-type flip-flop 116. Exclusive or gate 112 generates clock signal &#34;c&#34; which is applied to the clock input of D-type flip-flop 116. Output &#34;e&#34; of flip-flop 116 is applied to the other input of exclusive or gate 112. When signal &#34;e&#34; is low signal &#34;c&#34; is equal to signal &#34;b&#34;. When &#34;e&#34; is high &#34;c&#34; is equal to the complement of &#34;b&#34;. Signal &#34;e&#34; only changes on the rising edge of &#34;c&#34; and its value takes on the value of &#34;a&#34; at that instant. Signal &#34;e&#34; also represents the decoded Manchester data output. 
     In order to decode data that has been encoded in bi-phase mark or space, additional elements 114 and 118 are provided. Encoded data stream &#34;a&#34; is applied to exclusive or gate 114 which generates intermediate output &#34;d&#34;. The inverse output signal &#34;f&#34; from flip-flop 116 is also applied to exclusive or gate 114. When &#34;f&#34; is low, &#34;d&#34; is equal to &#34;a&#34;; when &#34;f&#34; is high, &#34;d&#34; is equal to the complement of &#34;a&#34;. D-type flip-flop 118 generates the bi-phase mark data output &#34;g&#34; when intermediate signal &#34;d&#34; is applied to the &#34;D&#34; input of D-type flip-flop 118 and clock signal &#34;c&#34; is applied to the clock input of D-type flip-flop 118. &#34;g&#34; only changes on the rising edge of &#34;c&#34; and takes on the value of &#34;d&#34; at that instant. Bi-phase space data can be recovered at output &#34;Q&#34; of D-type flip-flop 118. 
     Delay line 110 can be formed by using any suitable distributed or lumped delay element. For bi-phase encoded data, the ideal sample point is 3/4 of a bit period from the reference edge, so in this particular embodiment, the delay line has been preferably choosen to shift the input signal 3/4 of a bit period. Signal &#34;c&#34; therefore has a rising edge at the ideal sampling point. Data is recovered from the data stream by comparing the polarities of the signal at the reference edge and the sample point. For example, in the case of a zero encoded by bi-phase mark, the polarity of the data at the sample point is the same as at the beginning of the bit. In other words, the rising edge sampling a high or a falling edge sampling a low indicates a zero. A one has a transition in it so a rising edge sampling a low or a falling edge sampling a high indicates a one. The key is to keep track of the reference edge, which in the embodiment of FIG. 2 is accomplished by D-type flip-flop 116. 
     Short clock pulses are generated for half the data sequences where edges are added by flip-flop 116. In the case of bi-phase mark encoding, the clock out signal has short pulses wherever there is a zero. These can be fixed by adding an additional delay line in the signal line &#34;e&#34; from 116 to 112. The delay should be chosen to yield a 50% duty cycle on the clock signals. The speed of this circuit is only limited by the speed of the flip-flop and exclusive or gates and thus is usuable to gigahertz rates. 
     The decoding technique described here can be extended to any self-clocked encoding scheme which is defined as having at least one transition per bit period. Examples include Miller encoding, modified Miller encoding, and other pulse width modulation (PWM) or pulse code modulation (PCM) codes. 
     The circuit of FIG. 2 has been modified in FIG. 4 to accomplish these additional features. Like elements are shown with like numbers. Referring to FIG. 4, additional exclusive or gates 120, 122 and 124 have been provided for buffering purposes and have been arbitrarily choosen to be exclusive or gates but any other type gate for buffering purposes may be used. Exclusive or gate 126 has been added between the input signal to the &#34;D&#34; input of flip-flop 116 to match the delay of exclusive or gate 114. Preferably, 126 and 114 are identical exclusive or gates. Delay line 128 has been added between the &#34;Q&#34; output of flip-flop 116 and 112 to produce a 50% duty cycle clock. The circuit as shown in FIG. 4 has been built and operated to provide data throughput at the rate of 100 megabits per second. In this embodiment, exclusive or gates were chosen to be Motorola model MC10H107 and the D-type flip-flops were chosen to be Motorola model MC10H131. Delay line 110 was chosen to be a section of transmission line approximately 4 feet in length and delay line 128 was chosen to be a section of transmission line approximately 1 foot in length.