Abstract:
An apparatus for testing a semiconductor chip in which a built-in self test function is embedded, the apparatus including a plurality of error generators inserted between a plurality of function blocks performing a function of the semiconductor chip to input an error signal into the function blocks; and an external error controller for controlling the error generators through external input and output pins of the semiconductor chip and confirming the built-in self test function of the semiconductor chip by monitoring an output signal of the function blocks, and thus an error detection function embedded in the semiconductor chip can be correctly verified.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority to Korean Patent Application No. 10-2014-0192789, filed Dec. 30, 2014, the contents of such application being incorporated by reference herein. 
       FIELD OF THE INVENTION 
       [0002]    The present invention relates to an apparatus for testing a semiconductor chip (an apparatus for fault injection to a semiconductor chip), and more specifically, to an apparatus for testing a semiconductor chip, which can test a built-in self test function (diagnostic function) embedded in the semiconductor chip. 
       BACKGROUND OF THE RELATED ART 
       [0003]    As degrees of integration and complexity in a circuit such as a semiconductor chip abruptly increase, a method of testing or diagnosing a completed product also becomes more complex. Various testing methods for determining whether or not a produced product normally operates are provided, and a built-in self test (BIST) method including a test function inside thereof is also frequently used. 
         [0004]    Generally, testing a malfunction at an external pin of a semiconductor chip is performed by generating a direct connection error, and a CPU or memory is used to test operation of a fault detection function provided inside the chip. 
         [0005]    For example, a method of damaging a value in the memory or damaging a value of a CPU register (write an arbitrary value) using a CPU debugging function (JTAG: Joint Test Action Group) on the assumption that an operation error occurs inside the chip and confirming restoration of software or transition to a fault response mode is used. In addition, a method of creating a function for generating an error in each of major blocks, executing an error generation scenario at an arbitrary time by the CPU using a program, and confirming malfunctions and a prepared response action of the chip according thereto is used. 
         [0006]    Korean Patent Registration No. 10-0267096 proposes a method capable of scanning either a single scan chain or all parallel scan chains selected to be used in a JTAG environment for the purpose of debugging an integrated circuit chip. 
         [0007]    However, whether or not the built-in self test embedded in a semiconductor chip normally operates cannot be correctly confirmed only through a simulation using the CPU debugging function or the like as described above. That is, it is difficult to completely verify an error detection function of a semiconductor chip by an indirect test performed through a simulation as described above. 
         [0008]    It may be sufficient to use only a test method performed through a simulation as described above in the case of an apparatus or a system which is not related to safety. However, if a fault occurs in a semiconductor chip used in a vehicle, a train, an airplane or the like and an abnormal signal is output, it may cause irrevocable damage. 
         [0009]    Accordingly, development of a test apparatus which can test further securely whether or not a fault detection function embedded in a semiconductor chip normally operates is earnestly required. 
       SUMMARY OF THE INVENTION 
       [0010]    Accordingly, the present invention is made in view of the above-mentioned problems occurring in the prior art, and an aspect of the present invention aims to provide a test apparatus capable of correctly verifying an error detection function embedded in a semiconductor chip. 
         [0011]    To accomplish this, according to an aspect of the present invention, there is provided an apparatus for testing a semiconductor chip in which a built-in self test function is embedded, the apparatus including: a plurality of error generators inserted between a plurality of function blocks performing a function of the semiconductor chip to input an error signal into the function blocks; and an external error controller for controlling the error generators through external input and output pins of the semiconductor chip and confirming the built-in self test function of the semiconductor chip by monitoring output signals of the function blocks. 
         [0012]    The error generator includes: a control unit for receiving a first error control signal from the external error controller and determining whether or not to cause the error generator to be operated; an error code reception unit for receiving a second error control signal from the external error controller and transmitting, to the control unit, an error code signal, which is information relating to an error pattern to be generated by the error generator; an error pattern storage unit for storing a plurality error patterns, receiving the error code signal from the control unit and outputting an error pattern corresponding to an error code; and an output selection unit for outputting either a function signal from the function block or an error pattern signal from the error pattern storage unit according to a selection signal from the control unit. 
         [0013]    The second error control signal from the external error controller includes an error code signal, a clock signal and an effective signal, and the error code reception unit includes: a plurality of error code storage units for receiving and storing the error code signal in synchronization with the clock signal; and an effective signal determination unit for determining effectiveness of the error code signal and causing only effective error codes to be stored in the error code storage units. 
         [0014]    The error code storage units are preferably connected to each other in a series, and the error code signal is transferred in a manner of shifting, and the error code reception unit is connected to an error code reception unit of another error generator in a series, and the error code signal is transferred in the manner of the shifting. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  is a block diagram showing a connection structure between internal function blocks of a semiconductor chip. 
           [0016]      FIG. 2  is a block diagram showing the configuration of an apparatus for testing a semiconductor chip according to an embodiment of the present invention. 
           [0017]      FIG. 3  is a block diagram showing the function of an error generator according to an embodiment of the present invention. 
           [0018]      FIG. 4  is a block diagram showing the function of an error code reception unit according to an embodiment of the present invention. 
           [0019]      FIG. 5  is a waveform diagram showing timing of an input signal of an error code reception unit according to an embodiment of the present invention. 
       
    
    
     DESCRIPTION OF SYMBOLS 
       [0000]    
       
         
           
               100 : Semiconductor chip 
               200 : External error controller 
               300 : Error generator 
               310 : Control unit 
               320 : Error code reception unit 
               321 ,  322 ,  323 : Error code storage unit 
               324 : Effective signal determination unit 
               330 : Error pattern storage unit 
               340 : Output selection unit 
           
         
       
     
       DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0029]    Hereinafter, a preferred embodiment of the present invention will be described with reference to the attached drawings. 
         [0030]    Although a fault may be generated in a basic element (transistor/wire) of a semiconductor, generating a fault in each element and preparing a circuit for generating the fault in a semiconductor configured of some hundreds of thousands or millions of circuits is inefficient from the aspect of a limited size and commercialization. Accordingly, when a semiconductor is designed, it is designed to be divided into function blocks of an appropriate unit, and the blocks are connected using signal lines. An example of this is shown in  FIG. 1 . 
         [0031]    Although an error may occur at a certain part inside of each function block, the effect of generating the error influences output of each block, and the error is transferred to a final output of the semiconductor chip (a pin of the chip) and influences the outside (system). That is, since an error occurs inside a unit block and gives an effect between blocks or influences an external connection unit of the semiconductor chip, generating a fault and providing the fault to a connection signal between blocks to modify the signal can be an efficient error verification method. 
         [0032]    According to this point of view, in the present invention, an error generator is attached at the input and output terminals of each function to actively generate a fault (inject a fault) through the error generator so that a built-in self test function (diagnostic function) of a semiconductor can be completely verified. 
         [0033]      FIG. 2  is a block diagram showing the configuration of a semiconductor chip in which a test circuit of a built-in self test function is embedded according to an embodiment of the present invention. 
         [0034]    As shown in  FIG. 2 , a semiconductor chip  100  in which a test circuit of a built-in self test function of the present invention is embedded is configured such that an error generator  300  is inserted between function blocks. Each error generator  300  inputs a previously stored error signal into a function block, and an external error controller  200  receives an output signal of the function block and confirms whether or not the built-in self test function of semiconductor chip  100  normally operates. In  FIG. 2 , a first error control signal is a control signal for turning on/off each error generator, which is transmitted through an individual line connected to each error generator. Contrarily, a second error signal is a signal for transmitting an error code, which is input into each error generator by shifting. 
         [0035]    The external error controller  200  is configured to select an error pattern which the error generators input into a function block. Accordingly, a variety of predetermined error tests can be selectively performed outside the semiconductor chip  100 . 
         [0036]      FIG. 3  is a block diagram showing the configuration of an error generator. As shown in  FIG. 3 , the error generator  300  is configured to include a control unit  310 , an error code reception unit  320 , an error pattern storage unit  330  and an output selection unit  340 . 
         [0037]    First, the control unit  310  determines whether or not to operate the error generator  300  according to a first error control signal from the external error controller  200 . That is, as is understood from  FIG. 2 , the first error control signal is input into each error generator  300  through a separate signal line, and thus, the control unit  310  can control to determine whether or not to cause the error generator  300  to be operated so as to input an error signal into a function block. Like this, since activation or deactivation of the error generator  300  can be individually controlled from outside, a time point of testing the semiconductor chip  100  and a function block desired to be tested can be selectively determined. 
         [0038]    If the error generator  300  is activated by the control unit  310 , the error code reception unit  320  receives a second error control signal from the external error controller  200 . The second error control signal is configured of an error code signal, a clock signal and an effective signal as shown in  FIG. 4 , and the effective signal is a signal for verifying reception of the error code signal. 
         [0039]    As shown in  FIG. 4 , the error code reception unit  320  is configured of a plurality of error code storage units  321 ,  322  and  323  for receiving and storing an error code signal in synchronization with the clock signal and an effective signal determination unit  324  for determining effectiveness of the error code signal and storing only effective error code signals in the error code storage units. Although three error code storage units  321 ,  322  and  323  are exemplified in this embodiment, further more number of error code storage units may be installed as needed. 
         [0040]    The error code storage units  321 ,  322  and  323  are consecutively connected in series in order to input and output an error code signal in the manner of shifting. An output of the final error code storage unit  323  is input into the error code reception unit of a next error generator. That is, the error code reception units of all the error generators  300  embedded in the semiconductor chip  100  are connected to each other in series and transfer an error code signal input from the external error generator  200  by shifting the error code signal. 
         [0041]    The effective signal determination unit  324  determines whether or not the input error code signal is effective on the basis of the effective signal of the second error control signal and inputs only effective error codes into the error code storage units  321 ,  322  and  323 . That is, since the error code signal is input by shifting, the effective signal determination unit  324  performs a function of identifying the start and the end of the input error code signal using the effective signal. 
         [0042]    The error codes output from the error code storage units  321 ,  322  and  323  are input into the control unit  310 . The control unit  310  sends the error code to the error pattern storage unit  330 , and the error pattern storage unit  330  outputs an error pattern corresponding to the error code. The error pattern storage unit  330  stores a plurality of error patterns in advance and outputs a stored error pattern according to the error code input from the control unit so that the error pattern may be input into the output selection unit  340 . 
         [0043]    An error pattern stored in the error pattern storage unit  330  is stored in the manner of a scenario which is set in advance when the apparatus is designed. For example, in the case of a digital signal, since a normal signal has two types of values of High (1)/Low (0) and moves as a combination of these two signals, if 1 (fixed)/0 (fixed)/disconnection/soft error (instantaneous contamination of a signal (pulse form)) or the like is input as an error code, a predefined error pattern is output according thereto. 
         [0044]    The output selection unit  340  selects either a function signal (a normal operation signal) from function block  1  or an error pattern signal (an abnormal operation signal) from the error pattern storage unit  330  according to a selection signal received from the control unit  310  and outputs the selected signal to function block  3 . That is, a normal signal is output from the output selection unit  340  if the error generator  300  is in an inactive state, and a predetermined error signal is output if the error generator  300  is in an active state, so that an error may occur in a connection value between function blocks. 
         [0045]    According an embodiment of the present invention, since various error patterns can be selectively applied to a function block by inputting an error code from outside of a semiconductor chip  100 , a built-in self test function of the semiconductor chip can be tested while changing the error patterns. Accordingly, the semiconductor chip can be tested by applying a variety of test scenarios. 
         [0046]    The test apparatus of the present invention has following effects. 
         [0047]    First, an error detecting function in a semiconductor chip can be verified in detail. 
         [0048]    Second, since a scenario and a time point for detecting an error can be changed from outside of a semiconductor chip, verification can be performed more effectively and efficiently. 
         [0049]    Third, since an error data is transmitted to an error generator embedded in a semiconductor chip by shifting the error data in series, complexity can be minimized by simplifying the structure of a circuit for testing an error. 
         [0050]    Fourth, since a signal is input and output to and from an external error controller using a serial interface, the number of connection pins of a semiconductor chip can be minimized. 
         [0051]    While the present invention has been described with reference to the particular illustrative embodiments, it is not to be restricted by the embodiments but only by the appended claims. It is to be appreciated that those skilled in the art can change or modify the embodiments without departing from the scope and spirit of the present invention.