Abstract:
Interconnect structures having self-aligned dielectric caps are provided. At least one metallization level is formed on a substrate. A dielectric cap is selectively deposited on the metallization level.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates generally to the manufacture of interconnect structures, and more particularly to the formation of self-aligned dielectric caps on copper interconnects. 
     Dielectric caps are employed in copper interconnects to act as a copper diffusion barrier. Dielectric caps may also act as an oxygen diffusion barrier to prevent oxidation of copper. Dielectric caps ensure good electromigration performance; however, the dielectric constant of conventionally used dielectric caps such as silicon carbide (SiC) and silicon carbon nitride (SiCN) is high (e.g., 5-7). The dielectric cap substantially contributes to Resistive Capacitive (RC) delay. It is desired to have a self-aligned dielectric cap for capacitance reduction and performance improvement. 
     SUMMARY OF THE INVENTION 
     In a first aspect of the invention, a method of forming a device includes providing a substrate. The method further includes forming at least one metallization level on the substrate. The method also includes selectively depositing a dielectric cap on the metallization level. 
     In a second aspect of the invention, a method of forming a device includes providing a substrate. The method includes forming a first ILD layer above the substrate, wherein the first ILD layer has a top surface and a first opening. The method includes depositing a first metal liner in the first opening. The method includes forming a first metallization level in the first opening. The method includes forming a first cap layer on the top surface of the first ILD layer. The method includes forming a second ILD layer above the first cap layer, wherein the second ILD layer has a top surface and a second opening extending into the first metallization level. The method includes depositing a second metal liner on the top surface and in the second opening. The method includes forming a second metallization level in the second opening. The method includes performing a CMP of the second metallization level, wherein a top of the second metallization level is co-planar with a top of the second metal liner. The method further includes forming a second cap layer on the second metallization level. The method also includes removing the second metal liner from the top surface of the second ILD layer. 
     In a further aspect of the invention, a device includes a substrate. The device further includes at least one metallization level on the substrate. The device also includes a dielectric cap selectively deposited on the metallization level. 
     In a yet further aspect of the invention, a device includes a substrate. The device includes a first ILD layer formed above the substrate, wherein the first ILD layer has a top surface and a first opening. The device includes a first metal liner deposited in the first opening. The device includes a first metallization level formed in the first opening. The device includes a first cap layer formed on the top surface of the first ILD layer. The device includes a second ILD layer formed above the first cap layer, wherein the second ILD layer has a top surface and a second opening extending into the first metallization level. The device includes a second metal liner deposited in the second opening. The device further includes a second metallization level formed in the second opening, wherein the second metallization level is coplanar with the top surface of the second ILD layer. The device also includes a second cap layer formed on the second metallization level. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention is described in the detailed description below, in reference to the accompanying drawings that depict non-limiting examples of exemplary embodiments of the present invention. 
         FIG. 1  shows a starting interconnect structure in accordance with an embodiment of the invention; 
         FIG. 2  shows processing steps and an intermediate interconnect structure in accordance with an embodiment of the invention; 
         FIG. 3  shows processing steps and a final interconnect structure in accordance with an embodiment of the invention; 
         FIG. 4  shows a final interconnect structure in accordance with a second embodiment of the invention; 
         FIG. 5  shows a final interconnect structure in accordance with a third embodiment of the invention; and 
         FIG. 6  shows a final interconnect structure in accordance with a fourth embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 1  shows a starting interconnect structure  10  in accordance with an embodiment of the invention. Interconnect structure  10  may be formed on a substrate  15  using conventional processes. Interconnect structure  10  may include an underlying metallization or device level  20 , a cap layer  25 , an interlevel dielectric layer (ILD)  30 , a metal liner  31  and a copper metallization level  32 . Underlying metallization level  20  may include, but is not limited to copper (Cu), aluminum (Al), tungsten (W) and other low resistivity semiconductor compatible metals. Cap layer  25  may include, but is not limited to silicon carbon nitride (SiCN), silicon nitride (SiN) and silicon carbide (SiC). ILD  30  may include, but is not limited to: carbon doped silicon oxide (SiCOH), porous SiCOH and silicon oxide (SiO). Metal liner  31  may include, but is not limited to a stack of tantalum nitride (TaN) and tantalum (Ta). Chemical mechanical planarization (CMP) is performed to remove copper, stopping on field liner regions. Liner  31   a  is retained in the field regions. Liner  31   a  is not polished. CMP is stopped before the liner polish. 
     Referring to  FIG. 2 , dielectric cap  35  may be selectively deposited on copper metallization level  32 . It was discovered that plasma enhanced chemical vapor deposition (PECVD) silicon carbon nitride (SiCN), such as nBLoK has selective properties. It was observed that nBLoK does not deposit much on TaN and/or Ta. Due to the selective nature of the dielectric cap deposition, nBLoK deposits only on copper metallization level  32  and does not deposit on liner  31   a . Other dielectric cap materials such as SiN and SiC, deposited by PECVD, chemical vapor deposition (CVD) or atomic layer deposition (ALD) or any known or later developed processes may be tuned to have this selective deposition property. Dielectric cap  35  may be approximately 5 nm to 100 nm thick. 
     Referring to  FIG. 3 , liner  31   a  is etched back and removed in the field regions. Low bias fluorine containing plasmas or any known or later developed processes may be used. Liner  31   a  may be removed using a fluorine based chemistry, such as a carbon tetra fluoride (CF4) reactive ion etch (RIE). This chemistry may also remove some of dielectric cap  35 . This may be factored into the initial deposited thickness of dielectric cap  35 . Liner  31   a  may also be removed using a xenon fluoride (XeF) gas. XeF gas removes liner  31   a  selectively to dielectric cap  35 . The next level ILD may be subsequently deposited and the build continued using conventional processes. 
       FIG. 4  shows an interconnect structure  400  in accordance with a second embodiment of the invention. A selective etch of ILD  30  is performed on the structure shown in  FIG. 3 . This results in the formation of trenches  38  between sidewall liners  31  of copper metallization levels  32 . The trenches may have a depth in a range from about 50 nm to 500 nm. The trenches may have an aspect ratio (depth:width ratio) of about 2:1. Self-aligned dielectric cap  35  is used as an etch hard mask for the selective etch. ILD  30  may be carbon doped silicon oxide (SiCOH), porous SiCOH or silicon oxide (SiO). An ash etch may be performed for SiCOH. DHF may be performed for SiO. A non-conformal next level ILD deposition may be performed, resulting in air-gap shapes. Copper metallization level  32  is protected. The air-gap shapes may be formed using processes as described in commonly assigned U.S. Patent Publication No. US20090200636A1 entitled “Sub-lithographic Dimensioned Air Gap Formation and Related Structure” which is incorporated by reference herein in its entirety. 
       FIG. 5  shows an interconnect structure  500  in accordance with a third embodiment of the invention. A non-selective conformal dielectric material including, but not limited to silicon nitride (SiN) may be deposited and then subsequently etched back using conventional processes resulting in spacers  39 . The spacer thickness (as deposited) may be greater than or equal to the thickness of sidewall liner  31 . Spacers  39  provide protection for sidewall liner  31  during ILD etching. 
       FIG. 6  shows an interconnect structure  600  in accordance with a fourth embodiment of the invention. A recess  40  may be formed in copper metallization level  32  before deposition of selective dielectric cap  35 . Recess  40  may have a depth in a range from about 5 nm to 100 nm. Dielectric cap  35  may be approximately 5 nm to 100 nm thick. Recess  40  may be formed after the copper only CMP (as shown in  FIG. 1 ). This results in uniform dielectric cap thickness across different line widths and provides increased interconnect reliability. The selective deposition of dielectric cap  35  may be followed by liner etch back (as shown in  FIG. 3 ) using the same processes. The copper recess may be formed using processes as described in commonly assigned U.S. Pat. No. 6,975,032 entitled “Copper Recess Process with Application to Selective Capping and Electroless Plating” which is incorporated by reference herein in its entirety. 
     The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. 
     The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.