Abstract:
A semiconductor device includes a power gating circuit including a synchronous reset flip-flop, a retention circuit including a retention flip-flop, a clock management circuit configured to provide an operation clock to the power gating circuit and the retention circuit, and a power management circuit configured to transmit a power gating control signal to the power gating circuit, the retention circuit, and the clock management circuit. The power gating circuit is activated to signal entry to a power reduction mode. The retention circuit retains states of the semiconductor device. Upon exit from the power reduction mode, the power management circuit is configured to complete a reset operation of the power gating circuit before signaling the retention circuit to cancel a retention state and restore the states of the semiconductor device.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority under 35 U.S.C. §119 to U.S. Provisional Patent Application No. 62/286,900, filed on Jan. 25, 2016 in the United States Patent and Trademark Office, and Korean Patent Application No. 10-2017-0010427, filed on Jan. 23, 2017 in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entirety. 
     
    
     TECHNICAL FIELD 
       [0002]    Exemplary embodiments of the inventive concept relate to a semiconductor device and a method of operating the same. 
       DISCUSSION OF RELATED ART 
       [0003]    The degree of integration of semiconductor integrated circuits is gradually increasing while the size of semiconductor integrated circuits is decreasing. Generally, as the degree of integration of a semiconductor integrated circuit increases, the magnitude of a power supply voltage supplied to the semiconductor integrated circuit decreases. Accordingly, the semiconductor integrated circuit requires relatively low power to operate. However, the decreased magnitude of the power supply voltage reduces the operating speed of transistors in the semiconductor integrated circuit and thus limits the overall operation performance. 
         [0004]    Dynamic threshold voltage technology may be employed with a core circuit in a semiconductor integrated circuit having a complementary metal oxide semiconductor (CMOS) transistor with a low threshold voltage, and a switch circuit, e.g., a power gating circuit, located between the core circuit and a power supply voltage and/or between the core circuit and a ground voltage having a CMOS transistor with a high threshold voltage. Dynamic threshold voltage technology can increase the operating speed and reduce the leakage current of the semiconductor integrated circuit. In other words, in the power gating mode, the leakage current may be reduced by turning off the CMOS transistor of the power gating circuit having the high threshold voltage. In the active mode, high-speed operation of the semiconductor integrated circuit may be ensured by operating the semiconductor circuit to be dependent on the CMOS transistor of the core circuit having the low threshold voltage. 
       SUMMARY 
       [0005]    According to an exemplary embodiment of the inventive concept, a semiconductor device includes a power gating circuit including a synchronous reset flip-flop, a retention circuit including a retention flip-flop, a clock management circuit configured to provide an operation clock to the power gating circuit and the retention circuit, and a power management circuit configured to transmit a power gating control signal to the power gating circuit, the retention circuit, and the clock management circuit. The power gating circuit is activated to signal entry to a power reduction mode. The retention circuit retains states of the semiconductor device. Upon exit from the power reduction mode, the power management circuit is configured to complete a reset operation of the power gating circuit before signaling the retention circuit to cancel a retention state and restore the states of the semiconductor device. 
         [0006]    According to an exemplary embodiment of the inventive concept, a semiconductor device includes a first power control block including a first power gating circuit, a first retention circuit, and a first clock management circuit, a second power control block including a second power gating circuit, a second retention circuit, and a second clock management circuit, and a third power control block including a third clock management circuit. The first power control block and the second power control block are connected in parallel with each other at slave level. The third power control block is connected to the first and second power control blocks at a master level. After a power gating operation for the first power control block ends, a normal operation of the first clock management circuit is performed after a reset operation of the first power gating circuit. 
         [0007]    According to an exemplary embodiment of the inventive concept, a method of operating a semiconductor device includes resetting a power gating circuit after termination of a power gating operation, canceling a retention state of a retention circuit after resetting the power gating circuit, and maintaining a normal operation of a clock management circuit by canceling the protection of an input of the clock management circuit after the canceling of the retention state of the retention circuit. 
         [0008]    According to an exemplary embodiment of the inventive concept, in a method of operating a semiconductor device including a power control block including a clock management circuit, a power gating circuit, and a retention circuit, the method includes enabling an external shutoff signal to isolate the clock management circuit from an external input, enabling a shutoff signal to shut off output of the power control block after enabling the external shutoff signal, and enabling a first reset signal to initialize a state of the power gating circuit after enabling the shutoff signal. The method further includes, after enabling the first reset signal, entering a power reduction mode where a power gating operation and a retention operation are performed by the power gating circuit and the retention circuit, respectively, or entering an external power shutoff mode. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The above and other features of the inventive concept will become apparent and more readily appreciated by describing in detail exemplary embodiments thereof with reference to the accompanying drawings. 
           [0010]      FIG. 1  is a block diagram of a semiconductor device according to an exemplary embodiment of the inventive concept. 
           [0011]      FIGS. 2A and 2B  are a timing diagram and a flowchart, respectively, illustrating a retention operation of a retention unit of  FIG. 1  and a power gating operation of a power gating unit of  FIG. 1  in a power reduction mode according to an exemplary embodiment of the inventive concept. 
           [0012]      FIGS. 3A and 3B  are a timing diagram and a flowchart, respectively, illustrating the retention operation of the retention unit of  FIG. 1  and the power gating operation of the power gating unit of  FIG. 1  when external power is shut off according to an exemplary embodiment of the inventive concept. 
           [0013]      FIG. 4  is a block diagram of a semiconductor device according to an exemplary embodiment of the inventive concept. 
           [0014]      FIG. 5  is a block diagram of a system on chip (SoC) including a semiconductor device according to an exemplary embodiment of the inventive concept. 
           [0015]      FIG. 6  is a block diagram of a SoC including a semiconductor device according to an exemplary embodiment of the inventive concept. 
           [0016]      FIG. 7  is a block diagram of a semiconductor system including a SoC according to an exemplary embodiment of the inventive concept. 
           [0017]      FIG. 8  is a block diagram of a semiconductor system including a SoC according to an exemplary embodiment of the inventive concept. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0018]    Exemplary embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout this application. 
         [0019]    In a case where an exemplary embodiment of the inventive concept is otherwise feasible, functions or operations specified in a particular block may occur in a different order than the order described herein. For example, operations of two successive blocks may be performed substantially at the same time or may be performed in a reverse order depending on a related function or operation. 
         [0020]    Exemplary embodiments of the inventive concept provide a semiconductor device that can efficiently control a circuit having various power states using a power gating circuit and a retention circuit, and can prevent the circuit from malfunctioning when performing a normal operation after termination of a power gating operation. 
         [0021]    Exemplary embodiments of the inventive concept also provide a method of operating the above-described semiconductor device. 
         [0022]    According to an exemplary embodiment of the inventive concept, a power gating method or operation is provided for reducing standby power while a semiconductor device stops operating to reduce the power consumed by the semiconductor device, and a retention method or operation is provided for storing the state of the semiconductor device and restoring the state when the semiconductor device performs a normal operation after termination of a power gating operation. Furthermore, when the operation of the semiconductor device is stopped, the power supplied from an external power device is shut off to reduce standby power. 
         [0023]    In particular, according to exemplary embodiments of the inventive concept, a circuit having various power states can be implemented, and the area of the semiconductor device can be reduced by reducing the proportion of the size of a retention circuit to the size of a power gating circuit, where the retention circuit has a relatively larger area compared to the power gating circuit. 
         [0024]    In addition, when the circuit is returned to a normal operation mode after the power supplied from the external power device is shut off, the entire circuit may be initialized to ensure the normal operation of the circuit. 
         [0025]    Furthermore, a normal operation state of the circuit may be stored in the storage space of the retention circuit during the power gating operation. Then, when a retention signal is deactivated, the normal operation state of the circuit stored in the storage space of the retention circuit may be restored. This can ensure the normal operation of the circuit after the power gating operation. 
         [0026]    The internal state of the power gating circuit becomes an unknown state during the power gating operation. Therefore, an initialization operation is required when the power gating circuit returns to the normal operation mode. However, a clock management unit, which provides an operation clock, cannot generate the operation clock during the retention operation. In other words, the clock management unit can generate and supply the operation clock to the power gating circuit only after the retention operation is canceled. In addition, internal circuits of the power gating circuit can operate only after receiving the operation clock from the clock management unit. 
         [0027]    An output of a synchronous reset flip-flop of the power gating circuit is in an unknown state before the operation clock is provided to the power gating circuit. If this output is input to the retention circuit, the retention circuit may malfunction. To prevent this, all circuits may be implemented as retention circuits, or the power gating circuit may be composed only of asynchronous reset flip-flops. However, this can increase the area of the semiconductor device. 
         [0028]    According to exemplary embodiments of the inventive concept, the clock management unit is isolated from the retention circuit and controlled accordingly. In addition, the clock management unit performs a normal operation before the retention circuit or the power gating circuit. While the clock management unit is performing the normal operation, the retention circuit has not yet returned to the normal operation mode, and thus, an abnormal input may be provided to the clock management unit. Therefore, an input of the clock management unit may be isolated or protected until the output of the synchronous reset flip-flop of the power gating circuit is initialized to the normal operation mode. Accordingly, normal operation of the clock management unit may be ensured. 
         [0029]      FIG. 1  is a block diagram of a semiconductor device according to an exemplary embodiment of the inventive concept. 
         [0030]    Referring to  FIG. 1 , the semiconductor device according to an exemplary embodiment of the inventive concept includes a power control block  100  and a power management unit  200 . 
         [0031]    The power control block  100  may include a clock management unit  110 , a retention unit  120 , and a power gating unit  130 . 
         [0032]    The clock management unit  110  may perform a retention operation. The clock management unit  110  may receive a retention control signal CMU_RETENTION from the power management unit  200 . However, the inventive concept is not limited thereto, and the clock management unit  110  can also be implemented as a clock management unit without a retention function. 
         [0033]    To perform a power gating operation, the clock management unit  110  may receive a power gating control signal PG from the power management unit  200 . 
         [0034]    The clock management unit  110  may receive a reset signal CMU_RESET from the power management unit  200  to initialize its internal state after the power from an external power device is shut off or after the power gating operation. 
         [0035]    To prevent the clock management unit  110  from malfunctioning due to an abnormal input from an external source clock, the clock management unit  110  may receive an external shutoff signal SEPARATE_SMU from the power management unit  200 . 
         [0036]    The clock management unit  110  may include a clock multiplexer (mux) unit  111 , a clock dividing unit  112 , a dividing circuit state machine  113 , a clock stop state machine  114 , a clock gating unit  115 , and a clock gating state machine  116 . 
         [0037]    The clock mux unit  111  may include a control circuit and a clock mux circuit. The control circuit of the clock mux unit  111  may operate with a sequential behavior. The control circuit of the clock mux unit  111  may turn on/off a clock and may generate a first clock request signal to change the selection of the clock mux unit ( 111 ) when the clock is off. Additionally, the control circuit of the clock mux unit  111  may transmit the first clock request signal to a clock component being used by the clock mux circuit. 
         [0038]    The clock dividing unit  112  may include a control circuit and a clock dividing circuit. The control circuit of the clock dividing unit  112  may operate with a sequential behavior. The control circuit of the clock dividing unit  112  may turn on/off a clock and may generate a second clock request signal to change the clock dividing ratio of the clock dividing circuit when the clock is off. 
         [0039]    The dividing circuit state machine  113  may control the state of the clock dividing unit  112 . 
         [0040]    The clock stop state machine  114  may control a clock stop state and may operate by receiving a clock stop control signal CLKSTOP from the power management unit  200 . 
         [0041]    The clock gating unit  115  may provide an operation clock to the retention unit  120  and the power gating unit  130 , and may perform a clock gating operation. The clock gating operation divides a computer system into small function blocks and prevents dynamic current consumption of unused parts. When a computer is used, not all parts of the computer system are always operated. Therefore, through the clock gating operation, blocks in unused parts of the computer system may be stopped to lower power consumption and reduce the heat generated by these blocks. 
         [0042]    The clock gating state machine  116  may control a clock gating state and control the clock gating unit  115  to generate the operation clock or perform the clock gating operation according to the clock gating state. 
         [0043]    The retention unit  120  may include a retention flip-flop  121 . 
         [0044]    The retention unit  120  may perform the retention operation. The retention unit  120  may receive a retention control signal LOGIC_RETENTION from the power management unit  200 . 
         [0045]    The retention unit  120  may receive the power gating control signal PG from the power management unit  200  to perform the power gating operation when a retention state is maintained. 
         [0046]    The retention unit  120  may receive a reset signal SLEEP_RESET from the power management unit  200  to initialize its internal state after the power from the external power device is shut off. 
         [0047]    The retention unit  120  may receive the operation clock from the clock management unit  110 . 
         [0048]    The power gating unit  130  may include flip-flops  131  and  132 . For example, the power gating unit unit  130  may be implemented with a synchronous reset flip-flop. 
         [0049]    The power gating unit  130  may receive the power gating control signal PG from the power management unit  200  to perform the power gating operation. 
         [0050]    The power gating unit  130  may receive a reset signal LOGIC_RESET from the power management unit  200  to initialize 
         [0051]    its internal state after the power from the external power device is shut off or after the power gating operation. 
         [0052]    The power gating unit  130  may receive the operation clock from the clock management unit  110 . 
         [0053]    In addition, an output of the power gating unit  130  may be provided as an input to the retention unit  120  or the clock management unit  110 . 
         [0054]    Likewise, an output of the retention unit  120  may be provided as an input to the power gating unit  130  or the clock management unit  110 . 
         [0055]    The specific operations of the clock management unit  110 , the retention unit  120 , and the power gating unit  130  will be described below with reference to  FIGS. 2A, 2B, 3A , and  3 B. 
         [0056]      FIGS. 2A and 2B  are a timing diagram and a flowchart, respectively, illustrating a retention operation of a retention unit of  FIG. 1  and a power gating operation of a power gating unit of  FIG. 1  in a power reduction mode according to an exemplary embodiment of the inventive concept. 
         [0057]    Referring to  FIGS. 2A and 2B , a period e is a period during which the power gating operation is performed or executed (operation S 227 ). During the power gating operation execution period (the period e), the clock management unit  110  is in the retention state. In the power gating operation execution period, the retention control signal CMU_RETENTION for the clock management unit  110  is in a low state. In this example, external power is not shut off, and a disable operation for external power shutoff is skipped (operation S 229 ). After the power gating operation ends (operation S 231 ), the retention control signal CMU_RETENTION transitions to a high state. Accordingly, the retention state of the clock management unit  110  is canceled (operation S 235 ). In this example, a disable operation for the reset signal CMU_RESET is skipped (operation S 233 ). 
         [0058]    A shutoff signal CMU_ISO for the clock management unit  110  is disabled (operation S 239 ). 
         [0059]    An oscillator clock OSCCLK is provided to the clock management unit  110 , and the clock stop control signal CLKSTOP is disabled to resume the operation clock (e.g., functional CLK of CMU), which had been stopped. Accordingly, the clock management unit  110  provides the operation clock to the retention unit  120  and the power gating unit  130 . At this time, flip-flops of the power gating unit  130  are initialized. 
         [0060]    The operation clock is stopped to disable a shutoff signal LOGIC_ISO for the power control block  100  (operation S 241 ). The clock stop control signal CLKSTOP transitions back to a high state. 
         [0061]    After the shutoff signal LOGIC_ISO is disabled, the operation clock is started again. At this time, the initialization operation of the power gating unit  130  is completed, and the reset signal LOGIC_RESET for the power gating unit  130  is disabled (operation S 237 ). The reset signal LOGIC_RESET may be disabled at an earlier time, e.g., before operation S 239 . 
         [0062]    The operation clock is stopped again to cancel the retention operation of the retention unit  120 , and the retention control signal LOGIC_RETENTION for the retention unit  120  is disabled (operation S 243 ). Then, the clock stop control signal CLKSTOP is disabled (operation S 245 ) so that the operation clock is started again. 
         [0063]    A PLL disable signal DISABLE_PLL is disabled (operation S 247 ) so that a phase locked loop (PLL) is operated again (e.g., as illustrated by PLL FOUT), the external shutoff signal SEPARATE_CMU provided to protect the clock management unit  110  is disabled (operation S 249 ), and a clock gating signal FORCE_AUTOCLKGATE is disabled (operation S 251 ) to perform a normal operation (operation S 201 ). 
         [0064]    Referring to  FIGS. 2A and 2B , when the power gating operation is initiated, the clock gating signal FORCE_AUTOCLKGATE is enabled (operation S 203 ), the external shutoff signal SEPARATE_CMU provided to protect the clock management unit  110  is enabled (operation S 205 ), and the PLL disable signal DISABLE_PLL is enabled to stop the operation of the PLL (operation S 207 ). 
         [0065]    The clock stop control signal CLKSTOP is enabled to stop the output of the clock management unit  110  (operation S 209 ), and the retention control signal LOGIC_RETENTION is enabled to change the state of the retention unit  120  to retention state (operation S 211 ). 
         [0066]    The shutoff signal LOGIC_ISO for the power control block  100  is enabled to shut off the output of the power control block  100  (operation S 213 ). 
         [0067]    The shutoff signal CMU_ISO for the clock management unit  110  is enabled to shut off the output of the clock management unit  110  (operation S 215 ). 
         [0068]    The reset signal LOGIC_RESET for the power gating unit  130  is enabled to initialize the internal state of the power gating unit  130  (operation S 217 ). 
         [0069]    The retention control signal CMU_RETENTION for the clock management unit  110  is enabled so that the clock management unit  110  can perform the retention operation (operation S 219 ). An enable operation of the reset signal CMU_RESET is skipped (operation S 221 ). The power gating operation is enabled (operation S 223 ). In this example, external power is on, and thus, an enable operation for external power shutoff is skipped (operation S 225 ). Thus, the power gating operation is performed (operation S 227 ). 
         [0070]      FIGS. 3A and 3B  are a timing diagram and a flowchart, respectively, illustrating the retention operation of the retention unit of  FIG. 1  and the power gating operation of the power gating unit of  FIG. 1  when external power is shut off according to an exemplary embodiment of the inventive concept. 
         [0071]    Referring to  FIGS. 3A and 3B , the period e is a period during which the external power is shut off (operation S 327 ) (e.g., as illustrated by a power supply voltage VDD). When the external power shutoff is disabled (operation S 329 ), the reset signal CMU_RESET for the clock management unit  110  is disabled (operation S 333 ). 
         [0072]    In this example, a disable operation for the power gating operation is skipped (operation S 331 ). 
         [0073]    Additionally, a disable operation for the retention control signal CMU_RETENTION is skipped (operation S 335 ). 
         [0074]    The shutoff signal CMU_ISO for the clock management unit  110  is disabled (operation S 339 ). 
         [0075]    The oscillator clock OSCCLK is provided to the clock management unit  110 , and the clock stop control signal CLKSTOP is disabled to resume the operation clock, which had been stopped. Accordingly, the clock management unit  110  provides the operation clock to the retention unit  120  and the power gating unit  130 . At this time, the flip-flops of the retention unit  120  and the power gating unit  130  are initialized. The flip-flops of the retention unit  120  have unknown values due to the external power shutoff. However, the unknown values of the flip-flops may be initialized by the reset signal SLEEP_RESET. The clock stop control signal CLKSTOP transitions back to a high state so that the operation clock is stopped to disable the shutoff signal LOGIC_ISO (operation S 341 ) for the power control block  100 . 
         [0076]    After the shutoff signal LOGIC_ISO for the power control block  100  is disabled, the operation clock is started again. At this time, the initialization operation of the power gating unit  130  is completed, and the reset signal LOGIC_RESET for the power gating unit  130  is disabled (operation S 337 ). The reset signal LOGIC_RESET may be disabled at an earlier time, e.g., before operation S 339 . 
         [0077]    A disable operation for the retention control signal LOGIC_RETENTION is skipped (operation S 343 ). 
         [0078]    The operation clock is stopped again, and in this example, the retention control signal LOGIC_RETENTION for the retention unit  120  is maintained in a high state. Then, the clock stop control signal CLKSTOP is disabled so that the operation clock is started again (operation S 345 ). 
         [0079]    The PLL disable signal DISABLE_PLL is disabled so that the PLL is operated again (operation S 347 ), the external shutoff signal SEPARATE_CMU provided to protect the clock management unit  110  is disabled (operation S 349 ), and the clock gating signal FORCE_AUTOCLKGATE is disabled (operation S 351 ) to perform a normal operation (operation S 301 ). 
         [0080]    Referring to  FIGS. 3A and 3B , when the external power shutoff mode is entered, the clock gating signal FORCE_AUTOCLKGATE is enabled (operation S 303 ), the external shutoff signal SEPARATE_CMU provided to protect the clock management unit  110  is enabled (operation S 305 ), and the PLL disable signal DISABLE_PLL is enabled to stop the operation of the PLL (operation S 307 ). 
         [0081]    The clock stop control signal CLKSTOP is enabled to stop the output of the clock management unit  110  (operation S 309 ). 
         [0082]    An enable operation for the retention control signal LOGIC_RETENTION is skipped (operation S 311 ). 
         [0083]    The shutoff signal LOGIC_ISO for the power control block  100  is enabled to shut off the output of the power control block  100  (operation S 313 ). 
         [0084]    The shutoff signal CMU_ISO for the clock management unit  110  is enabled to shut off the output of the clock management unit  110  (operation S 315 ). 
         [0085]    The reset signal LOGIC_RESET for the power gating unit  130  is enabled to initialize the internal state of the power gating unit  130  (operation S 317 ). 
         [0086]    An enable operation for the retention control signal CMU_RETENTION is skipped (operation S 319 ). 
         [0087]    The reset signal CMU_RESET for the clock management unit  110  is enabled so that the clock management unit  110  can perform an initialization operation (operation S 321 ). 
         [0088]    An enable operation to initiate the power gating operation is skipped (operation S 323 ). 
         [0089]    External power shutoff is enabled (operation S 325 ) so that the external power is shut off (operation S 327 ). 
         [0090]    According to an exemplary embodiment of the inventive concept, when the power gating operation is canceled, it is possible to prevent the retention unit  120  from receiving an input of an unknown state due to an uninitialized output of the synchronous reset flip-flop  131  of the power gating unit  130 . For example, before the retention control signal LOGIC_RETENTION for the retention unit  120  is disabled, the reset signal LOGIC_RESET for the power gating unit  130  is enabled (low state), and, at substantially the same time, the operation clock is received from the clock management unit  110 . 
         [0091]    If the output of the power gating unit  130  that has not been initialized or the output of the retention unit  120  that has not been restored to a normal operating state is provided as an input to the clock management unit  110 , the clock management unit  110  may malfunction. To prevent this, according to an exemplary embodiment of the inventive concept, the initialization operation of the power gating unit  130  or the restoration operation of the retention unit  120  from the retention state to the normal operating state is performed before the external shutoff signal SEPARATE_CMU, for protecting the clock management unit  110  from an external input, is disabled. This can ensure the stable operation of the clock management unit  110 . 
         [0092]      FIG. 4  is a block diagram of a semiconductor device according to an exemplary embodiment of the inventive concept. 
         [0093]    Referring to  FIG. 4 , the semiconductor device according to an exemplary embodiment of the inventive concept includes a main block  40 , a plurality of power control blocks  100   a  through  100   c , and a power management unit  200 . 
         [0094]    Each of the power control blocks  100   a  through  100   c  may have substantially the same configuration as the power control block  100  described above with reference to  FIG. 1 . 
         [0095]    The power control blocks  100   a  through  100   c  may include clock management units  110   a  through  110   c , retention units  120   a  through  120   c , and power gating units  130   a  through  130   c , respectively. 
         [0096]    The main block  40  may provide the operation clock to each of the power control blocks  100   a  through  100   c . The main block  40  includes a clock management unit  110   d  but does not include a retention unit or a power gating unit. 
         [0097]    The main block  40  may operate to generate the operation clock, and the shutoff signal CMU_ISO for the main block  40  may be disabled before the shutoff signal LOGIC_ISO for the power control blocks  100   a  through  100   c . In addition, the operation of the main block  40  may continue after the operation of the power control blocks  100   a  through  100   c.    
         [0098]      FIG. 5  is a block diagram of a system on chip (SoC) including a semiconductor device according to an exemplary embodiment of the inventive concept. 
         [0099]    Referring to  FIG. 5 , a SoC  700  may include a central processing unit (CPU)  710 , a clock generator  720 , a clock management unit  730 , a random access memory (RAM)  740 , a read only memory (ROM)  750 , and a memory control module  760 , which may be connected to one another via a system bus. The clock management unit  730  may correspond to the clock management unit  110  of  FIG. 1 . The SoC  700  may further include a power management unit  731 , which corresponds to the power management unit  200  of  FIG. 1 . An oscillator OSC may be disposed outside the SoC  700  and provide an oscillation signal to the SoC  700 . However, this is merely an example, and the SoC  700  may include other various function blocks and/or the oscillator OSC may be provided within the SoC  700 . The SoC  700  of  FIG. 5  may be provided in a semiconductor system as an application processor. 
         [0100]    The clock generator  720  generates a reference clock signal CLK_IN having a reference frequency using the oscillation signal from the oscillator OSC. The clock management unit  730  may receive the reference clock signal CLK_IN, generate an operation clock signal CLK_OUT having a predetermined frequency, and provide the operation clock signal CLK_OUT to each function block. The clock management unit  730  may include one or more clock controllers, such as master clock controllers and slave clock controllers. Each of the clock controllers may generate the operation clock signal CLK_OUT using the reference clock signal CLK_IN. 
         [0101]    In addition, the clock controllers in the clock management unit  730  may be connected through a channel to manage clock signals through hardware. The clock controllers in the clock management unit  730  may also be connected to the function blocks through a channel to perform a clock request and a request response through hardware. 
         [0102]    The CPU  710  may process or execute codes and/or data stored in the RAM  740 . For example, the CPU  710  may process or execute the codes and/or the data in response to the operation clock output from the clock management unit  730 . The CPU  710  may be implemented as a multi-core processor. The multi-core processor is a computing component having two or more independent processors, each capable of reading and executing program instructions. The multi-core processor can simultaneously drive a plurality of accelerators. Therefore, a data processing system including the multi-core processor can perform multi-acceleration. 
         [0103]    The RAM  740  may temporarily store program codes, data, or instructions. For example, program codes and/or data stored in an internal or external memory may be temporarily stored in the RAM  740  according to the control of the CPU  710  or booting code stored in the ROM  750 . The memory control module  760  is a block for interfacing with the internal or external memory. The memory control module  760  controls overall operation of the internal or external memory and also controls all data exchanges between a host and the internal or external memory. 
         [0104]      FIG. 6  is a block diagram of a SoC including a semiconductor device according to an exemplary embodiment of the inventive concept. 
         [0105]    Referring to  FIG. 6 , a SoC  800  includes a power management unit  810  which manages power supply to function blocks. The power management unit  810  may be designed to manage the power used within the SoC  800 . 
         [0106]    The SoC  800  further includes a plurality of function blocks  821  and  822 . The function blocks  821  and  822  may be classified as a master function block  821  and slave function blocks  822 . For the master function block  821  to operate, power should be supplied to the master function block  821  and also to one or more slave function blocks  822  related to the operation of the master function block  821 . 
         [0107]    Within the power management unit  810 , a master power controller  811  may communicate with each of slave power controllers  812  and  813  through a channel. The power management unit  810  may receive input power Power_in and generate output power Power_out by adjusting and converting the input power Power_in to suit each function block. In addition, the power management unit  810  may provide power or block the supply of power to the master function block  821  and the slave function blocks  822  according to a power request Req. Each of the master power controller  811  and the slave power controllers  812  and  813  may provide the power gating control signal PG to the master function block  821  and the slave function blocks  822 . 
         [0108]    The master power controller  811  may receive the power request Req through software based on the code processing of a central processing unit, or receive the power request Req from the master function block  821  through hardware. The master function block  821  may provide a power on/off command Pwr On/Off to the slave power controllers  812  and  813 , and receive a power response Ack On/Off from the slave power controllers  812  and  813 , via the master power controller  811 . 
         [0109]      FIG. 7  is a block diagram of a semiconductor system including a SoC according to an exemplary embodiment of the inventive concept. 
         [0110]    Referring to  FIG. 7 , a semiconductor system  900  may include a SoC  901  according to the above-described exemplary embodiments, an antenna  910 , a wireless transceiver  920 , an input device  930 , and a display  940 . The wireless transceiver  920  may transmit or receive a radio signal via the antenna  910 . For example, the wireless transceiver  920  may change a radio signal received via the antenna  910  to a signal that can be processed by the SoC  901 . 
         [0111]    Thus, the SoC  901  may process the signal output from the wireless transceiver  920  and transmit the processed signal to the display  940 . In addition, the wireless transceiver  920  may convert a signal output from the SoC  901  into a radio signal and output the radio signal to an external device via the antenna  910 . The input device  930  is a device used to input a control signal for controlling the operation of the SoC  901  or data to be processed by the SoC  901 . The input device  930  may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, a keyboard, etc. 
         [0112]      FIG. 8  is a block diagram of a semiconductor system including a SoC according to an exemplary embodiment of the inventive concept. 
         [0113]    Referring to  FIG. 8 , a semiconductor system may include a memory system  1000 , and the memory system  1000  may be implemented as a data processing device such as a solid state drive (SSD). The memory system  1000  may include a plurality of memory devices  1500 , a memory controller  1200  which can control the data processing operation of each of the plurality of memory devices  1500 , a volatile memory device  1300  such as a dynamic random access memory (DRAM), and a SoC  1100  which controls data exchanged between the memory controller  1200  and a host  1400  and stored in the volatile memory device  1300 . The SoC  1100  may be implemented according to the above-described exemplary embodiments. 
         [0114]    While the inventive concept has been illustrated and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made thereto without departing from the spirit and scope of the inventive concept as defined by the following claims.