Abstract:
A level shift circuit. A level shift circuit may include a first voltage supply control unit connected to a first voltage terminal to control a supply of a first voltage via a first and/or second path according to statuses of first and/or second input signals inputted differentially, a second voltage supply control unit connected to a second voltage terminal to control a supply of a second voltage via a first and/or second path, a switching unit controlling a connection between first and second voltage supply control units on a first and/or second path, and/or a buffer unit outputting an output signal corresponding to a first voltage and/or a second voltage in response to a first potential outputted between a first voltage supply control unit and a switching unit and/or a second potential output between a second voltage supply control unit and a switching unit.

Description:
[0001]    The present application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2008-0137771 (filed on Dec. 31, 2008) which is hereby incorporated by reference in its entirety. 
       BACKGROUND 
       [0002]    Embodiments relate to electrical circuits and methods thereof. Some embodiments relate to a level shift circuit and methods thereof. 
         [0003]    A level shifter may be used to convert an input signal having a prescribed voltage level to a signal having another voltage level. A level shifter may convert an input signal of a relatively low voltage to an output signal of a relatively high voltage, and/or supply an output signal. A level shifter may convert an input signal of a relatively high voltage to an output signal of a relatively low voltage, and/or supply an output signal. Referring to example  FIG. 1 , a diagram of a level shift circuit is illustrated. 
         [0004]    Referring to  FIG. 1 , a level shift circuit may include level shift unit  10  and/or buffer unit  12 . Shift level shift unit  10  may include a plurality of PMOS transistors P 1  to P 4  and/or a plurality of NMOS transistors N 1  to N 4 . A shift signal SH may be output which may correspond to power source voltage VDD according to level statuses of input signal IN, inverse input signal INB and/or ground voltage VSS. Input signal IN of a logic high level may be inputted to a gate of NMOS transistor N 1  and/or an inverse input signal of a logic low level may be inputted to NMOS transistor N 4 , such that a PMOS transistor may be turned on and/or a potential corresponding to power source voltage VDD may be applied to a gate of NMOS transistor N 2 . NMOS transistor N 2  may be turned on such that a potential corresponding to ground voltage VSS may be applied to a gate of PMOS transistor P 4 . PMOS transistor P 4  may be turned on, such that shift signal SH having a potential corresponding to power source voltage VDD may be output. Inverse input signal INB of a logic low level may be input to NMOS transistor N 4 , such that PMOS transistors P and P 3 , and/or NMOS transistor N 3 , may remain turned off. 
         [0005]    Buffer unit  12  may include PMOS transistor P 5  which may receive shift signal SH in common and/or connected in series between a terminal of power voltage VDD and/or a terminal of ground voltage VSS. Buffer unit  12  may buffer shift signal SH, and/or output an output signal, such as output signal OUT. Shift signal SH of a logic high level may be output, such that output signal OUT having a potential corresponding to a level of ground voltage VSS may be output. Shift signal SH of logic low level may be output, such that output signal OUT having a potential corresponding to a level of power source voltage VDD may be output. 
         [0006]    However, since shift signal SH may be applied to gates of PMOS and NMOS transistors P 5  and N 5  in buffer unit  12 , a short-circuit current may be generated from a terminal of power source voltage VDD to a terminal of ground voltage VSS by PMOS and/or NMOS transistors P 5  and/or N 5  according to a level of shift signal SH. Therefore, electromagnetic interference (EMI) and the like may cause problems, for example a malfunction may be generated by ground bouncing attributed to a peak current. 
         [0007]    Accordingly, there is a need of a level shift circuit and methods thereof which may minimize a peak value of a sort-circuit current, for example generated from buffering a level shifted voltage. 
       SUMMARY 
       [0008]    Embodiments relate to a level shift circuit and methods thereof. According to embodiments, a level shift circuit may minimize a peak value of a sort-circuit current, for example generated from buffering a level shifted voltage. 
         [0009]    According to embodiments, a level shift circuit may include a first voltage supply control unit connected to a first voltage terminal, which may control a supply of a first voltage through a first and/or second path according to statuses of first and/or second input signals input differentially. In embodiments, a level shift circuit may include a second voltage supply control unit connected to a second voltage terminal, which may to control a supply of a second voltage through a first and/or second path. In embodiments, a level shift circuit may include a switching unit which may control a connection between first and second voltage supply control units on a first and/or second path. In embodiments, a level shift circuit may include a buffer unit which may output an output signal corresponding to a first voltage and/or a second voltage in response to a first potential output between a first voltage supply control unit and/or a switching unit, and/or a second potential output between a second voltage supply control unit and a switching unit. 
         [0010]    According to embodiments, first voltage supply control unit may include a first transistor connected between a first switching unit and a first voltage terminal on a first path. In embodiments, a first transistor may have a gate to receive a first input signal. In embodiments, a first voltage supply control unit may include a second transistor connected between a first switching unit and a first voltage terminal on a second path. In embodiments, a second transistor may have a gate to receive a second input signal. 
         [0011]    According to embodiments, a second voltage supply control unit may control a supply of a second voltage according to a presence and/or absence of a supply of a first voltage through a first voltage supply control unit. In embodiments, a second voltage supply control unit may include a first transistor connected between a second voltage terminal and a switching unit on a first path. In embodiments, a first transistor may have a gate connected to an output terminal of a first voltage supply control unit on a second path. In embodiments, a second voltage supply control unit may include a second transistor connected between a second voltage terminal and a switching unit on a second path. In embodiments, a second transistor may have a gate connected to an output terminal of a first voltage supply control unit on a first path. 
         [0012]    According to embodiments, a second voltage supply control unit may control a supply of a second voltage according to statuses of first and/or second input signals. In embodiments, a second voltage supply control unit may include a first transistor connected between a second voltage terminal and a switching unit on a first path. In embodiments, a first transistor may have a gate to receive a first input signal. In embodiments, a second voltage supply control unit may include a second transistor connected between a second voltage terminal and a switching unit on a second path. In embodiments, a first transistor may have a gate to receive a second input signal. 
         [0013]    According to embodiments, a switching unit may control a connection between first and second voltage supply units according to a presence and/or absence of a supply of a second voltage through a second voltage supply control unit. In embodiments, a switching unit may include a first transistor connected between first and second voltage supply control units on a first path. In embodiments, a first transistor may be controlled to be turned on according to a presence and/or absence of a supply of a second voltage on the first path through a second voltage supply control unit and/or a second transistor connected between first and second voltage supply control units on a second path. In embodiments, a second transistor may be controlled to be turned on according to a presence and/or absence a supply of a second voltage on a second path through a second voltage supply control unit. 
         [0014]    According to embodiments, a switching unit may include a third transistor connected between a gate of a second transistor and a first voltage terminal. In embodiments, a third transistor may have a gate connected to an output terminal on a second path of a second voltage supply control unit. In embodiments, a switching unit may include a fourth transistor connected between a gate of a first transistor and a first voltage terminal. In embodiments, a fourth transistor may have a gate connected to an output terminal on a first path of a second voltage supply control unit. 
         [0015]    According to embodiments, a switching unit may control a connection between first and second voltage supply units according to statuses of first and/or second input signals. According to embodiments, a switching unit may include a first transistor connected between first and second voltage supply control units on a first path. In embodiments, a first transistor may have a gate to receive a first input signal. In embodiments, a switching unit may include a second transistor connected between first and second voltage supply control units on a second path. In embodiments, a second transistor may have a gate to receive a second input signal. 
         [0016]    According to embodiments, a switching unit may control a connection between first and second voltage supply units according to a presence and/or absence of a supply of a first voltage through a first voltage supply control unit. In embodiments, a switching unit may include a first transistor connected between first and second voltage supply control units on a first path. In embodiments, a first transistor may have a gate connected to an output terminal on a first path of a first voltage supply control unit. In embodiments, a switching unity may include a second transistor connected between first and second voltage supply control units on a second path. In embodiments, a second transistor may have a gate connected to an output terminal on a second path, of a first voltage supply control unit. 
         [0017]    According to embodiments, a buffer unit may include a first transistor selectively supplying a first voltage as an output signal, which may include having a gate to receive a first potential output between a first voltage supply unit and a switching unit. In embodiments, a buffer unit may include a second transistor selectively supplying a second voltage as an output signal, which may include having a gate to receive a second potential output between a second voltage supply unit and a switching unit. 
         [0018]    According to embodiments, a first voltage may correspond to a ground voltage and/or a second voltage may correspond to a power source voltage. In embodiments, a level shift circuit may buffer a signal in response to two signals output from a level shift unit with a time difference. In embodiments, a peak value of a short-circuit current may be minimized. 
     
    
     
       DRAWINGS 
         [0019]      FIG. 1  is a diagram illustrating a level shift circuit. 
           [0020]      FIG. 2A  to  FIG. 2D  are diagrams illustrating level shift circuits in accordance with embodiments. 
       
    
    
     DESCRIPTION 
       [0021]    Embodiment relate to electrical circuits and methods thereof. According to embodiments, devices and/or methods may be suitable in a relatively wide scope of applications, including a buffer which may be configured to buffer a level-shifted voltage. In embodiments, a level shift circuit may include a level shift unit, a power source voltage supply control unit which may control a supply of power source voltage and/or a ground voltage supply control unit which may control a supply of a ground voltage. In embodiments, a level shift unit may receive an output of a power source voltage supply control unit and/or an output of a ground voltage control unit, and/or may buffers received outputs. 
         [0022]    Referring to example  FIGS. 2A to 2D , a level shift circuit in accordance with embodiments is illustrated. According to embodiments, a level shift circuit may include level shift unit  20  which may output shift signals SH 1  and/or SH 2 , which may be in response to statuses of two differentially inputted input signals IN and/or INB. In embodiments, a level shift circuit may include buffer unit  22 , which may output an output signal, such as output signal OUT, which may be in response to shift signals SH 1  and/or SH 2 . 
         [0023]    According to embodiments, level shift unit  20  may include a power source voltage supply unit which may include transistors to control a supply of a power source voltage. In embodiments, level shift unit  20  may include a ground voltage supply unit which may include transistors to control a supply of a ground voltage. In embodiments, level shift unit  20  may include a switching unit which may include transistors to control a connection between a power source voltage supply unit and a ground voltage supply unit. 
         [0024]    Referring to  FIG. 2A , a level shift circuit in accordance with embodiments is illustrated. According to embodiments, level shift unit  20  may include a power source voltage supply unit, a ground voltage supply unit having two NMOS transistors N 6 , N 9 , and/or a switching unit having two PMOS transistors P 8 , P 9  and two NMOS transistors N 7 , N 8 . In embodiments, PMOS transistor P 6  may be connected between a terminal of power source voltage VDD and node ND 11 . In embodiments, PMOS transistor P 7  may be connected between a terminal of power source voltage VDD and node ND 21 . In embodiments, a gate of PMOS transistor P 6  may be connected to node ND 22 . In embodiments, a gate of PMOS transistor P 7  may be connected to node ND 12 . In embodiments, NMOS transistor N 6  may be connected between node ND 12  and a terminal of ground voltage VSS. In embodiments, NMOS transistor N 9  may be connected between node ND 22  and a terminal of ground voltage VSS. In embodiments, a gate of NMOS transistor N 6  may receive input signal IN. In embodiments, a gate of NMOS transistor N 9  may receive inverse input signal NB. 
         [0025]    According to embodiments, PMOS transistor P 8  may be connected between two nodes ND 11 , ND 12 . In embodiments, PMOS transistor P 9  may be connected between two nodes ND 21 , ND 22 . In embodiments, NMOS transistor N 7  may be connected between a gate of PMOS transistor P 9  and a terminal of ground voltage VSS. In embodiments, NMOS transistor N 8  may be connected between a gate of PMOS transistor P 8  and a terminal of ground voltage VSS. In embodiments, a gate of NMOS transistor N 7  may be connected to node ND  21 . In embodiments, a gate of NMOS transistor N 8  may be connected to node ND 11 . 
         [0026]    According to embodiments, buffer unit  22  may include PMOS transistor P 10 , which may selectively supply power source voltage VDD to output signal OUT in response to shift signal SH 1  output from node ND 21 . In embodiments, buffer unit  22  may include NMOS transistor N 10 , which may selectively supply ground voltage VSS to output signal OUT in response to shift signal SH 2  output from node ND 22 . In embodiments, two differential input signals IN and INB may be input. In embodiments, PMOS transistor P 10  and NMOS transistor N 10  may not be substantially simultaneously turned on, for example as potentials of the two nodes ND 21  and ND 22  vary with a mutual time difference. 
         [0027]    According to embodiments, a potential of logic high level may be input as an input signal IN and/or a potential of logic low level may be input as an inverse input signal NB, such that NMOS transistor N 6  may be turned on and/or NMOS transistor N 9  may be turned off. In embodiments, NMOS transistor N 6  may be turned on, such that a potential corresponding to ground voltage VSS may be supplied to node ND 12  which may turn on PMOS transistor P 7 . In embodiments, a potential corresponding to power source voltage VDD may be supplied to node ND 21 . In embodiments, shift signal SH 1  may enters a logic high level, such that PMOS transistor P 10  may be turned off. 
         [0028]    According to embodiments, a potential corresponding to power source voltage VDD may be supplied to node ND 21 , such that NMOS transistor N 7  may be turned on and/or potential corresponding to ground voltage VSS may be supplied to a gate of PMOS transistor P 9 . In embodiments, PMOS transistor P 9  may be turned on such that a potential of node ND 21  may be supplied to node ND 22 . In embodiments, shift signal SH 2  may enter a logic high level, such that NMOS transistor N 10  may be turned on and/or output an output signal OUT having a potential corresponding to ground voltage VSS. In embodiments, NMOS transistor N 9  may be turned off by inverse input signal INB, such that when potential of node ND 22  corresponds to power source voltage VDD, PMOS transistor P 6 , NMOS transistor N 8  and/or PMOS transistor P 8  may be turned off. 
         [0029]    According to embodiments, a potential corresponding to power source voltage VDD may be supplied to two nodes ND 21 , ND 22  sequentially in time. In embodiments, shift signal SH 1  may have a potential corresponding to power source voltage VDD, and/or shift signal SH 2  may then have a potential corresponding to power source voltage VDD. In embodiments, PMOS transistor P 10  and NMOS transistor N 10  may not be substantially simultaneously turned on and/or a substantially simultaneously turned-on time may be relatively shorter than a previous one. In embodiments, a peak value of a short-circuit current may be minimized that may flow from a terminal of a power source voltage VDD to a terminal of ground voltage VSS through PMOS transistor P 10  and NMOS transistor N 10 . 
         [0030]    Referring to  FIG. 2B , a level shift circuit in accordance with embodiments is illustrated. According to embodiments, level shift unit  20  may include a power source voltage supply control unit having two PMOS transistor P 11 , P 12 , a ground voltage supply control unit having two NMOS transistors N 11 , N 12 , and a switching unit having two PMOS transistors P 13 , P 14 . In embodiments, PMOS transistor P 11  may be connected between a terminal of power source voltage VDD and node ND 31 . In embodiments, PMOS transistor P 12  may be connected between a terminal of power source voltage VDD and node ND 41 . In embodiments, a gate of PMOS transistor P 11  may be connected to node ND 42 . In embodiments, a gate of PMOS transistor P 12  may be connected to node ND 32 . 
         [0031]    According to embodiments, NMOS transistor N 11  may be connected between a terminal of ground voltage VSS and node ND 32 . In embodiments, NMOS transistor N 12  may be connected between a terminal of ground voltage VSS and node ND 42 . In embodiments, a gate of NMOS transistor N 11  may receive input signal IN and/or a gate of NMOS transistor N 12  may receive inverse input signal INB. In embodiments, PMOS transistor P 13  may be connected between two nodes ND 31 , ND 32 . In embodiments, PMOS transistor P 14  may be connected between two nodes ND 41 , ND 42 . In embodiments, a gate of PMOS transistor P 13  may receive input signal IN and/or a gate of PMOS transistor P 14  may receive inverse input signal INB. 
         [0032]    According to embodiments, buffer unit  22  may include PMOS transistor P 15 , which may selectively supply power source voltage VDD to output signal OUT in response to shift signal SH 1  output from node ND 41 . In embodiments, NMOS transistor N 13  may selectively supply ground voltage VSS to output signal OUT in response to shift signal SH 2  output from node ND 42 . In embodiments, if input signal IN of logic high level is input and/or inverse input signal INB of logic low level is input, NMOS and PMOS transistors N 11 , P 14 , respectively, may be turned on and/or NMOS and PMOS transistors N 12 , P 13 , respectively, may be turned off. In embodiments, NMOS transistor N 11  may be turned on, such that a potential corresponding to a ground voltage VSS may be supplied to node ND 32  which may turn on PMOS transistor P 12 . In embodiments, PMOS transistor P 12  may be turned on, such that a potential corresponding to power source voltage VDD may be supplied to node ND 41 . In embodiments, PMOS transistor P 14  may be turned on, such that a potential of node ND 41  may be supplied to node ND 42 . In embodiments, shift signal SH 1  may enters logic high level, such that PMOS transistor P 15  may be turned off. In embodiments, shift signal SH 2  may enter a logic high level which may turn on NMOS transistor N 13 . 
         [0033]    Referring to  FIG. 2C , a level shift circuit in accordance with embodiments is illustrated. According to embodiments, level shift unit  20  may include a power source voltage supply control unit having two PMOS transistor P 16 , P 17 , a ground voltage supply control unit having two NMOS transistors N 14 , N 15 , and/or a switching unit having two PMOS transistors P 18 , P 19 . In embodiments, PMOS transistor P 16  may be connected between a terminal of a power source voltage VDD and node ND 51 . In embodiments, PMOS transistor P 17  may be connected between terminal of power source voltage VDD and node ND 61 . In embodiments, a gate of PMOS transistor P 16  may be connected to node ND 62 . In embodiments, a gate of PMOS transistor P 17  may be connected to node ND 52 . 
         [0034]    According to embodiments, NMOS transistor N 14  may be connected between a terminal of ground voltage VSS and node ND 52 . In embodiments, NMOS transistor N 15  may be connected between a terminal of ground voltage VSS and node ND 62 . In embodiments, a gate of NMOS transistor N 14  may receive input signal IN and/or a gate of NMOS transistor N 15  may receive inverse input signal INB. In embodiments, PMOS transistor P 18  may be connected between two nodes ND 51 , ND 52 . In embodiments, PMOS transistor P 19  may be connected between two nodes ND 61 , ND 62 . In embodiments, a gate of PMOS transistor P 18  may be connected to node ND 52  and/or a gate of PMOS transistor  19  may be connected to gate node ND 62 . 
         [0035]    According to embodiment, buffer unit  22  may include PMOS transistor P 20 , which may selectively supply power source voltage VDD to output signal OUT in response to shift signal SH 1  output from node ND 61 . In embodiments, buffer unit  22  may include NMOS transistor N 16 , which may selectively supply ground voltage VSS to output signal OUT in response to shift signal SH 2  output from node ND 62 . In embodiments, an input signal IN of logic high level may be input and inverse input signal INB of logic low level may be input, such that NMOS transistor N 14  may be turned on and/or NMOS transistor N 15  may be turned off. In embodiments, NMOS transistor N 14  may be turned on, such that a potential corresponding to ground voltage VSS may be supplied to node ND 52  which may turn on PMOS transistor P 17 . In embodiments, PMOS transistor P 17  may be turned on, such that a potential corresponding to power source voltage VDD may be supplied to node ND 61 . In embodiments, PMOS transistor P 17  may be turned on, such that a potential of node ND 61  may be supplied to node ND 62 . In embodiments, shift signal SH 1  may enter a logic high level, such that PMOS transistor P 20  may be turned off. In embodiments, shift signal SH 2  may enter a logic high level which may turn on NMOS transistor N 16 . 
         [0036]    Referring to  FIG. 2C , a level shift circuit in accordance with embodiments is illustrated. In embodiments, level shift unit  20  ma include a power source voltage supply control unit having two PMOS transistor P 21 , P 22 , a ground voltage supply control unit having two NMOS transistors N 17 , N 18 , and/or a switching unit having two PMOS transistors P 23 , P 24 . In embodiments, PMOS transistor P 21  may be connected between a terminal of power source voltage VDD and node ND 71 . In embodiments, PMOS transistor P 22  may be connected between a terminal of power source voltage VDD and node ND 81 . In embodiments, a gate of PMOS transistor P 21  may receive input signal IN and/or a gate of PMOS transistor P 22  may receive inverse input signal INB. 
         [0037]    According to embodiments, NMOS transistor N 17  may be connected between a terminal of a ground voltage VSS and node ND 72 . In embodiments, NMOS transistor N 18  may be connected between a terminal of ground voltage VSS and node ND 82 . In embodiments, a gate of NMOS transistor N 17  may receive input signal IN and/or a gate of NMOS transistor N 18  may receive inverse input signal INB. In embodiments, PMOS transistor P 23  may be connected between two nodes ND 71 , ND 72 . In embodiments, PMOS transistor P 24  may be connected between two nodes ND 81 , ND 82 . In embodiments, a gate of PMOS transistor P 23  may be connected to node ND 82  and/or a gate of PMOS transistor P 24  may be connected to node ND 72 . 
         [0038]    According to embodiments, buffer unit  22  may include PMOS transistor P 25 , which may selectively supply power source voltage VDD to output signal OUT in response to shift signal SH 1  output from node ND 81 . In embodiments, a buffer unit  22  may include NMOS transistor N 19 , which may selectively supply ground voltage VSS to output signal OUT in response to shift signal SH 2  output from node ND 82 . In embodiments, input signal IN of logic high level may be input and/or inverse input signal INB of logic low level may be input, such that NMOS and/or PMOS transistors N 17  and/or P 22 , respectively, may be turned on, and/or such that NMOS and/or PMOS transistors N 18  and/or P 21 , respectively, may be turned off. In embodiments, PMOS transistor P 22  may be turned on, such that a potential corresponding to power source voltage VDD may be supplied to node ND 81 . In embodiments, NMOS transistor N 17  may be turned on, such that potential corresponding to ground voltage VSS may be supplied to node ND 72 . In embodiments, PMOS transistor P 24  may be turned on, such that a potential of node ND 81  may be supplied to node ND 82 . In embodiments, shift signal SH 1  may enter a logic high level, such that PMOS transistor P 25  may be turned off. In embodiments, shift signal SH 2  may enter a logic high level, which may turn on NMOS transistor N 19 . 
         [0039]    It will be obvious and apparent to those skilled in the art that various modifications and variations can be made in the embodiments disclosed. Thus, it is intended that the disclosed embodiments cover the obvious and apparent modifications and variations, provided that they are within the scope of the appended claims and their equivalents.