Abstract:
An image processing apparatus supporting both discrete wavelet transform and discrete cosine transform with reduced hardware resources. The image processing apparatus is composed of an input unit receiving a plurality of pixel data, a controlling unit selecting a desired transform from among discrete wavelet transform and discrete cosine transform, and providing a plurality of coefficients depending on the desired transform, and a processing unit which processes the pixel data using the plurality of coefficients to achieve the desired transform.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is related to an apparatus and method for image processing, in particular, to an image processor adaptive to a plurality of coding and decoding procedures. 
     2. Description of the Related Art 
     The JPEG (Joint Photographic Expert Group) algorithm, which uses a discrete cosine transform (DCT), is one of the most common static image compressing methods. The JPEG algorithm achieves high compression with reduced image deterioration, and thereby allows personal computers and facsimiles to process image data with reduced hardware resources. 
     The JPEG algorithm, however, suffers from several drawbacks, including image deterioration at low bit rates. 
     In order to overcome these drawbacks, JPEG 2000 algorithm has been recently standardized and become commercially available. The JPEG 2000 algorithm employs a discrete wavelet transform (DWT) to code and decode image data in place of the discrete cosine transform. 
     This situation requires image processing apparatuses to support both of the conventional JPEG and JPEG 2000 algorithms. Japanese Unexamined Patent Application No. 2001-103484 discloses an image processing apparatus selectively performing the DCT and DWT to be adaptive to the conventional JPEG and JPEG 2000 algorithms.  FIG. 1  shows a block diagram of the disclosed image processing apparatus. The disclosed image processing apparatus is composed of an input selector  50 , a DCT processor  51 , a DWT processor  52 , and an output selector  53 . The input selector  50  selects one of the DCT processor  51 , the DWT processor  52  in response to a selection signal received from a circuit, and transfers input data to the selected processor. The DCT processor  51  encodes the data received from the input selector  50  using the discrete cosine transform, while the DWT processor  52  encodes the data received from the input selector  50  using the discrete wavelet transform. The output selector  53  outputs the encoded data in response to the selector signal. 
     Japanese Unexamined Patent Application No. H06-46404 discloses an image data processing apparatus for reducing image derogation in image edges. This image data processing apparatus detects image edges in units of image blocks, and encodes the image block(s) including the detected image edge(s) using the wavelet transform in place of the discrete cosine transform. 
     An issue of the conventional image processing apparatuses is that they requires large hardware resources to support both the DCT and DWT algorithms. 
     A need exists to provide an image processing apparatus which supports both the DCT and DWT algorithms with reduced hardware resources. 
     SUMMARY OF THE INVENTION 
     Therefore, an object of the present invention is to provide an image processing apparatus which supports both the DCT and DWT algorithms with reduced hardware resources. 
     In an aspect of the present invention, an image processing apparatus is composed of an input unit receiving a plurality of pixel data, a controlling unit selecting a desired transform from among discrete wavelet transform and discrete cosine transform, and providing a plurality of coefficients depending on the desired transform, and a processing unit which processes the pixel data using the plurality of coefficients to achieve the desired transform. 
     The input unit preferably includes a storage unit storing the pixel data, and a rearrangement unit receiving and rearranging the pixel data so as to be adaptive to the desired transform in response to a control signal received from the control unit. The processing unit processes the rearranged pixel data to achieve the desired transform. 
     The processing unit preferably includes a plurality of adders, a plurality of multipliers, and an adder/subtractor unit. Each of the plurality of adders calculates a sum of two of the rearranged pixel data, the two of the rearranged pixel data being selected by the rearranged unit. Each of the plurality of multipliers calculates a product of associated one of the sums and associated one of the plurality of the coefficients. The adder/subtractor unit executes operation on the products received from the plurality of multipliers to obtain a result data of the desired transform. 
     It is advantageous if the controlling unit selects one procedure from among encoding and decoding through the desired transform, and develops the plurality of coefficients depending on the selected procedure. 
     It is also advantageous if the controlling unit selects one procedure from among encoding and decoding through the desired transform, and develops the control signal to allow the rearrangement unit to be adaptive to the selected procedure. 
     Preferably, the controlling unit selects one of an irreversible 9/7 filter and a reversible 5/3 filter to be used when selecting the discrete wavelet transform, and develops the plurality of coefficients depending on the selected filter. 
     It is also preferable that the controlling unit selects one of an irreversible 9/7 filter and a reversible 5/3 filter to be used when selecting the discrete wavelet transform, and develops the control signal to allow the rearrangement unit to be adaptive to the selected procedure. 
     The input unit may include a plurality of flipflops which respectively stores therein one of the plurality of pixel data, a rearrangement unit receiving the plurality of pixel data from the plurality of flipflops and rearranging the received pixel data so as to be adaptive to the desired transform in response to a control signal received from the control unit, and the processing unit may includes a plurality of adders, each receiving two of the plurality of pixel data selected by the rearrangement unit to calculate a sum of the received two pixel data, a plurality of multipliers, each calculating a product of associated one of the sums and associated one of the plurality of the coefficients, another multiplier receiving one of the plurality of pixel data from one of the flipflops and calculating a product of the received pixel data and associated one of the plurality of the coefficients, a selector; and an adder/subtractor unit, the selector selecting one of outputs of the another multiplier and the adder/subtractor unit, and the adder/subtractor unit executing operation on the products received from the plurality of multipliers and an output of the selector to obtain a result data of the desired transform. 
     In another aspect of the present invention, an image processing method is composed of: 
     receiving a plurality of pixel data; 
     selecting a desired transform from among discrete wavelet transform and discrete cosine transform; 
     providing a plurality of coefficients depending on the desired transform; and 
     processing the pixel data using the set of coefficients to achieve the desired transform. 
     The image processing method preferable further includes: 
     rearranging the pixel data so as to be adaptive to the desired transform, wherein the processing is executed with respect to the rearranged pixel data to achieve the desired transform. 
     the processing preferably includes: 
     providing pixel data pairs each including two of the rearranged pixel data, 
     calculating sums of respective pixel data pairs, 
     calculating products of the sums and the plurality of coefficients; 
     executing operation on the products to obtain a result data of the desired transform. 
     The image processing method preferably includes: 
     selecting one procedure from among encoding and decoding through the desired transform, wherein the plurality of coefficients are developed depending on the selected procedure. 
     The image processing method preferably includes: 
     selecting one procedure from among encoding and decoding through the desired transform, the rearranging the pixel data being executed depending on the selected desired procedure. 
     The image processing method preferably includes: 
     selecting one of an irreversible 9/7 filter and a reversible 5/3 filter to be used when selecting the discrete wavelet transform, the plurality of coefficients being developed depending on the selected filter. 
     The image processing method preferably includes: 
     selecting one of an irreversible 9/7 filter and a reversible 5/3 filter to be used when selecting the discrete wavelet transform, the rearranging being executed depending on the selected procedure. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a conventional image processing apparatus; 
         FIG. 2  is a block diagram of an image processing apparatus in a first embodiment of the present invention; 
         FIG. 3  is a detailed block diagram of the image processing apparatus in the first embodiment; 
         FIG. 4  is a table illustrating a set of coefficients provided for the multiplier unit  23  from the controller unit  30 ; 
         FIGS. 5 to 7  are timing diagrams illustrating encoding through the discrete cosine transform; 
         FIGS. 8 to 10  are timing diagrams illustrating decoding through the discrete cosine transform; 
         FIG. 11  is a block diagram of an image processing apparatus in a second embodiment; 
         FIG. 12  is a timing diagram illustrating encoding through discrete wavelet transform using a reversible 5/3 filter in the second embodiment; 
         FIG. 13  is a timing diagram illustrating decoding through discrete wavelet transform using a reversible 5/3 filter in the second embodiment; and 
         FIG. 14  is a block diagram illustrating a reversible circuit within the image processing apparatus in the second embodiment. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Preferred embodiments of the present invention are described below in detail with reference to the attached drawings. 
     DWT and DCT Algorithms 
     An image processing apparatus in accordance with the present invention encodes and decodes image data using discrete wavelet transform and discrete cosine transform. Below is an explanation of the discrete wavelet transform and the discrete cosine transform used in this embodiment. 
     The image processing apparatus is adapted to discrete wavelet transform using an irreversible 9/7 filter and/or a reversible 5/3 filter described in the following. 
     The DCT algorithm using the irreversible 9/7 filter is characterized in that the coefficients of the filter are real numbers and that the DWT algorithm fails to perform rounding of the encoded and decoded image data. 
     The DCT algorithm using the irreversible 9/7 filter encodes pixel data of even numbered columns of pixels in the image in accordance with the following equation (1):
 
 Y (2 n )= W 1*( X (2 n− 4)+ X (2 n+ 4))− W 0*( X (2 n− 3)+ X (2 n+ 3))− W 3*( X (2 n− 2)+ X (2 n+ 2))+ W 5*( X (2 n− 1)+ X (2 n+ 1))+ W 7 *X (2 n ),  (1)
 
where X(i) is an original pixel data, and Y(i) is an encoded pixel data, while encoding pixel data of odd numbered columns in accordance with the following equation (2):
 
 Y (2 n+ 1)= W 4*( X (2 n− 2)+ X (2 n+ 4))− W 2*( X (2 n− 1)+ X (2 n+ 3))− W 6*( X (2 n )+ X (2 n+ 2))+ W 8 *X (2 n+ 1)  (2)
 
where W 0  through W 7  are filter coefficients of the irreversible 9/7 filter given in the following:
         W 0 =0.0168641184 . . . ,   W 1 =0.0267487574 . . . ,   W 2 =0.0575435262 . . . ,   W 3 =0.0782232665 . . . ,   W 4 =0.0912717631 . . . ,   W 5 =0.2668641184 . . . ,   W 6 =0.5912717631 . . . ,   W 7 =0.6029490182 . . . , and   W 8 =1.1150870524 . . .       

     The DWT algorithm using the irreversible 9/7 filter, on the other hand, decodes pixel data of the even numbered columns of the pixels in accordance with the following equation (3):
 
 X (2 n )= W 0*( Y (2 n− 3)+ Y (2 n+ 3))− W 2*( Y (2 n− 2)+ Y (2 n+ 2))− W 5*( Y (2 n− 1)+ Y (2 n+ 1))+ W 8 *Y (2 n ),  (3)
 
while decoding pixel data of the odd numbered columns in accordance with the following equation (4):
 
 X (2 n+ 1)= W 1*( Y (2 n− 3)+ Y (2 n+ 5))− W 4*( Y (2 n− 2)+ Y (2 n+ 4))− W 3*( Y (2 n− 1)+ Y (2 n+ 3))+ W 6*( Y (2 n )+ Y (2 n+ 2))+ W 7 *Y (2 n+ 1)  (4)
 
where W 0  through W 7  are the above-described filter coefficients.
 
     The DWT algorithm using the reversible 5/3 filter, on the other hand, is characterized in that the coefficients of the filter are integers and that the DWT algorithm performs rounding of the encoded and decoded image data to integerize. 
     The DWT algorithm using the reversible 5/3 filter encodes pixel data of even numbered columns of pixels in the image in accordance with the following equation (5): 
                       Y   ⁡     (       2   ⁢   n     +   1     )       =       X   ⁡     (       2   ⁢   n     +   1     )       -     [         X   ⁡     (     2   ⁢   n     )       +     X   ⁡     (       2   ⁢   n     +   2     )         2     ]         ,           (   5   )               
while encoding pixel data of odd numbered columns of pixels in accordance with the following equation (6):
 
                       Y   ⁡     (     2   ⁢   n     )       =       X   ⁡     (     2   ⁢   n     )       -     [         Y   ⁡     (       2   ⁢   n     -   1     )       +     Y   ⁡     (       2   ⁢   n     +   1     )       +   2     4     ]         ,           (   6   )               
where [x] is the floor function defined as follows: for a real number x, [x] is the largest integer less than or equal to x,
 
     The DWT algorithm using the reversible 5/3 filter, on the other hand, decodes pixel data of the even numbered columns of pixels in accordance with the following equation (7): 
                       X   ⁡     (     2   ⁢   n     )       =       Y   ⁡     (     2   ⁢   n     )       -     [         Y   ⁡     (       2   ⁢   n     -   1     )       +     Y   ⁡     (       2   ⁢   n     +   1     )       +   2     4     ]         ,           (   7   )               
while decoding pixel data of the odd numbered columns of pixels in accordance with the following equation (8):
 
     
       
         
           
             
               
                 
                   
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                       ( 
                       
                         
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                         [ 
                         
                           
                             
                               X 
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                                 ( 
                                 
                                   2 
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                                   n 
                                 
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                             + 
                             
                               X 
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                                     2 
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                                     n 
                                   
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                                   2 
                                 
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                           2 
                         
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                       . 
                     
                   
                 
               
               
                 
                   ( 
                   8 
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     The image processing apparatus also performs a DCT algorithm described in the following. The DCT algorithm encodes pixel data of even numbered columns of pixels in accordance with the following equation (9): 
                       [         F0           F4           F2           F6         ]     =       [           a0   +   a1   +   a3   +   a2         0       0             a0   -   a1   +   a3   -   a2         0       0           0         a0   -   a3           a1   -   a2             0           -   a1     +   a2           a0   -   a3           ]     ⁡     [         D3           D5           D1         ]         ,           (   9   )               
while encoding pixel data of odd numbered columns of pixels in accordance with the following equation (10):
 
                       [         F1           F3           F5           F7         ]     =       [         a4       a5       a6       a7             -   a6         a4         -   a7           -   a5               -   a5         a7       a4       a6             -   a7         a6         -   a5         a4         ]     ⁡     [         D6           D4           D2           D0         ]         ,           (   10   )               
where F 0  through F 7  are encoded pixel data, D 0  through D 6  are filter coefficients defined as follows:
         D 0 =0.19509032,   D 1 =0.38268343,   D 2 =0.55557023,   D 3 =0.70710678,   D 4 =0.83146961,   D 5 =0.92387953, and   D 6 =0.98078528,
 
and a 0  through a 7  are coefficients defined as follows:
 
 a 0 =f 0 +f 7,
 
 a 1 =f 1 +f 6,
 
 a 2 =f 2 +f 5,
 
 a 3 =f 3 +f 4,
 
 a 4 =f 0 −f 7,
 
 a 5 =f 1 −f 6,
 
 a 6 =f 2 −f 5, and
 
 a 7 =f 3 −f 4,  (11)
 
where f 0  through f 7  are original pixel data.
       
     The DCT algorithm decodes pixel data of the even numbered columns of pixels in accordance with the following equations (12) and (13): 
                         1   2     ⁡     [                       f0   +   f4               f1   +   f5                     f2   +   f6                     f3   +   f7           ]       =       [           a0   +   a3         a2       a1             a0   -   a3           -   a1           -   a2               a0   -   a3         a1         -   a2               a0   +   a3           -   a2           -   a1           ]     ⁡     [         D3           D5           D1         ]         ,   and           (   12   )                       1   2     ⁡     [                       f0   -   f4               f1   -   f5                     f2   -   f6                     f3   -   f7           ]       =       [         a5       a7         -   a6           -   a4             a6       a5       a4         -   a7               -   a7           -   a4         a5         -   a6             a4         -   a6           -   a7         a5         ]     ⁡     [         D6           D4           D2           D0         ]         ,     ⁢                   (   13   )               
where a 0  through a 7  are coefficients defined as follows:
 a0=F0, a1=F6, a2=F2, a3=F4,   a 4 =−F 7, a5=F1,   a 6 =−F 5, and a7=F3.  (14) 
     First Embodiment 
       FIG. 2  shows a block diagram of an image processing apparatus in a first embodiment. The image processing apparatus in this embodiment is designed to support both discrete cosine transform and discrete wavelet transform using an irreversible 9/7 filter. 
     The image processing unit in this embodiment, is composed of an input unit  10 , a processing unit  20 , and a controller unit  30 , which are monolithically integrated within an LSI (large scale integrated circuit). 
     The input unit  10  includes a storage unit  11  and a rearranging circuit  12 . The storage unit  11  stores therein pixel data received from an external device. The storage unit  11  transfers the stored pixel data to the rearranging circuit  12 . As described below, the storage unit  11  is composed of a shift register. 
     The rearranging circuit  12  rearranges the order of the pixel data received from the storage unit  11  so that the order of the pixel data is adaptive to the discrete wavelet transform or the discrete cosine transform in response to a control signal received from the controller unit  30 . The rearranging circuit  12  defines pixel data pairs, which are different two of the pixel data. The rearranged pixel data is transferred to the processing unit  20 . 
     The processing unit  20  is composed of an adder unit  21 , a multiplier unit  22 , and an adder/subtractor unit  23 . The adder unit  21  calculates sums of the respective pixel data pairs or differences between the respective pixel data pairs, in response to a control signal S 2  received from the controller unit  30 . For the discrete wavelet transform in accordance with the equation (1), for example, the adder unit  21  calculates the sums a 1  to a 4  in parallel as follows:
 
 a 1 =X (2 n− 4)+ X (2 n+ 4),
 
 a 2 =X (2 n− 3)+ X (2 n+ 3),
 
 a 3 =X (2 n− 2)+ X (2 n+ 2), and
 
 a 4 =X (2 n− 1)+ X (2 n+ 1).
 
The calculated sums are transferred to the multiplier unit  23 .
 
     The multiplier unit  23  receives a control signal S 2  representative of filter coefficients from the controller unit  30 , and calculates respective products of the sums received from the adder unit  21  and the associated filter coefficients received from the controller unit  30 . For the discrete wavelet transform in accordance with the equation (1), for example, the multiplier unit  23  calculates the products MPY 1  to MPY 5  in parallel as follows:
 
 MPY 1 =W 1 ×a 1,
 
 MPY 2 =W 0 ×a 2,
 
 MPY 3 =W 3 ×a 3,
 
 MPY 4 =W 5 ×a 4, and
 
 MPY 5 =W 7 ×X (2 n ).
 
The calculated products are transferred to the adder/subtractor unit  25 .
 
     The adder/subtractor unit  25  is responsive to a control signal S 3  received from the controller unit  30  for calculating addition and/or subtraction with respect to the products MPY 1  to MPY 5 , and thereby obtains the encoded or decoded pixel data. For the discrete wavelet transform in accordance with the equation (1), for example, the adder/subtractor unit  25  calculates the encoded pixel data Y(2n) defined by the following equation:
 
 Y (2 n )= MPY 1 −MPY 2 −MPY 3 +MPY 4 +MPY 5.
 
The same goes for the equations (2) to (4) and the equations (9), (10), (12) and (13).
 
     The controller unit  30  provides the control signals S 1  for the input unit  10  and the control signals S 2  to S 4  for the processing unit  20 . The controller unit  30  determines which operation is to be performed, and indicate the input unit  10  and the processing unit  20  to perform the determined operation by providing the control signals S 1  to S 4 . The determined operation includes: encoding and decoding through the discrete wavelet transform using the irreversible 9/7 filter, and encoding and decoding through the discrete cosine transform. 
       FIG. 3  shows a detailed block diagram of the processing apparatus in this embodiment. The processing unit  20  includes latches  22  and  24 , a flipflop FF 19 , a limiter  26 , and a flipflop  20  in addition to the adder unit  21 , the multiplier unit  23 , and the adder/subtractor unit  25 . 
     The storage device  11  is composed of a flipflop FF inp  and a set of flipflops FF 0  through FF 8 . The flipflops FF 0  to FF 8  are provided to store pixel data f 0  to f 8 . The pixel data f 4  is associated with the pixel of interest of the discrete wavelet transform, and the pixel data f 0  to f 3 , and f 5  to f 8  are associated with the pixels adjacent to the pixel of interest. 
     The flipflop FF inp  functions as a buffer receiving the pixel data to be encoded or decoded. The output of the flipflop FF inp  is connected to the input of the flipflop FF 0 . The flipflops FF 0  through FF 8  are connected in serial to constitute a shift register. The flipflop FF inp  and flipflops FF 0  through FF 8  receives the same clock signal (not shown) and operates in synchronization with the clock signal. The received pixel data is transferred through the flipflops FF 0  and FF 8  in response to the clock signal. In an alternative embodiment, the flipflops FF 0  and FF 8  may directly receive the pixel data in parallel. The outputs of the respective flipflops FF 0  to FF 8  are connected to the rearrangement circuit  12 . 
     The rearrangement circuit  12  rearranges the order of the pixel data f 0  to f 8  as indicated by the control signal S 1  from the controller unit  30  to provide a set of pixel data m 1  to m 8 . The rearrangement of the pixel data f 0  to f 8  depends on which transform is to be performed. 
     The row indicated by the symbol “9/7 encoding” represents which pixel data are outputted as the respective pixel data m 1  to m 8  for the encoding through the discrete wavelet transform using the irreversible 9/7 filter. The rearrangement of the pixel data is executed depending on whether the pixel of interest is positioned in the even numbered columns or in the odd numbered columns. In detail, the rearrangement circuit  12  outputs the pixel data f 8  as the pixel data m 1 , regardless of the position of the pixel of interest. The rearrangement circuit  12  outputs the pixel data f 0  as the pixel data m 2  in the event that the pixel of interest is positioned in the even numbered column; otherwise the rearrangement circuit  12  outputs zero as the pixel data m 2 . The rearrangement circuit  12  outputs the pixel data f 7 , f 1 , f 6 , f 2 , f 5  and f 3  as the pixel data m 3 , m 4 , m 5 , m 6 , m 7 , and m 8 , respectively, regardless of the position of the pixel of interest. 
     Correspondingly, the row indicated by the symbol “9/7 decoding” represents which pixel data are outputted for the decoding through the discrete wavelet transform using the irreversible 9/7 filter. The rearrangement circuit  12  outputs zero as the pixel data m 1  in the event that the pixel of interest is positioned in the even numbered column; otherwise, the rearrangement circuit  12  outputs the pixel data f 8  as the pixel data m 1 . The rearrangement circuit  12  outputs zero as the pixel data m 2  in the event that the pixel of interest is positioned in the even numbered column; otherwise the rearrangement circuit  12  outputs the pixel data f 0  as the pixel data m 2 . And, the rearrangement circuit  12  outputs the pixel data f 7 , f 1 , f 6 , f 2 , f 5  and f 3  as the pixel data m 3 , m 4 , m 5 , m 6 , m 7 , and m 8 , respectively, regardless of the position of the pixel of interest. 
     The adder unit  21  is composed of a set of adders  21   1  to  21   4 . The adder  21   1  calculates the sum of the pixel data m 1  and m 2 . The sum of the pixel data m 1  and m 2  is denoted by the numeral “a 1 ” or “a 5 ”. Correspondingly, the adder  21   2 ,  21   3 , and  21   4  calculate the sum of the pixel data m 3  and m 4 , the sum of the pixel data m 5  and m 6 , and the sum of the pixel data m 7  and m 8 , respectively. The sum of the pixel data m 3  and m 4  is denoted by the numeral “a 2 ” or “a 6 ”, the sum of the pixel data m 5  and m 6  is denoted by the numeral “a 3 ” or “a 7 ”, and the sum of the pixel data m 7  and m 8  is denoted by the numeral “a 4 ” or “a 8 ”. The calculated sums a 1  through a 8  are transferred to the latch  22 . 
     The latch  22  is composed of a set of flipflops FF 9  and FF 13 . The flipflop FF 9  latches the sum a 1  (or a 5 ) received from the adder  21   1  and transfers the latched sum a 1  (or a 5 ) to the multiplier unit  23 . The flipflop FF 10  latches the sum a 2  (or a 6 ) received from the adder  21   2 , and transfers the latched sum a 2  (or a 6 ) to the multiplier unit  23 . The flipflop FF 11  latches the sum a 3  (or a 7 ) received from the adder  21   3 , and transfers the latched sum a 3  (or a 7 ) to the multiplier unit  23 . The flipflop FF 12  latches the sum a 4  (or a 8 ) received from the adder  21   4 , and transfers the latched sum a 4  (or a 8 ) to the multiplier unit  23 . The flipflop FF 13  latches the pixel data f 4  from the flipflop FF 4 , and transfers the latched pixel data to the multiplier unit  23 . 
     The multiplier  23  is composed of a set of multipliers  23   1  to  23   5 . The multiplier  23   1  calculate a product MPY 1  of the sum a 1  (or a 5 ) received from the flipflop FF 9  and a coefficient α described in the control signal S 3  from the controller unit  30 . The product MPY 1  is transferred to the latch  24 . Correspondingly, the multiplier  23   2  calculate a product MPY 2  of the sum a 2  (or a 6 ) received from the flipflop FF 10  and a coefficient β described in the control signal S 3  from the controller unit  30 . The product MPY 2  is transferred to the latch  24 . The multiplier  23   3  calculate a product MPY 3  of the sum a 3  (or a 7 ) received from the flipflop FF 11  and a coefficient γ described in the control signal S 3  from the controller unit  30 . The product MPY 3  is transferred to the latch  24 . The multiplier  23   4  calculate a product MPY 3  of the sum a 4  (or a 8 ) received from the flipflop FF 12  and a coefficient δ described in the control signal S 3  from the controller unit  30 . The product MPY 4  is transferred to the latch  24 . And the multiplier  23   5  calculate a product MPY 5  of the pixel data f 4  received from the flipflop FF 13  and a coefficient ε described in the control signal S 3  from the controller unit  30 . The product MPY 5  is transferred to the latch  24 . 
     As shown in  FIG. 4 , the coefficient α depends on the kind of the transfer to be performed as described in the following. For encoding through the discrete wavelet transform using the irreversible 9/7 filter, the coefficient a is set to the aforementioned coefficient W 1  in the event that the pixel of interest is positioned in the event numbered columns, while set to zero (0) in the event that the pixel of interest is positioned in the odd numbered columns. For decoding through the discrete wavelet transform using the irreversible 9/7 filter, the coefficient α is set to zero in the event that the pixel of interest is positioned in the even numbered columns, while set to W 1  in the event that the pixel of interest is positioned in the odd numbered columns. For both encoding and decoding through the discrete cosine transform, the coefficient α is set to D 0  in the event that the pixel of interest is positioned in the even numbered columns, while set to D 5  in the event that the pixel of interest is positioned in the odd numbered columns. 
     Correspondingly, the coefficients β through ε depend on the kind of the transfer to be performed as described in the following. For encoding through the discrete wavelet transform using the irreversible 9/7 filter, the coefficient β is set to −W 0  in the event that the pixel of interest is positioned in the even numbered columns, while set to W 4  in the event that the pixel of interest is positioned in the odd numbered columns. For decoding through the discrete wavelet transform using the irreversible 9/7 filter, the coefficient β is set to W 0  in the event that the pixel of interest is positioned in the even numbered columns, while set to −W 4  in the event that the pixel of interest is positioned in the odd numbered columns. For both encoding and decoding through the discrete cosine transform, the coefficient β is set to D 1  in the event that the pixel of interest is positioned in the even numbered columns, while set to D 4  in the event that the pixel of interest is positioned in the odd numbered columns. 
     For encoding through the discrete wavelet transform using the irreversible 9/7 filter, the coefficient γ is set to −W 3  in the event that the pixel of interest is positioned in the even numbered columns, while set to −W 2  in the event that the pixel of interest is positioned in the odd numbered columns. For decoding through the discrete wavelet transform using the irreversible 9/7 filter, the coefficient γ is set to −W 3  in the event that the pixel of interest is positioned in the even numbered columns, while set to −W 2  in the event that the pixel of interest is positioned in the odd numbered columns. For both encoding and decoding through the discrete cosine transform, the coefficient γ is set to D 3  in the event that the pixel of interest is positioned in the even numbered columns, while set to D 2  in the event that the pixel of interest is positioned in the odd numbered columns. 
     For encoding through the discrete wavelet transform using the irreversible 9/7 filter, the coefficient δ is set to W 5  in the event that the pixel of interest is positioned in the even numbered columns, while set to −W 6  in the event that the pixel of interest is positioned in the odd numbered columns. For decoding through the discrete wavelet transform using the irreversible 9/7 filter, the coefficient δ is set to −W 5  in the event that the pixel of interest is positioned in the even numbered columns, while set to W 6  in the event that the pixel of interest is positioned in the odd numbered columns. For both encoding and decoding through the discrete cosine transform, the coefficient δ is set to zero in the event that the pixel of interest is positioned in the even numbered columns, while set to D 0  in the event that the pixel of interest is positioned in the odd numbered columns. 
     For encoding through the discrete wavelet transform using the irreversible 9/7 filter, the coefficient ε is set to W 7  in the event that the pixel of interest is positioned in the even numbered columns, while set to W 8  in the event that the pixel of interest is positioned in the odd numbered columns. For decoding through the discrete wavelet transform using the irreversible 9/7 filter, the coefficient ε is set to W 8  in the event that the pixel of interest is positioned in the even numbered columns, while set to W 7  in the event that the pixel of interest is positioned in the odd numbered columns. For both encoding and decoding through the discrete cosine transform, the coefficient ε is set to zero regardless of the position of the pixel of interest. 
     The latch  24  is composed of a set of flipflops FF 14  through FF 18 . The flipflop FF 14  latches the product MPY 1  from the multiplier  24   1 , and transfers the latched product MPY 1  to the adder/subtractor unit  25 . The flipflop FF 15  latches the product MPY 2  from the multiplier  24   2 , and transfers the latched product MPY 2  to the adder/subtractor unit  25 . The flipflop FF 16  latches the product MPY 3  from the multiplier  24   3 , and transfers the latched product MPY 3  to the adder/subtractor unit  25 . The flipflop FF 17  latches the product MPY 4  from the multiplier  24   4 , and transfers the latched product MPY 4  to the adder/subtractor unit  25 . The flipflop FF 18  latches the product MPY 5  from the multiplier  24   5 , and transfers the latched product MPY 5  to the adder/subtractor unit  25 . 
     The adder/subtractor unit  25  is composed of adder  25   1  through  25   4  and a selector  25   5 . The selector  25   5  selects one of the data received from flipflops F 8  and F 19  in response to the control signal S 4  received from the controller unit  30 , and outputs the selected data. The data from the flipflop F 8  is selected for the discrete wavelet transform, while the data from the flipflop F 19  is selected for the discrete cosine transform. 
     The adder  25   1  calculates the sum Σ 1  of the products MPY 1  and MPY 2  received from the flipflops FF 14  and FF 15 , respectively. The adder  25   1  also calculates the sum Σ 2  of the products MPY 2  and MPY 3  received from the flipflops FF 15  and FF 16 , respectively. 
     The adder  25   2  calculates the sum Σ 3  of the sum Σ 2  received from the adder  25   1  and the product MPY 4  received from the flipflop FF 17 . The adder  25   2  also calculates the sum Σ 4  of the product MPY 4  and the data received from the selector  25   5 . The sums Σ 3  and Σ 4  are transferred to the adder  25   3 . 
     The adder  25   3  calculates the sum Σ 5  of the sums Σ 1  and Σ 3  received from the adder  25   1  and the adder  25   2 , respectively. The adder  25   3  also calculates the sum Σ 6  of the sums Σ 3  and Σ 4  received from the adder  25   2 . 
     The adder  25   4  calculates the sum Σ 7  of the sums Σ 5  and Σ 6  received from the adder  25   3 . The sum Σ 7  is transferred to the flipflop FF 19 . 
     The flipflop FF 19  latches the sum Σ 7  and transfers the latched sum Σ 7  to the selector  25   5  and the limiter  26 . 
     The limiter  26  receives the sum Σ 7  from the flipflop FF 19 , and outputs an output data defined as follows: the output data is equal to the sum Σ 7  in the event that the sum Σ 7  is smaller than a specified value, while the output data is equal to the specified value in the event that the sum Σ 7  is equal to or larger than the specified value. 
     The flipflop FF 20  latches the output data received from the limiter  26 , and develops the latched output data on the output. 
     The aforementioned latches  22 ,  23 , flipflops  19  and  20  allows the image processing apparatus to achieve pipeline processing. One skilled in the art would appreciate that the latches  22 ,  23 , flipflops  19  and  20  may be removed in an alternative embodiment. 
     Below is an explanation of the operation of the image processing apparatus in this embodiment. 
     1-1) Procedure of Encoding Pixel Data through the Discrete Wavelet Transform Using the Irreversible 9/7 Filter 
     This procedure begins with providing pixel data for the storage unit  11 . It should be noted that “mirror” pixel data of “virtual pixels” may be provided for the storage unit  11  when the pixel of interest is close to the end of the image The virtual pixels are defined as being pixels virtually disposed around the image, which are symmetrical to the pixels near the end of the image. The “mirror” pixel data are defined as the pixel data associated with the “virtual pixels”. The pixel data associated with the pixel of interest is set to the flipflop FF 4  of the storage unit  11 . 
     After the pixel data f 0  through f 8  are respectively latched into the flipflop FF 0  through FF 8 , the controller unit  30  develops the control signal S 1  to indicate the rearrangement circuit  12  to perform the rearrangement of the pixel data f 0  through f 8  so that the order of the pixel data f 0  through f 8  are adapted to encoding through the discrete wavelet transform using the irreversible 9/7 filter. In response to the control signal S 1 , the rearrangement circuit  12  executes the rearrangement as indicated by the row denoted by “9/7 (ENCODING)”. In the event that the pixel of interest is positioned in the even numbered columns, for example, the rearrangement circuit  12  outputs the pixel data f 8 , which is associated with X(2n+4) in the equation (1), as the pixel data m 1 , while outputting the pixel data f 0 , which is associated with X(2n−4) in the equation (1), as the pixel data m 2 . The same goes for the pixel data m 3  through m 8 . In the event that the pixel of interest is positioned in the odd numbered columns, the rearrangement circuit  12  outputs zero in place of the pixel data f 0 , as the pixel data m 2 . 
     The controller unit  30  then develops the control signal S 2  to indicate the adder  21   1  to  21   4  to execute addition. The adder  21   1  calculates the sum a 1  of the pixel data m 1  and m 2 . The calculation of the sum a 1  is equivalent to the calculation of the term “X(2n−4)+X(2n+4)” in the equation (1). The sum a 1  is transferred to the flipflop FF 9  of the latch  22 . Correspondingly, the adder  21   2 ,  21   3 , and  21   4  calculate the sum a 2  of the pixel data m 3  and m 4 , the sum a 3  of the pixel data m 5  and m 6 , and the sum a 4  of the pixel data m 7  and m 8 , respectively The calculations of sums a 2 , a 2  and a 3  are equivalent to the calculations of the term “X(2n+3)+X(2n−3)”, “X(2n+2)+X(2n−2)”, and “X(2n+1)+X(2n−1)”, respectively, in the equation (1). The sums a 2 , a 3 , and a 4  are transferred to the flipflops FF 10 , FF 11 , FF 12 , respectively. 
     In the meantime, the flipflop FF 13  receives the pixel data f 4 , associated with the pixel of interest, from the flipflop FF 4 . 
     The controller unit  30  then develops the control signal S 3  describing the coefficients α to ε so that the coefficients α to ε are adaptive to encoding through the discrete wavelet transform using the irreversible 9/7 filter. In the event that the pixel of interest is positioned in the even numbered columns, the coefficient α is set to W 1 , and this results in that the multiplier  23   1  calculates the product MPY 1  of the sum a 1  and the coefficient W 1 . The calculation of the product MPY 1  is equivalent to the calculation of the term “W 1 ×{X(2n−4)+X(2n+4)}” in the equation (1). In the event that the pixel of interest is positioned in the even numbered columns, on the other hand, the product MPY 1  is set to zero, because the coefficient α is defined as being zero. The product MPY 1  is transferred from the multiplier  23   1  to the flipflop FF 14  of the latch  24 . 
     Correspondingly, the coefficient β is set to −W 0  in the event that the pixel of interest is positioned in the even numbered columns, and this results in that the multiplier  23   2  calculates the product MPY 2  of the sum a 2  and the coefficient −W 0 . The calculation of the product MPY 2  is equivalent to the calculation of the term “−W 0 ×{X(2n−3)+X(2n+3)}” in the equation (1). In the event that the pixel of interest is positioned in the even numbered columns, on the other hand, the coefficient β is set to W 4 , and this results in that the multiplier  23   2  calculates the product MPY 2  of the sum a 2  and the coefficient W 4 . The calculation of the product MPY 2  is equivalent to the calculation of the term “W 4 ×{X(2n−3)+X(2n+3)}” in the equation (1). The product MPY 2  is transferred from the multiplier  23   2  to the flipflop FF 15  of the latch  24 . 
     Correspondingly, the coefficient γ is set to −W 3  in the event that the pixel of interest is positioned in the even numbered columns, and this results in that the multiplier  23   3  calculates the product MPY 3  of the sum a 3  and the coefficient −W 3 . The calculation of the product MPY 3  is equivalent to the calculation of the term “−W 3 ×{X(2n−2)+X(2n+2)}” in the equation (1). In the event that the pixel of interest is positioned in the even numbered columns, on the other hand, the coefficient γ is set to −W 2 , and this results in that the multiplier  23   3  calculates the product MPY 3  of the sum a 3  and the coefficient −W 2 . The calculation of the product MPY 3  is equivalent to the calculation of the term “−W 2 ×{X(2n−2)+X(2n+2)}” in the equation (1). The product MPY 3  is transferred from the multiplier  23   3  to the flipflop FF 16  of the latch  24 . 
     Correspondingly, the coefficient δ is set to W 5  in the event that the pixel of interest is positioned in the even numbered columns, and this results in that the multiplier  23   4  calculates the product MPY 4  of the sum a 4  and the coefficient W 5 . The calculation of the product MPY 4  is equivalent to the calculation of the term “W 5 ×{X(2n−1)+X(2n+1)}” in the equation (1). In the event that the pixel of interest is positioned in the even numbered columns, on the other hand, the coefficient δ is set to −W 6 , and this results in that the multiplier  23   4  calculates the product MPY 4  of the sum a 4  and the coefficient −W 6 . The calculation of the product MPY 3  is equivalent to the calculation of the term “−W 6 ×{X(2n−1)+X(2n+1)}” in the equation (1). The product MPY 4  is transferred from the multiplier  23   4  to the flipflop FF 17  of the latch  24 . 
     Correspondingly, the coefficient ε is set to W 7  in the event that the pixel of interest is positioned in the even numbered columns, and this results in that the multiplier  23   5  calculates the product MPY 5  of the pixel data f 4  from the flipflop FF 13  and the coefficient W 5 . The calculation of the product MPY 5  is equivalent to the calculation of the term “W 7 ×X(2n)” in the equation (1). In the event that the pixel of interest is positioned in the even numbered columns, on the other hand, the coefficient ε is set to W 8 , and this results in that the multiplier  23   5  calculates the product MPY 5  of the pixel data f 4  and the coefficient W 8 . The calculation of the product MPY 5  is equivalent to the calculation of the term “W 8 ×X(2n+1)” in the equation (1). The product MPY 5  is transferred from the multiplier  23   5  to the flipflop FF 18  of the latch  24 . 
     The controller unit  30  develops the control signal S 4  to indicate the selector  25   5  within the adder/subtractor unit  25  to select the output of the flipflop FF 18 . This allows the adder/subtractor unit  25  to calculate the sum of the products MPY 1  to MPY 5  received from the respective flipflops FF 14  to FF 18  by using the adder  25   1  to adder  25   4 . The sum of the products MPY 1  to MPY 5  is equal to Y(2n) in the equation (1) in the event that the pixel of interest is positioned in the even numbered columns, while equal to Y(2n+1) in the equation (2) in the event that the pixel of interest is positioned in the odd numbered columns. After the calculation of Y(2n) or Y(2n+1), the adder/subtractor unit  25  transfers Y(2n) or Y(2n+1) to the flipflop FF 19 . 
     The flipflop FF 19  provides the limiter  26  with Y(2n) or Y(2n+1), and the output of the limiter  26  is latched by the flipflop FF 20 . The output of the flipflop FF 20  is the encoded pixel data for the pixel of interest. 
     The same goes for the other pixels of the image, and this achieves 2-dimentional discrete wavelet transform of the pixel data. 
     (1-2) Decoding through the Discrete Wavelet Transform Using the Irreversible 9/7 Filter 
     The procedure of decoding the pixel data through the discrete wavelet transform using the irreversible 9/7 filter is almost identical to that of encoding, except for that the rearrangement of the pixel data f 0  to f 8  is executed as indicated by the row “9/7 DECODING” in  FIG. 3 , and that the coefficients α to ε are set to the value as indicated by the second row in  FIG. 3 . Therefore, no detailed explanation of the decoding is given. 
     (1-3) Encoding through the Discrete Cosine Transform  FIGS. 5 to 7  are timing diagrams illustrating the procedure of encoding the pixel data through the discrete cosine transform. The procedures at clock periods CLK 1  to CLK 27 , which are defined by a clock signal, are respectively described below in detail.
 
Clock Periods CLK 1  to CLK 9 
 
     As shown in  FIG. 5 , the pixel data f 0  to f 7  are serially transferred to the flipflop FF 0  to FF 7 , respectively, during the clock period CLK 1  through CLK 9 . After the flipflops FF 0  to FF 7  latches the pixel data f 0  to f 7 , the processing apparatus starts encoding the pixel data of the pixels. 
     At the clock period CLK 9 , the controller unit  30  develops the control signal S 1  to indicate the rearrangement circuit  12  to execute a procedure defined for the clock period CLK 9 . In response to the control signal S 1 , the rearrangement circuit  12  outputs the pixel data f 0 , and f 7  as the pixel data m 5 , and m 6 , respectively. The adder  21   3  calculates the sum of the pixel data m 5  and m 6 , that is, the sum a 0  (=f 0 +f 7 ) in the equation (9). The calculated sum a 0  is stored into the flipflop FF 11  at the end of the clock period CLK 9 . It should be noted that  FIGS. 5 to 7  refer to invalid data as symbols “*”, while referring to zero as symbols “x 0 ”. 
     Clock Period CLK 10   
     At the following clock period CLK 10 , the rearrangement circuit  12  outputs the pixel data f 1  and f 6  as the pixel data m 5  and m 6 , respectively, in response to the control signal S 1 , which is developed to indicate the rearrangement circuit  12  to execute a procedure defined for the clock period CLK 10 . The adder  21   3  calculates the sum of the pixel data m 5  and m 6 , that is, the sum a 1  (=f 1 +f 6 ) in the equation (9). The calculated sum a 1  is stored into the flipflop FF 11  at the end of the clock period CLK 10 . 
     In the meantime, the controller unit  30  sets the coefficient γ to D 3 , and the multiplier  23   3  receives the sum a 0  (=f 0 +f 7 ) from the flipflop FF 11 . This allows the multiplier  23   3  to calculate the product of the sum a 0  and the coefficient D 3  as described in the equation (10). The calculated product “a 0 ×D 3 ” is stored into the flipflop FF 16  at the end of the clock period CLK 10 . 
     In addition, the flipflops FF 14 , FF 15 , and FF 17  are reset to zero at the end of the clock period CLK 10 . 
     Clock Period CLK 11   
     During the following clock period CLK 11 , the rearrangement circuit  12  outputs the pixel data f 2  and f 5  as the pixel data m 5  and m 6 , respectively, in response to the control signal S 1 , which is developed to indicate the rearrangement circuit  12  to execute a procedure defined for the clock period CLK 11 . The adder  21   3  calculates the sum of the pixel data m 5  and m 6 , that is, the sum a 2  (=f 2 +f 5 ) described in the equation (9). The calculated sum a 2  is stored into the flipflop FF 11  at the end of the clock period CLK 11 . 
     In the mean time, the controller unit  30  sets the coefficient γ to D 3 , and the multiplier  23   3  receives the sum a 1  (=f 1 +f 6 ) from the flipflop FF 11 . This allows the multiplier  23   3  to calculate the product of the sum a 1  and the coefficient D 3  as described in the equation (10). The calculated product “a 1 ×D 3 ” is stored into the flipflop FF 16  at the end of the clock period CLK 11 . 
     In addition, the flipflops FF 14 , FF 15 , and FF 17  are reset to zero at the end of the clock period CLK 11 . 
     Furthermore, the adder/subtractor unit  25  calculates the sum of the outputs of the flipflops FF 14  to FF 17  and the selector  25   5 . The fact that the flipflops FF 14 , FF 15 , and FF 17  are reset to zero results in that the output of the adder/subtractor unit  25  is equal to the output of the flipflop FF 16 , that is, the product “a 0 ×D 3 ”. The product “a 0 ×D 3 ” is latched by the flipflop FF 19  at the end of the CLK 11 . 
     Clock Period CLK 12   
     During the following clock period CLK 12 , the rearrangement circuit  12  outputs the pixel data f 3  and f 4  as the pixel data m 5  and m 6 , respectively, in response to the control signal S 1 , which is developed to indicate the rearrangement circuit  12  to execute a procedure defined for the clock period CLK 12 . The adder  21   3  calculates the sum of the pixel data m 5  and m 6 , that is, the sum a 3  (=f 3 +f 4 ) described in the equation (9). The calculated sum a 3  is stored into the flipflop FF 11  at the end of the clock period CLK 12 . 
     In the mean time, the controller unit  30  sets the coefficient γ to D 3 , and the multiplier  23   3  receives the sum a 2  (=f 2 +f 5 ) from the flipflop FF 11 . This allows the multiplier  23   3  to calculate the product of the sum a 2  and the coefficient D 3  as described in the equation (10). The calculated product “a 2 ×D 3 ” is stored into the flipflop FF 16  at the end of the clock period CLK 11 . 
     In addition, the flipflops FF 14 , FF 15 , and FF 17  are reset to zero at the end of the clock period CLK 12 . 
     Furthermore, the adder/subtractor unit  25  calculates the sum of the outputs of the flipflops FF 14  to FF 17  and the selector  25   5 . The fact that the selector  25   5  selects the output of the flipflop FF 19 , and the flipflops FF 14 , FF 15 , and FF 17  are reset to zero results in that the adder/subtractor unit  25  calculates the sum of the product “a 0 ×D 3 ” received from the flip-flop FF 19  and the product “a 1 ×D 3 ” received from the flipflop FF 16 , that is, the term “(a 0 +a 1 )×D 3 ”. The calculated term “(a 0 +a 1 )×D 3 ” is latched by the flipflop FF 19  at the end of the CLK 12 . 
     Furthermore, the product “a 0 ×D 3 ”, which has been latched by the flipflop FF 19 , is transferred to the flipflop FF 20  at the end of the clock period CLK 12  before the latch of the calculated term “(a 0 +a 1 )×D 3 ”. 
     Clock Period CLK 13   
     During the following clock period CLK 13 , as shown in  FIG. 6 , the rearrangement circuit  12  outputs the pixel data f 0  and f 7  as the pixel data m 5  and m 6 , respectively, in response to the control signal S 1 , which is developed to indicate the rearrangement circuit  12  to execute a procedure defined for the clock period CLK 13 . The adder  21   3  calculates the sum of the pixel data m 5  and m 6 , that is, the sum a 0  (=f 0 +f 7 ) described in the equation (9). The calculated sum a 3  is stored into the flipflop FF 11  at the end of the clock period CLK 13 . 
     In the mean time, the controller unit  30  sets the coefficient γ to D 3 , and the multiplier  23   3  receives the sum a 3  (=f 3 +f 4 ) from the flipflop FF 11 . This allows the multiplier  23   3  to calculate the product of the sum a 3  and the coefficient D 3  as described in the equation (10). The calculated product “a 3 ×D 3 ” is set to the flipflop FF 16  at the end of the clock period CLK 13 . 
     In addition, the flipflops FF 14 , FF 15 , and FF 17  are reset to zero at the end of the clock period CLK 13 . 
     Furthermore, the adder/subtractor unit  25  calculates the sum of the outputs of the flipflops FF 14  to FF 17  and the selector  25   5 . The fact that the selector  25   5  selects the output of the flipflop FF 19 , and the flipflops FF 14 , FF 15 , and FF 17  are reset to zero results in that the adder/subtractor unit  25  calculates the sum of the product “(a 0 +a 1 )×D 3 ” received from the flipflop FF 19  and the product “a 2 ×D 3 ” received from the flipflop FF 16 , that is, the term “(a 0 +a 1 +a 2 )×D 3 ”. The calculated term “(a 0 +a 1 +a 2 )×D 3 ” is latched by the flipflop FF 19  at the end of the CLK 13 . 
     Furthermore, the term “(a 0 +a 1 )×D 3 ”, which has been latched by the flipflop FF 19 , is transferred to the flipflop FF 20  at the end of the clock period CLK 13  before the latch of the calculated term “(a 0 +a 1 +a 2 )×D 3 ”. 
     Clock Period CLK 14   
     During the following clock period CLK 14 , the rearrangement circuit  12  outputs the pixel data f 1  and f 6  as the pixel data m 5  and m 6 , respectively, in response to the control signal S 1 , which is developed to indicate the rearrangement circuit  12  to execute a procedure defined for the clock period CLK 14 . The adder  21   3  calculates the sum of the pixel data m 5  and m 6 , that is, the sum −a 1  (=−(f 1 +f 6 )) described in the equation (9). The calculated sum −a 1  is stored into the flipflop FF 11  at the end of the clock period CLK 14 . 
     In the mean time, the controller unit  30  sets the coefficient γ to D 3 , and the multiplier  23   3  receives the sum a 0  (=f 0 +f 7 ) from the flipflop FF 11 . This allows the multiplier  23   3  to calculate the product of the sum a 0  and the coefficient D 3  as described in the equation (10). The calculated product “a 0 ×D 3 ” is stored into the flipflop FF 16  at the end of the clock period CLK 14 . 
     In addition, the flipflops FF 14 , FF 15 , and FF 17  are reset to zero at the end of the clock period CLK 14 . 
     Furthermore, the adder/subtractor unit  25  calculates the sum of the outputs of the flipflops FF 14  to FF 17  and the selector  25   5 . The fact that the selector  25   5  selects the output of the flipflop FF 19 , and the flipflops FF 14 , FF 15 , and FF 17  are reset to zero results in that the adder/subtractor unit  25  calculates the sum of the product “(a 0 +a 1 +a 2 )×D 3 ” received from the flipflop FF 19  and the product “a 3 ×D 3 ” received from the flipflop FF 16 , that is, the term “(a 0 +a 1 +a 2 +a 3 )×D 3 ”. The calculated term “(a 0 +a 1 +a 2 +a 3 )×D 3 ” is latched by the flipflop FF 19  at the end of the CLK 14 . 
     Furthermore, the term “(a 0 +a 1 +a 2 )×D 3 ”, which has been latched by the flipflop FF 19 , is transferred to the flipflop FF 20  at the end of the clock period CLK 14  before the latch of the calculated term “(a 0 +a 1 +a 2 +a 3 )×D 3 ”. 
     Clock Period CLK 15   
     During the following clock period CLK 15 , the rearrangement circuit  12  outputs the pixel data f 2  and f 5  as the pixel data m 5  and m 6 , respectively, in response to the control signal S 1 , which is developed to indicate the rearrangement circuit  12  to execute a procedure defined for the clock period CLK 15 . The adder  21   3  calculates the sum of the pixel data m 5  and m 6 , that is, the sum −a 2  (=−(f 2 +f 5 )) described in the equation (9). The calculated sum −a 2  is stored into the flipflop FF 11  at the end of the clock period CLK 15 . 
     In the mean time, the controller unit  30  sets the coefficient γ to D 3 , and the multiplier  23   3  receives the sum −a 1  (=−(f 1 +f 6 )) from the flipflop FF 11 . This allows the multiplier  23   3  to calculate the product of the sum −a 1  and the coefficient D 3  as described in the equation (10). The calculated product “−a 1 ×D 3 ” is stored into the flipflop FF 16  at the end of the clock period CLK 15 . 
     In addition, the flipflops FF 14 , FF 15 , and FF 17  are reset to zero at the end of the clock period CLK 15 . 
     Furthermore, the adder/subtractor unit  25  calculates the sum of the outputs of the flipflops FF 14  to FF 17  and the selector  25   5 . The fact that the selector  25   5  is controlled to output zero, and the flipflops FF 14 , FF 15 , and FF 17  are reset to zero results in that the adder/subtractor unit  25  outputs the product “a 0 ×D 3 ”, which has been stored in the flipflop FF 16 . The calculated product “a 0 ×D 3 ” is latched by the flipflop FF 19  at the end of the CLK 15 . 
     Furthermore, the term “(a 0 +a 1 +a 2 +a 3 )×D 3 ”, which has been latched by the flipflop FF 19 , is transferred to the flipflop FF 20  at the end of the clock period CLK 15  before the latch of the calculated produce “a 0 ×D 3 ”. This allows the output of the encoded pixel data F 0  (=(a 0 +a 1 +a 2 +a 3 )×D 3 ) from the flipflop FF 20  at the following clock period CLK 16 . 
     Clock Period CLK 16   
     During the following clock period CLK 16 , the rearrangement circuit  12  outputs the pixel data f 3  and f 4  as the pixel data m 5  and m 6 , respectively, in response to the control signal S 1 , which is developed to indicate the rearrangement circuit  12  to execute a procedure defined for the clock period CLK 16 . The adder  21   3  calculates the sum of the pixel data m 5  and m 6 , that is, the sum a 3  (=f 3 +f 4 ) described in the equation (9). The calculated sum a 3  is stored into the flipflop FF 11  at the end of the clock period CLK 16 . 
     In the mean time, the controller unit  30  sets the coefficient γ to D 3 , and the multiplier  23   3  receives the sum −a 2  (=−(f 2 +f 5 )) from the flipflop FF 11 . This allows the multiplier  23   3  to calculate the product of the sum −a 2  and the coefficient D 3  as described in the equation (10). The calculated product “−a 2 ×D 3 ” is stored into the flipflop FF 16  at the end of the clock period CLK 16 . 
     In addition, the flipflops FF 14 , FF 15 , and FF 17  are reset to zero at the end of the clock period CLK 16 . 
     Furthermore, the adder/subtractor unit  25  calculates the sum of the outputs of the flipflops FF 14  to FF 17  and the selector  25   5 . The fact that the selector  25   5  selects the output of the flipflop FF 19 , and the flipflops FF 14 , FF 15 , and FF 17  are reset to zero results in that the adder/subtractor unit  25  calculates the sum of the product “a 0 ×D 3 ” received from the flip-flop F 19  and the product “−a 1 ×D 3 ” received from the flipflop FF 16 , that is, the term “(a 0 −a 1 )×D 3 ”. The calculated term “(a 0 −a 1 )×D 3 ” is latched by the flipflop FF 19  at the end of the CLK 16 . 
     Furthermore, the term “a 0 ×D 3 ”, which has been latched by the flipflop FF 19 , is transferred to the flipflop FF 20  at the end of the clock period CLK 16  before the latch of the calculated term “(a 0 −a 1 )×D 3 ”. 
     Clock Period CLK 17   
     During the following clock period CLK 17 , the rearrangement circuit  12  outputs the pixel data f 0  and f 7  as the pixel data m 1  and m 2 , the pixel data f 1  and f 6  as the pixel data m 3  and m 4 , respectively, in response to the control signal S 1 , which is developed to indicate the rearrangement circuit  12  to execute a procedure defined for the clock period CLK 17 . The adder  21   1  calculates the sum of the pixel data m 1  and m 2 , that is the sum a 0  (=f 0 +f 7 ) described in the equation (9). The calculated sum a 0  is stored in the flipflop FF 9  at the end of the clock period CLK 17 . In the meantime, the adder  21   2  calculates the sum of the pixel data m 3  and m 4 , that is, the sum a 1  (=f 1 +f 6 ) described in the equation (9). The calculated sum a 1  is stored into the flip-flop FF 10  at the end of the clock period CLK 17 . 
     In the mean time, the controller unit  30  sets the coefficient γ to D 3 , and the multiplier  23   3  receives the sum a 3  (=f 3 +f 4 ) from the flipflop FF 11 . This allows the multiplier  23   3  to calculate the product of the sum a 2  and the coefficient D 3  as described in the equation (10). The calculated product “a 3 ×D 3 ” is stored into the flipflop FF 16  at the end of the clock period CLK 17 . 
     In addition, the flipflops FF 14 , FF 15 , and FF 17  are reset to zero at the end of the clock period CLK 17 . 
     Furthermore, the adder/subtractor unit  25  calculates the sum of the outputs of the flipflops FF 14  to FF 17  and the selector  25   5 . The fact that the selector  25   5  selects the output of the flipflop FF 19 , and the flipflops FF 14 , FF 15 , and FF 17  are reset to zero, results in that the adder/subtractor unit  25  calculates the sum of the term “(a 0 −a 1 )×D 3 ” received from the flipflop F 19  and the product “−a 2 ×D 3 ” received from the flipflop FF 16 , that is, the term “(a 0 −a 1 −a 2 )×D 3 ”. The calculated term “(a 0 −a 1 −a 2 )×D 3 ” is latched by the flipflop FF 19  at the end of the CLK 17 . 
     Furthermore, the term “(a 0 −a 1 )×D 3 ”, which has been latched by the flipflop FF 19 , is transferred to the flipflop FF 20  at the end of the clock period CLK 17  before the latch of the calculated term “(a 0 −a 1 −a 2 )×D 3 ”. 
     Clock Period CLK 18   
     During the following clock period CLK 18 , the rearrangement circuit  12  outputs the pixel data f 3  and f 4  as the pixel data m 1  and m 2 , the pixel data f 2  and f 5  as the pixel data m 3  and m 4 , respectively, in response to the control signal S 1 , which is developed to indicate the rearrangement circuit  12  to execute a procedure defined for the clock period CLK 18 . The adder  21   1  calculates the sum of the pixel data m 1  and m 2 , that is the sum −a 3  (=−(f 3 +f 4 )) described in the equation (9). The calculated sum −a 3  is stored in the flipflop FF 9  at the end of the clock period CLK 18 . In the meantime, the adder  21   2  calculates the sum of the pixel data m 3  and m 4 , that is, the sum −a 2  (=−(f 2 +f 5 )) described in the equation (9). The calculated sum −a 3  is stored into the flipflop FF 10  at the end of the clock period CLK 18 . 
     In the mean time, the controller unit  30  sets the coefficient α to D 5 , and the multiplier  23   1  receives the sum a 0  (=f 0 +f 7 ) from the flipflop FF 9 . This allows the multiplier  23   1  to calculate the product of the sum a 0  and the coefficient D 5  as described in the equation (10). The calculated product “a 0 ×D 5 ” is stored into the flipflop FF 14  at the end of the clock period CLK 18 . 
     Correspondingly, the controller unit  30  sets the coefficient β to D 1 , and the multiplier  23   2  receives the sum a 1  (=f 1 +f 6 ) from the flipflop FF 10 . This allows the multiplier  23   2  to calculate the product of the sum a 1  and the coefficient D 1  as described in the equation (10). The calculated product “a 1 ×D 1 ” is stored into the flipflop FF 15  at the end of the clock period CLK 18 . 
     In addition, the flipflops FF 16 , and FF 17  are reset to zero at the end of the clock period CLK 18 . 
     Furthermore, the adder/subtractor unit  25  calculates the sum of the outputs of the flipflops FF 14  to FF 17  and the selector  25   5 . The fact that the selector  25   5  selects the output of the flipflop FF 19 , and the flipflops FF 14 , FF 15 , and FF 17  are reset to zero, results in that the adder/subtractor unit  25  calculates the sum of the term “(a 0 −a 1 −a 2 )×D 3 ” received from the flipflop F 19  and the product “a 3 ×D 3 ” received from the flipflop FF 16 , that is, the term “(a 0 −a 1 −a 2 +a 3 )×D 3 ”. The calculated term “(a 0 −a 1 −a 2 +a 3 )×D 3 ” is latched by the flip-flop FF 19  at the end of the CLK 18 . 
     Furthermore, the term “(a 0 −a 1 −a 2 )×D 3 ”, which has been latched by the flipflop FF 19 , is transferred to the flipflop FF 20  at the end of the clock period CLK 18  before the latch of the calculated term “(a 0 −a 1 −a 2 +a 3 )×D 3 ”. 
     Clock Period CLK 19   
     During the following clock period CLK 19 , the rearrangement circuit  12  outputs the pixel data f 1  and f 6  as the pixel data m 1  and m 2 , the pixel data f 0  and f 7  as the pixel data m 3  and m 4 , respectively, in response to the control signal S 1 , which is developed to indicate the rearrangement circuit  12  to execute a procedure defined for the clock period CLK 19 . The adder  21   1  calculates the sum of the pixel data m 1  and m 2 , that is the sum −a 1  (=−(f 1 +f 6 )) described in the equation (9). The calculated sum −a 1  is stored into the flipflop FF 9  at the end of the clock period CLK 19 . In the meantime, the adder  21   2  calculates the sum of the pixel data m 3  and m 4 , that is, the sum a 0  (=f 0 +f 7 ) described in the equation (9). The calculated sum a 0  is stored into the flipflop FF 10  at the end of the clock period CLK 19 . 
     In the mean time, the controller unit  30  sets the coefficient α to D 5 , and the multiplier  23   1  receives the sum −a 3  (=−(f 3 +f 4 )) from the flipflop FF 9 . This allows the multiplier  23   1  to calculate the product of the sum −a 3  and the coefficient D 5  as described in the equation (10). The calculated product “−a 3 ×D 5 ” is stored into the flipflop FF 14  at the end of the clock period CLK 19 . 
     Correspondingly, the controller unit  30  sets the coefficient β to D 1 , and the multiplier  23   2  receives the sum −a 2  (=−(f 2 +f 5 ) from the flipflop FF 10 . This allows the multiplier  23   2  to calculate the product of the sum −a 2  and the coefficient D 1  as described in the equation (10). The calculated product “−a 2 ×D 1 ” is stored into the flipflop FF 15  at the end of the clock period CLK 19 . 
     In addition, the flipflops FF 16 , and FF 17  are reset to zero at the end of the clock period CLK 19 . 
     Furthermore, the adder/subtractor unit  25  calculates the sum of the outputs of the flipflops FF 14  to FF 17  and the selector  25   5 . The selector  25   5  is controlled to develop zero on the output by the controller unit  30 . The fact that the selector  25   5  outputs zero, and the flip-flops FF 16 , and FF 17  are reset to zero, results in that the adder/subtractor unit  25  calculates the sum of the product “a 0 ×D 5 ” received from the flipflop FF 14  and the product “a 1 ×D 1 ” received from the flipflop FF 15 , that is, the term “a 0 ×D 4 +a 1 ×D 1 ”. The calculated term “a 0 ×D 4 +a 1 ×D 1 ” is latched by the flipflop FF 19  at the end of the CLK 19 . 
     Furthermore, the term “(a 0 −a 1 −a 2 +a 3 )×D 3 ”, which has been latched by the flip-flop FF 19 , is transferred to the flipflop FF 20  at the end of the clock period CLK 19  before the latch of the calculated term “a 0 ×D 4 +a 1 ×D 1 ”. This allows the output of the encoded pixel data F 4  (=(a 0 −a 1 −a 2 +a 3 )×D 3 ) from the flipflop FF 20  at the following clock period CLK 20 . 
     Clock Period CLK 20   
     During the following clock period CLK 20 , the rearrangement circuit  12  outputs the pixel data f 2  and f 5  as the pixel data m 1  and m 2 , and the pixel data f 3  and f 4  as the pixel data m 3  and m 4 , respectively, in response to the control signal S 1 , which is developed to indicate the rearrangement circuit  12  to execute a procedure defined for the clock period CLK 20 . The adder  21   1  calculates the sum of the pixel data m 1  and m 2 , that is the sum a 2  (=f 2 +f 5 ) described in the equation (9). The calculated sum a 2  is stored into the flipflop FF 9  at the end of the clock period CLK 20 . In the meantime, the adder  21   2  calculates the sum of the pixel data m 3  and m 4 , that is, the sum −a 3  (=−(f 3 +f 4 ) described in the equation (9). The calculated sum −a 3  is stored into the flipflop FF 10  at the end of the clock period CLK 20 . 
     In the mean time, the controller unit  30  sets the coefficient α to D 5 , and the multiplier  23   1  receives the sum −a 1  (=−(f 1 +f 6 )) from the flipflop FF 9 . This allows the multiplier  23   1  to calculate the product of the sum −a 1  and the coefficient D 5  as described in the equation (10). The calculated product “−a 1 ×D 5 ” is stored into the flipflop FF 14  at the end of the clock period CLK 20 . 
     Correspondingly, the controller unit  30  sets the coefficient β to D 1 , and the multiplier  23   2  receives the sum a 0  (=f 0 +f 7 ) from the flipflop FF 10 . This allows the multiplier  23   2  to calculate the product of the sum a 0  and the coefficient D 1  as described in the equation (10). The calculated product “a 0 ×D 1 ” is stored into the flipflop FF 15  at the end of the clock period CLK 20 . 
     In addition, the flipflops FF 16 , and FF 17  are reset to zero at the end of the clock period CLK 20 . 
     Furthermore, the adder/subtractor unit  25  calculates the sum of the outputs of the flipflops FF 14  to FF 17  and the selector  25   5 . The fact that the selector  25   5  selects the output of the flipflop FF 19 , and the flipflops FF 16  and FF 17  are reset to zero, results in that the adder/subtractor unit  25  calculates the sum of the term “a 0 ×D 5 +a 1 ×D 1 ” received from the flipflop FF 19 , the product “−a 3 ×D 5 ” received from the flipflop FF 14  and the product “−a 2 ×D 1 ” received from the flipflop FF 15 , that is, the term “(a 0 −a 3 )×D 5 +(a 1 −a 2 )×D 1 ”. The calculated term “(a 0 −a 3 )×D 5 +(a 1 −a 2 )×D 1 ” is latched by the flipflop FF 19  at the end of the CLK 20 . 
     Furthermore, the term “a 0 ×D 5 +a 1 ×D 1 ”, which has been latched by the flipflop FF 19 , is transferred to the flipflop FF 20  at the end of the clock period CLK 20  before the latch of the calculated term “(a 0 −a 3 )×D 5 +(a 1 −a 2 )×D 1 ”. 
     Clock Period CLK 21   
     During the following clock period CLK 21 , as shown in  FIG. 7 , the rearrangement circuit  12  outputs the pixel data f 0  and f 7  as the pixel data m 1  and m 2 , the pixel data f 1  and f 6  as the pixel data m 3  and m 4 , the pixel data f 2  and f 5  as the pixel data m 5  and m 6 , and the pixel data f 3  and f 4  as the pixel data m 7  and m 8  respectively, in response to the control signal S 1 , which is developed to indicate the rearrangement circuit  12  to execute a procedure defined for the clock period CLK 21 . 
     The adder  21   1  calculates the sum of the pixel data m 1  and m 2 , that is the sum a 4  (=f 0 −f 7 ) described in the equation (9). The calculated sum a 4  is stored into the flipflop FF 9  at the end of the clock period CLK 21 . In the meantime, the adder  21   2  calculates the sum of the pixel data m 3  and m 4 , that is, the sum a 5  (=f 1 −f 6 ) described in the equation (9). The calculated sum a 5  is stored into the flipflop FF 10  at the end of the clock period CLK 21 . Furthermore, the adder  21   3  calculates the sum of the pixel data m 5  and m 6 , that is, the sum a 6  (=f 2 −f 5 ) described in the equation (9). The calculated sum a 6  is stored into the flipflop FF 11  at the end of the clock period CLK 21 . In addition, the adder  21   4  calculates the sum of the pixel data m 7  and m 8 , that is, the sum a 7  (=f 3 −f 4 ) described in the equation (9). The calculated sum a 7  is stored into the flipflop FF 12  at the end of the clock period CLK 21 . 
     In the mean time, the controller unit  30  sets the coefficient α to D 5 , and the multiplier  23   1  receives the sum a 2  (=f 2 +f 5 ) from the flipflop FF 9 . This allows the multiplier  23   1  to calculate the product of the sum a 2  and the coefficient D 5  as described in the equation (10). The calculated product “a 2 ×D 5 ” is stored into the flipflop FF 14  at the end of the clock period CLK 21 . 
     Correspondingly, the controller unit  30  sets the coefficient β to D 1 , and the multiplier  23   2  receives the sum −a 3  (=f 0 +f 7 ) from the flipflop FF 10 . This allows the multiplier  23   2  to calculate the product of the sum −a 3  and the coefficient D 1  as described in the equation (10). The calculated product “−a 3 ×D 1 ” is stored into the flipflop FF 15  at the end of the clock period CLK 21 . 
     In addition, the flipflops FF 16 , and FF 17  are reset to zero at the end of the clock period CLK 21 . 
     Furthermore, the adder/subtractor unit  25  calculates the sum of the outputs of the flipflops FF 14  to FF 17  and the selector  25   5 . The selector  25   5  is controlled to develop zero on the output by the controller unit  30 . The fact that the selector  25   5  outputs zero and the flip-flops FF 16  and FF 17  are reset to zero, results in that the adder/subtractor unit  25  calculates the sum of the product “−a 1 ×D 5 ” received from the flipflop FF 14  and the product “a 0 ×D 1 ” received from the flipflop FF 15 , that is, the term “−a 1 ×D 5 +a 0 ×D 1 ”. The calculated term “−a 1 ×D 5 +a 0 ×D 1 ” is latched by the flipflop FF 19  at the end of the CLK 21 . 
     Furthermore, the term “(a 0 −a 3 )×D 5 +(a 1 −a 2 )×D 1 ”, which has been stored by the flipflop FF 19 , is transferred to the flip-flop FF 20  at the end of the clock period CLK 21  before the latch of the calculated term “−a 1 ×D 5 +a 0 ×D 1 ”. This allows the output of the encoded pixel data F 2  (=(a 0 −a 3 )×D 5 +(a 1 −a 2 )×D 1 ) from the flipflop FF 20  at the following clock period CLK 22 . 
     Clock Period CLK 22   
     During the following clock period CLK 22 , the rearrangement circuit  12  outputs the pixel data f 2  and f 5  as the pixel data m 1  and m 2 , the pixel data f 0  and f 7  as the pixel data m 3  and m 4 , the pixel data f 3  and f 4  as the pixel data m 5  and m 6 , and the pixel data f 1  and f 6  as the pixel data m 7  and m 8  respectively, in response to the control signal S 1 , which is developed to indicate the rearrangement circuit  12  to execute a procedure defined for the clock period CLK 22 . 
     The adder  21   1  calculates the sum of the pixel data m 1  and m 2 , that is the sum −a 6  (=−(f 2 −f 5 )) described in the equation (9). The calculated sum −a 6  is stored into the flip-flop FF 9  at the end of the clock period CLK 22 . In the meantime, the adder  21   2  calculates the sum of the pixel data m 3  and m 4 , that is, the sum a 4  (=f 0 −f 7 ) described in the equation (9). The calculated sum a 4  is stored into the flipflop FF 10  at the end of the clock period CLK 22 . Furthermore, the adder  21   3  calculates the sum of the pixel data m 5  and m 6 , that is, the sum −a 7  (=−(f 3 −f 4 )) described in the equation (9). The calculated sum −a 7  is stored into the flipflop FF 11  at the end of the clock period CLK 22 . In addition, the adder  21   4  calculates the sum of the pixel data m 7  and m 8 , that is, the sum −a 5  (=−(f 1 −f 6 ) described in the equation (9). The calculated sum −a 5  is stored into the flipflop FF 12  at the end of the clock period CLK 22 . 
     In the mean time, the controller unit  30  sets the coefficient α to D 6 , and the multiplier  23   1  receives the sum a 4  (=f 0 −f 7 ) from the flipflop FF 9 . This allows the multiplier  23   1  to calculate the product of the sum a 4  and the coefficient D 6  as described in the equation (10). The calculated product “a 4 ×D 6 ” is stored into the flipflop FF 14  at the end of the clock period CLK 22 . 
     Correspondingly, the controller unit  30  sets the coefficient β to D 4 , and the multiplier  23   2  receives the sum a 4  (=f 0 −f 7 ) from the flipflop FF 10 . This allows the multiplier  23   2  to calculate the product of the sum a 4  and the coefficient D 4  as described in the equation (10). The calculated product “a 4 ×D 4 ” is stored into the flipflop FF 15  at the end of the clock period CLK 22 . 
     Correspondingly, the controller unit  30  sets the coefficient γ to D 2 , and the multiplier  23   3  receives the sum a 6  (=f 2 −f 5 ) from the flipflop FF 11 . This allows the multiplier  23   3  to calculate the product of the sum a 6  and the coefficient D 2  as described in the equation (10). The calculated product “a 6 ×D 2 ” is stored into the flipflop FF 16  at the end of the clock period CLK 22 . 
     Correspondingly, the controller unit  30  set the coefficient δ to D 0 , and the multiplier  23   4  receives the sum a 7  (=f 3 −f 4 ) from the flip-flop FF 12 . This allows the multiplier  23   4  to calculate the product of the sum a 7  and the coefficient D 0  as described in the equation (10). The calculated product “a 7 ×D 0 ” is stored into the flip-flop FF 17  at the end of the clock period CLK 22 . 
     Furthermore, the adder/subtractor unit  25  calculates the sum of the outputs of the flipflops FF 14  to FF 17  and the selector  25   5 . The selector  25   5  is controlled to select the output of the flipflop FF 19  by the controller unit  30 . The fact that the selector  25   5  selects the output of the flipflop FF 19 , and the flipflops FF 16  and FF 17  are reset to zero, results in that the adder/subtractor unit  25  calculates the sum of the term “−a 1 ×D 5 +a 0 ×D 1 ” received from the flipflop FF 19 , the product “a 2 ×D 5 ” received from the flipflop FF 14 , and the product “−a 3 ×D 1 ” received from the flipflop FF 15 , that is, the term “(−a 1 +a 2 )×D 5 +(a 0 −a 3 )×D 1 ”. The calculated term “(−a 1 +a 2 )×D 5 +(a 0 −a 3 )×D 1 ” is latched by the flipflop FF 19  at the end of the CLK 22 . 
     Furthermore, the term “−a 1 ×D 5 +a 0 ×D 1 ”, which has been stored by the flipflop FF 19 , is transferred to the flipflop FF 20  at the end of the clock period CLK 22  before the latch of the calculated term “(−a 1 +a 2 )×D 5 +(a 0 −a 3 )×D 1 ”. 
     Clock Period CLK 23   
     During the following clock period CLK 23 , the rearrangement circuit  12  outputs the pixel data f 1  and f 6  as the pixel data m 1  and m 2 , the pixel data f 3  and f 4  as the pixel data m 3  and m 4 , the pixel data f 0  and f 7  as the pixel data m 5  and m 6 , and the pixel data f 2  and f 5  as the pixel data m 7  and m 8  respectively, in response to the control signal S 1 , which is developed to indicate the rearrangement circuit  12  to execute a procedure defined for the clock period CLK 23 . 
     The adder  21   1  calculates the sum of the pixel data m 1  and m 2 , that is the sum −a 5  (=−(f 1 −f 6 )) described in the equation (9). The calculated sum −a 5  is stored into the flip-flop FF 9  at the end of the clock period CLK 23 . In the meantime, the adder  21   2  calculates the sum of the pixel data m 3  and m 4 , that is, the sum a 7  (=f 3 −f 4 ) described in the equation (9). The calculated sum a 7  is stored into the flipflop FF 10  at the end of the clock period CLK 23 . Furthermore, the adder  21   3  calculates the sum of the pixel data m 5  and m 6 , that is, the sum a 4  (=f 0 −f 7 ) described in the equation (9). The calculated sum a 4  is stored into the flipflop FF 11  at the end of the clock period CLK 23 . In addition, the adder  21   4  calculates the sum of the pixel data m 7  and m 8 , that is, the sum a 6  (=f 2 −f 5 ) described in the equation (9). The calculated sum a 6  is stored into the flipflop FF 12  at the end of the clock period CLK 23 . 
     In the mean time, the controller unit  30  sets the coefficient α to D 6 , and the multiplier  23   1  receives the sum −a 6  (=−(f 2 −f 5 )) from the flipflop FF 9 . This allows the multiplier  23   1  to calculate the product of the sum −a 6  and the coefficient D 6  as described in the equation (10). The calculated product “−a 6 ×D 6 ” is stored into the flipflop FF 14  at the end of the clock period CLK 23 . 
     Correspondingly, the controller unit  30  sets the coefficient β to D 4 , and the multiplier  23   2  receives the sum a 0  (=f 0 −f 7 ) from the flipflop FF 10 . This allows the multiplier  23   2  to calculate the product of the sum a 0  and the coefficient D 4  as described in the equation (10). The calculated product “a 0 ×D 4 ” is stored into the flipflop FF 15  at the end of the clock period CLK 23 . 
     Correspondingly, the controller unit  30  sets the coefficient γ to D 2 , and the multiplier  23   3  receives the sum −a 7  (=−(f 3 −f 4 )) from the flipflop FF 11 . This allows the multiplier  23   3  to calculate the product of the sum −a 7  and the coefficient D 2  as described in the equation (10). The calculated product “−a 7 ×D 2 ” is stored into the flipflop FF 16  at the end of the clock period CLK 23 . 
     Correspondingly, the controller unit  30  set the coefficient δ to D 0 , and the multiplier  23   4  receives the sum −a 5  (=−(f 1 −f 6 )) from the flipflop FF 12 . This allows the multiplier  23   4  to calculate the product of the sum −a 5  and the coefficient D 0  as described in the equation (10). The calculated product “−a 5 ×D 0 ” is stored into the flipflop FF 17  at the end of the clock period CLK 23 . 
     Furthermore, the adder/subtractor unit  25  calculates the sum of the outputs of the flipflops FF 14  to FF 17  and the selector  25   5 . The selector  25   5  is controlled to develop zero on the output by the controller unit  30 . This results in that the adder/subtractor unit  25  calculates the sum of the product “a 4 ×D 6 ” received from the flipflop FF 14 , the product “a 5 ×D 4 ” received from the flipflop FF 15 , the product “a 6 ×D 2 ” received from the flipflop FF 16 , and the product “a 7 ×D 0 ” received from the flipflop FF 17 , that is, the term “a 4 ×D 6 +a 5 ×D 4 +a 6 ×D 2 +a 7 ×D 0 ”. The calculated term “a 4 ×D 6 +a 5 ×D 4 +a 6 ×D 2 +a 7 ×D 0 ” is latched by the flipflop FF 19  at the end of the CLK 23 . 
     Furthermore, the term “(−a 1 +a 2 )×D 5 +(a 0 −a 3 )×D 1 ”, which has been stored by the flipflop FF 19 , is transferred to the flipflop FF 20  at the end of the clock period CLK 23  before the latch of the calculated term “a 4 ×D 6 +a 5 ×D 4 +a 6 ×D 2 +a 7 ×D 0 ”. This allows the output of the encoded pixel data F 6  (=(−a 1 +a 2 )×D 5 +(a 0 −a 3 )×D 1 ) from the flipflop FF 20  at the following clock period CLK 24 . 
     Clock Period CLK 24   
     During the following clock period CLK 24 , the rearrangement circuit  12  outputs the pixel data f 3  and f 4  as the pixel data m 1  and m 2 , the pixel data f 2  and f 5  as the pixel data m 3  and m 4 , the pixel data f 1  and f 6  as the pixel data m 5  and m 6 , and the pixel data f 0  and f 7  as the pixel data m 7  and m 8  respectively, in response to the control signal S 1 , which is developed to indicate the rearrangement circuit  12  to execute a procedure defined for the clock period CLK 24 . 
     The adder  21   1  calculates the sum of the pixel data m 1  and m 2 , that is the sum −a 7  (=−(f 3 −f 4 )) described in the equation (9). The calculated sum −a 7  is stored into the flip-flop FF 9  at the end of the clock period CLK 24 . In the meantime, the adder  21   2  calculates the sum of the pixel data m 3  and m 4 , that is, the sum a 6  (=f 2 −f 5 ) described in the equation (9). The calculated sum a 6  is stored into the flipflop FF 10  at the end of the clock period CLK 24 . Furthermore, the adder  21   3  calculates the sum of the pixel data m 5  and m 6 , that is, the sum −a 5  (=f 1 −f 6 ) described in the equation (9). The calculated sum −a 5  is stored into the flipflop FF 11  at the end of the clock period CLK 24 . In addition, the adder  21   4  calculates the sum of the pixel data m 7  and m 8 , that is, the sum a 4  (=f 0 −f 7 ) described in the equation (9). The calculated sum a 4  is stored into the flipflop FF 12  at the end of the clock period CLK 24 . 
     In the mean time, the controller unit  30  sets the coefficient α to D 6 , and the multiplier  23   1  receives the sum −a 5  (=−(f 1 −f 6 )) from the flipflop FF 9 . This allows the multiplier  23   1  to calculate the product of the sum −a 5  and the coefficient D 6  as described in the equation (10). The calculated product “−a 5 ×D 6 ” is stored into the flipflop FF 14  at the end of the clock period CLK 24 . 
     Correspondingly, the controller unit  30  sets the coefficient β to D 4 , and the multiplier  23   2  receives the sum a 7  (=f 3 −f 4 ) from the flipflop FF 10 . This allows the multiplier  23   2  to calculate the product of the sum a 7  and the coefficient D 4  as described in the equation (10). The calculated product “a 7 ×D 4 ” is stored into the flipflop FF 15  at the end of the clock period CLK 24 . 
     Correspondingly, the controller unit  30  sets the coefficient γ to D 2 , and the multiplier  23   3  receives the sum a 4  (=f 0 −f 7 ) from the flipflop FF 11 . This allows the multiplier  23   3  to calculate the product of the sum a 4  and the coefficient D 2  as described in the equation (10). The calculated product “a 4 ×D 2 ” is stored into the flipflop FF 16  at the end of the clock period CLK 24 . 
     Correspondingly, the controller unit  30  set the coefficient δ to D 0 , and the multiplier  23   4  receives the sum a 6  (=f 2 −f 5 ) from the flip-flop FF 12 . This allows the multiplier  23   4  to calculate the product of the sum a 6  and the coefficient D 0  as described in the equation (10). The calculated product “a 6 ×D 0 ” is stored into the flip-flop FF 17  at the end of the clock period CLK 24 . 
     Furthermore, the adder/subtractor unit  25  calculates the sum of the outputs of the flipflops FF 14  to FF 17  and the selector  25   5 . The selector  25   5  is controlled to develop zero on the output by the controller unit  30 . This results in that the adder/subtractor unit  25  calculates the sum of the product “−a 6 ×D 6 ” received from the flipflop FF 14 , the product “−a 4 ×D 4 ” received from the flipflop FF 15 , the product “−a 7 ×D 2 ” received from the flipflop FF 16 , and the product “−a 5 ×D 0 ” received from the flipflop FF 17 , that is, the term “−a 6 ×D 6 +a 4 ×D 4 −a 7 ×D 2 −a 5 ×D 0 ”. The calculated term “−a 6 ×D 6 +a 4 ×D 4 −a 7 ×D 2 −a 5 ×D 0 ” is latched by the flipflop FF 19  at the end of the CLK 24 . 
     Furthermore, the term “a 4 ×D 6 +a 5 ×D 4 +a 6 ×D 2 +a 7 ×D 0 ”, which has been stored by the flipflop FF 19 , is transferred to the flip-flop FF 20  at the end of the clock period CLK 24  before the latch of the term “−a 6 ×D 6 +a 4 ×D 4 −a 7 ×D 2 −a 5 ×D 0 ”. This allows the output of the encoded pixel data F 1  (=a 4 ×D 6 +a 5 ×D 4 +a 6 ×D 2 +a 7 ×D 0 ) from the flipflop FF 20  at the following clock period CLK 25 . 
     Clock Period CLK 25   
     At the following clock period CLK 25 , pixel data of a next pixel of interest are provided for the flipflops FF 0  to FF 7 . The procedure for encoding the pixel data of the next pixel of interest is identical to that of the pixel data of the current pixel of interest. Therefore, detailed explanation is not given, hereinafter, for encoding the pixel data of the next pixel of interest. 
     During the clock period CLK 25 , the rearrangement circuit  12  outputs the pixel data m 1  to m 8  for the next pixel of interest in response to the control signal S 1  received from the controller unit  30 . 
     In the mean time, the controller unit  30  sets the coefficient α to D 6 , and the multiplier  23   1  receives the sum −a 7  (=−(f 3 −f 4 )) from the flipflop FF 9 . This allows the multiplier  23   1  to calculate the product of the sum −a 7  and the coefficient D 6  as described in the equation (10). The calculated product “−a 7 ×D 6 ” is stored into the flipflop FF 14  at the end of the clock period CLK 25 . 
     Correspondingly, the controller unit  30  sets the coefficient β to D 4 , and the multiplier  23   2  receives the sum a 6  (=f 2 −f 5 ) from the flipflop FF 10 . This allows the multiplier  23   2  to calculate the product of the sum a 6  and the coefficient D 4  as described in the equation (10). The calculated product “a 6 ×D 4 ” is stored into the flipflop FF 15  at the end of the clock period CLK 25 . 
     Correspondingly, the controller unit  30  sets the coefficient γ to D 2 , and the multiplier  23   3  receives the sum −a 5  (=f 1 −f 6 ) from the flipflop FF 11 . This allows the multiplier  23   3  to calculate the product of the sum −a 5  and the coefficient D 2  as described in the equation (10). The calculated product “−a 5 ×D 2 ” is stored into the flipflop FF 16  at the end of the clock period CLK 25 . 
     Correspondingly, the controller unit  30  set the coefficient δ to D 0 , and the multiplier  23   4  receives the sum a 4  (=f 0 −f 7 ) from the flip-flop FF 12 . This allows the multiplier  23   4  to calculate the product of the sum a 4  and the coefficient D 0  as described in the equation (10). The calculated product “a 4 ×D 0 ” is stored into the flip-flop FF 17  at the end of the clock period CLK 25 . 
     Furthermore, the adder/subtractor unit  25  calculates the sum of the outputs of the flipflops FF 14  to FF 17  and the selector  25   5 . The selector  25   5  is controlled to develop zero on the output by the controller unit  30 . This results in that the adder/subtractor unit  25  calculates the sum of the product “−a 5 ×D 6 ” received from the flipflop FF 14 , the product “−a 7 ×D 4 ” received from the flipflop FF 15 , the product “a 4 ×D 2 ” received from the flipflop FF 16 , and the product “a 6 ×D 0 ” received from the flipflop FF 17 , that is, the term “−a 5 ×D 6 −a 7 ×D 4 +a 4 ×D 2 +a 6 ×D 0 ”. The calculated term “−a 5 ×D 6 −a 7 ×D 4 +a 4 ×D 2 +a 6 ×D 0 ” is latched by the flipflop FF 19  at the end of the CLK 25 . 
     Furthermore, the term “−a 6 ×D 6 +a 4 ×D 4 −a 7 ×D 2 −a 5 ×D 0 ”, which has been stored by the flipflop FF 19 , is transferred to the flip-flop FF 20  at the end of the clock period CLK 25  before the latch of the term “−a 5 ×D 6 −a 7 ×D 4 +a 4 ×D 2 +a 6 ×D 0 ”. This allows the output of the encoded pixel data F 3  (=−a 6 ×D 6 +a 4 ×D 4 −a 7 ×D 2 −a 5 ×D 0 ) from the flipflop FF 20  at the following clock period CLK 26 . 
     Clock Period CLK 26   
     During the clock period CLK 25 , the rearrangement circuit  12  outputs the pixel data m 1  to m 8  for the next pixel of interest in response to the control signal S 1  received from the controller unit  30 . In the mean time, the multipliers  23   1  to  23   4  execute the operation for encoding the pixel data of the next pixel of interest. 
     Furthermore, the adder/subtractor unit  25  calculates the sum of the outputs of the flipflops FF 14  to FF 17  and the selector  25   5 . The selector  25   5  is controlled to develop zero on the output by the controller unit  30 . This results in that the adder/subtractor unit  25  calculates the sum of the product “−a 7 ×D 6 ” received from the flipflop FF 14 , the product “−a 6 ×D 4 ” received from the flipflop FF 15 , the product “−a 5 ×D 2 ” received from the flipflop FF 16 , and the product “a 4 ×D 0 ” received from the flipflop FF 17 , that is, the term “−a 7 ×D 6 −a 6 ×D 4 −a 5 ×D 2 +a 4 ×D 0 ”. The calculated term “−a 7 ×D 6 −a 6 ×D 4 −a 5 ×D 2 +a 4 ×D 0 ” is latched by the flipflop FF 19  at the end of the CLK 26 . 
     Furthermore, the term “−a 5 ×D 6 +a 7 ×D 4 +a 4 ×D 2 +a 6 ×D 0 ”, which has been stored by the flipflop FF 19 , is transferred to the flip-flop FF 20  at the end of the clock period CLK 26  before the latch of the term “−a 7 ×D 6 −a 6 ×D 4 −a 5 ×D 2 +a 4 ×D 0 ”. This allows the output of the encoded pixel data F 5  (=−a 5 ×D 6 +a 7 ×D 4 +a 4 ×D 2 +a 6 ×D 0 ) from the flipflop FF 20  at the following clock period CLK 27 . 
     Clock Period CLK 27   
     At the following clock period CLK 27 , the rearrangement circuit  12  outputs the pixel data m 1  to m 8  for the next pixel of interest in response to the control signal S 1  received from the controller unit  30 . In the mean time, the multipliers  23   1  to  23   4  execute the operation for encoding the pixel data of the next pixel of interest. Furthermore, the adder/subtractor unit  25  executes the operation for encoding the pixel data of the next pixel of interest. 
     During the clock period CLK 27 , the term “−a 7 ×D 6 +a 6 ×D 4 −a 5 ×D 2 +a 4 ×D 0 ”, which has been stored by the flipflop FF 19 , is transferred to the flipflop FF 20  at the end of the clock period CLK 27 . This allows the output of the encoded pixel data F 7  (=−a 7 ×D 6 +a 6 ×D 4 −a 5 ×D 2 +a 4 ×D 0 ) from the flipflop FF 20  at the following clock period CLK 28 . 
     (1-4) Decoding through the Discrete Cosine Transform 
       FIGS. 8 to 10  are timing diagram illustrating the procedure of decoding the pixel data through the discrete cosine transform. 
     Referring to the equations (13) and (14), the decoded pixel data f 0  is obtained from the following equation:
 
 f 0={( f 0 +f 4)/2}+{( f 0 −f 4)/2}.  (15)
 
The right hand first term of the equation (15) is obtained from the first row of the matrix of the equation (13), while the right hand second term of the equation (15) is obtained from the first row of the matrix of the equation (14).
 
     Correspondingly, the decoded pixel data f 1  to f 7  are obtained from the following equations:
 
 f 1={( f 1 +f 5)/2}+{( f 1 −f 5)/2}  (17)
 
 f 2={( f 2 +f 6)/2}+{( f 2 −f 6)/2},  (18)
 
 f 3={( f 3 +f 7)/2}+{( f 3 −f 7)/2},  (19)
 
 f 4={( f 0 +f 4)/2}−{( f 0 −f 4)/2},  (20)
 
 f 5={( f 1 +f 5)/2}−{( f 1 −f 5)/2},  (21)
 
 f 6={( f 2 +f 6)/2}−{( f 2 −f 6)/2}, and  (22)
 
 f 7={( f 3 +f 7)/2}+{( f 3 −f 7)/2}.  (23)
 
     Because the procedure of obtaining the decoded pixel data f 0  to f 7  are almost same, the explanation directed to only the decoded pixel data f 0  and f 4  will be given. 
     Clock Periods CLK 1  to CLK 9   
     The procedure begins with the input of the encoded pixel data F 0  to F 7 . As shown in  FIG. 8 , the encoded pixel data F 0  to F 7  are serially transferred to the flipflops FF 0  to FF 7 , respectively. 
     At the clock period CLK 9 , the controller unit  30  develops the control signal S 1  to indicate the rearrange circuit  12  to execute the procedure defined for the clock period CLK 9 . In response to the control signal S 1 , the rearrange circuit  12  outputs the pixel data F 2 , F 6 , F 0 , and F 4 , as the pixel data m 1 , m 3 , m 5  and m 6 , respectively. The pixel data m 2 , m 4 , m 7 , and m 8  are set to zero. 
     The adder  21   1  transfers the pixel data m 1  to the flipflop FF 9 , because the pixel data m 2  is set to zero. This results in that the pixel data F 2  is stored in the flipflop FF 9  at the end of the clock period CLK 9 . The pixel data F 2  is used as the element “a 2 ” in the equation (13). 
     Correspondingly, the adder  21   2  transfers the pixel data m 3  to the flipflop FF 10 . This results in that the pixel data F 6  is stored in the flipflop FF 10  at the end of the clock period CLK 9 . The pixel data F 6  is used as the element “a 1 ” in the equation (13). 
     Furthermore, the adder  21   3  calculates the sum of the pixel data m 5  and m 6 , that is, the sum of the pixel data F 0  and F 4 . This results in that the sum “F 0 +F 4 ” is stored in the flipflop FF 11  at the end of the clock period CLK 9 . The sum “F 0 +F 4 ” is used as the element “a 0 +a 3 ” in the equation (13). 
     Clock Period CLK 10   
     At the following clock period CLK 10 , the controller unit  30  develops the control signal S 1  to indicate the rearrange circuit  12  to execute the procedure defined for the clock period CLK 10 . In response to the control signal S 1 , the rearrange circuit  12  outputs the pixel data F 1 , F 3 , F 5 , and F 7  as the pixel data m 1 , m 3 , m 5  and m 7 , respectively. 
     The adder  21   1  transfers the pixel data ml to the flipflop FF 9 . This results in that the pixel data F 1  is stored in the flipflop FF 9  at the end of the clock period CLK 10 . The pixel data F 1  is used as the element “a 5 ” in the equation (14). 
     Correspondingly, the adder  21   2  transfers the pixel data m 3  to the flipflop FF 10 . This results in that the pixel data F 3  is stored in the flipflop FF 10  at the end of the clock period CLK 10 . The pixel data F 3  is used as the element “a 7 ” in the equation (14). 
     On the other hand, the adder  21   3  inverts the sign of the pixel data m 5 . The sign-inverted pixel data −m 5  is transferred to the flip-flop FF 11 . This results in that the sign-inverted pixel data −F 5  is stored in the flipflop FF 11  at the end of the clock period CLK 10 . The sign-inverted pixel data −F 5  is used as the element “−a 6 ” in the equation (14). 
     Correspondingly, the adder  21   4  inverts the sign of the pixel data m 7 . The sign-inverted pixel data −m 7  is transferred to the flip-flop FF 11 . This results in that the sign-inverted pixel data −F 5  is stored in the flipflop FF 12  at the end of the clock period CLK 10 . The sign-inverted pixel data −F 5  is used as the element “−a 4 ” in the equation (14). 
     In the meantime, the multiplier  23   1  receives the pixel data F 2  (=a 2 ) from the flip-flop FF 9 , while the controller unit  30  sets the coefficient α to D 5 . This allows the multiplier  23   1  to calculate the product of a 2  and D 5  used in the equation (13). The product “a 2 ×D 5 ” is stored into the flipflop FF 14  at the end of the clock period CLK 10 . 
     Correspondingly, the multiplier  23   2  receives the pixel data F 6  (=a 1 ) from the flip-flop FF 10 , while the controller unit  30  sets the coefficient β to D 1 . This allows the multiplier  23   2  to calculate the product of a 1  and D 1  used in the equation (13). The product “a 1 ×D 1 ” is stored into the flipflop FF 15  at the end of the clock period CLK 10 . 
     Correspondingly, the multiplier  23   3  receives the sum “F 0 +F 4 ” (=a 0 +a 3 ) from the flipflop FF 11 , while the controller unit  30  sets the coefficient γ to D 3 . This allows the multiplier  23   3  to calculate the product of the sum “a 0 +a 3 ” and the coefficient D 1  used in the equation (13). The product “(a 0 +a 3 )×D 1 ” is stored into the flipflop FF 16  at the end of the clock period CLK 10 . 
     In addition, the flipflop FF 17  is reset to zero at the end of the clock period CLK 10 . 
     Clock Period CLK 11   
     At the following clock period CLK 11 , the controller unit  30  develops the control signal S 1  to indicate the rearrange circuit  12  to execute the procedure defined for the clock period CLK 11 . In response to the control signal S 1 , the rearrange circuit  12  outputs the pixel data F 2 , F 6 , F 0 , and F 4  as the pixel data m 1 , m 3 , m 5  and m 6 . respectively. 
     The adder  21   1  transfers the pixel data m 1  to the flipflop FF 9 . This results in that the pixel data F 2  is stored in the flipflop FF 9  at the end of the clock period CLK 11 . The pixel data F 2  is used as the element “a 2 ” in the equation (13). 
     Correspondingly, the adder  21   2  transfers the pixel data m 3  to the flipflop FF 10 . This results in that the pixel data F 6  is stored in the flipflop FF 10  at the end of the clock period CLK 11 . The pixel data F 6  is used as the element “a 1 ” in the equation (14). 
     On the other hand, the adder  21   3  calculates the sum of the pixel data m 5  and m 6 , that is, the sum of the pixel data F 0  and F 4 . This results in that the sum “F 0 +F 4 ” is stored in the flip-flop FF 11  at the end of the clock period CLK 11 . The sum “F 0 +F 4 ” is used as the element “a 0 +a 3 ” in the equation (13). 
     In the meantime, the multiplier  23   1  receives the pixel data F 1  (=a 5 ) from the flip-flop FF 9 , while the controller unit  30  sets the coefficient α to D 6 . This allows the multiplier  23   1  to calculate the product of a 5  and D 6  used in the equation (14). The product “a 5 ×D 6 ” is stored into the flipflop FF 14  at the end of the clock period CLK 11 . 
     Correspondingly, the multiplier  23   2  receives the pixel data F 3  (=a 7 ) from the flip-flop FF 10 , while the controller unit  30  sets the coefficient β to D 4 . This allows the multiplier  23   2  to calculate the product of a 7  and D 4  used in the equation (14). The product “a 7 ×D 4 ” is stored into the flipflop FF 15  at the end of the clock period CLK 11 . 
     Correspondingly, the multiplier  23   3  receives the sign-inverted pixel data −F 5  (=−a 6 ) from the flipflop FF 11 , while the controller unit  30  sets the coefficient γ to D 2 . This allows the multiplier  23   3  to calculate the product of −a 6  and D 2  used in the equation (14). The product “−a 0 ×D 2 ” is stored into the flipflop FF 16  at the end of the clock period CLK 11 . 
     Correspondingly, the multiplier  23   4  receives the sign-inverted pixel data −F 7  (=−a 4 ) from the flipflop FF 12 , while the controller unit  30  sets the coefficient δ to D 0 . This allows the multiplier  23   4  to calculate the product of −a 4  and D 0  used in the equation (14). The product “−a 4 ×D 0 ” is stored into the flipflop FF 17  at the end of the clock period CLK 11 . 
     Furthermore, the adder/subtractor unit  25  calculates the sum of the outputs of the flipflops FF 14  to FF 17  and the selector  25   5 , and transfers the calculated sum to the flipflop FF 19 . The selector  25   5  is controlled to develop zero on the output by the controller unit  30 . The fact that the selector  25   5  and the flipflop FF 17  output zero results in that the adder/subtractor unit  25  calculates the term “(a 0 +a 3 )×D 3 +a 2 ×D 5 +a 1 ×D 1 ”, that is, the term “(f 0 +f 4 )/2”. The calculated term “(f 0 +f 4 )/2” is latched by the flipflop FF 19  at the end of the CLK 11 . 
     Clock Period CLK 12   
     At the following clock period CLK 12 , the controller unit  30  develops the control signal S 1  to indicate the rearrange circuit  12  to execute the procedure defined for the clock period CLK 12 . In response to the control signal S 1 , the rearrange circuit  12  outputs the pixel data F 1 , F 3 , F 5 , and F 7  as the pixel data m 1 , m 3 , m 5  and m 7 . respectively. 
     The adder  21   1  transfers the pixel data m 1  to the flipflop FF 9 . This results in that the pixel data F 1  is stored in the flipflop FF 9  at the end of the clock period CLK 12 . The pixel data F 1  is used as the element “a 5 ” in the equation (14). 
     Correspondingly, the adder  21   2  transfers the pixel data m 3  to the flipflop FF 10 . This results in that the pixel data F 3  is stored in the flipflop FF 10  at the end of the clock period CLK 12 . The pixel data F 3  is used as the element “a 7 ” in the equation (14). 
     On the other hand, the adder  21   3  inverts the sign of the pixel data m 5 . The sign-inverted pixel data −m 5  is transferred to the flip-flop FF 11 . This results in that the sign-inverted pixel data −F 5  is stored in the flipflop FF 11  at the end of the clock period CLK 12 . The sign-inverted pixel data −F 5  is used as the element “−a 6 ” in the equation (14). 
     Correspondingly, the adder  21   4  inverts the sign of the pixel data m 7 . The sign-inverted pixel data −m 7  is transferred to the flip-flop FF 11 . This results in that the sign-inverted pixel data −F 5  is stored in the flipflop FF 12  at the end of the clock period CLK 12 . The sign-inverted pixel data −F 5  is used as the element “−a 4 ” in the equation (14). 
     In the meantime, the multiplier  23   1  receives the pixel data F 2  (=a 2 ) from the flip-flop FF 9 , while the controller unit  30  sets the coefficient α to D 5 . This allows the multiplier  23   1  to calculate the product of a 2  and D 5  used in the equation (13). The product “a 2 ×D 5 ” is stored into the flipflop FF 14  at the end of the clock period CLK 12 . 
     Correspondingly, the multiplier  23   2  receives the pixel data F 6  (=a 1 ) from the flip-flop FF 10 , while the controller unit  30  sets the coefficient β to D 1 . This allows the multiplier  23   2  to calculate the product of a 1  and D 1  used in the equation (13). The product “a 1 ×D 1 ” is stored into the flipflop FF 15  at the end of the clock period CLK 12 . 
     Correspondingly, the multiplier  23   3  receives the sum “F 0 +F 4 ” (=a 0 +a 3 ) from the flipflop FF 11 , while the controller unit  30  sets the coefficient γ to D 3 . This allows the multiplier  23   3  to calculate the product of the sum “a 0 +a 3 ” and the coefficient D 1  used in the equation (13). The product “(a 0 +a 3 )×D 1 ” is stored into the flipflop FF 16  at the end of the clock period CLK 12 . 
     Furthermore, the adder/subtractor unit  25  calculates the sum of the outputs of the flipflops FF 14  to FF 17  and the selector  25   5 . The selector  25   5  is controlled to select the output of the flipflop FF 19  by the controller unit  30 . This results in that the adder/subtractor unit  25  calculates the decoded pixel data f 0 , because the adder/subtractor unit  25  calculates the sum of the value “a 5 ×D 6 +a 7 ×D 4 −a 6 ×D 2 −a 4 ×D 0 ”, which is the sum of the outputs of the flip-flops FF 14  to FF 17 , and the value “(a 0 +a 3 )×D 3 +a 2 ×D 5 +a 1 ×D 1 ”, which is the output of the flipflop FF 19 . This calculation is equivalent to the calculation of the sum of the term “(f 0 +f 4 )/2” and the term “(f 0 −f 4 )/2”. The decoded pixel data f 0  is latched by the flipflop FF 19  at the end of the clock period CLK 12 . 
     Furthermore, the value “(a 0 +a 3 )×D 3 +a 2 ×D 5 +a 1 ×D 1 ”, which has been stored in the flipflop FF 19 , is transferred to the flip-flop FF 20  at the end of the clock period CLK 12 . It should be noted that the value “(a 0 +a 3 )×D 3 +a 2 ×D 5 +a 1 ×D 1 ”, latched by the flipflop FF 20 , is not outputted as the decoded pixel data. 
     Clock Period CLK 13   
     At the following clock period CLK 13 , as shown in  FIG. 9 , the controller unit  30  develops the control signal S 1  to indicate the rearrange circuit  12  to execute the procedure defined for the clock period CLK 13 . In response to the control signal S 1 , the rearrange circuit  12  outputs the pixel data F 6 , F 2 , F 0 , and F 4  as the pixel data m 1 , m 3 , m 5  and m 6 . respectively. These pixel data m 1 , m 3 , m 5  and m 6  are used for the calculation of the decoded pixel data f 1  and f 7 , that is, the calculation of the second rows of the matrices in the equations (13) and (14). The output of the pixel data m 1 , m 3 , m 5  and m 6  allows the adders  23   1  to  23   3  to execute addition for calculating the decoded pixel data f 1  and f 7 . 
     In the meantime, the multiplier  23   1  receives the pixel data F 2  (=a 2 ) from the flip-flop FF 9 , while the controller unit  30  sets the coefficient α to D 5 . This allows the multiplier  23   1  to calculate the product of a 2  and D 5  used in the equation (13). The product “a 2 ×D 5 ” is stored into the flipflop FF 14  at the end of the clock period CLK 13 . 
     Correspondingly, the multiplier  23   2  receives the pixel data F 6  (=a 1 ) from the flip-flop FF 10 , while the controller unit  30  sets the coefficient β to D 1 . This allows the multiplier  23   2  to calculate the product of a 1  and D 1  used in the equation (13). The product “a 1 ×D 1 ” is stored into the flipflop FF 15  at the end of the clock period CLK 13 . 
     Correspondingly, the multiplier  23   3  receives the sum “F 0 +F 4 ” (=a 0 +a 3 ) from the flipflop FF 11 , while the controller unit  30  sets the coefficient γ to D 3 . This allows the multiplier  23   3  to calculate the product of the sum “a 0 +a 3 ” and the coefficient D 1  used in the equation (13). The product “(a 0 +a 3 )×D 1 ” is stored into the flipflop FF 16  at the end of the clock period CLK 13 . 
     The output of the multiplier  23   4  is ignored. 
     Furthermore, the adder/subtractor unit  25  calculates the sum of the outputs of the flipflops FF 14  to FF 17  and the selector  25   5 . The selector  25   5  is controlled to select the output of the flipflop FF 19  by the controller unit  30 . The fact that the flipflop FF 17  output zero results in that the adder/subtractor unit  25  calculates the term “(a 0 +a 3 )×D 3 +a 2 ×D 5 +a 1 ×D 1 ”, that is, the term “(f 0 +f 4 )/2”. The calculated term “(f 0 +f 4 )/2” is latched by the flip-flop FF 19  at the end of the CLK 13 . 
     In addition, the decoded pixel data f 0 , which has been stored in the flipflop FF 19 , is transferred to the flipflop FF 20  at the end of the clock period CLK 13 . This allows the output of the decoded pixel data f 0  from the flipflop FF 20  at the following clock period CLK 14 . 
     Clock Periods CLK 14  and CLK 15   
     At the following clock period CLK 14 , the controller unit  30  develops the control signal S 1  to indicate the rearrange circuit  12  to execute the procedure defined for the clock period CLK 14 . In response to the control signal S 1 , the rearrange circuit  12  outputs the pixel data F 5 , F 1 , F 7 , and F 3  as the pixel data m 1 , m 3 , m 5  and m 7 , respectively. These pixel data m 1 , m 3 , m 5  and m 7  and m 6  are used for the calculation of the decoded pixel data f 1  and f 7 , that is, the calculation of the second rows of the matrices in the equations (13) and (14). The output of the pixel data m 1 , m 3 , m 5  and m 7  allows the adders  23   1  to  23   3  to execute addition for calculating the decoded pixel data f 1  and f 7 . In addition, the multipliers  23   1  to  23   4  execute multiplication for calculating the decoded pixel data f 1  and f 7 . 
     Furthermore, the adder/subtractor unit  25  calculates the sum of the outputs of the flipflops FF 14  to FF 17  and the selector  25   5 . The selector  25   5  is controlled to invert the sign of the output of the flipflop FF 19  by the controller unit  30 . This results in that the adder/subtractor unit  25  calculates the decoded pixel data f 4 , because the adder/subtractor unit  25  calculates the difference when the value “(a 0 +a 3 )×D 3 +a 2 ×D 5 +a 1 ×D 1 ”, which is the output of the flipflop FF 19 , is subtracted from the value “a 5 ×D 6 +a 7 ×D 4 −a 6 ×D 2 −a 4 ×D 0 ”, which is the sum of the outputs of the flip-flops FF 14  to FF 17 . This calculation is equivalent to the calculation of the difference when the term “(f 0 −f 4 )/2” is subtracted from the term “(f 0 +f 4 )/2”. The decoded pixel data f 4  is latched by the flipflop FF 19  at the end of the clock period CLK 14 . 
     Furthermore, the value “(a 0 +a 3 )×D 3 +a 2 ×D 5 +a 1 ×D 1 ”, that is, the term “(f 0 +f 4 )/2”, which has been stored in the flipflop FF 19 , is transferred to the flipflop FF 20  at the end of the clock period CLK 14 . It should be noted that the value “(a 0 +a 3 )×D 3 +a 2 ×D 5 +a 1 ×D 1 ”, latched by the flipflop FF 20 , is not outputted as the decoded pixel data. 
     The decoded pixel data f 4  is then transferred from the flipflop FF 19  to the flipflop FF 20  at the clock period CLK 15 . This allows the output of the decoded pixel data f 4  from the flipflop FF 20 . 
     The same goes for the decoded pixel data f 1  to f 3 , and f 5  to f 7 . 
     Second Embodiment 
     In a second embodiment, the image processing apparatus is designed to perform the discrete wavelet transform using the reversible 5/3 filter in addition to the discrete wavelet transform using the irreversible 9/7 filter, and the discrete cosine transform. 
       FIG. 11  shows a block diagram of the image processing apparatus in the second embodiment. The image processing apparatus in the second embodiment is similar to that in the first embodiment, except for elements enclosed by a dashed line 40. In detail, additional circuits (not shown) are disposed around the adder  21   1  and  21   2  to form a reversible processing circuit  41 . Furthermore, selectors  42  and  45  are additionally disposed. 
     As shown in  FIG. 14 , the reversible processing circuit  41  includes selectors  46   a  and  46   b , a shifter  47 , a selector  48 , and a complementer  49 . The selector  46   a  selects one of the pixel data m 1 , the output of the flip-flop FF 14 , and the output of the flipflop FF 15  in response to a control signal from the controller unit  30 . The output of the selector  46   a  is connected to the first input of the adder  21   1 . The selector selects one of the pixel data m 2  and the output of the flipflop FF 15 . The output of the selector  46   b  is connected to the second input of the adder  21   1 . The input of the shifter  47  is connected to the output of the adder  21   1 . The output of the shifter  47  is connected to the input of the flipflop FF 9 . The selector  48  selects one of the pixel data m 3  and the output of the flipflop FF 9 . The output of the selector  48  is connected to the input of the complementer  49 . The output of the complementer  49  is connected to the first input of the adder  21   2 . The second input of the adder  21   2  receives the pixel data m 4 . 
     Referring back to  FIG. 11 , the selector  42  selects one of the outputs of the multiplier  23   1 , the flipflop FF 9 , and the flipflop FF 15 . The output of the selector  42  is connected to the flipflop FF 14 . 
     The selector  43  selects one of the outputs of the multiplier  23   2  and the flipflop FF 10 . The output of the selector  43  is connected to the flipflop FF 14 . The selectors  42  and  43  allow the image processor to disable the multipliers  23   1  and  23   2  during performing the discrete wavelet transform using the reversible 5/3 filter. 
     The selector  44  selects one of the outputs of the flipflops FF 14  and FF 10 . The output of the selector  44  is connected to an input of the selector  45 . 
     The selector  45  selects one of the outputs of the selector  45  and the limiter  26 . The output of the selector  45  is connected to the input of the flipflop FF 20 . The selector  45  is controlled to select the output of the selector  44  during performing the discrete wavelet transform using the reversible 5/3 filter. This implies that the discrete wavelet transform using the reversible 5/3 filter does not require the adder  21   3 ,  21   4 , the flipflops FF 11  to FF 13 , the multipliers  23   3  to  23   5 , the flipflops FF 16  to FF 18 , the adder  25   1  to  25   4 , the selector  25   5 , and the flipflop FF 19 , and the limiter  26 . 
     An explanation of the procedure of encoding through the discrete wavelet transform using the reversible 5/3 filter in this embodiment is given in the following. 
     As shown in  FIG. 12 , the encoding begins with the reception of the pixel data. The pixel data X(2n−2) to X(2n−8) are transferred to the flipflops FF 0  to FF 6 , respectively, in synchronization with the clock signal. The pixel data X(2n−3) is associated with the pixel of interest, which is positioned in the odd numbered columns. The following is the explanation of the procedure of encoding the pixel data associated with the pixel of interest positioned in the odd numbered columns. 
     At a clock period CLK 1 , the controller unit  30  develops the control signal S 1  to indicate the rearrange circuit  12  to execute the procedure defined for the clock period CLK 1 . In response to the control signal S 1 , the rearrange circuit  12  outputs the pixel data X(2n−2) and X(2n−4) as the pixel data m 1 , and m 2 , respectively. 
     The adder  21   1  calculates the sum of the pixel data X(2n−2) and X(2n−4), which is used in the equation (5). The sum “X(2n−2)+X(2n−4)” is provided for the shifter  47 . 
     The shifter  47  accomplishes 1-bit right-shift of the sum “X(2n−2)+X(2n−4)”. This right-shift is equivalent to the division by 2, and thus the output of the shifter  47  is equal to [(X(2n−2)+X(2n−4))/2], where [x] is the floor function. The output of the shifter  47  is transferred to the flipflop FF 9  at the end of the clock period CLK 1 . It should be noted that, in  FIG. 12 , numbers arranged in rows and columns denotes the indices specifying the pixels, the brackets “[ ]” represents that the data is processed by the floor function, and the symbols “*” represents that the associated data are intermediate results. 
     At the following clock period CLK 2 , pixel data X(2n−1) to X(2n−7) are transferred to the flipflops FF 0  to FF 6 , respectively. The controller unit  30  develops the control signal S 1  to indicate the rearrange circuit  12  to execute the procedure defined for the clock period CLK 2 . In response to the control signal S 1 , the rearrange circuit  12  outputs the pixel data X(2n−3) as the pixel data m 3 . 
     The complementer  49  develops a complement of the output of the flipflop FF 9 , that is, a complement of [(X(2n−2)+X(2n−4))/2], and the developed complement is inputted to the adder  21   2 . The adder  21   2  calculates the difference when [(X(2n−2)+X(2n−4))/2] received from the flipflop FF 9  is subtracted from the pixel data m 4 . As described in the equation (5), this achieves the calculation of the encoded pixel data Y(2n−3). The encoded pixel data Y(2n−3) is transferred to the flipflop FF 10  at the end of the clock period CLK 2 . 
     The encoded pixel data Y(2n−3) is transferred to the flipflop FF 15  through the selector  43 . The flipflop FF 15  contains the encoded pixel data Y(2n−3) till the clock period CLK 4  expires. The encoded pixel data Y(2n−3) is then transferred to the flipflop FF 14  through the selector  42  at the end of the clock period CLK 5 . The flipflop FF 14  contains the encoded pixel data Y(2n−3) till the clock period CLK 6  expires. Then, the encoded pixel data Y(2n−3) is transferred to the flipflop FF 20  through the selectors  44  and  45  at the end of the clock period CLK 7 . Finally, the encoded pixel data Y(2n−3) is outputted from the flipflop FF 20  at the clock period CLK 8 . 
     Below is an explanation of the procedure of encoding the pixel data associated with the pixel of interest positioned in the even numbered columns. The encoded pixel data for the even numbered columns is obtained using the intermediate results generated during the encoding for the odd numbered columns as described below. 
     At the clock period CLK 3 , the controller unit  30  develops the control signal S 1  to indicate the rearrange circuit  12  to execute the procedure defined for the clock period CLK 3 . In response to the control signal S 1 , the rearrange circuit  12  outputs the pixel data X(2n) and X(2n−2) as the pixel data m 1 , and m 2 , respectively. 
     The adder  21   1  calculates the sum of the pixel data X(2n) and X(2n−2), which is used in the equation (5). The sum “X(2n)+X(2n−2)” is provided for the shifter  47 . 
     The shifter  47  accomplishes 1-bit right-shift of the sum “X(2n)+X(2n−2)”. This right-shift is equivalent to the division by 2, and thus, the output of the shifter  47  is equal to [(X(2n)+X(2n−2))/2] in the equation (5). The output of the shifter  47  is transferred to the flipflop FF 9  at the end of the clock period CLK 3 . 
     At the following clock period CLK 4 , pixel data X(2n+1) to X(2n−5) are transferred to the flipflops FF 0  to FF 6 , respectively. The controller unit  30  develops the control signal S 1  to indicate the rearrange circuit  12  to execute the procedure defined for the clock period CLK 4 . In response to the control signal S 1 , the rearrangement circuit  12  outputs the pixel data X(2n−1) as the pixel data m 4 . 
     The complementer  49  develops a complement of the output of the flipflop FF 9 , that is, a complement of [(X(2n)+X(2n−2))/2], and the developed complement is inputted to the adder  21   2 . The adder  21   2  calculates the difference when [(X(2n)+X(2n−2))/2] received from the flip-flop FF 9  is subtracted from the pixel data m 4 . As described in the equation (5), this achieves the calculation of the encoded pixel data Y(2n−1). The encoded pixel data Y(2n−1) is transferred to the flipflop FF 10  at the end of the clock period CLK 4 . The encoded pixel data Y(2n−1) is transferred to the flipflop FF 15  through the selector  43  at the end of the clock period CLK 5 . 
     At the following clock period CLK 6 , the adder  21   1  receives the pixel data Y(2n−1) from the flipflop FF 15 , the pixel data Y(2n−3) from the flipflop FF 14 . The adder  21   1  then calculates the sum of the pixel data Y(2n−1), Y(2n−3), and a constant of “2”, that is, the term “Y(2n−1)+Y(2n+1)+2” in the equation (6). 
     The shifter  47  accomplishes 2-bit right-shift of the term “Y(2n−1)+Y(2n+1)+2”. This 2-bit right-shift is equivalent to the division by 4, and thus, the output of the shifter  47  is equal to [(Y(2n−1)+Y(2n+1))/2] in the equation (5). The output of the shifter  47  is transferred to the flipflop FF 9  at the end of the clock period CLK 6 . 
     At the following clock period CLK 7 , pixel data X(2n+4) to X(2n−2) are transferred to the flipflops FF 0  to FF 6 , respectively. The controller unit  30  develops the control signal S 1  to indicate the rearrange circuit  12  to execute the procedure defined for the clock period CLK 7 . In response to the control signal S 1 , the rearrangement circuit  12  outputs the pixel data X(2n−2) as the pixel data m 4 . 
     The adder  21   2  calculates the sum of the pixel data X(2n−2) and the output of the flip-flop FF 9 , that is, [(Y(2n−1)+Y(2n+1))/2]. This achieves the calculation of the right hand of the equation (6), that is, the encoded pixel data Y(2n−2). The encoded pixel data Y(2n−2) is transferred to the flipflop FF 10  at the end of the clock period CLK 7 . The pixel data Y(2n−2) is then transferred to the flipflop FF 20  through the selectors  44  and  45  at the end of the clock period CLK 8 . This allows the output of the encoded pixel data Y(2n−2) from the flipflop FF 20  at the following clock period CLK 9 . 
       FIG. 13  is a timing chart describing the procedure of decoding through the discrete wavelet transform using the reversible 5/3 filter. The procedure of the decoding is almost similar to the aforementioned encoding except for that the equations (7) and (8) are used in place of the equations (5) and (6). Therefore, detailed explanation is not given. 
     As thus-described, the image processing apparatus in accordance with the present invention can perform both the discrete wavelet transform and the discrete cosine transform by using the same circuitry. This effectively reduces the necessary hardware resources. 
     Although the invention has been described in its preferred form with a certain degree of particularity, it is understood that the present disclosure of the preferred form has been changed in the details of construction and the combination and arrangement of parts may be resorted to without departing from the scope of the invention as hereinafter claimed.