Abstract:
A process for the three step-multiplex control of electro-optical display arrangements having segment-like forward and back electrodes, through the intermediary of periodic pulse sequences which have six pulses within each control period, which can presently assume four different voltage levels. Three of these pulse sequences are constantly applied to the back electrodes and the additional pulse sequences, in accordance with the measure of the display which is to be represented, are applied to the forward electrodes. The invention further includes a circuit for effectuating the process for the three step-multiplex control.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a process for the three step-multiplex control of electro-optical display arrangements having segment-like forward and back electrodes, through the intermediary of periodic pulse sequences which have six pulses within each control period, which can presently assume four different voltage levels, and wherein three of these pulse sequences are constantly applied to the back electrodes and the additional pulse sequences, in accordance with the measure of the display which is to be represented, are applied to the forward electrodes. The invention further relates to a circuit for effectuating the process for the three step-multiplex control. 
     For the control of liquid crystal display arrangements it is necessary that the display segments thereof be operated with alternating current since, otherwise, the life expectancy of the displays is extensively reduced. This requirement renders more difficult a multiplex control of liquid crystal displays and leads to a considerable increase in its circuitry requirements. 
     2. Discussion of the Prior Art 
     In a data sheet of the firm Shinshu Seiki Co. Ltd., dated July 15, 1977, under the heading &#34;Specifications for Liquid Crystal Display LD-316&#34;, and in the periodical &#34;Electronics&#34; of July 5, 1979, page 141 under the title &#34;Three-line multiplexing cut pin count of complex LCDs&#34; by L. T. Reiss, there was disclosed a three step-multiplex control process which operates with four voltage levels and which evidences pulse sequences which are periodic step functions. For the control of displays, in particular of seven-segment displays, eight different pulse sequences are necessary for this process. Hereby, it is disadvantageous that for the generation of each pulse sequence it is necessary to provide a special switching circuit, which requires a significant manufacturing demand. In the utilization of microprocessors for the generation of the pulse sequences, this multiplicity of different pulse sequences leads to correspondingly high programming and storage requirements. 
     SUMMARY OF THE INVENTION 
     In recognition of the fact that for the production of monolithic pulse generating circuits there is to be preferred the utilization of functional groups which are the same relative to each other, the invention has as its object the development of a three step-multiplex control process of the above described type, which requires the least possible number of different pulse sequences. 
     For the representation of an indicia, for example, a numeral with a seven-segment display, there are accordingly required only four different pulse sequences, which substantially reduces the requirement for the development of the monolithic circuit. 
     Whereas the five forward electrode pulse sequences facilitate a representation of numerals, for instance, in a seven-segment display, for the representation of special indicia, for example, a point, sign digit and so forth, additional pulses sequences are necessary. Inventively, these additional forward electrode pulse sequences can be drawn off from the back electrode pulse sequences through a phase displacement by one-sixth of the control period, which signifies a further advantage in connection with the inventive object. 
     Furthermore, pursuant to the invention, there is also provided the advantageous capability of realizing a signal preparation circuit through a programmable storage logic control. As a programmable storage circuit that can be utilized a microprocessor which rhythmically transmits the data serially or in parallel to the logic circuit. Inventively, in a serial control there is provided a shift register at the input of the logic circuit which converts the series data into parallel data. 
     In a non-programmable storage, but connecting programmable realization of the signal preparation circuit, there is in particular, provided the capability that logic information processing operations can be coupled into the control cycle for the display whereby such a version, as is known, allows for higher operating speeds. Furthermore, it is advantageous that this circuit consists of circuit elements which can be integrated in an energy-saving CMOS technology. 
     Pursuant to the invention, there is also achieved a fixed-phase coupling of all operational units in an advantageous manner through a synchronizing oscillator and a frequency divider which is connected to the output of the oscillator. 
     A further advantage in the monolithic integration is provided through the capability that it is possible to save on OR interconnections through the above measures. For the generation of each of the four different pulse sequences there serve four different pulses generating switching circuits, so that there is simplified the production of monolithic switching circuits. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Reference may now be had to the following detailed description of the inventive process as well as to preferred exemplary embodiments of the invention, taken in conjunction with the accompanying drawings; in which: 
     FIG. 1 illustrates eight pulse sequences for the control of a seven-segment numerical display; 
     FIG. 2 illustrates further pulse sequences for the generation of special indicia; 
     FIG. 3 is a circuit block diagram for the effectuation of the process; 
     FIG. 4 is a circuit block diagram of a control circuit which includes a programmable storage circuit and a logic circuit pursuant to a first embodiment of the invention; 
     FIG. 5 illustrates a modified embodiment of the invention; 
     FIG. 6 is a representation of rhythmic and control pulse sequences pursuant to FIG. 5; 
     FIG. 7 is a view of the construction of a pulse generator pursuant to FIG. 5; 
     FIG. 8 is a current circuit diagram for a back electrode pulse sequence generator pursuant to FIG. 7; 
     FIG. 9 is a current circuit diagram for a forward electrode pulse sequence generator pursuant to FIG. 7; 
     FIGS. 10a, b, c, and d each show current circuit diagrams for the pulse generating switching circuits pursuant to FIGS. 8 and 9; 
     FIG. 11 is a current cycle diagram for the control of the forward and back electrodes of two seven-segment displays; and 
     FIG. 12 is a repesentation pursuant to FIG. 11 with special indicia. 
    
    
     DETAILED DESCRIPTION 
     The representation relates to segment displays wherein each segment S is optically activated through control of the forward electrode and of the back electrode. 
     FIG. 1 illustrates eight pulse sequences required for the display of a seven-segment numeral, which evidence four different voltage levels whereby there occur two extreme levels designated with EI and EII and two median levels designated with MI and MII. The length of the illustrated pulse sequences corresponds in time interval to a control period SP and is subdivided into six equal parts. Each two adjoining voltage plateaus lie apart about 1/3 of the maximum voltage which is obtained from difference between the two extreme levels EI and EII. Three back electrode pulse sequences PI supply power through three input conductors RZ to a plurality of back electrodes RE (see FIG. 11) of segments S. Deactuated segments are identified through an open circle, and actuated segments S additionally with a cross. Each one of at least five forward electrode pulse sequences PI controls the forward electrodes VE (see FIG. 11) through forward electrode input conductors VZ of segment S which are powered by three different back electrode pulse sequences PI. 
     Indicated in FIG. 2 are three additional forward electrode pulse sequences PIId which, together with those pursuant to FIG. 1, can be utilized for the formation of special indicia SO (see FIG. 12). 
     The effective voltage which is applied to a liquid crystal, according to the above indicated literature, is calculated as the quadratic median value of the voltage differential which is applied between two oppositely located segment electrodes. In order to achieve a high contrast it is advantageous when the effective voltage ratio between the actuated and deactuated condition is as high as possible. This relationship has, in the inventive process, a value of 1.915. A usual liquid crystal display (LCD in FIG. 3) evidences an effective threshold voltage value of approximately one volt so that, for effective voltages which lie below this value, the display is switched off, whereas with an increasing effective voltage above this value, the contrast increases quite rapidly. Therefore, when the voltage level EI, MI, MII and EII is selected so that the effective maximum voltage consists of about 1.8 volts, there is then obtained a liquid crystal display which is rich in its contrast. 
     Illustrated in FIG. 3 is the principal construction of a three step-multiplex control circuit. An input unit EE forms the information which is to be represented into a binary voltage level, which is interrogated through synchronizing pulses of a signal preparation circuit SAS. The signal preparation circuit SAS is connected with a voltage generator SG which generates the four voltage levels EI, MI, MII and EII. The signal preparation circuit SAS, in accordance with the information which is to be represented now controls the segments S of the liquid crystal display LCD. Hereby, the same back electrodes RE (see FIG. 11) for each indicia of a display LCD encompassing a plurality of indicia are connected with each other and commonly controlled through a predetermined pulse sequence of the three back electrode pulse sequences PI. For the representation of a predetermined indicia sequence, the forward electrodes VE (see FIG. 11) of the different indicia are controlled with predetermined pulse sequences of the forward electrode pulse sequences PII, as is described in the above-mentioned literature in connection with other pulse sequences. 
     In FIG. 4 the signal preparation circuit SAS consists of a programmable storage circuit MP, for example, a microprocessor, which is connected with a logic circuit LS which, in turn, is powered by the voltage generator SG. The microprocessor again rhythmically interrogates the information which is to be represented from the input unit VE, for example, a multidigit numeral, and transmits this further to the logic circuit LS. The data transmission preferably takes place serially. The logic circuit LS converts the serial data into parallel data through a shift register SR. The logic circuit LS particularly includes a pulse generator PG which generates the forward and back electrode pulse sequences PII and PI, and a multiplexer MUX whose function is more closely explained in connection with FIG. 5. 
     In FIG. 5 the signal preparation circuit SAS consists of an oscillator OSZ, a frequency divider FT, a pulse generator PG, a decoder driver DTR, an intermediate storage ZSP and the multiplexer MUX. The rhythmic pulses TI which are generated by the oscillator OSZ control the frequency divider which controls the input unit EE with rhythmic pulses TII, for example, at the frequency 1 HZ. Other outputs of the frequency divider FT generate, in effect, in synchronism with the control period SP, pulse sequences FI through FVI which are distinguished from each other through phase displacements of 1/6 of their period and which, during a time interval of 1/6 of their period, assume a voltage condition H and during 5/6 of their period another voltage condition L (see FIG. 6). Since the frequency divider is for this purpose equipped for a 1/6 division, at another output for the control of the intermediate storage ZSP, it delivers synchronizing pulses TII, the duration of which preferably consists of whole-digit multiple of the sextuple period duration of the synchronizing pulses TI (for example, a frequency of TI: 256 Hz; frequency of TII: 42.67 Hz). These pulse sequences FI through FVI will through a signal input control the pulse generator PG, whose other inputs are connected with the voltage generator SG and from which the outputs are connected with the multiplexer MUX and the display arrangement LCD. The input unit EE transmits binary-coded the information which is to be displayed in the rhythm TIII in the form of binary voltage pulses to the decoder-driver DTR, which decodes it into a normal seven-segment representation which reads into the intermediate storage ZSP from which there is further conveyed the information in rhythm TII to the multiplexer MUX, whereby the segments S which are selected therefor by the decoder-driver DTR are superimposed upon by the corresponding pulse sequences PII of the pulse generator PG. 
     The generation of the, as previously described, inventively constructed and applied pulse sequences PI and PII in the pulse generator PG is described in closer detail hereinbelow. Pursuant to FIG. 7, the pulse generator PG contains a back electrode pulse generator RP and a forward electrode pulse generator VP which are supplied with control pulse sequences FI through FVI of the frequency divider FT through connectors rd and va, and from the voltage generator SG through connectors ra and vc, and connected with each other through connectors rc and rb. The forward and back electrodes pulse sequences PI and PII can be taken off at the outputs vd and rb. 
     The voltage circuit diagram shown in FIG. 8 is that for the back electrode pulse generator RP. It consists of three identical pulse generating switching circuits A, A&#39;, A&#34;, whose control inputs a1 through a6, a1&#39; through a6&#39;, and a1&#34; through a6&#34; are controlled through the connectors ra by the control pulse sequences FI through FVI (see FIG. 6). Consequently, at the connector rb there appears the three back electrode pulse sequences PI, as described hereinbelow. 
     According to FIG. 9, the forward electrode pulse generator VP consists of five pulse generating switching circuits B, B&#39;, B&#34;, C and D, whereby three identical switching circuits B, B&#39; and B&#34; generated pulse sequences PIIa which are identical up to phase displacements. Each of the switching circuits B, B&#39; and B&#34; are controlled by the control signals FI through FVI whereby there are again generated the pulse sequences PIIa. 
     Pursuant to FIG. 10a, each of the pulse generating switching circuits A includes four transmission gates TG, whose outputs ta2, ta5, ta8 and tall are switched commonly to the switching circuit output a9, and whose inputs ta3, ta6, ta9 and ta12 are switched individually to the four switching circuit inputs a13, a12, a11 and a10, which are subjected through the connector rv with the voltage levels EI, MI, MII and EII. Two control inputs ta1 and ta10 of two transmission gates TG are directly connected with the switching circuit to control inputs a1 and a6. Two control inputs ta4 and ta7 of the two other transmission gates TG are connected with the outputs oa3 and oa6 of two dual-OR gates OG and with two switching circuit connections a7 and a8, whereby the connectors a7, a8 supply power through the connector rc to the forward electrode pulse generator VP (see FIG. 7). Hereby, there is achieved a simplification of the circuitry in that the same OR interconnections occur only once, in essence, need not again be duplicated for the forward electrode pulse generator. The connectors rc and vb (FIGS. 8 and 9) between the back electrode pulse generator RP and the forward electrode pulse generator VP includes the connectors r1 through r6 and v1 through v6, which are connected with each other in the indicated series sequence. The inputs oa1, oa2 and oa4, oa5 of the two OR gates OG are connected with the switching circuit control inputs a2, a3 and a4, a5. 
     Pulse generating switching circuit B, pursuant to FIG. 10b, has three transmission gates PG, whose outputs tb2, tb5 and tb8 are connected in common with the switching circuit output b5, and whose three inputs tb3, tb6 and tb9 are connected individually to the three switching circuit inputs b8, b7 and b6, whereby two transmission gate control inputs tb1, tb7 are connected directly with the switching circuit control inputs b1, b4, and a transmission gate control input tb4 with an output ob3 of a dual-OR gate OG, whose inputs ob1 and ob2 are connected to the switching circuit inputs b2 and b3. 
     The pulse generating switching circuits C and D serve in a corresponding manner for the generation of the pulse sequences PIIb and PIIc. 
     The switching circuit C, pursuant to FIG. 10c, has two transmission gates TG whose outputs tc2 and tc5 are connected in common to the switching circuit output c7 and whose two inputs tc3 and tc6 are individually connected to two switching circuit inputs c9 and c8, whereby two transmission gates control inputs tc1 and tc4 are connected with outputs oc3 and oc6 of two dual-OR gates OC and with the switching circuit connections c5 and c6, and whereby inputs oc1, oc2 and oc4, oc5 of the two OR gates OG are connected to switching circuit inputs c1 through c4. 
     The switching circuit D, pursuant to FIG. 10d, has two transmission gates TG whose outputs td2 and td5 are connected in common to the switching output d3 and whose two inputs td3 and td6 are connected to two switching circuit inputs d5 and d4, whereby two transmission gate control inputs td1 and td4 are connected directly with switching circuit control inputs d1 and d2. This switching circuit d4 does not include an OR gate since the functionally required OR interconnections have already been effectuated in other switching circuits and can be utilized for this purpose, as can be ascertained from the input circuitry of the switching circuit input d1 and d2 in FIG. 9. 
     The switching circuit connections b1 through b8, b1&#39; through b8&#39;, b1&#34; through b8&#34;, c1 through c9 and d1 through d5 of the switching circuits b, b&#39;, b&#34;, c and d (FIG. 10b through d) are correspondingly connected, pursuant to the previous constructions, to the switching circuit A (see FIGS. 8 and 10a) with the connectors va through vd of the forward electrode pulse generator VP (see FIG. 9). 
     The mode of operation of the pulse generator PG is predicated on that the pulse generating switching circuits, for example, A, B, C and D, are connected at their control inputs, for example, a1 through a6, b1 through b4, c1 through c4 and d1, d2 to the control pulse sequences FI through FVI either directly or interengaged with each other through OR gates. At each of the further inputs, for example, a10 through a13, b6, b8, c8, c9 and d4, d5, there is present one of the four voltage levels, EI, MI, MII, and EII as indicated in FIGS. 8 and 9. In order to minimize the number of conductors there is further provided an input, for example, b7, which is supplied not constantly, but in a switched manner, in effect with the output signal at d3 (see FIG. 9). 
     By way of example, there is now described the generation of the first pulse sequence of the back electrode pulse sequences PI illustrated in FIG. 1. At the commencement of the control period SP (see FIG. 1), through the control input a1 of the switching circuit A (see FIG. 8) there is applied a control pulse FI (see FIG. 6) to the control input ta1 of the transmission gate TG (see FIG. 10a) so as to thereby connect the voltage level b2 at the input a13 with the output a9. After a time interval of 1/6 of the control period SP, the control pulse FI is switched from the voltage condition H into the voltage condition L (see FIG. 6), and thereby the input a13 is disconnected from the output a9 and concurrently the control pulse FII is switched to the voltage condition H, in essence, is applied through the input a2 and the OR gate OG of the control pulse FII (see FIG. 8) to the control input ta4 of the transmission gate TG (see FIG. 10a), and thus the voltage level MII is now applied to the same output a9. In a corresponding manner there are subsequently sequentially connected the voltage levels MI, EI and EII to the output a9, in effect, here appears the first pulse sequence of the back electrode pulse sequence group PI (see FIG. 1). In this pulse sequence, the level MII appears at the times when the control pulses FII or FVI assume the voltage condition H (FIG. 6). Accordingly, the control pulses FII and FVI are conducted through the inputs oa1 and oa2 of the OR gate OG to the input ta4 which this level MII applies to the output a9 switching the transmission gate TG. 
     In a corresponding manner can there be generated various other pulse sequences PI, PII, whereby the number of the control impulses FI through FVI interconnected with each other through the OR connections corresponds to the occurence of the same voltage stages EI, MI, MII and EII during a control period SP of the present pulse sequence. 
     Illustrated in FIG. 11 is a voltage circuit diagram for the control of the forward and back electrodes VE and RE of two seven-segment displays. Hereby, each of the three back electrode pulse sequences PI is located at the same back electrode RE of each seven-segment display. The forward electrode pulse sequences PII are switched through the multiplexer MUX pursuant to the kind of indicia which is to be represented to the forward electrodes VE. 
     Illustrated in FIG. 12 is a representation pursuant to FIG. 11, which can be utilized for the control of special indicia SO, in this instance, a period and an arrow.