Abstract:
A configuration management system and method for adding or replacing devices in a bus in a computer system. The configuration system creates and maintains a memory structure having bus and device configuration information. The system includes a configuration manager which creates a memory structure containing configuration information for a bus and devices located on the bus within the computer system in which it operates. When a device on the bus is replaced, the configuration manager retrieves the configuration information for the replacement device from the memory structure and uses that information to configure the replacement device. In another aspect of the invention, when a device is added on the bus in the computer system, the configuration manager retrieves selected configuration information for the added device from the memory structure and uses that information to configure the added device.

Description:
RELATED APPLICATIONS 
     The subject matter of U.S. Patent Application entitled “Configuration Management Method for Hot Adding and Hot Replacing Devices”, filed on Oct. 1, 1997, Application Ser. No. 08/941,268, and A is related to this application. 
     PRIORITY CLAIM 
     The benefit under 35 U.S.C. §119(e) of the following U.S. provisional application(s) is hereby claimed: 
     
       
         
               
               
               
             
           
               
                   
               
               
                   
                 Application 
                   
               
               
                 Title 
                 No. 
                 Filing Date 
               
               
                   
               
             
             
               
                 “Hot Plug Software Architecture for Off 
                 60/046,311 
                 May 13, 1997 
               
               
                 the Shelf Operating Systems” 
               
               
                 “Means for Allowing Two or More 
                 60/046,491 
                 May 13, 1997 
               
               
                 Network Interface Controller Cards to 
               
               
                 Appear as One Card to an 
               
               
                 Operating System” 
               
               
                   
               
             
          
         
       
     
    
    
     APPENDICES 
     Appendix A, which forms a part of this disclosure, is a list of commonly owned copending U.S. patent applications. Each one of the applications listed in Appendix A is hereby incorporated herein in its entirety by reference thereto. 
     COPYRIGHT RIGHTS 
     A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to computer systems. Additionally, the invention relates to configuration space management for computer servers. 
     2. Description of the Related Technology 
     A server is a central computer in a network which manages the common data and supplies this data to workstations in the network. Current operating systems for servers do not by themselves provide the support users need to hot add and swap devices. Hot add refers to the addition of a device on a bus on the server while the server continues to operate. Hot replace refers to the replacement of a device on a bus of the server while the server continues to operate. Hot swap refers to a hot replace with the replacement device being identical to the replaced device. There is a need for the hot add and hot swap capabilities in order to avoid expensive server down time when replacing or adding devices to the server. Such devices include various peripheral devices such as mass storage and network adapters. Such devices are commonly interfaced with the server through various bus systems such as Peripheral Component Interconnect, CardBus, Microchannel, Industrial Standard Architecture (ISA), and Extended ISA (EISA). 
     One aspect of hot adding and hot swapping of devices that needs to be addressed is the system configuration. In the past in certain bus architectures, the system configuration was fixed prior to system initialization. However, such an approach does not support hot add or hot swap. Such systems also do not provide the ability to change the configuration parameters dynamically through a software interface. When performing a hot swap or hot add on a PCI bus, care must be taken to ensure that resources, such as, memory and I/O space, allocated to the new device do not conflict with concurrently assigned devices. Prior systems have required that for the replacement of a device or the addition of a device, the entire system be powered down, devices be replaced or added, and then the system be powered up and reconfigured. 
     There is a need for a methods and systems which facilitate the replacement and adding of a devices on a bus on the server while the server continues to operate. 
     There is also a need for systems and methods to ensure that resources, such as, memory and I/O space, allocated to the replacement devices and added devices do not conflict with concurrently assigned devices. 
     SUMMARY OF THE INVENTION 
     The invention addresses the above and other needs by providing a configuration system and method, which in one embodiment includes a configuration manager that creates a memory structure containing configuration information for a bus and devices located on the bus within the computer system in which it operates. When a device on the bus is replaced, the configuration manager retrieves the configuration information for the replacement device from the memory structure and uses that information to configure the replacement device. In another aspect of the invention, when a device is added on the bus in the computer system, the configuration manager retrieves selected configuration information for the added device from the memory structure and uses that information to configure the added device. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a computer system employing an embodiment of the invention; 
     FIG. 2 is a block diagram of a multiple bus computer configuration connected to a network of microcontrollers all of which are associated with the computer shown in FIG. 1; 
     FIG. 3 is a block diagram showing a multiple bus computer architecture with canisters connected to a network of microcontrollers which are all associated with the computer shown in FIG. 1; 
     FIG. 4 is a block diagram of a memory structure including configuration information; 
     FIG. 5 is a flowchart depicting the process followed in one embodiment of the invention for creating the configuration space data structure depicted in FIG. 4; 
     FIG. 6 is a flowchart depicting the process followed in one embodiment of the invention relating to hot swap; and 
     FIGS. 7A and 7B are flowcharts depicting the process followed in one embodiment of the invention relating to hot addition. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The invention will be described in terms of exemplary embodiments adapted to operate with particular computer systems. However, it will be clear to those skilled in the art that the principles of the invention can be utilized in other computer systems where it is desired to use and maintain configuration information. The exemplary embodiments are described below in further detail with reference to the Figures, wherein like elements are referenced by like numerals throughout. 
     One specific environment in which the invention can be utilized is described in application Ser. No. 08/942,309, entitled “Hot Add of Devices Software Architecture” incorporated by reference above and is described below in general terms to provide the reader with an example of a specific application of the invention. However, the invention can be utilized in various other systems. 
     FIG. 1 is a block diagram of a computer system which incorporates an embodiment of the invention. The system includes a computer  100  connecting to a mass storage adapter  102  and a Local Area Network (LAN) adapter  104 . The overall operation of the computer is managed by an industry standard operating system  101  such as Windows® NT, NetWare®, Disk Operating System (DOS), or UNIX®. Operating under the operating system is a configuration manager program  103 . The system may include a remote computer  130  which is in communication with computer  100  via a telephone link. The mass storage adapter  102  may contain various types of device controllers including, for example: a magnetic disk controller  108  for magnetic disks  110 , an optical disk controller  112  for optical disks  114 , a magnetic tape controller  116  for magnetic tapes  124 , a printer controller  120  for various printers  122 , and any other type of controller  122  for other devices  126 . The LAN adapter  104  may include a LAN controller  128 . Vendors for a magnetic disk controller  108  and magnetic disks  110  include Qlogic, Intel, and Adaptec. 
     The LAN adapter  104  allows digital communication between the computer system and other computers (not shown) such as a network of servers via a connection  130 . Typically, slots of the LAN adapter  104  and the slots of the mass storage adapter are contained on the same bus system. In different embodiments of the invention, various bus systems can be employed such as the Peripheral Component Interconnect (PCI), Microchannel, Small Computer system Interface (SCSI), Industrial Standard Architecture (ISA) and Extended ISA (EISA) architectures. 
     FIG. 2 shows an embodiment of the bus structure of the computer  100 . A number ‘n’ of central processing units (CPUs)  200  are connected through a host bus  202  to a memory controller  204 . Bridges  206 ,  208  and  210  connect the host bus to three additional bus systems  212 ,  214 , and  216 . Bus systems  212 ,  214  and  216  may be any conventional bus system such as PCI, ISA, EISA and Microchannel. In one embodiment of the invention, the bus system  212  is PCI to support an internal VGA card or a SCSI device (referred to generally herein as “PC buses”). 
     The ISA Bridge  218  is coupled to the bus system  212  so as to support legacy devices such as a keyboard  220 , one or more floppy disk drives  222  and a mouse  224 . In one embodiment a network of microcontrollers  225  is interfaced to the ISA bus  226  as is described in U.S. patent application Ser. No. 08/942,309, incorporated by reference above. Bridge  230  and bridge  232  couple PC buses  214  and  216  with PC buses  234  and  236 , respectively, to provide expansion slots for peripheral devices or adapters. Having separate PC buses  234  and  236  eliminates the potential that a device driver or other transient I/O error on one of those buses will bring the entire system to a stop or stop the system administrator from communicating with the system. 
     FIG. 3 shows another bus structure embodiment of the computer  100 . PC bus  214  and  216  include bridges  242 ,  244 ,  246 ,  246  and  248  which are connected, respectively, to PC bus systems  250 ,  252 ,  254 , and  256 . As were PC bus systems  214  and  216 , PC bus systems  250 ,  252 ,  254  and  256  can be designed according to any type of bus architecture including PCI, ISA, EISA, and Microchannel. PC buses  250 ,  252 ,  254 , and  256  are each implemented on one of a group of canisters  258 ,  260 ,  262  and  264 . Canisters  258 ,  260 ,  262 , and  264  comprise casings for a detachable bus system. 
     A memory structure according to one embodiment of the invention will now be described with reference to FIG.  4 . In general, the memory structure includes the PCI configuration information required to perform hot add and hot swap of devices on the PCI buses. The information includes the configuration information that is stored in the general purpose configuration registers on the PCI devices. 
     Referring to FIG. 4, the memory structure is in the form of an array  402  with each array element, e.g.,  404 , of the array representing a PCI bus in the system. Each element of the array is referred to as a PCI bus information structure. A linked list  406  is attached to each array element. The elements  408  of the linked list represent devices on the PCI bus. In one embodiment, the memory structure is located in the main memory of the operating system and is created and maintained by the configuration manager  103  (FIG.  1 ). 
     Each PCI bus array element  404  may include the memory start and end locations  410 ,  412  for that bus, the I/O start and end locations  414 ,  416  for that bus, and a pointer  418  to the linked list  408  containing the configuration information for devices on that bus. In addition, the bus memory structure may include the memory location of the last memory space  420  assignment performed on that bus. That information may be used when hot adding a device to the bus. In one embodiment, when memory is allocated for devices on a bus, the memory is allocated from the highest address to the lowest. Therefore, the last address allocated is also the smallest address allocated. Similarly, the last I/O address allocated  422  may also be stored in that array structure. The PCI bus information structure may also include configuration information defined by the PCI standard under which the system is operating. 
     Each element  408  on the linked list  406  attached to each PCI bus information structure is referred to as a device information structure. Each device information structure typically contains PCI configuration information for a specific device on the bus corresponding to the PCI bus information structure to which the linked list is attached. The PCI configuration information is governed by the PCI specification. As an example, the device information structure includes the PCI vendor identification, PCI device identification, PCI command, PCI status, PCI revision identification, PCI class code, PCI cache line size, PCI latency timer, and the base register addresses (BAR&#39;s). Each device information structure in the linked list may also include a pointer to the next device information structure in the linked list or a null indicating the end of the list. 
     Referring now to FIG. 5, there is depicted a flowchart which illustrates one inventive method for creating the PCI configuration space data structure depicted in FIG.  4 . FIG. 5 represents the steps which may be accomplished by the configuration manager  103  operating within the computer system  100 . 
     As indicated by box  510 , the process indicated and represented by FIG. 5 is carried out for one or more buses on the system. At step  512 , space in the memory of the computer  100  (see FIGS. 1 and 2) is allocated for the memory structure. This allocation can be performed at the time of compiling or dynamically. 
     Next, at step  514  the predefined start and end memory addresses for the PCI bus are written to the array element representing that PCI bus. The start and end memory addresses may be the same as those used when the system is initialized by the BIOS program during system boot-up. 
     Then, at step  516 , the predefined start and end input/output (“I/O”) addresses and the interrupt assignment (ISA IRQ) for the bus are written in the appropriate locations in the array element representing the PCI bus. As with the start and end memory addresses, the start and end I/O addresses and the interrupt assignment may also be the same as those used by the BIOS program when the system was initialized. 
     As represented by steps  518 ,  520 ,  522  and  524 , a repeated process or loop is next performed where each device number from 0 to 31 and function number from 0 to 7 is reviewed sequentially to determine whether such a device exists on the current bus and whether that device supports more than one function. At the first part of that loop, at step  518 , a standard PCI configuration access (query) is performed, which determines whether, for example, device 0, is present on the bus. If a device is located with that device number, the process continues to step  520  wherein the PCI configuration space information of that device is then read from that device including whether any other function numbers (0-7) are supported by the device. 
     Next, at step  522  memory space is allocated for the device information structure for that device and the PCI configuration information read from the device is then copied into the allocated device information structure. At step  524  that device information structure is linked into the list either by inserting a pointer into the corresponding bus information structure if this is the first device, or inserting the pointer into the next device location of the previous device information structure in the linked list for this bus. After step  524  is completed, the process returns to step  518  where the system may attempt to locate the next PCI device on the bus. This process or loop may be repeated for each device on the PCI bus. In this manner, a linked list of PCI devices with each element in the list containing configuration information is created in the form depicted in FIG.  4 . 
     After the last PCI device on the bus has been added to the linked list, the process proceeds to step  526 . In this step the last I/O address in the PCI bus information structure  422  (see FIG. 4) and the last memory address  420  in the PCI bus information structure are set, respectively, to the memory end  412  and the I/O end  416  addresses. 
     Next, in step  528 , the amount of memory and I/O address space used by all of the PCI devices on the bus may be determined. In one embodiment, the amount of memory and I/O address space used is determined by tracking the last memory and I/O address space assigned. The process for making those determinations is performed in steps  530  through  544 . Generally speaking, the process for determining the amount of memory an I/O address used by the PCI devices on the bus includes looking at each of the base address registers on each of the devices on the bus and determining the lowest base address register value for an I/O and the lowest base address register value for memory. 
     Specifically, at step  530 , the process locates the first device information structure on the bus by scanning the linked list attached to the bus information structure or, if the first device information structure has already been processed, the process looks for the next device information structure. If no device information structure is found, the process is complete. 
     When a device information structure is located at step  530 , then at step  534 , the data in the device information structure representing the first base address register is read. If the first base address register has already been read, the process attempts to read the next base address register. If no further base address registers exist, the process then returns to step  530 . 
     When a base register is found and read in step  534 , the process proceeds to the step represented by box  536 . Under the PCI configuration standard, if the low order bit of a base address register is set, then that base register represents an I/O address and the process then proceeds to step  540 . In step  540 , the base address register contents are masked with the hexadecimal number 0X FFFFFFFE (per the PCI specification) and a comparison is made between that value and the last I/O address in the bus information structure. If that masked value is a lower value, it is then written to the last I/O address in the bus information structure. The process then returns to step  534 . 
     However, if the low order bit in the base address register is not set, then the base address register represents a memory address and the process proceeds to step  538 . In step  538 , the contents of the base address register are masked with the hexadecimal number 0XFFFFFFF0 (per the PCI specification) and then compared with the contents of the last memory address in the bus information structure. If that masked value is a lower value, it is then written to the last memory address in the bus information structure. The process then returns to step  534 . 
     As represented by box  534 , this process is repeated for each of the base registers located on a device. After the last base address register has been analyzed according to steps  536 ,  538 ,  540 , the process returns to step  530  and the foregoing process is repeated for each device on the bus. This process thereby determines the lowest address for both I/O and memory used by the devices on the bus. The process proceeds in this manner because memory for the devices is allocated from the highest address to the lowest. After this has been completed, the PCI configuration initialization process is completed, 
     Turning now to FIG. 6, the aspects of the invention relating to its use in connection with the hot swap of a card or device on a PCI bus will be described. FIG. 6 represents the steps which are accomplished by the configuration manager  103  operating within the computer system. The following description of the process of a hot swap in a PCI bus system focuses on the details which relate directly to the configuration space. 
     As represented by box  610  in FIG. 6, the hot swap process is typically initiated by a system user request. The configuration manager may provide the driver with the information which defines the device to be swapped, such as the PCI bus number, the device number, the functions supported by the device, and identifies the slot in which the device resides. At step  612  the I/O to the card which is to be swapped out is suspended or frozen. Next, at step  614 , power to the slot holding the card to be swapped out is turned off. Then at step  616 , the user physically removes the card and replaces it with the replacement card. Next, at step  618 , the power to that slot is turned back on. 
     At step  620  the replacement card in the slot is queried to return the vendor identification and the device identification of the card installed in the slot using standard PCI configuration access known to those of ordinary skill in the art. 
     Next, at step  622 , the location of this card on the bus is located in the bus device information structure  404  (see FIG.  4 ). That is accomplished by locating the array element corresponding to the bus and then traversing the linked list linked to that array element until the PCI location (typically identified by bus number, device number and function number) corresponding to the current location of interest is located. Then, at step  624  the vendor identification and device identification which was read from the replacement card is compared to the vendor ID and device ID in the device information structure corresponding to the slot of interest. If those values are not the same, an improper swap has been attempted in that the replacement card is not identical to the card previously located in the slot. The system then proceeds to step  626  wherein power to that slot is turned off. The process then proceeds to step  628  wherein an error message is generated and the process terminates. 
     However, if the vendor identification and the device identification of the card currently located in the slot of interest and the vendor ID and device ID in the device information structure corresponding to that slot are identical, the process proceeds to step  630 . At step  630  the PCI configuration space information stored in the device information structure is written to the replacement device. Then, at step  632 , I/O to the slot is restarted. At that point, as represented by box  634 , the hot swap is completed. 
     Referring now to FIGS. 7A and 7B, the process for the hot addition of a device to the PCI bus will be described. The flowcharts represent the steps which may be accomplished by the configuration manager  103  operating within the computer system. Again, the description focuses upon those aspects of the hot addition which specifically relate to the PCI configuration space. 
     In general, the process for performing a hot add is similar to the steps that occur with regard to each device on a bus during system initialization associated with boot-up. However, generally speaking, the process differs in that rather than initializing every device in the system, the capability exists to initialize any device because configuration information is available and maintained in the PCI configuration space by the configuration manager. 
     As represented by step  710 , the power to the slot of interest should be turned off and the card to be added is then inserted into that slot. Next, at step  712 , the memory structure represented in FIG. 4 is reviewed to determine whether the PCI location representing the slot into which the card was added is already identified in that structure. If the answer is yes, the process continues to step  713  wherein a system error message is initiated. However, because that slot was empty, no entry for that slot should be present in the memory structure. Therefore, typically step  714  would be performed next. At step  714  power is typically restored to the slot of interest. Next, at step  716 , the card is initialized. The individual steps for this process are represented by boxes  720  through  786 . 
     First, at step  720 , a system query is sent to attempt to locate or read the newly added device. If the device cannot be read by the system, the process continues to step  722 , wherein the power to that slot is turned off. Next, at step  724 , an error message is generated and the process ends. 
     However, if the device is located in response to the system query, the process proceeds to step  725 , wherein, memory space is allocated for what will be the device information structure for the newly added device. Next, at step  726 , the configuration information that is presently stored on the device is read. Typically, this information includes the vendor identification, and the amounts and types of memory required by the device. At step  728  that information is written to the allocated memory location allocated in step  725 . 
     Next, as represented generally by box  728 , the base address registers of the device are programmed. Specifically, at step  730 , the first base address register is read in accordance with the PCI specification. This may be accomplished by writing FFFFFFFF to the base address register and then reading the base address register. Next, at step  732 , if no base address registers remain (i.e., if all of the base address registers have already been read), the system continues on to the sequence of steps beginning at point A. However, when the base address register is being read, the process continues to step  734 . 
     At step  734 , if the low order bit of the base register is set (equals 1) then that base address register represents an I/O address and the process continues to the series of steps beginning with step  752  and continuing on FIG. 7B which are described below. Alternatively, if the lower order bit is not set, the base address register is a memory base address register and the system proceeds to step  736 . 
     At step  736 , the four low order bits from the base address register are masked as a preliminary step to determining the size of the memory required by the base address register. The determination of the amount of memory required by the base address register is commonly known to those of ordinary skill in the art as part of the standards of the PCI bus architecture and is therefore only outlined here. 
     Next, at step  738 , the amount of memory required by the base address register is determined. Then, at step  740  the memory assignment for the base address register is determined with reference to the last memory address  420  in the bus information structure. 
     Next, as represented by box  742 , after the memory assignment for the base address register is determined, then that memory assignment is compared to the memory start address  410  stored in the PCI bus information structure for that bus to ensure that the memory being assigned to that base address register is within the range allocated for devices on that bus. Then, in steps  746 ,  748  and  750 , the proper value is written to the base address register according to the sequence of steps defined by the PCI specification. 
     Specifically, in step  746 , the memory assignment for the base address register is written to the base address register. Then, at step  748 , the base address register is read and at step  750 , that value is used to set the memory last  420  (see FIG. 4) in the PCI bus information structure. As those of ordinary skill will recognize, reads to and writes from the base address register sometimes involve masking of selected bits as specified by the PCI bus standard. After step  750  has been completed, the process returns to step  730 . 
     If the base address register had the lower order bit set at step  734 , indicating that the base address register was for I/O, not memory, then the process proceeds to the series of steps box  752  which are set forth in FIG. 7B which will now be described. 
     At step  754  in FIG. 7B, the number stored in the base address register is read and the low order bit is masked. Next, at step  756 , from that information the amount of I/O required by the base address register is determined according to the PCI specification, as is apparent to those of ordinary skill in the art. 
     Next, at step  760 , the I/O assignment for the base address register is determined by using the last I/O address  422  (see FIG. 2) stored in the PCI bus information structure and the amount of I/O required by the base address register. Next, at step  764 , a comparison is made to ensure that the I/O assignment given to the base address register does not fall outside the range of I/O allocated to devices on this bus. If it does, the process cannot be completed. 
     Then, at steps  768  and  770 , according to the PCI specification, the I/O assignment for the base address register is written to the base address register. First, at step  768 , the memory assignment is written to the base address register. Then, at step  770 , the base address register is read. Next, at step  772 , the information read from the base address register is used to set the last I/O  422  in the PCI bus information structure (see FIG.  4 ). 
     After the base address register has been programmed, the process returns to step  730  to read the next base address register. At step  732 , if no further base address registers are present, the system next executes steps  774  through  786  in FIG.  7 A. 
     First, at step  774 , the device interrupt line is programmed with the proper ISA IRQ corresponding to the bus number. This information is stored as part of the PCI bus information structure. Next, at step  776 , the device latency timer is programmed with a predefined value and at step  778 , the device command register is also programmed with a predefined value. 
     Then, at step  782 , the device PCI configuration information is read from the device and then written into the device information structure. Finally, at step  784 , the created device information structure is inserted into the linked list associated with the bus which completes the process. 
     The invention may be embodied in other specific forms and arrangements without departing from its spirit or essential characteristics. For example, the information required to initialize a device being hot added can be maintained in a template. The template may be based upon the configuration information of an adapter of the same type located on a reference system. After following the traditional initialization process of configuring the reference system which includes some or all the devices on some or all the buses, the configuration information for each bus and each device in each bus slot is stored in memory. That information is used to build a template which is then used to supply the configuration information when a device is hot added. However, such a system requires that devices which are hot added can only be the identical type and in the same location as in the reference system. 
     Additionally, the memory structure can be in forms other than an array with linked lists, such as a table. The invention may also be applied to various bus architectures such as CardBus, Microchannel, Industrial Standard Architecture (ISA), and Extended ISA (EISA) and used with various operating systems such as Windows® NT. The application to other various architectures and operating systems will require that the method and system account for the specific requirements of those systems such as memory allocation and configuration information as will be recognized by those of ordinary skill in the art. 
     The invention has been shown and described with respect to particular embodiments. However, it will be understood by those skilled in the art that various changes may be made therein without departing from the spirit and scope of the invention. The scope of the invention is indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope. 
     
       
         
               
             
               
               
               
             
           
               
                 APPENDIX A 
               
             
             
               
                   
               
               
                 Incorporation by Reference of Commonly Owned Applications 
               
               
                 The following patent applications, commonly owned and filed October 1, 1997, 
               
               
                 are hereby incorporated herein in their entirety by reference thereto: 
               
             
          
           
               
                 Title 
                 Application No. 
                 Attorney Docket No. 
               
               
                   
               
               
                 “System Architecture for Remote Access 
                 08/942,160 
                 MNFRAME.002A1 
               
               
                 and Control of Environmental 
               
               
                 Management” 
               
               
                 “Method of Remote Access and Control of 
                 08/942,215 
                 MNFRAME.002A2 
               
               
                 Environmental Management” 
               
               
                 “System for Independent Powering of 
                 08/942,410 
                 MNFRAME.002A3 
               
               
                 Diagnostic Processes on a Computer 
               
               
                 System” 
               
               
                 “Method of Independent Powering of 
                 08/942,320 
                 MNFRAME.002A4 
               
               
                 Diagnostic Processes on a Computer 
               
               
                 System” 
               
               
                 “Diagnostic and Managing Distributed 
                 08/942,402 
                 MNFRAME.005A1 
               
               
                 Processor System” 
               
               
                 “Method for Managing a Distributed 
                 08/942,448 
                 MNFRAME.005A2 
               
               
                 Processor System” 
               
               
                 “System for Mapping Environmental 
                 08/942,222 
                 MNFRAME.005A3 
               
               
                 Resources to Memory for Program Access” 
               
               
                 “Method for Mapping Environmental 
                 08/942,214 
                 MNFRAME.005A4 
               
               
                 Resources to Memory for Program Access” 
               
               
                 “Hot Add of Devices Software 
                 08/942,309 
                 MNFRAME.006A1 
               
               
                 Architecture” 
               
               
                 “Method for The Hot Add of Devices” 
                 08/942,306 
                 MNFRAME.006A2 
               
               
                 “Hot Swap of Devices Software 
                 08/942,311 
                 MNFRAME.006A3 
               
               
                 Architecture” 
               
               
                 “Method for The Hot Swap of Devices” 
                 08/942,457 
                 MNFRAME.006A4 
               
               
                 “Method for the Hot Add of a Network 
                 08/943,072 
                 MNFRAME.006A5 
               
               
                 Adapter on a System Including a 
               
               
                 Dynamically Loaded Adapter Driver” 
               
               
                 “Method for the Hot Add of a Mass 
                 08/942,069 
                 MNFRAME.006A6 
               
               
                 Storage Adapter on a System Including a 
               
               
                 Statically Loaded Adapter Driver” 
               
               
                 “Method for the Hot Add of a Network 
                 08/942,465 
                 MNFRAME.006A7 
               
               
                 Adapter on a System Including a Statically 
               
               
                 Loaded Adapter Driver” 
               
               
                 “Method for the Hot Add of a Mass 
                 08/962,963 
                 MNFRAME.006A8 
               
               
                 Storage Adapter on a System Including a 
               
               
                 Dynamically Loaded Adapter Driver” 
               
               
                 “Method for the Hot Swap of a Network 
                 08/943,078 
                 MNFRAME.006A9 
               
               
                 Adapter on a System Including a 
               
               
                 Dynamically Loaded Adapter Driver” 
               
               
                 “Method for the Hot Swap of a Mass 
                 08/942,336 
                 MNFRAME.006A10 
               
               
                 Storage Adapter on a System Including a 
               
               
                 Statically Loaded Adapter Driver” 
               
               
                 “Method for the Hot Swap of a Network 
                 08/942,459 
                 MNFRAME.006A11 
               
               
                 Adapter on a System Including a Statically 
               
               
                 Loaded Adapter Driver” 
               
               
                 “Method for the Hot Swap of a Mass 
                 08/942,458 
                 MNFRAME.006A12 
               
               
                 Storage Adapter on a System Including a 
               
               
                 Dynamically Loaded Adapter Driver” 
               
               
                 “Method of Performing an Extensive 
                 08/942,463 
                 MNFRAME.008A 
               
               
                 Diagnostic Test in Conjunction with a 
               
               
                 BIOS Test Routine” 
               
               
                 “Apparatus for Performing an Extensive 
                 08/942,163 
                 MNFRAME.009A 
               
               
                 Diagnostic Test in Conjunction with a 
               
               
                 BIOS Test Routine” 
               
               
                 “Configuration Management Method for 
                 08/941,268 
                 MNFRAME.010A 
               
               
                 Hot Adding and Hot Replacing Devices” 
               
               
                 “Apparatus for Interfacing Buses” 
                 08/942,382 
                 MNFRAME.012A 
               
               
                 “Method for Interfacing Buses” 
                 08/942,413 
                 MNFRAME.013A 
               
               
                 “Computer Fan Speed Control Device” 
                 08/942,447 
                 MNFRAME.016A 
               
               
                 “Computer Fan Speed Control Method” 
                 08/942,216 
                 MNFRAME.017A 
               
               
                 “System for Powering Up and Powering 
                 08/943,076 
                 MNFRAME.018A 
               
               
                 Down a Server” 
               
               
                 “Method of Powering Up and Powering 
                 08/943,077 
                 MNFRAME.019A 
               
               
                 Down a Server” 
               
               
                 “System for Resetting a Server” 
                 08/942,333 
                 MNFRAME.020A 
               
               
                 “Method of Resetting a Server” 
                 08/942,405 
                 MNFRAME.021A 
               
               
                 “System for Displaying Flight Recorder” 
                 08/942,070 
                 MNFRAME.022A 
               
               
                 “Method of Displaying Flight Recorder” 
                 08/942,068 
                 MNFRAME.023A 
               
               
                 “Synchronous Communication Interface” 
                 08/943,355 
                 MNFRAME.024A 
               
               
                 “Synchronous Communication Emulation” 
                 08/942,004 
                 MNFRAME.025A 
               
               
                 “Software System Facilitating the 
                 08/942,317 
                 MNFRAME.026A 
               
               
                 Replacement or Insertion of Devices in a 
               
               
                 Computer System” 
               
               
                 “Method for Facilitating the Replacement 
                 08/942,316 
                 MNFRAME.027A 
               
               
                 or Insertion of Devices in a Computer 
               
               
                 System” 
               
               
                 “System Management Graphical User 
                 08/943,357 
                 MNFRAME.028A 
               
               
                 Interface” 
               
               
                 “Display of System Information” 
                 08/942,195 
                 MNFRAME.029A 
               
               
                 “Data Management System Supporting Hot 
                 08/942,129 
                 MNFRAME.030A 
               
               
                 Plug Operations on a Computer” 
               
               
                 “Data Management Method Supporting 
                 08/942,124 
                 MNFRAME.031A 
               
               
                 Hot Plug Operations on a Computer” 
               
               
                 “Alert Configurator and Manager” 
                 08/942,005 
                 MNFRAME.032A 
               
               
                 “Managing Computer System Alerts” 
                 08/943,356 
                 MNFRAME.033A 
               
               
                 “Computer Fan Speed Control System” 
                 08/940,301 
                 MNFRAME.034A 
               
               
                 “Computer Fan Speed Control System 
                 08/941,267 
                 MNFRAME.035A 
               
               
                 Method” 
               
               
                 “Black Box Recorder for Information 
                 08/942,381 
                 MNFRAME.036A 
               
               
                 System Events” 
               
               
                 “Method of Recording Information System 
                 08/942,164 
                 MNFRAME.037A 
               
               
                 Events” 
               
               
                 “Method for Automatically Reporting a 
                 08/942,168 
                 MNFRAME.040A 
               
               
                 System Failure in a Server” 
               
               
                 “System for Automatically Reporting a 
                 08/942,384 
                 MNFRAME.041A 
               
               
                 System Failure in a Server” 
               
               
                 “Expansion of PCI Bus Loading Capacity” 
                 08/942,404 
                 MNFRAME.042A 
               
               
                 “Method for Expanding PCI Bus Loading 
                 08/942,223 
                 MNFRAME.043A 
               
               
                 Capacity” 
               
               
                 “System for Displaying System Status” 
                 08/942,347 
                 MNFRAME.044A 
               
               
                 “Method of Displaying System Status” 
                 08/942,071 
                 MNFRAME.045A 
               
               
                 “Fault Tolerant Computer System” 
                 08/942,194 
                 MNFRAME.046A 
               
               
                 “Method for Hot Swapping of Network 
                 08/943,044 
                 MNFRAME.047A 
               
               
                 Components” 
               
               
                 “A Method for Communicating a Software 
                 08/942,221 
                 MNFRAME.048A 
               
               
                 Generated Pulse Waveform Between Two 
               
               
                 Servers in a Network” 
               
               
                 “A System for Communicating a Software 
                 08/942,409 
                 MNFRAME.049A 
               
               
                 Generated Pulse Waveform Between Two 
               
               
                 Servers in a Network” 
               
               
                 “Method for Clustering Software 
                 08/942,318 
                 MNFRAME.050A 
               
               
                 Applications” 
               
               
                 “System for Clustering Software 
                 08/942,411 
                 MNFRAME.051A 
               
               
                 Applications” 
               
               
                 “Method for Automatically Configuring a 
                 08/942,319 
                 MNFRAME.052A 
               
               
                 Server after Hot Add of a Device” 
               
               
                 “System for Automatically Configuring a 
                 08/942,331 
                 MNFRAME.053A 
               
               
                 Server after Hot Add of a Device” 
               
               
                 “Method of Automatically Configuring and 
                 08/942,412 
                 MNFRAME.054A 
               
               
                 Formatting a Computer System and 
               
               
                 Installing Software” 
               
               
                 “System for Automatically Configuring 
                 08/941,955 
                 MNFRAME.055A 
               
               
                 and Formatting a Computer System and 
               
               
                 Installing Software” 
               
               
                 “Determining Slot Numbers in a 
                 08/942,462 
                 MNFRAME.056A 
               
               
                 Computer” 
               
               
                 “System for Detecting Errors in a Network” 
                 08/942,169 
                 MNFRAME.058A 
               
               
                 “Method of Detecting Errors in a Network” 
                 08/940,302 
                 MNFRAME.059A 
               
               
                 “System for Detecting Network Errors” 
                 08/942,407 
                 MNFRAME.060A 
               
               
                 “Method of Detecting Network Errors” 
                 08/942,573 
                 MNFRAME.061A