Abstract:
An apparatus and method for counting the number of cycles of a sensor signal and of a reference signal that occur during respective time intervals associated with a sampling interval defined by a sample signal. Sensor and reference gate signals are produced and respectively define sensor and reference intervals. The sensor interval begins and ends synchronously with respect to the sensor signal, and the reference interval begins and ends synchronously with respect to the reference signal. The sensor, reference and sampling intervals are approximately coextensive with one another. Cycles of the sensor and reference signals are counted during the sensor and reference intervals, respectively. The process may be repeated for a plurality of successive sampling intervals.

Description:
TECHNICAL FIELD 
     This invention relates to techniques for sampling the frequency of an input signal and for producing corresponding digital output signals. 
     BACKGROUND OF THE INVENTION 
     A common type of instrument is one in which a sensor produces a signal whose frequency is related in some functional way, often nonlinear, to a physical input variable. In order to use such a sensor in a digital system, the frequency of the sensor signal must be converted into a series of digital samples. The most versatile systems for measuring frequency operate either by counting cycles of the sensor or input signal for a known time interval, or by counting cycles of a reference signal for an interval controlled by the sensor signal. Using either technique, the resolution of such a frequency measurement depends on the number of counts that can be accumulated during the counting or sampling interval. The resolution may therefore be very poor at high sampling rates. 
     For wideband sensors such as accelerometers, sampling rates must often be much greater than would otherwise be required by system bandwidth requirements, in order to avoid errors due to frequency aliasing and input rectification. However, if resolution cannot be improved by digital low pass filtration, i.e., by averaging, substantial errors may be introduced by using high sample rates. With conventional frequency counting techniques counts are lost between adjacent sampling intervals, because the counters are reset for each sample. Therefore, with conventional frequency sampling methods, averaging several samples usually does not significantly improve the resolution. 
     SUMMARY OF THE INVENTION 
     The present invention provides a method and apparatus for counting the cycles of a sensor signal and of a reference signal in such a way that no sensor of reference counts are lost. The counting technique of the present invention therefore permits resolution to be improved by averaging counts over a plurality of succesive sampling intervals. 
     A preferred embodiment of an apparatus according to the present invention comprises gating means, sensor count means, and reference count means. A sample signal is provided that is operative to define a sampling interval. The gating means is responsive to the sensor, reference and sample signals to produce a sensor gate signal and a reference gate signal. The sensor gate signal has a characteristic that is operative to define a sensor interval that begins and ends synchronously with respect to the sensor signal. The reference gate signal has a characteristic that is operative to define a reference interval that begins and ends synchronously with respect to the reference signal. The sensor, reference and sample intervals are approximately coextensive with one another. The sensor count means counts the numbers of cycles of the sensor signal that occur during the sensor interval, and the reference count means counts the number of cycles of the reference signal that occur during the reference interval. The relationship of the frequency of the sensor signal to the frequency of the reference signal may thereby be determined. 
     In a preferred method according to the present invention, a sensor gate signal and a reference gate signal are produced in response to the sample, sensor and reference signals. The sensor and reference gate signals have characteristics that are operative to define the sensor and reference intervals respectively, and the sensor and reference signals are respectively counted during such sensor and reference intervals. 
     In a further embodiment, the present invention comprises a sensor for producing a sensor signal having a frequency that corresponds to an input variable, means for producing the reference and sample signals, counting means for counting the number of cycles of the sensor and reference signals that occur during respective time intervals associated with the sampling interval and for producing corresponding digital sensor and reference count signals, and processor means for receiving the sensor and reference count signals and determining therefrom the value of the input variable. The processor means may be operative to average values associated with the sensor and reference count signals over successive sampling intervals. 
     These and other features and advantages of the invention will become apparent in the detailed description and claims to follow, taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a device that includes a counting circuit according to the present invention. 
     FIG. 2 is a block diagram of a counting circuit according to the present invention. 
     FIG. 3 is a circuit diagram of the counting circuit of FIG. 2. 
     FIG. 4 is a timing diagram corresponding to the counting circuit of FIG. 3. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring initially to FIG. 1, an instrument or device is shown that includes a counting circuit according to the present invention. The instrument includes sensor 12 that produces an output signal F S  whose frequency is a function of the variable sensed or measured by the sensor. It is desired to sample the value of this variable by converting the frequency of F S  into a series of digital signals usable by a data processing system comprising CPU 20. The conversion is carried out by counting circuit 10 of the present invention. The inputs to counting circuit 10 include sensor signal F S , a SAMPLE signal, and a reference signal F R . The SAMPLE signal defines a series of successive sampling intervals. During time periods associated with each sampling interval, counting circuit 10 counts the cycles of sensor signal F S  and of reference signal F R . At the end of the respective time periods, the accumulated counts are stored. During the next sampling interval, counting circuit 10 outputs digital signals corresponding to the stored counts onto system bus 18. The digital signals are utilized by CPU 20 to determine the value of the variable sensed by sensor 12. As discussed below, CPU 20 may also average values corresponding to successive sampling intervals to improve resolution. 
     Reference signal F R  preferably comprises a periodic signal that has a frequency higher than that of sensor signal F S . In the embodiment of FIG. 1, F R  is a comparatively high frequency square wave signal provided by clock 14, and is asynchronous with respect to sensor signal F S . The SAMPLE signal is a comparatively low frequency signal that operates to define the sampling intervals. In the embodiment shown in FIG. 1, SAMPLE is derived from F R  by means of Divide by N Circuit 16, such that SAMPLE consists of a comparatively low frequency square wave signal. In the embodiment illustrated herein, each complete cycle of the SAMPLE signal defines one sampling interval, and the end of one sampling interval and the beginning of the next sampling interval corresponds to the rising edges of the SAMPLE pulses. Representative waveforms for F S , F R  and SAMPLE are shown in FIG. 4. It will be understood that it is not necessary to derive SAMPLE from F R , and that SAMPLE may in general be asynchronous with respect to both F S  and F R , and may have a form other than the square wave shown in FIG. 4. 
     Referring now to FIG. 2, a preferred embodiment of counting circuit 10 is shown comprising gating circuit 30, sensor count circuit 32, and reference count circuit 34. The sensor signal F S  is input to gating circuit 30 and to sensor count circuit 32. Similarly, reference signal F R  is input to gating circuit 30 and to reference count circuit 34. Gating circuit 30 also receives the SAMPLE signal. Referring again to FIG. 4, time interval T 1  is defined to be the interval between successive leading edges of the SAMPLE signal. Gating circuit 30 produces output signals GATE S  and GATE R  that operate to define the time intervals during which cycles of F S  and F R  respectively will be counted. In the illustrated embodiment, GATE S  follows SAMPLE on the falling edges of F S . GATE S  therefore comprises a comparatively low frequency, square wave signal that has a period approximately coextensive with time interval T 1 . However, GATE S  is shifted in time with respect to the SAMPLE signal such that GATE S  is synchronous with sensor signal F S . In a similar fashion, GATE R  follows GATE S  on the falling edges of F R . GATE R  therefore comprises a comparatively low frequency, square wave signal having a period that is also approximately coextensive with time interval T 1 . However, GATE R  is shifted in time with respect to the SAMPLE signal such that GATE R  is synchronous with reference signal F R . Thus GATE S  defines a time interval T 2  that is approximately coextensive with time interval T 1 , but that is synchronous with sensor signal F S , and GATE R  defines a time interval T 3  that is approximately coextensive with time intervals T 1  and T 2 , but that is synchronous with reference signal F R . In particular, time intervals T 1  and T 2  are coextensive within ±1 cycle of F S , and time intervals T 2  and T 3  are coextensive within ±1 cycle of F R . 
     It is to be understood that GATE S  and GATE R  may each comprise one or more separate signals, and may comprise waveforms other than those shown in FIG. 4, so long as the total GATE S  and GATE R  signals have characteristics that are operative to define appropriate time intervals T 2  and T 3 . 
     Referring again to FIG. 2, sensor count circuit 32 receives signals F S  and GATE S , and responds by counting the number of cycles of F S  that occur during the time interval T 2  defined by signal GATE S . In the particular embodiment illustrated, sensor count circuit 32 counts the number of cycles of F S  that occur during each complete cycle of signal GATE S . At each rising edge of GATE S , the current count of F S  cycles is stored, and a new count is commenced. At any convenient time during the succeeding T 2  time interval, an output enable signal on line 36 causes sensor count circuit 32 to output the stored count F S  cycles from the previous T 2  time interval onto system bus 18. The output enable signal on line 36 may be provided by any convenient means, such as by CPU 20 (FIG. 1). 
     Reference count circuit 34 operates in a manner similar to sensor count circuit 32. During each time period T 3  defined by signal GATE R , reference count circuit 34 counts the number of cycles of reference signal F R . In particular, reference count circuit 34 counts the number of cycles of F R  that occur during each complete cycle of signal GATE R . At each rising edge of GATE R , the current count of F R  cycles is stored, and a new count is begun. The stored count may then by retrieved at any time during the next T 3  time interval by providing an output enable signal on line 38. In response to such an output enable signal, reference count circuit 34 places the stored count F R  cycles from the previous T 3  time interval onto system bus 18. The output enable signals on line 36 and 38 are of course coordinated so that they occur sequentially rather than simultaneously. 
     Referring now to FIG. 3, a detailed embodiment of the present invention is illustrated. Gating circuit 30 comprises flip-flop 52, flip-flop 54, and inverters 56 and 58. Each flip-flop 52 and 54 is operative to transfer the signal (high or low) at its D input to its Q output at each rising edge of the signal at its CK input. As may be appreciated by reference to FIG. 4, the result of the arrangement of flip-flop 52 and inverter 56 is that signal GATE S , produced at the Q output of flip-flop 52, will tend to follow the SAMPLE signal at the D input of flip-flop 52, but GATE S  will only change to follow SAMPLE at the falling edges of F S , such changes occuring at the falling rather than therising edges of F S  due to inverter 56. In a similar manner, flip-flop 54 and inverter 58 will cause GATE R  to follow GATE S , but GATE R  will only change to follow GATE S  at the falling edges of F R . The result of this arrangement will therefore be the wareforms shown in FIG. 4 for SAMPLE, GATE S  and GATE R . Since F S  is asynchronous with respect to SAMPLE, GATE S  will lag SAMPLE by a variable delay which may range from the response time of flip-flop 52 up to one full cycle of F S . Similarly, since F R  is asynchronous with respect to F S , GATE R  will lag GATE S  by a variable delay which may range from the response time of flip-flop 54 up to one full cycle of F R . 
     Still referring to FIG. 3, sensor count circuit 32 comprises counter 62, latch 64, initial value circuit 66, NAND gate 68 and flip-flop 70. Sensor signal F S  is input directly to the clock input (CK) of counter 62, and counter 62 responds by incrementing an internally stored count at each rising edge of F S . As will be described below, the accumulated count in counter 62 is transferred to latch 64 at the beginning of each time interval T 2 , and counter 62 is then reinitialized from initial value circuit 66. During the succeeding time interval T 2 , an output enable signal on line 36 causes latch 64 to place its stored count for the previous T 2  time interval onto system bus 18. 
     The two inputs to NAND gate 68 are GATE S  and the signal on line 72 which originates at the Q output of flip-flop 70. The D and CK inputs to filp-flop 70 are GATE S  and F S , respectively. At each rising edge of F S , output Q of flip-flop 70 assumes a state (high or low) opposite to that of signal GATE S . Referring to FIG. 4, the result will be that prior to GATE S  going high, signal LOAD S  at the output of NAND gate 68 will be high because one of the NAND inputs (GATE S ) is low. The other input to the NAND gate, the signal on line 72, will be high at this time, because several low-to-high transitions of F S  have occurred since GATE S  went low. When GATE S  then goes high at the beginning of time interval T 2 , the signal on line 72 will remain high until the next rising edge of F S , i.e., for one-half cycle of F S . During this half cycle, both NAND inputs will be high, and the NAND output signal LOAD S  will therefore be low, as indicated in FIG. 4. LOAD S  is input into the load input (LD) of counter 62. Counter 62 is a conventional binary or decade counter that is operative to load the values specified by input value circuit 66 when the LD of the counter goes high. In the embodiment shown in FIG. 3, initial value circuit 66 connects the low order line of bus 74 to a high voltage through an appropriate resistor, and connects all other lines of bus 74 to a low voltage, thus supplying a initial count of +1. Therefore, one-half cycle (of F S ) after GATE S  goes high, counter 62 will be loaded with the initial value +1. Counter 62 will then proceed to increment its stored count by 1 each subsequent time that F S  goes high. An initial value of +1 (rather than zero) is supplied to counter 62 because the first low to high transition of F S  occurs one half cycle after GATE S  goes high, at the same time or very slightly before LOAD S  goes high. The first low to high transition of F S  will therefore be missed by counter 62, such missed count being compensated for by the +1 value supplied by initial value circuit 66. At the end of time interval T 2 , when GATE S  again goes high, the low-to-high transition at the CK input of latch 64 will cause the latch to store the accumulated count in counter 62. 
     Reference count circuit 34 comprises counter 82, latch 84, initial value circuit 86, NAND gate 88 and flip-flop 90. The operation of the reference count circuit is very similar to that of sensor count circuit 32. Reference signal F R  is input directly to the clock input (CK) of counter 82, and counter 82 responds by incrementing an internally stored count at each rising edge of F R . As will be described below, the accumulated count in counter 82 is transferred to latch 84 at the beginning of each time interval T 3 , and counter 82 is then reinitialized from initial value circuit 86. During the succeeding time interval T 3 , an output enable signal on line 38 causes latch 84 to place its stored count for the previous T 3  time interval onto system bus 18. 
     The two inputs to NAND gate 88 are GATE R  and the signal on line 92 which originates at the Q output of flip-flop 90. The D and CK inputs to flip-flop 90 are GATE R  and F R , respectively. At each rising edge of F R , output Q of flip-flop 90 will assume a state (high or low) opposite to that of signal GATE R . Referring to FIG. 4, the result will be that prior to GATE R  going high, signal LOAD R  at the output of NAND gate 88 will be high, because one of the NAND inputs (GATE R ) is low. The other input to the NAND gate, the signal on line 92, will be high at this time, because several low-to-high transitions of F R  have occurred since GATE R  went low. When GATE R  then goes high at the beginning of time interval T 3 , the signal on line 92 will remain high until the next rising edge of F R , i.e., for one-half cycle of F R . During this half cycle, both NAND inputs will be high, and the NAND output signal LOAD R  will therefore be low, as indicated in FIG. 4. LOAD R  is input into the load input (LD) of counter 82. Counter 82 is a conventional binary or decade counter that is operative to load the values specified by input value circuit 86 when the LD input of the counter goes high. In the embodiment shown in FIG. 3, initial value circuit 86 connects the low order line of bus 94 to a high voltage through an appropriate resistor, and connects all other lines of bus 94 to a low voltage, thus supplying an initial count of +1. Therefore, one-half cycle (of F R ) after GATE R  goes high, counter 82 will be loaded with the initial value +1. Counter 82 will then proceed to increment its stored count by 1 each subsequent time that F R  goes high. An initial value of +1 (rather than zero) is supplied to counter 82 because the first low to high transition of F R  occurs one-half cycle after GATE R  goes high, at the same time or very slightly before LOAD R  goes high. The first low to high transition of F R  will therefore be missed by counter 82, such missed count being compensated for by the +1 value supplied by initial value circuit 86. At the end of time interval T 3 , when GATE R  again goes high, the low-to-high transition at the clock input of latch 84 will cause the latch to store the accumulated count in counter 82. 
     In an instrument of the general type shown in FIG. 1 in which a conventional counting circuit is used, the resolution of the system generally cannot be improved by averaging the counts or frequencies over a number of sampling intervals. The reason that averaging does not improve resolution is that in conventional counting circuits, the counters are reset at the end of a fixed sampling interval. Since the sensor and reference signals are asynchronous, the result is that partial counts of either the sensor signal or the reference signal are lost. The present invention provides a technique for avoiding the loss of partial counts, allowing a significant improvement in system resolution through averaging. 
     The advantages of the present invention can be illustrated by means of the following calculations. Let n and m be the number of sensor and reference pulses respectively accumulated for one sampling interval. If f s  and f r  are the frequencies of signals F S  and F R  respectively, then the measured sensor frequency f sm  is: ##EQU1## Assuming that f r  is larger than f s , the asynchronous relationship between F S  and F R  means that for each sampling interval, there is an error uncertainty Δm in the value of m, with Δm being in the range -1 to +1. The relationship between f r  and the true sensor frequency f s  is therefor: ##EQU2## By combining equations (1) and (2), one obtains: ##EQU3## The k-th moment E{(Δm) k  } of the error Δm is given by: ##EQU4## since Δm has a uniform probability density in the range -1 to +1. We obtain E{Δm }=0 and E{(Δm) 2  }=1/3. If sensor 12 is, for example, an accelerometer for measuring acceleration a, and if there is a linear 
     relationship between acceleration a and frequency f s  such that: 
     
         a=A.sub.1 f.sub.s +A.sub.0                                 (5) 
    
     then the measured acceleration a m  can be written: 
     
         a.sub.m =a +Δa                                       (6) 
    
     where Δa=A 1  f s  Δm/m is the resolution error due to sampling. Thus the resolution error can be reduced by making m large, i.e., by lengthing the sampling period or by increasing the reference frequency f r . The resolution can also, however, be improved by averaging over several samples. The reason that averaging can improve resolution is that the counting circuit of the present invention does not lose any counts between sampling intervals, and thus, for example, a partial F R  cycle not counted in one sampling interval will be counted during the next sampling interval. The total count for a succession of sampling intervals will therefore be correct, and resolution can be significantly improved by averaging. In the limit of an infinite number of samples to be averaged, the resolution error for the linear sensor modeled by equation 5 will be zero, since: ##EQU5## and E{Δm}=0. 
     For a nonlinear relationship between acceleration and frequency, such as a quadratic relationship of the form: 
     
         a=A.sub.1 f.sub. s.sup.2 +A.sub.0                          (8) 
    
     the resolution error Δa in equation (6) becomes: ##EQU6## Since E{(Δm) 2  }=1/3, the resolution error for the limiting case of an infinite number of samples will be: ##EQU7## For most practical instruments, however, the resolution error indicated by equation (10) will be extremely small. 
     While the preferred embodiments of the invention have been illustrated and described, it should be understood that variations will become apparent to those skilled in the art. Accordingly, the invention is not to be limited to the specific embodiments illustrated and described, and the true scope and spirit of the invention are to be determined by reference to the following claims.