Abstract:
A technique is provided for an electrical device to automatically detect one of a plurality of interface standards to operate in accordance with. More particularly, a direct access arrangement (DAA) for communicating with telephone lines is provided for utilization with modem communications over a phone line. The DAA may be configured to automatically detect and operate in accordance with a plurality of interface standards for communications to a host system. For example, the DAA may detect that communications are to be provided in accordance with the AC-97 interface standard or the Azalia interface standard. In one embodiment, a clock signal may be monitored to determine the proper interface mode. In another embodiment, the automatic detection of the proper interface mode may be accomplished by monitoring the data presented to the DAA through the interface standard.

Description:
TECHNICAL FIELD OF THE INVENTION 
   This invention relates generally to techniques for connecting to communication networks and more particularly to circuits utilized to connect modems to telephone line networks. 
   BACKGROUND 
   Direct access arrangement (DAA) circuitry is often utilized to connect electrical systems to telephone networks such as the POTS network. Thus, the DAA circuitry provides the necessary circuitry that enables communication between an electrical system and the standard two wire phone line. 
   As shown in  FIG. 1 , DAA circuitry  100  is utilized provide a communication channel from the TIP and RING phone lines  110  and a host system  114 . The host system  114  may be any of a wide range of electrical systems, and may be for example, a personal computer, a laptop computer, a set-top box, or other electrical devices. The DAA circuitry  100  may include an isolation barrier  106 . The isolation barrier  106  provides the electrical isolation required by various governmental standards for isolation between the telephone line network and electrically powered circuitry. Example isolation barriers may include for example, capacitors, transformers, opto-couplers and/or any other devices that provide the required isolation. The DAA circuitry may also include system side circuitry  102  and line side circuitry  104 . The system side circuitry may include integrated circuits and/or discrete devices that are located on the system side of the isolation barrier  106 . The line side circuitry may include integrated circuits and/or discrete devices that are located on the telephone line side of the isolation barrier  106 . Exemplary prior art DAA circuitry is shown in U.S. Pat. Nos. 6,385,235 and 6,304, 597, the disclosures of which are each incorporated herein by reference. 
   The system side circuitry  102  may communicate with the host system  114  through a communication interface  116 . The communication interface  116  may provide data and control information between the host system  114  and the DAA circuitry  100 . In one exemplary application, the host system may include dedicated modem hardware. Such modem hardware provides the necessary modem data processing to communicate data from a host system across a phone line. In another exemplary application the host system may include a “soft” modem. A soft modem is implemented by utilizing system hardware resources (such the CPU of a personal computer) in conjunction with modem software that runs on the host system in order to provide the necessary modem functionality. In another exemplary application, the modem functionality may be performed within the system side circuitry  102 . 
   No matter what type of modem is implemented, the DAA circuitry generally must be configured in a manner such that it is compatible with the communication interface standard utilized by the host system  114 . Exemplary communication interface standards that the communication interface  116  may be in compliance with include for the Peripheral Component Interconnect (PCI) standard, the AC-97 standard, the Azalia standard, and others interfaces. The PCI standard is a common I/O bus standard that is well known in the art that provides a shared data path between processors and peripheral controllers. To provide a standard interface for computer system audio applications, Intel Corporation has sponsored the Audio Code &#39;97 (AC-97) Component Specification. Note that, as used here, AC-97 operational specifications include the current AC-97 operational specifications and any revisions or updates to those specifications, as well as any follow-on specifications that incorporate features of the current AC-97 operational specifications. The Audio CODEC &#39;97 Component Specification, revision 2.1 (May 22, 1998) is hereby incorporated by reference in its entirety. The AC-97 specifications enable a controller residing in a computer system to communicate with a variety of devices, including telecommunication devices through a TDM interface such as a five wire TDM interface. Some of those telecommunication devices, for example, data modems, may use telephone lines to communicate with other devices and exchange data. The Azalia standard is an upgrade of the AC-97 also sponsored by Intel Corporation. The Azalia standard provides a five wire interface as with the AC-97 standard, however, the Azalia interface is based upon a packet based protocol rather than a TDM based protocol. The Azalia Specification revision 0.7 is hereby incorporated by reference in its entirety. In prior art DAA solutions, the DAA circuitry is typically configured with a dedicated interface that operates with only one interface standard. For example, the Silicon Laboratories Si3038 product is a DAA that has an interface that complies with the AC-97 specification (the datasheet for the Si3038 is expressly incorporated herein by reference). 
     FIG. 1A  provides a block diagram of an exemplary DAA configured to operate with the AC-97 interface standard. As shown in  FIG. 1A , a system side integrated circuit  102 A may include clock circuitry  122 , AC-97 digital interface circuitry  118 , and control interface  124 . An isolation interface  126  may also be provided. The line side integrated circuit  104 A may include an isolation interface  128 , hybrid and dc termination circuitry  130  and control signal circuitry  132  (such as ring detect circuitry, off-hook detect circuitry, etc.). A plurality of lines  134  may couple the line side integrated circuit  104 A to discrete components that are used to couple the line side integrated circuit to the TIP and RING phone lines of a phone line network. An isolation barrier  106  may be provided between the line side integrated circuit  104 A and the system side integrated circuit  102 A. The isolation barrier  106  provides the electrical isolation of the phone line network as required by various U.S. and foreign governmental and international bodies and/or standards, such as for example as required by the FCC. 
   To accommodate an interface standard, the DAA circuitry  100  is generally hardwired or hard programmed to operate with a single known interface standard. It would be desirable to implement a DAA that may operate with a plurality of interface standards. 
   SUMMARY OF THE INVENTION 
   In one embodiment, the present invention provides a technique for an electrical device to automatically detect one of a plurality of interface standards to operate in accordance with. More particularly, a DAA is provided for utilization with modem communications over a phone line. The DAA may be configured to automatically detect and operate in accordance with a plurality of interface standards for communications to a host system. For example, the DAA may detect that communications are to be provided in accordance with the AC-97 interface standard or the Azalia interface standard. 
   In one embodiment, the clock signal may be monitored. The frequency of the clock may then be utilized to determine which interface standard the DAA should operate in accordance with. In another embodiment, the automatic detection of the interface standard may be accomplished by monitoring the data presented to the DAA through the interface standard. For example, the number of bit clocks provided across the interface during a frame SYNC signal (“SYNC”) may be counted to determine which interface standard the DAA should operate in accordance with. 

   
     DESCRIPTION OF THE DRAWINGS 
     The appended drawings illustrate only exemplary embodiments of the invention and therefore do not limit its scope, because the inventive concepts lend themselves to other equally effective embodiments. 
       FIG. 1  is block diagram of a DAA and host system. 
       FIG. 1A  is block diagram of a prior art DAA. 
       FIG. 2  is block diagram of a DAA system side circuit having a programmable interface and clock inputs. 
       FIG. 3  is a block diagram of a DAA system side circuit having circuitry to detect an input clock frequency. 
       FIG. 4  is a block diagram of a DAA system side circuit having circuitry to select an interface standard based upon data presented at the communication interface. 
       FIG. 5  is a timing diagram illustrating differences between the AC-97 and Azalia interface standards. 
       FIG. 6  is a block diagram of a programmable interface of a DAA system side circuit for selecting between the AC-97 and the Azalia interface standards. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   One embodiment of the system side circuitry  102  of  FIG. 1  is shown in more detail in FIG.  2 . As shown in  FIG. 2 , the system side circuitry  102  may communicate with the host system main bus through a communication interface  116 . The communication interface  116  may be configured for any of a wide variety of interface standards as discussed above. Typically the interface is configured as a multi-line bus connection as shown by communication interface lines  120 . Information provided across the communication interface may be input data, output data, clocking information, synchronization information, reset triggers, etc. as is known in the art. Generally, in addition to communication with the host system main bus through the communication interface  116 , the DAA also may receive a master clock from the system. As shown in  FIG. 2 , at least one clock line  122  may be provided to provide a clock signal to the system side circuitry  102 . Alternatively, rather than providing a clock signal via a clock line  122 , the clock source may be a crystal oscillator  124  that provides a clock signal to the system side circuitry  102  at nodes Xin and Xout through lines  125  and  127 . In one embodiment, the system side circuitry may be fully integrated within a single integrated circuit and the communication interface lines  120 , clock line  122  and the crystal oscillator Xin and Xout nodes are provided to separate pins of the integrated circuit. The node for the clock line  122  may be shared with the Xout node. Though not shown, the system side circuitry  102  may also communicate with the system through other pins that provide functionality such as device ID, general purpose I/O, etc. 
   As shown in  FIG. 2 , the system side circuitry  102  is shown to receive a clock signal from either a clock line  122  or a crystal oscillator  124 . However, the system side circuitry  102  need not be constructed to receive the clock signal from both sources but rather the system side circuitry  102  may also be constructed in a manner that the clock signal is only receive from the clock line  122  or only received from the crystal oscillator  124 . 
   As shown in  FIG. 3 , the system side circuitry  102  may also include a programmable interface  164  that transmits and receives data to and from the communication interface lines  120 . The programmable interface  164  may then provide the data to and from the rest of the system side circuitry  102  through lines  170  in order to provide the data to and from the line side circuitry  104  across an isolation barrier  106 . The programmable interface  164  may be interface circuitry that is programmable to operate in a plurality of modes. For example, the programmable interface circuitry  164  may receive and transmit data in accordance with two or more interface standards. In one embodiment, the programmable interface circuitry  164  may be operable in an AC-97 mode or in an Azalia mode of operation. Though described with relationship to switchable operations between AC-97 and Azalia modes, it will be recognized that the DAA techniques provided herein may also be utilized for providing a DAA that is programmable to operate with other interface standards. 
   In one embodiment, the programmable interface circuitry  164  may be programmed to a specific desired interface standard by detecting the frequency of the clock signal provided from the system to the DAA. For example, in a typical AC-97 mode of operation, the clock provided by the system to the DAA  100  is often at 12.288 MHZ, 14.31818 MHZ or 24.576 MHZ. Most typically, if the clock provided from an AC-97 based system is at 12.288 or 14.31818 MHZ, then the clock is provided via clock line  122 . Alternatively, a clock signal provided at 24.576 MHZ may most typically be provided at the Xin and Xout lines  125  and  127 . However, in a typical Azalia mode of operation, the clock provided by the system to the DAA  100  is often a 24.000 MHZ signal provided on the clock line  122 . Thus, as shown in  FIG. 3 , a clock detect circuit  160  may be provided. The clock detect circuit  160  may be coupled to clock lines  122 ,  125  and  127  to detect the frequency and/or source of the incoming clock signal. If the source of the clock is the crystal oscillator  124  and/or a frequency of 12.288 MHZ, 14.31818 MHZ or 24.576 MHZ is detected by the clock detect circuitry  160 , the system side circuitry  102  may then recognize that it is being utilized in an AC-97 standard based system. However, if the clock detect circuitry  160  detects a clock frequency of 24.000 MHZ, then the system side circuitry  102  may recognize that it is being utilized in an Azalia standard based system. The clock detect circuitry  160  may provide a mode select signal through line(s)  162  to the programmable interface  164  for setting the programmable interface to operate in accordance with the appropriate interface standard based upon the clock information presented to the system side circuitry  102 . 
   In this manner, a single system side circuitry  102  of a DAA  100  may be constructed to operate in plurality of interface modes. Thus, separate dedicated parts need not be provided for each mode of operation. Rather, one common DAA system  100  having the same system side circuitry  102  may be utilized independent of what type of communication interface standard the system in which the DAA is placed operates in accordance with. The system side circuitry  102  may in operation automatically detect what type of system the DAA  100  is being utilized within and switch the interface circuitry of the system side circuitry  102  accordingly. 
   In yet another embodiment, the system side circuitry  102  may determine what type of system interface standard that is being utilized based upon the data contained within the communication interface  116 . Thus, as a particular interface standard may have its own data format, synchronization protocols, framing protocols, etc., the system side circuitry  102  may monitor the information presented on the communication interface lines  120  to directly determine what type of interface standard is being utilized and then switch the interface circuitry of the system side circuitry accordingly. 
     FIG. 4  illustrates operations of system side circuitry  102  in which the interface standard is determined from the information presented on the communication interface lines  120 . As shown in  FIG. 4 , the programmable interface  164  receives information from the communication interface lines  120 . A mode detection circuit  190  detects what interface standard is being utilized based upon at least one characteristic of the information carried on the communication interface lines  120 . The mode detection circuit  190  provides a mode signal on line(s)  192  to switchable mode selection circuit  180  for configuring the programmable interface  164  to operate in accordance with the desired interface standard mode. 
   In one embodiment, the mode detection circuit  190  may be utilized to detect whether the system side circuitry  102  is being utilized in an AC-97 or Azalia interface standard system. For example, both the AC-97 and Azalia interface standards utilize a five wire interface having a RESET, SYNC, BIT_CLK, SDATA_IN, and SDATA_OUT line. The RESET signal is a hardware reset signal. The SYNC signal is a data framing signal that is used to identify data communication frames. The BIT_CLK signal controls data on the SDATA_IN line and latches data on SDATA_OUT line. The SDATA_IN line provides data from the DAA  100  to the host system  114 . The SDATA_OUT line provides data from the host system  114  to the DAA  100 . More details regarding the AC-97 and Azalia standards may be found in the AC-97 Specification and the Azalia Specification as noted above. 
     FIG. 5  provides more detail regarding the relationship of the SYNC signal and BIT_CLK signal in the AC-97 and Azalia standards. As can be seen in  FIG. 5 , sixteen pulses of the BIT_CLK signal  501  occur during the assertion of the SYNC signal  503  when operating in accordance with the AC-97 standard. However, when operating under the Azalia standard, four pulses of the BIT_CLK signal  505  occur during the assertion of the SYNC signal  507 . 
   In accordance with the techniques describe herein, a programmable interface may be set to either an AC-97 or Azalia mode by monitoring the number of BIT_CLK pulses during the assertion of the SYNC signal. In this exemplary technique, information provided on the SYNC and BIT_CLK lines is utilized to set the interface standard mode of the system side circuit  102 . Thus, the mode detection circuitry  190  of  FIG. 4  may monitor the SYNC and BIT_CLK lines to determine which standard the system is operating in accordance with. It will be recognized that the selection of modes between an AC-97 and Azalia mode and the use of the SYNC and BIT_CLK signals for the selection is exemplary and other standards and other signal lines may be utilized to achieve the techniques described herein. 
   One embodiment of a programmable interface  164  for use in system side circuitry  102  of a DAA  100  for selection between an AC-97 and Azalia operating mode is shown in FIG.  6 . As shown in  FIG. 6 , the communication interface lines  120  (comprising the SYNC line  602 , BIT_CLK line  604 , RESET line  606 , SDATA_OUT line  608 , and SDATA_IN line  610 ) are provided to the programmable interface  164 . More particularly, the communication interface lines  120  are provided to an AC-97 circuit  624  and an Azalia circuit  626 . The AC-97 circuit  624  may include serial to parallel converter circuitry to change the serial information contained on the SDATA_OUT line  608  to parallel information on parallel bus  625 . Thus, the AC-97 circuit  624  may extract the AC-97 field, data, and control information and present this information on the parallel bus  625 . Likewise, the Azalia circuit  626  may extract the serial Azalia based information and present it on the parallel bus  627 . Information that is being provided from the host system  114  through the programmable interface  164  to the rest of the DAA  100  is provided on bus  630 . 
   The AC-97 circuit  624  and the Azalia circuit  626  may also receive information that is to be communicated from the DAA  100  to the host system  114 . This information is provided on bus  640  and is converted to the appropriate serial format by either the AC-97 circuit  624  or the Azalia circuit  626  which provide the serial data through multiplexer  622  to the SDATA_IN line  610 . 
   A detector  612  is coupled to the SYNC line  602  and the BIT_CLK line  604 . The detector  612  counts the number of pulses of the BIT_CLK signal during an assertion of the SYNC line  602  to determine if the system is an AC-97 or Azalia based system. An output line  616  provides an output signal from the detector  612  that is indicative of whether the communication interface standard is AC-97 or Azalia. On initial start up, a power on reset circuit  614  selects a desired default standard, for example the Azalia standard. Then, if the detector  612  detects AC-97 conditions, an output on signal line  616  may change to indicate AC-97 operations. The output of the detector  612  may be provided to multiplexer  620 . Multiplexer  620  selects between the AC-97 based information on bus  625  or the Azalia based information on bus  627  and provides on bus  630  either the AC-97 based information or the Azalia based information to the rest of the DAA based upon the detector output signal on output line  616 . Similarly, the output of detector  614  may be provided to multiplexer  622  which selects between AC-97 based information or Azalia based information to provide to the host system  114  on the SDATA — 1N line  610 , again based upon the detector output signal on output line  616 . The output line  616  may also be provided to other circuits within the DAA that may change depending upon whether AC-97 or Azalia operations are desired. For example, PLLs which generate internal clocks within the system side circuitry  102  from the externally provided clock signals (which will vary in frequency depending upon which interface standard is utilized) may be coupled to the output line  616  so as to receive the detector output signal. In addition, various system side registers may be set depending upon the mode of operation indicated by the detector output. 
   The AC-97 circuit  624  and the Azalia circuit  626  may also be coupled to the detector output signal on output line  616 . If AC-97 data is indicated by the detector output signal, the Azalia circuit  626  may be held off. If Azalia data is indicated by the detector output signal, the AC-97 circuit  624  may be held off. In an alternative embodiment, the AC-97 circuit  624  and the Azalia circuit  626  may be combined in one programmable circuit that may perform the serial to parallel conversion for both interface standards. In such an approach, the circuit may be programmably set to process the incoming serial data according to the desired interface standard format and provide a parallel output on an output bus. Similarly, the circuit may be programmably set to convert parallel data presented on bus  640  to the desired interface standard format for presentation to the SDATA_IN line  610 . In such an approach multiplexers  620  and  622  may not be required. It will be recognized that the techniques described herein may be implemented with a wide range of circuit arrangements and may apply to a wide range of interface standards. 
   Further modifications and alternative embodiments of this invention will be apparent to those skilled in the art in view of this description of the invention. Accordingly, this description teaches those skilled in the art the manner of carrying out the invention and are to be construed as illustrative only. The forms of the invention shown and described should be taken as the presently preferred embodiments. Persons skilled in the art may make various changes in the shape, size and arrangement of parts. For example, persons skilled in the art may substitute equivalent elements for the elements illustrated and described here. Moreover, persons skilled in the art after having the benefit of this description of the invention may use certain features of the invention independently of the use of other features, without departing from the scope of the invention.