Abstract:
A device for writing data into a memory and a method thereof. The memory comprises a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. The data are divided into a plurality of segments. The segments are written into first memory cells of the memory cells of the memory arrays in sequence. The segments start being written into the second memory cells of the memory cells of the memory arrays when the first memory cells of the memory cells of the memory arrays are full, and so forth, till the operation of writing the segments into the memory is completed.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to devices for writing data into a memory and methods thereof, and in particular relates to devices for writing data into a memory in a DMB-TH system and methods thereof. 
         [0003]    2. Description of the Related Art 
         [0004]    Memory space of SDRAMs is usually divided into four Banks, which are Bank 0 , Bank 1 , Bank 2  and Bank 3  respectively. While writing data into an SDRAM, consequential data is saved in the four Banks respectively. Referring to  FIG. 1 ,  FIG. 1  shows the internal recording structure of an SDRAM. The internal part of the SDRAM is divided into four memory arrays, Bank 0 ˜Bank 3 . Each of the memory arrays comprises a plurality of memory cells. In conventional operational processes, while saving data in an SDRAM, the data is usually written into the memory arrays in sequence, from Bank 0  to Bank 3 . Specifically, the memory array Bank 1  would not be used until the memory array Bank 0  is full. The data is written into the SDRAM completely in the aforementioned sequence. 
         [0005]    However, according to the characteristics of an SDRAM, writing data from Bank 0  to Bank 3  requires a plurality of buffers to support the large number of data registering while reading and writing the data. Therefore, increased hardware is required, and data reading and writing efficiency is less than desired. Thus, a more novel method of writing data into an SDRAM more efficiently is desired. 
       BRIEF SUMMARY OF INVENTION 
       [0006]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
         [0007]    A device for writing data into a memory is disclosed. The memory comprises a plurality of memory arrays, and each of the memory arrays comprises a plurality of memory cells. The memory cells are arranged as a plurality of columns and a plurality of rows. The data are divided into a plurality of segments. The device comprises a controller configured to write the segments into a first row of the memory cells in sequence, a second row of the memory cells in sequence, . . . , and so forth till the operation of writing the segments into the memory is completed. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0008]    The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0009]      FIG. 1  is a diagram illustrating the internal recording structure of an SDRAM in an embodiment of the invention; 
           [0010]      FIG. 2  is a diagram illustrating the structure of a device for writing data into a memory in an embodiment of the invention; 
           [0011]      FIG. 3  is a diagram illustrating the structure of the memory data in an embodiment of the invention; and 
           [0012]      FIG. 4  is a diagram illustrating the steps of writing data into a memory in an embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF INVENTION 
       [0013]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0014]    Referring to  FIG. 2 ,  FIG. 2  is a diagram illustrating the structure of a device for writing data into a memory disclosed in an exemplary embodiment of the invention. The device for writing data into memory  2  comprises a first buffer  21 , a second buffer  22 , a controller  23  and a memory  24 . First buffer  21  and second buffer  22  are coupled to each other, and are coupled to controller  23  for reading data and temporarily saving data until controller  23  processes the data. Controller  23  is coupled to memory  24  for dividing the data into a plurality of segments and writing the data saved in first buffer  21  and second buffer  22  into memory  24  in sequence. 
         [0015]    Referring to  FIG. 3 ,  FIG. 3  is a diagram illustrating the data structure of a memory in an exemplary embodiment of the invention. Memory  24  comprises four memory arrays, which are first memory array Bank 0 , second memory array Bank 1 , third memory array Bank 2  and forth memory array Bank 3 . Each of the memory arrays comprises 13 memory cells. Accordingly, memory  24  comprises 52 memory cells, which are Branch 0 ˜Branch 51 . Branch 0  is the first memory cell of Bank 0 , Branch 1  is the first memory cell: of Bank 1 , Branch 2  is the first memory cell of Bank 2 , Branch 3  is the first memory cell of Bank 3 , Branch 4  is the second memory cell of Bank 0 , and so forth. Thus, the first memory array Bank 0  comprises memory cells Branch 4 X (0≦X≦13, X is an integer), Bank 1  comprises memory cells  4 X+1, Bank 2  comprises memory cells branck 4 X+2, and Bank 3  comprises memory cells Branch 4 X+3. When controller  23  is writing the data into memory  24 , the data is written in the sequence of Branch 0 , Branch 1 , Branch 2 , Branch 3 , . . . , Branch 51 . In another word, controller  23  writes the data into Bank 1  before Bank 0  is full, the data is written into the memory in the sequence of Bank 0 →Bank 1 →Bank 2 →Bank 3 →Bank 0  . . . For each memory array, the data is written into a memory cell at one time for conforming to the characteristics of the memory and increasing the efficiencies of data reading and writing. 
         [0016]    In the embodiment, it is preferred that both the first buffer  21  and second buffer  22  be FIFO (first in first out) buffers which each saves four banks of data with 20 bits, but it is not limited to the disclosed embodiments. First buffer  21  reads four banks of the data with 20 bits, the data is written into the first memory cells Branch 0 , Branch 1 , Branch 2  and Branch 3  of the memory arrays Bank 0 ˜Bank 3  via the controller. Because the memory size of each memory cell is about 20 bits, first buffer.  21  may temporarily save all the data which is going to be written into the four memory cells. When the data saved in first buffer  21  is being written into the memory, second buffer  22  reads the next four banks of the data with 20 bits simultaneously and saves the data in second buffer  22 . After the data saved in first buffer  21  has been written into the memory, then the data saved in second buffer  22  is written into the memory cells Branch 4 , Branch 5 , Branch 6  and Branch 7 , the second memory cells of Bank 0 ˜Bank 3 . Accordingly, first buffer  21  temporarily saves the data which is going to be written into the first, the third, the fifth, . . . , and the thirteenth memory cells of the memory arrays Bank 0 ˜Bank 3 , and second buffer  22  temporarily saves the data which is going to be written into the second, the forth, the sixth, . . . , and the twelfth memory cells of the memory arrays Bank 0 ˜Bank 3 . In addition, when first buffer  21  performs the writing operation, second buffer  22  may perform the reading operation simultaneously, in which the operation of writing the data into the memory may be performed ceaselessly and is not influenced by the operation of reading. The whole device may be referred to as ReadWrite 4 Banks. 
         [0017]    In the embodiment, memory  24  may be an SDRAM, and the device may be used in a DMB-TH system, but it is not limited to the disclosed embodiments. 
         [0018]    Referring to  FIG. 4 ,  FIG. 4  is a diagram illustrating the steps of writing data into a memory. When the operation of writing the data into memory  24  is started (S 1 ), the data is read dividedly and temporarily saved in first buffer  21  (S 2 ). Then, controller  23  writes, the data saved in first buffer  21  into the memory cells Branch 0 ˜ 3  in sequence (S 31 ), and the next data are read dividedly and temporarily saved in second buffer  22  simultaneously (S 32 ). Then, the data next to the next data are read dividedly and temporarily saved in first buffer  21  (S 41 ), and controller  23  writes the data saved in second buffer  22  into the memory cells Branch 4 ˜ 7  in sequence (S 42 ). The aforementioned operation is performed repeatedly in sequence until controller  23  writes the data saved in second buffer  22  into the memory cells Branch 44 ˜ 47  in sequence (S 82 ) and writes the data saved in first buffer  21  into the memory cells Branch 48 ˜ 51  in sequence (S 9 ) Finally, the operation of writing the data into memory  24  is finished (S 10 ). 
         [0019]    In the disclosed embodiments of the invention, the data are written into the SDRAM in sequence according to the characteristics of SDRAM. Not only does the speed of writing data into an SDRAM increase, but also the usage of buffers is conserved. Since the efficiency is increased and the costs are saved, the goal of improving the efficiency of SDRAM data writing is achieved. 
         [0020]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.