Abstract:
The invention provides a method for driving a CCD area image sensor. An interline transfer type CCD area image sensor includes a plurality of photo sensors arranged in a plurality of lines. A plurality of vertical shift registers are disposed along one of the lines of photo sensors. A horizontal shift register is formed to receive charges from the vertical shift registers. An output circuit converts the charges transferred through the horizontal shift resistor into electrical signals. The driving method includes the steps of accumulating charges in the photo sensors, transferring charges accumulated in all of the photo sensors to the vertical shift registers, and shifting the transferred charges to the horizontal shift register via the vertical shift registers. The start of charge-shiftings is initiated from the charges in the order of the distances between the transferred position and the photo sensors and the horizontal shift register. The charges received from the vertical shift registers are shifted through the horizontal shift register to an output circuit where the quality of charges reaching the output is converted into an electrical signal. The CCD area image sensor includes at least one shift register circuit for producing shift pulses which perform the above-mentioned operations.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a driving method and a structure of a CCD (Charge Coupled Device) area image sensor, and more particularly to a method for driving a CCD area image sensor of an interline transfer type in a non-interlace scanning and to a structure of the same suitable for the driving in the non-interlace scanning. 
     2. Description of the Related Art 
     A CCD area image sensor has been developed with a technical progress of semiconductor integrated circuits to the extent that it can be used as a TV camera for commercial-use and home-use. Vigorous studies still continue for improvement of the CCD area image sensor. An improvement of resolution is one of technical problems. While the resolution in horizontal direction can be easily improved by increasing the number of photosensor elements, that in the vertical direction cannot be improved by the same method, because the maximum limit in number of scanning lines is fixed by the TV standard. 
     In recent years, an attempt for improving the resolution in vertical direction is made by driving the CCD area image sensor in a non-interlace scanning in place of a driving in a conventional interlace scanning. The visual resolution of the non-interlaced picture is theoretically improved by 66 percent, compared to the interlaced picture. The conventional CCD area image sensor of an interline transfer type, however, is designed for the interlace scanning, and cannot be driven in the non-interlacing scanning. 
     More specifically, the interline transfer type CCD area image sensor has a plurality of lines of photosensors, a plurality of vertical shift registers interposed between the lines of photosensors, a horizontal shift register positioning at ends of the vertical shift registers and an output means producing a voltage signal from quantity of charges transferred through the horizontal shift register. The vertical and horizontal shift registers are made of a series connection of shift stages. One shift stage comprises two sets of storage and barrier electrodes. Charges are stored under one of storage electrodes. Two photo sensors are disposed besides one shift stage of the vertical shift register. At a time, charges accumulated in one of the two photo sensors are transferred to a portion under one of storage electrodes of the corresponding shift stage. The transferred charges are then transferred through the vertical shift register to the horizontal shift register. After the charges are transferred through the horizontal shift register to the output means, the transferred charges are converted into a voltage form signal. In the next time, charges accumulated in the other of the two photo sensors are transferred to another portion under the other storage electrode of the corresponding shift stage and then transferred through the vertical and horizontal shift registers to the output means. This process performs the interlace scanning. 
     If charges accumulated in the adjacent two photo sensors are simultaneously transferred to the portions under both storage electrodes in one shift stage, the charges are mixed during the transfer through the vertical shift register. The charge mixing is unavoidable, so far as the vertical shift register is driven by usual shift pulses of two or four phases. Due to such charge mixing, the electrical signals corresponding to picture elements can not be obtained with high fidelity. In this way, the non-interlace scanning is impossible by the conventional driving method of the interline type CCD area image sensor. 
     SUMMARY OF THE INVENTION 
     It is a primary object of the present invention to provide a method for driving an interline transfer type CCD area image sensor in a non-interlace scanning. 
     It is another object of the present invention to provide a structure of an interline transfer type CCD area image sensor for being driven in a non-interlace scanning. 
     It is still another object of the present invention to provide a structure of an interlace transfer type CCD area image sensor for being driven in both interlace and non-interlace scannings which are interchangeable. 
     According to a main feature of the present invention, a method for driving an interline transfer type CCD area image sensor includes a plurality of photo sensors arranged in a plurality of lines. A plurality of vertical shift registers are disposed along one of the lines of photo sensors, each of the vertical shift registers including a plurality of shift stages connected in series. Each of the photo sensors is disposed to correspond to one shift stage. A horizontal shift register is formed to receive charges from the vertical shift registers, converting charges transferred through the horizontal shift resistor into electrical signals. The charges accumulated in the photo sensors are transferred to the vertical shift register. The driving method includes the steps of accumulating charges in the photo sensors, and transferring those charges to the vertical shift registers. The transferred charges are shifted towad the horizontal shift register via the vertical shift registers so that starts of charge-shiftings are initiated in the order of distances between the horizontal shift register and the positions to which charges are transferred from the photo sensors. The shifting charges are received from the vertical shift registers via the horizontal shift register and moved toward the output means, converting the quantity of charges reaching the output into an electrical signal. 
     The main feature of the present invention includes the steps of delaying the shift operation in the vertical shift registers such that delay time for each stage increases as the distance from the horizontal shift register to that stage is increased. As a result, all the charges transferred from all the photo sensors to positions under every storage electrodes of the vertical shift register can be shifted through the vertical shift register without mixing with other charges. Thus, charges accumulated in all the photo sensors can be converted into electrical signal with a non-interlace scanning. 
     The driving of the vertical shift register can be realized by use of a shift register circuit which may include a series connection of a transfer gate and an inverter receiving the output of the transfer gate. The outputs from the inverters are sequentially applied to the storage and barrier electrodes of the vertical shift register in an order of distance from the horizontal shift register. 
     The driving method of the interline transfer type CCD area image sensor can be interchanged between the non-interlace scanning and the interlace scanning by modifying the shift register circuit so that four phase shift pulses are respectively applied to the input terminals of the inverters through switches. At the non-interlace driving, the switches are made open to shift a pulse applied to the first stage transfer gate through the shift register circuit. At the interlace driving, all the transfer gates are made open to apply the four phase shift pulses to the vertical shift register through the inverters. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and further objects, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, wherein: 
     FIG. 1 is a schematic plan view of the interline transfer type CCD area image sensor in the prior art; 
     FIG. 2 is a timing chart of shift pulses applied to the vertical shift register of the CCD area image sensor in the prior art shown in FIG. 1; 
     FIG. 3 is a schematic plan view of a first embodiment of the present invention; 
     FIG. 4 is a detailed plan view of a part of a horizontal shift resistor according to the first embodiment; 
     FIG. 5(a) is a detailed plan view of a part of photo sensors and vertical shift registers according to the first embodiment; 
     FIG. 5(b) is a sectional view taken along A-A&#39; of FIG. 5(a); 
     FIG. 6 is a circuit diagram of shift register circuit for producing shift pulses used in the first embodiment; 
     FIG. 7 is a timing chart of clock pulses and shift pulses used in the first embodiment; 
     FIG. 8 is a schematic view for explaining the shift of charges in the first embodiment; 
     FIG. 9 is a circuit diagram of shift register circuit for producing shift pulses used in a second embodiment according to the present invention; and 
     FIG. 10 is a timing chart of shift pulses at interlace scanning produced by the shift register circuit of FIG. 9. 
    
    
     The interline transfer type CCD area image sensor in the prior has a plurality of couples of a line of photo sensors 1, 4, 7, 10 . . . 13, 2, 5, 8, 11 . . . 14, . . . , 3, 6, 9, 12 . . . 15 and a vertical shift register 16, 17 . . . 18, as shown in FIG. 1. Each two photo sensors are disposed for each one shift stage of the vertical shift register. In each shift stage, a first barrier electrode receiving a shift pulse φ 1 , a first storage electrode receiving a shift pulse φ 2 , a second barrier electrode receiving a shift pulse φ 3  and a second storage electrode receiving a shift pulse φ 4  are arranged in this order from up to down in FIG. 1. That is, first barrier and storage electrodes oppose one photo sensor, second barrier and storage electrodes opposing another photo sensor. The storage electrodes are extended to the photo sensors, to transfer charges accumulated in the photo sensors in response to transfer pulse added to the shift pulses φ 2  and φ 4  in a vertical blanking period and having a hight higher than the pulses for shifting charges through the vertical shift register 16, 17 . . . 18. The pulses φ 1 , φ 2 , φ 3  and φ 4  for charge shifting are shown in FIG. 2. 
     At a time, charges accumulated in the photo sensors 1, 2, 3, 7, 8, 9 . . . are transferred to the vertical shift register 16, 17 . . . 18 and then shift therethrough toward a horizontal shift register 19. After every shift of charges by one shift stage at a horizontal blanking periods t B1  and t B2 , charges transferred to the horizontal shift register 19 are shifted therethrough toward a charge-voltage converter 20 at horizontal field periods t E1  and t E2  to produce output signals of a voltage form. Thereafter, charges accumulated in the other photo sensors 4, 5, 6, 7, 8, 9 . . . 13, 14, 15 are transferred to the vertical shift registers 16, 17, 18 to be shifted therethrough to the horizontal shift register 19. The charges transferred to the horizontal shift register 19 are shifted therethrough to the charge-voltage converter 20. 
     Thus performed operation is the interlace scanning. According to the interlace scanning, at any time, charges do not exist at adjacent half of shift stage and can be transferred through the vertical shift registers 16, 17 and 18 without mixing with other charges. If charges accumulated in all the photo sensors, however, are simultaneously transferred to the shift registers 16, 17 and 18, charges are stored under the storage electrodes of every shift stage. In such condition, if charges are shifted through the vertical shift registers 16, 17 and 18, charges in the adjacent half of shift stage are mixed to loose the information detected by the photo sensors. This means that it is impossible to drive the interline transfer type CCD area image sensor in the non-interlace scanning so far as the conventional shift pulses are used. 
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The first embodiment uses shift registers 51 and 52 for producing shift pulses applied to vertical shift registers 46, 47 . . . 48, as shown in FIG. 3. Input pulse generators 51&#39; and 52&#39; produces input pulses V I  and clock pulses φ 11  and φ 12  to be supplied to the shift registers 51 and 52. Power voltage controllers 51&#34; and 52&#34; raise voltages V DD  at high power voltage line of the shift registers 51 and 52, when charges are transferred to the vertical shift registers 46, 47 . . . 48 from photo sensors 31, 32 . . . 45 at vertical blanking periods. The other construction of the interline transfer type CCD area image sensor is similar to the CCD area image sensor in the prior art shown in FIGS. 1 and 2. A plurality of photo sensors 31, 32 . . . 45 are arranged in a matrix. Two of the photo sensors are disposed so as to oppose one shift stage of the vertical shift registers. A line of photo sensors and one vertical shift register form a pair. A plurality of pairs are disposed in parallel. A horizontal shift register 49 is disposed at the lower ends of the pairs of the photo sensor line and a vertical shift resistor. The charges accumulated in all the photo sensors 31, 32 . . . 45 are transferred to the vertical shift registers 46, 47 . . . 48, shifted through the vertical shift registers 46, 47 . . . 48 to the horizontal shift register 49, shifted through the horizontal shift register 49 to a charge-voltage converter 59, and then converted into voltage form signals by the charge-voltage converter 59. The shift register 51 supplies shift pulses to electrodes of the vertical shift registers in the left half. The shift register 52 supplies shift pulses to electrodes of the vertical shift registers in the right half. Those two shift registers 51 and 52 may be replaced with one shift register, if wiring impedance of the vertical shift registers 46, 47 . . . 48 can be neglected. All of FIG. 3 are formed on a single chip of semiconductor substrate. 
     The interline transfer type CCD area image sensor is formed on an N-type substrate 53 having an impurity concentration of 10 14  ˜10 16  cm -3 , as shown in a sectional view of FIG. 5(b). The horizontal shift register is formed on an N-type channel region 55&#39;, as shown in FIG. 4, which is formed in a P-type well region 54 (FIG. 5(b)) having an impurity concentration of 10 14  ˜5×10 15  cm -3  and which is formed in the N-type substrate 53. The channel region 55&#39; is surrounded by a P-type channel stopper region 56 and is extended to channel regions 55 of vertical shift registers. 
     The horizontal shift register 49 used in the first embodiment is a buried type. Surface of the channel region 55&#39; is covered with SiO 2  film. A first polycrystalline silicon electrode is deposited on the SiO 2  film to form storage electrodes 57&#39;. A second polycrystalline silicon electrode is deposited on the SiO 2  film to form barrier electrodes 58&#39;. The SiO 2  film under the storage electrodes 57&#39; is thinner than that under the barrier electrodes 58&#39;. Adjacent storage electrode 57&#39; and barrier electrode 58&#39; are connected with each other to form one shift electrode. Two phase shift pulses φ H1  and φ H2  are applied to the shift electrodes to shift charges from right to left of FIG. 4. The shift pulses φ H1  and φ H2  have a high voltage of 0 volt, a low voltage of -6 volts, a pulse width of 35 μsec. and a repetition interval of 35 μsec. 
     The vertical shift registers 46, 47 . . . 48 are coupled to the horizontal shift register 49 though a last electrode 60 formed on SiO 2  film on the channel regions 55 with a first polycrystalline silicon. The last electrode 60 is applied with a voltage of -8 volts when charges are shifted through the horizontal shift register 49 and with a voltage of 0 volt when charges are shifted through the vertical shift registers 46, 47 . . . 48. 
     The photo sensors 31, 32 . . . 45 and vertical shift registers 46, 47 . . . 48 are also formed in the P-type well region 54, as shown in FIGS. 5(a) and 5(b). The photo sensors 31, 32 . . . 45 is made of N -  -type regions 30 surrounded by the P-type channel stopper region 56 with an except of a part of the periphery of the N -  -type regions 30 through which charges accumulated in the N -  -type regions 30 are transferred to the vertical shift regions on the channel region 55 of N-type. Through SiO 2  film, a first and second polycrystalline silicon layers are deposited to form storage electrodes 57 and barrier electrodes 58, respectively. The vertical shift registers in the left half and right half respectively have common storage and barrier electrodes to receive shift pulses from the shift registers 51 and 52, respectively. The SiO 2  film under the storage electrodes 57 is thinner than that under the barrier electrodes 58. 
     The shift registers 51 and 52 are cascade connection of a transfer gate 62 and an inverter 61 receiving a signal from the transfer gate 62, as shown in FIG. 6. The circuit diagram of FIG. 6 shows a circuit for producing four shift pulses applied to electrodes of one shift stage of vertical shift registers. In actual use, the circuits of FIG. 6 are connected in cascade with the number of shift stages in one vertical shift register. The shift register of FIG. 6 is powered with power voltages V DD  and V SS . The power voltage V DD  is 0 volt and raised to 10 volts at a part of the vertical blanking period to transfer changes from the photo sensors 31, 32 . . . 45 to the vertical shift registers 46, 47 . . . 48. The other power voltage V SS  is held at -8 volts. 
     The transfer gates 62 are respectively formed of a MOS FET&#39;s 71, 72, 73 and 74. Clock pulses φ 11  and φ 12  shown in FIG. 7 are respectively applied to gates of the MOS FET&#39;s 71 and 73 and gates of the MOS FET&#39;s 72 and 74. The clock pulses φ 11  and φ 12  have a high voltage of 0 volt, a low voltage of -8 volts and a pulse width of 0.5 to 1.0 μsec. The inverters 61 are respectively made of P-channel MOS FET&#39;s 63, 64, 65 and 66 and N-channel MOS FET&#39;s 67, 68, 69 and 70. Gates of P-channel and N-channel MOS FET&#39;s are commonly connected to receive signal from the preceeding transfer gate 62. Drains of P-channel and N-channel MOS FET&#39;s are also commonly connected to output an inverted signal to the following transfer gate 62. 
     Input pulses V I  shown in FIG. 7 as a signal  ○A  is applied to the MOS FET 71. The pulses in the signal  ○A  have a high-voltage of 0 volt, a low voltage of -8 volt, a pulse width of 1 to 5 μsec. and a repetition interval of about 6.3 μsec. The input pulses V I  are shifted with the clock pulses φ 11  and φ 12  through the shift register. During the shift of the input pulses V I , pulses are produced at circuit points  ○B  to  ○K  as shown in FIG. 7. The signals at the points  ○J  to  ○K  are produced from inverters connected after the circuit point  ○I  to form following shift stages. The signals at the points  ○C ,  ○E , ○G ,  ○I  and  ○K  are applied to the vertical shift register 46, 47 . . . 48. The signal at the point  ○C  is to the storage electrode nearest the horizontal shift register 49. The signal at the point  ○E  is to the barrier electrode nearest the horizontal shift register 49 which is behind the storage electrode receiving the signal at the point  ○C . The signals at the points  ○G , ○I  and  ○K  are respectively applied to the next storage electrode, the next barrier electrode and the further next storage electrode. The simbols t 1  to t 13  in FIG. 7 are timing points in horizontal blanking period. The simbols t H1  to t H3  are effective horizontal field periods. 
     The operation of non-interlace scanning will now be explained with mainly referred to FIGS. 7 and 8. First, charges accumulated in all the photo sensors 31, 32 . . . 45 are transferred to the corresponding shift stages of vertical shift registers 46, 47 . . . 48 under the storage electrodes, at a vertical blanking period. This process is not shown in FIG. 7 but in FIG. 8 at a timing t o  and is performed by raising the power voltage V DD  of the shift registers 51 and 52 by the power voltage controller 51&#34; and 52&#34; to 10 volts. In a horizontal blanking period, an input pulse V I  (hereinafter, referred to as input pulse  ○A ) is applied the shift registers 51 and 52 from the input pulse generators 51&#39; and 52&#39;. At a timing t 1 , the MOS FET 71 is closed by the clock pulse φ 11  to lower the signal at circuit point  ○C (hereinafter, referred as a signal  ○C ). The charges transferred to the nearest storage electrode of the vertical shift registers 46, 47 . . . 48 are shifted to the horizontal shift register. At a timing t 2 , the clock pulse φ 12  closes the MOS FET 72 to raise the signal at the circuit point  ○E  (hereinafter, referred as a signal ○E ). The charges existing under the storage electrode of the second half of the first shift stage at the timing t 1  are expanded under the barrier electrode of the first half of the first shift stage, as shown at the timing t 2  in FIG. 8. At a timing t 3 , the signal at circuit point  ○G  (hereinafter, referred as a signal  ○G ) is lowered to exhaust charges from the storage electrode of the second half of the first shift stage. Simultaneously, the signal  ○C rises to shift charges to the storage electrode of the first half of the first shift stage, as shown at the timing t 3  of FIG. 8. At this timing t 3 , charges at the storage electrode of the first half of the second shift stage is not moved and are separated from the preceding charges by one storage electrode and one barrier electrode to allow usual shift without mixing with the preceding charges. At a timing t 4 , the clock pulses φ 12  raises signal at the circuit point  ○I (hereinafter, referred as a signal  ○I ) to expand charges to the barrier electrode of the second half of the first shift stage, and lowers the signal  ○E  to exhaust charges from the barrier electrode of the first half of the first shift stage and to collect charges existing under the storage and barrier electrodes of the first half of the first shift stage at the timings t 2  and t 3  to a part under the storage electrode only. The charges existing under the storage electrode of the second half of the second shift stage start moving, but the interval from the preceding charges prevent the charges from being mixed with the preceding charges. At an effective horizontal field period t H1 , charges shifted to the horizontal shift register 49 at the timing t 1  are shifted through the horizontal shift register 49 to the charge-voltage converter 50. 
     At timing t 5 , a signal at the circuit point K (hereinafter, referred as a signal  ○K ) the signal  ○G  respectively lowers and rises to move charges existing under the storage electrode of the first half of the second shift stage and the barrier electrode of the second half of the first shift stage at the timing t 4  to under the barrier and storage electrode of the second half of the first shift stage. The signal  ○C  lowers to shift charges existing under the storage electrode of the first half of the first shift stage at the timing t 4  to the horizontal shift register 49. At this timing t 5 , charges under the storage electrode of the second half of the second shift stage is separated from preceding charges by an interval of one storage electrode and one barrier electrode to allow to be shifted without being mixed with the preceding charges. The charges under the storage electrode of the first half of the second shift stage start shifting at the next timing. After charges are shifted at timings t 7  and t.sub. 8, charges shifted to the horizontal shift register 49 are shifted through the horizontal shift register 49 to the charge-voltage converter 50 at the next effective horizontal field period t H2 . The above processes are repeated at the timings t 9  to t 12  and the effective horizontal field period t H3  and the following timings and the following horizontal scanning periods. 
     By the above-mentioned driving method, all the charges accumulated in all the photo sensors are derived in series with voltage form signals during one vertical field period. In other words, it is possible to derive an interline transfer type CCD area image sensor with a non-interlace scanning without mixing charges accumulated in adjacent photo sensors. 
     A second embodiment of the present invention uses an interline transfer type CCD area type sensor similar to that used in the first embodiment explained with reference to FIGS. 3, 4, 5(a), 5(b). The operation in the non-interlace scanning is also similar to that of the first embodiment explained with reference to FIGS. 7 and 8. Only the circuit diagram of the shift registers 51 and 52 producing shift pulses is different from the first embodiment. The circuit diagram of the shift registers 51 and 52 is shown in FIG. 9 and is modified so as to perform an interlace scanning of the interline transfer type CCD area image sensor. 
     Fundamental construction of the shift register circuit is similar to the first embodiment to enable the non-interlace scanning. A plurality of combinations of a transfer gate 62 formed of one of MOS FET&#39;s 71, 72, 73 and 74 and an inverter 61 formed of one of P-channel MOS FET&#39;s 63, 64, 65 and 66 and one of N-channel MOS FET&#39;s 67, 68, 69 and 70 and receiving signal from the transfer gate 62 are connected in cascade. Switches 80 formed of MOS FET&#39;s 81, 82, 83 and 84 are added to the connection points of the transfer gates 62 and the inverters 61. Inverted signal of four phase shift pulses φ 1 , φ 2 , φ 3  and φ 4  shown in FIG. 10 are applied to the connection points through the switches under a control of a switch signal V SW  applied to gates of the MOS FET&#39;s 81, 82, 83 and 84. In actual case, the combinations of the transfer gate 62, the inverter 61 and the switch are connected in cascade with the number of four times of shift stages in the vertical shift register 46, 47 . . . 48. 
     At the non-interlace scanning, the switches 80 are opened by lowering the switch signal V SW  to some voltages under 0 volt. The functional part of the shift register shown in FIG. 9 becomes similar to FIG. 6 and produces shift pulses at the circuit points  ○C ,  ○E , ○G  and  ○I  as explained with reference to FIGS. 6, 7 and 8. The details of the operation for the non-interlace scanning is omitted to avoid overlapping. 
     At the interlace scanning, the switches 80 are closed by raising the switch signal V SW  to zero or some voltages above zero volt to supply the inverted four phase shift pulses φ 1 , φ 2 , φ 3  and φ 4  shown in FIG. 10 to the inverters 61 at horizontal blanking periods t B1 , t B2  . . . Simultaneously, the transfer gates 62 are opened by fixing the clock pulses at -8 volts. The circuit shown in FIG. 9 is transformed from a shift register to a plurality of independent inverters to produce the non-inverted four phase shift pulses shown in FIG. 10 as signals  ○C &#39;,  ○E &#39;,  ○G &#39; and  ○I &#39; at the circuit points  ○C ,  ○E ,  ○G  and ○I  of the circuit shown in FIG. 9. 
     Prior to application of the signals  ○C &#39;,  ○E &#39;,  ○G &#39; and  ○I &#39; to the vertical shift registers 46, 47 . . . 48, the power voltage V DD  is raised to 10 volts at a vertical blanking period with an application of a high voltage of the inverted shift pulses φ 1  and φ 2 . The charges accumulated in every other photo sensors 31, 32 . . . 45 are transferred to the vertical shift registers 46, 47 and 48. At the next vertical blanking period, the power voltage V DD  is raised to 10 volts with a high voltage of the other inverted shift pulses φ 3  and φ 4  to transfer charges accumulated in the other photo sensors 31, 32 . . . 45 to the vertical shift registers 46, 47 and 48. 
     In the vertical scanning period, the signals  ○C &#39;,  ○E &#39;, ○G &#39; and  ○I &#39; are applied to the vertical shift registers 46, 47 and 48 to shift the transferred charges through the vertical shift registers 46, 47 and 48 to the horizontal shift register 49. Since charges exist under one electrode among four electrodes of one shift stage, the charges are shifted in the conventional way of four phase pulse drive without being mixed with adjacent charges. 
     In this way, the second embodiment explained with reference to FIGS. 9 and 10 can change the driving method of an interlace transfer type CCD area image sensor between an interlace scanning and a non-interlace scanning by changing the switch signal V SW  and the clock pulses φ 11  and φ 12 . This change can be easily performed with a small addition of circuit elements to the shift registers 51 and 52. This change is convenient for selectively taking TV pictures with a current interlace scanning or TV pictures of high resolution with a non-interlace scanning. 
     Although some embodiment of the present invention has been described in the foregoing, the present invention is not limited to the above explained embodiments. Only one shift registers for producing shift pulses may be used in place of two shift registers 51 and 52 of FIG. 3. The CCD used in the vertical shift registers 46, 47 . . . 48 and the horizontal shift register 49 may be made of a surface channel type instead of the buried channel type used in the above embodiments. The photo sensors 31, 32 . . . 45 may be changed to MOS type from the PN-diode type used in the above embodiments.