Abstract:
This algorithm and apparatus provides the ability to determine the amount of skew that should be injected into a high-speed data communications system comprising of a plurality of lanes comprising a data bus on a per lane basis, relative to a reference lane, for the purpose of compensating for inherent system skew. By knowing the relative amount of skew that each lane requires for alignment, an appropriate amount of skew can then be injected on each lane to provide alignment and thus compliancy with relevant standards, such as the SxI-5 standard, in terms of data skew specifications. These relative skew amounts for each transmitting lane are determined using dual loopback methods.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    Not Applicable 
       STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
       [0002]    Not Applicable 
       REFERENCE TO SEQUENCE LISTING, A TABLE, OR A COMPUTER PROGRAM LISTING COMPACT DISC APPENDIX 
       [0003]    Not Applicable 
       BACKGROUND OF THE INVENTION 
       [0004]    1. Field of the Invention 
         [0005]    The present invention relates to chip-to-chip high speed data communications and the detection and correction of skew in each transmit channel, relative to a reference channel. 
         [0006]    2. Description of Related Art 
         [0007]    Parallel transmission, as defined with respect to the present invention, is the serial transmission of data over a plurality of lines on a data bus. In this parallel data transmission, skew can be added to each serial data lane through such means as serialization, cross-clock domain crossing, or through static skew parameters such as trace length. This skew can result in different alignments between lines of the data bus. Thus, there is an obvious need to correct this skew, or to deskew the data lines. If the amount of skew added on each line can be found, then a skew injecting apparatus that can compensate for the skew added on each line can eliminate the problem, and thus adhere to relevant standards which specify skew requirements. 
         [0008]    The following system description is applicable to any chip-to-chip high speed communications system where skew compensation may be of benefit. Specific standards mentioned throughout, such as SFI-5 and SxI-5, should be considered examples and are in no way exhaustive. 
         [0009]    One of the standards describing the objectives and requirements of a multi-bit bus for use in the interconnection between devices in communications systems with up to 50 Gb/s optical links is published by the Optical Internetworking Forum: Serdes Framer Interface Level 5 (SFI-5): Implementation Agreement for 40 Gb/s Interface for Physical Devices, with Serdes referring to Serialization and Deserialization (Dartnell, Lerer, and Lynch, 2002). The electrical I/O characteristics of this interface are defined in the standard System Interface Level 5 (SxI-5): Common Electrical Characteristics for 2.488-3.125 Gbps Parallel Interfaces (Palkert &amp; Lerer, 2002). 
         [0010]    The SFI-5 bus has a 16-bit wide data bus with each channel operating at up to 3.125 Gb/s with a Deskew, or Parity, Channel. The Serdes component of the communications system thus requires 17 transceivers to handle these 17 lanes. Each one of these transceivers may have different skew characteristics and may therefore cause misalignment to the standard when transmitting data. 
       BRIEF SUMMARY OF THE INVENTION 
       [0011]    To compensate for the skew differences between each individual lane on the transmit side, skew can be injected by the system into each individual lane to re-align the data. In order to determine how much skew should be injected by the system into each lane, the skew characteristics for each transmitter lane must be known. Using dual loopback techniques, these skew characteristics can be determined for each transmitter lane, and once known, can be corrected using skew injection techniques. 
         [0012]    This is different from the current systems on the market since those involve grouping bus lines with each group having its own clock domain (U.S. Pat. No. 06,839,862, Evoy, Pontius, and Ehmann, 2005) or by using multiple synchronization codes (U.S. Pat. No. 06,920,576, Ehmann, 2005). Evoy et al. describe “grouping the bus lines in groups with each group having its own clock domain, skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups”. Ehmann&#39;s solution “overcomes skewing problems by transferring digital data with automatic realignment”, i.e. using synchronization codes. 
         [0013]    The proposed system of the present invention uses neither separate clock domains for bus line groups nor adds synchronization codes, but rather employs a dual loopback methodology to determine skew characteristics for each bus line which can then be corrected by injecting offsetting skew amounts into the individual bus lines to re-align the data according to a single reference lane, thus eliminating any skew related problems and meeting all relevant standards. 
     
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
         [0014]      FIG. 1  is a block diagram of how the deskew algorithm may be implemented if only external loopback is used to achieve the dual loopback methodology. 
           [0015]      FIG. 2  is a block diagram of how the deskew algorithm may be implemented if both internal and external loopback are used to achieve the dual loopback methodology. 
           [0016]      FIG. 3  is a block diagram of how the deskew algorithm may be implemented if only internal loopback is used to achieve the dual loopback methodology. 
           [0017]      FIG. 4  is a block diagram of how the skew injection technique may be implemented. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0018]    On the transmit side, skew can be injected on a per-lane basis to compensate for any skew added by the system, such as Field Programmable Gate Array (FPGA) startup conditions. This injected skew achieves compliancy as specified by applicable standards, such as SxI-5. To determine how much skew should be injected to meet these standards, the following system is implemented. 
         [0019]    The present invention consists of N+1 transceivers for the purposes of data transmission and reception. The system is designed such that dual loopback can be used to determine the necessary per-lane skew to be added for total lane alignment. 
         [0020]    The term “dual loopback”, as used herein, refers to two transmit streams from the transmitters of two different transceivers that are looped back to the receiver portion of a transceiver. The transceiver that receives the loopback from the transmitters will also be one of the transmitting transceivers. 
         [0021]    To allow for ordinary data flow in the receive direction, multiplexers are used to select between feedback lines or regular data lines. In the case where selectable internal feedback is used within the transceiver and this internal feedback capability is provided by the transceiver, the amount of inputs to the multiplexer can be reduced or the need for an external multiplexer may be eliminated entirely. 
         [0022]    In accordance with the present invention, it may be necessary to use a fanout buffer to mitigate any extra stress on the transmitting lane to preserve signal integrity. This occurs when transmitting lanes have multiple loads (i.e. output to the optics and several loopbacks to receivers). 
         [0023]    A worker skilled in the art will understand that it is necessary for one of the transceivers to be chosen as the reference. This reference transceiver can be chosen as one of the active transceivers or may be a transceiver used solely for the purpose of providing a reference. All other lanes will have their skew determined relative to this reference. 
         [0024]    The system of the present invention enables the calculation of the skew for each transmit lane, relative to one of the lanes. The following examples will illustrate the workings of possible systems mathematically. These examples will deal with smaller 3 transceiver systems. The 3 transceiver example is easily expandable into an SFI-5 system with 17 transceivers, or any other transceiver-based system. Transceivers are herein referred to also as MGTs (Multi-Gigabit Transceivers). 
         [0025]    The following examples are set forth to gain a better understanding of the skew-detection portion of the invention described herein. These examples are provided for illustrative purposes only and they should not limit the scope of this invention in any way. 
       EXAMPLE 1 
     External Loopback Only 
       [0026]    The system in this case is a dual loopback system implemented using external feedback from two different transceivers as shown in  FIG. 1 . In this example a multiplexer with a minimum of three inputs will be necessary—two inputs for the external feedback lines and one input for the regular receive line. 
         [0027]    In Example 1, dual loopback is achieved by utilizing only external loopback to determine the relative skew amounts for each lane as illustrated in  FIG. 1 . The variables and constants used in this example are defined as: 
       Definition List 1 
       [0028]      
         [0000]    
       
         
               
               
               
             
           
               
                   
                   
               
               
                   
                 Term 
                 Definition 
               
               
                   
                   
               
             
             
               
                   
                 R1 
                 Unknown receive skew for MGT_1 
               
               
                   
                 R2 
                 Unknown receive skew for MGT_2 
               
               
                   
                 T0 
                 Unknown transmit skew for MGT_0 
               
               
                   
                 T1 
                 Unknown transmit skew for MGT_1 
               
               
                   
                 T2 
                 Unknown transmit skew for MGT_2 
               
               
                   
                 X01 
                 Unknown external skew for path from 
               
               
                   
                   
                 MGT_0 to MGT_1, from buffer, MUX, and 
               
               
                   
                   
                 PCB trace skew 
               
               
                   
                 X02 
                 Unknown external skew for path from 
               
               
                   
                   
                 MGT_1 to MGT_2, from buffer, MUX, and 
               
               
                   
                   
                 PCB trace skew 
               
               
                   
                 X11 
                 Unknown external skew for path from 
               
               
                   
                   
                 transmitter to receiver of MGT_1, from 
               
               
                   
                   
                 MUX and PCB trace skew 
               
               
                   
                 X22 
                 Unknown external skew for path from 
               
               
                   
                   
                 transmitter to receiver of MGT_2, from 
               
               
                   
                   
                 MUX and PCB trace skew 
               
               
                   
                 E01 
                 Known external skew constant from 
               
               
                   
                   
                 MGT_0 to MGT_1 
               
               
                   
                 E02 
                 Known external skew constant from 
               
               
                   
                   
                 MGT_0 to MGT_2 
               
               
                   
                 E11 
                 Known external skew constant from the 
               
               
                   
                   
                 transmitter to receiver of MGT_1 
               
               
                   
                 E22 
                 Known external skew constant from the 
               
               
                   
                   
                 transmitter to receiver of MGT_2 
               
               
                   
                   
               
             
          
         
       
     
         [0029]    Constants e 01 , e 12 , e 02 , and e 21  may be determined through empirical means, such as testing with a training sequence. This empirical information is collected by the receiver. 
         [0030]    With reference to  FIG. 1 , the following equations can be formulated: 
         [0000]        T 0 +R 1 +X 01 =e 01   (1) 
         [0000]        T 1 +R 1 +X 11 =e 11   (2) 
         [0000]        T 0 +R 2 +X 02 =e 02   (3) 
         [0000]        T 2 +R 2 +X 22 =e 22   (4) 
         [0031]    From equations (1) and (2), R 1  can be equated, giving: 
         [0000]        e 01 −T 0 −X 01 =e 11 −T 1 −X 11 
         [0032]    Therefore, 
         [0000]        T 1 =T 0 +e 11 −e 01 +X 01 −X 11 
         [0033]    Similarly from equations (3) and (4) by equating R 2 , 
         [0000]        e 02 −T 0 −X 02 =e 22 −T 2 −X 22 
         [0034]    Thus, 
         [0000]        T 2 =T 0 +e 22 −e 02 +X 02 −X 22 
         [0035]    And in general, 
         [0000]        T[n]=T 0 +e[nn]−e[ 0 n]+X[ 0 n]−X[nn]   
         [0036]    By taking T 0  (the transmit skew for MGT — 0) as a reference, it is shown that T 1  can be found relative to this skew, and similarly, T 2  can be found relative to T 0 &#39;s skew, with 2 unknowns still remaining in each equation—X[0n] and X[nn], where [n] corresponds to the MGT number. 
         [0037]    Each X[0n] and X[nn] value can be calculated using standard procedures for trace length and PCB characteristics, as well as taking into account the skew added by each MUX and the optional buffer. These values can be calculated to an approximate theoretical value with some amount of uncertainty in each calculation. Therefore, each X[0n] and X[nn] value can be broken into the theoretical calculated value and a statistical variation from this value: 
         [0000]        X[ 0 n]=y[ 0 n]+Z[ 0 n]   
         [0000]    
       
      
       X[nn]=y[nn]+Z[nn] 
      
     
         [0038]    where y[0n] and y[nn] are the theoretical calculated values, and Z[0n] and Z[nn] are the statistical variations from this value. 
         [0039]    Thus, the equations can be written as: 
         [0000]        T[n]=T 0 +e[nn]−e[ 0 n]+y[ 0 n]−y[nn]+Z[ 0 n]−Z[nn]   
         [0040]    where Z[0n] and Z[nn] are the only unknowns. 
         [0041]    As shown by the equation above, the amount of skew between T[n] and T 0  is: 
         [0000]        e[nn]−e[ 0 n]+y[ 0 n]−y[nn]+Z[ 0 n]−Z[nn]   
         [0042]    Since the following values are known: 
         [0000]        e[nn]−e[ 0 n]+y[ 0 n]−y[nn]   
         [0043]    this amount of skew can be injected into each lane to provide total lane alignment to within the resolution of the receiver. 
         [0044]    Thus, the values for Z[0n] and Z[nn] in addition with the resolution of the receiver has to be less than the allowable skew specified by the communication system or applicable standard (2 UI for SxI-5 compliancy). The buffer, MUX, and PCB constraints have to be chosen such that this value is met. 
         [0045]    To increase the number of transceivers from 3 to a higher number, the following procedure can implemented and describes a general way to interconnect any number of transceivers. We will assume sequential names for the transceivers, i.e MGT — 0, MGT — 1, MGT — 2, . . . MGT_N.
   From the N+1 transceivers, a reference transceiver must be chosen, e.g. MGT — 0.   The receiver of each transceiver, with the exception of the reference transceiver, will require a 3:1 MUX. One of the inputs to this MUX will be the normal data line from an external source.   The transmission of the reference transceiver can be used as an input to the MUXs for each of the next transceivers in sequence, i.e. MGT — 1 to MGT_N, if MGT — 0 is chosen as the reference.   The transmission of each transceiver after the reference transceiver, MGT — 1 to MGT_N to continue with the current naming convention, can be used as an input to the MUX for that same transceiver, i.e. the transmitter of MGT — 1 goes to the receiver of MGT — 1, the transmitter of MGT — 2 goes to the receiver of MGT — 2, etc.   By using this method, dual loopback is achieved using only external loopback methods.   It may be necessary to use a fanout buffer to mitigate any extra stress on the transmitting reference lane to preserve signal integrity.   
 
         [0052]    By following this process, all skew values for each transmit lane can be determined relative to a single reference lane. Once the skew for each transmit lane is known relative to this single lane, then the appropriate amount of skew can be injected into each lane to provide total lane alignment in compliancy with relevant standards, such as SxI-5. In order to accomplish this, the resolution of the receiver (typically 0.5 UI due to the RX PLL CDR) and the uncertainty added by any buffers, MUXs, and traces have to be accounted for and be within the allowable skew values for the standard. 
       EXAMPLE 2 
     Both Internal and External Loopback 
       [0053]    Using the present invention, when internal loopback is used within a transceiver, one of the inputs to the multiplexer can be eliminated. The internal loopback takes the place of one of the external loopbacks. Since the internal loopback can be selected or de-selected within the transceiver, the need for an input to the multiplexer for this particular line is eliminated. Thus, the multiplexer only needs a minimum of 2 inputs for this configuration. This example is shown in  FIG. 2 . 
         [0054]    In Example 2, dual loopback is achieved by utilizing internal and external loopback to determine the relative skew amounts for each lane as illustrated in  FIG. 2 . The variables and constants used in this example are defined as: 
       Definition List 2 
       [0055]      
         [0000]    
       
         
               
               
               
             
           
               
                   
                   
               
               
                   
                 Term 
                 Definition 
               
               
                   
                   
               
             
             
               
                   
                 R1 
                 Unknown receive skew for MGT_1 
               
               
                   
                 R2 
                 Unknown receive skew for MGT_2 
               
               
                   
                 T0 
                 Unknown transmit skew for MGT_0 
               
               
                   
                 T1 
                 Unknown transmit skew for MGT_1 
               
               
                   
                 T2 
                 Unknown transmit skew for MGT_2 
               
               
                   
                 X1 
                 Unknown external skew for path from 
               
               
                   
                   
                 MGT_0 to MGT_1, from buffer, MUX, and 
               
               
                   
                   
                 PCB trace skew 
               
               
                   
                 X2 
                 Unknown external skew for path from 
               
               
                   
                   
                 MGT_1 to MGT_2, from buffer, MUX, and 
               
               
                   
                   
                 PCB trace skew 
               
               
                   
                 i1 
                 Known internal skew constant for MGT_1 
               
               
                   
                 i2 
                 Known internal skew constant for MGT_2 
               
               
                   
                 E1 
                 Known external skew constant from 
               
               
                   
                   
                 MGT_0 to MGT_1 
               
               
                   
                 E2 
                 Known external skew constant from 
               
               
                   
                   
                 MGT_1 to MGT_2 
               
               
                   
                   
               
             
          
         
       
     
         [0056]    Constants i 1 , i 2 , e 1 , and e 2  may be determined through empirical means, such as testing with a training sequence. 
         [0057]    With reference to  FIG. 2 , the following equations can be formulated: 
         [0000]        T 0 +R 1 +X 1 =e 1   (5) 
         [0000]        T 1 +R 1 =i 1   (6) 
         [0000]        T 0 +R 2 +X 2 =e 2   (7) 
         [0000]        T 2 +R 2 =i 2   (8) 
         [0058]    From equations (5) and (6), R 1  can be equated, giving: 
         [0000]        e 1 −T 0 −X 1 =i 1 −T 1 
         [0059]    Therefore, 
         [0000]        T 1 =T 0 +i 1 −e 1 +X 1 
         [0060]    Similarly from equations (7) and (8) by equating R 2 , 
         [0000]        e 2 −T 1 −X 2 =i 2 −T 2 
         [0061]    Thus, 
         [0000]        T 2 =T 0 +i 2 −e 2 +X 2 
         [0062]    And in general, 
         [0000]        T[n]=T 0 +i[n]−e[n]+X[n]   
         [0063]    By taking T 0  (the transmit skew for MGT — 0) as a reference, it is shown that T 1  can be found relative to this skew, and similarly, T 2  can be found relative to T 0 &#39;s skew, with 1 unknown still remaining in each equation—X[n], where [n] corresponds to the MGT number. 
         [0064]    Each X[n] value can be calculated using standard procedures for trace length and PCB characteristics, as well as taking into account the skew added by each MUX and the buffer. These values can be calculated to an approximate theoretical value with some amount of uncertainty in each calculation. Therefore, each X[n] value can be broken into the theoretical calculated value and a statistical variation from this value: 
         [0000]    
       
      
       X[n]=y[n]+Z[n] 
      
     
         [0065]    where y[n] is the theoretical calculated value and Z[n] is the statistical variation from this value. 
         [0066]    Thus, the equations can be written as: 
         [0000]        T[n]=T 0 +i[n]−e[n]+y[n]+Z[n]   
         [0067]    where Z[n] is the only unknown. 
         [0068]    As shown by the equation above, the amount of skew between T[n] and T 0  is: 
         [0000]    
       
      
       i[n]−e[n]+y[n]+Z[n] 
      
     
         [0069]    Since the following values are known: 
         [0000]    
       
      
       i[n]−e[n]+y[n] 
      
     
         [0070]    this amount of skew can be injected into each lane to provide total lane alignment to within the resolution of the receiver. 
         [0071]    Thus, the value for Z[n] in addition with the resolution of the receiver has to be less than the allowable skew specified by the applicable standard (2 UI for SxI-5 compliancy). The buffer, MUX, and PCB constraints have to be chosen such that this value is met. 
         [0072]    To increase the number of transceivers from 3 to a higher number, the following procedure can implemented and describes a general way to interconnect any number of transceivers. We will assume sequential names for the transceivers, i.e MGT — 0, MGT — 1, MGT — 2, . . . MGT_N.
   From the N+1 transceivers, a reference transceiver must be chosen, e.g. MGT — 0.   The receiver of each transceiver, with the exception of the reference transceiver, will require a 2:1 MUX. One of the inputs to this MUX will be the normal data line from an external source.   Each transceiver, with the exception of the reference transceiver, will employ internal loopback from the transmitter to the receiver of the transceiver. This internal loopback must be selectable within the transceiver to eliminate the need for any external circuitry.   The transmission of the reference transceiver can be used as an input to the MUXs for each of the next transceivers in sequence, i.e. MGT — 1 to MGT_N, if MGT — 0 is chosen as the reference.   By using this method, dual loopback is achieved using both internal and external loopback methods.   It may be necessary to use a fanout buffer to mitigate any extra stress on the transmitting reference lane to preserve signal integrity.   
 
         [0079]    By following this process, all skew values for each transmit lane can be determined relative to a single reference lane. Once the skew for each transmit lane is known relative to this single lane, then the appropriate amount of skew can be injected into each lane to provide total lane alignment in compliancy with relevant standards, such as SxI-5. In order to accomplish this, the resolution of the receiver (typically 0.5 UI due to the RX PLL CDR) and the uncertainty added by any buffers, MUXs, and traces have to be accounted for and be within the allowable skew values for the standard. 
       EXAMPLE 3 
     Internal Loopback Only 
       [0080]    In this example, internal loopback is used within a transceiver and between transceivers. This results in dual loopback and hence elimination of the entire multiplexer. The internal loopback takes the place of one of the external loopbacks, while the internal loopback between transceivers takes the place of the other external loopback. Since both internal loopback can be selected or de-selected within the transceivers, the need for an external multiplexer is eliminated. This example is shown in  FIG. 3 . 
         [0081]    In Example 3, dual loopback is achieved by utilizing only internal loopback to determine the relative skew amounts for each lane as illustrated in  FIG. 3 . The variables and constants used in this example are defined as: 
       Definition List 3 
       [0082]      
         [0000]    
       
         
               
               
               
             
           
               
                   
                   
               
               
                   
                 Term 
                 Definition 
               
               
                   
                   
               
             
             
               
                   
                 R1 
                 Receive skew for MGT_1 
               
               
                   
                 R2 
                 Receive skew for MGT_2 
               
               
                   
                 T0 
                 Transmit skew for MGT_0 
               
               
                   
                 T1 
                 Transmit skew for MGT_1 
               
               
                   
                 T2 
                 Transmit skew for MGT_2 
               
               
                   
                 I11 
                 Known internal skew constant for MGT_1 
               
               
                   
                 I22 
                 Known internal skew constant for MGT_2 
               
               
                   
                 I01 
                 Known internal skew constant from 
               
               
                   
                   
                 MGT_0 to MGT_1 
               
               
                   
                 I12 
                 Known internal skew constant from 
               
               
                   
                   
                 MGT_1 to MGT_2 
               
               
                   
                   
               
             
          
         
       
     
         [0083]    Constants i 11 , i 22 , i 01 , and i 12  may be determined through empirical means, such as testing with a training sequence. 
         [0084]    With reference to  FIG. 3 , the following equations can be formulated: 
         [0000]        T 1 +R 1 =i 11   (9) 
         [0000]        T 2 +R 2 =i 22   (10) 
         [0000]        T 0 +R 1 =i 01   (11) 
         [0000]        T 1 +R 2 =i 12   (12) 
         [0085]    From equations (9) and (11), R 1  can be equated, giving: 
         [0000]        i 11 −T 1 =i 01 −T 0 
         [0086]    Therefore, 
         [0000]        T 1 =T 0 +i 11 −i 01 
         [0087]    Similarly from equations (10) and (12) by equating R 2 , 
         [0000]        i 22 −T 2 =i 12 −T 1 
         [0088]    Thus, 
         [0000]        T 2 =T 1 +i 22 −i 12 
         [0089]    By taking T 0  (the transmit skew for MGT — 0) as a reference, it is shown that T 1  can be found relative to this skew, and similarly, T 2  can be found relative to T 1 &#39;s skew (which is in turn relative to T 0 .) 
         [0090]    To increase the number of transceivers from 3 to a higher number, the following procedure can implemented and describes a general way to interconnect any number of transceivers. We will assume sequential names for the transceivers, i.e MGT — 0, MGT — 1, MGT_ 2 , . . . MGT_N.
   From the N+1 transceivers, a reference transceiver must be chosen, e.g. MGT — 0.   Each transceiver, with the exception of the reference transceiver, will employ internal loopback from the transmitter to the receiver of the transceiver. This internal loopback must be selectable within the transceiver to eliminate the need for any external circuitry.   The transceivers must be configured in such a way that internal loopback is able to be selected and de-selected between different transceivers without the addition of extra circuitry.   The transmission of the reference transceiver can be used as an input for the internal loopback of the next transceiver in sequence, i.e. MGT — 1 if MGT — 0 is chosen as the reference.   The transmission of the next transceiver after the reference transceiver, MGT — 1 to continue with the current naming convention, can be used as an input for the internal loopback of the next transceiver in sequence, i.e. MGT — 2.   This process continues until the last transceiver is reached, i.e. MGT_N. The transmission from this transceiver does not need to be used as an input to an internal loopback.   By using this method, dual loopback is achieved using only internal loopback methods.   
 
         [0098]    By following this process, all skew values for each transmit lane can be determined relative to a single reference lane. Once the skew for each transmit lane is known relative to this single lane, then the appropriate amount of skew can be injected into each lane to provide total lane alignment in compliancy with relevant standards, such as SxI-5. In order to accomplish this, the resolution of the receiver (typically 0.5 UI due to the RX PLL CDR) has to be accounted for and be within the allowable skew values for the standard. 
         [0099]    The previously explained loopback methods are only considered as examples. Different configurations of each are possible as long as dual loopback is achieved. Combined configurations of each are also possible as long as dual loopback is achieved. 
         [0100]    In order to inject the appropriate amount of skew into each lane to provide lane alignment, the unaligned transmit (TX) data lines enter a buffer for the purposes of lane deskewing. The skew values to be injected for each lane are supplied to the buffer. The buffer then shifts each lane the appropriate amount to ensure lane-to-lane alignment. A representation of a possible embodiment of this injection system is shown in  FIG. 4 . The output from the buffer is the aligned TX data lines, which can then be categorized as being within skew specifications for relevant standards. 
       REFERENCES CITED 
       [0101]    U.S. Patent Documents 
         [0000]    
       
         
               
               
               
               
             
           
               
                   
               
             
             
               
                 6557110 
                 April, 2003 
                 Sakamoto et al. 
                 713/503 
               
               
                 6690757 
                 February, 2004 
                 Bunton et al. 
                 375/371 
               
               
                 6820234 
                 November, 2004 
                 Deas et al. 
                 714/814 
               
               
                 6839862 
                 January, 2005 
                 Evoy et al. 
                 713/503 
               
               
                 6907552 
                 June, 2005 
                 Collins 
                 714/700 
               
               
                 6920576 
                 July, 2005 
                 Ehmann 
                 713/400 
               
               
                 6996738 
                 February, 2006 
                 Chiang 
                 713/503 
               
               
                   
               
             
          
         
       
     
         [0102]    Other References
   OIF, System Framer Interface Level 5 (SFI-5), Jan. 29, 2002   OIF, System Interface Level 5 (SxI-5), October 2002