Abstract:
There is to provide a semiconductor device capable of activating a circuit quickly, operating with a lower power consumption in a steady state, and coping with the dispersion of the elements. The semiconductor device includes an amplifier coupled to a power voltage, to output a voltage based on a reference voltage and a voltage of a negative feedback node, to an output node; and a voltage divider coupled to the output node, to output the divided voltage to the negative feedback node. The voltage divider includes first and second voltage dividing paths with different resistance, a first switching circuit coupled to the first and the second voltage dividing paths, in a dividing ratio adjustable way, and a second switching circuit for controlling the first and the second voltage dividing paths.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The disclosure of Japanese Patent Application No. 2016-143470 filed on Jul. 21, 2016 including the specification, drawings and abstract is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    This disclosure relates to a semiconductor device and particularly, to a semiconductor device having an amplifier. 
         [0003]    Generally, quick circuit activation is required of a semiconductor device and a current increase can speed up the activation. In a steady state after the activation, however, the above current flows, hence to increase the power consumption. On the contrary, when the current in the steady state is tried to narrow, the current at the activation is narrowed; therefore, the quick circuit activation cannot be achieved, in the contradicting properties. 
         [0004]    In Japanese Unexamined Patent Application Publication No. 2001-175802, there is proposed a method of switching a current flow amount after a predetermined time, hence to speed up and increase power consumption. 
         [0005]    Further, there is a possibility of fluctuation in the amplifier output because of dispersion of elements forming a semiconductor device; even if the elements are dispersed, the amplifier output has to be suppressed from the fluctuation. 
         [0006]    This disclosure is made in order to solve the above problems, and it is to provide a semiconductor device capable of activating a circuit quickly as well as operating with a lower power consumption in the steady state, and coping with the element dispersion. 
         [0007]    Other objects and novel characteristics will be apparent from the description of the specification and the attached drawings. 
         [0008]    According to one embodiment, a semiconductor device includes an amplifier coupled to a power voltage, to output a voltage based on a reference voltage and a voltage of a negative feedback node, to an output node, and a voltage divider coupled to the output node, to output divided voltage to the negative feedback node. The voltage divider includes first and second voltage dividing paths with different resistance, a first switching circuit coupled to the first and the second voltage dividing paths, in a dividing ratio adjustable way, and a second switching circuit for controlling the first and the second voltage dividing paths. 
         [0009]    According to one embodiment, the semiconductor device includes a first switching circuit capable of adjusting the dividing ratio and a second switching circuit for controlling the first and the second voltage dividing paths, which makes it possible to adjust the current amount while coping with the dispersion of the elements. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]      FIG. 1  is a view for use in describing a structure of a semiconductor device according to a first embodiment. 
           [0011]      FIG. 2  is a circuit diagram of a regulator circuit  100  according to the first embodiment. 
           [0012]      FIG. 3  is a flow chart for use in describing an operation of the regulator circuit  100  according to the first embodiment. 
           [0013]      FIG. 4  is a view for use in describing a circuit structure of a regulator circuit  102  according to a second embodiment. 
           [0014]      FIG. 5  is a flow chart for use in describing an operation of the regulator circuit  102  according to the second embodiment. 
           [0015]      FIG. 6  is a circuit diagram of a regulator circuit  104  according to a modified example of the second embodiment. 
           [0016]      FIG. 7  is a timing chart of the regulator circuit  104  according to the modified example of the second embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    Embodiments will be described in details with reference to the drawings. The same reference numerals are attached to the same or the corresponding portions and their description is not repeated. 
       First Embodiment 
       [0018]      FIG. 1  is a view for use in describing the structure of a semiconductor device according to a first embodiment. 
         [0019]    As illustrated in  FIG. 1 , a regulator circuit  100  as a semiconductor device will be described in this example. 
         [0020]    Upon receipt of power voltages VDD 1  and VDD 2 , the regulator circuit  100  supplies a predetermined voltage as the output based on a comparison with a reference voltage VREF. In this example, the power voltage VDD 1  is set at a higher voltage than the power voltage VDD 2 . As one example, the power voltage VDD 1  is set at 3.3 V and the power voltage VDD 2  is set at 1.5 V. 
         [0021]    The regulator circuit  100  receives the reference voltage VREF, a trimming signal TRM, a standby standby signal STB, and a timing signal TM. 
         [0022]      FIG. 2  is a circuit diagram of a regulator circuit  100  according to the first embodiment. 
         [0023]    As illustrated in  FIG. 2 , the regulator circuit  100  includes an amplifier (AMP)  50 , a voltage divider  10 , and standby setting circuits  6 A and  6 B. 
         [0024]    The amplifier  50  outputs a voltage amplified based on a comparison between the reference voltage VREF and the voltage of a negative feedback node N 2  as an output voltage VOUT from a node N 0 , with the power voltage VDD 1  as the operation power. 
         [0025]    The voltage divider  10  includes a resistor unit  1  forming a voltage dividing path, switches  3  and  5 , and switching groups  2  and  4 . 
         [0026]    The voltage divider  10  is coupled to the negative feedback node N 2  and outputs the divided voltage obtained by dividing the amplified voltage to the negative feedback node N 2 . 
         [0027]    The resistor unit  1  includes a plurality of resistor elements. In the example, the resistor unit  1  includes resistor groups RG 0  and RG 1  each having a plurality of resistor elements coupled in series. The resistor group RG 0  forms a first voltage dividing path. The resistor group RG 1  forms a second voltage dividing path. The resistor group RG 0  has a higher resistance than the resistor group RG 1 . Therefore, the current amount flowing in the resistor group RG 0  is less than the current amount flowing in the resistor group RG 1 . In this example, two voltage dividing paths will be described; however, it is not restricted to the above but a plurality of voltage dividing paths may be provided. 
         [0028]    The resistor group RG 0  is provided between the node N 0  and a node N 1 . The resistor group RG 1  is provided between the node N 0  and the node N 1  in parallel to the resistor group RG 0  through the switch  3 . 
         [0029]    The resistor group RG 0  includes respective connection nodes N 3 , N 5 , N 7 , N 9 , and N 11  of the respective resistor elements, and divided voltages can be output from the respective connection nodes N 3 , N 5 , N 7 , N 9 , and N 11 . 
         [0030]    The resistor group RG 1  includes respective connection nodes N 4 , N 6 , N 8 , N 10 , and N 12  of the respective resistor elements and divided voltages can be output from the respective connection nodes N 4 , N 6 , N 8 , N 10 , and N 12 . 
         [0031]    The switch  5  is provided between the node N 1  and the ground voltage VSS. The switch  5  receives a standby signal STB 2 . The switch  5  operates according to the standby signal STB 2 . During standby, the switch  5  is not conductive according to the standby signal STB 2  (“L” level). During operation, the switch  5  becomes conductive according to the standby signal STB 2  (“H” level). 
         [0032]    The switching group  2  includes a plurality of transfer gates TF 2  to TF 6  (hereinafter, referred to as a transfer gate TF collectively). 
         [0033]    The transfer gate TF includes P channel MOS transistors and N channel MOS transistors provided in parallel, and an inversion signal of the input signal to the gate of the N channel MOS transistor is input to the gate of the P channel MOS transistor. In this example, it is assumed that the transfer gate TF is conductive when the input signal is at the “H” level, while it is not conductive when the input signal is at the “L” level. Specifically, when the input signal to the transfer gate TF is at the “H” level, the signal of the “H” level is input to the gate of the N channel MOS transistor and the signal of the “L” level is input to the gate of the P channel MOS transistor. According to this, the transfer gate TF becomes conductive. On the other hand, when the input signal to the transfer gate TF is at the “L” level, the signal of the “L” level is input to the gate of the N channel MOS transistor, and the signal of the “H” level is input to the gate of the P channel MOS transistor. According to this, the transfer gate TF is not conductive. 
         [0034]    The transfer gate TF 2  is provided between the connection node N 3  and the connection node N 4 , to be able to short-circuit the respective connection nodes according to a trimming signal TRM 1 . 
         [0035]    The transfer gate TF 3  is provided between the connection node N 5  and the connection node N 6 , to be able to short-circuit the respective connection nodes according to the trimming signal TRM 2 . 
         [0036]    The transfer gate TF 4  is provided between the connection node N 7  and the connection node N 8 , to be able to short-circuit the respective connection nodes according to the trimming signal TRM 3 . 
         [0037]    The transfer gate TF 5  is provided between the connection node N 9  and the connection node N 10 , to be able to short-circuit the respective connection nodes according to the trimming signal TRM 4 . 
         [0038]    The transfer gate TF 6  is provided between the connection node N 11  and the connection node N 12 , to be able to short-circuit the respective connection nodes according to the trimming signal TRM 5 . 
         [0039]    The transfer gates TF 2  to TF 6  respectively short-circuit the connection nodes having the same dividing ratio in the first voltage dividing path of the resistor group RG 0  and in the second voltage dividing path of the resistor group RG 1 . 
         [0040]    The switching group  4  includes a plurality of transfer gates TF 7  to TF 11 . 
         [0041]    The transfer gate TF 7  is provided between the negative feedback node N 2  and the connection node N 3 . The transfer gate TF 7  couples the negative feedback node N 2  and the connection node N 3  according to the trimming signal TRM 6 . 
         [0042]    The transfer gate TF 8  is provided between the negative feedback node N 2  and the connection node N 5  in parallel to the transfer gate TF 7 . The transfer gate TF 8  couples the negative feedback node N 2  and the connection node N 5  according to the trimming signal TRM 7 . 
         [0043]    The transfer gate TF 9  is provided between the negative feedback node N 2  and the connection node N 7  in parallel to the transfer gate TF 8 . The transfer gate TF 8  couples the negative feedback node N 2  and the connection node N 7  according to the trimming signal TRM 8 . 
         [0044]    The transfer gate TF 10  is provided between the negative feedback node N 2  and the connection node N 9  in parallel to the transfer gate TF 9 . The transfer gate TF 9  couples the negative feedback node N 2  and the connection node N 9  according to the trimming signal TRM 9 . 
         [0045]    The transfer gate TF 11  is provided between the negative feedback node N 2  and the connection node N 11  in parallel to the transfer gate TF 10 . The transfer gate TF 11  couples the negative feedback node N 2  and the connection node N 11  according to the trimming signal TRM 10 . 
         [0046]    The transfer gates TF 7  to TF 11  control the connection between the connection node of the resistor unit  1  and the negative feedback node N 2 , to transmit the adjusted dividing voltage to the negative feedback node N 2 . 
         [0047]    Here, the transfer gate TF 2  is associated with the transfer gate TF 7 ; when the trimming signal TRM 1  is set at the “H” level, the trimming signal TRM 6  is also set at the “H” level. The transfer gate TF 3  is associated with the transfer gate TF 8 ; when the trimming signal TRM 2  is set at the “H” level, the trimming signal TRM 7  is also set at the “H” level. The transfer gate TF 4  is associated with the transfer gate TF 9 ; when the trimming signal TRM 3  is set at the “H” level, the trimming signal TRM 8  is also set at the “H” level. 
         [0048]    The transfer gate TF 5  is associated with the transfer gate TF 10 ; when the trimming signal TRM 4  is set at the “H” level, the trimming signal TRM 9  is also set at the “H” level. The transfer gate TF 6  is associated with the transfer gate TF 11 ; when the trimming signal TRM 5  is set at the “H” level, the trimming signal TRM 10  is also set at the “H” level. 
         [0049]    A standby setting circuit  6 A is provided in correspondence with the node N 0 . 
         [0050]    The standby setting circuit  6 A includes the transfer gate TF 1  between the power voltage VDD 2  and the node N 0  and operates according to the standby signal STB 1 . 
         [0051]    A standby setting circuit  6 B is provided in correspondence with the negative feedback node N 2 . 
         [0052]    The standby setting circuit  6 B includes the transfer gate TF 0  between the power voltage VDD 2  and the negative feedback node N 2  and operates according to the standby signal STB 1 . 
         [0053]    During standby, the standby setting circuits  6 A and  6 B are in an active state according to the standby signal STB 1  (“H” level). In short, the power voltage VDD 2  is coupled to the node N 0 . Further, the power voltage VDD 2  is coupled to the negative feedback node N 2 . 
         [0054]    During operation, the standby setting circuits  6 A and  6 B are in an inactive state according to the standby signal STB 1  (“L” level). 
         [0055]      FIG. 3  is a flow chart for use in describing the operation of the regulator circuit  100  according to the first embodiment. 
         [0056]    As illustrated in  FIG. 3 , the regulator circuit  100  performs the standby operation (Step S 0 ). Specifically, standby signals STB 1  (“H” level) and STB 2  (“L” level) are input from a controller not illustrated to the regulator circuit  100 . According to this, the standby setting circuits  6 A and  6 B are in the active state. The negative feedback nodes N 2  and the node N 0  are coupled to the respective power voltages VDD 2 . The switch  5  is in a non-conductive state. In this case, the current path is shut down. The controller sets some of the trimming signals TRM 6  to TRM 10  at the “H” level. Further, the controller sets some of the trimming signals TRM 1  to TRM 5  at the “H” level. 
         [0057]    According to the trimming signal TRM, the transfer gate TF of the corresponding switching group  2  or  4  becomes conductive. The connection node is short-circuited according to the conduction of the transfer gate TF in the switching group  2 . Further, the transfer gate TF of the corresponding switching group  4  becomes conductive according to the trimming signal TRM. The conductive connection node is electrically coupled to the negative feedback node N 2  and the dividing voltage of a predetermined dividing ratio is input to the amplifier  50 . 
         [0058]    The trimming signal TRM is previously set at some dividing voltage fixed based on the dividing ratio of the trimming signal TRM according to a test with consideration of the element dispersion in a semiconductor device. For example, when the output voltage as the result of a test after the regulator circuit designed is near the initial value, the trimming signal set in the initial state is used. On the other hand, when it is deviated from the initial value, the output voltage is adjusted to the trimming signal for outputting the initial value. The adjusted trimming signal information is set in a register (not illustrated). In this example, the case of setting the trimming signal TRM previously according to the information set in the register is described; alternatively, the trimming signal TRM may be adjusted again through a later test simulation. 
         [0059]    The timing signal TM is set at the “H” level and according to this, the switch  3  becomes conductive. 
         [0060]    Then, the regulator circuit  100  turns on (ON) the circuit operation (Step S 2 ). Specifically, the standby signals STB 1  (“L” level) and STB 2  (“H” level) are input from the controller not illustrated to the regulator circuit  100 . 
         [0061]    According to the standby signal STB 1  set at the “L” level, the standby setting circuits  6 A and  6 B are in the inactive state. 
         [0062]    According to the standby signal STB 2  set at the “H” level, the switch  5  becomes conductive, to form a current path. 
         [0063]    In this case, since the current path in the first voltage dividing path and the second voltage dividing path is formed, the current amount is increased. 
         [0064]    The potential of the negative feedback node N 2  is extracted from the connection node and when it becomes the same potential as the reference voltage VREF, the above potential gets stable according to the amplifier control. 
         [0065]    The output voltage VOUT from the node N 0  becomes a stable voltage when the potential gets stable according to the amplifier control. 
         [0066]    At this point, a speed of the output voltage VOUT transiently changing after activating the regulator circuit  100 , depends on the current amount flowing through the regulator circuit  100  and the response speed of the amplifier  50 . 
         [0067]    At the activation, the current amount is increased in order to speed up the rising of the output voltage VOUT. In this example, since the current path is formed in the first voltage dividing path and the second voltage dividing path, the current amount is increased. 
         [0068]    Next, the timing signal TM is adjusted (Step S 4 ). Specifically, the timing signal TM is set at the “L” level. The controller, not illustrated, has a timer function and after a predetermined elapse of time from turning on (ON) the circuit operation, it sets the timing signal TM at the “L” level. 
         [0069]    The predetermined time corresponds to the period of stabilizing the output voltage VOUT according to the amplifier control. The predetermined time can be set by previously measuring it through the simulation. 
         [0070]    Further, the short-circuit path is turned OFF (Step S 5 ). Specifically, all the trimming signals TRM 1  to TRM 5  of short-circuiting the connection nodes are set at the “L” level. According to this, all the transfer gates TF 2  to TF 6  are turned OFF. Accordingly, the short-circuit path being conductive is set to in a non-conductive state. Here, although the case of adjusting the timing signal TM and simultaneously turning OFF the short-circuit will be described, the short-circuit may be turned OFF before adjusting the timing signal TM. 
         [0071]    By adjusting the timing signal TM (=set at the “L” level), the switch  3  becomes non-conductive. Then, the second voltage dividing path is turned OFF (Step S 6 ). In other words, the current path having a large current amount is shut down. 
         [0072]    Whether the operation of the regulator circuit  100  is finished or not is checked (Step S 8 ), the above state is kept until it is finished; when the above operation is finished (YES in Step S 8 ), the processing is returned to Step S 0 . The processing thereafter is the same. The case of finishing the operation is the case of inputting the standby signals STB 1  (“H” level) and STB 2  (“L” level) from the controller to the regulator circuit  100 . 
         [0073]    In this example, after the output voltage VOUT is in a stable state, the current is narrowed by shutting down the second voltage dividing path. According to this, the power consumption on the whole circuit can be reduced. 
         [0074]    The transfer gate TF in the switching group  2  short-circuits the first voltage dividing path and the second voltage dividing path with the same dividing ratio, which makes it possible to suppress the propagation of a switchover noise to the negative feedback node N 2  occurring upon the switchover of the number of the voltage dividing paths. 
         [0075]    By increasing the operation current of the amplifier  50 , a responsibility of the negative feedback can be improved, overshoot or undershoot of the output voltage VOUT is reduced during circuit activation, and the time taken to stabilize the output voltage VOUT in the circuit activation can be reduced. 
         [0076]    During standby, the current consumption on the whole circuit can be suppressed. 
       Second Embodiment 
       [0077]      FIG. 4  is a view for use in describing a circuit structure of a regulator circuit  102  according to a second embodiment. 
         [0078]    As illustrated in  FIG. 4 , the regulator circuit  102  is different from the regulator circuit  100  having been described in  FIG. 1  in that the amplifier  50  is replaced with an amplifier  50 #. 
         [0079]    The other structure is the same as described in  FIG. 1 ; their detailed description is not repeated. 
         [0080]    The amplifier  50 # includes a current adjusting unit  7  formed by the P channel MOS transistors PT 1  to PT 5 , P channel MOS transistors PT 6  to PT 8 , and N channel MOS transistors NT 1  and NT 2 . 
         [0081]    The P channel MOS transistors PT 1  to PT 5  are coupled between the power voltage VDD 1  and the node N 14  in parallel, to receive the adjustment signals AP 1  to AP 5  respectively. 
         [0082]    The P channel MOS transistor PT 6  is provided between the node N 14  and the node N 13  and its gate receives the reference voltage VREF. The N channel MOS transistor NT 1  is provided between the node N 13  and the node N 15  and its gate is coupled to the node N 16 . The node N 15  is coupled to the ground voltage VSS. 
         [0083]    The N channel MOS transistor NT 2  is provided between the node N 15  and the node N 16  and its gate is coupled to the node N 16 . 
         [0084]    The P channel MOS transistor PT 7  is provided between the node N 14  and the node N 16  and its gate is coupled to the negative feedback node N 2 . 
         [0085]    The P channel MOS transistor PT 8  is provided between the power voltage VDD 1  and the node N 0 , and its gate is coupled to the node N 13 . 
         [0086]    The current adjusting unit  7  adjusts the operation current amount according to the adjustment signals AP 1  to AP 5 . When all the adjustment signals AP 1  to AP 5  are at the “L” level, the operation current gets larger. 
         [0087]    Further, of the adjustment signals AP 1  to AP 5 , according as the number of the adjustment signals with the “L” level is reduced, the operation current becomes smaller. 
         [0088]    In order to make the operation current the minimum, only the adjustment signal AP 1  may be set at the “L” level. 
         [0089]    The amplifier  50 # forms a differential amplifier and by comparison between the reference voltage VREF and the voltage of the negative feedback node N 2 , the voltage depending on the comparison is output to the node N 13  coupled to the gate of the P channel MOS transistor PT 8 . According to this, the amplified voltage is output as the output voltage VOUT. 
         [0090]    In the second embodiment, at the activation time, the current amount is increased in order to speed up the rising of the output voltage VOUT. In this example, the current path is formed in the first voltage dividing path and in the second voltage dividing path; and therefore, the current amount is increased. Together with this, all the adjustment signals AP 1  to AP 5  are set at the “L” level. According to this, the operation current amount of the amplifier  50 # increases, hence to make it possible to speed up the response of the amplifier  50 #. After the output voltage VOUT is in the stable state, the second voltage dividing path is shut down according to the timing signal TM and the adjustment signals AP 2  to AP 5  are set at the “H” level. Specifically, the operation current amount of the amplifier  50 # is narrowed. According to this, the operation current in the amplifier  50 # is reduced and the current consumption amount can be reduced. 
         [0091]      FIG. 5  is a flow chart for use in describing the operation of the regulator circuit  102  according to the second embodiment. 
         [0092]    As illustrated in  FIG. 5 , by comparison with the flow of  FIG. 3 , Step S 7  is further added differently from the first embodiment. The other structure is the same as in  FIG. 3  and their detailed description is not repeated. Specifically, in Step S 7 , the second voltage dividing path is shut down according to the timing signal TM and the current of the amplifier  50 # is adjusted. For example, the adjustment signals AP 2  to AP 5  are set at the “H” level. According to this, the current amount of the amplifier  50 # is adjusted. As the result, the current consumption amount of the amplifier  50 # can be reduced. 
       Modified Example of Second Embodiment 
       [0093]      FIG. 6  is a circuit diagram of a regulator circuit  104  according to a modified example of the second embodiment. 
         [0094]    As illustrated in  FIG. 6 , the regulator circuit  104  is different from the regulator circuit  102  having been described in  FIG. 4  in that the amplifier  50 # is replaced with an amplifier  51 . The other structure is the same as in the regulator circuit having been described in  FIG. 4  and the detailed description is not repeated. 
         [0095]    The amplifier  51  is different from the amplifier  50 # in that the switches  8 A to  8 C are further added. The other structure is the same as that having been described in  FIG. 4  and the detailed description is not repeated. 
         [0096]    The switch  8 A is a power switch provided between the P channel MOS transistor PT 8  and the power voltage VDD 1 , to receive the standby signal STB 3 . 
         [0097]    The switch  8 B is a power switch provided between the power voltage VDD 1  and the node N 13 , to receive the standby signal STB 4 . 
         [0098]    The switch  8 C is a power switch provided between the power voltage VDD 1  and the current adjusting unit  7 , to receive the standby signal STB 5 . 
         [0099]    The regulator circuit includes the current adjusting unit  7  formed by the P channel MOS transistors PT 1  to PT 5 , the P channel MOS transistors PT 6  to PT 8 , and the N channel MOS transistors NT 1  and NT 2 . 
         [0100]      FIG. 7  is a timing chart of the regulator circuit  104  according to the modified example of the second embodiment. 
         [0101]    As illustrated in  FIG. 7 , in the initial state, the standby signal STB 1  is set at the “H” level. Further, the standby signal STB 2  is set at the “L” level. Further, the standby signals STB 3  and STB 5  are set at the “H” level. Further, the standby signal STB 4  is set at the “L” level. Further, the timing signal TM is set at the “H” level. 
         [0102]    Further, in this example, the trimming signals TRM 1  and TRM 6  are set at the “H” level. The other trimming signals are set at the “L” level. 
         [0103]    Since the standby signal STB 1  is set at the “H” level, the standby setting circuit  6 A is turned on, and the output voltage VOUT is fixed at the voltage level of the power voltage VDD 2 . Further, the standby setting circuit  6 B is turned on and the negative feedback node N 2  is coupled to the power voltage VDD 2  and set at the “H” level. 
         [0104]    Since the standby signal STB 2  is set at the “L” level, the switch  5  is turned off. Therefore, the current path is not formed. 
         [0105]    Since the standby signal STB 3  is set at the “H” level, the switch  8 A is turned off. 
         [0106]    Since the standby signal STB 4  is set at the “L” level, the switch  8 B is turned on. Therefore, the node N 13  is coupled to the power voltage VDD 1  and is set at the “H” level. 
         [0107]    Since the standby signal STB 5  is set at the “H” level, the switch  8 C is turned off. 
         [0108]    The trimming signals TRM 1  and TRM 6  are set at the “H” level, hence to make the transfer gate TF of the switching groups  2  and  4  conductive. The negative feedback node N 2  is electrically coupled to the connection node N 3 . The connection node N 3  is electrically coupled to the connection node N 4 . 
         [0109]    At the time T 0 , when the circuit operation is turned on (ON), the standby signal STB 1  is set at the “L” level. The standby signal STB 2  is set at the “H” level. The standby signals STB 3  and STB 5  are set at the “L” level. The standby signal STB 4  is set at the “H” level. The timing signal TM is kept in the “H” level. 
         [0110]    According to the standby signal STB 1  being set at the “L” level, the standby setting circuits  6 A and  6 B are in an inactive state. Further, according to the standby signal STB 2  being set at the “H” level, the switch  5  becomes conductive, to form the current path. 
         [0111]    In this case, since the current path is formed in the first voltage dividing path and in the second voltage dividing path, the current amount increases. 
         [0112]    When the potential of the negative feedback node N 2  is extracted from the connection node to be at the same potential as the reference voltage VREF, it becomes stable according to the amplifier control. When it is stabilized by the amplifier control, the output voltage VOUT also becomes a stable voltage. 
         [0113]    From this point of view, the transiently-changing speed of the output voltage VOUT depends on the current amount flowing through the regulator circuit  100  and the response speed of the amplifier  51 . 
         [0114]    At the activation time, the current amount is increased in order to speed up the rising of the output voltage VOUT. In this example, the current path is formed in the first voltage dividing path and in the second voltage dividing path, hence to increase the current amount. 
         [0115]    Next, at the time T 1 , the timing signal TM is adjusted. Specifically, the timing signal TM is set at the “L” level. According to this, the switch  3  becomes non-conductive. The second voltage dividing path is turned OFF. In short, the current path having a larger current amount is shut down. According to this, the current is narrowed. 
         [0116]    Further, the trimming signal TRM 1  is set at the “L” level. According to this, the short-circuit path of the connection nodes N 3  and N 4  is turned OFF. The potential of the connection node N 4  rises. 
         [0117]    Further, the potential of the node N 12 # on the side of the drain of the switch  3  rises. 
         [0118]    In this example, after the output voltage VOUT is in the stable state, the current is narrowed by shutting down the second voltage dividing path. According to this, the power consumption on the whole circuit can be reduced. 
         [0119]    Further, the transfer gate TF in the switching group  2  short-circuits the first voltage dividing path and the second voltage dividing path with the same dividing ratio, which can suppress the propagation of a switchover noise to the negative feedback node N 2  occurring when the number of the voltage dividing paths is switched. 
         [0120]    The operation current of the amplifier  51  is increased, which can improve the responsibility of the negative feedback, reduce the overshoot or the undershoot of the output voltage VOUT in the circuit activation, and reduce the time taken to stabilize the output voltage VOUT in the circuit activation. 
         [0121]    As set forth hereinabove, the disclosure has been specifically described based on the embodiments; however, the disclosure is not restricted to the embodiments but it is needless to say that various modifications are possible without departing from the spirit.