Abstract:
An input buffer circuit compensates for a data hold time and reduces an operational current by implementing a delay operation with transistors having a long channel when the input buffer circuit is driven by a high external voltage. The input buffer circuit includes a delay unit to delay an input signal, the delay unit being powered by an external power voltage and having an associated variable delay which is varied according to a detection signal and the external power voltage, the detection signal indicating whether the external power voltage is high or low.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an input buffer circuit, and in particular to an input buffer circuit which can compensate for a data hold time and reduce an operational current. 
     2. Description of the Background Art 
     FIG. 1 is a circuit diagram illustrating a conventional input buffer circuit  5 . Referring to FIG. 1, the input buffer circuit  5  includes: a NOR gate NOR 1  NORing a data signal DIN inputted to a data input pad and a control signal WECS into which an enable signal WE and a chip selection signal CS are combined; and a delay unit  1 , having first to n-th inverters INV 1 ˜INVn delaying an output signal from the NOR gate NOR  1 . 
     The first inverter INV 1  of the delay unit  1  includes: first and second PMOS transistors PM 1 , PM 2  and first and second NMOS transistors NM 1 , NM 2  connected in series between an external power voltage VCC and a ground voltage VSS. The gates of PM 1 , PM 2 , NM 1  and NM 2  are commonly connected to form an input terminal receiving an output signal from the NOR gate NOR 1 , and drains of the second PMOS transistor PM 2  and the first NMOS transistor NM 1  are commonly connected to form an output terminal outputting an output signal. 
     Each inverter INV 2 ˜INVn−1 is identically constituted to the first inverter INV 1 , and thus each input terminal is connected to an output terminal of a preceding inverter, and each output terminal is connected to an input terminal of a succeeding inverter. 
     In addition, the n-th inverter INVn is identically constituted to the first inverter INV  1 . Thus, an output signal from a preceding inverter INVn−1 is inputted to its input terminal, and an input data DATAIN is outputted from its output terminal. 
     The operation of the thusly-constituted input buffer circuit will now be described with reference to FIGS. 2A-2D. 
     First, when the data signal DIN as shown in FIG.  2 A and the low-level control signal WECS as shown in FIG. 2B are inputted, if a low external power voltage VCCL is applied to the input buffer circuit at the inverters&#39;respective VCC terminals, the data signal DIN is delayed by the delay unit  1 , and thus outputted as the input data DATAIN as shown in FIG.  2 C. 
     On the other hand, when the data signal DIN as shown in FIG.  2 A and the low-level control signal WECS as shown in FIG. 2B are inputted, if a high external power voltage VCCH is applied to the input buffer circuit at the inverters&#39;respective VCC terminals, the data signal DIN is delayed by the delay unit  1 , and thus outputted as the input data DATAIN as shown in FIG.  2 D. 
     As illustrated in FIG. 2D, when the delay unit  1  is driven by the high external power voltage VCCH, not the low external power voltage VCCL, a driving current is increased as much as the external power voltage VCC rises. Thus each inverter INV 1 ˜INVn operates rapidly. Accordingly, a delay rate is lowered. 
     When the conventional input buffer circuit  5  is operated by the high external power voltage VCCH during a write operation, one must add more inverters in order to obtain a sufficiently long data hold time. However, when the low external power voltage VCCL is applied, the conventional input buffer circuit is delayed due to the additional inverters. Thus its operational speed becomes slower. 
     Also, when the delay unit  1  is operated by the high external power voltage VCCH, the driving current is increased. 
     SUMMARY OF THE INVENTION 
     Accordingly, the present invention is directed to an input buffer that substantially obviates one or more of the problems due to limitations and disadvantages of the related art. 
     In accordance with the purpose of the invention, as embodied and broadly described, one aspect the invention includes a delay unit to delay an input signal, the delay unit being powered by an external power voltage and having an associated variable delay which is varied according to a detection signal and the external power voltage, the detection signal indicating whether the external power voltage is high or low. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
     The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate one embodiment of the invention and together with the description serve to explain the principles of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become better understood with reference to the accompanying drawings which are given only by way of illustration and thus are not limitative of the present invention, wherein: 
     FIG. 1 is a circuit diagram illustrating a conventional input buffer circuit; 
     FIGS. 2A-2D are operational timing diagrams where an external power voltage is high and low in the configuration of FIG. 1; 
     FIG. 3 is a circuit diagram illustrating an input buffer circuit in accordance with the present invention; 
     FIG. 4 is a detailed circuit diagram illustrating an external power voltage detection unit for the configuration of FIG. 3; 
     FIGS. 5A-5D are operational timing diagrams where a low external power voltage is applied in the configuration of FIG. 3; and 
     FIGS. 6A-6D are operational timing diagrams where a high external power voltage is applied in the configuration of FIG.  3 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention provides an input buffer circuit which can obtain a sufficient data hold time and reduce a driving current without requiring an additional inverter, even when a high external power voltage is applied. The present invention does this by employing inverters having different delay rates according to the high or low external power voltage. 
     An input buffer circuit in accordance with a preferable embodiment of the present invention will now be described in detail with reference to the accompanying drawings. 
     FIG. 3 is a circuit diagram illustrating an input buffer circuit  15  in accordance with present invention. Referring to FIG. 3, the input buffer circuit  15  includes: a NOR gate NOR 10  NORing a data signal DIN inputted to a data input pad and a control signal WECS into which a write enable signal WE and a chip selection signal CS are combined. The input buffer circuit  15  also includes a delay unit  10  having first to n-th inverters INV 11 -INV 1 n to delay an output signal from the NOR gate NOR 10 . Also included is an external power voltage detection unit  20  detecting whether an external power voltage is high or low; and an inverter INVB inverting an output signal PWDET from the external power voltage detection unit  20 . The output signal PWDET indicates whether the external power voltage VCC is high or low. 
     Here, the first inverter INV 11  of the delay unit  10  includes: a first PMOS transistor PM 11  and a first NMOS transistor NM 11  having their gates commonly connected to form an input terminal receiving an output signal from the NOR gate NOR 10 , and having their drains commonly connected to form an output terminal. The inverter INV 11  also includes a second PMOS transistor PM 12  and a third PMOS transistor PM 13  connected in series between the external power voltage VCC and, a source of the first PMOS transistor PM 11 . A gate of the second PMOS transistor PM 12  is connected to a ground voltage VSS and a gate of the third PMOS transistor PM 13  receives a detection signal PWDET outputted from the external power voltage detection unit  20 . The first inverter INV 11  also includes a second NMOS transistor NM 12  and a third NMOS transistor NM 13  connected in series between a source of the first NMOS transistor NM 11  and the ground voltage VSS. A gate of the second NMOS transistor NM 12  receives the external power voltage VCC and, a gate of the third NMOS transistor NM 13  receives an inverted signal/PWDET of the detection signal PWDET. Also included in the first inverter INV 11  are a fourth PMOS transistor PM 14  and a fifth PMOS transistor PM 15  connected in series between the source of the first PMOS transistor PM  11  and the external power voltage VCC. A gate of the fourth PMOS transistor PM 14  is connected to the ground voltage VSS and, a gate of the fifth PMOS transistor PM 15  receives the inverted signal/PWDET. A fourth NMOS transistor NM 14  and a fifth NMOS transistor NM 15  are connected in series between the source of the first NMOS transistor NM 11  and the ground voltage VSS and, a gate of the fourth NMOS transistor NM 14  receives the external power voltage VCC. A gate of the fifth NMOS transistor NM 15  receives the detection signal PWDET outputted from the external power voltage detection unit  20 . 
     Here, channels of the second and third PMOS transistors PM 12 , PM 13  and the second and third NMOS transistors NM 12 , NM 13  are short and wide. Channels of the fourth and fifth PMOS transistors PM 14 , PM 15  and the fourth and fifth NMOS transistors NM 14 , NM 15  are long and narrow. 
     In addition, the gates of the third PMOS transistor PM 13 , and fifth NMOS transistor NM 15  receive the detection signal PWDET outputted from the external power voltage detection unit  20  and the gates of the third NMOS transistor NM 13  and fifth PMOS transistor PMOS 15  receive the inverted signal/PWDET inverted by the inverter INVB. These transistors serve as switching units selectively switching by whether the external power voltage VCC is high or low. 
     The second to n-th inverters INV 12 ˜INV 1 n of the delay unit  10  are identically constituted to the first inverter INV 11 . Each input terminal receives an output signal from a preceding inverter, and each output terminal is connected to an input terminal of a succeeding inverter. An input data DATAIN is outputted from the output terminal of the n-th inverter INV 1 n. 
     As illustrated in FIG. 4, the external power voltage detection unit  20  includes: an n+1st inverter INV 21  to invert the control signal WECS. The detection unit  20  also includes a sixth PMOS transistor PM 26  and a sixth NMOS transistor NM 26  connected in series between the external power voltage VCC and the ground voltage VSS. Their gates are commonly connected to form an input terminal, and their drains are commonly connected to form an output terminal. A seventh PMOS transistor PM 27  is connected to PM 26  and its gate receives the control signal WECS. A seventh NMOS transistor NM 27  is connected to NM 26  and its gate receives an inverted signal/WECS of the control signal WECS. Eighth to n-th NMOS transistors NM 28 ˜NM 2 n are connected in series between the external power voltage VCC and the input terminal, and have their gates and drains respectively commonly connected. An n+2nd inverter INV 22  inverts a voltage of the output terminal, and outputting the detection signal PWDET. An eighth PMOS transistor PM 28  has its source connected to receive the external power voltage VCC, its drain connected to the output terminal, and its gate connected to receive the inverted signal/WECS. 
     Here, the eighth to n-th NMOS transistors NM 28 ˜NM 2 n are used to lower the external power voltage VCC. The number of the NMOS transistors used is determined to lower the voltage to the extent that the sixth PMOS transistor PM 26  is turned off and the sixth NMOS transistor NM 26  is turned on when the high external power voltage VCCH is applied, and to the extent that the sixth PMOS transistor PM 26  is turned on and the sixth NMOS transistor NM 26  is turned off when the low external power voltage VCCL is applied. In addition, when the control signal WECS is at a high level, the eighth PMOS transistor PM 28  makes the detection signal PWDET a low-level signal, regardless of whether the external power voltage VCC is high or low. 
     The operation of the input buffer circuit according to the present invention will now be described with reference to the accompanying drawings. 
     First, when the low external power voltage VCCL is applied, the data signal DIN as shown in FIG.  5 A and the control signal WECS as shown in FIG. 5B are combined by the NOR gate NOR 10 , inputted to and delayed by the delay unit  10 , and outputted as the input data DATAIN as shown in FIG.  5 D. 
     Here, the control signal WECS is at a low level as shown in FIG.  5 B and the low external power voltage VCCL is inputted. Thus the external power voltage detection unit  20  outputs the low-level detection signal PWDET as shown in FIG.  5 C. 
     Accordingly, the third PMOS transistors PM 13  and the third NMOS transistors NM 13  of the inverters INV 11 ˜INVn of the delay unit  10  are turned on, the fifth PMOS transistors PM 15  and the fifth NMOS transistors NM 15  thereof are turned off. Thus the inverters INV 11 ˜INVn have a long delay. As a result, the data signal DIN inputted to the input pad is outputted as the input data DATAIN, delayed by a first delay width TD 1  as shown in FIG.  5 D. 
     The channels of the third and fourth PMOS transistors PM 13 , PM 14  and the third and fourth NMOS transistors NM 13 , NM 14  are short and wide, and thus inverters incorporating these transistors have a long delay. 
     On the other hand, when the high external power voltage VCCH is applied, the data signal DIN as shown in FIG.  6 A and the control signal WECS as shown in FIG. 6B are combined by the NOR gate NOR  10 , inputted to and delayed by the delay unit  10 , and outputted as the input data DATAIN. Here, the control signal WECS is at a high level as shown in FIG.  6 B and the high external power voltage VCCH is inputted. Thus, the external power voltage detection unit  20  outputs the high-level detection signal PWDET as shown in FIG.  6 C. 
     Accordingly, the third PMOS transistors PM 13  and the third NMOS transistors NM 13  of the inverters INV 11 ˜INVn of the delay unit  10  are turned off, the fifth PMOS transistors PM 15  and the fifth NMOS transistors NM 15  thereof are turned on. Thus, each inverter INV 11 ˜INVn of the delay unit  10  has a short delay. As a result, the data signal DIN inputted to the data input pad is outputted as the input data DATAIN delayed by a second delay width TD 2 , as shown in FIG.  6 D. 
     The channels of the fourth and fifth PMOS transistors PM 14 , PM 15  and the fourth and fifth NMOS transistors NM 14 , NM 15  are long and narrow. Thus the inverters have a short delay. 
     As described above, when the high external power voltage VCCH is applied, the inverters include the transistors PM 14 , PM 15 , NM 14 , NM 15  which have a long and narrow channel far decreasing the delay. To the contrary, when the low external power voltage VCCL is applied, the inverters include the transistors PM 12 , PM 13 , NM 12 , NM 13  which have a short and wide channel far increasing the delay. Here, a level of the external power voltage VCC is detected by detection unit  20 , and according to the detection result, the inverter having a short or long delay is selectively employed by a switching operation. 
     The input buffer circuit in accordance with the present invention can obtain a sufficient data hold time and reduce the driving current by using the inverter having the short delay when the high external power voltage VCCH is applied, and can improve an operational speed by using the inverter having the long delay when the low external power voltage VCCL is applied. 
     Of course, the present invention is not limited to the disclosed embodiment. The present invention includes any delay element, such as another logic gate other than an inverter, having at least two parallel transistors, one of which is selected based on a detected voltage level. The transistors in this alternate embodiment may, but need not, have differing channel geometries in accordance with the operation of the preferred embodiment. The present invention also includes any voltage sensing circuit, when used in conjunction with the above-described delay element. For example, the circuit which generates VCCL and VCCH could also generate a logical signal, to be input to the PWDET terminal, indicating which VCC level had been generated. 
     As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiment is not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalencies of such meets and bounds are therefore intended to be embraced by the appended claims.