Abstract:
A boost circuit reduces the consumed current during a startup condition of the boost circuit. The boost circuit comprises a plurality of charge pump circuit stages, each the charge pump circuit stage having a V i  input, a clock input, and a V o  output, each circuit stage providing a voltage at the V o  output which is higher than a voltage at the V i  input, the V i  input of a first of the circuit stages being connected to a power supply voltage, each of the plurality of circuit stages other than the first stage having the V i  input connected to the V o  output of an immediately preceding the circuit stage; wherein during a startup condition, each of the clock signals transitions from an inactive state to a reciprocating state, the transition of each of the clock signals being delayed by at least one clock cycle with respect to each transition of the clock signal supplied to each preceding stage.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates in general to a boost circuit, and more particularly to a boost circuit which is designed in such a way as to reduce the power source current when activating the boost circuit. 
     2. Description of the Related Art 
     A configuration of a prior art example of a boost circuit is shown in FIG. 15 and a timing chart thereof is shown in FIG.  16 . 
     In this circuit, boosting operation is terminated by setting CTL at a low level. Since output node P 1  of a NAND  151  which has received that input is held at a high level irrespective of the level of the input from CLK, the boosting operation is not carried out in each of pumping circuits  158 A to  158 H. 
     On the other hand, CTL is set to a high level to allow the boosting operation. A clock signal which has been inputted to the CLK is inverted to be outputted from the NAND  151 . The pumping circuits  158 A to  158 H, each of which has received the inverted clock signal, start the boosting operation at the same time. 
     Some semiconductor devices receive an external electric wave to activate the internal power source on the basis of the electric wave thus received. One example is the noncontact IC card, for which an increase of demand is expected. In such device there arises the problem that the power source voltage is reduced due to the increase of the power source current when starting the boosting operation. 
     In this connection, FIG. 19 is a graphical representation showing the simulation result of this circuit. In the figure, reference numeral  251  designates a waveform of a boosted voltage (VPP) and reference numeral  252  designates a waveform of a power source current (IDD). The boosted voltage of this circuit is 17.0 V and the peak current thereof is 842 μA. 
     Next, a circuit diagram disclosed in Japanese Patent Application Laid-open No. Hei 268294 is shown in FIG. 17 and a timing chart thereof is shown in FIG.  18 . 
     In this circuit, a clock signal is inputted from a CLK and pumping circuits  204 A to  204 H each of which has received the clock signal thus inputted thereto start the boosting operation. A point of difference between this circuit and that circuit shown in FIG. 15 is that the voltage which has been boosted in the pumping circuit  204 A in the previous stage is used as the power source of a level shifter  201 B which is the constituent element of the pumping circuit  204 B in the next stage. Likewise, the voltages which have been respectively boosted in the pumping circuits in the previous stages are used as the power sources of level shifters  201 C to  201 H, respectively. 
     However, in this boost circuit, the level shifters are used in the clock driver. As a result, since the output of each of the level shifters becomes equal to or lower than 0 V when starting the boosting operation, the switching device provided between the pumping circuits needs to be comprised of an N-channel enhancement MOS transistor having Vt which is larger than 0 V. 
     Therefore, the voltage which is transferred to the next stage during the boosting operation is expressed by the following expression: 
     
       
           VDD−Vt   (1) 
       
     
     and hence the transferred voltage is lost by Vt as compared with the prior art example. 
     Since the loss of voltage in the transferred voltage occurs in each of the stages of the pumping circuits  204 A to  204 H, there arises the problem that it takes a lot of time to boost the voltage. 
     In this connection, FIG. 20 is a graphical representation showing the simulation result of this circuit which has the pumping circuits of four stages. In the figure, reference numeral  261  designates a waveform of the boosting voltage (VPP), and reference numeral  262  designates a waveform of the power source current (IDD). The boosting voltage of this circuit is 5.3 V and the peak current thereof is equal to or larger than 10 mA. 
     In addition, FIG. 21 is a graphical representation showing the simulation result of this circuit which has the pumping circuits of eight stages. In the figure, reference numeral  271  designates a waveform of the boosted voltage (VPP) and reference numeral  272  designates a waveform of the power source current (IDD). 
     SUMMARY OF THE INVENTION 
     In light of the foregoing, the present invention has been made in order to solve the above-mentioned problems associated with the prior art, and it is therefore an object of the present invention to provide a novel boost circuit which is designed in such a way as to reduce the consumed current when activating the boost circuit. 
     In order to attain the above-mentioned object, the present invention adopts the following technical configurations. 
     The first aspect of the present invention provides a boost circuit comprising: a plurality of charge pump circuit stages, each charge pump circuit stage having a V i  input, a clock input, and a V o  output, each circuit stage providing a voltage at the V o  output which is higher than a voltage at the V i  input, the V i  input of a first of the circuit stages being connected to a power supply voltage, each of the plurality of circuit stages other than the first stage having its V i  input connected to the V o  output of an immediately preceding circuit stage. During a startup condition, each of the clock signals transitions from an inactive state to a reciprocating state, the transition of each of the clock signals being delayed by at least one clock cycle with respect to each transition of the clock signal supplied to each preceding stage. 
     In addition, the second aspect of the present invention provides a boost circuit comprising a first multi-stage charge pump circuit receiving a first clock signal at a first level and an input, the first multi-stage charge pump circuit producing a first output voltage having a higher voltage level than the input voltage, a level shifter receiving the first output voltage, the level shifter having a level shifter clock input and a shifted clock output, the level shifter producing a second clock signal at the shifted clock output having a predetermined higher voltage level than an input clock signal received at the level shifter clock input, and a second multi-stage charge pump circuit receiving the first output voltage and the second clock signal, the second multi-stage charge pump circuit producing a second output voltage having a higher voltage level than the first output voltage. Each stage of the second multi-stage charge pump circuit has a clock input which receives a clock signal at the predetermined higher voltage when the multi-stage charge pump reached steady state. 
     According to the present invention, the charge pump circuits are prevented from starting the boosting operation at the same time when activating the boost circuit. 
     As a result, there is obtained the effect that it is possible to reduce the power source current consumption when starting the boosting operation. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings wherein: 
     FIG. 1 is a circuit diagram showing a configuration of a boost circuit of a first embodiment of the present invention. 
     FIG. 2 is a block diagram showing a configuration of a clock generating circuit of the first embodiment. 
     FIG. 3 is a timing chart explaining the operation of the first embodiment. 
     FIG. 4 is a block diagram showing a configuration of the boost circuit of a second embodiment of the present invention. 
     FIG. 5 is a circuit diagram showing a configuration of a first boost circuit of the second embodiment. 
     FIG. 6 is a circuit diagram showing a configuration of a second boost circuit of the second embodiment. 
     FIG. 7 is a circuit diagram showing a configuration of a level shifter of the second embodiment. 
     FIG. 8 is a timing chart explaining the operation of the second embodiment. 
     FIG. 9 is a block diagram showing a configuration of a third embodiment of the present invention. 
     FIG. 10 is a circuit diagram showing a configuration of a first boost circuit of a third embodiment. 
     FIG. 11 is a circuit diagram showing a configuration of a second boost circuit of the third embodiment. 
     FIG. 12 is a circuit diagram showing a configuration of a level shifter of the third embodiment. 
     FIG. 13 is a block diagram showing a configuration of a clock generating circuit of the third embodiment. 
     FIG. 14 is a timing chart explaining the operation of the third embodiment. 
     FIG. 15 is a circuit diagram showing a configuration of a boost circuit of a prior art example. 
     FIG. 16 is a timing chart explaining the operation of the boost circuit of the prior art example shown in FIG.  15 . 
     FIG. 17 is a circuit diagram showing a configuration of the boost circuit of another prior art example. 
     FIG. 18 is a timing chart explaining the operation of the boost circuit of another prior art example shown in FIG.  17 . 
     FIG. 19 is a graphical representation showing the simulation result for the boost circuit of the prior art example shown in FIG.  15 . 
     FIG. 20 is a graphical representation showing the simulation result for the boost circuit of another prior art example shown in FIG.  17 . 
     FIG. 21 is a graphical representation showing the simulation result for the boost circuit which is configured by changing the configuration of the boost circuit of another prior art example shown in FIG.  17 . 
     FIG. 22 is a graphical representation showing the simulation result for the boost circuit of the first embodiment shown in FIG.  1 . 
     FIG. 23 is a graphical representation showing the simulation result for the boost circuit of the second embodiment shown in FIG.  4 . 
     FIG. 24 is a graphical representation showing the simulation result for the boost circuit which is obtained by changing the configuration of the boost circuit of the second embodiment shown in FIG.  4 . 
     FIG. 25 is a graphical representation showing the simulation result for the boost circuit of the third embodiment shown in FIG.  9 . 
     FIG. 26 is a diagram showing the simulation results of the peak current, the boosting time and the boosted voltage in the individual boost circuits. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Embodiment 1 
     The boost circuit of the first embodiment includes: a control signal CTL which is used to control the boosting operation; a clock signal CLK; an N-channel non-doped MOS transistor  5  whose source is electrically connected to a power source VDD; a inverter  6  whose output is electrically connected to a gate of the N-channel non-doped MOS transistor  5 ; and pumping circuits  4 A to  4 H; and the clock generating circuit  7  for successively supplying respectively the clock signals. 
     The pumping circuits  4 A to  4 H comprises N-channel non-doped MOS transistors  3 A to  3 H, capacitors  2 A to  2 H and inverters  1 A to  1 H, respectively. The N-channel MOS transistors  3 A to  3 H are electrically connected in series between the N-channel non-doped MOS transistor  5  and output terminal V OUT . One end of the capacitors  2 A to  2 H are respectively electrically connected to the gates of the N-channel MOS transistors  3 A to  3 H. The inverters  1 A to  1 H receive the respective clock signals at the input terminals and provide the inverted clock signals of the clock signals to the other terminals of the capacitors  2 A to  2 H. 
     The clock generating circuit  7 , as shown in FIG. 2, includes a NAND  9  through which both of the control signal CTL and the clock signal CLK are inputted, and the delay elements  8 A to  8 H. 
     According to this construction, the pumping circuits  4 A to  4 H are prevented from starting the boosting operation thereof at the same time when activating the boost circuit. 
     As a result, there is obtained the effect that it is possible to reduce the power source current consumption when starting the boosting operation. 
     Then, it is assumed that the frequency of the clock signal CLK inputted from the outside is 4 MHz, and the delay value of each of the delay devices  8 A to  8 H, for example, is 1.5 times as large as the period of the clock signal CLK inputted from the outside. In this connection, alternatively, if the clock signals A to J are 180 degrees out-of-phase with each other in this order, then the boost circuit may be configured in such a way that the delay value of each of the delay devices  8 A to  8 H is 1.5 or more times as large as the period of the clock signal CLK inputted from the outside. Likewise, alternatively, the frequency of the clock signal CLK from the outside may also be equal to or lower than 4 MHz as long as the boost circuit can be operated in this state. 
     Next, the operation of this embodiment will be hereinbelow described with reference to a timing chart shown in FIG.  3 . 
     Setting control signal CTL to low level stops the boosting operation. As a result, all of the outputs of the clock generating circuit  7  become high level to stop the boosting operation. 
     On the other hand, when starting the boosting operation, the control signal CTL is set to a high level. As a result, the clock signal CLK becomes valid. 
     Then, the clock signals A to J are successively outputted in this order from the outputs of the clock generating circuit  7  at every lapse of a predetermined time delay. For the output signal A, the clock signal is outputted in such a way as to be 180 degrees out-of-phase with respect to the clock signal CLK, and for the output signal B, the clock signal is outputted in such a way as to be in phase with the clock signal CLK and also as to be delayed with respect to the clock signal CLK by 375 nsec. 
     Likewise, the clock signal C is inputted in such a way as to be 180 degrees out-of-phase with the clock signal CLK and as to be delayed with respect to the clock signal CLK by 750 nsec; the clock signal D is outputted in such a way as to be in phase with the clock signal CLK and as to be delayed with respect to the clock signal CLK by 1,025 nsec; the clock signal E is outputted in such a way as to be 180 degrees out-of-phase with the clock signal CLK and as to be delayed with respect to the clock signal CLK by 1,400 nsec; the clock signal F is outputted in such a way as to be in phase with the clock signal CLK and as to be delayed with respect to the clock signal CLK by 1,775 nsec; the clock signal G is outputted in such a way as to be 180 degrees out-of-phase with respect to the clock signal CLK and as to be delayed with respect to the clock signal CLK by 2,250 nsec; the clock signal H is outputted in such a way as to be in phase with the clock signal CLK and as to be delayed with respect to the clock signal CLK by 2,625 nsec; and the clock signal J is outputted in such a way as to be 180 degrees out-of-phase with the clock signal CLK and as to be delayed with respect to the clock signal CLK by 2,900 nsec. 
     Now, when stopping the boosting operation, each of the outputs of the clock generating circuit  7  is held at the high level. As a result, since each of the inputs to the pumping circuits  4 A to  4 H also becomes high level, no boosting operation is carried out. On the other hand, when carrying out the boosting operation, the clock signal A is inputted from the clock generating circuit  7  to the pumping circuit  4 A a 375 nsec time delay after the level of the input from the control signal CTL has been changed from the low level to the high level, so that the pumping circuit  4 A starts the boosting operation. Next, since the clock signal B is inputted to the pumping circuit  4 B a 375 nsec time delay after the pumping circuit  4 A has started the boosting operation, the pumping circuit  4 B starts the boosting operation. Likewise, the pumping circuits  4 C to  4 H start the boosting operations, respectively, at every lapse of a 375 nsec time delay after the pumping circuits in the respective previous stages have started the boosting operations. 
     Therefore, when activating the boost circuit, from the following expression: 
     
       
         The power source current =ΔQ/Δt=ΔV×C/Δt   (2) 
       
     
     it becomes clear that ΔQ becomes ideally ¾ of the prior art and hence it is possible to reduce the power source current. 
     FIG. 22 is a graphical representation showing the simulation result of this circuit. In the figure, reference numeral  281  designates a waveform of the boosted voltage (VPP) and reference numeral  282  designates a waveform of the power source current (IDD). The boosting voltage of this circuit is 17.0 V and the peak current thereof is 553 μA. 
     Embodiment 2 
     The second embodiment features a reduction in the number of constituent elements. 
     As shown in FIG. 4, the boost circuit according to the second embodiment of the present invention comprises a first boost circuit  52 , second boost circuit  53  and a level shifter  54  for obtaining from the first clock signal M 1  a second clock signal M 3 . 
     The first boost circuit  52 , as shown in FIG. 5, comprises a clock terminal CLK receiving a first clock signal M 1 , an output terminal VOUT′, an inverter  55  receiving the first clock signal M 1 , an inverter  56  receiving an output signal of the inverter  55 , an N-channel MOS transistor  57  receiving an output of the inverter  56  at the gate electrode, and pumping circuits  61 A and  61 B. 
     The pumping circuits  61 A and  61 B have N-channel MOS transistors  60 A and  60 B, capacitors  59 A and  59 B, and inverters  58 A and  58 B, respectively. The N-channel MOS transistors  60 A and  60 B are electrically connected in series between the N-channel MOS transistor  57  and the output terminal VOUT′. One terminal of each of the capacitors  59 A and  59 B is electrically connected to the gate of the N-channel MOS transistors  60 A and  60 B, respectively. The inverter  58 A receives the clock signal of the clock terminal CLK and provides the output signal to the other terminal of the capacitor  59 A. The inverter  58 B receives the output signal of the inverter  55  and provides the output signal to the other end of the capacitor  59 B. 
     The second boost circuit  53 , as shown in FIG. 6, has a clock terminal CLX receiving the second clock signal which is an output of the level shifter  54 , an output terminal VOUT, an inverter  62  receiving the second clock signal, an inverter  63  receiving an output signal of the inverter  62 , an N-channel MOS transistor  64  receiving an output of the inverter  63  at the gate electrode, and pumping circuits  68 A to  68 D. 
     The pumping circuits  68 A to  68 D have N-channel MOS transistors  67 A to  67 D, capacitors  66 A to  66 D, and inverters  65 A to  65 D, respectively. The N-channel MOS transistors  67 A to  67 D are electrically connected in series between the N-channel MOS transistor  64  and the output terminal VOUT. The power supply terminals of the inverters  62  to  64  and  65 A to  65 D receive the output signal of the first boost circuit  52 . 
     The level shifter  54 , as shown in FIG. 7, includes: P-channel MOS transistors  69 A and  69 B sources of which are electrically connected to a power source terminal VP 1 ; an N-channel MOS transistor  70 A whose drain is electrically connected to the P-channel MOS transistor  69 A and a source of which is electrically connected to ground; and an N-channel MOS transistor  70 B a drain of which is electrically connected to the P-channel MOS transistor  69 B and a source of which is electrically connected to ground, wherein a gate of the P-channel MOS transistor  69 A is electrically connected to a drain of the P-channel MOS transistor  69 B; a gate of the P-channel MOS transistor  69 A is electrically connected to a drain of the P-channel MOS transistor  69 A; the clock signal CLK is inputted to a gate of the N-channel MOS transistor  70 A; a signal which has been obtained by inverting a clock signal CLK in an inverter  71  is inputted to a gate of the N-channel MOS transistor  70 B; and a signal CLX which is in phase with the clock signal CLK and which has been level-shifted is generated from the drain of the P-channel MOS transistor  69 B. 
     Thus, in the boost circuit of the second embodiment, the prior art boost circuit having eight stages in total is divided into the two boost circuits. That is, the first boost circuit  52  in the previous stage is configured in such a way as to have the two stages of the pumping circuits  61 A and  61 B, and the second boost circuit  53  in the after stage is configured in such a way as to have the four stages of the pumping circuits  68 A to  68 D. In addition, the boosted voltage which is obtained in the first boost circuit  52  in the previous stage is employed as the power source for the second boost circuit  53  in the after stage. 
     In this connection, each of the power source of the inverters  62  and  63  for controlling the MOS transistor  64  of the second boost circuit of this circuit and the power source of the inverters  65 A to  65 D for carrying out the electric charge accumulation/transfer of each of the capacitors  66 A to  66 D is the output voltage VPP of the first boost circuit  52 . 
     Next, the description will hereinbelow be given with respect to the circuit of the second embodiment with reference to a timing chart shown in FIG.  8 . 
     At the time when the level of the control signal CTL has been changed from the low level to the high level when starting the boosting operation so that the clock signal is valid, the first boost circuit starts the boosting operation. However, since the clock signal CLX is not inputted from the level shifter  54  to the boost circuit  53  until the boosted voltage VPP of the first boost circuit  52  has been boosted up to the power source voltage with which the level shifter  54  can be operated, the second boost circuit  53  does not carry out the boosting operation at all. 
     Therefore, at the time when starting the boosting operation, only the first boost circuit  52  carries out the boosting operation. Thus, since the number of stages of the pumping circuits is two, which is ¼ of the number of prior art stages, i.e., the eight stages, from the expression (2), it becomes clear that ideally, the power source current can be reduced down to ¼ of the prior art example. 
     In addition, the prior art boosted voltage is expressed by the following expression: 
     
       
           VPP= (the power source voltage  VDD )×(the number of stages of the pumping circuits of the boosting circuit)  (3) 
       
     
     Therefore, in the prior art circuit, the following expression is established: 
     
       
           VPP=VDD× 8 stages=8VDD  (4) 
       
     
     whereas in the second embodiment, the following expression is established: 
     
       
           VPP= (the boosted voltage of the boost circuit  52 )×(the number of stages of the boost circuit  53 )=2VDD×4=8VDD  (5) 
       
     
     Thus, it becomes clear that though the number of stages of the pumping circuits is decreased by two, by only adding the level shifter thereto, it is possible to obtain the boosted voltage which is equal to that of the prior art circuit. 
     In addition, there is obtained the effect that the number of stages of the pumping circuits of the boost circuit in the first stage is made into four stages, whereby with a total of eight stages of the pumping circuits, as in the prior art, ideally, the boosted voltage can be obtained which is 2 times as large as that of the prior art. 
     FIG. 23 is a graphical representation showing the simulation result of this circuit in which each of the first boost circuit  52  and the second boost circuit  53  is configured in such a way as to have four stages. In the figure, reference numeral  311  designates a waveform of the boosted voltage (VPP) and reference numeral  312  designates a waveform of the power source current (IDD). The boosted voltage of this circuit is 20.3 V and the peak current thereof is 432 μA. 
     In addition, FIG. 24 is a graphical representation showing the simulation result for this circuit in which the first boost circuit  52  is configured in such a way as to have two stages, and the second boost circuit  53  is configured in such a way as to have four stages. In the figure, reference numeral  321  designates a waveform of the boosted voltage (VPP) and reference numeral  322  designates a waveform of the power source current (IDD). The boosted voltage of this circuit is 19.0 V and the peak current thereof is 224 μA. 
     Embodiment 3 
     As shown in FIGS. 9 to  14 , the third embodiment of the boost circuit is configured in such a way that the first embodiment of the boost circuit is combined with the second embodiment of the boost circuit. 
     That is, in the same manner as that in the first embodiment, the clock signals A 2  to C 2  are applied to a first boost circuit  91  at every lapse of the successive time delay using a clock generating circuit  90 . 
     In addition, in the same manner as that in the first embodiment, the clock signals D 3  to H 3  are applied to a second boost circuit  93  at every lapse of the successive time delay, and also in the same manner as that in the second embodiment, such clock signals are successively supplied to the second boost circuit  93  through the level shifter  91  in the same manner as that in the second embodiment. 
     FIG. 25 is a graphical representation showing the simulation result of this circuit. In the figure, reference numeral  331  designates a waveform of the boosted voltage (VPP) and reference numeral  332  designates a waveform of the power source current (IDD). The boosted voltage of this circuit is 19.0 V and the peak current thereof is 218 μA. 
     Therefore, the boost circuit of the third embodiment provides the greatest reduction of power source current among the above-mentioned three boost circuits of the first to the third embodiments. 
     Since the boost circuit according to the present invention is configured in the manner as described above, it is possible to reduce the current when activating the boost circuit. 
     The present invention is not limited by the embodiments and it is obvious that they can be modified within the spirit and the scope of the present invention.