Abstract:
An LSI package including an area for mounting an LSI device thereon and a plurality of lines for connecting the LSI device and external terminals. At least two of the plurality of lines, in which differential signals are transmitted and are adjacent to each other in the LSI package, have equal lengths.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to an LSI package, and particularly relates to an LSI package including an LSI device operating at a higher clock frequency. 
     Recent LSI devices tend to operate at higher frequency and with higher electrical consumption. Accordingly, there is a need for packages for mounting the LSI devices thereon, or LSI packages, which can be used with such LSI devices. Thus, the LSI packages are modified as follows. 
     First, in order to stabilize an electric current supply, the LSI package is formed in a multilayer structure with an inner layer provided with a source/ground plane. Secondly, in order to reduce an inductance of source/ground lines, the source/ground lines are provided so as to be short in length and broad in width. Thirdly, in order to achieve a 50 Ω impedance matching, gaps between layers are adjusted by providing planes on layers above and below wiring layers. Finally, in order to reduce mutual inductance and crosstalk, gaps between signal lines are widened so that the signal lines do not interfere with each other. 
     2. Description of the Related Art 
     Now an LSI package of the related art will be described in detail with reference to FIGS. 1 and 2. An LSI package  1  shown in FIGS. 1 and 2 is a double-layer package including an upper layer  2  (shown in FIG. 1) and a lower layer  3  (shown in FIG.  2 ). FIGS. 1 and 2 show ⅛ of the whole pattern of the LSI package  1 . 
     As shown in FIGS. 1 and 2, through-hole lands  4  are formed in a matrix form on both the upper layer  2  and the lower layer  3 . The through-hole lands  4  are connected to external terminals via through-holes. The external terminals are provided with, for example, bumps. With the structure described above, the LSI package  1  may be used as a BGA (Ball Grid Array) type package. 
     Also, the upper layer  2  and the lower layer  3  are provided with a number of lines  5 . Each of the lines  5  is connected to one of the external terminals via a through-hole at one end, and to an electrode pad  6  on the other end. The electrode pads  6  are formed on the upper layer  2  and the lower layer  3  at positions facing a semiconductor chip (not shown). The electrode pads  6  are electrically connected to the semiconductor chip using wires. 
     Now, the lines  5  will be described in detail. In the related art, the relationship between the lengths of the lines  5  on either the upper layer  2  or the lower layer  3 , or the lines  5  on both the upper layer  2  and the lower layer  3 , was not of a great interest. The wiring pattern was determined so as to facilitate the forming process of the lines  5 . 
     However, for source lines and for ground/source lines, which are labeled a-g in FIGS. 1 and 2, the line lengths were shortened for the sake of electrical feature and the line widths were broadened as shown by the line labeled g in FIG.  2 . Also, impedance matching was achieved by a multilayer package provided with a signal-transmitting layer held between the source planar layer and the ground planer layer. 
     In the related art, improvement of electrical characteristics of the LSI package  1  has focused on improvement of the LCR characteristics or the 50 Ω matching of the characteristic impedance according to the modifications described above. Thus, the LCR characteristics, the impedance matching of the LSI package, and crosstalk problems have been improved. However, there is still a need for reducing the noise produced by the mismatch of transmission times between differential signals. 
     Also, when the above-described modifications are applied to the recent LSI devices having a clock frequency of over 1 GHz, there is a problem that when the LSI device is mounted on the LSI package  1 , the LSI device (semiconductor device) does not operate. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is a general object of the present invention to provide an LSI package which can solve the problems described above. 
     It is another and more specific object of the present invention to provide an LSI package which can achieve an improvement in the electrical characteristics even when an LSI device, which uses a higher clock frequency, is mounted on the LSI package. 
     It is still another object of the present invention to provide an LSI package, which can reduce the transmission time lag between differential signals, thus reducing the noise and improving electrical characteristics. 
     In order to achieve the above objects, an LSI package includes: 
     an area for mounting an LSI device thereon; and 
     a plurality of lines for connecting the LSI device and external terminals, 
     wherein at least two of the plurality of lines, in which differential signals are transmitted and are adjacent to each other in the LSI package, have equal lengths. 
     Further, the LSI package includes a multilayer structure having layers provided with the plurality of lines thereon, wherein the lines having equal lengths are provided on one of the layers. Also, the LSI package may include a multilayer structure having layers provided with the plurality of lines thereon, wherein the lines having equal lengths are provided on different ones of the layers. 
     It is yet another object of the present invention to provide an LSI package which can reduce the transmission time lag between differential signals including any loss at wires, thus improving electrical characteristics. 
     In order to achieve the above object, the plurality of lines connected to the external terminals are respectively connected to an LSI device using wires so that a plurality of interconnections are formed between the LSI device and the external terminals, the lengths of the interconnections being equal. 
     It is yet another object of the present invention to provide an LSI package which can prevent any crosstalk between a pair of lines. 
     In order to achieve to above object, the LSI package further includes a double-layer structure having an upper layer and a lower layer provided with the plurality of lines thereon, 
     wherein the lines provided on the upper layer and the lines provided on the lower layer are offset by half a pitch, and 
     wherein, when a pair of lines having equal lengths for transmitting differential signals are provided on either one of the upper layer and the lower layer, a line on the other one of the upper layer and the lower layer positioned between the pair of lines is used as one of terminating resistance line and a power supply/ground line. 
    
    
     Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram showing an upper layer of an LSI package of the related art. 
     FIG. 2 is a diagram showing a lower layer of the LSI package of the related art. 
     FIG. 3 is a diagram showing a wiring structure of an upper layer of an LSI package of the present invention. 
     FIG. 4 is a diagram showing a wiring structure of a lower layer of the LSI package of the present invention. 
     FIG. 5 is a side view partly showing the LSI package of a embodiment of the present invention. 
     FIGS. 6A and 6B are diagrams showing positioning of electrode pads formed on the LSI package of the embodiment of the present invention. 
     FIG. 7 is a side view showing positioning of electrode pads formed on the LSI package of the embodiment of the present invention. 
     FIG. 8 is a diagram showing positioning of wires between the electrode pads and a semiconductor chip of the LSI package of the embodiment of the present invention. 
     FIG. 9 is a diagram showing an example of lines having equal length, which are formed on the upper layer. 
     FIG. 10 is a diagram showing an example of lines having equal length, which are formed on the lower layer. 
     FIG. 11 is a graphical representation showing an effect of the present invention. 
     FIG. 12 is another graphical representation showing an effect of the present invention. 
     FIG. 13 is a diagram showing an example of lines which are formed on the upper layer of the LSI package according to the related art. 
     FIG. 14 is a diagram showing an example of lines which are formed on the lower layer of the LSI package according to the related art. 
     FIG. 15 is a graphical representation showing electrical characteristics of the lines according to the related art. 
     FIG. 16 is another graphical representation showing electrical characteristics of the lines according to the related art. 
     FIGS. 17 to  19  are charts indicating total wiring length, line length, wire length and pin connector number for lines formed on the LSI package shown in FIGS.  3  and  4 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the following, a principle and an embodiment of the present invention will be described with reference to the accompanying drawings. 
     FIGS. 3 to  8  are diagrams showing an LSI package  10  having a wiring structure of an embodiment of the present invention. The LSI package  10  according to the present invention has a multilayer structure. As shown in FIG. 5, in the present embodiment, the LSI package  10  is a double-layer package including an upper layer  12  and a lower layer  13 . FIG. 3 is a plan view of the upper layer  12  and FIG. 4 is a plan view of the lower layer  13 . Also in FIGS. 3 and 4, only ⅛ of the whole pattern of the LSI package  10  is shown for convenience sake of illustration. 
     The upper layer  12  and the lower layer  13  are provided on boards formed of an insulating member, respectively. The boards are fixed on a base  24  of the LSI package  10 . The upper layer  12  and the lower layer  13  are formed such that their surfaces are provided with lines  15   a  and  15   b . Also, openings  17  and  18  in which an LSI chip (semiconductor chip)  11  is mounted are formed at the central part of the upper layer  12  and the lower layer  13 . 
     The lines  15   a ,  15   b  include through-hole lands  14   a , 14   b  at one end and electrode pads  16   a , 16   b  at the other end, both being formed in an integrated manner. The through-hole lands  14  are formed in the upper layer  12  and in the lower layer  13  in a matrix form. The through-hole lands  14  are connected to external terminals via through-holes. The external terminals are provided with, for example bumps, by which the LSI package  10  may be used as a BGA (Ball Grid Array) type package. 
     In the present embodiment, each through-hole land  14   a ,  14   b  is specified by providing addresses  25 - 34  in a longitudinal direction and addresses A-U in a lateral direction. Also, since the through-hole lands  14   a ,  14   b  are in a one-to-one relationship with the lines  15   a ,  15   b , the lines  15   a ,  15   b  may also be specified by the above addresses. 
     Now, referring to FIGS. 6A,  6 B,  7  and  8 , the structure of the electrode pads  16   a  and  16   b , which are formed at end parts of each line  15 , will be described. 
     The electrode pads  16   a  and  16   b  are provided in parallel near the openings  17  and  18 . Also, as shown in FIG. 8, the electrode pads  16   a  and  16   b  are provided so as to oppose semiconductor chip pads  23  formed on an LSI chip  11 . The electrode pads  16   a  and  16   b  are electrically connected to the pads  23  via wires  19 - 22 . 
     FIG. 6A shows an enlarged view of the electrode pads  16   a  formed on the upper layer  12  and FIG. 6B shows an enlarged view of the electrode pads  16   b  formed on the lower layer  13 . 
     As shown in FIGS. 6A and 6B, the electrode pads  16   a  are formed with a pitch (W), a center to center distance on the upper layer  12  and the electrode pads  16   b  are formed with the same pitch (W) on the lower layer  13 . Also, adjacent electrode pads  16   a ,  16   b  have different levels in a vertical direction, such that the electrode pads  16   a ,  16   b  form saw-toothed structures on the upper layer  12  and on the lower layer  13 , respectively. 
     As shown in FIGS. 7 and 8, an electrode pad formed on one of the layers is provided between a pair of electrode pads formed on the other layer. In FIG. 3, the rightmost electrode pad  16   a  on the upper layer  12  is labeled P 1  and adjacent electrode pads are successively labeled P 3 , P 5  and the like. Similarly, in FIG. 4, the rightmost electrode pad  16   b  on the lower layer  13  is labeled P 2  and adjacent electrode pads are successively labeled P 4 , P 6  and the like. 
     Here, considering the above-described other layer to be the upper layer  12 , and the pair of electrode pads to be P 1  and P 3 , the electrode pad P 2  formed on the lower layer  13  will be positioned between the pair of electrode pads P 1  and P 3 . Accordingly, as shown in FIG. 8, the wires  19 - 22  can be provided with high density. 
     In the following, a wiring structure of the lines  15   a  and  15   b , which forms an important part of the present embodiment, will be described. 
     As shown in FIGS. 3 and 4, the through-hole lands  14   a  and  14   b  are labeled with numbers 1-12 and characters V and G. The lines  15   a ,  15   b  connected to the through-hole lands  14   a , 14   b  labeled with numbers 1-12 are signal lines. Also, the lines  15   a , 15   b  connected to the through-hole lands  14   a ,  14   b  labeled V are source lines. Further, the lines  15   a ,  15   b  connected to the through-hole lands  14   a ,  14   b  labeled G are ground lines. 
     For the signal lines, the lines labeled with the same number form one group in which the lengths of the lines  15   a ,  15   b  are equal. For example, there are six through-hole lands  14   a ,  14   b  which are labeled “1”, which means that there are six corresponding lines  15   a ,  15   b . These six lines  15   a ,  15   b  form a group of equal-length lines. In other words, the lines represented by U 33 , U 34 , T 33 , T 34 , R 33  and R 34  have the same length (equal length). Here, the group of equal-length lines, which are labeled “1”, is referred to as a “#1 group” and other groups labeled “2” to “12” are similarly referred to as a “#2 group” to a “#12 group”, respectively. 
     In the present embodiment shown in FIGS. 3 and 4, groups of six equal-length lines include the “#1 group”, “#2 group”, “#3 group”, “#4 group”, “#5 group”, “#6 group” and “#7 group”. 
     Also, the “#8 group” is a group of four equal-length lines. Further, groups of three equal-length lines include the “#9 group”, “#10 group” and “#11 group”. The “#12 group” is a group of two equal-length lines. In the figure, the through-hole lands  14   a , 14   b , which are not labeled, do not form a group of equal-length lines. 
     In the present embodiment, the LSI chip  11 , which uses a high clock frequency (e.g., 1 GHz), is mounted on the LSI package  10  and differential signals are supplied to a pair of adjacent lines  15   a  and  15   b  in each group. Note that, as described above, the lengths of the lines  15   a  and  15   b  in each group (#1 group-#12 group) are equal. Then, since the lengths of the pair of lines  15   a  and  15   b  through which the differential signals are transmitted are equal, the transmission time lag between the differential signals may be reduced. Therefore, noise in the differential signals will be reduced and the electrical characteristics will be sufficiently improved. 
     Now, a layout of lines  15   a  and  15   b  within each group will be described. 
     As shown above, from an electrical characteristic point of view, the lines  15   a  and  15   b  may be categorized into the signal lines for transmitting the differential signals, the source lines for supplying voltages and the ground lines to be grounded. Here, the #1 group is taken as an example. When providing the equal-length lines on the double-layered LSI package  10 , two lines for transmitting the differential signals may either be provided on the same layer or on different layers. In either case, in order to reduce the noise, at least the lengths of the lines for transmitting the differential signals need to be the equal. 
     When the two lines for transmitting the differential signals are provided on the same layer (i.e., only on the upper layer  12  or only on the lower layer  13 ), the lines corresponding to adjacent pins on the layer (e.g., U 33  and T 33 ) are made to be equal-length lines. Also, when the two lines for transmitting the differential signals are provided on different layers (i.e., one on the upper layer  12  and the other on the lower layer  13 ), the lines provided on each layer  12  and  13  (e.g., U 33  and U 34 ) are made to be equal-length lines. 
     However, when providing the two lines for the differential signals on the same layer, one line on the other layer is positioned between the two lines for differential signals. That is to say, with the wiring structure of the present embodiment, the lines  15   a  formed on the upper layer  12  and the lines  15   b  formed on the lower layer  13  are formed so as to be offset by half a pitch. 
     This will be described with reference to FIG.  7 . Lines connected to pads P 1  and P 3  formed on the upper layer  12  are lines for the differential signals. The line connected to pad P 2  formed on the lower layer  13  exists between the two lines connected to pads P 1  and P 3 . Therefore, by using the line connected to pad P 2  formed on the lower layer  13  as a line for end resistance or source/ground, the noise may be further reduced since the two lines P 1  and P 3  are electromagnetically shielded. 
     Now, a case is considered where six (or a multiple of six) equal-length lines form one group, for example, one of the #1 group-#7 group. When the two lines for the differential signals are provided on the same layer, a pair of equal-length lines may be provided on the upper layer and the lower layer, respectively (i.e., total of two pairs). In FIG. 7, the line P 1  and the line P 3  of the upper layer  12  form a pair of equal-length lines for the differential signals and the line P 4  and the line P 6  of the lower layer  13  form a pair of equal-length lines for the differential signals. The line P 2  and the line P 5  will be the lines for end resistance or source/ground of the upper layer  12  and the lower layer  13 , respectively. 
     When considering the equal-length lines, the wires  19 - 22  have a certain effect on the electrical characteristics. Therefore, the wiring structure of the LSI package  10  needs to be determined with consideration of the length of the wires  19 - 22 . 
     FIG. 8 shows a structure where the LSI package  10  includes the upper layer  12  and the lower layer  13 , and the electrode pads  16   a  and  16   b  formed on each wiring layer  12  and  13  are saw-toothed. In such a structure, the lengths of the wires  19 - 22  are different. Therefore, when only the length of the lines  15   a ,  15   b  are equal, each connection (including wires  19 - 22 ) may have different electric characteristics resulting from the difference of the length of the wires  19 - 22 . This may produce a noise. 
     In the present embodiment, the total wiring lengths, or the lengths of lines (line lengths)  15   a ,  15   b  plus the lengths of wires  19 - 22  (wire lengths), are determined to be equal. 
     This is shown in FIGS. 17 to  19 . Here, a wiring is considered to be formed of a line and a wire. FIGS. 17 to  19  are charts showing wire length, line length, and total wiring length (wire length+line length) individually for each wiring. The wire lengths of the wires  20  and  22  to be connected to the electrode pads  16   a  formed on the upper layer  12  are greater than the wire lengths of the wires  19  and  21  connected to the electrode pads  16   b  formed on the lower layer  13 . Therefore, the line lengths of the lines  15   a  formed on the upper layer  12  are determined so as to be shorter than the line lengths of the lines  15   b  formed on the lower layer  13 . 
     Thus, by introducing equal total wiring lengths (i.e., line lengths plus lengths of wires  19 - 22 ), it is possible to reduce the transmission time lag including any loss at wires. Therefore, electrical characteristics are improved. 
     In FIGS. 3 and 4, only ⅛ of the whole pattern of 672 pins is illustrated as described above. In order to obtain the number of equal-length lines for the whole LSI package  10 , every group must be multiplied by 8. That is to say, there are 7×8=56 groups of six equal-length lines (#1-#7 group), 1×8=8 groups of four equal-length lines (#8 group), 3×8=24 groups of three equal-length lines (#9-#11 group) and 1×8=8 groups of two equal-length lines (#12 group). Then, the number of two adjacent lines (pairs) for differential signals in the same layer may be obtained as follows. For a group of six equal-length lines, two pairs may be obtained, which is 2×56=112 pairs for the whole pattern. Similarly, 1×8=8 pairs for groups of four equal-length lines and 1×24=24 pairs for groups of three equal-length lines are obtained for the whole pattern. This results in 144 pairs in total. 
     Also, the number of two adjacent lines for differential signals in different layers may be obtained as follows. 3×56=168 pairs for groups of six equal-length lines, 2×8=16 pairs for groups of four equal-length lines, 1×24=24 pairs for groups of three equal-length lines and 1×8=8 pairs for groups of two equal-length lines are obtained for the whole pattern. This results in 216 pairs in total. By dividing the signals in half, each of the input and output can be provided with 108 pairs of the lines for differential signals. When the data and the number of the data units of the clock signals are known, the number of differential signals may be determined so as to be larger than this known number. 
     In the following, output data will be described which is obtained from a simulation using the lines for differential signals having two adjacent equal-length lines in the same layer and the lines for differential signals having two adjacent equal-length lines in different layers. FIGS. 9 and 10 show equal-length lines  15   a  and  15   b  of the group of six equal-length lines used in this simulation. FIG. 9 shows the equal-length lines  15   a  provided on the upper layer  12  and FIG. 10 shows the equal-length lines  15   b  provided on the lower layer  13 . 
     Lines L 1  and L 3  are used as models for the simulation of the two adjacent equal-length lines in the same layer. The lines L 1  and L 3  belong to the #6 group, and correspond to F 33  and E 33 , respectively (see FIG.  3 ). Here, a wire length is a length of a wire connected to a respective line and a total wiring length is a length of a wiring including the respective line. As shown in FIG. 18, the line L 1  (#6 group, pin connector number F 33 ) has aline length of 20.895 mm, a wire length of 3.50 mm and a total wiring length of 24.395 mm. The line L 3  (#6 group, pin connector number E 33 ) has a line length of 21.295 mm, a wire length of 3.09 mm and a total wiring length of 24.385 mm. The difference between the total wiring lengths of the two lines is 10 μm. 
     The result is shown in FIG.  11 . FIG. 11 shows output signals output on each line when the input wave indicated as a solid line curve is input. In the figure, the vertical axis indicates voltages and the horizontal axis indicates the time. As shown in FIG. 11, the transmission difference between the two lines L 1  and L 3  is a relatively small value, which may be 0.83 ps. Therefore, it is shown that good transmission characteristics may be obtained when the equal-length lines are provided on the same layer. 
     Lines L 3  and L 4  are used as models for the simulation of the two adjacent equal-length lines in different layers. The lines L 3  and L 4  belong to the #6 group, and correspond to E 33  and E 34 , respectively (see FIG.  3  and  4 ). As shown in FIG. 18, the line L 4  (#6 group, pin connector number E 34 ) has a line length of 22.872 mm, a wire length of 1.44 mm and a total wiring length of 24.312 mm. Thus, the difference between the total wiring length of the two lines is 73 μm. The result is shown in FIG.  12 . As shown in FIG. 12, the transmission difference between the lines L 3  and L 4  is a small value, which may be 7.20 ps. Therefore, it is shown that good transmission characteristics may be obtained even when the equal-length lines are provided on different layers. 
     In the following, as a comparison, output data will be described which results from the simulation using the lines for differential signals not formed as equal-length lines in the same layer and the lines for differential signals not formed as equal-length lines in different layers. FIGS. 13 and 14 show models of the upper and lower layers provided with lines not formed as equal lines, which are used in the simulation. FIG. 13 shows the lines  5  provided on the upper layer  12  and FIG. 14 shows the lines  5  provided on the lower layer  13 . 
     Lines M 1  and M 3  are used as models for the simulation of the two adjacent lines in the same layer. The line M 1  has a line length of 12.9 mm, a wire length of 3.395 mm and the total wiring length of 16.295 mm. The line M 3  has a line length of 16.444 mm, a wire length of 3.805 mm and a total wiring length of 20.249 mm. The difference between the total wiring lengths of the two lines M 1  and M 3  is 3.954 mm. FIG. 15 shows the result of this simulation. As shown in FIG. 15, the transmission difference between the two lines M 1  and M 3  is 12.50 ps. 
     Lines M 3  and M 4  are used as models for the simulation of the two adjacent lines in the different layers. The line M 4  has a line length of 17.944 mm, a wire length of 1.895 mm and a total wiring length of 19.839 mm. The difference between the total wiring lengths of the two lines M 3  and M 4  is 0.410 mm. FIG. 16 shows the result of this simulation. As shown in FIG. 16, the transmission difference between the two lines M 3  and M 4  is 14.30 ps. 
     As can be seen from the above-described simulations, when comparing the difference of the transmission time between the equal-length lines for the differential signals and the difference of the transmission time between the lines which are not equal-length lines, the difference in time is smaller between the equal-length lines for both the same layer and different layers. Therefore, it is shown that the time lag between the differential signals is reduced by using equal-length lines. 
     Further, the present invention is not limited to these embodiments, but variations and modifications may be made without departing from the scope of the present invention. 
     The present application is based on Japanese priority application No. 9-228548 filed on (Aug. 25, 1997) the entire contents of which are hereby incorporated by reference.