Abstract:
A device for debugging an electronic circuit manufactured from an initial program in hardware description language, HDL, comprising an instrumentation unit capable of receiving the initial program; receiving an additional program describing determined functions; determining an additional circuit to be incorporated into the electronic circuit from the additional program, capable of setting to a determined value a signal selected from among an input signal, an output signal, or a signal internal to the additional circuit; and providing a modified program in HDL language incorporating a description in HDL language of the additional circuit; and a debugging unit capable of debugging a modified electronic circuit manufactured from the modified program, the debugging unit being capable of communicating with the additional circuit to control the setting to the determined value of the selected signal.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to a device and a method for debugging an electronic circuit described by a program written in a hardware description language or HDL.  
       BACKGROUND OF THE INVENTION  
       [0002]     The HDL language is a programming language which has been developed and optimized for the design and the modeling of electronic circuits since it enables accurately describing the behavior of electronic circuits. It is, for example, the VHDL language (for VHSIC Hardware Description Language, with VHSIC standing for Very High Speed Integrated Circuit), or the Verilog language.  
         [0003]     Examples of electronic circuits formed based on HDL programs are Field Programmable Gate Array (FPGA) circuits or Application Specific Integrated circuits, or ASIC. More specifically, an FPGA circuit comprises electronic gates preimplanted on a circuit according to a given topology. In the initial state, these gates are not interconnected. To form an electronic circuit implementing specific functions based on an FPGA circuit, it is enough to create certain connections (which can be obtained by the turning-on of MOS transistors) between certain electronic gates of the FPGA to obtain the desired functions. For this purpose, a RAM, in which configuration data (bitstream) especially representing circuit connections are stored, may be used. The bitstream data are obtained from the HDL program describing the electronic circuit.  
         [0004]     In the full design process of an electronic circuit, it is necessary to provide a debugging step which comprises the error detection, diagnosis, and correction, during the electronic circuit operation. For an electronic circuit designed based on an HDL program, an error correction may correspond to a modification of the HDL program describing the electronic circuit.  
         [0005]     There currently exist two main types of methods for debugging an electronic circuit obtained from an HDL program.  
         [0006]     The first method consists of using a logic analyzer. It may for example be the logic analyzer sold by Altera Company under trade name Signal TAP. A logic analyzer enables modifying the initial HDL program describing an electronic circuit to obtain a modified HDL program which describes the same electronic circuit with additional circuits which generally have no influence upon the behavior of the electronic circuit and which implement specific functions useful to debug the electronic circuit. An additional circuit may perform logic operations on given signals used by the electronic circuit and provide an alert signal when a logic condition is fulfilled, check the values of several signals in parallel, etc. The debugging of an FPGA circuit programmed from the initial HDL program is carried out by programming the FPGA circuit with the modified HDL program. The modified FPGA circuit is then operated in real time in its normal operation environment, and the logic analyzer is used to collect the different signals provided by the additional circuits added to the electronic circuit described by the initial HDL program.  
         [0007]     The logic analyzer provides a user with a list of additional circuits from which it determines the specific functions for the electronic circuit debugging. However, the debugging functions that can be obtained are limited by the additional circuits provided by the logic analyzer. Even if more complex debugging functions are defined by combining the functions provided by the logic analyzer, not always can the user define specific debugging functions which would be particularly well adapted to the electronic circuit debugging.  
         [0008]     The second method corresponds to a direct debugging of the HDL program. Such a debugging method may be implemented by means of the debugger sold by Synplicity Company under trade name Identify. Such a debugger enables inserting watchpoints at the level of certain parts of an initial HDL program describing an electronic circuit and providing a modified HDL program from which an FPGA circuit, for example, is programmed. On operation of the modified FPGA circuit thus programmed, the debugger exchanges signals with the FPGA circuit and can indicate to a user whether the parts of the initial HDL program marked with watchpoints have been executed during the operation of the FPGA circuit. The debugger can also indicate the value of signals used by the initial HDL program at the time when the marked parts of the initial HDL program are executed. If errors occur during the operation of the FPGA circuit, the user can locate the parts of the initial HDL program at the level of which the errors have occurred.  
         [0009]     However, such a debugger, being purely code-oriented, does not enable building complex verification scenarios based on the values of the signals used by the FPGA circuit. The absence of a tool of logic analyzer type can make the detection of certain errors upon operation of the FPGA circuit or the determination of the origin of certain detected errors difficult.  
         [0010]     Further, before programming of an FPGA circuit or manufacturing of an ASIC circuit, the debugging of the initial HDL program can be performed by means of a static analyzer. This is a fully automated tool, usable for any type of program, and enabling predicting the behavior on execution of a program by the sole examination of its text to detect errors in the program design. The analysis is directly performed on the HDL program and not on the way in which an FPGA circuit programmed from the HDL program operates. However, as soon as the complexity of the initial HDL program becomes significant, a static analyzer appears to be less reliable and may not detect certain errors in the initial program design. Further, such a tool does not enable taking into account certain problems inherent to the physical nature of the components of the circuit manufactured from the initial HDL program.  
         [0011]     None of the previously-described debugging methods enables the user to freely define his own additional circuits to be incorporated to the electronic circuit associated with the initial HDL description program and which enable, on operation of the electronic circuit manufactured from the modified HDL description program, execution of specific debugging functions adapted to the debugging of the considered electronic circuit. Further, it is desirable for the user to be able, during the integrated circuit operation, to modify the value of an input signal, of an output signal, or of an internal signal used by the additional previously-defined circuits to perform a specific test.  
       SUMMARY OF THE INVENTION  
       [0012]     An object of the present invention is to provide a device and a method for debugging an electronic circuit manufactured from an HDL program which eases the electronic circuit debugging operation by enabling the user to freely define the additional circuits to be incorporated to the electronic circuit and to impose the values of signals relative to the additional circuits in a debugging phase.  
         [0013]     To achieve this object, the present invention provides a device for debugging an electronic circuit manufactured based on an initial program in hardware description language, HDL, comprising an instrumentation unit capable of receiving the initial program; receiving an additional program describing determined functions; determining an additional circuit to be incorporated into the electronic circuit based on the additional program, the additional circuit comprising at least one input terminal and/or one output terminal connected to the electronic circuit and being capable of setting to a determined value a signal selected from among a signal received at the input terminal, a signal provided at the output terminal, or a signal internal to the additional circuit; and providing a modified program in HDL language based on the initial program incorporating a description in HDL language of the additional circuit; and comprising a debugging unit capable of debugging a modified electronic circuit formed based on the modified program, the debugging unit being capable of communicating with the additional circuit to control the setting to the determined value of the selected signal.  
         [0014]     According to an embodiment of the present invention, the input terminal and/or the output terminal are connected to another additional circuit to be incorporated into the electronic circuit.  
         [0015]     According to an embodiment of the present invention, the additional program is written in a language different from the HDL language, the instrumentation unit comprising a means for converting the additional program into HDL language.  
         [0016]     According to an embodiment of the present invention, the additional circuit comprises a multiplexer controlled by a control signal and receiving at a first input the additional circuit signal and at a second input the determined value, the debugging unit being capable of providing the additional circuit with the value of the control signal.  
         [0017]     According to an embodiment of the present invention, the additional circuit is capable of providing a signal representative of the selected signal, the debugging unit further comprising a display screen and being capable of displaying on the display screen the value of the representative signal.  
         [0018]     According to an embodiment of the present invention, the electronic circuit is a programmable gate array circuit programmed from the initial program and the modified electronic circuit is a programmable gate array circuit programmed from the modified program.  
         [0019]     The present invention also provides a method for debugging an electronic circuit manufactured based on an initial program in hardware description language, HDL, comprising the steps of receiving an additional program describing determined functions; determining an additional circuit to be incorporated into the electronic circuit based on the additional program, the additional circuit comprising at least one input terminal and/or one output terminal connected to the electronic circuit and being capable of setting to a determined value a signal selected from among a signal received at the input terminal, a signal provided at the output terminal, or a signal internal to the additional circuit; providing a modified program in HDL language based on the initial program incorporating a description in HDL language of the additional circuit; manufacturing a modified electronic circuit from the modified program; and debugging the modified electronic circuit by setting, at a determined time, the selected signal to the determined value via the additional circuit.  
         [0020]     According to an embodiment of the present invention, the determined functions are debugging, test, and/or verification function.  
         [0021]     The foregoing and other objects, features, and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE FIGURES  
       [0022]     Understanding of the present invention will be facilitated by consideration of the following detailed description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which like numerals refer to like parts and in which:  
         [0023]      FIG. 1  generally illustrates the steps of an example of implementation of the debugging method according to the present invention;  
         [0024]      FIG. 2  schematically shows an example of a graphic interface of the debugging device according to the present invention upon preparation of a debugging operation;  
         [0025]      FIG. 3  schematically shows an example of forming of the debugging tool according to the present invention;  
         [0026]      FIG. 4  illustrates the steps of an example of a method for forming the debugging tool according to the present invention; and  
         [0027]      FIGS. 5A, 5B  to  7 A,  7 B show examples of the forming of the debugging tool according to the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0028]     Same elements have been designated with same reference numerals in the different drawings. For clarity, only those elements which are necessary to the understanding of the present invention have been shown.  
         [0029]      FIG. 1  illustrates, in the form of a block diagram, an example of implementation of the debugging method according to the present invention. In the following description, the debugging method according to the present invention will be described for the debugging of an FPGA circuit  10  which is desired to be programmed based on an initial HDL program  12 . However, the present invention also applies to the debugging of a dedicated electronic circuit, for example, of ASIC type, manufactured based on initial HDL program  12 .  
         [0030]     The debugging method according to the present invention comprises an instrumentation unit  14  capable of receiving the initial HDL program and of providing a modified HDL program  16  based on the initial HDL program  12  according to instructions provided by a user, as described in more detail hereafter. For this purpose, instrumentation unit  14  comprises a man/machine interface comprising, for example, a display screen, a mouse, and a keyboard, or any other adapted means.  
         [0031]     Modified HDL program  16  is then provided to a programming unit  18  conventionally capable of programming FPGA circuit  10  based on modified HDL program  16  and the operation of which will not be described in further detail.  
         [0032]     The debugging device according to the present invention comprises a debugging unit  20  which, upon operation of the FPGA circuit programmed based on the modified HDL program, is capable of exchanging data with FPGA circuit  10  and of providing the user with indications as to the progress of the debugging operation via the man/machine interface. The data exchange between debugging unit  20  and FPGA circuit  10  is, for example, performed via dedicated pins of FPGA circuit  10 , according to the JTAG test protocol defined by IEEE standard 1149.1.  
         [0033]      FIG. 2  shows an example of display on the display screen of the instrumentation unit  14  used to modify the initial HDL program  12 . A window  24 , called the Instrument window, provides the user with a block list  26 , each block being associated with a debugging tool capable of helping the user in the debugging operation. These may be tools provided by the logic analyzer sold by Temento Company under trade named DLI. As an example, the tools provided by instrumentation unit  14  especially correspond to the following non-exhaustive list:  
         [0034]     a tool receiving input signals and providing one or several output signals by performing logic operations on the input signals, the logic operations being possibly defined by the user;  
         [0035]     a tool simultaneously comparing the values of several input signals with predefined values and indicating, for example, by providing an output signal in the active state, whether the values of the input signals are, at a given time, equal to the predefined values;  
         [0036]     a tool observing the time variation of a signal and indicating whether the sequence of values taken by the observed signal corresponds to a sequence of predefined values;  
         [0037]     a tool observing the time variation of a signal and indicating whether the observed signal exhibits a transient pulse; and  
         [0038]     a tool analyzing the data flows on buses of the electronic circuit, for example, by measuring the bit rate on the bus or the bus occupation.  
         [0039]     The user may select some tools from among the provided tools and define which signals supply these tools. The user may also interconnect the tools, an output of a tool driving an input of another tool. This enables the user to obtain more complex debugging tools based on the tools initially provided by instrumentation unit  14 .  
         [0040]     The present invention consists of providing a specific tool, called a logic user tool, enabling the user to freely and easily define the functions to be performed by the tool in a debugging operation and which enables the user, in the debugging operation, to control the value of one or of several signals used by the tool that he has defined.  
         [0041]      FIG. 3  schematically shows the elements forming logic user unit  30 . The functions which will be executed by logic user unit  30  in a debugging operation are defined by a tool description program  32 , in HDL language, obtained from a program written by the user. Logic user unit  30  comprises an interface unit  34  which enables connecting the input/output signals of tool description program  32  to other signals of initial HDL description  12  or to signals associated with other debugging tools. Further, logic user unit  30  comprises a control and observation unit  36  which enables controlling and/or observing the value of one or several input signals, output signals, or internal signals of tool description program  32 .  
         [0042]      FIG. 4  describes steps of an example of a method for forming a tool based on logic user unit  30 .  
         [0043]     At step  40 , the user writes, in an appropriate language, a basic program defining the test, debugging, and/or verification functions that the tool must execute in a debugging phase. It may be the HDL description language, which is particularly well adapted to the writing of debugging functions, or the PSL Sugar or Verilog System language, particularly well adapted to the writing of so-called assertion functions consisting of verifying that an expected property is verified. The basic program must comprise interface signals intended to be connected to other signals (for example, signals of initial HDL description  12  or input/output signals of tools already incorporated in initial HDL description  12 ). Further, one of the input signals of the basic program must correspond to a clock signal which, in a debugging phase, is especially used by control and observation unit  36  for the sampling of the observed signals.  
         [0044]     At step  42 , the user adds a logic user unit  30  to the tools that he has already connected to initial HDL description  12 . At this time, logic user unit  30  does not yet comprise a tool description program  32 .  
         [0045]     At step  44 , the user incorporates the basic program defined at step  40  in logic user unit  30  as a tool description program  32 . Instrumentation unit  14  converts, if need be, the basic program into HDL language. Further, instrumentation unit  14  displays on the display screen the input and output signals and the internal signals associated with the tool description program.  
         [0046]     At step  46 , the user connects, at his convenience, the input/output signals of tool description program  32  to signals used by initial HDL description  12  or to input/output signals of tools that the user has already connected to initial description  12 . Further, the user connects the clock signal of logic tool unit  30  to the clock signal used in the initial HDL description  12 , or to one of the clock signals used in initial HDL description  12 . The user then connects, to control and observation unit  36 , the input signals, the output signals and/or the signals internal to tool description program  32  that he would like to observe in the subsequent debugging step. Finally, the user connects, to control and observation unit  36 , the input signals, the output signals and/or the internal signals of logic user unit  30 , the value of which he desires to be able to impose in the subsequent debugging step.  
         [0047]     At step  48 , instrumentation unit  14  modifies tool description program  32  to take into account signals to be observed or to be controlled and then modifies initial HDL description  12  to include therein the description in HDL language of logic user unit  30 . An FPGA circuit is then programmed from modified HDL description  16 .  
         [0048]     In the subsequent debugging phase, debugging unit  20  can display on the display screen the values of the observed input signals, output signals, or internal signals, in the form of a timing diagram or in the form of digital values, each digital value being associated with a symbol representative of the considered signal, for example, a virtual light-emitting diode. The user can then easily visualize the results of the test, debugging, and/or verification functions executed by the logic user unit  30  that it has incorporated to initial HDL description  12 . In the debugging step, the user may further, at any time, set the values independently from one another of the input/output signals or of the internal signals of logic user unit  30  that it has previously specified as being signals to be controlled.  
         [0049]     For the observation and the control of the signals associated with logic user unit  30 , debugging unit  20  uses, for example, the access terminals of the FPGA circuit dedicated to test protocol JTAG defined by standard IEEE 1149.1. More specifically, for the observation of signals, an observation register having the size of the number of signals to be observed is provided at the level of the programmed FPGA circuit. By means of the instructions conventionally used by the JTAG test protocol, the value of the signals to be observed in the observation register, the bits of which are transmitted in series to debugging unit  20  by terminal TDO of the FPGA circuit dedicated to the JTAG test protocol, is captured. The signal capture is performed synchronously with the clock that has been specified for logic user unit  30 . This enables sampling the values of the signals to be observed while being certain that they are not changing.  
         [0050]     The control of an input/output signal or of an internal signal of tool description program  32  is obtained by the addition, in the circuit described by tool description program  32 , of a multiplexer, of two new input signals, that is, a signal S COM  which corresponds to the value which is desired to be imposed to a signal to be controlled and a signal S MUX  which controls the multiplexer, and of a new internal signal S NEW . According to an exemplary embodiment, a control register formed of a number of bits equal to twice the number of signals which is desired to be controlled, that is, equal to the number of signals S COM  and S MUX , is provided at the level of a programmed FPGA circuit. In a debugging phase, the values of S COM  and S MUX  are provided in series by debugging unit  20  to the control register by terminal TDI of the FPGA circuit dedicated to the JTAG test protocol. The new values are then effectively transmitted to logic user unit  30  synchronously with the clock signal that has been specified for logic user unit  30 . By modifying, in the debugging step, the value of one or several input/output signals and/or internal signals implemented by logic user unit  30 , different tests can be executed in a same debugging step at the normal operating speed of the FPGA circuit programmed with the modified HDL description.  
         [0051]      FIGS. 5A, 5B  to  7 A,  7 B schematically illustrate examples of implementation of the signal control of tool description program  32 .  
         [0052]      FIG. 5A  shows a logic user unit  30  containing an internal element  50  defined from the basic program written by the user and which provides an output signal S OUT  of logic user unit  30 , the value of which is desired to be imposed.  
         [0053]      FIG. 5B  shows a drawing analog to  FIG. 5A  in which a multiplexer  52  is placed downstream of element  50 . The new internal signal S NEW  corresponds to the signal provided by element  50  and drives a first input of multiplexer  52  which provides output signal S OUT . Signal S COM  drives a second input of multiplexer  52  and signal S MUX  controls multiplexer  52 .  
         [0054]      FIG. 6A  shows a logic user unit  30  containing an internal element  50  defined from a basic program written by the user and which receives an input signal S IN  of logic user unit  30 , the value of which is desired to be imposed.  
         [0055]      FIG. 6B  shows a drawing analog to  FIG. 6A  in which multiplexer  52  is placed upstream of element  50 . The new internal signal S NEW  corresponds to the signal provided by multiplexer  52  and drives internal element  50 . Input signal S IN  drives a first input of multiplexer  52 , signal S COM  drives a second input of multiplexer  52 , and signal S MUX  controls multiplexer  52 .  
         [0056]      FIG. 7A  shows a logic user unit  30  containing a first internal element  52  providing an internal signal S INT  to a second internal element  54 , the first and second internal elements  52 ,  54  being defined from the basic program written by the user. The value of internal signal S INT  is desired to be imposed.  
         [0057]      FIG. 7B  shows a drawing analog to  FIG. 7A  in which multiplexer  52  is placed between internal elements  52 ,  54 . The new internal signal S NEW  is provided by multiplexer  52  to second internal element  56 . Internal signal S INT  drives a first input of multiplexer  52 . Signal S COM  drives a second input of multiplexer  52  and signal S MUX  controls multiplexer  52 .  
         [0058]     In its simplest expression, logic user unit  30  consists of a single multiplexer comprising a first input connected to the signal, the value of which is desired to be imposed, that is, a signal of initial HDL description  12  or an input or output signal of another tool incorporated to initial HDL description  12 , and a second input receiving signal S COM . Logic user unit  30  also receives signal S MUX  which controls multiplexer  52 .  
         [0059]     More generally, the present invention enables performing tests according to specific scenarios that the user can precisely adapt to the initial HDL description. It is, for example, the verification of a complex state machine. Indeed, it would be difficult to define such a verification operation via a graphic interface while the writing of such a verification operation by a conventional programming language is generally simple and fast. The scenarios may implement test, debugging, and/or verification functions that may be used jointly or separately. Further, in a debugging phase, the user may separately or simultaneously control the signals connected to the control and observation unit of the logic user unit. The user can thus easily apply specific test vectors directly in the FPGA circuit.  
         [0060]     An HDL program may implement several control clock signals used to synchronize different parts of the FPGA circuit programmed based on the HDL program. Each logic user unit is then advantageously controlled by the control clock signal which has the highest frequency and the measurement of the observed signals is performed at the highest control clock signal frequency so that any state switching of an observation signal is captured.  
         [0061]     Of course, the present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.