Abstract:
A method for digitizing a sensed signal in a digitally assisted current sense circuit and a digitally assisted current sense circuit that uses the disclosed method realize a simple way to sense and convert an analogue current signal into a digital signal. The method includes the steps of generating a voltage corresponding to a sensed inductor current I L ; and amplifying and buffering the voltage for creating an input signal to be converted by an analogue-to-digital converter (ADC). The ADC uses an estimate of the inductor current provided by a modified digital observer circuit as a starting point for an analogue-to-digital conversion.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority of German Application No. 10 2015 105 880.4 filed on Apr. 17, 2015, the entire contents of which is hereby incorporated by reference herein. 
       FIELD OF THE INVENTION 
       [0002]    The present disclosure relates to a method for digitizing a sensed signal in a digitally assisted current sense circuit. 
         [0003]    The present disclosure also relates to a digitally assisted current sense circuit that uses the disclosed method. 
       BACKGROUND OF THE INVENTION 
       [0004]    Current sensing circuits are an important part of digital controllers in dc to dc converters. There are three broad measurement methods that are used in current sense circuits, sense-fets for example by C. F. Lee, P. K. T. Mok, et al. in “A Monolithic Current-Mode CMOS DC-DC Converter With On-Chip Current-Sensing Technique”, vol. 39, no. 1, pp. 3-14, 2004, sensorless observer circuits for example by P. Midya, P. T. Krein, and M. F. Greuel, “Sensorless Current Mode Control—An Observer-Based Technique for Dc-Dc Converters”, Trans. Power Electron., vol. 16, no. 4, pp. 522-526, 2001 and A. Kelly and K. Rinne, “Sensorless current-mode control of a digital dead-beat DC-DC converter”, Ninet. Annu. IEEE Appl. Power Electron. Conf. Expo. 2004. APEC &#39;04., vol. 3, pp. 1790-1795, and voltage drop measurement techniques for example by H. D. C. Dc, M. Supplies, et al., “Lossless Current Sensing in Low-Voltage,” IEEE Trans. IDUSTRIAL Electron., vol. 47, no. 6, pp. 1249-1252, 2000. 
         [0005]    Each of these methods has different advantages and disadvantages when used with digital power controllers. Sense-fet&#39;s require the power fet and the sensing fet to match accurately and hence are limited by needing the digital power controller to be integrated onto the same process as the power-stage, because the two transistors must experience the same effects like temperature, voltage, process variations, and so on and hence must be fabricated on the same chip, or in multi-chip solutions require the use of a power-stage with integrated sense-fets included. Observer circuits synthesize the inductor current from known variables such as input voltage, output voltage and duty cycle but suffer from limited accuracy which can only be improved with tuning circuits for example by A. Prodic, Z. Lukic, et al., “Self-Tuning Digital Current Estimator For Low-Power Switching Converters”, pp. 529-534, 2011. While in voltage drop methods the voltage across a known resistance is sensed and used to generate the current. These circuits are also difficult to design as the resistance used is typically small for efficiency reasons and hence a small voltage must be sensed with high accuracy and bandwidth. 
         [0006]    From above it can be seen that there is no simple way to sense and convert the current signal. Any method to ease this conversion is of great benefit. 
       BRIEF SUMMARY OF THE INVENTION 
       [0007]    Current sensing circuits are an important part of digital controllers in dc to dc converters. The current sense signal I L  is usually a small voltage V sense  which must be digitized with high resolution, accuracy and bandwidth. Hence the analogue-to-digital converters (ADC&#39;s) used in these circuits are difficult to design, require significant silicon area and consume high current. 
         [0008]    The disclosed invention describes a method to ease the design of the current sense ADC by using a modified digital observer circuit in parallel with the current sense path to provide an estimate of the sensed signal to the ADC. Depending on the ADC architecture used this estimate allows the ADC to use less current, have a smaller area or complete its conversion in less time and hence provides a significant advantage in the design of these circuits. 
         [0009]    The present invention relates to a method for digitizing a sensed signal in a digitally assisted current sense circuit comprising the following steps: generating a voltage corresponding to a sensed inductor current; amplifying and buffering the voltage for creating an input signal to be converted by an analogue-to-digital converter (ADC) and the ADC uses an estimate of the inductor current provided by a modified digital observer circuit as a starting point for an analogue-to-digital conversion. The digital observer circuit is modified by using the previous ADC measurement to calculate the present estimate. Typically the previous estimate would be used. But as described later equation 4 is used rather than equation 3. 
         [0010]    The modified digital observer circuit is used to estimate the current to be sensed. This estimate is then used by the ADC in the current sense path and this eases the operation of the ADC. 
         [0011]    The inductor current is estimated from already known variables such as input voltage, output voltage and duty cycle. Hence the inductor current can be synthesized by a sensor-less digital circuit. One method to realize the estimate of the inductor current involves applying a bi-linear transformation to an I-V-relationship of a voltage across a power inductor whereas the estimate is performed in a controller of the modified digital observer circuit. 
         [0012]    The inductor current I L,est  can be calculated by the following I-V-relationship: 
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         [0000]    where V L  is the voltage across the power inductor of inductance value L and dc resistance R L  and T s  is the power converters switching frequency. 
         [0013]    To make the above equation practical to use V L [n] can be replaced with the average voltage across the inductor, V L,ave [n], over one switching period of the converter. This voltage can be approximated by 
         [0000]        V   L,ave   [n]=d[n]V   in   [n]−V   out   [n]   (2)
 
         [0000]    where d[n] is the duty cycle for the nth period, V in  is the sampled input voltage and V out  is the sampled output voltage. This then leads to 
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         [0014]    The accuracy of the estimated current is mainly compromised by errors in the approximated value for V L,ave  due to unknown parasitic resistances such as the power mosfet R dson . These errors cause the estimated inductor current and the actual inductor current to diverge. To prevent such divergence the previous inductor current estimate is replaced with the accurate previous adc measurement of the inductor current. The previous inductor current is the current that was determined in the previous clock cycle [n−1], if [n] is the actual clock cycle. 
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         [0015]    In one embodiment of the invention it is advantageous to use a successive-approximation register analogue-to-digital converter (SAR ADC) that uses a modified data dependent algorithm for the analogue-to-digital conversion whereas the calculated estimate is used as the starting point for the SAR ADC conversion. 
         [0016]    Data-dependent SAR ADCs are typically used in situations where the input signal has short periods of high activity as well as long periods of low activity. In these situations the input signal can be well approximated by the previous adc output and hence a data dependent successive approximation algorithm can be used to advantage over a binary search algorithm. 
         [0017]    The modified data dependent algorithm uses 4 clock cycles (corresponding to 4 duty cycles) for sampling the input signal. Then RANGE+2 additional clock cycles are used for completing the analogue-to-digital conversion, if the estimate of the inductor current provided by the digital observer circuit is within a range of +/−2 RANGE  lsbs (last significant bits) of the final result. The purpose of this algorithm is to reduce the number of clock cycles needed per conversion by using the estimate provided by the observer circuit. If the estimate is accurate then the ADC quickly completes the conversion to full resolution however in cases where the estimate is not accurate, such as during transient current ramps, the ADC reduces its resolution and completes the conversion to less accuracy. 
         [0018]    That means, if the sampled input falls within the range the SAR ADC completes the analogue-to-digital conversion to the full resolution of the SAR ADC; if the sampled input is outside the range, the SAR ADC widens its search range by a factor of 2 with each further clock cycle and once the range is found where the sampled input falls in the analogue-to-digital conversion is completed to less accuracy. 
         [0019]    The variable RANGE is set based on an expected error of the estimator and noise of the sampled inductor current. 
         [0020]    The present invention also relates to a digitally assisted current sense circuit comprising means for generating a voltage corresponding to a sensed inductor current; amplifier for amplifying and means for buffering the voltage for creating an input signal to be converted to a corresponding digital signal; an analogue-to-digital converter (ADC) for converting the input signal to the digital signal; and a modified digital observer circuit for providing an estimate of the inductor current as a starting point for the analogue-to-digital conversion of the ADC. 
         [0021]    The modified digital observer circuit comprises a controller providing inputs for an input voltage, an output voltage, a clock cycle and a previous inductor current measurement and an output connected to an input of the ADC for forwarding an estimate of the inductor current to the ADC. 
         [0022]    In one embodiment of the invention the ADC is a successive-approximation-register analogue-to-digital converter (SAR ADC). 
         [0023]    The ADC can also be a flash analogue-to-digital converter (Flash ADC) that uses the modified digital observer circuit for reducing the necessary number of comparators that are needed to convert an analogue signal into a digital signal. 
         [0024]    By using the modified digital observer circuit that is connected to the input of the Flash ADC the number of comparators is reduced in comparison to instead of 2B-1 comparators that are typically needed in conventional Flash ADCs to realize a conversion of B bits resolution. The modified digital observer uses an estimator. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0025]    Reference will be made to the accompanying drawings, wherein: 
           [0026]      FIG. 1  shows a block diagram of the invention; 
           [0027]      FIG. 2  shows a block diagram of the current sense circuit; 
           [0028]      FIG. 3  shows a SAR ADC operation with estimate within range, wherein RANGE=3; 
           [0029]      FIG. 4  shows a SAR ADC operation with estimate outside range, wherein RANGE=3; 
           [0030]      FIG. 5  shows a circuit operation with a slow input ramp from 0 A to 60 A, with RANGE=3, I err =0.29 mArms for I ni,eq =0.25 Arms; 
           [0031]      FIG. 6  shows a circuit operation with a fast current ramp from 20 A to 40 A at 10 A/μS, with RANGE=3, I err =0.329 mArms for I ni,eq =0.25 Arms; 
           [0032]      FIG. 7  shows a circuit operation with a fast current ramp from 20 A to 40 A at 10 A/μS, with RANGE=3, I err,40 A =0.44 A, I err,20 A =0.16 A; 
           [0033]      FIG. 8  shows another embodiment of the invention using the inventive modified digital observer circuit in combination with a flash ADC. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0034]      FIG. 1  shows the principle operation of the present invention. The method according to the invention eases the design of the current sense ADC  6  by using a modified digital observer circuit  7  in parallel with the current sense path  18 ,  181 ,  182  to provide an estimate  8  of the sensed signal to the ADC  6 . Depending on the ADC architecture  6 ,  16 ,  21  used this estimate  8  allows the ADC to use less current, have a smaller area or complete its conversion in less time and hence provides a significant advantage in the design of these circuits. 
         [0035]      FIG. 2  shows a first example of an observer and data dependent SAR ADC  21 . A modified digital observer circuit  7  is used to estimate the current  8  to be sensed. This estimate is then used by the ADC  21  in the current sense path  181 ,  182  and this eases the operation of the ADC  21 .  FIG. 2  shows one possible method to use the invention. In this diagram two current sense paths  181 ,  182  are shown. The matched filter current sense approach 22 described by H. D. C. Dc, M. Supplies, et al., “Lossless Current Sensing in Low-Voltage,” IEEE Trans. IDUSTRIAL Electron., vol. 47, no. 6, pp. 1249-1252, 2000 is used to generate the signals V sense1  and V sense2    19  which are scaled versions of the inductor current I L1  and I L2    18  if the filter components, R f1 , R f2 , C f1  and C f2  are chosen correctly. The V sense1/2  signals  19  are then amplified  2  and buffered  3  to create the signal to be converted by the ADC, V in,adc    4 . The ADC used in this case is a data dependent SAR ADC  21  with a modified successive approximation algorithm to take advantage of the estimate provided by the digital observer circuit  7 . The combination of inductor current estimate  8  and data dependent SAR ADC allows the conversion time of the ADC to be reduced and hence a SAR ADC running at much lower clock frequency than a SAR using a conventional binary search algorithm can be used to convert the current sense signal of 2 channels to high resolution and bandwidth. 
         [0036]    The operation of the modified digital observer circuit  7  is described below in more detail. 
         [0037]    Digital observer circuits work by estimating the inductor current I L  from already known variables in the controller  9  such as input voltage  10 , output voltage  11  and duty cycle  12 . Hence the inductor current can be synthesized by a sensor-less digital circuit. One method to realize the inductor current involves applying the bi-linear transformation to an i-v relationship of the voltage across the power inductor L. This leads to the following equation 
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         [0038]    Where V L  is the voltage across the power inductor of inductance value L and dc resistance R L , T s  is the power converters switching frequency and I L,est  is the estimated inductor current. To make the above equation practical to use we replace V L [n] with the average voltage across the inductor, V L,ave [n], over one switching period of the converter. This voltage can be approximated by 
         [0000]        V   L,ave   [n]=d[n]V   in   [n]−V   out   [n]   (2)
 
         [0000]    Where d[n] is the duty cycle for the nth period, V in  is the sampled input voltage and V out  is the sampled output voltage. This then leads to 
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         [0039]    The accuracy of the estimated current is mainly compromised by errors in the approximated value for V L,ave  due to unknown parasitic resistances such as the power mosfet R dson . These errors cause the estimated inductor current and the actual inductor current to diverge. To prevent such divergence the previous inductor current estimate is replaced with the accurate previous adc measurement of the inductor current. 
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         [0040]    This estimate is then used as the starting point for the SAR ADC conversion. 
         [0041]    The operation of the modified data dependent SAR ADC conversion is described below in more detail. 
         [0042]    Data-dependent SAR ADCs are typically used in situations where the input signal has short periods of high activity as well as long periods of low activity. In these situations the input signal can be well approximated by the previous adc output and hence a data dependent successive approximation algorithm can be used to advantage over a binary search algorithm. 
         [0043]    In the proposed current sense circuit a SAR ADC  21  with modified data dependent algorithm is used. The purpose of this algorithm is to reduce the number of clock cycles needed per conversion by using the estimate  8  provided by the observer circuit  7 . If the estimate  8  is accurate then the ADC  21  quickly completes the conversion to full resolution however in cases where the estimate is not accurate, such as during transient current ramps, the ADC reduces its resolution and completes the conversion to less accuracy. In this way one ADC with low frequency clock can be used to digitize the current of 2 current sense channels to high resolution at times when the sensed current is static. 
         [0044]    To explain how the algorithm works in detail a 12 bit SAR ADC is used. Such an ADC would normally take 16 clock cycles to complete its conversion to 12 bit accuracy if 4 cycles are used for input sampling and a further 12 cycles are used for the 12 bit conversion. However with the modified algorithm only (RANGE+2) additional clocks are needed in addition to the sampling phases to complete the conversion to 12 bit accuracy if the estimate provided by the observer circuit is within +/−2 RANGE  lsbs of the final result. RANGE is set based on the expected error of the estimator and noise of the sampled current. Referring to the example conversion shown in  FIG. 3 , RANGE is set to 3. In the 2 cycles following input sampling, RANGE1 and RANGE2, it is determined if the input voltage is in the expected range. During RANGE1 cycle, the ADC determines if the sampled input is higher or lower than the estimated value. If for example the estimate is high during RANGE1 the ADC then compares the input against I L,est [n]−2 RANGE  lsbs during RANGE2. If as expected the sampled input falls within this window the SAR ADC completes the conversion to the full resolution of the SAR ADC as in [6]. However if the sampled input is outside this window, for example during a transient current ramp, the SAR ADC widens its search range by a factor of 2 with each further clock cycle and hence once the range is found the conversion is completed to less accuracy.  FIG. 4  illustrates this situation where an extra cycle is needed to get the sampled current within range. 
         [0045]    For illustration purposes and for showing the functionality of the present circuit operations  FIGS. 5 and 6  show different simulation schemes of the inventive circuit. The following table lists some important simulation parameters. In the following simulations an equivalent input noise of 0.25 Arms has been added to the current sense signal. This is to show the circuit operation with a realistic noise source included. 
         [0000]    
       
         
               
               
               
             
           
               
                   
                   
               
               
                   
                 Converter Type 
                 VMC 
               
               
                   
                   
               
             
             
               
                   
                 Input Voltage [V] 
                  12 
               
               
                   
                 Output Voltage [V] 
                  1 
               
               
                   
                 Output Capacitor [F] 
                 1.14m 
               
               
                   
                 Output Inductor [H] 
                 330n 
               
               
                   
                 Output Inductor DCR [Ohm] 
                 165u 
               
               
                   
                 Output Capaciitor ESR [Ohm] 
                 1.3m 
               
               
                   
                 Filter resistor, Rf [Ohm] 
                 900 
               
               
                   
                 Filter resistor, Cf [F] 
                 2.2u 
               
               
                   
                 Switching Frequency [Hz] 
                 400k 
               
               
                   
                 Load Current [A] 
                 0 A-60 A 
               
               
                   
                 Voltage Sense ADC Isb [V] 
                 1.4m 
               
               
                   
                 Voltage Sense ADC sampling freq 
                 16M 
               
               
                   
                 Current Sense ADC Isb [A] 
                  0.25 
               
               
                   
                 Current Sense ADC sampling freq 
                 400k 
               
               
                   
                 Amplifier Gain [V/V] 
                  20 
               
               
                   
                 Amplifier Bandwidth [Hz] 
                 500k 
               
               
                   
                 Ini, eq [Arms] 
                  0.25 
               
               
                   
                   
               
             
          
         
       
     
         [0046]      FIG. 5  shows the circuit operating with a slow OA to 60 A ramp and the RANGE set to 3 so the SAR ADC is allowed 9 clocks to complete its conversion rather than the usual 16. In can be seen from the plot that the estimator and data dependent ADC convert the input current with very little extra errors above those already introduced by the noise signal at the input. In this case for a slow ramp the converted current has a sigma of 0.29 mArms for a noise source with equivalent input noise of 0.25 mArms. It can also be seen from this plot that as the current increases the estimator error also increases but the conversion accuracy remains constant even though the resolution is being decreased from 11 to 9 bits in some cases. 
         [0047]      FIG. 6  shows the circuit operating with a fast current ramp. Clearly the circuit loses accuracy during the fast current ramp as seen from the spikes in the current error and resolution dropping to 8 bits.  FIG. 7  zooms in on the static error at 20 A and 40 A, the error is only 0.16 A and 0.44 A. 
         [0048]      FIG. 8  shows another embodiment of the invention using the modified observer circuit  7  in combination with a flash ADC  16  for reducing the necessary number of comparators  17  needed for the analogue-to-digital conversion. Therefore, the estimate  8  from the modified digital observer  7  can be used to reduce the number of comparators  17  needed in a flash ADC  16  used to convert the current signal. A conventional Flash ADC  16  typically requires (2B-1) comparators  17  to realise a flash ADC of B bits resolution. This usually limits the resolution of such ADCs as the area required by the comparators gets too large. Using the estimator however a much smaller number of comparators  17  can be used to complete the conversion as only the levels around the estimated current need to be tested.  FIG. 8  shows an example where an 8 bit flash ADC is realised with only 32 comparators. Clearly this saves 223 comparators. The reduction in number of comparators depends on the error of the estimator, the desired resolution of the current to be sensed and full scale current to be sensed. 
         [0049]    For another example, if a 0.25 A resolution should be achieved, and the estimator was accurate to +/−5 A and the full scale range was +/−40 A. Then (2*5 A/0.25)=40 comparators are needed with the estimator. With-out the estimator (2*40 A/0.25)=320 comparators are needed. Hence the saving is 280 comparators.