Abstract:
The present invention provides a pulse amplitude modulation sampling gate using inexpensive integrated devices having a novel feedback arrangement. The addition of a few passive components to the basic sampling gate allows the gate to coact as a three pole high pass filter. Costs are reduced by this approach by a large factor.

Description:
FIELD OF THE INVENTION 
     The present invention relates to pulse amplitude modulation sampling gates in general and more particularly to a novel pulse amplitude modulation (PAM) sampling gate including a three pole high pass filter. 
     BACKGROUND AND SUMMARY OF THE INVENTION 
     It is one of the functions of a pulse code modulation (PCM) channel bank to receive voice frequency (VF) signals from a plurality of VF lines and deliver them encoded and multiplexed in a digital time division multiplexed format. The standard for North America is the 24 channel T1 format. 
     The first stage of this process is the sampling of the analog (VF) signal to obtain a pulse amplitude modulated signal. Twenty-four of these channels are time multiplexed onto a common bus. These PAM samples are then encoded one at a time by the PCM encoder in the transmit unit of the channel bank. 
     The VF signal is band limited to 3400 Hz by a low pass active filter. Additionally 60 Hz filtering is needed in the channel bank. Currently a passive inductor/capacitor (LC) filter is provided for the 60 Hz filtering and the PAM samples are obtained in a bipolar gate. However, the gate and passive filtering prove to be expensive. 
     The present invention uses inexpensive integrated devices to reduce the cost. A novel circuit arrangement is provided to obtain the performance of the bipolar gate at reduced cost. 60 Hz filtering with this arrangement was accomplished by addition of a few additional passive components eliminating a 60 Hz filter stage prior to the bipolar gate and reducing cost by a large factor. 
     It was found that by incorporating an a-c coupling capacitor in the feedback loop of a PAM sampling gate, low output offset voltage (or pedestal) was obtained. In the prior art the a-c coupling capacitor was utilized to couple the output of the sampling gate to the following circuit. Further, the addition of another resistor-capacitor (RC) network at the input of the sampling gate enables the gate to coact as a three pole high pass filter. 
     Thus in accordance with the invention there is provided a pulse amplitude modulation sampling gate having an input and an output, a differential input operational amplifier, a first sampling switch connected between the output of said differential input operational amplifier and said output characterized in that said output, through a second sampling switch, is a-c coupled to the non-inverting input of said operational amplifier. 
     Further, in accordance with the invention there is provided a pulse amplitude modulation gate which coacts as a three pole high pass filter additionally including a resistor-capacitor network connected at the input. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The preferred embodiment of the invention will now be described with reference to the accompanying drawings in which: 
     FIG. 1 is a schematic circuit diagram of an embodiment of a PAM sampling gate using an operational amplifier and a JFET analog switch without filtering according to the invention; 
     FIG. 2 is a schematic circuit diagram of an embodiment of a PAM sampling gate including a three pole high pass filter using a JFET operational amplifier and a JFET analog switch according to the invention; 
     FIG. 3 illustrates the waveform of the clock controlling a PAM sampling gate; and 
     FIG. 4 illustrates the frequency response of the PAM sampling gate coacting as a three pole high pass filter. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 1 the PAM gate comprises an input terminal 10 for connecting an input analog signal V in  thereto, an output terminal 11 for connecting an output PAM signal V out  therefrom and a common or ground terminal 12, suitable for connection in the North American Standard T1 carrier system. The PAM gate includes a single differential-input operational amplifier (op-amp) 13 which is preferably a junction field effect transistor (JFET). JFETs are preferred due to their low cost and relatively high switching speed. A first capacitor C 1  is connected between the input terminal 10 and the non-inverting input terminal of the op amp 13. A first resistor R 1  is connected between the non-inverting terminal of the op amp 13 and the common terminal 12. A second resistor R 2  is connected between the output terminal of the op amp 13 and the inverting terminal of the op amp 13. A second capacitor C 2  and a third resistor R 3  are connected in series between the inverting input terminal of the op amp 13 and the common terminal 12. A pair of JFET analog switches having three terminals, source and drain current carrying terminals and one gate control terminal are used. The first JFET switch 14 has its source terminal connected to the output terminal of the op amp 13. The second JFET switch 15 has its source terminal connected to the junction of the capacitor C 2  and the resistor R 3 . The drain terminal of both the JFET switches 14 and 15 are connected together. A fourth resistor R 4  is connected between the junction of the drain terminals of JFET switches 14 and 15 and the output terminal 11. A fifth resistor R 5  is connected between the output terminal 11 and the common terminal 12. 
     FIG. 2 illustrates the PAM gate with filtering, which is the circuit of FIG. 1 with an additional capacitor C 3  connected between the input terminal 10 and the capacitor C 1 . 
     As well there is an additional resistor R 6  connected between the junction of capacitors C 1  and C 3  and the inverting terminal of the op amp 13. 
     In operation a VF signal is introduced to the input terminal 10. The switches are controlled by a waveform shown in FIG. 3. The switches are closed during 4.55 μsec. at zero volts and open for 120.45 μsec. at 5 volts. The total cycle is 125 μsec. 
     As an example to show the reduction of output offset assume that: 
     C 2  =0.47 μf 
     R 2  =10KΩ 
     R 3  =10KΩ 
     R 4  =22Ω 
     R 5  =1KΩ. 
     The switches are part of an LF13201 single pole single throw (SPST) JFET analog switch and the operational amplifier is an LF355 with an input offset voltage maximum of 10 mv, typical bandwidth 2.5 MHz, slew rate typical 5 V/μsec. and due to its JFET input stage, input bias currents of 200 picoamps and maximum offset currents of 50 picoamps in our example. 
     During the off time T off  the switches are open thus disconnecting the op amp from the gate output terminal 11. Capacitor C 2  charges via R 3  to the output offset voltage of the operational amplifier with a time constant τ 1  =R 3  C 2  for 120.45 μsec. 
     During the on time T on  while the PAM sample is being taken and the switches are closed so that the op amp output is connected to the gate output terminal, the capacitor C 2  is effectively connected in parallel with resistor R 2  in a feedback loop. The charge on C 2  built during the off time supplies a voltage to the inverting input terminal of such a polarity to cancel the offset voltage at the op amp output terminal. The time constant for the discharge is τ 2  =R 2  C 2 . 
     The ratio of ##EQU1## 
     The ratio of ##EQU2## 
     Equations (1) and (2) show that both τ 1  and τ 2  are relatively long time constants. 
     Any output offset produced will be limited by the on-off time ratio and the respective time constants τ 1  and τ 2 . 
     During the off time the charging equation is: ##EQU3## where: V offset  is the output offset voltage and 
     V c .sbsb.2 is the voltage across capacitor C 2  ##EQU4## 
     During the on time the discharging equation is: ##EQU5## For an equilibrium the charge and discharge equations must be equal. ##EQU6## To solve--substituting equations (1) and (2)--Equation (5) becomes: ##EQU7## Assume V offset  =100 mV ##EQU8## Solve for V c .sbsb.2 ##EQU9## 
     This voltage V c .sbsb.2 is not directly equal to the output offset voltage V offset  due to the fact that the switches have a closed resistance R s  of approximately 150 Ω. Switch 15 is effectively an attenuator with R 3  relative to the output offset, so when it is closed the charge on C 2  is attenuated by the following ratio ##EQU10## Solving ##EQU11## The effective voltage V c .sbsb.2 =V c .sbsb.2 &#39;  ##EQU12## ∴ The pedestal produced across R 4  +R 5  is V p  ##EQU13## 
     V p  is further attenuated by the divider chain of R 4  +R 5 . 
     Thus the final output offset V p  &#39; seen at output terminal 11 is: ##EQU14## 
     Thus the d-c output offset of our example of 1000 mV is reduced to 49.77 mV or greater than a factor of twenty. 
     The PAM gate, because of its use of an operational amplifier, can coact as a three pole high pass filter with the addition of a capacitor and inductor at the input. 
     The overall filter response curve is shown in FIG. 4. It is shown that at 60 Hz the response is in the order of 27 dB down with a required response minimum of 20 dB down. 
     Two poles of the filter are due to the action of the network at the input of the operational amplifier. Thus there is a pole at f 1  =1/2πC 1  R 1  and another at f 2  =1/2πC 3  R 6 . There is a double zero that occurs at the origin. 
     The third pole response is complicated by the switching of switches 14 and 15. The switching causes the pole and zero to shift in comparison with the pole location if there was no switching. Thus the third pole occurs at: ##EQU15## and the third zero occurs ##EQU16## Due to the fact that T off  /(T on  +T off ) is very close to one, the shift of the pole is small. 
     However, due to the fact that T on  /(T on  +T off ) is very much less than one, the shift of the zero is much larger.