Abstract:
The invention is directed generally to a correlated double-sampling (CDS) circuit using a smaller number of capacitors than conventional circuits. In embodiments of the invention, a first portion of the CDS circuit uses just two capacitors to sample the reset voltage, amplify the sampled reset voltage, and subtract a first reference voltage from the amplified reset voltage. A second portion of the CDS circuit uses just two capacitors to sample the signal voltage, amplify the sampled signal voltage, and subtract a second reference voltage from the amplified signal voltage. Embodiments of the invention also provide a cyclic analog-to-digital converter (ADC) including the CDS circuit.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 of Korean Patent Application No. 2006-108516 filed on Nov. 3, 2006, the entire contents of which are hereby incorporated by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention disclosed herein relates to analog-to-digital conversion circuits. More particularly, but not by way of limitation, the invention disclosed herein is concerned with a correlated double-sampling and amplifying circuit for a CMOS image sensor, and a cyclic analog-to-digital converter including such a circuit. 
         [0004]    2. Description of the Related Art 
         [0005]    A general complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) has an active pixel sensor (APS) array that includes multiple pixels arranged in rows and columns. An analog-to-digital converter (ADC) processes received pixel data, for example data associated with all columns in a selected row of the APS array. 
         [0006]    Such an ADC typically includes a correlated double sampling (CDS) circuit. In a CDS operation, an output node is reset to a predetermined reference value, a pixel charge (signal value) is transferred to the output node, and the final value of charge assigned to the pixel is the difference between the reset and signal values. The CDS circuit may also amplify the received reset and signal values, for instance by a factor of two. 
         [0007]    A conventional CDS circuit includes multiple capacitors for sampling and amplifying the reset and signal voltages, and a differential amplifier for outputting a difference between the amplified voltages. Three capacitors are typically coupled to each of the inverted and non-inverted input terminals of the differential amplifier. Therefore, in total, the conventional CDS circuit of the ADC includes six capacitors for the CDS operation and amplification of the input signal. 
         [0008]    Such circuits are disadvantageous in that the six capacitors occupy a substantial portion of layout area of the CDS circuit, increasing a chip area of the CMOS image sensor. What is needed is a CDS circuit that is more space efficient. 
       SUMMARY OF THE INVENTION 
       [0009]    The invention is directed generally to a correlated double-sampling (CDS) circuit using a smaller number of capacitors than conventional circuits. In embodiments of the invention, a first portion of the CDS circuit uses just two capacitors to sample the reset voltage, amplify the sampled reset voltage, and subtract a first reference voltage from the amplified reset voltage. A second portion of the CDS circuit uses just two capacitors to sample the signal voltage, amplify the sampled signal voltage, and subtract a second reference voltage from the amplified signal voltage. Embodiments of the invention also provide a cyclic analog-to-digital converter (ADC) including the CDS circuit. 
         [0010]    In one respect, the invention provides a correlated double-sampling (CDS) circuit. The CDS circuit includes: a first circuit configured to sample a reset voltage, amplify the sampled reset voltage by a factor of two, and subtract a first reference voltage from the amplified reset voltage to produce a first difference; a second circuit configured to sample a signal voltage, amplify the sampled signal voltage by a factor of two, and subtract a second reference voltage from the amplified signal voltage to produce a second difference; and a differential amplifier coupled to the first circuit and the second circuit, the differential amplifier configured to produce a third difference based on a comparison of the first difference and the second difference. 
         [0011]    In another respect, the invention provides an analog-to-digital converter (ADC). The ADC includes: a first circuit configured to sample a reset voltage, amplify the sampled reset voltage, and subtract a first reference voltage from the amplified reset voltage to produce a first difference; a second circuit configured to sample a signal voltage, amplify the sampled signal voltage, and subtract a second reference voltage from the amplified signal voltage to produce a second difference; a differential amplifier coupled to the first circuit and the second circuit, the differential amplifier configured to produce a third difference based on a comparison of the first difference and the second difference; a comparator coupled to the differential amplifier, the comparator configured to compare an output of the differential amplifier with at least one predetermined comparison voltage and output a result of the comparison as a digital value; and a digital-to-analog converter (DAC) coupled to the first circuit, second circuit, and comparator, the DAC configured to control the first and second reference voltages in response to the digital value. 
         [0012]    A further understanding of the nature and advantages of the present invention herein may be realized by reference to the remaining portions of the specification and the attached drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0013]    Non-limiting and non-exhaustive embodiments of the present invention will be described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various figures unless otherwise specified. In the figures: 
           [0014]      FIG. 1  is a block diagram of a CMOS image sensor, according to an embodiment of the present invention; 
           [0015]      FIG. 2  is a block diagram of the cyclic ADC shown in  FIG. 1 , according to an embodiment of the present invention; 
           [0016]      FIG. 3  is a circuit diagram of the correlated double-sampling circuit shown in  FIG. 2 , according to an embodiment of the present invention; 
           [0017]      FIG. 4  is an operational timing diagram of the correlated double-sampling circuit shown in  FIG. 3 , according to an embodiment of the present invention; 
           [0018]      FIG. 5  is a circuit diagram showing a switching feature of a reset voltage sampling operation in the correlated double-sampling circuit shown in  FIG. 3 , according to an embodiment of the present invention; 
           [0019]      FIG. 6  is a circuit diagram showing a switching feature of a signal voltage sampling operation in the correlated double-sampling circuit shown in  FIG. 3 , according to an embodiment of the present invention; 
           [0020]      FIG. 7  is a circuit diagram showing an amplifying operation of sampled reset and signal voltages in the correlated double-sampling circuit shown in  FIG. 3 , according to an embodiment of the present invention; 
           [0021]      FIG. 8  is a circuit diagram showing a switching feature of a sampling operation with the first output signal in the correlated double-sampling circuit shown in  FIG. 3 , according to an embodiment of the present invention; and 
           [0022]      FIG. 9  is a circuit diagram showing a switching feature of an amplifying operation with the first output signal in the correlated double-sampling circuit shown in  FIG. 3 , according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0023]    Preferred embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be constructed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Like reference numerals refer to like elements throughout the accompanying figures. 
         [0024]      FIG. 1  is a block diagram of a CMOS image sensor according to an embodiment of the present invention. 
         [0025]    Referring to  FIG. 1 , the CMOS image sensor in this embodiment of the present invention includes active pixel sensor (APS) array  10  coupled to a row driver  20  and a cyclic analog-to-digital converter (ADC)  30 . 
         [0026]    The APS array  10  includes multiple pixels arranged in rows and columns. The ADC  30  may perform an operation of analog-to-digital conversion to all columns for a selected row in the APS array  10 . Thus, there may be multiple ADC units coupled to the APS array  10 . 
         [0027]    The row driver  20  drives a row of the APS array  10  that is selected by a row decoder (not shown). The APS array  10  senses light by means of optical devices, and generates image signals as electric signals corresponding to the sensed light. Image signals output from the APS array  10  are analog signals. The ADC  30  receives the analog signals from the APS array  10 , and converts the received analog signals into digital signals. The ADC  30  uses a correlated double-sampling (CDS) mode in converting analog signals into digital signals. 
         [0028]    The APS array  10  normally generates a reset voltage before outputting an analog signal sensed by the optical device. The reset voltage is applied to the ADC circuit  30 . After generating the reset voltage, the APS array  10  generates an analog voltage (hereinafter, referred to as ‘signal voltage’) sensed by the optical device. The signal voltage is also applied to the ADC  30 . 
         [0029]      FIG. 2  is a block diagram of the cyclic ADC shown in  FIG. 1 , according to an embodiment of the present invention. 
         [0030]    Referring to  FIG. 2 , the ADC  30  includes a CDS circuit  31  coupled to a comparator  33  and a digital-to-analog converter (DAC)  35 . The CDS circuit  31  is configured to amplify components of the input signal V IN  by a factor of two, and perform a CDS operation on the amplified input signal. The comparator  33  is configured to convert an output V OUT  of the CDS circuit  31  into a digital value D. The DAC  35  is configured to output a reference voltage to the CDS circuit  31  in response to the digital value D output from the comparator  33 . 
         [0031]    The input signal V IN  includes the reset voltage Vrst and the signal voltage Vsig. The reset and signal voltages Vrst and Vsig, are input to the CDS Circuit  31  in sequence. The CDS circuit  31  includes first through fourth capacitors (C 1P , C 2P , C 1M , and C 2M  in  FIG. 3 ). The reset voltage Vrst is sampled through the first and second capacitors, while the signal voltage Vsig is sampled through the third and fourth capacitors. The CDS circuit  31  then amplifies each of the reset and signal voltages Vrst and Vsig by a factor of two, and performs a CDS operation on the amplified reset and signal voltages Vrst and Vsig. 
         [0032]    In performing the CDS operation, the CDS circuit  31  subtracts a reference voltage V REF  from each of the amplified signals. The reference voltage V REF  may be any one of three reference voltages (V RP , V RN , or GND in  FIG. 3 ). The first reference voltage is a positive value Vref (V RP  in  FIG. 3 ), the second reference voltage is a negative voltage-Vref (V RN  in  FIG. 3 ), and the third reference voltage is a ground voltage GND. 
         [0033]    The comparator  33  converts the output signal Vout into a digital signal D by comparing the output signal Vout with a predetermined comparison voltage. The digital signal D output from the comparator  33  has two components, D0 and D1. The comparator  33  divides a voltage range, which is provided for comparison with Vout, into three regions: the first is ranged from the negative reference voltage-Vref to a comparison voltage-Vref/4; the second is ranged from the comparison voltage-Vref/4 to a comparison voltage Vref/4; and the third is ranged from the comparison voltage Vref/4 to the positive reference voltage Vref. The three voltage regions are allocated with digital codes −1, 0, and 1, respectively. 
         [0034]    The relations among the input signal Vout and the digital values D, D0 , and D1 are given by Equation 1. 
       [Equation 1] 
       [0035]      where  Vout&gt;Vref/ 4, then  D 1=1 , D 0=0, and  D= 1; 
         [0000]      where  Vref/ 4 ≧Vout≧−Vref/ 4, then  D 1=0 , D 0=0, and  D= 0; and 
         [0000]      where  Vout&lt;−Vref/ 4, then  D 1=0 , D 0=1, and  D=− 1. 
         [0036]    The digital value D is provided to an external storage unit (not shown) and the DAC  35 . The DAC  35  provides analog reference voltages to the CDS circuit  31  in response to the digital value D (hereinafter detailed with reference to  FIG. 9 ). 
         [0037]    The CDS circuit  31  thus processes the reset and signal voltages Vrst and Vsig and receives feedback from the DAC  35 . If the number of bits of the external storage unit (not shown) storing the digital signal output from the comparator  33  is N+1, the CDS  31  repeats the sampling and amplifying operations N times. 
         [0038]      FIG. 3  is a circuit diagram of the correlated double-sampling circuit shown in  FIG. 2 , according to an embodiment of the present invention. 
         [0039]    Referring to  FIG. 3 , the CDS circuit  31  includes a first CDS circuit  311  and a second CDS circuit  313 , each coupled to a differential amplifier  315 . 
         [0040]    The first CDS circuit  311  includes a first capacitor C 1P , a second capacitor C 2P , and switches φ SHR , φ 1D , φ 1 , φ 2 , φ 3 , φ SH , φ 4 . The second CDS circuit  313  includes a third capacitor C 1M , a fourth capacitor C 2M , and switches φ SHS , φ 1D , φ 1 , φ 2 , φ 3 , φ SH , φ 4 . The first through fourth capacitors C 1P , C 2P , C 1M , and C 2M  each have the same capacitance value. The first and second CDS circuits  311  and  313  each receive the input signal V IN  and the reference voltage V REF . The input signal V IN  includes the reset and signal voltages Vrst and Vsig. The reference voltage V REF  includes the first reference voltage Vref (=V RP ), the second reference voltage-Vref (=V RN ), and the third reference voltage GND that is the ground voltage. The CDS circuit  31  conducts the sampling, amplifying, and CDS operations in response to the input signal V IN  and the reference voltage V REF . 
         [0041]    The switch φ 4  is controlled by an external independent control logic unit (not shown), being turned on to provide the first and second reference voltages V RP  and V RN  to the CDS circuit  31  when the sampled reset and signal voltages Vrst and Vsig are amplified from the CDS circuit  31 . 
         [0042]    The DAC  35  includes switches φ H , φ L , and φ M . The first, second, and third reference voltages, V RP , V RN , and GND, are determined by on/off conditions of the switches φ H , φ L , and φ M . 
         [0043]    The switches φ SHR , φ SHS , φ 1 , φ 1D , φ 2 , φ 3 , φ SH , φ 4 , φ H , φ L , and φ M  each have two poles. Moreover, the status of each of these switches influences the operation of both circuits ( 311  and  313 ) as described below. 
         [0044]      FIG. 4  is an operational timing diagram of the CDS circuit  31  shown in  FIG. 3 . 
         [0045]    The timing diagram of the switches φ H , φ L , and φ M , shown in  FIG. 4 , illustrates on/off conditions of the switches controlled by the DAC  35 . The switches, φ H , φ L , and φ M , are turned off in low (L) level periods. In high (H) level periods, only a selective one of the switches φ H , φ L , and φ M  is turned on by the DAC  35 . 
         [0046]    The CDS circuit  31  samples and amplifies the reset and signal voltages Vrst and Vsig in a CDS period. The CDS circuit  31  also performs sampling and amplifying operations during an ADC period. The CDS circuit  31  may be referred to as a double amplifier in the ADC period. 
         [0047]      FIG. 5  is a circuit diagram showing a switching feature of a reset voltage sampling operation in the CDS circuit shown in  FIG. 3 . The reset voltage sampling operation of the CDS circuit  31  will now be described with reference to  FIGS. 4 and 5 . 
         [0048]    Referring to the timing diagram shown in  FIG. 4 , the switches φ SHR , φ SH , and φ 2  are turned on in a reset voltage sampling step. As illustrated in  FIG. 5 , one end of the first capacitor C 1P  is coupled to the input signal V IN  (through the switch φ SHR ). The other end of the first capacitor C 1P  is coupled to the inverted input terminal of the differential amplifier  315  and one end of the second capacitor C 2P  (through the switch φ 2 ), and to a non-inverted output terminal of the differential amplifier  315  (through the switch φ SH ). The other end of the second capacitor C 2P  is coupled to the input signal V IN  through the switch φ SHR . 
         [0049]    In the reset voltage sampling step, the input signal V IN  applied to the CDS circuit  31  is the reset voltage Vrst. The CDS circuit  31  provides the reset voltage Vrst to the first CDS circuit  311 . The reset voltage Vrst is sampled by the first and second capacitors C 1P  and C 2P  through the switch φ SHR  that is turned on. In other words, the reset voltage Vrst is charged in the first and second capacitors C 1P  and C 2P . 
         [0050]    Charges Q 1  and Q 2  accumulated each in the first and second capacitors C 1P  and C 2P  are represented as Q 1 =C 1P ·Vrst and Q 2 =C 2P ·Vrst, respectively. 
         [0051]      FIG. 6  is a circuit diagram showing a switching feature of a signal voltage sampling operation in the CDS circuit shown in  FIG. 3 . The signal voltage sampling operation of the CDS circuit  31  will now be described with reference to  FIGS. 4 and 6 . 
         [0052]    Referring to the timing diagram shown in  FIG. 4 , the switches φ SHS , φ SH , and φ 2  are turned on in a signal voltage sampling step. As illustrated in  FIG. 6 , one end of the third capacitor C 1M  is coupled to the input signal V IN  (through the switch φ SHS . The other end of the third capacitor C 1M  is coupled to the non-inverted input terminal of the differential amplifier  315  and one end of the fourth capacitor C 2M  (through the switch φ 2 ), and to an inverted output terminal of the differential amplifier  315  (through the switch φ SH ). The other end of the fourth capacitor C 2M  is coupled to the input signal V IN  through the switch φ SHS . 
         [0053]    In the signal voltage sampling step, the input signal V IN  applied to the CDS circuit  31  is the signal voltage Vsig. The CDS circuit  31  provides the signal voltage Vsig to the second CDS circuit  313 . The signal voltage Vsig is sampled by the third and fourth capacitors C 1M  and C 2M  through the switch φ SHS  that is turned on. In other words, the signal voltage Vsig is charged in the third and fourth capacitors C 1M  and C 2M . 
         [0054]    Charges Q 3  and Q 4  accumulated each in the first and second capacitors C 1M  and C 2M  are represented as Q 3 =C 1M  Vsig and Q 4 =C 2M ·Vsig, respectively. 
         [0055]      FIG. 7  is a circuit diagram showing the amplifying operation of the sampled reset and signal voltages in the CDS circuit shown in  FIG. 3 . The amplifying operation of the sampled reset and signal voltages in the CDS circuit  31  will now be described with reference to  FIGS. 4 and 7 . 
         [0056]    Referring to the timing diagram shown in  FIG. 4 , since the switches φ SHR  and φ SHS  are turned off in an amplifying &amp; CDS step of the sampled reset and signal voltages, the input signal V IN  is interrupted and the switches φ 2 , φ 3 , and φ 4  are turned on. Thus, as illustrated in  FIG. 6 , one end of the first capacitor C 1P  is coupled to the first reference voltage V RP  (Vref) through the switch φ 4 . The other end of the first capacitor C 1P  is connected to the inverted input terminal of the differential amplifier  315  and one end of the second capacitor C 2P  (through the switch φ 2 ). The other end of the second capacitor C 2P  is connected to the non-inverted output terminal of the differential amplifier  315  through the switch φ 3 . The second capacitor C 2P  forms a feedback loop of the differential amplifier  315 . 
         [0057]    One end of the third capacitor C 1M  is coupled to the second reference voltage V RN  (−Vref) through the switch φ 4 . The other end of the third capacitor C 1M  is connected to the non-inverted input terminal of the differential amplifier  315  and one end of the fourth capacitor C 2M  (through the switch φ 2 ). The other end of the fourth capacitor C 2M  is connected to the inverted output terminal of the differential amplifier  315  through the switch φ 3 . The fourth capacitor C 2M  forms a feedback loop of the differential amplifier  315 . 
         [0058]    In this configuration, the first CDS circuit  311  receives the first reference voltage V RP  and the second CDS circuit  313  receives the second reference voltage V RN . Thus, charge amounts accumulated in the first and third capacitors C 1P  and C 1M  are varied by the first and second reference voltages V RP  and V RN , respectively. In detail, a variation of charges at the first capacitor C 1P , ΔQ 1 , becomes ΔQ 1 =C 1P (Vrst−V RP ). This variation is transferred into the second capacitor C 2P . As a result, the final value of the sampled reset voltage Vrst becomes Vout ( 01 )=(Q 2 +ΔQ 1 )/C 2P =(C 1P (Vrst−V RP )+C 2P ·Vrst)/C 2P . As the first and second capacitors C 1P  and C 2P  have the same capacitance values, the final output Vout ( 01 ) of the sampled reset voltage Vrst is given by Equation 2. 
       [Equation 2] 
       [0059]        Vout ( 01 )=2 Vrst−V   RP    
         [0060]    Hence, the first CDS circuit  311  samples the reset voltage Vrst and amplifies the sampled reset voltage Vrst by a factor of two. Further, the first CDS circuit  311  subtracts the first reference voltage V RP  from the amplified reset voltage. 
         [0061]    A variation of charges at the third capacitor C 1M , ΔQ 3 , becomes ΔQ 3 =C 1M (Vsig−V RN ). This variation is transferred into the fourth capacitor C 2M . As a result, the final value of the sampled signal voltage Vsig becomes Vout ( 02 )=(Q 4 +ΔQ 3 )/C 2M ×(C 1M (Vsig−V RN )+C 2M ·Vsig)/C 2M . As the third and fourth capacitors C 1M  and C 2M  have the same capacitance value, the final output Vout ( 02 ) of the sampled signal voltage Vsig is given by Equation 3. 
       [Equation 3] 
       [0062]        Vout ( 02 )=2 Vsig−V   RN    
         [0063]    Hence, the second CDS circuit  313  samples the signal voltage Vsig and amplifies the sampled signal voltage Vsig by a factor of two. Further, the second CDS circuit  313  subtracts the second reference voltage V RN  from the amplified signal voltage. 
         [0064]    The differential amplifier  315  outputs a difference between the outputs Vout ( 01 ) and Vout ( 02 ) of the first and second CDS circuits  311  and  313 . Thus, a signal Vout ( 0 ) output from the CDS circuit  31  becomes Vout ( 0 )=2Vrst−V RP −(2Vsig−V RN ) as follows. 
       [Equation 4] 
       [0065]        Vout ( 0 )=2( Vrst−Vsig )−( V   RP   −V   RN ) 
         [0066]    The output signal Vout ( 0 ) means the first output signal of the CDS circuit  31 . The first output signal Vout ( 0 ) is generated from processing the input reset and signal voltages Vrst and Vsig in the CDS mode. 
         [0067]    Referring to Equation 4, the CDS circuit  31  amplifies a difference between the input reset and signal voltage Vrst and Vsig by a factor of two. Further, the CDS circuit  31  subtracts a difference between the first and second reference voltages V RP  and V RN  from the amplified difference signal. 
         [0068]    The CDS circuit  31  samples the reset voltage Vrst through the first and second capacitors C 1P  and C 2P  of the first CDS circuit  311 , and amplifies the sampled reset voltage Vrst. The CDS circuit  31  also samples the signal voltage Vsig through the third and fourth capacitors C 1M  and C 2M  of the second CDS circuit  313 , and amplifies the sampled signal voltage Vsig. Therefore, since the CDS circuit  31  according to embodiments of the invention uses only four capacitors C 1P , C 2P , C 1M , and C 2M  for sampling and amplifying the input signal V IN , it is able to reduce the chip area of the CMOS image sensor. In addition, as the CDS circuit  31  samples and amplifies the reset and signal voltages Vrst and Vsig through the first and second CDS circuits  311  and  313 , it is efficient in conducting the CDS process. 
         [0069]    The output signal Vout from the CDS circuit  31  includes output signals V OP  and V OM  that are contrary to each other in phase but the same in amplitude. 
         [0070]    The input signal V IN  is processed by the CDS circuit  31  in the CDS mode and converted into a digital signal D. The converted digital signal D is provided to an external storage unit (not shown) and the DAC  35 . The DAC  35  selects the first reference voltage V RP , the second reference voltage V RN , or the third reference voltages GND in response to the digital signal D. 
         [0071]      FIG. 8  is a circuit diagram showing a switching feature of a sampling operation with the first output signal in the CDS circuit shown in  FIG. 3 . The sampling operation with the first output signal will now be described with reference to  FIGS. 4 and 8 . 
         [0072]    The second and fourth capacitors, C 2P  and C 2M , hold the first output signal Vout ( 0 ) that is generated from the amplifying &amp; CDS step with the sampled reset and signal voltages Vrst and Vsig. The first output signal of the first CDS circuit  311  is Vout ( 01 )=2Vrst−V RP  and the first output signal of the second CDS circuit  313  is Vout ( 02 )=2Vsig−V RN . Thus, in the Sampling A step shown in  FIG. 4 , the charge amount Q 2  of the second capacitor C 2P  is Q 2 =C 2P  (Vout ( 01 )) and the charge amount Q 4  of the fourth capacitor C 2M  is Q 4 =C 2M  (Vout ( 02 )). 
         [0073]    Referring to the timing diagram of  FIG. 4 , the switches φ 3 , φ 1 , and φ 1D  are turned on in the Sampling A step. Thus, one end of the first capacitor C 1P  of the first CDS circuit  311  is connected to one end of the second capacitor C 2P  through the switch φ 1D  and, through the switches φ 1D  and φ 3 , to the non-inverted output terminal of the differential amplifier  315 . The other end of the first capacitor C 1P  is coupled to the ground voltage GND through the switch φ 1 . The other end of the second capacitor C 2P  is connected to the inverted input terminal of the differential amplifier  315 . The second capacitor C 2P  forms a feedback loop of the differential amplifier  315 . 
         [0074]    One end of the third capacitor C 1M  of the second CDS circuit  313  is connected to one end of the fourth capacitor C 2M  through the switch φ 1D  and, through the switches φ 1D  and φ 3 , to the inverted output terminal of the differential amplifier  315 . The other end of the third capacitor C 1M  is coupled to the ground voltage GND through the switch φ 1 . The other end of the fourth capacitor C 2M  is connected to the non-inverted input terminal of the differential amplifier  315 . The fourth capacitor C 2M  forms a feedback loop of the differential amplifier  315 . 
         [0075]    In this configuration, the first output signal Vout ( 0 ) is charged in the first and second capacitors C 1P  and C 1M . The first output signal of the first CDS circuit  311 , Vout ( 01 )=2Vrst−V RP , is charged in the first capacitor C 1P , while the first output signal of the second CDS circuit  313 , Vout ( 02 )=2Vsig−V RN , is charged in the third capacitor C 1M . Therefore, the charge amount Q 1  accumulated in the first capacitor C 1P  is Q 1 =C 1P  (Vout ( 01 )) and the charge amount Q 3  accumulated in the third capacitor C 1M  is Q 3 =C 1M  (Vout ( 02 )). 
         [0076]      FIG. 9  is a circuit diagram showing a switching feature of an amplifying operation with the first output signal in the CDS circuit shown in  FIG. 3 . 
         [0077]    Referring to the timing diagram shown in  FIG. 4 , the switches φ 3  and φ 2  are turned on in the Amplifying A step. In addition, the switches for supplying the reference voltages, as selected by the DAC  35 , are also selectively activated. 
         [0078]    The DAC  35  turns on the switches φ H , φ L , and φ M  in response to the digital values D1 and D0 output from the comparator  33  using an internal control logic unit (not shown). For instance, if the digital signals (i.e., the digital values) of the comparator  33  are D1=1 and D0=0, the DAC  35  turns the switch φ H  on. In this instance, the first CDS circuit  311  receives the first reference voltage V RP  and the second CDS circuit  313  receives the second reference voltage V RN . If the digital signals of the comparator  33  are D1=0 and D0=1, the DAC  35  turns the switch φ L  on. In this case, the first CDS circuit  311  receives the second reference voltage V RN  and the second CDS circuit  313  receives the first reference voltage V RP . If the digital signals of the comparator  33  are D1=0 and D0=0, the DAC  35  turns the switch φ M  on. In this instance, both the first and second CDS circuits  311  and  313  receive the ground voltage GND. 
         [0079]    As the switches φ 3  and φ 2  are turned on, one end of the first capacitor C 1P  of the first CDS circuit  311  is coupled to the reference voltage selected by the DAC  35 . The other end of the first capacitor C 1P  is connected to the inverted input terminal of the differential amplifier  315  and one end of the second capacitor C 2P  through the switch φ 2 . The other end of the second capacitor C 2P  is connected to the non-inverted output terminal of the differential amplifier  315 . The second capacitor C 2P  forms a feedback loop of the differential amplifier  315 . 
         [0080]    In addition, when the switches φ 3  and φ 2  are turned on, one end of the third capacitor C 1M  of the second CDS circuit  313  is coupled to the reference voltage selected by the DAC  35 . The other end of the third capacitor C 1M  is connected to the non-inverted input terminal of the differential amplifier  315  and one end of the fourth capacitor C 2M  through the switch φ 2 . The other end of the fourth capacitor C 2M  is connected to the inverted output terminal of the differential amplifier  315 . The fourth capacitor C 2M  forms a feedback loop of the differential amplifier  315 . 
         [0081]    With this configuration, charge amounts accumulated in the first and third capacitors C 1P  and C 1M  are varied by the reference voltages selected by the DAC  35 . For instance, if the DAC  35  turns switch φ H  on, then the first reference voltage V RP  is applied to the first CDS circuit  311  and the second reference voltage V RN  is applied to the second CDS circuit  313 . 
         [0082]    When the first and second reference voltages V RP  and V RN  are applied, the variation ΔQ 1  of charges accumulated in the first capacitor C 1P  becomes ΔQ 1 =C 1P (Vout ( 01 )−V RP ) and the variation ΔQ 2  of charges accumulated in the third capacitor C 1M  becomes ΔQ 2 =C 1M (Vout ( 02 )−V RN ). The charge variation ΔQ 1  is transferred to the second capacitor C 2P  and the charge variation ΔQ 2  is transferred to the fourth capacitor C 2M . 
         [0083]    Therefore, the final output of the first CDS circuit  311  becomes Vout ( 11 )=(Q 2 +ΔQ 1 )/C 2P =(C 1P (Vout ( 01 )−V RP )+C 2P ·Vout ( 01 ))/C 2P . As the first and second capacitors C 1P  and C 2P  have the same capacitance value, the final output Vout ( 11 ) of the first CDS circuit  311  is given by Equation 5. 
       [Equation 5] 
       [0084]        Vout ( 11 )=2 Vout ( 01 )− V   RP    
         [0085]    The final output of the second CDS circuit  313  becomes Vout ( 12 )=(Q 4 +ΔQ 3 )/C 2M =(C 1M (Vout ( 02 )−V RN )+C 2M ·Vout ( 02 ))/C 2M . As the third and fourth capacitors C 1M  and C 2M  have the same capacitance value, the final output Vout ( 12 ) of the second CDS circuit  313  is given by Equation 6. 
       [Equation 6] 
       [0086]        Vout ( 12 )=2 Vout ( 02 )− V   RN    
         [0087]    Therefore, the first CDS circuit  311  receives the output signal Vout ( 01 ), which is output from the amplifying &amp; CDS step with the sampled reset and signal voltages Vrst and Vsig, by way of the feedback loop, and samples the output signal Vout ( 01 ). The first CDS circuit  311  amplifies the sampled signal Vout ( 01 ) by a factor of two. The first VDS circuit  311  then subtracts the first reference voltage V RP , which is selected by the DAC  35 , from the amplified signal Vout ( 01 ). 
         [0088]    Meanwhile, the second CDS circuit  313  receives the output signal Vout ( 02 ), which is output from the amplifying &amp; CDS step with the sampled reset and signal voltages Vrst and Vsig, by way of the feedback loop, and samples the output signal Vout ( 02 ). The second CDS circuit  313  amplifies the sampled signal Vout ( 02 ) by a factor of two. Then, the second CDS circuit  313  subtracts the second reference voltage V RN , which is selected by the DAC  35 , from the amplified signal Vout ( 02 ). 
         [0089]    The differential amplifier  31  outputs a difference between the first and second CDS circuits  311  and  313 . Hence, a signal output from the CDS circuit  31  becomes Vout ( 1 )=2Vout ( 01 )−V RP −(2Vout ( 02 )−V RN ) as follows. 
       [Equation 7] 
       [0090]        Vout ( 1 )=2( Vout ( 0 ))−( V   RP   −V   RN ) 
         [0091]    The output signal Vout ( 1 ) means a second output signal of the CDS circuit  31 . The second output signal Vout ( 1 ) is obtained by sampling the first output signal Vout ( 0 ) input to the CDS circuit  31  through the feedback loop, amplifying the sampled first output signal Vout ( 0 ), and subtracting the reference voltage selected by the DAC  35  from the amplified first output signal Vout ( 0 ). 
         [0092]    The secondary sampling and amplifying steps (Sampling B and Amplifying B) shown in  FIG. 4  are performed the same as the Sampling A and Amplifying A steps, and so will not be described in detail. The ADC  30  repeats the sampling and amplifying operations through the CDS circuit  31  after inputting the reset and signal voltages Vrst and Vsig. If the number of bits of an external storage unit for storing the digital signals output from the comparator  33  is N+1, the sampling and amplifying operations of the CDS circuit  31  is repeated in N cycle times. 
         [0093]    In summary, the ADC  30  samples the reset voltage Vrst through the first and second capacitors C 1P  and C 2P  of the first CDS circuit  311 , and amplifies the sampled reset voltage Vrst by a factor of two. The ADC  30  also samples the signal voltage Vsig through the third and fourth capacitors C 1M  and C 2M  of the second CDS circuit  313 , and amplifies the sampled signal voltage Vsig by a factor of two. The first CDS circuit  311  subtracts the first reference voltage V RP  from the amplified reset voltage Vrst and outputs the difference. The second CDS circuit  313  subtracts the second reference voltage V RN  from the amplified signal voltage Vsig and outputs the difference. Then, the differential amplifier  315  outputs a difference between outputs of the first and second CDS circuits  311  and  313 . 
         [0094]    Hence, since the ADC  30  according to the present invention uses the four capacitors in sampling and amplifying the input signal V IN , it is able to reduce the chip area of the CMOS image sensor. Additionally, as the ADC  30  samples and amplifies the reset and signal voltages Vrst and Vsig through the first and second CDS circuits  311  and  313  of the CDS circuit  31 , corresponding respectively thereto, it is efficient in conducting the CDS process. 
         [0095]    The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the present invention. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.