Abstract:
Described are high-speed parallel-to-serial converters. The converters include data combiners with differential current-steering circuits that respond to parallel data bits by producing complementary current signals representing a differential, serialized version of the parallel data bits. One embodiment includes inductive and resistive loads to equalize the gain over the frequency of interest to reduce data-deterministic jitter.

Description:
This application is a division of Ser. No. 10/346,704 filed Jan. 17, 2003 now U.S. Pat. No. 6,812,872, which is a continuation-in-part of Ser. No. 10/043,771 filed Jan. 9, 2002 now U.S. Pat. No. 6,611,218. 

   BACKGROUND 
   Modern digital systems represent digital data either in series (i.e., as a series of bits) or in parallel (i.e., as a transmitting one or more bytes simultaneously using multiple data lines). While it is generally easier to store and manipulate data in parallel, it is often beneficial to transmit data in series. Many systems therefore employ parallel-to-serial converters. 
     FIG. 1  (prior art) depicts a parallel-to-serial converter  100  that serializes ten-bit words presented in parallel on data lines D&lt;9:0&gt;. Converter  100  includes a parallel shifter  105 , which in turn includes a pair of five-bit shift registers  110  and  115 . Shift registers  110  and  115  each connect to one of a pair of complementary clocks C EV  and C OD . Designations C EV  and C OD  stand for “clock even” and “clock odd,” respectively, because even data bits are presented on an output terminal D OUT  when C EV  is high and odd data bits are presented on output terminal D OD  when D EV  is high. 
   Every fifth rising edge of clock C EV , register  110  stores the even-numbered data bits D&lt;8,6,4,2,0&gt; presented on bus D&lt;9:0&gt; and register  115  stores the odd-numbered data bits D&lt;9,7,5,3,1&gt; presented on the same bus. Each of registers  110  and  115  then presents their respective data one bit at a time, so that both odd and even data bits are presented alternately to a data combiner  120 . Data combiner  120  alternately gates the odd and even data bits presented on respective data terminals D OD  and D EV  to produce a serialized version of the data produced by shifter  105 . 
   If manufactured using commonly available CMOS processes, converter  100  can perform with clock frequencies as high as about 2 Ghz. This is too slow for many modern high-speed digital communication systems, which can transmit serial data in the 10 Gb/s range. More exotic processes, such as those employing silicon germanium or gallium arsenide, provide improved high-frequency response; unfortunately, this improvement comes at considerable expense. 
   SUMMARY 
   The present invention is directed to differential circuits capable of operating at speeds sufficient to meet the needs of modern communication systems without consuming excessive power or requiring complex and expensive fabrication technologies. Converters in accordance with the invention include data combiners—a type of differential amplifier—that employ current sources and differential current-steering circuits. The current-steering circuits respond to parallel data bits by producing complementary current signals representing a differential, serialized version of the parallel data bits. One embodiment of the invention includes complementary data-input transistors to expedite the data combiner&#39;s response to changes in input data. Yet another embodiment includes inductive and resistive loads to equalize the gain over the frequency of interest to reduce data-deterministic jitter. 
   This summary does not define the scope of the invention, which is instead defined by the allowed claims. 

   
     BRIEF DESCRIPTION OF THE FIGURES 
       FIG. 1  (prior art) depicts a parallel-to-serial converter  100  that serializes converts ten-bit words presented in parallel on data lines D&lt;9:0&gt;. 
       FIG. 2A  depicts a data combiner  200  in accordance with one embodiment of the invention. 
       FIG. 2B  is a timing diagram  250  depicting the operation of current-steering circuit  205  of  FIG. 2A . 
       FIG. 3  depicts a parallel-to-serial converter  300  in accordance with another embodiment of the invention. 
       FIG. 4A  details an embodiment of data combiner 
       FIG. 4B  is a waveform diagram  430  depicting the operation of current-steering circuit  400  of  FIG. 4A . 
       FIG. 5  is a Bode plot  500  depicting an illustrative AC response for combiner circuit  200  of  FIG. 2 . 
       FIG. 6A  is a waveform diagram  600  of an output signal OUT from data combiner  200 . 
       FIG. 6B  highlights the data-deterministic jitter using a pair of complementary output signals OUT and OUTb that produce an “eye” pattern. 
       FIG. 7  depicts a data combiner  700  in accordance with an embodiment of the invention that ameliorates the problem of data-deterministic jitter. 
       FIG. 8  is a Bode plot  800  depicting the AC response of data combiner  700  of  FIG. 7 . 
       FIG. 9  is a waveform diagram  900  illustrating complementary output signals OUT and OUTb of data combiner  700  of  FIG. 7 . 
   

   DETAILED DESCRIPTION 
     FIG. 2A  depicts a data combiner  200  in accordance with one embodiment of the invention. Data combiner  200 , a type of differential amplifier, serializes two-bit data bytes at a rate far greater than can be achieved using data combiner  120  of  FIG. 1 . Data combiner  200  includes a pair of current-steering circuits  205  and  210 , each of which receives a pair of complementary clock signals C OD  and C EV . Steering circuit  205  steers current from a current source  215  to an output terminal OUTb and from output terminal OUTb to ground in response to even and odd data signals D EV  and D OD . The steered current represents a serialized version of data signals D EV  and D OD ; similarly, steering circuit  210  receives the complements D EV  and D OD  of respective even and odd data signals D EV  and D OD  to produce a serialized version of these data signals on an output terminal OUT. The serialized data signals on lines OUT and OUTb are complementary; signal designations terminating in a lower-case “b” identify active-low signals. Data combiner  200  drives a load, represented as a resistor R L , by steering current between output terminals OUT and OUTb in either direction. 
   Steering circuit  205  includes a pair of differential NMOS input transistors  220  and  225  having their respective control terminals (gates) tied to data terminals D EV  and D OD . Steering circuit  205  also includes a pair of differential NMOS input transistors  230  and  235  having their respective control terminals tied to respective complementary clock terminals C EV  and C OD . Finally, circuit  205  includes a pair of PMOS transistors  240  and  245  having their respective control terminals connected to respective data terminals D EV  and D OD . Complementary transistors  220  and  240  form an inverter that connects between input terminal D EV  and output terminal OUTb via transistor  230 . Steering circuits  205  and  210  are structurally identical, so a detailed discussion of steering circuit  210  is omitted for brevity. 
     FIG. 2B  is a timing diagram  250  depicting the operation of current-steering circuit  205  of  FIG. 2A . Diagram  250  assumes two arbitrary even and odd data streams, received in parallel, to be serialized by data combiner  200 . Each signal is identified using the node designation for the corresponding terminal. Whether a given designation refers to a node or a signal will be clear from the context. 
   Beginning at time T 0 , the odd and even data signals D EV  and D OD  are both logic zeroes. Transistors  220  and  225  are therefore biased off and transistors  240  and  245  biased on, so that terminals X 1  and X 2  both approach power-supply voltage VDD. Clocks C EV  and C OD  are high and low, respectively (clock C OD  is the complement of C EV ); consequently, transistor  230  is on and transistor  235  is off. Transistor  220  is off, so current-steering circuit  200  steers the current from current source  215  out through terminal OUTb. Since signal OUTb is active low, terminal OUTb expresses a positive (outgoing) current at time T 0  to express a logic zero. The logic zero “even” data on terminal D EV  is therefore expressed on output terminal OUTb between times T 0  and T 1 . 
   At time T 1 , the odd and even data signals D EV  and D OD  are still both logic zero, but clock signals C EV  and C OD  reverse. Transistor  235  is therefore biased on and the odd data signal D OD  selected to determine the logic level on output terminal OUTb. In this case, the output signal OUTb does not change; however, during this period the “odd” data on terminal D OD  is responsible for the logic zero expressed on output terminal OUTb. 
   Even data signal D EV  transitions to a logic one some time between T 1  and T 2 . Transistor  220  responds, pulling terminal X 1  toward ground potential. Then, at time T 2 , clock signal C EV  turns on transistor  230  so transistors  230  and  220  steer the current from source  215  to ground and away from output terminal OUTb. Data combiner  200  thus expresses a logic one output signal (recall that OUTb is active low, so a logic one is expressed using a “negative” current on that terminal). 
   Skipping ahead, the odd data signal D OD  changes from a logic one to a logic zero between times T 4  and T 5 . In the absence of transistor  245 , terminal X 2  would not respond to the change on terminal D OD  until transistor  235  turns on again at time T 5 . Current from current source  215  would then be steered to terminal X 2 , delaying the state change on output terminal OUTb until after time T 5 . Such a delay would undesirably slow the operation of data combiner  200 . The inclusion of transistor  245  expedites the transition on terminal X 2  by connecting terminal X 2  to VDD as soon as the data DOD transitions, thus pre-charging terminal X 2  a time t before time T 5 . When transistor  235  turns on, current source  215  does not waste valuable time charging node X 2 , so output terminal OUTb transitions more rapidly. Transistor  240  provides the same advantage as transistor  245  for data on terminal D EV . 
   Output signals OUT and OUTb are depicted as voltage fluctuations for clarity; however, the logic levels between output terminals OUT and OUTb are primarily expressed using differential currents. The preferred embodiments of the invention use current steering and differential signaling to improve noise immunity and to reduce the voltage swing required to express logic levels. These improvements deliver devices capable of higher data transmission speeds, greater bandwidth, and lower power consumption. 
   Current-steering circuit  210  functions identically to circuit  205  using complementary data signals. The resulting output signal on terminal OUT is therefore complementary to the signal on terminal OUTb. 
     FIG. 3  depicts a parallel-to-serial converter  300  in accordance with another embodiment of the invention. Converter  200  of  FIG. 2  serializes two-bit data; converter  300  of  FIG. 3  illustrates how the invention can be extended to serialize data represented using more than 2 bits. Converter  300  illustrates an example that serializes eight-bit data, but the invention can be extended to more or fewer that eight bits. 
   Converter  300  includes a conventional 8-phase phase-locked loop (PLL)  305  that produces, from a clock signal CLK, eight phase-delayed clocks signals C&lt;7:0&gt;. In one embodiment, the phase difference between clock signals C&lt;7:0&gt; is about 100 picoseconds. Converter  300  also includes a conventional shifter  310  that uses eight shift registers (not shown) and the eight phase-delayed clocks signals C&lt;7:0&gt; to convert each of a series of 64-bit data words on a bus D&lt;63:0&gt; into a series of eight eight-bit data words on a bus D&lt;7:0&gt;. Finally, converter  300  includes a data combiner  315  adapted in accordance with the invention to serialize the eight-bit data on lines D&lt;7:0&gt; using the clock signals on lines C&lt;7:0&gt;. Combiner  315  presents the serialized data as a pair of differential output signals TX and TXb on like-named output terminals. Terminal TX — VCM is the common-mode voltage terminal between the TX and TXb output terminals, and is produced, for example, between a pair of 50-ohm resistors. The common-mode voltage on terminal TX — VCM can be used in a conventional feedback configuration to set the common mode. 
     FIG. 4A  details an embodiment of data combiner  315 . Data combiner  315  includes a pair of complementary current-steering circuits  400  and  405  that provide respective complementary serialized signals TX and TXb. Circuits  400  and  405  are identical except that they receive complementary data signals to produce their respective complementary output signals. A detailed description of combiner  405  is therefore omitted for brevity. 
   Current-steering circuit  400  includes PMOS switch network  410  connected between a first current source  415  and output terminal TX and an NMOS switch network  420  connected between a second current source  425  and output terminal TX. Current steering circuit  400  expresses logic ones by directing current from current source  415  through switch network  410  to output terminal TX, and expresses logic zeroes by sinking current from terminal TX through switch network  420  and current source  425 . 
     FIG. 4B  is a waveform diagram  430  depicting the operation of current-steering circuit  400  of  FIG. 4A . Diagram  430  shows clock signal CLK, the eight phase-shifted signals C&lt;7:0&gt;, and a graphical representation of output signal TX. Complementary clock signals Cb&lt;7:0&gt; and complementary output signal TXb are omitted from  FIG. 4A . 
   From time T 0  to time T 1 , clock signals C 0  and C 5  are both high and their complementary counterparts Cb 0  and Cb 5  are low. The relative phases of clocks C&lt;7:0&gt; (and their complements) are such that in switch network  410  only the four transistors in the far-right column connected to clock terminals C 0 , C 5 , Cb 0 , and Cb 5  are biased on. The two transistors in the same far-right column with their control terminals connected to data terminal Db 0  therefore determine the logic level expressed on output terminal TX: if complementary data signal Db 0  is a logic zero, the PMOS transistor with its gate connected to terminal Db 0  turns on to complete the path for current between current source  415  and output terminal TX; if data signal Db 0  is a logic one, the NMOS transistor with its gate connected to terminal Db 0  turns on to complete the path for current between output terminal TX and current source  425 . Thus, of the eight data signals Db&lt;7:0&gt; presented to steering circuit  400 , the output signal TX is determined solely by the level on data terminal Db 0  from time T 0  to T 1 . This aspect of circuit  400  is depicted in diagram  430  as the “D 0 ” associated with signal TX, which is to say that output TX reflects that data bit at D 0  from time T 0  to time T 1 . 
   Clock signals C&lt;7:0&gt; combine to form eight unique combinations of clock signals, one combination for each presentation of data D&lt;7:0&gt;. Steering circuit  400  decodes each of the combinations of clock signals to present the eight data bits in series on output terminal TX before a subsequent sequence of eight bits is presented on data terminals D&lt;7:0&gt;. 
   The second steering circuit  405  is identical to steering circuit  400 , except that steering circuit  405  receives data signals D&lt;7:0&gt;, the complement of the data signals Db&lt;7:0&gt; presented to steering circuit  400 . Thus configured, steering circuit  405  produces an output signal TXb that is the complement of output signal TX. Thus, when steering circuit  400  provides current from current source  415  to output terminal TX, steering circuit  405  simultaneously sinks current from output terminal TXb through a current source in steering circuit  405  identical to current source  425 ; similarly, when steering circuit  400  sinks current from output terminal TX via current source  425 , steering circuit  405  will simultaneously source current to output terminal TXb via a current source in steering circuit  405  identical to current source  415 . 
     FIG. 5  is a Bode plot  500  depicting an illustrative AC response for combiner circuit  200  of  FIG. 2A . Inherent capacitances within combiner circuit  200  produce a dominant pole, creating a roll-off frequency of between about 200 and 300 MHz. From the roll-off frequency, the AC response degrades at about 20 dB per decade. The gain of combiner circuit  200  at 200 MHz is more than an order of magnitude greater than at 5 GHz, about 28 dB greater in one embodiment. This significant gain difference produces fluctuations in rise and fall times, and consequently introduces unwanted data-deterministic jitter. 
   Data combiner  200  switches at relatively low frequencies when producing streams of consecutive ones or zeroes. In such cases, data combiner  200  produces extreme voltage levels due to the relatively high gain at low frequencies. In contrast, combiner  200  switches at a much higher frequency to produce a series of alternating ones and zeroes, and consequently achieves a lower peak-to-peak output level. The shape of signal transitions in output signal OUT therefore depends in part on the preceding data pattern. The gain variation over the bandwidth of interest introduces undesirable data-dependent jitter in the output signal. 
     FIG. 6A  is a waveform diagram  600  of an output signal OUT from data combiner  200 , and illustrates how different data patterns can introduce jitter in output signal OUT. The high logic level  605  following first low-to-high transition of diagram  600  is of a different width than the second high logic level  610  following the second low-to-high transition. The same is true of the two low levels  615  and  620  following high-to-low transition  625 . 
     FIG. 6B  highlights the data-deterministic jitter using a pair of complementary output signals OUT and OUTb that produce an “eye” pattern. The two “eyes”  635  and  640  following streams of successive ones and zeros are shorter than those eyes produced by alternating ones and zeros. 
   The waveforms of  FIGS. 6A and 6B  are not intended to show the actual impact of data-deterministic jitter on data combiner  200 , but are instead intended to illustrate that the output of data combiner  200  depends on both the data combiner&#39;s gain curve and on historic data patterns, and that this dependency introduces undesirable data jitter. This problem, and the following solution, is also applicable to other embodiments, including those of  FIGS. 3 and 4A . 
     FIG. 7  depicts a data combiner  700  in accordance with an embodiment of the invention that ameliorates the problem of data-deterministic jitter. Data combiner  700  is a differential amplifier similar to data combiner  200  of  FIG. 2A , like-numbered elements being the same or similar. In addition to the components of data combiner  200 , data combiner  700  includes a pair of resistors  705  and  710 , an inductor  715 , and four PMOS transistors  720 . The resistors and inductor flatten the AC response of data combiner  700  to reduce data-deterministic gain jitter; the additional PMOS transistors enable and disable data combiner  700  in response to an active-low enable signal on line ENb. The description of the logical operation of data combiner  700  is similar to that of data combiner  200  and is therefore omitted here for brevity. 
     FIG. 8  is a Bode plot  800  depicting the AC response of data combiner  700  ( FIG. 7 ) from DC to a unity-gain frequency F UG . For comparison,  FIG. 8  also includes the AC response of data combiner  200  ( FIG. 2 ) as a dashed line. 
   Returning to  FIG. 7 , inductor  715  acts as a short at relatively low frequencies, and thus reduces the low-frequency gain of data combiner  700 . The amount of gain reduction depends on the value of the load resistance R L  and the values selected for resistors  705  and  710 . In one embodiment, the inclusion of inductor  715  and resistors  705  and  710  reduces the DC gain by over 20 dB, e.g. from about 40 dB to about 15 dB. As with the similar data combiner  200 , inherent capacitances within combiner circuit  700  produce a dominant pole, creating a roll-off frequency F RO  of between about 200 and 300 MHz. 
   Inductor  715  introduces a zero at a zero frequency F LZ  between the roll-off frequency F RO  and the unity gain frequency F UG . In one embodiment, the zero frequency F LZ  is greater than one gigahertz, e.g. about two gigahertz. The value of inductor  715  is selected to flatten the high-frequency gain, in one embodiment providing an AC response of about 3 dB at the 5 GHz maximum operating frequency. As a consequence of resistors  705  and  710  retarding the low-frequency gain and inductor  715  flattening the high-frequency gain of interest, the AC response of combiner circuit  700  varies by less than 10 dB between the roll-off frequency F RO  and the zero frequency F LZ . The resulting relatively flat AC response over the frequency band of interest reduces the data-deterministic jitter. 
     FIG. 9  is a waveform diagram  900  illustrating the complementary output signals on differential output terminals OUT and OUTb of data combiner  700  of  FIG. 7 . In comparison with the similar response of data combiner  200  depicted in  FIG. 6B , there is less variation in the eye pattern of waveform  900  because the flatter AC response produces less data-deterministic jitter. 
   In one embodiment, data combiner  700  is fabricated using a standard 0.18-micron CMOS process in which VSS and VDD are zero and 1.8 volts, respectively. Current source  215  is biased to produce 4.59 mA per side using a pair of PMOS transistors, each with an aspect ratio of 54.0; transistors  230 ,  235 ,  220 , and  225  are NMOS transistors, also having an aspect ratio of 54.0; transistors  240  and  245  are PMOS transistors with an aspect ratio of 13.52; transistors  720  are PMOS transistors with aspect ratios of 40.18; resistors  705  and  710  are 180.52 Ohms each; and inductor  715  is 14.076 nanohenrys. 
   While the present invention has been described in connection with specific embodiments, variations of these embodiments will be obvious to those of ordinary skill in the art. For example, while the above-embodiments serialize two- and eight-bit data presented in parallel, the present invention can be extended to serialize parallel data represented using different numbers of bits. Also, the benefits of leveling the AC response provided on differential output terminals can be provided to other types of differential amplifiers. Moreover, some components are shown directly connected to one another while others are shown connected via intermediate components. In each instance, the method of interconnection establishes some desired electrical communication between two or more circuit nodes, or terminals. Such communication may often be accomplished using a number of circuit configurations, as will be understood by those of skill in the art. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description.