Abstract:
A parallel equalizer for a DS-CDMA UWB system and method thereof are provided. The parallel equalizer includes: a filter block for filtering a training input signal in a ‘training mode’, and filtering the plurality of input signals in parallel in a ‘symbol decision mode’; a symbol decision block for obtaining a symbol error based on a output from the filter block and a training symbol in the ‘training mode’, and estimating a transmission symbol for each of the input signals in the ‘symbol decision mode’, obtaining an error of one among the estimated transmission symbols for a symbol error calculating input signal; and an weight update block for updating a filter tap coefficients of the filter block based on the training input signal or the symbol error calculating input signal and the symbol error and transmitting the updated filter tap coefficients into the filter block.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to a parallel equalizer for a direct sequence-code division multiple access (DS-CDMA) ultra wide-band (UWB) system and a method thereof; and, more particularly, to a parallel equalizer for a DS-CDMA UWB system and method thereof which updates filter tap coefficients based on a weight update block (WUB) and estimates transmission symbols in L filter blocks (FB), different from updating the filter tap coefficients of L WUBs individually in the conventional parallel equalizer to thereby decrease a complexity and a power consumption of the parallel equalizer.  
       DESCRIPTION OF RELATED ART  
       [0002]     A direct sequence-code division multiple access (DS-CDMA) ultra wide-band (UWB) system transmits signals by using an ultra wide-band frequency. Therefore, a serious synchronous error of the signals by a multi-path fading and a phase offset occurred by a multi-path of transmission channel, and a frequency offset occurring between clocks used in a radio frequency (RF) transceiver are generated when the signals are transmitted.  
         [0003]     To solve the serious synchronous error, a module for setting a packet synchronization and a symbol synchronization is designed and a channel estimator and a rake receiver for dealing with a channel variation during data frame transmission period are used for recovering a transmission data in a receiving block.  
         [0004]     However, delay of the multi-path fading is equal to or more than 150 to 200 nsec in a UWB channel environment. Since an inter-symbol interference (ISI) occurred in data transition cannot be removed by only the rake receiver, performance of a DS-CDMA UWB modem receiver is dropped. Therefore, an equalizer should be employed to a receiving unit of the DS-CDMA UWB modem for overcoming the above problems.  
         [0005]     In a data frame structure of the DS-CDMA UWB modem, a normal preamble is allocated with 15 μs. Herein, an allocated duration for converging filter tap coefficients of the equalizer by using a training symbol in order to remove the ISI is between 10 μs and 15 μs after transmitting a first preamble sequence. Since convergence of the equalizer by using the training symbol and processing of high-speed data should be performed within the duration of preamble transmitting in the UWB system, the equalizer of the receiving block is needed to be designed as a parallel processing structure.  
         [0006]     Generally, the filter tap coefficients of a symbol rate linear equalizer (SRLE) performing a parallel processing are adapted by a least mean-square algorithm. The least mean-square algorithm updates the filter tap coefficients in an opposition direction of a noisy error gradient. An adaptation (optimization) of the l th  filter tap coefficients of the equalizer is expressed by the following Eq. 1. 
 
 c   n+1,l    =c   n,l +Δ ff   e   n,l   , l= 0,1,  . . . , L− 1 Eq. 1 
 
         [0007]     Herein, an error rate e n,l  corresponds to Ŝ n−1 -c n,l   T r n,l ; Ŝ n−1     32  S   n−1−d  is an output of the slicer at the n th  symbol period; d denotes a overall delay from the transmitter to the receiver in baud rate interval. Δ ff  is a step size, and the symbol (·) T  is a transpose of (·).  
         [0008]     The real vector of the l th  filter tap coefficients of the equalizer c n,l   T  and the real vector of an l th  input signal of the equalizer r n,l   T  are expressed by the following Eq. 2. 
 
c n,l   T =[c n,l,0  c n,l,1  . . . c n,l,N−1 ]
 
 r   n,l   T =[r n−l  r n−4−l  . . . r n−4 (N−1)−l ] Eq. 2 
 
         [0009]     Herein, N is the number of the filter tap coefficients of the SRLE.  
         [0010]      FIG. 1  is a diagram of a general receiver of DS-CDMA UWB modem.  
         [0011]     The receiver of DS-CDMA UWB modem (hereinafter, which is referred to as DS-CDMA UWB modem receiver) includes an analog/digital converter (ADC)  10 , a correlator  11 , a rake receiver  12 , a parallel equalizer (an L-parallel equalizer)  13  and a viterbi decoder  14 .  
         [0012]     A RF processing block (not shown in  FIG. 1 ) of the DS-CDMA UWB modem receiver receives an RF transmission signal from a transmitter, converts the RF transmission signal into an analog baseband signal and transmits the analog baseband signal to the ADC  10 .  
         [0013]     The ADC  10  receives and converts the analog baseband signal  101  into a digital signal  102  (M digital signals). The correlator  11  receives the M digital signals  102  from the ADC  10 , performs correlation detection operation for the M digital signals and outputs M result signals (complex correlation signal)  103  into the rake receiver  12 .  
         [0014]     The rake receiver  12  receives the M complex correlation signals from the correlator  11  and outputs L real symbol signals  104  into the parallel equalizer  13 . The parallel equalizer  13  receives the L real symbol signals, eliminates the ISI and outputs L symbol decision signals  105 .  
         [0015]     Then, the viterbi decoder  14  receives the L symbol decision signals from the parallel equalizer  13  and obtains an encoding gain. Herein, the viterbi decoder  14  which is a decoder designed in the receiver based on a convolution encoder of the transmitter having L′ outputs signals  106  (M&gt;L&gt;L′).  
         [0016]      FIG. 2  is a detailed diagram illustrating a conventional parallel equalizer and represents the L-parallel equalizer  13  applied to the DS-CDMA UWB modem receiver generally.  
         [0017]     As shown in  FIG. 2 , each equalizer (equalizing block) of the L-parallel equalizer  13  used in the DS-CDMA UWB modem receiver includes a weight update block (WUB)  24 , a delaying block  21 , a filter block (FB)  22  and a symbol decision block  23 .  
         [0018]     The WUB updates the filter tap coefficients by using an input signal of the equalizer and a symbol error extracted in the slicer. The delaying block  21  delays the input signal of the equalizer and obtains N signals used in the FB  22  and the WUB  24 . Herein, the delaying block  21  is presented as separate block, but the delaying block  21  may be included in the FB  22  and the WUB  24 .  
         [0019]     The FB  22  obtains a symbol decision signal by using the updated filter tap coefficients from the WUB  24  and the input signal of the equalizer. The symbol decision block  23  decides a transmission symbol based on a result from the FB  22  or obtains the symbol error.  
         [0020]     Among the L input signals of equalizer outputted from the rake receiver  12 , a first input signal r n    201  is used as a input signal of a first FB; a second input signal r n−1    205  is used as a input signal of a second FB; a L th  input signal r n−(L−1)    207  is used as a input signal of a L th  FB.  
         [0021]     The conventional parallel equalizer is formed by L equalizing blocks having same structure. A first equalizing block will be described as below and L−1 numbers of equalizing blocks are designed as the same as the first equalizing block.  
         [0022]     As shown in  FIG. 2 , the N input values (r n , r n−L , . . . , r n−L(N−1) ) used in the FB  22  and the WUB  24  are generated by passing the input signal of equalizer r n  through N−1 D flip-flops  240  to  242 .  
         [0023]     The FB  22  includes N multiplier  230  to  233  for multiplying the N filter tap coefficients (c n, 0, 0 , c n, 0, 1 , . . . , c n, 0, N−1 ) updated in the WUB  24  and the N input signals (r n , r n−L , . . . , r n−L(N−1) ) outputted from the delaying block  21 , respectively, and adders  221  to  223  for adding results from the multipliers. Then, the adding result is transmitted into the slicer  225  through a bit regulator  224 .  
         [0024]     First, when the parallel equalizer operates in a ‘training mode’, the training symbol S n  is inputted into a subtractor  226  by moving a switch into downside. That is, the training symbol is adopted as a symbol value. Then, the subtractor  226  obtains a symbol error e n, 0  by subtracting the training symbol S n  and a symbol decision signal y n, 0 .  
         [0025]     Meanwhile when the parallel equalizer operates in a ‘symbol decision mode’, a symbol signal S n  from the slicer  225  is inputted into the subtractor  226  by moving a switch into upside. Then, the subtractor  226  obtains a symbol error e n, 0  by subtracting the symbol signal S n  and the symbol decision signal y n, 0 .  
         [0026]     Below, the WUB will be described in detail. The conventional parallel equalizer includes L WUBs having same structure.  
         [0027]     The WUB  24  includes N first multipliers  250  to  253 , N second multipliers  260  to  263 , N D flip-flops  280  to  283 , N adders  270  to  273  and N bit regulators  285  to  288 .  
         [0028]     The N first multipliers  250  to  253  multiply the symbol error e n, 0    229  from the symbol decision block  23  and the N input signals (r n , r n−L , . . . , r n−L(N−1) ), respectively.  
         [0029]     The N second multipliers  260  to  263  multiply the multiplying results of the N first multipliers  250  to  253  and the step size Δ ff  to update the filter tap coefficients in every symbol. The N second multipliers  260  to  263  are embodied as shift operators performing a right or left shifting in practice.  
         [0030]     The N adders  270  to  273  calculate new filter tap coefficients by adding the previous filter tap coefficients stored in D flip-flops  280  to  283  and results from the corresponding second multiplier, respectively. Herein, the D flip-flops  280  to  283  store the result (the previous filter tap coefficients) within one symbol duration for updating the filter tap coefficients continuously. The bit regulators  285  to  288  control bits of the filter tap coefficients.  
         [0031]     When ‘next symbol’ is inputted, the resulting filter tap coefficients are reused for determining a transmission symbol in the FB  22  and updating the filter tap coefficients in WUB  24 .  
         [0032]     Since the conventional parallel equalizer includes the L WUBs for updating the filter tap coefficients in every operating clock and the L FBs for estimating a transmission signal by using the updated filter tap coefficients, the system is complex and high-power consumption.  
         [0033]     Meanwhile, general UWB system uses an ultra-wideband more than 500 MHz. Since application manufactured goods are installed in home inside, mobility is very low. Therefore, because a Doppler frequency spread of UWB channel is near ‘0’ and a coherence time is long, a state of channel during several symbol transmitting durations does not change in the UWB system working several tens to several hundreds Mbps. Moreover, UWB chipset may be embedded in various digital image applications, PC products and digital individual appliance products. A UWB modem chip should be low-power consumption and small-sized by improving a modem receiving block to realize the above.  
         [0034]     That is, low-complexity equalizer is needed for the modem receiving block of a wireless personal area network (WPAN) using wide band frequency like the UWB system and having low channel variation.  
       SUMMARY OF THE INVENTION  
       [0035]     It is, therefore, an object of the present invention to provide a parallel equalizer for a DS-CDMA UWB system and method thereof which updates filter tap coefficients based on a weight update block (WUB) and estimates transmission symbols in L filter blocks (FB), different from updating the filter tap coefficients of L WUBs individually in the conventional parallel equalizer to thereby decrease a complexity and a power consumption of the parallel equalizer.  
         [0036]     In accordance with an aspect of the present invention, there is provided a parallel equalizer for a DS-CDMA UWB system, including: a filter block for filtering a training input signal which is one among a plurality of input signals when the parallel equalizer operates in a ‘training mode’, and filtering the plurality of input signals in parallel when the parallel equalizer operates in a ‘symbol decision mode’; a symbol decision block for obtaining a symbol error based on a output from the filter block and a training symbol in the ‘training mode’, and estimating a transmission symbol for each of the input signals based on outputs from the filter block in the ‘symbol decision mode’, obtaining an error of one among the estimated transmission symbols for a symbol error calculating input signal; and an weight update block for updating a filter tap coefficients of the filter block based on the training input signal or the symbol error calculating input signal and the symbol error obtained in the symbol decision block and transmitting the updated filter tap coefficients into the filter block.  
         [0037]     In accordance with another aspect of the present invention, there is a method for equalizing a signal in parallel for a DS-CDMA UWB system, including the steps of: a) filtering an input signal (a training input signal) among a plurality of input signals and obtaining a first symbol error based on the filtered training input signal and a predetermined training symbol; b) updating filter tap coefficients used step a) based on the first symbol error and the training input signal and going on step a) until the filter tap coefficients are converged; c) setting the final updated filter tap coefficients at step b) when the filter tap coefficients are converged as an initial filter tap coefficients, filtering for the plurality input signals in parallel and estimating transmission symbols for the filtered input signals; d) obtaining a second symbol error for a second input signal (a symbol error calculating input signal) among the plurality of the input signals estimated in step c) and going on step a) until transmission of the data frame is completed; and e) updating the filter tap coefficients used filtering in step c) based on the second symbol error and the symbol error calculating input signal and going on step d).  
         [0038]     The present invention is related to a parallel equalizer for a DS-CDMA UWB system and method thereof. That is, a low complexity equalizer is provided suitable for a modem receiver of a wireless personal area network (WPAN) such as a UWB system using wide band frequency and having low channel variation.  
         [0039]     In present invention, when L-parallel equalizer is designed, the filter tap coefficients are updated based on one WUB and transmission symbol is estimated by transmitting the filter tap coefficients into the L FBs different from updating the filter tap coefficients in L WUBs in every time in order to obtain the filter tap coefficients.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0040]     The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:  
         [0041]      FIG. 1  is a diagram of a general receiver of DS-CDMA UWB modem;  
         [0042]      FIG. 2  is a detailed diagram illustrating a conventional parallel equalizer for the DS-CDMA UWB modem receiver;  
         [0043]      FIG. 3  is a diagram showing a parallel equalizer for the DS-CDMA UWB modem receiver in accordance with an embodiment of the present invention; and  
         [0044]      FIG. 4  is a flowchart illustrating a method of optimizing filter tap coefficients and deciding a transmission symbol in accordance with an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0045]     The above-described objects, characteristics, and advantages of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, which is set forth hereinafter. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided to fully convey the concept of the invention to those skilled in the art. Also, in the description of the present invention, descriptions of related and published skills shall be omitted when they are deemed to induce unclearness in the purpose of the inventive description.  
         [0046]      FIG. 3  is a diagram showing a parallel equalizer for the DS-CDMA UWB system in accordance with an embodiment of the present invention. That is,  FIG. 3  represents the parallel equalizer suitable for DS-CDMA UWB modem receiver having improved complexity.  
         [0047]     As shown in  FIG. 3 , the parallel equalizer for the DS-CDMA UWB modem receiver includes a weight update block (WUB)  34 , L delaying blocks  31 , L filter blocks (FB)  32 , and L symbol decision blocks  33 .  
         [0048]     The WUB updates the filter tap coefficients based on an input signal of the parallel equalizer inputted from a rake receiver  12  and a symbol error extracted in a first symbol decision block  33 . The delaying block  31  delays the input signal of the parallel equalizer and obtains N signals used in the FB  32  and the WUB. Herein, the delaying block  31  is illustrated as a separate block, but the delaying block  31  may be included in the FB  32  and the WUB  34 .  
         [0049]     The L FBs  32  obtain L symbol decision signals by using the updated filter tap coefficients from the WUB  34  and the L input signals of the parallel equalizer. The L symbol decision blocks  33  decide transmission symbols based on results from the L FBs  32  or obtain the symbol error.  
         [0050]     Among the L input signals of parallel equalizer outputted from the rake receiver  12 , a first input signal r n    301  is used as an input signal of a first FB; a second input signal r n−1    305  is used as an input signal of a second FB; a L th  input signal r n−(L−1)    307  is used as an input signal of a L th  FB.  
         [0051]     When the parallel equalizer operates in a ‘training mode’, only the first FB is operated among L FBs and when the parallel equalizer operates in a ‘symbol decision mode’, the L FBs are all operated.  
         [0052]     The parallel equalizer includes L equalizing blocks having the same structure. A first equalizing block will be described as below and L−1 numbers of equalizing blocks are designed as the same as the first equalizing block.  
         [0053]     As shown in  FIG. 3 , the N input values (r n , r n−L , . . . , r n−L(N−1) ) used in the FB  32  and the WUB  34  are generated by passing the input signal r n  of the parallel equalizer through N−1 D flip-flops  340  to  342 . When the parallel equalizer operates in the ‘training mode’, only the first FB is operated. Herein, r n  inputted into the first FB in the ‘training mode’ is defined as a ‘training input signal’. Meanwhile, although the L FBs are operated when the parallel equalizer operates in the ‘symbol decision mode’, only the first FB participates to extract a symbol error used for updating the filter tap coefficients. Therefore, r n  inputted into the first FB in the ‘symbol decision mode’ is defined as a ‘symbol error calculation input signal’.  
         [0054]     The FB  32  includes N multiplier  330  to  333  for multiplying the N filter tap coefficients (c n, 0, 0 , c n, 0 , 1 , . . . , c n, 0, N−1 ) updated in the WUB  34  and the N input signals (r n , r n−L , . . . , r n−L(N−1) ) outputted from the delaying block  31 , respectively, and adders  321  to  323  for adding results from the multipliers. Then, the adding result is transmitted into the slicer  325  through a bit regulator  324 .  
         [0055]     In the parallel equalizer in accordance with the present invention, a first symbol decision block  33  obtains a symbol error e n, 0    329 , transmits the symbol error into the WUB  34  or decides a transmission symbol S n    395 . And, L−1 symbol decision blocks are operated in ‘symbol decision block’, decides transmission symbols  396  to  398  and do not obtain the symbol error.  
         [0056]     First, when the parallel equalizer operates in the ‘training mode’, the training symbol S n    399  is inputted into a subtractor  326  by moving a switch into downside. That is, the training symbol is adopted as symbol signal. Then, the subtractor  326  obtains a symbol error e n, 0    329  by subtracting the training symbol S n  and symbol decision signal y n, 0    328 .  
         [0057]     Meanwhile when the parallel equalizer operates in the ‘symbol decision mode’, a symbol signal S n  from the slicer  325  is inputted into the subtractor  326  by moving a switch into upside. Then, the subtractor  326  obtains a symbol error e n, 0    329  by subtracting the symbol signal S n    395  and symbol decision signal y n, 0    328 .  
         [0058]     Below, the WUB will be described in detail. The parallel equalizer in accordance with the present invention includes one WUB  34  for improving complexity different from the conventional parallel equalizer.  
         [0059]     The WUB  34  includes N first multipliers  350  to  353 , N second multipliers  360  to  363 , N D flip-flops  380  to  383 , N adders  370  to  373  and N bit regulators  385  to  388 . Each element will be described below.  
         [0060]     The N first multipliers  350  to  353  multiply the symbol error e n, 0    329  from the symbol decision block  33  and the N input signals (r n , r n−L , . . . , r n−L(N−1) )  301  to  304 , respectively.  
         [0061]     The N second multipliers  360  to  363  multiply the multiplying results of the N first multipliers  350  to  353  and the step size Δ ff  for updating the filter tap coefficients in every symbol. The N second multipliers  360  to  363  shown in  FIG. 3  are embodied as shift operators performing a right or left shifting in practice.  
         [0062]     The N adders  370  to  373  calculate new filter tap coefficients by adding the previous filter tap coefficients stored in D flip-flops  380  to  383  and result from the corresponding second multiplier, respectively. Herein, the D flip-flops  380  to  383  store the result (the previous filter tap coefficients) within one symbol duration to update the filter tap coefficients continuously. The bit regulators  385  to  388  control bits of the filter tap coefficients.  
         [0063]     When ‘next symbol’ is inputted, the resulting filter tap coefficients are reused for determining a transmission symbol in the FB  32  and updating the filter tap coefficients in WUB  34 .  
         [0064]      FIG. 4  is a flowchart illustrating a method of optimizing the filter tap coefficients and deciding a transmission symbol in accordance with an embodiment of the present invention.  FIG. 4  illustrates adaptation of the filter tap coefficients of the parallel equalizer suitable for DS-CDMA UWB modem receiver and decision of the transmission symbols from the transmitter. That is, one WUB and L FBs are used for determining the transmission symbols in the parallel equalizer of present invention.  
         [0065]     First, when the parallel equalizer operates in the ‘training mode’ within transmission of a preamble period, training symbol is used at step S 400 . That is, the training symbol S n    399  is inputted into a subtractor  326  by moving a switch  327  located in the first symbol decision block  33  into downside in the ‘training mode’.  
         [0066]     In the ‘training mode’, the filter tap coefficients are adapted based on the WUB  34  and a first FB, and L−1 FBs, i.e., a second FB to L th  FB do not operated at step S 401 . After a first decision block  33  adapts the training symbol S n    399 , a symbol error e n, 0    329  is extracted from the training symbol and a symbol decision signal y n, 0    328  and transmitted into the WUB  34  at step S 402 .  
         [0067]     Then, the WUB  34  updates the filter tap coefficients based on the symbol error  329 , input signals of equalizer  301  to  304  and a step size  365  to  368  and optimizes the number of bits by using the bit regulators  385  to  388 . Then, the bits optimized filter tap coefficients are transmitted into the first FB at step S 403 .  
         [0068]     Then, it is determined that whether the filter tap coefficients of the WUB are sufficiently converged or not at step S 410 . When the filter tap coefficients are converged sufficiently, parallel equalizer is operated in the ‘symbol decision mode’ at step S 420 . Otherwise, when the filter tap coefficients are not converged sufficiently, updating step of the filter tap coefficients at step S 403  is repeated based on an extracted symbol error transmitted into the WUB at step S 402 .  
         [0069]     Herein, in conformation methods that whether the filter tap coefficients are converged or not, there is a method that comparing a magnitude of the symbol error obtained from the symbol decision bock and a magnitude of a predetermined threshold value. Also, after a convergence time (K) of the filter tap coefficients are calculated by using a simulation and it is conformed that an adaptation time of the filter tap coefficients is over the convergence time (K).  
         [0070]     In present invention, the filter tap coefficients of the WUB are assumed to be converged sufficiently within transmission of a preamble duration. Moreover, the parallel equalizer is assumed to be operated in the ‘training mode’ during transmission of the preamble and in the ‘symbol decision mode’ during transmission of a data frame. In present invention, the conformation method whether equalizer convergent or not is decided as comparing the calculated convergence time and convergence time of the filter tap coefficients. Moreover, entire structure of the parallel equalizer is designed based on transmission of the preamble varying in accordance with the convergence time of the filter tap coefficients. Therefore, final updating filter tap coefficients in the ‘training mode’ are used as an initial filter tap coefficients in the ‘symbol decision mode’.  
         [0071]     Meanwhile, when the filter tap coefficients are converged, i.e., when the data frame is transmitted into the parallel equalizer, the parallel equalizer is operated in the ‘symbol decision mode’ adopting symbol decision value  395  from the symbol decision block  33  by switching the switch  327  at step S 420 . Then, one WUB and L FBs are operated at step S 421 . A first symbol decision block extracts the symbol error  329  and transmits the symbol error into the WUB  34  at step S 422 .  
         [0072]     Then, L symbol decision blocks determine the transmission symbol based on the symbol decision signal transmitted from the L parallel FBs, respectively. The determined transmission symbol is transmitted into the viterbi decoder  14  at step S 423 .  
         [0073]     Then, the WUB  34  updates the filter tap coefficients based on the symbol error  329 , input signals of the equalizer  301  to  304  and a step size  365  to  368  and optimizes the number of bits by using the bit regulators  385  to  388 . Then, the bits optimized filter tap coefficients are transmitted into the L FBs at step S 424 .  
         [0074]     Next, it is determined that whether transmission of a data frame is completed or not at step S 430 . When the data frame transmission is completed, the equalizing operation comes to end. Otherwise, when transmission of the data frame is not completed, steps S 422  to S 424  are repeated until transmission of the data frame is completed.  
         [0075]     As described above, the parallel equalizer according to the present invention can reduce a hardware complexity of 40% more than the conventional parallel equalizer. Also, the power consumption of the parallel equalizer can be reduced remarkably.  
         [0076]     That is, the parallel equalizer according to the present invention includes one WUB and L FBs different from the conventional equalizer having L WUBs and L FBs. In the preamble transmitting duration, the filter tap coefficients of the parallel equalizer are converged based on the training symbol and operating one WUB and one FB. In the data frame transmitting duration, the parallel equalizer operated in the ‘symbol decision mode’ and extracts transmission symbol from the transmitter by operating one WUB and L FB. Therefore, the complexity of the receiving system can be reduced so that the power consumption can be reduced remarkably.  
         [0077]     Referring to Table 1, comparing complexity of hardware between the parallel equalizer of present invention and the conventional parallel equalizer will be described in detail.  
                                                                                       TABLE 1                                       Number of Multiplier(s)   Number of adder(s)                        Calculating           Calculating                   symbol           symbol           FB   WUB   error   FB   WUB   error                        Conventional   L × N   L × N   —   L(N − 1)   L × N   L       parallel       equalizer       Parallel   L × N   N   —   L(N − 1)   N   1       equalizer       of present       invention                  
 
         [0078]     Generally, bits number of multipliers used in WUB of the parallel equalizer is more than bits number of multipliers used in FB. The parallel equalizer of present invention reduces complexity 40% than the conventional parallel equalizer. Moreover, the FB and the symbol decision block are operated when the parallel equalizer in the ‘training mode’, power consumption can be reduced remarkably.  
         [0079]     In a word, the present invention is the parallel equalizer suitable for the DS-CDMA UWB modem receiver. Referring to  FIG. 4 , the parallel equalizer is operated in the ‘training mode’ based on the training symbol during transmission of the preamble, the parallel equalizer determines the transmission symbol in the ‘symbol decision mode’ during transmission of the data frame.  
         [0080]     The methods in accordance with the embodiments of the present invention can be realized as programs and stored in a computer-readable recording medium that can execute the programs. Examples of the computer-readable recording medium include CD-ROM, RAM, ROM, floppy disks, hard disks, magneto-optical disks and the like.  
         [0081]     The present application contains subject matter related to Korean patent application Nos. 2005-0121108 and 2006-0059468, filed with the Korean Intellectual Property Office on Dec. 9, 2005, and Jun. 29, 2006, respectively, the entire contents of which is incorporated herein by reference.  
         [0082]     While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.