Abstract:
A split boost converter is disclosed herein, suitable for both single phase and three phase AC input applications. It provides two equal but unparallelable output voltages stored on two separate independent output capacitors. The implementation supports two modes of operation in which two power switches are operated simultaneously or alternately. Each mode maintains the advantage of a reduced boost inductor size. In the first mode the charging of the capacitors in parallel circuits and their discharge in a series connection substantially reduces ripple current in the inductor permitting the user of a smaller inductor. In the second mode the capacitors are charged and discharged in differing time intervals achieving a similar result. The circuit is operable with input voltages which must exceed the voltages of its two output capacitors.

Description:
FIELD OF THE INVENTION 
     This invention relates to boost convertors with multiple outputs that are used as a front-end power processing stage in off-line rectifiers. 
     BACKGROUND OF THE INVENTION 
     Boost converters are commonly used in high power factor applications as line conditioners. The boost stage processes the AC input and develops a DC output voltage, typically 400 V or 800 V. Boost converters are typically the topology of choice for providing a high output voltage (i.e., 400 V or 800 V) from substantially lower input DC voltages derived from sinusoidal input voltages. In applications with high AC input voltage (i.e., 320 to 480 VAC) where an intermediate DC bus voltage of 700 to 800 V is necessary, a soft-switched boost is often used to maintain the overall efficiency of the rectifier. For lower AC input voltage applications, a simple snubber to slow down the turn-off of the boost diode is all that is necessary to obtain a boost efficiency of 96-98%. In recent years, several new topologies have been proposed in which the semiconductor switching losses arc minimized by adding an auxiliary active circuit. The addition of the auxiliary circuit is an elegant solution but it results in increased cost and complexity. 
     A recent paper by Y. Jiang and F. C. Lee, entitled &#34;Three-Level Boost Converter for Application in Single Phase Power Factor Correction&#34;, Virginia Power Electronics Center (VPEC) Power Electronics Seminar Proceedings, 1994, Virginia Polytechnic Institute and State University, Blacksburg, Va., pp. 127-133 suggests a configuration for a boost stage that accommodates semiconductor devices rated for approximately half the normal output voltage, (i.e., V 0  /2) for use in high voltage, single-phase applications. Jiang and Lee&#39;s circuit, which they call a three-level boost, provides two unparallelable but equal output voltages. By reducing the maximum voltage stresses across the semiconductor devices, a zero-voltage switching topology becomes less important to maintain high efficiency. In addition to reducing the voltage stresses across all semiconductor devices to half of the normal output bus voltage, the three-level boost also decreases the size of the boost inductor without compromising EMI performance. 
     SUMMARY OF THE INVENTION 
     A split boost converter is disclosed herein, suitable for both single phase and three phase AC input applications including variable DC input voltage situations. It provides two equal but unparallelable output voltages stored on two separate, independent output capacitors. Efficiency is enhanced by a circuit topology which limits the lowest operative input voltage to a value not less than the voltage level of each of the two output voltages. The implementation supports two modes of operation. In one of the two modes the two power switches are operated simultaneously to optimize the use of available silicon devices while maintaining the advantage of a reduced boost inductor size. The charging of the capacitors in parallel circuits and their discharge in a series connection substantially reduces ripple current in the inductor permitting the use of a smaller sized inductor. In the other operational mode the capacitors are charged and discharged in differing time intervals achieving a similar reduction of inductor size. The circuit, in both modes, is operable with input voltages which must exceed the individual voltages of its two output capacitors. 
     FETs are used as the active switches in the below illustrative embodiment. However, the circuit topology is not limited to these types of semiconductor switches. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a schematic of a boost converter embodying the principles of the invention and having a three phase, six diode bridge; 
     FIGS. 2 and 3 are schematics of two stages of a first mode of operation of the circuit of FIG. 1; 
     FIG. 4 discloses waveforms of the boost converter of FIG. 1 operating in the first mode; 
     FIGS. 5 through 8 are schematics of stages of a second mode of operation of the circuit of FIG. 1; 
     FIG. 9 discloses waveforms of the boost converter of FIG. 1 operating in the second mode; 
     FIG. 10 is a schematic of the circuit topology for assisting in describing equalizing of the capacitor voltages; 
     FIG. 11 is a schematic of a multiple level split boost converter with three output capacitors, three switches, two diodes; and 
     FIGS. 12 and 13 are schematics of two stages for describing a mode of operation of the circuit of FIG. 11. 
    
    
     DETAILED DESCRIPTION 
     An implementation of the proposed boost stage is shown in FIG. 1. Inductor L F  is the boost inductor, capacitors C 1  and C 2  are the output capacitors, Q 1  and Q 2  are the active switches, and D 1  is the passive switch, i.e., the boost diode. Capacitors C  1  and C  2  are relatively large and the voltages across them are essentially constant during one switching cycle. Since the two output capacitors are not in series, the proposed boost stage supplies two independent loads as depicted in FIG. 1 by resistors R L1  and R L2 . Control circuitry for driving the power switches of converters such as these is well known and hence is not described herein. 
     This converter can operate in each of two different modes. In mode 1, switches Q 1  and Q 2  are turned on and off at the same time, i.e., synchronously. The two topological stages this converter goes through in one switching cycle are shown in the schematics of FIGS. 2 and 3, and the ideal waveforms representing this operation of the converter are shown in FIG. 4. 
     In this mode 1, as shown in the FIG. 2, when the two switches Q 1  and Q2 are simultaneously turned-on at time t 0 , the two capacitors C 1  and C 2  are connected in parallel, since the diode D 1  is non conducting. The current through the boost inductor L F  increases at a linear rate approximately equal to (V IN  -V 0  /2)/L F . At the same time t 0 , energy is stored in the output capacitors C 1  and C 2  and/or transferred to the load, as long as the condition. V 0  /2&lt;V IN  &lt;V 0  holds. It is the meeting of this last condition that makes this topology well suited for a three-phase application where a three-phase six-diode bridge is followed by a boost stage. Similar to the three-level boost proposed by Jiang and Lee, the tipple current through the inductor is reduced considerably relative to traditional boost stages by allowing the boost inductor to build up current through the series combination of the input voltage source and the parallel combination of the output capacitors. At time t 1  both active switches Q 1  and Q 2  are turned off and inductor L F  is reset through diode D 1  and the now series combination of capacitors C 1  and C  2  as shown in FIG. 3. It is important to note that in this mode 1 power is transferred to the load from the input at all times, reducing the rms current through the two output capacitors C 1  and C 2 . This is an important feature since capacitors are generally rated for supporting a maximum rms current. The circuit waveforms are shown in the FIG. 4 and include the inductor current I LF  and the two switching device currents I Q1  and I Q2  a and their voltage drops V Q1  and V Q2 . The diode current I D1  and its voltage drop V D1  is also shown. The voltage drops V GQ1  and V GQ2  represent the gate-to-source voltage applied to the FET switches Q 1  and Q 2 . 
     Just as switches Q 1  and Q 2  can be operated synchronously with simultaneous identical conduction states, they can also be turned on and off in an alternating fashion, defined herein as mode 2. The topological stages this converter goes through in one switching cycle are shown in the FIGS. 5 through 8 and the ideal waveforms representing the operating of the converter are shown in FIG. 9. The operation in this mode is similar to that described for the converter operating in mode 1. The main differences is that in mode 2, the effective frequency of the boost inductor current ripple is doubled and power is not transferred continuously from the input to the output, as it is in mode 1. &#34;In the second mode the two capacitors C  1 , C 2  are alternately connected to the same input current while they discharge into one another while connected in series&#34;. 
     In FIG. 5, Q 1  is conducting while Q 2  and D  1  are open or non conducting. In this state the capacitor C  1  is being charged by current I IN  through the inductor L F . 
     The subsequent connection stage in FIG. 6 has both switches Q 1  and Q 2  biased non conducting while the diode D 1  is conducting. In this stage the current I IN  charges the capacitor C 2 . 
     In the stage shown in FIG. 7 the switch Q 2  is biased conducting with switch Q 1  and diode D 1  non conducting. The input current I IN  continues to charge the capacitor C 2 . 
     The next stage, shown in FIG. 8 has both switches Q 1  and Q 2  non conducting and both the capacitors C 2  and C 2  are charged in series by I IN  through the diode D 1 . 
     Even though it may appear from the description above that two independent voltage control loops are necessary to maintain a voltage of V 0  /2 across both output capacitors, it can be seen that, in mode 1, by controlling the voltage across one of the output capacitors, the voltage across the second output is also controlled. This feature is inherent in the operation of the circuit of mode 1 and is a further advantage over the three level boost. It results from the fact that when both switches are turned on, as in mode 1, the two output capacitors are effectively in parallel, allowing for the capacitor with the higher output voltage to discharge into the other output capacitor, as shown in FIG. 10. Therefore, two perfectly matched loads are not necessary to insure proper balanced voltage operation. Computer simulations indicate that an imbalance of only a couple of volts will result between the two output capacitors for a 50% load imbalance. 
     The split-boost concept can be generalized to implement a multi-level boost stage by providing additional output capacitors, each accompanied by a switch and diode. A multi-level boost stage that can control the magnitude of the input current tipple depending on the number of switches that are open/closed at a given time can be implemented. FIG. 11 shows a split boost using three output capacitors, C 1 , C 2  and C 3  ; three switches, Q 1 , Q 2  and Q 3 , and two diodes, D 1  and D 2 . In this converter the magnitude of the current ripple given an input voltage can be one of two possible alternatives depending on whether one switch is closed at a time or a combination of two switches, as shown in FIGS. 12 and 13. Having the ability to control the slope of the input current can be used to shape the input current to a desired reference with better precision, or to reduce the size of the input inductor. It is this second feature that is often more important, since in many high power supplies the size of the magnetics dominates the overall design. 
     The three output split boost topology, particularly when operating in mode 1, has an intrinsic efficiency advantage compared to a traditional boost, both in FET conduction and in FET switching losses. In addition, the boost diode conduction and switching losses are also reduced because the required boost diode can have a lower voltage rating. 
     The mode illustrated in FIG. 12 allows for independent conduction of the switches Q 2  and Q 3  and the simultaneous conduction of switches Q 1 , Q 2  and Q 3 . The mode of FIG. 13 allows for simultaneous conduction of switches Q 1  and Q 2  and of Q 1  and Q 3 . 
     To demonstrate the FET switching loss improvement in mode one, the output capacitance C 0SS25  for a typical FET at 25 V drain to source can be approximated by the equation: 
     
         C.sub.0SS25 =0.2(V.sub.b /R.sub.ds)10.sup.-12 
    
     where V b  is the FET drain-to-source voltage rating, and R ds  is the FET on-resistance at 25° C. In a traditional boost the power loss P due to repetitively discharging the FET output capacitance can be represented by 
     
         P=(0.67V.sub.b V.sub.ds.sup.1.5 f.sub.s /R.sub.ds)10.sup.-12 
    
     where V ds  is the drain-to-source voltage of the FET at the time of switching, and f s  is the switching frequency. 
     The equivalent loss for the split beast can be calculated assuming the same FET silicon area is used in both circuits. Since the split boost requires only half the voltage rating for each FET, the total FET on-resistance is reduced by a factor of about four. Since two FETs are required in the split boost, each FET has about half the on-resistance of the equivalent traditional boost. The FET output capacitance is scaled from the equation for C 0SS25 , above. Completing the analysis shows that the resulting total switching losses for discharging FET output capacitances for the split boost are about 70% of those for the traditional boost. 
     The FET conduction losses for the split boost also compare favorably with those of a traditional boost converter. For a traditional boost with an input voltage of V IN  and an output voltage V 0 , the required duty cycle D is 
     
         D=(V.sub.0 -V.sub.IN)V.sub.0. 
    
     The FET losses P b due to conduction for an output current I  0  are 
     
         P.sub.b =D[I.sub.0 /(1-D)].sup.2 R.sub.ds. 
    
     where R ds  is the FET on-resistance. After substitution and simplification this becomes 
     
         P.sub.b =(V.sub.0 -V.sub.IN)I.sub.0.sup.2 V.sub.0 (R.sub.ds /V.sub.IN.sup.2). 
    
     For the split boost, assuming each output capacitor is charged to V o  /2, the duty cycle D is 
     
         D=2(V.sub.0 -V.sub.IN)/V.sub.0. 
    
     The total FET conduction losses P s  for the split boost, with each FET having an on-resistance of R ds  /2 to maintain equal silicon area, are 
     
         P.sub.s =2D[I.sub.0 /(2-D)].sup.2 R.sub.ds /2. 
    
     After substitution and simplification this becomes 
     
         P.sub.s =0.5(V.sub.0 -V.sub.IN)I.sub.0.sup.2 V.sub.0 (R.sub.ds /V.sub.IN.sup.2). 
    
     which is half the expression for the traditional boost. Thus the ratio of FET conduction losses of the split boost compared to the traditional boost for any input voltage V IN  where V o  /2&lt;V IN  &lt;V 0  is 0.5 for the same total FET silicon area. The reduced switching and conductor losses demonstrate the advantage of the split boost when the input voltage range can be limited as described.