Abstract:
A RAKE receiver for receiving a data signal transmitted from a transmitter in a spread spectrum communication system includes a symbol combiner having an adder for adding Walsh index output values, sequentially generated from a correlator using a fast Walsh transform algorithm according to N Walsh code sequences, to a value generated from a last stage of an N-stage shift register, and having the N-stage shift register for shifting an accumulated value of an output of a RAKE receiver corresponding to each index for a Walsh symbol generated from the adder each time a rake is assigned to each finger. The RAKE receiver also includes a first decision logic unit for determining a maximum value by sequentially sorting an output of the symbol combiner and generating a Walsh index corresponding to the determined maximum value as a code word; and a second decision logic unit for sorting and subtracting the output of the symbol combiner according to a state of each bit of a corresponding index and generating a probability value for the code word.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a code division multiple access (CDMA) communication technique used in a cellular radio telephone communication system and, more particularly, to a RAKE receiver for correlating a received signal sample with a despreading code sequence to determine a received data sequence. 
     2. Description of the Related Art 
     In a spread spectrum system, if a spread spectrum signal passes through a multipath fading channel, a received signal appears in a form resulting from adding components of the signal traveling over multiple paths, each having a different amplitude and phase relative to the other components of the signal. With respect to power efficiency, it is not preferable, in this case, to receive only the one main path signal having the strongest power, since power components of the other multipath signals are lost. 
     In a RAKE receiver, a plurality of receivers arranged in a parallel fashion are used, as shown in FIG. 1, to unitedly perform demodulation without losing the power of components of the multipath signals. Signals output from the receivers are combined through a combiner  16 . FIG. 1 is a conceptual diagram described in the book “SYNCHRONOUS DIGITAL COMMUNICATION”, pp.353-354, Jul. 20, 1995 by KYOHAKSA, Inc. The time interval between multipath receivers is variable, and the multipath power component is demodulated with a delay time τ i  through a tapped delay line (TDL)  10 , despreader  12 , and demodulator  14 . The delay time τ i  is dynamically adjusted by a control circuit (not shown). Such a construction maximizes the SNR (Signal-to-Noise Ratio) of the signal output from the RAKE receiver. 
     In a RAKE receiver, a rake is a logical unit including, for example, a transformer, combiner, etc. In order to receive the signals having respectively different path delays in the receiver, the rake performs its operation in the despreader process by setting the delay offset of the sample signals input to a correlator (despreader) to different delay values. A rake can be classified as either a finger or a searcher. A finger is a receipt rake for receiving and combining a plurality of multipath fading signals, and a searcher is a receipt rake for searching the signals&#39; positions on the time base for the multipath fading signals. 
     Although the RAKE receiver is very good at efficiently using the signal power, there is a limit to the number of parallel circuits which can be employed, since many additional hardware circuits are required. The RAKE receiver is based on the principle that if the spectrum width of a signal at a frequency selective fading channel is greater than a delay spread value, it is possible to classify the signal components into independently faded components according to several spectrums. If the number of parallel hardware circuits is greater than the number of actual paths of the signal, the performance of the RAKE receiver is degraded. If the power strength of the signal components traveling on paths between the actual paths are similar to or equal to each other, then the RAKE receiver exhibits maximum performance. 
     Meanwhile, U.S. Pat. No. 5,237,586, issued on Aug. 17, 1993, entitled “RAKE RECEIVER WITH SELECTIVE RAY COMBINING”, which is incorporated by reference herein, describes a RAKE receiver including multipliers for multiplying outputs of a fast Walsh transformer by a weight, accumulators for accumulating outputs of the multipliers and a decision device for detecting a received code word based on the outputs of the accumulators. In operation, a descrambler descrambles (or despreads) a received sample. A single correlator calculates result values corresponding to each Walsh index by using a FWT (Fast Walsh Transform). The multipliers multiply the result values by complex weights, and the accumulators accumulate the outputs of the multipliers. The accumulated values are supplied to the decision device. The decision device sequentially sorts the accumulated values and determines the Walsh index having the maximum value as the received code word. 
     However, since the RAKE receiver disclosed in the aforementioned U.S. Pat. No. 5,237,586 uses an additional accumulator with respect to each Walsh index, many hardware circuits are needed. Also, since the decision device generates only the Walsh index having the maximum value, the above-described RAKE receiver leaves much to be desired in terms of search performance, where a search is an operation for determining a signal component, that is, a pseudo noise phase component, to be demodulated by demodulator fingers within the RAKE receiver. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the invention to provide a RAKE receiver for reducing the amount of needed of hardware without deteriorating processing performance. 
     It is another object of the invention to provide a RAKE receiver for reducing the amount of hardware and improving search performance without deteriorating processing performance. 
     It is still another object of the invention to provide a method for operating a RAKE receiver which results in reducing the amount of hardware needed in the RAKE receiver without deteriorating processing performance. 
     It is yet another object of the invention to provide a method for operating a RAKE receiver with a reduced amount of hardware while improving search performance without deteriorating processing performance. 
     In one aspect of the invention, a RAKE receiver for receiving a data signal transmitted from a transmitter in a spread spectrum communication system includes: a symbol combiner having an adder for adding output values of Walsh indexes which are sequentially generated from a correlator using a fast Walsh transform algorithm according to N Walsh code sequences, to a value generated from a last stage of an N-stage shift register, and having the N-stage shift register for shifting an accumulated value of an output of the RAKE receiver corresponding to each index of a Walsh symbol generated from the adder each time a rake is assigned to each finger; a first decision logic unit for determining a maximum value by sequentially sorting an output of the symbol combiner and generating a Walsh index corresponding to the determined maximum value as a code word; and a second decision logic unit for sorting and subtracting the output of the symbol combiner according to a state of each bit of a corresponding index and generating a probability value of the code word. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The objects discussed above and other objects, features and advantages of the invention will be more clearly understood from the following detailed description when read with the attached drawings, in which: 
     FIG. 1 is a conceptual diagram of a conventional RAKE receiver; 
     FIG. 2 is a functional block diagram of a RAKE receiver in accordance with the present invention; 
     FIG. 3A is a table showing size values corresponding to eight (8) Walsh indexes; and 
     FIG. 3B is a diagram for explaining the operation of an embodiment of the soft-decision logic unit shown in FIG.  2 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention improves on a RAKE receiver and a symbol combiner thereof, used to cope with signal distortion caused by a signal traveling over multiple paths in a radio environment. The RAKE receiver compensates for different arrival delay times when information sent from a transmitter arrives at a receiver via different paths due to various causes such as weather, terrain, etc. To this end, the RAKE receiver receives not only a signal having the highest strength but it also receives various other signals traveling along different paths and thereby having different delay times. The RAKE receiver adds these signals to each other, thereby raising receiving sensitivity. 
     FIG. 2 is a functional block diagram of a RAKE receiver according to the present invention. In FIG. 2, a radio frequency (RF) receiver  31 , an in-phase (I) sample buffer  32   a,  a quadrature (Q) sample buffer  32   b,  a multiplexer  33 , a descrambler  34 , a single correlator  35 , complex multipliers  36 - 1  to  36 -N have the same structure as the corresponding blocks shown in FIG. 11 of U.S. Pat. No. 5,237,586 discussed above, and they perform similar operations. That is, a composite signal is received and sampled by the RF receiver  31 , thereby generating I and Q samples. The I and Q samples are buffered in the I and Q buffers  32   a  and  32   b,  respectively. If a regular RAKE approach is used, the multiplexer  33  selects ranges of samples which need not correspond to different I and Q components. If a limited RAKE approach is used, the multiplexer  33  selects ranges of I and Q samples. In both cases, the selected sample ranges are independent of each other. The descrambler  34  eliminates a scrambling code from the samples either by inverting or not inverting each sample, depending on the bit polarity of the scrambling code. The samples are transmitted in parallel to the single correlator  35 . The single correlator  35  simultaneously correlates the samples with several known code sequences using an FWT algorithm. The correlation results are multiplied by complex weights in the multipliers  36 - 1  to  36 -N. In the RAKE receiver shown in FIG. 11 of U.S. Pat. No. 5,237,586, accumulators are connected to the multipliers  36 - 1  to  36 -N and a decision device is connected to the accumulators. 
     In a preferred embodiment of the present invention, since the correlator  35  uses the FWT algorithm of N Walsh code sequences (Walsh-Hadamard=N), N outputs of the correlator  35  correspond to N Walsh indexes. For example, if the Walsh-Hadamard is 8, there are 8 Walsh indexes. 
     Unlike the RAKE receiver of U.S. Pat. No. 5,237,586, the RAKE receiver according to the present invention has a symbol combiner  40 , a hard-decision logic unit  48  and a soft-decision logic unit  50 , which are connected at a point in the signal flow beyond multipliers  36 - 1  to  36 -N. The symbol combiner  40  includes an adder  42 , a saturation logic unit  44 , and a shift register  46  consisting of N registers, and combines received symbols with one another. The adder  42  adds values output from the multipliers  36 - 1  to  36 -N to a value generated from the N-th register REG N of shift register  46 . The saturation logic unit  44  saturates an output value of the adder  42  so as not to exceed a preset maximum value. An output of the saturation logic unit  44  is applied to the first register REG  1  of the shift register  46 . Each of the registers REG  1  to REG N of the shift register  46  includes the accumulated value of the RAKE receiver output corresponding to each index of a Walsh symbol. 
     The hard-decision logic unit  48  and the soft-decision logic unit  50  are connected to an output of the first register REG  1  of shift register  46 . The hard-decision logic unit  48  determines a maximum value by sequentially sorting the output of the first register REG  1  of shift register  46  within the symbol combiner  40 , and generates the Walsh index corresponding to the determined maximum value as a code word. The hard-decision logic unit  48  includes a comparison and storage unit  60 , a maximum value register  62  and an index register  64 . 
     The soft-decision logic unit  50  sorts and subtracts the output of the first register REG  1  of shift register  46  within the symbol combiner  40  according to a state of each bit of a corresponding index, and generates a probability value for the code word. The soft-decision logic unit  50  has m (=log 2 N) decision logic units  50 - 1  to  50 -m, m being the number of bits constituting each Walsh index. Each of the decision logic units  50 - 1  to  50 -m includes first and second comparison and storage units  100  and  104 , first and second registers  102  and  106 , and a subtracter  108 . The first comparison and storage unit  100  determines a maximum value by sequentially sorting a corresponding output value according to binary logic “0” of the constituent bits, and stores the determined maximum value in the first register  102 . The second comparison and storage unit  104  determines a maximum value by sequentially sorting a corresponding output value according to binary logic “1” of the constituent bits, and stores the determined maximum value in the second register  106 . If the Walsh symbol for a single period is processed, the subtracter  108  subtracts the value stored in the second register  106  from the value stored in the first register  102  and generates result values R 1 -Rm. The result values R 1 -Rm are standards indicating the probability of the code word determined in the hard-decision logic unit  48 . Sign values S 1 -Sm of the result values R 1 -Rm are equal to the code word. 
     Operation of the RAKE receiver according to the present invention is now described in detail. For convenience, it is assumed that the Walsh-Hadamard is eight (8), although in a typical CDMA system, the Walsh-Hadamard is 64. 
     FIGS. 3A and 3B describe the operation of the soft-decision logic unit  50 . FIG. 3A depicts a table showing size values corresponding to eight (8) Walsh indexes. FIG. 3B depicts the operation of an embodiment of the soft-decision logic unit  50 . 
     The size values of the Walsh symbols corresponding to the Walsh indexes of correlator  35  are shown in FIG.  3 A. The Walsh symbols corresponding to the Walsh indexes are multiplied by the weights in multipliers  36 - 1  to  36 -N. The multiplication results are sequentially applied to adder  42  which adds the size values of the Walsh symbols to the value generated and held in the N-th register REG N of shift register  46 . Since it is assumed that there are eight (8) Walsh indexes, shift register  46  has eight (8) registers. Therefore, the two input sources added by adder  42  are a symbol size value of a previous rake for a corresponding index and a symbol size value of a current rake. The result obtained by adder  42  is supplied to the saturation logic unit  44 . Since the result of the adder  42  is obtained by repeatedly adding the symbol size values for various rakes, an overflow condition may occur. If the output of adder  42  exceeds a preset maximum value, the saturation logic unit  44  replaces that output value with the maximum value. The output of saturation logic unit  44  is applied to the first register REG  1  of the shift register  46 . An enable signal EN is supplied to the first to N-th registers (REG  1  to REG N) of shift register  46  each time the rake is assigned to a finger. The shift register  46  right-shifts the accumulated value whenever the enable signal EN is applied. As a result, registers REG  1  to REG N of shift register  46  hold the accumulated value of an output of the RAKE receiver corresponding to each Walsh symbol index. 
     The output of first register REG  1  of shift register  46  is applied to the soft-decision logic unit  50 . The output of first register REG  1  is also applied to the comparison and storage unit  60  of the hard-decision logic unit  48 . For example, as indicated in FIG. 3, the size values 3, 7, 5 , . . . , 1 and 2, corresponding to the Walsh indexes, are sequentially supplied to the comparison and storage unit  60  of the hard-decision logic unit  48 . The comparison and storage unit  60  compares a previous size value with a current size value and stores the larger value in an internal storage unit. For instance, if a size value three (3) of a Walsh index 000 is compared with a size value seven (7) of a Walsh index 001, the size value seven (7) is stored in the internal storage unit. In this case, the index 001 for the larger value seven (7) is also stored in the internal storage unit. If such a process is repeated for one period, a maximum size value Vmax and the index corresponding thereto are stored in the internal storage unit. Referring to FIG. 3A, the maximum size value Vmax, in this example, is 20 and its corresponding index is  100 . The maximum size value Vmax is temporarily stored in the maximum value register  62  and the index  100  corresponding thereto is temporarily stored in the index register  64 . The index temporarily stored in index register  64  corresponds to the code word. 
     Meanwhile, the size values corresponding to the Walsh indexes of bits B 0 , B 1  and B 2  having binary logic “0” among the output values of the first register REG  1  of shift register  46  are sequentially applied to each first comparison and storage unit  100  of first to m-th (where m is three (3) in this case) logic units  50 - 1  to  50 -m of the soft-decision logic unit  50 . For example, the size values 3, 5, 20 and 1, corresponding to the Walsh indexes of the least significant bit (LSB) B 0  having a binary logic value of “0”, are sequentially supplied to the first comparison and storage unit  100  of the first logic unit  50 - 1 . The size values 3, 7, 20 and 4, corresponding to the Walsh indexes of the bit B 1  having a binary logic value of “0”, are sequentially supplied to the first comparison and storage unit  100  of the second logic unit  50 - 2 . The size values 3, 7, 5 and 6, corresponding to the Walsh indexes of the most significant bit (MSB) B 2  having a logic value of “0”, are sequentially supplied to the first comparison and storage unit  100  of third logic unit  50 - 3 . Each first comparison and storage unit  100  of the logic units  50 - 1  to  50 - 3  compares the previous output value with the current output value and stores the larger value in an internal storage unit. The maximum size values 20(B 0 ), 20(B 1 ) and 7(B 2 ) for a binary logic value of “0” determined for one period are temporarily stored in each first register  102  of the logic units  50 - 1  to  50 - 3 , respectively. 
     The size values corresponding to the Walsh indexes for bits B 0 , B 1  and B 2 , having a binary logic value of “1” among the output values of the first register REG  1  of shift register  46 , are sequentially applied to each second comparison and storage unit  104  of logic units  50 - 1  to  50 - 3  of the soft-decision logic unit  50 . The second comparison and storage unit  104  and the second register  106  of logic units  50 - 1  to  50 - 3  operate similar to the first comparison and storage unit  100  and the first register  102 . The maximum size values 7 (B 0 ), 6 (B 1 ) and 20 (B 2 ), for a binary logic value of “1” determined for one period, are temporarily stored in each second register  106  of logic units  50 - 1  to  50 - 3 , respectively. 
     The maximum size values which are temporarily stored in the first register  102  and the second register  106 , according to each of the binary logic states “0” or “1” for the bits B 0 , B 1  and B 2  of the Walsh index, are shown in FIG.  3 B. Each subtracter  108  of logic units  50 - 1  to  50 - 3  subtracts the value stored in the second register  106  from the value stored in the first register  102  and generates the result values R 1 -R 3 . Referring to FIG. 3B, the result values are as follows: R 1 =+13, R 2 =+14, and R 3 =−13. The result values R 1 -R 3  indicate the probability of the code word determined in the hard-decision logic unit  48 , in which the larger the size of the result value, the higher the probability of the code word. If the result value is a positive number, the sign value is “0”, and if it is a negative number, the sign value is “1”. Therefore, the sign values S 1 -S 3  are 0, 0 and 1 which are equal to the code word (B 0 =0, B 1 =0 and B 2 =1). The output values (R 1 , S 1 ) to (R 3 , S 3 ) of the soft-decision logic unit  50  speed up determination for the signal component to be demodulated. That is, the soft-decision logic unit  50  raises search performance. 
     The outputs of the hard-decision logic unit  48  and the soft-decision logic unit  50  are applied to a subsequent signal processor, such as a channel decoder, for example. The channel decoder determines the signal component to be demodulated by using the outputs of the hard-decision logic unit  48  and the soft-decision logic unit  50 , and demodulates the signal component. 
     As may be apparent from the aforementioned description, the RAKE receiver according to the present invention is useful in reducing the amount of required hardware without lowering processing performance. For example, if 64 Walsh codes are used, a conventional RAKE receiver requires 64 accumulators. However, the preferred embodiment of the present invention described above uses only one accumulator and yet does not lower the processing speed. Moreover, since the present invention utilizes a soft-decision, the search performance is improved. 
     While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. That is, other modifications and variations to the invention will be apparent to those skilled in the art from the foregoing disclosure and teachings. Thus, while only certain embodiments of the invention have been specifically described herein, it will be apparent that numerous modifications may be made thereto without departing from the spirit and scope of the invention.