Abstract:
Carbon nanotube (CNT)-based devices and technology for their fabrication are disclosed. The discussed electronic and photonic devices and circuits rely on the nanotube arrays grown on a variety of substrates, such as glass or Si wafer. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for a large scale circuit integration. Such devices as p-n diode, CMOS-like circuit, bipolar transistor, light emitting diode and laser are disclosed, all of them are expected to have superior performance then their semiconductor-based counterparts due to excellent CNT electrical and optical properties. When fabricated on Si-wafers, the CNT-based devices can be combined with the Si circuit elements, thus producing hybrid Si-CNT devices and circuits.

Description:
FIELD OF THE INVENTION 
       [0001]    The invention relates to carbon nanotube array of p- and n-channel transistors and p-n diodes and specifically, to complementary circuits of nanorube array field-effect transistors as well as bipolar transistors and optoelectronic devices. 
       BACKGROUND OF THE INVENTION 
       [0002]    The Carbon Nanotubes (CNT) are viewed to be a new key element for future electronics. In the CNT, such unique properties as quantization of the electron spectrum, ballistic electron propagation along the tube, current densities as high as 10 9  A/cm 2 , existence of the semiconductor phase, possibilities for n- and p-doping with a high carrier mobilities, as well as excellent thermal conductance, make the nanotubes a great candidate for future novel high-speed, high efficiency electronic and photonic devices. 
         [0003]    The key element widely used in the electronic logic circuits is CMOS, wherein both switching states consume minimum energy, see. e.g. J. R. Brews in High-speed Semiconductor Devices, J. Wiley &amp;Sons, New York, p. 139, 1990. It is therefore important for future nanotube applications to reproduce such an element using CNT technology. Such attempts have been carried out in many research places worldwide. 
         [0004]      FIG. 1   a  shows as a Prior Art two CNT FETs in series, with n-type and p-type channel field-effect transistors (FET) forming the CMOS circuit, see V. Derycke et al, Nano Letters 1, p. 453,2001. The CNT CMOS is made from a single nanotube extended between source and drain metal contacts deposited on the Si substrate, while the controlling gate electrodes are made simply by placing the nanotube on top of the SiO 2  insulating layer on the n+Si substrate. To convert originally p-type CNT into n-type, one of the transistors has been subjected to annealing in vacuum. The resultant effect of voltage switch is shown in  FIG. 1   b.    
         [0005]    The proof-of-concept design, used in the above cited work, where a single nanotube is placed on the substrate between the contacts, is utilized in essentially all publication on this topic, for both CMOS circuit and individual transistors (see also E. Ungersboeck, et al, IEEE Transactions on nanotechnology, V 4, p. 533, 2005). The drawback of this method is its impracticality for any scale of circuit integration: placement of multiple identical nanotubes to enhance the output current or to form new circuit elements requires a special micro-manipulator and thus precludes any possibility of IC mass manufacturing. The future success of CNT devices will rely on emergence of a cost efficient manufacturing process that will ensure a high-yield and cost efficiency above the modem CMOS technology. 
         [0006]    The present invention discloses this technology. It is based on the growth of a controllable nanotube array on a metal electrode normally to the electrode plane and then sequential deposition of dielectric and metallayers to produce a solid platform for attachment of a second common contact to all the nanotube tips, thereby forming source and drain electrodes. The transistor gate electrode is made as a third conductive layer sandwiched between the dielectric layers and placed somewhere in the middle of the nanotube length. 
         [0007]    Such a technology was described in the patent application Ser. No. 11/705577 filed by A. Kastalsky on February 2007, where several nanotube array devices and method for their fabrication have been disclosed. Shown in  FIG. 2  as a Prior Art, is the nanotube array FET (the direction of the nanotube array is normal to the drawing plane) in which the nanotubes are grown normally to the substrate, and the gate electrode  51  is attached to the sidewall of every nanotube  57  in the array through a layer of insulator  54 . The key element is the metal layer  51  in the middle of the nanotube length, sandwiched between two insulator layers  52  and  53 . During deposition of the first insulator layer  52 , a thin layer of insulation material will also be deposited on the nanotube walls, thereby forming a gate insulator layer  54  around each nanotube. It is then followed by deposition of the gate metal layer  51  and the insulator layer  53 . After polishing of the insulator layer  53  and exposure of the nanotube tips, the top metal layer  55  (the drain electrode) is deposited to complete the structure. Such a design of the CNT transistor, with the nanotube buried within sequentially deposited insulating and metal layers, allows realization of the planar technology for commercial manufacturing of the CNT-based integration circuits. Several nanotube array devices will be disclosed below, all of them relying on the method of planar multilayer deposition technique combined with the appropriate processing for controllable formation of p- and n-type regions along the nanotube length during the device fabrication. 
         [0008]    Simple methods of variation of the carrier type of conductivity along the nanotube, utilized in the disclosed technology, allow simple fabrication of p-n diodes. They are expected to possess an extremely low intrinsic capacitance due to small nanotube diameter and therefore, very high operational frequency. Furthermore, p-n-p or n-p-n structures suitable for manufacturing of bipolar transistors are also within the scope of the disclosed devices. 
         [0009]    The electron-hole injection in the forward bias direction will provide inter-band optical emission due to electron-hole radiative recombination. Below, the nanotube array Light Emitting Diodes and Lasers will be disclosed, wherein excellent optical properties of CNTs ensure high efficiency of the proposed optoelectronic devices. 
         [0010]    The first object of the present invention is to disclose a new nanotube array circuit, analogous to Si-based CMOS logic element and the processing steps for its fabrication. 
         [0011]    The second object of the invention is to disclose the nanotube array bipolar transistor and the technology for its fabrication. 
         [0012]    The third object of the invention is to disclose the nanotube array p-n junction injection light emitting diode and the technology for its fabrication. 
         [0013]    The forth object of the invention is to disclose the nanotube array injection laser and the technology for its fabrication. 
       BRIEF DESCRIPTION OF THE INVENTION 
       [0014]    The above described objects of the invention essentially cover the majority of modem semiconductor electronic and optoelectronic devices: p-n diodes, transistors, CMOC switches, bipolar transistors, as well as light emitting diodes and lasers. Because of CNT outstanding electrical and optical properties, all these devices are expected to have parameters superior to their semiconductor counterparts. 
         [0015]    According to the present invention, the discussed above planar fabrication technology is used to disclose a circuit of two nanotube arrays of transistors with different types of conductivity connected in series to form a logic element Complementary Metal Insulator Nanotube (CMIN) device similar to the Si-based Complementary Metal Oxide Semiconductor (CMOS) circuitry. As in conventional CMOS, one of the transistor arrays has nanotubes with electron conductivity, while the second transistor array has nanotubes with hole conductivity. 
         [0016]    As discussed in the above cited publication by V.Derycke et al, the original single walled carbon nanotubes (SWCNT) are typically of p-type. The conversion into n-type occurs under annealing of nanotubes in vacuum. On the other hand, annealing in the oxygen atmosphere returns the nanotube back to p-type. Another option for p- to n-conversion is annealing of the CNTs in a potassium atmosphere. 
         [0017]    Thus, the CMIN, according to the present invention, contains two nanotube arrays of different types of conductivity, each having a transistor structure shown in  FIG. 2  as a Prior Art. The transistor arrays are connected in series through the top electrode, while the metal layer in the middle of the structure represents a common gate electrode for both arrays. This method of growth of CNT arrays in predetermined position and planar deposition of multi-layer structure, with the nanotubes being buried inside the structure, provides the device processing suitable for the large scale integration of CNT-based ICs. 
         [0018]    Similar planar multilayer deposition technique is applied for fabrication of a new nanotube array bipolar transistor (NABT) of p-n-p and n-p-n device configurations, the change in the type of conductivity in the middle of the nanotube (transistor base) being produced using the described above methods of annealing in vacuum or in appropriate gas atmosphere. The contact to the base will be made using the same method of deposition of the metal layer sandwiched between two dielectrics, similar to the gate in the CMIN. Unlike the insulated gate of the CMIN, however, the metal in the NABT is directly attached to the nanotube sidewall to provide the base contact with a low contact resistance. To minimize the contact resistance, Pd as a contact metal is preferable, see A. Javey et al, Nano Letters, V. 4. p. 1319, 2004. The disclosed nanotube array bipolar transistor is expected to possess unique speed of operation due to both ballistic carrier travel across the base and extremely low intrinsic device capacitances. 
         [0019]    A simple nanotube array of p-n junctions can be a very attractive new optical element. The electron-hole injection will result in a radiative recombination, and the device is expected to function as a nanotube array light emitting diode (NALED). 
         [0020]    The excellent optical properties of the CNTs (see below) can also be used for creation of the nanotube array injection lasers (NAIL). The nanotube array “quantum wire” laser is close in its nature to the semiconductor quantum wire laser, see e.g Book on Quantum Well Lasers, Ed. by P. S. Zory, 1993. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]      FIG. 3 . Cross-sectional view of the CMIN structure. 
           [0022]      FIG. 4 . Processing steps for CMIN fabrication. 
           [0023]      FIG. 5 . Cross-sectional view of the NABT structure. 
           [0024]      FIG. 6 . Cross-sectional view of the NALED structure. 
           [0025]      FIG. 7 . Cross-sectional view of the NAIL structure. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0026]    1. Design and Fabrication of CMIN 
         [0027]    In the CMIN design, shown in  FIG. 3   a , two arrays of the nanotubes  31  and  32  are grown on two separate metal electrodes  33  and  34  normally to the substrate  30 , which can be glass plate or Si wafer or any other dielectric substrate capable of sustaining nanotube growth temperatures (˜600° C.). The nanotube arrays have different types of conductivity, which are produced using above discussed methods of the type conversion. Let as assume that nanotubes  31  are p-type and nanotubes  32  are n-type, although reverse type assignment is equally applicable, since the CMIN structure is symmetrical. The metal layer  35  sandwiched between two dielectric layers  36  and  37  represents a common gate for two transistors, wherein the first transistors comprises the substrate metal  33  as a source, the nanotube array  31  as a conducting p-channel and the top metal layer  38  as a drain, while the same top metal layer  38  is a source of the second transistor, the nanotube array  32  is an n-channel and substrate metal  34  is a drain. The dielectric layer  39  provides the electrical insulation of the gate metal  35  to both transistor channels. 
         [0028]    If the p-channel (array  31 ) is originally conducting and n-channel (array  32 ) is depleted, a positive voltage to the gate metal  35  will make n-channel conducting and p-channel depleted, so that the output voltage taken from the connecting metal electrode  38  will be switched from minimum to maximum amplitude if positive voltage Vdd is applied to the drain electrode  34  of the n-channel transistor relative to the source electrode  33  of the p-channel transistor. On the other hand, change of the polarity of Vdd will result in switching the output voltage from its maximum to minimum amplitude at the same positive gate voltage. 
         [0029]    A single nanotube from each array  31  and  32  can form two nanotube CMIN circuit. Due to sustainable current density in the SWCNT of 10 9  cm −2 , the two nanotube CMIN can provide the current switch of 10 μA. With a realistic nanotube spacing in the array of 1 μm, a 100 μm-long and nanotube diameter wide array will provide 1 mA output current switch, sufficient for IC operations. 
         [0030]      FIG. 4  shows the processing steps for the CMIN fabrication. It begins from deposition on the substrate  41  of two arrays of metal pads  42  to form first source and drain contacts in predetermined positions,  FIG. 4   a.  As mentioned above, the layer of Pd is preferable since it provides the lowest contact resistance. It is followed by a placement on the contacts  42  of small pads  43  of catalytic material, such as Co, Ni or Fe, needed for the nanotube growth. After growth of the nanotube arrays  44  and  45 , see  FIG. 4   b,  which are normally have p-type conductance, one of the arrays,  44 , is protected by deposition of the sacrificial dielectric layer  46 , see  FIG. 4   c,  while another nanotube array  45  remains exposed and is annealed in vacuum or in potassium atmosphere to convert it into n-type. Then the sacrificial layer  46  is removed, and two arrays  44  and  45  of respective p- and n-types are ready for further processing.  FIG. 4   d  shows the dielectric layer  47  which is deposited on the substrate and covers the metal electrodes with the nanotubes. At the same time, a thin dielectric layer  48  also coats the side walls of the nanotubes. The metal layer  49  deposited atop of the dielectric  47  represents the common gate electrode for both arrays, see  FIG. 4   e,  while the layer  48  of  FIG. 4   d  is the gate insulator. Then the second dielectric layer  50  covers the nanotube arrays, see  FIG. 4   f.  This layer provides a platform for placement of the top contacts to the transistors. It is preferable to make the layer  50  thin enough to have the nanotube ends slightly protruded above this layer. After polishing, to remove the nanotube ends, the final metal layer  51  is deposited on the exposed nanotube ends to connect the arrays into the circuit of two transistor arrays and form the other two source and drain contacts for transistor circuit. Again, the Pd layer is preferable. Thus, according to the present invention, the planar technology of sequential deposition of dielectric and metal layers allows fabrication of the CMIN circuitry. 
         [0031]    The fundamental advantages of the CMIN devices, beyond simplicity of its fabrication, is absence of any physical limits for performance improvement. In the Si world, quantum mechanical laws preclude the current rate of reduction in transistor feature size (gate length), and in order to continue improvements in device speed and cost per chip at present pace it is necessary to develop new switching circuits wherein these limitations are not at work. In the CMIN design, with gate plane intersecting the nanotube cylinder, these limitations are not applicable. The gate length in this case is controlled essentially by the gate metal thickness and can be made very thin without complication in the device processing. On the other hand the gate insulator coating the nanotube sidewalls can also be made very thin. Finally, the carriers in the short nanotube transistor channel will move ballistically, i.e. with a velocity significantly exceeding the saturated carrier velocity in the Si channel of ˜10 7  cm/s. This implies that CMIN looks the best candidate for future replacement of Si-based transistors. On the other hand, Si wafer can be used as a substrate for CMIN fabrication, and therefore Si-based and CNT-based devices can merge into integrated hybrid ICc. 
         [0032]    2. Design and Fabrication of NABT 
         [0033]    The NABT structure contains the nanotubes, in which the conductivity within a short distance in the middle of the nanotube is converted into the opposite type to form a transistor base.  FIG. 5  illustrates the NABT structure. It starts from deposition of the emitter contact  50  on which the nanotube array  52  is grown. It is followed by deposition of four dielectric layers,  53 ,  54 ,  56  and  57  and the metal layer  55  which is sandwiched between two thin dielectric films  54  and  56 . 
         [0034]    After deposition of the layer  53 , the nanotubes are subjected to above discussed procedures for converting the type of conductivity. For example, if the p-n-p NABT is considered, after completion of the layer  53 , the nanotubes are cleaned up to remove a thin layer of insulator from the nanotube sidewalls and annealed in vacuum to convert uncovered nanotubes into n-type. Then a thin dielectric layer  54  is deposited to ensure that the metal layer  55  has a contact within the n-type region. After deposition of the protective dielectric film  56 , the nanotubes are cleaned and annealed again, this time in the air, to return the uncovered nanotubes back to p-type. Hence, the length of the n-type region (base “thickness”) is controlled by the total thickness of the layers  54 ,  55  and  56 . After deposition of the last dielectric layer  57 , the device surface is polished to expose the nanotube ends, and finally the metal layer  58  (collector) completes the structure. 
         [0035]    Similar processing steps can be done for the n-p-n type device configuration. In this case, starting from the n-type nanotubes, the base region can be converted into p-type by annealing the nanotubes in the air, and the collector part of the nanotubes is converted back to n-type by annealing in vacuum. 
         [0036]    The NABT is expected to possess superior properties than classical Si bipolar transistor. First, the base length determined by the thickness of the three layers  54 ,  55  and  56  can be made very short ˜20-30 nm. This length is sufficiently short to expect a ballistic carrier movement along the nanotube or at least within a part of it, see.e.g. A. Javey et al. Nano Letters, V. 4, p. 1319, 2004. This implies much higher carrier speed than that in a classical semiconductor transistor base. In addition, due to miniature nanotube size the intrinsic transistor capacitances will be minimized. Finally, there is no potential drop across the nanotube diameter, which precludes any effects of “current crowding”, when the transistor efficiency in the center of the device decreases due to a lateral potential drop across the base, see. e.g. S. Sze, Physics of Semiconductor Devices, J. Wiley &amp; Sons, NY, 1969. 
         [0037]    3. Design and Fabrication of NALED 
         [0038]    Simple methods of variation of the carrier type of conductivity along the grown nanotube allows fabrication of p-n diode arrays. They are expected to possess an extremely low intrinsic capacitance due to small nanotube diameter and therefore, very high operational frequency. 
         [0039]    Electron-hole injection in the forward bias direction will produce an interband photon emission. Two-dimensional quantization of electron and hole energy in the nanotube (i.e. “quantum wire” effect), with the density of states peaking at the quantum levels, ensures a high light emission efficiency, see E. Kapon, Proc. IEEE, 80, p. 398,1992 and Book on Quantum Well Lasers, Ed. by P. S. Zory, 1993, p. 461. In addition, the nanotubes are calculated to have oscillator strength orders of magnitude larger than that in conventional direct gap semiconductors, see V. Perebeinos et al, Phys. Rev. Lett. 94, 086802, 2005. These features suggest an extremely high optical efficiency in the NALED. 
         [0040]      FIG. 6  shows the NALED structure. It starts from deposition of the metal electrode  60  on which the nanotube matrix  61  is grown in the predetermined pattern: it can be made as a linear array or as a two-dimensional matrix, as shown in  FIG. 6 . The metal layer  60  is made from material having a high optical reflection, such as Al. The metal pads of Pd are then deposited (not shown), to minimize the contact resistance, and the small pads of the catalytic material are deposited to facilitate the nanotube growth (not shown). The thickness of the first dielectric layer  62  reaches approximately a half of the nanotube length. At this stage, the remaining exposed nanotube parts are cleaned, and change of the nanotube type of conductivity is made using the above discussed methods of p-to-n and n-to-p conversions, thus forming a p-n junction. The second dielectric layer  63  is then deposited, and the top surface is polished to expose the nanotube ends. It is followed by deposition of the optically transparent conductive layer of ITO 64 to provide both the top contact to the nanotubes and optical transparency for the surface light emission. 
         [0041]    It is important that the light radiating nanotubes are much smaller in size than the expected light wavelength. Therefore, light will be freely emitted from the nanotubes without any internal light reflections, in contrast with a conventional LED where due to internal light reflections typically only ˜5% of light is released, see e.g. R. H. Saul et al, LED Device Design, Semiconductors and Semimetals, v. 22, p. 193, Part C, 1985, unless special measures are undertaken to minimize this effect. In the NALED, having the light reflecting bottom metal layer  60 , almost 100% of light output will be emitted upward. In addition, other factors adversely affecting the light power in the semiconductor LED, such as interfacial non-radiative recombination or self-absorption in the heterostructure, do not exist in the NALED. Finally, the fabrication technology for NALED is immeasurably simpler than that for a classical LED, where a multilayer lattice matched semiconductor heterostructure must be epitaxially grown and then carefully processed. Even a single nanotube can be used as a light emitter. For a sustainable current of 10 −5  A (equivalent to the current density of ˜10 9  A/cm 2  in a single walled nanotube), the applied voltage of ˜2V and a conservatively chosen light efficiency of 10%, one obtains the output light power of ˜2 μW from a single nanotube. For the matrix of 100×100 nanotubes, 1 μm apart, it translates into a light power of 20 mW and the light power density of 200 W/cm 2 , unachievable for the existing LEDs. 
         [0042]    In the NALED of  FIG. 6 , the light output is directed into the top hemisphere through the transparent electrode ITO, thus making a surface emitting LED configuration. On the other hand, the light wave can propagate along the substrate plane. To minimize the light interaction with the metal electrodes, a specific wave guiding structure should be built using a combination of the dielectric layers having different index of refraction, such as SiO 2  and Si 3 N 4 , see below. In this case, the top contact layer  64  can be made from Pd. 
         [0043]    4. Design and Fabrication of the NAIL 
         [0044]    Excellent expected optical efficiency of the nanotubes produces attractive conditions for the CNT quantum wire laser activity: peaking density of states at the quantum levels make the carrier population inversion quite plausible. In comparison with the existing semiconductor heterostructure quantum wire lasers, see aforementioned citations of E. Kapon, the CNT exhibits significantly more pronounced effect of quantization due to much smaller size of the quantum wire (nanotube diameter): ˜100 nm for semiconductor case vs. ˜1 nm for SWCNT. High calculated oscillator strength at the energy gap in the CNT, much higher than that in the semiconductors, would provide lower threshold for lasing. Finally, the NAIL technology is simple and far less expensive than that of the semiconductor-based quantum wire lasers. 
         [0045]      FIG. 7 . shows the NAIL structure. The nanotube matrix  76  is grown on the metal layer  70 . It is preferable to use Pd layer to minimize the contact resistance. Then four dielectric layers  71 ,  71 ,  73  and  74  are deposited to form the core of the waveguide ( 72  and  73 ) and two cladding layers  73  and  74  for efficient light propagation parallel to the substrate plane. The thin identical layers  72  and  73  of the core have the index of refraction n c  larger than that of the cladding layers  73  and  74 , n cl . 
         [0046]    After deposition of the half of the waveguide, i.e. layers  71  and  72 , the type of conductivity in the exposed nanotube array is altered by the earlier discussed methods to obtain a p-n junction along the nanotubes, with the change of conductivity occurring in the middle of the nanotube length. Then two other layers,  73  and  74 , complete the waveguide structure. After polishing the top dielectric  74 , to expose the nanotube ends, the top contact layer  75 , preferably Pd, is deposited. 
         [0047]    The optimal thickness D of the total core layer composed of the layers  72  and  73 , depends on the difference of the refractive indices, n c −n cl , and the wavelength λ. The fraction of the light intensity contained within the core, Γ, is given by, see e.g. J. P. Leburton et al, J. Vac. Sci. Technol. B1, 415, 1983: 
         [0000]      Γ=(2π 2    D 2)/λ 2 ( n   c   2   −n   cl   2 ) 
         [0048]    Using the Si 3 N 4  material for the core layers  72  and  73 , with n c =2.5, and SiO 2  material for the cladding layers  71  and  74 , with n cl =1.46, one obtains for λ˜1 μm and Γ˜1, D˜200 nm. The cladding layers  71  and  74 , 2 μm each, make the total laser structure thickness of ˜4.2 μm. Under these conditions, the laser wave strongly decays within cladding layers and practically does not interact with the contact layers  70  and  75 . Two mirrors  77  and  78  at the ends of the laser bar are then deposited to make a Fabri-Perot resonator. It is also important that in the NAIL optical loss through free-carrier absorption is minimized since the interaction of the laser wave with conductive media occurs only at the nanotubes occupying extremely small device volume. 
         [0049]    The NAIL structure without the mirrors  77  and  78  will operates as the LED with light propagation within the waveguide structure parallel to the substrate plane. 
         [0050]    Thus, the disclosed technology unites together two different industries: electronics, normally relying on Si as a material for ICs, and opto-electronics, typically employing III-V heterostructure materials. The proposed CNT-based devices and fabrication methods cover both these worlds: the new disclosed electronic and photonic devices can be combined on the same substrate, which can be a Si wafer or a piece of glass. The performance of these devices is expected to be greater than that of their semiconductor counterparts, largely due to excellent nanotubes properties, while the manufacturing cost is expected to be significantly lower. 
         [0051]    The disclosed technology, according to the present invention, can be characterized by several key features, such as:
       1. The nanotube arrays are grown normally to the substrate plates in predetermined positions and with controlled height;   2. The planar multiple layer dielectric and metal deposition technique is the basic process for device fabrication;   3. The CNTs allow simple methods of p-to-n and n-to-p type conversion;   4. CNTs can be grown on a variety of substrates, from Si wafer, to piece of glass or ceramics.       
 
         [0056]    All these features open up the opportunity for mass production of the new classes of electronic and photonic devices with potentially great performance at low cost.