Abstract:
A power-up reset detector circuit is described which uses the threshold voltages of NMOS and PMOS transistors to detect the power-up of integrated circuits, and uses a current mirror to track power supply and process variations.

Description:
TECHNICAL FIELD 
     The present invention is directed generally to power-up detection circuitry, and more particularly to a power-up detection circuit which does not rely upon the energy transferred across a coupling capacitor or the beta ratio of back-to-back inverters. 
     BACKGROUND ART 
     The present invention is useful in integrated circuits that include data storage elements such that in order to protect the integrity of the stored data the chip has to remain in a disabled state until the power supply reaches some known stable value. In most cases, it is desirable to keep internal registers and timing circuits in a reset condition in order to prevent the chip from performing any functions until the power supply has been stabilized. This is to ensure that the chip always starts in a known condition. For example, the chip timing circuits normally will start from a count of zero. During power-up, a cross-coupled latch circuit can come up in any state. If the cross-coupled latch comes up in the wrong state, this could change the state of internal registers and counters used in timing and thereby change the functionality of the part. 
     In most systems where memory elements are employed, it is necessary to ensure that there is no inadvertent writing of data to the memory elements while the system is powered up. This is achieved by the use of power-up reset circuits to ensure that the system has stabilized before other circuit functions are enabled. A typical conventional power-up reset circuit is illustrated in FIG. 1. However, this type of circuit suffers from two main disadvantages as follows. 
     The first disadvantage is that it depends upon the amount of energy transferred across the coupling capacitor C 1  as the V cc  power supply, V supply , is rising. The amplitude of the energy transfer is largely a function of the &#34;rate&#34; at which the V cc  power is changing, which rate can vary from a few hundred microseconds to several milliseconds. In FIG. 1, the amplitude to which node V 1  rises will determine the trip point of the circuit Thus, the circuit is susceptible to noise spikes and may not respond to a very slowly rising power supply level. 
     Secondly, in FIG. 1, the beta ratio of the latch created by back-to-back inverters I 1  and I 2  has to be very carefully designed so that the nodes V 1  and V 2  come up in the correct state during the power-up process. Hence, the beta ratio has to allow the coupling capacitor C 1  to couple node V 1  high and capacitor C 2  to couple node V 2  low until the feedback voltage V 4  on the gate of transistor N 1  exceeds the threshold voltage V t . This causes N 1  to turn on and pull node V 1  back down to a low state, and the output of the circuit to go to a high state. 
     If instead, the beta ratio were not correct, inverter I 1  might start out with a logic one output which would cause inverter I 2  to prevent V 1  from going positive during power-up. This would also prevent N 5  from turning on and hence prevent feedback voltage V 4  from exceeding the threshold voltage of N 1 , and thereby prevent the flipping of the latch. 
     It would therefore be desirable to have a power-up detection circuit which does not depend primarily upon energy tranferred across a coupling capacitor or the beta ratio of back-to-back inverters for proper operation. 
     SUMMARY OF THE INVENTION 
     The above and other problems and disadvantages of the present invention are overcome by the present invention of a circuit for detecting a power-up condition on a supply voltage line including a power detect circuit, a current mirror circuit, an amplifier, and an output latch/power-down circuit. The power detect circuit provides a disable signal when power is initially applied to the supply voltage line. The current mirror disables the power detect circuit, and provides an output signal and a control signal, when a voltage on the supply voltage line exceeds a predetermined threshold level. The amplifier is controlled by the disable signal from the power detect circuit and the control signal from the current mirror, and is coupled to receive the current mirror output signal. The amplifier provides a drive signal proportional to the current mirror output signal. The output latch/power-down circuit is disabled by the disable signal from the power detect circuit and enabled by the drive signal from the amplifier. The power-down/latch circuit decouples the power detect circuit, the current mirror, and the amplifier from the supply voltage line, and provides a reset output signal upon receipt of the drive signal from the amplifier. 
     In accordance with the present invention, better control of the power-up reset function is obtained, and in a manner independent of the slew rate of the V cc  (supply voltage) power. 
     It is therefore an object of the present invention to provide a power-up reset circuit which is independent of the slew rate of the power supply voltage. 
     It is another object of the present invention to provide a power-up reset circuit which does not depend upon the beta ratio between back-to-back inverters. 
     It is a further object of the present invention to provide a power-up reset circuit which relies primarily upon transistor threshold voltages for setting internal threshold levels. 
     These and other objectives, features and advantages of the present invention will be more readily understood upon consideration of the following detailed description of the present invention and accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is schematic diagram of a prior art power-up reset circuit. 
     FIG. 2 is a simplified functional block diagram of one embodiment of the present invention. 
     FIG. 3 is a more detailed schematic of the embodiment of the power-up reset circuit of the present invention illustrated in FIG. 2. 
     FIG. 4A is a simulation of the voltages at selected nodes of the circuit of FIG. 3 during a power-up condition. 
     FIG. 4B is a simulation of the voltages at selected nodes of the circuit of FIG. 3 during a power-up condition, over different temperatures. 
     FIG. 5 is a more detailed schematic of the embodiment of the power-up reset circuit of the present invention illustrated in FIG. 2, where the threshold voltage is set to be approximately V tp  +2V tn . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 2 provides a simplified functional block diagram of one embodiment of the present invention. The circuit has four main circuit blocks: a current mirror 12, a power detector 14, an amplifier 16, and an output-driver/power-down stage 18. The current mirror 12, power detector 14, and amplifier 16 are coupled to the supply voltage line 20, V supply  by way of transistor M1. 
     When power is initially applied to the supply voltage line 20, power-up detector 14 generates a signal on line 28 which is applied to temporarily disable amplifier 16, and a signal on line 32 to temporarily maintain transistor M 1  in an ON state. 
     As the voltage level on the supply voltage line 20 rises further, current mirror 12 becomes operable and provides an output signal on line 22 and an enable (or control signal) signal on line 24. The output signal on line 22 disables the power detector 14 and overrides its disable signal on line 28, and the enable signal on line 32. At the same time the output signal on line 22 is amplified by amplifier 16 which at the same time is enabled by the enable signal on line 24. 
     The amplified signal from amplifier 16 operates to enable the output-driver/power-down stage 18, which in turn provides the reset output of the overall circuit, and also disables transistor M 1  by applying a disable signal to the gate of transistor M 1  via line 26 after the power up trip point voltage is reached. This removes power from the current mirror 12, power detector 14, and amplifier 16 circuitry, to reduce the power consumed thereafter by the power-up reset circuit of the present invention. 
     Referring now to FIG. 3, a more detailed schematic diagram of the preferred embodiment of the present invention is provided and will now be described. The circuitry in the schematic diagram of FIG. 3 is grouped generally according to the functional blocks of FIG. 2. Like signals and components between the two figures will be referred to by the same reference designations and names. 
     The current mirror 12 is formed by p-channel field effect transistors (&#34;PFETs&#34;) M 2  and M 3  and n-channel field effect transistors (&#34;NFETs&#34;) M 4 , M 5 , and M 6 . Transistor M 3  is diode-connected with its source connected to the drain of PFET M 1  at node Vpow. Transistor M 2  has its gate connected to the gate of M 3  and its source connected to node Vpow. Transistor M 6  is diode-connected with its source connected to ground and its drain connected to the drain of transistor M 3 . The gate of transistor M 5  is connected to the gate of transistor M 6  and to line 24, and its source is connected to ground. Transistor M 4  controls the signal path between the drain of transistor M 2  and the drain of transistor M 5 , and has a gate which is connected to be controlled by the voltage level at the junction of the drains of transistors M 3  and M 6 . 
     The power detector 14 is formed by PFET M 7 , NFETs M 8  and M 13 , and capacitor C 1 . The source of M 7 , is connected to node Vpow, its gate is connected to receive the output signal from current mirror 12 on line 22, and its drain is connected to the drain of M 8 . Capacitor C 1  is connected between the gate and drain of M 7 . The gate of transistor M 13  is connected to the drain of transistor M 7 , its source is connected to ground, and its drain is connected to the gate of M 1  via line 32. 
     The amplifier 16 in the embodiment of FIG. 3 is a voltage gain stage formed by PFETs M 9  and M 10 , and NFETs M 12 , M 14 , and M 15 . Transistor M 9  is diode-connected, with its source connected to node Vpow. The source of transistor M 10  is also connected to node Vpow, while its gate is connected to the gate of transistor M 9 . The sources of transistors M 12  and M 15  are connected to ground, with the drain of transistor M 12  being connected to the drain of transistor M 10 . The gate of transistor M 15  is connected to line 24 from current mirror 12, while the gate of transistor M 12  is connected to the drain of M 7  via line 28. Finally, transistor M 14  controls the signal path between the drains of transistors M 9  and M 15 , and is controlled by the signal on line 22. 
     The output-driver/power-down stage 18 is formed by inverters I 1  and I 2 , and PFETs M 16  and M 17 . Inverter I 1  receives a signal on line 30 from the junction of the drains of M 10  and M 12 , and in turn drives inverter I 2 . The gates of M 16  and M 17  are both connected to the output of inverter I 1 , and their sources are both connected to the output of inverter I 2 . The source of M 17  is used to feedback the reset output signal to the input of I 1  when the output of inverter I 1  is low. 
     Referring to FIGS. 3 and 4A, the operation of the circuitry of FIG. 3 will now be described. Initially, all nodes in the circuit are at 0 volts. As the power-up process begins, the source of transistor M 1  receives power from V supply  and M 1  begins to supply power to the current mirror 12, power detector 14, and amplifier 16. At this point in time, node Vpow is ramping toward V cc . When node Vpow reaches the PFET threshold voltage, V pt , transistors M 2 , M 3 , M 9 , and M 10  begin to turn on. 
     Transistor M 7 , however, is designed to have a turn-on rate which is faster that that for M 2 , M 3  and M 9  and M 10 , such as can be obtained by making the physical size of M 7  larger than that of M 2 , M 3 , M 9  or M 10 . This allows the voltage at node V3 to rise with V supply  and to cause transistors M 12  and M 13  to turn on once the voltage on node V3 has reached the NFETs threshold voltage, V tn . In the example of FIG. 4A, voltage V3 is shown ramping up to approximately 0.7 V during this time frame, t1. In turn, during time period t1, this keeps the voltage at node V4 low, and also turns on transistor M 13  to keep transistor M 1 , on. Thus, initially, the Reset Output level will be low. In FIG. 4A, this is shown by the dashed line labelled V(out), which is at or near the horizontal axis of the graph during period t1. 
     During this period t1 the voltage on nodes V2 and V5 will be rising, but at a slower rate than the voltage at node V3. As M 7  turns on, node V3 will follow the voltage Vpow-V tp , where V tp  is the PFET threshold voltage of transistor M 7 . Normally, V tn  &lt;V tp , hence as M 7  turns on, the voltage at node V3, Vpow-V tp , will be greater than Vtn thereby turning on transistors M 12  and M 13  and keeping node V4 low. 
     As Vpow continues to increase towards V supply  +V tp , current mirror 12 will begin to become operational. This will cause the voltage at node V1 to increase to a point where the gate-source voltage across M 7  begins to drop below V tp , thereby causing M 7  to begin to turn off. This can be seen to occur during time period t2 of FIG. 4A. 
     More specifically, the voltage V2 in current mirror 12 initially will follow Vpow-V tp , and then cause transistor M 4  to turn on once Vpow-V tp  has reached V tn . This occurs at time t3 in FIG. 4A. Preferrably, the current flowing in leg M 3  -M 6  is twice (2X) the current in M 2  -M 5 , and is set to control the trip point (the point at which the power detector 14 is disabled) of transistors M 7  and M 8 . In otherwords, by proper ratioing of the current in leg M 3  -M 6  to the current in leg M 2  -M 5 , the voltage at node V1 can be controlled as a function of the level of Vpow-V tp , and hence the point at which power detector 14 is disable can be controlled. 
     In operation, M 4  prevents current from flowing into M 5  until the gate of M 4  reaches the V tn  threshold level. At this point, Vpow will be at V tp  +V tn . Once M 4  begins to turn on, current will begin flowing into M 5  and the rate at which voltage V1 increases will be lower; however V1 continues to increase to ensure that M 7  will turn off. In the embodiment of FIG. 4A, V1 approaches and is eventually clamped at 2.6 V, at which point M 7  is turned off. 
     During time period t2, once M 4  is turned on, the current source formed by transistors M 5  and M 6  will begin to turn on transistors M 8  and M 15 . As M 8  turns on, the voltage at node V3 starts to fall, and transistors M 12  and M 13  begin to turn off. With M 15  now turning on, M 14  can begin to turn on, since the gate of M 14  in amplifier 16 will already be above V tn . This permits the voltage on node V5 to begin to fall which causes transistor M 10  to turn on. With M 12  and M 10  turning on and off, this permits the voltage on node V4 to rise, and thereby trigger output-driver/power-down stage 18 to output the reset output signal at time t3. 
     In other words, as Vpow reaches V tp  +V tn  during time t2, transistors M 7  is turning off and transistor M 8  is turning on. This causes the voltages at nodes V3 and V5 to fall, which in turn causes transistor M 12  to turn off and M 10  to turn on. This causes the voltage at node V4 to rise and trip the state of the circuit. 
     Therefore, the circuit will &#34;trip&#34; when Vpow is close to V tp  +V tn . 
     When the trip point of the circuit is reached, the voltage on node V4 will rise to V supply . This will force the output of inverter I 1  to go low, and turn on the PFET transistors M 16  and M 17 . Inverter I 2  provides the output drive for the circuit and follows the state of node V4. When transistors M 16  and M 17  are turned on, M 17  will feed back the output level of the circuit to the gate of transistor M 1 , to turn it off. This decouples the current mirror 12, power detector 14, and amplifier 16 from V supply  and powers them down so that these stages thereafter consume no power. Transistor M 16  feeds back the output voltage of the circuit to the input of inverter I 1  to keep the I 1  and I 2  latched in their current state. 
     Table 1 provides an illustrative list of the relative sizes of the transistors in FIG. 3. 
     
                       TABLE 1______________________________________Transistor      Type    Size______________________________________M1              NFET    50/2M2              NFET    20/10M3              NFET    20/10M4              NFET    40/3M5              NFET    10/10M6              NFET    15/10M7              NFET    40/5M8              NFET     5/10M9              NFET    20/10 M10            NFET    20/10 M12            NFET    10/6 M13            NFET    3/6 M14            NFET    20/3 M15            NFET     5/10 M16            PFET     3/12 M17            PFET     3/10______________________________________ 
    
     FIG. 4B illustrates the output response of the circuit of FIG. 3 for different supply voltages and temperatures. 
     In the amplifier 16 stage of FIG. 3, capacitor C 1  is useful when V supply  is at very low levels, such as below 2.0 V. Capacitor C 1  operates to couple the change in level of Vpow as the circuit is powered up, to the gates of M 12  and M 13  in order to assist M 7  in turning them on. 
     FIG. 5 illustrates another embodiment of the present invention in which transistor M 5 , instead of M 6 , of current mirror 12 is diode-connected. In this configuration, both M 5  and M 4  will have to turn on before current mirror 12 become operational. This results in an increase in the trip point voltage by an additional V tn . Therefore, while the trip point of the circuit of FIG. 3 is close to V tp  +V tn , the trip point of the circuit of FIG. 5 will be closer to V tp  +2V tn . 
     While the embodiments of FIGS. 2, 3 and 5 show the supply voltage line 20 coupled to Vpow through transistor M 1 , it is to be understood that the invention can be practiced without the use of M 1 , where it is not desired to power down the circuitry following issuance of the reset output. In that case, for example, the output-driver/power-down stage 18 may also not be necessary, and amplifier 16 might be used as the output circuit for the invention. Furthermore, while these figures also show the use of amplifier 16, it is to be understood that different amplifiers, or no amplifer at all, may be used within the spirit of the invention, depending upon the drive capabilities of the current mirror used and the requirements of the output-driver/power-down stage 18. 
     The terms and expressions which have been employed here are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding equivalence of the features shown and described, or portions thereof, it being recognized that various modifications are possible within the scope of the invention claimed.