Abstract:
A semiconductor integrated circuit includes a constant current circuit and a start-up circuit. The constant current circuit includes a first current mirror circuit including a first and second transistors; and a second current mirror circuit including a third transistor connected to a first node and a fourth transistor connected to a second node. The start-up circuit includes a fifth transistor that supplies start-up current to the constant current circuit via the second node; a sixth transistor that uses a potential of the first node as a control voltage; a seventh transistor that is connected to a third node into which current from the sixth transistor flows and that has a diode-connected configuration; a capacitor connected to a fourth node into which current from the seventh transistor flows; and a latch circuit that controls the fifth based on a potential of the fourth node.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based on and claims priority under 35 USC 119 from Japanese Patent Application No. 2011-124445 filed on Jun. 2, 2011, the disclosure of which is incorporated by reference herein. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The present invention pertains to a semiconductor integrated circuit and particularly relates to a semiconductor integrated circuit that starts up a constant current circuit. 
         [0004]    2. Related Art 
         [0005]    A semiconductor integrated circuit equipped with a circuit that starts up a constant current circuit has been proposed which, as illustrated in  FIG. 4 , includes a constant current circuit  112  and a start-up circuit  114 . The constant current circuit  112  includes a first current mirror circuit  101 ′ configured by two first electrically conductive transistors (P-channel MOS transistors) M 1 ′ and M 2 ′ and a second current mirror circuit  102 ′ configured by two electrically conductive transistors (N-channel MOS transistors) M 3 ′ and M 4 ′. The semiconductor integrated circuit illustrated in  FIG. 4  is a configuration that addresses a problem of not being able to supply a start-up current to the constant current circuit and not being able to start up the constant current circuit when the rise of the power supply voltage is slow in a case in which transistors whose threshold voltages Vt are low are used as the transistors configuring the current mirror circuits. 
         [0006]    That is, in the semiconductor integrated circuit illustrated in  FIG. 4 , a transistor M 5 ′ is switched on (becomes conductive) before a capacitor C 1 ′ is charged, and the on-current of the transistor M 5 ′ is used as the start-up current and is supplied to the constant current circuit  112  to start up the constant current circuit  112 . After start-up, a node N 4 ′ is charged to the power supply voltage level, the transistor M 5 ′ becomes non-conductive, and the constant current circuit  112  stabilizes at a predetermined operating point. Here, by using a transistor whose threshold voltage Vt is high as a transistor M 7 ′, in a case in which the rise of the power supply is slow, an increase in the potential of the node N 4 ′ resulting from leak current at a time when the temperature is high is prevented, while the gate-source voltage (Vgs) of the transistor M 5 ′ exceeds the threshold voltage Vt during that time, and the start-up current is supplied to the constant current circuit  112 . 
         [0007]    However, in the conventional semiconductor integrated circuit described above, in a case in which the rise of the power supply is slow, charging is performed, with respect to the capacitor C 1 ′ having one terminal connected to the node N 4 ′, by current in the sub-threshold region (also called the weak inversion region) of the transistor M 7 ′, that is, the capacitor C 1 ′ is charged by current flowing between the source and drain even if the gate voltage of the transistor M 7 ′ is equal to or less than the threshold voltage Vt. As a result, as indicated by the long dashed double-short dashed line in  FIG. 5  for example, the node N 4 ′ has a potential that increases because of the charging even though its inclination differs with respect to the rise of the power supply voltage VDD. In  FIG. 5 , the potential obtained by subtracting the potential V N4  of the node N 4 ′ from VDD (VDD V N4 ) between point A and point B is the gate-source voltage Vgs of the transistor M 5 ′. Consequently, a potential difference of V N4  arises between the gate-source voltage Vgs of the transistor M 5 ′ (referred to as Vgs 5 ) and the gate-source voltage Vgs of the transistor M 7 ′ (referred to as Vgs 7 ). 
         [0008]    It is known that the drain current in the weak inversion region of the transistor M 7 ′ has the characteristic that it increases exponentially with respect to an increase in the gate-source voltage Vgs. For that reason, the difference between the gate-source voltage Vgs 7  of the transistor M 7 ′ (=VDD) and the gate-source voltage Vgs 5  of the transistor M 5 ′ (=VDD−V N4 ) is important with respect to the application of the start-up current of the constant current circuit. The period of application of the start-up current of the conventional constant current circuit described above is a period from when the rise of the power supply voltage VDD exceeds point A (the point when the constant current circuit starts operating) in  FIG. 5  to until the power supply voltage VDD exceeds the threshold voltage Vt of the transistor M 7 ′ and the node N 4 ′ is charged to the potential of the power supply voltage VDD by the drain current in the strong inversion region. Supply of the start-up current is complete when this period elapses. Consequently, since the gate-source voltage Vgs 5  of the transistor M 5 ′ depends on the potential V N4  of the node N 4 ′ in the conventional current circuit described above, it is not clear whether or not the gate-source voltage Vgs 5  of the transistor M 5 ′, compared to the gate-source voltage Vgs 7  of the transistor M 7 ′, has reached the voltage Vgs that passes the start-up current of the constant current circuit between the period of point A to point B. 
         [0009]    Further, since the start-up current stops at a voltage of VDD exceeding the threshold voltage Vt of the transistor M 7 ′ in the conventional constant current circuit, it is not clear whether or not the start-up current has been supplied sufficiently to the constant current circuit and the constant current circuit is in a stable operating state. Moreover, it is necessary for VDD when the start-up current flows into the constant current circuit to be a potential at which the transistor M 4 ′ of the constant current circuit enters the operating point (potential at which the constant current circuit can operate) and which can hold current, but the start-up current cannot be passed to the constant current circuit in a stable state in which the transistor M 4 ′ can operate. 
       SUMMARY 
       [0010]    The present invention has been proposed in consideration of the above and provides a semiconductor integrated circuit that may start up a constant current circuit more stably and may reliably operate in normal state the constant current circuit after start-up. 
         [0011]    One aspect of the present invention is a semiconductor integrated circuit including: a constant current circuit including: a first current mirror circuit including a first transistor and a second transistor; and a second current mirror circuit including a third transistor that is connected to a first node into which current from the first transistor flows, and including a fourth transistor that is connected to a second node into which current from the second transistor flows; and a start-up circuit including: a fifth transistor that supplies start-up current to the constant current circuit via the second node; a sixth transistor that uses a potential of the first node as a control voltage; a seventh transistor that is connected to a third node into which current from the sixth transistor flows and that has a diode-connected configuration; a capacitor that is connected to a fourth node into which current from the seventh transistor flows; and a latch circuit that drives and controls the fifth transistor in accordance with an increase in a potential of the fourth node. 
         [0012]    According to this aspect, the transistors of the constant current circuit may be operated in a stable state to start up the constant current circuit, and the constant current circuit after start-up may be operated reliably. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    An exemplary embodiment of the present invention will be described in detail based on the following figures, wherein: 
           [0014]      FIG. 1  is a circuit diagram illustrating the configuration of a semiconductor integrated circuit pertaining to the embodiment; 
           [0015]      FIG. 2  is a drawing schematically illustrating a change in voltage during power-up of the semiconductor integrated circuit pertaining to the embodiment; 
           [0016]      FIG. 3A  and  FIG. 3B  are drawings for describing an inverter configuring a latch circuit of the semiconductor integrated circuit pertaining to the embodiment; 
           [0017]      FIG. 4  is a circuit diagram illustrating the configuration of a conventional semiconductor integrated circuit; and 
           [0018]      FIG. 5  is a drawing schematically illustrating a change in voltage during power-up of the conventional semiconductor integrated circuit. 
       
    
    
     DETAILED DESCRIPTION 
       [0019]      FIG. 1  is a circuit diagram illustrating the configuration of a semiconductor integrated circuit  10  pertaining to an embodiment of the present invention. As illustrated in  FIG. 1 , the semiconductor integrated circuit  10  is equipped with a constant current circuit  12  and a start-up circuit  14 . The start-up circuit  14  includes a latch circuit  105  that will be described below. Further, a power supply voltage VDD (hereinafter also called a first voltage) of 1 V, for example, and a ground voltage GND (hereinafter also called a second voltage) that is lower than the first voltage are supplied by an unillustrated power supply to the semiconductor integrated circuit  10 . 
         [0020]    The constant current circuit  12  includes a first current mirror circuit  101 , a second current mirror circuit  102 , and a resistor R 1 . The first current mirror circuit  101  is configured by two first electrically conductive transistors (e.g., P-channel MOS transistors) M 1  and M 2 . The P-channel MOS transistors M 1  and M 2  are configured by gate electrodes G (called control electrodes), source electrodes S (called first electrodes), and drain electrodes D (called second electrodes). The gate electrodes G of the transistor M 1  and the transistor M 2  are interconnected, and the gate electrode G and the drain electrode D of the transistor M 1  are connected (shorted). The drain electrode D of the transistor M 1  is connected to a first node N 1 , and the drain electrode D of the transistor M 2  is connected to a second node N 2 . The power supply voltage VDD that is the first voltage is supplied to the source electrodes S of the transistor M 1  and the transistor M 2 . 
         [0021]    The first current mirror circuit  101  becomes non-conductive when a voltage of the first voltage level is supplied to the interconnected gate electrodes G of the transistor M 1  and the transistor M 2  and becomes conductive when a voltage of the second voltage level is supplied. 
         [0022]    The second current mirror circuit  102  is configured by two second electrically conductive transistors (e.g., N-channel MOS transistors) M 3  and M 4 . The N-channel MOS transistors M 3  and M 4  are configured by gate electrodes G (called control electrodes), source electrodes S (called first electrodes), and drain electrodes D (called second electrodes). The gate electrodes G of the transistor M 3  and the transistor M 4  are interconnected. The source electrode S of the transistor M 3  is connected to one terminal of the resistor R 1 , and the drain electrode D of the transistor M 3  is connected to the first node N 1 . The gate electrode G and the drain electrode D of the transistor M 4  are connected (shorted). The drain electrode D of the transistor M 4  is connected to the second node N 2 , and the ground voltage GND that is lower than the first voltage is supplied to the source electrode S of the transistor M 4 . 
         [0023]    The second voltage—that is, the ground voltage GND—is supplied to the other terminal of the resistor R 1 . The current flowing in the first node N 1  and the second node N 2  is determined by the current gain of the second current mirror circuit  102  and depends on the resistor R 1 . The second current mirror circuit  102  becomes conductive when a voltage of the first voltage level is supplied to the interconnected gate electrodes G of the transistor M 3  and the transistor M 4  and becomes non-conductive when a voltage of the second voltage level is supplied. 
         [0024]    The start-up circuit  14  is configured by a P-channel MOS transistor M 5 , a P-channel MOS transistor M 6 , a P-channel MOS transistor  7  whose gate electrode G and drain electrode D are connected (shorted), a capacitor C 1 , and the latch circuit  105 . The gate electrode of the transistor M 7  and one terminal of the capacitor C 1  are connected to a node N 4 , and the ground voltage GND (the second voltage) is supplied to the other terminal of the capacitor C 1 . 
         [0025]    The latch circuit  105  is configured by an inverter T 1  and a P-channel MOS transistor M 8 . The input end of the inverter T 1  is connected to the node N 4 , and the output end of the inverter T 1  and the gate terminal G of the transistor M 8  are connected via a node N 5 . The drain electrode D of the transistor M 8  is connected to the gate electrode G of the transistor M 5  and is also connected to the input end of the inverter T 1 . The threshold voltage Vt of the transistor M 8  is set to the same value as the threshold voltage Vt of the transistor M 7 . Further, the threshold voltage of the inverter T 1  is set in such a way that the inverter T 1  recognizes it as a logical “L” (Low) when the power supply voltage VDD of the transistor M 7  has risen to the same potential as the threshold voltage Vt. 
         [0026]    The drain electrode D of the transistor M 5  is connected to the node N 2 . The gate electrode of the transistor M 6  is connected to the gate electrodes G (which are also the node N 1 ) of the transistor M 1  and the transistor M 2  configuring the first current mirror circuit  101 , so that the transistor M 1  and the transistor M 6  configure a current mirror circuit. The power supply voltage VDD is supplied to the source electrode S of the transistor M 6 , and the drain electrode D of the transistor M 6  is connected to a node N 3 . The source electrode S of the transistor M 7  is connected to the node N 3 , and the drain electrode D of the transistor M 7  is connected to the node N 4 . The transistors M 5  and M 6  become non-conductive when a voltage of the first voltage level is supplied to their gate electrodes G as a control voltage, and become conductive when a voltage of the second voltage level is supplied to their gate electrodes G. 
         [0027]    The threshold voltages Vt of the transistors configuring the semiconductor integrated circuit  10  are set such that the transistors M 7  and M 8  have threshold voltages Vt that are larger than the threshold voltages Vt of the transistors M 1 , M 2 , M 5 , and M 6 , and that the transistors M 7  and M 8  have threshold voltages Vt that are larger in absolute value than the threshold voltages Vt of the transistors M 3  and M 4 . For example, the threshold voltages Vt of the transistors M 1 , M 2 , etc. may be 0.5 V, and the threshold voltages Vt of the transistors M 7  and M 8  may be 0.9 V. 
         [0028]    Next, the operation of the semiconductor integrated circuit  10  of the present embodiment will be described. During power-up of the semiconductor integrated circuit  10 , the voltage level of the node N 1  is substantially that of the power supply voltage VDD (the first voltage level), and since a voltage of the same potential as that of the node N 1  is supplied to the gate electrode G of the transistor M 6 , the transistor M 6  is in a non-conductive state. Further, the node N 2  has a voltage level of substantially the ground voltage GND (the second voltage level), and the node N 4  is at a voltage level of substantially the ground voltage GND. Thus, the output of the inverter T 1  of the latch circuit  105  to which the voltage of the logical “L” level has been inputted will be a logical “H” (High), and the transistor M 8  in the latch circuit  105  becomes non-conductive. 
         [0029]    As a result, the voltage level of the node N 4 —that is, a voltage level of substantially the ground voltage GND—is supplied as a control voltage to the gate electrode G of the transistor M 5 . Therefore, the transistor MS becomes conductive and current flows to the node N 2  via the transistor M 5 . Because of this, the voltage level of the node N 2  rises, and the transistor M 3  and the transistor M 4  of the second current mirror circuit  102  become conductive. 
         [0030]    As the transistors M 3  and M 4  being in a conductive state, current flows to the node N 1  and the voltage level of the node N 1  falls. When the voltage level of the node N 1  falls to the level of the ground voltage GND, the transistor M 1  and the transistor M 2  of the first current mirror circuit  101  become conductive. Thus, current flows to the node N 1  via the transistor M 1 , and current flows to the node N 2  via the transistor M 2 . At this time, the transistor M 6  is in a non-conductive state, but the capacitor C 1  is charged by the current in the sub-threshold region of the transistor M 6  (leak current flowing between the source and drain when the gate voltage of the transistor M 6  is equal to or less than the threshold voltage Vt) and the sub-threshold current flowing out from the transistor M 7 . As a result, the voltage level of the node N 4  gradually rises as indicated by line segment a-b in  FIG. 2 . 
         [0031]    Meanwhile, the voltage level applied to the gate electrode G of the transistor M 6  of the start-up circuit  14  also falls because of the drop in the voltage level of the node N 1 . When the voltage level of the node N 1  falls to the ground voltage GND, the transistor M 6  becomes conductive, current flows to the node N 4  via the transistor M 6  and the transistor M 7  that is diode-connected, and the electric charge stored in the capacitor C 1  gradually increases because of that current. That is, in accompaniment with the rise in the power supply voltage VDD, the voltage level of the drain electrode D of the transistor M 7  that is diode-connected rises following the power supply voltage VDD while remaining dropped by the threshold voltage Vt of the transistor M 7  from the power supply voltage VDD as indicated by line segment b-c in  FIG. 2  for example. This is because the gate-source voltage (Vgs) of the transistor M 7  does not exceed the threshold voltage Vt because the transistor M 7  is diode-connected. Therefore, the gate-source voltage Vgs of the transistor M 5  (written as Vgs 5 ) and the gate-source voltage of the transistor M 7  Vgs (written as Vgs 7 ) become structurally the same, and the gate-source voltage Vgs 5  also rises with the potential remaining lower by a constant value than the rise in the power supply voltage VDD. Thus, the on-current (start-up current) of the transistor MS is larger than the on-current of the transistor M 7 . 
         [0032]    Because of the charging of the capacitor C 1 , when the potential of the node N 4  rises until the inverter T 1  of the latch circuit  105  recognizes the potential of the node N 4  as the logical “H” (point c in  FIG. 2 ), the output of the inverter T 1  inverts from the logical “H” to the logical “L”. The transistor M 8  in the latch circuit  105  receives the inverted voltage of the inverter T 1  and becomes conductive. As a result, the potential of the node N 4  and the power supply voltage VDD match (point d in  FIG. 2 ), the transistor M 5  of the start-up circuit  14  becomes non-conductive, and supply of the start-up current with respect to the constant current circuit  12  is complete. Even though the transistor M 5  becomes non-conductive, current is already flowing to the node N 1  and the node N 2 , so the constant current circuit  12  will stably operate. 
         [0033]    Given that gm 1 , gm 2 , gm 3 , and gm 4  represent the mutual conductance gin of the transistors M 1 , M 2 , M 3 , and M 4 , respectively, the current I 1  flowing through the node N 1  and the current  12  flowing through the node N 2  are expressed as follows: 
         [0000]        I 1 =k*T/q*{ 1 n ( gm 1 *gm 2 /gm 3 *gm 4)} 
         [0000]        I 2 =gm 2 /gm 1* I 1 
         [0034]    where k is the Boltzmann constant, T is absolute temperature, q is electron charge quantity, and * is a multiplication symbol. 
         [0035]    Next, the function of the latch circuit  105  provided in the start-up circuit  14  will be described. During the period in which the capacitor C 1  is being charged, current flows into the capacitor C 1 , whereby the node N 4  has a potential remaining lower by the threshold voltage Vt of the transistor M 7  than that of the power supply voltage VDD as described above. If the latch circuit  105  is not provided in the start-up circuit  14 , since the potential level of the node N 4  is substantially the power supply voltage VDD in a state in which charging of the capacitor C 1  has been complete, for example, when the source potential VSS (here, the ground voltage GND) fluctuates, the potential fluctuation travels to the node N 4  via the capacitor C 1 . The transistor M 7  is difficult to absorb the potential fluctuation with respect to the power supply voltage VDD since the gate-source voltage Vgs of the transistor M 7  is small. As a result, the voltage level of the gate electrode G of the transistor M 5  drops from the power supply voltage VDD, and the transistor M 5  that should be in a non-conductive state becomes conductive and unexpected current flows into the constant current circuit  12 . 
         [0036]    However, in the semiconductor integrated circuit  10  pertaining to the present embodiment which includes the latch circuit  105 , even if the potential of the node N 4  rises with the potential remaining lower by the threshold voltage Vt of the transistor M 7  than that of the power supply voltage VDD, the output of the inverter T 1  becomes the logical “L” at the time when the input level of the inverter T 1  of the latch circuit  105  disposed in the start-up circuit  14  is recognized as the logical “H” with respect to the level of the rising power supply voltage VDD, and the transistor M 8  in the latch circuit  105  strongly maintains the potential of the node N 4  at the level of the power supply voltage VDD. As a result, even if there is a fluctuation in the source potential VSS or the like, the voltage level of the gate electrode G of the transistor M 5  does not drop from the power supply voltage VDD, the non-conductive state of the transistor M 5  is maintained, and the constant current circuit  12  may be operated in a normal state. 
         [0037]    Further, as illustrated in  FIG. 3A  for example, the inverter T 1  of the latch circuit  105  is configured by connecting the drain electrode D of a P-channel MOS transistor M 31  to the drain electrode D of an N-channel MOS transistor M 32 . The power supply voltage VDD is supplied to the source electrode S of the transistor M 31 , and the ground voltage GND is supplied to the source electrode S of the transistor M 32 . The gate electrodes G of the transistors M 31  and M 32  are interconnected, and this point of connection being used as the input terminal of the inverter T 1  and the interconnected drain electrodes D being used as the output terminal of the inverter T 1 . 
         [0038]      FIG. 3B  illustrates the input/output characteristic of the inverter T 1  illustrated in  FIG. 3A . The input voltage (Vin) input to the interconnected gate electrodes G of the transistors M 31  and M 32  and the output voltage (Vout) from the interconnected drain electrodes D have a relationship in which their logical values (logical “H” and logical “L”) are inverted from each other. Here, the threshold voltage Vt 31  of the transistor M 31  is set lower than the threshold voltage Vt 32  of the transistor M 32 , or, the mutual conductance gm 31  of the transistor M 31  is set higher than the mutual conductance gm 32  of the transistor M 32 . In this way, the input voltage (Vin) that the inverter T 1  recognizes as the logical “H” is raised. That is, by raising the input voltage with which the output voltage of the inverter T 1  becomes the logical “L” (by changing Vin 1  to Vin 2  as illustrated in  FIG. 3B ), the range of the output that becomes the logical “H” of the inverter T 1  is expanded. Here, during power-up of the semiconductor integrated circuit  10 , the inverter T 1  is set to recognize that potential as the logical “L” when the power supply voltage VDD of the transistor M 7  has risen to the same potential as the threshold voltage Vt. 
         [0039]    As described above, the semiconductor integrated circuit pertaining to the present embodiment applies a control voltage of a start-up transistor that supplies a start-up current to a constant current circuit, which is a voltage that rises following a power supply voltage VDD while being dropped from the power supply voltage VDD by a threshold voltage Vt of a transistor that is diode-connected, and the semiconductor integrated circuit supplies the start-up current from the start-up transistor to the constant current circuit. Further, when the voltage applied to the start-up transistor has risen up to a level which a latch circuit including an inverter and a transistor recognizes it as the logical “H”, the output from the inverter is inverted from the logical “H” to the logical “L.” In this way, the rise in the control voltage applied to the start-up transistor that supplies the start-up current to the constant current circuit is delayed, and the start-up transistor may be avoided from being in a non-conductive state before supplying a sufficient start-up current to the constant current circuit. 
         [0040]    Further, by inverting the inverter output to the logical “L” when the voltage applied to the start-up transistor has risen until it is recognized as the logical “H” by the latch circuit, and using the output of the transistor in the latch circuit that has switched on because of that as the control voltage of the start-up transistor that supplies the start-up current to the constant current circuit, the control voltage applied to the start-up transistor is strongly held at the level of the power supply voltage VDD by the transistor in the latch circuit so that the non-conductive state of the start-up transistor is maintained, and unnecessary current may be prevented from flowing into the constant current circuit so that the constant current circuit may be operated reliably in a normal state. 
         [0041]    Moreover, by setting the threshold voltage Vt of the transistor M 8  configuring the latch circuit  105  to be the same as the threshold voltage Vt of the transistor M 7  that is diode-connected, the high-temperature leak current and the sub-threshold current of the transistor M 8  may be made smaller compared to those of the transistor M 7 . 
         [0042]    In the semiconductor integrated circuit pertaining to the above embodiment, an example has been described in which the on-current of the transistor M 5  is made larger than the on-current of the transistor M 7  by setting the threshold voltage Vt of the P-channel MOS transistor M 7  higher than the threshold voltage Vt of the P-channel MOS transistor M 5 , but embodiments are not limited to this. For example, the on-current of the transistor M 5  may also be made larger than the on-current of the transistor M 7  by making the mutual conductance gm 7  of the P-channel MOS transistor M 7  smaller than the mutual conductance gm 5  of the P-channel MOS transistor M 5 . 
         [0043]    Further, the capacitor C 1  connected to the node N 4  in the semiconductor integrated circuit pertaining to the above embodiment has been described as an element built into the semiconductor integrated circuit. However, embodiments are not limited to this and the capacitor C 1  may also be a capacitor that is externally connectable to an outside terminal disposed in correspondence to the node N 4  and the ground voltage GND. By making the capacitor C 1  externally connectable, it is possible to lengthen the delay time of the potential rise in the node N 4  by changing the capacitance of the capacitor C 1  to various values (e.g., by changing a capacitance of several picofarads to several microfarads). 
         [0044]    Moreover, the start-up circuit  14  of the semiconductor integrated circuit  10  pertaining to the above embodiment may also be given a configuration in which, instead of the capacitor C 1 , a resistor is connected to the node N 4  and the rising voltage resulting from the current flowing in that resistor is inputted to the latch circuit  105  to control the transistor M 5 .