Abstract:
A regulator circuit including output loading sense circuitry where the output loading sense circuitry comprises, in one example, a resistor in the feedback leg of the replica bias regulator, a switch in the feedback leg of the replica bias regulator for bypassing the resistor, and a comparator used to sense the output loading and selectively drive the switch.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
   This application claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 60/527,150 entitled “Replica Bias Regulator with Sense-Switched Load Regulation Control” filed Dec. 5, 2003, the disclosure of which is hereby incorporated by reference in its entirety. 

   FIELD OF THE INVENTION 
   The present invention relates generally to electronic circuits and in particular to circuits for replica bias regulation. 
   BACKGROUND OF THE INVENTION 
   A replica bias regulator is a regulator that isolates the output of the regulator from the feedback loop of the regulator. This is done to ensure stability of the feedback loop of the overall regulator. If the output node was in the loop, the loop could become unstable due to widely varying and unpredictable currents drawn by the load. The output voltage is then designed to be a replica (copy) of the voltage formed in the feedback loop that does not have varying current. 
   A conventional replica bias regulator  10  is shown in  FIG. 1  and comprises a simple replica bias regulator that has no adjustment for load regulation. In the conventional replica bias regulator of  FIG. 1 , the output signal (Vout) is taken from a replica output that is not connected in the feedback loop, thus isolating the output capacitance and load current from the feedback loop and ensuring stability of the overall circuit. As recognized by the present inventor, the problem with this architecture is the large load regulation that results from the change in voltage at this node due to a change in current. The output voltage drops as more current is pulled from the output. With large ranges of output currents, this architecture may not meet the output voltage requirements for all desired operating conditions. This phenomena is illustrated in  FIG. 2 . 
     FIG. 2  shows the output waveform with respect to load current of the conventional replica bias regulator for  FIG. 1 . The graph shows the output voltage (Vout) falling as the output current (Iout) increases. This is due to the increased gate-source voltage (Vgs) of the output transistor M 2  required to supply the load current. Also shown is the line indicating the source voltage of transistor M 1 . This is the reference voltage set by feedback. The output waveform Vout moves around this reference/source voltage of M 1  depending on the load current. The lower dashed horizontal line  12  represents the lower specified limit of Vout for the application. As the graph shows with the line  12 , there is a maximum Iout that can be sourced before the output signal Vout falls below the specified limit across line  12 . Conversely, if the output current drops (i.e., during a sleep mode or other low current mode), then the Vout signal rises above the specified limit shown by line  14 . 
   One solution for this problem is to increase the size of the output transistor M 2  to allow more current drive. However, when doing this, a new problem is created. The larger the transistor M 2 , the more sub-threshold current it sinks. This will cause the output to drift upward above the upper specification limit when very little or zero current is required from the regulator. This range of problems effects applications where large ranges of current are required such as those with standby modes and active modes. 
   As recognized by the present inventor, what is needed is a replica bias regulator that provides an output voltage characteristic that stays within the specified limits for all possible load currents that the regulator will have to supply. 
   It is against this background that various embodiments of the present invention were developed. 
   SUMMARY 
   In light of the above and according to one broad aspect of one embodiment of the present invention, disclosed herein is a circuit including a replica bias regulator having a feedback leg and an output voltage and output loading sense circuitry. In one example, the output loading sense circuitry may include a resistor in the feedback leg of the replica bias regulator; a switch in the feedback leg of the replica bias regulator, the switch for selectively bypassing the resistor; and a comparator used to sense the output voltage and selectively drive the switch. 
   In one example, when the output voltage is drifting high, the comparator is on and drives the switch closed which bypasses the resistor, thereby removing the resistor from the feedback leg. In another example, when the output voltage is drifting low, the comparator is off and the switch is open which maintains the resistor in the feedback leg. 
   In one embodiment, the replica bias regulator includes at least a pair of n-channel transistors. The comparator may include internal hysteresis. In one example, the replica bias regulator includes an error amplifier comparing a reference signal to a feedback signal and providing an output. 
   In another example, the replica bias regulator may include a first transistor having a drain coupled with a supply, a drain receiving the output of the error amplifier, and a source coupled with the switch. The switch may be an n-channel transistor. The feedback circuit may include at least one resistor when the switch is on, and in another example, the feedback circuit may include at least two resistors when the switch is off. 
   According to another broad aspect of another embodiment of the present invention, disclosed herein is a method of performing load regulation in a circuit. In one example, the method includes sensing a level of an output load current; and in response to the sensing operation, altering a feedback resistance in the replica bias circuit. 
   In one example, the altering operation may include bypassing a portion of the feedback resistance if the output load current is low, including a portion of the feedback resistance if the output load current is high. 
   According to another broad aspect of another embodiment of the present invention, disclosed herein is a circuit for performing load regulation of an output, comprising means for sensing a level of an output load current; and means for altering a feedback resistance in a replica bias circuit responsive to the sensing means. In one example, the means for altering may include means for bypassing a portion of the feedback resistance if the output load current is low, or may include means for including a portion of the feedback resistance if the output load current is high. The means for bypassing may include a comparator coupled with a switch. 
   The features, utilities and advantages of the various embodiments of the invention will be apparent from the following more particular description of embodiments of the invention as illustrated in the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a conventional replica bias regulator. 
       FIG. 2  is an output load regulation waveform of the conventional replica bias regulator of  FIG. 1 . 
       FIG. 3  is an example of a replica bias regulator in accordance with one embodiment of the present invention. 
       FIG. 4  is an example of an output load regulation waveform of the replica bias regulator of  FIG. 3 , in accordance with an embodiment of the present invention. 
   

   DETAILED DESCRIPTION 
   An example of an improved replica bias regulator  20  is shown in  FIG. 3  in accordance with one embodiment of the present invention. This improved replica bias regulator includes circuitry to increase the range of load current the regulator can handle while staying within output voltage specification requirements. Various embodiments of the present invention will now be described. 
   In the example of  FIG. 3 , N-channel transistors M 1  and M 2  each have their drains coupled with a supply Vpwr and the gates of both transistors M 1  and M 2  are coupled with the output of amplifier AMP 1  (i.e., an error amplifier). Amplifier AMP 1  receives at its input a reference voltage, as well as a signal derived from the series combination of resistors R 2 , R 1  which are coupled between the source of transistor M 1  and ground. The source of transistor M 2  is coupled with the load, and the source of transistor M 2  provides the output voltage shown as Vout. 
   Further, resistor R 3  is coupled between the source of transistor M 1  and resistor R 2 . Amplifier AMP 2  (i.e. a comparator or differential amplifier) has its non-inverting input coupled with the output voltage VOUT (which is the source voltage of transistor M 2  across the load). The inverting input of amplifier AMP 2  is coupled with the source of transistor M 1 , as well as the drain of N-channel MOSFET switch Msw which provides a switch between R 2  to the source of transistor M 1 . The gate of transistor Msw is coupled with the output of amplifier/comparator AMP 2 . Comparator AMP 2  may be provided with internal hysteresis if desired. 
   A feedback loop is formed including resistors R 1 , R 2 , R 3  and transistor M 1 , and switch Msw. When Msw is activated, this alters the feedback loop as resistor R 3  is controllably removed from the feedback loop by Msw. In this way, resistor R 3 , comparator AMP 2  and a MOSFET switch Msw provide the replica bias regulator with a greater output load current range while maintaining the overall output voltage Vout within specified operational limits. 
   As to the upper limit of output voltage, the output of the reference transistor M 1  can be set to a lower voltage thereby setting the gate of the replica transistor M 2  to a lower voltage. This keeps the output voltage Vout from exceeding the upper specification limit when small amounts of current are drawn by the load. 
   Specifically, for low values of current drawn from the regulator in  FIG. 3 , Vout is a higher voltage than the source of M 1 . When Vout is higher than the source voltage of transistor M 1 , resistor R 3  is shorted or bypassed so that the voltage across R 3  is approximately 0V. The resulting feedback action of the error amplifier forces the voltage at the source of M 1  to be at a value which forces the gate voltage of M 1  and M 2  to be low enough to prevent Vout from being pulled up beyond the upper specified limit. 
   When significant current is drawn from the regulator, Vout will be pulled low, eventually dropping below the voltage at the source of transistor M 1 . When this happens, resistor R 3  is connected in series with resistors R 2  and R 1  causing the feedback to raise the gate voltage of transistors M 1  and M 2 . The rise in gate voltage then allows more current to be drawn from Vout before it falls below its specified lower limit. 
     FIG. 4  shows an example waveform of the output Vout of the circuit of  FIG. 3  with respect to load current Iout. In effect, for low output currents (such as during a sleep mode or other low current mode), the circuit of  FIG. 3  shifts the Vout waveform downwardly so that Vout does not exceed the upper specification limit. Stated differently, when a low amount of current Iout is being pulled from the output node, the output voltage Vout climbs towards the upper specification limit as shown in  FIG. 4 . When the Vout node voltage is higher than the voltage at the source of transistor M 1 , the comparator AMP 2  turns on and switch Msw turns on effectively shorting or bypassing resistor R 3 . In this mode, the feedback loop of the circuit including the error amplifier AMP 1 , transistor M 1 , resistors R 1 , R 2  will then force the source voltage of M 1  to a lower voltage. This will in turn force the gate voltage of M 1  and M 2  to a lower voltage which will prevent the output node voltage Vout from drifting above the upper specification limit. Now, as an increasing load current is pulled from the output, it will reach a point where the Vout node voltage drops below the source voltage of M 1 . When this occurs, the comparator AMP 2  switches turning off Msw which introduces resistor R 3  into the feedback loop. This causes the source voltage of M 1  and the gate voltage of M 1  and M 2  to shift upward, which thereby shifts the output voltage upward adding margin to the lower specification limit. Hence, in one example. this process has built in hysteresis. The hysteresis occurs because when R 3  is either switched in or out, the feedback action of the loop pulls all node voltages in a direction that aids in the switching process. 
   Hence, it can be seen that a replica bias regulator made according to embodiments of the present invention can effectively provide greater currents to loads while maintaining the output voltage Vout within acceptable operating ranges. The extended output current range allows the regulator to be used in applications that require little or no current during a standby condition, and large currents in an active condition. 
   The hysterisis of an embodiment of the invention is advantageous because it adds noise immunity to the loop comprising the comparator. In one example, the hysteresis arises from the source of M 1  also being pulled upward when resistor R 3  is switched in by Msw. This increases the margin between the source of M 1  and Vout and keeps R 3  switched in. 
   An alternate solution that can be constructed using this method is to add multiple resistors, switches, or comparators in series with R 1  and R 2  allowing multiple switching points. This will allow smaller output transistors to be used. 
   In alternate embodiments, the switch Msw can be replaced with any type of switch device. In another alternate embodiment, the comparator can be any type of comparator including conventional comparators, and the resistor R 3  can be replaced with any device that can be operated as a resistor such as a transistor or any device that can force a voltage drop to occur. Another alternate embodiment is to remove the comparator and switch the gate of Msw with a standby enable signal which would be high during a standby condition and low during an active condition. 
   Embodiments of the present invention may be used in various semiconductors, memories, processors, controllers, integrated circuits, logic or programmable logic, clock circuits, communications devices, and the like. 
   It is understood that the term “transistor” or “switch” as used herein includes any switching element which can include, for example, n-channel or p-channel CMOS transistors, MOSFETs, FETs, JFETS, BJTs, or other like switching element or device. The particular type of switching element used is a matter of choice depending on the particular application of the circuit, and may be based on factors such as power consumption limits, response time, noise immunity, fabrication considerations, etc. Hence while embodiments of the present invention are described in terms of p-channel and n-channel transistors, it is understood that other switching devices can be used, or that the invention may be implemented using the complementary transistor types. 
   While the methods disclosed herein have been described and shown with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form equivalent methods without departing from the teachings of the present invention. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present invention. 
   It should be appreciated that reference throughout this specification to “one embodiment” or “an embodiment” or “one example” or “an example” means that a particular feature, structure or characteristic described in connection with the embodiment may be included, if desired, in at least one embodiment of the present invention. Therefore, it should be appreciated that two or more references to “an embodiment” or “one embodiment” or “an alternative embodiment” or “one example” or “an example” in various portions of this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined as desired in one or more embodiments of the invention. 
   Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed inventions require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment, and each embodiment described herein may contain more than one inventive feature. 
   While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various other changes in the form and details may be made without departing from the spirit and scope of the invention.