Abstract:
An electrostatic discharge protection network comprising electrostatic discharge (ESD) clamp devices distributed between turns of a coil shaped inductor. The inductance of the coil shaped inductor and parasitic capacitance of the ESD clamp devices form a low pass filter structure having a very high cut-off frequency. Below the low pass filter cutoff frequency, the capacitive influence of the ESD clamp devices are cancelled by the series inductance of the coil shaped inductor. The turns of the coil shaped inductor may be fabricated on insulation layers proximate to one another so as to achieve close magnetic coupling there between, thereby achieving a larger inductance value for a given sized coil structure. Improved input and output impedance matching is also achieved by adjusting the inductive and capacitive components of the low pass filter structure formed by the coil shaped inductor and capacitance of the ESD clamp devices.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to electronic circuits and systems sensitive to electrostatic discharge, and more particularly, to a distributed electrostatic discharge protection network for these electronic circuits and systems operating at radio frequencies. 
     2. Description of the Related Technology 
     Electrostatic charge was discovered by the early Greeks and was a novelty until electricity became better understood and more widely used. An electrostatic charge potential may become so large that the insulation medium between the positive and negative charges breaks down. This break down results in what is called “electrostatic discharge” or “ESD.” Examples of minor and major ESD events are an electric spark from a metal door knob to one&#39;s finger after shuffling across a carpeted floor, and a lightning bolt between the earth and the clouds, respectively. Electrical and electronic devices and systems are sensitive to ESD because insulation breakdowns, caused by ESD, may seriously degrade the electrical performance characteristics of the device or system. Electrical power systems are protected from ESD (lightning) by protective devices having voltage break down characteristics that short out and dissipate the ESD event before it can damage the electrical system. 
     Electronic circuits and systems have become more susceptible to ESD damage as the circuit elements thereof have become smaller and the insulation thinner therebetween. During the era of vacuum tube technology, the vacuum tube&#39;s operating voltages were hundreds or even thousands of volts, and the spacing between the vacuum tube&#39;s elements were fractions of an inch. Today, devices (transistors and diodes) in very large scale integrated circuits typically operate at three to five volts and have element and insulation dimensions of thousandths of an inch (microns). With the micron element spacing of integrated circuit devices, even relatively small ESD events can be catastrophic. The electronics industry has addressed the ESD problem in various ways. One way is to add ESD protective devices into an electronic system so that ail input and output lines are clamped below an ESD voltage that would damage the integrated circuits. Using an added ESD protective device, however, does not prevent integrated circuit ESD damage before the protective device is connected to the integrated circuit. Integrated circuit manufacturers have thus tried to incorporate some form of ESD protection into the integrated circuits themselves. Various forms of ESD protective devices such as zener diodes, capacitors and other controlled break down or surge filtering devices have been used to protect integrated circuit input/output (“I/O”) lines and typically may be connected between the I/O lines and both power supply rails (V DD  and ground). These ESD protective devices, however, have a significant amount of parasitic capacitance (capacitance associated with the structure of the ESD device). This parasitic capacitance may degrade the high frequency signal performance of the I/O lines of the digital integrated circuit that are connected to the ESD protective devices. In addition, the ESD protective devices generally require series resistors, for example, of about 300 ohms in series with each signal path. This combination of significant parasitic capacitance and relatively high series resistance in each of the signal paths of the I/O lines may prevent or impair proper performance of high frequency signals, especially digital signals having very fast rising and falling transition levels, i.e., logic 0 to logic 1, and logic 1 to logic 0, respectively. 
     What is needed is a system, method and apparatus for electrostatic discharge protection which does not significantly degrade high frequency signal performance. 
     SUMMARY OF THE INVENTION 
     The present invention overcomes the above-identified problems as well as other shortcomings and deficiencies of existing technologies by providing a system, method and apparatus for electrostatic discharge protection which does not significantly degrade high frequency signal performance. The embodiments of the present invention provide an electrostatic discharge protection network comprising an inductor having at least one turn of a coil, and at least one ESD clamp device connected to the at least one turn of the coil. More than one coil turn may be associated with one ESD clamp device, and more than one ESD clamp device may be associated with one turn of the coil. It is contemplated and within the scope of the present invention that the inductor coil may be comprised of any shape or form, and the ESD clamp device may be, for example but not limitation, a semiconductor device, a gas discharge device, a zener device, metal oxide varistor, avalanche or tunnel diode, or any other type of voltage limiting device. 
     The inductor portion of the embodiments of the present invention is connected in series between an electronic circuit node being protected and an external signal node which is subject to an ESD event. The ESD clamp device(s) may be connected to the inductor, preferably at each turn of the inductor coil, and to one or both of the common power supply rails. One of the common power supply rails may be at earth ground potential. In addition, it is contemplated and within the scope of the present invention that some of the ESD clamp devices may also be connected between one or more turns of the inductor coil and earth ground. 
     In the embodiments of the present invention, the series connected inductor coil and parallel or shunt connected ESD clamp devices, having parasitic capacitance associated therewith, form cascaded “π” sections of a low pass filter network. The series inductance of the inductor coil preferably cancels out the shunt capacitance of the ESD clamp device(s) connected thereto for signal frequencies below the low pass filter cutoff frequency. Efficient impedance matching for low impedance signal nodes may be accomplished by appropriate selection of inductance and capacitance values for the ESD network of the present invention. 
     According to an embodiment of the present invention, the ESD protection network is fabricated on a semiconductor integrated circuit substrate, a plurality of turns of a coil are formed from a plurality of conductive layers with a plurality of insulation layers interleaved therebetween. Each one of the plurality of insulation layers having a one of the plurality of conductive layers (forming each coil turn) thereon. Vias are formed in each of the plurality of insulation layers, and conductive material is deposited therein for connecting the plurality of coil turns together to form the inductor. The ESD clamp devices may be formed on each of the insulation layers and attached to the conductive layer coil turns on the insulation layers, or the ESD clamp devices may be formed in the semiconductor substrate as P and N junction wells with connection to the plurality of coil turns made through conductive vias in the various insulation layers on which the conductive layer coil turns are formed thereon. 
     According to another embodiment of the invention, the ESD protection network is fabricated on a substrate made of insulation material such as ceramic, glass epoxy, a printed wiring board (PWB) and the like. A plurality of turns of a coil are formed on a plurality of insulation layers on the substrate. Each one of the plurality of insulation layers having a one of the plurality of the coil turns thereon. Vias are formed in each of the plurality of insulation layers, and conductive material is deposited therein for connecting the plurality of coil turns together to form the inductor. The ESD clamp devices may be formed or attached oil each of the insulation layers or the ESD clamp devices may be attached to the substrate with connection to the plurality of coil turns made through conductive vias in the various conductive layers the coil turns are formed therefrom. 
     According to still another embodiment of the present invention, the ESD protection network is fabricated on an non-conductive (insulation) printed circuit board using printed circuit stripline conductors and surface mounted components. The insulation portion of the printed circuit board may be, for example but not limitation, glass epoxy, TEFLON® (a registered trademark of Dupont Co.), ceramic, glass and the like. The printed circuit stripline enables a constant impedance for the signal path. A plurality of turns of a coil are formed on the printed circuit board in a concentric spiral configuration. A metalized via (plated through hole) is formed through the printed circuit board at each of the plurality of coil turns, or portions thereof, and an ESD clamp device is attached to each of these vias and a planar ground plane located on the face opposite the face on which the plurality of coil turns is located thereon. The ESD clamp devices may be connected to the vias and the planar ground plane preferably using surface mount techniques. The plurality of coil turns may be tapped with vias at points of the coil representing a desired inductance needed to cancel out the parasitic capacitance of the associated ESD clamp device. The outer or larger coil turn(s) may be tapped at less than 360 degrees, and the inner or smaller coil turns may be tapped at more than 360 degrees, i.e., a multiple turn. 
     According to the aforementioned embodiments of the present invention, the insulation layers between the coil turns of the inductor may preferably be very thin so that the turns of the coil are close together, thus, improving the magnetic coupling therebetween and increasing the effective inductance for a given size coil diameter. It is also contemplated and within the scope of the present invention that a material of high magnetic permeability may be used by locating same within the coil so as to further increase the effective inductance value for a give size of coil structure. This material may be, for example but not limitation, iron oxide, ferrite, or other materials that increase the effective inductance of the inductor coil. 
     An advantage of the present invention is that signal paths may be protected from an ESD event without causing significant attenuation or degradation of desired high frequency signals. 
     Another advantage is that parasitic capacitance of an ESD clamp device may be effectively canceled by a series connected inductance. 
     Still another advantage is attenuation of ESD frequencies above a desired low-pass filter cut-off frequency. 
     A feature of the present invention is fabricating a coil inductor on a semiconductor integrated circuit die by depositing each turn of the coil on a respective insulation layer and connecting the turns together with metalized vias through these respective insulation layers. 
     Another feature is using vias to connect an ESD clamp device to each turn of the inductor coil. 
     Still another feature is having a constant impedance signal path that protects against an ESD event without significant attenuation of desired signal frequencies. 
     Other and further features and advantages will be apparent from the following description of presently preferred embodiments of the invention, given for the purpose of disclosure and taken in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of a prior art ESD protective circuit; 
         FIG. 2  is a schematic diagram of an ESD protection circuit, according to the present invention; 
         FIG. 3  is a schematic orthogonal view of a coil portion of the invention; 
         FIG. 4  is a schematic elevational cross-section view of an ESD network fabricated on a semiconductor integrated circuit die; 
         FIG. 5  is a schematic elevational cross-section view of an ESD network fabricated on a substrate; 
         FIGS. 6 and 7  are a schematic plan view and an elevational view, respectively, of an ESD protection network fabricated on an non-conductive portion of the printed circuit board using printed circuit stripline conductors and surface mounted components; and 
         FIG. 8  is a schematic orthogonal view of the coil portion of  FIG. 3  and a core having magnetic properties to increase the inductance of the coil. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to  FIG. 1 , a schematic diagram of a prior art ESD protective circuit for an integrated circuit is illustrated. An external signal node  104  is adapted for connection to signal circuits external to the integrated circuit package (not illustrated). The external signal node  104  may be for input and/or output signals. An internal signal node  102  is adapted for connection to signal circuits internal to the integrated circuit package. A resistor  106  is connected in series between signal nodes  102  and  104 . The resistor  106  may be, for example, 300 ohms. The signal node  104  and the resistor  106  may be connected to ESD clamp devices  108  and  110 . The ESD clamp devices  108  and  110  may also be connected the an electronic system&#39;s power rails V DD  and V SS , respectively. The ESD clamp devices  108  and  110  limit transient voltages coming into signal node  102  to approximately the voltages of the power rails V DD  and V SS . A P-channel metal oxide semiconductor (PMOS) transistor and an N-channel metal oxide semiconductor (NMOS) transistor are illustrated for the ESD clamp devices  108  and  110 , respectively. 
     The ESD protection circuit illustrated in  FIG. 1  is effective but degrades the high frequency performance of desired signals because the ESD clamp devices  108  and  110  have inherent parasitic capacitance and when connected to the resistor  106  form a RC low pass filter that may cause significant attenuation of fast rising digital signals. In addition, impedance matching for optimum signal to noise ratio and/or power transfer is greatly affected when the external signal circuit impedance is much lower than the value of the resistor  106 , e.g., 50 ohms. The embodiments of the present invention eliminate the requirement for the series connected resistor  106  and effectively cancel out the undesirable parasitic capacitance at the desired signal frequencies. 
     The present invention is a system, method and apparatus for providing an electrostatic discharge protection network on an integrated circuit die, a monolithic substrate, and a printed circuit board with or without constant impedance stripline conductors. Embodiments of the invention comprise an inductor having at least one turn of a coil, and at least one ESD clamp device connected to the at least one turn of the coil. More than one coil turn may be associated with one ESD clamp device, and more than one ESD clamp device may be associated with one turn of the coil. It is contemplated and within the scope of the present invention that the inductor coil may be comprised of any shape or form, and the ESD clamp device may be, for example but not limitation, a semiconductor device, a gas discharge device, a zener device, metal oxide varistor, avalanche or tunnel diode, or any other type of transient voltage limiting device. 
     The inductor portion of the embodiments of the present invention is connected in series between an electronic circuit node being protected and an external signal node which is subject to an ESD event. The ESD clamp device(s) may be connected to the inductor, preferably at each turn of the inductor coil, and to one or both of the common power supply rails. One of the common power supply rails may be at earth ground potential. In addition, it is contemplated and within the scope of the present invention that some of the ESD clamp devices may also be connected between one or more turns of the inductor coil and earth ground. 
     Referring now to the drawings, the details of preferred embodiments of the present invention are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix. 
     Referring to  FIG. 2 , a schematic diagram of the ESD protection circuit of the embodiments of the invention is illustrated. The ESD protection circuit of the present invention is generally represented by the numeral  200  and has an external node  206  and an internal node  208 . The external node  206  is adapted for connection to circuits having desired signals with undesirable ESD events and the internal node  208  is adapted for connection to circuits needing protection from ESD events. Between the nodes  206  and  208 . The ESD protection circuit  200  comprises a series connected inductor  202  between the nodes  206  and  208 , wherein the inductor  202  has tapped portions  202   a ,  202   b ,  202   c  and  202   d . Parallel or shunt connected ESD clamp devices represented by their parasitic capacitance  204   a ,  204   b ,  202   c  and  204   d  are connected to respective inductor  202  tapped portions  202   a ,  202   b ,  202   c  and  202   d . The inductor  202  and ESD clamp parasitic capacitance  204  form cascaded “π” sections of a low pass filter network. The series inductance of the inductor coil  202  portions  202   a ,  202   b ,  202   c  and  202   d  preferably cancel out the shunt parasitic capacitance  204   a ,  204   b ,  202   c  and  204   d  of the ESD clamp device(s) connected thereto for signal frequencies below the low pass filter cutoff frequency. Appropriate selection of inductance  202  and capacitance  204  values for the ESD network  200  may also be used for efficient impedance matching of the signal nodes  206  and  208  to a source and load, respectively. 
     Referring now to  FIG. 3 , a schematic orthogonal view of an embodiment of the invention is illustrated. The ESD protection network  200  may be fabricated on a semiconductor integrated circuit substrate or any other type of substrate which has insulation thereon (not illustrated). The inductor  202  may be comprised of a plurality of turns formed from conductive layers that are coil shaped. These coil shaped conductive layers, illustrated in  FIG. 3  as coil turns  202   a ,  202   b  and  202   c , are formed on a plurality of insulation layers (not illustrated for clarity). Each coil shaped conductive layer is formed on a respective insulation layer (See  FIG. 4 ). Vias through the insulation layers are used to connect the different coil shaped conductive layers together by conductive connections therethrough (See  FIG. 4 ). The shape of the coil may be for example but not limitation, round, square, rectangle, triangle, oval, hexagon, octagon and the like. The conductive layer may be comprised of metal such as, for example but not limitation, copper, aluminum, copper alloy and aluminum alloy, or any other conductive material used in the fabrication of an integrated circuit, such as conductive doped polysilicon. 
     Referring now to  FIG. 4 , a schematic elevational cross-section view of the ESD network  200  fabricated on a semiconductor integrated circuit die is illustrated. An integrated circuit die, generally represented by the numeral  400 , comprises a substrate  410  having doped wells  412   a ,  412   b ,  412   c  and  412   d  in which ESD clamp devices have either or both PMOS and NMOS transistors formed therein. The PMOS and NMOS transistors of the ESD clamp devices may be connected to the power supply rails, V DD  and V SS , in a fashion similar to the PMOS and NMOS transistor connections illustrated in  FIG. 1 . 
     Insulation layer  414   d  is formed over the substrate  410  and wells  412   a ,  412   b ,  412   c  and  412   d . The insulation layer  414   d  may also be formed over other conducting and insulation layers proximate to the substrate  410 . The coil turn  202   d  is formed over the insulation layer  414   d . Similarly, insulation layers  414   c ,  414   b  and  414   a , and coil turns  202   c ,  202   b  and  202   a  are formed as illustrated in  FIG. 4 . Another insulation layer  416  may be formed over the coil turn  202   a  for additional circuitry or physical protection of the integrated circuit die. 
     The ESD clamp devices formed in the wells  412   a ,  412   b ,  412   c  and  412   d  may be connected to the coil turns  202   a ,  202   b ,  202   c  and  202   d , respectively, through conductive vias (holes) in the insulation layers  414   a ,  414   b ,  414   c  and  414   d . The vias are filled with a conductive material such as aluminum. As illustrated in  FIG. 4 , Vias  418   a  pass through insulation layers  414   d ,  414   c  and  414   b , and connect the ESD clamp device in the well  412   a  to the coil turn  202   a . The vias  418   a  do not connect to the other coil turns  202   b ,  202   c  and  202   d . Vias  418   b  pass through insulation layers  414   d ,  414   c  and  414   b , and connect the ESD clamp device in the well  412   b  to the coil turn  202   b . The vias  418   b  do not connect to the other coil turns  202   a ,  202   c  and  202   d . Vias  418   c  pass through insulation layers  414   d  and  414   c , and connect the ESD clamp device in the well  412   c  to the coil turn  202   c . The vias  418   c  do not connect to the other coil turns  202   a ,  202   b  and  202   d . Via  418   d  passes through insulation layer  414   d , and connects the ESD clamp device in the well  412   d  to the coil turn  202   d . The internal node  208  connects to circuit logic (not illustrated) of the integrated circuit die, and the external node  206  is adapted for connection to external circuitry. It is also contemplated and within the scope of the invention that the ESD clamp devices may be formed on or attached to each of the insulation layers. 
     According to another embodiment of the invention, the ESD protection network may be fabricated on a substrate made of either insulation material such as ceramic, glass epoxy, a printed wiring board (PWB) and the like, or conductive material such as aluminum, copper, steel brass and the like. A plurality of turns of a coil are formed on a plurality of insulation layers on the substrate. Each one of the plurality of insulation layers having a one of the plurality of the coil turns thereon. Vias are formed in each of the plurality of insulation layers, and conductive material is deposited therein for connecting the plurality of coil turns together to form the inductor. The ESD clamp devices may be formed or attached on each of the insulation layers or the ESD clamp devices may be attached to the substrate with connection to the plurality of coil turns made through conductive vias in the various insulation layers on which the coil turns are formed thereon. 
     Referring now to  FIG. 5 , a schematic elevational cross-section view of the ESD network fabricated on a substrate is illustrated. A substrate  510  may be non-conductive or conductive. If conductive, an insulation layer  516  may be used, and if non-conductive then no insulation layer  516  may be required. A first coil turn  202   a  is formed over the insulation layer  516  or over the non-conductive substrate  510 . The first coil turn  202   a  is connected to an external input node  206 . An insulation layer  514   a  is formed over the first coil turn  202   a . A second coil turn  202   b  is formed over the insulation layer  514   a . Another insulation layer  514   b  is formed over the second coil turn  202   b . A third coil turn  202   c  is formed over the insulation layer  514   b . Still another insulation layer  514   c  is formed over the third coil turn  202   c . Yet another insulation layer  514   d  is formed over the third coil turn  202   c . A fourth coil turn  202   d  is formed over the insulation layer  514   c . And another insulation layer  514   d  is formed over the fourth coil turn  202   d . The fourth coil turn  202   d  is connected to an internal node  208 . Any number of coil turns and insulation layers are contemplated and within the scope of the present invention. 
     ESD clamp devices  512   a ,  512   b ,  512   c  and  512   d  may comprise PMOS and NMOS transistors, and may be connected to power supply rails, V DD  and V SS , in a fashion similar to the PMOS and NMOS transistor connections illustrated in  FIG. 1 . It is also contemplated and within the scope of the invention that the ESD clamp devices may be any type of clamp device, connected to a substrate common or earth ground. The ESD clamp devices  512   a ,  512   b ,  512   c  and  512   d  may be connected to the coil turns  202   a ,  202   b ,  202   c  and  202   d , respectively, through conductive vias (holes) in the insulation layers  514   a ,  514   b ,  514   c  and  514   d . The vias are filled with a conductive material such as aluminum. As illustrated in  FIG. 5 , Vias  518   a  pass through insulation layers  514   d ,  514   c  and  514   b , and connect the ESD clamp device  512   a  to the coil turn  202   a . The vias  518   a  do not connect to the other coil turns  202   b ,  202   c  and  202   d . Vias  518   b  pass through insulation layers  514   d ,  514   c  and  514   b , and connect the ESD clamp device  512   b  to the coil turn  202   b . The vias  518   b  do not connect to the other coil turns  202   a ,  202   c  and  202   d . Vias  518   c  pass through insulation layers  514   d  and  514   c , and connect the ESD clamp device  512   c  to the coil turn  202   c . The vias  518   c  do not connect to the other coil turns  202   a ,  202   b  and  202   d . Via  518   d  passes through insulation layer  514   d , and connects the ESD clamp device  512   d  to the coil turn  202   d . It is also contemplated and within the scope of the invention that the ESD clamp devices may be formed on each of the insulation layers and attached to the conductive layer coil turns on the insulation layers. 
     Referring now to  FIGS. 6 and 7 , a schematic plan view and an elevational view, respectively, of an ESD protection network fabricated on an non-conductive printed circuit board using printed circuit stripline conductors and surface mounted components is illustrated. It is contemplated and within the scope of the invention that transmission line strictures may be used instead of coil shaped structures with the ESD clamp devices. The non-conductive portion of a printed circuit board  610  may be, for example but not limitation, glass epoxy, TEFLON® (a registered trademark of Dupont Co.), ceramic, glass and the like. The printed circuit stripline enables a constant impedance for the signal path. A plurality of turns of a coil  602  are formed on the printed circuit board  610  in a concentric spiral configuration. Conductive vias  612   a – 612   d  (plated through holes) may be formed through the printed circuit board  610  at each of the plurality of coil turns, or portions thereof. ESD clamp devices  604   a – 604   d  may be attached to respective ones of these vias  612   a – 612   d  and to a planar ground plane  712 . The ground plane  712  may be located on the face opposite the face on which the plurality of coil turns  602  is located thereon. The ESD clamp devices  604  may be connected to the coil turns  602  by vias  612 , and to the planar ground plane  710  by vias  608 , or, preferably, by using surface mount techniques. The plurality of coil turns  602  may be tapped with, for example, the vias  612  at points along the coil  602  which may represent a desired inductance needed to cancel out the parasitic capacitance of the associated ESD clamp devices  604 . The ESD clamp devices  604  may connect to the outer or larger coil turn(s) at less than 360 degrees, and the ilner or smaller coil turns  602  at more than 360 degrees, i.e., a multiple turn. 
     According to the aforementioned embodiments of the present invention, the insulation layers between the coil turns of the inductor may preferably be very thin so that the turns of the coil are close together, thus, improving the magnetic coupling therebetween and increasing the effective inductance for a given size coil diameter. Referring to  FIG. 8 , a schematic orthogonal view of the coil portion of  FIG. 3  and a core having magnetic properties to increase the inductance of the coil  202  is illustrated. A core  820  comprising a material of high magnetic permeability may be located within the coil  202  so as to further increase the effective inductance value for a give size of coil structure. This material may be, for example but not limitation, iron, iron oxide, ferrite ceramic, ferrous oxide, or other materials that increase the effective inductance of the inductor coil. 
     The present invention, therefore, is well adapted to carry out the objects and attain the ends and advantages mentioned, as well as others inherent therein. While the present invention has been depicted, described, and is defined by reference to particular preferred embodiments of the invention, such references do not imply a limitation on the invention, and no such limitation is to be inferred. The invention is capable of considerable modification, alternation, and equivalents in form and function, as will occur to those ordinarily skilled in the pertinent arts. The depicted and described preferred embodiments of the invention are exemplary only, and are not exhaustive of the scope of the invention. Consequently, the invention is intended to be limited only by the spirit and scope of the appended claims, giving full cognizance to equivalents in all respects.