Abstract:
A spread spectrum clock generator includes a non-volatile memory to store control codes corresponding to a predetermined delay. A delay circuit receives a control code having a predetermined number of bits that determine a delay to apply to a fixed clock signal a period of time. The delay mitigates the electromagnetic interference caused by a periodic clock signal.

Description:
This application claims priority from Korean patent application number 2003-62863 filed Sep. 8, 2003 that we incorporate herein by reference. 
   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a spread spectrum clock generator and a method of generating a spread spectrum clock. 
   2. Description of the Related Art 
   A clock generator, such as  10  in  FIG. 1 , generally comprises a clock source  100  and a phase-locked loop (PLL)  102 . This generator  10  generates a system clock usually having square waves and a 50% duty cycle. The system clock is then used in many different types of systems, such as a memory system including a memory module  14  and a memory controller  12 . 
   System clocks such as this can be a source of unwanted electromagnetic interference (EMI). EMI can cause problems in electronic circuits, as it interferes with signal transmission. As technology improves, circuits can operate faster, requiring faster clocks that in turn generate more EMI. One technique to alleviate EMI is to use spread spectrum clock generators (SSCG). These clocks are referred to as spread spectrum in that their frequency is spread out over different frequencies, avoiding the energy peaks at clock edges. In some instances, SSCGs are implemented using PLLs as shown in the US patents described below. PLLs vary the voltage to a voltage controlled oscillator (VCO), causing varying delays in the clock. 
   Examples of this approach are shown in U.S. Pat. No. 5,631,920, issued May 20, 1997; U.S. Pat. No. 6,292,507 issued Sep. 18, 2001; and U.S. Pat. No. 6,351,485, issued Feb. 26, 2002. The use of a PLL typically allows a clock cycle to be switched between two frequency limits, adjusting the clock frequency back and forth between them. This approach may be somewhat limited, as it only allows for two fixed frequencies to be used, and does not allow programmable control. 
   Another approach is shown in U.S. Pat. No. 6,501,307, issued Dec. 31, 2002. As shown in  FIG. 2 , this approach has 2 capacitors used as loads switched by counter-sequencer  20 , clocked by fixed clock FCLK. The counter-sequencer  20  drives first control signal CTL 1  to the gate of load-switching transistor  22 , and second control signal CTL 2  to the gate of second load-switching transistor  24 . When CTL 1  is high, capacitor  26  has to be charged and discharged by input buffer  28  before the logic threshold of output buffer  30  is reached, thus delaying the clock edges. When CTL 2  is high, capacitor  32  has to be charged and discharged by input buffer  28  before the logic threshold of output buffer  30  is reached, thus also delaying the clock edges. When both CTL 1  and CTL 2  are high, both capacitors have to be charged, further delaying the clock edges. However, these loads cannot be changed linearly to adjust the clock frequency as needed. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other objects, features, and advantages of the invention will become more readily apparent from the detailed description of an embodiment that references the following drawings. 
       FIG. 1  shows a prior art embodiment of a memory system. 
       FIG. 2  shows a prior art embodiment of a spread spectrum clock generator. 
       FIG. 3  shows a signal diagram of energy pulses associated with clock generators. 
       FIG. 4  shows an embodiment of memory system according to this invention. 
       FIG. 5  shows an embodiment of a memory system employing a spread spectrum clock generator according to this invention. 
       FIG. 6  shows an alternative embodiment of a memory system employing a spread spectrum clock generator according to this invention. 
       FIG. 7  shows an embodiment of a spread spectrum clock generator according to this invention. 
       FIG. 8   a - 8   b  show alternative embodiments of a delay circuit according to this invention. 
       FIG. 9  shows an embodiment of a control circuit for a spread spectrum clock generator according to this invention. 
       FIG. 10  shows an embodiment of an address generator according to this invention. 
       FIG. 11  shows a timing diagram for a spread spectrum clock generator according to this invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 3  shows the basis of the problem with nonmodulated clock signals. The energy spike from a nonmodulator clock may have an amplitude of two to eighteen dB beyond that of a modulated, or spread spectrum, clock signal. This difference causes a much higher level of EMI that can have negative effects on electronic components and systems such as memory systems. Examples discussed herein may rely upon memory system components and methods, but are merely intended as examples, and it must be understood that application of embodiments of the invention are not limited to memory systems. 
   An example of such a system is shown in  FIG. 4 . A clock generator  40  generates a fixed frequency clock, FCLK, that is used by the spread spectrum clock generator (SSCG)  42 . SSCG  42  produces a spread spectrum clock and is in turn used by electronic devices  44   a  through  44   n . In a memory system, the devices  44   a - 44   n  may be memory banks or memory module or memory device or registers used to store data. 
   Alternative embodiments of a memory system employing a spread spectrum clock generator are shown in  FIGS. 5 and 6 . In  FIG. 5 , the clock generator  90  includes fixed frequency clock  900  and a phase locked loop  902 . The memory module  94  includes individual memory modules and the spread spectrum clock generator  904 . 
   The SSCG is shown in a more detailed embodiment in FIG  7 . In this embodiment, the SSCG  42  has a control circuit  50 , a programmable delay circuit  52  and a register circuit  54 . The register circuit  54  holds control codes that program the delay circuit  52 . The control circuit  50  provides the addresses to the register circuit  54 , which in turn provides the control codes to the delay circuit. This allows the delay to alter a delay period applied to a fixed clock FCLK, changing the frequency of the clock to alleviate the EMI of a periodic clock. 
   The programmable delay may be implemented by one of many sets of delaying components. Two examples are provided in  FIGS. 8   a  and  8   b , but it must be noted that these are merely examples of delay components. Embodiments of the invention generally provide components that can be selected by the control codes provided from the register circuit, allowing precise control of the delay in a spread spectrum clock generator. In the example of  FIG. 8   a , the delay elements are oppositely arranged capacitors, such as NMOS and PMOS capacitances. The fixed clock, FCLK, is buffered by inverting input buffer  60 . If the FCLK signal is high, the inverted signal is low. This causes a low signal to be at one terminal of the PMOS capacitances  62   a ,  62   b  and  62   c . If the control code for a particular component is low, the PMOS capacitance for that component will provide 100% of the capacitance, causing a delay equal to the charging time of the component. 
   For example, if the control code CO 1  is low, the capacitor  62   a  provides 100% of the capacitance that will need to charge before the signal can pass to the output inverter  66 . If the control code CO 1  is high, the capacitor  62   a  provides substantially ⅓ of the capacitance that would need to charge before the signal passes to the output inverter  66 . 
   If the clock signal FCLK is low, the output of the inverter  60  is high. This causes the NMOS capacitors  64   a - 64   c  to be the line loads for the signal prior to reaching the output inverter  66 . In this manner, the amount of delay can be programmed by the control codes, in conjunction with the input clock signal FCLK. 
   Another example of a delay circuit is shown in  FIG. 8   b . Each delay component in this embodiment has an access transistor such as  72   a  and a capacitor such as  74   a . When the control code for a particular component is high, the access transistor turns on and the capacitor will charge, causing a delay. For example, if the control code CO 1  is high, the transistor  72   a  turns on and capacitor  74   a  will charge. This causes a delay in the transmission of the signal from the input inverter buffer  70  to the output inverter buffer  76 . Each additional capacitor that turns on will cause the capacitors to charge, thereby increasing the delay. 
   The capacitors of  FIGS. 8   a  and  8   b  may all have the same value, or may all have differing values. For example, each capacitor may have a charging time that is equal to a unit amount of delay, d. Alternatively, the charging time of each capacitor may be controlled so as to have a binary equivalent. For example, the ‘a’ capacitors may have a charging time equal to the unit amount of delay, d. The ‘b’ capacitors may have a charging time equal to twice the unit amount of delay, 2d, or d+1. The ‘c’ capacitors may have a charging time equal to four times the unit amount of delay, 4d or d+3. 
   Turning now to the control circuit  50  of the SSCG, an embodiment is shown in  FIG. 9 . The control circuit  50  may comprise a frequency divider  80  for generating a lower frequency clock DFCLK and an address generator  82 . The address generator may be implemented as a state machine, where the output of a new address signal causes the machine to change state to the next state. The number of addresses needed may be known, as the number of combinations of control code values, or control words, may be finite. 
   For example, there may only be four control ‘words’ used to activate the delay circuit. Four addresses, 1000, 0100, 0010, and 0001, may be used. An address generator to generate the addresses is shown in  FIG. 10 . 
     FIG. 10  is a circuit diagram showing a configuration of the address generator shown in  FIG. 9 . The address generator includes an overflow detection and shift register  90  and a forward and backward shift control signal generation circuit  92 . 
   In  FIG. 10 , the overflow detection and shift register  90  includes a bidirectional shift register configured with D flip-flops DF 2 -DF 4 , switches FSW 1 -FSW 3 , BSW 1 -BSW 3 , and SW 1 -SW 4  and NOR gates NOR 1 -NOR 4 , and an overflow detection circuit configured with D flip-flops DF 1  and DF 6 . 
   The forward and backward shift control signal generation circuit  92  includes a pulse generation circuit configured with an OR gate OR, an AND gate AND and an inversion delay unit IDLC, and a toggling circuit configured with a D flip-flop DF 7 . 
   In FIG  10 , the D flip-flops DF 1  and DF 3 -DF 7  have a data input terminal D, a clock signal input terminal CK, an output terminal Q, an inversion output terminal QB and a reset terminal RE, and the D flip-flop DF 2  has a data input terminal D, a clock signal input terminal CK, an output terminal Q, an inversion output terminal QB, and a set terminal SE. Each of the switches SW 1 -SW 3 , FSW 1 -FSW 3 , and BSW 1 -BSW 3  is configured with a CMOS transfer gate and an inverter. 
   Next, the function of each block of the circuit shown in  FIG. 10  will be described. 
   When a forward shift control signal FCON is generated, the overflow detection and shift register  90  shifts address signals A 1 -A 4  in the forward direction in response to a clock signal DFCLK. When the address signal A 4  is “1”, an overflow detection signal F 2 B is generated and the address signal A 4  of “1” is generated once more. When a backward shift control signal BCON is generated, the overflow detection and shift register  90  shifts the address signals A 1 -A 4  in the backward direction in response to the clock signal DFCLK. When the address signal A 1  is “1”, an overflow detection signal B 2 F is generated and the address signal A 1  of “1” is generated once more. That is, the bidirectional shift register performs the forward shift operation in response to the forward shift control signal FCON and performs the backward shift operation in response to the backward shift control signal BCON. When the address signal A 1  of“1” is generated, the most significant bit may be activated, and the address signal A 1  of “1” is generated once more and then the address signals A 2 -A 4  are shifted. When the address signal A 4  of“1” is generated, the least significant bit may be activated, and the address signal A 4  of “1” is generated once more and then the address signals A 1 -A 3  are shifted. Persons having skill in the art will recognize that the A 1  may be either the least significant bit or the most significant bit, and A 4  may be either the least significant bit or the most significant bit. When the address signal A 1  of “1” is generated, the overflow detection circuit generates the address signal A 1  of “1” as the overflow detection signal B 2 F in response to the clock signal DFCLK. When the address signal A 4  of “1” is generated, the overflow detection circuit generates the address signal A 4  of “1” as the overflow detection signal F 2 B in response to the clock signal DFCLK. 
   When the overflow detection signals B 2 F and F 2 B are generated, the forward and backward shift control signal generation circuit  92  toggles the forward shift control signal FCON and the backward shift control signal BCON. That is, when the overflow detection signals B 2 F and F 2 B are generated, the pulse generation circuit generates a pulse signal. The toggling circuit is reset in response to a reset signal RESET, and toggles the forward shift control signal FCON and the backward shift control signal BCON in response to the pulse signal output from the pulse generation circuit. 
   When a reset signal, RESET, is applied, address signals A 1 -A 4  are generated to 1000. A flip-flop generating address signal A 1  generates a high signal in response to a set signal SE. Once the address signal A 1  is generated, the high data of the A 1  signal is shifted to a next address signal whenever the divided clock DFCLK is toggled. This results in address signals A 1 -A 4 , 0100, 0010, and, 0001. These are enabled in this sequence when a forward enable signal FCON is enabled. 
   After the final address A 4  is activated (A 1 -A 4  0001), a backward enabled signal BCON is enabled. This allows the high data of the A 4  signal to be output in reverse order, A 3 , A 2  and A 1 . Accordingly, the address signals A 1 -A 4  are changed with order such as 0010, 0100 and 1000. The switches are either forward switches FSW 1 -FSW 3 , or backward switches BSW 1 -BSW 3 . This process of address generation is continuously repeated in order to generate address signals in response to the divided clock DFLCK. The value of the delay load can be changed with an edge variation as will be discussed with regard to  FIG. 11 . 
   In  FIG. 11 , the timing of the signals for address generation is shown. The reset signal initiates the process. The two clock signals, FCLK and the divided clock, DFCLK are also shown. In this particular embodiment, the DFCLK has a frequency that is half that of the fixed clock. Other frequency divisions may also be used. 
   The forward control and backwards control signals FCON and BCON are generated from the B 2 F and F 2 B signals as shown in  FIG. 10 . Their related timing signals are shown in  FIG. 10 . The resulting spread spectrum clock signal, SSCLK, has a delay associated with it. For example, the period T is the period of the fixed clock signal plus a unit of delay, d. The number of delay units added to the clock signal can be programmed to vary according to the desires of the system designer. In the example of  FIG. 11 , the period T+1 has a delay of d+1; the period T+2 has a delay d+3, and period T+1, has a delay of d+4. As the addresses cycle backwards, the delays also cycle backwards, as shown in  FIG. 11 . 
   The delays shown are determined by the control signals that reside at the addresses A 1 -A 4 . The below table shows the control signals C 01 , C 02  and C 03 , in their control ‘words’ and their corresponding addresses. Referring back to  FIG. 7 , it can be seen that the addresses provided to the address circuit results in a particular control code being provided to the delay components as discussed above. An example of some control codes provided are shown in the below table. 
   
     
       
             
             
           
             
             
             
             
             
           
         
             
                 
                 
             
             
                 
               Control Signal 
             
           
        
         
             
                 
               Address 
               CO1 
               CO2 
               CO3 
             
             
                 
                 
             
             
                 
               0001 
               0 
               0 
               0 
             
             
                 
               0010 
               1 
               0 
               0 
             
             
                 
               0100 
               1 
               1 
               0 
             
             
                 
               1000 
               0 
               0 
               1 
             
             
                 
                 
             
           
        
       
     
   
   This particular example assumes that there are 3 delay components as shown in  FIGS. 8   a  and  8   b . However, it must be noted that any number of delay components could be used, as well as any number of control codes. Further, the nature of the control codes themselves may vary. The control codes may be a binary representation of the delay, where a delay control code of 001 would result in a delay of 1, while a delay control code of 100 would result in a delay of 4. 
   Alternatively, the control codes may be equally weighted representations. The control code 100 may be a delay of 2. For example, the equally-weighted representations are included in the table below. 
                                                                     Control Signal                Address   CO1   CO2   CO3   Binary   Equal                       0001   0   0   0   0   1           0010   1   0   0   4   2           0100   1   1   0   5   3           1000   0   0   1   1   4                        
In either case, the code may represent a number of repetitions of the delay.
 
   In one embodiment, the register circuit could be eliminated, using the address as the control code. However, this removes one level of modularization that would otherwise provide more flexibility in the programmability of the delay circuit. For example, the register circuit could be reprogrammed or replaced with a new register circuit that would have different values for the predetermined addresses. 
   Suppose the delay associated with address 0001 was desired to be 4 instead of 0. Allowing removal or reprogramming of the existing register circuit having the control codes above is possible because of the register circuit being separated from the address generator. The register circuit could be any type of non-volatile memory such as an erasable electronically programmable read only memory (EEPROM), a fuse array, an electronically programmable read-only memory (EPROM), a read-only memory (ROM), etc. 
   Having illustrated and described the principles of embodiments of the invention, it should be readily apparent to those skilled in the art that the embodiments can be modified in arrangement and detail without departing from such principles. All modifications coming within the spirit and scope of the accompanying claims are claimed.