Abstract:
A device for spectrally shaping a discrete-value transmission signal, in a radio transmitter, includes one input for receiving an in phase component of the transmission signal and a further input for receiving a quadrature component of the transmission signal. The device also includes a filter circuit with a plurality of multipliers. A multiplexing unit is located in the signal path before the filter circuit, and a demultiplexing unit is located in the signal path after the filter circuit.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of copending International Application No. PCT/DE00/03346, filed Sep. 22, 2000, which designated the United States. 
    
    
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The invention relates to a device and a method for spectrally shaping a transmission signal in a radio transmitter, in particular a mobile radio transmitter. 
     A known digital quadrature modulator, shown for example, in Published European Patent Application, EP 0 693 844 has a digital filter for spectrally shaping an in phase component and a quadrature component of a digital input signal. In this case, a multiplexer with two inputs (for the I branch and the Q branch) is connected upstream of each multiplier of the digital filter, and a demultiplexer with one input and two outputs is connected downstream of each multiplier. As a result, the same (multiplexed) multipliers are used for filtering the I branch and the Q branch. 
     In a known nonrecursive half-band filter device, shown for example, in Published European Patent Application, EP 0 622 898 A2, a single filter arrangement is provided for processing a complex input signal into a complex output signal with a reduction of the sampling rate. Temporally offset real and imaginary parts of the input signal are fed into this filter arrangement. The filter device, for this purpose, has time-delay elements that are coupled for sequentially picking up and buffering the alternating real and imaginary parts. 
     It is already known to subject a discrete-value (digital) transmission signal to signal shaping before converting the signal into an analog baseband signal and upwardly mixing the analog baseband signal to form a radio-frequency traffic channel, in order to permit narrow-band transmission of information that thereby sparingly uses frequency resources. The signal shaping is usually accomplished by at least two digital filters that are arranged in the in-phase branch (I branch) or in the quadrature branch (Q branch) of the signal path in the radio transmitter. Each digital filter has a large number of multipliers (see, for example,  FIG. 3 ). 
     The filters can comprise up to approximately 70% of the chip area in a typical DSP (Digital Signal Processor) transmitter chip for a mobile radio transmitter. It is therefore disadvantageous that the multiple use of identical components (filters, multipliers) necessitates a substantial outlay of hardware for implementing the spectral signal shaping. 
     SUMMARY OF THE INVENTION 
     It is accordingly an object of the invention to provide an apparatus for spectrally shaping a discrete-value transmission signal in a radio transmitter and a method for spectrally shaping a discrete-value transmission signal in a radio transmitter which overcome the above-mentioned disadvantages of the prior art apparatus and methods of this general type. 
     In particular, it is an object of the invention to provide an apparatus for spectrally shaping a discrete-value transmission signal in a radio transmitter that can be implemented with a comparatively low outlay. It is also an object of the invention to provide a method for spectrally shaping a discrete-value transmission signal in a radio transmitter that can be performed with a reduced hardware complexity as compared to the prior art. 
     With the foregoing and other objects in view there is provided, in accordance with the invention, a device for spectrally shaping a discrete-value transmission signal in a radio transmitter. The device includes: a first input for receiving an in-phase component of the transmission signal; a second input for receiving a quadrature component of the transmission signal; a first shift register having N first memory locations, the first shift register connected to the first input; a second shift register having N second memory locations, the second shift register connected to the second input; a multiplexer unit having a plurality of multiplexers; a discrete-value filter circuit having a plurality of multipliers and at least one adder; a first output for providing a filtered in-phase component of the transmission signal; a second output for providing a filtered quadrature component of the transmission signal; a demultiplexer unit; and a signal path. Each of the memory locations of the first shift register has M signal taps. Each of the memory locations of the second shift register has M signal taps, where M is greater than one. The multiplexer unit is configured in the signal path downstream from the first shift register and the second shift register. The multiplexer unit is configured in the signal path upstream of the filter circuit. The demultiplexer unit is configured in the signal path downstream of the filter circuit and upstream of the first output and the second output. 
     In accordance with an added feature of the invention, a plurality of filter coefficients are assigned to a single one of the plurality of the multipliers. 
     In accordance with an additional feature of the invention, the number of multiplexers in the multiplexer unit is N×M; and each one of the plurality of the multiplexers includes two multiplexer inputs. 
     In accordance with another feature of the invention, the nukmber of multiplexers in the multiplexer unit is N; and each one of the multiplexers includes 2×M multiplexer inputs. 
     In accordance with a further added feature of the invention, the multipliers have filter coefficients that have been selected such that the filter circuit performs Root-Raised-Cosine filtering. 
     In accordance with a further additional feature of the invention, the filtered in-phase component of the transmission signal has a sampling rate that is higher than that of the in-phase component of the transmission signal received at the first input by a multiple; and the filtered quadrature component of the transmission signal has a sampling rate that is higher than that of the quadrature component of the transmission signal received at the second input by the multiple. The multiple is preferably 4. 
     With the foregoing and other objects in view there is provided, in accordance with the invention, a method for spectrally shaping a discrete-value transmission signal in a radio transmitter, which includes steps of: providing an in-phase component of the transmission signal at a first input that is connected to a first shift register having N first memory locations; providing a quadrature component of the transmission signal at a second input that is connected to a second shift register having N second memory locations; filtering the in-phase component of the transmission signal and the quadrature component of the transmission signal in a discrete-value filter circuit having a plurality of multipliers and at least one adder; in a signal path upstream of the filtering, multiplexing the in-phase component of the transmission signal and the quadrature component of the transmission signal; at each one of the N first memory locations, providing an output signal at a plurality of taps; at each one of the N second memory locations, providing an output signal at a plurality of taps; and demultiplexing the in-phase component of the transmission signal and the quadrature component of the transmission signal in a signal path downstream of the filtering. 
     In accordance with an added mode of the invention, a plurality of filter coefficients are assigned to a single one of the plurality of the multipliers. 
     In accordance with an additional mode of the invention, Root-Raised-Cosine filtering is performed with the filter circuit. 
     The basic principle of the invention consists in providing each of the respective N memory locations of the two shift registers with M&gt;1 signal taps, and operating the filter circuit in multiplex mode so that both the I component and the Q component of the transmission signal can be spectrally shaped using one and the same filter circuit. It is thereby possible to substantially reduce the number of multipliers that are actually implemented on a transmitter chip, and thus also the need for chip area. 
     A further advantage of the invention is that after the filtering—as conditioned by the multiple memory taps—the two output signals (I component, Q component of the transmission signal) are present with a higher rate than that of the corresponding signals at the inputs of the signal-shaping device. This is advantageous because subsequent signal processing would require the undertaking of oversampling to suppress interference, but this is performed “automatically” in the case of the invention. 
     A particularly preferred embodiment of the invention is characterized in that a plurality of filter coefficients are assigned to a single multiplier. In this case, not only is multiple use made of the filter circuit (specifically for the I and Q branches), but each multiplier is also utilized multiply (specifically for the various filter coefficients), that is to say is employed even more efficiently in terms of hardware. 
     A first preferred embodiment is characterized in that the multiplexer unit is constructed from N×M multiplexers with two multiplexer inputs in each case. In this case, the multipliers alternately operate in the I and Q branches of the signal path. 
     A second preferred embodiment, which implements the already mentioned multiple use of the multipliers with reference to different filter coefficients, is characterized in that the multiplexer unit is constructed from N multiplexers with 2×M multiplexer inputs in each case. Here, a multiplier operates for M multiplexer working clock pulses in the I branch and for the next M multiplexer working clock pulses in the Q branch, etc. 
     Other features which are considered as characteristic for the invention are set forth in the appended claims. 
     Although the invention is illustrated and described herein as embodied in a device and method for spectrally shaping a transmission signal in a radio transmitter, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. 
     The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a radio transmitter for generally explaining signal processing taking place in the transmitter; 
         FIG. 2  is a block diagram of a prior art modulator; 
         FIG. 3  is a block diagram of a prior art single RRC filter; 
         FIG. 4  is a block diagram of a modulator with an inventive spectral signal shaping device; 
         FIG. 5  is a circuit diagram of a first embodiment of the spectral signal shaping device shown in  FIG. 4 ; and 
         FIG. 6  is a circuit diagram of a second embodiment of the spectral signal shaping device shown in  FIG. 4 . 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to the figures of the drawing in detail and first, particularly, to  FIG. 1  thereof, there is shown, the structure of a transmitting device SE of a radio transmitter, as it is used, for example, in a base station or a mobile station of a mobile radio system. 
     The transmitting device SE receives an analog source signal QS (generated, for example, by a microphone), and feeds it to an encoder COD. The encoder COD includes, in a way not illustrated, an analog-to-digital converter for digitizing the source signal and can, furthermore, include a source encoder, a channel encoder, an interleaver and a block former, which in a suitable way subject the digitized source signal QS to source coding, error protection coding and interleaving, and subdivide it into data blocks. 
     The encoder COD outputs a discrete-value data signal which consists of a data sequence {d n } of the elements d 0 , d 1 , . . . 
     The data sequence {d n } is fed to a modulator device MOD that modulates the data sequence for emission using a radio-frequency carrier, and—in the case of a CDMA (Code Division Multiple Access) system—impresses an individual subscriber spread code on each data symbol. A CPM (Continuous Phase Modulation) method with a continuous phase and a constant complex envelope can, for example, be utilized for modulation, and one of the known spread code methods, for example, DS (Direct Sequencing) CDMA, MC (Multi Carrier) CDMA, or else FH (Frequency Hopping) CDMA can be used for CDMA subscriber coding. 
     The modulator device MOD further splits the data signal into the I branch and the Q branch. The I and Q signal components output by the modulator device MOD are fed to a digital-to-analog converter DAC which generates the corresponding analog I and Q signal components. These are respectively mixed upward in conjunction with a mutual phase offset of 90° in mixing stages MI1 and MI2, respectively, and using a radio-frequency carrier of frequency f, are superimposed and emitted via an antenna A as a radio signal. 
       FIG. 2  shows a prior art modulator device MOD′. The modulator device MOD′ has four data inputs D 1 , D 2 , D 3  and D 4 , and is therefore suitable for simultaneously setting-up four physical channels. 
     The data sequences {d n1 }, {d n2 }, {d n3 } and {d n4 } are present at the data inputs D 1 , D 2 , D 3 , and D 4 . 
     The data sequences {d n1 }, {d n2 }, {d n3 } and {d n4 } are sampled by sampling stages A 1 , A 2 , A 3 , A 4  with oversampling (oversampling factor Q). The data rate is increased as a result in each signal path from 1/T s  to 1/T c , T s  denoting the symbol duration of the individual data symbols d n1  (and d n2 , d n3 , d n4 ) and T c  denoting the (shorter) chip duration, which constitutes the time basis for the later CDMA coding. In the case of a third mobile radio generation UMTS (Universal Mobile Telecommunications System) transmitter, the data rate 1/T c  at the output of the sampling stages A 1 , A 2 , A 3 , A 4  (that is to say the chip rate) is 4.096×10 6  samples per second. 
     Using multipliers M, the (oversampled) data symbols are subsequently multiplied by a complex scrambling code S and two CDMA codes C 1  (for the data symbols d n1  and d n2 ) or C 2  (for the data symbols d n3  and d n4 ). Here, s r , c r1  and c r2  denote the real parts, and s i , c i1  and c i2  denote imaginary parts of the elements of the previously mentioned code sequences. 
     The I components and the Q components of the corresponding digital transmission signals are generated by adding the real and imaginary parts of the signals thus generated in the adders AD 1 , AD 2 , AD 3  and AD 4 . 
     The further signal processing is explained using the Q and I signal components that are assigned to the data inputs D 1  and D 2  and that are illustrated in the upper half of  FIG. 2 . The processing of the Q and I signal components assigned to the data inputs D 3  and D 4  is of a corresponding nature. 
     The Q and I signal components are input into a device for spectral signal shaping ESF′ whose extent is represented in  FIG. 2  by a dashed line. The device for spectral signal shaping ESF′ includes a respective sampling stage a 1  or a 2  for each signal component. Each sampling stage a 1  or a 2 , for a respective signal component, increases the signal rate to a multiple M of the chip rate 1/T c  by a renewed oversampling. 
     Connected downstream of the sampling stages a 1  and a 2  are digital filters DF 1 , DF 2  that spectrally shape the Q signal component and the I signal component, respectively. The structure of the prior art digital filters DF 1 , DF 2  is explained in more detail later with reference to  FIG. 3 . 
     The processing of the Q and I signal components assigned to the data inputs D 3  and D 4  are analogously processed by the sampling stages a 3  and a 4 , and by the digital filters DF 3  and DF 4 . 
     The spectrally shaped Q signal components are added by an adder AD 5 , and the spectrally shaped I signal components are added by an adder AD 6 . The Q and I signal components are subject, as appropriate, to frequency correction (not illustrated), and are then relayed to a digital-to-analog converter DAC such as that shown in  FIG. 1 . 
       FIG. 3  shows the design of a known filter DF 1  or DF 2  as used in the modulator design MOD′ illustrated in  FIG. 2 . The filter has a shift register with  55  memory locations T, and  56  multipliers M as well as  55  adders AD. One of the inputs of each of the multipliers M are connected in parallel to a common tap. The multipliers M are present between and downstream of the memory locations T. The other input of each of the multipliers M is supplied with a respective one of the filter coefficients C 0 , . . . , C 55 . The adders AD add up the multiplication results that are calculated by the multipliers M. 
     The coefficients C 0 , . . . , C 55  of the filter are yielded from the samples of the filter transfer function at a rate of M/T C . In the design illustrated here with  56  filter coefficients C 0 , . . . , C 55 , fourteen chips of the Q and I signal component, respectively, are accommodated in the filter in the case of an M=4-fold oversampling. 
       FIG. 4  shows a block diagram of an embodiment of a modulator device MOD that can be used in the present invention. Patrs that are the same as those shown in the preceding figures are marked with the same reference symbols, or are represented by the same circuit symbols. 
     The data sequences {d n1 }, {d n2 }, {d n3 }, {d n4 }, are present at the data inputs D 1 , D 2 , D 3 , D 4  and have a word length l and a data symbol rate l/T s . The individual data symbols d n1 , d n2 , d n3 , d n4  can be extracted from the set of values {1, −1}. 
     In an optional weighting unit WG, the data symbols are weighted synchronously with the symbol clock by being multiplied by the weighting factors w 1 , w 2 , w 3  and w 4 , respectively. The data signals available at the outputs of the weighting unit have a word length of q we &gt;1. Their data rate is unchanged at l/T s . 
     The weighting factors w 1 , w 2 , w 3 , w 4  can be interpreted as “loudness factors”. By using different weighting factors w 1 , w 2 , w 3 , w 4  in the respective channels, different radio distances can be taken into account with reference to the various channels, and/or when different spread factors Q are used I the respective channels, the different channel energies effected thereby can be compensated. 
     The sampling stages A 1 , A 2 , A 3 , A 4  increase the signal rate by the oversampling factor (=spread factor) Q, and make a high-rate signal available at their output synchronously with the chip timing clock 1/T C . The oversampling factor Q can be, for example, between 4 and 512, that is to say T S =4T c  . . . 512T c . 
     The Q-fold oversampled data symbols d n1 , d n2 , d n3 , d n4  are then spread coded in the spread encoder SC by impressing a channel-specific digital spread code sequence. A first spread code sequence C 1  consisting of Q digital chips c 1  is impressed in each case onto the data symbols d n1 , fed from the first data input D 1 . There is a corresponding procedure with reference to the data symbols d n2 , d n3 , d n4  fed from the further data inputs D 2 , D 3 , D 4 . Impressing the spread code sequences C 1 , C 2 , C 3 , C 4  provides each data symbol with a “fingerprint” of its channel, as it were. The spread coded data signals are available at the output of the spread encoder SC with a signal rate of l/T c  and an (unchanged) word length of q we . 
     Located in the signal path downstream of the spread encoder SC is a channel adder CA. The channel adder CA includes two adders AD 1 , AD 2  operating synchronously with the chip clock. The adder AD 1  adds the signal data originating from the data inputs D 1 , D 3 , and the adder AD 2  adds the signal data originating from the data inputs D 2  and D 4 . Data signals with a signal rate of 1/T c  and a (possibly increased) word length of q ca  are present at the two outputs of the channel adder CA. 
     A complex scrambler CS impresses a base station identifier on the data signals. For this purpose the signals that are output by the channel adder CA are multiplied in the way illustrated by the real and imaginary parts s q  or s i , respectively, of the elements of a complex scrambling code sequence S, and are subsequently added as shown in a crosswise fashion. Furthermore, the complex scrambler CS generates the I and Q signal components of the transmission signal, which are available at the output of the complex scrambler CS with a signal rate of 1/T c  and a word length of q sc . 
     These two signal components (I and Q) are fed to the inputs E 1 , E 2  of a device for spectral signal shaping ESF 1 / 2 . The device for spectral signal shaping ESF 1 / 2  makes the spectrally shaped (that is to say, modulated) I and Q signal components, respectively, available at its outputs A 1 , A 2 . As shown in  FIG. 1 , these I and Q signal components are converted into analog signals using a frequency correction (not illustrated), and are emitted as a radio signal. 
       FIGS. 5 and 6  each show a circuit diagram of an embodiment (ESF 1  or ESF 2 ) of the device for spectral signal shaping. 
     According to  FIG. 5 , the I signal component is fed to a first shift register SR 1  and the Q signal component is fed to a second shift register SR 2  which each have ten memory locations T 1 , T 2 , . . . , T 10 . Each memory location T 1 , T 2 , . . . , T 10  stores a data word of word length q sc . The data words are pushed through the two shift registers SR 1  and SR 2  synchronously with the chip clock l/T c . 
     Four taps are respectively located at each memory location T 1 , T 2 , . . . , T 10  of the two shift registers SR 1  and SR 2  such that each shift register SR 1  and SR 2  has a total of 40 taps. The total of 80 taps of the two shift registers SR 1  and SR 2  are fed to a multiplexer unit MUXE 1 . 
     The multiplexer unit MUXE 1  includes 40 multiplexers MUX 1 , MUX 2 , . . . , MUX 40 . Each multiplexer MUX 1 , MUX 2 , . . . MUX 40  has two multiplexer inputs. The first tap of the first memory cell T 1  of the shift register SR 1  in the I signal path leads to one multiplexer input of the first multiplexer MUX 1 , and the first tap of the first memory cell T 1  of the shift register SR 2  in the Q signal path leads to the second multiplexer input of the first multiplexer MUX 1 . In a similar way, the second taps of the two shift registers SR 1  and SR 2  in each case lead to the two multiplexer inputs of the second multiplexer MUX 2 , . . . , and the two fortieth taps of the shift registers SR 1  and SR 2  lead to the two multiplexer inputs of the fortieth multiplexer MUX 40 . 
     The multiplexers MUX 1 , MUX 2 , . . . , MUX 40  alternately relay the signal words originating from the I and the Q signal components. Buffers are present in the multiplexers MUX 1 , MUX 2 , . . . , MUX 40  for buffering the signal words that are not currently being output at the multiplexer output. 
     Signal words of word length q sc  of the I and Q signal components are (alternately) available with a signal rate of 2/T c  at the forty outputs of the multiplexer unit MUXE 1 . 
     The forty outputs of the multiplexer unit MUXE 1  are fed to a filter circuit FS 1 . The filter circuit FS 1  includes forty multipliers M 1 , M 2 , . . . , M 40  and four adders ADD 1 , ADD 2 , ADD 3  and ADD 4 . Each multiplier M 1 , M 2 , . . . , M 40  multiplies an output signal of the multiplexer unit MUXE 1  by a single filter coefficient g 1 , g 2 , . . . , g 40 . The filter coefficients g 1 , g 2 , . . . , g 40  are determined (in this specific exemplary embodiment) by a 4-fold oversampling of the pulse response, limited to a time interval of 10 T c , of the fundamental spectral filter function (that is to say the transfer function of the filter circuit). 
     The spectral filter function can be an RRC (root raised cosine) function for example. Such a filter circuit is denoted as an RRC filter circuit. The RRC function is defined by the function (1+cos x) ½ /2 ½  in the range of 0≦x≦π, which reproduces the functional relationship of the filter edge of the RRC in the spectral range. 
     The adders ADD 1 , ADD 2 , ADD 3 , ADD 4  each have ten adder inputs. The ten adder inputs of the adder ADD 1  are connected to the outputs of the multipliers M 1 , M 5 , M 9 , M 13 , M 17 , M 21 , M 25 , M 29 , M 33  and M 37 , the inputs of the adder ADD 2  are connected to the outputs of the multipliers M 2 , M 6 , M 10 , M 14 , M 18 , M 22 , M 26 , M 30 , M 34 , M 38 , etc. In other words, the four adders ADD 1  to ADD 4  are assigned to the four taps 1 to 4 of each memory location T 1 , T 2 , . . . , T 10  of the shift registers SR 1  and SR 2 . 
     A demultiplexer unit DMUXE 1  is connected downstream of the filter circuit FS 1 . The demultiplexer unit DMUXE 1  first demultiplexes each adder output with reference to the I and Q signal components, and subsequently multiplexes the result of the four adders ADD 1 , ADD 2 , ADD 3 , ADD 4  separately in each case for the I signal component and the Q signal component. This produces a four-fold oversampled (filtered) I signal component at the output A 1  of the device for spectral signal shaping ESF 1 , and a four-fold oversampled (filtered) Q signal component at the output A 2 . 
     A second embodiment of the inventive device for spectral signal shaping ESF 2  is illustrated in  FIG. 6 . The device ESF 2  likewise has two shift registers SR 1  and SR 2  that each have ten memory locations T 1 , T 2 , . . . , T 10  and four taps per memory location. In contrast to ESF 1 , ESF 2  includes only ten multiplexers MUX 1 ′, MUX 2 ′, . . . , MUX 10 ′ which are combined in a multiplexer unit MUXE 2 . Each multiplexer MUX 1 ′, MUX 2 ′, . . . , MUX 10 ′ has eight multiplexer inputs and a corresponding number of buffers. The eight multiplexer inputs of the multiplexer MUX 1 ′ are connected to the four taps of the two memory locations T 1  with reference to the I signal component and the Q signal component, etc. In other words, each of the ten multiplexers MUX 1 ′, MUX 2 ′, . . . , MUX 10 ′ is assigned exactly one pair of memory locations T 1 , T 1 ; T 2 , T 2 ; . . . ; T 10 , T 10  of the two shift registers SR 1  and SR 2 . 
     The ten outputs of the multiplexer unit MUXE 2  each have a signal rate of 8/T c . 
     The ten outputs of the multiplexer unit MUXE 2  are fed to a filter circuit FS 2 . The filter circuit FS 2  includes ten multipliers M 1 , . . . , M 10  and an adder ADD, whose ten inputs are connected to the outputs of the multipliers M 1 , . . . , M 10 . 
     The multipliers M 1 , . . . , M 10  operate using the 8-fold chip timing clock. The filter coefficients g 1  to g 40  illustrated in  FIG. 6  are determined, in turn, by ten samples using four-fold oversampling of the spectral filter function (in particular RRC function). In contrast to the design of the filter circuit FS 1  shown in  FIG. 5 , each multiplier M 1 , . . . , M 10  shown here, processes a sequence of, for example, exactly four filter coefficients. That is to say, the multiplier M 1  processes the filter coefficients  9   1-4 , the multiplier M 2  processes the filter coefficients g 5-8 , . . . , and the multiplier M 10  processes the filter coefficients g 37-40 . Since, as mentioned, the multipliers M 1 , . . . , M 10  operate using the 8-fold chip timing clock, each multiplier M 1 , . . . , M 10  sequentially processes four samples of the I signal component, and thereafter four samples of the Q signal component, using in each case the filter coefficients assigned to it. 
     Subsequently, the results of the ten multipliers M 1 , . . . , M 10  are added in the adder ADD. 
     The results of the addition are communicated at a signal rate of 8/T c  to a demultiplexer DMUXE 2  with a buffer. The demultiplexer DMUXE 2  splits the results of the addition into the I signal component and the Q signal component, which are respectively output at a signal rate of 4/T c  at the outputs A 1  and A 2  of the device for spectral signal shaping ESF 2 . 
     The two embodiments ESF 1  and ESF 2  share the common feature that the multipliers of the filter coefficients are used, in a multiplex method, both for the I and for the Q signal components. The result is a reduction in the number of the multipliers implemented. Given a memory length of 10 T c  that is comparable with the embodiments ESF 1  and ESF 2 , the known filter structure shown in  FIG. 3  would include 2×40 multipliers. In contrast, the design of ESF 1  (see  FIG. 5 ) only includes 1×40 multipliers, and the design of ESF 2  (see  FIG. 6 ) includes only 1×10 multipliers. The chip area required for the transmitter chip is reduced simultaneously with the reduction in the number of the multipliers. 
     A further advantageous common feature of the two embodiments consists in that the input signals of the device for spectral signal shaping ESF 1 / 2  need not (no longer) be present in an oversampled state, whereas the output signals of the units ESF 1 / 2  are made available with the (e.g. 4-fold) oversampling required for the further signal processing.