Abstract:
A pipelined analog-to-digital (A/D) conversion system enhances the effective data rate of the converter in direct proportion to the number of stages in the pipeline. The pipelined A/D converter operates in conjunction with a charge-coupled device (CCD) multilevel storage (MLS) in a three-bit (eight-level) implementation. Three comparators are used in the three-bit system arranged in a sequential successive approximation configuration with control circuits and a CCD shift register.

Description:
DESCRIPTION 
     Technical Field 
     This invention relates to a pipelined, sequential successive approximation analog-to-digital converter. More particularly, this invention relates to such a converter as adapted to convert analog data stored in a charge-coupled device (CCD) multilevel storage (MLS) memory into the corresponding binary signals. 
     An object of this invention is to provide an improved data conversion system. 
     Another object of this invention is to provide an improved CCD multilevel storage to binary data conversion system. 
     Background Art 
     U.S. Pat. No. 3,968,486 issued July 6, 1976 to Gerdes on an application filed June 20, 1974 describes an electronic analog-to-digital converter utilizing a plurality of analog comparators, all comparators receiving a common analog input and separate respective reference voltages for comparison. The outputs of the comparators provide respectively the digital word output of the analog-to-digital converter wherein the output state of the comparators are dependent upon the output state of the higher order comparators and where the resolution of the analog-to-digital converter is dependent on the number of stages of comparators utilized. The reference voltage for the least significant digital bit is determined by all the higher order digital outputs. The analog-to-digital converter disclosed is of the asynchronous type not requiring a clock signal and the total analog-to-digital conversion time is nT c , where n is the number of comparator stages and T c  is the response time of an individual comparator. 
     The analog-to-digital converter of the present invention is different from the system of the patent in that one input (not common) is applied to the first comparator, the disclosed system employs charge packets rather than analog voltages though not restricted to such, and the output states of the disclosed comparators are not dependent on the output state of the higher order comparator in the same manner as shown in the Gerdes patent. Also, at any given time each stage of the pipelined system is decoding a different analog input quantity. In addition, the analog quantities to be decoded are periodically shifted from one stage to the next down the pipeline. 
     Additional prior art includes Klein, &#34;Successive-Approximation Analog-to-Digital Converter Using Josephson Devices,&#34; U.S. Pat. No. 3,949,395; Means, &#34;Analog to Digital Conversion by Charge Transfer Device,&#34; U.S. Pat. No. 3,930,255; Waehner, &#34;Bipolar A/D Converter Using Two Comparators,&#34; U.S. Pat. No. 3,982,240; Fletcher, &#34;Analogue to Digital Converters,&#34; U.S. Pat. 3,967,269; Smith, &#34;Charge Transfer Device Decoder and Compander,&#34; U.S. Pat. No. 3,903,543; Ailen, &#34;Successive Approximation Analog to Digital Converter,&#34; U.S. Pat. No. 3,964,061; Sandford, &#34;Digital to Analog Converter,&#34; U.S. Pat. No. 3,967,272; and Pastoriza, &#34;Integrated-Circuit; Digital-to-Analog Converter,&#34; U.S. Pat. No. 3,978,473. Patents which relate to CCD devices include Elmer et al, &#34;Multiphase Series-Parallel-Series Charge-Coupled Device Registers,&#34; U.S. Pat. No. 4,008,446; Barton et al, &#34;Isolation Element CCD Serial-Parallel-Serial Analog Memory,&#34; U.S. Pat. No. 3,914,748; Ert, &#34;Serial-Parallel-Serial CCD Memory with Interlaced Storage,&#34; U.S. Pat. No. 3,914,077; Boyle et al &#34;Information Storage Devices,&#34; U.S. Pat. No. 3,858,232; Merrill et al, &#34;Loop Organized Serial-Parallel-Series Memory Storage System,&#34; U.S. Pat. No. 4,130,894; and Heller et al, U.S. patent application Ser. No. 785,723, filed Apr. 7, 1977 for a &#34;Charge Transfer Device Differencing Circuit&#34;; Yee, &#34;Adaptive Leakage Compensation for CCD,&#34; IBM Technical Disclosure Bulletin 21, No. 5, 2144-2145 (1978). A circuit for comparing the magnitude of CCD charge packets is described in Terman et al, &#34;High Sensitivity Charge Comparator for Sensing and Comparing Very Small Charge Packets,&#34; IBM Technical Disclosure Bulletin 21, No. 3, 1262-3 (1978). 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a block diagram of a pipelined, sequential successive approximation analog-to-digital converter implemented by CCD and MOSFET technologies on the same substrate. 
     FIG. 2A shows a plan view of the structure of the shift register shown in FIG. 1. 
     FIG. 2B shows a sectional view of the shift register of FIG. 2A taken along line 2B--2B in FIG. 2A. 
     FIG. 3 is a timing diagram with the vertical axes indicating whether a clock pulse is up or down (on or off and where &#34;up&#34; is the &#34;1&#34; level and down is the &#34;0&#34; level). 
     FIG. 4 is a schematic plan view of the pipeline circuit shown in FIG. 1 implemented in CCD devices. 
     FIG. 5 is a timing diagram of additional clock pulses adapted to control the pipeline of FIG. 4. 
     FIG. 6 is an electrical schematic diagram of a comparator circuit in part, a segment of FIG. 4 in part, and a schematic representation of CCD potential wells in part. 
     FIG. 7 is a timing diagram for the pulses in FIG. 6 which is analogous and in addition to FIGS. 3 and 5 above. FIGS. 3, 5, and 7 are all drawn to the same time scale and are divided into separate figures simply to provide a simpler presentation of the timing data for easier understanding. 
     FIG. 8 is an electrical schematic diagram which shows the DAC C circuit of FIG. 1. 
    
    
     DISCLOSURE OF INVENTION 
     FIG. 1 shows a block diagram of a pipelined, sequential successive approximation analog-to-digital converter implemented by means including &#34;Charge Coupled Device&#34; and &#34;MOS Field Effect Transistor&#34; (MOSFET) technologies which are made on the same substrate. 
     Assuming n-channel technology for purposes of illustration a four-phase CCD shift register 8 receives data at input 7 in the form of &#34;charge packets&#34; Q comprised of minority carriers (electrons). Flow of data through the shift register 8 is controlled by pulses from the repetitive, sequential phase, clock pulse sources P 1  -P 4  in a manner well known to those versed in the art. The clock pulses move the charge packets Q towards output 21 for introduction into a pipeline circuit 9. Pipeline circuit 9 is a modified CCD shift register which is adapted to present the charge packets Q for measurement of their charge magnitude by a sequential successive approximation method. The method is performed by presenting each charge packet Q first to a comparator AA at position A, then to comparator BB at position B, and finally to comparator CC at position C sequentially in time. This process is pipelined in the sense that, for example, comparator AA is able to work on measuring the third packet Q 3  while comparators BB and CC are still working on the second packet Q 2  and the first packet Q 1  respectively. 
     The analog-to-digital conversion process of a given charge packet Q 1  will be explained first. Assume that the value of charge packet Q 1  is defined to vary from a minimum fractional value of 0 to a maximum fractional value of 1. Assume also that the charge packet will be decoded into a three-bit (eight level) representation. Packet Q 1  first moves from position 21 to position A in pipeline circuit 9. Then the highest order comparator AA receives an input signal proportional to the value of the charge Q 1  on line 37. A reference charge value of 1/2 is supplied to comparator AA from DAC A on line 34 which supplies it to pipeline 9. Pipeline 9 provides to comparator AA a proportional signal with the same proportionality as for the charge packet Q 1 . Comparator AA compares the unknown charge packet Q 1  and the reference charge packet of functional value 1/2, and produces a binary &#34;1&#34; or &#34;0&#34; signal which appears on lines 41 and 43 with delays introduced by delay circuits D. The signals on lines 41 and 43 to indicate the most significant bit in the three bit binary representation of the analog charge packet Q 1 . 
     After the above comparison, packet Q 1  moves to position B. Subsequently DAC B supplies the value of 1/4 or 3/4 through line 54 to the pipeline circuit 9 in analogous fashion to DAC A. The comparison by comparator AA on packet Q 1  in the previous cycle determines whether 1/4 or 3/4 is to be produced by DAC B. A proportional signal is then supplied to comparator BB which is used to determine the next most significant bit of packet Q 1 . 
     The output of comparator AA is binary, i.e., a &#34;1&#34; or &#34;0&#34;. If the value of the charge packet Q 1  is greater than 1/2, the output of the comparator AA is &#34;1&#34;. Otherwise, it is &#34;0&#34;. After a delay time D required for the packet Q 1  to move into position B in the pipeline circuit 9, logic B receives the output signal on line 41. If the binary value is &#34;1&#34;, DAC B is set via line 52 to emit a charge value of 3/4 to comparator BB as the reference signal for the charge packet Q 1  at position B. Alternatively, if the output of comparator AA for charge packet Q 1  was &#34;0&#34;, then logic B is caused to set DAC B on line 52 to emit a charge value of 1/4 on line 54 to comparator BB. 
     Comparator BB compares the signal charge packet value Q 1  with the reference charge packet value from DAC B, which is either 1/4 or 3/4. If the value of Q 1  is greater than the charge value from DAC B, then a &#34;1&#34; output on line 61 is produced after a delay D; if it is less a &#34;0&#34; output is produced. This output is the &#34;next most significant bit&#34; (NMSB) in the three bit binary representation of the analog charge packet Q 1 . Charge packet Q 1  is now moved to position C in the pipeline circuit 9. At this point, the process performed previously by the other comparators is repeated in an analogous fashion. The inputs on lines 43 and 61 cause logic C to generate a value of either 1/8, 3/8, 5/8, or 7/8. If lines 43 and 61 are both &#34;1&#39;s&#34;, then the DAC C will be set to 7/8 by logic C. The remaining permutations are explained in Table I which reads as follows: 
     
                       TABLE I______________________________________   line 43           &#34;1&#34;      &#34;0&#34;______________________________________line 61   &#34;1&#34;         7/8        3/8     &#34;0&#34;         5/8        1/8______________________________________ 
    
     The comparison of charge Q 1  with the reference charge packet value from DAC C via line 74 is made by the comparator CC. The output of comparator CC is presented on line 84 as a &#34;0&#34; or a &#34;1.&#34; The signal on the line indicates the value of the &#34;least significant bit&#34; (LSB) in the three-bit binary representation of the analog charge packet Q 1 . 
     The binary value of the signals at points 44, 64 and 84 from the delay units to line 44, unit D to line 64, and from comparator CC directly to line 84 at that time indicates the three-bit binary representation of charge Q 1 . If charge Q 1  produced positive values from all three comparators AA, BB and CC, then the output will be all &#34;1&#39;s&#34; indicating a value of 7/8. The fractional to three-bit binary conversion Table II is as follows: 
     
                       TABLE II______________________________________       THREE-BIT BINARY VALUESFRACTIONAL  LINESVALUES      44         64         84______________________________________  7/8-1.0   &#34;1&#34;        &#34;1&#34;        &#34;1&#34;3/4-7/8     &#34;1&#34;        &#34;1&#34;        &#34;0&#34;5/8-3/4     &#34;1&#34;        &#34;0&#34;        &#34;1&#34;1/2-5/8     &#34;1&#34;        &#34;0&#34;        &#34;0&#34;3/8-1/2     &#34;0&#34;        &#34;1&#34;        &#34;1&#34;1/4-3/8     &#34;0&#34;        &#34;1&#34;        &#34;0&#34;1/8-1/4     &#34;0&#34;        &#34;0&#34;        &#34;1&#34;0-1/8       &#34;0&#34;        &#34;0&#34;        &#34;0&#34;______________________________________ 
    
     In actual practice, more bit positions can be employed as will be obvious to one having ordinary skill in the art, but this structure suffices for purposes of explanation. 
     Best Mode for Carrying out the Invention 
     FIG. 2A shows a plan view of shift register 8 in FIG. 1. A number of storage electrodes 10, 12, 14, 16, 18, and 20 composed of a conductive material, such as polysilicon, are formed over a thin layer of oxide 48 on a silicon chip 46, as can be seen in FIG. 2B, which is a sectional view taken along line FIG. 2B--FIG. 2B in FIG. 2A. The polysilicon storage electrodes 10, 12, 14, 16, 18 and 20 are connected alternately to receive clock pulses from lines P 4  and P 2  as indicated. The substrate 46 is composed of P-type semiconductor material (with n-channel technology used for purposes of illustration). Covering the electrodes 10, 12 . . . 18 and 20 is a thin insulating layer of silicon dioxide 47 serving to support and insulate an additional second layer of transfer electrodes. The transfer electrodes 11, 13, 15, 17 and 19 are also composed of a material such as polysilicon, and they are connected alternately to receive either one of clock pulses P 3  and P 1 , as indicated. Transfer electrodes 11, etc. are deposited upon the silicon oxide layer 47 with their ends overlapping the adjacent edges of the storage electrodes 10 and 12, 12 and 14, 14 and 16, 16 and 18, 18 and 20 respectively, in the well known overlapping type of structure for CCD transfer electrodes. 
     A charge-coupled device is essentially an assembly of transfer electrodes interconnected in a periodic manner, which, when properly pulsed, produce a moving array of potential wells. The propagation of charge packets in such a moving array of potential wells is well-known by one skilled in the art. 
     Assume that a packet of charge Q 1  composed of electrons is stored in potential well 10&#39; shown in phantom in FIG. 2B beneath storage electrode 10. It is desired to propagate the charge packet Q 1  along through the shift register 8. If the potentials on electrodes 11 and 12 are raised, potential wells 11&#39; and 12&#39; are created under electrodes 11 and 12. When potential on electrode 10 is then lowered, charge from charge packet Q 1  will flow from well 10&#39; through transfer region 11&#39; beneath the transfer electrode 11 into the charge well 12&#39; formed beneath the larger storage electrode 12. If the potential on the transfer electrode 11 is dropped subsequently, then the entire packet of charge Q 1  is transferred into the storage well 12&#39; beneath storage electrode 12. 
     FIG. 3 is a timing diagram with the vertical axes indicating when a clock pulse is up (on) or down (off). When the clock pulse is on, the line rises to its higher value. When it is off, the pulse drops to its lower value. Assume that the charge packet Q 1  starts in well 10&#39; at time t 5 . Just after time t 6 , P 3  rises briefly followed by a short drop of P 4  for most of the time from t 6  to t 8 . Thus the charge packet Q 1  moves to the right under transfer electrode 11. Note that electrode 12 is under the control of P 2  which is at a positive value so a portion of packet Q 1  moves under electrode 12 into well 12&#39;. Halfway from t 7  to t 8 , P 3  drops forcing the remainder of packet Q 1  to move into charge well 12&#39;. 
     On the next cycle of the pulse train P 2 , after time t 3 , P 2  drops to a potential low enough to empty well 12&#39;. At the same time P 1  is up (t 3 ) raising the potential on transfer electrode 13. Further, P 4  is up, so Q 1  flows into well 14&#39; via transfer region 13&#39;. At time t 4 , P 1  drops again and transfer region 13&#39; empties as the remaining charge flows into well 14&#39;. One complete cycle of movement of a charge packet under the control of P 3 , P 4 , P 1 , and P 2  has been described. 
     The process of charge transfer repeats itself in the sense that electrode 14 is analogous to electrode 10, 15 to 11, 16 to 12, and 17 to 13, and so forth because they are attached to the same respective clock pulse lines. After time t 6 , P 3  rises to permit the flow of Q 1  from well 14&#39; through transfer region 15&#39; which flows readily into well 16&#39; because the voltage of P 2  is up at time t 6 . At the same time additional charge packets Q n , Q n-1 , Q n-2  are moving from well 10&#39; to well 12&#39;, well 18&#39; to 20&#39;, etc., under the control of the same clock pulses. With this type of CCD arrangement, it is necessary to keep the successive charge packets Q 1 , Q 2 , . . . Q n  moving through the shift register separated from each other by a potential barrier such as the regions 11&#39;, 13&#39;, 15&#39;, 17&#39; and 19&#39;  beneath electrodes connected to P 3  and P 1 . Thus, wells 10&#39;, 14&#39; and 18&#39; can be filled with packets Q 3 , Q 2 , and Q 1  respectively which had come from position 7 into shift register 8. At the same time, wells 12&#39;, 16&#39; and 20&#39; are necessarily empty to facilitate transfer of packets. Well 20&#39; is empty awaiting the arrival of packet Q 1  a moment later when pulse trains P 2  and P 3  are positive and P 4  drops. Well 16&#39; is awaiting Q 3  and well 12&#39; is awaiting Q 3 . In other words, at any given time looking at any two adjacent wells, one of the two should be filling or full and the other should be empty or emptying as the charge packets move from left to right. 
     FIG. 4 shows a schematic plan view of the CCD structure within the pipeline circuit 9 of FIG. 1. The pipeline circuit 9 in FIG. 1 consists of three operationally identical stages S A , S B , and S C . A, A+1, B, B+1, C, and C+1 are storage electrodes and 21, 23, 25, 27, 29 and 31 are transfer electrodes laid out in a manner similar to the alternated transfer and storage regions shown in FIG. 2A. 
     In stage S A , transfer electrode 21 from shift register 8 extends to a storage electrode A. Storage electrode A is connected by a transfer electrode 34 to DAC A (FIG. 1) for receipt of charge packets Q DAC  A from DAC A when pulse source P 8  is up (as in FIG. 5 from time t 10  to t 11 ). Storage electrode A has a thin film at metalization 37 connected to it to conduct the voltage thereon to comparator AA. Transfer electrodes 23 and 25 and intermediate storage electrode A+1 are connected in the same fashion as transfer electrodes 11 and 13 and storage electrode 12 in shift register 8 in FIGS. 2A and 2B. The intermediate storage electrode A+1 serves the purpose of storing a charge packet such as Q n  in the potential well (A+1)&#39; below intermediate storage electrode A+1 during the interval of time from t 8  of a given cycle to t 3  of the next cycle, whereupon pulse train P 1  goes on and pulse train P2 goes off, causing the charge packet to be moved out from under storage electrode (A+1). Storage electrode A is also coupled to a transfer electrode 35 for the purpose of transferring charge from storage well A&#39; to diffused region A x  when pulse train P 10  is on. Diffused region A x  is connected to a supply voltage V DD . Pulse train P 10  is sufficiently positive in the on condition that the associated potential well 35&#39; below transfer electrode 35 is more positive (lower potential for electrons) than the most positive level that potential well A&#39; below storage electrode A can achieve, and supply V DD  is sufficiently positive that diffused region A x  is always more positive than potential well 35&#39;. As a result any charge residing in potential well A&#39; when pulse train P 10  goes on will be attracted to the most positive potential, and will move to diffusion A x  by way of potential well 35&#39;, and be removed by the power supply V DD . Thus, when pulse train P 10  goes on, all charge in potential well A&#39; will be removed. 
     Storage electrode A+1 is connected by transfer electrode 25 to electrode B of the succeeding stage S B , which is analogous to transfer electrode 21. 
     The operation of stage S A  is as follows: at time t 2 , the beginning of an operational cycle, a charge packet Q 1  is in the last well 20&#39; of shift register 8, and the previous charge packet from shift register 8 Q 0  is in potential well (A+1)&#39; below storage electrode (A+1). Storage electrode A is precharged to a voltage level by the comparator AA via interconnection 37. From t3 to t5 the result of pulse trains P 1  and P 2  is to cause charge packet Q 1  to move to potential well A&#39;, and to cause charge packet Q 0  to move to potential well B&#39; in the next stage. 
     At time t 5 , storage electrode A is made electrically &#34;floating&#34; at potential V A . That is, it is disconnected from any D.C. potential. When &#34;floating&#34;, the potential of storage electrode A will vary in response to changes in the charge condition in the corresponding well A&#39; beneath electrode A. The voltage on electrode A is still conducted to comparator AA via interconnection 37. 
     Between time t 6  and t 8 , the effect of pulse trains P 3  and P 4  is to cause all charge in potential well A to be moved from beneath electrode A to beneath storage electrode A+1. This requires that the potential well 23&#39; under transfer electrode 23 be sufficiently positive that all charge in packet Q 1  in potential well A&#39; will drain out of A&#39; when pulse train P 3  is on, and pulse train P 2  must be sufficiently positive that all charge in packet Q 1  will go under storage electrode (A+1) when pulse train P 3  goes off subsequently. 
     As a result of the removal of charge packet Q 1  from potential well A&#39;, a positive voltage change ΔV 1  proportional to Q 1  is induced on floating electrode A. At time t 8  electrode A remains floating at its new potential V A  +ΔV 1 . 
     Beginning at time t 10  a reference charge packet Q DAC  A, from DAC A, is moved under floating electrode A in a manner analogous to that described previously when pulse train P 8  goes off at time t 11 . This induces a negative voltage change ΔV DAC  A, proportional to Q DAC  A, on floating electrode A. At time t 11  electrode A is floating at a potential given by 
     
         V.sub.A +ΔV.sub.1 -ΔV.sub.DAC A 
    
     At time t 12  comparator AA is pulsed to determine if the net difference voltage induced on electrode A is positive or negative; i.e., if ΔV 1  -ΔV DAC  A is greater or less than zero. If it is greater than zero, Q 1  is greater than Q DAC  A, and if it is less than zero, Q 1  is less than Q DAC  A. 
     After comparator A has compared Q 1  and Q DAC  A, at time t 1  pulse train P 10  goes on causing the charge Q DAC  A under electrode A to be transferred to diffusion A x  and to be removed by the power supply V DD . The comparison cycle concludes with charge packet Q 1  in potential well (A+1)&#39;, the next charge packet Q 2  in potential well 20&#39; in the last stage of shift register 8, and the comparator indicating whether Q 1  was greater than or less than the reference charge packet Q DAC  A from DAC A. At the beginning of the next cycle, packet Q 1  is moved into storage well B&#39; in stage B and charge packet Q 2  is moved into storage well A&#39; in stage A. 
     As can be seen from FIG. 4, stages S B  and S C  are operationally identical with stage S A . Thus, simultaneous with the operations of moving charge packet Q 1  and comparing it to a reference charge packet from DAC A, the previous charge packet Q 0  is moved and compared to a reference charge packet from DAC B in stage S B , and the next previous charge packet Q -1  is moved and compared to a reference charge packet from DAC C. In this manner the pipelined analog-to-digital conversion as described in conjunction with FIG. 1 is accomplished. Additional stages beyond C can be added to obtain addition resolution in the analog-to-digital conversion. 
     After a charge packet has gone through the pipeline, it is conducted out of the pipeline via a transfer electrode, such as electrode 33 in stage C for the three stage case, to a diffused region (not shown in FIG. 4) connected to a high positive voltage, analogous to regions A x , B x  and C x  in FIG. 4, where the charge is removed to the voltage supply. 
     FIG. 8 is a schematic diagram of a DAC C which illustrates how a charge packet Q DAC  C is generated as a function of the digital (binary) inputs which in turn were generated by logic C. DAC C employs a network consisting of binary-weighted capacitors 110, 111, 112, and 113 having relative capacitances of 1/8, 1/2, 1/4, and 1/8 respectively. Associated switching elements 115, 118, and 121 are controlled by the digital inputs MSB, NMSB and LSB when P 7  is positive through the AND gates. Switching elements 115, 118, and 121 are shown as mechanical switches for convenience of illustration although it will be understood that switching circuits such as FET devices are appropriate to this embodiment. Also included in the circuit is capacitor 150, FET device 129, storage electrode W, and its associated transfer electrode 74 which are necessary to transfer charge Q DAC  C to the well C&#39; below electrode C. A general description of the operation of a two stage weighted DAC system may be found in U.S. Pat. No. 4,077,035 of Y. S. Yee entitled &#34;Two Stage Weighted Capacitor Circuit for Analog-to-Digital and Digital-to-Analog Converters&#34;. Working in conjunction with the pipelined sequential successive approximation system, the operation of DAC C is divided into two parts. First, the DAC is initially reset by input P 7  from times t 1  -t 6  by the off outputs from the AND gates A which permit the armatures of switches 115, 118, and 121 to connect capacitors 111, 112, and 113 via lines 117, 119, and 122 respectively to positive potential source V REF . During this initialization phase, node S is reset to ground by FET device 125, connected by line 126 to ground by input P 10  from t 1  to t 2 . Node S is then precharged to one threshold voltage V t  below the gate potential V DC  via the FET device 129 (operating in the bucket brigade mode as in U.S. Pat. No. 4,035,667 of L. G. Heller entitled &#34;Input Circuits for Inserting Charge Packets Into a Charge-Transfer-Device&#34;), line 132, electrode W, transfer electrode 130, N +  diffusion 131 from the potential source V DD  during time t 3  to t 6  in response to input P 11  on electrode 130. P 11  goes low at time t 6  to turn off electrode 130, isolating the V DD  source and completing the precharge operation. At t 6  time, the precharge operation is completed and the DAC C circuit is ready to produce charge Q DAC  C to be sent to the electrode C for comparison with Q n . 
     To produce the required charge Q DAC  C, logic C in FIG. 1 provides the DAC input combination as provided in Table I above. Raising P 7  at time t 6  permits the DAC inputs (MSB, NMSB and LMSB) to pass the AND gates A and to operate the appropriate switches 115, 118 and 121. A switch is operated if the corresponding input is a &#34;1&#34; and is not operated if it is a &#34;0&#34;. The resultant switching of the appropriate capacitors 111, 112 and 113 as a function of the digital inputs produces charge Q DAC  C (see Heller). The operation of the DAC by switching the appropriate capacitors from the V REF  position to ground causes node M to drop to a lower potential by an amount ΔV M  which is proportional to the digital inputs, such that Q DAC  C =C c  ΔV M , and is therefore proportional to the analog value of the digital inputs as given by Table II. Device 129, originally off, turns on at t 6  in response to the negative ΔV M  to charge node S back to the essentially off state and the associated charge packet Q DAC  C is collected in potential well W&#39; under electrode W. Pulsing P 8  on between t 10  to t 11  to lower the potential barrier under transfer electrode 74 and dropping P 6  between t 10  and t 11  forces the charge packet Q DAC  C to flow from potential well W&#39; to potential well C&#39; under electrode C where the comparison operation, part of the pipelined sequential successive approximation A/D function, is performed as described previously. 
     Referring to FIG. 6 and the associated timing diagram FIG. 7, the operation of the comparator circuit is divided into two distinct phases. The first is the precharge phase and the second is the comparison phase. During the precharge phase φ 0  rises high and FET device 80 in comparator XX (representative of COMPARATORS AA, BB, and CC) sets the bias point. Clock φ 0  also resets nodes F and G of the cross-coupled charge transfer latch CTL via the devices 86 and 88. Latch CTL, as in U.S. Pat. No. 4,039,861 of L. G. Heller et al entitled &#34;Cross-Coupled Charge Transfer Sense Amplifier Circuits&#34;, includes FET devices 90, 94, 92, 96, 98, 100, 86 and 88 as well as capacitors 102, 106, 104 and 108. Latch CTL is connected to the output of charge amplifier CA. Charge packet Q n , which is to be compared with charge packet Q DAC  X, representative of charge packets Q DAC  A, Q DAC  B, and Q DAC  C, is placed in well X&#39; which represents any one of wells A&#39;, B&#39; and C&#39;. When φ 0  drops at time t 4  node N and electrode X representative of electrodes A, B, and C of pipeline 9 become electrically floating. Clock signal φ 1  precharges nodes F and G (from t 3  to about t 6 ) via FET devices 90 and 92 for node F and FET devices 94 and 96 for node G. The transient created through device 80 by clock signal φ 0  going off at time t 4  is absorbed by the precharging action at node F. At the end of the precharging operation, the charge amplifier CA is biased, the latch CTL is critically balanced in the sense that the nodes F and G are each precharged to one threshold below the gate voltages of devices 92 and 96 respectively so that devices 92 and 96 are just at cutoff, and charge packet Q n  is in the CCD well X&#39;. 
     To perform the comparison operation, charge Q n  is then transferred out of well X&#39; when P 2  and P 3  are up between times t 6  and t 8 , creating a positive voltage proportional to charge Q n . Then Q DAC  X is transferred into well X&#39; from DAC X when P 8  goes on at t 10  and off at t 11 , creating a negative voltage transient proportional to Q DAC  X to produce a difference signal at the input node N. Devices 82 and 84 operate as a source follower, resulting in an attenuated difference signal at the output of the charge amplifier CA. This attenuated difference signal is coupled to node F through capacitor 102. Although the difference signal voltage at node F is less than the difference signal at node N, charge amplification is achieved because the capacitance of node F can be made larger than that of node N. 
     The positive-going ramp of clock signal φ 2  at t 12  amplifies the signal charge placed in node F and develops an amplified difference signal between nodes H and I. A positive signal at node F will result in a positive voltage on node H with respect to node I, V HI , and a negative signal results in a negative voltage. 
     The falling edge of clock signal φ 3  between t 13  and t 14  and the rising edge of φ 1  at time t 14  causes the cross-coupled charge transfer latch CTL to go into one of its two stable states, depending upon the polarity of V HI . Normal logic levels are attainable at nodes H and I. Since a positive transient, as a result of Q n  transferring out, is always experienced first at node F, premature latchup of the comparator cannot occur since FET device 92 operates in the bucket brigade device mode. 
     Industrial Applicability 
     This system provides conversion of analog signals to digital representation. For example, telephone signal processing equipment requires such systems. It is also widely applicable to industrial applications as described in &#34;Electronic Analog/Digital Conversions&#34; by Herman Schmid, Van Nostrand Reinhold Company 1970.