Abstract:
The carrier tracking loop technique and apparatus provides smooth, accurate frequency tracking, fast reacquisition and doppler tracking over a wide dynamic range. The loop parameters of the carrier tracking loop are varied as a function of mode, i.e. flywheel, tracking or reacquisition modes. The various modes of operation are automatically detected and loop operation is enhanced by non-linear techniques. The enhancements include fourth power sample normalization to improve performance over a large dynamic range and to ease fixed point scaling. A slope limiter is included which aids in coherent detection by reducing phase noise introduced by the carrier tracking loop. Also, a predifferentiation filter further aids in coherent detection by reducing phase noise.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is related to U.S. Pat. No. 5,579,345 by Brian W. Kroeger, Jeffrey S. Baird and Joseph B. Bronder entitled &#34;Carrier Tracking Loop for QPSK Demodulator&#34;; U.S. Pat. No. 5,768,323 by Brian W. Kroeger, Joseph B. Bronder, Todd A. Oblak and Jeffrey S. Baird entitled &#34;Symbol Synchronizer Using Modified Early/Punctual/Late Gate Technique&#34; and U.S. Pat. No. 5,566,214 by Brian W. Kroeger and Jeffrey S. Baird entitled &#34;Automatic Noise Normalization and Reacquisition Control for a QPSK Demodulator Symbol Tracking Loop&#34;, which are all incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an improved carrier tracking technique and apparatus intended for use with a QPSK or π/4QPSK demodulator and providing enhanced performance including smooth accurate frequency tracking, fast reacquisition and doppler tracking over a wide dynamic range. 
     2. Description of the Background Art 
     The purpose of a carrier tracking loop is to minimize the carrier frequency offset error in a digital receiver after a QPSK (quadrature phase shift keying) or π/4QPSK modulated signal has been translated from an RF or IF frequency to near baseband. The residual frequency offset error may be due to any of several sources including doppler, inaccurate local oscillators at either the transmitter end or receiver end, or intentional offset included to eliminate the effects of DC offset due to inadvertent carrier leakage in a receiver front end. 
     Frequency tracking can be used with either coherent, partially coherent or differential QPSK detection. A frequency-locked loop (FLL) instead of a phase-locked loop (PLL) is preferred since the phase estimation is performed separately in the detection process. Another advantage of a frequency locked loop over a phase-locked loop is that the frequency locked loop has a wider capture range than the phase-locked loop. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide an improved carrier tracking technique and apparatus, intended for use with a π/4QPSK or QPSK demodulator in a preferred embodiment, which meets conflicting requirements of smooth, accurate frequency tracking, fast reacquisition and doppler tracking over a wide dynamic range which are not generally achievable with conventional carrier tracking techniques and apparatus. 
     A further object of the present invention is to provide a carrier tracking loop technique and apparatus having improved automatic flywheel/tracking/reacquisition mode detection and control. 
     A still further object of the present invention is to provide an improved carrier tracking loop technique and apparatus having normalized signal processing for well-behaved closed loop operation over a very large dynamic range of input signal. 
     An additional further object of the present invention is to provide an improved carrier tracking loop technique and apparatus having SNR (signal to noise ratio) estimation and error signal processing which allows the carrier tracking loop to flywheel when signal fading occurs, such as in a mobile communications application for example. 
     A yet further object of the present invention is to provide an improved carrier tracking loop technique and apparatus which implements low pass filtering of fourth-power samples before differentiation extends tracking performance down below 3 db Eb/No with sufficient gain to handle doppler variation (about 1% of symbol rate). 
     An additional further object of the present invention is to provide an improved carrier tracking loop technique and apparatus having slope limiting of the carrier tracking loop error signal for reducing phase noise introduced by the carrier tracking loop while retaining fast reacquisition response times. 
     The above-noted and other objects of the present invention are fulfilled by providing a carrier tracking loop having a mixer for mixing a received signal with a local oscillator signal to translate the received signal to a near baseband signal; an oscillator for generating the local oscillator signal in accordance with an error signal; a symbol synchronizer for sampling the near baseband signal at an optimum symbol timing and for outputting symbol samples; and loop control processing for generating the error signal in accordance with the symbol samples, determining a signal to noise ratio of the symbol samples and adjusting a gain of the carrier tracking loop in accordance with the determined signal to noise ratio. In a preferred embodiment, the loop control may include a slope limiter for limiting a slope of the error signal. 
     The above-noted and other objects of the present invention can also be fulfilled by a method of tracking a carrier signal in a carrier tracking loop including a) generating a local oscillator signal in accordance with an error signal; b) mixing a received signal with the local oscillator signal to translate the received signal to a near baseband signal; c) sampling the near baseband signal at an optimum symbol timing to provide symbol samples; d) generating the error signal in accordance with the symbol samples; e) determining a signal to noise ratio of the symbol samples; and f) adjusting a gain of the carrier tracking loop in accordance with the determined signal to noise ratio. The method of tracking a carrier signal may further include limiting a slope of the error signal. 
     Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitative of the present invention and wherein: 
     FIG. 1 illustrates a simplified block diagram of a direct conversion receiver including a QPSK demodulator; 
     FIG. 2 illustrates a block diagram of a carrier tracking loop of a preferred embodiment of the present invention; 
     FIG. 3(a) illustrates a QPSK constellation with a signal represented as one of four possible data points; 
     FIG. 3(b) illustrates the four possible data points of the QPSK constellation of FIG. 3(a) collapsed to a single point; 
     FIG. 4(a) illustrates a QPSK constellation wherein the four possible data points are offset from the zero angle by a small arbitrary phase angle; 
     FIG. 4(b) illustrates the four possible data points of the QPSK constellation of FIG. 4(a) collapsed to a single point along the unity circle; 
     FIG. 5 illustrates a filtered estimated error signal on a QPSK constellation within the unity circle; 
     FIG. 6 illustrates a simplified block diagram of the loop control circuit of FIG. 2 including the corresponding signals output therefrom to the slope limiter; and 
     FIG. 7 illustrates the error signal estimate with straight line approximation. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A block diagram of a direct conversion receiver including a QPSK demodulator is illustrated in FIG. 1. The received signal is respectively filtered and amplified by bandpass filter 102 and low noise amplifier 104 and subsequently provided to mixers 108 and 110. Local oscillator 106 is approximately tuned to the complex conjugate of the carrier frequency of the received signal. The local oscillator signals are used to translate or multiply the received signal to a baseband or near baseband data waveform consisting of complex pulses having complex real and imaginary polarities which represent the data stream. These in-phase and quadrature signal components are subsequently filtered and digitally converted in low-pass filters 112 and A/D converters 114, respectively. Digital samples of the baseband in-phase and quadrature signal components are provided to carrier tracking loop 116. Carrier tracking loop 116 attempts to minimize the frequency offset error. The corrected symbol samples are subsequently provided to QPSK detector 118. 
     FIG. 2 illustrates a schematic block diagram of a demodulator carrier tracking loop according to an embodiment of the present invention. In a preferred embodiment, the carrier tracking loop may be part of a QPSK or π/4QPSK demodulator, but is understood not to be limited thereto. In general, the carrier tracking loop is a closed-loop servo mechanism which attempts to keep the frequency of numerically controlled oscillator 210 equal to the complex conjugate of the incoming offset-baseband carrier frequency through negative feedback. 
     The offset baseband in-phase I0 and quadrature Q0 signal components are input to complex multiplier 200 and may be represented as 
     
         S.sub.input (m)=A.sub.m QPSK(m)e.sup.j(2πf.sbsp.off.sup.mT.sbsp.sample.sup.+φ.sbsp.m.sup.) +noise.sub.input (m)                                      (1). 
    
     The in-phase I0 signal component is provided as a first input to multipliers 201 and 204. The quadrature Q0 signal component is provided as a first input to multipliers 202 and 203. 
     Numerically controlled oscillator 210 outputs sine signal SIN 211 and cosine signal COS 212, which may be represented as 
     
         S.sub.NCO (m)=e.sup.j2πf.sbsp.NCO.sup.mT.sbsp.sample =e.sup.-j2π(f.sbsp.off.sup.+Δf)mT.sbsp.sample    (2). 
    
     An example of a numerically controlled oscillator is described in detail in copending application U.S. Pat. No. 5,579,345. It is to be understood that numerically controlled oscillator 210 is not limited to such a configuration and that equivalent oscillators as known to those skilled in the art may be used. 
     Sine signal SIN 211 is provided as a second input to multipliers 203 and 204 and cosine signal COS 212 is provided as a second input to multipliers 201 and 202. The outputs of multipliers 201 and 203 are added in adder 205 to provide a frequency corrected in-phase I1 signal component. The output of multiplier 204 is subtracted from the output of multiplier 202 in subtractor 206 to provide a frequency corrected quadrature Q1 signal component. In closed loop operation, the frequency perturbation term Δf is a zero mean random process. The in-phase I1 and quadrature Q1 signal components can be represented as 
     
         S.sub.input (m)S.sub.NCO (m)=A.sub.m QPSK(m) e.sup.j(2πΔfmT.sbsp.sample.sup.+φ.sbsp.m.sup.) +noise(m)(3). 
    
     The in-phase I1 and quadrature Q1 signal components are output to matched filter pair 220 to be matched-filtered synchronously with the symbol timing. An example of a matched filter pair is disclosed in U.S. Pat. No. 5,579,345. It is to be understood however that matched filter pair 220 is not limited to the particular embodiment disclosed in the above-noted patent. Since the matched filter pair 220 is provided within the carrier tracking loop, out of band signals are filtered out allowing the loop to track without interference. 
     The output symbol samples provided from matched filter pair 220 have arbitrary phase offset and some smaller residual frequency perturbations (frequency tracking error), possibly due to acceleration or oscillator drift, which are not corrected by the carrier tracking loop. However, the carrier tracking loop should be designed with parameters α and β as subsequently described such that the residual frequency perturbations are sufficiently small to minimize adverse effects on subsequent detection. Performance of the carrier tracking loop is generally a compromise between frequency tracking response time and loop noise bandwidth with minimum overshoot and ringing. The arbitrary phase offset noted above which is stationary or slowly changing should be removed by the subsequent QPSK detection process, which is not illustrated in FIG. 2. 
     The input sample rate with index m is greater than the symbol rate with index n by a factor equal to the number of complex input samples representing each symbol. The symbol synchronous output samples of matched filter pair 220 can be represented as 
     
         S.sub.MF (n)=a.sub.n e.sup.j(2πΔfnT.sbsp.s.sup.+d.sbsp.n.sup.θπ/2+φ.sbsp.n.sup.) +noise.sub.MF (n)                                  (4). 
    
     wherein d n  may be 0, 1, 2 or 3 dependent upon the pair of information bits representing the nth QPSK symbol, T s  represents the symbol period and φ n  represents the arbitrary phase offset. 
     The symbol synchronous output samples from matched filter pair 220 are provided to symbol shifter 230. It is to be understood that symbol shifter 230 is provided only for the case of π/4QPSK reception, and not for standard QPSK reception. Symbol shifter 230 removes the π/4 shift on alternate soft decision symbols from matched filter pair 220. The π/4 (45°) shift can be achieved by multiplication of alternate complex soft symbols output from matched filter pair 220 by the complex quantity (0.707-j0.707). The purpose of the π/4 shift at the transmitter side is to eliminate RF envelope transitions through zero amplitude. It is to be further understood that the symbol shifter 230 is not limited to the particular embodiment described and that the symbol shift can be provided by different means as would be evident to one of ordinary skill. 
     In the case of π/4QPSK reception, the output of symbol shifter 230 is provided as an output of the carrier tracking loop to a subsequent QPSK detector stage, which is not illustrated in FIG. 2. In the case of QPSK reception, the output of matched filter pair 220 is provided directly to a subsequent QPSK detector stage as the output of the carrier tracking loop. 
     The symbol synchronous in-phase I2 and quadrature Q2 signal components, as provided directly from matched filter pair 220 for QPSK reception or from symbol shifter 230 for π/4QPSK reception as described previously, are also provided to amplitude normalization/fourth power circuit 240. The input signal components are firstly normalized to unity amplitude, thereby removing amplitude from the signal components. Subsequently the signal components are raised to the fourth power in order to remove QPSK modulation. 
     In greater detail, the input to amplitude normalization/fourth power circuit 240 is a sequence of complex (I and Q) soft decision values of arbitrary magnitude, any one value represented in simplified form as 
     
         ae.sup.jθ =I+jQ                                      (5). 
    
     The square of this value normalized to unity magnitude (amplitude) is ##EQU1## The normalized fourth power is computed as the square of the normalized square 
     
         (e.sup.jθ).sup.4 =(x+jy).sup.2                       (7). 
    
     It is to be understood that the square is normalized first before computing the fourth power. This is done for practical purposes to limit the required dynamic range (number of bits) of the calculations. It is to be further understood that amplitude normalization/fourth power circuit may be hardware implemented or alternatively software implemented as would be evident to one of ordinary skill. The in-phase I3 and quadrature Q3 signal components output from normalization/fourth power circuit 240 can be expressed as 
     
         S.sub.MF.sup.4 (n)=e.sup.j(8πΔfnT.sbsp.s.sup.+4φ.sbsp.n.sup.) e.sup.jnoise 4(n)                                         (5). 
    
     Generally, a received signal has a varying amplitude. Upon raising the baseband in-phase I2 and quadrature Q2 signal components to the fourth power, or equivalently squaring the signals twice in circuit 240, the dynamic range is greatly increased. However, increasing the dynamic range may result in overflow since a bit range of the corresponding receiver processing circuitry may be greatly exceeded. Since the carrier tracking loop is designed to adjust the frequency of the numerically controlled oscillator 210 to be the complex conjugate of the carrier frequency, and since the carrier tracking loop extracts a phase from the baseband in-phase I2 and quadrature Q2 signal components, the overflow problem is resolved by amplitude normalization/fourth power circuit 240 which limits the complex amplitude to unity amplitude, as will be described hereinafter. 
     FIG. 3(a) illustrates a QPSK constellation wherein a signal can be represented as one of four possible data points in the constellation. The carrier component of the baseband in-phase I2 and quadrature Q2 signal components output matched filter 220 as represented by Equation (4) is assumed to be e -j2 πf.sbsp.c wherein the dπ/2 exponent represents the data such that d=0, 1, 2 or 3. In the absence of noise, upon raising this signal to the fourth power, the exponent is multiplied by four such that the information part of the exponent becomes 2πd, effectively wrapping or collapsing all four possible points into a single point, the single point as illustrated in FIG. 3(b) being on the unity circle as a result of normalization. Accordingly, normalization removes amplitude modulation and the fourth power operation removes phase information, so that the resultant components represent the carrier beat down to near DC. 
     FIG. 4(a) illustrates a constellation wherein the four possible points on the constellation are offset from the zero angle by a small arbitrary phase angle φ. In absence of noise, the four points will collapse to a single point A on the unity circle as illustrated in FIG. 4(b). As a result of the fourth power operation, the phase angle is multiplied by four and is designated as 4φ. 
     The constellation as illustrated in FIG. 4(b) is gradually spinning at a rate of the frequency offset. For instance, a 1 Hz frequency offset spins the constellation at a rate of 1 time per second. In the absence of a frequency offset or noise, the constellation will not spin. Collapsed points for successive samples will move along the unity circle at a rate equivalent to the frequency offset in the absence of noise. The frequency offset between successive samples is determined in phase differential circuit 260, providing an error estimate for adjusting numerically controlled oscillator 210, as will be described hereinafter. 
     The complex, normalized fourth power output of circuit element 240 is provided to filter 250 which functions to increase the signal to noise ratio of the fourth power samples prior to differentiation in phase differential circuit 260. Generally, the filtering reduces errors due to ambiguity when the phase error of the input signal due to noise exceeds π/4 and increases loop performance. However, this filtering limits the capture range of the carrier tracking loop. 
     Filter 250 is activated only when the carrier tracking loop has determined that it is in a LOCK condition, since filtering limits the frequency reacquisition range of the carrier tracking loop. When LOCK=1, filter 250 averages the most recent eight fourth power samples; otherwise, filter 250 simply transfers the fourth power samples to phase differential circuit 260. Filter 250 selectively filters the incoming signal components as follows ##EQU2## 
     As is readily apparent, when the carrier tracking loop is in a LOCK condition whereby LOCK=1, the left-hand portion of Equation (9) drops out such that the filter averages the most recent eight fourth power samples. 
     The constellation of FIG. 4(b) with collapsed point A on the unity circle illustrates a best case without noise. In actuality, there is noise on each of the four possible points of the constellation. Each of the four points are therefore sampled a plurality of times so that the points on the constellation of FIG. 4(a) appear fuzzy, actually representing plural samples. The normalization/fourth power circuit 240 therefore scatters the four possible data points of the constellation of FIG. 4(a) on an arc of the unity circle illustrated in FIG. 4(b). 
     In greater detail, when the tracking mode is invoked (LOCK=1), if the signal to noise ratio is high and there is no frequency offset, then successive fourth power samples will lie at 0 angle with unity amplitude. Noise will cause a distribution of angles on an arc about 0 angle on the complex plane, wherein the amplitude is always unity. Filtering of this sequence of noisy samples will result in a sample mean of the sequence of eight samples. As the signal to noise ratio becomes very high, the individual samples converge to the mean. As the signal to noise ratio becomes lower, the samples become spaced further apart on the arc. As the signal to noise ratio diminishes, the amplitude of the mean of the eight samples on the arc becomes smaller than unity. 
     The filtered in-phase I4 and quadrature Q4 signal components output from filter 250 are provided to phase differential circuit 260. The phase difference of successive in-phase I4 and quadrature Q4 signal components output from filter 250 is representative of frequency offset or the amount in which the constellation spins between successive samples, and is determined by multiplying each sample by the complex conjugate of a previous sample. 
     The in-phase I4 signal component output filter 250 is input to multipliers 261 and 262 and delay element 263. The quadrature Q4 signal component output filter 250 is provided to multipliers 264 and 265 and delay element 266. The output of delay element 266 is provided as a second input to multipliers 262 and 265 and the output of delay element 263 is provided as a second input to multipliers 261 and 264. Adder 267 adds the outputs of multipliers 261 and 265 to provide a differential in-phase Idiff signal component. Subtractor 268 subtracts the output of multiplier 262 from the output of multiplier 264 to provide as an output a differential quadrature Qdiff signal component. The complex difference phasor output from phase differential circuit 260 can be represented as 
     
         Idiff.sub.n +jQdiff.sub.n =&lt;S.sub.MF.sup.4 (n)&gt;&lt;S.sub.MF (n-1)&gt;≅e.sup.j8πΔfT.sbsp.s +noise8(n)  (10). 
    
     Estimation of the frequency offset by phase differential circuit 260 can be degraded by noise which scatters the points about the arc and also by a change in doppler, which may smear the points on the circle. For example, if a receiver in which the carrier tracking loop of FIG. 2 is embodied suddenly moves relative to a corresponding transmitter changing the distance therebetween, doppler will appear resulting in spinning of the constellation. 
     Since the amplitude of the complex output from phase differential circuit 260 is the product of the amplitudes of successive samples, then the amplitude of the complex output of phase differential circuit 260 is reduced as the signal to noise ratio is reduced. The differential in-phase Idiff signal component output from the phase differential circuit 260 is provided to amplifier 291, which along with adder 292 and amplifier 293, functions as an IIR filter or lossy integrator. The differential quadrature Qdiff signal component output from phase differential circuit 260 is provided to amplifier 294, which along with adder 295 and amplifier 296, functions as an IIR filter or lossy integrator. These filters provide additional smoothing of the differential output prior to signal to noise ratio estimation. The filtered differential in-phase Idiff and quadrature Qdiff signal components are provided to loop control circuit 270. 
     As will be described, the carrier tracking loop derives an error signal from the imaginary component of Equation (10). This error signal is processed by loop filtering consisting of constant gain α, gain β, the perfect integrator comprising adder 298 and delay 299 and additional gain control (nominally 1), which will be described hereinafter. It is to be understood that the values of α, α1, β1 and the various other parameters and thresholds of the carrier tracking loop of FIG. 2 are chosen to establish the best compromise between response time and tracking accuracy while ensuring closed-loop stability. 
     The error signal and control of the carrier tracking loop will now be described in connection with loop control circuit 270. Firstly, the filtered differential Idiff and Qdiff signal components will be described with reference to the constellation illustrated in FIG. 5. The differential signal component designated by the point in the constellation illustrated in FIG. 5 is a filtered phasor which represents an estimate of the frequency offset between successive samples. The phasor angle represents constellation shift in degrees between successive samples and is directly proportional to the frequency offset. A positive phasor angle corresponds to a positive frequency offset while a negative phasor angle corresponds to a negative frequency offset. 
     As described previously, filter 250 places the averaged sample point within the unity circle along the frequency offset angle of FIG. 4(b) for instance. As the amount of noise increases, the averaged sample point approaches the origin along the frequency offset angle. Also, the length of the filtered vector in the constellation illustrated in FIG. 5 is monotonically related to the signal to noise ratio of the input signal. The phasor length of a noisy signal will be smaller and will approach the origin. If the phasor length is very small, or within a certain distance of the origin, the signal to noise ratio of the input signal may be considered too low and the carrier tracking loop can subsequently be instructed to enter a flywheel mode, as will be described hereinafter. In this manner, the carrier tracking loop can be prevented from reacting to noise. 
     Loop control circuit 270 is illustrated in greater detail in FIG. 6 along with slope limiter 280. Although loop control circuit 270 will be described with reference to FIG. 6 as including discrete circuit components, it is to be understood that loop control circuit 270 may be software implemented. 
     Loop control circuit 270 improves acquisition and tracking performance of the carrier tracking loop under dynamic conditions. Conflicting requirements of smooth accurate frequency tracking, fast reacquisition, and doppler tracking over a wide dynamic range (Eb/No) are not necessarily achievable with conventional carrier tracking techniques. However, in the carrier tracking loop of a preferred embodiment of the present application, these conflicting requirements are realized by varying the loop parameters as a function of mode (i.e. flywheel, tracking or reacquisition). Accordingly, a key feature of the carrier tracking loop is determination of the active state of the carrier tracking loop as being in a flywheel, tracking or reacquisition mode. This determination enables appropriate setting of the GAIN (0 or BOOST+1) and the LOCK signal. 
     In order to determine the state of the carrier tracking loop, loop control circuit 270 estimates the signal to noise ratio (Eb/No) of the filtered differential signal components. This is accomplished by computing the sum of the squares of the complex filtered differential signal components. The filtered differential quadrature Qdiff signal component is provided to squarer 271 and the filtered differential in-phase Idiff signal component is provided to squarer 272. The outputs of squarers 271 and 272 are provided to adder 273 which adds the squared signals and outputs a smooth signal to noise ratio estimate to filter 274. In a preferred embodiment, filter 274 may be an IIR filter or two-stage lossy integrator having the following filter expression 
     
         y(n)= 4032y(n-1)-3969y(n-2)+x(n)!/4096                     (11). 
    
     It is to be understood that the filter expression of Equation (11) and the corresponding time constants are given by way of illustration only and are not to be considered limiting. Filter 274 filters the estimated signal to noise ratio and provides the filtered estimate as an SNR output signal. 
     An externally provided reacquisition signal is provided to filter 275 of loop control circuit 270, as illustrated in FIG. 6, to inform the loop control circuit that reacquisition is necessary. The reacquisition signal is preferably a digital impulse and may be provided from matched filter pair 220 or by peripheral circuitry, as would be understood by one of ordinary skill. In a preferred embodiment, filter 275 may be an IIR filter or two-stage lossy filter having the following filter expression 
     
         y(n)= 4032 y(n-1)-3969 y(n-2)!/4096                        (12). 
    
     It is to be understood that the filter expression of Equation (12) and the corresponding filter coefficients are given by way of illustration and are not to be considered as limiting. In a further preferred embodiment, filter 275 may be initialized to y(n)=0.125 and y(n-1)=2 for example. It is to be further understood that filters 274 and 275 may be software implemented. 
     Filter 275 outputs a digital impulse as a BOOST output signal upon receipt of the reacquisition signal. The BOOST signal rises quickly and then decays in a predetermined manner typical of an IIR response, in accordance with the filter expression of Equation (12). The purpose of the BOOST signal is to increase the loop GAIN and to disable the LOCK signal to LOCK=0 when the carrier tracking loop is commanded to reacquire. The BOOST signal is also used to provide a boolean function for detecting reacquisition mode whereby determination is made based on whether the BOOST signal is above a predetermined threshold. 
     The gain of the carrier tracking loop is controlled by gain control processor 276 based on the BOOST signal and SNR estimate. Gain control processor 276 outputs a GAIN signal to multiplier 277 which adjusts the gain of the filtered differential quadrature Qdiff signal component and outputs the estimated error signal ERR. The GAIN signal is nominally set to BOOST+1, which is usually near unity (independent of α, α1 and β1). 
     Gain control processor 276 functions to determine when the BOOST signal is active. The BOOST signal is considered active when BOOST is greater than a predetermined threshold THRES (i.e. BOOST&gt;THRES). As described previously, the BOOST signal rises quickly and then decays. Accordingly, when the BOOST signal is greater than THRES, the carrier tracking loop is determined as being in the reacquisition mode. Gain control processor 276 thus determines that the carrier tracking loop should reacquire by setting GAIN=BOOST+1. As the BOOST impulse response decays, the GAIN signal approaches unity and the carrier tracking loop is allowed to track with the error signal ERR. As is clearly evident, the gain of the carrier tracking loop is increased at the onset of reacquisition and thereafter decreases proportionally to the BOOST signal. 
     Gain control circuit 276 also functions to determine if the SNR estimate is greater than a predetermined minimum threshold MIN (i.e. SNR&gt;MIN). This determination by gain control processor 276 provides an indication that the signal to noise ratio of the filtered differential signal components output from phase differential circuit 276 is acceptable when the carrier tracking loop is no longer in a reacquisition mode. In this instance, gain control processor 276 maintains GAIN=BOOST+1 such that GAIN changes proportionally to the BOOST signal when SNR&gt;MIN and the carrier tracking loop is no longer in the reacquisition mode. 
     Lastly, gain control processor 276 functions to set GAIN=0 if it is determined that SNR&lt;MIN or BOOST&lt;THRES. This would correspond to a flywheel condition wherein the carrier tracking loop is not a reacquisition mode as indicated by the BOOST signal and the SNR estimate of the complex filtered differential signal is minimal. In the flywheel mode, numerically controlled oscillator 210 is prevented from responding to an overly noisy error signal ERR since GAIN=0. 
     It is to be understood that the previously described functions of gain control processor 276 may be carried out by a microprocessor under software control, as would be well within the scope of ordinary skill. In the alternative, gain control circuit 276 may be comprised of discrete circuit components such as comparators, adders or the like. Such variations are to be considered as within the scope of the present invention. 
     The loop control circuit functions as follows to provide the LOCK signal. The BOOST signal from filter 275 and the SNR estimate from filter 274 are input to lock control processor 278. As described previously, the lock signal provided to filter 250 is set to 1 when the carrier tracking loop is in a tracking mode and is set to zero otherwise. Lock control processor 278 establishes that the carrier tracking loop is not in the reacquisition mode when it is determined that the BOOST signal is less than THRES. Lock control processor 278 establishes that the carrier tracking loop is not in a flywheel mode when the SNR estimate is greater than MIN. Accordingly, lock control processor 278 sets LOCK to 1 when the carrier tracking loop is tracking, or when it has been established that the carrier tracking loop is not in a reacquisition mode and is not in a flywheel mode. Filter 250 averages the most recent eight fourth power samples when LOCK=1 as described previously. 
     Filter 250 is activated only when LOCK=1. Since the filter does not enhance carrier tracking loop performance in reacquisition or flywheel modes. In fact, the filter hinders performance in the reacquisition mode when the frequency is changing rapidly. This is because the eight fourth power samples are spread across a large arc on the complex plane. The length of the arc is proportional to the frequency change. When the length of the arc becomes sufficiently large, for example π radians, the error signal from phase differential circuit 260 diminishes rapidly even when the actual signal to noise ratio is high. This would have the undesirable effect of decreasing loop gain during reacquisition when the loop gain should actually be increased. 
     The BOOST signal, SNR estimate and the estimated error signal ERR are provided from loop control circuit 270 to slope limiter 280. The purpose of slope limiter 280 is to reduce unintentional phase noise in the error signal ERR attributed to the carrier tracking loop. Generally, noise in the incoming signal results in the introduction of noise in the error signal ERR from the carrier tracking loop. This error signal noise attributed to the carrier tracking loop modulates numerically controlled oscillator 210 as phase noise. Because of the particular nonlinearities in the carrier tracking loop, the error signal noise tends to be peaky, not gaussian. The noise becomes more severe as the signal to noise ratio decreases at the input of the carrier tracking loop. 
     Although reduction of loop bandwidth may serve to reduce the error signal noise, the carrier tracking loop response time to a frequency transient during reacquisition, for example, would suffer as a result. Instead, slope limiter 280 of a preferred embodiment of the present invention smooths the peaks in the error signal to reduce carrier tracking loop phase noise while retaining the effective integrated values of the clipped or excess portion of the error signal. This excess or clipped portion is added back to the error signal when it falls below the clip value. This effectively eliminates any additional error or bias which might be caused by limiting, especially in the presence of doppler variations. Accordingly, all of the integrated error information is preserved in memory 281 of slope limiter 280 while the peaks are made smooth to reduce carrier tracking loop phase noise and maintain enhanced loop response time. 
     FIG. 7 illustrates error signal estimate ERR which is provided to slope limiter 280 from loop control circuit 270. The error signal as illustrated is very peaky. A straight line approximation is superimposed on the error signal for the sake of description and since typically the average of the slope will approximate this straight line. As described previously, it is undesirable to permit spikes in the error signal estimate ERR to drive numerically controlled oscillator 210, since this would effectively introduce noise into the down converted signal output complex mixer 200. Slope limiter circuit 280 therefore limits how fast the error signal estimate ERR can change, such that the slope rate of the error signal estimate is limited and approaches the straight line approximation. Slope limiter 280 in this way prevents numerically controlled oscillator 210 from responding to noisy spikes in the error signal estimate. Slope limiter 280 functions to respond to all of the information of the error signal estimate by integrating the information that is clipped and subsequently adding the clipped excess back in when the error signal estimate falls below the straight line approximation. The slope limiter therefore tends to put a straighter, smoother line through the noisy spiky error signal estimate. 
     Slope limiter 280 firstly functions to determine when BOOST is less than 0.01 and SNR is less than 0.05 (about 6 db Eb/No). Accordingly, Equation (13) as follows is invoked when the carrier tracking loop is not in a reacquisition mode and the signal to noise ratio is low: 
     
         SUM(n)=ERR(n)+EXCESS(n)                                    (13). 
    
     In Equation (13), ERR(n) represents the error signal estimate output from loop control circuit 270 and EXCESS(n) represents that portion of the error signal estimate which is determined to be the excess or clipped portion. In accordance with Equation (13), at each symbol timing, slope limiter 280 adds an earlier determined stored value EXCESS(n) to the current value ERR(n) to provide a current value of SUM(n). 
     In greater detail, in a first operational range, slope limiter 280 determines a value of the error signal ERR(n) at a given time n. At time n, the value SUM(n) will be equivalent the value ERR(n) at time n and an earlier stored value of EXCESS(n). If it is determined by slope limiter 280 that the value SUM(n) is greater than 0.008, slope limiter 280 sets the value ERR(n) equal to 0.008, thus limiting the current value of the error signal estimate ERR(n), clipping the excess portion thereof. 
     Slope limiter 280 keeps account of the clipped or excess portion at time n whereby the value EXCESS(n+1) for the subsequent symbol time is determined as 
     
         EXCESS(n+1)= SUM(n)-0.008! 0.999                           (14). 
    
     This value EXCESS(n+1) for a subsequent symbol time is stored in memory 281 of slope limiter 280 and is used to determine the value SUM(n+1) of the subsequent symbol time. Accordingly, the excess or clipped portion is accounted for and the information is not disregarded. 
     In a second operational range, when slope limiter 280 determines that SUM(n) is less than -0.008, the value ERR(n) is set to -0.008. The value EXCESS(n+1) of a subsequent symbol time is set in accordance with Equation (13) above. 
     Lastly, in a third operational range, when slope limiter 280 determines that ERR(n)=SUM(n), the value EXCESS(n+1) for the subsequent symbol time is set equal to 0. Slope limiter 280 therefore limits the phase noise by clipping the value SUM(n) to ±0.008. It is to be understood that these parameters have been empirically derived in the above example and are given by way of illustration only, and thus are not to be considered limiting. 
     The slope limited error signal ERR output from slope limiter 280 is provided to amplifier 297 and subsequently to the perfect integrator comprising adder 298 and delay element 299. As described previously, the output of the integrator comprising adder 298 and delay 299 is provided to control the frequency of numerically controlled oscillator 210. As also noted previously, the values of α, α1, β1 and the various parameters and thresholds are chosen to establish the best compromise between response time and tracking accuracy while ensuring closed loop stability. In a preferred embodiment, the integrator comprising adder 298 and delay 299 may be set with an initial frequency estimate to improve carrier tracking loop performance. 
     It is to be understood that lock control processor 278 may be a software controlled microprocessor, or in the alternative discrete hardware components such as comparators, adders or the like. Also, the entire loop control circuit 270 including the functions provided by the gain control processor 276 and lock control processor 278 may be software implemented. It is further understood that the LOCK signal may be made available for use external to the carrier tracking loop. 
     Accordingly, a preferred embodiment of the present invention having an amplitude normalization/fourth power function and control of carrier tracking loop gain enables improved carrier tracking loop performance with arbitrary gain or signal to noise ratio and enhanced reacquisition speed when the modem experiences a fading or intermittent channel. The slope limiting function reduces unintentional phase noise introduced by the carrier tracking loop while retaining the response time characteristics. 
     It is to be understood that the invention as described above may be varied in many ways. For instance, the various circuit elements as described can be realized in a software implementation. Also, the circuit elements described can be replaced with various circuit elements which perform similar functions. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.