Abstract:
An input part and a feedback part are arranged in series between a second power supply line and input nodes of inverting circuits. The input part connects the second power supply line to one of the input nodes of the inverting circuits in accordance with an input signal. One of the inverting circuits operates so that a logical value corresponding to the input signal is latched into a latching part. The feedback part connects only one of the input nodes to the input part in accordance with an output level of the latching part, thereby fixing the latching state of the latching part. Since the number of stages of circuits from the input part to the latching part can be reduced, the input signal can be latched reliably even when the power supply voltages are low.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a semiconductor integrated circuit having input circuits for receiving input signals.  
           [0003]    2. Description of the Related Art  
           [0004]    Recently, semiconductor integrated circuits are ever decreasing in power supply voltage (operation voltage) for the sake of finer transistor structures, reduced power consumption, and so on. The threshold voltages of the transistors hardly depend on the power supply voltage. With the decreasing power supply voltage, the threshold voltages of the transistors thus increase in relation to the power supply voltage. As a result, circuits made of transistors tend to decrease in operation margin.  
           [0005]    [0005]FIG. 1 shows an example of an input circuit for receiving an input signal supplied from exterior.  
           [0006]    The input circuit has a latching part  1 , a precharging part  2 , a feedback part  3 , an input part  4 , a power supply connection part  5 , and a buffer part  6 . The latching part  1  is composed of two CMOS inverters  1   a  and  1   b  having inputs and outputs connected to each other. The precharging part  2  is composed of two pMOS transistors  2   a  and  2   b  which are connected at their drains to the input nodes ND 1  and ND 2  of the CMOS inverters  1   a  and  1   b,  respectively. The pMOS transistors  2   a  and  2   b  are connected to a power supply line VDD at their sources, and receive a clock signal CLK at their gates.  
           [0007]    The feedback part  3  is composed of two nMOS transistors  3   a  and  3   b  which are connected at their drains to the sources of the nMOS transistors of the CMOS inverters  1   a  and  1   b.  The gates of the nMOS transistors  3   a  and  3   b  receive the inverted levels of the nodes ND 2  and ND 1  (/ND 2  and /ND 1 ) which are supplied through the buffer part  6 , respectively. The input part  4  is composed of nMOS transistors  4   a  and  4   b  which are connected at their drains to the sources of the nMOS transistors of the CMOS inverters  1   a  and  1   b.  The gates of the nMOS transistors  4   a  and  4   b  receive an input signal IN and a reference voltage VREF, respectively. The reference voltage VREF is set at a central voltage between the high-level voltage and low-level voltage of the input signal IN.  
           [0008]    The power supply connection part  5  consists of an nMOS transistor  5   a  which is connected at its drain to the sources of the nMOS transistors  3   a,    3   b,    4   a,  and  4   b.  The nMOS transistor  5   a  is connected to a ground line VSS at its source, and receives the clock signal CLK at its gate. The buffer part  6  has inverters  6   a  and  6   b  for inverting the logic levels of the nodes ND 1  and ND 2 , respectively, and an output circuit  6   c.  The output circuit  6   c  has a pMOS transistor and an nMOS transistor arranged in series between the power supply line VDD and the ground line VSS. The gate of the pMOS transistor of the output circuit  6   c  is connected to the node /ND 1  through an inverter. The gate of the nMOS transistor of the output circuit  6 c is connected to the node /ND 2 .  
           [0009]    In the input circuit shown in FIG. 1, when the clock signal CLK is at low level, the pMOS transistors  2   a  and  2   b  of the precharging part  2  turn on so that the input nodes ND 1  and ND 2  of the CMOS inverters  1   a  and  1   b  both change to high level. Here, the nMOS transistor  5   a  is off. While the nodes ND 1  and ND 2  are at high level, the outputs of the inverters  6   a  and  6   b  of the buffer part  6 , i.e., the nodes /ND 1  and /ND 2  are low in level, turning off the nMOS transistors  3   a  and  3   b  of the feedback part  3 .  
           [0010]    Next, the input signal IN is supplied before the clock signal CLK changes to high level. The clock signal CLK of high level turns off the pMOS transistors  2   a,    2   b  of the precharging part  2  and turns on the nMOS transistor  5   a  of the power supply connection part  5 . For example, if the input signal is at high level (a voltage higher than the reference voltage VREF), the source-to-drain resistance of the nMOS transistor  4   b  becomes lower than that of the nMOS transistor  4   a.  Consequently, the node ND 1  falls below the node ND 2  in voltage. The source-to-drain resistance of the pMOS transistor  1   a  becomes lower than that of the PMOS transistor  1   b.  As a result, the node ND 2  rises in voltage and the node ND 1  falls in voltage. That is, the high level of the input signal IN is latched into the latching part  1 .  
           [0011]    The low level of the node ND 1  and the high level of the node ND 2  change the nodes /ND 1  and /ND 2  to high level and low level, respectively. The output circuit  6   c  of the buffer part  6  receives the low level of the node /ND 2  and the inverted level (low level) of the node /ND 1 , and changes the output signal OUT to high level. That is, the logic level of the input signal IN latched in the latching part  1  is output.  
           [0012]    Since the nMOS transistor  3   b  of the feedback part  3  turns on in response to the high level of the node /ND 1 , the latching state of the latching part  1  is fixed regardless of the level of the input signal IN. The latching part  1  latches the input signal IN until the clock signal CLK changes to low level.  
           [0013]    [0013]FIG. 2 shows another example of the input circuit. This input circuit is the input circuit shown in FIG. 1, inverted in polarity. More specifically, the nMOS transistors and pMOS transistors, as well as the power supply line VDD and ground line VSS, are replaced with each other.  
           [0014]    The input circuit has a latching part  1 , a precharging part  7 , a feedback part  8 , an input part  9 , a power supply connection part  10 , and a buffer part  11 . The precharging part  7  is composed of two nMOS transistors  7   a  and  7   b  which are connected at their drains to the input nodes ND 1  and ND 2  of the CMOS inverters  1   a  and  1   b,  respectively. The nMOS transistors  7   a  and  7   b  are connected to a ground line VSS at their sources, and receive a clock signal /CLK at their gates. The clock signal /CLK is the clock signal CLK inverted in phase.  
           [0015]    The feedback part  8  is composed of two PMOS transistors  8   a  and  8   b  which are connected at their drains to the sources of the pMOS transistors of the CMOS inverters  1   a  and  1   b.  The gates of the pMOS transistors  8   a  and  8   b  receive the inverted levels of the nodes ND 2  and ND 1  (/ND 2  and /ND 1 ) which are supplied through the buffer part  11 , respectively. The input part  9  is composed of pMOS transistors  9   a  and  9   b  which are connected at their drains to the sources of the pMOS transistors of the CMOS inverters  1   a  and  1   b.  The gates of the pMOS transistors  9   a  and  9   b  receive an input signal IN and a reference voltage VREF, respectively.  
           [0016]    The power supply connection part  10  is connected at its drain to the sources of the pMOS transistors  8   a,    8   b,    9   a,  and  9   b,  is connected at its source to a power supply line VDD, and receives the clock signal /CLK at its gate. The buffer part  11  has inverters  11   a  and  11   b  for inverting the levels of the nodes ND 1  and ND 2 , respectively, and an output circuit  11   c.  The output circuit  11   c  has a pMOS transistor and an nMOS transistor arranged in series between the power supply line VDD and the ground line VSS. The gate of the pMOS transistor of the output circuit  11   c  is connected to the node /ND 1 . The gate of the nMOS transistor of the output circuit  11   c  is connected to the node /ND 2  through an inverter.  
           [0017]    In the input circuit shown in FIG. 2, when the clock signal /CLK is at high level, the nMOS transistors  7   a  and  7   b  of the precharging part  7  turn on so that the input nodes ND 1  and ND 2  of the CMOS inverters  1   a  and  1   b  both change to low level. Then, the input signal IN is supplied before the clock signal /CLK changes to low level. Then, either one of the nodes ND 1  and ND 2  changes to high level, and the other to low level. Subsequently, in accordance with the voltages of the nodes ND 1  and ND 2 , either one of the pMOS transistors  8   a  and  8   b  of the feedback part  8  turns on so that the latching state is fixed until the clock signal /CLK changes to high level.  
           [0018]    In the input circuit shown in FIG. 1, three nMOS transistors (for example, the nMOS transistors  5   a,    4   a,  and the nMOS transistor of the CMOS inverter  1   a ) are connected in series between the ground line VSS and the nodes ND 1 , ND 2 . Similarly, in the input circuit shown in FIG. 2, three pMOS transistors are connected in series between the power supply line VDD and the nodes ND 1 , ND 2 . Consequently, when the foregoing input circuits are mounted on semiconductor integrated circuits of lower power supply voltages, it becomes harder for the ground voltage VSS (or the power supply voltage VDD) to be supplied to the latching part  1 . This results in a smaller voltage difference between the nodes ND 1  and ND 2 , so that the latching part  1  may latch incorrect data because of slight power supply noise etc.  
           [0019]    Additionally, in FIG. 1, the nMOS transistor  4   a  for receiving the reference voltage VREF is connected to the ground line VSS through the nMOS transistor  5   a.  Similarly, in FIG. 2, the pMOS transistor  9   a  for receiving the reference voltage VREF is connected to the power supply line VDD through the pMOS transistor  10   a.  On this account, the nMOS and pMOS transistors  4   a  and  9   b  are more likely to vary in source and drain voltages when the input circuits are in operation. In consequence, if the reference voltage VREF varies due to coupling noise in latching the input signal IN, the input signal IN to be supplied in synchronization with the next clock signal CLK (or /CLK) may not be latched correctly.  
         SUMMARY OF THE INVENTION  
         [0020]    It is an object of the present invention to provide a semiconductor integrated circuit having an input circuit capable of receiving an input signal with reliability. In particular, the object is to receive the input signal reliably when the power supply voltage is low.  
           [0021]    According to one of the aspects of the semiconductor integrated circuit of the present invention, an input circuit includes a latching part, a power supply connection part, an input part, and a feedback part. In this input circuit, the power supply connection part firstly connects inverting circuits of the input circuit to a first power supply line in response to an activation of a control signal, the first power supply line being supplied with the first power supply voltage. An input switch circuit of the input part connects a second power supply line to one of the input nodes of the inverting circuits through the feedback part in accordance with the input signal, the second power supply line being supplied with the second power supply voltage. Since one of the inverting circuits operates, the latching part is forced into an unbalanced state to latch a logical value corresponding to the input signal. A feedback switch circuit of the feedback part connects only one of the input nodes to the input part in accordance with a level of an output signal output from the latching part. Then, the latching state of the latching part is fixed.  
           [0022]    The input part and the feedback part are arranged in series between the second power supply line and the input nodes of the inverting circuits. That is, the input part is connected directly to the input nodes through the latching part. Since a voltage corresponding to the input signal can be supplied to the input nodes directly, a voltage difference between the input nodes of the inverting circuits can be widened quickly in accordance with the input signal. Thus, the input signal can be latched into the latching part with reliability. Since the number of stages of circuits from the input part for receiving the input signal to the latching part can be reduced, the input signal can be latched with reliability even when the power supply voltages are low (even when the difference between the first power supply voltage and the second power supply voltage is small).  
           [0023]    According to another aspect of the semiconductor integrated circuit of the present invention, an input circuit includes a latching part, a power supply connection part, an input part, and a feedback part. In this input circuit, the power supply connection part firstly connects inverting circuits of the input circuit to a first power supply line in response to an activation of a control signal, the first power supply line being supplied with the first power supply voltage. An input switch circuit of the input part connects a second power supply line to one of the inverting circuits in accordance with the input signal, the second power supply line being supplied with the second power supply voltage. Since one of the inverting circuits operates, the latching part is forced into an unbalanced state to latch a logical value corresponding to the input signal. A feedback switch circuit of the feedback part connects only one of the input nodes to the second power supply line in accordance with a level of an output signal output from the latching part. Then, the latching state of the latching part is fixed.  
           [0024]    The input part and the feedback part are arranged in parallel between the second power supply line and the inverting circuits. That is, the second power supply line is connected directly to the inverting circuits through the input part. Since the second power supply line can be connected directly to the inverting circuits according to the input signal, a voltage difference between the input nodes of the inverting circuits can be widened quickly in accordance with the input signal. Thus, the input signal can be latched into the latching part with reliability. Since the number of stages of circuits from the input part for receiving the input signal to the latching part can be reduced, the input signal can be latched with reliability even when the power supply voltages are low (even when the difference between the first power supply voltage and the second power supply voltage is small).  
           [0025]    According to another aspect of the semiconductor integrated circuit of the present invention, a precharging part sets the input nodes of the inverting circuits at a predetermined voltage when the control signal is inactivated. By putting the inverting circuits in an identical state before the latching part operates, the latching part can be quickly rendered out of balance in order to make itself such a state that corresponds to the input signal.  
           [0026]    According to another aspect of the semiconductor integrated circuit of the present invention, the output signal is amplified through a buffer part. Supplying the output signal to the feedback part allows a reduction in the time required for determining the latching state of the latching part.  
           [0027]    According to another aspect of the semiconductor integrated circuit of the present invention, the input circuit is composed of pMOS transistors and nMOS transistors. The input nodes of the inverting circuits are connected to the second power supply line through two stages of transistors (pMOS or nMOS transistors of the input part and the feedback part). Consequently, it becomes easier for the second power supply voltage to be transmitted to the input nodes in accordance with the input signal. The input signal can thus be latched with reliability even when the difference between the first power supply voltage and the second power supply voltage is small. As a result, the operation margin can be improved in the case of lower power supply voltages. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0028]    The nature, principle, and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by identical reference numbers, in which:  
         [0029]    [0029]FIG. 1 is a circuit diagram showing a conventional input circuit;  
         [0030]    [0030]FIG. 2 is a circuit diagram showing another example of the conventional input circuit;  
         [0031]    [0031]FIG. 3 is a block diagram showing a first embodiment of the semiconductor integrated circuit of the present invention;  
         [0032]    [0032]FIG. 4 is a circuit diagram showing the details of the input circuits of FIG. 3;  
         [0033]    [0033]FIG. 5 is a block diagram showing a second embodiment of the semiconductor integrated circuit of the present invention;  
         [0034]    [0034]FIG. 6 is a circuit diagram showing the details of the input circuits of FIG. 5;  
         [0035]    [0035]FIG. 7 is a circuit diagram showing the details of the input circuits according to a third embodiment of the semiconductor integrated circuit of the present invention;  
         [0036]    [0036]FIG. 8 is a circuit diagram showing the details of the input circuits according to a fourth embodiment of the semiconductor integrated circuit of the present invention;  
         [0037]    [0037]FIG. 9 is a block diagram showing a fifth embodiment of the semiconductor integrated circuit of the present invention.  
         [0038]    [0038]FIG. 10 is a circuit diagram showing the details of the input circuits of FIG. 9;  
         [0039]    [0039]FIG. 11 is a waveform chart showing the operation of the input circuit of FIG. 10; and  
         [0040]    [0040]FIG. 12 is a circuit diagram showing another example of the input circuit. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0041]    Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, each thick line represents a signal line that consists of a plurality of lines.  
         [0042]    [0042]FIG. 3 shows a first embodiment of the semiconductor integrated circuit of the present invention.  
         [0043]    The semiconductor integrated circuit is formed as a clock synchronous SDRAM (Synchronous DRAM) on a silicon substrate by using CMOS process technology.  
         [0044]    The SDRAM has a clock buffer  12  for receiving a clock signal (control signal) CLK, command buffers  14  for receiving a command signal CMD which consists of a plurality of bits, address buffers  16  for receiving an address signal AD which consists of a plurality of bits, a command latch/decoder  18 , an address latch circuit (address receiver circuit)  20 , a control circuit  22 , and a memory core  24 . Incidentally, aside from those shown in FIG. 3, the SDRAM also has data buffers, a data latch circuit, a data control circuit and so on for inputting/outputting a data signal. The data latch circuit has input circuits for latching the data signal in synchronization with the clock signal CLK.  
         [0045]    The clock buffer  12 , the command buffers  14 , and the address buffers  16  each have a differential input circuit including a current mirror circuit, and a buffer BUF. The clock buffer  12  outputs the received clock signal CLK as an internal clock signal ICLK. The command buffers  14  output the received command signal CMD as an internal command signal ICMD. The address buffers  16  receive an address signal AD for selecting memory cells MC to be subjected to a write operation or a read operation, and output the received address signal AD as an internal address signal IAD.  
         [0046]    The command latch/decoder  18  has input circuits  26  for receiving the internal command signal ICMD in synchronization with the internal clock signal ICLK, and a command decoder  28  for decoding the internal clock signal ICLK received. According to the decoding result, the command latch/decoder  18  outputs a core control signal CNT for performing a write operation or a read operation on the memory core  24 .  
         [0047]    The address latch circuit  20  has input circuits  30  which receive the internal address signal IAD in synchronization with the internal clock signal ICLK and output the received signal as a latched address signal LAD.  
         [0048]    The control circuit  22  receives the core control signal CNT and the latched address signal LAD, and outputs a control signal for operating the memory core  24  to this memory core  24 .  
         [0049]    The memory core  24  has memory cells MC arranged in a matrix, word lines WL and bit lines BL connected to the memory cells MC, and sense amplifiers SA connected to the bit lines BL. The memory cells MC are the same as typical DRAM memory cells, each having a capacitor for retaining data in the form of a charge and a transfer transistor arranged between this capacitor and a bit line BL. The gate of the transfer transistor is connected to a word line WL.  
         [0050]    The memory core  24  starts its operation in response to the control signal from the control circuit  22 , and selects a word line(s) WL in accordance with the latched address signal LAD. Through the selection of the word line(s) WL, any one of a read operation, a write operation, and a refresh operation is performed.  
         [0051]    [0051]FIG. 4 shows the details of the input circuits  30  in the address latch circuit  20  shown in FIG. 3. Incidentally, the input circuits  26  of the command latch/decoder  18  and the input circuits of the data latch circuit are the same circuits as the input circuits  30 . Description will thus be omitted of these input circuits.  
         [0052]    An input circuit  30  has an input part  32 , a feedback part  34 , a latching part  36 , a precharging part  38 , a power supply connection part  40 , and a buffer part  42 .  
         [0053]    The input part  32  is composed of pMOS transistors  32   a  and  32   b  (input switch circuit) which are connected to the feedback part  34  at their drains. The gates of the pMOS transistors  32   a  and  32   b  receive the internal address signal IAD inverted in phase, or an internal address signal /IAD, and the internal address signal IAD, respectively. The sources of the PMOS transistors  32   a  and  32   b  are connected to a power supply line (second power supply line) VDD to which a power supply voltage (second power supply voltage) VDD is supplied. In this embodiment, the power supply voltage VDD is set at 2.3 V.  
         [0054]    The feedback part  34  is composed of pMOS transistors  34   a  and  34   b  (feedback switch circuit) which are connected at their drains to the input nodes ND 1  and ND 2  of CMOS inverters  36   a  and  36   b  to be described later (=the output nodes ND 2  and ND 1  of the CMOS inverters  36   a  and  36   b ), respectively. The gates of the pMOS transistors  34   a  and  34   b  receive the inverted levels of the nodes ND 2  and ND 1  (/ND 2  and /ND 1 ), respectively, which are supplied through the buffer part  42 .  
         [0055]    The latching part  36  is composed of the CMOS inverters  36   a  and  36   b  which have inputs and outputs connected to each other. The sources of the pMOS transistors of the CMOS inverters  36   a  and  36   b  are connected to the power supply line VDD. The sources of the nMOS transistors of the CMOS inverters  36   a  and  36   b  are connected to the power supply connection part  40 .  
         [0056]    The precharging part  38  is composed of pMOS transistors  38   a  and  38   b  which are connected at their drains to the input nodes ND 1  and ND 2  of the CMOS inverters  36   a  and  36   b,  respectively. The pMOS transistors  38   a  and  38   b  are connected to the power supply line VDD at their sources, and receive the internal clock signal ICLK at their gates.  
         [0057]    The power supply connection part  40  consists of an nMOS transistor  40   a  which is connected at its drain to the sources of the nMOS transistors of the CMOS inverters  36   a  and  36   b.  The nMOS transistor  40   a  is connected at its source to a ground line (first power supply line) VSS to which a ground voltage (first power supply voltage) VSS is supplied. The nMOS transistor  40   a  receives the internal clock signal ICLK at its gate.  
         [0058]    The buffer part  42  has inverters  42   a  and  42   b  for inverting the logic levels of the nodes ND 1  and ND 2 , respectively, and an output circuit  42   c.  The output circuit  42   c  has a PMOS transistor and an nMOS transistor arranged in series between the power supply line VDD and the ground line VSS. The gate of the pMOS transistor of the output circuit  42   c  is connected to the node /ND 1  through an inverter. The gate of the nMOS transistor of the output circuit  42   c  is connected to the node /ND 2 . The buffer part  42  outputs the latched address signal LAD, a signal of the same logic level as that of the internal address signal IAD received by the input part  32 .  
         [0059]    In the input circuit  30  shown in FIG. 4, when the internal clock signal ICLK (clock signal CLK) is at low level, the pMOS transistors  38   a  and  38   b  of the precharging part  38  turn on so that the input nodes ND 1  and ND 2  of the CMOS inverters  36   a  and  36   b  both change to high level. Here, the nMOS transistor  40   a  of the power supply connection part  40  is off. While the nodes ND 1  and ND 2  are at high level, the outputs of the inverters  42   a  and  42   b  of the buffer part  42 , i.e., the nodes /ND 1  and /ND 2  are low in level, turning on the pMOS transistors  34   a  and  34   b  of the feedback part  34 . Consequently, when the internal clock signal ICLK is inactivated, the input nodes ND 1  and ND 2  of the CMOS inverters  36   a  and  36   b  are connected to the pMOS transistors  32   a  and  32   b  of the input part  32  through the pMOS transistors  34   a  and  34   b  of the feedback part  34 .  
         [0060]    Next, the internal address signal IAD is supplied before the internal clock signal ICLK changes to high level (an activated state). The internal clock signal ICLK of high level turns off the pMOS transistors  38   a,    38   b  of the precharging part  38  and turns on the nMOS transistor  40   a  of the power supply connection part  40 . Since the nMOS transistor  40   a  is turned on, the latching part  36  is activated to be capable of latching the internal address signal IAD.  
         [0061]    For example, when the internal address signal IAD is at high level, the pMOS transistor  32   a  turns on and the pMOS transistor  32   b  turns off. Since the pMOS transistors  34   a  and  34   b  of the feedback part  34  are on, the node ND 2  alone is connected to the power supply line VDD through the pMOS transistors  32   a  and  34   a.  The node ND 2  rises in voltage and the node ND 1  falls in voltage, turning off the pMOS transistor  36   b  and on the pMOS transistor  36   a  of the CMOS inverter  36 . Then, the internal address signal IAD of high level is latched into the latching part  36 .  
         [0062]    In this embodiment, the input node ND 1  of the CMOS inverter  36   a  is connected to the power supply line VDD through the PMOS transistors  32   a  and  34   a.  Similarly, the input node ND 2  of the CMOS inverter  36   b  is connected to the power supply line VDD through the pMOS transistors  32   b  and  34   b.  That is, the input nodes ND 1  and ND 2  are connected to the power supply line VDD through two stages of transistors connected in series. This is one stage fewer than heretofore (FIGS. 1 and 2). Consequently, even if the power supply voltage VDD is as low as 2.3 V, the voltage difference between the nodes ND 1  and ND 2  can be widened quickly and surely in accordance with the internal address signal IAD. In addition, the pMOS transistors  32   a  and  32   b,  both having an amplifying function, are directly connected to the power supply line VDD at their sources. Small changes in the voltage of the internal address signal IAD can thus be amplified and output to the drains of the pMOS transistors  32   a  and  32   b  quickly with reliability. As a result, the operation margin of the input circuits  30  (and the input circuits  26 ) with respect to the power supply voltage improves as compared to heretofore.  
         [0063]    The inverters  42   a  and  42   b  of the buffer part  42  amplify the low level of the node ND 1  and the high level of the node ND 2 , whereby the nodes /ND 1  and /ND 2  are changed to the power supply voltage VDD and the ground voltage VSS, respectively. The output circuit  42   c  of the buffer part  42  receives the low level of the node /ND 2  and the inverted level (low level) of the node /ND 1 , and changes the latched address signal LAD to high level. That is, the logic level of the internal address signal IAD latched in the latching part  36  (the power supply voltage VDD) is output.  
         [0064]    Moreover, the pMOS transistor  34   a  of the feedback part  34  remains turned on under the low level of the node /ND 2 . The PMOS transistor  34   b  of the feedback part  34  is turned off in response to the high level of the node /ND 1 . The input node ND 2  of the CMOS inverter  36   a  is connected to the power supply line VDD through the pMOS transistors  32   a  and  34   a,  so that the latching state of the latching part  36  is fixed irrespective of the level of the internal address signal IAD. Since the output signals (nodes ND 1  and ND 2 ) of the latching part  36  amplified by the inverters  42   a  and  42   b  are supplied to the feedback part  34 , the feedback operation can be performed at high speed. The latching part  36  latches the internal address signal IAD until the clock signal CLK changes to low level.  
         [0065]    As above, according to the first embodiment, the power supply line VDD is connected to the input node ND 2  (ND 1 ) of the CMOS inverter  36   b  ( 36   a ) through the two stages of pMOS transistors  32   a  and  34   a  ( 32   b  and  34   b ) connected in series. The voltage difference between the input nodes ND 1  and ND 2  can thus be widened quickly in accordance with the address signal AD. That is, the address signal AD can be latched into the latching part  36  with reliability. The improved operation margin of the input circuit  30  with respect to the power supply voltage VDD allows the address signal AD to be latched with reliability even if the power supply voltage VDD is low.  
         [0066]    When the clock signal CLK is inactivated, the input nodes ND 1  and ND 2  are connected to the power supply line VDD by using the precharging part  38 . Thus, the logic level of the address signal AD can be latched into the latching part  36  with reliability when the clock signal CLK is activated.  
         [0067]    Since the output signals (/ND 1 , /ND 2 ) amplified through the buffer part  42  are supplied to the feedback part  34 , it is possible to reduce the time for the latching state of the latching part  36  to be determined.  
         [0068]    [0068]FIG. 5 shows a second embodiment of the semiconductor integrated circuit of the present invention. The same elements as those of the first embodiment will be designated by identical reference numbers or symbols. Detailed description thereof will be omitted.  
         [0069]    In this embodiment, a command latch/decoder  18 A and an address latch circuit  20 A are formed instead of the command latch/decoder  18  and the address latch circuit  20  of the first embodiment. Besides, the command latch/decoder  18 A and the address latch circuit  20 A are supplied with an internal clock signal /ICLK, or the internal clock signal ICLK inverted in phase. The rest of the configuration is the same as in the first embodiment.  
         [0070]    The command latch/decoder  18 A has input circuits  26 A for receiving the internal command signal ICMD in synchronization with the internal clock signal /ICLK, and a command decoder  28  for decoding the internal command signal ICMD received. According to the decoding result, the command latch/decoder  18 A outputs the core control signal CNT for operating the memory core  24 .  
         [0071]    The address latch circuit  20 A has input circuits  30 A which receive the internal address signal IAD in synchronization with the internal clock signal /ICLK and output the received signal as the latched address signal LAD.  
         [0072]    [0072]FIG. 6 shows the details of the input circuits  30 A in the address latch circuit  20 A shown in FIG. 5. Incidentally, the input circuits  26 A of the command latch/decoder  18 A are the same circuits as the input circuits  30 A. Description will thus be omitted of the input circuits  26 A.  
         [0073]    The input circuits  30 A are the input circuits  30  shown in FIG. 4, inverted in polarity. More specifically, by way of comparison between the input circuits  30 A and the input circuits  30 , the nMOS transistors and pMOS transistors, as well as the power supply line VDD and ground line VSS, are replaced with each other.  
         [0074]    An input circuit  30 A has a power supply connection part  44 , a latching part  36 , a precharging part  46 , a feedback part  48 , an input part  50 , and a buffer part  52 . The power supply connection part  44  consists of a PMOS transistor  44   a  which is connected to the latching part  36  at its drain. The pMOS transistor  44   a  is connected to the power supply line (first power supply line) VDD at its source, and receives the internal clock signal /ICLK at its gate.  
         [0075]    The latching part  36  is composed of two CMOS inverters  36   a  and  36   b  having inputs and outputs connected to each other. The precharging part  46  is composed of two nMOS transistors  46   a  and  46   b  which are connected at their drains to the input nodes ND 1  and ND 2  of the CMOS inverters  36   a  and  36   b,  respectively. The nMOS transistors  46   a  and  46   b  are connected to the ground line (second power supply line) VSS at their sources, and receive the internal clock signal /ICLK at their gates.  
         [0076]    The feedback part  48  is composed of nMOS transistors  48   a  and  48   b  (feedback switch circuit) which are connected to the nodes ND 1  and ND 2  at their drains, respectively. The gates of the nMOS transistors  48   a  and  48   b  receive the inverted levels of the nodes ND 2  and ND 1  (/ND 2  and /ND 1 ), respectively, which are supplied through the buffer part  52 .  
         [0077]    The input part  50  is composed of nMOS transistors  50   a  and  50   b  (input switch circuit) which are connected at their drains to the sources of the nMOS transistors  48   a  and  48   b,  respectively. The gates of the nMOS transistors  50   a  and  50   b  receive the internal address signals /IAD and IAD, respectively.  
         [0078]    The buffer part  52  has inverters  52   a  and  52   b  for inverting the levels of the nodes ND 2  and ND 1 , respectively, and an output circuit  52   c.  The output circuit  52   c  has a pMOS transistor and an nMOS transistor arranged in series between the power supply line VDD and the ground line VSS. The gate of the pMOS transistor of the output circuit  52   c  is connected to the node /ND 2 . The gate of the nMOS transistor of the output circuit  52   c  is connected to the node /ND 1  through an inverter.  
         [0079]    In the input circuit  30 A shown in FIG. 6, when the internal clock signal /ICLK is at high level (inactivated state), the nMOS transistors  46   a  and  46   b  of the precharging part  46  turn on so that the input nodes ND 1  and ND 2  of the CMOS inverters  36   a  and  36   b  both change to low level. Here, the pMOS transistor  44   a  of the power supply connection part  44  is off. While the nodes ND 1  and ND 2  are at low level, the outputs of the inverters  52   a  and  52   b  of the buffer part  52 , i.e., the nodes /ND 1  and /ND 2  are high in level, turning on the nMOS transistors  48   a  and  48   b  of the feedback part  48 . Consequently, when the internal clock signal /ICLK is inactivated, the input nodes ND 1  and ND 2  of the CMOS inverters  36   a  and  36   b  are connected to the nMOS transistors  50   a  and  50   b  of the input part  50  through the nMOS transistors  48   a  and  48   b  of the feedback part  48 .  
         [0080]    Next, the internal address signal IAD is supplied before the internal clock signal /ICLK changes to low level (an activated state). The low level of the internal clock signal /ICLK turns off the nMOS transistors  46   a,    46   b  of the precharging part  46  and turns on the pMOS transistor  44   a  of the power supply connection part  44 . Since the pMOS transistor  44   a  is turned on, the latching part  36  is activated to be capable of latching the internal address signal IAD.  
         [0081]    For example, when the internal address signal IAD is at high level, the nMOS transistor  50   b  turns on and the nMOS transistor  50   a  turns off. Since the nMOS transistors  48   a  and  48   b  of the feedback part  48  are on, the node ND 1  alone is connected to the ground line VSS through the nMOS transistors  48   b  and  50   b.  The node ND 1  falls in voltage and the node ND 2  rises in voltage, turning on the pMOS transistor  36   a  and off the pMOS transistor  36   b  of the CMOS inverter  36 . Consequently, an operation of opposite polarity from in the first embodiment is performed, whereby the internal address signal IAD of high level is latched into the latching part  36 .  
         [0082]    The inverters  52   a  and  52   b  of the buffer part  52  amplify the low level of the node ND 1  and the high level of the node ND 2 , whereby the nodes /ND 1  and /ND 2  are changed to the power supply voltage VDD and the ground voltage VSS, respectively. The output circuit  52   c  of the buffer part  52  receives the low level of the node /ND 2  and the inverted level (low level) of the node /ND 1 , and changes the latched address signal LAD to high level. That is, the logic level of the internal address signal IAD latched in the latching part  36  (the power supply voltage VDD) is output.  
         [0083]    Moreover, the nMOS transistor  48   b  of the feedback part  48  remains turned on under the high level of the node /ND 1 . The nMOS transistor  48   a  of the feedback part  48  is turned off in response to the low level of the node /ND 2 . The input node ND 1  of the CMOS inverter  36   a  is connected to the ground line VSS through the nMOS transistors  48   b  and  50   b,  so that the latching state of the latching part  36  is fixed irrespective of the level of the internal address signal IAD.  
         [0084]    As above, the second embodiment can provide the same effects as those of the first embodiment.  
         [0085]    [0085]FIG. 7 shows the details of input circuits  30 B according to a third embodiment of the present invention. The same elements as those of the first embodiment described above will be designated by identical reference numbers or symbols. Detailed description thereof will be omitted.  
         [0086]    The input circuits  30 B are formed instead of the input circuits  30  of the first embodiment (FIG. 3). That is, the input circuits  30 B receive the internal address signal IAD in synchronization with the internal clock signal ICLK and output the received signal as the latched address signal LAD. Incidentally, the input circuits of the command latch/decoder (not shown) formed on the SDRAM of this embodiment are the same circuits as the input circuits  30 B.  
         [0087]    An input circuit  30 B has an input part  32 , a feedback part  54 , a latching part  36 , a precharging part  38 , a power supply connection part  40 , and a buffer part  56 .  
         [0088]    In the input part  32 , the gates of the pMOS transistors  32   a  and  32   b  receive the internal address signals /IAD and IAD, respectively. The drains of the pMOS transistors  32   a  and  32   b  are connected to the sources of the PMOS transistors of the CMOS inverters  36   a  and  36   b.  The sources of the pMOS transistors  32   a  and  23   b  are connected to the power supply line (second power supply line) VDD. The power supply voltage (second power supply voltage) VDD to be supplied to the power supply line VDD is set at 2.3 V.  
         [0089]    The feedback part  54  is composed of PMOS transistors  54   a  and  54   b  which are connected at their drains to the sources of the pMOS transistors of the CMOS inverters  36   a  and  36   b,  respectively. The gates of the pMOS transistors  54   a  and  54   b  receive the same level (NND 1 ) as that of the node ND 1  and the inverted level (NND 2 ) of the node /ND 2 , respectively, which are supplied through the buffer part  56 . The sources of the pMOS transistors  54   a  and  54   b  are connected to the power supply line VDD.  
         [0090]    The buffer part  56  has a buffer  56   a  for transmitting the logic level of the node ND 1 , an inverter  56   b  for inverting the logic level of the node ND 2 , and an output circuit  56   c.  The output circuit  56   c  has a pMOS transistor and an nMOS transistor arranged in series between the power supply line VDD and the ground line VSS. The gate of the pMOS transistor of the output circuit  56   c  is connected to the output of the buffer  56   a,  i.e., the node NND 1 . The gate of the nMOS transistor of the output circuit  56   c  is connected to the output of the inverter  56   b,  i.e., the node /ND 2 .  
         [0091]    The input circuit  30 B described above, as in the first embodiment, latches the internal address signal IAD in synchronization with the rising edge of the internal clock signal ICLK. The state when the internal clock signal ICLK is inactivated and the latching operation when the internal clock signal ICLK is activated are the same as in the first embodiment. Description thereof will thus be omitted.  
         [0092]    In this embodiment, the input node ND 1  of the CMOS inverter  36   a  is connected to the power supply line VDD through the pMOS transistor of the CMOS inverter  36   b  and the pMOS transistor  32   b  (or  54   b ). Similarly, the input node ND 2  of the CMOS inverter  36   b  is connected to the power supply line VDD through the PMOS transistor of the CMOS inverter  36   a  and the pMOS transistor  32   a  (or  54   a ). That is, the input nodes ND 1  and ND 2  are connected to the power supply line VDD through two stages of transistors connected in series. This is one stage fewer than heretofore (FIGS. 1 and 2). Consequently, even if the power supply voltage VDD is as low as 2.3 V, the voltage difference between the nodes ND 1  and ND 2  can be widened quickly and surely in accordance with the internal address signal IAD. In addition, the pMOS transistors  32   a  and  32   b,  both having an amplifying function, are directly connected to the power supply line VDD at their sources. Small changes in the voltage of the internal address signal IAD can thus be amplified and output to the drains of the pMOS transistors  32   a  and  32   b  quickly with reliability. As a result, the operation margin of the input circuits  30 B with respect to the power supply voltage improves as compared to heretofore.  
         [0093]    As above, the third embodiment can provide the same effects as those of the first embodiment.  
         [0094]    [0094]FIG. 8 shows the details of input circuits  30 C according to a fourth embodiment of the present invention. The same elements as those of the second embodiment described above will be designated by identical reference numbers or symbols. Detailed description thereof will be omitted.  
         [0095]    The input circuits  30 C are formed instead of the input circuits  30 A of the second embodiment (FIG. 6). That is, the input circuits  30 C receive the internal address signal IAD in synchronization with the internal clock signal /ICLK and output the received signal as the latched address signal LAD. Incidentally, the input circuits of the command latch/decoder (not shown) formed on the SDRAM of this embodiment are the same circuits as the input circuits  30 C.  
         [0096]    The input circuits  30 C are the input circuits  30 B shown in FIG. 7, inverted in polarity. More specifically, by way of comparison between the input circuits  30 C and the input circuits  30 B, the nMOS transistors and pMOS transistors, as well as the power supply line VDD and ground line VSS, are replaced with each other.  
         [0097]    An input circuit  30 C has a power supply connection part  44 , a latching part  36 , a precharging part  46 , a feedback part  58 , an input part  50 , and a buffer part  60 . The feedback part  58  is composed of nMOS transistors  58   a  and  58   b  which are connected at their drains to the sources of the nMOS transistors of the CMOS inverters  36   a  and  36   b,  respectively. The gates of the nMOS transistors  58   a  and  58   b  receive the same level (NND 1 ) as that of the node ND 1  and the inverted level (NND 2 ) of the node /ND 2 , respectively, which are supplied through the buffer part  60 . The sources of the nMOS transistors  58   a  and  58   b  are connected to the ground line VSS.  
         [0098]    The buffer part  60  has a buffer  60   a  for transmitting the logic level of the node ND 1 , an inverter  60   b  for inverting the logic level of the node ND 2 , and an output circuit  60   c.  The output circuit  60   c  has a pMOS transistor and an nMOS transistor arranged in series between the power supply line VDD and the ground line VSS. The gate of the PMOS transistor of the output circuit  60   c  is connected to the output of the inverter  60   b,  i.e., the node /ND 2 . The gate of the nMOS transistor of the output circuit  60   c  is connected to the output of the buffer  60   a,  i.e., the node NND 1 .  
         [0099]    The input circuit  30 C described above, as in the second embodiment, latches the internal address signal IAD in synchronization with the falling edge of the internal clock signal /ICLK. The state when the internal clock signal /ICLK is inactivated and the latching operation when the internal clock signal /ICLK is activated are the same as in the second embodiment. Description thereof will thus be omitted.  
         [0100]    As above, the fourth embodiment can provide the same effects as those of the first and second embodiments.  
         [0101]    [0101]FIG. 9 shows a fifth embodiment of the present invention. The same elements as those of the first embodiment described above will be designated by identical reference numbers or symbols. Detailed description thereof will be omitted.  
         [0102]    In this embodiment, the command signal CMD and the address signal AD supplied to the external terminals of the SDRAM are supplied directly to input circuits  26 D and  30 D without the intervention of input buffers. Moreover, the SDRAM has a phase adjustment circuit DLL for adjusting the phase of the internal clock signal ICLK. The phase adjustment circuit DLL adjusts the internal clock signal ICLK to the clock signal CLK in phase and outputs the resultant as an internal clock signal ICLK 2 . That is, the phase adjustment circuit DLL functions as a DLL (Delayed Locked Loop) circuit for advancing the phase of the internal clock signal ICLK by the delay time of the clock buffer  12  which receives the clock signal CLK. The rest of the configuration is the same as in the first embodiment.  
         [0103]    [0103]FIG. 10 shows the details of the input circuits  30 D in the address latch circuit  20 D shown in FIG. 9. Incidentally, the input circuits  26 D of the command latch/decoder  18 D are the same circuits as the input circuits  30 D. Description will thus be omitted of the input circuits  26 D.  
         [0104]    The input circuits  30 D are the same circuits as the input circuits  30  of the first embodiment except in that different signals are input thereto. More specifically, the gate of the pMOS transistor  32   a  of the input part  32  is supplied with a reference voltage VREF, not the internal address signal /IAD. The gate of the pMOS transistor  32   b  of the input part  32  is supplied with the address signal AD directly. The gates of the pMOS transistors  38   a,    38   b  of the precharging part  38  and the gate of the nMOS transistor  40   a  of the power supply connection part  40  are supplied with the internal clock signal ICLK 2 , not the internal clock signal ICLK.  
         [0105]    The reference voltage VREF is a voltage between the minimum input voltage at the high-level side (typically represented as a voltage specification VIH) and the maximum input voltage at the low-level side (typically represented as a voltage specification VIL) of the input signal (AD or CMD). The reference voltage VREF is generated by a not-shown voltage generator formed on the SDRAM. Otherwise, the reference voltage VREF is input from the exterior of the SDRAM.  
         [0106]    In the input circuit  30 D shown in FIG. 10, when the voltage of the address signal AD is higher than the reference voltage VREF, the pMOS transistor  32   b  for receiving the address signal AD exceeds the pMOS transistor  32   a  for receiving the reference voltage VREF in source-to-drain resistance. This raises the voltage of the node ND 2 , making the latching part  36  out of balance. The subsequent operations are the same as those of the input circuits  30  in the first embodiment. Incidentally, the amplitude of the address signal AD is smaller than the voltage difference between the power supply voltage VDD and the ground voltage VSS.  
         [0107]    Now, when the voltage of the address signal AD is lower than the reference voltage VREF, the pMOS transistor  32   b  for receiving the address signal AD falls below the PMOS transistor  32   a  for receiving the reference voltage VREF in source-to-drain resistance. This raises the voltage of the node ND 1 , making the latching part  36  out of balance. The subsequent operations are the same as those of the input circuits  30  of the first embodiment.  
         [0108]    In this embodiment, the source of the pMOS transistor  32   a  for receiving the reference voltage VREF is connected directly to the power supply line VDD. Consequently, when the input circuit  30 D is in operation, the source of the PMOS transistor  32   a  is fixed to the power supply voltage VDD. Voltage variations at the drain of the pMOS transistor  32   a  become significantly smaller than heretofore. This makes the reference voltage VREF less susceptible to coupling noise resulting from voltage variations across the source and drain of the pMOS transistor  32   a.  As a result, the input circuit  30 D can be prevented from malfunction (incorrect latch of the address signal AD).  
         [0109]    On the contrary, in the conventional input circuit (FIG. 2), the pMOS transistors  9   a  and  9   b  of the input part  9  are connected to the power supply line VDD through the PMOS transistor  10   a  of the power supply connection part  10 . In latching the input signal IN, the pMOS transistor  9   b  for receiving the reference voltage VREF thus varies at both the source and the drain, so that the reference voltage VREF fluctuates due to the coupling noise of the pMOS transistor  9   b.    
         [0110]    [0110]FIG. 11 shows the operation of the input circuit  30 D shown in FIG. 10 (waveforms from a circuit simulation). For a comparative example, the operating waveforms of the conventional input circuit shown in FIG. 2 are presented.  
         [0111]    In the conventional input circuit (FIG. 2), the source and drain of the MOS transistor  9   b  for receiving the reference voltage VREF vary 1 V and more in voltage. On the other hand, in the input circuit  30 D, the drain of the pMOS transistor  32   a  for receiving the reference voltage VREF shows voltage variations of 0.5 V and less. That is, the reference voltage VREF is less susceptible to the coupling noise of the pMOS transistor  32   a.    
         [0112]    As above, the fifth embodiment can provide the same effects as those of the first embodiment. In addition, the operation margin can be improved even if the input circuits  30 D are supplied with an address signal AD of smaller amplitude. The address signal AD can thus be latched with reliability.  
         [0113]    The foregoing second embodiment (FIG. 6) has dealt with the case where the input part  50  is supplied with the complementary internal address signals IAD and /IAD, and the precharging part  46  and the power supply connection part  44  are supplied with the internal clock signal /ICLK. The present invention is not limited thereto. For example, as in the fifth embodiment, the input part  50  may directly receive the address signal AD that is supplied to the external terminal. In this case, the gate of the nMOS transistor  50   a  of the input part  50  is supplied with the reference voltage VREF. The precharging part  46  and the power supply connection part  44  are then supplied with an internal clock signal /ICLK 2  that deviates from the clock signal CLK by 180° in phase.  
         [0114]    Similarly, as shown in FIG. 12, the gates of the pMOS transistors  32   a  and  32   b  of the input part  32  in the third embodiment (FIG. 7) may be supplied with the reference voltage VREF and the address signal AD, respectively. Here, the gates of the pMOS transistors  38   a,    38   b  of the precharging part  38  and the gate of the nMOS transistor  40   a  of the power supply connection part  40  are supplied with the internal clock signal ICLK 2 .  
         [0115]    The gate of the nMOS transistor  50   a  of the input part  50  in the fourth embodiment (FIG. 8) may also be supplied with the reference voltage VREF. Here, the precharging part  46  and the power supply connection part  44  are supplied with the internal clock signal /ICLK 2  which deviates from the clock signal CLK by 180° in phase.  
         [0116]    The data latch circuit described in the first embodiment may be applied to the second to fifth embodiments.  
         [0117]    The foregoing embodiments have dealt with the cases where the present invention is applied to an SDRAM. The present invention is not limited thereto. For example, the present invention may be applied to such semiconductor integrated circuits as SSRAMs, microcomputers, logic LSIs, and system LSIs.  
         [0118]    The invention is not limited to the above embodiments and various modifications may be made without departing from the spirit and scope of the invention. Any improvement may be made in part or all of the components.