Abstract:
A nonlinearity detection system for an analog to digital converter (ADC) comprises a signal generator that generates a periodic signal that is output to the ADC and that comprises first and second intervals. The periodic signal monotonically increases during the first interval and monotonically decreases during the second interval. A differentiator module communicates with the ADC and that generates an output signal that is based on an output of the ADC and a delayed output of the ADC. A nonlinearity detection module detects slope discontinuities in the output signal of the differentiator module.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation of U.S. patent application Ser. No. 10/795,907 filed on Mar. 8, 2004 now U.S. Pat. No. 6,943,712 and claims the benefit of U.S. Provisional Application No. 60/517,722, filed on Nov. 6, 2003, which are hereby incorporated by reference in their entirety. 

   FIELD OF THE INVENTION 
   The present invention relates to analog to digital converters (ADCs), and more particularly to digital non-linearity measurement devices and methods for ADCs. 
   BACKGROUND OF THE INVENTION 
   Analog to digital converters (ADCs) convert an analog input signal to a digital output signal. ADCs are typically implemented on an integrated circuit (IC) or chip. The output of the ADCs typically contain nonlinearity errors that need to be characterized. The nonlinearity errors may occur when the ADC has a higher gain than expected during design, a lower gain than expected during design, multiple input voltages having the same output code, and/or in other situations. 
   In one conventional approach for characterizing the nonlinearity of the ADC, a tone is applied to an input of ADC. Tones are sinusoidal signals having a fixed frequency. Referring now to  FIG. 1 , a test signal generator  10  outputs the tone to an input of an ADC  14 . An output of the ADC  14  is input to a nonlinearity detector  18 . The nonlinearity detector  18  is typically an off-chip device that uses conventional algorithms that detect nonlinearities in the output of the ADC  14 . Time consuming post-processing must be performed to characterize the nonlinearity of the ADC  14 . The post-processing is repeated for different operating conditions such as but not limited to temperature, which increases the characterization time. In some circumstances, it may take on the order of days to properly characterize the ADC  14 . 
   SUMMARY OF THE INVENTION 
   A nonlinearity detection system for an analog to digital converter (ADC) comprises a signal generator that generates a periodic signal that is output to the ADC and that comprises first and second intervals. The said periodic signal monotonically increases during the first interval and monotonically decreases during the second interval. A differentiator module communicates with the ADC and generates an output signal that is based on an output of the ADC and a delayed output of the ADC. A nonlinearity detection module detects slope discontinuities in the output signal of the differentiator module. 
   Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein: 
       FIG. 1  is a functional block diagram of a nonlinearity detector according to the prior art; 
       FIG. 2A  is a functional block diagram of a nonlinearity detection module according to the present invention; 
       FIG. 2B  is a functional block diagram of an exemplary differentiator module; 
       FIG. 2C  is a functional block diagram of one exemplary implementation of the nonlinearity detection module according to the present invention; 
       FIG. 3  are waveforms illustrating the input voltage, output voltage and differentiator module output according to the present invention; 
       FIG. 4  is a waveform illustrating positive and negative maximum and minimum slope ranges of the differentiator module output; 
       FIGS. 5A and 5B  are waveforms illustrating the output voltage of ADC and the output of the differentiator module, respectively, when the gain of the ADC is greater than expected; 
       FIGS. 6A and 6B  are waveforms illustrating the output voltage of ADC and the output of the differentiator module, respectively, when the gain of the ADC is less than expected; 
       FIGS. 7A and 7B  are waveforms illustrating the output voltage of ADC and the output of the differentiator module, respectively, when certain ranges of the ADC have the same output codes; 
       FIG. 8  is a flowchart illustrating steps for characterizing the nonlinearity of the ADC; 
       FIG. 9  is a flowchart illustrating steps for detecting discontinuities in the positive and negative slope regions of the ADC; 
       FIG. 10  is a state diagram for an exemplary implementation of the nonlinearity detection module; and 
       FIG. 11  is a functional block diagram of a network device that includes a physical layer module with nonlinearity detection module. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the term module refers to an application specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality. 
   Referring now to  FIGS. 2A and 2B , a triangle wave generator  50  outputs a triangular wave V in  to an input of the ADC  14 . The triangular wave V in  has alternating regions with positive and negative slopes. The output signal V out  of the ADC  14  is input to a differentiator module  54 . The differentiator module  54  generates an output signal that is biased on V out  and a delayed V out . The output of the differentiator module  54  is input to a nonlinearity detection module  58 , which generates a nonlinearity test pass/fail signal as will be described in further detail below. 
   In one implementation, the differentiator module  54  includes a delay element  59  and a summer  60 . The delay element  59  outputs a delayed V out  to an input of the summer  60 . Another input of the summer  60  receives V out . The summer  60  outputs V 1−D , which is V out  minus a delayed V out . The differentiator module  54  can be a discrete time differentiator, a discrete time filter, a finite impulse response (FIR) filter and/or any other suitable circuit. 
   Referring now to  FIG. 2C , one exemplary implementation of the nonlinearity detection module  58  according to the present invention is shown. A positive/negative slope module  61  identifies positive and negative slope regions (after being differentiated) in the output of the differentiator module  54 . A maximum/minimum positive slope limit module  62  sets maximum and minimum positive slope limits. A maximum/minimum negative slope limit module  64  sets maximum and minimum negative slope limits. A comparing module  66  compares the output of the differentiator module  54  to either the maximum/minimum positive slope limits when the positive slope region occurs or the maximum/minimum negative slope limits when the negative slope region occurs. If the slope values do not fall within the respective limits, the comparing module  66  of the nonlinearity detection module  58  generates a nonlinearity test fail signal. If the slope values fall within the respective limits, the comparing module  66  of the nonlinearity detection module  58  generates a nonlinearity test pass signal. As can be appreciated, the nonlinearity testing components can be implemented on-chip with the ADC  14 . 
   Referring now to  FIG. 3 , the input signal V in , the output signal V out  and the output of the differentiator module V 1−D  are shown at  70 ,  72 , and  74 , respectively. In an ideal ADC, if a triangular waveform is input to an ADC, the output of the ADC is linear and has a constant slope between clipped regions  75 - 1  and  75 - 2  as shown. If the difference between the current ADC output and the previous ADC output (V 1−D ) is plotted, the waveform has three major flat regions: maximum, 0, and minimum. The maximum and minimum values of V 1−D  correspond to the positive and negative slope regions of the rise and fall, respectively. 
   Referring now to  FIG. 4 , since ADCs are neither ideal nor perfectly linear, the maximum and minimum regions of V 1−D  will have a narrow range of values rather than the single value that is shown in  FIG. 3 . In other words, the positive slope will fall between a positive maximum slope value and a positive minimum slope value. The negative slope will fall between a negative minimum slope value and a negative maximum slope value. These expected values are used to set the limits of the limit modules  62  and  64 . The limit values that are selected will be based on the anticipated linearity of the ADC and the desired sensitivity of the nonlinearity test. 
   Referring now to  FIGS. 5A and 5B , if the gain of the ADC  14  is greater than expected during design, the output voltage of the ADC  14  will include non-uniform positive and/or negative slope regions  76  and  78 . These non-uniform positive and/or negative slope regions will cause discontinuities or spikes  80  and  82 , respectively, in the output of the differentiator module  54 . The discontinuities or spikes  80  and  82  represent nonlinearities in the output of the ADC  14 . 
   Referring now to  FIGS. 6A and 6B , if the gain of the ADC  14  is less than expected during design, the output voltage of the ADC  14  will include non-uniform positive and/or negative slope regions  88  and  92 , respectively. These non-uniform positive and/or negative slope regions  88  and  92  will cause discontinuities or spikes  94  and  96 , respectively in the output of the differentiator module  54 . The discontinuities or spikes  94  and  96  fall outside of the respective positive and negative minimum and maximum limits and represent nonlinearities in the output of the ADC  14 . 
   Referring now to  FIGS. 7A and 7B , if the ADC  14  outputs the same output code for certain input voltage regions, the output voltage of the ADC  14  will include non-uniform positive and/or negative slope regions  100  and  102 . These non-uniform positive and/or negative slope regions  100  and  102  will cause discontinuities or spikes  106  and  108 , respectively, in the output of the differentiator module  54 . The discontinuities or spikes  106  and  108  represent nonlinearities in the output of the ADC  14 . 
   Referring now to  FIG. 8 , steps for operating the nonlinearity detector for the ADC  14  are shown. In step  150 , a triangular wave is output to the ADC  14 . In step  152 , the output of the ADC  14  is differentiated. In step  156 , the nonlinearity detection module  58  monitors discontinuities or spikes in the output of the differentiator module  54 . In step  160 , control determines whether the discontinuities or spikes are detected. If not, the ADC  14  passes the test in step  164 . Otherwise, the ADC  14  fails the test in step  166 . 
   Referring now to  FIG. 9 , simplified steps for detecting discontinuities or spikes are shown. In step  200 , control determines whether there is a positive slope region. If true, control determines whether the positive slope of the positive slope region is less than a positive maximum slope value and greater than a minimum positive slope value in step  204 . If step  204  is false, control detects a discontinuity in step  205  and control returns in step  206 . If step  204  is true, control determines whether the positive slope region ended in step  208 . 
   If step  208  is true, control continues with step  204 . If step  208  is false, control continues with step  210  and determines whether the test is over. If step  210  is true, control returns in step  206 . If step  210  is false, control continues with step  200 . If step  200  is false, control continues with step  220  and determines whether there is a negative slope region. If step  220  is false, control continues with step  200 . If step  220  is true, control continues with step  224  and determines whether the negative slope is greater than a negative slope maximum value and less than a negative slope minimum value. If step  224  is true, control determines whether the output of the ADC is still in the negative slope region in step  226 . If step  226  is true, control continues with step  224 . If step  226  is false, control continues with step  210 . If step  224  is false, control detects a discontinuity in step  205  and control returns in step  206 . 
   Referring now to  FIG. 10 , a nonlinearity test state machine  248  for an exemplary 9-bit ADC is shown. As can be appreciated, while  FIG. 10  describes a 9-bit ADC, the ADC can be any n-bit ADC, where n is an integer. Variables used therein are defined as follows: count — 0 is a count of consecutive lowest ADC code, usually code 0. Count — 511 is a count of consecutive highest ADC code. ADC code 511 represents the highest code output (when 9 bit ADCs are used). As can be appreciated, ADCs with other bit lengths will have codes will have a code of (2 n −1). psl_max is a maximum slope for positive slope regions. psl_min is a minimum slope for positive slope regions. nsl_max is a maximum slope for negative slope regions. nsl_min is a minimum slope for negative slope regions. 
   When an enable signal is equal to zero, the state machine  248  goes to a RESET state  250 . In the RESET state  250 , variables are initialized as shown. When the enable signal is asserted, the state machine  248  moves to a WAIT state  254 . In the WAIT state  254 , it aligns to either the clip waveform region where the ADC code equals 0 (clip region 0) or the clip waveform region where the ADC code equals 511 (clip region 511). Variables count — 0 and count — 511 count the number of consecutive ADC codes equal to 0 or 511, respectively. When count — 0 or count — 511 reaches a count threshold, the waveform is either in clip region 0 or clip region 511. When a different ADC code is encountered after the count threshold has been reached, the state machine  248  moves to either 0 — 511_skip state  258  or 511 — 0_skip state  262 . In either of the states  258  or  262 , the slope based on this ADC  14  is not included in the calculation of the maximum and minimum slopes. In the next cycle, the state machine  248  moves to either 0 — 511 state  264  or  511   — 0 state  268 , respectively, where the maximum and minimum slopes are calculated based on the following equations:
     if((state == 0 — 511) &amp; ˜((ADC==0) &amp; (prev_ADC==0)) &amp; ˜((ADC==511) &amp; (prev_ADC==511)))
       begin   (delta &gt; psl_max) ? (psl_max = delta) : psl_max   (ADC!=511) &amp; (delta &lt; psl_min)(psl_min=delta) : psl_min   end   
       if((state==511 — 0) &amp; ˜((ADC==0) &amp; (prev_ADC==0)) &amp; ˜((ADC==511) &amp; (prev_ADC==511)))
       (delta &lt; nsl_min) ? (nsl_min = delta) : nsl_min   (ADC!=0) &amp; (delta &gt; nsl_max) (nsl_max=delta) : nsl_max   end   
       

   Referring now to  FIG. 11 , a network device  310  is shown that includes a physical layer module  314 , which includes the triangle wave generator  50 , the ADC  14 , the differentiator module  54 , and the non-linearity detection module  58 . The physical layer module  314  communicates with a medium  315 . In one embodiment, the medium  315  includes one or more twisted pairs of wire, although other media may be used. The output of the non-linearity detection module  58  may be sent to one or more other physical layer circuits  318 , to a medium access control (MAC) module  320  and/or other layers  322 . 
   The network device  310  can be an Ethernet network device that is wireless or wired. In one embodiment, the Ethernet network device is a wired network that is compliant with 1000BaseT. Still other implementations will be apparent to skilled artisans. 
   Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.