Abstract:
The diode drops associated with the output voltage from a conventional charge pump are eliminated in the present invention with a dual-chain charge pump that utilizes the pumped voltages from each charge pump chain to drive the gates of the other charge pump chain. As a result, the voltages on the gates of the transistors are pumped up to a level such that there is no threshold voltage drop across the transistor, and thus, making it behave like an ideal switch.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to charge pumps and, more particularly, to a cross-coupled, dual-chain charge pump, that is referred here as a bootstrapped charge pump. 
     2. Description of the Related Art 
     Historically, semiconductor devices that required voltages that were greater than the power supply voltage utilized dedicated pins to input the required voltages from an off-chip supply. Current-generation non-volatile memory devices, however, commonly use a charge pump, which utilizes the power supply voltage and ground, to generate the required voltages on the chip. 
     Thus, by utilizing a charge pump, dedicated pins are no longer required to input voltages from an off-chip supply that are greater than the power supply voltage. As a result, the total pin count of a device can be reduced accordingly. This is a significant advantage to current-generation chips that often have a limited number of pins available. Although charge pumps can provide the needed voltages from the power supply voltage and ground, charge pumps typically suffer from a low current drive (can source only a limited amount of current). 
     FIG. 1 shows a schematic diagram that illustrates a conventional charge pump  100 . As shown in FIG. 1, charge pump  100  includes a number of stages SG 1 -SGn that are serially connected together to form a chain. Each stage SG in the chain progressively “pumps” or increases the voltage input to the stage to achieve the needed voltage. 
     Stages SG 1 -SGn include a corresponding number of input nodes NI 1 -NIn, output nodes NO 1 -NOn, and diode-connected n-channel transistors DN 1 -DNn. Each transistor DN has a gate and drain connected to an input node NI and a source connected to an output node NO. In addition, stages SG 1 -SGn also include a corresponding number of capacitors CAP 1 -CAPn, switching nodes NS 1 -NSn, and switches SW 1 -SWn. Each capacitor CAP is connected between an output node NO and a switching node NS. Each switch SW, in turn, is connected to a switching node NS, and either a power supply voltage VCC or ground, depending on the logic state of a clock signal. 
     As further shown in FIG. 1, first stage SG 1  receives an input voltage VI such as the power supply voltage VCC, while last stage SGn outputs a pumped voltage VPM on output node NOn. The output node NO of each remaining stage is connected to the input node NI of the next stage SG in the chain. 
     In operation, the switch SW in each odd-numbered stage SG is controlled by a first clock signal PH 1 , while the switch SW in each even-numbered stage SG is controlled by a second clock signal PH 2  that is 180° out-of-phase with the first clock signal PH 1 . For both clock signals PH 1  and PH 2 , when the clock signal is asserted, the switch SW is connected to ground. On the other hand, when the clock signal is de-asserted, the switch is connected to the power supply voltage VCC. 
     Thus, when the first clock signal PH 1  is asserted, first switch SW 1  is connected to ground. In this condition, the gate-to-source voltage VGS of transistor DN 1  is greater than the threshold voltage VTH 1  of transistor DN 1 . As a result, transistor DN 1  turns on and a current flows from the input node NI 1  to the output node NO 1  until the voltage VO on output node NO 1  rises to a value that is a threshold voltage drop less than the power supply voltage VCC. 
     When the voltage VO on output node NO 1  is a threshold voltage drop less than the power supply voltage VCC (VO=VCC−VTH 1 ), transistor DN 1  turns off as transistor DN 1  conducts only as long as the gate-to-source voltage VGS is greater than the threshold voltage VTH 1 . As a result, the voltage across capacitor CAP 1  is also equal to VCC−VTH 1 . 
     When the first clock signal PH 1  is de-asserted, switch SW 1  of the first stage SG 1  is connected to the power supply voltage VCC. Since transistor DN 1  is turned off, thereby isolating output node NO 1  from the input node NI 1 , the power supply voltage VCC on switching node SW 1  also appears on output node NO 1  due to the principle of charge neutrality. As a result, the voltage VO 1  on the output node NO 1  is defined in equation EQ. 1 as: 
     
       
           VO   1   =VCC−VTH   1 + VCC= 2 VCC−VTH   1 .  EQ. 1 
       
     
     Thus, the voltage VO 1  on output node NO 1  is greater by the power supply voltage VCC when the first clock signal PH 1  is de-asserted. 
     At the same time that the first clock signal PH 1  is de-asserted, the second clock signal PH 2  is asserted which, in turn, causes switch SW 2  to be connected to ground. As with transistor DN 1 , transistor DN 2  turns on until the voltage VO 2  on output node NO 2  is a threshold voltage drop less than the voltage on input node NI 2 /output node NO 1 . 
     The voltage VO 2  on output node NO 2  takes several clock cycles to reach 2VCC−VTH 1 −VTH 2 . This is because, unlike transistor DN 1  where the current is delivered from the power supply voltage VCC, the current flowing into the output node NO 2  from input node NI 2 /output node NO 1  reduces the voltage on input node NI 2 /output node NO 1 , and thus, additional cycles are needed for the nodes to reach their full potentials. 
     When the second clock signal PH 2  is de-asserted, switch SW 2  is connected to the power supply voltage VCC which, in turn, causes the voltage VO 2  on output node NO 2  to be increased by the power supply voltage VCC. This process continues as described above. Thus, charge pump  100  shifts electrons from the output node NO to the input node NI of each stage SG until the pumped voltage VPM on output node NOn is equal to: 
     
       
           VPM=n ( VCC )−( VTH   1   +VTH   2   + . . . +VTHn ).  EQ. 2 
       
     
     (The pumped voltage VPM is actually slightly less due to the body effect of the transistors DN in each stage SG.) 
     One disadvantage of charge pump  100  is that the pump voltage VPM is reduced by the combined threshold voltage drops (VTH 1 +VTH 2 + . . . +VTHn). The transistors in the charge pump, being configured as diodes, do not act as ideal switches, as in the case of an ideal charge pump. Further, the drive strength of the pump is greatly reduced when current is drawn from the pump. In some cases, an additional stage SG may need to be added to compensate for this loss, thereby increasing the size and cost of the charge pump. Thus, there is a need for a charge pump that outputs a pumped voltage VPM that is not reduced by the accumulated threshold voltage drops. 
     SUMMARY OF THE INVENTION 
     The charge pump of the present invention outputs a pumped voltage that is not reduced by the accumulated threshold voltage drops by utilizing a dual-chain charge pump where the pumped voltages from each charge pump chain drive the gates of the other charge pump chain. As a result, the voltages on the gates of the transistors are pumped up to be at least one diode drop greater than the voltages on the drains of the n-channel transistors, and one diode drop less than the voltages on the sources of the p-channel transistors. 
     In the charge pump of the present invention, the diode drops associated with the transistors are eliminated as a result of the pumped voltages on the drains/sources of the transistors of each pump that gets coupled to the gates of the transistors of the other pump. This makes the transistors act as ideal switches, and thus, enables the voltages on the sources/drains of the transistors to reach their full potentials, without being limited by their threshold voltages. Thus, this cross-coupled charge pump exhibits a bootstrapping phenomena, as the sources/drains are bootstrapped to reach their full potentials. Hence, the charge pump of the present invention is referred to as a bootstrapped charge pump. 
     A charge pump stage in accordance with the present invention includes a bottom transistor and a top transistor. The bottom transistor has a first node, a gate, and a second node. The top transistor has a third node, a gate connected to the second node of the bottom transistor, and a second node connected to the gate of the bottom transistor. 
     The charge pump stage also includes a bottom capacitor that is connected between the second node of the bottom transistor and a first clock signal, and a top capacitor that is connected between the second node of the top transistor and a second clock signal. The second clock signal is out-of-phase and non-overlapping with the first clock signal. 
     A charge pump in accordance with the present invention includes a plurality of stages that are connected together in series. Each stage has a bottom transistor and a top transistor. The bottom transistor has a first node, a gate, and a second node, while the top transistor has a first node, a gate connected to the second node of the bottom transistor, and a second node connected to the gate of the bottom transistor. 
     Each stage also has a bottom capacitor that is connected between the second node of the bottom transistor and either a first clock signal or a second clock signal. The first clock signal is connected when a stage is an odd-numbered stage, while the second clock signal is connected when a stage is an even-numbered stage. 
     Each stage further has a top capacitor that is connected between the second node of the top transistor and either the first clock signal or the second clock signal. The first clock signal is connected when a stage is an even-numbered stage, while the second clock signal is connected when a stage is an odd-numbered stage. The second clock signal is out-of-phase and non-overlapping with the first clock signal. 
     The plurality of stages are connected together so that, excluding a last stage, the second nodes of the bottom and top transistors in each stage are connected to the first nodes of the bottom and top transistors, respectively, in an adjacent stage, and so that, excluding a first stage, the first nodes of the bottom and top transistors in each stage are connected to the second nodes of the bottom and top transistors, respectively, in an adjacent stage. 
     A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram illustrating a conventional charge pump  100 . 
     FIG. 2 is a schematic diagram illustrating a charge pump  200  in accordance with the present invention. 
     FIG. 3 is a schematic diagram illustrating a charge pump  300  in accordance with the present invention. 
     FIG. 4 is a schematic diagram illustrating a charge pump  400  in accordance with the present invention. 
     FIG. 5 is a schematic diagram illustrating a charge pump  500  in accordance with the present invention. 
     FIG. 6 is a schematic diagram illustrating a charge pump  600  in accordance with the present invention. 
     FIG. 7 is a schematic diagram illustrating a charge pump  700  in accordance with the present invention. 
     FIG. 8 is a schematic diagram illustrating a charge pump  800  in accordance with the present invention. 
     FIG. 9 is a schematic diagram illustrating a charge pump  900  in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION 
     FIG. 2 shows a schematic diagram that illustrates a charge pump  200  in accordance with the present invention. As shown in FIG. 2, charge pump  200  includes a number of stages SG 1 -SGn that are serially connected together to form a chain. The stages SG 1 -SGn have a number of bottom transistors BT 1 -BTn and a corresponding number of top transistors TT 1 -TTn. Each bottom transistor BT in a stage SG has a drain, a gate, and a source. Each top transistor TT in the stage SG has a drain, a gate connected to the source of the bottom transistor BT, and a source connected to the gate of the bottom transistor BT. 
     The stages SG 1 -SGn also have a number of bottom capacitors BC 1 -BCn and a corresponding number of top capacitors TC 1 -TCn. Each bottom capacitor BC in a stage SG is connected between the source of a bottom transistor BT and either a first clock signal PH 1  or a second clock signal PH 2 . The first clock signal PH 1  is utilized when the stage SG is an odd-numbered stage, while the second clock signal PH 2  is utilized when the stage SG is an even-numbered stage. 
     In addition, each top capacitor TC in a stage SG is connected between the source of the top transistor TT and either the first clock signal PH 1  or the second clock signal PH 2 . The first clock signal PH 1  is utilized when the stage SG is an even-numbered stage, while the second clock signal PH 2  is utilized when the stage SG is an odd-numbered stage. 
     The second clock signal PH 2  is out-of-phase and non-overlapping with the first clock signal PH 1 . In addition, both clock signals PH 1  and PH 2  alternate between a logic high voltage level such as the power supply voltage VCC, and a logic low voltage level such as ground (the logic low level can also be negative). 
     Stages SG 1 -SGn are connected together so that, with the exception of the last stage SGn, the sources of the bottom and top transistors BT and TT in each stage SG are connected to the drains of the bottom and top transistors BT and TT, respectively, in an adjacent stage SG. In addition, the drains of both the bottom and top transistors BT 1  and TT 1  in the first stage SG 1  are connected to receive the input voltage VIN (such as the power supply voltage VCC). Further, the sources of the bottom and top transistors BTn and TTn in the last stage SGn output a pumped bottom voltage PBV, and a pumped top voltage PTV, respectively. 
     The operation of charge pump  200  is illustrated with a two-stage charge pump. When the clock signal PH 1  falls to the logic low voltage level, a logic low potential approximately equal to the logic low voltage level is capacitively coupled to the source of bottom transistor BT 1 . Due to the cross coupling, the logic low potential is also coupled to the gate of top transistor TT 1 . When the clock signal PH 2  rises to the logic high voltage level, a logic high potential approximately equal to the logic high voltage level is capacitively coupled to the source of top transistor TT 1 , and to the gate of bottom transistor BT 1 . 
     In this condition, the gate-to-source voltage of bottom transistor BT 1  is greater than its threshold voltage. As a result, bottom transistor BT 1  turns on and the voltage on the source of bottom transistor BT 1  rises to a value that is equal to the logic high potential less the threshold voltage of bottom transistor BT 1 . The gate-to-source voltage of top transistor TT 1 , on the other hand, is less than its threshold voltage. As a result, top transistor TT 1  is turned off. 
     When the clock signal PH 2  switches back to the logic low voltage level from the logic high voltage level, the logic low potential is capacitively coupled to the source of top transistor TT 1 . Due to the cross coupling, the logic low potential is also coupled to the gate of bottom transistor BT 1 . When the clock signal PH 1  rises to the logic high voltage level, the logic high potential is capacitively coupled to the source of bottom transistor BT 1 . 
     However, since a voltage equal to the logic high potential less the threshold voltage of bottom transistor BT 1  is already on the source of bottom transistor BT 1 , the capacitively coupled logic high potential raises the potential on the source of bottom transistor BT 1 . The potential is raised by the difference between the logic low potential and the logic high potential to a potential equal to twice the logic high potential less the threshold voltage of bottom transistor BT 1 . 
     Due to the cross coupling, this same potential, which is more than one threshold voltage drop greater than the voltage on the drain of top transistor TT 1 , also sits on the gate of top transistor TT 1 . Thus, the voltage on the source of top transistor TT 1  rises to the input voltage VIN. 
     When the clock signal PH 1  switches back to the logic low voltage level from the logic high level, the logic low potential is capacitively coupled to the source of bottom transistor BT 1 . This reduces the potential on the source from twice the logic high potential less the threshold voltage of the bottom transistor to a single logic high potential less the threshold voltage of the bottom transistor. Due to the cross coupling, the same potential also sits on the gate of top transistor TT 1 . 
     When the clock signal PH 2  again rises to the logic high voltage level, the logic high potential is capacitively coupled to the source of top transistor TT 1 . However, since a voltage equal to the input voltage VIN is already on the source of top transistor TT 1 , the capacitively coupled logic high potential raises the potential on the source of top transistor TT 1 . The potential is raised by the value of the logic high potential so that a potential equal to the input voltage plus the logic high potential is on the source of top transistor TT 1 . 
     Due to the cross coupling, this same potential, which is more than one threshold voltage drop greater than the voltage on the drain of bottom transistor BT 1 , also sits on the gate of bottom transistor BT 1 . Thus, the voltage on the source of bottom transistor BT 1  rises to the input voltage VIN. 
     Thus, as the first clock signal PH 1  switches between the logic low voltage level and the logic high voltage level, the potential on the source of bottom transistor BT 1  switches between the input voltage VIN and the input voltage VIN plus the logic high potential. Similarly, as the second clock signal PH 2  switches between the logic low voltage level and the logic high voltage level, the potential on the source of top transistor TT 1  switches between the input voltage VIN and the input voltage VIN plus the logic high potential. Since the logic high potential is approximately equal to the input voltage VIN, the potentials on the sources of the bottom and top transistors of stage SG 1  roughly swing between VIN and  2 VIN. Thus, in accordance with the present invention, charge pump  200  provides pumped voltages that are not reduced by the threshold voltages of the pumping transistors. 
     When stage SG 2  is added, the adjoining bottom transistors are switched on and off out-of-phase so that when one transistor is on, the adjoining transistors are off. This allows the highest potential from stage SG 1  to become the lowest potential of stage SG 2 . Thus, the final predischarge potential on the source of bottom transistor BT 2  in stage SG 2  switches between the highest potential that is on the source of bottom transistor BT 1 , and this potential plus the logic high potential. 
     Similarly, the adjoining top transistors are switched on and off out-of-phase so that when one transistor is on, the adjoining transistors are off. This allows the highest potential from stage SG 1  to become the lowest potential of stage SG 2 . Thus, the final predischarge potential on the source of top transistor TT 2  in stage SG 2  switches between the highest potential that is on the source of top transistor TT 1 , and this potential plus the logic high potential. Since the logic high potential is approximately equal to the input voltage VIN, the potentials on the sources of the bottom and top transistors of stage SG 2  roughly swing between 2VIN and 3VIN. 
     Thus, for n stages, the final potential on the source of the bottom transistor of the nth stage switches between the input voltage VIN plus n−1 times the logic high potential; and the input voltage VIN plus n times the logic high potential. Similarly, the final potential on the source of the top transistor of the nth stage switches between the input voltage VIN plus n−1 times the logic high potential; and the input voltage VIN plus n times the logic high potential. 
     When additional stages are utilized, it takes a number of clock cycles before the sources of the bottom and top transistors BTn and TTn in the last stage SGn reach their final predischarge potentials. With the bottom and top transistors BT 1  and TT 1  in the first stage SG 1 , the currents to the sources are delivered by the power supply voltages VCC on the drains. 
     However, the drains of the top and bottom transistors of an additional stage SG, which are otherwise electrically isolated, are able to conduct a part of the currents to the sources of the additional stage as long as the increasing source potential does not turn off the transistor. Thus, it takes a number of clock cycles to shift or pump the charge to the sources of the transistors in the last stage SGn from the input voltage VIN connected to the drains on the transistors in the first stage SG 1 . The larger the difference between the logic low voltage level and the logic high voltage level, the greater the amount of charge that can be pumped each cycle. 
     FIG. 3 shows a schematic diagram that illustrates a charge pump  300  in accordance with the present invention. Charge pump  300  is similar to charge pump  200  and, as a result, utilizes the same reference numerals to designate the structures that are common to both pumps. 
     As shown in FIG. 3, pump  300  differs from pump  200  in that pump  300  includes a first diode-connected transistor DT 1  and a second diode-connected transistor DT 2 . Transistor DT 1  has a drain and a gate connected to the source of the top transistor TTn in the last stage SGn, and a source connected to an output node NOUT. Transistor DT 2  has a drain and a gate connected to the source of the bottom transistor BTn in the last stage SGn, and a source connected to the output node NOUT. 
     In operation, the voltage on the source of transistor DT 1  has an approximately square waveform that switches between first and second voltages. The first voltage is equal to the input voltage VIN plus n−1 times the logic high potential less the threshold voltage of transistor DT 1 . The second voltage is equal to the input voltage VIN plus n times the logic high potential less the threshold voltage of transistor DT 1 . 
     Similarly, the voltage on the source of transistor DT 2  has an approximately square waveform that switches between first and second voltages. The first voltage being equal to the input voltage VIN plus n−1 times the logic high potential less the threshold voltage of transistor DT 2 . The second voltage being equal to the input voltage VIN plus n times the logic high potential less the threshold voltage of transistor DT 2 . 
     The voltages on the sources of transistors DT 1  and DT 2  are 180° out-of-phase such that the first voltage on the source of transistor DT 1  and the second voltage on the source of transistor DT 2  are present at the same time. As a result, an approximately constant voltage equal to the input voltage VIN plus n times the logic high potential less the threshold voltage of transistor DT 1  (the threshold voltages of transistors DT 1  and DT 2  are assumed to be the same) is present on the output node NOUT. 
     FIG. 4 shows a schematic diagram that illustrates a charge pump  400  in accordance with the present invention. Charge pump  400  is similar to charge pump  200  and, as a result, utilizes the same reference numerals to designate the structures that are common to both pumps. 
     As shown in FIG. 4, pump  400  differs from pump  200  in that pump  400  includes an n-channel first transistor Q 1  and an n-channel second transistor Q 2 . First transistor Q 1  has a drain connected to the source of the bottom transistor BTn in the last stage SGn, a gate, and a source connected to an output node NOUT. Second transistor Q 2  has a drain connected to the source of the top transistor TTn in the last stage SGn, a gate, and a source connected to the output node NOUT. 
     Pump  400  also includes an n-channel third transistor Q 3  and an n-channel fourth transistor Q 4 . Third transistor Q 3  has a drain connected to the source of transistor Q 1  and the output node NOUT, a gate connected to the gate of transistor Q 1 , and a source. Fourth transistor Q 4  has a drain connected to the source of transistor Q 2  and the output node NOUT, a gate connected to the gate of transistor Q 2  and the source of transistor Q 3 , and a source connected to the gate of transistor Q 3 . 
     Pump  400  additionally includes a bottom capacitor CAP 1  and a top capacitor CAP 2 . Bottom capacitor CAP 1  is connected between the source of transistor Q 3  and the clock signal that is the same as the clock signal that is connected to the top capacitor TCn in the last stage SGn. Top capacitor CAP 2  is connected between the source of transistor Q 4  and the clock signal that is the same as the clock signal that is connected to the bottom capacitor BCn in the last stage SGn. Bottom and top capacitors CAP 1  and CAP 2  can be, for example, about one-tenth as large as the bottom and top capacitors BC and TC. 
     In operation, the voltages on the sources of transistors Q 3  and Q 4  are pumped up in the same way as if transistors Q 3  and Q 4  were the bottom and top transistors BT and TT of another stage SG. As noted above, for n stages, the final potential on the source of the bottom transistor BTn of the nth stage switches between the input voltage VIN plus n−1 times the logic high potential; and the input voltage VIN plus n times the logic high potential. Similarly, the final potential on the source of the top transistor TTn of the nth stage switches between the input voltage VIN plus n−1 times the logic high potential; and the input voltage VIN plus n times the logic high potential. 
     Thus, the final potentials on the sources of transistors Q 3  and Q 4  switch between the input voltage VIN plus n times the logic high potential; and the input voltage VIN plus n+1 times the logic high potential. As a result, the highest final potentials on the sources of transistors Q 3  and Q 4  are both one logic high potential greater than the highest final potentials on the sources of the bottom and top transistors BTn and TTn of the last stage SGn. 
     Due to the cross coupling, when the potential on the source of the bottom transistor BTn of the last stage SGn switches to its highest potential, the voltage on the gates of transistors Q 1  and Q 3  also switches to its highest potential. This, in turn, causes the potential on the output node NOUT to rise to the highest potential that is on the source of the bottom transistor BTn of the last stage SGn. 
     Similarly, when the potential on the source of the top transistor TTn of the last stage SGn switches to its highest potential, the voltage on the gates of transistors Q 2  and Q 4  also switches to its highest potential. This, in turn, causes the potential on the output node NOUT to rise to the highest potential that is on the source of the top transistor TTn of the last stage SGn. 
     The voltage on the source of transistor Q 1  has an approximately square waveform that switches between first and second voltages. The first voltage is equal to the input voltage VIN plus n−1 times the logic high potential. The second voltage is equal to the input voltage VIN plus n times the logic high potential. 
     Similarly, the voltage on the source of transistor Q 2  has an approximately square waveform that switches between first and second voltages. The first voltage being equal to the input voltage VIN plus n−1 times the logic high potential. The second voltage being equal to the input voltage VIN plus n times the logic high potential. 
     The voltages on the sources of transistors Q 1  and Q 2  are 180° out-of-phase such that the first voltage on the source of transistor Q 1  and the second voltage on the source of transistor Q 2  are present at the same time. As a result, an approximately constant voltage equal to the input voltage VIN plus n times the logic high potential is present on the output node NOUT. Thus, charge pump  400  eliminates the threshold voltage drop associated with the voltage output from charge pump  300 . 
     FIG. 5 shows a schematic diagram that illustrates a charge pump  500  in accordance with the present invention. Charge pump  500  is similar to charge pump  400  and, as a result, utilizes the same reference numerals to designate the structures that are common to both pumps. 
     As shown in FIG. 5, pump  500  differs from pump  400  in that pump  500  includes a pair of n-channel transistors N 1  and N 2  that are used to enable or disable pump  500 . Transistor N 1  has a drain connected to the gate of transistor Q 2 , a gate connected to receive a control signal CNT, and a source connected to ground. Transistor N 2  has a drain connected to the gate of transistor Q 1 , a gate connected to receive the control signal CNT, and a source connected to ground. In operation, when the control signal CNT is low, the gates of the transistors Q 1 -Q 4  are unaffected by transistors N 1  and N 2 , and thus enabling the pump to operate normally. However, when the control signal CNT is high, the gates of transistors Q 1 -Q 4  are pulled to ground, thereby turning transistors Q 1 -Q 4 , and as a result, the whole pump off. 
     The present invention can also be utilized to pump negative voltages from a supply voltage by exchanging p-channel transistors for the n-channel transistors. FIG. 6 shows a schematic diagram that illustrates a charge pump stage  600  in accordance with the present invention. 
     As shown in FIG. 6, charge pump  600  includes a number of stages NSG 1 -NSGn that are serially connected together to form a chain. The stages NSG 1 -NSGn have a number of bottom transistors NBT 1 -NBTn and a corresponding number of top transistors NTT 1 -NTTn. Each bottom transistor NBT in a stage NSG has a drain, a gate, and a source. Each top transistor NTT in the stage NSG has a source, a gate connected to the drain of the bottom transistor NBT, and a drain connected to the gate of the bottom transistor NBT. 
     The stages NSG 1 -NSGn also have a number of bottom capacitors NBC 1 -NBCn and a corresponding number of top capacitors NTC 1 -NTCn. Each bottom capacitor NBC in a stage NSG is connected between the drain of a bottom transistor NBT and either the first clock signal PH 1  or the second clock signal PH 2 . The first clock signal PH 1  is utilized when the stage NSG is an odd-numbered stage, while the second clock signal PH 2  is utilized when the stage NSG is an even-numbered stage. In addition, each top capacitor NTC in a stage NSG is connected between the source of the top transistor NTT and either the first clock signal PH 1  or the second clock signal PH 2 . The first clock signal PH 1  is utilized when the stage NSG is an even-numbered stage, while the second clock signal PH 2  is utilized when the stage NSG is an odd-numbered stage. 
     The second clock signal PH 2  is out-of-phase and non-overlapping with the first clock signal PH 1 . In addition, both clock signals PH 1  and PH 2  alternate between a logic high voltage level such as the power supply voltage VCC, and a logic low voltage level such as ground (the logic low level can also be negative). 
     Stages NSG 1 -NSGn are connected together so that, with the exception of the last stage NSGn, the drains of the bottom and top transistors NBT and NTT in each stage NSG are connected to the sources of the bottom and top transistors NBT and NTT, respectively, in an adjacent stage NSG. In addition, the sources of both the bottom and top transistors NBT 1  and NTT 1  in the first stage NSG 1  are connected to receive the input voltage VIN (such as the power supply voltage VCC). Further, the drains of the bottom and top transistors NBTn and NTTn in the last stage NSGn output a pumped bottom voltage NPBV, and a pumped top voltage NPTV, respectively. 
     The operation of charge pump  600  is illustrated with a two-stage charge pump. When the clock signal PH 1  rises to the logic high voltage level, a logic high potential approximately equal to the logic high voltage level is capacitively coupled to the drain of bottom transistor NBT 1 . Due to the cross coupling, the logic high potential is also coupled to the gate of top transistor NTT 1 . When the clock signal PH 2  falls to the logic low voltage level, a logic low potential approximately equal to the logic low voltage level is capacitively coupled to the drain of top transistor NTT 1 , and to the gate of bottom transistor NBT 1 . 
     In this condition, the gate-to-source voltage of bottom transistor NBT 1  is less (more negative) than the threshold voltage (which is negative) of bottom transistor NBT 1 . As a result, bottom transistor NBT 1  turns on and the voltage on the drain of bottom transistor NBT 1  rises to that of input voltage VIN. The gate-to-source voltage of top transistor NTT 1 , on the other hand, is greater than the threshold voltage of top transistor NTT 1 . As a result, top transistor NTT 1  is turned off and the voltage on its drain resides at the logic low voltage level. 
     When the clock signal PH 2  switches back to the logic high voltage level from the logic low voltage level, the logic high potential is capacitively coupled to the drain of top transistor NTT 1 . Due to the cross coupling, the logic high potential is also coupled to the gate of bottom transistor NBT 1 . When the clock signal PH 1  falls to the logic low voltage level, the logic low potential is capacitively coupled to the drain of bottom transistor NBT 1 . 
     However, since a voltage equal to the value of input voltage VIN is already on the drain of bottom transistor NBT 1 , the capacitively coupled logic low potential reduces the potential on the drain of bottom transistor NBT 1 . The potential is reduced by the difference between the logic low potential and the logic high potential. However, since in most cases, the logic high potential and the input voltage VIN equal the supply voltage VCC, the drain voltage is reduced to zero. 
     Due to the cross coupling, this same zero potential also sits on the gate of top transistor NTT 1 , and thus, passes the input voltage VIN onto the drain of top transistor NTT 1 . Therefore, voltages on the drains of the bottom and top transistors NBT 1  and NTT 1  in stage NSG 1  oscillate between VIN and ground. 
     In stage NSG 2 , when the clock signal PH 1  switches to the logic low voltage level from the logic high level, the logic low potential is capacitively coupled to the drain of top transistor NTT 2 . This decreases the potential on the drain by an amount equal to the difference between the logic high and the logic low voltages. Due to cross coupling, this voltage is coupled to the gate of bottom transistor NBT 2  and, thus, makes the bottom transistor NBT 2  conduct because the gate-to-drain voltage is lower than the threshold voltage of the p-channel transistor NBT 2 . (The source and drain of a MOS transistor are reversible and, in this instance, the drain of bottom transistor NBT 2  functions as a source.) The clock signal PH 2 , meanwhile, is at a logic high level. This gets coupled onto the drain of bottom transistor NBT 2 . As a result, the voltage on this node rises but because of the capacitively coupled low voltage on the gate of transistor NBT 2 , the transistor conducts, and thus, limits the voltage on the drain of transistor NBT 2 . 
     The voltage on the drain of the transistor NBT 2  can reach a maximum value that equals the absolute value of the threshold voltage of the PMOS transistor. This voltage is reached when the capacitively coupled low voltage on the gate of the transistor is assumed to be zero, in which case, the PMOS transistor NBT 2  acts like a diode because of zero voltages on both the drain (acting as a source) and gate. However, when the clock signal PH 2  switches to a logic low level in the next cycle, the logic low potential gets capacitively coupled to the drain of the bottom transistor NBT 2 . This drops the potential on the drain of bottom transistor NBT 2  by an amount equal to the difference between the logic high and the logic low voltages, and makes the voltage reach a negative value as this difference is usually greater than the absolute value of the threshold voltage of the p-channel transistor. 
     Due to cross coupling, the negative voltage on the drain of bottom transistor NBT 2  sits on the gate of top transistor NTT 2 . When the clock signal PH 2  is at a logic low state, the voltage on the drain of top transistor NTT 2  equals zero and this value gets passed on to its drain because of the sufficiently low negative voltage on the gate of top transistor NTT 2 . Meanwhile, the clock signal PH 1  is at a logic high state and when this gets down to logic low state, it pulls down the zero voltage on the drain of top transistor NTT 2  to a value that equals the difference between the logic low and the logic high voltages. 
     By a similar process, the negative voltage on the drain of top transistor NTT 2  causes a zero voltage to be passed to the drain of bottom transistor NBT 2  which, in the next cycle, gets reduced to a negative value that equals the difference between the logic low and the logic high voltages. In most cases, the logic low voltage is the same as the ground voltage and the logic high voltage equals the same value as the input voltage VIN. Thus, as the first clock signal PH 1  switches between the logic high voltage level and the logic low voltage level, the final predischarge potential on the drain of top transistor NTT 2  switches between zero voltage and the negative voltage −VIN. Similarly, as the second clock signal PH 2  switches between the logic high voltage level and the logic low voltage level, the final potential on the drain of bottom transistor NBT 2  switches between zero voltage and the negative voltage −VIN. Thus, in accordance with the present invention, charge pump  600  provides pumped negative voltages that are not affected by the threshold voltages of the pumping transistors. 
     When a stage is added, the adjoining bottom transistors are switched on and off out-of-phase so that when one transistor is on, the adjoining transistors are off. This allows the lowest potential from one stage to become the highest potential of the next stage in the series. Thus, the final predischarge potential on the drain of the bottom transistor NBT in a next stage switches between the lowest potential that is on the drain of the bottom transistor NBT in the previous stage, and this potential minus the difference between the logic high and the logic low potentials. 
     Similarly, the adjoining top transistors are switched on and off out-of-phase so that when one transistor is on, the adjoining transistors are off. This allows the lowest potential from one stage to become the highest potential of the next stage in the series. Thus, the final predischarge potential on the top transistor NTT in a next stage switches between the lowest potential that is on the top transistor NTT in the previous stage, and this potential minus the difference between the logic high and the logic low potentials. 
     For n stages, the final potential on the drain of the bottom transistor of the nth stage switches between the input voltage VIN minus n−1 times the difference between the logic high and the logic low potential; and the input voltage minus n times the difference between the logic high and the logic low potentials. Similarly, the final potential on the drain of the top transistor of the nth stage switches between the input voltage VIN minus n−1 times the difference between the logic high and the logic low potentials, and the input voltage minus n times the difference between the logic high and the logic low potentials. 
     FIG. 7 shows a schematic diagram that illustrates a charge pump  700  in accordance with the present invention. Charge pump  700  is similar to charge pump  600  and, as a result, utilizes the same reference numerals to designate the structures that are common to both pumps. 
     As shown in FIG. 7, pump  700  differs from pump  600  in that pump  700  includes a first p-channel diode-connected transistor PT 1  and a second p-channel diode-connected transistor PT 2  that are connected as transistors DT 1  and DT 2 . In operation, the voltage on the source of transistor PT 1  has an approximately square waveform that switches between first and second voltages. The first voltage is equal to the input voltage VIN minus n−1 times the difference between the logic high and the logic low potentials plus the absolute value of the threshold voltage of transistor PT 1 . The second voltage is equal to the input voltage minus n times the difference between the logic high and the logic low potentials plus the absolute value of the threshold voltage of transistor PT 1 . 
     Similarly, the voltage on the source of transistor PT 2  has an approximately square waveform that switches between first and second voltages. The first voltage is equal to the input voltage VIN minus n−1 times the difference between the logic high and the logic low potentials plus the absolute value of the threshold voltage of transistor PT 2 . The second voltage is equal to the input voltage minus n times the difference between the logic high and the logic low potentials plus the absolute value of the threshold voltage of transistor PT 2 . 
     The voltages on the sources of transistors PT 1  and PT 2  are 180° out-of-phase such that the first voltage on the source of transistor PT 1  and the second voltage on the source of transistor PT 2  are present at the same time. As a result, an approximately constant negative voltage equal to the negative voltage −VIN minus n times the logic low potential plus the absolute value of the threshold voltage of transistor PT 1  (the threshold voltages of transistors PT 1  and PT 2  are assumed to be the same) is present on the output node NOUT. 
     FIG. 8 shows a schematic diagram that illustrates a charge pump  800  in accordance with the present invention. Charge pump  800  is similar to charge pump  600 , as a result, utilizes the same reference numerals to designate the structures that are common to both pumps. 
     As shown in FIG. 8, pump  800  differs from pump  600  in that pump  800  includes a p-channel first transistor Q 1  and a p-channel second transistor Q 2 . First transistor Q 1  has a source connected to the drain of the bottom transistor NBTn in the last stage NSGn, a gate, and a drain connected to an output node NOUT. Second transistor Q 2  has a source connected to the drain of the top transistor NTTn in the last stage NSGn, a gate, and a drain connected to the output node NOUT. 
     Pump  800  also includes a third n-channel transistor Q 3  and a fourth n-channel transistor Q 4 . Third transistor Q 3  has a source connected to the drain of transistor Q 1  and the output node NOUT, a gate connected to the gate of transistor Q 1 , and a drain. Fourth transistor Q 4  has a source connected to the drain of transistor Q 2  and the output node NOUT, a gate connected to the gate of transistor Q 2  and the drain of transistor Q 3 , and a drain connected to the gate of transistor Q 3 . 
     Pump  800  additionally includes a bottom capacitor CAP 1  and a top capacitor CAP 2 . Bottom capacitor CAP 1  is connected between the drain of transistor Q 3  and the clock signal that is the same as the clock signal that is connected to the top capacitor NTCn in the last stage NSGn. Top capacitor CAP 2  is connected between the drain of transistor Q 4  and the clock signal that is the same as the clock signal that is connected to the bottom capacitor NBCn in the last stage NSGn. Bottom and top capacitors CAP 1  and CAP 2  can be, for example, about one-tenth as large as the bottom and top capacitors NBC and NTC. 
     In operation, the voltages on the drains of transistors Q 3  and Q 4  are pumped down in the same way as if transistors Q 3  and Q 4  were the bottom and top transistors NBT and NTT of another stage NSG. Thus, the final potentials on the drains of transistors Q 3  and Q 4  switch between the input voltage VIN minus n−1 times the difference between the logic high and the logic low potentials; and the input voltage VIN minus n times the difference between the logic high and the logic low potentials. As a result, the lowest final potentials on the drains of transistors Q 3  and Q 4  are both lower than the lowest final potentials on the drains of the bottom and top transistors NBT and NTT of the last stage NSGn by the difference between the logic high and the logic low potentials. 
     Due to the cross coupling, when the potential on the drain of the bottom transistor of the last stage NSGn switches to its lowest potential, the voltage on the gates of transistors Q 1  and Q 3  also switches to its lowest potential. This, in turn, causes the potential on the output node NOUT to fall to the lowest potential that is on the drain of the bottom transistor NBTn of the last stage NSGn. 
     Similarly, when the potential on the drain of the top transistor of the last stage NSGn switches to its lowest potential, the voltage on the gates of transistors Q 2  and Q 4  also switches to its lowest potential. This, in turn, causes the potential on the output node NOUT to fall to the lowest potential that is on the drain of the bottom transistor NBTn of the last stage NSGn. 
     The voltage on the drain of transistor Q 1  has an approximately square waveform that switches between first and second voltages. The first voltage is equal to the input voltage VIN minus n−1 times the difference between the logic high and the logic low potentials. The second voltage is equal to the input voltage minus n times the difference between the logic high and the logic low potentials. 
     Similarly, the voltage on the drain of transistor Q 2  has an approximately square waveform that switches between first and second voltages. The first voltage is equal to the input voltage VIN minus n−1 times the difference between the logic high and the logic low potentials. The second voltage is equal to the input voltage minus n times the difference between the logic high and the logic low potentials. 
     The voltages on the drains of transistors Q 1  and Q 2  are 180° out-of-phase such that the first voltage on the drain of transistor Q 1  and the second voltage on the drain of transistor Q 2  are present at the same time. As a result, an approximately constant voltage equal to the input voltage VIN minus n times the difference between the logic high and the logic low potentials is present on the output node NOUT. 
     FIG. 9 shows a schematic diagram that illustrates a charge pump  900  in accordance with the present invention. Charge pump  900  is similar to charge pump  800  and, as a result, utilizes the same reference numerals to designate the structures that are common to both pumps. 
     As shown in FIG. 9, pump  900  differs from pump  800  in that pump  900  includes a pair of p-channel transistors P 1  and P 2  that are used to enable or disable pump  900 . Transistor P 1  has a drain connected to the gate of transistor Q 2 , a gate connected to receive a control signal CNT, and a source connected to a supply voltage VCC. Transistor P 2  has a drain connected to the gate of transistor Q 1 , a gate connected to receive the control signal CNT, and a source connected to the supply voltage VCC. In operation, when the control signal is at a logic high potential, equal to that of the supply voltage VCC, the gates of the transistors Q 1 -Q 4  are unaffected by transistors N 1  and N 2 , and thus, enable the pump to operate normally. However, when the control signal CNT is low, the gates of transistors Q 1 -Q 4  are pulled to the supply voltage VCC, thereby turning transistors Q 1 -Q 4 , and as a result, the whole pump off. 
     It should be understood that various alternatives to the embodiment of the invention described herein may be employed in practicing the invention. Thus, it is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.