Abstract:
A method used in a time domain equalizer is provided. The method comprising the steps of: providing a time domain equalizer comprising; and extracting a real part of an input or a derivative of the input to the time domain equalizer and using the only real part of the input in the time domain equalizer to derive an output of the time domain equalizer.

Description:
CROSS-REFERENCE TO OTHER APPLICATIONS 
       [0001]    The following applications of common assignee and filed on the same day herewith are related to the present application, and are herein incorporated by reference in their entireties: 
         [0002]    U.S. patent application Ser. No. ______ with attorney docket number LSFFT-110. 
         [0003]    U.S. patent application Ser. No. ______ with attorney docket number LSFFT-102. 
         [0004]    U.S. patent application Ser. No. ______ with attorney docket number LSFFT-103. 
         [0005]    U.S. patent application Ser. No. ______ with attorney docket number LSFFT-104. 
         [0006]    U.S. patent application Ser. No. ______ with attorney docket number LSFFT-105. 
         [0007]    U.S. patent application Ser. No. ______ with attorney docket number LSFFT-106. 
     
    
     FIELD OF THE INVENTION  
       [0008]    The present invention relates generally to digital filters, more specifically the present invention relates to calculating the real decision feedback equalizer coefficients for a variable sideband (VSB) receiver. 
       BACKGROUND  
       [0009]    Electronic equipment and supporting software applications typically involve signal processing. For example, home theater, computer graphics, medical imaging and telecommunications all rely on signal-processing technology. Signal processing requires fast math in complex, but repetitive algorithms. Many applications require computations in real-time, i.e., the signal is a continuous function of time, which need be sampled and converted to digital, for numerical processing. A signal processor has to execute algorithms performing discrete computations on the samples as they arrive. The architecture of a digital signal processor (DSP) is optimized to handle such algorithms. The characteristics of a good signal processing engine typically may include fast, flexible arithmetic computation units, unconstrained data flow to and from the computation units, extended precision and dynamic range in the computation units, dual address generators, efficient program sequencing, and ease of programming. 
         [0010]    Therefore, it is desirous to improve upon a time domain equalizer by improving the computing efficiency. 
       SUMMARY OF THE INVENTION  
       [0011]    A method for calculating real decision feedback equalizer coefficients for a time domain equalizer is provided. 
         [0012]    A method for calculating real decision feedback equalizer coefficients for a time domain equalizer in a multi-leveled VSB receiver is provided. 
         [0013]    A method for calculating real decision feedback equalizer coefficients for a time domain equalizer in an 8-VSB receiver is provided. 
         [0014]    A method used in a time domain equalizer is provided. The method comprising the steps of: providing a time domain equalizer comprising; and extracting a real part of an input or a derivative of the input to the time domain equalizer and using the only real part of the input in the time domain equalizer to derive an output of the time domain equalizer. 
     
    
     
       BRIEF DESCRIPTION OF THE FIGURES  
         [0015]    The accompanying figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views and which together with the detailed description below are incorporated in and form part of the specification, serve to further illustrate various embodiments and to explain various principles and advantages all in accordance with the present invention. 
           [0016]      FIG. 1  is an example of a system diagram in accordance with some embodiments of the invention. 
           [0017]      FIG. 2  is an example of an equalizer structure in accordance with some embodiments of the invention. 
           [0018]      FIG. 3  is flowchart in accordance with some embodiments of the invention. 
           [0019]      FIG. 4  is an example of a digital receiver in accordance with some embodiments of the invention. 
       
    
    
       [0020]    Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention. 
       DETAILED DESCRIPTION  
       [0021]    Before describing in detail embodiments that are in accordance with the present invention, it should be observed that the embodiments reside primarily in combinations of method steps and apparatus components related to calculating real decision feedback equalizer coefficients for a time domain equalizer. Accordingly, the apparatus components and method steps have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein. 
         [0022]    In this document, relational terms such as first and second, top and bottom, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by “comprises . . . a” does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element. 
         [0023]    It will be appreciated that embodiments of the invention described herein may be comprised of one or more conventional processors and unique stored program instructions that control the one or more processors to implement, in conjunction with certain non-processor circuits, some, most, or all of the functions of using known sequences within the guard intervals being used for calculating real decision feedback equalizer coefficients for a time domain equalizer. The non-processor circuits may include, but are not limited to, a radio receiver, a radio transmitter, signal drivers, clock circuits, power source circuits, and user input devices. As such, these functions may be interpreted as steps of a method to calculating real decision feedback equalizer coefficients for a time domain equalizer. Alternatively, some or all functions could be implemented by a state machine that has no stored program instructions, or in one or more application specific integrated circuits (ASICs), in which each function or some combinations of certain of the functions are implemented as custom logic. Of course, a combination of the two approaches could be used. Thus, methods and means for these functions have been described herein. Further, it is expected that one of ordinary skill, notwithstanding possibly significant effort and many design choices motivated by, for example, available time, current technology, and economic considerations, when guided by the concepts and principles disclosed herein will be readily capable of generating such software instructions and programs and ICs with minimal experimentation. 
         [0024]    Referring to  FIG. 1 , a system diagram  100  depicting a transmitted signal x being subjected to a Hilbert transform block  102 . Hilbert transform separates a signal into its real part 1 and imaginary part ζ h . Block  102  transforms transmitted signal x to x+jx h  with x h  being the imaginary part. The (x+jx h ), in turn, is subjected to additive white Gaussian noise (AWGN) and a channel condition (h i +jh q ) to be derived to a received signal r which in turn is subjected to a channel estimator  14  to a Channel Estimation Results v. 
         [0025]    As can be appreciated, the received signal can be represented as follows: 
         [0000]        r =( x+jx   h )*( h   i   +jh   q )   Equation 1 
         [0026]    Equation 1 can be derived as follows: 
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         [0027]    Note that the imaginary part of Equation 2 is not represented, and the real part is (h i −ζ h *h q ). 
         [0000]    Channel Estimation Results can be represented as follows:
       v=(x+jx h )*(h i +jh q )*{tilde over (x)}; where {tilde over (x)}=fliplr(x) where fliplr represents flip left to right operation       
 
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         [0029]    So, r=x*real(y); 
         [0030]    It means that transmitted signal can be recovered by using the real part of the channel estimation results. In the present invention system, only the real part of the channel estimation results are advantageously used to calculate the real decision feedback equalizer (DFE) coefficients and only the real part of the received signals are advantageously passed through the equalizer. This advantageously reduces the equalizer complexity.  FIG. 2  shows how the equalizer works. 
         [0031]    As can be appreciated, only the real part of the channel estimation is used to calculate the coefficients of the decision feedback equalizer. Furthermore, real calculation of the matrix inversion and real DFE architecture advantageously reduce the complexity of the equalizer implementation for ASIC. 
         [0032]    Referring to  FIG. 2 , a Non-updated Decision Feedback Equalizer  100  is shown. An equalizer input  102  is both input into a real part extractor  104  and a channel estimation block  106 . In real part extractor  104 , the real portion (versus the imaginary portion) of input  102  is extracted. In channel estimation block  106 , both real and imaginary portions of the channel estimation block  106  are subjected to channel estimation. The estimated information is fed into real part extractor  108 , the real portion (versus the imaginary portion) of input estimated information is extracted. In turn, the real portion of the estimated information is input into a matrix inversion block  110 , wherein a matrix denoting the real portion of the estimated information is inverted. 
         [0033]    Matrix inversion block  110  generates two adjustment paths, a first path  112  and a second path  114 . First path  112  adjusts a feed forward equalizer block (FFE)  116 , which receives the real portion of the equalizer input  102  extracted by block  104 . Second path  114  adjusts a feedback equalizer block (FBE)  118 , which also receives sliced information from a slicer  124 . The outputs of both FFE and  116  and FBE  118  are input into an adder  120 . The added inputs are the equalizer output  122 . Output  122  is further subjected to slicer  124  and supplied to FBE  118 . 
         [0034]    As can be seen, the coefficients of the decision feedback equalizer  100  for a VSB receiver such as an 8-VSB receiver could be directly calculated through the real part of the channel estimation. The coefficients can be the optimum solution for the data at exactly that moment. However, if the equalizer input data are noisy in that data at the input of the equalizer have low signal to noise ratio i.e. noise-to-data ratio is deemed high, it is still very difficult to generate good equalizer output data  122  before the Slicer  124 . If this is the case, the Slicer  124  will make wrong decisions and the FBE output  118  will not be able to cancel the inter-symbol interferences caused by the post cursor [of the channel impulse response. Post cursor is the multipath path bins after the main path. 
         [0035]    As a result, more noise in equalizer output  122  is generated. The system will go into positive feedback and eventually diverge. 
         [0036]    Referring to  FIG. 3 , flow chart  300  depicting the recovery process of a transmitted signal is shown. Extract the real part of an equalizer input (Step  302 ). Extract the real part of an estimated equalizer input (Step  304 ). Provide a real DFE with real coefficients (Step  306 ). Use the output of the DFE or the real part of the channel estimation results (Step  308 ). 
         [0037]    Referring to  FIG. 4 , a block diagram of a conventional digital television receiver  400 , which can process a VSB signal, is shown. The receiver may be a multi-level variable side band (VSB) receiver. The digital television receiver  400  includes a tuner  410 , a demodulator  420 , an equalizer  430 , and a TC M (Trellis-coded Modulation) decoder  440 . TCM coding may use an error correction technique, which may improve system robustness against thermal noise. TCM decoding may have more robust performance ability and/or a simpler decoding algorithm. The output signal OUT of the TCM decoder  440  may be processed by a signal processor and output as multimedia signals (e.g., display signals and/or audio signals). The present invention is suitable for application in the equalizer  430 . However, the present invention is not limited in its use in receiver  400 . Other suitable applications are contemplated by the present invention as well. 
         [0038]    The decision feedback equalizer (DFE) of the present invention may be a non-updated DFE. The nature of non-updated DFE determines that the training process is necessary. 
         [0039]    In the foregoing specification, specific embodiments of the present invention have been described. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. The invention is defined solely by the appended claims including any amendments made during the pendency of this application and all equivalents of those claims as issued. 
         [0040]    Terms and phrases used in this document, and variations thereof, unless otherwise expressly stated, should be construed as open ended as opposed to limiting. As examples of the foregoing: the term “including” should be read as mean “including, without limitation” or the like; the term “example” is used to provide exemplary instances of the item in discussion, not an exhaustive or limiting list thereof; and adjectives such as “conventional,” “traditional,” “normal,” “standard,” and terms of similar meaning should not be construed as limiting the item described to a given time period or to an item available as of a given time, but instead should be read to encompass conventional, traditional, normal, or standard technologies that may be available now or at any time in the future. Likewise, a group of items linked with the conjunction “and” should not be read as requiring that each and every one of those items be present in the grouping, but rather should be read as “and/or” unless expressly stated otherwise. Similarly, a group of items linked with the conjunction “or” should not be read as requiring mutual exclusivity among that group, but rather should also be read as “and/or” unless expressly stated otherwise.