Abstract:
A method of operating a nonvolatile memory device comprising a plurality of memory blocks comprises storing first data and second data to be stored in a hot memory block of the memory blocks in a first buffer, transferring the first data stored in the first buffer to a second buffer to program the first data in the hot memory block, and generating RAID parity data based on the first and second data, wherein the RAID parity data and the first data form part of the same write stripe.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2012-0080206 filed Jul. 23, 2012, the subject matter of which is hereby incorporated by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    The inventive concept relates generally to electronic data storage technologies. More particularly, certain embodiments of the inventive concept relate to nonvolatile memory devices and related data management methods. 
         [0003]    Semiconductor memory devices can be roughly divided into two categories according to whether they retain stored data when disconnected from power. These categories include volatile memory devices, which lose stored data when disconnected from power, and nonvolatile memory device, which retain stored data when disconnected from power. Examples of volatile memory devices include DRAM and SRAM, and examples of nonvolatile memory devices include EEPROM, FRAM, PRAM, MRAM, and flash memory. 
         [0004]    Among nonvolatile memories, flash memory has gained popularity in recent years due to attractive features such as relatively high performance and data storage capacity, efficient power consumption, and an ability to withstand mechanical shock. Flash memory can currently be found in a wide variety of electronic devices, ranging from cellular phones, PDAs, digital cameras, laptops, and many others. 
         [0005]    Flash memory also suffers from certain drawbacks, such as potential failures due to limited program/erase endurance or various electrical malfunctions, for example. Consequently, nonvolatile memory devices also commonly use techniques such as bad block management, wear leveling, metadata mirroring, in an effort to minimize these various sources of failures. Unfortunately, many conventional techniques fail to adequately prevent certain types of errors that may be generated more readily in specific memory blocks or certain types of errors that arise after prolonged use of a data storage device. 
       SUMMARY OF THE INVENTION 
       [0006]    In one embodiment of the inventive concept, a nonvolatile memory device comprises a nonvolatile memory comprising a plurality of memory blocks, and a controller configured to control the nonvolatile memory. The controller identifies at least one of the memory blocks as a hot memory block and generates at least first and second RAID parity data based on first data corresponding to a first hot page of the hot memory block, wherein the first data and the first RAID parity data form part of a first write stripe, and the second RAID parity data forms part of a second write stripe different from the first write stripe. 
         [0007]    In another embodiment of the inventive concept, a data management method for a nonvolatile memory device comprising a plurality of memory blocks comprises storing first data and second data to be stored in a hot memory block of the memory blocks in a first buffer, transferring the first data stored in the first buffer to a second buffer to program the first data in the hot memory block, and generating RAID parity data based on the first and second data, wherein the RAID parity data and the first data form part of the same write stripe. 
         [0008]    In another embodiment of the inventive concept, a nonvolatile memory device comprises a nonvolatile memory comprising a plurality of memory cells arranged in a three-dimensional structure, and a controller configured to control the nonvolatile memory. The controller identifies memory cells adjacent to a common source line as a plurality of hot pages, wherein each of the hot pages is used to generate at least two different units of RAID parity data. 
         [0009]    These and other embodiments of the inventive concept can potentially improve the reliability of nonvolatile memory devices by expanding the conditions under which data recovery can be achieved. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The drawings illustrate selected embodiments of the inventive concept. In the drawings, like reference numbers indicate like features. 
           [0011]      FIG. 1  is a block diagram illustrating a memory system according to an embodiment of the inventive concept. 
           [0012]      FIG. 2  is a block diagram illustrating an example of a controller shown in  FIG. 1 . 
           [0013]      FIG. 3  is a block diagram illustrating a storage device in  FIG. 1  according to an embodiment of the inventive concept. 
           [0014]      FIG. 4  is a diagram illustrating an example of a nonvolatile memory in  FIG. 3 . 
           [0015]      FIG. 5  is a diagram illustrating a method of managing data using a RAID technique. 
           [0016]      FIG. 6A ,  6 B,  6 C and  6 D are diagrams illustrating a method of generating RAID parity data according to an embodiment of the inventive concept. 
           [0017]      FIG. 7  is a diagram illustrating a method of recovering data according to an embodiment of the inventive concept. 
           [0018]      FIG. 8  is a diagram illustrating a method of recovering data according to another embodiment of the inventive concept. 
           [0019]      FIG. 9  is a diagram illustrating a method of recovering data according to still another embodiment of the inventive concept. 
           [0020]      FIG. 10  is a flow chart illustrating a data managing method according to an embodiment of the inventive concept. 
           [0021]      FIG. 11  is a block diagram illustrating a flash memory according to an embodiment of the inventive concept. 
           [0022]      FIG. 12  is a perspective view illustrating a 3D structure of a memory block illustrated in  FIG. 11 . 
           [0023]      FIG. 13  is a circuit diagram illustrating an equivalent circuit of a memory block illustrated in  FIG. 12 . 
           [0024]      FIG. 14  is a block diagram illustrating a memory card system comprising a nonvolatile memory according to an embodiment of the inventive concept. 
           [0025]      FIG. 15  is a block diagram illustrating a solid state drive system comprising a nonvolatile memory according to an embodiment of the inventive concept. 
           [0026]      FIG. 16  is a block diagram illustrating an SSD controller in  FIG. 15 . 
           [0027]      FIG. 17  is a block diagram illustrating an electronic device comprising a flash memory system according to an embodiment of the inventive concept. 
       
    
    
     DETAILED DESCRIPTION 
       [0028]    Embodiments of the inventive concept are described below with reference to the accompanying drawings. These embodiments are presented as teaching examples and should not be construed to limit the scope of the inventive concept. 
         [0029]    In the description that follows, the terms “first”, “second”, “third”, etc., may be used to describe various elements, components, regions, layers and/or sections, but these elements, components, regions, layers and/or sections should not be limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept. 
         [0030]    Spatially relative terms, such as “beneath”, “below”, “lower”, “under”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. 
         [0031]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, indicate the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Also, the term “exemplary” is intended to refer to an example or illustration. 
         [0032]    Where an element or layer is referred to as being “on”, “connected to”, “coupled to”, or “adjacent to” another element or layer, it can be directly on, connected, coupled, or adjacent to the other element or layer, or intervening elements or layers may be present. In contrast, where an element is referred to as being “directly on,” “directly connected to”, “directly coupled to”, or “immediately adjacent to” another element or layer, there are no intervening elements or layers present. 
         [0033]    Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
         [0034]      FIG. 1  is a block diagram illustrating a memory system  100  according to an embodiment of the inventive concept. Memory system  100  is designed to prevent data loss using a RAID technique. In particular, memory system  100  may prevent loss of data stored in a hot page by using data to be stored in the hot page to generate multiple units of RAID parity data. 
         [0035]    Referring to  FIG. 1 , memory system  100  comprises a storage device  110  and a controller  120 . Storage device  110  can be used to store a variety of data such as a text, a graphic, a software code, and so on. Storage device  100  can be implemented by a nonvolatile memory or a plurality of nonvolatile memories. Storage device  110  can be implemented by a nonvolatile memory such as an Electrically Erasable Programmable Read-Only Memory (EEPROM), a flash memory, a Magnetic RAM (MRAM), a Spin-Transfer Torque MRAM (STT-MRAM), a Conductive bridging RAM (CBRAM), a Ferroelectric RAM (FeRAM), Ovonic Unified Memory (OUM), a Phase change RAM (PRAM), a Resistive RAM (RRAM or ReRAM), a Nanotube RRAM, a Polymer RAM (PoRAM), a Nano Floating Gate Memory (NFGM), a holographic memory, a Molecular Electronics Memory, or an Insulator Resistance Change Memory. For ease of description, it will be assumed that storage device  110  is implemented by a flash memory. 
         [0036]    A nonvolatile memory used for storage device  110  comprises a plurality of memory blocks. A predetermined memory block of the memory blocks may be determined to be a hot memory block. In general, the term “hot memory block” will refer to a memory block that is frequency erased (or alternatively, programmed, for instance), and the term “hot page” may refer to pages of a hot memory block. For example, where a memory block is erased more than other memory blocks, it may be determined to be a hot memory block. Memory cells of the hot memory block may be physically deteriorated more than memory cells of the other memory blocks. The probability of read failure on data stored in the hot memory block may be higher than that on data stored in the other memory blocks. Memory system  100  comprises a RAID unit  130  to protect the reliability of data stored in the hot memory block. 
         [0037]    Controller  120  stores data input from an external device in storage device  110  and transfers data read out from storage device  110  to the external device. In particular, controller  120  may manage data using the RAID scheme to protect the reliability of data stored in the hot memory block. 
         [0038]    RAID unit  130  stores data in storage device  110  using the RAID technique at a program operation. Also, in a read operation, RAID unit  130  recovers data at which a read error is generated, using the RAID technique. RAID unit  130  controls a program operation such that data corresponding to a hot page is used to generate two different units of RAID parity data. The probability that read failure occurs in a read operation on data stored in the hot page may become high due to deterioration of a physical characteristic of the hot page. 
         [0039]    Memory system  100  manages data corresponding to a hot page to be used to generate two different units of RAID parity data. Where read failure on data stored in the hot page is generated, the read failed data may be recovered using the two different units of RAID parity data. Thus, it is possible to protect the reliability of data stored in the hot page. 
         [0040]    Where a read failure occurs with respect to at least two units of data in a stripe, the data causing the failure may not be recovered by a typical RAID technique. However, memory system  100  may recover at least two units of read failed data by generating two different units of RAID parity data using data corresponding to a hot page. 
         [0041]      FIG. 2  is a block diagram illustrating an example of controller  120  of  FIG. 1 . 
         [0042]    Referring to  FIG. 2 , controller  120  comprises a processor  121 , a ROM  122 , a buffer controller  123 , a buffer memory  124 , a RAID controller  125 , a RAID buffer  126 , a host interface  127 , and a nonvolatile memory interface (hereinafter, referred to as an NVM interface)  128 . Collectively, RAID controller  125  and RAID buffer  126  constitute a RAID unit  130  in  FIG. 1 . 
         [0043]    Processor  121  controls overall operations of controller  120 . For example, processor  121  may be configured to operate firmwire such as a flash translation layer (FTL) stored in ROM  122 . For example, processor  121  may be configured to manage wear leveling and bad blocks of storage device  120  using the FTL. 
         [0044]    Buffer controller  123  controls buffer memory  124  under control of processor  121 . Buffer memory  124  temporarily stores data to be stored in storage device  110  or data read out from storage device  110 . 
         [0045]    RAID controller  125  controls RAID buffer  126  under control of processor  121 . RAID buffer  126  may be used as a working memory to generate RAID parity data. RAID controller  125  generates RAID parity data according to a RAID technique to prevent loss of data to be stored in a hot memory block. If the RAID parity data is generated, RAID controller  125  may store the RAID parity data in a predetermined area of storage device  110 . 
         [0046]    In some embodiments, RAID controller  125  generates two different units of RAID parity data using data corresponding to a hot page. This may mean that RAID controller  125  uses data to be stored in two different hot pages to generate RAID parity data. For example, to generate RAID parity data, RAID controller  125  may perform an XOR operation on data constituting the same parity stripe. RAID controller  125  may temporarily store a result of the XOR operation in RAID buffer  126 . 
         [0047]    Afterwards, RAID controller  125  generates RAID parity data by performing an XOR operation on data stored in RAID buffer  126  and data of a hot page constituting another parity stripe. After the RAID parity data is generated, RAID controller  125  may store the RAID parity data in storage device  110  and reset RAID buffer  126 . Host interface  127  is used to interface with a host, and NVM interface  128  is used to interface with storage device  110 . 
         [0048]      FIG. 3  is a block diagram illustrating an example of storage device  110  in  FIG. 1  according to an embodiment of the inventive concept. As described in relation to  FIG. 1 , storage device  110  in  FIG. 1  may be implemented by a nonvolatile memory or by a plurality of nonvolatile memories.  FIG. 3  shows an example where storage device  110  is formed of a plurality of nonvolatile memories. 
         [0049]    Referring to  FIG. 3 , storage device  110  comprises a plurality of nonvolatile memories NVM 11  to NVM 88 . Storage device  110  is connected with an NVM interface  128  through a plurality of channels CH 1  to CH 8 . Nonvolatile memories sharing the same channel may receive data from NVM interface  128  through the same channel and transfer read data to NVM interface  128  through the same channel. 
         [0050]    For example, nonvolatile memories NVM 11  to NVM 18  sharing a first channel CH 1  may receive data from NVM interface  128  through first channel CH 1  and transfer read data to NVM interface  128  through first channel CH 1 . Nonvolatile memories sharing the same channel may perform a program operation, a read operation, and an erase operation independently. 
         [0051]    Data transfer (or, transmitting/receiving) operations of nonvolatile memories sharing a channel may be performed in parallel with data transfer (or, transmitting/receiving) operations of nonvolatile memories sharing another channel. For example, the nonvolatile memories NVM 11  to NVM 18  sharing first channel CH 1  may perform data transfer (or, transmitting/receiving) operations through first channel CH 1 , and nonvolatile memories NVM 21  to NVM 28  sharing a second channel CH 2  may perform data transfer (or, transmitting/receiving) operations through second channel CH 2 . In this case, the data transfer (or, transmitting/receiving) operations using first channel CH 1  and the data transfer (or, transmitting/receiving) operations using second channel CH 2  may be performed in parallel with each other. 
         [0052]    Although  FIG. 3  shows an example where nonvolatile memories NVM 11  to NVM 88  are arranged in a matrix of eight channels CH 1  to CH 8  and eight ways Way 1  to Way 8 , the inventive concept is not limited to this example, and the number of channels and the number of ways can be variously changed. 
         [0053]      FIG. 4  is a diagram illustrating an example of nonvolatile memory NVM 11  of  FIG. 2 . Nonvolatile memory NVM 11  is placed in a first channel CH 1  and a first way Way 1 . For ease of description, it is assumed that nonvolatile memory NVM 11  is a flash memory. 
         [0054]    Referring to  FIG. 4 , nonvolatile memory NVM 11  comprises a plurality of memory blocks each comprising a plurality of pages. In the flash memory, a program unit may be different from an erase unit due the flash memory&#39;s lack of support for an overwrite operation. For example, a program operation may be performed by a page unit while an erase operation may be performed a memory block unit. 
         [0055]    A specific memory block may be frequently erased as compared with other memory blocks. For example, where data stored in a specific memory block is frequently updated, data stored in the specific memory block may be invalidated more frequently than data stored in another memory block. In this case, the specific memory block may be erased more frequently than another memory block. 
         [0056]    Because memory cells of a memory block frequently erased may become more deteriorated than memory cells of another memory block, the reliability of the memory block frequently erased may be lowered compared with another memory block. The probability of read failure on data stored in a memory block frequently erased may become higher than that of another memory block. 
         [0057]    As illustrated in  FIG. 4 , where the number of erase operations of a first memory block BLK 1  is greater than that of another memory block, first memory block BLK 1  may be determined to be a hot memory block. In some embodiments, processor  121  (refer to  FIG. 2 ) of controller  120  (refer to  FIG. 2 ) counts an erase number of each memory block to determine a memory block having the largest erase number as a hot memory block. 
         [0058]    Where read failure on a hot page of hot pages of the hot memory block is generated, data stored in the read failed hot page must be recovered. In general, read failed data may be recovered using ECC. However, an error may not be recovered when an error exceeds ECC coverage, when data associated with a file system is erroneous, when data associated with FTL mapping information is erroneous, and so one. 
         [0059]    Memory system  100  uses a RAID technique to prevent loss of data stored in a hot memory block. In particular, memory system  100  may prevent loss of data stored in a hot page by generating a plurality of RAID parity data using data corresponding to a hot page. 
         [0060]      FIG. 5  is a diagram illustrating a method of managing data using a RAID technique.  FIGS. 6A and 6B  are diagrams illustrating a method of generating RAID parity data according to an embodiment of the inventive concept.  FIG. 7  is a diagram illustrating a method of recovering data according to an embodiment of the inventive concept. As will be described in relation to  FIGS. 5 through 7 , it is possible to improve the reliability of data stored in a hot page by generating a plurality of RAID parity data using data corresponding to the hot page. 
         [0061]      FIG. 5  is a diagram illustrating a method in which normal parity data is generated using a typical RAID technique. For ease of description, it is assumed that a stripe is formed of four units of user data and one unit of RAID parity data. Also, it is assumed that a stripe of data is stored in first pages Page  11 , Page 12 , Page 13 , Page 14 , and Page 15  of first to fifth blocks BLK 1  to BLK 5  (refer to  FIG. 4 ), respectively. 
         [0062]    Referring to  FIG. 5 , first user data DT 1  stored in a buffer memory  124  is programmed in page Page  11  of first block BLK 1  of nonvolatile memory NVM 11 , and first user data DT 1  is transferred to a RAID buffer  126 . 
         [0063]    Then, second user data DT 2  stored in buffer memory  124  is programmed in page Page 12  of second block BLK 2  of nonvolatile memory NVM 11 . An XOR operation is performed with respect to second user data DT 2  and first user data DT 1 , and a result of the XOR operation is stored in RAID buffer  126 . 
         [0064]    Third user data DT 3  and fourth user data DT 4  are stored in page Page 13  of third block BLK 3  and page Page 14  of fourth block BLK 4 , respectively. A result of an XOR operation on first to fourth user data DT 1  to DT 4  is stored in RAID buffer  126 . A result of the XOR operation on first to fourth user data DT 1  to DT 4  may be normal parity data. Afterwards, a value (i.e., the normal parity data) stored in RAID buffer  126  is stored in page Page 15  of fifth block BLK 5 . 
         [0065]    In the above technique, if read failure occurs with respect to one unit of data in a stripe, the read failed data may be recovered by the RAID technique. On the other hand, if read failure occurs with respect to two units of data in a stripe, the read failed data may not be recovered by the RAID technique. As an example, as illustrated in  FIG. 5 , if first user data DT 1  is stored in a hot page, the probability that read failure on two or more data including first user data DT 1  is generated may be high. As described above, it is impossible to recover two data read failed. 
         [0066]      FIGS. 6A to 6D  are diagrams illustrating a method of generating RAID parity data according to an embodiment of the inventive concept. In this method, RAID parity data is generated using data corresponding to two different hot pages. Also, data corresponding to one hot page is used to generate two different units of RAID parity data. In contrast to the example of  FIG. 5 , even where a read failure occurs at two units of data in a stripe, read failed data may be recovered. 
         [0067]    For ease of description, in  FIGS. 6A to 6D , it is assumed that a first parity stripe is formed of first to fourth user data DT 1  to DT 4  and first RAID parity data Parity  1 . Also, it is assumed that the first to fourth user data DT 1  to DT 4  and first RAID parity data Parity  1  are programmed in pages Page  11  to Page 15  in  FIG. 4 , respectively. It is further assumed that a second parity stripe is formed of fifth to eighth user data DT 5  to DT 8  and second RAID parity data Parity  2 . Also, it is assumed that the fifth to eighth user data DT 5  to DT 8  and second RAID parity data Parity  2  are programmed in pages Page 21  to Page 25  in  FIG. 4 , respectively. 
         [0068]    As illustrated in  FIG. 4 , it is assumed that first block BLK 1  is a hot memory block and all pages Page  11  to Page 81  in first block BLK 1  are hot pages. Also, it is assumed that first user data DT 1  and second user data DT 2  are stored in a first hot page Page  11  and a second hot page Page 21 , respectively. 
         [0069]    Referring to  FIG. 6A , first user data DT 1  stored in buffer memory  124  is programmed in page Page  11  of nonvolatile memory NVM 11 . At this time, buffer controller  123  (refer to  FIG. 2 ) sends first user data DT 1  to RAID controller  125  (refer to  FIG. 2 ), and RAID controller  125  temporarily stores first user data DT 1  in a RAID buffer  126 . 
         [0070]    Then, the second user data DT 2  stored in buffer memory  124  is programmed in page Page 12  of nonvolatile memory NVM 11 . At this time, buffer controller  123  transfers second user data DT 2  to RAID controller  125 , and RAID controller  125  performs an XOR operation on first user data DT 1  and second user data DT 2 . RAID controller  125  stores a result of the XOR operation in RAID buffer  126 . 
         [0071]    Third user data DT 3  and fourth user data DT 4  are stored in page Page 13  of third block BLK 3  and page Page 14  of fourth block BLK 4 , respectively. A result of an XOR operation on first to fourth user data DT 1  to DT 4  is stored in RAID buffer  126 . 
         [0072]    Referring to  FIG. 6B , RAID controller  125  performs an XOR operation on a result of the XOR operation on first to fourth user data DT 1  to DT 4  and fifth user data DT 5 , and it stores a result of the XOR operation in RAID buffer  126 . That is, RAID controller  125  may perform an XOR operation on first to fifth user data DT 1  to DT 5  and store a result of the XOR operation in RAID buffer  126 . The result of the XOR operation on first to fifth user data DT 1  to DT 5  may be referred to as first RAID parity data Parity  1 , and first RAID parity data Parity  1  may be stored in page Page 15  of the nonvolatile memory NVM 11 . 
         [0073]    Below, an operation of generating second RAID parity data Parity  2  is described with reference to  FIGS. 6C and 6D . 
         [0074]    Referring to  FIG. 6C , fifth to eighth user data DT 5  to DT 8  stored in buffer memory  124  is sequentially stored in pages Page 21  to Page 25 , respectively. RAID controller  125  sequentially performs an XOR operation on fifth to eighth user data DT 5  to DT 8 . A result of the XOR operation on fifth to eighth user data DT 5  to DT 8  is stored in RAID buffer  126 . 
         [0075]    Referring to  FIG. 6D , RAID controller  125  performs an XOR operation on the result of the XOR operation on fifth to eighth user data DT 5  to DT 8  and first user data DT 1  to store a result of the XOR operation in RAID buffer  126 . Herein, the result of the XOR operation on fifth to eighth user data DT 5  to DT 8  and first user data DT 1  is referred to as second RAID parity data Parity  2 , and the second RAID parity data is stored in page Page 25  of nonvolatile memory NVM 11 . 
         [0076]    In the above described example, first RAID parity data Parity  1  may be a first parity stripe and second RAID parity data Parity  2  may be a second parity stripe. First RAID parity data Parity  1  may be generated using first user data DT 1  of the first parity stripe and the fifth user data DT 5  of the second parity stripe. That is, first RAID parity data Parity  1  may be generated using data to be stored in two hot pages in different parity stripes. 
         [0077]    Second RAID parity data Parity  2  is generated using first user data DT 1  of the first parity stripe and fifth user data DT 5  of the second parity stripe. That is, second RAID parity data Parity  2  is generated using data to be stored in two hot pages in different parity stripes. 
         [0078]    First user data DT 1  corresponding to first hot page Page 11  is used to generate first and second RAID parity data Parity  1  and Parity  2 . Likewise, fifth user data DT 5  corresponding to second hot page Page 21  is used to generate first and second RAID parity data Parity  1  and Parity  2 . 
         [0079]      FIG. 7  is a diagram illustrating an operation in which read failed data is recovered. The operation of  FIG. 7  recovers read failed data when two user data of data in a parity stripe are read failed. For ease of description, it is assumed that first RAID parity data Parity  1  and second RAID parity data Parity  2  are generated according a manner described with reference to  FIGS. 6A to 6D . Also, it is assumed that read failure occurs in first and fourth user data DT 1  and DT 4  of a first parity stripe. In the RAID technique described with reference to  FIG. 5 , if read failure occurs with respect to two units of data in a stripe, read failed data may not be recovered. In the example of  FIG. 7 , however, because one hot page is used to generate different RAID parity data, read failed data may be recovered. 
         [0080]    Referring to  FIG. 7 , first user data DT 1  is recovered to recover first user data DT 1  and fourth user data DT 4 . Because first user data DT 1  is used to generate both the first RAID parity data Parity  1  and second RAID parity data Parity  2 , it may be recovered using second RAID parity data Parity  2 . 
         [0081]    First, as illustrated in  FIG. 7 , first user data DT 1  is recovered using second RAID parity data Parity  2 . Thereafter, a recover operation is performed for fourth user data DT 4 . Because first user data DT 1  is recovered, fourth user data DT 4  may be recovered using first RAID parity data Parity  1 . That is, as illustrated in  FIG. 7 , fourth user data DT 4  may be recovered using first user data DT 1  recovered and first RAID parity data Parity  1 . 
         [0082]    The inventive concept is not limited to examples described in  FIGS. 6 and 7 . For example, in  FIGS. 6 and 7 , a parity stripe was assumed to be formed of four units of user data and one unit of RAID parity data. However, a parity stripe may be variously changed. Also, in  FIGS. 6 and 7 , user data of one parity stripe was assumed to be stored in the same nonvolatile memory. However, the inventive concept is not limited thereto. For example, user data of a parity stripe may be different nonvolatile memories (refer to  FIG. 3 ). 
         [0083]    In  FIGS. 6 and 7 , there was described an example in which two RAID parity data is generated and read failed data is recovered using two RAID parity data. However, the inventive concept is not limited thereto. For example, three or more RAID parity data may be generated, and read failed data is recovered using the three or more RAID parity data. This will be described with reference to  FIGS. 8 and 9 . 
         [0084]      FIG. 8  is a diagram illustrating another embodiment of the inventive concept. In  FIG. 8 , there is illustrated an example in which read failed data is recovered when read failure occurs in user data respectively corresponding to two hot pages. For ease of description, it is assumed that first to third RAID parity data is generated. Also, it is assumed that first to fourth user data DT 1  to DT 4  is stored in pages Page  11  to Page 14  of a nonvolatile memory NVM 11  (refer to  FIG. 4 ), fifth to eighth user data DT 5  to DT 8  is stored in pages Page 21  to Page 24  of nonvolatile memory NVM 11 , and ninth to twelfth user data DT 9  to DT 12  is stored in pages Page 13  to Page 34  of nonvolatile NVM 11 . 
         [0085]    Referring to  FIG. 8 , first RAID parity data Parity  1  is generated by XORing first to fifth user data DT 1  to DT 5 . That is, first RAID parity data Parity  1  may be generated using first user data DT 1  corresponding to a first hot page Page  11  and fifth user data DT 5  corresponding to a second hot page Page 21 . In this case, fifth user data DT 5  may belong to a second parity stripe and be used to generate second RAID parity data Parity  2 . 
         [0086]    Second RAID parity data Parity  2  is generated by XORing the fifth to ninth user data DT 5  to DT 9 . That is, second RAID parity data Parity  2  may be generated using fifth user data DT 5  corresponding to second hot page Page 21  and ninth user data DT 9  corresponding to a third hot page Page 31 . In this case, ninth user data DT 9  may belong to a third parity stripe and be used to generate third RAID parity data Parity  3 . 
         [0087]    Third RAID parity data Parity  3  may be generated by XORing ninth to twelfth user data DT 9  to DT 12 . That is, third RAID parity data Parity  3  may be generated using ninth user data DT 9  corresponding to third hot page Page 31  and first user data DT 1  corresponding to first hot page Page 11 . In this case, first user data DT 1  may belong to the first parity stripe and be used to generate the first RAID parity data Parity  1 . 
         [0088]    As illustrated in  FIG. 8 , each of first to third RAID parity data Parity  1  to Parity  3  may be generated using data of two different hot pages. Also, data corresponding to one page may be used to generate two different units of RAID parity data. Because user data corresponding to a hot page is used to generate two different units of RAID parity data, it may be maintained until RAID parity data corresponding to the user data is generated. For example, because first user data DT 1  is used to generate first and third RAID parity data Parity  1  and Parity  3 , it may be maintained in a buffer memory  124  (refer to  FIG. 2 ) until third RAID parity data Parity  3  is generated. 
         [0089]    As indicated by the foregoing, although a read failure occurs for user data corresponding to two hot pages, memory system  100  may recover read failed user data corresponding to two hot pages. For example, it is assumed that first user data DT 1  and fifth user data DT 5  are read failed. In this case, because first user data DT 1  is used to generate third RAID parity data Parity  3 , it may be recovered using the third RAID parity data. Parity  3 . Also, because fifth user data DT 5  is used to generate first RAID parity data Parity  1 , it may be recovered using first RAID parity data Parity  1  and first user data DT 1 . As a result, although a read failure occurs for user data corresponding to two hot pages, memory system  100  according to an embodiment of the inventive concept may successfully recover read failed user data corresponding to two hot pages. 
         [0090]      FIG. 9  is a diagram illustrating still another embodiment of the inventive concept. In  FIG. 9 , there is illustrated an example in which read failed data is recovered when read failure occurs in user data corresponding to all hot pages. 
         [0091]    For ease of description, it is assumed that first to third RAID parity data Parity  1  to Parity  3  is generated. Also, it is assumed that read failure occurs in user data corresponding to all hot pages. For example, it is assumed that read failure occurs in first, fifth, and ninth user data DT 1 , DT 5 , and DT 9 . Any one of first, fifth, and ninth user data DT 1 , DT 5 , and DT 9  may be stored to recover first, fifth, and ninth user data DT 1 , DT 5 , and DT 9 . To cope with a case in which all hot pages are read failed, memory system  100  may store one of a plurality of hot pages in one of a plurality of nonvolatile memories (refer to  FIG. 3 ). For example, where ninth user data DT 9  is stored in a nonvolatile memory, memory system  100  may recover first and fifth user data DT 1  and DT 5  as illustrated in  FIG. 9 . First and fifth user data DT 1  and DT 5  may be recovered the same as that described in  FIG. 8 , and a description thereof is thus omitted. 
         [0092]      FIG. 10  is a flow chart illustrating a data managing method according to an embodiment of the inventive concept. 
         [0093]    Referring to  FIG. 10 , in operation S  110 , controller  120  receives a program command and data from a host. The received data is temporarily stored in a buffer memory  124 . Thereafter, in operation S 120 , controller  120  determines whether to perform the RAID scheme described above in accordance with various embodiments of the inventive concept. For example, if a logical address (or, a physical address) corresponding to data to be programmed corresponds to a hot memory block, the RAID scheme may be applied. If the RAID scheme is determined not to be needed, in operation S  130 , controller  120  may perform a normal program operation. Otherwise, if the RAID scheme according is determined to be needed, controller  120  may perform the following data managing operation using the RAID scheme according to an embodiment of the inventive concept. 
         [0094]    In operation S  140 , data may be written in storage device  110  (refer to  FIG. 1 ). That is, as described with reference to  FIGS. 6A to 6D , data stored in buffer memory  124  may be programmed in storage device  110 . In this case, data may be programmed in the same nonvolatile memory of storage device  110 , or may be programmed in different nonvolatile memories of storage device  110  (refer to  FIG. 3 ). The data stored in buffer memory  124  is transferred to a RAID buffer  126  (refer to  FIG. 2 ) before or after a program operation is performed. 
         [0095]    In operation S  150 , an XOR operation is performed on data stored in RAID buffer  126 . That is, as described with reference to  FIGS. 6A to 6D , a RAID controller  125  (refer to  FIG. 2 ) may generate RAID parity data by performing an XOR operation on data stored in RAID buffer  126 . Under these circumstances, RAID controller  125  generates one RAID parity data using data corresponding to two different hot pages, and performs an XOR operation until generation of RAID parity data is completed. Afterwards, in operation S 170 , controller  120  resets RAID buffer  126 . 
         [0096]    As indicated by the foregoing, a memory system according to an embodiment of the inventive concept may prevent data loss using the RAID technique. In particular, the memory system may generate different RAID parity data using data to be stored in one hot page to protect the reliability of data in a hot memory block. Thus, it is possible to prevent data stored in a hot page from being lost. 
         [0097]    The embodiments described with reference to  FIGS. 1 to 10  are merely examples, and the inventive concept is not limited thereto. For example, in  FIGS. 1 to 10 , a memory block experiencing more erase operations than other memory blocks may be set to a hot memory block. The inventive concept can also be applied to a three-dimensional memory. In the three-dimensional memory, data of memory cells adjacent to a common source line may be easily damaged by particularity of a fabrication process. In this case, a hot memory block may be defined by memory cells adjacent to the common source line. Below, there will be described an embodiment in which the inventive concept is applied to the three-dimensional memory. 
         [0098]      FIG. 11  is a block diagram illustrating a flash memory  1000  according to an embodiment of the inventive concept. 
         [0099]    Referring to  FIG. 11 , flash memory  1000  comprises a three-dimensional (3D) cell array  1100 , a data input/output circuit  1200 , an address decoder  1300 , and control logic  1400 . 
         [0100]    3D cell array  1100  comprises a plurality of memory blocks BLK 1  to BLKz, each of which is formed to have a three-dimensional structure (or, a vertical structure). For a memory block having a two-dimensional (horizontal) structure, memory cells may be formed in a direction horizontal to a substrate. For a memory block having a three-dimensional structure, memory cells may be formed in a direction perpendicular to the substrate. Each memory block may be an erase unit of flash memory  1000 . 
         [0101]    Data input/output circuit  1200  is connected with the 3D cell array  1100  via a plurality of bit lines. Data input/output circuit  1200  receives data from an external device or outputs data read from the 3D cell array  1100  to the external device. Address decoder  1300  is connected with the 3D cell array  1100  via a plurality of word lines and selection lines GSL and SSL. Address decoder  1300  selects the word lines in response to an address ADDR. 
         [0102]    Control logic  1400  controls programming, erasing, reading, etc. of flash memory  1000 . For example, in programming, control logic  1400  may control address decoder  1300  such that a program voltage is supplied to a selected word line, and may control data input/output circuit  1200  such that data is programmed. 
         [0103]      FIG. 12  is a perspective view illustrating a 3D structure of a memory block illustrated in  FIG. 11 . 
         [0104]    Referring to  FIG. 12 , a memory block BLK 1  is formed in a direction perpendicular to a substrate SUB. An n+ doping region is formed in the substrate SUB. A gate electrode layer and an insulation layer are deposited on the substrate SUB in turn. A charge storage layer is formed between the gate electrode layer and the insulation layer. 
         [0105]    If the gate electrode layer and the insulation layer are patterned in a vertical direction, a V-shaped pillar may be formed. The pillar is connected with substrate SUB via the gate electrode layer and the insulation layer. An outer portion O of the pillar is formed of a channel semiconductor, and an inner portion I thereof is formed of an insulation material such as silicon oxide. 
         [0106]    The gate electrode layer of the memory block BLK 1  is connected with a ground selection line GSL, a plurality of word lines WL 1  to WL 8 , and a string selection line SSL. The pillar of memory block BLK 1  is connected with a plurality of bit lines BL 1  to BL 3 . In  FIG. 12 , there is illustrated the case that one memory block BLK 1  has two selection lines SSL and GSL, eight word lines WL 1  to WL 8 , and three bit lines BL 1  to BL 3 . However, the inventive concept is not limited thereto. 
         [0107]      FIG. 13  is a circuit diagram illustrating an equivalent circuit of a memory block illustrated in  FIG. 12 . 
         [0108]    Referring to  FIG. 13 , NAND strings NS 11  to NS 33  are connected between bit lines BL 1  to BL 3  and a common source line CSL. Each NAND string (e.g., NS 11 ) comprises a string selection transistor SST, a plurality of memory cells MC 1  to MC 8 , and a ground selection transistor GST. 
         [0109]    String selection transistors SST are connected with string selection lines SSL 1  to SSL 3 . Memory cells MC 1  to MC 8  are connected with corresponding word lines WL 1  to WL 8 , respectively. Ground selection transistors GST are connected with ground selection line GSL. A string selection transistor SST is connected with a bit line and a ground selection transistor GST is connected with a common source line CSL. 
         [0110]    Word lines (e.g., WL 1 ) having the same height are connected in common, and string selection lines SSL 1  to SSL 3  are separated from one another. During programming of memory cells (constituting a page) connected with a first word line WL 1  and included in NAND strings NS  11 , NS 12 , and NS 13 , a first word line WL 1  and a first string selection line SSL 1  may be selected. 
         [0111]    In a three-dimensional memory block, a diameter of a pillar may decrease toward a common source line CSL. This may mean that a read error on memory cells adjacent to common source line CSL is generated to be easier than that on memory cells adjacent to a string selection line SSL. 
         [0112]    In some embodiments, memory cells adjacent to common source line CSL may be designated to form hot pages. For example, in the example of  FIGS. 12 and 13 , memory cells sharing a first word line WL 1  may be designated to form hot pages. In this case, data corresponding to hot pages may be managed by the RAID scheme described with reference to  FIGS. 1 to 10 . Thus, it is possible to prevent data stored in hot pages from being damaged. 
         [0113]    For example, referring to  FIGS. 12 and 13 , memory cells immediately adjacent to common source line CSL may share first word line WL 1 . This may mean that memory cells sharing first word line WL 1  correspond to a pillar having the smallest diameter. In this case, memory cells sharing first word line WL 1  and corresponding to a first string selection line SSL 1  may be set to a first hot page, and memory cells sharing first word line WL 1  and corresponding to a second string selection line SSL 2  may be set to a second hot page. Likewise, memory cells sharing first word line WL 1  and corresponding to an nth string selection line SSLn may be set to an nth hot page. 
         [0114]    In this case, data corresponding to hot pages may be managed using the RAID technique described with reference to  FIGS. 1 to 10 . For example, data of a first hot page may be used to generate at least two units of RAID parity data. Likewise, data of a second hot page may be used to generate at least two RAID parity data. Thus, it is possible to prevent data stored in hot pages from being damaged. 
         [0115]    In the examples of  FIGS. 12 and 13 , RAID parity data may be generated in a variety of manners. For example, one RAID parity data may be generated using two different hot pages and a plurality of normal pages. Herein, the normal page may be a page corresponding to another word line except for first word line WL 1 . In this case, normal pages constituting one RAID parity data may correspond to different word lines, respectively. That is, normal pages constituting one RAID parity data may correspond to pillars having different diameters. 
         [0116]      FIG. 14  is a block diagram illustrating a memory card system  2000  comprising a nonvolatile memory according to an embodiment of the inventive concept. 
         [0117]    Referring to  FIG. 14 , memory card system  2000  comprises a host  2100  and a memory card  2200 . Host  2100  comprises a host controller  2110 , a host connection unit  2120 , and a DRAM  2130 . 
         [0118]    Host  2100  writes data in memory card  2200  and reads data from memory card  2200 . Host controller  2110  sends a command (e.g., a write command), a clock signal CLK generated from a clock generator (not shown) in host  2100 , and data to memory card  2200  via host connection unit  2120 . DRAM  2130  may be a main memory of host  2100 . 
         [0119]    Memory card  2200  comprises a card connection unit  2210 , a card controller  2220 , and a flash memory  2230 . Card controller  2220  stores data in flash memory  2230  in response to a command input via card connection unit  2210 . The data may be stored in synchronization with a clock signal generated from a clock generator (not shown) in card controller  2220 . Flash memory  2230  stores data transferred from host  2100 . For example, where host  2100  is a digital camera, flash memory  2230  may store image data. 
         [0120]    Memory card system  2000 , as described above, may prevent data loss using the RAID technique. In particular, memory card system  2000  may generate a plurality of different units of RAID parity data using data to be stored in one hot page to protect the reliability of data in a hot memory block. Thus, it is possible to prevent data stored in a hot page from being damaged. 
         [0121]      FIG. 15  is a block diagram illustrating a solid state drive system  3000  comprising nonvolatile memory according to the inventive concept. 
         [0122]    Referring to  FIG. 15 , solid state drive (SSD) system  3000  comprises a host  3100  and an SSD  3200 . Host  3100  comprises a host interface  3111 , a host controller  3120 , and a DRAM  3130 . 
         [0123]    Host  3100  writes data in SSD  3200  or reads data from SSD  3200 . Host controller  3120  transfers signals SGL such as a command, an address, a control signal, and the like to SSD  22000  via host interface  3111 . DRAM  3130  may be a main memory of host  3100 . 
         [0124]    SSD  3200  exchanges signals SGL with host  3100  via host interface  3211 , and is supplied with a power via a power connector  3221 . SSD  3200  comprises a plurality of nonvolatile memories  3201  to  320 n, an SSD controller  3210 , and an auxiliary power supply  3220 . Herein, nonvolatile memories  3201  to  320 n may be implemented by not only a NAND flash memory but also nonvolatile memories such as PRAM, MRAM, ReRAM, and the like. 
         [0125]    Nonvolatile memories  3201  to  320 n can be used as a storage medium of SSD  3200 . Nonvolatile memories  3201  to  320 n can be connected with SSD controller  3210  via a plurality of channels CH 1  to CHn. One channel may be connected with one or more nonvolatile memories. Nonvolatile memories connected with one channel may be connected with the same data bus. 
         [0126]    SSD controller  3210  exchanges signals SGL with host  3100  via host interface  3211 . Herein, the signals SGL may include a command, an address, data, and the like. SSD controller  3210  may be configured to write or read out data to or from a corresponding nonvolatile memory according to a command of host  3100 . SSD controller  3210  will be more fully described with reference to  FIG. 16 . 
         [0127]    Auxiliary power supply  3220  is connected with host  3100  via power connector  3221 . Auxiliary power supply  3220  is charged by a power PWR from host  3100 . Auxiliary power supply  3220  can be placed inside or outside SSD  3200 . For example, auxiliary power supply  3220  may be put on a main board to supply the auxiliary power to SSD  3200 . 
         [0128]      FIG. 16  is a block diagram illustrating an example of SSD controller  3210  of  FIG. 15 . 
         [0129]    Referring to  FIG. 16 , SSD controller  3210  comprises an NVM interface  3211 , a host interface  3212 , a RAID unit  3213 , a control unit  3214 , and an SRAM  3215 . 
         [0130]    NVM interface  3211  scatters data transferred from a main memory of host  2100  to channels CH 1  to CHn, respectively. NVM interface  3211  transfers data read from nonvolatile memories  3201  to  320 n to host  3100  via host interface  3212 . 
         [0131]    Host interface  3212  provides an interface with an SSD  3200  according to the protocol of host  3100 . Host interface  3212  may communicate with host  3100  using a standard such as Universal Serial Bus (USB), Small Computer System Interface (SCSI), PCI express, ATA, Parallel ATA (PATA), Serial ATA (SATA), Serial Attached SCSI (SAS), etc. Host interface  3212  performs a disk emulation function which enables host  3100  to recognize SSD  3200  as a hard disk drive (HDD). 
         [0132]    As described with reference to  FIG. 1 , RAID unit  3213  may generate a plurality of different RAID parity data using data to be stored in a hot page to protect the reliability of data in a hot memory block. Thus, it is possible to prevent loss of data stored in a hot page. 
         [0133]    Control unit  3214  may be used as a working memory to perform an overall operation. DRAM  3214  may be used as a buffer to store data temporarily. 
         [0134]    SRAM  3215  may be used to drive software which efficiently manages nonvolatile memories  3201  to  320 n. SRAM  3215  may store metadata input from a main memory of host  3100  or cache data. At a sudden power-off operation, metadata or cache data stored in SRAM  3215  may be stored in nonvolatile memories  3201  to  320 n using an auxiliary power supply  3220 . 
         [0135]    SSD system  3000 , as described above, may generate a plurality of different RAID parity data using data to be stored in one hot page to protect the reliability of data in a hot memory block. Thus, it is possible to prevent data stored in a hot page from being damaged. 
         [0136]      FIG. 17  is a block diagram illustrating an electronic device  4000  comprising a flash memory system according to an embodiment of the inventive concept. Herein, an electronic device  4000  may be a personal computer or a handheld electronic device such as a notebook computer, a cellular phone, a PDA, a camera, and the like. 
         [0137]    Referring to  FIG. 17 , electronic device  4000  may include a memory system  4100 , a power supply device  4200 , an auxiliary power supply  4250 , a CPU  4300 , a DRAM  4400 , and a user interface  4500 . Memory system  4100  may include a flash memory  4110  and a memory controller  4120 . Memory system  4100  can be embedded within electronic device  4000 . 
         [0138]    Electronic device  4000 , as described above, may generate a plurality of different RAID parity data using data to be stored in one hot page to protect the reliability of data in a hot memory block. Thus, it is possible to prevent data stored in a hot page from being damaged. 
         [0139]    The foregoing is illustrative of embodiments and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims.