Abstract:
A testing circuit and method for a phase-locked loop allow measurement of leakage currents in the phase-locked loop components. By forcing the output of the phase-frequency detector to a particular state, the charge pump can be disabled. This disables the effect of feedback in the phase-locked loop, and allowing the output frequency to be determined by the voltage on the control voltage node at the time the feedback is disabled. If there is no leakage, the control voltage, and therefore the output frequency, should remain the same as they were at the moment feedback was disabled. Monitoring the output frequency for changes provides an indication of the presence or absence of leakage. Conducting the test using two different charge pump reference currents allows one to detect leakage resulting from charge pump mismatch.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to phase-locked loops. More particularly, this invention relates to a method and apparatus for testing a phase-locked loop, and to circuitry for facilitating such testing. 
     The use of phase-locked loops for generating clock and frequency standards is well known. At its most basic, a phase-locked loop (“PLL”) includes, in series, a phase-frequency detector having a first input to which a reference frequency is applied, a charge pump, a loop filter and a voltage-controlled oscillator (“VCO”). The output of the VCO, which is the output of the PLL, is fed back to a second input of the phase-frequency detector. Any phase variance between the reference signal and the feedback signal causes the phase-frequency detector to generate a voltage which is input to the charge pump and loop filter, which output a control voltage to the voltage-controlled oscillator. The PLL output signal keeps changing as the control voltage changes until there is a match between the frequencies of the output and the reference signal, which is detected by the phase-frequency detector. At that point, the PLL is considered to be locked. 
     Known methods for testing a PLL test whether or not the PLL is capable of locking on a reference signal. However, even if the PLL locks, it may nevertheless be subject to drift if there is excessive leakage current in, e.g., the charge pump or the loop filter, resulting in a phase variance between the input signal and the output signal. It would be desirable to be able to provide a method for testing a PLL that would be capable of detecting such leakage currents or their effects, apparatus for performing such a test and a PLL adapted for such a test. 
     SUMMARY OF THE INVENTION 
     It is an advantage of the present invention that it provides a method for testing a PLL that would be capable of detecting such leakage currents or their effects, apparatus for performing such a test and a PLL adapted for such a test. 
     In accordance with the present invention, there is provided a method of testing a phase-locked loop. The method includes inputting a reference signal to the phase-locked loop, allowing the phase-locked loop to lock onto the reference signal, discontinuing feeding back of the loop output, and monitoring the loop output, after the discontinuing, for a change in the output frequency. Apparatus for performing such a test, and a phase-locked loop adapted to be so tested, are also provided. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which: 
     FIG. 1 is a schematic diagram of a phase-locked loop circuit adapted to be tested in accordance with the present invention; 
     FIG. 2 shows a schematic representation of a charge pump and loop filter in a phase-locked loop circuit, such as that of the present invention; 
     FIG. 3 is a representation of a leakage current model of the charge pump and loop filter of the circuit of FIG. 1; 
     FIG. 4 is an illustration of relationship of the control voltage to the input and feedback signals in the circuit of FIG. 1 in the absence of leakage current; 
     FIG. 5 is an illustration of the variation in the control voltage in the circuit of FIG. 1 in the presence of leakage current, and the effect on the output signal; 
     FIG. 6 is a schematic representation of a preferred embodiment of a phase-frequency detector in accordance with the present invention for controlling the charge pump to carry out the method according to the invention; and 
     FIG. 7 is a simplified block diagram of an illustrative system employing a programmable logic device incorporating a phase-locked loop in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In accordance with the present invention, phase-locked loops may be more thoroughly tested. In addition to testing whether or not a PLL is capable of locking onto a reference signal, the testing method according to the present invention determines whether or not there are leakage currents in the charge pump and/or loop filter that may affect the output signal, causing, e.g., a phase variance or misalignment in the output signal. The present invention also provides a testing apparatus for PLLs and a PLL circuit adapted for testing according to the method of the invention. 
     A phase-locked loop circuit  10  in accordance with the present invention is shown in FIG.  1 . Although PLL circuit  10  is particularly adapted for testing in accordance with the present invention, that does not make it any less susceptible than previously known PLL circuits to the conditions being tested for, and therefore it is not inappropriate to discuss those conditions in the context of PLL circuit  10 . 
     As seen in FIG. 1, PLL circuit  10  includes a phase-frequency detector (“PFD”)  11  having an input  110  which is the input of the PLL to which the input reference signal is applied. The outputs  111  of PFD  11  are input to charge pump  12 , whose output  121  is the control voltage input to loop filter  13  and to voltage-controlled oscillator (“VCO”)  14 . The output of VCO  14  is the output  101  of PLL circuit  10  (except as noted below), and also is fed back to PFD  11 . As is well known, PFD  11  reacts to any phase or frequency difference between the feedback signal  101  and the input reference signal  110  by outputting an UP or DOWN signal  111  that causes charge pump  12  to either charge or discharge loop filter  13 , raising or lowering control voltage  121 , which in turn adjusts the frequency and/or phase of output signal  101 . 
     The ultimate output signal  102  can be adjusted using optional scale counters  15 ,  16 ,  17 . Input scale counter  15  will divide the frequency of input signal  110  by N. Output scale counter  16  will divide the frequency of output  101  by G. Feedback scale counter  17  will multiply the frequency of output  101  by M. Thus, the output frequency will be the input frequency multiplied by M/NG. 
     As stated above, known testing methods for PLLs test whether or not the circuit locks onto the reference input signal, but do not test for drift of the output that may result from, e.g., leakage currents within the circuit—particularly within charge pump  12  and loop filter  13 . The effects of such leakage currents can be explained with reference to FIGS. 2-5. 
     FIG. 2 shows a simplified diagram of the charge pump  12  and loop filter  13 , along with a schematic representation of PFD  11 . If charge pump  12  is disabled so that it does not charge or discharge loop filter  13 , then the model shown in FIG. 3 can be used to describe the behavior of charge pump  12  and loop filter  13 . The drift of the control voltage at node  121  may be expressed as: 
     
       
         ΔV CTRL =(I leak     —     pmcs −I leak     —     nmos −I leak     —     cap )Δt/C lf , 
       
     
     where C lf  is low-frequency capacitor  131 . The control voltage cannot be directly observed without providing an additional output pin, so another method must be used to determine if there is excessive leakage current. One such method is to disable the feedback loop  101  so that charge pump  12  is not trying to adjust the control voltage. In accordance with the invention, one preferred way of doing that is using a modified phase-frequency detector as discussed below. However, regardless of how charge pump  12  is disabled, once that is done, only leakage currents will affect the control voltage  121 . 
     Specifically, as seen in FIG. 4, for the case without leakage current, a small amount of noise is coupled to control voltage  121  at every rising edge of the reference and feedback clocks  110 ,  101 , but control voltage  121  remains constant, and clocks  110 ,  101  remain in phase. Although as shown in FIG. 4, input clock  110  and output clock  101  have equal frequencies, that is not necessary, as long as the ratio of the frequencies is known as discussed below. 
     As seen in FIG. 5, for the case with leakage current, a static offset  50 , in the form of a phase shift, is generated to compensate for the leakage current. Control voltage  121  thus assumes a sawtooth pattern as it rises on each cycle as a result of the leakage current until the compensation effect causes it to fall back to its nominal value over the remainder of each cycle. This variation of control voltage  121  over the clock cycle will cause deterministic jitter on output  101 . Therefore, it is important to know if there are leakage currents in the circuit  10 . 
     In accordance with a preferred embodiment of the present invention, in order to test circuit  10 , a known input clock signal  110  is supplied and circuit  10  is allowed to lock. START signal  18  is then enabled. As discussed below in connection with FIG. 6, application of START signal  18  to PFD  11  preferably drives the PFDUP and PFDDN signals low, so that neither the UP nor DOWN charge pump of charge pump  12  is turned ON. Control voltage  121  is therefore free to float, and will remain constant in the absence of leakage current, so that in the absence of leakage current the frequencies of outputs  101  and  102  will not change once START signal  18  is applied. If, from the time START signal  18  is applied, input signal  110  is directed also to reference counter  19  and output  102  is directed to test counter  100  (with both counters  19 ,  100  enabled by START signal  18  for the purposes of the test), the relative values in counters  19 ,  100  would be expected to remain about the same (or to maintain a ratio of about G), although some variation may be tolerated. 
     FIG. 6 shows the internal logic of PFD  11 . The control block  112  is added in accordance with the present invention to respond to START signal  18 . START signal  18  can be connected to charge_pump_ON signal CPON, charge_pump_OFF signal CPOFF, or both. As can be seen from FIG. 6, if CPON and CPOFF are both low, both the UP and DN signals from PFD  11  to charge pump  12  will be off, disabling charge pump  12  by keeping both the UP and DOWN charge pumps off. If CPON is high, then both the UP and DN signals from PFD  11  to charge pump  12  will be high (regardless of the state of CPOFF), disabling charge pump  12  by forcing both the UP and DOWN charge pumps on, working against one another so that the control voltage at node  121  is about zero, but also revealing charge pump mismatch, if any. 
     It should be noted that control block  112  could be implemented with only AND gates  113  and the CPOFF input, or with only OR gates  114  and the CPON input. Alternatively, although both AND gates  113  and OR gates  114  are provided, one of the CPON or CPOFF inputs could be tied to a fixed value. In a preferred embodiment only AND gates  113  and the CPOFF input is provided. 
     The following truth table shows the possible states of control block  112 , where “X” indicates “Don&#39;t Care”: 
     
       
         
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                   
               
               
                 CPON 
                 CPOFF 
                 PFDUP 
                 PFDDN 
                 UPI 
                 DNI 
                 UP 
                 nUP 
                 DN 
                 nDN 
                 Note 
               
               
                   
               
             
             
               
                 1 
                 X 
                 X 
                 X 
                 1 
                 1 
                 0 
                 1 
                 1 
                 0 
                 1 
               
               
                 0 
                 0 
                 X 
                 X 
                 0 
                 0 
                 1 
                 0 
                 0 
                 1 
                 2 
               
               
                 0 
                 1 
                 0 
                 0 
                 0 
                 0 
                 1 
                 0 
                 0 
                 1 
                 3 
               
               
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
                 1 
                 0 
                 1 
                 0 
                 3 
               
               
                 0 
                 1 
                 1 
                 0 
                 1 
                 0 
                 0 
                 1 
                 0 
                 1 
                 3 
               
               
                 0 
                 1 
                 1 
                 1 
                 1 
                 1 
                 0 
                 1 
                 1 
                 0 
                 3 
               
               
                   
               
               
                 The following notes apply:  
               
               
                 1. Force charge pump on to enable both the up and down currents to measure charge pump mismatch  
               
               
                 2. Force charge pump off to measure the net loop filter and charge pump leakage current.  
               
               
                 3. Normal mode of operation.  
               
             
          
         
       
     
     The test should be allowed to run for a minimum time sufficient for a noticeable difference to accumulate. In a preferred embodiment such as that described, that minimum period preferably is long enough for reference counter  19  to reach a count of 2048. There is no maximum for the purposes of the test, but for production reasons, it would be undesirable to exceed the minimum necessary duration. 
     The magnitude of any leakage current can be calculated as follows: 
     First, simplify: 
     
       
         I leak     —     pmos −I leak     —     nmos −I leak     —     cap =I leak . 
       
     
     Therefore: 
     
       
         ΔV CTRL =I leak Δt/C lf . 
       
     
     The change, if any, in the frequency of output  101  may be written as: 
     
       
           Δf   VCO   =K   VCO   I   leak   Δt/C   lf , 
       
     
     where K VCO  is the gain of VCO  14 . Because Δf PLL =Δf VCO /G, then 
     
       
           Δf   PLL   =K   VCO   I   leak   Δt /( GC   lf ) 
       
     
     or: 
     
       
           I   leak   =Δf   PLL   GC   lf /( K   VCO   Δt ) 
       
     
     The value stored in reference counter  18  is: 
       N   ref   =f   ref   Δt  (from which we can derive Δt=N ref /f ref ), 
     and 
     
       
           N   PLL   =f   average   Δt= ( f   ref +0.5Δf PLL )Δ t,   
       
     
     where Δf PLL  is a signed quantity. Solving for Δf PLL  yields: 
     
       
           Δf   PLL =2 (( N   PLL   −N   ref )/ Δt ) 
       
     
     Therefore, 
     
       
           I   leak =2 GC   lf (( N   PLL   −N   ref )/Δ t )/( K   VCO   Δt ) 
       
     
     
       
         I leak =2 GC   lf ( N   PLL   −N   ref )/( K   VCO (Δ t   2 )). 
       
     
     Substituting Δt=N ref /f ref  from above yields: 
     
       
           I   leak=( 2 GC   lf ( f   ref   2 )/K VCO )(( N   PLL −N ref )/( N   ref   2 )).  (Equation 1) 
       
     
     This equation yields the leakage current in terms of the measured counter values, the known scale value G, and the quantities C lf  and K VCO . Although the latter two quantities are considered to be known in any particular case, they can vary as a result of process conditions, temperature and voltage. Thus, the equation yields an estimate whose accuracy is determined by the possible ranges of those variations. 
     The foregoing analysis does not take into account the possibility of balance among the three components of I leak —i.e., I leak     —     pmos , I leak     —     nmos  and I leak     —     cap  at the test voltage, making the PLL appear to pass the test, but allowing phase or frequency errors under operating conditions at different control voltages. If I leak     —     cap =0 and I leak     —     pmos  and I leak     —     nmos  are balanced, that is not a problem because the control voltage node would not be affected. However, if under the test conditions, one of I leak     —     pmos  and I leak     —     nmos  is zero, and the other of I leak     —     pmos  and I leak     —     nmos  is non-zero and balances I leak     —     cap  which also is non-zero, or both I leak     —     pmos  and I leak     —     nmos  are non-zero but different and the difference is balanced by I leak     —     cap , then under operating conditions that balance might not be maintained, allowing phase or frequency errors. 
     This condition can be tested for by testing PLL circuit  10  twice using two different charge pump reference currents. Ideally, for a given applied charge pump reference current, the reference current in the NMOS portion  20  of charge pump  12  is identical to the reference current in the PMOS portion  21  of charge pump  12 . In practice, however, 
     
       
           I   ref     —     pmos   =CI   ref     —     nmos , 
       
     
     where 0.9&lt;C&lt;1.1 as a function of voltage, equalling 1 only at a particular voltage. Similarly, 
     
       
         
           I 
           leak 
           
             — 
           
           pmos 
           =AI 
           ref 
           
             — 
           
           pmos 
         
       
     
     and 
     
       
           I   leak     —     nmos   =BI   ref     —     nmos , 
       
     
     where A and B are constants. In view of these relationships, if one tests twice, using two different charge pump reference currents, any balance that may exist among I leak     —     pmos , I leak     —     nmos  and I leak     —     cap  at one charge pump reference current will be lost at a different charge pump reference current, allowing an accurate determination of the leakage currents. 
     For example, in performing a test according to a preferred embodiment of the method of the present invention, a clock input of, e.g., about 20 MHz may be applied to PLL circuit  10 . The charge pump reference current may be set to 50 μA, and loop filter  13  should be configured with resistor  130  having a resistance R≈1 kΩ and high-frequency capacitor  132  having a capacitance C hf ≈20 pF. VCO  14  preferably is set to about the middle of its operating range (e.g., in a preferred embodiment, about 720 MHz). Output  102  from PLL circuit  10  should be routed to test counter  100  and the reference clock  110  should be routed to a reference counter  19 . Input scale counter  15  counter preferably is set for bypass mode (N=1), while both output scale counter  16  and feedback scale counter  17  preferably are set to G=M=36. 
     PLL circuit  10  should be allowed to lock to reference clock  110 . Once PLL circuit  10  locks, phase-frequency detector  11  should be disabled, while counters  19 ,  100  should be enabled, by asserting START signal  18 . Counters  19 ,  100  preferably should be run until reference counter  19  reaches a count of 2048 (after about 102.4 μs), at which point both counters  19 ,  100  preferably should be disabled by deasserting START signal  18 . 
     In a preferred embodiment, if the value in test counter  19  is less than 2048, then the leakage current is negative which implies that a leakage exists between control voltage node  121  and ground. In that embodiment, if the value in test counter  19  is greater than 2048, then the leakage current is positive which implies that a leakage exists between control voltage node  121  and V cc . Note, however, that in other embodiments, the frequency could decrease with increasing control voltage and increase with decreasing control voltage, in which case a higher count would signify a negative leakage current and a lower count would signify a positive leakage current. 
     The values in counters  19 ,  100  can be read and then used in Equation 1, above, to determine the leakage current. Because K VCO  and C lf  typically have known tolerances, Equation 1 can actually be used to compute a range of leakage currents. 
     As discussed above, in order to be more certain that the leakage current is not being masked by a fortuitous balance among the various leakage currents in charge pump  12 , the test preferably should be repeated with the charge pump current set to a different value, such as, e.g., 23 μA. 
     At both charge pump current settings, the acceptable difference in this preferred embodiment between the two counters  19 ,  100  is ±25. If the count measured for the two charge pump currents is the same, then the most likely source of the leakage current is loop filter  13 , whereas if the counts are different, the most likely source of leakage current is charge pump  12 . 
     It should be noted that although in PLL circuit  10  as described, counters  19 ,  100  are used to monitor the output frequency for changes that might indicate leakage, other monitoring devices could be used. For example, one might use an appropriately configured oscilloscope, frequency counter or spectrum analyzer. 
     PLL circuit  10  according to the present invention may be used in many kinds of electronic devices. One possible use is in a programmable logic device (“PLD”)  908  of a type that requires an accurate frequency standard. For example, PLD  908  may be of a type using the Low Voltage Differential Signaling (“LVDS”) input/output (“I/O”) standard. Such a PLD  908  may be used as part of a data processing system  900  shown in FIG.  7 . Data processing system  900  may include one or more of the following components: a processor  901 ; memory  902 ; I/O circuitry  903 ; and peripheral devices  904 . These components are coupled together by a system bus  905  and are populated on a circuit board  906  which is contained in an end-user system  907 . 
     System  900  can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application where the advantage of using programmable or reprogrammable logic is desirable. PLD  908  can be used to perform a variety of different logic functions. For example, PLD  908  can be configured as a processor or controller that works in cooperation with processor  901 . PLD  908  may also be used as an arbiter for arbitrating access to a shared resources in system  900 . In yet another example, PLD  908  can be configured as an interface between processor  901  and one of the other components in system  900 . It should be noted that system  900  is only exemplary, and that the true scope and spirit of the invention should be indicated by the following claims. 
     Various technologies can be used to implement PLDs  908  as described above and incorporating this invention. 
     It will be understood that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention, and the present invention is limited only by the claims that follow.