Abstract:
A method of etching in a plasma etching chamber having an upper electrode and a susceptor is disclosed. The method comprises: setting the upper electrode and the susceptor to a first predetermined distance; performing a first etch at the first predetermined distance for a first predetermined time; setting the upper electrode and the susceptor to a second predetermined distance; and performing a first etch at the second predetermined distance for a second predetermined time.

Description:
FILED OF THE INVENTION 
     The present invention relates to etching, and more specifically, to a method of etching using variable electrode spacing. 
     BACKGROUND OF THE INVENTION 
     Etching in semiconductor processing has inherent limitations. An ideal anisotropic etch leaves vertical walls in the resist and metal layers. However, because the etching chemical dissolves the top of the wall for a longer time than the bottom, the resulting hole is wider at the top than at the bottom. Hence, the etch is somewhat isotropic. 
     Dry etching processes, such as reactive ion etching, have decreased this problem. Dry etch techniques rely in part on material from the masking layer (usually photoresist) to achieve anisotropic profiles. This has the undesirable side effect of making the etch anisotropically sensitive to masking pattern density. 
     Another difficulty with prior etching techniques is that the etching varies over the surface of the wafer. In other words, certain portions of the wafer are over etched, while other portions of the wafer are under etched. The above are merely examples of etching limitations. 
     The etching process is performed in an etching tool, such as the tools manufactured by Tokyo Electron Ltd. (TEL) of Tokyo, Japan. TEL manufactures a dipole ring magnetron (DRM) etching tool called the Unity DRM. This tool is described in U.S. Pat. No. 6,014,943 to Arami et al. In the Unity DRM etching tool, a semiconductor wafer is subjected to a plasma atmosphere which is generated by introducing a process gas into a process vessel and converting the process gas into a plasma-state gas. 
     In recent years, the degree of integration of semiconductor devices has been increased and critical dimensions have decreased. One of the more difficult etching problems is evenly etching contact vias for connection to a bitline of a DRAM memory array, particularly over the entire surface of the wafer. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein: 
     FIG. 1 is a schematic diagram of a plasma etching chamber used in connection with the present invention; 
     FIG. 2 is a flow diagram illustrating the process of the present invention; and 
     FIGS. 3-7 illustrate how the method of the present invention can be used to etch a bitline contact in a DRAM memory cell. 
    
    
     SUMMARY OF THE INVENTION 
     A method of etching in a plasma etching chamber having an upper electrode and a susceptor is disclosed. The method comprises: setting the upper electrode and the susceptor to a first predetermined distance; performing a first etch at the first predetermined distance for a first predetermined time; setting the upper electrode and the susceptor to a second predetermined distance; and performing a first etch at the second predetermined distance for a second predetermined time. 
     DETAILED DESCRIPTION 
     Turning to FIG. 1, a plasma etching apparatus  101  is shown. The chamber  101  includes a cylindrical process vessel  103  made of a metal e.g., an anodized aluminum. The process chamber  103  can be opened or closed airtight. The process chamber  103  itself is grounded, for example, by connecting to a ground line. 
     In the bottom of the process chamber  103 , a cylindrical susceptor  105  for mounting a semiconductor wafer W thereon, is provided coaxially with the process vessel  103 . The susceptor  105 , whose surface is formed of anodized aluminum, serves as a lower electrode. The susceptor  105  is supported by a support pole  107 . The bottom end of the support pole  107  projects outwardly from the bottom wall of the process vessel  103 . The support pole  107  can move vertically (as indicated by a double-headed arrow in FIG. 1) under the control of a driving source (e.g., a motor) provided outside of the process vessel  103 . 
     FIG. 1 shows the position of the susceptor  105  during etching. When the wafer W is loaded/unloaded, the susceptor  105  is descended to low position. On the susceptor  105  is an electrostatic chuck (not shown) for holding the wafer W. The wafer W is disposed in a predetermined position on the electrostatic chuck. 
     A circular opening is provided in the center of the upper wall of the process. chamber  103 . In the periphery of the circular opening, a non-conductive ring  109  made of alumina or the like is set. Attached to the ring  109  is an upper electrode  111  positioned to face the susceptor  105  and thus the wafer W mounted thereon with a predetermined distance D apart from the wafer W. The entire upper electrode  111  of this preferable embodiment is made of a conductive material such as surface-anodized aluminum. 
     The upper electrode  111  has a hollow portion to which gas may be introduced through a gas inlet  113 . In the lower wall of the upper electrode  111 , a number of gas-emitting holes  115  are formed with a predetermined distribution, for supplying a process gas above the entire wafer surface W uniformly. 
     In this embodiment, a predetermined process gas, for example, a CF series etching gas such as a CF 4  gas or a C 4 F 8  gas is supplied. The etching gas is emitted from the gas-emitting holes  115  of the upper electrode  111 , at a controllable flow rate, and supplied uniformly to the wafer W. In other words, the gas is supplied into the plasma generation space between the susceptor  105  and the upper electrode  11 . 
     Further, a first high frequency power source  117  is used for generating a high frequency power having a frequency of several hundreds kHz, e.g., 800 kHz. The first high frequency power source  117  is connected to the susceptor  105  (the lower electrode). Also, a second high frequency power source  119  is connected to the upper electrode  111 . The second high frequency power source  119  is used for generating a high frequency power having a frequency of, e.g., 27.12 MHz which is higher than that of the first high frequency power source  117 . Finally, along the periphery of the process vessel  103 , a dipole ring magnet  121  is provided as a magnetic-field generation means. 
     It should be appreciated that other elements of the plasma etching apparatus  101  have not been described for simplicity. However, those of ordinary skill in the art will recognize that elements used for controlling temperature, pressure, gas flow rate, frequency, and power are all commonly used in such apparatus. For purposes of the present invention, the spacing D between the susceptor  105  and the upper electrode  111  is of primary interest. 
     In accordance with the present invention, and in contrast to the prior art, the spacing D is varied during an etching process. It has been found that using the variable electrode spacing technique, improved uniformity in etching can be achieved. Specifically, the plasma distribution during etching will be affected by the electrode gap. If the gap is larger, the etching rate in the center part of the wafer will be faster than at the edge. Further, if the gap is made smaller, the etching rate in the edge of the wafer will be higher than in the center. 
     In a conventional method, the gap is made relatively large and etching time is increased to ensure that the etching is complete in the peripheral regions of the wafer. However, this may result in overetching in the central portion of the wafer. 
     Thus, turning to FIG. 2, an etching process begins at box  201  with the susceptor  105  and upper electrode  111  having a large spacing D. The etching process continues for a predetermined amount of time, and at box  203 , the susceptor  105  and upper electrode  111  are moved to have a narrower spacing D. Finally, at box  205 , the etching continues with the narrower spacing D for a second predetermined amount of time. 
     In an alternative embodiment, the first etching is performed using a narrow spacing D and the second etching is performed using a wider spacing D. Thus, the order by which the etching is done is not crucial, but important consideration is that by adjusting the spacing D, improved results can be obtained. 
     In accordance with one actual embodiment, using the Unity DRM apparatus, the maximum spacing D is 37 millimeters and the minimum spacing D is 27 millimeters. In the prior art, the spacing D is typically on the order of 30-32 millimeters for optimal etching. In the prior art, for etching of about 7000 to 9000 angstroms of oxide to form a contact via to the bitline of a DRAM, the spacing D is set at 32 millimeters and the etching is performed for 75 seconds. 
     Specifically, as seen in FIGS. 3-7, the process of etching a bitline contact comprises the etching of an anti-reflective coating (ARC), a first self-aligned contact (SAC) oxide etch (SAC 1  etch), a second SAC oxide etch (SAC 2 ), and a liner oxide etch. 
     Turning to FIG. 3, a typical cross section of a DRAM memory cell is shown. A gate stack  301  is formed on a semiconductor substrate  303 . Typically, the gate stack is a composite of a thin oxide layer, a polysilicon layer, and a silicide layer. Formed over the two gate stacks  301  is a liner oxide layer  305 . Over the liner oxide layer  305  is a bulk oxide layer  307  that can be formed from borophosphosilicate glass (BPSG) or tetraorthoethlysilicate (TEOS). Next, formed over the bulk oxide layer is an anti-reflective coating (ARC) layer  309 . Finally, in order to form the bitline contact that extends down between the two gate stacks  301  to the substrate  303 , a photoresist layer  311  is deposited and patterned over the ARC  309  to include a bitline opening  313 . The photoresist layer  311  is used as an etching mask. The foregoing steps are conventional in the prior art. 
     Next, an etching step is performed to remove that portion of the ARC  309  that is exposed by the photoresist layer  311 . In the preferred embodiment using the Unity DRM apparatus, the etch is performed at a pressure of 60 millitorr, a power of 1400 watts, and a gap of 32 millimeters for 40 seconds. Also, the gases used are CF 4  flowed at 80 sccm, O 2  flowed at 20 sccm, and Ar flowed at 100 sccm. After the etch, the resulting structure is shown in FIG.  4 . 
     Next, a first part of the SAC 1  etch is performed. During the first part of the SAC 1  etch, the etch is performed at a pressure of 53 millitorr, a power of 1500 watts, and a gap spacing D of 37 millimeters for between 30 and 40 seconds. Also, the gases used are C 4 F 8  flowed at 12 sccm, CO flowed at 250 sccm, and Ar flowed at 285 sccm. 
     Next, a second part of the SAC 1  etch is performed with the spacing D at 27 millimeters for between 40 and 35 seconds. Similarly, during the second portion of the SAC 1  etch, the etch is performed at a pressure of 53 millitorr and a power of 1500 watts. Also, the gases used are C 4 F 8  flowed at 12 sccm, CO flowed at 250 sccm, and Ar flowed at 285 sccm. The resulting structure is shown in FIG.  5 . 
     Next, the SAC 2  etch is performed to removing the remaining bulk oxide between the gate stacks  301 . Preferably, the SAC 2  etch is performed at a pressure of 53 millitorr, a power of 1500 watts, and a gap spacing D of 32 millimeters for about 20 seconds. Also, the gases used are C 4 F 8  flowed at 10 sccm, CO flowed at 250 sccm, Ar flowed at 250 sccm, and O 2  flowed at 2 sccm. The resulting structure is shown in FIG.  6 . 
     Finally, the liner etch is performed to remove the liner oxide  305  between the gate stacks  301 . Preferably, the liner etch is performed at a pressure of 50 millitorr, a power of 500 watts, and a gap spacing D of 32 millimeters for about 10 seconds. Also, the gases used are CHF 3  flowed at 30 sccm and O 2  flowed at 30 sccm. The resulting structure is shown in FIG.  7 . 
     While the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention. For example, although a specific etching recipe is described in connection with a bitline contact etch, the present invention may be used with any etching process that requires uniform etching over the entire surface of the wafer.