Abstract:
A pre-distortion shaping network employing a field effect transistor as one leg of a resistive voltage divider for shaping the modulating signal of a voltage controlled oscillator is described.

Description:
BACKGROUND AND SUMMARY 
     Distortion in the modulation of a voltage-controlled oscillator (VCO) is a well-known problem. Frequently, a non-linear shaping function is employed to shape the modulating signal of a VCO for reducing distortion in the frequency modulation (FM) component of the output signal of the VCO. 
     One prior art shaping function utilizes a diode-resistor network such as that shown in FIG. 1. The resistors are typically selected for reduced distortion in VCO output which is time consuming and expensive. Distortion specifications for VCO&#39;s which employ such a network, range from about -29 dB to about -54 dB. 
     In another prior art shaping network shown in FIG. 2, the V GS  -I D  characteristic of a field-effect transistor (FET) is used to pre-distort the modulating signal of a VCO to reduce distortion. Since the FET operates in the saturated region of its characteristic, the non-linearity achievable for modulation of the VCO is essentially uncontrollable because it cannot be reduced below a computable minimum. Thus, VCO output distortion is typically no better than about -30 dB. 
     In the present invention, the non-linear resistance of an FET is employed as one leg of a resistive voltage divider network. The output of this network is also used to pre-distort a VCO modulation signal. However, this network relies on the V DS  -I D  characteristic of the FET which is biased to operate in the linear region of that characteristic. Therefore, nearly any degree of controllable pre-distortion may be achieved. 
     A pre-distortion shaping network constructed according to the principles of the present invention provides a second order voltage transfer function, the first and second order coefficients of which may be independently selected. The non-linearity of that voltage transfer function is approximately equal to the inverse of the VCO frequency modulation transfer function non-linearity. 
     The shaping network of the present invention provides at least 30 dB improvement in VCO FM distortion. Typically, -90 dB distortion is obtainable. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic of one prior art pre-distortion network which includes a diode-resistor network. 
     FIG. 2 is a schematic of another prior art pre-distortion network which employs the V GS  -I D  characteristic of an FET biased to the saturation region thereof. 
     FIGS. 3A, 3B, 3C and 3D are schematics of pre-distortion shaping networks constructed according to the principles of the present invention. 
     FIG. 4 is a schematic diagram of a typical oscillator tank circuit. 
     FIG. 5 is a block diagram including transfer function g(v). 
     FIG. 6 is a schematic diagram of an FET biased to operate in its linear region. 
     FIG. 7 is a diagram of V DS  -I D  characteristics curve of an FET for operation in the unsaturated region. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     An analysis of the non-linear shaping function required by a typical VCO to produce substantially distortion-free FM output signals, shows that the pre-distortion shaping required is predominantly second order and is given by the following relation: ##EQU1## The derivation of equation A is given in Exhibit A to this specification. The analysis is not necessary to understand the operation of the FET shaping network of the present invention, but is required to design such a shaping network for a particular VCO. 
     The transfer function of the FET shaping network 30 (as shown in FIGS. 3A and 3C) of the present invention is given by the relation: ##EQU2## Where R ON  is the resistance of the drain to sink junction of semiconductor device 32 evaluated when the gate-to-sink voltage is zero; i.e., V GS  =0 (see Exhibit B, page 16); 
     where R is the resistance of resistor 31 (as shown in FIGS. 3A-3D); 
     where V P  is the pinch-off voltage for semiconductor device 32 (as shown in FIGS. 3A-3D); and 
     where V in  and V out  are the input voltage and output voltage, respectively, of the shaping network 30 and 33 (as shown in FIGS. 3A-3D). 
     The derivation of equation B is given in Exhibit B to this specification. 
     The transfer function of the FET shaping network 33 (as shown in FIGS. 3B and 3D) of the present invention is given by the relation: ##EQU3## 
     The derivation of equation C is given in Exhibit C to this specification. 
     The close match between equations A and B and A and C indicate that the FET shaping network of the present invention very closely approximates the shaping required to linearize the output FM modulation of the VCO signal. 
     A comparison of equations A and B also shows the improvement of the present invention over traditional prior art diode-resistor shaping network. Such networks provide a transfer function comprised of interconnected straight-line segments having break points at the interconnection which approximate the desired curve. The more break points, the better the approximation, and many such break points are required to suppress higher order terms of the transfer function which are also produced by the network. The FET shaping network provides a transfer function having no break points and is inherently low in higher order terms. 
     The shaping networks 30, 33 of FIGS. 3A-3D are resistive voltage dividers a semiconductor device, 32 namely an FET, resistor 31 and voltage source 34. Semiconductor device 32 is employed as one of the two resistances in the divider. Two basic configurations of the divider are provided; divider 30 in FIGS. 3A and 3C are the same but different from dividers 33 in FIGS. 3B and 3D. Such networks are utilized to shape the modulating signal of a VCO to reduce distortion in the FM component of the output signal of a VCO. 
     The shaping network of the present invention attenuates its input voltage because it is a voltage divider. However, often it is desirable to have a shaper circuit with at least unity gain. Such gain may be achieved by amplifying the output signal from the divider network as shown in FIGS. 3A and 3B, or by scaling the input signal to the divider network as shown in FIGS. 3C and 3D. 
     The shaping networks of the present invention shown in FIGS. 3A through 3D introduce a controlled amount of second order non-linearity to the voltage divider transfer function whereby the second order term opposes the first order linear term. It should be noted that, if desirable, the sign of the second order term may be changed by interchanging the source and drain connections in the configuration shown or by using a p-channel FET. 
     Referring again to FIGS. 3A-3D, if g(v) is the transfer function of resistive dividers 30 and 33, and A is the gain of amplifiers 35 and 36, 
     then ##EQU4## for amplifier 35a and 36a, where ##EQU5## and ##EQU6## for amplifier 35b and 36b where 
     
         g(v)=μ(v+βv.sup.2) 
    
     and generally ##EQU7## 
     There are several constraints on the shaping networks of the present invention. The first is ##EQU8## 
     This constraint is necessary to satisfy the assumptions underlying the series expansions of Exhibit A. 
     
         V.sub.DS &lt;|V.sub.p | 
    
     This is a necessary condition for calculation of the drain current of the FET in the unsaturated region. If V DS  &gt;|V p  |, the FET will saturate. 
     
         V.sub.DS &gt;-0.5 v 
    
     This implies that 
     
         V.sub.DS PK &lt;0.5 v. 
    
     If 
     
         V.sub.DS &gt;-0.5 v, 
    
     the gate-drain junction will be forward biased and gate current will flow. The resultant current flow will dramatically alter the FET transfer function. Thus, this constraint is the most important to observe since |V p  | is usually greater than 0.5 v. 
     EXHIBIT A 
     Referring to FIG. 4, the capacitance, C v , of varactor 44 is given by: ##EQU9## where: C c  =Case capacitance 
     C o  =Junction capacitance at V R  =0 v 
     φ=Junction contact potential 
     σ=Diode power Uw 
     V R  =Diode reverse bias 
     Typically φ≈0.6 v and σ≈0.44. 
     For simplicity, lump C c  in with C p  so that C p  represents the total tank capacitance less the contribution of the varactor junction. The tank resonant frequency is: ##EQU10## Define f o  as the normal osc. frequency, obtained when V R  =V o  ##EQU11## 
     Referring now to FIG. 5, assume modulating signal, v(t), is passed through shaping network, g(v), and summed with tune voltage, V o . 
     Then: ##EQU12## The goal is to remove voltage dependance in (df/dv). Note v=v(t). Thus, let ##EQU13## where β=constant of integration units=Hz ##EQU14## It is desirable that g(v)=0 when v(t)=0. Applying this constraint: ##EQU15## Note that K v  V represents the peak deviation of the modulated oscillator Δf&lt;&lt;f o . ##EQU16## Isolating the term ##EQU17## performing a series expansion and retaining the first three terms of the expansion, ##EQU18## Substituting into g(v): ##EQU19## Previously, ##EQU20## Thus: ##EQU21## The term in brackets is of the form: 
     
         (1+av+bv.sup.2).sup.-1/σ 
    
     where: ##EQU22## Let f(v)=(1+av+bv 2 ) -1/ σ ##EQU23## I shall keep only the first three terms since I am looking for a quadratic approximation. ##EQU24## Previously, it was shown that: ##EQU25## Previously, it was shown that: ##EQU26## Using this result: ##EQU27## This is the required second order shaping. 
     EXHIBIT B 
     Referring to FIG. 6, for a symmetrical junction FET, the most positive junction controls the current flow, I D , in an N-channel device. A quadratic approximation of unsaturated drain current can be derived by assuming the substantially parabolic characteristic curve 70 as shown in FIG. 7. Thus, ##EQU28## Since the same relation describes the behavior of I D  in both quadrants 1 and 3, ##EQU29## For resistive voltage dividers 30, ##EQU30## At this point, note that V p  ≦V GS  ≦0. Therefore, V=V GS  -V p . 0≦V≦-V p   
     Let V=-αV p  ; where 0≦α≦1. Note, α=0 when V GS  =V p , and α=1 when V GS  =0 v. ##EQU31## If V IN  =0, V DS  must =0. V p  &lt;0 and ##EQU32## Therefore, ##EQU33## Since the square root will be positive, the negative radical must be taken. ##EQU34## Assume R&gt;&gt;R ON  : Then the radical becomes: ##EQU35## Perform a series expansion and retain the first three terms. ##EQU36## For this approximation to be valid, ##EQU37## Since a resistive-voltage divider attenuates the input voltage, all input voltages must be pre-amplified by an amount approximately equal to ##EQU38## to restore to the amplitude of the output signal if a post shaping network amplifier is not used. 
     EXHIBIT C 
     For resistive voltage divider 33, ##EQU39## The negative radical must be used so that v DS  =0 v when v IN  =0 v. ##EQU40## The radical has the same form as the radical in equation &#34;K&#34; for resistive voltage divider 30. Therefore, isolating and applying condition &#34;M&#34;, ##EQU41## Remember that ##EQU42## But V p  &lt;0; ##EQU43## If ##EQU44##