Abstract:
A method for tuning spread spread spectrum receivers to a frequency of a digital signal within a specified frequency band as the steps of coarse tuning the receiver while a preamble of the digital signal is being received, fine tuning the receiver while the preamble of the digital signal is being received, and demodulating the signal. Preferably, the step of coarse tuning the receiver comprises dividing the specified frequency band into a plurality of first sub-bands, and sequentially measuring a receive signal strength within each of the sub-bands until a receive signal strength is greater than a predetermined threshold. Preferably, the step of fine tuning the receiver comprises the dividing at least one first step-band which is found to have a receive signal strength greater than a predetermined threshold into a plurality of second sub-bands when a receive signal strength is greater than the predetermined threshold, sequentially measuring a receive signal strength within each sub-band so as to determine which second sub-band contains a signal having a receive signal strength above a predetermined threshold, and determining which second sub-band contained the signal with the greatest receive signal strength.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to digital data communications and more particularly to a method for tuning a spread spectrum receiver to the frequency of a digital signal which is within a specified frequency band. 
     BACKGROUND OF THE INVENTION 
     Spread spectrum digital communications techniques are well known. Such spread spectrum digital communications techniques provide a means for facilitating low power radio communications, increased bandwidth usage, and in many instances provide a low cost means for complying with Federal Communications Commission (FCC) regulations. 
     One such spread spectrum technique is Direct Sequence Spread Spectrum (DSSS) which utilizes burst transmissions. This is a phase modulation technique wherein the transmission phase of the message changes rapidly, perhaps every few microseconds. 
     Generally a communication system is designed so that both transmitter and receiver operate at precisely the same frequency. However, in less expensive systems it may not be possible to fix the frequency accurately enough to permit reception. In this instance, it will be necessary for the receiver to quickly tune to the frequency of the transmitted signal, so as to facilitate the modulation of the message before the transmission burst finishes. 
     In view of the forgoing, it would be desirable to provide a method for tuning a spread spectrum receiver to the frequency of the desired digital signal which is known to be located within a specific frequency band. 
     SUMMARY OF THE INVENTION 
     The present invention specifically addresses and alleviates the above mentioned deficiencies associated with the prior art. More particularly, the present invention provides a method for tuning a spread spectrum receiver to a frequency of a digital signal within a specified frequency band. The method generally comprises the steps of coarse tuning the receiver while a preamble of the digital signal is being received, then fine tuning the receiver while the preamble of the digital signal is still being received, and then demodulating the signal after the frequency thereof has been determined via such coarse and fine tuning. 
     According to the preferred embodiment of the present invention, the step of coarse tuning the receiver comprises dividing the specified frequency band into a plurality of sub-bands, and sequentially measuring a received signal strength within each first sub-band until a received signal strength is greater than a predetermined threshold. 
     According to the preferred embodiment of the present invention, the step of fine tuning the receiver preferably comprises dividing at least one first sub-band which was found above to have a receive signal strength greater than a predetermined value into a plurality of second sub-bands when a receive signal strength is greater than the predetermined threshold. This process is repeated as necessary. Thus, when the first one of the first sub-bands having a receive signal greater than a predetermined threshold is not found to contain the frequency of the digital signal, then the next first sub-band having a receive signal strength greater than the predetermined threshold is divided into second sub-bands. In this manner, each first sub-band is divided into second sub-bands and checked for the frequency of the digital signal until the frequency of the digital signal is found, as discussed in detail below. 
     After a first sub-band has been divided into a plurality of second sub-bands, then the receive signal strength within each second sub-band is sequentially measured so as to determine which second sub-band contains the signal having a receive signal strength above a predetermined threshold. 
     Since, as those skilled in the art will appreciate, a plurality of the second sub-bands may have a receive signal strength greater than the predetermined threshold, according to the present invention that second sub-band which contains the greatest received signal strength is determined to contain the desired frequency of the digital signal. Thus, that second sub-band which has the greatest received signal strength is de-modulated. 
     As discussed above, two different methods are utilized in the selection of the desired first sub-band and the selection of the desired second sub-band. Selection of the desired first sub-band is performed by selecting the first sub-band having a receive signal strength greater than predetermined threshold and then the next first sub-band having a receive signal strength greater than the predetermined threshold is assumed to contain the frequency of the desired frequency of the digital signal. This process is continued until that first sub-band which actually contains the desired frequency of the digital signal is found. 
     By way of contrast, determination of the second sub-band (which is contained within one of the first sub-bands) is performed merely by selecting that second sub-band having the highest received signal strength. While this procedure avoids the interactive process used to determine which second sub-band contains the desired frequency of the digital signal, this simplified procedure can not be utilized efficiently to determine the desired first sub-band, since the greater band width of the set of first sub-bands make it much more likely that an undesirable signal will have a greater amplitude than the desired digital signal, thereby increasing the probability that one of the first sub-bands, other than the desired first sub-band, will contain the highest receive signal strength. That is, the increased band width of the set of first sub-bands makes it likely that selection of the first sub-band by utilizing the greatest signal contained within any of the first sub-bands will provide a false indication. 
     According to the preferred embodiment of the present invention the step of sequentially measuring a receive signal strength within each first sub-band comprises averaging a plurality of separate receive signal strength measurements within each sub-band. 
     According to the preferred embodiment of the present invention, the method for tuning a spread spectrum receiver to a frequency of a digital signal within a specified frequency band further comprises the step of verifying the second sub-band by demodulating at least a portion of the preamble of the digital signal. 
     The step of fine tuning the receiver preferably comprises fine tuning the receiver to within a frequency band which is small enough for an automatic frequency control circuit to pull the frequency of the digital signal within its control. Thus, the automatic frequency control circuit can then pull in and maintain the frequency of the digital signal. 
     The demodulization process preferably comprises demodulating a preamble of the signal in the second sub-band which has the greatest receive signal strength, demodulating frame synchronization data associated with that preamble, demodulating error detection coding associated with that preamble, demodulating a message length associated with that preamble, and finally, demodulating the message itself. 
     Thus, according to the present invention, a method for tuning a spread spectrum receiver to a frequency of a digital signal within a specified frequency band is provided. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a typical burst message structure and algorithm timing according to the present invention; 
     FIG. 2 shows search/coarse tuning method of the present invention wherein the specified frequency band within which the desired frequency of the digital signal is known to be has been divided into a plurality of first sub-bands; 
     FIG. 3 shows the tuning step timing of the present invention; 
     FIG. 4 shows the fine tuning method of the present invention; and 
     FIG. 5 shows a block diagram of the single chip direct sequence spread spectrum receiver of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The detailed description set forth below in connection with the appended drawings is intended as a description of the presently preferred embodiment of the invention, and is not intended to represent the only form in which the present invention may be constructed or utilized. The description sets forth the functions and the sequence of steps for constructing and operating the invention in connection with the illustrated embodiment. It is to be understood, however, that the same or equivalent functions may be accomplished by different embodiments that are also intended to be encompassed within the spirit and scope of the invention. 
     DSSS Receiver for Transmissions at Unknown Frequencies 
     Introduction 
     This description addresses reception of Direct Sequence Spread Spectrum (DSSS) burst transmissions when the transmissions occur at unknown frequencies. The transmission frequency is bounded to a specific bandwidth, but can occur randomly within that bandwidth. Although the transmissions occur at random frequencies, the transmit frequency is relatively constant for an individual burst. 
     Problem Description 
     A DSSS receiver must be tuned within ±Δƒ of a DSSS transmission frequency, ƒ c , to accurately demodulate the transmission. Frequently, Δƒ is one quarter the data rate, ƒ d /4, and represents the maximum frequency deviation from which an Automatic Frequency Control (AFC) loop can tune. If the transmission frequency is unknown at the receiver and is likely to have deviation greater than ±Δƒ from ƒ c , then the receiver must first estimate the transmission frequency and tune to that frequency prior to demodulating the message. In this application, transmitter cost constraints must be evaluated in relation to frequency uncertainty, i.e., likelihood that frequency deviation exceeds ±Δƒ. 
     It is often desirable to minimize the time required to perform the frequency estimate. When the frequency estimate is correctly known, the receive can start decoding the message. Present embodiments of the receiver were capable of accurate frequency estimation in less than 100 ms. 
     Good performance for signals near the theoretical noise floor is desirable to maximize the range coverage of the receiver. Therefore, the frequency estimation should preferably perform well with low signal-to-noise ratios (SNR). 
     In practice, the receiver may be further constrained to operate on post-detection data of uncertain quality. In such cases it may be desirable to buffer the pre-detection sampled data for faster processing approaches. 
     It should be understood that in the embodiment described below the transmitted message formats were known by the receiver. The PN Code was known. Each data bit was modulated by the entire PN Code. 
     Approach 
     Referring now to FIG. 1, typical burst message structure and algorithm timing are shown. The DSSS Receive function is split into two sub functions: the acquisition algorithm and demodulation algorithm. Each of these algorithms is comprised of sub-functions. 
     Acquisition Algorithm 
     The acquisition algorithm scans the environment for burst transmissions that can occur at random frequencies and at random times. It detects any transmission and estimates that transmission&#39;s frequency. False alarms and time spent looking at false alarms are preferably minimized. The algorithm performs detection and frequency estimation with Search/Coarse Tune and Fine Tune functions. 
     Post-detection Received Signal Strength (RSS) data may be used as a discriminant to perform the algorithm. 
     Search/Coarse Tune 
     Referring now to FIG. 2, the search/coarse tune function sweeps across the system frequency bandwidth (BW system ) looking for Received Signal Strength (RSS) above a specified detection threshold. Its objective is signal detection and coarse ƒ c  estimation. The sweep process consists of tuning to a frequency, waiting for a data symbol to be completely received, measuring the RSS value, and then repeating the entire process for the next frequency. FIG. 3 shows the timing for an individual tuning step. 
     In some cases an individual RSS measurement can be uncertain or noisy. Averaging several RSS measurements reduces the standard deviation of the RSS values. The averaging can be performed in two ways: 1) the curve shown in FIG. 2 can be smoothed by averaging adjacent values, and 2) the RSS value certainty at each frequency can also be improved by averaging several measurements at that same frequency. This algorithm employed both techniques. 
     Smoothing the curve highlights the trend of the transmission frequency. It eliminates nulls that may occur close to the actual transmission frequency due to the PN Code correlating poorly at a specific frequency. (In this application the curve was smoothed by sweeping from lower to higher frequency. A fixed length window of the adjacent lower frequency RSS values was used to smooth the current frequency RSS value. This introduced a bias in the coarse frequency estimate that had to be removed prior to proceeding to the Fine Tune stage of the Acquisition algorithm.) 
     Averaging several RSS values at a specific frequency reduces the combined estimate&#39;s RMS error. However, the error is reduced only if the measurements are not correlated. Using RSS measurements from consecutive data symbols is less desirable than using measurements from data symbols that are separated in time, because adjacent data symbols are more likely to be correlated. 
     Fine Tune 
     When a detection is declared in the Search/Coarse Tune function, the receiver proceeds with the Fine Tune function. This function must estimate the transmission frequency, ƒ c , to within ±Δƒ of ƒ c . It performs sweeps over a narrower frequency range than specified in the Search Coarse Tune function. However, its frequency steps are much smaller than those in the Search/Coarse Tune function. 
     FIG. 4 shows how the Fine Tune algorithm focuses on a narrowed frequency sweep about the coarse frequency estimate determined during the Search/Coarse Tune function. The narrowed frequency sweep&#39;s range, ±Δƒ Fine     —     Range , is selected to optimize between maximizing the probability of enclosing the true frequency and minimizing the time spent searching for the true frequency. Widening the range increases the probability of enclosing the true frequency, but increases the search time. 
     The fine tune method performs one sweep over the narrowed frequency range using smaller frequency steps. The frequency steps were selected smaller than f d /2 to assure that at least one frequency step falls within the pull-in range of the DSSS receiver&#39;s AFC loop. A frequency estimate is determined by finding the largest RSS value, if any exist, that crosses a defined threshold. Multiple sweeps are performed to estimate multiple fine frequency estimates, where n is the n th  frequency estimate. These estimates are averaged to obtain a final frequency estimate. Averaging multiple individual estimates improves the accuracy and resolution of the individual estimates. The final frequency estimate can have fractional Fine Tune Frequency Step sizes while the individual estimate&#39;s resolution is limited to the step size. Although the DSSS receiver is able to demodulate any signal that transmits within its frequency pull-in range, its performance worsens as signal frequencies near the limits. Therefore, obtaining resolution finer than the frequency step size is beneficial. 
     Increasing the number of sweeps, which is greater than or equal to the number of estimates, increases the time required for the Fine Tune function. Therefore, the right trade must be made between maximizing frequency accuracy and minimizing function operational time. 
     Demodulation Algorithm 
     When a signal is detected and the transmission frequency estimated, the receiver starts demodulating the transmission. For the receiver to correctly decode the message, the burst transmission must still be in the Preamble (see FIG. 1) part of the burst. The demodulation algorithm must have time to verify the Preamble prior to entering the Frame Sync part of the burst. 
     Verification 
     At this point the frequency should be accurately estimated, but it is still possibly in error. However, the error should be relatively small. The verification function attempts to demodulate at several nearby frequencies before giving up and starting over. It determines whether too many bit errors occur at the first frequency estimate. If too many occur, it tunes to a new frequency that is slightly greater, by Δf Verify , than the original estimate, {circumflex over (f)} c   FINE , and again tries demodulating the Preamble. If too many bit errors occur at the new frequency it tunes to a new frequency Δf Verify  below the original estimate and again tries demodulating the Preamble. If it fails again, it tunes to a new frequency that is 2Δf Verify  greater than the original estimate. It continues trying new frequencies, working away from the original estimate, until either it demodulates the bit stream with few bit errors or it reaches a preset limit for number of re-tunes. If it reaches the present limit for attempts, the receive algorithm reverts back to attempting to acquire a burst. 
     When the receiver is tuned to a frequency where it is able to demodulate Preamble bits with few bit errors, it continues demodulation of the Preamble until the input bits match the Frame Sync. If too many Preamble bits are demodulated, the algorithm fails and reverts to searching for a new burst. 
     Once the Frame Sync is recognized by the algorithm, it aligns the bit retrieval on byte boundaries and signals the algorithm that the following bytes are Message Data bytes. If any bit error occurs in the Frame Sync, the algorithm reverts to searching for a new burst. In this application the Frame Sync was three bytes long. 
     The first piece of information demodulated is the message type and its error code. The algorithm demodulates this information and determines the length of the message being received from a look up table. This information is used by the algorithm to know when to stop demodulating data. If an error occurs in demodulating the message type or its error code, the algorithm fails and reverts to searching for a new burst. 
     If the message type and its error code are correctly demodulated, the algorithm continues demodulating data until the entire message is received. Since this algorithm is implemented in limited hardware, it passes bytes as they are received to another processor for further processing. The limited hardware is unable to store an entire message in its memory. Therefore, error code checking is not performed on the entire message in this algorithm. 
     Appendix A: STEL-2000 Register Programming 
     The STEL-2000 Direct Sequence Spread Spectrum (DSSS) receiver/transmitter chip&#39;s registers must be correctly programmed for a receiver algorithm to function properly. This appendix discusses the programming of the STEL-2000 registers for the application. This discussion assumes some familiarity with the STEL-2000 receiver/transmitter chip. 
     Certain key design parameters must be known to properly program the STEL-2000 for a given application. These parameters and the values applicable for the RF Identification program are listed below. Many other parameters must be known as well. These parameters will simply be indicated by the programming values later. 
     
       
         
               
             
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Key Parameters Required for Proper STEL-2000 Programming 
               
             
          
           
               
                   
                   
                 RF Identification 
               
               
                   
                 Parameter 
                 Project 
               
               
                   
                   
               
               
                   
                 Receiver Bandwidth 
                 1.25 to 5.25 MHz 
               
               
                   
                 A/D Sample Rate 
                 20 MHz 
               
               
                   
                 Peak Input (in LSB) 
                 102 
               
               
                   
                 N o , number of 
                 20 
               
               
                   
                 samples per half PN 
               
               
                   
                 chip 
               
               
                   
                 M, number of PN 
                 15 (60 - in Fine Tune 
               
               
                   
                 chips per data 
                 mode) 
               
               
                   
                 symbol 
               
               
                   
                 PN Sequence (per 
                 110101100100011 LSB   
               
               
                   
                 data bit) 
                 (lsb sent first) 
               
               
                   
                 Preamble Data bit 
                 1000 LSB  (lsb sent 
               
               
                   
                 pattern 
                 first) 
               
               
                   
                   
               
             
          
         
       
     
     Programming the Stel receiver is somewhat tricky. Changing a register&#39;s value early in the block diagram can cause improper operation if the values selected for following registers are not readjusted. Table 2 shows how the register values depend upon one another. The list following the table mentions specifics about each point in the block diagram shown in FIG.  5 . Each letter (e.g., A, B, etc.) represents a point in the block diagram. Note that two sets of numbers may be listed in this table. The two sets reflect the two different length PN Codes that may be used in the acquisition part of the receiver tuning algorithm. 
     
       
         
               
             
               
               
               
               
               
               
               
             
           
               
                 TABLE 2 
               
             
             
               
                   
               
               
                 Stel-2000 Register Value Calculations 
               
             
          
           
               
                 View 
                 Ref. 
                 Value 
                 Value 
                 Value 
                 Con- 
                 Register 
               
               
                 Port 
                 Point 
                 (Expr.) 
                 (Numeric) 
                 (LSBs) 
                 straint 
                 Program 
               
               
                   
               
               
                   
                 V(A) 
                 0.8 x 2 7   
                 0.8 x 2 7   
                 102.4 
                   
                   
               
               
                   
                 V(B) 
                 V(A) x 2 7   
                 0.8 x 2 14   
                 13107.2 
                   
               
               
                   
                 V(C) 
                 V(B) x 2 Log   2   H   
                 0.8 x 2 14+4.32   
                 262144 
                   
                 02 H : 0x13 
               
               
                   
                 V(D) 
                 V(C) x 2 −8   
                 0.8 x 2 6+4.32   
                 1024 
                   
               
               
                 ---&gt; 
                 V(E) 
                 V(D) x 2 
                 2 −0.32+6+4.32-VP _DC = 
                 2(9), 
                 &lt;=3.5 
                 01 H : 0x9?, 
               
               
                   
                   
                 VP_DC 
                 2 1   
                 4(8) 
                 (2 1.81 ) 
                 0x8? would 
               
               
                   
                   
                   
                   
                   
                   
                 cause 
               
               
                   
                   
                   
                   
                   
                   
                 clipping 
               
               
                   
                 V(F) 
                 V(E) x 2 
                 2 1+3.91 ,2 1+5.91   
                 30(15), 
                 M=15, 60 
                 2D H :0x0e, 0x 
               
               
                   
                   
                 Log 2 M 
                   
                 120(60) 
                   
                 3b 
               
               
                   
                 V(G) 
                 V(F) 
                 2 4.91 ,2 6.91   
                 30(15), 
                   
                 29, 2A, 2B, 2C 
               
               
                   
                   
                   
                   
                 120(60) 
                   
                   H :0x20,0x50 
               
               
                 ---&gt; 
                 V(H) 
                 V(G) x 2 −   
                 2 4.91(6.91)-VP _MF 
                 30(15), 
                 &lt;=100 
                 28 H 0x?0 
               
               
                   
                   
                 VP_MP 
                   
                 60(60) 
                 (2 6.64 ) 
                 (15), 0x?1 
               
               
                   
                   
                   
                   
                   
                   
                 (60) 
               
               
                   
                 V(I) 
                 V(H) 2  x 0.6 
                 0.6 x 
                 540(15), 
               
               
                   
                   
                   
                 2 2x4.91(6.91)-0(1)   
                 2160(60) 
               
               
                 ---&gt; 
                 V(J) 
                 V(I) x 2 −   
                 2 −0.74+2x[4.91(6.91)-   
                 67.5(15) 
                 &lt;=128 
                 33 H :0x3? 
               
               
                   
                   
                 VP_AFC 
                 0(1)]-VP_AFC 
                 , 
                 (2 7 ) 
                 (15), 0x5? 
               
               
                   
                   
                   
                   
                 67.5(60) 
                   
                 (60) 
               
               
                   
                 V(K) 
                 V(J) 
                 2 −0.74+2x[4.91(6.91)-   
                 67.5 
                   
                 34 H : 0x0b 
               
               
                   
                   
                   
                 0(1)]-3(5) 
                   
               
               
                   
                 V(L) 
                 K 2  x V(K) 
                 K 2  x 2 −0.74+2x4.91-3   
                 742.5 
               
               
                   
                 V(M) 
                   
               
               
                   
                 V(N) 
                 V(M) 
               
               
                   
                 V(O) 
                 V(N) x 2 −2   
                   
                   
                 &lt;=2 31   
               
               
                   
                 V(P) 
                 V(O) 
               
               
                   
                 V(Q) 
                 V(P) 
               
               
                   
                 V(R) 
                 V(Q) 
               
               
                   
                 V(S) 
                 2 7   
                 2 7   
               
               
                   
               
             
          
         
       
     
     Critical Point Description (FIG.  5 ) 
     A: The A/D accepts input signals with variation of up to +/−0.5V. It converts @20 MHz (40×DSSS Chip Rate, N o =20, 02 H  set to 13 H ). Its output is offset binary (01 H  bit  3  set to 0 H ). 
     C: The number of samples per half chip is set in reg 02 H  to 13 H . 
     E: The Integrate and Dump viewport is set in reg 01 H  bits  7 - 4  to 9x H  (or possibly 8x H ). This is described in the Spread Spectrum Development Kit pgs 66-67. 
     F: The number of chips per data symbol is set in reg 2D H  bits  5 - 0  to 0e H  (for 15 chips per symbol) or to 3b H  (for 60 chips per symbol). 
     G: The detection threshold is set in regs 29 H  and 2A H  to 0e H  (for 15 chips per symbol) or to 0e H  (for 60 chips per symbol). This is described in the Spread Spectrum Development Kit pgs 68-69. 
     H: The Matched Filter viewport is set in reg 28 H  to 00 H  (for 15 chips per symbol) or to 00 H  (for 60 chips per symbol). This is described in Spread Spectrum Development Kit pg 67. 
     J: The AFC viewport is set in reg 33 H  bits  7 - 4  to 0e H  (for 15 chips per symbol) or to 0e H  (for 60 chips per symbol). This is described in Spread Spectrum Development Kit pgs 74-76. 
     L: The K 2  loop gain factor is set in reg 34 H  bits  4 - 0  to 0e H . This is described in the Spread Spectrum Development Kit pgs 78-79. 
     Once the correct values are determined for the Stel receiver, they must be programmed into the Stel&#39;s registers. Table 3 lists the values selected for various modes of the receiver acquisition/demodulation algorithm. Three modes are listed: 1) Search (coarse tune), 2) Fine Tune, and 3) Demodulation. Listed in parenthesis are the values programmed in the Wescorp alpha stage. Just preceding each mode column is a column with ‘x’s, ‘?’s and blank spaces. The rows marked with ‘x’s represent the registers that must be programmed for the given mode (even though others may also be programmed). The ‘?’s may not require programming, but this has not yet been tested. Table 3 STEL-2000 Register Settings (Values in ( ) are from original asm code. The listing is in the order the values should be programmed.) 
     
       
         
               
               
               
               
               
             
           
               
                 TABLE 3 
               
               
                   
               
               
                   
                   
                 Fine 
                   
                   
               
               
                 Register 
                 Search 
                 Tune* 
                 Demod** 
                 Description 
               
               
                   
               
             
             
               
                 37 H   
                 x 03 H   
                 x 00H 
                 x 00 H   
                 Bit 0-NCO Enable 
               
               
                   
                 (00 H ) 
                   
                   
                 Bit l-Transmitter Enable 
               
               
                   
                   
                 (00 H ) 
                   
                 Bit 2-Receiver Enable 
               
               
                 37 H *** 
                 x 07 H   
                 x 07 H   
                 x 03 H   
               
               
                   
                 (05 H ) 
                   
                 (07 H ) 
               
               
                   
                   
                 (05 H ) 
                   
                 Downconverter Registers 
               
               
                 00 H   
                 00 H   
                 x 00 H   
                 00 H   
                 Bit 0 - Frequency Control Word 
               
               
                   
                 (00 H ) 
                   
                 (00 H ) 
                 Load 
               
               
                 01 H   
                 x 80 H   
                 (00 H ) 
                 x 80 H   
                 (Rising edge loads word.) 
               
               
                   
                 (80 H ) 
                 x 80 H   
                 (80 H ) 
               
               
                   
                   
                   
                   
                 Bit 0 - Manual Sample Control 
               
               
                   
                   
                 (80 H ) 
                   
                 Bit 1 - Invert Loop Filter Value 
               
               
                   
                   
                   
                   
                 Bit 2 - NCO Accumulator Carry 
               
               
                   
                   
                   
                   
                 In 
               
               
                   
                   
                   
                   
                 Bit 3 - Two&#39;s Complement 
               
               
                   
                   
                   
                   
                 Input 
               
               
                   
                   
                   
                   
                 Bits 7-4 - Integrate and Dump 
               
               
                   
                   
                   
                   
                 VP Control 
               
               
                   
                   
                   
                   
                 Bits 5-0 - Receiver Baseband 
               
               
                   
                   
                   
                   
                 Sampling 
               
               
                 02 H   
                 x 13 H   
                 x 13 H   
                 x 13 H   
               
               
                   
                 (13 H ) 
                   
                 (13 H ) 
                 Bits 7-0-NCO FCW Word 
               
               
                 03 H   
                 00 H   
                 (13 H ) 
                 00 H   
               
               
                   
                 (00 H ) 
                 00 H   
                 (00 H ) 
               
               
                   
                   
                 (00 H ) 
               
               
                 4 H   
                 00 H   
                 00 H   
                 00 H   
                 Bits 15-8-NCO FCW Word 
               
               
                   
                 (00 H ) 
                   
                 (00 H ) 
               
               
                 05 H   
                 00 H   
                 (00 H ) 
                 00 H   
                 Bits 23-16-NCO FCW Word 
               
               
                   
                 (00 H ) 
                 00 H   
                 (00 H ) 
               
               
                 06 H   
                 00 H   
                   
                 00 H   
                 Bits 31-24-NCO FCW Word 
               
               
                   
                 (00 H ) 
                 (00 H ) 
                 (00 H ) 
               
               
                   
                   
                 00 H   
               
               
                   
                   
                   
                   
                 PN Matched Filter Registers 
               
               
                   
                   
                 (00 H ) 
                   
                 Tap Bits 1,0     Tap Coef 
               
               
                   
                   
                   
                   
                 x 0                   0 
               
               
                   
                   
                   
                   
                 0 1                   + 1 
               
               
                   
                   
                   
                   
                 1 1                   − 1 
               
               
                   
                   
                   
                   
                 Addr 07 H   - 16 H   are 
               
               
                   
                   
                   
                   
                 Acq/Preamble Coef 
               
               
                   
                   
                   
                   
                 Addr 16 H   
               
               
                   
                   
                   
                   
                 Bits 7,6 - Coef 63: Bits 5,4 - 
               
               
                   
                   
                   
                   
                 Coef 62; 
               
               
                   
                   
                   
                   
                 Bits 3,2 - Coef 61; Bits 1,0 - 
               
               
                   
                   
                   
                   
                 Coef 60; 
               
               
                   
                   
                   
                   
                 . . .  
               
               
                   
                   
                   
                   
                 Addr 07 H   
               
               
                   
                   
                   
                   
                 Bits 7,6 - Coef3;Bits 5,4 - Coef 
               
               
                   
                   
                   
                   
                 2; 
               
               
                   
                   
                   
                   
                 Bits 3,2-Coef 1; Bits 1,0 - Coef 
               
               
                   
                   
                   
                   
                 0; 
               
               
                 07 H   
                 x 75 H   
                 x DF H   
                 x 75 H   
               
               
                   
                 (75 H ) 
                   
                 (DF H ) 
               
               
                 08 H   
                 x D7 H   
                 (DF H ) 
                 x D7 H   
               
               
                   
                 (D7 H ) 
                 x 7D H   
                 (7D H ) 
               
               
                 09 H   
                 x F7 H   
                   
                 x F7 H   
               
               
                   
                 (F7 H ) 
                 (7D H ) 
                 (5D H ) 
               
               
                 0A H   
                 x 17 H   
                 x 5D H   
                 x 17 H   
               
               
                   
                 (17 H ) 
                   
                 (FD H ) 
               
               
                 0B H   
                 x 00 H   
                 (5D H ) 
                 x 00 H   
               
               
                   
                 (00 H ) 
                 x FD H   
                 (77 H ) 
               
               
                 0C H   
                 x 00 H   
                   
                 x 00 H   
               
               
                   
                 (00 H ) 
                 (FD H ) 
                 (5F H ) 
               
               
                 0D H   
                 x 00 H   
                 x 77 H   
                 x 00 H   
               
               
                   
                 (00 H ) 
                   
                 (57 H ) 
               
               
                 0E H   
                 x 00 H   
                 (77 H ) 
                 x 00 H   
               
               
                   
                 (00 H ) 
                 x 5F H   
                 (FF H ) 
               
               
                 0F H   
                 x 00 H   
                   
                 x 00 H   
               
               
                   
                 (00 H ) 
                 (5F H ) 
                 (DD H ) 
               
               
                 10 H   
                 x 00 H   
                 x 57 H   
                 x 00 H   
               
               
                   
                 (00 H ) 
                   
                 (D7 H ) 
               
               
                 11 H   
                 x 00 H   
                 (57 H ) 
                 x 00 H   
               
               
                   
                 (00 H ) 
                 x FF H   
                 (D5 H ) 
               
               
                 12 H   
                 x 00 H   
                   
                 x 00 H   
               
               
                   
                 (00 H ) 
                 (FF H ) 
                 (D7 H ) 
               
               
                 13 H   
                 x 00 H   
                 x DD H   
                 x 00 H   
               
               
                   
                 (00 H ) 
                   
                 (5D H ) 
               
               
                 14 H   
                 x 00 H   
                 (DD H ) 
                 x 00 H   
               
               
                   
                 (00 H ) 
                 x D7 H   
                 (DF H ) 
               
               
                 15 H   
                 x 00 H   
                   
                 x 00 H   
               
               
                   
                 (00 H ) 
                 (D7 H ) 
                 (5F H ) 
               
               
                 16 H   
                 x 00 H   
                 x D5 H   
                 x 00 H   
               
               
                   
                 (00 H ) 
                   
                 (00 H ) 
               
               
                   
                   
                 (D5 H ) 
               
               
                   
                   
                 x D7 H   
               
               
                   
                   
                 (D7 H ) 
               
               
                   
                   
                 x 5D H   
               
               
                   
                   
                 (5D H ) 
               
               
                   
                   
                 x DF H   
                   
                 Addr 17 H   -  26 H   are Data Coef 
               
               
                   
                   
                   
                   
                 Addr 26 H   
               
               
                   
                   
                 (DF H ) 
                   
                 Bits 7,6 - Coef 63;  Bits 5,4 - 
               
               
                   
                   
                 x 5F H   
                   
                 Coef 62; 
               
               
                   
                   
                   
                   
                 Bits 3,2  - Coef 61;  Bits 1,0 - 
               
               
                   
                   
                 (5F H ) 
                   
                 Coef 60; 
               
               
                   
                   
                 00 H   
                   
                 . . .  
               
               
                   
                   
                   
                   
                 Addr 17 H   
               
               
                   
                   
                 (00 H ) 
                   
                 Bits 7,6  - Coef3; Bits 5,4- 
               
               
                   
                   
                   
                   
                 Coef2; 
               
               
                   
                   
                   
                   
                 Bits 3,2  - Coef1; Bits 1,0- 
               
               
                   
                   
                   
                   
                 Coef0; 
               
               
                 17 H   
                 x 75 H   
                 DF H   
                 x 75 H   
               
               
                   
                 (75 H ) 
                   
                 (75 H ) 
               
               
                 18 H   
                 x D7 H   
                 (DF H ) 
                 x D7 H   
               
               
                   
                 (D7 H ) 
                 7D H   
                 (D7 H ) 
               
               
                 19 H   
                 x F7 H   
                   
                 x F7 H   
               
               
                   
                 (F7 H ) 
                 (7D H ) 
                 (F7 H ) 
               
               
                 1A H   
                 x 17 H   
                 5D H   
                 x 17 H   
               
               
                   
                 (17 H ) 
                   
                 (17 H ) 
               
               
                 1B H   
                 x 00 H   
                 (5D H ) 
                 x 00 H   
               
               
                   
                 (00 H ) 
                 FD H   
                 (00 H ) 
               
               
                 1C H   
                 x 00 H   
                   
                 x 00 H   
               
               
                   
                 (00 H ) 
                 (FD H ) 
                 (00 H ) 
               
               
                 1D H   
                 x 00 H   
                 77 H   
                 x 00 H   
               
               
                   
                 (00 H ) 
                   
                 (00 H ) 
               
               
                 1E H   
                 x 00 H   
                 (77 H ) 
                 x 00 H   
               
               
                   
                 (00 H ) 
                 5F H   
                 (00 H ) 
               
               
                 1F H   
                 x 00 H   
                   
                 x 00 H   
               
               
                   
                 (00 H ) 
                 (5F H ) 
                 (00 H ) 
               
               
                 20 H   
                 x 00 H   
                 57 H   
                 x 00 H   
               
               
                   
                 (00 H ) 
                   
                 (00 H ) 
               
               
                 21 H   
                 x 00 H   
                 (57 H ) 
                 x 00 H   
               
               
                   
                 (00 H ) 
                 FF H   
                 (00 H ) 
               
               
                 22 H   
                 x 00 H   
                   
                 x 00 H   
               
               
                   
                 (00 H ) 
                 (FF H ) 
                 (00 H ) 
               
               
                 23 H   
                 x 00 H   
                 DD H   
                 x 00 H   
               
               
                   
                 (00 H ) 
                   
                 (00 H ) 
               
               
                 24 H   
                 x 00 H   
                 (DD H ) 
                 x 00 H   
               
               
                   
                 (00 H ) 
                 D7 H   
                 (00 H ) 
               
               
                 25 H   
                 x 00 H   
                   
                 x 00 H   
               
               
                   
                 (00 H ) 
                 (D7 H ) 
                 (00 H ) 
               
               
                 26 H   
                 x 00 H   
                 D5 H   
                 x 00 H   
               
               
                   
                 (00 H ) 
                   
                 (00 H ) 
                 Bit 0 - Front End Processor 
               
               
                 27 H   
                 x 00 H   
                 (D5 H ) 
                 x 00 H   
                 Disable 
               
               
                   
                 (00 H ) 
                 D7 H   
                 (00 H ) 
               
               
                 28 H   
                 x 00 H   
                 (D7 H ) 
                 x 00 H   
                 Power Estimator Registers 
               
               
                   
                 (00 H ) 
                 5D H   
                 (00 H ) 
                 Bits 1-0  - Matched Filter VP 
               
               
                   
                   
                   
                   
                 Control 
               
               
                 29 H   
                 x 20 H   
                 (5D H ) 
                 x 24 H   
               
               
                   
                 (30 H ) 
                 DF H   
                 (80 H ) 
                 Acquisition and Tracking 
               
               
                 2A H   
                 x 00 H   
                   
                 x 00 H   
                 Processor Registers 
               
               
                   
                 (00 H ) 
                 (DF H ) 
                 (00 H ) 
               
               
                 2B H   
                 x 20 H   
                 5F H   
                 x 20 H   
                 Bits 7-0 - Acq/Preamble Thres 
               
               
                   
                 (30 H ) 
                   
                 (08 H ) 
                 bits 7-0 
               
               
                 2C H   
                 x 00 H   
                 (5F H ) 
                 x 00 H   
               
               
                   
                 (00 H ) 
                 00 H   
                 (00 H ) 
               
               
                 2D H   
                 x 0E H   
                   
                 x 0E H   
                 Bits 1-0 - Acq/Preamble Thres 
               
               
                   
                 (0E H ) 
                 (00 H ) 
                 (0E H ) 
                 bits 9-8 
               
               
                 2E H   
                 x 4C H   
                 x 00 H   
                 x 03 H   
               
               
                   
                 (4C H ) 
                   
                 (4C H ) 
               
               
                 2F H   
                 x FF H   
                 (00 H ) 
                 x 08 H   
                 Bits 7-0 - Data Symbol Thres 
               
               
                   
                 (FF H ) 
                   
                 (FF H ) 
                 bits 7-0 
               
               
                 30 H   
                 x 60 H   
                 00 H   
                 x 44 H   
               
               
                   
                 (60 H ) 
                   
                 (60 H ) 
                 Bits 1-0 - Data Symbol Thres 
               
               
                   
                   
                 (00 H ) 
                   
                 bits 9-8 
               
               
                   
                   
                 x 80 H   
                   
                 Bits 5-0 - Rx Chips per Data 
               
               
                   
                   
                   
                   
                 Symbol +1 
               
               
                   
                   
                 (80 H ) 
               
               
                   
                   
                 x 00 H   
                   
                 Receiver Data Symbols per 
               
               
                   
                   
                   
                   
                 Burst Threshold 
               
               
                   
                   
                 (00 H ) 
               
               
                   
                   
                 80 H   
               
               
                 31 H   
                 x 00 H   
                 x 00 H   
                 x 00 H   
               
               
                   
                 (00 H ) 
                   
                 (00 H ) 
               
               
                 32 H   
                 x 00 H   
                 (00 H ) 
                 x 00 H   
                 Bit 0 - Receiver Manual Abort 
               
               
                   
                 (00 H ) 
                 x 00 H   
                 (00 H ) 
               
               
                   
                   
                 (00 H ) 
                   
                 Demodulator Registers 
               
               
                 33 H   
                 x 10 H   
                   
                 00 H   
                 Bits 1-0-Signal Rotation Control 
               
               
                   
                 (10 H ) 
                   
                 (00 H ) 
                 Bit 2-Not used (must be set to 
               
               
                   
                   
                 20 H   
                   
                 0) 
               
               
                 34 H   
                 x 00 H   
                   
                 x 68 H   
                 Bit 3- Loop Clear Disable 
               
               
                   
                 (00 H ) 
                 (40 H ) 
                 (2B H ) 
                 Bits 7-4-AFC VP Control 
               
               
                   
                   
                   
                   
                 Bits 4-0-K2 Gain Value 
               
               
                 35 H   
                 x 00 H   
                 00 H   
                 00 H   
                 Bit 5 - K2 On 
               
               
                   
                 (00 H ) 
                   
                 (00 H ) 
                 Bit 6-Freeze Loop 
               
               
                   
                   
                 (00 H ) 
                   
                 Output Processor Control 
               
               
                 36 H   
                 x 02 H   
                 00 H   
                 02 H   
                 Registers 
               
               
                   
                 (02 H ) 
                   
                 (02 H ) 
                 Bit 0 - Reverse I and Q 
               
               
                   
                   
                 (00 H ) 
                   
                 Bit 1 - BPSK Enable 
               
               
                 38 H   
                 x 01 H   
                   
                 x 01 H   
                 Bit 2 - Invert Output 
               
               
                   
                 (01 H ) 
                   
                 (01 H ) 
                 Bits 3-0 - RXTEST Function 
               
               
                 39 H   
                 x 00 H   
                 02 H   
                 x 7C H   
                 Select 
               
               
                   
                 (00 H ) 
                   
                 (00 H ) 
               
               
                 3A H   
                 x 00 H   
                 (02 H ) 
                 x 00 H   
               
               
                   
                 (1D H ) 
                   
                 (1D H ) 
                 Bits 6-0 - Matched Filter Power 
               
               
                 3B H   
                 x 00 H   
                 x 01 H   
                 x 00 H   
                 Saver 
               
               
                   
                 (00 H ) 
                   
                 (00 H ) 
               
               
                   
                   
                 (01 H ) 
               
               
                   
                   
                 x 00 H   
                   
                 Receiver Data Symbols per 
               
               
                   
                   
                 (00 H ) 
                   
                 Burst (bits 15-8) 
               
               
                   
                   
                 1D H   
               
               
                   
                   
                 (1D H ) 
                   
                 Bit 0 - Matched Filter Loopback 
               
               
                   
                   
                 x 00 H   
                   
                 Enable 
               
               
                   
                   
                   
                   
                 Bit 1 - IF Loopback Enable 
               
               
                   
                   
                 (00 H ) 
                   
                 Bit 3-2 - Receiver Overlay 
               
               
                   
                   
                   
                   
                 Select 
               
               
                   
                   
                   
                   
                 Addr 3 C H   thru 3F H   unused 
               
               
                   
                   
                   
                   
                 Transmit Control Register 
               
               
                 40 H   
                 x 03 H   
                 03 H   
                 x 03 H   
                 Bit 0 - Transmit BPSK 
               
               
                   
                 (03 H ) 
                   
                 (03 H ) 
                 Bit 1 - Offset Binary Output 
               
               
                   
                   
                 (03 H ) 
                   
                 Bit 2 - Manual Chip Clock 
               
               
                   
                   
                   
                   
                 Enable 
               
               
                   
                   
                   
                   
                 Bit 3 - Invert Symbol 
               
               
                   
                   
                   
                   
                 Bits 5-0 - TXIFCLK Cycles per 
               
               
                 41 H   
                 x 3F H   
                   
                 x 3F H   
                 Chip 
               
               
                   
                 (3F H ) 
                 3F H   
                 (3F H ) 
               
               
                 42 H   
                 x 0E H   
                   
                 x 0E H   
               
               
                   
                 (0E H ) 
                 (3F H ) 
                 (0E H ) 
                 Bits 5-0-Tx Chips per Data 
               
               
                 43 H   
                 x 0E H   
                 0E H   
                 x 0E H   
                 Symbol 
               
               
                   
                 (0E H ) 
                   
                 (0E H ) 
               
               
                   
                   
                 (0E H ) 
                   
                 Bits 5-0-Tx Chips per 
               
               
                   
                   
                 0E H   
                   
                 Acq/Preamble 
               
               
                   
                   
                 (0E H ) 
               
               
                   
                   
                   
                   
                 Addr 44 H -4B H   are Transmitter 
               
               
                   
                   
                   
                   
                 Acq/Preamble 
               
               
                   
                   
                   
                   
                 Symbol Code 
               
               
                   
                   
                   
                   
                 Addr 4B H   
               
               
                   
                   
                   
                   
                 Bits 7-0 - Code bits 63-56 
               
               
                   
                   
                   
                   
                 . . .  
               
               
                   
                   
                   
                   
                 Addr 44 H   
               
               
                   
                   
                   
                   
                 Bits 7-0 - Code bits 7-0 
               
               
                 4C H   
                 x 00 H   
                 00 H   
                 x 00 H   
               
               
                   
                 (00 H ) 
                   
                 (00 H ) 
               
               
                 4D H   
                 x 00 H   
                 (00 H ) 
                 x 00 H   
               
               
                   
                 (00 H ) 
                 00 H   
                 (00 H ) 
               
               
                 4E H   
                 x 00 H   
                   
                 x 00 H   
               
               
                   
                 (00 H ) 
                 (00 H ) 
                 (00 H ) 
               
               
                 4F H   
                 x 00 H   
                 00 H   
                 x 00 H   
               
               
                   
                 (00 H ) 
                   
                 (00 H ) 
               
               
                 50 H   
                 x 00 H   
                 (00 H ) 
                 x 00 H   
               
               
                   
                 (00 H ) 
                 00 H   
                 (00 H ) 
               
               
                 51 H   
                 x 00 H   
                   
                 x 00 H   
               
               
                   
                 (00 H ) 
                 (00 H ) 
                 (00 H ) 
               
               
                 52 H   
                 x 00 H   
                 00 H   
                 x 00 H   
               
               
                   
                 (00 H ) 
                   
                 (00 H ) 
               
               
                 53 H   
                 x 00 H   
                 (00 H ) 
                 x 00 H   
               
               
                   
                 (00 H ) 
                 00 H   
                 (00 H ) 
               
               
                 54 H   
                 x 00 H   
                   
                 x 00 H   
               
               
                   
                 (00 H ) 
                 (00 H ) 
                 (00 H ) 
               
               
                 55 H   
                 x 00 H   
                 00 H   
                 x 00 H   
               
               
                   
                 (00 H ) 
                   
                 (00 H ) 
                 Bits 1-0 - Transmitter Overlay 
               
               
                 56 H   
                 x 00 H   
                 (00 H ) 
                 x 00 H   
                 Select 
               
               
                   
                 (00 H ) 
                 00 H   
                 (00 H ) 
                 Bit 2 - Transmitter Symbols Per 
               
               
                   
                   
                   
                   
                 Burst off 
               
               
                   
                   
                 (00 H ) 
                   
                 (Must always be set to 0) 
               
               
                   
                   
                 00 H   
                   
                 Transmitter Data Symbols per 
               
               
                   
                   
                   
                   
                 Burst (bits 7-0) 
               
               
                   
                   
                 (00 H ) 
                   
                 Transmitter Data Symbols per 
               
               
                   
                   
                 00 H   
                   
                 Burst (bits 15-8) 
               
               
                   
                   
                 (00 H ) 
               
               
                   
                   
                 00 H   
               
               
                   
                   
                 (00 H ) 
               
               
                   
               
               
                 *See section on programming PN Code. [Note: Although still listed here, the Fine Tune no longer requires separate STEL-2000 register programming it no longer uses a different PN Code from the other modes.] 
               
               
                 **The register programming for the Demod mode must be immediately followed with the following additional sequence { (0x37,0x07), wait 200 μs, (0x30,0x60 - permit transition from acquisition to demodulation), wait 200 μs, (0x30,0x04 - permit resets on too many errors), wait 200 μs, (0x30,0x60 - disable resets) } 
               
               
                 ***Although this register is programmed to enable the transmit section of the STEL-2000, disabling the transmit section has been noted to reduce the receiver&#39;s noise floor ˜5 dB. This should be investigated further if additional sensitivity is desired.  
               
             
          
         
       
     
     Whenever the Stel is tuned to a new frequency, a sequence of registers must be programmed. Table 4 describes the sequence that is used. 
     
       
         
               
             
               
               
               
               
             
           
               
                 TABLE 4 
               
             
             
               
                   
               
               
                 STEL-2000 Register Settings Sequence for Tuning 
               
             
          
           
               
                   
                 Register 
                 Search 
                 Description 
               
               
                   
                   
               
               
                   
                 05 H   
                 freq_low_byte 
                 Bits 23-16 - NCO FCW Word 
               
               
                   
                 06 H   
                 freq_high_byte 
                 Bits 31-24 - NCO FCW Word 
               
               
                   
                 00 H   
                 01 H  (01 H ) 
                 Bit 0 - Frequency Control 
               
               
                   
                   
                   
                 Word Load 
               
               
                   
                   
                   
                 (Rising edge loads word.) 
               
               
                   
                 00 H   
                 00 H  (00 H ) 
                 Bit 0 - Frequency Control 
               
               
                   
                   
                   
                 Word Load 
               
               
                   
                   
                   
                 (Rising edge loads word.) 
               
               
                   
                 32 H   
                 01 H  (01 H ) 
                 Bit 0 - Receiver Manual 
               
               
                   
                   
                   
                 Abort 
               
               
                   
                 32 H   
                 00 H  (00 H ) 
                 Bit 0 - Receiver Manual 
               
               
                   
                   
                   
                 Abort 
               
               
                   
                   
               
             
          
         
       
     
     Programming PN Code 
     [Note: The Fine Tune mode no longer uses a different PN Code from that of the other modes.] 
     The PN code programming is somewhat tricky. The following description is based on the Z2000 Spread-Spectrum Transceiver Data Book pgs 1-11, 1-24 &amp; 25, and 1-35. It is also based on measurements made on the data stream. It is assumed that Tap  0  in FIG. 3 pg 1-11 of the data book is the same as Coeff  0  in Table 9 pg 1-24 of the data book. (From data book pg 1-35: Tap  0  is played last.) Then the following tables can be generated, where Table 5 describes how the register values are generated for the Search and Demodulation modes and Table 6 describes how the register values are generated for the Fine Tune mode. 
     
       
         
               
             
               
               
               
             
               
               
             
               
               
               
               
             
           
               
                 TABLE 5 
               
             
             
               
                   
               
               
                 STEL-2000 Register PN Code Settings for Coarse Tune 
               
             
          
           
               
                 Time 
                 First 
                            Last 
               
               
                   
               
             
          
           
               
                 Preamble 
                 1 
               
             
          
           
               
                   
                 x 
                   
                   
               
               
                 Seq. 
                   
                 xx 
                 110001001101011 
               
               
                 PN Seq. 
                   
                 0 
                 1 1-1-1-1 1-1-1 1 1-1 1-1 1 1 
               
               
                 (0, 1) 
               
               
                 PN Seq. 
                   
                 00 
                 0101111111011111010111011101110101 
               
               
                 (−1, 1) 
               
               
                 PN 
                   
                 1 
                 7  F  7  D  7  7  5 
               
               
                 Filter 
               
               
                 Tap Bits 
                   
                 17 
                    F7   D7   75 
               
               
                 Nibble 
               
               
                 Values 
                   
                 0A 
                    09   08   07 
               
               
                 Reg. 
               
               
                 Byte 
               
               
                 Values 
                   
                 15 
                 −12  11-8   7-4   3-0 
               
               
                 Register 
               
               
                 Address 
               
               
                 Coeff 
               
               
                   
               
             
          
         
       
     
     
       
         
               
             
               
               
               
             
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 6 
               
               
                   
               
               
                 STEL-2000 Register PN Code Settings for Fine Tune 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 TIME 
                 FIRST 
                 LAST 
               
             
          
           
               
                 Preamble 
                 0 
                 0 
                 0 
                 1 
               
               
                 Seq. 
               
               
                 PN Seq. 
                  0 0 1 1 1 0 1 1 
                  0 0 1 1 1 0 1 
                  0 0 1 1 1 0 1 
                  1 1 0 0 0 1 0 
               
               
                 (0, 1) 
                 0 0 1 0 1 0 0 
                 1 0 0 1 0 1 0 0 
                 1 0 0 1 0 1 0 0 
                 0 1 1 0 1 0 1 1 
               
               
                 PN Seq. 
                 −1−1 1 1 1−1 1 
                 −1−1 1−1 1−1−1 
                 −1−1 1 1 1−1 1 
                 1 1−1−1−1 1−1− 
               
               
                 (−1,1) 
                 1−1−1 1−1 1−1−1 
                 1 1−1 1 1 1−1−1 
                 1−1−1 1−1 1−1−1 
                 1 1 1−1 1−1 1 1 
               
               
                 PN 
                 1111010101110101 
                 111101010111010 
                 111101010111010 
                 010111111101111 
               
               
                 Filter 
                 11110111011111 
                 111110111011111 
                 111110111011111 
                 101011101110101 
               
               
                 Tap Bits 
               
             
          
           
               
                 Nibble 
                 F 
                 5 
                 7 
                 5 
                 D 
                 5 
                 D 
                 7 
                 F 
                 5 
                 7 
                 5 
                 7 
                 F 
                 7 
                 D 
               
             
          
           
               
                 Values 
                 F 
                 7 
                 7 
                 F 
                 D 
                 D 
                 F 
                 F 
                 7 
                 7 
                 D 
                 7 
                 7 
                 5 
               
             
          
           
               
                 Reg. 
                 F5 
                 75 
                 D5 
                 D7 
                 57 
                 5F 
                 F7 
               
             
          
           
               
                 Byte 
                 F7 
                 7F 
                 DD 
                 FF 
                 77 
                 D7 
                 D7 
                 75 
               
               
                 Values 
               
             
          
           
               
                 Register 
                 15 
                 14 
                 11 
                 10 
                 0D 
                 0C 
                 09 
               
             
          
           
               
                 Address 
                 13 
                 12 
                 OF 
                 OE 
                 OB 
                 OA 
                 08 
                 07 
               
             
          
           
               
                 Coeff 
                 59-56 
                 55-52 
                 43-40 
                 39-36 
                 28 
                 27-24 
                 23- 
                 −12 
                 11-8 
               
             
          
           
               
                   
                 51-48 
                 47-44 
                 35-32 
                 31- 
                 20 
                 19-16 
                 15 
                 7-4 
                 3-0 
               
               
                   
                   
               
             
          
         
       
     
     It is understood that the exemplary method for tuning a spread spectrum receiver described herein and shown in the drawings represents only a presently preferred embodiment of the invention. Indeed, various modifications and additions may be made to such embodiment without departing from the spirit and scope of the invention. Thus, various modifications and additions may be obvious to those skilled in the art and may be implemented to adapt the present invention for use in a variety of different applications.