Abstract:
The balanced output signal generator uses four interconnected plus-type second-generation current conveyors, a couple of load resistors and a single input resistor that can provide both current- and voltage-mode outputs. No matching conditions are required.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to signal generators, and particularly to a balanced output signal generator. 
     2. Description of the Related Art 
     Balanced-output-signal generators are widely used in many applications, such as the transmission of analog signals over long wires in order to reject unwanted common mode signals, in synchronous detection, and in lock-in-based systems. This justifies the numerous attempts reported in the literature to design such generators using operational amplifiers and plus-type second-generation current-conveyors (CCII+). However, most of the available circuits suffer from one or more disadvantages, such as requiring extensive matching conditions between active and passive elements in order to achieve high common-mode rejection ratio. The use of operational amplifiers, with their finite values of gain-bandwidth products, limits the frequency range of operation, resulting in narrowband balanced-output-signal generators and the use of two different types of active elements. 
     Thus, a balanced output signal generator solving the aforementioned problems is desired. 
     SUMMARY OF THE INVENTION 
     The balanced output signal generator uses four interconnected plus-type second-generation current conveyors, a couple of load resistors, and a single input resistor that can provide both current- and voltage-mode outputs. No matching conditions are required. 
     These and other features of the present invention will become readily apparent upon further review of the following specification and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
       The sole drawing Figure is a schematic diagram of a balanced output signal generator circuit according to the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The balanced output signal generator  10  shown in the drawing includes four CCII+ monolithic integrated circuits  12   a,    12   b,    12   c,  and  12   d.  Details and theory of operation of an exemplary CCII similar to CCII+  12   a,    12   b,    12   c,  and  12   d,  are included in U.S. Pat. No. 3,619,798, issued on Nov. 9, 1971, which is hereby incorporated by reference in its entirety. The CCII+/1  12   a  and CCII+/2  12   b  will force the voltage difference across the resistance R  19  to be equal to (V in1 −V in2 ). Thus, the current through this resistance will be (V in1 −V in2 )/R. With terminal Z of CCII+/1  12   a  connected to terminal Y of CCII+/3  12   c,  the current through terminal Z of CCII+/1  12   a  will be forced to zero. Thus, the current through terminal X of CCII+/1  12   a  will be forced to zero. Similar arguments apply to the currents in terminals Z and X of CCII+/2  12   b.  Thus, the current through terminals X of CCII+/3  12   c  and CCII+/4  12   d  will be forced to be equal to (V in1 −V in2 )/R. This current will produce an outward current through terminal Z of CCII+/3  12   c  and an inward current through terminal Z of CCII+/4  12   d.  Thus, the output currents will be given by: 
     
       
         
           
             
               
                 
                   
                     
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     Equations (1) and (2) represent the output currents of a current-mode balanced output signal generator. Moreover, if output voltages are required, then by connecting the resistors R L    18 , the output voltages will be given by: 
                       V     out   ⁢           ⁢   1       =         R   L     R     ⁢     (       V     in   ⁢           ⁢   1       -     V     in   ⁢           ⁢   2         )         ⁢     
     ⁢   and           (   3   )                 V     out   ⁢           ⁢   2       =       -       R   L     R       ⁢     (       V     in   ⁢           ⁢   1       -     V     in   ⁢           ⁢   2         )               (   4   )               
Equations (3) and (4) represent the outputs of a voltage-mode balanced output signal generator.
 
     A new CCII+ based balanced-output-signal generator  10  has been disclosed. The circuit can be easily implemented using off-the-shelf components, including four AD844 CCH+ integrated circuits and one input resistor  19 . The circuit can provide both current- and voltage-mode outputs. 
     It is to be understood that the present invention is not limited to the embodiments described above, but encompasses any and all embodiments within the scope of the following claims.