Abstract:
A current limiting circuit capable of increasing a range of applicable load values is disclosed. An output circuit ( 100 ) may include a current limiting circuit. A current limiting circuit may include a voltage detecting circuit ( 1 ) and a voltage clamping circuit ( 2 ). A voltage detecting circuit ( 1 ) may detect a plurality of output voltages (Vout). Voltage clamping circuit ( 2 ) may clamp a control terminal of an output transistor (M 1 ) to a plurality of clamped voltages in response to the plurality of detected output voltages (Vout). In this way, an output transistor (M 1 ) may have a plurality of current limitation values as an output voltage (Vout) changes. By doing so, an output circuit ( 100 ) may be applicable to a multitude of load (LOAD) values and properly operate without risks of overcurrent or undesired quiescent operating states being entered, as just two examples.

Description:
TECHNICAL FIELD 
     The present invention relates generally a current limiting circuit, and more particularly to a current limiting circuit for preventing an overcurrent from flowing through an output transistor. 
     BACKGROUND OF THE INVENTION 
     A number of methods can be used for a current limiting circuit in which a power MOS (metal-oxide-semiconductor) transistor is used as an output transistor. In one method, a Zener diode is connected to a gate-source voltage to control a current of an output transistor by limiting the gate-source voltage to the Zener voltage. In another method, several diodes are connected to a gate-source voltage to control a current of an output transistor using the cumulative forward voltages of the diodes as a clamp. In yet another method, such voltage control is carried out using a voltage clamping circuit, or the like. 
     Referring to  FIG. 5 , a circuit schematic diagram of an output circuit including a conventional current limiting circuit is set forth and given the general reference character  500 . In  FIG. 5 , a conventional current limiting circuit includes a voltage detecting circuit  501  and a current limiting portion  502 . 
     Voltage detecting circuit  501  includes MOS transistors (M 52 , M 53 , and M 54 ) and resistors (R 55 , R 56 , R 58 , and R 59 ). Voltage detecting circuit  501  monitors an output terminal voltage Vout appearing at an output terminal of an output MOS transistor M 1 . Voltage detecting circuit  501  can be viewed as an overcurrent detecting portion. Current limiting portion  502  includes diodes (D 51 , D 52 , and D 53 ). When voltage detecting circuit  501  judges that an overcurrent is being caused to flow through output transistor M 1 , current limiting portion  502  clamps the gate potential of output transistor M 1  to a cumulative forward bias voltage across diodes (D 51  to D 53 ) to limit the current flowing through output transistor M 1 . 
     The operation of conventional current limiting circuit of output circuit  500  will now be explained with reference to the I-V load curve of  FIG. 6  in conjunction with  FIG. 5 . In  FIG. 6 , it is assumed that a load LOAD illustrated in  FIG. 5  is an incandescent lamp and an input voltage Vin is applied as a flash control signal for the incandescent lamp to an input terminal IN. When input voltage Vin is at a low level (e.g., at 0 volt), MOS transistor M 1  is turned off. With MOS transistor M 1  turned off, no current flows through MOS transistor M 1  and output terminal voltage Vout becomes Vcc (e.g., 10 volts) as can be seen with load curve LOAD CURVE  1  which illustrates the I-V characteristics of the load LOAD. 
     Next, when signal Vin makes a transition to a high level (e.g., 5 volts), MOS transistor M 1  starts to conduct current. The gate of MOS transistor M 52  receives a voltage obtained by dividing the output terminal voltage Vout by a voltage divider circuit consisting of resistors (R 55  and R 56 ). If the output terminal voltage Vout is assumed to be VM under these conditions (see  FIG. 6 ), when a relationship of R 55 /(R 55 +R 56 )·VM≧Vt52 is established, MOS transistor M 52  is turned on (Vt52 is a threshold voltage of MOS transistor M 52 ). That is, when Vout≧VM, MOS transistor M 52  is turned on. VM can be expressed as (1+R 56 /R 55 )·Vt52. When MOS transistor M 52  is turned on, the gate of MOS transistor M 53  is pulled low and MOS transistor M 53  is turned off. With MOS transistor M 53  turned off, the gate of MOS transistor M 54  becomes input voltage Vin, in this case a high level. Thus, MOS transistor M 54  is turned on and a current flows from input terminal IN through a resistor R 510 , diodes (D 1  to D 3 ), and MOS transistor M 54 . In this way, the gate of MOS transistor M 1  is clamped to the cumulative forward bias voltages of diodes (D 1  to D 3 ). Assuming the cumulative forward bias voltages of diodes (D 1  to D 3 ) is a constant Vs, then a gate to source voltage (Vgs) of MOS transistor M 1  is fixed to Vs when Vout≧VM and a limited current value (Ilim 1 ) flows through transistor M 1 . 
     In this state, a resistance Ra of the load LOAD is much larger than an internal resistance Rm 1  of MOS transistor M 1 . Then, at the time when output terminal voltage Vout to be divided (note, the output terminal voltage Vout depends upon the resistances (Ra and Rm 1 , respectively) of load LOAD and MOS transistor M 1 ) has become lower than VM, MOS transistor M 52  is turned off. As a result, MOS transistor M 53  is turned on and the gate of MOS transistor M 54  is pulled low and MOS transistor M 54  is turned off. Consequently, the current path from the gate of MOS transistor M 1  through diodes (D 1  to D 3 ) is disabled and the gate of NMOS transistor M 1  receives the full input voltage Vin applied to input terminal IN. In this way, the internal resistance Rm 1  of MOS transistor M 1  is further reduced and the output terminal voltage Vout settles to a normal operating point A(Va, Ia) as illustrated in  FIG. 6 . The normal operating point A(Va, Ia) depends on the resistance Ra of the load LOAD and the resistance Rm 1  of MOS transistor M 1 . 
     Thus, at a time when a short-circuit failure, or the like, has occurred in a load LOAD, the output terminal voltage Vout is increased up to Vcc. However, when the output terminal voltage Vout reaches the above-mentioned voltage VM, MOS transistor M 52  is turned on and thereby MOS transistor M 54  is turned on to operate current limiting portion  502  and clamp the gate voltage of MOS transistor M 1  and limit an output current. In this way, even if the load LOAD is short-circuited, an overcurrent is prevented from flowing through MOS transistor M 1  and breakdown is prevented. Of course, the current limitation value ILIM 1  is set so that even when a voltage Vcc is applied to the drain of MOS transistor M 1 , the source-drain current of MOS transistor M 1  falls within a safe operating region. 
     However, in an output circuit  500  including a conventional current limiting circuit as described above, a problem arises in that when the resistance of the load LOAD is made smaller than Ra, the conventional current limiting circuit does not operate. For example, when the resistance of the load LOAD is a resistance Rb (in this case Rb is ½ Ra), the LOAD LOAD has an I-V characteristic as shown in load curve LOAD CURVE  2  in  FIG. 6 . Because the load LOAD is halved, the load current (Ib) becomes generally twice as large as Ia. Under this condition, the operating point is illustrated at point B(Vb, Ib). Here it is assumed that even in operating point B(Vb, Ib), the operation of MOS transistor M 1  is sufficiently within the safe operating region. In this case, as long as the output circuit  500  is in the normal operating state, resistance Rb should be sufficiently driven. 
     However, as viewed from the load curve LOAD CURVE 2 , there is another quiescent state of operation for conventional output circuit  500  at operating point C(Vc, Ilim 1 ). Thus, when the output terminal voltage is intended to go from Vcc to Vb in response to a change in the input voltage Vin, the operating point of the conventional output circuit  500  can settle at point C(Vc, Ilim 1 ) and not reach point B(Vb, Ib). As described above, although the output circuit  500  has the ability to drive the load LOAD having a resistance Rb, the conventional current limiting circuit can become an encumbrance in reaching the desired quiescent operating point. 
     Consequently, if conventional output circuit  500  is to be capable of correctly driving when a load LOAD has a resistance Rb, the current limitation value Ilim1 must be changed. However, this approach causes the current limiting circuit to be individually provided for every product and a dedicated design needs to be carried out in accordance with the particular load condition. Therefore, costs may be increased. 
     One approach to solving the above-mentioned problem is disclosed in Japanese Patent Application Laid-Open 2000-2726 A (JP 2000-2726 A). In JP 2000-2726 A, a conventional output circuit is shown in which a plurality of conventional current limiting circuits having different current limitation values is self-contained therein. Any one of these conventional current limiting circuit is adapted to be selected with a switch in accordance with the load condition. 
     However, in a conventional output circuit as disclosed in JP 2000-2726 A, a plurality of switches must be suitably changed over in accordance with the load used and control of the change over is specifically required. Also, after setting (changing over) the switches, the current limitation value is fixed. Therefore, if the load is then changed, the conventional output circuit of JP 2000-2726 A can have the same problems as discussed above for the conventional output circuit  500  of  FIG. 5 . 
     Another conventional output circuit is set forth in a circuit schematic diagram in  FIG. 7  and given the general reference character  700 . 
     Conventional output circuit  700  includes a voltage detecting circuit  701 , a voltage clamping circuit  702 , an output transistor M 1 , a load LOAD, and a resistor R 710 . 
     Resistor R 710  is connected between an input terminal IN and a gate of output transistor M 1 . Output transistor M 1  has a source connected to ground GND and a drain connected to a terminal of load LOAD. Load LOAD has another terminal connected to a power supply Vcc. Voltage detecting circuit  701  is connected to receive an input signal from input terminal IN and an output voltage Vout from the drain of output transistor M 1  and enables the voltage clamping circuit  702 . Voltage clamping circuit  702  is connected between the gate of output transistor M 1  and ground GND. 
     Voltage detecting circuit  701  includes resistors (R 75  to R 79 ) and transistors (M 72  to M 74 ). Resistors (R 75  and R 76 ) are connected in series between the output voltage Vout and ground GND. Resistor R 78  and transistor M 72  are connected to form an inverter. Resistor R 79  and transistor M 73  are connected to form an inverter. The inverter (R 78  and M 72 ) has an input connected to receive a voltage provided at a tap point connection between resistors (R 75  and R 76 ) and an output connected to the inverter (R 79  and M 73 ). The inverter (R 79  and M 73 ) has an output connected to a gate of transistor M 74 . Transistor M 74  has a source connected to ground GND and a drain connected to a drain of a transistor M 75  of voltage clamping circuit  702 . 
     Voltage clamping circuit  702  includes a transistor M 75  and resistors (R 71  and R 72 ). Resistors (R 71  and R 72 ) are connected in series between the gate of output transistor M 1  and ground GND. Transistor M 75  has a gate connected to a tap point formed at the connection of resistors (R 71  and R 72 ) and a drain connected to the gate of output transistor M 1 . 
     Voltage detecting circuit  701  is enabled when an input signal at input terminal IN is at a high level. When enabled, voltage detecting circuit  701  detects a voltage level of output voltage Vout. If the output voltage Vout is greater than a predetermined output voltage, transistor M 74  is turned on and voltage clamping circuit  702  is enabled to clamp the gate of output transistor M 1  to a predetermined voltage. If the output voltage Vout is less than the predetermined output voltage, transistor M 74  is turned off and voltage clamping circuit  702  is disabled. 
     In this way, conventional output circuit  700  provides a load curve characteristic as illustrated in  FIG. 6  and having only a current limitation value Ilim 1 . Thereby, conventional output circuit  700  has the same drawbacks as conventional output circuit  500 . 
     In light of the above, it would be desirable to provide an output circuit in which a value of a limited current flowing through an output transistor may be changed in a plurality of stages in response to a value of an output voltage of the output transistor. In particular, it would be desirable that a value of a limited current may be increased in response to a decrease in an output voltage. 
     SUMMARY OF THE INVENTION 
     A current limiting circuit capable of increasing a range of applicable load values is disclosed. An output circuit may include a current limiting circuit. A current limiting circuit may include a voltage detecting circuit and a voltage clamping circuit. A voltage detecting circuit ( 1 ) may detect a plurality of output voltages. Voltage clamping circuit may clamp a control terminal of an output transistor to a plurality of clamped voltages in response to the plurality of detected output voltages. In this way, an output transistor may have a plurality of current limitation values as an output voltage changes. By doing so, an output circuit may be applicable to a multitude of load values and properly operate without risks of overcurrent or undesired quiescent operating states being entered, as just two examples. 
     According to the embodiments, a current limiting circuit may set a current limitation of a current flowing through an output transistor by providing a predetermined one of a plurality of current limitation values in response to an output voltage of the output transistor. 
     According to another aspect of the embodiments, the current limitation may be increased in response to the output voltage decreasing. 
     According to another aspect of the embodiments, the current limitation may have a first value when the output voltage is essentially greater than a first voltage and a second value when the output voltage is essentially less than the first voltage. 
     According to another aspect of the embodiments, the current limiting circuit may be disabled when the output voltage is essentially less than a second voltage less than the first voltage. 
     According to another aspect of the embodiments, the current limiting circuit may include a voltage clamping circuit. A voltage clamping circuit may be coupled to a control terminal of the output transistor to provide the current limitation by limiting a control terminal voltage applied to the control terminal. 
     According to one aspect of the embodiments, a current limiting circuit may include a voltage clamping circuit. The voltage clamping circuit may control an output transistor control terminal. The voltage clamping circuit may change the output transistor control terminal to a first voltage level when the output voltage is at a first output voltage and may clamp the output transistor control terminal to a second voltage level when the output voltage is at a second output voltage lower than the first output voltage. 
     According to another aspect of the embodiments, the voltage clamping circuit may be enabled in response to the output voltage being greater than a predetermined voltage level. 
     According to another aspect of the embodiments, the predetermined voltage level may be less than the second output voltage. 
     According to another aspect of the embodiments, the second voltage level may be greater than the first voltage level. 
     According to another aspect of the embodiments, the current limiting circuit may include a voltage detecting circuit. A voltage detecting circuit may receive the output voltage and enable the voltage clamping circuit to provide the first voltage level when the output voltage is at the first output voltage and provide the second voltage level when the output voltage is at the second output voltage. 
     According to one aspect of the embodiments, the voltage detecting circuit may turn on a first switch for the voltage clamping circuit to provide the first voltage level and turns on a second switch for the voltage clamping circuit to provide the second voltage level. 
     According to another aspect of the embodiments, the voltage clamping circuit may include a plurality of diodes. The plurality of diodes may be connected in series between the output transistor control terminal and the first switch. The plurality of diodes may include a diode tap point connected to the second switch to essentially provide a shunt for at least one of the plurality of diodes when turned on. 
     According to another aspect of the embodiments, the voltage clamping circuit may include a plurality of resistors connected in series between the output transistor control terminal and a reference potential. The second switch may essentially provide a shunt for at least one of the plurality of resistors when turned on. 
     According to another aspect of the embodiments, the voltage detecting circuit may include a voltage divider. The voltage divider may receive the output voltage and provide a first divider output voltage and a second divider output voltage coupled to control the voltage clamping circuit. 
     According to another aspect of the embodiments, the output transistor control terminal may receive an input signal. The voltage detecting circuit may be enabled in response to the input signal having a first logic level and disabled in response to the input signal having a second logic level. 
     According to another aspect of the embodiments, a current limiting circuit may include a voltage detecting circuit and a voltage clamping circuit. The voltage clamping circuit may be activated in response to an input signal to detect an output voltage at an output terminal of an output transistor. A voltage clamping circuit may be connected to a gate terminal of the output transistor and may clamp the gate terminal to a first gate voltage in response to the voltage detecting circuit detecting a first output voltage and to a second gate voltage in response to the voltage detecting circuit detecting a second output voltage. 
     According to another aspect of the embodiments, the voltage detecting circuit may include a first switch and a second switch. The first switch may activate the voltage clamping circuit in accordance with an output voltage detected. The second switch may change the clamped voltage of the gate terminal from the first gate voltage and the second gate voltage. 
     According to another aspect of the embodiments, the voltage detecting circuit may change the state of the second switch so that the clamped voltage of the gate terminal is increased in accordance with a decrease of the output voltage. 
     According to another aspect of the embodiments, the voltage detecting circuit may include a first plurality of voltage division resistors, a first inverter, and a second inverter. The first plurality of voltage division resistors may be connected in series between an output terminal and a reference potential. The first plurality of voltage division resistors may have a plurality of voltage divider tap points. The first inverter may have a first inverter input coupled to a first tap point of the first plurality of voltage division resistors and a first inverter output coupled to a control terminal of the first switch. The second inverter may have a second inverter input coupled to a second tap point of the first plurality of voltage division resistors and a second inverter output coupled to a control terminal of the second switch. The voltage clamping circuit may include a second plurality of voltage division resistors and a reference transistor. The second plurality of voltage division resistors may be connected in series between the gate terminal of the output transistor and the reference potential. The second plurality of voltage division resistors may have at least one voltage divider tap point. The reference transistor may have a reference transistor current path connected between the gate terminal of the output transistor and an output terminal of the first switch and a reference transistor gate terminal coupled to a first tap point of the second plurality of voltage division resistors. The second switch may be connected to essentially provide a shunt for at least one of the second plurality of resistors when turned on. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit schematic diagram of an output circuit according to an embodiment of the present invention. 
         FIG. 2  is timing diagram illustrating the operation of the output circuit of  FIG. 1 . 
         FIG. 3  is a load curve illustrating the operation of an output circuit according to the present invention. 
         FIG. 4  is circuit schematic diagram of an output circuit according to another embodiment. 
         FIG. 5  is a circuit schematic diagram of a conventional output circuit. 
         FIG. 6  is a load curve illustrating the operation of a conventional output circuit. 
         FIG. 7  is a circuit schematic diagram of a conventional output circuit. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Various embodiments of the present invention will now be described in detail with reference to a number of drawings. 
     Referring now to  FIG. 1 , a circuit schematic diagram of an output circuit including a current limiting circuit according to an embodiment is set forth and given the general reference character  100 . 
     Output circuit  100  may include a transistor M 1 , a resistor R 10 , a voltage detecting circuit  1 , and a voltage clamping circuit  2 . Transistor M 1  may be an n-channel MOSFET (metal-oxide-semiconductor field effect transistor) and may be used as an output power transistor. A load LOAD may be connected between a power supply Vcc and an output terminal at a drain of transistor M 1  to produce an output voltage Vout. Transistor M 1  may have a source connected to a ground GND. Resistor R 10  may be connected between a gate of transistor M 1  and an input terminal IN. 
     Voltage detecting circuit  1  may be connected to the drain of transistor M 1  to detect an output voltage Vout. Voltage detecting circuit  1  may be considered as an overcurrent detecting portion for detecting whether or not an overcurrent may be caused to flow through transistor M 1 . Voltage detecting circuit  1  may be connected to input terminal IN and may essentially be powered by an input signal Vin received at input terminal IN. In this way, when an input signal Vin received at an input terminal IN is at a high level, voltage detecting circuit  1  may be activated and when input signal Vin is at a low level, voltage detecting circuit  1  may be disabled. 
     Voltage clamping circuit  2  may be activated in response to an output signal provided by voltage detecting circuit  1  to clamp a gate voltage of transistor M 1  to a voltage lower than that of input signal Vin. Voltage clamping circuit  2  may be connected as a current limiting portion to the gate of transistor M 1 . Voltage clamping circuit  2  is configured to generate different clamping voltages in accordance with an output signal provided by voltage detecting circuit  1 . That is, voltage clamping circuit  2  may be activated in accordance with a change in an output voltage of voltage detecting circuit  1  to automatically change from a first clamping voltage to a second clamping voltage in accordance with the change in the output voltage. In this way, a value of a limited current flowing through transistor M 1  may be changed in accordance with the state of operation. 
     Voltage detecting circuit  1  may include resistors (R 4 , R 5 , R 6 , R 7 , R 8 , and R 9 ) and transistors (M 2 , M 3 , M 4 , M 6  and M 7 ). Transistors (M 2 , M 3 , M 4 , M 6  and M 7 ) may be n-channel MOSFETs. 
     Resistor R 5  may have a first terminal connected to ground GND and a second terminal connected to a gate of transistor M 6 . Resistor R 4  may have a first terminal connected to a gate of transistor M 6  and a second terminal connected to a gate of transistor M 2 . Resistor R 6  may have a first terminal connected to a gate of transistor M 2  and a second terminal connected to receive the output voltage Vout at a drain of transistor M 1 . Resistors (R 4 , R 5 , and R 6 ) provide a voltage divider circuit that has voltage divider tap points at each terminal of resistor R 4 . 
     Resistor R 8  may have a first terminal connected to input terminal IN and a second terminal connected to a drain of transistor M 2  and a gate of transistor M 3 . Transistor M 2  may have a gate connected to a voltage divider tap point provided at a common connection node of resistors (R 4  and R 6 ) and a source connected to ground GND. Resistor R 8  and transistor M 2  may form a first inverter. 
     Resistor R 7  may have a first terminal connected to input terminal IN and a second terminal connected to a drain of transistor M 6  and a gate of transistor M 7 . Transistor M 6  has a gate connected to a voltage divider tap point provided at a common connection node of resistors (R 4  and R 5 ) and a source connected to ground GND. Resistor R 7  and transistor M 6  may form a second inverter. 
     Resistor R 9  may have a first terminal connected to input terminal IN and a second terminal connected to a drain of transistor M 3  and a gate of transistor M 4 . Transistor M 3  has a gate connected receive an output of the first inverter including resistor R 8  and transistor M 2  and a source connected to ground GND. Resistor R 9  and transistor M 3  may form a third inverter. 
     Transistor M 4  may have a gate connected to the output of the third inverter including resistor R 9  and transistor M 3  and a source connected to ground GND. Transistor M 4  may be conceptualized as a first switching transistor and may provide a controllable impedance path between ground GND and voltage clamping circuit  2 . 
     Transistor M 7  may have a gate connected to the output of the first inverter including resistor R 7  and transistor M 6  and a source connected to ground GND. Transistor M 7  may be conceptualized as a second switching transistor and may provide a controllable impedance path between ground GND and voltage clamping circuit  2 . 
     Voltage clamping circuit  2  may include resistors (R 1 , R 2 , and R 3 ) and a transistor M 5 . Transistor M 5  may be a n-channel MOSFET. 
     Resistor R 1  may have a first terminal connected to a gate of transistor M 1  and a second terminal connected to a gate of transistor M 5 . Resistor R 2  may have a first terminal connected to a gate of transistor M 5  and a second terminal connected to a drain of transistor M 7 . Resistor R 3  may have a first terminal connected to a drain of transistor M 7  and a second terminal connected to ground GND. In this way, transistor M 7 , which provides a second switch transistor, may be connected in parallel with resistor R 3 . Transistor M 5  may have a drain connected to a gate of transistor M 1  and a source connected to a drain of transistor M 4 . In this way, transistor M 5  may be connected in series with transistor M 4 , which can comprise a first switch transistor. 
     The operation of output circuit  100  will now be described with reference to  FIG. 2 .  FIG. 2  is a timing diagram illustrating the operation of output circuit  100  of  FIG. 1 .  FIG. 2  shows an input signal Vin at an input terminal IN and an output voltage Vout at a connection between the drain of transistor M 1  and the load LOAD. It is assumed that a load LOAD is a resistance R of an incandescent lamp, for example, and an input signal Vin as shown in  FIG. 2  is applied to input terminal IN as a flash control signal of the incandescent lamp. 
     Referring now to  FIG. 2  in conjunction with  FIG. 1 , when input signal Vin is at a low level (e.g. 0 volt) voltage detecting circuit  1  receives no power and may be disabled. In this condition, transistors M 4  and M 7  are turned off, thus voltage clamping circuit  2  may not provide a clamping of the voltage at the gate of transistor M 1 . Thus, the input signal Vin is provided at the gate of transistor M 1 . With the gate of transistor M 1  low, transistor M 1  is turned off and in a high impedance state so that essentially no current flows through transistor M 1 . Therefore, the output voltage Vout becomes essentially equal to the power supply Vcc (e.g., 10 volts). 
     Then at time t1, the input signal Vin makes a transition to the high level (e.g., 5V), transistor M 1  turns on and begins to conduct current. Here, the voltage applied to the gate of transistor M 2  of voltage detecting circuit  1  is (R 4 +R 5 )/(R 4 +R 5 +R 6 )·Vout. During the time period that this voltage is greater than a threshold voltage Vt2 of transistor M 2 , transistor M 2  is turned on and in a relatively low impedance state. This occurs as long as the following equation is satisfied.
 
( R 4+ R 5)/( R 4+ R 5+ R 6)· Vout≧Vt 2   (1)
 
If Vout at this time is assumed to be VM 1 , the following equation is obtained.
 
 V out≧(1+( R 6/( R 4+ R 5))· Vt 2 =VM 1   (2)
 
With transistor M 2  turned on, the gate of transistor M 3  is pulled low and transistor M 3  is turned off. With transistor M 3  turned off, the gate of transistor M 4  is pulled high toward the input signal Vin level through resistor R 9 . Thus, transistor M 4  is turned on. In this way, a current path from the gate of transistor M 1  through transistor M 5  of voltage clamping circuit  2  is enabled. Transistor M 4  may activate voltage clamping circuit  2  when turned on and may disable voltage clamping circuit  2  when turned off. Transistor M 4  may be turned on or turned off in accordance with the voltage level of output voltage Vout when the input signal Vin is at a high level.
 
     Transistor M 6  may receive a gate voltage from the voltage divider tap point at a common connection of resistors (R 4  and R 5 ). In this way, transistor M 6  may receive a gate voltage of Vout·R 5 /(R 4 +R 5 +R 6 ). If the voltage level of output voltage Vout that is required to turn on transistor M 6  is assumed to be VM 2 , then VM 2  can be expressed as follows.
 
 V out≧(1+( R 4+ R 6)/( R 4+ R 5+ R 6))· Vt 6   (3)
 
Vt6 is a threshold voltage of transistor M 6 . When transistor M 6  is turned on, the gate of transistor M 7  is pulled low and transistor M 7  may be turned off. However, if output voltage Vout is less than VM 2 , transistor M 6  is turned off. With transistor M 6  turned off, a voltage level essentially equal to the input signal Vin may be provided to a gate of transistor M 7  and transistor M 7  may be turned on.
 
     When transistor M 7  is turned on, resistor R 3  may be essentially shunted through transistor M 7 . In this way, a voltage applied to a gate of transistor M 5  may be at a lower voltage level. 
     As described above according to the embodiment of  FIG. 1 , when input signal Vin having a high level is applied to input terminal IN, voltage detection circuit  1  may be enabled. When voltage detection circuit  1  is enabled, transistor M 4  may be turned on when the output voltage Vout is greater or equal to VM 1 . With transistor M 4  turned on, voltage clamping circuit  2  may be enabled. When the output voltage Vout is greater than or equal to VM 2 , transistor M 7  may be turned off. However, when the output voltage Vout is less than VM 2 , transistor M 7  may be turned on. It should be noted VM 1 ≦VM 2 . 
     The operation of output circuit  100  as described above will now be further described with reference to the timing diagram of  FIG. 2  and the I-V load curve of  FIG. 3 .  FIG. 3  is an I-V load curve for the output circuit  100  of  FIG. 1 . 
     When input signal Vin is low, transistor M 1  is turned off and voltage detecting circuit  1  is disabled. At the time the input signal Vin transitions from a low level to a high level as illustrated at time t 1  of  FIG. 2 , transistor M 1  may turn on and the output voltage Vout begins to drop. Also, at this time, voltage detection circuit  1  may be enabled. As long as Vout≧VM 2  as shown when t 1 ≦t≦t 2 , transistors (M 3  and M 7 ) are turned off and transistors (M 2 , M 4  and M 6 ) are turned on. With transistor M 7  turned off and transistor M 4  turned on, the output voltage of voltage clamping circuit  2  at the gate of transistor M 1  assumed to be VGS 1  may follow the following expression.
 
 VGS 1=(1+( R 1/( R 2+ R 3)· Vt 5   (4)
 
     With the gate voltage of transistor M 1  being clamped to VGS 1  and transistor M 1  operating in the saturation region, the current flowing through transistor M 1  may be limited to a current Ilim 1  as illustrated in  FIG. 3 . It is noted that current Ilim 1  depends on VGS 1 . 
     If a resistance Rb of load LOAD is much larger than an internal resistance Rm 1  of transistor M 1  output voltage Vout continues to decrease. Then, when VM 1 ≦Vout≦VM 2  as shown when t 2 ≦t≦t 3  in  FIG. 2 , transistor M 6  may turn off and transistor M 7  may turn on. With transistor M 7  turned on, resistor R 3  may be essentially shunted. At this time, the output voltage of voltage clamping circuit  2  applied to the gate of transistor M 1  may depend on resistors (R 1  and R 2 ) and transistor M 5  and may be expressed as VGS 2  by the following expression.
 
 VGS 2=(1+( R 1/ R 2))· Vt 5   (5)
 
     With the gate voltage of transistor M 1  being clamped to VGS 2  and transistor M 1  operating in the saturation region, the current flowing through transistor M 1  may be limited to a current Ilim 2  as illustrated in  FIG. 3 . It is noted that current Ilim 2  depends on VGS 2 . 
     In this way, transistor M 7  may provide a control switch for changing an output clamping voltage of voltage clamping circuit  2  from a first voltage to a second voltage in accordance with the output voltage Vout of output circuit  100 . Because the potential of VGS 2  is larger than the potential of VGS 1 , a current limitation value Ilim 2  may be larger than a current limitation value Ilim 1  which may flow through transistor M 1 . 
     It is noted in accordance with equations 4 and 5, that a clamped voltage of transistor M 1  may be proportional to a threshold voltage (Vt5) of transistor M 5 . In this way, transistor M 5  may be conceptualized as a reference transistor. 
     As described above, because the limited current may be automatically increased as the output voltage Vout is decreased, a load curve LOAD CURVE  2  may not intersect with the current limitation line and output voltage Vout may decrease without settling into an undesired quiescent point. Then at a time when output voltage Vout&lt;VM 1  as shown at time t 3 , transistor M 2  may turn off. With transistor M 2  turned off, the gate of transistor M 3  may receive a high level and may turn on. With transistor M 3  turned on, the gate of transistor M 4  may be pulled low and transistor M 4  may be turned off. With transistor M 4  turned off, a current path from the gate of transistor M 1  through series connected transistors (M 4  and M 5 ) may be eliminated. In this way, voltage clamping circuit  2  may be disabled. 
     At the time when voltage clamping circuit  2  is disabled, a voltage value which is obtained at a voltage divider tap point (connection node of resistors R 10  and R 1 ) by dividing the voltage of input signal Vin by a voltage divider formed by resistors (R 10 , R 1 , and R 2 ) may be applied to the gate of transistor M 1 . It is understood that resistance values of resistors (R 10 , R 1 , and R 2 ) may be set so that the voltage applied to the gate of transistor M 1  at this time is larger than VGS 2  and may be nearly the voltage of the input signal Vin. In such a manner, because input signal Vin is substantially applied to transistor M 1  the output voltage Vout may transition to a normal quiescent operating point B(Vb, Ib) depending on a resistance Rb of load LOAD and an internal resistance Rm 1  of transistor M 1 . It is noted that, according to the embodiment of  FIG. 1 , the output voltage Vout may transition to a normal quiescent operating point without inadvertently settling into an undesired quiescent point as compared to a conventional output circuit. 
     Thereafter, if a short circuit failure occurs in the load LOAD, the output voltage Vout may make a substantial transition to Vcc. In response to this situation, voltage detecting circuit  1  may turn on transistor M 4 . In this way, voltage clamping circuit  2  may be activated or enabled. Also, voltage detecting circuit  1  may turn off transistor M 7  so the gate of transistor M 1  may be clamped to VGS 1  by voltage clamping circuit  2 . In such a way, the current of transistor M 1  may be limited to the smallest current limitation value Ilim 1  to protect the apparatus in the abnormal state. 
     The gate of transistor M 1  may be conceptualized as an output transistor control terminal. 
     While in the above-mentioned embodiment, a current limitation value having two stepped values is disclosed, a current limitation value having multiple steps greater than two may also be provided as illustrated by the dashed line of  FIG. 3 . It is to be understood that if a current limitation value having multiple steps greater than two is provided, the range of resistance values of drivable load LOAD may be further widened. Of course, the lower current limitation value may be set so that the operation of transistor M 1  falls with a safe current value when, for example, a short circuit of the load LOAD or the like occurs. 
     Referring now to  FIG. 4 , a circuit schematic diagram of an output circuit including a current limiting circuit according to another embodiment is set forth and given the general reference character  400 . 
     Output circuit  400  may include a transistor M 1  a resistor R 10 , a voltage detecting circuit  401 , and a voltage clamping circuit  402 . 
     Voltage detecting circuit  401  of  FIG. 4  may differ from voltage detecting circuit  1  of  FIG. 1  in that transistor M 6  and resistor R 7  forming the second inverter may be eliminated. Instead, transistor M 7  may have a gate connected to a voltage divider tap point provided at a common connection node of resistors (R 4  and R 5 ). 
     Voltage clamping circuit  402  may include diodes (D 1 , D 2 , D 3 , and D 4 ). Diode D 1  may have an anode connected to a gate of transistor M 1  and a cathode connected to an anode of diode D 2 . Diode D 2  may have a cathode connected to an anode of diode D 3 . Diode D 3  may have a cathode connected to an anode of diode D 4  and a drain of transistor M 7 . Diode D 4  may have a cathode connected to a drain of transistor M 4 . 
     The operation of output circuit  400  will now be briefly discussed. The operation of the turning on and turning off of transistor M 4  may be essentially the same as in the operation of output circuit  100  discussed above. When the output voltage Vout is essentially greater than or equal to VM 1 , transistor M 4  may be turned on. When the output voltage Vout is essentially less than VM 1 , transistor M 4  may be turned off. 
     However, the operation of voltage detecting circuit  401  may differ from the operation of voltage detecting circuit  1  in that transistor M 7  may turn on when the output voltage Vout is greater than or equal to VM 2  and transistor M 7  may turn off when the output voltage Vout is less than VM 2 . 
     Thus, when Vout≧VM 2 , transistor M 7  may be turned on and transistor M 4  may be turned on. With transistor M 7  turned on, diode D 4  may be essentially shunted. In this way, the gate of transistor M 1  may be clamped to essentially a cumulative forward bias voltage of three diodes (D 1  to D 3 ) and transistor M 1  may have a first current limitation value, for example Ilim 1 . 
     Then, when VM 1 ≦Vout≦VM 2 , transistor M 4  may be turned on and transistor M 7  may be turned off. In this way, the gate of transistor M 1  may be clamped to essentially a cumulative forward bias voltage of four diodes (D 1  to D 4 ) and transistor M 1  may have a second current limitation value, for example Ilim 2 . 
     Then, when Vout&lt;VM 1 , transistors (M 4  and M 7 ) may be turned off. In this way, the gate of transistor M 1  may receive essentially the voltage of input signal Vin. 
     It is understood that the embodiments described above are exemplary and the present invention should not be limited to those embodiments. Specific structures should not be limited to the described embodiments. 
     For example, a positive power supply is provided to a load LOAD. In this case, an n-channel MOSFET may be used as an output transistor (transistor M 1 ). However, as just one example, a p-channel MOSFET may be used as an output transistor. In this case, the output transistor may have a source connected to a positive power supply and a load may be connected to ground as one example. Alternatively, the output transistor may have a source connected to a ground and a load may be connected to negative supply as another example. When a p-channel MOSFET is used as an output transistor, a logic low value of input signal Vin may be used to enable the voltage detecting circuit. 
     As described above according to the embodiments, a value of a limited current flowing through an output transistor may be increased in accordance with a decrease in an output voltage provided at a connection between the output transistor and a load. Thus, even if an output circuit is used with a wide range of loads without an external load adjustment control, the output voltage may transition to desired quiescent states without inadvertently settling into an undesired quiescent state due to load lines intersecting with current limitation lines. In this way, one output circuit may be versatile to function with a large number of loads and the necessity of designing a load specific output circuit for each differing load may become unnecessary. Also, a need of providing, for example an external load adjustment control to an output circuit to be used with differing loads may become unnecessary. 
     While various particular embodiments set forth herein have been described in detail, the present invention could be subject to various changes, substitutions, and alterations without departing from the spirit and scope of the invention. Accordingly, the present invention is intended to be limited only as defined by the appended claims.