Abstract:
A shift register that is suitable for reducing the required number of clock signals as well as simplifying the configuration of an external control circuit uses a plurality of stages connected, in series, to a start pulse input line. In each stage, an output circuit responds to a first control signal to apply any one of first and second clock signals to a row line of a liquid crystal cell array and thus to charge the low line of the liquid crystal cell array, and responds to a second control signal to discharge a voltage at the row line. An output circuit responds to a clock signal different from any one of the start pulse and an output signal of the previous stage to generate the first control signal, and responds to a clock signal different from the first control signal to generate the second control signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a driving circuit for an active matrix display device, and more particularly to a shift register for driving pixel rows of a liquid crystal display device. 
     2. Description of the Related Art 
     A liquid crystal display (LCD) used as a display device for a television and a computer includes a liquid crystal matrix having liquid crystal cells arranged at intersections of data lines (i.e., column lines) with selection lines (i.e., row lines). These selection lines are horizontal lines (i.e., row lines) of the liquid crystal matrix and are selected by a shift register. 
     As shown in FIG. 1, the conventional shift register includes n stages  2   1  to  2   n  that are connected in cascade and that are connected, via output lines  4   1  to  4   n−1 , to n row lines ROW 1  to ROW n , respectively. The first stage  2   1  receives a start pulse SP, and the second to n th  stages  2   2  to  2   n  receive output signals g 1  to g n−1  of the previous stages  2   1  to  2   n−1 . Also, the 1 st  to n th  stages  2   1  to  2   n  shift the start pulse SP, or the output signals g 1  to g n−1  of the previous stages  2   1  to  2   n−1 , respectively, by two of three clock signals C 1  to C 3 , thereby sequentially enabling row lines ROW i  connected to the pixel rows. 
     As shown in FIG. 2, each of the stages  2   1  to  2   n  in FIG. 1 includes a fifth NMOS transistor T 5  for applying a high logic level voltage signal to an output line  4   i , and a sixth NMOS transistor T 6  for applying a low logic level voltage signal to the output line  4   i . Also, each stage  2   i  includes a first NMOS transistor T 1  for receiving the start pulse SP, or an output signal g i−1  of the previous stage  2   i−1  at gate and drain terminals thereof, and a third NMOS transistor T 3  for receiving the third clock signal C 3  at the gate terminal thereof. The third clock signal C 3  is changed from a low logic level into a high logic level simultaneously with the output signal g i−1 , of the previous stage  2   i−1 . Accordingly, the third NMOS transistor T 3  and the fourth NMOS transistor T 4  are simultaneously turned on. Since the W/L ratio of the fourth NMOS transistor T 4  (wherein W is a channel width and L is a channel length) is larger than that of the third NMOS transistor T 3 , a voltage VP 2  at a second node P 2  has a low logic level close to the ground voltage level. As described above, the stages  2   1  to  2   n  included in the conventional shift register have a ratio logic. Since a voltage VP 1  at a first node P 1  has a voltage level close to the output signal g i−1  of the previous stage  2   i−1  input via the first NMOS transistor T 1 , a fifth NMOS transistor T 5  is turned on. At this time, the first clock signal C 1  maintains a low logic level, so that a low logic level voltage signal appears at the output line  4   i . 
     If the first clock signal C 1  changes from a low logic level to a high logic level while the voltage VP 1  at the first node P 1  remains at a high logic level, the output line  4   i  charges to the high logic level voltage of the first clock signal C 1  input via the fifth NMOS transistor T 5 . At this time, the first node P 1  is coupled to the output terminal  4   i  by a parasitic capacitor C gs  existing between the gate terminal and the drain terminal of the fifth NMOS transistor T 5 , thereby allowing a charge voltage VP 1  at the first node P 1  to be raised to a higher level. 
     Accordingly, a high logic level voltage of the first clock signal C 1  is applied to the output line  4   i  without loss. The first and fourth NMOS transistors T 1  and T 4  are turned off by the output signal g i−1  of the previous stage  2   i−1  changing from a high logic level into a low logic level. Subsequently, if the first clock signal C 1  changes from a high logic level to a low logic level again, then the fifth NMOS transistor T 5  remains a turned-on state, so that a voltage V out  at the output line  4   i  changes to a low logic level. Next, if the third clock signal C 3  changes from a low logic level to a high logic level again, the third NMOS transistor T 3  is turned on, thereby allowing a supply voltage V cc  to be charged onto the second node P 2 . Thus, a high logic level voltage VP 2  appears at the second node P 2 . At this time, the sixth NMOS transistor TG receiving a high logic voltage VP 2  of the second node P 2  at its gate terminal is turned on to discharge a voltage V out  at the output line  4   i  to a ground voltage level V ss . Accordingly, a output voltage V out  at the output line  4   i  has a low logic level. Likewise, the second NMOS transistor T 2  receiving a high logic level voltage VP 2  at its gate terminal also is turned on to discharge a charge voltage VP 1  at the first node P 1  onto the ground voltage level V ss . As a result, a charge voltage VP 1  at the first node P 1  has a low logic level. As described above, the conventional shift register sequentially shifts the start pulse SP from the first output line  4   1  to the n th  output line  4   n  using the clock signals C 1  to C 3 , thereby sequentially driving the output lines  4   1  to  4   n . 
     However, the conventional shift register needs four pulse signals including three clock signals C 1  to C 3  and a start pulse SP and, at the same time, requires a circuitry for generating the clock signals and the pulse signals. This causes a complication in the structure of the external control circuit, as well as an increase in the manufacturing cost. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a shift register that is suitable for reducing the required number of clock signals and for simplifying an external control circuit. 
     In order to achieve these and other objects of the invention, each stage in the shift register according to one aspect of the present invention includes an output circuit for responding to a first control signal to apply any one of the first and second clock signals to the row line of the liquid crystal cell array and thus to charge the row line, and for responding to a second control signal to discharge a voltage at the row line; and an input circuit for responding to a clock signal different from any one of an output signal of the previous stage and the start pulse to generate the first control signal, and for responding to a clock signal different from the first control signal to generate the second control signal. 
     A shift register according to another aspect of the present invention includes odd-numbered stages each having an output circuit for responding to a first control signal to apply the first clock signal to the odd-numbered row line of the liquid crystal cell array and for responding to a second a-control signal to discharge a voltage at the odd-numbered row line of the liquid crystal cell array; and an input circuit for responding to any one of an output signal of the previous stage and the start pulse and the second clock signal to generate the first and second control signals, and even-numbered stages each having an output circuitry for responding to a third control signal to apply the second clock signal to the even-numbered row line of the liquid crystal cell array and for responding to a fourth control signal to discharge a voltage at the even-numbered row line of the liquid crystal cell array; and an input circuit for responding to an output signal of the previous stage and the first clock signal to generate the third and fourth control signals. 
     A shift register according to still another aspect of the present invention includes (3k)th stages (wherein K is an integer), each having a first output circuit for responding to a first control signal to apply the first clock signal to the (3k) th  row line of the liquid crystal cell array and for responding to a second control signal to discharge a voltage at the (3k) th  row line of the liquid crystal cell array; and a first input circuit for responding to any one of the start pulse and an output signal of the previous stage and the third clock signal to generate the first and second control signals, (3k+1) th  stages each having a second output circuit for responding to a third control signal to apply the second clock signal to the (3k+1) th  row line of the liquid crystal cell array and for responding to a fourth control signal to discharge a voltage at the (3k+1) th  row line of the liquid crystal cell array; and a second input circuit for responding to the output signal of the previous stage and the first clock signal to generate the third and fourth control signals, and (3k+2) th  stages each having a third output circuit for responding to a fifth control signal to apply the third clock signal to the (3k+2) th  row line of the liquid crystal cell array, and for responding to a sixth control signal to discharge a voltage at the (3k+2) th  row line of the liquid crystal cell array; and a third input circuit for responding to the output signal of the previous stage and the second clock signal to generate the fifth and sixth control signals. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects of the invention will be apparent from the following detailed description of the embodiments of the present invention with reference to the accompanying drawings, in which: 
     FIG. 1 is a schematic block diagram showing the configuration of a conventional shift register; 
     FIG. 2 is a detailed circuit diagram of a shift register stage shown in FIG. 1; 
     FIG. 3 is waveform diagram of input/output signals of the stage shown in FIG. 2; 
     FIG. 4 is a schematic block diagram showing the configuration of a shift register according to a first embodiment of the present invention; 
     FIG. 5 is waveform diagrams of an input/output signal of the shift register shown in FIG. 4; 
     FIG. 6 is a detailed circuit diagram of an embodiment of the stage shown in FIG. 4; 
     FIG. 7 is waveform diagrams of an input/output signal of the stage shown in FIG. 6; 
     FIG. 8 is a schematic block diagram showing the configuration of a shift register according to a second embodiment of the present invention; 
     FIG. 9 is waveform diagrams of an input/output signal of the shift register shown in FIG. 8; and 
     FIG. 10 is a detailed circuit diagram of another embodiment of the stage shown in FIG.  4 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 4, there is shown a shift register according to a first embodiment of the present invention. The shift register includes n stages  12   1  to  12   n  connected, in cascade, to a start pulse input line SPL to drive an m×n pixel array. Output lines  14   1  to  14   n  of the n stages  12   1  to  12   n  are connected to n row lines ROW 1  to ROW n  included in the pixel array, respectively. The first stage  12   1  receives a start pulse SP from the start pulse input line SPL, and the 2 nd  to n th  stages  12   2  to  12   n  receive output signals g 1  to g n−1  of the first to (n−1)th stages  12   1  to  12   n−1 , respectively, as a start pulse. Each stage  12   1  to  12   n  includes first and second clock terminals CLKA and CLKB for inputting two clock signals C 1  and C 2 , respectively. The first clock signal C 1  is applied to the first clock terminal CLKA of odd-numbered stages  12   1 ,  12   3 , . . . ,  12   n−1 , while a second clock signal C 2  is applied to the second clock terminal CLKB thereof. On the other hand, the second clock signal C 2  is applied to the first clock terminal CLKA of even-numbered stages  12   2 ,  12   4 , . . . ,  12   n  , while the first clock signal C 1  is applied to the second clock terminal CLKB thereof. The first clock signal C 1  has an inverted waveform with respect to the second clock signal C 2 , as shown in FIG.  5 . 
     The 1 st  to n th  stages  12   1  to  12   n  respond to the first and second clock signals C 1  and C 2  to sequentially shift the start pulse SP at the start pulse input line SPL from the first output line  14   1  to the n th  output line  14   1 , thereby allowing n output voltage signals Vout 1  to Vout n , as shown in FIG. 5, having a pulse enabled to a high logic level sequentially to emerge on the first to n th  output lines  14   1  to  14   n , respectively. 
     Accordingly, pixels included in the pixel array are driven sequentially for each line. These input signals of the shift register, that is, the start pulse SP, the first and second clock signals C 1  and C 2  having an inverted phase with respect to each other, the supply voltage VCC, and the ground voltage VSS, are supplied from an external control circuit (not shown). 
     Preferably, as shown in FIG. 6, each stage  12 , to  12   n  further includes a start pulse input terminal SPT, a first NMOS transistor T 1  connected between a second clock terminal CLKB and a first node P 1 , a second NMOS transistor connected among a supply voltage line VCCL, the second clock terminal CLKB and a second node P 2 , third and fourth NMOS transistors T 3  and T 4  connected, in series, between a ground voltage line VSSL and the second node P 2 , a fifth NMOS transistor T 5  connected among the first clock terminal CLKA, the first node P 1  and the output line  14   i , and a sixth NMOS transistor T 6  connected among the ground voltage line VSSL, the second node P 2  and the output line  14   i . 
     Prior to an explanation as to an operation of the circuit shown in FIG. 6, it is assumed that a stage of FIG. 6 should be the i th  stage  12   I , and i should be an odd number. In this case, the first clock terminal CLKA receives the first clock signal C 1  while the second clock terminal CLKB receives the second clock signal C 2 . As shown in FIG. 7, an output signal g i−1  of the previous stage  12   i−1  is changed from a low logic level to a high logic level simultaneously with the second clock signal C 2 . On the other hand, the first clock signal C 1  applied to the first clock terminal CLKA is changed from a high logic level to a low logic level. At this time, the first NMOS transistor T 1  is turned on to charge the output signal g i−1  of the previous stage  12   i  onto the first node P 1 . The fourth NMOS transistor T 4  is turned on by a charge voltage VP 1  charged in the first node P 1  to thereby connect the third NMOS transistor T 3  to the ground voltage line VSSL. The fifth NMOS transistor T 5  also is turned on by the charge voltage charged in the first node P 1  to thereby connect the first clock terminal CLKA to the output line  14   i . Furthermore, the second NMOS transistor T 2  also is turned on by the second clock signal C 2  to thereby deliver a supply voltage VCC on the supply voltage line VCCL onto the second node P 2 . On the other hand, the third NMOS transistor T 3  is turned off by the low logic level of first clock signal C 1  from the first clock terminal CLKA. Accordingly, the second node P 2  charges to the supply voltage VCC from the supply voltage line VCCL and the sixth NMOS transistor T 6  is turned on by a charge voltage on the second node P 2 , thereby connecting the output line  14   i  to the ground voltage line VSSL. The fifth and sixth NMOS transistors T 5  and T 6  are turned on in this manner and the first clock signal C 1  has a low logic level, so that a low logic level output voltage V out  emerges at the output line  14   i . 
     Subsequently, the second clock signal C 2  and the output signal g i−1  of the previous stage  12   i−1  transition from a high logic level to a low logic level, whereas the first clock signal C 1  changes from a low logic level to a high logic level. The first and second transistors T 4  and T 5  are turned off by the low logic level of second clock signal C 2 . On the other hand, the third NMOS transistor T 3  is turned on by the high logic level of the first clock signal C 1  to thereby discharge the charge voltage VP 2  on the second node P 2  onto the ground voltage line VSSL, via the drain and source terminals thereof and the drain and source terminals of the fourth NMOS transistor T 4 . Thus, a voltage at the second node P 2  has the ground voltage VSS. The sixth NMOS transistor T 6  is turned off by a charge voltage VP 2  with a ground voltage VSS from the second node P 2 , thereby opening or disconnecting the output line  14   i  from the ground voltage line VSSL. As a result, the output line  14   i  charges to the high logic level voltage of the first clock signal C 1  input from the first clock terminal CLKA via the fifth NMOS transistor T 5 , thereby generating a high logic level output voltage Vout as shown in FIG.  7 . At this time, the charge voltage VP 1  at the first node P 1  is coupled with the output line  14   i  by a parasitic capacitor C gs  existing between the gate terminal and the source terminal of the fifth NMOS transistor T 5 , thereby allowing the first node P 1  to be raised by a voltage V out  on the output line  14   i  as shown in FIG.  7 . Thus, the high logic level of the first clock signal C 1  is applied to the output line  14   i  with no attenuation. The i th  row line ROWi of the pixel array is enabled by such a high logic level output voltage, Vout. 
     Consequently, the first clock signal C 1  transitions from a high logic level to a low logic level, whereas the second clock signal C 2  changes from a low logic level to a high logic level. The first NMOS transistor T 1  is turned on to discharge the charge voltage VP 1  charged in the first node P 1  onto the start pulse input terminal SPT. Thus, a charge voltage VP 1  at the first node P 1  has the ground voltage VSS. Accordingly, the fourth NMOS transistor T 4  is turned off to open or disconnect the third NMOS transistor T 3  from the ground voltage line VSSL. The fifth NMOS transistor T 5  also is turned off by the ground voltage VSS on the first node P 1  to thereby open or disconnect a current path between the first clock terminal CLKA and the output line  14   i . Meanwhile, the second NMOS transistor T 2  turned on by the high logic level of the second clock signal C 2  delivers the supply voltage VCC on the supply voltage line VCCL onto the second node P 2 . At this time, since the fourth NMOS transistor T 4  has been turned off, the second node P 2  charges the supply voltage VCC input, from the supply voltage line VSSL via the second NMOS transistor T 2 . Thus, a high logic level charge voltage VP 2  emerges at the second node P 2 . The sixth NMOS transistor T 6  is turned on by the high logic level charge voltage VP 2  on the second node P 2  to thereby connect the output line  14   i  to the ground voltage line VSSL. As a result, the output voltage Vout at the output line  14   i  has a low logic level. 
     Referring now to FIG. 8, there is shown a shift register according to a second embodiment of the present invention. The shift register includes n stages  22   1  to  22   n  connected, in cascade, to a start pulse input line SPL. Output lines  24 , to  24   n  of the n stages are connected to n row lines ROW 1  to ROW n  included in a pixel array, respectively. A start pulse SP at a start pulse input line SPL is applied to the first stage  22   1 , whereas output signals g 1  to g n−1  of the first to (n−1) th  stages  22   1  to  22   n−1  are applied to the post stages  22   2  to  22   n , respectively, as a start pulse. 
     Each stage  22   1  to  22   n  includes first and second clock terminals CLKA and CLKB for inputting two clock signals of the first to third clock signals C 1  to C 3 , phase-delayed sequentially as shown in FIG.  9 . The first clock signal C 1  is applied to the first clock terminal CLKA of the (3k+1) th  stages (wherein K is an integer)  22   1 ,  22   4 , . . . while the third clock signal C 3  is applied to the second clock terminal CLKB thereof. The second clock signal C 2  is applied to the first clock terminal CLKA of the (3k+2) th  stages (wherein K is an integer)  22   2 ,  22   5 , . . . while the first clock signal C 1  is applied to the second clock terminal CLKB thereof. The third clock signal C 3  is applied to the first clock terminal CLKA of the (3k) th  stages (wherein K is an integer)  22   3 ,  22   6 , . . . while the second clock signal C 2  is applied to the second clock terminal CLKB thereof. 
     The 1 st  to n th  stages  22   1  to  22   n  respond to any two clock signal of the first to third clock signals C 1  to C 3  to sequentially shift the start pulse SP at the start pulse input line SPL from the first output line  24   1  to the n th  output line  24   n . Accordingly, n output voltage signals Vout 1  to Vout n , as shown in FIG. 9, having a pulse enabled to a high logic level, sequentially emerge on the 1 st  to n th  output lines  24   1  to  24   n  of the 1 st  to n th  stages  22   1  to  22   n , respectively. As a result, the 1 st  to n th  low lines ROW 1  to ROW n  of pixels included in the pixel array are sequentially enabled by the output signals of the 1 st  to n th  stages  22   1  to  22   n . 
     Preferably, such 1 st  to n th  stages  22   1  to  22   n  are implemented similarly to the stage circuit of FIG. 6 described earlier. It is assumed that a stage of FIG. 6 should be the i th  stage  22   i  and i should be 3k+1 (wherein k is an integer). In this case, the first clock terminal CLYA receives the first clock signal C 1 , while the second clock terminal CLKB receives the third clock signal C 3 . As shown in FIG. 9, an output signal g i−1  of the previous stage  22   i−1  is changed from a low logic level to a high logic level simultaneously with the third clock signal C 3 . On the other hand, the first clock signal C 1 , applied to the first clock terminal CLKA, remains at a low logic level. At this time, the first NMOS transistor T 1  is turned on to transfer the level of the output signal g i−1  of the previous stage  22   i−1  (FIG. 8) onto the first node P 1 . The fourth NMOS transistor T 4  is turned on by a charge voltage VP 1  charged in the first node P 1  to thereby connect the third NMOS transistor T 3  to the ground voltage line VSSL. The fifth NMOS transistor T 5  also is turned on by the charge voltage VP 1  charged in the first node P 1  to thereby connect the first clock terminal CLKA to the output line  24   i . 
     Furthermore, the second NMOS transistor T 2  also is turned on by the high logic level of the third clock signal C 3  from the second clock terminal CLKB to thereby deliver a supply voltage VCC on the supply voltage line VCCL into the second node P 2 . On the other hand, the third NMOS transistor T 3  is turned off by the low logic level of the first clock signal C 1  from the first clock terminal CLKA. Accordingly, the second node P 2  charges to the supply voltage VCC from the supply voltage line VCCL and the sixth NMOS transistor T 6  is turned on by a voltage VP 2  on the second node P 2 , thereby connecting the output line  24   i  (FIG. 8) or  14   i  (FIG. 6) to the ground voltage line VSSL. The fifth and sixth NMOS transistors T 5  and T 6  are turned on in this manner and the first clock signal C 1  has a low logic level, so that a low logic level output voltage Vout emerges at the output line  24   i  (FIG. 8) or  14   i  (FIG.  6 ). 
     Subsequently, the third clock signal C 3  and the output signal g i−1  of the previous stage  22   i−1  transition from a high logic level to a low logic level, whereas the first clock signal C 1  changes from a low logic level to a high logic level. The first and second transistors T 1  and T 2  are turned off by the low logic level of the third clock signal C 3 . On the other hand, the third NMOS transistor T 3  is turned on by a high logic level of the first clock signal C 1  from the first clock terminal CLKA to thereby discharge the charge voltage VP 2  out the second node P 2 , via the drain and source terminals thereof and the drain and source terminals of the fourth NMOS transistor T 4 , onto the ground voltage line VSSL. Thus, a voltage at the second node P 2  has the ground voltage VSS. The sixth NMOS transistor T 6  is turned off by the ground voltage VSS from the second node P 2 , thereby opening or disconnecting the output line  24   i  from the ground voltage line VSSL. As a result, the output line  24   i  charges to the high logic level of the first clock signal C 1  input from the first clock terminal CLKA, via the fifth NMOS transistor TS, thereby generating a high logic level of output voltage Vout as shown in FIG.  9 . At this time, the charge voltage VP 1  at the first node P 1  is coupled with the output line  24   i  by a parasitic capacitor C gs  existing between the gate terminal and the source terminal of the fifth NMOS transistor T 5 , thereby allowing the first node P 1  to be raised by a voltage Vout on the output line  24   i  as shown in FIG.  9 . Thus, the high logic level of the first clock signal C 1  is applied to the output line  24   i  with no attenuation. The i th  row line ROWi of the pixel array is enabled by such a high logic level output voltage Vout. 
     Next, if the first clock signal C 1  transitions from a high logic level into a low logic level, then the third NMOS transistor T 3  is turned off to open or disconnect the second node P 2  from the fourth NMOS transistor T 4 . Also, the output voltage Vout on the output line  24   i  is discharged, via the fifth NMOS transistor T 5 , onto the first clock line CLKA to thereby apply a low logic level of output signal Vout to the i th  row line ROWi. 
     Finally, if the third clock signal C 3  transitions from a low logic level to a high logic level, then the first NMOS transistor T 1  is turned on to discharge the voltage VP 1  charged onto the first node P 1 , into the start pulse input terminal SPT. Thus, a charge voltage VP 1  at the first node P 1  has the ground voltage VSS. Accordingly, the fourth NMOS transistor T 4  is turned off to open or disconnect the third NMOS transistor T 3  from the ground voltage line VSSL. The fifth NMOS transistor T 5  also is turned off by the ground voltage VSS on the first node P 1  to thereby open or disconnect a current path between the first clock terminal CLKA and the output line  24   i . Meanwhile, the second NMOS transistor T 2 , turned on by the high logic level of third clock signal C 3 , delivers the supply voltage VCC on the supply voltage line VCCL onto the second node P 2 . At this time, since the third and fourth NMOS transistors T 3  and T 4  have been turned off, the second node P 2  charges the supply voltage VCC input from the supply voltage line VSSL, via the second NMOS transistor T 2 . Thus, a high logic level of charge voltage VP 2  emerges at the second node P 2 . The sixth NMOS transistor T 6  is turned on by the high logic level of charge voltage VP 2  on the second node P 2  to thereby connect the output line  24   i  to the ground voltage line VSSL. As a result, the output voltage Vout at the output line  24   i  has a low logic level. 
     As described above, the shift register is driven by three-phase clock signals C 1  to C 3  to enlarge an interval between the clock signals. 
     Accordingly, the shift register operates stably, even though a clock delay or an overlap occurs. Also, since a voltage on the output line  24   i  is charged or discharged through the fifth NMOS transistor T 5 , the shift register can dramatically reduce the channel width of the sixth NMOS transistor T 6 . 
     Referring now to FIG. 10, there is shown another embodiment of the stage shown in FIG.  4 . For the sake of convenience, it is assumed that the stage of FIG. 10 is the i th  stage  12   i  wherein i is an odd integer. In FIG. 10, the stage  12   i  includes first and second NMOS transistors T 1  and T 2  connected, in series, between a start pulse input terminal SPT and a first node P 1 , third and fourth NMOS transistors T 3  and T 4  connected, in series, between a second clock terminal CLKB and a second node P 2 , fifth and sixth NMOS transistors T 5  and T 6  connected, in series, between a ground voltage line VSSL and the second node P 2 , a seventh NMOS transistor T 7  connected between the first node P 1  and the output line  14   i , and an eighth NMOS transistor T 8  connected between the second node P 2 , the ground voltage line VSSL, and the output line  14   i . All the gates of the first to fourth NMOS transistors T 1  to T 4  are connected to the second clock terminal CLKB. In the stage of FIG. 10 configured in this manner, a supply voltage line VCCL having been included in the stage shown in FIG. 6 is removed. Also, the first and second NMOS transistors T 1  and T 2  minimize a leakage current from the first node P 1  into the start pulse input terminal SPT when a current path between the first node P 1  and the start pulse input terminal SPT is disconnected. The third and fourth NMOS transistors T 3  and T 4  minimize a leakage current from the second node P 2  into the second clock terminal CLKB when a current path between the second node P 2  and the second clock terminal CLKB is disconnected. The stage of FIG. 10 has a wide operation region in accordance with the minimization of leakage current. 
     The odd-numbered stage  12   i  of FIG. 10 is operated as represented in the waveform diagrams of FIG.  7 . As shown in FIG. 7, the output signal g i−1  of the previous stage  12   i−1  and the second clock signal C 2  change from a low logic level to a high logic level. On the other hand, the first clock signal C 1  applied to the first clock terminal CLKA changes from a high logic level to a low logic level. At this time, the first and second NMOS transistors T 1  and T 2  are turned on such that the output signal g i−1  of the previous stage  12   i  is charged onto the first node P 1 . The sixth NMOS transistor T 6  is turned on by a charge voltage VP 1  charged onto the first node P 1  to connect the fifth NMOS transistor T 5  to the ground voltage line VSSL. The seventh NMOS transistor T 7  also connects the first clock terminal CLKA to the output line  14   i  by the voltage VP 1  charged onto the first node P 1 . On the other hand, the fifth NMOS transistor T 5  is turned off by the low logic level first clock signal C 1  from the first clock terminal CLKA. Thus, a high logic level second clock signal C 2  at the second clock terminal CLKB is charged, via the third and fourth NMOS transistors T 3  and T 4  acting as a diode series circuit, onto the second node P 2 . The eighth NMOS transistor T 8  is turned on by a charge voltage VP 2  at the second node P 2 , so that the output line  14   i  is connected to the ground voltage line VSSL. Since the seventh and eighth NMOS transistors are turned on in this manner and the first clock signal C 1  has a low logic level, a low logic level output voltage Vout emerges at the output line  142   i . 
     Subsequently, the second clock signal C 2  and the output signal g i−1  of the previous stage  12   i−1  transition from a high logic level to a low logic level, whereas the first clock signal C 1  changes from a low logic level to a high logic level. The first to fourth transistors T 1  to T 4  are turned off by the low logic level of second clock signal C 2 . On the other hand, the fifth NMOS transistor T 5  is turned on by the high logic level first clock signal C 1  from the first clock terminal CLKA to thereby discharge the charge voltage VP 2  on the second node P 2 , via the drain and source terminals thereof and the drain and source terminals of the sixth NMOS transistor T 6 , onto the ground voltage line VSSL. Thus, the voltage at the second node P 2  has the ground voltage VSS. The eighth NMOS transistor T 8  is turned off by the ground voltage VSS from the second node P 2 , thereby opening or disconnecting the output line  14   i  from the ground voltage line VSSL. As a result, the output line  14   i  charges to the high logic of first clock signal C 1  input form the first clock terminal CLKA, via the seventh NMOS transistor T 7 , thereby generating a high logic level output voltage Vout as shown in FIG.  7 . At this time, the charge voltage VP 1  at the first node P 1  is coupled with the output line  14   i  by way of a parasitic capacitor C gs  existing between the gate terminal and the source terminal of the seventh NMOS transistor T 7 , thereby allowing the first node P 1  to be raised by a voltage Vout on the output line  14   i  as shown in FIG.  7 . Thus, the high logic level of the first clock signal C 1  is applied to the  14   i  with no attenuation. The i th  row line ROWi of the pixel array is enabled by such a high logic level of output voltage Vout. 
     Consequently, the first clock signal C 1  transitions from a high logic level to a low logic level, whereas the second clock signal C 2  changes from a low logic level to a high logic level. The first and second NMOS transistors T 1  and T 2  are turned on to discharge the charge voltage VP 1  charged in the first node P 1  onto the start pulse input terminal SPT. Thus, the charge voltage VP 1  at the first node P 1  has the ground voltage VSS. Accordingly, the sixth NMOS transistor T 6  is turned off to open or disconnect the fifth NMOS transistor T 5  from the ground voltage line VSSL. The seventh NMOS transistor T 7  also is turned off by the ground voltage VSS on the first node P 1  to thereby open or disconnect a current path between the first clock terminal CLKA and the output line  14   i . 
     Also, the fifth NMOS transistor T 5  also is turned off by the low logic level first clock signal C 1 . As the fifth and sixth NMOS transistors T 5  and T 6  are turned off, the high logic level of second clock signal C 2  at the second clock terminal CLKB is charged, via the third and fourth NMOS transistors T 3  and T 4  serving as a diode series circuit, onto the second node P 2 . 
     Thus, a high logic level of charge voltage VP 2  emerges at the second node P 2 . The eighth NMOS transistor T 8  is turned on by the charge voltage VP 2  at the second node P 2  to connect the output line  14   i  to the ground voltage line VSSL. As a result, the output voltage Vout at the output line  14   i  is discharged onto the ground voltage line VSSL to a low logic level. The stage  12   i  of FIG. 10 may be used as a stage in the shift register of FIG. 8, requiring a three-phase clock. 
     As described above, the shift register according to the present invention may be driven with a two-phase clock signal, so that it can reduce the required number of clock supply lines and hence reduce the number of circuits. In other words, the shift register according to the present invention can simplify the configuration of an external control circuit. Furthermore, the shift register according to the present invention may be operated by a three-phase clock signal, so that it can enlarge an interval between clock signals and can drive the pixel array stably even when a delay or an overlap in the clock signals occurs. 
     Although the present invention has been explained by the embodiments shown in the drawings described above, it should be understood to the ordinary skilled person in the art that the invention is not limited to the embodiments, but rather that various changes or modifications thereof are possible without departing from the spirit of the invention. 
     Accordingly, the scope of the invention shall be determined only by the appended claims and their equivalents.