Abstract:
Various aspects of the technology provide for clamping a transient from a transient generator in a circuit using a Field Effect Transistor (FET) including a compound semiconductor layer forming a drain coupled to the transient voltage generator, a source, and a gate. The gate and the drain may be configured to clamp voltage transients in the circuit from the transient voltage generator independent of a clamping diode between the source and the drain. The FET may be a depletion mode type fabricated using germanium or a compound semiconductor such as gallium arsenide (GaAs) or gallium nitride (GaN).

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation in part and claims the priority benefit of U.S. patent application Ser. No. 13/270,145, filed Oct. 10, 2011 now U.S. Pat. No. 8,274,121 and titled “COMPOUND FIELD EFFECT TRANSISTOR WITH MULTI-FEED GATE AND SERPENTINE INTERCONNECT,” which is a continuation of U.S. patent application Ser. No. 13/205,433, filed Aug. 8, 2011 now U.S. Pat. No. 8,519,916, and titled “LOW INTERCONNECT RESISTANCE INTEGRATED SWITCHES,” which claims the priority benefit of U.S. provisional application No. 61/372,513, filed Aug. 11, 2010, and titled “Field Effect Transistor and Method of Making Same.” The above referenced applications are hereby incorporated by reference in their entirety. 
    
    
     TECHNICAL FIELD 
     The present invention relates to semiconductors devices, and more particularly to compound semiconductor Field Effect Transistor (FET) switches and power FETs. 
     BACKGROUND 
     A common type of Field Effect Transistors (FET) is a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), which may be fabricated using silicon. A typical circuit application for a MOSFET device is a synchronously-rectified step-down (buck) DC-DC converter output stage.  FIG. 1A  is a block diagram illustrating a prior art buck DC-DC converter output stage  10  using a blocking diode  12 . MOSFET devices include an intrinsic body diode that is useful for blocking current surges from an inductor. Blocking diode  12  may represent the intrinsic body diode in the case when device  14  is a MOSFET device. Unfortunately, MOSFET devices are generally larger and slower to turn on than desired because it has a lot of capacitance and a relatively high rate of loss. The body diode losses are a significant factor in the overall switch loss particularly at low current loads. Additional diodes may be used to supplement current blocking inherent in the body diode of a MOSFET. Unfortunately additional diodes increase the cost of a circuit. A compound semiconductor FET (CSFET) such as a GaAs FET or GaN FET is generally not used in rectified step-down buck DC-DC converter circuits or other circuits that include transient sources such as inductors because a GaAs CSFET does not include an intrinsic body diode for blocking current surges. 
     SUMMARY 
     Transients from a source in a circuit, such as an inductor, may be clamped using a depletion mode, compound semiconductor Field Effect Transistor (FET) in the circuit. The FET may be used without a diode in the circuit or in the device for suppressing and/or clamping the transients. 
     Various embodiments of circuits comprise a transient voltage generator or source, and a Field Effect Transistor including a compound semiconductor layer. The compound semiconductor layer forms a drain coupled to the transient voltage generator, a source, and a gate. The gate and the drain may be configured to clamp voltage transients from the transient voltage generator independent of a clamping diode between the source and the drain. 
     Various aspects of a circuit comprise an inductor configured to produce a transient voltage and a body diode-less FET including a source, a gate and a drain fabricated as a depletion mode device on a compound semiconductor substrate. The drain of the FET may be configured to receive the transient voltage from the inductor and render it possible to drive the gate in response to the transient voltage to reduce resistance between the drain and the source for clamping the transient voltage. 
     Various aspects of a converter circuit include an enhancement mode control FET fabricated using gallium arsenide and a depletion mode sync FET coupled to the control FET, the sync FET fabricated using gallium arsenide. The converter circuit further includes an inductor configured to couple a transient voltage to a source of the control FET and a drain of the sync FET. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a block diagram illustrating a prior art (buck) DC-DC converter output stage using a blocking diode. 
         FIG. 1B  illustrates a block diagram of a circuit for a synchronously-rectified power stage using a compound semiconductor FET, in accordance with embodiments of the invention. 
         FIG. 2  illustrates a timing diagram for the circuit of  FIG. 1B . 
         FIG. 3  is a circuit model illustrating details of an embodiment of the sync FET of  FIG. 1B . 
         FIG. 4  illustrates details of a portion of the circuit of  FIG. 1B  showing portions of the circuit model of  FIG. 3 . 
         FIG. 5  illustrates a commutation configuration for a test circuit for measuring parameters of a depletion mode, compound semiconductor FET, in accordance with embodiments of the invention. 
         FIG. 6  is a block diagram illustrating an alternative embodiment of a circuit for a synchronous CSFET active clamp in accordance with various embodiments of the invention. 
         FIG. 7  is a block diagram illustrating an alternative embodiment of a circuit for a synchronous CSFET active clamp, in accordance with various embodiments of the invention. 
         FIG. 8  is a block diagram illustrating an alternative embodiment of a circuit for a synchronous CSFET active clamp, in accordance with various embodiments of the invention. 
         FIG. 9  is a block diagram illustrating an alternative embodiment of a buck DC-DC converter output stage using a compound semiconductor FET for device and blocking diode. 
     
    
    
     DETAILED DESCRIPTION 
     A compound semiconductor FET device presents the user with a device possessing a new benchmark in figure of merit performance. Performance advantages that this device can deliver may be extracted from the operation of the device in an application such as the power switch(es) in a synchronously-rectified DC-DC buck converter and other circuits. A compound semiconductor FET fabricated as a depletion mode device may be used to clamp transient signals. Drive signal levels and timing of the device(s) in a synchronous buck converter application may be selected to prevent cross-conduction/shoot-through of the power switches without the use of intrinsic or extrinsic diodes to block surges from transient sources. While an example of a synchronously-rectified DC-DC buck converter is presented, a depletion mode compound semiconductor FET may be used to clamp transient signals in other circuits. 
       FIG. 1B  illustrates a block diagram of a circuit  100  for a synchronously-rectified power stage using a compound semiconductor FET, in accordance with embodiments of the invention.  FIG. 2  illustrates a timing diagram  200  for the circuit  100  of  FIG. 1B . The power stage circuit  100  of  FIG. 1B  includes a synchronously rectified step-down (buck) DC-DC converter output stage. The circuit  100  includes a control FET  102  (Q 1 ) and a compound semiconductor FET used as a sync FET  112  (Q 2 ). In various embodiments, the sync FET  112  is a depletion mode device fabricated using compound semiconductor material including gallium arsenide (GaAs), gallium nitride (GaN), and/or the like. In some embodiments, the control FET  102  is also a compound semiconductor FET. The control FET  102  may be a depletion mode device or an enhancement mode device. 
     The circuit  100  further includes an inductor  120  (L) and a capacitor  122  (C). A drain  114  of the sync FET  112  may be coupled to the inductor  120  and a source  106  of the control FET  102 . A source  116  of the sync FET  112  may be coupled to ground. A drain  104  of the control FET  102  may be coupled to an input voltage V in . The inductor  120 , drain  114  and source  106  may be coupled at a switching node  126 . 
     A gate  118  of the sync FET  112  and a gate  108  of the control FET  102  may be coupled to a driver  110 . The driver  110  is configured to apply a gate voltage V g1  to the gate  108  of control FET  102  (e.g., turn the control FET  102  on and off), and to apply a gate voltage V g2  to the gate  118  of the sync FET  112  (e.g., turn the control FET  102  on and off) according to timing illustrated in  FIG. 2 . The sync FET  112  of  FIG. 1B  is a depletion mode device configured for a gate pinch off voltage at about −1.0V, a gate full OFF voltage at about −2V, and a gate full ON voltage at about +0.4V, with respect to the source  116 . However, the sync FET  112  may be configured for other pinch OFF voltages, ON voltages, and/or OFF voltages. 
     The output voltage V out  at node  124  of circuit  100  may be determined from the duty cycle (ON time of control FET  102 ) from equation 1:
 
 V   out   =D*V   in   Eq. 1
 
     Where D is the duty cycle of the converter, defined in equation 2 as 
     
       
         
           
             
               
                 
                   D 
                   = 
                   
                     
                       T 
                       
                         ON 
                         ⁡ 
                         
                           ( 
                           
                             Q 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                           ) 
                         
                       
                     
                     T 
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                   ⁢ 
                   2 
                 
               
             
           
         
       
     
     Where T ON(Q1)  is the period of time  222  that control FET  102  is on, and T is the period of time  220  the clock is utilized. In some embodiments, V in  may be about 12 V and V out  may be about 1 volt. A time interval of interest is the time interval just after control FET  102  is turned OFF at time  202  and just prior to when sync FET  112  is turned ON at time  212 , the beginning of the time interval (1-T), as shown in  FIG. 2 . Thus, an interval between Q 1 (ON) and Q 2 (ON) a switching interval that may be selected to prevent turning both the control FET  102  and the sync FET  112  on simultaneously. 
     During the ON time interval  222  of control FET  102 , time T ON(Q1) , the drain current of control FET  102 , which is I d (Q 1 ) flows through control FET  102  into the inductor L. The driver  110  may send a signal to command the gate voltage V g  (Q 1 ) at gate  108  for control FET  102  to an OFF state at time  202 . In response, drain current I d (Q 1 ) may begin to switch to an OFF state at time t d(OFF) , or time  204 . After a fall time of t f  the drain current I d (Q 1 ) through the control FET  102  into the inductor is at an OFF state at time t OFF(Q1) , or time  206 . 
     After a delay, the driver  110  may send a signal to command the gate voltage V g (Q 2 ) at gate  118  for sync FET  112  to an ON state at time  212 . In response, the sync FET  112  may begin to switch to an ON state at t d(ON) , or time  214 . As the sync FET  112  switches to an ON state, current begins to flow through the sync FET  112 . After a rise time of t r  the drain current I d (Q 2 ) through the sync FET  112  is in an ON state at time t ON(Q2) , or time  216 . 
     Two time intervals are of interest. A time interval t bb  is a delay time between time  202  and time  212 , and is a delay time that may be inserted between switching OFF the control FET  102  at time  202  and switching ON the sync FET  112  at time  212  so as to avoid an uncontrolled cross-conduction of current from V in  directly to ground through control FET  102  and sync FET  112 . A time interval t dt , which may also be referred to as the dead time, is a time when both the control FET  102  and sync FET  112  are off between time  206  and time  214 . During the time t dt  uncontrolled voltage transients from the inductor  120  may cause damage to the circuit  100 . 
     A compound semiconductor FET does not have an intrinsic drain-source body diode as found in silicon MOSFET devices. Thus, the time interval t dt  is of interest. During time t dt , both control FET  102  and sync FET  112  are OFF and the inductor  120  may expose the drain of the sync FET  112  to excessive reverse, and potentially destructive, voltage. If the sync FET  112  were provisioned using a silicon MOSFET as illustrated in  FIG. 1A , a body diode  12  such as is intrinsically present in silicon MOSFET devices, such as device  14 , would serve to provide protection from voltage transients produced by the inductor  120  during t dt  by clamping such negative voltage transients to the forward voltage of the body diode. However, a compound semiconductor FET such as sync FET  112  illustrated in  FIG. 1B  does not have a body diode. 
     What has not been previously appreciated is that a circuit design such as circuit  100  may use a sync FET  112  that is fabricated as a depletion mode device using compound semiconductor materials. Such sync FET  112  may be used without a diode in the circuit and without a diode fabricated into the device. The depletion mode, compound semiconductor sync FET  112  may nonetheless prevent deleterious, uncontrolled voltage or current conditions that occur in circuits having transients, such as circuit  100  during the time interval t dt . The inventor has found a voltage clamping property that occurs in compound semiconductor FET devices that may be used instead of a MOSFET in switching circuit designs that include transient sources, such as inductor  120  of the circuit  100 . A circuit may be designed to use the voltage clamping property of the compound semiconductor sync FET  112 , instead of the body diode of a MOSFET, to protect a circuit from breakdown or damage resulting from transients generated, for example, in the inductor  120  of circuit  100 . Thus, for example, sync FET  112  of circuit  100  may be a depletion mode device fabricated from compound semiconductor materials, and configured to clamp transient voltages from the inductor  120 . 
       FIG. 3  is a circuit model  300  illustrating details of an embodiment of the sync FET  112  of  FIG. 1B .  FIG. 4  illustrates details of a portion of the circuit  100  of  FIG. 1B  showing portions of the circuit model  300  of  FIG. 3 . A look at the inter-electrode model of the sync FET  112  may aid in further understanding the circuit operation of the sync FET  112 . The model  300  for sync FET  112  illustrated in  FIG. 3  includes a channel  302 , a drain Schottky diode  304 , a source Schottky diode  306 , a drain resistor  314  (Rd), and a source resistor  316  (Rs). Referring to  FIG. 4 , a drain-source resistor  402  (R ds ) may be equivalent to a sum of the drain resistor  314  and the source resistor  316 . That is, R ds =R d +R s . When the sync FET  112  is in an ON state, resistance of the drain-source resistor  402  R ds(ON)  may be very low, for example, about 0.01 Ohms.  FIG. 4  illustrates a direction of the current I(L) during the OFF state of the control FET  102  when the drain  114  of the sync FET  112  (Q 2 ) is at a negative voltage and sync FET  112  is either clamping the voltage at the drain  114  or in an ON state. 
     Referring again to  FIG. 3 , the model  300  further includes a gate drain capacitor  324 , a gate source capacitor  326 , and a drain source capacitor  328 . The channel  302  may be represented by the drain-source resistor  402  in  FIG. 4 . The resistance between the drain  114  and the source  116  depends on voltage at the gate  118  with reference to the source  116 . As the channel  302  resistance of the drain-source resistor  402  decreases, it forms a reasonably low resistance path for the negative current to flow to ground, and provides for self-clamping of the voltage across the channel  302 . Voltage is described in an algebraic sense. Thus, for example, −4 volts is less than −2 volts, and +2 volts is greater than −4 volts. 
     During the time interval  226  that sync FET  112  is turned off, the gate  118  of circuit  100  is held at the potential V g , which is a potential less than the pinch off voltage (V p ), which is about −1.0 volts. For example, V g  (Q 2 ) may be held at about −2 volt. When the control FET  102  turns off, at time  206 , the voltage potential at the switching node  126 , will make a negative excursion towards a large negative value because of transient current from the inductor  120 . When the switching node  126 , which is also the drain of sync FET  112 , falls just below a clamping voltage, (V clamp ) the channel begins to turn to an ON state (albeit weakly) and then the voltage at the switching node  126  will become clamped at the approximately value V clamp . V clamp  may be determined from:
 
 V   clamp   =V   g(Q2)   −V   fgd   Eq. 3
 
Where V fgd  is the forward voltage of the gate-drain Schottky diode. In some embodiments, V g  (Q 2 ) is about −2V and V fgd  is about −0.7 V. Thus, V clamp  may be about −2.7 V.
 
     The drain-source resistance  402  during conditions that obtain during the time interval between time  206  and time  216  may typically be about 5-10 times that of the R ds(ON)  of the device. A typical resistance for R ds(ON)  is about 10 milli-ohm. So, resistances on the order of 50-100 milli-ohm may describe the channel resistance R ds . 
     A power dissipation during this time may be given by: 
     
       
         
           
             
               
                 
                   
                     P 
                     clamp 
                   
                   = 
                   
                     
                       I 
                       Lp 
                       2 
                     
                     * 
                     
                       R 
                       ds 
                     
                     * 
                     
                       
                         t 
                         dt 
                       
                       T 
                     
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                   ⁢ 
                   4 
                 
               
             
           
         
       
     
     Where I Lp  is the peak value of the inductor current. The peak value of the inductor current I Lp  may be calculated from an average current (I La ) of the inductor plus one half a ripple current (I Lr ), or
 
 I   Lp   =I   La +(0.5 *I   Lr )  Eq. 5
 
     For example, using some typical values: 
     R ds =75 milliohms 
     I Lp =23 A 
     I La =20 A 
     I Lr =6 A 
     t cc =20 ns 
     T=1.33 us (a 750 kHz switching frequency) 
     and applying Eq. 4 and Eq. 5, the average power dissipated in the sync FET  112  is about 23 A 2 *0.075 ohm=600 mW. A voltage to which the drain of the sync FET  112  will be clamped may be calculated as:
 
 V   clamp   =I   La +(0.5 *I   Lr   *R   ds )=−23*0.075=−1.75V.
 
Since no minority carriers are involved, there is no reverse recovery time involved.
 
     A calculation of P conduction , which is the power dissipated by sync FET  112  due to conduction during the ON state of the sync FET  112  may be calculated from the relation: 
     
       
         
           
             
               
                 
                   
                     P 
                     conduction 
                   
                   = 
                   
                     
                       I 
                       La 
                       2 
                     
                     * 
                     
                       R 
                       
                         ds 
                         ⁡ 
                         
                           ( 
                           ON 
                           ) 
                         
                       
                     
                     * 
                     
                       
                         T 
                         
                           ON 
                           ⁡ 
                           
                             ( 
                             
                               Q 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               2 
                             
                             ) 
                           
                         
                       
                       T 
                     
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                   ⁢ 
                   6 
                 
               
             
           
         
       
     
     If an input voltage V in  of about 12 V and an output voltage of about 1 Vdc is assumed, then the duty cycle for the converter (the ON time interval  222  of the control FET  102 ) is about 1/12=0.083. This means that the duty cycle for the Sync FET  112  is about 1−0.083=0.917 (91.7%.). That is also the time interval  228  that sync FET  112  is in the ON state divided by the total time interval T. Note that  FIG. 2  is not to scale. Assuming typical values of: 
     I La =20 A, 
     
       
         
           
             
               
                 T 
                 
                   ON 
                   ⁡ 
                   
                     ( 
                     
                       Q 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                     
                     ) 
                   
                 
               
               T 
             
             = 
             0.917 
           
         
       
     
     R ds(ON) =0.01 ohm. 
     The conduction power during the ON state  228  of the sync FET  112  may be calculated from Eq. 6. For example, using the values above, P conduction  conduction may be calculated to be P conduction =400*0.01*0.917=3.67W. 
     A compound semiconductor may have fast switching speeds compared to other commercially-available semiconductor switching devices. In some embodiments, these times may be 3 ns for the rise time and 1 ns for the fall time. The value of P switching  is then given by 
     
       
         
           
             
               
                 
                   
                     P 
                     switching 
                   
                   = 
                   
                     
                       ( 
                       
                         0.5 
                         * 
                         
                           I 
                           La 
                         
                         * 
                         
                           V 
                           sw 
                         
                         * 
                         
                           
                             t 
                             r 
                           
                           T 
                         
                       
                       ) 
                     
                     + 
                     
                       ( 
                       
                         0.5 
                         * 
                         
                           I 
                           La 
                         
                         * 
                         
                           V 
                           sw 
                         
                         * 
                         
                           
                             t 
                             f 
                           
                           T 
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   Eq 
                   . 
                   
                       
                   
                   ⁢ 
                   7 
                 
               
             
           
         
       
     
     Where V sw  is the voltage at the switching node  126 , determined from:
 
 V   sw   =V   clamp   −V   conducting ,
 
and
 
 V   conducting   =I   La   *R   ds (on)
 
and
 
 V   sw =1.75−(23*0.01)=1.52V
 
     Therefore
 
 P   switching =(0.5*23*1.52*0.003/1.33)+(0.5*23+1.52*0.001/1.33)=52 mW.
 
     A compound semiconductor FET may have a very low gate charge compared to other commercially-available semiconductor switching devices. In some embodiments, the gate charge is lower than about 1 nano-coulomb (nC). A typical gate charge for the sync FET  112  may be about 0.8 nC. The power loss due to gate drive associated with this charge may be calculated from the relation:
 
 P   gate   =Q   g   *V   g   *f   sw   Eq. 8
 
     Where Q g  is the total gate charge (e.g., 0.8 nC), V g  is the total gate-source voltage deviation (e.g., +0.5 to −2.0V=2.5V) and f sw  is the PWM switching frequency (e.g., 750 kHz). Given the above values, P gate =0.8*10 −9 *2.5*750000=15 mW. 
     In some embodiments, a total power dissipation of the sync FET  112  may be calculated from the relation:
 
 P   total   =P   clamp   +P   conduction   +P   gate   +P   switching   Eq. 9
 
For the above examples, the total power may be calculated as P total =0.600+3.67+0.052+0.015=4.33W.
 
     If an adequate copper etch layout and area are provisioned on an application printed circuit board for the sync FET  112 , then this power dissipation can be safely accommodated by the device, resulting in a reliable operating temperature and high conversion efficiency. 
       FIG. 5  illustrates a commutation configuration for a test circuit  500  for measuring parameters of a depletion mode, compound semiconductor FET  502 , according to embodiments of the invention. The FET  502  includes a source  516  coupled to ground, a drain  514  coupled to a current source  504 , and a gate  518  coupled to a gate voltage control  528  V gg  fixed at −2.00 Volts. A voltage source  510  was set to −5.0V (V in ) and a fixed gate voltage of −2.00 Vdc was applied to the gate  518 . The current source  504  applied a drain current (Id) from −0.1 to −5.0 amps to the drain  514 . A drain-source voltage (V ds ) through the FET  502  was measured at the drain  514 . A drain clamping voltage was determined to be about −1.2 volts. 
     A Table 1 illustrates experimental results using the circuit  500  illustrated in  FIG. 5 . The column labeled “I d ” shows the drain current in amps provided from the current source  504 . The column labeled “V ds ” shows the drain-source voltage measured at the drain  514  relative to the source  516 . The column labeled “I g ” shows the gate current in micro-amps through  506 . The column labeled “Resistance” is the resistance in ohms of a channel through the FET  502  calculated from the drain current Id and the drain-source voltage V ds . The column labeled “Power” is the power in watts calculated from the drain current Id and the drain-source voltage V ds . 
     
       
         
               
               
               
               
               
             
               
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                   
                   
                   
                 Resistance  
                 Power 
               
               
                 I d  (A) 
                 V ds  (V) 
                 I g  (uA) 
                 (Ohms) 
                 (Watts) 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 −0.1 
                 −1.24 
                 1.24 
                 12.40 
                 0.12 
               
               
                 −0.2 
                 −1.26 
                 1.50 
                 6.30 
                 0.25 
               
               
                 −0.3 
                 −1.28 
                 1.60 
                 4.27 
                 0.38 
               
               
                 −0.4 
                 −1.29 
                 1.70 
                 3.23 
                 0.52 
               
               
                 −0.5 
                 −1.30 
                 1.70 
                 2.60 
                 0.65 
               
               
                 −1.0 
                 −1.33 
                 2.30 
                 1.33 
                 1.33 
               
               
                 −1.5 
                 −1.36 
                 3.60 
                 0.91 
                 2.04 
               
               
                 −2.0 
                 −1.37 
                 5.70 
                 0.69 
                 2.74 
               
               
                 −3.0 
                 −1.40 
                 14.90 
                 0.47 
                 4.20 
               
               
                 −4.0 
                 −1.41 
                 52.00 
                 0.35 
                 5.64 
               
               
                 −5.0 
                 −1.42 
                 91.00 
                 0.28 
                 7.10 
               
               
                   
               
             
          
         
       
     
     It was determined that for the FET  502 , the drain clamping voltage breakpoint for low currents is about −1.20V, and that the channel resistance is about 37 milliohms for the FET  502 . At low currents it appears that the gate  518  is not conducting current, thus, operation of the FET  502  is a result of a channel effect. However, as the drain current (I d ) increases, the drain-source voltage (V ds ) increases in absolute value (becomes more negative) and approaches the magnitude of the gate voltage. 
     Accordingly, it can be seen that a compound semiconductor FET can be used to self-commutate transient currents during the dead time delay period and can result in safe, efficient and reliable circuit operation. In some embodiments, power losses incurred add approximately 0.6 W, which is about 20% to the circuit operation at an operating frequency of 750 kHz, an output voltage of 1.00 Vdc and a load current of 20 A. 
     The following are a set of prophetic examples of circuit design techniques for using a depletion mode compound semiconductor FET coupled to transient source for clamping transients: 
     In some embodiments, the ON/OFF swing of the gate-source voltage may be maintained as small as practical for sync FET  112 . A V gs(OFF)  of −3V and a V gs(ON)  of ≈0.2V may be used for a  20 A circuit application. 
     The V gate  bias supply may be bypassed. Several decades of low ESR ceramic capacitors (e.g. 0.1 uF, 0.01 uF, 0.001 uF and 100 pF) of at least 0805 size may be used to reduce the net impedance of the bypass capacitance below resonance during the time interval (t dt .) 
     A shorter time interval t dt  may reduce switching power. The compound semiconductor FET may have very fast switching times. In some embodiments, t ON  and t OFF  are less than 5 ns. In some embodiments it is possible to reduce the dead time interval, t dt , to less than 10 ns. 
     Reducing the clamping losses to less than 750 mW by minimizing V clamp  and t dt  may help to avoid catastrophic thermal damage to the device and insure reliable operation. 
     The circuit  100  is configured as an output stage for a DC-DC convertor including an inductor and is illustrative of use of a compound semiconductor FET in a circuit including transient sources. However, other circuits that include transient sources may include a compound semiconductor FET for suppressing and/or clamping transients. 
       FIG. 6  is a block diagram illustrating an alternative embodiment of a circuit  600  for a synchronous CSFET active clamp  602  in accordance with various embodiments of the invention. The circuit  600  of  FIG. 6  uses a fixed negative gate bias (−Vgg) at gate  604 , which is provided by a semiconductor switch  606  (S 2 ) to achieve a clamping level at the switching node  608  (Vsw). 
       FIG. 7  is a block diagram illustrating an alternative embodiment of a circuit  700  for a synchronous CSFET active clamp  702 , in accordance with various embodiments of the invention. The circuit  700  of  FIG. 7  uses a gate-side negative gate bias (−Vgg) provided to the gate  704  using a Schottky diode at clamping diode  706  (Dgate) to achieve a clamping level at the switching node  708  (Vsw). 
       FIG. 8  is a block diagram illustrating an alternative embodiment of a circuit  800  for a synchronous CSFET active clamp  806 , in accordance with various embodiments of the invention. The circuit  800  of  FIG. 8  uses a second compound semiconductor device for the active CSFET  806  (Q 3 ) in parallel with a synchronous switch device  802  (Q 2 ). The active clamp CSFET  806  is configured to achieve a clamping level at the switching node  808  (Vsw). The active clamp CSFET  806  may be provisioned with a fixed negative gate bias (−Vgg) at gate  804  and may be provisioned to freely switch ON/OFF such that a clamping function is decoupled from the synchronous switch device  802 . The embodiment illustrated in  FIG. 8  may be useful for reducing power losses due to the synchronous switch device  802 . 
       FIG. 9  is a block diagram illustrating an alternative embodiment of a buck DC-DC converter output stage  900  using a compound semiconductor FET for device  904  and blocking diode  902 . A compound semiconductor FET such as a GaAs FET is generally not used for device  904  in rectified step-down buck DC-DC converter circuits  900  or other circuits that include transient sources such as inductors because a GaAs FET does not include an intrinsic body diode for blocking current surges. In some embodiments, a blocking diode  902  may be provisioned in a CSFET during fabrication of the device  904 . Similarly, a blocking diode  902  may be used as an additional component in the circuit design  900 . However, these alternatives may result in increased cost, complexity, size, and parts count of the circuit  900 . 
     As used in this specification, the terms “include,” “including,” “for example,” “exemplary,” “e.g.,” and variations thereof, are not intended to be terms of limitation, but rather are intended to be followed by the words “without limitation” or by words with a similar meaning. Definitions in this specification, and all headers, titles and subtitles, are intended to be descriptive and illustrative with the goal of facilitating comprehension, but are not intended to be limiting with respect to the scope of the inventions as recited in the claims. Each such definition is intended to also capture additional equivalent items, technologies or terms that would be known or would become known to a person having ordinary skill in this art as equivalent or otherwise interchangeable with the respective item, technology or term so defined. Unless otherwise required by the context, the verb “may” indicates a possibility that the respective action, step or implementation may be performed or achieved, but is not intended to establish a requirement that such action, step or implementation must be performed or must occur, or that the respective action, step or implementation must be performed or achieved in the exact manner described. 
     The above description is illustrative and not restrictive. This patent describes in detail various embodiments and implementations of the present invention, and the present invention is open to additional embodiments and implementations, further modifications, and alternative constructions. There is no intention in this patent to limit the invention to the particular embodiments and implementations disclosed; on the contrary, this patent is intended to cover all modifications, equivalents and alternative embodiments and implementations that fall within the scope of the claims. Moreover, embodiments illustrated in the figures may be used in various combinations. Any limitations of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims along with their full scope of equivalents.