Abstract:
A control circuit for a piezo transformer based power supply for a fluorescent lamp includes driver circuitry generating pulse waveforms for providing excitation to primary inputs of the piezo transformer, and circuitry for regulating lamp current and the voltage across the piezo transformer primary inputs. The frequency of the pulse waveforms is varied in response to the magnitude of lamp current to maintain a predetermined desired lamp current as represented by a current reference signal. The duty cycle of the driver circuitry is varied in response to the magnitude of the voltage across the piezo transformer primary inputs to maintain a predetermined desired piezo primary voltage as represented by a voltage reference signal. The piezo transformer is operated as close to resonance as possible, contributing to greater circuit efficiency. The driver circuitry in the control circuit employs four transistors arranged as a full bridge with respect to the piezo transformer primary inputs. The phase of drive signals supplied to one pair of the transistors is varied with respect to the phase of drive signals supplied to the other pair, thereby varying duty cycle and average voltage of the piezo transformer primary inputs. A controller integrated circuit contains a number of components of the control circuit, enabling its use in a variety of piezo-based power supply applications.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims priority under 35 U.S.C. §119(e) of provisional application No. 60/149,978 filed Aug. 20, 1999. 
    
    
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
     Not Applicable 
     BACKGROUND OF THE INVENTION 
     The present invention is related to the field of power circuits, and more particularly to power supply circuits using piezoelectric transformers to supply power to fluorescent lamps. 
     Recent advances in ceramics technology have yielded a new generation of so-called “piezoelectric transformers” (also referred to herein as “piezo transformers”) that are useful in certain applications. These devices, which are constructed using laminated thin layers of ceramic material, exploit a well-known phenomenon called the “piezoelectric effect” to provide AC voltage gain, in contrast to the magnetic field effects relied upon by conventional wound transformers. Like conventional transformers, piezo transformers are fairly rugged and can be used to obtain voltage gain in high-voltage applications. Additionally, due to their thin profile, piezo transformers can be used in applications where bulkier wire-wound transformers are impractical. For example, piezo transformers are used in power supplies that provide high-voltage power to fluorescent lamps used as backlights in portable computers. Due to their thin profiles, piezo transformers used in such applications do not adversely affect the desired sleekness of the portable computer enclosure. 
     Piezo transformers have recommended operating voltage ratings, arising in part from their ceramic construction. If the input and/or output voltage of a piezo transformer is not within the ratings of the device, then undesirable conditions such as unstable operation, overheating, or failure of the piezo transformer may result. It is therefore important that power supply circuits using piezo transformers comply with these operating voltage ratings. 
     Piezo transformers operate most efficiently when operated at frequencies at or near a multiple of a fundamental resonant frequency, which is a function of mechanical characteristics of the transformer such as material type, dimensions, etc. However, piezo transformers are high-impedance devices, and therefore their resonance characteristics as well as other characteristics are sensitive to the loading of the transformer output in operational circuits. Resonant frequency, voltage gain at the resonant frequency, and sharpness of the gain-versus-frequency curve all diminish with increased loading. 
     The diminishing of resonant frequency and gain with an increase in loading are purposely exploited when a piezo transformer is used to drive a fluorescent lamp. The frequency of the signal applied to the primary inputs of the piezo transformer is slowly swept from a frequency higher than the unloaded resonant frequency toward lower frequencies. As the resonant frequency is approached, the gain increases to the point that the transformer output voltage is sufficiently high to “strike”, or initiate conduction in, the lamp. Once the lamp begins conducting, it presents a much higher load to the transformer, causing the voltage gain and therefore the output voltage of the transformer to drop considerably. The conduction characteristics of the lamp are such that it continues to conduct current at the reduced voltage, so the circuit then enters a stable, lower-voltage operating condition. The intensity of the lamp is regulated by controlling the frequency of the AC drive supplied to the piezo transformer as a function of the lamp current. 
     There are numerous portable computers and other devices in use today, and therefore a number of different configurations of power supply circuits for fluorescent lamps used for backlighting or other purposes. Each unique circuit entails costs associated with design, testing, qualification, fabrication and maintenance. Additionally, each circuit is generally designed to operate with one or at most a limited number of different sets of operating parameters, such as the permissible range of lamp current, the DC voltage from which the power supply circuit obtains power, and other parameters. One circuit may be incapable of operation in other environments, or at best may operate with only low efficiency. 
     BRIEF SUMMARY OF THE INVENTION 
     In accordance with the present invention, a control circuit for a piezo transformer based power supply for a fluorescent lamp is disclosed that can be readily adapted to be used in a variety of operating environments, and has features ensuring that optimum efficiency is attained despite the variability of key operational parameters such as DC supply voltage. 
     The disclosed control circuit includes driver circuitry that supplies respective pulse waveforms to the primary inputs of the piezo transformer, and circuitry for regulating the current in the fluorescent lamp and the voltage across the primary inputs of the piezo transformer. The lamp current regulating circuitry detects the magnitude of current in the fluorescent lamp and varies the frequency of the pulse waveforms generated by the driver circuitry so as to maintain a predetermined desired lamp current, as represented by a predetermined current reference signal. The piezo primary voltage regulating circuitry detects the magnitude of the voltage across the primary inputs of the piezo transformer, and varies the duty cycle of the driver circuitry so as to maintain a predetermined desired piezo primary voltage, as represented by a predetermined voltage reference signal. 
     In the disclosed system, efficiency is improved by operating the piezo transformer at its optimal gain (i.e., the ratio V out /V in ) The value of V out  is determined by the magnitude of lamp current, which in turn is determined by the desired lamp intensity. The RMS voltage value at the piezo transformer primary is programmed such that as the system&#39;s DC input voltage is varied (for example from 7 to 22V in the case of a typical notebook computer), the RMS voltage at the piezo transformer primary is held constant. This results in a constant gain and an operating frequency optimized for the piezo transformer. Also, the RMS input voltage to the piezo primary can be programmed to change with lamp load in order to optimize the gain and frequency as the dimming level of the lamp is changed. The piezo transformer can be operated within its recommended operating region despite large variations in the the system&#39;s DC input voltage and/or lamp load. 
     The disclosed driver circuitry employs four switching transistors arranged as a full bridge with respect to the primary inputs of the piezo transformer. The switching transistors include a first pair for providing a positive pulse to the piezo primary, and a second pair for providing a negative pulse to the piezo primary. Phase shifting circuitry is used to vary the phase of drive signals supplied to the second pair of switching transistors with respect to the phase of drive signals supplied to the first pair of switching transistors so as to maintain the desired voltage across the piezo primary. 
     A disclosed controller integrated circuit contains a number of components connected to input/output pins such that the integrated circuit can be used in a variety of piezo-based power supply applications. 
     Other aspects, features, and advantages of the present invention are disclosed in the detailed description that follows. 
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
     The invention will be more fully understood by reference to the following Detailed Description in conjunction with the Drawing, of which: 
     FIG. 1 is a block diagram of a piezo transformer based power supply for a cold cathode fluorescent lamp (CCFL) as known in the art; 
     FIG. 2 is a diagram illustrating the operation of a piezo transformer as known in the art; 
     FIG. 3 is a schematic diagram representing a model of a piezo transformer as known in the art; 
     FIG. 4 is a plot of the gain characteristics with respect to loading of piezo transformers as known in the art; 
     FIG. 5 is a plot of lamp voltage and impedance characteristics with respect to current of CCFLs as known in the art; 
     FIG. 6 is a schematic diagram of a CCFL power supply circuit according to the present invention; 
     FIG. 7 is a block diagram of a controller circuit used in the CCFL power supply circuit of FIG. 6; and 
     FIG. 8 is a timing diagram illustrating the operation of the CCFL power supply of FIG.  6 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The disclosure of provisional application No. 60/149,978 filed Aug. 20, 1999 is hereby incorporated by reference herein. 
     FIG. 1 shows a prior art arrangement for providing power to a cold cathode fluorescent lamp (CCFL)  10 . The CCFL  10  is driven by the secondary-side output of a piezo transformer  12 . The primary-side inputs to the piezo transformer  12  are provided by controller and driver circuitry  14 . As indicated by the dotted line, the operating current of the CCFL is sensed and provided to the controller  14  as feedback, enabling the controller  14  to regulate the lamp current and thus the lamp intensity. 
     FIG. 2 depicts the operation of the piezo transformer  12 . The piezo transformer  12  operates in what is referred to as a “longitudinal mode” in which mechanical motion in the thickness direction T causes motion in the longitudinal or length direction L. An AC voltage V in  applied to primary-side electrodes (not shown) generates mechanical expansion and compression in the thickness direction T. The mechanical displacement in the thickness direction T is transferred to the longitudinal direction L. The longitudinal mechanical displacement induces an output voltage V out  at a secondary-side electrode (not shown). 
     The piezo transformer  12  provides a voltage gain whose value depends on several factors. For a given material, the gain is related to the dimensions of the device as well as the number of layers used for the primary-side electrodes:          V        (   gain   )       ∼       Length   ·   layers     thickness                            
     Efficient energy transfer is achieved by operating the device near resonance. Resonance occurs at multiple standing wave frequencies f n  based on the transformer&#39;s length (L) and the velocity (v) of mechanical wave propagation:          f   n     =     n        υ     2      L                                
     As shown in FIG. 2, mechanical supports  20  are placed at locations ¼ and ¾ along the length of the piezo transformer  12 , which allows the piezo transformer  12  to generate standing waves having wavelength L. 
     FIG. 3 shows an equivalent electrical circuit model for the piezo transformer  12 . A large primary capacitance C in  arises from the multi-layer construction of the primary-side electrodes. The value of the capacitance C in  is given below, where L is transformer length, W is width, and T is thickness:          C   in     ≈       L   ·   W   ·   layers   ·   ɛ       2   ·   T                              
     An output capacitance C out  is formed between the secondary electrode and the primary electrodes. Since the secondary electrode is small and the distance from the primary is large, output capacitance is typically only tens of picofarads.          C   out     ≈       2   ·   T   ·   W   ·   ɛ     L                            
     A piezo transformer has many resonant frequencies, and a different gain-versus-frequency characteristic in the neighborhood of each. When operation at or near a given resonant frequency is desired, it is advisable that the piezo transformer be excited by a sinusoidal signal, in order to avoid undesired resonant frequencies. The value of what can be called the “fundamental” resonant frequency (w o ) is proportional to the elasticity (Y) and density (p) of the material, as well as the length, as follows:          ω   0     ∝       1   Length            Y   ρ                                
     The piezoelectric gain near a single resonant frequency can be modeled by a series R, L, and C circuit as depicted in FIG.  3 . For such a circuit, the resonant frequency and “Q” or sharpness of its response are given by the following:          ω   0     =         1       L   ·   C                       Q     =       ω   0     ·     L   R                                
     FIG. 4 shows a plot of gain versus frequency for a typical piezo transformer with four different output load values R L . As shown, the resonant frequency diminishes from about 72.5 KHz to about 67 KHz as the value of R L  diminishes from 2.5 MΩ to 100 KΩ. Also, the peak and average gain diminish with diminishing load resistance as shown. 
     FIG. 5 shows the voltage-versus-current and impedance-versus-current characteristics of a typical CCFL such as the CCFL  10 . As shown, it is necessary to provide an increasing lamp voltage to bring the lamp current up to about 1 mA, and the required lamp voltage decreases with further increases in lamp current. The lamp impedance, which is the ratio of voltage to current, is thus very high at low current levels, and falls to a much lower value as current rises. 
     The characteristics of the piezo transformer  12  and the CCFL  10  as shown in FIGS. 4 and 5 are exploited to control the supply of power to CCFL  10 . When the CCFL  10  is unlit, it provides essentially infinite load resistance. As a result, the gain characteristic of the piezo transformer  12  resembles the upper curve in FIG.  4 . The controller  14  generates an input voltage V in  having a frequency at or near the resonant frequency. As a result, the output voltage V out  attains a sufficiently high value to “strike” the lamp, or cause the lamp to being conducting current and emit light. 
     Once the CCFL  10  is conducting sufficient current, its impedance drops considerably, as shown in FIG.  5 . This change significantly increases the loading of the piezo transformer  12 . As a result, the gain characteristic of the piezo transformer  12  shifts toward the lower curve in FIG. 4, i.e., its gain and resonant frequency shift to lower values. The controller  14  automatically reduces the frequency of the input voltage signal V in  in order to reduce the voltage gain of the piezo transformer  10  to a point where the desired operating current is reached. 
     FIGS. 6 and 7 show detailed schematic diagram of a piezo-based power supply for a CCFL. In FIG. 6, several components are shown having connections to a controller  30 , the details of which are shown in FIG.  7 . The controller  30  can be realized as a single integrated circuit (IC) that interfaces to external circuitry by input/output pins labeled as shown. As a separate component, a single-IC controller can be flexibly used in a variety of different CCFL power supply circuits. As shown in FIG. 7, the controller  30  includes switching transistors Q 1 , Q 2 , Q 3  and Q 4 , which implement a full bridge inverter circuit in the circuit of FIG. 6. A voltage controlled oscillator (VCO)  40  generates a variable frequency signal used to drive the transistors Q 1 -Q 4 . The transistors Q 1  and Q 2  are driven in phase with the VCO signal and at ½ its frequency. A phase shifter circuit  42  is used to provide a variable phase shift to the signal driving the transistors Q 3  and Q 4 . This operation is described below. The controller  30  also includes an error amplifier (EA)  44 , voltage amplifier (VA)  46 , difference amplifier (DA)  48 , and circuitry  50  that performs miscellaneous functions such as undervoltage detection, shutdown, and open lamp detection. 
     Referring back to FIG. 6, the controller  30  provides pulse waveform drive to the piezo transformer  12  via pins labeled OUT 1  and OUT 2 . An inductor L 1  is placed in series between OUT 1  and the piezo to create a tank circuit with the input capacitance of the piezo transformer  12 , as described above. The pulse waveform from the controller  30  provides excitation for the tank circuit, resulting in a substantially sinusoidal voltage across the piezo primary. 
     The current through the CCFL  10  is detected by a circuit including diodes D 1 A and D 1 B and resistors R 17  and R 11 . The magnitude of the current is represented as a voltage applied to one input of the EA  44  via a pin labeled EA−. The other input to the error amplifier, via pin EA+, is a reference voltage developed by a network of resistors R 6 -R 10  and a 3 volt reference signal REF generated by the controller  30 . As shown, an externally generated dimming control signal can be supplied to this network to effect dimming of the CCFL  10 . 
     The output of the error amplifier  44  is provided to a network including capacitors C 3  and C 4  and resistors R 1  and R 2 , which are used to establish the range of operating frequencies of the VCO  40 . In conjunction with the capacitor C 4  and the resistor R 11 , the error amplifier  44  integrates the output of the current sensing circuitry, and this integrated value affects the operating frequency of the VCO  44  by its influence at the OSC pin. 
     The circuit of FIGS. 6 and 7 operates from a DC supply voltage V input  that can range from 6 to 24 volts. Power regulation circuitry within the controller  30  (not shown) is used to generate desired operational voltages for the various on-chip components. As shown in FIG. 7, the transistors Q 1  and Q 3  provide switched paths between the DC supply voltage (labeled VDD within controller  30 ) and the output pins OUT 1  and OUT 2  respectively. 
     Referring to FIG. 6, the voltage between nodes VD 1  and VD 2 , which is the voltage across the primary of the piezo transformer  12 , is sampled by an amplifier circuit including the DA  48  of FIG.  7  and resistors R 14 , R 16  and R 17 . The output of the DA  48  is connected to one input of an integrating amplifier circuit including the VA  46  of FIG. 7, resistor R 12 , and capacitor C 5 . The output of the VA  46  provides a control signal for the phase shifter circuit  42  of FIG.  7 . 
     As described above, the current through the CCFL  10  is controlled by adjusting the frequency of operation. The voltage at the pin EA+ represents the magnitude of the lamp current in accordance with the following:                V     EA   -       =       I   lamp     ·   R17   ·       2     π               (   eq1   )                                
     The EA  44  regulates the lamp current to a level set by the externally supplied dimming control voltage. When this voltage is in the range of 0-3 volts, it affects the voltage at pin EA+ as follows:                V     EA   +       =       3        V   ·     [       R5   //   R6         R7   +   R5     //   R6       ]         +       V   DIM          [       R5   //   R7         R6   +   R5     //   R7       ]                 (   eq2   )                                
     Once R 5  is selected, R 6  and R 7  can be determined from the following equations:              R6   =       R5   ·     (       3      V     -     V     MAXEA   -         )         (       V     MAXEA   -       -     V     MINEA   -         )               (   eq3   )               R7   =       R5     V     MINEA   -              (       3      V     -     V     MAXEA   -         )               (   eq4   )                                
     As an example, if 5 mA lamp current and a 5:1 dimming range are desired, the value of resistor R 17  may be chosen as 750 ohms. As a result, the voltage VEA+ falls within the range 1.7 V to 0.35 V. If resistor R 5  is set to 20 KΩ, then R 6  and R 7  are calculated from equations 3 and 4 to be 20 KΩ and 75 KΩ respectively. Substituting these values into equations 1 and 2 (and assuming VEA+=VEA+ in closed loop operation) results in the following relationship for dimming operation:          I   lamp     =         0.35   +     0.45   ·     V   DIM         338                     (for FIG. 1)                              
     When the current through the CCFL  10  is below the level programmed at pin EA+, the output of the EA  44  increases and causes the operating frequency generated by the VCO  40  to decrease. When lamp current is greater than the programmed level, the opposite occurs. The operational frequency range is programmed at the OSC pin using resistors R 1  and R 2  and capacitor C 3 . Voltage controlled oscillation occurs by allowing the voltage at the OSC pin to decay from 3 volts to 1 volt. The decay time is determined by the value of C 3  and the discharge (or charge) current generated in R 1  and R 2 . When the voltage at the OSC pin reaches 1 volt, a gated current source (not shown) within the VCO  40  is turned on and drives the voltage at the OSC pin back to 3 volts. The nominal frequency at OSC is set by R 1  and C 3  in accordance with the following:                f   nom     =       1     R1   ·   C3   ·     ln        (   3   )                         Hz             (   eq5   )                                
     With R 1 =18 KΩ and C 3 =360 pF, the nominal frequency of the oscillator is 140 kHz. As indicated above, the transistors Q 1 -Q 4  switch at one-half this frequency, or 70 kHz in this case. The frequency range is programmed by adding in the effect of R 2  and the output V EAO  of the EA 44:                f        (     V   EAO     )       =       [       R1   +   R2       R1   ·   R2   ·   C3       ]     /     ln        [           (     3   -     V   EAO       )     ·   R1     +     3   ·   R2             (     1   -     V   EAO       )     ·   R1     +   R2       ]                 (   eq6   )                                
     The value of R 2  is selected to be approximately ten times the value of R 1 , and thus in this example R 2  is 180 KΩ. This selection results in a frequency range of approximately +/−10% from nominal. Using equation 6, the maximum frequency (when V EAO =0 V) is equal to 154 kHz, and the minimum frequency (when V EAO =3.5 V) is equal to 125 kHz in the example circuit. 
     To improve efficiency over a wide input voltage range, the circuit of FIGS. 6 and 7 includes a control loop programmed to limit the voltage across the primary of the piezo transformer  12 . This loop includes the DA  48 , VA  46  and phase shifter  42  of FIG. 7, as well as associated components shown in FIG.  6 . By shifting the phase of the drive signals for Q 3  and Q 4  with respect to the drive signals for Q 1  and Q 2 , the duty cycle of the piezo transformer primary voltage is controlled, and therefore the average value of the primary voltage is controlled. Because the reference voltage appearing at VA+ changes in response to dimming, the average voltage that is maintained by the control loop changes accordingly, and therefore efficient operation is maintained throughout the operating range of the lamp  10 . 
     FIG. 8 illustrates the operation of the duty cycle control loop under three conditions. FIG. 8A shows operation with a “nominal” DC input voltage V inN  of about 10 volts. FIG. 8B shows operation with a “reduced” DC input voltage V inR  of about 7 volts. FIG. 8C shows operation with an “increased” DC input voltage V inI  of about 13 volts. 
     In FIG. 8, periods of the waveforms for OUT 1  and OUT 2  are labeled to identify which of the four transistors Q 1 -Q 4  are conducting. The drive signals supplied to transistors Q 1  and Q 2  are 180 degrees out of phase, as are the drive signals supplied to transistors Q 3  and Q 4 . Although not shown in the Figures, the controller  30  includes anti-cross-conduction circuitry to prevent transistors Q 1  and Q 2  from conducting simultaneously when drive is switched from one to the other. 
     In the nominal case shown in FIG. 8A, the signals OUT 1  and OUT 2  have amplitude equal to V inN , and the signal OUT 2  is about −90 degrees out of phase with the signal OUT 1 . During about half of every other half cycle, transistors Q 1  and Q 4  are conducting simultaneously, so that the difference OUT 1 -OUT 2  is a positive pulse, which is provided to the series combination of the inductor L 1  and the piezo primary. During about half of the other half cycles, transistors Q 2  and Q 3  are conducting simultaneously, so that the difference OUT 1 -OUT 2  is a negative pulse provided to the series combination of the inductor L 1  and the piezo primary. The resulting piezo primary voltage is a substantially sinusoidal waveform having an RMS voltage of about 7.5 volts. 
     It will be appreciated from FIGS. 8B and 8C that as the input voltage changes, the amplitude of the difference value OUT 1 -OUT 2  changes accordingly, and the duty cycle changes in an opposite manner such that the RMS value of the sinusoidal piezo primary voltage remains at about 7.5 volts. In FIG. 8B, the amplitude of OUT 1 -OUT 2  is reduced to 2*V inR , but the duty cycle is increased substantially to compensate for this reduced amplitude. Similarly, in FIG. 8C the amplitude of OUT 1 -OUT 2  is increased to 2*V inI , but the duty cycle is commensurately decreased. 
     This operation can be quantified as follows. The first element of the voltage clamping feedback loop is the DA  48 . When R 14 =R 15  and R 16 =R 17 , the output of the difference amplifier (DAO) is:                V   DAO     =       R14   R16     ·     (       V   D2     -     V   D1       )               (   eq7   )                                
     Since the DA  48  produces only a positive output voltage, V DAO  is zero volts when VD 2 &lt;VD 1 . As with lamp current (equation 1), V DAO  is averaged by the integrating voltage amplifier circuit including VA  46 , resistor R 12  and capacitor C 5 . Assuming a sinusoidal voltage across the piezo transformer primary, its average value is given by:                V       V                 A     -       =       R14   ·     V   PPRMS     ·     2         R16   ·   π               (   eq8   )                                
     Where Vpprms is the RMS voltage across the piezoelectric transformer primary (VD 2 −VD 1 ). For the circuit in FIG. 1, R 16 =R 17 =20 KΩ and R 14 =R 15 =80 KΩ, producing a gain of ¼. In order to achieve high efficiency for the piezoelectric transformer used in FIG. 1, primary voltage is controlled to 7 volts RMS at maximum lamp current and 3.5 volts RMS at minimum lamp current. From equation 8, VVA− is regulated to 0.8V at full intensity and 0.4V when dimmed to lowest intensity. VVA− is controlled by the voltage amplifier at VA+ and the 0-3V dimming control as follows:                V       V                 A     +       =       3        V   ·     [       R8   //   R9         R10   +   R8     //   R9       ]         +       V   DIM          [       R8   //   R9         R9   +   R8     //   R10       ]                 (   eq9   )                                
     Once R 8  is selected, R 9  and R 10  can be determined from the following equations:              R9   =       R8   ·     (       3      V     -     V     MAXVA   -         )         (       V     MAXVA   -       -     V     MINVA   -         )               (   eq10   )               R10   =       R8     V     MINVA   -              (       3      V     -     V     MAXVA   -         )               (   eq11   )                                
     With R 8  set to 20 KΩ and VEA+ ranging from 0.4 to 0.8V (see above), R 9  and R 10  are calculated to be 110 KΩ. Substituting these values into equations 8 and 9 (assuming VVA+=VVA− in closed loop operation):                V   PPRMS     =       0.4   +     0.133   ·     V   DIM         0.1125             (     for                   FIG   .              1       )                                
     Due to the high gain characteristics of the piezo transformer  12 , it is important that operation be suspended if an open lamp occurs. Within the circuitry  50 , a 2 volt comparator (not shown) is connected to the OPEN pin, and the output of this comparator triggers a shutdown of the circuitry when an open lamp is triggered. The voltage at which an open lamp shutdown occurs is given by the following, in which “R 21 ” is equal to the sum of R 21 A, R 21 B and R 21 C:                V   OPENRMS     =       2   ·   R21         2     ·   R20               (   eq12   )                                
     In the above example, this value is approximately 1500 volts RMS. 
     Circuitry for a piezo transformer based power supply for a fluorescent lamp has been shown. Although the illustrated circuitry incorporates a full-bridge converter topology, the techniques described herein are applicable to other power topologies, such as half-bridge, push-pull and flyback topologies for example. It will be apparent to those skilled in the art that other modifications to and variations of the disclosed circuitry are also possible without departing from the inventive concepts disclosed herein, and therefore the invention should not be viewed as limited except to the full scope and spirit of the appended claims.