Abstract:
A memory controller is provided. The memory controller is powered by first and second power source and includes an input/output pin, a driver circuit, a terminal resistor, and an input buffer. The driver circuit is coupled to the input/output pin and capable of providing to a writing signal to the input/output pin. The terminal resistor is coupled between the input/output pin and the first power source. The input buffer is coupled to the input/output pin and capable of receiving a reading signal from the input/output pin. No terminal resistor is coupled between the input/output pin and the second power source.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application No. 61/545,740, filed on Oct. 11, 2011, the contents of which are incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a memory controller, and more particularly to a low power DDR memory controller. 
     2. Description of the Related Art 
     Generally, in a double data rate (DDR) memory system, such as a DDR dynamic random access memory (DRAM) system, each of a main die comprising a memory controller and a memory device comprising a DRAM device has one set of two terminal resistors coupled in series between a respective operation voltage and ground voltage for one input/output (I/O) pin of a bi-directional transmitter, and the joint point between the two terminal resistors is coupled to the I/O pin. For each of the main die and the memory controller, a respective on-die termination (DOT) voltage is equal to a half of the respective operation voltage. In this structure, static power dissipation occurs. For example, in a DRAM system with a series DDR3 1.5V/240Ω, there is a static current of 6.25 mA per one bit for each of the read and write paths. In a DRAM system with a series DDR2 1.8V/30Ω, there is a static current of 6 mA per one bit for each of read and write paths. In recent years, low power is required for DRAMs. Thus, static current induced in a DRAM system may be decreased to achieve the low power requirement. 
     Thus, it is desired to provide a low power memory controller which induces a low static current. 
     BRIEF SUMMARY OF THE INVENTION 
     An exemplary embodiment of a memory controller is powered by a first power source and a second power source. The memory controller comprises an input/output pin, a driver circuit, a terminal resistor, and an input buffer. The driver circuit is coupled to the input/output pin and capable of providing to a writing signal to the input/output pin. The terminal resistor is coupled between the input/output pin and the first power source. The input buffer is coupled to the input/output pin and capable of receiving a reading signal from the input/output pin. No terminal resistor is coupled between the input/output pin and the second power source. 
     An exemplary embodiment of a memory system comprises a memory controller and a memory device. The memory controller is packaged in a first die, and the memory device is packaged in a second die. The memory controller is powered by a first power source and a second power source. The memory controller comprises a first input/output pin, a first driver circuit, a first terminal resistor, and a first input buffer. The first driver circuit is coupled to the first input/output pin and capable of providing to a writing signal to the first input/output pin. The first terminal resistor is coupled between the first input/output pin and the first power source. The first input buffer is coupled to the first input/output pin and capable of receiving a reading signal from the first input/output pin. No terminal resistor is coupled between the input/output pin and the second power source. The memory device comprises a second input/output pin, a memory array, a controlling circuit, a second driver circuit, and a second input buffer. The second input/output pin is coupled to the first input/output pin. The memory array is capable of storing data. The controlling circuit is capable of accessing the memory array. The second driver circuit is coupled to the second input/output pin. The controlling circuit is capable of reading data from the memory array to generate the reading signal. The second driver circuit is capable of driving the reading signal and providing the driven reading signal to the second input/output pin. The second input buffer is coupled to the second input/output pin. The second input buffer is capable of receiving the writing signal from the second input/output pin and buffing the writing signal to the controlling circuit. The controlling circuit is capable of writing data to the memory array according to the writing signal. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  shows an exemplary embodiment of a memory system; and 
         FIG. 2  shows an exemplary embodiment of a memory system. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
     Memory systems are provided. In an exemplary embodiment shown in  FIG. 1 , a memory system  1  comprises a memory controller  10  and a memory device  11 . In the embodiment, the memory system  1  is a double data rate (DDR) dynamic random access memory (DRAM) system. The memory controller  10  (such as an DRAM controller) and the memory device (such as a DRAM device)  11  are packaged separately. For example, the memory controller  10  is packaged in one die serving a main die, and the memory device  11  is packaged in the other die serving memory die. The memory controller  10  is powered by two power sources  104  and  105 . One power source  104  provides an operation voltage VDD 10  of the memory controller  10 , and the other power source  105  provides a ground voltage GND 10  of the memory controller  10 . An input/output (I/O) pin P 10  of the memory controller  10  is coupled to an I/O pin P 11  of the memory device  11  through a transmission line  12 . The memory controller  10  comprises a front-end circuit  100 , a driver circuit  101 , an input buffer  102 , a voltage source  103 , and a terminal resistor R 10 . An input terminal of the driver circuit  101  is coupled to the front-end circuit  100 , and an output terminal thereof is coupled to the I/O pin P 10 . A positive input terminal of the input buffer  102  is coupled to the I/O pin P 10 . The voltage source  103  is coupled between a negative input terminal of the input buffer  102  and the power source  105  (ground voltage GND 10 ). The terminal resistor R 10  is coupled between the power source  104  (operation voltage VDD 10 ) and the I/O pin P 10 . An output terminal of the input buffer  102  is coupled to the front-end circuit  100 . According to the structure of the memory controller  10 , the input buffer  102  is merely coupled to the power source  104  through the terminal resistor R 10  in the respective die, and there is no resistor coupled between the I/O pin P 10  and the power source  105 . In other words, the input buffer  102  is merely coupled to the operation voltage VDD 10  through the terminal resistor R 10  in the respective die, and the input buffer  102  is not coupled to the ground voltage GND 10  through a resistor in the respective die. 
     The memory device  11  comprises a controlling circuit  110 , a driver circuit  111 , an input buffer  112 , a voltage source  113 , and a memory array  114 , and terminal resistors R 100 . An input terminal of the driver circuit  111  is coupled to the controlling circuit  110 , and an output terminal thereof is coupled to the I/O pin P 11 . A positive input terminal of the input buffer  112  is coupled to the I/O pin P 11 . The voltage source  113  is coupled between a negative input terminal of the input buffer  112  and a ground voltage GND 11  of the memory device  11 . The terminal resistor R 11  is coupled between an operation voltage VDD 11  of the memory device  11  and the I/O pin P 11 . The terminal resistor R 12  is coupled between the I/O pin P 11  and the ground voltage GND  11 . An output terminal of the input buffer  112  is coupled to the controlling circuit  110 . According to the structure of the memory device  11 , the input buffer  112  is coupled to not only the operation voltage VDD 11  through the terminal resistor R 11  but also the ground voltage GND 11  through the terminal resistor R 12 . The voltage source  113  provides a voltage VR 11  (also called “on-die termination (DOT) voltage”) which is equal to a half of the operation voltage VDD 11 . In the embodiment, the operation voltage VDD 10  of the memory controller  10  is equal to the operation voltage VDD 11  of the memory device  11 , and the ground voltage GND 10  of the memory controller  10  is equal to the ground voltage GND 11  of the memory device  11 . In the embodiment, each of the terminal resistors R 11  and R 12  is a pseudo open drain terminator of the memory device  11 . 
     Referring to  FIG. 1 , when the memory system  1  performs a writing operation. The front-end circuit  100  generates a writing signal SW to the driver circuit  101 . The driver circuit  101  drives the writing signal SW and provides the driven writing signal SW to the transmission line  12  via the I/O pin P 10 . The input buffer  112  of the memory device  11  receives the writing signal SW via the I/O pin P 11 . The input buffer  112  buffers the writing signal SW to the controlling circuit  110 . The controlling circuit  110  performs an accessing operation to write data to the memory array  114  according to the writing signal SW. Accordingly, the driver circuit  101  of the memory controller  10 , the transmission line  12 , and the input buffer  112  of the memory device  11  form a writing path. 
     When the memory system  1  performs a reading operation, when controlling circuit  110  performs the accessing operation to read data from the memory array  114 . The controlling circuit  110  generates a reading signal SR. The driver circuit  111  drives the reading signal SR and provides the driven reading signal SR to the transmission line  12  via the I/O pin P 11 . The input buffer  102  of the memory controller  10  receives the reading signal SR via the I/O pin P 10 . The input buffer  102  buffers the reading signal SR to the front-end circuit  100 . Accordingly, the driver circuit  111  of the memory device  11 , the transmission line  12 , and the input buffer  102  of the memory controller  10  form a reading path. 
     In the embodiment, the terminal resistor R 10  is a pseudo open drain terminator of the memory controller  10 . Based on the structure of  FIG. 1 , the memory controller  10 , a voltage VR 10  (also called “on-die termination (DOT) voltage”) provided by the voltage source  103  is determined according to the resistance of the terminal resistor R 10 . The voltage VR 10  is larger than a half of the operation voltage VDD 10  (VR 10 &gt;½×VDD 10 ). In a preferred embodiment, the voltage VR 10  is equal to 0.7 times of the operation voltage VDD 10  (VR 10 =0.7×VDD 10 ). Referring to  FIG. 1 , there is only one terminal resistor R 10  coupled to the I/O pin P 10  and the positive input terminal of the input buffer  102 , that is, the input buffer  102  is merely coupled to the power source  104  (the operation voltage VDD 10 ) through the terminal resistor R 10 . Thus, the static current induced in the reading path is decreased. Particularly, when the resistance of the terminal resistor R 10  is 60Ω, there is no the static current in the reading path. 
     In some embodiments, the terminal resistor of the memory controller  10  is coupled between the between the I/O pin P 10  and the power source  105 . As shown in  FIG. 2 , a terminal resistor R 10 ′ is coupled between the between the I/O pin P 10  and the power source  105  (the ground voltage GND 10 ). In this structure of  FIG. 2 , the voltage VR 10  provided by the voltage source  103  is less than a half of the operation voltage VDD 10  (VR 10 &lt;½×VDD 10 ). In a preferred embodiment, the voltage VR 10  is equal to 0.3 times of the operation voltage VDD 10  (VR 10 =0.3×VDD 10 ). Referring to  FIG. 2 , the input buffer  102  is merely coupled to the power source  105  through the terminal resistor R 10 ′, and there is no resistor coupled between the I/O pin P 10  and the power source  104 . In other words, the input buffer  102  is merely coupled to the ground voltage GND 10  through the terminal resistor R 10 ′ in the respective die, and the input buffer  102  is not coupled to the operation voltage VDD 10  through a resistor in the respective die. The static current induced in the reading path is decreased. Particularly, when the resistance of the terminal resistor R 10 ′ is 60Ω, there is no the static current in the reading path. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.