Abstract:
A line card circuit using a pair of comparators such that the output of the first comparator is coupled to an input of the second comparator through an RC circuit. The RC circuit is tuned such that short transients, such as false pulses and false off hook indications passed by the first comparator are not passed by the RC circuit to the second comparator. The input of the first comparator is coupled to the subscriber line and the output of the second comparator is coupled to the switch&#39;s hook status detection circuitry.

Description:
FIELD OF THE INVENTION 
     The present invention relates to analog glitch filter circuitry, and more particularly to a hook switch status glitch filter to prevent false dial pulses and false off hook indications at the central office. 
     BACKGROUND OF THE INVENTION 
     A telephone line, or subscriber loop, provides electrical and physical connection of a subscriber telephone to the central office. The telephone may be built using components which, by their nature, are such that they may create undesirable electrical transients. These transients can adversely interfere with the expected operation of the line equipment. For example, when an off hook subscriber dials a digit using a rotary dial pulse telephone, the subscriber opens, or breaks, and closes, or makes, the loop current thereby creating temporary on hook and off hook conditions. Sequences of these makes and breaks form a pulse train that indicates to the central office the digit dialed by the subscriber. On occasion, an extra, or false, pulse may be created by the telephone dial due to the nature of the handset relay. The central office dial pulse detector must ignore these false pulses to ensure that the proper dialed digit is interpreted. 
     Ringing transients may also be created during the application or removal of ringing power to the loop. These transients can be so severe that they cause the central office loop status detector to falsely detect an off hook condition on the line. When the false off hook is detected, the central office removes ringing from the line. 
     According to Telcordia standards document GR-506-CORE, “LSSGR: Signaling for Analog Interfaces”, Issue 1, June 1996, Section 10.1.4 Rejection of False Dial Pulses, the central office should ignore as a dial pulse any pulse of 2 ms or less, and, according to Section 14.1.4 Ring Trip, ignore transients of 12 ms or less as an off hook condition during the alerting state. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a line card circuit that will mask false pulses during digit dialing while maintaining the integrity of the dialed pulse train. Another object of the invention is to provide a line card circuit that will mask the shorter duration false off hook indications during ringing. 
     The invention of Applicant is a line card circuit that employs a pair of comparators arranged such that the output of the first comparator is coupled to an input of the second comparator through an RC circuit. The RC circuit is tuned such that short transients, such as false pulses and false off hook indications, passed by the first comparator are not passed by the RC circuit to the second comparator. The input of the first comparator is coupled to the subscriber line and the output of the second comparator is coupled to the switch&#39;s hook status detection circuitry. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     The FIGURE shows a circuit diagram of the preferred embodiment of Applicants&#39; invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The FIGURE shows a circuit diagram of the preferred embodiment of Applicant&#39;s invention. A comparator CM 1  receives dial pulse and off hook input signal SIGNAL IN at its positive input voltage connection CM 1 +. Negative input voltage connection CM 1 − of comparator CM 1  is connected between series resistors R 2  and R 3 , which form a simple voltage divider network between the 5 volt operating voltage and ground that supplies an intermediate voltage. The output of comparator CM 1  is connected through a resistor R 4  to the positive input voltage connection CM 2 + of a second comparator CM 2 . Connection CM 2 + is also connected to the 5 volt operating voltage through a resistor R 5  and to ground through a capacitor C 2 . Resistors R 4  and R 5  and capacitor C 2  are components of an RC circuit. Negative input voltage connection CM 2 − of comparator CM 2  is also connected between series resistors R 2  and R 3 . The output of comparator CM 2  is the circuit output signal SIGNAL OUT. Comparators CM 1  and CM 2  are each powered through their respective supply voltage connections VCC to the 5 volt operating voltage and their respective ground connections GND to ground. 
     In the preferred embodiment, pull-up resistors R 1  and R 6  are connected between the SIGNAL IN input signal on connection CM 1 + and the 5 volt operating voltage, and between the SIGNAL OUT output signal on the output connection of comparator CM 2  and the 5 volt operating voltage, respectively. The functions served by pull-up resistors R 1  and R 6  may be incorporated in circuitry upstream or downstream, respectively, from Applicant&#39;s circuit, and one or both of these resistors may not be required in the circuit. 
     An optional bypass capacitor C 1  is connected between connection CM 1 − and ground and serves to keep input signal SIGNAL IN stable. 
     In the preferred embodiment, resistors R 1 , R 5  and R 6  have values of 49.9 kΩ, and resistor R 4  has a value of 16.9 kΩ. Resistors R 2  and R 3  have values of 16.9 kΩ and 14.3 kΩ, respectively, giving the midpoint connection between R 2  and R 3  a value of 2.3 volts. Capacitor C 1  has a value of 0.1 μf, and capacitor C 2  has a value of 0.22 μf. Comparators CM 1  and CM 2  are both National Semiconductor model LP339. However, any standard comparator make and model that satisfies the design requirements can be used. 
     In normal operations, input signal SIGNAL IN comprises either dial pulses from the subscriber&#39;s telephone, a constant high voltage signal indicating on hook status, or a constant low voltage signal indicating off hook status. The high-to-low or low-to-high transitions will approximate square waves. False dial pulses and false off hook indications will appear as spikes on input signal SIGNAL IN. 
     In the equilibrium SIGNAL IN high state, connection CM 1 + has a voltage of 5 volts. Connection CM 1 − has a value of 2.3 volts. The output of comparator CM 1  is 5 volts. Capacitor C 2  has a voltage across it of 5 volts. Connection CM 2 − has a value of 2.3 volts and connection CM 2 + has a voltage of 5 volts. The output of comparator CM 2 , signal SIGNAL OUT, is 5 volts. 
     When signal SIGNAL IN transitions to a low state of 0.2 volts, a current path is created from the 5 volt operational voltage to ground through resistors R 5 , R 4  and the comparator CM 1  output and GND connections. There is a 0.2 volt drop across the comparator CM 1  output and GND connections while this current path is conducting. When this current path is conducting, capacitor C 2  discharges through resistors R 5  and R 4  in a time interval governed by the behavior of the RC circuit formed by resistors R 4 , R 5  and capacitor C 2  according to the familiar equation 
     
       
           V ( t )= V   f +( V   i   −V   f ) e   −t/RC   
       
     
     where V i =initial equilibrium voltage across the capacitor, and V f =final equilibrium voltage across the capacitor. 
     In the preferred embodiment, where resistors R 4  and R 5  are in parallel with respect to capacitor C 2  during discharge, the denominator of the exponential becomes the time constant.          C2        [     R4R5     R4   +   R5       ]       =     2.8                   ms   .                              
     The final equilibrium voltage across capacitor C 2  after discharge, which is governed by the values of resistors R 4 , R 5  and the 0.2 voltage drop across comparator CM 1 , is 1.4 volts. 
     Solving for the time at which the voltage across capacitor C 2  discharges from the SIGNAL IN high state voltage of 5 volts to a value of 2.3 volts, the voltage at which comparator CM 2  flips, yields about 3.6 ms. When the voltage across capacitor C 2 , and hence connection CM 2 +, drops below 2.3 volts, a current path is created from the 5 volt operational voltage to ground through resistor R 6  and the comparator CM 2  output. This causes signal SIGNAL OUT to drop from 5 volts to 0.2 volts. Thus, a falling edge of signal SIGNAL IN appears as a falling edge of signal SIGNAL OUT after a delay of 3.6 ms. 
     When signal SIGNAL IN transitions from a low to a high state, the current path through resistors R 5 , R 4  and comparator CM 1  becomes non-conducting. This allows capacitor C 2  to charge from 1.4 volts to an equilibrium voltage of 5 volts through resistor R 5  in a time interval governed by the behavior of the RC circuit formed by resistor R 5  and capacitor C 2 . When capacitor C 2  charges above 2.3 volts, the current path through resistor R 6  and comparator CM 2  becomes non-conducting, causing signal SIGNAL OUT to rise to 5 volts. 
     For the RC circuit formed by resistor R 5  and capacitor C 2  during charging, the time constant for the exponential equation is 
     
       
           R   5   C   2 =11 ms. 
       
     
     Solving for the time at which the voltage across capacitor C 2  charges from the SIGNAL IN low state voltage of 1.4 volts to a value of 2.3 volts, the voltage at which comparator CM 2  flips, yields about 3.6 ms. Thus, a rising edge of signal SIGNAL IN appears as a rising edge of signal SIGNAL OUT after a delay of 3.6 ms. 
     In the invention, the rising edge delay and the falling edge delay between the SIGNAL IN input signal and the SIGNAL OUT output signal are made approximately equal so as not to distort the pulse length. As can be seen, the 3.6 ms charging and discharging interval for capacitor C 2  to reach the 2.3 volt level required for comparator CM 2  to flip ensures that an input glitch of less than 3.6 ms will not be passed to the output signal. 
     The circuit can be tuned to meet a variety of power and timing requirements through judicious choices of the values of the components of the RC circuits in the system, i.e., resistors R 4  and R 5  and capacitor C 2 , and also the “trip” voltage values on negative connections CM 1 − and CM 2 −, as governed by the values of resistors R 2  and R 3 . 
     While a preferred embodiment of a hook switch status analog glitch filter circuit has been particularly shown and described, it is not intended to be exhaustive nor to limit the invention to the embodiment disclosed. It will be apparent to persons having ordinary skill in the art that modifications can be made to the present invention without departing from the scope and spirit thereof. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.