Abstract:
A method for forming a redistribution layer in a wafer structure, including (a) providing a wafer having a plurality of conductive structures and a first passivation layer thereon, wherein the first passivation layer covers the wafer except the conductive surfaces of the conductive structures; (b) forming a second passivation layer over the first passivation layer; (c) selectively removing part of the second passivation layer to form a plurality of grooves corresponding to a predetermined circuit; (d) forming a redistribution layer in the grooves; and (e) forming a third passivation layer over the second passivation layer and the redistribution layer. As a result, the redistribution layer is “embedded” in the second passivation layer so as to avoid the delamination of the redistribution layer.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
   This is a divisional application of application Ser. No. 11/099,172, filed on Apr. 5, 2005, now U.S. Pat. No. 7,220,618, which is hereby incorporated by reference in its entirety for all purposes. 
   The present application claims priority under 35 U.S.C. 119 to Taiwan R.O.C. Application No. 093110006 filed on Apr. 9, 2004, which is hereby incorporated by reference in its entirety for all purposes. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a method for forming a redistribution layer in a wafer structure, particularly to a method for embedding redistribution layer in the passivation layer of the wafer structure. 
   2. Description of the Related Art 
     FIG. 1  shows a cross sectional view of a conventional wafer structure. The conventional wafer structure  10  comprises a wafer  11 , a plurality of bonding pads  12 , a first passivation layer  13 , a redistribution layer  14 , a second passivation layer  15 , an under bump metallurgy layer  16  and a solder bump  17 . 
   The bonding pads  12  are disposed on a surface of the wafer  11 , and the material of the bonding pads  12  is usually aluminum, copper or the like. The first passivation layer  13  covers the wafer  11  and part of each bonding pads  12  so as to expose a conductive surface on each bonding pads  12 . That is, the first passivation layer  13  does not cover the top surfaces of the bonding pads  12  completely. The material of the first passivation layer  13  is usually benzocyclobutene (BCB), polyimide (PI) or the like. The redistribution layer  14  is disposed over the first passivation layer  13  and is used for electrically connecting the bonding pads  12  and the under bump metallurgy layer  16 . The material of the redistribution layer  14  is usually aluminum or the like. The second passivation layer  15  is disposed over the first passivation layer  13  and is used for protecting the redistribution layer  14 . The material of the second passivation layer  15  is usually benzocyclobutene (BCB), polyimide (PI) or the like. The under bump metallurgy layer  16  is disposed on a predetermined location and has the solder bump  17  thereon. The under bump metallurgy layer  16  includes an adhesion layer, a barrier layer and a wetting layer (not shown), and is used for enhancing the attachment between the solder bump  17  and the redistribution layer  14 . The material of the solder bump is usually tin/lead alloy. 
     FIGS. 2   a  to  2   m  show a conventional method for forming a redistribution layer in the wafer structure  10  of  FIG. 1 . The conventional method is described as follows. First, a wafer  11  having a plurality of bonding pads  12  is provided, as shown in  FIG. 2   a . A first passivation layer  13  is then formed on the wafer  11  to protect the wafer  11  by coating or deposition. The first passivation layer  13  does not cover the top surfaces of the bonding pads  12  completely but exposes the conductive surface  121  of the bonding pads  12 , as shown in  FIG. 2   b . Then, a conductive layer  14   a  is formed over the first passivation layer  13  and the bonding pads  12  by sputtering, as shown in  FIG. 2   c . The conductive layer  14   a  is patterned according to the following steps. A photoresist film is applied to the conductive layer  14   a  and is exposed and developed to form a patterned photoresist film that serves as a mask. Then, the conductive layer  14   a  is selectively removed by wet etching to form the redistribution layer  14 , as shown in  FIG. 2   d . Then, the second passivation layer  15  is formed by coating or deposition on the redistribution layer  14  to protect the redistribution layer  14 , as shown in  FIG. 2   e . The second passivation layer  15  is selectively removed by utilizing exposing and development technique so as to have a plurality of openings  151  and expose part of the redistribution layer  14 , as shown in  FIG. 2   f . Then, a conductive layer  16   a  is formed over the second passivation layer  15  by sputtering, as shown in  FIG. 2   g.    
   A photoresist film, for example, a dry film or a liquid photo resist layer, is applied to the conductive layer  16   a . By an appropriate way, for example, patterning, a plurality of openings are defined on the photoresist film. The photoresist film is selectively removed so that a patterned photoresist film  18  remains on the opening  151 , as shown in  FIG. 2   h . Then, the conductive layer  16   a  is patterned by etching according to the mask of patterned photoresist film  18 . For example, part of the conductive layer  16   a  is removed by wet etching, and the conductive layer  16   a  on the opening  151  remains to form the under bump metallurgy layer  16 , then the patterned photoresist film  18  is stripped, as shown in  FIG. 2   i.    
   Referring to  FIG. 2   j , the entire surface is covered by another photoresist film  181  on which an opening  182  corresponding to the solder bump  17  is formed by patterning. Then, a silver paste  19  is filled in the opening  182  by screen printing, as shown in  FIG. 2   k . The solder bump  17  is made of the silver paste  19  after reflow, as shown in  FIG. 2   l . Finally, the conventional wafer structure  10  is formed after the photoresist film  181  is stripped, as shown in  FIG. 2   m.    
   A shortcoming of the conventional wafer structure  10  is that the redistribution layer  14  is on the surface of the first passivation layer  13 , which will cause delamination easily. That is, the redistribution layer  14  cannot be fixed on the first passivation layer  13  tightly due to the poor attachment therebetween. Thus, the performance of the redistribution layer  14  will be reduced, and moreover, the packaging may fail. 
   Consequently, there is an existing need for a novel and improved method for forming a redistribution layer in a wafer structure to solve the above-mentioned problem. 
   SUMMARY OF THE INVENTION 
   One objective of the present invention is to “embed” the redistribution layer in a passivation layer so that the redistribution layer is fixed in a passivation layer tightly and the delamination of the redistribution layer can be avoided. 
   Another objective of the present invention is to provide a method for forming a redistribution layer in a wafer structure comprising: 
   (a) providing a wafer having a plurality of conductive structures and a first passivation layer thereon, wherein the first passivation layer covers the wafer except the conductive surfaces of the conductive structures; 
   (b) forming a second passivation layer over the first passivation layer; 
   (c) selectively removing part of the second passivation layer to form a plurality of grooves corresponding to a predetermined circuit, wherein the grooves expose the conductive surfaces of the conductive structures; 
   (d) forming a redistribution layer in the grooves; and 
   (e) forming a third passivation layer over the second passivation layer and the redistribution layer. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows a cross sectional view of a conventional wafer structure; 
       FIGS. 2   a  to  2   m  show a conventional method for forming a redistribution layer in the wafer structure of  FIG. 1 ; and 
       FIGS. 3   a  to  3   r  show a method for forming a redistribution layer in a wafer structure according to the preferable embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIGS. 3   a  to  3   r  show a method for forming a redistribution layer in a wafer structure according to the preferable embodiment of the present invention. The method according to the present invention is described as follows. First, a wafer  21  having a plurality of conductive structures, for example, bonding pads  22 , is provided, as shown in  FIG. 3   a . A first passivation layer  23  is then formed by coating or deposition on the wafer  21  to protect the wafer  21 . The first passivation layer  23  does not cover the top surfaces of the bonding pads  22  completely but exposes the conductive surface  221  of the bonding pads  22 , as shown in  FIG. 3   b . A second passivation layer  24  is then formed by coating or deposition over the first passivation layer  23  and covers the bonding pads  22 , as shown in  FIG. 3   c.    
   Next,  FIGS. 3   d  to  3   i  show the cross sectional view taken along line A-A of  FIG. 3   c . Part of the second passivation layer  24  is selectively removed by utilizing exposing and development technique so that the second passivation layer  24  has a plurality of grooves  241  corresponding to a predetermined circuit, wherein the grooves  241  pass over the bonding pads  22  and expose the conductive surfaces  221  ( FIG. 3   b ) of the bonding pads  22 , as shown in  FIG. 3   d . In other words, the grooves  241  extend from an exposed portion of the second passivation layer  24  which exposes the conductive surfaces  221  of the bonding pads  22  to another portion of the second passivation layer  24  other than the exposed portion. The grooves  241  extend to outside of the bonding pads  22 . A seed layer  25  is then formed on the sidewalls of the grooves  241  by electroless plating, sputtering, chemical vapor deposition or physical vapor deposition, as shown in  FIG. 3   e.  The material of the seed layer  25  can be aluminum, copper or the like. Then, a photoresist film  26 , for example, a dry film or a liquid photo resist layer, is applied to the seed layer  25 . By an appropriate way, for example, patterning, a plurality of openings  261  corresponding to the grooves  241  are formed on the photoresist film  26  so as to expose the seed layer  25  in the grooves  241 , as shown in  FIG. 3   f . Then, a metal material is fulfilled in the grooves  241  by electroplating or electrodepositing so as to form a redistribution layer  27 . The material of the redistribution layer  27  is the same as that of the seed layer  25 , which is aluminum, copper, or the like, as shown in  FIG. 3   g . Then, the photoresist film  26  is stripped and the excessive material of the redistribution layer  27  is etched back. The redistribution layer  27  does not extend out of grooves  241  in relation to a top surface of the second passivation layer  24 . Preferably, the top surface of the redistribution layer  27  and the top surface of the second passivation layer  24  are on the same horizontal plane, as shown in  FIG. 3   h . Accordingly, the redistribution layer  27  is “embedded” in the second passivation layer  24  so that the redistribution layer  27  is fixed in the second passivation layer  24  tightly and the delamination of the redistribution layer  27  can be avoided. 
   Then, a third passivation layer  28  is formed over the second passivation layer  24  and the redistribution layer  27 , as shown in  FIG. 3   i.    
   Next, the view angle of  FIGS. 3   j  to  3   r  is same as that of  FIG. 3   c . Taking  FIGS. 3   i  and  3   j  for example, they show the same structure from a different view angle. 
   Part of the third passivation layer  28  is selectively removed by utilizing exposing and development technique so that the third passivation layer  28  has a plurality of openings  281  to expose part of the redistribution layer  27 , as shown in  FIG. 3   k . Then, a conductive layer  29  is formed over the third passivation layer  28  by sputtering, as shown in  FIG. 3   l.    
   A photoresist film, for example, a dry film or a liquid photo resist layer, is applied to the conductive layer  29 . By an appropriate way, for example, patterning, a plurality of openings are defined on the photoresist film. The photoresist film is selectively removed so that a patterned photoresist film  30  remains on the opening  281 , as shown in  FIG. 3   m . Then, the conductive layer  29  is patterned by etching according to the mask of the patterned photoresist film  30 . For example, part of the conductive layer  29  is removed by wet etching, and the conductive layer  29  on the opening  281  remains to form a under bump metallurgy layer  31 , then the patterned photoresist film  30  is stripped, as shown in  FIG. 3   n.    
   Referring to  FIG. 3   o , the entire surface is covered by another photoresist film  32  on which an opening  321  corresponding to a solder bump  34  ( FIG. 3   q ) is formed by patterning. Then, a silver paste  33  is filled in the opening  321  by screen printing, as shown in  FIG. 3   p . The solder bump  34  is made of the silver paste  33  after reflow, as shown in  FIG. 3   q . Finally, the wafer structure  20  is formed after the photoresist film  32  is stripped, as shown in  FIG. 3   r.    
     FIG. 3   r  shows the wafer structure  20  according to the preferable embodiment of the present invention. The wafer structure  20  comprises a wafer  21 , a plurality of bonding pads  22 , a first passivation layer  23 , a second passivation layer  24 , a redistribution layer  27 , a third passivation layer  28 , a under bump metallurgy layer  31  and a solder bump  34 . 
   The bonding pads  22  are disposed on a surface of the wafer  21 , and the material the bonding pads  22  is usually aluminum, copper or the like. The first passivation layer  23  covers the wafer  21  and part of each bonding pads  22  so as to expose a conductive surface on each bonding pads. That is, the first passivation layer  23  does not cover the top surfaces of the bonding pads  22  completely. The material of the first passivation layer  23  is usually benzocyclobutene (BCB), polyimide (PI) or the like. The second passivation layer  24  is disposed over the first passivation layer  23  and has a plurality of grooves corresponding to a predetermined circuit, wherein the grooves expose the conductive surfaces of the bonding pads  22 . The material of the second passivation layer  24  is usually benzocyclobutene (BCB), polyimide (PI) or the like. The redistribution layer  27  is disposed in the grooves and is used for electrically connecting the bonding pads  22  and the under bump metallurgy layer  31 . The material of the redistribution layer  27  is usually aluminum. Preferably, the top surface of the redistribution layer  27  and the top surface of the second passivation layer  24  are on the same horizontal plane. The third passivation layer  28  is disposed over the second passivation layer  24  and the redistribution layer  27  to protect the redistribution layer  27 . The material of the third passivation layer  28  is usually benzocyclobutene (BCB), polyimide (PI) or the like. The under bump metallurgy layer  31  is disposed on a predetermined location over the third passivation layer  28  and is electrically connected to the redistribution layer  27 . The solder bump  34  is formed on the under bump metallurgy layer  31 . The under bump metallurgy layer  31  includes an adhesion layer, a barrier layer and a wetting layer (not shown), and is used for enhancing the attachment between the solder bump  34  and the redistribution layer  27 . The material of the solder bump  34  is usually tin/lead alloy. 
   While several embodiments of the present invention have been illustrated and described, various modifications and improvements can be made by those skilled in the art. The embodiments of the present invention are therefore described in an illustrative but not restrictive sense. It is intended that the present invention may not be limited to the particular forms as illustrated, and that all modifications which maintain the spirit and scope of the present invention are within the scope as defined in the appended claims.