Abstract:
In a modified Booth&#39;s algorithm only one shift unit is required for multiplication of the partial products. This is based on the known coding prescriptions of the Booth&#39;s algorithm, which respectively determines from 3 bits of the multiplier how the partial products are to be produced. From the respective 3 bits of the multiplier of the current iteration and of the preceding iteration, it is determined whether the partial product used for the next iteration has to be multiplied by 1/2, 1/4 or 1/8. For this purpose, a coding table and a multiplier that operates according to this principle are provided.

Description:
BACKGROUND OF THE INVENTION 
     U.S. Pat. No. 5,457,804 discloses a multiplication circuit in which multiplication time for multiplications with doubled precision is shortened, whereby either a higher-value half or a lower-value half of an input word of the multiplication circuit is selectively supplied to a standard Booth decoder via a multiplexer. 
     There are many algorithms for the accelerated calculation of a multiplication. In the classical Booth&#39;s algorithm, two bits of the multiplier are always simultaneously viewed, and a factor is formed therefrom by which the multiplicand is multiplied. This product is respectively added to the partial product. This method works with n uniform shift operations by a bit position to the right (division by 2) and n/2 additions, where n is the word length of the multiplier. For two&#39;s complement representations, no sign corrections are required. 
     A faster modified method has been proposed in (O. L. MacSorley, High-speed arithmetic in binary computers, Proc. IRE, vol. 49, pp. 67-91, 1961; L. P. Rubinfield, A proof of the modified Booth&#39;s algorithm for multiplication, IEEE Trans. Computers, pp. 1014-1015, October 1975). In this method, three bits of the multiplier are viewed simultaneously, which are decoded into 5 different factors (0; +-1; +-2; see Table 1). This algorithm requires only n/2 shift operations by two bit positions to the right (division by 4) and n/2 additions. In both methods mentioned, the decoding can be begun either at the LSB (least significant bit) or at the MSB (most significant bit). A special treatment of the sign is not required. The decoding beginning with the LSB has the advantage (A. Stotzle, A. Rainer and W. Ulbrich, Parallel-serial multiplication using Booth&#39;s algorithm and Horner scheme, Proc. ISCAS &#39;85, pp. 1389-1390, May 1985) that via the use of the Horner scheme the word length of the product is limited to the word length of the multiplicand. The result thus obtained agrees with the first m bit of the exactly n+n bit long product. In the following, the modified Booth&#39;s algorithm is specified somewhat more precisely, since it is the point of departure for the invention. 
     Let the multiplier Y and the multiplicand X be given by their two&#39;s complement representation. ##EQU1## with y i  ε {0,1} for i=0, 1, 2, . . . , n-1 and x j  ε {0, 1}, for j=0, 1, 2, . . . , m-1 
     By means of the combination of two successive summation steps, the multiplier Y can be transformed into ##EQU2## for i=1, 3, 5, . . . , n-1 and y n  =0. 
     The product of the multiplication P thus results with the multiplicand X, as ##EQU3## for I=1, 3, 5, . . . , n-1, with y n  =0 and with ##EQU4## for i=1, 3, 5, . . . , n-1 
     FIG. 1 shows the processing in principle of the multiplier X with the modified Booth decoder. Beginning at the LSB side, three bits are always decoded simultaneously, and subsequently the decoding window is shifted two bit positions to the left. The bit y n  is set to 0, and if the word length n is odd, an additional bit is produced by the doubling of the multiplier MSB. The corresponding decoder table can be seen in Table 1. This does not require further explanation, since it results from (A. Stotzle, A. Rainer and W. Ulbrich, Parallel-serial multiplication using Booth&#39;s algorithm and scheme, Proc. ISCAS &#39;85, pp. 1389-1390, May 1985). 
     
                       TABLE 1______________________________________Multiplier bits (Y)Y.sub.i - 1      Y.sub.i            Y.sub.i +1  Operation______________________________________0          0     0           PP.sub.i ← 0.25PP.sub.i + 20          0     1           PP.sub.i ← 0.25PP.sub.i + 2 + X0          1     0           PP.sub.i ← 0.25PP.sub.i + 2 + X0          1     1           PP.sub.i ← 0.25PP.sub.i + 2 + 2X1          0     0           PP.sub.i ← 0.25PP.sub.i + 2 - 2X1          0     1           PP.sub.i ← 0.25PP.sub.i + 2 - X1          1     0           PP.sub.i ← 0.25PP.sub.i + 2 - X1          1     1           PP.sub.i ← 0.25PP.sub.i______________________________________                        + 2 
    
     Corresponding to the coding prescriptions of Table 1, control signals are produced, namely the factor signal C, the shift signal K 0  and the sign signal S i . The control signals control the concrete execution of the individual cycles of the multiplication. FIG. 2 shows a schematic diagram of a standard Booth multiplier architecture. At the beginning of a multiplication, the multiplicand X is first loaded into the register REGX, and the accumulation register ACCU is set to 0 and initialized. Corresponding to the value of the multiplier Y and to the corresponding result of the Booth decoding according to Table 1, the individual partial products are produced in n/2 steps according to Equation 6. For this purpose, the multiplicand X must be multiplied by 0, 1 or 2 in each iteration. The shift unit SHE1 in FIG. 2 serves for this purpose. The multiplication by the factor of 2 means that an operation of shifting the multiplicand to the left by one bit position must be carried out. The partial product PP is calculated in each iteration using a shift unit SHE2 that divides the partial product of the preceding iteration by 4 (shift to the right by two bit positions). After n/2 iterations, the product is available in the accumulation register ACCU. Care is to be taken that the multiplicand X must have a doubled MSB, so that no overflow can occur during the execution of the additions or subtractions. Using the multiplier according to FIG. 2, the equations indicated in Table 1 under the heading `Operation` are thus realized. The factor signal C is used to let the multiplicand X through to the shift unit SHE1 or to set 0. An operation of this sort is required according to the first and the last lines of Table 1. A multiplication by 2 is required for the multiplicand X according to Table 1, in the 4 th  and 5 th  lines. The addition or, respectively, subtraction ensues in an arithmetic logic unit ALU, dependent on the sign signal S i . From the last column of Table 1, it can be seen when the multiplicand X must be added to or subtracted from the preceding partial product PP i+2 . The partial product PP i+2  is in the accumulation register ACCU and is multiplied by 0.25 in the shift unit SHE2, and is then supplied again for the formation of the next partial product PP i  of the ALU. The allocation of the multiplier bits y i-1 , y i , y i+1  to the individual operations can be found in Table 1. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to modify the above-described Booth&#39;s algorithm in order to achieve a simplification of the multiplier. 
     A further object is to indicate a Booth multiplier that operates according to the modified Booth&#39;s algorithm. 
     Finally, the object is to indicate a decoding circuit with which the control signals for the multiplier are produced. 
     In general terms the present invention is a method for a multiplication circuit for multiplication of a multiplicand and a multiplier according to the Booth method in iterative steps. 
     Beginning with the least significant bit, three multiplier bits are respectively decoded, and a partial product is formed iteratively, dependent on the decoding result, from the previous partial product and from the multiplicand, whereby the partial product is set to 0 at the beginning. 
     In the respective next iteration, the decoding window is subsequently shifted to the left by two bits via the multiplier. 
     In order to obtain a first intermediate result dependent on a factor signal obtained from the bits to be decoded, the multiplicand is multiplied by 0 or 1. 
     The first intermediate result and a second intermediate result obtained from the partial product of the preceding iteration are added or subtracted dependent on a sign signal obtained from the bits to be decoded. 
     In order to obtain the second intermediate result dependent on two control signals produced from the bit to be decoded of the current iteration and from the bit to be decoded of the preceding iteration of the multiplier, the partial product of the preceding iteration is multiplied by 1/2, 1/4 or 1/8. 
     A multiplication by 1/4 ensues if the decoding result of the current iteration yields the result that the multiplicand is combined in simple form with the preceding partial product. 
     A multiplication by 1/8 ensues if the decoding result of the current iteration yields the result that the multiplicand is combined in duplicate form with the preceding partial product. 
     A multiplication by 1/2 ensues if the decoding result of the preceding iteration yields the result that the multiplicand was to be combined in duplicate form. 
     The present invention is also a multiplier circuit for carrying out the method. A multiplicand register is provided that stores the multiplicand. A multiplier is provided at the output of the multiplicand register, which multiplier multiplies the multiplicand by 0 or 1, dependent on the factor signal. An arithmetic logic unit is provided, which, dependent on the sign signal, adds or subtracts the result emitted at the output of the multiplier to the second intermediate result present at the other output. An accumulation register is arranged at the output of the arithmetic logic unit. A shift unit is provided at the output of the accumulation register, with which the content of the accumulation register is multiplied by 1/2, 1/4 or 1/8, dependent on the control signals, in order to produce the second intermediate result. The output of the shift unit is connected with the arithmetic logic unit. 
     In a further embodiment a decoding circuit is provided for the production of the control signals of the factor signal and of the sign signal. The decoding circuit has: a latch memory for storing the multiplier; multiplexers connected to the output of the latch memory, which select at the output the bits of the decoding window from the multiplier bits; a decoder that produces the control signals from the bits of the decoding window. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features of the present invention which are believed to be novel, are set forth with particularity in the appended claims. The invention, together with further objects and advantages, may best be understood by reference to the following description taken in conjunction with the accompanying drawings, in the several Figures of which like reference numerals identify like elements, and in which: 
     FIG. 1 shows the decoding window of the multiplier according to the known method; 
     FIG. 2 shows the known Booth multiplier; 
     FIG. 3 shows a schematic diagram of the modified Booth multiplier; 
     FIG. 4 shows the decoding window of the multiplier according to the modified Booth&#39;s algorithm; 
     FIG. 5 shows a schematic diagram of the Booth decoding circuit; and 
     FIG. 6 shows a realization of the Booth decoder. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The schematic diagram according to FIG. 3 shows, in comparison to the schematic diagram of FIG. 2, that there is no longer a shift unit SHE in the left branch of the ALU. In this left branch, only a multiplication by 0 or 1 and a change of sign is still executed. However, for this purpose a variable right-shift operation is executed in the accumulator loop (right ALU branch). The remaining construction of the multiplier according to FIG. 3 corresponds to that of the multiplier according to FIG. 2. 
     The multiplicand X is stored in the register REGX. This multiplicand is either passed or set to 0 via the unit MULT, which is driven by the factor signal C. For this purpose, the factor signal C is produced from the multiplier signal Y in a circuit C-ERZ, corresponding to the operations of Table 1. 
     
                       TABLE 2______________________________________Multiplier bits Yy.sub.i-1y.sub.i      y.sub.i+1              y.sub.i+2                   y.sub.i+3                         s.sub.i                             c.sub.i                                  H.sub.1                                      H.sub.2                                           K.sub.2                                               K.sub.1______________________________________0    0     0       0    0     0   0    1   1    0   10    0     0       0    1     0   0    1   1    0   10    0     0       1    0     0   0    1   1    0   10    0     0       1    1     0   0    1   0    1   00    0     1       0    0     0   1    1   0    1   00    0     1       0    1     0   1    1   1    0   10    0     1       1    0     0   1    1   1    0   10    0     1       1    1     0   1    1   1    0   10    1     0       0    0     0   1    1   1    0   10    1     0       0    1     0   1    1   1    0   10    1     0       1    0     0   1    1   1    0   10    1     0       1    1     0   1    1   0    1   00    1     1       0    0     0   1    0   0    0   10    1     1       0    1     0   1    0   1    1   10    1     1       1    0     0   1    0   1    1   10    1     1       1    1     0   1    0   1    1   11    0     0       0    0     1   1    0   1    1   11    0     0       0    1     1   1    0   1    1   11    0     0       1    0     1   1    0   1    1   11    0     0       1    1     1   1    0   0    0   11    0     1       0    0     1   1    1   0    1   01    0     1       0    1     1   1    1   1    0   11    0     1       1    0     1   1    1   1    0   11    0     1       1    1     1   1    1   1    0   11    1     0       0    0     1   1    1   1    0   11    1     0       0    1     1   1    1   1    0   11    1     0       1    0     1   1    1   1    0   11    1     0       1    1     1   1    1   0    1   01    1     1       0    0     1   0    1   0    1   01    1     1       0    1     1   0    1   1    0   11    1     1       1    0     1   0    1   1    0   11    1     1       1    1     1   0    1   1    0   1______________________________________ 
    
     The sign signal S i  is likewise generated from the multiplier Y, in the circuit S-ERZ. The shifting of the partial product is carried out in the shift unit SHE3, whereby a multiplication by 1/2, 1/4, or 1/8 is carried out by means of shifting to the right, corresponding to the operations to be executed. 
     Table 2 indicates a possible coding of the multiplier Y. As can be seen from Table 2, an expansion of the decoding size to 5 bits is necessary, as is also specified in the prior art (A. Stotzle, A. Rainer and W. Ulbrich, Parallel-serial multiplication using Booth&#39;s algorithm and Horner scheme, Proc. ISCAS &#39;85, pp. 1389-1390, May 1985). The sign signal S i  indicates whether the multiplicand X is added (S i  =0) or subtracted (S i  =1), the factor signal C indicates the factor with which the multiplicand X is weighted (C=1 multiplication by 1, C=1 multiplication by 0), and the control signals K 1  (right-shift operation by one bit position if K 1  =1) and K 2  (right-shift operation by two bit positions if K 2  =1) define the shift vector for the shift unit SHE3. The value of the control signals K 1  and K 2 , and the multiplication, to be carried out correspondingly, of the shift unit SHE3, can also be seen in Table 3. As is also the case in the previous algorithm, the bit y i  represents the current position. The bits y n , y n+1  and Y n+2  are next set to 0 (see FIG. 4), and, if the word length n is odd, an additional bit is produced by means of doubling of the multiplier MSB. 
     
                       TABLE 3______________________________________H.sub.1  H.sub.2          K.sub.2     K.sub.1                          Multiplication______________________________________0        1     1           1   PP * 0.1251        0     0           1   PP * 0.50        0     1           0   PP * 0.251        1     1           0   PP * 0.25______________________________________ 
    
     The multiplication takes place as in the modified Booth&#39;s algorithm with a constant shift vector (FIG. 2). The multiplicand is first loaded into the register REGX, and the accumulation register ACCU is initialized. Beginning at the LSB side, the 5-bit-long decoding window is laid over the two lowest-valued bits of the multiplier Y (see FIG. 4), and is shifted 2 bit positions to the left after each iteration. The result of the decoding determines the concrete execution of the operations during an iteration. The partial product PP i  is calculated using the variable shift unit SHE3, which allows shifts to the right by 1, 2 or 3 bit positions. After n/2 iterations, the product is available in the accumulation register ACCU. So that no overflow can occur during the execution of the additions or subtractions, the multiplicand X must have a doubled MSB. 
     The testing of the correctness of Table 2 can be carried out using Table 1. With the logical operation H 1   
     
         H.sub.1 =(y.sub.i-1 ⊕y.sub.i)×(y.sub.i ⊕y.sub.i+1)(7) 
    
     it is detected whether a multiplication by 2 needs to be carried out in the original coding according to Table 1, and with the corresponding logical operation H 2   
     
         H.sub.2 =(y.sub.i+1 ⊕y.sub.i+2)×(y.sub.i+2 ⊕y.sub.i+3)(8) 
    
     it is detected whether a multiplication by 2 was carried out in the preceding cycle. With the multiplier according to FIG. 3, a multiplication by 2 is realized by an additional right-shift operation of the partial product by one bit position. The partial product must then in the next iteration be shifted to the right not by two but by only one bit position. The described operations can be detected using the logical functions H 1  and H 2 . The control signals K 1  and K 2  for the shift unit SH3 can be determined therefrom as follows: ##EQU5## 
     Since the sign of the multiplicand Y is doubled (y 0  =y 1 ), the condition H 1  in the last iteration is never fulfilled, and no additional cycle is required for a further shift operation, so that n/2 shift operations and n/2 additions are also required for the modified Booth&#39;s algorithm with variable shift vectors. 
     The control signals S i  and C can be produced as follows: 
     
         S.sub.i =y.sub.i-1                                         (11) 
    
     
         C.sub.i =(y.sub.i-1 ⊕y.sub.i)×(y.sub.i ×y.sub.i+1)(12) 
    
     Table 2 shows the 5 bits of the multiplier Y acquired by the decoding window, and also the factor signal C and the sign signal S, as well as the results of the operations H 1  and H 2  or, respectively, K 1  and K 2 . The control signals K 1  and K 2  are outlined in those cases in which the control signal K 2  is binary 1. Table 3 extracts the various cases from Table 2, and indicates which multiplication is to be carried out in the shift unit SHE3. If both the control signal K 1  and K 2  are binary 1, a multiplication by 1/8 takes place by means of three shift operations to the right. 
     If the control signal K 1  is binary 1 and the control signal K 2  is binary 0, then only one shift operation or a multiplication by 1/2 ensues. If the control signal K 1  is binary 0 and the control signal K 2  is binary 1, two shift operations or a multiplication by 1/4 take place. 
     FIG. 5 shows the schematic diagram of the Booth decoding circuit DEKOY with a variable shift vector. The multiplier Y is stored in an n-bit long latch memory LA, using the accept signal U. The decoding window function is formed using 5 multiplexers MUX1 to MUX5, each with 8 inputs. The inputs are selected successively by means of the control lines S1 to S8. The control signals S i , C, K 1  and K 2 , corresponding to the equations 7 to 12, are produced from the 5 bits of the current decoding window, using the actual Booth decoder B-DOC. 
     FIG. 6 shows the schematic diagram of the Booth decoder B-DOC. Since the logical functions H 1  and H 2  are identical, they can be combined by storing the results from the preceding cycle to form a function as shown in FIG. 6. The result of the function H 1  is stored with the accept signal CL in the register REG, and in the next clock period corresponds to the result of the function H 2 . At the beginning of the Booth decoding, the content of the register is to be set to logical 0. Since the function H 2  was the only one that required the signals y i+2  and y i+3 , the multiplexers MUX1 and MUX2 in FIG. 5 can be omitted. 
     The individual circuits of FIG. 6 are explained by the symbols, which correspond to those of equations 7 to 12. Corresponding circuits are known in the literature. 
     The invention is not limited to the particular details of the method and apparatus depicted and other modifications and applications are contemplated. Certain other changes may be made in the above described method and apparatus without departing from the true spirit and scope of the invention herein involved. It is intended, therefore, that the subject matter in the above depiction shall be interpreted as illustrative and not in a limiting sense.