Abstract:
A fabrication method of a wafer level semiconductor package includes: forming on a carrier a first dielectric layer having first openings exposing portions of the carrier; forming a circuit layer on the first dielectric layer, a portion of the circuit layer being formed in the first openings; forming on the first dielectric layer and the circuit layer a second dielectric layer having second openings exposing portions of the circuit layer; forming conductive bumps in the second openings; mounting a semiconductor component on the conductive bumps; forming an encapsulant for encapsulating the semiconductor component; and removing the carrier to expose the circuit layer. By detecting the yield rate of the circuit layer before mounting the semiconductor component, the invention avoids discarding good semiconductor components together with packages as occurs in the prior art, thereby saving the fabrication cost and improving the product yield.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
     This application claims under 35 U.S.C. §119(a) the benefit of Taiwanese Application No. 101109611, filed Mar. 21, 2012, the entire contents of which is incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to fabrication methods of semiconductor packages, and more particularly, to a fabrication method of a wafer level semiconductor package and a fabrication method of a wafer level packaging substrate for improving the product accuracy. 
     2. Description of Related Art 
     Along with the rapid development of electronic industries, electronic products are developed towards multi-function and high performance. To meet the miniaturization requirement of semiconductor packages, wafer level packaging (WLP) technologies have been developed. 
     U.S. Pat. No. 6,452,265 and U.S. Pat. No. 7,202,107 provide fabrication methods of wafer-level packages.  FIGS. 1A to 1E  are schematic cross-sectional views showing a fabrication method of a conventional wafer level semiconductor package  1 . 
     Referring to  FIG. 1A , a thermal release tape  11  is formed on a carrier  10 . 
     Referring to  FIG. 1B , a plurality of semiconductor components  12  are disposed on the thermal release tape  11 . Each of the semiconductor components  12  has an active surface  12   a  with a plurality of electrode pads  120  and an inactive surface  12   b  opposite to the active surface  12   a . Each of the semiconductor components  12  is disposed on the thermal release tape  11  via the active surface  12   a  thereof. 
     Referring to  FIG. 1C , an encapsulant  13  is formed on the semiconductor components  12  and the thermal release tape  11  through molding. 
     Referring to  FIG. 1D , the thermal release tape  11  and the carrier  10  are removed to expose the active surfaces  12   a  of the semiconductor components  12 . 
     Referring to  FIG. 1E , by performing a redistribution layer (RDL) process and a bump process, a circuit structure  14  is formed on the encapsulant  13  and the active surfaces  12   a  of the semiconductor components  12  and electrically connecting the electrode pads  120  of the semiconductor components  12 . 
     However, since the thermal release tape  11  is flexible, the positioning accuracy of the semiconductor components  12  is adversely affected by the CTE (Coefficient of Thermal Expansion) of the thermal release tape  11  and lateral forces applied on the thermal release tape  11  by the encapsulant  13  during the molding process. Therefore, an increase in the size of carrier  10  results in an increase in the position error of the semiconductor components  12 , thereby causing yield losses in the RDL and bump processes. 
     Furthermore, since the above-described method forms the encapsulant  13  before performing the RDL process, if it is detected that the circuit structure  14  is of low quality during a subsequent test, the overall semiconductor package  1  has to be discarded. That is, good semiconductor components  12  are also discarded, thus resulting in a high fabrication cost. Therefore, the above-described method is not economic. 
     Therefore, how to overcome the above-described drawbacks has become critical. 
     SUMMARY OF THE INVENTION 
     The present invention provides a fabrication method of a wafer level packaging substrate, which comprises the steps of: forming on a carrier a first dielectric layer having a plurality of first openings for exposing portions of the carrier; forming a circuit layer on the first dielectric layer, a portion of the circuit layer being formed in the first openings of the first dielectric layer; forming on the first dielectric layer and the circuit layer a second dielectric layer having a plurality of second openings for exposing portions of the circuit layer; and forming a plurality of conductive bumps on the exposed portions of the circuit layer in the second openings and electrically connected to the circuit layer. 
     The above-described method further comprises removing the carrier to expose the circuit layer. 
     The present invention further provides a fabrication method of a wafer level semiconductor package, which comprises the steps of: providing a carrier for carrying a packaging substrate, wherein the packaging substrate comprises a first dielectric layer formed on the carrier, a circuit layer formed on the first dielectric layer, a second dielectric layer formed on the first dielectric layer, and a plurality of conductive bumps disposed on the second dielectric layer and electrically connected to the circuit layer; providing a semiconductor component having an active surface and an inactive surface opposite to the active surface and mounting the semiconductor component on the packaging substrate and electrically connecting the semiconductor component to the conductive bumps; forming an encapsulant on the second dielectric layer for encapsulating the semiconductor component; and removing the carrier to expose the circuit layer. 
     In the above-described fabrication method of a semiconductor package, the active surface of the semiconductor component can have a plurality of conductive portions. By performing a dispensing process or a reflow process, the conductive portions can be electrically connected to the conductive bumps through an adhesive material or a solder material. 
     In the above-described fabrication method of a semiconductor package, the semiconductor component can be a single chip or a chip stack structure. 
     In the above-described fabrication method of a semiconductor package, the inactive surface of the semiconductor component can be exposed from the encapsulant. 
     The above-described fabrication method of a semiconductor package can further comprise grinding the encapsulant so as to thin the thickness of the encapsulant. 
     Before forming the encapsulant, the above-described fabrication method of a semiconductor package can further comprise forming an underfill between the semiconductor component and the second dielectric layer. 
     The above-described fabrication method of a semiconductor package can further comprise performing a singulation process. 
     In the above-described fabrication methods of a packaging substrate and a semiconductor package, the first and second dielectric layers can be made of polyimide (PI), benezocyclobutene (BCB), polybenzoxazole (PBO), silicon dioxide or silicon nitride. 
     In the above-described fabrication methods, the carrier can be a silicon wafer, a glass plate, a plate with an aluminum layer formed thereon, a silicon wafer with an aluminum layer formed thereon or an aluminum plate. Preferably, the carrier can be a silicon wafer with an aluminum layer formed thereon. 
     In the above-described fabrication methods, the fabrication of the circuit layer can comprise the steps of: forming a first metal layer on a surface of the first dielectric layer, a portion of the first metal layer being formed in the first openings of the first dielectric layer; forming a resist layer on the first metal layer and forming a plurality of openings in the resist layer for exposing portions of the first metal layer; forming the circuit layer on the exposed portions of the first metal layer in the openings of the resist layer; and removing the resist layer and the first metal layer under the resist layer. 
     In the above-described fabrication methods, the fabrication of the conductive bumps can comprise the steps of: forming a second metal layer on a of the second dielectric layer, a portion of the second metal layer being formed in the second openings of the second dielectric layer; forming a resist layer on the second metal layer and forming a plurality of openings in the resist layer for exposing portions of the second metal layer; forming the conductive bumps on the exposed portions of the second metal layer in the openings of the resist layer; and removing the resist layer and the second metal layer under the resist layer. 
     In the above-described methods, the conductive bumps can be made of a solder material and reflowed. 
     The above-described methods can further comprise forming a redistribution layer structure between the first dielectric layer and the second dielectric layer for electrically connecting the circuit layer and the conductive bumps. 
     In the above-described methods, the carrier can be removed through a grinding process or an etching process. 
     After removing the carrier, the above-described methods can further comprise forming conductive elements on the circuit layer. 
     Therefore, the present invention forms the circuit layer before removing the carrier so as to avoid performing an RDL process after removing the carrier, thus preventing the positioning accuracy of semiconductor components from being adversely affected by the CTE and flexibility of a thermal release tape as in the prior art. Therefore, an increase in the size of the carrier does not result in an increase in the position error of the semiconductor components, thereby facilitating accurate control of the position of the semiconductor components. 
     Further, the present invention can detect the yield rate of the circuit layer before mounting semiconductor components. If the circuit layer is detected to be of low quality, the structure is directly discarded without performing subsequent processes such as mounting semiconductor components. Therefore, the present invention does not discard good semiconductor components as in the prior art when the circuit layer is detected to be of low quality, thereby saving material costs and achieving cost efficiency. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIGS. 1A to 1E  are schematic cross-sectional views showing a fabrication method of a conventional wafer level semiconductor package; 
         FIGS. 2A to 2K  are schematic cross-sectional views showing a fabrication method of a wafer level semiconductor package according to the present invention, wherein FIG.  2 G′ shows another embodiment of  FIG. 2G , and FIGS.  2 K′ and  2 K″ show different embodiments of  FIG. 2K ; and 
       FIGS.  2 A to  2 H′ are schematic cross-sectional views showing a wafer level packaging substrate according to the present invention, wherein FIG.  2 H″ shows another embodiment of FIG.  2 H′. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those in the art after reading this specification. 
     It should be noted that the drawings are only for illustrative purposes and not intended to limit the present invention. Meanwhile, terms such as ‘on’, ‘a’ etc. are only used as a matter of descriptive convenience and not intended to have any other significance or provide limitations for the present invention. 
       FIGS. 2A to 2K  are schematic cross-sectional views showing a fabrication method of a wafer level semiconductor package  2  according to the present invention. 
     Referring to  FIG. 2A , a first dielectric layer  21  is formed on a carrier  20  by coating, and further patterned such that a plurality of openings  210  are formed in the first dielectric layer  21  for exposing portions of the carrier  20 . 
     In the present embodiment, the first dielectric layer  21  can be made of polyimide (PI), benezocyclobutene (BCB) or polybenzoxazole (PBO). The carrier  20  can be a silicon wafer, a glass plate, a plate with an aluminum layer formed thereon, a silicon wafer with an aluminum layer formed thereon or an aluminum plate. Preferably, the carrier  20  is a silicon wafer with an aluminum layer sputtered thereon. It should be noted that the carrier  20  is not limited to the above-described materials. Instead, the carrier  20  can be made of any rigid material. 
     Referring to  FIG. 2B , a first metal layer  22  is formed on a surface of the first dielectric layer  21  by sputtering. A portion of the first metal layer  22  is formed in the first openings  210  of the first dielectric layer  21 . 
     Then, a resist layer  23   a  such as photoresist is formed on the first metal layer  22  by coating, and further patterned through exposure and development such that a plurality of openings  230   a  are formed in the resist layer  23   a  for exposing portions of the first metal layer  22  in the first openings  210  and on the first dielectric layer  21 . 
     In the present embodiment, the first metal layer  22  can be used a seed layer for electroplating, and the first metal layer  22  can be made of, but not limited to, Ti, Cu, Ni, V, Al, W, Au or a combination thereof. 
     Referring to  FIG. 2C , a circuit layer  24  is formed on the exposed portions of the first metal layer  22  by using the first metal layer  22  as a current conductive path. 
     In the present embodiment, the circuit layer  24  can be made of, but not limited to, Cu or Al. 
     Referring to  FIG. 2D , the resist layer  23   a  is stripped and the first metal layer  22  under the resist layer  23   a  is removed by etching. 
     Referring to  FIG. 2E , a second dielectric layer  25  is formed on the first dielectric layer  21  and the circuit layer  24  by coating, and patterned through exposure and development such that a plurality of second openings  250  are formed in the second dielectric layer  25  for exposing portions of the circuit layer  24 . 
     Then, a second metal layer  26  is formed on a surface of the second dielectric layer  25  by sputtering. A portion of the second metal layer  26  is formed in the second openings  250  of the second dielectric layer  25 . 
     In the present embodiment, the second dielectric layer  25  can be made of polyimide (PI), benezocyclobutene (BCB) or polybenzoxazole (PBO). The second metal layer  26  can be made of, but not limited to, Ti, Cu, Ni, V, Al, W, Au or a combination thereof. 
     Referring to  FIG. 2F , another resist layer  23   b  such as photoresist is formed on the second metal layer  26  by coating, and further patterned through exposure and development such that a plurality of openings  230   b  are formed in the resist layer  23   b  for exposing portions of the second metal layer  26  in and around the second openings  250 . 
     Then, by performing an electroplating process that uses the second metal layer  26  as a current conductive path, a plurality of conductive bumps  27  are formed on the exposed portions of the second metal layer  26  for electrically connecting the circuit layer  24 . 
     In the present embodiment, the conductive bumps  27  can be made of, but not limited to, a solder material, such as a Sn—Ag lead-free solder material. The solder material can also contain Cu, Ni or Ge. The second metal layer  26  can serve as a UBM (Under Bump Metallurgy) layer. 
     Referring to  FIG. 2G , the resist layer  23   b  is stripped and the second metal layer  26  under the resist layer  23   b  is removed by etching. Then, the conductive bumps  27  are reflowed. 
     Referring to FIG.  2 G′, in another embodiment, the first and second dielectric layers  21 ′,  25 ′ can be made of silicon dioxide (SiO 2 ) or silicon nitride, and formed through PECVD (Plasma-Enhanced Chemical Vapor Deposition). Further, the first and second openings  210 ′,  250 ′ are formed through dry etching. 
     If the carrier  20  is an aluminum plate or a silicon wafer having an aluminum layer sputtered thereon, an electrical test can be performed to obtain the yield rate of the circuit layer  24  and the conductive bumps  27 . If it is detected that the circuit layer  24  and the conductive bumps  27  are of low quality, the overall structure, i.e., the carrier  20  and the structure thereon, is discarded without performing subsequent die mounting and packaging processes, thereby effectively controlling the quality of the structure and avoid discarding good semiconductor components. 
     Referring to  FIG. 2H , continued from  FIG. 2G , a semiconductor component  28  is mounted on the conductive bumps  27 . The semiconductor component  28  has an active surface  28   a  and an inactive surface  28   b  opposite to the active surface  28   a , and the semiconductor component  28  is mounted on the conductive bumps  27  via the active surface  28   a  thereof. 
     In the present embodiment, the semiconductor component  28  has a plurality of electrode pads  280  bonding with copper conductive portions  280   a , respectively. Further, a solder material or an adhesive material  280   b , such as a non conductive paste (NCP) or an anisotropic conductive film (ACF), can be selectively formed on the conductive portions  280   a . By performing a reflow process or a dispensing process, the conductive portions  280   a  are accurately aligned and electrically connected to the conductive bumps  27  so as to form solder joints  27 ′, thereby securing the semiconductor component  28  to the second dielectric layer  25 , as shown in  FIG. 2I . 
     In the present embodiment, the semiconductor component  28  is a single chip. In other embodiments, the semiconductor component  28  can be a chip stack structure. 
     Referring to FIG.  2 H′, continued from  FIG. 2G , the carrier  20  is removed to expose the first metal layer  22 , thereby forming a wafer level packaging substrate  2   a . If the carrier  20  is a silicon wafer, a grinding process can be performed first so as to reduce the thickness of the carrier  20  to a certain value and then a dry etching process and a chemical mechanical polishing (CMP) process are performed to remove the remaining portion of the carrier  20 . 
     In another embodiment, referring to FIG.  2 H″, continued from  FIG. 2D , a redistribution layer structure  24   a  is formed on the first dielectric layer  21  and the circuit layer  24  and a second dielectric layer  25  is further formed on the redistribution layer structure  24   a.    
     In the present embodiment, the redistribution layer structure  24   a  has at least a dielectric layer  240 , a circuit layer  241  formed on the dielectric layer  240  for electrically connecting the circuit layer  24  and the conductive bumps  27 . 
     Referring to  FIG. 2I , continued from  FIG. 2H , an underfill  29   a  is disposed between the semiconductor component  28  and the second dielectric layer  25 , and an encapsulant  29   b  is formed on the second dielectric layer  25  to encapsulate the semiconductor component  28  and the underfill  29   a.    
     Referring to  FIG. 2J , the encapsulant  29   b  is ground to reduce its thickness. 
     Thereafter, the carrier  20  is removed to expose the first metal layer  22 . For example, if the carrier  20  is a silicon wafer, a grinding process is performed first so as to reduce the thickness of the carrier  20  to a certain value, and then a dry etching process and a CMP process are performed to remove the remaining portion of the carrier  20 . 
     Referring to  FIG. 2K , a plurality of conductive elements  30  are disposed on the first metal layer  22  such that the first metal layer  22  serves as a UBM layer. Then, a singulation process is performed. 
     In the present embodiment, the conductive elements  30  can be, but not limited to, solder balls, conductive bumps or conductive pins. 
     Referring to FIG.  2 K′, if the process is continued from FIG.  2 G′, a semiconductor package  2 ′ is obtained. 
     If the process is continued from FIG.  2 H″, a semiconductor package having the redistribution layer structure  24   a  is obtained. 
     Further, referring to FIG.  2 K′, in order to overcome the void problem during a molding process, the underfill  29   a  can be omitted such that an encapsulant  29   b ′ is formed through the molding process. Furthermore, through a grinding process, the top surface of the encapsulant  29   b ′ can be flush with the inactive surface  28   b  of the semiconductor component  28  such that the inactive surface  28   b  of the semiconductor component  28  is exposed from the encapsulant  29   b ′, thereby improving the heat dissipating effect. 
     Therefore, by forming the circuit layer  24  before performing processes such as forming the encapsulant  29   b ,  29   b ′,  29   b ″, the present invention prevents the positioning accuracy of the semiconductor component  28  from being adversely affected by the CTE of the encapsulant  29   b ,  29   b ′,  29   b ″ and eliminates the thermal effect of an RDL process on the semiconductor component  28  as in the prior art. Therefore, an increase in the size of the carrier  20  does not result in an increase in the position error of the semiconductor components  28 , thereby facilitating accurate control of the position of the semiconductor components  28 . For example, for a semiconductor component  28  having an electrode pad pitch of 40 um, its position can be accurately aligned in a 12-inch wafer (carrier  20 ) without being adversely affected by the CTE and flexibility of a thermal release tape, thus improving the product yield and saving the cost. 
     Further, the present invention can detect the yield rate of the circuit layer  24  before mounting the semiconductor component  28 . If the circuit layer  24  is detected to be of low quality, the structure is directly discarded without performing subsequent processes such as mounting the semiconductor component  28 . Therefore, the present invention does not discard good semiconductor components as in the prior art when the circuit layer is detected to be of low quality, thereby saving material costs and achieving cost efficiency. 
     Furthermore, since the surface of the carrier  20  is conductive, after the circuit layer  27  and the conductive bumps  27  are formed, an electrical test can be performed (without the need to electrically connect another electronic device) to detect the yield rate of the circuit layer. As such, subsequent processes such as mounting semiconductor components are performed only when the circuit layer is detected to be of high quality, thereby improving the product yield and saving the fabrication time. 
     According to the present invention, the conductive portions of a semiconductor component are aligned to the corresponding conductive bumps, respectively, and an encapsulant is formed to encapsulant the semiconductor component, and then the carrier is removed so as to prevent the positioning accuracy of the semiconductor component from being adversely affected by a thermal release tape as in the prior art, thereby improving the product yield and saving the fabrication cost. 
     In addition, the present invention can detect the yield rate of the circuit layer before mounting semiconductor components so as to avoid discarding good semiconductor components as in the prior art, thereby saving the fabrication cost and improving the product yield. 
     The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.