Abstract:
A power loss detector for generating a signal indicating the need to switch from a main power supply to an auxiliary power supply responsive to detecting that the main power supply has dropped below a predetermined threshold.

Description:
FIELD OF THE INVENTION 
     The invention pertains to power loss detection in a circuit. More particularly, the invention pertains to detecting loss of a main power supply in order to generate a control signal for switching to an auxiliary power supply. 
     BACKGROUND OF THE INVENTION 
     Many electronic devices are designed with auxiliary power supplies that turn on when a main power supply fails. For instance, it is desirable and, in fact, standard practice to provide an on-board battery back-up power source in computers for keeping the time and date clock circuitry running when the main power source for the computer is off so that the computer always has the current date and time available. For example, in a laptop computer, a power supply detector circuit must be provided to detect when the portable laptop computer is plugged into an AC outlet. When it is plugged into an AC outlet, power to run the computer is supplied from the AC outlet. However, when the computer is unplugged, that absence of the power from the AC input terminal of the computer must be detected so that the computer can be switched over to operate from the on-board battery power supply. 
     In general, the power loss detector circuits of the prior art comprise a comparator for comparing the voltage supplied by the main power supply to the voltage supplied by the auxiliary (e.g., battery) power supply. The voltage provided by the main power supply and the voltage provided by the battery are provided to the two inputs of a comparator through respective voltage dividers. The voltage dividers are ratioed so that the comparator output switches states when the main power supply drops below a predetermined threshold. For instance, in a notebook computer, the 120V AC power available from an outlet is converted to 3.3V DC which is used to power all the circuits in the computer. The battery, on the other hand, may be regulated to provide 3V of power. The resistor dividers corresponding to the main power and the auxiliary power may be ratioed such that the comparator output will switch states when the main power supply drops below 2.8V. The output of the comparator is then used as a main power supply loss indicator signal. When that signal switches state, indicating that the main power supply has dropped below 2.8V, a power supply switching circuit switches to auxiliary power. 
     U.S. Pat. No. 5,457,414 entitled Power Supply Loss Sensor discloses another power loss detector circuit. In the circuit disclosed in that patent, ring oscillators and other digital circuitry are used in the scheme for detecting power loss. 
     In both of the above-described schemes, the auxiliary or battery power supply is compared to the main power supply. Accordingly, a constant DC drain on the auxiliary power supply is needed for the operation of the power loss detector circuit. Over very long periods of time between rechargings, the battery can be completely drained. 
     Accordingly, it is an object of the present invention to provide an improved power loss detection method and apparatus. 
     It is another object of the present invention to provide a power loss detection method and apparatus which does not consume DC power from the auxiliary power supply. 
     SUMMARY OF THE INVENTION 
     The invention is a power loss detector circuit for an integrated circuit that asserts a signal when the main power drops below a predetermined threshold. The detector circuit is very simple and comprises two transistors, a resistor divider network and, optionally, an inverter. 
     The main power source is supplied to one end of the voltage divider. The voltage divider produces a voltage signal that is a fraction of the main power supply voltage. The main power supply voltage also is provided to the source terminal of a transistor. The fractional voltage is provided to the gate terminal of the same transistor. The voltage divider is configured such that the difference between the power supply voltage and the fractional voltage when the power supply voltage is at the minimum acceptable level is equal to the threshold voltage of the transistor. The minimum acceptable level is the point at which it is desired to switch from the main power supply to an auxiliary power supply. Thus, when the main voltage supply is greater than the minimum acceptable level, the transistor is turned on. Otherwise, it is off. The drain of the transistor is coupled to the output node of the detector circuit. This node is also coupled to the drain of a second transistor having its source coupled to ground. The gate of the second transistor is coupled to the auxiliary power supply such that the second transistor is on as long as the auxiliary power supply is sufficient, i.e, greater than the threshold voltage of the second transistor. Alternately, the gate of the second transistor is coupled to a second voltage level through an inverter that is powered by the auxiliary power supply. 
     Thus, when the main voltage supply is greater than the minimum acceptable level, the transistor is turned on. Otherwise, it is off. The drain of the transistor is coupled to the output node of the detector circuit. This node is also coupled to the drain of a second transistor having its source coupled to ground. The gate of the second transistor is coupled to the auxiliary power supply such that the second transistor is on as long as the auxiliary power supply is sufficient, i.e, greater than the threshold voltage of the second transistor. 
     The second transistor has a much longer channel than the first transistor so that it has a much higher impedance. Accordingly, regardless of whether the second transistor is on or off, if the main power supply is above the minimum acceptable level, the output node is driven to the voltage provided by the main power supply, i.e., logic high. Thus, a logic high at the output node indicates that the main power supply is operational and should be used to power the integrated circuit. Only when the main power supply drops below the minimum level, thus turning the first transistor off, can the second transistor drive the output terminal to ground (i.e., logic low). Accordingly, a logic low level at the output node indicates that the main power supply is off or has dropped below the predetermined minimum voltage and power should be switched to auxiliary power. 
     The circuit draws no DC current from the auxiliary power supply. The auxiliary power supply used to power the inverter draws only transient current when the comparator output switches. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a power loss detector circuit in accordance with the present invention. 
     FIG. 2 is a circuit diagram of a second embodiment of a power supply loss detector circuit in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 is a circuit diagram of a power loss detector circuit in accordance with the present invention. Circuit  10  comprises a resistor divider network  14  comprising resistors  16  and  18 , a p-channel transistor  20 , and an n-channel transistor  22 . A main power supply  12 , V Main , is supplied to one of the current flow terminals (e.g., the source terminal) of the p-channel transistor  20 . It also is supplied to the top of the resistor divider network  14 . In most integrated circuits, nominal main power is usually either 3.3 volts or 5 volts and is derived from an AC power source through a step-down DC rectifier circuit. 
     The resistor divider network  14  comprises two resistors  16  and  18  and a node  19  between the resistors  16  and  18 . Node  19  is provided to the control terminal (i.e., the gate) of p-channel transistor  20 . The other current flow terminal of transistor  20  (the drain) is coupled to node  21 , which is the output node of the detector circuit that indicates when to switch between the main and auxiliary power sources. Resistor divider network  14  generates a voltage at node  19  which is a fraction of V Main  (hereinafter termed V MainR ). The ratio between V Main  and V MainR , of course, remains the same regardless of the value of V Main . Therefore, as V Main  drops in voltage, the ratio between V Main  and V MainR  remains the same, but the difference between V Main  and V MainR  decreases. V Main  is supplied to the gate of transistor  20 . Thus, transistor  20  is turned on and off as a function of the difference between V Main  and V MainR . In particular, as the voltage V Main  decreases, the difference between V Main  and V MainR  decreases (because the ratio therebetween stays the same). When V Main −V MainR  is greater than the threshold voltage of p-channel transistor  20 , transistor  20  is on. However, when V Main −V MainR  drops below the threshold voltage of transistor  20 , transistor  20  is turned off. Resistors  16  and  18  of resistor divider network  14  are ratioed so that V Main −V MainR  will be equal to the threshold voltage of transistor  20  when V Main  is the minimum voltage desired from the main power supply before power should be switched over to the auxiliary power supply, e.g., 2.8 volts. 
     N-channel transistor  22  has one of its current flow terminals (e.g., its source terminal) coupled to ground, the other current flow terminal (drain) coupled to node  21 , and its control terminal (gate) coupled to the auxiliary power supply, V Aux . Accordingly, the gate of n-channel transistor  22  is held high and n-channel transistor  22  is on at all times. However, transistor  22  has a very long channel relative to transistor  20  and thus offers a higher impedance between node  21  and ground than the impedance of transistor  20  between V Main  and node  21 . Accordingly, with transistor  20  on, node  21  remains high even when transistor  22  is on. Specifically, node  21  is held at approximately V Main  (the actual voltage at node  21  is slightly below V Main  because of the small voltage drop across transistor  20  and the small current drain to ground through transistor  22 ). However, when V Main  drops below the minimum acceptable voltage, transistor  20  turns off. Then, transistor  22  will quickly drive node  21  to ground. 
     Note that if the auxiliary power supply fails while the main power supply is still operational, the circuit  10  still operates in the same manner. Specifically, if V aux  drops to zero volts, it turns off transistor  22 . However, this has no affect on output node  21  which, as mentioned above, is held high when the main power supply is above the minimum acceptable level regardless of whether transistor  22  is on or off. 
     The signal on node  21  is provided to a power supply switching circuit  30 . Power supply switching circuit  30  is designed to select the main power supply to power the integrated circuit when signal  29  is high and to switch to the auxiliary power supply when line  29  goes low. 
     Accordingly, circuit  10  provides the necessary control signal (the signal at node  21 ) indicating when the main power supply has dropped below an acceptable level. Circuit  10  draws no DC current from the auxiliary power supply since it is used for no purpose in circuit  10  other than as the input to the high impedance gate of transistor  22 . 
     FIG. 2 illustrates a preferred embodiment of the invention particularly adapted for use in a circuit which must be IDDQ friendly. IDDQ friendly chips must be able to be placed in a quiescent state in which the chip draws no power so the chip to be tested for various purposes. FIG. 2 illustrates a circuit  100  in accordance with the present invention adapted for IDDQ friendly mode operation. Those circuit components which are the same as those shown in the FIG. 1 embodiment bear the same reference numerals. The circuit of FIG. 2 is essentially the same as that of circuit  1  except that for the addition of transistor  102  and inverters  104 ,  106  and  108 . The current flow terminals of transistor  102  are coupled between V Main    12  and the resistor divider network  14 . The gate of p-channel transistor  102  is coupled to an IDDQ friendly mode signal (shown in the drawing as LP for Low Power). LP is also coupled to the input of an inverter  104 . Inverter  104  drives the gate of n-channel transistor  22  rather than V aux . However, V aux  provides the power to inverter  104 . Further, in a preferred embodiment, inverters  106  and  108  are added at the output in order to buffer the output node  21  from the power supply switching circuit  30 . Inverters  106  and  108  also receive their power from V AUX . 
     In normal operation (i.e., non-IDDQ friendly mode), operation is essentially exactly as described above in connection with FIG.  1 . Particularly, since LP is at logic low, transistor  102  is fully on and has essentially no affect on circuit operation. Further, the gate of transistor  22  is held at logic high (by virtue of inverter  104  being powered by V aux ), just as in the FIG. 1 embodiment. 
     However, in IDDQ friendly mode, LP is asserted high. Accordingly, transistor  102  is turned off such that V main  does not reach the voltage divider  14 . Accordingly, node  19  of resistor voltage divider goes to ground. Since the source of transistor  20  is still coupled directly to V main , transistor  20  remains on. With LP asserted high, the output of inverter  24  now goes low turning transistor  22  off. Therefore, node  21  remains high, thus instructing power supply switching circuit  30  to provide power to the circuit from the main power supply V Main . Thus, in IDDQ friendly mode, resistor divider network  14  draws no power, yet still maintains a logic high level on node  21  to indicate that main power is to remain in use. Inverters  106  and  108  are not necessary, but are provided in a preferred embodiment to buffer node  21  from the power supply switching circuit  30 . Like inverter  104 , inverters  106  and  108  are powered by the auxiliary power supply rather than the main power supply because they need to remain functional when the main power supply fails so that the circuit can be switched over to auxiliary power. 
     It should be understood that, while the detector circuit of the present invention has been described above in connection with several preferred embodiments utilizing CMOS transistors, the circuit can be readily implemented with other types of transistors. Further, logic level polarities and magnitudes can be readily changed without departing from the spirit of the invention. 
     Having thus described a few particular embodiments of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications and improvements as are made obvious by this disclosure are intended to be part of this description though not expressly stated herein, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only, and not limiting. The invention is limited only as defined in the following claims and equivalents thereto.