Abstract:
A voltage regulation scheme for an on-chip voltage generator includes a voltage sensing circuit (VSC) and a configurable buffer circuit (CBC) to regulate the on-chip voltage generator. The CBC generates an output signal that is received by the on-chip voltage generator to activate and de-activate the voltage generator. The VSC generates a voltage level detection (VLD) signal having a voltage level that is a function of the level of the on-chip generated voltage. The CBC receives a control signal that is used to dynamically configure the chip into an operational mode, as well as the VLD signal. In response to the control signal, the switch threshold of the CBC is configured to a predetermined level corresponding to the selected operational mode. The predetermined trip point causes the CBC to appropriately activate and de-activate the on-chip voltage generator to regulate the on-chip generated voltage at the level required by the configured operational mode. One embodiment of the CBC uses a configurable pull-up circuit to alter its switch threshold or trip point. The configurable pull-up circuit is used to pull-up the voltage at an intermediate node that is buffered and propagated to the on-chip voltage generator to activate and de-activate the voltage generator. The configurable pull-up circuit more strongly pulls up this voltage in one operational mode compared to another operational mode to alter the switch threshold.

Description:
FIELD OF THE INVENTION 
   The present invention relates to integrated circuits and, more particularly, to on-chip voltage generators for integrated circuits. Still more particularly, the present invention is related to voltage generators that can be adjusted for different operational modes. 
   BACKGROUND 
   Many integrated circuits (commonly referred to as “chips”) have more than one operational mode. For example, the chip may have a normal mode during which the chip performs the normal functions for which the chip was designed; e.g., in a memory chip, the normal mode might be to process memory access requests. In addition, the chip may have test modes in which the chip is tested to determine whether the chip is functioning properly. One test mode is commonly referred to as “burn-in”. The burn-in mode is a reliability test mode during which the chip is operated while “stressed” to a degree that is greater than expected in normal operating conditions. For example, a chip might be stressed in a burn-in test by heating the chip to a relatively high temperature while powering the chip with a relatively high supply voltage VDD. Burn-in mode is commonly used to find chips that would most likely fail after a short period of use. Hereinafter, the level or value of supply voltage VDD during normal mode will be referred to as VDD N  and during burn-in mode as VDD BI . 
   However, burn-in modes may damage otherwise good chips that have on-chip voltage generators. In particular, some chips have on-chip voltage generators that provide a negative supply voltage used to “back-bias” a substrate so as to control the threshold voltage Vtn of N-channel field effect transistors (NFETs). This negative supply voltage is commonly referred to as the VBB supply voltage. The negative substrate supply voltage VBB together with supply voltage VDD being at the higher burn-in level VDD BI  may result in some transistor devices being subjecting to voltages exceeding the devices&#39; breakdown voltage, thereby damaging these devices. Still further, some chips also have an on-chip voltage generator providing a boosted supply voltage having a level of about a volt higher than supply voltage VDD. Thus, the boosted supply voltage can further exacerbate the breakdown voltage problem. 
   One conventional solution to this problem is shown in  FIG. 1  in which the level of negative supply voltage VBB is adjusted to a less negative value VBB BI  during burn-in mode. This scheme reduces the difference between VDD BI  and VBB BI  to a value that is less than the breakdown voltage of the devices in the chip. 
   Conventional system  10  includes a normal mode section implemented by a voltage sensing circuit (VSC)  11  and a buffer circuit  12 . VSC  11  has an output lead connected to an input lead of buffer circuit  12 , which has an output lead that is connected to an input lead of a multiplexer  13 . VSC  11  is configured to detect whether the supply voltage VBB has reached a predetermined normal mode VBB threshold. The normal mode VBB threshold is typically set to about −VDD/2, where VDD is the value of the VDD supply voltage. When the level of negative supply voltage VBB reaches the normal mode VBB threshold, VSC  11  asserts a voltage level detect signal VLD N , which is propagated by buffer circuit  12  to multiplexer  13 . 
   System  10  also includes a burn-in section implemented by burn-in VSC  15  and a buffer circuit  16 , which is also connected to multiplexer  13 . VSC  15  is configured to detect whether the level of negative supply voltage VBB has reached a predetermined burn-in mode VBB threshold. The burn-in mode VBB threshold is set to a level that is less negative than the normal mode VBB threshold. When the level of supply voltage VBB reaches the burn-in mode VBB threshold, VSC  15  asserts a voltage level detect signal VLD BI , which is propagated by buffer circuit  16  to multiplexer  13 . 
   Multiplexer  13  has an output lead connected to a charge pump (CP)  19  and a select lead connected to receive a burn-in control signal BI. Typically, signal BI is provided from an on-chip test mode register (not shown) that is loaded by an external tester (not shown). Signal BI is asserted to configure system  10  into the burn-in mode. Alternatively, on-chip detection circuitry may be used to detect when the supply voltage is at the burn-in mode level and assert signal BI. 
     FIG. 2  is a timing diagram illustrative of the operation of system  10  when initially powered up. The level of supply voltage VBB is represented by a waveform  21 , with control signal BI being represented by a waveform  23 . Voltage level detection signals VLD N , VLD BI  and VLD O  are respectively represented by waveforms  25 ,  27  and  29 . In this embodiment, VSCs  11  and  15  are voltage divider type VSCs. Consequently, signals VLD N  and VLD BI  are analog signals, but for clarity are shown as digital signals in FIG.  2 . In this example, system  10  uses a three volt VDD supply voltage, with normal mode and burn-in mode VBB thresholds being about −1.5 volts and −1.0 volts, respectively. 
   Referring to  FIGS. 1 and 2 , in this example the chip is powered up in burn-in mode. Because initially the value of supply voltage VBB is about zero volts, VSCs  11  and  15  de-assert signals VLD N  and VLD BI  (i.e., at logic high levels). During the burn-in mode, signal BI is asserted (i.e., at a logic high level), thereby causing multiplexer  13  to select the output signal from buffer circuit  16 . Consequently, signal VLD BI  essentially serves as signal VLD O  during burn-in mode. The logic high level of signal VLD O  activates charge pump  19  to begin negatively increasing the level of VBB supply voltage. Thus, initially, waveform  21  has a negative slope, negatively increasing from about zero volts as indicated by arrow  21   1 . 
   When the level of supply voltage VBB reaches −1.0 volts (i.e., the burn-in mode VBB threshold), VSC  15  asserts the active low signal VLD BI , thereby causing signal VLD O  to transition to a logic low level, as indicated by arrows  21   2  and  27   1 . The logic low level of signal VLD O  de-activates charge pump  19 , causing the level of supply voltage VBB to stabilize at about −1 volt as indicated by arrow  21   3 . 
   Conversely, when signal BI is de-asserted to configure the chip into the normal mode, multiplexer  13  selects signal VLD N  (generated by VSC  11  and buffered by buffer circuit  12 ) to serve as output voltage level detection signal VLD O . As described above, VSC  11  de-asserts the active low signal VLD N  when the level of negative supply voltage VBB is less negative than the normal mode VBB threshold. Thus, when signal BI is de-asserted, signal VLD O  is also de-asserted as indicated by arrow  23   1  because the normal mode VBB threshold is more negative than the burn-in mode VBB threshold. Consequently, charge pump  19  is activated, causing the level of negative supply voltage VBB to negatively increase as indicated by arrow  21   4 . 
   When the level of negative supply voltage VBB reaches the normal mode VBB threshold, VSC  11  asserts signal VLD N  causing signal VLD O  to also be asserted, as indicated by arrows  21   5  and  25   1 . As a result, charge pump  19  is de-activated, allowing the level of negative supply voltage VBB to stabilize at about the normal mode VBB threshold of about −1.5 volts as indicated by arrow  21   6 . However, one problem with this conventional approach is that the separate burn-in section occupies a relatively large portion of chip area that could be used for other circuitry. Thus, there is a need for an approach that provides normal mode and burn-in mode VBB threshold detection while occupying minimal area on the chip. 
   SUMMARY 
   In accordance with the present invention, a voltage regulation scheme for an on-chip voltage generator is provided that is configurable to support different operational modes that require the on-chip generated voltage to be different for each operational mode. One embodiment includes a voltage sensing circuit (VSC) and a configurable buffer circuit (CBC) to regulate the on-chip voltage generator. The CBC generates an output signal that is received by the on-chip voltage generator to activate and de-activate the voltage generator. The VSC generates a voltage level detection (VLD) signal having a voltage level that is a function of the level of the on-chip generated voltage. 
   More specifically, the CBC is connected to receive a control signal that is used to configure the chip into an operational mode, as well as to receive the VLD signal. In response to the control signal, the switch threshold or trip point of the CBC is configured to a predetermined level corresponding to the selected operational mode. In particular, a trip point is predetermined for each operational mode so that the CBC will appropriately activate and de-activate the on-chip voltage generator to regulate the on-chip generated voltage at the level required by that operational mode. This configurable on-chip voltage regulation scheme advantageously requires less circuitry than the aforementioned conventional scheme, thereby reducing the chip area occupied by the regulator circuitry. In addition, this scheme reduces power consumption by eliminating a VSC, which can dissipate a relatively large amount of power. 
   In one aspect of the present invention, the CBC uses a configurable pull-up circuit to alter its switch threshold or trip point. The configurable pull-up circuit is used to pull-up the voltage at an intermediate node that is then buffered and propagated to the on-chip voltage generator to activate and de-activate the voltage generator. In one operational mode, the configurable pull-up circuit more strongly pulls up this voltage compared to another operational mode, thereby altering the switch threshold. In another aspect of the present invention, the CBC uses a configurable pull-down circuit to achieve a similar result. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a functional block diagram illustrative of a conventional on-chip voltage generator system for adjusting an on-chip voltage generator for burn-in mode. 
       FIG. 2  is a timing diagram illustrative of the operation of the system of FIG.  1 . 
       FIG. 3  is a functional block diagram illustrative of a dynamically adjustable on-chip voltage generator system, according to one embodiment of the present invention. 
       FIG. 4  is a timing diagram illustrative of the switch threshold levels of a dynamically configurable buffer circuit (CBC) according to one embodiment of the present invention. 
       FIG. 5  is a functional block diagram illustrative of a CBC having a configurable pull-up circuit, according to one embodiment of the present invention. 
       FIG. 6  is a functional block diagram illustrative of a CBC having a configurable pull-down circuit, according to one embodiment of the present invention. 
       FIG. 7  is a schematic diagram illustrative of one implementation of the CBC of FIG.  5 . 
       FIG. 8  is a timing diagram illustrative of the operation of the CBC of FIG.  7 . 
       FIG. 9  is a schematic diagram illustrative of one implementation of the CBC of FIG.  6 . 
   

   DETAILED DESCRIPTION 
     FIG. 3  is a functional block diagram illustrative of a dynamically adjustable on-chip voltage generator system  30 , according to one embodiment of the present invention. For clarity, the same reference numbers are used between drawings to indicate elements having the same or similar function or structure. System  30  includes VSC  11 , charge pump  19  and a configurable buffer circuit (CBC)  32 . As in system  10 , VSC  11  is configured to detect when negative supply voltage VBB reaches the normal mode VBB threshold. VSC  11  generates at a lead  34  an output signal VLD, which has a voltage that is a function of the level of negative supply voltage VBB. In particular, VSC  11  is configured to generate signal VLD so that when the negative supply voltage reaches the normal mode VBB threshold, signal VLD ideally has a value equal to the normal mode switch threshold or trip point of CBC  32 . In this embodiment, signal VLD is essentially proportional to the magnitude of negative supply voltage VBB. 
   CBC  32  has an input terminal connected to lead  34 , a control terminal connected to receive signal BI through a lead  36  and an output terminal connected to charge pump  19  through a lead  38 . In accordance with the present invention, in response to control signal BI, CBC  32  has a switch threshold or trip point that is dynamically configurable into a normal mode trip point or a burn-in mode trip point. As used herein, the terms “switch threshold” or “trip point” refer to a voltage level that CBC  32 , in effect, compares to the voltage level of the input signal. If the voltage level of the input signal is below the trip point, CBC  32  detects the input signal as having a logic low level and, conversely, if the voltage level of the input signal is above the trip point, CBC  32  detects the input signal as having a logic high level. 
   As described above, VSC  11  generates signal VLD to have a voltage level proportional to the value of negative supply voltage VBB. The normal mode trip point of CBC  32  is predetermined so that CBC  32  will transition or switch when the levels of supply voltages VBB and VDD are respectively equal to about −1.5 volts and the normal mode VDD level (e.g., 3.3 volts). In contrast, the burn-in mode switch level is predetermined so that CBC  32  will switch when the levels of supply voltages VBB and VDD are respectively equal to about −1 volts and the burn-in mode VDD level (e.g., 5.5 volts). These switch thresholds for CBC  32  are described below in more detail in conjunction with FIG.  4 . 
     FIG. 4  is a timing diagram illustrative of the switch threshold levels of CBC  32  (FIG.  3 ), according to one embodiment of the present invention. The voltage levels of supply voltage VBB and signal VLD are represented by waveforms  40  and  41 , respectively. As described above in conjunction with  FIG. 3 , VSC  11  generates signal VLD with a voltage level that is proportional to the magnitude of negative supply voltage VBB. 
   Signal VLD O  during burn-in mode operation is represented by a waveform  43 . Before the voltage level of signal VLD (waveform  41 ) reaches the predetermined burn-in mode trip point of CBC  32 , CBC  32  generates signal VLD O  with a logic high level. However, when the voltage level of signal VLD reaches the predetermined burn-in mode switch level (indicated by point  44  on waveform  41 ), CBC  32  is configured to transition signal VLD O  to a logic low level, as indicated by arrow  45 . The logic low level of signal VLD O  turns off charge pump  19  (FIG.  3 ), allowing the voltage levels of supply voltage VBB and signal VLD to remain roughly constant as indicated by portions  40   1  and  41   1  of waveforms  40  and  41 . Of course, if the level of supply voltage VBB were to become less negative, then CBC  32  would transition signal VLD O  to a logic high level to turn on charge pump  19  ( FIG. 3 ) to pump supply voltage VBB to be more negative. 
   Signal VLD O  during normal mode operation is represented by a waveform  47 . Before the voltage level of signal VLD (waveform  41 ) reaches the predetermined normal mode trip point of CBC  32 , CBC  32  generates signal VLD O  with a logic high level. However, when the voltage level of signal VLD reaches the predetermined normal mode switch level (indicated by point  48  on waveform  41 ), CBC  32  is configured to transition signal VLD O  to a logic low level, as indicated by arrow  49 . The logic low level of signal VLD O  turns off charge pump  19  (FIG.  3 ), allowing the voltage levels of supply voltage VBB and signal VLD to remain roughly constant as indicated by portions  40   2  and  41   2  of waveforms  40  and  41 . Of course, if the level of supply voltage VBB were to become less negative, then CBC  32  would transition signal VLD O  to a logic high level to turn on charge pump  19  ( FIG. 3 ) to pump supply voltage VBB to be more negative. 
   As a result of these configurable switch thresholds, when in the normal mode, CBC  32  will generate signal VLD O  so as to switch to a logic low level when negative supply voltage VBB reaches −1.5 volts, whereas in the burn-in mode, CBC  32  will generate signal VLD O  so as to switch to a logic low level when negative supply voltage VBB reaches −1.0 volt. 
     FIG. 5  is a functional block diagram illustrative of one embodiment of CBC  32  (FIG.  3 ), according to the present invention. In this embodiment, CBC  32  includes a configurable pull up circuit (CPUC)  51 , a pull-down circuit (PDC)  53  and an inverting buffer  55 . More particularly, CPUC  51  has an input lead connected to lead  36  to receive signal BI, another input lead connected to lead  34  to receive signal VLD, and a pull-up lead connected to a node  57 . PDC  53  has an input lead connected to lead  34  and a pull-down lead connected to node  57 . Buffer  55  has an input lead connected to node  57  and an output lead connected to lead  38 . 
   This embodiment of CBC  32  operates as follows. In response to signal BI, CPUC  51  is configured into either the normal mode or the burn-in mode. CPUC  51  and PDC  53  form, in effect, an inverter with a configurable switch threshold or trip point. In particular, CPUC  51  is configured to more strongly pull up the voltage at node  57  when in the burn-in mode than in the normal mode, thereby altering the switch threshold of the inverter. Consequently, when CBC  32  is in the burn-in mode, the relatively stronger pull up action of CPUC  51  causes the switch threshold or trip point to be at a relatively higher positive voltage level, thereby resulting in CBC  32  asserting active low signal VLD O  at a relatively less negative value of supply voltage VBB. In this embodiment, CPUC  51  is configured so that in combination with PDC  53 , this trip point is reached when supply voltage VBB has a level of −1.0 volt. 
   Thus, at power up in burn-in mode, supply voltage VBB has a value of about zero volts. Consequently, VSC  11  ( FIG. 3 ) initially generates signal VLD with a logic high level, which causes CBC  32  to generate a logic low level signal at node  57 . In response to the logic low level at node  57 , inverting buffer  55  generates signal VLD O  with a logic high level, thereby activating charge pump  19  ( FIG. 3 ) to pump supply voltage VBB to be more negative. However, when the level of supply voltage VBB reaches −1.0 volt, CBC  32  “trips”, thereby outputting a logic high level signal at node  57 . The logic high level at node  57  causes inverting buffer  55  to generate signal VLD O  with a logic low level, thereby de-activating charge pump  19  (FIG.  3 ). 
   Conversely, when CBC  32  is configured in the normal mode, the relatively weaker pull up action of CPUC  51  causes the switch threshold or trip point to be at a relatively lower positive voltage level, thereby resulting in CBC  32  asserting active low signal VLD O  at a more negative value of supply voltage VBB. In this embodiment, CPUC  51  is configured so that in combination with PDC  53 , this trip point is reached when supply voltage VBB has a level of −1.5 volts. As described above, once CPUC  51  is tripped, the logic low level of signal VLD generated by VSC  11  ( FIG. 3 ) is propagated through CPUC  51  and buffer circuit  53  to de-activate charge pump  19  (FIG.  3 ). 
     FIG. 6  is a functional block diagram illustrative of one embodiment of CBC  32  ( FIG. 3 ) having a pull-up circuit  61  and a configurable pull-down circuit (CPDC)  63 , according to the present invention. This embodiment of CBC  32  is basically the converse of the embodiment of  FIG. 5 , with pull-up circuit (PUC)  61  and CPDC  63  respectively replacing CPUC  51  and PDC  53  (FIG.  5 ). 
   This embodiment of CBC  32  operates as follows. In response to signal BI CPDC  63  is configured into either the normal mode or the burn-in mode. CPDC  63  and PUC  61  form, in effect, an inverter with a configurable switch threshold or trip point. In particular, CPDC  63  is configured to less strongly pull down the voltage at node  57  when in the burn-in mode than in the normal mode, thereby altering the switch threshold of the inverter. Consequently, when CBC  32  is in the burn-in mode, the relatively weaker pull down action of CPDC  63  causes the switch threshold or trip point to be at a relatively higher positive voltage level, thereby resulting in CBC  32  asserting active low signal VLD O  at a relatively less negative value of supply voltage VBB (i.e., −1.0 volt). 
   Conversely, when CBC  32  is configured in the normal mode, the relatively stronger pull down action of CPDC  63  causes the switch threshold or trip point to be at a relatively lower positive voltage level, thereby resulting in CBC  32  asserting active low signal VLD O  at a relatively more negative value of supply voltage VBB (i.e., −1.5 volts). 
     FIG. 7  is a schematic diagram illustrative of one implementation of CBC  32  ( FIG. 5 ) having a configurable pull-up circuit. In addition, an embodiment of VSC  11  ( FIG. 3 ) is also schematically shown. In this embodiment, VSC  11  includes P-channel field effect transistors (PFETs) P 70 -P 73  and an inverter  71 . PFETs P 70 -P 73  are connected so that when turned on, their channel regions form a conductive path between a source of supply voltage VDD (e.g., a VDD bus) and a source of supply voltage VBB (e.g., a VBB bus). In particular, the gate of PFET P 70  is connected to the output lead of inverter  71 . The input lead of inverter  71  is connected to receive a low power control signal LP. Signal LP is generated by a control circuit (not shown) to configure the chip into a low power mode. When asserted, signal LP causes PFET P 70  to be turned off, thereby interrupting the current path between the VDD bus and the VBB bus through PFETs P 70 -P 73  to reduce power dissipation. 
   Referring again to PFET P 70 , the source and drain of PFET P 70  are respectively connected to the VDD bus and the source of diode-connected PFET P 71 . The gate and drain of PFET P 71  are connected to lead  34  and also to the source of diode-connected PFET P 72 . The gate and drain of PFET P 72  are connected to the source of diode-connected PFET P 73 . The gate and drain of PFET P 73  are connected to the VBB bus. 
   In this embodiment, CBC  32  includes an inverter  73 , a capacitor  75 , CPUC  51  (implemented by PFETs P 74 , P 77  and P 78 ), PDC  53  (implemented by N-channel field effect transistor or NFET N 75 ) and inverting buffer circuit  55  (implemented by three cascaded inverters  77 - 79 ). Capacitor  75  is implemented with a PFET having its source and drain connected together to form a first capacitor electrode, with the gate serving as the second capacitor electrode. 
   CBC  32  is interconnected as follows. The first and second capacitor electrodes of capacitor  75  are respectively connected the VDD bus and lead  34 . In addition, lead  34  is connected to the gates of FETs N 75 , P 74  and P 78 . The source and drain of PFET P 74  are respectively connected to the VDD bus and node  57 . The source and drain of NFET N 75  are respectively connected to a ground bus and node  57 . In addition, node  57  is connected to the drain of PFET P 78 . The source of PFET P 78  is connected to the drain of PFET P 77 . The gate and source of PFET P 77  are respectively connected to the output lead of inverter  73  and the VDD bus. The input lead of inverter  73  is connected to receive signal BI. 
   This embodiment of CBC  32  operates as follows. VSC  11  is configured so that when supply voltages VBB and VDD are respectively at −1.5 volts and the normal mode VDD level, the voltage level at lead  34  will be about equal to the normal mode trip point of CBC  32 . More specifically, the sizes of PFETs P 70 -P 73  are predetermined so that the voltage drop across each of these PFETs results in the voltage level at lead  34  being at about the normal mode trip point of CBC  32  when the levels of supply voltages VBB and VDD respectively are about equal to −1.5 volts and the normal mode VDD level. The sizes of PFETs P 70 -P 73  can be predetermined by modeling and simulation using conventional commercially-available modeling/simulation tools such as, for example, HSPICE. In addition, the sizes of these PFETs can be altered by means of spare devices that can be coupled to one or more of these PFETs through metal option. 
   FETs P 74  and N 75  essentially form a CMOS inverter, with a trip point that depends on their relative sizes. Generally, increasing the size (i.e., the width-to-length ratio) of the PFET pull-up device in effect increases the strength of the pull-up path, whereas increasing the size of the pull-down device generally increases the strength of the pull-down path. As is well known in the art of integrated circuits, increasing the strength of the pull-up path relative to the pull-down path raises the trip point of a CMOS inverter to a relatively higher positive voltage level, while increasing the strength of the pull-down path relative to the pull-up path lowers the trip point to a relatively less positive voltage level. This concept is used in the present invention to selectively alter the trip point of CBC  32  as follows. 
   PFETs P 77  and P 78  form a selectively activated pull-up path in parallel with PFET P 74  to alter the strength of pull-up path of the inverter formed by CPUC  51  and PDC  53 . In burn-in mode, signal BI is asserted, causing inverter  73  to provide a logic low level signal to PFET P 77 . Thus, the parallel pull-up path provided by PFETs P 77  and P 78  between the VDD bus and node  57  is enabled. As a result, the pull-up path is strengthened, thereby raising the trip point of the configurable inverter formed by CPUC  51  and PDC  53  (i.e., NFET N 75 ). The sizes of PFETs P 77  and P 78  of CPUC  51  can be predetermined through modeling and simulation under burn-in conditions so as to achieve a trip point corresponding to supply voltage VBB being equal to −1.0 volt. 
     FIG. 8  is a timing diagram illustrative of the operation of the system depicted in FIG.  7 . The voltage levels of signal VLD generated by VSC  11  and the configurable switch threshold (V ST ) of CBC  32  are respectively represented by waveform  81  and  83 . Referring now to  FIGS. 7 and 8 , during power up in the burn-in mode, charge pump  19  ( FIG. 3 ) pumps the level of supply voltage VBB to be more negative as indicated by arrow  21   1  in FIG.  8 . During the burn-in mode, CPUC  51  is configured to enable the parallel pull-up path formed by PFETs P 77  and P 78  so that V ST  (i.e., the burn-in mode switch threshold or trip point) is at a relatively high level as indicated by arrow  83   1 . Thus, at this initial stage, the voltage level of signal VLD remains above the burn-in mode trip point of CBC  32 , causing CBC  32  to generate signal VLD O  with a logic high level. 
   When the level of supply voltage VBB reaches −1.0 volts, the level of signal VLD reaches the burn-in mode trip point of CBC  32 , causing CBC  32  to generate signal VLD O  with a logic low level to de-activate charge pump  19  (FIG.  3 ). Thus, the level of supply voltage VBB stays roughly constant at about −1.0 volt as indicated by arrow  21   3 . 
   In normal mode operation, signal BI is de-asserted. As a result, inverter  73  provides a logic high level signal to the gate of PFET P 77 . Consequently, PFET P 77  is turned off, thereby disabling the pull-up path between the VDD bus and node  57  through PFETs P 77  and P 78 . Thus, PFETs P 77  and P 78  are in effect isolated from node  57  and do not affect the trip point of CBC  32 . Therefore, the trip point of CBC  32  depends essentially on FETs P 74  and N 75 , without PFETs P 77  and P 78 . In particular, the sizes of FETs P 74  and N 75  are predetermined in conjunction with the sizes of the PFETs of VSC  11  so as to achieve a trip point of CBC  32  that ideally is equal to the voltage level of signal VLD when the levels of supply voltages VBB and VDD are respectively equal to −1.5 volts and the normal mode VDD level. 
   Accordingly, when signal BI is de-asserted to configure CBC  32  into the normal mode, the parallel pull-up path formed by PFETs P 77  and P 78  in CPUC  51  is disabled as described above, thereby causing V ST  to transition to a relatively low level, as indicated by arrows  85  and  83   2  in FIG.  8 . Because the trip point is lowered, CBC  32  causes a low-to-high transition of signal VLD O  as indicated by arrow  86 , thereby re-activating charge pump  19  (FIG.  3 ). As a result, the level of supply voltage VBB again begins to negatively increase as indicated by arrow  21   4 . 
   When the level of supply voltage VBB reaches −1.5 volts, the level of signal VLD reaches the normal mode trip point of CBC  32 , causing CBC  32  to generate signal VLD O  with a logic low level to de-activate charge pump  19  (FIG.  3 ). Thus, the level of supply voltage VBB stays roughly constant at about −1.5 volts as indicated by arrow  21   6 . Accordingly, CBC  32  generates signal VLD O  to be essentially identical to signal VLD O  as generated by system  10  (FIG.  1 ), but with less circuitry. 
     FIG. 9  is a schematic diagram illustrative of one implementation of a CBC  90  having a configurable pull-down circuit as described in conjunction with FIG.  6 . In this embodiment, CBC  90  basically replaces CBC  32  ( FIG. 7 ) and is different from CBC  32  in that the pull-down path is configurable instead of the pull-up path. However, the same basic concept is used; i.e., increasing the strength of the pull-up path relative to the pull-down path raises the trip point of a CMOS inverter circuit to a relatively higher positive voltage level, while increasing the strength of the pull-down path relative to the pull-up path lowers the trip point to a relatively less positive voltage level. 
   This embodiment of CBC  90  includes inverting buffer  55 , CPDC  63  (implemented by NFETs N 75 , N 91 -N 93 ) and PUC  61  (implemented by PFET P 74 ). Unlike in the embodiment of  FIG. 7 , the source of NFET N 75  is connected to a node  95  instead of the ground bus. Node  95  is also connected to the drains of NFETs N 91  and N 92 . In addition, unlike CBC  32  (FIG.  7 ), the output lead of inverter  73  is connected to the gate of NFET N 91  instead of PFET P 77 , which is deleted from CBC  90  along with PFET P 78 , CBC  90  is further interconnected as follows. The source of NFET N 91  is connected to the ground bus. The gate and source of NFET N 92  are respectively connected to lead  34  to receive signal VLD and the drain of NFET N 93 . The gate and source of NFET  93  are respectively connected to lead  36  to receive signal BI and the ground bus. 
   Unlike CBC  32  (FIG.  7 ), this embodiment alters the strength of the configurable path by changing the “effective” channel length of the path instead of enabling/disabling a parallel path. Of course, the parallel path method may be used in different embodiments of CPDC  63  and, conversely, the configurable channel length method may be used in other embodiments of CPUC  51  (FIG.  5 ). CBC  90  may have slightly different switch thresholds or trip points than CBC  32  ( FIG. 7 ) and, therefore, the sizes of the PFETs in VSC  11  ( FIG. 7 ) may need to slightly changed so as to achieve the appropriate trip points for CBC  90 . 
   More specifically, in the burn-in mode, signal BI is asserted, thereby directly turning on NFET N 93  while turning off NFET N 91  via inverter  73 . As a result, during the burn-in mode, NFETs N 75 , N 92  and N 93  form the pull-down path. This three device pull-down path has a relatively long effective channel length. Thus, the burn-in mode pull-down path is relatively weak thereby causing the trip point of CBC  90  to be at a relatively high positive voltage level. 
   Conversely, in the normal mode, signal BI is de-asserted, thereby turning on NFET N 91  via inverter  73  while directly turning off NFET N 93 . As a result, during the normal mode, NFETs N 75  and N 91  form the pull-down path. This two device pull-down path has a relatively short effective channel length. Thus, the normal mode pull-down path is relatively strong, thereby causing the trip point of CBC  90  to be at a relatively low positive voltage level. Accordingly, in response to signals VLD and BI, CBC  90  provides essentially the same function as CBC  32  ( FIG. 7 ) in generating signal VLD O . 
   The embodiments of the adjustable on-chip voltage generation circuit described above are illustrative of the principles of the present invention and are not intended to limit the invention to the particular embodiments described. For example, in light of the present disclosure, those skilled in the art of integrated circuit design can devise other implementations for use with different supply voltages and supply voltage levels, including positive supply voltages, without undue experimentation. Also, voltage sensing circuits different from the types described can be used in other embodiments. In addition, those skilled in the art of logic circuits can implement equivalent logic for CBC  32  or CBC  90  adapted for use with control signals having polarities (i.e., being active high instead of active low or vice versa) that are different from the control signals described (e.g., signal BI). Accordingly, while the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention.