Abstract:
A pre-processor (10) for target trackers is disclosed which allows several image analysis algorithms to be computed simultaneously so as to provide improved real-time target recognition. The pre-processor (10) is also equipped to compensate for the rapid rotation of the target image when the tracking aircraft performs abrupt turning maneuvers.

Description:
FIELD OF THE INVENTION 
     This invention relates to target tracking devices, and more specifically to a pre-processor chip capable of running several different tracking algorithms concurrently or sequentially. 
     BACKGROUND OF THE INVENTION 
     Target tracking in high-performance aircraft involves the use of a pre-processor which analyzes the movement of a pilot-selected target across the video image seen by the pilot, and provides tracking information to a tracking device which centers the field of view of the sensor about the target. 
     Accurately recognizing and locating selected targets of different size, shape and intensity against complex backgrounds in successive fields of the video scan is no easy task. To provide reliable tracking, the image needs to be examined by several preprocessing algorithms which may be different for different kinds of targets. Tracking information is then derived from a comparison of the results of the algorithms used. Typically, such algorithms include geometric (for large targets) and intensity (for small targets) centroids, and convolution-based algorithms such as Sobel edge detection, brightness feature match correlation (BFMA) or Sum of Products, difference squared (Δ 2 ), and sequential similarity detection (SSDA) algorithms. 
     The pre-processing task is further complicated by the fact that during abrupt maneuvers of the aircraft, the target aspect changes rapidly as a result of image rotation. 
     A significant factor in the design of tracking pre-processors is the fact that all calculations have to be completed in no more than 15 ms so that a new set of results can be generated for each field of the 60 Hz video scan. In the prior art, it was necessary to provide a separate pre-processor for each algorithm to allow simultaneous computation of all the results within the available time interval--an undesirable situation from the point of view of cost, weight, size and power. 
     Prior art in this field includes: U.S. Pat. No. 4,363,104 to Nussmeier, which deals with a process for creating multiple images for simultaneous processing; U.S. Pat. No. 4,433,438 to Couturier, which discloses a circuit for processing the Sobel square root edge extraction algorithm; U.S. Pat. No. 4,464,789 to Sternberg in which successive images are analyzed for motion therebetween; U.S. Pat. No. 4,484,346 to Sternberg et al which ties multiple chips together but basically performs only a series of 3×3 convolutions; U.S. Pat. No. 4,484,349 to McCubbrey in which a plurality of pipelines simultaneously operate on adjacent segments of an image matrix; U.S. Pat. No. 4,499,597 to Alves which describes a centroid calculation; U.S. Pat. No. 4,750,144 to Wilcox which shows a circuit for convolution computations; and U.S. Pat. No. 4,790,026 to Gennery et al which discusses a modular pipelined image processor. 
     SUMMARY OF THE INVENTION 
     Considerable economy of cost, space and weight, together with improved performance, is achieved in a tracking device by providing a multi-function pre-processor (10) capable of being implemented on a single chip. The inventive pre-processor achieves this implementation by providing a set of pipeline processors (16, 18, 20) which selectively and sequentially process image data through several algorithms in the same pipeline, all within a time interval which allows a full set of data to be generated for each field of a 60 Hz video display. 
     A significant pin reduction is achieved by the use of an on-chip address generator (12) which permits a large number of reads and writes to be generated from a single address pointer input (15). Also, the address generator (12), by using a pair of pipelines (22, 24), can compensate internally of the chip for rotation of the image. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of the pre-processor of this invention; 
     FIGS. 2a through 2e, taken together, are a flow chart diagram illustrating the operation of the pre-processor; 
     FIGS. 3a through 3c illustrate the effect of the rotation compensation program of this invention; 
     FIG. 4 is a diagram illustrating the operation of the rotation compensation program; and 
     FIG. 5 is a flow chart diagram of the rotation compensation program. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIGS. 1a through 1c illustrate the architecture of the pre-processor 10 of this invention. In its preferred embodiment, the invention is implemented in a very large scale integrated (VLSI) gate array with more than 22,000 gates using 1.5μ CMOS technology. The pre-processor 10 runs at a clock rate of 16.67 MHz for a maximum throughput rate in excess of 83 MIPS. 
     Control of the pre-processor 10 is achieved through a twenty-two-pin general-purpose microprocessor interface 12 with one address pin, sixteen data pins, and five control pins. The provision of a single address pin, which results in a considerable saving in connections and buffers, is made possible by providing the address generator 14. When reading, or writing data, a single address pointer 15 is transmitted to the generator 14 over the data line 17. Thereafter, the generator 14 merely increments the address by 1 for each transmitted data byte. In this manner, a sequence of memory registers can be accessed for data entry or retrieval with a single address instruction. 
     During a first data pass, pipeline 16 computes the x-sums and y-sums of the centroid. Simultaneously, pipeline 18 computes the difference between the previous field&#39;s row and column pixel counts and those of the present one (DRPC and DCPC). Again simultaneously, pipeline 20 computes the row and column pixel accumulations for the centroid, as well as pixel intensity (if an intensity centroid is selected) or target intensity (if a geometric centroid is selected). 
     During a second data pass, pipeline 16 selectably computes either the BFMA or Δ 2  correlation algorithm. Simultaneously, pipeline 18 computes the SSDA algorithm. During this second pass, pipeline 20 is idle. 
     Pipelines 22 and 24 compute the sine and cosine rotation compensation factors, respectively, as described in more detail hereafter. These pipelines are part of the address generator 14, and their output serves to maintain, for evaluation purposes, the orientation of the target image as the aircraft performs rotational maneuvers. 
     The pipelines 16, 18 and 20 are arranged to perform different calculations depending upon status and timebase signals produced by the interface controller 12. In addition to these signals, the controller 12 generates mode control signals in response to external mode selection inputs. It also serves as an interface between the tracker device and the pre-processor 10. 
     Memory registers which are preferably not physically part of the pre-processor 10 but directly participate in its operation are provided by the acquisition RAM 26 and the results, mask and reference (RMR) RAM 28. The acquisition RAM 26 is preferably a 16K×8 RAM which allows a pilot-selected input image window of up to 128×128 pixels from a moving input image such as a forward-looking infrared (FLIR) video image to be stored. The RMR RAM 28 is preferably an 8K×16 RAM and is used for storing the masks and references required for the correlation algorithms. The results of all algorithms are also stored in the RMR RAM 28. 
     The operation of the pre-processor 10 is best illustrated by the flow chart of FIGS. 2a-e. The pre-processing begins with state=0 (idle) and the selected centroid mode active. The state is then incremented to 1, and the pipeline is filled from the previously loaded acquisition memory 26 for four timebase intervals. 
     When the state is incremented to 2, the results of the selected centroid algorithm are calculated. The calculation continues along a row of the window until the end of the row is reached (EQGX active). The state is then incremented to 3 for 4 timebase intervals, during which the pipeline is emptied and the final sum of the pixels in the row is determined. This is the RPC vector, which is stored in RMR RAM 28 when the state is incremented to 4. 
     In centroid calculation, DRPC is calculated during state 5. In state 6, the pipelines 16, 18, 20 and the row (x) counter are cleared. The column (y) counter is then incremented, and the centroid algorithm is repeated with column data loaded into the pipelines. When all columns have been summed (EQRY active), the state is incremented to 7, and an interrupt is generated to the tracker processor indicating that the results of the preprocessing are ready to be read out. For this purpose, the RPC and CPC values computed by pipeline 18 are stored in the RMR RAM, while the maximum and minimum DRPC and DCPC are held a the output of pipeline 18. 
     The pre-processor 10 functions similarly in the correlation mode. However, in the correlation mode, the results from pipeline 18 are stored at state 4, and the results from pipeline 16 are stored at state 5. 
     FIGS. 3a through 3c illustrate a feature of the invention which is useful in countering loss of correlation during violent rotational meneuvers of the aircraft. FIG. 3a shows a target 40 in an image 42 in one video field, while FIG. 3b shows the target 40 in the next video field if the aircraft has rotated 30° during that time. 
     In order to retain the same target aspect for pre-processing, the address generator 14 is provided with a pair of pipelines 22, 24 which, in response to an orientation signal provided by the tracker processor, computes address conversions that, in effect, result in the pipelines 16, 18, 20 being presented with the image of FIG. 3c in which the target 40 has the same aspect as in FIG. 3a. 
     The address generator 14 performs essentially the following derotation computation: 
     
         X=X&#39; cos θ-Y&#39; sin θ 
    
     
         Y=X&#39; sin θ+Y&#39; cos θ 
    
     where X&#39; and Y&#39; are the x- and y-addresses, respectively, of a given pixel in the derotated output image of FIG. 3c, X and Y are the x- and y-addresses of the same (i.e. conjugate) pixel in the input image of FIG. 3b, and θ is the angle of rotation. 
     The strategy for computing the location of each point in the output image of FIG. 3c in the input reference frame of FIG. 3b is as follows, reference being had to FIG. 4: 
     1) Compute leftmost top coordinates of the output image in the input frame. 
     2) Step ΔX H ,ΔY H  units in the input frame to reach the next pixel in the current frame. 
     3) Continue to end of the line. 
     4) Step down ΔX V ,ΔY V  from the starting point of the previous line to reach the location of the starting point of the next line. 
     5) Continue the above row and column operations until entire output image has been covered. 
     ΔX H ,ΔY H , ΔX V  and ΔY V  are computed as follows: 
     For any point X&#39;, Y&#39; in the output frame, stepping to the next point in the line is equivalent to incrementing X&#39; while holding Y&#39; constant, i.e. ##EQU1## 
     Similarly for any point X&#39;, Y&#39; in the output frame stepping down the next point in the column is equivalent to decrementing Y&#39; while holding X&#39; constant, i.e. ##EQU2## 
     The sequence of operations to carry out this operation is illustrated in the flow chart diagram of FIG. 5, which is self-explanatory.