Abstract:
The present document relates to a pre-charge circuit of electronic circuits having Miller compensation and significant output capacitance such as LDOs or multistage amplifiers. The pre-charge circuit limits an inrush current right after enabling of the electronic circuit. The pre-charge circuit limits and clamps the fast charging of the Miller capacitor. A delay circuit disables the pre-charge circuit when the bias conditions of the Miller capacitor are close to normal bias conditions.

Description:
TECHNICAL FIELD 
     The present document relates to low drop-out (LDO) voltage regulators. In particular, the present document relates to limiting inrush current from a supply during a start-up phase of an LDO regulator or other electronic circuits with Miller compensation connected to a large size external capacitor. 
     BACKGROUND 
     Inrush currents must be minimized to avoid large voltage drops on the supply that can cause the system to lock or reset. The use of large decoupling capacitors in parallel to the supply can limit the effect of inrush but requires an increased area on printed boards. 
     Other integrated solutions addressing the problem might be less effective when the tolerance of external components and the effects of Process, Voltage and Temperature (PVT) variations come into picture. 
     Therefore it is a challenge for engineers to design LDOs having a limited inrush current in spite of PVT tolerances of components such as an external capacitor. 
     SUMMARY OF THE DISCLOSURE 
     A principal object of the present disclosure is to reduce the inrush current of an LDO connected to a large size output capacitor by limiting and clamping the fast charging of a Miller compensation capacitor. 
     A further object of the disclosure is to pre-charge the Miller capacitor close to the normal bias conditions of the close loop operation of the LDO. 
     A further object of the disclosure is to reduce the inrush current independent of process, voltage, and temperature conditions and variations. 
     A further object of the disclosure is to require very small bias current only at start-up time. 
     A further object of the disclosure is to extend the method disclosed to all multistage amplifiers driving capacitive loads with Miller compensation. 
     A further object of the disclosure is to control in-rush current of an LDO at the very beginning of the start-up phase when neither the control loop nor the internal current limit circuit are in operation. 
     A further object of the invention is to reduce cost and area in the printed board by requiring a smaller decoupling capacitor on the supply to limit voltage drops. 
     In accordance with the objects of this disclosure an electronic circuit configured to reduce inrush current of electronic circuits with a Miller compensation capacitor during a start-up phase only has been disclosed. The circuit achieved comprises the Miller capacitor connected between an output of the circuit and a Miller node of the circuit amplifying an effect of capacitance between the input and output terminals, an input stage of the circuit, a pre-charge circuit configured to pre-charge the Miller capacitor and to clamp a Miller capacitor voltage close to normal operating conditions during a start-up phase only, and a constant current source, generating bias current for the input stage and the pre-charge circuit. 
     In accordance with the objects of this disclosure a method to reduce inrush current of electronic circuits having a Miller compensation capacitor connected to an output, the method has been disclosed. The method achieved comprises the steps of: providing an electronic circuit having an input stage and a pre-charge circuit and a Miller compensation capacitor connected to capacitive load, pre-charging a terminal of the Miller capacitor, which is connected to an input stage of the electronic circuit, to bias conditions close to normal biasing conditions at the very beginning of a start-up phase of the circuit, clamping a terminal of the Miller capacitor to a voltage close to normal biasing conditions, while the electronic circuit is starting up, and disabling the pre-charging and clamping after a defined timespan being long enough to ensure that the biasing of an input stage of the electronic circuit is close to the final biasing conditions. 
    
    
     
       SHORT DESCRIPTION OF THE FIGURES 
       The invention is explained below in an exemplary manner with reference to the accompanying drawings, wherein 
         FIG. 1  illustrates output voltage and supply current of an LDO during start-up. 
         FIG. 2  illustrates a schematic of the proposed LDO circuit. 
         FIG. 3  illustrates a schematic to address the problem of inrush current in phase  1  already by adding a pre-charge circuit. 
         FIG. 4  shows details of the integrated pre-charge circuit for in-rush current control. 
         FIG. 5  depicts simulation results showing time-charts of inrush-current and output voltage of an LDO of the present disclosure under worst case conditions when loaded with 60 μF. 
         FIG. 6  illustrates silicon results showing time-charts of inrush-current and output voltage of an LDO of the present disclosure under typical conditions when loaded with 10 μF. 
         FIG. 7  shows a flowchart of a method to reduce inrush current of electronic circuits having a Miller compensation capacitor connected to capacitive load. 
         FIG. 8 a    illustrates showing time-charts of output currents of a LDO with and without inrush current control. 
         FIG. 8 b    illustrates time-charts of output voltages of a LDO with and without inrush current control. 
         FIG. 9 a    shows maximum peak values of inrush current of an LDO without inrush current control versus output capacitors of 10, 30 and 60 μF shown on the horizontal scale. 
         FIG. 9 b    shows peak values of inrush currents without inrush current control using output capacitors of 10 μF, 30 μF, and 60 μF versus time. 
         FIG. 9 c    shows a time chart of the output voltage using output capacitors of 10 μF, 30 μF, and 60 μF. 
         FIG. 10 a    shows maximum peak values of inrush current of an LDO without inrush current control versus output capacitors of 10, 30 and 60 μF shown on the horizontal scale. 
         FIG. 10 b    shows inrush currents with inrush current control using output capacitors of 10, 30 and 60 μF versus time. 
         FIG. 10 c    shows a time chart of the output voltage. There are only very small differences of the output voltage when using output capacitors of 10, 30 and 60 μF 
     
    
    
     DETAILED DESCRIPTION 
     First, the characteristics of a non-limiting example of an LDO regulator regulated at 3.0 V with 60 μF (before voltage and temperature deteriorating effects) capacitor is presented. 
       FIG. 1  illustrates output voltage and supply current of such an LDO during start-up. It shows the characteristic of the output voltage (VOUT)  10  and inrush current  11  through the output pass device (IOUT) during start-up. 
       FIG. 1  shows are four phases of the start-up:
         T 1 : all internal nodes of the LDO are discharged and biasing up. The output node is charging an external capacitor without control on the output current and a high inrush current  10   a  is possible (as shown in the dashed ellipse), such a high inrush current may be harmful for the circuit and the supply;   T 2 : internal slew rate controlled phase: an internal Miller capacitor starts to charge up while an internal LDO current limit circuit has not yet started to operate;   T 3 : the internal current limit circuit kicks in;   T 4 : the output voltage reaches 90% of the final regulated target value.       

       FIG. 2  illustrates a schematic of an exemplary LDO circuit having an output capacitor connected to a Miller compensation capacitor.  FIG. 2  shows three gain stages with internal Miller compensation. 
       FIG. 2  comprises the components of a basic integrated LDO, namely a pass transistor MPout  24 , a voltage divider (R 0 +R 1 )/(R 0 +R 1 +R 2 ), a feedback node fbk, and a differential pair stage (MP 1 , MP 2  MN 1 , and MN 2 ) controlling the pass transistor MPout and a Miller capacitor Cmiller. Furthermore an external output capacitor Cout is provided. 
     A current limit loop comprises feedback node fbk, nodes vd 1 , vd 2 , vd 3 , and vd 4 , current comparator  21 , transistor MN 3 , and voltage comparator  22 , wherein both comparators are connected to a control circuit  23  comprising transistors MPswrt, MP 4  and MP 3 . The gates of MP 3  and MP 4  are connected to node vd 4 , which is controlling the gate of the power switch MPout. The gate of MPswt is connected to the output of the voltage comparator  22 , which is detecting if the output voltage of the LDO has reached e.g. 90% of the final regulated target voltage. The control circuit  23  provides input to the current comparator  21  which is controlling node vd 3  via transistor MN 3   
     The transistors MP 3  and MP 4  of the control circuit  23  mirror the current lout from the power transistor MPout to the current comparator  21 . The ratio of the current mirroring is: 
                       WMP   ⁢           ⁢   3       LMP   ⁢           ⁢   3       +       WMP   ⁢           ⁢   4       LMP   ⁢           ⁢   4           WMPOUT   LMPOUT       =           W   L     +     W   nL           m   ⁢           ⁢   W     L       =       1   +     1   n       m         ,         
wherein W=channel width, L=channel length, and assuming that all the devices (MP 3 , MP 4 , and MPout) have same channel length and channel width but MPout has more units in parallel (m) and MP 4  has more units in series (n).
 
     At the beginning of the start-up of the LDO of  FIG. 2  the output node (VOUT)  20  is completely discharged, hence the feedback node (fbk)  25  is low. The input differential pair (MP 1 , MP 2 ; MN 1 , MN 2 ), building the 1 st  gain stage, is completely unbalanced (fbk voltage is close to ground voltage and the reference voltage vref is relatively high) and the node vd 2  is low forcing the output vd 3  of the second gain stage A 1  to be high and the output vd 4  of the third gain stage A 2  to be low. The node vd 4  drives directly the gate of the output pass device Mpout, which is connected to the supply voltage VIN. If at start-up the node vd 4  is close to ground, the output pass device MPout is completely turned on with a high gate to source voltage and behaves like a switch and a high inrush current is flowing. 
     It is only when the output vd 2  of the differential pair of the 1 st  stage (MP 1 , MP 2 ; MN 1 , MN 2 ) has reached the same level of biasing to match the opposite branch voltage vd 1  that the second gain stage A 1  and the third gain stage A 2  can take control of the regulation loop that the output current is enabled to start to be limited. 
     Phase T 3  is when the current limit kicks in because the circuit requires to operate a minimum Vout. 
     The voltage at node vd 1  is in the preferred embodiment equivalent of gate-source voltage of device MN 1  (about 0.6 V), i.e. 
     The peak output inrush current during phase T 1  (the time can be defined in design, i.e. 50 μs) is therefore:
 
 I OUT_peak( T 1)= C out× dV/dt;  
 
     this corresponds in the preferred embodiment:
 
 I OUT_peak( T 1)=60 μF×0.6V/50 μs=0.72 A
 
       FIGS. 1 and 2  show that inrush current limitations should be activated in phase  1  already. 
       FIG. 3  illustrates how the problem of inrush current is being addressed in phase  1  already. A pre-charge circuit  30  is activated by an enable LDO signal as soon as the LDO is turned on and will immediately bias node vd 2  close to the voltage of node vd 1 . Pre-charging of the node vd 2  is done through a replica MN 6  of the MN 1  device; hence the circuit can closely track the changes due to PVT variations. A current mode buffer MN 4 , MN 5  has to clamp the voltage at node vd 2  while the LDO is powering up. The pre-charge circuit  30  comprises a current mode buffer  40  comprising transistors MN 4  and MN 5 . The pre-charge circuit  30  will remain in operation for a time long enough to ensure that the biasing of the input differential pair MP 1 , MP 2 , MN 1 , MN 2  is close to the final biasing conditions. In the example of the preferred embodiment the delay circuit  31  is set to approximately 100 μs, which is long enough to cover for the worst case conditions over PVT corners. After this delay, this pre-charge circuit is turned off and the MN 4  device stops providing current; the vd 2  node is regulated now by the control loop of the LDO. Furthermore a miller capacitor Cmiller is connected between the output of the LDO and a Miller node  25 . 
     A further improvement to the method (not shown in  FIG. 3 ) is to attach to node vd 1 , in parallel to device MN 1 , node a dummy replica of the device MN 4  in order to balance the capacitive load between the two branches of the input differential pair MP 1 , MP 2 , MN 1 , and MN 2  Furthermore the current source  32  may be scaled with current Rail provided by current source  33 . 
       FIG. 4  shows details of the integrated pre-charge circuit  30  for in-rush current control as implemented in the exemplary LDO shown in  FIGS. 1 and 2 . As already shown in the circuit of  FIG. 3 ,  FIG. 4  shows the delay circuit  31 , and transistor MN 6 , which is a replica of the MN 1 . The current mode buffer  40  clamps the voltage at the Miller node vd 2  shown in  FIG. 3 . The pre-charge circuit is disabled after a delay signal from the delay block  31  or in other words biasing of the input differential pair is close to final biasing conditions. In a preferred embodiment the pre-charge circuit  30  is disabled after e.g. about 100 μsecs after an enable signal of the LDO or amplifier circuit. 
     Transistor MP 40  is connected in a current mirror configuration to the current source  33  generating bias current ITAIL for the input stage as shown in  FIG. 3 . This current mirror is configured in a way that a current ITAIL/2 is provided by transistor MP 40  to the pre-charge circuit  30 . 
     Transistors MN 5  and MN 4  are identical transistors connected in a current mirror configuration, therefore the same current ITAIL/2 flows through both transistors MN 5  and MN 4 , hence voltage VG 1  has about the same value as voltage vd 1  shown in  FIG. 3 . 
     Current ITAIL is the bias current in the main input differential pair. Under normal conditions each branch (MP 1 +MN 1  and MP 2 +MN 2 ) have a same current ITAIL/2, hence to replicate the vd 1  voltage, ITAIL/2 has to be used. 
     It has to be noted that at start-up point of time the vref pin has a much higher voltage than the fbk pin as the Vout node is charging slowly hence at the very beginning of the start-up there is no current flowing through the MP 2 +MN 2  devices. This way it is easy for the pre-charge circuit  30  to bias the node vd 2  to the target value vd 1 . 
       FIG. 5  depicts worst case, simulation results showing time-charts of inrush-current and output voltage, regulated at 3.0 V, of an LDO with inrush current control of the present disclosure when loaded with 60 μF. The worst case includes temperature of −40 degrees C. The inrush current has a peak of 523 mA.  FIG. 6  illustrates silicon results showing time-charts of inrush-current and output voltage of an LDO, regulated at 2.2 V, of the present invention when loaded with 10 μF. The inrush current has a peak of 130 mA. 
       FIGS. 5 and 6  show both results from 2 versions of the same LDO.  FIG. 5  shows current and voltage diagrams from simulations under worst case conditions, while  FIG. 6  shows silicon results of the LDO under typical conditions. 
       FIG. 7  shows a flowchart of a method to reduce inrush current of electronic circuits having a Miller compensation capacitor connected to capacitive load. A first step  700  depicts a provision of providing an electronic circuit having an input stage and a pre-charge circuit and a Miller compensation capacitor connected to capacitive load. The next step  701  shows pre-charging a terminal of the Miller capacitor, which is connected to an input stage of the electronic circuit, to bias conditions close to normal biasing conditions at the very beginning of a start-up phase of the circuit. Step  702  clamping by the pre-charge circuit the terminal of the Miller capacitor to a voltage close to normal biasing conditions, while the electronic circuit is starting up. Step  703  depicts disabling the pre-charge after a defined timespan being long enough to ensure that the biasing of an input stage of the electronic circuit is close to the final biasing conditions. 
     It should be noted that the method disclosed to pre-charge and clamp the node vd 2  at start-up and consequently reduce the inrush current from the supply voltage VIN is valid in all PVT conditions. 
       FIGS. 8   a+b  illustrate time-charts comprising an LDO with and without inrush current control with a large capacitor (60 μF) when the output is regulated at 3.0 V. The temperature is ambient temperature, the silicon corner is typical. In  FIG. 8 a    curve  80  shows a time diagram of the LDO without inrush current control and the peak on the left hand side of curve  80  shows clearly the problem addressed by the present disclosure. Furthermore in  FIG. 8 a    curve  81  illustrates a current diagram with the inrush current control of the present disclosure. The dramatic improvements by the inrush current control are obvious. Curve  82  shows the rise of the output voltage of the LDO with inrush current control and curve  83  shows the rise of the voltage without inrush current control. It should be noted that the maximum inrush current amounts to about 8 A as shown by curve  80 . 
       FIGS. 9   a - c  illustrate charts of inrush-current versus output capacitances for LDOs without inrush current control.  FIG. 9 a    with curve  90  shows maximum peak values of inrush current of an LDO without inrush current control versus output capacitors of 10, 30 and 60 μF shown on the horizontal scale. The peak value of the inrush-current using e.g. 30 μF is about 7.8 A.  FIG. 9 b    with curves  91 - 93  shows peak values of inrush currents without inrush current control using output capacitors of 10 μF (curve  93 ), 30 μF (curve  92 ), and 60 μF (curve  91 ) versus time. Numeral  91  shows a maximum inrush current when using 60 μF, numeral  92  shows a maximum inrush current when using 30 μF, and numeral  93  shows a maximum inrush current when using 10 μF.  FIG. 9 c    with curve  94  shows a time chart of the output voltage using output capacitors of 10 μF, 30 μF, and 60 μF versus time. There is not much impact of the different capacitors. 
       FIGS. 10   a - c  illustrate charts of inrush-current versus output capacitances for LDOs with inrush current control.  FIG. 10 a    with curve  100  shows maximum peak values of inrush current of an LDO without inrush current control versus output capacitors of 10, 30 and 60 μF shown on the horizontal scale. The peak value of the inrush-current using e.g. 30 μF is 220 mA compared to 7.8 as shown in  FIG. 9 a    without inrush current control.  FIG. 10 b    with curves  101 - 103  shows inrush currents with inrush current control using output capacitors of 10, 30 and 60 μF versus time. Curve  101  shows a maximum inrush current when using 60 μF, curve  102  shows a maximum inrush current when using 30 μF, and curve  103  shows a maximum inrush current when using 10 μF.  FIG. 10 c    with curve  104  shows a time chart of the output voltage. There are only very small differences of the output voltage when using output capacitors of 10, 30 and 60 μF. 
     It should also be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiment outlined in the present document are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the proposed methods and systems. Furthermore, all statements herein providing principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.