Abstract:
An image-pixel signal processor is used to process image-pixel signals obtained from an image-sensing area, divided into a first section and a second section, of a solid-type image sensor. The processor has an image-pixel signal reader, which simultaneously and correspondingly reads two respective series of image-pixel signals line by line from the sections. A leading signal of the image-pixel signals, included in each line, is farthest away from a boundary between the sections, and a trailing signal of the image-pixel signals, included in each line, is nearest to the boundary. The processor has a regulator, which correspondingly regulates differences in level between the signals in each line derived from the first section, and the corresponding signals in each line derived from the second section, so that a gradual reduction occurs, resulting in both levels of the trailing signals, derived from the sections, being substantially coincident with each other.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an image-pixel-signal processor used in, for example, an electronic video camera having a solid-type image sensor, and, in particular, to an image-pixel-signal processor for processing image-pixel signals derived from divided sections of an image-sensing area of a solid-type image sensor. 
     2. Description of the Related Art 
     In an electronic camera, a solid-type image sensor, such as a CCD (charge-coupled device) image sensor, is used to photoelectrically convert an optical objective image into a frame of image-pixel signals. The optical objective image is reproduced based on a video signal generated from the frame of image-pixel signals, which have been subjected to suitable processing. 
     Recently, there has been a demand for the reproduced image to have a higher resolution. A resolution of the reproduced image depends on a number of image-pixel signals included in one frame, which then corresponds to a number of CCD elements included in the CCD image sensor. As is well known, the CCD elements are arranged in a matrix on an image-sensing area or light-receiving area of the CCD image sensor. To obtain a reproduced image with a high resolution, the number of CCD elements must be increased. In this case, the increase in the number of CCD elements is exponential, because of the matrix arrangement of the CCD elements on the image-sensing area of the CCD image sensor. 
     On the other hand, a CCD image sensor, having a large number of CCD elements, produces a detrimental effect on the reading time of a frame of image-pixel signals from the CCD image sensor. To solve this problem, it is proposed that the image-sensing area of the CCD image sensor is vertically and/or horizontally divided into at least two sections; that image-pixel signals are simultaneously read from the divided sections of the image-sensing area; and that the read image-pixels are reintegrated to form a frame of image-pixel signals. Thus, the reading of the image-pixel signals from the CCD image sensor can be carried out in a short time. 
     Nevertheless, a boundary between two adjacent sections of the image-sensing area may be apparent on a reproduced image as a difference of luminous intensity between two image areas, corresponding to the two adjacent sections, of the reproduced image, because an average level of the image-pixel signals, derived from one of the two adjacent sections, may be different from an average level of the image-pixel signals, derived from the other section. 
     In particular, for example, the respective image-pixel signals, read from the two adjacent sections, are successively amplified by two amplifiers. In this case, although the amplifiers used are the same products, it cannot be ensured that the amplifiers exhibit the same amplification characteristic. Accordingly, the respective average levels, derived from the two adjacent sections, may be different from each other, and thus the boundary between the two adjacent sections of the image-sensing area may be apparent on the reproduced image as a difference of luminous intensity between the two image areas. 
     Also, in manufacturing a large-sized CCD image sensor having a large number of CCD elements, at least two small-sized CCD image sensors, each having a small number of CCD elements, are frequently combined with each other to construct the large-sized CCD image sensor. Of course, in this case, image-pixel signals are simultaneously read from the combined small-sized CCD image sensors, and the read image-pixel signals are reintegrated to form a frame of image-pixel signals. Similar to the above-mentioned case, a boundary between two adjacent combined CCD image sensors may be apparent on a reproduced image as a difference of luminous intensity between two image areas, corresponding to the combined small-sized CCD image sensors, of the reproduced image, because of different characteristics between the combined CCD image sensors and different characteristics between amplifiers incorporated into the combined CCD image sensors. 
     SUMMARY OF THE INVENTION 
     Therefore, an object of the present invention is to provide an image-pixel-signal processor for processing image-pixel signals derived from divided sections of an image-sensing area of a solid-type image sensor, wherein a boundary between two adjacent sections of the image-sensing area is not apparent as a difference between luminous intensities on a reproduced image. 
     In accordance with a first aspect of the present invention, there is provided an image-pixel signal processor for processing image-pixel signals obtained from an image-sensing area, divided into a first section and a second section, of a solid-type image sensor. Optionally, the solid-type image sensor may be constructed by combining at least two small-sized solid-type image sensors with each other such that the image-sensing area is formed of a first section and a second section corresponding to image-sensing areas of the small-sized solid-type image sensors, respectively. The processor comprises an image-pixel signal reader, which simultaneously and correspondingly reads two respective series of image-pixel signals line by line from the first and second sections of the image-sensing area. A leading image-pixel signal, of the image-pixel signals included in each line, is farthest away from a boundary between the first and second sections, whereas a trailing image-pixel signal, of the image-pixel signals included in each line, is nearest to the boundary. The processor also comprises a regulator, which correspondingly regulates respective differences between levels of the image-pixel signals in each line derived from the first section, and the corresponding image-pixel signals in each line derived from the second section, so that a gradual reduction occurs, resulting in both levels of the trailing image-pixel signals, derived from the first and second sections, being substantially coincident with each other. 
     In the first aspect of the present invention, the regulator may comprise a first level-changer for changing a level of each image-pixel signal derived from the first section, a second level-changer for changing a level of each image-pixel signal derived from the second section, a first level-detector for detecting a level of the image-pixel signal outputted from the first level-changer, a second level-detector for detecting a level of the image-pixel signal outputted from the second level-changer, a calculator for calculating a differential level between the levels of the image-pixel signals outputted from the first and second level-changers, and a weight-factor multiplier for multiplying the differential level by a weight-factor, which is cyclically varied from a minimum value to a maximum value. The first and second changers correspondingly change the levels of the image-pixel signals, derived from the first and second sections, on the basis of the differential level multiplied by the cyclically-varied weight-factor, such that the regulation of the respective differences between levels of the image-pixel signals in each line derived from the first section, and the corresponding image-pixel signals in each line derived from the second section, is carried out. 
     Also, in the first aspect of the present invention, each of the first and second level-changers may comprise a voltage-controlled amplifier, a magnification factor of which is controlled in accordance with a variation of an inputted control voltage, the control voltage being set on the basis of the differential level multiplied by the cyclically-varied weight-factor. 
     In accordance with a second aspect of the present invention, there is provided an image-pixel signal processor for processing image-pixel signals obtained from an image-sensing area, vertically divided into a first section and a second section, of a solid-type image sensor, wherein a plurality of image-pixel signals is produced in a matrix on each of the first and second sections. Optionally, the solid-type image sensor may be constructed by combining at least two small-sized solid-type image sensors with each other such that the image-sensing area is formed of a first section and a second section corresponding to image-sensing areas of the small-sized solid-type image sensors, respectively, with a vertical boundary being defined between the first and second sections. The processor comprises an image-pixel signal reader, which reads respective series of image-pixel signals, from a leading line of the first and second sections of the image-sensing area, by vertically transferring the image-pixel signals in a line by line succession, and by horizontally transferring a vertically-transferred leading line of the image-pixel signals. A leading image-pixel signal of the image-pixel signals included in each line is farthest from a vertical boundary between the first and second sections, and a trailing image-pixel signal of the image-pixel signals in each line is nearest to the vertical boundary. The processor also comprises a regulator, which correspondingly regulates respective differences between levels of the image-pixel signals in each line derived from the first section, and the corresponding image-pixel signals in each line derived from the second section, so that a gradual reduction occurs, resulting in the levels of the corresponding trailing image-pixel signals, derived from the first and second sections, being substantially coincident with each other. 
     In the second aspect of the present invention, the regulator comprises a first level-changer for changing a level of each image-pixel signal derived from the first section, a second level-changer for changing a level of each image-pixel signal derived from the second section, a first level-detector for detecting a level of the image-pixel signal outputted from the first level-changer, a second level-detector for detecting a level of the image-pixel signal outputted from the second level-changer, a calculator for calculating a differential level between the levels of the image-pixel signals outputted from the first and second level-changers, and a weight-factor multiplier for multiplying the differential level by a weight-factor, the weight-factor being cyclically varied from a minimum value to a maximum value, in accordance with a series of clock pulses, on the basis of which the vertical transfer of the plurality of image-pixel signals is carried out in each of the first and second sections. The first and second changers correspondingly change the levels of the image-pixel signals, derived from the first and second sections, on the basis of the differential level multiplied by the cyclically-varied weight-factor, such that the regulation of the respective differences between levels of the image-pixel signals in each line derived from the first section, and the corresponding image-pixel signals in each line derived from the second section, is carried out. 
     In the second aspect of the present invention, the first and second level-changers may comprise a voltage-controlled amplifier, a magnification factor of which is controlled in accordance with a variation of an inputted control voltage, the inputted control voltage being set on the basis of the differential level multiplied by the cyclically-varied weight-factor. 
     In accordance with a third aspect of the present invention, there is provided an image-pixel signal processor for processing image-pixel signals obtained from an image-sensing area, horizontally divided into a first section and a second section, of a solid-type image sensor, wherein a plurality of image-pixel signals is produced in a matrix on each of the first and second sections. Optionally, the solid-type image sensor may be constructed by combining at least two small-sized solid-type image sensors with each other such that the image-sensing area is formed of a first section and a second section corresponding to image-sensing areas of the small-sized solid-type image sensors, respectively, with a horizontal boundary being defined between the first and second sections. The processor comprises an image-pixel signal reader, which reads respective series of image-pixel signals, from a leading line of the first and second sections of the image-sensing area, by vertically transferring the image-pixel signals in a line by line succession, and by horizontally transferring a vertically-transferred leading line of the image-pixel signals. A leading series of the image-pixel signals, being first to be horizontally transferred from the first and second sections, is farthest from a horizontal boundary between the first and second sections, and a trailing series of the image-pixel signals, being last to be horizontally transferred from the first and second sections, is nearest to the horizontal boundary. The processor also comprises a regulator, which correspondingly regulates respective differences between levels of the image-pixel signals in respective lines derived from the first section, and levels of the image-pixel signals in respective lines derived from the second section, so that a gradual reduction occurs, resulting in the levels of the corresponding trailing-line image-pixel signals, of the first and second sections, being substantially coincident with each other. 
     In accordance with the third aspect of the present invention, the regulator may comprise a first level-changer for changing a level of each image-pixel signal derived from the first section, a second level-changer for changing a level of each image-pixel signal derived from the second section, a first level-detector for detecting a level of the image-pixel signal outputted from the first level-changer, a second level-detector for detecting a level of the image-pixel signal outputted from the second level-changer, a calculator for calculating a differential level between the levels of the image-pixel signals outputted from the first and second level-changers, and a weight-factor multiplier for multiplying the differential level by a weight-factor, the weight-factor being cyclically varied from a minimum value to a maximum value, in accordance with a series of clock pulses, on the basis of which the horizontal transfer of the plurality of image-pixel signals is carried out for each of the first and second sections. The first and second changers correspondingly change the levels of the image-pixel signals, derived from the first and second sections, on the basis of the differential level multiplied by the cyclically-varied weight-factor, such that the regulation of the respective differences between levels of the image-pixel signals in each line derived from the first section, and the corresponding image-pixel signals in each line derived from the second section, is carried out. 
     In the third aspect of the present invention, each of the first and second level-changers may comprise a voltage-controlled amplifier, a magnification factor of which is controlled in accordance with a variation of an inputted control voltage, the control voltage being set on the basis of the differential level multiplied by the cyclically-varied weight-factor. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These objects and other objects of the present invention will be better understood from the following description, with reference to the accompanying drawings, in which: 
     FIG. 1 is a block diagram of an electronic camera having an image-pixel-signal processor according to the present invention; 
     FIG. 2 is a conceptual block diagram of the CCD image sensor shown in FIG. 1; 
     FIG. 3 is an enlargement showing a part of FIG. 2; 
     FIG. 4 is a block diagram of the image-pixel-signal processor, together with the CCD image sensor, the CCD driver circuit and the timing generator circuit shown in FIG. 1; 
     FIG. 5 is a block diagram of a weight-factor controlling circuit shown in FIG. 4; 
     FIG. 6 is a graph showing a characteristic curve of a weight-factor used in the weight-factor multiplier of the image-pixel-signal processor shown in FIG. 5; and 
     FIG. 7 is a block diagram of another weight-factor controlling circuit shown in FIG.  4 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows a block diagram of an electronic camera, in which the present invention is embodied. The electronic camera comprises a photographing optical system  102  which focuses an optical objective-image to be photographed on a CCD (charge-coupled device) image sensor  104 , such that the optical objective image is incident and focused on an image-sensing area or light receiving area of the CCD image sensor  104 . The optical objective image is photoelectrically converted into a frame of image-pixel signals in the CCD image sensor  104 . 
     The frame of image-pixel signals is successively read from the CCD image sensor  104  by a CCD driver circuit  106 , and is then outputted to an image-pixel-signal processor  108 , in which the read image-pixel signals are processed in accordance with the present invention, as stated in detail hereinafter. 
     The electronic camera also comprises a digital image-processing circuit  110 , in which the image-pixel signals, processed in the image-pixel-signal processor  108 , are converted into digital image-pixel signals, and are then subjected to various image processes, such as shading-correction, gamma correction and so on. The processed digital image-pixel signals are outputted from the digital image-processing circuit  110  into an encoder  112 , which produces a video signal on the basis of the processed digital image-pixel signals. The video signal is then fed to an LCD (liquid crystal display) type monitor  114 , on which the photographed image is reproduced and observed. 
     The electronic camera further comprises a system control circuit  116 , which may comprise a microcomputer to control the electronic camera as a whole. For example, the system control circuit  116  controls the reading of the image-pixel signals from the CCD image sensor  104 , through the CCD driver circuit  106 . Also, the system control circuit  116  controls a timing generator circuit  118  for outputting a first series of clock pulses and a second series of clock pulses to both the CCD driver circuit  106  and the image-pixel-signal processor  108 . The reading of the image-pixel signals, from the CCD image sensor  104 , and the processing of the image-pixel signals, in the image-pixel processor  108 , are performed in accordance with the first and second series of clock pulses, outputted from the timing generator circuit  118 , as stated in detail hereinafter. Further, the system control circuit  116  controls the digital image-processing circuit  110 , which performs the various image processes, as mentioned previously. 
     The electronic camera is provided with a recording medium  120 , such as an IC memory card, a floppy disk and so on, and a recording-medium driver circuit  122  for storing the digital image-pixel signals, outputted from the digital image-processing circuit  110 , in the recording medium  120 . The memory-medium driver circuit  122  is controlled by the system control circuit  116 . 
     FIG. 2 conceptually shows an arrangement of the image-sensing area of the CCD image sensor  104 . As shown in this drawing, the image-sensing area of the CCD image sensor  104  is divided into four sections A, B, C and D, and respective boundaries between the sections A, B, C and D are indicated by references A/B, B/C, C/D and D/A. In each of the sections A, B, C and D, a hundred CCD elements, numbered  1  through  100 , are arranged in a 10×10 matrix; so as to form ten vertical CCD element columns having ten respective CCD elements ( 1 ,  11 ,  21 , ˜ 91 ;  2 ,  12 ,  22 , ˜ 92 ;  3 ,  13 ,  23 , ˜ 93 ; . . . ;  10 ,  20 ,  30 ,˜ 100 ), respectively. 
     Note, although, in reality, a CCD image sensor has a greater number of CCD elements, the CCD elements of the CCD image sensor  104  have been restricted to four hundred, for the sake of convenience of explanation. 
     Of course, the CCD image sensor  104  may be constructed by combining four small-sized CCD image sensors, each having a small number of CCD elements, so as to be arranged to form the sections A, B, C and D. For example, when each of the small-sized CCD image sensor has 410,000 CCD elements, a total number of CCD elements of the constructed CCD image sensor  104  is 1,640,000, which is equivalent to an actual size required of the CCD image sensor  104  to enable a sufficiently high resolution image to be produced. 
     Each CCD element includes a photodiode which is arranged so as to form a part of the image-sensing area of the CCD image sensor  104 , with each of the CCD elements storing an electric charge produced by the corresponding photodiode in accordance with an amount of incident light. Namely, when the optical objective image is formed and focused on the image-sensing area of the CCD image sensor  104 , the respective photodiodes produce electric charges, referred to as image-pixel signals, in accordance with a distribution of the light intensity of the optical objective image. Each of the image-pixel signals is thus stored in the corresponding CCD element. 
     Also, in each section A, B, C and D, ten vertical-transfer CCD paths ( 124 A,  124 B,  124 C,  124 D) are arranged adjacent to and alternately with the vertical CCD element columns, being connected to respective horizontal-transfer CCD paths ( 126 A,  126 B,  126 C,  126 D). An output terminal of the horizontal-transfer CCD paths ( 126 A,  126 B,  126 C,  126 D) is connected to an amplifier ( 128 A,  128 B,  128 C,  128 D). 
     At the beginning of the reading of the frame of image-pixel signals from the CCD image sensor  104 , in each of the sections A, B, C and D, the ten image-pixel signals, stored in each CCD element column, are shifted to the corresponding vertical-transfer CCD path ( 124 A,  124 B,  124 C,  124 D) under the control of the CCD driver circuit  106 , as representatively indicated by open arrows in FIG.  3 . 
     Then, the ten image-pixel signals, shifted from each CCD element column, are successively transferred to the corresponding horizontal-transfer CCD path ( 126 A,  126 B,  126 C,  126 D) along each of the ten vertical-transfer CCD paths ( 124 A,  124 B,  124 C,  124 D), included by each section (A, B, C, D), in accordance with the first series of clock pulses, as representatively indicated by curved arrows in FIG.  3 . Namely, whenever one pulse of the first clock pulses is outputted from the timing generator circuit  118  to the CCD driver circuit  106 , the horizontal-transfer CCD paths ( 126 A,  126 B,  126 C,  126 D) obtain a horizontal-line of ten image-pixel signals from the corresponding ten vertical-transfer CCD paths ( 124 A,  124 B,  124 C,  124 D), included in each section (A, B, C,  10  D). 
     The ten image-pixel signals contained in the respective horizontal-transfer CCD paths ( 126 A,  126 B,  126 C,  126 D) are successively transferred to the respective amplifier  128 A,  128 B,  128 C and  128 D, in accordance with the second series of clock pulses outputted from the timing generator circuit  118  to the CCD driver circuit  106 . Thus, the hundred image-pixel signals are successively read from each of the sections A, B, C and D of the CCD image sensor  104 , in ascending numerical order of the numbering of the hundred CCD elements, to the corresponding amplifier ( 128 A,  128 B,  128 C,  128 D). Namely, the four respective sets of the hundred image-pixel signals are simultaneously and correspondingly read in succession from the sections A, B, C and D of the CCD image sensor  104 . 
     Note, of course, in the conceptual example shown in FIGS. 2 and 3, the second series of clock pulses has a frequency ten times that of the first series of clock pulses. 
     With reference to FIG. 4, a relationship between the CCD image sensor  104 , the CCD driver circuit  106 , the image-pixel-signal processor  108  and the timing generator circuit  118  is shown in detail as a block diagram. 
     As shown in FIG. 4, the timing generator circuit  118  includes a vertical-clock-pulse generator  118 V, for outputting the first series of clock pulses, and a horizontal-clock-pulse generator  118 H, for outputting the second series of clock pulses. While the first and second series of clock pulses are outputted from the generators  118 V and  118 H to the CCD driver circuit  106 , a series of horizontal-transfer-command signals and a series of vertical-transfer-command signals are outputted from the CCD driver circuit  106  to the CCD image sensor  104 , in accordance with the first and second series of clock pulses, respectively. 
     Whenever one of the vertical-transfer-command signals is outputted to the CCD image sensor  104 , the successive vertical transfer of the image-pixel signals along the ten respective vertical-transfer CCD paths ( 124 A,  124 B,  124 C,  124 D) is carried out, such that a horizontal-line of ten image-pixel signals is transferred to each horizontal-transfer CCD path ( 126 A,  126 B,  126 C,  126 D). Also, whenever one of the horizontal-transfer-command signals is outputted to the CCD image sensor  104 , the horizontal transfer of the image-pixel signals to the respective amplifier ( 128 A,  128 B,  128 C,  128 D) along the horizontal-transfer CCD path ( 126 A,  126 B,  126 C,  126 D) is performed. 
     As shown in FIG. 4, the image-pixel-signal processor  108  comprises four correlation-double-sampling (CDS) circuits  130 A,  130 B,  130 C and  130 D, which are respectively connected to output terminals of the amplifiers  128 A,  128 B,  128 C and  128 D of the CCD image sensor  104 . While the image-pixel signals, amplified by each of the amplifiers ( 128 A,  128 B,  128 C,  128 D), pass through the corresponding CDS circuit ( 130 A,  130 B,  130 C and  130 D), noise is eliminated from the image-pixel signals. 
     The CDS circuits  130 A,  130 B,  130 C and  130 D are connected, via their output terminals, to four voltage-controlled amplifiers (VCA)  132 A,  132 B,  132 C and  132 D, respectively. Each image-pixel signal, passing through the voltage-controlled amplifiers  132 A,  132 B,  132 C and  132 D, is amplified by an amplification factor, which is varied in accordance with a magnitude of a control voltage inputted to each voltage-controlled amplifier ( 132 A,  132 B,  132 C,  132 D). Namely, as the magnitude of the control voltage increases, the amplification factor also increases. Note, in FIG. 4, the control voltages, inputted to the voltage-controlled amplifiers  132 A,  132 B,  132 C and  132 D, are indicated by references CV a , CV b , CV c  and CV d , respectively. The image-pixel signals, amplified by each voltage-controlled amplifier ( 132 A,  132 B,  132 C,  132 D), are inputted to the digital image-processing circuit  110 . 
     In the digital image-processing circuit  110 , the respective image-pixel signals, derived from the sections A, B, C and D of the CCD image sensor  104 , are converted into digital image-pixel signals, as mentioned above, and are reintegrated to form a frame of image-pixel signals derived from the combined sections A, B, C and D. After the reintegrated digital image-pixel signals have been subjected to the above-mentioned processes, the reintegrated digital image-pixel signals are successively outputted from the digital image-processing circuit  110  to the encoder  112 , in which a video signal is produced on the basis of the processed reintegrated digital image-pixel signals. The video signal is then fed to the LCD-type monitor  114 , on which the photographed image is reproduced and observed. 
     When the photographed image is reproduced on the LCD-type monitor  114 , each of the boundaries A/B, B/C, C/D and D/A may appear on the reproduced image, due to a difference of luminous intensity between two image areas of the reproduced image, corresponding to two adjacent sections (A and B; B and C; C and D; and D and A), because an average level of the image-pixel signals, derived from one of the two adjacent sections, may be different from an average level of the image-pixel signals, derived from the other section. 
     As discussed hereinbefore, although the amplifiers  128 A,  128 B,  128 C and  128 D of the CCD image sensor  104  are identical products, each of these amplifiers cannot have precisely identical amplification characteristics. Similarly, with respect to each of the CDS circuits  130 A,  130 B,  130 C and  130 D, precisely identical characteristics cannot exist. Also, when the CCD image sensor  104  is constructed by combining the small-sized CCD image sensors with each other, each of the small-sized CCD image sensors cannot have precisely identical characteristics. Accordingly, for example, an average level of the image-pixel signals, derived from section A, is different to an average level of the image-pixel signals, derived from section B, resulting in the appearance of the boundary A/B between the sections A and B on the reproduced image. 
     Nevertheless, according to the present invention, it is possible to eliminate the appearance of the boundaries A/B, B/C, C/D and D/A from the reproduced image by suitably regulating the respective control voltages CV a , CV b , CV c  and CV d  to be applied to the voltage-controlled amplifiers  132 A,  132 B,  132 C and  132 D. 
     In order to regulate the control voltage CV a , the image-pixel-signal processor  108  is provided with a signal-level detector (DET)  134 A, a subtractor  136 A and a subtractor  138 A, and these elements are arranged as shown in FIG.  4 . 
     In order to regulate the control voltage CV b , the image-pixel-signal processor  108  is provided with a signal-level detector (DET)  134 B, an adder  136 B and an adder  138 B, these elements being arranged as shown in FIG.  4 . 
     In order to regulate the control voltage CV c , the image-pixel-signal processor  108  is provided with a signal-level detector (DET)  134 C, a subtractor  136 C and an adder  138 C, these elements being arranged as shown in FIG.  4 . 
     In order to regulate the control voltage CV d , the image-pixel-signal processor  108  is provided with a signal-level detector (DET)  134 D, an adder  136 D and a subtractor  138 D, these elements being arranged as shown in FIG.  4 . 
     Further, in order to correlatively regulate the control voltages CV a , CV b , CV c  and CV d , the image-pixel-signal processor  108  is provided with four differential amplifiers (DA)  140 A/B,  140 D/A,  140 B/C and  140 C/D, and four weight-factor controlling circuits (WFC)  142 A/B,  142 D/A,  142 B/C and  142 C/D, and these elements are arranged as in FIG.  4 . 
     The detector  134 A detects a voltage level of each of the image-pixel signals, derived from section A of the CCD image sensor  104 , and outputs a voltage VL a  representing the detected voltage level; the detector  134 B detects a voltage level of the image-pixel signals, derived from section B of the CCD image sensor  104 , and outputs a voltage VL b  representing the detected voltage level; the detector  134 C detects a voltage level of the image-pixel signals, derived from section C of the CCD image sensor  104 , and outputs a voltage VL c  representing the detected voltage level; and the detector  134 D detects a voltage level of the image-pixel signals, derived from section D of the CCD image sensor  104 , and outputs a voltage VL d  representing the detected voltage level. 
     Each of the detectors  134 A,  134 B,  134 C and  134 D includes an integration circuit such that each of the detected voltages (VL a , VL b , VL c  and VL d ) of the respective corresponding image-pixel signals, detected by each detector ( 134 A,  134 B,  134 C,  134 D), is outputted as one value representing an averaged voltage level. Consequently, a high frequency noise component is eliminated from the detected voltage (VL a , VL b , VL c , VL d ) by the integration circuit. 
     The detector  134 A has an output terminal connected to a non-inverting input terminal of the differential amplifier  140 A/B and a non-inverting input terminal of the differential amplifier  140 D/A. Namely, the detected voltage VL a  is inputted to each of the differential amplifiers  140 A/B and  140 D/A through the non-inverting input terminal thereof. 
     The detector  134 B has an output terminal connected to an inverting input terminal of the differential amplifier  140 A/B and an inverting input terminal of the differential amplifier  140 B/C. Namely, the detected voltage VL b  is inputted to each of the differential amplifiers  140 A/B and  140 B/C through the inverting input terminal thereof. 
     The detector  134 C has an output terminal connected to a non-inverting input terminal of the differential amplifier  140 B/C and an inverting input terminal of the differential amplifier  140 C/D. Namely, the detected voltage VL c  is inputted to the differential amplifier  140 B/C through the non-inverting input terminal thereof, and is simultaneously inputted to the differential amplifier  140 C/D through the inverting input terminal thereof. 
     The detector  134 D has an output terminal connected to an inverting input terminal of the differential amplifier  140 D/A and a non-inverting input terminal of the differential amplifier  140 C/D. Namely, the detected voltage VL d  is inputted to the differential amplifier  140 D/A through the inverting input terminal thereof, and is simultaneously inputted to the differential amplifier  140 C/D through the non-inverting input terminal thereof. 
     The differential amplifier  140 A/B outputs a differential voltage ΔV A/B , generated from the detected voltages VL a  and VL b , to the weight-factor controlling circuit  142 A/B. The differential voltage ΔV A/B  represents a differential signal-level between an image-pixel signal derived from section A and a corresponding image-pixel signal derived from section B. In this case, if the detected voltage VL a  is larger than the detected voltage VL b , the differential voltage ΔV A/B  is positive, and, if the detected voltage VL a  is smaller than the detected voltage VL b , the differential voltage ΔV A/B  is negative. 
     The differential amplifier  140 D/A outputs a differential voltage ΔV D/A , generated from the detected voltages VL d  and VL a , to the weight-factor controlling circuit  142 D/A. The differential voltage ΔV D/A  represents a differential signal-level between an image-pixel signal derived from section D and a corresponding image-pixel signal derived from section A. In this case, if the detected voltage VL d  is smaller than the detected voltage VL a , the differential voltage ΔV D/A  is positive, and, if the detected voltage VL d  is larger than the detected voltage VL a , the differential voltage ΔV D/A  is negative. 
     The differential amplifier  140 B/C outputs a differential voltage ΔV B/C , generated from the detected voltages VL b  and VL c , to the weight-factor controlling circuit  142 B/C. The differential voltage ΔV B/C  represents a differential signal-level between an image-pixel signal derived from section B and a corresponding image-pixel signal derived from section C. In this case, if the detected voltage VL b  is smaller than the detected voltage VL c , the differential voltage ΔV B/C  is positive, and, if the detected voltage VL b  is larger than the detected voltage VL c , the differential voltage ΔV B/C  is negative. 
     The differential amplifier  140 C/D outputs a differential voltage ΔV C/D , generated from the detected voltages VL c  and VL d , to the weight-factor controlling circuit  142 C/D. The differential voltage ΔV C/D  represents a differential signal-level between an image-pixel signal derived from section C and a corresponding image-pixel signal derived from section D. In this case, if the detected voltage VL c  is smaller than the detected voltage VL d , the differential voltage ΔV C/D  is positive, and, if the detected voltage VL c  is larger than the detected voltage VL d , the differential voltage ΔV C/D  is negative. 
     As shown in FIG. 5, the weight-factor controlling circuit, indicated by references  142 A/B and  142 C/D, includes a multiplier  144 H, a weight-factor outputter  146 H and a counter  148 H. The differential voltage (ΔV A/B , ΔV C/D ) is inputted to the multiplier  144 H, and is multiplied by a weight-factor or multiplying factor (W A/B , W C/D ), which is outputted as a voltage signal from the weight-factor outputter  146 H to the multiplier  144 H. The voltage signal (W A/B , W C/D ), representing the weight-factor, is cyclically varied by the counter  148 H. 
     Specifically, the counter  148 H counts a number of the second clock pulses outputted from the horizontal-clock-pulse generator  118 H of the timing generator circuit  118 , and is reset to zero whenever it counts ten clock pulses. Also, whenever the counter number of the counter  148 H is incremented by “1”, the counter  148 H outputs a weight-factor-outputting-command signal to the weight-factor outputter  146 H. Whenever the weight-factor-outputting-command signal is outputted to the weight-factor outputter  146 H during the counting of the ten clock pulses by the counter  148 H, the weight-factor, i.e. the voltage signal (W A/B , W C/D ), outputted from the weight-factor-outputter  146 H to the multiplier  144 H, is gradually increased in accordance with a characteristic curve, as shown in FIG.  6 . As is apparent from this graph, when the number of the counter  148 H is one, the weight-factor (W A/B , W C/D ) is zero, and, when the number of the counter  148 H is ten, the weight-factor (W A/B , W C/D ) one. 
     Namely, for example, the ten respective differential voltages ΔV A/B , derived from both the ten detected voltages VL a , generated from a horizontal-line of the CCD elements in section A, and the ten detected voltages VL b , generated from a corresponding horizontal-line of the CCD elements in section B, are multiplied by the weight-factors W A/B , which are gradually incremented in accordance with the characteristic curve of FIG.  6 . Similarly, this is true for the ten respective differential voltages ΔV C/D , derived from both the ten detected voltages VL c , generated from a horizontal-line of the CCD elements in section C, and the ten detected voltages VL d , generated from a corresponding horizontal-line of the CCD elements in section D. In short, each of the above-mentioned ten differential voltages ΔV C/D , multiplied by the varying weight-factors W C/D , is outputted as a weighted voltage WV C/D  from the multiplier  144 H. 
     As shown in FIG. 7, the weight-factor controlling circuit, indicated by references  142 D/A and  142 B/C, includes a multiplier  144 V, a weight-factor outputter  146 V and a counter  148 V. The differential voltage (ΔV D/A , ΔV B/C ) is inputted to the multiplier  144 V, and is multiplied by a weight-factor or multiplying factor (W D/A , W B/C ), which is outputted as a voltage signal from the weight-factor outputter  146 V to the multiplier  144 V. The voltage signal (W D/A , W B/C ), representing the weight-factor, is cyclically varied by the counter  148 V. 
     Specifically, the counter  148 V counts a number of the first clock pulses outputted from the vertical-clock-pulse generator  118 V of the timing generator circuit  118 , and is reset to zero whenever it counts ten clock pulses. Also, whenever the counter number of the counter  148 V is incremented by “1”, the counter  148 V outputs a weight-factor-outputting-command signal to the weight-factor outputter  146 V. Whenever the weight-factor-outputting-command signal is outputted to the weight-factor outputter  146 V during the counting of the ten clock pulses by the counter  148 V, the weight-factor, i.e. the voltage signal (W D/A , W B/C ), outputted from the weight-factor-outputter  146 V to the multiplier  144 V, is gradually increased in accordance with the characteristic curve shown in FIG.  6 . Of course, when the number of the counter  148 V is one, the weight-factor (W D/A , W B/C ) is zero, and, when the number of the counter  148 V is ten, the weight-factor (W D/A , W B/C ) is one. 
     Namely, for example, the ten respective differential voltages ΔV D/A , derived from both the ten detected voltages VL d , generated from a horizontal-line of the CCD elements in section D, and the ten detected voltages VL a , generated from a corresponding horizontal-line of the CCD elements in section A, are multiplied by an identical weight-factor W D/A  determined by a counter number of the counter  148 V, due to the frequency of the first clock pulses being one-tenth of the second clock pulses outputted from the horizontal-clock-pulse generator  118 H. The weight-factor is gradually incremented, whenever the multiplication of the above-mentioned ten differential voltages ΔV D/A  by the weight-factor W D/A  is performed. Similarly, this is true for the ten respective differential voltages ΔV B/C , derived from both the ten detected voltages VL b , generated from a horizontal-line in the section B, and the ten detected voltages VL c , generated from a corresponding horizontal-line of the CCD elements in section C. In short, each of the differential voltages ΔV B/C , multiplied by the weight-factor W B/C , is outputted as a weighted voltage WV B/C  from the multiplier  144 V. 
     As is apparent from FIG. 4, the weighted voltage WV A/B , outputted from the weight-factor controlling circuit  142 A/B, is inputted to the subtractor  138 A and the adder  138 B, and the weighted voltage WV C/D , outputted from the weight-factor controlling circuit  142 C/D, is inputted to the adder  138 C and the subtractor  138 D. Also, the weighted voltage WV D/A , outputted from the weight-factor controlling circuit  142 D/A, is inputted to the adder  136 D and the subtractor  136 A, and the weighted voltage WV B/C , outputted from the weight-factor controlling circuit  142 B/C, is inputted to the adder  136 B and the subtractor  136 C. 
     With the arrangement as mentioned, the control voltages CV a , CV b , CV c  and CV d  to be applied to the voltage-controlled amplifiers  132 A,  132 B,  132 C and  132 D, respectively, are suitably regulated, so that the appearance of the boundaries A/B, B/C, C/D and D/A can be eliminated from the reproduced image. 
     For example, as shown in FIG. 4, when the voltage VL a , detected by the detector  134 A, is outputted to the differential amplifier  140 D/A, the voltage VL a  is simultaneously outputted to the subtractor  136 A. Therefore, in the subtractor  136 A, the corresponding weighted voltage WV D/A , outputted from the weight-factor controlling circuit  142 D/A, is subtracted from the voltage VL a . On the other hand, when the voltage VL d , detected by the detector  134 D, is outputted to the differential amplifier  140 D/A, the voltage VL d  is simultaneously outputted to the adder  136 D. Therefore, in the adder  136 D, the corresponding weighted voltage WV D/A , outputted from the weight-factor controlling circuit  142 D/A, is added to the voltage VL d . 
     If VL a &gt;VL d , the weighted voltage WV D/A , outputted from the weight-factor controlling circuit  142 D/A, is positive. Accordingly, the level of the voltage VL a  is decreased due to the inputting of the positive weighted voltage WV D/A  to the subtractor  136 A, whereas the level of the voltage VL d  is correspondingly increased due to the inputting of the positive weighted voltage WV D/A  to the adder  136 D. The decreased voltage VL a  is inputted as the control voltage CV a  to the voltage-controlled amplifier  132 A, and thus the magnification factor of the voltage-controlled amplifier  132 A is lowered, whereby a level of the image-pixel signal becomes smaller. On the other hand, the increased voltage VL d  is inputted as the control voltage CV d  to the voltage-controlled amplifier  132 D, and thus the magnification factor of the voltage-controlled amplifier  132 D is raised, whereby a level of the image-pixel signal becomes larger. 
     On the contrary, if VL a &lt;VL d , the weighted voltage WV D/A , outputted from the weight-factor controlling circuit  142 D/A, is negative. Accordingly, the level of the detected voltage VL a  is increased due to the inputting of the negative weighted voltage WV D/A  to the subtractor  136 A, whereas the level of the voltage VL d  is correspondingly decreased due to the inputting of the negative weighted voltage WV D/A  to the adder  136 D. The increased voltage VL a  is inputted as the control voltage CV a  to the voltage-controlled amplifier  132 A, and thus the magnification factor of the voltage-controlled amplifier  132 A is raised, whereby a level of the image-pixel signal becomes larger. On the other hand, the decreased voltage VL d  is inputted as the control voltage CV d  to the voltage-controlled amplifier  132 D, and thus the magnification factor of the voltage-controlled amplifier  132 D is lowered, whereby a level of the image-pixel signal becomes smaller. 
     Nevertheless, the regulation of the control voltages CV a  and CV d  is substantially equivalent with respect to both the ten image-pixel signals, included in a horizontal-line of the CCD elements in section A, and the ten image-pixel signals, included in a corresponding horizontal-line of the CCD elements is section D, because the generated ten differential voltages ΔV D/A , as described previously, are multiplied by identical weight-factors. 
     More significantly, the regulation of the control voltages CV a  and CV d  becomes increasingly critical as the weight-factor approches one. Namely, a difference in level between an image-pixel signal, derived from section A, and a corresponding image-pixel signal, derived from section D, approches zero, as both the image-pixel signals near the boundary D/A between the sections D and A. Thus, a difference in level between the ten image-pixel signals, derived from the CCD elements numbered  91 ,  92 ,  93 , ˜,  98 ,  99  and  100  in section D, and the ten image-pixel signals, derived from the CCD elements numbered  91 ,  92 ,  93 , ˜,  98 ,  99  and  100  in section A, substantially becomes zero, because the regulation of the control voltages CV a  and CV d  is performed with a weighted voltage WV D/A  derived from a weight-factor of “1”. Namely, the boundary D/A between the sections D and A cannot appear on the reproduced image. 
     In short, the respective control voltages CV a  and CV d  can be represented by the following formulas:                CV   a     =       VL   a     -       W     D   /   A       *   Δ                   V     D   /   A                       =       VL   a     -       W     D   /   A            (       VL   a     -     VL   d       )                     =         (     1   -     W     D   /   A         )          VL   a       +       W     D   /   A       *     VL   d                               CV   d     =       VL   d     +       W     D   /   A       *   Δ                   V     D   /   A                       =       Vl   a     +       W     D   /   A            (       VL   a     -     VL   d       )                     =         (     1   -     W     D   /   A         )          VL   d       +       W     D   /   A       *     VL   d                                      
     Herein: 0≦W D/A ≦1 
     Of course, this is also true for a relationship between the image-pixel signals in section B and the image-pixel signals in section C. Namely, the respective control voltages CV b  and CV c  can be represented by the following formulas:                CV   b     =       VL   b     +       W     B   /   C       *   Δ                   V     B   /   C                       =       VL   b     +       W     B   /   C            (       VL   c     -     VL   b       )                     =         (     1   -     W     B   /   C         )          VL   b       +       W     B   /   C       *     VL   c                               CV   c     =       VL   c     -       W     B   /   C       *   Δ                   V     B   /   C                       =       Vl   c     -       W     B   /   C            (       VL   c     -     VL   b       )                     =         (     1   -     W     B   /   C         )          VL   c       +       W     B   /   C       *     VL   b                                      
     Herein: 0≦W B/C ≦1 
     Also, as shown in FIG. 4, when the voltage VL a  detected by the detector  134 A, is outputted to the differential amplifier  140 A/B, the voltage VL a  is simultaneously outputted to the subtractor  138 A. Therefore, in the subtractor  138 A, the corresponding weighted voltage WV A/B , outputted from the weight-factor controlling circuit  142 A/B, is subtracted from the voltage VL a . On the other hand, when the voltage VL b , detected by the detector  134 B, is outputted to the differential amplifier  140 A/B, the voltage VL b  is simultaneously outputted to the adder  138 B. Therefore, in the adder  138 B, the corresponding weighted voltage WV A/B , outputted from the weight-factor controlling circuit  142 A/B, is added to the voltage VL b . 
     If VL a &gt;VL b , the weighted voltage WV A/B , outputted from the weight-factor controlling circuit  142 A/B, is positive. Accordingly, the level of the voltage VL a  is decreased due to the inputting of the positive weighted voltage WV A/B  to the subtractor  138 A, whereas the level of the voltage VL b  is correspondingly increased due to the inputting of the positive weighted voltage WV A/B  to the adder  138 B. The decreased voltage VL a  is inputted as the control voltage CV a  to the voltage-controlled amplifier  132 A, and thus the magnification factor of the voltage-controlled amplifier  132 A is lowered, whereby a level of the image-pixel signal becomes smaller. On the other hand, the increased voltage VL b  is inputted as the control voltage CV b  to the voltage-controlled amplifier  132 B, and thus the magnification factor of the voltage-controlled amplifier  132 B is raised, whereby a level of the image-pixel signal becomes larger. 
     On the contrary, if VL a &lt;VL b , the weighted voltage WV A/B , outputted from the weight-factor controlling circuit  142 A/B, is negative. Accordingly, the level of the detected voltage VL a  is increased due to the inputting of the negative weighted voltage WV A/B  to the subtractor  138 A, whereas the level of the voltage VL b  is correspondingly decreased due to the inputting of the negative weighted voltage WV A/B  to the adder  138 B. The increased voltage VL a  is inputted as the control voltage CV a  to the voltage-controlled amplifier  132 A, and thus the magnification factor of the voltage-controlled amplifier  132 A is raised, whereby a level of the image-pixel signal becomes larger. On the other hand, the decreased voltage VL b  is inputted as the control voltage CV b  to the voltage-controlled amplifier  132 B, and thus the magnification factor of the voltage-controlled amplifier  132 D is lowered, whereby a level of the image-pixel signal becomes smaller. 
     Accordingly, a difference in level between an image-pixel signal, derived from section A, and a corresponding image-pixel signal, derived from section B, approaches zero, as both the image-pixel signals near the boundary A/B between the sections A and B. Thus, a difference in level between the ten image-pixel signals, derived from the CCD elements numbered  10 ,  20 ,  30 ,˜,  80 ,  90  and  100  in section A, and the ten image-pixel signals, derived from the CCD elements numbered  10 ,  20 ,  30 ,˜,  80 ,  90  and  100  in section B, substantially becomes zero, because the regulation of the control voltages CV a  and CV b  is performed with a weighted voltage WV A/B  derived from a weight-factor of “1”. Namely, the boundary A/B between the sections A and B cannot appear on the reproduced image. 
     In short, the respective control voltages CV a  and CV b  can be represented by the following formulas:                CV   a     =       VL   a     -       W     A   /   B       *   Δ                   V     A   /   B                       =       VL   a     -       W     A   /   B            (       VL   a     -     VL   b       )                     =         (     1   -     W     A   /   B         )          VL   a       +       W     D   /   A       *     VL   b                               CV   b     =       VL   b     +       W     A   /   B       *   Δ                   V     A   /   B                       =       VL   b     +       W     A   /   B            (       VL   a     -     VL   b       )                     =         (     1   -     W     A   /   B         )          VL   b       +       W     A   /   B       *     VL   a                                      
     Herein: 0≦W A/B ≦1 
     Of course, this is also true for a relationship between the image-pixel signals in section C and the image-pixel signals in section D. Namely, the respective control voltages CV c  and CV d  can be represented by the following formulas:                CV   c     =       VL   c     +       W     C   /   D       *   Δ                   V     C   /   B                       =       VL   c     +       W     C   /   D            (       VL   d     -     VL   C       )                     =         (     1   -     W     C   /   D         )          VL   c       +       W     C   /   D       *     VL   d                               CV   d     =       VL   d     -       W     C   /   D       *   Δ                   V     C   /   D                       =       VL   d     -       W     C   /   D            (       VL   d     -     VL   c       )                     =         (     1   -     W     C   /   D         )          VL   d       +       W     C   /   D       *     VL   c                                      
     Herein: 0≦W C/D ≦1 
     Finally, it will be understood by those skilled in the art that the foregoing description is of preferred embodiments of the device, and that various changes and modifications may be made to the present invention without departing from the spirit and scope thereof. 
     The present disclosure relates to subject matter contained in Japanese Patent Application No. 9-102750 (filed on Apr. 4, 1997) which is expressly incorporated herein, by reference, in its entirety.