Abstract:
A first plurality of clock signals including a first clock signal and a second clock signal is received, the first and second clock signal out of phase with each other. A second plurality of clock signals comprising a third clock signal and a fourth clock signal is received, the third and fourth clock signals out of phase with each other. A plurality of enable signals are received. A fifth clock signal is determined based on the first plurality of clock signals and the plurality of enable signals. A sixth clock signal is determined based on the second plurality of clock signals and the plurality of enable signals. A seventh clock signal is determined based on the fifth clock signal and the sixth clock signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is related to co-pending U.S. patent application Ser. No. 11/750,267, entitled “TECHNIQUES FOR INTEGRATED CIRCUIT CLOCK MANAGEMENT” filed on May 17, 2007, U.S. patent application Ser. No. 11/750,284, entitled “TECHNIQUES FOR INTEGRATED CIRCUIT CLOCK MANAGEMENT USING PULSE SKIPPING” filed on May 17, 2007, U.S. patent application Ser. No. 11/750,290, entitled “TECHNIQUES FOR INTEGRATED CIRCUIT CLOCK MANAGEMENT USING MULTIPLE CLOCK GENERATORS” filed on May 17, 2007, and U.S. patent application Ser. No. 11/750,275, entitled “TECHNIQUES FOR INTEGRATED CIRCUIT CLOCK SIGNAL MANIPULATION TO FACILITATE FUNCTIONAL AND SPEED TEST” filed on May 17, 2007, the entirety of which is incorporated by reference herein. 
     BACKGROUND 
     1. Field of the Disclosure 
     The present disclosure is generally directed to clock management and, and more particularly to clock management at an integrated circuit. 
     2. Description of the Related Art 
     A data processing device, such as an integrated circuit microprocessor device, can include a large number of data subsystems fabricated at a single semiconductor die. For example, a microprocessor device can include a memory interface subsystem and a graphics acceleration subsystem in addition to a central processing unit. Each data subsystem can operate as a data processor and can include disparate operating frequency limitations. Therefore, the computational performance of the microprocessor device is typically improved if each data subsystem is configured to operate at a respective frequency that can be different from that of another data subsystem. Furthermore, it can be advantageous if the operating frequency of a particular data subsystem can be changed efficiently while the data subsystem continues to operate. For example, the microprocessor can transition a data subsystem between a typical power operating mode and a low-power operating mode by altering the frequency of a clock signal provided to that data subsystem. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. 
         FIG. 1  illustrates in block diagram form a data processing device including a digital frequency synthesizer in accordance with a specific embodiment of the present disclosure. 
         FIG. 2  is a timing diagram illustrating the operation of a clock delay module and clock pulse module of  FIG. 1  in accordance with a specific embodiment of the present disclosure. 
         FIG. 3  illustrates in schematic form a portion of the DFS of  FIG. 1  including the clock pulse module and clock generator module in accordance with a specific embodiment of the present disclosure. 
         FIG. 4  is a timing diagram illustrating the operation of the clock pulse module and a clock generator module of  FIG. 1  in accordance with a specific embodiment of the present disclosure. 
         FIG. 5  is a flow diagram illustrating a method in accordance with a specific embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     A digital frequency synthesizer (DFS) is disclosed that is operable to provide an output clock signal, wherein the frequency of the output clock signal is a fractional multiple of the frequency of an input reference clock signal. The fractional multiple (divisor) can be adjusted, and the DFS can be configured to provide an output clock waveform with a substantially balanced duty cycle. By replicating portions of the DFS, multiple clock signals can be provided wherein the frequency of each clock signal can be individually determined and wherein each clock signal has a known phase relationship. The known phase relationship between the generated clocks allows for low-latency and deterministic exchange of data information between data subsystems operating at different clock frequencies. 
       FIG. 1  illustrates in block diagram form a data processing device  100  including a DFS in accordance with a specific embodiment of the present disclosure. Data processing device  100  includes a DFS  110 , a DFS  112 , a data subsystem  150 , and a data subsystem  152 . DFS  110  includes a clock delay module  1102 , a clock pulse module  1104 , and a clock generator module  1106 . Clock delay module  1102  has an input to receive a clock signal labeled “CLK,” and an output. Clock pulse module  1102  has an input connected to the output of clock delay module  1102 , and an output. Clock generator module  1106  has an input connected to the output of clock pulse module  1104 , an input connected to the output of clock delay module  1102 , an input to receive a signal labeled “ENAB(0:4),” and an output to provide a clock signal labeled “DFS CLOCK.” DFS  112  is operable to provide a second clock signal labeled “DFS 2  CLOCK.” A clock generator (not shown) included at DFS  112  is configured by a second enable signal labeled “ENAB 2 (0:4). 
     Clock delay module  1102  is configured to provide multiple delayed clock signals. For example, eight delayed clock signals can be provided, wherein each of the eight delayed clock signals represents the clock signal CLK delayed by a particular phase angle. The eight phase delays provided by clock delay module  1102  include 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°, respectively. Clock delay module  110  can include a delay-locked-loop (DLL), not shown, that includes eight substantially equivalent delay elements connected in series and provided to a phase detector along with clock signal CLK. Thus, while the DLL is in a condition of lock with respect to clock signal CLK, the output of each respective delay element provides a corresponding one of the eight delayed clock signals. Therefore, each of the eight delayed clock signals provided by clock delay module  110  maintain their phase relationship relative to each other, even as the frequency of clock signal CLK is changed. In another embodiment, the delay locked loop included at clock delay module  110  is integral with a primary voltage-controlled phase locked loop (PLL) that provides clock signal CLK. 
     Clock pulse module  1104  is configured to receive the eight delayed clock signals from clock delay module  1102  and provide eight corresponding clock pulse signals. Each clock pulse signal transitions to a logic-high level substantially coincident with the logic-high transition of its corresponding delayed clock signal, and transitions back to a logic-low level before the logic-low transition of the corresponding delayed clock signal. The logic-high level of each clock pulse signal is maintained for a duration corresponding to 90° (Π/2 radians). Each clock pulse can be the result of a logical AND of two delayed clock signals. For example, the logical AND of the 0° delayed clock and the 270° delayed clock provides a clock pulse that transitions to a logic-high level at 0° and returns to a logic-low level at 90°. In another embodiment, clock delay module  1102  can provide a greater or a fewer number of delayed clock signals to clock pulse module  1104 . For example, clock delay module  1102  can include ten delay elements and thus provide ten delayed clock signals to clock pulse module  1104 , corresponding to phase delays of 0°, 36°, 72°, 108°, 144°, 180°, 216°, 252°, 288°, and 324°. Clock pulse module  1104  would thus provide ten corresponding clock pulse signals to clock generator module  1106 , wherein the duration of each pulse is 72°. The operation of clock delay module  1102  and clock pulse module  1104  is further described with reference to the timing diagram at  FIG. 2 . 
     Clock generator module  1106  is configured to selectively combine the clock pulses provided by clock pulse module  1106  to generate clock signal DFS CLOCK at the output of the DFS module  110  in response to enable signals ENAB(0:4). The frequency of signal DFS CLOCK can be adjusted to represent input clock signal CLK divided by a factor of between one and 7.75 by configuring signal ENAB(0:3) appropriately. In particular, the frequency of clock signal DFS CLOCK=the frequency of input clock signal CLK divided by N/4, where N is an integer that can range from 4 to 63. Thus, the frequency of clock signal DFS CLOCK can be configured to be equal to the frequency of input clock CLK divided by one of 1, 1.25, 1.5, 1.75, 2.0, 2.25, 2.5, 2.75, 3.0, 3.25, 3.5, 3.75 . . . 7.75. Furthermore, the duty cycle of clock signal DFS CLOCK can be configured to be substantially fifty percent for each clock divisor. 
     Signal ENAB(0:3) is configured to provide a sequence of four-bit data values that determines the frequency of clock signal DFS CLOCK. The data value provided by signal ENAB(0:3) is maintained for one cycle of clock signal CLK, and then a new data value can be provided. Signal ENAB( 4 ) is asserted to configure the duty cycle of clock signal DFS CLOCK to substantially fifty percent when the desired clock divisor is not evenly divisible by decimal 0.5. For example, signal ENAB( 4 ) is asserted when a divisor of 1.25, 1.75, 2.25 . . . 7.75 is desired, and negated when a divisor of 1.0, 1.5, 2.0 . . . 7.5 is desired. 
     Data subsystem  150  and data subsystem  152  each include one or more data processing modules (not shown). Each data processing module included at data subsystem  150  is included within a common clock domain, and each data processing module included at data subsystem  152  shares another clock domain. A clock domain is a particular clock frequency shared by a group of data processing modules. Data processing device  100  can include multiple data subsystems and each respective data subsystem can be associated with a corresponding clock domain. DFS  110 , or a portion of DFS  110  can be replicated to provide a desired clock signal for each clock domain. Each DFS can be individually configured to provide a preferred output clock frequency using a corresponding sequence of enable values. In one embodiment, two clock generators can share clock delay module  1102  and clock pulse module  1104  to provide two output clock signals to two data subsystems. For example, DFS  112  can include the same modules as DFS  110 , or it may share the clock delay module, the clock pulse module, or both, with DFS  110 . Each additional DFS, such as DFS  112 , includes a clock generator module (not shown). 
       FIG. 2  is a timing diagram  200  illustrating the operation of a clock delay module  1102  and clock pulse module  1104  of  FIG. 1  in accordance with a specific embodiment of the present disclosure. Timing diagram  200  includes a horizontal axis representing time and a vertical axis representing voltage in units of volts. Timing diagram  200  includes a waveform  210  representing input clock signal CLK, waveforms  220 ,  221 ,  222 ,  223 ,  224 ,  225 ,  226 , and  227  representing delayed clock signals labeled “C 0 ,” “C 45 ,” “C 90 ,” “C 135 ,” “C 180 ,” “C 225 ,” “C 270 ,” and “C 315 ,” respectively. Timing diagram  200  also includes waveforms  230 ,  232 ,  234 ,  236 ,  238 ,  240 ,  242 , and  244  representing clock pulses labeled “P 0 ,” “P 45 ,” “P 90 ,” “P 135 ,” “P 80 ,” “P 225 ,” “P 270 ,” and “P 315 ,” respectively. 
     Each of delayed clock signals C 0 -C 315  represent input clock signal CLK delayed by 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°, respectively. Each of clock pulses P 0 -P 315  represents the logical AND of a pair of delayed clock signals C 0 -C 315 . For example, clock pulse P 0  is the logical AND of delayed clock signals C 270  and C 0 . Clock pulse P 90  is the logical AND of delayed clock signals C 0  and C 90 . Clock pulse P 180  is the logical AND of delayed clock signals C 0  and C 90 . Clock pulse P 180  is the logical AND of delayed clock signals C 90  and C 180 . Clock pulse P 270  is the logical AND of delayed clock signals C 180  and C 270 . Clock pulse P 45  is the logical AND of delayed clock signals C 315  and C 45 . Clock pulse P 135  is the logical AND of delayed clock signals C 45  and C 135 . Clock pulse P 225  is the logical AND of delayed clock signals C 135  and C 225 . Clock pulse P 315  is the logical AND of delayed clock signals C 225  and C 315 . 
     Delayed clocks C 0 -C 315  and pulse clocks P 0 - 315  maintain their respective relationship to input clock signal CLK independent of how clock generator  1106  is configured and independent of the frequency of clock signal DFS CLOCK. Due to delays inherent at clock delay module  1102  and clock pulse module  1104 , individual delayed clocks and clock phases may be skewed relative to clock signal CLK. 
       FIG. 3  illustrates in schematic form a portion  300  of DFS  110  of  FIG. 1  including clock pulse module  1104  and clock generator module  1106  in accordance with a specific embodiment of the present disclosure. Portion  300  includes latches  302 ,  304 ,  306 ,  308 ,  310 ,  312 ,  314 ,  316 ,  318 , and  320 , AND gates  330 ,  332 ,  334 ,  336 ,  340 ,  342 ,  344 ,  346 ,  360 ,  362 ,  364 , and  366 , NAND gates  350 ,  352 ,  354 ,  356 ,  370 ,  372 ,  374 , and  376 , transmission gates  380 ,  381 ,  382 ,  383 ,  384 ,  385 ,  386 , and  387 , level retention latches  390  and  392 , and an OR gate  395 . 
     Latch  302  has a clock input to receive delayed clock signal C 0 , an input to receive signal ENAB( 0 ), and an output. Latch  304  has a clock input to receive delayed clock signal C 180 , an input connected to the output of latch  302 , and an output connected to a node labeled “EN 0 .” Latch  306  has a clock input to receive delayed clock signal C 0 , an input to receive signal ENAB( 1 ), and an output. Latch  308  has a clock input to receive delayed clock signal C 270 , an input connected to the output of latch  306 , and an output connected to a node labeled “EN 90 .” Latch  310  has a clock input to receive delayed clock signal C 0 , an input to receive signal ENAB( 2 ), and an output. Latch  312  has a clock input to receive delayed clock signal C 180 , an input connected to the output of latch  310 , and an output. Latch  314  has an clock input to receive delayed clock signal C 0 , an input connected to the output of latch  312 , and an output connected to a node labeled “EN 180 .” Latch  316  has a clock input to receive delayed clock signal C 0 , an input to receive signal ENAB( 3 ), and an output. Latch  318  has a clock input to receive delayed clock signal C 180 , an input connected to the output of latch  316 , and an output. Latch  320  has an clock input to receive delayed clock signal C 90 , an input connected to the output of latch  318 , and an output connected to a node labeled “EN 270 .” 
     AND gate  330  has an input to receive signal ENAB( 4 ), an input connected to node EN 0 , and an output to provide a signal labeled “EN 45 .” AND gate  332  has an input to receive signal ENAB( 4 ), an input connected to node EN 90 , and an output to provide a signal labeled “EN 135 .” AND gate  334  has an input to receive signal ENAB( 4 ), an input connected to node EN 180 , and an output to provide a signal labeled “EN 225 .” AND gate  336  has an input to receive signal ENAB( 4 ), an input connected to node EN 270 , and an output to provide a signal labeled “EN 315 .” 
     AND gate  340  has an input to receive delayed clock signal C 270 , an input to receive delayed clock signal C 0 , and an output. AND gate  342  has an input to receive delayed clock signal C 0 , an input to receive delayed clock signal C 90 , and an output. AND gate  344  has an input to receive delayed clock signal C 90 , an input to receive delayed clock signal C 180 , and an output. AND gate  346  has an input to receive delayed clock signal C 180 , an input to receive delayed clock signal C 270 , and an output. 
     NAND gate  350  has an input to receive delayed clock signal C 270 , an input to receive delayed clock signal C 0 , and an output. NAND gate  352  has an input to receive delayed clock signal C 0 , an input to receive delayed clock signal C 90 , and an output. NAND gate  354  has an input to receive delayed clock signal C 90 , an input to receive delayed clock signal C 180 , and an output. NAND gate  356  has an input to receive delayed clock signal C 180 , an input to receive delayed clock signal C 270 , and an output. 
     AND gate  360  has an input to receive delayed clock signal C 315 , an input to receive delayed clock signal C 45 , and an output. AND gate  362  has an input to receive delayed clock signal C 45 , an input to receive delayed clock signal C 135 , and an output. AND gate  364  has an input to receive delayed clock signal C 135 , an input to receive delayed clock signal C 225 , and an output. AND gate  366  has an input to receive delayed clock signal C 225 , an input to receive delayed clock signal C 315 , and an output. 
     NAND gate  370  has an input to receive delayed clock signal C 315 , an input to receive delayed clock signal C 45 , and an output. NAND gate  372  has an input to receive delayed clock signal C 45 , an input to receive delayed clock signal C 135 , and an output. NAND gate  374  has an input to receive delayed clock signal C 135 , an input to receive delayed clock signal C 225 , and an output. NAND gate  376  has an input to receive delayed clock signal C 225 , an input to receive delayed clock signal C 315 , and an output. 
     Transmission gate  380  has an input connected to node EN 0 , an n-channel input connected to the output of AND gate  340 , a p-channel input connected to the output of NAND gate  350 , and an output connected to a node labeled “SET 0 _CLK. Transmission gate  381  has an input connected to node EN 90 , an n-channel input connected to the output of AND gate  342 , a p-channel input connected to the output of NAND gate  352 , and an output connected to a node labeled “SET 0 _CLK. Transmission gate  382  has an input connected to node EN 180 , an n-channel input connected to the output of AND gate  344 , a p-channel input connected to the output of NAND gate  354 , and an output connected to a node labeled “SET 0 _CLK. Transmission gate  383  has an input connected to node EN 270 , an n-channel input connected to the output of AND gate  346 , a p-channel input connected to the output of NAND gate  356 , and an output connected to a node labeled “SET 0 _CLK. 
     Transmission gate  384  has an input connected to node EN 45 , an n-channel input connected to the output of AND gate  360 , a p-channel input connected to the output of NAND gate  370 , and an output connected to a node labeled “SET 45 _CLK. Transmission gate  385  has an input connected to node EN 135 , an n-channel input connected to the output of AND gate  362 , a p-channel input connected to the output of NAND gate  372 , and an output connected to a node labeled “SET 45 _CLK. Transmission gate  386  has an input connected to node EN 225 , an n-channel input connected to the output of AND gate  364 , a p-channel input connected to the output of NAND gate  374 , and an output connected to a node labeled “SET 45 _CLK. Transmission gate  387  has an input connected to node EN 315 , an n-channel input connected to the output of AND gate  366 , a p-channel input connected to the output of NAND gate  376 , and an output connected to a node labeled “SET 45 _CLK. 
     Level retention latch  390  has an input/output terminal connected to node SET 0 _CLK. Level retention latch  392  has an input/output terminal connected to node SET 45 _CLK. OR gate  395  has an input connected to node SET 0 _CLK, an input connected to node SET 45 _CLK, and an output to provide signal DFS CLOCK. 
     Latches  302  and  304  are configured to delay signal ENAB( 0 ) by 180°. Latches  306  and  308  are configured to delay signal ENAB( 1 ) by 270°. Latches  310 ,  312 , and  314  are configured to delay signal ENAB( 2 ) by 360°. Latches  316 ,  318 , and  320  are configured to delay signal ENAB( 3 ) by 450°. 
     AND gates  340 ,  342 ,  344 , and  346  are configured to provide signals P 0 , P 90 . P 180 , and P 270 , respectively. NAND gates  350 ,  352 ,  354 , and  356  are configured to provide the inverse of signals P 0 , P 90 . P 180 , and P 270 , respectively. AND gates  360 ,  362 ,  364 , and  366  are configured to provide signals P 45 , P 135 . P 225 , and P 315 , respectively. NAND gates  3770 ,  372 ,  374 , and  376  are configured to provide the inverse of signals P 45 , P 135 . P 225 , and P 315 , respectively. 
     Transmission gates  380 - 383  are configured to select one of clock pulse signals P 0 , P 90 , P 180 , and P 270  and provide that clock pulse signal to node SET 0 _CLK in response to the logic level of signals provided at nodes EN 0 , EN 90 , EN 180 , EN 270 , respectively. The Transmission gates  384 - 387  are configured to select one of clock pulse signals P 45 , P 135 , P 225 , and P 315  and provide that clock pulse signal to node SET 45 _CLK in response to the logic level of signals provided at nodes EN 45 , EN 135 , EN 225 , and EN 315 , respectively. During any time that node SET 0 _CLK is not actively driven, level retention latch  390  maintains the previously driven value at node SET 0 _CLK. During any time that node SET 45 _CLK is not actively driven, level retention latch  392  maintains the previously driven value at node SET 45 _CLK. 
     OR gate  395  is configured to combine signals conducted at nodes SET 0 _CLK and SET 45 _CLK to provide clock signal DFS CLOCK, which represents the superposition of the individual clock signals at node SET 0 _CLK and node SET 45 _CLK. Clock generator  130  can provide clock signal DFS CLOCK, where clock signal DFS CLOCK is a desired clock frequency relative to the frequency of input clock signal CLK as previously described. Clock signal DFS CLOCK is a superposition of particular individual clock pulses. The selection of particular clock pulses is determined by a sequence of values encoded by signal ENAB(0:3) and signal ENAB( 4 ). In a particular embodiment, the sequence of values provided by signal ENAB(0:3) can include up to sixteen four-bit values derived from a sequence of up to sixty-four binary values. A longer or shorter sequence of binary values can be used to provide a greater or fewer number of frequency divisor options. Clock signal SET 45 _CLK remains at a logic-low level if signal ENAB( 4 ) is negated. Signal ENAB( 4 ) is asserted when a desired clock divisor is not evenly divisible by decimal 0.5 so that the generated clock signal DFS CLOCK exhibits a substantially fifty percent duty cycle. 
       FIG. 4  is a timing diagram  400  illustrating the operation of the clock pulse module and a clock generator module of  FIG. 1  in accordance with a specific embodiment of the present disclosure. Timing diagram illustrates the operation of DFS  110  as configured to provide a clock signal DFS CLOCK, wherein the frequency of clock signal DFS CLOCK is substantially equal to the frequency of signal CLK divided by a value of 5/4. Timing diagram  400  includes a horizontal axis representing time, and a vertical axis representing voltage in volts. 
     Timing diagram  400  includes signal waveforms  402 ,  403 ,  404 ,  405 ,  406 ,  407 , 408 ,  410 ,  412 ,  414 ,  416 ,  418 ,  420 ,  422 ,  424 ,  426 , and  428 . Waveform  402  represents clock signal CLK of  FIG. 1  and  FIG. 2 . Waveform  408 ,  412 ,  416 , and  420  represent signals P 0 , P 90 , P 180 , and P 270  of  FIG. 3 , respectively. Waveforms  410 ,  414 ,  418 , and  422  represent signals EN 0 , EN 90 , EN 180 , and EN 270  of  FIG. 3 , respectively. Waveform  424 ,  426 , and  428  represent signals at nodes SET 0 _CLK and SET 45 _CLK, and signal DFS CLOCK of  FIG. 3 , respectively. Waveforms  403 ,  404 ,  405 ,  406 , and  407  represents the values associated with signal ENAB(0:4) during each cycle of clock signal CLK. A first cycle of clock signal CLK is associated with reference  450 , and the second cycle of clock signal CLK is associated with reference  452 . Timing diagram  400  also includes exemplary signal pulses  4082 ,  4122 ,  4242 ,  4262 , and  4282 . 
     DFS  110  is configured to select appropriate portions of signals provided by clock delay module  1102 , clock pulse module  1104 , and clock generator module  1106 , and superimpose the selected signal waveforms to represent a desired clock signal DFS CLOCK at the output of clock generator  1106 . Particular signals are selected based upon the value encoded by signal ENAB(0:4) during successive cycles of clock signal CLK. The data value provided by signal ENAB(0:3) at a particular cycle of clock signal CLK is based on a repeating sequence of binary values, whereby the repeating sequence of binary values determines the clock divisor implemented by clock generator  1106 . The clock divisor illustrated at  FIG. 4  is 5/4. Therefore, the frequency of clock signal DFS_CLOCK will be equal to the frequency of clock signal CLK divided by 1.25. The repeating sequence of binary value associated with a clock divisor of 5/4 is 1, 1, 0, 0, 0. The binary sequence is partitioned into groups of four binary values where each respective group is associated with a corresponding clock cycle. Signal ENAB(0:3) is encoded to these four binary values for the duration of each clock cycle. For example, during cycle  450 , signal ENAB( 0 ) is set to a value of 1, signal ENAB( 1 ) is set to a value of 1, signal ENAB( 2 ) is set to a value of 0, and signal ENAB( 3 ) is set to a value of 0, and these values are maintained for the duration of cycle  450 . The final zero of the five-bit binary sequence is provided during cycle  452  via signal ENAB( 0 ), while signals ENAB(1:3) represent the sequence beginning anew. Thus, the repeating five-bit binary sequence 110001100011000 . . . is partitioned into four-bit groups 1100 0110 0011 0001, etc. Each group is provided by signal ENAB(0:3) during each successive cycle of clock signal CLK. 
     During clock cycle  450 , signal ENAB( 0 ) has a value of 1. Thus, signal EN 0   410  is generated. Signal EN 0   410  is logically ANDed with signal P 0  and the resulting pulse  4802  is provided to node SET 0 _CLK during cycle  452 . During clock cycle  450 , signal ENAB( 1 ) is also asserted. Thus, signal EN 90   414  is generated. Signal EN 90   414  is logically ANDed with signal P 90 , and the resulting pulse  4122  is provided to node SET 0 _CLK during cycle  452 . The superposition of pulses  4802  and  4122  are illustrated by pulse  4242  of signal  424  at node SET 0 _CLK. 
     When the desired clock divisor is not divisible by 0.5, signal ENAB( 4 ) will remain asserted, as illustrated by binary sequence  407 . If the desired clock divisor is divisible by 0.5, signal ENAB( 4 ) will remain negated. The assertion of signal ENAB( 4 ), enables the operation of the portion of clock generator  1106  associated with node SET 45 _CLK. Pulses accumulated at node SET 45 _CLK are substantially the same as pulses provided to node SET 0 _CLK with the distinction that each respective pulse provided to node SET 45 _CLK is delayed by 45° relative to a corresponding pulse provided to node SET 0 _CLK. For example, pulse  4262  at node SET 45 _CLK is substantially equal to pulse  4242  at node SET 0 _CLK, but delayed by 45°. In another embodiment, clock generator  1106  can be configured to manipulate a greater or a fewer number of clock pulses. For example, clock pulse module  1104  can provide ten unique clock pulses to clock generator module  1106 , and each respective pulse provided to node SET 45 _CLK would be delayed by 36° relative to a corresponding pulse provided to node SET 0 _CLK. 
     Signal DFS CLOCK is the logical AND of the signals at nodes SET 0 _CLK and SET 45 _CLK. Thus, pulse  4282  at signal DFS CLOCK  428  represents the superposition of pulse  4242  and pulse  4262 . Binary sequence  404  represented by signal ENAB(0:3) determines which of pulses P 0 , P 45 , P 90 , P 135 , P 180 , P 225 , P 270 , and P 315  are selected during particular cycles of clock signal CLK. Clock signal DFS CLOCK is provided by DFS  110  as long as the repeating binary sequence is provided to clock generator  1106 . 
     The following table illustrates the binary sequence operable to provide the indicated clock divisor. 
     
       
         
               
             
               
               
             
           
               
                   
               
               
                 DIVISOR, BINARY SEQUENCE 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                  4/4 
                 4′b1100 
               
               
                  5/4 
                 5′b11000 
               
               
                  6/4 
                 6′b111000 
               
               
                  7/4 
                 7′b1110000 
               
               
                  8/4 
                 8′b11110000 
               
               
                  9/4 
                 9′b111100000 
               
               
                 10/4 
                 10′b1111100000 
               
               
                 11/4 
                 11′b11111000000 
               
               
                 12/4 
                 12′b111111000000 
               
               
                 13/4 
                 13′b1111110000000 
               
               
                 14/4 
                 14′b11111110000000 
               
               
                 15/4 
                 15′b111111100000000 
               
               
                 16/4 
                 16′b1111111100000000 
               
               
                 17/4 
                 17′b11111111000000000 
               
               
                 18/4 
                 18′b111111111000000000 
               
               
                 19/4 
                 19′b1111111110000000000 
               
               
                 20/4 
                 20′b11111111110000000000 
               
               
                 21/4 
                 21′b111111111100000000000 
               
               
                 22/4 
                 22′b1111111111100000000000 
               
               
                 23/4 
                 23′b11111111111000000000000 
               
               
                 24/4 
                 24′b111111111111000000000000 
               
               
                 25/4 
                 25′b1111111111110000000000000 
               
               
                 26/4 
                 26′b11111111111110000000000000 
               
               
                 27/4 
                 27′b111111111111100000000000000 
               
               
                 28/4 
                 28′b1111111111111100000000000000 
               
               
                 29/4 
                 29′b11111111111111000000000000000 
               
               
                 30/4 
                 30′b111111111111111000000000000000 
               
               
                 31/4 
                 31′b1111111111111110000000000000000 
               
               
                 32/4 
                 32′b11111111111111110000000000000000 
               
               
                 33/4 
                 33′b111111111111111100000000000000000 
               
               
                 34/4 
                 34′b1111111111111111100000000000000000 
               
               
                 35/4 
                 35′b11111111111111111000000000000000000 
               
               
                 36/4 
                 36′b111111111111111111000000000000000000 
               
               
                 37/4 
                 37′b1111111111111111110000000000000000000 
               
               
                 38/4 
                 38′b11111111111111111110000000000000000000 
               
               
                 39/4 
                 39′b111111111111111111100000000000000000000 
               
               
                 40/4 
                 40′b1111111111111111111100000000000000000000 
               
               
                 41/4 
                 41′b11111111111111111111000000000000000000000 
               
               
                 42/4 
                 42′b111111111111111111111000000000000000000000 
               
               
                 43/4 
                 43′b1111111111111111111110000000000000000000000 
               
               
                 44/4 
                 44′b11111111111111111111110000000000000000000000 
               
               
                 45/4 
                 45′b111111111111111111111100000000000000000000000 
               
               
                 46/4 
                 46′b1111111111111111111111100000000000000000000000 
               
               
                 47/4 
                 47′b11111111111111111111111000000000000000000000000 
               
               
                 48/4 
                 48′b111111111111111111111111000000000000000000000000 
               
               
                 49/4 
                 49′b1111111111111111111111110000000000000000000000000 
               
               
                 50/4 
                 50′b11111111111111111111111110000000000000000000000000 
               
               
                 51/4 
                 51′b111111111111111111111111100000000000000000000000000 
               
               
                 52/4 
                 52′b1111111111111111111111111100000000000000000000000000 
               
               
                 53/4 
                 53′b11111111111111111111111111000000000000000000000000000 
               
               
                 54/4 
                 54′b111111111111111111111111111000000000000000000000000000 
               
               
                 55/4 
                 55′b1111111111111111111111111110000000000000000000000000000 
               
               
                 56/4 
                 56′b11111111111111111111111111110000000000000000000000000000 
               
               
                 57/4 
                 57′b111111111111111111111111111100000000000000000000000000000 
               
               
                 58/4 
                 58′b1111111111111111111111111111100000000000000000000000000000 
               
               
                 59/4 
                 59′b11111111111111111111111111111000000000000000000000000000000 
               
               
                 60/4 
                 60′b111111111111111111111111111111000000000000000000000000000000 
               
               
                 61/4 
                 61′b1111111111111111111111111111110000000000000000000000000000000 
               
               
                 62/4 
                 62′b11111111111111111111111111111110000000000000000000000000000000 
               
               
                 63/4 
                 63′b111111111111111111111111111111100000000000000000000000000000000 
               
               
                   
               
             
          
         
       
     
     The first column of the table indicates the desired divisor, and ranges from 4/4 where the frequency of clock signal DFS CLOCK is the same as input clock signal CLK, to 63/4, where the frequency of clock signal DFS CLOCK is equal to the frequency of input clock signal CLK divided by 63/4 (decimal 7.75). The second column of the table includes a decimal number indicating the number of binary bits included in the binary sequence, followed by the binary sequence. For example, a divisor of 5/4 as illustrated at timing diagram  400  at  FIG. 4  is included at the second row of the table. The associated information identifies that the binary sequence is five bits in length, and the binary sequence is 1, 1, 0, 0, and 0. The binary sequence is continuously repeated for as long as clock signal DFS CLOCK is desired. The frequency of clock signal DFS CLOCK can be adjusted as desired by providing an appropriate sequence of data values at signal ENAB(0:4). Furthermore, the frequency of clock signal DFS CLOCK can be adjusted while data subsystem  150  continues to operate. Because the divisor 5/4 is not divisible by 0.5, signal ENAB( 4 ) is asserted for the entire duration that signal DFS CLOCK is desired. 
     A divisor of 6/4 is achieved by using the six-bit binary sequence included at the third row of the table: 1, 1, 1, 0, 0, 0. This sequence is repeated and is portioned into groups of four bits: 1110 0011 1000 1110, etc, and each four-bit group is encoded via signal ENAB(0:3) during successive cycles of clock signal CLK. Because the divisor 6/4 is divisible by 0.5, signal ENAB( 4 ) is negated for the entire duration that signal DFS CLOCK is desired. 
       FIG. 5  is a flow diagram  500  illustrating a method in accordance with a specific embodiment of the present disclosure. The flow begins at block  510  where a first plurality of phase shifted clock signals is received from clock delay module  1102 , including signals C 0 , C 90 , C 180 , and C 270 . The flow proceeds to block  520  where a second plurality of phase shifted clock signals is received from clock delay module  1102 , including signals C 45 , C 135 , C 225 , and C 315 . These signals represent input clock signal CLK successively shifted by 45°. The flow proceeds to block  530  where a sequence of data values are received at clock generator  1106  via enable signals ENAB(0:4). The flow proceeds to block  540  where a portion of output clock signal DFS CLOCK is synthesized at node SET 0 _CLK based on the first plurality of phase shifted clock signals and the signal ENAB(0:4). The flow proceeds to block  550  where another portion of output clock signal DFS CLOCK is synthesized at node SET 45 _CLK based on the second plurality of phase shifted clock signals and the signal ENAB(0:4). The flow proceeds to block  560  where output clock signal DFS CLOCK is determined by logically superimposing the signals provided at nodes SET 0 _CLK and SET 45 _CLK. 
     Note that not all of the activities or elements described above in the general description are required, that a portion of a specific activity or device may not be required, and that one or more further activities may be performed, or elements included, in addition to those described. Still further, the order in which activities are listed are not necessarily the order in which they are performed. 
     Also, the concepts have been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present disclosure as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present disclosure. 
     For example, DFS  110  can be configured to provide a clock signal other than a fifty percent duty cycle square-wave. Providing an appropriate sequence of enable data values to clock generator module  1106  can provide clock signals with another duty cycle. Furthermore, DFS CLOCK can be configured to include a pulse-train with a desired sequence of duty cycles. The transition from one clock frequency to another can be configured to include specific control of pulse-duration as needed to achieve setup and hold requirements. 
     Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any feature(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature of any or all the claims.