Abstract:
A method and system for providing parity protection to data. The method and system includes transmitting pairs of groups of bits. Each one of the groups of bits has bits representing the data and a parity bit. The parity sense of one of the pair of groups of bits is opposite to the parity sense of the other one of the pair of groups of bits. The transmitted pair of groups of bits are received. The received pair of groups of bits are parity checked to determine whether the parity sense of one of the received pair of groups, of bits is opposite to the parity sense of the other one of the received pair of groups of bits. With such an arrangement, a failure in the data driver or data receiver which causes the output of all bits produced by such driver to assume the same logic state can be detected because the received pair of groups of bits will have, with such failure, the same parity sense. The method and system also includes transmitting successive groups of bits in response to clock pulses. With such an arrangement, a method and system are provided for detecting a failure in the clock pulses because such a failure will result in the absence of an alternating parity sense in the successively received groups of bits.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates generally to fault tolerant parity generation. 
     As is known in the art, data is typically transferred from a source to a destination, or target, through a data driver and a data receiver. More particularly, referring to FIG. 1, a parallel bus data transmission system is shown to include a data source which produces a sequence of N bit digital data to be transmitted to a data target. Here, the data from the data source is transmitted over a backplane. The data produced by the data source is fed first to a data driver. The driver is used to provide sufficient power to drive the backplane. The data on the backplane is then fed to a data receiver. The data receiver is a high input impedance device, or buffer, used to isolate the data target from the backplane (i.e., to reduce loading on the backplane). 
     In order to provide some assurance of data transfer between the data source and the data target, the N bit data produced by the data source has appended to it an additional bit, i.e., a parity bit, as shown in FIG.  2 . The parity bit is representative of the number of logic 1 states in the N bit digital word. For example, if there are an odd number of logic 1 bits in the N bit word, a logic 0 parity bit may be appended to the word. In such case, the parity sense of the appended word is sometimes referred to as odd parity. In other cases, if there are an odd number of logic 1 bits in the N bit word, a logic 1 parity bit may be appended to the word. In such case, the parity sense of the appended word is referred to as even parity. In either case, the N plus one bit word is checked for parity sense by a parity checker at the output of the data receiver. A byte 00100101 protected with even parity has a logic 1 parity bit. The byte 00100101 protected with odd parity has a logic 0 parity bit. Thus, parallel data transmission with parity protection over the data is provided, given the parity bit correctly corresponds with the given protection sense, odd or even. 
     Typically, the data on the backplane shown in FIGS. 1 and 2 is segmented into groups, typically bytes, where a byte is eight bits. Thus, for example, with a 72 bit backplane bus, there are 9 bytes. Furthermore, the parity scheme of FIG. 2 is typically byte-parity, where one parity bit is generated for each byte of data. Thus, with the 72 bit backplane bus, there are 8 bytes of data and 8 parity bits. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, a method and system are provided for providing parity protection to data. The method and system include transmitting data as a pair of groups of bits, one of the pair having odd parity and the other one of the pair having even parity. Embodiments of this method and system include transmitting the groups of bits in parallel and/or sequentially. 
     In accordance with another aspect of the invention a method and system are provided for providing parity protection to data. The method and system includes transmitting data as a pair of sequential transmitted groups of bits, one of the pair having odd parity and the other one of the pair having even parity. 
     In accordance with another aspect of the invention, a method and system are provided for providing parity protection to data. The method and system transmit a pair of groups of bits. Each one of the groups of bits has bits representing the data and a parity bit. The parity sense of one of the pair of groups of bits is opposite to the parity sense of the other one of the pair of groups of bits. The transmitted pair of groups of bits is received and their parity is checked to determine whether the parity sense of one of the received pair of groups of bits is opposite to the parity sense of the other one of the received pair of groups of bits. 
     With such an arrangement, a failure in the data driver or data receiver, which causes the output of all bits produced by such driver, or receiver, to assume the same logic state, can be detected because the received pair of groups of bits will have, with such failure, the same parity sense rather than the opposite parity sense as such groups of bits were transmitted. 
     In accordance with another feature of the invention, a method and system are provided for providing parity protection to data. The method and system includes transmitting successive groups of bits in response to clock pulses. Each one of the groups of bits has bits representative of the data and a parity bit. The parity sense of the groups of bits alternates as such groups are successively transmitted. The transmitted groups of bits are successively received in response to the clock pulses. The successively received groups are parity checked to determine whether the parity sense of the successively received groups of bits alternate with the clock pulses. 
     With such an arrangement, a method and system are provided for detecting a failure in the clock pulses because such a failure will result in the absence of an alternating parity sense in the successively received groups of bits. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     These and other features of the invention will become more readily apparent from the following detail description when read together with the accompanying drawings, in which: 
     FIG. 1 is a data transmission system according to the PRIOR ART; 
     FIG. 2 is a data transmission system having parity checking according to the PRIOR ART; 
     FIG. 3 is a data transmission system according to the invention; 
     FIG. 4 is a timing diagram showing a sequence of data being clocked, with one group of bits of such data having an alternating sequence of parity sense and another group of such bits of the data having an opposite alternating sequence of parity sense; 
     FIG. 5 is a timing diagram showing inputs and outputs of a pair of parity checkers used in the system of FIG. 3, such outputs being shown in the absence of faults in the system; 
     FIG. 6 is a schematic diagram of a pulse train detector used in the system of FIG. 3, such detector being adapted to detect a fault in such system; 
     FIG. 7 is a timing diagram showing outputs of a pair of parity checkers and the output of the pulse train detector of FIG. 6, such outputs being shown in the absence of a fault in the system; 
     FIG. 8 is a timing diagram showing outputs of a pair of parity checkers and the output of the pulse train detector of FIG. 6, such outputs being shown in the presence of one type of fault in the system; 
     FIG. 9 is a timing diagram showing outputs of a pair of parity checkers and the output of the pulse train detector of FIG. 6, such outputs being shown in the presence of another type of fault in the system; 
     FIG. 10 is a data transmission system in according to the invention; and 
     FIG. 11 is a timing diagram showing outputs of a pair of parity checkers and the output of the pulse train detector of FIG. 10, such outputs being shown in the presence of another type of fault in the system. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to FIG. 3, a system  10  is shown adapted to provide parity protection to data. The system  10  includes a data source section  11  for successively transmitting data in response to clock pulses, CLK. Each transmitted data, D, includes a pair of groups of bits, GA T , GB T . Each one of the groups of bits GA T , GB T  has bits representing data from a data source  12  (i.e., BYTE A T , BYTE B T , respectively) and a parity bit provided by parity bit generators  14 A,  14 B, respectively, (i.e., PA T , PB T , respectively). (It should be understood that while two bytes are used for purposes of understanding, a more typical application may include, for example, eight bytes. In such case, there would be formed four pairs of bytes.) Here, in this example using a pair of bytes produced by the data source  12  , BYTE A T  and BYTE B T , each of the two bytes, BYTE A T , BYTE B T , is fed to a corresponding one of the pair of parity bit generators  14 A,  14 B, respectively, as indicated. The output PA T , PB T , of the parity bit generators  14 A,  14 B together with BYTE A T  and BYTE B T , provide the pair of groups of bits, i.e., group of bits GA T  and group of bits GB T , respectively. The parity sense of one of the pair of groups of bits is opposite to the parity sense of the other one of the pair of groups of bits. Further, the parity sense of the each of the pair of groups of bits GA T , GB T , alternates successively with the clock pulses CLK. 
     More particularly, and referring to FIG. 4, as data D 1 , D 2 , D 3 , . . . is sequentially produced by the data source  12 , the parity sense of the group of bits GA T  alternates sequentially in response to the clock pulses, and concurrently therewith, the parity sense of the group of bits GB T  alternates with opposite parity sense in response to the clock pulses CLK. Further, the parity sense provided by parity generator  14 A alternates in response to clock pulses CLK, the default, or initial, parity sense being, here odd parity. Conversely, the parity sense provided by parity generator  14 B alternates in response to clock pulses CLK, the default, or initial, parity sense being, here even parity. 
     Thus, as shown in FIG. 4, for the sequence of data D 1 , D 2 , D 3 , D 4 , . . . , the first group of bits GA T  are: GA T1 ; GA T2 ; GA T3 ; GA T4 ; . . . , and the parity sense of such sequence of the first group of bits is: odd; even; odd; even; . . . respectively, while, the parity sense sequence of the second group of bits GB T1 ; GB T2 ; GB T3 ; GB T4 ; . . . . is, in such case: even; odd; even; odd; . . . , respectively. Thus, if the parity sense of the first group of bits, GA T  has an even parity sense, the parity sense of the second group of data GB T  has an odd parity sense. Conversely, if the parity sense of the first group of bits GA T  (i.e., BYTE A T  and parity bit PA T ) has an odd parity sense, the parity sense of the second group of bits GB T  (i.e., BYTE B T and parity bit PB T ) has an even parity sense. 
     The data source section  11  includes a data driver  18  for coupling the groups of bits GA T , GB T , respectively to the busses  13 A,  13 B, respectively. Here, the data driver  18  includes a register, not shown, adapted to store the two bytes, i.e., BYTE A T  and BYTE B T , and the parity bits PA T  and PB T associated with such BYTES A T  and B T , respectively, in response to a clock pulse CLK fed to such driver  18 . 
     The system  10  (FIG. 3) also includes a backplane bus  13  for receiving the sequentially transmitted data. For each transmitted data, i.e., the transmitted pair of groups of bits GA T , GB T , are fed, in parallel, i.e. in the same state or clock cycle CLK, to a corresponding pair of busses  13 A,  13 B, respectively, of bus  13 . 
     A data receiver section  15  is provided for receiving the pair of groups of bits on busses  13 A,  13 B, in parallel, such received groups of bits being designated as GA R , GB R , respectively, where group of bits GA R  includes a data BYTE A R  and associated parity bit PA R  and group of bits GB R  includes a data BYTE B R  and associated parity bit PB R . It is noted that, in the absent of any fault in the transmission of the groups GA T , GB T  through the busses  13 A,  13 B, respectively, the received group of bits GA R  will be the same as the transmitted group of bits GA A  and, likewise, the received group of bits GB R  will be the same as the transmitted group of bits GB T . 
     The data receiver section  15  includes a data receiver  22 . The data receiver  22  is coupled to bus  13 A to receive the group of bits GA R  and to bus  13 B to receive the group of bits GB R . Here, the data receiver  22  includes a register, not shown, adapted to store the two groups of bits GA R , GB R  in response to clock pulse CLK fed to data receiver  22 . 
     The data receiver section  15  also includes a pair of parity checkers  16 A,  16 B coupled to the data receiver  22 , as shown. The parity checkers  16 A,  16 B perform a parity check on the received pair of groups of bits GA R , GB R , respectively, to determine whether the parity sense of one of the received pair of groups of bits is opposite to the parity sense of the other one of the received pair of groups of bits. Both groups of bits GA R , GB R  are sequentially fed to the parity checkers  16 A,  16 B, respectively, in response to the data receiver  22  storing both groups GA R , GB R  in response to the clock pulses CLK. That is, in sequence to CLK 1 , CLK 2 , both GA R1 , GB R1 , and GA R2 , GB R2  are sent to parity checkers  16 A,  16 B. The parity checkers  16 A,  16 B will produce a logic output having a first logic state, here for example a logic 1, if the group of bits to it have an odd parity sense and the opposite logic state, here a logic 0, if the group of bits fed to it have an even parity sense. 
     Thus, and referring also to FIG. 5, with the parity sense of the sequence of groups of bits GA R1 , GA R2 , . . . changing in response to the clock pulses, absent a fault, the parity checker  16 A will change from logic 1 to logic 0, etc., with the clock pulses CLK, as shown in FIG.  5 . Thus, in the absence of a fault, it is noted that there is a train of pulses produced by parity checker  16 A (i.e., 1010 . . . ). 
     In like manner, with the parity sense of the sequence of groups of bits GB R1 GB R2 , . . . changing in response to the clock pulses, absent a fault, the parity checker  16 A will change from logic 0 to logic 1, etc., with the clock pulses CLK, as shown in FIG.  5 . Thus, in the absence of a fault, it is noted that there is a train of pulses produced by parity checker  16 B (i.e., 0101 . . . ). 
     The outputs of the parity checkers  16 A,  16 B are fed to a pulse train detector  30 , here a three bit up/down counter, as shown in FIG.  6 . Also fed to the pulse train detector  30  is a clock pulse, 4CLK, having a rate 4 times the clock rate fed to the data source  12 , parity bit generators  14 A,  14 B, data driver  18  and data receiver  22 , as indicated in FIG.  7 . The UP input of the counter is fed by the output of parity checker  16 A and the COUNTER CLOCK input is fed by 4CLK (i.e., clock pulse at 4 times CLK). The contents of counter  30  will increment by one from an initial reset count of 0 to a maximum count of 7 in response to each one of the clock pulses fed to the COUNTER CLOCK input thereof when the output of the parity checker  16 A is logic 1 (i.e., when the parity checker  16 A indicates odd parity). The DOWN input is fed by the output of the parity checker  16 B. The contents of counter  30  will decrement by one in response to each one of the clock pulses fed to the COUNTER CLOCK input thereof when the output of the parity checker  16 B is logic 1 (i.e., when the parity checker  16 B indicates odd parity). Thus, in the absence of a fault, the contents of the counter  30  increment by one from an initial reset count of 0 to a count of 4 when parity checker  16 A produces a logic 1 and then the contents of the counter decrement by one from the count of 4 to a count of zero when the parity checker  16 B produces a logic 1. It is noted that absent a fault the contents of the counter  30  will never be the same value for two consecutive clock pulses fed to the COUNTER CLOCK input. It is further noted that the contents of counter  30  will hold its count value in response each one of the clock pulses fed to the COUNTER CLOCK input thereof should the output from both parity checker  16 A and parity checker  16 B be the same. 
     Referring now to FIG. 8, an example is presented where there is a fault in system  10  (FIG.  3 ). Here, the fault is such that the data driver  18  has its output “stuck” at time t 1  so that it produces all logic  1 s, as indicated. That is all 18 bits at the output of the driver  18  are logic 1 (i.e., group of bits GA R  and group of bits GB R  will both have odd parity). Thus, the output of parity checker  16 A will continue to indicate odd parity and therefore continue to produce a logic 1 and the output of parity checker  16 B will change to also indicate odd parity. Therefore, the contents of the counter  30  will be unable to count, i.e. freeze, holding the counter at a count of 4 in this example, as shown. A fault is therefore detected because the contents of counter  30  does not change for two consecutive clock pulses fed to the COUNTER CLOCK input. 
     Referring to FIG. 9, an example is presented where there is a different type of fault in system  10  (FIG.  3 ). Here, the fault is that the data driver  18  fails to respond to a clock pulse CLK at time t 1 . That is, the same group of bits GA T  and GB T  remain, here at even parity and odd parity, respectively in the data driver  18  for two consecutive clock pulses CLK even though the parity bit generators  14 A and  14 B have changed the parity sense for these two consecutive clock pulses CLK. Thus, in this example, the parity of group of bits GA R  will remain at even parity for the two consecutive clock pulses CLK and the group of bits GB R  will remain at odd parity for the two consecutive clock pulses CLK. Thus, the counter  30  will be enabled to decrement in response to the clock pulse 4CLK fed to the COUNTER CLOCK terminal thereof; however, the contents of such counter  30  cannot decrement to less than a count of 0. Therefore, a fault is therefore detected because the contents of counter  30  will remain at the same count, here a count of 0, for two consecutive clock pulses fed to the COUNTER CLOCK input. 
     Referring to FIG. 10, system  100  is an alternative embodiment of FIG. 3 wherein the elements having the same numerical designator as described above in association with FIG. 3 provide substantially the same function in system  100  as the corresponding elements in system  10 . However, system  100  replaces data driver  18  in FIG. 3 with a group of data drivers, here  18 ′ and  18 ″. Data drivers  18 ′,  18 ″ serve to couple groups of bits GA T , GB T , respectively to busses  13 A and  13 B, respectively. System  100  also replaces data receiver  22  in FIG. 3 with a group of data receivers, here  22 ′ and  22 ″. Data receivers  22 ′,  22 ″ are also coupled to busses  13 A and  13 B, respectively and function to receive groups of data bits GA R , GB R , respectively, transmitted over bus  13 . 
     Referring to FIG. 11, an example is presented where a sequential type fault occurs in system  100  (FIG.  10 ). Here, the data driver  18 ′ fails to respond to a clock pulse CLK at time t 1 . That is, the same group of bits GA T  remain in the driver  18 ′, here at even parity, respectively, for two consecutive clock pulses CLK even though the parity bit generators  14 A and  14 B have changed the parity sense for these two consecutive clock pulses CLK. Thus, in this example, the parity of group of bits GA R  will remain even parity for the two consecutive clock pulses CLK and the group of bits GB R  will continue to alternate parity. Thus, when signals GA R  and GB R  are non complementary, i.e. when both are logic 1 or logic 0, counter  30 , the pulse train detector, will be unable to count in response to the clock pulse 4CLK fed to the COUNTER CLOCK terminal thereof. Therefore, a fault is detected because the contents of counter  30  will remain at the same count, here a count of 0, for two consecutive clock pulses 4CLK fed to the COUNTER CLOCK input. 
     Thus, in summary, it is noted that pulse train detector  30  is provided for detecting the presence of both faults in parallel data transmissions, i.e. same state or CLK faults, as in FIG. 8, and faults in consecutive data transmissions, i.e. sequential state faults, as in FIGS. 9 and 11. 
     Same state faults are detected when the parity sense between parallel groups of transmitted bits, i.e. groups of bits received in the same CLK cycle or state, are the same. Such faults are detected when the pair of the group of received bits GA Rn  has the same parity sense as the other pair of the group of bits GB Rn . In other words, a same state fault is detected when the parity sense of the groups of bits received in parallel, GA Rn , GB Rn , do not oppose each other. 
     Sequential state faults are detected when the parity sense between sequential groups of received bits are the same. Such faults are detected when the one group of received bits, GA Rn , (or GB Rn ), has the same parity sense as the next sequential group of received bits, GA Rn+1 , (or GB Rn+1 ). In other words, a sequential state fault is detected when the parity sense of sequentially received groups of bits do not alternate, or toggle, in their parity sense. 
     Other embodiments are within the spirit and scope of the appended claims.