Abstract:
An apparatus conducts current through a two terminal inductive load. The apparatus has a first conduction path, from a first supply voltage to one terminal of the inductive load and a second conduction path from the second terminal of the inductive load to a second supply voltage. The first conduction path includes a switching device that is controlled by a field-effect transistor having a gate terminal, second terminal, and third terminal. The gate terminal of the field-effect transistor is coupled to a reference voltage. The voltage at the second terminal of the field-effect transistor increases when the voltage at the field-effect transistor&#39;s third terminal increases.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a write circuit for an inductive transducer in a magnetic data storage device. In particular, the present invention pertains to a write circuit with an improved pre-driver stage that reduces switching time while avoiding transistor breakdown. 
     The present invention is typically used to store information on a magnetic disc in a magnetic disc drive. The information is stored on the disc by creating a series of small magnetic domains within the disc. The small magnetic domains are formed by passing an inductive transducer near the surface of the disc while the inductive transducer creates a magnetic field. As the transducer passes over an area of the disc, the magnetic moment of that area aligns to the direction of the transducer&#39;s magnetic field. This alignment forms the magnetic domain, which is defined at its boundaries by a change in the direction of the disc&#39;s magnetic moment. Changes in the direction of the disc&#39;s magnetic moment are created by changing the direction of the magnetic field generated by the transducer as it passes over the disc. 
     The magnetic field generated by the transducer is produced by passing current through an inductive load. The direction of the current passing through the inductive load determines the direction of the magnetic field. Thus, reversing the direction of the current through the inductive load reverses the direction of the magnetic field. 
     The direction of the current passing through the inductive load is controlled by a write circuit. Typically the write circuit is configured as an H-switch that contains two pairs of switches; a lower pair of switches and on upper pair of switches. By simultaneously activating one switch in each pair, the write circuit can direct current in a first direction through the inductive load. By deactivating these two switches and activating the other two switches, one from each pair, the write circuit can direct current in an opposite direction through the inductive load. 
     Typically, the two lower switches are directly activated and deactivated in a complimentary manner by two complimentary input signals. The two input signals also indirectly activate and deactivate the upper switches through a pre-driver stage. The speed with which the complimentary input signals and the pre-driver stage cause the switches of the H-switch to change states partially determines the performance of the write circuit. Specifically, the speed of the switching partially determines the rate at which data may be written to the disc. 
     FIG. 1 shows a write circuit of the prior art which includes an H-switch constructed from transistors Q 1 , Q 2 , Q 3 , Q 4 , inductor L, and current source I W , Transistor Q 1  has its collector connected to upper power supply V CC  and its emitter connected to the collector of transistor Q 3  and one terminal of inductor L. Transistor Q 2  has its collector connected to upper power supply V CC  and its emitter connected to the collector of transistor Q 4  and the other terminal of inductor L. The emitters of transistors Q 3  and Q 4  are connected together and to current source I W , which is further connected to lower power supply V EE . Transistors Q 1  and Q 2  form an upper pair of switches and transistors Q 3  and Q 4  form a lower pair of switches. When transistors Q 1  and Q 4  are active, current is conducted through inductor L in a first direction and when transistors Q 2  and Q 3  are active, current is a conducted in a second direction through inductor L. 
     The bases of transistors Q 1  and Q 2  are connected to a pre-driver stage that activates and deactivates the two transistors in a complimentary manner. The portion of the pre-driver stage connected to the base of transistor Q 1  is an inverter constructed from P-channel Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) M 2  and N-channel MOSFET M 1 . The source of MOSFET M 2  is connected to upper power supply V CC  and the source of MOSFET M 1  is connected to lower power supply V EE . The gates of MOSFETs M 1  and M 2  are connected together to form an inverter input that is indirectly connected to an input node V Y  through level shifter LS 1 . The level shifter enhances the signal on input node V Y  so that the enhanced signal can control the MOSFETs. The drains of MOSFETs M 1  and M 2  are connected together to form an inverter output that is connected to the base of transistor Q 1 . 
     Similarly, P-channel MOSFET M 4  and N-channel MOSFET M 3  are configured as an inverter at the base of transistor Q 2 . The source of MOSFET M 4  is connected to upper power supply V CC  and the source of MOSFET M 3  is connected to lower power supply V EE . The drains of MOSFETs M 3  and M 4  are connected together to form an inverter output that is connected to the base of transistor Q 2 . The gates of MOSFETs M 3  and M 4  are connected together to form an inverter input, which is connected to a second input node V X  through level shifter LS 2 . The level shifter enhances the signal on input node V X  so that the enhanced signal can control the MOSFETs. 
     In operation, when the signal on input node V Y  is high, the signal on input node V X  is low, transistor Q 3  is active and transistor Q 4  is inactive. Thus, transistor Q 4  does not conduct current and transistor Q 3  conducts nearly all of the current from current source I W . The high value at input node V Y  raises the voltage at the gates of MOSFETs M 1  and M 2  and causes MOSFET M 2  to act as a high impedance between upper power supply V CC  and the base of transistor Q 1 . The high value at input node V Y  also causes MOSFET M 1  to act as a low impedance element between lower power supply V EE  and the base of transistor Q 1 . Thus, the base of transistor Q 1  is essentially reduced to the voltage of lower power supply V EE , deactivating transistor Q 1 . 
     The low value at input node V X  lowers the voltage at the gates of MOSFETs M 3  and M 4  and causes N-channel MOSFET M 3  to act as a high impedance between lower power supply V EE  and the base of transistor Q 2 . The low value at V X  also causes P-channel MOSFET M 4  to act as a low impedance between upper power supply V CC  and the base of transistor Q 2 . This raises the voltage at the base of transistor Q 2  to nearly the voltage of upper power supply V CC  and thereby activates transistor Q 2 . 
     Thus, with V Y  high and V X  low, transistors Q 1  and Q 4  are inactive and do not conduct current and transistors Q 2  and Q 3  are active and conduct nearly all of the current of current source I W . 
     If the input values are reversed with V Y  low and V X  high, transistors Q 1  and Q 4  conduct current I W  and transistors Q 2  and Q 3  are inactive. Thus, the direction of the current flowing through inductor L is reversed when the input values are reversed. 
     The MOSFETs of FIG. 1 have several characteristics that make them desirable as pre-driver transistors. In particular, MOSFETs are able to pull the bases of the upper switching transistors to nearly V CC  and thereby are able to maximize the amount of swing for a given voltage difference between the power supplies. However, the MOSFETs also limit the write circuit of FIG. 1 because they have a breakdown voltage that limits the voltage difference between the power supplies. Specifically, when input V Y  is high, the base of transistor Q 1  has its voltage lowered to essentially the voltage of lower power supply V EE . In this state, MOSFET M 2  sees a source-to-drain voltage equal to V CC  minus V EE . If this voltage difference exceeds the source-to-drain breakdown voltage of the MOSFET, the MOSFET will &#34;burn out&#34; and the write circuit will be destroyed. Thus, the two power supply voltages must be chosen so that the difference between the voltages is less than the MOSFET breakdown voltage. 
     By limiting the difference between the supply voltages, the MOSFET breakdown voltage indirectly limits the voltage across the inductor during switching. This inductor voltage, known as swing, determines the switching time of the inductor because the rate of change of current in the inductor is equal to the voltage across the inductor divided by the inductance. Thus, by limiting the voltage difference between the power supplies, the MOSFET breakdown voltage indirectly limits the switching speed of the write circuit. 
     To avoid limiting the switching speed of the inductor, the MOSFET breakdown voltages may be increased so that a larger voltage difference between the power supplies does not cause MOSFET breakdown. However, if a MOSFET&#39;s breakdown voltage is increased, its switching speed will deteriorate. The reason for this deterioration is that a MOSFET&#39;s breakdown voltage is proportional to the gate length, and it is the gate length that determines the switching speed. The shorter the gate length, the lower the corresponding breakdown voltage. 
     Therefore, if MOSFETs are to be used in the prior art write circuits, either the switching speed of the MOSFET or the switching speed of the inductor must be sacrificed to accommodate the breakdown voltages of the MOSFETs. 
     SUMMARY OF THE INVENTION 
     The present invention is an apparatus for conducting current through a two terminal inductive load. The apparatus has a first conduction path from a power supply to one end of the inductive load. This first conduction path includes a switching device used to control the current along the first conduction path. The apparatus also has a second conduction path extending from a second end of the inductive load to a second supply voltage. The apparatus further contains a field-effect transistor having a gate terminal coupled to a reference voltage, a second terminal coupled to a node having a time varying voltage, and a third terminal coupled to the switching device of the first conduction path. The voltage at the third terminal of the field-effect transistor is capable of increasing when the voltage at the second terminal of the field-effect transistor increases. 
     Since the voltages at the second and third terminals of the field-effect transistor track each other, the voltage difference between these two terminals is kept small and relatively independent of the voltage difference between the two power supplies. In a typical embodiment, where the field-effect transistor is a P-channel MOSFET with its gate coupled to the reference voltage, its source coupled to the time varying voltage node, and its drain coupled to the switching device, the fact that the second and third terminals track each other means that the source-to-drain breakdown voltage of the MOSFET does not significantly affect the choice of power supply voltages. 
     In some embodiments of the present invention, the time varying voltage at the second terminal of the field effect transistor is created by an inverter. The inverter is preferably constructed from a P-channel MOSFET and an N-channel MOSFET, with the drains of the MOSFETs coupled to the source of the common-gate MOSFET and the gates of the inverter MOSFETs connected together to form an inverter input. The source of the inverter&#39;s P-channel MOSFET is connected to the first power supply voltage, and the source of the inverter&#39;s N-channel MOSFET is connected to the reference voltage. 
     In such embodiments, the inverter and the common-gate MOSFET provide two distinct voltage-impedance states. In one state, the inverter input is low, causing a high source-to-drain impedance in the inverter&#39;s N-channel MOSFET and a low source-to-drain impedance in the inverter&#39;s P-channel MOSFET. Because of the P-channel MOSFETs low impedance, the output of the inverter is essentially at the first power supply voltage, meaning that the source of the common-gate MOSFET is at the first power supply voltage. This causes the P-channel common-gate MOSFET to have a low source-to-drain impedance and thereby completes a high-conductivity/low-impedance path between the switching device and the first power supply voltage. This state quickly raises the base of the switching device to the first supply voltage. The low impedance is significant since it allows the base voltage to be raised close to the first supply voltage. 
     In the second voltage-impedance state, the input to the inverter is high, the inverter&#39;s P-channel MOSFET has a high source-to-drain impedance, and the inverter&#39;s N-channel MOSFET has a low source-to-drain impedance to the reference voltage. Thus, with the inverter input high, the source of the common-gate MOSFET is essentially at the reference voltage. Since this is the same voltage as the voltage at the gate of the common-gate MOSFET, the common-gate MOSFET has a high source-to-drain impedance. This means that the switching device is coupled to the reference voltage through a high-impedance/low-conductivity path. This state can be used to quickly lower the voltage at the base of the switching device by discharging all of the capacitance at the base&#39;s node. This will lower the voltage at the base of the switching device to a value below the reference voltage. 
     It is preferred in the second state described above that the voltage at the base of the switching device be prevented from coming too close to the second power supply voltage since such voltages can cause other elements in the invention to saturate. Preferably, this is accomplished using a P-N junction, such as a diode, and a saturation reference voltage. The P-N junction is connected between the saturation reference voltage and the base of the switching device so that when the common-gate MOSFET has a high source-to-drain impedance, the voltage at the base of the switching device only differs from the saturation reference voltage by the forward-bias voltage across the P-N junction. The saturation reference voltage is preferably chosen to be as close to the second power supply voltage as possible without causing saturation of other elements in the circuit. 
     When the present invention is used as part of an H-switch, the swing of the inductor is dependent on the voltage difference between the first power supply voltage and the saturation reference voltage. It is not necessarily dependent on the maximum voltage seen by the inverter&#39;s MOSFETs, which is the voltage difference between the first power supply voltage and the common-gate reference voltage. The fact that the swing voltage is not dependent on the maximum voltage seen by the inverter means that the swing voltage is not limited by the source-to-drain breakdown voltage of the inverter&#39;s MOSFETs. As such, in the present invention, the swing voltage may be greater than the breakdown voltage of the MOSFETs. 
     Since the present invention separates the breakdown voltages of the inverter&#39;s MOSFETs from the swing of the inductive transducer, it can use the MOSFETs ability to raise the base of the switching device close to the first supply voltage without significantly restricting the value of the second supply voltage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram of a prior art write circuit. 
     FIG. 2 is a diagram of a write circuit according to the present invention. 
     FIG. 3 is a detailed diagram of a second embodiment of a second pre-driver stage for the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 2 is a circuit diagram of one embodiment of the present invention. The current through an inductor L A  is controlled by an H-switch constructed from four transistors, Q 1A , Q 2A , Q 3A , and Q 4A , as well as current source I WA . Transistor Q 1A  has its collector connected to an upper power supply voltage V CC  and its emitter connected to one terminal of inductor L A . Transistor Q 2A  has its collector connected to upper power supply voltage V CC  and its emitter connected to a second terminal of inductor L A . The collectors of transistors Q 3A  and Q 4A  are connected to the emitters of transistors Q 1A  and Q 2A , respectively. The emitters of transistors Q 3A  and Q 4A  are connected together and to current source I WA , which is connected between these emitters and lower power supply voltage V EE . 
     The H-switch, which forms a driver or switching stage, is connected to a first pre-driver stage constructed from BJT transistors Q 5  and Q 6 , P-channel MOSFETs M 5  and M 6 , and diodes D 1  and D 2 . The bases of transistors Q 1A  and Q 2A  are connected to the drains of MOSFETs M 5  and M 6 , respectively. The drain of MOSFET M 5  is further connected to the collector of transistor Q 6  and to the cathode of diode D 2 . The gate of MOSFET M 5  is connected to a reference voltage, which has a value between upper power supply voltage V CC  and lower power supply voltage V EE , and is typically at ground. Since MOSFET M 5  has its gate connected to a reference voltage, it is known as a common-gate MOSFET. Transistor Q 6  has its base connected to the base of transistor Q 3A  and its emitter connected to current source I PD1 . The anode of diode D 2  is connected to the same reference voltage that is connected to the gate of MOSFET M 5 . Although diode D 2  &#39;s connection to this reference voltage is preferred, it is not necessary, and the diode could be connected to a separate voltage. In general, the reference voltage connected to the anode of diode D 2  is known as the saturation reference voltage for reasons discussed further below. 
     The base of transistor Q 2A  is connected to the drain of MOSFET M 6 , which has its gate connected to the same reference voltage as the gate of MOSFET M 5 , making MOSFET M 6  a common-gate MOSFET like MOSFET M 5 . The drain of MOSFET M 6  is connected to the collector of transistor Q 5  and the cathode of diode D 1 . The anode of diode D 1  is connected to the same reference voltage that is connected to the gate of MOSFET M 5 . However, this is not necessary. The anode could be connected to a separate saturation reference voltage as long as the anode is connected to the same voltage connected to the anode of diode D 2 . The base of transistor Q 5  is connected to the base of transistor Q 4A , and the emitter of transistor Q 5  is connected to current source I PD1 , which has a second terminal connected to lower power supply voltage V EE . 
     The pre-driver stage described above is further connected to a second pre-driver stage constructed from inverters INV 1  and INV 2 , resistors R 1  and R 2 , and transistors Q 7  and Q 8 . 
     The outputs of inverters INV 1  and INV 2  are connected to the sources of MOSFETs M 5  and M 6 , respectively. The input to inverter INV 1  is connected to one terminal of resistor R 1  and the collector of transistor Q 7 . The other terminal of resistor R 1  is connected to upper power supply voltage V CC . The input to inverter INV 2  is connected to resistor R 2  and the collector of transistor Q 8 . The other terminal of resistor R 2  is connected to upper power supply voltage V CC . The emitters of transistors Q 7  and Q 8  are connected together at one terminal of current source I PD2 , which has a second terminal connected to lower power supply voltage V EE . The base of transistor Q 7  is connected to the bases of transistors Q 5  and Q 4A , forming an input node V X . Similarly, the base of transistor Q 8  is connected to the bases of transistors Q 6  and Q 3A , forming an input node V Y . 
     Inverter INV 1  is composed of P-channel MOSFET M 9  and N-channel MOSFET M 10 . The gates and drains of MOSFETs M 9  and M 10  are connected together forming an inverter input and inverter output, respectively. The source of MOSFET M 9  is connected to upper power supply voltage V CC  and the source MOSFET M 10  is connected to the same reference voltage connected to the gates of common-gate MOSFETs M 5  and M 6 . Inverter INV 2  is composed of P-channel MOSFET M 7  and N-channel MOSFET M 8 . The gates and drains of MOSFETs M 7  and M 8  are connected together forming an inverter input and inverter output, respectively. The source of MOSFET M 7  is connected to upper power supply voltage V CC , and the source of MOSFET M 8  is connected to the same reference voltage connected to the gates of common-gate MOSFETs M 5  and M 6 . 
     In operation, when input V Y  is high relative to input V X , transistor Q 8  conducts nearly all the current created by current source I PD2  and transistor Q 7  does not conduct current. The collector current of transistor Q 8  is drawn through resistor R 2  and causes a voltage drop across resistor R 2 , resulting in a low voltage at the input to inverter INV 2 . When the input to inverter INV 2  is low, MOSFET M 8  is inactive and creates a high impedance to the reference voltage. At the same time, P-channel MOSFET M 7  is active and creates a high conductivity path to upper power supply voltage V CC , thereby causing the output of inverter INV 2  to rise to upper power supply voltage V CC . 
     Since transistor Q 7  has no collector current when V X  is low, there is no voltage drop across resistor R 1  and the input to inverter INV 1  is equal to upper power supply voltage V CC . When the input to inverter INV 1  rises toward upper power supply voltage V CC , P-channel MOSFET M 9  shuts off and creates a high impedance source-to-drain path to upper power supply voltage V CC . At the same time, N-channel MOSFET M 10  is active and creates a low impedance path to the reference voltage. Thus, the output of inverter INV 1  is at the reference voltage. 
     As discussed above, the output of inverter INV 1  is connected to the source of MOSFET M 5 . When the output of inverter INV 1  is at the same reference voltage as the gate of common-gate MOSFET M 5 , the P-channel of MOSFET M 5  is severely constricted at the source, creating a high source-to-drain impedance in MOSFET M 5 . Thus, the base of transistor Q 1A , which is at the drain of MOSFET M 5 , is separated from the reference voltage by a large impedance when V X  is low. At the same time, the high input value of input node V Y  causes transistor Q 6  to conduct a collector current nearly equal to the current created by current source I PD1 . This large collector current, combined with the high source-to-drain impedance of MOSFET M 5 , causes the voltage at the base of transistor Q 1A  to drop rapidly. The voltage reduction at the base of transistor Q 1A  is limited by diode D 2 , so that the voltage at the base of transistor Q 1A  does not drop more than approximately 0.7 volts below the saturation reference voltage. By limiting the voltage reduction at the base of transistor Q 1A , diode D 2  is able to keep transistor Q 6  from saturating. In other words, the base-collector junction of transistor Q 6  never becomes forward biased. In addition, diode D 2  keeps transistor Q 3A  from saturating by limiting the voltage drop at the base of transistor Q 1A  and thus limiting the voltage drop at the collector of transistor Q 3A . Thus, diode D 2  acts as a saturation control element. 
     Although diode D 2  is shown as a single element, those skilled in the art will recognize that resistors and/or additional diodes may be added or substituted between the saturation reference voltage and the drain of MOSFET M 5  to modify the minimum voltage allowed for the base of transistor Q 1A . In addition, as discussed above, the saturation reference voltage does not have to be the same as the common-gate reference voltage. In fact, if lower power supply voltage V EE  is lowered, the saturation reference voltage can be chosen to be much lower than the common-gate reference voltage, as long as it is still high enough, relative to V EE  and the input signals, to keep transistors Q 5 , Q 6 , Q 4A , and Q 3A  from saturating. 
     The drop in voltage at the base of transistor Q 1A  causes transistor Q 1A  to turn off and the high input value on input node V Y  causes transistor Q 3A  to turn on. With transistor Q 1A  off and transistor Q 3A  on, the voltage at the base of transistor Q 1A  determines the voltage at the terminal of the inductor connected to the emitter of transistor Q 1A . Specifically, the voltage at Q 1A  &#39;s emitter is equal to the saturation reference voltage minus the diode voltage drop across diode D 2  and a minus similar diode voltage drop across transistor Q 1A . 
     As discussed above, the output of inverter INV 2  is equal to upper power supply voltage V CC  when V Y  is high. Since inverter INV 2  &#39;s output is connected to the source of common-gate MOSFET M 6 , this high value creates a high conductivity path in MOSFET M 6  from upper power supply voltage V CC  to the base of transistor Q 2A . At the same time, the low input value of input node V X  causes transistor Q 5  to turn off, thereby keeping transistor Q 5  from pulling down the voltage at the base of transistor Q 2A . Together, the lack of current being pulled from the base of transistor Q 2A  and the high conductivity path to upper power supply voltage V CC , cause the base of transistor Q 2A  to quickly rise to nearly upper power supply voltage V CC , and thereby quickly activate transistor Q 2A . The low input value of V X  also causes transistor Q 4A  to turn off. Therefore, with V Y  high and V X  low, transistors Q 2A  and Q 3A  conduct nearly all of current I WA , and transistors Q 1A  and Q 4A  conduct no current. 
     In this embodiment, the swing voltage of inductor L A  is equal to the voltage at the emitter of transistor Q 2A  minus the voltage at the emitter of transistor Q 1A  immediately after transistor Q 2A  turns on and transistor Q 1A  turns off. At that instance, the voltage at the emitter of transistor Q 2A  is equal to upper power supply voltage V CC  minus a diode drop across transistor Q 2A . The voltage at the emitter of transistor Q 1A  is equal to the saturation reference voltage minus a diode drop across diode D 2  and minus another diode drop across transistor Q 1A . Thus, the voltage swing is equal to V CC  minus the saturation reference voltage plus a voltage drop across diode D 2 . 
     When the input values are reversed, with V X  higher than V Y , the circuit operates in a complimentary manner resulting in transistors Q 1A  and Q 4A  conducting nearly all of the current from current source I WA  and transistors Q 2A  and Q 3A  conducting no current. 
     An important feature of the present invention is that the sources and drains of MOSFET M 5  and M 6  have voltages that increase and decrease together. In fact, the source and drain voltages will not be more than about 2.5 volts apart during switching if the respective source node capacitances and drain node capacitances are approximately equal. Thus, when the output of inverter INV 2  rises to upper power supply voltage V CC , the common-gate configuration of MOSFET M 6  causes it to turn on, thereby creating a low impedance pathway to the drain of MOSFET M 6 . With the complimentary turning off of transistor Q 5 , this allows the drain voltage of MOSFET M 6  to increase with the source voltage to nearly V CC . Similarly, when the output of inverter INV 1  drops to the reference voltage, thereby lowering the voltage at the source of MOSFET M 5 , transistor Q 6  turns on and causes the voltage at the drain of MOSFET M 5  to decrease until it reaches a value equal to the saturation reference voltage minus the voltage drop across diode D 2 . Because the source and drain voltages track together in both MOSFET M 5  and MOSFET M 6 , the MOSFETs are less likely to experience a breakdown voltage between their sources and drains. This is notable since inductor L A  still experiences a swing voltage greater than V CC  minus the saturation reference voltage, and this swing voltage is typically greater than the breakdown voltage of the MOSFETs. Thus, in the present invention, the swing voltage for the inductor is independent of the breakdown voltage of the MOSFETs in the first pre-driver stage. 
     It is also notable that the maximum source-to-drain voltage seen by the MOSFETs in the inverters is less than the swing voltage across the inductor. The maximum source-to-drain voltage seen by an inverter MOSFET in the present invention is V CC  minus the common-gate reference voltage. However, the swing voltage is V CC  minus the saturation reference voltage plus at least one diode voltage drop. Thus, even if the saturation reference voltage is chosen to be the same as the common-gate reference voltage, as shown in FIG. 2, the swing voltage can be greater than the voltage across the inverter MOSFETs. In fact, if the saturation reference voltage is much lower than the common-gate reference voltage, the swing voltage can be much larger than the breakdown voltage. Thus, the swing voltage is not limited by MOSFET breakdown voltages in the present invention. 
     FIG. 3 shows a second embodiment of the second pre-driver stage of FIG. 2. For simplicity, the first pre-driver stage and the H-switch have been removed. To implement this second pre-driver stage with the first pre-driver stage and switching stage of FIG. 2, node N1 of FIG. 3 would be connected to the source of MOSFET M 6  of FIG. 2, node N2 would be connected to the source of MOSFET M 5 , node N3 would be connected to the bases of transistors Q 6  and Q 3A , and node N4 would be connected to the bases of transistors Q 5  and Q 4A . Of course, the second pre-driver stage of FIG. 3 would replace the second pre-driver stage of FIG. 2, which means replacing inverters INV 1  and INV 2 , resistors R 1  and R 2 , transistors Q 7  and Q 8 , and current source I PD2 . 
     MOSFETs M 11  and M 12  form an inverter INV 3 . The drains and gates of MOSFETs M 11  and M 12  are connected together, with the drains forming an inverter output, and the gates forming an inverter input. The source of P-channel MOSFET M 11  is connected to upper power supply voltage V CC , and the source of N-channel MOSFET M 12  is connected to the same reference voltage connected to the gates of the common-gate MOSFETs in the first pre-driver stage of FIG. 2. 
     The input to inverter INV 3  is connected to circuit elements that quickly change the voltage level at the inverter input. Transistors Q 20  and Q 24 , resistor R 11 , and diodes D 10  and D 11  quickly raise the input voltage of inverter INV 3  when input V Y  is high. Transistors Q 21  and Q 25 , resistors R 10  and R 12 , and diodes D 12  and D 13 , operate to lower the input voltage of inverter INV 3  when input V Y  is low. 
     Transistor Q 20  is a PNP transistor with its collector connected to the input of inverter INV 3 , its emitter connected to upper power supply voltage V CC , and its base connected to the anode of diode D 11  and one terminal of resistor R 11 . The other terminal of resistor R 11  is connected to upper power supply voltage V CC . Resistor R 10  is connected between the emitter and the collector of transistor Q 20 . Diode D 10  has its anode connected to the collector of transistor Q 20  and its cathode connected to the cathode of diode D 11  and the collector of NPN transistor Q 24 . The base of transistor Q 24  is connected to input V Y  and the emitter of transistor Q 24  is connected to current source I PD4 , which has a second terminal connected to lower power supply voltage V EE . 
     The input to inverter INV 3  is also connected to the collector of NPN transistor Q 21 , which has its emitter connected to the reference voltage, and its base connected to one terminal of resistor R 12  and the cathode of diode D 13 . The other terminal of resistor R 12  is connected to the reference voltage. The cathode of diode D 12  is connected to the collector of transistor Q 21 , and the anode of diode D 12  is connected to the anode of diode D 13  and the collector of PNP transistor Q 25 . The base of transistor Q 25  is connected to input V Y , and the emitter of transistor Q 25  is connected to current source I PD3 , which has a second terminal connected to upper power supply voltage V CC . 
     In operation, when V Y  is high, transistor Q 25  is inactive and prevents current flow in its collector. Since transistor Q 25  &#39;s collector is the only source of current for resistor R 12 , transistor Q 25  prevents current from flowing through resistor R 12 . With no current flowing through resistor R 12 , the base of transistor Q 21  is at the same voltage as the emitter of transistor Q 21 , and transistor Q 21  is inactive. Since transistor Q 21  does not conduct a current at its collector when it is inactive, transistor Q 21 , along with diode D 12 , create an extremely high impedance between inverter INV 3  &#39;s input and lower power supply voltage V EE . 
     While transistor Q 25  is inactive, transistor Q 24  is active. The active collector current of transistor Q 24  is partially drawn through resistor R 11 , causing a voltage drop at the base of transistor Q 20 . This voltage drop activates transistor Q 20  and causes it to act as a low impedance bypass to resistor R 10 . This low impedance path quickly raises the voltage at the gate of inverter INV 3  to V CC  minus the base-emitter voltage of transistor Q 20 . Diodes D 11  and D 10  prevent the voltage from increasing beyond this point. When the voltage is high enough, P-channel MOSFET M 11  stops conducting a source-to-drain current and N-channel MOSFET M 12  begins to conduct a source-to-drain current. The open channel of MOSFET M 12  thereby lowers the voltage at Node N1 to the reference voltage. 
     When input V Y  is low, transistor Q 24  is inactive. Since transistor Q 24  has no collector current when it is inactive, no current flows through resistor R 11  and the voltage at the base of transistor Q 20  is the same as the voltage at the emitter of transistor Q 20 . Thus transistor Q 20  is inactive and has no collector current. Further, diode D 10  is reversed biased so there is no current flowing through diode D 10 . 
     With V Y  low, transistor Q25 is active and a portion of the active collector current of transistor Q 25  passes through resistor R 12  creating sufficient voltage to turn on transistor Q 21 . The active collector current of transistor Q 21  is drawn through resistor R 10  and creates a voltage drop across resistor R 10  resulting in a low voltage at the input to inverter INV 3 . The voltage at the input to inverter INV 3  is prevented from dropping too low by diodes D 12  and D 13 , which prevent the voltage from dropping below the reference voltage plus the base-emitter voltage of transistor Q 21 . The low inverter input voltage causes N-channel MOSFET M 12  to turn off and creates a high conductivity source-to-drain path in P-channel MOSFET M 11  between upper power supply voltage V CC  and node N1. This raises the voltage at node N1 to approximately upper power supply voltage V CC . 
     Inverter INV 4  is constructed from P-channel MOSFET M 13  and N-channel MOSFET M 14 , which have their drains connected together to form an inverter output and their gates connected together to form an inverter input. The source of MOSFET M 13  is connected to upper power supply voltage V CC  and the source of MOSFET M 14  is connected to the reference voltage. The input of inverter INV 4  is connected to a circuit that is the compliment of the circuit connected to the input of inverter INV 3 . 
     Transistors Q 22  and Q 27 , resistor R 14 , and diodes D 14  and D 15  operate to increase the voltage at the inverter&#39;s input when input V X  is high. Transistor Q 22  is a PNP transistor with its collector connected to the input of inverter INV 4 , its emitter connected to upper power supply voltage V CC  and its base connected between one terminal of resistor R 14  and the anode of diode D 15 . The other terminal resistor R 14  is connected to upper power supply V CC . Diode D 14  has its anode connected to the collector of transistor Q 22  and its cathode connected to the cathode of diode D 15  and the collector of NPN transistor Q 27 . Transistor Q 27  has its emitter connected to current source I PD4  and its base connected to input V X . 
     Transistors Q 26  and Q 23 , resistors R 13  and R 15 , and diodes D 16  and D 17 , operate to lower the input voltage of inverter INV 4  when input V X  is low. Transistor Q 23  is an NPN transistor with its emitter connected to the reference voltage, its collector connected to inverter INV 4  &#39;s input, and its base connected to one terminal of resistor R 15  and the cathode of diode D 17 . The other terminal of resistor R 15  is connected to the reference voltage. Diode D 16  has its cathode connected to the input of inverter INV 4 , and its anode connected to the anode of diode D 17  and to the collector of PNP transistor Q 26 . The base of transistor Q 26  is connected to input V X , and the emitter of transistor Q 26  is connected to current source I PD3 . Resistor R 13  is connected between the emitter and collector of transistor Q 22 . 
     Inverter INV 4  and the associated circuitry used to raise and lower the input voltage of the inverter, operate in a manner identical to that explained above for inverter INV 3  and its accompanying circuitry. The only difference is that inverter INV 4  is driven by input V X  instead of V Y . Since V Y  and V X  are differential inputs, the outputs of inverters INV 3  and INV 4  will not be the same in steady state. When one output is at upper power supply voltage V CC , the other will be at the reference voltage. 
     Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.