Abstract:
An analog signal sampler with improved correlated double sampling (CDS) performance for imaging systems includes a dual mode input amplifier, a switched capacitor network and a differential amplifier. The dual mode input amplifier has a high input impedance and allows for receiving either positive-going contact image sensor (CIS) or negative-going charge couple device (CCD) image signals as desired. The switched capacitor network and differential amplifier together perform an improved CDS of the image signal and convert the unipolar input image signal to a bipolar differential output signal with an improved dynamic signal range. The CDS technique used relies upon simultaneous charging of the coupling and sample and hold capacitances with charge transfer from the coupling capacitance to the sample and hold capacitance. The gain of the sampler can be programmed by appropriate selection of the ratio of the coupling capacitance to the sample and hold capacitance.

Description:
RELATED APPLICATIONS 
     This is a Continuation-In-Part of U.S. patent application Ser. No. 60/005,807, filed Oct. 23, 1995, and entitled &#34;Imaging System Analog Signal Sampler.&#34; 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to analog signal samplers for imaging systems, and in particular, to analog signal samplers which use correlated double sampling (CDS) techniques for removing signal noise. 
     2. Description of the Related Art 
     Image sensors using charge couple devices (CCDs) are employed in many imaging applications such as scanners, digital cameras and video camcorders. As is well known in the art, CCD image sensors store analog signals as a series of discrete packets of charge. The charge stored at each cell of the CCD unit is proportional to the intensity of the light of an image incident on the area of that particular cell at a given point in time. The charge is transferred onto an output node once per sampling interval. Within each sampling interval, the previous charge at the output node is discharged to a circuit reference potential through a reset switch, thereby establishing a reference level at the output prior to each new charge transfer. Upon receiving a new charge, the output will charge to a new voltage level. A clock feedthrough appears at the output when the reset switch is turned off and the output settles to the reference level. However this reference level fluctuates due to the presence of noise having a mean square value given by kT/C. The existence of such noise limits the dynamic range of the analog image processing system. This problem is of particular concern in the more recently developed high resolution and high speed image sensors which must work with lower input charge and at much higher frequency. 
     One conventional technique for removing kT/C noise is that of correlated double sampling (CDS). This technique essentially measures the reference level of the output prior to the arrival of the new charge packet and subtracts this pre-charge level from the postcharge level. This method cancels the kT/C noise as well as suppresses low frequency noise. 
     Referring to FIG. 1, an early CDS circuit realization consists of an input buffer amplifier, a clamping circuit, a second buffer amplifier and a sample and hold stage. Following a reset pulse, when the CCD signal reaches the reference level, the clamp switch is closed briefly, thereby causing any reset noise to be stored on the coupling capacitor C CL . Following the new charge transfer, when the CCD signal settles at the new signal level, the sample switch is closed, resulting in an output voltage (across the sample and hold capacitor C SH ) equal to the difference between the reference level and the new signal level of the CCD signal. Within one pixel, the reset noise is fully correlated between clamp and sample and is, therefore, virtually eliminated. The kT/C noise is more effectively removed if the coupling capacitor C CL  is sufficiently large so that its own self-generated noise is small in comparison to the reference fluctuations on a much smaller capacitance of the floating diffusion node of the CCD. 
     Referring to FIG. 2, a circuit which eliminates the coupling capacitor C CL  also eliminates the clamp switch. In this circuit, a delay line having delay dT, which is equivalent to the time difference between the clamp and sample pulse times in the circuit of FIG. 1, stores the reference level. A differential amplifier subtracts this stored reference level from the new signal level. 
     Referring to FIG. 3, an alternative circuit replaces the delay line and the differential amplifier with a delay line terminated by a short circuit. In this circuit, the CCD output signal is supplied to the input terminal of the delay line through a resistance Z O  which is the same as the characteristic impedance of the delay line. The reflected delayed signal from the delay line is mixed with the non-delayed signal at the input of the delay line. With a proper delay time, the output signal from the sample and hold is the difference between the signal and reference level of the CCD signal. 
     By eliminating the clamping pulses, those circuits which use the delay lines are theoretically useful for high frequency applications. However, practical implementations of this approach suffer from complications resulting from signal loss and propagation dispersion. Furthermore, the delay line can not be realized in an integrated circuit (IC). 
     Referring to FIG. 4, another circuit which uses a differential average, or dual slope technique, theoretically yields the best signal-to-noise ratio for kT/C noise. The circuit consists of a buffer amplifier, a switch, an inverting amplifier and an integrator. The integrator input is connected to the output of the buffer amplifier or the inverting amplifier, or left open, depending upon the position of the three-position switch. First, the integrator is reset by closing switch position S4. Then, switch position S4 is opened and switch position S1 is closed during the reference level interval of the CCD signal, thereby allowing the inverted reference level to be integrated onto the integrating capacitor C during time t S . When the CCD signal changes to the image, or video, level, switch position S1 is opened and switch position S2 is closed, thereby connecting the integrator to the output of the buffer amplifier. The reference level plus the video level are integrated for the time t S  when switch position S3 is opened. A signal equal to the difference between the reference level and video level is then held by the integrator. However, while this circuit has a better signal-to-noise ratio, it is less suitable for high speed applications due to the slow response of the integrator. 
     Since the CCD image sensor is generally the most expensive component in an imaging system, the lower cost contact image sensor (CIS) is seeing increasing use. The CIS consists of optical source, a rod lens array, photo sensors and electronic components housed in one unit. Unfortunately, the image signal produced by a CIS is different than the one produced by a CCD sensor. This presents a new challenge to the analog signal sampler which must work with both CIS and CCD sensors. 
     SUMMARY OF THE INVENTION 
     An analog signal sampler with improved correlated double sampling (CDS) performance for imaging systems in accordance with the present invention uses improved CDS techniques to remove thermal (KT/C) noise and offsets from analog image signals received from a charge coupled device (CCD) image sensor or contact image sensor (CIS). Such a signal sampler has a high input impedance and accepts unipolar signals from CCD and/or CIS sensors and maximizes the dynamic range by providing bipolar outputs in response to such signals with a programmable signal gain. Any internal offsets generated within the sampler are removed, or nulled out, by the topography of the sampler circuit itself. 
     An analog signal sampler with improved correlated double sampling (CDS) performance in accordance with one embodiment of the present invention includes two capacitive stages and a switching stage. The first capacitive stage is for selectively receiving an analog reference signal, a switched reference signal and an analog pixel signal and in accordance therewith charging to a first coupling charge state during a reference interval, providing a first plurality of transfer charges and charging to a second coupling charge state during an active interval. The analog pixel signal includes a reference value during the reference interval and an image value during the active interval. The second capacitive stage is for receiving the first plurality of transfer charges and the switched reference signal and in accordance therewith charging to a first sampling charge state during the reference interval, charging to a second sampling charge state during a first portion of the active interval, substantially maintaining the second sampling charge state during a second portion of the active interval and providing a first output signal which, in accordance with the second sampling charge state, corresponds to a first difference between the image and reference values of the analog pixel signal. The switching stage is coupled to and between the first and second capacitive stages and is for receiving the analog reference signal and a plurality of sampling control signals and in accordance therewith coupling the first and second capacitive stages during the reference interval and the first portion of the active interval, decoupling the first and second capacitive stages during the second portion of the active interval and providing the switched reference signal. 
    
    
     These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a conventional correlated double sampling (CDS) circuit using a clamping technique. 
     FIG. 2 illustrates a conventional CDS circuit using a delay line and differential amplifier. 
     FIG. 3 illustrates a conventional CDS circuit using a delay line terminated by a short circuit. 
     FIG. 4 illustrates a conventional CDS circuit using differential average technique. 
     FIG. 5 illustrates an analog signal sampler connected to a CCD/CIS sensor though a dc restoration circuit. 
     FIG. 6 illustrates an analog signal sampler in accordance with one embodiment of the present invention. 
     FIG. 7 is a signal timing diagram for the circuit of FIG. 6. 
     FIG. 8 illustrates an analog signal sampler in accordance with another embodiment of the present invention. 
     FIG. 9 illustrates a capacitor array for use in the circuits of FIGS. 7 and 8 to provide a programmable gain. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     An analog signal sampler with improved correlated double sampling (CDS) performance for imaging systems in accordance with the present invention uses improved CDS techniques to remove thermal (KT/C) noise and offsets from analog image signals received from a charge coupled device (CCD) image sensor or contact image sensor (CIS). Such a signal sampler has a high input impedance and accepts unipolar signals from CCD and/or CIS sensors and maximizes the dynamic range by providing bipolar outputs in response to such signals with a programmable signal gain. Any internal offsets generated within the sampler are removed, or nulled out, by the topography of the sampler circuit itself. 
     Referring to FIG. 5, an analog signal sampler in accordance with the present invention is intended to be connected to the output of a CCD or CIS image sensor through a coupling capacitor C CL . The coupling capacitor C CL , in conjunction with a clamp switch, performs a DC restoration function and provides level shifting from a higher voltage (e.g. 12 volts) CCD or CIS image sensor to a lower voltage (e.g. 3-5 volts) image signal processing circuit. 
     During the reference pixel interval, the clamp switch is closed and the coupling capacitor C CL  is charged up to a voltage having a value equal to the difference between the DC level of the image sensor signal and the clamp reference voltage. (The optimum clamp reference voltage is preferably equal in value to half of the supply voltage for the sampler circuit). Subsequently, during the active pixel interval, the clamp switch is opened. Provided that the input impedance of the sampler circuit is high, the coupling capacitor C CL  holds its charge and acts as a DC level shifter for the image sensor signal, thereby shifting the DC level of the image sensor signal from its own DC level to a clamp reference level suitable for the sampler circuit. 
     Referring to FIG. 6, an analog signal sampler with improved correlated double sampling (CDS) performance in accordance with one embodiment of the present invention includes an input buffer amplifier stage, an input switching network, a switched capacitor network, a reference and sampled signal switching network, and a differential integrator. As discussed in more detail below, these elements perform a number of functions: correlated double sampling of input signals; digitally programmable signal gain; conversion of single-ended input signals to differential output signals; and conversion of unipolar output signals to bipolar output signals. 
     The input analog image pixel signal CCDIN, from either a CIS or CCD sensor, is inputted to two unity gain amplifiers composed of N-type metal oxide semiconductor field effect transistors (MOSFETs) M1 and M2, P-type MOSFET M3, and current sources I1, I2 and I3. Transistor M3 is fabricated in an isolated N-well with the N-well substrate electrode connected to the source electrode of transistor M3. Hence, with a zero volt potential existing between the source and substrate, the threshold voltage V T  of transistor M3 is not modulated by the input signal CCDIN driving its gate terminal. Therefore, the source-to-gate voltage V GS  of transistor M3 is constant regardless of the variation in the input signal CCDIN voltage, and transistor M3 and current source I3 thereby function as a unity gain buffer amplifier. 
     Transistor M1 receives the input signal CCDIN at its gate terminal and operates as a source follower. Transistor M2 operates as a diode level shifter with the output signal provided at its interconnected gate and drain terminals. Transistors M1 and M2 are fabricated in a common P-type substrate and, since the P-type substrate is normally biased to the lowest power supply potential, will be subject to threshold voltage modulation due to changes in the input signal voltage. However, this interconnection of transistors M1 and M2 causes the threshold voltage of transistor M2 to track that of transistor M1. Therefore, the gate-to-source voltage of transistor M2 tracks the gate-to-source voltage of transistor M1, thereby causing the output signal voltage to equal that of the input. Current sources I1 and I2 provide biasing current sufficient to guarantee that I1 is greater than I2, thereby preventing current starving of transistor M2. Accordingly, transistors M1 and M2 and current sources I1 and I2 function together as a unity gain buffer amplifier. 
     As noted above, the input signal CCDIN is normally received by way of a DC restoration circuit which biases the input to a clamp reference voltage, which is typically half of the power supply voltage potential. Input transistors M1 and M3 provide high input impedances as required by such DC restoration circuit. Additionally, transistor M3 and current source I3, biased between positive and negative power supply potentials VDD and VSS, respectively, provide buffering for negative-going CCD image sensor signals, while transistors M1 and M2 and current sources I1 and I2, also biased between VDD and VSS, provide buffering for positive-going CIS image sensor signals. 
     The outputs of the buffer amplifiers, appearing at the source terminal of transistor M3 and drain terminal of transistor M2, are selectively switched by switches SW1 and SW3. An input reference voltage ICM (e.g., selected to be equal to the input common mode voltage of differential operational amplifier OA1, as discussed in more detail below) is selectively switched by switches SW2 and SW4. All of these switches SW1-SW4 are controlled by input control logic signal CCD and its inverse CCDB which indicate whether the incoming image signal CCDIN is from a CIS or CCD image sensor. 
     When the input image signal CCDIN is from a CCD image sensor, control logic signal CCD is at a logic high and switches SW1 and SW2 are closed while switches SW3 and SW4, driven by the inverse signal CCDB, are open. Hence, the output signal from transistor M3 is passed by switch SW1 to capacitor array CA1, while the input reference voltage ICM is passed by switch SW2 to capacitor array CA2. 
     When the input image signal CCDIN is from a CIS image sensor, logic signal CCD is at a logic low, thereby causing switches SW1 and SW2 to be open and switches SW3 and SW4, driven by the inverse signal CCDB, to be closed. Accordingly, the buffered input signal, appearing at the drain terminal of transistor M2, is passed by switch SW3 to capacitor array CA2, while the input reference voltage ICM is passed by switch SW4 to capacitor array CA1. (As should be understood from the following discussion, this switching action of switches SW1-SW4 causes positive-going image signals to be produced at the final output of the circuit, regardless of the polarity of the input signal CCDIN). 
     Capacitor arrays CA1 and CA2, in conjunction with operational amplifier (op-amp) OA1, integrating capacitors C3 and C4, and switches SW5-SW11, function together as a switched capacitor network stage and provide correlated double sampling, programmable signal gain and bipolar differential output signals. Op-amp OA1 is preferably constructed of MOSFETs so as to provide very high input and output impedances and limited output current sinking and sourcing. 
     This switched capacitor network stage is controlled by three control logic signals: TRACK, CLAMP and CLAMPD. The CLAMPD signal is a time-delayed version of signal CLAMP. Reference voltages REFN and REFP, selectively applied to output terminals OUTP and OUTN of op-amp OA1 via switches SW9 and SW10, respectively, are high and low reference voltages, respectively, which cover the output voltage range of op-amp OA1. 
     Referring to FIGS. 6 and 7 together, operation of the switched capacitor network stage can be better understood. At time T1, when input image signal CCDIN, whether from a CIS or CCD image sensor, reaches the reference level V REF , both input logic signals TRACK and CLAMP are set at logic high levels. Accordingly, switches SW5-SW11 are closed. If operating in the CCD mode, input signal CCDIN is from a CCD image sensor and logic signal CCD is high and capacitor array CA1 charges to a voltage value equal to the difference between the image signal reference voltage V REF  and the input reference voltage ICM. Meanwhile, capacitor array CA2 has zero volts across it due to the application of the input reference voltage ICM on both of its terminals via switches SW2 and SW6. Capacitor C3 charges up to a voltage value equal to the difference between output reference voltage REFN (applied via switch SW9) and the input reference voltage ICM (applied via switches SW5 and SW7). Capacitor C4 charges to a voltage value equal to a difference between output reference voltage REFP (applied via switch SW10) and input reference voltage ICM (applied via switches SW6 and SW8). 
     At time T2, logic signal CLAMP is reset to a logic low level, thereby causing switches SW5, SW6, SW9 and SW10 to open. (Charge injection to the inverting and non-inverting terminals of op-amp OA1 from switches SW5 and SW6 turning off may cause an offset but not distortion since switches SW5 and SW6 are switching the same voltage signal off, i.e. input reference voltage ICM. If the symmetrically corresponding components of this differential circuit are perfectly matched, any such offset will be cancelled at the output. In practice, however, such components are not perfectly matched, but switch SW11 helps to minimize any such offset). A short time delay thereafter, delayed logic signal CLAMPD is also reset to a logic low, thereby causing switch SW11 to open. (Provided that the time constant based upon the on-resistance of switch SW11 and the capacitances of capacitors C3 and C4 is small compared to the time delay of signal CLAMPD, switch SW11 will balance out any charge injection from both switches SW5 and SW6, thereby minimizing any offset due to charge injection). 
     If the electrical charges being held by the capacitances at the non-inverting and inverting input terminals of op-amp OA1 are designated as q1 +   and q1 - , respectively, it can be shown that: 
     
         q1.sup.+ =(v.sub.icm -v.sub.ref)*kC+(v.sub.icm -v.sub.refn)*C(1) 
    
     
         q1.sup.- =(v.sub.icm -v.sub.refp)*C                        (2) 
    
     where: 
     kC=capacitance value of capacitor array CA1 and CA2 
     C=capacitance value of capacitors C3 and C4. 
     At time T3, the input image signal CCDIN begins changing from its reference level V REF  to a value V VIDEO  representing the new image pixel value. Accordingly, capacitor array CA1 begins acquiring new charge and the amount of such new charge transfers from capacitor array CA1 to capacitor C3. This, in turn, causes the output voltage V OUTP  at terminal OUTP of op-amp OA1 to start changing. The common mode feedback present within the op-amp OA1 senses this change and internally drives the op-amp OA1 in such a manner as to maintain the common mode output. Hence, the inverting output voltage V OUTN  at terminal OUTN of op-amp OA1 also starts changing. At time T4, the image signals reaches its new pixel value V VIDEO . At time T5, both outputs OUTP, OUTN of op-amp OA1 settle to their final values and logic signal TRACK is reset to a logic low, thereby causing switches SW7 and SW8 to open and the op-amp OA1 outputs OUTP, OUTN to hold their final values. 
     When switches SW7 and SW8 turn off (open), charges from them are injected into the inverting and non-inverting terminals, respectively, of op-amp OA1. These charges, which vary in accordance with the input signal, will cause distortion in the output signal(s) if they are not cancelled out. Such distortion can be minimized, however, by ensuring that the symmetrically corresponding components in this differential circuit are closely matched. 
     At this point in time, it can be shown that the electrical charges q2 +   and q2 -   held at non-inverting and inverting input terminals, respectively, of op-amp OA1 are as follows: 
     
         q2.sup.+ =(v.sub.inn -v.sub.video)*kC+(v.sub.inn -v.sub.outp)*C(3) 
    
     
         q2.sup.- =(v.sub.inp -v.sub.icm)*kC+(v.sub.inp -v.sub.outn)*C(4) 
    
     where: 
     V INN  =input voltage at inverting terminal of op-amp OA1 
     V INP  =input voltage at non-inverting terminal of op-amp OA1. 
     Due to charge conservation, it can be shown that: 
     
         q1.sup.+ =q2.sup.+                                         (5) 
    
     
         q1.sup.- =q2.sup.-                                         (6) 
    
     Assuming op-amp OA1 has a negligible input offset, it can be further shown that: 
     
         v.sub.inp =v.sub.inn                                       (7) 
    
     Solving Equations (1) through (7), it can be shown that: 
     
         v.sub.outp -v.sub.outn =-k*(v.sub.video -v.sub.ref)+(v.sub.refn -v.sub.refp)(8) 
    
     As can be seen from Equation (8), correlated double sampling is performed by the switched capacitor network by sampling the difference between the input signal reference V REF  and pixel V VIDEO  voltage levels for each pixel and providing a differential output V OUTP  -V OUTN . Additionally, the outputs are converted from unipolar to bipolar in accordance with a DC level shift equal to V REFN  -V REFP . The signal gain k provided is the ratio of the value of capacitor array CA1 (or CA2) to that of integrating capacitor C3 (or C4). Hence, the signal gain k is programmable in accordance with the value of capacitor arrays CA1 and CA2. 
     Equation (7) above assumes that the input offset for op-amp OA1 is negligible. However, if the input offset voltage V OFFSET  of op-amp OA1 is included (i.e. v inp  =v inn  +v offset ), it can be shown that: 
     
         v.sub.outp -v.sub.outn =-k*(v.sub.video -v.sub.ref)+(v.sub.refn -v.sub.refp)+(k+1)*v.sub.offset                           (9) 
    
     As shown in Equation (9), the output offset, (k+1)*V OFFSET , changes with signal gain. This will create output distortion if the gain changes at the pixel rate. 
     Referring to FIG. 8, an alternative signal sampler includes a input buffer amplifier stage, input switching stage and capacitor arrays, as discussed above for the circuit of FIG. 6, but uses a different configuration of switches between the capacitor arrays CA1, CA2 and op-amp OA1. For example, switches SW9 and SW10 are connected in parallel with integrating capacitors C3 and C4 instead of connecting between op-amp OA1 outputs OUTP and OUTN and reference voltages REFN and REFP, respectively. Also, switches SW5, SW6 and SW11 are eliminated. Four additional switches SW13-SW16 and two additional capacitors C5, C6 are included. Capacitors C5 and C6 have capacitance values equal to those of capacitors C3 and C4. The control timing of this circuit is similar to that for the circuit shown in FIG. 6, and it can be shown that: 
     
         q1.sup.+ =(v.sub.inn -v.sub.ref)*kC+(v.sub.inn -v.sub.icm)*C(10) 
    
     
         q1.sup.- =(v.sub.inp -v.sub.icm)*kC+(v.sub.inp -v.sub.icm)*C(11) 
    
     
         q2.sup.+ =(v.sub.inn -v.sub.video)*kC+(v.sub.inn -v.sub.refp)*C+(v.sub.inn -v.sub.outp)*C                                            (12) 
    
     
         q2.sup.- =(v.sub.inp -v.sub.icm)*kC+(v.sub.inp -v.sub.refn)*C+(v.sub.inp -v.sub.outn)*C                                            (13) 
    
     
         v.sub.outp -v.sub.outn =-k*(v.sub.video -v.sub.ref)+(v.sub.refn -v.sub.refp)-V.sub.offset                                 (14) 
    
     As shown in Equation (10), the output offset voltage for this circuit does not vary with signal gain. Hence, the offset will not create distortion in applications where the gain is switching at a pixel rate. However, one requirement for this circuit is that the input and output common mode operations of the op-amp OA1 must be the same. 
     Referring to FIG. 9, a capacitor array suitable for use as capacitor arrays CA1 and CA2 includes an array of capacitors C1-C5 which are selectively interconnected by switches SW1-SW4 which, in turn, are controlled by logic gates I1-I10. Two binary input control signals B0 and B1 are decoded by the logic gates I1-I10 to generate four control signals S0-S3 and their complementary control signals S0B-S3B. Any logic high level of control signals S0-S3 will connect its corresponding capacitor (C2-C5) in parallel with primary capacitor C1. Hence, the value of this capacitor array, and thus the signal gain, as discussed above, is determined by the two logic control signals B0 and B1. 
     The above-discussed signal switches SW1-SW16 are preferably constructed as transmission gates by connecting N-type and P-type MOSFETs in parallel with interconnected drain terminals and interconnected source terminals. One of the device gate terminals is connected to the input control logic signal, while the gate terminal of the other device is connected to the logical inverse of such signal. For purposes of simplicity, the above-discussed switches have been discussed and shown as receiving one input control logic signal. However, it should be understood that such signal can be considered as representing the application of both the control logic signal and its inverse, or alternatively, it should be understood that inversion of the input logic signal is accomplished within the switch assembly itself. 
     Various other modifications and alterations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.