Abstract:
A back-gated field effect transistor (FET) includes a substrate, the substrate comprising top semiconductor layer on top of a buried dielectric layer on top of a bottom semiconductor layer; a front gate located on the top semiconductor layer; a channel region located in the top semiconductor layer under the front gate; a source region located in the top semiconductor layer on a side of the channel region, and a drain region located in the top semiconductor layer on the side of the channel region opposite the source regions; and a back gate located in the bottom semiconductor layer, the back gate configured such that the back gate abuts the buried dielectric layer underneath the channel region, and is separated from the buried dielectric layer by a separation distance underneath the source region and the drain region.

Description:
FIELD 
       [0001]    This disclosure relates generally to the field of field effect transistor (FET) fabrication, and more specifically to formation of a FET having a back gate. 
       DESCRIPTION OF RELATED ART 
       [0002]    In order to be able to make integrated circuits (ICs), such as memory, logic, and other devices, of a higher integration density than is currently feasible, field effect transistor (FET) dimensions must be scaled down, as FETs are an important component of many ICs. However, as FET dimensions are scaled down, FETs may suffer from various problems. In particular, interactions between the source and drain of the FET may degrade the ability to control whether the FET is on or off, which may result in memory or logic errors during IC operation. As the FET size is reduced, the distance between source and drain regions of the FET is decreased, leading to increased interaction with the channel by the source and drain, and reduced gate control of the channel. This phenomenon is referred to as the short channel effect. It becomes increasingly more difficult to control short channel effects by conventional techniques as FETs become smaller. 
         [0003]    An evolution beyond the standard FET with a single top gate that controls the FET channel, is the double-gated FET, wherein the channel is confined between a top and a bottom gate. Positioning the channel between a top and a bottom gate allows for control of the channel by the two gates from both sides of the channel, reducing short channel effects. Further, a double-gated FET may exhibit higher transconductance and reduced parasitic capacitance as compared to a single-gated FET. The presence of the back gate allows enhanced for on-chip power management and device tuning. Multiple threshold voltage (Vt) devices may also be achieved on a single IC chip by applying different back biases at the back gates of various devices. However, the back gate may be formed as a flat layer located underneath both the FET channel and source/drain regions at a uniform depth. This proximity of the back gate to the FET source and drain regions may cause unwanted parasitic capacitance between the source/drain regions and the back gate of a double-gated FET. 
       SUMMARY 
       [0004]    In one aspect, a back-gated field effect transistor (FET) includes a substrate, the substrate comprising top semiconductor layer on top of a buried dielectric layer on top of a bottom semiconductor layer; a front gate located on the top semiconductor layer; a channel region located in the top semiconductor layer under the front gate; a source region located in the top semiconductor layer on a side of the channel region, and a drain region located in the top semiconductor layer on the side of the channel region opposite the source regions; and a back gate located in the bottom semiconductor layer, the back gate configured such that the back gate abuts the buried dielectric layer underneath the channel region, and is separated from the buried dielectric layer by a separation distance underneath the source region and the drain region. 
         [0005]    In one aspect, a method of forming a back-gated FET includes forming a first ground plate in a bottom semiconductor layer of a substrate, the substrate comprising a top semiconductor layer on top of a buried dielectric layer on top of a bottom semiconductor layer; forming a dummy gate over the top semiconductor layer; forming a channel region in the top semiconductor layer; forming a source region located in the top semiconductor layer on a side of the channel region, and forming a drain region located in the top semiconductor layer on the side of the channel region opposite the source regions; forming a top dielectric layer over the source and drain regions; removing the dummy gate to form a gate opening; implanting with dopants a portion of the bottom semiconductor layer located underneath the channel region through the gate opening; annealing the implanted portion of the bottom semiconductor layer to form a second ground plate, wherein the first and second ground plate together form a back gate of the FET; and forming a front gate in the gate opening. 
         [0006]    In one aspect, a method of forming a back-gated FET includes forming a channel region in a top semiconductor layer of a substrate, the substrate comprising a top semiconductor layer on top of a buried dielectric layer on top of a bottom semiconductor layer; forming a source region located in the top semiconductor layer on a side of the channel region, and forming a drain region located in the top semiconductor layer on the side of the channel region opposite the source regions; forming a front gate over the channel region on the top semiconductor layer; implanting with dopants a portion of the bottom semiconductor layer through the front gate, channel region, and source and drain regions; and annealing the implanted portion of the bottom semiconductor layer to form a back gate of the FET. 
         [0007]    Additional features are realized through the techniques of the present exemplary embodiment. Other embodiments are described in detail herein and are considered a part of what is claimed. For a better understanding of the features of the exemplary embodiment, refer to the description and to the drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0008]    Referring now to the drawings wherein like elements are numbered alike in the several FIGURES: 
           [0009]      FIG. 1  illustrates an embodiment of a gate-last method of forming a FET with a self-aligned back gate. 
           [0010]      FIG. 2  illustrates an embodiment of an extremely thin silicon-on-insulator (ETSOI) substrate after formation of a ground plate. 
           [0011]      FIG. 3  illustrates an embodiment of the device of  FIG. 2  after formation of a dummy gate, spacer, and raised source/drain regions. 
           [0012]      FIG. 4  illustrates an embodiment of the device of  FIG. 3  after dielectric deposition and planarization. 
           [0013]      FIG. 5  illustrates an embodiment of the device of  FIG. 4  during implantation after removal of the dummy gate. 
           [0014]      FIG. 6  illustrates an embodiment of the device of  FIG. 5  after annealing to form the back gate and formation of the front gate to form a FET with a self-aligned back gate. 
           [0015]      FIG. 7  illustrates an embodiment of a gate-first method of forming a FET with a self-aligned back gate. 
           [0016]      FIG. 8  illustrates an embodiment of an ETSOI substrate. 
           [0017]      FIG. 9  illustrates an embodiment of the device of  FIG. 8  after formation of a gate, spacer, and source/drain regions on the substrate. 
           [0018]      FIG. 10  illustrates an embodiment of the device of  FIG. 9  during implantation. 
           [0019]      FIG. 11  illustrates an embodiment of the device of  FIG. 10  after annealing to form the self-aligned back gate. 
           [0020]      FIG. 12  illustrates an embodiment of the device of  FIG. 11  after formation of raised source and drain regions to form a FET with a self-aligned back gate. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    Embodiments of a FET with a self-aligned back gate, and a method of forming a FET with a self-aligned back gate, are provided, with exemplary embodiments being discussed below in detail. A FET device having a front gate and a back gate that is self-aligned to the front gate may be fabricated in a bottom semiconductor layer of an extremely thin silicon-on-insulator (ETSOI) substrate having a thin buried insulating (dielectric) layer over a bottom semiconductor layer. The back gate may be formed by implantation in the bottom semiconductor layer, and shaped such that the back gate abuts the thin buried dielectric layer underneath the channel region of the FET, allowing control of the channel region by the back gate, while being located deeper in the bottom silicon under the source/drain regions, thereby reducing parasitic capacitance between the source/drain regions and the back gate. A FET with a self-aligned back gate may be formed by either a gate-last method, in which the FET front gate is formed after an activation anneal of the device (discussed below with respect to  FIGS. 1-6 ), or a gate-first method, in which the FET front gate is formed before the activation anneal (discussed below with respect to  FIGS. 7-12 ). 
         [0022]      FIG. 1  illustrates an embodiment of a gate-last method  100  of forming a FET with a self-aligned back gate.  FIG. 1  is discussed with reference to  FIGS. 2-6 . In block  101 , a first ground plate  202  is formed in a bottom semiconductor layer ( 201  and  203 ) of ETSOI substrate  200 , as shown in  FIG. 2 . Substrate  200  comprises bottom semiconductor layer  201 / 203 , thin buried dielectric layer  204  (e.g., buried oxide), and ETSOI layer  205 , which comprises a top semiconductor layer. First ground plate  202  comprises a layer of doped semiconductor; the dopants used to form ground plate  202  may comprise any appropriate n-type or p-type dopants, including but not limited to arsenic (As), boron (B), phosphorus (P), or indium (In). The first ground plate  202  may be formed either during fabrication of substrate  200 , or by implanting the bottom semiconductor layer  201 / 203  of substrate  200  with dopants after fabrication of substrate  200 . Thin buried dielectric layer  204  may be between about 10 nanometers (nm) to about 30 nm thick in some embodiments; thin buried dielectric layer  204  may also be greater than 30 nm or less than 10 nm thick in other embodiments. 
         [0023]    The ETSOI layer  205  may comprise any semiconducting material including, but not limited to: silicon (Si), strained Si, silicon carbide (SiC), silicon germanium (SiGe), silicon germanium carbon (SiGeC), Si alloys, germanium (Ge), Ge alloys, gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP), or any combination thereof. The ETSOI layer  205  may be thinned to a desired thickness by planarization, grinding, wet etch, dry etch or any combination thereof. In one embodiment, the ETSOI layer  205  may have a thickness ranging from 1.0 nm to 10.0 nm. In another embodiment, the ETSOI layer  205  may have a thickness ranging from 1.0 nm to 5.0 nm. In a further embodiment, the ETSOI layer  205  may have a thickness ranging from 3.0 nm to 8.0 nm. The bottom semiconductor layer  201 / 203  may comprise a semiconducting material, including but not limited to: Si, strained Si, SiC, SiGe, SiGeC, Si alloys, Ge, Ge alloys, GaAs, InAs, or InP, as well as other III/V and II/VI compound semiconductors. The thin buried dielectric layer  204  may be formed by implanting a high-energy dopant into the substrate  200 , and then annealing the structure to form the buried dielectric layer  204 . In another embodiment, the thin buried dielectric layer  204  may be deposited or grown on bottom semiconductor layer  201 / 203  prior to the formation of the ETSOI layer  205 . In yet another embodiment, the substrate  200  may be formed using wafer-bonding techniques, where a bonded wafer pair is formed utilizing glue, adhesive polymer, or direct bonding. 
         [0024]    In block  102 , a channel  301 , source/drain regions  302 A-B, raised source/drain (RSD) regions  303 A-B, dummy gate  304 , and spacer  305  are formed on the device  200  of  FIG. 2 , resulting in device  300  as shown in  FIG. 3 . Channel  301  and source/drain regions  302 A-B are formed from ETSOI layer  205 . Channel region  301  may comprise undoped semiconductor, and source/drain regions  302 A-B may comprise doped semiconductor in some embodiments. Spacer  305  may comprise nitride in some embodiments. 
         [0025]    The dummy gate  304  may be formed using deposition, photolithography and selective etch processes. In one embodiment, a gate layer stack is formed on ETSOI layer  205  by depositing at least one dummy gate dielectric layer (e.g., silicon oxide formed by thermal oxidation) on the ETSOI layer  205 , and then depositing a second dummy gate layer (e.g., polysilicon or silicon nitride) on the dummy gate dielectric layer. The gate layer stack is then patterned and etched to form the dummy gate  304 . 
         [0026]    The RSD regions  303 A-B may comprise an epitaxially formed material, and have a thickness ranging from 5 nm to 80 nm, as measured from the upper surface of the ETSOI layer  205 . In another embodiment, each of the RSD regions  303 A-B may have a thickness ranging from 10 nm to 50 nm, as measured from the upper surface of the ETSOI layer  205 . 
         [0027]    The RSD regions  303 A-B may be selectively formed in direct contact with the ETSOI layer. The RSD regions  303 A-B may be formed using an epitaxial growth process. As used herein, the terms “epitaxially formed”, “epitaxial growth” and/or “epitaxial deposition” mean the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has the same crystalline characteristics as the semiconductor material of the deposition surface. When the chemical reactants are controlled and the system parameters set correctly, the depositing atoms arrive at the surface of the ETSOI layer  205  with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Thus, an epitaxial film deposited on a {100} crystal surface will take on a {100} orientation. If, on the other hand, the wafer surface has an amorphous surface layer, possibly the result of implanting, the depositing atoms have no surface to align to, resulting in the formation of polysilicon instead of single crystal silicon. 
         [0028]    The RSD regions  303 A-B may be provided by selective growth of silicon. The silicon may be single crystal, polycrystalline or amorphous. The RSD regions  303 A-B may comprise epitaxial silicon. The RSD regions  303 A-B may also be formed by selective growth of germanium. The germanium may be single crystal, polycrystalline or amorphous. In another example, the RSD regions  303 A-B may comprise SiGe. 
         [0029]    A number of different sources may be used for the selective deposition of silicon. Silicon sources for growth of silicon (epitaxial or polycrystalline) include silicon tetrachloride, dichlorosilane (SiH2Cl2), and silane (SiH4). The temperature for epitaxial silicon deposition typically ranges from 550° C. to 900° C. Higher temperature typically results in faster deposition; the faster deposition may result in crystal defects and film cracking. In one embodiment, the RSD regions  303 A-B each have a tapered portion that extends from the sidewall spacers  305 . 
         [0030]    The RSD regions  303 A-B are doped with a dopant having a same conductivity as the underlying source/drain regions  303 A-B. For example, and in the embodiments in which the source/drain regions  302 A-B are doped to a p-type conductivity, the RSD regions  303 A-B are also doped to a p-type conductivity. In the embodiments in which the source/drain regions  302 A-B are doped to an n-type conductivity, the RSD regions  303 A-B are doped to a n-type conductivity. The dopant may be introduced in-situ during the epitaxial growth process that forms the RSD regions  303 A-B. In another embodiment, the dopant may be introduced using ion implantations following the epitaxial growth process that deposits the semiconductor material of the RSD regions  303 A-B. Resulting dopant concentrations for the RSD regions  303 A-B may range from 2×1019 dopant atoms per cubic centimeter to 5×1021 dopant atoms per cubic centimeter in some embodiments. 
         [0031]    In block  103 , a top dielectric layer  401  (e.g., oxide), as shown in  FIG. 4 , is formed over the device  300  of  FIG. 3 . Top dielectric layer  401  is formed by deposition of a dielectric material over the top of device  300 , and planarizing the deposited dielectric to expose the top of dummy gate  304 . Then, in block  104 , dummy gate  304  is removed from device  400  of  FIG. 5 . Dummy gate  304  may be removed in any appropriate manner that does not damage channel  301 , top dielectric layer  401 , and spacers  305 . Then, silicon layer  203  is implanted with dopants  501  through the gate opening left by the removal of dummy gate  304 , as shown in  FIG. 5 . Dopants  501  may include but are not limited to As, B, P, or In; dopants  501  may be selected to be the same as, or of the same type (n-type or p-type) as the dopants used to form ground plate  202  in block  101 . Dopants  501  form an implanted region in silicon layer  203  underneath channel  301 . Top dielectric layer  401  prevents the dopants  501  from implanting the portion of silicon  203  located underneath dielectric layer  401 , RSD regions  303 A-B, and source/drain regions  302 A-B. 
         [0032]    In block  105 , the device  500  of  FIG. 5  is annealed to activate the implanted dopants  501  in silicon layer  203 , forming second ground plate  601  as shown in  FIG. 6 . The anneal may comprise a laser anneal, flash anneal, spike anneal, or any suitable combination of those anneal techniques, in some embodiments. Then, after the anneal of block  105 , a front gate comprising gate dielectric layer  603  and gate conducting layer  602  is formed in the gate opening. Device  600  comprises a FET having a self-aligned back gate comprising first ground plate  202 , which directly abuts thin buried dielectric layer  204  under channel region  301 , and second ground plate  601 . Because the portion of the back gate comprising second ground plate  601  is not formed under the source/drain regions  302 A-B, FET  600  may have a relatively low parasitic capacitance as compared to a FET device having a flat back gate underneath both the channel and source/drain regions. There may be a separation distance of about 20 nanometers to about 70 nanometers in bottom semiconductor layer  203  between the ground plate  202  portion of the back gate and the bottom of thin buried dielectric layer  204  underneath the source/drain regions  302 A-B in some embodiments. 
         [0033]    In one embodiment, the gate dielectric layer  603  may include, but is not limited to, an oxide, nitride, oxynitride and/or silicates including metal silicates, aluminates, titanates and nitrides. In one example, when the gate dielectric layer  603  is comprised of an oxide, the oxide may be selected from the group including, but not limited to, SiO2, HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3, LaAlO3, Y2O3 and mixture thereof. In another embodiment, the gate dielectric layer  603  is composed of a nitride, such as silicon nitride. The physical thickness of the gate dielectric layer  603  may vary, but typically, the gate dielectric layer  603  has a thickness ranging from 1 nm to 10 nm. In another embodiment, the gate dielectric layer  603  has a thickness ranging from 1 nm to 3 nm. The gate dielectric layer  603  may be formed using any of several deposition and growth methods, including but not limited to, thermal or plasma oxidation or nitridation methods, chemical vapor deposition methods and physical vapor deposition methods. 
         [0034]    The gate conducting layer  602  may be composed of conductive materials including, but not limited to, metals, metal alloys, metal nitrides and metal silicides, as well as laminates thereof and composites thereof. In one embodiment, the gate conducting layer  602  may be any conductive metal including, but not limited to, tungsten (W), nickel (Ni), titanium (Ti), molybdenum (Mo), tantallum (Ta), copper (Cu), platinum (Pt), silver (Ag), gold (Au), ruthenium (Ru), iridium (Ir), rhodium (Rh), and rhenium (Re), and alloys that include at least one of the aforementioned conductive elemental metals. The gate conducting layer  602  may also comprise doped polysilicon and/or polysilicon-germanium alloy materials (i.e., having a dopant concentration from 1×1018 to 1×1022 dopant atoms per cubic centimeter) and polycide materials (doped polysilicon/metal silicide stack materials). The gate conducting layer  602  may be composed of the same material or different materials. The gate conducting layer  602  may be formed using a deposition method including, but not limited to, salicide methods, atomic layer deposition methods, chemical vapor deposition methods and physical vapor deposition methods, such as, but not limited to, evaporative methods and sputtering methods. Although the gate conducting layer  602  is depicted in  FIG. 6  as being a single layer, embodiments have been contemplated in which the gate conducting layer  602  are each a multi-layered structure of conductive materials. 
         [0035]      FIG. 7  illustrates an embodiment of a gate-first method  700  of forming a FET with a self-aligned back gate.  FIG. 7  is discussed with reference to  FIGS. 8-12 . In block  701 , a substrate  800  as shown in  FIG. 8  is provided, comprising bottom semiconductor layer  801 , thin buried dielectric layer  802  (e.g., buried oxide), and ETSOI layer  803 , which comprises a top semiconductor layer. Thin buried dielectric layer  802  may be between about 10 nanometers and about 30 nanometers thick in some embodiments. 
         [0036]    The ETSOI layer  803  may comprise any semiconducting material including, but not limited to: silicon (Si), strained Si, silicon carbide (SiC), silicon germanium (SiGe), silicon germanium carbon (SiGeC), Si alloys, germanium (Ge), Ge alloys, gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP), or any combination thereof. The ETSOI layer  803  may be thinned to a desired thickness by planarization, grinding, wet etch, dry etch or any combination thereof. In one embodiment, the ETSOI layer  803  may have a thickness ranging from 1.0 nm to 10.0 nm. In another embodiment, the ETSOI layer  803  may have a thickness ranging from 1.0 nm to 5.0 nm. In a further embodiment, the ETSOI layer  803  may have a thickness ranging from 3.0 nm to 8.0 nm. The bottom semiconductor layer  801  may comprise a semiconducting material, including but not limited to: Si, strained Si, SiC, SiGe, SiGeC, Si alloys, Ge, Ge alloys, GaAs, InAs, or InP, as well as other III/V and II/VI compound semiconductors. The thin buried dielectric layer  802  may be formed by implanting a high-energy dopant into the substrate  800 , and then annealing the structure to form the buried dielectric layer  802 . In another embodiment, the thin buried dielectric layer  802  may be deposited or grown on bottom semiconductor layer  801  prior to the formation of the ETSOI layer  803 . In yet another embodiment, the substrate  800  may be formed using wafer-bonding techniques, where a bonded wafer pair is formed utilizing glue, adhesive polymer, or direct bonding. 
         [0037]    In block  702 , a channel region  901 , source/drain regions  902 A-B, a gate comprising gate conducting layer  903  and gate dielectric layer  904 , and a spacer  905  are formed on substrate  800 , resulting in device  900  as shown in  FIG. 9 . Channel region  901  and source/drain regions  902 A-B are formed in ETSOI layer  803 . Channel region  901  may comprise undoped semiconductor, and source/drain regions  902 A-B may comprise doped semiconductor in some embodiments. Spacer  905  may comprise nitride in some embodiments. The gate, comprising gate conducting layer  903  and gate dielectric layer  904 , may be about 30 nanometers to about 50 nanometers high in some embodiments. 
         [0038]    In one embodiment, the gate dielectric layer  904  may include, but is not limited to, an oxide, nitride, oxynitride and/or silicates including metal silicates, aluminates, titanates and nitrides. In one example, when the gate dielectric layer  904  is comprised of an oxide, the oxide may be selected from the group including, but not limited to, SiO2, HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3, LaAlO3, Y2O3 and mixture thereof. In another embodiment, the gate dielectric layer  904  is composed of a nitride, such as silicon nitride. The physical thickness of the gate dielectric layer  904  may vary, but typically, the gate dielectric layer  904  has a thickness ranging from 1 nm to 10 nm. In another embodiment, the gate dielectric layer  904  has a thickness ranging from 1 nm to 3 nm. The gate dielectric layer  904  may be formed using any of several deposition and growth methods, including but not limited to, thermal or plasma oxidation or nitridation methods, chemical vapor deposition methods and physical vapor deposition methods. 
         [0039]    The gate conducting layer  903  may be composed of conductive materials including, but not limited to, metals, metal alloys, metal nitrides and metal silicides, as well as laminates thereof and composites thereof. In one embodiment, the gate conducting layer  903  may be any conductive metal including, but not limited to, tungsten (W), nickel (Ni), titanium (Ti), molybdenum (Mo), tantallum (Ta), copper (Cu), platinum (Pt), silver (Ag), gold (Au), ruthenium (Ru), iridium (Ir), rhodium (Rh), and rhenium (Re), and alloys that include at least one of the aforementioned conductive elemental metals. The gate conducting layer  903  may also comprise doped polysilicon and/or polysilicon-germanium alloy materials (i.e., having a dopant concentration from 1×1018 to 1×1022 dopant atoms per cubic centimeter) and polycide materials (doped polysilicon/metal silicide stack materials). The gate conducting layer  903  may be composed of the same material or different materials. The gate conducting layer  903  may be formed using a deposition method including, but not limited to, salicide methods, atomic layer deposition methods, chemical vapor deposition methods and physical vapor deposition methods, such as, but not limited to, evaporative methods and sputtering methods. Although the gate conducting layer  903  is depicted in  FIGS. 9-12  as being a single layer, embodiments have been contemplated in which the gate conducting layer  903  are each a multi-layered structure of conductive materials. 
         [0040]    In block  703 , the device  900  of  FIG. 9  is implanted with dopants  1001  as shown in  FIG. 10 . Dopants  1001  form an implanted region in bottom semiconductor layer  801 . Dopants  1001  may include but are not limited to arsenic (As), boron (B), phosphorus (P), or indium (In); the type of dopants used for dopants  1001  are selected based on whether the finished FET is n-type or p-type. Dopants  1001  are driven deeper into in bottom semiconductor layer  801  under source/drain regions  902 A-B than under the gate (comprising gate conducting layer  903  and gate dielectric layer  904 ) because of the difference in height between source/drain regions  902 A-B and the gate. 
         [0041]    In block  704 , the implanted device  1000  of  FIG. 10  is annealed to form back gate  1101  in bottom semiconductor layer  801 . The stair-step shape of back gate  1101  is due to the difference in implantation depth under the source/drain regions  902 A-B versus under the gate comprising gate conducting layer  903  and gate dielectric layer in block  703 . In block  705 , RSD regions  1201 A-B are formed on source/drain regions  902 A-B, resulting in FET  1200  with self aligned back gate  1101 . RSD regions  1201 A-B may be formed using any of the materials and techniques discussed above with respect to RSD regions  303 A-B. Because the back gate  1101  is farther away from the source/drain regions  902 A-B, there is reduced parasitic capacitance between source/drain regions  902 A-B and back gate  1101  as compared to a FET device having a flat back gate underneath the channel and source/drain regions. There may be a separation distance of about 20 nanometers to about 70 nanometers in bottom semiconductor layer  801  between the back gate  1101  and the bottom of buried dielectric layer  802  underneath the source/drain regions  902 A-B in some embodiments; this separation distance may vary with the height of the gate comprising gate conducting layer  903  and gate dielectric layer  904 . 
         [0042]    The technical effects and benefits of exemplary embodiments include formation of a FET device having a back gate that is self-aligned to the front gate by implantation. 
         [0043]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0044]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.