Abstract:
Some embodiments regard a method comprising: using an input voltage to generate an output voltage having a first voltage level; in a first period, when the output voltage changes from the first voltage level to a second voltage level, storing electrical charges resulted from the output voltage changing from the first voltage level to the second voltage level; and in a second period subsequent to the first period when the output voltage demands energy, using a voltage generated from the stored electrical charges in place of the input voltage to generate the output voltage.

Description:
FIELD 
       [0001]    The present disclosure is generally related to saving energy, and, in some embodiments, the energy saving is used in multi-color Light-Emitting Diode (LED) backlights or displays. 
       BACKGROUND 
       [0002]    RGB (red, green, blue) LED backlights are commonly used to increase the gamut range of LED-backlit LCD televisions. Such RGB LEDs can also be used to directly display images in LED televisions (LED TVs). Each R, B, or G light or diode, however, requires a different turn-on voltage (e.g., the forward-bias voltage). As a result, when a same driving voltage is used to bias all R, G, and B LEDs in the same circuit, the R LEDs appear to consume much more power than the G and B LEDs. Various approaches use different techniques to reduce power consumption, but increase the size and cost for printed-circuit boards (PCBS) having the LEDs, due to additional components/circuitry. For example, one approach that uses three power converters, one for each R, G, and B LED also uses three inductors and numerous external components. Another approach uses a parallel driving structure, but with a complex transformer and two inductors. Another approach uses a single converter, but also uses a pulse-width modulator (PWM) current controller that consumes high power. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0003]    The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description, drawings, and claims. 
           [0004]      FIG. 1  is a schematic diagram of a circuit that uses some embodiments. 
           [0005]      FIG. 2  is a graph of waveforms related to some signals in the circuit of  FIG. 1 , in accordance with some embodiments. 
           [0006]      FIG. 3  is a schematic diagram of the circuit in  FIG. 1  in a boost mode, in accordance with some embodiments. 
           [0007]      FIG. 4  is a graph of waveforms illustrating the relationship of some signals of the circuit in  FIG. 3 , in accordance with some embodiments. 
           [0008]      FIG. 5  is a schematic diagram of the circuit in  FIG. 1  in an energy recycle mode, in accordance with some embodiments. 
           [0009]      FIG. 6  is a graph of waveforms illustrating the relationship of some signals of the circuit in  FIG. 5 , in accordance with some embodiments. 
           [0010]      FIG. 7  is a schematic diagram of the circuit in  FIG. 1  in a silence mode, in accordance with some embodiments. 
           [0011]      FIG. 8  is a schematic diagram of the circuit in  FIG. 1  in an energy transfer mode, in accordance with some embodiments. 
           [0012]      FIG. 9  is a graph of waveforms illustrating an operation of the circuit in  FIG. 1 , in accordance with some embodiments. 
           [0013]      FIG. 10  is a flow chart illustrating a method related to the circuit in  FIG. 1 , in accordance with some embodiments. 
           [0014]      FIG. 11  is a graph of waveforms illustrating an advantage of the circuit in  FIG. 1 , in accordance with some embodiments. 
       
    
    
       [0015]    Like reference symbols in the various drawings indicate like elements. 
       DETAILED DESCRIPTION 
       [0016]    Embodiments, or examples, illustrated in the drawings are now being disclosed using specific language. It will nevertheless be understood that the embodiments and examples are not intended to be limiting. Any alterations and modifications in the disclosed embodiments, and any further applications of the principles disclosed in this document are contemplated as would normally occur to one of ordinary skill in the pertinent art. Reference numbers may be repeated throughout the embodiments, but they do not require that feature(s) of one embodiment apply to another embodiment, even if they share the same reference number. 
       EXEMPLARY CIRCUIT 
       [0017]      FIG. 1  is a diagram of an exemplary circuit  100  that uses some embodiments. Circuit  100  can be called a power converter, a power driver, etc. In some embodiments, circuit  100  operates in a cycle including a first boost mode, an energy recycling mode, a silence mode, an energy transfer mode, and a second boost mode. Voltage V IN  is a DC voltage around 12V. Additionally, when current I L  switches in the positive domain, current I L  flows in the direction from node V IN  towards node V O , e.g., direction D IO , and in the direction from node V O  towards node V IN , e.g., direction D OI  when current I L  switches in the negative domain. For illustration, the symbol |I L | refers to the amplitude of current I L . 
         [0018]    Active diode M R  controls the current flow between nodes V IN  and V CR . When voltage V IN  is greater than voltage V CR , diode M R  turns on allowing current to flow from node V IN  to node V CR . But when voltage V IN  is lesser than voltage V CR  diode M R  turns off and thus electrically disconnects node V IN  from node V CR . When diode M R  is on, voltage V CR  is lower than voltage V IN , the voltage drop across diode M R , which, in some embodiments, is about 0.2V. In some embodiments, diode M R  is turned on/off automatically based on the relationship between voltages V IN  and V CR . For example, initially in the first boost mode during a display of one or more LEDs of a first color, e.g., the B LED (blue LED), when there is no current I L , voltage V CR  is 0V, V IN  at about 12V is greater than V CR  and thus turns on diode M R . Current I L  then flows. But when current I L  increases causing V CR  to increase until V CR  is greater than V IN  diode M R  turns off. Active diode M R  is used for illustration only, a conventional diode or equivalent circuitry can be used. 
         [0019]    Capacitor or energy tank C R  stores energy when output voltage V O  drops (e.g., from 40V to 26V) and increases voltage V CR  in the energy recycle mode. After the energy is recycled, it is later used, e.g., to drive the LEDs. For example, in the energy-transfer mode, voltage V CR  representing the stored energy is used to drive one or more LEDs of a second color, e.g., the G LED (green LED). Without this saved energy that generates voltage V CR , voltage V IN  would be used. Because voltage V CR  instead of voltage V IN  is used, energy is saved. 
         [0020]    Resistor R S  is used to sense inductor current I L . Circuit CS, based on current I L  flowing through resistor R S , generates signal (e.g., voltage) C SE  based on which current direction controller I CTRL  generates signals C ML  and C MH  to turn on/off powered NMOS transistors M L  and M H . In some embodiments, the magnitude of voltage C SE  (e.g., |C SE |) is proportional to the magnitude of current I L . Further, when current I L  is positive, voltage C SE  is positive, but when current I L  is negative, voltage C SE  is negative. The magnitude of current I L  (e.g., whether increasing or decreasing) depends on which of the two powered NMOS M L  or M H  is turned on. In effect, signal O CMP1  generated by amplifier CMP 1  having voltage C SE  as an input limits the current I L  when |C SE | is greater than signal |O EA1 |. Voltage C SE  together with circuit ZCD is also used to detect the zero current condition of current I L  (e.g., when |I L | has decreased to zero from a positive current or increases to zero from a negative current). When current I L  is zero, voltage C SE  is zero. Zero current detector ZCD recognizing signal C SE  being 0 (i.e., I L  being 0) generates signal O ZCD  indicating a zero current condition based on which current controller I CTRL  generates signals C ML  and C MH . For example, when |I L | decreases to 0, current direction controller I CTRL  based on signal O CMP1  generates a high signal C ML  and a low signal C MH  to turn on the respective powered NMOS M L  and M H . Turning on NMOS M L  and turning off NMOS M H  changes the flow of current I L  (e.g., from decreasing to increasing). 
         [0021]    Inductor L M , powered NMOS M H , and powered NMOS M L  form a power converter providing voltage V O  to drive the array of multi-color LEDs. In the particularly illustrated embodiments, blue/red/green LEDs (BRG LEDs) are used in the array. However, LEDs of one or more other colors are used in some embodiments. Likewise, any other types of light emitting devices including, but not limited to, laser diodes or OELDs (organic electro luminescent device), are used in further embodiments. In some embodiments, when NMOS M L  is on NMOS M H  is off, and when NMOS M L  is off NMOS M H  is on. When NMOS M L  is on a current path is created and current I L  flows through NMOS M L  to ground. When NMOS M L  is off and NMOS M H  is on, the current I L  flows through NMOS M H  to the BRG LEDs. In some embodiments, powered NMOS M L  and M H  (as opposed to conventional NMOS transistors) are used to handle large current flowing through them. 
         [0022]    Current controller I CRTL  controls the direction of energy flow or the direction of current I L . In some embodiments, when I L  increases and is larger than zero current I L  flows in the positive direction, the amplitude of voltage C SE  (e.g., |C SE |) increases, which is compared with the amplitude of signal O EA1  (e.g., |O EA1 |) to generate signal O CMP1  based on which current controller I CTRL  generates signals C ML  and C MH . When I L  decreases, however, circuit ZCD, based on the zero current condition reflected on voltage C SE , provides output O ZCD  based on which current controller I CTRL  generates signals C ML  and C MH . For example, when |I L | decreases to zero, |C SE | decreases to 0, circuit ZCD detects a zero current condition of current I L  and generates appropriate signal O ZCD  based on which current controller I CTRL  generates a high signal C ML  to turn on NMOS M L . In some embodiments, current controller I CTRL  generates a high signal C ML  and C MH  to turn on NMOS M L  and M H  respectively. When current I L  switches from the positive to the negative direction, the last zero current signal O ZCD  in the positive current I L  is skipped by the trigger signal S SCAN  to keep the status of NMOS M H  and M L . That is, when current I L  decreases during the boundary between the positive and negative domain, the NMOS M H  and M L  are respectively on and off even though current I L  decreases to zero. When current I L  decreases in the negative domain (e.g., current I L  is negative), the amplitude of voltage C SE  (e.g., |C SE |) increases and is compared with the amplitude of signal O EA1  (e.g., |O EA1 |) to generate signal O CMP1  based on which current controller I CTRL  generates signals C ML  and C MH  that are the inverse signals of those signals when current I L  is positive. For example, when |C SE | is larger than |O EA1 |, NMOS M H  and M L  respectively turn off and on when current I L  is negative. When the |I L | decreases to zero, circuit ZCD detects a zero current condition of current I L  and generates appropriate signal O ZCD  based on which current controller I CTRL  generates a high signal C ML  to turn off NMOS M L . When current I L  switches from negative to positive, the last zero current signal O ZCD  when current I L  is negative is skipped by the positive signal O EA1  to keep the status of NMOS M H  and M L . 
         [0023]    Signal S SCAN  acting as a trigger signal synchronizes control signals C ML  and C MH  through current controller I CRTL . Signal S SCAN  through the current directional controller I CTRL  and driver Drv generates signals C ML  and C MH  to control NMOS M L  and M H  respectively. Signal S SCAN  includes signals B SCAN , R SCAN , and G SCAN  (shown in  FIG. 2 ) corresponding to the respective B, R and G LEDs. In some embodiments, signal S SCAN , via signal R SCAN  transitioning from a low to a high, triggers the energy recycling mode. Further, signals B SCAN , R SCAN , and G SCAN  when transitioning from a low to a high indicate the respective LED transitioning from the Data phase to the Wait phase, and when transitioning from a high to a low indicate the end of the Display phase for the corresponding LED. 
         [0024]    Driver Drv controls (e.g., turn on/off) powered NMOS M L  and M H . Driver Drv acts as a buffer for current controller I CTRL  and sends control signals C ML  and C MH  to control powered NMOS M L  and M H , respectively. In some embodiments, signals C ML  and C MH  are reverse logics so that when NMOS M L  is on, NMOS M H  is off and vice versa. When signal C ML  is high, signal C MH  is low turning NMOS M L  and M H  on and off, respectively. When signal C ML  is low, signal C MH  is high turning NMOS M L  and M H  off and on, respectively. 
         [0025]    Capacitor C O  is used to filter the ripples, if any, existed on voltage V O , and provides a stable voltage V O . 
         [0026]    Voltage V O  commonly called a driving voltage (e.g., driving the LEDs) provides the voltage/current to light the RGB LEDs. The voltage level of voltage V O  depends on the number of LEDs driven by voltage V O . The higher the number of LEDs, the higher the voltage level for voltage V O . In some embodiments, the high voltage of V O  is 40V for 12 LEDs, but this voltage is about 30V for 8 LEDs, for example. In some embodiments, voltage V O  dynamically switches for a corresponding R, G, or B LED. Further, when V O  switches from a high voltage level towards a low voltage level (e.g., when the R LED transitions from the Data phase to the Wait phase), the charge due to the voltage drop is stored in capacitor (e.g., energy tank) C R . When an LED demands energy (e.g., the G LED transitions from the Data phase to the Wait phase), the saved charge (e.g., energy) is used to generate the 40V high voltage level to drive the G LED. Because the saved energy is reused, energy is saved for circuit  100  as a whole. 
         [0027]    In some embodiments, if ΔV O  is the change in voltage V O , and ΔV CR  is the change in voltage V CR , then 
         [0000]      Δ V   O   *C   O   =ΔV   CR   *C   R  or
 
         [0000]      Δ V   CR   =ΔV   O   *C   O   /C   R  
 
         [0000]    Further, so that the driving voltage (e.g., output voltage) V O  is greater than the supply voltage (e.g., or V CR ), 
         [0000]        V   O   −ΔV   O   &gt;V   CR   +ΔV   CR  or 
         [0000]        V   O   &gt;V   CR   +ΔV   CR   +ΔV   O  or 
         [0000]        V   O   &gt;V   CR   +ΔV   O *( C   O   /C   R )+ΔV O  or
 
         [0000]        V   O   &gt;V   CR   +ΔV   O (1+ C   O   /C   R ) 
         [0028]    The plurality of G, B, and R LEDs in some embodiments is used as backlights for a LED-backlit LCD display device or are used to directly display images in an LED display device, such as an LED television screen. Further, there are 12 LEDs for each G, B, and R color, but the embodiments are not limited to any particular number of LEDs. Each B, R, or G LED includes a data receiving phase (e.g., “Data”), a waiting phase (e.g., “Wait”) and a display phase (e.g., “Display”). In the Data phase the LED, either B, R, or G, is “addressed,” i.e., the system/circuit (e.g., a television) using the LEDs locates the appropriate LED. In the Wait phase, the television waits for the LCD image rotation to the appropriate position, and in the Display phase, the LED is turned on. Additionally, the forward (e.g., turn on) bias voltage for the G, B, and R LEDs are 3.3V, 3.3V, and 2.2V, respectively. In some embodiments, the B, R, and G LEDs are controlled to pass through the Data, the Wait, and the Display phases by the television using the LEDs. 
         [0029]    PWM current controller receives dimming control signal DIMCTRL to control the duty cycle and the current of each B R or G LED. An LED using a higher current is brighter than an LED having a lower current. An LED is turned on/off depending on the duty cycle or the logic level of the corresponding pulse width in PWM current controller. For example, if the pulse width is high, the LED turns on, but if the pulse width is low, the LED turns off. 
         [0030]    Resistors R 1  and R 2  serve as a voltage divider for voltage V O  to generate voltage V FB . When voltage V O  changes, voltage V FB  changes. Voltage V FB  is used to compare with a corresponding reference voltage V R , V B , or V G  reflecting through voltage V REF . 
         [0031]    Error amplifier EA 1  compares voltage V FB  to one of reference voltages V R , V B , or V G  chosen as voltage V REF , and provides signal O EA1 . Switches S R , S B , or S G  are used to select the corresponding voltages V R , V B , or V G  as the reference voltage V REF  for amplifier EA 1 . For example, when switch S R  is closed the corresponding voltage V R  is selected as reference voltage V REF . When switch S B  is closed the corresponding voltage V B  is selected as reference voltage V REF , and when a switch S G  is closed the corresponding voltage V G  is selected as reference voltage V REF , etc. In some embodiments, when the LED lighting sequence is B, R, and G, voltage V REF  following voltages V B , V R , and V G  has a wave form of High (H) Low (L) High (H) where the H, L, H correspond to V B , V R , and V G , which is 3.3V, 2.2V, and 3.3V respectively. Signal S SCAN  that includes signals B SCAN , R SCAN , G SCAN  (shown in  FIG. 2 ) corresponding to the B, R, G LEDs, controls the respective switches S B , S R , and S G . For example, when signal B SCAN  is high, switch S B  closes and signal V B  is used as a reference voltage V REF  for error amplifier EA 1 . When signal R SCAN  is high, switch S R  closes and signal V R  is used as a reference input for amplifier EA 1 . When signal G SCAN  is high, switch S G  closes and signal V G  is used as a reference input for amplifier EA 1 , etc. Amplifier EA 1  generates signal O EA1  based on the difference between signals V FB  and V REF . In some embodiments, when V FB  is lower than V REF , signal O EA1  is high, and when V FB  is higher than V REF , signal O EA1  is low or negative. 
         [0032]    Comparator CMP 1  compares signal O EA1  with voltage C SE  and provides signal O CMP1  to control the direction of current I L . In some embodiments, comparator CMP 1  generates signal O CMP1  to stop |I L | from increasing when |I L | reaches a level that |C SE | is higher than |O EA1 |. In some embodiments, whenever |C SE | is higher than |O EA1 |, O CMP1  is high and current controller C CTRL  generates a low signal C ML  and a high signal C MH  to turn off M L  and turn on M H . Turning off M L  and turning on M H  changes the flow of current I L  (e.g., from increasing to decreasing). 
       ILLUSTRATIVE WAVEFORMS 
       [0033]      FIG. 2  is a graph of waveforms  200  illustrating the relationship between various signals for circuit  100 , in accordance with some embodiments. In this illustration, circuit  100  is in the energy recycle mode in the period between time tt 2  and tt 3 . 
         [0034]    In  FIG. 2 , whenever |C SE | is greater than |O EA1 |, signal O CMP1  is high, and signal C SE  corresponding current I L  changes the flow from increasing to decreasing or from decreasing to increasing. Similarly, whenever |C SE | reaches 0 indicating the zero current condition for current I L , |C SE | and |I L | also changes the flow from increasing to decreasing or from decreasing to increasing. 
         [0035]    In effect, signals O CMP1  and O ZCD  set the respective maximum and minimum values for |C SE |. Considering the real value including the sign (e.g., positive/negative), when current I L  is in the positive domain (e.g., prior to time tt 2  and after time tt 3 ), signals O CMP1  and O ZCD  set the respective maximum and minimum amplitude for signal C SE . But when current I L  is in the negative domain (e.g., time period between time tt 2  and tt 3 , signals O CMP1  and O ZCD  set the respective minimum and maximum amplitude for signal C SE . 
         [0036]    In some embodiments where current I L  is in the negative domain and signal O EA1  is not generated as a negative voltage for comparator CMP 1 , a timer is used to generate signal O CMP1  having a fixed time pulse. 
       THE BOOST MODE 
       [0037]      FIG. 3  is a schematic diagram  300  illustrating the operation of circuit  100  in the boost mode, in accordance with some embodiments. 
         [0038]    In the boost mode, voltage V IN  is used as the voltage source to generate voltage V O . In some embodiments, voltage V CR  is initially 0V while voltage V IN  is 12V. Because voltage V IN  is greater than voltage V CR , diode M R  turns on, current I L  flows in the positive domain, e.g., in direction D IO , but through two different paths, path PA 1  and path PA 2 . Further, current I L  flows through path PA 1  first because the power converter comprising inductor L M  and two NMOS M L  and M H  first stores the energy in inductor L M  that causes current I L  to increase. The power converter then converts the stored energy to output V O  and switches back and forth between paths PA 1  and PA 2 . In path PA 1  NMOS M H  is off while NMOS M L  is on, and current flows through M L . Current I L  increases from 0V to its peak level determined by signal O EA1 . That is, current I L  increases until voltage C SE  is greater than voltage O EA1 . At that time, comparator CMP 1  generates a high signal O CMP1 , and current direction controller I CTRL , based on the high O CMP1 , generates a low signal C ML  to turn off M L  and turn on M H . When M H  turns on current I L  flows through path PA 2  and turns on the corresponding LED. Because the LED lights and consumes energy, current I L  starts to decrease, and causes voltage C SE  to decrease until circuit ZCD, based on voltage C SE , detects the zero current condition and provides the corresponding signal O ZCD  (e.g., high). Current direction controller I CTRL , based on signal O ZCD , generates a high signal C ML  to turn on M L  for current I L  to flow through path PA 1 . Current switching between paths PA 1  and PA 2  continues until circuit  100  is out of the boost mode. 
         [0039]      FIG. 4  is a graph of waveforms  400  illustrating the relationship of various currents and voltages corresponding to the operation of circuit  100  in  FIG. 3 , in accordance with some embodiments. During the time signal C ML  is high NMOS M L  is on, current I L  flows through path PA 1  and its magnitude increases until voltage C SE  reaches (e.g., a little higher) than signal O EA1 . In contrast, during the time signal C ML  is low, NMOS M L  is off, NMOS M H  is on. Current I L  flows through path PA 2 , and decreases until the zero current condition occurs. 
       THE ENERGY RECYCLING MODE 
       [0040]      FIG. 5  is a schematic diagram  500  illustrating circuit  100  in the energy recycling mode, which follows a boost mode as illustrated in  FIG. 3 . When voltage V O  starts dropping from a high voltage level (e.g., 40V) toward a low (e.g., 26V) (e.g., when the R LED transition from the Data phase to the Wait phase), some embodiments save the energy (e.g., the charge) resulting from this voltage drop. In this illustration, the power converter comprising inductor L M  and two NMOS M L  and M H  switches to the “buck” mode operation in which voltage V CR  is “stepped down” from about 40V of the output V O  to about  19V . Current I L  flows in direction D OI , which is trigged by the signal S SCAN  and ended by signal O EA1 . Current I L  flows through two different paths, e.g., path PA 3  and path PA 4 . Because current I L  flows in direction D OI , it&#39;s a negative current. Current I L  flowing through inductor L M  generates the energy stored by capacitor C R . Stated another way, current I L  harvests the charge resulting from the voltage drop to the energy tank C R . As |I L | increases, voltage V CR  increases until it&#39;s higher than voltage V IN , diode M R  turns off. Because, in some embodiments V R  is about 0.2 V less than voltage V IN , it does not take too long from the time current I L  flows in the D OI  direction for diode M R  to turn off. 
         [0041]    In some embodiments, current I L  flows through path PA 4  first because the boundary between the positive and negative domain is current path PA 2  in the boost mode and current path PA 4  in this energy recycling mode. Current I L  also switches back and forth between paths PA 4  and PA 3 . In path PA 4  NMOS M H  is on while NMOS M L  is off, and current flows through M H . The |I L | increases (or current I L  decreases) from 0V to its peak level determined by signal O EA1 . That is, |I L | increases until |C SE | is greater than |O EA1 |. At that time, current direction controller I CTRL  generates a high signal C ML  to turn on M L  and turn off M H . When M L  turns on current I L  flows through path PA 3 . |I L | starts to decrease causing |C SE | to decrease until circuit ZCD detects the zero current condition through voltage C SE  from which current direction controller I CTRL  generates a low signal C ML  to turn off M L  for current I L  to flow through path PA 3 . Current switching between paths PA 3  and PA 4  continues until circuit  100  is out of the energy recycle mode. 
         [0042]      FIG. 6  is a graph of waveforms  600  illustrating the relationship of various currents and voltages corresponding to the operation of circuit  100  in  FIG. 5 , in accordance with some embodiments. During the time signal C ML  is low NMOS M L  is off, current I L  flows through path PA 4  and |I L | increases until |C SE | reaches (e.g., a little higher than) |O EA1 |. In contrast, during the time signal C ML  is high, NMOS M L  is on, NMOS M H  is off. Current I L  flows through path PA 3 , and |I L | decreases until the zero current condition occurs. 
         [0043]    In some embodiments, current direction controller I CTRL  includes a time constant T CONST  to limit the time current I L  flows through path PA 4 . Even if the zero current condition has not occurred but if the time from which |I L | starts increasing has passed the time constant T CONST , current direction controller I CTRL  also generates signal C ML  (e.g., a low) to turn off NMOS M L . 
       THE SILENCE MODE 
       [0044]      FIG. 7  is a schematic diagram  700  illustrating circuit  100  in the silence mode that follows an energy recycle mode as illustrated in  FIG. 5 , in accordance with some embodiments. When voltage node V O  does not demand energy (e.g., voltage/current) for the LEDs (e.g., the R LED is in the Wait phase), current I L  is zero, circuit  100  switches to the silence mode. In this illustration, because circuit  100  has just come out of the energy recycling mode, voltage V CR  is greater than voltage V IN , diode M R  turns off. Additionally, because there is not any current I L , both M H  and M L  turn off. During the silence mode the energy (the charge) is hold in the energy tank C R . 
       THE ENERGY TRANSFER MODE 
       [0045]      FIG. 8  is a schematic diagram  800  illustrating the operation of circuit  100  in the energy transfer mode that follows the silence mode as illustrated in  FIG. 7 , in accordance with some embodiments. In the energy transfer mode, voltage V CR  from the energy tank C R , instead of voltage V IN , is used as an input to generate voltage V O . In  FIG. 8 , because circuit  100  has just come out of the silence mode, voltage V CR  remains greater than voltage V IN , diode M R  turns off. Current I L  flows in direction D IO  through an LED (e.g., the R LED) that lights the LED. Because voltage V CR  is used as an input, the saved charge in capacitor C R  during the energy-recycle mode is transferred to node V O  to drive the corresponding LED (e.g., R LED). The operation in this mode is the same as in the boost mode except voltage V CR  instead of voltage V IN  is used as an input. As a result, the current paths PA 5  and PA 6  correspond to the respective current paths PA 1  and PA 2 . Once the saving energy is fully transferred, i.e., the charge stored in capacitor C R  has exhausted, voltage V CR  drops until V IN  is greater than V CR . At that time, active diode M R  turns on and circuit  100  returns to the boost mode, i.e., voltage V IN  functions in place of voltage V CR . 
       ILLUSTRATIVE WAVEFORMS 
       [0046]      FIG. 9  is a graph of waveforms  900  illustrating an operation of circuit  100  in accordance with some embodiments. In this illustration, circuit  100  transitions through an operation cycle including a first boost mode, an energy-recycling mode, a silence mode, an energy transfer mode, and a second boost mode. The operation cycle corresponds to the sequential operation of three B, R, and G LEDs, each of which transitions through the Data, the Wait, and the Display phases. 
         [0047]    When signals B SCAN , R SCAN , and G SCAN  rise from a low to a high the respective B, R, and G LEDs transition from the Data phase to the Wait phase. That is, the LEDs have been addressed and the LCDS for the LEDs enter the LCD rotation mode. The system (e.g., the television) using the LEDs waits for the LEDs to be ready for lighting. When signals B SCAN , R SCAN , and G SCAN  fall from a high to a low, the corresponding LEDs have been displayed for the particular operation cycle. At the beginning of the first boost mode (e.g., prior to time t 1 ) and at the end of the second boost mode (e.g., a little after time t 6 ), voltage V O  is at the high logic level (e.g., about 40V). 
         [0048]    At time t 1 , the B LED is in the Display mode. Voltage V O  drops a little because of the current demand for displaying, but still stays around the 40V range. The B LED turns on. Current I L  switches in the positive domain, having the peak controlled by voltage V O , V FB , and O EA1 . Current I L  is in the cycle of increasing, decreasing, increasing, etc., reflecting the current paths PA 1  and PA 2  in  FIG. 3 . The amplitude of current I L  during the Display phase (e.g., between time t 1  and time t 2 ), however, is higher than that of the other phases (e.g., B Data, B Wait, and R Data phases) because displaying demands higher current. 
         [0049]    At time t 2 , after the B LED has been displayed, the R LED is in the Data phase (e.g., the television addresses the R LED). |I L | drops to about 0V like in the time period prior to time t 1  because the high current demand for displaying the B LED has ended. 
         [0050]    At time t 3 , in some embodiments, when the R LED transitions from the Data to the Wait phase, signal R SCAN  (e.g., the scan signal for the R LED) reaches a high voltage V O  starts dropping from 40V towards 26V, circuit  100  enters the energy recycling mode. As a result, current I L  switches in the negative domain in direction D OI . The amplitude of current I L  in the repeated cycles of increasing then decreasing reflects the current paths PA 3  and PA 4  in  FIG. 4 . Voltage V CR  increases because |I L | increases and the negative current I L  is the charging current that causes voltage V CR  to increase. 
         [0051]    At time t 4 , after the energy-recycling mode ends, circuit  100  enters the silence mode where the energy is stored in the energy tank until time t 5 . In this mode, between times t 4  and t 5 , voltage V O  remains at the low of 26V, but circuit  100  does not experience any activity because the television is waiting for the R LED to be displayed. As a result, current I L  remains at 0 A without switching. Voltage V CR  slopes a little around the voltage acquired during the energy recycling mode because of some current leakage in circuit  100 . 
         [0052]    At time t 5 , the R LED is displayed, which demands energy (e.g., voltage/current at V O ). Circuit  100  enters the energy-transfer mode. That is, circuit  100  uses the energy stored in energy tank C R  (e.g., voltage V CR ) to generate voltage V O  to display the R LED. Current I L  starts switching in the positive domain using the current paths P 5  and P 6  in  FIG. 8 . As the energy is consumed, voltage V CR  starts decreasing until the saved energy in energy tank C R  is exhausted. At that time, circuit  100  ends its energy transfer mode. 
         [0053]    At time t 6 , because the saved energy has been exhausted, circuit  100  enters the boost mode (e.g., the second boost mode) to use voltage V IN  to continue generating voltage V O  and thus continues displaying the R LED. As a result, current I L  still switches in the positive domain in direction D IO . 
         [0054]    At time t 7  the R LED ends its Display phase and the G LED enters the Data phase, which does not demand much current. |I L |, as a result, decreases. 
         [0055]    At time t 8 , the G LED enters its Wait phase, demanding voltage V O . Voltage V O  starts to increase until it reaches 40V some time later in the Wait phase, and remains around 40V during the Wait and Display phases of the G LED. During the time voltage V O  increases, |I L | increases, and decreases when voltage V O  stables at 40V. 
         [0056]    At time t 9 , the G LED enters its Display phase, circuit  100  having been in the second boost mode uses voltage V IN  to generate voltage V O . Because the G LED is in the Display phase, |I L | increases. 
         [0057]    In the above illustration, current I L  switches in the positive domain or flows in direction D IO  in time periods prior to time t 3  and subsequent to time t 4 , and flows in the direction D OI  in the period between times t 3  and t 4 , which is consistent with the fact that in the energy recycling phase current flows in an opposite direction with the current flow in other phases. 
       EXEMPLARY METHOD 
       [0058]      FIG. 10  is a flow chart  1000  illustrating a method related to circuit  100 , in accordance with some embodiments. 
         [0059]    In step  1005 , a first boost mode of circuit  100  is used to drive a Data, a Wait, and a Display phase of a B LED. 
         [0060]    In step  1010 , the first boost mode continues to drive a Data phase of a R LED. 
         [0061]    In step  1015 , while the R LED enters a Wait phase having a voltage V O  drop, the charge resulting from the voltage drop to is saved to an energy tank. 
         [0062]    In step  1020 , the television waits for the R LED to complete its Wait phase. 
         [0063]    In step  1025 , the saved energy in step  1015  is used to continue driving the R and/or G LED until the saved energy is exhausted. For illustration, the saved energy is exhausted before the Display phase of the R LED. 
         [0064]    In step  1030 , the second boost mode is used to continue driving the Display phase of the R LED. 
         [0065]    In step  1035 , the second boost mode is used to continue driving a Data, a Wait, and a Display phase of the G LED. 
       EXEMPLARY ADVANTAGE 
       [0066]      FIG. 11  is a graph of waveforms  1100  illustrating an advantage of circuit  100 , in accordance with some embodiments. The X-axis shows the output current (e.g., current I O ), which is the current at node V O  flowing into the corresponding LEDs, in milli Amperes (mA) in a log scale. The Y-axis shows the efficiency in terms of the ratio between the output power P O  and the input power P I  wherein P O =V O *I O  and P I =V IN *the input current. In an ideal situation, PO/PI=100%. Line  1110  represents the efficiency with respect to output current I O  without the energy saving mechanism of circuit  100 . Line  1120  represents the efficiency with respect to current I O  with the energy saving mechanism of circuit  100 . As shown in  FIG. 11 , circuit  100  (line  1120 ) is about 10% better than a circuit without using the energy saving mechanism. 
         [0067]    A number of embodiments have been described. It will nevertheless be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, the various transistors being shown as a particular dopant type (e.g., NMOS and PMOS) are for illustration purposes, embodiments of the disclosure are not limited to a particular type, but the dopant type selected for a particular transistor is a design choice and is within the scope of embodiments. The logic level (e.g., low or high) of the various signals used in the above description is also for illustration purposes, embodiments are not limited to a particular level when a signal is activated and/or deactivated, but, rather, selecting such a level is a matter of design choice. 
         [0068]    The various figures show the resistors and capacitors (e.g., resistors R 1 , R 2 , capacitors C R , C O , etc.) using discrete resistors and capacitors for illustration only, equivalent circuitry may be used. For example, a resistive device, circuitry or network (e.g., a combination of resistors, resistive devices, circuitry, etc.) can be used in place of the resistor. Similarly, a capacitive device, circuitry or network (e.g., a combination of capacitors, capacitive devices, circuitry, etc.) can be used in place of the capacitor. Additionally, other devices, networks, etc., including rechargeable batteries, that store energy (e.g., charge) can be used in place capacitor or energy tank C R . 
         [0069]    Circuit  100  with exemplary voltage levels of 40V, 26V, etc., is used for illustration. Some embodiments include other circuits that use multiple voltage levels, including, for example, 30V, 20V, 15V, etc. Embodiments of this disclosure are not limited to any number of voltage levels or a particular value for a level. The energy recycling mode is illustrated when voltage V O  decreases, but principles of the disclosed embodiments are applicable when the voltage increases. Further, the disclosed embodiments can be used in programmable DC power supplies (such as the Agient N6705A), sequential power applications, traffic LED lights, advertising lights, etc. 
         [0070]    The above method embodiment shows exemplary steps, but they are not necessarily performed in the order shown. Steps may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of disclosed embodiments. 
         [0071]    Each claim of this document constitutes a separate embodiment, and embodiments that combine different claims and/or different embodiments are within scope of the disclosure and will be apparent to those of ordinary skill in the art after reviewing this disclosure.