Abstract:
In a power MOS transistor, for example, a source electrode is formed so as to be commonly connected to a plurality of source regions formed on the front surface. Thus, a current density varies based on in-plane resistance of the source electrode, thereby providing the necessity of increasing the number of wires connecting the sources and a lead. In the invention, an electrode structure includes a copper plating layer  10   e  formed on a pad electrode  10   a  by an electrolytic plating method, and a nickel plating layer  10   f  and a gold plating layer formed so as to cover the upper and side surfaces of the copper plating layer  10   e  by an electroless plating method.

Description:
REFERENCE TO RELATED APPLICATIONS 
     This application is a national stage application under 35 USC 371 of International Application No. PCT/JP08/057127, filed Apr. 4, 2008, which claims the priority of Japanese Patent Application No. 2007-100838, filed Apr. 6, 2007, the contents of which prior applications are incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to an electrode structure and a semiconductor device, and reduction of on-resistance. 
     2. Description of the Related Art 
     In recent years, due to a mobile terminal or the like used widely, a switching element is required to be small and have low on-resistance. Therefore, in a power MOS transistor, for example, operation cells of MOS transistors are integrated in a single semiconductor die so as to be connected parallel, and a high current flows in the vertical direction of the semiconductor die. 
     For example, in a vertical MOS transistor having a trench structure in which a channel is formed on a side surface of a trench, high density formation of 72 million operation cells per square inch reduces the on-resistance to 12 mΩ. 
       FIG. 11  shows a conventional semiconductor device, and (a) shows a plan view and (b) shows a cross-sectional view of line x-x. 
     A semiconductor die  101  has a plurality of operation cells (not shown) on its front surface side, forming a vertical MOS transistor in which a current flows between the front surface and the back surface. In detail, a source electrode  110  and a gate pad electrode  112  are formed on the front surface of the semiconductor die  101 . An operation cell has a gate electrode, a gate oxide film and a source region. The source electrode  110  covers all the operation cells and is connected to each of the source regions. Each of the gate electrodes is electrically connected to the gate pad electrode  112 . In this structure, the source electrode  110  and the gate pad electrode  112  are electrically connected to leads  116   a,    116   b  through wires  117   a,    117   b,  respectively. A collector electrode  113  is formed on the back surface of the semiconductor substrate  1 . The collector electrode  113  is bonded to an island  114  with conductive paste  115  such as solder or the like. 
     The relevant technique is described in Japanese Patent Application Publication No. 2001-250946. 
     As described above, the source electrode  110  is formed so as to cover all the plurality of operation cells. However, the wire  117   a  is bonded to only a part of the source electrode  110 , thereby causing differences in distances between a bonding portion  119  of the wire  117   a  and the operation cells. As a result, the operation cells operate unevenly based on the resistance of the source electrode  110 , and the die may be broken due to current concentration. 
     Therefore, conventionally, many approaches have been taken for minimizing the uneven operation of the operation cells. 
     For example, as shown in  FIG. 12 , the source electrode  110  and the lead  116   a  are connected through a plurality of wires  117   a . The wires  117   a  are bonded to the source electrode  110  in a wide region. This reduces differences in distances between the bonding portions  119  of the wires  117   a  and the operation cells, thereby providing an even current density. However, a semiconductor device is being miniaturized year after year, and increase of the number of the wires  117   a  prohibits the miniaturization. Furthermore, the wires  117   a  need be carefully bonded to the source electrode  110  so as not to short-circuit an interlayer insulation film insulating the gate electrode and the source electrode  110  due to stress caused by the bonding, and the increase of the number of the wires  117   a  increases the possibility of occurrence of a defect. Furthermore, the cost increases corresponding to the increase of the number of the wires  117   a.    
     Furthermore, as shown in  FIGS. 13A and 13B , the source electrode  110  and a lead  120   a  are connected through a metal frame  120   b  formed together with the lead  120   a  without using a wire. Since the metal frame  120   b  is bonded to the source electrode  110  in a wide region, each of the operation cells is hardly influenced by the in-plane resistance of the source electrode  110 . Furthermore, the metal frame  120   b  has largely lower resistance than a wire, thereby realizing a semiconductor device having low on-resistance. 
     However, when the area of the metal frame  120   b  is increased corresponding to the area of the source electrode  110 , conductive paste  122  bonding the source electrode  110  and the metal frame  120   b  easily becomes uneven and the current density varies accordingly. Furthermore, it is difficult to align the source electrode  110  and the metal frame  120   b  when these are bonded. Furthermore, the cost increases corresponding to the area of the metal frame  120   b.    
     SUMMARY OF THE INVENTION 
     Considering the above, an electrode structure according to the invention includes: a pad electrode; a protection film formed covering the pad electrode so as to partially expose the pad electrode; a copper plating layer formed on the pad electrode; and a cap layer formed on the copper plating layer, wherein the copper plating layer and the cap layer are continuously formed by an electrolytic plating method, and the copper plating layer is covered by a passivation film on its side surface. 
     An electrode structure according to the invention includes: a pad electrode; a protection film formed covering the pad electrode so as to partially expose the pad electrode; a copper plating layer formed on the pad electrode; and a cap layer formed on the copper plating layer, wherein the copper plating layer is formed by an electrolytic plating method and the cap layer is formed by an electroless plating method so as to cover upper and side surfaces of the copper plating layer. 
     A semiconductor device according to the invention includes: a plurality of operation cells and a first electrode connected to all the operation cells on a front surface of a semiconductor substrate, wherein a current flows in a vertical direction of the semiconductor substrate by operation of the operation cells, the first electrode being electrically connected to a first external connection terminal through a bonding portion, and the first electrode including a copper plating layer for minimizing uneven operation based on distances between the operation cells and the bonding portion. 
     In the invention, a semiconductor device has an electrode structure having a thick copper plating layer formed by an electrolytic plating method. Therefore, the position and number of a bonding portion of an electrode are freely designable. 
     Furthermore, since the copper plating layer is covered by a passivation film or a plating film on its side surface portion, oxidation of the side surface portion is prevented regardless of the thickness of the copper plating layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a first electrode structure and a process of manufacturing the same. 
         FIG. 2  shows a second electrode structure and a process of manufacturing the same. 
         FIG. 3  shows a plan view and a cross-sectional view of a first semiconductor die. 
         FIG. 4  shows a plan view and a cross-sectional view of a second semiconductor die. 
         FIG. 5  shows a plane view and a cross-sectional view of a third semiconductor die. 
         FIG. 6  shows a plane view and a cross-sectional view of a fourth semiconductor die. 
         FIG. 7  shows a plan view and a cross-sectional view of a first semiconductor device. 
         FIG. 8  shows a plan view and a cross-sectional view of a second semiconductor device. 
         FIG. 9  shows a plan view and a cross-sectional view of a third semiconductor device. 
         FIG. 10  shows a plan view and a cross-sectional view of a fourth semiconductor device. 
         FIG. 11  shows a plan view and a cross-sectional view of a conventional semiconductor device. 
         FIG. 12  shows a plan view and a cross-sectional view of a conventional semiconductor device. 
         FIG. 13  shows a plan view and a cross-sectional view of a conventional semiconductor device. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A semiconductor device of an embodiment of the invention will be described in detail referring to figures. In the following, an electrode structure is described first, then a semiconductor die having the electrode structure is described, and lastly a semiconductor device having the semiconductor die is described. 
     &lt;Electrode Structure&gt; 
     First, an electrode structure of a semiconductor device will be described in detail. In the following, a numeral  2  indicates a semiconductor substrate, where an element region such as a source region or the like is formed on the front surface in a case of a MOS transistor, for example, although the detail is omitted here. A numeral  10   a  indicates a pad layer, which is formed by depositing A 1  by, for example, a sputtering method so as to be electrically connected to the element region. 
     -First Electrode Structure  10 A- 
       FIG. 1  shows cross-sectional views of a first electrode structure  10 A and a method of manufacturing the same. 
     First, as shown in  FIG. 1  ( a ), a nitride film  10   b  is formed so as to expose the pad layer  10   a . A titanium barrier layer  10   c  and a copper seed layer  10   d  are then continuously formed on the nitride film  10   b  by a sputtering method or a vapor deposition method so as to be electrically connected to the pad layer  10   a.    
     As shown in  FIG. 1  ( b ), a resist film  33   a  is patterned so as to have an opening on the pad layer  10   a . A copper plating layer  10   e,  a nickel plating layer  10   f  and a gold plating layer  10   g  are then continuously deposited by an electrolytic plating method. 
     Then, as shown in  FIG. 1  ( c ), the resist film  33   a  is removed, and the exposed portions of the titanium barrier layer  10   c  and the copper seed layer  10   d  are partially removed. 
     Then, as shown in  FIG. 1  ( d ), a passivation film  26   a  such as a solder resist or the like is patterned so as to cover the side surface of the copper plating layer  10   e,  thereby completing the first electrode structure  10 A. 
     As described above, in the first electrode structure  10 A, the copper plating layer  10   e  is formed by the electrolytic plating method. Therefore, the formation of the copper plating layer  10   e  is achieved for a short time at a low cost even when it has a thickness larger than 10 μm. 
     When the copper plating layer  10   e  is formed thick, it is easily oxidized at its side surface. However, in the first electrode structure  10 A, the passivation film  26   a  is formed on the side surface of the copper plating layer  10   e  and prevents the oxidation. 
     -Second Electrode Structure  10 B- 
       FIG. 2  shows cross-sectional views of a second electrode structure  10 B and a method of manufacturing the same. 
     First, as shown in  FIG. 2  ( a ), in the similar manner to the first electrode structure  10 A, the nitride film  10   b,  the titanium barrier layer  10   c  and the copper seed layer  10   d  are formed on the pad layer  10   a.    
     Then, as shown in  FIG. 2  ( b ), a resist film  33   b  is patterned so as to have an opening on the pad layer  10   a . The copper plating layer  10   e  is then formed by an electrolytic plating method. 
     Then, as shown in  FIG. 2  ( c ), the resist film  33   b  is removed and the exposed portions of the titanium barrier layer  10   c  and the copper seed layer  10   d  are partially removed. 
     Then, as shown in  FIG. 2  ( d ), the nickel plating layer  10   f  and the gold plating layer  10   g  are formed by an electroless plating method so as to totally cover the copper plating layer  10   e.    
     As described above, in the second electrode structure  10 B, the nickel plating layer  10   f  and the gold plating layer  10   g  are formed by the electroless plating method so as to cover the copper plating layer  10   e  including its side surface. This eliminates the necessity of forming the passivation film  26   a  for preventing the oxidation like in the first electrode structure  10 A. 
     &lt;Structure of Semiconductor Die having First or Second Electrode Structure&gt; 
     Next, a structure of a semiconductor die having the first or second electrode structure will be described in detail. In the following, a source electrode  10  is formed to have the first or second electrode structure. 
     It is noted that the following description uses a vertical MOS transistor as an example of a semiconductor die  1 . However, the invention is not limited to this, and may be applied similarly to other devices such as IGBT (insulated gate bipolar transistor) or the like as long as a current flows in the vertical direction of the semiconductor die. 
     -First Semiconductor Die  1 A- 
       FIG. 3  shows a first semiconductor die  1 A, and  FIG. 3  ( a ) is a plan view and  FIG. 3  ( b ) is a cross-sectional view of line x-x. 
     First, the structure of the semiconductor die  1 A will be described. The semiconductor die  1 A has, on its front surface side, an N+type semiconductor substrate  2  as a drain region and an N−type epitaxial layer  3 , a P type channel layer  4  formed on the front surface of the epitaxial layer  3 , trenches  5  formed in the channel layer  4  and extending to the epitaxial layer  3 , gate electrodes  7  made of polysilicon embedded in the trenches  5  with gate insulation films  6  therebetween, N+type source regions  8  provided adjacent to the trenches  5 , P+type body regions  9  formed between the adjacent source regions  8 , a source electrode  10  formed so as to cover the source regions  8 , an interlayer insulation film  11  insulating the gate electrodes  7  and the source electrode  10 , and a gate pad electrode  12  electrically connected to the gate electrodes  7  through connection wiring (not shown). The semiconductor die  1 A further has a drain electrode  13  on its whole back surface. 
     Next, the operation of the semiconductor die  1 A will be described. When a voltage is applied to the gate electrodes  7  through the gate pad electrode  12 , channels are formed in the channel layer  4  near the gate electrodes  7 . At this time, when a voltage is applied between the source electrode  10  and the drain electrode  13 , a current flows from the drain electrode  13  to the semiconductor substrate  2  and the epitaxial layer  3 , and then to the source regions  8  through the channels formed in the channel layer  4 , reaching the source electrode  10 . It means that a plurality of operation cells each having the source region  8 , the gate electrode  7  and the gate oxide film  6  is formed in a single die and the operation cells are connected parallel. 
     At this time, in the first semiconductor die  1 A, the source electrode  10  has low in-plane resistance since it has the first or second electrode structure. Therefore, voltages applied to the source regions  8  hardly vary, and thus in-plane current distribution is less biased, thereby preventing current concentration to a certain operation cell. 
     -Second Semiconductor Die  1 B- 
       FIG. 4  show a second semiconductor die  1 B, and  FIG. 4  ( a ) is a plan view and  FIG. 4  ( b ) is a cross-sectional view of line x-x. 
     In the second semiconductor die  1 B, a drain electrode  29  is formed on the same front surface side as well as the source electrode  10  and the gate pad electrode  12 . Furthermore, low-resistance drain current leading means  30  is provided so as to extend from the drain electrode  29  at least to the semiconductor substrate  2 . 
     With this structure, a drain current is led to under the drain electrode  29  through the conductive layer  31   a,  and further to the drain electrode  29  through the drain current leading means  30 . 
     The drain current leading means  30  need have lower resistance than the epitaxial layer  3 , and is preferably an N+type ion implantation layer, an embedded electrode such as metal or the like, for example. 
     For leading a drain current to the drain electrode  29  formed on the front surface side, other various methods are applicable as descried below. 
     For example, as shown in  FIG. 5 , drain current leading means  30   b  may be formed from the back surface of the semiconductor substrate  2  toward the drain electrode  29 . In this case, too, a drain current is led to the drain electrode  29  formed on the front surface side. In this embodiment, simultaneous formation of a conductive layer  31   b  and the drain current leading means  30   b  is achieved by forming an opening  32   b  in a position for forming the drain current leading means  30   b  in advance. 
     Furthermore, as shown in  FIG. 6 , a plurality of openings  32   c  may be formed from the back surface of the semiconductor substrate  2  to the epitaxial layer  3  and a conductive layer  31   c  may be formed so as to be embedded in the openings  32   c . With this structure, a drain current flows through a portion of the conductive layer  31   c  formed in the openings  32   c  to the drain electrode  29  without through the high resistance semiconductor substrate  2 . 
     &lt;Semiconductor Device having First Semiconductor Die  1 A&gt; 
     Next, a semiconductor device having the first semiconductor die  1 A will be described in detail. In the following, a numeral  1 A indicates the first semiconductor die  1 A, although the detail is omitted. A numeral  10  has the first or second electrode structure, although the detail is omitted. 
     -First Semiconductor Device  50 A- 
       FIG. 7  shows a first semiconductor device  50 A, and  FIG. 7  ( a ) is a plan view and  FIG. 7  ( b ) is a cross-sectional view of line x-x. 
     An island  14  is an external connection terminal electrically connected to the drain electrode  13  of the semiconductor die  1 A, which is formed by punching a copper, for example. The semiconductor die  1 A is bonded to this island  14  with conductive paste  15  such as solder or silver to electrically connect the island  14  and the drain electrode  13 . 
     A lead  16   a  is an external connection terminal electrically connected to the source electrode  10  of the semiconductor die  1 A through a wire  17   a  at a bonding portion  19  where conductive paste  18  such as solder or the like is coated, and a lead  16   b  is an external connection terminal electrically connected to the gate pad electrode  12  of the semiconductor die  1 A through a wire  17   b.    
     The source electrode  10  has low in-plane electric resistance since it has the first or second electrode structure. Therefore, the operation cell formed immediately under the bonding portion  19  and the operation cell formed at a distance from the bonding portion  19  operate to flow about the same current. 
     Since the copper plating layer  10   c  and the semiconductor die  1 A are largely different in coefficient of thermal expansion, when the copper plating layer  10   e  is formed too thick, it provides the possibility of separation of the source electrode  10  and the semiconductor die  1 A. Therefore, by forming the bonding portion  19  at the center of the source electrode  10 , preferably, the maximum distance between the bonding portion  19  and the operation cell is reduced, so that the thickness of the copper plating layer  10   e  is minimized and the separation is prevented. 
     As described above, in the first semiconductor device  50 A, since the number of the wires  17   a  is reduced, the damage of the interlayer insulation film  11  by wire-bonding is minimized and a short circuit between the gate electrodes  7  and the source electrode  10  is prevented. 
     -Second Semiconductor Device  50 B- 
       FIG. 8  shows a second semiconductor device  50 B, and  FIG. 8  ( a ) is a plan view and  FIG. 8  ( b ) is a cross-sectional view of line x-x. 
     In the second semiconductor device  50 B, a lead  20   a  is formed together with a metal frame  20   b,  and this metal frame  20   b  is electrically connected to the source electrode  10  at a bonding portion  22  where conductive paste  21  such as solder or the like is coated. 
     The source electrode  10  has low in-plane electric resistance since it has the first or second electrode structure. Therefore, the metal frame  20   b  is formed to have a small area such that the conductive paste  21  spreads evenly between the source electrode  10  and the metal frame  20   b,  thereby minimizing variation of on-resistance. Furthermore, preferably, the metal frame  20   b  is formed at the center of the source electrode  10  at a distance from the end of the source electrode  10 . This reduces the maximum distance between the bonding portion  22  and the operation cell, and further prevents the conductive paste  21  from spreading to the gate pad electrode  12  and causing a short circuit. 
     -Third Semiconductor Device  50 C- 
       FIG. 9  shows a third semiconductor device  50 C, and  FIG. 9  ( a ) is a plan view and  FIG. 9  ( b ) is a cross-sectional view of line x-x. 
     In the third semiconductor device  50 C, the external terminals of the source electrode  10 , the gate pad electrode  12  and the drain electrode  13  are formed of a source bump electrode  23   a,  a gate bump electrode  23   b  and a drain bump electrode  23   c,  respectively. Then, the semiconductor die  1 A is mounted facedown on conductive patterns  25  of a mounting substrate  24 , and the bump electrodes  23  and the conductive patterns  25  are respectively aligned and bonded by solder reflowing with heat or supersonic vibration under pressure. 
     In detail, the source bump electrode  23   a  and the gate bump electrode  23   b  are formed on the source electrode  10  and the gate pad electrode  12  and electrically connected thereto respectively so as to be exposed from the contact holes of the protection film  26  made of, for example, solder resist. Furthermore, the drain electrode  13  is electrically led to the front surface side of the semiconductor die  1 A by a leading frame  27  extending from the back surface of the semiconductor die  1 A to the front surface thereof, and electrically connected to the conductive pattern  25   c  through the drain bump electrode  23   c.    
     The source electrode  10  has low in-plane electric resistance since it has the first or second electrode structure. Therefore, the position and number of the source bump electrode  23   a  are freely designable corresponding to the conductive pattern  25   a  of the mounting substrate  24 . 
     &lt;Semiconductor Device having Second Semiconductor Die  1 B&gt; 
     Next, a semiconductor device having the second semiconductor die  1 B will be described in detail. In the following, a numeral  1 B indicates the second semiconductor die  1 B, although the detail is omitted. A numeral  10  has the first or second electrode structure, although the detail is omitted. 
     -Fourth Semiconductor Device  50 D- 
       FIG. 10  show a fourth semiconductor device  50 D, and  FIG. 10  ( a ) is a plan view and  FIG. 10  ( b ) is a cross-sectional view of line x-x. 
     The semiconductor die  1 B has the source bump electrode  23   a  on the source electrode  10 , the gate bump electrode  23   b  on the gate pad electrode  12 , and the drain bump electrode  23   d  on the drain electrode  29 , which are mounted facedown on the conductive patterns  25   a,    25   b  and  25   d  of the mounting substrate  24 , respectively. 
     The source electrode  10  has low in-plane electric resistance since it has the first or second electrode structure. Therefore, the number and position of the source bump electrode  23   a  are freely designable corresponding to the conductive pattern  25   a.    
     It should be noted that these disclosed embodiments are illustrative in all respects and not limitative. The scope of the invention is defined by claims but not by the above description of the embodiments, and covers all equivalent meanings to claims and all modifications within the scope. 
     For example, although the gate electrode and the drain electrode are not described in detail in the embodiments described above, these may be formed to have the same structure by the same process as those for the source electrode. 
     The feature of the invention is that the position and number of the bonding portion of the source electrode  10  and the external connection terminal are freely designable since the source electrode  10  has low in-plane electric resistance, and the position and number of the bonding portion shown in the embodiments are merely an example. 
     Although a method of forming the drain electrode is not described in detail, it may be formed by the same process as the process of forming the electrodes on the front surface. 
     The copper plating layer  10   e  is not necessarily made of pure copper as long as the material is mainly made of copper. 
     In the second to fourth semiconductor dies  1 B to  1 D, still lower resistance is realized by forming the openings  32   b  to  32  penetrating the epitaxial layer  3  and the semiconductor substrate  2  totally to connect the drain electrode  29  and the conductive layers  31   b  to  31 .