Abstract:
An overvoltage protection circuit for a CMOS electronic multimeter circuit uses a pair of complementary field-effect protection transistors connected to each input line of the meter circuit. The gate electrodes of the protection transistors are connected to bias voltage sources which provide bias voltages with magnitudes slightly less than the meter power supply voltages. The protection transistors go into conduction when an overvoltage condition causes the voltage on the input to exceed the bias voltages and the conducting protection transistors clamp the input voltage to substantially the bias voltage. Current caused by an overvoltage condition is shunted to ground thereby avoiding a charging condition in the power supplies.

Description:
This is a continuation of U.S. patent application Ser. No. 07/858,580, for OVERVOLTAGE PROTECTION FOR BATTERY POWERED EQUIPMENT, filed on Mar. 27, 1992, and now abandoned. 
    
    
     FIELD OF THE INVENTION 
     This invention relates generally to overvoltage protection in solid state equipment, and, more particularly, to an overvoltage protection circuit for use with battery powered equipment. 
     BACKGROUND OF THE INVENTION 
     In many electronic apparatus, such as multimeters, externally generated voltages are applied to the apparatus for processing or analysis thereof. In the case of a multimeter, voltages of various magnitudes are coupled to the meter input for measurement. Typically, if the input voltage exceeds the potential of the power supply, the input voltage is clamped to the most positive and the most negative power supply rails in the apparatus. However, in battery powered apparatus, such as multimeters, clamping excessive voltages to the supply rails can be undesirable and even dangerous. In particular, if the multimeter is implemented, in whole or part, as an integrated circuit, the voltage tolerance is very low, on the order of less than 10 volts. Excessive voltages can destroy integrated circuit elements, requiring repair or, often, complete replacement. 
     FIG. 1 illustrates a prior art overvoltage protection circuit 10A for use with a battery-powered apparatus. In circuit 10A, a diode 18 is coupled between input terminal 14 and positive power supply 22. A diode 20 is similarly coupled between input terminal 14 and negative power supply 24. An input voltage, V IN , from an external voltage source 12, is coupled to diodes 18 and 20 through input terminal 14 and input resistor 16. When V IN  is greater than the positive power supply voltage, V DD , by at least the threshold voltage of diode 18, diode 18 begins to conduct current to the positive power supply 22, effectively charging the power supply. Similarly, when V IN  is less than the negative power supply voltage, V SS , by at least the threshold voltage of diode 20, diode 20 begins to conduct current from negative power supply 24, effectively charging the negative power supply. For an electronic apparatus powered by non-alkaline batteries, such a result is acceptable. However, if the apparatus is powered by alkaline batteries, even a minute charging current, typically hundreds of microamps, will cause the alkaline batteries to generate hydrogen gas. The formation of such hydrogen gas can be very dangerous and creates both a fire and explosion hazard. 
     In order to overcome this difficulty, prior art circuits have used a pair of Zener diodes connected in series with reverse polarity as shown in circuit 10B of FIG. 1B. In circuit 10B, an input voltage, V IN , from an external voltage source 12, is coupled to an electrical device through input terminal 14 and input resistor 16 in a manner similar to that shown in FIG. 1A. Zener diodes 26 and 28 are connected from input resistor 16 to ground. If a positive input voltage exceeds the reverse breakdown voltage or Zener voltage of Zener diode 26, this diode begins reverse conduction. In this configuration, Zener diode 28 is forward-biased and so the positive input voltage is clamped to ground and cannot exceed the Zener voltage of diode 26. 
     In a similar manner, if a negative input voltage exceeds the Zener voltage of Zener diode 28, this diode begins reverse conduction. In this configuration, Zener diode 26 is forward-biased and so the negative input voltage is clamped to ground and cannot exceed the Zener voltage of diode 28. 
     This configuration has the advantage that the current which is generated as a result of an overvoltage condition is shunted to ground rather than the power supply. The circuit thus avoids the battery charging problems associated with the previous prior art circuit. However, when the double Zener diode circuit is used with high-impedance circuits such as CMOS circuits, the Zener clamp circuit can heavily load the input. This loading is the result of the relatively high reverse leakage current normally found in Zener diodes. This high reverse leakage current appears as a stray impedance connected across the input to ground. In the case of a multimeter circuit, this stray impedance appears as a shunt resistance and can cause errors in the readings taken with the meter. 
     Accordingly, a need exists for a way to safely protect an electronic apparatus from excessive voltages applied to its inputs. 
     It is, therefore, an object of the present invention to provide an overvoltage protection circuit which can safely shunt excessive input voltages. 
     Another object of the present invention is to provide an overvoltage protection circuit suitable for use with battery-powered electronic apparatus. 
     Yet another object of the present invention is to provide an overvoltage protection circuit which shunts current produced by an overvoltage condition to ground. 
     A further object of the present invention is to provide an overvoltage protection circuit which can be used with high-impedance circuitry. 
     Still a further object of the present invention is to provide an overvoltage protection circuit which has low leakage when in the non-conducting state. 
     BRIEF SUMMARY OF THE INVENTION 
     The above and other object are achieved in accordance with the present invention which, according to one embodiment, provides an overvoltage protection circuit comprising a first bias voltage source for supplying a control voltage which is less than or equal to the power supply voltage and a current amplifier having a first terminal coupled to the input terminal, a second terminal coupled to a potential less than the control voltage and a control terminal coupled to the first bias voltage source for controlling the conduction between the first and second terminals. 
     In one embodiment, the current amplifier comprises a p-channel field effect transistor having its source terminal coupled to the input terminal and its drain terminal coupled to ground. The field effect transistor shunts excessive input voltages to ground when the input voltage has a greater potential than the control voltage applied to its gate terminal. Alternately, the p-channel field effect transistor may be replaced with a bipolar PNP transistor to achieve the same functionality. 
     In an embodiment in which both positive and negative DC power supplies are present, a second bias voltage source is included for supplying a control voltage having greater than or equal potential to the negative power supply voltage. A second current amplifier operates in a complementary, opposite manner to shunt excessive negative voltages present at the input terminal of the circuit back through the input terminal. The second current amplifier may be implemented with either an n-channel field effect transistor or a bipolar NPN transistor. 
     The foregoing and other features, objects and advantages of the invention will be more fully understood by reading the detailed description below in conjunction with the drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings: 
     FIG. 1A is a schematic diagram of a prior art diode overvoltage protection circuit; 
     FIG. 1B is a schematic diagram of a prior art Zener diode overvoltage protection circuit; 
     FIG. 2 is a schematic diagram of an overvoltage protection circuit according to a first embodiment of the present invention; and 
     FIG. 3 is a schematic diagram of an overvoltage protection circuit according to a second embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     With reference to the drawings, and more particularly FIG. 2 thereof, an overvoltage protection circuit 30 in accordance with a first embodiment of the present invention is illustrated. Circuit 30 comprises an input terminal 34, an input resistor 36, a p-channel Field Effect Transistor (FET) 40, an n-channel FET 50, a first bias voltage source 48, and a second bias voltage source 58. For the purposes of clarity, the source, gate and drain terminals of FET 40 will be designated 42, 44, and 46, respectively. Similarly, the source, gate and drain terminals of FET 50 will be designated 52, 54 and 56, respectively. 
     As illustrated in FIG. 2, source 42 of FET 40 is coupled to input terminal 34 through input resistor 36. Gate 44 of FET 40 is coupled to bias voltage source 48, as illustrated. Bias voltage source 48 supplies a voltage to gate 44 which may be less than or equal to the positive power supply (not shown), V DD . Bias voltage source 48 can be implemented in any number of conventional ways. For example, source 48 may comprise a voltage dividing network of resistors within the multimeter or electronic apparatus which is coupled to the positive power supply. Accordingly, the construction and implementation of the bias voltage source does not form any part of this invention. Drain 46 of FET 40 is coupled to ground, as illustrated. 
     In a similar manner, source 52 of FET 50 is coupled to input terminal 34 through input resistor 36. Gate 54 of FET 50 is coupled to bias voltage source 58, as illustrated. Bias voltage source 58 supplies a voltage to gate 54 which may be greater than or equal to the negative power supply (not shown), V SS . Bias voltage source 58 can be implemented similar to source 48 or in any number of conventional ways. Accordingly, the construction and implementation of bias voltage source 58 does not form any part of this invention. Drain 56 of FET 50 is coupled to ground, as illustrated. 
     The value of input resistor 36 should be chosen to protect FETs 40 and 50 from being destroyed by excessive current at input terminal 34. External voltage source 32 is connected to input terminal 34 and may either be an AC or DC voltage source. 
     Circuit 30 operates as follows. When an input voltage, received at input terminal 34, causes source 42 of FET 40 to be at a greater potential than the biasing voltage at gate 44, FET 40 will begin to conduct current and shunt the input voltage to ground through drain 46. In this manner, excessive voltage harmful to source 48, which is connected to a voltage dividing network of resistors in a multimeter, is shunted to ground, preventing damage to the network and the multimeter. In this manner, FET 40 functions as a current amplifier. If the bias voltage at gate 44 is maintained at slightly less than or equal to the positive power supply voltage, V DD , any input voltage greater than V DD  will be shunted to ground through FET 40. Drain 46 may alternately be coupled to the negative power supply, V SS . However, this configuration is less desirable. 
     Similarly, when an input voltage, received at input terminal 34, causes source 52 of FET 50 to be at a lower potential than the biasing voltage at gate 54, FET 50 will begin to conduct current and shunt the negative input voltage to input terminal 34. In this manner, FET 50 likewise acts as a current amplifier. If the bias voltage at gate 54 is maintained at slightly greater than or equal to the negative power supply voltage, V SS , any input voltage less than V SS , will be shunted back to input terminal 34 of circuit 30. Drain 56 may alternately be coupled to the positive power supply, V DD . Again, however, this configuration is less desirable. 
     Since, in a majority of instances, excessive voltages applied to an apparatus will be positive and not negative, FET 50 and bias voltage source 58 may be optionally removed from circuit 30. Similarly, if overvoltage protection is required for only negative input voltages, FET 40 and bias voltage source 48 may be optionally removed from circuit 30. In the disclosed embodiment, circuit 30 contains complementary FETs which may be implemented using complementary metal oxide semiconductor (CMOS) fabrication technology. 
     An overvoltage protection circuit 60, in accordance with a second embodiment of the present invention, is illustrated in FIG. 3. Circuit 60 is similar in construction and function to circuit 30 except that FET 40 has been replaced with a bipolar PNP transistor 70 and FET 50 has been replaced with a bipolar NPN transistor 80. For the purposes of clarity, the emitter, base and collector terminals of transistor 70 will be designated 72, 74 and 76, respectively. Similarly, the emitter, base and collector terminals of transistor 80 will be designated 82, 84 and 86, respectively. 
     As illustrated in FIG. 3, emitter 72 of transistor 70 is coupled to input terminal 34 through input resistor 36. Base 74 of transistor 70 is coupled to bias voltage source 48, as illustrated. As in the first embodiment, bias voltage source 48 supplies a voltage to base 74 which may be less than or equal to the positive power supply source, V DD . Collector 76 of transistor 70 is coupled to ground, as illustrated. 
     In a similar manner, emitter 82 of transistor 80 is coupled to input terminal 34 through input resistor 36. Base 84 of transistor 80 is coupled to bias voltage source 58, as illustrated. As in the first embodiment, bias voltage source 58 supplies a voltage to base 84 which may be greater than or equal to the negative power supply source, V SS . Collector 86 of transistor 80 is coupled to ground, as illustrated. In this embodiment, the value of input resistor 36 should be chosen to protect transistors 70 and 80 from being destroyed by excessive current at input terminal 34. 
     Circuit 60 operates as follows. When an input voltage, received at input terminal 34, causes emitter 72 of transistor 70 to be at a greater potential than the biasing voltage at base 74, transistor 70 will begin to conduct current and shunt the input voltage to ground through collector 76. As in the embodiment of FIG. 2, excessive voltage harmful to source 48, which is connected to a voltage dividing network of resistors in a multimeter, is shunted to ground, preventing damage to the sensitive circuit elements in the network and multimeter. As such, transistor 70 functions as a current amplifier, the load current through the transistor being dependent on the base current. As with the embodiment of circuit 30, if the bias voltage at base 74 is maintained at slightly less than or equal to the positive power supply voltage, V DD , any input voltage greater than V DD  will be shunted to ground through transistor 70. Collector 76 may alternately be coupled to the negative power supply, V SS . 
     Similarly, when an input voltage, received at input terminal 34, causes emitter 82 of transistor 80 to be at a lower potential than the biasing voltage at base 84, transistor 80 will begin to conduct current and shunt the negative input voltage to input terminal 34. Transistor 80, like the transistor 70, acts as a current amplifier. As with the first embodiment, if the bias voltage at base 84 is maintained slightly greater than or equal to the negative power supply, V SS , any input voltage less than V SS  will be shunted to input terminal 34 through transistor 80. Collector 86 may alternately be coupled to a negative power supply, V SS . 
     As with the first embodiment, either transistor 70 or 80, and its respective bias voltage source, may optionally be removed from circuit 60, if overvoltage protection is desired against excessive voltages of only one polarity. Circuit 60 may also be implemented using bipolar semiconductor fabrication technology. 
     It may be appreciated from the above disclosure that the various embodiments of the present invention each provide an overvoltage protection circuit which safely shunts input voltages having magnitudes which exceed those of the power supply in a manner which will not cause damage to the electronic circuit and which can be implemented readily using conventional semiconductor fabrication technology. 
     Accordingly, it will be appreciated that the detailed disclosure has been presented by way of example only and is not intended to be limiting. Various alterations, modifications and improvements will readily occur to those skilled in the art, and may be practiced without departing from the spirit and scope of the invention. For example, the exact values of bias voltage sources 48 and 58 will depend on the values of V DD  and V SS , respectively. Similarly, the value of input resistor 36 will be dependent on these exact specifications of the actual transistors implemented in circuits 30 and 60. Further, other circuit elements which function as current amplifiers may be substituted for the transistors of the present invention. Additionally, the inventive overvoltage protection circuit may be used to protect direct current power supplies which are not implemented with batteries and can be used to protect against excessive voltages which are generated either externally or internally of an apparatus. The invention is limited only as required by the following claims and equivalents thereto.