Abstract:
An input gradation converting circuit has a gradation conversion table in which M-bit intermediate gradation data are correlated with each of N-bit input gradation data, and is operable to convert each of the input gradation data into the M-bit intermediate gradation data by using the gradation conversion table and output the converted M-bit intermediate gradation data. A diffusion gradation converting circuit is operable to convert each of the intermediate gradation data outputted from the input gradation converting circuit into N-bit output gradation data and output the converted N-bit output gradation data. The diffusion gradation converting circuit acquires a uniform random number Rnd in the range of −SFT/2 to SFT/2 and outputs [X+Rnd+0.5] as the output gradation data for each of the intermediate gradation data in which X obtained by dividing a value of the intermediate gradation data by 2 M·N  and a specified value SFT satisfy a conditional expression “SFT/2≦[X]≦2 N −1−SFT/2” (where [ ] is a Gauss symbol). The diffusion gradation converting circuit acquires a uniform random number Rnd′ in the range of 0≦[X+Rnd′+05]≦2 N −1 and outputs [X+Rnd′+0.5] as the output gradation data for each of the intermediate gradation data in which the X and the specified value SFT do not satisfy the conditional expression.

Description:
[0001]    The disclosure of Japanese Patent Application No. 2006-252313 filed Sep. 19, 2006 including specification, drawings and claims is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    The present invention relates to an image processing circuit performing a gradation conversion of image data (a gradation data set), a gradation converting method, and a printing apparatus performing a gradation conversion of image data at the time of printing images of the image data. 
         [0003]    In general printers currently available on the market, an image processing circuit generates data for operating a print engine on the basis of an RGB data set which a CPU in the printer generates by analyzing print data (or, on the basis of an RGB data set which is transmitted, as print data, from a host). However, existing image processing circuits are configured to decrease the number of gradations. 
         [0004]    Specifically, as an image processing circuit for a color printer, there is an image processing circuit having a configuration shown in  FIG. 6 . In the image processing circuit, a gradation converting circuit  52  converts 8-bit Z data sent (Z=C, M, Y, and K) from a color converting circuit  51  into 8-bit Z′ data by the use of a gradation conversion table as shown in  FIG. 7  (gradation conversion table for performing a gradation conversion as shown in  FIG. 8 ). The color converting circuit  51  is a circuit for converting 8-bit R, G, and B data into 8-bit C, M, Y, and K data. A binarization and smoothing processing circuit  53  is a circuit for converting the Z′ data supplied from the gradation converting circuit  52  into Z″ data (data for operating the print engine) to be used as a depiction width of each pixel. 
         [0005]    Since it is necessary to perform the gradation conversion shown in  FIG. 8 , some values are not set as outputs in the gradation conversion table. Accordingly, in the image processing circuit, the number of gradations is reduced by the processing of the gradation converting circuit  52 . 
         [0006]    In another image processing circuit different from the circuit shown in  FIG. 6  in a specific configuration, the gradation converting process of decreasing the number of gradations is performed in a manner similar to the case of the above-mentioned image processing circuit (e.g., see Japanese Patent Publication No. 2006-197359A). 
       SUMMARY 
       [0007]    It is therefore an object of the invention to provide an image processing circuit and a gradation converting method capable of performing gradation conversion with a high precision. It is another object of the invention to provide a printing apparatus capable of printing with a higher quality than the related-art apparatus. 
         [0008]    In order to solve the above-mentioned problems, there is provided an image processing circuit comprising: 
         [0009]    an input gradation converting circuit, having a gradation conversion table in which M-bit intermediate gradation data are correlated with each of N-bit input gradation data, and operable to convert each of the input gradation data into the M-bit intermediate gradation data by using the gradation conversion table and output the converted M-bit intermediate gradation data; and 
         [0010]    a diffusion gradation converting circuit, operable to convert each of the intermediate gradation data outputted from the input gradation converting circuit into N-bit output gradation data and output the converted N-bit output gradation data, wherein: 
         [0011]    the diffusion gradation converting circuit acquires a uniform random number Rnd in the range of −SFT/2 to SFT/2 and outputs [X+Rnd+0.5] as the output gradation data for each of the intermediate gradation data in which X obtained by dividing a value of the intermediate gradation data by 2 M·N  and a specified value SFT sat a conditional expression “SFT/2≦[X]≦2 N −1−SFT/2” (where [ ] is a Gauss symbol); and 
         [0012]    the diffusion gradation converting circuit acquires a uniform random number Rnd′ in the range of 0≦[X+Rnd′+05]≦2 N −1 and outputs [X+Rnd′+0.5] as the output gradation data for each of the intermediate gradation data in which the X and the specified value SFT do not satisfy the conditional expression. 
         [0013]    That is, the image processing circuit according to an aspect of the invention is operable to convert the N-bit input gradation data into the M-bit intermediate data and then to convert the intermediate gradation data into the N-bit output gradation data on the basis of an algorithm in which an expected value corresponds to X (X is a value obtained by dividing the intermediate gradation data by 2 M·N ). Since the image processing circuit of the invention does not reduce the number of gradations at the time of gradation conversion (i.e., the number of gradations of input gradation data is equal to that of output gradation data), the image processing circuit can perform the gradation conversion with a higher precision than the related-art image processing circuit. 
         [0014]    In realizing (manufacturing) the image processing circuit of the invention, the diffusion gradation converting circuit may acquire the uniform random number Rnd′ in the range of −(2·[X]+[X−[X]+0.5])/2 to (2·[X]+[X−[X]+0.5])/2 for each of the intermediate gradation data in which the X and the specified value SFT satisfy SFT/2&gt;[X]; and the diffusion gradation converting circuit may acquire the uniform random number Rnd′ in the range of −(2·(2 N −1−[X])−[X−[X]+0.5])/2 to (2·(2 N −1−[X])−[X−[X]+0.5])/2 for each of the intermediate gradation data in which the X and the specified value SFT satisfy SFT/2&gt;2 N −1−[X]. In addition, the diffusion gradation converting circuit may acquire a uniform random number Rnd′ in the range of −0.5 to 0.5 for each intermediate gradation data in which the X and the specified value SFT do not satisfy the conditional expression, and to output [X+Rnd′+0.5] as output gradation data. 
         [0015]    In a similar manner to the case of the image processing circuit, the gradation convening method according to another aspect of the invention is configured to convert the N-bit input gradation data into the M-bit intermediate gradation data and then to convert the intermediate gradation data into the N-bit output gradation data on the basis of an algorithm in which an expected value corresponds to X (X is a value obtained by dividing intermediate gradation data by 2 M·N ). Accordingly, by using the gradation converting method according to the invention, it is possible to perform gradation conversion with a higher precision than that of the related-art gradation converting method. 
         [0016]    Further, the printing apparatus according to a further aspect of the invention includes the image processing circuit of the invention and performs printing by using the image processing circuit. Therefore, the printing apparatus according to the invention can perform printing with a higher quality than that of the related-art apparatus. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]    The above objects and advantages of the present invention will become more apparent by describing in detail preferred exemplary embodiments thereof with reference to the accompanying drawings, wherein: 
           [0018]      FIG. 1  is a diagram illustrating a printing apparatus according to an embodiment; 
           [0019]      FIG. 2  is a diagram illustrating an image processing circuit according to the embodiment; 
           [0020]      FIG. 3  is a gradation conversion table to which an input gradation converting circuit in the image processing circuit according to the embodiment refers; 
           [0021]      FIG. 4  is a flowchart illustrating processes executed by a diffusion gradation converting circuit in the image processing circuit according to the embodiment; 
           [0022]      FIGS. 5(A) to 5(C)  are diagrams showing a meaning of the processes executed by the diffusion gradation converting circuit in the image processing circuit according to the embodiment; 
           [0023]      FIG. 6  is a diagram illustrating an image processing circuit used in a related-art color printer; 
           [0024]      FIG. 7  is a gradation conversion table in a related-art image processing circuit; and 
           [0025]      FIG. 8  is a diagram illustrating a gradation conversion performed by the related-art image processing circuit on the basis of the gradation conversion table. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0026]    Hereafter, embodiments of the invention will be described in detail with reference to the drawings. 
         [0027]    First, an overview of a printing apparatus  10  according to an embodiment of the invention will be described with reference to  FIGS. 1 and 2 . 
         [0028]    As shown in  FIG. 1 , the printing apparatus  10  according to the embodiment of the invention includes an operation panel  11 , a controller  12 , and a print engine  13 . The printing apparatus  10  is connected to a PC (personal computer) having a printer driver for the printing apparatus installed therein via a parallel cable or a LAN cable. 
         [0029]    The print engine  13  of the printing apparatus  10  is a unit that performs a color or monochrome printing operation on a sheet. The operation panel  11  is interface means for connecting the printing apparatus  10  to a user, and is provided on a case of the printing apparatus  10 . The operation panel  11  includes an LCD, a plurality of LEDs, a push-button switch, and the like. 
         [0030]    The controller  12  is a unit that performs processes (e.g., process causing the print engine  13  to perform printing) of the contents designated by the data sent from the PC. 
         [0031]    The printing apparatus  10  according to the present embodiment is different from the related-art printing apparatus only in that a configuration of an image processing circuit  20  mounted on a controller  2  for the present embodiment is different from that of the related-art printing apparatus (i.e., the image processing circuit  20  is mounted instead of the related-art image processing circuit). 
         [0032]    Next, a configuration and an operation of the image processing circuit  20  used in the printing apparatus  10  (controller  12 ) of the present embodiment will be described with reference to  FIGS. 2 to 6 . 
         [0033]    As shown in  FIG. 2 , the image processing circuit  20  includes a color converting circuit  21 , a gradation converting circuit  22 , and a binarization and smoothing processing circuit  23 . 
         [0034]    The color converting circuit  21  and the binarization and smoothing processing circuit  23  in the image processing circuit  20  are the same as the color converting circuit  51  and the binarization and smoothing processing circuit  53  shown in  FIG. 6 , respectively. 
         [0035]    The gradation converting circuit  22  is a circuit for converting 8-bit Z data (Z=C, M, Y, and K) into 8-bit Z′ data in a manner similar to the case of the gradation converting circuit  52 . However, the gradation converting circuit  22  is not a circuit for only outputting data stored in a gradation conversion table as a conversion result of the Z data. The gradation converting circuit  22  is configured to covert 8-bit Z data into 16-bit data (hereinafter, referred to as intermediate gradation data), and then convert the 16-bit intermediate gradation data into 8-bit Z′ data, thereby outputting the converted data. 
         [0036]    Specifically, the gradation converting circuit  22  includes input gradation converting circuits and diffusion gradation converting circuits which are provided for each Z data, respectively. 
         [0037]    Each of the input gradation converting circuits in the gradation converting circuit  22  is a circuit for converting the 8-bit Z data into the 16-bit intermediate gradation data for Z data by the use of a gradation conversion table as shown in  FIG. 3  (which is a gradation table that stores data (having double the number of bits) with a higher precision than that of the gradation conversion table shown in  FIG. 7 ). 
         [0038]    Each of the diffusion gradation converting circuits in the gradation converting circuit  22  is a circuit for performing a process shown in  FIG. 4  for the 16-bit intermediate gradation data that are outputted from a corresponding one of the input gradation converting circuits. As used in  FIG. 4  and the following descriptions, X is a value obtained by dividing a value of the 16-bit intermediate gradation data by 2 8 . 
         [0039]    That is, when the intermediate gradation data is inputted, the diffusion gradation converting circuit judges whether “X=0” is satisfied or not (Step S 101 ). When “X=0” is satisfied (Step S 101 : YES), the diffusion gradation converting circuit outputs “0” as a conversion result (Z′ data) (Step S 102 ); and then the process (process in  FIG. 4 ) for the inputted intermediate gradation data ends. 
         [0040]    When “X=0” is not satisfied (Step S 101 : NO), the diffusion gradation converting circuit judges whether “X≧255” is satisfied or not (Step S 103 ). When “X≧255” is satisfied (Step S 103 : YES), the diffusion gradation converting circuit outputs “255” as a conversion result (Step S 104 ) and then the process for the inputted intermediate gradation data ends. 
         [0041]    When “X≧255” is not satisfied (step S 103 : NO), the diffusion gradation converting circuit judges whether “0&lt;X&lt;1 or 254&lt;X&lt;255” is satisfied or not (Step S 105 ). When “0&lt;X&lt;1 or 254&lt;X&lt;255” is satisfied (Step S 105 : YES), the diffusion gradation converting circuit acquires a uniform random number Rnd in the range of −0.5 to 0.5 (Step S 106 ) and outputs [X+Rnd+0.5] (where [ ] is a Gauss symbol) as a conversion result (Step S 112 ); and then the process for the inputted intermediate gradation data ends. 
         [0042]    When “0&lt;X&lt;1 or 254&lt;X&lt;255” is not satisfied (Step S 105 : NO), the diffusion gradation converting circuit judges whether “[X]&lt;STF/2” is satisfied or not (Step: S 105 ). In this case, SFT is an integer (e.g., “15”) preset in the image processing circuit  20 . 
         [0043]    When “[X]&lt;SFT/2” satisfied (Step S 107 : YES), the diffusion gradation converting circuit acquires a uniform random number Rnd in the range of −(2·[X]+[X−[X]+0.5])/2 to (2·[X]+[X−[X]+0.5])/2 (Step S 108 ). Then, the diffusion gradation converting circuit outputs [X+Rnd+0.5] as a conversion result (Step S 112 ) and then the process for the inputted intermediate gradation data ends. 
         [0044]    Meanwhile, when “[X]&lt;SFT/2” is not satisfied (Step S 107 : NO), the diffusion gradation converting circuit judges whether “255−[X]&lt;SFT/2” is satisfied or not (Step S 109 ). When “255−[X]&lt;SFT/2” is satisfied (Step S 109 : YES), the diffusion gradation converting circuit acquires a uniform random number Rnd in the range of −(2·(255−[X])·[X−[X]+0.5])/2 to (2·(255−[X])−[X−[X]+0.5])/2 (Step S 110 ). Then, the diffusion gradation converting circuit outputs [X+Rnd+0.5] as a conversion result (Step S 112 ) and then the process for the inputted intermediate gradation data ends. 
         [0045]    When “255−[X]&lt;SFT/2” is not satisfied (Step S 107 : YES), the diffusion gradation converting circuit acquires a uniform random number Rnd in the range of −SFT/2 to SFT/2 (Step S 111 ) and outputs [X+Rnd+0.5] as a conversion result (Step S 112 ); and then the process for the inputted intermediate gradation data ends. 
         [0046]    Hereinafter, the operation (meaning of the process in  FIG. 4 ) of the diffusion gradation converting circuit will be described in more detail with reference to  FIGS. 5(A) to 5(C) . 
         [0047]    It is assumed that intermediate gradation data (intermediate gradation data satisfying SFT/2≦[X]&lt;255−SFT/2) is inputted to perform the process of Step S 111  under the condition where 2k+1 (odd number) is set as SFT. 
         [0048]    In this case, a value of “X+Rnd+0.5” is in the range of X−k to X+k+1 as shown in  FIG. 5(A) . Since the Rnd acquired in the process of Step S 111  is a uniform random number, in the process of Step S 112  “[X]−k” (=[X−k]) is outputted in the probability of (1−Xfac)/(2k+1) (Xfrac is X−[X]: decimal fraction of X); “[X]+k+1” (=[X+k+1]) is outputted in the probability of Xfrac(2k+1); and each integer in the range of “[X]−k+1” to “[X]+k” is outputted in the probability of 1/(2k+1). 
         [0049]    In this case, an expected value of the data (data outputted in the process of Step S 112 ) outputted as a conversion result from the diffusion gradation converting circuit is equal to X as descried below. 
         [0000]    
       
         
           
             
               
                 
                   
                     Expected 
                      
                     
                         
                     
                      
                     Value 
                   
                   = 
                     
                    
                   
                     
                       
                         ( 
                         
                           
                             [ 
                             X 
                             ] 
                           
                           - 
                           k 
                         
                         ) 
                       
                       · 
                       
                         
                           1 
                           - 
                           Xfrac 
                         
                         
                           
                             2 
                              
                             
                                 
                             
                              
                             k 
                           
                           + 
                           1 
                         
                       
                     
                     + 
                   
                 
               
             
             
               
                 
                     
                    
                   
                     
                       
                         ( 
                         
                           
                             [ 
                             x 
                             ] 
                           
                           + 
                           k 
                           + 
                           1 
                         
                         ) 
                       
                       · 
                       
                         Xfrac 
                         
                           
                             2 
                              
                             
                                 
                             
                              
                             k 
                           
                           + 
                           1 
                         
                       
                     
                     + 
                     
                       
                         ∑ 
                         
                           y 
                           = 
                           
                             
                               - 
                               k 
                             
                             + 
                             1 
                           
                         
                         k 
                       
                        
                       
                           
                       
                        
                       
                         
                           
                             [ 
                             X 
                             ] 
                           
                           - 
                           y 
                         
                         
                           
                             2 
                              
                             
                                 
                             
                              
                             k 
                           
                           + 
                           1 
                         
                       
                     
                   
                 
               
             
             
               
                 
                   
                     = 
                       
                      
                     
                       ( 
                       
                         
                           [ 
                           X 
                           ] 
                         
                         + 
                         k 
                         + 
                         1 
                         - 
                         
                           [ 
                           X 
                           ] 
                         
                         + 
                         k 
                       
                       ) 
                     
                   
                    
                   
                     
                       · 
                       
                         Xfrac 
                         
                           
                             2 
                              
                             k 
                           
                           + 
                           1 
                         
                       
                     
                     + 
                     
                       
                         ∑ 
                         
                           y 
                           = 
                           
                             - 
                             k 
                           
                         
                         k 
                       
                        
                       
                           
                       
                        
                       
                         
                           
                             [ 
                             X 
                             ] 
                           
                           - 
                           y 
                         
                         
                           
                             2 
                              
                             k 
                           
                           + 
                           1 
                         
                       
                     
                   
                 
               
             
             
               
                 
                   = 
                     
                    
                   
                     Xfrac 
                     + 
                     
                       [ 
                       X 
                       ] 
                     
                   
                 
               
             
             
               
                 
                   = 
                     
                    
                   X 
                 
               
             
           
         
       
     
         [0050]    When intermediate gradation data in which Xfrac is 0.5 or more is inputted to perform the process of Step S 111  under the condition where 2k (even number) is set as SFT, a value of “X+Rnd+0.5” is in the range of X−k+0.5 to X+k+0.5 as shown in  FIG. 5(B) . Since the Rnd acquired in the process of Step S 111  is a uniform random number, in the process of Step S 112  “[X]−k+1” (=[X−k+0.5]) is outputted in the probability of (1−Xfrac)/2k; “[X]+k+1” ([X+k+0.5]) is outputted in the probability of (Xfrac−0.5)/2k; and each integer in the range of “[X]−k+2” to “[X]+k−1” is outputted in the probability of ½k. 
         [0051]    When intermediate gradation data in which Xfrac is smaller than 0.5 is inputted to perform the process of Step S 111  under the condition where 2k is set as SFT, a value of “X+Rnd+0.5” is in the range of X−k+0.5 to X+k+0.5 as shown in  FIG. 5(C) . Since the Rnd acquired in the process of Step S 111  is a uniform random number, in the process of Step S 112  “[X]−k” (=[X-k+0.5]) is outputted in the probability of (0.5−Xfrac)/2k; “[X]+k” (=[X+k+0.5]) is outputted in the probability of (Xfrac+0.5)/2k; and each integer in the range of “[X]−k+1” to “[X]+k−1” is outputted in the probability of ½k. 
         [0052]    Accordingly, the expected value (formula is omitted) of the data outputted as a conversion result from the diffusion gradation converting circuit is also equal to X, in the above cases. 
         [0053]    As described above, when the processes in Steps S 111  and S 112  are performed for the intermediate gradation data satisfying SFT/2≦[X]&lt;255−SFT/2, the diffusion gradation converting circuit outputs, as a conversion result, the data of which the expected value is equal to X, independently from the SFT. 
         [0054]    However, when the diffusion gradation converting circuit is configured to perform the processes in Steps S 111  and S 112  for every intermediate gradation data, the value of [X+Rnd+0.5] may become a negative value that cannot be outputted as Z′ data, or may become a value equal to or greater than 256 that cannot be outputted as Z′ data. For this reason, the diffusion gradation converting circuit of the image processing circuit  20  (gradation converting circuit  22 ) according to the present embodiment is configured to reduce (steps S 106 , S 108 , and S 110 ) a generation range of Rnd so that the value of [X+Rnd+0.5] is in the range of 0 to 255, for the intermediate gradation data for which the value of [X+Rnd+0.5] is a negative value or a value equal to or greater than 256, as described above. 
         [0055]    As described above, the image processing circuit  20  mounted on the printing apparatus  10  according to the present embodiment performs a sequence of processes including: “a process of converting 8-bit input gradation data into 16-bit intermediate gradation data; and a process of converting the intermediate gradation data into 8-bit output gradation data on the basis of an algorithm in which an expected value correspond to X (X is a value obtained by dividing intermediate gradation data by 2 8 ),” in order to convert 8-bit input gradation data into 8-bit output gradation data. Since the image processing circuit  20  does not reduce the number of gradations at the time of gradation conversion (i.e., the number of gradations of input gradation data is equal to that of output gradation data), the image processing circuit  20  can perform the gradation conversion with a higher precision than the related-art image processing circuit. The printing apparatus  10  according to the present embodiment includes the image processing circuit  20  that generates the data for allowing the print engine  13  to perform the printing. Accordingly, when the printing apparatus  10  is installed in an office or the like, it is possible to realize a circumstance in which the printing can be performed with a higher quality than that for the case where the related-art printing apparatus is installed in the office or the like. 
       Modified Embodiment 
       [0056]    The printing apparatus  10  and the image processing circuit  20  may be modified in various forms. For example, the image processing circuit  20  may be modified into a circuit having the number of bit of input gradation data or the number of bit of intermediate gradation data which is different from the numbers described above or into a circuit which does not include the color converting circuit  21  or the binarization and smoothing processing circuit  23 . Further, the image processing circuit  20  may be modified into a circuit different from the image processing circuit  20  in that the manner of reducing the generation range of Rnd for the intermediate gradation data in which the value of [X+Rnd+0.5] is a negative value or 256 or more (e.g., a circuit generating Rnd in the range of −0.5 to 0.5). 
         [0057]    The printing apparatus  10  is the so-called printer, but may be a printing apparatus using the image processing circuit  20  (e.g., an apparatus for printing such as a facsimile and a multifunctional apparatus) in addition to the printer.