Abstract:
A charge based analog to digital converter includes a plurality of charge storage elements, each having a charge receive mode and a charge expel mode, and were in each of the charge storage elements is configured for storing a predetermined amount of charge. There is preferably a two to one ratio between the storage capacity of adjacent charge storage elements. A comparator includes a sensing diffusion connected to all of the charge storage elements. The comparator produces a &#34;0&#34; bit if the sensing diffusion is in a first condition, and a &#34;1&#34; bit if the sensing diffusion is in a second condition. Selection electronics connected to the charge storage elements selectively and successively set the individual charge storage elements in the charge expel mode to successively test the charge quantity stored in each charge storage element by the initial analog charge packet.

Description:
The invention herein described was made in the course of and/or under Contract DASG60-86-C-0095 with the Department of the Army. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention is an analog to digital converter for converting an analog charge based signal to a digital representation of the analog signal. 
     Conventional low-speed analog to digital converters operate by comparing a sampled analog voltage to a reference voltage, and adjusting the reference voltage until a null output is obtained. The digital device used to adjust the reference voltage is then decoded and read out as the digital equivalent. The reference voltage source used requires ultra-precision resistors, and dissipates power. 
     A typical successive-approximation analog to digital converter (A/D) is shown in block diagram form in FIG. 1. The input signal, usually held at a fixed level by a sample and hold circuit 31, is compared against the output of a digital to analog converter (D/A) 33. This is accomplished by inputting the sample and hold output and the D/A output into a differencing amplifier 35 and the amplifier output into a comparator 37. 
     At sample input time, the serial shift register and the bit latch 39 are set to all &#34;0&#34; by the control logic 41. The clock then advances the control logic at a fixed rate. The control logic shifts a &#34;1&#34; through the serial shift register. The control logic also, in combination with the comparator, sets the bit latch. The output from the shift register is ORed with the bit latch to control the D/A converter. 
     The A/D converter is exercised starting with the Most 10 Significant Bit (MSB). The MSB is activated in the D/A by the 11 shift register, causing comparison of the input against a 1/2 of full scale value. If the differencing amplifier output to the comparator indicates that the held input sample is more than 1/2 of full scale, as shown by the comparator 37, the MSB is left &#34;ON&#34;, and a &#34;1&#34; is recorded in the bit latch for the MSB. If the differencing amplifier output to the comparator indicates that the input sample is less than 1/2 of full scale, the MSB is turned &#34;OFF&#34;, and a &#34;0&#34; is recorded in the bit latch for the MSB. 
     The exercising of the A/D continues in order of descending bit weight, each bit weight being equal to 1/2 of the previous bit. Each bit weight is individually compared to the input sample via the D/A by summation with the D/A&#39;s output of the previous bits, if they were left &#34;ON&#34;. The comparator therefore must be able to resolve a difference equal to the least significant bit. 
     FIG. 2 shows the bit weighting scheme of the typical A/D converters. The analog input signal is almost 3/4 of full scale. The MSB test produced a &#34;1&#34; for greater than half. This caused the D/A to be left &#34;ON&#34; for the MSB. The second bit equal to a 1/4 caused overflow and was set to &#34;0&#34; causing the D/A to be turned off for that bit. The third bit equal to 1/8 produced a &#34;1&#34; for a D/A sum less than the input so the D/A was left on. The fourth bit equal to a 1/16 caused overflow and was set to &#34;0&#34;. causing the D/A to be turned off for that bit. The fifth bit equal to 1/32 produced a &#34;1&#34; for a D/A sum less than the input so the D/A was left &#34;ON&#34;. The resultant output binary code was therefore 10101. The digital result can be serially output as each bit is evaluated or parallel output from the stored results. Accuracy, linearity, and speed are primarily affected by the properties of the D/A converter and the comparator. 
     The invention is particularly suited to converting the analog signals received from individual infrared detectors of a focal plane array to a digital form for processing by digital signal processing electronics. In that application, the output of a detector is an analog charge domain signal. This signal is sampled to produce a charge packet. Conventional voltage based analog to digital converters require that the charge packet analog signal be converted to a voltage prior to being input to the analog to digital converter. The charge packet to voltage conversion process is non-linear, and the voltage must be corrected following conversion. 
     Furthermore, in the infrared detector application, the signal processing electronics, including any charge to voltage and analog to digital converters, are frequently placed adjacent the detector array. Therefore, heat generated in the conversion processes may be transferred to the detectors, interfering with their operation. 
     The invention is also generally suitable for use with signals produced by charge coupled devices (CCD&#39;s) or other sources of charge domain signals. 
     The invention is further suitable for use with a voltage input, as the conversion from voltage to charge can be made quite linear. 
     SUMMARY OF THE INVENTION 
     The present invention is a low power consumption device and method for directly converting a charge domain analog signal to a digital representation. 
     The method of the invention includes receiving a charge packet representative of a signal amplitude, and storing the charge packet in a plurality of charge storage wells, each having a predetermined relative storage capacity. The charge is distributed proportionally among the charge storage wells. The charge in the first storage well is unloaded onto a sensing diffusion connected to the storage wells and into the other storage wells, and a comparator connected to the sensing diffusion is sampled. If the comparator does not sense an overflow condition, a &#34;0&#34; is recorded for the first bit of the digital representation, and the well is left unloaded. The charge is subsequently unloaded from a second of the storage wells onto the sensing diffusion and the other charge storage wells, but not onto the first charge storage well. If, during the first sampling step, the comparator senses an overflow condition, a &#34;1&#34; is recorded for the first bit of the digital representation, and the well is returned to the store charge state. The charge is subsequently unloaded from the second storage well onto the sensing diffusion and the other charge storage wells, including the first storage well. The comparator is sampled a second time, and if the first condition is sensed, a &#34;0&#34; is recorded for the second bit of the digital representation, and the well is left unloaded. If the second condition is sensed, a &#34;1&#34; is recorded for the second bit of the digital representation, and the well is returned to store charge. This process is repeated until all bits have been sampled. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a system block diagram of a conventional successive approximation analog to digital converter. 
     FIG. 2 a bit weighting scheme for a conventional five bit analog to digital converter. 
     FIG. 3 is a system block diagram of an analog to digital conversion apparatus incorporating the invention. 
     FIG. 4 is a block diagram of the analog to digital converter constructed according to the invention. 
     FIG. 5 shows the bit weighting scheme for a five bit analog to digital converter constructed according to the invention. 
     FIG. 6 is a layout diagram of an analog to digital converter according to the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 3, an overall system block diagram for an analog to digital converter incorporating the invention is shown. The analog signal charge packet is received at the charge input 11. sampled into the A/D at the correct time by the sampling switch 12, and applied to the digitally weighted charge storage wells 13. When a charge packet from a CCD or other charge source is input, the diffusion must be reset to a fixed voltage prior to charge arrival. 
     The operation of the sampling switch 12, as well as certain other elements of the system, is controlled by control logic 15. The control logic is conventional in construction. 
     The charge packet could also have been sampled from an input diffusion and applied to the digitally weighted charge storage wells, in which case it is directly proportional to a sampled signal equivalent voltage. The charge packet from a previous analog to digital conversion need not be cleared from the charge wells, as the charge stored will equilibrate to the new sampled value. 
     The digitally weighted charge storage wells 13 are shown in greater detail in the block diagram of FIG. 4. The embodiment illustrated is for producing a 5-bit digital value. Those skilled in the art will recognize that the apparatus can be expanded or reduced for different numbers of digital bits. 
     The A/D includes a plurality of charge storage elements or charge storage wells 21-25. The charge storage wells are controlled by storage gates. Each charge storage well has a predetermined charge volume. The volume of each well is determined by the area of the charge storage gate on the die and the voltage applied to the gate when creating a storage well. Each well can be caused to either hold charge (store or receive charge) or expel charge (unload charge). Whether the well is in the charge receive or the charge expel mode depends on the voltage applied to the gate. 
     In addition, there is a predetermined charge volume relationship among the different wells that corresponds to the relationship among the bit values in the converted digital representation. In the preferred embodiment shown for generating a binary digital result, each well is constructed to hold half the charge of the preceding well. Thus, the first well 21 holds a predetermined amount of charge. The second well 22 holds one-half the charge that the first well holds the third well 23 holds one-half the charge that the second well holds, and so forth. In the illustrated embodiment, the voltage applied to the gates is the same, so the volume differences are obtained by varying the areas of the gates. Thus, the second gate for the second well 22 has one-half the area of the first gate of the first well 21, the third gate of the third well 23 has one-half the area of the second gate, and so forth. 
     The number of gates and wells corresponds to the number of bits desired in the digital representation of the signal. The largest well corresponds to the most significant bit of the digital result, the second largest well corresponds to the next most significant bit, and so forth, with the smallest well corresponding to the least significant bit. 
     All of the charge storage wells are connected to a floating gate or common sensing diffusion 27. This floating gate forms the sensing element for a charge-based comparator 29. The comparator is conventional in construction, and compares the charge on the floating gate with a threshold to determine if an overflow condition exists. 
     The structure shown in block diagram form in FIGS. 3 and 4 may be implemented on a semiconductor die. An exemplary multi-layer layout of the weighted A/D 13 and the comparator 29 is shown in FIG. 6. The weighted A/D shown includes ten charge storage gates, for generating a ten bit digital output. In the illustrated layout, each gate is formed in two halves, as illustrated for example by the largest charge storage gate 30, which is formed of halves 30a and 30b. The split charge storage gates provide greater control over the size and positioning of the gates. Those skilled in the art will recognize that the size ratios among the gates are important to accurate generation of the digital bits. With the exception of the comparator, the entire structure can be formed using an all digital CMOS design. 
     In operation, the charge storage wells 21-25 are initially set to a voltage that will expel all charge from the gate, to empty the gates of any residual charge. The floating gate 27 is reset to a predetermined starting voltage. 
     The charge storage elements 21-25 are then all set in the charge store mode by adjusting the voltage applied to the charge storage gates. 
     The signal, in the form of a packet of charge that is directly proportional to a sampled signal equivalent voltage is input to the floating gate 27, and through the floating gate to the charge storage gates 21-25. Because of the common connection of the charge storage gates to the floating gate, the charge is distributed proportionally among the charge storage wells. 
     Conversion of this received analog charge to a digital value begins with the most significant binary bit (MSB). The voltage applied to the first charge storage gate (the MSB well) 21 is adjusted to change the first, MSB well from the charge store mode to the charge expel mode, and expel all the charge from the first gate onto the floating gate and the other charge storage gates 22-25. The charge on the common diffusion exceeds the threshold of the comparator when the charge in the storage gates exceeds a particular level. 
     The comparator 29 then samples the state of the floating gate 27, to determine if the preset threshold of charge on the floating gate has been exceeded. 
     If the threshold is not exceeded, a &#34;0&#34; is recorded in the memory 31 (FIG. 1) for the most significant bit, and the first storage gate 21 is left in the charge expel mode for the remainder of the conversion process. 
     If the comparator detects that the charge on the floating gate has exceeded the threshold, a digital &#34;1&#34; is recorded in the bit latch and serial shift register 31 (FIG. 1), and the first gate is reset to the charge hold or store mode. 
     Next, the second gate 22 is changed to the charge expel mode to begin the process of determining the second or next most significant bit in the digital representation. In the charge expel mode, the second gate discharges or unloads charge onto the sensing diffusion 27 and the other smaller charge storage gates 23-25. Whether the charge goes onto the first (MSB) charge storage gate 21 depends on the output of the first comparison. If 13 the first comparison produced a digital &#34;0&#34;, and the gate was thus left in the charge expel mode, no charge will be stored on the first gate. But, if the first comparison produced a digital &#34;1&#34;, and the gate reset to the charge store mode, charge from the second gate will be stored on the first gate as well as the other gates 23-25. 
     Each of the gates receives the additional charge from the second gate in proportion to the size of the gate. 
     The comparator attached to the common diffusion is again sampled. As before, if the comparator attached to the diffusion by an overflow condition on the floating gate, a &#34;0&#34; is not set by an overflow condition on the floating gate, a &#34;0&#34; is recorded in the shift register bit latch 31 for the second most significant bit, and the second gate 22 is left in the charge expel mode. If, however, the comparator is set by an overflow condition on the gate, a &#34;1&#34; is recorded in the bit latch for the second most significant bit and a second gate is reset to the charge storage mode. 
     The process of expelling charge from the successive gates, sensing the status of the floating gate with the comparator, and recording digital values in the bit latch is continued for each successive gate, until all the desired digital bits have been generated. The digital data may be output serially as the A/D converter progresses, or may be output in serial or parallel form from the bit latch at the conclusion of the conversion process. 
     FIG. 5 shows a bit weighing scheme of the charge domain analog to digital converter for producing a five bit output. The gate forming the MSB well 21 is caused to unload charge onto the rest of the gates and the sensing diffusion. The comparator, attached to the diffusion, is then sampled for status. In this example a &#34;1&#34; was recorded for the MSB. The operation of conversion continues with each gate in binary order from the MSB to the least significant bit (LSB). Each gate is successively interrogated, comparator status stored in memory, and left unloaded or returned to the hold charge condition dependent on the status of the comparator. The second bit therefore was a &#34;0&#34;, the third a &#34;1&#34;, the fourth a &#34;0&#34;, and the fifth a &#34;1&#34;. The resultant binary output code was 10101. This was the same result as in the example of the conventional analog to digital converter in FIG. 2. 
     Successive approximation of data requires a finite period of time for each bit. As each data bit is used in determining the next bit, the completed conversion is preferably transferred to a separate output shift register or parallel output latch 33. The converter may then be cleared and made ready for the next signal charge packet. In this way, the completed conversion can be output at any convenient time during the next conversion cycle. This output can be in either serial or parallel form. 
     The construction of the charge based comparator 29, the serial shift register and bit latch 31 and the output register 33, as well as the control logic 15 and other selection electronics for controlling the operation of the charge-based analog to digital converter are known in the art, and will be apparent to those skilled in the art. 
     FIG. 6 shows the die layout of a particular embodiment of the analog to digital converter of the invention. In particular, the individual gates forming the digitally weighted charge storage wells 13 are seen. 
     The invention may be embodied in other specific forms without departing from its spirit. The above-described embodiment is therefore to be considered as illustrative and not restrictive, the scope of the invention being defined by the following claims and their equivalents.