Abstract:
An electronic system having a central controller coupled to a plurality of remote transceiver modules by means of a serial bus. The modules are designed to remain in a sleep mode in which they consume no power until such time as a wakeup signal is sent over the bus by the central controller. Each module includes a source of power and power supply circuitry adapted to provide power for operating the module when the power supply circuitry is connected to the source of power. Each module further includes an energy detector coupled to the bus and adapted to connect the power supply circuitry to the source of power upon detection of energy, in the form of the wakeup signal, on the bus. Within each module is a microprocessor which responds to the provision of power by maintaining the connection between the source of power and the power supply after the wakeup signal has terminated and until such time as the module completes its assigned task.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a communications system including a central controller coupled to a plurality of remote transceiver modules by a serial bus and, more particularly, to such a system where the modules remain in a sleep mode without consuming any power until such time as the central controller provides a wakeup signal over the bus. 
     Systems are known which include a central controller and a plurality of remote transceiver modules communicating with the central controller over a bus. It is common in such a system that the remote transceiver modules are normally in a low power consuming standby mode and at regular intervals “wake up” to look for an interrogation signal placed on the bus by the central controller. If no such interrogation signal is recognized, the module returns to its standby mode. However, even while it is in a standby mode, the module consumes power. There are applications where such power consumption is undesirable. For example, in a system where the modules are utilized to monitor battery systems and each module receives its operating power from the batteries which it is monitoring, the aforedescribed approach results in unacceptable battery drain. Accordingly, it would be desirable to have a system of the type described wherein the remote modules do not consume any power whatsoever while in the standby mode. 
     SUMMARY OF THE INVENTION 
     According to the present invention, there is provided an electronic system having a central controller, at least one remote transceiver module, and a serial bus interconnecting the central controller and all of the remote transceiver modules. Each module includes a source of power and power supply circuitry adapted to provide power for operating the module when the power supply circuitry is connected to the source of power. The central controller is adapted to transmit energy along the bus as a signal to all of the modules to change state to an active mode from a sleep mode in which each module consumes no power. Each module further includes an energy detector coupled to the bus and adapted to connect the power supply circuitry to the source of power upon detection of energy on the bus. 
     In accordance with an aspect of this invention, the bus is a continuous twisted pair of wires coupled together at an end remote from the central controller. Each module includes a transformer having a ferrite core extending through the twisted pair of wires so that the primary winding of the transformer is a single turn of the bus wires, with the transformer further having a secondary winding coupled to the energy detector. 
     In accordance with another aspect of this invention, the power supply circuitry includes a transformer to provide galvanic separation between the source of power and the power provided by the power supply circuit. 
     Further according to this invention, each module includes a winding inductively coupled to the bus for selectively effecting communication between the module and the central controller, and each module is arranged to short its winding when that module is not communicating with the central controller. Accordingly, the bus is minimally loaded by those modules not communicating with the central controller. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing will be more readily apparent upon reading the following description in conjunction with the drawings in which like elements in different figures thereof are identified by the same reference numeral and wherein: 
     FIG. 1 is an overall block diagram showing a system constructed in accordance with the principles of this invention; 
     FIG. 2 is a block diagram showing a remote transceiver module for the system shown in FIG. 1; 
     FIG. 3 is a schematic diagram showing the wakeup circuitry and the power supply circuitry of the module shown in FIG. 2; 
     FIG. 4 is a schematic diagram showing the receive and transmit circuitry of the module shown in FIG. 2; 
     FIG. 5 shows illustrative signal waveforms used in the system of FIG. 1; and 
     FIG. 6 is a schematic diagram showing a portion of the central controller illustrating how the central controller is coupled to the bus. 
    
    
     DETAILED DESCRIPTION 
     Referring now to the drawings, FIG. 1 shows a system constructed in accordance with the principles of this invention. As shown, the inventive system includes a central controller  10  and a plurality of remote transceiver modules  12 . A serial bus  14  is used to couple the central controller  10  with the modules  12 . Illustratively, the bus  14  is a continuous twisted pair of wires coupled together at an end  16  which is remote from the central controller  10 . As shown, the twisted pair of wires are merely shorted together at the end  16 , but in some applications the bus  14  would be terminated at the end  16  in its characteristic impedance. To couple each of the modules  12  to the bus  14 , each of the modules  12  is provided with a respective ferrite core  18  which is split and preferably of a self-shielding “square” or “pot” configuration. To couple each ferrite core  18  to the bus  14 , at the location of each module  12  the twisted pair of wires of the bus  14  is spread apart and slid over the center pole of the associated ferrite core  18  to provide a single turn primary of a transformer. Accordingly, signals placed on the bus  14  by the central controller  10  are sensed by all of the modules  12 . Windings on the core  18  within the module  12  are used both to pick off signals placed on the bus  14  by the central controller  10  or to place signals on the bus  14  for transmission to the central controller  10 , as will be described. 
     According to the present invention, each of the modules  12  is arranged to remain in a sleep mode in which it consumes no power whatsoever until such time as a “wakeup” signal is received over the bus  14  from the central controller  10 . Each module  12  then changes state into an active mode during which it receives data signals placed on the bus  14  by the central controller  10  and places data signals on the bus  14  for receipt by the central controller  10 . When all such activity is terminated, each module  12  returns to its sleep mode until such time as the central controller  10  again places a wakeup signal on the bus  14 . Thus, power is consumed by each module  12  only during the time it is in the active mode. 
     FIG. 2 is a block diagram showing a module  12 , constructed according to the present invention. The module  12  includes power supply circuitry  20  which provides power for operating the module  12  when the power supply circuitry  20  is connected to a source of power (not shown in FIG.  2 ). The wakeup circuitry  22  is connected to a winding  24  which is wound on the ferrite core  18  and operates to sense energy applied to the bus  14  by the central controller, in the form of the wakeup signal, to cause the power supply circuitry  20  to be connected to the source of power. When the power supply circuitry  20  is connected to the source of power, it provides power to the microprocessor  26 , which acts as the controller for the module  12 , and to the receive circuitry  28  and the transmit circuitry  30 . 
     As illustrated by the broken lines, the receive circuitry  28  and the transmit circuitry  30  share some common circuitry, as will be described. Upon the provision of power to the microprocessor  26 , the module  12  changes state from its sleep mode to its active mode. The receive circuitry  28  and the transmit circuitry  30  are connected to the winding  32  wound on the ferrite core  18  so that the receive circuitry  28  can receive signals placed on the bus  14  by the central controller  10  and the transmit circuitry  30  can place signals on the bus  14  for receipt by the central controller  10 . The microprocessor  26  is adapted to respond to instructions placed on the bus  14  by the central controller  10 , in the form of data signals processed by the receive circuitry  28  and passed along to the microprocessor  26 , to perform a task, which may include monitoring some peripheral equipment, and then transmit information back to the central controller  10  over the bus  14  by means of the transmit circuitry  30 . At the end of each such task, the microprocessor  26  is arranged to disconnect the power supply circuitry  20  from the source of power, thereby returning the module  12  to its sleep mode. 
     FIG. 3 illustrates circuitry implementing the wakeup circuitry  22  and the power supply circuitry  20 . It will be recalled that when the module  12  is in its sleep mode, the power supply circuitry  20  is not connected to the source of power. As shown in FIG. 3, the source of power is illustratively a battery having a positive terminal  34  and a negative terminal  36 . In an application where the modules  12  are used to monitor battery systems, the terminals  34 ,  36  can be terminals of the batteries being monitored. In any event, the transistor  38  operates as a normally open switch coupled in series between the battery terminal  34  and the power supply controller  40 . As will be described, upon receipt of a wakeup signal on the bus  14  from the central controller  10 , the transistor  38  becomes conductive. 
     Illustratively, the wakeup signal provided on the bus  14  by the central controller  10  is a twenty kilohertz current squarewave having a duration of approximately one second. This signal is transformed by the winding  24 , which illustratively is a two hundred turn center tapped winding, and converted by the diodes  42 ,  44  into a substantially constant current on the lead  46  to the P-channel JFET device  48 , which acts as a normally closed switch. The current then passes through the light emitting diode  50  in the optocoupler  52 . Light emitted by the diode  50  is received at the base of the phototransistor  54 , which becomes conductive and causes the transistor  38  to likewise conduct. With the transistor  38  conducting, the power source is connected to the power supply controller  40 . The voltage regulator  55  senses the voltage across the power supply controller  40  and limits the current through the phototransistor  54  and the transistor  38  to maintain a constant voltage across the power supply controller  40 . The power supply controller  40  controls the N-channel MOSFET device  56  to charge the primary winding  58  of the transformer  60  with current. The secondary windings  62 ,  64 ,  66  of the transformer  60  are connected through the diodes  68 ,  70 ,  72 , respectively, to filter and regulator  74 , filter  76  and filter  78 , respectively, to provide voltages on the leads  80 ,  82 ,  84 , respectively, for powering the module  12 . The use of the transformer  60  maintains a galvanic separation between the power source terminals  34 ,  36  and the power supply output on the leads  80 ,  82 ,  84 . 
     When the microprocessor  26  receives power from the power supply circuitry  20 , it turns on and goes into its active mode. At such time, it places a low signal on the lead  86 , which causes the transistor  88  to become conductive. Thus, the transistor  88  functions as a normally open switch, and when it “closes” by becoming conductive, it provides a path for current to flow from the power supply output V DD  (lead  80 ) through the light emitting diode  50 . At the same time, this causes the device  48  to become non-conductive. As long as the power supply circuitry  20  is providing power to the module  12 , the transistor  88  remains conductive to allow current to flow through the light emitting diode  50  through the resistor  89 . This maintains the conductivity of the phototransistor  54 , which keeps the transistor  38  conductive and connects the source of power to the power supply circuitry. In effect, the wakeup circuitry  22  functions as a latching relay. When the microprocessor  26  determines that the task of the module  12  is completed, it removes the low signal from the lead  86 . Accordingly, the transistor  88  turns off and stops the flow of current through the light emitting diode  50 . In the absence of current through the light emitting diode  50 , the transistor  54  becomes non-conductive, opening the path provided by the transistor  38 , and disconnecting the power supply circuitry  20  from the power source terminals  34 ,  36 . Without power on the leads  80 ,  82 ,  84 , the module  12  reverts to its sleep mode. 
     FIG. 4 shows the receive circuitry  28  and the transmit circuitry  30 . The receive and transmit circuitry  28 ,  30  share the amplifier  90 , since they are not both active at the same time. For communication over the bus  14  with the central controller  10 , the winding  32  on the ferrite core  18  is divided into two parts. The first part  92  of the winding  32  is used for receiving signals transmitted by the central controller  10  and illustratively has one hundred turns, while the second part  94  of the winding  32  is used for transmitting signals to the central controller  10  and illustratively has forty turns. When the module  12  is in the receive mode, the microprocessor  26  places an appropriate signal on the lead  96  to close the switch  98  and connect the first part  92  of the winding  32  to the amplifier  90 . In the feedback loop of the amplifier  90 , the Zener diodes  100 ,  102  provide a clamping function because the current on the bus  14  varies depending on its length. The diodes  104 ,  106  speed up the switching of the amplifier  90 . The output of the amplifier  90  is provided to the microprocessor  26  over the lead  108 . At the end of the receive mode, the microprocessor  26  removes the signal from the lead  96  to open the switch  98 . 
     When the module  12  is in the transmit mode, the microprocessor  26  provides an appropriate signal on the lead  110  to close the switch  112  and connect the output of the amplifier  90  to the second part  94  of the winding  32 , through the resistor  114 , which limits the current through the winding part  94  when the switch  112  is closed but the transmitter is idle. When the module  12  is transmitting, the microprocessor  26  provides data signals on the input lead  116  to the exclusive OR gate  118  and provides half-bit signals on the input lead  120  to the exclusive OR gate  118 . The formats of the data and half-bit signals are shown in FIG.  5 . As shown, the data stream is a start bit followed by eight data bits followed by a stop bit. The half-bit signal is a pulse train having two transitions for each data bit to insure that the duty cycle of the resulting bit stream on the bus  14  is always 50%. 
     FIG. 6 shows a portion of the central controller  10  and how it is coupled to the bus  14 . As shown, the bus  14  is terminated by a winding  122  on a core  124 . The central controller  10  includes a transmit winding  126  on the core  124  and a receive winding  128  on the core  124 . Illustratively, the windings  122 ,  126 ,  128  all have forty turns. When transmitting on the bus  14 , the central controller  10  places a transmit enable signal on the lead  130 , which is one input of the exclusive NOR gate  132 . The other input to the exclusive NOR gate  132  is over the lead  134  from the output of the exclusive NOR gate  136 . The inputs to the exclusive NOR gate  136  are data signals on the lead  138  and a half-bit pulse train on the lead  140 . The function of the half-bit pulse train has been discussed above. The output of the exclusive NOR gate  136  is provided as an input to the current amplifier  142  and the output of the exclusive NOR gate  132  is provided as an input to the current amplifier  144 . The amplifiers  142 ,  144  provide complementary signals on their outputs through the resistors  146  and  148 , respectively, to the transmit winding  126 . 
     With the transmit enable signal present on the lead  130 , the transistor  150  is non-conductive, so that no current flows through the light emitting diode  152 . When the transmit enable signal is taken away from the lead  130 , the transistor  150  conducts, allowing the light emitting diode  152  to conduct and emit light, thereby closing the photosensitive switch  154 . The central controller  10  can then receive signals placed on the bus  14  by one of the modules  12 , via the receive winding  128  and the amplifiers  156  and  158 . 
     When the wakeup signal is transmitted over the bus  14  by the central controller  10 , all of the modules  12  change state to the active mode. However, the central controller  10  only communicates with one of the modules  12  at any given time. It does this by transmitting a signal over the bus  14  identifying a particular module with which it wishes to communicate. The other modules remain in their active state but are off-line. These off-line modules do not load the bus  14  because their secondaries are shorted by the switch  98 . 
     Accordingly, there has been disclosed a communications system including a central controller coupled to a plurality of remote transceiver modules by a serial bus wherein the modules remain in a sleep mode without consuming any power until such time as the central controller provides a wakeup signal over the bus. While an illustrative embodiment of the present invention has been disclosed herein, it is understood that various adaptations and modifications to the disclosed embodiment are possible, and it is intended that this invention be limited only by the scope of the appended claims.