Abstract:
A system for measuring the stability of a power signal from a power supply includes a threshold violation detector. The threshold violation detector includes a comparator and an indicator. The comparator has a power signal input, a threshold signal input, and a comparison result output, and is configured to compare the power signal on the power signal input with a threshold on the threshold signal input to present a comparison result signal on the comparison result output. The indicator has a threshold violation output and a comparison input that receives the comparison result signal from the comparator. The indicator presents a threshold violation signal on the threshold violation output when the comparison result signal indicates that the power signal has violated the threshold.

Description:
TECHNICAL FIELD  
         [0001]    This invention relates to measuring power supply stability.  
         BACKGROUND  
         [0002]    Ideal power supplies maintain a constant output over an infinite range of loads. Real power supplies, on the other hand, will deliver an output that varies with, for example, the load on the supply, temperature, and line-voltage. For voltage power supplies, as supply current requirements increase and supply voltages decrease, minimizing output voltage variations generally becomes more difficult.  
           [0003]    This problem is particularly germane to the microelectronics industry, where each generation of devices tends to require more current to operate at lower voltages than the previous generation. Moreover, as the load current increases, the magnitude of the voltage droop due to parasitic impedance of the package, socket, and motherboard interconnects also increases. As a result, it has become increasingly difficult to maintain on-die supply voltage levels within windows in which device performance is acceptable.  
         DESCRIPTION OF DRAWINGS  
         [0004]    [0004]FIG. 1 is a block diagram of a threshold violation detector and a power supply.  
           [0005]    [0005]FIG. 2 is a block diagram of the detector.  
           [0006]    [0006]FIG. 3 is a block diagram of a comparator for use in the detector.  
           [0007]    [0007]FIG. 4 is a block diagram of a latch for use in the detector.  
           [0008]    [0008]FIG. 5 is a graph illustrating an exemplary operation of the detector.  
           [0009]    [0009]FIG. 6 is a block diagram of another latch for use in the detector.  
           [0010]    [0010]FIG. 7 is a flow chart of a method for determining sensitivity of the detector.  
           [0011]    [0011]FIG. 8 is a graph illustrating exemplary waveforms during the determination of the sensitivity of the detector.  
           [0012]    [0012]FIG. 9 is a graph illustrating exemplary sensitivity curves obtained during the determination of the sensitivity of the detector.  
           [0013]    [0013]FIG. 10 is a flow chart of a method for measuring noise amplitude using the detector.  
           [0014]    [0014]FIG. 11 is a graph illustrating exemplary waveforms during the measurement of noise amplitude using the detector.  
           [0015]    [0015]FIG. 12 is a block diagram of another detector.  
           [0016]    [0016]FIG. 13A is a graph illustrating exemplary input waveforms during the operation of the other detector.  
           [0017]    [0017]FIG. 13B is a graph illustrating an exemplary output waveform during the operation of the other detector with the input waveforms of FIG. 13A. 
       
    
    
       [0018]    Like reference symbols in the various drawings indicate like elements.  
       DETAILED DESCRIPTION  
       [0019]    Referring to FIG. 1, a threshold violation detector  100  is connected to a voltage power supply  102 . Inputs to detector  100  are the output  112  (V IN ) of the power supply  102 , a reference voltage  114  (V REF ), and a reset voltage  116  (V RESET ). Detector  100  has a single output  118  (V OUT ). The input  112  (V IN ) provides the detector  100  with the varying output of power supply  102  that is to be monitored by the detector  100 . Input  114  (V REF ) presents a threshold reference voltage against which the varying output is compared. Input V RESET    116  presents a reset signal to detector  100 . Output  118  (V OUT ) carries a detector output voltage that indicates when the supply voltage on input  112  (V IN ) has crossed the threshold reference voltage on input  114  (V REF ). Output  118  (V OUT ) may be reset using the reset signal on input  116  (V RESET ), as discussed further below. Detector  100  may be implemented on-die with a microprocessor or other integrated circuits. For example, detector  100  may be implemented using CMOS devices.  
         [0020]    Referring to FIG. 2, one implementation of the detector  100  includes a comparator  200  and a RS latch  205 . Comparator  200  receives the inputs  112  (V IN ) and  114  (V REF ), and presents an output  210  (V SET ) to RS latch  205 . RS latch  205  has inputs  210  (V SET ) and  116  (V RESET ), and output  118  (V OUT ). Comparator  200  includes an amplifier  215  and an inverter  220 .  
         [0021]    The non-inverting input  225  of amplifier  215  receives the threshold reference voltage on input  114  (V REF ) and the inverting input  230  of amplifier  215  receives the supply voltage on input  112  (V IN ). Amplifier  215  also has an amplifier output  235  that presents an amplifier output voltage to inverter  220 .  
         [0022]    Amplifier  215  amplifies the voltage difference between the supply voltage on inverting input  230  and the threshold reference voltage on non-inverting input  225  to generate an amplifier output voltage on amplifier output  235 . The influence of the open loop gain of amplifier  215  is discussed in regard to FIGS. 8 and 9.  
         [0023]    Inverter  220  receives the amplifier output voltage and presents a set voltage to RS latch  205  on output  210  (V SET ). In particular, when the amplifier output voltage indicates that the threshold reference voltage on non-inverting input  225  is greater than the supply voltage on inverting input  230 , inverter  220  presents a logic low set voltage on output  210  (V SET ), and, when the amplifier output voltage indicates that the threshold reference voltage on non-inverting input  225  is less than the supply voltage on inverting input  230 , inverter  220  presents a logic high set voltage on output  210  (V SET ).  
         [0024]    RS latch  205  has inputs  210  (V SET ) and  116  (V RESET ), and output  118  (V OUT ). A logic high reset signal on input  116  (V RESET ) resets RS latch  205  when the set voltage  210  (V SET ) indicates that the supply voltage on input  112  (V IN ) is on the acceptable side of the threshold reference voltage on input  114  (V REF ). Resetting drives the detector output voltage on output  118  (V OUT ) to logic low. After the reset signal on input  116  (V RESET ) transitions to logic low, RS latch  205  maintains a logic low output voltage on output  118  (V OUT ) until the set voltage on input  210  (V SET ) transitions to indicate that the supply voltage on input  112  (V IN ) is on the unacceptable side of the threshold reference voltage on input  114  (V REF ). At this time, RS latch  205  presents a logic high output voltage on output  118  (V OUT ). RS latch  205  maintains the logic high output voltage on output  118  (V OUT ) until RS latch  205  is reset by another logic high reset signal applied to input  116  (V RESET ).  
         [0025]    Referring to FIG. 3, the amplifier  215  of comparator  200  may include a cascade of a first differential amplifier  300 , a second differential amplifier  305 , and an analog inverter  310 . First differential amplifier  300  includes non-inverting input  225 , inverting input  230 , a negative output  0   −   315 , and a positive output  0   +   320 . Second differential amplifier  305  has a non-inverting input  325  connected to the negative output  0   31  of amplifier  300 , an inverting input  330  connected to the positive output  0   + of amplifier  300 , and a positive output  0   +   335 . Analog inverter  310  includes an input  340  connected to the output of amplifier  305  and an output  345 .  
         [0026]    First differential amplifier  300  receives input  112  (V IN ) on inverting input  230  and input  114  (V REF ) on non-inverting input  225  and presents a first output voltage on negative output  0   31    315  and a second output voltage on positive output  0   +   320 . First differential amplifier  300  amplifies the difference between the threshold reference voltage on non-inverting input  225  and the supply voltage on inverting input  230  with negative gain to produce the first output voltage on negative output  0   −   315  and with positive gain to produce the second output voltage on positive output  0   +   320 .  
         [0027]    Second differential amplifier  305  receives the first output voltage of first differential amplifier  300  on non-inverting input  325  and the second output voltage of first differential amplifier  300  on inverting input  330  and produces an output voltage on positive output  0   +   335 . Second differential amplifier  305  amplifies the difference between the first output voltage on non-inverting input  325  and the second output voltage on inverting input  330  with positive gain to produce the output voltage on positive output  0   +   335 .  
         [0028]    Analog inverter  310  receives the output voltage of second differential amplifier  305  on input  340  and presents an inverted output voltage on output  345 . The cascade of first differential amplifier  300 , second differential amplifier  305 , and analog inverter  128  increases the net open loop gain of amplifier  215 . Moreover, the use of both positive and negative outputs  315 ,  320  of first differential amplifier  300  improves the tolerance of amplifier  215  to variability in the supply voltages and manufacturing processes.  
         [0029]    Referring to FIG. 4, RS latch  205  which is adapted for maximum detection, includes inputs  210  (V SET ) and  116  (V RESET ) and output  118  (V OUT ). As shown, RS latch  205  may be implemented using inverters I 1   400 , I 2   405 , I 3   410 , I 4   415 , transistors M 1   420 , M 2   425 , M 3   430 , M 4   435 , M 5   440 , M 6   445 , and nodes  450 ,  455 . RS latch  205  is supplied with a positive supply voltage on a supply line  460 . When the set voltage on input  210  (V SET ) is logic low, transistors M 4   435  and M 1   420  turn off. When the set voltage on  210  (V SET ) is logic high, transistors M 4   435  and M 1   420  turn on. When the reset voltage on  116  (V RESET ) is logic low, transistors M 2   425  and M 3   430  turn off. When the set voltage on  116  (V RESET ) is logic high, transistors M 2   425  and M 3   430  turn on.  
         [0030]    A logic high reset signal on input  116  (V RESET ) while the set voltage on input  210  (V SET ) is logic low resets RS latch  205 . Namely, since the set voltage on input  210  (V SET ) is logic low, transistors M 4   435  and M 1   420  are turned off and the logic high reset signal on input  116  (V RESET ) turns on transistors M 2   425  and M 3   430 . This draws the voltage on node  450  to logic low and the voltage on node  455  toward logic high. As the voltage on node  455  moves toward logic high, it turns transistor M 6   445  on and draws the detector output voltage on output  118  (V OUT ) to logic low.  
         [0031]    Once the reset signal on input  116  (V RESET ) changes to logic low, transistors M 2   425  and M 3   430  turn off. However, RS latch  205  maintains a logic low output voltage on output  118  (V OUT ). In particular, inverters I 3   410  and I 4   415  maintain the voltage on node  450  at logic low and the voltage on node  455  at logic high.  
         [0032]    The logic low output of RS latch  205  is maintained until the set voltage on input  210  (V SET ) transitions to logic high and turns on transistors M 4   435  and M 1   420 . This draws the voltage on node  450  toward logic high and the voltage on node  455  to logic low. The logic low voltage on node  455  turns off transistor M 6   445 , allowing transistor M 5   440  to draw the output voltage on output  118  (V OUT ) toward a logic high output voltage.  
         [0033]    once the set signal on input  210  (V SET ) changes to logic low, Transistors M 4   435  and M 1   420  turn off. However, RS latch  205  maintains a logic high output voltage on output  118  (V OUT ) In particular, inverters I 3   410  and I 4   415  maintain the voltage on node  450  at logic high and the voltage on node  455  at logic low. This maintenance continues until a logic high reset signal on input  116  (V RESET ) resets RS latch  205 , as discussed above.  
         [0034]    Exemplary time traces of a threshold reference voltage V REF , a reset voltage V RESET , a detector input voltage V IN , and a detector output voltage V OUT  during operation of detector  100  are shown in FIG. 5. Threshold reference voltage V REF  defines, for example, the uppermost acceptable output voltage of a power supply. Reset voltage V RESET  resets RS latch  205  of detector  100  when, for example, detector  100  is powered up or a predetermined time after detector  100  has detected a threshold crossing. Input voltage V IN  is, for example, the supply voltage output by power supply  102 . Detector output voltage V OUT  indicates when input voltage V IN  crosses threshold reference voltage V REF .  
         [0035]    Referring to FIGS.  2 - 5 , at a time T1, detector input voltage V IN  is below threshold reference voltage V REF . The set voltage (not shown) on input  210  (V SET ) is thus logic low, and the reset voltage V RESET  is logic high. This resets detector  100 , drawing the detector output voltage V OUT  to logic low.  
         [0036]    At time T2, reset voltage V RESET  changes to logic low. However, RS latch  205  maintains output voltage V OUT  at logic low until time T3 when input voltage V IN  rises above threshold reference voltage V REF . The set voltage (not shown) on input  210  (V SET ) rises to logic high which draws the detector output voltage V OUT  to logic high at time T4.  
         [0037]    Referring to FIGS. 4 and 5, the components of RS latch  205  may be configured to increase the bandwidth of the detector. In particular, transistors M 1   420 , M 4   435  may be made small so that they are able to respond more quickly to a change in the set voltage on input  210  (V SET ). Smaller transistors M 1   420 , M 4   435  decrease the parasitic capacitive load on the set voltage, leading to higher bandwidth. Transistors M 1   420 , M 4   435  may have, for example, an input capacitance smaller than 1×10 −14  F. Furthermore, transistor M 6   445  may also be made small to speed the response to a change in the voltage on node  455 . Transistor M 6   445  may also have, for example, an input capacitance smaller than 1×10 −14  F. As a consequence of such sizing of components, the input capacitance of input  210  (V SET ) may be made smaller than the input capacitance of  116  (V RESET ).  
         [0038]    The trip points of inverters I 3   410 ,  14   415  may also be selected to increase the bandwidth of the detector. In particular, I 3   410  may be configured to have a trip point below the midpoint between logic high and logic low and I 4   415  may be configured to have a trip point above the midpoint between logic high and logic low. In general, the trip point of an inverter may be configured, for example, by sizing the transistors of the inverter. For example, making a pMOS device larger may increase the trip point, and making an nMOS device larger may decrease the trip point. The trip point of inverter I 3   410  may be above logic low by, for example, less than 35% of the difference between logic high and logic low, and the trip point of inverter I 4   415  may be above logic low by, for example, greater than 65% (for example, 70%) of the difference between logic high and logic low.  
         [0039]    Referring to FIG. 6, another RS latch  600 , adapted for minimum detection, is laid out similarly to RS latch  205 . RS latch  600  includes inputs  210  (V SET ) and  116  (V RESET ) and output  118  (V OUT ). As shown, RS latch  600  may be implemented using inverters I 1   602 , I 2   605 , I 3   610 , I 4   615 , transistors M 1   620 , M 2   625 , M 3   630 , M 4   635 , M 5   640 , M 6   645 , and nodes  650 ,  655 . RS latch  600  is supplied with a positive supply voltage on a supply line  660 . RS latch  600  differs from RS latch  205  in that inverter I 1   602  has been shifted from between input  210  (V SET ) and transistor M 1   620  to between input  210  (V SET ) and transistor M 4   635 . As a result of this shift, transistors M 4   635  and M 1   620  turn on when the set voltage on  210  (V SET ) is logic low, and transistors M 4   635  and M 1   620  turn off when the set voltage on  210  (V SET ) is logic high.  
         [0040]    A logic high reset signal on input  116  (V RESET ) while the set voltage on  210  (V SET ) is logic high resets RS latch  600 . Namely, since the set voltage on input  210  (V SET ) is logic high, transistors M 4   635  and M 1   620  are turned off and the logic high reset signal on input  116  (V RESET ) turns transistors M 2   625  and M 3   630  on. This draws the voltage on node  650  to logic low and the voltage on node  655  toward logic high. As the voltage on node  655  moves toward logic high, it turns transistor M 6   645  on and draws the detector output voltage on output  118  (V OUT ) to logic low.  
         [0041]    Once the reset signal on input  116  (V RESET ) changes to logic low, transistors M 2   625  and M 3   630  turn off but RS latch  600  maintains a logic low output voltage on output  118  (V OUT ). In particular, inverters I 3   610  and I 4   615  maintain the voltage on node  650  at logic low and the voltage on node  655  at logic high.  
         [0042]    This maintenance continues until the set voltage on input  210  (V SET ) transitions to logic low thereby turning on transistors M 4   635  and M 1   620 . This draws the voltage on node  650  toward logic high and the voltage on node  655  to logic low. The logic low voltage on node  655  turns off transistor M 4   635 , which allows transistor M 5   640  to draw the output voltage on output  118  (V OUT ) toward logic high. In other words, a logic high output voltage is presented on output  118  (V OUT ).  
         [0043]    Once the set signal on input  210  (V SET ) changes to logic high, transistors M 4   635  and M 1   620  turn off. However, RS latch  600  maintains a logic high output voltage on output  118  (V OUT ). In particular, inverters I 3   610  and I 4   615  maintain the voltage on node  650  at logic high and the voltage on node  655  at logic low. This maintenance continues until a logic high reset signal on input  116  (V RESET ) resets RS latch  600 , as discussed above.  
         [0044]    [0044]FIGS. 7 and 8 illustrate a process flow  700  for determining a sensitivity curve for detector  100  when adapted for maximum detection. Process flow  700  may be implemented using, for example, a pair of voltage sources, a pulse generator, and a microcomputer with an output capable of communicating with the pulse generator and inputs capable of at least measuring the logic state of V OUT  and the output voltages of the voltage sources. Initially, threshold reference voltage V REF  and supply voltage V IN  are presented to detector  100  using the voltage sources configured such that threshold reference voltage V REF  is greater than supply voltage V IN  ( 710 ). Next, a parameter determining the width of a test pulse is set to a predetermined minimum value (min width) ( 720 ) and a parameter determining the voltage of a test pulse is set to a predetermined minimum value (min voltage) ( 730 ).  
         [0045]    Detector  100  is reset ( 740 ) and a test pulse  810  is superimposed upon the supply voltage V IN  using, for example, the pulse generator in conjunction with a respective one of the voltage sources ( 750 ). Test pulse  810  has a width  850  determined by the width parameter and a voltage  860  determined by the voltage parameter. The logic state of detector output voltage V OUT  is then determined using, for example, an input of the microcomputer and examined ( 760 ). If detector output voltage V OUT  is logic low, then the parameter determining the voltage is increased ( 770 ) and a further test pulse  820  with an increased voltage  860  is superimposed on the supply voltage V IN  ( 770 ). This may be repeated as many times as needed. In other words, the parameter determining the voltage is successively increased and further test pulses  830  and  840  are generated until detector output voltage V OUT  is logic high. When this happens, the values of the parameter determining the voltage and the parameter determining the width are recorded ( 780 ).  
         [0046]    Next, the relationship between the current parameter determining the width and a predetermined maximum value (max width) is determined ( 790 ). If the parameter determining the width is less than the maximum value (max width), then the parameter determining the width is increased ( 795 ) and the voltage parameter is reset to the minimum value ( 730 ). The process is repeated as needed until the parameter determining the width is equal to the maximum value (max width), at which time process flow ends.  
         [0047]    Referring to FIG. 8, although supply voltage V IN  is greater than threshold reference voltage V REF  during pulse  830  by a differential voltage  870 , detector output voltage V OUT  remains logic low during pulse  830 . This may be due to, for example, amplifier  215  having an open loop gain that is too small to amplify the relatively small difference between supply voltage V IN  and threshold reference voltage V REF . Alternatively, the bandwidth of amplifier  215  and latch  205  may be too small to be able to capture a pulse of width  850 , or amplifier  215  may have a positive input offset V OFFSET  (not shown) that increases the actual threshold voltage of amplifier  215  above V REF . The combined influence of the open loop gain of amplifier  215 , the bandwidth of amplifier  215  and latch  205 , an input offset, and other detector parameters may be determined empirically using process flow  700  and is referred to simply as the “sensitivity” of the detector.  
         [0048]    [0048]FIG. 9 illustrates exemplary sensitivity curves  910 ,  920  obtained using process flow  700  of FIG. 7. Sensitivity curves  910 ,  920  illustrate, for two different detectors, the minimum voltage differences between supply voltage V IN  and threshold reference voltage V REF  (voltage  860  of FIG. 8) that drive detector output voltage V OUT  to logic high as a function of pulse width (width  850  of FIG. 8). Sensitivity curve  910  is obtained with a relatively sensitive detector with a cut-off width  911 , whereas sensitivity curve  920  is obtained with a relatively insensitive detector with a cut-off width  921 . When the pulse width is larger than width  911 , the relatively sensitive detector responds to a small voltage overshoot by supply voltage V IN  beyond threshold reference voltage V REF . However, pulse width must be larger than width  921  for the relatively insensitive detector to respond to the same relatively small voltage overshoot. For either detector, pulse widths below the respective cut-off width  911 ,  921  require larger voltage differences between supply voltage V IN  and threshold reference voltage V REF . The required voltage differences increase as pulse width decreases.  
         [0049]    As discussed above, the structural components of comparator  200  and RS latch  205  may be configured to increase the overall sensitivity of detector  100 .  
         [0050]    [0050]FIGS. 10 and 11 illustrate a process flow  1001  for measuring noise amplitude of a device such as, for example, a power supply, using detector  100 . Process flow  1001  may be implemented using, for example, an adjustable voltage source and a microcomputer with a D/A converter and an input port capable of measuring the logic state of V OUT . The device and detector are assembled, for example, as shown in FIG. 1.  
         [0051]    Initially, threshold reference voltage V REF  is presented to detector  100  using the adjustable voltage source such that the operator believes that the threshold reference voltage V REF  is greater than supply voltage V IN  ( 1010 ). Next, detector  100  is reset at time T5 ( 1020 ) and the logic state of detector output voltage V OUT  is determined using, for example, the input port of the microcomputer and examined ( 1030 ). If detector output voltage V OUT  is logic high, then the threshold reference voltage V REF  has not been set sufficiently greater than supply voltage V IN , and the threshold reference voltage V REF  is increased ( 1040 , not shown in FIG. 11). This process is repeated to increase threshold reference voltage V REF  until V OUT  remains logic low for a predetermined period. When this happens, the threshold reference voltage V REF  is decreased at time T6 ( 1050 ). The magnitude of the decrease  1100  ( 1050 ) may be smaller than the magnitude of the previous increase ( 1040 ). The logic state of detector output voltage V OUT  is again examined for a predetermined period from time T6 to time T7 ( 1060 ). If detector output voltage V OUT  is logic low, then threshold reference voltage V REF  is decreased again at time T7. Threshold reference voltage V REF  is repeatedly decreased until detector output voltage V OUT  is logic high. When this happens at time T8, the current V REF  is recorded ( 1070 ) and the process flow  1001  ends.  
         [0052]    Referring to FIG. 12, another detector  1200  includes a maximum detector  1205 , a minimum detector  1210 , and a NOR gate  1215 . Maximum detector  1205  may be, for example, a detector  100  including a comparator  200  and a RS latch  205 , as described above. Minimum detector  1210  may be, for example, a detector  100  including a comparator  200  and a RS latch  600 , as described above.  
         [0053]    Detector  1200  has inputs V IN    1220 , V MAX    1225 , V MIN    1230 , and V RESET    1235 , nodes  1240 ,  1245 , and an output PWR_GOOD  1250 . Input V IN    1220  presents an input voltage to detector  1200  and may be connected, for example, to the voltage supply output of a power supply. Input V MAX    1225  presents a maximum reference voltage to detector  1200 . Input V MIN    1230  presents a minimum reference voltage to detector  1200 . Input V RESET    1235  presents a reset signal to detector  1200 . Node  1240  carries a maximum detector output voltage that indicates when the voltage on input V IN    1200  is greater than the maximum threshold reference voltage on input V MAX    1225 . Node  1245  carries a minimum detector output voltage that indicates when the supply voltage on input V IN    1200  is less than the minimum threshold reference voltage on input V MIN    1220 . Nodes  1240 ,  1245  may be reset using the reset signal on input V RESET    1235 . Output PWR_GOOD  1250  carries a detector output voltage that is logic low when either or both of the maximum detector output voltage on node  1240  and the minimum detector output voltage on node  1245  is logic high.  
         [0054]    [0054]FIGS. 13A and 13B illustrate exemplary input waveforms and an exemplary output waveform, respectively, during the operation of detector  1200 . Exemplary time traces show a maximum threshold reference voltage V MAX 00 , a minimum threshold reference voltage V MIN 00 , a detector input voltage V IN 00 , and a detector output voltage V OUT 00  during operation of detector  1200 . The difference between maximum threshold reference voltage V MAX 00  and minimum threshold reference voltage V MIN 00  defines a voltage band  1300  in which, for example, input voltage V IN 00  is within an acceptable range.  
         [0055]    Initially, for example at time T9, the input voltage V IN 00  is less than the maximum threshold reference voltage V MAX 00  and greater than the minimum threshold reference voltage V MIN 00 . a result, the maximum detector output voltage on node  1240  and the minimum detector output voltage on node  1245  are logic low (not shown), and the detector output voltage V OUT 00  is logic high. This continues until input voltage V IN 00  crosses one of the maximum threshold reference voltage V MAX 00  and the minimum threshold reference voltage V MIN 00 .  
         [0056]    In the illustrated example of FIG. 13A, input voltage V IN 00  falls below minimum threshold reference voltage V MIN 00  at time T10. This drives minimum detector output voltage on node  1245  to logic high (not shown), and the detector output voltage V OUT 00  to logic low where it is maintained until a logic high reset signal is presented (not shown) while the input voltage V IN 00  is less than the maximum threshold reference voltage V MAX 00  and greater than the minimum threshold reference voltage V MIN 00 .  
         [0057]    The output voltages of the detectors  100  and  1200  may be used, for example, to test a power supply and the power requirements of circuitry. For example, detectors  100  and  1200  may implemented on a CMOS die and used to determine if other circuitry on the die such as, e.g., a microprocessor causes unacceptably large fluctuations in a supply voltage. Such testing may be done, for example, during the debugging of die designs and the binning of parts.  
         [0058]    A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made. Accordingly, other implementations are within the scope of the following claims.