Abstract:
A method and apparatus for providing electrical output current. The method includes providing a supply current, providing a first and second voltage input signal for controlling output current and generating an output current based on a differential voltage measured between the first and second input voltage signals including increasing the supply current as the output current increase. The apparatus for providing electrical current includes biasing circuitry providing a biasing current I CC  and input circuitry including a first and second voltage input. The input circuitry is operable to receive the biasing current I CC  and to divide the biasing current I CC  based on the differential voltage measured between the first and second voltage inputs producing first and second biasing currents. A pair of translinear circuits is included that are operable to receive the first and second biasing currents and responsive thereto produce a first and second output current. The first and second output currents are summed to produce a final output current for the device where the final output current is a minimum of I CC  when the differential voltage is approximately zero volts.

Description:
The present invention relates generally to electrical circuits and, more particularly, to a voltage-controlled current source with a variable supply current. 
     BACKGROUND 
     In conventional electrical circuits, current sources are often essential to a circuit design. One especially useful form of a current source is a voltage-controlled current source, in which the output current is dependent upon an input differential voltage. Depending on the application, a current source may be required to support dramatically different loads. That is, the current source may be required to operate at a high current output level for one time period, then operate at a low current output level for another time period. Conventional voltage-controlled current sources that operate to source a wide range of current levels generally are designed to include a large standby current to support the large current output required during high output modes (cycles). In these applications, the large standby current must be maintained even if the output current is low. A high standby current may result in an inefficient use of power, and also may cause undesirable heating. 
     SUMMARY 
     In one aspect, the invention provides a method for providing electrical output current. The method includes providing a supply current, providing a first and second voltage input signal for controlling output current and generating an output current based on a differential voltage measured between the first and second input voltage signals including increasing the supply current as the output current increase. 
     In another aspect, the invention provides a device for providing electrical current and includes biasing circuitry providing a biasing current I CC  and input circuitry including a first and second voltage input. The input circuitry is operable to receive the biasing current I CC  and to divide the biasing current I CC  based on the differential voltage measured between the first and second voltage inputs producing first and second biasing currents. A pair of translinear circuits is included that are operable to receive the first and second biasing currents and responsive thereto produce a first and second output current. The first and second output currents are summed to produce a final output current for the device where the final output current is a minimum of I CC  when the differential voltage is approximately zero volts. 
     Aspects of the invention can include one or more of the following advantages. A current boost circuit is provided that can generate an output current that is based on the magnitude of a differential input voltage. The current boost circuit includes a supply current that increases as the output current increases. No standby high supply current is required when the output of the current boost circuit is low. The current boost circuit can be customized to increase or decrease gain characteristics of the device and limit current output for the device. 
     Other features and advantages of the invention will become apparent from the following description and from the claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram for a voltage-controlled current source in accordance with the invention. 
     FIG. 2 is a schematic diagram of an electrical circuit for an alternative implementation of a voltage-controlled current source. 
     FIG. 3 is a graph showing output current as a function of differential voltage for the circuit of FIG.  2 . 
     FIG. 4 is a schematic diagram of an electrical circuit for an alternative implementation of a voltage-controlled current source including resistors to provide degeneration. 
     FIG. 5 is a graph showing output current as a function of differential voltage for the circuit of FIG.  4 . 
     FIG. 6 is a schematic diagram of an electrical circuit for an alternative implementation of a voltage-controlled current source including blocking diodes. 
     FIG. 7 is a schematic diagram of an electrical circuit for an alternative implementation of a voltage-controlled current source including additional independent current sources and blocking diodes. 
     FIG. 8 is a schematic diagram of an electrical circuit for an alternative implementation of a voltage-controlled current source including additional independent current sources, degeneration and blocking diodes. 
     FIG. 9 is schematic diagram of an electrical circuit for an alternative implementation of a voltage-controlled current source including additional independent current sources and blocking diodes. 
     FIG. 10 is schematic diagram of an electrical circuit for an alternative implementation of a voltage-controlled current source including additional independent current sources, degeneration and blocking diodes. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 is block diagram showing the principal elements of a current boost device  100 . In one implementation current boost device  100  is mirror-symmetric, with a left half  36  and right half  38 . In one implementation, current boost device is constructed with plural transistors and includes an independent biasing current source  12  that may be used to bias the transistors into a desired state. The biasing current source  12  provides a constant current with a value of I CC  amperes. Circuits which may be used to create a biasing independent current source are well known to those skilled in the art. In one implementation, the transistors in current boost device  100  are bipolar junction transistors biased in the forward active state. 
     Current boost device  100  includes plural inputs including a first input voltage  16  (of value V1) and a second input voltage  18  (of value V2). Although the circuit&#39;s left half  36  and right half  38  may have identical hardware, they may operate differently by the application of varied input voltages. The first input voltage  16  is applied to the left half  36  and the second input voltage  18  is applied to the right half  38 . The sources of the input voltages are not shown. The input voltages are applied to half differential transconductance circuits  14 ,  15 , which together form a differential transconductance input pair. 
     If input voltages V1 and V2 are not equal to each other (a differential voltage V d  is not equal to zero, where V d =V1−V2) then the currents produced on each half of the circuit will not be equal. The current produced by the left half differential transconductance circuit  14  is designated I 101  and the current produced by the right half differential transconductance circuit  15  is designated I 102 . On one side of the differential pair (either of the left or right half  36 ,  38 ), the bias current I CC /2 plus some differential current I d  flows; on the other side, I CC /2 less the differential current I d  flows. 
     Current from each half differential transconductance circuit  14 ,  15  flows into translinear circuits  20 ,  26 , respectively. As will be shown below, each translinear circuit  20 ,  26  includes a current mirror, which requires that the translinear circuits share mirror voltages Vcm 101  and Vcm 102 . Translinear circuits  20 ,  26  also include an output stage. Currents from the left and right output stages are designated I 103  and  1104 , respectively. Currents  1103  and  1104  combine according to Kirchhoff&#39;s current law to produce the output current  34 , which has a value of I OUT  amperes. The direction of current flow shown is merely for reference and does not necessarily indicate the direction of positive current flow. 
     Referring now to FIG. 2, a circuit diagram for an implementation of current boost device  100  is shown. The circuitry for the current boost device resides between two power supplies, represented by voltages applied to nodes  10  and  32 . The sources of the power are not explicitly shown. The first power supply  10  has a value of V CC  volts and the second power supply  32  has a value of V EE  volts. In one implementation, the voltage of the first power supply  10  is higher than that of the second power supply  32 . Further, it is anticipated that the circuit will best function if V CC  is at a higher potential than V EE . 
     The current boost device  100  is mirror-symmetric. The differential transconductance circuits  14 ,  15  are represented as a differential pair of transistors QI 01 , Q 102  respectively. Coupled to bases of Q 101  and Q 102  are independent voltage sources  40 ,  42 , with values of V1, V2 respectively. In this implementation, translinear circuit  20  includes npn bipolar junction transistors Q 103 , Q 104 , Q 105 , Q 106  and Q 107 , while translinear Circuit  26  includes npn bipolar junction transistors Q 108 , Q 109 , Q 110 , Q 111  and Q 112 . 
     In the implementation shown, it is assumed that each transistor is near-ideal, i.e., with a very large amplification factor beta (β) and a negligible base current. A consequence of this assumption is that the each bipolar junction transistor&#39;s collector current is equal to its emitter current, and may be generally called the “current flowing through” the transistor. The current flowing through QI 01  is identified as I 101  and the current flowing through Q 102  is identified as I 102 . 
     Focusing upon the left half of the current boost device  100 , current I 101  flows through QI 01 , to and through diode-connected transistor Q 103  and diode-connected transistor Q 104 , and on to the second power supply  32 . Transistors Q 104  and Q 110  are an emitter-coupled pair, forming a current mirror. The bases of Q 104  and Q 110  share a common voltage, Vcm 101 . Because the base-to-emitter voltage (V BE ) of Q 104  is equal to the V BE  Of Q 110 , the collector currents of these transistors, I 101  and I 101 M, are equal in magnitude. The relation between collector current and base-to-emitter voltage is described in greater detail below. Consequently the amount of current I 101  flowing through Q 104  is mirrored to Q 110 , and flows through Q 110 , where it is designated I 101 M. The current flowing through Q 110  is drawn through Q 109 . As a result, current I 101 M flows through Q 109  and Q 110 , then to the second power supply  32 . 
     By a similar analysis, current I 102  flows through Q 102 , diode-connected transistor Q 111  and diode-connected transistor Q 112 , then to the second power supply  32 . Q 112  and Q 106  form a emitter-coupled current mirror, causing current I 102 M to flow through Q 106 . The current I 102 M is drawn through Q 105 . As a result, current I 102 M flows through Q 105  and Q 106 , then to the second power supply  32 . 
     In a bipolar junction transistor, the base-to-emitter voltage V BE  is approximately related to the collector current Ic by the non-linear equation 
     
       
           I   C   =I   S exp( V   BE   /V   T )  
       
     
     where I S  is the reverse saturation current (sometimes called the scale current) and V T  is the thermal voltage. V T  is dependent upon temperature. I S  is dependent upon several factors, such as temperature, doping densities and transistor geometry. Increasing collector current will cause an increase in the base-to-emitter voltage, all other factors being constant, and vice-versa. In the same way, a decrease in collector current will lead to a decrease in the base-to-emitter voltage, all other factors being constant and vice-versa. In analysis of this circuit, it may be assumed that I S  and V T  are identical for all transistors. 
     If the left side input voltage  40  is less than the right side input voltage  42 , then the magnitude of V BE  Of Q 101  will be greater than the magnitude of V BE  of Q 102 , and as a consequence I 101  will be greater than I 102 . I 101  will be I CC /2 plus some differential current I d , and I 102  will be I CC /2 less some differential current I d . In particular, 
     
       
         I 101 = I   CC /(1+exp( V   d   /V   T ))  
       
     
     where V d  is the differential voltage at the voltage inputs  16  and  18  (V1−V2). Similarly, 
     
       
         I 102 = I   CC /(1+exp(− V   d   /V   T ))  
       
     
     The differential current I d  is equal to (I 101 −I 102 )/2. The relationship between V d  and I d  is that of a hyperbolic tangent: 
     
       
           I   d =−( I   CC /2)tan h( V   d /V T )  
       
     
     Looking at the left half of the device, and assuming I 101  is greater than I 102 M, the base-to-emitter voltage drops of Q 103  and Q 104  will be greater than the base-to-emitter voltage drops of Q 105  and Q 106 . The effect is that the emitter voltage of Q 105  will be greater than the emitter voltage of Q 103 . Because the emitter voltage of Q 105  is the same as the base voltage of Q 107 , it follows that the base-to-emitter voltage of Q 107  will be greater than the individual base-to-emitter voltages of Q 103 , Q 104 , Q 105 , and Q 106 . Consequently the collector current flowing through Q 107  will be greater than the currents flowing through Q 103 , Q 104 , Q 105 , and Q 106 , according to the non-linear equation given above. 
     Looking at the right half of the circuit, and again assuming I 101  is greater than  1102 , the base-to-emitter voltage drops of Q 111  and Q 112  will be less than the base-to-emitter voltage drops of Q 109  and Q 110 . The effect is that the emitter voltage of Q 109  will be less than the emitter voltage of Q 111 . Because the emitter voltage of Q 109  is the same as the base voltage of Q 108 , it follows that the base-to-emitter voltage of Q 108  will be less than the individual base-to-emitter voltages of Q 109 , Q 110 , Q 111 , and Q 112 . Consequently the collector current flowing through Q 108  will be less than the currents flowing through Q 109 , Q 110 , Q 111 , and Q 112 , according to the non-linear equation given above. 
     By Kirchhoff&#39;s current law, the collector currents flowing through Q 107  and Q 108 , I 103  and  1104  respectively, add together to produce the output current I OUT . 
     As previously noted, the mathematical relationship between base-to-emitter voltage and collector current is not a linear one. As a consequence, the higher base-to-emitter voltage of Q 107  creates a higher collector current I 103 . The lower base-to-emitter voltage of Q 108  creates a lower collector current  1104 . Because of the nonlinear relationship, the increase in  1103  is far greater than the decrease in  1104 : 
     
       
           I   OUT   =I   CC (cos h(3 V   d/ 2 V   T ))/(cos h( V   d /2 V   T )).  
       
     
     As such, an output current is produced which varies according to the absolute value of the differential voltage. Because the hyperbolic cosine function is an even function, the relationship between the output current and the differential voltage is also an even function. For I 101 &gt;&gt;I 102 , the following approximation holds: 
     
       
           I   OUT ≈(I 101 ) 2 /(I 102 )  
       
     
     FIG. 3 shows the approximate relationship between the differential voltage and the output current I OUT . Output current is at a minimum when the two input voltages are identical, and the output current is not less than I CC . 
     The currents flowing into the second power supply  32  which supply V EE  may be summed: 
     
       
           I   TOTAL= 2 I   CC   +I   OUT =2 I   CC   +I   CC (cos h(3 V   d /2 V   T ))/(cos h( V   d /2 V   T ))  
       
     
     No standby current is required. The current flowing into the second power supply increases only as I OUT  increases, and I OUT  increases as the magnitude of the differential voltage V d  increases. 
     FIG. 4 shows an alternative implementation of the invention. Resistors RI 01  and R 102  are coupled between the current bias source  12  and the respective emitters of transistors Q 101  and Q 102 , forming an alternative implementation of differential input circuits  14 ,  15  of FIG.  1 . Resistors R 101  and R 102  provide emitter degeneration of transistors Q 101  and Q 102 , decreasing the gain of the device. 
     FIG. 5 shows the effect upon output current I OUT  as a function of input differential voltage for this configuration. As can be readily seen, the steepness of the function that describes the output current has been reduced as the gain is reduced. 
     Another implementation of the device appears in FIG.  6 . In this implementation, diode-connected transistors Q 113  and Q 114  have been added between independent biasing current source  12  and transistors Q 101  and Q 102  (forming a third variation of differential input circuits  14 ,  15  of FIG.  1 ). Transistors Q 113  and Q 114  act as blocking diodes, increasing the maximum differential voltage which may be applied to the inputs, while keeping the remaining transistors in forward active operation mode. Although shown as transistors with the base and collector shorted, actual diodes may be used in their place. The effect of the blocking diodes is to decrease the gain of the device. 
     Another implementation is shown in FIG. 7, which is similar to FIG. 6 except that two additional Independent Current Sources  150  and  152  are included that provide currents I L1  and I L2  to the emitters of the input transistors Q 101  and Q 102  (forming a fourth variation to the differential input circuits  14 ,  15  of FIG.  1 ). In one implementation, I L1  and I L2  are equal to each other, but they are not necessarily equal to I CC . Independent Current Sources  150  and  152 , along with Independent  1 . Biasing Current Source  12 , serve to place maximum and minimum values on I OUT  by setting maximum base voltages on Q 107  and Q 108 . Independent Current Sources  150  and  152  set a minimum current through Q 104  and Q 112 , and consequently set minimum currents through mirror transistors Q 110  and Q 106 . Currents through Q 106  and Q 110  act to pull down the base voltages of Q 107  and Q 108 , respectively. This pulling down of base voltages prevents the base voltages of Q 107  and Q 108  from going as high, thereby limiting the base-to-emitter voltages of Q 107  and Q 108 , which in turn limits their collector currents, thereby limiting I OUT  Another implementation is shown in FIG. 8, which is similar to FIG. 7 with the addition of emitter-degenerating resistors R 101  and R 102  between independent biasing current source  12  and the emitters of transistors Q 113  and Q 114  (forming a fifth variation to the differential input circuits  14 ,  15  of FIG.  1 ). Resistors Ri 01  and R 102  can be used to again reduce the circuit gain. In one implementation, resistors R 101  and R 102  are sized to be 6.9 kiloohms, current sources  150  and  152  each produce I L1 =I L2 =approximately 6.25 microamps, current source  12  produces I CC  approximately 50 microamps, with the first power supply  10  set to V CC =+15 volts and the second power supply  32  set to V EE =−5 volts. 
     FIG. 9 shows a further implementation. This circuit is similar to that shown in FIG. 7, except that Independent Current Sources  150  and  152  provide currents I L1  and I L2  to the collectors of input transistors Q 101  and Q 102  respectively, rather than to the emitters of the input transistors Q 101 , Q 102  (forming a sixth variation to the differential input circuit  14 ,  15  of FIG.  1 ). I L1  and I L2  may be equal to each other but not equal to I CC . If I L1  and I L2  are equal to each other (their common value being I L ), then the minimum output current would be I CC  plus 2I L , and the maximum current would be 
     
       
           I   MAX =( I   L   +I   CC ) 2   /I   L   +I   L   2 /( I   L   +I   CC )  
       
     
     The gain of this circuit would also be slightly greater than that of the circuit shown in FIG.  7 . 
     In an additional implementation shown in FIG. 10, the circuit is similar to that shown in FIG. 9, except degeneration resistors R 101  and R 102  have been added between independent biasing current source  12  and the emitters of transistors Q 113  and Q 114  (forming a seventh variation to the differential input circuits  14 ,  15  of FIG.  1 ). Resistors R 101  and R 102  can be used to again reduce the circuit gain. 
     While this invention has been described in terms of several preferred implementations, it is contemplated that alterations, modifications and permutations thereof will become apparent to those skilled in the art upon a reading of the specification and study of the drawings. For example, the invention may be implemented with pnp bipolar junction transistors in place of npn bipolar junction transistors (and vice versa), or the invention may be implemented with field effect transistors. The circuit may be implemented with supply voltages of various positive or negative values, or with a supply voltage tied to a circuit ground. Different biasing currents may be selected. Although the implementations described above are mirror-symmetric, mirror-symmetry is not essential to this invention, and many variations on the output curves shown in FIG.  3  and FIG. 5 are possible. Various transistor geometries and doping concentrations may be used. The materials employed to implement the invention may be any suitable semiconducting materials, such as silicon or gallium arsenide. Additional features can be incorporated to meet particular demands, such as frequency response, common mode rejection, and signal swing. Application of the invention is virtually unlimited, as it may be applied to many circuits requiring current sources, and may be especially useful in circuits which cannot efficiently provide large standby current.