Abstract:
A method and apparatus for arbitrating between a plurality of masters for use of a common bus. Arbitration is preferably performed based on an urgency and a predetermined priority of a master requesting use of the common bus, wherein a lower priority master requesting urgent use of the common bus can be granted authority to use the common bus over a master having a higher priority.

Description:
TECHNICAL FIELD  
         [0001]    The present invention relates to a method and apparatus for arbitrating between a plurality of masters for use of a common bus in a communication system. More specifically, the invention relates to a method and apparatus for arbitrating between a plurality of masters for use of a common bus based on an urgency and a predetermined priority of a master requesting use of the common bus, wherein a lower priority master requesting urgent use of the common bus can be granted authority to use the common bus over a master having a higher priority.  
         BACKGROUND  
         [0002]    In general, in a system in which a plurality of master processors are commonly coupled to one serial bus for communicating between the masters, one master processor at a time is granted authority to transmit data over the bus. By way of example, an integrated system on a single chip, such as a microcontroller, typically comprises several types of functional blocks. To minimize the size of the chip, such system architecture generally comprises a common data bus.  
           [0003]    A system, such as a microcontroller, generally has an arbiter for performing an arbitrating operation to control access to the common bus by the integrated functional blocks (or masters). In such systems, to perform arbitration, a bus master that uses a common data bus can be classified with an importance level (or priority level) based on the rate at which the master uses the common bus, wherein a fixed preference arbitrating method is typically used to perform arbitration based on such priorities.  
           [0004]    [0004]FIG. 1 is a diagram of a conventional system for arbitrating between a plurality of masters for access to common bus. The system includes a common bus  10  and first through nth masters ( 20 - 1 ˜ 20 -N) that are connected to the common bus  10 . The masters communicate with each other over the common bus  10 . Each of the masters ( 20 - 1 ˜ 20 -N) individually generate first through nth bus request signals (Request_ 1 ˜Request_N), respectively, and output the bus request signals to an arbiter  30 . The arbiter  30  receives bus request signals (Request_ 1 ˜Request_N) from the masters ( 20 - 1 ˜ 20 -N), and then outputs bus grant signals (Grant_ 1 ˜Grant_N) to the first through nth masters ( 20 - 1 ˜ 20 -N), respectively, according to a designated preferential order (predetermined priority). The master that receives a bus grant signal is authorized to access the common bus  10  and communicates with other masters.  
           [0005]    There are various disadvantages to the system architecture of FIG. 1. For instance, data can be lost and the bus use efficiency can decrease when a master having a lower preferential order has difficulty in receiving timely authority to use the bus. These problems are enhanced as the amount of masters using the bus increases.  
         SUMMARY OF THE INVENTION  
         [0006]    The present invention is directed to a method and apparatus for arbitrating between a plurality of masters for use of a common bus. Arbitration is preferably performed based on an urgency and a predetermined priority of a master requesting use of the common bus. Arbitration is preferably performed through use of an urgent channel that enables the masters to transmit urgency requests to an arbiter. A master having urgency can obtain authorization to use the bus by simultaneously transmitting a bus request signal and an urgent requirement signal to the arbiter. As such, a lower priority master requesting urgent use of the common bus can be granted authority to use the common bus over a master having a higher priority.  
           [0007]    According to one aspect of the invention, a method of arbitrating between a plurality of masters for use of a common bus comprises the steps of receiving a bus request signal and an urgent requirement signal through an urgent channel from a master having an urgency to use the common bus over at least one other master requesting use of the bus and having a higher priority of use of the bus, and authorizing use of the common bus by sending a bus grant signal to the master having the urgency to use the bus.  
           [0008]    The urgent requirement signal can be generated by a master to specify an urgency of that master for using the common bus and there may be several urgent requirement signals generated simultaneously by two or more masters. The urgent requirement signal can specify some extent of the urgency of a master by combining an urgent requirement signal with a bus request signal generated by the master.  
           [0009]    In another aspect of the invention, when two or more masters generate an urgent requirement signal together with a bus request signal at the same time, a bus grant signal is sent to the master having the highest preferential order (priority) among the two or more masters, based on a predetermined preferential order (priority) of the masters for using the bus.  
           [0010]    In yet another aspect, when two or more masters generate only a bus request signal (no urgent requirement signal) at the same time, a bus grant signal will be sent to the master having the highest preferential order according to the predetermined preferential order.  
           [0011]    According to another aspect of the invention, an apparatus comprises a bus and a plurality of masters commonly connected to the bus, wherein each master can generate a bus request signal and an urgent requirement signal to request use of the bus. The apparatus further comprises an arbiter that receives and processes bus request signals and urgent requirement signals that are output from one or more masters requesting use of the bus, and selectively outputs a bus grant signal to one of the masters requesting use of the bus based on one of priority, urgency, and both, to authorize use of the bus.  
           [0012]    In another aspect of the invention, the arbiter comprises a plurality of decoders, wherein each of the decoders receives and processes a bus request signal and an urgent requirement signal output from a corresponding one of the plurality of masters, and outputs a corresponding bus request signal and a preferential group selection signal in response thereto, and a plurality of arbiter logic circuits for receiving an uppermost preferential group selection signal output from the plurality of decoders, and generating and outputting bus grant signals. The arbiter further comprises a selection logic circuit for receiving the preferential group selection signals output from the plurality of decoders, and outputting a bus grant selection signal, and a multiplexer for selectively outputting one of the bus grant signals generated by the arbiter logic circuits in response to the bus grant selection signal output from the selection logic circuit.  
           [0013]    Preferably, when two or more masters send an urgent requirement signal together with a bus request signal to the arbiter at the same time, the arbiter selectively outputs a bus grant signal for the master having the highest preferential order (priority) among the two or more masters, based on a predetermined preferential order (priority) of the masters for using the bus.  
           [0014]    Preferably, when two or more masters send only a bus request signal (no urgent requirement signal) to the arbiter at the same time, the arbiter selectively outputs a bus grant signal for the master having the highest preferential order among the two or more masters according to the predetermined preferential order.  
           [0015]    In another aspect of the invention, the arbiter comprises a plurality of decoders, wherein each of the decoders receives and processes a bus request signal and an urgent requirement signal output from a corresponding one of the plurality of masters, and outputs a corresponding bus request signal and a preferential group selection signal in response thereto and a plurality of arbiter logic circuits for receiving an uppermost preferential group selection signal output from the plurality of decoders, and generating and outputting bus grant signals. The arbiter further comprises a selection logic circuit for receiving bus request signals, and outputting a bus grant selection signal, and a multiplexer for selectively outputting one of the bus grant signals generated by the arbiter logic circuits in response to the bus grant selection signal output from the selection logic circuit. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]    Preferred embodiments of the invention will become apparent from the following description in conjunction with the accompanying drawings, in which:  
         [0017]    [0017]FIG. 1 is a diagram of a conventional system for arbitrating between a plurality of masters for use of a common bus;  
         [0018]    [0018]FIG. 2 is a diagram illustrating a system for arbitrating between a plurality of masters for use of a common bus according to an embodiment of the present invention; and  
         [0019]    [0019]FIG. 3 is a schematic diagram of an arbiter according to an embodiment of the invention.  
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0020]    Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. For purposes of clarity, a detailed description of known functions and systems has been omitted.  
         [0021]    [0021]FIG. 2 is a diagram illustrating a system for arbitrating between a plurality of masters for use of a common bus according to an embodiment of the present invention. The system comprises a common bus  10  and first through nth masters ( 20 - 1 ˜ 20 -N) that are coupled to the common bus  10 . The masters ( 20 - 1 ˜ 20 -N) generate first through nth bus request signals (Request_ 1 ˜Request_N) and first through nth urgent requirement signals (URGENT_ 1 ˜URGENT_N), respectively. An arbiter  30  receives the bus request signals (Request_ 1 ˜Request_N) and the urgent requirement signals (URGENT_ 1 ˜URGENT_N) from the masters ( 20 - 1 ˜ 20 -N), and selectively outputs the bus grant signals (Grant_ 1 ˜Grant_N) to the masters ( 20 - 1 ˜ 20 -N)) based on designated preferential order (priority) and an urgency. The urgent requirement signals (URGENT_ 1 ˜URGENT_N) are preferably transmitted through a separate urgent channel.  
         [0022]    [0022]FIG. 3 is a schematic diagram of an arbiter according to an embodiment of the present invention, which may be implemented in the system of FIG. 2. The arbiter  30  comprises first through nth decoders ( 31 - 1 ˜ 31 - n ) for receiving the first through nth bus request signals (Request_ 1 ˜Request_N) and the first through nth urgent requirement signals (URGENT_ 1 ˜URGENT_N) from the first through nth masters ( 20 - 1 ˜ 20 -N), respectively. Each of decoders ( 31 - 1 ˜ 31 - n ) outputs a corresponding bus request signal and a preferential group selection signal. First through nth arbiter logic circuits ( 32 - 1 ˜ 32 - n ) receive an uppermost preferential group selection signal output from the decoders ( 31 - 1 ˜ 31 - n ), and generate and output bus grant signals (Grant_ 1 ˜Grant_N). A selection logic circuit  33  receives the preferential group selection signals output from the decoders ( 31 - 1 ˜ 31 - n ), and outputs bus grant selection signals to a multiplexer  34 . The multiplexer  34  selectively outputs one of the bus grant signals (Grant_ 1 ˜Grant_N) generated by an arbiter logic circuit ( 32 - 1 ˜ 32 - n ) in response to the bus grant selection signal output from the selection logic circuit  33 .  
         [0023]    A detailed description of a method operation of the systems shown in FIGS. 2 and 3 will now be provided.  
         [0024]    In FIGS. 2 and 3, the first through nth masters ( 20 - 1 ˜ 20 -N) generate the first through nth bus request signals (Request_ 1 ˜Request_N) and the first through nth urgent requirement signals (URGENT_ 1 ˜URGENT_N), respectively, and separately output the signals (Request_ 1 ˜Request_N) and (URGENT_ 1 ˜URGENT_N) to the arbiter  30 . The arbiter  30  processes the first through nth bus request signals (Request_ 1 ˜Request_N) and the first through nth urgent requirement signals (URGENT_ 1 ˜URGENT_N), and then selectively outputs the bus grant signal (Grant_ 1 ˜Grant_N) to one of the first through nth masters ( 20 - 1 ˜ 20 -N) according to a designated priority and an urgency. The master that receives the bus grant signal among the first through nth masters ( 20 - 1 ˜ 20 -N) is authorized to access the common bus  10  to thereby communicate with other masters, for example.  
         [0025]    A method for generating the bus grant signals (Grant_ 1 ˜Grant_N) will now be described in further detail with reference to FIG. 3. As explained above, the bus grant signals (Grant_ 1 ˜Grant_N) are transmitted to the first through nth masters ( 20 - 1 ˜ 20 -N) according to a predetermined priority and urgency, when the arbiter  30  receives the first through nth bus request signals (Request_ 1 ˜Request_N) and the first through nth urgent requirement signals (URGENT_ 1 ˜URGENT_N).  
         [0026]    Preferably, a preferential order is pre-designated to the masters ( 20 - 1 ˜ 20 -N) for authorizing use of the common bus  10 . Each of the first through nth decoders ( 31 - 1 ˜ 31 - n ) combines the bus request signals (Request_ 1 ˜Request_N) and the first through nth urgent requirement signals (URGENT_ 1 ˜URGENT_N) received from the masters ( 20 - 1 ˜ 20 -N), and outputs a corresponding bus request signal and preferential group selection signal. In one embodiment, the preferential group is preferably divided into an uppermost preferential group, a medium preferential group and a lowermost preferential group.  
         [0027]    The first through nth arbiter logic circuits ( 32 - 1 ˜ 32 - n ) receive the uppermost preferential group selection signal outputted from the first through nth decoders ( 31 - 1 ˜ 31 - n ), and generate and output the bus grant signals (Grant_ 1 ˜Grant_N). A selection logic circuit  33  receives the preferential group selection signal output from the first through nth decoders ( 31 - 1 ˜ 31 - n ), and outputs the bus grant selection signal to a multiplexer  34 . The multiplexer  34  selectively outputs the bus grant signals (Grant_ 1  Grant_N) generated by the first through nth arbiter logic circuits ( 32 - 1 ˜ 32 - n ) in response to the bus grant selection signal output from the selection logic circuit  33 .  
         [0028]    For example, assume the first master  20 - 1  is designated as the highest preferential order. Assume further that the first master  20 - 1  generates the first bus request signal Request_ 1  and sends it to the first decoder  31 - 1 . The first decoder  31 - 1  preferably outputs a logic “high” control signal to a line Master 1 , and the second through nth decoders ( 31 - 2 ˜ 31 - n ) output a logic “low” control signal to the remaining lines (Master 2 ˜MasterN). The first arbiter logic circuit  32 - 1  thus outputs the first through nth bus grant signals (Grant_ 1 ˜Grant_N) to the multiplexer  34 . At this time, the selection logic circuit  33  receives a logic “high” control signal output from the first decoder  31 - 1 , and outputs a signal for selecting the first bus grant signal Grant_ 1 . Thus, the multiplexer  34  selects and outputs the first bus grant signal Grant_ 1  output from the first arbiter logic circuit  32 - 1 . The first bus grant signal Grant_ 1  is received by the first master  20 - 1 , which is then authorized to use the common bus  10 .  
         [0029]    Each of the first through nth masters ( 20 - 1 ˜ 20 -N) occupies the common bus according to such designated preferential order. Under an occupancy state based on the preferential order, assuming that the second master  20 - 2  is-designated as the lowermost preferential order among the masters having a lower preferential order, it is difficult for the second master  20 - 2  to obtain access to the common bus  10  because its preferential order is the lowermost order. In accordance with one aspect of the invention, when the second master  20 - 2  needs to use the bus  10 , the second master  20 - 2  can generate the second bus request signal Request 2  and the second urgent requirement signal URGENT 2 , and send such signals to the second decoder  31 - 2 . Then, the second decoder  31 - 2  outputs a logic “high” control signal to the line Master 2 , and the first decoder  31 - 1  and the third through nth decoders ( 31 - 3 ˜ 31 - n ) output a logic “low” control signal to the remaining lines (Master 1 , Master 3 ˜MasterN). The first arbiter logic circuit  32 - 1  therefore outputs the first through nth bus grant signals (Grant_ 1 ˜Grant_N). At this time, the selection logic circuit  33  receives the high signal outputted from the second decoder  31 - 2 , and outputs a signal for selecting the second bus grant signal Grant 2 . Thus, the multiplexer  34  selectively outputs the second bus grant signal Grant 2  output from the first arbiter logic circuit  32 - 1 , and sends it to the second master  20 - 2 . In doing so, the second master  20 - 2  is granted access to the common bus  10  and communicates thereby.  
         [0030]    In another aspect of the invention, when bus request signals are generated at the same time from two or more masters among the first through nth masters ( 20 - 1 ˜ 20 -N), a bus grant signal Grant is outputted to its corresponding master according to a pre-designated preferential order. In another aspect of the invention, when one of the masters generates a bus request signal Request and an urgent requirement signal URGENT simultaneously, the arbiter will output a bus grant signal Grant to the master to authorize access to the common bus  10 . In another aspect of the invention, when a bus request signal Request and an urgent requirement signal URGENT are simultaneously sent from two or more masters, a bus grant signal Grant is sent to the master having the uppermost preferential order by the predetermined preferential order to grant access to the common bus  10 .  
         [0031]    Preferably, the highest preferential order in the respective masters should not exceed some predetermined constant rate so as to evenly grant use of the bus to all masters. The preferential order is effectively designated on the basis of a characteristic of the masters by increasing a rank of a master having a high bus use rate and by lowering the rank of a master having a low bus use rate.  
         [0032]    According to one embodiment of the present invention, the selection logic circuit  33  is configured to receive outputs of the first through nth decoders ( 31 - 1 ˜ 31 - n ) and selectively output one of the bus grant signals (Grant_ 1 ˜Grant_N). In another embodiment, the selection logic circuit  33  can be configured to receive the bus request signal (Request_ 1 ˜Request_N) and then selectively output the bus grant signal (Grant_ 1 ˜Grant_N) without deviating from a scope of the present invention.  
         [0033]    The urgent requirement signal URGENT indicates an urgency concerning the bus use, and can be provided with several signals instead of one urgent requirement signal. The urgency may be also represented by combining the urgent requirement signal URGENT and the bus request signal Request.  
         [0034]    As mentioned above, in accordance with the present invention, among numerous masters whose preferential order is predetermined, when a master having a low preferential order requires an urgent preferential order, the master can send a bus request signal and an urgent requirement signal together to use a common bus. Thus, the invention provides an advantage of preventing data from being lost and enables efficient use of the common bus.  
         [0035]    It will be apparent to those skilled in the art that various modifications and variations can be made in preferred embodiments of the present invention without deviating from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of the embodiments, as defined by the appended claims.