Abstract:
In a liquid crystal display apparatus including a plurality of gate lines, a plurality of drain lines, and a plurality of pixels each including a liquid crystal cell having a pixel electrode connected to a storage capacitor and a switching element connected between the liquid crystal cell and one of the drain lines, a gate of the switching element is connected to one of the gate lines, and a capacitance of the storage capacitor is changed in accordance with a distance between said pixel and an input end of a corresponding one of the gate lines.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an active matrix liquid crystal display (LCD) apparatus. 
     2. Description of the Related Art 
     Active matrix LCD apparatuses formed by liquid crystal cells and thin film transistors (TETs) have adopted polarity reversion driving systems to improve the picture quality such as the contrast and response speed for moving pictures. As a result, such LCD apparatuses have been broadly used in portable personal computers, desktop personal computers and the like. 
     For example, a pixel of a gate storage type LCD apparatus is formed by a liquid crystal cell connected to a common counter electrode, a TFT connected between a drain line and the liquid crystal cell, and a storage capacitor between the liquid crystal cell and a gate line adjacent to a gate line of this pixel. In this case, usually, since the capacitance of the storage capacitor is definite, a feed-through voltage fluctuates in the apparatus. Particularly, as LCD aparatuses have been increased in size and numerical aperture, and fine-structured, so that the width of the gate lines is reduced to increase the resistance thereof, the feed-through voltage greatly fluctuates. This will be explained later in detail. 
     In order to reduce the fluctuation of the feed-through voltage array, the resistances of the gate lines can be reduced. For example, the thickness of the gate lines can be reduced, and also, the gate lines can be made of material such as aluminum or gold having a low resistance. However, if the thickness of the gate lines is increased or the gate lines are made of the above-mentioned material, the manufacturing steps have to be changed. 
     Also, in a prior art LCD apparatus, the sizes of TFTs are gradually increased, thus compensating for the in-plane-fluctuation of the feed-through voltage (see JP-A-3-306221). This will also be explained later in detail. In this prior art LCD apparatus, however, the leakage current of the TFTs is increased. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide an LCD apparatus capable of suppressing the fluctuation of feed-through voltage without modification of the manufacturing steps and without increasing the leakage current of the TFTs. 
     According to the present invention, in a liquid crystal display apparatus including a plurality of gate lines, a plurality of drain lines, and a plurality of pixels each including a liquid crystal cell having a pixel electrode connected to a storage capacitor and a switching element connected between the liquid crystal cell and one of the drain lines, a gate of the switching element is connected to one of the gate lines, and a capacitance of the storage capacitor is changed in accordance with a distance between the pixel and an input end of a corresponding one of the gate lines. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more clearly understood from the description as set forth below, compared with prior art, with reference to the accompanying drawings, wherein: 
     FIG. 1 is a diagram illustrating a general LCD apparatus; 
     FIG. 2 is a circuit diagram of the apparatus of FIG. 1; 
     FIG. 3 is a plan view illustrating a prior art LCD apparatus; 
     FIG. 4 is a plan view illustrating a first embodiment of the LCD apparatus according to the present invention; 
     FIGS. 5A, 5B and 5C are cross-sectional views taken along the lines I-I&#39;, II-II&#39; and III-III&#39;, respectively, of the apparatus of FIG. 4; 
     FIG. 6 is an equivalent circuit diagram of the apparatus of FIG. 4; 
     FIGS. 7A, 7B, 8A and 8B are timing diagrams for showing the operation of the apparatus of FIG. 4; 
     FIG. 9 is a graph showing the effect of the first embodiment and the prior art; 
     FIG. 10 is a plan view illustrating a second embodiment of the LCD apparatus according to the present invention; 
     FIGS. 11A, 11B and 11C are cross-sectional views taken along the lines I-I&#39;, II-II&#39; and III-III&#39;, respectively, of the apparatus of FIG. 10; 
     FIG. 12 is an equivalent circuit diagram of the apparatus of FIG. 10; 
     FIG. 13 is a plan view illustrating a modification of the apparatus of FIG. 10; and 
     FIGS. 14A, 14B and 14C are cross-sectional views taken along the lines I-I&#39;, II-II&#39; and III-III&#39;, respectively, of the apparatus of FIG. 13. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Before the description of the preferred embodiments, a prior art LCD apparatus will be explained with reference to FIGS. 1, 2 and 3. 
     In FIG. 1, which illustrates a general LCD apparatus, reference PA designates a pixel array, DR1 designates a gate line driving circuit, and DR2 designates a drain line driving circuit. 
     As illustrated in FIG. 2, which is a gate storage type LCD apparatus, the pixel array PA includes a plurality of pixels P 00 , P 01 , . . . connected gate lines GL 0 , GL 1 , . . . driven by the gate line driving circuit DR1 and drain lines DL 0 , DL 1 , . . . driven by the drain line driving circuit DR2. In more detail, each of the pixels, such as P 10 , is formed by a liquid crystal cell CL connected to a common counter electrode CE, a TFT Q connected between the drain line DL 0  and the liquid crystal cell CL, and a storage capacitor SC between the liquid crystal cell LC and the gate line GL 0  adjacent to the gate line GL 1 . 
     At each of the pixels, a feed-through voltage V FD  is represented by 
     
         V.sub.FD =[C.sub.GS /(C.sub.LC +C.sub.SC +C.sub.GS)]·ΔV.sub.G                       (1) 
    
     where C GS  is a capacitance between the gate and source of the TFT Q; 
     C LC  is a capacitance of the liquid crystal cell LC; 
     C SC  is a capacitance of the storage capacitor SC; and 
     ΔV G  is an amplitude of a pulse voltage applied to the gate line such as GL 1 . 
     On the other hand, when a falling edge of the pulse voltage at the gate line such as GL 1  is rounded by the resistance of the gate line, a current I DS  flows from the drain line DL 0  to the source electrode of the TFT Q while the TFT Q is turned ON. Therefore, the feed-through voltage V FD  is actually represented by 
     
         V.sub.FD =(C.sub.GS ·ΔV.sub.G -∫I.sub.DS dt)/(C.sub.LC +C.sub.SC +C.sub.GS)                                      (2) 
    
     The value ∫I DS  dt is dependent upon the rounded amount of the falling edge of the pulse voltage. Therefore, at the pixels such as &#34;A&#34; and &#34;a&#34; as illustrated in FIG. 1 near to the gate line driving circuit DR1, the value of ∫I DS  dt≈0. Also, at the pixels such as &#34;C&#34; and &#34;c&#34; as illustrated in FIG. 1 far from the gate line driving circuit DR1, the value of ∫I DS  dt is very large. Further, at the pixels such as &#34;B&#34; and &#34;b&#34; as illustrated in FIG. 1, the value of ∫I DS  dt is medium. Therefore, there is generated the following in-plane fluctuation in the pixel array PA1: 
     
         ΔV.sub.FD =(∫I.sub.DS dt)max/(C.sub.LC +C.sub.SC +C.sub.GS)(3) 
    
     In order to reduce the fluctuation ΔV FD  in the pixel array PA, in a first prior art LCD apparatus, the resistances of the gate lines GL 0 , GL 1 , . . . can be reduced. For example, the width and/or thickness of the gate lines GL 0 , GL 1 , . . . can be reduced, and also, the gate lines GL 0 , GL 1 , . . . can be made of material such as aluminum or gold having a low resistance. However, if the thickness of the gate lines GL 0 , GL 1 , . . . is increased or the gate lines GL 0 , GL 1 , . . . are made of the above-mentioned material, the manufacturing steps have to be changed. Also, if the width of the gate lines. GL 0 , GL 1 , . . . is increased, the numerical aperture is reduced. 
     In FIG. 3, which illustrates a second prior art LCD apparatus, the sizes of TFTs Q A , Q B  and Q C  are gradually increased, thus compensating for the in-plane-fluctuation ΔV FD  (see JP-A-3-306221). Note that pixels A, B and C of FIG. 3 correspond to the pixels A, B and C, respectively of FIG. 1. 
     In the LCD apparatus of FIG. 3, however, the leakage current of the TFTs is increased. 
     FIG. 4 is a plan view illustrating a first embodiment of the present invention, and FIGS. 5A, 5B and 5C are cross-sectional views taken along the lines I-I&#39;, II-II&#39; and III-III&#39;, respectively, of FIG. 4. Note that the LCD apparatus of the first embodiment is of a gate storage type, and also, pixels A, B and C of FIG. 4 correspond to the pixels A, B and C, respectively, of FIG. 1. 
     In FIGS. 4, 5A, 5B and 5C, a conductive layer 2 made of Cr or the like is deposited on a glass substrate 1, and patterned to form gate lines GL 0 , GL 1 , . . . , which also serve as gate electrodes of TFTs Q A , Q B  and Q C . Also, a gate insulating layer 3 made of silicon nitride is deposited on the entire surface. Further, a semiconductor active layer 4 made of amorphous silicon is formed and patterned. In addition, a conductive layer 5 made of Cr or the like is deposited and patterned to form drain lines DL A , DL B  and DL C  as well as source electrodes (not shown) of the TFTs Q A , Q B  and Q C . Then, an indium tin oxide (ITO) layer 6 is deposited by a sputtering process, and is patterned to form transparent pixel electrodes E A , E B  and E C  which are connected to the source electrodes of the TFTs Q A , Q B  and Q C , respectively. Further, a passivation layer 7 is formed on the entire surface. 
     On the other hand, a common counter electrode CE is formed on a counter glass substrate 8. Finally, liquid crystal as indicated by reference numeral 9 is inserted into a gap between the passivation layer 7 and the common counter electrode CE. 
     In FIGS. 4, 5A, 5B and 5C, the adjacent gate line GL 0  is overlapped via the gate insulating layer 3 to the transparent pixel electrodes E A , E B  and E C  to form storage capacitors SC A , SC B  and SC C , respectively, to form a gate storage type apparatus. 
     As indicated by shaded portions in FIGS. 5A, 5B and 5C, the overlapped areas between the adjacent gate line GL 0  and the transparent pixel electrodes E A , E B  and E C  are gradually reduced as the distance from the gate line driving circuit DR1 is increased. Therefore, 
     
         C.sub.SCA)C.sub.SCB)C.sub.SCC                              (4) 
    
     where C SCA , C SCB  and C SCC  are capacitances of the storage capacitors SC A , SC B  and SC C , respectively. 
     In FIG. 6, which is an equivalent circuit diagram of the apparatus of FIGS. 4, 5A, 5B and 5C, the feed-through voltage V FD  (A) at the pixel A is 
     
         V.sub.FD (A)=(C.sub.GS ·ΔV.sub.G -∫I.sub.DS (A)dt)/(C.sub.LC +C.sub.SCA +C.sub.GS)                    (5) 
    
     Also, the feed-through voltage V FD  (B) at the pixel B is 
     
         V.sub.FD (B)=(C.sub.GS ·ΔV.sub.G -∫I.sub.DS (B)dt)/(C.sub.LC +C.sub.SCB +C.sub.GS)                    (6) 
    
     Further, the feed-through voltage V FD  (C) at the pixel C is 
     
         V.sub.FD (C)=(C.sub.GS ·ΔV.sub.G -∫I.sub.DS (C)dt)/(C.sub.LC +C.sub.SCC +C.sub.GS)                    (7) 
    
     In this case, generally, 
     
         ∫I.sub.DS (A)dt&lt;∫I.sub.DS (B)dt&lt;∫I.sub.DS (C)dt (8) 
    
     Therefore, if CSCA=SSCB=SSCC (in the prior art), from the formulae (5), (6) and (7), 
     
         V.sub.FD (A)&gt;V.sub.FD (B)&gt;V.sub.FD (C)                     (9) 
    
     However, according to the first embodiment, since the capacitances C SCA , C SCB  and C SCC  are adjusted under the condition (4), 
     
         V.sub.FD (A)≈V.sub.FD (B)≈V.sub.FD (C)     (10) 
    
     can be satisfied. 
     That is, at the pixel A, the voltage at the gate line GL 1  is changed rapidly as shown in FIG. 7A. In FIG. 7A, DL A  designates the voltage at the drain line DL A . As shown in FIG. 7B, when the voltage at the gate line GL 1  rapidly falls, the voltage at the source electrode S A  of the TFT Q A  also rapidly falls due to the capacitive coupling by ΔV A . In this case, since the leakage amount ∫I DS  (A)dt is small, the voltage at the source electrode S A  remains at almost the same level. Also, the center value S A0  of the voltage at the source electrode S A  depends upon ΔV A . Therefore, the feed-through voltage V FD  (A) is represented by 
     
         V.sub.FD (A)=DL.sub.A0 -S.sub.A0 
    
     where DL A0  is the center value of the voltage at the drain line DL A  and is constant. 
     On the other hand, at the pixel C, the voltage at the gate line GL 1  is changed slowly as shown in FIG. 8A. In FIG. 8A, DL C  designates the voltage at the drain line DL C . As shown in FIG. 8B, when the voltage at the gate line GL 1  slowly falls, the voltage at the source electrode S C  of the TFT Q C  also slowly falls due to the capacitive coupling by ΔV C1 . Note that the value ΔV C1  is larger than ΔV A , since C SCC  is smaller than C SCA . In this case, since the leakage amount ∫I DS  (C)dt is large, the voltage at the source electrode S C  almost rises a little indicated by ΔV C2  in FIG. 8B. In this case, the center value S C0  of the voltage at the source electrode S C  depends upon ΔV C1  -ΔV C2 . Therefore, if ΔV A  =ΔV C1  -ΔV C2 , the feed-through voltage V FD  (C) is represented by 
     
         ΔV.sub.FD (C)=DL.sub.C0 -V.sub.FD (A) 
    
     where DL C0  is the center value of the voltage at the drain line DL C  and is constant (DL A0  =DL C0 ). 
     Thus, in the first embodiment, as shown in FIG. 9, the feed-through voltage V FD  can be almost uniform within the pixel array. 
     FIG. 10 is a plan view illustrating a second embodiment of the present invention, FIGS. 11A, 11B and 11C are cross-sectional views taken along the lines I-I&#39;, II-II&#39; and III-III&#39;, respectively, of FIG. 10, and FIG. 12 is an equivalent circuit diagram of the apparatus of FIG. 10. Note that the LCD apparatus of the second embodiment is of a storage capacitor line type, and also, pixels A, B and C of FIG. 10 correspond to the pixels A, B and C, respectively, of FIG. 1. 
     In the second embodiment, storage capacitor lines L 0 , L 1 , are provided for the gate lines GL 0 , GL 1 , . . . . The storage capacitor lines L 0 , L 1 , are made of an ITO layer 10 on the glass substrate 1 as illustrated in FIGS. 11A, 11B and 11C. 
     In FIGS. 10, 11A, 11B, 11C and 12, the storage capacitor line L 1  is overlapped via the gate insulating layer 3 to the transparent pixel electrodes E A , E B  and E C  to form storage capacitors SC A , SC B  and SC C , respectively. 
     As indicated by shaded portions in FIGS. 11A, 11B and 11C, the overlapped areas between the storage capacitor line L 1  and the transparent pixel electrodes E A , E B  and E C  are gradually reduced as the distance from the gate line driving circuit DR1. Therefore, in the same way as the formula (4), 
     
         C.sub.SCA)C.sub.SCB)C.sub.SCC 
    
     where C SCA , C SCB  and C SCC  are capacitances of the storage capacitors SC A , SC B  and SC C , respectively. Thus, the effect of the second embodiment is the same as that of the first embodiment. 
     FIG. 13 is a modification of the apparatus of FIG. 10, and FIGS. 14A, 14B and 14C are cross-sectional views taken along the lines I-I&#39;, II-II&#39; and III-III&#39;, respectively, of FIG. 13. That is, an optical shield layer 11 is mounted on the glass substrate 8, and the overlapped portions between the storage capacitor line L 1  and the transparent pixel electrodes E A , E B  and E C  are changed under the optical shield layer 11. Thus, the fluctuation of the numerical aperture can be improved. 
     As explained hereinabove, according to the present invention, since the feed-through voltage can be uniform within the pixel array, the picture quality can be improved.