Abstract:
A state saving circuit and method for using the same. The circuit comprises a first latch powered by an uninterrupted power supply, wherein the first latch includes a first pair of cross coupled inverters for storing data, and includes an input cut-off control for isolating the data in the first pair of cross coupled inverters; a second latch coupled to an output of the first latch and powered by an interruptible power supply, wherein the second latch includes a second pair of cross coupled inverters and a clock input for latching the data from the first latch to the second latch; and wherein an interruption of power to the second latch results in a state being saved in the first latch.

Description:
BACKGROUND OF THE INVENTION 
     1. Technical Field 
     The present invention relates generally to integrated circuits, and more particularly to an integrated circuit having a state saving latch. 
     2. Related Art 
     With the increasing popularity of portable electronic devices, such as laptops, cell phones and personal digital assistants (PDA&#39;s), there is a growing need for systems that can reduce power consumption in order to extend energy storage times of the device&#39;s power supply (e.g., battery). Namely, applications that utilize CMOS integrated circuits (IC&#39;s) require circuits that utilize a minimal amount of power and have the capability to be powered down when not in use. 
     Many electronic devices, including systems having custom and application specific IC&#39;s (ASIC) feature some form of standby, sleep, or low power mode—referred to collectively herein as sleep mode. These modes exhibit greatly reduced power dissipation by essentially disconnecting some of the logic in the device from the power supply when the logic is not required. Powering down portions of an IC cannot only be used to save power and extend battery life, but can be used in certain schemes to manage chip power in systems operating from a standard power supply. 
     Recovery from sleep mode generally requires returning the IC to the state it was in just prior to entering sleep mode. However, without power, storage elements in an IC will lose their stored bits of information. Accordingly, for commonly used elements, such as data latches, the stored value in the latch must be maintained when the IC is switched to sleep mode and be restored after power-up. Accordingly, a need exists for circuitry that can save the state of a latch before power-down, and restore the state of the latch after power-up. 
     SUMMARY OF THE INVENTION 
     The present invention addresses the above-mentioned problems, as well as others, by providing a circuit having a state saving mode of operation. In a first aspect, the invention provides a state saving circuit, comprising: a first latch powered by an uninterrupted power supply, wherein the first latch includes a first pair of cross coupled inverters for storing data, and includes an input cut-off control for isolating the data in the first pair of cross coupled inverters; a second latch coupled to an output of the first latch and powered by an interruptible power supply, wherein the second latch includes a second pair of cross coupled inverters and a clock input for latching the data from the first latch to the second latch; and wherein an interruption of power to the second latch results in a state being maintained in the first latch. 
     In a second aspect, the invention provides a method of saving a state in a circuit, comprising: providing a first latch powered by an uninterrupted power supply, wherein the first latch includes a first pair of cross coupled inverters for storing data, and includes an input cut-off control for cutting off input into the first latch; providing a second latch coupled to an output of the first latch and powered by an interruptible power supply, wherein the second latch includes a clock input for latching the data from the first latch to the second latch; inputting and storing data in the first latch; activating the input cut-off control to cut off further input into the first latch; and interrupting the power supply to the second latch. 
     In a third aspect, the invention provides a system having a power down mode for managing power consumption, the system having a state saving circuit, comprising: a first latch powered by an uninterruptible power supply, wherein the first latch includes a data input for receiving data and a storage circuit for storing received data; a second latch coupled to an output of the first latch and powered by an interruptible power supply, wherein the second latch includes a clock input for latching the data from the first latch to the second latch; and an input cut-off control for isolating data in the first latch by preventing further data from being inputted to the first latch, wherein the input cut-off control is activated when power to the interruptible power supply is cut off. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     An exemplary embodiment of the present invention will hereinafter be described in conjunction with the appended drawing, where like designations denote like elements, and wherein: 
     The FIGURE depicts an exemplary circuit in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to the FIGURE, an exemplary state saving circuit  10  is shown. The state saving circuit  10  can be utilized in any device or system  11  that incorporates power consumption management, e.g., sleep mode, and requires data to be saved during power down periods. Such devices may include, e.g., a handheld device, a cellular phone, a laptop, an integrated circuit, etc., and may utilize one or more state saving circuits  10 . 
     The circuit  10  is composed of three stages, an input stage (or circuit)  12 , an L 1  latch stage  14 , and an output or L 2  latch stage  16 . Circuit  10  utilizes an interruptible power supply VDD  22  to power the input and output stages  12 , 16 , and an uninterruptible power supply VDDG  18  to power the L 1  latch stage  14 . Interruptible power supply VDD  22  may comprise any power source that can be toggled off and on for the purposes of power management, e.g., to place the overall system  11  in a sleep mode. Uninterruptible power supply VDDG  18  may comprise any power source that remains on during periods of power management, e.g., during sleep mode. As will be described, circuit  10  allows data to be saved while power to the input stage  12 , the L 2  latch stage  16 , and other system components, is interrupted or powered down into a sleep mode. Specifically, data is maintained in the L 1  latch stage  14 , which saves the state of the data passing through circuit  10  when VDD  22  is turned off. 
     The input stage  12  is shown comprising a multiplexor scan circuit (Mux Scan) capable of receiving two different types of input and a clock signal C. It should be recognized, however, that any type of “input circuit,” including a simple input line, could be utilized to exploit the state saving feature of the invention. In this exemplary embodiment, the input stage  12  is powered from VDD  22  and has two data input pins, a scan input (I) for receiving scanned in test data from a scan chain, and a data input (D) for receiving data input. A select input (S) is used to select between the data input and the scan input. A zero applied to the S input will allow data from the D input to propagate to node DX and a one at the S input will allow scan data from the I input to propagate to node DX. 
     The C clock input to the input stage  12  is used to clock the propagating data to the L 1  stage  14  via DC and DCN. When the S input is a one, the transmission gate formed by transistors T 1  and T 2  will pass the data from input I to node DX. When the S input is a zero, the transmission gate formed by transistors T 3  and T 4 , will pass the data from the D input to node DX. When DX is a one and the C clock goes high, the input stage  12  output “DC” will go high and remain high as long as the C clock and node DX remain high. Under all other conditions, DC will be held low. When node DX is a zero and the C clock goes high, input stage  12  output “DCN” goes high and will remain high as long as the C clock is high and node DX is held low. Under all other conditions DCN will be held low. 
     The L 1  latch stage  14  receives data via DC and DCN from the input stage  12  and outputs data to the L 2  latch stage  16  via L 1  and L 1 N. The L 1  latch stage  14  stores data using a pair of cross coupled inverters, the first formed by transistors T 12  and T 13 , and the second formed by transistors T 14  and T 15 . VDDG  18 , which powers this stage, is an uninterruptible global power supply that always remains on or high. Accordingly, when circuit  10  goes into a sleep mode, the L 1  latch stage  14  remains powered. An input cutoff control, made up of input FENCEN  20  and transistors T 8  and T 10 , can be used to turn off the input DCN and DC to the L 1  latch stage  14 . Input FENCEN  20  is also powered by VDDG  18  and remains deactivated, i.e., high, under normal operations so that data can freely flow into the L 1  latch stage  14  via input transistors T 9  and T 11 . With FENCEN  20  high, a one at DC and a zero at DCN will force node L 1  high and node L 1 N low. When the input DC goes low and DCN remains low, the state of L 1  and L 1 N will be held or stored on the via the cross coupled inverters until node DCN goes high and node DC stays low. When DCN goes high and DC remains low, the states of L 1  and L 1 N will switch forcing L 1 N high and L 1  low. 
     The L 2  latch stage  16  is similar to the construction of the L 1  latch stage  14 . However, the L 2  stage is powered from interruptible power supply VDD  22  and uses a B clock to pass data from its input nodes L 1 , L 1 N to its output nodes L 2 , L 2 N, respectively. When the B clock is high, L 1  is high and L 1 N is low, then output L 2  is forced to a one and L 2 N is forced to a zero. L 2  will stay high as long as B is high, L 1  is high and L 1 N is low. When the B clock goes low, the states for L 2  and L 2 N are held or latched in the cross coupled inverters formed by T 20 , T 21 , T 22  and T 23 . Changes in L 1  and L 1 N will not affect the state of L 2  and L 2 N when B is low because transistors T 16  and T  18  are off and cross coupled inverters will hold the states of L 2  and L 2 N. L 2  will only go low again when the B clock is high, L 1  is a zero and L 1 N is a one. The above describes the basic operation of a scannable L 1 , L 2  data latch running in a normal power mode. 
     Next, the circuit  10  is described operating in its state saving mode when interruptible power supply VDD  22  is interrupted or turned off. Before power supply VDD  22  is powered down, C clock is held low to latch the state of the L 1  latch  14 . Next, the input cut-off control is activated, i.e., FENCEN  20  is switched low, cutting off transistors T 8  and T 10 . This isolates the cross coupled inverters T 12 , T 13 , T 14  and T 15  from all other devices in the circuit and stores the current state in L 1  latch stage  14 . VDD  22  can then be powered down to zero volts and the states of L 1  and L 1 N will be held because transistors T 12 -T 15  are powered from VDDG  18 , which stays high when VDD  22  is powered down. 
     When the circuit  14  comes out of its power saving state, VDD  22  is powered back up to its operating voltage. At this point with FENCEN  20  still low, the state of L 1  can be transferred to L 2  by pulsing the B clock high and restoring the state of the L 2  latch to the original state before VDD  22  was powered down. FENCEN  20  is then switched high (i.e., input cut-off control is deactivated) and the L 1  latch stage can resume its normal mode of operation. 
     Another option for powering the circuit  10  back up is to hold the C clock low after VDD  22  is powered up, then bring FENCEN  20  high. The L 1  state can then be transferred to the L 2  by bringing the B clock high, or the L 1  state can be updated by switching the C clock high. At this point, the latch can also resume its normal mode of operation. 
     The foregoing description of the embodiments of this invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of this invention as defined by the accompanying claims.