Abstract:
A switch device executes a multi-state function to a computer. The computer has a system on chip. The switch device comprises a switch, a power output circuit, a control circuit, a timer circuit and an interface circuit of the system on chip. A user can press the switch, the control circuit controls the power output circuit to output a control signal to the system on chip for controlling the computer turning on or going into suspend state. When the user continues to press the switch, the timing circuit will execute a timer function to the switch device.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    Embodiments of the present disclosure relate to switches, and more particularly to a switch device for computers. 
         [0003]    2. Description of Related Art 
         [0004]    Microcontrollers in computers are often programmed to output corresponding control signals by which the computers are able to be turned off or enter a suspend mode to conserve power. However, costs of such microcontrollers are high. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]      FIG. 1  is a block diagram of one embodiment of a switch device in connection with a computer. 
           [0006]      FIG. 2  is an electronic circuit diagram of one embodiment of the switch device of  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0007]    The disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one. 
         [0008]      FIG. 1  is a block diagram of one embodiment of a switch device  100  in connection with a computer  200 . The switch device  100  includes a switch  11 , a control circuit  12 , a timer circuit  13 , a power output circuit  14  and an interface circuit of system on chip (SoC)  15 . The control circuit  12  electrically connects to the switch  11 , the timer circuit  13 , the power output circuit  14  and the interface circuit of system on chip  15 . 
         [0009]    The computer  200  includes a SoC  20 . The SoC  20  integrates all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analog, and mixed-signal functions. The SoC  20  is on a single chip substrate. In one embodiment, The SoC  20  includes a power control end  21 , an awakening signal end  22  and a shutdown signal end  23 . 
         [0010]    The control circuit  12  is operable to control the power output circuit  14  outputting a power control signal to the SoC  20  of the computer  200  to control a power status of the computer  200 . For example, the control circuit  12  can control the power output circuit  14  outputting a shutdown signal to the SoC  20  to turn off the computer  200 . In one embodiment, the control circuit  12  comprises a npn type 1, 3 transfer resistor Q 1 , a npn type 2, 3 transfer resistor Q 2  and a npn type 3, 3 transfer resistor Q 3 . Each npn type transfer transistor has terminals labeled base, collector, and emitter. The base of the npn type 1, 3 transfer resistor Q 1  connects to a moving contact point S 2  of the switch  11 . One end of a resistor R 2  connects to the base of the npn type 1, 3 transfer resistor Q 1 . The other end of the resistor R 2  connects to a first point J 1 . The emitter of the npn type 1, 3 transfer resistor Q 1  connects to the first point J 1 . The collector of the npn type 1, 3 transfer resistor Q 1  connects to the collector of the npn type 2, 3 transfer resistor Q 2  through a resistor R 3 . The collector of the npn type 1, 3 transfer resistor Q 1  further connects to the ground through series resistors R 4  and R 5 . 
         [0011]    The base of the npn type 2, 3 transfer resistor Q 2  connects to a second point J 2  through a resistor R 6 . The emitter of the npn type 2, 3 transfer resistor Q 2  connects to the ground. The collector of the npn type 2, 3 transfer resistor Q 2  further connects to the ground through a capacitor C 1 . The capacitor C 1  is operable to filter an alternating current outputted from the collector of the npn type 1, 3 transfer resistor Q 1 . The emitter of the npn type 3, 3 transfer resistor Q 3  connects to the ground. The collector of the npn type 3, 3 transfer resistor Q 3  connects to the power output circuit  14 . The base of the npn type 3, 3 transfer resistor Q 3  connects to the collector of the npn type 2, 3 transfer resistor Q 2 . The base of the npn type 3, 3 transfer resistor Q 3  is operable to amplify a voltage outputted from the npn type 1, 3 transfer resistor Q 1  to the power output circuit  14 . 
         [0012]    The timer circuit  13  is operable to execute a timer function to the switch device  100 . In one embodiment, the timer circuit  13  includes a resistor R 7 , a set of parallel capacitors C 2 , C 3 . One end of the resistor R 7  connects to the first point J 1  and the second point J 2 . One end of the set of the parallel capacitors C 2 , C 3  connects to the second point J 2  and the other end of the set of parallel capacitors C 2 , C 3  connects to the ground. 
         [0013]    The power output circuit  14  is operable to output the power control signal to the power control end  21  of the computer  200 . The power output circuit  14  includes a npn type 4, 3 transfer resistor Q 4 . The base of the npn type 4, 3 transfer resistor Q 4  connects to the collector of the npn type 3, 3 transfer resistor Q 3  through a resistor R 8 . The base of the npn type 4, 3 transfer resistor Q 4  further connects to the base of the npn type 1, 3 transfer resistor Q 1  through a resistor R 9  and a capacitor C 4  being in series connection. The emitter of the npn type 4, 3 transfer resistor Q 4  connects to a first power VDD and connects to a resistor R 9  and the capacitor C 4  being in series connection. The collector of the npn type 4, 3 transfer resistor Q 4  connects to the power control end  21 . The power control end  21  is operable to provide an electronic power to the computer  200 . In addition, the collector of the npn type 4, 3 transfer resistor Q 4  connects to the series resistors R 4 , R 5  and feedbacks the power control signal to the control circuit  12 . 
         [0014]    The interface circuit of system on chip  15  includes a npn type 5, 3 transfer resistor Q 5 . The base of npn type 5, 3 transfer resistor Q 5  connects to the ground through the base of a resistor R 10  and connects to the first point J 1  through a resistor R 11 . The collector of the npn type 5, 3 transfer resistor Q 5  connects to a second power VCC through a resistor R 12 . In addition, the npn type 5, 3 transfer resistor Q 5  further connects to an awakening signal end  22  through a resistor R 13 . The awakening signal end  22  is operable to output an awakening signal to the SoC  20  to awaken the computer  200  in the suspend mode. 
         [0015]    The shutdown signal end  23  connects to the ground through a set of series resistors R 14  and R 15 . The second point J 2  connects to the resistors R 14  and R 15  and is positioned between the resistors R 14  and R 15 . The shutdown signal end  23  can send a shutdown signal to the control circuit  12  through the resistor R 14 . 
         [0016]    The switch  11  is operable to interrupt the flow of electrons in a circuit that are either completely on (“closed”) or completely off (“open”). In one embodiment, the switch  11  comprises a fixed contact point S 1  and a moving contact point S 2 . Wherein, the fixed contact point S 1  connects to the first power VDD through a resistor R 1 . The moving contact point S 2  connects to the control circuit  12 . In other embodiments, users can connect the switch  11  in a short time to force the computer  200  to run the suspend mode or a booting mode. Furthermore, users can connect the switch  11  in a long time connection to force the computer  200  to run a shutdown mode. 
         [0017]    As shown in  FIG. 2 , an electronic circuit diagram of the switch device  100  is shown. The npn type 1, 3 transfer resistor Q 1  of the control circuit  12  is connected if the switch  11  is connected. Then the collector of npn type 1, 3 transfer resistor Q 1  outputs a high level voltage. The moving contact point S 2  of the switch  11  connects to the first point J 1  through the resistor R 2  and the voltage of the first point J 1  is the high level voltage. The parallel capacitors C 2 , C 3  start to be charged because of the high level voltage of the first point J 1 . Because the switch  11  is not connected continuously, the parallel capacitors C 2 , C 3  are not charged continuously. Therefore, the voltage of the base of npn type 2, 3 transfer resistor Q 2  is small than a start voltage of the npn type 2, 3 transfer resistor Q 2 . Accordingly, the npn type 2, 3 transfer resistor Q 2  is not active. 
         [0018]    In addition, the collector of the npn type 1, 3 transfer resistor Q 1  connects to the base of the npn type 3, 3 transfer resistor Q 3  through the resistor R 3 . Then the npn type 3, 3 transfer resistor Q 3  is in an electric conduction. The npn type 3, 3 transfer resistor Q 3  amplifies the voltage of the collector of the npn type 1, 3 transfer resistor Q 1  to the npn type 4, 3 transfer resistor Q 4 . Then the npn type 4, 3 transfer resistor Q 4  is in the electric conduction. Accordingly, the collector of the npn type 4, 3 transfer resistor Q 4  outputs a high level voltage (power control signal) to the power control end  21 . The high level voltage can be a power to the SoC  20 . The SoC  20  is then active and controls the computer  200  operating in the booting mode or the suspend operation. 
         [0019]    The voltage of the power control end  21  is through the resistors R 4 , R 3  to feedback to the base of the npn type 3, 3 transfer resistor Q 3 . The npn type 3, 3 transfer resistor Q 3  and the npn type 4, 3 transfer resistor Q 4  are in the electric conduction continually. The electric conduction makes the control circuit  12  having a memory function to the SoC  20 . In one embodiment, even if switch  11  is broken immediately after the electric conduction, the control circuit  12  can still output the power control signal to the SoC  20 . 
         [0020]    In other embodiments, the computer  200  is in the suspend mode before connecting the switch  11  and then connects the switch  11 . The high level voltage of the first point J 1  forces the npn type 5, 3 transfer resistor Q 5  being in the electric conduction. The electric conduction of the npn type 5, 3 transfer resistor Q 5  makes an input voltage of the awakening signal end  22  being a low level voltage. If the SoC  20  is in a continuous supply condition, the control circuit  12  also can output the awakening signal to the SoC  20  to awaken the computer  200  in the suspend mode. 
         [0021]    In other embodiments, if the switch  11  is connected continually, the high level voltage of the first point J 1  makes the parallel capacitors C 2 , C 3  being charged continually. Until the voltage between the two ends of the parallel capacitors C 2 , C 3  equals to the start voltage of the npn type 2, 3 transfer resistor Q 2 , the npn type 2, 3 transfer resistor Q 2  is then in the electric conduction. At the moment, the voltage of the base of the npn type 3, 3 transfer resistor Q 3  is low level voltage. The npn type 3, 3 transfer resistor Q 3  and the npn type 4, 3 transfer resistor Q 4  are not active. The voltage outputted from the collector of the npn type 4, 3 transfer resistor Q 4  to the power control end  21  is in the low level voltage (the shutdown signal). Therefore, the power of the SoC  20  is broken and the computer  200  is shutdown. 
         [0022]    In other embodiments, the SoC  20  can set a predetermine time period for controlling the computer  200 . For example, If the computer  200  is active and operates over the predetermine time period. The SoC  20  outputs the high level voltage to the npn type 2, 3 transfer resistor Q 2  through the shutdown signal end  23 . The npn type 2, 3 transfer resistor Q 2  is then in the electric conduction. The npn type 3, 3 transfer resistor Q 3  and the npn type 4, 3 transfer resistor Q 4  are broken and the computer  200  is shutdown. 
         [0023]    In alternative embodiments, instead of a microcontroller, the users can define different states of the switch  11  according to the different conditions. The switch  11  can provide the power or break power to the SoC  20  to control the computer  200 . It saves cost of the microcontroller and saves consumption of the electronic power. 
         [0024]    Although certain embodiments of the present disclosure have been specifically described, the present disclosure is not to be construed as being limited thereto. Various changes or modifications may be made to the present disclosure without departing from the scope and spirit of the present disclosure.