Abstract:
A method of forming a conductive bump of the present invention, includes the steps of, preparing a substrate including a connection pad and a protection insulating layer, in which an opening portion is provided on the connection pad, on a surface layer side, arranging a first conductive ball, at least an outer surface portion of which is made of solder, on the connection pad in the opening portion of the protection insulating layer, filling a solder layer in the opening portion by applying a reflow heating to the first conductive ball, arranging a second conductive ball on the solder layer, and obtaining a conductive bump which protrudes from an upper surface of the protection insulating layer, by joining the solder layer and the second conductive ball by a reflow heating.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is based on and claims priority of Japanese Patent Application No. 2007-300149 filed on Nov. 20, 2007, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a method of forming conductive bumps and, more particularly, a method of forming conductive bumps acting as connection terminals of a wiring substrate onto which a semiconductor chip is flip-chip mounted, or an element built-in silicon wafer, or the like. 
         [0004]    2. Description of the Related Art 
         [0005]    In the prior art, there is a wiring substrate that is equipped with solder bumps on which a semiconductor chip is flip-chip mounted. In the method of forming the solder bumps on the wiring substrate in the prior art, as shown in  FIG. 1A , first, a wiring substrate  100  on which the solder bumps are to be formed is prepared. In the wiring substrate  100 , connection pads  200  connected to the build-up wiring (not shown) are formed on an interlayer insulating layer  110 , and a solder resist  300  in which opening portions  300   a  are provided on the connection pads  200  respectively is formed. 
         [0006]    Then, as shown in  FIG. 1B , a flux  400  is coated on the connection pads  200 . Then, a solder ball  500   a  whose diameter corresponds to the opening portion  300   a  in the solder resist  300  is arranged on the connection pads  200  respectively. At this time, the solder balls  500   a  are arranged to project from an upper surface of the solder resist  300 . 
         [0007]    Then, as shown in  FIG. 1C , the solder balls  500   a  are melted by applying the reflow heating to them, and joined to the connection pads  200 . Then, a flux residue is removed. Accordingly, solder bumps  500  that project from the upper surface of the solder resist  300  are obtained. 
         [0008]    As the technology related to the above, in Patent Literature 1 (Patent Application Publication (KOKAI) Hei 9-51050), it is set forth that a brazing paste (solder) is filled on the connection pads provided on inner surfaces of the recess portions in the insulating substrate, then the ball-like terminals are arranged thereon, and then the heating is applied to melt the brazing paste and the ball-like terminals integrally and also join them to the connection pads by the brazing. 
         [0009]    Also, in Patent Literature 2 (Patent Application Publication (KOKAI) Hei 9-107045), it is set forth that the solder paste is printed on respective electrodes of the package, the ball is arranged on respective electrodes through the mask, and then respective balls are soldered to the electrodes by heating the package. 
         [0010]    Also, in Patent Literature 3 (Patent Application Publication (KOKAI) Hei 11-54557), it is set forth that, in the semiconductor device in which one chip electrodes and the other substrate are electrically connected mutually, the chip electrodes and the substrate are electrically connected to each other via two minute balls that are inserted between one chip electrodes and the other substrate. 
         [0011]    Recently, a narrower pitch (e.g., 100 μm or less) between the connection pads of the wiring substrate is advancing with enhancing performance of the semiconductor chip. Also, in order to get enough reliability of the connection to the semiconductor chip, a height of the solder bumps in excess of 30 μm must be ensured from an upper surface of the solder resist in the wiring substrate. 
         [0012]    In the method of forming the solder bumps using the above solder balls ( FIGS. 1A to 1C ), in order to join the solder bumps  500  to the connection pads  200  stably and prevent a short circuit between adjacent solder bumps  500 , a diameter of the solder ball  500   a  must be set equal to or smaller than a diameter of the opening portions  300   a  of the solder resist  300 . 
         [0013]    For example, when a diameter of the opening portions  300   a  of the solder resist  300  is 50 μm and a height of the same is 20 μm, merely the solder ball  500   a  having a diameter of 50 μm at a maximum can be arranged thereon. In this case, the solder ball  500   a  is arranged on the connection pad in a state that such solder ball is protruded by 30 μm from an upper surface of the solder resist  300 . However, when the reflow heating is applied to the solder ball  500   a  subsequently, the solder ball  500   a  is melted to rise from the upper surface of the solder resist  300  by about 20 μm. As a result, a resultant height of the solder bump  500  becomes lower than a height in the designed specification. 
         [0014]    In this manner, in the method of forming the solder bumps using the solder balls in the prior art, when a reduction of the pitch between the connection pads is proceeding, it is difficult to ensure sufficiently a height of the solder bump. Thus, such a problems exists that the above method cannot easily respond to the mounting of the high-performance semiconductor chip. For this reason, the method of increasing a height of the solder bump from the solder resist by reducing a thickness of the solder resist is considered. But a problem of reliability arises and thus this method cannot also easily respond to the mounting of the high-performance semiconductor chip. 
         [0015]    Also, in above Patent Literatures 1 and 2, because the solder balls are mounted on the solder paste, it is possible to ensure a height of the bump to some extent. However, when the solder paste is applied, sometimes voids may be produced in applying the reflow heating. In particular, it is feared that, specially when a pitch between the connection pads is narrowed, sufficient yield cannot be attained. 
       SUMMARY OF THE INVENTION 
       [0016]    It is an object of the present invention to provide a method of forming conductive bumps, capable of forming conductive bumps of enough height on connection pads in opening portions in a protection insulating layer (a solder resist) with good reliability even when a pitch between connection pads of a wiring substrate, or the like is narrowed. 
         [0017]    The present invention is concerned with a method of forming a conductive bump, which includes the steps of, preparing a substrate including a connection pad and a protection insulating layer, in which an opening portion is provided on the connection pad, on a surface layer side, arranging a first conductive ball, at least an outer surface portion of which is made of solder, on the connection pad in the opening portion of the protection insulating layer, filling a solder layer in the opening portion by applying a reflow heating to the first conductive ball, arranging a second conductive ball on the solder layer, and obtaining a conductive bump which protrudes from an upper surface of the protection insulating layer, by joining the solder layer and the second conductive ball by a reflow heating. 
         [0018]    In the present invention, first, the substrate (the wiring substrate, the element built-in silicon wafer, or the like) that is equipped with the connection pads and the protection insulating layer (solder resist) in which the opening portions are provided on the connection pads on the surface layer side is prepared. Then, the first conductive ball (the solder ball, or the like) is arranged on the connection pads in the opening portions of the protection insulating layer respectively. Then, the solder layer is filled in the opening portions in the protection insulating layer by applying the reflow heating to the first conductive balls. Thus, a level difference of the opening portions in protection insulating layer is eliminated by the solder layer. 
         [0019]    Then, the second conductive ball (the solder ball or other metal ball) is arranged on the solder layers respectively, and then the solder layers and the second conductive balls are joined together by applying the reflow heating. Thus, the conductive bumps projecting from the upper surface of the protection insulating layer are formed. 
         [0020]    In this manner, in the present invention, the solder layer formed of the first conductive ball is buried in the opening portions in the protection insulating layer, and then the conductive bumps are formed by stacking the second conductive ball thereon respectively. As a result, even when a pitch between the connection pads is narrowed smaller than 100 μm, the conductive bumps projecting from the upper surface of the protection insulating layer at a desired height can be formed in a situation that a short circuit between adjacent solder bumps can be prevented. 
         [0021]    Also, the solder layer which is buried in the opening portions in the protection insulating layer is formed of the solder ball. Therefore, there is no fear that voids should be produced in applying the reflow heating unlike the case where the solder paste is buried, and thus the conductive bumps can be obtained with high reliability. 
         [0022]    In one mode of the present invention, the conductive ball is passed through the opening portions in the mask in which the opening portions are provided to correspond to the connection pads, and is arranged on the connection pads respectively. 
         [0023]    Also, in the above present invention, the first and second conductive balls are arranged via the flux. In this mode, in the step of forming the solder layer, the solder layer is formed to have a projection portion that projects from an upper surface of the protection insulating layer, and the flux may be transferred/formed onto the projection portions of the solder layers by pushing the projection portions of the solder layers against the flux provided on a supporting substrate. 
         [0024]    Also, in the step of arranging the second conductive ball, the fluxes provided on the projection portions of the solder layers may be pushed against the second conductive balls arranged side by side in the ball aligning jig and adhered thereto. 
         [0025]    As described above, in the present invention, even when a pitch between connection pads on the wiring substrate, or the like is narrowed, the conductive bumps of enough height can be formed on the connection pads in the opening portions in the protection insulating layer with good reliability. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0026]      FIGS. 1A to 1C  are sectional views showing a method of forming solder bumps in the prior art; 
           [0027]      FIG. 2  is a sectional view (# 1 ) showing a method of forming conductive bumps of a first embodiment of the present invention; 
           [0028]      FIG. 3  is a sectional view (# 2 ) showing the method of forming the conductive bumps of the first embodiment of the present invention; 
           [0029]      FIG. 4  is a sectional view (# 3 ) showing the method of forming the conductive bumps of the first embodiment of the present invention; 
           [0030]      FIGS. 5A to 5C  are sectional views (# 4 ) showing the method of forming the conductive bumps of the first embodiment of the present invention; 
           [0031]      FIGS. 6A to 6C  are sectional views (# 5 ) showing the method of forming the conductive bumps of the first embodiment of the present invention; 
           [0032]      FIG. 7  is a sectional view showing a state in which a semiconductor chip is flip-chip mounted on the conductive bumps of a wiring substrate according to the first embodiment of the present invention; 
           [0033]      FIG. 8  is a sectional view showing a semiconductor device constructed by flip-chip mounting the semiconductor chip on the conductive bumps of the wiring substrate according to the first embodiment of the present invention; 
           [0034]      FIGS. 9A and 9B  are sectional views showing a mode in which the method of forming the conductive bumps of the first embodiment of the present invention is applied in forming the conductive bumps of an element built-in silicon wafer; 
           [0035]      FIGS. 10A to 10C  are sectional views (# 1 ) showing a method of forming conductive bumps of a second embodiment of the present invention; 
           [0036]      FIGS. 11A and 11B  are sectional views (# 2 ) showing the method of forming the conductive bumps of the second embodiment of the present invention; 
           [0037]      FIGS. 12A and 12B  are sectional views (# 3 ) showing the method of forming the conductive bumps of the second embodiment of the present invention; 
           [0038]      FIGS. 13A and 13B  are sectional views (# 4 ) showing the method of forming the conductive bumps of the second embodiment of the present invention; and 
           [0039]      FIG. 14  is a sectional view showing another ball aligning jig used in the second embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0040]    Embodiments of the present invention will be explained with reference to the accompanying drawings hereinafter. 
       First Embodiment 
       [0041]      FIG. 2  to  FIG. 6  are sectional views showing a method of forming conductive bumps of a first embodiment of the present invention. 
         [0042]    In the method of forming the conductive bumps of the first embodiment of the present invention, as shown in  FIG. 2 , first, a wiring substrate  1  on which the conductive bumps are to be formed is prepared. In the wiring substrate  1 , through holes TH are provided in a core substrate  10  made of a glass epoxy resin, or the like, and a through electrode  12  made of copper, or the like is filled in the through holes TH respectively. Also, first wiring layers  14   a  made of copper, or the like and connected mutually via the through electrode  12  are formed on both surface sides of the core substrate  10  respectively. 
         [0043]    Alternately, the first wiring layers  14   a  on both surface sides of the core substrate  10  may be connected mutually via the through hole plating layer formed on inner walls of the through holes TH, and a resin may be filled in the hollows in the through holes TH. 
         [0044]    An interlayer insulating layer  16  for coating the first wiring layers  14   a  is formed on both surface sides of the core substrate  10  respectively. The interlayer insulating layer  16  is formed by pasting a resin film made of an epoxy resin, a polyimide resin, or the like on the core substrate  10 , for example. Via holes VH whose depth arrives at the first wiring layer  14   a  are formed on the interlayer insulating layer  16  on both surface sides of the core substrate  10  respectively. Also, a second wiring layer  14   b  connected to the first wiring layer  14   a  via the via holes VE is formed on the interlayer insulating layer  16  on both surface sides of the core substrate  10  respectively. 
         [0045]    Also, a solder resist  18  in which opening portions  18   a  are provided on connection pads C 1 , C 2  of the second wiring layer  14   b  is formed on both surface sides of the core substrate  10  respectively. 
         [0046]    In this manner, the wiring substrate  1  having the connection pads C 1  and the solder resist  18  (protection insulating layer), in which the opening portion  18   a  is provided on the connection pads C 1  respectively, on the surface side is prepared. Then, a first flux  20  is formed on the connection pads C 1  of the second wiring layer  14   b  on the upper surface side of the wiring substrate  1 . The first flux  20  is coated on the connection pads C 1  in a pattern by the printing, the dispensing, the ink jet method, or the like. Otherwise, the flux may be formed on the overall upper surface side of the core substrate  10 . 
         [0047]    Here, a rigid substrate is illustrated as the wiring substrate  1 . But a flexible wiring substrate using a film as a substrate may be employed. 
         [0048]    Next, a method of mounting conductive balls on the connection pads C 1  on the upper surface side of such wiring substrate  1  will be explained hereunder. As shown in  FIG. 3 , above wiring substrate  1  is loaded on a stage of a ball mounting apparatus, and then a mask  40  used to mount the conductive balls is arranged on the wiring substrate  1 . The mask  40  is composed of a metal mask portion  42  in which opening portions  40   a  are provided, a mesh portion  44  provided on the peripheral side of the metal mask portion  42  and is made of a resin, or the like, and a frame portion  46  provided around the mesh portion  44 . 
         [0049]    At this time, the mask  40  is arranged to be aligned to the wiring substrate  1  by recognizing alignment marks of the wiring substrate  1  while using an image recognizing camera (not shown), such that the opening portions  40   a  of the mask  40  corresponds to the connection pads C 1  of the wiring substrate  1 . 
         [0050]    Then, as also shown in  FIG. 3 , first conductive balls  30  are supplied onto the mask  40  from a ball supplying means (not shown). The first conductive balls  30  are supplied in considerably larger numbers than those of the opening portions  40   a  of the mask  40  (corresponding to the connection pads C 1  of the wiring substrate  1 ). 
         [0051]    Then, as also shown in  FIG. 3 , a large number of first conductive balls  30  are moved by a brush  48  and swept out into one end side of the mask  40  (an outside area of a production area). At this time, the first conductive balls  30  moved by the brush  48  pass through respective opening portions  40   a  of the mask  40 , and then stick to the first flux  20  on the underlying connection pads C 1  and are arranged there. 
         [0052]    A size of the opening portion  40   a  of the mask  40  is set one size large than a size of the first conductive ball  30 . Thus, the first conductive ball  30  can easily pass through the opening portion  40   a  of the mask  40 . In this manner, one of the first conductive balls  30  is transferred into the each portion  40   a  of the mask  40  respectively, and is arranged on the underlying connection pads C 1  of the wiring substrate  1  respectively. 
         [0053]    Then, as shown in  FIG. 4 , the wiring substrate  1  is put down, and is separated from the mask  40 . Then, the wiring substrate  1  is carried from the stage to the outside. 
         [0054]    In the subsequent steps, explanation will be made while referring to fragmental enlarged sectional views in which an A portion of the wiring substrate  1  is illustrated in an enlarged manner. As shown in  FIG. 5A , the first conductive balls  30  are arranged on the connection pads C 1  on the upper surface side of the wiring substrate  1  respectively by the ball mounting method using the mentioned-above mask  40 . The first conductive balls  30  are arranged on the connection pads C 1  in a state that these balls are sunk in the first flux  20  in the opening portions  18   a  of the solder resist  18 . 
         [0055]    As the first conductive ball  30 , the solder ball made fully of solder, the ball formed by coating an outer surface of a core ball made of a resin with solder, the ball formed by coating an outer surface of a core ball made of a copper with solder, or the like may be employed. In the first conductive ball  30 , the solder must be melted by the reflow heating, and therefore the ball at least an outer surface portion of which is formed of solder is employed. 
         [0056]    The first conductive ball  30  is set in size to fill a major portion of the opening portion  18   a  of the solder resist  18  when the ball is melted by the reflow heating. For example, when a height of the opening portion  18   a  of the solder resist  18  (a film thickness of the solder resist  18  on the connection pad C 1 ) is 20 μm and a diameter of the opening portion  18   a  is 50 μm, a diameter of the first conductive ball  30  is set to 40 to 45 μm. 
         [0057]    Then, the wiring substrate  1  on which the first conductive balls  30  are mounted is reflow-heated at a temperature of 240° C., for example. Accordingly, as shown in  FIG. 5B , the first conductive ball  30  is melted and thus a solder layer  32  containing the solder as a principal component is filled in the opening portion  18   a  of the solder resist  18  and joined to the connection pad C 1 . Because an oxide film of the solder is removed by a function of the first flux  20  when the first conductive ball  30  is melted, the solder layer  32  is joined to the connection pad C 1  with good reliability. 
         [0058]    At this time, as described above, the first conductive ball  30  is set in size to fill the opening portion  18   a  of the solder resist  18  when the ball is melted. Therefore, the main portion of the opening portion  18   a  of the solder resist  18  is buried by the solder layer  32 . Then, as shown in  FIG. 5C , a flux residue  20   x  still remaining on the solder layer  32  in  FIG. 5B  is removed. 
         [0059]    Then, as shown in  FIG. 6A , second fluxes  22  are formed on the solder layers  32  as patterns. The second flux  22  is formed by the similar method to the first flux  20 , and may be formed on the whole surface of the wiring substrate  1  on the upper surface side. Here, when a flux which is not cured after the reflow heating is applied (low solid content flux) is employed as the above first flux  20  in  FIG. 2 , such flux may be employed as the second flux  22  without cleaning it. In this case, the step of removing the flux residue  20   x  in  FIG. 5C  and the step of forming the second flux  22  in  FIG. 6A  are omitted. 
         [0060]    Then, as shown in  FIG. 6B , a second conductive ball  50  is mounted on the second fluxes  22  on the solder layers  32  respectively. Like the foregoing method explained in  FIG. 3  and  FIG. 4 , the second conductive ball  50  is arranged on the solder layers  32  through the opening portions  40   a  of the mask  40  respectively. As the second conductive ball  50 , a metal ball such as a single-body copper ball not containing the solder, or the like may be employed in addition to the ball at least an outer surface portion of which is formed of the solder, like the first conductive ball  30 . 
         [0061]    Then, the reflow heating is applied to the wiring substrate  1  on which the second conductive balls  50  are provided. Thus, as shown in  FIG. 6C , the second conductive balls  50  (the solder balls, or the like) and the underlying solder layers  23  are melted, so that the second conductive balls  50  are joined to the solder layers  23  to constitute conductive bumps B. In this case, when the metal ball not containing the solder is employed as the second conductive ball  50 , the underlying solder layers  23  are melted and thus the solder layer  32  are joined to the metal balls to constitute conductive bumps B. 
         [0062]    In the present embodiment, a height of the conductive bump B from the upper surface of the solder resist  18  is mainly decided by the second conductive ball  50 . The conductive bump B having a desired height can be obtained by adjusting a diameter of the second conductive ball  50 . 
         [0063]    For example, when the opening portion  18   a  of the solder resist  18  is mainly buried by the solder layer  32  and then the solder bump B projecting from the upper surface of the solder resist  18  at a height of 30 μm is obtained, the solder ball whose diameter is about 40 μm is employed as the second conductive ball  50 . When the solder ball is employed as the second conductive ball  50 , the conductive bump B whose height is slightly lower than a height of the second conductive ball  50  is formed because the solder is melted. 
         [0064]    As described above, in the method forming the conductive bumps of the present embodiment, first, the first conductive ball  30  (the ball at least an outer surface portion of which is made of solder) is mounted on the connection pads C 1  in the opening portions  18   a  of the solder resist  18  respectively, and then the solder layer  32  is buried in the opening portions  18   a  of the solder resist  18  by applying the reflow heating. Accordingly, a level difference of the opening portions  18   a  of the solder resist  18  is eliminated. 
         [0065]    Then, the second conductive ball  50  (the solder ball, or the like) is mounted on the solder layers  32  respectively, and then the solder layers  32  and the second conductive balls  50  are melted by applying the reflow heating and joined together. Thus, the conductive bumps B joined to the connection pads C 1  respectively and projecting from the upper surface of the solder resist  18  at a desired height are obtained. 
         [0066]    In this manner, in the present embodiment, the solder layer  32  formed of the solder ball, or the like is buried in the opening portions  18   a  of the solder resist  18  on the connection pads C 1  respectively to planarize the surface, and then the second conductive ball  50  is stacked separately on the solder layers  32  respectively, whereby the conductive bumps B are obtained. 
         [0067]    According to employment of such approach, even when a pitch between the connection pads C 1  is narrowed smaller than 100 μm (line:space=50:50 μm), the conductive bumps B projecting from the upper surface of the solder resist  18  at a desired height can be formed in a situation that a short circuit between adjacent solder bumps in the lateral direction can be prevented. 
         [0068]    In addition, even when a film thickness of the solder resist  18  is increased (for example, 30 to 50 μm), the conductive bumps B having a desired height can be formed independent on the film thickness of the solder resist  18  since the opening portions  18   a  of the solder resist  18  are buried by the solder layer  32 . 
         [0069]    Also, the solder layer  32  buried in the opening portions  18   a  of the solder resist  18  is formed of the solder ball. Therefore, there is no fear that voids should be produced in applying the reflow heating unlike the case where the solder paste is buried, and thus the conductive bumps B with high reliability can be obtained. 
         [0070]    In this case, a height of the conductive bumps B can be further increased by stacking a conductive ball on the conductive bumps B via the flux respectively. 
         [0071]    Next, a method of flip-chip connecting the semiconductor chip to the wiring substrate equipped with the conductive bumps obtained by the present embodiment will be explained hereunder. As shown in  FIG. 7 , a semiconductor chip  60  having bumps  62  (solder) thereon is prepared, the bumps  62  of the semiconductor chip  60  are arranged to the conductive bumps B (solder) of the wiring substrate  1 , and the bumps  62  are flip-chip joined to the conductive bumps B by the reflow heating. 
         [0072]    Accordingly, as shown in  FIG. 8 , the conductive bumps B of the wiring substrate  1  and the bumps  62  of the semiconductor chip  60  are fused together and then bump electrodes  34  are formed. Thus, the semiconductor chip  60  is connected electrically to the connection pads C 1  of the semiconductor substrate  1  by the bump electrodes  34 . 
         [0073]    The bumps  62  of the semiconductor chip  60  and the conductive bumps B of the wiring substrate  1  can be formed of not only the solder but also various metals. 
         [0074]    Then, before or after the mounting of the semiconductor chip  60 , external connection terminals  36  are provided by mounting the solder ball on the connection pads C 2  on the lower surface side of the wiring substrate  1 , or the like. 
         [0075]    Accordingly, a semiconductor device  2  according to the present embodiment is obtained. In this case, when the large-size substrate for multiple production is used as the wiring substrate  1 , the wiring substrate  1  is cut and divided before or after the semiconductor chip  60  is the mounted. 
         [0076]    In the present embodiment, the method of forming the conductive bumps on the wiring substrate onto which the semiconductor chip is to be flip-chip mounted is illustrated. But the conductive bumps may be formed on the element built-in silicon wafer instead of the wiring substrate. Such element built-in silicon wafer  70  is shown in  FIG. 9A . As shown in  FIG. 9A , an element area  72 , in which an semiconductor element such as a transistor, a diode, or the like is built, is provided in the element built-in silicon wafer  70 . Also, a multi-layered wiring (not shown) which wires the transistors, or the like is formed over the element area  72 . 
         [0077]    Also, the connections pads C 1  connected to the multi-layered wiring are provided on the upper surface side of the element built-in silicon wafer  70 . Also, the protection insulating layer  18  (passivation layer) in which the opening portions  18   a  are provided on the connections pads C 1  is formed. A plurality of chip areas are built in the element built-in silicon wafer  70 , but one chip area in the wafer is shown schematically in  FIG. 9A . 
         [0078]    Then, as shown in  FIG. 9B , according to the similar method to the above method of forming the conductive bumps, the conductive bumps B which are connected to the connections pads C 1  of the element built-in silicon wafer  70  and projected from the upper surface of the protection insulating layer  18  at a desired height are formed. 
         [0079]    Such element built-in silicon wafer  70  is divided into individual semiconductor chips such as CPUs, memories, etc. by the dicing. 
       Second Embodiment 
       [0080]      FIG. 10  to  FIG. 13  are sectional views showing a method of forming conductive bumps of a second embodiment of the present invention. A difference of the second embodiment from the first embodiment resides in the method of forming the second flux and the method of mounting the second conductive balls. In the second embodiment, detailed explanation about the same steps as those in the first embodiment will be omitted herein. 
         [0081]    First, as shown in  FIG. 10A , like the first embodiment, the first conductive ball  30  is arranged on the first flux  20  on the connection pads C 1  in the opening portions  18   a  of the solder resist  18  respectively. In the second embodiment, a diameter of the first conductive ball  30  is set larger than that of the first embodiment such that the solder layer is protruded from the upper surface of the solder resist  18  after the reflow heating. For example, when a height of the opening portion  18   a  of the solder resist  18  is 20 μm and a diameter of the same is 50 μm, the first conductive ball  30  whose diameter is slightly smaller than 50 μm is placed. Thus, the first conductive ball  30  is caused to project from the upper surface of the solder resist  18  by about 30 μm. 
         [0082]    Then, as shown in  FIG. 10B , the first conductive ball  30  is melted by applying the reflow heating. Thus, the solder layer  32  is buried in the opening portion  18   a  of the solder resist  18 , and also is joined to the connection pad C 1 . At this time, a height of the first conductive ball  30  is lowered because it is melted, and the solder layer  32  is formed to have a projection portion  32   a  that is projected from the upper surface of the solder resist  18  by about 20 μm. 
         [0083]    In this manner, in the second embodiment, the second flux is formed on the top end portions of the solder layers  32  as described later. Therefore, the projection portions  32   a  of the solder layers  32  are caused to project from the upper surface of the solder resist  18 . 
         [0084]    Then, as shown in  FIG. 10C , an adsorbing jig  80  is caused to adsorb the solder resist  18  on the back surface of the wiring substrate  1 , and thus the wiring substrate  1  is supported by the adsorbing jig  80 . The adsorbing jig  80  has an adsorbing port (not shown), and the adsorbing jig  80  can adsorb and support the wiring substrate  1  by evacuating an air through the adsorbing port. 
         [0085]    Then, as also shown in  FIG. 10C , a supporting substrate  85  on a surface of which the viscous second flux  22  is coated is prepared. Then, as shown in  FIG. 10C  and  FIG. 11A , the projection portions  32   a  of the solder layers  32  on the wiring substrate  1  which is supported by the adsorbing jig  80  are pushed against the second flux  22  on the supporting substrate  85 . 
         [0086]    Then, as shown in  FIG. 11B , the wiring substrate  1  which is supported by the adsorbing jig  80  is pulled up from the second flux  22 . Thus, the second flux  22  is transferred/formed onto the top ends of the projection portions  32   a  of the solder layers  32  on the wiring substrate  1 . In this manner, since the transferring technology is utilized in the second embodiment, the second flux  22  can be coated selectively and collectively in a self-alignment fashion onto the projection portions  32   a  of the solder layers  32  without use of a mask. 
         [0087]    Then, as shown in  FIG. 12A , a ball aligning jig  90  used to align a plurality of balls is prepared. A plurality of recess portions  92  are provided on the upper surface side of the ball aligning jig  90 , and an alignment port  94  used to align the ball is opened in centers of bottom portions of the recess portions  92  respectively. Then, the second conductive ball  50  is arranged on the alignment ports  94  in the recess portions  92  of the ball aligning jig  90  respectively. The alignment ports  94  in the recess portions  92  of the ball aligning jig  90  are aligned to correspond to the connection pads C 1  of the wiring substrate  1 . 
         [0088]    Then, as also shown in  FIG. 12A , the second fluxes  22  which are transferred onto the projection portions  32   a  of the solder layers  32  on the wiring substrate  1 , which is supported by the adsorbing jig  80 , are aligned to oppose to the second conductive balls  50  which are aligned on the ball aligning jig  90 . Then, the second fluxes  22  on the solder layers  32  are pushed against the second conductive balls  50 , and are adhered collectively thereto. 
         [0089]    Then, as shown in  FIG. 12B , the wiring substrate  1  which is supported by the adsorbing jig  80  is pulled up upward. Thus, the second conductive balls  50  are collectively transferred/formed onto the second fluxes  22  on the solder layers  32  on the wiring substrate  1  from the ball aligning jig  90  side. 
         [0090]    In this manner, as shown in  FIG. 13A , like the first embodiment, the second conductive ball  50  is stacked on the solder layers  32  on the connection pads C 1  of the wiring substrate  1  via the second flux  22  respectively. 
         [0091]    In this case, as shown in  FIG. 14 , instead of the ball aligning jig  90  in which a plurality of recess portions  92  are arranged in  FIG. 12A , while using a plate-like ball aligning jig  91  having a collective recess portion  92   a  in the inside, a large number of conductive balls may be spread all over in the lateral direction and be arranged in the recess portion  92   a . In this case, like  FIG. 12B , the second conductive balls  50  can also be adhered collectively onto the second fluxes  22  provided to the projection portions  32   a  of the solder layers  32  on the wiring substrate  1  individually. 
         [0092]    Then, the reflow heating is applied to the structure in  FIG. 13A , and then the flux residue is removed. As a result, as shown in  FIG. 13B , the solder layers  32  and the second conductive balls  50  are melted mutually and thus the conductive bumps B projected from the upper surface of the solder resist  18  at a desired height can be obtained. 
         [0093]    The second embodiment can achieve the similar advantages to those in the first embodiment. In addition to this, in the second embodiment, the second fluxes  22  and the second conductive balls  50  are formed collectively by the transfer method. Therefore, particularly when a pitch between the connection pads C 1  is narrowed, the conductive bumps B can be formed with good reliability at a higher production efficiency than that in the first embodiment.