Abstract:
A channel selection voltage generator comprises a tuning voltage generator circuit having a capacitor for supplying a tuning voltage to an electronic tuner, a first constant current source for constantly discharging the capacitor at a first constant current and a second constant current source adapted to be rendered selectively in an operative state and in an inoperative state for selectively charging the capacitor at a second constant current which is higher than the first constant current, a frequency discrimination circuit for producing a discrimination signal representative of the amount of frequency deviation when a tuning voltage deviates from a receiving frequency, a buffer circuit for producing a binary &#34;1&#34; level signal when the discrimination signal is higher than a predetermined value and producing a binary &#34;0&#34; level signal when the discrimination signal is lower than the predetermined value, and a control circuit for causing the second constant current source to assume the inoperative state when the binary signal is at &#34;0&#34; level and causing the second constant current source to assume the operative state when the binary signal is at &#34;0&#34; level, the control circuit serving to maintain the second constant current source in the operative state or the inoperative state irrespective of the level of the binary signal during the frequency sweep.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a channel selection voltage generator for a radio receiver, a television receiver or the like which is equipped with an automatic frequency control circuit for automatically maintaining a received signal frequency at a constant frequency. 
     2. Description of the Prior Art 
     The channel selection voltage generator for a radio receiver, a television receiver or the like which is equipped with an automatic frequency control circuit has been known, for example, by Japanese Pat. Appln. Post-Exam. Publn. No. 22125/68. In such a prior art apparatus, however, since the direction of sweep is limited to one direction, when it is desired to select a channel or a broadcasting station which is close to a channel or a broadcasting station currently being received but lies in a rearward frequency position with respect to the sweep direction, it is necessary to sequentially capture undesired stations and release the capture. Therefore, the channel selection operation is very troublesome. 
     Furthermore, since the prior art apparatus uses a continuously variable current source to control the received signal frequency, the apparatus is not suitable for digital control, and in particular it is not suitable for the channel selection voltage generator for a television receiver which is equipped with a discriminator for discriminating a picture carrier from a sound carrier to produce a digital discrimination signal. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a channel selection voltage generator capable of bidirectionally sweeping the frequency. 
     It is another object of the present invention to provide a channel selection voltage generator capable of automatically and in a digital manner controlling the frequency. 
     The channel selection voltage generator of the present invention may comprise a capacitor with a charge the voltage across which is supplied to an electronic tuner, a first constant current source for charging or discharging the capacitor with a first constant current, and a second constant current source for discharging or charging the capacitor with a second constant current higher than the first constant current and adapted to be rendered selectively operative or inoperative. When the second constant current source is operative, the capacitor is charged or discharged with a differential current between the first and second constant currents for a frequency sweep, and when the second constant current source is inoperative, the capacitor is charged or discharged with the first constant current and the frequency sweep takes place in the opposite direction to the first frequency sweep. During the frequency sweep, the second constant current source is maintained in an operative or in an inoperative state until a broadcasting signal is captured, and when the broadcasting signal is captured, the operative state and the inoperative state of the second constant current source are repeated such that the charge voltage of the capacitor lies within a predetermined range centered at a capacitor charge voltage corresponding to the received signal frequency. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of one embodiment of a channel selection voltage generator of the present invention. 
     FIG. 2 shows a specific example of the tuning voltage generator circuit shown in FIG. 1. 
     FIG. 3 shows a frequency characteristic curve of the frequency discriminator shown in FIG. 1. 
     FIG. 4 shows a specific example of the buffer circuit shown in FIG. 1. 
     FIG. 5 shows an input-output characteristic of the buffer circuit of FIG. 4. 
     FIG. 6 shows a specific example of a Schmitt circuit shown in FIG. 1. 
     FIG. 7 shows an input-output characteristic of the Schmitt circuit of FIG. 6. 
     FIG. 8 shows a specific example of a synchronizing signal discrimination circuit shown in FIG. 1. 
     FIG. 9 shows waveforms at major points in FIG. 1. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 1, numeral 1 denotes an antenna, 2 an electronic tuner, 3 an intermediate frequency amplifier, 4 a video detector circuit, 5 a video amplifier circuit, 6 a picture tube, 7 a sync separation circuit, 8 a deflection circuit and 9 a frequency discriminator circuit. These constitute a portion of a conventional television receiver. A tuning voltage generator circuit 20 comprises a capacitor 24, a constant current source 25 for charging the capacitor 24 and a constant current source 26 for discharging the capacitor 24. The current of the constant current source 25 may be in the order of 200 μA and the current of the constant current source 26 may be one half of the current of the constant current source 25, that is, in the order of 100 μA. Thus, when both the constant current sources 25 and 26 are rendered operative, the capacitor 24 is charged with a differential current of 100 μA to produce a voltage which increases with time at an output terminal 22. On the other hand, when the constant current source 25 is rendered inoperative while the constant current source 26 is kept operative, the capacitor 24 is discharged with the current of 100 μA of the constant current source 26 to produce a voltage which decreases with time at the output terminal 22. When the capacitance of the capacitor 24 is equal to 22 μF, the rate of increase or decrease of the charge voltage is approximately 4.5 V/sec. The charge voltage of the capacitor 24 is supplied to a variable capacitance diode of the tuner 2 as a tuning voltage to determine a receiving frequency. The constant current source 25 is rendered operative when a binary signal applied to a terminal 23 is &#34;1&#34; (e.g. 12 volts) and is rendered inoperative when the binary signal is &#34;0&#34; (e.g. 0 volt). 
     The tuning voltage generator circuit 20 may be constructed as shown in FIG. 2, in which a transistor 260 constitutes the constant current source 26 which constantly discharges the capacitor 24 with the current of 100 μA. Transistors 250 and 252 constitute the constant current source 25, and they are both turned on when the &#34;1&#34; level signal is applied to the control terminal 23 to operate as the 200 μA constant current source. In this case, the capacitor 24 is charged with the differential current of 100 μA of the two constant current sources. When the &#34;0&#34; level signal is applied to the control terminal 23, the transistors 250 and 252 are both nonconductive. 
     Input-output conditions for AND circuits 31 and 32, NOR circuits 33 and 34, NAND circuits 35 and 36, an inverter circuit 37 and set-reset type flip-flop circuits 38 and 39 are shown in the truth table set forth below, where &#34;1&#34; corresponds to 12 volts and &#34;0&#34; corresponds to 0 volt. 
     
         ______________________________________Truth Table______________________________________ ##STR1##                ##STR2##A       B       C            A     B     C______________________________________0       0       0            0     0     10       1       0            0     1     01       0       0            1     0     01       1       1            1     1     0______________________________________ ##STR3##                ##STR4##A       B       C             A      B______________________________________0       0       10       1       1             0      11       0       11       1       0             1      0______________________________________ ##STR5##--R     --S     Qn______________________________________0       0       10       1       01       0       11       1       Qn-1______________________________________ 
    
     The frequency discriminator circuit 9 has an input-output characteristic as shown in FIG. 3, in which a center frequency f o  corresponds to the frequency of the picture carrier wave in the intermediate frequency amplifier 3 of FIG. 1, and it is equal to 58.75 MHz in a Japanese standard television receiver. The output signal of the frequency discriminator circuit 9 which is produced in accordance with the characteristic shown in FIG. 3 as the frequency is swept is converted to binary signals by a buffer circuit 40 and a Schmitt circuit 50, respectively. 
     The buffer circuit 40 may comprise, as shown in FIG. 4, resistors 41 and 42, inverters 43 and 44 and a potentiometer 45, and it has an input-output characteristic between input and output terminals 46 and 47 as shown in FIG. 5. The potentiometer 45 serves to compensate for any variance of a threshold voltage of the inverter circuit 43. 
     The Schmitt circuit 50 may comprise, as shown in FIG. 6, resistors 51, 52 and 58, inverter circuits 53 and 54 and a potentiometer 55 and it has an input-output characteristic between input and output terminals 56 and 57 as shown in FIG. 7. The potentiometer 55 serves to compensate for any variance of a threshold voltage of the inverter circuit 53. 
     A synchronizing signal discriminator circuit 60 produces a binary &#34;1&#34; signal only when the phase of the horizontal synchronizing signal derived from the output of the sync separation circuit 7 coincides with the phase of the horizontal flyback pulse derived from the deflection circuit 8, and produces a binary &#34;0&#34; signal when they do not coincide with each other. The synchronizing signal discriminator circuit 60 may be constructed as shown in FIG. 8, in which a power supply voltage is at 12 volts, and the positive polarity horizontal synchronizing signal of approximately 10 volts peak-to-peak is applied to an input terminal 61 from the sync separation circuit 7 while the positive polarity horizontal flyback pulse of approximately 10 volts peak-to-peak is applied to an input terminal 62 from the deflection circuit 8. 
     When a normal synchronizing signal is not included in a composite video signal derived from the output of the video detector circuit 4, the voltage at the input terminal 61 does not exceed the threshold voltage (approximately 6 volts) of the NAND circuit 63 at the same timing as the voltage at the input terminal 62 does. In this case, therefore, the output voltage of the NAND circuit 63 is equal to 12 volts and the capacitor 64 is charged to 12 volts. Accordingly, the output of the inverter circuit 65, that is, the voltage at the output terminal 66 assumes 0 voltage. When the output of the video detection circuit 4 produces the normal composite video signal and the output of the sync separation circuit 7 includes the horizontal synchronizing signal, the voltages at the input terminals 61 and 62 simultaneously assume approximately 10 volts periodically. Thus, the voltage of the capacitor 64 which has been charged through resistors 67 and 68 during the absence-of-synchronizing signal period is discharged through a resistor 68 and a diode 69 each time a synchronizing signal is applied. When the resistance of the resistor 68 is selected to be sufficiently smaller than the resistance of the resistor 67, the charge voltage of the capacitor 64 when the normal horizontal synchronizing signal is received falls below the threshold voltage (approximately 6 volts) of the inverter circuit 65 so that the output of the inverter circuit 65, that is, the voltage at the output terminal 66 assumes 12 volts. Accordingly, when the output of the video detector circuit 4 includes the normal composite video signal, the synchronizing signal discriminator circuit 60 produces a binary &#34;1&#34; signal, and when the output of the video detector circuit 4 does not produce the normal composite video signal, the synchronizing signal discriminator circuit 60 produces a binary &#34;0&#34;  signal. 
     Since the frequency discriminator circuit 9 produces the output voltage as shown in FIG. 3 as the receiving frequency of the signal carrier changes, it can discriminate whether the signal carrier is being received or not. However, since the television signal includes a picture carrier and a sound carrier and the television receiver is designed to carry out normal reproduction when the tuner 2 is tuned to the picture carrier, it is necessary to discriminate the picture carrier from the sound carrier when the television signal is selected by the sweep of the frequency. When the tuning frequency of the tuner 2 coincides with the sound carrier frequency, no horizontal synchronizing signal is produced at the output of the sync separation circuit 7 and the picture carrier can be discriminated from the sound carrier by the synchronizing signal discriminator circuit 60. 
     Channel selection starting switches 71 and 72 are normally open and they are closed only when they are manually actuated. When the channel selection starting switches are closed, flip-flop circuits 38 and 39 are set, respectively. 
     First, assume that a television broadcasting wave is being received and the receiving frequency is stable. In this case, the flip-flop circuits 38 and 39 are both in their reset states and the outputs Q are at &#34;0&#34; level. The output of the buffer circuit 40 is inverted by a NOR circuit 33 and further inverted by another NOR circuit 34. Therefore, the same signal as the output of the buffer circuit 40 is applied to the control terminal 23. 
     If the output of the NOR circuit 34 is at &#34;1&#34; level at a certain time, the constant current source 25 is rendered operative and the capacitor 24 is charged. As a result, the output voltage of the tuning voltage generator circuit 20 gradually rises so that the tuning frequency of the electronic tuner 2 also gradually rises. The tuning frequency of the electronic tuner 2 is monitored by the frequency discriminator circuit 9. As the input frequency to the frequency discriminator circuit 9 rises above the frequency f o  by a small frequency increment, the output voltage of the frequency discriminator circuit 9 rapidly falls in accordance with the characteristic shown in FIG. 3. When the output voltage of the frequency discriminator circuit 9, that is, the input voltage to the buffer circuit 40 falls below 6 volts, the output of the buffer circuit 40 assumes the &#34;0&#34; level and the constant current source 25 is rendered inoperative so that the capacitor 24 is discharged by the constant current source 26. As a result, the output voltage of the tuning voltage generating circuit 20 gradually falls and the tuning frequency of the electronic tuner 2 also gradually falls. Accordingly, the input frequency of the frequency discriminator circuit 9 approaches the frequency f o  and falls below f o  by a small frequency increment, at which point the output voltage of the frequency discriminator circuit 9 rapidly rises. When the output voltage of the frequency discriminator circuit 9, that is, the input voltage to the buffer circuit 40 exceeds 6 volts, the output voltage of the buffer circuit again assumes the &#34;1&#34; level and the output voltage of the tuning voltage generator circuit 20 gradually rises. Thus, when a television broadcasting wave is being received and the circuit is stable, the tuning frequency is stable while it oscillates around the normal receiving frequency by a small frequency increment. The output voltage of the frequency discriminator circuit 9 increases or decreases by only several millivolts around 6 volts and this change of frequency is too small to be detected on the screen of a television receiver. 
     The frequency sweep operation when the channel selection starting switches 71 and 72 are closed will now be explained. The output terminals Q of the flip-flop circuits 38 and 39 are at &#34;1&#34; level when they are set and at &#34;0&#34; level when they are reset. The set and reset states of the flip-flop circuits 38 and 39 are maintained unless reset and set signals, respectively, are applied subsequently. When the channel selection starting switch 71 is closed, the S-terminal of the flip-flop circuit 38 and the R-terminal of the flip-flop 39 assume &#34;0&#34; level so that the flip-flop circuits 38 and 39 are set (Q=&#34;1&#34;) and reset (Q=&#34;0&#34;), respectively. Under this condition, irrespective of the output state of the buffer circuit 40, the output of the NOR circuit 33 assumes &#34;0&#34; level and the output of the NOR circuit 34 assumes &#34;1&#34; level so that the constant current source 25 is rendered operative. Consequently, the output voltage of the tuning voltage generating circuit 20 gradually rises. In order to render the constant current source 25 inoperative, it is necessary to switch at least one input of the NOR circuit 34 to &#34;1&#34; level. When the channel selection starting switch 72 is closed to set the flip-flop circuit 39, the first input terminal 34A of the NOR circuit 34 becomes to be at &#34;1&#34; level. Otherwise, when the output of the NAND circuit 35 assumes &#34;0&#34; level to reset the flip-flop circuit 38 and the output of the buffer circuit 40 produces a &#34;0&#34; level signal, the second input terminal 34B of the NOR circuit 34 becomes to be at &#34;1&#34; level. Accordingly, when one of these cases occurs, the operation of the tuning voltage generator circuit 20 is switched from rising mode to falling mode. 
     When the channel selection starting switch 72 is closed, the flip-flop circuit 39 is set and the &#34;1&#34; level signal is applied to the first input terminal 34A of the NOR circuit 34. Therefore, irrespective of the input state at the second input terminal 34B and hence irrespective of the output state of the buffer circuit 40, the output of the NOR circuit 34 assumes &#34;0&#34; level and the constant current source 25 is rendered inoperative. Consequently, the charge voltage of the capacitor 24 gradually falls. Since the flip-flop circuit 38 is reset by the closure of the channel selection starting switch 72, the output of the NAND circuit 36 produces the &#34;0&#34; level signal in the course of fall of the tuning voltage. At this time, the flip-flop circuit 39 is reset and the output of the buffer circuit 40 assumes &#34;1&#34; level so that the constant current source 25 is switched from inoperative state to operative state. 
     Thus, the input state at the control terminal 23 is at &#34;1&#34; level when the channel selection starting switch 71 is closed and the flip-flop circuits 38 and 39 are set and reset, respectively, it is at &#34;0&#34; level when the channel selection starting switch 72 is closed and the flip-flop circuits 38 and 39 are reset and set, respectively, and it assumes the output state of the buffer circuit 40 when the flip-flop circuits 38 and 39 are both reset. 
     Now, consider a channel A and a channel B and the channel B lies at a higher frequency than the channel A. When the receiving channel is to be changed from the channel A to the channel B, the output of the NAND circuit 35 is maintained at &#34;1&#34; level to keep the flip-flop circuit 38 set until the charge voltage of the capacitor 24 changes from the tuning voltage for the channel A and approaches the tuning voltage for the channel B, when the output of the NAND circuit 35 is switched to &#34;0&#34; level to reset the flip-flop circuit 38 so that the charge voltage of the capacitor 24 is controlled by the output state of the buffer circuit 40. With this arrangement, the pull-in of the tuning frequency of the tuner 2 to an undesired signal frequency such as the sound carrier of the television signal during the frequency sweep can be prevented. Similarly, when the receiving channel is to be changed from the channel B to the channel A, the output of the NAND circuit 36 is maintained at &#34;1&#34; level in the course of a fall of the charge voltage of the capacitor 24 and the flip-flop circuit 39 is kept set. 
     FIG. 9 shows voltage waveforms at major points in FIG. 1, where the abscissa represents the receiving frequency, f PA  and f SA  represent the picture carrier frequency and the sound carrier frequency, respectively, of the channel A, and f PB  and f SB  represent the picture carrier frequency and the sound carrier frequency, respectively, of the channel B. As the frequency is swept, the output of the frequency discriminator circuit 9 produces a voltage shown in FIG. 9(a) and the output of the synchronizing signal discriminator circuit 60 produces a voltage shown in FIG. 9(b). The horizontal synchronizing usually appears only in the vicinity of the normal tuning frequency, that is, the frequency f PA  or f PB , and when the sound carrier approaches the tuning frequency, the level of the sound carrier signal becomes higher than the level of the picture carrier signal so that the signal waveform detected by the video detector circuit 4 does not include the composite video signal and the output of the sync separation circuit 7 does not produce the normal horizontal synchronizing signal. Accordingly, the output assumes &#34;1&#34; level only in the vicinity of the frequencies f PA  and f PB , as shown in FIG. 9(b). FIG. 9(c) shows an output voltage of the Schmitt circuit 50 when the receiving frequency rises. It assumes &#34;1&#34; level when the output of the frequency discriminator circuit 9 produces a voltage of 7 volts or higher. FIG. 9(d) shows an inversion of a logical AND of the binary signals shown in FIG. 9,(b) and (c) and it shows an output state of the NAND circuit 35 when the receiving frequency rises. FIG. 9(e) shows an output voltage of the Schmitt circuit 50 when the receiving frequency falls. It assumes &#34;1&#34; level when the output of the frequency discriminator circuit 9 produces a voltage of 5 volts or higher. FIG. 9(f) shows an inversion of a logical AND of the output of the inverter 37 to which the binary signal shown in FIG. 9(e) is applied and the binary signal shown in FIG. 9(b), and it shows an output state of the NAND circuit 36 when the receiving frequency falls. 
     When the channel A is being selected, the capacitor 24 is charged to a voltage V PA  which corresponds to the receiving frequency f PA . The output of the frequency discriminator circuit 9 produces a voltage which varies around 6 volts within the amount of several millivolts. When the channel selection starting switch 71 is closed to set and reset the flip-flop circuits 38 and 39, respectively, the capacitor 24 is charged as described above and the charge voltage rises above V PA  and the receiving frequency also rises. Since the output of the frequency discriminator 9 falls below 5 volts in response to a slight rise of the receiving frequency, the output of the Schmitt circuit 50 assumes &#34;0&#34; level so that the flip-flop circuit 38 is kept set even after the channel selection starting switch 71 is opened. Thus, the receiving frequency continues to rise. As the receiving frequency rises, the audio signal of the channel A is received and the output of the frequency discriminator circuit 9 rises above 7 volts to change the output of the Schmitt circuit 50 to &#34;1&#34; level. However, since no horizontal synchronizing signal is present, the flip-flop circuit 38 is not reset but kept set so that the receiving frequency continues to rise. Only when the sound carrier of the channel B has been received, two &#34;1&#34; level signals are applied to the NAND circuit 35 and the flip-flop circuit 38 is reset so that the receiving frequency is controlled by the output of the buffer circuit 40 and the receiving frequency is stabilized to f PB . Once the receiving frequency is stabilized, the output voltage of the frequency discriminator circuit 9 does not fall below 5 volts. Therefore, the output level of the Schmitt circuit 50 remains at &#34;1&#34; level and the flip-flop circuits 38 and 39 are kept reset. 
     When the channel B is being selected, and the channel selection starting switch 72 is closed and the receiving frequency starts to fall, the receiving frequency continues to fall until the picture carrier is again received, when the receiving frequency is stabilized at that picture carrier frequency.