Abstract:
Power converters typically have unique circuitry for graceful start-up and to develop correct operating voltage biases. Typically this unique circuitry is incorporated into a primary-side “start-up” controller. This start-up controller can also be the primary means of control of the power converter once started. However, a secondary-side controller is typically needed for more exact output voltage regulation, duplicating circuitry already present in the primary-side start-up controller. During light-load or no load conditions, on and off switching of the gate driver is stopped when the secondary-side controller sends a standby code inhibit (disable) command to the start-up controller. When power needs to be sent to the secondary side of the transformer to charge a secondary side capacitor, the secondary-side controller sends an enable code command to the start-up controller where it is detect to allow the start-up controller to operate in a normal fashion with the secondary side controller.

Description:
RELATED PATENT APPLICATION 
       [0001]    This application claims priority to commonly owned U.S. Provisional Patent Application No. 62/169,415; filed Jun. 1, 2015; and is related to U.S. patent application Ser. No. 14/945,729; filed Nov. 19, 2015; and U.S. Provisional Patent Application No. 62/208,123; filed Aug. 21, 2015; all are hereby incorporated by reference herein for all purposes. 
     
    
     TECHNICAL FIELD 
       [0002]    The present disclosure relates to power converters, and, in particular, to reducing power used by the power converter when in a stand-by mode during light-load or no-load conditions. 
       BACKGROUND 
       [0003]    Power converters, in particular switched-mode AC/DC power converters, typically have unique circuitry to reduce power used during light-load and no-load conditions. A power converter having a low power standby mode may be used to efficiently operate the power converter during light-load and no-load conditions. During this low power standby mode a secondary-side controller commands a start-up controller on the primary side of the power converter transformer to inhibit operation of the power switch coupled to the transformer primary. However, the secondary-side controller must use energy stored on the secondary side capacitor to continuously send control signals to the start-up controller for inhibiting operation of the power converter switch during this low power standby mode. 
       SUMMARY 
       [0004]    Therefore a need exists for reducing power used when a power converter is in a low-power standby mode. 
         [0005]    According to an embodiment, a method for reducing standby power in a power converter may comprise the steps of: providing a primary-side start-up controller and a secondary-side controller in a power converter; controlling a power switch coupled to a transformer in the power converter with the start-up controller until a secondary-side voltage from the transformer reaches a desired value then controlling the power switch by sending a pulse width modulation (PWM) signal from the secondary-side controller to the start-up controller; sending a disable signal from the secondary-side controller to the start-up controller to inhibit operation of the power switch and enter into a standby mode; and sending an enable signal from the secondary-side controller to the start-up controller to enable operation of the power switch and return to an operating mode. 
         [0006]    According to a further embodiment of the method, the steps of sending the enable and disable signals may comprise the steps of sending the enable and disable signals over a first isolation circuit, and the step of sending the PWM signal may comprise the step of sending the PWM signal over a second isolation circuit. According to a further embodiment of the method, the steps of sending the enable, disable and PWM signals may comprise the steps of sending the enable, disable and PWM signals over a single isolation circuit. 
         [0007]    According to a further embodiment of the method, the disable signal may comprise a first coded signal and the enable signal may comprise a second coded signal. According to a further embodiment of the method, the steps of decoding the first and second coded signals may comprise the steps of decoding the first and second coded signals in the primary-side start-up controller. According to a further embodiment of the method, the enable and disable signals may be at higher frequencies than the PWM signal frequencies. According to a further embodiment of the method, the enable and disable signals may be at frequencies of at least ten times the PWM signal frequencies. According to a further embodiment of the method, the enable and disable signals may be at frequencies of about 500 kHz plus or minus about 50 kHz, and the PWM signal may be at frequencies from about 20 kHz to about 65 kHz. 
         [0008]    According to a further embodiment of the method, the step of filtering the higher frequency enable and disable signals from the PWM signal may comprise the step of using a high pass filter. According to a further embodiment of the method, the high pass filter may be a digital high pass filter. According to a further embodiment of the method, the high pass filter may be an analog high pass filter. 
         [0009]    According to another embodiment, a power converter having reduced standby power may comprise: a start-up controller coupled to a first DC voltage; a transformer having primary and secondary windings, wherein the transformer primary winding may be coupled to the first DC voltage; a current measurement circuit for measuring current through the primary winding of the transformer and providing the measured primary winding current to the start-up controller; a power switch coupled to the transformer primary and controlled by the start-up controller; a secondary-side rectifier coupled to the transformer secondary winding for providing a second DC voltage; a secondary-side controller coupled to the start-up controller and the secondary-side rectifier; wherein when the start-up controller receives the first DC voltage it starts to control the power switch on and off whereby a current flows through the transformer primary, an AC voltage develops across the transformer secondary winding, the second DC voltage from the secondary side rectifier powers up the secondary-side controller, the secondary-side controller takes over control of the power switch when the second DC voltage reaches a desired voltage level by sending a pulse width modulation (PWM) signal from the secondary-side controller to the start-up controller, the secondary-side controller sends a disable signal to the start-up controller to inhibit operation of the power switch when entering into a standby mode, and the secondary-side controller sends an enable signal to the start-up controller to enable operation of the power switch and return to an operating mode. 
         [0010]    According to a further embodiment, the enable and disable signals may be sent over a first isolation circuit, and the PWM signal may be sent over a second isolation circuit. According to a further embodiment, the enable, disable and PWM signals may be sent over a single isolation circuit. According to a further embodiment, the disable signal may comprise a first coded signal and the enable signal may comprise a second coded signal, and the start-up controller may further comprise decoding circuits for decoding the first and second coded signals. According to a further embodiment, the enable and disable signals may be at higher frequencies than the PWM signal frequencies. According to a further embodiment, the enable and disable signals may be at frequencies of at least ten times the PWM signal frequencies. According to a further embodiment, the enable and disable signals may be at frequencies of about 500 kHz plus or minus about 50 kHz, and the PWM signal may be at frequencies from about 20 kHz to about 65 kHz. 
         [0011]    According to a further embodiment, a high pass filter may be used to filter out the PWM signal before the enable and disable signals may be decoded. According to a further embodiment, the power converter may comprise a flyback power converter. According to a further embodiment, the power converter may be selected from any one of the group consisting of a forward converter, an LLC converter, a half-bridge converter, a full-bridge converter, and a phase-shifted full-bridge converter. 
         [0012]    According to a further embodiment, the power switch may be a power metal oxide semiconductor field effect transistor (MOSFET). According to a further embodiment, the isolation circuit may be an optical coupler. According to a further embodiment, the isolation circuit may be a pulse transformer. According to a further embodiment, the start-up controller may comprise an open-loop current regulator and power switch driver. 
         [0013]    According to a further embodiment, the start-up controller may comprise: a high voltage regulator having an input coupled to the first DC voltage; over-voltage and under-voltage lockout circuits coupled to the high voltage regulator; a shutdown circuit coupled to the over-voltage and under-voltage lockout circuits; a pulse width modulation (PWM) generator; a gate driver for driving the power switch, where the gate driver may be coupled to the shutdown circuit; a PWM signal selection circuit coupled between the PWM generator, the gate driver and an external pulse input; a current protection circuit coupled to the PWM generator; an external command detection circuit adapted to detect a PWM signal on the external pulse input and to switch the gate driver from the PWM generator to the external pulse input; and enable/disable signal detection circuits coupled to an external enable/disable input and the shutdown circuit. 
         [0014]    According to a further embodiment, the start-up controller may comprise: a high voltage regulator having an input coupled to the first DC voltage; over-voltage and under-voltage lockout circuits coupled to the high voltage regulator; a shutdown circuit coupled to the over-voltage and under-voltage lockout circuits; a pulse width modulation (PWM) generator; a gate driver for driving the power switch, where the gate driver may be coupled to the shutdown circuit; a PWM signal selection circuit coupled between the PWM generator, the gate driver and an external pulse input; a current protection circuit coupled to the PWM generator; an external command detection circuit adapted to detect a PWM signal on the external pulse input and to switch the gate driver from the PWM generator to the external pulse input; and enable/disable signal detection circuits coupled to the external pulse input and the shutdown circuit. According to a further embodiment, the start-up controller may be provided by a first microcontroller, and the secondary-side controller may be provided by a second microcontroller. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    A more complete understanding of the present disclosure may be acquired by referring to the following description taken in conjunction with the accompanying drawings wherein: 
           [0016]      FIG. 1  illustrates a schematic block diagram of a power converter that is adapted for reducing standby power draw, according to the teachings of this disclosure; 
           [0017]      FIG. 2  illustrates a schematic block diagram of a power converter that is adapted for reducing standby power draw, according to a specific example embodiment of this disclosure; and 
           [0018]      FIG. 3  illustrates a schematic block diagram of a power converter that is adapted for reducing standby power draw, according to another specific example embodiment of this disclosure. 
       
    
    
       [0019]    While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the particular forms disclosed herein. 
       DETAILED DESCRIPTION 
       [0020]    Power supplies, in particular DC-to-DC and AC-to-DC power converters, typically have unique circuitry to start them up. According to various embodiments of this disclosure, a power converter may comprise a primary-side start-up controller and a secondary-side controller, wherein the start-up controller is utilized to send power to the secondary-side controller when power (voltage) is first applied to the primary side of the power converter. This provides a low cost integrated circuit (IC) solution for start-up of DC-to-DC and AC-to-DC power converters using conventional devices on the primary side that does not duplicate the resources of a secondary-side controller and minimizes discrete components on the primary side. More detailed descriptions of the implementation and operation of power converters, according to the teachings of this disclosure, are provided in commonly owned U.S. patent application Ser. No. 14/945,729; filed Nov. 19, 2015; entitled “Start-Up Controller for a Power Converter,” by Thomas Quigley, and is hereby incorporated by reference herein for all purposes. 
         [0021]    A “burst-mode” may be used to efficiently operate the power converter during light-load and no-load conditions, e.g., when the power converter is in a “standby mode.” According to various embodiments disclosed herein, circuitry may be provided in a start-up controller located on the primary-side of the power converter that latches enabling and disabling of power switch drive via digitally coded commands from a secondary-side controller via an isolation circuit. Therefore power switch drive disabling commands need not be continuously sent from the secondary-side controller to the primary-side start-up controller, thereby saving power used by the power converter when in a standby mode. 
         [0022]    Referring now to the drawings, the details of example embodiments are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix. 
         [0023]    Referring now to  FIG. 1 , depicted is a schematic block diagram of a power converter that is adapted for reducing standby power draw, according to the teachings of this disclosure. A power converter, generally represented by the numeral  100 , may comprise a start-controller  106 , a MOSFET switch  110 , a current sensor  112 , e.g., a resistor; a transformer  122 , a bias voltage rectifier  108 , a power rectifier  124 , a filter capacitor  126 , a secondary-side controller  118 , and isolation circuits  114  and  116 . The power rectifier  124  and filter capacitor  126  may be coupled to an application load  128 . A flyback power converter is shown for explanatory purposes but it is contemplated and within the scope of this disclosure that any configuration of a power converter used in switched mode power supplies, e.g., forward converter, LLC (combination of two inductors and one capacitor) converter, half-bridge converter, full-bridge converter, phase-shifted full-bridge converter and the like, may utilize and benefit from what is disclosed and claimed herein. 
         [0024]    The start-up controller  106  may be a pulse width modulation (PWM) source open-loop, peak current-mode controller operating with a fixed OFF-time and comprise a high voltage (HV) regulator  150 , an internal PWM generator  152 , over-current protection  154 , external command detection  156 , a PWM source selection switch  158 , over-voltage and under-voltage lockout  160 , shutdown circuit  162 , a MOSFET gate driver  164 , and a current sense circuit  166 . 
         [0025]    When an AC line power source  102  is applied to the primary side power rectifier and filters  104  a DC voltage, V_Link, results. This DC voltage, V_Link, is coupled to a primary winding of transformer  122  and the VIN input of the start-up controller  106 . The start-up controller  106  becomes active when the voltage, V_Link, reaches a sufficient voltage for proper operation thereof. Once activated the start-up controller  106  starts pulsing the MOSFET gate driver  164  which turns on and off the MOSFET switch  110  thereby allowing the transformer  122  of the flyback power converter  100  to convert energy to its secondary side and bias voltage windings. The start-up controller  106  is not a primary-side power converter controller that can linearly regulate the output of the flyback power converter  100  via transformer coupling. It does not duplicate the precision reference and voltage error amplifier of the secondary-side controller  118 . 
         [0026]    The start-up controller  106  basically has two modes of operation: In the first mode, during start-up of the flyback power converter  100 , it performs as an open-loop current regulator that drives the MOSFET switch  110  until the secondary-side controller  118  takes control (command) of the PWM signals that drive the MOSFET switch  110 . In the second mode, once the secondary-side controller  118  is fully operational, it starts sending PWM signal commands to the start-up controller  106  through the isolation circuit  116 . Once external PWM signal commands from the secondary-side controller  118  (via isolation circuit  116 ) are received by the start-up controller  106 , its internal gate driver  164  may be coupled to the external PWM signal, whereby the secondary-side controller  118  now controls the MOSFET switch  110 . 
         [0027]    The start-up controller  106  controls the switching of the MOSFET switch  110  in an open-loop manner based upon regulation of the peak current through the MOSFET switch  110 . A voltage is developed across resistor  112  in series with the MOSFET switch  110  and primary of the transformer  122  that is proportional to the peak current therethrough. This voltage is coupled to the C/S (current sense) input of the start-up controller  106  which senses it and adjusts the on time of the MOSFET switch  110  to limit the peak current to a certain design value. An internal high voltage linear regulator  150  in the start-up controller  106 , whose input is the DC voltage, V_Link, regulates a voltage, V DD , usable by the internal circuits of the start-up converter  106 . V DD  is the peak voltage at the Gate node of the start-up controller  106 . Initially, the internal linear regulator supplies V DD  for operation of the start-up controller  106 , but once a DC voltage is provided from a primary-side tertiary winding of the transformer  122  through the power diode  108  this internal linear regulator  150  stops supplying current to the internal circuits of the start-up controller  106 . This allows internal thermal dissipation in the start-up controller  106  to be reduced. 
         [0028]    Driving the MOSFET switch  110  on and off will cause the transformer  122  through rectifier  124  to charge a capacitor  126  to a voltage, V_Out. The secondary-side controller  118  of the power converter  100  is located on the secondary side, and when there is sufficient voltage, V_Out, on the filter capacitor  126 , the secondary side controller  118  becomes active and takes over controlling the gate driver  164  through the isolation circuit  116 , e.g., optical-coupler, pulse transformer, etc. The external command detection  156  senses the PWM pulses from the isolation circuit  116  and will cause the PWM selection switch  158  to switch over from the internal PWM generator  152  to the PWM pulses from the secondary-side controller  118 . 
         [0029]    The transformer  122  also provides bias voltage, V_Bias, via diode  108 . V_Bias may be cross-regulated to the start-up controller  106  by transformer coupling. The winding turns ratio of the transformer  122  is such that V_Bias is higher than the output voltage set point of the internal linear voltage regulator  150  of the start-up controller  106 , thereby effectively shutting off this internal linear voltage regulator  150  and reducing the internal thermal dissipation of thereof. 
         [0030]    When the power converter  100  goes into a low power standby mode, the PWM pulses from the secondary-side controller  118  stop. However when that happens the start-up controller  106  thinks that it is in the start-up mode and will force the switch  158  to reconnect the internal PWM generator  152  to the gate driver  164 . This is not desired when going into a low power standby mode. To prevent the start-up controller  106  from becoming active again to drive the MOSFET switch  110 , the secondary-side controller  118  may assert a hold or standby signal on the PWMD (PWM disable) input to the start-up controller  106  via a second isolation circuit  114  coupled to a digital output from the secondary-side controller  118 . The secondary-side controller  118  holds the PWM disable signal for as long as the low power standby mode is in effect or until a voltage on the filter capacitor drops below a certain value and the secondary-side controller  118  needs for the start-up controller  106  to become active again long enough to recharge the filter capacitor  126 . 
         [0031]    However by requiring the secondary-side controller  118  to actively maintain a PWM disable signal on the PWMD input to the start-up controller  106 , power is consumed and the filter capacitor  126  will discharge faster than necessary during the low power standby mode. Over time the secondary-side controller  118  will have to come out of the low power sleep mode and then re-enable the start-up controller  106  in order to refresh the voltage charge on the filter capacitor  126 , then and only then can the secondary-side controller  118  go back into the low power sleep mode. Therefore what is needed is a way to eliminate the secondary-side controller having to maintain a PWM disable signal to the start-up controller  106 , and thereby stay for a longer period of time in a low power sleep mode. 
         [0032]    Referring now to  FIG. 2 , depicted is a schematic block diagram of a power converter that is adapted for reducing standby power draw, according to a specific example embodiment of this disclosure. A power converter, generally represented by the numeral  200 , works in substantially the same way as the power converter  100  described hereinabove except for the addition of a sleep command detection circuit  270  in the start-up controller  206 , and different shutdown and enable protocols from the secondary-side controller  218 . Now when the secondary-side controller  218  wants to go into a low power sleep mode its Gate output will be held so that there are no PWM pulses sent to the start-up controller  206  and a brief coded shutdown command is sent to the start-up controller  206  via the isolation circuit  114 . Then the secondary-side controller  218  goes into a passive (no signals generated) low power sleep mode that draws minimal current from the filter capacitor  126 . When the secondary-side controller  218  wakes up to either recharge the filter capacitor  126  or start supplying load current again to the application load  128 , it asserts a brief coded enable command via the isolation circuit  114  to the start-up controller  206 , the sleep command detection circuit  270  decodes the enable command, and the start-up controller  206  then resumes normal operation with PWM pulses from the secondary-side controller via the isolation circuit  116 . By latching the start-up controller  206  into a standby sleep mode the secondary-side controller  218  no long has to continuously drive the PWMD input of the start-up controller  206  via the isolation circuit  114 . Thus the secondary-side controller  218  consumes less energy (lower current draw) from the filter capacitor  126 . 
         [0033]    Referring now to  FIG. 3 , depicted is a schematic block diagram of a power converter that is adapted for reducing standby power draw, according to another specific example embodiment of this disclosure. A power converter, generally represented by the numeral  300 , works in substantially the same way as the power converter  200  described hereinabove except that the sleep command detection circuit  270  and the second isolation circuit  114  have been eliminated, and the required integrated circuit package pin count has been reduce from eight (8) pins to seven (7) pins, thus leaving one spare pin available for other purposes. 
         [0034]    The external command detection  356  is now used to detect normal operating PWM pulses, and disable and enable commands from the secondary-side controller  318  via the isolation circuit  116 . The operating PWM pulses, and the disable and enable commands are multiplexed on the signal line from the gate output of the secondary-side controller  318  to the Pulse input of the start-up controller  306 . To multiplex the operating PWM pulses, and the disable and enable commands on the same signal line, different pulse frequencies are used. For example, an allowable PWM pulse stream frequency range may be from about 20 kHz to about 65 kHz. An allowable frequency range for the disable and enable commands may be about 500 kHz plus or minus about 50 kHz. Since the operating PWM pulse stream or the disable and enable commands are mutually exclusive (do not occur at the same time), the external command detection  356  need only differentiate between the frequencies of the pulses it receives, e.g., ignores the lower frequency PWM pulses when detecting the enable/disable signals, and will only react to the high frequency disable and enable commands. For that differentiation a simple high pass or frequency selective filter, either analog or digital (preferably digital), need be employed 
         [0035]    A simple analog high-pass filter can be described as having two components; a capacitor (from input to output) and a resistor (output to ground). The resistance value and the capacitance value determine the ‘break frequency’. The break frequency can be described as the frequency when half the input signal amplitude is present at the output. This is also known as the “3 dB breakpoint”. So, in this application the normal PWM frequency is much lower than the 3 dB breakpoint (output of filter is near zero amplitude signal) and the sleep command “burst frequency” is much higher than the 3 dB breakpoint (output is nearly 100% of the input amplitude). The difference in amplitude allows simple circuitry to easily distinguish the two signal types. A simple digital filter would be a set of shift registers in series. The high frequency “burst” could be at 500 kHz and have a 50% duty cycle. 500 kHz has a period of 2 μs. Say, for instance, the rising edge of the 500 kHz signal sets the first resister from a 0 to a 1 state, and it also triggers a timer of, say, 2.2 μs in duration. If the next rising edge appears before the end of the timer&#39;s 2.2 μs duration, then both the first and second registers of the series are set to “1”. Say there are 5 shift resisters in series. When all 5 are at “1” then the circuitry determines that a valid sleep command has been issued. If at any time the 2.2 μs goes its entire duration without the next rising edge, then the signal is determined not to be a “sleep” command and the detection circuit is reset. 
         [0036]    Now when the secondary-side controller  318  wants to go into a low power sleep mode it will issue a “high frequency burst” disable command to the Pulse input of the start-up controller  306  via the single isolation circuit  116 . The external command detection  356  will detect this high frequency burst disable command and hold the shutdown circuit  162  in a standby sleep condition which inhibits the gate driver  164  from pulsing the MOSFET switch  110  on and off (maintains MOSFET switch  110  off). Then the secondary-side controller  318  goes into a passive (no PWM drive signals generated) low power sleep mode that draws minimal current from the filter capacitor  126 . 
         [0037]    Detection of the “high frequency burst” disable command takes a finite number of cycles before the disable command may be recognized by the external command detection  356 . Therefore, the external MOSFET switch  110  will be gated at the “high frequency burst” frequency that may cause the power converter  300  to a enter into a “continuous conduction mode (CCM)” of operation. The current protection  154  will protect the power converter  300  from a CCM condition, but does not prevent the external command detection  356  from taking sufficient time to recognize the “high frequency burst” disable command. 
         [0038]    The secondary-side controller  318  may “wake” to refresh filter capacitor  126  to then return to “sleep” mode. It can send a single pulse to the Pulse input of the start-up controller  306  via the single isolation circuit  116  which allows the Start-Up Function of the start-up controller  306  to function. Or, the secondary-side controller  318  may send a normal PWM signal to the Pulse input of the start-up controller  306  via the single isolation circuit  116  and control the recharge itself. Either way, once the capacitors are refreshed the secondary-side controller  318  may issue the “high frequency burst” to return to sleep. The secondary-side controller  318  may “wake” to start supplying load current again to the application load  128 . It does this by resuming a normal PWM command to the PULSE input of the start-up controller  306  via the single isolation circuit  116 . If the secondary-side controller  318  allows “sleep” to occur for too long a period then the voltage on the V DD  pin of the start-up controller  306  will eventually decay below the UVLO level set by OVLP/UVLO circuit  160 , which enables the start-up controller  306  to enter a start-up mode. The secondary-side controller  318  monitors the rise of voltage on V_Out to determine that the start-up controller  306  has awaken and is in start-up mode, and then awakens itself to regain control (to either re-enter sleep mode or continue normal operation). In this way there is always a strategy to exit the sleep mode state. 
         [0039]    It is contemplated and within the scope of this disclosure that the control methods described and claimed herein may be used with other configurations of power converters used in switched mode power supplies, e.g., flyback power converter, forward converter, LLC converter, half-bridge converter, full-bridge converter, phase-shifted full-bridge converter and the like.