Abstract:
A low standby power DC-DC converter can be powered down during standby mode. The DC-DC converter can be periodically awakened between sleep cycles to check if the output voltage needs to be recharged (refreshed). The duration of the sleep cycles can be varied to accommodate for changing load conditions that would affect the output voltage.

Description:
BACKGROUND 
       [0001]    Unless otherwise indicated, the foregoing is not admitted to be prior art to the claims recited herein and should not be construed as such. 
         [0002]    Standby power is an important specification in many mobile integrated circuits (ICs), particularly ICs involving large digital circuits such as WLAN/WAN SoCs, and application processors. For example, in a wireless local area network (WLAN), delivery traffic indication maps (DTIMs) inform clients about the presence of buffered multicast/broadcast data on the access point. DTIMs are generated and included in beacons to signal the presence of data at the access point. Accordingly, the power requirements for DTIM communications is an important specification in ICs that support wireless systems, comprising a mix of active power consumption and sleep state power consumption specifications. Lowering sleep state power consumption can reduce DTIM power consumption and thus improve mobile device battery life. 
         [0003]    In general, lowering sleep state power consumption in any power device can improve battery life. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]    With respect to the discussion to follow and in particular to the drawings, it is stressed that the particulars shown represent examples for purposes of illustrative discussion, and are presented in the cause of providing a description of principles and conceptual aspects of the present disclosure. In this regard, no attempt is made to show implementation details beyond what is needed for a fundamental understanding of the present disclosure. The discussion to follow, in conjunction with the drawings, make apparent to those of skill in the art how embodiments in accordance with the present disclosure may be practiced. In the accompanying drawings: 
           [0005]      FIG. 1  is a high level diagram of a power converter with standby capability in accordance with the present disclosure. 
           [0006]      FIG. 1A  is a high level diagram of a power converter with standby capability in accordance with the present disclosure, showing some additional detail. 
           [0007]      FIG. 2  is an illustrative power converter in accordance with the present disclosure. 
           [0008]      FIG. 3  shows sleep mode processing in accordance with the present disclosure. 
           [0009]      FIG. 4  shows sleep mode processing of the illustrative embodiment shown in  FIG. 2 . 
           [0010]      FIG. 5  shows an alternative sleep mode processing of the illustrative embodiment shown in  FIG. 2   
       
    
    
     DETAILED DESCRIPTION 
       [0011]    In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be evident, however, to one skilled in the art that the present disclosure as expressed in the claims may include some or all of the features in these examples, alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein. 
         [0012]    Referring to  FIG. 1 , a power supply  100  in accordance with the present disclosure may include a power converter section  102  for converting an input voltage to produce an output voltage V out . The power converter section  102  may include an input terminal  122  for a connection to a source for V in  (e.g., a battery). The power converter section  102  may include an output terminal  124  for a connection to a load (not shown) to provide the output voltage V out  to the load. A supply voltage V DD  may be used to power the power converter section  102 . In various embodiments, the power converter section  102  may be any type of DC-DC converter, including for example, but not limited to buck regulators, boost regulators, buck-boost regulators, switched capacitor regulators, low dropout (LDO) regulators, etc. 
         [0013]    In accordance with the present disclosure, the power supply  100  may further include a sleep state controller  104 . As will be explained in more detail below, the sleep state controller  104  may generate one or more control signals  126  to place the power converter section  102  in a sleep state (sleep mode). In other words, operation of the power converter section  102  can be selectively enabled or disabled by the sleep state controller  104  by selective assertion and de-assertion of control signals  126 . 
         [0014]    In accordance with the present disclosure, the control signals  126  may selectively enable and/or disable operation of different parts of the power converter section  102 . In some embodiments, the sleep state controller  104  may receive a signal  128  from the power converter section  102  that the sleep state controller can use to selectively enable and/or disable operation of different parts of the power converter section  102 . 
         [0015]    The sleep state controller  104  may manage one or more sleep state values  106  to control the duration of time of the sleep state in the power converter section  102 . In accordance with the present disclosure, the sleep state controller  104  may alter one or more of the sleep state values  106 . This aspect of the present disclosure will be described in more detail below. 
         [0016]      FIG. 1A  illustrates a more detailed embodiment of a power supply  100 ′ in accordance with the present disclosure. The power supply  100 ′ may comprise a voltage modulator  112  to modulate an input voltage V in  at input terminal  122  to produce an output voltage V out  at output terminal  124 . A compensation circuit  114  can provide a feedback path from the output terminal  124 . The compensation circuit  114  can produce a feedback signal  116  that the voltage modulator  112  can use to modulate the input voltage in accordance with a reference voltage V ref . In some embodiments, the feedback signal  116  may serve as the control signal  128  to the sleep state controller  104 . 
         [0017]    Referring to  FIG. 2 , details for an illustrative example of  FIGS. 1 and 1A  will now be described. The example shown in  FIG. 2  represents a switching type converter (regulator) known as a buck (step down) converter  200  configured in accordance with the present disclosure. The circuit shown in  FIG. 2  is merely an example to illustrate aspects of the present disclosure in the context of a particular DC-DC converter circuit. It will be appreciated by one of ordinary skill that other kinds of DC-DC converter circuits can be readily embodied in accordance with the present disclosure. 
         [0018]    Continuing with  FIG. 2 , the voltage modulator section of the buck converter  200  may include an oscillator  202  and a pulse width modulator  204  connected to a driver section comprising drivers D 1  and D 2 . The time base for oscillator  202  can be provided by a clock input. The drivers D 1  and D 2  may drive switching transistors M 1  and M 2  in accordance with a pulse output of the pulse width modulator  204 . As one of ordinary skill will understand, transistor M 2  operates as the diode component of a conventional buck converter, and transistor M 1  provides the switching function. 
         [0019]    The compensation circuit may comprise an error amplifier (e.g., a comparator)  206  that compares the output voltage V out  with a reference voltage V ref  to produce an error signal V error . The error signal V error  may be connected to the pulse width modulator  204  to control the switching of transistors M 1  and M 2 . 
         [0020]    Components comprising the voltage modulator and the compensation circuit may be powered by a voltage source V DD . Conventionally, power consuming circuits such as the oscillator  202 , the pulse width modulator  204 , the drivers D 1 , D 2 , and the error amplifier  206  are always ON. In power limited systems, such as battery operated devices, such continuous operation can quickly drain the power source. Accordingly, providing for adequate sleep mode processing can be an important design consideration. 
         [0021]    In accordance with the present disclosure, the buck converter  200  may further include a sleep control circuit  212 . The sleep control circuit  212  may generate control signals ctl- 1 , ctl- 2  that can selectively enable and disable operation of circuit components comprising the buck converter  200 . In some embodiments, for example, the sleep control circuit  212  may generate a control signal ctl- 1  that can serve to selectively enable and disable operation of the error amplifier  206 . Similarly, the sleep control circuit  212  may generate a control signal ctl- 2  that can serve to selectively enable and disable operation of components of the voltage modulator, such as the oscillator  202 , the pulse width modulator  204 , and the drivers D 1 , D 2 . It will be appreciated that the use of control signals, and their number, is an implementation specific detail. Thus, for example, in some embodiments, there may be more or fewer control signals to accomplish the enable and disable operations. 
         [0022]    The particular manner by which operation of a circuit is disabled and enabled will vary from one circuit to the next. In some embodiments, for example, disabling operation of a circuit may include placing the circuit is a low power consumption mode. In other embodiments, disabling operation of a circuit may include disconnecting power (e.g., V DD ) to the circuit, and so on. 
         [0023]    The sleep control circuit  212  may place the voltage modulator section and the compensation circuit in a sleep state by disabling operation of components comprising the voltage modulator section and the compensation circuit. The sleep control circuit  212  may exit the sleep state by enabling components comprising the voltage modulator section and the compensation circuit. In some embodiments, for example, the sleep control circuit  202  may exit the sleep state in response to the error signal V error  generated by the error amplifier  206 . This aspect of the present disclosure will be discussed in more detail below. 
         [0024]    In accordance with the present disclosure, parameters for the sleep control circuit  202  may be stored in a memory  214 . The parameters may include a sleep duration value that specifies the duration of each sleep cycle during which operation of components comprising the voltage modulator section and the compensation circuit are disabled. In accordance with the present disclosure, the sleep duration value may be adjusted over time. The parameters may include a sleep cycles threshold value that is used to determine when to adjust the sleep duration value. These aspects of the present disclosure will be discussed in more detail below. 
         [0025]    The sleep control circuit  212  may be connected to an external sleep control signal to cause the sleep control circuit to enter and exit the sleep state according to activity in the device that contains the buck converter  200 . The memory  214  may be programmed from an external source with initial values for the parameters. 
         [0026]    Referring now to  FIG. 3 , the discussion will turn to a high level description of operation of sleep control in a power converter (e.g.,  200 ,  FIG. 2 ) by sleep control logic (e.g., sleep control circuit  212 ,  FIG. 2 ) in accordance with the present disclosure. At block  302 , the sleep control logic may initiate a sleep cycle (e.g., in response to a sleep control signal,  FIG. 2 , being asserted), thus putting the power converter in a sleep mode. During the sleep mode, operation of components of the power converter may be disabled, such as the voltage modulator section and the compensation circuit (e.g.,  FIG. 2 ). As a consequence, the voltage level of output voltage V out  will start to drop. 
         [0027]    At block  304 , after a duration of time has passed, the sleep cycle may terminate. In some embodiments, for example, the sleep control logic may use a timing circuit. It will be appreciated that, in general, the passage of time may be measured by any suitable adaptive delay element. 
         [0028]    In block  306 , the sleep control logic may determine whether or not to restore the voltage level of the output voltage V out . In accordance with the present disclosure, the sleep control logic may enable operation of a portion of the power converter (e.g., error amplifier  206 ,  FIG. 2 ) to determine if V out  has fallen below a threshold value (e.g., V error ,  FIG. 2 ). If V out  has fallen below the threshold value, then at block  308  the sleep control logic may enable operation of the power converter to recharge the output voltage V out . 
         [0029]    At block  310 , a determination is made in accordance with the present disclosure whether or not to adjust the duration of the sleep cycle. If the sleep cycle duration should be adjusted, then at block  312 , the duration of the sleep cycle can be adjusted. This aspect of the present disclosure will be discussed in more detail below. 
         [0030]    Returning to block  306 , if the output voltage level has not dropped below the threshold value, then processing may simply proceed to block  314 . If at block  310  the sleep cycle duration does not need to be updated, then processing may simply proceed to block  314 . At block  314 , if the sleep mode is terminated, then processing of sleep cycles completes and the sleep control logic may enable operation of all components of the power converter. Otherwise, processing proceeds to block  302  where another sleep cycle is repeated. 
         [0031]    Termination of sleep mode is likely to occur asynchronously with respect to the flow in  FIG. 3 . In some embodiments, therefore, block  314  may be omitted as a discrete action in the flow in  FIG. 3 . Instead, termination of sleep mode may manifest itself as an interrupt signal to the sleep control logic, which can then respond by enabling operation of all components of the power converter. 
         [0032]    Referring now to  FIGS. 2 and 4 , a description of additional details of sleep control in accordance with an embodiment of the present disclosure will be described with respect to the buck converter  200 . At block  402 , in response to activation of sleep mode, the sleep control circuit  212  may obtain from memory  214  an initial value sleep_period_init for the sleep cycle duration. This initial value can then be used to initialize a sleep_period counter that is maintained in the sleep control circuit  212 . In addition, a sleep_count counter may be initialized to zero. 
         [0033]    At block  404 , the sleep control circuit  212  may initialize a sleep_cycles counter to zero. 
         [0034]    At block  406 , the sleep control circuit  212  may activate a sleep cycle in the buck converter  200 . For example, the sleep control circuit  212  may assert control signals ctl- 1  and ctl- 2  to disable operation of the compensation circuit and components of the voltage modulator. In some embodiments, this will effectively disable operation of the buck converter  200 , leaving only the sleep control logic operational. As a result, the output voltage V out  will begin to drop. In addition, during the sleep cycle, the sleep control circuit  212  may increment the sleep_count counter in a loop until the counter reaches the value of sleep_period. 
         [0035]    At block  408 , the sleep control circuit  212  may increment the sleep_cycles counter to keep track of consecutive sleep cycles. The significance of this counter will become apparent below. The sleep_count counter may be reset to zero. In accordance with the present disclosure, the sleep control circuit  212  may enable only a portion of the buck converter  200 , in block  408 . In particular, the sleep control circuit  212  may enable the error amplifier  206 ; for example, by de-asserting the control signal ctl- 1 . In some embodiments, the control signal ctl- 2  remains asserted, thus keeping the voltage modulator section disabled. 
         [0036]    At block  410 , the now-enabled error amplifier  206  may operate to compare the voltage level of output voltage V out  against the reference voltage V ref  to produce an error signal V error . The sleep control circuit  212  may use V error  (V min =V error ) as a criterion for whether or not to enable operation of the voltage modulator section; e.g., by de-asserting the control signal ctl- 2 . In other embodiments, V min  may be some function of V error . 
         [0037]    If the output voltage V out  does not fall below V min , then the output voltage V out  does not need to be restored (recharged) and processing proceeds to block  406 , where another sleep cycle is repeated. A sleep cycle may therefore be defined by the loop comprising blocks  406 ,  408 , and  410 . 
         [0038]    If, on the other hand, the output voltage V out  does fall below V min , then the output voltage V out  should be restored (recharged) and processing proceeds to block  412 , where the voltage modulator section is enabled; e.g., by de-asserting the control signal ctl- 2 . Operation of the now-enabled voltage modulator section serves to recharge the output voltage V out . 
         [0039]    At block  414 , the sleep_cycles counter may be tested against a target value cycles_target. If the sleep_cycles counter exceeds the target value, then the sleep_period may be increased at block  422 . For example, the sleep_period may be increased by one. If, on the other hand, the sleep_cycles counter does not exceed the target value, then processing proceeds to block  416 . 
         [0040]    At block  416 , the sleep_cycles counter may be tested against the target value cycles_target. If the sleep_cycles counter is less than the target value, then the sleep_period may be decreased at block  424 . For example, the sleep_period may be increased by one. If the sleep_cycles counter does not exceed the target value, then processing proceeds to block  404 . Processing from blocks  422  and  424  may proceed to block  404  where the sleep_cycles counter is reset to zero and sleep mode processing repeats with block  406 . 
         [0041]    An aspect of the present disclosure is illustrated in blocks  408 ,  410 , and  412 . At block  408 , the compensation circuit is enabled while keeping the voltage modulating section is a disabled state. The voltage modulation section is enabled in block  412  if the output voltage falls below and remains disable otherwise. By conditionally enabling the voltage modulation section, power consumption during sleep mode (or standby mode) can be kept to a minimum. 
         [0042]    Another aspect of the present disclosure is illustrated in loop  406 ,  408 ,  410 . The sleep_cycles counter continues to be incremented without being reset so long as the test at block  410  indicates that the output voltage does not need to be recharged. The sleep_cycles counter is reset (via block  404 ) when the output voltage V out  has to be recharged (e.g., at block  412 ). Accordingly, the sleep_cycles counter counts the number of consecutive sleep cycles that are repeated without recharging the output voltage V out . 
         [0043]    When the sleep_cycles counter is too high (e.g., as determined by block  414 ), this suggests that the error amplifier  206  is being enabled (e.g., at block  408 ) too often without having to recharge V out , thus consuming power unnecessarily. In other words, V out  is being tested too frequently. Accordingly blocks  414  and  416  serve adjust the sleep_period so that the sleep control circuit  212  stays in block  406  for a longer period of time, thus reducing how frequently V out  is tested. In some embodiments, the sleep_period value may be adjusted by one on each adjustment. However, in other embodiments, the amount of adjustment may be made according to algorithms that vary the amount of adjustment. Being able to dynamically vary the sleep_period in this way allows for different load conditions in different applications, and for changing load conditions in a given application. 
         [0044]    In some embodiments, the cycles_target value used in blocks  414  and  416  may be the same value. In other embodiments, the cycles_target value used in blocks  414  and  416  may be different values. 
         [0045]    Referring now to  FIGS. 2 and 5 , an alternative process for sleep control in accordance with an embodiment of the present disclosure will be described with respect to the buck converter  200 . At block  502 , in response to activation of sleep mode, the sleep control circuit  212  may obtain from memory  214  an initial value for the sleep cycle duration, sleep_period_in it. This initial value can then be used to initialize a sleep_period counter that is maintained in the sleep control circuit  212 . In addition, the sleep_count counter may be initialized to zero. 
         [0046]    At block  504 , the sleep control circuit  212  may activate a sleep cycle in the buck converter  200 . For example, the sleep control circuit  212  may assert control signals ctl- 1  and ctl- 2  to disable operation of the compensation circuit and components of the voltage modulator. In some embodiments, this will effectively disable operation of the buck converter  200 , leaving only the sleep control logic operational. As a result, the output voltage V out  will begin to drop. In addition, during the sleep cycle, the sleep control circuit  212  may increment the sleep_count counter in a loop until the counter reaches the value of sleep_period. 
         [0047]    At block  506 , the sleep control circuit  212  may enable only a portion of the buck converter  200 . In particular, the sleep control circuit  212  may enable the error amplifier  206 ; for example, by de-asserting the control signal ctl- 1 . In some embodiments, the control signal ctl- 2  remains asserted, thus keeping the voltage modulator section disabled. 
         [0048]    At block  508 , the output voltage V out  may be tested as described above in connection with block  410 . If the output voltage V out  does not fall below V min , then the output voltage V out  does not need to be restored (recharged) and processing proceeds to block  510 , where the sleep_period is unconditionally incremented by some amount. Processing may then proceed to block  504  to repeat another sleep cycle. 
         [0049]    If, on the other hand, the output voltage V out  does fall below V min , then the output voltage V out  should be restored (recharged) and processing proceeds to block  512 , where the voltage modulator section is enabled; e.g., by de-asserting the control signal ctl- 2 . Operation of the now-enabled voltage modulator section serves to recharge the output voltage V out . 
         [0050]    At block  514 , the sleep_period is unconditionally decremented by some amount. Processing may then proceeds to block  504  to repeat another sleep cycle. 
         [0051]    In various embodiments, the sleep control circuit  212  may comprise any suitable circuitry that can operate according to the processing described above. In some embodiments, for example, the sleep control circuit  212  may comprise digital logic circuits configured to operate as a state machine. In other embodiments, the sleep control circuit  212  may comprise a digital signal processor (DSP), and so on. 
       Advantages and Technical Effect 
       [0052]    In some embodiments, we can disable most if not all analog functionality in a DC-DC converter during sleep (standby) mode while the load is less than maximum operational; e.g., retention mode in a memory. This can allow for standby-mode converter current to be very low. In some embodiments, for example, the standby current can be &lt;&lt;1 μA in a DC-DC converter according to the present disclosure. By comparison, standby current in conventional converters can be as high as 15-50 μA. 
         [0053]    In some embodiments, only a digital finite state machine and a low power delay (or other suitable timing element) are needed for standby mode operation in accordance with the present disclosure. 
         [0054]    The above description illustrates various embodiments of the present disclosure along with examples of how aspects of the particular embodiments may be implemented. The above examples should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the particular embodiments as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents may be employed without departing from the scope of the present disclosure as defined by the claims.