Abstract:
A high-speed circuit that performs unsigned mode, two&#39;s complement mode, and mixed mode multiplication-accumulation with equal facility. The invention incorporates a high degree of regularity and interconnectivity. Speed is accomplished through interconnectivity, use of high speed adder elements, and a multiple-row addition technique.

Description:
BACKGROUND OF THE INVENTION 
     1. FIELD OF THE INVENTION 
     This invention generally relates to high-volume high-speed digital parallel processing, in particular a multiplier-accumulator integrated circuit array that will accept input operands in two&#39;s complement, unsigned magnitude, and mixed modes. 
     2. DESCRIPTION OF THE RELATED ART 
     A multiplier-accumulator is a computational device that multiplies two multiplier input terms and sums the product with an accumulator term, providing a final output term. A parallel multiplier has the characteristic of operating on multiple bits within the terms simultaneously, that is, in parallel. High speed parallel multipliers and multiplier-accumulators and their efficient integration into silicon or some other semiconductor substrate have been of interest since the early days of digital computers. 
     Many arithmetic circuits which are widely used in the digital arts are designed for use with two&#39;s complement binary signals. While such signals and the associated circuits are particularly well adapted for performing efficiently under many circumstances, two&#39;s complement multiplication often requires the use of specialized circuits for correcting errors or characteristically incomplete results. Attempts have been made to reduce specialized circuitry in two&#39;s complement arithmetic circuits. See, for example, U.S. Pat. No. 3,866,030 by inventors Baugh and Wooley for a two&#39;s complement parallel array multiplier. 
     A multiplier-accumulator that can operate equally well across unsigned mode, two&#39;s complement mode, and mixed modes is desirable. 
     It is therefore an object of the present invention to provide a multiplier-accumulator that accepts operand formats in all three of the aforementioned modes. 
     Although a multiplier-accumulator has speed advantages when compared to equivalent circuits, more speed is always desirable. 
     The present invention therefore has the object of high speed operation. 
     It has been recognized for some time that a regular circuit structure is advantageous when implementing it in silicon, as circuit regularity permits a faster layout time (either by hand or by a layout generator). Local interconnection between elements of an integrated circuit, which works well when the circuit is regular, minimizes parasitic capacitance and resistance to provide faster circuit operation. 
     It is therefore a further object of the present invention to provide multiple-mode multiplier-accumulator which has a high degree of circuit regularity and exploits local interconnection. 
     SUMMARY OF THE INVENTION 
     The invention is a circuit that can perform multiple-mode multiplication-accumulation. The circuit operates with equal facility on unsigned mode, two&#39;s complement mode, or mixed mode inputs. 
     By deriving special compensation expressions for terms having negative weight for each multiplication mode (two&#39;s complement, unsigned magnitude, and mixed modes), and by grouping these compensations in a particular manner, it is possible to eliminate the need for the generation of negative partial products. Further making these compensations conformal across the three multiplication modes, specialized circuitry is minimized and circuit regularity is maximized. Similar adder elements are arrayed, with all specialized circuitry being implemented as circuit modifications on some of these elements, thus improving circuit regularity and interconnectivity. 
     Fast adder elements are included to improve overall speed of the invention. Speed is further increased with the use of multiple-row addition techniques. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1a-1c depict multiplier input operands X and Y and accumulator input Z in binary form. For example, in FIG. 1a, m=8 for an 8-bit word, and each a is a bit in that word. 
     FIGS. 2a-2c show expressions that yield magnitudes of two&#39;s complement terms X tc , Y tc , and Z tc . 
     FIGS. 2d-2f show expressions that yield magnitudes of unsigned magnitude terms X uns , Y uns , and Z uns . 
     FIGS. 3a-3d are expressions for the products P tc  =X tc  ·Y tc , P uns  =X uns  ·Y uns , P A  =X tc  ·Y uns , and P B  =X uns  ·Y tc , respectively. 
     FIGS. 4a-4e, 5a-5f, 6a-6f, and 7a-7e illustrate two-row compensation derivations for L, N, O, and Z, respectively. 
     FIGS. 8a-8c, 9a-9c, 10a-10c, and 11a-11c illustrate multiplication-accumulation in unsigned mode, two&#39;s complement mode, and mixed modes A and B. &#34;a&#34; figures show a standard representation. &#34;b&#34; figures show the representation condensed and slightly rearranged. &#34;c&#34;, figures show an array configuration that will perform the multiplication-accumulation. 
     FIG. 12a is block diagram of the preferred multiplier-accumulator. FIG. 12b is a schematic of the array portion. 
     FIGS. 13a-13b, 14a-14b, 15a-15b, 16a-16b, 17a-17b, 18a-18b, 19a-19b, 20a-20b, 21a-21b and 22a-22b detail preferred adder elements and their operation. &#34;a&#34; figures are schematics of the elements. &#34;b&#34; figures are logical symbols, which are used in FIG. 12, for example. 
     FIG. 23 details a preferred exclusive-OR gate. 
     FIG. 24 details generation of control signals TCA, TCB, TCC, and MXM. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The design of the preferred embodiment of the invention follows certain algorithms, so this description will begin with their derivations. When the algorithms are understood, the design and use of the preferred embodiment are easier to comprehend. 
     1. Derivations 
     The inventive multiplier-accumulator has two multiplier input operands X and Y (also called product terms) and one accumulator term Z, expressed in FIGS. 1a-1c as binary power expansions. The two possible accumulator input modes are two&#39;s complement and unsigned magnitude. In this disclosure, subscript &#34;tc&#34; indicates two&#39;s complement mode, and subscript &#34;uns&#34; indicates unsigned magnitude mode. For example, X tc  indicates X interpreted as a two&#39;s complement number. Further, in this disclosure, a term may be represented as a vector. For example, X (shown as a binary power expansion in FIG. 1) may also be represented as the vector (a m-1 , a m=2 , . . . , a 0 ), Y as (b n-1 , b n-2 , . . . , b 0 ), and Z as (c m+n-1 , c m+n-2 , . . . , c 0 ). Multiplication is indicated by the symbol &#34;·&#34; and addition is indicated by the symbol &#34;+&#34;. Logic operations are indicated in capitals, such as in the expression &#34;a AND b&#34;, for example. 
     FIG. 2a is a two&#39;s complement expression of X: when X is to be interpreted as X tc , the expression in FIG. 2a will yield the magnitude of X tc . FIGS. 2b-2c show corresponding expressions for Y tc  and Z tc . FIGS. 2d-2f show similar expressions for X uns , Y uns , and Z uns . 
     Since each of the input operands X and Y can be in two&#39;s complement mode or unsigned magnitude mode, there are four possible multiplication modes for the operation P=X·Y. These are two&#39;s complement mode (P tc  =X tc  ·Y tc ), unsigned magnitude mode (P uns  =X uns  ·Y uns ), mixed mode A (P A  =X tc  ·Y uns ), and mixed mode B (P B  =X uns  ·Y tc ) FIGS. 3a-3d, respectively, show expressions for each of these multiplication modes, based on FIGS. 2a-2f. 
     Note in FIGS. 3a-3d that each product includes different sign combinations of expressions L, M, N, and O. That is, P tc  =+L+M-N-O, P uns  =+L+M+N+O, P A  =-L+M+N-O, and P B  =-L+M-N+O. This is a significant observation and has bearing on the design of the preferred embodiment. 
     It is well known that binary addition of a two&#39;s complement form word is equivalent to its unsigned binary subtraction. Addition is more straightforward and more readily implemented than subtraction. To obtain a two&#39;s complement form, a word is inverted and a 1 is added to it. In the above-listed multiplication modes, terms L, N, and O are subtracted. In the preferred embodiment, &#34;two-row compensations&#34; are derived to aid in these subtractions. The two-row compensation L 2RC , for example, is a pair of rows of bits that when summed with an operand, gives a final accumulation that is as if L was subtracted. The two-row compensation contains two&#39;s complement arithmetic in a form that allows efficient design of the inventive multiplier-accumulator. 
     FIG. 4a shows the expression for term L, written the same as in FIG. 3a, for example. L may also be expressed as a summation of the two rows in FIG. 4b. FIG. 4c shows L inverted and a 1 added to obtain a two&#39;s complement inversion, rewritten in FIG. 4d. FIG. 4e shows L in a two&#39;s complement binary matrix form. FIG. 4e is the two-row compensation L 2RC . 
     Two-row compensation N 2RC  is generated as shown in FIGS. 5a-5f. FIG. 5a expresses term N, the same as in FIG. 3b, for example. N may also be expressed as shown in FIG. 5b. Note that b n-1  is a binary constant, a 1 or 0. If b n-1  =1, then N reduces to FIG. 5c. If b n-l  =0, then N and its two&#39;s complement are both zero. For b n-1  =1, the two&#39;s complement of N is shown in FIG. 5d. Using this information, a generalized expression for the two&#39;s complement of N can be created, shown in FIG. 5e. The expression of FIG. 5e is then converted to N 2RC , shown in FIG. 5f. 
     Term O (FIG. 6a) is similar to N. The derivation of O 2RC , shown in FIG. 6f, is therefore derived using a similar technique. 
     Since the invention accumulates as well as multiplies, two-row compensation Z 2RC  for accumulator term Z must also be derived, since Z may be positive or negative in any multiplication-accumulation mode involving two&#39;s complement. This is shown in FIGS. 7a-7e. Note that when c m+n-1  =1, Z&lt;0, and when c m+n-1  =0, Z&gt;0. 
     With reference to FIGS. 8-11, the four multiply-accumulate modes are now detailed for 8-bit X and Y terms (m=8, n=8). In each figure, a somewhat standard representation of the operation is shown, and then an equivalent, preferred arrangement. Since M remains the same across all cases four modes are readily embodied in a single circuit. 
     FIG. 8a illustrates an unsigned mode multiplication-accumulation, that is, X uns  ·Y uns  +Z uns . Elements of L, M, N and O are shown in their proper columns for addition. FIG. 8b shows the same algorithm, but with 0 moved over the upper left edge of M. FIG. 8c shows this operation in an array configuration. The correct result is obtained if addition is diagonally performed. 
     FIG. 9a illustrates a two&#39;s complement mode multiplication-accumulation, that is, X tc  ·Y tc  +Z tc . Recall from FIG. 3a that N and O are subtracted in this mode. Instead of subtracting N and O in the preferred embodiment, two-row compensations N 2RC  and O 2RC  are summed. Because Z may be positive or negative in this mode, Z 2RC  is also summed. FIG. 9b shows the same derivation, but with all ones in the two-row compensations pre-summed and all but two elements of O 2RC  moved over the upper left edge of M. For the specific case of a multiply-only algorithm (no accumulation), the inventive method reduces to the familiar Baugh-Wooley two&#39;s complement multiplier method. FIG. 9c shows the operation in an array configuration. The correct result is obtained if addition is performed diagonally. 
     Mixed mode A (X tc  ·Y uns  +Z tc ) is illustrated in FIG. 10a. As shown in FIG. 3c, L and O are subtracted in this mode. Therefore L 2RC  and O 2RC  are added. Z 2RC  is also added because Z may be positive or negative in this mode. FIG. 10b shows the corresponding preferred arrangement. As in two&#39;s complement mode in FIG. 9b, all ones in the two-row compensations are pre-summed. As above, FIG. 10c shows an array configuration. 
     Finally, FIG. 11a illustrates mixed mode B (X uns  ·Y tc  +Z tc ). As shown in FIG. 3d, L and N are subtracted in this mode. Therefore L 2RC  and N 2RC  are added. Z 2RC  is also added because Z may be positive or negative in this mode. FIG. 11c shows a corresponding array configuration. 
     2. Embodiment 
     The preferred embodiment of the invention includes an n by m multiplier array having multiple-function adder elements to perform the above-derived algorithms as represented in the array configurations of FIGS. 8c, 9c, 10c, and 11c. For the sake of illustration, an 8 by 8 multiplier-accumulator according to the invention is shown in FIGS. 12a and 12b. The preferred embodiment merges the four multiplication-accumulation modes into a single arrayed set 10 of adder elements 100-107, 110-117, 120-127, 130-137, 140-147, 150-157, 160-169, 170-179, and 180-188, detailed in FIGS. 13 through 23, of which the &#34;A&#34; figures show a schematic, and the &#34;B&#34; figures show a corresponding logical symbol used in FIG. 12b. It is noted that some of the signals shown in the logical symbols are to interpreted differentially, and some nondifferentially. For example, SIN in FIG. 14b is differential (representing true SIN and complement SIN*, shown in FIG. 14a), while input a i  is not. 
     The elements will now be described. The following chart is provided for cross-reference: 
     
         ______________________________________AdderType     Figure    Elements______________________________________FA1S     13        110, 120, 130, 140, 150, 160,              170, 172-177, 180-187FA1A     14        111-116, 121-126, 131-136, 141-146              151-156, 178FA2A     15        100-106, 171FAC      16        161-166FACA     17        107, 117, 127, 137, 147, 157FACC     18        167FAAC     19        168FAAC3    20        169HAC      21        179HAC2     22        188______________________________________ 
    
     FAlS (FIG. 13) is a 3-bit fully differential full-adder cell, with propagation times of 2 gate delays from sum-in to sum-out and 1 gate delay from carry-in to carry-out, when the preferred EXOR circuit of FIG. 23 is used. PG,12 
     FA1A (FIG. 14) performs: 
     
         (a.sub.i ·b.sub.j)+SIN+CIN. 
    
     FA2A (FIG. 15) performs: 
     
         (a.sub.j+1 ·b.sub.0)+(a.sub.j ·b.sub.1)+CIN. 
    
     FAC (FIG. 16) performs: 
     
         ((A.sub.m-j ·b.sub.n-1 AND TCB) OR (a.sub.m-j ·b.sub.n-1 AND TCB*))+SIN+CIN, where TCB* is the inverse of TCB. 
    
     FACA (FIG. 17) performs: 
     
         ((a.sub.m-1 ·B.sub.n-j AND TCA) OR (a.sub.m-1 ·b.sub.n-j AND TCA*))+a.sub.m-2 ·b.sub.n-j+1 +CIN. 
    
     FACC (FIG. 18) performs: 
     
         ((a.sub.m-1 ·B.sub.n-2 AND TCA) OR (a.sub.m-1 ·b.sub.n-2 AND TCA*))+((A.sub.m-2 ·b.sub.n-1 AND TCB) OR (a.sub.m-2 ·b.sub.n-1 AND TCB*))+CIN. 
    
     FAAC (FIG. 19) performs: 
     
         ((a.sub.m-1 ·b.sub.n-1 AND MXM) OR (NOT(a.sub.m-1 ·b.sub.n-1) AND MXM*))+a.sub.m-1 ·TCA+b.sub.n-1 ·TCB. 
    
     Note here that A·B+l is logically equivalent to NOT(A·B). 
     FAAC3 (FIG. 20) performs: 
     
         ((c.sub.m+n-1 AND TCC) OR (C.sub.m+n-1 AND TCC*)+A.sub.m-1 ·TCA+B.sub.n-1 ·TCB. 
    
     HAC (FIG. 21) performs: 
     
         TCC+SIN. 
    
     HAC2 (FIG. 22) performs: 
     
         A+B. 
    
     FAC, FACA, FACC, FAAC, FAAC3 are all adder elements that perform more than one type of addition, and are controlled by signals TCA, TCB, TCC, and MXM. The generation of TCA, TCB, TCC, and MXM is detailed in FIG. 24 and in the chart below. 
     
         ______________________________________Mode           TCA    TCB      TCC  MXM______________________________________Unsigned       0      0        0    0Mixed Mode B   0      1        0    1Mixed Mode A   1      0        0    1Two&#39;s Complement          1      1        1    0______________________________________ 
    
     The above elements when connected as shown in FIG. 12 perform together as a universal multiplier-accumulator, capable of multiplying in unsigned mode, two&#39;s complement mode, and mixed modes A and B. 
     FIG. 12b further shows the preferred embodiment having multiple data input bits V SS  (logical 0), V DD  (logical 1), a 0  -a 7 , b 0  -b 7 , and carry in bits c 0  -c 15 . Output bits include carry-out bits co 0  -co 15  and sum bits s 0  -s 16 . MXM, TCA, TCB, and TCC are control inputs, and NC denotes a no-connect. SUM-out and carry-out bits s 0  -s 16  and co 0  -co 15  are summed in final adder 11 of FIG. 12a. 
     Simplicity and interconnectivity are improved by designing similarity across all elements. For example, each full-adder shares the same basic primitive cell (FAIS) with compensation logic included as required. Some adder elements must be able to perform more than one function. It is primarily for this reason that several adder types are used in the preferred embodiment. 
     For example, element 168 of FIG. 12b multiply-accumulates a 7  ·b 7  in unsigned mode, a 7  ·b 7  +a 7  +b 7  in two&#39;s complement mode, A 7  ·B 7  +a 7  in mixed mode A, and A 7  ·B 7  +b 7  in mixed mode B (compare FIGS. 8c, 9c, 10c, and 11c, respectively). 
     The partial products within term M for all multiplication modes are performed within elements 100-106, 200-206, 300-306, 400-406, 500-506, 600-606, and 700-706. For example, the partial product a 0  ·b 0  is implemented by FA2A element 100 when connected as shown in FIG. 12b. 
     Term O of FIG. 8a is shown in FIG. 8b at the upper left side of M. These terms are implemented by elements 107, 117, 127, 137, 147, 157, and 167. For example, term a 7  ·b 0  in FIG. 8b is implemented by element 107 when connected as shown. 
     Term N of FIGS. 8a and 8b is implemented by elements 160-166. For example, term a 0  ·b 7  is implemented by element 160 when connected as shown. 
     These terms in other modes are similarly accomplished by the preferred embodiment. 
     Elements 108 and 171 are now further elucidated. Term a m-1  is added in the column of c m-1  in two&#39;s complement mode and mixed mode A. Term b n-1  is added in the column of c n-1  in two&#39;s complement mode and mixed mode B. In the preferred embodiment, m=n=8, so a7 and/or b7 are added in the column of c7 in all but unsigned mode. The addition of term a 7  is accomplished by element 108. Note that 108 outputs a differential signal. The addition of term b 7  is accomplished by element 171. This arrangement allows proper addition of a m-1  and b n-1  even if m≠n. 
     Final addition of the sumout and carryout terms of the preferred array 10 is performed by final adder 11, shown in FIG. 12a, which comprises any of several possible adder configurations, including, for example, full carry lookahead, carry select, and conditional-sum type adders. 
     The preferred embodiment is fast when fast adders (such as the preferred) are used. Speed is further improved in the preferred embodiment in FIG. 12 by summing all even rows together, summing all odd rows together, and adding the even sum with the odd sum in final adder 11 (a Wallace tree technique). It is noted that three or more groups of rows can similarly be summed, but the apparent speed improvement thus gained is lost due to increased parasitic capacitances in the longer interconnections. A path limit of 22 mils or less is deemed desirable to limit parasitics and optimize speed. Short interconnections therefore makes Wallace tree summation of two groups of rows preferable. 
     Many variations may be made to the embodiment without making it a different invention. Different adder element designs may be used, as well as alternate EXOR designs. Although the preferred embodiment is integrated into a semiconductor substrate using CMOS techniques, other fabrication technologies might be used. The circuit may be constructed discretely and still embody the same invention.