Abstract:
An adaptive pulse positioning system for a voltage converter providing an output voltage, the system including a PWM generation circuit, a sensor, and a pulse positioning circuit. The PWM generation circuit generates a PWM signal with PWM pulses for controlling the output voltage of the voltage controller. The sensor senses an output load condition of the voltage converter and provides a load signal indicative thereof. The pulse positioning circuit adaptively positions the PWM pulses based on the load signal. A method of adaptively positioning PWM pulses that are used to control an output voltage of a voltage regulator including generating a series of PWM pulses based on a clock signal, sensing an output load condition, and adaptively shifting the series of PWM pulses based on the output load condition.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     The present application claims the benefit of U.S. Provisional Application No. 60/737,523 filed on Nov. 16, 2005, and also claims benefit of U.S. Provisional Application No. 60/774,459 filed on Feb. 17, 2006, in which both are herein incorporated by reference for all intents and purposes. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to power regulators, and more particularly to adaptive PWM pulse positioning for fast transient response by reducing the blank period between cycles.  
         [0004]     2. Description of the Related Art  
         [0005]     The load current of modern circuits including the modern central processing unit (CPU) is highly dynamic and changes very quickly from low to high and from high to low. A CPU current transient may occur within 1 microsecond (μs), for example, which is less than the typical switching period of conventional voltage regulators. It is desired to provide a DC-DC power regulator with a control loop that has sufficient response time to fast load transitions whenever they occur.  
         [0006]     In many conventional pulse-width modulation (PWM) schemes, the compensation output of an error amplifier is typically compared to a fixed ramp signal by a PWM comparator. The PWM comparator generates a PWM signal used to control switching of a DC-DC power regulator. To provide switching noise immunity, a reset-set (R-S) flip-flop is often coupled to the output of the comparator to ensure that there is only one pulse for each switching cycle. In a leading-edge modulation scheme, each PWM pulse is initiated based on the comparator output and terminated synchronous with a clock signal. The leading-edge modulation scheme is good for the load-adding transient event but not always responsive to a load-releasing transient. In a trailing-edge modulation scheme, each PWM pulse is initiated synchronous with a clock signal and terminated based on the comparator output. The trailing-edge modulation scheme is good for the load-releasing transient event but not always responsive to a load-adding transient event. In a conventional dual-edge modulation scheme, the ramp is a triangular waveform so that each PWM pulse begins and ends based on a comparison of the triangular waveform with the compensation signal. The conventional dual-edge modulation scheme, however, also exhibits turn-on or turn-off delays since the ramp is fixed and since the leading-edge of the PWM pulse occurs only in the first half cycle while the trailing-edge only occurs in the second half cycle. Each of these conventional schemes, therefore, insert clock signal delays under certain load varying situations.  
       SUMMARY OF THE INVENTION  
       [0007]     An adaptive pulse positioning system for a voltage converter providing an output voltage according to an embodiment of the present invention includes a pulse width modulation (PWM) generation circuit, a sensor, and a pulse positioning circuit. The PWM generation circuit generates a PWM signal with PWM pulses for controlling the output voltage of the voltage controller. The sensor senses an output load condition of the voltage converter and provides a load signal indicative thereof. The pulse positioning circuit adaptively positions the PWM pulses based on the load signal.  
         [0008]     In one embodiment, the pulse positioning circuit includes a delay function having a first input receiving the load signal, a second input receiving a first clock signal, and an output providing a delayed clock signal having a delay based on the load signal. In this case, the PWM generation circuit controls timing of the PWM pulses based on the delayed clock signal. In more specific embodiments, the PWM generation circuit may include an error amplifier, a signal generator, a comparator, and PWM logic. The error amplifier provides a compensation signal indicative of error of the output voltage of the voltage controller. The signal generator has an input which receives the delayed clock signal and an output which provides a ramp signal. The comparator compares the compensation signal with the ramp signal and generates a PWM control signal indicative thereof. The PWM logic has a first input receiving the delayed clock signal, a second input receiving the PWM control signal and an output providing the PWM signal. Various modulator configurations are contemplated, including trailing edge modulators, dual edge modulators, etc.  
         [0009]     In another embodiment, a dual-ramp dual-edge PWM modulation circuit is contemplated. In this case, the PWM generation circuit includes first and second ramp generators, an error amplifier, first and second comparators, and pulse control logic. The first ramp generator provides a leading-edge ramp signal synchronous with a clock signal. The error amplifier provides a compensation signal indicative of error of the output voltage of the voltage controller. The first comparator compares the leading-edge ramp signal with the compensation signal and asserts a set signal indicative thereof. The second ramp generator provides a trailing-edge ramp signal that begins ramping when the set signal is asserted. The second comparator compares the trailing-edge ramp signal with the compensation signal and asserts a reset signal indicative thereof. The pulse control logic asserts the PWM signal when the set signal is asserted and de-asserts the PWM signal when the reset signal is asserted.  
         [0010]     For the dual-ramp dual-edge embodiments, several configurations are contemplated for the pulse positioning circuit. In a first embodiment, the pulse positioning circuit has a first input receiving the compensation signal, a second input receiving the load signal and an output providing a second compensation signal. The second compensation signal is provided to the first comparator rather than the compensation signal. In this case, the pulse positioning circuit adaptively adjusts the second compensation signal based on the load signal. In another embodiment, the pulse positioning circuit has a first input receiving the leading-edge ramp signal, a second input receiving the load signal and an output providing a second leading-edge ramp signal. The second leading-edge ramp signal is provided to the first comparator rather than the first. In this case, the pulse positioning circuit adaptively adjusts the second leading-edge ramp signal based on the load signal. In yet another embodiment, the pulse positioning circuit adjusts a slew rate of the leading-edge ramp signal based on the load signal. In a more specific slew-rate adjustment embodiment, the first ramp circuit includes a capacitor, a switch circuit which charges the capacitor to a maximum voltage level synchronous with a clock signal, and a controlled current sink which discharges the capacitor at a slew rate based on a current control signal. The pulse positioning circuit adjusts the current control signal based on the load signal.  
         [0011]     A method of adaptively positioning PWM pulses that are used to control an output voltage of a voltage regulator according to an embodiment of the present invention includes generating a series of PWM pulses based on a clock signal, sensing an output load condition, and adaptively shifting the series of PWM pulses based on the output load condition.  
         [0012]     The method may include sensing output load current. The method may include delaying a first clock signal to provide a delayed clock signal, generating a ramp signal based on the delayed clock signal, generating a compensation signal based on an error of the output voltage of the voltage regulator, comparing the ramp signal and the compensation signal and providing a control signal indicative thereof, asserting each PWM pulse based on the delayed clock signal and the control signal, and adaptively adjusting an amount of delay between the first clock signal and the delayed clock signal.  
         [0013]     The method may include initiating the ramp signal with each pulse of the delayed clock signal, initiating each PWM pulse with a corresponding pulse of the delayed clock signal, and terminating each PWM pulse based on the control signal. The method may include generating a triangular waveform based on the delayed clock signal, asserting the control signal to a first level when the compensation signal is greater than the triangular waveform, asserting the control signal to a second level when the compensation signal is less than the triangular waveform, and transitioning each PWM pulse based on the control signal.  
         [0014]     The method may include providing a leading-edge ramp signal synchronous with the clock signal, generating a first compensation signal based on an error of the output voltage of the voltage regulator, comparing the leading-edge ramp signal with a second compensation signal and providing a set signal indicative thereof, initiating a trailing-edge ramp signal when the set signal is provided, comparing the trailing-edge ramp signal with the first compensation signal and providing a reset signal indicative thereof, initiating each PWM pulse when the set signal is provided, terminating each PWM pulse when the reset signal is provided, generating an offset based on the output load condition, and adding the offset to the first compensation signal to provide the second compensation signal.  
         [0015]     The method may include providing a first leading-edge ramp signal synchronous with the clock signal, generating a compensation signal based on an error of the output voltage of the voltage regulator, comparing a second leading-edge ramp signal with the compensation signal and providing a set signal indicative thereof, initiating a trailing-edge ramp signal when the set signal is provided, comparing the trailing-edge ramp signal with the compensation signal and providing a reset signal indicative thereof, initiating each PWM pulse when the set signal is provided, terminating each PWM pulse when the reset signal is provided, generating an offset based on the output load condition, and adding the offset to the first leading-edge ramp signal to provide the second leading-edge ramp signal.  
         [0016]     The method may include providing a leading-edge ramp signal synchronous with the clock signal, generating a compensation signal based on an error of the output voltage of the voltage regulator, comparing the leading-edge ramp signal with the compensation signal and providing a set signal indicative thereof, initiating a trailing-edge ramp signal when the set signal is provided, comparing the trailing-edge ramp signal with the compensation signal and providing a reset signal indicative thereof, initiating each PWM pulse when the set signal is provided, terminating each PWM pulse when the reset signal is provided, and adjusting a slew rate of the leading-edge ramp signal based on the output load condition. In this slew-adjust case, the method may further include charging a capacitor to a predetermined level synchronous with the clock signal and discharging the capacitor at a rate based on the output load condition. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]     The benefits, features, and advantages of the present invention will become better understood with regard to the following description, and accompanying drawings where:  
         [0018]      FIG. 1  is a timing diagram illustrating an operation mode of an adaptive PWM pulse positioning scheme according to an embodiment of the present invention;  
         [0019]      FIG. 2  is a simplified block diagram of a trailing edge modulator circuit implemented according to an embodiment of the present invention;  
         [0020]      FIG. 3  is a timing diagram illustrating operation of the trailing edge modulator circuit of  FIG. 2 ;  
         [0021]      FIG. 4  is a simplified block diagram of a dual edge modulator circuit implemented according to an embodiment of the present invention;  
         [0022]      FIG. 5  is a timing diagram illustrating operation of the dual edge modulator circuit of  FIG. 4 ;  
         [0023]      FIG. 6  is a schematic diagram of a dual-ramp dual-edge PWM modulation circuit according to an embodiment described in a previously filed patent application;  
         [0024]      FIG. 7  is a timing diagram illustrating operation of the dual-ramp dual-edge PWM modulation circuit of  FIG. 6  illustrating the long blank period issue in the dual-ramp dual-edge modulation scheme for a 4-phase system;  
         [0025]      FIG. 8  is a block diagram illustrating an adaptive PWM pulse positioning system according to one embodiment of the present invention applicable to dual-ramp dual-edge PWM modulation circuits;  
         [0026]      FIG. 9  is a schematic diagram of a PWM pulse positioning system implementing an exemplary embodiment of the adaptive PWM pulse positioning system of  FIG. 8 ;  
         [0027]      FIG. 10  is a timing diagram illustrating operation of the adaptive PWM pulse positioning system of  FIG. 9  for a four phase system;  
         [0028]      FIG. 11  is a block diagram illustrating an adaptive PWM pulse positioning system according to another embodiment of the present invention applicable to dual-ramp dual-edge PWM modulation circuits.  
         [0029]      FIG. 12  is a block diagram illustrating an adaptive PWM pulse positioning system according to another embodiment of the present invention applicable to dual-ramp dual-edge PWM modulation circuits;  
         [0030]      FIG. 13  is a schematic diagram of an adaptive PWM pulse positioning system implementing an exemplary embodiment of the adaptive PWM pulse positioning system of  FIG. 12 ;  
         [0031]      FIG. 14  is a timing diagram illustrating operation of the adaptive PWM pulse positioning system of  FIG. 13  for a four phase system;  
         [0032]      FIG. 15  is a block diagram of a down ramp generator which may be used to develop the down ramp signal of the dual-ramp dual-edge PWM modulation circuit of  FIG. 6 , thus illustrating an adaptive PWM pulse positioning system according to another embodiment of the present invention; and  
         [0033]      FIG. 16  is a timing diagram illustrating operation of an adaptive PWM pulse positioning system employing the down ramp generator of  FIG. 15 . 
     
    
     DETAILED DESCRIPTION  
       [0034]     The following description is presented to enable one of ordinary skill in the art to make and use the present invention as provided within the context of a particular application and its requirements. Various modifications to the preferred embodiment will, however, be apparent to one skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described herein, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.  
         [0035]      FIG. 1  is a timing diagram illustrating an operation mode of an adaptive PWM pulse positioning scheme according to an embodiment of the present invention. In  FIG. 1 , an output load current I LOAD  of a DC-DC power regulator (not shown) is plotted versus a clock signal and a PWM signal. At an initial time t 0 , the I LOAD  signal is at a normal level I NORM . The clock signal generates a periodic clock pulse according to a predetermined clock frequency. During normal operation under normal load as indicated by the I NORM  level of the I LOAD  signal, each PWM pulse begins during each clock cycle and is terminated by a pulse on the clock signal. At a subsequent time t 1 , an output transient occurs as indicated by the I LOAD  signal jumping to a new high current level indicated as I HIGH . In response to the output load transient, the next pulse  101  of the PWM signal is repositioned towards the beginning of the current clock cycle as indicated by arrow  103  relative to its normal position indicated with dotted lines. By moving the pulse  101  towards the beginning of the cycle after applying heavy load, the blank period after the transient event is naturally shortened, resulting in no extra voltage drop after the initial transient response. In this case, the pulse  101  also has a longer duration in response to the increase in the output load. The subsequent pulses  105 ,  107  and  109  of the PWM signal during the increased load event (while I LOAD  is at I HIGH ) are shifted towards the beginning of respective clock cycles.  
         [0036]     At subsequent time t 2 , the I LOAD  signal returns to the normal level I NORM . The next pulse  111  of the PWM signal is shifted back to the normal position at the end of the clock cycle as indicated by arrow  113 . In certain modulation schemes as indicated in  FIG. 1 , the PWM pulse usually occurs at the end of the cycle. Under the transient event, the PWM pulse is pulled ahead in response to the output voltage drop. After the transient event, the PWM pulse goes back to its normal position (e.g., the end of the cycle). In order to avoid the extra voltage drop due to the blank period, the PWM pulse is moved towards the beginning of the cycle under the heavy load. The PWM pulse is at the end of the cycle under light load, therefore, and it moves according to the load condition such as towards the beginning of the cycle under full load condition. The PWM pulse position is flexible for better performance.  
         [0037]     Rather than re-positioning the pulse, it is possible to allow a second PWM pulse in the same cycle, which causes the output to settle down sooner. A second pulse in the same cycle, however, tends to increase the switching frequency and thermal dissipation on the power stage if the transient event happens at a high repetitious rate. For fast transient response, it is desired that the PWM pulse be pulled ahead in one or more cycles. It is better to keep the PWM pulse near the end of the cycle under light load, so there is sufficient space to pull the pulse ahead in response to load transient events. The PWM pulse can be placed anywhere within a switching cycle under heavy load. For a load release event, the PWM ends soon after the transient and some blank time is necessary to discharge inductor current. So it is desirable to let the PWM pulse occur at the beginning of the cycle under heavy load condition. Therefore the PWM pulse is kept at the end of the cycle under light load condition, and moved to the beginning of the cycle when the load increases.  
         [0038]      FIG. 2  is a simplified block diagram of a trailing edge modulator circuit  200  implemented according to an embodiment of the present invention. A timing source  201  generates a clock signal A which is provided to the input of a delay function  203 . The delay function  203  delays the A signal and provides a delayed clock signal AD to the input of a ramp generator  205  and to a clock (CK) input of pulse timing circuit  211 . In an alternative embodiment, the pulse timing circuit is replaced by an SR flip-flop. The ramp generator  205  generates a ramp signal B, which is provided to one input (e.g., inverting input) of a PWM comparator  207 . An error amplifier  209  provides a compensation signal C to the other input (e.g., non-inverting input) of the comparator  207 . The comparator  207  generates a signal D, which is provided to a control (CTL) input of the pulse timing circuit  211 . The pulse timing circuit  411  generates a PWM signal based on the D signal used to control the output voltage of the DC-DC power regulator, and is configured to ensure only one pulse per cycle of the AD signal. A current sense block  213  provides an adjust signal ADJ to another input of the delay function  203 . The current sense block  213  senses output current, such as the load current I LOAD  through an output load (as shown) and controls the ADJ signal accordingly. The C signal and the output voltage of the converter V OUT  are also shown provided to the delay function  203 . The amount of delay between the signals A and AD, or T DELAY , is a function of ADJ, V OUT  and C, or T DELAY =TD1+f1*ADJ+f2*C+f3*V OUT , where TD1 is a constant, and the functions f1, f2 and f3 are any suitable functions that range from relatively simple to as complex as desired. In one embodiment, f1-f3 are constants.  
         [0039]     In an alternative embodiment, the current sense block  213  senses current through an output inductor of the regulator, or senses the phase current of each of one or more output phase circuits.  
         [0040]      FIG. 3  is a timing diagram illustrating operation of the trailing edge modulator circuit  200 . The signals I LOAD , A, AD, B, C, D, and PWM are plotted versus time. The B and C signals are superimposed with each other to more clearly illustrate the function of the comparator  207 . In the illustrated embodiment, the ramp generator  205  generates the B signal as a sawtooth waveform with rising ramps. Thus, the ramp signal B begins at a low ramp level R LO  when the AD signal pulses high and rises at a constant rate when the AD pulse goes back low. The ramp signal B is constrained to a predetermined high level R HI  in the illustrated embodiment. The compensation signal C is configured to range between R LO  and R HI . In operation, the B ramp signal resets back to R LO  upon the initial edge of the AD clock signal and ramps up beginning with the trailing edge of the AD clock signal. The comparator  207  asserts the D signal high while B is lower than C, and otherwise asserts the D signal low. The pulse timing circuit  211  generally asserts the PWM signal coincident with the D signal except beginning after the AD signal goes low in each cycle, so that PWM goes high when AD goes low and goes low when D goes low. Operation repeats in this manner and the duration of each PWM pulse depends in part on the level of the compensation signal C.  
         [0041]     In a conventional trailing edge modulator circuit (not shown), the delay function  203  is not present so that timing is based on the A clock signal rather than the AD clock signal. The delay function  203  enables the timing of the AD clock signal to be adjusted based on the ADJ signal from the current sense block  213 , which modifies the ADJ signal based on the level of the I LOAD  signal (or other sensed output current). At a time t 9 , the I LOAD  signal jumps from I NORM  to I HIGH  as previously described. In response, the current sense block  213  modifies the ADJ signal to decrease the delay of the AD signal relative to the clock signal A. As shown at  301 , the next pulse on the AD signal is shifted or re-positioned to earlier in the cycle. The early initial edge of the AD pulse causes the ramp signal B to reset back to R LO  earlier than normal as shown at  303 . The early reset of the ramp signal B causes the D signal to shift position to earlier in the cycle as shown at  305 . The early pulse on the D signal causes the PWM signal to be shifted to be asserted earlier in the cycle as shown at  307 . After the load transient shift event, timing of the pulses are effectively the same except that they are shifted relative to the normally condition. The relative widths of the PWM pulses may adjust to handle the additional load. In this manner, the PWM signal is repositioned to earlier in the cycle in response to the load transient event. The PWM signal remains shifted as long as the load transient condition exists, and returns to normal when the higher load condition is removed. As shown at time t 10 , the I LOAD  signal returns to I NORM , and the next AD pulse shifts to later in the cycle as shown at  309 . This causes the D and the PWM pulses to shift back to their normal positions. In this manner, the positions of the PWM pulses are adjusted or adapted in response to the load transient to provide better performance.  
         [0042]     The delay function  203  does not increase the frequency of the clock signal but instead simply enables a temporary adjustment of the positioning of the PWM pulses. It is noted that the delay during normal conditions may be made as long as desired, such as one period of the A signal. If the delay is about equal to the clock period, then the PWM pulse may be repositioned to almost anywhere within a given cycle to properly respond to an asynchronous load transient event.  
         [0043]      FIG. 4  is a simplified block diagram of a dual edge modulator circuit  400  implemented according to an embodiment of the present invention. In a similar manner as with the trailing edge modulator circuit  200 , a timing source  401  generates a clock signal A which is provided to the input of a delay function  403 . The delay function may operate in substantially the same manner as the delay function  205 . The delay function  403  delays the A signal and provides a delayed clock signal AD to the input of a triangle ramp generator  405  and to a clock (CK) input of pulse timing circuit  411 . The triangle ramp generator  405  generates a triangle ramp signal T, which is provided to one input (e.g., inverting input) of a comparator  407 . An error amplifier  409  provides a compensation signal C to the other input (e.g., non-inverting input) of the comparator  407  and to the delay function  403 . The comparator  407  generates a signal D, which is provided to a control input of the pulse timing circuit  411 . The pulse timing circuit  411  generates a PWM signal based on the D signal used to control the output voltage, and is configured to ensure only one pulse per clock cycle. A current sense circuit  413  receives the I LOAD  signal and provides an adjust signal ADJ to another input of the delay function  403 , which also receives the V OUT  signal as shown. The current sense circuit  413  senses output current, such as the load current through an output load or the current through an output inductor or the phase current of each of one or more output phase circuits, and controls the ADJ signal accordingly as previously described. The V OUT  signal is also shown provided to the delay function  403 . The amount of delay provided by the delay function  403  is substantially similar to the delay function  203 , or T DELAY =TD1+f1*ADJ+f2*C+f3*V OUT .  
         [0044]      FIG. 5  is a timing diagram illustrating operation of the trailing edge modulator circuit  400 . The signals I LOAD , A, AD, T, C, D, and PWM are plotted versus time. The T and C signals are superimposed with each other to more clearly illustrate the function of the comparator  407 . In this case, the clock signals A and AD are 50% duty cycle signals. The triangle ramp signal T ramps up while the AD signal is low and ramps down while the AD signal is high. In operation, the D signal is asserted high when the T signal is less than the C signal but is otherwise asserted low. The PWM signal is asserted by the pulse timing circuit  411  while the D signal is high. Operation repeats in this manner and the duration of each PWM pulse depends in part on the level of the compensation signal C.  
         [0045]     In a conventional dual edge modulator circuit (not shown), the delay function  403  is not present so that timing is based on the A clock signal rather than the AD clock signal. For the dual edge modulator circuit  400 , the delay function  403  enables the timing of the AD clock signal to be adjusted based on the ADJ signal from the current sense block  413 , which modifies the ADJ signal based on the level of the I LOAD  signal. At a time t 11 , the I LOAD  signal jumps from I NORM  to I HIGH  as previously described. The current sense block  413  modifies the ADJ signal in response to decrease the delay of the AD signal relative to the clock signal A. As shown at  501 , the AD signal is shifted earlier in the cycle because of the reduced delay. The triangular ramp signal T ramps down earlier (as compared to normal conditions) to intersect the C signal earlier in the clock cycle as shown at  503 . The early intersection between the T and C signals causes the D signal to be shifted to be asserted earlier in the cycle as shown at  505 , which thus causes the PWM signal to be re-positioned to earlier in the cycle as shown at  507 . The adaptive positioning results in the PWM signal being repositioned to earlier in the cycle in response to the load transient event. The PWM pulses remain shifted as long as the load transient condition exists, and return to normal positions when the load condition is removed. As shown as subsequent time t 12 , the I LOAD  signal returns to I NORM , causing the AD, D and PWM signals to shift back to their normal positions. In this manner, the position of the PWM pulse is adjusted or adapted and thus flexible for better performance.  
         [0046]     A dual-edge modulation scheme using dual ramps was disclosed in U.S. patent application Ser. No. 11/318,081 entitled “PWM controller with dual-edge modulation using dual ramps” filed Dec. 23, 2005, which is herein incorporated by reference for all intents and purposes. The dual-ramp, dual-edge modulation scheme also limits the PWM pulses to one per clock cycle. Due to one pulse per cycle limit, there may exist a period without any PWM pulse after an initial response to a heavy load transient event. This blank period may result in extra voltage drop after the transient event. In one dual-ramp dual-edge modulation scheme, the PWM pulse always happens at the end of the cycle. Under the transient event, the PWM pulse may be pulled ahead in response to the output voltage drop. After the transient event, the PWM pulse goes back to the end of the cycle. In order to avoid the extra voltage drop due to the blank period, the PWM pulse can be moved to the beginning of the cycle under the heavy load. Therefore the PWM pulse is at the end of the cycle under light load, and it moves according to the load condition, and at the beginning of the cycle under full load condition. The PWM pulse position is flexible for better performance.  
         [0047]      FIG. 6  is a schematic diagram of a dual-ramp dual-edge PWM modulation circuit  600  according to an embodiment described in the above-referenced patent application. A down ramp comparator CMP 1  has a non-inverting input receiving a compensation signal V COMP  (such as from an error amplifier, e.g.,  209 ,  409 ), an inverting input receiving a down ramp signal V DOWN     —     RAMP , and an output coupled to the set input of a set-reset (SR) flip-flop  601 . An up ramp comparator CMP 2  has an inverting input receiving the V COMP  signal, a non-inverting input receiving an up ramp signal V UP     —     RAMP , and an output coupled to the reset input of the SR flip-flop  601 . The Q output of the SR flip-flop  601  asserts the PWM signal providing PWM pulses. A timing source  603  generates a clock signal CK, which is provided to a leading-edge ramp generator  605 . In the embodiment shown, the leading-edge ramp generator  605  generates the down ramp sawtooth waveform, shown as V DOWN     —     RAMP , synchronous with the CK signal. When the down ramp signal falls to the level of V COMP , the comparator CMP 1  asserts its output high and sets the SR flip-flop  601 , which asserts the PWM signal high to initiate each PWM pulse. A trailing-edge ramp generator  607  generates a trailing-edge ramp signal for purposes of terminating each PWM pulse, which is shown as the up ramp signal V UP     —     RAMP . When the PWM signal is asserted high, the trailing-edge ramp generator  607  begins ramping up the V UP     —     RAMP  signal (see, e.g., operation of the V UP     —     RAMP  signal shown in  FIG. 16 ). When V UP     —     RAMP  reaches V COMP , the comparator CMP 2  asserts its output high, resetting the SR flip-flop  601 , and pulling the PWM signal low thereby terminating each PWM pulse. When PWM is pulled low, the trailing-edge ramp generator  607  pulls the V UP     —     RAMP  signal back low again.  
         [0048]     The dual-ramp dual-edge PWM modulation circuit  600  turns on and off the PWM pulse at any time within one switching cycle, so its transient response is very quick. Under normal operation, the PWM pulse occurs at the end of the switching cycle. When the heavy load is applied at the beginning of the cycle, the PWM pulse is pulled ahead to the beginning of the switching cycle to try to keep the output within the specifications. In order to limit the switching frequency, typically only one PWM pulse is allowed in one switching cycle. If the heavy transient load event and PWM pulse happens at the beginning of the cycle, another PWM pulse does not occur until next cycle. There may exist a long period in which a PWM pulse does not occur, resulting in extra voltage drop after the initial response.  
         [0049]      FIG. 7  is a timing diagram illustrating operation of the dual-ramp dual-edge PWM modulation circuit  600  illustrating the long blank period issue in the dual-ramp dual-edge modulation scheme for a 4-phase system. Signals I LOAD , four V DOWN     —     RAMP  signals  1 - 4  (one for each phase, or V DOWN     —     RAMP1 -V DOWN     —     RAMP4 ), the voltage of the compensation signal (V COMP ) and corresponding four PWM signals PWM 1 , PWM 2 , PWM 3  and PWM 4  are plotted versus time. At about a time t 20 , a heavy load is applied to the system and the control loop quickly turns on all phases responding to this event as illustrated by simultaneous pulses on each PWM signal. At subsequent time t 21 , all phases are turned off. At subsequent time t 22 , the control voltage, V COMP , returns to its operational point. In the ideal case, if the system is stable after this time, the control voltage is expected to be constant as indicated by a dashed line  701 . Due to the one-pulse-per-cycle limitation, however, there is not another PWM pulse until a time t 24 . In the ideal case, therefore, there exists a “blank” period T 1  between times t 21  and t 24 , which is about equal to the switching period. In an actual case, since no PWM pulse occurs in the blank period, the output voltage drops until next PWM pulse. Therefore the actual compensation voltage V COMP  increases as shown at  703  attempting to maintain the output voltage within the specifications. So, there is a PWM pulse earlier in the cycle at a time t 23  so that the actual blank period T 2  between times t 21  and t 23  is much less than the switching period. Even though the blank period T 2  is less than one switching cycle, it causes the extra voltage drop, and the output voltage may oscillate several cycles before it settles down.  
         [0050]     Therefore, in the illustrated dual edge scheme, there may exist a blank period after the initial transient response in the dual-ramp dual-edge modulation scheme, which results in the extra voltage drop and possible oscillation issue. In order to avoid the extra voltage drop, the blank period should be as short as possible. One way to solve the issue is to allow a second pulse in the same cycle under the heavy transient event. As shown in  FIG. 7 , V COMP  goes up again after the initial transient response. If the second PWM pulse is allowed in the same cycle, the output settles down soon. But it may increase the switching frequency and thermal dissipation on the power stage if the transient event happens at a high repetitious rate. For fast transient response, the PWM pulse should be able to be pulled ahead in one cycle. It is better to keep the PWM pulse at the end of the cycle under light load, so there is space to pull the pulse ahead. However, the PWM pulse can be placed anywhere within a switching cycle under heavy load. For a load release event, the PWM ends soon after the transient and some blank time is necessary to discharge the inductor current. So it is desirable to let the PWM pulse occur at the beginning of the cycle under heavy load condition. As described further below, the PWM pulse is kept at the end of the cycle under light load condition, and is moved to the beginning of the cycle when the load increases.  
         [0051]      FIG. 8  is a block diagram illustrating an adaptive PWM pulse positioning system  800  according to one embodiment of the present invention applicable to dual-ramp dual-edge PWM modulation circuits. Similar components as those of the dual-ramp dual-edge PWM modulation circuit  600  assume identical reference characters. The timing source  603  and the generators  605  and  607  are not shown but are provided and operate in the same manner. The up ramp comparator CMP 2  receives the V COMP  and V UP     —     RAMP  signals and has its output coupled to the reset input of the SR flip-flop  601 . The inverting input of the down ramp comparator CMP 1  receives the down ramp signal V DOWN     —     RAMP  and its output is coupled to the set input of the SR flip-flop  601 . In this case, an offset voltage VO is added to the error amplifier output signal V COMP  using a function block  801  and an adder  803 , which provides an adjusted compensation signal V C1  to the non-inverting input of the comparator CMP 1 . The output of the comparator CMP 1  is coupled to the set input of the SR flip-flop  601 . The offset voltage VO is a function f 1 (s) of the sensed average current I AVG  of all phases, such that VO=f 1 (s)*I AVG  in which an asterisk “*” denotes multiplication. Under heavy load, the offset voltage VO is high to trigger the PWM pulse early in the cycle. Although not shown, a balance current may be used to adjust the compensation signal provided to the up ramp comparator CMP 2 , in which the balance current is related to a sensed phase current of one phase I phase  and the sensed average current I AVG  of all phases, e.g, f 2 (I AVG , I phase ) where f 2  is any suitable function. A simple example is I balance =k*(I AVG −I phase ), where k is a constant.  
         [0052]      FIG. 9  is a schematic diagram of a PWM pulse positioning system  900  implementing an exemplary embodiment of the adaptive PWM pulse positioning system  800 . Similar components as those of the dual-ramp dual-edge PWM modulation circuit  800  assume identical reference characters. The timing source  603  and the generators  605  and  607  are not shown but are provided and operate in the same manner. In this case, the V COMP  signal is provided to one end of a resistor R 1 , having its other end developing the V C1  signal provided to the non-inverting input of the comparator CMP 1 . The I AVG  current is injected into the node developing the V C1  signal, so that VO=R 1 *I AVG  and V C1 =V COMP +R 1 *I AVG .  
         [0053]      FIG. 10  is a timing diagram illustrating operation of the adaptive PWM pulse positioning system  900  for a four phase system, which includes four down ramp signals V DOWN     —     RAMP1 -V DOWN     —     RAMP4  and four PWM signals PWM 1 -PWM 4 . The signals I LOAD , V C1 , V DOWN     —     RAMP1 -V DOWN     —     RAMP4 , and PWM 1 -PWM 4  are plotted versus time. The V C1  signal is superimposed with the V DOWN     —     RAMP1 -V DOWN     —     RAMP4  signals to illustrate operation of respective comparators for developing the PWM1-PWM4 signals. The voltage of V COMP  is shown with dashed lines for purposes of comparison. As shown, a load transient occurs just before a time t 30 , causing triggering of all of the PWM1-PWM4 signals, which go low again at about time t 31 . Additional PWM pulses occur on the PWM2, PWM3 and PWM4 signals at times t 32 , t 33  and t 34 , respectively, each significantly earlier than would otherwise occur if the V COMP  signal was provided directly to the comparator CMP 1  rather than the modified compensation signal V C1 . In this manner, performance is significantly improved.  
         [0054]      FIG. 11  is a block diagram illustrating an adaptive PWM pulse positioning system  1100  according to another embodiment of the present invention applicable to dual-ramp dual-edge PWM modulation circuits. The adaptive PWM pulse positioning system  1100  is similar to the adaptive PWM pulse positioning system  800 , in which similar components assume identical reference characters. The timing source  603  and the generators  605  and  607  are not shown but are provided and operate in the same manner. The I AVG  signal is provided to the function block  801  for developing the offset voltage VO, which is provided to the inverting input of an adder  1101 . The adder  1101  receives the V DOWN     —     RAMP  signal at its non-inverting input. In this case, the V DOWN     —     RAMP  signal is adjusted by the offset voltage VO rather than the error amplifier output signal V COMP . The adder  1101  subtracts VO from V DOWN     —     RAMP  to develop an adjusted ramp signal VR, which is provided to the inverting input of the comparator CMP 1 . As shown, the error amplifier output signal V COMP  is provided directly to the inverting input of the comparator CMP 2 , which receives the V UP     —     RAMP  at its non-inverting input and which has its output coupled to the reset input of the SR flip-flop  601 . The SR flip-flop  601  operates in similar manner to provide the PWM signal.  
         [0055]      FIG. 12  is a block diagram illustrating an adaptive PWM pulse positioning system  1200  according to another embodiment of the present invention applicable to dual-ramp dual-edge PWM modulation circuits. The adaptive PWM pulse positioning system  1200  is similar to the dual-ramp dual-edge PWM modulation circuit  600  in which similar components assume identical reference characters. The timing source  603  and the generators  605  and  607  are not shown but are provided and operate in the same manner. The comparator CMP 1  is provided and compares the V COMP  and V DOWN     —     RAMP  signals and provides its output to the set input of the SR Flip-Flop  600  providing the PWM signal at its Q output. In this case, a different offset voltage VO 2  is developed which is related to the sensed phase current I PHASE  of the respective phase of a multiphase converter. The current I PHASE  is provided to the input of a function block  1201  (multiplying I PHASE  by a function f3(s)) to develop VO 2 , which is then provided to an input of an adder  1203 . The adder  1203  adds V COMP  to VO 2  develop an adjusted compensation signal VC 2 . The VC2 signal is provided to the inverting input of the comparator CMP 2 , which receives V UP     —     RAMP  at its non-inverting input and which has its output coupled to the reset input of the SR flip-flop  601 . Under heavy load, the offset voltage VO 2  is high, and the V C2  voltage increases to keep the same duty cycle, resulting in early triggering of the PWM pulse for each phase.  
         [0056]      FIG. 13  is a schematic diagram of an adaptive PWM pulse positioning system  1300  implementing an exemplary embodiment of the adaptive PWM pulse positioning system  1200 . Again, similar components assume identical reference characters. The timing source  603  and the generators  605  and  607  are not shown but are provided and operate in the same manner. In this case, the function block  1201  and the adder  1203  are effectively replaced with a resistor R 2 , having one end receiving the V COMP  signal and another end developing the V C2  signal, which is provided to the inverting input of the comparator CMP 2  as shown. The I PHASE  current is pulled from the node developing the V C2  signal, such that V C2 =V COMP −R 2 *I PHASE . The adjusted compensation signal V C2  is compared with the V UP     —     RAMP  signal by the comparator CMP 2 , which has its output coupled to the reset input of the SR flip-flop  601 . The circuit of the comparator CMP 1  is the same as that shown in  FIG. 12 .  
         [0057]      FIG. 14  is a timing diagram illustrating operation of the adaptive PWM pulse positioning system  1300  for a four phase system, which includes four down ramp signals V DOWN     —     RAMP1 -V DOWN     —     RAMP4  and four PWM signals PWM 1 -PWM 4 . The signals I LOAD , V C2 , V DOWN     —     RAMP1 -V DOWN     —     RAMP4 , AND PWM 1 -PWM 4  ARE PLOTTED VERSUS TIME. THE V C2  signal is superimposed with the V DOWN     —     RAMP1 -V DOWN     —     RAMP4  signals to illustrate operation of respective comparators for developing the PWM1-PWM4 signals. As shown, a load transient occurs about a time t 40 , causing triggering of all of the PWM1-PWM4 signals, which go low again at a subsequent time t 41 . Additional PWM pulses occur on the PWM2, PWM3 and PWM4 signals at times t 42 , t 43  and t 44 , respectively, each significantly earlier than would otherwise occur if the V COMP  signal was provided directly to the comparator CMP 2  rather than the modified compensation signal V C2 . In this manner, performance is significantly improved.  
         [0058]      FIG. 15  is a block diagram of a down ramp generator  1500  which may be used to develop the V DOWN     —     RAMP  signal of the dual-ramp dual-edge PWM modulation circuit  600 , thus illustrating an adaptive PWM pulse positioning system according to another embodiment of the present invention. Thus, the dual-ramp dual-edge PWM modulation circuit  600  is used except that the leading-edge ramp generator  605  is replaced with the down ramp generator  1500 . And for the down ramp generator  1500 , a controlled current sink  1501  is coupled between ground (GND) and a node  1502  developing the V DOWN     —     RAMP  signal. A capacitor C 1  is coupled between node  1502  and GND. A diode  1503  has its cathode coupled to node  1502  and its anode coupled to the positive terminal of a voltage source  1505  developing a minimum ramp voltage V MIN . A single-pole, single-throw (SPST) switch SW has its switched terminals coupled between node  1502  and the positive terminal of a voltage source  1507  developing a maximum ramp voltage V MAX , where V MAX  is greater than V MIN . The negative terminals of the voltage sources  1505  and  1507  are coupled to GND. The switch SW has a control terminal receiving the clock signal (CLK), which opens and closes the SW at the frequency of the CLK signal. The current sink  1501  has a control terminal receiving a signal C+k*I AVG , in which C and k are constants. In this manner, the current of the current sink  1501  is based on the measured or sensed level of I AVG .  
         [0059]     In operation of the down ramp generator  1500 , the switch SW closes and the voltage source  1507  charges the capacitor C 1  to the voltage level V MAX . When the switch SW is opened, the current sink  1501  discharges the capacitor C 1  at a rate based on the I AVG  signal. The constants C and k are determined to provide a suitable slew rate of the V DOWN     —     RAMP  signal for a normal operating level of the I AVG  signal. When the I AVG  signal is increased due to a load transition, the slew rate of the V DOWN     —     RAMP  signal is increase accordingly to accelerate discharge of the capacitor C 1  and thus re-position the next PWM pulse earlier in the cycle. Consequently, the slew rate of the V DOWN     —     RAMP  signal is adjusted based on the sensed average current I AVG . Under light load, I AVG  is lower and the slew rate of the V DOWN     —     RAMP  signal is low. Under heavy load, I AVG  is increased and the slew rate of the V DOWN     —     RAMP  signal is increased, resulting in early triggering of the PWM pulse in the cycle.  
         [0060]      FIG. 16  is a timing diagram illustrating operation of an adaptive PWM pulse positioning system employing the down ramp generator  1500 . The I LOAD , CLK, V DOWN     —     RAMP , V UP     —     RAMP , V COMP  and PWM signals are plotted versus time. The V COMP  signal is superimposed with both the V DOWN     —     RAMP  and V UP     —     RAMP  signals to illustrate operation of the comparators CMP 1  and CMP 2 . When the I LOAD  signal jumps from I NORM  to I HIGH , the V COMP  signal temporarily increases and the I AVG  signal also increases causing early triggering the PWM signal.  
         [0061]     Although the present invention has been described in considerable detail with reference to certain preferred versions thereof, other versions and variations are possible and contemplated. For example, the delay adjustment of the clock signal or the offset voltage added to the ramp signals and/or the compensation signals may be based on operational parameters other than output or load current, such as input voltage, a differential of output current and/or output voltage (e.g., a transient event or the like), etc. The present invention is also applicable to digital modulators in which the analog functions (e.g., ramps, error signals, compensation signals, etc.) are replaced by digital calculations and/or algorithms and the like. The present invention is applicable to modulators employing digital control, such as used to adjust the delay time, adjusting the clock signal, adjusting timing of PWM pulse activation, adjusting PWM duty cycle based on a calculation result, etc. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for providing out the same purposes of the present invention without departing from the spirit and scope of the invention.