Abstract:
A data storage control device including a DRAM and a storage device has an address bus common to the DRAM and the storage device, and a control device for selectively applying an address signal relating to the DRAM and another address signal relating to the storage device to the address bus.

Description:
FIELD OF THE INVENTION 
     This invention relates to a data storage control device. 
     BACKGROUND OF THE INVENTION 
     In conventional data storage control devices that include a dynamic RAM (referred to herein as a DRAM) and a ROM, a control circuit associated with a CPU or the like has a first group of address terminals for the DRAM and a second group of address terminals for the ROM, these groups being connected to separate address buses. 
     Since the conventional device uses separate address buses for the DRAM and the ROM, it is large in size and high in cost. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a data storage control device of simplified configuration. 
     To solve the foregoing problems, the present invention provides a data storage control device including a DRAM and storage means such as a ROM or the like, comprising common address bus means for the DRAM and the storage means, and control means for selectively applying address signals for the DRAM and address signals for the storage means to the address bus means. 
    
    
     BRIEF DESCRIPTION OF THE FIGURES 
     An embodiment of the present invention will now be described with reference to the drawings, whereby: 
     FIG. 1 is a block diagram showing an embodiment of the present invention; and 
     FIG. 2 is a time chart used in describing the operation of the device of FIG. 1. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In FIG. 1, DRAM 1 has seven address terminals A0-A6. Storage means 2 has fifteen address terminals A0-A14, and is a ROM in the present embodiment. CPU 3 controls data accessing with respect to the DRAM 1 and data reading with respect to the ROM 2. DRAM controller 4 controls addressing with respect to the DRAM 1, and a selector 5 selectively delivers address signals for the DRAM 1 and address signals for the ROM 2, these units constituting a control means 6. The CPU 3 and the DRAM controller 4 are synchronized with a common clock signal. In the illustrated embodiment, the seven address terminals of the DRAM 1 and the seven address terminals of the ROM 2 are connected to a common address bus B extending from the selector 5. 
     Referring to the time chart of FIG. 2, the process of accessing the DRAM I and the ROM 2 will be described. In this embodiment, the address signals are comprised of sixteen bits A0-A15, and the DRAM 1 is accessed when bit A15 is &#34;1&#34; (i.e. HIGH), whereas the ROM 2 is accessed when it is &#34;0&#34; (i.e. LOW). 
     First, assume, as shown at line a in FIG. 2 that address signal &#34;OOFFH&#34; is delivered from the CPU 3. Since bit A15 is &#34;0&#34;, this address signal is used for the ROM 2. That is, since bit A15 is low, the selector 5 chooses its terminal b, and as shown at line e in FIG. 2, bits A0-A6 (=7FH ) delivered from the CPU 3 are applied to the address bus B as seven lower-order address bits for the ROM 2. Bits A7-A14 are directly applied from the CPU 3 to the ROM 2. Bit A15 is applied to a CS (chip select) terminal of the ROM 2 to set the ROM 2 to an accessible state. Then, when a read signal RD delivered from the CPU 3 changes to &#34;0&#34; as shown at line c in FIG. 2, read data D0-D7 as shown at line b in FIG. 2 is read out from the address of the ROM 2 designated by bits A0-A14. It should be noted that when bit A15 is &#34;0&#34;, the RAS (row address strobe) signal and CAS (column address strobe) signal delivered from the DRAM controller 4 are not &#34;0&#34;, as shown at lines f and g in FIG. 2; thus, the DRAM 1 is not accessed. 
     Then, assume, as shown at line a in FIG. 2 that address signal &#34;FOFOH&#34; is delivered from the CPU 3. Since bit A15 is &#34;1&#34;, this address signal is to be used for the DRAM 1. That is, since bit A15 is high, the selector 5 chooses its terminal a. The DRAM controller 4 delivers bits A0-A6 (=70H ) and then bits A7-A13 (=61H) in a time sharing manner, these bits or the address signal being applied through the selector 5 to the address bus B as shown at line e in FIG. 2. Then, when the RAS signal changes to &#34;0&#34; as shown at line f in FIG. 2, bits AO-A6 are latched in the DRAM 1, and when the CAS signal changes to &#34;0&#34; as shown at line g in FIG. 2, bits A7-A13 are latched in the DRAM 1. Then, when a write signal WR delivered from the CPU 3 changes to &#34;0&#34; as shown at line d in FIG. 2, write data D0-D7 as shown at b in FIG. 2 is written at the address designated by bits AO-A13. 
     When data is to be read out from the DRAM 1, a process similar to the write process is performed under conditions in which the write signal WR delivered from the CPU 3 is not &#34;0&#34;. 
     As described above, the DRAM 1 and ROM 2 can be accessed through the common address bus B. 
     As will be appreciated, the number of bits of the address signal and the number of storage units can be set arbitrarily. The storage means may be a static RAM or the like instead of a ROM. 
     According to the present invention, the address bus is used in common for the DRAM and the storage means; therefore, the components, such as address terminals and address buses, can be reduced, the device can be miniaturized, and the cost can be decreased.