Abstract:
A video display system employing a flat display panel of X-Y matrix type, signal sampling means, &#34;write in&#34; and &#34;read out&#34; memory circuits serially connected between the signal sampling means and the display panel, and a novel signal control means connected to the &#34;write in&#34; and &#34;read out&#34; memory circuits wherein the number of lines or leads for distributing signals from the &#34;read out&#34; memory circuits to the display panel and the number of memory devices used in the &#34;read out&#34; memory circuits are reduced substantially.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to a video display system and more particularly to such a system which includes a flat panel of X-Y matrix type and an improved signal storing and read-out means for making the whole system simple in construction and small in size. 
     2. Description of the Prior Art 
     Recently, video display systems utilizing a flat panel of X-Y matrix type have become the object of considerable interest for television signal reproducing apparatus. 
     In such systems, different kinds of flat panels, such as gas discharge panels, liquid crystal panels, electroluminescent panels and the like have been used, and extensive research has been conducted in respect to the flat panels and their driving circuits. 
     However, the video display systems of the prior art are usually complicated especially in their driving circuits. 
     One reason for this complexity is the very large number of signal distribution lines or leads for driving the flat panel and another reason is the correspondingly large number of memory devices used therein. 
     In more detail, supposing that an X-Y matrix of display panel is formed by 300 column lines and 300 row lines and a video input signal is sampled and each sample converted to a 4-bit digitally coded signal, the system is usually provided with 300 × 4 = 1200  memory devices for storing or writing the digitially coded signal and another 1200 memory devices for reading out the digitally coded signal, so that the total number of the memory devices is of 1200 × 2 = 2400, and further the number of the signal distribution lines or leads from the memory devices to the display panel also is 1200 × 2 = 2400. 
     OBJECTS AND SUMMARY OF THE INVENTION 
     Accordingly, it is an object of this invention to provide an improved video display system of the type referred to above, and in which the inherent disadvantages in the prior art are avoided. 
     It is another object of the invention to provide an improved video display system having a flat panel of X-Y matrix type in which signal memory circuits are simplified. 
     It is a further object of the invention to provide an improved video display system having a flat panel of X-Y matrix type in which a signal distribution system in the memory circuits is simplified and made efficient. 
     The video display system of this invention includes a flat display panel of X-Y matrix type, signal sampling means, &#34;write in&#34; and &#34;read out&#34; memory circuits serially connected between the signal sampling means and the display panel, and a novel signal control means connected to the &#34;write in&#34; and &#34;read out&#34; memory circuits. 
     In accordance with an aspect of the invention, each of the &#34;read out&#34; memory circuits is formed as an m-bit (m being a positive integer) shift register having an input terminal for receiving signals from the corresponding one of the &#34;write in&#34; memory circuits and m output terminals for reading out signals in parallel therefrom whereby the signal distribution from the &#34;read out&#34; memory circuits to the display panel is simplified and made efficient. 
     According to another aspect of this invention, the number of &#34;read out&#34; memory circuits is reduced to be a fraction of the number of &#34;write in&#34; memory circuits by introducing a novel control means for transmitting signals from the &#34;write in&#34; memory circuits to the &#34;read out&#34; memory circuits fragmentarily during a horizontal scanning period. 
     This invention will best be understood from the following detailed description read in connection with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a video display system according to the prior art. 
     FIGS. 2A-2J, inclusive, are waveform diagrams which are useful in explaining the operation of the video display system shown in FIG. 1. 
     FIG. 3 is a block diagram of a video display system according to one embodiment of the present invention, and 
     FIGS. 4A-4E and 5A-5U, inclusive, are waveform diagrams which are useful in explaining the operation of the video display system of the embodiment shown in FIG. 3. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In order to better understand the present invention, the prior art video display system will be described with reference to FIGS. 1 and 2A to 2J. 
     In FIG. 1, reference numeral 1 designates a video display panel or flat panel such as, for example, of a discharge tube of X-Y matrix type which has a plurality of parallel row lines X 1 , X 2 , . . . and a plurality of parallel column lines Y 1 , Y 2 , . . . Y K  perpendicular to the former (K being a positive integer). In this case, byway of example, the row lines X 1 , X 2 , . . . serve as cathode electrodes, while the column lines Y 1 , Y 2 , . . . Y K  serve as anode electrodes, respectively. The vertical and horizontal start pulsesignals obtained from the vertical and horizontal synchronizing signals aresupplied to a row line scanning circuit 2 which then produces at its pluraloutput terminals driving pulses which are shifted or delayed by one horizontal scanning period, respectively. The driving pulses are then supplied to a row line driving circuit 3 whose driving transistors T X1 , T X2 , . . . are made conductive sequentially in a delayed orshifted manner by one horizontal scanning period, respectively. While, a video signal S VI , such as shown in FIG. 2A, from a video detector circuit (not shown) is supplied to a level detector circuit 4 which divides the level of the video signal S VI  by, for example, 16 steps and delivers at its output terminals t O , t 1 , . . . t 15  output signals in accordance with the divided, or thus sampled, levels. The output signals from the level detector circuit 4 are supplied to a 4-bit coder 5 which produces 4-bit binary coded signals at its output terminals t P , t Q , t R  and t S , respectively, the 4-bit binary signal being a digitally-coded representation of the sampled level of video signal S VI . The respective bit signals obtained at the terminals t P , t Q , t R  and t S  are applied to &#34;write in&#34; memory circuits 6 P , 6 Q , 6 R  and 6 S  each of which comprises flip-flop circuits F 1 , . . . F K  provided in number in correspondence with the column lines Y 1 , . . . Y K , which flip-flop circuits F 1  F K  operate as shift registers, respectively. The shift registers forming the respective &#34;write in&#34; memorycircuits 6 P  to 6 S  are controlled with a clock pulse C W  such as shown in FIG. 2C, respectively. Thus, the video signal S VI  shown in FIG. 2A is sampled in such a manner that, during an effective picture period T A  in the horizontal scanning period, the video signal S VI  is sequentially sampled at every clock pulse C W  following the occurrence of a horizontal start pulse S H  (FIG. 2B). As the sampling operation is performed, 4-bit coder 5, and output terminals t P  to t S  of the 4-bit coder 5, and the thus sampled signals are sequentially shifted from coder 5 into the respective &#34;write in&#34; memory circuits 6 P  to 6 S  from the right to the left laterally in synchronism with the clock pulses C W  and sequentially written or stored therein. When the sampled signals have been written or stored in all the flip-flop circuits F 1  to F K  of the respective &#34;write in&#34;memory circuits 6 P  to 6 S , the stored signals in the flip-flop circuits F 1  to F K  are shifted or transmitted with a memory shiftpulse C T  (shown in FIG. 2D) through AND-circuits A P1  to A PK ,A Q1  to A QK , A R1  to A RK  and A S1  to A SK  to flip-flop circuits F P1  to F PK , F Q1  to F QK , F R1  toF RK  and F S1  to F SK  which form &#34;read out&#34; memory circuits in parallel with one another, simultaneously and at the same time. As shown in FIGS. 2A to 2J, during the next horizontal period or a composite periodof non-effective picture period T B  and the effective picture period T A  i.e. during the next display interval T D , the signals stored in the flip-flop circuits F P1  to F PK , F Q1  to F QK  , F R1  to F RK  and F S1  to F SK  as the &#34;read out&#34; memory circuits are read out with pulse signals P P , P Q , P R  and P S  (shown in FIGS. 2E, 2F, 2G and 2H), whose pulse widths increase inorder as the binary representations 1, 2, 4 and 8 sequentially, the stored signals being read out sequentially through AND-circuts B P1  to B PK , B Q1  to B QK , B R1  to B RK  and B S1  to B SK , respectively. The thus read-out signals from the flip-flop circuits F P  to F S  are derived, at every group corresponding to each of the column lines Y 1  to Y K , supplied through OR-circuits O R1  to O RK , and then supplied to driving transistors T Y1  toT YK  of a column line driving circuit 7, respectively. 
     Accordingly, in such a case that the level of the video signal S VI  at a certain sampling time in a certain effective picture period T A  of ahorizontal scanning period is at, for example, the 7th step in the 16 stepsof 0, 1, 2, . . . 15, this video signal S VI  is coded as  0111  by the 4-bit coder 5. During the next display period T D , the corresponding column line is driven with the coded pulse signal represented by a line-driving signal whose pulse width is 1 + 2 + 4 = 7 shown in FIG. 2I, and a discharging current flows between the corresponding column and row lines to make the brightness at the crossing point therebetween be equal to a brightness level corresponding to the 7th step. When the level of thevideo signal S VI  is at the 10th step, for example, it is coded by the 4-bit coder 5 as  1010 . Then, the corresponding column line is driven during the display period T D  with the line-driving pulse signal whosepulse width is 2 + 8 = 10 shown in FIG. 2J and the brightness at the crossing point between the column line and the corresponding row line becomes equal to a brightness level corresponding to the 10th step. Similarly, the time interval of discharge current flowing between the remaining column and row lines is varied and hence the brightness at the crossing points therebetween is modulated or controlled to display a picture on the display panel 1. 
     With the prior art display system constructed as above, the &#34;read ou&#34; memory circuit corresponding to one column line requires memory devices whose number is same as the number of bits included in the coded representation of the video signal, and accordingly it becomes complicatedin construction and, thus, expensive. Further, the number of leads or conductors for reading out the signals from the &#34;read out&#34; memory circuitslikewise is relatively high. By way of example, if the video signal is encoded with 4 bits as shown in FIG. 1 and there are 300 (K = 300), 4 × 300 = 1200 leads are required for reading out the signals. Similarly, the same number of leads are also necessary for deriving the read-out signals of the respective bits in each group at every column line. Thus, the wiring becomes greatly complicated. 
     An embodiment of the video display system according to the present invention which is free from the defects of the above mentioned prior art system will be described with reference to FIGS. 3, 4A to 4E and 5A to 5U. 
     In FIG. 3, reference numeral 11 designates a display panel which may be of a discharge tube type such as shown in FIG. 1. This display panel 11 comprises a plurality of parallel row lines X 1 , X 2 , . . . and a plurality of parallel column lines Y 1 , Y 2 , . . . Y K  (K being a positive integer) which are perpendicular to the row lines x 1 , X 2 , . . . In this case, the row lines X 1 , X 2 , . . . serve as cathode electrodes and the column lines Y 1 , Y 2 , . . .Y K  serve as anode electrodes, respectively. 
     In this invention, &#34;write in&#34; memory circuits W 1 , W 2 , . . . W K  each of which consists of, for example, 6 bits are provided for the column lines Y 1 , Y 2 , . . . Y K , respectively. The &#34;writein&#34; memory circuits W 1 , W 2 , . . . W K  include 6 flip-flop circuits F A1  to F F1 , F A2  to F F2  . . . F AK  to F FK  are connected in such a manner that they form shift registers in the respective memory circuits W 1 , W 2 . . . . W K  in the longitudinal direction. These flip-flop circuits are further connected such that those corresponding to the respective column lines Y 1 , Y 2 , . . . Y K  at every bit are connected to form lateral shift registers, respectively following the occurrence of a horizontal start pulse S H  (FIG. 2B). As the to form &#34;write in&#34; memory circuits W A , W B , W C , W D , W E  and W F  at the respective bit location. For the respective column lines Y 1 , Y 2 , . . . Y K , there are further provided &#34;read out&#34; memory circuits R 1 , R 2 , . . . R K  of, for example, 2 bits. The &#34;read out&#34; memory circuits R 1 , R 2 , . . . R K  include 2 flip-flop circuits F G1  to F H1 , F G2  to F H2 , . . . F GK  to F HK  each pair of flip-flop circuits being connected to form longitudinal shiftregisters, respectively. The output terminals of the flip-flop circuits F A1  to F AK , which correspond to the lowest or least significant bits of the &#34;write in&#34; memory circuits W 1  to W K , are connected to the input terminals of the flip-flop circuits F H1  to F HK  of the &#34;read out&#34; memory circuits R 1  to R K , respectively to longitudinally transmit the signals from the &#34;write in&#34; memory circuits W 1  to W K  to the &#34;read out&#34; memory circuits R 1  to R K , respectively. The base electrodes of driving transistors T Y1 , T Y2 , . . . T TK  in a column line driving circuit 12 are connectedthrough resistors R G  and R H  to the flip-flop circuits F G1 , F H1  ; F G2 , F H2  ; . . . F GK , F HK , respectively. Inthe illustrated example, the resistors R G  and R H  are selected to be of different resistance vaue. When both groups of the flip-flop circuits F G1  to F GK  and F H1  to F HK  in the &#34;read out&#34; circuits R 1  R K  are in the state of  0 , the transistors T Y1 to T YK  become non-conductive, while when the flip-flop circuit group F G1  to F GK  is in the state of  1  but the other group F H1  to F HK  is in the state of  0 , a current having the amplitude corresponding to the level 1 flows in the transistors T Y1  to T YK , respectively. On the contrary, when the circuit group F G1  to F GK  is  0 but the other group F H1  to F HK  is  1 , a current having the amplitude corresponding to the level 2 flows in the transistors T Y1  to T YK . When both the groups F G1  to F GK  and F H1  to F HK  are  1 , a current having the amplitude corresponding to the level 3 flows in the transistors T Y1  to T YK . This current selection is performed by suitably selecting the resistance values of the resistors R G  and R H . 
     A television signal received by antenna 13 is supplied through a tuner 14 and an IF amplifier circuit 15 to a video detector circuit 16. The video signal S V1  obtained from the video detector circuit 16 is applied to a sync. separator circuit 17 which then produces vertical and horizontal synchronizing signals P V  and P H  as shown in FIGS. 4A and 4B, respectively. The signals P V  and P H  are applied to a start pulsegenerator 18 which then produces vertical and horizontal start pulses S V  and S H  such as shown in FIGS. 4C and 4D, respectively. The start pulses S V  and S H  are supplied to a row line scanning circuit 19 formed of shift registers which produces at its plural output terminals pulses S X  which are shifted or delayed by one horizontal scanning period as shown in FIG. 4E. The pulses S X  are applied to a row line driving circuit 20 to make its driving transistors T X1 , T X2 , . . . conductive sequentially in delayed manner by one horizontal scanning period and thereby to make the row lines or cathode electrodes X 1 , X 2 , . . . nearly ground potential sequentially atevery one horizontal scanning period. 
     The video signals S V1  (refer to FIG. 5A) from the video detector circuit 16 is supplied to a level detector circuit 21 which detects, or samples the video signal S V1  with its level divided into, for example, 64 steps and delivers the divided, or sampled outputs to its output terminals t 0 , t 1 , . . . t 63  in response to the divided levels. The output signals at the terminals t 0 , t 1 , . . . t 63  are supplied to and encoded by a 6-bit coder 22. That is, flip-flop circuits F A1 , F A2 , . . . F AK  are connected to form a lateral shift register, flip-flop circuits F B1 , F B2 , . . . F BK  are connected to form a lateral shift register, and so on, 6-bit binary coded signals at output terminals t A , t B , . . . t F  of the 6-bit coder. The 6-bit binary coded signals are supplied tothe &#34;write in&#34; memory circuits W.sub. A, W B , . . . W F  connected to receive the respective bits. The horizontal start pulse S H  (shown in FIG. 5B) produced by the start pulse generator 18 is further supplied to an oscillator circuit 23 to drive the same in synchronism therewith. The output signal produced by the oscillator circuit 23 is supplied to a gate circuit 24. The horizontal start pulse S H  is also supplied to a gate pulse generator circuit 25 whose output gate pulse in supplied to thegate circuit 24 to control the same. Thus, the gate circuit 24 produces a train of clock pulses C W  during the effective picture period T A  of the horizontal scanning period as shown in FIG. 5C. The clock pulse C W  is supplied to the flip-flop circuits F A1  to F AK , . . . F F1  to F FK  of the &#34;write in&#34; memory circuits W A  to W F ,respectively, to sample the respective bit levels supplied to the respective &#34;write in&#34; memory circuits W A  to W F  by coder 22 and to laterally shift the sampled values through the circuits W A  to W F  from the right to the left sequentially. Thus, the sampled values are written in the &#34;write in&#34; memory circuits W 1  to W K  corresponding to the column lines Y 1  to Y K , respectively. In this case, the effective picture period T A  of the horizontal scanningperiod is selected to be about 16/21 of the horizontal scanning period T H  (16/21 T H .) 
     Another oscillator circuit 26 is also driven by the horizontal start pulse S H  in synchronism therewith and its output is supplied to a gate circuit 27. The horizontal start pulse S H  is also supplied to a gate pulse generator circuit 28 whose output pulse or gate pulse is supplied tothe gate circuit 27 to control the same. Thus, the gate circuit 27 producespulses CR at the time when the &#34;write in&#34; operations to all the &#34;write in&#34; memory circuits W 1  to W K  are completed, that is, immediately after the effective picture period T A . The pusles CR comprise a pair of closely occurring pulses C R1 , a pair of closely occurring pulses C R2  which delayed from the pulses C R1  by 1/21 T H , and a pair of closely occurring pulses C R3  which are delayed from the pulses C R2  by 4/21 T H  sequentially. The pulses C R1 , C R2  and C R3  are supplied to all the flip-flop circuits in the &#34;write in&#34; memory circuits W 1  to W K  and &#34;read out&#34; memory circuits R 1  to R K  as longitudinal or &#34;read out&#34; shift pulses, respectively. Thus, immediately after the end of the effective picture period T A , the signals stored in the flip-flop circuits F A1  to F AK  and F B1  and F BK  are transmitted by the pair of pulses C R1  to the flip-flop circuits F G1  to F GK  and F H1  to F HK , respectively. Thereafter, the signals stored initially in the flip-flop circuits F C1  to F CK  and F D1  to F DK  are transmitted by the pair of pulses C R2  to the flip-flop circuits F G1  to F GK  and F H1  to F HK , respectively, and then the signals stored initially in the flip-flop circuits F E1  to F EK  and F F1  to F FK  are transmitted by the pair of pulses C R3  tothe flip-flop circuits F G1  to F GK  and F H1  to F.sub. HK, respectively. Since the transistors T Y1  to T YK  of the column driving circuit 12 are driven by the flip-flop circuits F G1  to F GK  and F H1  to F HK  as mentioned previously, the transistorsT Y1  to T YK  are driven sequentially with the signals stored in theflip-flop circuits F A1  to F AK  and F B1  to F BK  ; F C1 to F CK  and F D1  to F DK  ; and F E1  to F EK  and F F1  to F FK  in accordance with the pulses C R1 , C R2  and C R3 , respectively. 
     As an example when the encoded 6-bit sampled video signal  1  at the first bit, the discharge current having the amplitude corresponding to the level1 flows during a time period T 1  of 1/21 T H  (refer to FIG. 5E);. That is, flip-flop circuits F A1 , F A2 , . . . F AK  are connected to form a lateral shift register, flip-flop circuits F B1 , F B2 , . . . F BK  are connected to form a lateral shift register, and so on, when the second bit of the encoded signal is  1 , the dischargecurrent having the amplitude corresponding to the level 2 flows during the same time period T 1  (refer to FIG. 5F); and when the third bit of theencoded signal is  1 , the discharge current having the amplitude corresponding to the level 1 flows during a time period T 2  of 4/21 T H  (refer to FIG. 5G) such that the sampled levels of the video signal S VI  are represented as. The operation thereafter will be similarly performed, as shown in FIGS. 5H to 5J. That is, during the display period T D  of one horizontal scanning period T H  consisting of the non-effective horizontal picture period T B  and effective horizontal picture period T A  write-in operations are performed, and after all the write-in operations have been completed, the discharge currents flow having the amplitudes and pulse widths corresponding to the respective bits in the encoded 6-bit sample of the video signal. 
     Accordingly, when the level of the video signal S VI  at a sampling timeis, for example, at the 25th step of the steps 0, 1, 2, . . . 63 and is coded as  011001 , the discharging currents having the amplitudes corresponding to the levels 1, 2 and 1 flow during the time periods T 1 , T 2  and T 3 , respectively, as shown in FIG. 5K. Thus, thebrightness such that the sampled levels of the video signal S VI  are represented as the 25th step. When the sampled level of video signal S VI  sampled is at, for example, the 51st step and is coded as  110011, the discharging current has amplitude corresponding to the level 3 duringthe time period T 1  due to the fact that both the flip-flop circuits F Gn  and F Hn  of the &#34;read out&#34; memory circuit R n  become  1 ,and the time during which the flip-flop circuits F A1  to F AK  are &#34;read out&#34; the current has an amplitude corresponding to the level 3 during the time period T 3  as shown in FIG. 5L. Thus, by integration of the discharging currents the brightness is equal to a brightness level corresponding to the 51st step. 
     At the time that the lost of the signals stored in the &#34;write in&#34; memory circuits W 1  to W K  are transmitted by the read out pulse C R3 to the &#34;read out&#34; memory circuits R 1  to R K , the next effective horizontal picture period T A  occurs and the video signal S VI  in the next horizontal scanning period is sampled in accordance with the above mentioned clock pulse C W  an amplitude corresponding to the level 0 during the time period T 2  due to the fact that these flip-flop circuits F Qn  and F Hn  become  0 . Similarly, the &#34;writein&#34; memory circuits W 1  to W K , to be stored therein similar to theforegoing operation, the sampled signal s encoded and the encoded representation is &#34;written&#34; into, a picture is displayed on the display panel 11. 
     The above description is given for the case where the resistance values of the resistors R G  and R H  are selected to be different from each other such that the amplitudes of the discharge currents resulting from a1  in the flip-flop circuits F H1  to F HK  become twice when these stored signals are read out on a line-by-line basis the flip-flop circuitsF G1  to F GK . However, in an alternative embodiment, the resistancevalues of the resistors R G  and R H  are made equal and the amplitudes of the discharging currents resulting from a  1  in the flip-flop circuits F G1  to F GK  of the &#34;read out&#34; memory circuits R 1  to R K  are equal to the amplitudes of the discharging currentsresulting from a  1  in the flip-flop circuits F Hl  to F HK . In this alternative embodiments, &#34;read out&#34; pulses C Q1 , C Q2  and C Q3  are at the mid times between the pulses C R1  and C R2 , between the pulses C R2  and C R3 , and between the pulses C R3  and C R1 , respectively, as shown in FIG. 5M. These &#34;read out&#34; pulses C Q1 , and C Q2  and C Q3  are produced in a manner similar to the production of pulses C R1  to C R3  and are supplied together with pairs of pulses C R1 , C R2  and C R3  to the flip-flop circuits F G1  to F GK  and F H1  to F HK  of the &#34;read out&#34; memory circuits R 1  to R K . 
     Thus, as shown in FIGS. 5N to 5S, the signal at the first or least significant bit is read out from the flip-flop circuits F G1  to F GK  during a time period T 11  having a time duration of 1/42 T H  in the first half of the time period T 1  ; the signal at the second bit is also read out from the flip-flop circuits F H1  to F HK  during the time period T 11  and at the conclusion of time period T 11  the latter signal is transmitted to the flip-flop circuitsF G1  to F GK  and then read out therefrom during a next period T 12  also having a time duration of 1/42 T H . The signals at the third and fourth bits, and those at the fifth and sixth bits are similarlytreated, respectively, and the discharging currents having amplitudes determined by the signals at the respective bits flow during time periods corresponding to the relative significance of the respective bits. 
     As an example, when the level of the sampled video signal S VI  is at, for example, the 25th step and is coded as  011001 , the current having the amplitude corresponding to the level 1 flows during the time periods T 11 , T 21 , T 22  and T 31 , as shown in FIG. 5T, and the brightness becomes 25th step as its integrated value. As another example, if the level of the sampled video signal the 51st step and is coded as 110011 , the discharging current having the amplitude corresponding to thelevel 2 flows during the time period T 11  due to the fact that both of the flip-flop circuits F Gn  and F Hn  of the &#34;read out&#34; memory circuit R n  exhibit the state of  1 . 
     At the conclusion of period T 11 . &#34;read out&#34; pulse C Q1  is applied to flip-flop circuits F Gn  and F Hn  so that during period T 12 the discharging current amplitude corresponds to the level 1. At the conclusion of period T 12 , &#34;read out&#34; pulses C R2  transfer the signals initially stored in flip-flop circuits F Cn  and F Dn  into flip-flop circuits F Gn  and F Hn . Since these signals exhibit the states 0 and 0, respectively, the discharging current amplitude during period T 21  corresponds to the level 0. At the conclusion of period T 21 , &#34;read out&#34; pulse C Q2  transfers the contents of flip-flop circuit F Hn  into flip-flop circuit F Gn . Thus, during the period T 22  the discharging current amplitude corresponds to the level 0. At the conclusion of period T 22 , &#34;read out&#34; pulses C R3  transfer thesignals initially stored in flip-flop circuits F En  and F Fn  into flip-flop circuits F Gn  and F Hn . Since these signals exhibit the states  1  and  1 , respectively, the discharging current amplitude duringperiod T 31  corresponds to the level 2. At the conclusion of period T 31 , &#34;read out&#34; pulse C Q3  transfers the contents of flip-flop circuit F Hn  into flip-flop circuit F Gn . Thus, during the period T 32  the discharging current amplitude corresponds to the level 1. This discharging current is shown in FIG. 5U. Since brightness is determined by integrating the discharging current, the brightness for thissample of the video signal is equal to a level corresponding to the 51st step. 
     With the video display system according to the present invention described above, even if the video signal is coded to be, for example, 6 bits, a 2-bit &#34;read out&#34; memory circuit is sufficient, so that the construction orthe display system becomes much simplified and inexpensive over that shown in, for example, FIG. 1. Further, the signal transmission from the &#34;write in&#34; memory circuit to the &#34;read out&#34; memory circuit is carried out sequentially in a series manner. Only the signals from the two memory devices of the &#34;read out&#34; memory circuit are transmitted in parallel, so that the wiring therebetween becomes much simple. 
     In the illustrated embodiment of the invention, the video signal is coded to be 6 bits, and then each of the &#34;write in&#34; memory circuits stores a 6 bit signal and each of the &#34;read out&#34; memory circuits is stores 2 bits. However, the present invention need not be restricted to this encoding scheme. That is, the present invention can be applied to the case where the video signal is sampled and coded with m x n bits (m and n being both positive integers); each of the &#34;write in&#34; memory circuits stores m x n bits; each of the &#34;read out&#34; memory circuits stores m bits; the contents of the &#34;write in&#34; memory circuits are transferred to the &#34;read out&#34; memorycircuits m bits at a time and sequentially from lower or least significant bits to higher or most significant bits with different transfer intervals corresponding to the weight of the coded or most significant; and then read out. 
     Having described an illustrative embodiment of the invention, it will be apparent that many modifications and variations could be effected therein by one skilled in the art without departing from the spirit and scope of the novel concepts of the invention. Therefore, it is intended that the appended claims be construed to cover all such modifications and variations.