Abstract:
A buffer circuit, which supplies current to a capacitive load, has a first circuit for reducing the power supply charging current to the capacitive load during switching intervals. The first circuit includes a charge storage device precharged between inverter switching intervals to produce at least a portion of the load charging current during the switching intervals. A second circuit includes a switching element connected between the power supply and the capacitive load to electrically connect the power supply through the second circuit to the load at a selected time in the switching interval to supplement the charging current produced by the charge storage device.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to an inverter or switching circuit making use of complementary insulated gate field effect transistors (hereinafter abbreviated as CMOSFET&#39;s). More particularly, it relates to an inverter circuit with a capacitive load connected to the output terminal thereof in which a heavy transient current flows from a power supply under a transient condition where an input signal is changed to invert the inverter output. 
     Since an inverter circuit using CMOSFET&#39;s (hereinafter abbreviated as CMOS inverter) consumes little power in the steady state condition, its use in large-scale integrated circuits (thereinafter abbreviated as IC) is desirable. Under the transient condition, however, a considerably large power supply current (hereinafter abbreviated as I DD ) flows through the CMOS inverter due to a charging current flowing to a capacitive component of the load. Accordingly, the peak value of I DD  in the CMOS inverter is large during the transient period. Therefore, it is necessary to take measures, such as lowering the impedance of power supply wirings to the CMOS inverter to reduce this transient current. But such a measure would deteriorate a valuable feature of the CMOS circuit; namely, that it can use fine wirings because of the low steady state power consumption. This problem becomes more remarkable in a memory IC where a large number of address inverters operate simultaneously. For instance, in a 64K-bit memory, an address input is 16-bits, which means that at least 16 address inverters operate simultaneously in response to 16 address input signals applied in parallel. In that case, I DD  is multiplied by a factor of 16, causing an extremely large peak current to flow from the power supply of this memory IC. Consequently, a noise is generated in the power supply lines, causing many faults in the operation of the memory IC. 
     It has been proposed to reduce the peak current by prolonging the CMOS inverter switching time to thereby gradually charge the load capacitance. However, this method has a drawback that speed-up of the whole IC is prevented because of the prolonged response time of the inverter. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide an inverter circuit, in which the peak value of the load capacitance charging current component of the power supply current can be largely reduced while maintaining high-speed operation. 
     According to one feature of the present invention, there is provided an inverter circuit responsive to an input signal for outputting an inverted signal of the input signal, with a first auxiliary circuit connected to the inverter circuit. The first auxiliary circuit includes an auxiliary capacitor which is charged at a time other than the transient time when the output transfers from the low level to the high level (e.g. when the input signal is &#34;1&#34; (or &#34;0&#34;) level), and is discharged during the transient period when the input signal is changed from the low level to the high level. Since the discharge current from the auxiliary capacitor is added to the power supply current from the power supply for charging the capacitive load in the transient period, the peak power supply current during the transient period can be greatly reduced. The power supply current for charging the auxiliary capacitor flows at a time other than the transient period and contributes to the reduced peak current. 
     According to another feature of the invention, a second auxiliary circuit is added to the inverter circuit in parallel with the first auxiliary circuit to feed a part of the output current of the inverter circuit at least after the discharging current from the auxiliary capacitor starts to flow and favorably after the mentioned discharging current ends during the transient period. 
     The inverter circuit may comprise a first P-channel type field effect transistor (hereinafter abbreviated as Pch-FET) and a first N-channel type field effect transistor (hereinafter abbreviated as Nch-FET) connected in series between the two power supply terminals, the gates of these FET&#39;s being commonly connected to an input terminal, and the common junction point therebetween being used as an output terminal. The first auxiliary circuit may include second, third and fourth Pch-FET&#39;s (or Nch-FET&#39;s) connected in series between one of the power supply terminals and the output terminal of the inverter circuit with their respective gates connected to the other power supply terminal, the output terminal of the inverter circuit and the input terminal of the inverter circuit, respectively. An auxiliary capacitor is inserted between the common junction point between the second and third FET&#39;s and the other power supply terminal. The second auxiliary circuit may include a fifth Pch-FET (or Nch-FET) inserted between the one of the power supply terminals and the output terminal of the inverter circuit and a delay circuit coupled between the input terminal of the inverter circuit and the gate of the fifth FET. The second auxiliary circuit may further include a sixth Pch-FET (or Nch-FET) inserted between the drain of the fifth FET and the output terminal of the inverter circuit and having its gate connected to the input terminal of the inverter circuit. With the first and second auxiliary circuits, the inverter circuit according to this invention can reduce the peak value of the capacitive load charging current component of the power supply current as compared to the prior art inverter circuit, while maintaining a high-speed operation. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a basic inverter circuit in the prior art making use of CMOSFET&#39;s. 
     FIG. 2 illustrates the waveforms of an input signal φ IN , an output signal φ OUT , and a charging current component I DDL  of the power supply current I DD  as functions of time for the inverter circuit shown in FIG. 1, 
     FIG. 3 is a circuit diagram showing one preferred embodiment of the present invention, 
     FIG. 4 illustrates the waveforms of the input voltage φ IN  the output voltage φ OUT  and the charging current component I DDL  of the power supply current as functions of time as the inverter circuit of FIG. 3 goes from the &#34;1&#34; level to &#34;0&#34; level. 
     FIG. 5 illustrates the waveforms of the input voltage φ IN , the output voltage φ OUT  and the charging current components of the power supply current as functions of time as the inverter circuits of FIGS. 3 and 6 are changed from &#34;0&#34; level to &#34;1&#34; level. 
     FIG. 6 is a circuit diagram showing another preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Referring to FIG. 1, a prior art inverter circuit comprises an Nch-FET Q 1  and a Pch-FET Q 2  with their drains connected in common to form an output terminal 3. The source of the FET Q 1  is connected to a V SS  power supply terminal (in the illustrated example, to the ground terminal) and the source of the FET Q 2  is connected to a V DD  power supply terminal 4 (in the illustrated example, V DD  represents a positive voltage). The gates of both FET&#39;s are connected in common and form an input terminal 2. It is to be noted that a load capacitor C L  is present between the output terminal 3 and the ground terminal. 
     Referring also to FIG. 2, when the input signal φ IN  is at &#34;1&#34; level (in the illustrated example, a high voltage V DD  level) at a time t o , the Nch-FET Q 1  is ON, and hence the output signal φ OUT  maintains &#34;0&#34; level (V SS  level). Since the Pch-FET Q 2  is OFF at this time, the power supply current I DD  does not flow. Subsequently, the input signal φ IN  begins to transfer from the &#34;1&#34; level to the &#34;0&#34; level (in the illustrated example the low voltage V SS  is the 0 volt level), and when the voltage of the input signal has lowered to V DD  -|V TP  | (V TP  : a threshold voltage of the Pch-FET Q 2 ) at a time t 1 , the Pch-FET Q 2  is turned ON and a power supply current I DD  begins to flow. As a result, the voltage of the output signal φ OUT   begins to rise, determined by the capability ratio between the Nch-FET Q 1  and the Pch-FET Q 2 . As the voltage of the output signal φ OUT  rises, the load capacitor C L  is driven, and a charging current I DDL  flows from the V DD  power supply terminal through the Pch-FET Q 2  into the load capacitor C L . Therefore, the power supply current I DD  which is the sum of the charging current I DDL  and a current I DDO  flowing through the FET Q 1  to the ground becomes large. Then, the input signal φ IN  approaches the &#34;0&#34; level, and when the voltage reaches V TN  (a threshold voltage of the Nch-FET Q 1 ), the Nch-FET Q 1  is turned OFF, and the power supply current component flowing through the Nch-FET Q 1  (I DDO ) stops. When the input signal φ IN  reaches &#34;0&#34; level at a time t 2 , the output signal φ OUT  also reaches &#34;1&#34; level, so that the I DDL  also stops flowing. Thus the charging current component I DDL  has a nearly symmetric waveform with a large peak value. The peak value of the charging current I DDL  become larger as the load capacitor C L  is increased. As described previously, an important problem to be solved is how best to reduce the peak value of this I DDL . 
     With reference to FIG. 3, the circuit of a preferred embodiment of the present invention comprises a basic inverter circuit 11 which includes a first Pch-FET Q 12  and a first Nch-FET Q 11  connected in series at an output terminal 17. The source of the Nch-FET Q 11  is connected to V SS  terminal (the ground terminal in this example) and the source of the Pch-FET Q 12  is connected to a V DD  power supply terminal 16. The gates of the Nch-FET Q 11  and the Pch-FET Q 12  are both connected to an input terminal 15. A first auxiliary circuit 12 is added to the inverter circuit 11, which in turn includes second, third and fourth Pch-FET&#39;s Q 14 , Q 15  and Q 16  connected in series between the V DD  power supply terminal 16 and the output terminal 17. The respective gates of Q 14 , Q 15  and Q 16  are connected to the input terminal 15, the output terminal 17, and the ground terminal, respectively. The first auxiliary circuit further includes an auxiliary capacitor C A  inserted between the common junction point N2 of the Pch-FET&#39;s Q 15  and Q 16  and the ground terminal. A second auxiliary circuit 13 is also added, which includes a fifth Pch-FET Q 13  inserted between the V DD  power supply terminal 16 and the output terminal 17 and a delay circuit 14 inserted between the input terminal 15 and the gate of Q 13 . The delay circuit 14 is used to delay the input signal φ IN  by a predetermined period. Since precision is not required, the delay circuit 14 can be easily constructed using known techniques. 
     Now description will be made of the operation of this circuit when the input signal φ IN  transfers from &#34;1&#34; level (V DD ) to the &#34;0&#34; level (ground), with reference to FIG. 4. Since the basic inverter circuit 11 has the same construction as the circuit in the prior art shown in FIG. 1, its operation is basically the same as that of the prior art circuit. 
     At first, when the input signal φ IN  is at the &#34;1&#34; level (V DD ) at a time between t o  and t 11 , the Pch-FET&#39;s Q 15  and Q 16  of the first auxiliary circuit 12 are ON and the Pch-FET Q 14  is OFF. Hence the auxiliary capacitor C A  is charged via the Pch-FET Q 16  by V DD  and stores electric charge therein. Accordingly, the charging current I DDA  for this capacitor C A  flows from the V DD  power supply terminal 16 as a component of the power supply current I DD , during the period of time t o  to t 11 . At this moment, the Nch-FET Q 11  is ON and the Pch-FET&#39;s Q 12  and Q 13  are OFF. Therefore, the output voltage φ OUT  at the output terminal 17 is at the &#34;0&#34; level, and the power supply current I DDO  through the Nch-FET Q 11  and the charging current I DDL  for the load capacitor C L  are both zero. 
     Within the period of t 0  to t 11 , the input signal φ IN  starts to fall. When the voltage of the input signal φ IN  is lowered to V DD  -|V TP  | at the time t 11 , the Pch-FET Q 12  and the Pch-FET Q 14  are turned ON, and hence a current I DDO  through the Pch-FET Q 12  and the Nch-FET Q 11  and a charging current I DDL1  through the Pch-FET Q 12  and load capacitor C L  for charging the load capacitor C L  begin to flow. Furthermore, the electric charge previously stored in the auxiliary capacitor C A  begins to discharge as a part of the charging current for the load capacitor C L  through the Pch-FET Q 14  (this component being represented by I DDL2 ). Since this discharge current I DDL2  is based on the discharge of electric charge that has been preliminarily stored in the auxiliary element C A , an increment of the power supply current I DD  that is necessary for I.sub. DDL2 after the time t 11  is very small. If the conductance of the Pch-FET Q 16  is chosen less than about 1/10 of that of the Pch-FET Q 12 , then the I DD  component passing through the Pch-FET Q 16  is very small, and therefore it can be neglected. Moreover, if the auxiliary capacitor C A  is chosen nearly the same size as the load capacitor C L , then about one-half of the charging current I DDL  can be obtained from I DDL2 . 
     Subsequently, the voltage of the input signal φ IN  is further lowered after t 11  and accordingly the voltage of the output signal φ OUT  rises, and when the output voltage value reaches about V DD  /2 at a time t 12 , the input signal φ&#39; IN  delayed by the delay circuit 14 in the second auxiliary circuit is applied to the Pch-FET Q 13 , so that the Pch-FET Q 13  is turned ON and sends out an output current to the output terminal 17 which forms another part of the charging current for the load capacitor C L  (this component being called I DDL3 ). As a result the power supply current I DD  now includes the I DDL3  component. On the other hand, the potential at the node N 2  which serves as one terminal of the auxiliary capacitor C A  becomes nearly the same level as the φ OUT  when the voltage of the output signal φ out  exceeds V DD  /2, and hence the Pch-FET Q 15  is turned OFF, so that the charging current I DDL2  from the auxiliary capacitor C A  is eliminated. Therefore, at this time the charging current for the load capacitor C L  is comprised of two components; that is, the I DDL1  passing through the Pch-FET Q 12  and the I DDL3  passing through the Pch-FET Q 13 . This I DDL3  component compensates for the loss of the above-described I DDL2  component to promote charging of the load capacitor C L  and serves to quickly raise the voltage of the output signal φ OUT . Therefore, it is favorable to select the conductance of the Pch-FET Q 13  larger than that of the Pch-FET Q 12 . 
     Next, when the input signal φ IN  approaches the &#34;0&#34; level and its voltage becomes equal to or lower than V TN , then the Nch-FET Q 11  is turned OFF, and hence the I DDO  component passing through the Nch-FET stops. Then, the input signal φ IN  reaches the &#34;0&#34; level and the output signal φ OUT  reaches the &#34;1&#34; level at a time t 13 , and as a result, the I DDL1  component passing through the Pch-FET Q 12  as well as the I DDL3  component passing through the Pch-FET Q 13  are also eliminated. 
     As will be apparent from the above description, in the circuit of the illustrated embodiment, the charging current I DDL  for the load capacitor C L  is formed in such a manner that until the voltage of the output signal φ OUT  becomes nearly equal to V DD  /2, the charging current is comprised of the I DDL1  passing through the Pch-FET Q 12  and the discharging current I DDL2  of the auxiliary capacitor C A  which has been preliminarily charged, and after the output signal φ OUT  nearly exceeds V DD  /2, the I DDL2  is eliminated and instead the I DD3  passing through the Pch-FET Q 13  is newly added. Consequently, the load capacitor charging current component I DDL  of the power supply current of the circuit would flow over the entire region of operation, and its peak value during the period t 11  to t 13  becomes very small as shown in FIG. 4. The extent of this reduction of the peak value depends upon the design of the first and second auxiliary circuits such as the magnitude of the auxiliary capacitor C A  and the conductance of the Pch-FET Q 13 . However, it is quite easy to reduce the peak value of the charging current to 1/2 or less of the peak value in the prior art inverter circuit. 
     Furthermore, since those auxiliary charging currents can be subjected to appropriate adjustment by varying the delay characteristics of the delay circuit 14 in the second auxiliary circuit 13 so as to meet the response time of the circuit, there is no need to prolong a response time of the inverter circuit 11, and the response time may be rather shortened by selecting appropriate timing. 
     Now description will be made of the case where the input signal transfers from the &#34;0&#34; level to the &#34;1&#34; level, with reference to FIG. 5 which shows waveforms of the input signal φ IN , the output signal φ OUT  and the power supply current I DD  for this case. 
     At first, during the period t 0  to t 20 , when the input signal φ IN  is at the &#34;0&#34; level (ground), the Pch-FET&#39;s Q 12 , Q 13 , Q 14  and Q 16  are ON and the Nch-FET Q 11  and the Pch-FET Q 15  are OFF. Accordingly, the auxiliary capacitor C A  is charged, and a power supply charging current I DDA  flows. 
     Next, the input signal φ IN  starts to rise at a time t 20 . When it rises up to V TN  at a time t 21 , the Nch-FET Q 11  is turned ON and the discharging current of the load capacitor C L  begins to flow through the Nch-FET Q 11 . Furthermore the power supply current I DDO  flows through the Pch-FET Q 12  and the Nch-FET Q 11 , and the power supply current I DDO  &#39; flows through the Pch-FET Q 13  and the Nch-FET Q 11 . At this moment, since the Pch-FET Q 15  is kept OFF, only the I DDA  flows through the first auxiliary circuit. 
     Subsequently, when the input signal φ IN  reaches V DD  -|V TP  |, at a time t 23 , the Pch-FET Q 13  is turned OFF and the I DDO  stops flowing, but since the voltage of the delayed signal φ IN  for the input signal φ IN  which is a driving voltage for the Pch-FET Q 13  does not rise as shown in FIG. 5, the Pch-FET Q 13  is still kept ON, and so the I DDO  &#39; continues to flow. Thereafter when the φ&#39; IN  becomes V DD  -V TP  at a time t 24 , the Pch-FET Q 13  is turned OFF and the I DDO  &#39; stops flowing. The input signal φ IN  reaches the &#34;1&#34; level, and the output signal φ OUT  reaches the &#34;0&#34; level. 
     In other words, in the transient period when the input signal φ IN  transfers from the &#34;0&#34; level to the &#34;1&#34; level, the I DDO  &#39; passing through the Pch-FET Q 13  is added to the power supply current I DDO  which flows together with the discharge current of the load capacitor C L  in the circuit known in the prior art, and therefore, the overall power supply current I&#39; DD  takes the form shown in FIG. 5. As described, the circuit of the illustrated embodiment of FIG. 3 has a problem that although the peak value of the load capacitor charging current component I DDL  of the power supply current I DD  can be greatly reduced when the input signal φ IN  transfers from the &#34;1&#34; level to the &#34;0&#34; level, the power supply current I DDO  &#39; caused by the second auxiliary circuit is added to the power supply current when the input signal φ IN  transfers from the &#34;0&#34; level to the &#34;1&#34; level. 
     The circuit of another preferred embodiment of the present invention shown in FIG. 6 solves the above-mentioned problem. The only difference from the circuit shown in FIG. 3 and described previously resides in that the second auxiliary circuit 13&#39; includes another Pch-FET Q 17  inserted between the drain of the Pch-FET Q 13  and the output terminal 17 and having its gate connected to the input terminal 15. In this circuit of the modified embodiment, the Pch-FET Q 17  is turned OFF in response to the input signal φ IN  and the I DDO  &#39; also ceases to flow at the same time when I DDO  ceases to flow through Q 12 . Therefore, the I DD  in this modified embodiment becomes small as indicated by I&#34; DD  in FIG. 5. 
     It is to be noted that in the above-described embodiments, the conductivity type of the respective FET&#39;s can be changed if necessary. For instance, in place of the Pch-FET an Nch-FET can be used for the FET Q 14 , and an inverted input signal φ IN  would then be applied to the gate of this FET. The Pch-FET&#39;s and Nch-FET&#39;s may be replaced by Nch-FET&#39;s and Pch-FET&#39;s, respectively, with the terminals of the power supply voltage being reversely connected.