Abstract:
Complementary Electrical Erasable Programmable Read Only Memory (CEEPROM) is disclosed. CEEPROM cell comprises a pair of non-volatile memory elements and one access transistor. The two elements of the non-volatile memory pair are configured to be one with high electrical conductance and the other with low electrical conductance. The positive voltage V DD  for digital value “1” and ground voltage V SS  for digital value “0” are connected to the two input nodes of the two non-volatile elements respectively after configuration. The digital signal either V DD  or V SS  passed through the high conductance non-volatile memory element in the pair is directly accessed by the access transistor without applying a sense amplifier as the conventional EEPROM would require. Without sense amplifiers, the digital data in CEEPROM can be fast accessed. The power consumption and the silicon areas required for sense amplifiers can be saved as well.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to reprogrammable non-volatile memory devices able to output stored digital information “1” or “0” without applying a sense amplifier. In particular, Complementary Electrical Erasable Programmable Read Only Memory (CEEPROM) is configured to a static stored signal of either V DD  (“1”) or V SS  (“0”) in the memory cell. The digital data in the memory cell are directly accessed by an access transistor without passing through a sense amplifier. 
     2. Description of the Related Art 
     In the digital world of electronic systems, Complementary Metal-Oxide Semiconductor (CMOS) process becomes the most popular fabrication process for Application Specific Integrated Circuit (ASIC). An ASIC contains the specific functionality of a device or a system on a single Integrated Circuit (IC) or a chip. Changes for the specific functionality or configurations are required in many applications. For example, the initial programming and configuring a microprocessor require a programmable and non-volatile memory to store the programmed instructions. The programmed instructions shall be allowed to change any time without changing the hardware during developments. This requirement for electronic systems is done by Electrically Erasable Programmable Read-Only Memory (EEPROM) device. 
     The conventional semiconductor EEPROM devices usually consist of a charge storing memory cell  120  and an access MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor)  110  as the schematic shown in  FIG. 1 . The charge storing memory cell  120  is a MOSFET with a layer of charge storage material  122  under the control gate  124  and above the channel surface of a MOSFET. The amounts of charges in the storing layer  122  can affect the threshold voltage applied to the control gate  124  to turn on the channel of the MOSFET memory cell. For instance, the threshold voltage of N-type semiconductor memory cell shifts to a higher voltage from storing electrons (negative charge) in the charge storage layer. While the threshold voltage of P-type semiconductor memory cell shifts to a lower voltage from storing electrons (negative charge) in the charge storage layer. By injecting into the storing layer of the semiconductor memory cell to cause threshold voltage changes, the electrical conductance of the semiconductor memory cell is also altered, when applying a voltage bias to the control gate of the semiconductor memory cell. The semiconductor memory cells become non-volatile, if the charges in the storing layer can be retained for a long period of time (&gt;10 years for a typical semiconductor non-volatile memory). If a non-volatile memory element can perform the cycles of erase/programming operations the non-volatile memory is Multiple Times Programming Non-Volatile Memory (MTPNVM). Usually, the numbers of erase/programming cycling for a semiconductor non-volatile memory are between thousands to millions times. 
     In the conventional scheme of reading out a stored bit in EEPROM as depicted in  FIG. 2 , the source and drain electrodes of the semiconductor memory cell  120  are connected to ground node and the source electrode of the access transistor  110 , respectively. The drain electrode of the access transistor  110  is then attached to a bitline. The control gate of semiconductor memory cell  120  is biased with a constant voltage V CG . The access transistor  110  is activated to attach to the bitline by applying a voltage bias V G . A current source configured with a constant voltage bias V R  to one node of a load device  220  and the other node connected to the bitline passes electrical current I CELL  through the access transistor  110  to the ground node of the semiconductor memory cell  120 . The cell current I CELL  flowing through the memory cell varies according to the conductance of the memory cell altered by the threshold voltage change with a constant control gate voltage bias V CG . The cell current I CELL  is then proportionally amplified by a current mirror circuitry  210 . By comparing the amplified cell current with a reference current I REF , the bit information (“1” and “0”) is read out by a current comparator  230 . That is, the output signal of the comparator  230  is V DD  (logic“1”) for amplified cell current greater than the reference current or V SS  (logic “0”) for amplified cell current less than reference current and vise versa. Since the DC currents including the amplified cell currents (cell current+mirror current) and the reference current are compared in the conventional readout scheme the required total sensing power is high. The DC current consumption is usually greater than 100 s μA per cell for a typical semiconductor non-volatile memory not including the switching currents of outputting “1” or “0”. 
     In this invention we apply two non-volatile memory elements and one access transistor to form a Complementary Electrical Erasable Programmable Read Only Memory (CEEPROM) cell. The CEEPROM outputs digital signals V DD  (“1”) and V SS  (“0”) without going through a sense amplifier. The digital datum from the CEEPROM can be fed into to digital circuitries directly. The CEEPROM can provide fast-access, simple, low power, and cost effective solutions for embedded re-configurable digital integrated circuitries. 
     SUMMARY OF THE INVENTION 
     CEEPROM cell  300  comprises two re-configurable non-volatile elements  310  and  320  and one access transistor  340  as shown in  FIG. 3 . The re-configurable non-volatile elements  310  and  320  can be repeatedly programmed and erased to two distinct “on” and “off” states for MTP application. The “on” state and “off” state for the non-volatile elements  310  and  320  indicate the high and low conductance of the non-volatile elements, respectively. The input node  311  of non-volatile element  310  and the input node  321  of non-volatile element  320  are connected to the positive voltage supply V DD  and the ground voltage V SS  for digital circuitries, respectively. The output nodes of two non-volatile elements  310  and  320  are connected to the input node  341  of the access transistor  340 . The access transistor  340  is turned on to pass the voltage signal at node  341  to the output node  350  by applying a voltage bias V G  larger than (V thn +V DD ) to the gate electrode  342  of access transistor  340 , where V thn  is the threshold voltage of the access transistor  340 . In the configuration mode, the complementary non-volatile elements  310  and  320  is always configured to one “on” and the other “off”. For the case in  FIG. 3 , non-volatile element  310  and non-volatile element  320  are programmed (erased) to “on” and “off” state, respectively for storing bit “1”. While non-volatile element  310  and non-volatile element  320  are programmed (erased) to “off” and “on” state, respectively for storing bit “0”. 
     Since CEEPROM  300  outputs digital signals “1” (V DD ) and “0” (V SS ), CEEPROM  300  does not require sense amplifier and current comparator to convert the responding cell currents of the non-volatile elements into digital voltage signals. The output signals of CEEPROM  300  can be directly fed into digital circuitries. CEEPROM  300  offers excellent compatibility with digital circuitries. Although CEEPROM  300  requires two non-volatile memory elements  310  and  320  for the complementary pair, one element more than the conventional EEPROM, the omission of sense amplifier and current comparator circuitry may result in more silicon area saving for small density embedded digital circuit applications. It is also emphasized that the active and standby power for CEEPROM  300  is the most significant saving without the sense amplifier and current comparator circuitries. 
     In another aspect of CEEPROM, the CEEPROM  300  can be applied in the Multiple Times Programmable (MTP) non-volatile devices in the typical structure of one non-volatile element and one access transistor such as semiconductor non-volatile memory device (conventional EEPROM), Phase Change Memory (PCM), Programmable Metallization Cell (PMC), Magneto-Resistive Random Memories (MRAM), Ferroelectric Random Access Memory (FRAM), Resistive Random Access Memory (RRAM), and Nano-Random Access Memory (NRAM), without having current sense amplifier reading out digital signals. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a better understanding of the present invention and to show how it may be carried into effect, reference will now be made to the following drawings, which show the preferred embodiment of the present invention, in which: 
         FIG. 1  shows the schematic of a conventional Electrical Erasable Programmable Read Only Memory (EEPROM). 
         FIG. 2  shows the readout schematic for a conventional Electrical Erasable Programmable Read Only Memory (EEPROM). 
         FIG. 3  shows the general schematics of CEEPROM consisting of a pair of complementary non-volatile elements, and one access transistor according to the invention. 
         FIG. 4  shows one embodiment of CEEPROM using two N-type semiconductor non-volatile memory elements and one N-type access MOSFET (a) schematic; (b) voltage biases at the nodes of a CEEPROM cell for configuring bit “0”; (c) voltage biases at the nodes of a CEEPROM cell for configuring bit “1”; (d) voltage biases at the nodes of a CEEPROM cell in normal read mode after configuration. 
         FIG. 5  shows one embodiment of CEEPROM using two P-type semiconductor non-volatile memory elements and one N-type access MOSFET (a) schematic; (b) voltage biases at the nodes of a CEEPROM cell for configuring bit “0”; (c) voltage biases at the nodes of a CEEPROM cell for configuring bit “1”; (d) voltage biases at the nodes of a CEEPROM cell in normal read mode after configuration. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following detailed description is meant to be illustrative only and not limiting. It is to be understood that other embodiment may be utilized and element changes may be made without departing from the scope of the present invention. Also, it is to be understood that the phraseology and terminology used herein are for the purpose of description and should not be regarded as limiting. Those of ordinary skill in the art will immediately realize that the embodiments of the present invention described herein in the context of methods and schematics are illustrative only and are not intended to be in any way limiting. Other embodiments of the present invention will readily suggest themselves to such skilled persons having the benefits of this disclosure. 
     The schematic for a CEEPROM cell  400  consisting with a pair of complementary N-type semiconductor non-volatile memory elements  410  and  420 , and one access N-type MOSFET  440  is shown in  FIG. 4   a . The complementary N-type semiconductor non-volatile memory elements  410  and  420  are controlled by the same control gate  430 . The source electrodes  401  and  402  of the complementary N-type semiconductor non-volatile memory elements  410  and  420  form voltage bias input nodes for positive voltage supply V DD  and ground voltage V SS , respectively. The drain electrodes  441  of the complementary N-type semiconductor non-volatile elements  410  and  420  are connected together to the source electrode  441  of the N-type access MOSFET  440 . A voltage bias V G  greater than (V DD +V thn ) is applied to the gate electrode  442  of the N-type access MOSFET  440  to pass the signals at node  441  to the output node  450  of the CEEPROM  400 , where V thn  is the threshold voltage of the access transistor  440 . 
     Before configuring the complementary N-type semiconductor non-volatile memory elements  410  and  420 , the N-type semiconductor non-volatile memory elements are initially in the erased state, where the N-type semiconductor non-volatile memory elements have lower threshold voltages to be turned on. A voltage bias below the lower threshold voltages must be applied to the control gate  430  to deactivate devices  410  and  420  in the erased state to prevent large current passing the complementary N-type semiconductor non-volatile memory elements  410  and  420  from positive voltage V DD  to ground V SS . The N-type semiconductor non-volatile memory elements  410  and  420  are configured by programming either one of the two complementary memory elements to a higher threshold voltage by injecting electrons to its charge storing material. For instance, Hot Carrier Injection (HCI) can be applied to inject electrons into the storing material of an N-type semiconductor non-volatile memory element. 
       FIG. 4   b  and  FIG. 4   c  are the voltage biases at the electrodes of the CEEPROM by applying HCI programming for configuring bit “0” and bit “1”, respectively. During configuring a storing bit into the CEEPROM cell, a high voltage bias V DH  (3.5V˜5V) are passed to the drain electrodes  441  of semiconductor non-volatile memory elements  410  and  420  by applying a gate voltage V GPH  higher than (V DH +V thn ) to the gate electrode  442  of access transistor  420 . For configuring bit “0” as shown in  FIG. 4   b , the input node  401  of element  410  is connected to the ground voltage V SS  by a switch SW 1  according to a control signal CS 1  while the input node  402  of element  420  is floating by a switch SW 2  according to a control signal CS 2 . When a voltage pulse with amplitude V CGH  (5V˜8V) are applied to the control gate  430  for about several μs, element  410  is turned on to flow electron current from the input node  401  toward the drain electrode  441  of element  410 . The hot carriers (electrons and holes) are generated near the depletion region of the drain electrode of element  410  by the impacted ionization of injecting electron current from the input node  401 . Consequently the energetic hot electrons are injected into its charge storing material. The threshold voltage of N-type semiconductor non-volatile memory element  410  is thus shifted to a higher threshold voltage by electrons in the storing material. On the other hand, since the input electrode  402  of element  420  are floating without connecting to any voltage bias, the voltage bias V DH  at the drain node  441  is directly passed to the input node  402  of element  420  with the application of control gate voltage pulse V CGH . No hot carriers in element  420  are generated. The threshold voltage of N-type semiconductor non-volatile memory element  420  remains the same as its erased threshold voltage. The programming process can take place simultaneously for configuring bit “1” in another CEEPROM cell with floating node  401  and grounded node  402  as shown in  FIG. 4   c.    
     In the normal read mode after configuration as shown in  FIG. 4   d , the input node  401  of element  410  is connected to the positive voltage supply V DD  by the switch SW 1  according to the control signal CS 1  and the input node  402  of element  420  is connected to the ground voltage V SS  by the switch SW 2  according to the control signal CS 2  for the digital circuitry. A constant voltage bias V CG  (wherein (V DD +V the )&lt;V CG &lt;(V SS +V thp )) is applied to the control gate  430 , that is, V CG  can turn on the N-type non-volatile memory element with low threshold voltages (erased) V the  to pass V DD , and turn off” the N-type non-volatile memory element with high threshold voltages (programmed) V thp . The voltage potential at the node  441  is either V DD  for bit “1” or V SS  for bit “0” after configuration. To access the bit information of CEEPROM  400 , the voltage signal of either V DD  or V SS  is passed to the output node  450  of the CEEPROM by applying a voltage bias V GP  greater than (V DD +V thn ) to the gate  442  of access transistor  440 . The voltage signal at the output node  450  can be directly applied to logic gates in the digital circuitries. 
     In the standby read mode with the access transistor  440  “off”, the total steady current flowing from V DD  to V SS  through the complementary pair of “on” and “off” (or “off” and “on”) non-volatile memory elements is the “off” leakage current for a single non-volatile memory element. Usually the “off” leakage current for an N-type semiconductor non-volatile memory element could be as low as about pA per element as those of typical complementary MOSFET devices used in digital circuitries. Therefore, the standby current consumption for the CEEPROM  400  is compatible with those of Static Random Access Memory (SRAM) mostly applied in digital circuitries. 
     To erase the digital configuration in CEEPROM  400 , the Fowler-Nordheim tunneling scheme can be applied to the N-type semiconductor non-volatile memory elements  410  and  420 . After erasing the N-type semiconductor non-volatile memory elements to the lower threshold voltage state, CEEPROM  400  is ready for new configuration. The CEEPROM is a Multiple Times Configurable (MTC) non-volatile memory. 
     In another embodiment CEEPROM  500  comprises with a pair of complementary P-type non-volatile memory elements  510  and  520 , and one N-type access MOSFET  540  as the schematic shown in  FIG. 5   a . The complementary P-type semiconductor non-volatile elements  510  and  520  are embedded inside an N-type well connected by the N-well electrode  535 . The complementary P-type semiconductor non-volatile memory elements  510  and  520  are controlled by the same control gate  530 . The source electrodes  501  and  502  of the P-type semiconductor non-volatile memory elements  510  and  520  form the voltage bias input nodes for positive voltage supply V DD  and ground voltage V SS , respectively. The drain electrodes  541  of the P-type semiconductor non-volatile devices  510  and  520  are connected together to the source electrode  541  of the N-type access MOSFET  540 . A voltage bias V G  greater than (V thn +V DD ) is applied to the gate electrode  542  of the N-type access MOSFET  540  to pass the signals at node  541  to the output node  550  of the CEEPROM  500 , where V thn  is the threshold voltage of the access transistor  540 . 
     Before configuring the P-type semiconductor non-volatile memory elements  510  and  520 , the P-type semiconductor non-volatile memory elements are initially in the erased state, where the P-type semiconductor non-volatile memory elements have lower threshold voltages (toward more negative side of voltage), that is, turning on the P-type non-volatile memory elements requires more negative applied control gate voltage relative to the source electrodes of the elements. The P-type non-volatile memory elements are initially “off” by applying the same positive voltage bias to the control gate  530 , source electrodes  501  and  502 , and well electrode  535  of the complementary P-type non-volatile memory elements. The complementary P-type semiconductor non-volatile memory elements  510  and  520  are configured by programming either one of the two elements to a higher threshold voltage (toward more positive side of voltage), that is, turning off the P-type non-volatile memory elements requires more positive applied control gate voltage relative to the source electrodes of the elements by injecting electrons to its charge storing material. For instance, p/n junction Band-To-Band (BTB) hot electron injection can be applied to inject electrons into the storing material of a P-type semiconductor non-volatile memory element. The programmed P-type non-volatile memory elements (threshold voltage shifted more positive) can be turned off only with a more relatively positive control gate voltage. Thus, in the configuration of  FIG. 5   a  one of the complementary P-type non-volatile memory elements after programming (injecting electrons to the storing material) would be always “on” by applying the same positive voltage bias to the control gate  530 , source electrodes  501  and  502 , and well electrode  535  of the complementary P-type non-volatile memory elements. 
       FIG. 5   b  and  FIG. 5   c  are the voltage biases at the electrodes of the CEEPROM  500  using complementary P-type semiconductor non-volatile memory elements  510  and  520  for configuring bit “0” and bit “1”, respectively. For configuring bit “0”, the input node  501  of element  510  is connected to the N-type well electrode  535  by a switch SW 3  according to a control signal CS 3  and the input node  502  of element  520  is connected to the ground voltage V SS  by a switch SW 4  according to the control signal CS 4 . The output node  550  and the input node  501  of element  510  are electrically shorted together. The control gates  530  of the elements  510  and  520  are floating. The gate  542  of the N-type MOSFET  540  are applied with a high voltage V GPH  greater than (V WH +V thn ) to equalize the N-type well voltage potential with the P-type drain electrodes of elements  510  and  520 , where V WH  is the amplitude of the applied voltage bias for BTB tunneling and V thn  is the threshold voltage of the N-type access MOSFET  540 . When a voltage pulse with amplitude V WH  is applied to the N-type well electrode  535  for several μs, the p/n junction of source/well in element  520  are reverse-biased to generate BTB tunneling for facilitating the hot electrons injected into the storing material of element  520 . Thus threshold voltage of element  520  shifted to more positive sides requires more positive applied control gate voltage to turn off. The programming process takes place simultaneously for configuring bit “1” in another CEEPROM cell with node  502  connected to N-type well electrode  535  and node  501  connected to ground as shown in  FIG. 5   c.    
     In the normal read mode after configuration as shown in  FIG. 5   d , the input node  501  of element  510  is connected to the positive voltage supply V DD  by the switch SW 3  according to the control signal CS 3  and the input node  502  of element  520  is connected to the ground voltage V SS  by the switch SW 4  according to the control signal CS 4  for the digital circuitry. The N-type well electrode  535  is also biased to V DD . A constant voltage bias V CG  (wherein (V DD +V the )&lt;V CG &lt;(V DD +V thp −V SS )) is applied to the control gate  530  such that V CG  can turn on the programmed P-type non-volatile devices with threshold voltage V thp , and turn off the un-programmed (erased) P-type non-volatile devices with threshold voltage V the . Note that for P-type MOSFET, the threshold voltage V the  is usually a negative value. For convenience, V CG  can be the positive voltage V DD , if the threshold voltage shifts of the programmed P-type semiconductor non-volatile elements are able to be fully turned “on” to pass the ground voltage V SS  under the applied gate voltage bias V DD , that is, V thp &gt;V SS , where V thp  is the threshold voltage of the programmed P-type non-volatile elements. The voltage potential at the node  541  is either V DD  for bit “1” or V SS  for bit “0” after configuration. To access the bit information of CEEPROM, the voltage signal of either V DD  or V SS  is passed to the output node  550  of the CEEPROM by applying a voltage bias V GP  greater than (V DD +V thn ) to the gate  542  of access transistor  540 . The voltage signal at the output node  550  can be directly applied to the logic gates in the digital circuitries. 
     In the standby read mode with the access transistor  540  “off”, the total steady current flowing from V DD  to V SS  through the pair of “on” and “off” (or “off” and “on”) non-volatile devices is the “off” leakage current for a single non-volatile device. Usually the “off” leakage current for a P-type semiconductor non-volatile memory element could be as low as few pA per element as those of typical complementary MOSFET devices used in digital circuitries. Therefore, the standby current consumption for the CEEPROM  500  is compatible with those of Static Random Access Memory (SRAM) mostly applied in digital circuitries. 
     To erase the digital configuration in CEEPROM  500 , the Fowler-Nordheim tunneling scheme can be applied to the P-type semiconductor non-volatile elements  510  and  520  to remove the electrons in the storing material. After erasing the P-type semiconductor non-volatile elements  510  and  520  to the lower threshold voltage state CEEPROM  500  (to be turned on by more negative gate voltage relative to the source electrode voltage) is ready for new configuration. The CEEPROM  500  is a Multiple Times Configurable (MTC) non-volatile memory. 
     The aforementioned description of the preferred embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations of non-volatile memory elements including the types of non-volatile memory device made of different non-volatile material and the types of access transistors will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. The abstract of the disclosure is provided to comply with the rules requiring an abstract, which will allow a searcher to quickly ascertain the subject matter of the technical disclosure of any patent issued from this disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Any advantages and benefits described may not apply to all embodiments of the invention. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.