Abstract:
A system and method of decoupling timing in a high speed bus system. A master/slave translator is coupled between a master device and a slave device. A pseudo slave of the master/slave translator responds to the master in a first timing protocol. A pseudo master of the master/slave translator masters the slave devices under a different timing protocol. The master/slave translator causes the master to believe its communications with the slave device are occurring under the first protocol.

Description:
BACKGROUND 
     (1) Field of the Invention 
     The invention relates to a bus system. More specifically, the invention relates to satisfying timing constraints in high-speed bus systems. 
     (2) Background 
     One typical bus configuration is a system having a single master and a plurality of slaves. The master may, for example, go poll every slave to determine whether the slave has something to send to the master or whether the slave can accept something from the master. Depending on their responses to the polling, the master selects among the slaves to send or receive data. One existing bussing protocol that falls within this genre is the Utopia 2 protocol, as set forth in the Utopia Level 2, V 1.0 June 1995 (Utopia 2). Utopia 2 and subsequent revisions are referred to generically herein as “Utopia” protocols. The Utopia 2 system is a synchronous bus system in which the master communicates with the slaves by putting the address on the bus and then the slave having a corresponding address answers with its availability. Utopia 2 is broken down into two separate busses, a transmit bus and a receive bus. If the address is asserted on the receive bus, the answer indicates whether the slave has something to send to the master. If the address is asserted on the transmit bus, the answer indicates whether the slave is capable of receiving something from the master. There is a limited window after the assertion of the address within which the slave must answer. As clock speed increases, this window shrinks. For example, a 50 MHz clock implies a clock cycle of 20 ns, and therefore, a window for possible response of 20 ns. This means that the communication must pass between the master and the slave within 20 ns. In certain backplane environments, and any other time when the slave is relatively remote from the master, the propagation delay in the backplane coupled with other factors may cause the time budget for the communication to be exceeded. Typically, the total budget=clock to out+2 buffer delays+propagation delay+target setup+clock skew. At 50 MHz, this must be less than 20 ns for a valid transaction. On, for example, a 21″ backplane, the propagation delay alone may be eight ns, thereby absorbing 40% of the total timing budget. As a result, achieving synchronous bus speeds on the order of 50 MHz has been highly problematic in such systems. 
     BRIEF SUMMARY OF THE INVENTION 
     A system and method of decoupling timing in a high speed bus system is disclosed. A master/slave translator is coupled between a master device and a slave device. A pseudo slave of the master/slave translator responds to the master in a first timing protocol. A pseudo master of the master/slave translator masters the slave devices under a different timing protocol. The master/slave translator causes the master device to believe its communications with the slave device are occurring under the first protocol. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of one embodiment of a bus system. 
     FIG. 2 is a flow chart of the operation of one embodiment of a pseudo master. 
     FIG. 3 is a flow diagram of operation in one embodiment of the pseudo slave. 
     FIG. 4 is a timing diagram showing the existing timing sequence of a Utopia 2 protocol. 
     FIG. 5 is a timing diagram of one embodiment of a protocol between the pseudo master and the slave devices. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 is a block diagram of one embodiment of a bus system. A master board  10  having a master  14  thereon is coupled to a bus  22  having a transmit bus  24  and a receive bus  26  as part thereof. A plurality of slave boards  12  are coupled to a bus  22 . Coupled to the master  14  on the master board  10  is a master/slave translator  16  which includes a pseudo slave  28  that communicates with master  14  and a pseudo master  30  that communicates via the bus  22  with the slave boards  12 . Also on the master board are a transmit buffer  18  and a receive buffer  20  corresponding to the transmit bus  24  and receive bus  26 , respectively. The slave boards  12  include a slave unit  32  coupled to a timing control unit  34  and a transmit buffer  36  and receive buffer  38  through which the slave board is coupled to the bus  22 . As used herein, the slave may be any bus entity which functions as a slave of the master. This includes a wide array of I/O devices and peripherals. 
     In one embodiment, the master  14  employs a Utopia protocol to communicate with its slaves using ATM cells. A VHDL coding of a master/slave translator  16  of such an embodiment is attached as Appendix A. A VHDL coding of a timing control unit  34  of such an embodiment is attached as Appendix B. In this embodiment, for example, the master  14  asserts the address for SLAVE 0  on its local bus, then deassert the address and expect a response during the idle time. A master/slave translator  16  is transparent to the master  14 , such that the pseudo slave  28  intercepts the address request and provides a response for SLAVE 0 . Thus, from the master&#39;s perspective, timing constraints have been satisfied. Because the pseudo slave  28  is proximate to the master, propagation delay and delay through the buffers is avoided. To ensure that the pseudo slave  28  has the current state information available when the master  14  polls, the pseudo master  30  polls all the slaves and provides the current states of each slave to a pseudo slave  28  for storage in register set  40 . Initially, at startup or reset the pseudo master  30  loads the pseudo slave  28  to reflect no cells available, such that the register set  40  has data available when the master  14  begins to poll. Then, as the pseudo master performs its polling of the slaves, the actual status is loaded into the pseudo slave  28 . 
     In performing its polling, the pseudo master  30  asserts an address, for example, on the transmit bus  24 . The pseudo master  30  then deasserts the address in the next cycle and asserts a next address in the following cycle. It is during an idle cycle following assertion of the next address that the first slave having the first address will respond to the assertion of the first address. By allowing for two clock delays, the window for response has effectively been expanded for the slave to respond in a timely manner. It is the responsibility of the timing control unit  34  to drive the response in the correct time period. Notably, while the state information provided by the pseudo slave  28  to the master  14  is not real time, it is accurate current state information in the sense that the state information, once retrieved from the slaves, will not change until acted on by the master  14 . 
     On the transmit side, the master  14  may poll all slave devices  32  and then select any available one for transfer of a cell, because unlike the polling, the transfer occurs in real time. The pseudo master  30  predicts the slave  32  that will be selected and prepares it for receipt of cell prior to the master  14  initiating the transaction. However, if the master  14  is permitted to choose a slave that was not prepared, an error occurs. Thus, the pseudo slave  28  masks the cell available response from all but one slave in any given time, thereby forcing the master  14  to select the predicted slave device  32 . 
     The above issue with transmit does not arise in the receive context under the Utopia protocol because the master  14  is required to service a slave  32  in need. Thus, in the course of the polling, if the master  14  identifies a receive slave cell available, that slave  32  will be serviced in the next cycle. Thus, pseudo master  30  knows in advance that a particular slave  32  will be serviced and causes the slave  32  to drive its first data word of the cell into receive buffer  20  and hold the data valid until the transaction is initiated by the master  14 . In this manner, the pseudo slave  28  is able to supply the master  14  data on every clock cycle within the timing budget of the master&#39;s timing protocol. In systems that do not require the master to immediately service a slave in need, a masking protocol consistent with that described above to force correct prediction on the receive side is within the scope and contemplation of the invention. 
     FIG. 2 is a flow chart of the operation of a pseudo master of one embodiment of the invention. The pseudo master asserts a first address on the backplane bus at functional block  100 . Then at functional block  102 , corresponding to the next clock cycle, the pseudo master deasserts the first address. At functional block  104  (corresponding to a third cycle) the pseudo master asserts a next address on the backplane bus. At functional block  106 , the pseudo master receives a response corresponding to the previous address. Thus, if an address for SLAVE 0  is asserted at functional block  100 , and SLAVE 1  is asserted at functional block  104 , the assertion or non-assertion of the cell available line at functional block  106  would correspond to an availability of a cell in SLAVE 0 . 
     A received response from functional block  106  is stored at functional block  110 . That next address is deasserted in a next clock cycle at functional block  108 . A determination is made if a previous address is the last address at decision block  112 . If it is not, the master proceeds with polling the remaining addresses repeating functional blocks  104  through  110 . If it is the last address, a determination is made that the master is polling at decision block  114 . If the master is polling, a determination is made if it is polling the transmit bus at functional block  116 . If the master is not polling the transmit bus (and it is polling), it is by implication polling the receive bus. Accordingly, the pseudo master loads data from the first slave entitled to send into the buffer on the master board at functional block  118 . A determination is then made at decision block  120  if the master has initiated the transaction. If the master has not initiated the transaction, the pseudo master holds the data in the buffer. Once the transaction has been initiated the pseudo master continues to master the bus to continue the cell transaction at functional block  124 . If the master is polling a transmit bus at functional block  116 , the pseudo master predicts a target (which will then be forced by the pseudo slave) at functional block  126 . Then at functional block  128 , the pseudo master prepares that target to receive prior to its selection by the master. Then at functional block  130 , the pseudo master drives the cell provided by the master to the pseudo slave out to the target slave. After the cell transactions are completed in either functional block  124  or functional block  130 , the system revisits the master polling decision block  114  before repolling the slaves at functional block  100  if the master is not polling. 
     FIG. 3 is a flow diagram of operation of one embodiment of a pseudo slave in one embodiment of the invention. At functional block  200 , the pseudo slave receives an address from the master. A determination is then made at functional block  202  if the master is asserting an active enable signal on the bus. If enable is not active, then pseudo slave returns the status or mask during and immediately following idle phase at functional block  204 . The pseudo slave then receives the next address at functional block  206 . If the enable is active, a determination is made at decision block  208  whether the enable was asserted on the transmit bus. If the enable was inserted on the transmit bus, the pseudo slave forwards the cell data provided by the master to the pseudo master to be driven out to the respective slave. If the enable was not on the transmit bus, the pseudo slave sends the cell data residing in the transmit buffer to the master. Sending of cell data at functional block  210  continues until the entire cell has been sent. Similarly, an entire cell of data will be forwarded successively at functional block  212 . After the cell is sent, the pseudo slave returns to wait for a next address asserted by the master. 
     FIG. 4 is a timing diagram showing the existing timing sequence of a transmit bus for a Utopia 2 protocol. In one embodiment, this timing sequence is carried out between the master and the pseudo slave. As can be seen, an address is asserted on the address lines in a clock cycle, for example, cycle  2 . N+2 is asserted on the address lines. Then in cycle  3 , the address lines are idle and the transmit cell available is driven by the device whose address was on the transit bus in the previous cycle, in this case, N+2. Here, N+2 does not have a cell available. However, N−3 and N+3 do have cells available, as reflected further along in the polling scheme. During cycles  1 - 15 , slave device N is receiving a cell along the data lines. Then with the rising edge of clock  16 , a new device, N+3 is selected for receipt of the next cell. The master begins polling immediately after beginning transmission of the next cell to device N+3. 
     FIG. 5 shows a timing diagram of a protocol between the pseudo master and the slave devices. In this embodiment, the transmit cell available signal is delayed by one address cycle so that it is received during a next active address idle time from the assertion of the original address. Thus, the transmit cell available for N+2 asserted on the address lines in cycle  2  appears on the transmit cell available line at cycle  5  during the N−3 address idle time. The timing is otherwise analogous to that of FIG.  4 . FIGS. 4 and 5 show timing for the transmit bus. Timing for the receive bus is analogous. It is noted that other embodiments may have responses received during active address times or have a plurality of address cycles between assertion of the address and a corresponding response. 
     In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. Therefore, the scope of the invention should be limited only by the appended claims.