Abstract:
Switching loss in push-pull switching transistors in a resonant inverter or the like, is minimized by assuring the switching of each of the transistors into conduction occurs when the voltage across its principal conduction path is zero-valued, or substantially so. This is done responsive to sensing the flow of forward currents through clamp diodes connected across the principal conduction paths of each of the transistors. This sensing is done so as to avoid the need for an additional coupling transformer. More particularly, the current flow to or from either of the terminals of the primary direct voltage supply, which current flow is in a first direction when either of the switching transistors is conductive and is in a second direction opposite to the first direction when the clamp diodes are conductive, is sensed for determining the times when the switching transistors are to begin to be conditioned for conduction. The switching transistors begin to be conditioned for conduction when the current flow is in the second direction.

Description:
The present invention relates to resonant inverters and more particularly to switching circuitry for conditioning switching transistors therein for conduction when their principal conduction paths have substantially zero voltages thereacross, prior to the application of voltages for causing actual conduction. 
     BACKGROUND OF THE INVENTION 
     FIG. 1A shows a resonant half-bridge inverter which includes, in addition to a resonant circuit, a primary supply 4 of direct voltage V DD , a coupling transformer T 1  with a primary winding and split-phase secondary windings, switching transistors Q 1  and Q 2 , clamp diodes D 1  and D 2 , and charge capacitors C 1 , C 2 , C 3  and C 4 . The resonant circuit is formed from the series connection of a resonance inductor L r  with a parallel connection of a resonance capacitor C r  and a load resistance R L . The resonant inverter is useful for high-frequency lighting using a fluorescent light or a discharge lamp, for example, with the fluorescent light or discharge lamp providing the load resistance R L  and some portion of the resonance capacitor C r . In such instances, the load resistance R L  exhibits substantial variation caused by changing conditions in the conduction through plasma, and the resonance inductor L r  provides ballasting. The primary supply 4 may be a battery of electrochemical cells, as when a fluorescent light or discharge lamp is used in emergency lighting. Alternatively, the primary supply 4 may instead comprise a rectifier for rectifying alternating voltage and a smoothing filter for converting the rectified alternating voltage to direct voltage. Such arrangement is useful, for example, for converting 60-cycle power from the electric mains to higher frequency to avoid flicker in lighting using a fluorescent light or a discharge lamp. 
     A switching signal appearing between terminals OUT1 and OUT2 applied to the primary winding of the transformer T 1  comprises, in effect, pulses that are alternately positive and negative in polarity. Respective secondary windings of the transformer T 1  apply this switching signal between the source and gate electrodes of the switching transistors Q 1 , and Q 2 , respectively, for conditioning them for alternate drain-to-source conduction with intervening intervals that neither of them is conditioned for drain-to-source conduction. The beginning of each interval when one of the switching transistors Q 1  and Q 2  is conditioned for drain-to-source conduction is timed to precede a zero-current condition in the resonance inductor L r . This is so that the switching transistor comes into conduction immediately upon reversal of the polarity of its source-to-drain potential as the resonant current flowing through the resonance inductor L r  builds up in polarity opposite to its previous polarity. 
     The capacitors C 1  and C 2  function primarily as commutating capacitors, and normally their respective capacitances are designed to be the same as each other. The capacitors C 1  and C 2  are made not to be too large in capacitance, so that losses owing to dissipation of their charge in the switching devices should switching be mis-timed does not reduce conversion efficiency of the resonant inverter too much. Normally, the respective capacitances of the capacitors C 3  and C 4  are designed to be the same as each other, as well, so that after operation is established in the resonant half-bridge inverter, the quiescent voltage at the interconnection of the charge capacitors C 3  and C 4  is essentially V DD  /2as referred to the negative terminal of the V DD  direct voltage supply 4. Furthermore, the capacitances of the charge capacitors C 3  and C 4  are customarily made large enough to suppress reasonably well the ripple voltage at their interconnection. The primary supply 4 is designed to include sufficient internal resistance that the initial charging of the capacitors C 1 , C 2 , C 3  and C 4  proceeds slowly enough that charging currents are not excessive. 
     The drain-to-source conduction of the switching transistor Q 1  maintains the capacitor C 1  discharged, applies a voltage that builds up the field surrounding the winding of the inductor L r  to cause an increasing positive current i L  flow therethrough, and charges the capacitor C 2  until the direct voltage supply potential V DD  appears between its plates. The positive current i L  flows from the positive terminal of the primary supply 4 through the conductive channel of the transistor Q 1  (which channel is the principal conduction path of that transistor), through the inductor L r , through the parallel connection of the resonant capacitor C r  and the load resistor R L  and returns to the negative terminal of the primary supply 4 via capacitor C 2 . When the capacitor C 2  charges so the direct voltage supply potential V DD  appears between its plates, drain-to-source conduction of the switching transistor Q 1  halts owing to lack of drain-to-source potential. The trailing edge of the positive pulse in the switching signal that conditions the switching transistor Q 1  to exhibit drain-to-source conduction is caused to occur at this time. The field surrounding the winding of the inductor L r  begins to collapse, tending to maintain the demand for positive current i L  flowing through the inductor L r  in accordance with Lenz&#39;s Law, discharging the capacitor C 2  and charging the capacitor C 1  as the voltage V g  at the node between the capacitors C 1  and C 2  falls during to a ground potential at the negative terminal of the direct voltage supply 4. The field surrounding the winding of the inductor L r  continues to collapse, tending to maintain the demand for positive current i L  flowing through the inductor L r  in accordance with Lenz&#39;s Law, and the clamp diode D 2  for the switching transistor Q 1  is drawn into conduction until the field surrounding the winding of the inductor L r  is completely collapsed and the demand for positive current i L  ceases. When the demand for positive current i L  ceases, the cathode of the diode D 2  is no longer pulled negative respective to its anode. The leading edge of the negative pulse in the switching signal that conditions the switching transistor Q 2  to exhibit drain-to-source conduction preferably occurs after the redistribution of charge from the capacitor C 2  to the capacitor C 1  and before free-running in the resonant circuit formed by the inductor L r  and the capacitor C r  begins to demand negative current i L . 
     The drain-to-source conduction of the switching transistor Q 2  maintains the capacitor C 2  discharged, applies a voltage that builds up the field surrounding the winding of the inductor L r  to cause an increasing negative current i L  flow therethrough, and charges the capacitor C 1  until the direct voltage supply V DD  potential appears between its plates. The negative current i L  flows to the negative terminal of the primary supply 4 through the conductive channel of the transistor Q 2  (which channel is the principal conduction path of that transistor) from the inductor L r  being drawn from the positive terminal of the primary supply 4 to the inductor L r  via the capacitor C 3  and thence the parallel connection of the resonant capacitor C 1  and the load resistor R L . When the capacitor C 2  charges so the direct voltage supply potential V DD  appears between its plates, halts owing to lack of drain-to-source potential. The trailing edge of the negative pulse in the switching signal that conditions the switching transistor Q 2  to exhibit drain-to-source conduction is caused to occur at this time. The field surrounding the winding of the inductor L r  begins to collapse, tending to maintain the demand for negative current i L  flowing through the inductor L r  in accordance with Lenz&#39;s Law, discharging the capacitor C 1  and charging the capacitor C 2  as the voltage V g  at the node between the capacitors C 1  and C 2  rises during flyback to the V DD  potential at the positive terminal of the direct voltage supply 4. The field surrounding the winding of the inductor L r  continues to collapse, tending to maintain the demand for positive current i L  flowing through the inductor L r  in accordance with Lenz&#39;s Law, and the clamp diode D 1  is driven into conduction until the field surrounding the winding of the inductor L r  is completely collapsed and the demand for negative current i L  ceases. When the demand for negative current i L  ceases, the anode of the diode D 1  is no longer pushed positive respective to its cathode. The leading edge of the positive pulse in the switching signal that conditions the switching transistor Q 1  to exhibit drain-to-source conduction preferably occurs after the redistribution of charge from the capacitor C 1  to the capacitor C 2  and before free-running in the resonant circuit formed by the inductor L R  and the capacitor C r  begins to demand positive current i L . 
     FIG. 1B shows the waveform of the current i L  flowing through the inductor L R  Of the FIG. 1A circuit during the cycle when the switching transistors Q 1  and Q 2  are alternately conditioned to exhibit drain-to-source conduction. In FIG. 1B the time t 0  is that at which the switching transistor Q 1  is conditioned by switching signal applied between its source and gate electrodes to exhibit drain-to-source conduction. The time t 1  is that at which the switching transistor Q 1  quits conduction. The charge interval for capacitor C 1  and the discharge interval for capacitor C 2  extend for the time duration t d1  from time t 1  until time t 2 , and the interval when the diode D 2  is drawn into conduction extends for the time duration t d2  from time t 2  until time t 3 . The switching signal applied between the source and gate electrodes of the switching transistor Q 2  should begin to condition transistor Q 2  to exhibit drain-to-source conduction some time after time t 2 , but no later than time t 3 . 
     Applying the switching signal between the source and gate electrodes of the switching transistor Q 2  before time t 2  conditions the transistor for inverse-mode conduction before the charging of the capacitor C 1  and the discharging of the capacitor C 2  are completed so the source-to-drain voltage of transistor Q 2  is essentially zero before it is conditioned for conduction. Charge remaining in capacitor C 2  has to be dissipated by conduction through the switching transistor Q 2 , and the charging of the capacitor C 1  has to be completed by drawing current from the primary supply 4 through the conductive switching transistor Q 2 . This switching loss, and analogous switching loss when the switching transistor Q 1  is conditioned for drain-to-source conduction too early, undesirably reduces conversion efficiency. 
     In practice, the switching signal applied between the source and gate electrodes of the switching transistor Q 2  generally has to be applied somewhat earlier than time t 3 , while the source-to-drain voltage of transistor Q 2  is essentially zero. Otherwise, capacitor C 1  is discharged somewhat, so its charging must be completed by drawing current from the primary supply 4 through the conductive switching transistor Q 2  ; and charge undesirably builds up in capacitor C 2  that has to be dissipated by conduction through the switching transistor Q 2 . This switching loss, and analogous switching loss when the switching transistor Q 1  is conditioned for drain-to-source conduction too late, also undesirably reduces conversion efficiency. Undesirable glitches are introduced into the waveform of the voltage V g  as well. 
     In the prior art the timings of the leading edges of the pulses in the switching signal applied across the primary winding of the split-phase coupling transformer T 1  have been inferred from the trailing edges of the immediately preceding pulses. However, the method has a practical problem that the timing of the occurrence of the zero-current condition in the resonant inductor L r , as referred to the switching off of the switching transistors, varies. Variation is caused by changes in the voltage V DD  supplied by the direct voltage supply 4 and by changes in the loading on the resonant circuit, which alter the decay time of the resonant current. Accordingly, the leading edges of the switching signal that condition the switching transistors to exhibit drain-to-source conduction have to be timed to be early enough to suit the worst-case increases in the voltage V DD  and the worst-case heaviest loading on the resonant circuit in order to prevent the introduction of undesirable glitches into the waveform of the voltage V g . The timing of the completion of charge redistribution in the capacitors C 1  and C 2  is also affected by changes in the voltage V DD  supplied by the direct voltage supply 4 and by changes in the loading on the resonant circuit, however, so the design should try to avoid the possibility of undesirable switching loss owing to the leading edges of the switching signal being made too early during worst-case decreases in the voltage V DD  and the worst-case reductions in loading on the resonant circuit. 
     There is a desire, then, for a better way to time the leading edges of the switching signal applied to the switching transistors Q 1  and Q 2  to assure that they occur during the periods of forward conduction by the diodes D 1  and D 2 . Preferably, this better way is one that does not require additional coupling transformers. 
     In the resonant inverter of FIG. 1 the source-to-drain voltage of the switching transistor Q 1  is close to being zero-valued when the clamp diode D 1  conducts and becomes zero-valued at the time the diode D 1  stops conducting responsive to the resonant current I L  passing through zero value to become positive in polarity. Conditioning the switching transistor Q 1  for conduction when its source-to-drain voltage is close to being zero-valued means that the capacitor C 1  in parallel with its channel is substantially discharged and conduction through the channel of transistor Q 1  does not dissipate substantial stored charge from the capacitor C 1  causing energy losses that must subsequently be replenished by drawing energy from the primary supply 4. Sensing when there is forward conduction by the diode D 1  provides an indication that the source-to-drain voltage of the transistor Q 1  is close to being zero-valued. Similarly, the source-to-drain voltage of the switching transistor Q 2  is close to being zero-valued when the clamp diode D 2  conducts and becomes zero-valued at the time the diode D 2  stops conducting responsive to the resonant current I L  passing through zero value to become negative in polarity. Conditioning the switching transistor Q 2  for conduction when its source-to-drain voltage is close to being zero-valued means that the capacitor C 2  in parallel with its channel is substantially discharged and conduction through the channel of transistor Q 2  does not dissipate substantial stored charge from the capacitor C 2  causing energy losses that must subsequently be replenished by drawing energy from the primary supply 4. Sensing when there is forward conduction by the diode D 2  provides an indication that the source-to-drain voltage of the transistor Q 2  is close to being zero-valued. The current flow to or from either of the terminals of the primary direct voltage supply 4 is in a first direction when either of the switching transistors is conductive and is in a second direction opposite to the first direction when either of the clamp diodes is conductive. The observations in this paragraph, the inventors point out, form the basis for being able to control the leading edges of the pulses in the switching signal so that they occur when the source-to-drain voltage of the one of the switching transistors Q 1  and Q 2  being switched into conduction is substantially zero-valued. 
     The flow of current through the clamp diodes of a resonant inverter can be sensed without need for a further coupling transformer, the inventors point out, even though one (or both) of the switching transistors has its source electrode connected other than to one of the terminals of the primary direct voltage supply 4. The current flow to or from either of the terminals of the primary direct voltage supply 4, which current flow is in a first direction when either of the switching transistors is conductive and to the extent it exists when the clamp diodes are conductive is in a second direction opposite to the first direction, is sensed for determining the times when the switching transistors are to begin to be conditioned for conduction. The switching transistors begin to be conditioned for conduction when the current flow is in the second direction. 
     SUMMARY OF THE INVENTION 
     The invention in a general aspect thereof seeks to minimize the switching loss in a switching transistor having a principal conduction path paralleled by a capacitor and a clamp diode, the principal conduction path of the switching transistor connected for supplying current of a first polarity from a primary direct voltage supply to a resonant circuit comprising a resonant inductor and resonant capacitor, and the clamp diode connected for receiving from the resonant circuit forward current of a second polarity opposite the first polarity. A control electrode of the switching transistor is supplied a switching signal that conditions the transistor for conduction when the voltage across its principal conduction path is zero-valued, or substantially so, which avoids the switching loss caused by dissipation of charge from the capacitor in the principal conduction path of the switching transistor during conduction of current therethrough when the voltage across its principal conduction path is no longer zero-valued. The flow of forward current through the clamp diode is sensed to provide a determination when the voltage across the principal conduction path of the switching transistor is zero-valued, or essentially so, and in accordance with a principle of the invention the generation of the switching signal supplied to the control electrode of the switching transistor is predicated on that determination. 
     The invention in more particular aspects thereof seeks to minimize the switching loss in push-pull switching transistors in a resonant inverter or the like, by assuring the switching of each of the transistors into conduction occurs when the voltage across its principal conduction path is zero-valued, or substantially so. This is done responsive to sensing the flow of forward currents through clamp diodes connected across the principal conduction paths of each of the transistors, and preferably this sensing is done so as to avoid the need for an additional coupling transformer. More particularly the current flow to or from either of the terminals of the primary direct voltage supply, which current flow is in a first direction when either of the switching transistors is conductive and is in a second direction opposite to the first direction when the clamp diodes are conductive, can be sensed for determining the times when the switching transistors are to begin to be conditioned for conduction. The switching transistors begin to be conditioned for conduction when the current flow is in the second direction. 
     In certain resonant inverters embodying the invention, the current flow to or from either of the terminals of the primary direct voltage supply is through an inverse-parallel connection of first and second semiconductor rectifier diodes, and the voltage across the inverse-parallel connection being of correct polarity and of sufficient amplitude enables an alternately selected one of the switching transistors to be conditioned for conduction. 
     In certain other resonant inverters embodying the invention, the current flow to or from either of the terminals of the primary direct voltage supply is through low-resistance resistive element, and the voltage across the resistive element being of correct polarity and of sufficient amplitude enables an alternately selected one of the switching transistors to be conditioned for conduction. 
     In still other resonant inverters embodying the invention, the current flow to or from either of the terminals of the primary direct voltage supply is through an avalanche, and the voltage across the resistive element being of correct polarity and of sufficient amplitude enables an alternately selected one of the switching transistors to be conditioned for conduction. 
     A slight delay may be introduced into the enablement of an alternately selected one of the switching transistors to be conditioned for conduction, so enablement is moved closer to the time zero-crossings occur in the resonant current. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The above objects and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which: 
     FIG. 1A is a circuit diagram showing a conventional resonant half-bridge inverter; 
     FIGURE 1B shows the waveform of a load current i L  of the resonant half-bridge inverter shown in FIG. 1A; 
     FIG. 2 is a circuit diagram of a resonant half-bridge inverter that is a first embodiment of the invention; 
     FIG. 3 is a circuit diagram of a resonant half-bridge inverter that is a second embodiment of the invention; 
     FIG. 4 is a circuit diagram of a resonant half-bridge inverter that is a third embodiment of the invention; 
     FIGS. 5A-5D show waveforms occurring in the case of the wrong operation of a zero-voltage switching; 
     FIGS. 6A-6I show output waveforms of each portion in the operation of a resonant half-bridge inverter constructed in accordance with the invention; 
     FIG. 7 is a circuit diagram of a resonant half-bridge inverter that is a fourth embodiment of the invention; 
     FIG. 8 is a circuit diagram of a resonant half-bridge inverter that is a fifth embodiment of the present invention; 
     FIG. 9 is a circuit diagram of a zero-voltage switching circuit according to a sixth embodiment of the invention; 
     FIG. 10 is a circuit diagram of a resonant half-bridge inverter that is a seventh embodiment of the invention; 
     FIGS. 11A-F show waveforms occurring in the operation of the resonant half-bridge inverter shown in FIG. 7; and 
     FIG. 12 is a graph showing the effect of the number of diodes in the circuitry for sensing conduction by either of the clamp diodes in the circuitry for sensing conduction by either of the clamp diodes in the FIG. 7 resonant half-bridge inverter upon the charging of the capacitor in a sawtooth oscillator therein. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 2 is a circuit diagram of a first embodiment of the invention comprising a resonant inverter 1, circuitry 2 for sensing conduction by either of the clamp diodes D 1  and D 2 , and switch driver circuitry 3 controlled by the circuitry 2 for driving the switching transistors Q 1  and Q 2  in the resonant inverter 1 into alternate conduction. The resonant inverter 1 differs from the conventional resonant inverter shown in FIG. 1 in that the negative terminal of the direct-voltage primary supply 4 connects to a signal ground S GND  which differs from a power ground P GND  to which interconnected plates of charge capacitors C 2  and C 4 , the source electrode of the switching transistor Q 2 , and the anode of the diode D 2  all connect. 
     The circuitry 2 for sensing conduction by either of the clamp diodes D 1  and D 2  includes a diode D 3  with anode connected to the power ground P GND  and cathode connected to the signal ground S GND , a diode D 4  with cathode connected to the power ground P GND  and with anode connected to the signal ground S GND , a source 5 of offset voltage V offset  connected at its positive terminal to the power ground P GND , a voltage comparator 10 having an inverting input connected to the negative terminal of the offset voltage source 5 and a non-inverting input connected to the signal ground S GND , and an RS flip-flop 13 a set port of which has the output of the comparator 10 connected thereto. 
     (The order in which the source 5 of offset voltage V offset  and the differential input circuit of the comparator are serially connected can be interchanged, supposing the comparator design is such as to still permit the voltage V 2  to be brought close to signal ground S GND . That is, alternatively, V t  can be applied directly to the inverting input of the comparator 10, and the non-inverting input of the comparator 10 can be biased from the positive terminal of a source of offset voltage V offset  that has its negative terminal connected to signal ground S GND .) 
     The switch driver circuitry 3 includes a sawtooth oscillator 11; a voltage comparator 12 having an inverting input to which an output signal V 0  of oscillator 11 is applied, a non-inverting input to which a reference voltage V r  is applied and an output for applying an output signal V 1  to the reset port of RS latch 13; an OR gate 14 for logically summing an output signal V 3  of RS latch 13 and an output signal V 1  of the comparator 12 to generate a voltage V 4 , a triggered (T) flip-flop 15 for receiving the output of OR gate 14 and acting as a frequency divider, an AND gate 16 generating output signal OUT1 in response to V 4  and the &#34;true&#34; output of the T flip-flop 15, and an AND gate 17 generating output signal OUT2 in response to V 4  and the &#34;not-true&#34; output of the T flip-flop 15. Alternatively, in an equivalent circuit that can replace AND gates 16 and 17, a first NAND gate is used for generating output signal OUT1 in response to V 4  and the &#34;not-true&#34; output of the T flip-flop 15, and a second NAND gate is used for generating output signal OUT2 in response to V 4  and the &#34;true&#34; output of the T flip-flop 15. Applying the pulses in the output waveform of the comparator 12 alternately to the OUT1 and OUT2 terminals of the transformer 1 primary winding, while the other of the OUT1 and OUT2 terminals is grounded, avoids direct current flow in the primary winding. Such arrangements are simpler than push-pull driving arrangements that have balanced power supplies or driving arrangements that have direct-current blocking capacitors in series with the primary windings of coupling transformers. 
     The sawtooth oscillator 11 oscillates at a predetermined rate close to twice the resonant frequency of the resonant circuit formed by the inductor L r  and the capacitor C r . The sawtooth oscillator 11 is often constructed as a relaxation oscillator, in which a capacitor is charged relatively slowly at a prescribed rate until a prescribed voltage appears thereacross, at which time the capacitor is rapidly discharged (e.g., by causing a switch between its plates to conduct and dissipate the charge as heat). Where the oscillator 11 is not included in an automatic frequency control (AFC) feedback loop, better frequency stability can be achieved by using a clock oscillator generating sinusoidal oscillations stabilized by a crystal or an anti-resonant tank, cyclically counting the oscillations with a counter, and decoding selected portions of the count to generate an output voltage corresponding to V 1 . Other pulse generators, as known in the art, rather than either of the alternatives described, can be used for supplying pulses to reset RS latch 13. 
     FIG. 3 is a circuit diagram of a second embodiment of the invention differing from the first embodiment of the invention shown in FIG. 2 in that the diodes D 1  and D 2  are replaced by a resistor R t  connected between signal ground S GND  and power ground the positive terminal of offset voltage source 5 to signal ground S GND  and to power ground P GND . 
     FIG. 4 is a circuit diagram of a third embodiment of the invention that modifies the second embodiment of the invention shown in FIG. 3, to include a capacitor C c  and resistor R c  respectively connecting the positive terminal of offset voltage source 5 to signal ground S GND  and to power ground P GND , rather than the positive terminal of offset voltage source 5 connecting directly to power ground P GND . The resistor R c  and the capacitor C c  form a lowpass filter that provides some delay in turning on the switching transistors Q 1  and Q 2 . Similar delaying arrangements can be used to modify the FIG. 2 embodiment of the invention. 
     FIGS. 5A-5D shows example waveforms for the case of a malfunctioning zero-voltage switching operation. FIG. 5A shows a voltage V g  of a first interconnection node n 1  between switching transistors Q 1  and Q 2 . FIG. 5B shows the waveform of a current i L  which flows through the inductor L r . FIG. 5C also shows the waveform of the output signal V 0  of an oscillator. FIG. 5D shows the output waveform of the comparator 12. In the prior art the transformer driver 16 applied the pulses in the output waveform of the comparator 12 alternately to the OUT1 and OUT2 terminals of the transformer 1 primary winding, while the other of the OUT1 and OUT2 terminals was grounded. 
     Referring to FIG. 2 showing a resonant inverter embodying the invention, consider a logic ZERO being applied to the OR gate 14 instead of the voltage V 3  shown. Such modification causes the operation of the FIG. 2 resonant inverter to emulate operation of the prior art circuit. Now, referring to FIGS. 5A-D, the faulty operation of zero-voltage switching that is caused by such modification will be described. 
     To assure zero-voltage switching, switching transistors Q 1  and Q 2  must be turned on while their respective clamp diodes are conductive before a current i L  in the waveform of FIG. 5B passes through a zero point Z. During the earlier of the sawtooth oscillations shown in FIG. 5C this occurs. However, during the last of the sawtooth oscillations shown in FIG. 5C, the switching transistor Q 2  is turned on after current i L  passes through zero point Z. This permits undesirable recharging of the capacitor C 2  and discharging of the capacitor C 1  after current i L  passes through zero point Z, causing a undesirable spike in the voltage V g  commonly called a &#34;glitch&#34;. When the switching transistor Q 2  is turned on, it discharges the capacitor C 2 , dissipating the energy contained in the charge as heat; and the resultant energy loss must be supplied via the switching transistor Q 2  from the primary supply 4 in order to bring the capacitor C 1  up to full charge. The dissipation of energy required of switching transistor Q 2  stresses the device. If the subsequent sawtooth oscillation after those shown in FIG. 5C turns the switching transistor Q 1  on after current i L  passes through its next zero point Z, it experiences similar problems, having to dissipate charge in the capacitor C 1  and having to bring the capacitor C 2  up to full charge. 
     Referring to FIGS. 6A-6I, circuitry 2 for sensing conduction by either of the clamp diodes D 1  and D 2 , and switch driver circuitry 3 controlled by the circuitry 2 for driving the switching transistors Q 1  and Q 2  in the resonant inverter 1 into alternate conduction will be described. 
     FIG. 6A shows the waveform of a voltage V g  of the first interconnection node n 1  between switching transistors Q 1  and Q 2 . When a voltage V g  rises and falls between supply voltage V DD  and ground voltage Ground by the operation of switching transistors Q 1  and Q 2 , a resonant inductor L r  and a resonant capacitor C r  resonate. 
     FIG. 6B shows the waveform of a current i L  which flows through the inductor L r . 
     In an interval M1, switching transistor Q 2  is turned on while switching transistor Q 1  remains turned off, which clamps to a low level the voltage V g  of the first interconnection node n 1  between switching transistors Q 1  and Q 2 . Current flow is from the positive terminal of the primary supply 4 through the capacitor C 3 , the resonant circuit, the switching transistor Q 2 , and the diode D 3  to the negative terminal of the primary supply 4. At this time, voltage V t  at the node n 2  connected to power ground P GND  is V D3 . (V D3  is a forward-conduction voltage of diode D 3 , which is about 0.7 V.) 
     The switching transistor Q 2  is turned off at the boundary between the interval M1 and an immediately following interval M5 of free-running. During the interval M2 capacitor C 1  discharges and capacitor C1 1  charges and the voltage V g  of the node n 1  between the switching transistors Q 1  and Q 2  rises to a high level. The voltage V t  at a node n 2  connected to a power ground P GND  remains essentially a zero voltage respective to the signal ground S GND . 
     In an interval M3, since voltage V g  of the connection between switching transistors Q 1  and Q 2  is a high level, diode D 1  is turned on to conduct the continuing current from the inductor L r . The current to support the forward conduction of diode D 1  flows through the third node n 3  from the capacitor C 4  and through the resonant circuit. The current flows to the positive terminal of the primary supply 4, through the primary supply 4 as a voltage-translating element and out its negative terminal to forward bias the diode D 4  into forward conduction as the current completes its loop return to the capacitor C 4 . At this time, then, voltage V t  applied to power ground P GND  is -V D4 . (V D4  is a forward-conduction voltage of diode D 4 , which is about 0.7 V.) 
     In an interval M4, switching transistor Q 1  is turned on while switching transistor Q 2  remains turned off, causing the voltage V g  at the first interconnection node n 1  between switching transistors Q 1  and Q 2  to be high in level. Current flows from the positive V DD  terminal of the primary direct voltage supply 4 through the conductive switching transistor Q 1 , through the resonant circuit and the capacitor C 4 , and thence to the negative terminal of the supply 4 through the diode D 3 , forward biasing D 3  into conduction. At this time, voltage V t  applied at the node n 2  connected to power ground P GND  is again V D3 . 
     The switching transistor Q 1  is turned off at the boundary between the interval M4 and an immediately following interval M5. M5 is an interval of free-running during which capacitor C 2  discharges and capacitor C 1  charges and the voltage V g  of the node n 1  between the switching transistors Q 1  and Q 2  falls to a low level. The voltage V t  at a node n 2  connected to a power ground P GND  becomes essentially a zero voltage respective to the signal ground S GND . 
     In an interval M6, during which voltage V g  of the connection point between switching transistors Q 1  and Q 2  remains at a low level, diode D 2  turns on to conduct the continuing current into the inductor L r . The current to support the forward conduction of diode D 2  flows from the higher potential supplied by the capacitor C 3  to the positive terminal of the primary supply 4, through the primary supply 4 as a voltage-translating element and out its negative terminal, and forward biases the diode D 4  into forward conduction. At this time, voltage V t  at the node n 2  connected to power ground P GND  is again -V D4 . 
     FIG. 6C shows the sawtooth waveform of an output signal voltage V 0  supplied from the oscillator 11. Note that the rightmost sawtooth of the output signal voltage V 0  extends beyond the time that the inductor L r  current i L  crosses through zero in FIG. 6B, giving rise to the problem solved by the invention. 
     FIG. 6D shows the waveform of an output signal voltage V 1  of the comparator 12. The comparator 12 compares an output signal V 0  of the oscillator with a reference voltage V r , supplying a high signal when voltage V 0  is lower than reference voltage V r  and supplying a low signal when voltage V 0  is higher than voltage V r . FIG. 6D also shows how the rightmost sawtooth of the output signal V 0  in FIG. 6C being too extended delays the rightmost low-to-high transition in the output signal V 1  of the comparator 12. This would delay the corresponding transition in the drive signal OUT2 in the prior art. 
     FIG. 6E shows the waveform of an output signal voltage V 2  of the comparator 10, which supplies a high signal when voltage V t  falls below the offset voltage V offset . The comparator 10 output voltage is high responsive to the voltage drop across D 4  as it conducts the current needed to supply the inductor L r  current i L  when one of the diodes D 1  and D 2  is conductive. 
     FIG. 6F shows the waveform of the &#34;true&#34; output voltage V 3  of the RS latch 13, which is set &#34;high&#34; in response to the leading edge of each positive pulse in the output signal voltage V 2  of the comparator 10, and which is reset &#34;low&#34; in response to the leading edge of each positive pulse in the output signal voltage V 1  of the comparator 12. When the falling edge of a sawtooth oscillation occurs concurrently with the falling edge of an output signal voltage V 2  pulse, which normally is the case, the output voltage V 3  of the RS latch 13 exhibits pulses similar to those in the output signal voltage V 2  of the comparator 10. When the falling edge of a sawtooth oscillation occurs later than the falling edge of an output signal voltage V 2  pulse, the output voltage V 3  of the RS latch 13 exhibits pulses of extended duration. Such an extension of the duration of the rightmost pulse of the output voltage V 3  is cross-hatched in FIG. 6F. This pulse extension is used to prevent erroneously turning off the switching transistor Q 2 , which would undesirably permit a positive-going glitch to appear in the voltage V g  at the first interconnection node n 1  between switching transistors Q 1  and Q 2 . 
     FIG. 6G shows the waveform of an output signal voltage V 4  of the OR gate 14, which receives the output signal voltage V 1  of the comparator 12 and the &#34;true&#34; output voltage V 3  of the RS latch 13 as its two input signals. Since the RS latch 13 is set &#34;high&#34; until the output signal voltage V 1  of the comparator 12 goes &#34;high&#34; to reset the RS latch 13 in response thereto, the output signal voltage V 4  of the OR gate 14 will go &#34;high&#34; when the RS latch 13 is set &#34;high&#34; and will remain &#34;high&#34; until the comparator 12 output signal voltage V 1  subsequently goes &#34;low&#34;. The waveform shown in FIG. 6G accordingly has its duty increased by +D. 
     FIGS. 6H and 6I show waveforms of output signal OUT1 and output signal OUT2 supplied from the transformer driver 16 in amplified response to alternate ones of the positive pulses in the output signal voltage V 4  of the OR gate 14 shown in FIG. 6G. The T flip-flop 15 is triggered by the falling edges of the comparator 10 output signal voltage V 4  and functions as a frequency divider. The AND gate 16 responds to V 4  and the &#34;true&#34; output of the T flip-flop 15 to generate the output signal OUT1 shown in FIG. 6H, and the AND gate 17 responds to V 4  and the &#34;not-true&#34; output of the T flip-flop 15 to generate the output signal OUT2 shown in FIG. 6I. 
     When a current i L  rises too rapidly in intervals M2 and M3, or falls too rapidly in intervals M5 and M6, so a discharging time t 1  of a sawtooth waveform appears after a current i L  passes through a zero point, an output operation signal turning on switching transistors Q 1  and Q 2  tends to be delayed to cause wrong operation of the zero-voltage switching. Accordingly, to avoid the wrong operation of the zero-voltage switching, a circuitry 2 for sensing conduction by either of the clamp diodes D 1  and D 2  detects a state of a voltage V t  and then turns on switching transistors Q 1  and Q 2  at the time when diode D 4  is turned on. That is, switching transistors Q 2  and Q 1  are switched into conduction at the beginning of interval M3 and at the beginning of interval M6, respectively, in order always to perform the switching operation when the voltage V g  is zero. This avoids power loss in the switching operation. 
     FIG. 7 is a circuit diagram of a resonant inverter including zero-voltage switching circuitry according to a fourth embodiment of the invention that differs from the FIG. 2 first embodiment of the invention in the following respects, although the same resonant inverter 1 is used in both embodiments. 
     In the FIG. 7 switch driver circuitry 30, the fixed-rate sawtooth oscillator 11 of the FIG. 2 switch driver circuitry 3 is replaced by a controlled-rate sawtooth oscillator 100. The voltage comparator 12 and the OR gate 14 are dispensed with, as well as connections to the RS latch 13. Instead, a voltage comparator 110 compares the output voltage V 5  of the controlled-rate sawtooth oscillator 100 with a reference voltage V r  to generate a voltage V 6  comprising a train of pulses. The T flip-flop 15 is triggered by the falling edges of these pulses and still functions as a frequency divider. The AND gate 16 responds to V 6  and the &#34;true&#34; output of the T flip-flop 15 to generate the output signal OUT1 responsive to alternate ones of the V 6  voltage pulses, and the AND gate 17 responds to V 4  and the &#34;not-true&#34; output of the T flip-flop 15 to generate the output signal OUT2 responsive to the intervening V 6  voltage pulses. The controlled-rate sawtooth oscillator 100 has a charging period during which a capacitor C t  associated therewith is charged by current of a value corresponding to a control current applied to a terminal of the oscillator 100 held close in potential to its positive operating supply, which typically is a few volt (e.g. 5 V.) supply. Typically, the oscillator 100 is constructed using a monolithic integrated circuit, with the capacitor C t  charged from the output connection of a current mirror amplifier that receives the applied control current at its input connection and has its common connection to the positive operating supply of the oscillator 100 The duration of the charging period is determined by the capacitance of the capacitor C t  and the value of the applied control current. 
     The circuitry 20 for sensing conduction by either of the clamp diodes D 1  and D 2  shown in FIG. 7 dispenses with the offset voltage supply 5, the comparator 10 and the RS latch 13 of the FIG. 2 circuitry 2 for sensing conduction by either of the clamp diodes D 1  and D 2 . The voltage V t  at the node n 2  is applied to a resistor R t  for generating the applied current that controls the charging slope of the sawtooth generated by the sawtooth oscillator 100 and thus controls the duration of the sawtooth. The single diode D 4  may be replaced by a series connection of diodes, so the charging slope of the sawtooth generated by the sawtooth oscillator 100 is affected in more pronounced way when either of the clamp diodes D 1  and D 2  conduct. 
     FIG. 12 is a graph showing the variation of charge slope in the FIG. 7 oscillator 100 according to the number of diodes D 4 . In FIG. 12, four different plots show the cases where the number of diodes D 4  decreases from one up to four. The sensitivity of charge slope change that is available is determined by adjusting the number of diodes D 4 . That is, a value of a voltage V t  is changed according to the number of diodes and the quantity of a current flowing through a resistor R t  is changed according to the voltage value. Consequently, the difference of the quantity of a current leads to the difference between normal charge current and accelerated charge current of the capacitor C t  connected to an oscillator. Thus, current variations result in frequency variations according to f=I/(CV). That is, the increase of the number of diodes leads to increased current through a resistor R t . Accordingly, the average charge current of capacitor C t  is increased, so that the resonant frequency is increased. 
     Lowering the positive operating supply for the controlled-rate sawtooth oscillator 100, or otherwise reducing the potential at which the control terminal of the oscillator is held, are alternative ways to increase the effect upon the charging slope of the oscillator 100 of either of the clamp diodes D 1  and D 2  conducting. 
     FIG. 8 is a circuit diagram of a resonant inverter including zero-voltage switching circuitry according to a fifth embodiment of the invention. It modifies the FIG. 7 fourth embodiment of the invention in that a resistor R 2  is connected in series with the diode(s) D 4 . 
     FIG. 9 is a circuit diagram of a resonant inverter including zero-voltage switching circuitry according to a sixth embodiment of the invention. It modifies the FIG. 7 fourth embodiment of the invention in that the resistor R t  is replaced by a serial connection of resistors R f  and R t , with a capacitor C f  bypassing to ground the interconnection between resistors R f  and R t . The resistor R f  and the capacitor C f  form a lowpass filter that make the feedback control of the controlled-rate sawtooth oscillator 100 more stable. 
     FIG. 10 is a circuit diagram of a resonant inverter including zero-voltage switching circuitry according to a seventh embodiment of the invention. It modifies the FIG. 7 fourth embodiment of the invention in that the diode(s) D 4  are replaced by a Zener or avalanche diode D z  poled for reverse conduction of the current that flows when either of the clamp diodes D 1  and D 2  conduct. During such reverse conduction the reverse voltage across the diode D z  is constrained to a voltage V zener . The forward conduction of the diode D z  generally suffices to carry the forward current flowing when either of the switching transistors Q 1  and Q 2  is conductive. Accordingly, the diode D 3  can be dispensed with unless operating frequency of the resonant converter is so high that the time delay associated with changing the mode of conduction through the diode D z  is significant. 
     FIGS. 11A-11F show waveforms occurring in the operation of the resonant inverter including zero-voltage switching circuitry shown in FIG. 7. 
     FIG. 11A shows a waveform of a voltage V g  of the node n 1  at the connection point between switching transistors Q 1  and Q 2 . FIG. 11B shows a waveform of a current i L  flowing through the inductor L r . FIG. 11C shows the waveform of an output signal V 5  of the oscillator 100, FIG. 11D the waveform of an output signal V 6  of the comparator 110, FIG. 11E the waveform of an output signal OUT1 of the AND gate 16, and FIG. 11F the waveform of an output signal OUT2 of the AND gate 17. The operation of the resonant inverter including zero-voltage switching circuitry shown in FIG. 7 will now be more particularly described, referring to FIGS. 11A-F. 
     When the current i L  shown in FIG. 7 falls in intervals M5 and M6, as shown in FIGS. 6B and 6C, if a discharging time t 1  of a sawtooth waveform appears after current i L  passes through a zero point, an output operation signal turning on switching transistors Q 2  would be delayed to cause incorrect operation of zero-voltage switching. To prevent this from occurring, the charging of the capacitor C t  is accelerated once the diode D 1  conducts to cause forward conduction of the diode(s) D 4 . Accordingly, switching transistor Q 2  is turned on earlier in the interval M3 in order that the operation of switching is performed on the condition that a voltage V g  of the connection between switching transistors Q 1  and Q 2  is zero, achieving switching operation having no power loss. 
     Now, referring to FIGS. 11A-F, the operation of a zero-voltage switching circuit by each interval will be described. 
     In an interval M4 when a switching transistor Q 1  is turned on so the diode D 3  is forward conduction, a voltage V t  is a forward voltage V D4  of diode D 3  and the current I 1  flowing through a resistor R t  is calculated as 
     
         I.sub.1 =(V.sub.ref -V.sub.D3)/R.sub.t. 
    
     In an interval M5, voltage V t  free-runs to an interval when capacitors C 1  and C 2  are charged and discharged and then becomes zero voltage. The current I 2  flowing through a resistor R t  is calculated as 
     
         I.sub.1 =(V.sub.ref -0)/R.sub.t. 
    
     In an interval M6 when each diode D 4  is in forward conduction to have a forward voltage V D  thereacross, voltage V t  is (N+1)V D  and the current I 3  flowing through a resistor R t  is calculated as 
     
         I.sub.1 =[V.sub.ref -(N+1)V.sub.D ]R.sub.t. 
    
     Here, V ref  indicates a voltage determined within a zero-voltage switching circuit by receiving a supply voltage V DD  and N is a whole number indicative of he number of diodes D 4  in excess of one. Subsequently, the procedure is repeatedly performed. At this time, the variation of a current determines a frequency. A frequency f (or 1/T) is obtained according to 
     
         f=(C.sub.t V).sup.-1 
    
     and 
     
         I=C.sub.t (dV/dt). 
    
     Here, C t  indicates a capacity of a capacitor, I a charge or discharge current of a relaxation oscillator, dV incremental voltage change across the capacitor, and dt the incremental charging (or discharging) time of the capacitor. In particular, the earlier portion of interval M3 exhibits a steep charging slope because a frequency is suddenly varied in response to current I 3  being suddenly increased. 
     The invention also has obvious application to resonant inverters of full-bridge type and in dc-to-dc converters constructed from resonant inverters of half-bridge or full-bridge type. Any of the resonant inverters of half-bridge type is readily converted to a resonant inverter of full-bridge type by adjusting the capacitance of the capacitors C 3  and C 4  to be substantially the same as that of the capacitors C 1  and C 2 , then connecting the capacitors C 3  and C 4  together with elements Q 3 , Q 4 , D 5 , D 6 , and T 2  corresponding to the elements Q 1 , Q 2 , D 1 , D 2 , and T 1 . The capacitors C 3  and C 4  are connected together with the elements Q 3 , Q 4 , D 5 , D 6 , and T 2  the same way the capacitors C 1  and C 2  are connected together with the elements Q l , Q 2 , D 1 , D 2 , and T 1  ; and the primary windings of the split-phase transformers T 1  and T 2  are driven in antiphase, so transistors Q 1  and Q 4  are simultaneously conditioned for drain-to-source conduction, and so transistors Q 2  and Q 3  are simultaneously conditioned for drain-to-source conduction. Dc-to-dc converters can be constructed by using the primary winding of a transformer as the resonant inductor L r  and rectifying currents from the secondary winding(s) of the transformer.