Abstract:
A method of driving a plasma display panel reduces an address write cycle and also realizing a stable high definition, high-quality display without erroneous discharge. In the light emission by driving the plasma display panel having plural pairs of row electrodes and plural column electrodes arranged so as to cross these pairs of row electrodes and forming discharge cells at intersections of the pairs of row electrodes and the column electrodes, ones of the pairs of row electrodes are divided into first and second row electrode groups, and a scan pulse is applied to one row electrode of the second row electrode group just after applying the scan pulse to one row electrode of the first row electrode group.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a method of driving a matrix display type plasma display panel (hereinafter referred to as PDP). 
     2. Description of Related Art 
     As well known, PDP has been variously studied as a thin planar display device. A matrix display type PDP is known as one of the PDPs. 
     As one of methods of displaying an image with gradation on this matrix display type PDP, known is a so-called subfield method in which the image is displayed by dividing one field of display period into N subfields to be lighted for a period of time corresponding to weighted bit positions of N-bit pixel data. 
     This subfield method comprises the steps of: simultaneous reset for once initializing all of discharge cells; address writing for setting lighting discharge cells and un-lighting discharge cells by scanning an address (writing the data) in accordance with image data; and sustain discharge for holding the lighting discharge cells and un- lighting discharge cells discharged by the application of a sustain pulse. 
     At this time, a cycle of the address write must be shortened in order to realize a highly fine display by increasing the number of lines and increasing the number of display gradation in such a PDP. 
     For example, when the image is displayed at VGA resolution of 640×480 dots, 4-5 [μSEC] are satisfactory for a scan rate. However, the higher-speed write, for example, a write period of about 2 [μSEC] is required to display the image at XGA resolution of 1024×768 dots. 
     FIG. 1 shows a configuration of a plasma display device for carrying out such a high-speed address write. 
     In PDP  10  shown in FIG. 1, formed are row electrodes Y 1 -Y 4  and row electrodes X 1 -X 4  which make pairs of row electrodes so that a pair of X and Y may correspond to each of rows (the first to fourth rows) on one screen. Furthermore, formed are column electrodes D 1 -D 4  which make column electrodes so that they may be perpendicular to these pairs of row electrodes, a dielectric layer and a discharge space (not shown) may be placed therebetween and they may each correspond to each of columns (the first to fourth columns) on one screen. At this time, one discharge cell is formed at an intersection of a pair of row electrodes (X, Y) and one column electrode D. 
     An address driver  20  converts one screen of pixel data in the PDP  10  into pixel data pulses corresponding to these pixel data on a row-by-row basis. These pulses are applied to each of the address electrodes D 1 -D 4  in an order as shown in FIGS.  2 A- 2 G: 
     a pixel data pulse group DP 1  corresponding to the first row; 
     a pixel data pulse group DP 3  corresponding to the third row; 
     a pixel data pulse group DP 2  corresponding to the second row; and 
     a pixel data pulse group DP 4  corresponding to the fourth row. 
     Here, an X-row electrode driver  30  first applies a reset pulse RP X  as shown in FIG. 2B to the row electrodes X 1 -X 4 . 
     A Y-row electrode driver  40 A is used for applying various driving pulses as described below to a block of the row electrodes Y in the upper half of one screen in the PDP  10 ,that is, the row electrodes Y 1  and Y 2 . On the other hand, a Y-row electrode driver  40 B is used for applying various driving pulses as described below to a block of the row electrodes Y in the lower half of one screen in the PDP  10 , that is, the row electrodes Y 3  and Y 4 . 
     In FIGS. 2C through 2F, at the same time when the reset pulse RP X  is applied to the row electrodes, the Y-row electrode driver  40 A applies a reset pulse RP Y  as shown in FIGS. 2C and 2D to the row electrodes Y 1  and Y 2 . Moreover, at the same time when the reset pulse RP X  is applied to the row electrodes, the Y-row electrode driver  40 B applies a reset pulse RP Y  as shown in FIGS. 2E and 2F to the row electrodes Y 3  and Y 4  (a reset step). 
     This application of the reset pulse causes all the discharge cells in the PDP  10  to be discharged/excited, so that charged particles are generated. After the termination of this discharge, a predetermined amount of wall charges are uniformly formed on the dielectric layers in all the discharge cells. 
     Next, immediately after applying a positive-voltage priming pulse as shown in FIG. 2C to the row electrode Y 1 , the Y-row electrode driver  40 A applies a negative-voltage scan pulse SP to the row electrode Y 1 . At this time, immediately after applying the positive-voltage priming pulse to the row electrode Y 3  at a timing as shown in FIG. 2E, the Y-row electrode driver  40 B applies the negative-voltage scan pulse SP to the row electrode Y 3 . Furthermore, immediately after applying the positive-voltage priming pulse to the row electrode Y 2  at a timing as shown in FIG. 2D, the Y-row electrode driver  40 A applies the negative-voltage scan pulse SP to the row electrode Y 2 . 
     Furthermore, immediately after applying the positive-voltage priming pulse to the row electrode Y 4  at a timing as shown in FIG. 2F, the Y-row electrode driver  40 B applies the negative-voltage scan pulse SP to the row electrode Y 4  (an address step). 
     At this time, out of the same cells existing in the row electrodes to which the scan pulse SP has been applied, the discharge occurs in the discharge cells to which the high-voltage pixel data pulse DP has been applied, most of the wall charges are thus lost. On the other hand, since no discharge occurs in the discharge cells to which the low-voltage pixel data pulse DP has been applied, the wall charges remain. That is, executed is a so-called pixel data write in which whether or not the wall charges remain in the discharge cells is determined depending on the pixel data pulse DP applied to the column electrode. 
     A priming pulse PP is applied to the electrode immediately before the application of the scan pulse, whereby the charged particles, that have been obtained in the above-described reset step and reduced as time has passed, are reformed in the discharge space in the PDP. 
     Therefore, under the same conditions in which these charged particles are present on any one of the first to fourth rows, the pixel data write by the application of the scan pulse SP is carried out. 
     Next, the X-row electrode driver  30  incessantly applies a positive-voltage sustain pulse IP X  to the row electrodes X 1 -X 4 . The Y-row electrode drivers  40 A and  40 B incessantly apply a positive-voltage sustain pulse IP Y  to the row electrodes Y 1 -Y 4  at a timing shifted from the timing of the application of the sustain pulse IP X  (a sustain discharge step). 
     Over the time period for which the sustain pulses IP X  and IP Y  are alternately applied to the row electrodes, the discharge cells in which the above-mentioned wall charges remain are repeatedly discharged and emit a light, and the discharge cells keep emitting the light. 
     As described above, in such a driving method, an attempt is made to reduce an address write cycle by overlapping the timing of the application of the priming pulse PP with the timing of the application of the scan pulse SP to other row electrodes. 
     For example, when a write scan (addressing) is performed for the row electrode Y 1  on the first row, the negative-polarity scan pulse SP applied to this row electrode Y 1 , the positive-polarity pixel data pulse DP 1  applied to the column electrodes D 1 -D 4  and the positive-polarity priming pulse PP applied to the row electrode Y 3  on the third row of a second row electrode group (the row electrodes Y 3 and Y   4 ) are applied to the electrodes at an overlapping timing. 
     However, when the timings of the application of the pixel data pulse DP 1  and the priming pulse PP are thus overlapped with each other, the negative wall charges are stored in the column electrodes D 1 -D 4  during a priming discharge by the priming pulse PP applied to the above-described row electrode Y 3 . 
     Therefore, in the write scan on the third row following this priming discharge, the negative-polarity scan pulse SP is applied to the row electrode Y 3 , whereby, during attempting to generate a selective erasure discharge responding to the positive-polarity pixel data pulse DP 3 , the selective erasure discharge is difficult to generate by an influence of the negative wall charges on the column electrodes D 1 -D 4  stored due to the just previous priming discharge, which makes a stable display operation difficult. 
     Moreover, when the waveform of each driving pulse to be applied to the aforementioned first row electrode group is caused to differ from the waveform of each driving pulse to be applied to the second row electrode group, the Y-row electrode drivers  40 A and  40 B become also disadvantageously unbalanced at the address margins thereof. 
     OBJECT AND SUMMARY OF THE INVENTION 
     The present invention is made in order to solve problems as described above. It is an object of the present invention to provide a method of driving a plasma display panel which can reduce an address write cycle and also realize a stable highly-fine/high-quality display without erroneous discharge. 
     According to the present invention, there is provided a method of driving a plasma display panel which has a plurality of pairs of row electrodes and a plurality of column electrodes, the plurality of column electrodes being arranged so as to cross the pairs of row electrodes and forming discharge cells at intersections of the pairs of row electrodes and the column electrodes, the method performing when driving the plasma display panel to emit light, an operation of dividing one field of display period is into a plurality of subfields, each subfield being composed of an address period and a sustain discharge period so as to display an image, the address period in which, immediately after applying a priming pulse of a predetermined polarity to one of the pair of row electrodes, a scan pulse of an opposite polarity to the polarity of the priming pulse is applied to said row electrode and simultaneously a pixel data pulse is applied to the column electrode whereby lighting discharge cells and un-lighting discharge cells are set in response to said pixel data pulse, the sustain discharge period for holding said lighting discharge cells and the un-lighting discharge cells discharged by applying a sustain pulse to the pair of row electrodes, wherein ones of the pairs of row electrodes are divided into first and second row electrode groups, and the scan pulse is applied to one row electrode of the second row electrode group immediately after applying the scan pulse to one row electrode of the first row electrode group. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which; 
     FIG. 1 is a diagram schematically showing the structure of a plasma display device; 
     FIGS. 2A-2G are timing charts of the application of various driving pulses by drivers of FIG. 1; 
     FIG. 3 is a diagram schematically showing the structure of the plasma display device driven by a driving method according to the present invention; 
     FIGS. 4A-4I are timing charts of the application of the driving pulses based on the driving method of the present invention; 
     FIG. 5 is a diagram showing another embodiment of the plasma display device driven by the driving method according to the present invention; 
     FIGS. 6A-6I are timing charts of the application of the driving pulses based on another driving method of the present invention; 
     FIG. 7 is a diagram showing still another embodiment of the plasma display device driven by the driving method according to the present invention; 
     FIG. 8 is a diagram showing an internal structure of a Y-row electrode driver  80 ; 
     FIG. 9 is a diagram showing the constitution of the plasma display device to which the Y-row electrode driver  80  shown in FIG. 8 is applied; 
     FIGS. 10A-10O show operating waveforms generated by the plasma display device shown in FIG. 9; 
     FIGS. 11A-11O show another example of the operating waveforms generated by the plasma display device shown in FIG. 9; 
     FIG. 12 is a diagram showing another exemplary structure of the plasma display device shown in FIG. 9; and 
     FIGS. 13A-13M are diagrams showing still another example of the operating waveforms generated by the plasma display device shown in FIG.  12 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 3 shows the structure of a plasma display device for driving PDP by a driving method according to the present invention. FIGS. 4A-4I are timing charts of the application of various driving pulses by this driving method. 
     In PDP  50  shown in FIG. 3, formed are row electrodes Y 1  through Y n  and row electrodes X 1  through X n  which make pairs of row electrodes so that a pair of X and Y may correspond to each of rows (the first to n-th rows) on one screen. Furthermore, formed are column electrodes D 1  through D m  which make column electrodes so that they may be perpendicular to these pairs of row electrodes, a dielectric layer and a discharge space (not shown) may be placed therebetween and they may each correspond to each of columns (the first to m-th columns) on one screen. At this time, one discharge cell is formed at an intersection of a pair of row electrodes (X, Y) and one column electrode D. In this case, one screen in the PDP  50  is divided into two upper and lower blocks A and B as shown in FIG.  3 . 
     A Y-row electrode driver  80 A is used for applying various driving pulses as described below to the row electrodes Y included in the block A, that is, the row electrodes Y 1  through Y k . On the other hand, a Y-row electrode driver  80 B is used for applying various driving pulses as described below to the row electrodes Y included in the block B, that is, the row electrodes Y k+1  through Y n . An X-row electrode driver  70  is used for applying various driving pulses as described below to the row electrodes X 1  through X n  in the PDP  50 . 
     In the first place, the X-row electrode driver  70  applies a positive-voltage reset pulse RP X  as shown in FIG.  4 B to the row electrodes X 1  through X n  in the PDP  50  at the same time. At the same time when this reset pulse RP X  is applied to the row electrodes, the Y-row electrode driver  80 A applies a negative-voltage reset pulse RP Y  as shown in FIGS. 4C-4E to the row electrodes Y 1  through Y k  in the PDP  50  at the same time. Moreover, at the same time when this reset pulse RP X  is applied to the row electrodes, the Y-row electrode driver  80 B applies the negative-voltage reset pulse RP Y  as shown in FIGS. 4F-4H to the row electrodes Y k+1  through Y n  in the PDP  50 , simultaneously (a reset step). 
     In response to the application of these reset pulses RP X  and RP Y , all the discharge cells in the PDP  50  are discharged, so that charged particles are generated in the discharge spaces. After the termination of this discharge, a predetermined amount of wall charges are uniformly formed on the dielectric layers in all the discharge cells. 
     When this reset step is terminated, an address driver  60  converts one screen of pixel data into pixel data pulse groups DP on a row-by-row basis. Pixel data pulse groups DP 1  through DP n  corresponding to the respective rows are then applied to the electrodes in a form as shown in FIG.  4 A. 
     That is, the pixel data pulse groups DP 1  through DP k  corresponding to the respective “rows” included in the block A in the PDP  50  shown in FIG. 3 are sequentially applied to the column electrodes in a cycle T 1  as shown in FIG.  4 . In addition, the pixel data pulse groups DP k+1  through DP k  corresponding to the respective “rows” included in the block B are sequentially applied to the column electrodes in the above-described cycle T 1  at a delayed timing by a pulse width later than the timings of the pixel data pulse groups DP k+1  through DP n . 
     Here, immediately before the above-mentioned pixel data pulse group DP 1  is applied to the column electrode, the Y-row electrode driver  80 A generates a positive-voltage priming pulse PP as shown FIG.  4 C and applies this priming pulse PP to the row electrode Y 1 . Next, the Y-row electrode driver  80 A applies a negative-voltage scan pulse SP as shown FIG. 4C to the row electrode Y 1  at the same timing as the timing of the application of the pixel data pulse group DP 1 . 
     On the other hand, immediately before the above-mentioned pixel data pulse group DP k+1  is applied to the column electrode, the Y-row electrode driver  80 B generates the positive-voltage priming pulse PP as shown FIG.  4 F and applies this priming pulse PP to the row electrode Y k+1 . Next, the Y-row electrode driver  80 B applies the negative-voltage scan pulse SP as shown FIG. 4F to the row electrode Y k+1  at the same timing as the timing of the application of the pixel data pulse group DP k+1 . 
     On the termination of the application of the above-described scan pulse SP by the Y-row electrode driver  80 B, just before the aforementioned pixel data pulse group DP 2  is applied to the column electrode, the Y-row electrode driver  80 A generates the positive-voltage priming pulse PP as shown FIG.  4 D and applies this priming pulse PP to the row electrode Y 2 . Next, the Y-row electrode driver  80 A applies the negative-voltage scan pulse SP as shown FIG. 4D to the row electrode Y 2  at the same timing as the timing of the application of the pixel data pulse group DP 2 . 
     On the other hand, just before the above-described pixel data pulse group DP k+2  is applied to the column electrode, the Y-row electrode driver  80 B generates the positive-voltage priming pulse PP as shown FIG.  4 G and applies this priming pulse PP to the row electrode Y k+2 . Next, the Y-row electrode driver  80 B applies the negative-voltage scan pulse SP as shown FIG. 4G to the row electrode Y k+2  at the same timing as the timing of the application of the pixel data pulse group DP k+2 . 
     At the same timing as the above-mentioned timing, the Y-row electrode driver  80 A successively applies the priming pulse PP and the scan pulse SP to the row electrodes Y 3  through Y k  in the PDP  50 . Moreover, the Y-row electrode driver  80 B successively applies the priming pulse PP and the scan pulse SP to the row electrodes Y k+3  through Y n  (an address step). 
     In the described-above address step, the discharge cells existing in the row electrodes which have been subjected to the application of the scan pulse SP are divided into two kinds in response to the pixel data pulse groups DP applied at this time. One is the discharge cells which perform discharging excitation and the other is the discharge cells which perform no discharging excitation. In this case, the wall charges remain on the dielectric layers in the discharge cells which performed no discharging excitation, while the wall charges on the dielectric layers disappear from the discharge cells which performed the discharging excitation. The lighting discharge cells and the un-lighting discharge cells are set in accordance with an amount of the wall charges, so that a so-called pixel data write is carried out. 
     The priming pulse PP is applied to the electrode immediately before the application of the scan pulse SP, whereby the charged particles, which have been generated in the above-described reset step and reduced with the passage of time, are reformed in the discharge space in the PDP  50 . That is to say, before the charged particles are absent, the pixel data is written by the application of the above-mentioned scan pulse SP. Therefore, under the same conditions (where the amount of the charged particles within the discharge cells) on any one of the first to n-th rows, the pixel data write is carried out. 
     Subsequently, the X-row electrode driver  70  incessantly applies a positive-voltage sustain pulse IP X  as shown in FIG. 4B to the row electrodes X 1  through X n . The Y-row electrode drivers  80 A and  80 B incessantly apply a positive-voltage sustain pulse IP Y  as shown in FIGS. 4C-4H to the row electrodes Y 1  through Y n  at a timing shifted from the timing of the application of the sustain pulse IP X  (a sustain discharge step). 
     Over the time period for which the sustain pulses IP X  and IP Y  are alternately applied to the row electrodes, the discharge cells which have been set to the lighting discharge cell in the above-described address step (the discharge cells in which the wall charges remain residual) are repeatedly discharged and emit a light, and the discharge cells keep emitting the light. Luminance is visually recognized in accordance with the time period for which this sustain discharge is carried out. 
     As described above, in the driving method shown in FIGS. 4A-4I, the timings of the application of the priming pulse PP to two different row electrodes are set so that they may be substantially the same as each other, whereby an attempt is made to reduce an address write cycle. For example, in FIGS. 4A-4I, the timing of the application of the priming pulse PP to the row electrode Y 1  is substantially the same as the timing of the application of the priming pulse PP to the row electrode Y k+1 , or the timing of the application of the priming pulse PP to the row electrode Y 2  is substantially the same as the timing of the application of the priming pulse PP to the row electrode Y k+2 . 
     Furthermore, as shown in FIGS. 4C-4H explained above, the row electrode Y of a pair of the row electrodes X and Y is divided into two groups A and B. Immediately after applying the scan pulse SP to the row electrode Y in the group A, the scan pulse is applied to the row electrode Y in the group B. By such a driving method, the timings of the application of the pixel data pulse groups DP 1  through DP n  (the timings of the application of the scan pulse SP) are set in such a manner that they are not the same as the timings of the application of the priming pulse PP to any row electrode. 
     Thus, the address write cycle can be reduced, while an erroneous discharge caused by the simultaneous application of the pixel data pulse groups DP and the priming pulse PP can be also prevented, and therefore a high image quality can be maintained. 
     Also, in the above-described embodiment shown in FIG. 3, the screen in the PDP  50  is divided into two upper and lower blocks A and B, namely, the block A including the row electrodes X 1  through X k  (Y 1  through Y k ) in the upper half and the block B including the row electrodes X k+1  through X n  (Y k+1  through Y n ) in the lower half. The row electrodes in the blocks A and B are driven by the Y-row electrode drivers  80 A and  80 B, respectively. 
     However, as shown in FIG. 5, the row electrodes X 1  through X k  (Y 1  through Y k ) in the upper half on the screen in the PDP  50  may be furthermore divided into two upper and lower blocks A and B, and the row electrodes X k+1  through X n  (Y k+1  through Y n ) in the lower half may be furthermore divided into two upper and lower blocks A and B. The row electrodes in the blocks A and B may be driven by the Y-row electrode drivers  80 A and  80 B, respectively. 
     In FIG. 5, the row electrodes X 1  through X k  (Y 1  through Y k ) in the upper half on the screen in the PDP  50  are divided into blocks A and B, namely, the block A including the row electrodes X 1  through X p  (Y 1  through Y p ) and the block B including the row electrodes X p+ 1 through X k  (Y p+1  through Y k ). The row electrodes X k+1  through X n  (Y k+1  through Y n ) in the lower half on the screen in the PDP  50  are also divided into blocks A and B, namely. The block A includes the row electrodes X k+1  through X r  (Y k+1  through Y r ), and the block B includes the row electrodes X r+1  through X n  (Y r+1  through Y n ). 
     In this case, the Y-row electrode driver  80 A drives the row electrodes Y 1  through Y p  and the row electrodes Y k+1  through Y r , simultaneously, while the Y-row electrode driver  80 B drives the row electrodes Y p+1  through Y k  and the row electrodes Y r+1  through Y n , simultaneously. 
     Additionally, the column electrodes D 1  through D m  are divided into two sections, namely, the upper half (the first to k-th rows) and the lower half (the (k+1)-th to n-th rows) in the PDP  50 . The upper and lower halves are driven by first and second address drivers  60 A and  60 B, respectively. Pixel data A supplied to the first address driver  60 A corresponds to the first to k-th rows in the PDP  50 , while pixel data B supplied to the second address driver  60 B corresponds to the (k+1)-th to n-th rows in the PDP  50 . 
     According to the constitution shown in FIG. 5, it will be possible to perform a simultaneous writing/scanning for the row electrode groups in the upper and lower halves in the PDP  50 . 
     For example, in FIG. 5, the Y-row electrode driver  80 A applies the scan pulse SP to the row electrodes Y 1  and Y k  simultaneously. At this time, the pixel data pulse group DP 1  corresponding to the row electrode Y 1  is applied to the column electrodes by the first address driver  60 A, while the pixel data pulse group DP k  corresponding to the row electrode Y k  is applied to the column electrodes by the second address driver  60 B. That is to say, two rows of write is done by one scan. 
     Therefore, the employment of the constitution shown in FIG. 5 allows the address write cycle to be furthermore reduced to ½. 
     In the embodiment shown in FIGS. 4A-4I, the start timing of the application of the priming pulse PP in the block A does not precisely coincide with the start timing of the application of the priming pulse PP in the block B. However, as shown in FIGS. 6A-6I, both the timings may exactly coincide with each other by advancing the start timing of the application of the priming pulse PP in the block B. 
     However, due to this advancement of the start timing of the application of the priming pulse PP in the block B, the pulse width of the priming pulse PP generated by the Y-row electrode driver  80 B is larger than the pulse width of the priming pulse PP generated by the Y-row electrode driver  80 A. 
     Thus, the Y-row electrode drivers  80 A and  80 B become disadvantageously unbalanced at the address margins thereof. 
     FIG. 7 shows the other constitution of a driving device for overcoming such a problem. 
     The constitution shown in FIG. 7 is the same as the constitution shown in FIG. 3 except for a selector  90 . Modules having the same functions as the functions of the modules shown in FIG. 3 have the same reference numerals. 
     The selector  90  shown in FIG. 7 applies various driving pulses from the Y-row electrode driver  80 A to the row electrodes (the row electrodes Y 1  through Y k ) in the block A or the row electrodes (the row electrodes Y k+1  through Y n ) in the block B in response to a field switch signal. The selector  90  also applies various driving pulses from the Y-row electrode driver  80 B to the row electrodes (the row electrodes Y k+1  through Y n ) in the block B or the row electrodes (the row electrodes Y 1  through Y k ) in the block A in response to the field switch signal. 
     At this time, the field switch signal has its logical level which is changed from “1” to “0” or from “0” to “1”, for example, for every field (sub-field) in the supplied pixel data. 
     For example, when the logical level of the field switch signal is “1”, various driving pulses from the Y-row electrode driver  80 A are applied to the row electrodes (the row electrodes Y 1  through Y k ) in the block A, and various driving pulses from the Y-row electrode driver  80 B are also applied to the row electrodes (the row electrodes Y k+1  through Y n ) in the block B. Here, when the logical level of the field switch signal is switched from “1” to “0”, various driving pulses from the Y-row electrode driver  80 A are applied to the row electrodes (the row electrodes Y k+1  through Y n ) in the block B, and various driving pulses from the Y-row electrode driver  80 B are applied to the row electrodes (the row electrodes Y 1  through Y k ) in the block A. 
     That is, in the above-mentioned constitution shown in FIG. 7, the Y-row electrode drivers  80 A and  80 B alternately drive the blocks A and B on the field-by-field basis (subfield-by-subfield basis). 
     Therefore, even if the pulse width of the priming pulse PP generated by the Y-row electrode driver  80 A is different from the pulse width of the priming pulse PP generated by the Y-row electrode driver  80 B, the address margin can be uniformly formed. 
     FIG. 8 shows a partially internal constitution (a priming pulse generator and a scan pulse generator) of the above-mentioned Y-row electrode driver  80 . 
     As shown in FIG. 8, the aforementioned Y-row electrode driver  80  is provided with first to third power sources B 1 -B 3  whose voltage values differ from each other. The second power source B 2  generates a DC voltage V 2  that is, by a predetermined voltage, lower than a DC voltage V 1  generated by the first power source B 1 . The positive terminal of the third power source B 3  is connected to the positive terminal of the DC power source B 2 . A serial circuit constituted of switching elements S 1  and S 2  is connected between both the terminals of the third power source B 3 . When the switching element S 1  is turned on, the element S 1  applies the potential of the positive terminal of the second power source B 2  (or the positive terminal of the third power source B 3 ) onto a line L. When the switching element S 2  is turned on, the element S 2  applies the potential of the negative terminal of the third power source B 3  onto the line L. 
     The line L is connected to the positive terminal of the first power source B 1  generating the DC voltage V 1 . 
     Pulse output circuits  82   1  through  82   k  are composed of the same circuit constitution. Each of the circuits  82   1  through  82   k  comprises a switching element S 11  for applying the potential on the line L to the row electrodes Y during the period of time when being turned on and a switching element S 12  for applying the potential of the negative terminal of the first power source B 1  to the row electrodes Y during being turned on. 
     FIG. 9 shows the constitution of the plasma display device when the Y-row electrode driver  80  having the internal constitution shown in FIG. 8 is applied to the Y-row electrode drivers  80 A and  80 B of FIG.  3 . FIGS. 10A-10O show operating waveforms of the plasma display device of FIG.  9 . 
     In FIGS. 10A-10O, there is shown the operation only when the priming pulse PP and the scan pulse SP are applied to the row electrode Y 1  of the row electrodes in the block A and the row electrode Y k+1  of the row electrodes in the block B. 
     As shown in FIGS. 10A-10O, switching elements S 1   a  and S 2   a  (S 1   b  and S 2   b ) included in the Y-row electrode driver  80  are alternately/periodically turned on/off. In his way, a positive terminal potential VA H  and a negative terminal potential VA L  of a first power source B 1   a  (a positive terminal potential VB H  and a negative terminal potential VB L  of a first power source B 1   b ) are each allowed to periodically form a period having the potential that is offset by a voltage value V 3 . Here, during the time when a switching element S 11   a  (S 11   b ) is turned off and a switching element S 12   a  (S 12   b ) is turned on, the as-unchanged negative terminal potential VA L  (VB L ) is applied onto the row electrodes Y. Next, when the switching element S 11   a  (S 11   b ) is switched on and the switching element S 12   a  (S 12   b ) is switched off, the as-unchanged positive terminal potential VA H  (VB H ) is applied onto the row electrodes Y. This is the priming pulse PP. Subsequently, again, when the switching element  11   a  (S 11   b ) is switched off and the switching element S 12   a  (S 12   b ) is switched on, the as-unchanged negative terminal potential VA L  (VB L ) is applied onto the row electrodes Y. At t is time, as described above, the period having the potential that is offset by the voltage value V 3  is the scan pulse SP. 
     Also in FIGS. 10A-10O, the application of the scan pulse SP to one row electrode (Y 1 ) in the block A is followed by the application of the scan pulse SP to one row electrode (Y k+1 ) in the block B. That is, an address operation (a selective address erasure) is successively executed on one line in the block A and one line in the block B. 
     At this time, as shown in FIGS. 10N and 10O, when the scan pulse SP is applied to the row electrode Y k+1  in the block B and the pixel data pulse DP k+1  is applied to the column electrodes D 1  through D m  so as to write the pixel data, a back porch BP of the scan pulse SP is present on the row electrode Y 1  in the block A at the same timing as this timing. However, if a potential difference V a  between the scan pulse SP and the back porch BP is small, the erroneous discharge is generated between the row electrode Y 1  and the column electrode due to the pixel data pulse DP k+1 . Moreover, if a potential difference V A  shown in FIGS. 10G and 10N is small the erroneous priming discharge (between the row electrodes X and Y) is easily generated in a front porch FP just before the priming pulse PP. 
     Accordingly, in the embodiment shown in FIGS.  9  and  10 A- 10 O, the potential of the back porch BP in the block A overlapping with the period of the application of the scan pulse in the block B is set to an intermediate potential (a third potential) between the potential of the scan pulse SP and the potential of the priming pulse PP. 
     Alternatively, the pulse width of the scan pulse SP in the block B may be longer than the priming pulse PP in the block A by eliminating the back porch BP just after the scan pulse SP in the block B. 
     FIGS. 11A-11O show the other operating wave forms of the plasma display device made in view of this point. 
     In FIGS. 11A-11O, in the first place, the timing at which the switching element S 11   b  (S 12   b ) included in the Y-row electrode driver  80 B is switched from OFF to ON (from ON to OFF) is made equal to the switch timing of the switching elements S 11   a  and S 12   a  of the Y-row electrode driver  80 A. After that, only during the period when the positive and negative terminal potentials VB H  and VB L  of the first power source B 1   b  included in the Y-row electrode driver  80 B are offset by the voltage value V 3 , the switching element S 11   b  (S 12   b ) is turned off (on). Thus, as shown in FIG. 11N, not only the back porch BP just after the application of the scan pulse but also the front porch FP just before the priming pulse PP are eliminated from the row electrode Y k+1 . 
     As shown in FIGS. 11G and 11N, when the block A is driven by the Y-row electrode driver  80 A, the back porch BP is present just after the scan pulse SP. On the other hand, when the block B is driven by the Y-row electrode driver  80 B, the back porch BP and the front porch FP are eliminated. Thus, the pulse width of the priming pulse PP in the block B can be increased, and consequently the address margin in the block B is increased. 
     In the embodiment shown in FIGS.  9  and  11 A- 11 O, the potentials of the back porch BP and the front porch FP existing during driving the block A are determined by the potential of the negative terminal of the first power source B 1 . Therefore, since the potentials of these back porch BP and front porch FP cannot be thoughtlessly adjusted, it is not easy to take measures to prevent the erroneous discharge. 
     FIG. 12 shows another constitution of the plasma display device made in view of this point. 
     In the plasma display device shown in FIG. 12, a circuit comprising a second power source B 2   a  (B 2   b ), a third power source B 3   a  (B 3   b ) and switching elements S 1   a  (S 1   b ) and S 2   a  (S 2   b ) is shared by the Y-row electrode drivers  80 A and  80 B, although such a circuit is disposed in each of the Y-row electrode drivers  80 A and  80 B in the constitution shown in FIG.  9 . Furthermore, pulse output circuits  82 ′ (if FIG. 12 are constituted so that an output from the switching element S 11   a  (S 11   b ) or S 12   a  (S 12   b ) is applied to the row electrodes Y through a switching element S 13   a  (S 13   b ). In short, during the period when the switching element S 13  is turned off, the application of the voltage to the row electrodes Y is forced to be stopped. 
     FIGS. 13A-13M show the operating waveforms generated by the plasma display device shown in FIG.  12 . 
     As shown in FIG. 13G, the switching element S 13   a  is switched from ON to OFF during driving the block A, whereby the application of the voltage from the Y-row electrode driver  80 A is stopped. At this time, since the PDP  50  is capacitively loaded, the potential just after switching is fixedly left on the row electrodes Y. As shown in FIG. 13H, this potential is changed into the back porch BP or the front porch FP. That is, the potentials of the back porch BP just before the priming pulse PP and the front porch FP just after the scan pulse SP are set in accordance with the timing of the switching from ON to OFF by the switching element S 13   a.  Therefore, this timing is adjusted, whereby the potentials of the back porch BP and the front porch FP can be set so that they may be within a range in which the erroneous discharge is not generated between the row electrodes or between the row and column electrodes. 
     The increase of the address margin is therefore facilitated, and thus the image quality and the panel yield can be improved. Moreover, although the second and third power sources B 2  and B 3  are disposed in each of the Y-row electrode drivers  80 A and  80 B in FIG. 9, they are shared by the Y-row electrode drivers  80 A and  80 B as shown in FIG.  12 . Thus, the circuit scale can be reduced in comparison to the constitution shown in FIG.  9 . 
     Although the above-described embodiments show that one screen in the PDP  50  is divided into two upper and lower blocks and one of a pair of row electrodes is divided into two row electrode groups so as to drive the electrodes, the present invention is not limited to this example. The electrodes may be driven by dividing one screen into two sections, an odd line and an even line and by dividing one of a pair of row electrodes into three or four row electrode groups. 
     Although the preferred embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions and alternations can be made therein without departing from spirit and scope of the inventions as defined by the appended claims.