Abstract:
Output switch noise resulting from simultaneous switching is reduced by time multiplexing the output switching operation. A plurality of phase-shifted clock signals are generated such that each of the phase-shifted clock signals exhibits an active (e.g., rising) edge during a single period of the reference clock signal. Different groups of input/output blocks are switched in response to the various phase-shifted clock signals, such that output switching occurs at various times during the period of the reference clock signal. The phase-shifted clock signals can be generated with predetermined phase differences or with dynamically determined phase differences.

Description:
FIELD OF THE INVENTION 
   The present invention relates to a method and apparatus for reducing the transient currents associated with simultaneously switched outputs of a semiconductor chip. 
   RELATED ART 
   Output signals of a semiconductor chip are typically switched simultaneously in response to an output clock signal. Such simultaneously switched outputs result in large transient currents, which cannot be easily controlled. Conventional methods used to control the large transient currents associated with simultaneously switched outputs include controlling the slew rate of the output signals and/or controlling the strength of the output signals. However, such methods either require excessive circuitry, or reduce the integrity of the output signals. 
   It would therefore be desirable to have an improved method and apparatus for reducing the high transient current associated with simultaneously switched outputs. 
   SUMMARY 
   Accordingly, the present invention reduces transient current created during output switching by time multiplexing the output switching operation within each clock period. A plurality of output clock signals are generated in response to an input clock signal, wherein the output clock signals are phase-shifted with respect to the input clock signal. Each of the phase-shifted clock signals exhibits an active (e.g., rising) edge during a single period of the input clock signal. Different groups of input/output blocks are switched in response to the various phase-shifted clock signals, such that output switching occurs at various times during the period of the input clock signal. The phase- shifted clock signals can be generated with predetermined phase differences or with dynamically determined phase differences. 
   In accordance with one embodiment, a digital clock manager generates a plurality of output clock signals, which are separated by 90-degree phase differences. For example, a first output signal may be synchronous with the input clock signal, a second output clock signal may lag the first output clock signal by 90 degrees, a third output clock signal may lag the second output clock signal by 90 degrees, and a fourth output clock signal may lag the third output clock signal by 90 degrees. A first set of input/output resources are clocked by the first output clock signal, a second set of input/output resources are clocked by the second output clock signal, a third set of input/output resources are clocked by the third output clock signal, and a fourth set of input/output resources are clocked by the fourth output clock signal. As a result, the transient switching current existing at any given time is reduced by a factor of four. 
   In accordance with another embodiment, a digital clock manager determines the period of the input clock signal. For example, delay elements may be introduced to the path of the input clock signal until the resulting output clock signal is synchronous with the input clock signal. At this time, the delay introduced by the delay elements is equal to one period of the input clock signal. The input clock signal (or resulting output clock signal) is applied to a chain of series-connected programmable delay lines, thereby generating a corresponding plurality of delayed clock signals. The delay introduced by each of the programmable delay lines is selected with respect to the period of the input clock signal. Thus, the sum of the delays introduced by the programmable delay lines is less than the period of the input clock signal. 
   In one embodiment, each of the programmable delay lines includes a plurality of delay elements, wherein each of the delay elements in the programmable delay lines is identical to each delay element in the digital clock manager. In this embodiment, the number of delay elements enabled within each of the programmable delay lines is determined by dividing the number of delay elements introduced by the digital clock manager by the number of programmable delay lines. As a result, each of the programmable delay lines introduces the same delay to the received clock signal. 
   The present invention will become more clearly understood in view of the following description and drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram of a field programmable gate array (FPGA) in accordance with one embodiment of the present invention. 
       FIG. 2  is a waveform diagram illustrating an input clock signal CLK IN , associated data values, and output clock signals CLK 0 , CLK 90 , CLK 180  and CLK 270 , in accordance with one embodiment of the present invention illustrated by  FIG. 1 . 
       FIG. 3  is a circuit diagram illustrating a portion of an FPGA in accordance with another embodiment of the present invention. 
       FIG. 4  is a circuit diagram of a programmable delay line in accordance with one embodiment of the present invention illustrated by  FIG. 3 . 
       FIG. 5  is a waveform diagram illustrating an input clock signal CLK IN , output clock signals CLK 0 –CLK 16  and associated data values in accordance with one embodiment of the present invention illustrated by  FIG. 3 . 
   

   DETAILED DESCRIPTION 
     FIG. 1  is a block diagram of a semiconductor chip  100  in accordance with one embodiment of the present invention. In the described embodiments, semiconductor chip  100  is a programmable logic device, such as a field programmable gate array (FPGA). However, semiconductor chip  100  need not be a programmable logic device. FPGA  100  includes an array of configurable logic blocks (CLBs) and a programmable interconnect structure, which are illustrated as block  101 , a digital clock manager (DCM)  111 , and configurable input/output blocks (IOBs)  121 – 124 ,  131 – 134 ,  141 – 144  and  151 – 154 . In general, the elements of FPGA  100  are largely conventional, and are described in more detail in “Virtex™-II Platform FPGA Handbook”, available from Xilinx, Inc. As described in more detail below, the configuration of FPGA  100  significantly reduces transient currents during output switching. 
   FPGA  100  operates as follows in accordance with one embodiment of the present invention. First, FPGA  100  is configured to implement a desired circuit by programming configuration memory cells of the FPGA. DCM  111  is configured to provide four output clock signals CLK 0 , CLK 90 , CLK 180  and CLK 270  in response to an input clock signal CLK IN  during normal operation of FPGA  100 . Although DCM  111  generates four clock phases in the present embodiment, it is understood that DCM  111  can be modified to provide other numbers of clock phases in other embodiments. 
     FIG. 2  is a waveform diagram illustrating the input clock signal CLK IN , associated data values D 1 –D 4 , and the clock signals CLK 0 , CLK 90 , CLK 180  and CLK 270 . As illustrated by  FIG. 2 , the clock signals CLK 0 , CLK 90 , CLK 180  and CLK 270  are separated in phase by ninety degrees. In the described embodiment, the input clock signal CLK IN  and the clock signal CLK 0  are synchronized by DCM  111 . Thus, both the CLK IN  and CLK 0  signals exhibit rising edges at time T 0 . One-quarter period later, at time T 1 , the CLK 90  signal exhibits a rising edge, such that the CLK 90  signal lags the CLK 0  signal by 90 degrees. One-quarter period after time T 1  (at time T 2 ), the CLK 180  signal exhibits a rising edge, such that the CLK 180  signal lags the CLK 90  signal by 90 degrees. One-quarter period after time T 2  (at time T 3 ), the CLK 270  signal exhibits a rising edge, such that the CLK 270  signal lags the CLK 180  signal by 90 degrees. Note that data values D 1 [15:0] are clocked out of FPGA  100  during the clock period that includes times T 0 –T 3 . 
   In accordance with one embodiment, various IOBs of FPGA  100  are clocked with different clock signals. For example; IOBs  121 – 124  are clocked with the CLK 0  signal, IOBs  131 – 134  are clocked with the CLK 90  signal, IOBs  141 – 144  are clocked with the CLK 180  signal, and IOBs  151 – 154  are clocked with the CLK 270  signal. Thus, four bits of the D 1 [15:0] value (e.g., D 1 [3:0]) are clocked out through IOBs  121 – 124  at time T 0 , four bits of the D 1 [15:0] value (e.g., D 1 [7:4]) are clocked out through IOBs  131 – 134  at time T 1 , four bits of the D 1 [15:0] value (e.g., D 1 [11:8]) are clocked out through IOBs  141 – 144  at time T 2 , and four bits of the D 1 [15:0] value (e.g., D 1 [15:2]) are clocked out through IOBs  151 – 154  at time T 3 . Thus, only one fourth of the IOBs are clocked at any given time. This substantially reduces the transient current associated with output switching. Although the clock signals are applied to adjacent IOBs in an interleaved manner in the illustrated example, this is not required. For example, each of the IOBs located along a single edge of FPGA  100  (e.g., IOBs  121 ,  131 ,  141  and  151 ) can be coupled to receive the same clock signal. 
   Note that an external device attached to FPGA  100  must receive the input clock signal CLK IN , and in response, generate clock signals equivalent to the CLK 0 , CLK 90 , CLK 180  and CLK 270  signals. The external device must have a first set of input circuits coupled to receive the equivalent CLK 0  signal, a second set of input circuits coupled to receive the equivalent CLK 90  signal, a third set of input circuits coupled to receive the equivalent CLK 180  signal, and a fourth set of input circuits coupled to receive the equivalent CLK 270  signal. The first, second, third and fourth sets of input circuits are coupled to receive the data signals clocked out of IOBs  121 – 124 ,  131 – 134 ,  141 – 144  and  151 – 154 , respectively. The data values clocked out of IOBs  121 – 124 ,  131 – 134 ,  141 – 144  and  151 – 154  are then clocked into the first, second, third and fourth sets of input circuits of the external device in response to the equivalent CLK 0 , CLK 90 , CLK 180  and CLK 270  signals, respectively. 
     FIG. 3  is a circuit diagram illustrating a portion of a semiconductor chip  300  in accordance with another embodiment. In the described embodiment, semiconductor chip  300  is described as a programmable logic device, such as an FPGA (although this is not necessary). FPGA  300  and FPGA  100  include similar programmable logic resources. 
   The illustrated portion of FPGA  300  includes IOBs  301   0 – 301   N , DCM  311 , programmable delay lines  321   1 – 321   N , delay select register  340  and arithmetic unit (AU)  350 . DCM  311  includes delay select circuit  312 , delay line  313  and multiplexer  314 . Delay line  313  includes a plurality (X) of delay elements  315   1 – 315   X , which are connected in series as illustrated. The output terminals of delay elements  315   1 – 315   X  are coupled to input terminals of multiplexer  314 . 
   IOB  301   0  is configured to receive the CLK 0  signal from DCM  311 . IOB  301   0  clocks the input signal IN 1  and output signal O 0  in response to the CLK 0  signal. As described in more detail below, the CLK 0  signal is synchronized with the input clock signal CLK IN . In other embodiments, the CLK 0  can simply have a fixed phase relationship with respect to the CLK IN  signal. 
   The CLK 0  signal is propagated through delay lines  321   1 – 321   N , thereby creating delayed clock signals CLK 1 –CLK N , respectively. The delayed clock signals CLK 1 –CLK N  are provided to IOBs  301   1 – 301   N , respectively. Thus, IOBs  301   1 – 301   N , clock the respective input signals IN 1 –IN N  and output signals O 1 –O N , in response to delayed clock signals CLK 1 –CLK N , respectively. 
   In the described embodiment, each of delay lines  321   1 – 321   N  is programmed to introduce the same delay (although this is not necessary in all embodiments). The delay introduced by each of delay lines  321   1 – 321   N  is selected in response to a delay control signal M provided by register  340 . That is, the number of delay elements introduced by each of delay lines  321   1 – 321   N  is selected in response to delay control signal M. 
     FIG. 4  is a circuit diagram of delay line  321   1  in accordance with one embodiment of the present invention. In this embodiment, delay line  321   1  includes series-connected delay elements  401   1 – 401   Z  and multiplexer  402 . The CLK 0  signal propagates through delay elements  401   1 – 401   Z , thereby creating delayed clock signals CD 1 –CD Z , respectively. The CLK 0  signal and the delayed clock signals CD 1 –CD Z  are provided to input terminals of multiplexer  402 . Delay control signal M is provided to control terminals of multiplexer  402 . Multiplexer  402  routes one of the clock signals CLK 0 , CD 1 –CD Z  as the output clock signal CLK 1  in response to delay control signal M. For example, if the delay control signal M has a value of “3”, then multiplexer  402  routes the clock signal CD 3  as the CLK 1  signal, thereby introducing three delay elements (and three delay periods) to the path of the CLK 0  signal. In this manner, delay control signal M controls the delay introduced by delay line  321   1 . Each of delay elements  401   1 – 401   Z  can be implemented by a plurality of series connected inverters, or by other well known delay circuitry. In the described this embodiment, delay lines  321   2 – 321   N  are identical to delay line  321   1 . 
   Returning now to  FIG. 3 , DCM  311  provides the CLK 0  signal in response to the input clock signal CLK IN . More specifically, the CLK IN  signal is applied to delay line  313 . In response, delay elements  315   1 – 315   X  provide delayed clock signals C 1 –C X , respectively. The CLK IN  signal and the delayed clock signals C 1 –C X  are provided to input terminals of multiplexer  314 . Delay select circuit  312 , which is described in more detail below, provides delay select value Y to control terminals of multiplexer  314 . Multiplexer  314  routes one of the clock signals CLK IN , C 1 –C X  as the output clock signal CLK 0  in response to delay select value Y. 
   The signal routed by multiplexer  314  is provided as the CLK 0  signal. As described above, the CLK 0  signal is provided to IOB  301   0  and delay line  321   1 . The CLK 0  signal is also provided to an input terminal of delay select circuit  312  within DCM  311 . Delay select circuit  312  compares the CLK 0  and CLK IN  signals, and adjusts the delay select value Y until the CLK 0  signal is synchronized with the CLK IN  signal. That is, delay select circuit  312  adjusts the delay select value Y until the delay introduced to the CLK 0  signal is equal to one period of the CLK IN  signal. The delay select value Y identifies the number of delay elements  315   1 – 315   X  introduced to the path of the CLK 0  signal. Thus, when DCM  311  is locked, the delay select value Y identifies the number of delay elements  315   1 – 315   X  corresponding with one period of the CLK IN  signal. 
   The number of delay elements (Z) in each of programmable delay lines  321   1 – 321   N  is selected to be equal to a subset of the number of delay elements (X) in delay line  313 . In one embodiment, delay line  313  includes 128 delay elements (i.e., x=128), and each of programmable delay lines  321   1 – 321   N  includes 8 delay elements (i.e., Z=8). In one embodiment, the number N of delay lines coupled in series is selected such that the total number of delay elements in the series-connected delay lines  321   1 – 321   N  equals the total number of delay steps in delay line  313 . Thus, in the described embodiment, N is equal to 16 (i.e., 128/8). Note that the variables Z, X and N can have other values in other embodiments. 
   Each of the delay elements in programmable delay lines  321   1 – 321   N  is identical to the delay elements in delay line  313 . For example, each of the delay elements  315   1 – 315   X  in delay line  313  and each of the delay elements (e.g.,  401   1 – 401   Z ) in each of delay lines  321   1 – 321   N  may introduce a signal delay of 200 picoseconds. 
   The delay select value Y is also provided to arithmetic unit  350 . In response, arithmetic logic unit  350  divides the number of delay elements represented by delay select value Y by the number (N) of programmable delay elements  321   1 – 321   N , thereby creating a delay control value M that represents the number of delay elements to be inserted by each of the programmable delay lines  321   1 – 321   N . For example, if delay select value Y indicates that 42 delay elements (i.e., delay elements  315   1 – 315   42 ) are introduced to the path of the CLK IN  signal (i.e., the period of the CLK IN  signal is equal to 42 delay periods), then ALU  350  provides a delay control value M representative of the quotient of 42 and 16, or 2. Note that any fractional portion of the quotient is truncated. The delay control value M is stored in delay control register  340 , and is provided to each of delay lines  321   1 – 321   N . In the described example, each of programmable delay elements  321   1 – 321   N  introduces two delay periods in response to the delay control value M. 
     FIG. 5  is a waveform diagram illustrating the clock signals CLK IN , CLK 0 –CLK 16  and associated data values (e.g., D 1 [16:0]) in accordance with the described embodiment. As shown in  FIG. 5 , the CLK IN  and CLK 0  signals exhibit rising edges at time T 0 , and the CLK 1 –CLK 16  signals exhibit rising edges at times T 1 –T 16 , respectively. Delays of about 400 picoseconds (the delay associated with two delay elements) exist between the rising edges of the successive clock signals CLK 0 –CLK 16 . 
   As a result, the bits associated with data value D 1  are sequentially switched out of IOBs  301   0 – 301   16  in a “zipper-like” manner during a single cycle of the CLK IN  signal. Because these IOBs  301   0 – 301   16  are not simultaneously switched, the transient output switching current is greatly reduced (e.g., by a factor of 17). 
   Although only one set of IOBs  301   0 – 301   N  is illustrated in  FIG. 3 , it is understood that other identical sets of IOBs can be implemented in the same manner on the same FPGA. 
   When the temperature or other operating conditions of the FPGA change, the delay select value Y (i.e., the number of selected delay elements in delay line  313 ) may change dynamically. In this case, arithmetic logic unit  350  generates a new delay control value M (as appropriate) in response to the new delay select value Y. If a new delay control value M is generated (and stored in delay control register  340 ), then each of programmable delay lines  321   1 – 321   N  is adjusted in view of this new delay control value M. 
   Although the invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications, which would be apparent to one of ordinary skill in the art. For example, the number of programmable delay line  321   1 – 321   N  ( FIG. 3 ) can be selected during configuration of the FPGA. That is, each IOB can have an associated programmable delay line that may be selectively coupled or de-coupled from adjacent programmable delay lines during the configuration of the FPGA. Thus, the present invention is only limited by the following claims.