Abstract:
A method for forming first and second devices from first and second silicon bodies is described. A sacrificial layer allows gate regions to be defined with underlying insulating members. After the sacrificial layer and bodies are surrounded in a dielectric layer, the insulative member is removed from one of the bodies. After removal of the sacrificial layer, gate structures are formed. For one device, the gate surrounds three sides of the body, and for the other device two independent gates on the sides of the body result.

Description:
FIELD OF THE INVENTION 
     The invention relates to the field of semiconductor processing. 
     PRIOR ART AND RELATED ART 
     One relatively recent development in semiconductor processing is the independently-controlled double-gate (I-gate) transistor. This transistor has two gates disposed on opposite sides of a channel, each gate being independently controlled. Independent gate control provides some unique transistor characteristics and enables, for example, a single body, dynamic random-access memory (DRAM) cell. 
     Another relatively recent development in semiconductor processing is the tri-gate transistor. Here, a gate is formed on three sides of a channel region. This transistor, particularly when used with a high-k insulator and metal gate, provides substantial performance improvements. 
     Several I-gate structures have been proposed. This and other related technology is described at C. Kuo,  IEDM,  Dec. 2002, following M. Chan  Electron Device Letters,  Jan. 1994; C. Kuo,  IEDM,  Dec. 2002, “ A Hypothetical Construction of the Double Gate Floating Body Cell;”  T. Ohsawa, et al.,  IEEE Journal of Solid - State Circuits,  Vol. 37, No. 11, Nov. 2002; David M. Fried, et al., “ High - Performance P - Type Independent - Gate FinFETs,” IEEE Electron Device Letters,  Vol. 25, No. 4, Apr. 2004; and David M. Fried, et al., “ Improved Independent Gate N - Type FinFET Fabrication and Characterization,” IEEE Electron Device Letters,  Vol. 24, No. 9, Sep. 2003. 
     Tri-gate structures are described at, for instance, publication number U.S. 2004-0036127-A1. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a perspective view of a substrate which includes two silicon bodies with overlying insulative members 
         FIG. 1B  is a cross-sectional, elevation view of the structure of  FIG. 1  taken through section line  1 B- 1 B of  FIG. 1A . 
         FIG. 2A  illustrates the structure of  FIG. 1  following the patterning of a sacrificial layer. 
         FIG. 2B  is a cross-sectional, elevation view of the structure of  FIG. 2A  taken through section line  2 B- 2 B of  FIG. 2A . 
         FIG. 3  is a perspective view of the structure of  FIG. 2A  following the deposition of an interlayer dielectric (ILD). 
         FIG. 4A  is a perspective view of the structure of  FIG. 3  following planarization. 
         FIG. 4B  is a cross-sectional, elevation view taken through section line  4 B- 4 B of  FIG. 4A . 
         FIG. 5  is a perspective view of the structure of  FIG. 4  following the covering of a section of the substrate on which an I-gate transistor is fabricated. 
         FIG. 6A  is a perspective view of the structure of  FIG. 5  following an etching step. 
         FIG. 6B  is a cross-sectional view of the structure of  FIG. 6A  taken through section line  6 B- 6 B of  FIG. 6A . 
       FIG  7 A is a perspective view of the structure of  FIG. 6A  following removal of the patterned, sacrificial layer. 
         FIG. 7B  is a cross-sectional, elevation view of the structure of  FIG. 7A  taken through section in  7 B- 7 B of  FIG. 7A . 
         FIG. 8  is a cross-sectional, elevation view of the structure of  FIGS. 7A and 7B  following the formation of an insulative layer and a metal layer. 
         FIG. 9A  is a perspective view of the structure of  FIG. 8  following planarization of the metal layer. 
         FIG. 9B  is a perspective view of the structure of  FIG. 9A  with the ILD removed. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, the fabricating of an independently accessed, double-gate (I-gate) transistor and a tri-gate transistor on a common substrate is described. Numerous specific details are set forth, such as specific materials, in order to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art, that the present invention may be practiced without these specific details. In other instances, well known processing steps have not been described in detail, in order not to unnecessarily obscure the present invention. For example, well-known cleaning steps, and some protective layers often used in the fabrication of integrated circuits, are not described. 
     The method which follows describes the formation of both the I-gate transistor and a tri-gate transistor in a single process flow. While the fabrication of only a single I-gate transistor and a single tri-gate transistor are illustrated, it will be apparent to one skilled in the art, that in a typical integrated circuit, numerous such transistors are simultaneously fabricated. Moreover, the I-gate and tri-gate transistors may be fabricated wherever needed in the integrated circuit. Thus, a single circuit, such as a buffer, may have both I-gate and tri-gate transistors. In some cases, for example in a DRAM, an array of memory cells using only I-gate transistors may be fabricated and connected to peripheral circuits which use both I-gate and tri-gate transistors. A memory using I-gate memory cells is described in “Memory with Split-Gate Devices and Method of Fabrication,” Ser. No. 10/816,282, filed Mar. 31, 2004, and assigned to the assignee of the present application. 
     In one embodiment, the transistors are fabricated on an oxide layer  10  which is formed on a silicon substrate  12 . The transistor bodies are fabricated from a monocrystalline silicon layer  14  (shown in dotted lines in  FIGS. 1A and 1B ) disposed on layer  10 . This silicon-on-insulator (SOI) substrate is well-known in the semiconductor industry, where as shown, the layer  14  is disposed on the layer  10 . By way of example, the SOI substrate is fabricated by bonding the oxide layer  10  and a silicon layer  14  onto the substrate  12 , and then, planarizing the layer  14  so that it is relatively thin. This relatively thin, low body effect layer, is used to form the bodies of active devices, as mentioned. Other techniques are known for forming an SOI substrate including, for instance, the implantation of oxygen into a silicon substrate to form a buried oxide layer. In the subsequent cross-sectional views, the transistors are shown fabricated on the oxide layer  10 , the underlying silicon substrate  12  is not shown. 
     The layer  14  may be selectively ion-implanted with an n-type dopant in the regions where n channel devices are to be fabricated, and with a p type dopant in those regions where p channel devices are to be fabricated. This is used to provide the relatively light doping typically found in the channel regions of MOS devices fabricated in a CMOS integrated circuit. Both the I-gate and tri-gate transistors may be fabricated with the described process as either p channel or n channel devices. (The doping of the channel regions of the transistors may be done at other points in the process flow such as the point in the process shown in  FIG. 1A  or  7 A.) 
     In the processing for one embodiment, a protective oxide (not shown) is disposed on the silicon layer  14  followed by the deposition of a silicon nitride layer. The nitride layer is masked to define a plurality of insulative members, such as members  17  and  18  of  FIGS. 1A and 1B . Then, the underlying silicon layer  14  is etched in alignment with these members resulting in the silicon bodies  15  and  16 . 
     The width of the silicon bodies  15  and  16  may be the critical dimension in a particular process, for instance, in a 30 nanometer (nm) gate length process, these bodies may have a width of 30 nm. The thickness of the layer  14 , and the silicon nitride layer from which the members  17  and  18  are formed, may each be, by way of example, in the range of 10-50 nm. 
     Now, a sacrificial layer is deposited over the structure of  FIG. 1A  on the oxide layer  10 . In one embodiment, this layer is a polysilicon layer 50-100 run thick. Other materials may be used for the sacrificial layer. The material for the sacrificial layer should be able to protect the channel regions of the devices from ion implantation during the formation of the source and drain regions, as will be described. Moreover, the sacrificial layer should be able to be etched without destroying the integrity of an ILD formed around the sacrificial layer after patterning, as will be described. Additionally, the insulative members must be able to be selectively etched in the presence of the sacrificial layer. 
     Next, the sacrificial layer is patterned into gate-defining members shown as members  20  and  22  in  FIG. 2A . The member  20  occupies the region in which the two gates for the I-gate transistor is fabricated as well as “fins” for these gates to allow contact with the gates as shown later. The member  22  occupies the region in which the tri-gate is formed for the tri-gate transistor, as well as a fin, again for contact. 
     At this point in the processing, the silicon nitride members  17  and  18  may be etched in alignment with the member  20  and  22 , thereby exposing portions of the underlying silicon bodies  15  and  16 . As shown by the arrows  25 , the silicon bodies, to the extent they are not covered by the members  20  and  22 , are ion implanted to form source and drain regions for both the I-gate and tri-gate transistors. As is commonly done, but not shown, separate ion implantation steps are used for the p channel and n channel devices, with protective layers being used to permit separate implantation of the source and drains for the p channel and n channel devices. 
     Alternatively, the silicon nitride members  17  and  18  may remain in place, and the source and drain regions implanted at an angle, so that the dopant enters the sides of the silicon bodies  15  and  16 . 
     Additionally, spacers may be formed to allow a more lightly doped source and drain region to be implanted adjacent the channel region, and more heavily doped source and drain regions spaced apart from the channel region. This is described in the above-referenced application Ser. No. 10/816,282. 
     An ILD  30  is now formed on the insulative layer  10  as shown in  FIG. 3 . The ILD  30  surrounds the members  20  and  22 , and as will be seen, allows the inlay of metal once the polysilicon is removed. The ILD  30  may be, for instance, a chemical vapor deposited (CVD) silicon dioxide layer. 
     The structure of  FIG. 3  is now planarized, for instance, if a chemical mechanical polishing (CMP) process, so as to expose the silicon nitride insulative members  17  and  18 . This is illustrated in both  FIGS. 4A and 4B . Note, the members  17  and  18  are flush with the upper surface of the ILD  30 , as are the members  20  and  22 . 
     Now, a photoresist layer is deposited over the structure of  FIGS. 4A and 4B , and patterned so as to remain in place over the I-gate transistor region. The photoresist layer  50  covers the insulative member  17 . As shown in  FIG. 5 , the photoresist layer  50  leaves exposed insulative member  18  of the tri-gate device. 
     Then, as shown in  FIGS. 6A and 6B , an etching process is used to remove the plug-shaped silicon nitride member  18 . An etchant that discriminates between the silicon nitride and both the ILD  30  and sacrificial layer is used so that the ILD  30  and member  22  remains substantially intact. A dry or wet etchant may be used. Once the member  18  is removed, the underlying silicon body  16  as shown in  FIG. 6B  is exposed. 
     The polysilicon sacrificial layer is next removed with, for example, a wet etch process. The resultant structure is shown in  FIGS. 7A and 7B . The remaining ILD  30  now defines a form in which the gates for the transistors may be fabricated. 
     A gate dielectric layer  60  is formed on and around each semiconductor bodies  15  and  16  as seen in  FIG. 8 . Specifically, a gate dielectric may be deposited such that it covers the top surface of the semiconductor body  16  and the insulative member  17  as well as on the opposite side-walls of each of the semiconductor bodies. This gate dielectric, ideally has a high dielectric constant, such as a metal oxide dielectric, for instance, HfO 2  or ZrO or other high-k dielectrics, such as PZT or BST. A high-k dielectric film can be formed by any well-known technique such as by chemical vapor deposition (CVD). Alternatively, the gate dielectric can be a grown dielectric. In one embodiment, the gate dielectric layer  60  is a silicon dioxide film grown with a dry/wet oxidation process. For example, the silicon dioxide film is grown to a thickness of between 5-50 Å. (A conformally deposited dielectric layer is shown in  FIG. 8 .) 
     Next, as shown in  FIG. 8 , a gate electrode (metal) layer  61  is formed over the gate dielectric layer  60 . The gate electrode layer  61  may be formed by blanket deposition of a suitable gate electrode material. In one embodiment, a gate electrode material comprises a metal film such as Tungsten, Tantalum, Titanium and/or nitrides and alloys thereof. For the n channel, I-gate and tri-gate transistors, a work function in the range of 4.0 to 4.6 eV may be used. For the p channel, I-gate and tri-gate transistors, a work function of 4.6 to 5.2 eV may be used. Consequently, for substrates with both n channel and p channel transistors, two separate metal deposition processes may need to be used. 
     The metal layer  61  is planarized using, for example CMP, and such planarization continues until at least the upper surface of the insulative member  17  is exposed, as shown in  FIG. 9A . This is done in order to assure that no metal spans the member  17 , since otherwise, the gates in the I-gate transistor will be shorted together. As can be seen in  FIG. 9 , there are two independent gates  62  and  64  for the I-gate transistor, and a single gate  65  for the tri-gate device. 
     The gate  65  for the tri-gate transistor has a top surface opposite the bottom surface and has a pair of laterally opposite sidewalls formed adjacent the tri-gate structure best seen in  FIG. 9B . These sidewalls are connected on the upper surface of the silicon body. Thus, the gate surrounds the channel region of the tri-gate transistor on three sides. For the I-gate transistor, two independent gates  62  and  64  are separated by the insulative member  17 , again best seen in  FIG. 9B  where the ILD is shown removed. 
     Also, best seen in  FIG. 9B , the silicon bodies  15  and  16  are shown on the insulative layer  10 . Source regions  68  and  70  are shown for each of the transistors along with drain regions  71  and  72 . The independent gates  62  and  64  along with their orthogonally disposed fins are readily seen. The same is true for the gate  65 . These fins allow for easier contact to be made to the gates from overlying metalization layer, as shown by contact regions  80 ,  81  and  82 . While not shown in  FIG. 9B , contact is made to the source and drain regions as well as to the gates from overlying metalization layers through contacts not shown. 
     I-gate transistors may be used in logic circuits along with the tri-gate transistors. I-gate transistors have characteristics which make them desirable in certain circuits. For instance, a single I-gate transistor may provide both a high current and medium current device depending on the potential applied to one or both gates. Such devices may provide a “strong off” device to reduce leakage in a sleep mode or power-down mode. I-gate transistors also provide a device for pre-charge lines by allowing a trickle current. In the above-mentioned patent application, the I-gate devices are used as DRAM cells, and the process described above, may be used in connection with such DRAM fabrication. In this case, the silicon body  15  is an elongated body formed in a plurality of parallel, spaced-apart lines and used in an array of DRAM cells. 
     While in the figures two separate silicon bodies are shown, it will be appreciated that a single body may be used. Then, a tri-gate and I-gate transistor may be fabricated in series with one another In this case, the series transistors have a source/drain region. 
     Thus, a process has been described and a resultant structure for an integrated circuit having both an I-gate and tri-gate structure on a common substrate.