Abstract:
An interleave control device using a nonvolatile ferroelectric memory is disclosed. More specifically, a memory interleave structure using a nonvolatile ferroelectric register configured to individually control interleaves of banks is disclosed. In an embodiment of the present invention, interleaves of each bank can be individually controlled using a single nonvolatile ferroelectric memory chip, a multi-bank nonvolatile. ferroelectric memory chip or a multi-bank interleave nonvolatile ferroelectric memory chip.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention generally relates to a nonvolatile ferroelectric memory device, and more specifically, to a technology of stably controlling a power source applied to a cell capacitor, thereby improving a sensing margin.  
         [0003]     2. Description of the Prior Art  
         [0004]     Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FeRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory DRAM and conserves data even after the power is turned off.  
         [0005]     The FeRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes the characteristic of a high residual polarization of the ferroelectric substance in which data is not deleted even after an electric field is eliminated.  
         [0006]     The technical contents on the above FeRAM are disclosed in the Korean Patent Application No. 2002-85533 by the same inventor of the present invention. Therefore, the basic structure and the operation on the FeRAM are not described herein.  
         [0007]     Meanwhile, as the pattern size of a semiconductor memory device becomes smaller, an operation voltage of a CMOS device is reduced at the same ratio. When the operation voltage of the CMOS device drops, the power consumption of the semiconductor memory device is also reduced.  
         [0008]     In general, a capacitor included in the conventional FeRAM cell corresponds to a device which requires a relatively higher voltage. As a result, when the FeRAM cell is operated, a power voltage VCC is pumped to rise to an external power voltage VEXT level.  
         [0009]     However, since the external power voltage VEXT having a high voltage level is also applied to adjacent circuits which do not require the high voltage except a cell capacitor, the power consumption of the semiconductor memory device increases. In addition, the area of the whole system board also increases because an additional power supply circuit for controlling power of the memory cell is included in the outside of a chip.  
       SUMMARY OF THE INVENTION  
       [0010]     Accordingly, it is the first object of the present invention to improve a sensing margin of a cell and reduce unnecessary power consumption by controlling an operation voltage of the cell depending on an external supply voltage VEXT and applying a power voltage VCC obtained by dropping an external power voltage to adjacent circuits.  
         [0011]     It is the second object of the present invention to improve reliability of a capacitor at a high voltage by employing a ferroelectric capacitor for stabilizing power to obtain capacitance of high capacity with a small area.  
         [0012]     It is the third object of the present invention to simplify configuration of a system board and vary a regulation range of power by positioning a power supply circuit not in the outside but in the inside of a chip.  
         [0013]     In an embodiment, a nonvolatile ferroelectric memory device having a power control function comprises a voltage dropping unit, a nonvolatile ferroelectric circuit unit and a power stabilization unit. The voltage dropping unit drops an external power voltage to a predetermined level and supplies a power voltage. The nonvolatile ferroelectric circuit unit comprising a nonvolatile ferroelectric capacitor reads/writes data stored in a cell depending on the power voltage. The power stabilization unit removes noise from the power voltage applied from the voltage dropping unit and provides a stabilized voltage. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]     Other aspects and advantages of the present invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:  
         [0015]     FIGS.  1  to  3  are diagrams illustrating examples of a nonvolatile FeRAM device having a power control function according to an embodiment of the present invention;  
         [0016]      FIG. 4  is a diagram illustrating the operation of the nonvolatile FeRAM device having a power control function according to an embodiment of the present invention;  
         [0017]      FIG. 5  is a circuit diagram of a voltage dropping unit according to an embodiment of the present invention;  
         [0018]      FIG. 6  is a circuit diagram of a FeRAM circuit unit according to an embodiment of the present invention;  
         [0019]      FIG. 7  is a circuit diagram of a power stabilization unit according to an embodiment of the present invention;  
         [0020]      FIG. 8  is a circuit diagram of a FeRAM register unit according to an embodiment of the present invention;  
         [0021]      FIG. 9  is a timing diagram illustrating of the power-up operation of the FeRAM register unit of  FIG. 8 ;  
         [0022]      FIG. 10  is a timing diagram illustrating of the write operation of the nonvolatile FeRAM device having a power control function according to an embodiment of the present invention; and  
         [0023]      FIG. 11  is a timing diagram illustrating of the read operation of the nonvolatile FeRAM device having a power control function according to an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0024]     The present invention will be described in detail with the accompanying drawings.  
         [0025]      FIG. 1  is a diagram illustrating a first example of a nonvolatile FeRAM device having a power control function according to an embodiment of the present invention.  
         [0026]     In the first example, the nonvolatile FeRAM device comprises a voltage dropping unit  100 , a FeRAM circuit unit  200  and a power stabilization unit  300 .  
         [0027]     Here, the power dropping unit  100  drops an external power voltage VEXT applied externally to a predetermined level, and supplies a power voltage VCC. The FeRAM circuit unit  200  comprises cell arrays and a regulation circuit for driving the nonvolatile FeRAM device. The FeRAM circuit unit  200  drives a memory cell depending on the power voltage VCC supplied from the power dropping unit  100 . The power stabilization unit  300  removes noise generated from the power voltage VCC supplied from the power dropping unit  100 , and stabilizes the voltage.  
         [0028]      FIG. 2  is a diagram illustrating a second example of a nonvolatile FeRAM device having a power control function according to an embodiment of the present invention.  
         [0029]     In the second example, the nonvolatile FeRAM device comprises a voltage dropping unit  100 , a FeRAM circuit unit  200 , a power stabilization unit  300  and a power-up detection reset unit  400 . Here, the second example of  FIG. 2  further comprises the power-up detection reset unit  400  in comparison with the first example of  FIG. 1 .  
         [0030]     The power-up detection reset unit  400  detects a power-up voltage level, and generates a reset signal RESET to initialize the operation of the FeRAM circuit unit  200 . Here, the power-up detection reset unit  400  detects the power-up voltage level depending on the external power voltage VEXT at a power-up mode.  
         [0031]     As a result, the power-up detection reset unit  400  secures the stable operation of a chip while a voltage level of the reset signal RESET rises to that of the power voltage VCC. That is, when the voltage level of the reset signal RESET is at the level of the power voltage VCC, a margin of the voltage level for generating the reset signal RESET between the external power voltage VEXT and the power voltage VCC, thereby securing the stable operation of the chip.  
         [0032]      FIG. 3  is a diagram illustrating a third example of a nonvolatile FeRAM device having a power control function according to an embodiment of the present invention.  
         [0033]     In the third example, the nonvolatile FeRAM device comprises a voltage dropping unit  100 , a FeRAM circuit unit  200 , a power stabilization unit  300  and a power-up detection reset unit  400  and a FeRAM register unit  500 . Here, the third example of  FIG. 3  further comprises the FeRAM register unit  500  in comparison with the second example of  FIG. 2 .  
         [0034]     The operation of the FeRAM register unit  500  is controlled in response to the reset signal RESET applied from the power-up detection reset unit  400 . The FeRAM register unit  500  is controlled in response to the external power voltage VEXT.  
         [0035]     That is, when a cell of a common semiconductor device is operated, the power voltage VCC is pumped to rise to the level of the external power voltage VEXT. On the other hand, the FeRAM register unit  500  according to an embodiment of the present invention does not pump the power voltage VCC but uses the external power voltage VEXT directly.  
         [0036]      FIG. 4  is a diagram illustrating the operation of the nonvolatile FeRAM having a power control function according to an embodiment of the present invention.  
         [0037]     In an interval t 0 , a power is not supplied to a chip yet.  
         [0038]     When an interval t 1  starts, the level of the external power voltage VEXT starts to rise. Here, the interval t 1  is a redundant voltage interval where the reset signal RESET can be stably generated.  
         [0039]     Thereafter, when an interval t 2  starts, the reset signal RESET is generated, and the voltage level of the reset signal RESET reaches the level of the power voltage VCC so that the power voltage VCC is stably generated. Here, the power voltage VCC does not reach the voltage level of the external power voltage VEXT yet.  
         [0040]     When an interval t 3  starts, the power voltage VCC reaches the level of the external power voltage VEXT. As a result, the external power voltage VEXT is supplied to the inside of the semiconductor device.  
         [0041]      FIG. 5  is a circuit diagram of the voltage dropping unit  100  according to an embodiment of the present invention.  
         [0042]     The voltage dropping unit  100  comprises a voltage drop driving unit  110  and a switching unit  120 .  
         [0043]     Here, the voltage drop driving unit  110  comprises a plurality of diode devices D 1 ˜D 3  connected serially for sequentially dropping the external power voltage VEXT. Here, each of the plurality of diode devices D 1 ˜D 3  comprises a PN diode.  
         [0044]     The switching unit  120  determines which one of the plurality of diode devices D 1 ˜D 3  is used. The switching unit  120  comprises a plurality of switches SW 1 ˜SW 3  for controlling connection of the plurality of diode devices D 1 ˜D 3 .  
         [0045]     The voltage dropping unit  100  generates the dropped power voltage VCC depending on the selective usage number of the diode devices D 1 ˜D 3  serially connected. For example, when the switch SW 1  is connected, a short state is caused so that the diode device D 1  does not serve as a voltage dropping device. The other switches SW 2  and SW 3  which are disconnected can drop the external power voltage VEXT by the diode devices D 2  and D 3 .  
         [0046]     In an embodiment, an additional power supply circuit is positioned not in the outside of the chip but in the inside of the chip. As a result, the configuration of the system board is simplified, and the regulation range of the power is varied.  
         [0047]      FIG. 6  is a circuit diagram of the FeRAM circuit unit  200  according to an embodiment of the present invention.  
         [0048]     The FeRAM circuit unit  200  comprises a main bit line load control unit  210  and a plurality of sub cell arrays  220 .  
         [0049]     Here, the main bit line load control unit  210  comprises a PMOS transistor P 1  for controlling sensing load of a main bit line MBL. The PMOS transistor P 1  has a source to receive the power voltage VCC, a drain connected to the main bit line MBL and a gate to receive a main bit line control signal MBLC.  
         [0050]     The sub cell array  220  has a hierarchical bit line structure comprising a plurality of main bit lines MBL and a plurality of sub bit lines SBL. Each main bit line MBL of the sub cell array  220  is selectively connected to one of the plurality of sub bit lines SBL. That is, when one of a plurality of sub bit line selecting signals SBSW 1  is activated, a NMOS transistor N 5  is turned on to activated one of the sub bit lines SBL. Also, a plurality of cells C are connected to one of the sub bit lines SBL.  
         [0051]     When a sub bit line pull-down signal SBPD is activated to turn on a NMOS transistor N 3 , the sub bit line SBL is pulled down to a ground level. A sub bit line pull-up signal SBPU is to control a power supplied to the sub bit line SBL. That is, a voltage higher than the power voltage VCC is generated at a low voltage, and supplied to the sub bit line SBL.  
         [0052]     A sub bit line selecting signal SBSW 2  controls the connection between a sub bit line pull-up signal SBPU terminal and the sub bit line SBL depending on the switching operation of a NMOS transistor N 4 .  
         [0053]     A NMOS transistor N 2 , connected between a NMOS transistor N 1  and the main bit line MBL, has a gate to connected to the sub bit line SBL. The NMOS transistor N 1 , connected between a ground voltage terminal and the NMOS transistor N 2 , has a gate to receive a main bit line pull-down signal MBPD, thereby regulating the sensing voltage of the main bit line MBL.  
         [0054]      FIG. 7  is a circuit diagram of the power stabilization unit  300  according to an embodiment of the present invention.  
         [0055]     The power stabilization unit  300  comprises a capacitor CAP and a ferroelectric capacitor FC 1  For stabilizing the power voltage VCC.  
         [0056]     Here, the capacitor CAP, connected between the power voltage VCC terminal and the ground voltage terminal, has a NMOS gate capacitor structure. The ferroelectric capacitor FC 1  is connected in parallel to the capacitor CAP.  
         [0057]     Here, when the ferroelectric capacitor FC 1  which occupies a relatively small area for stabilization of the power voltage VCC is used to obtain capacitance of high capacity, the reliability of the capacitor can be improved at a high voltage.  
         [0058]     Here, the power stabilization unit  300  can comprise at least one of the capacitor CAP and the ferroelectric capacitor FC 1  in order to remove noise of the power voltage VCC or can use both of the capacitor CAP and the ferroelectric capacitor FC 1  if necessary.  
         [0059]      FIG. 8  is a circuit diagram of the FeRAM register unit  500  according to an embodiment of the present invention.  
         [0060]     The FeRAM register unit  500  comprises a PMOS transistor P 2  as a pull-up regulating device, memory cell  510 , and a NMOS transistor N 10  as a pull-down regulating device. Here, the memory cell  510  comprises a PMOS latch unit  511 , a write/read port selecting unit  512 , a ferroelectric capacitor unit  513  and a NMOS latch unit  514 .  
         [0061]     The PMOS transistor P 2 , connected between the external power voltage VEXT terminal and the memory cell  510 , has a gate to receive a pull-up enable signal ENP. Here, the PMOS transistor P 2  selectively supplies the external power voltage VEXT to the memory cell  510 .  
         [0062]     The PMOS latch unit  511  comprises PMOS transistors P 3  and P 4  having a latch structure located between the PMOS transistor P 2  and the write/read port selecting unit  512 . The PMOS transistors P 3  and P 4  are cross-coupled between nodes CN 1  and CN 2 .  
         [0063]     The write/read port selecting unit  512  comprises a NMOS transistor N 6  connected between the node CN 1  and the internal bit line /BL, and a NMOS transistor N 7  connected between the node CN 2  and the internal bit line BL. A common gate of the NMOS transistors N 6  and N 7  is connected to the word line WL.  
         [0064]     Here, the internal bit lines BL and /BL can be used as terminals for reading/writing data in the memory cell  510  or as terminals connected to a random external driver.  
         [0065]     The ferroelectric capacitor unit  513  comprises ferroelectric capacitors FC 2 , FC 3 , FC 4  and FC 5 . The ferroelectric capacitor FC 2  has one terminal connected to the node CN 1 , and the ferroelectric capacitor FC 3  has one terminal connected to the node CN 2 . The other terminals of the ferroelectric capacitors FC 2  and FC 3  receive a cell plate signal CPL in common. The ferroelectric capacitor FC 4  has one terminal connected to the node CN 1 , and the ferroelectric capacitor FC 5  has one terminal connected to the node CN 2 . The other terminals of the ferroelectric capacitors FC 4  and FC 5  receive a ground voltage in common. Here, the ferroelectric capacitors FC 4  and FC 5  can be selectively used depending on loading level control of the nodes CN 1  and CN 2 .  
         [0066]     The NMOS latch unit  514  comprises NMOS transistors N 8  and N 9  located between the ferroelectric capacitor unit  513  and a NMOS transistor N 10 . The NMOS transistors N 8  and N 9  are cross-coupled between the nodes CN 1  and CN 2 .  
         [0067]     The NMOS transistor N 10 , connected between the memory cell  510  and the ground voltage VSS terminal, has a gate to receive a pull-down enable signal ENN.  
         [0068]     As described above, the memory cell  510  comprises the PMOS latch unit  511  comprising two transistors, the write/read port selecting unit  512  comprising two transistors, and the NMOS latch unit  514  comprising two transistors.  
         [0069]     Additionally, the memory cell  510  comprises four ferroelectric capacitors FC 2 ˜FC 5  for storing nonvolatile data and controlling sensing load. Therefore, the memory cell  510  of  FIG. 8  has a 6T4C structure including 6 transistors and 4 capacitors.  
         [0070]      FIG. 9  is a timing diagram illustrating of the power-up operation of the FeRAM register unit of  FIG. 8 .  
         [0071]     After a power-up, in an interval T 1 , if the power voltage reaches the stabilized external power voltage VEXT level, the reset signal RESET is disabled, and a power-up detecting signal PUP is enabled to the external power voltage VEXT level.  
         [0072]     Thereafter, the cell plate signal CPL is enabled to the external power voltage VEXT level in response to the power-up detecting signal PUP. Here, charges stored in the ferroelectric capacitors FC 2  and FC 3  of the FeRAM register unit  500  generate a voltage difference in both nodes of the cell by capacitance load of the ferroelectric capacitors FC 4  and FC 5 .  
         [0073]     When an interval T 2  where a sufficient voltage difference is generated in both nodes of the cell starts, the pull-down enable signal ENN is enabled to the external power voltage VEXT level. Then, the pull-up enable signal ENP is disabled to ‘low’, thereby amplifying data of both terminals of the cell.  
         [0074]     Thereafter, when an interval T 3  starts and the data amplification of both terminals of the cell is completed, the power-up detecting signal PUP and the cell plate signal CPL transit to ‘low’ again.  
         [0075]     As a result, destroyed high data of the ferroelectric capacitor FC 2  or FC 3  are restored. Here, the word line WL is maintained at the low level to prevent external data from being written in the cell.  
         [0076]      FIG. 10  is a timing diagram illustrating of the write operation of the nonvolatile FeRAM having a power control function according to an embodiment of the present invention.  
         [0077]     When an interval t 1  starts, an address is inputted, a chip selecting signal CSB and a write enable signal /WE are disabled to ‘low’, the nonvolatile ferroelectric memory becomes at a write mode active state. The sub bit line pull-down signal SBPD and the main bit line control signal MBLC are disabled to ‘low’, the power voltage VCC is applied to the main bit line MBL. Here, the main bit line pull-down signal MBPD is enabled.  
         [0078]     Thereafter, when an interval t 2  starts, the word line WL and a plate line PL are enabled to the external power voltage VEXT level, the voltage levels of the sub bit line SBL and the main bit line MBL rise.  
         [0079]     When an interval t 3  starts, a sense amplifier enable signal SEN is enabled, and cell data applied to the main bit line MBL.  
         [0080]     Thereafter, when an interval t 4  starts, the plate line PL is disabled to ‘low’, the sub bit line selecting signal SBSW 2  is enabled to the power voltage VCC level. Then, the sub bit line pull-down signal SBPD is enabled to ‘high’, and the sub bit line SBL is disabled to ‘low’ Here, the main bit line pull-down signal MBPD is disabled to ‘low’, and the main bit line control signal MBLC is enabled.  
         [0081]     Next, in an interval t 5 , effective data are applied to the cell, and hidden data “1” is written. Then, the voltage of the word line WL rises, and the sub bit line selecting signal SBSW 2  is enabled to the pumping voltage level VPP level in response to the sub bit line pull-up signal SBPU. As a result, the voltage level of the sub bit line SBL rises to the external power voltage VEXT level.  
         [0082]     In an interval t 6 , data are written in response to the write enable signal /WE. When the interval t 6  starts, the plate line PL is enabled to the external power voltage VEXT level again. Then, the sub bit line selecting signal SBSW 1  is enabled to the power voltage VCC level, and the sub bit line selecting signal SBSW 2  is disabled, thereby writing new data in a page cell.  
         [0083]     When an interval t 7  starts, the word line WL, the plate line PL, the sub bit line selecting signal SBSW 1 , the sub bit line pull-up signal SBPU and the sense amplifier enable signal are disabled. Then, the sub bit line pull-down signal SBPD is enabled.  
         [0084]      FIG. 11  is a timing diagram illustrating of the read operation of the nonvolatile FeRAM having a power control function according to an embodiment of the present invention.  
         [0085]     In the read mode, the write enable signal /WE is maintained at the power voltage VCC level. In intervals t 2  and t 3 , data are sensed. In an interval t 5 , hidden data “1” is written, and high level data are written in all cells of the page. During intervals t 6 ˜t 8 , data output effective period is maintained.  
         [0086]     In the interval t 6 , the plate line PL transits to ‘high’, the sub bit line selecting signal SBSW 1  transits to ‘high’, and restoration data are written in the cell of the page.  
         [0087]     As described above, in the write/read operations according to an embodiment of the present invention, the external power voltage VEXT is supplied to the word line WL, the plate line PL, the sub bit line pull-up signal SBPU and the sub bit line SBL, thereby increasing the operation voltage of the cell.  
         [0088]     Accordingly, a nonvolatile FeRAM device according to an embodiment of the present invention provides the following effects: to improve a sensing margin of a cell and reduce unnecessary power consumption by controlling an operation voltage of the cell depending on an external supply voltage VEXT and applying a power voltage VCC obtained by dropping an external power voltage to adjacent circuits; to improve reliability of a capacitor at a high voltage by employing a ferroelectric capacitor for stabilizing power to obtain capacitance of high capacity with a small area; and to simplify configuration of a system board and vary a regulation range of power by positioning a power supply circuit not in the outside but in the inside of a chip.  
         [0089]     While the invention is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, it should be understood that the invention is not limited to the particular forms disclosed. Rather, the invention covers all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined in the appended claims.