Abstract:
Multi-band fractional-N PLL synthesizers with built-in spurious sideband compensation, which tracks the VCO output, tend to consume large amounts of power (as much as 10 times) due to the RF operation of the compensation circuitry. This patent introduces a dynamic power approach where the compensation circuitry is biased only during the fractional portion of the cycle. This technique provides the advantages of fractional-N synthesizers with spur suppression, such as higher speed and lower phase noise with ultra low power dissipation.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to frequency tracking in fractional-N phase-lock-loops (PLLs) and more specifically to the generation of a low-power fractional compensation pulse used in the suppression of spurious sidebands in these PLL circuits. 
     2. Brief Description of the Prior Art 
     Fractional-N synthesizers have become popular in many wireless transceiver applications due to their good RF performance. Standards such as GSM, IS-136, PHS, and PDC are all based on time division multiple access (TDMA) techniques, where low phase noise and fast switching from one channel to another is imperative to meet system sensitivity and time-slot requirements. 
     FIG. 1 shows a typical architecture for the conventional type integer-N PLL used predominantly in the wireless market today. In this conventional scheme, N is an integer number. In this circuit, the reference frequency ƒ R , which is divided down by reference divider  2  from the crystal  1 , drives the phase frequency detector (PFD)  3  as does the feedback signal ƒ v , which is the output frequency ƒ o  from the voltage controlled oscillator (VCO)  6 , divided by integer N in the main divider  7 . The output of the charge pump  4  is coupled to filter  5  to provide a dc voltage to the VCO  6 . In conventional type PLL synthesizers, the phase frequency detector (PFD) comparison frequency must be equal to the channel spacing because the main divider can only increment or decrement in integer steps; i.e., 
     
       
         ƒ o =N·ƒ R , and  Eq. 1 
       
     
     
       
         Δƒ o =ƒ ch =ƒ R .  Eq. 2 
       
     
     On the other hand, the main divider in a fractional-N synthesizer, shown in FIG. 2, is capable of generating steps in fractions of the comparison frequency, so that 
     
       
         ƒ o =N eff ·ƒ R   Eq. 3 
       
     
     where the total effective division ratio, N eff , is given as                  N   eff     =     N   +     x   m         ,   where           Eq. 4                                      x   m                           
     represents the fractional portion of the equation and is produced by incrementing an L-bit accumulator in a continuous fashion by x amount at the reference rate up to the maximum count m. 
     In this circuit, the L-bit accumulator  8  will overflow at the rate of            f   R     ·     x   m       ,   where                          
     m=2 L  is the maximum count for the accumulator. 
     The circuit for the fractional-N synthesizer looks much like that for the integer-N synthesizer discussed above, but now the main divider  7  is capable of switching from divide by N to divide by N+1 based on the overflow conditions of an L-bit accumulator  8 . As a result the channel spacing is related to the comparison frequency ƒ R  as N or x changes for a specific m as                  Δ                   f   o       =       f   ch     =       [       (     N   +     x   m       )     -     (     N   -       x   -   1     m       )       ]          f   R           ,   or           Eq. 5                 f   ch     =         f   R     m     .             Eq. 6                                
     The principle of operation for the fractional-N synthesizer is based on the fact that the main divider  7  will divide by N while the L-bit accumulator  8  is incrementing until an accumulator overflow occurs, at which point the main divider  7  will divide by N+1, resulting in the N eff  fractional division ratio given in Eq. 4. From Eqs. 2 and 6 it is seen that the comparison frequency in fractional-N PLL synthesizers is m-times higher than in the conventional integer-N synthesizer and from Eq. 3 it is seen that for a constant RF output frequency, ƒ o , this higher comparison frequency will result in a lower division ratio, N eff . 
     It is well known in the art that in a PLL based system with constant PFD phase noise (£), the so called “close-in noise” (the synthesizer noise floor within the loop bandwidth) is directly proportional to the division ratio, so that 
     
       
         £=PFD(phase noise)+20 log(N),  Eq. 7 
       
     
     in dBc/Hz. 
     Therefore, reducing the division ratio N eff  by adopting fractional-N techniques, as discussed above, results in lower phase noise in the synthesizer. In addition, the higher comparison frequency in the fractional-N type synthesizer provides faster switching times since the loop bandwidth can be made wider as a result of the comparison spurs being further out in the spectrum. For example, in a modulus 8 (m=8) fractional-N synthesizer there is a phase noise improvement of 
     
       
         20 log(m)=20 log(8)=18 dB, and  Eq.8 
       
     
     for a channel spacing of 30 KHz, the comparison frequency is increased to 
     
       
         ƒ n =ƒ ch ·m=30·8=240 Khz.  Eq. 9 
       
     
     The timing diagram for a fractional-N synthesizer with m=8 and x=2 is shown in FIG.  3 . Because the main divider  7  operation is integer in nature but on average a fractional part is introduced due to the switching from divide by N to divide by N+1, the output of the main divider  7 , ƒ v , is phase modulated with a fractional-N phase ripple. Unfortunately, this phase ripple shows up at the output of the phase detector and results in pulse width modulated (PWM) current, I cp , out of the charge pump  4 . If left uncompensated, this ripple current produces sideband energy in the output VCO spectrum which is considered the major problem with fractional-N PLL synthesizers. 
     FIG. 4 shows a fractional compensation circuit that compensates for this PWM phase ripple in the I cp  current and significantly reduces the magnitude of the fractional-N sidebands. In this case, the PWM phase ripple is proportional and synchronized to the contents of the L-bit fractional accumulator  8 , and as a result can be used to control the fractional-N sideband compensation pulse amplitude. In this circuit, fractional timing circuitry  11 , a fractional charge pump  10  and a digital to analog converter (DAC)  9  are added to the conventional-N PLL circuit. The fractional pulses, which are driven at a constant rate from the crystal  1 , have constant width and their amplitude is modulated. The content of the L-bit accumulator  8  is feed through a digital-to-analog converter (DAC)  9  and used to modulate the amplitude of the compensation current (I comp ), which is generated by the fractional charge pump  10 . Special fractional timing circuitry  11 , running at a fixed frequency from the crystal  1  and controlled by the ƒ v  signal from main divider  7 , generates the fixed-width fractional compensation pulse which in turn drives the fractional charge pump  10 . The theory is that the PAM output from the fractional charge pump  10  cancels the spurious PWM signals from the main charge pump  4 . 
     FIG. 5 shows the relationship between the I cp  (PWM) pulse, the I comp  (PAM) pulse, the fractional compensation pulse T FP , and the accumulator count. To properly minimize the fractional-N sidebands in the VCO spectrum, it is essential that the area under the main charge pump  4  pulse (I cp ), which represents the amount of charge delivered to the loop filter, is equally matched to the area of the fractional charge pump  10  pulse (I comp ). The fractional timing circuitry  11  provides a fractional compensation pulse which is precisely positioned such that it always encloses the short current pulses of the main charge pump, I cp  This compensation method works effectively for single band applications, but due to the fixed width of the compensation pulse which is driven from the fixed frequency crystal, it is ineffective for dual-channel or multi-channel operation. 
     SUMMARY OF THE INVENTION 
     Fractional-N PLL synthesizers are finding greater use today due to their lower phase noise and higher speed compared to conventional integer-N synthesizers. One problem with these synthesizers is the presence of sideband spurious charge pulses, known as spurs. In conventional fractional-N PLLS, fractional compensation circuitry is used to suppress these spurs. However, this compensation circuitry is usually driven from a fixed frequency reference, such as a crystal, and as a result is not very effective in modern multi-band (multi-frequency) applications. This has brought about the need for fractional compensation circuitry which tracks the VCO frequency so as to provide effective spur suppression across all bands of operation. 
     Since these new fractional compensation circuits are driven at RF frequencies from the VCO, they tend to consume larger amounts of power which is somewhat undesirable for portable wireless products such as a cellular phone. To address this issue, the present invention introduces a new low power dynamic approach to sideband spur suppression. The circuitry generates fractional pulse width compensation pulses with VCO frequency tracking characteristics, but at the same time requires as little as one-tenth normal power. The principle of operation for this technique is to apply power to the divider chain and control logic portion of the compensation circuitry during the fractional divide by N+1 time period and then idle the power back during the normal divide by N time period. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The included drawings are as follows: 
     FIG. 1 shows a block diagram for an integer-N PLL based frequency synthesizer. (prior art) 
     FIG. 2 shows a basic block diagram for a fractional-N PLL based frequency synthesizer. (prior art) 
     FIG. 3 is a fractional-N timing diagram showing PFD phase ripple for x=2 and m=8. (prior art) 
     FIG. 4 is the block diagram of a fractional-N PLL synthesizer with fractional compensation circuitry. (prior art) 
     FIG. 5 illustrates the fractional-N multi-band compensation approach for x=2 and m=8. (prior art) 
     FIG. 6 shows a block diagram of the fractional-N PLL synthesizer with frequency tracking compensation scheme according to a preferred embodiment of the invention. 
     FIG. 7 shows a functional block diagram for the proposed low power dynamic switching technique used in the fractional pulse generation of the present invention. 
     FIG. 8 shows a typical schematic diagram of the new proposed low power fractional pulse generation scheme of the present invention. 
     FIG. 9 is a timing diagram illustrating the dynamic functionality of the low power fractional pulse generation scheme of the present invention. 
     FIG. 10 is a block diagram for a wireless transceiver showing where the PLL of the present invention is used. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In single-band fractional-N synthesizers, the fractional compensation pulse has a fixed pulse width, T FP , which is often derived from the crystal  1  (T cxo ) reference (typically 10 to 20 MHz) after being scaled by the reference divider  2 . However, for multi-band synthesizers this approach of using a fixed pulse width fractional compensation pulse fails when additional channels (frequencies) are selected. For multi-band fractional-N synthesizers, the fractional compensation pulse width needs to track the VCO output in order to guarantee that the charge matching requirements are met at all frequencies, as shown earlier in FIG.  5 . 
     FIG. 6 shows an expanded block diagram for the fractional-N PLL synthesizer with frequency tracking compensation circuitry which is explained in copending application No. TI-28060, herein incorporated by reference, which is the basis for the present invention. The important thing is that in this case the fractional timing block  20  generates a fractional pulse whose width tracks the VCO period as 
     
       
         T FP =F·T VCO ,  Eq. 10 
       
     
     where F is an integer number which is a multiple of 2 that is introduced within the fractional timing circuitry  20 . A normal value for F is 128 which leads to the following pulse widths, T FP , for typical applications; 
     
       
         T FP =64 in PCS mode applications where ƒ VCO ≈2 GHz, and 
       
     
     
       
         T FP =128 in Cellular mode where ƒ VCO ≈1 GHz. 
       
     
     This fractional timing block  20  is comprised basically of a divide by F (typically 128) circuit  12 , synchronization circuitry  13 , and control logic  14 . The current switch  15  is added to provide dynamic power control of the circuit, which is the primary function of the present invention. The variable width of the compensation pulse results in an effective cancellation of the sideband spurious pulses. Also in the circuit, the main divider  7  is comprised of a prescaler  16 , along with blocks A ( 17 ) and B ( 18 ) which are used to generate a divide-by-N, such that: 
     
       
         N=P*B+A, where P may typically equal 32.  Eq. 11 
       
     
     However, since the compensation circuitry in this approach is driven at the higher VCO output frequency, there is a considerable power increase involved. A feasibility study shows that the generation of such a pulse train, established at RF VCO frequencies (1-2 GHz), requires a total current of 1.5 to 2.0 mA within the divider chain and control logic circuitry. To address this issue, the approach of the present invention features a new dynamic switching scheme to cut down the required power dissipation and as a result provides a power savings of greater than 10 times. The present low power dynamic scheme is conceptually explained in the block diagram of FIG.  7 . There are basically four primary blocks involved, as follows: 
     1. a timing or synchronization D-type flip-flop  13  that delays the reference divider output signal (DIV_R) by one T cxo  cycle and synchronizes it to the positive edge of the T cxo  out signal. The output of this flip-flop is applied to the PFD_R input of phase detector  3 . 
     2. an F counter 12 which divides the VCO output frequency by a factor of F, typically 128. 
     3. a logic control circuit  14  which is a SR flip-flop that initiates the counter functionality on the positive edge of the DIV_R signal and then inhibits the high speed counter once the required pulse width is generated. 
     4. a transistor switch  15 , controlled by the control logic circuit  14 , which allows current to flow from a constant current source  19  to the fractional compensation circuitry during the overflow period, and then prevents current from flowing to this part of the circuit the rest of the time. 
     The low power feature of this new architecture stems from the dynamic operation of the fixed modulus divide by F (typically F=128) prescaler  12  that starts its high speed division cycle upon receiving a “1” at the circuit&#39;s overflow DIV_R input which sets the SR flip-flop  14 , thereby applying proper bias to all the divider chain circuitry. FIG. 8 shows a schematic diagram for the divider chain which is comprised of the synchronization circuitry  13 , the divide by F circuit  12 , the control logic  14 , and current source and switching circuitry  15 . The fractional pulse is generated once the divider  12  reaches it maximum count of 128, whereby a reset signal resets the SR flip-flop  14 . This in turn disables the prescaler flip-flops and other circuitry of FIG. 8 by shutting off the current source that feeds the CML, ECL, and ECL-to-CMOS circuits until the next DIV_R pulse occurs and so on. 
     The power savings achieved by this dynamic technique, whose functionality is illustrated by the timing diagram of FIG. 9, can be estimate as follows: 
     Assuming an example in the PCS mode where 
     
       
         ƒ R =240 KH/z T≅4.17 μS, 
       
     
     
       
         ƒ VCO ≈2 GH/z T VCO ≈0.5 nS, 
       
     
     
       
         F=128 and P=32. 
       
     
     Then for the worst case scenario, the fractional timing block  20  will be “ON” for a time t ON  determined by 
     (1) the T cxo  pulse width                T   CXO     =       1     f   TXO       =       1     20                 MHz       =     50                 nS                 and                 Eq. 12                                
     (2) the fractional pulse width 
     
       
         T FP =F·T vco =128·0.5 nS=64 nS, and  Eq. 13 
       
     
     as shown in FIG.  9 . So, in the worst case 
     
       
         t ON =T CXO +T FP , which is  Eq. 14 
       
     
     
       
         t ON =50 nS+64 nS=114 nS. 
       
     
     The average current is then                  I   avg     =         t   ON     T          (       ∑     I   ECL_FF       +     I   ECL_CMOS     +     ∑     I   CMOS         )         ,           Eq. 15                                
     and based on typical current values of 
     
       
         Σ I ECL     —     FF =1.4 mA  Eq. 16 
       
     
     
       
         I ECL     —     CMOS =0.2 mA  Eq. 17 
       
     
     
       
         Σ I CMOS =1.0 mA  Eq. 18 
       
     
     the average current is estimated to be                I   avg     =         114   4160     ·     (       1.4                 mA     +     0.2                 mA     +     1.0                 mA       )       =     40                 μ                   A   .                 Eq. 19                                
     In addition, since the fractional timing block is biased from a continuous current source of 50 μA, the net total current is therefore 
     
       
         I FRAC     —     BLOCK =50 μA+70 μA=120 μA.  Eq. 20 
       
     
     Thus, the power for the compensation circuitry is reduced by more than one order of magnitude. 
     FIG. 10 shows a block diagram for a typical wireless transceiver (celluar phone) which uses the low power fractional-N synthesizer of this patent. The system is comprised of the receiver (R x ) and transmitter (T x ) RF/IF portions, the baseband controller functions, the power supply, and the user input/output functions. Of particular interest relative to this invention is the phase-lock-loop (PLL)  21  circuit which features the fractional-N synthesizer with dynamic power spurious sideband suppression circuitry. Both fixed-band and particularly multi-band wireless transceivers, such as this, will benefit significantly from the improved switching time, reduced phase noise, reduced reference feedthrough, and lower power operation gained from the use of the fractional-N PLL with fractional spur suppression of this patent. Although this represents one important application which can benefit from the use of the fractional-N PLL approach of the present invention, many other uses where high speed, low noise PLL&#39;s are required will benefit as well. 
     While the invention has been described in the context of a preferred embodiment, it will appear to those skilled in the art that the present invention may be modified in numerous ways and may assume many embodiments other than that specifically set out and described above. Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.