Abstract:
A clock network for an integrated circuits includes a first set of lines configured to distribute clock signals to a first section of the integrated circuit. The clock network also includes a second set of lines configured to distribute clock signals to a second section of the integrated circuit separately from the first section of the integrated circuit.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
   The present application claims the benefit of earlier filed provisional application U.S. Ser. No. 60/289,244, entitled HIGH SPEED PROGRAMMABLE CLOCK TREE, filed on May 6, 2001, the entire content of which is incorporated herein by reference. 

   BACKGROUND 
   1. Field of the Invention 
   The present invention generally relates to clock networks, and more particularly to clock networks for integrated circuits. 
   2. Description of the Related Art 
   Clock networks, which are also known as clock trees, are used in integrated circuits to distribute clock signals. More particularly, in conventional clock networks, input-clock signals are received through dedicated clock-input pins. The clock signals are then distributed throughout the integrated circuit using a network of lines and drivers. Conventional clock networks also typically include multiple layers of buffers to reduce clock skew. 
   One shortcoming of conventional clock networks is that clock signals are distributed to all areas of an integrated circuit, even those that may not need to receive the clock signals. This can result in inefficient and undesirable use of power as clock networks are typically one of the most-demanding components of integrated circuits. 
   Another shortcoming of conventional clock networks is that input-clock signals are only received through dedicated clock-input pins. This limits both the number and type of clock signals that can be carried by the clock network. 
   SUMMARY 
   The present invention relates to a clock network for integrated circuits. In accordance with one aspect of the present invention, the clock network includes a first set of lines configured to distribute clock signals to a first section of the integrated circuit. The clock network also includes a second set of lines configured to distribute clock signals to a second section of the integrated circuit separately from the first section of the integrated circuit. In accordance with another aspect of the present invention, the clock network can receive input-clock signals from input pins on the integrated circuit that are not designated input-clock pins. 

   
     DESCRIPTION OF THE DRAWING FIGS 
     The present invention can be best understood by reference to the following description taken in conjunction with the accompanying drawing figures, in which like parts may be referred to by like numerals: 
       FIG. 1  is a simplified block diagram of an exemplary clock network embodied within a programmable logic device (PLD); 
       FIG. 2  is a simplified block diagram of another exemplary clock network embodied within a PLD; 
       FIG. 3  is a portion of the block diagram depicted in  FIG. 1 ; 
       FIG. 4  is a portion of the block diagram depicted in  FIG. 2 ; 
       FIG. 5  is a schematic of a portion of the block diagram depicted in  FIG. 1 ; 
       FIG. 6  is a block diagram of a portion of the block diagram depicted in  FIG. 1 ; and 
       FIG. 7  is a block diagram of another portion of the block diagram depicted in  FIG. 1 . 
   

   DETAILED DESCRIPTION 
   In order to provide a more thorough understanding of the present invention, the following description sets forth numerous specific details, such as specific configurations, parameters, and the like. It should be recognized, however, that such description is not intended as a limitation on the scope of the present invention, but is intended to provide a better description of exemplary embodiments. 
   With reference to  FIG. 1 , in one exemplary embodiment of the present invention, a clock network  100  is depicted as embodied within a programmable logic device (PLD)  102 . Although the following description describes clock network  100  with respect to its use in PLD  102 , it should be recognized that clock network  100  can be used in any integrated circuit. 
   As depicted in  FIG. 1 , PLD  100  includes sets of logic array blocks (LABs)  104 , which are grouped sets of programmable logic resources. More particularly, with reference to  FIG. 3 , each set of LABs  104  includes a plurality of logic array blocks (LABs)  302  that have logic elements that can be configured or programmed to perform logical functions, such as AND, OR, NOT, XOR, NAND, NOR, and the like. 
   With reference again to  FIG. 1 , it should be recognized that PLD  102  can include any number of programmable logic resources arranged in various configurations with an interconnect structure. Furthermore, PLD  102  can be known by various names or terms, such as PAL, PLA, FPLA, EPLD, CPLD, EEPLD, LCA, FPGA, and the like. Additionally, PLD  102  can be a component of various electronic systems, such as a PDA, cell phone, and the like. 
   As will be described in greater detail below, clock network  100  includes a plurality of signal paths, also referred to as lines, that distribute signals to various regions of PLD  102 . More particularly, in the present embodiment, clock network  100  includes spine lines  106 , input-clock lines  110 , global-clock lines  112 , local-clock lines  114 , and regional-clock lines  118 . It should be recognized, however, that clock network  100  can include any number and types of lines arranged in various configurations. 
   As depicted in  FIG. 1 , clock network  100  can be segmented into a number of regions. More particularly, in the present embodiment, PLD  102  and clock network  100  are segmented into quadrants. Although four quadrants are depicted and described below, it should be recognized that PLD  102  and clock network  100  can be segmented into any number of regions. 
   As will be described below, clock network  100  can distribute various types of signals selectively to different regions of PLD  102 . More particularly, clock network  100  can distribute a signal that is common to all of the regions of PLD  102  (a global signal); a signal that is specific to one or more regions (a local signal), a signal distributed within a specific region (a regional signal), and a signal that is specific to a portion of one region (a local signal). It should be recognized that the names for these different types of signals are somewhat arbitrary and that various other names can be used. 
   One type of signals that can be distributed through clock network  100  are clock signals. In the present embodiment, clock network  100  can distribute global-clock signals, regional-clock signals, local-clock signals, and fast-clock signals. The global-clock signals can be distributed to all regions of PLD  102  through global-clock lines  112 . The local-clock signals can be distributed to one or more regions of PLD  102  through local-clock lines  114 . The regional-clock signals can be distributed within a region of PLD  102  through regional-clock lines  118 . The fast-clock signals can be distributed to a particular area within a region of PLD  102  through spine lines  106 . In this manner, a wide selection of clock signals can be provided to different areas or regions of PLD  102 . Additionally, different areas or regions of PLD  102  can be selectively provided with clock signals. As such, a specific area or region of PLD  102  can be provided with clock signals without having to provide all area or regions of PLD  102  with clock signals, which has the advantage of reducing the amount of power consumed. 
   As also described below, another type of signals that can be distributed through clock network  100  are general-purpose routing signals. One advantage to using clock network  100  for distributing general-purpose routing signals is that clock network  100  may typically have less loading than the routing lines of PLD  102 . Additionally, clock network  100  may typically have wider line widths than the routing lines of PLD  102 . Furthermore, clock network  100  may typically have less skew and delay than the routing lines of PLD  102 . 
   Global Clocks 
   As mentioned above, clock network  100  can be used to distribute global-clock signals to the various regions of PLD  102 . In the present embodiment, global-clock signals are generated from a plurality of input-clock signals. 
   More particularly, as depicted in  FIG. 1 , a plurality of input-clock signals are brought from input-clock blocks  108  to the center of the core of PLD  102  through input-clock lines  110 . In the present embodiment, each input-clock block  108  includes four input clocks. More particularly, input-clock block  108 A includes input-clock signals CLK 0 , CLK 1 , CLK 2 , CLK 3 . Input-clock block  108 B includes input-clock signals CLK 4 , CLK 5 , CLK 6 , and CLK 7 . Input-clock block  108 C includes input-clock signals CLK 8 , CLK 9 , CLK 10 , and CLK 11 . Input-clock block  108 D includes input-clock signals CLK 12 , CLK 13 , CLK 14 , and CLK 15 . As such, at the center of PLD 102 , a total of 16 input-clock signals converge. It should be recognized, however, that clock network  100  can include any number of input-clock signals and any number of input-clock blocks arranged in any number of configurations. 
   In  FIG. 5 , input-clock block  108 A ( FIG. 1 ) is depicted in more detail. As depicted in  FIG. 5 , in the present embodiment, input-clock signals CLK 0 , CLK 1 , CLK 2 , and CLK 3  are brought from their dedicated input pins  502  to the center of the core of PLD  102  ( FIG. 1 ). As also depicted in  FIG. 5 , a number of different clock signals can be generated from the input-clock signals. More particularly, PLL-clock signals (i.e., PLLCLK 0 , PLLCLK 1 , PLLCLK 2 , and PLLCLK 3 ) are generated from the input-clock signals by passing each input-clock signal through a differential buffer  504 , a PLL  506 , and PLL Output Muxing Block  508 . Buffer-clock signals are generated from the input-clock signals by passing each input-clock signal through a differential buffer  504 . Direct-clock signals are generated directly from each input-clock signal. 
   With reference to  FIG. 7 , a power bus is assigned to the input-clock signals. More particularly, in the present embodiment, eight power buses (i.e., VCCN 1 , VCCN 2 , VCCN 3 , VCCN 4 , VCCN 5 , VCCN 6 , VCCN 7 , and VCCN 8 ) are brought into the center of the core. One power bus is assigned to a pair of input-clock signals. VCCN 1  is assigned to input-clock signals CLK 0  and CLK 1 . VCCN 2  is assigned to CLK 2  and CLK 3 . VCCN 3  is assigned to input-clock signals CLK 4  and CLK 5 . VCCN 4  is assigned to input-clock signals CLK 6  and CLK 7 . VCCN 5  is assigned to input-clock signals CLK 8  and CLK 9 . VCCN 6  is assigned to input-clock signals CLK 10  and CLK 11 . VCCN 7  is assigned to input-clock signals CLK 12  and CLK 13 . VCCN 8  is assigned to input-clock signals CLK 14  and CLK 15 . It should be noted that any number of power buses can be used and can be assigned to the various input-clock signals in any number of configurations. 
   With reference again to  FIG. 5 , in addition to receiving input-clock signals through dedicated input pins  502 , clock network  100  ( FIG. 1 ) can be configured to receive input-clock signals from the logic resources of PLD  102  ( FIG. 1 ). More particularly, in the present embodiment, a set of input-clock signals can be received through a sneak path from LABs  302  ( FIG. 3 ). As such, the number of input-clock signals is not limited by the number of dedicated input pins  502 . 
   As depicted in  FIG. 5 , the various input-clock signals are multiplexed together using muxes  510 . In the present embodiment, each mux  510  is a 4:1 mux that has as inputs a PLL-clock signal, a buffer-clock signal, and a direct-clock signal from dedicated input pins  502  of input-clock signals CLK 0 , CLK 1 , CLK 2 , and CLK 3 . Additionally, each mux  510  has as an input a sneak path  518  from a LAB  302  ( FIG. 3 ). More particularly, as depicted in  FIG. 6 , LAB  302  A is connected through sneak path  518 A to muxes  510 A and  510 B and sneak path  518 C to muxes  510 E and 51° F. LAB  302 B is connected through sneak path  518 B to muxes  510 C and  510 D and sneak path  518 D to muxes  510 G and  510 H. In the present embodiment, muxes  510 A,  510 B,  510 C, and  510  D are connected to input-clock block  108 A. Muxes  510 E and  510 F are connected to input-clock block  108 D ( FIG. 1 ). Muxes  510 G and  510 H are connected to input-clock block  108 B ( FIG. 1 ). It should be recognized that any number of LABs  302  can be connected to any number of muxes  510  in any number of configurations. It should also be recognized that the number of input clock signals and thus the number of inputs of muxes  510  can vary. 
   With reference again to  FIG. 5 , global-clock signals GCLK 0 , GCLK 1 , GCLK 2 , and GCLK 3  can be generated and selected from any of the various input-clock signals. With reference again to  FIG. 5 , in the present embodiment, a total of 16 global-clock signals are generated. It should be recognized, however, that any number of global-clock signals can be generated from any number of inputs from various types of sources. 
   With reference again to  FIG. 1 , the global-clock signals are distributed through global-clock lines  112 . In the present embodiment, 16 global-clock signals are distributed to each region of PLD  102 . It should be recognized, however, that any number of global-clock signals can be distributed to each region. Furthermore, different numbers of global-clock signals can be distributed to each region. 
   Local Clocks 
   As depicted in  FIG. 5 , in the present embodiment, local-clock signals are also generated from the input-clock signals. More particularly, the output of a differential buffer  504  and the output of PLL Output Muxing Block  508  can be multiplexed together to generate a local-clock signal. Two local-clock signals are generated for each region from the input-clock signals and PLLs closes to that region. For example, in  FIG. 5 , local-clock signals LCLK 0  and LCLK 1  are generated from input-clock signals CLK 0 , CLK 1 , and PLL 0 . Local-clock signals LCLK 2  and LCLK 3  are generated from input-clock signals CLK 2 , CLK 3 , and PLL 1 . 
   As depicted in  FIG. 1 , local-clock signals LCLKO and LCLK 1  ( FIG. 5 ) are distributed to the center of the upper left region of PLD  102  along local-clock line  114 A. Local-clock signals LCLK 2  and LCLK 3  are distributed to the center of the lower left region of PLD  102  along local-clock line  114 B. As further depicted in  FIG. 1 , two more local-clock signals are distributed from input-clock block  108 D to the upper left region of PLD  102  along local-clock line  114 D. As such, four local-clock signals converge at the center of each region of PLD  102 . It should be recognized, however, that any number of local-clock signals can converge at each region of PLD  102 . 
   As depicted in  FIG. 1 , each region of PLD  102  can be provided with different local-clock signals. As such, each region can be provided with a wide selection of clock signals. Additionally, clock signals can be provided selectively to certain regions using the local-clock lines  114  for those regions without using the global clock network. As such, power consumption can be reduced by not using the global-clock lines and bus. 
   Regional Clocks 
   In each region of PLD  102 , local-clock signals and global-clock signals converge to form regional-clock signals. In the present embodiment, four local-clock signals and sixteen global-clock signals meet at the center of each region. For example, at the center of the upper left region of PLD  102 , two local-clock signals from input-clock block  108 A converge with two local-clock signals from input-clock block  108 D. Sixteen global-clock signals from the center of PLD  102  converge with these four local-clock signals to form regional-clock signals for this region of PLD  102 . It should be recognized, however, that the regional-clock signals can include any number and type of clock signals. 
   The regional-clock signals are then distributed within each region of PLD  102  through regional-clock lines  118 . In the present embodiment, regional-clock lines  118  connect to spine lines  106 , which are connected to sets of LABs  104 . As such, the regional-clock signals can be distributed to sets of LABs  104  through regional-clock lines  118  and spine lines  106 . It should be recognized, however, that regional-clock lines  118  can be connected directly to sets of LABs  104 . 
   Fast Clocks 
   As depicted in  FIG. 1 , fast-clock signals can be generated at input/output (I/O) blocks  116 . In the present embodiment, two fast-clock signals are generated in two 4:1 muxes. The inputs to each mux are two I/O bus signals and two I/O pin signals. Thus, each mux can select which I/O bus signal or I/O pin signal to use as the fast-clock signal. It should be recognized, however, that any number of fast-clock signals can be generated. 
   As depicted in  FIG. 1 , fast-clock signals can be distributed into a region more directly than local-clock signals or global-clock signals. As also depicted in  FIG. 1 , different fast-clock signals can be provided to different areas of a region. As such, clock signals can be provided to certain areas of a region using the fast-clock signals for those areas without using the local or global clock network. As such, power consumption can be reduced by not using the local or global clock lines and buses. Additionally, fast-clock signals can be provided to an area of a region more directly and quickly than using local-clock signals or global-clock signals. Furthermore, the number of input-clocks signals is not limited by the dedicated input pins. 
   Spine Lines 
   As depicted in  FIG. 1 , the regional-clock signals converge with the fast-clock signals to form spine-clock signals. More particularly, two fast-clock signals from each I/O block  116  converge with twenty regional-clock signals (i.e., sixteen global-clock signals and four local-clock signals) to form twenty-two spine-clock signals. 
   The spine-clock signals are distributed through spine lines  106 . In the present embodiment, each region of PLD  102  includes two spine lines  106 . For example, the upper left region of PLD  102  includes spine lines  106 A and  106 B, each spine line carrying twenty-two spine-clock signals. It should be recognized, however, that clock network  100  can include any number of spine lines  106  that carry any number of spine-clock signals. 
   Additionally, spine lines  106  can be configured as diffusion columns running from top to the bottom of the core. Furthermore, clock related drivers and buffers, with the exception of the drivers at the center of the core, can be placed in a clock-spine region. More particularly, in the present embodiment, the drivers and buffers for the local-clock signals and the global-clock signals, again with the exception of those at the center of the core, are placed in a clock-spine region. In this manner, any interface to the rest of the chip layout by clock network  100  can be reduced. Additionally, these drivers and buffers can be configured and tuned to reduce skew and delay. 
   Thus far, spine-clock signals and spine lines  106  have been described as including and carrying global-clock signals, local-clock signals, regional-clock signals, and fast-clock signals. In this manner, a wide selection of clock signals can be provided throughout clock network  100 . It should be recognized, however, that spine-clock signals and spine lines  106  can include and carry any combination of clock signals. For example, spine-clock signals and spine lines  106  can include and carry just global-clock signals and local-clock signals. Alternatively, in some applications, spine-clock signals and spine lines  106  can include and carry just one type of clock signal. Thus, in this manner, the configuration of the spine-clock signals and spine lines  106  is flexible and can be altered depending on the application. 
   Labs 
   As described earlier, with reference to  FIG. 1 , PLD  102  includes a plurality of sets of LABs  104 . As depicted in  FIG. 1  and described earlier, in the present embodiment, spine lines  106  are disposed between columns of sets of LABs  104  to provide a wide selection of clock signals to each set of LABs  104 . More particulary, in  FIG. 1 , four spine lines  106  (i.e., spine lines  106 A,  106 B,  106 C, and  106 D) are disposed between 8 columns of sets of LABs  104 , with each set of LABs  104  adjacent to and connected to a spine line  106 . It should be recognized, however, that clock network  100  can include any number of spine lines  106  adjacent any number of columns of sets of LABs  104 . 
   Section  120  of PLD  102  is depicted in greater detail in  FIG. 3 . As described earlier, with reference now to  FIG. 3 , each set of LABs  104  can include a number of LABs  302  arranged in any number of rows. As depicted in  FIG. 3 , in the present embodiment, each row of LABs  302  is connected to a spline line  106 . 
   As also depicted in  FIG. 3 , spine line  106  is connected to a mux  304  that generates a LAB-clock signal. More particularly, each row of LABs  302  include eight 22:1 muxes with each mux connected to spine line  106  to have access to twenty-two spine-clock signals (i.e., 16 global-clock signals, 4 local-clock signals, and 2 fast-clock signals). As such, each row of LABs  302  includes eight LAB-clock signals. 
   At each LAB  302 , the eight LAB-clock signals are multiplexed into two local-LAB clocks. In this manner, a wide selection of clock signals can be provided to LAB  302 . 
   I/Os 
   As depicted in  FIG. 3 , spine-clock signals can be provided to I/O decoders. More particularly, in a top or bottom I/O decoder  306 , spine line  106  is connected to a mux  308  that generates a top or bottom I/O clock (TBIOCLK) signal. More particularly, eight 22:1 muxes are utilized to generate 8 TBIOCLK signals on a TBLIOCLK line  310 . Similarly, in a left or right I/O decorder  312 , spine line  106  is connected to a mux  314  that generates a left or right I/O clock (LRIOCLK) signal. Additionally, the TBIOCLK or LRIOCLK signals can be muxed into one local-IO clock signal for each I/O register. 
   Memory Devices 
   As noted earlier, clock network  100  described above can be used in various devices. For example, the PLD depicted in  FIG. 1  can include memory devices in addition to LABs  302  ( FIG. 3 ). These memory devices can be provided with clock signals similar to the manner in which LABs  302  ( FIG. 3 ) are provided with LAB-clock signals. For example, the 8 LAB-clocks signals can be multiplexed into 2 Local-memory clock signals for each memory device. 
   General Purpose Routing 
   As noted earlier, clock network  100  described above can be used for general purpose routing. As also described earlier, fast-clock signals can include inputs from I/O buses and I/O pins. Additionally, the input clock buffers of clock network  100  can support all I/O standards. As such, these inputs can be used for general purpose routing in addition to providing clock signals. 
   Additionally, as noted earlier, the use of clock network  100  for general purpose routing can be advantageous in that clock network  100  can have less loading than the general routing network. Additionally, the line widths for clock network  100  can be larger than that of the general routing network. Furthermore, clock network  100  can have less skew and delay than the general routing network. 
   Although the present invention has been described in conjunction with particular embodiments illustrated in the appended drawing figures, various modifications can be made without departing from the spirit and scope of the invention. For example, in  FIGS. 2 and 4 , a clock network with 2 spine lines  106  is depicted. Therefore, the present invention should not be construed as limited to the specific forms shown in the drawings and described above.