Abstract:
A multiple step-up rectifier circuit, according to the invention, has a plurality of multiple step-up rectifier circuits, each of which is constituted by a combination of a plurality of diodes connected in series, output capacitors which are connected in parallel with this series circuit of the diodes, and supply capacitors which are charged by the input AC voltages and which supply the voltages to the output capacitors in amounts equal to the discharged voltages thereof. These plurality of multiple step-up rectifier circuits are connected in series, and each of these circuits receives an arbitrary AC voltage and generates a multiple step-up voltage. In these two adjacent circuts, there is the following relation: ##EQU1## where, C 1  is the capacitance of each of the capacitors constituting one of the multiple step-up rectifier circuits; E 1  is the input voltage thereof; I 1  is the value which is obtained by adding the output current of this circuit and all of the output currents of the circuits of the post stage of this circuit; n 1  is the half of the number of supply capacitors of this circuit; C 2  is the capacitance of each of the capacitors constituting the other multiple step-up rectifier circuits; E 2  is the input voltage thereof; I 2  is the value which is derived by adding the output current of the second circuit and all of the output currents of the circuits at the post stage of this circuit; and n 2  is the half of the number of the supply capacitors of the second circuit.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a multiple step-up rectifier circuit which is constituted by a combination of a plurality of capacitors and diodes and, more particularly, to a multiple step-up rectifier circuit having a plurality of output terminals in which different voltages and currents can be output from these output terminals, respectively. 
     In general, the multiple step-up rectifier circuit constituted by a combination of a plurality of capacitors and diodes has a high internal impedance; therefore, it has a drawback such that the output voltage changes significantly in response to a variation in load. In the case of taking out a voltage from the center tap of the rectifier circuit, other output voltages will be significantly influenced. Consequently, it is difficult to keep the ratios among the output voltages constant irrespective of the load condition. Therefore, in the conventional multiple step-up rectifier circuit, in the case of outputting a plurality of different voltages, it is very difficult to simultaneously regulate the output voltages. In addition, since each output voltage depends on the number of multiple steps, the voltage values can hardly be arbitrarily determined. 
     SUMMARY OF THE INVENTION p It is an object of the present invention to provide a multiple step-up rectifier circuit in which a plurality of output voltages can be arbitrarily set, the output voltage ratios can be maintained at constant values irrespective of the load condition, and each output voltage can be regulated. 
     According to an aspect of the present invention, there is provided a multiple step-up rectifier circuit comprising: 
     a plurality of rectifying elements which are connected in series so that the rectifying directions are the same and in each of which one end is connected to a reference potential point; 
     a plurality of first capacitors which are connected in series between both ends of the plurality of rectifying elements connected in series and which are connected in parallel with the plurality of rectifying elements; 
     a plurality of output terminals, each for taking out a voltage across an arbitrary number of first capacitors among the plurality of first capacitors; 
     a plurality of second capacitors, each end of which is connected to every other node among a plurality of mutual nodes of the plurality of rectifying elements connected with each other between the reference potential point and each of the output terminals; 
     a plurality of third capacitors, each end of which is connected to the nodes to which the second capacitors are not connected among the mutual nodes of the plurality of rectifying elements connected with each other between the reference potential point and each of the output terminals, each of the third capacitors having the same capacitance as that of each of the second capacitors; and 
     a plurality of pairs of input terminals which are provided for every circuit which is constituted between the reference potential point and each of the output terminals, the second capacitors of the circuit being connected in series with one of the pair of input terminals and the third capacitors being connected in series with the other pair of input terminals, and the plurality of pairs of input terminals being supplied with arbitrary AC voltages for a reference potential, respectively, 
     wherein the relation of the following expression is presented between the adjacent two circuits among the respective circuits which are constituted between the reference potential point and each of the output terminals, ##EQU2## where, C 1  : capacitance value of each of the second and third capacitors constituting one of the two adjacent circuits, 
     C 2  : capacitance value of each of the second and third capacitors constituting the other circuit, 
     n 1  : half of the number of the second and third capacitors constituting one of the circuits, 
     n 2  : half of the number of the second and third capacitors constituting the other circuit, 
     I 1  : current value which is obtained by adding all of the output currents of the circuits at the post stage of one of the circuits to the output current of one of the circuits, 
     I 2  : current value which is obtained by adding all of the output currents of the circuits at the post stage of the other circuit to the output current of the other circuit, 
     E 1  : value of the AC voltage which is supplied to one of the circuits, 
     E 2  : value of the AC voltage which is supplied to the other circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit arrangement diagram showing the first embodiment of a multiple step-up rectifier circuit according to the present invention; 
     FIG. 2 is a reference circuit arrangement diagram for explaining the invention; and 
     FIG. 3 is a circuit arrangement diagram showing the second embodiment of a multiple step-up rectifier circuit according to the invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     An embodiment of the present invention will now be described in detail hereinbelow with reference to tne drawings. 
     FIG. 1 shows an arrangement of the first embodiment. In the diagram, reference character A denotes an AC power source in which a voltage to be generated can be arbitrarily adjusted. AC power source A is connected to a primary winding n 1  of a transformer T. A secondary winding n 2  of transformer T has a center tap terminal m. Tap terminals a 2  and b 2  are provided among center tap terminal m and respective terminals a 1  and b 1  at both ends of secondary winding n 2 , respectively. In this multiple step-up rectifier circuit, terminals a 1  and b 1  are used as the first input terminals and tap terminals a 2  and b 2  are used as the second input terminals, and center tap terminal m is connected to the ground and used as the reference potential terminal. Diodes D 1  to D 15  are connected in series between reference potential terminal m and first output terminal P 1  so that the rectifying directions are the same. The anode of diode D 1  is connected to terminal m and the cathode of diode D 15  is connected to output terminal P 1 . 
     It is now assumed that the respective nodes among diodes D 1  to D 15  are e, f, g, h, j, k, l, n, s, t, u, v, w, and x. A capacitor C 1  is connected between a 2  and f. A capacitor C 2  is connected between f and j. A capacitor C 3  is connected between a 1  and n. A capacitor C 4  is connected between n and u. A capacitor C 5  is connected between u and x. A capacitor C 6  is connected between m and g. A capacitor C 7  is connected between g and k. A capacitor C 8  is connected between k and s. A capacitor C 9  is connected between s and v. A capacitor C 10  is connected between v and P 1 . A capacitor C 11  is connected between b 2  and e. A capacitor C 12  is connected between e and h. A capacitor C 13  is connected between b 1  and l. A capacitor C 14  is connected between l and t. A capacitor C 15  is connected between t and w. 
     Capacitors C 1  and C 2  ; C 3  to C 5  ; C 6  to C 10  ; C 11  and C 12  ; and C 13  to C 15  are connected in series, respectively. Node k is a second output terminal P 2 . Namely, capacitors C 6  and C 7  are the output capacitors between second output terminal P 2  and reference potential terminal m. Capacitors C 8  to C 10  are output capacitors between first and second output terminals P 1  and P 2 . The other capacitors, C 1  to C 5  and C 11  to C 15 , are supply capacitors to supply charging currents to output capacitors C 6  to C 10 , respectively. As mentioned above, according to this multiple step-up rectifier circuit, the first multiple step-up rectifier circuit is constituted between first and second output terminals P 1  and P 2 , the second multiple step-up rectifier circuit is constituted between second output terminal P 2  and reference potential terminal m, and second output terminal P 1  is used as the reference potential terminal of the first multiple step-up rectifier circuit. 
     The respective capacitances of capacitors C 3  to C 5 , C 8  to C 10 , and C 13  to C 15  constituting the first rectifier circuit are all equal and assume C a  [F]. On the other hand, the respective capacitances of capacitors C 1 , C 2 , C 6 , C 7 , C 11 , and C 12  constituting the second rectifier circuit are all equal and assume C b  [F]. It is also assumed that AC power source A generates the AC voltage of a frequency f (=1/T: T is a period) [Hz]. 
     In the above constitution, the operations in the loadless condition and in the condition in which a load is connected will now be described herein below. 
     In the loadless condition, it is now assumed that when the AC voltage of frequency f [Hz] was supplied to primary winding n 1  of transformer T from AC power source A, the AC voltage of 2E 01  [V] is generated between terminals a 1  and b 1  of secondary winding n 2  and the AC voltage of 2E 02  [V] is generated between terminals a 2  and b 2 , respectively. It is now assumed that the potential of terminal b 2  becomes -E 02 . At this time, diode D 1  is made conductive and a current flows from reference potential terminal m to terminal b 2  through diode D 1 , node e, and capacitor C 11  (hereinafter, this current flow is expressed by m→D 1  →e→C 11  →b 2 ). Thus, the voltage of E 02  is charged into capacitor C 11  in which polarity on the node e side is positive. 
     Next, when the potential of terminal a 2  becomes -E 02 , diode D 2  is made conductive and a current flows in accordance with the order of b 2  →C 11  →e→D 2  →f→C 1  →a 2 . Thus, the voltage of 3E 02 , which is the sum of the voltage 2E 02  between a 2  and b 2  and the charging voltage E 02  of capacitor C 1 , is charged into capacitor C 1  in which the polarity on the node f side is positive. 
     Subsequently, when the potential of terminal b 2  becomes -E 02 , diode D 3  is made conductive and a current flows in accordance with the order of a 2  →C 1  →f→D 3  →g→C 6  →m. Thus, the voltage of 4E 02 , which is the sum of the voltage E 02  between a 2  and m and the charging voltage 3E 02  of capacitor C 1 , is charged into capacitor C 6  in which the polarity on the node g side is positive. At this time, since the potential of terminal a 2  is +E 02 , diode D 4  is made conductive and a current flows in accordance with the order of a 2  →C 1  →f→D 3  →g→D 4  →h→C 12  →C 11  →b 2  →m. Thus, the voltage of 4E 02 , which is the sum of the voltage 2E 02  between a 2  and b 2  and the charging voltage 3E 02   of capacitor C 1  and the charging voltage -E 02  of capacitor C 11 , is charged into capacitor C 12  in which the polarity on the node h side is positive. 
     Next, when the potential of terminal b 2  becomes +E 02 , diode D 5  is made conductive and a current flows in accordance with the order of b 2  →C 11  →C 12  →h→D 5  C 2  →C 1  →a 2 . Thus, the voltage of 4E 02 , which is the sum of the voltage 2E 02  between a 2  and b 2 , the charging voltage E 02  of capacitor C 1 , the charging voltage 4E 02  of capacitor C 12 , and the charging voltage -3E 02  of capacitor C 1 , is charged into capacitor C 2  in which the polarity on the node j side is positive. When the potential of terminal a 2  then becomes +E 02 , diode D 6  is made conductive and a current flows in accordance with the order of a 2  →C 1  →C 2  →j→D 6  →k (P 2 )→C 7  →C 6  →m. Thus, the voltage of 4E 02 , which is the sum of the voltage E 02  between a 2  and m, the charging voltage 3E 02  of capacitor C 1 , the charging voltage 4E 02  of capacitor C 6 , and the charging voltage -4E 02  of capacitor C 6 , is charged into capacitor C 7  in which the polarity on the node k side is positive. 
     At this time, since the potential of terminal b 1  is -E 01 , diode D 7  is made conductive, and a current flows in accordance with the order of a 2  →C 1  →C 2  →j→D 6  →k→D 7  →l→C 13  →b 1 . Thus, the voltage of 8E 02  +E 01 , which is the sum of the voltage E 02  between a 2  and m, the charging voltage 3E 02  of capacitor C 1 , the charging voltage 4E 02  of capacitor C 2 , and the voltage E 01  between m and b 1 , is charged into capacitor C 13  in which the polarity on the node l side is positive. 
     Next, when the potential of terminal b 1  becomes -E 01 , diode D 8  is made conductive and a current flows in accordance with the order of b 2  →C 13  →l→D 8  →n→C 3  →a 1 . Thus, the voltage of 8E 02  +3E 01 , which is the sum of the voltage 2E 01  between a 1  and b 1  and the charging voltage 8E 02  +E 01  of capacitor C 13 , is charged into capacitor C 3  in which the polarity on the node n side is positive. 
     Then, when the potential of terminal a 1  becomes +E 01 , diode D 9  is made conductive, and a current flows in accordance with the order of a 1  →C 3  →n→D 9  →s C 8  →C 7  →C 5  →m. Thus, the voltage of 4E 01 , which is the sum of the voltage E 01  between a 1  and m, the charging voltage 8E 02  +3E 01  of capacitor C 3 , and charging voltages -4E 02  and -4E 02  of capacitors C 7  and C 6 , is charged into capacitor C 8  in which the polarity on the node s side is positive. At this time, since the potential of terminal b 1  is -E 01 , diode D 10  is made conductive, and a current flows in accordance with the order of a 1  →C 3  →n→D 9  →s→D 10  →t→C 14  →C 13  →b 1 . Thus, the voltage of  4E 01 , which is the sum of the voltage 2E 01  between a 1  and b 2 , the charging voltage 8E 02  +3E 01  of capacitor C 3 , and the charging voltage -(8E 02  +E 01 ) of capacitor C 13 , is charged into capacitor C 14  in which the polarity on the node t side is positive. 
     Subsequently, when the potential of terminal b 1  becomes +E 01 , diode D 11  is made conductive, and a current flows in accordance with the order of b 1  →C 13  →C 14  →t→D 11  →u→C 4  →C 3  →a 1 . Thus, the voltage of 4E 01 , which is the sum of the voltage 2E 01  between a 1  and b 1 , the charging voltages 8E 02  +E 01  and 4E 01  of capacitors C 13  and C 14 , and the charging voltage -(8E 02  3E 01 ) of capacitor C 3 , is charged into capacitor C 4  in which the polarity on the node u side is positive. 
     Next, when the potential of terminal a 1  becomes +E 01 , diode D 12  is made conductive, and a current flows in accordance with the order of a 1  →C 3  →C 4  →u→D 12  →v→C 9  →C 8  →C 7  →C 6  →m. Thus, the voltage of 4E 01 , which is the sum of the voltage E 01  between a 1  and m, the charging voltages 8E 02  +3E 01  and 4E 01  of capacitors C 3  and C 4 , and the charging voltages -4E 01 , -4E 02 , and -4E 02  of capacitors C 8 , C 7 , and C 6 , is charged into capacitor C 9 , in which the polarity on the node v side is positive. At this time, since the potential of terminal b 1  is -E 01 , diode D 13  is made conductive, and a current flows in accordance with the order of a 1  →C.sub. 3 →C 4  →u→D 12  →v→D 13  →w→C 15  →C 14  →C 13  →b 1 . Thus, the voltage of 2E 01 , which is the sum of the voltage 2E 01  between a 1  and b 1 , the charging voltages 8E 02  +3E 01  and 4E 01  of capacitors C 3  and C 4 , and the charging voltages -4E 01  and -(4E 02  +E 01 ) of capacitors C 14  and C 13 , is charged into capacitor C 15 , in which the polarity on the node w side is positive. 
     Next, when the potential of terminal b 1  becomes +E 01 , diode D 14  is made conductive, and a current flows in accordance with the order of b 1  →C 13  →C 14  →C 15  → w→D 14  →x→C 5  →C 4  →C 3  →a 1 . Thus, the voltage of 4E 01 , which is the sum of the voltage 2E 01  between a 1  and b 1 , the charging voltages 8E 02  +E 01 , 4E 01 , and 4E 01  of capacitors C 13 , C 14 , and C 15 , and the charging voltages -4E 01  and -(8E 02  +3E 01 ) of capacitors C 4  and C 3 , is charged into capacitor C 5 , in which the polarity on the node x side is positive. 
     Next, when the potential of terminal a 1  becomes +E 01 , diode D 15  is made conductive and a current flows in accordance with the order of a 1  →C 3  →C 4  →C 5  →x→D 15  →P 1  →C 10  →C 9  →C 8  →C 7  →C 6  →m. Thus, the voltage of 4E 01 , which is the sum of the voltage 2E 01  between a 1  and b 1 , the charging voltages 8E 02  +3E 01 , 4E 01 , and 4E 01  of capacitors C 3 , C 4 , and C 5 , and the charging voltages -4E 01 , -4E 01 , -4E 02 , and -4E 02  of capacitors C 9 , C 8 , C 7 , and C 6 , is charged into capacitor C 10 , in which the polarity of output terminal P 1  is positive. 
     Namely, in the loadless condition, each charging voltage of output capacitors C 6  and C 7  of the second multiple step-up rectifier circuit is 4E 02 , which is twice as high as the voltage 2E 02  between a 2  and b 2 . Each of the charging voltages of output capacitors C 8 , C 9 , and C 10  of the first multiple step-up rectifier circuit is 4E 01 , which is twice as high as the voltage 2E 01  between a 1  and b 1 . Therefore, assuming that the voltage 2E 01  is generated between second output terminal P 2  and reference potential terminal m is E 2  [V], E 2  is equal to 8E 02 . Assume that the voltage which is generated between first and second output terminals P 1  and P 2  is E 1  [V], E 1  is equal to 12E 01 . Therefore, when it is assumed that the number of steps of the first multiple step-up rectifier circuit (namely, the number of supply capacitors which are connected between either one of first input terminals a 1  and b 1  and each node among the diodes which are connected in series between P 1  and P 2 ) is n 1  (n 1  =3 in the case of FIG. 1), and the number of steps of the second multiple step-up rectifier circuit (namely, the number of supply capacitors which are connected between either one of second input terminals a 2  and b 2  and each node among the diodes which are connected in series between m and P 2 ) is n 2  (n 2  =2 in the case of FIG. 1), output currents i 1  and i 2  of output terminals P 1  and P 2  are 0 in the loadless condition. Therefore, output voltages E 1  and E 2  of the first and second multiple step-up rectifier circuits in the loadless condition can be obtained by the following expressions, respectively. 
     
         E.sub.1 =2n.sub.1 ·2E.sub.01                      (1) 
    
     
         E.sub.2 =2n.sub.2 ·2E.sub.02                      (2) 
    
     The operation under the condition such that a load is connected will now be described. As mentioned above, voltage drops occur in the output voltages by the load current under the condition with a load. This voltage drop will be described with reference to FIG. 2. 
     A circuit (shown in FIG. 2) is constituted in a manner such that diodes D 1  to D 6  and capacitors C 1 , C 2 , C 6 , C 7 , C 11 , and C 12 , which constitute the first multiple step-up rectifier circuit, are removed from the circuit (shown in FIG. 1), the cathode of diode D 7 , constituting the first rectifier circuit, is connected to reference potential terminal m, and a load resistor R L  is connected between output terminal P 1  and reference potential terminal m. In FIG. 2, the same parts and elements as those shown in FIG. 1 are designated by the same reference numerals. 
     First, if it is assumed that the mean value of the load current for one period is I [A], all of the voltage drops which will be caused in capacitors C 8  to C 10  for one period T are equal to e 0 . In this case, the following conditions (a) to (c) are satisfied. 
     (a) The load current is supplied from output capacitors C 8 , C 9 , and C 10 . Thus, identical voltage drops e 0  occur in these capacitors. 
     (b) The respective voltage drops which are caused in output capacitors C 8 , C 9 , and C 10  within one period T are compensated by supply capacitors C 3 , C 4 , and C 5  when the potential of terminal a 1  becomes positive. Namely, the voltages discharged by output capacitors C 8 , C 9 , and C 10  are supplemented by the currents from supply capacitors C 3 , C 4 , and C 5 , respectively. 
     (c) Similarly to item (b), the voltage drops which are caused in supply capacitors C 3 , C 4 , and C 5  within one period T are respectively compensated by supply capacitors C 13 , C 14 , and C 15  when the voltage of terminal b 1  becomes positive. 
     Consequently, the voltage drops which are caused in the respective capacitors within one period T are as follows. 
     C 8 , C 9 , C 10  : e 0   
     C 5  : e 0  (Voltage drop due to the supply of the current to capacitor C 10 ) 
     C 15  : e 0  (Voltage drop due to the supply of the current to capacitor C 5 ) 
     C 4  : 2e 0  (Voltage drop due to the supply of the currents to capacitors C 9  and C 15 ) 
     C 14  : 2e 0  (Voltage drop due to the supply of the current to capacitor C 4 ) 
     C 3  : 3e 0  (Voltage drop due to the supply of the currents to capacitors C 8  and C 14 ) 
     C 13  : 3e 0  (Voltage drop due to the supply of the current to capacitor C 3 ) 
     Since the voltage drops which are caused in the respective capacitors are sequentially accumulated by the supply of the currents, they will become as follows: 
     C 13  :3e 0 , C 3  :6e 0 , C 14  :8e 0 , 
     C 4  :10e 0 , C 15  :11e 0 , C 5  :12e 0   
     Since the voltage drop which is caused in output capacitor C 10  is supplied by supply capacitor C 5 , the voltage drop after the current was supplied becomes 12e 0 . Similarly, the voltage drops which are caused in output capacitors C 9  and C 8  are 10e 0  and 6e 0 , respectively. 
     Therefore, the values of the voltage drops in output capacitors C 8 , C 9 , and C 10  can be expressed as follows, respectively: 
     C 8  : (2×3)e 0   
     C 9  : (2×3+2×2 )e 0   
     C 10  : (2×3+2×2+2×1)e 0   
     In the above expressions, 3 indicates the number of supply capacitors C 3 , C 4 , and C 5  or C 13 , C 14 , and C 15  connected between either one of first input terminals a 1  and b 1  and each node among the diodes. Therefore, when the number of supply capacitors connected between terminal a 1  or b 1  and each node among the diodes is represented by n, the voltage drops which are caused in the output capacitors C 8 , C 9 , and C 10  are expressed by the following expressions: 
     
         C.sub.8 : 2 ne.sub.0                                       (a) 
    
     
         C.sub.9 :{2n+2(n-1)}e.sub.0                                (b) 
    
     
         C.sub.10 : {2n+2(n-1)+2(n-2)}e.sub.0                       (c) 
    
     Assuming that the whole voltage drop which is caused by the load current is E d , whole voltage drop E d  is the sum of the voltage drops which are caused in output capacitors C 8 , C 9 , and C 10  ; therefore, it can be expressed as follows: 
     
         E.sub.d ={2n×3+2(n-1)(3-1)+2(n-2)(3-2)}e.sub.0 
    
     In this expression, 3 denotes the number of output capacitors. When the number of output capacitors is also represented by n, whole voltage drop E d  is expressed as follows: ##EQU3## 
     It is now assumed that the capacitance of each capacitor is C [F], the charge amount is Q [C], the load current is I [A], the period of the input voltage is T [sec], and the frequency is f [Hz]. In this case, e 0  is expressed as follows: ##EQU4## Therefore, expression (3) can be rewritten as follows: ##EQU5## 
     On the basis of the above description, it is now assumed that, in the circuit shown in FIG. 1, load currents i 1  and i 2  are respectively output from first and second output terminals P 1  and P 2 . The voltage drops by load currents i 1  and i 2  will now be considered. First, voltage drop E 1d  in output voltage E 1  is expressed as follows from expression (4): ##EQU6## where n 1  is the number of steps between P 1  and P 2  and I 1  equals i 1 . Voltage drop E 2d  in output voltage E 2  is expressed as follows from expression (4), since the voltage drop by load current i 1  which is output from terminal P 1  is added to the voltage drop by load current i 2 , which is output from terminal P 2  : ##EQU7## where n 2  is the number of steps between P 2  and m and I 2  =i 1  +i 2 . 
     In the loadless condition, since output voltages E 1  and E 2  are indicated by expressions (1) and (2), output voltages E 1  and E 2 , when a load is connected, can be expressed as follows: ##EQU8## 
     On the basis of the above-mentioned relations, control means for making the output voltages constant, irrespective of the loadless condition, and the condition in which a load is connected will now be described herein below. 
     First, assuming that by increasing the output voltage value of AC power source A, voltage 2E 01  between a 1  and b 1  was adjusted to 2E 01 , so as to compensate the voltage drop in output voltage E 1 , the following relation can be derived from expressions (1) and (7): ##EQU9## In this case, voltage 2E 02  between a 2  and b 2  also increases. Therefore, when it is assumed that the increased voltage is 2E 02  &#39; and output voltage E 2  is also equalized to the voltage under the loadless condition, the following relation will be obtained from expressions (2) and (8): ##EQU10## The following expressions are derived by dividing both sides in expressions (9) and (10) by 4n 1  E 01  and 4n 2  E 02 , respectively: ##EQU11## When the voltage on the primary side of transformer T increases, the voltage between a 1  and b 1  and the voltage between a 2  and b 2  on the secondary side also increases at the same ratio. Therefore, the following relation is obtained: ##EQU12## Thus, the following expression can be derived from expressions (11) and (12): ##EQU13## 
     Therefore, in the circuit shown in FIG. 1, if the ratio of the capacitances of the capacitors is set so as to satisfy expression (14), and one output voltage (for example: E 2 ) is regulated, the other output voltage (for example: E 1 ) can be also simultaneously regulated. This regulating means may be realized by, for instance, detecting the level of output voltage E 2  and by controlling the output value of AC power source A so that this detection level always coincides with the reference voltage level. 
     FIG. 3 shows the second embodiment, in which the same parts and elements as those shown in the circuit of FIG. 1 are designated by the same reference numerals. 
     Namely, in a multiple step-up rectifier circuit shown in FIG. 3, capacitor C 1  is connected between a 2  and f; capacitor C 2  is connected between a 1  and j; capacitor C 11  is connected between b 1  and e; capacitor C 12  is connected between b 2  and h; and capacitor C 3  is connected between a 2  and n. Node g between diodes D 3  and D 4  is a third output terminal P 3 . The other circuit constitution is the same as that in FIG. 1. Namely, diodes D 7  to D 15  and capacitors C 3  to C 5 , C 8  to C 10 , and C 13  to C 15  constitute the first multiple step-up rectifier circuit; diodes D 4  to D 6  and capacitors C 2 , C 7 , and C 12  constitute the second multiple step-up rectifier circuit; and diodes D 1  to D 3  and capacitors C 1 , C 6 , and C 11  constitute the third multiple step-up rectifier circuit. It is now assumed that all of the capacitances of capacitors C 3  to C 5 , C 8  to C 10 , and C 13  to C 15  of the first multiple step-up rectifier circuit are equal to C a  [F]. It is assumed that all of the capacitances of capacitors C 2 , C 7 , and C 12  of the second multiple step-up rectifier circuit are equal to C b  [F]. It is assumed that all of the capacitances of capacitors C 1 , C 6 , and C 11  of the third multiple step-up rectifier circuit are equal to C c  [F]. 
     In the above constitution, it is now assumed that the voltage of 2E 01  is generated between first input terminals a 1  and b 1  and the voltage of 2E 02  is generated between second input terminals a 2  and b 2 . In this case, the following voltages are charged into the capacitors, respectively: 
     C 11  :E 01 , C 1  :2E 01  +E 02 , C 6  :2(E 01  +E 02 ), 
     C 12  :2E 01  +3E 02 , C 2  :3E 01  +4E 02 , C 7  :2(E 01  +E 02 ), 
     C 13  :5E 01  +4E 02 , C 3  :6E 01  +5E 02 , C 8  :2(E 01  +E 02 ), 
     C 14  :2(E 01  +E 02 ), C 4  :2(E 01  +E 02 ), C 9  :2(E 01  +E 02 ), 
     C 15  :2(E 01  +E 02 ), C 5  :2(E 01  +E 02 ), C 10  :2(E 01  +E 02 ) 
     From the above description, output voltages E 1  to E 3  of the first to third multiple step-up rectifier circuits under the loadless condition can be expressed as follows when the numbers of steps of these circuits assume n 1 , n 2 , and n 3 , respectively: 
     
         E.sub.1 =2n.sub.1 (E.sub.01 +E.sub.02)                     (15) 
    
     
         E.sub.2 =2n.sub.2 (E.sub.01 +E.sub.02)                     (16) 
    
     
         E.sub.3 =2n.sub.3 (E.sub.01 +E.sub.02)                     (17) 
    
     Voltage drops E 1d , E 2d , and E 3d  of the first to third multiple step-up rectifier circuits can be expressed as follows from expression (4): ##EQU14## In this case, it is assumed that the load currents which are output from first to third output terminals P 1  to P 3  are i 1 , i 2 , and i 3 , respectively, and that I 1  =i 1 , I 2  =i 1  +i 2 , and I 3  =i 1  +i 2  +i 3 . Therefore, output voltages E 1 , E 2 , and E 3 , when a load is connected, are expressed as follows, respectively: ##EQU15## 
     The output voltage of power source A is adjusted so that output voltage E 3  under the loadless condition is equal to output voltage E 3  when a load is connected. When it is now assumed that the voltage between a 2  and b 1  is (E 02  +E 01 )&#39;, the following relation is obtained from expressions (17) and (23): ##EQU16## At this time, the voltage between a 1  and b 2  also increases at the same ratio as the change in voltage between a 2  and b 1 . When this increased voltage assumes (E 01  +E 02 )&#34;, the following relations are derived from expressions (16), (22), (15), and (21): ##EQU17## In this case, since ##EQU18## the following expressions can be derived from expression (24) to (27): ##EQU19## 
     Therefore, if the ratios among the capacitances of the respective capacitors are set so as to satisfy expressions (28) to (30), by regulating one output voltage (for example: E 3 ), all of the output voltages (e.g., E 1  and E 2 ) can be also regulated. 
     The present invention is not limited to the above embodiments. For example, in the first and second embodiments, the description has been made with respect to the case of using the secondary winding of the transformer having the first and second input terminals receive the AC voltage and the center tap terminal as the reference potential terminal. However, the invention can be also realized by the constitution such that the first and second input terminals and reference input terminal are directly connected to the AC power source without passing through the transformer. On the other hand, the description has been made with regard to the operation in the above embodiments in the case where the voltage between the second input terminal and the reference potential terminal differs from the voltage of the corresponding first input terminal. However, even if they are the same voltage, no contradiction will be caused in the operation. The essential point is to determine the capacitances of the capacitors constituting each multiple step-up rectifier circuit so as to satisfy expression (14) in accordance with the magnitude of load current and with the number of multiple steps.