Abstract:
This invention is generally concerned with digital-to-analogue converters and more particularly relates to techniques for reducing signal dependent loading of reference voltage sources used by these converters. 
     A differential switched capacitor digital-to-analogue (DAC) circuit ( 500 ) comprises first and second differential signal circuit portions ( 500   a,b ) for providing respective positive and negative signal outputs with respect to a reference level, and has first and second reference voltage inputs ( 112,114 ) for receiving respective positive and negative references. Each of said first and second circuit portions comprises an amplifier ( 102   a,b ) with a feedback capacitor ( 104   a,b ), a second capacitor ( 106   a,b ), and a switch ( 108   a,b,    110   a,b ) to switchably couple said second capacitor to a selected one of said reference voltage inputs to charge the second capacitor and to said feedback capacitor to share charge with the feedback capacitor. The switch of said first circuit portion is further configured to connect said second capacitor ( 106   a ) of said first circuit portion to share charge with said feedback capacitor ( 104   b ) of said second circuit portion; and the switch of said second circuit portion is further configured to connect said second capacitor ( 106   b ) of said second circuit portion to share charge with said feedback capacitor ( 104   a ) of said first circuit portion. This enables the second capacitors to in effect be alternately pre-charged to positive and negative signal-dependent nodes so that, on average, signal dependent loading of the references is approximately constant.

Description:
FIELD OF THE INVENTION 
   This invention is generally concerned with digital-to-analogue converters and more particularly relates to techniques for reducing signal dependent loading of reference voltage sources used by these converters. 
   BACKGROUND TO THE INVENTION 
   Digital-analogue conversion based on converting a delta-sigma digital representation of a signal into an analogue waveform is now a commonplace technique. In a simple delta-sigma digital-to-analogue converter a string of pulses is generated, with a pulse density dependent upon the digital value to be converted, and low-pass filtered. The technique is prevalent in many high-volume application areas, for example digital audio, where several channels of high quality relatively low frequency (audio frequency) signals are required. High quality in this context typically implies −100 dB THD (Total Harmonic Distortion) and 100 dB SNR (Signal to Noise Ratio). However, in such high-volume markets manufacturing cost is also very important. 
   In general, a digital-to-analogue converter requires positive and negative reference voltages to define the amplitude of the output signal. A digital-to-analogue converter draws some current from these reference voltage ports, and this current will generally be signal dependent. 
   These reference voltages are typically generated from a source of low but non-zero output impedance, for example by a power supply or buffer with a decoupling capacitor. The source will have a finite ESR (Equivalent Series Resistance), and there will be additional resistance between the source, the decoupling and the device due to the effects of resistive PCB tracking, package lead resistance, and bond wire resistance. 
   The result is that any signal-dependent current drawn by the DAC from the references causes a signal-dependent voltage ripple to appear on the reference voltages actually applied to the DAC. Since the DAC output signal is proportional to the reference voltage, this multiplies the ideal digital-to-analogue converter output by this ripple. The consequent modulation of the output signal is apparent as signal distortion, for example, generating harmonic distortion components with a sine wave signal. 
   Furthermore in a stereo or multi-channel system it is often uneconomic to supply a digital-to-analogue converter for each channel with a separate voltage reference supply, or even separate decoupling, PCB traces, or integrated circuit pins. In these situations the reference ripple caused by one channel&#39;s DAC can appear on the reference voltage for other DACs, modulating the outputs of these other DACs as well as its own output. 
   The invention described herein is directed to digital-to-analogue converter circuits intended to reduce or eliminate signal dependent reference currents. A digital-to-analogue converter design for which the reference currents are substantially independent of output signal should be capable of lower distortion for a given source impedance. Alternatively, for a given acceptable level of performance, the digital-to-analogue converter should be more tolerant of source impedance, so allowing a design engineer to reduce costs by specifying fewer or cheaper, lower quality external components. 
   Many delta-sigma digital-to-analogue converters use switched-capacitor techniques.  FIG. 1   a  shows an example of a simple switched-capacitor DAC  100  suitable for use in a delta-sigma DAC system. 
   An operational amplifier  102  has a non-inverting input connected to a constant voltage V mid    118 , typically ground. Operational amplifier  102  has an output  120  providing an output voltage V out  and a feedback capacitor C f    104  is connected between the output and an inverting input of the operational amplifier. A second capacitor C 2   106  is switchably connected across feedback capacitor  104  by means of switches  108  and  110 . Switch  108  allows one plate of capacitor  106  to be connected either to C f    104  or to a positive reference voltage V P    112  or a negative reference voltage V N    114 . Switch  110  allows the other plate of capacitor  106  to be connected either to feedback capacitor  104  or to a second constant voltage, V mid2    116 . 
   In operation switches  108  and  110  are controlled respective by two-phase, preferably non-overlapping clocks supplied by a clock generator (not shown in  FIG. 1 ). As shown in  FIG. 1   b , each of these clock signals comprises a charge phase Phi 1  during which switch  110  is connected to V mid2  and switch  108  is connected to either V P  or V N , and capacitor C 2   106  is charged and a dump phase Phi 2  during which switch  110  is connected to C f  and switch  108  is connected to C f , and the charge on capacitor C 2   106  is shared with or dumped to the feedback capacitor C f    104 . This clocking scheme can conveniently be represented by the table of  FIG. 1   c , reproduced below as Table 1a. 
   
     
       
             
           
             
             
             
           
         
             
               TABLE 1a 
             
           
           
             
                 
             
             
               Switch positions versus clock phase for the circuit of FIG. 1a 
             
           
        
         
             
                 
               Connected to: 
                 
             
             
               Switch 
               During Phi1 (Charge) 
               During Phi2 (Dump) 
             
             
                 
             
             
               110 
               Vmid2 
               Cf 
             
             
               108 
               VP/VN 
               Cf 
             
             
                 
             
           
        
       
     
   
   Henceforth clocking schemes for subsequent circuits will likewise be represented by tables along the lines of table 1a, these representing corresponding, preferably non-overlapping switch control clock signals. 
     FIG. 1   d  shows an example of a clock generator circuit  150  for the circuit of  FIG. 1   a . The input data signal is DIN. An external clock CKIN generates non-overlapping clocks CK 1  and CK 2 . CK 1  is ON in clock phase Phi 1 , CK 2  is ON in clock phase Phi 2 . CK 2  can thus be used to drive the poles of switches  108  and  110  connecting to Cf during Phi 2 , and CK 1  is suitable to drive the pole of switch  110  connecting to V mid2  during Phi 1 . To drive the remaining poles of switch  108  during Phi 1  to VP when DIN is high and VN when DIN is low, clocks CK 1 A and CK 1 B are generated by the AND gates  152   a  and  152   b . The operation of these clocks is summarised in the expanded version of Table 1a, in Table 1b below, where the clocks in the right-hand column correspond to the connections shown in the centre two columns. 
   
     
       
             
             
             
             
           
         
             
               TABLE 1b 
             
             
                 
             
             
                 
               Connected to: 
                 
                 
             
             
                 
               During Phi1 
               During Phi2 
             
             
               Switch 
               (Charge) 
               (Dump) 
               By Clock: 
             
             
                 
             
           
           
             
               110 
               Vmid2 
                 
               CK1 
             
             
                 
                 
               Cf 
               CK2 
             
             
               108 
               VP/ 
                 
               CK1A 
             
             
                 
               VN 
                 
               CK1B 
             
             
                 
                 
               Cf 
               CK2 
             
             
                 
             
           
        
       
     
   
     FIG. 1   e  shows a timing diagram the circuit of  FIG. 1   d , in particular CKIN  160 , DIN  162  (11001 . . . ), CK 1   164 , CK 2   166 , CK 1 A  168   a , &amp; CK 1 B  168   b ; note the underlap of clocks CK 1 , CK 2 , and CK 1 A, CK 1 B alternating according to DIN. 
   In more detail, during the charging phase Phi 1  capacitor C 2  is charged, with V mid2  (generally the same voltage as V mid ) applied to one terminal via switch  110  and V P  or V N  applied to the other terminal via switch  108 . Typically values of V P    112  and V N    114  are +3V and −3V respectively, with respect to V mid    118 . The choice of V P  or V N  for any particular cycle is defined by a digital delta-sigma signal applied to switch  108  during this charging phase Phil 1 . During the dump phase, Phi 2 , C 2  is disconnected from V P , V N  and V mid2  and connected in parallel with the op amp feedback capacitor C f    104  via switches  110  and  108 . 
   Typically C 2   106  is much smaller than the op amp feedback capacitor C f    104 . The left-hand side of C 2  is switched between a voltage equal to V mid    118  (since the inverting terminal of op amp  102  is a virtual earth, that is it is at substantially the same voltage as the non-inverting terminal) and V mid2 . Assume for simplicity that as usual V mid2 =V mid . Then if V P  rather than V N  is applied to the other end of C 2  during Phi 1  for many consecutive clock cycles, the output V out    120  will converge to equal V P    112 , to achieve a steady state in which both the left-hand side and the right-hand side of C 2   106  are switched between equal voltages each cycle. Similarly if V N    114  is applied each cycle, V out  will converge to V N    114 . If V P  and V N  are each applied half the time, the output  120  will be the average of V P  and V N . In general for a V P :V N  duty cycle of m:(1−m), the steady-state output will be given by:
 
 V   out   =m*V   P +(1− m )* V   N   (Equation 1)
 
   For example, if m=0.9, V out =0.9V P +0.1V N . In this context “duty cycle” should be understood as the fraction, proportion or ratio of the number of connections to V P  to the number of connections to V N , for example measured in clock cycles. 
   In general m will vary with time, corresponding to the varying value of the input audio signal, but the clock frequency is generally much higher than a typical audio frequency, so it is a good approximation to discuss operation in terms of an m value constant over many cycles. 
   The duty cycle m is controlled by a digital delta-sigma signal to alternately connect C 2   106  to V P  and V N  to provide the required output voltage  120 . This output voltage  120  will vary from V P  to V N  according to the duty cycle applied. Thus, in effect, the DAC circuit may be considered as having a gain from the voltages ( 112  and  114 ) applied to the switched capacitor to the output  102  defined by (V out,max −V out,min )/(V P −V N ) of substantially unity. 
   The skilled person will recognise that the gain of circuit  100  may be adjusted, for example, by connecting a voltage divider to output  120  and taking the voltage for capacitor C f    104  from a tap point on this divider, for example to provide a gain of 2. However typically the circuit will have a relatively low gain, for example less than 10 and more typically less than 3. This also applies to the DAC circuits which are described later. 
   An earlier patent of one of the inventors, U.S. Pat. No. 6,573,850, recognised that the above-described prior art DAC circuit suffers from a problem associated with signal-dependent loading of reference voltage sources for voltages V P    112  and V N    114 . The way in which this problem arises and the solution provided by U.S. Pat. No. 6,573,850 is discussed further below. Other background prior art (also referenced in U.S. Pat. No. 6,573,850) can be found in U.S. Pat. No. 5,790,064 (a switched capacitor integrator which does not operate on the principle of charge sharing but instead dumps charge into an input of an operational amplifier which in turn drives an integration capacitor), U.S. Pat. No. 5,703,589 and FR 2,666,708 (other switched capacitor integrators), all for analogue-to-digital converter circuits and not intended or suitable for use as high quality digital-to-analogue converters; U.S. Pat. No. 4,896,156, U.S. Pat. No. 4,994,805, EP 0 450 951 (and U.S. Pat. No. 5,148,167), U.S. Pat. No. 6,081,218, U.S. Pat. No. 6,337,647, EP 1 130 784, and “A 120 dB Multi-bit SC Audio DAC with Second Order Noise Shaping”, J Rhode, Xue-Mei Gong et al., pages 344–5 in IEEE Solid State Circuit Conference Procs. (ISSCC) 2000. 
   The manner in which signal-dependent reference source loading arises in the DAC circuit of  FIG. 1  can be seen by considering the charge taken from V P  and V N  averaged over many cycles. For the above m:(1−m) duty cycle, and assuming for simplicity that C 2 &lt;&lt;C f , so that cycle-by-cycle ripple on V out  is small, for V P  this is given by:
         m*(V P −V out )*C 2     =m*(V P −(m*V P +(1−m)*V N ))*C 2     =m*(1−m)*(V P −V N )*C 2 
 
This has a parabolic dependence on m, with zeros at m=0 and m=1, and a maximum of 0.25*(V P −V N )*C 2  at m=0.5. Loading of V N  shows a similar dependence.
       

     FIG. 2  shows a digital-to-analogue converter  200  with a differential voltage output  120   a, b , based upon the circuit of  FIG. 1 . As can be seen from inspection of  FIG. 2 , the differential DAC  200  comprises two similar but mirrored circuits  100   a ,  100   b , each corresponding to DAC  100 . The positive differential signal processing circuit portion  100   a  generates a positive output V out +  120   a  and the negative differential signal processing portion  100   b  generates a negative voltage output V out   −   120   b . Likewise the positive circuit portion  100   a  is coupled to first reference voltage supplies V P   +   112   a  and V N   +   114   a  and the negative circuit portion  100   b  is coupled to second reference voltage supplies V P   −   112   b  and V N   −   114   b.    
   Preferably V P   +   112   a  and V P   −   112   b  are supplied from a common positive reference voltage source and V N   +   114   a  and V N   −   114   b  are supplied from a common negative reference voltage source. Thus preferably V P   +  and V P   −  are at the same voltage and V N   +  and V N   −  are at the same voltage. As can be seen C 2   +   106   a  is switched to references V P   +   112   a  and V N   +   114   a  and C 2   −   106   b  is switched to references V P   −   112   b  and V N   −   114   b . Voltages V mid2   +   116   a  and V mid2   −   116   b  preferably have the same value, preferably the value of V mid    118 , typically ground. Preferably feedback capacitors  104   a, b  and switched capacitors  106   a, b  have the same value and op amps  102   a  and  102   b  are matched. Op amps  102   a, b  may comprise a single differential-input, differential-output op amp. These same comments also apply to the later described differential DAC circuits. 
   A clocking scheme for the DAC of  FIG. 2  is shown in Table 2 below: 
   
     
       
             
           
             
             
             
           
         
             
               TABLE 2 
             
           
           
             
                 
             
             
               Switch positions versus clock phase for the 
             
             
               differential circuit of FIG. 2 
             
           
        
         
             
                 
               Connected to: 
                 
             
             
               Switch 
               During Phi1 (Charge) 
               During Phi2 (Dump) 
             
             
                 
             
             
               110a 
               Vmid2+ 
               Cf+ 
             
             
               110b 
               Vmid2− 
               Cf− 
             
             
               108a 
               VP+/VN+ 
               Cf+ 
             
             
               108b 
               VN−/VP− 
               Cf− 
             
             
                 
             
           
        
       
     
   
   Continuing to refer to  FIG. 2 , in operation, whenever V P   +  is chosen to charge C 2   + , then V N   −  is selected to charge C 2   − . Thus by symmetry, from equation (1) above, one can write
 
 V   out   −   =m*V   N   − +(1− m )* V   P   −   (Equation 2)
 
   When, for example, m=0.9, V out   − =0.9 V N   − +0.1 V P   − ; when m=0.5, V out   + =V out   − =(V P +V N )/2. As m varies V out   +  and V out   −  will swing in equal amplitude but opposite polarities about this common-mode (m=0.5) voltage. 
   The average charge taken from V P   +  will be as above:
         m*(V P   + −V out   + )*C 2   +     =m*(V P +−(m*V P   + (1−m)*V N ))*C 2     =m*(1−m)*(V P   + −V N   + )*C 2   +         

   The average charge taken from V P   −  will be:
         (1−m)*(V P   − −V out   −)*C2   −     =(1−m)*(V P −m*V N   − −(1−m)*V P   − )*C 2   −     =(1−M)*m(V P   − −V N   − )*C 2   −         

   Thus the average total charge taken from V P  (that is V P   +  and V P   − ) is 2*m*(1−m)*(V P −V N )*C 2  (where V P   + =V P   − =V P  and C 2   + =C 2   − =C 2 ). This is just double the charge of the single-sided implementation, as might be surmised by the symmetries of the circuit. Again the function is parabolic, with a minimum of zero (for m=0 or 1) and a maximum of 0.5*(V P −V N )*C 2 . 
   To take an example, consider a case where V P =+3V, V N =−3V, and C 2 =10 pF. Assuming the circuit is clocked at 10 MHz, this will give rise to a current varying from zero to 0.5*(+3V−(−3V))*10 pF*01 MHz=300 μA drawn from V P  and V N  depending on the low-frequency level of the output signal V out . If the equivalent source impedance of the sources of V P  and V N  are 1 ohm each, this will give a modulation of (V P −V N ) of 0.6 m Vpk−pk., that is 0.1% of (V P −V N ). This will modulate the output signal by a similar amount (as with a multiplying DAC) and is a gross effect in a system aimed at typically −100 dB (0.001%) THD. 
     FIG. 3  shows a multibit differential switched capacitor DAC  300 , a common extension to the circuit of  FIG. 2 . In this extension multiple independently switched capacitors are used in place of the capacitor C 2   +  (and C 2   − ). Although  FIG. 3  shows just two additional capacitors for each circuit  106   aa,bb  (for simplicity) and four corresponding additional switches  108   aa,bb ,  110   aa,bb , in practice a plurality of additional capacitors and switches may be provided for each differential signal processing circuit portion. A clocking scheme for this circuit is given in Table 3 below. 
   
     
       
             
           
             
             
             
             
           
         
             
               TABLE 3 
             
           
           
             
                 
             
             
               Switch positions versus clock phase for the 
             
             
               multi-bit differential circuit of FIG. 3 
             
           
        
         
             
                 
                 
               Connected to: 
                 
             
             
                 
               Switch 
               During Phi1 (Charge) 
               During Phi2 (Dump) 
             
             
                 
                 
             
             
                 
               110a 
               Vmid2+ 
               Cf+ 
             
             
                 
               110b 
               Vmid2− 
               Cf− 
             
             
                 
               108a 
               VP+/VN+ 
               Cf+ 
             
             
                 
               108b 
               VN−/VP− 
               Cf− 
             
             
                 
               110aa 
               Vmid2+ 
               Cf+ 
             
             
                 
               110ba 
               Vmid2− 
               Cf− 
             
             
                 
               108aa 
               VP+/VN+ 
               Cf+ 
             
             
                 
               108ba 
               VN−/VP− 
               Cf− 
             
             
                 
               . . . 
             
             
                 
                 
             
           
        
       
     
   
   In effect, the switched capacitors C 2  of  FIG. 3  may be replaced by an array of capacitors. The capacitors in such arrays may or may not be binary weighted. In one arrangement the LSB capacitors are binary weighted, but the MSB capacitors are equally weighted, and used in a random manner to decrease the effects of mismatch. Suitable methods for deriving the necessary multi-bit delta-sigma digital control waveforms, to define the cycle-by-cycle connections to V P  or V N  of each capacitor in these arrays, are well known to those skilled in the art and described, for example, in “Delta-sigma data converters—theory design and simulation” edited by Steven R Norsworthy, Richard Schreier, Gabor C Temes, IEEE Press, New York 1997, ISBN 0-7803-1045-4, hereby incorporated by reference. Analysis of this circuit gives a similar variation in reference loading with signal. 
   There is therefore a need for charge-sharing, switched capacitor DAC circuits which exhibit reduced signal-dependent loading of reference sources. 
   The circuit of U.S. Pat. No. 6,573,850 achieves this by briefly connecting the switched capacitor to a substantially signal-independent reference voltage prior to connection of this capacitor to one of the reference voltages. Connecting the switched capacitor to a substantially signal-independent reference before connecting it to one of the references allows signal-dependent charges to flow onto or off the switched capacitor before the capacitor is recharged. In other words the charge on the switched capacitor may be brought to a substantially signal-independent or predetermined state of charge prior to its connection to one of the references, so that there is little or no signal-dependent loading of these references. However the circuits of U.S. Pat. No. 6,573,850 require an additional clock phase to be generated and distributed, and generally also require the generation of a suitable signal-independent reference voltage. 
   Two further issues arise with high performance switched-capacitor audio DACs, firstly problems of flicker noise (sometimes called 1/f noise) in the MOS devices typically used to implement the op amps, and secondly problems with crosstalk between amplifiers due to combinations of common supply impedances, poor audio-frequency supply decoupling, and finite op amp power-supply rejection. 
   Flicker noise power is approximately inversely proportional to the area of the devices used, so to gain 6 dB in reduced flicker noise requires input devices of four times the area. For SNR of 100 dB or greater (120 dB is becoming a target for high-performance systems), it rapidly becomes impractical to achieve a flicker noise corner frequency below say 1 kHz, and even then with a significant impact on chip area and hence cost. 
   The load regulation bandwidth of active power supplies is often inadequate to prevent millivolts of ripple at higher audio frequencies, especially as these supplies may also be supplying high-power outputs to drive speakers or headphones. Often several channels of DAC (e.g. six) are implemented on the same silicon chip but without the expense of extra supply pins it is difficult to distribute the supplies to all amplifiers (including power output stages) without several ohms of common supply impedance. The resulting modulation of the local supply voltage of each channel in conjunction with the finite supply rejection of the op amps, itself diminishing with high audio frequency, can be a significant source of crosstalk between channels relative to a typical target of 100 dB. 
   Both the op amp flicker noise and op amp supply rejection (or rather lack of it) can be modelled as a modulation of the input offset voltage of the op amps in question. One known technique for mitigating these effects is the “chopper” technique.  FIG. 4  shows this applied to a simple DAC circuit  400 . Table 4, below, shows a clocking scheme for the DAC of  FIG. 4 . 
   
     
       
             
           
             
             
             
             
             
           
         
             
               TABLE 4 
             
           
           
             
                 
             
             
               Switch positions versus clock phase for the 
             
             
               chopped differential DAC circuit of FIG. 4 
             
           
        
         
             
                 
               Connected to: 
                 
                 
                 
             
             
                 
               During Phi1 
               During Phi2 
               During Phi3 
               During Phi4 
             
             
               Switch 
               (Charge) 
               (Dump) 
               (Charge) 
               (Dump) 
             
             
                 
             
             
               110a 
               Vmid2+ 
               Cf+ 
               Vmid2+ 
               Cf+ 
             
             
               110b 
               Vmid2− 
               Cf− 
               Vmid2− 
               Cf− 
             
             
               108a 
               VP+/VN+ 
               Cf+ 
               VP+/VN+ 
               Cf+ 
             
             
               108b 
               VN−/VP− 
               Cf− 
               VN−/VP− 
               Cf− 
             
             
               401a 
               Cf+ 
               Cf+ 
               Cf− 
               Cf− 
             
             
               401b 
               Cf− 
               Cf− 
               Cf+ 
               Cf+ 
             
             
               402a 
               Cf+ 
               Cf+ 
               Cf− 
               Cf− 
             
             
               402b 
               Cf− 
               Cf− 
               Cf+ 
               Cf+ 
             
             
                 
             
           
        
       
     
   
   In the differential circuit of  FIG. 4  the difference in offsets between the two op amps is modelled as an effective offset V off  to the first op amp  102   a . In one clock cycle, op amp  102   a  is connected to one feedback capacitor, and its effective offset V off  affects the output of the respective output, V out   +  by V off . In the next clock cycle, op amp  102   a  is connected to the other symmetric half of the capacitor network, and has the same effect on the negative output V out   − . The low-frequency offset of the op amp thus appears on the outputs as a common-mode average signal of V off/ 2, together with a differential output as a modulation of +/−V off/ 2 at f s/ 2 where f s  is the sample rate of the input signal (ie. the charge-dump cycle frequency), but there is no corresponding low-frequency differential signal. In embodiments the high frequency components are filtered out by a subsequent post-filter preferably employed in any case to attenuate the ultrasonic high-frequency delta-sigma quantisation noise components. 
   The differential DAC circuits of U.S. Pat. No. 6,573,850 are intended to provide a substantially constant load on a clock cycle-by-cycle basis, for example to give a constant charge load on V P  each clock cycle. We will now describe alternative schemes, based on a different but related principle, providing a substantially constant charge load only when averaged over multiple clock cycles. This is nonetheless useful, since the clock frequency is normally much greater than the signal frequency and thus any artefacts at half the clock frequency can be easily post-filtered. In any case some post-filtering is generally required because of spikes of current on V P  and V N  at the clock frequency. 
   SUMMARY OF THE INVENTION 
   According to a first aspect of the present invention there is therefore provided a differential switched capacitor digital-to-analogue (DAC) circuit comprising first and second differential signal circuit portions for providing respective positive and negative signal outputs with respect to a reference level, and having at least one first reference voltage input and at least one second reference voltage input for receiving respective positive and negative references with respect to said reference level; each of said first and second circuit portions comprising an amplifier with a feedback capacitor, a second capacitor, and a switch to switchably couple said second capacitor to a selected one of said reference voltage inputs to charge the second capacitor and to said feedback capacitor to share charge with the feedback capacitor, and wherein said switch of said first circuit portion is further configured to connect said second capacitor of said first circuit portion to share charge with said feedback capacitor of said second circuit portion, and wherein said switch of said second circuit portion is further configured to connect said second capacitor of said second circuit portion to share charge with said feedback capacitor of said first circuit portion. 
   The facility to connect the second capacitor of each (say the positive) circuit portion to share charge with the feedback capacitor of either circuit portion enables the second capacitor to in effect be alternately pre-charged to positive and negative (signal dependent) nodes so that, on average, signal dependent loading of a reference source supplying positive and negative (voltage) references to which the second capacitor is connected for charging is mitigated. More particularly, in embodiments each second capacitor is connected alternately to positive and negative signal-dependent nodes of the circuit (in effect to share charge with the feedback capacitors of the positive and negative circuit portions). Still more particularly each second capacitor is connected alternately to positive and negative feedback capacitor (signal) nodes firstly when being charged to the positive reference voltage, and secondly when being charged to the negative reference voltage. Charging each second capacitor to both the positive reference voltage (for two charge-dump cycles) and to the negative reference voltage (for two charge-dump cycles) enables the capacitor to be charged (positively, and negatively) in such a way that the charge can be dumped to positive and negative signal nodes (feedback capacitors), thus facilitating the above-mentioned positive/negative pre-charge. In embodiments this results in an eight phase charge-dump clocking scheme, comprising four successive charge-dump cycles, the second (switched) capacitors being connected to a positive signal node for a first pair of charge-dump cycles and to a negative signal node for a second pair of charge-dump cycles. 
   According to a related aspect of the present invention there is therefore further provided a differential switched capacitor circuit comprising positive and negative circuit portions to provide respective positive and negative differential signal outputs based upon positive and negative references, each of said positive and negative circuit portions comprising an operational amplifier with a feedback capacitor and at least one switched capacitor connectable to one of said positive and negative references to store charge and to one of a positive and negative signal node to substantially dump said stored charge to a said feedback capacitor, and wherein said switched capacitors of said positive and negative circuit portions are switched according to an eight phase clocking scheme comprising four successive charge-dump cycles and in which said switched capacitors are connected to a said positive signal node for a first pair of said charge-dump cycles and to a said negative signal node for a second pair of said charge-dump cycles. 
   Preferred embodiments of the above described aspects of the invention also chop or exchange the amplifiers for the first and second (positive and negative) circuit portions in alternate charge-dump cycles, preferably alternating every second charge-dump cycle. 
   In embodiments this provides additional benefits, of firstly desensitising the output signal to flicker noise of the amplifiers employed, allowing smaller devices to be used therein, with a consequent chip area saving; and secondly improving the rejection of audio frequency supply ripple, giving potentially less crosstalk between DACs, especially when sharing supplies on one chip, or allowing relaxation of the requirements for audio frequency supply decoupling for a given performance, with potential external component cost savings. 
   Preferred embodiments of the above described aspects of the invention further include a switch controller or clock generator to control switching of the second (switched) capacitors and, where implemented, of the amplifiers of the first and second circuit portions, in particular responsive to a digital input to the DAC. 
   In embodiments the above described DACs may be implemented as multi-bit DACs by using a plurality or array of capacitors in place of each of the above mentioned second (switched) capacitors, providing corresponding switching to allow each capacitor of the array to be connected to a selected one of the feedback capacitors of the first and second (or positive and negative) circuit portions. 
   In a further aspect the invention provides a method of operating a differential digital-to-analogue (DAC) circuit to reduce signal dependent loading of a reference source associated with the DAC circuit, the DAC circuit comprising positive and negative signal processing devices each with a feedback capacitor coupled to a respective positive and negative signal node and each having a second capacitor switchably couplable to said reference source for charging and to a said signal node for dumping charge to a said feedback capacitor, the method comprising repeatedly: coupling said second capacitors to said reference source for charging; and coupling said second capacitors to alternate ones of said positive and negative signal nodes for dumping stored charge to a said feedback capacitor; such that on average over a plurality of charge-dump cycles charge loading of said reference source by said DAC circuit is substantially constant. 
   Preferably each of the second capacitors is coupled to one of said positive and negative signal nodes for two cycles and then to the other of said positive and negative signal nodes for two cycles, for each of these two cycles the capacitor being charged from the same (positive or negative) reference voltage level (which preferably also alternates every two charge-dump cycles). 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other aspects of the invention will now be further described, by way of example only, with reference to the accompanying figures in which: 
       FIGS. 1   a  to  1   e  show, respectively a switched capacitor digital-to-analogue converter (DAC) according to the prior art, a clocking scheme for the DAC of  FIG. 1 , and a tabular representation of the clocking scheme, a clock generator circuit for the clocking scheme, and a timing diagram for the clock generator circuit; 
       FIG. 2  shows a differential switched capacitor DAC according to the prior art; 
       FIG. 3  shows a multi-bit differential switched capacitor DAC according to the prior art; 
       FIG. 4  shows a differential switched capacitor DAC with chopper switching of the operational amplifiers; 
       FIGS. 5   a  to  5   c  show, respectively, a digital-to-analogue converter (DAC) with chopper connections to the switched capacitors to reduce signal-dependent reference source loading, on eight phase clock generator for the DAC of  FIG. 5   a , and a timing diagram for the clock generator, according to an embodiment of the present invention; 
       FIG. 6  shows a digital-to-analogue converter (DAC) circuit with means to reduce signal dependent reference loading by simplified chopping connections to the switched capacitors; 
       FIG. 7  shows a digital-to-analogue converter (DAC) circuit with chopper connections to op amp and switched-capacitor; and 
       FIG. 8  shows multi-bit extension to the circuit of  FIG. 7 . 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Referring to  FIG. 5   a , this shows a differential DAC circuit  500  including chopper switches  501   a,b ,  502   a,b  to reduce the signal-dependent reference loading. The DAC circuit of  FIG. 5  is a development of that shown in  FIG. 2  (like elements are indicated by like reference numerals) and comprises a pair of DAC circuits  500   a,b  to provide a differential output  520   a, b.    
   Capacitor  106   a  is still charged to V P  or V N  via switches  110   a ,  108   a . However, rather than discharging directly via switches  110   a ,  108   a  onto capacitor  104   a , it discharges onto either capacitor  104   a  or  104   b , via additional connections  503 ,  505 , and  504 ,  506 , according to the polarity of additional series switches  501   a ,  502   a . There is a similar arrangement for capacitor  106   b . The switches  501   a ,  501   b ,  502   a ,  502   b  may be switched to alternate every cycle giving a 4-phase clocking scheme as shown in Table 5a (below) or every second cycle giving an 8-phase clocking scheme as shown in Table 5c. Other possible clocking schemes are discussed later. By alternately discharging to either capacitor  106   a  or  106   b , i.e. to nodes whose signal voltages are equal and opposite, the aim is to cancel the signal-dependent terms in time-average charge taken from references V P  and V N . 
   Table 5a, below, shows a 4-phase clocking scheme for the DAC  500  of  FIG. 5   a . 
   
     
       
             
           
             
             
             
             
             
           
         
             
               TABLE 5a 
             
           
           
             
                 
             
             
               Switch positions versus clock phase for a 
             
             
               4-phase clocking scheme for the DAC circuit of FIG. 5 
             
           
        
         
             
                 
               Connected to: 
                 
                 
                 
             
             
                 
               During Phi1 
               During Phi2 
               During Phi3 
               During Phi4 
             
             
               Switch 
               (Charge) 
               (Dump) 
               (Charge) 
               (Dump) 
             
             
                 
             
             
               110a 
               Vmid2+ 
               501a 
               Vmid2+ 
               501a 
             
             
               110b 
               Vmid2− 
               501b 
               Vmid2− 
               501b 
             
             
               108a 
               VP+/VN+ 
               502a 
               VN+/VP+ 
               502a 
             
             
               108b 
               VN−/VP− 
               502b 
               VP−/VN− 
               502b 
             
             
               501a 
               Cf+ 
               Cf+ 
               Cf− 
               Cf− 
             
             
               501b 
               Cf− 
               Cf− 
               Cf+ 
               Cf+ 
             
             
               502a 
               Cf+ 
               Cf+ 
               Cf− 
               Cf− 
             
             
               502b 
               Cf− 
               Cf− 
               Cf+ 
               Cf+ 
             
             
                 
             
           
        
       
     
   
   This clocking scheme is implemented by a clock generator  508 , in response to a digital signal input  510 , the clock generator also performing delta-sigma digital signal preprocessing in a conventional manner. In later described DAC circuits the clock generator will not be shown in the figures, for simplicity. The switches of this and the later described DAC circuits may comprise FET (or MOSFET) switches controlled by clock generator  508 . Additional low pass filtering (not shown in the Figure) may be provided on outputs  520   a,b , starting to roll off, for example just above the audio band (say 0.1 dB at 20 kHz) to maximise attenuation of ultrasonic delta-sigma quantisation noise, and so providing substantial (say&gt;40 dB) attenuation by fs/4, (typically 3 MHz). 
   We next analyse the clocking scheme of Table 5a (it is helpful to read this in conjunction with Table 5b below). As before assume C f   +   104   a  is to receive positive increments of charge from V P  for a fraction m of the clock cycles, and negative increments of charge from V N  for the remaining fraction (1−m). Then C f   −   104   b  is to receive positive increments of charge from VP for a fraction (1−m) of the clock cycles, and negative increments of charge from V N  for the remaining fraction m, giving V out   + =m*V P   + (1−m)*V N , V OUt   − =(1−m)*V P   + m*V N . 
   In those (charge) cycles where C 2   +  has just previously been disconnected from C f   −  (and hence V out   − ), i.e. Phi 1 , it will be connected to C f   +  on the next (dump) phase Phi 2 , so for a fraction (m) of the cycles it will be charged to V P , taking a charge of C 2   + *(V P −V out   − ) and for a fraction (1−m) of the cycles it will be charged to V N , taking a charge of C 2   + * (V N −V out   − ). In those (charge) cycles where C 2   +  has just been disconnected from C f   +  (and hence V out   + ), i.e. Phi 3 , it will be connected to C f   −  on the next (dump) phase Phi 4 , so for a fraction (1−m) of the cycles it will be charged to V P , taking a charge of C 2   + *(V P −V out   − ), and for a fraction (m) of the cycles it will be charged to V N , taking a charge of C 2   + *(V N −V out ). 
   Thus the (average) charge taken from V P  by C 2   +  over each four clock phases will be:
 
C 2   + *( V   P   −V   out   + )*(1−m)+C 2   + *( V   P   −V   out   − )* m  
 
   Since C 2   +  and C 2   −  are indistinguishable in this circuit, C 2   −  will take an equal charge, so the total charge taken from V P  will be:
 
2*C 2 *( V   P   −V   out   + *(1 −m )−V out   −   *m ).
 
   Noting that V out   +=m*V   P +(1−m)*V N , V out   − =(1−m)*V P +m*V N , the total charge from V P  can be written as:
         2*C 2 *(V P −(1−m)*(m.V P +(1−m).V N )−m*((1−m).V P +m*V N )   =2*C 2 *(V P (1−m+m 2 −m+m 2 )−V N (1−2 m+m 2 +m 2 ))   =2*C 2 *(V P −V N )(1−2 m+2 m 2 )
 
However this is still not signal independent as desired (having a maximum at m=0.5), essentially because of the correlation of V out   +  and V out   −  with m.
       

   Table 5b below summarises the charging and dumping of one of the switched capacitors (C 2   + ) and the above analysis. 
   
     
       
             
             
           
             
             
             
             
             
             
           
             
             
             
             
             
           
         
             
                 
               TABLE 5b 
             
             
                 
                 
             
             
                 
               Clock 
             
             
                 
                 
             
           
           
             
                 
             
           
        
         
             
               Charge 
               Φ 1 
               C2 +  (for fraction m) 
               to V P   
               [C2 +  was at V out   − ] 
               cycle 1 
             
             
               Dump 
               Φ 2 
               C2 +   
               to C f   +   
               [C2 +  to V out   + ] 
             
             
               Charge 
               Φ 3 
               C2 +  (for fraction m) 
               to V N   
               [C2 +  was at V out   + ] 
               cycle 2 
             
             
               Dump 
               Φ 4 
               C2 +   
               to C f   −   
               [C2 +  to V out   − ] 
             
           
        
         
             
               During 
               Φ 1 
               C2 +  takes 
               m C2 +  (V P  − V out   − ) 
               from V P   
             
             
               During 
               Φ 3 
               C2 +  takes 
               (1 − m) C2 +  (V P  − V out   + ) 
               from V P   
             
             
               Total 
               for C2 +   
                 
               C2 (V P  − V N )(1 − 2m + 2m 2 ) 
             
             
               (average) 
               for C2 −   
                 
               C2 (V P  − V N )(1 − 2m + 2m 2 ) 
             
             
               charge over 
               (same as C2 + ) 
             
             
               several cycles 
                 
                 
                 
             
             
               Total 
                 
                 
               2(C2(V P  − V N )(1 − 2m + 2m 2 ) 
                 
             
             
                 
             
           
        
       
     
   
   The situation can be improved by using an alternate, 8-phase clocking scheme for the DAC  500  of  FIG. 5   a , as shown in Table 5c below, where the new switches are clocked at half the clock rate. 
   
     
       
             
           
             
             
             
             
             
             
             
             
             
           
         
             
               TABLE 5c 
             
           
           
             
                 
             
             
               Switch positions versus clock phase for an 
             
             
               8-phase clocking scheme for the DAC circuit of FIG. 5 
             
           
        
         
             
                 
               Connected 
                 
                 
                 
                 
                 
                 
                 
             
             
                 
               to: 
             
             
                 
               Phi1 
               Phi2 
               Phi3 
               Phi4 
               Phi5 
               Phi6 
               Phi7 
               Phi8 
             
             
               Switch 
               (Charge) 
               (Dump) 
               (Charge) 
               (Dump) 
               (Charge) 
               (Dump) 
               (Charge) 
               (Dump) 
             
             
                 
             
             
               110a 
               Vmid2+ 
               501a 
               Vmid2+ 
               501a 
               Vmid2+ 
               501a 
               Vmid2+ 
               501a 
             
             
               110b 
               Vmid2− 
               501b 
               Vmid2− 
               501b 
               Vmid2− 
               501b 
               Vmid2− 
               501b 
             
             
               108a 
               VP+/VN+ 
               502a 
               VP+/VN+ 
               502a 
               VN+/VP+ 
               502a 
               VN+/VP+ 
               502a 
             
             
               108b 
               VN−/VP− 
               502b 
               VN−/VP− 
               502b 
               VP−/VN− 
               502b 
               VP−/VN− 
               502b 
             
             
               501a 
               Cf+ 
               Cf+ 
               Cf+ 
               Cf+ 
               Cf− 
               Cf− 
               Cf− 
               Cf− 
             
             
               501b 
               Cf− 
               Cf− 
               Cf− 
               Cf− 
               Cf+ 
               Cf+ 
               Cf+ 
               Cf+ 
             
             
               502a 
               Cf+ 
               Cf+ 
               Cf+ 
               Cf+ 
               Cf− 
               Cf− 
               Cf− 
               Cf− 
             
             
               502b 
               Cf− 
               Cf− 
               Cf− 
               Cf− 
               Cf+ 
               Cf+ 
               Cf+ 
               Cf+ 
             
             
                 
             
           
        
       
     
   
   To analyse this scheme again consider operation with a “duty cycle” of m (it is helpful to read this in conjunction with Table 5d below). We start with Phi 1  where C 2   +  has just been disconnected from V out   −  and anticipates a connection with V out   +  in the second half of the cycle, dump phase Phi 2 . The probability of being charged to V P  from V out   −  is m, giving an expected average charge taken from V P  of m.C 2   +  (V P −V out   − ). The next Phi 3 , there is still a probability m of being charged to V P , giving an expected charge taken from V P  of m.C 2   + (V P −V out   + ). Thus the (average) charge taken from V P  by C 2   +  over these two clock cycles is 2m.C 2   + (V P −(V out   + +V out   − )/2). Similarly, the charge taken by C 2   −  over these two clock periods is 2(1−m)C 2   + (V P −(V out   −+V   out   + )/2). So the total charge over these two clock periods (which is the same for the next two clock periods) taken by the combination of C 2   +  and C 2   −  is 2.C 2 (V P −(V out   +  +V out   − )/2). Since the signals on V out   +  and V out   −  are in antiphase, this is independent of the signal (and can be simplified to C 2 (V P −V N ) relying on (V out ++V out −)/2=(V P +V N )/2). 
   Table 5d below summarises the 8-phase charging and dumping clocking scheme for one of the switched capacitors (C 2   + ) and the results of the above analysis. 
   
     
       
             
             
           
             
             
             
             
             
             
           
             
           
         
             
                 
               TABLE 5d 
             
             
                 
                 
             
             
                 
               Clock 
             
             
                 
                 
             
           
           
             
                 
             
           
        
         
             
               Charge 
               Φ1 
               (for fraction m) 
               to V P   
               [C2 +  was at V out   − ] 
               cycle 1 
             
             
               Dump 
               Φ2 
                 
               to C f   +   
               [C2 to V out   + ] 
               (V P C f   + ) 
             
             
               Charge 
               Φ3 
               (for fraction m) 
               to V P   
               [C2 was at V out   + ) 
               cycle 2 
             
             
               Dump 
               Φ4 
                 
               to C f   +   
               [C2 to V out   + ] 
               (V P C f   + ) 
             
             
               Charge 
               Φ5 
               (for fraction m) 
               to V N   
               [C2 was at V out   + ] 
               cycle 3 
             
             
               Dump 
               Φ6 
                 
               to C f   −   
               [C2 to V out   − ] 
               (V N C f   − ) 
             
             
               Charge 
               Φ7 
               (for fraction m) 
               to V N   
               [C2 +  was at V out   − ] 
               cycle 4 
             
             
               Dump 
               Φ8 
                 
               to C f   −   
               [C2 to V out   − ] 
               (V N C f   − ) 
             
           
        
         
             
               Charge taken from V P  during charging phases: 
             
             
               
                 
                   
                     
                       
                         
                           
                             
                                 
                             
                           
                         
                         
                           
                             
                               Φ 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                           
                         
                         
                           
                             
                               Φ 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               3 
                             
                           
                         
                         
                           
                             
                               Sum: 
                             
                           
                         
                         
                           
                             
                               Total: 
                             
                           
                         
                       
                       ⁢ 
                       
                         
                           
                             
                               By 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               
                                 C2 
                                 + 
                               
                             
                           
                           
                             
                                 
                             
                           
                           
                             
                               By 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               
                                 C2 
                                 - 
                               
                               ⁢ 
                               
                                 : 
                               
                             
                           
                         
                         
                           
                             
                               
                                 mC2 
                                 + 
                               
                               ⁡ 
                               
                                 ( 
                                 
                                   
                                     V 
                                     P 
                                   
                                   - 
                                   
                                     V 
                                     out 
                                     - 
                                   
                                 
                                 ) 
                               
                             
                           
                           
                             
                                 
                             
                           
                           
                             
                                 
                             
                           
                         
                         
                           
                             
                               
                                 mC2 
                                 + 
                               
                               ⁡ 
                               
                                 ( 
                                 
                                   
                                     V 
                                     P 
                                   
                                   - 
                                   
                                     V 
                                     out 
                                     + 
                                   
                                 
                                 ) 
                               
                             
                           
                           
                             
                                 
                             
                           
                           
                             
                                 
                             
                           
                         
                         
                           
                             
                               2 
                               ⁢ 
                               
                                 
                                   mC2 
                                   + 
                                 
                                 ( 
                                 
                                   
                                     V 
                                     P 
                                   
                                   - 
                                   
                                     
                                       1 
                                       / 
                                       2 
                                     
                                     ⁢ 
                                     
                                       ( 
                                       
                                         
                                           V 
                                           out 
                                           + 
                                         
                                         + 
                                         
                                           V 
                                           out 
                                           - 
                                         
                                       
                                       ) 
                                     
                                   
                                 
                               
                             
                           
                           
                             
                                 
                             
                           
                           
                             
                               2 
                               ⁢ 
                               
                                 ( 
                                 
                                   1 
                                   - 
                                   m 
                                 
                                 ) 
                               
                               ⁢ 
                               
                                 
                                   C2 
                                   - 
                                 
                                 ( 
                                 
                                   
                                     V 
                                     P 
                                   
                                   - 
                                   
                                     
                                       1 
                                       / 
                                       2 
                                     
                                     ⁢ 
                                     
                                       ( 
                                       
                                         
                                           V 
                                           out 
                                           + 
                                         
                                         + 
                                         
                                           V 
                                           out 
                                           - 
                                         
                                       
                                       ) 
                                     
                                   
                                 
                               
                             
                           
                         
                         
                           
                             
                                 
                             
                           
                           
                             
                               C2 
                               ⁡ 
                               
                                 ( 
                                 
                                   
                                     V 
                                     P 
                                   
                                   - 
                                   
                                     V 
                                     N 
                                   
                                 
                                 ) 
                               
                             
                           
                           
                             
                                 
                             
                           
                         
                       
                     
                   
                 
               
             
             
                 
             
             
               
                 
                   
                     
                       
                         
                           
                             
                               
                                 Φ 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 5 
                               
                               ⁢ 
                               
                                   
                               
                             
                           
                         
                         
                           
                             
                               Φ 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               7 
                             
                           
                         
                         
                           
                             
                               Sum: 
                             
                           
                         
                         
                           
                             
                               Total: 
                             
                           
                         
                       
                       ⁢ 
                       
                         
                           
                             
                               
                                 ( 
                                 
                                   1 
                                   - 
                                   m 
                                 
                                 ) 
                               
                               ⁢ 
                               
                                 
                                   C2 
                                   + 
                                 
                                 ⁡ 
                                 
                                   ( 
                                   
                                     
                                       V 
                                       P 
                                     
                                     - 
                                     
                                       V 
                                       out 
                                       - 
                                     
                                   
                                   ) 
                                 
                               
                             
                           
                           
                             
                                 
                             
                           
                           
                             
                                 
                             
                           
                         
                         
                           
                             
                               
                                 ( 
                                 
                                   1 
                                   - 
                                   m 
                                 
                                 ) 
                               
                               ⁢ 
                               
                                 
                                   C2 
                                   + 
                                 
                                 ⁡ 
                                 
                                   ( 
                                   
                                     
                                       V 
                                       P 
                                     
                                     - 
                                     
                                       V 
                                       out 
                                       - 
                                     
                                   
                                   ) 
                                 
                               
                             
                           
                           
                             
                                 
                             
                           
                           
                             
                                 
                             
                           
                         
                         
                           
                             
                               2 
                               ⁢ 
                               
                                 ( 
                                 
                                   1 
                                   - 
                                   m 
                                 
                                 ) 
                               
                               ⁢ 
                               
                                 
                                   C2 
                                   + 
                                 
                                 ( 
                                 
                                   
                                     V 
                                     P 
                                   
                                   - 
                                   
                                     
                                       1 
                                       / 
                                       2 
                                     
                                     ⁢ 
                                     
                                       ( 
                                       
                                         
                                           V 
                                           out 
                                           + 
                                         
                                         + 
                                         
                                           V 
                                           out 
                                           - 
                                         
                                       
                                       ) 
                                     
                                   
                                 
                               
                             
                           
                           
                             
                                 
                             
                           
                           
                             
                               2 
                               ⁢ 
                               m 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               
                                 
                                   C2 
                                   - 
                                 
                                 ( 
                                 
                                   
                                     V 
                                     P 
                                   
                                   - 
                                   
                                     
                                       1 
                                       / 
                                       2 
                                     
                                     ⁢ 
                                     
                                       ( 
                                       
                                         
                                           V 
                                           out 
                                           + 
                                         
                                         + 
                                         
                                           V 
                                           out 
                                           - 
                                         
                                       
                                       ) 
                                     
                                   
                                 
                               
                             
                           
                         
                         
                           
                             
                                 
                             
                           
                           
                             
                               C2 
                               ⁡ 
                               
                                 ( 
                                 
                                   
                                     V 
                                     P 
                                   
                                   - 
                                   
                                     V 
                                     N 
                                   
                                 
                                 ) 
                               
                             
                           
                           
                             
                                 
                             
                           
                         
                       
                     
                   
                 
               
             
             
                 
             
           
        
       
     
   
     FIG. 5   b  shows an example of a clock generator circuit  550  for the DAC circuit  500  of  FIG. 5   a . The operation of these clocks is summarised in the expanded version of Table 5d in Table 5e, where the clocks in the right-hand column correspond to the connections shown in the centre eight columns. As before, the input data signal is DIN. An external clock CKIN generates non-overlapping clocks CK 1  and CK 2 . CK 1  is ON in odd phases, CK 2  is ON in even clock phases. CK 2  can thus be used to drive the poles of switches  110   a ,  110   b ,  108   a ,  108   b , connecting to  501   a ,  501   b ,  502   a ,  502   b  respectively during even phases, and CK 1  is suitable to drive the poles of switches  110   a ,  110   b  connecting to Vmid 2 +, Vmid 2 − respectively during odd phases. 
   Clock CHCK is derived by dividing CKIN by 4 using the two D-types. From CHCK are generated non-overlapping clocks CHCK 1  and CHCK 2 , respectively driving switches  501   a ,  501   b ,  502   a ,  502   b  to Cf+ or Cf− in alternate sets of four clock phases. 
   To drive the remaining poles of switch, clocks CK 1 A and CK 1 B are generated by the AND gates  552   a  and  552   b , but instead of the gates being driven directly from DIN, DIN is inverted in phases Phi 5  to Phi 8 , to allow for the effective periodic inversion of gain by the chopper action. 
   
     
       
             
             
             
             
             
             
             
             
             
             
           
         
             
               TABLE 5e 
             
             
                 
             
             
                 
               Connected 
                 
                 
                 
                 
                 
                 
                 
                 
             
             
                 
               to: 
             
             
                 
               Phi1 
               Phi2 
               Phi3 
               Phi4 
               Phi5 
               Phi6 
               Phi7 
               Phi8 
               By 
             
             
               Switch 
               (Charge) 
               (Dump) 
               (Charge) 
               (Dump) 
               (Charge) 
               (Dump) 
               (Charge) 
               (Dump) 
               Clock: 
             
             
                 
             
           
           
             
               110a 
               Vmid2+ 
                 
               Vmid2+ 
                 
               Vmid2+ 
                 
               Vmid2+ 
                 
               CK1 
             
             
                 
                 
               501a 
                 
               501a 
                 
               501a 
                 
               501a 
               CK2 
             
             
               110b 
               Vmid2− 
                 
               Vmid2− 
                 
               Vmid2− 
                 
               Vmid2− 
                 
               CK1 
             
             
                 
                 
               501b 
                 
               501b 
                 
               501b 
                 
               501b 
               CK2 
             
             
               108a 
               VP+/ 
                 
               VP+/ 
                 
               VP+/ 
                 
               VP+/ 
                 
               CK1A 
             
             
                 
               VN+ 
                 
               VN+ 
                 
               VN+ 
                 
               VN+ 
                 
               CK1B 
             
             
                 
                 
               502a 
                 
               502a 
                 
               502a 
                 
               502a 
               CK2 
             
             
               108b 
               VN−/ 
                 
               VN−/ 
                 
               VN−/ 
                 
               VN−/ 
                 
               CK1A 
             
             
                 
               VP− 
                 
               VP− 
                 
               VP− 
                 
               VP− 
                 
               CK1B 
             
             
                 
                 
               502b 
                 
               502b 
                 
               502b 
                 
               502b 
               CK2 
             
             
               501a 
               Cf+ 
               Cf+ 
               Cf+ 
               Cf+ 
                 
                 
                 
                 
               CHCK1 
             
             
                 
                 
                 
                 
                 
               Cf− 
               Cf− 
               Cf− 
               Cf− 
               CHCK2 
             
             
               501b 
               Cf− 
               Cf− 
               Cf− 
               Cf− 
                 
                 
                 
                 
               CHCK1 
             
             
                 
                 
                 
                 
                 
               Cf+ 
               Cf+ 
               Cf+ 
               Cf+ 
               CHCK2 
             
             
               502a 
               Cf+ 
               Cf+ 
               Cf+ 
               Cf+ 
                 
                 
                 
                 
               CHCK1 
             
             
                 
                 
                 
                 
                 
               Cf− 
               Cf− 
               Cf− 
               Cf− 
               CHCK2 
             
             
               502b 
               Cf− 
               Cf− 
               Cf− 
               Cf− 
                 
                 
                 
                 
               CHCK1 
             
             
                 
                 
                 
                 
                 
               Cf+ 
               Cf+ 
               Cf+ 
               Cf+ 
               CHCK2 
             
             
                 
             
           
        
       
     
   
     FIG. 5   c  shows a timing diagram for the circuit of  FIG. 5   b , in particular CKIN  560 , DIN  562  (1110001110 . . . ), CK  1564 , CK  2566 , CK 1 A  568   a , CK 1 B  568   b , CHCK  570 , CHCK 1   572 , CHCK 2   574 . Note that the senses of CK 1 A, CK 1 B are flipped according to CHCK. The desired underlaps depend on logic speed and loading for a particular technology and circuit design. 
     FIG. 6  shows a functionally equivalent circuit  600 , that operates in essentially the same way, but combines switches  110   a  and  501   a  into switch  601   a ,  108   a  and  502   a  into  602   a ,  110   b  and  501   b  into  601   b , and  108   b  and  502   b  into switch  602   b . This gives a circuit with fewer switches, albeit more complex ones. The circuit is designed for use with a modified clocking scheme as defined by Table 6 below. 
   
     
       
             
           
             
             
             
             
             
             
             
             
             
           
         
             
               TABLE 6 
             
           
           
             
                 
             
             
               Switch positions versus clock phase for an 
             
             
               8-phase clocking scheme for the simplified DAC circuit of FIG. 6 
             
           
        
         
             
                 
               Connected 
                 
                 
                 
                 
                 
                 
                 
             
             
                 
               to: 
             
             
                 
               Phi1 
               Phi2 
               Phi3 
               Phi4 
               Phi5 
               Phi6 
               Phi7 
               Phi8 
             
             
               Switch 
               (Charge) 
               (Dump) 
               (Charge) 
               (Dump) 
               (Charge) 
               (Dump) 
               (Charge) 
               (Dump) 
             
             
                 
             
             
               601a 
               Vmid2+ 
               Cf+ 
               Vmid2+ 
               Cf+ 
               Vmid2+ 
               Cf− 
               Vmid2+ 
               Cf− 
             
             
               601b 
               Vmid2− 
               Cf− 
               Vmid2− 
               Cf− 
               Vmid2− 
               Cf+ 
               Vmid2− 
               Cf+ 
             
             
               602a 
               VP+/VN+ 
               Cf+ 
               VP+/VN+ 
               Cf+ 
               VN+/VP+ 
               Cf− 
               VN+/VP+ 
               Cf− 
             
             
               602b 
               VN−/VP− 
               Cf− 
               VN−/VP− 
               Cf− 
               VP−/VN− 
               Cf+ 
               VP−/VN− 
               Cf+ 
             
             
                 
             
           
        
       
     
   
   In the circuits of  FIGS. 5 and 6  it is the switched capacitor which can be regarded as being “chopped” i.e. with connections alternately swapped with the rest of the circuit. 
     FIG. 7  shows a circuit  700  where both the op amp and the switched capacitor are chopped. As regards the loading of the references, switches  701   a ,  702   a ,  701   b , and  702   b  serve the function of switches  601   a ,  602   a ,  601   b  and  602   b  of  FIG. 6  respectively. However chopping the op amp connections gives advantages (as previously discussed with reference to prior art  FIG. 4 ) in terms of rejection of low-frequency modulation of effective input offset voltages, i.e. of flicker noise or power supply coupling, and accomplishes this with no extra switches as compared with the arrangement of  FIG. 5 . 
   Table 7, below, shows a clocking scheme for the DAC  700  of  FIG. 7 . 
   
     
       
             
           
             
             
             
             
             
             
             
             
             
           
         
             
               TABLE 7 
             
           
           
             
                 
             
             
               Switch positions versus clock phase for an 
             
             
               8-phase clocking scheme for the choppered op amp circuit of FIG. 7 
             
           
        
         
             
                 
               Connected 
                 
                 
                 
                 
                 
                 
                 
             
             
                 
               to: 
             
             
                 
               Phi1 
               Phi2 
               Phi3 
               Phi4 
               Phi5 
               Phi6 
               Phi7 
               Phi8 
             
             
               Switch 
               (Charge) 
               (Dump) 
               (Charge) 
               (Dump) 
               (Charge) 
               (Dump) 
               (Charge) 
               (Dump) 
             
             
                 
             
             
               110a 
               Vmid2+ 
               701a 
               Vmid2+ 
               701a 
               Vmid2+ 
               701a 
               Vmid2+ 
               701a 
             
             
               110b 
               Vmid2− 
               701b 
               Vmid2− 
               701b 
               Vmid2− 
               701b 
               Vmid2− 
               701b 
             
             
               108a 
               VP+/VN+ 
               702a 
               VP+/VN+ 
               702a 
               VN+/VP+ 
               702a 
               VN+/VP+ 
               702a 
             
             
               108b 
               VN−/VP− 
               702b 
               VN−/VP− 
               702b 
               VP−/VN− 
               702b 
               VP−/VN− 
               702b 
             
             
               701a 
               Cf+ 
               Cf+ 
               Cf+ 
               Cf+ 
               Cf− 
               Cf− 
               Cf− 
               Cf− 
             
             
               701b 
               Cf− 
               Cf− 
               Cf− 
               Cf− 
               Cf+ 
               Cf+ 
               Cf+ 
               Cf+ 
             
             
               702a 
               Cf+ 
               Cf+ 
               Cf+ 
               Cf+ 
               Cf− 
               Cf− 
               Cf− 
               Cf− 
             
             
               702b 
               Cf− 
               Cf− 
               Cf− 
               Cf− 
               Cf+ 
               Cf+ 
               Cf+ 
               Cf+ 
             
             
                 
             
           
        
       
     
   
   Each of the circuits of  FIGS. 5 ,  6 ,  7  can be readily extended to multi-bit DACs, as shown by way of example in  FIG. 8 . Broadly speaking DAC  800  of  FIG. 8  represents a modification to the DAC  700  of  FIG. 7 , in a similar manner to that in which DAC  300  of  FIG. 3  represents a modification to DAC  200  of  FIG. 2 . 
   Table 8, below, shows a clocking scheme for the DAC  800  of  FIG. 8 . 
   
     
       
             
           
             
             
             
             
             
             
             
             
             
           
         
             
               TABLE 8 
             
           
           
             
                 
             
             
               Switch positions versus clock phase for an 8-phase clocking 
             
             
               scheme for the op amp choppered, multi-bit DAC circuit of FIG. 8 
             
           
        
         
             
                 
               Connected 
               to 
                 
                 
                 
                 
                 
                 
             
             
                 
               Phi1 
               Phi2 
               Phi3 
               Phi4 
               Phi5 
               Phi6 
               Phi7 
               Phi8 
             
             
               Switch 
               (Charge) 
               (Dump) 
               (Charge) 
               (Dump) 
               (Charge) 
               (Dump) 
               (Charge) 
               (Dump) 
             
             
                 
             
             
               110a 
               Vmid2+ 
               701a 
               Vmid2+ 
               701a 
               Vmid2+ 
               701a 
               Vmid2+ 
               701a 
             
             
               110b 
               Vmid2− 
               701b 
               Vmid2− 
               701b 
               Vmid2− 
               701b 
               Vmid2− 
               701b 
             
             
               108a 
               VP+/VN+ 
               702a 
               VP+/VN+ 
               702a 
               VN+/VP+ 
               702a 
               VN+/VP+ 
               702a 
             
             
               108b 
               VN−/VP− 
               702b 
               VN−/VP− 
               702b 
               VP−/VN− 
               702b 
               VP−/VN− 
               702b 
             
             
               110aa 
               Vmid2+ 
               701a 
               Vmid2+ 
               701a 
               Vmid2+ 
               701a 
               Vmid2+ 
               701a 
             
             
               110ba 
               Vmid2− 
               701b 
               Vmid2− 
               701b 
               Vmid2− 
               701b 
               Vmid2− 
               701b 
             
             
               108aa 
               VP+/VN+ 
               702a 
               VP+/VN+ 
               702a 
               VN+/VP+ 
               702a 
               VN+/VP+ 
               702a 
             
             
               108ba 
               VN−/VP− 
               702b 
               VN−/VP− 
               702b 
               VP−/VN− 
               702b 
               VP−/VN− 
               702b 
             
             
               . . . 
             
             
               801a 
               Cf+ 
               Cf+ 
               Cf+ 
               Cf+ 
               Cf− 
               Cf− 
               Cf− 
               Cf− 
             
             
               801b 
               Cf− 
               Cf− 
               Cf− 
               Cf− 
               Cf+ 
               Cf+ 
               Cf+ 
               Cf+ 
             
             
               802a 
               Cf+ 
               Cf+ 
               Cf+ 
               Cf+ 
               Cf− 
               Cf− 
               Cf− 
               Cf− 
             
             
               802b 
               Cf− 
               Cf− 
               Cf− 
               Cf− 
               Cf+ 
               Cf+ 
               Cf+ 
               Cf+ 
             
             
                 
             
           
        
       
     
   
   Although  FIG. 8  shows just two additional capacitors  106   aa,bb  and two corresponding additional pairs of switches  108   aa,bb ,  110   aa,bb  for each circuit  800   a,b  (for simplicity), in practice a plurality of additional capacitors may be provided for each differential signal processing circuit portion. Thus, in effect, the switched capacitors C 2  of  FIG. 6  may be replaced by an array of capacitors. The capacitors in such arrays may or may not be binary weighted. In one embodiment the LSB capacitors are binary weighted, but the MSB capacitors are equally weighted, and used in a random manner to decrease the effects of mismatch. Clock generators for the clocking schemes of Tables 6, 7 and 8 above may be constructed along similar lines to the example clock generator circuit described with reference to  FIG. 5   b.    
   As previously mentioned, there are often many capacitors in the banks for a multi-bit coder, for example configured as a binary-weighted array. In this case, the V P /V N  switching control signals to the large capacitors in the array often change only slowly, following an approximation to the output signal, and only the “LSB” (least significant bit) capacitors show much high-frequency switching activity. In this case it is therefore reasonable to assume that the drive to the biggest capacitors in each bank will be constant over several clock cycles. In such a case the load on V P  due to the largest capacitors should average out to be signal independent and should show little or no frequency-shifted quantisation noise tones. The smaller capacitors will have more high-frequency activity, so these may exhibit such tones but, since they are smaller, the resulting baseband components will also be small. This small amount of high-frequency energy on the V P  and V N  reference inputs is relatively easy to decouple. 
   The above analysis only deals with the effect of averaged m, corresponding to the audio frequency components of the applied delta-sigma input. However, delta-sigma techniques do not remove quantisation noise, but only move it up to higher frequencies. The chopper techniques will frequency-shift any components of charging requirements near to f s /4 down to audio-frequency, giving rise to baseband noise, rather than distortion or cross-talk. An approximate analysis to show this is not a significant problem is as follows. 
   The total quantisation noise for a one-bit modulator small signal is that of a square wave with amplitude equal to the peak audio signal, i.e. +3 dB above the largest sine wave possible (ignoring a small correction due to the practical maximum modulation index being sub-unity). For a well-designed high order modulator, the quantisation noise above the audio bandwidth will be almost flat. This means that the quantisation noise power within an audio bandwidth around say f s /4 will be of the order of that of a +3 dB signal divided by the oversampling ratio, say 64 or 18 dB. The chopper techniques will frequency-shift such f s /4 components of charging requirements down to audio-frequency. Thus the consequent Vref currents, instead of being those due to say a 0 dB sine wave, will be similar to those which would be caused by trying to output a baseband noise signal whose power is only 15 dB down from the 0 dB sine wave, reducing the benefits of the technique. However, for multibit operation, the spectral density of the noise is already suppressed by typically 2 N  where N is the number of capacitors in the binary array, say 5, giving 30 dB less quantisation energy at f s /4. By comparison multibit operation does not make much difference to the signal-dependent load current in a conventional modulator. So overall (with this example) one could expect 45 dB improvement in audio-band V P  load current variation relative to conventional multibit modulators. This supports the contention that this quantisation noise aliasing effect is not a significant limit on performance. 
   Strictly speaking the best load averaging will only occur for “random” spectra of the V P  delta-sigma control signals. For example, if the delta-sigma control signals were to have tones close to f s /4, these would appear in the V P  load current, frequency shifted by f s /4 into the low-frequency baseband. For well-designed high-order delta-sigma modulators, such tones are not an issue, but were this to become an issue in future high-performance systems, to reduce the possibility of this effect the “chopping” may be randomised, for example by alternating the switching of each C 2  to the positive or negative halves of the differential circuit according to a pseudo-random sequence generated by a pseudo-random sequence generator. 
   The skilled person will recognise that many variations of the above-described circuits are possible. For example the above-described differential DAC circuits are illustrated using a pair of operational amplifiers  102   a,b  but the skilled person will recognise that this pair of operational amplifiers may be replaced by a single differential-input, differential-output amplifier. 
   Although the DAC circuits have been described in the general context of delta-sigma digital control techniques, applications of the circuits are not limited to schemes in which the switching control waveforms are generated by such techniques. For example other digital filter-derived techniques or PWM (pulse width modulation) could be employed or appropriate pulse trains could be retrieved from storage, for example for digital voice or other synthesis. 
   The skilled person will further recognise that the above-described DAC circuits may be incorporated into other systems. For example one or more of the above-described DAC circuits may be incorporated within a switched-capacitor delta-sigma analogue-to-digital converter, in one or more feedback elements. For example, the skilled person will understand that a delta-sigma analogue-to-digital converter may be constructed by adding, for example, an integrator and a digital filter to one of the above DAC circuits. 
   No doubt many other effective alternatives will occur to the skilled person and it would be understood that the invention is not limited to the described embodiments and encompasses modifications apparent to those skilled in the art lying within the spirit and scope of the claims appended hereto.