Abstract:
One embodiment of the invention provides a semiconductor memory apparatus comprising: a multiplicity of memory cells which are arranged in the manner of a matrix at least in regions, a multiplicity of address contacts for receiving a row address and/or column address for at least one memory cell, at least one address decoder for decoding the row and/or column addresses, and a descrambling device which is arranged in the electrical signal path between the address contacts and the address decoder. The descrambling device comprises address inputs for accepting input address bits of an input address which are received via the address contacts and address outputs for outputting output address bits of an output address to the address decoder. In a descrambling mode, the descrambling device is designed to allocate an output address bit explicitly to each input address bit of a received, scrambled row and/or column address such that the output address is the same as the unscrambled address. The descrambling device further comprises, for each output address bit, an allocation device for allocating the output address bit to a corresponding input address bit. The allocation devices of all output address bits may have the same design.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims foreign priority benefits under 35 U.S.C. §119 to co-pending German patent application number DE 10 2004 009 692.9-55, filed 27 Feb. 2004. This related patent application is herein incorporated by reference in its entirety.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a semiconductor memory apparatus.  
         [0004]     2. Description of the Related Art  
         [0005]     When a dynamic random access memory (DRAM) is stacked with or onto another electronic component, the apparatuses connected in this manner generally share the same address bus and the same data bus. Generally, the address bits and the data bits can be scrambled or renamed or their order can be altered to adapt the data buses in a simple manner. By way of example, the individual bits of a row address or of a column address in a DRAM can be scrambled or interchanged with one another as desired or at random to simplify or permit the layout of the redistribution layer or the bonding. At the system level, the scrambling performed has no influence. When transmitting particular commands, however, it is necessary for the actual address produced by the processor or controller to be known in the semiconductor memory apparatus. The transmitted address bits therefore need to be “unscrambled” again.  
         [0006]     It is known practice to provide a processor with processing in which, for particular commands or command sequences, the individual bits in this command sequence are present in a semiconductor memory apparatus in the actual arrangement or order produced by the processor. The multiplicity of possible semiconductor memory apparatuses which can be used with a processor means that it is a very complex matter to provide a suitable implementation for the possible semiconductor memory apparatuses in the processor.  
         [0007]     Therefore, there is a need to provide a semiconductor memory apparatus which provides a simple way of descrambling or unscrambling received bits in a command sequence.  
       SUMMARY OF THE INVENTION  
       [0008]     One embodiment of the invention provides a semiconductor memory apparatus, comprising: 
        a multiplicity of memory cells which are arranged in the manner of a matrix at least in regions;     a multiplicity of address contacts for receiving a row address and/or column address for at least one memory cell;     at least one address decoder for decoding the row and/or column addresses; and     a descrambling device which 
            is arranged in the electrical signal path between the address contacts and the address decoder,     comprises address inputs for accepting input address bits of an input address which are received via the address contacts and address outputs for outputting output address bits of an output address to the address decoder, and     is designed so as, in a descrambling mode, to allocate an output address bit explicitly to each input address bit of a received, scrambled row and/or column address such that the output address is the same as the unscrambled address,    
               
 
         [0016]     wherein the descrambling device comprises, for each output address bit, an allocation device for allocating or connecting the output address bit to a corresponding input address bit, wherein the allocation devices of essentially all output address bits are of essentially the same design.  
         [0017]     In particular, the descrambling device is designed such that, in the descrambling mode, each input address bit is explicitly allocated an output address bit such that the output address is the same as the address which is output by a processor device.  
         [0018]     Address bits, in particular the individual positions in an address, may be received in parallel via the address inputs of a semiconductor memory apparatus.  
         [0019]     A scrambled address is, in particular, an address in which the order or arrangement of the address bits, which may be transmitted in parallel, has been altered. In a scrambled address, the arrangement, in particular, of address bits, which may be transmitted in parallel, with respect to one another is different than an arrangement of such address bits as those produced by a processor device, for example. An unscrambled or descrambled address is, in particular, an address in which the arrangement or order of the parallel-transmitted bits with respect to one another is the same as the arrangement or order of the address bits which have been produced by a processor device. An unscrambled address therefore corresponds to an address before it is subjected to a scrambling operation.  
         [0020]     The allocation of input address bits to output address bits and vice versa means, in particular, that the position of an address bit in an input address is assigned to the same or to a different position in the output address according to a predetermined descrambling pattern.  
         [0021]     The descrambling device may also have a normal operation mode in which the received address bits are essentially subjected to no processing and are “looped” through the descrambling device. In the descrambling device&#39;s normal operating mode, the output address bits thus correspond essentially to the input address bits.  
         [0022]     The number of input address bits may be the same as the number of output address bits. The number of allocation devices may be the same as the number of bits in an address which is to be processed.  
         [0023]     In one embodiment, all of the allocation devices are of the same design when the semiconductor memory apparatus is fabricated. The descrambling device can be matched to the respective processor device or to the respective transmission bus, which the semiconductor memory apparatus uses for communication, at a later time. By way of example, such matching can be performed during a test on the semiconductor memory apparatus. In particular, this may involve stipulating the respective descrambling method or stipulating the allocation of the input address bits to the output address bits. It is thus advantageously possible to simplify the fabrication method for the semiconductor memory apparatus, since it is not necessary to provide a particular semiconductor memory apparatus for each different scrambling operation.  
         [0024]     The allocation devices each may have a signal connection to an address output and to all address inputs. Furthermore, the allocation devices also each may comprise a selection device for selecting an input address bit which needs to be allocated to the respective output address bit.  
         [0025]     Thus, it is a simple matter to produce an association between an output address bit and an input address bit. In particular, the form of the descrambling device allows such an allocation to be made at a later time than the fabrication time.  
         [0026]     In one embodiment, each selection device comprises a number of outputs which corresponds to the number of bits or positions in the address, a respective output being associated with an input address bit, and the selection devices are in a form such that, during operation, a predetermined selection signal is transmitted only via that output which is associated with the input address bit which needs to be allocated to the respective output address bit.  
         [0027]     The 1:1 association between the outputs of the selection device and the input address bits makes it a simple matter to select that input address bit which needs to be allocated to the respective output address bit. Those outputs which are associated with input address bits that do not need to be allocated to the respective output address bit may be utilized to transmit a signal which is the logic complement of the predetermined selection signal.  
         [0028]     The selection device may be also in a form such that the predetermined selection signal is transmitted just via a single output. Furthermore, the multiplicity of selection devices provided in a descrambling device may be in a form such that they are each in different forms than one another in the standby state.  
         [0029]     In one embodiment, the selection device comprises a number of fuses which corresponds to the number of bits in the address, a respective fuse having a signal connection to an output on the selection device.  
         [0030]     A respective fuse is thus associated with an input address bit. Particular forms for the respective fuses makes it a simple matter to select that input address bit which needs to be allocated to the respective output address bit. To this end, preferably during a test on the semiconductor memory apparatus, that fuse is destroyed which is associated with the input address bit which needs to be allocated to the output address bit. Destroying the fuse makes it possible for the allocated output of the selection device to produce, during operation of the semiconductor memory apparatus, a signal which is different than (e.g., complementary to) the signal which is at the other outputs of the selection device.  
         [0031]     Alternatively, the selection device comprises a number of fuses to provide binary coding for the number of bits in an address and a selection decoder which has a signal connection to the fuses and which has a number of outputs corresponding to the number of bits in the address. The outputs of the selection decoder have a signal connection to the outputs of the selection device, and the selection decoder is in a form such that the output which corresponds to the input address bit that needs to be allocated to the respective output address bit is used to output a selection signal on the basis of the signals which are applied to the fuses.  
         [0032]     In particular, the number of fuses corresponds to the base  2  logarithm (rounded up to an integer) of the number of bits in an address. Expressed another way, the number of fuses corresponds to the value (respectively rounded, up to an integer) of ld(n) or log 2 (n), where n corresponds to the number of bits in an address. Preferably, exactly the same number of fuses is used as is needed for providing binary coding for the number of address bits.  
         [0033]     Hence, the binary coding by the fuses and the subsequent decoding by the selection decoder can be used to select one of the input address bits which needs to be allocated to the output address bit. In particular, the selection decoder uses just one output to output the predetermined selection signal. The other outputs are then used to output a signal which is the complement thereof.  
         [0034]     To this end, preferably during a test on the semiconductor memory apparatus, none, one or a plurality of the fuses is/are destroyed to produce the binary coding.  
         [0035]     The allocation devices each may also comprise: an initial circuit or input circuit which has a signal connection at least to the first input address bit, a final circuit or output circuit which has a signal connection at least to the last input address bit, and at least one central circuit, with each central circuit having a signal connection at least to one of the remaining or central input address bits, and all of the central circuits being of essentially the same design.  
         [0036]     The first input address bit may be the input address bit which is transmitted via the first address contact from the address contacts, which may be consecutively numbered in ascending order. The last input address bit may be the input address bit which is transmitted via the last address contact. The remaining or central input address bits are those input address bits which are received neither via the first nor via the last address contact.  
         [0037]     The allocation devices are thus constructed from three, possibly multiple-instance circuits. The input circuit and the output circuit are each in separate form. The form of the initial circuit, final circuit and of the central circuits is independent of the number of bits in an address. In particular, just the number of central circuits varies with the number of bits in an address. In particular, a respective central circuit is provided per central input address bit. In this context, the central circuits are all in the same form.  
         [0038]     In one embodiment, the initial circuit, the final circuit and the central circuit(s) each have a signal connection to an output on the selection device.  
         [0039]     Furthermore, the initial circuit, the central circuit(s) and the final circuit may have a signal connection to one another.  
         [0040]     Moreover, a first central circuit may have a signal connection to the signal output of the initial circuit; the subsequent central circuits have a signal connection to the signal output of the respective preceding central circuit; the final circuit has a signal connection to the signal output of the last central circuit; and the signal output of the final circuit has a signal connection to the respective address output of the descrambling device.  
         [0041]     The initial circuit, the final circuit and the central circuits perform logic operations, with the result of a preceding logic operation in one of the circuits being used as input for the logic operation in a subsequent circuit. During operation of the semiconductor memory apparatus, the signal output of the final circuit may produce the respective input address bit associated with the output address bit.  
         [0042]     The semiconductor memory apparatus may also comprise a control input for accepting a control signal which can be used to select the descrambling mode.  
         [0043]     By transmitting a control signal to the semiconductor memory apparatus, it is thus possible to stipulate whether the semiconductor memory apparatus needs to descramble the received address bits or whether the address bits can be processed further as received.  
         [0044]     The descrambling device may be in a form such that the descrambling mode is used when a configuration command or a configuration command sequence is transmitted to the semiconductor memory apparatus.  
         [0045]     In one embodiment, the configuration command is a mode register set command (or MRS command) which can be used to determine, by way of example, the operating mode, the burst type, the burst length, the CAS latency, the type of operation, etc., of the semiconductor memory apparatus. The configuration command can be used to program the semiconductor memory apparatus. The configuration command may be sent at least at the start of operation of the semiconductor memory apparatus. Transmission of the configuration command also involves the use of the address bits or address contacts of a semiconductor memory apparatus. However, in contrast to read or write commands, where it makes essentially no difference to which memory cell data are written or whether the address of this memory cell is scrambled, it is of great importance for configuration commands that the information which the address bits contains is present in the semiconductor memory apparatus in unscrambled form, i.e., corresponds to that arrangement which has been produced by the processor device.  
         [0046]     In one embodiment, the descrambling device is designed as part of the address decoder. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0047]     So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.  
         [0048]      FIG. 1  shows a highly schematic view of a semiconductor memory apparatus according to one embodiment of the present invention;  
         [0049]      FIG. 2  shows a highly schematic view of a descrambling device in the semiconductor memory apparatus shown in  FIG. 1 ;  
         [0050]      FIG. 3  shows a schematic view of a descrambling device according to a first embodiment of the present invention;  
         [0051]      FIG. 4  shows a schematic view of an allocation device in the descrambling device shown in  FIG. 3 ;  
         [0052]      FIG. 5  shows a schematic view of a first exemplary form of an allocation device according to the first embodiment of the present invention;  
         [0053]      FIG. 6  shows a schematic view of a second exemplary form of an allocation device according to the first embodiment of the present invention;  
         [0054]      FIG. 7  shows a schematic view of a descrambling device according to a second embodiment of the present invention;  
         [0055]      FIG. 8  shows a schematic view of a selection device which is used in the descrambling device shown in  FIG. 7 ; and  
         [0056]      FIG. 9  shows a schematic view of a selection decoder which is used in the selection device shown in  FIG. 8 . 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0057]     First, the design of a semiconductor memory apparatus  10  according to one embodiment of the present invention is described with reference to  FIGS. 1 and 2 .  
         [0058]     The semiconductor memory apparatus  10  comprises a multiplicity of memory cells  12  which are arranged in the manner of a matrix and which can be addressed via word lines WL and bit lines BL. The semiconductor memory apparatus  10  also comprises an address decoder  14  which decodes a received row address or column address and activates the corresponding word line WL or bit line BL. In the embodiment shown, just one address decoder  14  for the row addresses is shown, for reasons of clarity. A corresponding address decoder may also be provided for decoding the column addresses, however.  
         [0059]     In addition, the semiconductor memory apparatus  10  contains a descrambling device  16 , as illustrated in  FIG. 2 . The descrambling device  16  comprises a multiplicity of address inputs IN 0  . . . IN n−1  and a corresponding number of address outputs OUT 0  . . . OUT n−1 . The address inputs IN 0  . . . IN n−1  can be used for inputting input address bits a 0  . . . a n−1  of an address which has been input into the semiconductor memory apparatus  10 , e.g., a row or column address, into the descrambling device  16 . The address outputs OUT 0  . . . OUT n−1  are used for outputting output address bits A 0  . . . A n−1 . The descrambling device  16  is in a form such that, during operation of the semiconductor memory apparatus  10 , for example, when the latter is in a descrambling mode, an output address bit A 0  . . . A n−1  may be allocated explicitly to each input address bit a 0  . . . a n−1  according to a prescribed pattern (described in detail later). The number of address inputs IN 0  . . . IN n−1 , and hence the number of input address bits a 0  . . . a n−1  is equal to the number of address outputs OUT 0  . . . OUT n−1 , and hence to the number of output address bits A 0  . . . A n−1 .  
         [0060]     In addition, the semiconductor memory apparatus  10  comprises address contacts AK 0  . . . AK n−1  which can be used to input addresses into the semiconductor memory apparatus  10 . The address contacts AK 0  . . . AK n−1  have a signal connection to the address inputs IN 0  . . . IN n−1  of the descrambling device  16 . Furthermore, the address outputs OUT 0  . . . OUT n−1  of the descrambling device  16  each have a signal connection to inputs on the address decoder  14 .  
         [0061]     A descrambling device  16  according to a first embodiment of the present invention is described below with reference to  FIGS. 3-6 . In this context,  FIG. 3  shows a schematic view of a descrambling device according to a first embodiment of the present invention.  FIG. 4  shows a schematic view of an allocation device in the descrambling device shown in  FIG. 3 .  FIG. 5  shows a schematic view of a first exemplary form of an allocation device according to the first embodiment of the present invention.  FIG. 6  shows a schematic view of a second exemplary form of an allocation device according to the first embodiment of the present invention.  
         [0062]     The descrambling device  16  according to the first embodiment of the present invention comprises a multiplicity of allocation devices  18 . In the embodiment shown, one allocation device  18  is provided for each bit or for each position a 0  . . . a n−1  in a parallel-transmitted input address, for example. In the embodiment shown, an address has n=16 bits. There are thus 16 allocation devices  18 .  
         [0063]     An allocation device  18  is used to allocate an input address bit a i  explicitly to an output address bit A j . This means, in particular, that an input address bit a i , which is at the position i in the input address, is allocated to an output address bit A j , and is thus at the position j in the output address.  
         [0064]      FIG. 4  shows a detailed view of an allocation device  18  for allocating an input address a i  to an output address bit A j . The allocation device  18  comprises an initial circuit  20 , a plurality of central circuits  22  and a final circuit  24 .  
         [0065]     In addition, the allocation device  18  comprises a selection device  26  which comprises a multiplicity of outputs C 0j  . . . C 15j . In the allocation device  18  shown in  FIG. 4 , according to the first embodiment of the present invention, the selection device  26  comprises a multiplicity of fuses F 0j  . . . F 15j . In this context, each fuse F 0j  . . . F 15j  has a signal connection to an output C 0j  . . . C 15j . The outputs C 0j  . . . C 15j  are respectively used to transmit selection signals k 0j  . . . k 15j .  
         [0066]     A respective output C 0j  . . . C 15j  on the selection device  26  has a signal connection to one of the circuits  20 ,  22 ,  24 . In particular, the first output C 0j  has a signal connection to the initial circuit  20 ; the central outputs C 1j  . . . C 14j  each have a signal connection to a central circuit  22 ; and the last output C 15j  has a signal connection to the final circuit  24 .  
         [0067]     In addition, the initial circuit  20  has a signal connection to the first input address bit a 0 ; the central circuits  22  each have a signal connection to the central input address bits a 1  . . . a 14 ; and the final circuit  24  has a signal connection to the last input address bit a 15 . Furthermore, the final circuit  24  has a signal connection to an address output OUT j  which is used to output an output address bit A j .  
         [0068]     The above-described basic design of the allocation device  18  may be the same for all of the allocation devices  18  shown in  FIG. 3 . Furthermore, all of the central circuits  22  may have the same design.  
         [0069]     In order to allow descrambling or unscrambling, just one fuse F ij  of an allocation device  18  is respectively destroyed (e.g., burned by laser). Hence, that output C ij  of the allocation device  18  which has a signal connection to this destroyed fuse F ij  is used to output a selection signal k ij  which is the complement of the signal which is output via the other outputs. As a result, the respective input address bit a i  can be selected and allocated to the respective output address bit A j . The selected input address bit a i  is, in particular, that bit which is associated with the destroyed fuse F ij .  
         [0070]     In the arrangement shown in  FIG. 3 , a respective different fuse F ij  has been destroyed in each allocation device  18  shown. Hence, each output address bit A 0  . . . A 15  is allocated a different input address bit a 0  . . . a 15 . The signal or the output address bit A j  which is at an address output OUT j  can thus be represented using equation (1) below. 
 
 A   j   =k   0j   ·a   0   +k   ij   ·a   1   + . . . +k   ij   ·a   i   + . . . +k   (n−1)j   ·a   (n−1 )  Equation (1) 
 
         [0071]     In this context, k 0j  . . . k (n−1)j  corresponds to the respective signal which is transmitted via the respective output C 0j  . . . C (n−1)j  of the selection device. For each output address bit A j , precisely one k ij  assumes the logic value 1, whereas all other k assume the logic value 0. In this way, the output address bit A j  is allocated the input address bit a i .  
         [0072]      FIG. 5  shows a more detailed form of the allocation device  18  shown in the  FIG. 4 . For representation reasons, the present case provides an example having just three input address bits A 0  . . . A 2 .  
         [0073]     In this context, the initial circuit  20  comprises a NAND gate NAND IN , the first input address bit a 0  and the signal k 0j  being used as input for the gate NAND IN .  
         [0074]     The central circuit  22  comprises two NAND gates, i.e., NAND CEN1  and NAND CEN2 . The input of the gate NAND CEN1  has a signal connection to the central input address bit a 1  and to the signal k 1j . The input of the second gate NAND CEN2  has a signal connection to the output of the first gate NAND CEN1  and to the output of the gate NAND IN  of the initial circuit  20 . The output of the gate NAND CEN2  is logically inverted by means of a gate NOT.  
         [0075]     The final circuit  24  comprises two NAND gates NAND OUT1  and NAND OUT2 . The input of the gate NAND OUT1  has a signal connection to the last input address bit a 2  and to the signal k 2j . The inputs of the gate NAND OUT2  have a signal connection to the output of the first gate NAND OUT1  and to the signal from the central circuit  22 , which signal has been inverted by the gate NOT. The signal output of the gate NAND OUT2  then produces the output address bit A j .  
         [0076]     Depending on which of the fuses f 0j  . . . f 2j  has been destroyed and hence which respective signal k 0j  . . . k 2j  has the logic value 1, the gates in the initial circuit  20 , central circuit  22  and final circuit  24  switch such that the respective input address bit a i  associated with the destroyed fuse is at the output A j .  
         [0077]     This can be expressed by the equations (3.1) and (3.2) below.  
               A   j     =           a   0     ·     k     0   ⁢   j         +       a   1     ·     k     1   ⁢   j         +       a   2     ·     k     2   ⁢   j           =           (       a   0     ·     k     0   ⁢   j         )     _     ·       (       a   1     ·     k     1   ⁢   j         )     _     ·       (       a   2     ·     k     2   ⁢   j         )     _       _               Equation   ⁡     (   3.1   )                   A   j     =           a   0     ·     k     0   ⁢   j         +       a   1     ·     k     1   ⁢   j         +       a   2     ·     k     2   ⁢   j           =             (         (       a   0     ·     k     0   ⁢   j         )     _     ·       (       a   1     ·     k     1   ⁢   j         )     _       )     _     _     ·       (       a   2     ·     k     2   ⁢   j         )     _       _               Equation   ⁡     (   3.2   )               
 
         [0078]      FIG. 6  shows a further example of the allocation device  18  shown in  FIG. 5 . In this context, four address bits are provided. The allocation device  18  shown is of essentially the same design as the allocation device  18  shown in  FIG. 5 . The difference in this context is that two central circuits  22  are provided for the two central input address bits a 1  and a 2 . The two central circuits shown in  FIG. 6  may have the same design as the central circuit  22  shown in  FIG. 5 . For this reason, a detailed description thereof is omitted.  
         [0079]     As shown in  FIG. 6 , the signal which is on the output address bit A j  can be expressed using the equations (4.1) and (4.2).  
                 A   j     =           a   0     ·     k     0   ⁢   j         +       a   1     ·     k     1   ⁢   j         +       a   2     ·     k     2   ⁢   j         +       a   3     ·     k     3   ⁢           ⁢   j           =           (       a   0     ·     k     0   ⁢   j         )     _     ·       (       a   1     ·     k     1   ⁢   j         )     _     ·       (       a   2     ·     k     2   ⁢   j         )     _     ·       (       a   3     ·     k     3   ⁢   j         )     _       _         ⁢     
             Equation   ⁡     (   4.1   )                   A   j     =           a   0     ·     k     0   ⁢   j         +       a   1     ·     k     1   ⁢   j         +       a   2     ·     k     2   ⁢   j         +       a   3     ·     k     3   ⁢   j           =             [           (         (       a   0     ·     k     0   ⁢   j         )     _     ·       (       a   1     ·     k     1   ⁢   j         )     _       )     _     _     ·       (       a   2     ·     k     2   ⁢   j         )     _       ]     _     _     ·       (       a   3     ·     k     3   ⁢   j         )     _       _               Equation   ⁡     (   4.2   )               
 
         [0080]     In order to provide an allocation device  18  having 16 address bits as shown in  FIG. 4 , an appropriate number of central circuits  22  are interconnected as appropriate. In this context, the number of central circuits  22  used is two lower than the total number of address bits, or is equal to n-2, where n is the total number of address bits.  
         [0081]     In the embodiment described above, n fuses are needed for each allocation device  18 , and n allocation devices  18  are needed per descrambling device  16 . The total number of fuses required is thus n*n=n 2 .  
         [0082]     A second embodiment of a descrambling device  16  is described below with reference to  FIGS. 7-9 . In this context,  FIG. 7  shows a schematic view of a descrambling device according to a second embodiment of the present invention;  FIG. 8  shows a schematic view of a selection device which is used in the descrambling device shown in  FIG. 7 ; and  FIG. 9  shows a schematic view of a selection decoder which is used in the selection device shown in  FIG. 8 .  
         [0083]     The descrambling device  16  shown may have essentially the same design as the descrambling device  16  according to the first embodiment. However, the selection device is in a different form. For this reason, a detailed description of the elements which are common to the first and second embodiments is omitted below.  
         [0084]     Like the selection device  26  according to the first embodiment, the selection device  50  has a multiplicity of outputs C 0j  . . . C 15j . This is shown in  FIGS. 7 and 8  as a contact with an output bus K i0  bus.  
         [0085]     The selection device  50  comprises a plurality of fuses FB 0j  . . . FB 3j  which are used for providing binary coding for the number i of the input address bit A i . To this end, none, one or a plurality of the fuses FB 0j  . . . FB 3j  is/are destroyed. Depending on which of fuses FB 0j  . . . FB 3j  has/have been destroyed, a different coding is obtained.  
         [0086]     The number of fuses FB 0j  . . . FB 3j  used corresponds to the base  2  logarithm (rounded up to an integer) of the number of bits in an address. Expressed another way, the number of fuses corresponds to the value (respectively rounded up to an integer) of the ld(n) or log 2 (n), where n corresponds to the number of bits in an address. In one embodiment, exactly the same number of fuses are used as are required for providing binary coding for the number of address bits. In the embodiment shown, an address has 16 bits. Hence, ld(16)=4 fuses are required.  
         [0087]     In addition, the selection device  50  has a selection decoder  52  which has a signal connection to the fuses FB 0i  . . . FB 3i . In this context, the signals f 0i  . . . f 3i  are used as inputs for the selection decoder  52 . The selection decoder  52  takes the binary coding and determines that input address bit a i  which needs to be allocated to the respective output address bit A j .  
         [0088]     A selection decoder  52  (shown generally in the selection device  50  shown in  FIG. 8 ) is shown in detail in  FIG. 9 .  
         [0089]     In the logic circuit shown, all signals f 0j  . . . f 3j  are respectively supplied to NAND gates NAND 0j  . . . NAND 15 , with the signals f 0j  . . . f 3j  being inverted and not inverted in different combinations. In this context, a number of NAND gates NAND 0j  . . . NAND 15j  which corresponds to the number of address bits is provided. In other words, the input of each of the gates NAND 0j  . . . NAND 15j  shown respectively has all of the signals f 0j  . . . f 3j  applied to it, with the signals f 0j  . . . f 3j  not being inverted, being inverted at least in part or all being inverted. In particular, the form of the interconnection achieves all possible combinations of inverted and non-inverted signals.  
         [0090]     The output signals from the gates NAND 0j  . . . NAND 15j  are inverted. The resultant signal corresponds to the signals k 0j  . . . k 15j  in the first embodiment. The form shown for the circuit makes it possible to achieve a situation in which just a single signal case k 0j  . . . k 15j  assumes the logic value “1”. Using these signals k 0j  . . . k 15j , a respective input address bit a j  may be selected which needs to be allocated to the output address bit A j .  
         [0091]     In the second embodiment described above, Id(n)*n fuses are required. The advantageous form according to the second embodiment thus allows the number of fuses required to be reduced in comparison with the first embodiment.  
         [0092]     During fabrication of the semiconductor memory apparatus  10  described, the descrambling device  16  may be produced. The fuses may be “fused” or destroyed at a later time. In particular, it is advantageous if the fusing takes place while the semiconductor memory apparatus  10  is being tested. The form of the descrambling device  16  in the semiconductor memory apparatus  10  allows the respective descrambling pattern required for a particular application to be produced in the descrambling device when the application of the semiconductor memory apparatus  10  is stipulated.  
         [0093]     Provision may also be made for the descrambling devices  16  described to contain a bypass (not shown) which may be used to bypass the circuit arrangements described. In addition, the semiconductor memory apparatus  10  may contain a control input (not shown) which may be used to receive a control signal. Such a control signal may be used to select various operating modes of the semiconductor memory apparatus  10  or of the descrambling devices  16 . In this context, at least one normal operating mode and a descrambling mode may be provided. During the descrambling mode, the descrambling device  16  is active, i.e., appropriate descrambling is performed. During the normal operating mode, the bypass is active, and no descrambling takes place.  
         [0094]     In one embodiment, the descrambling mode is used when a configuration command or a configuration command sequence is transmitted to the semiconductor memory apparatus  10 . The configuration command may be a mode register set command (or MRS command). The MRS command may be used, in particular, to determine the burst length, the burst type, the CAS latency and a type of operation for the semiconductor memory apparatus  10 . In this context, address bits are also used to program or configure the semiconductor memory apparatus  10 .  
         [0095]     The MRS command is sent from the processor unit to the semiconductor memory apparatus  10  at least once at the start of operation of the circuit arrangement. Programming the semiconductor memory apparatus  10  using the MRS command is typically a slow application.  
         [0096]     The text above described the descrambling for address bits. However, it is likewise conceivable to provide appropriate descrambling for data bits.  
         [0097]     While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.