Abstract:
A method and a tool for quickly evaluating the circuit response of VLSI designs in the presence of parasitics assists in improving VLSI designs. Offending induced voltgages are quickly identified through a simple approximation procedure, and the circuit lines where such voltages are induced are marked for evaluation with tools that make an accurate assessment. When it is determined that these circuit lines do exceed predetermined thresholds, the circuit designer is alerted to the need to redesign the circuit or its layout. The tool disclosed considers each circuit line of the VLSI circuit, and with respect to each considered circuit line, computes an estimated peak voltage due to the parasitics. The computations are very simple, involving only a summation of terms, each of which involves a quotient of one RC product by a sum of two RC products.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to very large-scale integrated circuit (VLSI) design and, more particularly, to tools that assist in the design and creation of VLSI circuits. 
     Current designs of VLSIs include components that number in the millions. Obviously, when dealing with the design of such circuits it is necessary to employ automated tools in order to create, validate and improve the circuit designs and their layouts. Indeed, many tools are available in the art, and different tools cover different aspects of the VLSI circuit creation process, such as 
     tools that assist in creating the VLSI circuit design, 
     tools that prepare listings of elements and their connections, in preparations for other automated processes, 
     tools that analyze the design, 
     tools the simulate the circuit&#39;s operation, 
     tools that create the circuit layout, 
     tools that identify the parasitics circuit that corresponds to the circuit&#39;s design and layout, etc. 
     It is important to consider the circuit&#39;s parasitic capacitances and resistances because they degrade the circuit&#39;s performance and potentially can make the circuit fall outside its intended range of operation. An example of a tool which creates a circuit consisting of the parasitic elements of a given circuit (the “parasitics circuit”) is called “Clover,” which is marketed by the Design Automation Organization of Bell Labs, which is part of Lucent Technologies. Given a circuit design, “Clover” creates the parasitics circuit, expresses it in an established, standardized format, e.g., the “DSPF format , (where DSPF stands for Detailed Standards Parasitic Format), and makes it available for further analysis. Various prior art tools are available that analyze parasitics circuits, such as “SPICE,” which currently is a public domain program. 
     The problem with current tools for analyzing parasitics circuits is that they are too slow; primarily because they perform all of the necessary calculations, and the number of the required calculations is staggering. The challenge is to quickly evaluate the step response of an analyzed parasitics circuit in order to expedite the overall design process. 
     SUMMARY 
     This invention provides a method and a tool for quickly evaluating the impact of parasitics on the functionality of VLSI designs. It quickly identifies, through a simple approximation procedure, the circuit lines where signals are induced by the parasitic capacitances and resistances. When these approximations are in excess of a predetermined threshold, the circuit lines are marked for evaluation with tools that make a more accurate assessment, and if it is determined that these circuit lines do exceed the predetermined thresholds, the circuit designer is alerted to the need to redesign the circuit or its layout. 
     The tool disclosed herein considers each circuit line of the VLSI circuit, and with respect to each considered circuit line, computes an estimated peak voltage due to the parasitics. The computations are very simple, involving only a summation of terms, each of which involves a quotient of one resistor-capacitor (RC) product by a sum of two RC products. Consequently, the estimate of the peak induced signal on a circuit line is obtained quickly. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 illustrates a portion of a schematic diagram of a VLSI circuit; 
     FIG. 2 presents a portion of the parasitics circuit associated with the schematic diagram of FIG. 1; 
     FIG. 3 shows a block diagram of apparatus in conformance with the principles disclosed herein; and 
     FIG. 4 presents a fi chart of a process for quickly estimating the step response of parasitics circuits. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 presents an example of a VLSI layout schematic. It comprises gates A though G that drive circuit lines, and those lines are terminated at input terminals of gates H through N. It may be noted that the circuit lines of FIG. 1 run parallel to some circuit lines and perpendicular to other circuit lines. Since every circuit line has a) a resistance, b) capacitance to ground, and c) a coupling capacitance to many other lines, it is easy to envision the fact that there is another, hidden, circuit that is associated with the FIG. 1 circuit, which comprises those various resistances and capacitances. This disclosure refers to this circuit as the parasitics circuit. A portion of the parasitics circuit that is associated with the FIG. 1 circuit is shown in FIG.  2 . Specifically, FIG. 2 shows a portion of the parasitics circuit for the line driven by gates A and B. 
     It may be observed that the circuit line driven by gates A and B is represented in FIG. 2 by a plurality of resistances with interposed capacitances connected to ground at the junction of each pair of resistances. This is the classic RC representation of a wire. The number of resistances is arbitrary because, theoretically, there is an infinite number of these resistances, and the value of each one of these resistances is infinitesimally small. The wire resistances of FIG. 2 are designated by R i (ν), where v is the identity of the circuit line, and the total wire resistance for that line, R(ν), is the sum of the resistances. That is,                  R        (   v   )       =         R   d          (   v   )       +       ∑     i   =   1     n                       R   i          (   v   )             ,           (   1   )                                
     where R d  (ν) is the equivalent source resistance, and n is the number of the resistances that represent the circuit line. Similarly, with respect to the wire capacitance to ground,                  C        (   v   )       =       ∑     i   =   1     m                       C   i          (   v   )           ,           (   2   )                                
     where ν is the identity of the circuit line, C i (ν) is the value of the individual capacitances of the circuit line to ground, and m is the number of such capacitances. With respect to the other sets of capacitances, i.e., capacitances that couple to other circuit lines, the equation is similar. That is, the total capacitance between circuit line ν and circuit line j, C(v,j), is          ∑     i   =   1     k                       C   i          (     v   ,   j     )                              
     where k is the number of capacitances that participate in the coupling between circuit line ν and circuit line j. A total capacitance measure for circuit line v, is expressed by                    C   t          (   v   )       =       C        (   v   )       +       ∑     j   =   1     M                     C        (     v   ,   j     )             ,           (   3   )                                
     where M is the number of lines that have a measurable effect on circuit line ν. 
     In accordance with the approach disclosed herein, the estimated normalized peak voltage that is induced on circuit line ν (the “victim” circuit line) by circuit line j (an “aggressor” circuit line) conforms to the equation                    e   peak          (     v   ,   j     )       =         k1C        (     v   ,   j     )            R        (   v   )               k2C        (   v   )            R        (   v   )         +       k3C        (   j   )            R        (   j   )               ,           (   4   )                                
     where the factors k1, k2, and k3 are preselected constants. Finally, per force of the Superposition Theorem, the overall peak voltage is derived from                  e   peak          (   v   )       =       ∑     j   =   1     M                         e   peak          (     v   ,   j     )       .               (   5   )                                
     Currently, we set the values of k1, k2, and k3 to 1. However, other artisans may find other values to be beneficial. Also, equation (4) can be generalized to be a quotient of sums of RC constants, as long as the number of terms in the numerator is lower than in the denominator. 
     The VLSI design assistance that equation 5 can provide is embodied in a software tool that includes a data gathering module, a computation module, and an assessment module. The tool is most advantageously installed in a digital computer and, under direction of a controller, interacts with other tools to provide the desired quick layout enhancement benefits. 
     FIG. 3 presents a general block diagram of such a digital computer arrangement. In FIG. 3, CPU  100  has a keyboard  130 , a display  120 , and an associated a plotter  110  that is adapted to plot images of integrated circuit layouts. Typically, those images are lithographically reduced to create masks which are used in the actual manufacturing of integrated circuits. Also associated with CPU  100  is a memory  200  which stores a controller  300 , a representation of the integrated circuit&#39;s design and layout  210 , and a representation of parasitics circuit  220  which corresponds to representation  210 . In addition, memory  200  includes a number of tools that are employed in the creation of the integrated circuit layout and its image, under direction of controller  300 . Illustratively, memory  200  includes data entry tool  240 , parasitics circuit creation tool  230 , estimator tool  250 , response calculator tool  260 , layout modifier tool  270 , and display &amp; print tool  280 . 
     Data entry tool  240  can be any software module and associated hardware (such as a tape drive) that inserts data into memory  200  and thereby populates the memory portion devoted to circuit layout, i.e., memory segment  210 . An example of such a tool is DRACULA, marketed by Cadence Design System. 
     Parasitics circuit creation tool  230  creates a representation of that circuit created solely from the parasitic capacitances and resistances that are expected to be found in the circuit represented in memory segment  210 . As example of such a tool is “Clover” which, as indicated above, is a commercial tool. 
     Estimator tool  250  is a software module that, with assistance from controller  300 , carries out the equation 4 and 5 calculations disclosed above. 
     Response calculator tool  260  evaluates the response of the parasitics circuit, but unlike estimator tool  250 , it develops an accurate value for the expected response, as compared to a mere estimate. An example of such a tool is “SPICE”. 
     Layout modifier tool  270  modifies the layout of the circuit being designed, and thereby changes circuit representation  210 . The aim of tools  270  is to change the layout so as to reduce all voltages which are induced by the parasitic capacitances and resistances to a level below a preselected threshold. This tool may be simply a software module that displays circuit lines which contribute most of the induced voltages in those circuit lines where the induced voltage exceeds the above-mentioned threshold, e.g., on display  120 . The tool then allows the user to change the position of those lines, the orientation of those lines, or even to change the actual circuit architecture, e.g., via keyboard  130 ; all in an effort to reduce the parasitic coupling. 
     Display &amp; print tool  280  is a conventional utility that creates the image, or images which corresponds to the layout representation  210 . 
     FIG. 4 presents a flowchart of the process carried out, in accordance with the instant disclosure, under direction of controller  300 . Block  10  creates/modifies the design and layout of the integrated circuit under consideration. The creating can be done in the processor of FIG. 3 (with a tool that is not described), or it can be done elsewhere. The modification is done with tool  280 , as described below. The resultant circuit representation ( 210 ) is inserted by block  10  into memory  200 . Control then passes to block  11  which calls tool  230 , creates parasitics circuit  220 , and installs it in memory  200 . Estimator tool  250  is then activated, and control passes to block  12  where a victim circuit line is selected and an iterative process is initiated to develop an estimate of the induced voltage. 
     Block  13  selects an aggressor line, block  14  computes the estimated induced voltage due to the selected aggressor line (equation 4), and block  15  accumulates the estimated induced voltage. As long as aggressor lines remain that contribute more than an insignificant amount of induced voltage, e.g. within a certain physical distance from the victim line, block  16  returns control to block  13  to select another aggressor line. The result is that when block  16  passes control to block  17 , the accumulated contribution developed by block  15  corresponds to the estimated peak induced voltage of equation 5. 
     Block  17  compares the developed peak induced voltage to a preselected threshold. When it is determined that the threshold has been exceeded, block  18  adds the identity of the victim circuit line to a list. Otherwise, or after addition to the list is effected, control passes to block  19  which determines whether they may be other victim circuit lines that have not been considered. When that is the case, control passes to block  12 , where another victim line is selected. 
     When all circuit lines have been considered as victim circuit lines, control passes to block  20  where the circuit lines which are included in the list created by block  18  are considered. The induced voltage of those lines is again computed, but this time the computation is accurate rather than a mere estimation. This is done with tool  260 . When, following the calculations of tool  260 , it is determined that a modification of the integrated circuit layout is called for block  21  returns control to block  10  and with the aid of layout modifier tool  280  the layout is modified, and the process repeats. 
     Finally, when block  21  determines that no layout modifications are called for, control passes to block  22  where the image of the layout, in the format of a mask, for example, is created with tool  280  on display  120  or plotter  110 . 
     It should be understood that the above disclosed the principles of this invention but modifications from the illustrative embodiment can be readily made without departing from the spirit and scope of this invention. For example, different tools can be employed that generate different types of parasitics circuits, inductive parasitics can be accounted for, etc.