Abstract:
A semiconductor device for manufacturing a semiconductor memory cell includes the steps of: a) preparing an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conductive plugs; b) forming a supporting layer, made of carbon, on top of the active matrix and patterned into a predetermined configuration, thereby obtaining a patterned supporting layer; c) forming bottom electrodes on the patterned supporting layer; and d) removing the patterned supporting layer.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a semiconductor device; and, more particularly, to a method for manufacturing a semiconductor memory device incorporating therein textured electrodes for implementing a high-density storage capacitor.  
         DESCRIPTION OF THE PRIOR ART  
         [0002]    As is well known, a dynamic random access memory (DRAM) with at least one memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly by downsizing through micronization. However, there is still a demand for downsizing the area of the memory cell.  
           [0003]    To meet the demand, therefore, there have been proposed several methods, such as a trench type or a stack type capacitor, which is arranged three-dimensionally in a memory device to reduce the cell area available to the capacitor. However, the process of manufacturing three-dimensionally arranged capacitor is a long and tedious one and consequently involves high manufacturing cost. Therefore, there is a strong demand for a new memory device that can reduce the cell area with securing a requisite volume of information without requiring complex manufacturing steps.  
           [0004]    In attempt to meet the demand, there have been proposed a high-density dynamic random access memory (DRAM) which incorporates bottom electrodes having textured surface morphology by forming hemispherical grain (HSG) thereon.  
           [0005]    One of the major shortcomings of the above-described high-density DRAM is that it requires processes for forming a nitride layer and a buffer oxide layer as an etching stop layer during the formation of the bottom electrodes.  
         SUMMARY OF THE INVENTION  
         [0006]    It is, therefore, an object of the present invention to provide a method for manufacturing a semiconductor device capable of simplifying the manufacturing steps thereof by incorporating therein a carbon layer as a supporting layer.  
           [0007]    In accordance with one aspect of the present invention, there is provided a method for manufacturing a semiconductor device for use in a memory cell, the method comprising the steps of: a) preparing an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conductive plugs; b) forming a supporting layer, made of carbon, on top of the active matrix and patterned into a predetermined configuration, thereby obtaining a patterned supporting layer; c) forming bottom electrodes on the patterned supporting layer; d) removing the patterned supporting layer; e) forming hemispherical grains (HSGs) on surfaces of the bottom electrodes; f) forming capacitor dielectric films on top of the bottom electrodes; and g) forming top electrodes on top of the capacitor dielectric films, thereby obtaining a capacitor.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]    The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:  
         [0009]    [0009]FIG. 1 is a cross sectional view setting forth a semiconductor device in accordance with the present invention; and  
         [0010]    [0010]FIGS. 2A to  2 F are schematic cross sectional views setting forth a method for the manufacture of the semiconductor memory device in accordance with the present invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0011]    There are provided in FIGS. 1 and 2A to  2 F a cross sectional view of a semiconductor device  100  for use in a memory cell and cross sectional views setting forth a method for the manufacture thereof in accordance with preferred embodiments of the present invention. It should be noted that like parts appearing in FIGS. 1 and 2A to  2 F are represented by like reference numerals.  
         [0012]    In FIG. 1, there is provided a cross sectional view of the inventive semiconductor device  100  comprising an active matrix  10 , bottom electrodes  25  provided with hemispherical grains (HSGs)  26 , a capacitor dielectric layer  28  and a top electrode layer  30 . The active matrix  10  includes a silicon substrate  2 , transistors formed on top of the silicon substrate  2 , an isolation region  4  for isolating the transistors, poly plugs  16 , a bit line  18  and word lines  20 . Each of the transistors has diffusion regions  6 , a gate oxide  8 , a gate line  12  and a side wall  14 .  
         [0013]    In the semiconductor device  100 , the bit line  18  is electrically connected to one of the diffusion regions  6  to apply an electric potential. Each of the bottom electrodes  26  is electrically connected to the other diffusion regions  6  through the poly plugs  16 . Although the bit line  18  actually extends in right and left directions bypassing the poly plugs  16 , the drawing does not show these parts of the bit line  18 . It is preferable that the bottom electrodes  25  are made of a material such as polysilicon, amorphous silicon (a—Si) or the like. And also, each of the bottom electrodes  26  has a textured surface to enlarge the electrode surface area without increasing the lateral dimensions thereof.  
         [0014]    [0014]FIGS. 2A to  4 F are schematic cross sectional views setting forth the method for manufacture of a semiconductor memory device  100  in accordance with the present invention.  
         [0015]    The process for manufacturing the semiconductor device  100  begins with the preparation of an active matrix  10  including a silicon substrate  2 , an isolation region  4 , diffusion regions  6 , gate oxides  8 , gate lines  12 , side walls  14 , a bit line  18 , poly plugs  16  and an insulating layer  22 , as shown in FIG. 2A. The bit line  18  is electrically connected to one of the diffusion regions  6  to apply an electric potential. Each of the poly plugs  16  is electrically connected to the other diffusion regions  6 , respectively. Although the bit line  18  actually extends in right and left directions bypassing the poly plugs  16 , the drawing does not show these parts of the bit line  18 . The insulating layer  22  is made of a material, e.g., boron-phosphor-silicate glass (BPSG).  
         [0016]    In an ensuing step, a supporting layer, e.g., made of carbon, is formed on top of the active matrix  10  by using a method such as a chemical vapor deposition (CVD) or a physical vapor deposition (PVD) and patterned into a predetermined configuration, thereby obtaining a patterned supporting layer  24 , as shown in FIG. 2B. If the supporting layer is made of oxide and an etching stop layer is made of nitride, there is occurred a punch effect during the etching of the supporting layer due to its low etching ratio between the supporting layer and the etching stop layer. In the preferred embodiment, the present invention employs a carbon layer as a supporting layer to prevent the active matrix  10  from the attack during the etching of the supporting layer without forming an additional etching stop layer. This is achieved by utilizing an O 2  gas as an etchant gas.  
         [0017]    In a following step, a conductive layer  23  is formed on top of the patterned supporting layer  24  and the active matrix  10 , as shown in FIG. 2C. Preferably, the conductive layer  25  is made of a material selected from a group consisting of amorphous silicon, poly silicon, Ta 2 O 5  and TiN. In the preferred embodiment, the conductive layer  23  has a thickness ranging from approximately 400 Å to approximately 700 Å.  
         [0018]    In the next step, a photoresist layer (not shown) is formed on the entire surface of the conductive layer  23 . The photoresist layer has a thickness ranging from approximately 8,000 Å to approximately 15,500 Å. And then, the photoresist layer and the conductive layer  23  are planarized by using a method such as a chemical mechanical polishing (CMP) or the like until the patterned supporting layer  24  is exposed. Thereafter, the patterned supporting layer  24  are removed by using a dry etching, thereby obtaining bottom electrode structures  25 , as shown in FIG. 2D. In this case, the dry etching utilizes an O 2  gas as a reaction gas. It is possible that the patterned supporting layer  24  can be removed by using an etch-back process.  
         [0019]    In an ensuing step, the bottom electrode structures  25  are carried out by a seeding and an annealing processes to produce a rugged surface which has relatively large polycrystalline silicon grains of about 50 to about 250 nm, thereby obtaining bottom electrodes  26 , as shown in FIG. 2E. The annealing process can include the step of dispersing a material such as polysilicon or silicon dioxide on the surfaces of the bottom electrode structures  25  for producing nucleation sites. And also, the annealing process can include the step of accumulating silicon at the nucleation sites, thereby forming the rugged surface having a rough surface morphology. The resulting surface morphology is usually comprised of relatively large polycrystallites, referred as hemispherical grain (HSG) silicon.  
         [0020]    Thereafter, a capacitor dielectric layer  28  and a top electrode layer  30  are formed on top of the bottom electrodes  26 , successively, as shown in FIG. 2F.  
         [0021]    By utilizing a carbon layer as a supporting layer, the present invention can manufacture a semiconductor memory device without forming an etch stop layer on top of the active matrix.  
         [0022]    While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.