Abstract:
In a virtual machine system (VMS) capable of concurrently running at least one operating system (OS) under one real computer system and a control program (VMCP) for controlling the VMS, the object is to reduce the overhead produced for simulating VM I/Os by direct I/O execution. A VM information area of a real sub-channel control block has a status field in which a flag indicating that the sub-channel is dedicated or not is contained. When the flag is &#34;1&#34;, it means that the sub-channel is dedicated to the VM and the sub-channel scheduling by the VMCP is not necessary. As a real interruption priority order is dedicated to a VM, only I/O interruption requests of the VM are queued into the real interruption request queue of that dedicated priority order, and the mixing of VMs in that real interruption priority order is avoided. When an interruption control mask of an interruption priority order of the OS on the VM is &#34;0&#34; indicating that the interruption is not acceptable by the VM, the interruption conrol mask of the corresponding dedicated real interruption priority order is also &#34;0&#34; and the hardware interruption does not take place. Accordingly, the interruption is retained by the hardware and the I/O interruption retention for the VM by the VMCP is avoided.

Description:
This application is a continuation of application Ser. No. 691,909, filed Jan. 16, 1985, now U.S. Pat. No. 4,885,681, issued Dec. 5, 1989. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to a high speed virtual machine system (VMS), and more particularly to method and system for reducing an I/O simulation overhead of the VMS. 
     The specifications of the Japanese Patent Application Kokai No. 55-76950 laid open on Jun. 24, 1975, No. 56-19153 laid open on Feb. 23, 1981 and No. 55-42326 laid open on Mar. 25, 1980 and the U.S. Pat. No. 4,459,661 (Saburo Kaneda et al., Apr. 21, 1982), which was filed with the Convention priority based on the latter Japanese Patent Application Kokai, disclose virtual machine systems. 
     FIG. 1 shows the configuration of a real computer system 9000. Numeral 1000 denotes a central processing unit (CPU), numeral 2000 denotes a main memory, numeral 3000 denotes an I/O processor (IOP), and numeral 4000 denotes an I/O controller (IOC). Numeral 100 denotes a signal line between the CPU 1000 and the main memory 2000, numeral 200 denotes a signal line between the CPU 1000 and the IOP 3000, numeral 300 denotes a signal line between the IOP 3000 and the main memory 2000, and numeral 400 denotes a signal line between the IOP 3000 and the IOC 4000. The real computer system 9000 is operated under a control of a resource management (CPU, main memory and I/O devices) of an overall system of an operating system (OS) on the main memory 2000. 
     The configuration of a virtual machine system (VMS) is shown in FIG. 2. A real computer system 10000 has a similar hardware configuration (CPU, main memory and I/O devices) as that shown in FIG. 1 but it has a VMS control program (VMCP or simply CP) on the main memory 2000. A plurality of logical machines (called virtual machines (VM)) are logically configured by a hardware simulation function of the VMCP. The VM&#39;s 10000-1 (VM1), 10000-2 (VM2) and 10000-3 (VM3) each is logically configured to have the same hardware configuration as the real computer system (called a host system) 10000. The OS-N (N=1, 2, 3) which controls the VM exists on each main memory 2000-N (N=1, 2, 3) of each VM, and those OS&#39;s run concurrently under one host system. The hardware configuration (CPU, main memory, IOP and IOC) in each VM of FIG. 2 is logically configured by the VMCP and most portions of the substance thereof exist on the corresponding hardware configuration in each virtual machine configured by the host system. For example, as its main memory, the VM may exclusively occupy a portion of the main memory 2000 of the host system or may share the main memory 2000, and as its I/O devices, the VM may share the I/O devices of the host system or may exclusively occupy the I/O device. Alternatively, there may be no corresponding I/O device on the host system and the I/O device may be virtually configured by simulation by the VMCP. In any case, the OS on the main memory 2000-N (N=1, 2, 3) on each VM can see the same hardware configuration (CPU, main memory, IOP and IOC) as that of the host system. It should be noted that the architecture (hardware configuration and function as viewed from the OS) of each VM may be somewhat different from the architecture of the host system. Similarly, the architectures of the respective VM&#39;s may be different from each other. For example, a machine instruction set of the host system may not be exactly identical to a machine instruction set of each VM. However, a completely different machine instruction set is excluded from the VMS in the present invention because it increases the load of the VMCP and increases the scale of the host system emulation mechanism. The virtual machine VM in the present invention requires that most of the machine instructions can be directly executed with the same performance as that (execution speed) of the host system on the host system without intervention of the VMCP. While only three VM&#39;s are shown in FIG. 2, any number of VM&#39;s may be included and the upper limit thereof is determined by compromise between the resource capacitance of the host system and the performance of the VM. The host system has a privileged state and a nonprivileged state. A machine instruction which imparts a significant influence to the system (e.g. I/O instruction or system interrupt mask change instruction) is called a privileged instruction and it can be used only in the privileged state. This is well known in the art. 
     FIG. 3 shows the memory hierarchy of the virtual machine VM1 of FIG. 2. Numeral 2060 denotes a virtual space generated by the OS1 on the VM1. The OS1 exists on the main memory 2000-1 of the VM1. The main memory 2000-1 of the VM1 is copied on the main memory 2002 of the host system. (The main memory 2000 of the host system is divided into a hardware system area 2001 and a programmable area 2002 as shown in FIG. 7.). The copy is given by an address translation table 2010. FIG. 4a shows an address translation table 2010(1). The address translation table contains entries corresponding to addresses v2 on the main memory 2000-1 of the VM1 and corresponding addresses r on the main memory 2002. A start address of the address translation table 2010(1) is stored in one control register (Real Address Translation Table Origin Register (RATOR)) 1110 of basic control registers 1100 (see FIG. 7) in the CPU 1000 when the OS1 on the VM1 operates on the main memory 2000-1. In the present case, the address translation table 2010(1) exists on the main memory 2000-1 of the VM 10000-1, that is, on the main memory 2002 of the host system, and the start address is set in the register 1110 described by an address in the main memory 2002 of the host system. 
     Numeral 2060 in FIG. 3 denotes a virtual storage generated by the OS1 on the VM1 and a copy thereof to the main memory 2000-1 of the VM1 is given by an address translation table 2040 managed by the OS1. FIG. 4b shows a format of the address translation table. It contains entries corresponding to addresses v3 of the virtual storage 2060 and corresponding addresses v2 of the main memory 2000-1 of the VM1. A start address of the address translation table 2040 is stored in one control register (VATOR) 1120 of the basic control registers 1100 (see FIG. 7) of the CPU 1000 when the OS1 of the VM1 is running on the virtual storage 2060. In the present case, since the address translation table 2040 exists on the main memory 2000-1 of the OS1, the start address is described by an address system of the main memory 2000-1 of the OS1. The address translation table 2010(1) (called a translation table A) is managed and updated by the VMCP for the VM&#39;s, and the address translation table 2040 (called a translation table B) is managed and updated by the OS on each VM for its own virtual storage. The main memory 2002 of the host system is referred to as a level 1 memory, the main memory 2000-N (N=1, 2, 3, . . . ) of each VM is referred to as a level 2 memory, and the virtual storage 2060 generated by the OS on each VM (usually the OS generates a plurality of virtual storages) are collectively referred to as a level 3 memory. The virtual storage is usually divided into pages of a predetermined size (e.g. 4KB) and mapped into the main memory for each page, and a certain number of continuous pages (e.g. 256 pages,  1MB) are called one segment, as is well known in the art. Numeral 2020 in FIG. 3 denotes I/O operation command words (CCW) generated by the VMCP to start its own I/O operation. Since the VMCP operates on the level 1 memory, the CCW 2020 is generated at the level 1 memory address. It is called a level 1 CCW. The level 1 CCW need not be address-translated, and when an I/O start command is issued to the level 1 CCW, it is directly interpreted by the IOP 3000 and sent to the IOC 4000. The IOC 4000 executes each CCW for each I/O device. Numeral 2030 denotes a CCW prepared by the OS on the VM and is described by the level 2 memory address. The level 2 CCW is prepared by the OS on the VM. When an I/O start instruction is issued to the CCW from the OS on the VM, it may be translated to an equivalent level 1 CCW through the VMCP and the I/O start may be effected by the equivalent level 1 CCW through the VMCP. However, this leads to increase an overhead of the VMCP. Accordingly, in the alternative method, the VMCP intervenes to indicate an address of the address translation table from the level 2 memory to the level 1 memory (translation table A) to the IOP 3000, and the IOP 3000, looking up the translation table 2010, translates the data address in the level 2 CCW (or level 2 memory address) to the level 1 memory address. In this method, the intervention of the VMCP is reduced and the overhead is reduced. The OS on the VM in many cases executes on the level 3 memory and hence the CCW generated by the OS on the VM in many cases exists on the level 3 memory. Numeral 2050 in FIG. 3 denotes a CCW described by the level 3 memory address, that is, a level 3 CCW. When the start I/O instruction is issued to the level 3 CCW by the OS on the VM, it indicates an address of the address translation table from the level 3 memory to the level 2 memory (translation table B) and the address of the translation table from the level 2 memory to the level 1 memory (translation table A) to the IOP 3000 (FIG. 7), and the IOP 3000 looks up the translation table B to translate the data address of the level 3 CCW (level 3 memory address) to the level 2 memory address and looks up the translation table A to translate the translated level 2 memory address to the level 1 address in order to execute the CCW. 
     FIG. 4c shows an address translation buffer 3030 provided in a local storage in the IOP 3000 (FIG. 7) to reduce the address translation overhead in the IOP 3000. A field 1 of the address translation buffer 3030 contains VM numbers (VM #), a field 2 contains start addresses of the translation table A and the translation table B, a field 3 contains identification flags thereof, a field 4 contains CCW data addresses before translation and a field 5 contains level 1 memory addresses after translation. The IOP 3000 (FIG. 7) looks up the address translation buffer to translate the address, and if it is not found, looks up the translation table B and the translation table A to translate the address and register the translated address in the translation buffer 3030. The address translation buffer is a high speed local storage in the IOP 3000 and it is faster than the speed of looking up the translation tables B and A on the main memory 2002. It should be noted that the level 2 CCW, the level 3 CCW and the data buffers thereof should be fixed on the level 1 memory during the I/O execution. FIG. 5 illustrates a manner of dividing a continuous area of the main memory 2002 of the host system to use the divided sub-areas as the main memories for the respective VM&#39;s. When such VM&#39;s are used, a predetermined address displacement α is added to the address of the main memory of the VM to obtain the address of the main memory 2002 of the host system. In FIG. 5, the address displacement for the VM1 is α 1  and the address displacement for the VM2 is α 2 . In this case, the address translation 2010 from the level 2 memory address to the level 1 memory address may be a mere table to manage lower limit addresses and upper limit addresses of the respective VM&#39;s, as shown by 2010(2). In this case, it is easy to address-translate the level 2 CCW and an entry of the address translation buffer 3030 for the level 2 CCW (entry of &#34;0&#34; field 3 of the address translation buffer 3030) is not necessary. Alternatively, as shown in FIG. 5, the translation table 2010(2) is read into the local storage in the IOP 3000 (FIG. 7), the address displacement α is obtained by the VM # and it is added to translate the address (translation from the level 2 memory address to the level 1 memory address). A high speed VM mode is provided for the VM in which the entire main memory of the VM (FIG. 3) is resident in the main memory 2002 of the host system and fixed therein or it occupies a continuous area of the main memory of the host system as shown in FIG. 5. In the high speed VM mode, most privileged instructions issued by the OS on the VM are directly executed (execution without the VMCP in the almost same performance as that of the host system). However, the I/O instruction on the VM requires the intervention by the VMCP as will be described later. 
     Referring to FIG. 6, a manner in which the start IO instruction issued by the OS on the VM is executed by the VMCP is explained. The OS on the VM designates a sub-channel number (sub-channel #) which corresponds to the I/O device to issue the start I/O instruction. Since this sub-channel # is one under the VM, it is called a virtual sub-channel #. The VMCP translates it to a corresponding real sub-channel #. The correspondence is determined at the time of defining the VM. The VMCP checks the level of the CCW to which the start I/O instruction was issued by the OS on the VM. Usually, it is represented by an operand of the start I/O instruction. Let us assume that the start I/O instruction is issued to the level 3 CCW. In FIG. 6, the CCW 2810 is the CCW on the level 2 memory and the data address thereof is the level 3 memory address. The VMCP adds the operand 2800 to the CCW 2810 generated by the OS to issue the start I/O instruction. The operand 2800 contains a field L indicating the level of the CCW. When L=3, CCWs (2810) are the level 3 CCWs, and the operand 2800 contains the start address (VATOR) of the translation table B, a segment size (SS) and a page size (PS) of the level 3 memory which is the virtual space created by the OS on the VM. It also contains the start address RATOR of the translation table A, a segment size (SS), a page size (PS) of the level 2 memory when the level 2 memory is the virtual space created by the VMCP, and also contains an address to the CCW (2810). They are sent to the IOP 3000 (FIG. 7) through the line 200 upon the issuance of the start I/O instruction by the VMCP and basic information is set in the corresponding sub-channel register 3011. Similar basic information is stored in the corresponding sub-channel control block in the sub-channel control blocks 2090 shown in FIG. 7. (See sub-channel control block 2091 of FIG. 10). The IOP 3000 (FIG. 7) uses the address translation table in the sub-channel to execute the CCW 2810 generated by the OS while it translates the address. 
     FIG. 7 shows a hardware configuration in the prior art VMS and a block diagram concerning the I/O execution. A CPU 1000 includes a prefix register 1010 including an address of an area prefix (PSA) containing hardware interrupt information, CPU control registers 1100 and a program status word (PSW) 1020 containing a CPU basic status (such as an interrupt control bit or a machine instruction address to be executed next). It also includes an I/O instruction execute circuit 1030, an I/O interrupt circuit 1040, an I/O instruction execution microprogram 1050 and an I/O interrupt processing microprogram 1060. The V-bit representing a VM mode is present in 1090 as a VMS flag. During the running of VM, this bit is set to &#34;1&#34; by the VMCP. The high speed VM mode flag H exists in 1090. The VMS control flag 1090 may be in another form. For example, a VMCP mode (hypervisor mode) and a VM mode may be provided and the VM mode may include the preferred or high performance VM mode and the non-preferred VM mode. They are more or less similar, as described above, the IOP 3000 executes the level 3 CCW or the level 2 CCW (see FIG. 3) while using the information of the address translation buffer 3030 (see FIG. 4C) under the control of the microprogram 3020 in accordance with the address translation information (FIG. 6) contained in the sub-channel control blocks 2090 and the sub-channel registers 3010. The main memory 2000 in FIG. 7 is divided into a hardware system area (HSA) 2001 and a programmable area 2002. The HSA 2001 contains hardware information to be used by the CPU 1000 and the IOP 3000 and it can be accessed and updated by the microprograms 1050, 1060 and 3020 of the CPU and the IOP but cannot be accessed by a machine instruction opened to a normal user of the CPU 1000. The programmable area 2002 can be accessed by a machine instruction and it is a main memory area as viewed from the OS or the VMCP. I/O instruction, such as start I/O instruction, and step I/O instructions request the operations of the I/O devices, and these I/O requests issued from those I/O instructions are queued in an I/O request queue 2070 in a form of request queue. It comprises control blocks 2071 containing I/O request real sub-channel numbers interconnected by address pointers. After queuing to the I/O request queue, a start signal is sent to the IOP 3000 through the line 200. The IOP 3000 accesses the I/O request queue 2070 in the HSA 2001 and sequentially reads out request queue elements 2071 to process the I/O request. The I/O interrupt request is queued in the I/O interrupt request queue 2080 in the priority order of real interruption. A structure therefor is shown in FIG. 9. Eight interruption priority orders 0, 1, 2, 3, 4, 5, 6 and 7 are available and they are assigned by the operands together with the sub-channel numbers when the I/O instructions are issued. FIG. 10 shows a sub-channel control block 2091 in the sub-channel control blocks 2090 (FIG. 7). The sub-channel control blocks are arranged in the order of the real sub-channel numbers and their locations are uniquely determined by the real sub-channel numbers. The start address of the sub-channel control block 2090 is set in one control register in the control registers 1100 of the CPU 1000 (FIG. 7). The interruption priority order can be assigned to each sub-channel. Let us assume that the OS on the VM issues the I/O instruction while designating the sub-channel number and one of the interruption priority orders 0-7. Since the VM mode bit 1090 in FIG. 7 is &#34;1&#34;, the I/O instruction executing μp(microprocessor) 1050 transfers the control to the VMCP. The control is transferred to the VMCP by a new PSW in the PSA 2100 of the VMCP as a kind of interruption. Since the address of the PSA of the VMCP has been set in the VMCP prefix register 1010 (FIG. 7) when the VM was started, it is referred to. 
     The VMCP handles the sub-channel number designated by the OS on the VM as a virtual sub-channel number, translates it to a real sub-channel number, manages a real sub-channel status and if the real sub-channel is available, designates the address translation information 2800 shown in FIG. 6 and issues an I/O instruction in place of the OS on the VM. 
     The interruption priority order designated by the OS on the VM is the virtual interruption priority order. The VMCP issues the I/O instruction while using the virtual interruption priority order as the real interruption priority order. Accordingly, the real interruption priority order is shared by the OS&#39;s on the VM&#39;s. Accordingly, the I/O interrupt requests from the sub-channels of the OS&#39;s on the VM&#39;s are mixedly queued in the real interruption priority order queue of the I/O interrupt request queue 2080 of FIG. 9. 
     The reasons for intervention by the VMCP to the execution of the I/O instruction from the OS on the VM are as follows. 
     (i) The virtual sub-channel number designated by the OS on the VM must be translated into the real sub-channel number. 
     (ii) Since the real sub-channel may be shared by the OS&#39;s on the VM&#39;s, sub-channel scheduling therefor is required. 
     FIG. 11 shows a manner of controlling the I/O interruption. The I/O interrupt request from the sub-channel is detected by the IOP 3000 and the corresponding sub-channel control block is queued in the I/O interrupt request queue 2080 (see FIG. 7). A structure of the I/O interrupt request queue is shown in FIG. 9, and the sub-channel control blocks are queued in the order of the real interruption priority. A bit of a corresponding real interruption pending register 1042 shown in FIG. 11 is set to &#34;1&#34;. When the bit of the interruption pending register 1042 and the bit of the corresponding real interruption priority order mask register 1041 are both &#34;1&#34; and an I/O mask of the PSW 1020 is &#34;1&#34;, the I/O interruption is initiated for the corresponding real interruption priority order and the control is transferred to the I/O interrupt processing microprogram 1060. The above operation in carried out by a hardware circuit shown in FIG. 11. 
     In the VMS, the real interruption priority order is shared by the OS&#39;s on the VM&#39;s as described above. Accordingly, during the running of the VM, the bits of the real interruption priority order mask register 1041 are set to the OR function of the interruption priority order masks of the OS&#39;s on the VM&#39;s or to &#34;1&#34; so that the interruption is always accepted. The I/O mask of the PSW 1020 is also set to &#34;1&#34;. Consequently, if a bit of the real interruption pending register 1042 is changed to &#34;1&#34; by the I/O interrupt request from the sub-channel, an output of the one of AND gates 1046 becomes &#34;1&#34;, an output of an OR gate 1043 becomes &#34;1&#34; and an output of an AND gate 1044 becomes &#34;1&#34; so that the I/O interrupt processing microprogram 1060 is immediately started by the I/O interrupt circuit shown in FIG. 11. The I/O interrupt processing microprogram 1060 dequeues the sub-channel queued in the corresponding highest interruption priority order I/O interrupt request queue (FIG. 9) to reflect the interruption to the prefix of the VMCP. If the interrupt request queue of the real interruption priority order is vacant, the bit of the real interruption priority order real interruption pending register 1042 is set to &#34;0&#34;. As a result, the interruption pending is cleared. By the reflection of the interruption to the VMCP, the control is transferred to the I/O interrupt processing program of the VMCP. The real subchannel number which requested the I/O interruption as the I/O interrupt parameter and the corresponding VM number are also transferred to the VMCP. The VMCP carries out the following processing to reflect the I/O interruption to the VM. 
     (i) Translates the real sub-channel number to the virtual sub-channel number. 
     (ii) Checks the interruption priority mask register of the VM and the I/O mask of the PSW to determine if the I/O interruption is acceptable. 
     (iii) If the VM accepts the interruption, the interruption is indicated to the prefix PSA of the VM. 
     (iv) If the VM does not accept the interruption, the interruption is made pending by the VMCP. 
     Since the real interruption priority order is shared by the VM&#39;s, the mask must be set to an OR function (usually &#34;1&#34;) of the corresponding masks of the VM&#39;s. As a result, the VMCP may be interrupted even for the noninterruptable order in the VM. In such a case, the I/O interruption is made pending by the VMCP. Accordingly, simulation by the intervention of the VMCP is required for the I/O instruction to the sub-channel. 
     As described above, in the I/O execution of the OS on the VM in the prior art virtual machine system, the function of the IOP for directly executing the level 3 CCW and the level 2 CCW exists but the VMCP always intervenes and the simulation is required. Accordingly, the simulation overhead of the VMCP increases for a load having a high I/O issuance frequency. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to reduce the simulation overhead of an I/O instruction and the I/O interruption of the OS on the VM by VMCP and support direct execution of the I/O instruction on the VM and the I/O interruption by hardware and microprogram. 
     In accordance with the present invention, in a system having a virtual machine system (VMS) in which at least one operating system can be simultaneously run under one real computer system (host system) and a control program (VMCP) for controlling the VMS, whether an I/O device of the host system is dedicated to or occupied by an OS or not in accordance with information stored in the real computer system is determined, and if the I/O device designated by an I/O instruction other than an I/O start instruction issued by the OS is dedicated to the OS which is currently being run, the I/O instruction is issued to that I/O device, and if it is not dedicated to the OS which is currently running, the OS is interrupted and control is transferred to the VMCP. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a block diagram of a real computer system by a conventional OS; 
     FIG. 2 is a block diagram of a prior art virtual machine system (VMS); 
     FIG. 3 shows a memory hierarchy in a prior art virtual machine (VM); 
     FIGS. 4-11 show prior art examples in which; 
     FIGS. 4A to 4C show address translation tables; 
     FIG. 5 shows the VM main memory which occupies a continuous area of a real main memory; 
     FIG. 6 shows an operand of an I/O instruction issued by a VMCP to simulate the I/O of the VM; and sub-channel registers; 
     FIG. 7 shows a configuration of a host system; 
     FIG. 8 shows an I/O request queue; 
     FIG. 9 shows an I/O interrupt request queue; 
     FIG. 10 shows real sub-channel control blocks; 
     FIG. 11 shows an I/O interrupt circuit; 
     FIGS. 12 to 22 relate to the present invention in which: 
     FIG. 12 shows a configuration of a host system; 
     FIG. 13 shows a prefix control table; 
     FIG. 14 shows a device address translation table and priority order translation table; 
     FIG. 15 shows a main memory address translation table; 
     FIG. 16 shows real sub-channel control blocks; 
     FIG. 17 shows a start VM instruction; 
     FIG. 18 shows a VM number register; 
     FIG. 19 shows VMS control flags; 
     FIGS. 20A and 20B illustrate a manner of assigning interruption priority orders; 
     FIGS. 21A -21D shows a VMS interrupt control registers; 
     FIG. 22 shows a VMS I/O interrupt circuit. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The preferred embodiments of the present invention are now described. FIG. 12 shows an overall configuration of one embodiment of the present invention. 
     Elements of a CPU 1000&#39; are similar to those of FIG. 7 but some of them are expanded in function. An HSA 2001 includes the same elements as those in FIG. 7. (I/O request queue 2070, I/O interrupt request queue 2080 and real sub-channel control blocks 2090&#39;.). However, a prefix control table 2300, a translation table address management table 2400 and a VM management table 2700 include new information. 
     A programmable area 2002 includes the same elements as those of FIG. 7 (VMCP PSA 2100, VM1 PSA 2110, VM2 PSA 2120, (PSA&#39;s of other VM&#39;s), VMCP 2200, level 2 memory to level 1 memory address translation tables 2010 and level 3 memory to level 2 memory address translation tables 2040). However, an interruption priority order number translation table 2500 and sub-channel number translation tables 2600 include new information. An IOP 3000&#39; is similar to the IOP 3000 in FIG. 7 in configuration but expanded in function. The new information included in the HSA 2001 and the programmable area 2002 is now explained. 
     FIG. 13 shows the prefix management table 2300. It includes the VMCP PSA address, VM1 PSA address, VM2 PSA address and VM3 PSA address. While not shown in FIG. 13, other VM PSA&#39;s may be registered. The PSA addresses are referred by a microprogram of the CPU 1000&#39; and they are addresses in a host system programmable area 2002. The VM PSA address is imparted as one of start instruction operands when the VM is started and it is stored in the corresponding entry of the prefix management table 2300 when the instruction is executed. A start address of the prefix management table 2300 is stored in one of the control registers 1100&#39; of the CPU 1000&#39; (see FIG. 12). The prefix management table is optional. A case where it is used will be explained later. FIG. 14 shows the translation table address management table 2400. It contains a start address of the sub-channel number translation table 2600 and a start address of the interruption priority order translation table 2500, for each VM. A start address of the translation table address management table 2400 is also stored in one of the control registers 1100&#39; of the CPU 1000&#39;. A method of looking up the sub-channel number translation table 2600 and the interruption priority order translation table 2500 is shown in FIG. 14. A virtual sub-channel number (two bytes) is divided into D0.256 and Dl, and a first half table 2601 pointed to by the content of the corresponding entry of the address management table 2400 is looked up by D0. An address of a second half table 2602 is contained in the D0-th entry of the first half table 2601 so that a D1-th entry of the second half table 2602 is looked up. In this manner, the corresponding real sub-channel number D0&#39;.256+D1&#39; is obtained. The virtual interruption priority order is translated to the corresponding real interruption order by merely reading the corresponding entry of the translation table 2500. The sub-channel number translation table 2600 and the interruption priority order translation table 2500 are prepared by the VMCP when they are designated by the VMCP command or when the VM is defined from the VM defining information, and designated by the start instruction operand when the VM is started, and stored in the corresponding entry of the translation table address management table 2400 when the start instruction is executed. The translation tables 2600, 2500 and 2400 are optional. Those translation tables are not necessary so long as the VM which uses the I/O execution system of the present invention in the VMS obeys a rule of virtual sub-channel number being equal to a real sub-channel number, and virtual interruption priority order being equal to real interruption priority order. 
     FIG. 15 shows the content of the VM management table 2700. It contains sizes (Z0, Z1, . . . ) of the main memories of the corresponding VM&#39;s, and address (RATOR0, RATOR1, . . . ) of the level 2 memory address to level 1 memory address translation table 2010. Such information is derived from the VM definition information and stored in the corresponding entry of the VM control table 2700 in the HSA 2001 by the start VM instruction. A start address of the VM control table 2700 is stored in one of the control registers 1100&#39; (see FIG. 12) in the CPU 1000&#39;. A start address of the control block in the HSA 2001 is stored in the control register 1100&#39; in the CPU 1000&#39; as is done in the prior art system. When the VM which supports the I/O execution system of the present invention is limited to one which occupies the continuous area on the main memory 2002 (FIG. 5) as a main memory therefor, the VM management table 2700 may be replaced by a translation table 2010(2) which defines upper and lower limits. When the translation table 2010(2) shown in FIG. 5 is used, the upper and lower limit addresses α i  and α i+1  (i=1, 2, 3,. . . ) are designated by the VM start instruction, and the corresponding entry of the translation table 2010 (2) is set in the HSA 2001 as the instruction is executed. FIG. 16 shows the real sub-channel control blocks 2090&#39;, one real sub-channel control block 2091&#39; thereof and a VM information area 2092&#39; thereof. The VM information area 2092&#39; includes status field, VM number, virtual sub-channel number, corresponding real sub-channel number, virtual interruption priority order, corresponding real interruption priority order and CCW address translation information 2094. The status field includes flags indicating whether the sub-channel is occupied or not and whether the sub-channel is in an I/O direct execution suppress mode or not. The CCW address translation information 2094 has the same content as the address translation information 2092 of FIG. 10. The information in the VM information area 2092&#39; is set from the VM definition information when the VM is defined, or when it is designated by the VMCP command, or when the I/O instruction is executed. 
     The dedication of the real sub-channel or the dedication of the real interruption priority order is designated when the VM is defined or by the VMCP command. When a real sub-channel is dedicated, the following fields in the VM information area 2092&#39; are set. 
     A sub-channel dedication flag in the status field 2093 
     The I/O direct execution mode suppress flag is normally set to &#34;0&#34; and the I/O direct execution mode is set to a support state. 
     A VM number to which the sub-channel is dedicated, 
     Virtual sub-channel number and real sub-channel number 
     Start address (RATOR, see FIG. 4a) of the dedicating VM main memory (level 2 memory) to level 1 memory address translation table, in the CCW address translation information 2094. If the VM occupies the main memory shown in FIG. 5, the upper and lower limits thereof α i  and α i+1  (i=1, 2, 3, . . . ) may be set. 
     In the shared sub-channel, such information is set as required when the I/O instruction is executed. In this case, it is set in the corresponding field on the VM information area of the I/O issuing VM. 
     FIG. 17 shows the format of the start VM instruction. Numeral 2900 denotes the start VM instruction and numeral 2910 denotes an operand. The operand 2910 contains the VM number, VM PSW, VM PSA address, start address of the sub-channel number translation table 2600 (FIG. 14), start address of the interruption priority order translation table 2500 (FIG. 14), start address RATOR (see FIG. 4a) of the VM main memory to host system main memory address translation table 2010 (FIG. 15) and VM main memory size. (For the latter two, when the VM to be started uses the continuous area of the main memory 2002 shown in FIG. 5 as the VM main memory, the upper and lower limits α i  and α i+1  (i=1, 2, 3, . . . ) may be designated. Of those operand information, the VM running PSW, VM PSA address, real interruption priority order status and VMS control flags are determined when the VM is started, and other information is determined by the VM definition information when the VM is defined. The real interruption priority order status, real interruption priority order dedication status and VMS control flags will be explained later. Those operands are set by the VMCP. The start VM instruction is not necessarily of the format shown in FIG. 17, although the information shown in FIG. 17 is needed as the operands. FIG. 18 shows a VMS control register 1080. A register 1081 contains the VM number of the currently running VM and is set by the start VM instruction. The content of the register is given by the content of one field of the operand 2910 (FIG. 17) of the start VM instruction. FIG. 19 shows the VMS control flags 1090&#39; (see FIG. 12). The flags are initialized by one field of the operand of the VM start instruction (FIG. 17). The flags have the following meanings, respectively. 
     V: It is &#34;1&#34; during running of the VM. It is &#34;0&#34; during running of the VMCP or running in the real computer mode. It is set to &#34;1&#34; by the start VM instruction and set to &#34;0&#34; when the control is transferred to the VMCP by the interruption. It is similar to the prior art system (FIG. 7). 
     H: It is set to &#34;1&#34; when a privileged instruction may be directly executed during the running of VM. When this flag is &#34;1&#34;, most privileged instructions in the running of VM are directly executed by the instruction execute circuit of the CPU 1000&#39;. When H is &#34;1&#34;, it is a high speed VM mode, similar to the prior art system (FIG. 7). 
     R: It is set to &#34;1&#34; when the OS on the VM is limited such that the virtual sub-channel number is equal to the real sub-channel number, and the virtual interruption priority order is equal to the real interruption priority order. When this flag is &#34;1&#34;, the sub-channel number translation and the interruption priority order translation by the microprogram are eliminated. (In this case, the translation tables 2400, 2600 and 2500 shown in FIG. 14 are not necessary.) 
     D: It is &#34;1&#34; when the direct I/O execution by the VM (without the intervention of the VMCP) in accordance with the present invention is enabled. It is initially set to &#34;1&#34; by the start VM instruction of the VMCP. 
     In general, a VM can accept an I/O interruption from an I/O interruption priority order only if both the VM&#39;s PSW I/O mask is &#34;1&#34; and the I/O interruption priority order mask of the VM is &#34;1&#34;. When the currently running VM has an I/O interruption pending factor on a shared I/O interruption priority order, and the pending is caused by the fact that the shared I/O interruption priority order mask of the VM is &#34;1&#34;, and the VM&#39;s PSW I/O mask, however, is &#34;0&#34;, the N is set to &#34;1&#34;. The pending factor is actually managed by the VMCP for the VM. 
     The N is used when an I/O instruction which checks the I/O interrupt request of the VM is issued from the OS on the VM. That I/O instruction checks the I/O interruption from an I/O interruption priority order whose mask of the VMis &#34;1&#34;. The N is initialized by the VMCP by the start VM instruction. It is used when an instruction for checking the I/O interrupt virtual interruption priority order mask is &#34;1&#34; is executed. It is initialized by the VMCP by the start VM instruction. 
     FIGS. 20a and 20b show a method of assigning the real interruption priority orders. 32 real interruption priority orders 0-31 are used. The real interruption priority order 0 is the highest priority order and is exclusively used by the VMCP. The real interruption priority orders to be dedicated to the VM&#39;s are assigned to the VM&#39;s in the ascending order starting from the real interruption priority order 1 (descending order in the interruption priority order). The shared interruption priority orders are assigned to the VM&#39;s in the descending order starting from the real interruption priority order 31 (ascending order in the interruption priority order). In FIGS. 20a and 20b, the real interruption priority order 1 is assigned to the virtual interruption priority order 0 of the VM1 and it is exclusively used, and the real interruption priority order 31 is assigned to the virtual interruption priority orders 1-7 and it is shared by the VM&#39;s. For the VM2 and VM3, the assignment is done as shown in FIGS. 20a and 20b. The virtual interruption priority order in the VM1 is actually 0 or (1-7). Accordingly, there are two real interruption priority orders which can be effectively used by the OS on the VM1. The restriction to the OS can be permitted. The particular interruption priority order to be dedicated to the VM should be determined under an overall plan of the VMS and controlled by the VMCP. The exclusive or shared status of the real interruption priority order thus determined is given by the operand of the start VM instruction (see FIG. 17) and set into the real interruption priority order dedicated status register 1049 (FIG. 21) when the instruction is executed. 
     FIG. 21 shows the real interruption priority order mask register 1041&#39;, real interruption pending register 1042&#39;, real interruption priority order status register 1045 and real interruption priority order dedication status register 1049. Those are all included in the I/O interrupt circuit 1040&#39; of FIG. 12. The registers 1041&#39; and 1042&#39; are similar to those in the prior art system but have increased number of bits. In FIG. 21, they have 32 bits which are four times as large as 8 bits in the prior art system, in order to support the dedication system of the real interruption priority order in the VM. The explanation thereof is omitted because the meaning is the same. The meaning of the real interruption priority order status register 1045 is described below. It means that when the bit n (0-31) is &#34;0&#34;, the real interruption priority order n is dedicated to the currently running VM. In another case, it is set to &#34;1&#34;. The content of the real interruption priority order dedication status register 1049 is described below. When a bit c (0-31) is &#34;0&#34;, it means that the real interruption priority order c is dedicated to a VM, and when the bit c is &#34;1&#34;, it means that the real interruption priority order c is shared. The registers 1045 and 1049 are initialized by the operand of the start VM instruction. The real interruption priority order mask register 1041&#39; is controlled and updated by the VMCP. The real interruption pending register 1042&#39; is set by the IOP 3000&#39; (FIG. 12) and reset by the I/O interrupt processing microprogram 1060&#39; (FIG. 22). 
     FIG. 22 is a circuit diagram of the I/O interrupt circuit 1040&#39; of the present invention. For the sake of simplicity, only ten real interruption priority orders are shown in FIG. 22 but there are actually 32 orders connected in a similar manner. Let us assume that the real interruption priority order c (c=0-31) has an interruption pending factor (that is, the sub-channel having the interrupt request is queued to the real interruption priority order (c) level queue of the I/O interrupt request queue 2080 and the corresponding bit of the pending register 1042&#39; is set to &#34;1&#34;). If the interruption priority order c is dedicated to the currently running VM, the corresponding bit of the real interruption priority order status register 1045 is zero, and the OR gate 1048 outputs the content of the I/O mask of the PSW so that the I/O interrupt mask of the PSW 1020 is effective. Accordingly, only when the corresponding bit of the corresponding real interruption priority order mask register 1041&#39; is &#34;1&#34; and the I/O mask of the PSW is &#34;1&#34;, the corresponding output of the AND gate 1047 is &#34;1&#34;, the I/O interruption is started and the control is transferred to the I/O interrupt processing microprogram 1060&#39;. When the interruption priority order c is shared or dedicated to another VM, the corresponding bit of the register 1045 is &#34;1&#34;, the corresponding output of the OR gate 1048 is &#34;1&#34; and the I/O mask of the PSW 1020 is ignored so that the I/O interruption is started if the bit of the corresponding real interruption priority order mask register 1041&#39; is &#34;1&#34;. After the processing of the interruption by the microprogram 1060&#39;, if the interrupt request queue of the interruption priority order c is vacant, the corresponding bit of the pending register 1042&#39; is cleared to &#34;0&#34; by the microprogram. 
     The manner in which the I/O instruction of the OS on the VM and the I/O interruption are executed and processed by the hardware, microprogram and information on the main memory is now explained. 
     The following presumptions are made and the VM is in the high speed VM mode. 
     (i) The entire main memory of the VM is resident in the main memory of the host system. 
     (ii) The direct I/O execution of the OS on the VM (without the intervention of the VMCP, including the direct execution of the I/O interrupt) is supported only for the dedicated sub-channel and the sub-channel having the dedicated interruption priority order. 
     When the VM is started, the VMCP sets the operand of the start VM instruction of FIG. 17 and the value of the bit c of the real interruption priority order mask register 1041&#39; in a manner shown below. 
     When the real interruption priority order c (0-31) is dedicated to the currently running VM, its mask is set to the mask of the corresponding virtual interruption priority order (only one is assumed for the sake of simplicity) of the OS on the VM. 
     When the interruption priority order c is dedicated to other VM, its mask is set to the value of an AND function of the mask of the corresponding virtual interruption priority order of the VM and the I/O mask of the PSW of the VM. Alternatively, the bit c may be set to &#34;0&#34; if the delay of the interruption of the interruption priority order c does not cause a problem. 
     When the interruption priority order c is shared by the VM&#39;s, the bit c is set to &#34;1&#34;. 
     When the virtual interruption priority order mask is changed during the running of the VM, the change is immediately reflected to the real interruption priority order mask register 1041&#39; (FIG. 21). Accordingly, the instruction to change the virtual interruption priority order mask of the OS may be simulated via the VMCP or the change may be reflected to the register 1041&#39; by the microprogram processing of the CPU, as is done in the prior art system. When the VM in the high speed VM mode is started, the PSW of the VM is set in the VM PSW of the operand of the start VM instruction of FIG. 17 and it is set in the PSW 1020 (FIG. 12) of the CPU 1000&#39;. Accordingly, the I/O mask of the PSW coincides with the I/O mask of the running VM. The coincidence is attained because the change of the PSW of the OS during the VM run is immediately reflected to the PSW 1020. The instruction to change the PSW of the OS may be reflected to the PSW 1020 of the CPU 1000&#39; by the direct execution or may be reflected by the simulation via the VMCP. After those settings, the control is transferred to the OS on the VM by the start VM instruction (FIG. 17). As the instruction is executed, the currently running VM number register 1081 of FIG. 18, PSW 1020 (FIG. 12) of the CPU 1000&#39;, the corresponding entry of the prefix control table of FIG. 13, the corresponding entry of the translation table address, management table 2400 of FIG. 14, the corresponding entry of the VM management table of FIG. 15, real interruption priority order status register 1045 of FIG. 21 and VMS control flags of FIG. 19 are initialized. 
     Let us assume that the I/O instruction is issued from the OS on the VM. The I/O execute circuit 1030&#39; of the CPU 1000&#39; carries out the following processings under the control of the microprogram 1050&#39;. 
     (1) If not in the high speed VM mode (VMS control flag H=&#34;0&#34;, see FIG. 19), the OS is interrupted and control is transferred to the VMCP by reflecting the interruption to the PSA 2100 of the VMCP by using the prefix register 1010 of the VMCP (FIG. 12). 
     (2) In the high speed VM mode (VMS control flag H=&#34;1&#34;), whether the VM is in an I/O direct execution mode (VMS control flag D=&#34;1&#34;) or not is checked (FIG. 19). 
     (3) When D=&#34;0&#34;, the OS is interrupted and control is transferred to the VMCP. 
     (4) When D=&#34;1&#34;, the VMS control flag R is checked. If R=&#34;0&#34;, the corresponding virtual sub-channel number translation table 2600 is looked up to translate the given virtual sub-channel number to a real sub-channel number. If the virtual interruption priority order is given by the instruction operand, the interruption priority order translation table is looked up to translate it into the real interruption priority order. Whether it is dedicated or not is checked by the real interruption priority order dedication status register 1049, and it is written into the status field of the VM information area 2092&#39; of the sub-channel control block (FIG. 16). 
     The correspondence between the virtual interruption priority order and the real interruption priority order is also written. When R=&#34;1&#34;, no translation is required and the same values are written. 
     (5) When the real sub-channel control block 2091&#39; (FIG. 16) obtained is the dedicated sub-channel and has the dedicated interruption priority order, the I/O instruction is executed. The subsequent operation is similar to that in the real computer system. When an asynchronous I/O device operation is required, the sub-channel is queued in the I/O request queue 2070 (FIG. 8). A condition code and control are returned to the program which issued the I/O. 
     (6) If the real sub-channel obtained is the shared sub-channel or the interruption priority order is shared, the OS is interrupted, control is transferred to the VMCP and the simulation is effected. The remaining processes are entrusted to VMCP&#39;s simulation. 
     (7) If the I/O instruction issued by the OS on the VM is one which examines an I/O interrupt request whose virtual interruption priority order mask is &#34;1&#34;, the following processing is carried out. The interrupt request is checked for the dedicated real interruption priority order of the current running VM. If there is no I/O interrupt request, the shared interruption priority order should be checked. Since the VMCP manages the interrupt pending for the shared interruption priority order, it is necessary to transfer the control to the VMCP. However, since this is contrary to the principle of direct execution, the control flag N (FIG. 19) of the VMS is used. When N=&#34;1&#34;, it means that VMCP holds the I/O interrupt the shared interruption priority order and its virtual interruption priority order mask is &#34;1&#34;. Accordingly, the OS is interrupted and control is transferred to the VMCP. When N=&#34;0&#34;, there is no such I/O interrupt pending and the OS need not be interrupted and the direct execution is permitted. The I/O interrupt processing is now explained. 
     (1) The I/O interrupt request from the I/O device is detected by the IOP 3000&#39; and the corresponding real sub-channel control block is queued in the corresponding real interruption priority order of the I/O interrupt request queue 2080 of the HSA 2001 (see FIG. 9), as is done in the prior art system. 
     (2) The IOP 3000&#39; shown in FIG. 22 sets the corresponding bit of the real interrupt pending register 1042&#39; to &#34;1&#34;, as is done in the prior art system. 
     (3) The real interruption priority order mask register 1041&#39; is set in the manner described before. The I/O interrupt circuit of FIG. 22 operates in the manner described above. Let us assume that the I/O interruption was started and the control was transferred to the I/O interrupt processing microprogram 1060&#39;. 
     (4) If the interruption occurs with the real dedicated interruption priority order of the VM, the VM can accept the interruption for the virtual interruption priority order because of the settings in the real interruption priority order mask register 1041&#39; and the real interruption priority order status register 1045. If the VM cannot accept the interruption, the I/O interruption cannot occur for that real interruption priority order by the actions of the I/O mask of the PSW 1020 and the registers 1041&#39; and 1045, and the control is not transferred to 1060&#39; but it is made pending by the hardware. 
     (5) The I/O interrupt microprogram 1060&#39; carries out the following processings. 
     (i) Dequeues the real sub-channel of the I/O interrupt request queue 2080 (FIG. 9) on the real interruption priority order c requested the interruption. 
     (ii) Checks the VM mode flag bit V and the high speed VM mode flag H of the VMS control flag 1090&#39; (FIG. 19), and if V=&#34;0&#34; or H=&#34;0&#34;, reflects the interruption to the PSA of the VMCP. The PXR 1010 of the VMCP (FIG. 12) is used and control is transferred to the VMCP. 
     (iii) If V=&#34;1&#34; and H=&#34;1&#34;, checks the I/O direct execution mode bit D of the VM. If D=&#34;0&#34;, it is not the I/O direct execution mode, and reflects the interruption to the PSA of the VMCP. 
     (iv) If D=&#34;1&#34;, the following processings are carried out. 
     (a) Whether the sub-channel is dedicated or not is determined by the status field (FIG. 16) in the real sub-channel control block, and if it is the shared sub-channel, reflects the interruption to the PSA of the VMCP. 
     (b) If the real interruption priority order c requesting the interruption is dedicated to the currently running VM, that is, if the corresponding bit of the real interruption priority order status register 1045 is &#34;0&#34; (see FIG. 21), reflects the interruption to the PSA of the currently VM to continue the current VM. The VM prefix register 1070 (FIG. 12) is used. The I/O interrupt information to the VM prefix is reflected by the virtual sub-channel number in the real sub-channel control block 2092&#39; or the virtual interruption priority number. 
     (c) When the real interruption priority order c is dedicated to another VM, the interruption is reflected to the VMCP. Then, the interruption is reflected to the PSA of the VM by the VMCP. 
     (d) When the real interruption priority order c is shared, the interruption is reflected to the VMCP. Then, the interruption is reflected to the VM by the VMCP. The VM may not accept the interruption. In such a case, the I/O interruption is held pending by the VMCP. 
     As described above when the sub-channel is dedicated and has the dedicated real interruption priority order, the I/O direct execution (without the intervention of the VMCP) of the OS on the VM is supported for that sub-channel. For the I/O interruption, only the I/O interruption from the sub-channel dedicated to the current running VM is directly executed. For the I/O interruption from the sub-channel dedicated to another VM, the VMCP is to intervene because of necessity for scheduling of the VM&#39;s. 
     The direct I/O execution mode suppress flag of the status field 2093 in the real sub-channel control block of FIG. 16 is normally &#34;0&#34; so that the direct I/O execution mode of that sub-channel is supported. In the dedicated sub-channel, the I/O instruction is not issued from the OS on the VM other than the occupying VM but it may be issued from the VMCP. In this case, the direct I/O execution mode suppress flag in the status field 2093 is set to &#34;1&#34; until the I/O of the VMCP is completed so that the I/O direct execution mode for that sub-channel is suppressed. 
     Accordingly, this flag is set and reset under the control of the VMCP. In the above I/O execution system, the following considerations are pointed out. 
     (a) The R bit of the VMS control flags 1090&#39; (FIG. 19) may be omitted. It is not necessary if the virtual sub-channel number and the virtual interruption priority order are always translated, or if those numbers are always equal when the direct I/O execution system of the present invention is applied in the VMS. 
     (b) The D flag may be replaced by the H flag, but the high speed VM mode flag H cannot control the direct execution of only the I/O instruction because it also controls the direct execution of the privileged instructions other than the I/O instruction. 
     (c) In the I/O interrupt processing, the I/O interruption from the real interruption priority order dedicated to the VM other than the currently running VM is reflected to the VMCP, as described above. Since the VM to which it is dedicated can accept the interruption, the interruption may be reflected to the PSA of that VM and then the control may be transferred to the VMCP in a form of VMCP call. The address of the PSA of the VM can be determined from the prefix management table of FIG. 13. In this case, it is necessary to determine the PSW of the VM and information therefor is required. It may be determined based on the VM number in various ways, although it is not illustrated. 
     (d) The start address of the sub-channel number translation table, the start address of the interruption priority order translation table, the real interruption priority order status register 1045 and the real interruption priority order dedication status register 1049 (FIG. 21) are all initialized by the operand of the start VM instruction (see FIG. 17). Alternatively, they may be initialized by a separate instruction of the VMCP. 
     As described hereinabove, in accordance with the present invention, the I/O instruction issued by the OS on the VM and the I/O instruction can be directly executed so that the I/O simulation overhead of the VMCP can be substantially reduced. This is an essential function to attain a virtual machine which has a performance very close to that of a real computer.