Abstract:
A switched capacitor MOS high-pass filter (10) includes a blocking capacitor (C 1 ) which accepts an input signal at one side (IN). A first electronic toggle switch (S 1 ) connects the gate of a depletion-mode buffer transistor (T 1 ) alternately to the other side of the blocking capacitor (C 1 ) and to ground in response to a pair of non-overlapping switching pulse trains (φ 1 ), (φ 2 ). A depletion-mode transistor (T 2 ) provides current to the buffer transistor (T 1 ). One side of an output capacitor (C 2 ) is connected to the source of the buffer transistor (T 1 ). A second toggle switch (S 2 ) connects the other side of the output capacitor (C 2 ) alternately to an output terminal (OUT) and to ground. 
     Also disclosed is a filter (14) which includes a correction network (18) to eliminate from the output signal the effect of a feed-through error voltage generated by the action of the first switch (S 1 ).

Description:
BACKGROUND OF THE INVENTION 
     The invention relates generally to frequency domain high-pass electronic filters and relates more particularly to precision switched capacitor filters for integrated circuits. 
     A known basic high-pass frequency domain filter is shown in FIG. 1. It includes a signal input terminal, a d.c. (direct current) blocking capacitor C, a resistor R, and a signal output terminal such as would typically be connected to the summing node of a negative feedback amplifier. The reference symbol C, as is used herein with different subscripts to identify particular capacitors, is also used to denote the capacitance value of that capacitor. 
     In very large scale integrated MOS (metal-oxide-silicon) circuits, it is generally not feasible to provide either a precision resistor for R or to provide a capacitor whose value tracks the inverse of the resistor value over variations in the manufacturing process. The resistor R can, however, be replaced by a capacitor C 2 , which is switched by a pair of break-before-make electronic toggle switches S 1 , S 2  operated by non-overlapping switching pulse trains φ 1 , φ 2  to result in the known switched capacitor filter structure of FIG. 2. The value of the capacitor C 2  corresponding to the resistance value of resistor R is 1/C 2  f s , where f s  is the frequency of the switching pulse trains. It is noted that larger C 1  capacitance values correspond to lower break frequencies for such a filter. The break frequency of a filter is that frequency associated with the knee of the transmission characteristic curve for that filter. 
     One problem with the switched capacitor filter structure of the type shown in FIG. 2 is that for a given capacitor value C 2 , as required for output drive, and a given switching pulse rate for the electronic switches S 1 , S 2 , a relatively large value is required for the capacitance C 1  in order to obtain relatively low break frequency capability. This is because a lower limit on the value of the capacitance C 2  is determined by the nature of the load circuitry. Large capacitance value elements require additional area on the integrated circuit chip. Furthermore, requiring the signal source to supply all of the current required to charge C 2  may also lead to significant additional cost. 
     Another problem relates to a parasitic capacitance C X , shown in phantom lines in FIG. 2, which is present on the switch S 1  side of the capacitance of C 2  in the prior art circuit. This additional switched capacitance is troublesome in that it is generally voltage-dependent, and introduces non-linear transmission loss which may be significant. 
     While a lower break frequency capability could also be obtained for the prior art structure by lowering the frequency of the switching pulses for the switches S 1 , S 2 , this would cause problems in realizing other circuit functions on the chip, assuming that it is the main clock frequency that is lowered; it might also create new antialiasing problems if the switching pulses represent a further count-down from the main clock. 
     SUMMARY OF THE INVENTION 
     The switched capacitor high-pass filter structure in accordance with the present invention includes a buffer means which makes it possible to obtain a given break frequency for given switching frequency and transadmittance capability with a relatively low input blocking capacitance value. The buffer also increases the input impedance and thereby reduces the stress on the input circuitry. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic circuit diagram of a prior art basic high-pass filter. 
     FIG. 2 is a schematic circuit diagram of a prior art switched capacitor version of the high-pass filter of FIG. 1. 
     FIG. 3 is a schematic circuit diagram of one example of a switched capacitor high-pass filter in accordance with the present invention. 
     FIG. 4 is a schematic circuit diagram of another example of a switched capacitor high-pass filter in accordance with the present invention and including an error correction branch. 
    
    
     DETAILED DESCRIPTION 
     The filter 10 of FIG. 3 includes a d.c. blocking capacitor C 1  receiving an input signal voltage from an input terminal IN. The other side of the blocking capacitor C 1  is connected through a switch S 1  operated at rate f s  to the gate electrode of an MOS buffer transistor T 1 . The drain of the buffer transistor T 1  is connected to a stable voltage supply V DD . The source of the buffer transistor T 1  is connected to a current source, shown as depletion-mode transistor T 2 , which in turn has its source and gate connected to a relatively negative voltage supply -V SS . An output capacitor C 2  is coupled at one side to the source of the buffer transistor T 1  and at its other side to an output terminal OUT 1  through a second switch S 2 . It is advantageous to make the source-follower transistor T 1  a depletion-mode device also, to avoid a substantial d.c. voltage level shift, which would reduce the signal range of linearity. 
     The switches S 1  and S 2  are single pole break-before-make toggle switches which may be configured readily in numerous ways with MOS FET (metal-oxide-silicon field effect transistor) devices and operated by separate switching pulse trains φ 1  and φ 2  which do not overlap. The switches S 1 , S 2  are shown in their φ 1  switching phase state in all the figures of the drawings. In the φ 2  phase condition they would be in their alternate state. 
     The switch S 1  connects the gate of the buffer transistor T 1  alternately to the blocking capacitor C 1  and signal ground. The second switch S 2  connects the output side of the capacitor C 2  alternately between the OUT 1  terminal and signal ground. 
     There is shown in phantom lines in FIG. 2 a capacitor C 3  which represents the gate-to-drain capacitance of the blocking transistor T 1  plus the parasitic capacitance of switch S 1 . It is a particularly advantageous feature of the filter 10 that the switched capacitance that determines the load resistance terminating C 1  can be limited to the relatively low value C 3 , resulting in a relatively high equivalent resistance value and either a relatively low break frequency or low C 1  value. 
     Also shown in phantom lines in FIG. 2 is a second output branch condition capacitor C 4  connected through a third toggle switch S 3  to an additional output terminal to illustrate that a plurality of outputs may be derived from the source of the buffer transistor T 1 , as desired, by providing additional capacitors and switch pairs. 
     While, of course, the specific values of the capacitors C 1 , C 2 , C 3 , C 4 , etc. for a particular application of the filter 10 must be appropriately chosen in view of the switching pulse rate and other considerations, the blocking capacitor C 1  is assumed to be large enough that its charge does not change appreciably over the period of the lowest signal frequency component that must be passed by the filter 10 in order for it to have a loss level as low as is needed above the break frequency. 
     MODE OF OPERATION 
     In the operation of the filter 10, the relatively small capacitance C 3  toggled between the output end of the relatively large input capacitance C 1  and the reference voltage (ground) slowly leaks away signal charge that resides on the right-hand plate of the input capacitor C 1 . Signal frequency components below a break frequency determined by the capacitance values C 1 , C 3  and the switching rate f s  are substantially shorted to ground. The toggle switch S 1  also serves as the left-hand toggle of the capacitors C 3  and C 4 . The first and second output branches would typically be expected to act as input resistors to amplifiers (not shown). The &#34;buffer&#34; transistor T 1 , which is a source follower large enough to be able to fully charge its load during the conducting time period of the switches S 1 , S 2 , transfers its gate voltage variations unattenuated to the left-hand terminals of the capacitors C 2  and C 4 . As a practical matter, the nonlinear parasitic capacitance C X  to ground from the node at which the source of the buffer transistor T 1  joins capacitor C 2  is immaterial, as is also the d.c. voltage level at that node, except for its effect on signal voltage range. The d.c. voltage level at the source of the buffer transistor T 1  has no material effect on output offset. 
     In the operation of the filter 10, the switching of the control voltage of the switch S 1  between its low and high logic levels results in a switching feed-through error, which is characteristic of MOS devices. In effect, it means that the voltage at the node 12 includes an error voltage V error  in the φ 1  phase, so that the node 12 voltage jumps from ground the settle to a value 
     
         C.sub.1 /C.sub.1 +C.sub.3 V.sub.signal +V.sub.error 
    
     in the φ 1  phase. In the φ 2  phase it jumps back to ground or 0 volts. While this error is very small, for some applications of the filter 10 it may be desirable to eliminate it. 
     Another example of a filter in accordance with the invention is the filter 14 of FIG. 4, which is a form of the filter 10 of FIG. 3 modified to include means for compensating in the output signal for the effect of the above-described feed-through error voltage V error . The modified filter 14 includes an upper, filter branch 16 and a lower, compensation branch 18, both enclosed by broken line rectangles. The filter branch 16 can be seen to be virtually identical to the filter 10 of FIG. 3, and is therefore shown with the same reference symbols as appeared for the corresponding elements in FIG. 3. The compensation branch 18 is similar to the filter branch 16 in its configuration and in the characteristics of its components, but has its IN terminal is connected to the OUT 1  terminal grounded. Its OUT&#39; 1  terminal of the filter branch 16. The circuit elements are identified by primed reference symbols of corresponding elements in the upper, filter branch 16. It is noted that the switching of the switch S&#39; 1  of the compensation branch 18 is substantially 180 degrees out of phase with the switching of S 1  of the filter branch 16. However, the same d.c. voltage error V error  is developed at node 20 as is developed at node 18. Since the gate of buffer transistor T&#39; 1  jumps from a voltage value V error  to ground in the φ 1  phase, the compensation branch 18 feeds to the output node only a switching feed-through correction charge which is opposite in sign to, but precisely the same magnitude as, the error charge (due to V error ) fed to the OUT 1  node of the filter branch 16 in the φ 1  phase. Since the outputs of the branches 16 and 18 are combined, this leads to a complete cancellation of the error in the OUT 1  terminal. 
     GENERAL CONSIDERATIONS 
     The current source for the buffer T 1  can be any of various current source configurations, such as for example, a current mirror configuration. 
     The function of the buffer transistor T 1  can be provided by a depletion or enhancement mode FET device or by an operational or other amplifier. In the case of the buffer transistor T 1 , the node 12 corresponds to a buffer input port and the source corresponds to a buffer output port. 
     The filter of FIG. 4 may also be provided with a plurality of OUT terminals in a manner similar to that discussed above with respect to the filter 10 of FIG. 3. 
     The capacitance C 3  may also include a relatively stable supplemental capacitance added by design to the gate-to-drain capacitance of transistor T 1  to obtain a filter with less amplitude distortion. 
     The term &#34;ground&#34; as used herein means a reference potential which is essentially constant. While in the FIGS. 2, 3, and 4 the same commonly used symbol is used to denote such a potential at various points in the circuits, it should be understood that the various such potentials for a given circuit need not necessarily be the same.