Abstract:
The multiplication circuitry of the present invention operates to generate multiple monolithic electrical currents, all referenced to a single external resistor. A first current referenced to a first monolithic resistor, a second current referenced to a second monolithic resistor, and a third current referenced to an external resistor are used to generate an output current, which is also referenced to the external resistor. The present invention accurately generates two currents each being referenced to the single external resistor, while simultaneously minimizing the number of external connections and overall cost of producing the circuitry.

Description:
FIELD OF THE INVENTION 
     The present invention relates to accurately controlling the current in an integrated circuit, and more specifically relates to generating multiple monolithic electrical currents, all referenced to a single accurate resistor. 
     BACKGROUND OF THE INVENTION 
     As the need to reduce current in transceiver products and other integrated circuits increases, the need to more accurately control this current also increases. Typically, a design for an integrated circuit requires two currents: a current proportional to absolute temperature (IPTAT) and a bias current, which is defined herein as a current independent of temperature (IBIAS). In general, these currents are generated by placing an accurate on-chip voltage, such as a bandgap voltage or a thermal voltage, across a monolithic resistor. A monolithic resistor, also referred to as an internal resistor, is a resistor manufactured on the same semiconductor die as the associated integrated circuit. These electrical currents IPTAT and IBIAS are then provided to a current mirror, where the currents are mirrored as many times as necessary throughout the circuit. 
     Monolithic resistors typically have tolerances ranging from ±15% to ±25% at room temperature. In addition, the tolerance of monolithic resistors may vary an additional 5% to 25% across reasonable temperatures depending on resistor type and processing. Therefore, when the currents IPTAT and IBIAS are generated based on the resistance values of monolithic resistors, these currents may vary 35% or more. 
     In order to more accurately produce the currents IPTAT and IBIAS, accurate external or off-chip resistors have been used in place of the monolithic or on-chip resistors. The external resistors may have tolerances as low as 1%, thereby greatly increasing the accuracy of the currents IPTAT and IBIAS from 35% or more down to the accuracy of the on-chip voltage. Typically, multiple off-chip resistors are required to generate the currents IPTAT and IBIAS. However, the external resistors require additional pins to be added to the semiconductor die and increase the number of components, thereby increasing the cost of manufacturing the associated integrated circuit. 
     Therefore, there remains a need for a circuit and method for generating multiple monolithic electrical currents all referenced to a single external resistor. 
     SUMMARY OF THE INVENTION 
     The multiplication circuitry of the present invention operates to generate multiple monolithic electrical currents, all referenced to a single external resistor. A first current referenced to a first monolithic resistor, a second current referenced to a second monolithic resistor, and a third current referenced to an external resistor are used to generate an output current, which is also referenced to the external resistor. The present invention accurately generates two currents each being referenced to the single external resistor, while simultaneously minimizing the number of external connections and overall cost of producing the circuitry. 
     In an exemplary embodiment, a first current proportional to absolute temperature (IPTAT INT ) referenced to the first monolithic resistor, a first current independent of temperature (IBIAS INT ) referenced to the second monolithic resistor, and a second current independent of temperature (IBIAS EXT ) referenced to the external resistor are used to generate the output current. The output current is a second current proportional to absolute temperature (IPTAT EXT ), which is also referenced to the external resistor. 
     In one implementation of the exemplary embodiment, the multiplication circuitry of the present invention generates the second current proportional to absolute temperature (IBIAS EXT ) by multiplying the first current proportional to absolute temperature (IBIAS INT ) by a ratio of the second current independent of temperature (IBIAS EXT ) to the first current independent of temperature (IBIAS INT ). The multiplication circuitry may be biased by feedback circuitry such that the multiplication circuitry is held out of saturation. Further, the feedback circuitry may be configured to reduce the gain associated with the multiplication circuitry. 
     Those skilled in the art will appreciate the scope of the present invention and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING FIGURES 
     The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the invention, and together with the description serve to explain the principles of the invention. 
     FIG. 1 illustrates a general block diagram of a system for generating multiple currents from one reference resistor according to one embodiment of the present invention: 
     FIG. 2 illustrates an exemplary embodiment of the system illustrated in FIG.  1 . 
     FIG. 3 illustrates a circuit for generating a current proportional to absolute temperature according to one embodiment of the present invention; 
     FIG. 4 illustrates a circuit for generating a current independent of temperature according to one embodiment of the present invention; 
     FIG. 5 illustrates a current multiplication circuit according to one embodiment of the present invention; and 
     FIG. 6 illustrates one implementation of a current multiplication circuit according to one embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the invention and illustrate the best mode of practicing the invention. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the invention and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
     FIG. 1 illustrates a basic block diagram of a system  10  for generating multiple currents referenced to a single accurate resistor according to the present invention. A single semiconductor die  12  includes a first circuit  14 , a second circuit  16   INT , and a third circuit  16   EXT , internal resistors R 1INT  and R 2INT , and multiplication circuitry  18 . In addition to the semiconductor die  12 , the system  10  includes an external resistor R 2EXT . The first circuit  14  generates a first current (I 1 ) based on the first internal resistor R 1INT , the second circuit  16   INT  generates a second current (I 2 ) based on the second internal resistor R 2INT , and the third circuit  16   EXT  generates a third current (I 2 ) based on the external resistor R 2EXT . The first current I 1  is a first type of current, such as a current proportional to absolute temperature or a current inversely proportional to absolute temperature. The second current I 2  and the third current I 3  are a second type of current, such as a current independent of temperature. In general, the multiplication circuitry  18  produces a fourth current (I 4 ) that is referenced to the external resistor R 2EXT  based on the currents I 1 , I 2 , and I 3 , where the fourth current I 4  is the same type of current as the first current I 1 . Therefore, the system  10  produces the third current I 3  and the fourth current I 4 , each referenced to the single accurate external resistor R 2EXT . 
     FIGS. 2-6 illustrate an exemplary embodiment of the system  10 . In this embodiment, the semiconductor die  12  includes an IPTAT circuit  20 , a first IBIAS circuit  22   INT , and a second IBIAS circuit  22   EXT , the internal resistors R 1INT  and R 2INT , and the multiplication circuitry  18 . In addition to the semiconductor die  12 , the system  10  includes the external resistor R 2EXT . The IPTAT circuit  20  generates a first current proportional to absolute temperature (IPTAT INT ) based on the first internal resistor R 1INT , the first IBIAS circuit  22   INT  generates a first current independent of temperature (IBIAS INT ) based on the second internal resistor R 2INT , and the second IBIAS circuit  22   EXT  generates a second current independent of temperature (IBIAS EXT ) based on the external resistor R 2EXT . In general, the multiplication circuitry  18  produces a second current proportional to absolute temperature (IPTAT EXT ) that is referenced to the external resistor R 2EXT  based on the currents IPTAT INT , IBIAS INT , and IBIAS EXT . Therefore, the system  10  produces the currents IPTAT EXT  and IBIAS EXT  referenced to the single accurate external resistor R 2EXT    
     FIG. 3 illustrates the IPTAT circuit  20  in more detail. The IPTAT circuit  20  includes transistors M 1 , M 2 , M 3 , Q 1 , and Q 2 , and a start-up circuit  24 . As illustrated in FIG. 1, the IPTAT circuit  20  is coupled to an internal resistor R 1INT . To begin conducting current through the transistors M 1 , M 2 , M 3 , Q 1 , and Q 2 , the start-up circuit  24  briefly operates to create a small current through transistors M 1  and Q 1 . This current is mirrored through transistors M 2  and Q 2 . In this example, transistor Q 2  has an emitter size (AREA=8) that is eight times larger than the emitter size of transistor Q 1  (AREA=1). Therefore, a voltage V is created across resistor R 1INT  that is defined as: 
     
       
           V=V   T  *ln  (8)  
       
     
     where the term ln(8) is the natural log of the ratio of the current density of transistor Q 2  to the current density of the transistor Q 1  and the current densities are directly proportional to the emitter areas of the transistors Q 1  and Q 2 . Further, V T  is the thermal voltage defined by the equation: 
     
       
         
           V 
           T 
           =kT/q,  
         
       
     
     where k is Boltzman&#39;s Constant, T is absolute temperature, and q is the charge of an electron. From this equation, it is seen that the voltage V T  and, therefore, the voltage V are proportional to the absolute temperature T. 
     Once the voltage V is created across resistor R 1INT , the current through transistors M 2  and Q 2  is mirrored through transistor M 3  and defined by the equation:          IPTAT   INT     =           V   T     *     ln        (   8   )           R     1      INT         .                            
     Hence, the IPTAT circuit  20  produces the current IPTAT INT , which is proportional to the voltage V T  and, therefore, to the absolute temperature T. Notably, the current IPTAT INT  is also inversely proportional to the resistance of the resistor R 1INT . 
     FIG. 4 illustrates in more detail the IBIAS circuits  22   INT  and  22   EXT  for generating the currents independent of temperature IBIAS INT  and IBIAS EXT . It is important to note that FIG. 4 is a general illustration of both the IBIAS circuits  22   INT and 22   EXT , wherein resistor R 2INT  is internal to the semiconductor die  12  and resistor R 2EXT  is external to the semiconductor die  12  as illustrated in FIG.  2 . The IBIAS circuit  22  includes an operational amplifier  26  having an inverting input (−) operatively connected to a bandgap circuit  28 . The bandgap circuit  28  provides a stable bandgap voltage V BG , which is independent of temperature. The operational amplifier  26  operates to control the voltage at a non-inverting input (+) such that the voltages at both the inverting (−) and non-inverting (+) inputs are equal. Therefore, the IBIAS circuit  22  generates the bandgap voltage V BG  across a resistor R 2 , thereby producing a current defined as V BG /R 2  through the resistor R 2  and a transistor M 4 . The IBIAS circuit  22  mirrors the current defined as V BG /R 2  through a transistor M 5  in order to provide the current IBIAS; and since the bandgap voltage V BG  is independent of temperature, the current IBIAS is also independent of temperature. 
     FIG. 5 illustrates one embodiment of the multiplication circuitry  18 , which includes transistors Q 3 , Q 4 , Q 5 , and Q 6  interconnected as shown. Although this description of the multiplication circuitry  18  is given with respect to the currents IPTAT INT , IBIAS INT , IBIAS EXT , and IPTAT EXT , it is to be recognized that this description also applies to the currents I 1 , I 2 , I 3 , and I 4  illustrated in FIG.  1 . Current IPTAT INT  is a current proportional to absolute temperature generated by a circuit such as the IPTAT circuit  20 , where the current IPTAT INT  is referenced to an internal resistor. Current IBIAS INT  is a current independent of temperature generated by a circuit such as the first IBIAS circuit  22   INT  where the current IBIAS INT  is referenced to an internal resistor, and current IBIAS EXT  is a current independent of temperature generated by a circuit such as the second IBIAS circuit  22   EXT  where the current IBIAS EXT  is referenced to an external resistor. 
     The operation of the multiplication circuitry  18  can best be described mathematically by the following loop equation: 
     
       
           V   BE3   −V   BE6   +V   BE5   −V   BE4 =0,  
       
     
     where V BE3  is a voltage measured across the base to emitter of the transistor Q 3 , V BE4  is a voltage measured across the base to emitter of the transistor Q 4 , V BE5  is a voltage measured across the base to emitter of the transistor Q 5 , and V BE6  is a voltage measured across the base to emitter of the transistor Q 6 . 
     By replacing the base emitter voltages with the forward biased diode current equation, the above loop equation becomes:              V   T     *     ln        (       IPTAT   INT       I   S       )         -       V   T     *     ln        (       IBIAS   INT       I   S       )         +       V   T     *     ln        (       IBIAS   EXT       I   S       )         -       V   T     *     ln        (       IPTAT   EXT       I   S       )           =   0.                          
     After simplification, the loop equation becomes:            ln        (       (       IPTAT   INT     *     IBIAS   EXT       )       (       IPTAT   EXT     *     IBIAS   INT       )       )       =   0     ,                          
     which further simplifies to:          IPTAT   EXT     =       IPTAT   INT     *         IBIAS   EXT       IBIAS   INT       .                              
     In operation, the multiplication circuitry  18  produces the current IPTAT EXT , defined as a current proportional to absolute temperature generated based on an external resistor. More importantly, the multiplication circuitry  18  generates the currents IPTAT EXT  and IBIAS EXT  referenced to only one external resistor, thereby accurately producing these currents using a minimal number of external connections and minimizing the cost of manufacturing the circuit. 
     FIG. 6 illustrates a practical implementation of the multiplication circuitry  18 , wherein additional circuitry is used to bias the transistors Q 3 , Q 4 , Q 5 , and Q 6 . In this implementation, biasing of transistors Q 5  and Q 06  is accomplished by diode connecting each of the transistors Q 5  and Q 6 . In order to diode connect each of the transistors Q 5  and Q 6 , the base of transistor Q 5  is connected to the collector of transistor Q 5 , and the base of transistor Q 6  is connected to the collector of transistor  06 . 
     Transistors Q 7 , Q 8 , and Q 9 , resistors R 3  and R 4 , and capacitor C form a feedback loop used to bias transistor Q 3 . The feedback loop operates to control the base of transistor Q 7  in order to hold transistor Q 3  out of saturation. Transistor Q 8  acts on the base of transistor Q 7  as an emitter follower and level shifter. Resistor R 3  biases transistor Q 8 , and resistor R 4  reduces the loop gain to improve stability. Very little loop gain is necessary, since the absolute voltage at the collector of transistor Q 3  is not critical. Therefore, resistor R 4  may be biased such that the voltage across resistor R 4  is in the range of 50 millivolts to 100 millivolts. Transistor Q 9  acts as a level shifter to keep transistor Q 7  out of saturation, and capacitor C is a compensation capacitor used to stabilize the feedback loop. 
     In operation, the IPTAT circuit  20 , the first IBIAS circuit  22   INT , and the second IBIAS circuit  22   EXT  generate the currents IPTAT EXT , IBIAS INT , and IBIAS EXT  based on resistors R 1INT , R 2INT , and R 2EXT , respectively. The multiplication circuitry  18  operates as described above with respect to FIG. 5, and generates the current IPTAT EXT  referenced to external resistor R 2EXT  based on the currents IPTAT EXT , IBIAS INT , and IBIAS EXT . When implementing the present invention in an integrated circuit, the current IPTAT EXT  may be fed to a current mirror circuit in order to provide the current to the entire integrated circuit. The details of current mirror circuits will vary and are commonly known in the art. 
     Using the present invention, the current IPTAT EXT  varies less than 1% due to the ±25% tolerances of the remaining monolithic resistors, and less than 2% as temperature varies from −40° C. to +85° C. Further, the current IPTAT EXT  varies less than 4% when V cc  is swept from 2.7 volts to 3.6 volts and varies less than 2% when the collector of the transistor Q 4  is properly cascoded to match the collector voltages of the transistors Q 3 , Q 5 , and Q 6 . The variation of IPTAT EXT  may be further reduced by increasing the channel lengths of transistors M 1 , M 2 , M 3 , M 4 , and M 5 . Once these steps have been taken to decrease the variation in the current IPTAT EXT , the most significant source of variation remaining is the variation in the bandgap voltage V BG  produced by the bandgap circuit  28 . 
     The IPTAT circuit  20 , the IBIAS circuit  22 , and the implementation of the current multiplication circuit  18  offer substantial opportunity for variation without departing from the spirit and scope of the invention. For example, there are numerous circuits that could be used to produce a current proportional to absolute temperature and a current independent of temperature. The importance of the IPTAT circuit  20  and the IBIAS circuit  22  is to illustrate that resistors R 1  and R 2  are used as references to produce the currents IPTAT and IBIAS. Further, the implementation of the current multiplication circuit  18  illustrated in FIG. 6 is only one example of a circuit which biases transistors Q 3 , Q 4 , Q 5 , and Q 6 , such that the current multiplication circuit  18  operates properly. As another example, transistors Q 7  and Q 8  are illustrated as bipolar junction transistors. However, transistor Q 7  may be replaced by an n-type field effect transistor so that resistor R 4 , which is used for degeneration, is not necessary. Further, transistor Q 8  may be replaced by an n-type field effect transistor so that its base current does not interfere with the operation of the multiplication circuit  18 . 
     The foregoing details should, in all respects, be considered as exemplary rather than as limiting. The present invention allows significant flexibility in terms of implementation and operation. Examples of such variation are discussed in some detail above; however, such examples should not be construed as limiting the range of variations falling within the scope of the present invention. The scope of the present invention is limited only by the claims appended hereto, and all embodiments falling within the meaning and equivalency of those claims are embraced herein.