Abstract:
An inductor-capacitor voltage controlled oscillator is implemented using an active inductor. The active inductor may use bipolar technology or CMOS technology. The VCO with an active inductor offers a more compact design and is useable with flip chip technology. The active inductor may be implemented in bipolar junction or complementary metal oxide semiconductor technology. The configuration of the voltage controlled oscillator with an active inductor of the present invention is fully differential and fully symmetric.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention generally relates to the field of voltage controlled oscillators, and particularly to inductor-capacitor (LC) voltage controlled oscillators.  
       BACKGROUND OF THE INVENTION  
       [0002]     Voltage controlled oscillators (VCOs) are very useful components for a wide variety of integrated circuit applications. Voltage controlled oscillators (VCO) may be implemented using a parallel combination of a passive inductance (L) and a passive capacitance (C). The voltage and current for an inductor are related as V=L di/dt. For a capacitor, the relationship of current and voltage is i=C dV/dt or V=1/C ∫ i dt. Applying Kirchoff&#39;s voltage law for the parallel combination of an inductor and capacitor, L di/dt=1/C ∫i dt. The relationship of voltage and current between the parallel inductor and capacitor may be rearranged and differentiated such that L d 2 i/d 2 t−1/C i. A solution to this equation is i=i 0  sin ω, where ω=1{square root}LC. Thus, a sinusoidal timing signal may be generated by the VCO at an operating frequency of f=½π 1/{square root}LC.  
         [0003]     Thus far, LC VCOs have been limited to wirebond designs. Flip chip designs, which use conductive bumps to make electrical connections, offer smaller sizes, improved performance, and lower cost, as well as flexibility and reliability, when compared to wirebond. The use of an LC VCO in a silicon flip chip design is hampered by the need to synthesize the L with a spiral inductor and the lack of tunability. VCO configurations with spiral inductors consume a large amount of silicon area, can have poor performance when used in flip chip applications, have a low quality factor, and may interact with adjacent metal layers and flip chip underfill material. Wirebond is not suitable for high speed, high density IO that are commonly found on Application Specific Integrated Circuits (ASICs).  
         [0004]     Therefore, it would be desirable to reduce the size of a voltage controlled oscillator by replacing the passive inductor with an active inductor.  
       SUMMARY OF THE INVENTION  
       [0005]     Accordingly, the present invention is directed to a voltage controlled oscillator that uses an active inductor. By using an inductor synthesized through the use of an active circuit and placing the circuit in the VCO, the advantages of an LC VCO are maintained while the disadvantages associated with a spiral inductor are eliminated.  
         [0006]     In a first aspect of the present invention, a voltage controlled oscillator includes an active inductor and a capacitance. The active inductor and capacitance establish a frequency of a timing signal output by the voltage controlled oscillator.  
         [0007]     In a second aspect of the present invention, a method is provided for generating a timing signal using an active inductor in an inductor-capacitor voltage controller oscillator. In the method, the ends of a capacitor electrically connected in parallel with the active inductor are alternately charged and discharged. A differential voltage is generated across the active inductor in response to the charging and discharging of the capacitor, thus simulating inductor behavior.  
         [0008]     The active inductor of the present invention offers several advantages. It is more compact since no spiral inductor is used. The VCO with the active inductor easily achieves the metallization design rules and so reduces or eliminates cross contamination and does not rely on the quality of passive components. The voltage controlled oscillator may be tuned by adjusting either the capacitor or the inductor. The phase noise is superior to that of ring oscillator implementations. The present invention may be implemented in flip chip or wirebond applications and may use a bipolar or CMOS active inductor.  
         [0009]     It is to be understood that both the forgoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]     The numerous advantages of the present invention may be better understood by those skilled in the art by reference to the accompanying figures in which:  
         [0011]      FIG. 1  shows an LC voltage controlled oscillator of the present invention;  
         [0012]      FIG. 2  shows an alternate embodiment of the general circuit of the present invention;  
         [0013]      FIG. 3  shows an active inductor formed using bipolar technology;  
         [0014]      FIG. 4  shows the incorporation of a bipolar active inductor into a complementary metal oxide semiconductor (CMOS) voltage controlled oscillator;  
         [0015]      FIG. 5  shows an active inductor formed using CMOS technology;  
         [0016]      FIG. 6  shows a CMOS active inductor incorporated into a CMOS VCO; and  
         [0017]      FIG. 7  shows a flow chart of an embodiment of a method of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0018]     Reference will now be made in detail to the presently preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings.  
         [0019]     The present invention relates to a voltage controlled oscillator that generates a timing signal from the parallel combination of a capacitor and an active inductor. The active inductor may be implemented in bipolar junction or metal oxide semiconductor technology. The configuration of the voltage controlled oscillator with an active inductor of the present invention is fully differential and fully symmetric. The voltage controlled oscillator may be used in flip chip or wirebond applications.  
         [0020]      FIG. 1  shows an embodiment of a circuit of the present invention. The active inductor and the capacitor C 1  are electrically connected in parallel such that the voltage across the capacitor is the same as the voltage across the inductor. The parallel combination of the inductance and capacitance C 1  from a parallel resonant circuit. In a parallel resonant circuit, the voltage across the capacitor and inductor are the same; however, a time varying current alternately flows from the inductor to the capacitor. The frequency of the oscillation of the current is set by the values of L and C. The devices P 1 , P 2 , N 1 , and N 2  provide current into the parallel resonant circuit to start and sustain the oscillation. Because voltage across the inductor is directly proportional to the change in current over time through the inductor, the inductor current is constantly changing in a manner consistent with the voltage present across the capacitor C 1 , resulting in a time varying, sinusoidal waveform. Negative charge is supplied to the capacitor C 1  alternately through PMOS transistors P 1  and P 2 . When the voltage at node B is sufficiently low, transistor P 1  is turned ON and NMOS transistor N 1  is turned OFF such that charge flows to node A of the capacitor C 1 . During this time, transistor P 2  is turned OFF and transistor N 2  is turned ON to discharge the node B end of capacitor C 1 . Node A, initially positive, becomes increasing negative because of the time varying current flow through the impedance of the parallel resonant circuit. During the other half of the cycle, node B becomes sufficiently positive to turn OFF transistor P 1  and turn ON transistor N 1 . A sinusoidal waveform results at nodes A and B.  
         [0021]      FIG. 2  shows an alternate embodiment of a circuit of the present invention. Two active inductors are formed. The capacitance is represented by capacitances C 2  and C 3 . An optional element or connection may be electrically connected to the nodes of the inductors and the capacitors. The optional element or connection may be a circuit ground or a simple connection to the two nodes to form one node. In the case where the simple connection forms a single node, the single node may be tied to circuit ground or a power supply through a passive or active component. For instance, a passive element may be a resistor or capacitor. Other arrangements are possible. For example, the active inductor may be effectively undivided whereas the capacitance may be formed of two capacitors. The two capacitors may be tied to circuit ground directly or through a passive component or may be tied to a power supply through a passive component. Additionally or alternatively, a resistor may be electrically connected in parallel with each capacitor. As another example, the active inductor may be divided, whereas the capacitor is undivided. Because the voltage controlled oscillator is supplied power by a power supply, any resistive losses do not dampen the oscillation.  
         [0022]      FIG. 3  shows an active inductor formed by a bipolar transistor BT 2  and an emitter resistor. Node Zin is formed at the electrical junction of the emitter of transistor BT 2  and resistor R 2 . A control voltage at the base of transistor BT 2  synthesizes the inductance at node Zin. The inductance is directly proportional the transistors internal capacitance and is inversely proportional to the transistor beta. Two of the bipolar inductors are electrically connected through their base electrodes to form a bipolar active inductor.  
         [0023]      FIG. 4  shows an embodiment of the VCO in which a bipolar active inductor used in a fully differential widely tunable CMOS voltage controlled oscillator. Bipolar transistors BT 1  and BT 2  form a differential pair and should be identical or as closely matched as possible. For a constant current condition at nodes A and B, the voltage across the two nodal points is approximately zero volts. A change in current at either node A or B is transferred to the other node after a time delay. During the time delay, a potential difference exists across nodes A and B, simulating inductor behavior.  
         [0024]      FIG. 5  shows an embodiment of an active inductor using CMOS technology. Although transistors Q 4 , Q 5 , and Q 6  are shown as NMOS transistors, PMOS transistors may be used instead. Current sources CS 3  and CS 4  are used to illustrate the current flow paths in the active inductor. The resistor R 4  limits the flow of charge to and from the gate electrode of transistor Q 6 . Because the gate voltage of transistor Q 6  is always higher than the source voltage, transistor Q 6  is always turned on to permit current flow from the drain to the source. The combination of Q 6  and R 4  will result in an inductance provided that R 4  is greater than the transconductance of Q 6 . If R 4  is less than the transconductance of Q 6 , then the circuit appears capacitive. The presence of transistors Q 4  and Q 5  act to reduce the effective transconductance of Q 6 , and the control voltage VCONTROL affects the change in transconductance that Q 4  and Q 5  apply to Q 6 . This increases the range of operating conditions over which the circuit will appear inductive. The inductance is approximated as being proportional to the gate-source capacitance of transistor Q 5  multiplied by R 4  and the effective transconductance of Q 4 .  
         [0025]      FIG. 6  shows an embodiment of a voltage controlled oscillator in which two of the inductors of  FIG. 5  are joined together in a differential arrangement through the electrical connection of the gate electrodes of transistors Q 3  and Q 5 . When there is no change in either nodal voltage, there is no voltage differential across the active inductor.  
         [0026]      FIG. 7  shows a flow chart for an embodiment of the method of the present invention. One end of the active inductor—capacitor parallel combination is charged  710 . The charging causes a difference in potential across the inductor, approximating the behavior of an inductor or coil. That same end is then discharged  720  which cases a potential of the opposite polarity to form across the active inductor. The opposite end is charged  730  and discharged  740 , causing the development of potentials across the active inductor. In the preferred embodiment, steps  710  and  740  occur simultaneously or nearly so and steps  720  and  730  are essentially synchronized such that steps  710  and  740  are alternately performed with steps  720  and  730 .  
         [0027]     It is believed that the present invention and many of its attendant advantages will be understood by the forgoing description. It is also believed that it will be apparent that various changes may be made in the form, construction and arrangement of the components thereof without departing from the scope and spirit of the invention or without sacrificing all of its material advantages, the form hereinbefore described being merely an explanatory embodiment thereof. It is the intention of the following claims to encompass and include such changes.