Abstract:
This invention relates to a method of estimating the signal delay in a VLSI circuit and accurately estimating the delay and conversion time of a transmission signal in the circuit in order to prevent a designer of the VLSI circuit from erroneously judging the logic made by the designed circuit.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    This invention relates to a method of estimating the signal delay in a VLSI circuit and particularly to a method of feasibly fast calculating the delay and conversion time of a transmission signal in the VLSI circuit in order to prevent the erroneous logic judgment of a circuit design. 
         [0003]    2. Description of Related Art 
         [0004]    In U.S. Pat. No. 5,845,223 as a conventional technology, a method of estimating the signal delay in an interconnection circuit by fixing the structure, number of components, and capacitance function of an interconnection network was proposed, but the technology could not be widely used in the structures of different interconnection networks. 
         [0005]    In U.S. Pat. No. 0,102,933 as a conventional technology that broke through the limit to the structure of fixed interconnection network, a method of feasibly estimating the transmission signal delay caused by components in two circuits was proposed, but it could not be used for calculating the total signal delay from input to output in a VLSI circuit. 
         [0006]    Consequently, because of the technical defects of described above, the applicant keeps on carving unflaggingly through wholehearted experience and research to develop the present invention, which can effectively improve the defects described above. 
       SUMMARY OF THE INVENTION 
       [0007]    This invention relates to a method of estimating the signal delay in a VLSI circuit and accurately estimating the delay and conversion time of a transmission signal in the circuit in order to prevent a designer of the VLSI circuit from erroneously judging the logic made by the designed circuit. 
         [0008]    In a process of the algorithm of clock signal delay that is proposed in this invention, at first, calculation of the parasitic parameters, signal conversion time, logic cell library, and circuit architecture in an inputted file-based interconnection circuit is made for the voltage moment at each node and the current moment in a branch line of the specified interconnection circuit, and what is obtained is applied to a reduced model for forming die original circuit, in which the reduced model retains passivity and stability and the operation conditions of its input and output nodes are identical to those of the original system; finally, a signal time domain is simulated and then the equivalent capacitance is calculated so that drive logic gate delay time, interconnection circuit delay time, and output signal conversion time are analyzed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  is a flow chart of this invention; 
           [0010]      FIG. 2  is a flow chart of a technique of recursion moment operation of this invention; 
           [0011]      FIG. 3  is a flow chart of a technique of model reduction; 
           [0012]      FIG. 4  is a flow chart of time domain simulation; 
           [0013]      FIG. 5  is a flow chart of calculation of equivalent capacitance; 
           [0014]      FIG. 6   a  is a view of an original RC circuit; 
           [0015]      FIG. 6   b  is a view of a structured equivalent model; 
           [0016]      FIG. 6   c  is a view of an equivalent circuit; and 
           [0017]      FIG. 7  is a view of the validity of an algorithm proposed in this invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0018]    Now, the present invention will be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only; it is not intended to be exhaustive or to be limited to the precise form disclosed. 
         [0019]    A method of estimating the signal delay in a VLSI circuit is provided in this invention, as shown in  FIG. 1 , in which at the step of Start, a file interconnect circuit parasitic parameter, signal conversion time, logic cell library, and a circuit structure are inputted to a file data read system. 
         [0020]    For each network interconnection system, the structure of a specific target interconnection circuit is analyzed and the system moment of the specified system is calculated, in which the calculation of moment is made for voltage moment of each node and current moment of a branch line, which may be applied to the calculation of equivalent capacitance and the construction of projection matrix. In recursion moment operation, the circuit moment of each node in the circuit may be obtained in linear time, and thus the projection matrix is further constructed. 
         [0021]    In the process of construction of the reduced model, it is determined whether the amount of nodes in the specified system is higher than a default order. When the specified order exceeds, the system is significantly complicated, and due to the special structure of a tree network, this invention may be applied to a sparse matrix to store the circuit parameter of original system, which significantly reduces the resource of operation. Sparse matrix multiplication is applied to obtain a final reduced model for analysis of the signal time domain simulation. The reduced model stays passive and stable, and the operation condition of its input and output node is identical to that of original system. 
         [0022]    Contrarily, when the order of target interconnect circuit is less than a default order, a Modified Nodal Analysis matrix system is constructed directly corresponding to a Modified Nodal Analysis matrix system that may represent its current and voltage behavior pattern for analysis of the time domain simulation. 
         [0023]    At the step of analysis of the time domain simulation, the equivalent capacitance loaded by a drive element is first calculated, and table look-up is applied to get an output signal of an input interconnect circuit structure. 
         [0024]    By means of analysis of the time domain simulation, the time domain simulation is made for the Modified Nodal Analysis matrix system and then off analyzed for drive logic gate delay time, interconnection circuit delay time, and output signal conversion time. 
         [0025]    Determination is made whether a network interconnection system has not yet been processed, and if a system has not yet been processed, the step of determining the interconnect circuit structure returns for analysis of a next interconnect circuit signal, or all of the interconnect circuits has been off processed, end of estimation of the system delay of this invention takes place. 
         [0026]    The algorithm applied to this invention comprises the techniques of moment calculation, model reduction, recursion moment operation, time domain analysis, and equivalent capacitance operation, which will be described in detail. 
       Moment Calculation 
       [0027]    As shown in  FIG. 2  illustrates a flow of calculation of voltage moment of each node and current moment of each branch line, at the step of Start, calculation must be done for the voltage moment and the current moment. For a RC interconnect circuit, a tree connection structure may be formed, in which each branch is resistance and each node is ground capacitance, both of which are calculated for the (voltage and current) moment by means of the recursion algorithm. 
         [0028]    In this invention, calculation is done from the default order for the voltage moment of each node, and O(kn) the complexity of operation, in which k is the order of reduced system and n is the number of node, making the moment calculation (flow) end. 
       Recursion Moment Operation 
       [0029]    In the technique of model reduction, the Arnoldi iteration algorithm and PVL iteration algorithm are conventionally used to construct the projection matrix. Matrix multiplication is included in the iteration process, so the complexity of operation of a large system increases. In  FIG. 2  according to this invention, the recursion algorithm is applied for moment calculation in order to speed up the execution of a program. The formula of the current and voltage moment between the nodes that is given for moment by means of the recursion algorithm may be expressed as: 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     
                       j 
                       , 
                       k 
                     
                   
                   = 
                   
                     
                       
                         I 
                         
                           C 
                           
                             j 
                             , 
                             k 
                           
                         
                       
                       - 
                       
                         
                           ∑ 
                           
                             
                               n 
                               x 
                               i 
                             
                             ∈ 
                             
                               S 
                                
                               
                                 ( 
                                 
                                   n 
                                   j 
                                   i 
                                 
                                 ) 
                               
                             
                           
                         
                          
                         
                           
                             I 
                             
                               x 
                               , 
                               k 
                             
                           
                            
                           
                               
                           
                            
                           and 
                            
                           
                               
                           
                            
                           
                             V 
                             
                               j 
                               , 
                               k 
                             
                           
                         
                       
                     
                     = 
                     
                       
                         V 
                         
                           
                             F 
                              
                             
                               ( 
                               j 
                               ) 
                             
                           
                           , 
                           k 
                         
                       
                       - 
                       
                         
                           R 
                           j 
                         
                          
                         
                           I 
                           
                             j 
                             , 
                             k 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0030]    where I j,k  indicates the moment of current j in order k, I C     j,k    is the capacitive current related to node j, 
         [0000]    
       
         
           
             
               ∑ 
               
                 
                   n 
                   x 
                   i 
                 
                 ∈ 
                 
                   S 
                    
                   
                     ( 
                     
                       n 
                       j 
                       i 
                     
                     ) 
                   
                 
               
             
              
             
               I 
               
                 x 
                 , 
                 k 
               
             
           
         
       
     
         [0000]    is the total of the moment of current flowing out of node j, V j,k  is the moment at node j in order k, and V F(j),k  is the moment of voltage at a father node of node j. 
       Model Reduction 
       [0031]    The model order of the interconnect VLSI circuit is quite huge, and in order to reduce the complexity of system operation, the technique of model reduction is applied for a next step of simulation and analysis, in which the flow of model reduction is shown in  FIG. 3 . 
         [0032]    First, regarding the analysis of interconnect circuit, Kirchhoff&#39;s current law is applied to give the following equation; 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         ( 
                         
                           
                             s 
                              
                             
                               
                                 
                                   [ 
                                   
                                     
                                       
                                         
                                           C 
                                           1 
                                         
                                       
                                       
                                         0 
                                       
                                     
                                     
                                       
                                         0 
                                       
                                       
                                         
                                           C 
                                           2 
                                         
                                       
                                     
                                   
                                   ] 
                                 
                                  
                               
                               M 
                             
                           
                           + 
                           
                             
                               
                                 [ 
                                 
                                   
                                     
                                       
                                         G 
                                         1 
                                       
                                     
                                     
                                       
                                         - 
                                         
                                           G 
                                           1 
                                         
                                       
                                     
                                   
                                   
                                     
                                       
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                         ) 
                       
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                             [ 
                             
                               
                                 
                                   
                                     
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                                       1 
                                     
                                      
                                     
                                       ( 
                                       s 
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                                       2 
                                     
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                                       ( 
                                       s 
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                             ] 
                           
                            
                         
                         
                           X 
                            
                           
                             ( 
                             s 
                             ) 
                           
                         
                       
                     
                     = 
                     
                       
                         bV 
                         s 
                       
                        
                       
                         ( 
                         s 
                         ) 
                       
                     
                   
                   , 
                   
                       
                   
                    
                   
                     
                       Y 
                        
                       
                         ( 
                         s 
                         ) 
                       
                     
                     = 
                     
                       
                         c 
                         T 
                       
                        
                       
                         X 
                          
                         
                           ( 
                           s 
                           ) 
                         
                       
                     
                   
                 
               
               
                 
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                   2 
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         [0033]    where X(s)εR n  is a state vector, V m (s)εR m  is an input vector, Y(s)εR p  is an output vector, and M,NεR N×n , bεR n×m , cεR n×p  are so-called MNA matrices, in which M and N matrix comprises a capacitor C and a conductance G; it is a Positive Definite matrix, and M is a symmetric matrix and N is an asymmetric matrix. 
         [0034]    where X(s)εR n  is a state vector, V s (s)εR m  is an input vector, Y(s)εR p  is an output vector, and M,NεR n×N , bεR N×m , cεR N×p  are so-called MNA matrices, in which M and N matrix comprises a capacitor C and a conductance G; it is a Positive Definite matrix, and M is a symmetric matrix and N is an asymmetric matrix. n is the entries of nodes in the interconnect circuit, and when the order of interconnect circuit is higher, the size of a matrix increases, thereby a great deal of memory data being wasted. n is the entries of nodes in the interconnect circuit, and when the order of interconnect circuit is higher, the size of a matrix increases, thereby a great deal of memory data being wasted. When the system reduction (flow) starts, in which the special structure of RC circuit is considered in this invention, the sparse matrix is used to form an original system, in which the technique of sparse matrix is applied to store the data regarding the capacitance and resistance, thereby the system resource being significantly reduced. In order to form an equivalent reduced system, the voltage moment that is used to establish the projection matrix (as shown in  FIG. 2  illustrating the recursion moment) is applied to form a low-order system: 
         [0000]      {circumflex over (N)}=Q T NQ, {circumflex over (M)}=Q T MQ, {circumflex over (b)}=Q T b, and ĉ=Q T c   (3) 
         [0035]    where the projection matrix Q is given to form the voltage moment of order k in formula (1), and after the projection, an output reduced system of the original system is obtained and may be made to stay passive and stable; finally the system reduction ends. 
       Time Domain Simulation 
       [0036]    As shown in  FIG. 4  illustrating a How of time domain simulation starting from time domain simulation  150  for equivalent capacitance, the time domain simulation is to analyze clocks in the circuit, in which the flow may be divided into two parts. 
         [0037]    For the first part of signal delay; calculation is done for the delay of input signal passing through a drive element. This program makes use of the table look-up of logic cell library to obtain such information. The method of table look-up is applied for the information on input signal conversion time and output load, thereby the signal delay and the output signal conversion time being obtained. 
         [0038]    For the second part of interconnect circuit analysis on the delay and conversion time of output signal passing through the interconnect circuit, the operation condition after calculation of the signal passing through the interconnect circuit is applied for the reduced model given in the technique of model reduction, and a moment equation is solved for an output result, in which an ordinary moment equation may be expressed as: 
         [0000]        M             +Nx=bV             ,    (4) 
         [0039]    where the time domain simulation is made to end. 
       Equivalent Capacitance Calculation 
       [0040]    Regarding the manner of table look-up for the algorithm of time domain simulation, the pieces of input information are the input signal transition time and the output load. Because the load connected to the drive element is an RC interconnect circuit, in order to obtain an equivalent capacitive load, a technique of calculating the equivalent capacitance is used to obtain an accurate output signal. 
         [0041]    As shown in  FIG. 5  illustrating a flow of equivalent capacitance calculation, calculation of the equivalent capacitance starts. At the time of equivalent capacitance calculation, for a large interconnect RC circuit, the interconnect circuit is used to calculate the moment of first 4 orders, a π (equivalent) model is formed, and the manner of iteration is used to calculate equivalent capacitance, thereby the equivalent capacitance being obtained and the equivalent capacitance calculation being made to end. 
         [0042]    The structure of equivalent model, as shown in  FIGS. 6   a  through  6   c , is an original RC circuit system  250 . In this invention, calculation is done for former 2 orders of voltage moment and former 3 orders of current moment that are at Root of RC interconnect circuit. A technique of moment matching is applied to obtain three parameters C 1 , C 1 , and C 1   252  of the π model, and in case of: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         i 
                         root 
                       
                       
                         v 
                         root 
                       
                     
                     = 
                     
                       
                         
                           a 
                           0 
                         
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                           1 
                         
                         + 
                         
                           
                             s 
                             2 
                           
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                           sb 
                           1 
                         
                       
                     
                   
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                         then 
                          
                         
                             
                         
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                           c 
                           1 
                         
                       
                       = 
                       
                         
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                     , 
                     
                         
                     
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                         c 
                         2 
                       
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                               2 
                             
                           
                         
                         . 
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0000]    Finally, it is reduced to equivalent capacitance  254 . 
         [0043]    Regarding the analysis on the operation complexity, for example of a huge interconnect RC circuit, there are two parts in this algorithm, namely model reduction and time domain analysis. This algorithm lets n be the entries of nodes of the original system and k be the reduced order, and in the technique of model reduction, the skill of recursion moment is applied to obtain the projection matrix; the complexity is O(nk), and at the step of model reduction fulfilled by the skill of congruent projection, the original system MN may represent a type of sparse matrix, so the complexity is O(nk 2 ) and O(k 2 ) for the matrix operation of reduced system; thus, by all accounts, the complexity of operation is O(nk+nk 2 +k 2 ), and k&lt;&lt;n. 
       Simple Embodiment 
       [0044]    In order to prove the accuracy of algorithm in this invention, as shown in  FIG. 7 , a circuit model (Case 1 ) with 10 nodes is provided and applied to analyze the performance of algorithm; however, the application of this application is not limited to the structure only. 
         [0045]    Case 1  consists of 10 resistors and 10 capacitors, of which the parameters are 100Ω and 0.01 pF, respectively. Standard error margin discussion is made through the waveform of input signal from the original circuit of this testing circuit, the calculation in the technique of model reduction and the analysis on output result, and the result obtained from the calculation by means of the Golden SPICE software, in which Golden means standard that is used in the industry and SPICE is a kind of software on language and simulation that is used in circuit description and simulation to detect the connection of circuits and the integrity of functions and predict the behavior of a circuit. It is mainly used for the simulation of a simulated circuit and a mixed signal circuit. The drive logic cell delay error is defined to: 
         [0000]    
       
         
           
             
               
                 
                   
                     ( 
                     
                       
                         
                           cell 
                            
                           
                               
                           
                            
                           delay 
                            
                           
                               
                           
                            
                           of 
                            
                           
                               
                           
                            
                           the 
                            
                           
                               
                           
                            
                           SPICE 
                         
                         - 
                         
                           cell 
                            
                           
                               
                           
                            
                           delay 
                            
                           
                               
                           
                            
                           of 
                            
                           
                               
                           
                            
                           the 
                            
                           
                               
                           
                            
                           patent 
                         
                       
                       
                         delay 
                          
                         
                             
                         
                          
                         of 
                          
                         
                             
                         
                          
                         the 
                          
                         
                             
                         
                          
                         SPICE 
                       
                     
                     ) 
                   
                   * 
                   100 
                    
                   % 
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
         [0000]    The output signal delay error of the interconnect wire is defined to: 
         [0000]    
       
         
           
             
               
                 
                   
                     ( 
                     
                       
                         
                           
                             
                               
                                 wire 
                                  
                                 
                                     
                                 
                                  
                                 delay 
                                  
                                 
                                     
                                 
                                  
                                 of 
                                  
                                 
                                     
                                 
                                  
                                 the 
                                  
                                 
                                     
                                 
                                  
                                 SPICE 
                               
                               - 
                             
                           
                         
                         
                           
                             
                               wire 
                                
                               
                                   
                               
                                
                               delay 
                                
                               
                                   
                               
                                
                               of 
                                
                               
                                   
                               
                                
                               the 
                                
                               
                                   
                               
                                
                               patent 
                             
                           
                         
                       
                       
                         wire 
                          
                         
                             
                         
                          
                         delay 
                          
                         
                             
                         
                          
                         of 
                          
                         
                             
                         
                          
                         the 
                          
                         
                             
                         
                          
                         SPICE 
                       
                     
                     ) 
                   
                   * 
                   100 
                    
                   % 
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
         [0000]    The output signal transition error of the interconnect wire is defined to: 
         [0000]    
       
         
           
             
               
                 
                   
                     ( 
                     
                       
                         
                           
                             
                               
                                 wire 
                                  
                                 
                                     
                                 
                                  
                                 transition 
                                  
                                 
                                     
                                 
                                  
                                 of 
                                  
                                 
                                     
                                 
                                  
                                 the 
                                  
                                 
                                     
                                 
                                  
                                 SPICE 
                               
                               - 
                             
                           
                         
                         
                           
                             
                               wire 
                                
                               
                                   
                               
                                
                               transition 
                                
                               
                                   
                               
                                
                               of 
                                
                               
                                   
                               
                                
                               the 
                                
                               
                                   
                               
                                
                               patent 
                             
                           
                         
                       
                       
                         wire 
                          
                         
                             
                         
                          
                         transition 
                          
                         
                             
                         
                          
                         of 
                          
                         
                             
                         
                          
                         the 
                          
                         
                             
                         
                          
                         SPICE 
                       
                     
                     ) 
                   
                   * 
                   100 
                    
                   % 
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
         [0046]    Five columns in Table 1 give respectively: (1) comparison between the error of cell delay and that of golden SPICE, (2) comparison between the error of wire delay and that of golden SPICE, (3) comparison between the error of wire transition and that of golden SPICE, (4) time spent for calculation, and (5) memory occupied for execution. 
         [0000]    
       
         
               
               
               
               
               
               
             
               
               
               
               
               
               
               
             
           
               
                   
               
               
                   
                   
                   
                   
                   
                 Occupied 
               
               
                   
                   
                   
                   
                 Time 
                 memory 
               
               
                   
                 cell 
                   
                 wire 
                 spent for 
                 size during 
               
               
                 Case 
                 delay 
                 wire delay 
                 transition 
                 calculation 
                 execution 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 1 
                 0.74% 
                 0.98% 
                 0.90% 
                 Less than 1 s 
                 254 
                 KB 
               
               
                 2 
                 0.51% 
                 0.82% 
                 0.88% 
                 0.04 s 
                 2736 
                 KB 
               
               
                 3 
                 0.89% 
                 0.74% 
                 0.83% 
                 0.07 s 
                 3176 
                 KB 
               
               
                 4 
                 1.22% 
                 1.18% 
                 1.33% 
                 4.66 s 
                 8 
                 MB 
               
               
                 Average 
                 0.84% 
                 0.93% 
                 0.98% 
                 Less than 1 s 
                 4 
                 MB 
               
               
                   
               
             
          
         
       
     
         [0047]    Through the calculation for a mean error given in Table 1 by the comparison between the result obtained in the technique proposed by this case and that obtained by means of the Golden SPICE software, it is apparent to give the accuracy of this invention. The algorithm proposed in this invention is achieved by Ansi C, compiled by gee in a Uxix system, and executed on the platform of SUN Blade 2000 with a memory of 2 GB. 
         [0048]    Case 2  consists of five interconnect systems, amounting to 5 resistors and 15 capacitors. 
         [0049]    Case 3  consists of ten interconnect systems, amounting to 178 resistors and 170 capacitors. 
         [0050]    Case 4  consists of six interconnect systems, amounting to 6000 resistors and 6000 capacitors. 
         [0051]    Case 2 ˜Case 4  consists of separately a plurality of interconnect systems; the values of resistance and capacitance vary with the interconnect systems in different Case for achievement of an analysis of extensive testing and real performance. 
         [0052]    While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.