Abstract:
An integrated charge pump is provided, comprising: a pump capacitor having a first terminal and a second terminal; a control unit, which operates the charge pump in an alternation between a first phase and a second phase; a first switching device in order to charge the pump capacitor with a pump voltage in the first phase; a second switching device in order to pull the potential of the first terminal to a predetermined potential in the second phase, and in order to connect the second terminal of the pump capacitor to an output node, the second switching device having a first transistor in order to connect the second terminal of the pump capacitor to the output node, a substrate terminal of the first transistor being fixedly connected to the output node; and the second switching device pulling the first terminal to the predetermined potential with a gradient, the gradient being chosen such that at no point in time is a diode breakdown voltage exceeded in the first transistor.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims foreign priority benefits under 35 U.S.C. §119 to co-pending German patent application number DE 10 2004 060 969.1-34, filed 17 Dec. 2004. This related patent application is herein incorporated by reference in its entirety.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The invention relates to an integrated charge pump, in particular for use in integrated circuits with reduced current consumption.  
         [0004]     2. Description of the Related Art  
         [0005]     Integrated circuits usually require, in addition to the external supply voltage, further internal voltages which do not correspond to the external supply voltage and are either larger or smaller than the external supply voltage or are provided with a different sign. In order to convert the external supply voltage into the respective internal supply voltage, a suitable voltage supply source is provided, which, for voltage conversion purposes, usually requires an additional operating current, e.g., for the voltage regulation, which additional operating current becomes apparent in the current balance of the entire integrated circuit. This additional current is essentially constant irrespective of what supply current is drawn at the output of the voltage supply source. In low-power applications, in which the voltage supply sources are operated both in a normal operating mode and in a standby operating mode, different supply currents are drawn from the voltage supply source depending on the operating mode. The efficiency of the voltage supply source deteriorates as the supply current decreases since, as mentioned previously, the additional current required, e.g., for the voltage regulation remains constant. Therefore, it is important, particularly in low-power applications, to optimize the efficiency of such voltage supply sources.  
         [0006]     In the case of charge pumps, the supply current for the supply sources is determined to a considerable extent by the switching of transistors for changing over between a first and a second cycle. Thus, by way of example, switching devices are provided in a charge pump in order to optimize the operation of the charge pump, e.g., a switching device which, depending on the operating state, connects the substrate (back gate) of a switching transistor to the respective lowest or respective highest potential.  
       SUMMARY OF THE INVENTION  
       [0007]     It is an object of the present invention to provide a charge pump which can be operated efficiently and with a low supply current/total current ratio.  
         [0008]     One aspect of the present invention provides an integrated charge pump comprising a pump capacitor having a first terminal and a second terminal. The charge pump furthermore has a control unit, by means of which the charge pump can be operated in an alternation between a first phase and a second phase. A first switching device is provided to charge the pump capacitor with a pump voltage in the first phase, and a second switching device is provided to pull the potential of the first terminal to a predetermined potential in the second phase and to connect the second terminal of the pump capacitor to an output node. The second switching device has a first transistor to connect the second terminal of the pump capacitor to the output node. Furthermore, a substrate terminal of the first transistor is fixedly connected to the output line. The second switching device pulls the first terminal to the predetermined potential with a voltage change gradient, so that at no point in time is a diode breakdown voltage exceeded in the first transistor.  
         [0009]     The charge pump according to the invention is distinguished by the fact that the first transistor, which connects the second terminal of the pump capacitor to the output line, has a substrate terminal fixedly connected to the output line. This distinguishes the charge pump according to the invention from charge pumps according to the prior art, in which the corresponding transistor with a comparable function has a substrate terminal which, depending on the phase, is alternately connected to the output line and to a potential present at the second terminal of the pump capacitor in order to apply the respective highest or lowest occurring potential in the entire charge pump circuit to the substrate terminal of the first transistor, depending on the conductivity type of the first transistor. To protect the diode breakdown voltage from being exceeded in the first transistor when the predetermined potential is present at the first terminal of the pump capacitor, the predetermined potential is applied to the first terminal of the pump capacitor with a gradient that is chosen such that at no point in time is the diode breakdown voltage exceeded in the first transistor. In this way, it is possible to significantly reduce the outlay on circuitry for such a charge pump, since, by way of example, transistors for switching the substrate terminal of the first transistor, which are usually switched synchronously with the alternation between the first and second phases, could be obviated.  
         [0010]     This can be achieved in accordance with one embodiment such that the second switching device has a second transistor, by means of which the first terminal is connected to the predetermined potential via a resistance in the second phase. The resistance may be wholly or partly formed by the forward resistance of the second transistor.  
         [0011]     In accordance with one embodiment of the invention, the channel width of the first transistor may be greater than the channel width of the second transistor, so that the voltage drop across the channel of the first transistor in the second phase can be kept as small as desired by way of the width ratio of first to second transistor and can thus be kept below the diode breakdown voltage.  
         [0012]     Preferably, the first switching device may have a third transistor in order to connect the second terminal of the pump capacitor to a charge potential in the first phase, the first and third transistors being driven with the same control signal, and the first and third transistors having an inverse switching characteristic with respect to one another. What is furthermore achieved in this way is that the circuit of the integrated charge pump can be designed with a reduced number of transistors since there is no need to separately provide drive signals for the first and third transistors.  
         [0013]     It may furthermore be provided that the first switching device has a fourth transistor, which is connected in series with the third transistor, and the fourth transistor is closed only when the first transistor is fully open. This avoids the situation in which, in the event of simultaneous switching of the first and third transistors, the switching characteristic curves overlap in such a way that a charge flows away from the output node into the voltage source for the supply potential and thus reduces the pump effect. In particular, the fourth transistor may be driven in such a way that it is opened at the same time as or before the first transistor is closed.  
         [0014]     It may furthermore be provided that the control unit receives a clock signal at an input and generates control signals for the first and second switching devices from the clock signal. In particular, a level converter may be provided to fix a level of the control signal for the first and third transistors genrally at an output potential of the output line. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]     So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.  
         [0016]      FIG. 1  shows a circuit diagram of an integrated charge pump according to the invention in accordance with a preferred embodiment; and  
         [0017]      FIG. 2  shows a signal timing diagram for the drive signals of the transistors of the charge pump shown in  FIG. 1 .  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0018]      FIG. 1  illustrates a circuit diagram of a preferred embodiment of the integrated charge pump according to the invention. The charge pump has a pump capacitor  1 , which is charged in a first phase and raises the potential at an output node A in a second phase, so that a potential greater than the supply voltage potential V DD  is achieved. This is effected by means of a number of transistors T 1 , T 2 , T 3 , T 4 , T 5 , which are driven with corresponding drive signals obtained from a clock signal CLK. The drive signals are generated in a control unit  2 , as is described in greater detail later.  
         [0019]     The pump capacitor  1  is connected to a first node K, by a first terminal and to a second node K 2  by a second terminal. The second node K 2  is connected to a first terminal of a first transistor T 1 , the second terminal of which is connected to the output node A. The second node K 2  is likewise connected to a first terminal of a third transistor T 3 , the second terminal of which is connected to a first terminal of a fourth transistor T 4 . A second terminal of the fourth transistor T 4  is connected to a first high supply voltage potential V DD  of a voltage supply. The first node K 1  is connected to a first terminal of a second transistor T 2 , the second terminal of which is connected to the first high supply voltage potential V DD  or alternatively to a further high supply potential. The first node K, is furthermore connected to a first terminal of a fifth transistor T 5 , the second terminal of which is connected to a second low supply voltage potential, preferably a ground potential GND.  
         [0020]     The first, second and fourth transistors T 1 , T 2 , T 4  have an inverse switching behavior with respect to the third and fifth transistors T 3 , T 5 . In the example illustrated, the first, second and fourth transistors T 1 , T 2  and T 4  are of a p conductivity type and the third and fifth transistors T 3 , T 5  are of an n conductivity type. These form a charge pump that generates an increased output potential in comparison with the first high supply voltage potential V DD . As an alternative, the conductivity types of the transistors may be reversed, and the polarity of the supply voltages may be interchanged, thereby forming a charge pump for a reduced output voltage in comparison with the lowest potential provided.  
         [0021]     In order to avoid the presence of a diode breakdown voltage at the first transistor T 1 , the substrate (back gate) of the first transistor T 1  is connected to the output node A, so that the substrate is always maintained at the highest possible potential in the exemplary embodiment shown. If the first transistor T 1  is formed as an n-channel field effect transistor, the substrate is connected to the lowest potential of the entire charge pump.  
         [0022]     The control terminals (gate terminals) of the first and third transistors T 1 , T 3  are connected to an output of a level converter  3 , which receives a provided clock signal CLK for controlling the cyclic first and second phases. The level converter  3  converts a level (high level) of the clock signal CLK, so that this level in this state is at the level of the output node. In the example shown, the charge pump serves to provide, at the output node A, an increased potential in comparison with the first high supply voltage V DD . If the clock signal is at a high level, then the potential of the high level is adapted to the increased potential of the output node A, so that the first and third transistors T 1 , T 3  acquire as the high level a potential corresponding to the increased potential at the output node A, so that the first and third transistors T 1 , T 3  are driven in such a way that they are fully open and fully turned off, respectively, in accordance with the high level present. If a high level is present at the transistor T 1 , then the latter turns off fully if the gate voltage is greater than the potential at the output node A reduced by the threshold voltage of the first transistor T 1 .  
         [0023]     Such a charge pump is operated in two phases. In a first phase, the pump capacitor  1  is charged by the transistors T 3 , T 4  and T 5  being closed, so that, from the first high supply voltage potential V DD , the second node K 2  and, from the second low supply voltage potential GND, the first node K, correspondingly charge the pump capacitor  1 . In a second phase, the third, fourth and fifth transistors T 3 , T 4  and T 5  are correspondingly opened. With the opening of the transistor T 3 , the transistor T 1  is also closed before the transistor T 2  is closed. The second transistor T 2  is then turned on, so that the potential of the first node is raised and thus raises the potential of the second node K 2  to the same extent. With the transistor T 1  already switched on, what is then achieved in the second phase is that the stored charge of the pump capacitor  1  can flow away to the output node A, so that a charge voltage which is increased in comparison with the first high supply voltage potential V DD  builds up there.  
         [0024]     If the potential at the node K, is raised significantly more rapidly than the charge can flow away from the node K 2  via the first transistor T 1  to the output node A, then the highest voltage present at the first transistor T 1  is at the drain terminal of the first transistor T 1 , which voltage can then exceed the diode breakdown voltage. This may have the effect that a diode current flows between the drain terminal and the substrate of the first transistor T 1 , which may lead to a latch-up effect. For this reason, it is provided according to the invention that the terminal of the pump capacitor  1  at the first node K, is not connected directly and as rapidly as possible to the first high supply voltage potential V DD  via the second transistor T 2 , so that the voltage at the second node considerably exceeds the voltage present at the output node A. Instead, the potential at the first node K, is permitted to rise with a predetermined maximum voltage change gradient. The gradient is dependent inter alia on the forward resistance of the first transistor T 1 , which determines how rapidly a charge potential on the second node K 2  can flow away to the output node A. In order to avoid a latch-up effect at the first transistor T 1 , it is necessary not to permit the voltage difference between the second node K 2  and the output node A to become greater than the threshold voltage of the pn junction that forms between the drain and the substrate terminal.  
         [0025]     The second transistor T 2  is preferably dimensioned in such a way that the first high supply voltage potential V DD  is applied to the first node K, in the closed state of the second transistor T 2  with the forward resistance inherent to the second transistor T 2 . Through a suitable dimensioning in particular of the channel width of the first and second transistors T 1 , T 2 , it is possible to ensure that the charge potential at the second node K 2  does not exceed the threshold voltage with regard to the potential at the output node A. This makes it possible for the substrate terminal of the first transistor T 1  to be fixedly connected to the output node A, since there is no need to provide further additional driving for avoiding a latch-up effect. In particular, the first and second transistors T 1 , T 2  are to be dimensioned in such a way that the channel width of the first transistor is significantly greater than the channel width of the second transistor, preferably greater by approximately a factor of 10.  
         [0026]     The first transistor T 1  and the third transistor T 3  are preferably chosen with an inverse switching behavior and driven with the same drive signal. In this way, the first transistor T 1  is closed while the third transistor T 3  is open, and vice versa. In order to prevent a current from being able to flow momentarily between the first high supply potential V DD  and the output node A while the first and third transistors T 1 , T 3  are in transition between two states, the fourth transistor T 4  is provided, which is closed only when the first transistor T 1  is certainly open.  
         [0027]      FIG. 2  illustrates a signal timing diagram for the clock signal CLK and the drive signals PRP, BOOST and PRN, which are provided by the control unit  2 . An operating cycle of the charge pump is subdivided into six time windows (identified by encircled numbers in  FIG. 2 ) in which different levels of the drive signals are in each case present at the transistors T 1  to T 5 . The PRP signal is applied to a control input of the fourth transistor T 4 , the PRN signal is applied to a control input of the fifth transistor T 5 , and the BOOST signal is applied to a control input of the second transistor T 2 . The clock signal CLK provided is present at the control inputs (gate terminals) of the first and third transistors T 1 , T 3 , in the case of which clock signal a level corresponding to the state of the clock signal CLK is put at the potential of the output node A. The first time window is characterized by a low level of the PRP signal, a high level of the PRN signal, a high level of the BOOST signal and a high level of the clock signal CLK. The first time window begins with a change in level of the PRP signal and of the PRN signal. As a result, the fourth and fifth transistors T 4  and T 5  are turned on (closed) and, on account of the high level of the clock signal CLK, the third transistor T 3  is likewise turned on, so that the first node K, is connected to the second low supply potential GND, and the second node K 2  is connected to the first high supply potential V DD . The pump capacitor  1  is thereby charged until the fourth and fifth transistors T 4 , T 5  are opened at the end of the first time window by a change in level of the PRP signal and of the PRN signal, so that the charging of the pump capacitor  1  is ended.  
         [0028]     In a second time window extending from the end of the first time window up to a change in level of the clock signal, provision is made for ensuring that no charge can flow away from the output node A to the first high supply potential V DD  if the first, third and fourth transistors T 1 , T 3 , T 4  are open in a transition phase. The provision of the second time window ensures that the fourth transistor is reliably closed before the first transistor T 1  is closed and the third transistor T 3  is opened as a result of the change in level of the clock signal CLK in a subsequent third time window.  
         [0029]     The third time window serves to ensure that the first transistor T 1  is completely closed, that is to say that the forward resistance of the first transistor is as low as possible, before the second transistor T 2  is turned on in a subsequent fourth time window by virtue of the low level of the BOOST signal, and the potential of the first node K 1  is raised in the direction of the first high supply potential V DD . As mentioned previously, the channel widths of the first and second transistors T 1  and T 2  should be chosen such that the channel width of the first transistor T 1  is significantly greater than that of the second transistor T 2 . As an alternative, it may also be provided that the BOOST signal is not provided as a digital drive signal but rather as an analog drive signal, and during the BOOST phase, that is to say during the fourth time window, the second transistor T 2  is not completely turned on, but rather is turned on only such that, with a closed first transistor T 1 , the voltage difference between the second node K 2  and the output node A does not exceed the threshold voltage (diode forward voltage), in order to preclude a latch-up effect.  
         [0030]     As an alternative, an additional resistance (not shown) may also be inserted between the first high supply potential V DD  and the first node K 1  in order to limit the charge flow to the first terminal of the pump capacitor  1 .  
         [0031]     In the fifth time window, which follows the fourth time window during cyclic operation, the second transistor T 2  is switched off again. The latter is preferably opened (or switched-off) before the transistor T 1  in order to avoid a high voltage jump at the second node K 2  if the first transistor T 1  were opened first. In a subsequent sixth time window, the first transistor T 1  is switched off, such that it is not possible for a voltage jump to occur at the second node K 2  since the parasitic capacitances between the first and second nodes are large in comparison with the overcoupling capacitance between the control terminals of the first and third transistors T 1 , T 3  and the second node.  
         [0032]     One advantage of the charge pump circuit proposed is that the highest voltage that occurs in the circuit is essentially the potential at the output node A, so that the well terminals (substrate terminals) of the first and fourth transistors T 1 , T 4  can be fixedly connected to the output node. Furthermore, the first and third transistors T 1 , T 3  can be driven with the same drive signal, so that instead of two separate level converters only one level converter  3  is required, which drives the two control terminals of the first and third transistors T 1  and T 3 . The second, third, fifth and sixth time windows should be chosen to be as small as possible in order that the charging time of the pump capacitor is not restricted unnecessarily, but large enough to achieve the effects described.  
         [0033]     While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.