Abstract:
A semiconductor device with a capacitor structure for improving area utilization comprises a plurality of electrically conductive layers and a plurality of dielectric layers. The dielectric layers and the electrically conductive layers are alternately superposed one over another, and the electrically conductive layers are alternately electrically connected.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The invention relates generally to a semiconductor device with a capacitor and, in particular, to the structure of the capacitor.  
         [0003]     2. Description of the Related Art  
         [0004]     A capacitor in an existing semiconductor device generally has a structure where, above and below an insulating layer that constitutes a dielectric layer, electrically conductive layers constituting a pair of electrodes are formed. A capacitance value of the capacitor is determined by the dielectric constant of the dielectric layer and the area size of the capacitor. The “area size” means the overlapping facing area of the opposed electrically conductive layers that sandwich the dielectric layer. (See Japanese Unexamined Patent Application Publication No. JP-A-5-190766).  
       SUMMARY OF THE INVENTION  
       [0005]     In the prior art capacitor structure, assuming the condition that the dielectric constants are same, in order to increase the capacitance value, the facing area of the respective electrically conductive layers has to be increased. That is, in order to obtain a capacitor having a larger capacitance value, a larger area size is necessary. Accordingly, in order to form a capacitor that has a large capacitance value, a problem of larger-sized semiconductor devices cannot be avoided. The present invention seeks to overcome this problem and provides a capacitor structure that, without increasing semiconductor device size, can obtain a large capacitance value.  
         [0006]     In order to achieve the foregoing and other objects, according to a first aspect of the present invention, a capacitor structure includes a plurality of electrically conductive layers and a plurality of dielectric layers, wherein the dielectric layers and the electrically conductive layers are alternately superposed one over another, and the electrically conductive layers are alternately electrically connected.  
         [0007]     Similarly, in order to achieve the foregoing and other objects, according to a second aspect of the present invention, a semiconductor device with a capacitor structure which includes a dielectric layer sandwiched between a first capacitor electrode and a second capacitor electrode, comprises a first capacitor portion including a diffusion region formed in a semiconductor substrate, a first dielectric layer formed on the diffusion region, and the second capacitor electrode formed on the first dielectric layer; and a second capacitor portion including the second capacitor electrode, a second dielectric layer formed on the second capacitor electrode, and a conductive layer formed on the second dielectric layer; wherein the diffusion region and the conductive layer are electrically connected to each other such that the diffusion region and the conductive layer comprise the first capacitor electrode.  
         [0008]     Furthermore, in a capacitor structure involving a third aspect of the present invention, in the semiconductor device according to the second aspect of the invention, the diffusion region and the conductive layer are connected by a metal layer.  
         [0009]     According to the first and second aspects of the present invention, the facing area of the electrically conductive layers that constitute a pair of electrodes that face each other with the dielectric layer interposed therebetween can be increased not planarly but superposedly. Accordingly, without enlarging the semiconductor device, a capacitor having a large capacitance value can be obtained.  
         [0010]     According to the third aspect of the present invention, in addition to the above advantages, electrical connections between the electrically conductive layers can be more assuredly carried out.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]      FIG. 1  is a schematic sectional view of a semiconductor device with a capacitor according to one embodiment of the present invention.  
         [0012]      FIG. 2  is a schematic plan view of the semiconductor device with a capacitor shown in  FIG. 1 .  
         [0013]      FIG. 3  is an explanatory circuit diagram for explaining the constitution of the capacitor in the embodiment shown in  FIGS. 1-2 .  
         [0014]      FIG. 4  is an explanatory circuit diagram for explaining the constitution of a capacitor in another embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0015]     Now, preferred embodiments of the invention will be described with reference to  FIGS. 1 through 3 .  FIG. 1  is a schematic sectional view of a semiconductor device with a capacitor,  FIG. 2  is a plan view thereof, and  FIG. 3  is a circuit diagram for explaining the constitution of the capacitor.  
         [0016]     As shown in  FIG. 1 , on a silicon substrate  1  of a semiconductor device, impurity ions such as arsenic or phosphorus are implanted to form an N-diffusion layer  2  and a diffusion region  2   a  where the impurity ions are partially implanted at a high concentration. The diffusion layer  2  constitutes an electrically conductive layer, and a first insulating layer  3  comprised, for example, of silicon oxide is formed on and overlies the electrically conductive diffusion layer  2 . A lower electrically conductive layer  4 , preferably comprised of polysilicon, is formed on and overlies the first insulating layer  3 . Thereby, a first capacitor is formed having the first insulating layer  3  as a dielectric layer sandwiched between the diffusion layer  2  and the lower electrically conductive layer  4  as a pair of electrodes.  
         [0017]     On the lower electrically conductive layer  4 , a second insulating layer  5  is formed, the second insulating layer  5  overlying the electrically conductive layer  4  and being comprised, for example, of silicon oxide. On the second insulating layer  5 , an upper electrically conductive layer  6  is formed, the conductive layer  6  overlying the second insulating layer  5  and preferably being comprised of polysilicon. Thereby, a second capacitor is formed having the second insulating layer  5  as a dielectric layer sandwiched between the lower electrically conductive layer  4  and the upper electrically conductive layer  6  as a pair of electrodes. The lower electrically conductive layer  4  is an electrode common for both capacitors.  
         [0018]     An insulating layer  10  comprised, for example, of silicon oxide is formed on both the upper electrically conductive layer  6  and the second insulating layer  5 , and the upper electrically conductive layer  6  and the high concentration region  2   a  of the diffusion layer  2  are electrically connected with a wiring  7  of metal such as aluminum. By such a construction, as shown in  FIG. 3 , two superposed capacitors are formed that share the common electrode  4  and are connected in parallel with each other.  
         [0019]     In  FIGS. 1 and 2 , reference numeral  11  denotes a contact region between the metal wiring  7  and the high concentration region  2   a,  and reference numeral  12  denotes a contact region between the metal wiring  7  and the upper electrically conductive layer  6 . Furthermore, as understood from  FIGS. 1 and 2 , the lower electrically conductive layer  4  is electrically connected to an electrode of a MOS transistor formed on the silicon substrate  1  by a wiring  8  of metal, such as aluminum, in a contact region  13 . In  FIG. 1 , reference numeral  9  denotes a LOCOS element isolation region.  
         [0020]     In the embodiment described above, a first capacitor having the diffusion layer  2  and the lower electrically conductive layer  4  as a pair of electrodes and a second capacitor having the lower electrically conductive layer  4  and the upper electrically conductive layer  6  as a pair of electrodes are superposedly formed, and the diffusion layer  2  and the upper electrically conductive layer  6  are electrically connected. By such a construction, without horizontally expanding facing electrically conductive layers  2 ,  4  and  4 ,  6  that constitute pairs of opposed electrodes, the facing area of the opposed electrodes can be increased. That is, when compared with a capacitor that occupies the same area in a horizontal direction of the opposed electrodes, a capacitor having substantially two times the capacitance value can be obtained.  
         [0021]     The present invention is not restricted to the above embodiment. For instance, the diffusion layer  2  and the electrically conductive layer  6  can be electrically connected not through the metal wiring  7  but directly. When the diffusion layer  2  and the electrically conductive layer  6  are directly electrically connected together rather than indirectly connected through the metal wiring  7 , the high concentration region  2   a  of the diffusion layer  2  can be dispensed with. Furthermore, the number of superposed capacitors is not restricted to two and may be three or more. In this case, as shown in  FIG. 4 , electrically conductive layers, C 1  through Cn, which are located above and below one another, are alternately electrically connected.