Abstract:
The invention discloses a semiconductor switching circuit suitable for a Single Pole n Throw (SPnT) switching circuit having: a common terminal; first through third terminals, ground and control terminals, through FETS, shunt FETs, wherein when a first electric potential is supplied only to a Jth control terminal, and a second lower electric potential is supplied to the other control terminals, the common and Jth terminals are electrically connected and the first through third terminals are electrically disconnected.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
   This application is based upon and claims benefit of priority under 35 USC §119 from the Japanese Patent Application No. 2004-304350, filed on Oct. 19, 2004, the entire contents of which are incorporated herein by reference. 
   BACKGROUND OF THE INVENTION 
   The present invention relates to a semiconductor switching circuit and, more particularly, to a semiconductor switching circuit suited for, e.g., an SPnT (Single-Pole n-Throw) switching circuit. 
   For example, an SP3T switch is widely used as a switch for switching transmission and reception of radio-frequency signals by a single antenna in a cellphone. 
   This radio-frequency switch of 1 GHz or more is in many cases made of a compound semiconductor such as GaAs having high electron mobility and excellent characteristics in a radio-frequency region. 
   Unfortunately, a P-channel FET is difficult to realize by the compound semiconductor. Therefore, when logic circuits necessary to control switching are to be fabricated by using OR circuits, they are fabricated by using, e.g., N-channel FETs alone, N-channel FETs and resistors, or N-channel FETs and diodes. In any case, current consumption occurs in a standby state. 
   If it is necessary to reduce this current consumption in the standby state to zero, the logic circuits must be fabricated by using externally attached CMOS circuits. In this case, however, six control terminals are necessary. 
   This increases the number of pads and inevitably increases the chip size. The increase in chip size is a fatal problem in a switching IC which is severely required to reduce the fabrication cost. 
   Also, it is necessary to form many interconnections on a packaging substrate, and form an additional logic IC for control. This increases both the packaging area and cost. 
   The conventional SP3T switch, therefore, must incorporate OR circuits, and this increases the current consumption. 
   As described above, it is difficult for the conventional shunt type SP3T switch to decrease the number of control terminals to three or less and at the same time reduce the current consumption in the standby state. 
   A reference disclosing the conventional semiconductor switching circuit is as follows. 
   Japanese Patent Laid-Open No. 2000-68807 
   SUMMARY OF THE INVENTION 
   According to one of the present invention, there is provided a semiconductor switching circuit comprising: 
   a common terminal; 
   first, second, and third terminals; 
   first, second, and third ground terminals; 
   first, second, and third control terminals; 
   a first through FET having a source and drain connected in series between said common terminal and first terminal, and a gate connected to said first control terminal via a first resistor; 
   a second through FET having a source and drain connected in series between said common terminal and second terminal, and a gate connected to said second control terminal via a second resistor; 
   a third through FET having a source and drain connected in series between said common terminal and third terminal, and a gate connected to said third control terminal via a third resistor; 
   11th and 12th shunt FETs each having a source and drain connected in parallel between said first terminal and first ground terminal; 
   21st and 22nd shunt FETs each having a source and drain connected in parallel between said second terminal and second ground terminal; and 
   31st and 32nd shunt FETs each having a source and drain connected in parallel between said third terminal and third ground terminal, 
   wherein gates of said 11th and 22nd shunt FETs are connected to said third control terminal via 11th and 22nd resistors, respectively, 
   gates of said 21st and 31st shunt FETs are connected to said first control terminal via 21st and 31st resistors, respectively, 
   gates of said 12th and 32nd shunt FETs are connected to said second control terminal via 12th and 32nd resistors, respectively, and 
   when a first electric potential is supplied only to a Jth (J is a natural number of 1 to 3) control terminal, and a second electric potential lower than the first electric potential is supplied to the rest of said control terminals, 
   said common terminal and a Jth terminal are electrically connected, and 
   said first to third terminals except for said Jth terminal and said common terminal are electrically disconnected. 
   According to one of the present invention, there is provided a semiconductor switching circuit comprising: 
   a common terminal; 
   first, second, jth (j is an integer of 3 to n−1), and nth (n is an integer of not less than 3) terminals; 
   first, second, jth, and nth ground terminals; 
   first, second, jth, and nth control terminals; 
   a first through FET having a source and drain connected in series between said common terminal and first terminal, and a gate connected to said first control terminal via a first resistor; 
   a second through FET having a source and drain connected in series between said common terminal and second terminal, and a gate connected to said second control terminal via a second resistor; 
   a jth through FET having a source and drain connected in series between said common terminal and jth terminal, and a gate connected to said jth control terminal via a jth resistor; 
   an nth through FET having a source and drain connected in series between said common terminal and nth terminal, and a gate connected to said nth control terminal via an nth resistor; 
   11th, 12th, (1j)th, and (1(n−1))th shunt FETs each having a source and drain connected in parallel between said first terminal and first ground terminal; 
   21st, 22nd, (2j)th, and (2(n−1))th shunt FETs each having a source and drain connected in parallel between said second terminal and second ground terminal; 
   (j1)th, (j2)th, (jj)th, and (j(j−1))th FETs each having a source and drain connected in parallel between said jth terminal and jth ground terminal; and 
   (n1)th, (n2)th, (nj)th, and (n(n−1))th FETs each having a source and drain connected in parallel between said nth terminal and nth ground terminal, 
   wherein gates of said 11th to (1(n−1))th shunt FETs are connected to said second to nth control terminals except for said first control terminal via 11th to (1(n−1))th resistors, respectively, 
   gates of said 21st to (2(n−1))th shunt FETs are connected to said first and third to nth control terminals except for said second control terminal via 21st to (2(n−1))th resistors, respectively, 
   gates of said (n1)th to (n(n−1))th shunt FETs are connected to said first to (n−1)th control terminals except for said nth control terminal via (n1)th to (n(n−1))th resistors, respectively, and 
   when a first electric potential is supplied only to a kth (k is an integer of 1 to n) control terminal, and a second electric potential lower than the first electric potential is supplied to the rest of said control terminals, 
   said common terminal and a kth terminal are electrically connected, and 
   said first to nth terminals except for said kth terminal and said common terminal are electrically disconnected. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a circuit diagram showing the arrangement of a semiconductor switching circuit according to the first embodiment of the present invention; 
       FIG. 2  is a circuit diagram showing the arrangement of a semiconductor switching circuit according to a comparative example; 
       FIG. 3  is a circuit diagram showing the arrangement of a semiconductor switching circuit according to the second embodiment of the present invention; 
       FIG. 4  is a circuit diagram showing the arrangement of a semiconductor switching circuit according to the third embodiment of the present invention; 
       FIG. 5  is a circuit diagram showing the arrangement of a semiconductor switching circuit according to the fourth embodiment of the present invention; 
       FIG. 6  is a circuit diagram showing the arrangement of a semiconductor switching circuit according to a modification of the second embodiment of the present invention; and 
       FIG. 7  is a circuit diagram showing the arrangement of a semiconductor switching circuit according to a modification of the third embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Semiconductor switching circuits according to embodiments of the present invention will be described below with reference to the accompanying drawing. 
   (1) First Embodiment 
   The first embodiment as shown in  FIG. 1  comprises one common radio-frequency signal terminal RF_COM, three radio-frequency signal terminals RF_ 1 , RF_ 2 , and RF_ 3 , three control terminals Cont_ 1 , Cont_ 2 , and Cont_ 3 , three radio-frequency ground terminals GND_ 1 , GND_ 2 , and GND_ 3 , three through FETs Q_T 1 , Q_T 2 , and Q_T 3 , three shunt FETs Q_S 1 A, Q_S 2 A, and Q_S 3 A, three shunt FETs Q_S 1 B, Q_S 2 B, and Q_S 3 B, three resistors R_T 1 , R_T 2 , and R_T 3 , three resistors R_S 1 A, R_S 2 A, and R_S 3 A, and three resistors R_S 1 B, R_S 2 B, and R_S 3 B. 
   The above circuit elements are connected as follows. 
   The drains and sources of the through FETs Q_T 1 , Q_T 2 , and Q_T 3  are connected in series between the terminal RF_COM and terminal RF_ 1 , between the terminal RF_COM and terminal RF_ 2 , and between the terminal RF_COM and terminal RF_ 3 , respectively. The gates of the through FETs Q_T 1 , Q_T 2 , and Q_T 3  are connected to the control terminals Cont_ 1 , Cont_ 2 , and Cont_ 3  via the high resistors R_T 1 , R_T 2 , and R_T 3 , respectively. 
   The drains and sources of the shunt FETs Q_S 1 A, Q_S 2 A, and Q_S 3 A are connected in series between the terminal RF_ 1  and ground terminal GND_ 1 , between the terminal RF_ 2  and ground terminal GND_ 2 , and between the terminal RF_ 3  and ground terminal GND_ 3 , respectively. 
   The drains and sources of the shunt FETs Q_S 1 B, Q_S 2 B, and Q_S 3 B are connected in series between the terminal RF_ 1  and ground terminal GND_ 1 , between the terminal RF_ 2  and ground terminal GND_ 2 , and between the terminal RF_ 3  and ground terminal GND_ 3 , in parallel with the shunt FETs Q_S 1 A, Q_S 2 A, and Q_S 3 A, respectively. 
   The gates of the shunt FETs Q_S 1 A, Q_S 2 A, and Q_S 3 A are connected to the control terminals Cont_ 3 , Cont_ 1 , and Cont_ 1  via the high resistors R_S 1 A, R_S 2 A, and R_S 3 A, respectively. 
   The gates of the shunt FETs Q_S 1 B, Q_S 2 B, and Q_S 3 B are connected to the control terminals Cont_ 2 , Cont_ 3 , and Cont_ 2  via the high resistors R_S 1 B, R_S 2 B, and R_S 3 B, respectively. 
   In the first embodiment as described above, the paired shunt FETs Q_S 1 A and Q_S 1 B, Q_S 2 A and Q_S 2 B, and Q_S 3 A and Q_S 3 B are connected in parallel between the terminal RF_ 1  and ground terminal GND_ 1 , between the terminal RF_ 2  and ground terminal GND_ 2 , and between the terminal RF_ 3  and ground terminal GND_ 3 , respectively. 
   The following three modes can be switched by the electric potentials of the control terminals Cont_ 1 , Cont_ 2 , and Cont_ 3 . 
   (A) When the control terminals are Cont_ 1 =high level, Cont_ 2 =low level, and Cont_ 3 =low level;
         the FETs Q_T 1 , Q_S 2 A, and Q_S 3 A are ON, and the FETs Q_T 2 , Q_T 3 , Q_S 1 A, Q_S 1 B, Q_S 2 B and Q_S 3 B are OFF.       

   Accordingly, the terminals RF_COM and RF_ 1  are electrically connected, and the terminals RF_COM and RF_ 2  and the terminals RF_COM and RF_ 3  are electrically disconnected. 
   (B) When the control terminals are Cont_ 2 =high level, Cont_ 1 =low level, and Cont_ 3 =low level; 
   the FETs Q_T 2 , Q_S 1 B, and Q_S 3 B are ON, and the FETs Q_T 1 , Q_T 3 , Q_S 2 A, Q_S 2 B, Q_S 1 A and Q_S 3 A are OFF. 
   Accordingly, the terminals RF_COM and RF_ 2  are electrically connected, and the terminals RF_COM and RF_ 1  and the terminals RF_COM and RF_ 3  are electrically disconnected. 
   (C) When the control terminals are Cont_ 3 =high level, Cont_ 1 =low level, and Cont_ 2 =low level; 
   the FETs Q_T 3 , Q_S 1 A, and Q_S 2 B are ON, and the FETs Q_T 1 , Q_T 2 , Q_S 3 A, Q_S 3 B, Q_S 1 B and Q_S 2 A are OFF. 
   In this state, the terminals RF_COM and RF_ 3  are electrically connected, and the terminals RF_COM and RF_ 1  and the terminals RF_COM and RF_ 2  are electrically disconnected. 
   As described above, in the electrically disconnected state, the through FETs are OFF, and the shunt FETs are ON. This increases the isolation between two terminals. 
   The resistor connected to the gate of each FET has a resistance value high enough to prevent a leak of RF signals. That terminal of each resistor, which is not connected to the gate is connected to the control terminal so as to implement the above function. 
   Also, the ground terminals GND_ 1 , GND_ 2 , and GND_ 3  are desirably so grounded that when this embodiment is formed into a chip, no RF signals leak outside the chip. 
   When the above circuit is produced, the ground terminals GND_ 1 , GND_ 2 , and GND_ 3  are connected to external terminals by bonding wires. These bonding wires have parasitic inductances and hence are not completely grounded. Therefore, if these three ground terminals are bound in the integrated circuit, RF signals may leak through the path to deteriorate the isolation characteristics between the terminals RF_ 1 , RF_ 2 , and RF_ 3 . 
   Accordingly, as described above, it is important that the shunt FET pairs, i.e., the FETs Q_S 1 A and Q_S 1 B, Q_S 2 A and Q_S 2 B, and Q_S 3 A and Q_S 3 B are connected to the independent ground terminals GND_ 1 , GND_ 2 , and GND_ 3  for RF signals. 
   Note that if the ground terminals GND_ 1 , GND_ 2 , and GND_ 3  can be regarded as ideal RF signal compatible ground terminals owing to bump packaging or the like, these ground terminals may also be connected together in the integrated circuit. 
   In the first embodiment, an SP3T switch can be implemented only with three control terminals although practically no control circuit formed by, e.g., logic circuits requiring current consumption exits. 
   Note that current consumption occurs only when a reverse leakage current is produced in the gate of the FET. However, a current value in this case is extremely small and practically almost negligible. Therefore, it is possible to implement an SP3T having practically zero current consumption. 
     FIG. 2  shows the arrangement of an SP3T switch as a comparative example of the first embodiment described above. 
   In this comparative example, unlike in the first embodiment, shunt FETs Q_S 1 , Q_S 2 , and Q_S 3  are connected between terminals RF_ 1 , RF_ 2 , and RF_ 3 , respectively, and common ground terminal connected to them. 
   Instead of the shunt FET pairs in the first embodiment, three two-input OR circuits are used as control circuits. That is, OR circuits OR_ 1 , OR_ 2 , and OR_ 3  are formed between through FETs Q_T 1 , Q_T 2 , and Q_T 3  and the shunt FETs Q_S 1 , Q_S 2 , and Q_S 3 , respectively. 
   For example, when control terminals Cont_ 1 , Cont_ 2 , and Cont_ 3  are high level, low level, and low level, respectively, the FETs Q_T 1 , Q_S 2 , and Q_S 3  are ON, and the FETs Q_T 2 , Q_T 3 , and Q_S 1  are OFF. 
   Consequently, only a terminal RF_COM and the terminal RF_ 1  are electrically connected, and the terminals RF_COM and RF_ 2  and the terminals RF_COM and RF_ 3  are electrically disconnected. 
   In this comparative example as described above, logic circuits necessary to control switching are fabricated by using OR circuits, and these OR circuits are formed by externally attached CMOS circuits in order to prevent current consumption in a standby state. However, as described previously, at least six control terminals are required, and this increases the chip size and cost. 
   By contrast, the first embodiment can prevent the increase in number of control terminals, and reduce the current consumption in the standby state to practically zero. 
   (2) Second Embodiment 
     FIG. 3  shows the arrangement of an SP3T switch according to the second embodiment of the present invention. 
   The second embodiment differs from the first embodiment in that a capacitor C 1  for removing the DC component is connected between a terminal CF_COM and the ends on one side of through FETs Q_T 1  to Q_T 3 , and capacitors C 2  to C 7  for removing the DC component are connected between terminals RF_ 1  to RF_ 3  and GND_ 1  to GND_ 3  and shunt FETs Q_S 1 B to Q_S 3 B connected to these terminals. 
   As explained in the first embodiment, a shunt FET Q_S 1 A and the shunt FET Q_S 1 B, a shunt FET Q_S 2 A and the shunt FET Q_S 2 B, and a shunt FET Q_S 3 A and the shunt FET Q_S 3 B are connected in parallel between the terminal RF_ 1  and ground terminal GND_ 1 , the terminal RF_ 2  and ground terminal GND_ 2 , and the terminal RF_ 3  and ground terminal GND_ 3 , respectively. What is important is that the capacitors C 2  to C 7  are formed independently of each other between the terminals RF_ 1  to RF_ 3  and GND_ 1  and GND_ 3  and the shunt FETs Q_S 1 B to Q_S 3 B connected to these terminals. Accordingly, the RF characteristics can be improved by removing the DC component for each terminal. 
   Since these capacitors for removing the DC component are necessary, they are formed outside the integrated circuit in the first embodiment. In the second embodiment, the capacitors C 1  to C 7  are formed inside the circuit, so no capacitors need be externally connected. This helps reduce the device area and cost. 
   Note that practical materials of the capacitors C 1  to C 7  are not particularly limited. However, if MIM (Metal-Insulator-Metal) capacitors are used, the value of the capacitance can be accurately set. 
   This makes it possible to accurately adjust the capacitance value to a value which causes series resonance at a desired frequency with respect to the series parasitic inductance, such as a bonding wire, of an enclosure. As a consequence, the characteristics of an SP3T switch can be well achieved. 
   (3) Third Embodiment 
     FIG. 4  shows the arrangement of an SP3T switch according to the third embodiment of the present invention. 
   In the second embodiment, the through FETs Q_T 1  to Q_T 3  ad the shunt FETs Q_S 1 A to Q_S 3 A and Q_S 1 B to Q_S 3 B are single-gate FETs. The third embodiment differs from the second embodiment in that all these FETs are multi-gate FETs. 
   Although FETs shown in  FIG. 4  are triple-gate FETs, any FETs having two or more gates can be used. 
   In the third embodiment as described above, the use of the multi-gate FETs increases the maximum allowable input power. The rest of the arrangement and the effects of this embodiment are the same as the second embodiment, so an explanation thereof will be omitted. 
   (4) Fourth Embodiment 
   The fourth embodiment is equivalent to applying the arrangement of the SP3T switch according to the second embodiment to an SP4T switch.  FIG. 5  shows the arrangement of the fourth embodiment. 
   The drains and sources of through FETs Q_T 1 , Q_T 2 , Q_T 3 , and Q_T 4  are connected in series between a terminal RF_COM and a terminal RF_ 1 , between the terminal RF_COM and a terminal RF_ 2 , between the terminal RF_COM and a terminal RF_ 3 , between the terminal RF_COM and a terminal and RF_ 4 , respectively. The gates of the through FETs Q_T 1 , Q_T 2 , Q_T 3 , and Q_T 4  are connected to control terminals Cont_ 1 , Cont_ 2 , Cont_ 3 , and Cont_ 4  via high resistors R_T 1 , R_T 2 , R_T 3 , and R_T 4 , respectively. 
   The drains and sources of shunt FETs Q_S 1 A, Q_S 2 A, Q_S 3 A, and Q_S 4 A are connected in series between the terminal RF_ 1  and a ground terminal GND_ 1 , the terminal RF_ 2  and a ground terminal GND_ 2 , the terminal RF_ 3  and a ground terminal GND_ 3 , and the terminal RF_ 4  and a ground terminal GND_ 4 , respectively. 
   The drains and sources of shunt FETs Q_S 1 B, Q_S 2 B, Q_S 3 B, and Q_S 4 B are connected in series between the terminal RF_ 1  and ground terminal GND_ 1 , the terminal RF_ 2  and ground terminal GND_ 2 , the terminal RF_ 3  and ground terminal GND_ 3 , and the terminal RF_ 4  and ground terminal GND_ 4 , in parallel with the shunt FETs Q_S 1 A, Q_S 2 A, Q_S 3 A, and Q_S 4 A, respectively. 
   The drains and sources of shunt FETs Q_S 1 C, Q_S 2 C, Q_S 3 C, and Q_S 4 C are connected in series between the terminal RF_ 1  and ground terminal GND_ 1 , the terminal RF_ 2  and ground terminal GND_ 2 , the terminal RF_ 3  and ground terminal GND_ 3 , and the terminal RF_ 4  and ground terminal GND_ 4 , in parallel with the shunt FETs Q_S 1 A and Q_S 1 B, Q_S 2 A and Q_S 2 B, Q_S 3 A and Q_S 3 B, and Q_S 4 A and Q_S 4 B, respectively. 
   The gates of the shunt FETs Q_S 1 A, Q_S 2 A, Q_S 3 A, and Q_S 4 A are connected to the control terminals Cont_ 3 , Cont_ 1 , Cont_ 1 , and Cont_ 1  via high resistors R_S 1 A, R_S 2 A, R_S 3 A, and R_S 4 A, respectively. 
   The gates of the shunt FETs Q_S 1 B, Q_S 2 B, Q_S 3 B, and Q_S 4 B are connected to the control terminals Cont_ 2 , Cont_ 3 , Cont_ 2 , and Cont_ 2  via high resistors R_S 1 B, R_S 2 B, R_S 3 B, and R_S 4 B, respectively. 
   The gates of the shunt FETs Q_S 1 C, Q_S 2 C, Q_S 3 C, and Q_S 4 C are connected to the control terminals Cont_ 4 , Cont_ 4 , Cont_ 4 , and Cont_ 3  via high resistors R_S 1 C, R_S 2 C, R_S 3 C, and R_S 4 C, respectively. 
   In the fourth embodiment as described above, the shunt FETs Q_S 1 A, Q_S 1 B, and Q_S 1 C, Q_S 2 A, Q_S 2 B, and Q_S 2 C, and Q_S 3 A, Q_S 3 B, and Q_S 3 C are connected in parallel between the terminal RF_ 1  and ground terminal GND_ 1 , terminal RF_ 2  and ground terminal GND_ 2 , and terminal RF_ 3  and ground terminal GND_ 3 , and terminal RF_ 4  and ground terminal GND_ 4 , respectively. 
   The following four modes can be switched by the electric potentials of the control terminals Cont_ 1 , Cont_ 2 , Cont_ 3 , and Cont_ 4 . 
   (A) When the control terminals are Cont_ 1 =high level, Cont_ 2 =low level, Cont_ 3 =low level, and Cont_ 4 =low level; 
   the FETs Q_T 1 , Q_S 2 A, Q_S 3 A, and Q_S 4 A are ON, and the FETs Q_T 2 , Q_T 3 , Q_T 4 , Q_S 1 A, Q_S 1 B, Q_S 1 C, Q_S 2 B, Q_S 2 C, Q_S 3 B, Q_S 3 C, Q_S 4 B and Q_S 4 C are OFF. 
   Accordingly, the terminals RF_COM and RF_ 1  are electrically connected, and the terminals RF_COM and RF_ 2 , the terminals RF_COM and RF_ 3 , and the terminals RF_COM and RF_ 4  are electrically disconnected. 
   (B) When the control terminals are Cont_ 2 =high level, Cont_ 1 =low level, Cont_ 3 =low level, and Cont_ 4 =low level; 
   the FETs Q_T 2 , Q_S 1 B, Q_S 3 B, and Q_S 4 B are ON, and the FETs Q_T 1 , Q_T 3 , Q_T 4 , Q_S 2 A, Q_S 2 B, Q_S 2 C, Q_S 1 A, Q_S 1 C, Q_S 3 A, Q_S 3 C, Q_S 4 A and Q_S 4 C are OFF. 
   Accordingly, the terminals RF_COM and RF_ 2  are electrically connected, and the terminals RF_COM and RF_ 1 , the terminals RF_COM and RF_ 3 , and the terminals RF_COM and RF_ 4  are electrically disconnected. 
   (C) When the control terminals are Cont_ 3 =high level, Cont_ 1 =low level, Cont_ 2 =low level, and Cont_ 4 =low level; 
   the FETs Q_T 3 , Q_S 1 A, Q_S 2 B, and Q_S 4 C are ON, and the FETs Q_T 1 , Q_T 2 , Q_T 4 , Q_S 3 A, Q_S 3 B, Q_S 3 C, Q_S 1 B, Q_S 1 C, Q_S 2 A, Q_S 2 C, Q_S 4 A and Q_S 4 B are OFF. 
   Accordingly, the terminals RF_COM and RF_ 3  are electrically connected, and the terminals RF_COM and RF_ 1 , the terminals RF_COM and RF_ 2 , and the terminals RF_COM and RF_ 4  are electrically disconnected. 
   (D) When the control terminals are Cont_ 4 =high level, Cont_ 1 =low level, Cont_ 2 =low level, and Cont_ 3 =low level; 
   the FETs Q_T 4 , Q_S 1 C, Q_S 2 C, and Q_S 3 C are ON, and the FETs Q_T 1 , Q_T 2 , Q_T 3 , Q_S 4 A, Q_S 4 B, Q_S 4 C, Q_S 1 A, Q_S 1 B, Q_S 2 A, Q_S 2 B, Q_S 3 A and Q_S 3 B are OFF. 
   In this case, the terminals RF_COM and RF_ 4  are electrically connected, and the terminals RF_COM and RF_ 1 , the terminals RF_COM and RF_ 2 , and the terminals RF_COM and RF_ 3  are electrically disconnected. 
   As in the first to third embodiments described above, the resistors R_T 1  to R_T 4 , R_S 1 A to R_S 4 A, R_S 1 B to R_S 4 B, and R_S 1 C to R_S 4 C connected to the gates of the FETs each have a resistance value high enough to prevent a leak of RF signals. Also, that terminal of each resistor, which is not connected to the gate of any FET is connected to one of the control terminals Cont_ 1  to Cont_ 4  so as to implement the above switching function. 
   Note that as in the first to third embodiments, the ground terminals GND_ 1  to GND_ 4  are desirably so grounded that no RF signals leak outside the integrated circuit. 
   Note also that it is important that the four shunt FET sets, i.e., the FETs Q_S 1 A to Q_S 1 C, Q_S 2 A to Q_S 2 C, Q_S 3 A to Q_S 3 C, and Q_S 4 A to S 4 C are independently connected to the different ground terminals GND_ 1 , GND_ 2 , GND_ 3 , and GND_ 4 , respectively, in order to improve the RF characteristics. 
   The circuit of this embodiment can implement an SP4T switch by using only four control terminals without any control circuits formed by, e.g., logic circuits which consume electric currents. That is, the semiconductor switching circuit of this embodiment can reduce the current consumption in the standby state without increasing the number of control terminals. 
   In the arrangement shown in  FIG. 5 , no capacitor for removing the DC component is formed, and each FET has a single-gate structure. 
   It is, however, also possible to form capacitors as in the second or third embodiment, or use FETs having a multi-gate structure as in the third embodiment. 
   The above embodiments are merely examples and can be modified within the technical scope of the present invention. 
   For example, although the present invention is applied to an SP3T switch in each of the first to third embodiments and an SP4T switch in the fourth embodiment, it is also applicable to an SPnT switch (n is a natural number of 3 or more). 
   In addition, as described previously, the present invention can implement an SPnT switch by using n control terminals without any logic circuit. 
   Also, as a modification of the second embodiment in which the capacitors C 1  to C 7  for removing the DC component are formed, it is also possible, as shown in  FIG. 6 , to newly form a power supply terminal Vdd, and connect a resistive element R 1  having a resistance value by which no RF signals leak, between the power supply terminal Vdd and internal signal lines (the sources or drains of through FETs Q_T 1  to Q_T 3 ), thereby setting the DC potential of internal signals at a desired power supply voltage Vdd. 
   Similarly, as a modification of the third embodiment, it is also possible, as shown in  FIG. 7 , to newly form a power supply terminal Vdd, and connect a resistive element R 2  having a resistance value by which no RF signals leak, between the power supply terminal Vdd and internal signal lines (the sources or drains of through FETS Q_T 1  to Q_T 3 ), thereby setting the DC potential of internal signals at a desired power supply voltage Vdd. The same effects as in the first to fourth embodiments described above can be achieved in this modification as well. 
   Furthermore, to improve the RF characteristics, the through FETs and shunt FETs in the above embodiments are desirably FETs formed on a compound semiconductor substrate.