Abstract:
An ESD protection circuit is disclosed. The ESD protection circuit includes a stacked MOS circuit, and a trigger current generator. The object of the stacked MOS circuit is to be the first releasing path of the ESD current; the object of the trigger current generator is to generate the trigger current to turn on the stacked MOS circuit, and then the stacked MOS circuit would be the first releasing path of the ESD current.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to an ESD protection circuit, and more particularly relates to an ESD protection circuit that utilizes low voltage sensible components for being a releasing path of the ESD current.  
         [0003]     2. Description of the Prior Art  
         [0004]     Because of the minuteness of the circuit components and the improvement in precision of the electronic apparatus, the apparatus, the minute electric components inside especially are very sensitive and need protection against the static electricity that is induced by the working environment or touch of a user.  
         [0005]     Therefore, most of the precise electric apparatus needs additional design of an ESD protection circuit for suitably releasing static electricity that may occur and protecting the electric components of the circuit in the apparatus against the damage of the high voltage induced by ESD.  
         [0006]     An I-V graph of a typical stacked NMOS ESD protection circuit is illustrated in  FIG. 1 . Referring to  FIG. 1 , the horizontal coordinate is the voltage difference between the source and the drain and the vertical coordinate is the current of the drain. According to the graph, when the voltage difference between the source and the drain increases, the current of the drain increases correspondingly. After the voltage difference between the source and the drain exceeds a trigger voltage value, the punch through effect will occur that makes the voltage difference start to snap-back till the voltage difference decrease to a holding voltage value. The voltage difference range from the trigger voltage to the holding voltage is called snap-back region. Furthermore, after the voltage difference between the source and the drain decrease to the holding voltage, the voltage difference will increase smoothly, and the current of the drain will increase correspondingly.  
         [0007]     Following the description above, when the static electricity voltage exceeds the trigger voltage value, the punch through effect will happen and result in electric conduction of the stacked NMOS as an ESD protection circuit, so the static electricity current is released to the ground through the stacked NMOS. Thus the electric components have been protected against the damage of ESD. However, there are disadvantages for the typical NMOS ESD protection circuit: If the static electricity voltage does not exceed the trigger voltage value, then the ESD protection circuit will not conduct electrically, i.e. the static electricity current will not be released and it will be constantly held in the electric apparatus. It is a instable factor and the user cannot predict when the electric apparatus will be seriously damaged.  
         [0008]     A typical stacked NMOS ESD protection circuit in a IC is illustrated in  FIG. 2 . The object of the IC is to connect semiconductor chips or interfaces of a subsystem that work with different voltages. Therefore there is mixed-voltage inside the IC and the voltage values are Vdd and Vss respectively. Referring to  FIG. 2 , a I/O pad of the IC is connected to the inner circuit and the drain of the first NMOS (N 1 ), the gate of N 1  is connected to the power supply Vdd, the source of N 1  is connected to the drain of the second NMOS (N 2 ), the gate of N 2  is connected to the power supply Vss and the source of N 2  is connected to the ground.  
         [0009]     Still referring to  FIG. 2 , N 1  and N 2  are connected with cascade configuration and the nodes between them become a common diffusion region as there is a parasite lateral NPN bipolar transistor existed inside the stacked NMOS. When the static electricity voltage exceeds the trigger voltage value, the lateral NPN bipolar transistor will conduct electrically and the static electricity current can be released from the inner circuit. However referring to  FIG. 1 , if the static electricity voltage does not exceed the trigger voltage value, then the lateral NPN bipolar transistor will not conduct electrically, the static electricity current will not be released and it will be constantly held in the IC. And because the breakdown voltage of the MOS gate oxide decrease in a mixed voltage I/O circuit, finally the static electricity current held in the IC will result in damage of the MOS gate oxide that belongs to the I/O buffer inside the I/O pad.  
         [0010]     Considering in a typical ESD protection circuit of above description, when the static electricity exists in the circuit but does not exceed the trigger voltage, the protection circuit will not be active. Thus a protection circuit that is more sensitive to detect and release static electricity is needed for releasing the static electricity that does not exceed the trigger voltage and protecting the components inside the circuit against damage.  
       SUMMARY OF THE INVENTION  
       [0011]     Because of the disadvantages of the typical ESD protection circuit, it is therefore a primary object of the present invention to provide an ESD protection circuit that is more sensitive to release static electricity and reacts to the smaller static electricity voltage instantly.  
         [0012]     There is another object of the present invention to provide an ESD protection circuit that is constituted by the low withstanding voltage components and able to carry high voltage static electricity that the static electricity can pass through the circuit and be released.  
         [0013]     According to abovementioned objects, the present invention provides an ESD protection circuit that comprises mainly a stacked MOS circuit and a trigger current generation circuit. The object of the stacked MOS circuit is to be the first releasing path of static electricity current; and the object of the trigger current generation circuit is to generate trigger current that makes the stacked MOS circuit electrically conductive that the stacked MOS circuit becomes the first releasing path of static electricity.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]      FIG. 1  is an I-V graph of a typical stacked NMOS ESD protection circuit.  
         [0015]      FIG. 2  is a circuit diagram of a typical stacked NMOS ESD protection circuit.  
         [0016]      FIG. 3  is an ESD protection circuit diagram of a preferred embodiment of the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0017]     The following detailed description of the present invention describes the ESD protection circuit necessary to provide an understanding of the present invention, but does not cover a complete structure composition and the operating theory. While embodiments are discussed, it is not intended to limit the scope of the present invention. Except expressly restricting the amount of the components, it is appreciated that the quantity of the disclosed components may be greater than that disclosed.  
         [0018]     An ESD protection circuit is disclosed in the present invention. The circuit can be utilized inside IC that works with mixed power supplies. And the object of the IC usually is to connect semiconductor chips or interfaces of subsystem that work with different voltages, so there are mixed voltages inside the IC. An ESD protection circuit diagram of a preferred embodiment of the present invention is illustrated in  FIG. 3 . The circuit comprises: a trigger current generation circuit  10 , a stacked MOS circuit  20 , and a diode D 1 .  
         [0019]     Wherein the current generation circuit  10  comprises: a first resistor R 1 , a second resistor R 2 , a third resistor R 3 , a first capacitor C 1 , a second capacitor C 2 , a third capacitor C 3 , a fourth capacitor C 4  and a third NMOS N 3 . And the stacked MOS circuit  20  comprises: a fourth NMOS N 4  and a fifth NMO 4  N 5 . Referring to  FIG. 3 , the first end of the first resistor R 1  and the first end of the third resistor R 3  are connected to the first power supply (Reg3.3 volt), and the second end of the first resistor R 1  is connected to the first end of the first capacitor C 1 . The second end of the first capacitor C 1 , the source of N 3 , the second end of the second resistor R 2 , the source of N 5 , and the positive electrode of the diode D 1  are connected to the ground (i.e. VSS). And in the embodiment the first capacitor C 1 , the second capacitor C 2 , the third capacitor C 3 , and the fourth capacitor C 4  are all composed of PMOS. However, the present invention is not limited to PMOS for the capacitors; for instance, the capacitors can be composed of NMOS. Furthermore, the first resistor R 1 , the second resistor R 2 , and the third resistor R 3  are not only limited to resistor; for instance, the resistors can be composed of other impedances like transistors.  
         [0020]     The second end of the first resistor R 1  is connected to the gate of N 3 , and the substrate of N 3  is connected to the source of N 3 . The drain of N 3 , the first end of the second resistor R 2 , the second end of the third capacitor C 3 , and the gate of N 5  are connected to each other. The first end of the third capacitor C 3  is connected to the second end of the second capacitor C 2 . The first end of the second capacitor C 2 , the first end of the fourth capacitor C 4 , the drain of N 4 , and the negative electrode of the diode D 1  are all connected to the second power supply (Reg5 volt). The second end of the fourth capacitor C 4  is connected to the second end of the third resistor R 3  and the gate of N 4  at the same time. The substrate of N 4 , N 5  and the drain of N 5  are mutually connected. The source of N 4  is connected to the drain of N 5 .  
         [0021]     In one of the preferred embodiments, every pad in an IC has an ESD protection circuit as  FIG. 3 . If exterior static electricity enters the ESD protection circuit through the first and the second power supply when the IC chip is not coupled onto a printed circuit board (PCB), then there is voltage at node A and B that makes N 4  and N 5  electrically conductive in the stacked NMOS circuit  20 . Thus the ESD current will release to the ground through the stacked NMOS circuit  20 . When the IC chip is coupled onto the PCB, the practical voltage enters through the first power supply and the second power supply respectively. Thus the voltage at the node A equals to the voltage at the first power supply, and therefore N 4  is electrically conductive; however the voltage at node C equals to the voltage at the first power supply, thus N 3  conducts electrically. Therefore the voltage at the drain of N 4  equals to the voltage at the source of N 4 , and N 4  can be thought as the ground. Because node B connects the ground, the voltage at node B results in no electrically conduction of N 5 . When N 5  is not electrically conductive, the inner circuit of the IC (not shown in  FIG. 3 ) works normally and is not affected by the ESD protection circuit because of the electric leakage in the circuit.  
         [0022]     Furthermore, the stacked MOS circuit  20  of the present invention is not limited to the NMOS components. In another preferred embodiment of the present invention, the stacked MOS circuit  20  can be made by PMOS components. And because there is a parasite diode in the stacked MOS circuit  20 , the diode D 1  in  FIG. 3  can be ignored.  
         [0023]     The foregoing description is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obvious modifications or variations are possible in light of the above teachings. In this regard, the embodiment or embodiments discussed were chosen and described to provide the best illustration of the principles of the invention and its practical application to thereby enable one of ordinary skill in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly and legally entitled.