Abstract:
An improved digital signal processor, in which arithmetic multiply-add instructions are performed faster with substantial accuracy. The digital signal processor performs multiply-add instructions with look-ahead rounding, so that rounding after repeated arithmetic operations proceeds much more rapidly. The digital signal processor is also augmented with additional instruction formats which are particularly useful for digital signal processing. A first additional instruction format allows the digital signal processor to incorporate a small constant immediately into an instruction, such as to add a small constant value to a register value, or to multiply a register by a small constant value; this allows the digital signal processor to conduct the arithmetic operation with only one memory lookup instead of two. A second additional instruction format allows the digital signal processor to loop back to a location relatively addressed from the looping instructions; this allows the digital signal processor to conduct the loop operation with only one memory lookup instead of two.

Description:
This is a continuation of application Ser. No. 08/657,555 filed Jun. 4, 1996, now U.S. Pat. No. 6,128,726. A marked-up version of the prior allowed page is also submitted. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to an improved digital signal processor. 
     2. Description of Related Art 
     A digital signal processor (DSP) performs computations which generally require large numbers of arithmetic operations to be performed rapidly. Because it is desirable for arithmetic operations to be performed as rapidly as possible, it is desirable to find ways for the DSP use fewer processor cycles to perform a given set of arithmetic operations, or to perform more arithmetic operations in a given number of processor cycles. 
     One operation which is often performed by a digital signal processor is to multiply two numbers together and add the product to an accumulating sum. This operation is particularly important for audio and video applications, such as for example in computing vector dot products. In audio and video applications, it is desirable to perform many such operations at high speed and with substantial accuracy. 
     Accordingly, it would be advantageous to provide a digital signal processor which can perform certain arithmetic operations at high speed and with substantial accuracy. 
     SUMMARY OF THE INVENTION 
     The invention provides an improved digital signal processor, in which arithmetic multiply-add instructions are performed faster with substantial accuracy. In a preferred embodiment, the digital signal processor performs multiply-add instructions with look-ahead rounding, so that rounding after repeated arithmetic operations proceeds much more rapidly. 
     In a preferred embodiment, the digital signal processor is also augmented with additional instruction formats which are particularly useful for digital signal processing. A first additional instruction format allows the digital signal processor to incorporate a small constant immediately into an instruction, such as to add a small constant value to a register value, or to multiply a register by a small constant value; this allows the digital signal processor to conduct the arithmetic operation with only one memory lookup instead of two. A second additional instruction format allows the digital signal processor to loop back to a location relatively addressed from the looping instructions; this allows the digital signal processor to conduct the loop operation with only one memory lookup instead of two. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A shows a block diagram of an arrangement for look-ahead rounding for arithmetic operations. 
     FIG. 1B shows a diagram of an instruction sequence for look-ahead rounding for arithmetic operations. 
     FIG. 1C shows a flow diagram of the method for look-ahead rounding for arithmetic operations. 
     FIG. 2A shows a diagram of a loop-relative instruction format. 
     FIG. 2B shows a flow diagram for a method of interpretation of the loop-relative instruction format. 
     FIG. 2C shows a diagram of a program fragment employing the loop-relative instruction format. 
     FIG. 3A shows a diagram of a short-immediate instruction format. 
     FIG. 3B shows a flow diagram for a method of interpretation of the short-immediate instruction format. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In the following description, a preferred embodiment of the invention is described with regard to preferred process steps and data structures. However, those skilled in the art would recognize, after perusal of this application, that embodiments of the invention may be implemented using a set of general purpose computers operating under program control, and that modification of a set of general purpose computers to implement the process steps and data structures described herein would not require undue invention. 
     L OOK -A HEAD  R OUNDING OF  A RITHMETIC  O PERATIONS    
     FIG. 1A shows a block diagram of an arrangement for look-ahead rounding for arithmetic operations. 
     An arrangement  100  for look-ahead rounding for arithmetic operations comprises a first input port  101  for a first input data value, a second input port  102  for a second input data value, and an output port  103  for an output data value. 
     In a preferred embodiment, the first input port  101  is 16 bits wide and the first data value is interpreted in two&#39;s-complement integer notation; thus the first data value may range from −32,768 (i.e., −2 16 ) to +32,767 (i.e., 2 16 −1). The second input port  101  is similarly 16 bits wide and the second data value is similarly interpreted in two&#39;s-complement integer notation. 
     The first input port  101  and the second input port  102  are coupled to respective inputs of a multiplier  110 , which multiplies the two values and produces a 32 bit data value on a product bus  111 . 
     The product bus  111  is coupled to a first input of an adder  120 . The adder  120  produces a 40 bit output on a sum bus  121 , which is coupled to an accumulator register  130 . 
     The accumulator register  130  is divided into a most significant portion  131 , a middle portion  132 , and a least significant portion  133 . In a preferred embodiment, the most significant portion  131  is 8 bits wide, i.e., bit  35  through bit  32  inclusive, the middle portion  132  is 16 bits wide, i.e., bit  31  through bit  16  inclusive, and the least significant portion  133  is 16 bits wide, i.e., bit  15  through bit  0  inclusive. Thus, the accumulator register  130  is 40 bits wide. All three portions of the accumulator register  130  are fed back to the adder  120  at a second input thereof. 
     The middle portion  132  is coupled to the output port  103 , which is also 16 bits wide; the output data value is interpreted in two&#39;s-complement integer notation. 
     When computing a dot product, the first input port  101  is coupled to a first sequence of 16 first input data values and the second input port  102  is coupled to a second sequence of 16 second input data values. After N multiply-add operations, the accumulator register  130  contains the sum of products for the first N pairs of data values. Thus, after 15 multiply-add operations, the accumulator register  130  contains the sum of products for the first 15 pairs of data values. 
     When the sequence of data values at the first input port  101  and the sequence of data values at the second input port  102  are scaled appropriately, data value in the register  103  comprises 16 bits of results at the middle portion  132 , 16 bits of roundoff at the least significant portion  133 , and 8 bits of saturation at the most significant portion  131 . 
     The existence of roundoff implies that the results differ slightly from exact accuracy, in an amount which varies between (−1) (LSB) and zero, where LSB is the value of the least significant bit of results, i.e., bit  16  of the accumulator register  130 . Thus, the results which are coupled to the output port  103  may be inaccurate in the least significant bit. 
     To mitigate this inaccuracy, a rounding register  140  comprises a rounding value which is loaded into the accumulator register  130  before any multiply-add operations are performed. In a preferred embodiment, the rounding value is loaded into the accumulator register  130  before simultaneously with triggering operation of the multiplier  110 , so there is no time delay for the operation of loading the accumulator register  130 . 
     In a preferred embodiment, the rounding value comprises a value which represents (½)(LSB), where LSB is the value of the least significant bit of results. Thus, when using two&#39;s complement notation, the rounding value comprises “1000 0000 0000 0000” in binary, i.e., bit  15  of the rounding value is 1 and bit  14  through bit  0  of the rounding value are 0. 
     When the look-ahead rounding value is pre-loaded into the accumulator register  130 , the results still differ slightly from exact accuracy, but only in an amount which varies between (−½)(LSB) and almost (+½)(LSB). Thus, the results which are coupled to the output port  103  should be accurate in the least significant bit. There is only a tiny amount of bias toward the negative because the 16 bit value for roundoff at the least significant portion  133  varies between −(32,768)/(32,768) (i.e., negative 1), and +(32,767)/(32,768) (i.e., positive 1-2 16 ). 
     In alternative embodiments, the rounding value may be adjusted to eliminate even this bias, such as by toggling bit  0  of the rounding value for alternate look-ahead rounding operations, or by supplying a random or pseudorandom value for bit  0  of the rounding value in successive look-ahead rounding operations. 
     FIG. 1B shows a diagram of an instruction sequence for look-ahead rounding for arithmetic operations. 
     An instruction sequence  150  for computing a dot product of two vectors comprises a repeat instruction  151  and a multiply-add instruction  152 . The repeat instruction  151  comprises an opcode field  153 , count field  154 , and a rounding field  155 . The multiply-add instruction  152  comprises an opcode field  153  and two register fields  156 . 
     The opcode field  153  designates the instruction type; it has a first value for the repeat instruction  151  and a second value for the multiply-add instruction  152 . 
     The count field  154  designates how many times the multiply-add instruction  152  is to be performed. 
     The rounding field  155  designates whether look-ahead rounding is to be performed. In a preferred embodiment, the rounding field  155  comprises a single bit which designates whether the accumulator register  130  is to be pre-loaded with the rounding value. 
     The register fields  156  designate a first register which points to the first sequence of data values and a second register which points to the second sequence of data values. In a preferred embodiment, the registers are each incremented as the sequences of data values are loaded. 
     FIG. 1C shows a flow diagram of the method for look-ahead rounding for arithmetic operations. 
     A method  160  for look-ahead rounding comprises the steps  161  through  163  inclusive. 
     At a step  161 , the rounding value is loaded into the accumulator register  130 . 
     At a step  162 , the multiply-add operation is performed with a corresponding of data values. The step  162  is repeated N times if there are N pairs of data values, where N is preferably  16 . 
     At a step  163 , the middle portion  132  of the accumulator register  130  is output. There is no requirement for a separate rounding step and the output value may be directly coupled for downstream operation in the digital signal processor. 
       LOOP - RELATIVE  I NSTRUCTION  F ORMAT    
     FIG. 2A shows a diagram of a loop-relative instruction format. 
     A loop-relative instruction  200  comprises a single instruction word having 16 bits, ordered from a most significant bit  15  to a least significant bit  0 . The loop-relative instruction  200  comprises an opcode field  210 , an offset field  220 , and a count field  230 . 
     The opcode field  210  of the loop-relative instruction  200  comprises bit  15  through bit  12  inclusive. One specific value of the opcode field  210 , such as a hexadecimal “F”, indicates that the instruction is a loop-relative instruction  200 . 
     The offset field  220  of the loop-relative instruction  200  comprises bit  11  through bit  6  inclusive. The offset field  220  designates an unsigned binary integer having a value from 0 to 63 inclusive. The offset field  220  represents an offset from the loop-relative instruction  200  to a final instruction of a program loop. 
     The count field  230  of the loop-relative instruction  200  comprises bit  5  through bit  0  inclusive. The count field  230  designates an unsigned binary integer having a value from 0 to 63 inclusive. The count field  230  represents a count of the number of times the digital signal processor will execute the program loop. 
     FIG. 2B shows a diagram of a program fragment employing the loop-relative instruction format. 
     A program loop  240  comprises a sequence of instructions  241 , beginning with a loop instruction  242  at a loop-begin location  243 , and ending at a loop-ending location  244 . In alternative embodiments, the loop-ending location  244  may refer either to the last instruction to be executed as part of the loop, or to the first instruction to be executed after the loop is completed. 
     The opcode field  210  of the loop-relative instruction  200  indicates that the program fragment  240  comprises a loop. 
     The offset field  220  of the loop-relative instruction  200  indicates the relative offset of the loop-ending location  244  from the loop-begin location  243 , i.e., the length of the program fragment  240  in bytes or instruction words. 
     The count field  230  of the loop-relative instruction a  200  indicates the number of times the program fragment  240  is to be executed. 
     FIG. 2C shows a flow diagram for a method of interpretation of the loop-relative instruction format. 
     When the digital signal processor recognizes a loop-relative instruction  200 , it notes the loop-begin location  243  (i.e., the program counter for the location at which the loop-relative instruction  200  was found), and records three items of information in a loop register  250 . 
     First, the digital signal processor determines the loop-ending location  244 , i.e., the program counter for the location at which the loop ends. The digital signal processor determines the loop-ending location  244  by simply adding the value for the offset field  230  to the value for the loop-begin location  243 . The digital signal processor records this value in a target program counter field  251  of the loop register  250 . 
     Second, the digital signal processor determines an offset from the loop-ending location  244  back to the loop-begin location  243 . The digital signal processor determines the offset by simply using the value for the offset field  230 . The digital signal processor records this value in an offset field  252  of the loop register  250 . 
     Third, the digital signal processor determines a count of the number of times the loop should be executed. The digital signal processor determines the count by simply using the value for the count field  240 . The digital signal processor records this value in a count field  253  of the loop register  250 . 
     While executing the program fragment  240 , as with executing other instructions, the digital signal processor maintains a program counter  260  which designates the specific instruction to be next executed. The digital signal processor updates the program counter  260  for each instruction. For each instruction in the program fragment  240 , the digital signal processor compares the program counter  260  against the target program counter field  251  of the loop register  250 . 
     Whenever the program counter  260  equals the target program counter field  251 , normal incrementing of the program counter does not occur and the digital signal processor alters the flow of control so the next instruction is from the beginning of the program fragment  240 . To perform this operation, the digital signal processor subtracts the offset value  252  of the loop register  250  to form a replacement program counter value, and replaces the program counter with than new value. 
     Each time this occurs, the digital signal processor decrements the count value, to indicate that the program fragment  240  has been executed one more time. When the count value reaches zero, the program fragment  240  has been executed the correct number of times, and normal flow of control, i.e., normal incrementing of the program counter occurs at the end of the program fragment  240 . 
     S HORT -I MMEDIATE  I NSTRUCTION  F ORMAT    
     FIG. 3A shows a diagram of a short-immediate instruction format. 
     A short-immediate instruction  300  comprises a single instruction word having 16 bits, ordered from a most significant bit  15  to a least significant bit  0 . The short-immediate instruction  300  comprises an opcode field  310  and an immediate field  320   
     The opcode field  310  of the short-immediate instruction  300  comprises bit  16  through bit  8  inclusive. The opcode field  310  represents one of a set of arithmetic operations which may be performed on designated registers and a constant value designated by the immediate field  320 . 
     For example, the arithmetic operation specified by the opcode field  310  may be an ADD operation, so that the constant value designated by the immediate field  320  is added to a designated register. 
     In a preferred embodiment, the designated registers are the registers A 0  and A 1  in a set of registers, the operation is performed on the value stored in register A 1  and a result of the operation is stored in register A 0 . In alternative embodiments, other designated registers could be used, or the designated registers could be selected in response to the opcode field  310  or another field of the short-immediate instruction  300 . 
     The immediate field  320  of the short-immediate instruction  300  comprises bit  6  through bit  0  inclusive. In a preferred embodiment, the immediate field  320  is coded to represent numeric values other than the binary value of those bits. In a preferred embodiment, these numeric values are optimized for values used in MPEG audio processing, but in alternative embodiments other sets of values, or values optimized for other processing tasks, may be used. 
     Table 3-1 shows the coding of the immediate field  320 . In table 3-1, bit b 0 =bit  0 , bit b 1 =bit  1 , bit  2 =bit  2 , bit b 3 =bit  3 , bit b 4 =bit  4 , bit b 5 =bit  5 , bit b 6 =bit  6 , and bit b 7 =bit  7 . 
     
       
         
               
               
               
             
           
               
                   
                 TABLE 3-1 
               
               
                   
                   
               
               
                   
                 immediate field 
                 coded value 
               
               
                   
                   
               
             
             
               
                   
                 0 b5 b4 b3 b2 b1 b0 
                 positive value 0 through 63 in- 
               
               
                   
                   
                 clusive, as represented by six- 
               
               
                   
                   
                 bit value b5 b4 b3 b2 b1 b0 
               
               
                   
                 1 1 b4 b3 b2 b1 b0 
                 negative value −32 through −1 
               
               
                   
                   
                 inclusive, as represented by 
               
               
                   
                   
                 five-bit value b4 b3 b2 b1 b0 
               
               
                   
                 1 0 0 b3 b2 b1 b0 
                 single one of 16 bits “1”, all 
               
               
                   
                   
                 others “0”, choice of single 
               
               
                   
                   
                 bit represented by the four-bit 
               
               
                   
                   
                 value b3 b2 b1 b0 
               
               
                   
                 1 0 1 b3 b2 b1 b0 
                 single one of 16 bits “0”, all 
               
               
                   
                   
                 others “1”, choice of single 
               
               
                   
                   
                 bit represented by the four-bit 
               
               
                   
                   
                 value b3 b2 b1 b0 
               
               
                   
                   
               
             
          
         
       
     
     FIG. 3B shows a flow diagram for a method of interpretation of the short-immediate instruction format. 
     At a flow point  350 , the digital signal processor fetches an instruction having the short-immediate instruction format, and is about to interpret that instruction. 
     At a step  351 , the digital signal processor decodes the opcode field  310  and determines the operation to be performed. 
     At a step  352 , performed in parallel with the step  351 , the digital signal processor decodes the immediate field  320  and determines the constant with which the operation is to be performed. 
     At a step  353 , performed after the step  351  and the step  352 , the digital signal processor performs the operation determined by the opcode field  320  on the designated registers with the constant determined by the immediate field  330 . 
     At a flow point  360  after the step  353 , the instruction having the short-immediate format is complete. 
     Alternative Embodiments 
     Although preferred embodiments are disclosed herein, many variations are possible which remain within the concept, scope, and spirit of the invention, and these variations would become clear to those skilled in the art after perusal of this application.