Abstract:
Integrated television receivers with I and Q analog to digital converters on the integrated circuit. The television receivers may be nearly fully integrated, typically with one or more filter elements such as one or more inductors off chip. Single conversion and double conversion versions of the invention are disclosed. In single conversion versions, conversion to baseband is disclosed. In double conversion versions, conversion first upward to a high IF frequency, and then conversion to baseband is disclosed. Various other features are disclosed.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to the field of analog and digital television receivers and broadband data receivers.  
         [0003]     2. Prior Art  
         [0004]     The present state of art in television receivers is a single-conversion or dual-conversion architecture with a balanced IF output, requiring at least one IF (intermediate frequency) SAW (surface acoustic wave) filter and subsequent gain stage to drive an analog demodulator or external Analog-to-Digital Converter (ADC), which is typically in a demodulator integrated circuit.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]      FIG. 1  is a block diagram of a television receiver in accordance with one embodiment of the present invention.  
         [0006]      FIGS. 2   a  through  2   c  illustrate a High-IF filter using integrated and/or external inductors and switched-capacitor array filters, a circuit illustrating the capacitor switching and a graph illustrating a typical frequency response for the filter, respectively.  
         [0007]      FIG. 3  is a block diagram of a television receiver similar to that of  FIG. 1 , though having analog-to-digital converters that are a pipeline type with a parallel output.  
         [0008]      FIGS. 4 and 5  illustrate single conversion embodiments of the present invention.  
         [0009]      FIG. 6  illustrates further signal processing that may be done in the demodulator.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0010]     Now referring to  FIG. 1 , a block diagram of a receiver having two receiver inputs, a cable input and an antenna input having both a VHF input pin and a UHF input pin, may be seen. One of the three inputs are band pass filtered, amplified and sent to the Up-Converter mixer  20 . The mixer  20 , as well as the I and Q down shifting mixers  22  and  24 , use frequency references from local oscillators LO 1  and L 02  controlled by the externally controlled Dual Synthesizer. Local oscillator L 02  generally operates at a constant frequency to down shift the output of the HI-IF filter to baseband, while local oscillator LO 1  varies, depending on the channel selection, causing mixer  20  to up-shift the desired channel to the band pass frequency of the HI-IF filter.  
         [0011]     From the mixer  20 , the converted signals are filtered by the High-IF filter. This filter can be a simple bandpass filter, using integrated and/or external inductors and switched-capacitor array filters.  
         [0012]     An example of a High-IF filter using integrated and/or external inductors and on-chip switched-capacitor array filters may be seen in  FIG. 2   a . The inductors for the filter may be microstrip printed inductors on a printed wiring board to which the integrated circuit is mounted. Tuning for the filter may be by way of capacitor switching, three capacitor switching being illustrated in  FIG. 2   b , though more may be provided if desired. The switches may be controlled, typically through the serial interface at the time an entire TV receiver is assembled, to tune the circuit for the desired frequency response, given reasonable fabrication tolerances on the switched capacitors themselves and the external inductors. A typical filter response is illustrated in  FIG. 2   c , where the desired frequencies (M 1 ) are passed with little attenuation and the image frequencies (M 2 ) are highly attenuated.  
         [0013]     The output of the HI-IF filter is amplified and then down converted to baseband by I and Q mixers  22  and  24 . Following the mixers is an amplifier for each of the I and Q channels and a low-order low-pass filter to further attenuate adjacent channels and serve as an anti-alias filter. Next is a VGA (variable gain amplifier) in each channel which drives an analog to digital converter for that channel, either a single bit or multiple bit Sigma-Delta data ADC or modulator, or a track-and-hold pipeline ADC. The output of the ADC is a bit-stream. For a Sigma-Delta ADC, the bit-stream is converted to a balanced, low-voltage differential signal by the LVDS circuit, which communicates to an off chip digital demodulator.  
         [0014]     The circuit shown in  FIG. 3  is similar to that of  FIG. 1 , but the analog-to-digital converters are pipeline type with a parallel output. The pipeline ADCs, having a much lower data-rate, can have the two bit-streams multiplexed together as shown for transfer of the data to the demodulator. This reduces the number of I/O pins for the receiver and the demodulator integrated circuits.  
         [0015]     Alternatively, a single (direct) conversion approach can be used (see  FIGS. 4 and 5 ) with the incorporation of integrated tracking filters consisting of monolithic high-Q inductors and switched capacitor arrays. Several tracking filters  36  are used in a sub-banding configuration to cover the entire VHF and UHF TV bands. Each filter is tunable over a limited frequency range, with the one filter for any one desired frequency being switched into the circuit and tuned as required. The circuits shown in  FIGS. 4 and 5  show such direct conversion receivers incorporating both pipe-line and sigma-delta ADC structures, respectively.  
         [0016]     Thus the present invention introduces a zero IF, eliminating the need for an IF SAW filter, and also incorporates I and Q channel ADCs on the receiver integrated circuit. The result is an RF-to-Bits solution, eliminating the need for ADCs within the demodulator ICs, simplifying the continuous transition to ever smaller CMOS device geometries and lower supply voltages. IF SAW filters and IF VGA stages are also eliminated, further simplifying the board-level design.  
         [0017]     Additionally, a High-IF filter is also integrated, using inductors, capacitors, and switched-capacitor arrays to form a filter on-die, or by using a fcLGA (flip chip land grid array) where external printed inductors are used along with on-die switched capacitor arrays that together form a high-IF filter.  
         [0018]     The present invention may be extended whereby additional signal processing occurs within the digital demodulator, which may simply be a DSP (digital signal processor). This additional signal processing would be defined by the particular implementation of the RF receiver and Analog to Digital Converters. This may include, but is not limited to, clock recovery, decimation of the receiver output bit stream(s), adaptive equalization of the output bit streams(s) and additional interference filtering in the digital domain. By way of example,  FIG. 6  schematically illustrates a receiver integrated circuit  30 , the additional signal processing in block  32 , and demodulation. Since the signals are received and all of the functions in blocks  32  and  34  are in the digital domain, the functions of both blocks  32  and  34  may be carried out in a digital signal processor without requiring an analog to digital interface on the DSP chip or as a separate chip between the receiver chip and the DSP. Thus the receiver can be used as a multimode receiver for analog and/or digital television and/or for data.  
         [0019]     While certain preferred embodiments of the present invention have been disclosed and described herein, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention. Similarly, the various aspects of the present invention may be advantageously practiced by incorporating all features or various sub-combinations of features.