Abstract:
A layout of a semiconductor device is disclosed, which forms one transistor in one active region to reduce the number of occurrences of a bridge encountered between neighboring layers, thereby improving characteristics of the semiconductor device. Specifically, the landing plug connected to the bit line contact is reduced in size, so that a process margin of word lines is increased to increase a channel length, thereby reducing the number of occurrences of a bridge encountered between the landing plug and the word line.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The priority of Korean patent application No. 10-2009-0000423 filed Jan. 5, 2009, the disclosure of which is hereby incorporated in its entirety by reference, is claimed. 
       BACKGROUND OF THE INVENTION 
       [0002]    The present invention relates to a layout of a semiconductor device. 
         [0003]    Generally, a semiconductor device forms two transistors in one active region using an active region of I-type or G-type, so that it results in a “one active region and two capacitors therein” structure. However, the “one active region and two capacitors therein” structure encounters a bridge problem between neighboring patterns so that it unavoidably deteriorates characteristics of a semiconductor device. In more detail, with the increasing degree of integration of a semiconductor device, higher-aspect-ratio patterns are laminated in the semiconductor device. In this case, some patterns fall down so that they bridge neighboring patterns, resulting in a deterioration of characteristics of the semiconductor device. In brief, this problem is generally referred to as a bridge problem. 
         [0004]      FIG. 1  is a plan view illustrating the layout of a semiconductor device according to the related art.  FIGS. 2A to 2D  are cross-sectional views illustrating a method for forming a semiconductor device according to the related art. 
         [0005]    Referring to  FIG. 1 , an active region  14 , a word line  16 , landing plugs  22   a  and  22   b,  a bit line contact  26 , a bit line  27 , and a storage electrode contact (not shown) are formed on a semiconductor substrate  10 . The active region  14  is defined by a device isolation region  12 . The word line  16  vertically traverses the active region  14  to be trisected. The landing plugs  22   a  and  22   b  are formed on each trisected active region  14 . The bit line contact  26  is connected to the landing plug  22   a  located at the center of the trisected active region  14 , and is arranged in parallel to the word line  16 . The bit line  27  is connected to the bit line contact  26 , and is arranged perpendicular to the word lines  16 . The storage electrode contact (not shown) is connected to the trisected landing plugs  22   b.  For convenience of explanation, detailed description of the layout of the conventional semiconductor device will be limited only up to the storage electrode contacts (not shown). 
         [0006]    Referring to  FIG. 2A , an active region  14  defined by a device isolation region  12  is formed on a semiconductor substrate  10 , and a conductive layer and a hard mask layer are deposited on the active region  14  and then patterned, so that the word line  16  including a spacer  18  is formed on the active region  14 . 
         [0007]    Referring to  FIG. 2B , after an interlayer insulating layer  20  is formed on an overall upper surface including the word line  16 , and then selectively removed to form a recess and expose the active region  14 . Then, conductive material is filled in the recess and contacts the exposed active region  14  to form landing plugs  22   a  and  22   b.  In this case, if the spacer formed at the sidewalls of the word line is removed due to misalignment, the word line  16  becomes electrically connected with the landing plugs  22   a  or  22   b,  and thus an electrical short may occur. In this case, the landing plugs are classified into one landing plug  22   a  connected to a bit line and another landing plug  22   b  connected to a storage electrode. 
         [0008]    Referring to  FIG. 2C , a first interlayer insulating layer  24  is formed on the overall structure including the landing plugs  22   a  and  22   b,  and selectively etched to expose the landing plug  22   a  to form a bit line contact region. Then, conductive material is filled in the bit line contact region to form a bit line contact  26 . Even in this step, there is a possibility that the bit line contact  26  and the word line  16  are electrically connected due to misalignment. Thereafter, a bit line (not shown) is formed to be in contact with the bit line contact  26 . 
         [0009]    Referring to  FIG. 2D , a second interlayer insulating layer  28  is formed on an overall upper surface, and the first and second interlayer insulating layers  24 ,  28  are selectively etched to expose the landing plug  22   b.  Conductive material is formed on the exposed landing plug  22   b  to form a storage electrode contact  30 . 
         [0010]    The conventional semiconductor device having the above-mentioned layout structure has a disadvantage in that an electrical short occurs easily due to misalignment. In addition, as the distance between neighboring layers becomes shorter as a semiconductor device shrinks in size. 
       BRIEF SUMMARY OF THE INVENTION 
       [0011]    Various embodiments of the present invention are directed to provide a semiconductor device layout that substantially obviates limitations and disadvantages of the related art. According to the related art in which two transistors are formed in one active region, electrical connection between a word line and a landing plug may easily occur and this problem becomes more serious as a channel length of a semiconductor device becomes shorter. 
         [0012]    In accordance with an aspect of the present invention, a first active region provided on a substrate, the first active region having an “L” shape; 
         [0013]    a second active region provided adjacent to the first active region, the second active region having a mirrored “L” shape; and 
         [0014]    an isolation region separating the first active region and the second active region. The active region having the above-mentioned shapes increases a margin, resulting in the prevention of a bridge encountered between neighboring landing plugs. 
         [0015]    Preferably, the first active region is provided along a first row and the second active region is provided along a second row, the first and second active regions being symmetrically arranged to each other with respect to a column direction. 
         [0016]    Preferably, a first word line extending across over the first and second active regions; and 
         [0017]    a second word line extending across over the first and second active regions, the second word line being provided adjacent to the first word line, 
         [0018]    wherein the first word line includes a first extension extending in a first row direction and the second word line includes a second extension extending in a second row direction that is in an opposing direction to the first row direction. 
         [0019]    Preferably, the first and second active regions each has a short region and a long region, wherein the first and the second word line traverse over the long region of the first and second active regions, respectively. 
         [0020]    Preferably, the first and second word lines expose ends of each of the first and second active regions, the semiconductor device layout further comprising: 
         [0021]    a bit line landing plug formed over one end of each of the first and second active regions exposed by the first and second word lines; and a storage electrode landing plug formed over the other end of each of the first and second active regions exposed by the first and second word lines, 
         [0022]    wherein the bit line landing plug and the corresponding storage electrode landing plug are formed on opposite sides of each other with respect to the first or second word line. 
         [0023]    Preferably, the bit line landing plug and the corresponding storage electrode landing plug are on different lines. 
         [0024]    Preferably, the semiconductor device layout may further comprising: 
         [0025]    a bit line contact formed over and electrically connected to the bit line landing plug. 
         [0026]    Preferably, the semiconductor device layout may further comprising: 
         [0027]    a bit line arranged perpendicular to the first and the second word lines, 
         [0028]    wherein the bit line contact is no larger than the bit line landing plug. 
         [0029]    Preferably, the semiconductor device layout may further comprising: 
         [0030]    a storage electrode contact formed over and electrically connected to the storage electrode landing plug. 
         [0031]    Preferably, the semiconductor device layout wherein the device further comprises: 
         [0032]    a first storage electrode contact extending in one direction parallel to the row; and 
         [0033]    a second storage electrode contact extending in the opposite direction to the first storage electrode contact. 
         [0034]    Preferably, the first and the second storage electrode contact are shaped like a square. 
         [0035]    Preferably, the semiconductor device layout may further comprising: 
         [0036]    a first storage electrode formed over and electrically connected to the first storage electrode contact; and a second storage electrode formed over and electrically connected to the second storage electrode contact, 
         [0037]    wherein the first and the second storage electrode formed in zigzag format along the column direction. 
         [0038]    Preferably, the semiconductor device layout may further comprising: 
         [0039]    a first active region in an “L” shape formed in an odd row; 
         [0040]    a second active region in a mirrored “L” shape formed in an even row; 
         [0041]    a first word line running traversing over the first and second active regions an odd column and a second word running traversing over the first and second active regions in an even column, the first word line including an first extension extending in a first row direction and the second word line including a second extension extending in an opposite direction to the first extension; 
         [0042]    a bit line landing plug formed over one end of each of the first and second active regions exposed by the first and second word lines; and 
         [0043]    a storage electrode landing plug formed over the other end of each of the first and the second active regions exposed by the first and second word lines, 
         [0044]    wherein the bit line landing plug and the storage electrode landing plug are formed on opposite sides to each other with respect to the first or second word line. 
         [0045]    Preferably, the bit line landing plug and the storage landing plug electrically connected to the same active region are provided in different lines. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0046]      FIG. 1  is a plan view illustrating the layout of a semiconductor device according to the related art. 
           [0047]      FIGS. 2A to 2D  are cross-sectional views illustrating a method for forming a semiconductor device according to the related art. 
           [0048]      FIGS. 3A to 3G  illustrate the layouts of a semiconductor device according to embodiments of the present invention. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0049]    Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like element. 
         [0050]      FIGS. 3A to 3G  illustrate the layouts of a semiconductor device according to embodiments of the present invention. 
         [0051]    Referring to  FIG. 3   a,  an active regions  104  defined by a device isolation layer  102  is formed on a semiconductor substrate  100 . In this case, the active region  104  is formed to have an “L”-shaped structure in which a vertical axis (L) is short and a horizontal axis (W) is relatively long. In another embodiment, the vertical axis may be long and the horizontal axis is short. In yet another embodiment, the vertical axis and the horizontal axis is substantially the same. 
         [0052]    In the present embodiment, neighboring rows in a vertical direction are symmetrical to each other with respect to the vertical axis (L). For convenience of description, the direction of the horizontal axis (W) of the active region  104  is referred to as a “row.” A first row A 1  includes an “L”-shaped active region  104 , and a second row A 2  includes a “mirrored L”-shaped active region  104  which has a mirror image of “L” and is symmetrical to the “L”-shaped active region  104  of the first row A 1  with respect to the vertical axis (L). A third row A 3  includes an “L”-shaped active region  104  which is symmetrical to the “mirrored L”-shaped active region  104  of the second row A 2  with respect to the vertical axis (L). That is, the third row A 3  is configured as the first row A 1 . In this way, the active region  104  in each odd row has an “L” shape, and the active region  104  in each even row has a “mirrored L” shape which is symmetrical to the “L”-shape in each odd row with respect to the vertical axis (L). The reason why the active region is defined as described above is to provide an additional margin and prevent a bridge between neighboring landing plugs from occurring. 
         [0053]    Referring to  FIG. 3b , a word line  106  is arranged in parallel to the vertical axis (L) of the active region  104 . The word line  106  is formed along a short axis (L) of each active region  104 , and includes a first extended word line  106   a  or a second extended word line  106   b,  each of which is extended along a long axis (W) of the active region  104 . The first and the second extended word lines  106   a  and  106   b  of the word line  106  are extended along opposite directions from each other. Here, the short axis of the active region  104  is a vertical axis (L) of the active region  104 , and the long axis of the active region  104  is a horizontal axis (W) of the active region  104 . In other words, the word line  106  corresponding to a first column B 1  includes the first extended word line  106   a,  which is extended to the left side along the long axis of the active region  104  in each odd row (i.e., each of first and third rows A 1  and A 3 ). The word line  106  corresponding to a second column B 2  includes the second extended word line  106   b,  which is extended to the right side along the long axis of the active region  104  in each even row (i.e., the second row A 2 ). In this way, the word line  106  in each odd column has the first extended word line  106   a,  which is extended to the left side toward the active region  104  in each odd row. In addition, the word line  106  in each even column has the second extended word line  106   b,  which is extended to the right side toward the active region  104  in each even row. 
         [0054]    Referring to  FIG. 3   c,  a landing plug  108   a  and a second landing plug  108   b  are formed on the active region  104 . The first landing plug  108   a  is located at the end of the short axis of the active region  104 . In other words, the first landing plug  108   a  is located on both sides of the first extended word line  106   a  so as to connect to the active region  104 . The first landing plug  108   a  is connected to a bit line contact in a subsequent process. The second landing plug  108   b  is located at the end of the long axis of the active region  104 . In other words, the second landing plug  108   b  is located on the opposite side to the first landing plug  108   a  with respect to the word line  106  so as to electrically connect to the active region  104 . The second landing plug  108   b  is connected to the storage electrode contact in a subsequent process. In this manner, the first and the second landing plugs  108   a  and  108   b  are not formed on the same line, but are arranged in a zigzag manner at opposite sides of the word line  106 . 
         [0055]    Referring to  FIG. 3d , the bit line contact  110  is formed on the first landing plug  108   a.  The bit line contact  110  of  FIG. 3D  is formed in the same size as or smaller size than the first landing plug  108   a,  whereas a bit line contact shown in the related art ( FIG. 1 ) is configured in an oval shape extended along the direction of the word line to interconnect the landing plug and the bit line. That is, the first and the second landing plugs  108   a  and  108   b  are not formed on the same line according to the present invention, whereas the bit line contact and storage electrode contact are formed on the same line. Thus, the bit line contact of  FIG. 3D  may be formed in smaller size than that of the related art. Accordingly, it is possible to prevent a bridge between the misaligned bit line contact and the word line  106 . Preferably, a cross-sectional shape of the bit line contact  110  may be a square or a rectangle. 
         [0056]    Referring to  FIG. 3   e,  a bit line  112  is perpendicular to the word line  106  and is connected to the bit line contact  110 . Therefore, the bit line  112  is formed on the same line as that of the first landing plug  108   a.  A width (Wb) of each bit line  112  is adjusted to enlarge the area of a storage electrode contact connected to the second landing plug  108   b  by increasing the distance between the bit lines  112 . As a result, the margin of the storage electrode contact connected to the second landing plug  108   b  formed in the subsequent process may be increased. 
         [0057]    Referring to  FIG. 3   f,  a first storage electrode contact  114   a  in an odd row is arranged to be in electrical contact with the second landing plug  108   b  and extends along one direction, and a second storage electrode contact  114   b  in an even row is arranged to be in electrical contact with the storage electrode contact  114   a  and extends along the opposite direction of the first storage electrode contact  114   a.  The first storage electrode contact  114   a  and the second storage electrode contact  114   b  are arranged in opposite directions in order to increase a process margin required to form the storage electrode in a subsequent process. A cross-sectional shape of the first and second storage electrode contacts  114   a  and  114   b  may be a square or a rectangle. 
         [0058]    Referring to  FIG. 3   g,  a storage electrode  116  is formed on the end of the first and the second storage electrode contact  114   a  and  114   b.  Accordingly, the storage electrode  116  becomes electrically connected to the active region  104 . As described above, since the first and second storage electrode contacts  114   a  and  114   b  in an odd row and in an even row extend along opposite directions, the storage electrodes  116  in an odd row and an even row are arranged along different vertical axes from each other. Thus, a process margin for a semiconductor device may be increased. In addition, it is possible to prevent a semiconductor device from being deteriorated due to bridging. 
         [0059]    The active region is formed in an L shape in an odd row and in a reversed-L shape in an even row, so that the landing plug for a bit line contact and the landing plug for a storage electrode contact are located in different lines from each other. Such structure enables the landing plug connected to the bit line contact to be made smaller, thereby preventing bridging and allowing a longer channel length. 
         [0060]    The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the type of deposition, etching polishing, and patterning steps described herein. Nor is the invention limited to any specific type of semiconductor device. For example, the present invention may be implemented in a dynamic random access memory (DRAM) device or non volatile memory device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.