Abstract:
A reprogrammable fuse has a pair of non-volatile memory cells differentially programmed. The pair of non-volatile memory cells are connected to a pair of bitlines and through a pair of switches to a precharging voltage. The switches are controlled by a precharging and equalization signal, which when activated, serves to precharge the bitlines. The charged bitlines are then connected to the pair of differentially programmed non-volatile memory cells and one of the bitlines is discharged faster than the other. The resultant output is taken from one of the bitlines.

Description:
TECHNICAL FIELD 
     The present invention relates to the field of reprogrammable fuses and more particularly to a reprogrammable fuse using a pair of non-volatile memory cells having floating gates for storing charges thereon in which the cells are differentially sensed. 
     BACKGROUND OF THE INVENTION 
     Reprogrammable fuses are well-known in the art. See, for example, U.S. Pat. No. 6,222,765 which discloses a non-volatile flip flop circuit in which a pair of non-volatile memory cells differentially store charges thereon. In addition, the two cells are connected to a volatile flip flop for faster access. 
     A non-volatile memory cell of the split gate floating gate type is also well-known in the art. See, for example, U.S. Pat. Nos. 5,029,130 and 5,572,054, whose disclosures are incorporated herein in their entirety by reference. As disclosed in these patents, the non-volatile memory cell comprises a first terminal and a second terminal with a channel therebetween. A floating gate is formed over a first portion of the channel and is insulated therefrom and is over a portion of the first terminal. The non-volatile memory cell also comprises a control gate which overlaps a second portion of the channel. The action of erase, programming, and read are disclosed in the aforementioned patents. 
     SUMMARY OF THE INVENTION 
     A reprogrammable fuse comprises a first and a second non-volatile memory cell. Each non-volatile memory cell is of the type having a first terminal and a second terminal in a substrate with a channel therebetween. Each of the first and second non-volatile memory cells has a floating gate for storing charges with the floating gate overlying a portion of the channel and is capacitvely coupled to the first terminal. Each of the first and second non-volatile memory cells further has a control gate overlying a second portion of the channel and serves to remove charges stored on the floating gate. The fuse has a first bitline connected to the second terminal of the first non-volatile memory cell and a second bitline connected to the second terminal of the second non-volatile memory cell. A word line is commonly connected to the control gates of the first and second non-volatile memory cells. A source line is commonly connected to the first terminals of the first and second non-volatile memory cells. A precharging and equalization circuit is commonly connected to the second terminals of the first and second non-volatile memory cells. An output terminal is connected to one of the first or second bitlines for supplying an output signal indicative of the state of the fuse. The fuse is erased by supplying erase voltages to the word line and the source line. The fuse is programmed by supplying programming voltages to the source line, word line, and the first bitline and the second bitline wherein the fuse is programmed to one state or another state. When the fuse is programmed to one state, the floating gate of the first non-volatile memory cell stores more charges than the floating gate of the second non-volatile memory cell. When the fuse is programmed to another state, the floating gate of the first non-volatile memory cell stores less charges than the floating gate of the second non-volatile memory cell. The programmed state of the fuse is read by supplying a precharging voltage to the first and second bitlines with the first and second bitlines being differentially sensed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of the reprogrammable fuse of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 1 there is shown a circuit diagram of a reprogrammable fuse  10  of the present invention. The reprogrammable fuse  10  comprises a first non-volatile memory cell  12   a  and a second non-volatile memory cell  12   b.  Each of the first and second non-volatile memory cells  12   a  and  12   b  is of the type having a first terminal  14   a  and  14   b  and a second terminal  18   a  and  18   b  in a substrate with a channel therebetween. A floating gate stores charges and overlies a first portion of the channel and is capacitively coupled to the first terminals  14   a  and  14   b.  A control gate overlies a second portion of the channel and serves to remove charges stored on the floating gate and to control the conduction of current between the first terminal  14  and the second terminal  18 . The connection to the control gates are designated as nodes D and E and are connected to the control gate lines  20   a  and  20   b  respectively. 
     Each of the first and second non-volatile memory cells  12   a  and  12   b  is of the type that is described in U.S. Pat. Nos. 5,029,130 and 5,572,054 whose disclosures are incorporated herein in their entirety by reference. 
     The first terminals  14   a  and  14   b  are commonly connected and received the signal SL. The control gate line  20   a  is connected to the signal WL through transistors  24   a  and  26   a  which are controlled by the signal WLFUSENB_N. The control gate line  20   b  is connected to the signal WL through the transistor  26   b  whose gate is also controlled by the WLFUSENB_N signal. Thus, when WLFUSENB_N is activated, the WL signal is supplied to both control gate lines  20   a  and  20   b  and to the control gate nodes D and E respectively. 
     The second terminals  18   a  and  18   b  of each of the non-volatile memory cells  12   a  and  12   b  are connected respectively through pass gates  16   a  and  16   b  respectively to the signals BL and BL_N. The pass gates  16   a  and  16   b  are controlled by the signal EP. The signal EP is supplied to one terminal of each of the pass gates  16   a  and  16   b.  The EP signal is also supplied to an inverter  22  which supplies the output thereof to the second gate of the pass gates  16   a  and  16   b.  Thus when the EP signal is activated, the pass gates  16   a  and  16   b  are activated permitting the signals BL and the BL_N to be supplied to the second terminals  18   a  and  18   b  respectively,. 
     An EQ_N signal is supplied to an inverter  28  which supplies as an output to a second inverter  30  which then supplies as its output to the gates of a pair of P-type MOS transistors  32   a  and  32   b.  Each of the P-type MOS transistors  32   a  and  32   b  is connected at a first terminal (source/drain) thereof to a voltage source VDD. The second terminals (drain/source) of the P-type MOS transistors  32   a  and  32   b  are connected to a first and second bitlines  40   a  and  40   b  respectively. The first and second bitlines  40   a  and  40   b  are connected respectively to the first terminals (source/drain) of a first N-type MOS transistor  34   a  and a second N-type MOS transistor  34   b.  The second terminal (drain/source) of the first N-type MOS transistor  34   a  and the second terminal (drain/source) of the second N-type MOS transistor  34   b  are connected to the second terminals  18   a  and  18   b  of the NVM cells  12   a  and  12   b  respectively. The gates of the N-type MOS transistor  34   a  and  34   b  are connected together and receive the output signal from an inverter  44 . The inverter  44  receives as its input the output of a NAND gate  42 . The NAND gate  42  receives as one of its input the signal EQ_N. The other input of the NAND gate  42  is the signal EP which is then inverted by an inverter  40  and whose output is then supplied to the input of the NAND gate  42 . 
     The fuse  10  also comprises a second pair of P-type MOS transistors  36   a  and  36   b.  The second pair of P-type MOS transistors  36   a  and  36   b  have first terminals-(source/drain) connected to the voltage source VDD. The second terminals of the second pair of P-type MOS transistors  36   a  and  36   b  are connected to the first and second bitlines  40   a  and  40   b  respectively. The gates of the second pair of P-type MOS transistors  36   a  and  36   b  are connected to the first terminals (source/drain) of a second pair of N-type MOS transistors  38   a  and  38   b.  The second terminals (drain/source) of the second pair of N-type MOS transistors  38  and  38   b  are connected to the control gate lines  20   a  and  20   b  respectively. The gates of the second pair of N-type MOS transistors  38   a  and  38   b  are connected together and receive the output of the inverter  44 . Further, the second terminals of the P-type MOS transistors  36   a  and  36   b  are cross coupled. Thus, the gate of the P-type MOS transistor  36   a  is connected to the second terminal of the P-type MOS transistor  36   b.  The gate of the P-type MOS transistor  36   b  is connected to the second terminal of the P-type MOS transistor  36   a.    
     An output of the fuse  10  is supplied from the second bitline  40   b  between the second terminal of the P-type MOS transistor  36   b  and the first terminal of the N-type MOS transistor  34   b.  The output terminal is supplied to an inverter  46 , whose output is supplied to yet another inverter  48  and is the output of the fuse  10 . 
     In the operation of the reprogrammable fuse  10  the non-volatile memory cells  12   a  and  12   b  are first erased. This is accomplished by grounding the signal WLFUSENB_N thereby turning on transistors  24   a,    26   a  and  26   b.  This supplies the WL signal to the control gate lines  20   a  and  20   b  respectively The WL signal is held high at approximately +12 volts. The signal SL, commonly connected to terminals  14   a  and  14   b  of the non-volatile memory cells  12   a  and  12   b  is grounded. Electrons that are stored on the floating gates of cells  12   a  and  12   b  are then Fowler-Nordheim tunneled onto the control gate lines  20   a  and  20   b  respectively. The floating gates are then erased. 
     Alternatively, the signal EP is held at high or approximately +5 volts, turning on the pass gates  16   a  and  16   b.  The signals BL and BL_N are held at ground. With WL at +12 volts, and with WLFUSENB_N high (&gt;+12 volts), the control gates of NVM cells  12   a  and  12   b  are at the high voltage of +12 volts. This turn on the second portion of the channel ever which the control gates lie. The high positive voltage on the control gate capacitvely coupled to the floating gate also turns on the first portion of the channel over which the floating gate lies. This then causes the terminals  14   a  and  14   b  to reach ground. 
     The fuse  10  is then programmed in the following manner. The fuse  10  can be programmed into one of two states. In the first state, more electrons are stored on the floating gate of the non-volatile memory cell  12   a  than on the floating gate of the non-volatile memory cell  12   b.  In a second state, more electrons are stored on the floating gate of the non-volatile memory cell  12   b  than on the floating gate of the non-volatile memory cell  12   a.  To program the fuse  10  into the first state wherein more electrons are stored on the floating gate of the nonvolatile memory cell  12   a,  the commonly connected SL line is raised to approximately +10 volts. WLFUSENB_N is grounded, thereby turning on transistors  24   a,    26   a  and  26   b.  The WL signal is raised to approximately 2 to 3 volts. The EP signal is held high at approximately +5 volts thereby turning on the pass gates  16   a  and  16   b  permitting the signals BL and BL_N to be supplied to the terminals  18   a  and  18   b  respectively. With EP at +5 volts, a zero volt is supplied to the input of the NAND gate  42  which causes the output of the NAND gate  42  to be high. This causes the output of the inverter  44  to be low, thereby turning off the N-type MOS transistors  34   a,    34   b,    38   a  and  38   b.  This isolates the terminals  18   a  and  18   b,  of non-volatile memory cells  12   a  and  12   b  respectively from the bitlines  40   a  and  40   b  respectively. In addition, the output of the inverter  44  isolates the voltage on the control gate lines  20   a  and  20   b  from reaching the gates of the transistors  36   a  and  36   b  and nodes B and A respectively. 
     To program electrons through the mechanism of hot election injection on the floating gate of the non-volatile memory cell  12   a,  the BL line is held low at approximately ground or slightly above ground. This causes electrons to be supplied from the terminal  18   a  and into the channel between the terminal  18   a  and  14   a  and to be injected onto the floating gate of the non-volatile memory cell  12   a.  The voltage on the signal BL_N is held at approximately 2-3 volts or at least above the voltage of the control gate line  20   b  minus Vth. In that case, electrons will not traverse into the channel between the terminals  18   b  and  14   b.    
     To program the fuse  10  into the other state, the voltages on BL_N and BL are reversed. In that event, BL_N is at ground whereas BL is held positive such that no electron would migrate into the channel between the terminal  18   a  and  14   a.  During the programming mode, the signal EQ_N is held high. This turns off the transistors  32   a  and  32   b  from connecting the bitlines  40   a  and  40   b  to the voltage VDD. 
     During the read operation, WLFUSEN_B is held high thereby shutting off transistors  24   a,    26   a  and  26   b.  This prevents the signal WL from being supplied to the control gates of the non-volatile memory cells  12   a  and  12   b.  The commonly connected signal SL is held at ground, thereby grounding the terminals  14   a  and  14   b.  The signal EP is held at low or ground thereby turning off the pass gates  16   a  and  16   b.  Thus, signals BL_N and BL are not connected to the terminals  18   a  and  18   b.  With EP at low, the output of the inverter  40  is high. In the read mode, initially, the signal EQ_N is held low. With EQ_N at low, the output of the NAND gate  42  is high resulting in a low output from the inverter  44  turning off the transistors  34   a,    34   b,    38   a  and  38   b.  This disconnects the terminals  18   a  and  18   b  from the bitlines  40   a  and  40   b.  In addition, this disconnects nodes B and A from the control gate lines  20   a  and  20   b  and the control gates of the non-volatile memory cells  12   a  and  12   b  respectively. With EQ_N at low, the output of the inverter  30  is also low. However, this turns on the P-type MOS transistors  32   a  and  32   b.  This causes VDD to be supplied to the bitlines  40   a  and  40   b.  With bitlines  40   a  and  40   b  high, transistors  36   a  and  36   b  are turned off. Thus, bitlines  40   a  and  40   b  are first precharged. 
     After the precharging action, the signal EQ_N is brought high. Again, the signal EP remains low. With EP low, the output of the inverter  40  is high. With EQ_N also high, the output of the NAND gate  42  is low. This results in a high output from the inverter  44 . With the output of the inverter  44  at high, transistors  34   a  and  34   b  are turned on connecting the bitlines  40   a  and  40   b  to the terminals  18   a  and  18   b  respectively. In addition, with the output of the inverter  44  high, the N-type MOS transistors  38   a  and  38   b  are turned on thereby connecting the precharged node of the bitlines  40   a  and  40   b  to the control gates D and E respectively of the non-volatile memory cells  12   a  and  12   b,  respectively. Depending on the state in which the fuse  10  is programmed, one of two actions can occur. In one action, non-volatile memory cell  12   a  conducts more readily than the non-volatile memory cell  12   b.  In that event, the voltage on bitline  40   a  will lower quicker than the voltage on the bitline  40   b.  With  40   b  remaining at a higher voltage level than  40   a,  the control gate of the non-volatile memory cell  12   a  will be turned on harder than the control gate on the non-volatile memory cell  12   b.  In addition, as the voltage on bitline  40   a  is lowered faster than the voltage on the bitline  40   b  P-type MOS transistor  36   b  is turned on faster than the P-type MOS transistor  36   a.  This further replenishes the voltage on the bitline  40   b  faster than the voltage on the bitline  40   a.  In a second state, the actions are reversed and the voltage on bitline  40   b  is lowered faster than the voltage on the bitline  40   a.  In either event, the output is detected at the output of the inverter  48 . If the bitline  40   b  in one state remains at a higher voltage than bitline  40   a,  the output of the inverter  48  would be high. If the voltage on bitline  40   b  is drained faster than the voltage on bitline  40   a,  when the voltage on bitline  40   a  reaches ground, the output of the inverter  48  would be ground.