Abstract:
A circuit capable of providing electrostatic discharge (ESD) protection includes a first transistor including a first gate and a first source, the first gate being connected to a conductive pad, an impedance device between the first source and a first power rail capable of providing a resistor, a second transistor including a second gate and a second source, the second source being connected to the first power rail through the impedance device, and a clamp device between the first power rail and a second power rail, wherein the clamp device is capable of conducting a first portion of an ESD current and the second transistor is capable of conducting a second portion of the ESD current as the conductive pad is relatively grounded.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. Provisional Application No. 60/824,795, filed Sep. 7, 2006. 
     
     BACKGROUND OF THE INVENTION 
       [0002]    The present invention relates generally to circuits for electrostatic discharge (“ESD”) protection. 
         [0003]    A semiconductor integrated circuit (“IC”) is generally susceptible to an electrostatic discharge (“ESD”) event, which may damage or destroy the IC. An ESD event refers to a phenomenon of electrical discharge of a current (positive or negative) for a short duration during which a large amount of current is provided to the IC. The susceptibility of a device to ESD can be determined by testing for one of three models: Human Body Model (“HBM”), Machines Model (“MM”), and Charged-Device Model (“CDM”). 
         [0004]      The ESD Association Standard for the Development of an Electrostatic Discharge Control Program for Protection of Electrical and Electronic Parts, Assemblies and Equipment  ( Excluding Electrically Initiated Explosive Device ), ANSI/ESD-S20.20-1999 (Aug. 4, 1999), provides for ESD sensitivity testings for each of the three models. The HBM model represents the discharge from the fingertip of a standing individual delivered to conductive leads of a device. In an HBM model ESD test circuit modeled by a 100 picofarad (pF) capacitor, representing the effective capacitance of the human body, a discharge through a switching component and 1,500 ohm series resistor, representing the effective resistance of the human body, into the device under tests is a double exponential waveform with a rise time of 2-10 nanoseconds (nS) and a pulse duration of approximately 150 nS. 
         [0005]    The MM model represents a rapid discharge from items such as a charged board assembly, charged cables, or the conduction arm of an automatic tester. The effective capacitance is approximately 200 pF discharged through a 500 nanohenry (nH) inductor directly into the device because the effective resistance of the machine is approximately zero. The discharge is a sinusoidal decaying waveform having a peak current of approximately 3.8 amperes (A) with a resonant frequency of approximately 16 MHz. 
         [0006]    The CDM model represents a phenomenon where a device acquires a charge through frictional or electrostatic induction processes and then abruptly touches a grounded object or surface.  FIG. 1  is a schematic diagram illustrating the CDM phenomenon. Referring to  FIG. 1 , most of the charge is accumulated in a substrate, including a base, a bulk or a well of the device, and is uniformly distributed in the substrate. Unlike the HBM model and the MM model, the CDM model includes situations where the device itself becomes charged and discharges to ground. The rise time is generally less than 200 picoseconds (pS), and the entire ESD event can take place in less than 2 nS. Current levels can reach several tens of amperes during discharge, which are remarkably greater than those of the HBM and MM models. 
         [0007]    Since the charge is mainly stored in the substrate, a gate oxide of an input-stage metal-oxide-semiconductor (“MOS”) transistor may be easily damaged by a CDM ESD.  FIG. 2  is a schematic circuit diagram of a conventional ESD protection circuit for an input-stage inverter. Referring to  FIG. 2 , the ESD protection circuit comprises an ESD clamp and an n-type metal-oxide-semiconductor (“NMOS”) transistor Mn 1 , and the input-stage inverter comprises a p-type metal-oxide-semiconductor (“PMOS”) transistor Mp 5  and an NMOS transistor Mn 5 . The ESD protection circuit designed for HBM and MM ESD protection, however, may not provide effective CDM ESD protection for the input-stage inverter. When a CDM ESD occurs as an input pad is grounded, a CDM ESD current I ESD  due to negative charge may damage the gate oxide of the NMOS transistor Mn 5 . Likewise, a CDM ESD current due to positive charge stored in the substrate may also damage the gate oxide of the NMOS transistor Mn 5 . 
         [0008]    Verious Studies have addressed protecting an IC from ESD events. In a paper entitled “Active-source-pump (ASP) technique for ESD design window expansion and ultra-thin gate oxide protection in sub-90 nm Technologies” by Mergens et al.,  Proc. of IEEE CICC,  2004, pp. 251-254, it has been found that gate-to-source breakdown voltages are much lower than gate-to-bulk breakdown voltages. Consequently, pumping schemes to reduce a gate-to-source voltage so as to prevent the gate oxide from CDM ESD damage have been proposed to enhance the ESD robustness in nanoscale complementary metal-oxide-semiconductor (“CMOS”) techniques. 
       BRIEF SUMMARY OF THE INVENTION 
       [0009]    The present invention is directed to circuits capable of ESD protection. Examples of the present invention may provide a circuit capable of providing electrostatic discharge (ESD) protection that comprises a first transistor including a first gate and a first source, the first gate being connected to a conductive pad, an impedance device between the first source and a first power rail capable of providing a resistor, a second transistor including a second gate and a second source, the second source being connected to the first power rail through the impedance device, and a clamp device between the first power rail and a second power rail, wherein the clamp device is capable of conducting a first portion of an ESD current and the second transistor is capable of conducting a second portion of the ESD current as the conductive pad is relatively grounded. 
         [0010]    Some examples of the present invention may provide a circuit capable of providing electrostatic discharge (ESD) protection that comprises a first transistor including a first gate and a first source, the first gate being connected to a conductive pad, an impedance device between the first source and a first power rail capable of providing a resistor, a second transistor including a second source, the second source being connected to the first power rail through the impedance device, a clamp device between the first power rail and a second power rail, and a third transistor capable of conducting a first portion of an ESD current through the clamp device as the conductive pad is relatively grounded, wherein the second transistor is capable of conducting a second portion of the ESD current between the conductive pad and the first power rail as the first portion of the ESD current flows through the clamp device. 
         [0011]    Examples of the present invention may also provide a circuit capable of providing electrostatic discharge (ESD) protection that comprises a first transistor including a first gate and a first source, the first gate being connected to a conductive pad, an impedance device between the first source and a first power rail capable of providing a resistor, and a second transistor including a second source connected to the first power rail through the impedance device, the second transistor being capable of increasing a voltage level at the first source as the conductive pad is relatively grounded by conducting a portion of an ESD current between the conductive pad and the first power rail. 
         [0012]    Additional features and advantages of the present invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The features and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. 
         [0013]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed. 
     
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0014]    The foregoing summary, as well as the following detailed description of the invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there are shown in the drawings embodiments which are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown. 
           [0015]    In the drawings: 
           [0016]      FIG. 1  is a schematic diagram illustrating a charged-device model (“CDM”) phenomenon; 
           [0017]      FIG. 2  is a schematic circuit diagram of a conventional electrostatic discharge (“ESD”) protection circuit for an input-stage inverter; 
           [0018]      FIG. 3A  is a circuit diagram of a circuit capable of ESD protection consistent with one example of the present invention; 
           [0019]      FIG. 3B  is a layout diagram of a pumping transistor of the ESD protection circuit illustrated in  FIG. 3A  consistent with one example of the present invention; 
           [0020]      FIG. 3C  is a layout diagram of a pumping transistor of the ESD protection circuit illustrated in  FIG. 3A  consistent with another example of the present invention; 
           [0021]      FIG. 3D  is a cross-sectional view of the pumping transistor illustrated in  FIG. 3B ; 
           [0022]      FIG. 4A  is a schematic diagram illustrating an operation of the circuit illustrated in  FIG. 3A  consistent with one example of the present invention; 
           [0023]      FIG. 4B  is a schematic diagram illustrating an operation of the circuit illustrated in  FIG. 3A  consistent with another example of the present invention; 
           [0024]      FIG. 5A  is a circuit diagram of a circuit capable of ESD protection consistent with another example of the present invention; 
           [0025]      FIG. 5B  is a layout diagram of a pumping transistor of the ESD protection circuit illustrated in  FIG. 5A  consistent with one example of the present invention; 
           [0026]      FIG. 5C  is a layout diagram of a pumping transistor of the ESD protection circuit illustrated in  FIG. 5A  consistent with another example of the present invention; 
           [0027]      FIG. 5D  is a cross-sectional view of the pumping transistor illustrated in  FIG. 5B ; 
           [0028]      FIG. 6A  is a schematic diagram illustrating an operation of the circuit illustrated in  FIG. 5A  consistent with one example of the present invention; 
           [0029]      FIG. 6B  is a schematic diagram illustrating an operation of the circuit illustrated in  FIG. 5A  consistent with another example of the present invention; 
           [0030]      FIG. 7  is a circuit diagram of an ESD protection circuit consistent with still another example of the present invention; 
           [0031]      FIG. 8  is a circuit diagram of an ESD protection circuit consistent with yet another example of the present invention; 
           [0032]      FIG. 9  is a circuit diagram of an ESD protection circuit consistent with yet still another example of the present invention; and 
           [0033]      FIG. 10  is a circuit diagram of an ESD protection circuit consistent with an example of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0034]    Reference will now be made in detail to the present examples of the invention, which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. 
         [0035]      FIG. 3A  is a circuit diagram of a circuit  10  capable of ESD protection consistent with one example of the present invention. Referring to  FIG. 3A , the circuit  10  may include an ESD clamp further comprising a PMOS transistor  11   p  and an NMOS transistor  11   n , a self-biased current trigger (“SBCT”) circuit  14  and a pumping NMOS transistor  12 . The ESD clamp, disposed near a pad  13 , may be capable of providing HBM and MM ESD protection for a CMOS inverter, which may comprise a PMOS transistor  12   p  and the NMOS transistor  12 . The PMOS transistor  11   p  of the ESD clamp includes a gate, a source and a bulk, all of which (not numbered) are connected to a VDD 1  line. Furthermore, the PMOS transistor  51   p  includes a drain (not numbered) connected to the pad  13 . The NMOS transistor  1  in of the ESD clamp includes a gate, a source and a bulk, all of which (not numbered) are connected to a VSS 1  line. Furthermore, the NMOS transistor  1  in includes a drain (not numbered) connected to the pad  13 . 
         [0036]    The PMOS transistor  12   p  of the inverter includes a source and a bulk, both of which (not numbered) are connected to a VDD 2  line, a gate (not numbered) connected to the pad  13 , and a drain (not numbered) connected to internal circuits. The NMOS transistor  12  of the inverter includes a source and a bulk, both of which are connected to a VSS 2  line, a gate connected to the pad  13 , and a drain connected to the internal circuits. Furthermore, the source of the NMOS transistor  12  is connected to the VSS 2  line through a densely doped n-type (N+) diffused region  15 , which functions to serve as a resistor, and a densely doped p-type (P+) diffused region  16 , which serves as a pickup. 
         [0037]    The SBCT circuit  14  may include an NMOS transistor  14   n  and a diode assembly  14   d . The NMOS transistor  14   n  includes a source and a bulk, both of which (not numbered) are connected to the VSS 2  line through the N+ region  15  and the P+ region  16 , a gate (not numbered) connected to the VSS 1  line through a resistor (not numbered), and a drain connected to the pad  13 . The diode assembly  14   d  may include a first diode string  14   d - 1  and a second diode string  14   d - 2  connected in parallel to each other between the VSS 1  and VSS 2  lines. 
         [0038]      FIG. 3B  is a layout diagram of the pumping transistor  12  of the ESD protection circuit  10  illustrated in  FIG. 3A  consistent with one example of the present invention. Referring to  FIG. 3B , the pumping transistor  12  includes a gate  120 , an N+ source  121  and an N+ drain  122 . The source  121  is connected to the P+ pickup  16  through the N+ resistor region  15 . The resistance of the N+ resistor region  15  may be determined by the width and length of the N+ resistor region  15 . A patterned metal layer  17  is formed over the source  121 , the drain  122  and the pickup  16  to serve as contacts, which are electrically connected to another patterned metal layer  18  formed over the patterned metal layer  17 . 
         [0039]      FIG. 3C  is a layout diagram of a pumping transistor  12 - 1  of the ESD protection circuit  10  illustrated in  FIG. 3A  consistent with another example of the present invention. Referring to  FIG. 3C , the pumping transistor  12 - 1  includes a multi-finger structure further comprising a plurality of gates  120 - 1 , sources  121 - 1  and drains  122 - 1 . Each of the sources  121 - 1  is connected to a P+ pickup region  16 - 1  through an N+ resistor region  15 - 1 . 
         [0040]      FIG. 3D  is a cross-sectional view of the pumping transistor  12  illustrated in  FIG. 3B  along a line AA. Referring to  FIG. 3D , the pumping transistor  12  includes the N+ regions  121  and  122  formed in a p-type well region (P-well), which in turn is formed in a p-type substrate (P-substrate). The N+ regions  121  and  122  serve as a source and a drain of the pumping NMOS transistor  12 , respectively. Another N+ region  15  formed in the P-well serves as the resistor. The source  121  is connected to the P+ pickup  16  through the N+ region  15 . 
         [0041]      FIG. 4A  is a schematic diagram illustrating an operation of the circuit  10  illustrated in  FIG. 3A  consistent with one example of the present invention. Referring to  FIG. 4A , if the substrate is negatively charged and the pad  13  is relatively grounded, a negative CDM ESD stress occurs. A portion of the CDM ESD stress is rapidly coupled by a parasitic capacitor  11   c  (illustrated in dotted lines) formed by the gate and drain of the NMOS transistor  11   n . The coupled voltage triggers a parasitic bipolar transistor  11   npn  (illustrated in dotted lines) formed by the drain, bulk and source of the NMOS transistor  11   n . A first portion of the CDM ESD current, I 1 , is discharged through the turn-on parasitic bipolar transistor  11   npn  and the second diode string  14   d - 2 , which is forward biased. Note that the first current I 1  flows from the pad  13  to the substrate because the substrate is negatively charged. 
         [0042]    The gate of the NMOS transistor  14   n  is biased by the first current I 1  flowing through the second diode string  14   d - 2 . The NMOS transistor  14   n  is then turned on to conduct a second portion of the CDM ESD current, I 2 , which may generally be smaller than the first portion I 1 . The second current I 2  flows from the pad  13  to the substrate through the N+ region  15  and the P+ region  16 , which pumps the source of the pumping transistor  12 , increasing the source voltage level and in turn decreasing the gate-to-source voltage of the pumping transistor  12 . The reduction in the gate-to-source voltage, as previously discussed, helps reduce the risk of gate oxide damage and therefore enhance the ESD robustness of the pumping transistor  12 . 
         [0043]      FIG. 4B  is a schematic diagram illustrating an operation of the circuit  10  illustrated in  FIG. 3A  consistent with another example of the present invention. Referring to  FIG. 4B , if the substrate is positively charged and the pad  13  is relatively grounded, a positive CDM ESD stress occurs. A first portion of the CDM ESD current, I 3 , is discharged through the first diode string  14   d - 1  and a parasitic diode  11   d  (illustrated in dotted lines) formed by the bulk and drain of the NMOS transistor  11   n . Note that the first current I 3  flows from the substrate to the pad  13  because the substrate is positively charged. A second portion of the CDM ESD current, I 4 , is discharged through a parasitic diode  14   nd  formed by the bulk and drain of the NMOS transistor  14   n  (illustrated in dotted lines) to the pad  13 . The second current I 4  pumps the source of the pumping transistor  12 , increasing the source voltage level and in turn decreasing the gate-to-source voltage of the pumping transistor  12 . 
         [0044]      FIG. 5A  is a circuit diagram of a circuit  50  capable of ESD protection consistent with another example of the present invention. Referring to  FIG. 5A , the circuit  50  may include an ESD clamp further comprising a PMOS transistor  51   p  and an NMOS transistor  51   n , a self-biased current trigger (“SBCT”) circuit  54  and a pumping PMOS transistor  52 . The ESD clamp, disposed near a pad  53 , may be capable of providing HBM and MM ESD protection for a CMOS inverter, which comprises the PMOS transistor  52  and an NMOS transistor  52   n . The PMOS transistor  51   p  of the ESD clamp includes a gate, a source and a bulk, all of which (not numbered) are connected to a VDD 1  line. Furthermore, the PMOS transistor  51   p  includes a drain (not numbered) connected to the pad  53 . The NMOS transistor  51   n  of the ESD clamp includes a gate, a source and a bulk, all of which (not numbered) are connected to a VSS 1  line. Furthermore, the NMOS transistor  51   n  includes a drain (not numbered) connected to the pad  53 . 
         [0045]    The NMOS transistor  52   n  of the inverter may include a source and a bulk, both of which (not numbered) are connected to a VSS 2  line, a gate (not numbered) connected to the pad  53 , and a drain (not numbered) connected to internal circuits. The PMOS transistor  52  of the inverter includes a source and a bulk, both of which are connected to a VDD 2  line, a gate connected to the pad  53 , and a drain connected to the internal circuits. Furthermore, the source of the PMOS transistor  52  is connected to the VDD 2  line through a densely doped p-type (P+) diffused region  55 , which functions to serve as a resistor, and a densely doped n-type (N+) diffused region  56 , which serves as a pickup. 
         [0046]    The SBCT circuit  54  may include a PMOS transistor  54   p  and a diode assembly  54   d . The PMOS transistor  54   p  includes a source and a bulk, both of which (not numbered) are connected to the VDD 2  line through the P+ region  55  and the N+ region  56 , a gate (not numbered) connected to the VDD 1  line, and a drain connected to the pad  53 . The diode assembly  54   d  includes a first diode string  54   d - 1  and a second diode string  54   d - 2  connected in parallel to each other between the VDD 1  and VDD 2  lines. 
         [0047]      FIG. 5B  is a layout diagram of the pumping transistor  52  of the ESD protection circuit  50  illustrated in  FIG. 5A  consistent with one example of the present invention. Referring to  FIG. 5B , the pumping transistor  52  includes a gate  520 , a P+ source  521  and a P+ drain  522 . The source  521  is connected to the N+ pickup  56  through the P+ resistor region  55 . The resistance of the P+ resistor region  55  may be determined by the width and length of the P+ resistor region  55 . A patterned metal layer  57  is formed over the source  521 , the drain  522  and the pickup  56  to serve as contacts, which are electrically connected to another patterned metal layer  58  formed over the patterned metal layer  57 . 
         [0048]      FIG. 5C  is a layout diagram of a pumping transistor  52 - 1  of the ESD protection circuit  50  illustrated in  FIG. 5A  consistent with another example of the present invention. Referring to  FIG. 5C , the pumping transistor  52 - 1  includes a multi-finger structure further comprising a plurality of gates  520 - 1 , sources  521 - 1  and drains  522 - 1 . Each of the sources  521 - 1  is connected to an N+ pickup region  56 - 1  through a P+ resistor region  55 - 1 . 
         [0049]      FIG. 5D  is a cross-sectional view of the pumping transistor  52  illustrated in  FIG. 5B  along a line BB. Referring to  FIG. 5D , the pumping transistor  52  includes the P+ regions  521  and  522  formed in an n-type well region (N-well), which in turn is formed in a p-type substrate (P-substrate). The P+ regions  521  and  522  serve as a source and a drain of the pumping NMOS transistor  52 , respectively. Another P+ region  55  formed in the N-well serves as the resistor. The source  521  is connected to the N+ pickup  56  through the P+ region  55 . 
         [0050]      FIG. 6A  is a schematic diagram illustrating an operation of the circuit illustrated  50  in  FIG. 5A  consistent with one example of the present invention. Referring to  FIG. 6A , if the N-well (also referring to  FIG. 5D ) is positively charged and the pad  53  is relatively grounded, a positive CDM ESD stress occurs. A portion of the CDM ESD stress is rapidly coupled by a parasitic capacitor  51   c  (illustrated in dotted lines) formed by the gate and drain of the PMOS transistor  51   p . The coupled voltage triggers a parasitic bipolar transistor  51   pnp  (illustrated in dotted lines) formed by the drain, bulk and source of the PMOS transistor  51   p . A first portion of the CDM ESD current, I 5 , is discharged through the turn-on parasitic bipolar transistor  51   pnp  and the first diode string  54   d - 1  to the pad  53 . 
         [0051]    The gate of the PMOS transistor  54   p  is biased by the first current I 5  flowing through the first diode string  54   d - 1 . The PMOS transistor  54   p  is then turned on to conduct a second portion of the CDM ESD current, I 6 . The second current I 6  flows from the substrate to the pad  53  through the P+ region  55  and the N+ region  56 , which pumps the source of the pumping transistor  52 , increasing the source voltage level and in turn decreasing the gate-to-source voltage of the pumping transistor  52 . 
         [0052]      FIG. 6B  is a schematic diagram illustrating an operation of the circuit  50  illustrated in  FIG. 5A  consistent with another example of the present invention. Referring to  FIG. 6B , if the N-well is negatively charged and the pad  53  is relatively grounded, a negative CDM ESD stress occurs. A first portion of the CDM ESD current, I 7 , is discharged through the second diode string  54   d - 2  and a parasitic diode  51   d  (illustrated in dotted lines) formed by the bulk and drain of the PMOS transistor  51   p . A second portion of the CDM ESD current, I 8 , is discharged through a parasitic diode  54   pd  (illustrated in dotted lines) formed by the bulk and drain of the PMOS transistor  54   p . The second current I 8  flowing through the P+ region  55  and the N+ region  56  pumps the source of the pumping transistor  52 , increasing the source voltage level and in turn decreasing the gate-to-source voltage of the pumping transistor  52 . 
         [0053]      FIG. 7  is a circuit diagram of an ESD protection circuit  70  consistent with still another example of the present invention. Referring to  FIG. 7 , the ESD protection circuit  70  is similar in structure to the circuit  10  illustrated in  FIG. 3A , except an ESD clamp  71 . Instead replaces the diode assembly  14   d , the ESD clamp  71  includes an NMOS transistor  71   n , which functions to provide a parasitic diode  71   d  (illustrated in dotted lines) in response to a CDM ESD stress. 
         [0054]      FIG. 8  is a circuit diagram of an ESD protection circuit  80  consistent with yet another example of the present invention. Referring to  FIG. 8 , the ESD protection circuit  80  is similar in structure to the circuit  70  illustrated in  FIG. 7  except for ESD clamps  81  and  82 . The ESD clamp  8  includes one of a diode assembly  14   d  as illustrated in  FIG. 3A  and an NMOS transistor  71  as illustrated in  FIG. 7 . Skilled persons in the art will understand that the ESD clamp  81  may be replaced by other ESD clamp that provides a parasitic diode. The ESD clamp  82  includes a PMOS transistor  82   p , which functions to provide a parasitic diode  82   d  (illustrated in dotted lines) in response to a CDM ESD stress. 
         [0055]      FIG. 9  is a circuit diagram of an ESD protection circuit  90  consistent with yet still another example of the present invention. Referring to  FIG. 9 , the ESD protection circuit  90  is similar in structure to the ESD protection circuit  80  illustrated in  FIG. 8  except that an NMOS transistor  96   n  replaces the N+ resistor region. An NMOS transistor  94   n  of an SBCT circuit  94  includes a source (not numbered) and a bulk (not numbered) connected to a drain (not numbered) of the NMOS transistor  96   n . An NMOS transistor  92   n  includes a source (not numbered) connected to the drain of the NMOS transistor  96   n . The NMOS transistor  96   n  further includes a gate (not numbered) connected to the VDD 2  line, and a source (not numbered) and a bulk (not numbered) connected to the VSS 2  line. The NMOS transistor  96   n  functions to serve as a resistor. 
         [0056]      FIG. 10  is a circuit diagram of an ESD protection circuit  100  consistent with an example of the present invention. Referring to  FIG. 10 , the ESD protection circuit  100  includes a first SBCT circuit  101 , a second SBCT circuit  102 , a first pumping circuit  103  and a second pumping circuit  104 . Each of ESD clamps  101 - 1  and  102 - 1  may be replaced by one of a diode assembly and an MOS transistor. An NMOS transistor  103 - 1  may be replaced by an N+ resistor region and a P+ pickup region. A PMOS transistor  104 - 1  may be replaced by a P+ resistor region and an N+ pickup region. 
         [0057]    It will be appreciated by those skilled in the art that changes could be made to the embodiments described above without departing from the broad inventive concept thereof. It is understood, therefore, that this invention is not limited to the particular embodiments disclosed, but it is intended to cover modifications within the spirit and scope of the present invention as defined by the appended claims. 
         [0058]    Further, in describing representative embodiments of the present invention, the specification may have presented the method and/or process of the present invention as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. As one of ordinary skill in the art would appreciate, other sequences of steps may be possible. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. In addition, the claims directed to the method and/or process of the present invention should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the present invention.