Abstract:
A sense amplifier circuit used in, for example, a MIS static RAM includes a differential amplifier (Q 11  through Q 14 ) for sensing and amplifying the difference in potential between two input lines (DB and DB) and generating two bipolar differential signals (D and D) and a pull-down circuit (Q 15 ) for establishing a reference potential (V REF ) for the differential amplifier. A compensation circuit (Q 16 , Q 17  and Q 18 ) is provided for detecting the in-phase component of the input lines so as to control the pull-down circuit. Therefore, the fluctuation of the reference potential follows the fluctuation of the in-phase component of the input lines so that a stable and high-speed sensing operation is effected.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a sense amplifier circuit which is, for example, used in a MIS static random access memory (RAM). 
     2. Description of the Prior Art 
     In general, a MIS static RAM cell comprises a bistable flip-flop circuit which uses four or six transistors per bit. That is, the memory cell has a pair of driver transistors which are cross-coupled to each other, a pair of load resistors or load transistors, and a pair of transfer transistors connected to one word line and to one pair of bit lines. In this memory cell, only one of the driver transistors is turned on to correspond to memory data &#34;1&#34; or &#34;0&#34;. In order to read the cell, the transfer transistors are turned on by changing the potential of the word line and the data on the driver transistors is transferred to the bit lines. In this memory, a sense amplifier circuit is provided for sensing and amplifying a small difference in potential between the bit line pair. 
     One conventional sense amplifier circuit used in a MIS static RAM has a differential amplifier for sensing and amplifying a small difference in potential between a bit line pair, and a pull-down circuit for generating a reference potential to the differential amplifier. In this case, the pull-down circuit is controlled by a power supply or a voltage which is in response to the power supply. However, in this conventional sense amplifier circuit, when the potential of the power supply is increased, the potentials of the bit line pair are also increased, while the reference potential for the differential amplifier is unchanged or decreased. As a result, the difference between the potentials of the bit line pair and the reference potential is increased, which deteriorates the sensing operation of the sense amplifier circuit. In other words, the sensing operation is susceptible to fluctuation in the power supply. In particular, in a high-integrated memory wherein the cell area thereof is small, the conductance gm of the driver transistors is small, so that the difference in potential between the bit line pair is very small. As a result, the sensing operation is very susceptible to fluctuation in the power supply. 
     SUMMARY OF THE INVENTION 
     Therefore, it is a principal object of the present invention to provide a sense amplifier circuit which can perfom a stable operation even when the potential of the power supply fluctuates. 
     According to the present invention, there is provided a sense amplifier circuit comprising: first and second power supplies; first and second input lines; first and second output lines; a differential amplifier, connected to the first power supply, to the first and second input lines and to the first and second output lines, for sensing and amplifying the difference in potential between the first and second input lines and generating bipolar signals, whose difference in potential is in response to the difference in potential between the first and second input lines, to the output lines; a first pull-down circuit, connected to the differential amplifier and to the second power supply, for pulling down the reference potential of the differential amplifier; and a compensation circuit, connected to the first and second power supplies, to the pull-down circuit and to the input lines, for detecting the in-phase component of the potentials of the input lines so as to control the conductance of the pull-down circuit. 
     The present invention will be more clearly understood from the following description, contrasting the present invention with the conventional circuit, and with reference to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram illustrating one conventional sense amplifier circuit applied to a MIS static RAM; 
     FIGS. 2 and 3 are diagrams for explaining the operation of the prior art circuit of FIG. 1; 
     FIG. 4 is a circuit diagram a first embodiment of the sense amplifier circuit according to the present invention, applied to a MIS static RAM; 
     FIG. 5 is a diagram for explaining the operation of the circuit of FIG. 4; 
     FIGS. 6, 7 and 8 are circuit diagrams illustrating second, third and fourth embodiments of the sense amplifier circuit according to the present invention, respectively. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In FIG. 1, which illustrates one conventional sense amplifier circuit applied to a MIS static RAM, C 00  and C 01  are memory cells; WL 0  is a word line; BL 0 , BL 0 , BL 1  and BL 1  are bit lines; Q L0 , Q L0  &#39;, Q L1  and Q L1  &#39; are load transistors connected to a power supply; Q B0 , Q B0  &#39;, Q B1  and Q B1  &#39; are column selection transistors which are selected by column selection signals Y 0  and Y 1  ; DB and DB are data bit lines; and SA is a sense amplifier circuit connected to the data bit lines DB and DB. 
     Each of the memory cells C 00  and C 01  comprises resistors R 1  and R 2 , driver transistors Q 1  and Q 2  with drains and gates cross-coupled, and transfer transistors Q 3  and Q 4 . 
     In the sense amplifier circuit SA, a differential amplifier, which is formed by depletion type load transistors Q 11  and Q 12  and enhancement type input transistors Q 13  and Q 14 , senses and amplifies the difference in potential between the data bit lines DB and DB and generates bipolar differential signals D and D. A pull-down circuit formed by an enhancement transistor Q 15  determines a reference potential V REF  of the differential amplifier. Note that the power supply voltage V CC  is applied to the gate of the transistor Q 15 . 
     The operation of the circuit of FIG. 1 will now be explained. For example, when the data stored in the cell C 00  is read out, the potential of the word line WL 0  is caused to be high by a word decoder/driver (not shown) so as to turn on the transfer transistors Q 3  and Q 4 , and simultaneously, or after that, the potential of the column selection signal Y 0  is caused to be high so as to turn on the transistors Q B0  and Q B0  &#39;. At this time, if the state of the cell C 00  is that the transistors Q 1  and Q 2  are turned on and off, respectively, that is, the potentials at nodes N 1  and N 2  are low and high, respectively, the potentials of the bit lines BL 0  and BL 0  become low and high, respectively. In addition, the potentials of the data bit lines DB and DB also become low and high, respectively. Therefore, the difference in potential between the data bit lines DB and DB is sensed and amplified by the sense amplifier SA so that the differential signals D and D are obtained. 
     In this state, when the power supply V CC  fluctuates, for example, when the potential of the power supply V CC  is increased, the potentials of the data bit lines DB and DB are also increased, as illustrated in FIG. 2. However, since the gate potential of the transistor Q 15  is also increased so as to increase the conductivity of the transistor Q 15 , the reference potential V REF  is unchanged or becomes a little low. As a result, the difference between the potential of the data bit line DB and the reference potential V REF  and the difference beween the potential of the data bit line DB and the reference potential V REF  both become large. At worst, even when the potential of the data bit line DB is low, the transistor Q 14  is not turned off. As a result, as indicated by the broken line in FIG. 3, the high-potential side differential output signal D rises slowly, and in addition, the potential level of the signal D is reduced. That is, the access time is changed from an optimum time t 1  to a long time t 2 . Further, at worst, the signals D and D are both determined to be low by a subsequent circuit. This is because the in-phase component (or common direct component) of the data bit line DB and DB become large as compared with the differential component thereof. Therefore, the fluctuation tolerance of the power supply V CC  is small, and in addition, the access time becomes large and at worst, a read-out error may be generated. 
     Contrary to this, in the present invention, even when the potential of the power supply V CC  fluctuates, the reference potential V REF  is changed in response to the potential fluctuation of the data bit lines DB and DB so as to obtain an accurate and high-speed sensing operation. 
     FIG. 4 is a circuit diagram illustrating a first embodiment of the sense amplifier circuit according to the present invention, applied to a MIS static RAM. In FIG. 4, the elements which are the same as those of FIG. 1 are denoted by the same references. In FIG. 4, a compensation circuit formed by a depletion type load transistor Q 16  and enhancement type transistors Q 17  and Q 18  is added to the sense amplifier circuit SA of FIG. 1. In this case, the gates of the transistors Q 17  and Q 18  are connected to the data bit lines DB and DB, respectively, and the transistor Q 16  is connected to the power supply V CC  and to the transistors Q 17  and Q 18 . Further, the pull-down circuit formed by the transistor Q 15  is controlled by the potential V 1  at a node connecting the transistor Q 16  to the transistors Q 17  and Q 18 . 
     In the circuit of FIG. 4, when the driver transistors Q 1  and Q 2  of the selected memory cell C 00  are turned on and off, respectively, the potentials of the data bit lines DB and DB are low and high, respectively. In this case, the differential component of the data bit lines DB and DB is suppressed by the compensation circuit formed by the transistors Q 16 , Q 17  and Q 18 , so that the potential V 1  is not changed. That is, if one of the potentials of the data bit lines DB and DB is high, then the other is low. Therefore, if one of the transistors Q 17  and Q 18  is turned on, then the other is turned off. As a result, the compensation circuit is unchangeable. Therefore, in this case, the pull-down circuit formed by the transistor Q 15  is controlled by the potential V 1  which is constant. 
     On the other hand, in the circuit of FIG. 4, when the power supply V CC  fluctuates, the in-phase component of the data bit lines DB and DB is also fluctuated. For example, as illustrated in FIG. 5, due to the increase of the potential of the power supply V CC , the potentials of the data bit lines DB and DB are both increased. As a result, the conductances of the transistors Q 17  and Q 18  are both increased, and in turn, the potential V 1  is decreased. Therefore, the conductance of the transistor Q 15  is decreased so as to increase the reference potential V REF . Therefore, as illustrated in FIG. 5, the difference between the potential of the data bit line DB (or DB) and the reference potential V REF  is always almost constant, regardless of the fluctuation of the power supply V CC , so that a stable and high-speed sensing operation is achieved. 
     FIG. 6 is a circuit diagram illustrating a second embodiment of the sense amplifier circuit according to the present invention. In FIG. 6, a latch circuit formed by transistors Q 19  and Q 20  is added to the sense amplifier circuit of FIG. 4. Therefore, when a definite difference in potential between the differential signals D and D is generated, a latch operation is rapidly effected. 
     FIG. 7 is a circuit diagram illustrating a third embodiment of the sense amplifier circuit according to the present invention. In FIG. 7, another pull-down circuit formed by a transistor Q 21  is added to the circuit of FIG. 6. However, the operation of the circuit of FIG. 7 is similar to that of the circuit of FIG. 6. 
     FIG. 8 is a circuit diagram illustrating a fourth embodiment of the sense amplifier circuit according to the present invention. In FIG. 8, the transistors Q 13  and Q 14  are omitted from the circuit of FIG. 6, and in addition the data bit lines DB and DB are connected to the output lines for generating the differential output signals D and D. In FIG. 8, immediately after the latch operation is effected, the transistors Q B0  and Q B0  &#39; (or Q B1  and Q B1  &#39;) are cut off. As a result, the data stored in the latch circuit formed by the transistors Q 19  and Q 20  is not fedback to any memory cells. 
     In FIGS. 4, 6, 7 and 8, each of the load transistors Q 11 , Q 12  and Q 16  is of a depletion type; however, this transistor can be of an enhancement type with a drain and a gate coupled. 
     As explained hereinbefore, the sense amplifier circuit according to the present invention has an advantage, as compared with the conventional circuit, in that a stable sensing operation is performed even when the potential of a power supply fluctuates, since the reference potential V REF  is changed in response to the in-phase component of the input lines (the data bit lines DB and DB).