Abstract:
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (STI) around the fin-shaped structures on the first region and the second region; forming a patterned hard mask on the second region; removing the fin-shaped structures and the first STI from the first region; forming a second STI on the first region; removing the patterned hard mask; and forming a gate structure on the second STI.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The invention relates to a method for fabricating semiconductor device, and more particularly to a method of forming shallow trench isolation (STI) between fin-shaped structures. 
         [0003]    2. Description of the Prior Art 
         [0004]    With the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the fin FET can be controlled by adjusting the work function of the gate. 
         [0005]    In current FinFET fabrication, gate structures are often formed on the shallow trench isolation (STI) between fin-shaped structures as gate structures are fabricated in the active region. These gate structures atop STIs however are typically formed into the substrate, influencing the isolation effect of the STI. Hence, how to improve the current FinFET fabrication and structure for resolving this issue has become an important task in this field. 
       SUMMARY OF THE INVENTION 
       [0006]    According to a preferred embodiment of the present invention, a method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (STI) around the fin-shaped structures on the first region and the second region; forming a patterned hard mask on the second region; removing the fin-shaped structures and the first STI from the first region; forming a second STI on the first region; removing the patterned hard mask; and forming a gate structure on the second STI. 
         [0007]    According to another aspect of the present invention, a semiconductor device is disclosed. The semiconductor device includes: a substrate; a fin-shaped structure on the substrate and having a first portion and a second portion; and a shallow trench isolation (STI) between the first portion and the second portion of the fin-shaped structure. Preferably, the STI includes a top portion and a bottom portion, and the top portion is higher than the top surface of the fin-shaped structure. 
         [0008]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIGS. 1-6  illustrate a method for fabricating semiconductor device according to a preferred embodiment of the present invention. 
           [0010]      FIGS. 7-9  illustrate a method for fabricating a gate structure on the STI according to different embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0011]    Referring to  FIGS. 1-6 ,  FIGS. 1-6  illustrate a method for fabricating semiconductor device according to a preferred embodiment of the present invention, in which the top portion of  FIG. 1  illustrates a top view of the semiconductor device, the lower left portion illustrates a cross-sectional view of the top portion along the sectional line AA′, and the lower right portion illustrates a cross-sectional view of the top portion along the sectional line BB′. As shown in  FIG. 1 , a substrate  12 , such as a silicon substrate or silicon-on-insulator (SOI) substrate is provided, and a first region  14  and a second region  16  are defined on the substrate  12 . In this embodiment, the first region  14  is preferably used to form STI between fin-shaped structures while the second region  16  is preferably the region outside the first region  14 . A plurality of fin-shaped structures  18  is then formed on the substrate  12 , and a STI  20  is formed to surround the fin-shaped structures  18 . 
         [0012]    The formation of the fin-shaped structure  18  could be accomplished by first forming a patterned mask (now shown) on the substrate,  12 , and an etching process is performed to transfer the pattern of the patterned mask to the substrate  12 . Next, deposition, chemical mechanical polishing (CMP), and etching back processes are carried out to form a STI  20  surrounding the bottom of the fin-shaped structure  18 . Next, depending on the structural difference of a tri-gate transistor or dual-gate fin-shaped transistor being fabricated, the patterned mask could be selectively removed or retained. In this embodiment, it would be desirable to first remove the patterned mask so that the top surface of each fin-shaped structure  18  is even with the top surface of the STI. Alternatively, the formation of the fin-shaped structure  18  could also be accomplished by first forming a patterned hard mask (not shown) on the substrate  12 , and then performing an epitaxial process on the exposed substrate  12  through the patterned hard mask to grow a semiconductor layer. This semiconductor layer could then be used as the corresponding fin-shaped structure  18 . Similarly, the patterned hard mask could be removed selectively or retained, and deposition, CMP, and then etching back could be used to form a STI surrounding the bottom of the fin-shaped structure  18 . Moreover, if the substrate  12  were a SOI substrate, a patterned mask could be used to etch a semiconductor layer on the substrate until reaching a bottom oxide layer underneath the semiconductor layer to form the corresponding fin-shaped structure. If this means is chosen the aforementioned steps for fabricating the STI could be eliminated. 
         [0013]    Next, as shown in  FIG. 2 , a buffer layer  22  and a hard mask  24  are formed to cover the STI  20  and fin-shaped structures  18 , and another patterned mask, such as patterned resist  26  is formed on the hard mask  24  to expose the hard mask  24  surface on first region  14 . In this embodiment, the buffer layer  22  is composed of silicon oxide and the hard mask  24  is composed of silicon nitride, but not limited thereto. 
         [0014]    Next, as shown in  FIG. 3 , at least one etching process is conducted by using the patterned resist  26  as mask to remove the hard mask  24 , buffer layer  22 , fin-shaped structures  18 , and STI  20  on the first region  14 . This forms a recess  28  to expose the substrate  12  surface on first region  14 , in which the hard mask  24  is partially removed during the aforementioned etching process to form into a patterned hard mask  24  on the STI  20  and fin-shaped structures  18  on the second region  16 . Viewing from another perspective as shown in the right portion of  FIG. 3 , the etching process conducted by using the patterned resist  26  as mask preferably divides part of the fin-shaped structure  18  into two portions while the recess  28  is formed between the divided fin-shaped structure  18 . 
         [0015]    Next, as shown in  FIG. 4 , insulating material is deposited into the recess  28  to form another STI  30  on the first region  14 . In this embodiment, the formation of the STI  30  could be accomplished by first depositing an insulating material (not shown) composed of silicon oxide in the recess  28  on first region  14  and on top of the patterned hard mask  24  on second region  16 , and then using CMP process to remove part of the insulating material or even part of the patterned hard mask  24  so that the top surfaces of the insulating material and patterned hard mask  24  are coplanar. This forms a STI  30  on the first region  14 . 
         [0016]    Next, as shown in  FIG. 5 , an etching process is conducted to remove the patterned hard mask  24  from the second region  16  and expose the buffer layer  22  underneath. According to a preferred embodiment of the present invention, as shown in the cross-sectional view on the right hand side of  FIG. 5 , the STI  30  on the first region  14  preferably protrudes from the fin-shaped structure  18  after the patterned hard mask  24  is removed. 
         [0017]    Next, as shown in  FIG. 6 , another etching is conducted to remove part of the STI  30  on both first region  14  and second region  16  so that the fin-shaped structures  18  on second region  16  would protrude from the STI  30  surface while the STI  30  on first region  14  still protrude from the fin-shaped structure  18  surface. 
         [0018]    Referring to  FIGS. 7-9 ,  FIGS. 7-9  illustrate different embodiments of forming a gate structure on the STI  30  after STI  30  were formed to protrude from the fin-shaped structure  18  surface, in which each of the figures from  FIGS. 7-9  illustrate a cross-sectional view of  FIG. 1  along the sectional line BB′. A shown in  FIGS. 7-9 , an oxide layer  52  could be selectively formed on the fin-shaped structure  18 , and a gate structure formation process is carried out to form a dummy gate or gate structure  32  on the STI  30  of first region  14  and a dummy gate or gate structure  50  on the fin-shaped structure  18  of second region  16 , in which both the gate structures  32  and  50  are composed of polysilicon. A spacer  34  is then formed on the sidewalls of each of the gate structures  32  and  50 . In this embodiment, different embodiments of gate structures  32  formed on the STI  30  is revealed, such as the gate structure  32  shown in  FIG. 7  is disposed only on the STI  30  without passing or overlapping the sidewalls of the STI  30 , the gate structure  32  shown in  FIG. 8  is disposed on the STI  30  and aligned with the sidewalls of the STI  30 , or the gate structure  32  shown in  FIG. 9  is formed on both STI  30  and part of the fin-shaped structure  18  at the same time. 
         [0019]    In this embodiment, the fin-shaped structure  18  after being processed by the etching process in  FIG. 3  is divided into a first portion  36  and a second portion  38 , the STI  30  is disposed between the first portion  36  and the second portion  38 , the STI  30  includes a top portion  40  and a bottom portion  42 , and the top portion  40  is higher than the top surface of the fin-shaped structure  18 . Specifically, each of the top portion  40  and bottom portion  42  of the STI  30  includes a substantially trapezoid shaped cross-section. For instance, the trapezoid shaped cross-section of the top portion  40  includes a top surface  44 , a bottom surface  46 , and two inclined sidewalls  48 , in which the width of the top surface  44  is less than the width of the bottom surface  46 . 
         [0020]    As shown in the embodiment revealed in  FIG. 7 , the gate structure  32  is disposed on the top surface  44  of the STI  30  without overlapping the two inclined sidewalls  48 . The width of the gate structure  32  is preferably less than or equal to the width of the top surface  44 . The spacer  34  adjacent to the gate structure  32  is sitting on the top surface  44  and two inclined sidewalls  48 , or could even pass through the two inclined sidewalls  48  to sit on the first portion  36  and second portion  38  of the fin-shaped structure  18 . 
         [0021]    As shown in the embodiment revealed in  FIG. 8 , the gate structure  32  is disposed on the top surface  44  of the STI  30  and the two inclined sidewalls  48  of the top portion  40 , in which the sidewalls of the gate structure  32  are also aligned with the intersecting spot of the inclined sidewalls  48  and fin-shaped structure  18 . The spacer  34  adjacent to the gate structure  32  is preferably disposed on the first portion  36  and second portion  38  of the fin-shaped structure  18 . As shown in the embodiment revealed in  FIG. 9 , the gate structure  32  is disposed on the top surface  40  of the STI  30 , two inclined sidewalls  48 , and also on top of the first portion  36  and second portion  38  of the fin-shaped structure  18 . The spacer  34  adjacent to the gate structure  32  is disposed on the fin-shaped structure  18 . 
         [0022]    It should be noted that since the gate structure  50  on the second region  16  and the gate structure  32  on the STI  30  or on first region  14  are formed at the same time, the gate structures  50  and  32  are preferably made of same material, and the top surface of the gate structure  50  on second region  16  is preferably even with the top surface of the gate structure  32  on first region  14  or on STI  30 . 
         [0023]    Next, FinFET process could be conducted by forming a source/drain region and/or epitaxial layer in the fin-shaped structure  18  adjacent to two sides of the spacer  34 , selectively forming a silicide (not shown) on the source/drain region and/or epitaxial layer, forming a contact etch stop layer (CESL) on the gate structure or dummy gate, and forming an interlayer dielectric (ILD) layer on the CESL. Next, a replacement metal gate (RMG) process could be conducted to planarize part of the ILD layer and CESL and then transform the gate structures  32  and  50  composed of polysilicon into metal gates. Since the RMG process is well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. This completes the fabrication of a semiconductor device according to a preferred embodiment of the present invention. 
         [0024]    Overall, the present invention discloses an approach of forming STI between two fin-shaped structures, which preferably uses a patterned hard mask to remove part of the fin-shaped structure and part of STI on the substrate to form a recess, and then deposits insulating material into the recess to form another STI. After removing the patterned hard mask, the top surface of the newly formed STI would be higher than the top surface of the adjacent fin-shaped structure. Since the STI between fin-shaped structure is higher than the top surfaces of adjacent fin-shaped structures, the gate structure formed afterwards could be disposed directly on top of the fin-shaped structure so that the isolation effect of the STI is not compromised. 
         [0025]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.