Abstract:
A system for improving the operation of an autofocus circuit under high intensity light situations by controlling the &#34;start&#34; time of a plurality of detectors directly from a computer rather than through a clock which is limited in its ability to &#34;start&#34; by the phases of signals it generates.

Description:
BACKGROUND OF THE INVENTION 
     In U.S. Pat. No. 4,321,486 of Clifford H. Boler and myself and assigned to the assignee of the present invention, a system is described for use in autofocus cameras particularly of the through the lens type such as is found in the U.S. Pat. No. 4,333,007 of Richard A. Langlais, Francis T. Ogawa, and myself and also assigned to the assignee of the present invention. 
     Such systems operate utilizing a plurality of light sensitive detectors which are normally of the CCD type arranged in pairs behind a plurality of lenslets so as to receive an image of the exit pupil of the taking lens that receives light from the remote subject to be focused upon. If the taking lens is at the correct focal position, the outputs of the two detectors behind each lenslet will be substantially the same, but as the taking lens moves from the desired focal position, differences in the outputs of the two detectors behind each lenslet will occur in such a manner that the system may determine the direction and amount of movement necessary to bring the taking lens back to the proper focal position. In the circuitry of the prior art, a clock phase generator is employed to drive a shift register and a microprocessor operating through a bus control and an R-S flip-flop, operates to produce a &#34;start&#34; signal in synchronism with the clock to activate the detectors. The detectors then begin the process of integrating the light they receive. After a short period of time which depends normally upon the intensity of light being received, the clock operates to activate a transfer gate which then dumps the built-up charges on the individual detectors in parallel into the shift register. The shift register produces these signals in series to the microcomputer so that they may be analyzed to determine the correct output for proper focus. 
     Because the shift register is driven by the clock producing 3 phases, φ 1 , φ 2 , and φ 3 , there are only predetermined times available when the charges from the detector may be dumped into the shift register (for example, upon the occurrence of a φ 1  signal). When it is desired to &#34;start&#34; the detectors, the microprocessor through the bus control produces a signal, this signal is usually the removal of a voltage to the reset terminal of an R-S flip-flop to cause resetting thereof. The set terminal of the flip-flop is connected to the clock so that after reset, the next φ 1  of the clock causes the flip-flop to produce an output to activate the detectors. At the end of the desired integrating period, a signal from the microprocessor causes the clock to produce a transfer signal, at the next φ 1 , directly to the transfer gate which then dumps the charges from the detectors into the shift register. 
     In the system described above, the switching on and off must be done in synchronism with the clock, and as will be more fully discussed hereinafter in connection with FIG. 1, this produces a problem when very high intensities of light are encountered. Since, as mentioned above, the flip-flop is triggered by the falling edge of one of the three phases of the clock, the detectors can only be activated at one of these three times in a cycle. Likewise, since the shift register can only receive the charges from the detectors at the predetermined times (for exmaple the falling edge of φ 1 ), the transfer gate can be activated only then. Therefore, the minimum time period between activation of the detectors and dumping the charges into the shift register can be no shorter than the time from one falling edge of a signal from the clock to the next time the shift register is capable of receiving the next group of charges, i.e., the time between the two consecutive φ 1  &#39;s. This time period, although very short, may be still too long in the event of high intensities of light and the detectors may saturate and thus loose the significance of their charges during that short time period. Furthermore, there is no way to vary the exposure time of the detectors between the occurrences of all three phases. 
     SUMMARY OF THE INVENTION 
     The present invention provides an improvement which will allow the &#34;start&#34; signal to the detectors to occur at any desired time so that then the time period between the &#34;start&#34; signal and the &#34;transfer&#34; signal can be made as short as is needed and can be made as variable as desired. More particularly, the present invention provides this feature by allowing the microprocessor operating through the bus control to directly and asynchronously with the clock, produce the &#34;start&#34; signal to the detectors rather than, as in the prior art, producing the &#34;start&#34; signal in conjunction and synchronously with the clock. Thus, the microprocessor alone controls the time of &#34;start&#34; and, while the clock must still control the &#34;transfer&#34; signal (because the shift register driven thereby can only accept charges at predetermined times in its cycle) being able to start at a time later than that allowed by the falling edge of on of the three phases permits the narrowing of the integration time to any desired value and thus allows greater light intensities to be considered. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a simplified block diagram of the circuitry of the prior art; and 
     FIG. 2 shows a block diagram of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 shows a simplified block diagram of the prior art similar to that shown in the above-referred to United States patents. In FIG. 1 a clock 10 is shown producing three phase signals identified as φ 1 , φ 2 , and φ 3 . An R-S flip-flop 20 is shown having a &#34;S&#34; input connected to receive at least one of the phase signals from clock 10 by way of a line 22. 
     A control microprocessor 30 is also shown which is connected by way of a line 32 to a bus control 34. The bus control is connected to the &#34;R&#34; input of flip-flop 20 by way of a line 36. Bus control 34 is also connected to clock 10 and vise versa by line 38 so that microprocessor 30 is aware of the phase timings of the clock 10 and clock 10 can receive command signals from microprocessor 30. 
     An array of detectors 40, which detectors may be of the CCD type, is shown connected to receive the &#34;Q&#34; output from flip-flop 20 by way of a line 42. The &#34;Q&#34; output from flip-flop 20 on line 42 is used to produce the &#34;start&#34; signal for the detectors in array 40. Although not shown, the detectors in the array 40 receive light through the taking lens of a camera from a remote object and upon the occurrence of a &#34;start&#34; signal, begin integrating that light. 
     Clock 10 is also shown connected by way of a line 46 to a shift register 50 and thereby controls the timing of the shift register synchronously with the phase φ 1 , φ 2 , and φ 3 . At certain predetermined times, the shift register produces the charges stored therein on a line 52 which is used to provide information to utilization apparatus such as a computer or back to microprocessor 30 in order to enable the computer to determine the proper focus position for the taking lens of the camera. Accordingly, there is only certain times at which the shift register 50 is capable of receiving charges from the detectors 40. These times are controlled by the clock 10 and a transfer gate 60 which is shown connected between detector array 40 and shift register 50 by lines 62 and 64 respectively. Transfer gate 60 is connected to clock 10 by way of a line 66. A signal such as φ 1 , φ 2  or φ 3  trailing edge on line 66 from clock 10 operates to open transfer gate 60 at such times as the shift register 50 can receive the charges from the detectors in array 40 and the charges on the detectors are then dumped via line 62, transfer gate 60, and line 64 into shift register 50. 
     Because flip-flop 20 operates to produce a signal from its &#34;Q&#34; output on line 42 only upon the occurrence of a set signal from clock 10, e.g., the trailing edge of a φ 1 , φ 2 , or φ 3 , on line 22 after receipt of a reset signal from microprocessor 30 through bus control 34 on line 36, the &#34;start&#34; time for the detector array 40 is limited to the time that the trailing edge of the chosen phase occurs from clock 10. More particularly, if the prior art utilized the falling edge of, say, the φ 1  signal to operate flip-flop 20, the &#34;start&#34; signal to the detector array 40 could only occur at that time. Since, as mentioned above, transfer gate 60 can only dump the charges into shift register 50 at predetermined times (for example, another falling edge of, say, φ 1 ), the shortest interval of time between the &#34;start&#34; and the &#34;transfer&#34; is the time interval between two falling edges of the φ 1  signal. This time period may be too long to accommodate certain very bright scenes wherein the intensity of light falling on the detectors in array 40 is great enough that during this short interval of time the detectors will have integrated all of the light they can, have saturated, and their output become relatively useless for analyzation by the downstream computer. If attempts are made to operate the flip-flop 20 on the occurrence of a φ 2  or φ 3  falling edge, this time could be shortened but perhaps still not enough and other problems would also be involved, i.e., no matter which phase is chosen to set the flip-flop 20, there can thereafter be no variation in the start signal and the timer period between two set signsl will still be the full three phase signals. Thus, if a time greater than that between φ 3  and φ 1  but less than the time between φ 1  and the next φ 1  were desired, the apparatus could not accommodate it. It is therefore desirable to provide &#34;start&#34; time which is not dependent on the clock phases so that shorter and more variable exposure times for the detectors than that presently available in the prior art. 
     In FIG. 2, a relatively simple modification to the circuit of FIG. 1 enables the &#34;start&#34; signal to be produced at any time rather than at only those times dictated by the falling edge of on of the three phase signals. In FIG. 3, the components which are common to FIG. 2 have the same reference numerals for convenience. Clock 10 is again shown producing the three phase signals φ 1 , φ 2 , and φ 3 . The microprocessor 30 is also shown connected by way of the line 32 to the bus control 34. The detector array 40 is shown connected to the transfer gate 60 by way of the line 62 and the shift register 50, having an output on line 52, is shown connected to the transfer gate 60 by way of a line 64. Shift register 50 is again connected to the clock 10 by way of a line 46 to receive the timing signals therefrom and the transfer gate 60 is again activated by clock 10 via line 66. Clock 10 is shown connected to the bus control by a two-way line 38 so that microprocessor 30 can receive information of the timing of clock 10 and can send a signal through bus control 34 to clock 10 when it is desired to terminate integration and transfer the charges from the detectors and arra 40 through transfer gate 60 to shift register 50. 
     In FIG. 2 the flip-flop 20 of FIG. 1 has been eliminated and the &#34;start&#34; signal to the detectors in array 40 is controlled directly by the microprocessor 30 through the bus control 34 via a line 82. Accordingly, when it is desired to begin integration, microprocessor 30 through bus control 34 sends a &#34;start&#34; signal by way of line 82 to the detectors in array 40 and this signal may be produced at any particular time chosen by microprocessor 30 regardless of the phases of the signals to clock 10. Later, when it is desired to stop integration and transfer the signals to the shift register 50, microprocessor 30 through bus control 34, line 38, and clock 10 produces a signal on line 66 to transfer gate 60 so that the charges are then dumped into shift register 50. Although this latter signal can only occur at predetermined times as before, the &#34;start&#34; signal on line 82 can be as short prior to this time as is necessary to accommodate high lighting situations. 
     Accordingly, it is seen that I have provided a circuit with only a simple adjustment from the prior art to accomplish an improved performance under high intensity situations for an autofocus circuit. By doing so I have eliminated components which make the resulting circuitry simpler and less expensive. I do not wish, however, to be limited by the specific disclosures used in connection with the preferred embodiment and intend rather only to be limited by the following claims.