Abstract:
A process for simultaneously forming a first opening to a copper contact structure, and a deeper, second opening, overlying a fuse structure, has been developed. The process features the use of a barrier metal shape, located on a recessed copper contact structure, providing the needed etch stop during a dry etching procedure used to define a first opening in a composite insulator layer. The low etch rate exhibited by the barrier metal shape, in this dry etching environment provides protection of the recessed copper contact structure during the extended dry etching procedure, which is employed to form a deeper, second opening, in thicker dielectric layers, in a region overlying the fuse structure.

Description:
BACKGROUND OF THE INVENTION 
     (1) Field of the Invention 
     The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form an opening to, and then to protect, a copper structure, during a procedure used to form a fuse opening. 
     (2) Description of Prior Art 
     Fuse, of antifuse elements have been used to allow defective regions, in a body of array devices, to be replaced with adjacent, spare device arrays. This is accomplished by placing a programmable fuse or antifuse element, between the main body of gate arrays, and a region comprised of replacement gate arrays. The fuse or antifuse element can sometimes be comprised of a high resistance material, such as amorphous silicon, resulting in an “off” state. The high resistance material, although physically connected to both the main body of gate arrays, and the region of replacement arrays, is not electrically connected due its high resistance. A laser or high voltage pulsing procedure, results in the conversion of the high resistance amorphous silicon layer to a low resistance layer, resulting in the “on” state, featuring electrical, as well as physical connection to both the main body of gate arrays, and to the region of spare gate arrays. 
     To reduce processing costs and complexity the fuse opening in dielectric layers, used to expose the region of the fuse structure to be pulsed, is sometimes simultaneously accomplished with an opening procedure used to expose the top surface of a metal pad structure, wherein the metal pad structure is either used to accept a wire bond, or to be used as a pad for a “flip chip” attachment to a ceramic module, or package. However the underlying fuse structure is located deeper than the metal pad structure, therefore if simultaneous openings are desired, via dry etching procedures, the metal pad structure will be exposed to additional dry etching procedures used to form a deeper opening for exposure of the fuse structure. The exposed metal pad layer, sometimes comprised of copper, can therefore be damaged when subjected to the additional dry etching needed to complete the fuse opening. 
     This invention will describe a procedure for simultaneously forming openings to a copper pad structure, and to a fuse structure, in which the fuse opening, formed in a group of dielectric layers, is deeper then the opening to the metal pad structure, which is formed in a thinner group of dielectric layers. This is accomplished via forming a barrier layer, overlying a recessed metal pad structure, offering high etch rate selectivity between the dielectric layers, overlying the fuse structure, and the barrier layer, thus protecting the metal, or copper pad structure, during the remaining fuse opening procedure. Prior art, such as Motsiff et al, in U.S. Pat. No. 5,795,819, describe a procedure for simultaneously forming openings to a wire bond pad, and to a fuse structure. However that prior art forms both openings in the same thickness of insulator, therefore not describing the novel barrier layer, overlying a recessed metal pad structure, needed in the present invention for protection of the metal pad structure during the conclusion of the fuse opening procedure. 
     SUMMARY OF THE INVENTION 
     It is an object of this invention to simultaneously form an opening to a metal pad structure, in a first group of dielectric layers, and to form a deeper opening to a fuse structure, in a second group of dielectric layers, with the first group of dielectric layers included in the thicker, second group of dielectric layers. 
     It is another object of this invention to recess the metal pad structure, below the top surface of the dielectric layer in which the metal pad structure is located in. 
     It is still another object of this invention to form a barrier metal shaper on the top surface of the recessed metal pad structure. 
     It is still yet another object of this invention to simultaneously form openings to the metal pad structure, and to the fuse structure, via a dry etching procedure which exhibits high etch rate selectivity between the groups of dielectric layers, and the barrier metal shape, located on the recessed metal pad structure. 
     In accordance with the present invention a method of forming an opening to a metal contact structure, and simultaneously forming a deeper opening to a fuse structure, featuring the use of a barrier metal shape, overlying a recessed metal pad structure, is described. A metal contact structure is formed in a dual damascene opening in a first composite dielectric layer. The metal contact structure is then recessed below the top surface of the first composite dielectric, exposing an underlying metal interconnect structure. A barrier metal layer is deposited, then subjected to a chemical mechanical polishing procedure, resulting in the barrier metal shape residing only on the top surface of the recessed metal contact structure. After deposition of an overlying second composite dielectric layer, photolithographic and reactive ion etching, (RIE), procedures are used to form a first opening in the second composite dielectric layer, exposing the top surface of the barrier metal shape, located on the top surface of the recessed metal contact structure; and to form a second opening in the second composite dielectric layer, and in a top portion of the first composite dielectric layer, exposing a region of insulator layer overlying a fuse structure. The barrier metal shape protected the underlying recessed metal contact structure, during the extended RIE procedure. A second barrier metal layer, and a conductive layer, are next deposited, followed by conventional photolithographic and RIE procedures, creating a bonding pad structure, in a region overlying and contacting, the recessed metal contact structure, structure. The same RIE procedure. unprotected by the photoresist shape used to define the bonding pad structure, results in the formation of spacers on the sides of the fuse opening. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The object and other advantages of this invention are best described in the preferred embodiment with reference to the attached drawings that include: 
     FIGS. 1-9, which schematically, in cross-sectional style, describe key stages of fabrication used to form an opening to a metal contact structure, and to simultaneously form a deeper opening to a fuse structure. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The method of forming an opening to a metal contact structure, and simultaneously forming a deeper opening to a fuse structure, will now be described in detail. FIG. 1, schematically shows metal plug structure  2 , in region  50 , to be used for a metal contact structure, and metal plug structures  3 , in region  60 , to be used for a fuse structure. Metal plug structures  2  and  3 , comprised of a metal chosen from a group that containing metals such as aluminum, tungsten, or copper, are located in via holes that in turn are opened in an intermetal dielectric, (IMD), layer  1 , with IMD layer  1 , comprised of an insulator layer such as a silicon oxide, or borophosphosilicate glass, (BPSG). The metal plug structures are formed via deposition of the metal, using plasma vapor deposition, (PVD), procedures, filling the via holes, followed by a chemical mechanical polishing, (CMP), procedure, resulting in the formation of the metal plug structures, in the via holes. 
     Deposition of another IMD layer, such as silicon oxide, or BPSG, obtained via low pressure chemical vapor deposition, (LPCVD), or via plasma enhanced chemical vapor deposition, (PECVD), procedures, is obtained at a thickness between about 3000 to 8000 Angstroms, then patterned via conventional photolithographic, (photoresist shape  5 ), and reactive ion etching, (RIE), to form IMD pad  4 , shown schematically in FIG.  2 . After removal of photoresist shape  5 , via plasma oxygen ashing and careful wet cleans, an electrochemical deposition, (ECD), of copper, at a thickness between about 3000 to 8000 Angstroms is performed, followed by a CMP procedure, resulting in definition of metal pad, or metal interconnect structure  6 a, in metal contact region  50 , and metal pad, or fuse structure  6 b, in fuse structure region  60 . This is schematically shown in FIG.  3 . 
     A series of insulator layers, to be used to accept a dual damascene opening in metal contact region  50 , are next deposited, and shown schematically in FIG. 4. A liner layer  7 , comprised of silicon nitride, is first deposited via LPCVD or PECVD procedures, at a thickness between about 300 to 1000 Angstroms, followed by deposition of insulator layer  8 , comprised of either silicon oxide or BPSG, at a thickness between about 5000 to 10000 Angstroms, again using LPCVD or PECVD procedures. LPCVD or PECVD procedures are again employed to deposit etch stop layer, (ESL),  9 , comprised of silicon nitride, at a thickness between about 300 to 800 Angstroms, followed by deposition of insulator layer  10 , comprised of BPSG or silicon oxide, at a thickness between about 4000 to 15000 Angstroms. Finally another barrier layer  11 , such as silicon nitride, or silicon oxynitride, is deposited, again via LPCVD or PECVD procedures, at a thickness between about 400 to 1200 Angstroms. Photoresist shape  12 , is then used as an etch mask to allow a RIE procedure, using CF 4  as an etchant for the silicon nitride, or silicon oxynitride layers, and using CHF 3  as an etchant for the silicon oxide or BPSG layers, to form the narrow diameter component  13 , of a subsequent dual damascene opening, exposing the top surface of metal structure  6   a , in metal contact region  50 . This is schematically shown in FIG.  4 . 
     After removal of photoresist shape  12 , used to define narrow diameter opening  13 , via plasma oxygen ashing and careful wet cleans, photoresist shape  14 , is formed and used as an etch mask to define wide diameter opening  15 , via anisotropic RIE procedures, again using CF 4  as an etchant for silicon nitride, and using CHF 3  as an etchant for silicon oxide or BPSG. This is schematically shown in FIG.  5 . After removal of photoresist shape  14 , via plasma oxygen ashing and careful wet cleans, copper is deposited via ECD procedures, to a thickness between about 6000 to 20000 Angstroms, completely filling the dual damascene opening. A CMP procedure is next performed removing the regions of the copper layer from the top surface of silicon nitride layer  11 , resulting in the formation of copper structure  16   a , in dual damascene opening  15 . This is schematically shown in FIG.  6 . 
     Preparing copper structure  16   a , for protection from a subsequent RIE procedure, used to from a deep opening in fuse region  60 , is next addressed. The objective is to place a metal barrier shape on the top surface of copper structure  16   a , which will withstand the RIE procedure used to define a deep fuse opening, after a shallower opening to copper structure  16   a , has been completed. The process used to satisfy this objective is initiated by recessing of copper structure  16   a . This is accomplished via a blanket, selective wet etch procedure, removing, or recessing copper structure  16   a , between about 1000 to 2000 Angstroms below the top surface of the dual damascene opening, resulting in recessed copper structure  16   b , schematically shown in FIG.  7 . The selective wet etch used for copper recessing allows the attainment of recessed copper structure  16   b , to be accomplished without any etching of, or removal of silicon nitride layer  11 . A barrier metal layer, such as tantalum nitride, is next deposited via PVD procedures, to a thickness between about 100 to 1000 Angstroms. A CMP procedure is then employed to selectively remove regions of the barrier metal layer from the top surface of silicon nitride layer  11 , resulting in barrier metal shape  17 , only overlying recessed copper structure  16   b , and with the top surface of barrier metal shape  17 , planar with the top surface of silicon nitride layer  11 . This is schematically shown in FIG.  7 . 
     A composite insulator layer, comprised of an underlying silicon oxide layer  18 , at a thickness between about 3000 to 6000 Angstroms, and an overlying silicon nitride layer  19 , at a thickness between about 4000 to 10000 Angstroms, is next deposited via LPCVD or PECVD procedures. A photoresist shape  20 , is next formed on the composite insulator layer, and used as a mask to allow an anisotropic RIE procedure, using CF 4  as an etchant for silicon nitride layers, and CF 3  as an etchant for silicon oxide and BPSG layers, to define deep opening  22 , in fuse region  60 , with the RIE procedure terminated in insulator layer  8 . The bottom of deep opening  22 , is located between about 5000 to 10000 Angstroms above the top surface of metal structure  6   b , in fuse region  60 . The same photolithographic and anisotropic RIE procedure results in the definition of shallow opening  21 , in metal contact region  50  The presence of tantalum nitride shape  17 , with a low etch rate in CF 4  and CHF 3 , protected underlying copper structure  16   b , during the definition of deeper opening  22  The etch rate ratio of silicon oxide, and silicon nitride, to tantalum nitride, in a CF 4  or in a CHF 3  ambient, is between about 100 to 1. This is schematically shown in FIG.  8 . 
     After removal of photoresist shape  20 , via plasma oxygen ashing and careful wet cleans, shallow opening  21 , exposing recessed copper structure  16   b , is prepared for either wire bonding to a ceramic module or package, or is prepared for a subsequent flip chop configuration, also used to connect a semiconductor chip to a module or carrier. For the case of a subsequent wire bond, a tantalum nitride layer  23 , is deposited via PVD procedures, to a thickness between about 300 to 1000 Angstroms, followed by the deposition of aluminum layer  24 , via PVD procedures, at a thickness between about 4000 to 1500 Angstroms. Aluminum layer  24 , completely fills shallow opening  21   b , while only coating the exposed surfaces of deeper opening  22 . A photoresist shape, not shown in the drawings, is then formed on a portion of aluminum layer  24 , in a region overlying recessed copper structure  16   b , while the remaining portion of aluminum layer  24 , is not covered by photoresist. A selective RIE procedure, using Cl 2  or SF 6  as an etchant, are used to define wire bond pad  30 , comprised of aluminum layer  24 , and underlying tantalum nitride layer  23 . The same selective RIE procedure results in the removal of both aluminum layer  24 , and of tantalum nitride layer  23 , in the bottom of deeper opening  22 , exposing the bottom portion of insulator layer  8 , overlying metal structure  6   b , in fuse region  60 . In addition, spacers comprised of aluminum layer  24 , and tantalum nitride layer  23 , are formed on the sides of deeper opening  22 . The photoresist shape used to define wire bond pad  30 , is again removed via plasma oxygen ashing and careful wet cleans. The result of these procedures is schematically shown in FIG.  9 . The spacers formed on the sides of deeper opening  22 , will protect the materials adjacent to this opening during a high voltage pulse or a laser application, used to convert a high resistance fuse structure, to a lower resistance structure, allowing electrical connection between elements or arrays, located at both ends of the fuse structure. A wire bond, such as a gold bond, can now be successfully made on bond pad structure  30 , allowing electrical communication between underlying conductive regions, of a semiconductor chip, and a ceramic package, to be realized. 
     While this invention has been particularly shown and described with reference to, the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of this invention.