Abstract:
A method of computing overhead associated with executing instructions on an out-of-order processor which includes determining when a first instruction retires, determining when a second instruction retires, and calculating an overhead based upon subtracting when the first instruction retired from when the second instruction retired.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to out-of-order processors and more particularly to computing overhead for out-of-order processors. 
   2. Description of the Related Art 
   It is relatively straightforward to determine execution time that an instruction spends in an in-order processor. A younger instruction is issued only after all older instructions have been issued and retired (i.e., completed). Sampling a Program Counter (PC) at a given interval provides statistical time spent on each instruction by comparing when the instruction completes execution (i.e., retires) against when the instruction started execution using the PC. For example,  FIG. 1 , labeled Prior Art, shows a sequence of three instructions. The first instruction takes 10 cycles to execute, the second instruction starts executing when the first instruction retires and takes 5 cycles to execute and the third instruction starts executing when the second instruction retires, takes 15 cycles to execute and retires after a total of 30 cycles from the beginning of the first instruction to the retiring of the third instruction. Thus, the first instruction uses 10/30 (33.3%) of the total execution time, the second instruction uses 5/30 (16.6%) or the total execution time and the third instruction uses 15/30 (50%) or the total execution time. 
   However, determining execution time for an instruction when the processor is an OOO (out-of-order) processor is more difficult. When instructions are issued out-of-order, there is no guarantee that a younger instruction is issued after all old instructions are issued and retired. Also, multiple outstanding transactions to memory and parallel replays and rewinds make it difficult to compute the overhead in a program. For example, determining that a program has 12% of total clock cycles attributable to Level 2 cache misses does not provide much insight into what percentage of the total elapsed time is attributed to the Level 2 cache misses. Of the 12% total clock cycles, it is possible that more than 6% of the total clock cycles are attributable to one L2 cache miss. 
     FIG. 2 , labeled Prior Art, shows an example of this issue. In the  FIG. 2  example, the first instruction starts executing at clock cycle t and retires at clock cycle t+10. The second instruction starts executing at clock cycle t+2 and retires at clock cycle t+25. The third instruction starts executing at clock cycle t+2 and retires at clock cycle t+30. Thus, the first instruction uses 10/30 (33.3%) of the elapsed time, but 10/61 (16.4%) of the total execution cycles. The second instruction uses 23/30 (76.6%) of the elapsed time, but 23/61 (37.7%) of the total execution cycles. The third instruction uses 28/30 (93.3%) of the elapsed time, but 28/61 (46.6%) of the total execution time. The percentage of total elapsed time is the overhead computation that is desirable to determine. However, this is the computation that is difficult to determine with OOO processors. 
   SUMMARY OF THE INVENTION 
   In one embodiment, the invention relates to a method of computing overhead associated with executing instructions on an out-of-order processor which includes determining when a first instruction retires, determining when a second instruction retires, and calculating an overhead based upon subtracting when the first instruction retired from when the second instruction retired. 
   In one embodiment, the inventions relates to an apparatus for computing overhead associated with executing instructions on an out-of-order processor which includes means for determining when a first instruction retires, means for determining when a second instruction retires, and means for calculating an overhead based upon subtracting when the first instruction retired from when the second instruction retired. 
   In one embodiment, the invention relates to a system for computing overhead associated with executing instructions on an out-of-order processor which includes a first determining module, a second determining module and an overhead calculating module. The first determining module determines when a first instruction retires. The second determining module determines when a second instruction retires. The overhead calculating module calculates an overhead based upon subtracting when the first instruction retired from when the second instruction retired. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference number throughout the several figures designates a like or similar element. 
       FIG. 1 , labeled Prior Art, shows a timing diagram of a sequence of three instructions executing on an in-order processor. 
       FIG. 2 , labeled Prior Art, shows a timing diagram of a set of three instructions executing on an out-of-order processor. 
       FIG. 3  shows a block diagram of an out-of-order processor in which the execution overhead is computed 
       FIG. 4  shows a flow chart of the operation of the method for computing overhead in an out-of-order processor. 
       FIG. 5  shows an example of the results from the use of the method for computing overhead. 
   

   DETAILED DESCRIPTION 
   Referring to  FIG. 3 , a block diagram of an example out-of-order (OOO) processor  100  is shown. The out-of-order processor  100  may execute program instructions in an order different from the order present in the user program. When the OOO processor  100  stalls on an instruction, the processor  100  looks ahead and executes instructions provided that the instructions are independent instructions. Even though the OOO processor  100  executes instructions in an out-of-order fashion, completed instructions must retire from the processor in-order. I.e., even if an instruction is completed, the instruction can not retire from the processor  100  if one of the older instructions is not retired. This is to maintain the TSO (Total Store Ordering) constraint. 
   With the OOO processor  100 , the overhead computation is performed based upon precise traps as compared to deferred traps. A precise trap is induced by a particular instruction and occurs before any program visible state has been changed by the trap inducing instruction. A deferred trap is induced by a particular instruction; however, a deferred trap may occur after a program visible state has been changed. Such a state may have been changed by the execution of either the trap inducing instruction itself or by one or more other instructions. 
   The processor includes Instruction Scheduling Window (ISW)  122  and one or more execution units  124 . To achieve out-of-order execution, the processor  100  maintains a plurality of buffers to hold the intermediate results. More specifically, the processor includes a Memory Disambiguation Buffer (MDB)  120 , Load Buffer (LB)  126 , and a Store Buffer (SB)  128 . 
   Each instruction in the program first gets inserted into the Instruction Scheduling Window  122 . The Instruction Scheduling Window  122  is the window that tracks the instruction execution order. Instructions enter and exit from the Instruction Scheduling Window  122 . From the Instruction Scheduling Window  122 , each instruction that is ready (i.e., all operands for the instruction are available for execution), is accessed and executes via the appropriate execution unit  124  in the processor pipeline. If the instruction is a load or a store instruction, the instruction is also inserted into MDB  120 . MDB  120  addresses any TSO constraints. Since loads and stores may get executed in an out-of-order fashion, it is necessary that the loads are provided the latest data either from the appropriate cache or from the appropriate store instruction in the MDB  120 . 
   If a load misses the L1 Cache  130 , the request to fill the L1 cache line goes to the Load Buffer  126 . Load Buffer  126  issues requests to either the L2 Cache  132  or to memory and installs a line into L1 Cache  130 . Once the line gets installed in the L1 Cache  130 , the corresponding entry from Load Buffer  126  is released. Until the load completes its execution, the load resides in Load Buffer  126 . 
   Stores are also inserted into the MDB  120 . Stores provide data to longer load instructions if the addresses correspond. There are a plurality of conditions imposed in the processor architecture that enable bypassing store data to load. Since the OOO processor  100  looks ahead and execute independent instructions, the processor  100  may execute load instructions which are dependent on older store instructions. A dependency check is performed between instructions based on register entries and not based on memory addresses. Because loads and stores are dependent on each other based on memory address, younger loads potentially get executed before older stores complete. If this condition is detected, the processor  100  recycles the load as an OverEager (OE) load. 
   Loads can get data either from a cache or from the older stores in the MDB  120 . If the load address matches with any of the older stores, the load should get data from the store in the MDB  120 . This is called a read after write (RAW) bypass. If the store cannot bypass to the load, then the load gets replayed. This is called RAW recycling. 
   Referring to  FIG. 4 , a flow chart of the operation of the method of computing overhead in an out-of-order processor is shown. More specifically, the method starts by executing an instruction at step  210 . The method then determines whether the instruction is retired at step  216 . If the instruction is not retired, then the instruction is discarded at step  218 . 
   If the instruction is retired (i.e., the instruction has completed its execution), then the method calculates the overhead percentage for each event of the instruction at step  220 . After the overhead percentages are calculated at step  220  then the method determines whether there are any instructions left to execute at step  222 . If so, then the method returns to step  210  and the next instruction is executed. 
   If there are not any more instructions in the program as determined at step  222 , then the method accumulates the overhead breakdown for each of the events at step  226  and completes execution. 
   Accordingly, targeting event counters to only “retired instructions” provides performance bottleneck information for a specific program. This performance bottleneck information enables performance engineers to tune a program. 
   More specifically, for each instruction in the scheduling window, cycle counts when an event occurs are recorded. When that instruction is in the correct path and gets retired, using the information recorded, the retired latency between two consecutive instructions (ret 13 lat) may be obtained. More specifically,
 
ret_lat =‘cycle when instruction  x  retired’−‘cycle when instruction  x− 1 retired’
 
   This retired latency, ret_lat, represents an overhead for the instruction. One cycle out of ret_lat accounts for normal instruction retirement. The remaining amount of cycles (ret — 1) represents as overhead.
 
overhead=(ret — 1)
 
   The method  200  computes a plurality of specific event overheads associated with out-of-order processors. More specifically, the method calculates event overheads for the percentage of cycles when MDB  120  was full; the percentage of cycles when MDB  120  read after write recycled; the percentage of cycles when MDB  120  partial read after write recycled; the percentage of cycles when STB partial read after write recycled; the percentage of cycles when LMB  126  is full; the percentage of cycles when a TLB fill event happened; the percentage of cycles when an Over Eager load is recycled; the percentage of cycles when an L1 Cache  130  bank conflict triggers recycling; the percentage of cycles when the TLB was busy; and the percentage of cycles when a load instruction is waiting for data in the L1 Cache  130 . 
   The overhead is separated into different components based on events that occur during the life cycle of each instruction.  FIG. 5  shows an example of the results of the use of this method. For example, if an instruction spends 10% of its execution time on replaying because of Level 2 cache misses and 20% of its execution time on memory disambiguation buffer full condition and 50% of its execution time on Level 3 cache miss, the following breakdown of overhead is provided:
 
% of L2 cache miss=overhead*10%
 
% of MBD full replay=overhead*20%
 
% of L3 cache miss=overhead*50%
 
% of base execution=20%
 
   This overhead breakdown provides accurate information as well as overall information on the amount of bottleneck in the program. 
   More specifically, instructions (1), (2), (3), (4) and (5) get inserted into ISW  122 . Assume that the load instruction in (1) gets its data from LI Cache  130 . Instruction (2) cannot be issued unless instruction (1) is able to bypass its result through register % f 1 . So, the retired latency (Ret Lat) for instruction (2) is from the completion of (1) to completion of (2). But, instruction (3) is independent of (1) and (2). Hence instruction (3) is issued in parallel with instruction (1). If the load at instruction (3) misses L1 cache  130  and has to wait until it gets a line from L2 Cache  132 . So, the retired latency for instruction (3) is the difference in time from when instruction (2) retired to the time when instruction (3) retired. There are no negative retired latencies. If the instruction completes before the previous instruction, then the Ret Lat=0 (e.g., the Ret Lat for instruction (4)=0). Also, the retired latency is calculated from the most recent retired instruction (e.g., the retired latency for instruction (5) is the difference in time from when instruction (3) retired to when instruction (5) retired). 
   The present invention is well adapted to attain the advantages mentioned as well as others inherent therein. While the present invention has been depicted, described, and is defined by reference to particular embodiments of the invention, such references do not imply a limitation on the invention, and no such limitation is to be inferred. The invention is capable of considerable modification, alteration, and equivalents in form and function, as will occur to those ordinarily skilled in the pertinent arts. The depicted and described embodiments are examples only, and are not exhaustive of the scope of the invention. 
   Also for example, the above-discussed embodiments include software modules that perform certain tasks. The software modules discussed herein may include script, batch, or other executable files. The software modules may be stored on a machine-readable or computer-readable storage medium such as a disk drive. Storage devices used for storing software modules in accordance with an embodiment of the invention may be magnetic floppy disks, hard disks, or optical discs such as CD-ROMs or CD-Rs, for example. A storage device used for storing firmware or hardware modules in accordance with an embodiment of the invention may also include a semiconductor-based memory, which may be permanently, removably or remotely coupled to a microprocessor/memory system. Thus, the modules may be stored within a computer system memory to configure the computer system to perform the functions of the module. Other new and various types of computer-readable storage media may be used to store the modules discussed herein. Additionally, those skilled in the art will recognize that the separation of functionality into modules is for illustrative purposes. Alternative embodiments may merge the functionality of multiple modules into a single module or may impose an alternate decomposition of functionality of modules. For example, a software module for calling sub-modules may be decomposed so that each sub-module performs its function and passes control directly to another sub-module. 
   Consequently, the invention is intended to be limited only by the spirit and scope of the appended claims, giving full cognizance to equivalents in all respects.