Abstract:
An active power-on reset (POR) current comparator circuit creates a POR signal for resetting logic devices and masking reference startup signals during the initial power supply ramp of an integrated circuit. The comparator circuit provides a logic level signal (i.e., the POR signal) that will actuate when a bias current is above a predetermined level as compared to another current. The predetermined level for the bias current is set by a ratio established between two resistance levels within the active POR current comparator circuit.

Description:
FIELD OF THE INVENTION 
   The present invention relates to the field of power-on reset circuits, and in particular, to an apparatus and method for an active power-on reset current comparator circuit. 
   BACKGROUND OF THE INVENTION 
   Circuits often use a power-on reset (POR) signal for resetting the circuitry during power-up. As the bias current approaches a stable operating level, the POR signal is used to reset, or initialize, the circuitry. Circuits may also use a POR signal to disable certain circuits until a stable bias current signal is available. Using a POR signal ensures stable operation of the circuit until a stead-state is reached. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  illustrates a schematic diagram of an active power-on reset current comparator circuit; 
       FIG. 2  illustrates a schematic diagram of another active power-on reset current comparator circuit; and 
       FIG. 3  illustrates a schematic diagram of a further active power-on reset current comparator circuit, in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
   In the following detailed description of exemplary embodiments of the invention, reference is made to the accompanied drawings, which form a part hereof, and which is shown by way of illustration, specific exemplary embodiments of which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims. 
   Throughout the specification, and in the claims, the term “connected” means a direct electrical connection between the things that are connected, without any intermediary devices. The term “coupled” means either a direct electrical connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term “signal” means at least one current signal, voltage signal or data signal. 
   The present invention relates to an active power-on reset (POR) current comparator circuit. The POR current comparator circuit compares the ratio of two currents. A first current is produced in response to a current proportional-to-absolute-temperature generator (I PTAT  generator). The I PTAT  current is determined according to a first resistance level. A second current is determined in response to the I PTAT  current and a second resistance level. When compared, the first and second currents are related according to a scaling factor (e.g., N). The scaling factor may be selected such that the POR signal will de-assert at any selected point during startup. The present invention allows for the generation of a POR signal from a higher voltage supply (e.g., 40V) while using a minimum number of components. In previous applications, standard comparator circuits were used, but required additional circuitry to prevent breakdown at higher voltages. 
     FIG. 1  illustrates a schematic diagram of an active power-on reset (POR) current comparator circuit. The POR current comparator circuit ( 100 ) includes start-up circuit  110 , I PTAT  generator  112 , comparator stage  114 , and gain stage  130 . I PTAT  generator  112  (i.e., current generator  112 ) includes current mirror circuit  120 , transistors Q 1  and Q 2 , and resistance circuit R 1 . Comparator stage  114  includes current mirror circuit  122 , transistors Q 3  and Q 4 , and resistance circuit N·R 1 . Current mirror circuit  120  includes transistors M 1  and M 2 . Current mirror circuit  122  includes transistors M 3  and M 4 . 
   Transistor M 1  includes a source that is coupled to an upper voltage supply (Vdd), a gate that is coupled to node N 1 , and a drain that is coupled to node N 2 . Transistor M 2  includes a source that is coupled to Vdd and a gate and drain that are coupled to node N 1 . Transistor M 3  includes a source that is coupled to Vdd and a gate and drain that are coupled to node N 5 . Transistor M 4  includes a source that is coupled to Vdd, a gate that is coupled to node N 5 , and a drain that is coupled to node N 7 . Transistor Q 1  includes an emitter that is coupled to a lower voltage supply (Vss) and a base and collector that are coupled to node N 2 . Transistor Q 2  includes an emitter that is coupled to node N 3 , a collector that is coupled to node N 1 , and base that is coupled to node N 2 . Transistor Q 3  includes an emitter that is coupled to node N 4 , a collector that is coupled to node N 5 , and a base that is coupled to node N 2 . Transistor Q 4  includes an emitter that is coupled to Vss, a collector that is coupled to node N 7 , and a base that is coupled to node N 2 . Resistance circuit R 1  is coupled between node N 3  and Vss. Resistance circuit N·R 1  is coupled between node N 4  and Vss. Start-up circuit  110  is coupled between node N 1  and Vss. Gain stage  130  is coupled between node N 7  and the output (POR). 
   In operation, the POR circuit current comparator circuit ( 100 ) produces a POR signal for use in resetting logic devices and mask reference startup signals during the initial power supply ramp of an integrated circuit. Actuation of the POR signal is dependent on the ratios between the currents flowing through the resistance circuits R 1  and N·R 1  (where N is a scaling factor). The current (I PTAT1 ) flowing through resistance circuit R 1  may be determined at steady state according to the following voltage loop equations:
 
− V   be1   +V   be2   +I   PTAT1   R   1 =0   (1) 
 
 V   be   =V   1   Ln ( I   c   /I   s )   (2) 
 
− V   1   Ln ( I   PTAT1   /I   s )+ V   1   Ln ( PTAT1   /AI   s )=− I   PTAT1   R   1    (3) 
 
               I   PTAT1     =         V   t     ⁢     Ln   ⁡     (   A   )           R   1               (   4   )             
 
wherein V be  corresponds to the base-emitter voltage of the corresponding transistor, V 1  corresponds to the threshold voltage, and A corresponds to the ratio between emitter areas for transistors Q 1  and Q 2  (Q 2 /Q 1 ).
 
   Correspondingly, the current (I PTAT2 ) flowing through resistance circuit N·R 1  may be expressed as follows: 
               I   PTAT2     =         V   t     ⁢     Ln   ⁡     (   A   )                   ⁢     N   ·     R   1                   (   5   )             
 
   By scaling N to be larger than 1, the POR signal actuates when the current flowing through resistance circuit N·R 1  is at approximately the level expressed in the following equation: 
               I   PTAT2     =       I   PTAT1     ⁡     (     1   N     )               (   6   )             
 
   As presented in the preceding equation, the scaling factor (N) may be selected such that the POR signal is actuated at a selectable point (i.e., time interval or supply voltage level) during startup. 
   As voltage increases on Vdd, start-up circuit  110  continues to hold the gate voltages for transistors M 1  and M 2  at a low level. Once a selected voltage on Vdd is reached, start-up circuit  110  releases the gate voltages for transistors M 1  and M 2 , activating I PTAT  generator  112 . As start-up circuit  110  disengages, low level currents are flowing throughout the entire circuit ( 100 ), while competing currents will be flowing through transistors M 4  and Q 4 . Initially, the current (I PTAT2 ) through transistor Q 3  and resistance circuit N·R 1  is measurably higher than the current flowing through Q 4 . In one example, the emitter area for transistor Q 1  corresponds to 1X, transistor Q 2  to AX, transistor Q 3  to AX, and transistor Q 4  to 1X. The difference in emitter area between transistor Q 3  and transistor Q 4 , results in a V be  for transistor Q 3  that is less than the V be  for transistor Q 4 . The lower V be  for transistor Q 3  results in a small current (I PTAT2 ) flowing through resistance circuit N·R 1 , which is larger than the corresponding current flow in transistor Q 4 . This current (I PTAT2 ) is mirrored by current mirror  122 , to flow through transistor M 4 . Accordingly, the current through transistor M 4  is also measurably higher than the current through transistor Q 4 , pulling the POR signal to a high logic level. As the current I PTAT2  begins to ramp up, the current through transistor Q 4  increases. At a selected bias current level, the current flowing through transistor Q 4  surpasses the current flowing through Q 3  and M 4 , pulling the POR signal to a low logic level. During a start-up cycle, the POR is initially pulled high, preventing instability of subsequent circuits (not shown), and then the POR circuit is pulled low, allowing subsequent circuitry to initiate at an acceptable bias current. The POR circuit remains low for the remainder of the operational range of the POR current comparator circuit ( 100 ). 
   In another embodiment, transistors Q 3  and Q 2  are not matched in size as described above. Instead, transistor Q 3  may be made a 1X device, while proportionally reducing the size of resistance circuit N·R 1  (e.g., by 1/A) and transistor circuit Q 4  (e.g., by 1/A). 
   In yet another embodiment, a transistor (not shown) is included to source more current into transistor Q 4 . When the POR signal is pulled to a low logic level, transistor Q 4  saturates, resulting in base current injection back into I PTAT  generator  112 . This injection of base current may result in errors of regulation for I PTAT  generator  112 . An additional transistor sourcing more current into transistor Q 4  prevents transistor Q 4  from reaching saturation. 
     FIG. 2  illustrates a schematic diagram of another active power-on reset (POR) current comparator circuit. The POR current comparator circuit ( 200 ) includes I PTAT  generator  212 , comparator stage  214 , cascode bias circuit  224 , and gain stage  230 . I PTAT  generator  212  includes current mirror circuit  220 , transistors M 9  and M 10 , and resistance circuit R 1 . Comparator stage  214  includes current mirror circuit  222 , transistors M 11  and M 12 , and resistance circuit N·R 1 . Current mirror circuit  220  includes transistors M 1 , M 2 , M 3 , and M 4 . Current mirror circuit  222  includes transistors M 5 , M 6 , M 7 , and M 8 . Gain stage  230  includes transistors Qx and Mx, and resistance circuit Rx. 
   Transistor M 1  includes a source that is coupled to an upper voltage supply (Vdd), a gate that is coupled to node N 1 , and a drain that is coupled to node N 2 . Transistor M 2  includes a source that is coupled to Vdd and a gate and drain that are coupled to node N 1 . Transistor M 3  includes a source that is coupled to node N 2 , a gate that is coupled to node N 3 , and drain that is coupled to node N 5 . Transistor M 4  includes a source that is coupled to node N 1 , a gate that is coupled to node N 3 , and a drain that is coupled to node N 4 . Transistor M 5  includes a source that is coupled to Vdd and a gate and drain that are coupled to node N 7 . Transistor M 6  includes a source that is coupled to Vdd, a gate that is coupled to node N 7 , and a drain that is coupled to node N 8 . Transistor M 7  includes a source that is coupled to node N 7 , a gate that is coupled to node N 9 , and drain that is coupled to node N 10 . Transistor M 8  includes a source that is coupled to node N 8 , a gate that is coupled to node N 9 , and a drain that is coupled to node N 12 . Transistor M 9  includes a source that is coupled to a lower voltage supply (Vss) and a drain and gate that are coupled to node N 5 . Transistor M 10  includes a source that is coupled to node N 6 , a drain that is coupled to node N 4 , and gate that is coupled to node N 5 . Transistor M 11  includes a source that is coupled to node N 11 , a drain that is coupled to node N 10 , and a gate that is coupled to node N 5 . Transistor M 12  includes a source that is coupled to Vss, a drain that is coupled to node N 12 , and a gate that is coupled to node N 5 . Resistance circuit R 1  is coupled between node N 6  and Vss. Resistance circuit N·R 1  is coupled between node N 11  and Vss. Cascode bias circuit  224  is coupled between node N 3  and node N 9 . 
   In gain stage  230 , transistor Qx includes a base and collector that are coupled to node N 12 , and an emitter that is coupled to node N 13 . Transistor Mx includes a source that is coupled to node N 13 , a gate that is coupled to node N 12 , and a drain that is coupled to node N 14 . Resistance circuit Rx is coupled between node N 14  and Vss. 
   In operation, POR current comparator circuit  200  operates similarly to POR current comparator circuit  100  shown in FIG.  1 . In the present embodiment, the BJT transistor (Q 1 -Q 4 ) shown in  FIG. 1  have been replaced by threshold FET transistors (M 9 -M 12 ). In addition, different current mirrors ( 220 ,  222 ) are used in place of the current mirrors ( 120 ,  122 ) shown in FIG.  1 . Current mirrors  220  and  222  are cascoded current mirrors that utilize an external cascode bias circuit ( 224 ). Also, gain stage  230  illustrates an exemplary gain stage for use with the present invention. In other embodiments, other gain stages may be utilized (e.g., the gain stage shown in FIG.  3 ), or the gain stage may be eliminated from the circuit. 
   Gain stage  230  includes a diode connected NPN transistor (Qx), a PMOS device (Mx), and a resistance circuit (Rx) to provide an inverting gain stage for the output of the POR signal. Transistor Qx is used to protect transistor Mx from an over-voltage that may occur at the voltage supply (Vdd). In an over-voltage condition does occur, transistor Qx prevents the gate of transistor Mx from increasing too high. In other embodiments, resistance circuit Rx may be replaced with a current source or diode connected circuit. 
     FIG. 3  illustrates a schematic diagram of a further active power-on reset (POR) current comparator circuit, in accordance with the present invention. The POR current comparator circuit ( 300 ) includes I PTAT  generator  312 , comparator stage  314 , and gain stage  230 . I PTAT  generator  312  includes current mirror circuit  320 , transistors Q 1  and Q 2 , and resistance circuit R 1 . Comparator stage  314  includes current mirror circuit  322 , transistors Q 3  and Q 4 , and resistance circuit N·R 1 . Current mirror circuit  320  includes transistors M 1 , M 2 , M 3 , and M 4 . Current mirror circuit  322  includes transistors M 5 , M 6 , M 7 , and M 8 . Gain stage  330  includes inverter circuits INV 1  and INV 2 . 
   Transistor M 1  includes a source that is coupled to a lower voltage supply (Vss), a gate that is coupled to node N 1 , and a drain that is coupled to node N 2 . Transistor M 2  includes a source that is coupled to Vss and a gate and drain that are coupled to node N 1 . Transistor M 3  includes a drain and gate that are coupled to node N 2 , and a source that is coupled to node N 4 . Transistor M 4  includes a drain that is coupled to node N 1 , a gate that is coupled to node N 2 , and a source that is coupled to node N 3 . Transistor M 5  includes a source that is coupled to Vss, and a gate and drain that are coupled to node N 6 . Transistor M 6  includes a source that is coupled to Vss, a gate that is coupled to node N 6 , and a drain that is coupled to node N 7 . Transistor M 7  includes a drain that is coupled to node N 6 , a gate that is coupled to node N 2 , and source that is coupled to node N 9 . Transistor M 8  includes a drain that is coupled to node N 7 , a gate that is coupled to node N 2 , and a source that is coupled to node N 11 . Transistor Q 1  includes an emitter that is coupled to an upper voltage supply (Vdd) and a base and collector that are coupled to node N 4 . Transistor Q 1  includes an emitter that is coupled to node N 5 , a collector that is coupled to node N 3 , and base that is coupled to node N 4 . Transistor Q 3  includes an emitter that is coupled to node N 10 , a collector that is coupled to node N 9 , and a base that is coupled to node N 4 . Transistor Q 4  includes an emitter that is coupled to Vss, a collector that is coupled to node N 11 , and a base that is coupled to node N 4 . Resistance circuit R 1  is coupled between node N 5  and Vss. Resistance circuit N·R 1  is coupled between node N 10  and Vss. 
   In gain stage  330 , inverter circuit INV 1  is coupled between node N 11  and node N 12 . Inverter circuit INV 2  is coupled between node N 12  and the output (POR). 
   In operation, POR current comparator circuit  300  operates similarly to the POR current comparator circuits ( 100 ,  200 ) shown in  FIGS. 1 and 2 . In the present embodiment, the NPN BJT transistors (Q 1 -Q 4 ) shown in  FIG. 1  have been replaced by PNP BJT transistors (Q 1 -Q 4 ). In addition, different current mirrors ( 320 ,  322 ) are used in place of the current mirrors ( 120 ,  122 ) shown in FIG.  1 . Current mirrors  320  and  322  are self-biased cascoded current mirrors. Also, gain stage  330  illustrates another exemplary gain stage for use with the present invention. Gain stage  330  includes two inverter circuits INV 1  and INV 2 . The inverter circuits (INV 1 , INV 2 ) serve to clean up and provide gain to the POR signal. Two inverter circuits are illustrated, however, in other embodiments, any number of inverter circuits that provide the desired POR signal may be used. 
   In the above FIGS. ( 1 - 3 ), the circuit is shown as including a lower supply voltage (Vss). Vss is interchangeable with a ground connection and should not be construed as a limitation of the invention. In addition, the start-up circuit ( 110 ) shown in  FIG. 1  may be used in  FIG. 2 ,  FIG. 3 , and further embodiments without departing from the scope of the invention. 
   The above specification, examples and data provide a complete description of the manufacture, use, and composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention resides in the claims hereinafter appended.