Abstract:
A semiconductor memory device includes: a core region having a plurality of bank sets for outputting/storing a data in response to an inputted address, wherein each bank set includes one bank, one row address control unit and two column address control units; and a peripheral region having two pad groups, wherein two pad groups are respectively located at the opposite side of the core region.

Description:
FIELD OF INVENTION 
   The present invention relates to a semiconductor memory device; and, more particularly, to a semiconductor memory device capable of reducing difference in data access time by adjusting positioning of data output pads and address input pads in a semiconductor memory device. 
   DESCRIPTION OF PRIOR ART 
     FIG. 1  is a block diagram showing a conventional semiconductor memory device. 
   Referring to  FIG. 1 , the conventional semiconductor memory device includes a first to a fourth banks  10 - 40 , the banks having the respective row address controlling unit  11 - 41  and the respective column address controlling unit  12 - 42 . Further, there are included address input pads for receiving external addresses, a number of data input/output pads for input/outputting data, driving voltage input pads for receiving various driving voltages, and a first and a second input pad units  50 ,  60  for receiving various control signals, in either sides of the banks  10 - 40 . 
   The number of the input/output pads in the memory device depends on the number of the inputted address signals and the number of data that are input/outputted at a time. In  FIG. 1 , total 74 input/output pads are included. 
     FIG. 2  is a table showing input/output pads of a semiconductor memory device shown in  FIG. 1 . 
   Referring to the table shown in  FIG. 2 , the total  74  input/output pads includes 22 address input pads A 0 -A 21 , 16 data input/output pads  101 - 1016 , driving voltage input pads VCCQ, VBB, VSS, VCORE and the like for receiving various driving voltages, and control input pads /WE, CS1, CS2, /OE and the like for receiving control signals. 
     FIG. 3  is a block diagram showing a signal transfer path when data access occurs at a unit cell A in the third bank  30  of a semiconductor memory device shown in  FIG. 1 . 
   Referring to  FIG. 3 , in the memory device, in order to access the data stored at the unit cell A, an address signal that is inputted through the 41-st address input pad is applied to the row address controlling unit  31  corresponding to the third bank  30 , and an address signal that is inputted through the 20-th address input pad is applied to the column address controlling unit  32 . 
   In the memory device shown in  FIG. 3 , all the signal that are inputted through the 22 address input pads are applied to the row address controlling unit  31  and the column address controlling unit  32 , which decode them to select one unit cell. The 2 address input pads among the 22 address input pads correspond to the addresses A 20 , A 21  for selecting the bank, the 11 address input pads correspond to the row address signals A 9 -A 19 , and the remaining 9 address input pads correspond to the column address signals A 0 -A 8 . 
   In  FIG. 3 , there is shown an example in that the row address is inputted through the 20-th address input pad and the column address is inputted through the 41-st address input pad. 
   The row address controlling unit  31  and the column address controlling unit  32  select the unit cell A by decoding the inputted row address and the column address, respectively. Then, the data that is stored at the unit cell A is outputted outside through the 7-th data output pad. Here, data can be outputted outside through any one of the 16 data output pads than the exemplary 7-th data output pad. 
     FIG. 4  is a block diagram showing a signal transfer path when data access occurs at a unit cell B in the first bank  10  of a semiconductor memory device shown in  FIG. 1 . 
   Referring to  FIG. 4 , in order to access the data that is stored at the unit cell B, an address signal that is inputted through the 41-st address input pad is applied to the row address controlling unit  11  corresponding to the first bank  10 , and the address signal that is inputted through the 20-th address input pad is applied to the column address controlling unit  12 . 
   Then, the unit cell B in the first bank is selected and the data stored in the unit cell B is outputted outside through the 7-th data output pad. 
   As described above, in the memory device typically including 4 banks, the four banks are positioned at the corners, respectively. The row address controlling unit and the column address controlling unit are positioned at one side of the corresponding bank, respectively. 
   Further, each of the first input/output pad unit  50  and the second input/output pad unit  60  includes data input/output pads and address input pads together. 
   Accordingly, depending on the selected bank, data access time for which the address signal is decoded to select the unit cell and data is outputted from the selected unit cell can be significantly varied. 
   Since each of the first input/output pad unit  50  and the second input/output pad unit  60  includes data input/output pads and address input pads together and the distances between the address input pads and the banks are different from each other, path through which the inputted address signal is transferred is varied depending on the selected bank, i.e., decoding time for the address signal is varied depending on the selected bank. 
   Further, since the distance between the banks and the data input/output pads are significantly different from each other, the time for which data stored at the unit cell in the selected bank is outputted outside through the data output pad is varied with regard to the selected bank. 
   Due to data access time difference between the banks, high-speed data access is restricted so that the memory device cannot be operated at a high speed. 
   SUMMARY OF INVENTION 
   It is, therefore, an object of the present invention to provide a semiconductor memory device capable of having uniform data access time without regard to a data access bank. 
   In accordance with an aspect of the present invention, there is provided a semiconductor memory device including: a core region having a plurality of bank sets for outputting/storing a data in response to an inputted address, wherein each bank set includes one bank, one row address control unit and two column address control units; and a peripheral region having two pad groups, wherein two pad groups are respectively located at the opposite side of the core region. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a block diagram showing a conventional semiconductor memory device; 
       FIG. 2  is a table showing input/output pads of a semiconductor memory device shown in  FIG. 1 ; 
       FIG. 3  is a block diagram showing a signal transfer path when data access occurs in the third bank of a semiconductor memory device shown in  FIG. 1 ; 
       FIG. 4  is a block diagram showing a signal transfer path when data access occurs in the first bank of a semiconductor memory device shown in  FIG. 1 ; 
       FIG. 5  is a block diagram showing a semiconductor memory device in accordance with a preferred embodiment of the present invention; 
       FIG. 6  is a table showing input/output pads of a semiconductor memory device shown in  FIG. 5 ; 
       FIG. 7  is a block diagram showing a signal transfer path when data access occurs in the second bank of a semiconductor memory device shown in  FIG. 5 ; and 
       FIG. 8  is a block diagram showing a signal transfer path when data access occurs in the fourth bank of a semiconductor memory device shown in  FIG. 5 . 
   

   DETAILED DESCRIPTION OF INVENTION 
   Hereinafter, a semiconductor memory device in accordance with the present invention will be described in detail referring to the accompanying drawings. 
     FIG. 5  is a block diagram showing a semiconductor memory device in accordance with a preferred embodiment of the present invention. 
   Referring to  FIG. 5 , the semiconductor memory device of the present invention includes data input/output pads for inputting/outputting accessed data and address input pads for receiving address signals. The data input/output pads are included in a first input/output pad unit  500  positioned at one side of a memory core region  1000  having a first to a fourth banks  100 - 400 . The plurality of address input pads are included in a second input/output pad unit  600  positioned at the other side of the memory core region  1000 . 
   Here, the first input/output pad unit  500  may further include driving voltage input/output pads for receiving various driving voltages and control signal input/output pads in addition to the data input/output pad. The second input/output pad unit  600  may also further include the driving voltage input/output pads for receiving the various driving voltages and the control signal input/output pads in addition to the address input pads. 
   However, all the data input/output pads used for data input/output in the memory device of the present invention are positioned in the first input/output pad unit  500  while all the address input pads for address input are positioned in the second input/output pad unit  600 . 
   On the other hand, the memory core region  1000  includes the first to fourth banks  100 - 400  arranged in a row and each bank has a plurality of unit cells. 
   The first to fourth banks  100 - 400  have the respective row address controlling units  110 - 410 , which are arranged at the side in which the second input/output pad unit  600  having the plurality of the address input pads is arranged. Each of the row address controlling units  110 - 410  processes a row address that is inputted through the address input pads and selects one of a number of word-lines that are included in the corresponding bank. 
   Further, the memory core region  1000  includes, correspondingly to the bank  100 , a first column address controlling unit  120  for processing a column address that is inputted through the plurality of address input pads to access data in the unit cell X that is positioned in the left half region of the unit cells in the bank  100 , and a second column address controlling unit  130  for processing the column address that is inputted through the plurality of address input pads to access data in the unit cell Y that is positioned in the right half region of the unit cells in the bank  100 . Further, there are included first column address controlling units  220 ,  320 ,  420  and second column address controlling units  230 ,  330 ,  430  corresponding to the respective remaining banks  200 - 400 . 
     FIG. 6  is a table showing input/output pads of a semiconductor memory device shown in  FIG. 5 . 
   Referring to  FIG. 6 , there is shown an example for the address input pads and the data input/output pads according to pin numbers of the semiconductor memory device of the present invention. As shown, no address input pad is positioned in the first to 32-nd pads that are included at one side of the memory core region, but all the included are the data input/output pads. On the other hand, no data input/output pad is positioned in the 33-th to 72-th pads that are included at the other side of the memory core region, but all the included are the address input pads. 
     FIG. 7  is a block diagram showing a signal transfer path when data access occurs in the second bank  200  of a semiconductor memory device shown in  FIG. 5 . 
   Referring to  FIG. 7 , a row address that is inputted through the 41-st pad is applied to the row address controlling unit  210  corresponding to the second bank  200  and a column address that is inputted through the 58-th pad is applied to the second column address controlling unit  230  corresponding to the second bank  200  in order to select a unit cell C of the plurality of unit cells. As described above, in the memory device of the embodiment, the left half unit cells among the unit cells that are included in one bank are controlled with the first column address controlling unit, and the right half unit cells are controlled with the second column address controlling unit. Accordingly, since the unit cell C is positioned in the right half region of the first bank  100 , it is controlled with the second column address controlling unit  230 . 
   Then, data that is stored in the unit cell C is outputted outside through the 7-th data input/output pad via data transfer path. 
   Though each of one row address and one column address are shown as inputted to an address input pad, the row address and the column address are actually inputted to all the address input pads in the memory device to be inputted to the row address controlling unit and the column address controlling unit of the corresponding bank, which decodes them to select one unit cell. 
     FIG. 8  is a block diagram showing a signal transfer path when data access occurs in the fourth bank  400  of the semiconductor memory device shown in  FIG. 5 . 
   Referring to  FIG. 8 , a row address that is inputted through the 41-st pad is applied to the row address controlling unit  410  corresponding to the fourth bank  400  while a column address that is inputted through the 58-th pad is applied to the second column address controlling unit  430  corresponding to the fourth bank  400 , thereby the unit cell D positioned in the right half region of the fourth bank  400 . 
   As described above, in the memory device of the embodiment, by positioning all the address input pads in one side(33-th to 72-nd pads) of the memory core region  1000  and positioning all the data input/output pads in the other side(1-st to 32-nd pads) of the memory core region  1000 , the paths through which the row address and the column address are transferred to the corresponding row address controlling unit and the corresponding column address controlling unit, respectively, are substantially uniform without regard to the bank that accesses data. Further, the path through which the accessed data is transferred from the bank to the data input/output pad is substantially uniform without regard to the selected bank. 
   Accordingly, data access time for which the address signal is processed and data is outputted is uniform regardless the selected bank. 
   Further, in the memory device of the embodiment, by arranging the bank in a line, the distances from all the address input pads to the respective banks are substantially uniform and the distances from the respective banks to all the data input/output pads are substantially uniform. Accordingly, data access time can be maintained uniform regardless of the accessed bank. 
   Further, in the memory device of the embodiment, the unit cells that are positioned in the left half region of the bank are controlled with the first column address controlling unit that is positioned in the left side of the bank and the unit cells that are positioned in the right half region of the bank are controlled with the second column address controlling unit that is positioned in the right side of the bank so that data access time can be maintained uniform without regard to the position of the unit cell for which data is accessed within the bank. 
   As described above, with the memory device of the present invention, data access time can be maintained uniform regardless of the data accessed bank. 
   Further, by constructing the memory device as prescribed, the wiring from the respective address input pads to the respective banks and the wiring from the data input/output pads to the respective banks can be implemented in a simpler form than the conventional wiring, so as to reduce circuit area in layout, i.e., to improve integration of the memory device. 
   According to the present invention, a memory device having a number of banks can maintain uniform data-access time without regard to data access bank. 
   The present application contains subject matter related to Korean patent application No. 2003-98565, filed in the Korean Patent Office on Dec. 29, 2003, the entire contents of which being incorporated herein by reference. 
   While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.