Abstract:
Inverter power supply control circuitry that protects power supply components from relatively quick-changing over-current conditions and that provides regulation of the power supply&#39;s output current upon relatively slow-changing load conditions.

Description:
BACKGROUND OF THE INVENTION 
     In the prior art it is known to provide regulated DC power to a load using an inverter power supply--see the publication &#34;Power Supplies for Computers and Peripherals,&#34; S. Davis, Computer Design, July, 1972, Pages 55 through 65. Generally, a filtered DC input voltage is inverted to a bi-directional DC signal that is coupled to a center tap of an input winding of an output or coupling transformer via switching transistors. Control circuitry is coupled to the output winding of the coupling transformer to regulate the output voltage across the load. Additionally, current sensing circuitry on the output side of the coupling transformer may be utilized to provide overload or short circuit protection for variations in loading--see the publication &#34;Here Are More Protective Circuits,&#34; A. Annunziato, Electronic Design 10, May 13, 1971, Pages 64 through 67, with particular reference to FIG. 12. However, it is desirable that such inverter power supplies include both fast-acting and slow-acting reactions to fast-changing and slow-changing variations in loading. 
     SUMMARY OF THE INVENTION 
     In the present invention, a variable-amplitude, pulse-width-modulator (PWM) current signal from an inverter power supply&#39;s switching transistors is sampled by a transformer-coupled current detector that generates a corresponding sample voltage v s  level. This sample voltage v s  is coupled to a slow-acting current limiting circuit and to a voltage regulator. The voltage regulator is referenced to a feedback voltage v fb , from the power supply&#39;s load circuit generating a control voltage v c . The control voltage v c  is, in turn, coupled back to the PWM that controls the duty cycle of the switching transistors and, in turn, the duty cycle of the PWM current signal. Slow changes in the feedback voltage v fb  or the sample voltage v s  cause appropriate slow changes in the control voltage v c , which maintains, via a corresponding change in the duty cycle of the switching transistors, a regulated output voltage at the power supply&#39;s load. A fast change in the sample voltage v s  is detected by a fast-acting current limiting circuit to cause a fast change in the control voltage v c  and a corresponding fast change in the duty cycle of the PWM current signal and a corresponding change in the regulated output voltage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a portion of an inverter power supply incorporating the present invention. 
     FIG. 2 is a schematic illustration of the control circuitry of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     With particular reference to FIG. 1 there is illustrated a portion of an inverter power supply in which the control circuitry 10 of the present invention is incorporated. A high voltage, unregulated DC voltage V IN  is coupled to the primary winding of sampling transformer T 1  and is then coupled to the center tap of the primary winding of output or coupling transformer T 2 . The end terminals of the primary winding of output transformer T 2  are, in turn, coupled to switching transistors Q S1  and Q S2 . Switching transistors Q S1  and Q S2 , which are controlled by the pulse-width-modulator (PWM) 12, couple a pulse width modulated current signal to the secondary winding of output transformer T 2 . The output circuitry 14 samples the output current flowing through the load 16 providing a feedback voltage v fb . This feedback voltage v fb  is coupled to control circuitry 10, which is coupled to the secondary winding of sampling transformer T 1 , and which, in turn, generates a control voltage v c . Control voltage v c  is, in turn, coupled to the PWM 12 for controlling the duty cycle or pulse width of the switching transistors Q S1  and Q S2  and, in turn, the load or output voltage V OUT . The present invention is directed toward the control circuitry 10. 
     With particular reference to FIG. 2 there is presented a schematic illustration of the control circuitry 10 of the present invention. A variable-amplitude, variable duty cycle current signal i d  is sampled by a transformer-coupled current detector 20 that generates a corresponding sample voltage v s  level. This sample voltage v s  is representative of the power supply&#39;s output current for steady state operation. This sample voltage v s  is coupled to a slow-acting current limiting circuit 22 and to a voltage regulator 24. The voltage regulator 24 is referenced to a fixed-level reference voltage v r2  and to a variable feedback voltage v fb , from, e.g., the power supply&#39;s output circuitry 14, for generating a control voltage v c . The control voltage v c  is, in turn, coupled back to the PWM 12 that controls the duty cycle of the switching transistors Q S1  and Q S2  and, in turn, the duty cycle of the PWM current signal i s  =i s1  +i s2  that flows through the primary winding of the output transformer T 2 . Slow changes in the feedback voltage v fb  or the sample voltage v s  cause appropriate slow changes in the control voltage v c , which maintains, via a corresponding change in the duty cycle of the switching transistors Q S1  and Q S2 , a regulated output voltage V OUT  at the power supply&#39;s load 16. A fast change in the sample voltage v s  is detected by a fast-acting current limiting circuit 26 to cause a fast change in the control voltage v c  and a corresponding fast change in the duty cycle of the PWM current signal i s  and a corresponding change in the regulated output voltage V OUT . 
     Current detector 20 is comprised of a current transformer T 1 , rectifying diode CR 1  and resistor R 1 . The current signal i d , which flows through the primary winding of current transformer T 1 , is converted to a sample voltage v s  across resistor R 1 , which is, in turn, coupled at node N 0  to slow-acting current limiter 22 and to fast-acting current limiter 26. 
     Slow-acting current limiter 22 is comprised of: (1) a peak detector including diode CR 2 , resistor R 2  and capacitor C 1  that at node N 1  converts the pulse sample voltage v s  to an equivalent DC voltage v i  level; (2) a summing node N 1  which compares the voltage v i  to a fixed or constant level reference voltage v r1  generating an error voltage v e1  ; and (3) an error amplifier E c  which generates the amplified error voltage v ae1  which, in turn, couples the amplified error voltage v ae1  to voltage regulator 24 via diode CR 3 . 
     Voltage regulator 24 is comprised of: (1) a summing node N 2  which generates an error voltage v e2  from a fixed or constant level reference voltage v r2 , amplified error voltage v ae1  and a variable feedback voltage v fb  from, e.g., output circuitry 14; (2) error amplifier E v  which generates the amplified error voltage v ae2  ; and, (3) rectifying diode CR 4  which couples the rectified amplified error voltage v ae2  to node N 4  which is coupled to a fixed or constant level reference voltage E 1  by resistor R 3 . 
     Fast-acting current limiter 26 is comprised of zener diode CR 5 , rectifier diode CR 6 , NPN transistor Q 1 , resistors R 4  and R 5 , and capacitor C 2 . Whenever the sample voltage v s  at node N 0  exceeds the zener voltage of zener diode CR 5  and the base-emitter voltage drop of transistor Q 1 , transistor Q 1  is switched ON discharging capacitor C 2  to ground therethrough. This forward biases rectifier diode CR 6  causing control voltage v c  at node N 4  to quickly drop toward ground through transistor Q 1 . The decreasing control voltage v c  at PWM 12 decreases the duty cycle of the switching transistors Q S1  and Q S2  forcing the PWM current signal i s  to a lower safe level. Note that in the configuration shown, an increase in the control voltage v c  will provide a corresponding increase in the duty cycle of the switching transistors Q S1  and Q S2 .