Abstract:
A time base correction apparatus comprising: a delay means (10) for providing a first signal (E3) as an input signal (E1) delay by a given time in accordance with a frequency of a clock signal (E2); a comparator (16) which compares a signal component (E4) contained in the first signal (E3) with a given comparison signal (E5) thereby to produce a second signal (E7) with a level corresponding to a phase difference between the signal component (E4) and the given comparison signal (E5); a VCO (12) for producing the clock signal (E2) depending on the level of the second signal (E7); and a compensator (20) which provides an output signal (E8) obtained by compensating variation components of the first signal (E3) so that the output signal (E8) exactly corresponds to the input signal (E1), depending on the first signal (E3) and the second signal (E7).

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to a time base correction apparatus using a variable signal delay device such as a CCD (charge coupled device). 
     A reproduced video signal obtained from recording/playback apparatus such as a VTR (video tape recorder) usually contains jitter-drift components. For correcting the jitter-drift components, a time base correction apparatus using a variable delay device such as a CCD (charge coupled device) is considered to be effective. As one of those apparatuses, there is a single delay apparatus which is disclosed in Japanese Patent Public Disclosure No. 52349/77. This prior art delay apparatus uses a signal delay element such as a shift register, a BBD or a CCD for effecting the time base correction. When the CCD, for example, is used for the signal delay element, the time base correction is performed through the control of a delay time by changing a clock frequency for transferring an input signal of the CCD. In the time base correction apparatus based on such a time correction idea, the signal transfer efficiency is degraded as the transfer clock frequency becomes high. In other words, a delayed output signal level of the CCD is reduced as the transfer clock frequency becomes higher. Additionally, the prior time base correction apparatus has a disadvantage that a DC level and an amplitude of the CCD output signal vary with a change of the transfer clock frequency caused by the time-delay control. Thus, the apparatus is effective for the correction of the jitter-drift components attendant with a time or phase variation, but is ineffective for the correction of the DC level and amplitude variations. This means that the amplitude and the DC component of the CCD output signal may vary in synchronism with the period of jitter-drift. When the time base correction apparatus is applied to a VTR, for example, a video output signal applied from the VTR to a monitor TV accordingly varies to possibly cause flicker noise to appear on a CRT screen. 
     SUMMARY OF THE INVENTION 
     Accordingly, an object of the present invention is to provide a time base correction apparatus in which a corrected signal component is not influenced by the correcting operation for the jitter-drift components. 
     To achieve the above object, there is provided a time base correction apparatus comprising: a delay means for providing a first signal as an input signal delayed by a given time in accordance with a frequency of a clock signal; a comparator means connected to the delay means which compares a specific signal component contained in the first signal with a given comparison signal thereby to produce a second signal with a level corresponding to a phase difference between the signal component and the given comparison signal; a generator means connected to the delay means and the comparator means for producing the clock signal depending on a level of the second signal; and a compensation means connected to the delay means and the comparator means, which provides an output signal obtained by compensating variation components of the first signal so that the output signal exactly corresponds to the input signal. 
     The time base correction apparatus with such a circuit arrangement can correct a time base variation caused by the jitter-drift and a variation of the output signal due to the correction of the jitter-drift as well. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of an embodiment of a time base correction apparatus according to the present invention; 
     FIGS. 2A and 2B illustrate waveforms of signals E4 and E5 shown in FIG. 1; 
     FIG. 3A is a graphical representation of a relation between a frequency of a signal E2 shown in FIG. 1 and a level (DC component) of a signal E3; 
     FIG. 3B is a graphical representation of a relation between a frequency of the signal E2 shown in FIG. 1 and a level (amplitude) of the signal E3; 
     FIG. 4 is a circuit diagram of a detailed compensating circuit shown in FIG. 1; 
     FIGS. 5A to 5C are a set of waveforms of the signals E3, E7 and E8; 
     FIG. 6 is a circuit diagram of another detailed compensating circuit; 
     FIGS. 7A to 7C show a set of waveforms of the signals E3, E7 and E8; 
     FIGS. 8 and 9 show modifications of the circuit 20A shown in FIG. 4; and 
     FIG. 10 shows a modification of the circuit 20B shown in FIG. 6. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows a circuit configuration of the time base correction apparatus according to the invention when it is used for correcting a jitter and a flicker of a VTR reproduced video signal. Time delay control for compensating the jitter is performed by a CCD 10. Into the CCD 10 a reproduced video signal E1 applied by a VTR is inputted. Also into the CCD 10 a transfer clock signal E2 is applied from a voltage controlled oscillator (VCO) 12. The video signal E1 is delayed by a given time delay according to a frequency of the clock signal E2. The signal E1 delayed by the CCD 10 is inputted, in the form of a first signal E3, into a synchronized signal separator 14. The separator 14 separates a specific signal component, i.e. a horizontal synchronizing signal E4 from the first signal E3. The synchronizing signal E4 is inputted into a phase comparator 16. Into the phase comparator 16, a comparison signal E5 is further inputted. The comparison signal E5 is produced by a sawtooth wave generator 18. The generator 18 is triggered by a reference signal E6 for the time correction to generate the signal E5. Namely, the comparison signal E5 has a given period in synchronism with the reference signal E6. 
     FIGS. 2A and 2B show a relation of the comparison signal E5 and the synchronizing signal E4. At a point P where the levels of the signals E5 and the E4 are coincident with each other, the comparator 16 produces a second signal E7. The second signal E7 has a signal level held at a level corresponding to the level-coincident point. The holding operation of the signal E7 is performed every period of the reference signal E6. The signal level of the second signal E7 corresponds to a phase difference between the signal E4 and the signal E5. The second signal E7 is inputted into the VCO 12. The VCO 12, according to the signal level of the second signal E7, changes the frequency of the transferring clock signal E2. 
     The circuit components 10 through 16 form a negative feedback loop. With a sufficient loop gain of the negative feedback loop, the first signal E3 constantly keeps a fixed phase difference with respect to the reference signal E6. However, if the loop gain is too high, a lock out phenomenon occurs at the moment of transients such as drop-out. Therefore, it is necessary to select an optimum negative feedback loop gain. By the above negative feedback operation, the jitter-drift component is removed from the first signal E3. However, the first signal E3 contains variations of the DC level and the amplitude which correspond to the frequency of the clock signal E2 or the signal level of the second signal E7. FIG. 3A is a graphical representation of a relation of the frequency of the clock signal E2 and the signal level (DC component) of the first signal E3. This graph shows that the higher the frequency of the transferring clock, i.e. the shorter the delay time in the CCD 10, the lower the DC level of the first signal E3. FIG. 3B is a graphical representation of a relation of the frequency of the clock signal E2 and the signal level of the first signal E3. This graph shows that the higher the frequency of the transferring clock, the lower the level or the amplitude of the first signal E3. The transfer clock frequency corresponds to the signal level of the second signal E7. Therefore, it is possible to cancel the reduction of the DC level or the amplitude of the first signal E3 by using the second signal E7. The canceling operation is made in a compensator 20. The first signal E3 and the second signal E7 are inputted into the compensator 20 where the DC variation or the amplitude variation of the first signal E3, that is, a flicker component, is canceled by the second signal E7. 
     FIG. 4 shows a detailed circuit 20A of the compensator 20. FIGS. 5A to 5C are waveforms of the signals E3 and E7, and the video output signal E8 outputted from the compensator 20. In FIG. 4, the first signal E3 with the DC level variation as shown in FIG. 5A, is applied to the base of an NPN transistor 20a, through a resistor R10. The collector of the transistor 20a is connected to positive power source +Vc and the emitter thereof is connected to a negative power source -Vs, through a resistor R14. The second signal E7, as shown in FIG. 5B, is applied to the base of the transistor 20a through an adjustable resistor R12. The signals E3 and E7 combined here are outputted from the emitter of the transistor 20a in the form of the compensated video signal E8. The first signal E3 and the second signal E7 have the same periods but the opposite phases. Therefore, by adjusting the resistor R12, a video signal E8 having only a small DC level variation, as shown in FIG. 5C, is obtainable. The signal E3, after being subjected to the jitter-compensation in the CCD 10, is further subjected to the flicker canceling, so that the output signal E8 does not include the jitter and the flicker. 
     FIG. 6 shows another detailed circuit 20B of the compensator 20. FIGS. 7A to 7C show waveforms of the video output signal E8 outputted from the compensator 20, and the signals E3 and E7. 
     In FIG. 6, the first signal E3 with the amplitude variation, as shown in FIG. 7A, is applied to the base of an NPN transistor 20 1  through a resistor R20. The emitter of the transistor 20 1 , together with the emitter of an NPN transistor 20 2 , is connected to the collector of an NPN transistor 20 3 . The second signal E7 as shown in FIG. 7B is supplied to the base of the transistor 20 3  through an adjustable resistor R22. The emitter of the transistor 20 3  is connected to the emitter of an NPN transistor 20 4  through a resistor R24. The emitter of the transistor 20 4  is connected to the collector of an NPN transistor 20 5 . The emitter of the transistor 20 5  is connected to a negative power source -Vs through a resistor R26. The base of the transistor 20 5  is grounded through a resistor R28 and connected to the power source -Vs, through a temperature-compensation diode D20 and a resistor R30. 
     The base of the transistor 20 4  is grounded through a resistor R32 and connected to the power source -Vs through a resistor R34. The collector of the transistor 20 4  is connected to emitters of NPN transistors 20 6  and 20 7 . The bases of the transistors 20 2 , 20 6  and 20 7  are grounded. The collectors of the transistors 20 1  and 20 7  are connected to a positive power source +Vc through a resistor R36. The collector of the transistor 20 2 , together with the collector of the transistor 20 6 , is connected to the power source +Vc through a resistor R38. From the collectors of the transistors 20 2  and 20 6 , the compensated video signal E8 is derived. 
     A level variation of the first signal E3 inputted into the base circuit of the transistor 20 1 , is caused by a frequency change of the transfer clock signal E2. Therefore, an envelope of the first signal E3 has same period as the second signal E7. Let us consider the positive envelope of the first signal E3 inputted into the base of the transistor 20 1 . The collector current of the transistor 20 2  decreases as a positive envelope level of the first signal E3 becomes higher. At this time, a positive half-period of the second signal E7 has been inputted into the base of the transistor 20 3 . Accordingly, a collector current of the transistor 20 3 , i.e. the sum of the collector currents of the transistors 20 1  and 20 2 , increases as a positive level of the second signal E7 increases. Consequently, the decrease of the collector current of transistor 20 2  is offset by the increase of the collector current of the transistor 20 3 . Conversely, when the envelope level of the signal E3 decreases and the collector current of the transistor 20 2  increases, the increase is offset by the decrease of the collector current of the transistor 20 3 . The same thing is true for a negative envelope of the first signal E3. As described above, by adjusting the adjustable resistor R22 properly, the video output signal E8 having only a small level variation, i.e. the flicker component, is obtainable, as shown in FIG. 7C. 
     Specifically, the input signal E1 which is jitter-compensated by the CCD 10 is further flicker-compensated by the compensator 20. In this way, the output signal E8 not including the jitter and the flicker is formed. Accordingly, by using the time base correction apparatus as shown in FIG. 1, the flicker inherent to the delay circuit using a CCD or the like may be removed, whereby a good quality picture reproduced is obtainable. 
     It is apparent to those persons skilled in the art that the present invention is not limited to the embodiments described thus far referring to accompanying drawings, and that the present invention may be variously changed or modified within the scope of the present invention. For example, when the DC component of the signal E3 and the signal E7 are in phase, the circuit 20A of FIG. 4 may be constructed by a differential amplifier circuit, as shown in FIG. 8. Alternatively, as shown in FIG. 9, it may also be constructed by the combination of an inverter and an adder. The circuit 20B of FIG. 6 may be constructed by, as shown in FIG. 10, an AGC or an ALC circuit having a variable impedance element such as an FET or CdS which circuit is controlled by the signal E7. Further, the CCD 10 of FIG. 1 may be replaced by another delay device such as a BBD, a shift register or the like.