Abstract:
A magnetic laminating structure and process for preventing substrate bowing include a first magnetic layer, at least one additional magnetic layer, and a dielectric spacer disposed between the first and at least one additional magnetic layers. The magnetic layers are characterized by defined tensile strength. To balance the tensile strength of the magnetic layer, the dielectric layer is selected to provide compressive strength so as to counteract the tendency of the wafer to bow as a consequence of the tensile strength imparted by the magnetic layer(s).

Description:
BACKGROUND 
       [0001]    The present invention relates to on-chip magnetic devices, and more specifically, to on-chip magnetic structures and methods for relieving stress and preventing wafer bowing. 
         [0002]    On-chip magnetic inductors/transformers are important passive elements with applications in the fields such as on-chip power converters and radio frequency (RF) integrated circuits. In order to achieve high energy density, magnetic core materials with thickness ranging several 100 nm to a few microns are often implemented. For example, in order to achieve the high energy storage required for power management, on-chip inductors typically require relatively thick magnetic yoke materials (several microns or more). 
         [0003]    There are two basic configurations, closed yoke and solenoid structure inductors. The closed yoke has copper wire with magnetic material wrapped around it and the solenoid inductor has magnetic material with copper wire wrapped around it. Both inductor types benefit by having very thick magnetic materials. One issue with depositing thicker materials is stress. Stress can cause wafers to bow and the bow can cause issues with lithography alignment and wafer chucking on processing tools. Stress for magnetic materials like CoFeB for example can be about 200 to about 400 megapascals (MPa). However, since the total magnetic film thickness requirement is greater than 1 micrometer (μm), the wafer bow can be considerably high. 
         [0004]    Ferrite materials that are often used in bulk inductors have to be processed at high temperature (&gt;800° C.), which is generally incompatible with complementary metal-oxide-semiconductor (CMOS) processing. Thus, a majority of magnetic materials integrated on-chip are magnetic metals such as nickel iron (Ni—Fe), cobalt iron (Co—Fe), cobalt iron boron (Co—Fe—B), cobalt zirconium titanium (Co—Zr—Ti) and the like. 
       SUMMARY 
       [0005]    Exemplary embodiments include inductor structures and methods for forming the inductor structures In one or more embodiments, the inductor structure includes a plurality of metal lines; and a laminated film stack comprising alternating layers of magnetic materials and insulating materials enclosing the metal lines, each magnetic material layer having a tensile stress and each insulation material layer having a compressive stress, wherein the compressive stress of the insulating material layer is in an amount effective to counterbalance the tensile stress of the magnetic material layer, wherein the layers of the magnetic materials have a cumulative thickness greater than 1 micron. 
         [0006]    In one or more embodiments, a method of forming an inductor structure includes depositing alternating magnetic and insulating layers on a processed substrate, wherein the magnetic layers have a tensile strength and the insulating layers have a compressive strength in an amount effective to counterbalance the tensile stress of the magnetic layers, wherein the magnetic layers have a cumulative thickness greater than 1 micron. 
         [0007]    In one or more embodiments, an inductor structure includes alternating magnetic and insulating layers on a processed substrate, wherein the magnetic layers have a tensile stress and the insulating layers have a compressive stress in an amount effective to counterbalance the tensile stress of the magnetic layers, wherein each of the insulating layers has a thickness greater than each of the magnetic layers, wherein the magnetic layers have a cumulative thickness greater than 1 micron. 
         [0008]    In one or more embodiments, a closed yoke inductor includes a laminated structure including alternating magnetic and insulating layers on a processed substrate, wherein the magnetic layers have a tensile strength and the insulating layers have a compressive strength in an amount effective to counterbalance the tensile stress of the magnetic layers, wherein the magnetic layers have a cumulative thickness greater than 1 micron; and a copper wire, wherein the laminated structure is wrapped around the laminated structure. 
         [0009]    In one or more embodiments, a solenoid inductor includes a laminated structure comprising alternating magnetic and insulating layers on a processed substrate, wherein the magnetic layers have a tensile strength and the insulating layers have a compressive strength in an amount effective to counterbalance the tensile stress of the magnetic layers, wherein the magnetic layers have a cumulative thickness greater than 1 micron; and a copper wire wrapped about the laminated structure. 
         [0010]    Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
           [0012]      FIG. 1  illustrates a cross section of an inductor structure in accordance with the present invention; and 
           [0013]      FIG. 2  depicts a process flow diagram in accordance with the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]    Disclosed herein are on chip magnetic inductor structures and methods for relieving stress as a function of the relatively thick magnetic layers utilized therein. The magnetic inductor structures and methods generally include formation of a stress balanced laminated magnetic stack structure and method for forming the laminated structure. An insulating layer is intermediate adjacent magnetic layers and has a compressive stress value effective to counterbalance the tensile stress value of the magnetic layers. Embodiments of a laminated magnetic material for inductors in integrated circuits and the method of manufacture thereof will be described. 
         [0015]    Turning now to  FIG. 1 , there is depicted a cross section of an exemplary inductor structure in accordance with the present invention. The inductor structure  10  generally includes a plurality of alternating magnetic layers  12  and insulating layers  14  disposed on a processed wafer  16 . Once the desired number of magnetic layers has been deposited, which typically provides a total magnetic layer thickness greater than 1 micron to several microns, a hard mask  18  is provided for additional processing to complete the device. For example, a resist image  20  can be lithographically formed to provide additional structures and connections. 
         [0016]    A “processed wafer” is herein defined as a wafer that has undergone semiconductor front end of line processing (FEOL) middle of the line processing (MOL), and back end of the line processing (BEOL), wherein the various desired devices and circuits have been formed. 
         [0017]    The typical FEOL processes include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The MOL is mainly gate contact formation, which is an increasingly challenging part of the whole fabrication flow, particularly for lithography patterning. The state-of-the-art semiconductor chips, the so called 14 nm node of Complementary Metal-Oxide-Semiconductor (CMOS) chips, in mass production features a second generation three dimensional (3D) FinFET, a metal one pitch of about 55 nm and copper (Cu)/low-k (and air-gap) interconnects. In the BEOL, the Cu/low-k interconnects are fabricated predominantly with a dual damascene process using plasma-enhanced CVD (PECVD) deposited interlayer dielectric (ILDs), PVD Cu barrier and electrochemically plated Cu wire materials. 
         [0018]    Each of the magnetic layers  14  in the laminate stack can have a thickness of about 100 nanometers or more and typically has a tensile stress value of about 50 to about 400 MPa. Tensile stress is a type of stress in which the two sections of material on either side of a stress plane tend to pull apart or elongate. In contrast, compressive stress is the reverse of tensile stress, wherein adjacent parts of the material tend to press against each other through a typical stress plane. 
         [0019]    The magnetic layers  14  can be deposited through vacuum deposition technologies (i.e., sputtering) or electrodepositing through an aqueous solution. Vacuum methods have the ability to deposit a large variety of magnetic materials and to easily produce laminated structures. However, they usually have low deposition rates, poor conformal coverage, and the derived magnetic films are difficult to pattern. Electroplating has been a standard technique for the deposition of thick metal films due to its high deposition rate, conformal coverage and low cost. 
         [0020]    The magnetic layers are not intended to be limited to any specific material and can include CoFe, CoFeB, CoZrTi, CoZrTa, CoZr, CoZrNb, CoZrMo, CoTi, CoNb, CoHf, CoW, FeCoN, FeCoAlN, CoP, FeCoP, CoPW, CoBW, CoPBW, FeTaN, FeCoBSi, FeNi, CoFeHfO, CoFeSiO, CoZrO, CoFeAlO, combinations thereof, or the like. Inductor core structures from these materials have generally been shown to have low eddy losses, high magnetic permeability, and high saturation flux density. 
         [0021]    The insulating layer  14  is not intended to be limited to any specific material and can include dielectric materials such as silicon dioxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiO x N y ), magnesium oxide (MgO), aluminum oxide (AlO 2 ), or the like. The bulk resistivity and the eddy current loss of the magnetic structure can be controlled by the insulating layer. The thickness of the insulating layer  16  should be minimal and is generally at a thickness effective to electrically isolate the magnetic layer upon which it is disposed from other magnetic layers in the film stack. Generally, the insulating layer has a thickness of about 1 nanometer to about 500 nanometers and is about one half or more of the magnetic layer thickness. 
         [0022]    The thickness and stress of the insulating layer  16  are optimized to counterbalance the wafer bowing caused by the presence of the tensile stress within the magnetic material. Thus, the insulating layer generally serves two primary purposes. One purpose is to isolate the magnetic material from each other in the stack and the other purpose is to counterbalance the unwanted wafer bow produced by the magnetic material. As noted above, the thickness of the insulating layer is generally about one half of the magnetic material. 
         [0023]    In one or more embodiments, the compressive stress of the insulating layer  16  at a particular thickness is within 20% of the tensile stress of the first magnetic layer at a particular thickness but of an opposite magnitude (i.e., negative versus positive stress). By way of example, if the magnetic layer has a tensile stress of 200 MPa at a given thickness, the insulating material is selected and configured to have a compressive stress of −160 MPa to −240 MPa. In one or more embodiments, the compressive stress of the insulating layer is at about half the thickness of the magnetic layer. In one or more other embodiments, the compressive stress of the insulating layer is within 10% of the tensile stress of the magnetic layer. By way of example, if the magnetic layer has a tensile stress of 200 MPa, the insulating material is selected and configured to have a compressive stress of −180 MPa to −220 MPa. In one or more embodiments, the compressive stress of the insulating layer is at about an equal magnitude to the first magnetic layer albeit compressive in nature. 
         [0024]    In one or more embodiments the thickness of the dielectric material is larger and with opposite sign stress compared to the magnetic material. The thickness of the dielectric material is used to balance the stress of the magnetic material. Thus for example if the magnetic material is about 400 MPa tensile and 100 nm in thickness then the dielectric material can be 200 MPa compressive and about 200 nm in thickness or 100 MPa compressive and about 400 nm in thickness or some other combination of stress and thickness to balance the stress in the magnetic material. In one or more other embodiments, the dielectric has higher magnitude and opposite sign stress compared to the magnetic material and would be thinner to counter balance the stress due to the magnetic material. In one or more other embodiments, the magnetic material is selected to have a compressive stress and the dielectric material is selected to have a tensile stress. In or more other embodiments, the magnetic material is selected to be neutral in terms of stress and the dielectric material is selected to be neutral in terms of stress as well. 
         [0025]    The insulating layer can be deposited using a deposition process, including, but not limited to, PVD, CVD, PECVD, or any combination thereof. The deposition parameters are known to control the stress within the insulating material, which for some materials can vary between tensile stress and compressive stress depending on the deposition parameters. For example, by changing the duty cycle of two different plasma excitation frequencies during deposition, the stress of silicon nitride deposited at 300° C. can be controlled in a wide range from compressive to tensile. The magnitude of stress as well as the type of stress, e.g., compressive or tensile, can be readily measured using known techniques, e.g., laser induced diffraction imaging methods. A conventional wafer bow measurement tool as is available in the industry can be used to measure film stress on a full 200 mm or 300 mm wafer. 
         [0026]    The inductor including the laminate structure as described can be integrated in a variety of devices. A non-limiting example of inductor integration is a transformer, which can include metal lines (conductors) formed parallel to each other by standard silicon processing techniques directed to forming metal features. The inductor structures can be formed about the parallel metal lines to form a closed magnetic circuit and to provide a large inductance and magnetic coupling among the metal lines. The inclusion of the magnetic material and the substantial or complete enclosure of the metal lines can increase the magnetic coupling between the metal lines and the inductor for a given size of the inductor. Inductors magnetic materials are also useful for RF and wireless circuits as well as power converters and EMI noise reduction. 
         [0027]    Referring now to  FIG. 2 , the process of forming the on chip magnetic inductor is shown and generally begins with depositing a magnetic layer onto the processed wafer as shown in step  100 , which after FEOL, MOL, and BEOL processing has a planar uppermost surface. The magnetic layer  12  is deposited onto the processed wafer  16 . 
         [0028]    In step  110 , an insulating layer  14  is then deposited onto the magnetic material layer  12 . The insulating layer has a compressive stress as described above. 
         [0029]    Next, as shown in step  120 , at least one additional magnetic layer  12  is deposited onto the insulating layer  14 . The at least one additional magnetic layer  12  can be the same or different relative to other magnetic layers within the laminate structure. Likewise, the tensile stress value can be the same or different. In addition, the thickness can be the same or different. By way of example, the film thickness can be about 100 nanometers and can have a tensile stress of about 50 to about 400 MPa. 
         [0030]    In step  130 , at least one additional insulating layer  14  is deposited onto the at least one additional magnetic layer  12 . The at least one additional insulating layer  14  can be the same or different relative to other insulating layers within the laminate structure but is selected to provide a compressive stress value as described above. The compressive stress value can be the same or different. In addition, the thickness can be the same or different. 
         [0031]    As shown in step  140 , the deposition of the at least one magnetic layer and the at least one additional dielectric layer can be repeated until the desired inductor stack is formed, which includes a magnetic film having a total thickness in excess of 1 micron to several microns. By utilizing a laminate structure including insulating layers having a compressive stress value between magnetic layers having a tensile stress value, wafer bowing can be prevented. 
         [0032]    Once the desired laminate structure is formed, the process can further include deposition of a hard mask onto the laminate structure followed by lithography to complete the device, wherein lithography can then be performed without alignment issues due to wafer bowing. 
         [0033]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one more other features, integers, steps, operations, element components, and/or groups thereof. 
         [0034]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated 
         [0035]    It should be apparent that there can be many variations to this diagram or the steps (or operations) described herein without departing from the spirit of the invention. For instance, the steps can be performed in a differing order or steps can be added, deleted or modified. All of these variations are considered a part of the claimed invention. 
         [0036]    While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, can make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.