Abstract:
Disclosed herein is a voltage regulator, and related method, for regulating a boost voltage generated by a boost circuit. In one embodiment, the voltage regulator includes a regulated voltage input operable to receive a regulated voltage derived from the boost voltage, a reference voltage input operable to receive a constant reference voltage, and an output node operable to provide a feedback signal to the boost circuit for controlling the generated boost voltage. In addition, the voltage regulator includes at least one transistor coupled to the regulated voltage input, the reference voltage input, and the output node, and operable to produce the feedback signal based on a comparison of the regulated voltage to the reference voltage. The voltage regulator still further includes a variable current source coupled to the output node and having one or more performance characteristics, where the variable current source is operable to generate a variable current at the output node to mitigate the affect of one or more performance characteristics of the at least one transistor based on the comparison and the feedback signal such that the boost circuit generates the boost voltage to be substantially constant.

Description:
TECHNICAL FIELD 
   Disclosed embodiments herein relate generally to the regulation of voltage in electrical circuits, and more particularly to a voltage regulator capable of generating a positive temperature coefficient for self-compensation, as well as related methods of regulating voltage. 
   BACKGROUND 
   In recent years, there continues to be dramatic density increases in integrated circuit technology for semiconductor chips. For example, the minimum feature size of lithography, such as the size of MOSFETs, has been reduced to one micrometer and below. In the fabrication of precision capacitors in conjunction with FET devices on the same chip at these reduced dimensions, it is increasingly difficult to maintain manufacturing parameters such that precise outputs from these devices are still available. 
   Many applications implemented on modern semiconductor chips require accurate voltages. A classic example is writeable memory, which requires the amplitude of the erase voltage to balance the write voltage of the writeable memory cells. If the erase voltage does not accurately match the write voltage, the memory cell will typically continue to store a binary “1” value, rather than the intended “0” binary value. To insure that the write voltage and erase voltage are generated properly, an on-chip voltage regulation circuit (e.g., a voltage regulator) is typically required. 
   Unfortunately, there are several on-chip and environmental effects that consistently counteract the regulation of on-chip voltages. Examples of these include temperature effects and manufacturing process variations. Relatively extreme variations in temperature, for example, the operating temperature of active devices within a voltage regulator, often affect the resistance, capacitance, voltage and current flow of on-chip components, and thus the overall semiconductor chip itself. In addition, process variations typically affect line spacings and the thickness of oxides, metals, and other layers of the semiconductor wafer, which consequently can affect on-chip voltages. This disclosure is directed to combating the problems caused by temperature fluctuations and process variations in voltage regulator circuitry. 
   BRIEF SUMMARY 
   Disclosed herein is a voltage regulator for regulating a boost voltage generated by a boost circuit to compensate an applied voltage of an electrical circuit. In one embodiment, the voltage regulator includes a regulated voltage input operable to receive a regulated voltage derived from the boost voltage, a reference voltage input operable to receive a constant reference voltage, and a control voltage output operable to provide a feedback output voltage to the boost circuit for controlling the generated boost voltage. In addition, the voltage regulator includes at least one active load element coupled to the regulated voltage input, the reference voltage input, and the control voltage output, and operable to produce the feedback output voltage based on a comparison of the regulated voltage to the reference voltage. In such an embodiment, the at least one active load element has one or more performance characteristics affecting the comparison and thus the feedback output voltage. The voltage regulator still further includes a variable current source coupled to the control voltage output and having one or more performance characteristics, where the variable current source is operable to generate a variable current at the control voltage output to mitigate the affect of the one or more performance characteristics of the at least one active load element on the comparison and the feedback output voltage such that the boost circuit generates the boost voltage to be substantially constant. 
   Also disclosed is a method of regulating a boost voltage generated by a boost circuit. In one embodiment, the method includes receiving a regulated voltage derived from the boost voltage and receiving a constant reference voltage. The method also includes producing a feedback output voltage based on a comparison of the regulated voltage to the reference voltage, where the producing is affected by one or more performance characteristics. Also the method includes providing the feedback output voltage to the boost circuit for controlling the generated boost voltage. Furthermore, in this embodiment, the method also includes generating a variable current associated with the feedback output voltage to mitigate the affect of the one or more performance characteristics on the comparison and the feedback output voltage such that the boost voltage is generated to be substantially constant, where the variable current is also affected by one or more performance characteristics. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the principles disclosure herein, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
     (1)  FIG. 1  illustrates a general block diagram of one embodiment of a conventional boosted voltage regulator; 
     (2)  FIG. 2  illustrates a graph of the change in regulator voltage generated by the boosted voltage regulator of  FIG. 1 , plotted as a function of temperature increase during operation; 
     (3)  FIGS. 3A and 3B  illustrate circuit diagrams of conventional positive boosted voltage regulators; 
     (4)  FIG. 4  illustrates a graph of a transfer curve for the conventional boosted voltage regulator circuits illustrated in  FIGS. 3A and 3B ; 
     (5)  FIG. 5  illustrates a circuit diagram of one embodiment of a positive boosted voltage regulator constructed according to the principles disclosed herein; 
     (6)  FIG. 6  illustrates a graph of the increase in regulated voltage, as a function of temperature increase, provided by the leakage current source of the disclosed boosted voltage regulator; 
     (7)  FIGS. 7A and 7B  illustrate circuit diagrams of conventional negative boosted voltage regulators; and 
     (8)  FIG. 8  illustrates a circuit diagram of one embodiment of a negative boosted voltage regulator constructed according to the principles disclosed herein. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   Referring initially to  FIG. 1 , illustrated is a general block diagram  100  of a typical environment of a conventional boosted voltage regulator  110 . As illustrated, such boosted voltage regulators  110  typically receive a regulated voltage (V REG ) as part of a feedback loop, and that regulated voltage V REG  is compared to a reference voltage (V REF ). An output of the boosted voltage regulator  110  (V OUT ) is then used to control a charge pump  120 , typically via a ring oscillator  130 , in order to generate the required boosted voltage (V BOOST ) for use by the desired application. While voltage regulator  110  illustrated in  FIG. 1  is discussed as a conventional regulator, the block diagram  100  may also provide an environment for a novel boosted voltage regulator constructed as set forth below. 
   Conventional boosted voltage regulator circuits  110  are widely utilized in many applications requiring a positive boosted voltage V BOOST  higher than the applied voltage of the overall circuit in the application. Alternatively, a negative boosted voltage below ground is provided, as the application varies. For example, when the boosted voltage V BOOST  reaches or goes over the regulated level, the regulator  110  will shut down the charge pump  120  so that the positive boosted voltage V BOOST  stops increasing. Conversely, when the boosted voltage V BOOST  is below the regulated level, the regulator  110  will allow the charge pump  120  to supply the necessary amount of boosted voltage V BOOST . 
   Unfortunately, the boosted voltage V BOOST  regulated by a conventional boosted voltage regulator will typically decrease as operating temperature for the circuit increases. To illustrate this point, attention is turned to  FIG. 2  where illustrated is a graph  200  of the change in regulator voltage (V REG ) used by the conventional boosted voltage regulator  110  shown in  FIG. 1 , plotted as a function of temperature increase during operation. In this embodiment, the regulator voltage V REG  used by the voltage regulator  110  decreases as the operating temperature of the regulator  110  increases from 25° C. to 125° C. Discussed in greater detail below is the effect of the increased temperature on the voltage driven active devices found in the regulator  110 . 
   Looking now at  FIGS. 3A and 3B , illustrated are circuit diagrams of conventional positive boosted voltage regulators  310 ,  320 . Looking individually at the circuits,  FIG. 3A  illustrates a positive boosted voltage regulator  310  incorporating a single voltage driven active device in the form of transistor device M 0 . Specifically, the device M 0  is a PMOS transistor device having the regulated voltage V REG  coupled to its source terminal and a reference voltage V REF  coupled to its gate. In addition, a constant reference current (I REF ) source S 0  is provided in the circuit  310 , which is coupled to the drain of transistor M 0 . With regard to  FIG. 3B , boosted voltage regulator  320  includes two transistor devices M 1 , M 2 , where both are PMOS devices. In this circuit  320 , the regulated voltage V REG  is coupled to the source of the second transistor M 2 , while its gate and drain terminals are both coupled to the source of the first transistor M 1 . The reference voltage V REF  is coupled to the gate of the first transistor M 1 , and a constant reference current I REF  source S 1  is coupled to its drain terminal. 
   For either voltage regulator  310 ,  320 , the voltage across the source and gate nodes (|V GS |) of the transistors M 0 , M 1 , M 2  is:
 
 V   GS   =V   REG   −V   REF ,  (1)
 
and a current through the transistors M 0 , M 1 , M 2  (Id) is provided. Therefore, during normal operation, the current source S 0 , S 1  draws a constant current I REF  through the transistors M 0 , M 1 , M 2  such that the absolute value of the voltage across the source and gate nodes (|V GS |) of the transistors M 0 , M 1 , M 2  is equal to the absolute value of the respective threshold voltage (|V TH |) for those transistors M 0 , M 1 , M 2 . Thus, in the first voltage regulator circuit  310 , when:
 
| V   REG   −V   REF   |&gt;|V   TH | (M0) ,  (2)
 
the drain current (Id) of M 0  will overcome the reference current I REF  causing the output V OUT  of the voltage regulator  310  to move from low to high. Similarly, in the second voltage regulator circuit  320 , when:
 
| V   REG   −V   REF   |&gt;|V   TH | (M1)   +|V   TH | (M2) ,  (3)
 
the drain current (Id) of the transistors M 1 , M 2  will overcome the reference current I REF  causing the output V OUT  of the voltage regulator  320  to move from low to high. For both circuits  310 ,  320 , when the output V OUT  goes high, the charge pump (see  FIG. 1 ) will be inhibited from generating the boost voltage V BOOST , thus decreasing the regulator voltage V REG  tapped from the V BOOST . Once the regulator voltage V REG  drops below a certain level, the drain current Id will also drop until it equals the constant reference current I REF , where the output V OUT  will then go low again.
 
   Therefore, the transfer point for the voltage regulator output V OUT  of circuit  310  is defined in equation (4):
 
 V   REG   =V   REF   +|V   TH |,  (4)
 
where V REF  is the reference voltage and V TH  is the threshold voltage of the transistor devices having a negative temperature coefficient. Consequently, the negative temperature coefficient of the transistors M 0 , M 1 , M 2  results in the regulator voltage V REG  decreasing, and thus an incorrect output voltage V OUT , as their temperature increases due to a drop in each transistor&#39;s threshold voltage V TH  (see  FIG. 4 ). The transfer point for the voltage regulator output V OUT  of circuit  320  is defined in equation (5):
 
 V   REG   =V   REF   +N*|V   TH |,  (5)
 
where V REF  and V TH  are as defined above for equation (1), and N is the number of PMOS devices in the voltage regulator circuit  320  in series between the output voltage node V OUT  and the regulator voltage V REG .
 
   Looking briefly at  FIG. 4 , illustrated is a graph  400  of a transfer curve for the conventional boosted voltage regulator circuits  310 ,  320  illustrated in  FIGS. 3A and 3B . As may be seen, as the operating temperature increases from 25° C. to 125° C., the output voltage V OUT  of the voltage regulators  310 ,  320  goes high at a lower regulated voltage V REG , since, as mentioned above, the regulated voltage V REG  decreases as temperature increases due to the drop in threshold voltage V TH . Stated another way, the drain current Id will increase at the same regulator voltage V REG  as the temperature increases because of the drop in threshold voltage V TH . As a result, the accuracy of the compensation provided by the voltage regulators  310 ,  320  diminishes with an increase in operating temperature. The graph  400  accordingly illustrates the problem of a negative temperature coefficient addressed by a circuit designed and operated as disclosed herein. 
   Turning now to  FIG. 5 , illustrated is a circuit diagram of one embodiment of a positive boosted voltage regulator  500  constructed according to the principles disclosed herein. Similar to the second conventional voltage regulator circuit  320  illustrated in  FIG. 3B , the disclosed voltage regulator  500  includes first and second transistor devices M 3 , M 4 , which are PMOS devices. The regulated voltage V REG  input to the voltage regulator  500  is coupled to the source of the second transistor M 4 , while its gate and drain terminals are both coupled to the source of the first transistor M 3 . Also, a constant reference voltage V REF  is coupled to the gate of the first transistor M 3 , while a constant reference current (I REF ) source S 2  is coupled to the drain of transistor M 3 . Also as before, the output voltage V OUT  of the voltage regulator  500  is found between the drain of the first transistor M 3  and the constant current source S 2 . These components of the voltage regulator  500  form a base circuit  510 . 
   The voltage regulator  500  of  FIG. 5  also includes third, fourth and fifth transistor devices M 5 , M 6 , M 7 . The third transistor M 5  is a PMOS device, while the fourth and fifth transistors M 6 , M 7  are NMOS devices, for a positive boost circuit. Specifically, the source and gate of the third transistor M 5  are coupled to a power supply voltage (V DD ), while the drain of the third transistor M 5  is coupled to the source of the fourth transistor M 6 . While the drain of the fourth transistor M 6  is coupled to ground, its gate is coupled to the gate of the fifth transistor M 7 . Finally, the source of the fifth transistor M 7  is coupled to the node where the output voltage V OUT  from the voltage regulator  500  is tapped (i.e., between the drain of the first transistor M 3  and the constant current source S 2 ), while the drain of the fifth transistor M 7  is coupled to ground. With these connections in mind, a discussion of the operation of the voltage regulator  500  follows. 
   As mentioned above, during the boosting of voltage at the output V OUT  of the voltage regulator  500 , the threshold voltage V TH  of the transistors M 3 , M 4  in the base circuit  510  decreases as temperature increases. This results in the threshold voltage V TH  being overcome at a lower regulator voltage V REG , which causes the drain current Id to increase too soon and make the output voltage V OUT  prematurely high. Accordingly, the disclosed voltage regulator  500  is configured to overcome the problems associated with threshold voltage V TH  decline at high temperatures, by incorporating this characteristic of MOSFET threshold voltage V TH  into a leakage current source  520  that provides a positive temperature coefficient to the base circuit  510 . 
   As illustrated in  FIG. 5 , to create a positive temperature coefficient for the voltage regulator  500 , the variable leakage current source  520  is created with the coupling of the third, fourth and fifth transistor devices M 5 , M 6 , M 7  in the manner described above. More specifically, this leakage current source  520  creates a variable leakage current (I p-leak ) at the drain of the original first transistor device M 3  (at the same place as the output voltage V OUT ). As a result, equation (5) (or even equation (4), if only one transistor device is used to create the output voltage V OUT ) may be modified to derive equation (6):
 
 V   REG   =V   REF   +N*|V   TH   |+ΔV ( I   p-leak ).  (6)
 
As before, V REF  and V TH  are as defined above, N is the number of PMOS devices that are placed in series between the output voltage node V OUT  and the regulator voltage V REG , and V(I p-leak ) is a positive temperature coefficient item created by the leakage current I p-leak  drawn by the leakage current source  520 . The ΔV(I p-leak ) is the cumulative threshold voltage V TH  difference across the N transistors based on their drain/source currents I DS  when the leakage current I p-leak  is drawn.
 
   During operation, the PMOS M 5  is biased at an OFF state because the gate is coupled to the power supply V DD ; thus, the gate-source voltage V GS  of PMOS M 5  is 0 Volts. As a result, the current I off  drawn from PMOS M 5  is an off current or a sub-threshold current or a sub-threshold leakage. However, the current I off  from PMOS M 5  rapidly increases as its temperature rises during operation. This current I off  then drains through NMOS M 6 . Transistors M 6  and M 7  are coupled together to form a current mirror. Therefore, as the current drained from PMOS M 5  through NMOS M 6  is magnified, the magnification is mirrored through NMOS M 7  to draw a current I p-leak . The ratio of magnification corresponds to the ratio of transistor size for NMOS M 7  over NMOS M 6 . 
   As illustrated, the leakage current I p-leak  is pulled from the drain of the first transistor M 3 , where the output voltage V OUT  is tapped. As mentioned above, when the current through PMOS M 3  overcomes the reference current I REF  (which remains constant), the output voltage V OUT  increases. Since the increasing temperature typically results in the drain current Id overcoming the reference I REF  current sooner than desired, because the decreased threshold voltage V TH  is overcome by a lower regulator voltage V REG , the leakage current I p-leak  compensates for the premature drain current Id so that the output voltage V OUT  does not increase as quickly. Since the amount of leakage current I p-leak  is proportional to the temperature increase (through PMOS M 5 ), when the drain current Id increases based on the threshold voltage V TH  degradation caused by increasing temperature, the leakage current I p-leak  proportionally increases based on that same increasing temperature. By proportionally compensating for this threshold voltage V TH  decline, the output voltage V OUT  is not allowed to go high until a higher regulator voltage V REG  is reached. As a result, the regulator voltage V REG  is allowed to reach substantially the same amount that would be required make the output V OUT  high if increasing temperature did not decrease the threshold voltage V TH  of NMOS M 3  and M 4  in the first place (i.e., before increased temperature degraded the threshold voltage V TH ). Looking briefly at  FIG. 6 , illustrated is a graph  600  of the increase in regulated voltage V REG , as a function of temperature increase, provided by the leakage current source  520  of the disclosed boosted voltage regulator. 
   In addition, with a voltage regulator circuit constructed according to the disclosed principles, the voltage expense of generating the leakage current I p-leak  by operating the leakage current source  520  as disclosed above is relatively low, especially in low temperature situations. A still further benefit of the disclosed voltage regulator circuit is that the same or similar compensation may be provided if the threshold voltage V TH  decline is caused by process variation when manufacturing the circuit. In this situation, as before, PMOS M 5  will have a current I off  leaking therethrough because of the same threshold voltage V TH  decline based on a process corner variation in all the MOSFETs in the regulator circuit. As a result, the leakage current I p-leak  generated by the leakage current source disclosed herein will equally compensate the decline in threshold voltage V TH  found in the base circuit MOSFETs in spite of manufacturing process variations. 
   Turning now to  FIGS. 7A and 7B , illustrated are circuit diagrams of conventional negative boosted voltage regulators  710 ,  720 . Looking individually at the circuits,  FIG. 7A  illustrates a negative boosted voltage regulator  710  incorporating a single voltage driven active device in the form of transistor device M 9 . Specifically, the transistor M 9  is an NMOS transistor device having the regulated voltage V REG  coupled to its drain terminal and a reference voltage V REF  coupled to its gate. In addition, a constant reference current (I REF ) source S 3  is provided in the circuit  710  and coupled to the source terminal of NMOS M 9 , and then to an applied power supply voltage V DD . In  FIG. 7B , the illustrated negative boosted voltage regulator  720  includes first and second transistor devices M 10 , M 11 , where both are NMOS devices. In this circuit  720 , the regulated voltage V REG  is coupled to the drain of the second NMOS M 11 , while its gate and source terminals are both coupled to the drain of the first NMOS M 10 . The reference voltage V REF  is coupled to the gate of the first transistor M 10 , and a constant reference current (I REF ) source S 4  is coupled to its source terminal, and then to an applied voltage V DD . 
   Similar to the conventional positive regulator circuits  310 ,  320 , for either negative voltage regulator  710 ,  720 , the current source S 3 , S 4  draws a constant current IREF through the transistors M 9 , M 10 , M 11  such that the absolute value of the voltage across the source and gates (|V GS |) of each transistor M 9 , M 10 , M 11  is almost equal to the absolute value of the respective threshold voltage (|V TH |) for those transistors M 9 , M 10 , M 11 . However, since the voltage regulators  710 ,  720  in  FIGS. 7   a  and  7 B are negative boost, the transfer point for the output voltage V OUT  of first circuit  710  is defined by equation (7):
 
 V   REG   =V   REF   −|V   TH |,  (7)
 
while the transfer point for the output voltage V OUT  of the second circuit  720  is defined by equation (8):
 
 V   REG   =V   REF   −N*|V   TH |.  (8)
 
As with the prior equations, V REF  is the reference voltage, V TH  is the threshold voltage of the transistor devices M 9 , M 10 , M 11 , and N is the number of transistor devices employed in the voltage regulator circuit  720 . Also as with conventional PMOS circuits, increased temperatures can degrade the threshold voltages V TH  of the NMOS devices, resulting in inaccurate regulation of the regulator voltage V REG  by altering the state of the output signal V OUT .
 
   Turning finally to  FIG. 8 , illustrated is a circuit diagram of one embodiment of a negative boosted voltage regulator  800  constructed according to the principles disclosed herein. Similar to the second conventional voltage regulator circuit  720  illustrated in  FIG. 7B , the disclosed voltage regulator  800  includes first and second transistor devices M 12 , M 13 , which are NMOS devices for use in a negative boost regulator. The regulated voltage V REG  input to the voltage regulator  800  is coupled to the drain of NMOS M 13 , while its gate and source terminals are both coupled to the source of NMOS M 12 . Also, a reference voltage V REF  is coupled to the gate of NMOS M 12 , while a constant reference current (I REF ) source S 5  is coupled to the source of NMOS M 12 . The output voltage V OUT  of the voltage regulator  800  is found between the source of NMOS M 12  and the constant current source S 5 . These components of the voltage regulator  800  form a base circuit  810 . 
   The voltage regulator  800  of  FIG. 8  also includes third, fourth and fifth transistor devices M 14 , M 15 , M 16 , where the third transistor M 14  is an NMOS device and the fourth and fifth transistors M 15 , M 16  are PMOS devices. Specifically, the drain and gate of NMOS M 14  are coupled to ground (V SS ), while the source of NMOS M 14  is coupled to the drain and gate of PMOS M 15 . Next, the source of PMOS M 15  is coupled to an applied operating voltage V DD , while its gate is coupled to the gate of PMOS M 16 . Finally, the drain of PMOS M 16  is coupled to the node where the output voltage V OUT  from the voltage regulator  800  is tapped, while the source on the PMOS M 16  is coupled to the applied voltage V DD . 
   In order to properly boost voltage at the output V OUT  in a negative boost application, and thus to create the positive temperature coefficient discussed above, a leakage current source  820  is created with the third, fourth and fifth transistor devices M 14 , M 15 , M 16 , and is coupled to the base circuit  810 . As this current begins to flow through NMOS M 14  it reaches PMOS M 15 , providing a magnification of the current. The magnified current is then mirrored by PMOS M 16  as leakage current I n-leak . In this negative boost application, the leakage current source  820  creates the leakage current I n-leak  and provides it to the base circuit  810  of the voltage regulator  800  at the source of NMOS M 12 , where the output voltage V OUT  is tapped, in order to compensate the constant reference current I REF  when needed, so as to prevent the output voltage V OUT  from changing states (low vs. high) prematurely because of increases in temperature (that cause the threshold voltages V TH  of NMOS M 12  and M 13  to decline). Equation (8) (or equation (7), in one transistor regulator circuits) may thus be derived into equation (9):
 
 V   REG   =V   REF   −N*|V   TH   |−ΔV ( I   n-leak ),  (9)
 
where V REF , N, and V TH  are as defined above, and V(I n-leak ) is the positive temperature coefficient item in the negative boost application that is created by the leakage current I n-leak  provided by the leakage current source  820 . The ΔV(I n-leak ) is the cumulative threshold voltage V TH  difference across the N transistors based on their drain/source currents I DS  when the leakage current I n-leak  is provided. Thus, with a voltage regulator based on the circuit  800  illustrated in  FIG. 8 , a positive temperature coefficient may also be generated in negative boost applications, while retaining all the benefits described above for positive boost applications.
 
   While various embodiments of voltage regulator circuits, and methods for regulating voltages, according to the principles disclosed herein have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the invention(s) should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with any claims and their equivalents issuing from this disclosure. Furthermore, the above advantages and features are provided in described embodiments, but shall not limit the application of such issued claims to processes and structures accomplishing any or all of the above advantages. 
   Additionally, the section headings herein are provided for consistency with the suggestions under 37 CFR 1.77 or otherwise to provide organizational cues. These headings shall not limit or characterize the invention(s) set out in any claims that may issue from this disclosure. Specifically and by way of example, although the headings refer to a “Technical Field,” such claims should not be limited by the language chosen under this heading to describe the so-called technical field. Further, a description of a technology in the “Background” is not to be construed as an admission that technology is prior art to any invention(s) in this disclosure. Neither is the “Brief Summary” to be considered as a characterization of the invention(s) set forth in issued claims. Furthermore, any reference in this disclosure to “invention” in the singular should not be used to argue that there is only a single point of novelty in this disclosure. Multiple inventions may be set forth according to the limitations of the multiple claims issuing from this disclosure, and such claims accordingly define the invention(s), and their equivalents, that are protected thereby. In all instances, the scope of such claims shall be considered on their own merits in light of this disclosure, but should not be constrained by the headings set forth herein.