Abstract:
An exemplary method for examining bonding resistance includes providing a first electronic component having a first and second reference pins. A second electronic component having a third and fourth reference pins is also provided. A first input voltage is applied to the first reference pin. A bias resistor connected between the third reference pin and ground is provided, with the third reference pin serving as an output for providing a first reference voltage. The first reference voltage is measured. Bonding resistance between the first reference pin and the third reference pin is evaluated according to the measured first reference voltage.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to methods for examining bonding resistance, and more particularly to a method typically used for examining bonding resistance between two integrated circuits of an electronic product such as a liquid crystal display (LCD). In this description, unless the context indicates otherwise, the term “bonding resistance” refers to electrical resistance where two or more electronic components are mechanically bonded together. 
       GENERAL BACKGROUND 
       [0002]    Presently, integrated circuits are widely used in various electronic products such as mobile phones, personal digital assistants, and liquid crystal displays. These kinds of electronic products usually need a lot of components to be electrically connected together. For example, in an LCD, the components can include integrated circuits (ICs), glass substrates, flexible printed circuits (FPCs), and printed circuit boards (PCBs), which are packaged together in the form of a module bonding structure. Generally, module bonding technologies for LCDs include chip on glass (COG) technology, tape automated bonding (TAB) technology, film on glass (FOG) technology, chip on board (COB) technology, and chip on film (COF) technology. A conductive bonding material for bonding two electronic components together, such as an anisotropic conductive film (ACF), is usually needed. 
         [0003]    Referring to  FIG. 5 , a typical module bonding structure  10  includes a first IC  11 , a second IC  12 , an FPC  13 , and a glass substrate  14 . The first IC  11  is bonded on the glass substrate  14  by COG technology. The second IC  12  is bonded on an end of the FPC  13  by COF technology. The other end of the FPC  13  is bonded on the glass substrate  14  by COG technology. 
         [0004]    Referring also to  FIG. 6 , this is essentially an abbreviated circuit diagram of the module bonding structure  10 . The glass substrate  14  includes a plurality of conductive lines (not shown) therein. The FPC  13  includes a plurality of metal wires (not shown). The first IC  11  includes a plurality of first pins A 1 ˜An (n is a natural number). The second IC  12  includes a plurality of second pins B 1 ˜Bn. The first pins A 1 ˜An correspond to the second pins B 1 ˜B 2  one-to-one. The first pins A 1 ˜An are electrically connected to the corresponding second pins B 1 ˜Bn via the conductive lines of the glass substrate  14  and the metal wires of the FPC  13 , respectively. Normally, a bonding resistance inevitably exists in a bonding area because of a resistance of the bonding material and the ICs. Taking the first pin A 1  and the second pin B 1  as an example, R 1  is a resistance between the first pin A 1  and the glass substrate  14 , R 2  is a combined resistance of the metal wire of the glass substrate  14  corresponding to the first pin A 1  plus the conductive line of the FPC  13  corresponding to the second pin B 1 , and R 3  is a resistance between the FPC  13  and the second pin B 1 . Thus, a bonding resistance R between the first pin A 1  and the second pin B 1  is equal to the sum of R 1 , R 2  and R 3 . 
         [0005]    In general, the bonding resistance R has a maximum tolerance value, in order to meet requirements of stable and reliable operation when the module bonding structure  10  is used in an electronic product such as an LCD. However, during the process of manufacturing the module bonding structure  10 , it is difficult to keep the bonding resistance R in a normal range below the maximum tolerance value. If the maximum tolerance value is exceeded, working signals of the module bonding structure  10  are liable to be adversely affected, and the module bonding structure  10  may not work accurately and stably. 
         [0006]    What is needed, therefore, is a method for examining bonding resistance that can help overcome the above-described deficiencies. 
       SUMMARY 
       [0007]    In one preferred embodiment, a method for examining a bonding resistance includes providing a first electronic component having a first and second reference pins. A second electronic component having a third and fourth reference pins is also provided. A first input voltage is applied to the first reference pin. A bias resistor connected between the third reference pin and ground is provided, with the third reference pin serving as an output for providing a first reference voltage. The first reference voltage is measured. Bonding resistance between the first reference pin and the third reference pin is evaluated according to the measured first reference voltage. 
         [0008]    Other aspects, novel features and advantages will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of at least one embodiment of the present invention. In the drawings, like reference numerals designate corresponding parts throughout various views, and all the views are schematic. 
           [0010]      FIG. 1  is a side-on view of an exemplary module bonding structure used in an examining method according to any of various embodiments of the present invention. 
           [0011]      FIG. 2  is a circuit diagram illustrating an examining method according to a first embodiment of the present invention, the examining method being applied to the module bonding structure of  FIG. 1 . 
           [0012]      FIG. 3  is a circuit diagram illustrating an examining method according to a second embodiment of the present invention, the examining method being applied to the module bonding structure of  FIG. 1 . 
           [0013]      FIG. 4  is a block diagram of a comparator used in any of various embodiments of the present invention. 
           [0014]      FIG. 5  is a side-on view of a conventional module bonding structure. 
           [0015]      FIG. 6  is essentially an abbreviated circuit diagram of the module bonding structure of  FIG. 5 . 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0016]    Reference will now be made to the drawings to describe preferred and exemplary embodiments in detail. 
         [0017]    Referring to  FIG. 1 , a module bonding structure  20  according to an exemplary embodiment of the present invention is shown. The module bonding structure  20  includes a first IC  21 , a second IC  23 , an FPC  25 , a PCB  24 , and a glass substrate  22 . 
         [0018]    The first IC  21  is bonded on a main portion of the glass substrate  22 . The second IC  23  is bonded on a main portion of the PCB  24 . One end portion of the FPC  25  is bonded on an end portion of the glass substrate  22 , and the other end portion of the FPC  25  is bonded on an end portion of the PCB  24 . 
         [0019]    Referring also to  FIG. 2 , this is a circuit diagram illustrating an examining method according to a first embodiment of the present invention, the examining method being applied to the module bonding structure  20 . The first IC  21  includes a plurality of first signal pins (not shown), a first reference pin  211 , and a second reference pin  212 . The second IC  23  includes a plurality of second signal pins (not shown) corresponding to the first signal pins, a third reference pin  231 , and a fourth reference pin  232 . The first and second reference pins  211 ,  212  correspond to the third and fourth reference pins  231 ,  232 , respectively. The first signal pins, the first reference pin  211 , and the second reference pin  212  are mutually insulated. The second signal pins, the third reference pin  231 , and the fourth reference pin  232  are mutually insulated. R 1  is a resistance between the first reference pin  211  and the glass substrate  22 . R 4  is a resistance between the second reference pin  212  and the glass substrate  22 . R 2  is a resistance between the glass substrate  22  and the PCB  24  corresponding to the first reference pin  211  (including a resistance between the glass substrate  22  and the FPC  25 , and a resistance between the FPC  25  and the PCB  24  corresponding to the first reference pin  211 ). R 5  is a resistance between the glass substrate  22  and the PCB  24  corresponding to the second reference pin  212  (including a resistance between the glass substrate  22  and the FPC  25  and a resistance between the FPC  25  and the PCB  24  corresponding to the second reference pin  212 ). R 3  is a resistance between the PCB  24  and the third reference pin  231 . R 6  is a resistance between the PCB  24  and the fourth reference pin  232 . Working signals of the module bonding structure  20  are transferred between the first signal pins and the corresponding second signal pins. A bonding resistance R between the third reference pin  231  and the fourth reference pin  232  is equal to the sum of R 1 , R 2 , R 3 , R 4 , R 5 , and R 6 . A maximum tolerance value of the bonding resistance R is defined as Rmax. 
         [0020]    When the bonding resistance R is examined, the third reference pin  231  has an input voltage V applied thereto. 
         [0021]    The first and second reference pins  211 ,  212  are connected to each other. 
         [0022]    The fourth reference pin  232  is connected to ground via a bias resistor Rin. The fourth reference pin  232  serves as an output for providing a reference voltage Vout. The reference voltage Vout is also a drop voltage of the bias resistor Rin. Thus, the third reference pin  231  is electrically connected to ground via R 3 , R 2 , R 1 , the first reference pin  211 , the second reference pin  212 , R 4 , R 5 , R 6 , and Rin, which together constitute a series branch. 
         [0023]    Then, the reference voltage Vout is measured from the fourth reference pin. 
         [0024]    A minimum value of the reference voltage Vout is calculated. The reference voltage Vout can also be calculated according to the following equations: 
         [0000]        V=V out+ I*R  ( I  represents a current of the series branch); 
         [0000]        V out= I*R in; 
         [0000]      Accordingly,  V out=( V*R in)/( R+R in). 
       Because the bonding resistance R is not more than the Rmax (R≦Rmax), then the theoretical reference voltage Vout=(V*Rin)/(R+Rin)≧(V*Rin)/(Rmax+Rin). If one defines a minimum value of the reference voltage Vout as Vmin, then Vmin=(V*Rin)/(Rmax+Rin). 
       [0025]    The bonding resistance R is examined. When the reference voltage Vout as measured is less than Vmin, the bonding resistance R is greater than Rmax. 
         [0026]    Thus, once Rin and Rmax are confirmed, the bonding resistance R can be examined by measuring the reference voltage Vout. If the measured reference voltage Vout is less than Vmin, the bonding resistance is abnormal. If the measured reference voltage Vout is equal to or greater than Vmin, the bonding resistance is normal. 
         [0027]    Referring to  FIG. 3 , this is a circuit diagram illustrating an examining method according to a second embodiment of the present invention, the examining method being applied to the module bonding structure  20 . 
         [0028]    The first reference pin  211  is connected to a first input voltage V 1 . 
         [0029]    The third reference pin  231  is connected to ground via a bias resistor Rin. The first reference pin  211 , the third reference pin  231 , and the bias resistor Rin constitute a first series branch  200 . The third reference pin  231  serves as an output for providing a first reference voltage V 1  out. 
         [0030]    The first reference voltage V 1 out is measured from the third reference pin  231 . 
         [0031]    A minimum value of the first reference voltage V 1 out is calculated. A maximum resistance of (R 1 +R 2 +R 3 ) is defined as R 1 max. Thus, V 1 out meets the following formula: 
         [0000]        V 1out≧( V 1 *R in)/( R 1max+ R in) 
         [0032]    If one defines the minimum value of the first reference voltage V 1 out as V 1 min, then V 1 min=(V 1 *Rin)/(R 1 max+Rin). Thus, once the values of the bias resistor Rin, the R 1 max, and the first input voltage V 1  are confirmed, a bonding resistance of the first branch  200  can be examined by comparing the measured value of V 1 out to the computed value of (V 1 *Rin)/(R 1 max+Rin). 
         [0033]    The second reference pin  212  is coupled to a second input voltage V 2 . 
         [0034]    The fourth reference pin  232  is connected to ground via the bias resistor Rin. The second reference pin  212 , the fourth reference pin  232 , and the bias resistor Rin constitute a second series branch  210 . The fourth reference pin  232  serves as an output for providing a second reference voltage V 2 out. 
         [0035]    The second reference voltage V 2 out is measured from the fourth reference pin  231 . 
         [0036]    A minimum value of the second reference voltage V 2 out is calculated. A maximum resistance of (R 4 +R 5 +R 6 ) is defined as R 2 max. Thus, V 1 out meets the following formula: 
         [0000]        V 2out≧( V 2 *R in)/( R 2max+ R in) 
         [0037]    If one defines the minimum value of the second reference voltage V 2 out as V 2 min, then V 2 min=(V 2 *Rin)/(R 2 max+Rin). Thus, once the values of the bias resistor Rin, the R 2 max, and the second input voltage V 2  are confirmed, a bonding resistance of the second branch  210  can be examined by comparing the measured value of V 2 out to the calculated value of (V 2 *Rin)/(R 2 max+Rin). 
         [0038]    Referring to  FIG. 4 , this shows a comparator  40  that can be used in either of the above-described first and second embodiments of the present invention. In general, the comparator  40  can compare a value of a received voltage Cin to a pre-stored voltage value, and can output a comparison signal Cout representing a result of the comparison. Thus the above-described comparing processes of the first and second embodiments can be performed by the comparator  40 . The comparator  40  includes a memory unit  41  for storing the values of Vmin, V 1 min, and V 2 min. The comparator  40  receives the reference voltages Vout, V 1 out, and V 2 out, and compares the reference voltages Vout, V 1 out, and V 2 out to Vmin, V 1 min, and V 2 min respectively. If Vout≧min, or V 1 out≧V 1 min, or V 2 out≧V 2 min, the comparator  40  outputs a high-level comparison signal Cout to indicate that the bonding resistance examined is normal and satisfactory. Otherwise, the comparator outputs a low-level comparison signal Cout to indicate that the bonding resistance examined is abnormally high and not satisfactory. 
         [0039]    Further or alternative embodiments may include the following. In one example, the first and second reference pins  211 ,  212  can also be two first signal pins, and the third and fourth reference pins  231 ,  232  can also be two second signal pins. 
         [0040]    It is believed that the present embodiments and their advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the spirit or scope of the invention or sacrificing all of its material advantages, the examples hereinbefore described merely being preferred or exemplary embodiments of the invention.