Abstract:
VCO frequency is continuously variable through a wide frequency range in proportion to a first control voltage VC produced by a PLL containing the VCO. A second control voltage NVC is produced as a monotonically decreasing function of VC. A first current I 0  is produced in proportion to VC and a second current I 1  is produced in proportion to NVC. I 1  is subtracted from I 0 , producing a control current IC=I 0 -I 1  which is applied to the VCO.

Description:
TECHNICAL FIELD 
     The invention provides a wide frequency range voltage-controlled oscillator (VCO) which utilizes negative feedback of the control voltage output by a phase locked loop (PLL) to adjust the VCO&#39;s frequency. 
     BACKGROUND 
     Phase-locked loops (PLLs) are widely used in a variety of communications and control systems applications, including frequency synthesis, clock recovery, signal modulation and signal demodulation applications. A typical analog PLL incorporates a phase detector, a voltage-controlled oscillator (VCO) and a low pass filter. In some applications, it is desirable that the frequency of the VCO&#39;s output clock signal be variable within a wide frequency range. 
     FIG. 1 schematically depicts a voltage-controlled ring oscillator—a common prior art VCO architecture formed by connecting a plurality of delay cells  10 ,  12  . . .  14  in a closed loop. The output clock frequency is determined by the delay contributed by each delay cell, which is in turn controlled by the PLL&#39;s output control voltage VC, as shown schematically in FIG. 2 for a representative delay cell D. If the FIG. 1 VCO is to be variable within a wide frequency range, then each delay cell must have a correspondingly wide delay tuning range. 
     Each delay cell D typically comprises two transistors (not shown) coupled to form a differential pair, and some active loading components (not shown). Each delay cell D sinks a tail current I tail  through voltage-to-current converter  16 . Each delay cell D&#39;s delay value is determined by that cell&#39;s I tail  value, which is in turn determined by the control voltage VC. Accordingly, the delay tuning range of each delay cell D is limited by the voltage range within which VC can be varied, which is in turn constrained by the power supply voltage, i.e. 0≦VC≦V dd . More particularly delay cell D&#39;s output frequency f is a function of both I tail  and VC. Consequently, and as shown in FIG. 3, if I tail  is too small, f is constrained within a relatively low frequency sub-range [f L1 ,f H1 ] as indicated at  18 ; whereas, if I tail  is too large, f is constrained within a relatively high frequency sub-range [f L2 ,f H2 ] as indicated at  20 . 
     If an offset current source  22  is connected in parallel across voltage-to-current converter  16  as shown in FIG. 4, then the output frequency f can be controlled as a function of both the tail current I tail  sunk through voltage-to-current converter  16  (which is determined by VC as aforesaid) and the offset current I offset  sunk through offset current source  22 . A digital counter or similar means (not shown) can be used to control offset current source  22  so as to vary I offset  through a range of discrete values I offset1 , I offset2 , I offset3 , I offset4 , I offset5 , etc. By selectably controlling I offset  in this fashion one may select any one of a corresponding number of discrete frequency operating sub-ranges [f L1 ,f H1 ], [f L2 ,f H2 ], [f L3 ,f H3 ], [f L4 ,f H4 ], [f L5 ,f H5 ], etc. as indicated at  24 ,  26 ,  28 ,  30 ,  32  respectively in FIG.  5 . 
     The discrete I offset  values, and consequently the discrete frequency operating sub-ranges of the FIG. 4 apparatus are undesirably affected by changes in integrated circuit process and operating temperature conditions. The FIG. 4 apparatus also requires presetting of digital registers, initialization of comparator reference voltages, or some similar operation in order to select a particular one of the discrete frequency operating sub-ranges. It is difficult to ensure that all such preset or initialization values will produce the desired frequency operating sub-range under all integrated circuit process and operating temperature conditions which are likely to be encountered. Moreover, the PLL locking time is increased by the delay inherent in changing the preset or initialization values in order to select a different frequency operating sub-range. 
     SUMMARY OF INVENTION 
     The invention provides a method and apparatus for continuously varying VCO frequency through a wide frequency range in proportion to a first control voltage VC produced by a PLL containing the VCO. A second control voltage NVC is produced as a monotonically decreasing function of VC. A first current I 0  is produced in proportion to VC and a second current I 1  is produced in proportion to NVC. I 1  is subtracted from I 0 , producing a control current IC=I 0 -I 1  which is applied to the VCO. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     FIG. 1 schematically depicts a prior art voltage-controlled ring oscillator. 
     FIG. 2 schematically depicts a prior art voltage controlled delay cell. 
     FIG. 3 graphically depicts the output clock frequency to input voltage transfer function of the FIG. 2 apparatus. 
     FIG. 4 schematically depicts a prior art voltage controlled delay cell having an offset current source. 
     FIG. 5 graphically depicts the output clock frequency to input voltage transfer function of the FIG. 4 apparatus. 
     FIG. 6 is a block diagram representation of a negative feedback VCO control scheme in accordance with the invention. 
     FIG. 7 graphically depicts the voltage transfer function of the negative feedback voltage generator portion of the FIG. 6 apparatus. 
     FIG. 8 is an electronic circuit schematic depicting one embodiment of a negative feedback voltage generator in accordance with the invention. 
     FIG. 9 schematically depicts one embodiment of a voltage-to-current converter in accordance with the invention. 
     FIG. 10 graphically depicts the output current to input voltage transfer function of the FIG. 9 apparatus. 
     FIG. 11 graphically depicts the output clock frequency to input voltage transfer function of the FIG. 9 apparatus. 
    
    
     DESCRIPTION 
     Throughout the following description, specific details are set forth in order to provide a more thorough understanding of the invention. However, the invention may be practiced without these particulars. In other instances, well known elements have not been shown or described in detail to avoid unnecessarily obscuring the invention. Accordingly, the specification and drawings are to be regarded in an illustrative, rather than a restrictive, sense. 
     As shown in FIG. 6, the invention incorporates a negative feedback control voltage generator  34  and a voltage-to-current (V-I) converter  36 . As hereinafter explained, negative feedback control voltage generator  34  converts the control voltage VC supplied by a PLL (not shown) to a negative feedback control voltage NVC and applies NVC to one of V-I converter  36 &#39;s two input ports. VC is applied to V-I converter  36 &#39;s other input port. As is also hereinafter explained, V-I converter  36  utilizes VC and NVC to produce a control current IC which is applied to delay cell D to control the cell&#39;s delay value. Delay cell D can be a conventional prior art delay cell and accordingly need not be described further. 
     As depicted in FIG. 7, negative feedback control voltage generator  34  has a monotonic (not necessarily linear) decreasing transfer function such that if VC is low NVC is high, and vice versa. Negative feedback control voltage generator  34  automatically and continuously adjusts NVC as VC changes, without any need for presetting of digital registers, initialization of comparator reference voltages, etc. 
     FIG. 8 depicts one possible embodiment of negative feedback control voltage generator  34  incorporating two NMOS transistors N 1 , N 2  and one PMOS transistor P 1 . The power supply voltage V dd  is applied to P 1 &#39;s source. P 1 &#39;s gate is connected to P 1 &#39;s drain (i.e. P 1  is diode-connected to function as a load). N 2 &#39;s drain is also connected to P 1 &#39;s drain. N 1 &#39;s drain is connected to N 2 &#39;s source and N 1 &#39;s source is grounded (i.e. N 1  is configured as a single stage common source amplifier). The PLL control voltage VC is applied to N 1 &#39;s gate and a biasing voltage V bias  is applied to N 2 &#39;s gate to match negative feedback control voltage generator  34  to delay cell D. The desired NVC output signal is provided at N 1 &#39;s drain. When VC is low, N 1  operates in its cut-off region, pulling N 1 &#39;s drain to a high voltage. When VC is high, N 1  turns on, pulling N 1 &#39;s drain voltage almost to ground, such that the output voltage NVC is very small. 
     As previously explained, VC and NVC are applied to the respective inputs of V-I converter  36  which thereupon produces control current IC for application to each delay cell in the VCO. More particularly, if VC is small and NVC is large, V-I converter  36  produces a correspondingly small IC. Conversely, if VC is large and NVC is small, V-I converter  36  produces a correspondingly large IC. FIG. 9 depicts one possible embodiment of V-I converter  36  incorporating opposite polarity voltage-controlled DC current sources  38 ,  40  connected in parallel. Current source  38  is controlled by the PLL control voltage VC and produces an output current I 0 . Current source  40  is controlled by the negative feedback control voltage NVC and produces an output current I 1 . The resultant control current IC=I 0 -I 1 . 
     FIG. 10 graphically depicts V-I converter  36 &#39;s output current to input voltage transfer function. As can be seen, I 0  increases as the PLL control voltage VC increases, whereas I 1  decreases as VC increases. If VC is small, the resultant control current IC is small, even if I 0  is relatively large, due to the current subtracting effect of the lower I 1  value. Conversely, if VC is large, IC is large since I 1  becomes negligible and IC approaches I 0  as VC approaches its maximum. 
     In operation, when the PLL&#39;s reference clock frequency is low, the PLL produces a low control voltage VC. Consequently, negative feedback control voltage generator  34  produces a correspondingly high negative feedback control voltage NVC. When applied to the respective inputs of V-I converter  36 , the low VC and high NVC produce a low control current IC which can be applied to the VCO to generate a low frequency to lock the PLL. Conversely, when the PLL&#39;s reference clock frequency is high, VC is high, causing negative feedback control voltage generator  34  to produce a correspondingly low NVC. When applied to V-I converter  36 , the high VC and low NVC produce a high IC which can be applied to the VCO to generate a high frequency to lock the PLL. FIG. 11 reproduces the relatively low [f L1 ,f H1 ] and relatively high [f L2 ,f H2 ] prior art frequency sub-ranges  18 ,  20  previously described with reference to FIG. 3, and also shows the extended frequency range [f L1 ,f H2 ]  42  attainable by the invention. 
     Persons skilled in the art will appreciate that the invention extends the VCO frequency tuning range without dividing the tuning range into discrete frequency sub-ranges which must be selected by time consuming presetting of digital registers, initialization of comparator reference voltages, etc. Automatic, continuously variable frequency tuning is achieved solely by adjusting the control voltage VC, independently of changes in integrated circuit process and operating temperature conditions.