Abstract:
A control circuit for controlling a plurality of power supply modules connected in parallel to provide power to a single load. The control module first converts first analog data corresponding to a voltage level which is applied to the load. The control module then compares the voltage level to a predetermined voltage level and computes a voltage deviation between the predetermined voltage level and the voltage applied to the load. The control module then computes whether the voltage deviation is within a proper limit or not. The control module then sends a pulse width data signal corresponding to the voltage deviation to the power supply modules in order to control the amount of power each module supplies to the load.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a power control system for data processing apparatuses or the like, and more particularly to a power control system for balancing the output currents and stabilizing the output voltages of a plurality of switching power supply modules. 
     Power control systems of this kind according to the prior include what is disclosed in the U.S. Pat. No. 4,924,170. Each of the power supply modules disclosed therein comprises converter means for detecting an amperage supplied to each connected load and converting into a preset corresponding voltage; a comparator means for comparing the voltage from the converting means with a predetermined reference voltage; and pulse width changing means for supplying a power switch with a control signal to enlarge the pulse width when the comparator means determines the voltage from the converting means to be lower than the reference voltage, and supplying the power switch with a control signal to narrow the pulse width when the comparator means determines the voltage from the converting means to be higher than the reference voltage. 
     This prior art power supply module, however, involves the following problems. 
     First, since the output amperages from different loads are not in a perfect equilibrium, usually large currents are supplied to some of the loads all the time, with the result that the loads themselves are heavily burdened and deteriorated in reliability. 
     Furthermore, even if said means is operated to balance the output currents from the loads, it takes time to control the output currents from the loads because the output impedance of each load is extremely small at an amperage below the rated output current, and the output current from the output voltage from each load after adjustment is unstable. 
     SUMMARY OF THE INVENTION 
     A principal object of the present invention is to obviate the above-mentioned disadvantages and provide a power control system for simultaneously and precisely accomplishing the balancing and stabilization of output currents from a plurality of switching power supply modules connected in parallel and the stabilization of output voltages therefrom. 
     According to the invention, there is provided a power control system equipped with first processing means for converting first analog data supplied from a plurality of switching power supply modules; second processing means for comparing said digital data, converted by said first processing means, with predetermined reference voltage data and computing voltage deviations; third processing means for judging whether or not said voltage deviations computed by said second processing means are within a permissible extent; fourth processing means for adding said voltage deviations to, or subtracting them from, predetermined reference pulse width data if said voltage deviations are judged to be beyond the permissible extent; and fifth processing means for supplying each switching power supply module with the result of arithmetic operation by said fourth processing means as first pulse width data. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, wherein: 
     FIG. 1 is a block diagram of a preferred embodiment of the invention; 
     FIG. 2 is a flow chart showing the output voltage control processing in this preferred embodiment; and 
     FIG. 3 is a flow chart showing the output current control processing in this preferred embodiment. 
     In these drawings, the same reference numerals denote respectively the same constituent elements. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Next will be described in detail a preferred embodiment of the present invention with reference to drawings. 
     Referring to FIG. 1, the preferred embodiment of the invention consists of a host control unit 1, a power supply control module 10, a first switching power supply module 100, a second switching power supply module 106, and a logical unit 113. 
     The host control unit 1 is connected to the power supply control module 10 via an interface circuit (not shown). 
     The first switching power supply module 100 and the second switching power supply module 106 are respectively provided with a first current feedback section 103 and a second current feedback section 109, and with a first DC-to-DC converter section 101 and a second DC-to-DC converter section 107. 
     The power supply control module 10 consists of an input/output (I/O) port 11; a program memory 12; a data memory 13 for storing predetermined reference voltage data; a first analog-to-digital (A/D) converter section 14 for converting second analog data I1 related to a first output current 104, received from the first current feedback section 103 of the first switching power supply module 100 via a signal line 105, into digital data DI1; a second A/D converter section 15 for converting second analog data I2 related to a second output current 110, received from the second current feedback section 109 of the second switching power supply module 106 via a signal line 111, into digital data DI2; a third A/D converter section 16 for receiving first analog data V, related to a stabilized power output voltage generated by parallel feeding of the first stabilized output voltage 104 of the first switching power supply module 100 and the second stabilized output voltage 110 of the second switching power supply module 106, via a signal line 114, and converting the first analog data V into digital data DV; a microprocessor 17 for controlling each section to perform processing to balance or stabilize its output current or output voltage; a first register 18 for storing second pulse width data V2 generated corresponding to the second analog data I1; a second register 19 for storing second pulse width data V2 generated corresponding to the second analog data I2; a counter 20 for counting the output pulses from a second clock generating section 23 and outputting the count; a bus 21 connecting the I/O port 11, program memory 12, data memory 13; first A/D converter section 14, second A/D converter section 15, third A/D converter section 16, microprocessor 17, first register 18 and second register 19; a first clock generating section 22; the second clock generator section 23 for supplying pulses having the minimum sufficient pulse width for allowing the first switching power supply module 100 and the second switching power supply module 106 to perform control to stabilize the output voltages; a first comparator section 24 for comparing the second pulse width data V2, stored in the first register 18, with the output value of the counter 20 and, if they are found identical, supplying an identity signal; a second comparator section 25 for comparing the second pulse width data V2, stored in the second register 19, with the output value of the counter 20 and, if they are found identical, supplying an identity signal; a first flip-flop (F/F) 26 which is set in accordance with the identity signal supplied from the first comparator section 24 to supply first DC drive pulses and reset in accordance with an overflow signal of the counter 20; and a second F/F 27 which is set in accordance with the identity signal supplied from the second comparator section 25 to supply second DC drive pulses and reset in accordance with an overflow signal of the counter 20. 
     The first switching power supply module 100 is provided with the first DC-to-DC converter section 101 for receiving first DC drive pulses to perform pulse width control to stabilize the output voltage or output current, a first non-stabilized voltage input 102, and the first current feedback section 103. 
     The second switching power supply module 106 is provided with the second DC-to-DC converter section 107 for receiving second DC drive pulses to perform pulse width control to stabilize the output voltage or output current, a second non-stabilized voltage input 108, and the second current feedback section 109. 
     The logical unit 113 is provided with a stabilized power output terminal 112 to which is fed a stabilized power output voltage generated by parallel feeding of the first stabilized output voltage 104 of the first switching power supply module 100 and the second stabilized output voltage 110 of the second switching power supply module 106. 
     Next will be described the operation of this preferred embodiment with reference to FIGS. 1 through 3. 
     First, the microprocessor 17 of the power supply control module 10 receives via the signal line 114 first analog data V, related to a stabilized power output voltage generated by parallel feeding of the first stabilized output voltage 104 supplied from the first DC-to-DC converter section 101 of the first switching power supply module 100 to the logical unit 113 and the second stabilized output voltage 110 supplied from the second DC-to-DC converter section 107 of the second switching power supply module 106 to the logical unit 113, and converts the first analog data V into digital data (FIG. 2, step S200). 
     Then, the microprocessor 17 of the power supply control module 10 compares, using the third A/D converter section 16, the digital data converted from the first analog data V with reference data stored in advance in the data memory 13, and computes the voltage deviation between them (FIG. 2, step S201). 
     The microprocessor 17 of the power supply control module 10 further judges whether or not this voltage deviation is within a predetermined extent of permissible errors (FIG. 2, step S202). 
     At this time, the microprocessor 17 of the power supply control module 10, if it judges that the voltage deviation is beyond the predetermined extent of permissible errors, reads out reference pulse width data stored in advance in the data memory 13, performs an arithmetic operation add this voltage deviation to, or subtract it from, the reference pulse width data (FIG. 2, step S203), and generates the results of this operation as first pulse width data (FIG. 2, step S204). 
     Next, the microprocessor 17 of the power supply control module 10 receives at predetermined intervals the second analog data I1 related to the first stabilized output voltage 104 supplied from the first switching power supply module 100 and the second analog data I2 related to the second stabilized output voltage 110 supplied from the second switching power supply module 106 via the signal lines 105 and 111, respectively, and convert them into the digital data DI1 and DI2 with the first A/D converter section 14 and the second A/D converter section 15, respectively (FIG. 3, step S300). 
     Then, the microprocessor 17 of the power supply control module 10 computes the average from the digital data DI1 and DI2, and figures out current deviations by comparing the output currents of the first switching power supply module 100 and the second switching power supply module 106 with this average (FIG. 3, step S301). 
     The microprocessor 17 of the power supply control module 10 further compares the current deviations with the digital data, and judges whether or not they are within the extent of permissible errors (FIG. 3, step S302). 
     Thus, if the digital data is greater by the average by 1[A] or more, it will perform an arithmetic operation to subtract 1 unit from the first pulse width data, or if the average is greater than the digital data by 1[A] or more, it will perform an operation to add 1 unit to the first pulse width data (FIG. 3, step S303), generates the result of operation as second pulse width data, and supplies it to the first register 18 or the second register 19 (FIG. 3, step S304). 
     The second pulse width data stored in the first register 18 and the second register 19 are supplied, respectively via the first comparator section 24 and the second comparator section 25 and via the first F/F 26 and the second F/F 27, to the first switching power supply module 100 and the second switching power supply module 106 as first DC drive pulse and second DC drive pulse, respectively. 
     By repeating the above-described series of operations, control is accomplished by the arithmetic processing by the microprocessor 17 so as to balance the output current of the first switching power supply module 100 and that of the second switching power supply module 106 in a stable state. 
     Accordingly, the balancing and stabilization of the output currents of a plurality of switching power supply modules connected in parallel and the stabilization of their output voltages can be achieved simultaneously at high precision. 
     While the present invention has been described with reference to the preferred embodiment thereof, it will now be readily possible for persons skilled in the art to put this invention into practice in various other manners.