Abstract:
For a hot carrier injection tolerant network on chip (NoC) router architecture, a coupling module modifies couplings of connecting wires to input buffer data bits in an NoC data channel. A connection module modifies connection points of an input buffer to the connecting wires.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority to Provisional Patent Application No. 61/865,304 entitled “Hot Carrier Injection Tolerant Network on Chip Router Architecture” and filed on Aug. 13, 2013 for Dean Michael Ancajas et al., which is incorporated herein by reference. 
     
    
       [0002]    This invention was made with government support under contract CNS-1117425 and CAREER-1253024 awarded by the National Science Foundation. The government has certain rights in the invention. 
     
    
     FIELD 
       [0003]    The subject matter disclosed herein relates to network-on-chip (NoC) router architectures and more particularly relates to hot carrier injection (HCI) tolerant NoC router architectures. 
       BACKGROUND 
     Description of the Related Art 
       [0004]    NoC router architectures are often used for multiple core semiconductor devices. Unfortunately, some elements of a NoC router may degrade and fail earlier than other elements due to HCI as charge carriers are trapped in gate dielectrics. As a result, the overall life of the device is reduced. 
       BRIEF SUMMARY 
       [0005]    An apparatus is disclosed for a hot carrier injection tolerant NoC router architecture. A coupling module modifies couplings of input buffer data bits to connecting wires in a NoC data channel. A connection module modifies connection points of an input buffer to the connecting wires. A method and NoC performing the functions of the apparatus are also disclosed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    In order that the advantages of the embodiments of the invention will be readily understood, a more particular description of the embodiments briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings. Understanding that these drawings depict only some embodiments and are not therefore to be considered to be limiting of scope, the embodiments will be described and explained with additional specificity and detail through the use of the accompanying drawings, in which: 
           [0007]      FIG. 1  is a schematic block diagram illustrating one embodiment of a NoC; 
           [0008]      FIG. 2A  is schematic block diagram illustrating one embodiment of a node; 
           [0009]      FIG. 2B  is schematic block diagram illustrating one alternate embodiment of a node; 
           [0010]      FIG. 3  is a schematic block diagram illustrating one embodiment of an input buffer; 
           [0011]      FIG. 4  is a schematic block diagram illustrating one embodiment of a selector; 
           [0012]      FIG. 5  is a schematic block diagram illustrating one embodiment of an idle circuit; 
           [0013]      FIG. 6  is a schematic block diagram illustrating one embodiment of a router apparatus; 
           [0014]      FIG. 7  is a schematic flow chart diagram illustrating one embodiment of a router modification method; and 
           [0015]      FIG. 8  is a schematic flow chart diagram illustrating one embodiment of an idle cycle modification method. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0016]    Reference throughout this specification to “one embodiment,” “an embodiment,” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases “in one embodiment,” “in an embodiment,” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment, but mean “one or more but not all embodiments” unless expressly specified otherwise. The terms “including,” “comprising,” “having,” and variations thereof mean “including but not limited to” unless expressly specified otherwise. An enumerated listing of items does not imply that any or all of the items are mutually exclusive and/or mutually inclusive, unless expressly specified otherwise. The terms “a,” “an,” and “the” also refer to “one or more” unless expressly specified otherwise. 
         [0017]    The schematic flowchart diagrams and/or schematic block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations. It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the Figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. Although various arrow types and line types may be employed in the flowchart and/or block diagrams, they are understood not to limit the scope of the corresponding embodiments. Indeed, some arrows or other connectors may be used to indicate only an exemplary logical flow of the depicted embodiment. 
         [0018]    The description of elements in each figure may refer to elements of proceeding figures. Like numbers refer to like elements in all figures, including alternate embodiments of like elements. Ancajas, Dean Michael et al., “HCI-Tolerant NoC Router Microarchitecture” (Ancajas) is incorporated herein by reference in its entirety. 
         [0019]      FIG. 1  is a schematic block diagram illustrating one embodiment of an NoC  100 . The NoC  100  includes a plurality of nodes  105  and a plurality of cores  190 . The cores  190  may include one or more processor cores, one or more specialized processing units, one or more memories, or combinations thereof. 
         [0020]    The nodes  105  are coupled to connecting wires  110 . Data may be communicated between the nodes  105 . In one embodiment, data is communicated between cores  190  and/or input/out modules  195  through the nodes  105  and connecting wires  110 . As a result, the NoC  100  provides a highly flexible architecture. 
         [0021]    When semiconductor gates of elements of the NoC  100  switch frequently and/or carry current, HCI is more likely. As a result, charge carriers may be trapped within a gate dielectric of an element. The trapping of charge carriers in gate dielectrics may damage and/or destroy the ability of a semiconductor gate to switch. As a consequence, the gate fails, preventing the NoC element from functioning and degrading and/or terminating operations of the NoC device  100 . 
         [0022]    Unfortunately, some gates may consistently switch frequently and/or carry current because of the data values that those gates carry while other gates switch and/or carry current much less frequently. The embodiments described herein balances switching and/or current carrying in element gates to reduce HCI and extend the life of the element gates and the NoC device  100  as will be described hereafter. 
         [0023]      FIG. 2A  is a schematic block diagram illustrating one embodiment of a node  105 . The node  105  includes one or more input buffers  115 , a selector  145 , and one or more connection points  150  from the selector  145  to the connecting wires  110 . 
         [0024]    The connection points  150  each connect to one connecting wire  110 . The input buffers  115  receive input values from a core  190 , a connecting wire  110 , or the like. The input values are encoded as input buffer data bits  125 .  FIG. 2A  depicts the input buffer  115  communicating the input buffer data bits  125  through the selector  145  to a connection point  150 . The input buffer data bits  125  are then communicated over the connecting wire  110  to another node  105 . 
         [0025]      FIG. 2A  is a schematic block diagram illustrating one alternate embodiment of a node  105 .  FIG. 2B  depicts the input buffer data bits  125  being communicated through the input buffer  115 , the selector  145 , the connection points  150 , and a switch  120  to the connecting wires  110 . In one embodiment, the switch  120  is a crossbar switch. 
         [0026]    The connecting wires  110  may carry the data values of the input buffer data bits  125  to the input buffer  115  of another node  105 . The paths followed by the input buffer data bits  125  may comprise an NoC data channel. In the depicted embodiments, the input buffer data bits  125  include north input buffer data bits  125 N, south input buffer data bits  125 S, east input buffer data bits  125 E, and west input buffer data bits  125 W. The selector  145  may route input buffer data bits  125  from any of the input buffers  145  to any of the connection points  150  as will be described hereafter. For example, the selector  145  may route north input buffer data bits  125 N to the south connection point  150 S, the east connection point  150 E, or the west connection point  150 W. 
         [0027]      FIG. 3  is a schematic block diagram illustrating one embodiment of an input buffer  115 . The input buffer  115  may modify the couplings of the input buffer data bits  125  to the selector  145 , the connection points  150 , and ultimately to the connecting wires  110 . The input buffer includes the input buffer data bits  125 , one or more multiplexers  135 , one or more multiplexer outputs  135 , buffers  185 , and shuffled input buffer data bits  155 . In the depicted embodiment, the input buffer data bits  125  are divided into four groups, a first input buffer data bit group  125   a , a second input buffer data bit group  125   b , a third input buffer data bit group  125   c , and a fourth input buffer data bit group  125   d . Each input buffer data bit groups  125   a - d  may have a same number of bits. One of skill in the art will recognize that the embodiments may be practiced with any number of input buffer data bit groups. 
         [0028]    Input buffer data bit groups  125   a - d  are received at the multiplexers  135 . A coupling module  405  may select one of the input buffer data bit groups  125   a - d  at each multiplexer  135 . The selected input buffer data bit groups  125   a - d  at each multiplexer  135  is communicated through multiplexer outputs  135  to the buffer  185 . The buffer  185  outputs shuffled input buffer data bits  155 . The selector  145  may further communicate the shuffled input buffer data bits  155  to the connecting wires  110  and/or to the switch  120 . 
         [0029]    The coupling module  410  modifies the couplings of the input buffer data bits  125  to the connecting wires  110 . For example, for 16-bit input buffer data groups  125   a - d , the input buffer data bits  125  may be shuffled relative to the input bits of the connecting wire  110  and/or switch  120  as illustrated in Table 1. 
         [0000]    
       
         
               
               
               
             
               
               
               
               
               
             
               
               
               
             
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
             
             
               
                   
                   
               
               
                   
                 Connecting wire/Switch Input Bits 
                   
               
             
          
           
               
                 Multiplexer 
                 63-58 
                 32-47 
                 31-16 
                 15-0  
               
             
          
           
               
                 Selection 
                 Shuffled Input Buffer Data Bits 
               
               
                   
               
             
          
           
               
                 0 
                 63-58 
                 32-47 
                 31-16 
                 15-0  
               
               
                 1 
                 32-47 
                 31-16 
                 15-0  
                 63-58 
               
               
                 2 
                 31-16 
                 15-0  
                 63-58 
                 32-47 
               
               
                 3 
                 15-0  
                 63-58 
                 32-47 
                 31-16 
               
               
                   
               
             
          
         
       
     
         [0030]    As a result, the coupling of the input buffer data bits  125  to the buffer  185 , selector  145 , connection points  150 , and connecting wires  110  are shuffled so that the same input buffer data bits  125  are not communicated over the same NoC data channel bits. As a result, frequently switching and/or current carrying input data buffer bits  125  are balanced across the paths of the NoC data channel. 
         [0031]    The input buffer  115  may be the north input buffer  115 N, the south input buffer  115 S, the east input buffer  115 E, or the west input buffer  115 W. As a result, the shuffled input buffer data bits  155  may be the north shuffled input buffer data bits  155 N, the south shuffled input buffer data bits  155 S, the east shuffled input buffer data bits  155 E, and the west shuffled input buffer data bits  155 W. 
         [0032]      FIG. 4  is a schematic block diagram illustrating one embodiment of a selector  145 . The selector  145  includes one or more decoders  175 , virtual channel paths  170 , and one or more virtual channels  180 . A connection module  410  may employ the selector  145  to modify the connection points  150  of the input buffer  115  to the connecting wires  110 . 
         [0033]    The selector  145  receives shuffled input buffer data bits  155  at the decoders  175 . For example, a north decoder  175 N may receive north shuffled input buffer data bits  155 N, a south decoder  175 S may receive south shuffled input buffer data bits  155 S, an east decoder  175 E may receive east shuffled input buffer data bits  155 E, and a west decoder  175 W may receive west shuffled input buffer data bits  155 W. 
         [0034]    The virtual channels  180  handle multiple concurrent streams of input values. Each virtual channel  180  waits for a turn to use the connecting wires  110  and/or switch  120 . Each decoder  175  selects a virtual channel path  170  to a virtual channel  180 . Each decoder  175  may select a virtual channel path  170  through to any virtual channel  180 . In one embodiment, the virtual channels  180  request access to the connection points  150  and the switch  120  or connecting wires  110 . The virtual channels  180  may request access each clock cycle. When one of virtual channels  180  is granted access, that virtual channel  180  communicates the shuffled input buffer data bits  155  to the switch  120  or the connecting wires  110 . 
         [0035]    The connection module  410  may employ the decoders  175  to modify the connection points  150  of the input buffers  115  to the connecting wires  110  and/or to the switch  120 . In one embodiment, the connection module  410  may balance frequently switching and/or current carrying input data buffer bits  125  across the paths of the NoC data channel. Table 2 illustrates some possible combinations of virtual channels  180  and input buffers  115 . For simplicity, only an illustrative portion of the combinations are shown. In Table 2, the first digit refers to a number of the virtual channel  180  and a second letter refers to “north,” “south,” “east,” and “west.” 
         [0000]    
       
         
               
               
               
               
               
             
           
               
                   
               
               
                 Virtual 
                   
                   
                   
                   
               
               
                 Channel Path 
                 North 
                 South 
               
               
                 Selection 
                 Decoder 
                 Decoder 
                 East Decoder 
                 West Decoder 
               
               
                   
               
             
             
               
                 0 
                 1N 
                 1S 
                 1E 
                 1W 
               
               
                 1 
                 2S 
                 2E 
                 2W 
                 2N 
               
               
                 2 
                 1E 
                 1W 
                 1N 
                 1S 
               
               
                 3 
                 2W 
                 2N 
                 2S 
                 2E 
               
               
                 . . . 
                 . . . 
                 . . . 
                 . . . 
                 . . . 
               
               
                 255  
                 2W 
                 2E 
                 2S 
                 2N 
               
               
                   
               
             
          
         
       
     
         [0036]    Thus any decoder  175  may route the input data buffer bits  125  or shuffled input data buffer bits  125   155  through any virtual channel  180  to a desired connection point  150 . 
         [0037]      FIG. 5  is a schematic block diagram illustrating one embodiment of an idle circuit  102 . The idle circuit  102  includes an aging optimized value  205 , an idle value selector  215 , and an idle module  415 . 
         [0038]    The aging optimized value  205  may be identified during an off-line analysis of data traffic within the NoC  100 . The analysis may be a simulated analysis. The aging optimized value  205  may be selected reduce transistor aging in the NoC data channel when transmitted in place of an idle data value during an idle cycle. In one embodiment, the aging optimized value is selected to reduce HCI. The aging optimized value may be selected to reduce switching. Alternatively, the aging optimized value may be selected to reduce asserted signals. In a certain embodiment, the aging optimized value is selected to reduce de-asserted signals. 
         [0039]    The aging optimized value  205  may be transmitted to the idle value selector  215  from a register storing the aging optimized value  205 . The idle value selector  215  may be a multiplexer controlled by the idle module  415 . 
         [0040]    The idle module  415  may detect an idle cycle for an NoC data channel. The idle cycle may be detected for the input buffers  115 , the decoders  175 , the virtual channels  180 , the elements of the switch  120 , and/or the connecting wires  110 . In addition, the idle cycle may be detected for the switch  120 . In one embodiment, the idle module  415  detects the idle cycle when no active data values are transmitted over a specified portion of the NoC data channel. 
         [0041]    In one embodiment, an idle input  210  receives signals encoding data values in the NoC data channel and an idle output  220  transmits the signals. If the idle module  415  does not detect an idle cycle, the data values are transmitted by the idle values selector  215  from the idle input  210  to the idle output  220 . However, if the idle module  415  detects the idle cycle, the idle values selector  215  transmits the aging optimized value  205  from the idle output  220  instead of data values of the idle input  210 . As a result, the aging optimized value  205  is transmitted in place of an idle value, reducing transistor aging. 
         [0042]      FIG. 6  is a schematic block diagram illustrating one embodiment of a router apparatus  400 . The apparatus  400  includes a coupling module  405 , a connection module  410 , an idle module  415 , and the condition module  420 . The coupling module  405 , the connection module  410 , the idle module  415 , and the condition module  420  may each comprise a plurality of semiconductor gates. In addition, the coupling module  405 , the connection module  410 , the idle module  415 , and the condition module  420  may comprise a computer readable storage medium storing program code and executed by a processor. 
         [0043]    The coupling module  405  may modify couplings of input buffer data bits  125  to the switch  120  and/or the connecting wires  110  in the NoC data channel. For example, least significant input buffer data bits  125  may first be routed through the least significant bits of the connecting wire  110  and/or switch  120 , and subsequently routed through the most significant bits of the connecting wire  110  and/or switch  120  by modifying the input buffer data bits  125  selected by each of the multiplexers  135  as illustrated in Table 1. In one embodiment, couplings of the input buffer data bits  125  to the connecting wires  110  and/or switch  120  are regularly modified. In one embodiment, the couplings of the input buffer data bits  125  to the connecting wires  110  and/or switch  120  are modified when a modification condition is satisfied. 
         [0044]    The connection module  410  may modify the connection points  150  of an input buffer  115  to the connecting wires  110  and/or switch  120 . For example, the north input buffer data bits  125 N of the north input buffer  115 N may be routed through the north connection points  150 N, the south connection points  150 S, the east connection points  150 E, or the west connection points  150 W. Thus data transfer and switching may be balanced across the connecting wires  110  and/or elements of the switch  120 . The connection points  150  of the input buffer  115  to the connecting wires  110  and/or switch  120  may be regularly modified. In one embodiment, the connection points  150  of the input buffer  115  to the connecting wires  110  and/or switch  120  are modified when the modification condition is satisfied. 
         [0045]    The idle module  415  may detect an idle cycle for a monitored NoC data channel element such as input buffers  115 , decoders  175 , virtual channels  180 , elements of the switch  120 , and/or connecting wires  110 . An idle cycle may be one or more clock cycles during which no data value, also referred to as an idle data value, is transferred through one or more of the input buffer  115 , selector  145 , and/or switch  120 . The idle module  415  may transmit the age optimizing value  205  in place of the idle data value to the input buffer  115 , the selector  145 , and/or switch  120  in response to detecting the idle cycle for the input buffer  115 , decoder  175 , virtual channel  180 , element of the switch  120 , and/or connecting wire  110 . Alternatively, the idle module  415  may transmit the age optimizing value  205  in place of the idle data value to an element of the input buffer  115 , the selector  145 , and/or switch  120  in response to detecting the idle cycle for the input buffer  115 , decoder  175 , virtual channel  180 , element of the switch  120 , and/or connecting wire  110 . 
         [0046]    The condition module  420  determines if the modification condition is satisfied. In one embodiment, the modification condition is an epoch boundary. An epoch may be a specified time interval, a specified number of clock cycles, a specified amount of data transferred, or the like. The epoch boundary may be a start of an epoch, an end of an epoch, an epoch midpoint, or the like. 
         [0047]    Alternatively, the modification condition may be an operational change. In a certain embodiment, the modification condition is satisfied by maintenance operation. 
         [0048]      FIG. 7  is a schematic flow chart diagram illustrating one embodiment of a router modification method  500 . The method  500  may perform functions of the NoC and/or the apparatus  400 . The method  500  may be performed by one or more semiconductor circuits. The semiconductor circuits may include logic circuits, registers, latches, multiplexers, sequencers, data stores, and the like. 
         [0049]    The method  500  starts, and in one embodiment the apparatus  400  initializes  505  states of the coupling module  405 , the connection module  410 , the idle module  415 , and the condition module  420 . For example, the coupling module  405  may store an initial multiplexer selection such as a multiplexer selection of 0 for the multiplexers  135  of the input buffers  115 . In addition, the connection module  410  may select initial virtual channel paths  170  for each of the decoders  175  in the selector  145 . For example, the connection module  410  may select a first north virtual channel  180 Na for the north decoder  175 N, a first south virtual channel  180 Sa for the south decoder  175 S, a first east virtual channel  180 Ea for the east decoder  175 E, and a first west virtual channel  180 Wa for the west decoder  175 W. 
         [0050]    In one embodiment, the idle module  415  may select the aging optimized value  205 . In one embodiment, the aging optimized value  205  is selected from a plurality of values based on a forecast of operations performed by the NoC  100 . Each of the values may be determined during an off-line analysis to reduce transistor aging for a particular type of operation. 
         [0051]    In one embodiment, the condition module  420  initiate an epoch. The epoch may be initiated by starting an epoch timer, zeroing a data counter, or zeroing a clock cycle counter. 
         [0052]    The condition module  420  determines  510  if the modification condition is satisfied. In one embodiment, the modification condition is an epoch boundary. The modification condition may be satisfied when the epoch boundary is reached. For example, the modification condition may be satisfied in the end of each epoch. 
         [0053]    If the modification condition is not satisfied, the condition module  420  continues to determine  510  when the modification condition is satisfied. If the modification condition is satisfied, the coupling module  405  modifies  515  the couplings of input buffer data bits  125  to the switch  120  and/or the connecting wires  110  in the NoC data channel. In one embodiment, the coupling module  405  may modify  515  the couplings by changing the multiplexer selection for the multiplexers  135  as described for  FIG. 3 . 
         [0054]    The connection module  410  may modify the connection points  150  of an input buffer  115  to the connecting wires  110  and/or switch  120 . The connection points  150  may be modified according to a specified schedule such as illustrated in Table 2. Alternatively, the connections of decoders  175  to connection points  150  may be randomly selected. 
         [0055]    The method  500  may loop to continue determining  510  if the modification condition is satisfied, thus regularly modifying  515  the couplings of input buffer data bits  125  to the switch  120  and/or the connecting wires  110  and regularly modifying  520  the connection points  150  of an input buffer  115  to the connecting wires  110  and/or switch  120 . As a result HCI and transistor aging is reduced. 
         [0056]      FIG. 8  is a schematic flow chart diagram illustrating one embodiment of an idle cycle modification  501 . 
         [0057]    The idle module  415  may detect  550  an idle cycle for an element such as input buffer  115 , decoder  175 , virtual channel  180 , element of the switch  120 , and/or connecting wire  110 . An idle cycle may be one or more clock cycles during which no data value is transferred through a monitored element. If no idle cycle is detected, the idle module  415  may cause the idle value selector  215  to select the value of idle input  210  as the idle output  220  and the idle module  415  may continue to monitor for idle cycles. 
         [0058]    If the idle module  415  detects  550  the idle cycle for the monitored element, the idle module  415  may transmit  555  the age optimizing value  205  in place of an idle data value to the monitored element in response to detecting the idle cycle for the monitored element. In one embodiment, the idle module  415  may cause the idle value selector  215  to select the age optimizing value  205  as the idle output  220 . 
         [0059]    For example, if the idle module  415  detects  550  the idle cycle for an input buffer  115 , the idle module  415  may transmit  555  the age optimizing value  205  from the input buffer  115  in place of the idle values of the shuffled input buffer data bits  155 . By transmitting the age optimizing value  205  during idle cycles, HCI and transistor aging are further minimized. As a result, the NoC  100  is more tolerant of HCI. 
         [0060]    The embodiments may be practiced in other specific forms. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.