Abstract:
A variable bias current is provided for the differential pair of an operational transconductance amplifier to improve the gain performance, especially to overcome the slew rate limit of the operational transconductance amplifier. The bias current is adjusted according to the differential input to the differential pair, the difference between the currents of the differential pair, or any one of the currents of the differential pair.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention is related generally to an operational transconductance amplifier (OTA) and, more particularly, to an operational transconductance amplifier without slew rate limit. 
       BACKGROUND OF THE INVENTION 
       [0002]    As shown in  FIG. 1 , in an operational transconductance amplifier  100 , a current source  110  provides a bias current I 1  to a differential pair  108  of which NMOS transistors M 1  and M 2  are controlled by a pair of differential input voltages V −  and V +  to produce two currents I 2  and I 3  respectively, a current mirror  102  composed of two PMOS transistors M 3  and M 4  mirrors the current I 2  to produce a current I 4 , a current mirror  104  composed of two PMOS transistors M 5  and M 6  mirrors the current I 3  to produce a current I 5 , a current mirror  106  composed of two NMOS transistors M 7  and M 8  mirrors the current I 4  to produce a current I 6 , and the output current Io of the operational transconductance amplifier  100  is produced from the difference between the currents I 5  and I 6 . The gain of the operational transconductance amplifier  100  is 
         [0000]    
       
         
           
             
               
                 
                   GM 
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                         Io 
                       
                       
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                               V 
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         [0000]    Ideally, the gain GM of the OTA  100  should be constant. However, in reality, the output current Io tends to be saturated with the increase of the difference between the input voltages V +  and V −  of the OTA  100 , as shown in  FIG. 2 , that is to say, the gain GM of the OTA  100  will be less and less and go into slew rate limit range when the difference between the input voltages V +  and V −  becomes larger. It is because that the bias current I 1  provided by the current source  110  of the OTA  100  is constant, which causes that the differential current d(I 2 −I 3 ) produced by a same differential voltage d(V + −V − ) becomes less and less when the difference between the currents I 2  and I 3  reaches some certain value, and further causes that the variation dIo of the output current Io becomes less and less, so that the gain GM becomes less and less. For some cases, for example response to a load transient, a fast response speed is needed, whereas the OTA  100  cannot have such fast response speed due to the slew rate limit. 
         [0003]    Therefore, an improved operational transconductance amplifier is desired. 
       SUMMARY OF THE INVENTION 
       [0004]    An object of the present invention is to provide a gain improved operational transconductance amplifier. 
         [0005]    According to the present invention, an operational transconductance amplifier comprises a variable current source or a variable voltage source connected to a differential pair such that the bias current provided for the differential pair varies with the differential input of the differential pair, thereby improving the gain in the high differential input range. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0006]    These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which: 
           [0007]      FIG. 1  shows a conventional operational transconductance amplifier; 
           [0008]      FIG. 2  shows the relationship between the differential input and the output current of a conventional OTA; 
           [0009]      FIG. 3  shows a first embodiment OTA according to the present invention; 
           [0010]      FIG. 4  shows the core circuit of  FIG. 3 ; 
           [0011]      FIG. 5  shows a first embodiment for the variable current source shown in  FIG. 4 ; 
           [0012]      FIG. 6  shows a simulation of the relationship between the output current and the differential input of the circuit of  FIG. 5 ; 
           [0013]      FIG. 7  shows a second embodiment for the variable current source shown in  FIG. 4 ; 
           [0014]      FIG. 8  shows a gain performance comparison between the embodiments of the present invention and the conventional OTA of  FIG. 1 ; 
           [0015]      FIG. 9  shows an output performance comparison between the embodiments of the present invention and the conventional OTA of  FIG. 1 ; 
           [0016]      FIG. 10  shows a second embodiment OTA according to the present invention; and 
           [0017]      FIG. 11  is another embodiment by modifying the circuit of  FIG. 10   
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0018]      FIG. 3  shows a first embodiment OTA  200 , which comprises a variable current source  210  to provide a variable bias current I 1  to a differential pair  208  including two PMOS transistors  2082  and  2084  to produce two currents I 2  and I 3  according to two input voltages V −  and V +  respectively, a current mirror  204  composed of two NMOS transistors  2042  and  2044  to mirror the current I 2  to produce a current I 4 , a current mirror  206  composed of two NMOS transistors  2062  and  2064  to mirror the current I 3  to produce a current I 5 , a current mirror  202  composed of two PMOS transistors  2022  and  2024  to mirror the current I 4  to produce a current I 6 , and an output current Io produced from the difference between the currents I 5  and I 6 . In particular, the variable current source  210  adjusts the variable bias current I 1  upon the difference between the input voltages V −  and V + . 
         [0019]      FIG. 4  is the core circuit of  FIG. 3 . It is well know that the current following through a MOS transistor is 
         [0000]        I   D   =K ( Vgs−Vtp ) 2 ,   [Eq-2] 
         [0000]    where K is a constant, Vgs is the voltage between the gate and the source of the MOS transistor, and Vtp is the threshold voltage of the MOS transistor. Assuming that the voltage on node A is Y+Vtp, the voltage V − =Va+X, and the voltage V + =Va, and if the channel-length modulation is ignored, the current following through the PMOS transistor  2082  is 
         [0000]        I 2 =K ( Va+X−Y ) 2 ,   [Eq-3] 
         [0000]    and the current following through the PMOS transistor  2084  is 
         [0000]        I 3 =K ( Va−Y ) 2 .   [Eq-4] 
         [0020]    If the gain GM of the OTA  2 C 0  is constant, d(I 2 −I 3 )/dX is also constant, and therefore (I 2 − 13 ) is a linear function of X. By subtracting the equation Eq-4 from the equation Eq-3, it has 
         [0000]        I 2 −I 3 =K ( Va+X−Y ) 2   −K ( Va−Y ) 2 .   [Eq-5] 
         [0021]    the equation Eq-5 can be simplified as 
         [0000]      ( I 2 −I 3)/ K=X   2 +2 X ( Va−Y ).   [Eq-6] 
         [0022]    As mentioned in the above description, to have a constant gain GM, (I 2 −I 3 ) must be a linear function of X. To eliminate the term X 2  in the equation Eq-6, it will have 
         [0000]        Y =const+(½) X,    [Eq-7] 
         [0023]    where const is a constant. From the equation Eq-7, it can be know that when the difference between the input voltages V −  and V +  increases, the voltage on the node A will increase a half of the difference. 
         [0024]      FIG. 5  shows a first embodiment for the variable current source  210 , in which two NMOS transistors  2102  and  2104  are so arranged to produce two currents I 11  and I 12  upon the voltages V 1 =V − +Vs and V 2 =V + +Vs respectively, where the voltage Vs is constant, and the currents I 11  and I 12  converge to be the bias current I 1 . Assuming that the PMOS transistor  2082  has a transconductance gmp 1 , the PMOS transistor  2084  has a transconductance gmp 2 , the NMOS transistor  2102  has a transconductance gmn 1 , the NMOS transistor  2104  has a transconductance gmn 2 , gmn 1 =gmp 2 , and gmn 2 =gmp 1 , when the differential input V −  or V +  changes, the voltage V 1  or V 2  will change accordingly, and the voltage on the node A will also change to reach a balance between the currents I 11  and I 12  and the currents I 2  and I 3 . Because gmn 1 =gmp 2  and gmn 2 =gmp 1 , when the difference between the input voltages V −  and V +  changes, the voltage variation on the node A will be a half of the variation of the differential input. 
         [0025]      FIG. 6  shows a simulation of the relationship between the output current Io and the differential input (V + −V − ) of the circuit of  FIG. 5 , in which the output current Io and the differential input (V + −V − ) have a substantially linear relationship, and the gain GM is substantially constant. 
         [0026]    In some cases, for example a load transient happens, a greater gain GM is needed to increase the response speed when the difference between the input voltages V +  and V −  is greater.  FIG. 7  shows a second embodiment for the variable current source  210 , which includes two current sources  2106  and  2108  for providing two currents I 7  and I 8  to converge to be the bias current I 1 , and a detector  2109  for detecting the input voltages V +  and V − , or the currents I 2  and I 3 , in order to control the current source  2108 . In this embodiment, the current source  2108  is enabled by the detector  2109  to produce the current I 8  to the node A only when the input voltages V +  and V −  or the currents I 2  and I 3  meet some certain conditions, for example, the difference between the input voltages V +  and V −  reaches some certain value, the difference between the currents I 2  and I 3  reaches some certain value, or one of the currents I 2  and I 3  is lower than some certain value, by which the gain GM is increased, and the current I 8  will increase with the increase of the absolute value of the difference between the input voltages V +  and V −  or the difference between the currents I 2  and I 3 . This embodiment is available for the burst gain application. 
         [0027]      FIG. 8  shows a gain performance comparison between the embodiments of the present invention and the OTA  100  of  FIG. 1 , in which curve  300  represents the relationship between the differential input (V + −V − ) and the output current Io of the OTA  200  using the circuit of  FIG. 7 , curve  302  represents the relationship between the differential input (V + −V − ) and the output current Io of the OTA  200  using the circuit of  FIG. 5 , and curve  304  represents the relationship between the differential input (V + −V − ) and the output current Io of the OTA  100  of  FIG. 1 . As shown in  FIG. 8 , the gain GM of the OTA  200  of the present invention is improved.  FIG. 9  shows an output performance comparison between the embodiments of the present invention and the OTA  100  of  FIG. 1 , in which a curve  306  represents the voltage on the output load of the OTA  200  using the circuit of  FIG. 7 , curve  308  represents the voltage on the output load of the OTA  200  using the circuit of  FIG. 5 , and curve  310  represents the voltage on the output load of the OTA  100  of  FIG. 1 . As shown in  FIG. 8 , when the load transient happens at time 20 us, the response speed of the OTA  200  of the present invention is improved. 
         [0028]      FIG. 10  shows a second embodiment OTA, which comprises a differential pair connected with a variable voltage source  402  to adjust the bias voltage V A  on the common source node A as Y+(X/2) under the control of the difference X between the input voltages V +  and V − , where Y is a constant. In this embodiment, the operational transconductance amplifier will have a stable gain GM. 
         [0029]      FIG. 11  is another embodiment, in which a variable voltage source  404  is used to control the bias voltage V A  on the common source node A of the differential pair, and a detector  406  detects the difference between the input voltages V +  and V − , the difference between the currents I 2  and I 3 , or the value of the currents I 2  and I 3 , in order to produce a signal S 2  to control the voltage source  404  to adjust the bias voltage V A . For example, when the difference between the input voltages V +  and V −  or the difference between the currents I 2  and I 3  reaches some certain value, or one of the currents I 2  and I 3  is lower than some certain value, the voltage source  404  will pulls high the bias voltage V A . This embodiment is also available for the burst gain application. 
         [0030]    While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.