Abstract:
A single-ended to differential conversion circuit for converting an input signal into a pair of differential signals is provided. An amplifier includes an inverting input terminal, a non-inverting input terminal for receiving a reference signal, and an output terminal. A first resistor is coupled between the inverting input terminal and the output terminal of the amplifier. A second resistor is coupled to the inverting input terminal of the amplifier. The third resistor is coupled to the output terminal of the amplifier. The resistor string is coupled between the output terminal of the amplifier and the second resistor, and includes a fourth resistor and a fifth resistor connected in series. A signal of the pair of differential signals is provided via the third resistor, and another signal of the pair of differential signals is provided via the resistor string.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a Continuation-In-Part of pending U.S. patent application Ser. No. 15/200,045, filed Jul. 1, 2016 and entitled “SINGLE-ENDED TO DIFFERENTIAL CONVERSION CIRCUIT AND SIGNAL PROCESSING MODULE”, which claims the benefit of Provisional Application No. 62/214,103, filed on Sep. 3, 2015, the entirety of which are incorporated by reference herein. 
    
    
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The invention relates to a single-ended to differential conversion circuit, and more particularly to a signal processing module with a single-ended to differential conversion circuit for converting an input signal into a pair of differential output signals. 
     Description of the Related Art 
     Currently, analog to digital converters (ADCs) are used widely in a variety of applications, such as medical systems, audio systems, test and measurement equipment, communication systems, and image and video systems. In recent years, the differential input ADCs have been used in instrumentation or communications systems. This is because the signal amplitude of a differential input is half that of a single-ended input. Therefore, distortion is decreased and the even-order distortion and the in-phase component noise that are generated by circuits in front of the ADC are canceled by the differential input of the ADC. Thus, it is possible to realize the properties of broad band, low noise, and low distortion. 
     Therefore, for the performance of the ADC, when the input signals are single-ended signals, it is necessary to set up in front of the ADC a signal converter that converts single-ended signals into differential signals. 
     BRIEF SUMMARY OF THE INVENTION 
     A single-ended to differential conversion circuit and a signal processing module are provided. An embodiment of a single-ended to differential conversion circuit for converting an input signal into a pair of differential signals is provided. The single-ended to differential conversion circuit comprises an amplifier, a first resistor, a second resistor, a third resistor and a resistor string. The amplifier comprises an inverting input terminal, a non-inverting input terminal for receiving a reference signal, and an output terminal. The first resistor is coupled between the inverting input terminal and the output terminal of the amplifier. The second resistor is coupled to the inverting input terminal of the amplifier, wherein the inverting input terminal of the amplifier receives the input signal via the second resistor. The third resistor is coupled to the output terminal of the amplifier. The resistor string is coupled between the output terminal of the amplifier and the second resistor, and comprises a fourth resistor and a fifth resistor connected in series. A signal of the pair of differential signals is provided via the third resistor, and another signal of the pair of differential signals is provided via the resistor string. 
     Furthermore, an embodiment of a signal processing module is provided. The signal processing module comprises a differential signal processing circuit and a single-ended to differential conversion circuit. The differential signal processing circuit providing a pair of differential output signals according to a pair of differential intermediate signals, and comprises a fully-differential amplifier. The single-ended to differential conversion circuit converts an input signal into the pair of differential intermediate signals, and comprises an amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor. The amplifier comprises an inverting input terminal, a non-inverting input terminal for receiving a reference signal, and an output terminal. The first resistor is coupled between the inverting input terminal and the output terminal of the amplifier. The second resistor is coupled to the inverting input terminal of the amplifier, wherein the inverting input terminal of the amplifier receives the input signal via the second resistor. The third resistor is coupled between the output terminal of the amplifier and a non-inverting input terminal of the fully-differential amplifier. The fourth resistor is coupled between the output terminal of the amplifier and an inverting input terminal of the fully-differential amplifier. The fifth resistor is coupled between the second resistor and the inverting input terminal of the fully-differential amplifier. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  shows a signal processing module according to an embodiment of the invention; and 
         FIG. 2  shows a signal processing module according to another embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
       FIG. 1  shows a signal processing module  100  according to an embodiment of the invention. The signal processing module  100  comprises a single-ended to differential conversion circuit  110  and a differential signal processing circuit  120 . The single-ended to differential conversion circuit  110  is capable of converting a single-ended input signal into a pair of intermediate signals (labeled as the differential current signals I CM +I SIG  and I CM −I SIG , wherein I CM  represents the DC component and I SIG  represents the AC component). In some embodiments, the pair of intermediate signals may be the voltage signals, and the single-ended to differential conversion circuit  110  is capable of converting the single-ended input signal into the voltages (e.g. the differential voltage signals V CM +V SIG  and V CM −V SIG ) corresponding to the pair of intermediate signals. The differential signal processing circuit  120  is capable of processing the pair of intermediate signals and providing a pair of differential output signals OUT P /OUT N  according to the pair of intermediate signals (e.g. I CM +I SIG  and I CM −I SIG ). For example, in some embodiments, the differential signal processing circuit  120  amplifies the pair of intermediate signals (e.g. I CM +I SIG  and I CM −I SIG ) to obtain the pair of differential output signals OUT P /OUTN. As another example, in some embodiments, the differential signal processing circuit  120  modifies the pair of intermediate signals (e.g. I CM +I SIG , I CM −I SIG ) according to a modification signal (not shown) to obtain the pair of differential output signals OUT P /OUT N . It should be noted that the operation of the differential signal processing circuit  120  is used as an example, and not to limit the invention. 
       FIG. 2  shows a signal processing module  200  according to another embodiment of the invention. The signal processing module  200  comprises a single-ended to differential conversion circuit  210  and a differential signal processing circuit  220 . The single-ended to differential conversion circuit  210  is capable of converting a single-ended input signal V CM +V IN  into a pair of differential intermediate signals. In the embodiment, the pair of differential intermediate signals are a pair of differential current signals (e.g. the current (I P1 +I P2 ) at the node n2 and the current—I N  at the node n3 in  FIG. 2 ). It should be noted that, V CM  may represent a DC voltage, and V IN  may represent an AC component containing the AC voltage. For example, when V CM =0V, V IN  can be used to represent a pure AC signal without a DC component. Of course, V IN  can also be used to represent an AC signal with a DC component. In particular, the embodiments are used as the examples, and not to limit the invention. In the embodiment, the single-ended to differential conversion circuit  210  comprises an amplifier  230  (as shown in  FIG. 2 , the amplifier  230  is a single-ended amplifier), and six resistors R 1 -R 6 . In some embodiments, the resistor R 6  could be omitted. In other words, the resistor R 6  is optional. The differential signal processing circuit  220  comprises a fully-differential amplifier  240 , and two feedback units  250  and  260 . The feedback unit  250  is coupled between an inverting input terminal and a non-inverting output terminal of the fully-differential amplifier  240 , and the feedback unit  260  is coupled between a non-inverting input terminal and an inverting output terminal of the fully-differential amplifier  240 . In some embodiments, the differential signal processing circuit  220  further comprises two input units (not shown), wherein one input unit is coupled between the inverting input terminal of the fully-differential amplifier  240  and a node n2 of the single-ended to differential conversion circuit  210  (for example, between one differential output terminal of the single-ended to differential conversion circuit  210  and the inverting input terminal of the fully-differential amplifier  240 ), and another input unit is coupled between the non-inverting input terminal of the fully-differential amplifier  240  and the resistor R 3  of the single-ended to differential conversion circuit  210  (for example, between the other differential output terminal of the single-ended to differential conversion circuit  210  and the non-inverting input terminal of the fully-differential amplifier  240 ). Thus, a gain is determined according to the input units and the feedback units  250  and  260  for the fully-differential amplifier  240 . In practice, if the fully-differential amplifier  240  is an ideal amplifier, the input voltages of its inverting input terminal and its non-inverting input terminal are equal. If the fully-differential amplifier  240  is a non-ideal amplifier, the input voltages of its inverting input terminal and its non-inverting input terminal are the differential voltages. In the embodiment, no matter whether the fully-differential amplifier  240  is an ideal amplifier, the two input currents of the fully-differential amplifier  240  are the differential currents. Therefore, in the embodiment, for the convenience of explanation, the differential intermediate signals are the differential current signals, and the fully-differential amplifier  240  is an ideal amplifier  240 . It should be noted that the specific type of the fully-differential amplifier  240  is used as an example, and not to limit the invention. The reason is that, for a particular type of fully-differential amplifier  240 , the fully-differential amplifier  240  will automatically adjust the voltages of its input terminals, such that the voltages of the input terminals can meet the objective requests of the particular type of fully-differential amplifier. In the embodiment, for the convenience of description, the voltages of two input terminals of the fully-differential amplifier  240  are maintained at the voltage V CM  (i.e. the voltage V n2  of the node n 2  and the voltage V n3  of the node n 3  are equal to the voltage V CM , e.g. V n2 =V n3 =V CM ), and it should be noted that the invention is not limited thereto. 
     In the single-ended to differential conversion circuit  210  of  FIG. 2 , the amplifier  230  has an inverting input terminal coupled to a terminal of the resistor R 1  and a terminal of the resistor R 2 , a non-inverting input terminal for receiving a reference signal V ref , and an output terminal coupled to another terminal of the resistor R 1 , a terminal of the resistor R 3 , and a terminal of the resistor R 4 . In some embodiments, the reference signal V ref  has a constant voltage value. For example, the voltage level of the reference signal V ref  is equal to that of the DC voltage V CM . For convenience of description, the reference signal V ref  is equal to that the DC voltage V CM  in the embodiment, and it should be noted that the invention is not limited to this. Because, if the voltage level of the DC voltage V CM  is not equal to that of the reference signal V ref , V can be replaced by (V CM −V ref +V IN ). Thus, based on the following embodiments, the resistance value of the resistor R 3 , and the equivalent impedance of the single-ended to differential conversion circuit  210  can be obtained accordingly. The resistor R 6  is coupled to a node n 1 , and the resistor R 6  is an input resistor for receiving the input signal V IN . The resistor R 2  is coupled between the node n 1  and the inverting input terminal of the amplifier  230 , and the inverting input terminal of the amplifier  230  can receive the input signal V IN  via the resistor R 2 . The resistor R 1  is coupled between the inverting input terminal and the output terminal of the amplifier  230 . The resistor R 3  is coupled between the output terminal of the amplifier  230  and the non-inverting input terminal of the fully-differential amplifier  240 . The resistor R 4  is coupled between the output terminal of the amplifier  230  and the node n 2 . The resistor R 5  is coupled between the node n 2  and the node n 1 . Furthermore, the resistors R 4  and R 5  form a resistor string coupled between the node n 1  and the output terminal of the amplifier  230 . In some embodiments, the resistance value of the resistor R 3  is determined according to the resistors R 1 , R 2 , R 4  and R 5 . 
     In one embodiment, the resistance (or impedance) of the resistor R 5  is R, which is a unit resistance for the single-ended to differential conversion circuit  210 . The resistance of the resistor R 6  is m×R. The resistance of the resistor R 2  is x×R. The resistance of the resistor R 1  is y×R. The resistance of the resistor R 4  is n×R. According to the resistances of the resistors R 1 , R 2 , R 4  and R 5 , the resistance of the resistor R 3  is obtained according to the following formula (1): 
     
       
         
           
             
               
                 
                   
                     R 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     3 
                   
                   = 
                   
                     
                       
                         y 
                         x 
                       
                       
                         1 
                         - 
                         
                           
                             y 
                             x 
                           
                           ⁢ 
                           
                             1 
                             n 
                           
                         
                       
                     
                     × 
                     
                       R 
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     Furthermore, according to a virtual ground concept of circuit analysis in operational amplifier, the nodes at the non-inverting input terminal and inverting input terminal of the amplifier  230 , and the nodes at the non-inverting input terminal and inverting input terminal of the fully-differential amplifier  240  are maintained at a steady reference potential (i.e. a virtual ground). Thus, a voltage V n1  at the node n 1  is obtained according to the following formula (2): 
                       V     n   ⁢           ⁢   1       =         V   CM     +     V   ⁢           ⁢   1       =       V   CM     +         x     1   +   x         m   +     x     1   +   x           ×     V   IN             ,           (   2   )               
wherein
 
     
       
         
           
             
               V 
               ⁢ 
               
                   
               
               ⁢ 
               1 
             
             + 
             
               
                 
                   x 
                   
                     1 
                     + 
                     x 
                   
                 
                 
                   m 
                   + 
                   
                     x 
                     
                       1 
                       + 
                       x 
                     
                   
                 
               
               × 
               
                 
                   V 
                   IN 
                 
                 . 
               
             
           
         
       
     
     Furthermore, according to the voltage V n1  at the node n 1 , and the resistors R 1  and R 2 , a voltage V 2  at the output terminal of the amplifier  230  is obtained according to the following formula (3): 
     
       
         
           
             
               
                 
                   
                     V 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                   = 
                   
                     
                       V 
                       CM 
                     
                     - 
                     
                       
                         y 
                         x 
                       
                       × 
                       V 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1. 
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     According to the voltages V n1 , V n2  and V 2 , the current I p1  flowing through the resistor R 5 , the current I p2  flowing through the resistor R 4 , and current I N  flowing through the resistor R 3  are respectively obtained according to the following formulas (4)-(6): 
     
       
         
           
             
               
                 
                   
                     
                       I 
                       
                         P 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                     = 
                     
                       - 
                       
                         
                           V 
                           1 
                         
                         R 
                       
                     
                   
                   ; 
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       I 
                       
                         P 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         2 
                       
                     
                     = 
                     
                       
                         
                           y 
                           x 
                         
                         × 
                         V 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                       
                         n 
                         · 
                         R 
                       
                     
                   
                   ; 
                   and 
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
             
               
                 
                   
                     I 
                     N 
                   
                   = 
                   
                     
                       
                         
                           y 
                           x 
                         
                         × 
                         V 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                       
                         
                           
                             y 
                             x 
                           
                           × 
                           R 
                         
                         
                           1 
                           - 
                           
                             
                               y 
                               x 
                             
                             · 
                             
                               1 
                               n 
                             
                           
                         
                       
                     
                     = 
                     
                       
                         
                           ( 
                           
                             1 
                             - 
                             
                               
                                 y 
                                 n 
                               
                               · 
                               
                                 1 
                                 n 
                               
                             
                           
                           ) 
                         
                         × 
                         
                           
                             V 
                             1 
                           
                           R 
                         
                       
                       = 
                       
                         - 
                         
                           
                             ( 
                             
                               
                                 I 
                                 
                                   P 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   1 
                                 
                               
                               + 
                               
                                 I 
                                 
                                   P 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   2 
                                 
                               
                             
                             ) 
                           
                           . 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
     From the formulas (4) - (6), by appropriately setting the resistance value of the resistor R 3 , the output currents of the single-ended to differential conversion circuit  210  are always a pair of differential signals based on the architecture shown in  FIG. 2 , i.e. I N =−(I P1 +I P2 ). Furthermore, by determining the relationship between the voltage/current of the inverting input terminal and the voltage/current of the non-inverting input terminal of the fully-differential amplifier  240 , a common mode or a differential mode is determined for the signal processing module  200 , so as to estimate the common mode or differential mode perturbations for the pair of intermediate signals, and then the equivalent impedance R EQ   _   P  observed at the inverting input terminal of the fully-differential amplifier  240  (in other words, observing the single-ended to differential conversion circuit  210  from the inverting input terminal of the fully-differential amplifier  240 ) and the equivalent impedance R EQ   _   N  observed at the non-inverting input terminal of the fully-differential amplifier  240  are obtained (in other words, observing the single-ended to differential conversion circuit  210  from the non-inverting input terminal of the fully-differential amplifier  240 ). In some embodiments, the equivalent impedances R EQ   _   P  and R E Q_N may be set to the same. In some embodiments, the equivalent impedances R EQ   _   P  and R EQ   _   N  are the output impedances for the single-ended to differential conversion circuit  210 . 
     In order to calculate the output impedances, the voltages V CM +V P  and V CM +V N  are applied to the output terminals of the single-ended to differential conversion circuit  210 , without receiving the single-ended input signal at its input terminal. For example, in order to calculate the common mode output impedances of the single-ended to differential conversion circuit  210 ), the voltage V CM +V P  applied to the inverting input terminal and the voltage V CM +V N  applied to the non-inverting input terminal of the fully-differential amplifier  240  are assumed to be the same, i.e. Vp=V P =V N . Furthermore, in a common mode, if the equivalent impedances R EQ   _   P  and R EQ   _   N  are equal, a current from the inverting input terminal of the fully-differential amplifier  240  to the single-ended to differential conversion circuit  210  is equal to a current from the non-inverting input terminal of the fully-differential amplifier  240  to the single-ended to differential conversion circuit  210 , i.e. I P1 +I P2 =I N . Thus, the equivalent impedances R EQ   _   P  and R EQ   _   N  are obtained according to the following formulas (7)-(8): 
                       R   EQ_P     =       1     1   +       m   ·   x       m   +   x           +       1   n     ⁢     (     1   +       y   x     ·         m   ·   x       m   +   x         1   +       m   ·   x       m   +   x               )           ;   and           (   7   )                 R   EQ_N     =         1   +       y   x     ·         m   ·   x       m   +   x         1   +       m   ·   x       m   +   x                   y   x       1   -       y   x     ·     1   n             .             (   8   )               
When
 
                 1     1   +       m   ·   x       m   +   x           +       1   n     ⁢     (     1   +       y   x     ·         m   ·   x       m   +   x         1   +       m   ·   x       m   +   x               )         =       1   +       y   x     ·         m   ·   x       m   +   x         1   +       m   ·   x       m   +   x                   y   x       1   -       y   x     ·     1   n                   
is satisfied, the equivalent impedances R EQ   _   P  and R EQ   _   N  are the same in the common mode.
 
     Correspondingly, in order to calculate the differential mode output impedances of the single-ended to differential conversion circuit  210 , the voltage V CM +V P  applied to the inverting input terminal and the voltage V CM +V N  applied to the non-inverting input terminal of the fully-differential amplifier  240  are the differential signals, e.g. V P =−V N . Furthermore, in a differential mode, if the equivalent impedances R EQ   _   P  and R EQ   _   N  are equal, a current from the single-ended to differential conversion circuit  210  to the inverting input terminal of the fully-differential amplifier  240  is equal to a current from the non-inverting input terminal of the fully-differential amplifier  240  to the single-ended to differential conversion circuit  210 , i.e. I P1 +I P2 =−I N . Thus, the equivalent impedances R EQ   _   P  and R EQ   _   N  are obtained according to the following formulas (9)-(10): 
                       R   EQ_P     =       1     1   +     m   ⁢        x           +       1   n     ⁢     (     1   +       y   x     ⁢       m   ⁢        x         1   +     m   ⁢        x               )           ;   and           (   9   )                 R   EQ_N     =         1   -       y   x     ⁢       m   ⁢        x         1   +     m   ⁢        x                   y   x       1   -       y   x     ⁢     1   n             .             (   10   )               
When
 
                 1     1   +       m   ·   x       m   +   x           +       1   n     ⁢     (     1   +       y   x     ·         m   ·   x       m   +   x         1   +       m   ·   x       m   +   x               )         =       1   -       y   x     ·         m   ·   x       m   +   x         1   +       m   ·   x       m   +   x                   y   x       1   -       y   x     ·     1   n                   
When is satisfied, the equivalent impedances R EQ   _   P  and R EQ   _   N  are the same in the differential mode.
 
     It should be noted that if the common-mode output impedances or the differential mode output impedances are respectively equal, the absolute value of the sum of the currents I 1  and I 2  is equal to the absolute value of the current I 3 , i.e. |I P1 +I P2 |=|I N |. Furthermore, according to actual application, the equivalent impedances R EQ   _   P  and R EQ   _   N  can be obtained for a common mode or a differential mode perturbation. Typically, it can not meet that the common-mode equivalent impedances and the differential-mode equivalent impedances are respectively equal. Specifically, according to actual requirements, it is possible to set that the common-mode equivalent impedances are equal or the differential-mode equivalent impedances are equal, and the invention does not make this any limitation. For example, since the circuit (e.g. the single-ended to differential conversion circuit  110 ) disposed in front of the differential signal processing circuit  120  usually has a common-mode noise, the common-mode noise can be cancelled between the two differential input terminals of the fully-differential amplifier  240  by setting the equivalent impedances R EQ   _   P  and R EQ   _   N  are the same in the common mode, thereby decreasing noise. For another example, by setting the equivalent impedances R EQ   _   P  and R EQ   _   N  are the same in the differential mode, distortion is decreased in the applications with a differential mode feedback. 
     By adding the resistor R 4  between the node n 2  and the output terminal of the amplifier  230 , only a single single-ended amplifier (i.e. the amplifier  230 ) is used in the single-ended to differential conversion circuit  210 . Thus, compared with the conventional single-ended to differential conversion circuits (e.g. using two single-ended amplifiers solution, or a fully-differential amplifier solution, and so on), the layout area and the power consumption are decreased in the single-ended to differential conversion circuit  210 . Furthermore, trade-off between the input magnitude of the single-ended input signal and the performance of the amplifier  230  can be optimized. With the introduction of the resistor R 4  (e.g. a resistance of n×R), the equivalent input is scaled by 1-1/n (n&gt; 1 ), and the non-idealities of the amplifier  230  can be cancelled to be |1/n−(1(y/x)×(1/n))/(y/x)|. For example, assuming that the resistors R 1  and R 2  are equal to the resistor R 5  (i.e. x=y=1) and the resistor R 4  is twice as big as the resistor R 5  (i.e. n=2), the noise and distortion caused by the amplifier  230  can be cancelled completely. Specifically, the noise and distortion caused by the amplifier  230  can be decreased by appropriately controlling the ratio of the resistors R 1 , R 2 , R 4  and R 5 . It should be noted that, x, y, m and n of the embodiments are not limited to an integer. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.