Abstract:
One well known problem associated with voltage controlled oscillators or VCOs is phase noise, and it is desirable to reduce phase noise in order to improve VCO performance. Here, a VCO is provided where gain elements are provided that reduce phase noise. These gain elements are generally comprised of oscillator tanks.

Description:
TECHNICAL FIELD 
       [0001]    The invention relates generally to oscillators and, more particularly, to LC oscillators with improved phase noise characteristics. 
       BACKGROUND 
       [0002]    Referring to  FIG. 1  of the drawings, the reference numeral  100  generally designates a conventional voltage controlled oscillator (VCO). The VCO  100  is generally comprised of an oscillator tank, a pair of cross-coupled NMOS FETs Q 1  and Q 2  (which operate as amplifiers having transconductances of g m ), and a current source  102 . Each of the FETs Q 1  and Q 2  has its gate coupled to the drain of the other FET Q 1  and Q 2 , and the drain of each of the FETs Q 1  and Q 2  is coupled to the oscillator tank. The oscillator tank is generally comprised of inductors L 1  and L 2  (which generally have equal values) and capacitors C 1  and C 2  (which are variable capacitors). 
         [0003]    In operation, VCO  100  is able to generate an output signal with a frequency that is generally proportional the current through current source  102  and the output resistance. The phase noise would, thus, be as follows: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       P 
                        
                       
                           
                       
                        
                       N 
                     
                     = 
                     
                       
                         
                           
                             
                               i 
                               2 
                             
                             _ 
                           
                            
                           
                             R 
                             P 
                             2 
                           
                         
                         
                           2 
                            
                           
                             V 
                             OUT 
                             2 
                           
                         
                       
                        
                       
                         
                           ( 
                           
                             
                               ω 
                               0 
                             
                             
                               2 
                                
                               
                                 Q 
                                 0 
                               
                                
                               Δ 
                                
                               
                                   
                               
                                
                               
                                 ω 
                                 0 
                               
                             
                           
                           ) 
                         
                         2 
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where  i 2    is the equivalent output current noise, Q 0  is the loaded quality factor, R P  is the output resistance, and V OUT  is the output voltage. Specifically, for a steady state oscillation, the average transconductance (g m ) is approximately equal to the inverse of resistance R P  (g m =1/R P ). Under these steady state conditions, equivalent output current noise  i 2    is as follows: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         i 
                         2 
                       
                       _ 
                     
                     = 
                     
                       
                         
                           
                             4 
                              
                             kT 
                           
                           
                             R 
                             p 
                           
                         
                         + 
                         
                           4 
                            
                           kT 
                            
                           
                               
                           
                            
                           γ 
                            
                           
                               
                           
                            
                           
                             g 
                             m 
                           
                         
                       
                       = 
                       
                         
                           4 
                            
                           
                             kT 
                              
                             
                               ( 
                               
                                 1 
                                 + 
                                 γ 
                               
                               ) 
                             
                           
                         
                         
                           R 
                           p 
                         
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where the first term corresponds to tank resistance and the second term corresponds to the active device. By substituting Equation (2) into Equation (1), the phase noise PN can be represented as follows: 
         [0000]    
       
         
           
             
               
                 
                   
                     P 
                      
                     
                         
                     
                      
                     N 
                   
                   = 
                   
                     
                       
                         
                           4 
                            
                           
                             kT 
                              
                             
                               ( 
                               
                                 1 
                                 + 
                                 γ 
                               
                               ) 
                             
                           
                            
                           
                             R 
                             p 
                           
                         
                         
                           2 
                            
                           
                             V 
                             OUT 
                             2 
                           
                         
                       
                        
                       
                         
                           ( 
                           
                             
                               ω 
                               0 
                             
                             
                               2 
                                
                               
                                 Q 
                                 0 
                               
                                
                               Δ 
                                
                               
                                   
                               
                                
                               
                                 ω 
                                 0 
                               
                             
                           
                           ) 
                         
                         2 
                       
                     
                     = 
                     
                       
                         
                           4 
                            
                           
                             kT 
                              
                             
                               ( 
                               
                                 1 
                                 + 
                                 γ 
                               
                               ) 
                             
                           
                            
                           
                             R 
                             p 
                           
                         
                         
                           2 
                            
                           
                             
                               ( 
                               
                                 
                                   kI 
                                   AVE 
                                 
                                  
                                 
                                   R 
                                   p 
                                 
                               
                               ) 
                             
                             2 
                           
                         
                       
                        
                       
                         
                           
                             ( 
                             
                               
                                 ω 
                                 0 
                               
                               
                                 2 
                                  
                                 
                                   Q 
                                   0 
                                 
                                  
                                 Δ 
                                  
                                 
                                     
                                 
                                  
                                 
                                   ω 
                                   0 
                                 
                               
                             
                             ) 
                           
                           2 
                         
                         . 
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0000]    Thus, it can be seen from this conventional VCO  100  that that improving the phase noise characteristics can be accomplished through increasing the quality factor Q of the oscillator tank or optimization of related device properties in the VCO  100 . 
         [0004]    Some examples of conventional circuits are: U.S. Patent Pre-Grant Publ. No. 2008/0143446; U.S. Patent Pre-Grant Publ. No. 2008/0150644; and Hegazi et al., “A filtering technique to lower LC oscillator phase noise,”  IEEE Journal of Solid State Circuits,  Vol. 36, No. 12, December 2001. 
       SUMMARY 
       [0005]    A preferred embodiment of the present invention, accordingly, provides an apparatus. The apparatus comprises a voltage source; a first node; a second node; an oscillator tank including: an inductive network that is coupled to the voltage source, the first node, and the second node; and a capacitive network that is coupled to the first node and the second node; a first transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode is coupled to the first node; a first gain element that is coupled between the second node and the control electrode of the first transistor; a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode is coupled to the second node; and a second gain element that is coupled between the first node and the control electrode of the second transistor. 
         [0006]    In accordance with a preferred embodiment of the present invention, the first gain element further comprises a second oscillator tank coupled between the gate of the first transistor and the second node. 
         [0007]    In accordance with a preferred embodiment of the present invention, the first gain element further comprises a third oscillator tank coupled between the gate of the second transistor and the first node. 
         [0008]    In accordance with a preferred embodiment of the present invention, each of the second and third oscillator tanks further comprise: an inductor; and a first capacitor coupled in parallel to the inductor; and a second capacitor that is coupled to the inductor and the first capacitor. 
         [0009]    In accordance with a preferred embodiment of the present invention, the inductive network further comprises: a first inductor having a first and a second terminal, wherein the first terminal of the first inductor is coupled to the first node, and wherein the second terminal of the second inductor is coupled to the voltage source; and a second inductor having a first and a second terminal, wherein the first terminal of the second inductor is coupled to the second node, and wherein the second terminal of the second inductor is coupled to the voltage source. 
         [0010]    In accordance with a preferred embodiment of the present invention, the capacitive network further comprises: a first variable capacitor that is coupled to the first node and a third node; a second variable capacitor that is coupled to the second node and the third node, wherein a tuning voltage is applied to the third node. 
         [0011]    In accordance with a preferred embodiment of the present invention, the first and second transistors further comprise first and second NMOS transistors. 
         [0012]    In accordance with a preferred embodiment of the present invention, an apparatus is provided. The apparatus comprises a phase/frequency detector (PFD) that receives a reference signal; a charge pump that is coupled to the PFD; a filter that is coupled to the charge pump; a voltage controlled oscillator (VCO) that is coupled to the filter and that generates an output signal, the VCO including: a voltage source; a first node; a second node; an oscillator tank including: an inductive network that is coupled to the voltage source, the first node, and the second node; and a capacitive network that is coupled to the first node and the second node; a first transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode is coupled to the first node; a first gain element that is coupled between the second node and the control electrode of the first transistor; a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode is coupled to the second node; and a second gain element that is coupled between the first node and the control electrode of the second transistor; and a feedback circuit that is coupled to the VCO and to the PFD. 
         [0013]    In accordance with a preferred embodiment of the present invention, the feedback circuit further comprises: a prescaler that is coupled to the VCO; and a divider that is coupled between the prescaler and the PFD. 
         [0014]    In accordance with a preferred embodiment of the present invention, an apparatus is provided. The apparatus comprises a voltage source; a first node; a second node; a first oscillator tank having: a first inductor having a first and a second terminal, wherein the first terminal of the first inductor is coupled to the first node, and wherein the second terminal of the second inductor is coupled to the voltage source; and a second inductor having a first and a second terminal, wherein the first terminal of the second inductor is coupled to the second node, and wherein the second terminal of the second inductor is coupled to the voltage source; and a capacitive network that is coupled to the first node and the second node; a first NMOS transistor that is coupled to the first node at its drain; a second NMOS transistor that is coupled to the second node; a current source that is coupled to the sources of each of the first and second NMOS transistors; a second oscillator tank having: a third inductor that is coupled to the second node and to the gate of the first NMOS transistor; a first capacitor that is coupled to the second node and to the gate of the first NMOS transistors; and a second capacitor that is coupled to the coupled to the gate of the first NMOS transistor and that receives a generally constant voltage; and a third oscillator tank having: a fourth inductor that is coupled to the second node and to the gate of the second NMOS transistor; a third capacitor that is coupled to the second node and to the gate of the second NMOS transistors; and a fourth capacitor that is coupled to the coupled to the gate of the second NMOS transistor and that receives the generally constant voltage. 
         [0015]    In accordance with a preferred embodiment of the present invention, the second and fourth capacitors are each coupled to the voltage source so as to receive the generally constant voltage. 
         [0016]    The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]    For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
           [0018]      FIG. 1  is an example of a convention VCO; 
           [0019]      FIG. 2  is an example of circuit diagram for a phase locked loop (PLL) in accordance with a preferred embodiment of the present invention; and 
           [0020]      FIG. 3  is an example of circuit diagrams for the VCO of  FIG. 2 . 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    Refer now to the drawings wherein depicted elements are, for the sake of clarity, not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views. 
         [0022]    Referring to  FIG. 2  of the drawings, the reference numeral  200  generally designates a phase lock loop (PLL) in accordance with an embodiment of the invention. The PLL  200  is generally comprised of a phase/frequency detector (PFD)  202 , a charge pump  204 , a low pass filter (LPF)  206 , a voltage controlled oscillator (VCO)  400 , a prescaler  208 , and a divider  210 . 
         [0023]    This PLL  200  operates to generally create an output signal V OUT  based on an input reference signal V REF . The typical application for a PLL, such as PLL  200 , would be for the generation of a local clock signal from a system clock signal. To accomplish this, the PFD  202  receives a feedback signal and a reference signal V REF , and provides a signal to the charge pump  204  based on a comparison of the feedback signal and the reference signal V REF . The output of the charge pump  204  is filtered by the LPF  204  and input into the VCO  400 , where an output signal is generated that has a frequency that is proportional to the input voltage. The output signal from the VCO  400  is then prescaled to generate the output signal V OUT , which is further divided by the divider  210  to generate the feedback signal for the PFD  202 . 
         [0024]    Turning to  FIG. 3 , VCO  400  can be seen in greater detail. As with the VCO  100  of  FIG. 1 , the VCO  400  is generally comprised of an oscillator tank  402  and a pair of cross-coupled FETs Q 3  and Q 4  (which operate as transconductance amplifiers). One difference between VCO  100  and VCO  400  is the use of two additional tanks  422  and  424 , which are discussed in further detail below. Additionally, the oscillator tank  402  can be subdivided into several components: an inductive network  404  and the capacitive network  406 . 
         [0025]    The inductive network  404  is generally comprised of a single inductive branch. This inductive branch includes two inductors L 3  and L 4  (which preferably have the same value) coupled in series to one another between nodes N 1  and N 2 . An input voltage V DD  is also provided to the node between the inductors L 3  and L 4  to generally provide additional power to the VCO  400 . Alternatively, the two inductors L 3  and L 4  can be replaced with a signal inductor with the input voltage being input into a center tap. 
         [0026]    The capacitive network  406  is generally comprised of several fixed capacitance branches and a variable capacitance branch; however, for the sake of simplicity as shown in  FIG. 3 , the capacitive network  406  can be represented two capacitors C 3  and C 4  (which are preferably variable capacitors). In this configuration, capacitors C 3  and C 4  are coupled in series with one another between nodes N 1  and N 2  with a variable voltage V TUNE  being received at the node between the capacitors C 3  and C 4 , which allows for adjustment of the impedance of the oscillator tank  402  so as to adjust the frequency of the VCO  400 . 
         [0027]    Coupled the oscillator tank  402  at nodes N 1  and N 2  are FETs Q 3  and Q 4  at their respective drains. Preferably, each of these FETs Q 3  and Q 4  is an NMOS FET. Each of FETs Q 3  and Q 4  is cross-coupled to nodes N 2  and N 1  at its respective gate with oscillator tanks  422  and  424  interposed therebetween, and each of FETs Q 3  and Q 4  is coupled to current source I DC  at its respective source. As can be seen in  FIG. 3 , oscillator tanks  422  and  424  are generally comprised of inductors L 5  and L 6  (respectively) and capacitors C 5  and C 6  (respectively). Preferably, the values of inductors L 5  and L 6  are the same while the values of capacitors C 5  and C 6  are also preferably the same. Additionally, capacitors C 7  and C 8  are coupled in series between the gates of transistors Q 3  and Q 4  with voltage VB (which is preferably input voltage V DD  or ground) applied to the node between capacitors C 7  and C 8 . There is also a parasitic resistance R PAR  within each oscillator tank  422  and  424 , as shown in  FIG. 3 . Collectively, each of the oscillator tanks  422  and  424  (along with capacitors C 8  and C 7 , respectively) operate as gain elements with a gain K. 
         [0028]    By implementing these oscillator tanks  422  and  424 , the drain noise of each FET Q 3  and Q 4  can be reduced by 1/K, where K is the gain of oscillator tanks  422  and  424 . This results in the following equivalent output current noise  i 2   : 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         i 
                         2 
                       
                       _ 
                     
                     = 
                     
                       
                         
                           
                             4 
                              
                             kT 
                           
                           
                             R 
                             p 
                           
                         
                         + 
                         
                           4 
                            
                           kT 
                            
                           
                               
                           
                            
                           γ 
                            
                           
                             1 
                             
                               KR 
                               p 
                             
                           
                         
                       
                       = 
                       
                         
                           
                             4 
                              
                             kT 
                           
                           
                             R 
                             p 
                           
                         
                          
                         
                           ( 
                           
                             1 
                             + 
                             
                               γ 
                               K 
                             
                           
                           ) 
                         
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
         [0000]    and a phase noise of: 
         [0000]    
       
         
           
             
               
                 
                   
                     P 
                      
                     
                         
                     
                      
                     N 
                   
                   = 
                   
                     
                       
                         4 
                          
                         
                           kT 
                            
                           
                             ( 
                             
                               1 
                               + 
                               
                                 γ 
                                 K 
                               
                             
                             ) 
                           
                         
                          
                         
                           R 
                           p 
                         
                       
                       
                         2 
                          
                         
                           V 
                           OUT 
                           2 
                         
                       
                     
                      
                     
                       
                         
                           ( 
                           
                             
                               ω 
                               0 
                             
                             
                               2 
                                
                               
                                 Q 
                                 0 
                               
                                
                               Δ 
                                
                               
                                   
                               
                                
                               
                                 ω 
                                 0 
                               
                             
                           
                           ) 
                         
                         2 
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0000]    Thus, because the drain noise is usually the dominant noise source in the overall output noise, the reduction in the drain noise can decrease the phase noise directly. 
         [0029]    Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.