Abstract:
A plasma display panel having a plurality of first electrodes and a driver for applying scan signals to the first electrodes in order, the driver having a plurality of selection circuit groups, each selection circuit group having a plurality of selection circuits. Driving signals are applied to the first electrodes through the output ends of selection circuits in one selection circuit group, the output ends being connected in parallel.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims priority to and the benefit of Korea Patent Application No. 10-2003-0079094 filed on Nov. 10, 2003 in the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     (a) Field of the Invention  
         [0003]     The present invention relates to a plasma display panel (PDP). More particularly, the present invention relates to a driving circuit of the PDP.  
         [0004]     (b) Description of the Related Art  
         [0005]     Recently, PDPs have been highlighted among flat display devices due to high brightness, emission efficiency, and wide viewing angle. The PDP is a flat display device for displaying characters or images using plasma caused by gas discharge, and several tens to several millions of pixels are arranged in a matrix format on the PDP according to the PDP size.  
         [0006]      FIG. 1  is a partial perspective view of a PDP.  FIG. 2  shows an arrangement of electrodes in the PDP. As shown in  FIG. 1 , the PDP includes two glass substrates  1 ,  6  which are arranged in a face-to-face relationship. On first substrate  1 , pairs of scan electrode  4  and sustain electrode  5 , which are covered with dielectric layer  2  and protective layer  3 , are arranged in parallel. On second substrate  6 , a plurality of address electrodes  8 , which are covered with insulating layer  7 , are arranged. Barrier ribs  9  are formed in parallel with address electrodes  8  on insulating layer  7 . Fluorescent material  10  is formed on the surface of insulating layer  7  and on both sides of barrier ribs  9 . Glass substrates  1 ,  6  are arranged in a face-to-face relationship with discharge space  11  formed therebetween, such that scan electrodes  4  and sustain electrodes  5  lie in a direction perpendicular to address electrodes  8 . Discharge space  11  at intersections of address electrodes  8  and the pairs of scan electrode  4  and sustain electrode  5  forms discharge cells  12 .  
         [0007]     As shown in  FIG. 2 , the PDP has a pixel matrix in an m×n matrix format. A plurality of address electrodes A 1  to A m  are arranged in a column direction, and a plurality of scan electrodes Y 1  to Y n  and a plurality of sustain electrodes X 1  to X n  are alternately arranged in a row direction.  
         [0008]     Generally, in the PDP one frame is divided into a plurality of subfields, and is driven. Grays of the PDP can be expressed by a combination of the subfields, and generally, each subfield includes a reset period, an address period, and a sustain period. The reset period is a period for erasing wall charges that have been formed by a previous sustain discharge, and setting up a new wall charge in order to stably perform a next address discharge. The address period is a period for selecting cells being turned on and cells being turned off, and accumulating a wall charge on cells being turned on (addressed cell). The sustain period is a period for performing a sustain discharge to display a video image on an addressed cell. Here, “wall charge” means a charge that is formed on a wall close to each electrode of the discharge cell and is accumulated on the electrode. The wall charge is described as being “formed” or “accumulated” on the electrode, although the wall charge does not actually contact the electrodes. Further, “wall voltage” means a potential difference formed on the wall of the discharge cell by the wall charge.  
         [0009]     An address operation of the PDP is performed by the operation of a scan IC and an address IC, which include a plurality of selection circuits having two switches connected serially. Further, the output of the scan selection circuit corresponds to the scan electrode (Y electrode) and the output of the address selection circuit corresponds to the address electrode. Generally, one driver IC includes a plurality of selection circuits. However, hereinafter one driver IC is understood to include one selection circuit for convenience.  
         [0010]      FIG. 3  shows a connection diagram of a scan IC and a Y electrode according to a conventional circuit. As shown in  FIG. 3 , the output of SCAN IC  1  is coupled to scan electrode Y 1 , and the output of SCAN IC 2  is coupled to scan electrode Y 2 .  
         [0011]     Because the size of panels has gradually been enlarged in recent years, the requirement for capacity of the circuit elements has also gradually increased. Thus, the capacity of a driver IC (scan IC and address IC) also needs to be increased. In particular, a driver IC that is capable of dealing with a large quantity of current is required, since the driving current for a 70 inch grade PDP is three times greater than the driving current for a 40 inch grade PDP. However, the production amount of the large sized PDP is smaller than that of the 40 inch grade PDP, thus the development of an exclusive driver IC for the large size PDP is not advantageous with regard to cost.  
       SUMMARY OF THE INVENTION  
       [0012]     In accordance with the present invention, a driving circuit of a plasma display panel for driving a large PDP by using a small capacity driver IC is provided.  
         [0013]     In one aspect of the present invention a plasma display panel is provided including: a panel having a plurality of first electrodes; and a driver for applying scan signals to the first electrodes in order, the driver having a plurality of selection circuit groups, each selection circuit group being composed of a plurality of selection circuits. The scan signals are applied to the first electrodes through output ends of the selection circuits in one selection circuit group, the output ends being connected in parallel.  
         [0014]     Each selection circuit may include a first switch coupled to a first power source supplying power corresponding to the scan signals, and a second switch coupled to a second power source; and driving signals are applied to the first electrode when the first switches of each selection circuit in one selection circuit group are turned on at the same time and the second switches are turned off at the same time.  
         [0015]     Further, the outputs of the selection circuits may be floated by turning off all switches of a plurality of selection circuit groups during a predetermined time, before a next driving signal is applied to a plurality of the first electrodes; when the driving signals are applied to a plurality of the first electrodes in order.  
         [0016]     In addition, the outputs of the selection circuits may be floated by turning off all switches of a selection circuit group for applying a previous driving signal and a selection circuit group for applying a next driving signal during a predetermined time, before the next driving signal is applied to a plurality of the first electrodes, when driving signals are applied a to plurality of the first electrodes in order.  
         [0017]     In exemplary embodiments the first electrodes are scan electrodes or address electrodes.  
         [0018]     In accordance with another aspect of the present invention a driving method of a plasma display panel having a plurality of first electrodes and a driver for applying a driving signal to a plurality of first electrodes is provided, wherein the drive has a plurality of selection circuit groups, each selection circuit group being composed of a plurality of selection circuits. The driving method includes: applying a driving signal to one first electrode through outputs of a plurality of selection circuits in one selection circuit group being connected in parallel, wherein the application of the driving signal to the one first electrode is performed in order for a plurality of first electrodes; floating outputs of the selection circuits in a first selection circuit group for outputting a previous driving signal and a second selection circuit group for outputting a next driving signal during a predetermined time, before the next driving signal is applied to a plurality of the first electrodes.  
         [0019]     Here, the driving method of the plasma display panel may float the outputs of all selection circuits in a plurality of selection circuits during the predetermined time. Further, the driving method of the plasma display panel operates the selection circuits in the selection circuit groups normally except for the first and the second selection circuit groups.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]      FIG. 1  is a partial perspective view of a PDP.  
         [0021]      FIG. 2  shows an arrangement of electrodes in the PDP of  FIG. 1 .  
         [0022]      FIG. 3  shows a schematic diagram of a conventional scan IC and scan electrode connection.  
         [0023]      FIG. 4  shows a plasma display panel according to an exemplary embodiment of the present invention.  
         [0024]      FIG. 5  shows a schematic diagram of a scan IC and a scan electrode according to an exemplary embodiment of the present invention.  
         [0025]      FIG. 6  shows a waveform being input to a scan electrode according to a driving method of a scan IC of an exemplary embodiment of the present invention.  
         [0026]      FIG. 7  shows a waveform being input to a scan electrode according to a driving method of a scan IC of another exemplary embodiment of the present invention.  
         [0027]      FIG. 8  shows a schematic diagram of a address IC and a address electrode according to an exemplary embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0028]     Referring now to  FIG. 4 , the plasma display panel device includes plasma display panel  100 , address driver  200 , Y electrode driver  300 , X electrode driver  300 , and controller  400 .  
         [0029]     Plasma display panel  100  includes a plurality of address electrodes A 1  to A m  extended in a row direction, and a plurality of pairs of first electrodes (hereinafter “Y electrode”) Y 1  to Y n  and second electrodes (hereinafter “X electrode”) X 1  to X n  extended in a column direction.  
         [0030]     Address driver  200  receives address driving control signal S A  from controller  400 , and applies a data signal for display to each address electrode A 1  to A m  to select a discharge cell that is to be displayed.  
         [0031]     Y electrode driver  320  receives Y electrode driving signal S Y  from controller  400  and applies the data signal to the Y electrode. X electrode driver  340  receives X electrode driving signal S X  from controller  400  and applies the data signal to the X electrode.  
         [0032]     Controller  400  receives a video signal externally, and generates address driving control signal S A , Y electrode driving signal S Y , and X electrode driving signal S X , and transfers each signal to address driver  200 , Y electrode driver  320 , and X electrode driver  340 , respectively.  
         [0033]      FIG. 5  shows a connection diagram of a selection circuit in a scan IC and a Y electrode which are included in Y electrode driver  320  according to a first exemplary embodiment of the present invention. As shown in  FIG. 5 , Y electrode driver  320  includes two selection circuits SC 1 , SC 3 , of which outputs are connected in parallel to one Y electrode Y 1 . In the same manner, the outputs of two selection circuits SC 2 , SC 4  are connected in parallel to one Y electrode Y 2 . When a scan voltage is applied to the Y electrode though the above circuit, an on/off operation of switches M 11 , M 31  is performed at the same time, and an on/off operation of switches M 12 , M 32  is performed at the same time. Then, the current at the switches can be reduced by 50%, since the two switches are connected in parallel.  
         [0034]     Further, although the same model of switches may be used for the scan IC selection circuit, the on/off switching time for each switch may be slightly different, thus it is possible for the switch being turned on and the switch being turned off to be on at the same time.  
         [0035]     For example, in  FIG. 5 , the output of Y electrode Y 1  is changed from low to high, and the output of Y electrode Y 2  is changed from high to low, when a scan pulse is applied to Y electrode Y 1  and then is applied to Y electrode Y 2 . Thus, switches M 12  and M 32  are changed from on state to off state, and switches M 11 , M 31  are changed from an off state to an on state. Further, switches M 21 , M 41  are changed from an on state to an off state, and switches M 22 , M 42  are changed from an off state to an on state.  
         [0036]     Further, the switch timing of switches M 31 , M 32  is faster than the switch timing of switches M 11 , M 12 . Thus, switch M 31  can be turned off and switch M 32  can be turned on, before switch M 11  is turned off and switch M 12  is turned on, when the scan pulse is applied to Y electrode Y 1 . In the same manner, switch M 11  can be turned on and switch M 12  can be turned off, before switch M 31  is turned on and switch M 32  is turned off, when the scan pulse is applied to Y electrode Y 2 . Then, switches M 11 , M 32  are turned on at the same time, or switches M 12 , M 31  are turned on at the same time, so that the circuit is short circuited. Thus, the selection circuit cannot output a desired waveform to electrodes Y 1 , Y 2 .  
         [0037]     To solve the problem, the present invention provides a method wherein the outputs of all selection circuits are floated by allowing the outputs of all selection circuits to be at high impedance states, and then applying a scan pulse to the scan electrode when the scan pulse is applied to the scan electrode. Then, all switches are in an off state while the outputs of the selection circuits maintain high impedance states. Thus, a short circuit due to switch timing can be prevented.  
         [0038]      FIG. 6  shows a waveform being input to scan electrodes (Y 1 , Y 2 , Y 3  . . . ) according to a driving method of a selection circuit of the first exemplary embodiment of the present invention. The dotted line of  FIG. 6  indicates that the output of the selection circuit is at a high impedance state, and the output voltage is floated.  
         [0039]     The first exemplary embodiment discloses an example in which outputs of all selection circuits are in a high impedance state whenever the scan pulse is applied to the scan electrode. Otherwise, only the output of the selection circuit connected to the scan electrode of which voltage is changed can be in the high impedance state.  
         [0040]      FIG. 7  shows a waveform being input to the scan electrodes (Y 1 , Y 2 , Y 3  . . . ) by a driving method of a scan circuit according to a second exemplary embodiment of the present invention. As shown in  FIG. 7 , the outputs of the selection circuits for driving Y electrodes Y 1 , Y 2  are made to be in a high impedance state for a predetermined time, when the scan pulse is applied to Y electrode Y 1  but the scan pulse is not applied to Y electrode Y 2 . At this time, the voltages of Y electrodes Y 1 , Y 2  are floated. At this time, the output of the selection circuit for driving Y electrode Y 3  is maintained at the normal state, since the voltage variation does not occur at Y electrode Y 3 .  
         [0041]     In the same manner, the outputs of the selection circuits for driving Y electrodes Y 2 , Y 3  are made to be in high impedance state for a predetermined time, when the scan pulse is applied to Y electrode Y 2  but the scan pulse is not applied to Y electrode Y 3 . At this time, the voltages of Y electrodes Y 2 , Y 3  are floated. Also at this time, the output of the selection circuit for driving Y electrode Y 1  is maintained at the normal state, since the voltage variation does not occur at Y electrode Y 1 .  
         [0042]     The first and second exemplary embodiments disclose the selection circuit in the scan IC and scan electrode (Y electrode). However, the present invention can be also applied to the selection circuit in the address IC and address electrode.  FIG. 8  shows a connection diagram of a selection circuit in a address IC and a address electrode according to a first and second exemplary embodiment of the present invention.  
         [0043]     Further, the first and second exemplary embodiments disclose that two selection circuits are connected in parallel to drive one electrode. However, at least three selection circuits can also be connected in parallel to drive one electrode.  
         [0044]     As described above, the present invention connects two selection circuits in parallel to increase a driving current and a power capacity, and drives one scan electrode or address electrode. Thus, the present invention can drive a large PDP by using small capacity drivers which are used for driving small PDPs.  
         [0045]     While this invention has been described in connection with what is presently considered to be practical embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.