Abstract:
A method to fill a valley on a substrate comprises depositing a first material onto the substrate using a chemical vapor deposition process to partially fill the valley and depositing a second material onto the substrate using a spin-on deposition process to completely fill the valley. The chemical vapor deposition process may comprise a high-density plasma chemical vapor deposition process or a low-pressure chemical vapor deposition process. The method may further comprise depositing a sacrificial layer, performing a first curing process on the first and second materials, polishing at least the sacrificial layer to remove at least a portion of the second material, and performing a second curing process on the first and second materials.

Description:
BACKGROUND  
       [0001]     As the semiconductor manufacturing industry moves towards smaller feature sizes, the size and aspect ratio for trenches and vias used in shallow trench isolation (STI), pre-metal dielectric, and other isolation structures provides more challenges. Newer devices are being built using 90-nanometer (nm) or sub-90 nm processes, and STI trenches for these devices often have aspect ratios of 4.5:1 and higher. At these smaller sizes, the use of conventional gap-filling deposition processes, as described below, leads to a greater incidence of problems such as voids or cracking in trenches and vias. Other problems also increase, such as poor insulation due to low quality dielectric material being present within trenches and vias after gap fill, and the creation of large topographical surface variations post chemical vapor deposition which may pose great problems for subsequent chemical mechanical planarization (CMP) processes.  
         [0002]     Plasma enhanced chemical vapor deposition (PECVD) is one commonly used technique in which one or more gaseous reactors are used to form a solid insulating or conducting layer on the surface of a substrate enhanced by the use of plasma. This process is advantageous because it may be used at lower temperatures. In general, PECVD enables gap fill with aspect ratios up to 3:1 to be filled. One drawback is that multiple PECVD/sputter sequential processes need to be carried out to completely fill a gap with a high aspect ratio. Even after multiple process sequences, the processes still tend to leave voids or seams in the trenches and the quality of the PECVD fill is still inferior to another deposition technique, known as high-density plasma chemical vapor deposition (HDPCVD). This process uses a higher density plasma and is known to fill gaps with aspect ratios of around 4.5:1. In some cases, the addition of species such as Helium, Hydrogen, NF 3 , and SiF 4  to the deposition chemistry may be used to improve gap fill capabilities for aspect ratios up to 6:1. Gaps with higher aspect ratios, however, may not adequately be filled using HDPCVD.  
         [0003]     Other techniques for filling gaps are low pressure chemical vapor deposition (LPCVD) and sub-atmospheric chemical vapor deposition (SACVD), both of which are performed in a vacuum environment. These processes use the chemical reaction of gaseous compounds to provide a conformal deposition. Gap fill isolation using LPCVD or SACVD is a single step, highly conformal deposition. Gaps with aspect ratios as high as 5:1 or more may be filled with this process, however, weak seams often develop in the middle of the filled valley, resulting in device failure.  
         [0004]     Spin-on dielectrics (SOD) using silicon derivatives as a stand-alone process may be used for gap fill isolation, and have been known to fill gaps with aspect ratios as high as 10:1. The problem with SODs, however, is that the gap fill materials derived from SOD tend to have poor electrical or mechanical properties due to heterogeneous densification, high shrinkage, and incomplete oxidation. Cracking or low quality dielectric material being present within trenches and vias after gap-filling using SOD is common. Another technique that has been used is an SOD deposition followed by one of the chemical vapor deposition (CVD) processes described above. The SOD process improves the aspect ratio of the gap and the subsequent CVD process fills the gap. This technique is not suitable for sub-90 nm applications because as device dimensions decrease, the low quality SOD materials may not provide adequate electrical insulation for the smaller devices and electrical field breakdowns and leakage tend to occur.  
         [0005]     Accordingly, improved deposition processes are needed to provide higher quality gap fill isolation for smaller devices, such as devices built using 90 nm and sub-90 nm ultra large scale integration (ULSI) processes.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]      FIG. 1  is a semiconductor wafer with high-aspect ratio structures.  
         [0007]      FIGS. 2A  to  2 C demonstrate an HDP-SOD gap fill isolation process in accordance with the invention.  
         [0008]      FIGS. 3A  to  3 C demonstrate a CVD-SOD gap fill isolation process in accordance with the invention.  
     
    
     DETAILED DESCRIPTION  
       [0009]     Implementations of a method to practice a sequential chemical vapor deposition (CVD) process and spin-on dielectric (SOD) process are described herein. In the following description numerous specific details are set forth to provide a thorough understanding of the implementations. One skilled in the relevant art will recognize, however, that the techniques described herein may be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.  
         [0010]     The sequential CVD-SOD process of the invention may be used in semiconductor wafer manufacturing. In one implementation the CVD-SOD process may be used to fill high-aspect ratio valleys found on a surface of a semiconductor wafer or other substrate. As used herein, the term “valley” may refer to any gaps, trenches, vias, or other voids found on the surface of the semiconductor wafer. The valleys may be found between or around active areas on the semiconductor wafer, and the gap fill isolation process electrically isolates these active areas. The invention may be applicable to, but not limited to, shallow trench isolation, pre-metal dielectric, or inter-metal dielectric deposition processes. In implementations of the invention, the CVD-SOD process may fill gaps with aspect ratios of 7:1 and higher, and gap widths of 50 nm and below.  
         [0011]      FIG. 1  illustrates a substrate  100 , such as a portion of a semiconductor wafer, having several structures  102  that may be used in forming active areas. These active areas include, but are not limited to, devices such as transistors and electrical interconnections. Between the structures  102  are valleys  104 . The valleys  104  include any gaps, trenches, vias, or other voids that exist between structures  102 , and may also include gaps within the substrate  100  itself. Each valley  104  includes a trench opening  106 . In  FIG. 1 , the aspect ratio of each valley  104  is approximately 7:1. Therefore, the depth of each valley  104  is approximately seven times the width of the valley  104 . The width of each valley  104  is often the same as the width of trench opening  106 .  
         [0012]     In accordance with implementations of the invention, the valleys  104  may be filled using a sequential HDPCVD-SOD process.  FIG. 2A  shows a first step of this process where an HDPCVD deposition process is carried out on the substrate  100  and the structures  102 . The HDPCVD process deposits a high quality oxide  200  into the valleys  104  for good electrical isolation. The process provides a high bottom-to-side coverage ratio so that more of the oxide  200  may be deposited at the bottom of the valleys  104  than on the sides of the structures  102 . The HDPCVD process shown in  FIG. 2A  reduces the aspect ratio of the valley  104  and provides each partially-filled valley  104  with a relatively larger opening towards the surface. The initial HDPCVD process also deposits a high-quality oxide  200  at the critical interfaces. For example, in shallow trench applications, the initial HDPCVD process provides robust electrical isolation at trench corners and sidewalls.  
         [0013]     If used alone, the HDP deposition generally leads to voids and may not adequately handle valleys  104  with high aspect ratios. Therefore, in accordance with the invention,  FIG. 2B  illustrates a second step of the sequential process involving an SOD deposition. After the oxide  200  has been deposited by the HDPCVD process, an SOD process may be carried out to fill the valleys  104  with a dielectric material  202 . The spin-on process substantially completes the filling of the valleys  104  with dielectric material  202  so that the overall fill is void-free. Within each valley  104 , the SOD dielectric material  202  sits atop the oxide  200 .  
         [0014]     The spin-on process used to deposit the dielectric material  202  may be self-planarizing; accordingly, the dielectric material  202  may have a top surface that is substantially planarized. Furthermore, in some implementations the SOD process may leave a sacrificial layer of dielectric material  202  over the structures  102  for optimal chemical mechanical polishing (CMP). The sacrificial layer may be polished by the CMP process until a thin layer of the sacrificial layer remains atop the oxide  200 , or until at least a portion of the oxide  200  is exposed.  
         [0015]     The addition of the SOD deposition may provide void-free trench-fill after the initial HDP deposition because the SOD deposition has gap fill capability that is less sensitive to trench profiles such as reentrant trench sidewalls. In addition, the self-planarizing nature of the SOD deposition enables high within-die thickness uniformity for optimized pre and post CMP uniformity. In an implementation of the invention, the sequential process described herein may be capable of providing a gap fill capability exceeding a 7:1 aspect ratio with gap space of 50 nm or less, and optimal planarized topography to enable better CMP process control.  
         [0016]     After the SOD process, in an implementation of the invention a thermal curing process may be carried out. The thermal curing process may be used for cross-linking, oxidation, and densification of the SOD. During the thermal curing process, organic compounds may be driven out of the SOD dielectric material  202  while oxygen molecules may be driven into the dielectric material  202 .  FIG. 2C  illustrates the result of the thermal curing process in which a now relatively uniform and void-free dielectric material  204  fills the valleys  104 . In other implementations of the invention, the oxide  200  and the dielectric material  202  may be cured through the application of ultraviolet (UV) radiation or other means of high energy treatment. In such an implementation, the oxide  200  and the dielectric material  202  must be UV-curable materials.  
         [0017]     The initial HDPCVD process may result in an oxide profile that is very favorable for the subsequent SOD thermal curing process. As shown in  FIG. 2A , the HDPCVD process reduces the aspect ratio of the valley  104  while providing each partially-filled valley  104  with a new, relatively larger trench opening  206  compared to the original trench opening  106  (shown in  FIG. 1 ). During the thermal curing process, the large angle of acceptance provided by the new trench opening  206  may allow organics to more easily diffuse out of the dielectric material  202  and may allow oxygen to more easily diffuse into the dielectric material  202 . The result may be a cured dielectric material  202  that provides a more crack-free, high-quality isolation.  
         [0018]     In an implementation, an optional thermal curing process may be conducted after the sacrificial layer of dielectric material  202  over the structures  102  has been polished by the CMP process. Since either a thin layer or no layer of the sacrificial layer may remain atop the oxide  200  after the CMP process, the diffusion path will be shortened and therefore the SOD densification will be further improved. The shortened diffusion path may allow organics to more easily diffuse out of the dielectric material  202  and allow oxygen to more easily diffuse into the dielectric material  202 .  
         [0019]      FIGS. 3A  to  3 C demonstrate another implementation of the invention. In the process shown, an alternative CVD process, such as LPCVD or SACVD, may be used to provide a high quality oxide and good interface at critical isolation regions.  FIG. 3A  shows a first step of this process where an LPCVD or SACVD deposition process is carried out on the substrate  100  and the structures  102 . Similar to the HDPCVD process, the LPCVD or SACVD process deposits a high quality oxide  300  into the valleys  104  at the critical interfaces for good electrical isolation. The LPCVD/SACVD process shown in  FIG. 3A  reduces the aspect ratio of the valley  104 , however, unlike the HDPCVD process, the aspect ratio for trench openings  301  after the LPCVD/SACVD process may not be smaller than the original trench openings  106 . This is generally because the LPCVD/SACVD process is a more conformal process than the HDPCVD process. The trench profile after LPCVD/SACVD may also become reentrant which means only the SOD process may generally provide satisfactory gap fill capability.  
         [0020]     In sub-90 nm applications, the oxide profile after the initial LPCVD or SACVD process may tend to have an open seam or a narrow void due to the conformal deposition characteristics. The seams or voids may be very small and tend to be difficult for conventional CVD processes to fill. In accordance with the invention, however, such a seam or narrow void may be filled by a subsequent SOD process. Furthermore, because the seam or void will generally have a small volume, any shrinkage that occurs due to SOD densification will have a minimal impact on the overall trench isolation performance.  
         [0021]      FIG. 3B  illustrates this subsequent step of the LPCVD/SACVD-SOD process according to the invention. After the oxide  300  has been deposited by the LPCVD/SACVD process, an SOD process may be carried out to fill the remainder of the valleys  104  with a dielectric material  302 . The spin-on process substantially completes filling the valleys  104  with dielectric material  302  so that the overall fill is void-free. Within each valley  104 , the dielectric material  302  may sit atop the oxide  300 . And as described above, the spin-on process used to deposit the dielectric material  302  may be self-planarizing; accordingly, the dielectric material  202  may have a top surface that is substantially planarized and may act as a sacrificial layer for an optimized CMP process.  
         [0022]     After the SOD process, in an implementation of the invention a thermal curing process may be carried out. The thermal curing process may be used for cross-linking, oxidation, and densification of the SOD. As described above, during the thermal curing process organic compounds may be driven out of the dielectric material  302  while oxygen molecules may be driven in.  FIG. 3C  illustrates the result of the thermal curing process in which a now relatively uniform and void-free dielectric material  304  fills the alleys  104 .  
         [0023]     In some implementations, the HDPCVD process conditions for 200 nm semiconductor wafers using an Applied Materials Ultima Plus™ system may include the following: 
        1) Top/Side Source Radio Frequency (RF): 2.0 Mhz     2) Bias RF: 13.56 Mhz     3) Top Coil Source RF Power: 100-5000 Watts     4) Side Coil Source RF Power: 100-5000 Watts     5) Bias RF Power: 100-5000 Watts     6) Pressure: 2-50 mTorr     7) Key gases for deposition: SiH 4  and O 2  at 20-500 std cubic cm per min (sccm)     8) Optional gases for deposition: Ar, He, SiF 4 , and NF 3  at 20-500 sccm.        
 
         [0032]     In some implementations, the SACVD process conditions for 200 mm semiconductor wafers using an Applied Materials Ultima Plus™ system may include the following range of tetraethylorthosilicate (TEOS) based conditions: 
        1) Temperature: 200-600° C.     2) Pressure: 300-760 torr     3) O 2  flow rate: 3000-12,000 sccm     4) O 3  concentration in O 2 : 3-10%     5) Dilution N 2  at 9,000-27,000 sccm     6) TEOS/N 2  at 500-1500 sccm     7) O 3 /TEOS ratio of 5:1 to 25:1.        
 
         [0040]     In some implementations, the SOD process conditions may include a dielectric material composed of silicon containing polymers dissolved or dispensed in suitable solvents. The dielectric material may be applied to the substrate by spin coating under the following process conditions: 
        1) Substrate rotation speed of 500 to 4000 RPM     2) Baking at 100° C. to 400° C. in an inert or an oxidative atmosphere     3) Optional cure at 400° C.-500° C. for 2 min to 3 hr     4) Additional high temp cure at 600° C.-900° C. in inert or oxidative atmosphere to fully converted the cured film to oxide.        
 
         [0045]     In some implementations, the SOD film may exhibit oxide-like properties after the high temperature cure. Other high energy processes may be used to achieve the same effect. The high temperature cure may also be performed after the CMP to shorten the diffusion path.  
         [0046]     In some implementations, the SOD process conditions may include the following: 
        1) Apply SOD while substrate is static     2) Spin substrate at 500 RPM for 3 sec     3) Spin substrate at 1000 RPM for 2 sec     4) Spin substrate at 3000 RPM for 30 sec     5) Bake at 150° C. for 1 min in N 2  or air     6) Bake at 250° C. for 1 min in N 2  or air     7) Bake at 350° C. for 1 min in N 2  or air     8) Cure at 450° C. for 1 hr in air     9) High temp steam cure at 850° C. for 1 hr in O 2  with water vapor.        
 
         [0056]     In implementations of the invention, the methods described above may be carried out on separate tools for the chemical vapor deposition process and the subsequent spin-on dielectric process. For instance, the CVD process may be carried out in a CVD chamber, and the SOD process may then be carried out on a SOD tool. In some implementations, a combined system may be used that includes a spin-on dielectric tool within a chemical vapor deposition chamber. Known CVD systems and known SOD tools may be used to carry out the methods described above.  
         [0057]     The above description of illustrated implementations of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. For example, implementations of the invention include CVD processes other than HDPCVD, LPCVD, and SACVD.  
         [0058]     These modifications may be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.