Abstract:
A method for transmitting image data through reduced swing differential signaling (RSDS) transmission interfaces to a driver in a display is provided, in which the image data include a number of pixel values each represented by a number of bits. The method includes the step of: simultaneously transmitting at least two bits of one of the pixel values by a single timing controller in one time period, in which each of the simultaneously transmitted bits is transmitted through a respective data line of the RSDS transmission interfaces.

Description:
BACKGROUND 
       [0001]    1. Field of Invention 
         [0002]    The present invention relates to a method for transmitting image data. More particularly, the present invention relates to a method for transmitting image data through reduced swing differential signaling (RSDS) transmission interfaces to a driver in a display. 
         [0003]    2. Description of Related Art 
         [0004]    Reduced swing differential signaling (RSDS) is a differential interface with a nominal signal swing of 200 mV. RSDS defines the output characteristics of a transmitter and the inputs of a receiver along with the protocol for a chip-to-chip interface between timing controllers and drivers. RSDS also retains many benefits such as high noise immunity, high data rate, low EMI characteristics and low power dissipation. 
         [0005]    The image data including a plurality of pixel values, each of which represented by a plurality of bits, is transmitted through the RSDS transmission interface from the timing controller to the driver in a display. However, with the display resolution getting higher, the frequency for image data transmission between the timing controller and the driver also gets higher, which causes EMI issues and power consumption. 
       SUMMARY 
       [0006]    In accordance with one embodiment of the present invention, a display is provided. The display includes a timing controller and a source driver. The timing controller includes a transmitter connected to a bus including a plurality of transmission lines each for sending a same number of pixel data. The source driver includes a receiver and plural channels, in which the receiver is connected to the bus to receive the pixel data sent through the bus, for reorganizing the pixel data to generate a new sequence of pixel data, based on a bus mode, for the channels. 
         [0007]    In accordance with another embodiment of the present invention, a method for transmitting image data in a display is provided. The method includes the steps of: sending a same number of pixel data respectively through one of a plurality of transmission lines of a bus to a source driver; reorganizing the pixel data in the source driver; and generating a new sequence of pixel data according to the reorganization of the pixel data sent through the transmission lines, for channels in the source driver. 
         [0008]    It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the invention as claimed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The invention can be more fully understood by reading the following detailed description of the embodiments, with reference to the accompanying drawings as follows: 
           [0010]      FIG. 1  illustrates a general block diagram of a display according to one embodiment of the present invention; 
           [0011]      FIG. 2A  illustrates a timing diagram of data transmission in  FIG. 1  according to a first embodiment of the present invention; 
           [0012]      FIG. 2B  illustrates a general timing diagram of data transmission and reorganization mentioned in  FIG. 2A ; 
           [0013]      FIG. 2C  illustrates a timing diagram of data transmission in  FIG. 1  according to a second embodiment of the present invention; 
           [0014]      FIG. 2D  illustrates a general timing diagram of data transmission and reorganization mentioned in  FIG. 2C ; 
           [0015]      FIG. 3A  illustrates a timing diagram of data transmission in  FIG. 1  according to a third embodiment of the present invention; 
           [0016]      FIG. 3B  illustrates a general timing diagram of data transmission and reorganization mentioned in  FIG. 3A ; 
           [0017]      FIG. 3C  illustrates a timing diagram of data transmission in  FIG. 1  according to a fourth embodiment of the present invention; and 
           [0018]      FIG. 3D  illustrates a general timing diagram of data transmission and reorganization mentioned in  FIG. 3C . 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0019]    In the following detailed description, the embodiments of the present invention have been shown and described. As will be realized, the invention is capable of modification in various respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not restrictive. 
         [0020]      FIG. 1  illustrates a general block diagram of a display according to one embodiment of the present invention. The display includes a timing controller  100  and a source driver  120 . The timing controller  100  includes a transmitter  102 , which is for example a reduced swing differential signaling (RSDS) transmitter. The transmitter  102  is connected to a transmission bus  104 , for sending pixel data through the transmission bus  104  to the source driver  120 . The transmission bus  104  includes a plurality of buses  110  each respectively for sending pixel data. 
         [0021]    The source driver  120  includes a receiver  122  and plural channels  124 , in which the receiver  122  can be embodied as a line buffer. The receiver  122  is connected to the transmission bus  104  and receives the pixel data through the transmission bus  104 . In other words, the receiver  122  receives the pixel data respectively from the buses  110 . 
         [0022]    Further, the receiver  122  reorganizes the pixel data to generate a new sequence of pixel data, based on a bus mode, for the channels  124 . In one embodiment, the receiver  122  alternatively selects the pixel data sent by each of transmission lines  110  to be outputted as the new sequence of pixel data for the channels  124 . 
         [0023]    In one embodiment, the transmission bus  104  includes two buses  110  each respectively for sending pixel data.  FIG. 2A  illustrates a timing diagram of data transmission in  FIG. 1  according to a first embodiment of the present invention. Hereinafter, 1 st  bus  110  is provided for transmitting a first sequence of pixel data (e.g. D 29 , D 28 , D 27 , D 26 , . . . , D 15 ) of 1 st  image data from the timing controller  100 , 2 nd  bus  110  is provided for transmitting a second sequence of pixel data (e.g. D 14 , D 13 , D 12 , D 11 , . . . , D 00 ) of 1 st  image data from the timing controller  100 . First, if an enable input/output signal (EIO) is activated, the first sequence of pixel data D 29 , D 28 , D 27 , D 26 , . . . , D 15  and the second sequence of pixel data D 14 , D 13 , D 12 , D 11 , . . . , D 00  are sent respectively from the 1 st  bus  110  and the 2 nd  bus  110  to the receiver  122  of the source driver  120 . Then, the first sequence of pixel data D 29 , D 28 , D 27 , D 26 , . . . , D 15  and the second sequence of pixel data D 14 , D 13 , D 12 , D 11 , . . . , D 00  are reorganized by the receiver  122  of the source driver  120 , and the new sequence of pixel data are generated according to the reorganization of the first sequence of pixel data D 29 , D 28 , D 27 , D 26 , . . . and the second sequence of pixel data D 14 , D 13 , D 12 , D 11 , . . . . 
         [0024]      FIG. 2B  illustrates a general timing diagram of data transmission and reorganization mentioned in  FIG. 2A . As shown in  FIG. 2B , after the first sequence of pixel data D 29 , D 28 , D 27 , D 26 , . . . , D 15  and the second sequence of pixel data D 14 , D 13 , D 12 , D 11 , . . . , D 00  are transmitted to and reorganized by the receiver  122 , bus C representing the bus (not shown) for the receiver  122  transmits the new sequence of pixel data (e.g. D 29 , D 28 , D 27 , D 26 , . . . , D 00 ) of 1 st  image data to the channels  124 . 
         [0025]    In another embodiment, the receiver  122  alternatively selects the pixel data sent by the 1 st  and 2 nd  transmission lines to be outputted as the new sequence of pixel data for the channels  124 .  FIG. 2C  illustrates a timing diagram of data transmission in  FIG. 1  according to a second embodiment of the present invention. In present embodiment, 1 st  bus is provided for transmitting a first sequence of pixel data (e.g. D 29 , D 27 , D 25 , D 23 , . . . , D 01 ) of 1 st  image data from the timing controller  100 , 2 nd  bus is provided for transmitting a second sequence of pixel data (e.g. D 28 , D 26 , D 24 , D 22 , . . . , D 00 ) of 1 st  image data from the timing controller  100 . Similarly, if the enable input/output signal (EIO) is activated, the first sequence of pixel data D 29 , D 27 , D 25 , D 23 , . . . , D 01  and the second sequence of pixel data D 28 , D 26 , D 24 , D 22 , . . . , D 00  are sent respectively from the 1 st  bus  110  and the 2 nd  bus  110  to the receiver  122  of the source driver  120 . Then, the first sequence of pixel data D 29 , D 27 , D 25 , D 23 , . . . , D 01  and the second sequence of pixel data D 28 , D 26 , D 24 , D 22 , . . . , D 00  are reorganized by the receiver  122  of the source driver  120 , and the new sequence of pixel data are generated according to the reorganization of the first sequence of pixel data D 29 , D 27 , D 25 , D 23 , . . . , D 01  and the second sequence of pixel data D 28 , D 26 , D 24 , D 22 , . . . , D 00 . 
         [0026]      FIG. 2D  illustrates a general timing diagram of data transmission and reorganization mentioned in  FIG. 2C . As shown in  FIG. 2D , after the first sequence of pixel data D 29 , D 27 , D 25 , D 23 , . . . , D 01  and the second sequence of pixel data D 28 , D 26 , D 24 , D 22 , . . . , D 00  are transmitted to and reorganized by the receiver  122 , bus C representing the bus (not shown) for the receiver  122  transmits the new sequence of pixel data (e.g. D 29 , D 28 , D 27 , D 26 , . . . , D 00 ) of 1 st  image data to the channels  124 . 
         [0027]    Notably, in the embodiment of  FIG. 2B  or  FIG. 2D , the timing controller  100  sends the pixel data through 1 st  bus and 2 nd  bus at a first clock rate, and the receiver  122  can output through bus C the new sequence of pixel data for the channels at a second clock rate twice the first clock rate. 
         [0028]    In another aspect, the transmission bus  104  includes three buses  110  each respectively for sending pixel data.  FIG. 3A  illustrates a timing diagram of data transmission in  FIG. 1  according to a third embodiment of the present invention. Hereinafter, 1 st  bus  110  is provided for transmitting a first sequence of pixel data (e.g. D 29 , D 28 , D 27 , D 26 , . . . , D 20 ) from the timing controller  100 , 2 nd  bus  110  is provided for transmitting a second sequence of pixel data (e.g. D 19 , D 18 , D 17 , D 16 , . . . , D 10 ) from the timing controller  100 , 3 rd  bus  110  is provided for transmitting a third sequence of pixel data (e.g. D 09 , D 08 , D 07 , D 06 , . . . , D 00 ) from the timing controller  100 . First, if an enable input/output signal (EIO) is activated, the first sequence of pixel data D 29 , D 28 , D 27 , D 26 , . . . , D 20 , the second sequence of pixel data D 19 , D 18 , D 17 , D 16 , . . . , D 10  and the third sequence of pixel data D 09 , D 08 , D 07 , D 06 , . . . , D 00  are sent respectively from the 1 st  bus  110 , the 2 nd  bus  110  and the 3 rd  bus  110  to the receiver  122  of the source driver  120 . Then, the first sequence of pixel data D 29 , D 28 , D 27 , D 26 , . . . , D 20  the second sequence of pixel data D 19 , D 18 , D 17 , D 16 , . . . , D 10  and the third sequence of pixel data D 09 , D 08 , D 07 , D 06 , . . . , D 00  are reorganized by the receiver  122  of the source driver  120 , and the new sequence of pixel data are generated according to the reorganization of the first sequence of pixel data D 29 , D 28 , D 27 , D 26 , . . . , D 20 , the second sequence of pixel data D 19 , D 18 , D 17 , D 16 , . . . , D 10  and the third sequence of pixel data D 09 , D 08 , D 07 , D 06 , . . . , D 00 . 
         [0029]      FIG. 3B  illustrates a general timing diagram of data transmission and reorganization mentioned in  FIG. 3A . As shown in  FIG. 3B , after first sequence of pixel data D 29 , D 28 , D 27 , D 26 , . . . , D 20 , the second sequence of pixel data D 19 , D 18 , D 17 , D 16 , . . . , D 10  and the third sequence of pixel data D 09 , D 08 , D 07 , D 06 , . . . , D 00  are transmitted to and reorganized by the receiver  122 , bus C representing the bus (not shown) for the receiver  122  transmits the new sequence of pixel data (e.g. D 29 , D 28 , D 27 , D 26 , . . . , D 00 ) of 1 st  image data to the channels  124 . 
         [0030]    In another embodiment, the receiver  122  alternatively selects the pixel data sent by the 1 st , 2 nd  and 3 rd  bus  110  to be outputted as the new sequence of pixel data for the channels  124 .  FIG. 3C  illustrates a timing diagram of data transmission in  FIG. 1  according to a fourth embodiment of the present invention. In present embodiment, the 1 st  bus  110  is provided for transmitting a first sequence of pixel data (e.g. D 29 , D 26 , D 23 , D 20 , . . . , D 02 ) from the timing controller  100 , the 2 nd  bus  110  is provided for transmitting a second sequence of pixel data (e.g. D 28 , D 25 , D 22 , D 19 , . . . , D 01 ) from the timing controller  100 , the 3 rd  bus  110  is provided for transmitting a third sequence of pixel data (e.g. D 27 , D 24 , D 21 , D 18 , . . . , D 00 ) from the timing controller  100 . Similarly, if the enable input/output signal (EIO) is activated, the first sequence of pixel data D 29 , D 26 , D 23 , D 20 , . . . , D 02 , the second sequence of pixel data D 28 , D 25 , D 22 , D 19 , . . . , D 01 , and the third sequence of pixel data D 27 , D 24 , D 21 , D 18 , . . . , D 00  are sent respectively from the 1 st  bus  110 , the 2 nd  bus  110  and the 3 rd  bus  110  to the receiver  122  of the source driver  120 . Then, the first sequence of pixel data D 29 , D 26 , D 23 , D 20 , . . . , D 02 , the second sequence of pixel data D 28 , D 25 , D 22 , D 19 , . . . , D 01 , and the third sequence of pixel data D 27 , D 24 , D 21 , D 18 , . . . , D 00  are reorganized by the receiver  122  of the source driver  120 , and the new sequence of pixel data D 29 , D 28 , D 27 , D 26 , . . . , D 00  are generated accordingly. 
         [0031]      FIG. 3D  illustrates a general timing diagram of data transmission and reorganization mentioned in  FIG. 3C . As shown in  FIG. 3D , after the first sequence of pixel data D 29 , D 26 , D 23 , D 20 , . . . , D 02 , the second sequence of pixel data D 28 , D 25 , D 22 , D 19 , . . . , D 01 , and the third sequence of pixel data D 27 , D 24 , D 21 , D 18 , . . . , D 00  are transmitted to and reorganized by the receiver  122 , bus C representing the bus (not shown) for the receiver  122  transmits the new sequence of pixel data (e.g. D 29 , D 28 , D 27 , D 26 , . . . , D 00 ) of 1 st  image data to the channels  124 . 
         [0032]    Notably, in the embodiment of  FIG. 3B  or  FIG. 3D , the timing controller  100  sends the pixel data through 1 st , 2 nd  and 3 rd  bus at a first clock rate, and the receiver  122  can output through bus C the new sequence of pixel data for the channels at a second clock rate tripling the first clock rate. 
         [0033]    For the foregoing embodiment of the present invention, the method for transmitting the image data through the RSDS transmission interfaces can be provided to improve the efficiency and speed of the image data transmission, so as to further improve the operation speed of the display. 
         [0034]    As is understood by a person skilled in the art, the foregoing embodiments of the present invention are illustrative of the present invention rather than limiting of the present invention. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structures.