Abstract:
A transmission apparatus includes a first storage configured to store data received from external into a write enable area, a second storage configured to store the data in accordance with a write request and output a retry request in response to occurring an error of writing a first data included in the data, and a controller configured to read the data from the first storage and send the write request to the second storage, set an area of the first storage storing the first data to a write disable area in combination with stop sending the retry request to external when receiving the retry request from the second storage, and send the first data reading from the write disable area of the first storage to external in response to a read request from external.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2015-169715, filed on Aug. 28, 2015, the entire contents of which are incorporated herein by reference. 
       FIELD 
       [0002]    The embodiments discussed herein are related to a transmission apparatus and a retry method for transmitting a received packet after storing the packet in a memory. 
       BACKGROUND 
       [0003]    With the recent increased communication traffic, there has been a demand for a transmission apparatus achieving data communications with higher speed, larger capacity, and higher quality. To meet such demand, some transmission apparatus employs a high-speed serial memory as a memory to temporarily hold received data within the transmission apparatus. This high-speed serial memory is provided as a packet buffer in a reception unit of the transmission apparatus, for example, and is used as a memory from which data is read within a certain period of time after the data is written, even though the read order of the data changes according to the priority. 
         [0004]    There is one using a serializer/deserializer (Serdes) transceiver as an interface of the high-speed serial memory. In the Serdes, an error occurs probabilistically (with a predetermined probability) due to noise or the like on a transmission path within the transmission apparatus. When the Serdes has an access error (write error) to the high-speed serial memory, a retry (another write processing) to the high-speed serial memory within the transmission apparatus is performed in order to reduce data loss and to ensure data quality. 
         [0005]    Moreover, there is a technique for data transmission between apparatuses to reduce a retry frequency, by monitoring a state of a reception buffer in a reception-side apparatus, obtaining a reference time corresponding to the time of occurrence of a retry request, and controlling data read from a transmission buffer in a transmission-side apparatus. 
         [0006]    Japanese Laid-open Patent Publication No. 2010-191569 is known as an example of prior art. 
         [0007]    In the above prior technique, a data transmission amount between the apparatuses may not be reduced since data is transmitted between the apparatuses upon every retry. 
         [0008]    Moreover, when the Serdes is used as a memory interface in the transmission apparatus, a retry to the serial memory is performed in the transmission apparatus upon occurrence of a write error to the high-speed serial memory. Therefore, an access band of the high-speed serial memory is occupied. When an interface speed of the Serdes is increased in response to the band occupancy, power consumption is significantly increased. 
       SUMMARY 
       [0009]    According to an aspect of the invention, a transmission apparatus includes a first storage configured to store data received from external into a write enable area, a second storage configured to store the data in accordance with a write request and output a retry request in response to occurring an error of writing a first data included in the data, and a controller configured to read the data from the first storage and send the write request to the second storage, set an area of the first storage storing the first data to a write disable area in combination with stop sending the retry request to external when receiving the retry request from the second storage, and send the first data reading from the write disable area of the first storage to external in response to a read request from external. 
         [0010]    The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
         [0011]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0012]      FIG. 1  is a configuration diagram illustrating a transmission apparatus according to Embodiment 1; 
           [0013]      FIG. 2  is a diagram illustrating a configuration example of a memory controller part of the transmission apparatus according to Embodiment 1; 
           [0014]      FIG. 3  is a diagram illustrating a configuration example of a retry avoidance buffer used in the transmission apparatus according to Embodiment 1; 
           [0015]      FIG. 4  is a sequence diagram illustrating a processing example of respective units during a data write in the transmission apparatus according to Embodiment 1; 
           [0016]      FIG. 5  is a sequence diagram illustrating a processing example of the respective units during a data read in the transmission apparatus according to Embodiment 1; 
           [0017]      FIG. 6  is a flowchart illustrating a data processing content example in the transmission apparatus according to Embodiment 1 (Processing Part 1 during write); 
           [0018]      FIG. 7  is a flowchart illustrating a data processing content example in the transmission apparatus according to Embodiment 1 (Processing Part 2 during write); 
           [0019]      FIG. 8  is a flowchart illustrating a data processing content example in the transmission apparatus according to Embodiment 1 (Processing Part 3 during write); 
           [0020]      FIG. 9  is a flowchart illustrating a data processing content example in the transmission apparatus according to Embodiment 1 (Processing Part 1 during read); 
           [0021]      FIG. 10  is a flowchart illustrating a data processing content example in the transmission apparatus according to Embodiment 1 (Processing Part 2 during read); 
           [0022]      FIG. 11  is a flowchart illustrating a data processing content example in the transmission apparatus according to Embodiment 1 (Processing Part 3 during read); 
           [0023]      FIG. 12  is a flowchart illustrating a data processing content example in the transmission apparatus according to Embodiment 1 (Processing Part 4 during read); 
           [0024]      FIG. 13  is a diagram illustrating a configuration example of a memory controller part of a transmission apparatus according to Embodiment 2; 
           [0025]      FIG. 14  is a sequence diagram illustrating a processing example of avoiding a write access to the same bank during a read retry in the transmission apparatus according to Embodiment 2; 
           [0026]      FIG. 15  is a flowchart illustrating a data processing content example in the transmission apparatus according to Embodiment 2; 
           [0027]      FIG. 16  is a diagram illustrating a configuration example of a memory controller part of a transmission apparatus according to Embodiment 3; 
           [0028]      FIG. 17  is a sequence diagram illustrating an autonomous retry processing example in the transmission apparatus according to Embodiment 3; 
           [0029]      FIG. 18  is a flowchart illustrating a data processing content example in the transmission apparatus according to Embodiment 3 (Part 1); 
           [0030]      FIG. 19  is a flowchart illustrating a data processing content example in the transmission apparatus according to Embodiment 3 (Part 2); 
           [0031]      FIG. 20  is a flowchart illustrating another data processing content example in the transmission apparatus according to Embodiment 3; and 
           [0032]      FIG. 21  is a sequence diagram illustrating a state of band occupancy of an existing transmission apparatus. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0033]    It is an object of one aspect of embodiments to make it possible to avoid occupancy of a communication band of a memory by reducing a write retry to the memory even if a write error of a received packet into the memory occurs. 
         [0034]    Embodiments of disclosed transmission apparatus and retry method are described in detail. 
       Embodiment 1 
       [0035]      FIG. 1  is a configuration diagram illustrating a transmission apparatus according to Embodiment 1. A transmission apparatus  100  is connected to multiple processors  102  through transmission paths  101  such as a LAN. The example of  FIG. 1  illustrates a state where the transmission apparatus  100  transmits data transmitted from three processors  102   a  to  102   c  on data transmission side to one processor  102   d  on data reception side. Packets described below are all data to be transferred from the processors  102  ( 102   a  to  102   c ) on the transmission side to the processor  102  ( 102   d ) on the reception side. The packets and the data are synonymous. 
         [0036]    The processors  102  ( 102   a  to  102   c ) such as PCs on the transmission side transmit packets  112  ( 112   a  to  112   c ) to the transmission apparatus  100 , respectively. Each of the packets  112  includes a header  121  and data  122 . 
         [0037]    The transmission apparatus  100  includes a reception buffer  131 , a reception unit  132 , a control unit  133 , a memory control unit  134 , a memory controller  135 , a transmission unit  136 , a transmission buffer  137 , and a high-speed serial memory  141 . 
         [0038]    A field-programmable gate array (FPGA)  150  may be used for the reception buffer  131 , the reception unit  132 , the control unit  133 , the memory control unit  134 , the memory controller  135 , the transmission unit  136 , and the transmission buffer  137 , for example. 
         [0039]    The embodiments are not limited to the FPGA  150  but may adopt a configuration in which a CPU and a ROM, a RAM and the like are used and a control program stored in the ROM is executed by the CPU to use the RAM as a work area. 
         [0040]    The reception buffer  131  performs buffering to temporarily accumulate a predetermined amount of packets received from the transmission-side processors  102  ( 102   a  to  102   c ) through the transmission paths  101 , and outputs the packets to the reception unit  132 . The reception unit  132  performs reception processing of the received packets, and outputs the packets to the memory control unit  134  after checking the header, ECC (OK/FAILED) and the like. 
         [0041]    The control unit  133  controls the respective units in the transmission apparatus  100 . For example, the received packets are subjected to reception processing by the reception unit  132 , and are written into the serial memory  141  as a storage through the memory control unit  134 . Also, the control unit  133  controls the memory control unit  134  to read the packets according to the priority for each packet from the serial memory  141 , and then controls the transmission unit  136  to transmit the packets to the corresponding reception-side processor  102  ( 102   d ) after assembling the packets. 
         [0042]    The memory control unit  134  includes a memory write control unit  134   a,  a conflict settlement unit  134   b,  and a memory read control unit  134   c.  The memory controller  135  controls write and read of data (packets) into and from the serial memory  141 . Also, the memory controller  135  uses a Serdes  135   a,  for example, as an interface with the serial memory  141 .  135   b  denotes a transmission path of the Serdes  135   a  within the transmission apparatus. 
         [0043]    For example, the serial memory  141  has a transmission band (read/write rate) of 12.5 Gbps, and the transmission path  135   b  has a transmission rate of 10 Gbps. 
         [0044]    In the example of  FIG. 1 , the serial memory  141  is used as a packet buffer  141   a  in which the received packets are stored and from which the packets are read upon elapse of a certain period of time after the packets are written. The packets written into the serial memory  141  (packet buffer  141   a ) are read in the order of read corresponding to the priority. 
         [0045]    The memory write control unit  134   a  in the memory control unit  134  writes the packets subjected to the reception processing by the reception unit  132  into the serial memory  141  (packet buffer  141   a ) through the memory controller  135 . 
         [0046]    The conflict settlement unit  134   b  settles conflict between write and read of data to the serial memory  141 . Also, the conflict settlement unit  134   b  performs control to settle a write access during a read retry to the same Bank among banks (Banks; four regions storing packets in  FIG. 1 ) in the serial memory  141  (packet buffer  141   a ) and to temporarily put a write operation on standby. 
         [0047]    The memory read control unit  134   c  reads the packets from the serial memory  141  (packet buffer  141   a ) and outputs the packets to the transmission unit  136 . 
         [0048]    The transmission unit  136  changes the header, adds ECC or the like to transmit the packets read from the serial memory  141  (packet buffer  141   a ) to a predetermined destination, and outputs the packets to the transmission buffer  137 . The transmission buffer  137  performs buffering to temporarily accumulate a predetermined amount of packets to be transmitted, and transmits and outputs the packets onto the transmission path  101  toward the corresponding reception-side processor (the processor  102   d  in the example of  FIG. 1 ) based on the headers of the packets. 
         [0049]    In the example of  FIG. 1 , the transmission apparatus  100  transmits the packets in a predetermined priority order (order of the packets  112   b,    112   b,  and  112   a ) to the reception-side processor  102   d.    
         [0050]      FIG. 2  is a diagram illustrating a configuration example of a memory controller part of the transmission apparatus according to Embodiment 1.  FIG. 2  illustrates the memory controller  135  part extracted from the configuration illustrated in  FIG. 1 . The Serdes  135   a  is provided as an IF circuit on each of the memory controller  135  side and the serial memory  141  side across the transmission path  135   b.    
         [0051]    The transmission apparatus  100  according to Embodiment 1 has an additional function to the memory controller  135 . The memory controller  135  includes a retry request determination unit  201 , a command/retry address comparison unit  202 , and a retry avoidance buffer  203 . The command/retry address comparison unit  202  and the retry avoidance buffer  203  are added as new functions. 
         [0052]    The retry avoidance buffer  203  functions as a temporary storage to temporarily store and hold packets (data and address information) to be written into the serial memory  141 . The data temporarily stored in the retry avoidance buffer  203  is deleted when the packets are normally written into the serial memory  141 . The read retry buffer  203   a  stores and holds information such as address for retry to read the data from the retry avoidance buffer  203  during a retry. 
         [0053]    The retry request determination unit  201  determines whether or not there is a retry request to the serial memory  141 . The command/retry address comparison unit  202  searches for the same address in the retry avoidance buffer  203  upon issuance of a read request. Then, based on the search result, data is read from the serial memory  141  when there is no same address, and data is read from the retry avoidance buffer  203  when there is the same address. 
         [0054]    When an error occurs and a retry request S 1  is returned during the write access to the serial memory  141 , the memory controller  135  holds the relevant address and data in the retry avoidance buffer  203  and does not execute a write retry to the serial memory  141 . The retry avoidance buffer  203  holds only the packets which have failed to be written into the serial memory  141  (S 2 ). 
         [0055]    When a read request is issued from a user circuit in response to occurrence of an event, the retry request determination unit  201  causes the command/retry address comparison unit  202  to search for the same address in the retry avoidance buffer  203 . 
         [0056]    The user circuit is a circuit for reading and writing data to the serial memory  141 , which corresponds to the memory control unit  134  (the memory write control unit  134   a  and the memory read control unit  134   c ) in the above configuration example. 
         [0057]    Then, when there is no same address in the retry avoidance buffer  203 , the retry request determination unit  201  issues a read to the serial memory  141 . On the other hand, when there is the same address in the retry avoidance buffer  203 , the retry request determination unit  201  returns the read data read from the retry avoidance buffer  203  to the user circuit without issuing any read to the serial memory  141 . 
         [0058]    When the Serdes  135   a  is used in the memory controller  135 , a write error occurs probabilistically in the serial memory  141  due to noise or the like on the transmission path. However, according to the above configuration, retries to the serial memory  141  may be reduced, thus enabling operation of the serial memory  141  without occupying the communication band to the serial memory  141 . 
         [0059]    The serial memory  141  is a packet buffer holding received data, and is a memory from which packets are read upon elapse of a certain period of time after the packets are written, even though the read order changes according to the priority. 
         [0060]      FIG. 3  is a diagram illustrating a configuration example of the retry avoidance buffer used in the transmission apparatus according to Embodiment 1. The retry avoidance buffer  203  may have various configurations, and an example thereof is illustrated in  FIG. 3 . Flags, addresses, and lengths of data are stored in FF (register), while data is stored in an internal memory in the retry avoidance buffer  203 . 
         [0061]    In the event of a data write to the retry avoidance buffer  203 , data is basically added to the stored data (additionally written into a region after the final address). In this event, an address and the length of data are stored in a region having “0” as the value of a flag. When the data is stored, the flag is set to “1”. The presence or absence of data in the retry avoidance buffer  203  is managed using the flag. Also, when the data is deleted from the retry avoidance buffer  203 , the flag of the corresponding address is only changed to “0”. Thus, the processing of deleting the data itself may be reduced. Thus, the flag indicates a write enable area when the flag is “0”, and the flag indicates a write disable area when the flag is “1”. 
         [0062]    As described above, when the serial memory  141  is used as the packet buffer, the capacity of the retry avoidance buffer  203  (the number of frames in the vertical direction in  FIG. 3 ) may be set to about error occurrence rate+margin within a predetermined maximum read time. 
         [0063]      FIG. 4  is a sequence diagram illustrating a processing example of the respective units during a data write in the transmission apparatus according to Embodiment 1. In the event of a write request of data, the memory controller  135  and the serial memory  141  perform the following processing. 
         [0064]    First, description is given of processing when a data write to the serial memory  141  is successfully performed. 
         [0065]    (1) A write request (Write1) as an event of the user circuit (memory control unit  134 ) is transmitted to the memory controller  135  and the Serdes  135   a.    
         [0066]    (2) The memory controller  135  stores an address (Add1) and data (Data1) of Write1 in the retry avoidance buffer  203 . 
         [0067]    (3) The memory controller  135  issues a write command (Write1) to the serial memory  141 . 
         [0068]    (3)′ The memory controller  135  also restricts (Stop) access to the user circuit  134 . 
         [0069]    (4) When the serial memory  141  has successfully performed the data write, OK (Ack1 (positive)) is returned to the memory controller  135 . The serial memory  141  performs ECC check to determine if the data write has been successful or failed. 
         [0070]    (5) Since the serial memory  141  has successfully performed the data write, the memory controller  135  deletes the corresponding address (Add1) and data (Data1) in the retry avoidance buffer  203 . 
         [0071]    (5)′ The memory controller  135  permits access to the user circuit  134  (ready). 
         [0072]    Next, description is given of processing upon failure of a data write to the serial memory  141 . 
         [0073]    (6) A write request (Write2) as an event is transmitted to the memory controller  135  and the Serdes  135   a.    
         [0074]    (7) The memory controller  135  stores an address (Add2) and data (Data2) of Write2 in the retry avoidance buffer  203 . 
         [0075]    (8) The memory controller  135  issues a write command (Write2) to the serial memory  141 . 
         [0076]    (8)′ The memory controller  135  also restricts (Stop) access to the user circuit  134 . 
         [0077]    (9) When the data write to the serial memory  141  fails, write failure (Ack1 (NG)) is returned to the memory controller  135 . 
         [0078]    (10) Since the data write to the serial memory  141  has failed, the memory controller  135  does not do anything to (does not delete) the corresponding address (Add1) and data (Data1) in the retry avoidance buffer  203 . 
         [0079]    (10)′ The memory controller  135  permits access to the user circuit  134  (ready). 
         [0080]    As described above, upon failure of the data write to the serial memory  141 , the address (Add2) and data (Data2) of Write2 are stored in the retry avoidance buffer  203 . 
         [0081]      FIG. 5  is a sequence diagram illustrating a processing example of the respective units during a data read in the transmission apparatus according to Embodiment 1. In the event of a read request of data, the memory controller  135  and the serial memory  141  perform the following processing. 
         [0082]    First, description is given of data read processing after the processing (1) to (5)′ when the data write to the serial memory  141  has been successful in  FIG. 4  described above. 
         [0083]    (1) A read request (Read1) as an event is transmitted to the memory controller  135 . 
         [0084]    (2) An address of a read target (Read1) is compared with an address in the retry avoidance buffer  203 . 
         [0085]    (3) When the addresses do not correspond as a result of the comparison, a read request (Read1) is issued to the serial memory  141 . 
         [0086]    (4) Data (ReadData1) read from the serial memory  141  is returned to the user circuit  134 . 
         [0087]    As described above, when the data write to the serial memory  141  has been successful, there is no data in the retry avoidance buffer  203 , and the memory controller  135  reads data from the serial memory  141 . 
         [0088]    Next, with reference to  FIG. 5  (processing (5) to (7)′), description is given of data read processing after the processing (6) to (9)′ upon failure of the data write to the serial memory  141  in  FIG. 4  described above. 
         [0089]    (5) A read request (Read2) from the user circuit  134  is transmitted to the memory controller  135 . 
         [0090]    (6) An address of a read target (Read1) is compared with an address in the retry avoidance buffer  203 . 
         [0091]    (7) When the addresses correspond as a result of the comparison, corresponding data (ReadData2) in the retry avoidance buffer  203  is read and returned to the user circuit  134 . 
         [0092]    (7)′ The memory controller  135  deletes corresponding address and data of the data (ReadData2) read from the retry avoidance buffer  203 . 
         [0093]    As described above, when the date write to the serial memory  141  has failed, data is written and held in the retry avoidance buffer  203 , and the memory controller  135  reads data from the serial memory  141 . 
         [0094]    According to the above processing, data in which a write error has occurred during the write processing of the received packet into the serial memory  141  is left in the retry avoidance buffer  203 . Then, during the read processing, an address comparison is made to check if there is an address of data to be read is in the retry avoidance buffer  203 . If the address is in the retry avoidance buffer  203 , the same data may be read from the retry avoidance buffer  203  without access (retry) to the serial memory  141 . 
         [0095]      FIGS. 6 to 12  are flowcharts each illustrating a data processing content example in the transmission apparatus according to Embodiment 1. 
         [0096]    (Processing Example During Data Write) 
         [0097]    First, with reference to  FIGS. 6 to 8 , detailed description is given of processing contents during data write.  FIGS. 6 to 8  also each illustrate the flow of write data WD. 
         [0098]    First,  FIG. 6  illustrates processing performed by the write control unit  134   a  in the memory control unit  134  that is the user circuit. The user circuit  134  determines whether or not there is write data (S 601 ). If there is no write data (S 601 : No loop), the memory control unit  134  waits for input of write data. On the other hand, if there is write data (S 601 : Yes), it is determined based on a status flag or the like in the retry avoidance buffer  203  whether the data may be written into the serial memory  141  (ready state) (S 602 ). 
         [0099]    If the data write is not in the ready state (S 602 : No), the memory control unit  134  returns to S 601 . On the other hand, if the data write is in the ready state (S 602 : Yes), the conflict settlement unit  134   b  determines if there is no simultaneous access to the same Bank with the read side (S 603 ). 
         [0100]    In Embodiment 1, the conflict settlement unit  134   b  is set to give priority to write processing over read processing. Thus, the processing moves to S 604  in any case regardless of the determination result (S 603 : Yes/No) in S 603 . 
         [0101]    In S 604 , the user circuit issues a write command (address, data, and others) (S 604 ). 
         [0102]    After the processing by the user circuit (memory control unit  134 ) illustrated in  FIG. 6  described above, the memory controller  135  executes processing illustrated in  FIG. 7 . First, the memory controller  135  waits for a write command (address, data, and others) to be received (S 701 ). 
         [0103]    Upon receipt of the write command, the memory controller  135  changes the write status flag in the retry avoidance buffer  203  to a Stop state. Also, the memory controller  135  checks an empty region (region with the flag “0” in  FIG. 3 ), stores write data WD in the empty region, and changes the flag of the region storing the write data to “1” (S 702 ). 
         [0104]    Next, the memory controller  135  generates a write command (address, data, and others) to the serial memory  141 , and issues the write command (S 703 ). Thus, the write data WD is multiplexed and outputted to the Serdes  135   a  on the memory controller  135  side (SA). 
         [0105]    Thereafter, the memory controller  135  changes the write status flag in the retry avoidance buffer  203  to a ready state (S 704 ), and waits for a write ACK to be received from the serial memory  141  (S 705 ). 
         [0106]    Then, the memory controller  135  determines whether or not the write ACK received from the serial memory  141  is positive (S 706 ). If the write ACK is positive (S 706 : Yes), the write of the write data WD into the serial memory  141  is successfully completed, and the flag of the corresponding address in the write data WD stored in the retry avoidance buffer  203  is changed to “0” (S 707 ). Then, the processing returns to S 701 . 
         [0107]    On the other hand, if the write ACK is not positive but is negative (S 706 : No), the processing returns to S 701 . In this case, the flag of the corresponding address in the write data WD in the retry avoidance buffer  203  remains as “1”, and the write data WD is held in the retry avoidance buffer  203 . 
         [0108]    After the processing by the memory controller  135  illustrated in  FIG. 7  described above, the serial memory  141  executes processing illustrated in  FIG. 8 . First, the write data WD is multiplexed and inputted to the Serdes  135   a  on the serial memory  141  side (SB), and the serial memory  141  receives a write command (address, data, and others) (S 801 ). 
         [0109]    Then, the serial memory  141  determines whether or not the write command is normal (S 802 ). If the write command is normal (S 802 : Yes), the serial memory  141  writes the write data WD into the memory (packet buffer  141   a ) (S 803 ), and generates a positive ACK (S 804 ). 
         [0110]    On the other hand, if the write command is not normal (S 802 : No), the serial memory  141  generates a negative ACK (S 804 ) without performing the data write in S 803 . The generated ACK is transmitted to the memory controller  135  (for the processing of S 706  in  FIG. 7 ). Note that the ACK is transmitted to the memory controller  135  through the Serdes  135   a  (see  FIG. 12  and the like for the route). 
         [0111]    (Processing Example During Data Read) 
         [0112]    Next, with reference to  FIGS. 9 to 12 , detailed description is given of processing contents during data read.  FIGS. 9 to 12  also each illustrate the flow of read data RD. 
         [0113]    First,  FIG. 9  illustrates processing performed by the read control unit  134   c  in the memory control unit  134  that is the user circuit. The user circuit determines whether or not there is read permission data (S 901 ). If there is no read permission data (S 901 : No loop), the memory control unit  134  waits for input of read permission. On the other hand, if there is read permission data (S 901 : Yes), it is determined based on a status flag or the like in the retry avoidance buffer  203  whether the read data RD may be read from the serial memory  141  (ready state) (S 902 ). 
         [0114]    If the data read is not in the ready state (S 902 : No), the memory control unit  134  returns to S 901 . On the other hand, if the data read is in the ready state (S 902 : Yes), the conflict settlement unit  134   b  determines if there is no simultaneous access to the same Bank with the write side (S 903 ). 
         [0115]    As described above, in Embodiment 1, the conflict settlement unit  134   b  is set to give priority to write processing over read processing. Thus, if there is simultaneous access to the same Bank with the write side during the read as a result of the determination in S 903  (S 903 : No), the processing moves to S 905  after waiting for read for a period corresponding to a command conflict (S 904 ). 
         [0116]    If there is no simultaneous access to the same Bank with the write side during the read as a result of the determination in S 903  (S 903 : Yes), the user circuit issues a read command (address and others) (S 905 ). 
         [0117]    After the processing by the user circuit (memory control unit  134 ) illustrated in  FIG. 9  described above, the memory controller  135  executes processing illustrated in  FIGS. 10 and 11 . First, as illustrated in  FIG. 10 , the memory controller  135  waits for a read command (address and others) to be received (S 1001 ). 
         [0118]    Upon receipt of the read command, the memory controller  135  changes the read status flag from the retry avoidance buffer  203  to a Stop state. Also, the memory controller  135  compares information such as address in the received read command with information (address and others) in the retry avoidance buffer  203  (S 1002 ). 
         [0119]    Then, based on the comparison in S 1002 , the memory controller  135  checks if there is no read data RD in the retry avoidance buffer  203  (S 1003 ). If there is read data RD in the retry avoidance buffer  203  (S 1003 : No), the memory controller  135  reads data from the retry avoidance buffer  203  at a timing not ahead of the read command read data. Also, the memory controller  135  changes the flag of address in the read data RD to “0” (S 1004 ). 
         [0120]    Thereafter, the memory controller  135  changes the status flag in the retry avoidance buffer  203  to the write ready state (S 1005 ), and then returns to S 1001 . 
         [0121]    On the other hand, if there is no read data RD in the retry avoidance buffer  203  (S 1003 : Yes), the memory controller  135  stores address and others of the read command in the read retry buffer  203   a  (S 1006 ), and then moves to S 1007 . 
         [0122]    In S 1007 , the memory controller  135  determines whether or not there is a retry request of the read command (S 1007 ). The memory controller  135  moves to S 1008  if there is the retry request of the read command (S 1007 : Yes), and moves to S 1010  if there is no retry request of the read command (S 1007 : No). 
         [0123]    In S 1008 , the memory controller  135  reads information such as address and others for retry from the read retry buffer  203   a  (S 1008 ). Then, the memory controller  135  determines whether or not the read address from the read retry buffer  203   a  is one included in the final data (S 1009 ). 
         [0124]    If the read address from the read retry buffer  203   a  is the one included in the final data (S 1009 : Yes), the memory controller  135  clears the retry request. In this event, the memory controller  135  also clears the read address of the read retry buffer. Then, the memory controller  135  generates a read command (address and others) to the serial memory  141 , and issues a read command (S 1010 ). 
         [0125]    On the other hand, if the read address from the read retry buffer  203   a  is not the one included in the final data (S 1009 : No), the memory controller  135  increments (+1) the read address of the read retry buffer (S 1011 ). Then, the memory controller  135  generates a read command (address and others) to the serial memory  141 , and issues a read command (S 1012 ). 
         [0126]    The memory controller  135  transmits the read commands issued in S 1010  and S 1012  to the serial memory  141  through the Serdes  135   a  on the memory controller  135  side (see SA in  FIG. 7 ). 
         [0127]    Next, as illustrated in  FIG. 11 , the memory controller  135  changes the read status flag of the retry avoidance buffer  203  to the ready state (S 1101 ), and waits for a read ACK to be received from the serial memory  141  (S 1102 ). 
         [0128]    Then, the memory controller  135  determines whether or not the read data RD (ACK and data) read from the serial memory  141  is normal (S 1103 ). If the read data is normal (S 1103 : Yes), the memory controller  135  determines whether or not the ACK is positive (S 1104 ). If the ACK is positive (S 1104 : Yes), the memory controller  135  moves to S 1106 . 
         [0129]    On the other hand, if the read data is not successfully read in S 1103  (S 1103 : No), the memory controller  135  executes processing of S 1105  and S 1100 . If the ACK is negative in S 1104  (S 1104 : No), the memory controller  135  again executes the processing of S 1105  and S 1100 . 
         [0130]    The memory controller  135  changes the read status flag of the retry avoidance buffer  203  to the Stop state, and makes a retry request (S 1105 ). In this retry request, a read address of the read retry buffer is set, and read data RD is read from the retry avoidance buffer  203 . Meanwhile, in S 1100 , the read data RD from the serial memory  141  is deleted as invalid data (S 1100 ). 
         [0131]    In S 1106 , the memory controller  135  determines whether or not the retry request is being made (S 1106 ). If the retry request is being made (S 1106 : Yes), the memory controller  135  determines whether or not the read data is retry data (S 1107 ). On the other hand, if the retry request is not being made (S 1106 : No), the memory controller moves to S 1109 . 
         [0132]    If the read data is the retry data in S 1107  (S 1107 : Yes), the memory controller  135  deletes the data in the read retry buffer  203   a  of the corresponding address (S 1108 ) and returns to S 1007  in  FIG. 10 . On the other hand, if the read data is not the retry data in S 1107  (S 1107 : No), the memory controller  135  returns to S 1007  in  FIG. 10 . 
         [0133]    In S 1109 , the memory controller  135  deletes the data in the read retry buffer  203   a  of the corresponding address (S 1109 ) and returns to S 1001  in  FIG. 10 . 
         [0134]    The read data RD from the serial memory  141  is multiplexed with the read data RD illustrated in  FIG. 11  and inputted to the Serdes  135   a  on the memory controller  135  side (SD). The memory controller  135  performs the processing illustrated in  FIG. 11  to read the read data RD from the serial memory  141  or the retry avoidance buffer. 
         [0135]    After the processing by the memory controller  135  illustrated in  FIG. 11  described above, the serial memory  141  executes processing illustrated in  FIG. 12 . First, the serial memory  141  receives a read command (address, data, and others) (S 1201 ). 
         [0136]    Then, the serial memory  141  determines whether or not the read command is normal (S 1202 ). If the read command is normal (S 1202 : Yes), the serial memory  141  reads read data RD from the memory (packet buffer  141   a ) (S 1203 ). Thereafter, the serial memory  141  generates an ACK (positive or negative) corresponding to a read status (S 1204 ). 
         [0137]    On the other hand, if the read command is not normal (S 1202 : No), the serial memory  141  generates a negative ACK (S 1204 ) without performing the data read in S 1203 . The generated ACK is transmitted (multiplexed and outputted to the Serdes  135   a:  SC) to the memory controller  135  (for the processing of S 1102  in  FIG. 11 ). 
         [0138]    According to Embodiment 1, data in which a write error has occurred during the write processing of the received packet into the serial memory is left in the retry avoidance buffer. Then, during the read processing, an address comparison is made to check if there is an address of data to be read is in the retry avoidance buffer. If the address is in the retry avoidance buffer, the same data may be read from the retry avoidance buffer without access (retry) to the serial memory. 
         [0139]    The data read from the retry avoidance buffer is data in which a write error has occurred in the serial memory. Thus, a write retry to the serial memory in response to a data error occurring probabilistically in the Serdes may be reduced, making it possible to avoid occupancy of the communication band to the serial memory for an execution time of a write retry to the serial memory. 
         [0140]    Such occupancy of the band occurs during a retry in a situation such as one where the existing transmission apparatus, for example, waits for next write access while accumulating data in the reception buffer, and eventually has an overflow of the reception buffer or the like with the result of making a request to stop data transmission or the like to the transmission-side processor. 
         [0141]    In this regard, according to Embodiment 1, when a write error occurs in the serial memory, the same data is read from the retry avoidance buffer. Thus, even if the write error occurs in the serial memory, the write processing and the read processing may be both efficiently executed without any occupancy of the communication band to the serial memory. 
         [0142]    Also, according to Embodiment 1, even if the write error occurs in the serial memory, no retry to the serial memory is performed. Thus, the occupancy of the communication band to the serial memory may be avoided. Moreover, an increase in power consumption of the transmission apparatus may be suppressed without the request to increase the transmission rate of a transceiver (Serdes) that is an IF with the serial memory in order to secure a band for a retry. 
       Embodiment 2 
       [0143]    In Embodiment 2, description is given of a configuration example of avoiding a write access to the same bank during a read retry to the serial memory  141 . 
         [0144]    When the ReadData during the data read from the serial memory  141  described in Embodiment 1 is failed, there is data in the serial memory  141 , and thus a read retry is unavoidable. In this event, the conflict settlement unit  134   b  settles a write access to the same bank in the serial memory  141 , in which the read retry has been performed, thereby putting a write operation on standby. As a result, a write band is lost. Note that a write operation may be normally performed to a bank different from the bank in which the read retry has been performed. 
         [0145]      FIG. 13  is a diagram illustrating a configuration example of a memory controller part of a transmission apparatus according to Embodiment 2. The entire configuration ( FIG. 1 ) is the same as that of Embodiment 1. As illustrated in  FIG. 13 , a function of a bank management control unit  1301  is added to the memory controller  135  ( FIG. 2 ) described in Embodiment 1. The bank management control unit  1301  controls to avoid simultaneous read and write to the same banks in the serial memory  141 . 
         [0146]      FIG. 14  is a sequence diagram illustrating a processing example of avoiding a write access to the same bank during a read retry in the transmission apparatus according to Embodiment 2. The memory controller  135  and the serial memory  141  perform the following processing. 
         [0147]    (1) A read request (Read1) issued as an event by the user circuit (memory control unit  134 ) is transmitted to the memory controller  135  and the Serdes  135   a.    
         [0148]    (2) The memory controller  135  compares a target address of Read1 with an address in the retry avoidance buffer  203 . 
         [0149]    (3) When the addresses do not correspond as a result of the comparison, the memory controller  135  issues Read1 to the serial memory  141 . 
         [0150]    (4) The serial memory  141  returns ReadData1. In this event, if ReadData is failed (uncorrectable data as a result of ECC), the serial memory  141  controls the memory controller  135  not to issue Write when a Write request arrives at the same bank as Read1. 
         [0151]    (4)′ The memory controller  135  checks if ReadData is failed. 
         [0152]    (5) Since ReadData is failed, the memory controller  135  issues retry Read1 to the serial memory  141 . 
         [0153]    (6) It is assumed that a write request (Write1) is issued to the memory controller  135  from the user circuit at approximately the same timing as the retry Read1. 
         [0154]    (7) In this case, the bank management control unit  1301  in the memory controller  135  determines whether or not Write1 is accessible. In other words, the bank management control unit  1301  determines if Write1 is access to the same bank as Read1. In the example of  FIG. 14 , since Read1 and Write1 are simultaneous access to the same bank, control is performed not to issue Write1 (S 3 ). In this case, the memory controller  135  holds data WriteData of Write1 in the retry avoidance buffer  203 . 
         [0155]    (7)′ The memory controller  135  permits access from the user circuit after waiting for a predetermined period of time (about access time of Write1) to pass. 
         [0156]    (8) Thereafter, the memory controller  135  returns data (ReadData) of the retry Read1 from the serial memory  141  to the user circuit. Note that, when ReadData is OK (correctable data as a result of ECC) and after the data is returned to the user circuit, Write access to the same bank as Read1 may be processed. 
         [0157]    (Processing Example During Data Write/Read) 
         [0158]    In Embodiment 2, as in the case of Embodiment 1, data write processing ( FIGS. 6 to 8 ) and read processing ( FIGS. 9 to 12 ) are performed using the data processing content example illustrated in  FIGS. 6 to 12 . 
         [0159]      FIG. 15  is a flowchart illustrating a data processing content example in the transmission apparatus according to Embodiment 2. In  FIG. 15 , some of the processing contents during data write are different from those of the processing in Embodiment 1 ( FIG. 7 ). In  FIG. 15 , the same processing contents as those in  FIG. 7  are denoted by the same reference numerals (numbers). 
         [0160]    After the processing by the user circuit (memory control unit  134 ) illustrated in  FIG. 6  described above, the memory controller  135  executes processing illustrated in  FIG. 15 . First, the memory controller  135  waits for a write command (address, data, and others) to be received (S 701 ). 
         [0161]    Upon receipt of the write command, the memory controller  135  changes the write status flag in the retry avoidance buffer  203  to a Stop state. Also, the memory controller  135  checks an empty region (region with the flag “0” in  FIG. 3 ), stores write data WD in the empty region, and changes the flag of the region storing the write data to “1” (S 702 ). 
         [0162]    Next, the memory controller  135  generates a write command (address, data, and others) to the serial memory  141  (S 703   a ). 
         [0163]    Then, the bank management control unit  1301  in the memory controller  135  checks if there is no read access to the same bank in the serial memory  141  (S 703   b ). If there is access to the same bank of write/read by a read retry or the like to the serial memory  141  (S 703   b:  No), the bank management control unit  1301  stops issuance of a write command (S 1010  and S 1012  in  FIG. 10 ). Thereafter, the processing returns to S 701 . On the other hand, if there is no access to the same bank of write/read (S 703   b:  Yes), the memory controller  135  issues a write command without stopping the issuance thereof (S 703   c ). Then, the write data WD is multiplexed and outputted to the Serdes  135   a  on the memory controller  135  side (SA). 
         [0164]    Thereafter, the memory controller  135  changes the write status flag in the retry avoidance buffer  203  to the ready state (S 704 ), and waits for a write ACK to be received from the serial memory  141  (S 705 ). 
         [0165]    Then, the memory controller  135  determines whether or not the write ACK received from the serial memory  141  is positive (S 706 ). If the write ACK is positive (S 706 : Yes), the write of the write data WD into the serial memory  141  is successfully completed, and the flag of the corresponding address in the write data WD stored in the retry avoidance buffer  203  is changed to “0” (S 707 ). Then, the processing returns to S 701 . 
         [0166]    On the other hand, if the write ACK is not positive but is negative (S 706 : No), the processing returns to S 701 . In this case, the flag of the corresponding address in the write data WD in the retry avoidance buffer  203  remains as “1”, and the write data WD is held in the retry avoidance buffer  203 . After the processing by the memory controller  135  illustrated in  FIG. 15  described above, the serial memory  141  executes processing illustrated in  FIG. 8 . 
         [0167]    According to Embodiment 2, the same advantageous effect as that of Embodiment 1 may be achieved, and a write retry to the serial memory may be reduced in response to a data error occurring probabilistically in the Serdes. This makes it possible to avoid occupancy of the communication band to the serial memory for an execution time of a write retry to the serial memory. 
         [0168]    Moreover, according to Embodiment 2, when a read retry occurs to the serial memory, write access to the same bank in which the read retry is being performed in the serial memory may be avoided. Note that the write data in this event may be stored in the retry avoidance buffer and write processing may be executed. 
       Embodiment 3 
       [0169]    In Embodiment 3, description is given of a configuration example of an autonomous retry to write the data stored in the retry avoidance buffer  203  into the serial memory  141  by using blank time. 
         [0170]      FIG. 16  is a diagram illustrating a configuration example of a memory controller part of a transmission apparatus according to Embodiment 3. The entire configuration ( FIG. 1 ) is the same as that of Embodiment 1. As illustrated in  FIG. 16 , a function of an autonomous retry control unit  1601  is added to the memory controller  135  ( FIG. 13 ) described in Embodiment 2. Also, a blank time monitoring circuit  1602  is provided outside the memory controller  135 . The blank time monitoring circuit  1602  may be a part of the function of the reception unit  132  (see  FIG. 1 ), for example. 
         [0171]    The blank time monitoring circuit  1602  includes an input state monitoring unit  1602   a  to monitor an input state of a packet to the user circuit (or the memory controller  135 ). The input state monitoring unit  1602   a  outputs autonomous accessible state (autonomous retriable state) information (S 4 ) to the autonomous retry control unit  1601  when a predetermined blank time is generated in an inputted packet. 
         [0172]    Upon receipt of the autonomous retriable state information (S 4 ), the autonomous retry control unit  1601  reads data stored in the retry avoidance buffer  203  and writes the data into the serial memory  141 . 
         [0173]      FIG. 17  is a sequence diagram illustrating an autonomous retry processing example in the transmission apparatus according to Embodiment 3. The memory controller  135 , the blank time monitoring circuit  1602 , and the serial memory  141  perform the following processing. 
         [0174]    (1) A write request (Write1) as an event is transmitted to the memory controller  135  and the Serdes  135   a.    
         [0175]    (2) The memory controller  135  stores an address (Add1) and data (Data1) of Write1 in the retry avoidance buffer  203 . 
         [0176]    (3) The memory controller  135  issues a write command (Write1) to the serial memory  141 . 
         [0177]    (3)′ The memory controller  135  restricts (Stop) access to the user circuit  134 . 
         [0178]    (4) Here, write to the serial memory  141  is failed, write failure (Ack1 (NG)) is returned to the memory controller  135 . The memory controller  135  sets up a flag indicating the Write failure of the corresponding data. 
         [0179]    (5) The memory controller  135  holds the corresponding address (Add1) and data (Data1) in the retry avoidance buffer  203 . 
         [0180]    (5)′ The memory controller  135  permits access to the user circuit  134  (ready). 
         [0181]    (6) The user circuit  134  issues a write request (Write2, Add2, and Data2) to the memory controller  135 . 
         [0182]    (7) The memory controller  135  issues a write command (Write2) to the serial memory  141 . 
         [0183]    (7)′ The memory controller  135  restricts (Stop) access to the user circuit  134 . 
         [0184]    (8) When the serial memory  141  has successfully performed the data write, Ack2 (positive) is returned to the memory controller  135 . 
         [0185]    (9) The memory controller  135  deletes the corresponding address and data (Add2 and Data2) and the like in the retry avoidance buffer  203 . 
         [0186]    (9)′ The memory controller  135  permits access to the user circuit  134  (ready). 
         [0187]    (10) Thereafter, when a blank time is generated as a result of monitoring a received packet by the input state monitoring unit  1602   a  in the blank time monitoring circuit  1602 , the autonomous retriable state information S 4  is notified to the autonomous retry control unit  1601  in the memory controller  135 . 
         [0188]    (10)′ The autonomous retry control unit  1601  checks if there is data in the retry avoidance buffer  203 . The autonomous retry control unit  1601  moves to (11) if there is data, and does not do anything if there is no data. 
         [0189]    (11) The autonomous retry control unit  1601  issues a write request (Write1′) and writes data into the serial memory  141 . 
         [0190]    (11)′ The memory controller  135  restricts (Stop) access to the user circuit  134 . 
         [0191]    (12) The serial memory  141  returns Ack1′ (positive) to the memory controller  135 . 
         [0192]    (13) The memory controller  135  deletes the corresponding address and data (Add1 and Data1) and the like in the retry avoidance buffer  203 . 
         [0193]    (13)′ The memory controller  135  permits access to the user circuit  134  (ready). 
         [0194]    Upon detection of a blank time, the input state monitoring unit  1602   a  in the blank time monitoring circuit  1602  performs the processing of (10) to (13)′ described above. On the other hand, when no blank time is detected, the processing of (10) to (13)′ is put on standby until there is an instruction from the user circuit  134 . 
         [0195]    (Processing Example During Data Write/Read) 
         [0196]    Hereinafter, description is given of a processing example of adding the autonomous retry processing to the data write processing and read processing described in Embodiment 2. 
         [0197]      FIGS. 18 and 19  are flowcharts each illustrating a data processing content example in the transmission apparatus according to Embodiment 3. In  FIG. 18 , some of the processing contents during data write are different from those of the processing in Embodiment 1 ( FIG. 6 ). 
         [0198]    First, in  FIG. 18 , the same processing contents as those in  FIG. 6  are denoted by the same reference numerals (numbers).  FIG. 18  illustrates processing performed by the memory control unit  134  that is the user circuit. The user circuit determines whether or not there is write data (S 601 ). 
         [0199]    If there is no write data (S 601 : No), the input state monitoring unit  1602   a  in the blank time monitoring circuit  1602  notifies the autonomous retry control unit  1601  in the memory controller  135  of information S 2  of change to the autonomous retriable (enabled) state (S 601   a ). Then, the processing returns to S 601 . On the other hand, if there is write data (S 601 : Yes), the input state monitoring unit  1602   a  in the blank time monitoring circuit  1602  notifies the autonomous retry control unit  1601  in the memory controller  135  of information S 2  of the autonomous unretriable (disabled) state (S 601   b ). 
         [0200]    Next, the user circuit  134  determines, based on a status flag or the like in the retry avoidance buffer  203 , whether the data may be written into the serial memory  141  (ready state) (S 602 ). 
         [0201]    If the data write is not in the ready state (S 602 : No), the processing returns to S 601 . On the other hand, if the data write is in the ready state (S 602 : Yes), the conflict settlement unit  134   b  determines if there is no simultaneous access to the same Bank with the read side (S 603 ). 
         [0202]    Here, the conflict settlement unit  134   b  is set to give priority to write processing over read processing. Thus, the processing moves to S 604  in any case regardless of the determination result (S 603 : Yes/No) in S 603 . 
         [0203]    In S 604 , the user circuit issues a write command (address, data, and others) (S 604 ). 
         [0204]    After the processing by the user circuit (memory control unit  134 ) illustrated in  FIG. 18  described above, the memory controller  135  executes processing illustrated in  FIG. 7 . Processing illustrated in  FIG. 19  includes the processing (bank management control) according to Embodiment 2 ( FIG. 15 ). First, the memory controller  135  waits for a write command (address, data, and others) to be received (S 701 ). 
         [0205]    Upon receipt of the write command, the memory controller  135  changes the write status flag in the retry avoidance buffer  203  to a Stop state. Also, the memory controller  135  checks an empty region (region with the flag “0” in  FIG. 3 ), stores write data WD in the empty region, and changes the flag of the region storing the write data to “1” (S 702 ). 
         [0206]    Next, the memory controller  135  generates a write command (address, data, and others) to the serial memory  141  (S 703   a ). 
         [0207]    Then, the bank management control unit  1301  in the memory controller  135  checks if there is no read access to the same bank in the serial memory  141  (S 703   b ). If there is access to the same bank of write/read by a read retry or the like to the serial memory  141  (S 703   b:  No), the bank management control unit  1301  stops issuance of a write command (S 1010  and S 1012  in  FIG. 10 ). Thereafter, the processing returns to S 701 . On the other hand, if there is no access to the same bank of write/read (S 703   b:  Yes), the memory controller  135  issues a write command without stopping the issuance thereof (S 703   c ). Then, the write data WD is multiplexed and outputted to the Serdes  135   a  on the memory controller  135  side (SA). 
         [0208]    Thereafter, the memory controller  135  changes the write status flag in the retry avoidance buffer  203  to the ready state (S 704 ), and waits for a write ACK to be received from the serial memory  141  (S 705 ). 
         [0209]    Then, the memory controller  135  determines whether or not the write ACK received from the serial memory  141  is positive (S 706 ). If the write ACK is positive (S 706 : Yes), the write of the write data WD into the serial memory  141  is successfully completed, and the flag of the corresponding address in the write data WD stored in the retry avoidance buffer  203  is changed to “0” (S 707 ). Then, the processing returns to S 701 . 
         [0210]    On the other hand, if the write ACK is not positive but is negative (S 706 : No), the processing returns to S 701 . In this case, the flag of the corresponding address in the write data WD in the retry avoidance buffer  203  remains as “1”, and the write data WD is held in the retry avoidance buffer  203 . After the processing by the memory controller  135  illustrated in  FIG. 19  described above, the serial memory  141  executes the processing illustrated in  FIG. 8 . 
         [0211]    Then, in Embodiment 3, processing of determining whether or not an autonomous retry is possible (S 710 ) is additionally performed. In this processing, the blank time monitoring circuit  1602  in the user circuit  134  determines an autonomous retriable state (enabled/disabled) by monitoring, with a flag, the autonomous retriable state and whether or not there is data in the retry avoidance buffer  203 . If the autonomous retry is possible, the write is changed to the Stop state (S 711 ), and data is read from the retry avoidance buffer  203  to execute the processing of S 703   a.    
         [0212]      FIG. 20  is a flowchart illustrating another data processing content example in the transmission apparatus according to Embodiment 3. The processing example of  FIG. 19  includes the processing according to Embodiments 1 and 2. Meanwhile,  FIG. 20  illustrates a processing example of adding the processing according to Embodiment 3 (autonomous retry) to Embodiment 1 while omitting the processing according to Embodiment 2 (the same bank control). 
         [0213]    After the processing illustrated in  FIG. 18 , the memory controller  135  executes the processing illustrated in  FIG. 19  and waits for a write command (address, data, and others) to be received (S 701 ). 
         [0214]    Upon receipt of the write command, the memory controller  135  changes the write status flag in the retry avoidance buffer  203  to a Stop state. Also, the memory controller  135  checks an empty region (region with the flag “0” in  FIG. 3 ), stores write data WD in the empty region, and changes the flag of the region storing the write data to “1” (S 702 ). 
         [0215]    Next, the memory controller  135  generates a write command (address, data, and others) to the serial memory  141 , and issues the write command (S 703 ). Thus, the write data WD is multiplexed and outputted to the Serdes  135   a  on the memory controller  135  side (SA). 
         [0216]    Thereafter, the memory controller  135  changes the write status flag in the retry avoidance buffer  203  to a ready state (S 704 ), and waits for a write ACK to be received from the serial memory  141  (S 705 ). 
         [0217]    Then, the memory controller  135  determines whether or not the write ACK received from the serial memory  141  is positive (S 706 ). If the write ACK is positive (S 706 : Yes), the write of the write data WD into the serial memory  141  is successfully completed, and the flag of the corresponding address in the write data WD stored in the retry avoidance buffer  203  is changed to “0” (S 707 ). Then, the processing returns to S 701 . 
         [0218]    On the other hand, if the write ACK is not positive but is negative (S 706 : No), the processing returns to S 701 . In this case, the flag of the corresponding address in the write data WD in the retry avoidance buffer  203  remains as “1”, and the write data WD is held in the retry avoidance buffer  203 . After the processing by the memory controller  135  illustrated in  FIG. 20  described above, the serial memory  141  executes the processing illustrated in  FIG. 8 . 
         [0219]    Then, in  FIG. 20 , processing of determining whether or not an autonomous retry is possible (S 710 ) is additionally performed. In this processing, the blank time monitoring circuit  1602  in the user circuit  134  determines an autonomous retriable state (enabled/disabled) by monitoring, with a flag, the autonomous retriable state and whether or not there is data in the retry avoidance buffer  203 . If the autonomous retry is possible, the write is changed to the Stop state (S 711 ), and data is read from the retry avoidance buffer  203  to execute the processing of S 703 . 
         [0220]    According to Embodiment 3, the same advantageous effect as that of Embodiment 1 may be achieved, and a write retry to the serial memory may be reduced in response to a data error occurring probabilistically in the Serdes. This makes it possible to avoid occupancy of the communication band to the serial memory for an execution time of a write retry to the serial memory. 
         [0221]    Moreover, according to Embodiment 3, the same advantageous effect as that of Embodiment 2 may be achieved, and when a read retry occurs to the serial memory, write access to the same bank in which the read retry is being performed in the serial memory may be avoided. Note that the write data in this event may be stored in the retry avoidance buffer and write processing may be executed. 
         [0222]    In Embodiments 1 and 2 described above, the serial memory  141  is used as a memory (packet buffer  141   a ) from which packets are read upon elapse of a certain period of time after the packets are written, even though the read order changes according to the priority. In Embodiment 3, the data stored in the retry avoidance buffer  203  is written into the serial memory  141  by the autonomous retry. Thus, an increase in capacity of the retry avoidance buffer  203  is not requested. Moreover, the condition of the serial memory  141  as the packet buffer  141   a  may be eased or canceled. 
         [0223]      FIG. 21  is a sequence diagram illustrating a state of band occupancy in an existing transmission apparatus. Hereinafter, description is given of processing upon failure of data write to the serial memory  141  in the existing transmission apparatus including no retry avoidance buffer  203 . 
         [0224]    (1) A write request (Write1) as an event is transmitted to the memory controller  135  (and the Serdes  135   a ). 
         [0225]    (2) The memory controller  135  issues a write command (Write1) to the serial memory  141 . 
         [0226]    (2)′ The memory controller  135  restricts (Stop) access to the user circuit  134 . 
         [0227]    (3) When the data write fails, the serial memory  141  returns write failure (Ack1 (NG)) to the memory controller  135 . 
         [0228]    (4) The memory controller  135  retries the write (Write1) to the serial memory  141 . 
         [0229]    (5) When the data write is successfully performed, the serial memory  141  returns Ack1 (positive) to the memory controller  135 . 
         [0230]    (5)′ The memory controller  135  permits access to the user circuit  134  (ready). 
         [0231]    (6) Then, the memory controller  135  permits access (read request in the example of  FIG. 21 ). 
         [0232]    In the existing processing described above, the memory controller  135  retries the write to the serial memory  141  due to failure that probabilistically occurs during the data write to the serial memory  141 . Thus, in the existing transmission apparatus, next access is put on standby during a period T requested for a retry, and causes occupancy of the communication band to the serial memory  141 . When the reception buffer  131  becomes full, a request to stop packet transmission is made to the previous transmission apparatus which transmits packets. Thus, when failure of data write probabilistically occurs in the serial memory  141 , the communication band to the serial memory  141  is occupied. 
         [0233]    On the other hand, according to the respective embodiments, as illustrated in  FIG. 4  and the like, even if failure of data write probabilistically occurs, the data is stored in the retry avoidance buffer  203  by using the high-speed serial memory  141 . Thus, the data may be read from the retry avoidance buffer  203  without performing a retry to the serial memory  141 . Since a write retry to the serial memory  141  is reduced, the occupancy of the communication band of the serial memory  141  may be reduced. Thus, the write processing and read processing may be both efficiently performed. 
         [0234]    Moreover, since no retry to the serial memory  141  is performed, an increase in transmission rate of a transceiver (Serdes or the like) that is an IF with the serial memory in order to occupy a band for a retry is not requested. As a result, an increase in power consumption of the transmission apparatus may be suppressed. 
         [0235]    All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.