Abstract:
A source driver is provided with: a D/A converter outputting a gray-level voltage corresponding to pixel data; and a source amplifier outputting a drive voltage in response to the gray-level voltage. The source amplifier includes: an NMOS differential pair including first and second NMOS transistors; a PMOS differential pair including first and second PMOS transistors; an output circuitry outputting a drive voltage in response to currents flowing through the NMOS and PMOS differential pairs; a first input level conversion circuit generating a first level-converted voltage through input level conversion on the gray-level voltage in response to the gray-level voltage and/or a polarity of the drive voltage defined with respect to a common level on an opposite electrode of a liquid crystal display panel and feeding the first level-converted voltage to gates of the first NMOS transistor and the first PMOS transistor; and a second input level conversion circuit generating a second level-converted voltage through input level conversion on the drive voltage in response to the gray-level voltage and/or the polarity of the drive voltage and feeding the second level-converted voltage to gates of the second NMOS transistor and the second PMOS transistor.

Description:
INCORPORATION BY REFERENCE 
       [0001]    This application claims the benefit of priority based on Japanese Patent Application No. 2010-028435, filed on Feb. 12, 2010, the disclosure of which is incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a source driver and a liquid crystal display device incorporating the same, and more particularly relates to source amplifier architecture in a source driver for driving a liquid crystal display panel. 
         [0004]    2. Description of the Related Art 
         [0005]    In recent years, liquid crystal display devices used in televisions and personal computer monitors have been increased in the size and definition. This requires a source driver which drives greater capacitive loads (such as source electrodes) within a liquid crystal display panel in a liquid crystal display device at high speed with reduced power consumption. In particular, the number of gray-levels is increased in a high-definition color liquid crystal display panel; recent liquid crystal display devices support 1,670,000-color display, in which each gray-level of red, green and blue is represented by 8-bit data, while conventional liquid crystal display devices only support 260,000-color display, in which each gray-level is represented by 6-bit data. 
         [0006]    In general, a source driver drives source electrodes (data lines) of the liquid crystal display panel with differential amplifiers. Specifically, gamma voltages applied from outside are subjected to voltage division with resistors to generate gray-level voltages corresponding to allowed grayscale levels of the liquid crystal pixels, respectively, and the gray-level voltages are selected by D/A converters. The selected gray-level voltages are inputted to the differential amplifiers configured as voltage followers which provide impedance conversion. The outputs of the differential amplifiers are connected to the source electrodes of the liquid crystal display panel, and the differential amplifiers drive respective pixels of the liquid crystal display panel with drive voltages having substantially same voltage levels as the selected gray-level voltages. Differential amplifiers which are integrated within a source driver to drive source electrodes of a liquid crystal display panel are often referred to as source amplifiers. The source amplifiers may also provide fine adjustments of the drive voltages. 
         [0007]      FIG. 1  shows an exemplary circuit configuration of a differential amplifier used as the source amplifier. The differential amplifier shown in  FIG. 1  is a so-called rail-to-rail amplifier and depicted as a typical circuit in textbooks, famous documents and the like (See Japanese Patent Application Publications Nos. P2007-202127A and P2006-94534A, for example). The differential amplifier shown in  FIG. 1  is schematically provided with an input stage  101 , an intermediate stage  2  and an output stage  3 .  FIG. 2  is a simplified illustration of the circuit shown in  FIG. 1 . 
         [0008]    The input stage  101  is provided with PMOS transistors MP 11 , MP 12 , NMOS transistors MN 11 , MN 12  and current sources I 11  and I 12 . The PMOS transistors MP 11  and MP 12  form a PMOS differential pair, and the NMOS transistors MN 11  and MN 12  form an NMOS differential pair. The sources of the PMOS transistors MP 11  and MP 12  are commonly connected to the current source I 12 , and the sources of the NMOS transistors MN 11  and MN 12  are commonly connected to the current source I 11 . The PMOS transistor MP 11  and the NMOS transistor MN 11  have gates commonly-connected to an input terminal IN 11 , and the PMOS transistor MP 12  and the NMOS transistor MN 12  have gates commonly-connected to an input terminal IN 12 . It should be noted here that the input stage  101 , which includes both of the PMOS and NMOS differential pairs, provides a rail-to-rail operation. The current source I 11  has a function for supplying a bias current to the NMOS differential pair and includes an NMOS transistor which has a gate supplied with a bias voltage BN 1 . The current source I 12 , on the other hand, has a function for supplying a bias current to the PMOS differential pair and includes a PMOS transistor having a gate supplied with a bias voltage BP 1 . 
         [0009]    The intermediate stage  2  and the output stage  3  function as an output circuitry for outputting an output voltage from the amplifier output OUT in response to the currents through the PMOS transistors MP 11 , MP 12  and the NMOS transistors MN 11  and MN 12 . In detail, the intermediate stage  2  includes PMOS transistors MP 43  to MP 48  and NMOS transistors MN 43  to MN 48 . A bias voltage BP 2  is supplied to the PMOS transistors MP 45  and MP 46 , and a bias voltage BN 2  is supplied to the NMOS transistors MN 45  and MN 46 . Moreover, bias voltages BP 3  and BP 4  are supplied to the PMOS transistors MP 47  and MP 48 , respectively, and bias voltages BN 3  and BN 4  are supplied to the NMOS transistors MN 47  and MN 48 , respectively. The PMOS transistors MP 43  to MP 46  form a first folded cascode current mirror, and the NMOS transistors MN 43  to MN 46  form a second folded cascode current mirror. On the other hand, the PMOS transistor MP 47  and the NMOS transistor MN 47  form a first floating current source, and the PMOS transistor MP 48  and the NMOS transistor MN 48  form a second floating current source. That is, the intermediate stage  2  is provided with a folded cascode current mirror composed of the PMOS transistors, a folded cascode current mirror composed of the NMOS transistors, and two floating current sources provided between the current mirrors. 
         [0010]    The output stage  3  is provided with: a PMOS transistor MP 49  connected between the amplifier output OUT and a positive power source line to which a positive power source voltage VDD is supplied; and an NMOS transistor MN 49  connected between the amplifier output OUT and a negative power source line to which a negative power source voltage (ground voltage) VSS is supplied. The amplifier output OUT is connected to the input terminal IN 12  of the input stage  101 . In addition, a capacitive element C 1  is connected between the amplifier output OUT and the source of the PMOS transistor MP 46  (the drain of the MP 44 ) for phase compensation, and a capacitive element C 2  is connected between the amplifier output OUT and the source of the NMOS transistor MN 46  (the drain of the MN 44 ) for phase compensation. 
         [0011]    The differential amplifier having the above-described configuration forms a voltage follower, and a voltage approximately coincident with the voltage supplied to the input terminal IN 11  is outputted from the amplifier output OUT.  FIG. 2  is a schematic diagram showing the configuration of the differential amplifier shown in  FIG. 1  for easy understanding. 
         [0012]    In the following, a description is given of the allowed input voltage range of the differential amplifier shown in  FIG. 1  ( FIG. 2 ), referring to  FIG. 3 . In order to attain the rail-to-rail operation, the input stage  101  includes both of the NMOS differential pair (namely, the NMOS transistors MN 11 , MN 12 ) and the PMOS differential pair (namely, the PMOS transistors MP 11 , MP 12 ). When a voltage VIN 11  inputted to the input terminal IN 11  is in a range close to the negative power source voltage VSS, the PMOS differential pair (MP 11 , MP 12 ) operates, and both of the PMOS and NMOS transistor differential pairs operate when the voltage VIN 11  in the middle voltage range. Also, when the voltage VIN 11  is in a range close to the positive power source voltage VDD, only the NMOS differential pair (MN 11 , MN 12 ) operates. Accordingly, the input stage  101  of the differential amplifier in  FIG. 1  is operated in the entire input voltage range from the negative power source voltage VSS to the positive power source voltage VDD. 
         [0013]    When a liquid crystal display panel is driven, the application of a direct current voltage may cause deterioration of the liquid crystal, depending on the characteristics of the liquid crystal. Thus, an alternating voltage is applied to each pixel to avoid the liquid crystal being deteriorated. For this reason, polarities of the drive voltages of the liquid crystal display panel are switched. In a case of a so-called common constant drive, a common voltage V COM  of about VDD/2 is applied to the common electrode (opposite electrode) of the liquid crystal display panel. Hereinafter, a drive voltage in a range between the negative power source voltage VSS and the common voltage V COM  is referred to as a negative drive voltage and a drive voltage in a range between the common voltage V COM  and the positive power source voltage VDD is referred to as a positive drive voltage. In a liquid crystal display device having a typical configuration, a polarity signal (often, denoted by symbol POL) is supplied to each source driver to specify the polarity of the respective drive voltages. 
         [0014]    It should be noted that, in an actual panel drive, the input voltage inputted to the source amplifier are not set to the positive power source voltage VDD, the voltage VDD/2 equal to half thereof, or the negative power source voltage VSS. An input voltage in a range from VSS+α to VDD/2−α is inputted for outputting a negative drive voltage, and an input voltage in a range from VDD/2+α to VDD−α is inputted for outputting a positive drive voltage. The offset voltage a typically ranges from 0.1 V to 0.2 V in a currently used panel. It should be noted that, in the following, the offset voltage a of the input voltage is basically omitted for simplicity in describing the allowed range of the input voltage; the allowed range of the input voltage are defined only with the negative power source voltage VSS, VDD/2 and the positive power source voltage VDD. 
         [0015]    An input voltage of about VDD/2−VGM is fed to a source amplifier which outputs a negative drive voltage, and this source amplifier outputs an output voltage corresponding to the input voltage fed thereto, where VGM is a gray-level voltage required to set a certain pixel to a particular gray-level (namely, a voltage applied between the pixel electrode in the pixel and the opposite electrode). On the other hand, an input voltage of about VDD/2+VGM is fed to a source amplifier which outputs a positive drive voltage, and this source amplifier outputs an output voltage corresponding to the input voltage fed thereto. The difference between the output voltage V OUTP  actually outputted when the input voltage is VDD/2+VGM and the output voltage V OUTN  actually outputted when the input voltage is VDD/2−VGM is referred to as peak-to-peak voltage (Vpp), and variations in the peak-to-peak voltages of amplifiers are referred to as peak-to-peak voltage variations. In order to improve the accuracy of a drive voltage (namely, in order to actually output a desired drive voltage), the peak-to-peak voltage variations are desired to be 0 V. 
         [0016]    Although reduced peak-to-peak voltage variations are obtained in the configuration of  FIG. 1  (and  FIG. 2 ) in a case that the input voltage is in a middle voltage range away from the ground voltage VSS and the power source voltage VDD, the peak-to-peak voltage variations are increased in a voltage range close to the power source voltage VDD and a voltage range close to the ground voltage VSS. The reason will be discussed in the following. 
         [0017]    As shown in  FIG. 3 , for an input voltage VIN 11  in a voltage range close to the negative power source voltage VSS (0 V), only the PMOS differential pair (MP 11 , MP 12 ) operates in the differential amplifier in  FIG. 1 ; the NMOS differential pair (MN 11 , MN 12 ) does not operate. This is because the operation of the NMOS transistors MN 11  and MN 12 , which form the NMOS differential pair, requires the input voltage VIN 11  supplied to the gates of the NMOS transistors MN 11  and MN 12  to exceed the sum of the threshold voltage VT(MN 11 ) (=VT(MN 12 )) of the NMOS transistors MN 11  and MN 12  and the drain-to-source voltage VDS(I 11 ) of the NMOS transistor, which forms the current source I 11 . It should be noted here that enhancement-types are usually used as NMOS transistors integrated within an integrated circuit. When the input voltage VIN 11  is close to the negative power source voltage VSS (namely, when the gate voltages of the NMOS transistors MN 11  and MN 12  are close to the negative power source voltage VSS), however, the source voltages of the NMOS transistors MN 11  and MN 12  are also close to 0 V, resulting in that that the NMOS differential pair consisting of the NMOS transistors MN 11  of MN 12  does not operate. In  FIG. 3 , the lower limit value VT(MN 11 )+VDS(I 11 ) at which the NMOS transistor MN 11  operates is illustrated as the lower dotted line. 
         [0018]    When the input voltage is in a voltage range close to the power source voltage VDD (namely, when the gate voltages of the respective transistors in the PMOS differential pair are close to the power source voltage VDD), on the other hand, the source voltages are also close to the power source voltage VDD, resulting in that the PMOS differential pair (MP 11 , MP 12 ) does not operate. In  FIG. 3 , the upper limit value (VDD−VDS(I 12 )−VT(MP 11 )) at which the PMOS transistor MP 11  operates is illustrated as the upper dotted line, where VDS(I 12 ) is the drain-to-source voltage of the PMOS transistor forming the current source I 12 , and VT(MP 11 ) is the threshold voltage of the PMOS transistor MP 11 . 
         [0019]    When the input voltage VIN 11  is in a range between VT(MN 11 )+VDS(I 11 ) and VDD−VDS(I 12 )−|VT(MP 11 )| (namely, when the input voltage VIN 11  is in the middle voltage range), both of the PMOS differential pair (MP 11 , MP 12 ) and the NMOS differential pair (MN 11 , MN 12 ) operate. When the gray-level voltage VGM is small (namely, when the input voltage VIN 11  is in the middle voltage range), the peak-to-peak voltage variations are advantageously reduced since offset voltages of the PMOS differential pair (MP 11 , MP 12 ) and the NMOS differential pair (MN 11 , MN 12 ) are cancelled. The cancellation of the offset voltages will be described below with reference to  FIGS. 4A and 4B . 
         [0020]    For a certain amplifier output OUT_ 1 , let us define “offset 1 ” as an input-to-output offset of the corresponding source amplifier from the desired values V OUTP * and V OUTN * of the positive and negative drive voltages. When the input voltage VIN 11  is in the middle voltage range, the input-to-output offset offset 1  has a value determined on the operations of both of the PMOS differential pair (MP 11 , MP 12 ) and the NMOS differential pair (MN 11 , MN 12 ). 
         [0021]    In the middle voltage range, both of the differential pairs operate and thus the input-to-output offset offset 1  is unchanged between a case that the positive drive voltage is outputted and a case that the negative drive voltage is outputted. 
         [0022]    Accordingly, the peak-to-peak voltage Vpp_ 1  of the amplifier output OUT_ 1  is represented as follows: 
         [0000]        Vpp   — 1=( V   OUTP *+offset1)−( V   OUTN *+offset1),
 
         [0000]    for a case that the input-to-output offset of the amplifier output OUT_ 1  has a positive value with respect to the desired drive voltages, where V OUTP * is the desired value of the positive drive voltage to be outputted, and V OUTN * is the desired value of the negative drive voltage to be outputted. As is understood from the fact that offset 1  is cancelled in the above equation, the peak-to-peak voltage Vpp_ 1  of the amplifier output OUT_ 1  is finally obtained as V OUTP *−V OUTN *. 
         [0023]    For another amplifier output OUT_ 3 , let us define “offset 2 ” as the offset voltage thereof. When offset 2  has a negative value with respect to the desired output voltage, the peak-to-peak voltage Vpp_ 3  of the amplifier output OUT_ 3  for the same desired output voltage is represented as follows: 
         [0000]        Vpp   — 3=( V   OUTP *+offset2)−( V   OUTN *+offset2).
 
         [0000]    Similarly to the amplifier output OUT_ 1 , the offset 2  is cancelled, and the peak-to-peak voltage Vpp_ 3  of the amplifier output OUT_ 3  is finally obtained as V OUTP *−V OUTN *. 
         [0024]    As thus discussed, the peak-to-peak voltages Vpp of the amplifier outputs OUT_ 1  and OUT_ 3  are both V OUTP *−V OUTN *, and the peak-to-peak voltage variation between the amplifier outputs OUT_ 1  and OUT_ 3  is 0 V. That is, when the input voltage VIN 11  is in the middle voltage range, reduced peak-to-peak voltage variations are obtained. 
         [0025]    When the gray-level voltage VGM is high, (namely, when the input voltage VIN 11  is close to the negative power source voltage VSS or close to the positive power source voltage VDD), on the other hand, only one of the PMOS differential pair (MP 11 , MP 12 ) and the NMOS differential pair (MN 11 , MN 12 ) is operates, and the input-to-output offset is not cancelled. This undesirably increases the peak-to-peak voltage variations. Such increase in the peak-to-peak voltage variations will be discussed in the following with reference to  FIG. 4B . 
         [0026]    For the amplifier output OUT_ 1 , let us define “offset 1 ” as the input-to-output offset of the source amplifier from the desired value V OUTP * of the positive drive voltage, and define “offset 2 ” as the input-to-output offset of the source amplifier from the desired value V OUTN * of the negative drive voltage to be outputted. The input-to-output offset “offset 1 ” is the value for the case that only the NMOS differential pair (MN 11 , MN 12 ) operates, and the input-to-output offset offset 2  is the value for the case that only the PMOS differential pair (MP 11 , MP 12 ) operates. Thus, the input-to-output offsets offset 1  and offset 2  have different values. 
         [0027]    In one example, when the input-to-output offset offset 1  of the amplifier output OUT_ 1  is positive with respect to the desired value V OUTP * of the positive drive voltage and the input-to-output offset offset 2  is negative with respect to the desired value V OUTN * of the positive drive voltage, the peak-to-peak voltage Vpp_ 1  of the amplifier output OUT_ 1  is represented as follows: 
         [0000]        Vpp   — 1 =V   OUTP *+offset1 −V   OUTN *−offset2.
 
         [0000]    In this equation, the input-to-output offsets offset 1  and offset 2  are not cancelled, since the input-to-output offsets offset 1  and offset 2  have different values. 
         [0028]    Similarly, let us define “offset 3 ” and “offset 4 ” as the input-to-output offsets for the amplifier output OUT_ 3 . When the output offset offset 3  is negative with respect to the desired value V OUTP * of the positive drive voltage and the input-to-output offset offset 4  is positive with respect to the desired value V OUTN * of the negative drive voltage, the peak-to-peak voltage Vpp_ 3  of the amplifier output OUT_ 3  is represented as follows: 
         [0000]        Vpp   — 3 =V   OUTP *−offset3 −V   OUTN *−offset4.
 
         [0029]    Similarly to the amplifier output OUT_ 1 , the input-to-output offsets offset 3  and offset 4  are not cancelled. 
         [0030]    As thus discussed, the input-to-output offsets offset 1 , offset 2 , offset 3  and offset 4  are not cancelled for both of the amplifier outputs OUT_ 1 , OUT_ 3 , and the peak-to-peak voltages Vpp of the amplifier outputs OUT_ 1  and OUT_ 3  have different values. This results in that the peak-to-peak voltage variations are increased, making it difficult to attain higher definition of the drive voltages. 
       SUMMARY 
       [0031]    In an aspect of the present invention, a source driver for driving a liquid crystal display panel is provided. The source driver is provided with: a D/A converter outputting a gray-level voltage corresponding to pixel data; and a source amplifier outputting a drive voltage in response to the gray-level voltage. The source amplifier includes: an NMOS differential pair including first and second NMOS transistors; a PMOS differential pair including first and second PMOS transistors; an output circuitry outputting a drive voltage in response to currents flowing through the NMOS and PMOS differential pairs; a first input level conversion circuit generating a first level-converted voltage through input level conversion on the gray-level voltage in response to the gray-level voltage and/or a polarity of the drive voltage defined with respect to a common level on an opposite electrode of the liquid crystal display panel and feeding the first level-converted voltage to gates of the first NMOS transistor and the first PMOS transistor; and a second input level conversion circuit generating a second level-converted voltage through input level conversion on the drive voltage in response to the gray-level voltage and/or the polarity of the drive voltage and feeding the second level-converted voltage to gates of the second NMOS transistor and the second PMOS transistor. 
         [0032]    The present invention effectively improves the peak-to-peak voltage variations of the source amplifier in the source driver. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0033]    The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which: 
           [0034]      FIG. 1  is a circuit diagram showing an exemplary configuration of a conventional source amplifier; 
           [0035]      FIG. 2  is a schematic view showing the configuration of the conventional source amplifier; 
           [0036]      FIG. 3  is a graph showing the relation between the input voltage and the gate voltages of transistors in the differential pair in the conventional source driver; 
           [0037]      FIG. 4A  is a graph showing a peak-to-peak voltage variation when the input voltage is in a middle voltage range, in the conventional source amplifier; 
           [0038]      FIG. 4B  is a graph showing a peak-to-peak voltage variation when the input voltage is close to the positive power source voltage or the negative power source voltage, in the conventional source amplifier; 
           [0039]      FIG. 5A  is a block diagram showing an exemplary configuration of a liquid crystal display device in a first embodiment of the present invention; 
           [0040]      FIG. 5B  is a block diagram showing an exemplary configuration of a source driver in the first embodiment; 
           [0041]      FIG. 5C  is a circuit diagram showing an exemplary configuration of a source amplifier in the first embodiment; 
           [0042]      FIG. 6  is a graph showing an exemplary relation between an input voltage and gate voltages of transistors in a differential pair, in the first embodiment; 
           [0043]      FIG. 7A  is a graph showing a simulation result of input-to-output offsets of the source amplifiers in the conventional circuit and the first embodiment; 
           [0044]      FIG. 7B  is a graph showing a simulation result of amplitude differences of the source amplifiers in the conventional circuit and the first embodiment; 
           [0045]      FIG. 8A  is a graph showing a simulation result of peak-to-peak voltage variations of the conventional circuit; 
           [0046]      FIG. 8B  is a graph of a simulation result of peak-to-peak voltage variations of the source amplifier in this embodiment; 
           [0047]      FIG. 9A  is a block diagram showing an exemplary configuration of a source driver in a second embodiment of the present invention; 
           [0048]      FIG. 9B  is a circuit diagram showing an exemplary configuration of a source amplifier in the second embodiment; 
           [0049]      FIG. 10  is a graph showing an exemplary relation between an input voltage and gate voltages of transistors in a differential pair, in the second embodiment; 
           [0050]      FIG. 11  is a circuit diagram showing an exemplary configuration of a source amplifier in a third embodiment; 
           [0051]      FIG. 12  is a graph showing an exemplary relation between an input voltage and gate voltages of transistors in a differential pair; 
           [0052]      FIG. 13  is a circuit diagram showing an exemplary configuration of a source amplifier in a fourth embodiment; and 
           [0053]      FIG. 14  is a graph showing an exemplary relation between an input voltage and gate voltages of transistors in a differential pair, in the fourth embodiment. 
       
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0054]    The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes. 
       First Embodiment 
       [0055]      FIG. 5A  is a block diagram showing an exemplary configuration of a liquid crystal display device in a first embodiment of the present invention. The liquid crystal display device of this embodiment is provided with a source driver  100 , a gate driver  200  and a liquid crystal display panel  300 . The source driver  100  drives source electrodes (data lines) within the liquid crystal display panel  300 . The gate driver  200  drives gate electrodes (gate lines) in the liquid crystal display panel  300 . Pixels are provided respective intersections of the source electrodes and the gate electrodes within the liquid crystal display panel  300 . 
         [0056]      FIG. 5B  is a block diagram showing an exemplary configuration of the source driver  100  in the first embodiment.  FIG. 5B  shows a circuit portion of the source driver  100  which drives two source electrodes (data lines) in the liquid crystal display panel  300 . 
         [0057]    The source driver  100  is provided with latches  21 , level shifters  22 , D/A converters  23 , a gray-level voltage generator circuit  24  and source amplifiers  25 . The latch  21  receives a pixel data D IN  and supplies through the level shifter  22  to the D/A converter  23 . In  FIG. 5B , symbols OUT_ 1  and OUT_ 2  denote two amplifier outputs OUT and symbols “D IN1 ” and “D IN2 ” denote the pixel data D IN  corresponding to the amplifier outputs OUT_ 1  and OUT_ 2 , respectively. The level shifters  22  provide signal level conversion to achieve signal level matching between the latches  21  and the D/A converters  23 . The gray-level voltage generator circuit  24  supplies a set of gray-level voltages which correspond to the respective allowed gray-levels of the pixels within the liquid crystal display panel  300 , to the D/A converters  23 . The gray-level voltages supplied to the D/A converters  23  include positive gray-level voltages (the gray-level voltages higher than the common voltage V COM ) and the negative gray-level voltages (the gray-level voltages lower than the common voltage V COM ). The D/A converters  23  select the gray-level voltages corresponding to the pixel data D IN1  and D IN2  received from the latches  21  out of the gray-level voltages received from the gray-level voltage generator circuit  24 , and output the selected gray-level voltages to the source amplifiers  25 . The source amplifiers  25  are formed as a voltage follower and output voltages approximately equal to the gray-level voltages received from the D/A converter  23  as the drive voltages from the amplifier outputs OUT_ 1  and OUT_ 2 . The amplifier outputs OUT_ 1  and OUT_ 2  are connected to the source electrodes (data lines) of the liquid crystal display panel  300 . Then, the drive voltages outputted from the amplifier outputs OUT_ 1  and OUT_ 2  are supplied to desired pixels in the liquid crystal display panel  300  to drive the pixels. 
         [0058]    The D/A converters  23  select the polarities of the selected gray-level voltages in response to a polarity signal POL. It should be noted here that the polarity signal POL is a signal which specifies the polarities of the drive voltages to be outputted from the respective source amplifiers  25  in the source driver  100 , as mentioned above. When the source driver  100  carries out a line inversion drive, for example, the D/A converters  23  and the source amplifiers  25  operate as follows: When the polarity signal POL is set to “H”, all of the D/A converters  23  output the positive gray-level voltages, and all of the source amplifiers  25  output the positive drive voltages in response to the positive gray-level voltages received from the D/A converters  23 . When the polarity signal POL is set to “L”, on the other hand, all of the D/A converters  23  output the negative drive voltages, and all of the source amplifiers  25  output the negative drive voltages in response to the negative gray-level voltages received from the D/A converters  23 . On the other hand, when the source driver  100  carries out a dot inversion drive, in response to the polarity signal POL, one of every two adjacent D/A converters  23  outputs a positive gray-level voltage and the other outputs a negative gray-level voltage. In response thereto, one of every two adjacent source amplifiers  25  outputs the corresponding positive drive voltage, and the other outputs the corresponding negative drive voltage. 
         [0059]      FIG. 5C  is a circuit diagram showing an exemplary configuration of the source amplifiers  25  in this embodiment. The source amplifiers  25  in the first embodiment are configured so that the input stage  101  is replaced with an input stage  1 , as compared with the conventional circuit in  FIG. 1 ; the configurations of the intermediate stage  2  and the output stage  3  are same as those shown in  FIG. 1 . A gray-level voltage selected by a D/A converter  23  is supplied to the input terminal IN 13 . That is, the input voltage VIN 13  on the input terminal IN 13  is identical to the gray-level voltage selected by the D/A converter  23 . Also, the output terminal of the output stage  3  (namely, the amplifier output OUT) is connected to the input terminal IN 14  to thereby achieve feed-back of the drive voltage outputted by the amplifier output OUT to the input stage  1 . 
         [0060]    The input stage  1  is provided with NMOS transistors MN 11  and MN 12  forming an NMOS differential pair, PMOS transistors MP 11  and MP 12  forming a PMOS differential pair, and a current source I 12 . The dimensions of the NMOS transistors MN 11  and MN 12  are equal, and the dimensions of the PMOS transistors MP 11  and MP 12  are equal. The sources of the NMOS transistors MN 11  and MN 12  are commonly connected to the current source I 11 , and the gates of the NMOS transistors MN 11  and MN 12  are connected to input nodes IN 11  and IN 12 , respectively. The drains of the NMOS transistors MN 11  and MN 12  are connected to the sources of PMOS transistors MP 45  and MP 46  of the intermediate stage  2 , respectively. On the other hand, the sources of the PMOS transistors MP 11  and MP 12  are commonly connected to the current source I 12 , and the gates of the PMOS transistors MP 11  and MP 12  are connected to the input nodes IN 11  and IN 12 , respectively. The drains of the PMOS transistors MP 11  and MP 12  are connected to the sources of the NMOS transistors MN 45 , MN 46  of the intermediate stage  2 , respectively. 
         [0061]    The input stage  1  further includes input level conversion circuits  4  and  5 . The input level conversion circuits  4  and  5  perform input level conversions on the input voltages inputted to the input terminals IN 13  and IN 14 , respectively. The input level conversions by the input level conversion circuits  4  and  5  are performed in response to the polarity signal POL. 
         [0062]    In detail, the input level conversion circuit  4  includes a PMOS source follower  11 , an NMOS source follower  12  and an input switch SW 11 . The PMOS source follower  11  is provided with a PMOS transistor MP 13  and a bias current source I 13 . The NMOS source follower  12  is provided with an NMOS transistor MN 13  and a bias current source I 14 . The gate of the PMOS transistor MP 13  serves as the input of the PMOS source follower  11 , and the source of the PMOS transistor MP 13  serves as the output of the PMOS source follower  11 . Similarly, the gate of the NMOS transistor MN 13  serves as the input of the NMOS source follower  12 , and the source of the NMOS transistor MN 13  serves as the output of the NMOS source follower  12 . 
         [0063]    The PMOS source follower  11  outputs a voltage higher than the voltage VIN 13  of the input terminal IN 13  by a predetermined voltage (specifically, by the threshold voltage of the PMOS transistor MP 13 ) from the source of the PMOS transistor MP 13 . The NMOS source follower  12  outputs a voltage lower than the voltage of the input terminal IN 13  by a predetermined voltage (specifically, by the threshold voltage of the NMOS transistor MN 13 ) from the source of the NMOS transistor MN 13 . That is, the source voltage VS(MP 13 ) of the PMOS transistor MP 13  and the source voltage VS(MN 13 ) of the NMOS transistor MN 13  are represented by the following equations: 
         [0000]        VS ( MP 13)= V IN13 +|VT ( MP 13)|, and 
         [0000]        VS ( MN 13)= V IN13 −|VT ( MN 13)|, 
         [0000]    where VIN 13  is the voltage of the input terminal IN 13 ; |VT(MP 13 )| is the absolute value of the threshold voltage of the PMOS transistor MP 13 ; and VT(MN 13 ) is the threshold voltage of the NMOS transistor MN 13 . 
         [0064]    The input switch SW 11  switches the connections between the input node IN 11  and the PMOS and NMOS source followers  11  and  12 , in response to the polarity signal POL. Specifically, when a negative drive voltage is to be outputted (namely, a drive voltage lower than the common voltage V COM  is to be outputted), the input switch SW 11  connects the input node IN 11  to the source of the PMOS transistor MP 13 . When a positive drive voltage is to be outputted (namely, when a drive voltage lower than the common voltage V COM  is outputted), on the other hand, the input switch SW 11  connects the input node IN 11  to the source of the NMOS transistor MN 13 . 
         [0065]    The input level conversion circuit  4  configured as described above outputs a voltage higher than the voltage VIN 13  of the input terminal IN 13  by |VT(MP 13 )|, or a voltage lower than the voltage VIN 13  by VT(MN 13 ), to the gates of the NMOS transistor MN 11  and the PMOS transistor MP 11 , in response to the polarity signal POL. 
         [0066]    Similarly, the input level conversion circuit  5  is provided with a PMOS source follower  13 , an NMOS source follower  14  and an input switch SW 12 . The PMOS source follower  13  is provided with a PMOS transistor MP 14  and a bias current source I 15 . The NMOS source follower  14  is provided with an NMOS transistor MN 14  and a bias current source I 16 . 
         [0067]    The PMOS source follower  13  outputs a voltage higher than the voltage of the input terminal IN 14  by a predetermined voltage (specifically, by the threshold voltage of the PMOS transistor MP 14 ) from the source of the PMOS transistor MP 14 . The NMOS source follower  14  outputs a voltage lower than the voltage of the input terminal IN 14  by a predetermined voltage (specifically, by the threshold voltage of the NMOS transistor MN 14 ) from the source of the NMOS transistor MN 14 . That is, the source voltage VS(MP 14 ) of the PMOS transistor MP 14  and the source voltage VS(MN 14 ) of the NMOS transistor MN 14  are represented by the following equations: 
         [0000]        VS ( MP 14)= V IN14 +|VT ( MP 14)|, and 
         [0000]        VS ( MN 14)= V IN14 −|VT ( MN 14)|, 
         [0000]    where VIN 14  is the voltage of the input terminal IN 14 ; |VT(MP 14 )| is the threshold voltage of the PMOS transistor MP 14 , and VT(MN 14 ) is the threshold voltage of the NMOS transistor MN 14 . 
         [0068]    Similarly, the input switch SW 12  switches the connections between the input node IN 12  and the PMOS and NMOS source followers  13  and  14 . Specifically, when the negative drive voltage is to be outputted, the input switch SW 12  connects the input node IN 12  to the source of the PMOS transistor MP 14 . When the positive drive voltage is outputted, on the other hand, the input switch SW 12  connects the input node IN 12  to the source of the NMOS transistor MN 14 . 
         [0069]    The dimensions of the respective transistors within the input level conversion circuits  4  and  5  are determined as follows: First, the dimensions of the PMOS transistor MP 13  are designed to satisfy the following equation. 
         [0000]      | VT ( MP 13)|&gt; VT ( MN 11)+ VDS ( I 11),  (1a)
 
         [0000]    where VT(MN 11 ) is the threshold voltage of the NMOS transistor MN 11 , and VDS(I 11 ) is the drain-to-source voltage of the NMOS transistor forming the current source ill. The dimensions of the PMOS transistors forming the bias current sources I 13  and I 15  are designed to be equal, and the dimensions of the PMOS transistors MP 13  and MP 14  are designed to be equal. Thus, the following equation is established at the same time: 
         [0000]      | VT ( MP 14)|&gt; VT ( MN 12)+ VDS ( I 11),  (1b)
 
         [0070]    Similarly, the dimensions of the NMOS transistor MN 13  are designed to satisfy the following equation: 
         [0000]      | VT ( MN 13)|&gt; VT ( MP 11)+ VDS ( I 12),  (2a)
 
         [0000]    where VT(MP 11 ) is the threshold voltage of the NMOS transistor MN 11 , and VDS(I 11 ) is the drain-to-source voltage of the NMOS transistor forming the current source I 11 . The dimensions of the PMOS transistors forming the bias current sources I 13  and I 15  are designed to be equal, and the dimensions of the PMOS transistors MP 13  and MP 14  are designed to be equal. Thus, the following equation is established at the same time: 
         [0000]        VT ( MN 14)&gt;| VT ( MP 12)|+ VDS ( I 12)  (2b)
 
         [0071]    Next, a description is given of the operation of the source amplifiers  25  in this embodiment. Hereafter, an exemplary operation of a source amplifier  25  is described for a case that a positive drive voltage is outputted in response to the polarity signal POL being set to “H”, a negative drive voltage is outputted in response to the polarity signal POL being set to “L”. In this case, the input switches SW 11  and SW 12  provide connections between the input node IN 11  and the source of the PMOS transistors MP 13  and between the input node IN 12  and the source of the PMOS transistor MP 14 , when the polarity signal POL is set to “L”, and provide connections between the input node IN 11  and the source of the NMOS transistor MN 13  and between the input node IN 12  and the source of the NMOS transistor MN 14 , when the polarity signal POL is set to “H”. It should be noted that, in such operation, the input voltage VIN 13  is lower than VDD/2 when the polarity signal POL is “L”, and the input voltage VIN 1   13  is higher than VDD/2 when the polarity signal POL is “H”. 
         [0072]    When the polarity signal POL is set to “L”, the input node IN 11  is connected to the source of the PMOS transistor MP 13  by the input switch SW 11 . 
         [0073]    Consequently, a voltage of VIN 13 +|VT(MP 13 )| is applied to the gate of the NMOS transistor MN 11  in the NMOS differential pair. Thus, even when the input voltage VIN 13  is close to the negative power source voltage VSS, the voltage VIN 11  of the input node IN 11  is not reduced below VSS+|VT(MP 13 )|. The lower limit value of the voltage VIN 11  of the input node IN 11  at which the NMOS transistor MN 11  operates is VT(MN 11 )+VDS(I 11 ), whereas the voltage of VT(MN 11 )+VDS(I 11 ) or more is applied to the input node IN 11  as understood from the equation (1a). Thus, the NMOS transistor MN 11  can operate even when the input voltage VIN 13  is close to the negative power source voltage VSS. 
         [0074]    At this time, the other NMOS transistor MN 12  in the NMOS differential pair can also operate. More specifically, the input voltage VIN 14  inputted to the input terminal IN 14  is also close to the negative power source voltage VSS due to the feedback operation, when the input voltage VIN 13  is close to the negative power source voltage VSS. Here, the input node IN 12  is connected to the source of the PMOS transistor MP 14  by the input switch SW 12 . Thus, a voltage of VIN 14 +|VT(MP 14 )| is applied to the gate of the NMOS transistor MN 12  in the NMOS differential pair even when the input voltage VIN 14  is close to the negative power source voltage VSS. As understood from the equation (1b), the voltage of VT(MN 12 )+VDS(I 11 ) or more is also applied to the input node IN 12 . Hence, the NMOS transistor MN 12  can operate, even when the input voltage VIN 13  is close to the negative power source voltage VSS. 
         [0075]    When the polarity signal POL is set to “H”, on the other hand, the input node IN 11  is connected to the source of the NMOS transistor MN 13  by the input switch SW 11 . Thus, a voltage of VIN 13 −VT(MN 13 ) is applied to the gate of the PMOS transistor MP 11  in the PMOS differential pair, even when the input voltage VIN 13  is high. The upper limit value of the voltage VIN 11  at which the PMOS transistor MP 11  operates is VDD−VDS(I 12 )−|VT(MP 11 )|, whereas the voltage of VDD−VDS(I 12 )−|VT(MP 11 )| or less is applied to the input node IN 11  as understood from the equation (2a). Thus, the PMOS transistor MP 11  can operate even when the input voltage VIN 13  is close to the positive power source voltage VDD. At this time, a voltage of VDD−VDS(I 12 )−|VT(MP 12 )| or less is applied to the other PMOS transistor MP 12  in the PMOS differential pair, as is understood from the equation (2b). Thus, the PMOS transistor MP 12  can operate even when the input voltage VIN 13  is close to the positive power source voltage VDD. 
         [0076]      FIG. 6  is a graph showing the relation between the input voltage VIN 13  and the gate voltages VG of the NMOS transistor MN 11  and the PMOS transistor MP 11 . As shown in  FIG. 6 , when the polarity signal POL is set to “L” and the input voltage VIN 13  is close to the negative power source voltage VSS, the gate voltage of the NMOS transistor MN 11  is increased up to VIN 13 +|VGS(MP 13 )|. When the polarity signal POL is “H” and the input voltage VIN 13  is close to the positive power source voltage VDD, on the other hand, the gate voltage of the PMOS transistor MP 11  is decreased down to VIN 13 −VGS(MN 13 ). 
         [0077]    Thus, the gate voltages of the NMOS transistor MN 11  and the PMOS transistor MP 11  are always in a range between the lower limit value (indicated by the lower dotted line) at which the NMOS transistor MN 11  operates and the upper limit value (indicated by the upper dotted line) at which the PMOS transistor MP 11  operates, for the entire voltage range of the input voltage VIN 13  between the negative power source voltage VSS and the positive power source voltage VDD. That is, in this embodiment, both of the NMOS differential pair and the PMOS differential pair can operate irrespectively of the value of the input voltage VIN 13 . This implies that the source amplifier  25  of this embodiment exhibits the improved peak-to-peak voltage variations, for any voltage level of the input voltage VIN 13  in the voltage range between the negative power source voltage VSS and the positive power source voltage VDD. 
         [0078]    One may consider that the configuration of the source amplifier  25  of this embodiment may cause deterioration of the linearity of the drive voltage in a voltage range around the voltage of VDD/2, since the connections of the input switches SW 11  and SW 12  are switched when the input voltage VIN 13  is changed across the common voltage V COM  (≈VDD/2); however, this does not cause any problem in actual operations, because, as mentioned above, the actual input voltage VIN 13  is in the voltage range between VSS+α and VDD/2−α for the polarity signal POL of “L”, and in the voltage range between VDD/2+α and VDD−α for the polarity signal POL of “H”. The voltage in the voltage range of VDD/2±α is never inputted as the input voltage VIN 13 . Thus, the poor linearity in the voltage range around the voltage of VDD/2 does not cause any problem. 
         [0079]    In the following, a further description is given of advantages of the source amplifier  25  of this embodiment with reference to the simulation results shown in  FIGS. 7A ,  7 B. In  FIGS. 7A ,  7 B, the horizontal axis indicates the input voltage VIN 13 , and the vertical axis indicates the input-to-output offset and the amplitude difference, respectively. 
         [0080]    For the input-to-output offset shown in  FIG. 7A , the input-to-output offset of the conventional circuit ( FIG. 1 ) is large in the voltage regions close to the negative power source voltage VSS and the positive power source voltage VDD. On the other hand, the input-to-output offset of the circuit in this embodiment is small in the voltage regions close to the negative power source voltage VSS and the positive power source voltage VDD, as is the case of the middle voltage range. 
         [0081]      FIG. 7B  shows the amplitude difference of the source amplifier, namely, the difference between the desired value Vpp*(=V OUTP *−V OUTN *) of the peak-to-peak voltage Vpp and the calculated peak-to-peak voltage Vpp obtained by a simulation. The conventional circuit shown in  FIG. 1  exhibits an increased amplitude difference in the voltage ranges close to the negative power source voltage VSS and the positive power source voltage VDD, whereas the source amplifier  25  of this embodiment exhibits a reduced amplitude difference in those voltage ranges, as is the case of the middle voltage range. 
         [0082]      FIGS. 8A and 8B  are graphs showing the simulation results of the peak-to-peak voltage variations for the conventional circuit shown in  FIG. 1  and the source amplifier  25  of this embodiment. In  FIGS. 8A and 8B , the horizontal axis indicates the input voltage, and the vertical axis indicates the peak-to-peak voltage variations. The conventional circuit in  FIG. 1  exhibits increased peak-to-peak voltage variations in the voltage ranges close to the negative power source voltage VSS and the positive power source voltage VDD. On the other hand, the source amplifier  25  of this embodiment exhibits reduced peak-to-peak voltage variations in those voltage ranges, similarly to the middle voltage range. As thus discussed, the source amplifier  25  of this embodiment effectively achieves improved peak-to-peak voltage variations. 
         [0083]    In this embodiment, the PMOS source followers  11 ,  13  and the NMOS source followers  12  and  14  in the input level conversion circuits  4  and  5  may stop operating when they are disconnected from the input node IN 11  and IN 12 . Such operations are preferable in terms of the decrease in the power consumption of the source amplifier  25 . Specifically, when the input switches SW 11  and SW 12  connect the input nodes IN 11  and IN 12  to the PMOS source followers  11  and  13 , respectively (for example, when the polarity signal POL is “L”), the operations of the bias current sources I 14  and I 16  of the NMOS source followers  12 ,  14  are stopped. On the other hand, when the input switches SW 11  and SW 12  connect the input nodes IN 11  and IN 12  to the NMOS source followers  12  and  14 , respectively (for example, when the polarity signal POL is “H”), the operations of the bias current sources I 13  and I 15  of the PMOS source followers  11  and  13  are stopped. Such operation can be achieved by on-off controls of the bias current sources I 13  to I 16  in response to the polarity signal POL, for example. 
       Second Embodiment 
       [0084]      FIG. 9A  is a circuit diagram showing an exemplary configuration of a source driver  100 A in a second embodiment of the present invention, and  FIG. 9B  is a circuit diagram showing an exemplary configuration of a source amplifier  25 A in the second embodiment. In the second embodiment, the source driver  100 A and the source amplifier  25 A integrated therein are configured to provide the input level conversion only in the voltage ranges close to the negative power source voltage VSS and the positive power source voltage VDD; the source amplifier  25 A does not provide input level conversion in the middle voltage range. 
         [0085]    Specifically, as shown in  FIG. 9A , the source driver  100 A is provided with a switch control circuit  26 . The switch control circuit  26  generates a switch control signal SW_CTRL for controlling input switches SW 21  and SW 22  in the input stage  1 A in the source amplifier  25 A, in response to the pixel data D IN  latched by the latches  21  and the polarity signal POL. 
         [0086]    The source amplifier  25 A differs from the source amplifier  25  in the first embodiment in that the input switches SW 21  and SW 22  have functions for providing direct connections between the input nodes IN 11  and IN 12  to the input terminals IN 13  and IN 14 , respectively as shown in  FIG. 9B . In detail, the input switch SW 21  connects the input node IN 11  to one of the input terminal IN 13 , the PMOS source follower  11  and the NMOS source follower  12 , in response to the switch control signal SW_CTRL outputted by the switch control circuit  26 . On the other hand, the input switch SW 22  connects the input node IN 12  to one of the input terminal IN 14 , the PMOS source follow  13  and the NMOS source follower  14 , in response to the switch control signal SW_CTRL. Since the switch control signal SW_CTRL is generated in response to the pixel data D IN  and the polarity signal POL as described above, the input switches SW 21  and SW 22  are controlled in response to the pixel data D IN  and the polarity signal POL. 
         [0087]    In the following, a description is given of the operation of the source amplifier  25 A of this embodiment. Hereafter, the operation of the source amplifier  25 A is described which outputs a positive drive voltage when the polarity signal POL is “H” and outputs a negative drive voltage when the polarity signal POL is “L”, similarly to the first embodiment. 
         [0088]    In this embodiment, the states of the input switches SW 21  and SW 22  are switched in response to the input voltage VIN 13  inputted to the input voltage VIN 13 . When the input voltage VIN 13  is a voltage close to the negative power source voltage VSS, (more specifically, when the input voltage VIN 13  is lower than a standard voltage V STD1 ), the input switches SW 21 , and SW 22  connect the input nodes IN 11  and IN 12  to the sources of the PMOS transistors MP 13  and MP 14  in the PMOS source followers  13  and  14 , respectively. Here, the standard voltage V STD1  is a predetermined voltage, which is lower than the voltage VDD/2 and equal to or higher than VT(MN 11 )+VDS(I 11 ). In one embodiment, the standard voltage V STD1  is adjusted as follows: 
         [0000]        V   STD1   =VT ( MN 11)+ VDS ( I 11). 
         [0000]    When the input nodes IN 11  and IN 12  are connected to the sources of the PMOS transistors MP 13  and MP 14 , respectively, a voltage that is higher than the voltage of the input terminal IN 13  (input voltage VIN 13 ) by the threshold voltage VT(MP 13 ) of the PMOS transistor MP 13  is supplied to the input node IN 11 , and a voltage that is higher than the voltage of the input terminal IN 14  (input voltage VIN 14 ) by the threshold voltage VT(MP 14 ) of the PMOS transistor MP 14  is supplied to the input node IN 12 . 
         [0089]    When the input voltage VIN 13  is in the middle voltage range (more specifically, when the input voltage VIN 13  is higher than the standard voltage V STD1  and lower than a predetermined standard voltage V STD2  (&gt;VDD/2)), on the other hand, the input switches SW 21  and SW 22  directly connect the input nodes IN 11  and IN 12  to the input terminals IN 13  and IN 14 , respectively. In this case, the voltage of the input terminal IN 13  (input voltage VIN 13 ) is supplied to the input node IN 11  as it is, and the voltage of the input terminal IN 14  (input voltage VIN 14 ) is supplied to the input node IN 12  as it is. 
         [0090]    Also, when the input voltage VIN 13  is a voltage close to the positive power source voltage VDD, (more specifically, when the input voltage VIN 13  is higher than the standard voltage V STD2 ), the input switches SW 21  and SW 22  connect the input nodes IN 11  and IN 12  to the sources of the NMOS transistors MN 13  an MN 14  in the NMOS source followers  12  and  14 , respectively. 
         [0091]    Here, the standard voltage V STD2  is a predetermined voltage, which is higher than the voltage VDD/2 and equal to or lower than VDD−VDS(I 12 )−|VT(MP 11 )|. In one embodiment, the standard voltage V STD2  is adjusted as follows: 
         [0000]        V   STD1   =VDD−VDS ( I 12)−| VT ( MP 11)|,
 
         [0000]    When the input nodes IN 11  and IN 12  are connected to the sources of the NMOS transistors MN 13  and MN 14 , respectively, a voltage that is lower than the voltage of the input terminal IN 13  (input voltage VIN 13 ) by the threshold voltage VT(MN 13 ) of the NMOS transistor MN 13  is supplied to the input node IN 11 , and a voltage that is lower than the voltage of the input terminal IN 14  (input voltage VIN 14 ) by the threshold voltage VT(MN 14 ) of the PMOS transistor MP 14  is supplied to the input node IN 12 . 
         [0092]    Here, the states of the input switches SW 21  and SW 22  may be determined in response to the polarity signal POL and the pixel data D IN , since the input voltage VIN 13  depends on the value of the pixel data D IN . That is, when the polarity signal POL is “L” and the pixel data D IN  have a value corresponding to the gray-level voltage lower than the standard voltage V STD1 , the input switches SW 21  and SW 22  connect the input nodes IN 11  and IN 12  to the sources of the PMOS transistors MP 13  and MP 14  in the PMOS source followers  11  and  13 , respectively. When the polarity signal POL is “H” and the pixel data D IN  have a value corresponding to the gray-level voltage higher than the standard voltage V STD2 , on the other hand, the input switches SW 21  and SW 22  connect the input nodes IN 11  and IN 12  to the sources of the NMOS transistors MN 13  and MN 14  in the NMOS source followers  12  and  14 , respectively. When any of the above-described conditions is not satisfied, the input switches SW 21  and SW 22  directly connect the input nodes IN 11  and IN 12  to the input terminals IN 13  and IN 14 , respectively. 
         [0093]      FIG. 10  is a graph showing an exemplary relation between the input voltage VIN 13  and the gate voltages VG of the NMOS transistor MN 11  and the PMOS transistor MP 11 . When the input voltage VIN 13  is close to the negative power source voltage VSS (specifically, VIN 13 &lt;V STD1 ), the gate voltages of the NMOS transistor MN 11  and the PMOS transistor MP 11  are increased up to VIN 13 +|VT(MP 13 )|. 
         [0094]    When the input voltage VIN 13  is in the middle voltage range (specifically, V STD1 ≦VIN 13 ≦V STD2 ), the input switch SW 21  directly connects the input node IN 11  to the input terminal IN 13  and the gate voltages of the NMOS transistor MN 11  and the PMOS transistor MP 11  coincide with the VIN 13 . 
         [0095]    Moreover, when the input voltage VIN 13  is close to the positive power source voltage VDD (specifically, VIN  13 &gt;VDD−VDS(I 12 )−|VT(MP 11 )|, the gate voltages of the NMOS transistor MN 11  and the PMOS transistor MP 11  are decreased down to VIN 13 −VT(MN 13 ). 
         [0096]    In any case, the gate voltages of the NMOS transistor MN 11  and the PMOS transistor MP 11  are between the lower limit value (indicated by the lower dotted line) at which the NMOS transistor MN 11  operates and the upper limit value (indicated by the upper dotted line) at which the PMOS transistor MP 11  operates, even when the input voltage VIN 13  has any voltage level between the negative power source voltage VSS and the positive power source voltage VDD. That is, in this embodiment, both of the NMOS differential pair and the PMOS differential pair can operate irrespectively of the value of the input voltage VIN 13 . This implies that the source amplifier  25  of this embodiment exhibits improved peak-to-peak voltage variations, even when the input voltage VIN 13  has any voltage level in the voltage range between the negative power source voltage VSS and the positive power source voltage VDD. 
         [0097]    In addition, the configuration of the source amplifier of this embodiment has an advantage that the influences caused by the property difference between the PMOS transistors MP 13  and MP 14  and the property difference between the NMOS transistors MN 13  and MN 14  can be reduced. In detail, the pair of the PMOS transistors MP 13  and MP 14  and the pair of the NMOS transistors MN 13  and MN 14  also operate as a differential pair. Thus, the differential pairs may cause small input-to-output offsets. In this embodiment, in the middle voltage range, the input terminal IN 13  and the input node IN 11  are directly connected and the input terminal IN 14  and the input node IN 12  are directly connected. This effectively reduces the influences caused by the pair of the PMOS transistors MP 13  and MP 14  and the pair of the NMOS transistors MN 13  and MN 14 . Consequently, the input-to-output offset in the middle voltage range is reduced, and the higher definition of the drive voltage is attained. 
         [0098]    It should be noted that, also in the second embodiment, the operations of the PMOS source followers  11 ,  13  and the NMOS source followers  12  and  14  in input level conversion circuits  4 A and  5 A may be stopped when they are disconnected to the input nodes IN 11  and IN 12 . The above-described operations are preferable in order to decrease the power consumption of the source amplifier  25 A. Specifically, when the input switches SW 21  and SW 22  connect the input nodes IN 11  and IN 12  to the PMOS source followers  11  and  13 , respectively, the operations of the bias current sources I 14  and I 16  of the NMOS source followers  12  and  14  are stopped. On the other hand, when the input switches SW 21  and SW 22  connect the input nodes IN 11  and IN 12  to the NMOS source followers  12  and  14 , respectively, the operations of the bias current sources I 13  and I 15  of the PMOS source followers  11  and  13  are stopped. Also, when the input switches SW 21  and SW 22  directly connect the input nodes IN 11  and IN 12  to the input terminals IN 13  and IN 14 , respectively, all of the operations of the bias current sources I 13  to I 16  are stopped. In any case, the on-off controls of the bias current sources I 13  I 16  may be achieved in response to the polarity signal POL and the pixel data D IN . 
       Third Embodiment 
       [0099]      FIG. 11  is a circuit diagram showing an exemplary configuration of a source amplifier in a source driver of a third embodiment of the present invention. The source amplifier  25 B of the third embodiment is configured similarly to the source amplifier  25  of the first embodiment. The most significant difference is that the NMOS differential pair of the input stage  1 B is composed of depletion type NMOS transistors MN 31  and MN 32 . The threshold voltage of the depletion type transistor is low as compared with the enhancement type transistor. This embodiment is described under an assumption that the threshold voltage of depletion type transistors is adjusted to −0.1 V; the threshold voltage of depletion type transistors may range from −0.2 V to 0 V. 
         [0100]    It should be noted here that the NMOS differential pair formed by the depletion type NMOS transistors MN 31  and MN 32  can operate even when the input voltage is the negative power source voltage VSS. 
         [0101]    In this embodiment, both of the NMOS differential pair and the PMOS differential pair operate, even when the input voltage is close to the negative power source voltage VSS. In this embodiment, the input level conversion is therefore carried out by input level conversion circuits  4 B and  5 B only when the input voltage is close to the positive power source voltage VDD. 
         [0102]    In association with the use of the depletion type NMOS transistors MN 31  and MN 32  as the NMOS differential pair, the input stage  1 B of the source amplifier  25 B of this embodiment is configured as follows: The input level conversion circuit  4 B is provided with an NMOS source follower  12  and an input switch SW 31 , and the input level conversion circuit  5 B is provided with an NMOS source follower  14  and an input switch SW 32 . It should be noted here that, in this embodiment, the input level conversion circuits  4 B and  5 B do not incorporate any PMOS source follower. The input switch SW 31  connects the input node IN 11  to one of the input voltage VIN 13  and the NMOS source follower  12 , in response to the switch switching signal SW_CTRL. Similarly, the input switch SW 32  connects the input node IN 12  to one of the input terminal IN 14  and the NMOS source follower  14 , in response to the switch switching signal SW_CTRL. When the input node IN 11  is connected to the source of the NMOS transistor MN 13  in the NMOS source follower  12 , the input voltage VIN 11  of the input node IN 11  is set to VIN 13 −VT(MN 13 ). Similarly, when the input node IN 12  is connected to the source of the NMOS transistor MN 14  in the NMOS source follower  14 , the input voltage VIN 11  of the input node IN 11  is set to VIN 14 −VT(MN 14 ). 
         [0103]    In the following, a description is given of the operation of the source amplifier  25 B in this embodiment. Also in this embodiment, the states of the input switches SW 31  and SW 32  are switched in response to the input voltage VIN 13  inputted to the input terminal IN 13 . When the input voltage VIN 13  has a voltage level close to the positive power source voltage VDD (more specifically, when the polarity signal POL is “H” and the input voltage VIN 13  is higher than the standard voltage V STD2 ), the input switches SW 31  and SW 32  connect the input nodes IN 11  and IN 12  to the sources of the NMOS transistors MN 13  and MN 14  in the NMOS source followers  12  and  14 , respectively. Here, the standard voltage V STD2  is a predetermined voltage which is higher than the voltage VDD/2 and equal to or less than VDD−VDS(I 12 )−|VT(MP 11 )|. In one embodiment, the standard voltage V STD2  is adjusted as follows: 
         [0000]        V   STD1   =VDD−VDS ( I 12)−| VT ( MP 11)|.
 
         [0000]    When the input nodes IN 11  and IN 12  are connected to the sources of the NMOS transistors MN 13  and MN 14 , respectively, a voltage that is lower than the voltage of the input terminal IN 13  (input voltage VIN 13 ) by the threshold voltage VT(MN 13 ) of the NMOS transistor MN 13  is supplied to the input node IN 11 , and a voltage that is lower than the voltage of the input terminal IN 14  (input voltage VIN 14 ) by the threshold voltage VT(MN 14 ) of the PMOS transistor MP 14  is supplied to the input node IN 12 . 
         [0104]    When the input voltage VIN 13  is in the voltage range close to the negative power source voltage VSS or in the middle voltage range (more specifically, when the input voltage VIN 13  is lower than the predetermined standard voltage V STD2 ), on the other hand, the input switches SW 31  and SW 32  directly connect the input nodes IN 11  and IN 12  to the input terminals IN 13  and  14 , respectively. In this case, the voltage of the input terminal IN 13  (input voltage VIN 13 ) is supplied as it is to the input node IN 11 , and the voltage of the input terminal IN 14  (input voltage VIN 14 ) is supplied as it is to the input node IN 12 . 
         [0105]    Also in the third embodiment, the states of the input switches SW 31  and SW 32  may be determined in response to the polarity signal POL and the pixel data D IN  That is, when the polarity signal POL is “H” and the pixel data D IN  has a value corresponding to the gray-level voltage higher than the standard voltage V STD2 , the input switches SW 31  and SW 32  connect the input nodes IN 11  and IN 12  to the sources of the NMOS transistors MN 13  and MN 14  in the NMOS source followers  12  and  14 , respectively. Otherwise, the input switches SW 31  and SW 32  directly connect the input nodes IN 11  and IN 12  to the input terminals IN 13  and IN 14 , respectively. 
         [0106]      FIG. 12  is a graph showing an exemplary relation between the input voltage VIN 13  and the gate voltages VG of the NMOS transistor MN 31  and the PMOS transistor MP 11 , in the third embodiment. It should be noted here that  FIG. 12  shows the operation for a case that the standard voltage V STD2  is VDD−VDS(I 12 )−|VT(MP 11 )|. 
         [0107]    When the input voltage VIN 13  is close to the positive power source voltage VDD (specifically, VIN 13 &gt;V STD2 ), the input switches SW 31  and SW 32  connect the input nodes IN 11  and IN 12  to the sources of the NMOS transistors MN 13  and MN 14  in the NMOS source followers  12  and  14 , respectively. As a result the gate voltage of the PMOS transistor MP 11  is decreased to VIN 31 −VT(MN 13 ). Since the PMOS transistor MP 11  is an enhancement-type PMOS transistor, therefore the PMOS transistor MP 11  may be hard to operate when the gate voltage is close to the positive power source voltage VDD; however, the gate voltage of the PMOS transistor MP 11  is decreased down to VIN 31 −VT(MN 13 ) in this embodiment and this actually allows the PMOS transistor MP 11  to operate. 
         [0108]    When the input voltage VIN 13  is close to the negative power source voltage VSS or in the middle voltage range (more specifically, VIN 13 ≦V STD2 ), on the other hand, the input voltage VIN 13  is directly applied to the gates of the NMOS transistor MN 31  and the PMOS transistor MP 11 . Since the NMOS transistor MN 31  is a depletion-type NMOS transistor, the NMOS transistor MN 31  can operate, even when the input voltage VIN 13  is close to the negative power source voltage VSS. 
         [0109]    That is, the use of the depletion type NMOS transistors MN 31  and MN 32  in the NMOS differential pair effectively causes the same effects as the first and second embodiments in the third embodiment without using any PMOS source follower. 
         [0110]    When depletion-type NMOS transistors are used as the NMOS transistors MN 31  and MN 32  in the NMOS differential pair, application of a gate voltage close to the positive power source voltage VDD may cause a problem in establishing drain-to-source voltages of the NMOS transistors MN 31  and MN 32 . This is because the source voltage may be higher than the positive power source voltage VDD, since the NMOS transistors MN 31  and MN 32  have a negative threshold voltage. In general, a drain-to-source voltage of an overdrive voltage (Vov) or higher is required in order to stably operate an NMOS transistor. Thus, as for the source voltage VS(MN 31 ) of the NMOS transistor MN 31 , the following equation must be established: 
         [0000]        VS ( MN 31)&lt; VDD−VDS ( MP 43)− Vov ( MN 31),  (3)
 
         [0000]    where VDS(MP 43 ) is the drain-to-source voltage of the PMOS transistor MP 43  that functions as the active load at the intermediate stage  2  (see  FIG. 1 ). When the gate voltage of the NMOS transistor MN 31  is close to the positive power source voltage VDD, the source amplifier  25 B may not stably operate, since the source voltage VS(MN 31 ) of the NMOS transistor MN 31  does not satisfy the condition of equation (3). One may consider that this leads to deteriorations in the input-to-output offset and the peak-to-peak voltage variations. 
         [0111]    In the circuit configuration in  FIG. 11 , however, the increase in the source voltage VS(MN 31 ) of the NMOS transistor MN 31  does not cause a serious problem, because the gate voltage of the NMOS transistor MN 31  is decreased to VIN 13 −VT(MN 13 ). The NMOS transistor MN 31  stably operates even when the input voltage VIN 13  is close to the positive power source voltage VDD. 
         [0112]    It should be noted that the operations of the NMOS source followers  12  and  14  in the input level conversion circuits  4 B and  5 B may be stopped also in the third embodiment, when the NMOS source followers  12  and  14  are disconnected from the input nodes IN 11  and  12 , respectively. Such operations are preferable for decreasing the power consumption of the source amplifier  25 B. More specifically, the operations of the bias current sources I 14  and I 16  of the NMOS source followers  12  and  14  may be stopped when the input switches SW 31  and SW 32  directly connect the input nodes IN 11  and IN 12  to the input terminals IN 13 ,  14 , respectively. Such operations may be attained through on-off controls of the bias current sources I 14  and I 16  in response to the polarity signal POL and the pixel data D IN . 
       Fourth Embodiment 
       [0113]      FIG. 13  is a circuit diagram showing an exemplary configuration of a source amplifier in a source driver of a fourth embodiment of the present invention. The source amplifier  25 C of the fourth embodiment is configured similarly to the source amplifier  25 B in the third embodiment. The difference is that depletion type PMOS transistors MP 31  and MP 32  are used as the PMOS differential pair within the input stage  1 C, in place of the depletion type NMOS transistors MN 31  and MN 32  of the NMOS differential pair. In this case, the input level conversion circuit  4 C is provided with a PMOS source follower  11  and an input switch SW 31 , and the input level conversion circuit  5 C is provided with a PMOS source follower  13  and an input switch SW 32 . 
         [0114]      FIG. 14  is a graph showing an exemplary relation between the input voltage VIN 13  and the gate voltages VG of the NMOS transistor MN 11  and the PMOS transistor MP 31  in the fourth embodiment. 
         [0115]    When the input voltage VIN 13  is close to the negative power source voltage VSS (specifically, VIN 13 &lt;V STD1 ), the input switches SW 31  and SW 32  connect the input nodes IN 11  and IN 12  to the sources of the PMOS transistors MP 13  and MP 14  in the PMOS source followers  11  and  13 , respectively. Here,  FIG. 14  shows the operation for a case that the standard voltage V STD1  is VT(MN 11 )+VDS(I 11 ). As a result, the gate voltage of the NMOS transistor MN 11  is increased up to VIN 31 +|VT(MP 13 )|. Since the NMOS transistor MN 11  is an enhancement-type NMOS transistor, the NMOS transistor MN 11  may be hard to operate when the gate voltage is close to the negative power source voltage VSS; however, the NMOS transistor MN 11  actually operate, since the gate voltage of the NMOS transistor MN 11  is increased up to VIN 31 +|VT(MP 13 )|. 
         [0116]    When the input voltage VIN 13  is close to the positive power source voltage VDD or in the middle voltage range (specifically, VIN 13 ≧V STD1 ), on the other hand, the input voltage VIN 13  is directly applied to the gates of the NMOS transistor MN 11  and the PMOS transistor MP 31 . The PMOS transistor MP 31  is the depletion type transistor and thus the PMOS transistor MP 31  can operate even when the input voltage VIN 13  is close to the positive power source voltage VDD. 
         [0117]    That is, the use of the depletion type PMOS transistors MP 31  and MP 32  as the PMOS differential pair effectively causes the same effects as the first and second embodiments without using any NMOS source follower. 
         [0118]    Also in the fourth embodiment, the states of the input switches SW 31  and SW 32  may be switched in response to the polarity signal POL and the pixel data D IN . Specifically, when the polarity signal POL is “L” and the pixel data D IN  has a value corresponding to the gray-level voltage lower than the standard voltage V STD1 , the input switches SW 31  and SW 32  connect the input nodes IN 11  and IN 12  to the sources of the PMOS transistors MP 13  and MP 14  in the PMOS source followers  11  and  13 , respectively. Otherwise, the input switches SW 31  and SW 32  directly connect the input nodes IN 11  and IN 12  to the input terminals IN 13  and IN 14 , respectively. 
         [0119]    Also in the fourth embodiment, the operations of the PMOS source followers  11  and  13  in the input level conversion circuits  4 C and  5 C may be stopped, when the PMOS source followers  11  and  13  in the input level conversion circuits  4 C and  5 C are disconnected from the input nodes IN 11  and IN 12 , respectively. Such operations are preferable in order to decrease the power consumption of the source amplifier  25 C. Specifically, when the input switches SW 31  and SW 32  directly connect the input nodes IN 11  and IN 12  to the input terminals IN 13  and IN 14 , respectively, the operations of the bias current sources I 13  and I 15  of the PMOS source followers  11  and  13  are stopped. Such operations may be attained through on-off controls of the bias current sources I 13  and I 15  in response to the polarity signal POL and the pixel data D IN . 
         [0120]    It would be apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope of the invention. For example, although the second to fourth embodiments are described to recite that the gray-level voltages supplied to the source amplifiers  25 A to  25 C are judged from the polarity signal POL and the pixel data D IN  in controlling the operations of the input switches SW 21 , SW 22 , SW 31  and SW 32 , the gray-level voltages supplied to the source amplifiers  25 A to  25 C may be directly measured and the operations of the input switches SW 21 , SW 22 , SW 31  and SW 32  are controlled in response to the measured gray-level voltages. It should be noted, however, that the configuration in which the gray-level voltages supplied to the source amplifiers  25 A to  25 C are judged from the polarity signal POL and the pixel data D IN  is preferable in view of the easiness of data processing.