Abstract:
A method for providing an improved solder joint for a via-in-pad ball grid array package. One or more bonding pads are formed upon a substrate. One or more vias are formed through the substrate within the bonding pad. The vias are plugged with a via plug material. The via plug material is then preconditioned such that an amount of volatiles within the via plug material is reduced.

Description:
FIELD  
         [0001]    Embodiments of the invention relates generally to the field of surface mount technology for integrated circuit (IC) packages, and more specifically to an improved via-in-pad (VIP) ball grid array (BGA).  
         BACKGROUND  
         [0002]    Integrated circuits (ICs) are typically assembled into packages that are physically and electrically coupled to a substrate such as a printed circuit board (substrate) to form an “electronic assembly”. The “electronic assembly” can be part of an “electronic system”. An “electronic system” is broadly defined herein as any product comprising an “electronic assembly”. Examples of electronic systems include computers (e.g., desktop, laptop, hand-held, server, etc.), wireless communications devices (e.g., cellular phones, cordless phones, pagers, etc.), computer-related peripherals (e.g., printers, scanners, monitors, etc.), entertainment devices (e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders, etc.), and the like.  
           [0003]    In the field of IC package mounting there is a constant pressure to increase component density and performance while decreasing production costs. Each new generation of board-level packaging must provide increased performance while generally being smaller or more compact in size.  
           [0004]    A substrate typically includes a number of insulation and metal layers selectively patterned to provide metal interconnect lines (referred to herein as “traces”), and a plurality of electronic components mounted on one or more surfaces of the substrate and functionally interconnected through the traces. The routing traces typically carry signals that are transmitted between the electronic components, such as ICs, of the system. Some ICs have a relatively large number of input/output (I/O) pads. The large number of I/O pads requires a relatively large number of routing traces. Some substrates require multiple layers of routing traces to accommodate all of the system interconnections. Routing traces located within different layers are typically connected electrically by vias formed in the board. A via can be made by making a hole through some or all layers of a substrate and then coating or plating the interior hole surface with an electrically conductive material, such as copper.  
           [0005]    BGA is a surface mount technology that typically uses a plurality of conductive interconnects, which may be ball shaped and formed from solder or conductive polymers, on one surface of the component, as electrical and physical connections to the substrate. Each conductive ball connects to a conductor within the component and is coupled to corresponding metallized mounting or bonding pads (pads) on the surface of the substrate.  
           [0006]    [0006]FIGS. 1A, 1B, and  1 C illustrate conventional layouts for vias and pads in accordance with the prior art. A typical configuration on the substrate is the interstitial via or “dogbone” layout shown in FIG. 1A. System  100 A illustrates the key feature of the dogbone layout, which is the separation of the vias, represented by via  110 A from the pads represented by pad  114 A. The vias are electrically coupled to the pads through traces represented by trace  112 A. This physical separation, of the via from the pad, helps to prevent the conductive ball from wicking down the via during the soldering process. However, the dogbone layout provides limited open channel space (space between vias) for circuit connections. This limits the density of the connections.  
           [0007]    [0007]FIG. 1B illustrates a variation known as a via-behind-pad (VPB) layout. System  100 B, includes vias (e.g.,  110 B) coupled to pads (e.g.,  114 B) by traces (e.g.,  112 B). The distance between the vias and the pads (and hence the length of the traces) is less than the dogbone layout. This is achieved through improved solder mask registration technology. To further increase connection densities, a via-in-pad (VIP) layout is employed. FIG. 1C illustrates the VIP layout. In system  300 , the vias (e.g.,  110 C) are implemented within the pads (e.g.,  114 C), thus conserving valuable “real estate” on the substrate that would otherwise be separately occupied by the via and the pad.  
           [0008]    Though the higher connection density achieved with a VIP layout results in decreased package size and cost, it is not without drawbacks. The typical production process for a VIP-BGA substrate involves partially filling the via with solder mask material to prevent solder from draining down into the via and out the other side of the substrate. During assembly when the conductive balls of the IC/Package are reflowed (heated) to form the connections, volatile organic compounds (volatiles) within the solder mask may expand or “outgas” upwards into the overlying conductive balls. This may cause the conductive balls to expand creating short circuits with other conductive balls, or may cause voids where the conductive balls are supposed to make contact with the vias, creating open circuits, or may otherwise degrade or destroy the conductive ball, which adversely impacts reliability. This problem has been identified and addressed in the prior art, though not entirely satisfactorily, by significantly reducing the diameter of the via. Thus, less solder mask to plug the via and therefore less volatiles. This method results in reduced expansion of the conductive balls and reduced voids within the conductive balls, but has additional manufacturing and tooling costs.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    Embodiments of the invention may be best understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention. In the drawings:  
         [0010]    [0010]FIGS. 1A, 1B, and  1 C illustrate conventional layouts for vias and pads in accordance with the prior art;  
         [0011]    [0011]FIG. 2 is a portion of the process flow diagram of a process in which a VIP-BGA is produced in accordance with one embodiment of the invention;  
         [0012]    [0012]FIGS. 3A and 3B illustrate, respectively, a substrate via prior to plugging, and subsequent to plugging, in accordance with one embodiment of the invention;  
         [0013]    [0013]FIG. 4 illustrates the substrate  300  of FIG. 3B having a developed SM layout in accordance with one embodiment of the invention;  
         [0014]    [0014]FIG. 4A illustrates the substrate  300  of FIG. 3B having a developed SM layout in accordance with an alternative embodiment of the invention;  
         [0015]    [0015]FIG. 5 illustrates the substrate  300  of FIG. 4 after undergoing a process to precondition the VPM in accordance with one embodiment of the invention; and  
         [0016]    [0016]FIG. 5A illustrates the substrate  300  of FIG. 4A after undergoing a process to precondition the VPM in accordance with one embodiment of the invention.  
     
    
     DETAILED DESCRIPTION  
       [0017]    An embodiment of the invention provides a method for producing a VIP-BGA having preconditioned via plug material (VPM). During the preconditioning process, a substantial portion of the plug material volatiles is driven off. For one embodiment, the preconditioning is accomplished during a standard high-temperature manufacturing process. For such an embodiment, in which the via plug material is a solder mask material, the preconditioning is accomplished during the hot air solder leveling (HASL) process presently used in VIP-BGA manufacturing. Such an embodiment eliminates the need for a via-capping process.  
         [0018]    In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.  
         [0019]    Reference throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearance of the phrases “in one embodiment” or “in an embodiment” in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.  
         [0020]    [0020]FIG. 2 is a portion of a process flow diagram of a process in which a VIP-BGA is produced in accordance with one embodiment of the invention. Process  200  begins with operation  205  in which a via of a substrate (e.g., PCB) is plugged with VPM. For one embodiment this is accomplished subsequent to a typical strip-etch-strip process. FIGS. 3A and 3B illustrate a substrate via prior to plugging, and subsequent to plugging, respectively. As shown in FIG. 3A, substrate  300  is a multilayer structure having a via  310  therethrough. In alternative embodiments, the substrate  300  may be a single layer structure. Via  310  is typically comprised of a conductive metal (e.g., copper) tube to enable interconnection between the conductive layers  312 ,  314 ,  316 , and  318 . The conductive layers are typically comprised of a sheet material (e.g., glass fabric) impregnated with a curable resin. At this point in the manufacturing process, the via  310  has nothing in it. FIG. 3B illustrates the substrate of FIG. 3A wherein the via  310  is plugged with VPM. For one embodiment the VPM is a liquid photo-imageable solder mask (SM) material. As shown in FIG. 3B, for such an embodiment, the via may be completely filled with the SM material  326  which may also provide a SM coating  324  for the primary surface  321  and the secondary surface  322  of the substrate  300 . In various alternative embodiments, the VPM may be a material other than SM and the via may not be completely filled with VPM.  
         [0021]    Referring again to FIG. 2, at operation  210  the VPM is retained within the via through the SM developing process. This is in contrast to the typical prior art process in which the solder masking is accomplished without plugging the via. In the SM developing process, the desired SM layout (that portion of SM to be retained on the substrate) is polymerized through exposure to ultraviolet (UV) light. The substrate is selectively exposed to UV light using a photo tool that blocks UV light in some desired areas, but allows the UV light to pass in others. After exposure to the UV light, the substrate is put through a chemical wash that removes the solder mask in those areas that were not exposed to the UV light. This results in the desired layout of the solder mask. FIG. 4 illustrates the substrate  300  of FIG. 3B having a developed SM layout. As shown in FIG. 4, the exposed portion of SM  324 , including the SM covering the via is retained and the VPM  326  is retained within the via. However, the unexposed SM covering the pad  330  has now been removed. Had the solder mask covering the via not been retained, the VPM would have been removed during the chemical wash process. For one embodiment a photo tool that is approximately 0-3 mils larger than the circumference of the vias is used. This leaves solder mask unexposed over the pad area, but exposed over the via as desired.  
         [0022]    [0022]FIG. 4A illustrates an embodiment of the invention in which the via is not completely filled with VPM.  
         [0023]    Referring again to FIG. 2, at operation  215  the VPM is preconditioned to remove volatiles or other problematic components such as gases or moisture. This is accomplished, for one embodiment, by subjecting the VPM to a high-temperature process, the temperature of which is sufficient to drive the volatiles and gases from the VPM. For an embodiment in which the VPM is SM material, the temperature may be approximately 183 C, which is the temperature of the solder reflow process. For such an embodiment, the high-temperature process used for preconditioning the VPM may be a standard hot-air-solder-leveling (HASL) manufacturing process. After the SM developing process, the areas of the substrate not covered by SM are coated with solder. It is desirable that the solder be evenly applied and the amount of solder applied be controlled. This may be accomplished through a HASL process. Typically the solder may be introduced by submerging the substrate in a pot of molten solder or a solder wave. Then hot air is applied at high velocity in the HASL process. The hot air keeps the solder molten (or melts the solder) and the velocity of the air forces excess solder from the board. It is during this high temperature process that the VPM is preconditioned for one embodiment of the invention. The high temperature air of the HASL process causes the solder mask within the via to outgas (de-aerate or other gaseous emission). This results in the substantial reduction or absence of volatiles or other unevaporated thermally expansive material within the via. Because the VPM has been retained in the via, there is no need for a separate via capping process required in the typical prior art VIP-BGA production methods.  
         [0024]    After the VPM has been preconditioned, the process of creating a VIP-BGA package continues in a conventional manner. A solder paste is screened over the substrate to coat the pads. Components (e.g., ICs) having conductive balls are then placed on the pads. FIG. 5 illustrates the substrate  300  of FIG. 4 after undergoing a process to precondition the VPM. In FIG. 5, the conductive ball  332 , attached to the component (not shown) is placed upon the pad  330 . The conductive ball  332  is placed over the via that contains VPM  326 . The components are subsequently electrically connected to the substrate by reflowing the solder. The VPM, having had a substantial portion or all of the volatiles driven therefrom, exhibits substantially reduced outgassing during solder reflow.  
         [0025]    [0025]FIG. 5A illustrates an embodiment of the invention in which the via is not completely filled with VPM. As shown in FIG. 5A, the conductive ball  332  partially fills the via  310 . In an alternative embodiment, the conductive ball  332  may fill the entire portion of the via  310  left unfilled by the VPM  326 .  
         [0026]    General Matters  
         [0027]    Embodiments of the invention have been described in which preconditioning of the VPM is accomplished by plugging the via with SM material during a typical SM process, retaining the SM within the via throughout SM developing, and subjecting the SM filling of the via to a typical HASL process. This is in contrast to the prior art in which the via is plugged with SM after the HASL process has been accomplished as discussed above in reference to FIG. 2. Such an embodiment of the invention offers advantages over the prior art in that the HASL process drives volatiles and other problematic components from the VPM prior to the solder reflow process. An additional benefit of such an embodiment is the elimination of the via capping step necessary in the prior art manufacturing process as discussed above in reference to FIG. 2.  
         [0028]    For one embodiment of the invention the via is filled or substantially filled with VPM. This reduces corrosion which may occur due to etching solution entering the via during the surface finish process. A substantially filled via also reduces the area in which air may be trapped within the via. Such an air pocket could expand during reflow and degrade the conductive ball.  
         [0029]    In various alternative embodiments the VPM need not be SM material, but may be a variety of other suitable materials. For example, the VPM may be a conductive material comprising an SM material embedded with metal (e.g., silver) shavings.  
         [0030]    In various alternative embodiments, the high temperature process used to cause outgassing of the VPM need not be the standard HASL process, but may be an alternative or an additional process. In still another alternative embodiment the preconditioning may not be accomplished using a high temperature process, but may be alternatively be accomplished by subjecting the VPM to low pressure to cause outgassing. For still another alternative embodiment, a combination of high temperature and low pressure may be used to effect outgassing.  
         [0031]    While the invention has been described in terms of several embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims, The description is thus to be regarded as illustrative instead of limiting.