Abstract:
In an application system of a liquid crystal display, for protecting transmissions between a master terminal and a slave terminal, effects caused by an unstable power source of the slave terminal have to be reduced to a lowest degree. When the application system is reset or under normal operations with the power source having a suddenly-decreased or suddenly-unstable voltage level, the transmission between the master terminal and the slave terminal have to be terminated, and related data of the terminated transmission is temporarily stored. When the voltage of the slave terminal is confirmed to reach to a stable voltage over a predetermined duration, the transmission may be restored by the stored data.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a method and a system for protecting information, and more particularly, to a method and a system having a master terminal and a slave terminal for protecting information between the master terminal and the slave terminal. 
         [0003]    2. Description of the Prior Art 
         [0004]    In an application system of a conventional liquid crystal display, an electrically erasable programmable read-only memory (EEPROM) is further added to a master terminal as a slave terminal for storing related information of the application system. The stored related information includes data, such as a clock parameter, a brightness, a contrast, a specification of images, or an operating procedure, of the liquid crystal display. In considerations of cost for display system, the added EEPROM may also be implemented with a serial electrically erasable programmable read-only memory (Serial EEPROM). 
         [0005]    Please refer to  FIG. 1 , which is a diagram of an application system  100  applied on a liquid crystal display in the prior art. As shown in  FIG. 1 , the application system  100  includes a master terminal  102 , a slave terminal  104 , and two resistors  106  and  108 , where both the resistors  106  and  108  may indicate equivalent resistances of the slave terminal  104 . The application system  100  is utilized for supporting the liquid crystal display  100 , and is biased with a power source VDD. In other words, both the master terminal  102  and the slave terminal  104  are biased with the power source VDD. Both pins SDA and SCL shown in  FIG. 1  are utilized for exchanging related data, such as clocks, between the master terminal  102  and the slave terminal  104 . Moreover, a two-wire transmission interface may also be utilized for exchanging information between the master terminal  102  and the slave terminal  104 . For storing data related to the application system  100  in a real-time manner, the EEPROM for implementing the slave terminal  104  may be set to a writable mode, and disables its write protection. However, when the voltage level of the power source VDD is unstable or overly low, signals transmitted between the master terminal  102  and the slave terminal are unstable as well so that the slave terminal  104  erroneously reads or stores data. In other words, transmitted information between the master terminal  102  and the slave terminal are damaged by the unstable power source VDD, and therefore, the application  100  may erroneously operate the liquid crystal display  110 . The unstable or overly low power source VDD may be resulting from rapid and repeated resets of the application system  100  or insufficient power of the power source VDD. 
       SUMMARY OF THE INVENTION 
       [0006]    The claimed invention discloses an information protecting method applied on a master terminal and a slave terminal in a system. The disclosed method comprises (a) 
         [0007]    detecting if a voltage level of a power of the slave terminal is lower than a voltage level of a reference voltage; and (b) if the voltage level of the power of the slave terminal is lower than the reference voltage, storing a data related to a transmission between the master terminal and the slave terminal, and terminating the transmission. 
         [0008]    The claimed invention discloses a system for protecting information between a master terminal and a slave terminal. The system comprises a slave terminal, a master terminal, and a detecting device. The slave terminal has a power terminal coupled to a power. The master terminal is utilized for accessing information of the slave terminal. The detecting device is utilized for detecting the voltage level at the power terminal of the slave terminal, and for performing a detecting/protecting mechanism. The master terminal terminates or restores transmission between the master terminal and the slave terminal according to results of the detecting/protecting mechanism. 
         [0009]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]      FIG. 1  is a diagram of an application system applied on a liquid crystal display in the prior art. 
           [0011]      FIG. 2  is a diagram of an application system for protecting the transmission between the master terminal and the slave terminal according to a preferred embodiment of the present invention. 
           [0012]      FIG. 3  is a flowchart of the method for protecting the transmission between the master terminal and the slave terminal, where the method is applied on the application system shown in  FIG. 2 . 
           [0013]      FIG. 4  is a diagram for illustrating the transmission between the master terminal and the slave terminal when the voltage level at the power terminal of the slave terminal drops suddenly. 
           [0014]      FIG. 5  is a state diagram for illustrating pulses of the data line and the clock line according to the detecting/protecting mechanism of the present invention while a two-wired transmission interface is applied on the transmission interface between the master terminal and the slave terminal shown in  FIG. 2  and when the voltage level of the power source is unstable. 
           [0015]      FIG. 6  illustrates the form of related data while the master terminal holds the state STATE_ 19  in  FIG. 5  according to the detecting/protecting mechanism of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    For preventing information transmitted between the master terminal and the slave terminal from being damaged by an unstable or overly low power source in the application system, a method and a system for protecting information transmitted between the master terminal and the slave terminal are disclosed in the present invention. According to embodiments of the present invention, a detecting/protecting mechanism, in which if transmission between the master terminal and the slave terminal is terminated or restored is determined according to a status of the power source of the slave terminal, is implemented so that the transmission between the master terminal and the slave terminal is prevented from being damaged by the unstable or overly low power source of the slave terminal. 
         [0017]    Please refer to  FIG. 2  and  FIG. 3 .  FIG. 2  is a diagram of an application system  200  for protecting the transmission between the master terminal  202  and the slave terminal  204  according to a preferred embodiment of the present invention.  FIG. 3  is a flowchart of the method for protecting the transmission between the master terminal  202  and the slave terminal  204 , where the method is applied on the application system  200  shown in  FIG. 2 . 
         [0018]    As shown in  FIG. 2 , the application system  200  includes a master terminal  202 , a slave terminal  204 , and a detecting device  206 , and is coupled to a liquid crystal display  210  for supporting the liquid crystal display  210 . The transmission between the master terminal  202  and the slave terminal  204  in the present invention is implemented in a similar manner with the transmission between the master terminal  102  and the slave terminal  104  in the prior art, where the implementation is based on a two-wire transmission interface also, and thus is not described further. The master terminal  202  may access information of the slave terminal  204 . Information transmitted between the master terminal  102  and the slave terminal  204  includes a shared clock and an operating procedure of both the master terminal  202  and the slave terminal  204 , and parameters including a brightness, a contrast, and an image specification for supporting the liquid crystal display  210 . The detecting device  206  includes a processor  208 , a timer  212 , a comparator  214 , and a storage device  216 . The detecting device  206  is utilized for detecting the voltage level of the power source VDD coupled to the slave terminal  204  with its elements, and for performing a detecting/protecting mechanism. The master terminal  202  terminates or restores the transmission between the master terminal  202  and the slave terminal  204  according to a result of the detecting/protecting mechanism. The comparator  214  is utilized for comparing voltage levels of the power source VDD and a reference voltage Vref, and for outputting a comparison result signal for indicating which one among the compared voltage levels is higher. The processor  208  is utilized for performing the detecting/protecting mechanism of the detecting device  206  according to the comparison result signal from the comparator  214 , and for providing the result of the detecting/protecting mechanism. The timer  212  is utilized for providing its hour-counting function for the processor  208  when the detecting/protecting mechanism is performed by the detecting device  206 . The storage device  216  is utilized for storing related data transmitted between the master terminal  202  and the slave terminal  204  through the processor  208  when the detecting/protecting mechanism is performed by the detecting device  206 . In a preferred embodiment of the present invention, the storage device  216  is implemented with a random access memory (RAM) for storing necessary data in a real-time and dynamic manner when the transmission between the master terminal  202  and the slave terminal  204  is terminated. The slave terminal  204  is further connected with a power-storing element  218  in parallel so that the voltage level of the power source VDD coupled to a power terminal of the slave terminal  204  is decreased smoothly. In a preferred embodiment of the present invention, the power-storing element  218  is implemented with a capacitor. 
         [0019]    The method disclosed in  FIG. 3  with respect to the detecting/protecting mechanism includes steps as follows: 
         [0020]    Step  302 : Detect if the voltage level of a power of the slave terminal  204  (hereinafter, the voltage level is referred to the voltage Vc is lower than a reference voltage Vref. When the voltage Vc at the power terminal of the slave terminal  204  is lower than the reference voltage Vref, go to Step  304 . Otherwise, repeat Step  302 . 
         [0021]    Step  304 : If the voltage Vc at the power terminal of the slave terminal  204  is lower than the reference voltage Vref, store a data related to a transmission between the master terminal  202  and the slave terminal  204 , and terminate the transmission. 
         [0022]    Step  306 : Detect if the voltage Vc at the power terminal of the slave terminal  204  is stable for a predetermined time. If the voltage Vc at the power terminal of the slave terminal  204  is stable for the predetermined time, go to Step  310 . Otherwise, repeat Step  306 . 
         [0023]    Step  310 : Restore the transmission between the master terminal  202  and the slave terminal  204  according to the data stored in Step  304 . 
         [0024]    In Step  302 , when the detecting device  206  is normally operated, or when the application system  200  is just reset, the voltage Vc at the power terminal of the slave terminal  204  is repeatedly compared with the reference voltage Vref by the comparator  214  for detecting the voltage Vc at the power terminal of the slave terminal  204  is lower than the reference voltage Vref. 
         [0025]    When the voltage Vc at the power terminal of the slave terminal  204  is lower than the reference voltage Vref, in Step  304 , the processor  208  orders the storage device  216  to store data related to a transmission between the master terminal  202  and the slave terminal  204 , and orders the master terminal  202  to terminate the transmission with the slave terminal  204  for preventing transmitted information from being damaged by the unstable or overly low power source VDD. 
         [0026]    In Step  306 , the processor  208  detects if the voltage Vc at the power terminal of the slave terminal  204  is higher than the reference voltage Vref with the aid of the comparator  214 , and detects if the voltage Vc at the power terminal of the slave terminal  204  is higher than the voltage Vc of the reference voltage Vref for a predetermined time with the aid of the timer  212 , where the related operations are indicated in Step  306 . Under the condition that the voltage Vc at the power terminal of the slave terminal  204  is stable, the voltage Vc is not higher than the reference voltage Vref, or the voltage Vc is higher than the reference voltage Vref without exceeding the predetermined time, it is not proper to continue the transmission. It may also indicate that the power source VDD is not stable. Therefore, Step  306  has to be performed again under such circumstances. 
         [0027]    In Step  310 , when the voltage Vc at the power terminal of the slave terminal  204  is higher than the reference voltage Vref and is stable for the predetermined time, it is proper to restore the transmission under the current voltage level Vc. The processor  208  then orders the master terminal  202  to restore the transmission according to data stored in the storage device  216  corresponding to Step  204 . Note that a start of the restored transmission should not be limitations to the present invention. 
         [0028]    In this case, when the processor  208  detects the voltage Vc at the power terminal of the slave terminal  204  is lower than a minimum operation voltage Vmin and then is higher than the reference voltage Vref, and then the voltage Vc at the power terminal of the slave terminal  204  is stable for the predetermined time, the processor  208  allows the transmission, but the transmission is not sure to be restored. 
         [0029]    Note that in a preferred embodiment of the present invention, a length of the predetermined time is 20 milliseconds, the reference voltage is 3.3 volts, the voltage Vc corresponding to a stable state of the power source VDD is 5 volts, a voltage level Vmax indicating an upper bound of the voltage level Vc is 5.5 volts, and a voltage level Vmin indicating a lower bound of the voltage level Vc is 1.8 volts. 
         [0030]    For ensuring capturing transmitted data right before the transmission is terminated, where the transmitted data is important for initiating a next transmission between the master terminal  202  and the slave terminal  204 , certain adaptation is added in Step  304 . In the added adaptation of Step  304 , the storage device  216  further stores end information in a last transmission between the master terminal  202  and the slave terminal  204 , and then the processor  208  orders the master terminal  202  to terminate the transmission. 
         [0031]    For ensuring soundness of transmitted data right before the transmission is terminated when said transmission is restored and initiated again, an other adaptation is added in Step  310 . In the added adaptation of Step  310 , the transmission is restored from the transmission right before the termination, according to stored data of the terminated transmission. 
         [0032]    When the abovementioned adaptations are added and adopted in Step  304  and Step  310 , differences of moments in storing related data corresponding to transmission terminated internal or external to one transmission merely result in tiny differences in safety of protecting transmitted data and in saving wasted transmitted time. However, since the stored data of the storage device  216  are utilized for restoring the terminated transmission, the aim of protecting the transmission is achieved. 
         [0033]    Please refer to  FIG. 4 , which is a diagram for illustrating the transmission between the master terminal and the slave terminal when the voltage at the power terminal of the slave terminal drops suddenly, and please refer to  FIG. 2  together. For the slave terminal  204 , a maximal operating voltage is Vmax, a minimum operating voltage is Vmin, and the reference voltage Vref ranges between the maximum operation voltage Vmax and the minimum operation voltage Vmin. Since the slave terminal  204  is connected with the power-storing element  218  in parallel at the power terminal of the slave terminal  204  and the ground, the voltage level at the power terminal equals a storage voltage level of the power-storing element  218 , where said voltage at the power terminal is Vc. 
         [0034]    When the voltage Vc suddenly drops, the voltage Vc is buffered with the aid of the power-storing element  218 . Therefore, the voltage Vc at the slave terminal  204  drops smoothly. That is, after the detecting device  206  confirms that the voltage Vc is lower than the reference voltage Vref, and within the time T active  that indicates a duration before the voltage Vc at the slave terminal  204  drops below the minimum operating voltage Vmin, related data in the transmission and end information in one transmission are stored. After the end information is stored, the transmission is terminated immediately. The stored data in transmission includes addresses, read/write states, input/output data between the master terminal  202  and the slave terminal  204 , an end information, and includes internal states of the master terminal  202 . 
         [0035]    In  FIG. 4 , the voltage Vc drops under the minimum operation voltage Vmin, and then the voltage Vc rises over the reference voltage Vref, and then the voltage Vc keeps a stable state for a time. The detecting device  206  restores the transmission according to the performed detecting/protecting mechanism of the present invention. As shown in  FIG. 4 , the beginning of restoring the transmission is located at the leftmost start symbol of the time T active . 
         [0036]    Please refer to  FIG. 5 , which is a state diagram for illustrating pulses of the data line and the clock line according to the detecting/protecting mechanism of the present invention while a two-wired transmission interface (such as I2C bus) is applied on the transmission interface between the master terminal  202  and the slave terminal  204  shown in  FIG. 2  and when the voltage level of the power source is unstable. When the master terminal  202  holds a state STATE_ 19  so that the master terminal  202  writes a datum DATA_F 7  at an address ADDR_ 44  on the slave terminal  204 , which may be implemented with EEPROM, the voltage level at the power terminal is decreased suddenly.  FIG. 6  illustrates the form of related data while the master terminal  202  holds the state STATE_ 19  in  FIG. 5  according to the detecting/protecting mechanism of the present invention. As shown in  FIG. 6 , the related data is stored in form of stack into the storage device  216 , which may be implemented with random access memory. After the related data is stored, the transmission between the master terminal  202  and the slave terminal  204  is terminated immediately so that the pulses of both the data line and the clock line stay fixed at this time. According to the detecting/protecting mechanism of the present invention, when the voltage level at the power terminal is stable, the master terminal  202  enters a waiting state, which is denoted as STATE_HOLD in  FIG. 5 . When the transmission is ready to be restored, the master terminal  202  reenters the state STATE_ 19 , and rewrites the data DATA_F 7  at the address ADDR_ 44  on the slave terminal  204  according to the data stored in the storage device  216  and shown in  FIG. 6 . 
         [0037]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.