Abstract:
A power-down mode is activated when equal voltages are detected on a pair of differential inputs. The voltage difference across the differential inputs is applied to a multiplier, which generates a squared difference. The squared difference is smoothed and filtered by a low-pass filter to produce an average signal. The average signal is compared to a reference voltage, either explicitly or implicitly, to detect when the voltage difference across the differential inputs is too small. A power-down signal is activated when the average signal is too small. The multiplier can be implemented with a Gilbert cell, while a filter-comparator converts the differential Gilbert-cell output to a single-ended signal and filters the signal. The reference voltage compared can be set by the switching threshold of the filter comparator or other logic gates. A complementary Gilbert cell and filter-comparator can be used to increase the operating range.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to electronic systems, and more particularly to powering down when equal voltages are detected on differential inputs. 
     Many electronic systems use differential signaling to improve speed and noise immunity. A pair of differential signals has one signal line driven high when the other signal line is driven low to transmit a bit of data. The difference in voltage between the two signal lines in the differential pair, rather than the absolute voltages, determines the data state. 
     Failures can occur, such as when a cable carrying a differential pair breaks or is accidentally disconnected. Fail-safe circuits are sometimes added to differential inputs to detect when such a cable break occurs. Often a load resistor at the receiver side of a cable connects the two signal lines in the differential pair. When the cable is disconnected, the load resistor equalizes the voltages on the two signal lines until both signal-line inputs to the differential receiver have the same voltage. This same-voltage condition is detected by the differential receiver, and the output of the differential receiver is forced to a known state, rather than left in an unstable or undefined state. 
     Rather than simply force the differential receiver output to a known state, detection of equal voltages on the differential input signal lines can be used to power-down a circuit or sub-system. See for example, “Power Down Mode Signaled by Differential Transmitter&#39;s High-Z State Detected by Receiver Sensing Same Voltage on Differential Lines”, U.S. Ser. No. 10/064,074, filed Jun. 7, 2002, and assigned to Pericom Semiconductor Corp. of San Jose, Calif. 
     While such an equal-voltage detector for power-down control is useful, a more advanced detector is desired for detecting the equal-voltage condition on a pair of differential lines. An advanced equal-voltage detector and power-down circuit is desired. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     FIG. 1 is a block diagram of an equal-voltage detector for a differential input. 
     FIG. 2 is a schematic of a first part of a differential equal-voltage detector. 
     FIG. 3 is a schematic of a complementary part of a differential equal-voltage detector. 
     FIG. 4 is a waveform of operation of the equal-voltage power-down detector of FIGS.  2 - 3 . 
    
    
     DETAILED DESCRIPTION 
     The present invention relates to an improvement in differential detectors. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed. 
     FIG. 1 is a block diagram of an equal-voltage detector for a differential input. The voltages on a pair of differential inputs are normally different, except for a brief moment at cross-over during switching. When the voltages are equal, a failure is usually the cause, such as when a cable carrying the differential pair is disconnected or broken. 
     Differential inputs VIN+, VIN− are normally driven to opposite states by a differential transmitter (not shown). A load resistor (not shown) between VIN+ and VIN− equalizes the two voltages when the transmitter no longer drives the differential inputs, such as when the transmitter is disconnected due to a cable break. 
     Differential inputs VIN+, VIN− are input to differential multiplier  10 , in both the normal and reverse connections (VIN+, VIN−, and VIN−, VIN+). The voltage difference (VIN+−VIN−) is multiplied by the reverse voltage difference (VIN−−VIN+) by differential multiplier  10 . When the amplitude of the voltage difference is A, the output of differential multiplier  10  is A 2 . For a sine-wave input, the averaged output of differential multiplier  10  is A 2 /2. 
     The output of differential multiplier  10 , voltage V 1 , is filtered by low-pass filter  14  to produce a smoothed or averaged voltage V 2 . This averaged voltage V 2  can be the average over several cycles of the differential input at the target switching frequency. 
     The averaged voltage V 2  is applied to the non-inverting (+) input of differential comparator  16 . The inverting input (−) of differential comparator  16  receives a reference voltage VREF. When V 2  is above VREF, differential comparator  16  outputs a high to inverter  18 , which drives power-down signal PD low (inactive). 
     When V 2  is below VREF, differential comparator  16  outputs a low to inverter  18 , which drives power-down signal PD high (active). Since V 2  is proportional to the square of the absolute voltage difference between differential inputs VIN+, VIN−, V 2  is a measure of the differential signal strength. When a failure occurs and VIN+, VIN−equalize, V 2  drops to zero. Reference voltage VREF can be set to a predetermined value that is below V 2  during normal operation, but above V 2  when differential inputs VIN+, VIN− are equalized. The exact value of VREF used can be estimated or determined by circuit simulation, and a range of values may be substituted. Sensitivity of the power-down detector can be increased by lowering VREF, while false triggering can be reduced by increasing VREF. 
     FIG. 2 is a schematic of a first part of a differential equal-voltage detector. Differential inputs VIN+, VIN− are applied to first differential multiplier  60 , which is a Gilbert multiplier. N-channel tail transistor  62  receives a bias voltage BIASN on its gate, and sinks a constant current that is combined from the four legs of n-channel multiplier transistors  72 ,  74 ,  76 ,  78 . P-channel current source transistors  68 ,  70  each have their gates and drains connected together. The gate and drain of p-channel source transistor  68  is node VQ 1 , while gate and drain of p-channel source transistor  70  is node VQ 2 . Nodes VQ 1 , VQ 2  are the outputs of first differential multiplier  60 . 
     Differential-to-single-ended conversion is performed by first filter comparator  80 . The filtering and comparing functions are combined. Filtering is provided by drain resistance of transistors  88 ,  84  of first filter comparator  80  and the gate capacitances of transistors  92 ,  94  of inverter  90 . Rather than explicitly compare the outputs of first differential multiplier  60  to a reference voltage VREF, the reference voltage is implicitly determined by the switching voltage of first filter comparator  80  and inverter  90 . 
     The VQ 1  output of first differential multiplier  60  is applied to the gate of p-channel transistor  88 , while the VQ 2  output of first differential multiplier  60  is applied to the gate of p-channel transistor  86 . Mirrored current is provided to the drains of transistors  86 ,  88  by n-channel mirror transistors  82 ,  84 , respectively, which have their gates connected together and to the drain of n-channel mirror transistor  82 . The drains of n-channel mirror transistor  84  and p-channel transistor  88  are the V 3  output of first filter comparator  60 . When voltage V 3  is above the switching threshold of transistors  92 ,  94  of inverter  90 , then power-down output PD is driven low (inactive). When voltage V 3  is below the switching threshold of transistors  92 ,  94  of inverter  90 , then power-down output PD is driven high (active). 
     Operation—FIG. 2 
     During normal operation when VIN+ is higher than VIN−, multiplier transistors  74 ,  76 , which receive VIN+ at their gates, have a higher transconductance than multiplier transistors  72 ,  78 , which receive VIN− at their gates. Multiplier transistors  72 ,  78  tend to turn off when VIN− goes low. 
     Thus changes in current through n-channel differential transistor  64  are coupled to p-channel current-source transistor  70  through multiplier transistor  74 , while changes to current through n-channel differential transistor  66  are coupled to p-channel current-source transistor  68  through multiplier transistor  76 . 
     The higher VIN− causes more current to pass through differential transistor  66  than through differential transistor  64 . The increased current through transistor  66  pulls more current from current-source transistor  68 , causing its gate and drain, node VQ 1 , to fall in voltage. This lower VQ 1  voltage increases the current through p-channel transistor  88 . The higher current sourced by transistor  88  raises the voltage of node V 3 , and inverter  90  drives PD low (inactive). 
     The lower VIN− produces less current through transistor  64 . The lower current through transistor  64  pulls less current from current-source transistor  70 , causing its gate and drain, node VQ 2 , to rise in voltage. This higher VQ 2  voltage decreases the current through p-channel transistor  86 . The reduced current sourced by transistor  86  also reduces the current through n-channel transistor  82 , causing Its gate voltage to fall and reduce the current through n-channel transistor  84 . This reduces the pull-down current from node V 3  and thus helps raise the voltage of node V 3 , and inverter  90  drives PD low (inactive). 
     During normal operation when VIN− is higher than VIN+, multiplier transistors  74 ,  76 , which receive VIN+ at their gates, have a lower transconductance than multiplier transistors  72 ,  78 , which receive VIN− at their gates. Multiplier transistors  74 ,  76  tend to turn off when VIN+ goes low. 
     Changes in current through n-channel differential transistor  64  are coupled to p-channel current-source transistor  68  through multiplier transistor  72 , while changes in current through n-channel differential transistor  66  are coupled to p-channel current-source transistor  70  through multiplier transistor  78 . 
     The higher VIN− causes more current to pass through differential transistor  64  than through differential transistor  66 . The increased current through transistor  64  pulls more current from current-source transistor  68 , causing its gate and drain, node VQ 1 , to fall in voltage. This lower VQ 1  voltage increases the current through p-channel transistor  88 . The higher current sourced by transistor  88  raises the voltage of node V 3 , and inverter  90  drives PD low (inactive). 
     The lower VIN+ produces less current through transistor  66 . The lower current through transistor  66  pulls less current from current-source transistor  70 , causing its gate and drain, node VQ 2 , to rise in voltage. This higher VQ 2  voltage decreases the current through p-channel transistor  86 . The reduced current sourced by transistor  86  also reduces the current through n-channel transistor  82 , causing its gate voltage to fall and reduce the current through n-channel transistor  84 . This reduces the pull-down current from node V 3  and thus helps raise the voltage of node V 3 , and inverter  90  drives PD low (inactive). 
     Thus when either VIN+ or VIN− is higher, more current is sourced by current-source transistor  68  than by transistor  70 , and node VQ 1  is lower than VQ 2 , driving node V 3  high and PD low. 
     When VIN+ and VIN− are equal in voltage, the same current passes through all four multiplier transistors  72 ,  74 ,  76 ,  78 , since these have the same size. Differential transistors  64 ,  66  also sink identical currents, since these two transistors are the same size. Thus source currents through p-channel current-source transistors  68 ,  70  are nearly identical, causing nodes VQ 1 , VQ 2  to have the same voltage. 
     Different sizes are used for p-channel transistors  86 ,  88  in first filter comparator  80 . Transistor  86  is larger than transistor  88 , so that when VQ 1  and VQ 2  are equal, more current is sourced by transistor  86  than transistor  88 . The larger current in transistor  86  draws more current through n-channel transistor  82 , raising its gate voltage. This increases the pull-down current from node V 3  through n-channel transistor  84 , lowering V 3 . Since the voltage of VQ 1  is less when VIN+, VIN− have a differential voltage, and more when VIN+ and VIN− are equal, the higher VQ 1  reduces the source current through transistor  88 , allowing node V 3  to fall. The lower V 3  is inverted by inverter  90 , driving power-down signal PD high, activating the power-down mode. 
     FIG. 3 is a schematic of a complementary part of a differential equal-voltage detector. Differential inputs VIN+, VIN− are applied to second differential multiplier  20 , which is a Gilbert multiplier using complementary devices. The p-channel and n-channel transistors are generally reversed compared with FIG.  2 . Operating principles are similar. 
     While first differential multiplier  60  operates well when the common-mode voltage of VIN+, VIN− is above Vcc/2, performance can be degraded for voltages below Vcc/2. Second differential multiplier  20  and second filter comparator  40  having complementary devices are added to operate when the common-mode input voltage is below Vcc/2. 
     Bias generator  50  generates bias voltage BIASP that is applied to the gate of p-channel tail transistor  22 , which supplies current to all legs of second differential multiplier  20 . Bias generator  50  also generates BIASN for n-channel tail transistor  62  in second differential multiplier  60  of FIG.  2 . Bias generator  50  is a voltage divider of p-channel transistor  52 , resistor  56 , and n-channel transistor  54 . The gate and drain of p-channel transistor  52  generate bias BIASP, while gate and drain of n-channel transistor  55  generate bias BIASN. 
     The current from p-channel tail transistor  22  is split into two legs at the drain of transistor  22 . One current leg passes through p-channel differential transistor  24 , which has VIN− at its gate, while the other current leg passes through p-channel differential transistor  26 , which has VIN+ at its gate. When VIN+, VIN− are equal voltages, the same current passes through each leg. Non-equal VIN+, VIN− produce a current difference in the two legs. 
     The drain of p-channel differential transistor  24  is connected to the sources of p-channel multiplier transistors  32 ,  34 , which receive voltages VIN+, VIN−, respectively at their gates. This further splits current through transistor  24  into two legs. Similarly, the drain of p-channel differential transistor  26  is connected to the sources of p-channel multiplier transistors  36 ,  38 , which receive voltages VIN−, VIN+, respectively at their gates. This further splits current through transistor  26  into two legs. The source current of tail transistor  22  is thus split into a total of four current legs, through transistors  32 ,  34 ,  36 ,  38 . 
     The currents through multiplier transistors  32 ,  36  are combined since their drains are connected together. This combined current is sunk by n-channel current-sink transistor  28 , which has its gate and drain connected together as output node VM 1  from second differential multiplier  20 . This combined current includes one current through transistors  24 ,  32 , and another current through transistors  26 ,  36 . The gates of transistors  24 ,  32  are VIN−, VIN+, respectively, while gates of transistors  26 ,  36  are VIN+, VIN−, respectively. 
     The VM 1  output of second differential multiplier  20  is applied to the gate of n-channel transistor  48 , while the VM 2  output of second differential multiplier  20  is applied to the gate of n-channel transistor  46 . Mirrored current is provided to the drains of transistors  46 ,  48  by p-channel mirror transistors  42 ,  44 , respectively, which have their gates connected together and to the drain of p-channel mirror transistor  42 . The drains of p-channel mirror transistor  44  and n-channel transistor  48  are the V 3  output of first filter comparator  40 . 
     The currents from first filter comparator  80  and second filter comparator  40  are combined at node V 3 . When node V 3  rises above a switching threshold, PD is driven low. 
     Operation—FIG. 3 
     During normal operation when VIN+ is higher than VIN−, multiplier transistors  34 ,  36 , which receive VIN− at their gates, have a greater transconductance than multiplier transistors  32 ,  38 , which receive VIN+ at their gates. Multiplier transistors  32 ,  38  tend to turn off when VIN+ goes high. 
     Changes in current through p-channel differential transistor  24  are coupled to n-channel current-sink transistor  30  through multiplier transistor  34 , while changes in current through p-channel differential transistor  26  are coupled to n-channel current-sink transistor  28  through multiplier transistor  36 . 
     The lower VIN− causes more current to pass through p-channel differential transistor  24  than through differential transistor  26 . The increased current through transistor  24  pulls more current from current-sink transistor  30 , causing its gate and drain, node VM 2 , to rise in voltage. This higher VM 2  voltage increases the current through n-channel transistor  46 . The increased current sunk by transistor  46  increases the current through p-channel transistor  42 , causing its gate voltage to fall and increase the current through p-channel transistor  44 . This increases the pull-up current from node V 3  and thus helps raise the voltage of node V 3 , and inverter  90  drives PD low (inactive). 
     The higher VIN+ produces less current through transistor  26 . The reduced current through transistor  26  pulls less current from current-sink transistor  28 , causing its gate and drain, node VM 1 , to fall in voltage. This lower VM 1  voltage decreases the current through n-channel transistor  48 . The lower current sourced by transistor  48  raises the voltage of node V 3 , and inverter  90  drives PD low (inactive). 
     During normal operation when VIN+ is lower than VIN−, multiplier transistors  34 ,  36 , which receive VIN− at their gates, have a lower transconductance than multiplier transistors  32 ,  38 , which receive VIN+ at their gates. Multiplier transistors  34 ,  36  tend to turn off when VIN− goes high. 
     Changes in current through p-channel differential transistor  24  are coupled to n-channel current-sink transistor  28  through multiplier transistor  32 , while changes in current through p-channel differential transistor  26  are coupled to n-channel current-sink transistor  30  through multiplier transistor  38 . 
     The lower VIN+ causes more current to pass through differential transistor  26  than through differential transistor  24 . The increased current through transistor  26  pulls more current from current-sink transistor  30 , causing its gate and drain, node VM 2 , to rise in voltage. This higher VM 2  voltage increases the current through n-channel transistor  46 . The increased current sourced by transistor  46  also increases the current through p-channel transistor  42 , causing its gate voltage to fall and increase the current through p-channel transistor  44 . This increases the pull-up current from node V 3  and thus helps raise the voltage of node V 3 , and inverter  90  drives PD low (inactive). 
     The higher VIN− produces less current through transistor  24 . The lower current through transistor  24  pulls less current from current-sink transistor  28 , causing its gate and drain, node VM 1 , to fall in voltage. This lower VM 1  voltage decreases the pull-down current thorough n-channel transistor  48 . The lower current sourced by transistor  48  raises the voltage of node V 3 , and inverter  90  (FIG. 2) drives PD low (inactive). 
     Thus when either VIN− or VIN+ is lower, more current is sourced by current-sink transistor  30  than by transistor  28 , and node VM 1  is lower than VM 2 , driving node V 3  high and PD low. 
     When VIN− and VIN+ are equal in voltage, the same current passes through all four multiplier transistors  32 ,  34 ,  36 ,  38 , since these have the same size. Differential transistors  24 ,  26  also sink identical currents, since these two transistors are the same size. Thus sink currents through n-channel current-sink transistors  28 ,  30  are nearly identical, causing nodes VM 1 , VM 2  to have the same voltage. 
     Since the voltage of VM 1  is less when VIN−, VIN+ have a differential voltage, and more when VIN− and VIN+ are equal, the higher VM 1  increases the current through transistor  48 , causing node V 3  to fall. The lower V 3  is inverted by inverter  90 , driving power-down signal PD high, activating the power-down mode. 
     Different sizes are used for n-channel transistors  46 ,  48  in second filter comparator  40 . Transistor  46  is smaller than transistor  48 , so that when VM 1  and VM 2  are equal, more current is sunk by transistor  48  than transistor  46 . The smaller current in transistor  46  reduces the current through p-channel transistor  42 , which is mirrored to reduce the pull-up current through p-channel transistor  44 . The reduced pull-up current from node V 3  helps to pulls down node V 3 . 
     FIG. 4 is a waveform of operation of the equal-voltage power-down detector of FIGS. 2-3. When differential inputs VIN+, VIN− operate normally, as shown by the initial series of sine wave inputs, the square voltage difference V 2  is above VREF. Power-down signal PD is low. 
     When the differential signal strength weakens, as for the last sine wave in the initial series, the averaged voltage difference V 2  falls below VREF, although V 2  is still above zero. Then the power-down signal PD is driven high to power-down the receiver or a sub-system or circuit that uses the differential receiver&#39;s output. 
     When the dirrerential inputs VIN+, VIN− fully equalize, V 2  falls to zero. Since V 2  is still below VREF, power-down signal PD remains active. 
     When VIN+, VIN− again diverge, as shown by the rectangular wave sequence at the right of the waveform, the large input-voltage difference causes V 2  to rise above VREF. The power-down signal PD is driven low to deactivate the power-down mode. Note that different voltage differences produce different values of V 2  that are still above VREF. 
     ALTERNATE EMBODIMENTS 
     Several other embodiments are contemplated by the inventor. For example other components such as capacitors, resistors, buffers, and transistors may be added. Inversions may be added using inverters or by swapping differential lines. Many choices for transistor device sizes could be made. Additional stages could be added. Other kinds of bias-voltage generators could be substituted, or an external bias voltage used. Input and output buffers and drivers could be added. The sensitivity and switching threshold of the detector may be adjusted by varying ratios of transistor sizes, such as the ratio of the sizes of transistors  68 ,  88 . 
     First and second filter comparators  80 ,  40  may be combined so only one filter and comparator is needed. A voltage divider could be added before the multiplier to limit the Vin+ and Vin− DC bias voltage of the multiplier from 0 to Vdd/2 (if the multiplier in FIG. 3 is used), or from Vdd/2 to Vdd (if the multiplier in FIG. 2 is used). Thus, either differential multiplier  20  or  60  can work properly for input common mode voltage from 0 to Vdd. 
     Different filtering may be used, including addition of capacitors rather than using parasitic resistances and capacitances. Larger capacitance values can further smooth intra-cycle variations and prevent false triggering at cross-over when VIN+, VIN− are momentarily equal. Other kinds of multipliers could be substituted. 
     The abstract of the disclosure is provided to comply with the rules requiring an abstract, which will allow a searcher to quickly ascertain the subject matter of the technical disclosure of any patent issued from this disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims 37 C.F.R. § 1.72(b). Any advantages and benefits described may not apply to all embodiments of the invention. When the word “means” is recited in a claim element, Applicant intends for the claim element to fall under 35 USC § 112, paragraph 6. Often a label of one or more words precedes the word “means”. The word or words preceding the word “means” is a label intended to ease referencing of claims elements and is not intended to convey a structural limitation. Such means-plus-function claims are intended to cover not only the structures described herein for performing the function and their structural equivalents, but also equivalent structures. For example, although a nail and a screw have different structures, they are equivalent structures since they both perform the function of fastening. Claims that do not use the word means are not intended to fall under 35 USC § 112, paragraph 6. Signals are typically electronic signals, but may be optical signals such as can be carried over a fiber optic line. 
     The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.