Abstract:
An overdrive circuit having a first current source which supplies an overdrive current and a second current source which supplies an ordinary current smaller than the overdrive current. A first circuit operates the first current source that supplies the overdrive current for a predetermined time period after the start of current supply. A second circuit stops the action of the first current source after the predetermined time period has passed and drives the second current source to supply the ordinary current as the driving current.

Description:
This invention pertains to an overdrive circuit which operates switching elements, such as a switching regulator, at a high rate of speed. 
     BACKGROUND OF THE INVENTION 
     Conventionally, when the collector voltage of pnp or npn transistors used as switching elements installed outside of the IC in switching regulators, etc., is changed (increased or decreased) at high speed, a high speed operation has been done by temporarily increasing the base current of the external transistor by adding an external capacitive element (capacitor) to the drive circuit. 
     FIG. 5 is a circuit diagram which illustrates the first structural example of a conventional overdrive circuit. 
     In FIG. 5, I e1  is the current source, Q 1 , Q 2  are npn transistors, D 1  is a diode, R 1  is a resistance element, C 1  is an external capacitor, QPT 1  is an external pnp transistor, SD 1  is a Schottky diode, L 1  is a coil, C 2  is a capacitor, V CC  is the power source voltage, T 1 , T 2 , and T 3  are the input/output terminals of the IC (IC terminals, hereafter). 
     In this circuit, the current source I e1 , npn transistors Q 1 , Q 2 , diode D 1 , and the resistance element R 1  are formed inside of the IC, and each element is connected as follows: 
     That is, the collector and the base of the transistor Q 1  are connected to the current source I e1 , and the emitter is connected to the anode of the diode D 1 . The cathode of the diode D 1  is grounded. 
     The connection midpoints of the collector and the base of the transistor Q 1  are connected to the base of the transistor Q 2 . The collector of the transistor Q 2  is connected to the IC terminal T 1 , the emitter is connected to one end of the resistance element R 1  and the IC terminal T 2 , and the other end of the resistance element R 1  is grounded. 
     The electrode at one side of the external capacitor C 1  is connected to the IC terminal T 2 , and the other electrode is connected to the IC terminal T 3 . 
     The emitter of the external transistor QPT 1  is connected to the supply line of the power source voltage V CC , the base is connected to the IC terminal T 1 , and the collector is connected to the cathode of the Schottky diode SD 1  and one end of the coil L 1 . The anode of the Schottky diode SD 1  is grounded, the other end of the coil L 1  is connected to one electrode of the capacitor C 2 , the other electrode of the capacitor C 2  is grounded, and the connection midpoint of the other end of the coil L 1  and one electrode of the capacitor C 2  is connected to a load not illustrated in the figure. 
     In such a structure, the electric current from the current source I e1  is supplied to the collector and the base of the transistor Q 1 , and the base of the transistor Q 2 . 
     In this manner, both transistors Q 1  and Q 2  will be on, and the base emitter voltage V BE  portion of the diode D 1  will be impressed on both ends of the resistance terminal R 1  as the voltage V 1 . 
     At this time, in the initial state, while the charge flows into the transistor Q 2 , the overdrive current I OVR  such as illustrated in FIG. 6 will flow into the external capacitor C 1 , and this current is supplied to the base of the external transistor QPT 1 . 
     Therefore, the collector voltage V P1  of the external transistor QPT 1  will rapidly rise as illustrated in FIG. 7. 
     In this manner, high-speed operation is realized and conversion efficiency will increase. 
     FIG. 8 is a circuit diagram illustrating the second structural example of a conventional overdrive circuit. 
     In FIG. 8, I e2  is a current source, P 1  is a pnp transistor, Q 3  and Q 4  are npn transistors, D 2  and D 3  are diodes, R 2  is a resistance element, C 3  is an external capacitor, QPT 1  is an external pnp transistor, SD 1  is a Schottky diode, L 1  is a coil, C 2  is a capacitor, V CC  is power source voltage, and T 1 , T 2 , and T 3  indicate input/output terminals of the IC. 
     In the structure of this circuit, the transistors Q 1  and Q 2  and the diode D 1  in the circuit in FIG. 5 are replaced by the diode D 3 , transistor P 1 , and diode D 2 . The external capacitor C 3  and the resistance element R 2  play similar roles to those of the external capacitor C 1  and the resistance element R 1  in FIG. 5. The connecting relationship between each element in the IC is different from that in the circuit in FIG. 5. 
     That is, the anode of the diode D 2  is connected to the power source voltage V CC , and the cathode is connected to the anode of the diode D 3 . The cathode of the diode D 3  is connected to both the current source I e2  and the base of the transistor P 1 . 
     The emitter of the transistor P 1  is connected to one end each of the resistance element R 2  and the IC terminal T 3 , and the collector is connected to both the collector and the base of the transistor Q 3 . The other end of the resistance element R 2  is connected to the power source voltage V CC  and the IC terminal T 2 . 
     One electrode of the external capacitor C 3  is connected to the IC terminal T 2 , and the other electrode is connected to the IC terminal T 3 . 
     The emitter of the transistor Q 3  is grounded, and the connection midpoint between the collector and the base is connected to the base of the transistor Q 4 . The collector of the transistor Q 4  is connected to the IC terminal T 1 , and the emitter is grounded. 
     In the circuit in FIG. 8, when the electric current from the current source I e2  begins to flow, in the initial state, during the time while the charge of the external capacitor C 3  flows out via the transistor P 1 , the overdrive current I OVR  as illustrated in FIG. 9 will flow into the collector of the transistor P 1 . 
     That is, with regard to the collector current I P1  of the transistor P 1 , as illustrated in FIG. 9, the overdrive current I OVR  will flow temporarily. Such a collector current I P1  of the transistor P 1  is amplified by the transistors Q 3  and Q 4 , which constitute a current mirror circuit, and is supplied to the base of the external transistor QPT 1  as the current I Q4 . 
     Therefore, the collector voltage V P1  of the external transistor QPT 1  will rise quickly as illustrated in FIG. 7, and consequently, high speed operation is realized, and the conversion efficiency will increase. 
     Recently, in the field of portable equipment such as video cameras, the trend is to make the mounting area smaller by reducing as many external parts of the IC as possible. 
     However, with regard to the aforementioned conventional circuits, several hundred to several thousand pF will be needed as the capacitance for the capacitor C 1  in the circuit in FIG. 5, and several tens to several hundred pF will be needed as the capacitance for the capacitor C 3  in the circuit in FIG. 8. While it is possible to form a capacitor of several tens of pF inside the IC, this will result in an increased chip area, and consequently an increase in the IC cost. Therefore, it is inevitable that the aforementioned capacitors are attached outside the IC, meaning that a structure which is not desirable for the actual situation will be adopted, and which is a reason why the equipment is made larger. 
     It is an object of the present invention to provide an overdrive circuit that can have the number of external parts decreased without increasing the chip area or the IC cost. 
     SUMMARY OF THE INVENTION 
     An overdrive circuit in accordance with the invention has a switching element, a first current source which supplies a first current, a second current source which supplies a second current which is smaller than the first current, a first circuit which operates the first current source for a predetermined time period from the time of the starting of the driving of the switching element, and supplies the first current as the driving current for the switching element, and a second circuit which stops the operation of the first current source by means of the first circuit after the predetermined time period has expired, operates the second current source, and supplies the second current as the driving current for the switching element. 
     With the overdrive circuit in accordance with the invention, when the supply of driving current to the switching element is started, the first current source is initially driven by the first circuit. 
     Consequently, the first current, which is a large value, is supplied from the first current source to the external switching element as overdrive current. 
     After a predetermined time has passed from the start of supplying the first current, the operation of the first current source by the first circuit is stopped by the second circuit. At the same time, the second current source is driven by the second circuit. 
     Consequently, the second current, which has a smaller value than the first current, is supplied from the second current source to the external switching element as ordinary current. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a first embodiment of an overdrive circuit in accordance with the invention. 
     FIG. 2 is a graph illustrating the result of simulation by the circuit in FIG. 1 which does not use any external capacitor and by a conventional circuit. 
     FIG. 3 is a circuit diagram of a second embodiment of an overdrive circuit in accordance with the invention. 
     FIG. 4 is a circuit diagram of a third embodiment of an overdrive circuit in accordance with the invention. 
     FIG. 5 is a circuit diagram of a conventional overdrive circuit. 
     FIG. 6 is a waveform illustrating the base current of an external transistor in the circuit of FIG. 5. 
     FIG. 7 is a waveform illustrating the collector voltage of the external transistor. 
     FIG. 8 is a circuit diagram of a second conventional overdrive circuit. 
     FIG. 9 is a waveform illustrating the collector current of the transistor P 1  in the circuit of FIG. 8. 
    
    
     Symbols as shown in the drawings: ##EQU1## 
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 1 is a circuit diagram of a first embodiment of an overdrive circuit in accordance with the invention. 
     In FIG. 1, I e11  is a current source, Q 11  -Q 13  are npn transistors, PG 11  and PG 12  are pnp transistor groups, R 11  -R 14  are resistance elements, Q M11  -Q M15  are npn transistors for the current mirror circuit MR, QPT 1  is an external pnp transistor, T 1  is an IC terminal, and V CC  is the power source voltage. 
     The pnp transistor group PG 11  is configured by connecting the bases to bases, the emitters to emitters, and the collectors to collectors of the pnp transistors P 111  -P 113 , respectively. 
     Similarly, the pnp transistor group PG 12  is configured by connecting the bases to bases, the emitters to emitters, and the collectors to collectors of the pnp transistors P 121  -P 123 , respectively. 
     The bases to bases, the emitters to emitters, and the collectors to collectors of the npn transistors Q M13  -Q M15  of the current mirror circuit MR are also connected. 
     The collector of the npn transistor Q 11  is connected to each of the connection midpoints between bases of the pnp transistor group PG 11 , one end of the resistance element R 13 , and the base of the npn transistor Q 12 , the base is connected to both the emitter of the npn transistor Q 13  and one end of the resistance element R 11 , and the emitter is connected to each of the other end of the resistance element R 11  and the emitter of the npn transistor Q 12 , respectively. 
     The connection midpoint between the emitter of the transistor Q 11  and the other end of the resistance element R 11  constitutes the node ND 1 , and is connected to the constant current source I e11 . 
     The collector of the npn transistor Q 12  is connected to the connection midpoint between the bases of the pnp transistor group PG 12 . 
     The connection midpoint between the collectors of the pnp transistor group PG 11  is connected to each of the connection midpoints between the collectors of the pnp transistor group PG 12 , the base of the transistor Q M11  and the collector of the transistor Q M12  of the current mirror circuit MR. The connection midpoint between the emitters is connected to one end of the resistance element R 12 . 
     The connection midpoint between the emitters of the pnp transistor group PG12 is connected to one end of the resistance element R 11 . 
     The other ends of the resistance elements R 12 , R 13 , and R 14  are connected to the power source voltage V CC . With regard to the resistance value of these resistance elements R 12 , R 13 , and R 14 , for instance, the resistance value of the resistance element R 12  is set at 2 kΩ, the resistance value of the resistance element R 13  is set at 50 kΩ, and the resistance value of the resistance element R 14  is set at 200 kΩ. 
     The collector of the transistor Q M11  of the current MR mirror circuit is connected to the power source voltage V CC , and the emitter is connected to both the base of the transistor Q M12  and the connection midpoints between the bases of the transistors Q M13  -Q M15 . Both the emitter of the transistor Q M12  and the connection midpoints between the emitters of the transistors Q M13  -Q M15  are grounded, and the connection midpoint between the collectors of the transistors Q M13  -Q M15  is connected to the IC terminal T 1 . 
     The IC terminal T 1  is connected to the base of the external pnp transistor QPT 1 . The emitter of the external pnp transistor QPT 1  is connected to the power source voltage V CC , and the collector is connected to both the Schottky diode SD 1  and the coil L 1  in the same way as in FIG. 5. 
     The operation of the aforementioned structure will be explained next. 
     First, when the electric current starts flowing in the current source I e11 , and the voltage of the node ND 1  starts decreasing, since the resistance element R 11  is connected between the base and the emitter of the transistor Q 11 , and the resistance element R 13  is connected to the base of the transistor Q 12  from the power source voltage V CC , between the transistors Q 11  and Q 12 , the transistor Q 12  will be first to conduct. 
     Since the collector of the transistor Q 12  is connected to the connection midpoint between the bases of the pnp transistor group PG 12 , accompanying the fact that the transistor Q 12  is on, the base current will flow into the pnp transistor group PG 12 . 
     Here, if the current flowing in the resistance element R 11  and the transistor Q 13  is ignored, the current I e12  will flow in the emitter of the transistor Q 12  until the electric potential of the node ND 1  reaches (V CC  -2V SE ). 
     Suppose the saturation voltage V CESATQ12  of the transistor Q 12  is 0.1 V, the voltage V 14  applied to the resistance element R 14  will be as in the following formula: ##EQU2## 
     Thus, supposing the current amplification factor h fe  of the pnp transistor group PG 12  is infinite, the current I PG12  of the value indicated by the following formula will flow in the collector of the pnp transistor group PG 12  as overdrive current: 
     
         I.sub.PG12 2=0.6 V/R.sub.14V,                              (2) 
    
     where R 14V  indicates the resistance value of the resistance element R 14 . 
     However, in actuality, since the operation is transient, the value of the collector current I PG12  of the pnp transistor group PG 12  will be smaller than the value given by formula (2). 
     This overdrive current will receive an amplification function in the current mirror circuit MR, and be supplied to the base of the external transistor QPT 1  via the IC terminal T 1 . 
     When the amplified overdrive current is supplied, the rise of the collector voltage V P1  of the external transistor QPT 1  will suddenly change; thus, the high speed operation will be realized, and the conversion efficiency will increase. 
     When the electric potential of the node ND 1  reaches (V CC  -2V BE ), the transistor Q 11  will be on. 
     Since the collector of the transistor Q 11  is connected to the base of the transistor Q 12 , when the transistor Q 11  is on, consequently, the transistor Q 12  will be switched from on to off. 
     As a result, the pnp transistor group PG 12  will be off, and the supply of overdrive current by the pnp transistor group PG 12  will be stopped. 
     Since the collector of the transistor Q 11  is connected to the connection midpoint between the bases of the pnp transistor group PG 11 , when the transistor Q 11  is on, consequently, the pnp transistor group PG 11  will be on. 
     As a result, the current I PG11  will flow in the collector of the pnp transistor group PG 11  as ordinary current. 
     Suppose the saturation voltage V CESATQ11  of the transistor Q 11  is 0.1 V, the voltage V 12  applied to the resistance element R 12  will be as indicated by the following formula: ##EQU3## 
     Thus, supposing the current amplification factor h fe  of the pnp transistor group PG 11  is infinite, the value of the ordinary current I PG11  which flows in the collector of the pnp transistor group PG 11  is given by the following formula: 
     
         I.sub.PG11 =0.6V/R.sub.12V,                                (4) 
    
     where R 12V  indicates the resistance value of the resistance element R 12 . 
     This ordinary current receives an amplification function in the current mirror circuit MR, and is supplied to the base of the external transistor QPT 1  via the IC terminal T 1 . 
     As described above, in this circuit, the overdrive current is determined by the resistance element R 14 , and the ordinary current is determined by the resistance element R 12 . 
     FIG. 2 is a graph illustrating the result of a simulation both by the circuit in FIG. 1 which does not use an external capacitor and a conventional circuit which uses an external capacitor. 
     This simulation was made under the atmosphere of the ambient temperatures of 125° C. and -25° C. 
     In FIG. 2, the horizontal coordinate indicates the time (μsec) and the vertical coordinate indicates the base current (A) of the external transistor QPT 1 , respectively. 
     In FIG. 2, the curve of thick solid line labeled X 125  is the result of simulation by the circuit in FIG. 1 under an atmosphere of 125° C., the curve of thick solid line labeled X -25  is the result of simulation by the circuit in FIG. 1 under an atmosphere of -25° C., the curve of thin solid line labeled Y 125  is the result of simulation by a conventional circuit under an atmosphere of 125° C., and the curve of thin solid line labeled Y -25  is the result of simulation by a conventional circuit under an atmosphere of -25° C. 
     As can be observed in FIG. 2, the circuit in FIG. 1 can induce overdrive current in a good condition, and consequently it can realize a high-speed operation, and can improve the conversion efficiency. 
     As explained above, in this embodiment, since overdrive current can be induced in a good condition only with a logical circuit without using an external capacitance, the number of external parts can be reduced without increasing the chip area or the IC cost. 
     The overdrive current and the ordinary current can be set separately by the resistance elements R 14 , and R 12 , respectively; thus, for instance, setting can be made arbitrarily using an external resistance element, etc. 
     In this embodiment, the number of transistors which the pnp transistor groups PG 11  and PG 12  connect was three. However, the number of such transistor connecting is not limited to this embodiment. 
     That is, if it is possible for a large volume of current to flow to the base of the external transistor QPT 1 , one transistor will be enough. The number will be determined by the manufacturing process, etc. 
     FIG. 3 is a circuit diagram of a second embodiment of an overdrive circuit in accordance with the invention. 
     This second embodiment of FIG. 3 is different from the first embodiment of FIG. 1 in terms of the following points. Instead of the transistor Q13, this circuit is configured by the Schottky diode SD 11 . The current source I e11  is configured by the npn transistor Q 14  where the external signal S 11  is supplied to the base. The current mirror circuit MR is configured by one npn transistor QM 16 . 
     In this configuration, the base of the npn transistor QM 16  is connected to the connection midpoint between the collectors of the pnp transistor groups PG 11  and PG 12 , the collector is connected to the IC terminal T 1 , and the emitter is grounded. 
     The other configuration is the same as that of the first embodiment. The same effect as that of the first embodiment can be obtained. 
     FIG. 4 is a circuit diagram of a third embodiment of an overdrive circuit in accordance with the invention. 
     The third embodiment of FIG. 4 is different from the first embodiment of FIG. 1 in terms of the following points: This circuit is configured by the npn transistor QNT 1  instead of the pnp transistor QPT 1  as the external transistor, and the connection midpoint between the emitters of the transistors Q M12  -Q M15  of the current mirror circuit MR is connected to the IC terminal T 1 . 
     While the first embodiment of FIG. 1 is a decreasing pressure chopper circuit, the third embodiment of FIG. 4 is an increasing pressure chopper circuit. The emitter of the transistor QNT 1  is grounded, and the collector is connected to one end of the coil L 1  and the anode of the diode SD 1 . 
     In this embodiment, the fall of the collector potential of the transistor QNT 1  will be fast; thus, the high speed operation of the circuit can be realized and the conversion efficiency can be improved in a similar fashion to the first embodiment. 
     As explained above, with this invention, the overdrive current can be induced in a good condition with only a logic circuit without using any external capacitor, and the number of external parts can be reduced without increasing the chip area or the IC cost. 
     Also, with this invention, the overdrive current can be supplied to the switching element by means of a circuit configured by transistors, resistance elements, etc., without using the charge-discharge current of the capacitor; thus, the effects that the manufacture of semiconductor integrated circuits will be easier, the cost will be lower, and the whole circuit can be integrated in one semiconductor chip, etc., can be obtained.