Abstract:
A method and a circuit achieve fully isolated sampling of bipolar differential voltage signals. The isolated sampling network is suitable for applications in which sampling signals far outside of the supply voltages are desired. A sampling network of the present invention may sample a differential signal between voltages −V DSMAX  and V DSMAX , even with common mode voltages that exceed the supply voltage (e.g., an input stage of an ADC). The bipolar isolated input sampling network may include a polarity comparator and sampling switches that operate as rectifiers. Rectification ensures that a unipolar sampling network needs only to sample signals of predetermined voltage levels.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     The present application relates to and claims priority of U.S. provisional patent application (“Provisional Application”), Ser. No. 61/897,067, entitled “Bipolar Isolated High Voltage Sampling Network,” filed on Oct. 29, 2013. The disclosure of Provisional Application is incorporated by reference in its entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to isolated sampling of differential input signals. In particular, the present invention relates to isolated sampling of differential input signals in a sampling network, such as an input stage of an analog-to-digital converter (ADC). 
     2. Discussion of the Related Art 
       FIG. 1  is a schematic diagram of a differential double-correlated sampling instrumentation amplifier (circuit  100 ) disclosed in the article (“the Yen article”), entitled “A MOS Switched-Capacitor Instrumentation Amplifier,” by R. C. Yen and P. R. Gray, published in the  IEEE Journal of Solid State Circuits , pp. 1008-13, December, 1982. As shown in  FIG. 1 , circuit  100  of  FIG. 1  shorts the input terminals V IN   +  and V IN   −  with switch S 3  that is controlled by a signal φ 2 . Signal φ 2  is a logic signal that swings within the power supply voltages. As circuit  100  does not use charge pumps for controlling the input sampling network, circuit  100  is unable to sample far outside of the power supply voltages. 
       FIG. 2  shows a prior art ADC driver circuit that receives a single-ended input signal to provide a differential signal for an ADC. As shown in  FIG. 2 , the ADC driver circuit requires resistive dividers and an additional buffer amplifier to limit the differential voltage at the ADC input terminals to a voltage swing that is close to that of the ADC&#39;s supply voltages. 
     SUMMARY 
     According to one embodiment of the present invention, a method and a circuit achieve fully isolated sampling of bipolar differential voltage signals. The isolated sampling network is suitable for applications in which sampling signals far outside of the supply voltages is desired. A sampling network of the present invention may sample a differential signal between voltages −V DSMAX  and V DSMAX , even with common mode voltages that exceed the supply voltage (e.g., an input stage of an ADC). The bipolar isolated input sampling network may include a polarity comparator and sampling switches that operate as rectifiers. Rectification ensures that a unipolar sampling network needs only to sample signals of predetermined voltage levels. A sampling network of the present invention may sample a differential signal between voltages −V DSMAX  and V DSMAX , even with common mode voltages that exceed the supply voltage. In one implementation, an ADC with a maximum supply voltage of 3V is able to sample differential signals of ±3V or more at a common mode voltage of 10V. 
     A bipolar isolated sampling network of the present invention may sample a differential input signal having a voltage swing between minus V DSMAX  to plus V DSMAX . Such a sampling network (i) has better noise and increased linearity, as no resistive divider or buffer amplifier is needed, (ii) has lower power consumption and less aging and drift, due to its shorter analog signal processing chain, and (iii) allows sampling of signals far beyond the power supply voltage. In one embodiment, the source terminals of the sampling switches are connected to low impedance points, so that local charge pumps may be connected to control the gate voltage of the sampling switches relative to the potential at the source terminals of the sampling switches. 
     The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of a differential double-correlated sampling instrumentation amplifier (circuit  100 ) disclosed in the prior art. 
         FIG. 2  shows a prior art ADC driver that receives a single-ended input signal to provide a differential signal for an ADC. 
         FIG. 3  shows isolated sampling network  600  disclosed in a copending patent application by the present inventor. 
         FIG. 4  is a block diagram of differential isolated ADC input sampling network  400  that can accurately sample positive input voltages, which is controlled by complementary, but non-overlapping clock signals PHI 1  and PHI 2 . 
         FIG. 5  shows the waveforms of clock signals PHI 1  and PHI 2  of  FIG. 4 . 
         FIG. 6  is a block diagram of input sampling network  700  which includes rectifier circuit  701  that provides a positive differential signal to input sampling network  400 , in accordance with one embodiment of the present invention. 
         FIG. 7  is a block diagram of input sampling network  800  in which switched capacitor polarity comparator  803  detects signal polarity from the output differential signal of sampling circuit  400 , in accordance with one embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       FIG. 3  shows isolated sampling network  600  disclosed in the present inventor&#39;s copending patent application (“Copending Patent Application”), entitled “ISOLATED HIGH VOLTAGE SAMPLING NETWORK,” Ser. No. 13/841,459, filed Mar. 15, 2013. The Copending Patent Application is hereby incorporated by reference in its entirety. Isolated sampling network  600  can sample differential signals from minus two diode drops up to two times the maximum drain-to-source voltage (V DSMAX ) for a given technology in which isolated sampling network  600  is implemented. As shown in  FIG. 3 , PMOS device S 4  samples positive input terminal VP and NMOS device S 1  samples negative input terminal VM. Body diodes of PMOS device S 4  and NMOS device  51  turn on when the differential input voltage across positive input terminal VP and negative input terminal VM reaches minus two diode drops, thereby constraining the negative differential voltage that can be sampled to minus two diode drops. 
       FIG. 4  is a block diagram of differential isolated ADC input sampling network  400  that can accurately sample positive input voltages, which is controlled by complementary, but non-overlapping clock signals PHI 1  and PHI 2 . The waveforms of clock signals PHI 1  and PHI 2  are shown in  FIG. 5 . As shown in  FIG. 4 , input sampling network  400  includes charge pump circuits  406   a ,  406   b ,  407   a  and  407   b , switches S 1   a , S 1   b , S 2   a  and S 2   b , and input sampling capacitors C SA  and C SB  of ADC  403 . Clock signal PHI 1   b  is the inverted signal of clock signal PHI 1 . Clock signal PHI 2   b  is the inverted signal of clock signal PHI 2 . (Inverted signals are applied to charge pumps connected to PMOS switches because a negative gate-to-source voltage causes an PMOS switch to become conducting.) In sampling network  400 , when clock signal PHI 1  is at logic HIGH (i.e., “active”), switches S 1   a  and S 2   b  are conducting and switches S 2   a  and S 1   b  are non-conducting, so that differential signal Vs across input terminals  401  and  402  is presented at input terminals  404  and  405  of ADC  403 . When clock signal PHI 2  is active, switches S 2   a  and S 1   b  are conducting and switches S 1   a  and S 2   b  are non-conducting, so that differential signal Vs across input terminals  401  and  402  is presented in opposite polarity (i.e., −Vs) to input terminals  404  and  405  of ADC  403 . Presenting the input signal in opposite polarities to ADC  403  allows offsets in the ADC circuit be canceled out, thereby enhancing accuracy. However, when input voltage Vs falls below minus one diode drop, the parasitic diodes of input sampling switches S 1   b  and S 2   a  at PHI 1  active (or S 2   b  and S 1   a  at PHI 2  active) become conductive, thereby causing significant sampling errors. Therefore, similar to isolated sampling network  600  of  FIG. 3 , the input voltage range Vs across terminals  401  and  402  in sampling network  400  is limited from minus one diode drop to plus V DSMAX . Charge pumps  406   a ,  406   b ,  407   a  and  407   b  may be implemented in the same manner as charge pumps  402   a  and  402   b  shown in  FIG. 3 . 
     According to one embodiment of the present invention, the deficiency in input sampling network  400  is overcome by ensuring that it only receives positive input signals.  FIG. 6  is a block diagram of input sampling network  700  which includes rectifier circuit  701  that provides a positive differential signal to input sampling network  400 , in accordance with one embodiment of the present invention. In  FIG. 6 , input sampling circuit  400  is shown in single-ended form for brevity. However, it is understood that input sampling network  400  may be implemented in the differential input form shown in  FIG. 4 . As shown in  FIG. 6 , polarity comparator  703  determines the polarity of input differential signal V in  across input terminals  705  and  706 . Output signal  707  of polarity comparator  703 , representing the polarity determination, selectively activates switch pairs S 3  and S 6  or S 4  and S 5  through charge pumps  711   a  through  711   d . When input differential signal V IN  is positive, output signal  703  causes switches S 3  and S 6  to be conducting through the input signals to charge pumps  711   a  and  711   d . When input differential signal V IN  is negative, output signal  703  causes switches S 4  and S 5  to be conducting through the input signals to charge pumps  711   b  and  711   c . This results in a signal inversion which would cause the ADC to sample the wrong signal polarity. The control signals to charge pumps  711   a - 711   d  may be implemented in combinational circuit by those of ordinary skill in the art. (This rectification results in a signal inversion which would cause ADC  704  to sample the wrong signal polarity.) Output signal  707  may be stored into a flip-flop or register to record a polarity of input differential signal V IN , so as to allow proper restoration of polarity in the output value from ADC  704 . Alternatively, the sampling phases of clock signals PHI 1  and PHI 2  at switches S 1  (i.e., switches S 1   a  and S 2   b  of  FIG. 4 ) and S 2  (i.e., switches S 2   a  and S 1   b  of  FIG. 4 ) must be exchanged to compensate for the signal inversion. Such an exchange may be implemented by multiplexers that exchanges clock signals PHI 1  and PHI 2 . Since input signal Vs across terminals  708  and  709  may become slightly negative without causing sampling errors, polarity comparator  703  is preferably provided some hysteresis to prevent a signal that has a magnitude close to polarity comparator  703 &#39;s threshold from causing too many signal inversions. Output signal  707  of polarity comparator  707  is sampled by the ADC sampling clock and therefore causes only signal inversions that are synchronous with the ADC sampling clock. 
       FIG. 7  is a block diagram of input sampling network  800  in which switched capacitor polarity comparator  803  detects signal polarity from the output differential signal of sampling circuit  400  by reusing switches S 1  and S 2  as input switches, in accordance with one embodiment of the present invention. 
     Accordingly, a bipolar isolated input sampling network of the present invention is capable of sampling large bipolar differential signals using isolated sampling switches. The input range is significantly extended to between V DSMAX  and V DSMAX . Any signal inversion in the rectifier circuit may be compensated by changing the polarity sensitivity of subsequent blocks (e.g., by swapping clock signals PHI 1  and PHI 2  in isolated sampling network  400  of  FIGS. 6 and 7 ) of the ADC. 
     The above detailed description is provided to illustrate specific embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is set forth in the accompanying claims.