Abstract:
The invention provides a method of making a transistor. A gate dielectric layer is formed on a semiconductor substrate. A gate is formed on the dielectric layer, the gate having an exposed upper surface and exposed side surfaces. A first silicon nitride layer having a first thickness is deposited over the gate, for example over an oxide layer on the gate, at a first deposition rate. A second silicon nitride layer having a second thickness is deposited over the first silicon nitride layer at a second deposition rate, the second thickness being more that the first thickness and the second deposition rate being more than the first deposition rate. The first silicon nitrogen layer then has a lower hydrogen concentration. At least the second silicon nitride layer (or a silicon oxide layer in the case of an ONO spacer) is etched to leave spacers next to the side surfaces while exposing the upper surface of the gate and areas of the substrate outside the spacers.

Description:
BACKGROUND OF THE INVENTION 
     1). Field of the Invention 
     This invention relates generally to a method of making a transistor and more specifically to a method according to which side wall spacers of the transistor are made. 
     2). Discussion of Related Art 
     Electronic circuits are often manufactured in and on semiconductor wafers. Such an electronic circuit often includes millions of tiny transistors. Such a transistor usually includes a gate dielectric layer formed on the semiconductor material of the wafer, followed by a gate having a width in the region of 0.15 microns. Ions are implanted next to the gate to form lightly doped regions. Spacers are then formed adjacent side walls of the gate and more ions are implanted adjacent the spacers. The spacers shield an area of the semiconductor material near the gate from the higher concentration of ions due to the second implantation step. 
     The formation of the spacers usually involves the deposition of a silicon nitride layer over and next to the gate, followed by an anisotropic etch which removes upper surfaces of the silicon nitride layer until the gate is exposed and surfaces of the semiconductor material outside the spacers are exposed for the second ion implantation step. The silicon nitride layer is deposited by introducing relatively high concentrations of SiH 4  and NH 3  gases into a chamber, which react with one another to form silicon nitride which then deposits out. Due to the high concentrations of these gases and other factors such as temperature, pressure, and flow rate, hydrogen is usually trapped within the silicon nitride layer. The hydrogen may diffuse into the gate and the semiconductor material thus affecting functioning of the transistor. 
     SUMMARY OF THE INVENTION 
     The invention provides a method of making a transistor. A gate dielectric layer is formed on a semiconductor substrate. A gate is formed on the dielectric layer, the gate having an exposed upper surface and exposed side surfaces. A first silicon nitride layer having a first thickness is deposited over the gate, for example over an oxide layer on the gate, at a first deposition rate. A second layer having a second thickness is deposited over the first silicon nitride layer at a second deposition rate, the second thickness being more than the first thickness and the second deposition rate being more than the first deposition rate. The second layer is then etched to leave spacers next to the side surfaces while exposing the upper surface of the gate and areas of the substrate outside the spacers. The first silicon nitride layer then has a lower hydrogen concentration than the second layer. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention is further described by way of example with reference to the accompanying drawings wherein: 
     FIG. 1 is a cross-sectional side view illustrating an apparatus which may be used for carrying out the method according to the invention; 
     FIG. 2 is a cross-sectional side view illustrating an initial stage of semiconductor transistor fabrication; 
     FIG. 3 is a view similar to FIG. 2 after a first silicon nitride layer is deposited; 
     FIG. 4 is a view similar to FIG. 3 after a second silicon nitride layer is deposited; 
     FIG. 5 is a view similar to FIG. 4 after an etch step; 
     FIG. 6 is a view similar to FIG. 5 after implantation of ions; 
     FIG. 7 is a time chart of wafer temperature during the formation of the first and second silicon nitride layer shown in FIGS. 3 and 4; 
     FIG. 8 is a time chart of total pressure during the deposition of the first and second silicon nitride layers; 
     FIG. 9 is a time chart of SiH 4  partial pressure during the deposition of the first silicon nitride layer and the deposition of the second silicon nitride layer; and 
     FIG. 10 is a time chart of NH 3  partial pressure during the deposition of the first silicon nitride layer and the second silicon nitride layer. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 of the accompanying drawings illustrates an apparatus  10  which is used for carrying out the method according to the invention. The apparatus includes a chamber  12 , a susceptor  14 , a valve  16 , a pump  18 , a slit valve  20 , and a dispersion plate  21 . The susceptor  14  is located in a base of the chamber  12 . The valve  16  is connected to an upper part of the chamber  12  and the pump  18  is connected to a base of the chamber  12 . The slit valve  20  opens and closes a slit valve opening in a side of the chamber  12 . The dispersion plate  21  is located in the chamber  12  above the slit valve  20  and separates the chamber  12  into upper and lower portions. 
     In use, a wafer substrate  22  is inserted through the slit valve opening into the chamber  12  and located on the susceptor  14 . The slit valve  20  then closes the slit valve opening. The valve  16  is closed and the pump  18  is switched on so that a pressure within the chamber  12  reduces. Gases are then introduced through the valve  16  into the chamber  12  and flow through openings  24  in the dispersion plate  21  through the chamber to the pump  18 . The wafer substrate  22  is then exposed to the gases. The valve  16  is typically connected to a manifold which is connected to different gases. Different gases can thus be introduced into the chamber  12  at different times. The pump  18  can be operated to maintain the pressure within the chamber  12  at a certain level, or to increase or decrease the pressure. A resistive heater  26  is located within the susceptor  14 . A current through the resistive heater  26  causes heating of the susceptor and the wafer substrate  22 . An apparatus (not shown) is used to monitor the pressure within the chamber  12  and another apparatus (not shown) detects the temperature of the wafer substrate  22 . The method according to the invention may be carried out in different chambers or all only in the apparatus  10  shown in FIG.  1 . 
     FIG. 2 of the accompanying drawings illustrates initial fabrication of the transistor, all of which is conventional. A silicon wafer is provided on which a monocrystalline epitaxial silicon layer  30  is formed, followed by a gate dielectric layer  32 , and then a transistor gate  34 . The gate dielectric layer  32  is made of a dielectric material such as silicon oxide and is typically only a few tens of angstroms thick. The transistor gate  34  is typically made of a polysilicon which is later doped to make it conductive. The polysilicon layer is patterned utilizing conventional photoresist technology. Following patterning of the polysilicon layer, the transistor gate  34  remains with an exposed upper surface  36  and exposed side surfaces  38 . Surfaces  40  of the epitaxial silicon layer  30  on opposing sides of the gate  34  are also exposed. 
     Following the patterning of the gate  34 , ions are implanted into the surfaces  40 . The implanted ions form lightly doped source and drain regions  42  on opposing sides of the gate  34 . The ions dope the regions  42  oppositely to doping of the epitaxial silicon layer  30 . The epitaxial silicon layer  30  may, for example, be N-doped and the regions  42  be P-doped. 
     A high-temperature oxide layer  44  is subsequently deposited. The high-temperature oxide layer  44  is located on the surfaces  36 ,  38 , and  40 . The intention of the high-temperature oxide layer  44  is to provide a good barrier which prevents diffusion of hydrogen from silicon nitride layers that are subsequently deposited into the gate  34 , the epitaxial silicon layer  30 , and the source and drain regions  42 . 
     Processing is now illustrated, in time sequence, with respect to FIGS. 3-6. Reference is also made to FIGS. 7-10, which are time charts of processing conditions utilized according to an embodiment of the invention. FIG. 9, for example, illustrates SiH 4  partial pressure as it varies to obtain the layers shown in FIGS. 3 and 4. 
     As shown in FIG. 7, the temperature of the wafer substrate is increased to approximately 700° C. As shown in FIG. 8, the total pressure within the chamber is increased from approximately 0 Torr to approximately 275 Torr by flowing an N 2  carrier gas into the chamber. In another embodiment, the temperature may be between 400° C. and 800° C. and the pressure between 50 and 350 Torr. 
     SiH 4  and NH 3  gases are introduced into the chamber, together with an N 2  carrier gas. As shown in FIG. 9, the SiH 4  gas has a partial pressure within the chamber of only approximately 0.15 Torr and flows at a rate of approximately 5 standard cubic centimeters (sccm). As shown in FIG. 10, the NH 3  gas has a partial pressure of only approximately 0.46 Torr and flows at a rate of approximately 20 sccm. The SiH 4  and NH 3  react with one another to form silicon nitride which deposits as a first silicon nitride layer  48 . The first silicon nitride layer  48  forms on all surfaces of the high-temperature oxide layer  44 . The first silicon nitride layer  48  forms at a rate of approximately 100 Å per minute, which is relatively low and has a thickness of approximately 100 Å. Because of the relatively low rate at which the first silicon nitride layer forms, relatively little hydrogen is trapped in the first silicon nitride layer  48 . The first silicon nitride layer  48  is thus relatively pure. Not only does the purity of the first silicon nitride layer  48  contribute to less diffusion of hydrogen from the first silicon nitride layer  48  through the high-temperature oxide layer  44 , but the first silicon nitride layer  48  also creates a barrier which prevents diffusion from layers formed on top of the first silicon nitride layer  48  therethrough to the high-temperature oxide layer  44  and components located below the high-temperature oxide layer  44 . 
     In another embodiment, the deposition rate of the first silicon nitride layer  48  may be between 50 and 300 Å per minute. The first silicon nitride layer  48  may be between 50 and 200 Å thick. The partial pressure of the SiH 4  may be between 0.10 and 1.5 Torr. The total pressure may be between 50 and 350 Torr. The temperature may be between 400° C. and 800° C. It may also be possible to use other silicon-containing process gases instead of or in addition to SiH 4 , such as Si 2 H 6 , etc. It may also be possible to form the first silicon nitride layer  48  utilizing another silicon nitride process such as a process known in the art as “atomic layer deposition.” 
     The partial pressure of the SiH 4  is then increased to approximately 1.0 Torr and the flow rate of the SiH 4  is increased to approximately 50 sccm. The partial pressure of the NH 3  is simultaneously increased to approximately 90 Torr and the flow rate of the NH 3  is increased to approximately 4000 sccm. Temperature and pressure are maintained constant. The SiH 4  and NH 3  react with one another to form silicon nitride which deposits as a second silicon nitride layer  50 . A boundary between the layers  48  and  50  may or may not be definite. The second silicon nitride layer  50  deposits on all upper and side surfaces of the first silicon nitride layer  48 . The second silicon nitride layer deposits at a rate of between 500 and 1000 Å per minute and is approximately 700 Å thick. Because of the high rate of deposition of the second silicon nitride layer  50 , it is likely that the second silicon nitride layer  50  may include more hydrogen and other contaminants. However, these contaminants do not diffuse through the barrier provided by the first silicon nitride layer  48  and the underlying silicon oxide layer  44 , especially during subsequent high-temperature processing. 
     In another embodiment the second silicon nitride layer  50  may be between 300 and 1200 Å thick. The second silicon nitride layer  50  may deposit at a rate of between 300 and 2000 Å per minute. The second silicon nitride layer  50  may deposit at a rate which is at least 500 Å per minute higher than the deposition rate of the first silicon nitride layer  48 . Partial pressure of the SiH 4  while depositing the second silicon nitride layer  50  may be between 1.5 and 100 Torr. The total pressure may be between 50 and 350 Torr while depositing the second silicon nitride layer  50 . The wafer temperature while depositing the second silicon nitride layer  50  may be between 400 and 800° C. The partial pressure of the SiH 4  while depositing the second silicon nitride layer  50  may be at least 0.5 Torr, more preferably at least 1.0 Torr higher than the partial pressure while depositing the first silicon nitride layer  48 . The second silicon nitride layer  50  is preferably at least three times, more preferably at least seven times as thick as the first silicon nitride layer  48 . It may also be possible to form a silicon oxide layer instead of the second silicon nitride layer  50 , the layers  44 ,  48 , and  50  thus forming an oxide-nitride-oxide (ONO) structure with a more distinct boundary between the layers  48  and  50 . 
     FIG. 5 illustrates subsequent processing wherein the layers  44 ,  48 , and  50  are etched back. An anisotropic etchant is used which removes upper surfaces of the layers  44 ,  48 , and  50  without much removal of side surfaces of these layers. Etching is continued until the surfaces  40  and  36  are exposed. Spacers  52  remain on the surfaces  40  next to the side surfaces  38 . Each spacer  52  includes a portion of the silicon oxide  44 , a portion of the first silicon nitride layer  48 , and a portion of the second silicon nitride layer  50 . The location of the first silicon nitride layer  48  is L-shaped. The location of the second silicon nitride layer  50  is in a comer of the L shape of the first silicon nitride layer  48 . 
     As shown in FIG. 6, ions are then implanted into the surfaces  40 . The spacers  52  prevent ion implantation into the silicon layer  30  below the spacers  52 . The concentration and depth of the P-doped regions  42  is thereby increased below exposed areas of the surfaces  40 . 
     While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and not restrictive of the current invention, and that this invention is not restricted to the specific constructions and arrangements shown and described since modifications may occur to those ordinarily skilled in the art.