Abstract:
A circuit comprising an oscillator configured to generate a periodic signal in response to (i) control signal and (ii) a current. The current may be varied independently of the control signal. In one example, the oscillator may generate the periodic signal in further response to a second current that may vary in response to the control signal. In another example, the oscillator may be used in a phase-locked loop circuit.

Description:
FIELD OF THE INVENTION 
     The present invention relates to oscillators generally and, more particularly, to a method, circuit and/or architecture to improve the frequency range of a voltage controlled oscillator. 
     BACKGROUND OF THE INVENTION 
     Referring to FIG. 1, an example of a conventional phase locked loop circuit  10  is shown. The circuit  10  generally comprises phase frequency detector  12 , a charge pump  14 , a voltage controlled oscillator (VCO)  16  and a divider  18 . The circuit  10  is used to multiply a reference signal REFCLK having a fixed frequency, received at an input  24 , by some multiple set by the divider  18 . The frequency detector  12  is coupled to the VCO  16  through the charge pump/filter  14 . The divider circuit  18  has an input  28  that receives a feedback of the signal CLK presented at an output  30  of the VCO  16 . The divider  18  presents a signal to an input  32  of the frequency detector  12 . Errors coupled through the charge pump  14  cause the VCO  16  to change the frequency of the signal CLK to minimize the error. VCO frequency errors may be managed by the circuit  10 . The nominal frequency of operation of the signal CLK will be the frequency of the reference signal REFCLK multiplied by the divider ratio. 
     The VCO  16  is an integral part of the PLL  10 . The gain of the VCO  16  (i.e., the frequency of the signal CLK vs. the change in the input control voltage Vcontrol), and the frequency range of the VCO  16  are two very important design parameters. The gain of the VCO  16  is important to determine the bandwidth of the PLL  10 . Also, the gain of the VCO  16  has a significant impact on jitter (i.e., high frequency semi-random displacement of a signal from its ideal location). The frequency of the VCO  16  determines the operating frequency of the PLL  10 . 
     FIG. 2 illustrates a diagram of a conventional VCO  16 . The VCO  16  is usually made up of a voltage to current converter  40  and a current controlled oscillator (ICO)  50 . The converter  40  comprises a current mirror  42 , a comparator  44 , a transistor  46  and a resistor R. The frequency of operation of the VCO  16  is directly dependent on the current Ivco received by the ICO  50 . The current Ivco is the voltage of the signal Vcontrol divided by the resistance R. The higher the current IVCO, the higher frequency of the signal CLK. The current of the ICO  50  depends on the value of resistor R. Also, the gain of the VCO  16  depends on the value of the resistor R. 
     The value of the resistance R determines the gain of the VCO  16  (i.e., slope of the F-V curve). Changing the gain of the VCO  16  will also change the frequency of operation of VCO  16 . This may put the frequency of the VCO  16  out of the required range. 
     SUMMARY OF THE INVENTION 
     The present invention concerns a circuit comprising an oscillator configured to generate a periodic signal in response to (i) control signal and (ii) a current. The current may be varied independently of the control signal. In one example, the oscillator may generate the periodic signal in further response to a second current that may vary in response to the control signal. In another example, the oscillator may be used in a phase-locked loop circuit. 
     The objects, features and advantages of the present invention include providing an oscillator that may (i) generate a signal having a frequency that may be adjusted without changing the gain of the oscillator, (ii) have an expanded frequency range, (iii) provide an offset current to adjust the frequency, and/or (iv) provide post-production configuration of the oscillator. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
     FIG. 1 is a block diagram of a conventional PLL; 
     FIG. 2 is a block diagram of the ICO included in the VCO of FIG. 1; and 
     FIG. 3 is a block diagram of a preferred embodiment of the present invention; and 
     FIG. 4 is a timing diagram illustrating the operation of the circuits of FIG.  2  and FIG.  3 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 3, a block diagram of a circuit  100  is shown in accordance with a preferred embodiment of the present invention. The circuit  100  generally comprises a generation block (or circuit)  102  and an adjustment block (or circuit)  104 . The generation block  102  generally comprises a voltage-to-current converter block (or circuit)  105  and a current controlled oscillator (ICO)  106 . The converter circuit  105  generally comprises a comparator  110 , a transistor  112 , a transistor  114 , a transistor  116  and a resistor R. The transistor  112  and the transistor  116  may form a current mirror  117 . The converter circuit  105  generally presents a current (e.g., Imir) to an input  120  of the ICO  106 . The ICO  106  generally presents a signal (e.g., CLK) at an output  122 . The adjustment circuit  104  generally presents a current (e.g., Ioffset) at an output  124  that may also be presented to the input  120  of the ICO  106 . The current Ioffset is generally added or subtracted from the current Imir, to present a current Ivco, which may ultimately control the frequency of oscillation of the signal CLK. The adjustment circuit  104  generally comprises one or more current sources  130   a - 130   n.    
     The offset current Ioffset may be independently varied with respect to the signal Vcontrol. The generation of the offset current Ioffset may be added to a VCO structure. In one example, the offset current Ioffset is generally small compared to the current Ivco and may provide fine tuning of the frequency of oscillation of the signal CLK. However, the offset current Ioffset may also provide large variations in the frequency of oscillation of the signal CLK. In general, the frequency of oscillation of the signal CLK may depend on the value of the resistor R plus the value of the current offset Ioffset as defined by the following Equation EQ1: 
     
       
         Ivco=(VCON/R)+/−Ioffset  EQ1 
       
     
     However, the current offset Ioffset does not generally affect the gain of the VCO  16 , because the gain of the VCO  16  generally depends only on the value of the resistor R. 
     Referring to FIG. 4, a diagram illustrating the operation of the circuit of FIG. 3 compared to the circuit of FIG. 2 is shown. FIG. 4 includes a waveform  200 , a waveform  202  and a waveform  204 . The waveform  200  may be a frequency versus current plot of the signal CLK. When the offset current Ioffset is increased or decreased, the waveform  200  may shift up or down on the frequency curve, as illustrated by the waveform  202 . A gain curve  206  illustrates a portion of the waveform  200  between a vertical line  210  and a vertical line  212 . During the gain curve  206 , the output of the signal CLK generally varies linearly in response to the signal Ivco. Similarly, a gain curve  208  provides a generally linearly increase in the frequency of the signal CLK between the vertical lines  210  and  212 . As a result, the gain of the circuit  100  generally remains constant while the frequency of oscillation of the signal CLK is varied in response to the offset current Ioffset. 
     In contrast, the waveform  204  illustrates an example of the operation of the circuit of FIG.  2 . Specifically, the gain portion of the curve  204  is shown having a much more steep slope. 
     As a result, the frequency of the signal CLK is only adjusted between the vertical lines  220  and  222 . This reduces the overall adjustability of the signal CLK. The circuit of FIG. 2 changes the slope of the gain portion of the waveform  204  at the same time that it increases the overall oscillation of the signal CLK. Similarly, if the frequency of oscillation of the signal CLK is decreased, the slope of the gain portion  214  would correspondingly decrease. Such changes in the gain portion are undesirable since they directly change the amount of current necessary to adjust the frequency of oscillation of the signal CLK. 
     The value of the resistor R and the value of the offset current Ioffset may be optimized to achieve the required gain and frequency range. For example, the range of the frequency of oscillation of the signal CLK may be, in one example, varied between 10 and 500 MHz. In one example, the offset current Ioffset may be small compared to the overall value of the current Ivco. However, large adjustments in the signal Ioffset may be implemented accordingly to meet the design criteria of a particular implementation. For example, the offset current Ioffset may be, in one example, between 0 and 2% of the value of the current Ivco. In another example, the current Ioffset may be between 0 and 20% of the value of the signal Ivco. In yet another example, the current Ioffset may be between 0 and 50% of the value of the signal Ivco. In a further example, the current Ioffset may be between 0 and 90% of the value of the signal Ivco. In any event, the signal Ioffset is generally independently variable with respect to the value of the signal VCON or the value of the current Imir. Additionally, the offset current Ioffset may be a negative current that is actually subtracted from the value of the signal Ivco which may decrease the frequency of oscillation of the signal CLK. 
     The current sources  130   a - 130   n  may be adjustable current sources that may provide an optimal value of the offset current Ioffset. For example, the current sources  130   a - 130   n  may be adjusted after fabrication of the circuit  100  by various means including fuses, metal mask options, configuration bits from an EEPROM, configuration bits from a digital-to-analog converter (DAC), configuration bits from an analog-to-digital converter (ADC), etc. Additionally, each of the current sources  130   a - 130   n  may be independently adjustable. 
     While the voltage to current converter circuit  105  is shown implemented with P-channel transistors  112  and  116 , other transistors, such as N-channel transistors may be implemented accordingly to meet the design criteria of a particular implementation. 
     The present invention may also be constructed by making the current offset Ioffset a part of the voltage to current converter  105 , or by making the current offset Ioffset a part of the current controlled oscillator  106 . 
     The present invention may be used to provide post-production configuration of the frequency of oscillation of the signal CLK. In one example, the post-production configuration may be used to calibrate a particular part to operate within a particular specification. In another example, the post-production configuration may allow a single part to be used in a variety of applications. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.