Abstract:
A loading stage for outputting an amplified differential output, including: a noise source inducing noises originally located in a first frequency band, and a first modulating device coupled to the noise source for modulating the noises into a second frequency band from the first frequency band.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of co-pending U.S. patent application Ser. No. 11/778,645 (filed on Jul. 16, 2007) which claims the benefit of U.S. Provisional Application No. 60/807,721, (filed on Jul. 19, 2006), the contents of which are incorporated herein by reference. 
     
    
     BACKGROUND 
       [0002]    The present invention relates to an operating operational amplifier, and more particularly, to a folded cascode operating amplifier and an operating method thereof. 
         [0003]    In applications involving analog-to-digital converter (ADC) chips, the processing of noise signals is a primary concern. For example, in an ADC or a digital-to-analog converter (DAC), increasing the signal-to-noise ratio (SNR) is regarded as an important design consideration. One of the critical factors influencing the SNR is the transistor flicker noise. Flicker noise is an unwanted energy level that is generated when many dangling bonds appear at the interface between an oxide layer and the silicon substrate in the gate terminal of a transistor. When a charge carrier moves on the interface, some carriers are randomly captured and then released to the energy level to allow the drain terminal current to generate flicker noise. Therefore, reducing the flicker noise in an operational amplifier is a primary design concern. 
         [0004]    Enlarging the area of a transistor is one method to reduce flicker noise. The energy associated with the flicker noise is related to the voltage source of the transistor gate terminal. The exact relationship is provided below in the following formula (Razavi, B, “Design of Analog CMOS Integrated Circuits”, pp. 215, McGraw Hill): 
         [0000]    
       
         
           
             
               
                 V 
                 n 
                 2 
               
               _ 
             
             = 
             
               
                 K 
                 
                   
                     C 
                     OX 
                   
                    
                   WL 
                 
               
                
               
                 1 
                 f 
               
             
           
         
       
     
         [0005]    From the above-described formula, it can be induced from the inverse proportionality of WL that the component area must increase as (f) noise signal decreases. Moreover, an accompanying stray capacitance acts to increase the chip power load. Generally, noise from a PMOS transistor is less than that of an NMOS transistor. 
       SUMMARY OF THE INVENTION 
       [0006]    One of the objectives of the claimed invention is to therefore provide an operational amplifier with a modulating device to modulate the flicker noise from a current source into a higher frequency. 
         [0007]    According to an embodiment of the present invention, a loading stage for outputting an amplified differential output is disclosed. The loading stage comprises a noise source and a first modulating device. The noise source induces noises originally located in a first frequency band. The first modulating device is coupled to the noise source for modulating the noises into a second frequency band from the first frequency band. 
         [0008]    According to a second embodiment of the present invention, an operational amplifier is disclosed. The operational amplifier comprises an input stage, a loading stage, a noise source, and a first modulating device. The input stage receives a differential input signal pair. The loading stage outputs an amplified differential output at output nodes. The noise source induces noises originally located in a first frequency band. The first modulating device is coupled to the noise source for modulating the noises into a second frequency band from the first frequency band, wherein the first modulating device is not within a signal path. 
         [0009]    According to a third embodiment of the present invention, an operational amplifier is disclosed. An operational amplifier comprises an input stage and a loading stage. The input stage receives a differential input signal pair. The loading stage outputs an amplified differential output at output nodes, and comprises a noise source and a first modulating device. The noise source induces noises originally located in a first frequency band. The first modulating device is coupled to the noise source for modulating the noises into a second frequency band from the first frequency band, wherein the first modulating device is not within a signal path. 
         [0010]    According to a fourth embodiment of the present invention, an analog-to-digital converter is disclosed. The analog-to-digital converter comprises a sigma-delta modulator and a digital decimation filter. The sigma-delta modulator receives an input signal and generating a first output signal, wherein the sigma-delta modulator comprises a plurality of operational amplifiers, noises from at least one noise source of the operational amplifiers are modulated by a modulating device from a first frequency band into a second frequency band, and the modulating device is not within a signal path. The digital decimation filter receives the first output signal and filtering out the modulated flicker noises to generate a second output signal. 
         [0011]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  is a diagram illustrating an operational amplifier according to a first embodiment of the present invention. 
           [0013]      FIG. 2  is a timing diagram illustrating the relationship between the clock rate and the first and second control clocks of the embodiment shown in  FIG. 1 . 
           [0014]      FIG. 3  is a simulation diagram illustrating the output power (dB) versus the frequency (Hz) of the embodiment of  FIG. 1 . 
           [0015]      FIG. 4  is a diagram illustrating an operational amplifier according to a second embodiment of the present invention. 
           [0016]      FIG. 5  is a diagram illustrating an operational amplifier according to a third embodiment of the present invention. 
           [0017]      FIG. 6  shows a diagram of an ADC using sigma-delta modulation technique. 
       
    
    
     DETAILED DESCRIPTION 
       [0018]    Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. 
         [0019]    Please refer to  FIG. 1 .  FIG. 1  is a diagram illustrating an operational amplifier  300  according to a first embodiment of the present invention. The operational amplifier  300  comprises an input stage  301  and a loading stage  302 . The input stage  301  comprises a first and a second transistor M 1 , and M 2 . The first and second transistors M 1 , M 2  form a differential pair configuration with source terminals N 1  coupled together, and a first current source I 1  is further coupled to the terminal N 1 . A gate of the first transistor M 1  and a gate of the second transistor M 2  are utilized for receiving a differential input signal pair Vi+, Vi− corresponding to a first frequency band fin. Furthermore, the modulating device  3011  is coupled to a drain terminal N 2  of the first transistor M 1  and a drain terminal N 3  of the second transistor M 2 , a first connecting node N 4  is coupled to a second current source I 2  (e.g. N-type transistor M 7 ), and a second connecting node N 5  is coupled to a third current source I 3  (e.g. N-type transistor M 8 ). The loading stage  302  is coupled to the drain terminal N 2  of the first transistor M 1 , and the drain terminal N 3  of the second transistor M 2 , for amplifying outputs at the drain terminal N 2  of the first transistor M 1  and the drain terminal N 3  of the second transistor M 2  in order to generate a differential output signal pair Vout+, Vout− at a first output node N 6  and a second output node N 7 . Please note that, in order to describe the spirit of the invention more clearly, the loading stage  302  can be implemented using a cascode configuration, therefore making the present invention become a folded cascode operating amplifier; however, this is not a limitation of the present invention. In the embodiment shown in  FIG. 1 , the loading stage  302  comprises a third transistor M 3 , a fourth transistor M 4 , a fifth transistor M 5 , and a sixth transistor M 6 . The source terminals of the third transistor M 3  and the fourth transistor M 4  are coupled to the terminal N 2  and N 3 , respectively; and the fifth transistor M 5  and the sixth transistor M 6  are cascoded to the third transistor M 3  and the fourth transistor M 4  at terminals N 6  and N 7 . 
         [0020]    In addition, the modulating device  3011  comprises a first switch S 1 , a second switch S 2 , a third switch S 3 , and a fourth switch S 4 . The first switch S 1  is coupled between the first connecting node N 4  and the terminal N 2 , the second switch S 2  is coupled between the second connecting node N 5  and the terminal N 3 ; the third switch S 3  is coupled between the first connecting node N 4  and the terminal N 3 ; and the fourth switch S 4  is coupled between the second connecting node N 5  and the terminal N 2 , wherein the first and second switches S 1 , S 2  are controlled by a first control clock S ck1 , and the third and fourth switches S 3 , S 4  are controlled by a second control clock S ck1bar , which is the inversed clock of the first control clock S ck1 . 
         [0021]    The embodiment of  FIG. 1  further comprises a fourth current source I 4  (e.g. P-type transistor M 9 ) coupled to a source terminal N 8  of the fifth transistor M 5 , and a fifth current source I 5  (e.g. P-type transistor M 10 ) coupled to the source terminal N 9  of the sixth transistor M 6 . 
         [0022]    One of the applications of the operational amplifier  300  of the present invention is being the operational amplifier of a Delta-Sigma analog-to-digital converter (Delta-Sigma ADC), but this should not be taken as a limitation of the present invention. Therefore, when the operational amplifier  300  operates in the Delta-Sigma ADC, an internal clock V ck  must be accompanied with the differential input signal pair Vi+, Vi−. Furthermore, the frequency of the internal clock V ck  can be designed to be 128 times the sampling rate f sample  of the Delta-Sigma ADC, and the frequency of the first control clock S ck1  and the second control clock S ck1bar  can be designed to be 8 times the sampling rate. Please note that the determination of the first and second control clocks S ck1 , S ck1bar  is prior art, and further description is thus omitted here for brevity. Please refer to  FIG. 2 .  FIG. 2  is a timing diagram illustrating the relationship between the clock rate and the first and second control clock S ck1 , S ck1bar  of the embodiment of  FIG. 1 . Furthermore, it is well-known that the flicker noise generated by the N-type transistor is much higher than that of the P-type transistor, therefore the modulating device  3011  of this embodiment is mainly positioned to block the flicker noise generated by the N-type transistors M 7  and M 8 . On the other hand, the terminals N 2  and N 3  are the low impedance nodes of the operational amplifier  300 , and the modulating device  3011  is not positioned on the signal path of the operational amplifier  300 , therefore adding the modulating device  3011  between the terminals N 2 , N 3 , and N 4 , N 5  will not affect the differential input signal pair Vi+, Vi− that is to be amplified. A signal path is a path from a signal input node to a signal output node for transmitting a wanted signal. 
         [0023]    In  FIG. 2 , the first control clock S ck1  turns on the first switch S 1  and the second switch S 2  at time t 2  to link the first connecting node N 4  and the terminal N 2 , and to link the second connecting node N 5  and the terminal N 3  respectively. In this embodiment, the time t 2  is located between the time t 1  and t 3 , which is the high level of the internal clock V ck . Meanwhile, the second control clock S ck1bar  turns off the third switch S 3  and the fourth switch S 4  at time t 1 . After 8 cycles of the internal clock V ck , the first control clock S ck1  turns off the first switch S 1  and the second switch S 2  at time t 5 , while the second control clock S ck1bar  turns on the third switch S 3  and the fourth switch S 4  to link the first connecting node N 4  and the terminal N 3 , and to link the second connecting node N 5  and the terminal N 2  respectively. Similarly, the time t 5  is located between the time t 4  and t 6 , which is the high level of the internal clock V ck . Then, the modulating device  3011  will repeat to switch between the first connecting node N 4  and the terminal N 2 , and the second connecting node N 5  and the terminal N 3 . Accordingly, the flicker noise generated by the N-type transistors M 7  and M 8  will be modulated to odd harmonics of the frequency of the first and second control clocks S ck1 , S ck1bar  at the first output node N 6  and the second output node N 7 . Furthermore, because the modulating device  3011  is not positioned on the signal path of the operational amplifier  300 , a down modulation is not needed. Therefore, one modulating device is sufficient in the embodiment. 
         [0024]    Please refer to  FIG. 3 .  FIG. 3  is a simulation diagram illustrating the output power (dB) versus the frequency (Hz) of the embodiment of  FIG. 1 . The simulation result is obtained by adding 20 mV offset at the differential input signal pair Vi+, Vi−. When the modulating device  3011  is discarded from the operational amplifier  300 , the noise at low frequency will increase tremendously at the output of the amplifier, as shown by the dotted line  501 . However, when the modulating device  3011  is implemented in the operational amplifier  300 , the noise at low frequency will be removed at the output of the amplifier, as shown by the line  502 . The line  503  represents the power of the output signal at the desired frequency, which is at about 10 KHz. Accordingly, using only one modulating device in the present invention can achieve excellent performance in the noise figure of the operational amplifier. 
         [0025]    Please refer to  FIG. 4 .  FIG. 4  is a diagram illustrating an operational amplifier  600  according to a second embodiment of the present invention. The operational amplifier  600  comprises an input stage  601  and a loading stage  602 . The input stage  601  comprises a first and a second transistor M 1 ′, and M 2 ′. The first and second transistors M 1 ′, M 2 ′ form a differential pair configuration with source terminals N 1 ′ coupled together, and a first current source I 1 ′ further coupled to the terminal N 1 ′. A gate of the first transistor M 1 ′ and a gate of the second transistor M 2 ′ are utilized for receiving a differential input signal pair Vi+, Vi− corresponding to a first frequency band f in . Furthermore, the first modulating device  6011  is coupled to a drain terminal N 2 ′ of the first transistor M 1 ′ and a drain terminal N 3 ′ of the second transistor M 2 ′, a first connecting node N 4 ′ is coupled to a second current source I 2 ′ (e.g. N-type transistor M 7 ′), and a second connecting node N 5 ′ is coupled to a third current source I 3 ′ (e.g. N-type transistor M 8 ′). The loading stage  602  is coupled to the drain terminal N 2 ′ of the first transistor M 1 ′ and the drain terminal N 3 ′ of the second transistor M 2 ′, for amplifying outputs at the drain terminal N 2 ′ of the first transistor M 1 ′ and the drain terminal N 3 ′ of the second transistor M 2 ′ to generate a differential output signal pair Vout+, Vout− at a first output node N 6 ′ and a second output node N 7 ′ respectively. Please note that, in order to describe the spirit of the invention more clearly, the loading stage  602  can be implemented using a cascode configuration, therefore making the present embodiment become a folded cascode operating amplifier; however, this is not a limitation of the present invention. In the embodiment shown in  FIG. 4 , the loading stage  602  comprises a third transistor M 3 ′, a fourth transistor M 4 ′, a fifth transistor M 5 ′, a sixth transistor M 6 ′, and a second modulating device  6021 . The source terminals of the third transistor M 3 ′ and the fourth transistor M 4 ′ are coupled to the terminal N 2 ′ and N 3 ′, respectively; and the fifth transistor M 5 ′ and the sixth transistor M 6 ′ are cascoded to the third transistor M 3 ′ and the fourth transistor M 4 ′ at terminals N 6 ′ and N 7 ′. 
         [0026]    Furthermore, the second modulating device  6021  is coupled to a source terminal N 8 ′ of the fifth transistor M 5 ′ and a source terminal N 6 ′ of the sixth transistor M 6 ′, a third connecting node N 10 ′ is coupled to a fourth current source I 4 ′ (e.g. P-type transistor M 9 ′), and a fourth connecting node N 11 ′ is coupled to a fifth current source I 5 ′ (e.g. P-type transistor M 10 ′). Please note that the configuration and the operation of the first modulating device  6011  and the second modulating device  6021  are mostly the same as the modulating device  3011  of  FIG. 1 , thus the detailed description of the first modulating device  6011  and the second modulating device  6021  are omitted. A skilled person will easily understand that the second modulating device  6021  is utilized for modulating the flicker noise generated by P-type transistors M 9 ′, M 10 ′ to odd harmonics of the frequency of the control clock of the second modulating device  6021  after reading the above disclosure in view of  FIG. 1 . Furthermore, please note that the control clock of the first modulating device  6011  is not necessarily the same as the control clock of the second modulating device  6012 . In other words, the frequency of the control clock of the first modulating device  6011  can be different from the control clock of the second modulating device  6012 . 
         [0027]    Please refer to  FIG. 5 .  FIG. 5  is a diagram illustrating an operational amplifier  700  according to a third embodiment of the present invention. The operational amplifier  700  comprises an input stage  701  and a loading stage  702 . The input stage  701  comprises a first and a second transistor M 1 ″, M 2 ″. The first and second transistors M 1 ″, M 2 ″ form a differential pair configuration with source terminals N 1 ″ coupled together, and a first current source I 1 ″ further coupled to the terminal N 1 ″. A gate of the first transistor M 1 ″ and a gate of the second transistor M 2 ″ are utilized for receiving a differential input signal pair Vi+, Vi− corresponding to a first frequency band f in . Furthermore, a drain terminal N 2 ″ of the first transistor M 1 ′ is coupled to a second current source I 2 ″ and a drain terminal N 3 ′ of the second transistor M 2 ′ is coupled to a third current source I 3 ″. The loading stage  702  is coupled to the drain terminal N 2 ″ of the first transistor M 1 ″ and the drain terminal N 3 ″ of the second transistor M 2 ″, for amplifying outputs at the drain terminal N 2 ″ of the first transistor M 1 ″ and the drain terminal N 3 ″ of the second transistor M 2 ″ to generate a differential output signal pair Vout+, Vout− at a first output node N 6 ″ and a second output node N 7 ″. In this embodiment, the loading stage  702  is implemented using a cascode configuration, therefore making the present embodiment become a folded cascode operating amplifier; however, this is not a limitation of the present invention. In the embodiment of  FIG. 5 , the loading stage  702  comprises a third transistor M 3 ″, a fourth transistor M 4 ″, a fifth transistor M 5 ″, a sixth transistor M 6 ″, and a modulating device  7021 . The source terminals of the third transistor M 3 ″ and the fourth transistor M 4 ″ are coupled to the terminal N 2 ″ and N 3 ″, respectively; and the fifth transistor M 5 ″ and the sixth transistor M 6 ″ are cascoded to the third transistor M 3 ″ and the fourth transistor M 4 ″ at terminals N 6 ″ and N 7 ″. 
         [0028]    Furthermore, the modulating device  7021  is coupled to a source terminal N 8 ″ of the fifth transistor M 5 ″ and a source terminal N 6 ″ of the sixth transistor M 6 ″, a first connecting node N 10 ″ is coupled to a fourth current source I 4 ″ (e.g. P-type transistor M 9 ″), and a second connecting node N 11 ″ is coupled to a fifth current source I 5 ″ (e.g. P-type transistor M 10 ″). Please note that the configuration and the operation of the modulating device  7021  is mostly the same as the modulating device  3011  of  FIG. 1 , and thus a detailed description of the modulating device  7021  is omitted. A skilled person will easily understand that the modulating device  7021  is utilized for modulating the flicker noise that is generated by P-type transistors M 9 ″, M 10 ″ to odd harmonics of the frequency of the control clock of the modulating device  7021  after reading the disclosure in view of  FIG. 1 . 
         [0029]    The operational amplifiers mentioned in the above description can be used in an analog-to-digital converter (ADC) using sigma-delta modulation technique.  FIG. 6  shows a diagram of an ADC using sigma-delta modulation technique. The ADC  800  comprises a sigma-delta modulator  802  and a digital decimation filter  804 . The sigma-delta modulator  802  may comprise a plurality of operational amplifiers and each of the operational amplifiers may have flicker noise sources, such as current sources. Embodiments of operational amplifiers mentioned in the above description can be implemented into the sigma-delta modulator  802  for modulating flicker noises into a higher frequency band. 
         [0030]    For example, as shown in  FIG. 6 , an input signal  806  is inputted into, and processed by the sigma-delta modulator  802  to generate a first output signal  808 . Flicker noises of the operational amplifiers in the sigma-delta modulator  802  are modulated by a modulating device (such as the modulating device  3011  in  FIG. 1 ) into a higher frequency band (such as the higher frequency band  814  shown in  FIG. 6 ). A frequency domain diagram  810  is used to illustrate frequency components of the first output signal  808 . In the frequency domain diagram  810 , flicker noises have been modulated from a lower frequency band into a higher frequency band  814 . Thus, quantization noises and modulated flicker noises are all within the higher frequency band  814 . The desired signal  812  is left at a lower frequency band. 
         [0031]    In this embodiment, there are two clock inputs. One with frequency f CLK , and the other with frequency f MOD . f CLK  is the over-sampling frequency of the sigma-delta modulator  802 , which could be 256xf S , 128xf S , 64xf S , or other values, depending upon designers&#39; choice, where f S  is the sampling frequency of the ADC. f MOD  is the frequency of the modulating device for modulating flicker noises. 
         [0032]    The digital decimation filter  804 , serving as a low-pass filter, can filter out the higher frequency band  814  and let the desired signal  812  pass through. Therefore, a second output signal  811  outputted by the digital decimation filter  804  has only the desired signal. 
         [0033]    Removing flicker noises is especially important in audio signal processing because an audio signal is at a low frequency band (usually ranging from 20 Hz to 20 kHz). These embodiments can achieve good performance for audio signal processing. 
         [0034]    The frequency of the control clock of the modulating device  3011  can be different from the control clock of the modulating device  7012 . A skilled person will easily understand the steps of the noise reduction method, and therefore a detailed description is omitted for brevity. 
         [0035]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.