Abstract:
Flash memory devices having a cell string structure. According to the present invention, the size of a first group of memory cells connected to a first word line and a second group of memory cells connected to a last word line is formed greater than that of a third group of memory cells respectively connected to the remaining word lines other than the first and last word lines. Accordingly, the program speed of the first and second groups of the memory cells can be improved.

Description:
BACKGROUND  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to flash memory devices, and more specifically, to NAND-type flash memory devices having a uniform program speed.  
         [0003]     2. Discussion of Related Art  
         [0004]     A flash memory is a type of non-volatile memory that can maintain data when power is off and can be electrically programmed and erased. It does not need a refresh function of rewriting data on a predetermined cycle. In this case, the term “program” refers to an operation of writing data into memory cells, and the term “erase” refers to an operation of erasing data from a memory. This flash memory device can be largely classified into a NOR-type and a NAND type depending on the structure and operation condition of cells. In the NOR-type flash memory, the source of each memory cell transistor is connected to a ground terminal (VSS), and program and erase can be performed on a predetermined address. The NOR-type flash memory has been usually used for fields requiring a high-speed operation. On the other hand, in the NAND-type flash memory, a plurality of memory cell transistors is serially connected to form one string, and one string is connected to the source and drain. The NAND-type flash memory has been usual used for fields such as high-integration data retention.  
         [0005]      FIG. 1  is a layout diagram showing the configuration of a unit cell string of a common NAND-type flash memory device.  
         [0006]     Referring to  FIG. 1 , a unit cell string of the NAND-type flash memory device includes a source select transistor SST connected to a common source line (not shown), a drain select transistors DST connected to a bit line (not shown), and memory cells MC 0  to MC 31  serially connected between the source select transistor SST and the drain select transistors DST. Furthermore, the gate of the drain select transistors DST is connected to a drain select line DSL, the gate of the source select transistor SST is connected to a source select line SSL, and the gates of the memory cells MCC 1  to MC 31  are connected to word lines WL 0  to WL 31 , respectively. In this case, the number of the memory cells MC serially connected between the source select transistor SST and the drain select transistors DST is 16, 32, or 64 in consideration of a device and density.  
         [0007]     In the unit cell string structure as shown in  FIG. 1 , the program speed of the memory cells MC 0  and MC 31  connected to the first and last word lines WL 0  and WL 31  is slower than that of the remaining memory cells MC 1  to MC 30 . This is because the first word line WL 0  is adjacent to the source select line SSL and the last word line WL 31  is adjacent to the drain select line DSL.  
         [0008]     To be more specific, in a program operation, a program prohibit voltage (Vpass) is applied to non-selected word lines, whereas the ground voltage (VSS) is applied to the source select line SSL and the power supply voltage (VCC) is applied to the drain select line DSL. If so, the memory cells MC 0  and MC 31  experience interference by a voltage of the source select transistor SST and the drain select transistors DST, so that the program speed of the memory cells MC 0  and MC 31  becomes slower than that of the remaining memory cells MC 1  to MC 30 .  
         [0009]      FIG. 2  is a graph showing a threshold voltage depending on each word line in  FIG. 1 . A low threshold voltage corresponds to a slow program speed.  
         [0010]     From  FIG. 2 , it can be seen that the threshold voltage (Vt) of the memory cell MC 31  connected to the last word line WL 31  that is the nearest to the drain select line DSL is the lowest, and the threshold voltage (Vt) of the memory cell MC 0  connected to the first word line WL 0  that is the nearest to the source select line SSL is the second lowest.  
         [0011]     As described above, if the threshold voltage of particular memory cells (for example, MC 0  and MC 31  adjacent to DST and SST) is lower than that of the remaining memory cells MC 1  to MC 30 , the program speed of the NAND-type flash memory device becomes non-uniform and distribution of the threshold voltage with a chip widens. This results in a degraded performance of the NAND-type flash memory devices.  
       SUMMARY OF THE INVENTION  
       [0012]     An advantage of the present invention is a NAND-type flash memory device in which the program speed can be improved for a first group of memory cells connected to word lines that are the nearest to a source select line and a second group of memory cells connected to word lines that are the nearest to a drain select line of the memory cells respectively connected to the word lines.  
         [0013]     Another advantage of the present invention is a NAND-type flash memory device in which the program speed can be improved for memory cells connected to the last word line that is the nearest to a drain select line of the memory cells respectively connected to the word lines.  
         [0014]     According to one embodiment of the present invention, there is provided a non-volatile memory device, including first select transistors, each connected to a plurality of bit lines, second select transistors connected to a common source line, and a plurality of memory cells respectively connected between the first select transistors and the second select transistors in series and connected to the plurality of word lines, respectively. In this case, the size of a first group of memory cells connected to a first word line and a second group of memory cells connected to a last word line, of the plurality of word lines, is greater than that of a third group of memory cells connected to the remaining word lines, respectively, other than the first and last word lines.  
         [0015]     According to another embodiment of the present invention, there is provided a NAND-type flash memory device, including first select transistors, each connected to a plurality of bit lines, second select transistors connected to a common source line, and a plurality of memory cells respectively connected between the first select transistors and the second select transistors in series and connected to the plurality of word lines, respectively. In this case, the size of the first group of the memory cells connected to a last word line, of the plurality of word lines, is greater than that of the second group of the memory cells respectively connected to the remaining word lines other than the last word line.  
         [0016]     A non-volatile memory device includes a first select transistor coupled to a bit line; a second select transistor coupled to a common source line; and a plurality of memory cells coupled in series and in an array between the first select transistor and the second select transistor, each memory cell coupled to a word line, the memory cells defining a first memory cell that is provided on one end of the array and having a first memory cell size, a last memory cell that is provided in an opposing end of the array and having a second memory cell size, and remaining memory cells provided between the first and last memory cells, each of the remaining memory cells having a third memory cell size; wherein both of the first and second memory cell sizes are greater than the third memory cell size.  
         [0017]     The first memory cell size is at least 10% greater than the third memory cell size, and the second memory size cell is at least 12% greater than the third memory cell size, so that threshold voltages associated with first and last memory cells are increased to improve the uniformity of a program operation speed of the memory cells and decrease a program threshold distribution.  
         [0018]     A NAND-type flash memory device includes a first select transistor coupled to a bit line; a second select transistor coupled to a common source line; and a plurality of memory cells in an array coupled in series between the first select transistor and the second select transistor, each memory cell coupled to a word line, wherein a first group of the memory cells have a different cell size than that of a second group of the memory cells.  
         [0019]     A non-volatile memory device includes a first select transistor coupled to a bit line; a second select transistor coupled to a common source line; and a plurality of memory cells coupled in series and in an array between the first select transistor and the second select transistor, each memory cell coupled to a word line, the memory cells defining a first memory cell that is provided on one end of the array and having a first memory cell size, a second memory cell that is provided in an opposing end of the array and having a second memory cell size, and remaining memory cells provided between the first and second memory cells, each of the remaining memory cells having a third memory cell size, wherein both of the first and second memory cell sizes are greater than the third memory cell size. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]      FIG. 1  is a layout diagram showing the configuration of a unit cell string of a common NAND-type flash memory device;  
         [0021]      FIG. 2  is a graph showing a threshold voltage depending on each word line in  FIG. 1 ;  
         [0022]      FIG. 3  is a circuit diagram of a NAND-type flash memory device according to the present invention;  
         [0023]      FIGS. 4 and 5  are layout diagrams showing the configuration of a unit cell string shown in  FIG. 3 ; and  
         [0024]      FIGS. 6 and 7  are process sectional views of the unit cell string shown in  FIG. 3 . 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0025]     Embodiments in accordance with the present invention will be described with reference to the accompanying drawings. Since these embodiments are provided for the purpose that those ordinary skilled in the art are able to understand the present invention, they may be modified in various manners so that the scope of the present invention is not limited by the embodiments described later.  
         [0026]      FIG. 3  is an overall cell string structure of a NAND-type flash memory device according to the present invention.  
         [0027]     Referring to  FIG. 3 , the NAND-type flash memory device includes N number of cell strings  10 - 0  to  10 -n in which  32  memory cells form one string.  
         [0028]     A memory cell (e.g., MC 0 ) is controlled by one word line WL 0  and forms one page, i.e.. a group of memory cells. Each of the cell strings  10 - 0  to  10 -n includes a source select transistor SST connected to a common source line CSL, drain select transistors DST connected to bit lines BL 0  to BLn, respectively, and memory cells MC 0  to MCn connected between the source select transistors SST and the drains of the transistors DST. Furthermore, the gate of each of the drain select transistors DST is connected to the drain select line DSL, the gate of the source select transistors SST is connected to the source select line SSL, and the gates of the memory cells MC 0  to MC 31  are connected to first to thirty-first word lines WL 0  to WL 31 .  
         [0029]     In this case, memory cells such as 8, 16, 32, or 64 in number are connected between the source select transistors SST and the drain select transistors DST in series.  
         [0030]      FIGS. 4 and 5  are a layout diagram of one cell string of the cell strings  10 - 0  to  10 -n of the NAND-type flash memory device shown in  FIG. 3  and a process sectional view thereof according to one embodiment of the present invention.  
         [0031]     As shown in  FIGS. 4 and 5 , a distance between the word lines is the same, but the size of the memory cell MC 0  to MC 31  is not the same. The memory cell MC 31  connected to the last word line WL 31  that is the nearest to the drain select line DSL and the memory cell MC 0  connected to the word line WL 0  that is the nearest to the source select line SSL are greater than the remaining memory cells MC 1  to MC 30 . The reason is for improving the program speed of the memory cell MC 0  connected to the first word line WL 0  and the memory cell MC 31  connected to the last word line WL 31 .  
         [0032]     If the size of the memory cell MC 31  connected to the last word line WL 31  that is the nearest to the drain select line DSL and the memory cell MC 0  connected to the word line WL 0  that is the nearest to the source select line SSL is large, the threshold voltage (Vt) of the memory cells MC 0  and MC 31  becomes high. It is thus possible to prevent the program speed of the memory cells MC 0  and MC 31  from relatively becoming slower than that of the remaining memory cells MC 1  to MC 30 .  
         [0033]     According to one embodiment of the present invention, the size of memory cell MC 31  connected to the last word line WL 31  is at least about 12% to 15% greater than the size of the remaining memory cells MC 1  to MC 30 . The size of memory cell MC 0  connected to the first word line WL 0  is at least about 10% to 13% greater than the size of the remaining memory cells MC 1  to MC 30 . In one embodiment, the size of memory cell MC 31  is at least 20% or 25% greater than that of the memory cells MC 1 -MC 30 , and the size of memory cell MC 0  is at least 15% or 20% greater than that of the memory cells MC 1  to MC 30 .  
         [0034]     As described above, if the size of the memory cells MC 0  and MC 31  connected to the first and last word lines WL 0  and WL 31  is greater than that of the remaining memory cells MC 1  to MC 30 , the threshold voltage (Vt) of the memory cells MC 0  and MC 31  becomes high like the remaining memory cells MC 1  to MC 30 . The distribution of the whole program threshold voltage becomes narrow. If the threshold voltage (Vt) of the cells MC 0  and MC 31  increases, the program speed of the memory cells MC 0  and MC 31  increases. Thus, the program speed of these cells MC 0  and MC 31  becomes similar to that of the remaining memory cells MC 1  to MC 30 .  
         [0035]     In  FIGS. 4 and 5 , the word line WL 0  that is the nearest to the source select line SSL is the first word line. If the word line WL 0  adjacent to the source select line SSL is the last word line and the word line WL 31  adjacent to the drain select line DSL is the first word line, the size of memory cell MC 0  connected to the word line WL 0  is at least about 12% to 15% greater than the size of remaining memory cells MC 1  to MC 30 , and the size of memory cell MC 31  connected to the word line WL 31  is at least about 10% to 13% greater than the size of remaining memory cells MC 1  to MC 30 . In one embodiment, the size of memory cell MC 31  is at least 20% or 25% greater than that of the memory cells MC 1 -MC 30 , and the size of memory cell MC 0  is at least 15% or 20% greater than that of the memory cells MC 1  to MC 30 .  
         [0036]      FIGS. 6 and 7  are a layout diagram of one cell string of the cell strings  10 - 0  to  10 -n of the NAND-type flash memory device shown in  FIG. 3  and a process sectional view thereof according to another embodiment of the present invention.  
         [0037]     As shown in  FIGS. 6 and 7 , a distance between the word lines is the same, but the size of the memory cells MC 0  to MCn is not the same. The size of the memory cell MC 31  connected to the word line WL 31  that is the nearest to the drain select line DSL is greater than that of the remaining memory cells MC 0  to MC 30 . The reason is for improving the program speed of the memory cell MC 31  connected to the last word line WL 31 .  
         [0038]     If the size of the memory cell MC 31  connected to the word line WL 31  that is the nearest to the drain select line DSL is large, the threshold voltage (Vt) of the memory cell MC 31  increases. It is thus possible to prevent the program speed of the memory cell MC 31  from becoming relatively slower than that of the remaining memory cells MC 0  to MC 30 .  
         [0039]     According to another embodiment of the present invention, the size of memory cell MC 31  connected to the last word line WL 31  is about 12% to 15% greater than the size of remaining memory cells MC 0  to MC 30 .  
         [0040]     As described above, if the size of the memory cell MC 31  connected to the word line WL 31  that is the nearest to the drain select line DSL is greater than that of the remaining memory cells MC 0  to MC 30 , the threshold voltage (Vt) of the memory cell MC 31  increases and distribution of the whole program threshold voltage becomes narrow. That is, if the threshold voltage of the memory cell MC 31  increases, the program speed of the memory cell MC 31  becomes high. Thus, the program speed of the memory cell MC 31  becomes similar to that of the remaining memory cells MC 0  to MC 30 .  
         [0041]     In  FIGS. 6 and 7 , only the size of the memory cell MC 31  connected to the word line WL 31  that is the nearest to the drain select line DSL is formed greater than that of the remaining memory cells. Even in this case, the distribution of the program threshold voltage can be significantly reduced. This is because the memory cell MC 31  connected to the last word line WL 31  has a threshold voltage much lower than that of the remaining memory cells, as shown in  FIG. 2 .  
         [0042]     In  FIGS. 6 and 7 , the word line WL 31  that is the nearest to the drain select line DSL is the last word line. If the word line WL 31  adjacent to the drain select line DSL is the first word line, the size of memory cell MC 0  connected to the word line WL 0  is about 12% to 15% greater than the size of remaining memory cells MC 1  to MC 31 .  
         [0043]     The present invention is more effective in the case where the number of memory cells in a cell string increases.  
         [0044]     Furthermore, the flash memory device of a single level cell has been described above. It is, however, to be understood that the present invention is more effective in a flash memory device of a multi level cell, which employs a faster program speed and narrower program threshold voltage distribution.  
         [0045]     As described above, according to the present invention, threshold voltages of memory cells connected to first and last word lines adjacent to a source select line and a drain select line are increased. Accordingly, the program operation speed of the whole memory cells can become uniform and program threshold voltage distribution can be narrow.  
         [0046]     Furthermore, threshold voltages of memory cells connected to a last word line adjacent to a source select line or a drain select line is increased. Accordingly, program threshold voltage distribution can become narrow.