Abstract:
A programmable burst sequence counter is described. The counter is capable of counting sequences of binary numbers in a linear burst sequence or interleaved burst sequence starting from a initial binary number that is presented to the inputs of the counter. The programmable burst sequence counter is applicable to the generation of addresses for the storage and retrieval of digital data from memory arrays.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to electronic digital counter circuits and more particularly to programmable parallel counters that will provide a sequence of binary numbers as is necessary for address generation for digital memory applications. 
     2. Description of Related Art 
     Parallel counters are well known in the art and have applications in such areas as the generation of sequential addresses for the accessing and retrieval of digital data from memory arrays. 
     FIG. 1a shows a ripple burst counter. The inverted output Q of a D-type Flip-Flop 30 is connected to the data input of the D-type Flip-Flop 30 configuring the Flip-Flop as a toggling Flip-Flop. The Flip-Flop will change to the opposite state, that is output Q 0  will change from a logic 0 to logic 1 or from a logic 1 to a logic 0, at each rising edge of the clock signal clk 10. 
     The D-type Flip-Flops 40 and 50 are configured with their inverted output Q connected to each of the data inputs D to also form toggling Flip-Flops. The clock clk terminal of D-type Flip-Flop 40 is the inverted output Q of D-type Flip-Flop 30 and the clock input clk of D-type Flip-Flop 50 is the inverted output D-type Flip-Flop 40. 
     The clear signal clr 20 is connected to the clear terminals clr of the D-type Flip-Flops 30, 40, and 50. FIG. 1b shows that when the clear signal clr is brought active 25, the noninverted outputs Q 0 , Q 1 , and Q 2 , are brought to a logic 0 and the inverted outputs Q 0 , Q 1 , and Q 2  are brought to a logic 1. 
     After the clear signal clr 20 becomes inactive 27, the next rising edge 12 of the clock clk 10 cause the output Q 0  35 to change to a logic 1 after a logic delay T. At the rising edge 14 of the clock clk 10 the noninverting output Q 0  35 will now change to a logic 0 and the inverting output Q 0  will change to a logic 1 causing the noninverting output Q 1  45 to change to a logic 1 at a delay time 2T after the rising edge 14 of the clock clk 10. This delay 2T is a result of the delays inherent in the circuitry of the D-type Flip-Flops 30 and 40. At the rising edge 16 of clock clk 10, the noninverting output Q 0  35 again toggles to a logic 1, with the inverted output Q 0  changing to a logic 0. Finally, at the rising edge 18 of clock clk 10. the noninverting outputs Q 0  35, Q 1  45, and Q 2  55 to change to a logic 0. The change in the noninverting output Q 2  55 to a logic 0 happens at the rising edge of the inverting output Q 1  and this change will happen at the delay time 3T, which is, again, the circuit delay of each of the D-type Flip-Flops 30, 40, and 50. 
     FIG. 2a illustrates a technique to prevent the delay of each D-type Flip-Flop from being accumulated with each additional stage as in the ripple burst counter of FIG. 1a. The parallel burst counter of FIG. 2a has a first stage that is a D-type Flip-Flop 130 that is configured as toggling Flip-Flop similar to the first stage 30 of FIG. 1a. The second stage is two D-type Flip-Flops 140 and 142 configured as a toggling Flip-Flop, except that instead of toggling on every clock clk 110 cycle it will toggle on alternate clock clk 110 cycles. The third stage will be formed by D-type Flip-Flops 150, 152, 154, and 156. The D-type Flip-Flops 150, 152, 154, and 156 are configured again as a toggling Flip-Flop that will toggle at every fourth cycle of the clock clk 110. Any number of stages can be added to form a binary number from the outputs Q 0  135, Q 1  145, Q 2  155, . . . . The number of D-type Flip-Flops in each stage will be 2 n  where n is the stage number of the digit of the binary number. 
     As is shown in FIG. 2b, each output Q 0  135, Q 1  145, and Q 2  155 is now delayed from the clock by the uniform amount T. This is a result of each D-type Flip-Flop being timed by the same clock clk 110. Thus when the clear signal clr 120 is active 125 all of the noninverting output Q 0  135, Q 1  145, Q 2  155, . . . are brought to a logic 0. The clear signal clr 120 becomes inactive 127 and at each rising edge 112, 114, 116, and 118 of the clock, the noninverting outputs Q 0  135, Q 1  145, and Q 2  155 of the counter assume the next binary number of the sequence. 
     The only sequence of binary numbers that can be generated from the counters of FIG. 1 and FIG. 2 are as shown in Table 
     
                       TABLE 1______________________________________     Clock          Q.sub.2     Q.sub.1                            Q.sub.0______________________________________Clear       0      0           0   0       1      0           0   1       2      0           1   0       3      0           1   1       4      1           0   0       5      1           0   1       6      1           1   0       7      1           1   1______________________________________ 
    
     This pattern will be repeated for subsequent clock cycles clk 10 of FIG. 1a or 110 of FIG. 2a. 
     U.S. Pat. No. 4,360,742 (Freyman) teaches a technique for a parallel binary counter and rate divider where a series of toggle Flip-Flops are configured such that the frequency output can be a sub-multiple of the input clocking frequency. 
     U.S. Pat. No. 4,891,827 (Slater) shows a loadable ripple counter wherein an initial binary number can be loaded to the counter and the subsequent binary counts will placed at the outputs at each timing signal. 
     In memory address generation, a series of sequential addresses are often needed to rapidly retrieve or store data to a memory array. There are two types of sequential address formats that are commonly used, the interleaved burst address and the linear burst address. 
     Table 2 is the sequence of binary numbers for the interleaved burst address format. 
     
                       TABLE 2______________________________________      A 1:0!            A 1:0!    A 1:0!  A 1:0!______________________________________Start Address        00      01        10    112nd Address  01      00        11    103d Address   10      11        00    014th Address  11      10        01    00______________________________________ 
    
     Table 3 is the sequence of binary numbers for the linear burst address format. 
     
                       TABLE 3______________________________________      A 1:0!            A 1:0!    A 1:0!  A 1:0!______________________________________Start Address        00      01        10    112nd Address  01      10        11    003d Address   10      11        00    014th Address  11      00        01    10______________________________________ 
    
     The Tables 2 and 3 show only a two digit binary address sequence for reference. Any number of digits may used with these formats. 
     The counters as shown in the prior art are capable of generation of sequences of the linear bust address only and can not be easily programmed to any other sequence of binary numbers. 
     SUMMARY OF THE INVENTION 
     An object of this invention is the creation of a programmable digital sequence counter for the generation of a series of memory addresses. Another object of this invention is providing both an interleaved burst sequence and a linear burst sequence of binary numbers dependent on the programming of the programmable digital sequence counter. Furthermore, still another object of this invention is the counting of the sequence starting from an initial input binary number. 
     To accomplish these and other objects a programmable digital sequence counter has a counting means that will provide a sequence of linear burst or interleaved burst binary numbers to a plurality of outputs. An external address means provides the initial input binary from which the counting means will begin. A burst sequence means determines which type of binary number sequence the counting means will provide. A clocking signal will synchronize the timing of the counting means while an advancing means will instruct the counting means to determine each subsequent binary number. The clearing means will bring all the output to an initial binary number that is dependent on the external address means. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1a is a schematic diagram of a ripple burst counter of prior art. 
     FIG. 1b is a timing diagram of the ripple burst counter of prior art. 
     FIG. 2a is a schematic diagram of a parallel burst counter of prior art. 
     FIG. 2b is a timing diagram of the parallel burst counter of prior art. 
     FIG. 3 is a schematic diagram of the Burst Counter Circuit of this invention. 
     FIG. 4 is a schematic diagram of a two input/two AND/OR Invert utilized in this invention 
     FIG. 5 is a schematic diagram of a D-type Flip-Flop utilized in this invention. 
     FIG. 6 is a schematic diagram of a D-type Flip-Flop utilized in this invention. 
     FIG. 7 is a timing diagram of the burst counter of this invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 3 shows the preferred embodiment of this invention. A parallel burst counter consists of D-type Flip-Flops 210, 220, and 230 and logic circuit 240 and 250. D-type Flip-Flop 210 is configured as a toggling Flip-Flop. While the clear signal clr is 0, the output Q 0 , Q 1  will be 0 at the rising edge of the clock signal clk. At each successive change of the clock signal clk from a logic 0 to a logic 1 while the advance signal ADV is at a logic 1, the output Q 0  will change state from the previous state that is from a logic 1 to a logic 0 or from a logic 0 to a logic 1. 
     The D-type Flip-Flops 220 and 230, and logic circuits 240 and 250 are configured so that the output Q 1  will change from a logic 0 to a logic 1 or from a logic 1 to a logic 0 at every alternate change of the clock signal clk while the advance signal ADV at a logic 1. The terminals A and B, that are connected to the logic circuits 240 and 250, determine the sequence of counts from the parallel burst counter 200. Table 4 shows the sequence of counts that possible from the outputs Q 0  and Q 1  of the parallel burst counter 200. 
     
                       TABLE 4______________________________________     A   B        clr   clk    Q.sub.1                                   Q.sub.0______________________________________COUNT       1     0        0   ↑                                 0   0SEQUENCE 1  1     0        1   ↑                                 0   1       1     0        1   ↑                                 1   0       1     0        1   ↑                                 1   1COUNT       0     1        0   ↑                                 0   0SEQUENCE 2  0     1        1   ↑                                 1   1       0     1        1   ↑                                 1   0       0     1        1   ↑                                 0   1______________________________________ 
    
     The burst control circuit 290 determines the values of the signals A and B and consequently the type of count from the parallel burst counter. If the signal LBO is at a logic 0, the count is count sequence 1 from Table 4 and if the signal LBO is at a logic 1 and the signal AOM is at a logic 0 the count is again count sequence 1 from Table 4. Finally if the signal LBO is at a logic 1 and the signal AOM is at a logic 1 the count is now count sequence 2 from Table 4. 
     The programming input and data output section 300 consists of D-type Flip-Flops 310 and 320 and exclusive-or&#39;s (XOR) 330 and 340. The D-type Flip-Flop 310 has the first external address A 0  X connected to the data input terminal D. At the reception of the clear signal clr, the output has the value of the first external address A 0  X. This value is will be maintained until there is another clear signal clr. The output Q of the D-type Flip-Flop 310 form the signal AOM that is connected to the burst control circuit 290. The D-type Flip-Flop 320 has the second external address A 1  X connected to the data input D. At the reception of the clear signal clr, the output Q of the D-type Flip-Flop 320 assumes a logical value of the second external address A 1  X. Again, this value will remain until another clear signal clr is received. 
     The output of the D-type Flip-Flop 310 and the output Q 0  of the parallel burst counter 200 are connected to the input of XOR 330 and the output Q of the D-type Flip-Flop 320 and the output Q 1  of the parallel burst counter 200 are connected to the inputs of XOR 340. The outputs of the XOR&#39;s 330 and 340 form the outputs A 0  I and A 1  I of the programmable digital sequence counter. 
     The signal LBO determines the type of sequence that will be present at the outputs A 0  I and A 1  I. If the signal LBO is a logic 1, the outputs A 0  I and A 1  I are linear burst sequences and if the signal LBO is at a logic 0, the output A 0  I and A 1  are interleaved burst sequences of binary numbers. 
     Table 5 shows the logical values for points within the circuit of FIG. 3 and for the output A 0  I and A 1  I for all combinations of input signals. 
     
                       TABLE 5______________________________________LBO  A.sub.1 X       A.sub.0 X              AOM  clr  clk ADV  Q.sub.1                                      Q.sub.0                                          A.sub.1 I                                               A.sub.0 I______________________________________INTERLEAVED0    0      0      0    0    ↑                            X    0    0   0    0                   1    ↑                            1    0    1   0    1                   1    ↑                            1    1    0   1    0                   1    ↑                            1    1    1   1    10    0      1      0    0    ↑                            X    0    0   0    1                   1    ↑                            1    0    1   0    0                   1    ↑                            1    1    0   1    1                   1    ↑                            1    1    1   1    00    1      0      1    0    ↑                            X    0    0   1    0                   1    ↑                            1    0    1   1    1                   1    ↑                            1    1    0   0    0                   1    ↑                            1    1    1   0    10    1      1      1    0    ↑                            X    0    0   1    1                   1    ↑                            1    0    1   1    0                   1    ↑                            1    1    0   0    1                   1    ↑                            1    1    1   0    0LINEAR1    0      0      0    0    ↑                            X    0    0   0    0                   1    ↑                            1    0    1   0    1                   1    ↑                            1    1    0   1    0                   1    ↑                            1    1    1   1    11    0      1      1    0    ↑                            X    0    0   0    1                   1    ↑                            1    1    1   1    0                   1    ↑                            1    1    0   1    1                   1    ↑                            1    0    1   0    01    1      0      0    0    ↑                            X    0    0   1    0                   1    ↑                            1    0    1   1    1                   1    ↑                            1    1    0   0    0                   1    ↑                            1    1    1   0    11    1      1      1    0    ↑                            X    0    0   1    1                   1    ↑                            1    1    1   0    0                   1    ↑                            1    1    0   0    1                   1    ↑                            1    0    1   1    0______________________________________ 
    
     FIG. 4 is a circuit schematic for the logic circuits 240 and 250 of FIG. 3. The P-type Metal Oxide Semiconductor Transistors (P-MOST) M 3  and M 4  with the N-type Metal Oxide Semiconductor Transistors (N-MOST) M 7  and M 5  form a first complementary MOS NAND gate, and P-MOST M 1  and M 2  with N-MOST M 6  and M 8  form a second complementary MOS NAND gate. The first and second NAND gates are connected in parallel to form an OR gate. The output of the logic circuit is at the point INB. The logic function implemented in the circuit of FIG. 4 is: ##EQU1## where table 6 shows the truth table for the logic circuit formed by FIG. 4. 
     
                       TABLE 6______________________________________D          Q     CE          CEB  INB______________________________________X          0     0           1    1X          1     0           1    0X          0     0           1    1X          1     0           1    00          X     1           0    10          X     1           0    11          X     1           0    01          X     1           0    0______________________________________ X = DON&#39;T CARE 
    
     A schematic of D-type Flip-Flops 310 and 320 of FIG. 3 is shown in FIG. 5. The logic signal CEB is connected to the input of inverter 400 and CEB input of logic circuit 420. The output of inverter 400 is connected to the input CE of logic circuit 420. The input signal AIN is connected to the inverter 410. The output of inverter 410 is connected to the input D of the logic circuit 420. 
     The NAND gates 440 and 430 have their outputs X 2  and X 2  cross coupled their inputs to form a Set-Reset (SR) Flip-Flop where the Reset terminal is connected to the INB output of logic circuit 420 and the set terminal is connected to the of the clock signal clk and the output X 1  of the NAND gate 450. 
     The NAND gates 450 and 460 also have their outputs X 1  and X 1  cross-coupled to each others inputs to form a second SR Flip-Flop. The reset terminal is connected to the clock signal clk and the set signal is connected to the output X 2  of the first SR Flip-Flop. 
     The NAND gates 470 and 480 also have their outputs Q and Q B  cross-coupled to each others inputs to form a third SR Flip-Flop. The reset terminal is the output X 2  of NAND gate 440 and the set terminal is the output X 1  of NAND gate 450. 
     The Table 6 is a Truth Table for the outputs Q and Q B  for all combination of the inputs. 
     
                       TABLE 6______________________________________AIN        CEB    CLK          Q   Q.sub.B______________________________________0          0      ↑      0   11          0      ↑      1   00          1      ↑      UC  UC1          1      ↑      UC  UC______________________________________ UC = Unchanged 
    
     FIG. 6 is a schematic diagram of the D-type Flip-Flops 220 and 230 of FIG. 3. The input signal CE is connected to the input of inverter 500 and the input CE of logic circuit 520. The output of the inverter 500 is connected to the input CEB of the logic circuit 520. The input signal DATA is connected to the input D of the logic circuit of 520 and the Q input of the logic circuit 520 is the output Q of the NAND gate 570. 
     The NAND gates 530 and 540 have their outputs X 2  and X 2  cross coupled to each others inputs to form an SR Flip-Flop where the Reset terminal is determined by the NAND combination of INB output of logic circuit 520 and the clear input signal clr. The set is determined by the NAND combination of the output X 1  of the NAND gate 550 and the input clock signal clk. 
     A second SR Flip-Flop is formed by NAND gates 550 and 560 with their output X 1  and X 1  cross-coupled to each other inputs. The reset terminal is the input clock signal clk and the set terminal is the output X 2  of the NAND gate 530. 
     A third SR Flip-Flop is formed by NAND gates 570 and 580 with their outputs Q and Q B  cross-coupled to each others inputs. The set terminal is the output X 1  of the second SR Flip-Flop and the reset terminal is the output X 2  of the first Flip-Flop. The outputs of the D-type Flip-Flop (220 or 230 of FIG. 3) is the output Q and Q B  of the third SR Flip-Flop. 
     The Table 7 is a Truth Table for the outputs Q and Q B  for all combination of the inputs. 
     
                       TABLE 7______________________________________DATA     CE        CLK    CLR      Q   Q.sub.B______________________________________1        1         ↑                     1        1   00        1         ↑                     1        0   1X        X         ↑                     0        0   1X        0         ↑                     1        UC  UC______________________________________ X = DON&#39;T CARE UC = UNCHANGED 
    
     A timing diagram of the programmable burst counter of FIG. 3 is shown in FIG. 7. An external address A --  external 900 is presented to the programmable burst counter of FIG. 3 prior to the rising edge 610 of the clock 600 and the clear signal clr 700 is brought to a logic 0 710. At the rising edge of the clock pulse 610 and while the clear signal clr 700 is at a logic 0 719, the initial address A --  external 900 is transferred to the first internal address 1010 A --  internal 1000 after the completion of the rising edge 610 of clock clk 600. At each successive rising edge of the clock clk 620, 630, and 640 and with each advance ADV 800 pulse 820, 830, and 840, the internal address A --  internal 1000 will increment to the second address 1020, then the third address 1030, and then the fourth address 1040. At the rising edge of the 650 clock clk 600 and while the advance ADV 850 is a logical 1, the counter will re-initialize to the first address 1050 and continue this sequence. 
     The hashed areas 705, 805, and 905 are times when the respective inputs are not examined and may assume any value of a logic 1 or a logic 0. The cross-hashed area 1005 are times when the output internal address A --  internal 1000 is at an indeterminate state. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.