Abstract:
A fully differential operational amplifier is provided having a common-mode feedback portion which accurately sets the common-mode output voltage at a predetermined value. The feedback portion utilizes a pair of parallel transistors which source a combined current which is used to provide a common-mode control voltage relative to a reference common-mode current. The common-mode control voltage controls load devices of the operational amplifier in a manner such that a differential output voltage remains centered about the predetermined common-mode output voltage.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     Application Ser. No. 06/728,628 entitled, &#34;A Clocked Gain Stage Having Differential Inputs And Outputs&#34;, filed simultaneously herewith by Joe W. Peterson. 
     TECHINCAL FIELD 
     This invention relates generally to amplifiers, and more particularly, to operational amplifiers having differential inputs and differential outputs. 
     BACKGROUND ART 
     A general class of amplifiers includes fully differential operational amplifiers having two inputs and two outputs. Fully differential operational amplifiers have the advantage of providing good power supply rejection. Operational amplifiers with differential outputs have a maximum dynamic range of input voltage only when the common-mode D.C. output voltage is at the midpoint value of the power supply voltages. A fully differential operational amplifier which functions to maintain the D.C. common-mode output voltage at an optimum value for dynamic output voltage range is taught by Roger A. Whatley in U.S. patent application Ser. No. 682,873. However, such differential operational amplifiers typically have several low frequency poles which must be compensated in most applications to prevent oscillation. Further, a fully differential operational amplifier with fewer transistors may be desirable in applications where size is an extreme limitation. 
     BRIEF DESCRIPTION OF THE INVENTION 
     Accordingly, an object of the present invention is to provide an improved fully differential operational amplifier. 
     Another object of the present invention is to provide an improved fully differential operational amplifier which uses D.C. common-mode feedback. 
     Yet another object of the present invention is to provide an improved differential output operational amplifier circuit having an output voltage with a maximized dynamic range. 
     A further object of the present invention is to provide an improved differential output operational amplifier circuit which minimizes circuitry. 
     In carrying out the above and other objects of the present invention, there is provided, in one form, a fully differential operational amplifier generally comprising first current source means for providing a first constant source current. A first differential input means is coupled to the first current source means for selectively receiving a first input voltage and providing a first output voltage in response thereto. A second differential input means is coupled to the current source means, for selectively receiving a second input voltage and providing a second output voltage in response thereto. First and second load means are respectively coupled to the first and second differential input means, for respectively sinking first and second differential currents in response to a common-mode control voltage. Common-mode feedback means are provided for maintaining a common-mode output voltage at a predetermined value. First and second parallel-connected transistors of the feedback means provide a first bias current, and a third transistor of the feedback means provides a second bias current. Output means coupled to the first, second and third transistors provide the common-mode control voltage in proportion to the first and second bias currents. These and other objects, features and advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates in schematic form a fully differential operational amplifier in accordance with the present invention; 
     FIG. 2(A) illustrates in schematic form another embodiment of the present invention; and 
     FIG. 2(B) illustrates in graphical form timing signals associated with the circuit of FIG. 2(A). 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Shown in FIG. 1 is a fully differential operational amplifier 10 illustrating one form of the present invention. A current source 11 has a first terminal connected to a power supply voltage V DD  and a second terminal connected to a source of both P-channel transistors 12 and 13. A gate of transistor 12 provides a positive input terminal for receiving a positive input voltage, and a gate of transistor 13 provides a negative input terminal for receiving a negative input voltage. A drain of transistor 12 is connected to a drain of an N-channel transistor 14 via a first output terminal 16 for providing a negative output voltage referenced to a predetermined voltage such as analog ground, V AG . Transistor 14 has a source connected to a second supply voltage potential such as earth ground potential and has a gate. A drain of transistor 13 is connected to a drain of an N-channel transistor 17 via a second output terminal 18 which provides a positive output voltage referenced to analog ground. A source of transistor 17 is connected to earth ground. A gate of transistor 17 is connected to the gate of transistor 14 at a common-mode output node 19. A current source 20 has a first terminal coupled to power supply voltage V DD  and a second terminal connected to a source of both P-channel transistors 21 and 22. A gate of transistor 21 is connected to output terminal 16, and a gate of transistor 22 is connected to output terminal 18. Each of transistors 21 and 22 has a drain connected together at a node 23. An N-channel transistor 25 has both a drain and a gate connected to node 23 and has a source connected to earth ground. A P-channel transistor 26 has a source connected to the second terminal of current source 20, a gate coupled to analog ground and a drain connected to a drain of an N-channel transistor 27 via node 19. A gate of transistor 27 is connected to the gate of transistor 25 at node 23, and a source of transistor 27 is connected to earth ground. A capacitor 28 has a first electrode connected to node 23 and a second electrode connected to node 19. In a preferred form, the source of each of N-channel transistors 14, 17, 25 and 27 is connected to the substrate thereof to minimize conventional Body effects. While specific N-channel and P-channel MOS devices are shown, it should be obvious that operational amplifier 10 may be implemented by completely reversing the processing techniques (e.g. P-channel to N-channel) or by using other types of transistors. 
     In operation, assume that the positive and negative inputs of operational amplifier 10 receive substantially equal input voltages. Therefore, transistors 12 and 13, if sized with substantially equal physical dimensions, will each conduct approximately one-half of the current supplied by current source 11. Transistors 14 and 17 function as output load devices. When the input voltages are approximately equal, transistors 14 and 17 conduct approximately equal currents and have equal gate-to-source voltages. Therefore, the output voltages at terminals 16 and 18 are approximately equal. 
     In the illustrated form, transistors 21, 22, 25, 26 and 27 and current source 20 function as a common-mode feedback amplifier 30. Transistors 12, 13, 14 and 17 function as a main amplifier portion of operational amplifier 10. A negative feedback path between node 19 and output nodes 16 and 18 via transistors 14 and 17, respectively, places common-mode feedback amplifier 30 in a closed loop configuration which forces the output voltages to be balanced. Assuming that the output voltages are substantially equal, transistors 21 and 22 of feedback amplifier 30 are biased so that the gate-to-source voltage of each of transistors 21 and 22 is the same. Transistors 21, 22 and 26 are proportionately sized with respect to each other so that transistor 26 conducts a known amount of current with respect to the combination of transistors 21 and 22. Transistor 26 is biased by a predetermined common-mode output voltage, V AG . Therefore, the bias voltages applied to transistors 21 and 22 determine the amount of common-mode feedback voltage applied to the main amplifier comprising transistors 12, 13, 14 and 17. In a preferred form, each of transistors 21 and 22 is sized approximately one-half the size of transistor 26. Therefore, when transistors 21 and 22 are biased with equal voltages, transistors 21 and 22 which are connected in series with transistor 25 effectively appear to be one transistor coupled in parallel with transistor 26. In a balanced output voltage condition with the assumed transistor geometries, transistor 26 conducts one-half of the current supplied by current source 20 in response to the common-mode output voltage V AG , and transistors 21 and 22 equally conduct one-half of the current from current source 20. The voltage potential at common-mode output node 19 adjusts accordingly so that the current through transistor 26 equals the sum of the currents through transistors 21 and 22. Regardless of the absolute value of the equal voltages applied to the positive and negative inputs, common-mode amplifier 30 will provide a bias voltage at node 19 which will force the output voltages at nodes 16 and 18 to V AG . Therefore, the common-mode output voltage is established with balanced input voltages and a differential output voltage of zero volts. 
     Whenever a differential input voltage is applied to the gates of transistors 12 and 13, the output voltages at nodes 16 and 18 will reflect an output voltage which is equal to the product of the input voltage differential and the gain of amplifier 10. The gain of amplifier 10 is determined by transistors 12, 13, 14 and 17 and current source 11 in a conventional manner. This circuit operation has assumed that operational amplifier 10 has remained in a linear region of operation. In other words, no output signal clipping has occurred due to a saturated output condition of operation. Additionally, common-mode feedback amplifier 30 must remain in the linear operating region. The differential summing function provided by transistors 21 and 22 both with respect to the negative feedback function and with respect to the overall functional operation of amplifier 10 must be linear. By adjusting the width and length of the control electrode regions of transistors 21 and 22, the second derivative of the ratio of the current and gate-to-source voltage of each of transistors 21 and 22 is minimized in a conventional manner to provide substantially linear operation. 
     When the input voltage at the gate of transistor 12 is increased by an amount, say ΔV, a differential voltage equal to the product of the gain of the primary amplifier and ΔV will appear across the output nodes 16 and 18. Common-mode feedback amplifier 30 functions to provide negative feedback to transistors 14 and 17 and make the average value of the differential output voltage equal to the predetermined value of V AG . The common-mode output voltage will remain equal to V AG  as long as the sum of the currents through transistors 21 and 22 is equal to the current through transistor 26. Common-mode feedback amplifier 30 cannot change the amount of voltage differential appearing across the output nodes 16 and 18, but functions to vary the absolute values of the output voltages in response to the input voltage differential in order to maintain the common-mode output voltage at a fixed value. 
     In particular, if the output voltages at the gates of transistors 21 and 22 both increase, transistors 21 and 22 conduct less and transistor 26 must conduct more. As a result, the voltage potential at node 19 rises slightly making transistors 14 and 17 conduct more. The net effect of the action of transistors 14 and 17 is to lower the voltage potential at output nodes 16 and 18. The reduced voltage potential causes transistors 21 and 22 to conduct more current until a balance of current is established between transistors 21 and 22 and transistor 26. As a result, the voltage differential at nodes 16 and 18 is not changed but the differential is translated so that the difference is centered about V AG . An exactly opposite but analogous circuit operation occurs if the voltage potential at the gates of transistors 21 and 22 decreases. Because the closed-loop common-mode feedback of operational amplifier 10 has two dominant frequency poles, capacitor 28 may be provided to insure that operational amplifier 10 does not oscillate. However, no frequency compensating capacitor is needed for the main amplifier portion of operational amplifier 10 because the main amplifier portion only has one dominant frequency pole. 
     Shown in FIG. 2(A) is another embodiment of the present invention illustrating an autozeroed fully differential A.C. coupled amplifier 10&#39; with common-mode feedback. Circuit elements which are common to FIG. 1 are illustrated in FIG. 2(A) by the same number. An N-channel transistor 41 has a drain connected to the drain of transistor 27, a gate coupled to a control signal labeled .0. 3  and a source connected to node 19. A capacitor 42 has a first electrode connected to node 19 and a second electrode connected to earth ground. An N-channel transistor 45 has a drain coupled to the common-mode reference voltage V AG , a gate coupled to a control signal labeled .0. 2 , and a source connected to both a first electrode of a capacitor 47 and a gate of transistor 12. A second electrode of capacitor 47 forms the positive input terminal. An N-channel transistor 48 has a drain connected to the first electrode of capacitor 47, a gate coupled to a control signal labeled .0. 1 , and a source connected to output terminal 16 for providing a negative output. An N-channel transistor 52 has a drain coupled to the common-mode reference voltage V AG , a gate coupled to control signal .0. 2 , and a source connected to both a first electrode of a capacitor 53 and the gate of transistor 13. A drain of an N-channel transistor 54 is connected to the gate of transistor 13. A second electrode of capacitor 53 forms the negative input terminal. A gate of transistor 54 is coupled to control signal .0. 1 , and a source of transistor 54 is connected to output node 18 for providing a positive output. An example of control signals .0. 1 , .0. 2  and .0. 3  is illustrated in FIG. 2(B). 
     In operation, operational amplifier 10&#39; provides a fully differential input and output structure which is selectively autozeroed to compensate for inherent offset voltage errors. During an autozero period, control signals .0. 1  and .0. 2  make transistors 45, 48, 52 and 54 conductive which selectively connects the negative input and positive output and the positive input and negative output to the known reference voltage V AG . After a predetermined amount of time, transistors 45 and 52 become nonconductive and switch 41 is made conductive. This switching action disconnects V AG  from the unity gain configured operational amplifier and charges a common-mode feedback control voltage onto capacitor 42 via transistor 41. The common-mode control voltage at node 19 represents the amount of negative feedback bias voltage required to maintain the common-mode output voltage of operational amplifier 10&#39; at V AG . After the common-mode control voltage has been charged onto capacitor 42 with amplifier 10&#39; in unity gain, common-mode feedback amplifier 30 is disconnected from the main amplifier portion of operational amplifier 10&#39; via transistor 41 in response to signal .0. 3 . Transistors 48 and 54 respectively disconnect the negative and positive output terminals from the positive and negative input terminals, respectively, in response to control signal .0. 1 . Operational amplifier 10&#39; is now ready for valid circuit operation. Capacitors 47 and 53 function as A.C. coupling capacitors to the positive and negative inputs, respectively. No frequency compensating capacitor is needed for the main amplifier portion of amplifier 10&#39; because the main amplifier portion only has one dominant frequency pole. 
     In the illustrated form, transistor 41 disconnects the common-mode voltage portion from the main amplifier of operational amplifier 10&#39; because for some circuit operations such as a voltage comparison operation, operational amplifier 10&#39; may become saturated. Once saturated, the value of the common-mode feedback voltage may not be accurate since transistors 21, 26 and 22 may not respond in a linear manner. Therefore, the stored correct voltage on capacitor 42 insures that a predetermined common-mode output voltage of V AG  is maintained. 
     By now it should be apparent that a fully differential operational amplifier with common-mode D.C. feedback has been provided. The present invention provides good power supply noise rejection characteristic of fully differential operational amplifier structures. Accurate control of the output common-mode voltage has been provided in an operational amplifier structure having only one dominant frequency pole in the amplifier portion. Therefore, frequency compensating capacitors are only required in the common-mode feedback portion of the amplifier structure. In one form, the present invention may be implemented as an autozeroed operational amplifier in which a common-mode feedback control voltage is sampled onto a capacitor. Therefore, a plurality of circuit operations may be performed without the risk of saturating the common-mode voltage control portion of the amplifier and negatively affecting the accuracy of the common-mode output voltage. 
     While an embodiment has been disclosed using certain assumed parameters and specified transistor proportions, it should be understood that certain obvious modifications to the circuit or the given parameters will become apparent to those skilled in the art, and the scope of the invention should be limited only by the scope of the claims appended hereto.