Abstract:
A trans-impedance amplifier (TIA) for a light-receiving circuit is disclosed where the TIA reduces the power consumption as suppressing the degradation of the signal quality in high frequency regions. The TIA comprises a primary core, a dummy core, and a differential amplifier that receives each output of two cores in the differential mode. Two cores have an arrangement substantially same to each other except that the power consumption thereof is smaller in the dummy core. Because the output impedance of two cores becomes substantially equal, the scattering parameter of the common mode to the differential mode at the output of the primary core becomes small enough.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a trans-impedance amplifier (hereafter denoted as TIA), in particular, the invention relates to a TIA for converting an optical signal into an electrical signal. 
         [0003]    2. Related Prior Arts 
         [0004]    The United States Patent, U.S. Pat. No. 7,868,701, has disclosed a TIA for the optical communication system, in which the TIA includes two TIA core circuits and an output buffer. The first TIA core circuit converts a photocurrent into a voltage signal. The output buffer provides an input to receive the output of the first TIA core circuit. The second TIA core circuit, which has a configuration same as those of the first TIA core circuit, is coupled with a reference terminal of the output buffer. 
       SUMMARY OF THE INVENTION 
       [0005]    One aspect of the present invention relates to a TIA that receives a photocurrent generated in a photodiode and outputs a differential electrical signal corresponding to the photocurrent. The TIA comprises a primary core, a dummy core, and a differential amplifier. The primary core converts the photocurrent into a voltage signal. The dummy, which has an arrangement substantially same with those of the primary core, generates a reference voltage. The differential amplifier, which receives the voltage signal from the primary core and the reference voltage from the dummy core in the differential mode, outputs a differential signal between to voltage signals. A feature of the TIA according to the present invention, the dummy core has the output impedance substantially equal to the output impedance of the primary core in a high frequency region but greater the output impedance of the primary core in a low frequency region. 
         [0006]    The primary and dummy cores may provide an output stage including a transistor with an emitter grounded arrangement and a load element connected to the collector of the transistor for providing an output of respective cores. In the present invention, the output impedance of the load element of the dummy core may become substantially equal to the output impedance of the load element of the primary core in the high frequency region but greater than the output impedance of the primary core at the low frequency region. The load element of the dummy core may include a series circuit of a first resistor and a circuit element of a second resistor and a capacitor connected in parallel to the second resistor. The first resistor may have resistance substantially equal to the impedance of the load element of the primary core and the second resistor may have resistance which is r−1 times greater than the impedance of the load element of the primary core. The capacitor may have capacitance able to be regarded as a short circuit in the high frequency region and to be regarded as an open circuit in the low frequency region. The emitter resistor of the dummy core may have resistance which is r times greater than the resistance of the emitter resistor of the primary circuit. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0007]    Non-limiting and non-exhaustive embodiments of the present invention will be described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various figures unless otherwise specified: 
           [0008]      FIG. 1  is a block diagram of a TIA according to an embodiment of the present invention; 
           [0009]      FIG. 2  is a circuit diagram of a primary core shown in  FIG. 1 ; 
           [0010]      FIG. 3  is a circuit diagram of a dummy core shown in  FIG. 1 ; 
           [0011]      FIG. 4  compares the output impedance of the primary core with the output impedance of the dummy core; 
           [0012]      FIG. 5  shows scattering parameters for the mode conversion from the common to the differential at the output terminal of the primary core; and 
           [0013]      FIG. 6  explains respective scattering parameters of the outputs in the differential mode. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0014]    Next, some preferred embodiments according to the present invention will be described as referring to accompanying drawings. In the description of the drawings, the same numerals or symbols will refer to the same elements without overlapping explanations. 
         [0015]      FIG. 1  is a block diagram of a trans-impedance amplifier (hereafter denoted as TIA)  3  of the present embodiment. The TIA  3 , which includes a primary core  5 , a dummy core  7 , a differential amplifier  9  and an output buffer  11 , may receive a photocurrent with frequency components over 10 GHz from the photodiode (hereafter denoted as PD)  1 . The photocurrent output from the anode of the PD  1  may be input in the input terminal  3   a , and led to the primary core  5 . The primary core  5 , which is set between the input  3   a  and the differential amplifier  9 , may convert the photocurrent into a voltage signal to be processed by the differential amplifier  9 . The dummy core  7 , which is coupled with the differential amplifier in another input thereof different from that coupled with the primary core  5 , may output a reference to the differential amplifier  9 . The differential amplifier  9  may amplify a difference between the voltage signal coming from the primary core  5  and the reference from the dummy core  7 , and may output the difference between them to the output buffer  11 . The output buffer  11  may output the difference coming from the differential amplifier  9  to the outside with a designed magnitude. The output buffer  11  may show adequate output impedance. 
         [0016]      FIG. 2  is a circuit diagram of the primary core  5  in an exemplary configuration thereof. The primary core  5  provides an input terminal  5   a , an output terminal  5   b , an impedance element  5   c , a first transistor  5   d , a load resistor  5   f , a second transistor  5   g , a load element  5   i , an emitter resistor  5   j  and two power supplies,  5   e  and  5   h . Two transistors,  5   d  and  5   g , are the npn-type bipolar transistor. The base of the first transistor  5   d , which is called as the control terminal, is connected to the input terminal  5   a  and the impedance element  5   c , the collector thereof, which is called as the current terminal, is connected to the load resistor  5   f  and the base of the second transistor  5   g , and the emitter is grounded. The first transistor  5   d  is powered from the power supply  5   e  through the load resistor  5   f , thus the current flows from the power supply  5   e  to the ground along the arrow S 1  in  FIG. 2 . 
         [0017]    The second transistor  5   g  directly receives in the base thereof the output of the first transistor  5   d . The collector of the second transistor  5   g  is connected with the output terminal  5   b  and the load element  5   i , and the emitter thereof is connected to the impedance element  5   c  and the emitter resistor  5   j . The load element  5   i  may include a resistor  51 . The second transistor  5   g  is powered by the power supply  5   h  through the load element  5   i  and grounded through the emitter resistor  5   j . The current flows from the power supply  5   h  to the ground along the arrow S 2  in  FIG. 2 . The impedance element  5   c  is set between the base of the first transistor  5   d  and the emitter of the second transistor  5   g , which operates as a trans-impedance. 
         [0018]    The primary core  5  shown in  FIG. 2   may  operate, assuming the impedance of the load element  5   i  and that of the emitter resistor are substantially equal to the others, as a current-to-voltage converter where the input impedance Zin and the current-to-conversion ratio Zt thereof are given by: 
         [0000]        Z in= R   f /(1 +gm×R ), and 
         [0000]        Zt˜R   f , 
         [0000]    where R f , gm, and R are the resistance of the impedance element  5   c , the trans-conductance of the first transistor  5   g , the resistance of the load resistor  5   f.    
         [0019]    Receiving an optical signal with a level “1”, which causes the PD  1  to generate the photocurrent, the photocurrent flows in the impedance element  5   c  and the emitter resistor  5   j , which rises the base level of the first transistor  5   d  and the increases the current flowing therein. The increased current flowing in the first transistor  5   d  lowers the collector level thereof, which is equal to the base input level of the second transistor  5   g . Thus, the current passing through the second transistor  5   g  decreases, which also decreases the voltage drop across the load element  5   i  and raises the output level which is appeared in the output terminal  5   b . Thus, the primary core  5  may output the voltage with the “1” level corresponding to the optical signal with the level “1”. 
         [0020]    On the other hand, when the PD  1  receives the optical signal with a level “0”, which is the dark state, and the photocurrent generated in the PD  1  decreases, the base level of the first transistor  5   d  decreases because a voltage drop across the impedance element  5   c  and the emitter resistor  5   j  due to the photocurrent diminishes. Then, the current flowing in the first transistor  4   d  decreases and the collector level thereof increases, which increases the current flowing in the second transistor  5   g  and decreases the collector level thereof because a voltage drop across the load element  5   i  increases. Thus, the output of the primary core  5 , which appears in the output terminal  5   b , is set to the “0” level corresponding to the optical signal with the “0” level. 
         [0021]      FIG. 3  is a circuit diagram of the dummy core  7  in an exemplary configuration thereof. The dummy core  7  includes an input terminal  7   a , an output terminal  7   b , an impedance element  7   c , a third and forth transistors,  7   d  and  7   g , a load resistor  7   f , a load element  7   i , an emitter resistor  7   j  and two power supplies,  7   e  and  7   h . Two transistors,  7   d  and  7   g , are the npn-type bipolar transistor. The base of the third transistor  7   d  is connected to the input terminal  7   a  and the impedance element  7   c ; the collector thereof is connected to the load resistor  7   f  and the base of the fourth transistor  7   g ; and the emitter is grounded. The third transistor  7   d  is powered from the power supply  7   e  through the load resistor  7   f , thus the current flows from the power supply  5   e  to the ground along the arrow S 3  in  FIG. 3 . The input terminal  7   a  is directly coupled with the other input  3   d  of the TIA and connected to the cathode of the PD  1  through a coupling capacitor  1   d.    
         [0022]    The fourth transistor  7   g  directly receives in the base thereof the output of the third transistor  7   d . The collector of the third transistor  7   g  is connected to the output terminal  7   b  and the load element  7   i ; while the emitter thereof is connected to the impedance element  7   c  and the emitter resistor  7   j . The fourth transistor  7   g  is powered by the power supply  7   h  through the load element  7   i  and grounded through the emitter resistor  7   j . The current flows from the power supply  7   h  to the ground along the arrow S 4  in  FIG. 3 . The impedance element  7   c  is set between the base of the first transistor  7   d  and the emitter of the second transistor  7   g , which operates as the trans-impedance. 
         [0023]    The load element  7   i  may include a resistor  71  and a parallel circuit of another resistor  73  and a capacitor  75 . The resistor  71  is connected to the parallel circuit in series, that is, one end of the resistor  71  is connected to the collector of the fourth transistor  7   g , the other thereof is commonly connected to the resistor  73  and the capacitor  75 . The other end of the resistor  73  and that of the capacitor  75  are commonly connected to the power supply  7   h.    
         [0024]    The circuit elements in the primary core  5  and those in the dummy core  7  are substantially same to the others. That is, two impedance elements,  5   c  and  7   c ; two transistors,  5   d  and  7   d ; and two transistors,  5   g  and  7   g , have a characteristic same to the other, respectively. 
         [0025]    However, the embodiment shown in  FIGS. 2 and 3  according to the present embodiment has a feature that the load resistor  7   f  and the emitter resistor  7   j  in the dummy core  7  has the resistance thereof which is r times greater than those of the load resistor  5   f  and the emitter resistor  5   j  in the primary core  5 , respectively, where r is greater than unity. Moreover, the resistor  71  and the resistor  51  each has the characteristic including the resistance thereof substantially same to the other; the resistor  73  has the resistance which is r−1 times greater than that of the resistor  51 ; and the total resistance of two resistors,  71  and  73 , is r times greater than the resistance of the resistor  51 . 
         [0026]    The output impedance of the primary core  5 , which corresponds to the impedance viewed from the output terminal  5   b  toward the inside of the primary core  5 , is given by a parallel circuit of the load element  5   i  with equivalent resistance of the collector of the second transistor  5   g . The latter resistance, that is, the resistance of the collector, may be regarded as substantially greater that the resistance of the former because the second transistor  5   g  has the emitter grounded arrangement. Accordingly, the output impedance of the primary core  5  becomes substantially equal to the impedance of the load element  5   i . Similarly, the output impedance of the dummy core  7  may be regarded as the impedance of the load element  7   i.    
         [0027]    However, the load element  7   i  shows frequency dependence; that is, in a relatively higher frequency region where the capacitor  75  may be regarded as short-circuited, the impedance of the load element  7   i  may be substantially equal to the resistance of the resistor  71 , which is set to be equal to the resistance of the resistor  51  in the primary core  5 ; accordingly, the output impedance of the dummy core  7  becomes substantially equal to the output impedance of the primary core  5  in the high frequencies. While, in a relative lower frequency where the capacitor  75  may be regarded as an open-circuited, the impedance of the load element  7   i  is given by a series circuit of two resistors,  71  and  73 , which becomes r times greater than the resistance of the load element  5   i  in the primary circuit  5 . 
         [0028]      FIG. 4  compares the output impedance of the primary core  5  with that of the dummy core  7 , where the vertical axis shows the output impedance Zout and the horizontal axis corresponds to the frequency. In  FIG. 4 , G 1  is the output impedance of the dummy core  7  with the capacitor  75 , G 2  is the output impedance of the dummy core  7  when the capacitor  75  is omitted, and G 3  shows the output impedance of the primary core. In the analyses of  FIG. 4 , resistors  51 ,  71  and  73 , are assumed to have resistance of 100Ω.  FIG. 4  explicitly shows that the output impedance of the dummy core  7  becomes substantially equal to that of the primary core  5  around 10 GHz when the capacitor  75  exists, but the behavior G 2  that omits the capacitor  75  shows still higher impedance even around 10 GHz. 
         [0029]    The mode conversion of two cores,  5  and  7 , will be analyzed by using the mix-mode scattering parameters. Considering the conversion from the common mode to the differential mode between two outputs,  5   b  and  7   b ;  FIG. 5  shows the differential mode output Sdc converted from portions of the common mode signal appeared in respective output terminals,  5   b  and  7   b , which are reflected by the common mod signal appeared in the downstream of two cores,  5  and  7 . The symbol Sdc means the S-parameter converted from the common mode to the differential mode, and Sdc is given by: 
         [0000]        Sdc   22 =( S   22   +S   23   −S   32   −S   33 )/2, 
         [0000]    where S 22 , S 23 , S 32 , and S 33  are given by elements indicated in  FIG. 6 . In  FIG. 5 , the behavior G 4  corresponds to the dummy core  7  without the capacitor  75  in the load element  7   i , while, the other behavior G 5  corresponds to the result with the capacitor  71 . 
         [0030]    According to  FIG. 5 , the former case G 4  without the capacitor  75  detects a half, (1/√2) 2 =−3 dB, of a common mode signal as the differential signal independent of a intrinsic signal coming from the PD  1  at the output terminal  5   b  around 20 GHz. While for the latter case G 5  with the capacitor  75 , only 1/10 (−20 dB) of the common mode signal may be detected as the differential mode signal. Thus, the dummy core  7  with the capacitor  75  in the load element  7   i  may improve the conversion effect from the common mode to the differential mode at the output terminal M. Although  FIG. 5  assumes that the capacitance is 0.5 pF, another capacitor with greater capacitance may show the same or more improved result. In these analysis described above, the differential amplifier  9  and the output buffer  11  show less contribution to the mode conversion by two cores,  5  and  7 , because these circuits,  9  and  11 , receive signals complementary to each other and output differential signals. 
         [0031]    The TIA  3  according to the present embodiment provides the dummy core  7  with the load element  7   i  that includes a resistor  71  and a parallel circuit of a resistor  73  and a capacitor, which is connected in series to the former resistor  71 . In a high frequency where the capacitor  75  may be regarded as a short-circuited, the impedance of the load element  7   i  becomes substantially equal to that of the load element  5   i  in the primary core, which may improve the conversion characteristic from the common mode to the differential mode at the output terminal  5   b . On the other hand in a lower frequency where the capacitor  75  may be regarded as an open-circuit, the impedance of the load element  7   i  becomes r times greater than that of the load element  5   i  in the primary core  5 , which may effectively reduce the power consumption of the dummy core  7 . Thus, the TIA  3  according to the present embodiment may improve the power consumption as suppressing degradation in a high frequency performance. 
         [0032]    In the foregoing detailed description, the method and apparatus of the present invention have been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present invention. The present specification and figures are accordingly to be regarded as illustrative rather than restrictive