Abstract:
An adaptive equalizer provides different degrees of high frequency boosts to the received signal, while retaining a relatively constant phase shift for each boost setting. The response of the equalizer is controlled by a control circuit (e.g., a digital signal processor) to compensate for the high frequency signal attenuation primarily caused by the signal path. For example, the signal path may include a telephone line between the communications system (e.g., a modem) and the central office. The dynamic response of the equalizer is selected based upon the characteristics of the signal path which the receive signal travels along. The equalizer may receive single ended or doubled ended signals. Advantageously, the equalizer conditions the received signal to ensure efficient utilization of the dynamic range of the ADC located in the receive circuit path. The equalizer is suitable for on-chip implementation, resulting in lower cost and power consumption.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to communications, and in particular to an adaptive analog equalizer. 
     Due to the widespread popularity of the World Wide Web, internet traffic is at an all time high and rapidly increasing. The resulting congestion is taking its toll on users and telephone companies alike. Users are often frustrated by the length of time it takes to download complex graphics and videos. For example, a ten megabyte video clip which is the equivalent of a four minute movie, takes approximately ninety-three minutes using a 14.4 kilobyte modem and forty-six minutes using a 28.8 kilobit modem. 
     In addition, lengthy data transmissions are tying up telephone company switches that were designed to handle brief telephone calls. Broadband modems, and in particular asymmetric digital subscriber line (ADSL) modems are an emerging technology that promises to dramatically increase the ability to transfer data over conventional telephone lines. Significantly, ADSL modems allow data transfers at rates over two hundred times faster than current modems, and over ninety times faster than ISDN lines. 
     ADSL was originally conceived of as a technology for delivering interactive multimedia services, such as video on demand over existing telephone networks. However, it is internet access that is currently driving the demand for ADSL. Unlike other high speed data transmission technologies such as ISDN, ADSL requires no massive rewiring or other changes to a telephone company&#39;s local exchange or central office. Notably, ADSL modems use the existing telephone infrastructure, including the so-called “last mile” of the network, which is the leg from the central office to a subscriber site (e.g., a home or office) that uses a twisted pair of copper lines. Although it is often referred to as the “last mile”, the leg from the central office to the subscriber site is typically about 12,000-18,000 feet long. 
     The bandwidth of a conventional copper twisted pair telephone line is approximately 1 MHz. However, conventional analog signals that carry voice over these lines operate in a 4 kHz bandwidth. Advantageously, ADSL takes advantage of the remaining portion of the 1 MHz bandwidth. Specifically, ADSL technology effectively subdivides the 1 MHz bandwidth of the copper twisted pair line into three information channels: i) a high speed downstream channel, ii) a medium speed duplex (upstream/downstream) channel, and iii) a conventional voice channel. Downstream refers to transmissions from the telephone network to the ADSL modem located at a subscriber site, while upstream is the route from the subscriber site to the telephone network. This multichannel approach enables subscribers to access the internet, order a video for viewing and send a facsimile or talk on the telephone all at the same time. 
     FIG. 1 illustrates a communication system  10  that employs ADSL technology. The system  10  includes a subscriber site  12 , which includes a phone  14 , a facsimile machine  16  and a personal computer or computer network  18 . The subscriber site  12  receives a twisted pair of copper telephone lines  20  that connect the subscriber site with a telephone central office  22 . The run length of the telephone line  20  between the subscriber site and the central office  22  is typically 12,000 feet and it could reach 18,000 feet. A POTS splitter  24  located at the subscriber site  12  is connected to the telephone line  20  and couples the telephone line to an ADSL modem  26  and to the phone  14  and facsimile machine  16 . 
     Central office  22  includes a POTS splitter  30  that is operatively connected to an ADSL modem rack  32  and to a public telephone switch  34 . As known, the public telephone switch  34  communicates over a public switch telephone network  36 . The ADSL modem rack  32  also communicates over the public switch telephone network and is connected via an internet backbone  38  to various devices including a video server  40 , a video conferencing server  42  and a World Wide Web server  44 . 
     FIG. 2 is a functional block diagram illustration of the ADSL modem  26  and the POTs splitter  24 . The modem  26  includes a hybrid circuit  50  that couples a transmit circuit  52  and a receive circuit  54  to the telephone line. 
     The transmit circuit  52  includes a digital signal processor (DSP)  56  that provides a digitized transmit signal on a line  58  to a digital-to-analog converter (DAC)  60 . The resultant analog signal is input to a low pass filter (LPF)  62  and a filtered transmit signal is provided on a line  64  to the hybrid circuit  50 . 
     The receive circuit  54  receives a signal on a line  66  and includes a high pass filter  68 , a programmable gain amplifier  70 , a low pass filter  72 , an analog-to-digital converter (ADC)  74  and a DSP  76  which together process the signal on the line  66  in a known manner. 
     The POTs splitter  24  includes a high pass filter  78  and a LPF  80 . The LPF  80  has a cut-off frequency set at approximately 4 kHz in order to allow the voice band signal to pass onto the line  28 . The HPF  78  filters signals that are transmitted and received by the modem. Therefore, the cut-off frequency of the HPF  78  can be set at no higher than about 30 kHz to ensure that signals from the transmit circuit  52  pass relatively unattenuated through the POTS splitter. In addition, the hybrid  50  is typically used to terminate the HPF  78  in this embodiment. 
     Attenuation caused by the twisted pair is not constant over frequency spectrum. That is, the telephone line attenuates high frequency components within the received signal spectrum more than lower frequency components. To compensate for signal losses due to the cable/wire, a programmable gain amplifier (PGA) is typically placed in front of the analog-to-digital converter (ADC). The function of the PGA is to amplify the received signal and to increase/maximize the dynamic range of ADC. However, the PGA gain is flat over the frequency band. Therefore, after amplification, the low frequency components will still have a much higher amplitude than the high frequency components. As a result, the dynamic range of ADC is often limited by the low frequency signals. This leads to a situation where the dynamic range of ADC needs to be greater in order to achieve required signal-to-noise ratio (SNR) for system performance. 
     The amount of signal gain to be provided is further complicated by the fact that signal attenuation increases with the length of the copper wire. Since the distance between the subscriber site and the central office varies considerably (e.g., generally between 12 and 18 kilo-feet), modems at different subscriber sites will see various levels of high frequency signal attenuation. Moreover, signal attenuation is also a function of temperature and copper conditions that are not easily controlled. Hence, modems may experience different degrees of copper loss over time. 
     Therefore, there is a need for an adaptive equalizer that compensates for the attenuation of the high frequency components, while leaving the lower frequency components relatively unchanged. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide an adaptive equalizer to compensate for signal attenuation at high frequencies in the receive path of a broadband communications device. 
     Briefly, according to the present invention, a broadband communications system includes a receive circuit path and a hybrid circuit. The hybrid circuit provides a receive signal to the receive circuit path that comprises an adaptive equalizer circuit, which conditions the received signal and provides a compensated received signal that is processed by the receive path circuit. In a preferred embodiment, the broadband communications system includes a modem. 
     The adaptive equalizer is an adaptive analog filter that provides different degrees of high frequency boosts to the received signal, while retaining a relatively constant phase shift for each boost setting. The response of the equalizer is controlled by a control circuit (e.g., a digital signal processor) to compensate for the high frequency signal attenuation primarily caused by the signal path. For example, the signal path may include a telephone line between the communications system (e.g., a modem) and the central office. The dynamic response of the equalizer is selected based upon the characteristics of the signal path which the receive signal travels along. 
     The equalizer may receive single ended or doubled ended signals. 
     Advantageously, the equalizer conditions the received signal to ensure efficient utilization of the dynamic range of the ADC located in the receive circuit path. The equalizer is suitable for on-chip implementation, resulting in lower cost and power consumption. 
     These and other objects, features and advantages of the present invention will become apparent in light of the following detailed description of preferred embodiments thereof, as illustrated in the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a communication system  10  that employs DSL technology; 
     FIG. 2 is a functional block diagram illustration of a DSL modem  26  and POTS splitter  24 ; 
     FIG. 3 illustrates a functional block diagram of a modem receive circuit according to the present invention; 
     FIG. 4 illustrates a schematic diagram of an embodiment of the adaptive equalizer; 
     FIG. 5 illustrates a Laplacian block diagram of the adaptive equalizer; 
     FIG. 6 illustrates some typical magnitude responses of the analog adaptive equalizer; 
     FIG. 7 is a table that identifies the component values for the five equalizerconfigurations that were used to generate the plots illustrated in FIG. 6; 
     FIG. 8 illustrates a plot of phase shift versus frequency for each of the equalizer configurations specified in FIG. 7; and 
     FIG. 9 illustrates an alternative embodiment adaptive equalizer that is suitable for use with double ended/balanced signals. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention shall be discussed in the context of use in a modem. However, one of ordinary skill will appreciate that the equalizer of the present invention is not limited to use in a modem. Indeed, it may be used in virtually any communications system desiring adaptive equalization. 
     FIG. 3 illustrates a functional block diagram of a broadband modem receive circuit path  90  that employs an adaptive equalizer  92  according to the present invention. The receive circuit path  90  is substantially similar to path  54  in the modem  26  illustrated in FIG. 2, with the principal exception of the addition of the adaptive equalizer  92 . In addition, to select the desired response from the adaptive equalizer  92 , a DSP  94  provides control signals on a line  96  to the equalizer. In a preferred embodiment, the receive circuit path (with the exception of the HPF  68  and the DSP  76 ) is located on an integrated circuit. Alternatively, the receive circuit and/or the equalizer may be constructed from discrete components. 
     FIG. 4 illustrates a schematic diagram of an embodiment of the adaptive equalizer  92 . The equalizer has the topology of a biquadratic filter. The equalizer  92  receives a filtered signal on a line  104  from the HPF  68  (FIG.  3 ). The equalizer includes a capacitor network  93  comprising a plurality of parallel capacitors C 1 -C n    106 - 108  that are each input to an associated one of a plurality of switches  110 - 112 . Each of the switches  110 - 112  is individually controllable in response to control signals on the line  96 . Significantly, by opening and closing 5 various combinations of the switches  110 - 112 , the resultant capacitance from the network  93  can be set to a desired value C k . The significance of this adaptive/programmable feature shall be discussed in detail hereinbelow. 
     The equalizer  92  also includes a first operational amplifier  116  and a second operational amplifier  118  connected in cascade with negative feedback around each of the amplifiers. Specifically, the first operational amplifier  116  includes a negative feedback path having a resistor R 3    120  and a capacitor C 1    122  arranged in parallel. The second operational amplifier  118  includes a capacitor C 2    124  that is connected between the output and the negative input of the second amplifier  118 . 
     The equalizer also comprises a feedback path from the output of the second amplifier  118  to the negative input of the first amplifier  116 . The feedback path includes a unity gain inverting amplifier  126  and a series resistor R 4    128 . The virtual grounds available at the inputs of the two operational amplifiers  116 ,  118  allow signals to be summed directly. 
     The equalizer  92  also includes a feedforward path  130  from the input signal on the line  104  to the negative input of the second amplifier  118 . This path  130  comprises a unity gain inverting amplifier  132  and a series resistor R 1    134 . Significantly, the unity gain inverting amplifier  132  on this feedforward path moves the location of the zeros from the jω-axis onto the real axis. A resistor R 2    136  is connected between the output of the first amplifier  116  and the negative input of the second amplifier  118 . The equalizer output V 0  is provided on a line  138  from the output of the first amplifier  116 . 
     FIG. 5 illustrates a Laplacian block diagram  140  of the equalizer schematically illustrated in FIG.  4 . Two negative integrators  141 ,  142  are connected in cascade in an overall feedback loop. These integrators represent the two Miller integrators illustrated in FIG.  4 . That is, referring to FIGS. 4 and 5, opamp  116  and capacitor  122  form the basis of integrator  141 , while opamp  118  and capacitor  124  form the basis of integrator  142 . Summation operators  143 ,  144  represent the signal summation that occurs at the negative inputs of the opamps  116 ,  118  (FIG.  4 ), respectively. The 1/Q gain feedback path around the first integrator  141  represents the function of the damping resistor R 3    120  (FIG.  4 ). The scalar operator K  145  (FIG. 5) represents the dc gain of the equalizer, which corresponds to the ratio of resistor R 2    136  to resistor R 1    134  (FIG.  4 ). Functional block  148  represents the programmable capacitor network  93  (FIG.  4 ), which realizes the zeroes of the equalizer transfer function. Significantly, the programmable capacitor network  93  (FIG. 4) is responsible for the programmable high-frequency boost by changing the location of the zeroes (i.e., ω z ). Referring to FIG. 5, note that when ω z  is pushed to infinity, the feedforward path to the first integrator is effectively eliminated, and the Laplacian block diagram  140  simplifies to a conventional lowpass filter. 
     The transfer function H(s) for the equalizer can be derived from FIG.  5  and written as follows:                H        (   s   )       =       K   ·       (       ω   0       ω   z       )     2            (         s   2     -     ω   z   2           s   2     +       (       ω   0     Q     )        s     +     ω   0   2         )               (     EQ   .              1     )                                
     The filter poles, Q, K and zeroes can be written in terms of circuit components (FIG. 4) as:                ω   o     =     ±       1       R   2          C   2          R   4          C   1                     (EQ.  2a)               Q   =           C   1          R   3   2           C   2          R   2          R   4                   (EQ.  2b)               K   =     -       R   2       R   1                 (EQ.  2c)                 ω   z     =       1       R   1          R   4          C   2          C   k                   (EQ.  2d)                                
     EQs. 2a-2d illustrate that there is a high degree of freedom to realize a particular set of biquadratic filter characteristics (namely, the ω 0 , Q, and K) with different values for the R&#39;s and C&#39;s. For example, in one embodiment one may set R 2 =R 1 =R a  so that the magnitude of the equalizer DC gain is unity. In addition, one may assign R 3 =R 4 =R b , and C 1 =C 2 =C. One of ordinary skill in the art will recognize that these values represent one of many different configurations for the analog adaptive equalizer. A designer familiar with the art can easily come up with numerous different configurations of the analog adaptive equalizer to achieve the particular design requirements. Therefore, with these substitutions EQs. 2a-2d can be rewritten as:                ω   o     =       1       R   a          R   b          C   2                       Q   =         R   b       R   a                     K   =     -   1                   ω   z     =       1       R   a          R   b          CC   k                                        
     From EQ. 1, the magnitude of the equalizer gain at high-frequency (i.e., at s goes to infinity) is determined by the square of the ratio between the pole and the zero, which is            (       ω   0       ω   z       )     2     .                          
     Therefore, the equalizer high-frequency can be programmed by varying the zero location (assuming fixed poles—for reasons to be discussed shortly). This is achieved by configuring the capacitor network  93  (FIG. 4) to provide the appropriate capacitance. 
     When the distance of the channel is short, high frequency boost is not required because the high frequency attenuation is relatively small. Therefore, the equalizer is configured as a lowpass filter by configuring the capacitor network  93  (FIG. 4) to place the zeros at a very high frequency. Then, the transfer function H(s) set forth in EQ. 1 simplifies to a second order low pass filter, which can be expressed as:                H        (   s   )       =     -       ω   0   2         s   2     +       (       ω   0     Q     )        s     +     ω   0   2                   (EQ.  1a)                                
     As an example, FIG. 6 illustrates a plot of gain (in dB) versus frequency (Hz) of the typical equalizer output signal on the line  138  (FIG. 4) for five different equalizer configurations. Gain is plotted along a vertical axis and frequency is plotted along a horizontal axis on a log scale. The plots were generated by computer simulation. In a first plot, gain versus frequency is plotted along a line  150 . As shown, the gain of the system is about 0 dB until approximately 100 kHz where the gain increases to approximately 22 dB at around 2 MHz. The gain plotted along the line  150  begins rolling off at approximately 30 MHz due to parasitics and the finite bandwidth of the amplifier. If less gain is required then the DSP  94  (FIG. 3) configures the equalizer  92  to provide one of the other selectable responses plotted along lines  151 - 154 . 
     Referring to FIGS. 4 and 6, to configure the equalizer  92 , the DSP  94  (FIG. 3) provides the command signal on the line  96 . The command signal sets the position of the individually controllable switches  110 - 112 . C k  is equal to the sum of the capacitance&#39;s for the switches that are closed. For example, if only switch  110  is closed, then C k  is equal to the value of C 1    106 . If switches  110  and  111  are closed, and the remaining switches are open, then C k  is equal to the value (C 1 +C 2 ) since the capacitors sum in parallel. Similarly, if switches  111  and  112  are closed while switch  110  is open, then C k  will be equal to the value of (C 2 +C n ). It is contemplated that the capacitive network may also include series capacitors that can be short circuited by closing a switch (not shown) that is parallel to the capacitor. 
     The capacitive network  93  (FIG. 4) provides the largest capacitance (i.e., C k ) to obtain maximum boost (i.e., smallest ω z ). To decrease the system boost, the value of C k  is reduced. For a low pass response, all the switches  110 - 112  are opened, which moves the zeroes ω z  to infinity. It should be noted that since the two zeroes of the second order equalizer  92  are realized by the capacitive network  93  (FIG.  4 ), the zeroes will lie on the real axis and be symmetrical about the imaginary axis (i.e., jω-axis). Therefore, the phase response of the equalizer remains substantially the same for all boost settings. 
     FIG. 7 is a table that identifies the component values for the five equalizer configurations that were used to generate the plots illustrated in FIG.  6 . Referring to FIGS. 6 and 7, the plot on the line  150  (FIG. 6) is associated with the equalizer configuration specified on a first  160  line on the table. Specifically, R a =42.43 kohms, R b =21.21 kohms, C=5.424 pF and C k =65.09 pF. This results in ω z =0.28 MHz, ω 0 =0.98 MHz, Q=0.707 and a gain of about 20.4 dB at 1.1 MHz. The plot on the line  151  (FIG. 6) is associated with the equalizer configuration specified on a second line  161  of the table. Specifically, R a , R b  and C remain unchanged, while the capacitive network  93  (FIG. 4) is set so C k =32.54 pF. This results in ω z =0.40 MHz, ω 0 =0.98 MHz, Q=0.707 and a gain of about 14.7 dB at 1.1 MHz. Similarly, the plots on lines  152 - 154  (FIG. 6) are associated with the equalizer configurations specified on lines  162 - 164  respectively, of the table set forth in FIG.  7 . The Q of the equalizer is selected to be 0.707 for a flat response. Referring to FIG. 7, for each gain reduction of approximately 6 dB at 1.1 MHz, the value of C k  is cut in half. 
     FIG. 8 illustrates a plot of phase shift versus frequency for each of the equalizer configurations specified in FIG.  7 . Phase shift is plotted along a vertical axis and frequency is plotted along a horizontal axis. Notably, the phase shift versus frequency characteristics are almost identical for the various equalizer configurations within the operational spectrum of the receive circuit path (i.e., several kHz to about 1.1 MHz). That is, phase shift as a function of frequency is plotted along a line  170  for the equalizer configurations in FIG. 7. A key to adaptive equalization of the present invention is that the phase shift versus frequency needs to be relatively the same for each of the equalizer configurations. Specifically, phase shift as a function of frequency should track for the various adaptive settings. To ensure this relationship, the zeros of the equalizer should appear as mirror-images around the imaginary axis. Therefore, their contributions to the phase are mutually cancelled. In other words, the phase will be determined by the pole locations of the equalizer. Significantly, the equalizer  92  provides the ability to select one of a plurality of high-frequency boosts by adjusting the zero locations only (while the poles are fixed). 
     FIG. 9 illustrates an alternative embodiment equalizer  180  that is suitable for use with double ended signals. One of ordinary skill will recognize that by interchanging the opamp output terminals, signal inversion is readily obtained, thus allowing the two inverting amplifiers  132 ,  126  in FIG. 4 to be removed from this alternative embodiment. This fully balanced equalizer  180  has improved linearity and immunity from substrate noise in contrast to the single ended embodiment illustrated in FIG.  3 . 
     The equalizer embodiments illustrated in FIGS. 4 and 9 are based on a biquadratic transfer function having two complex poles and two real zeroes. Significantly, if the poles are fixed, the zeros are shifted (by controlling capacitance C k ) to provide the desired high frequency boost, or to provide a lowpass response. In addition, since the zeroes are symmetrical around the jω-axis, the same phase shift versus frequency relationship can be maintained regardless of the selected equalizer configuration (i.e., boost settings). However, one of ordinary skill in the art will recognize that the present invention is not limited to a second order equalizer. It is contemplated that the equalizer may be a higher order at the expense to additional circuitry. In addition, although the analog adaptive equalizer has been described in the context of being used in a modem, it is contemplated that the adaptive equalizer may be employed in essentially any communication system where it is desirable to employ an adaptive equalizer, which ensures that the phase shift versus frequency remains the same within a predetermined frequency range for various equalizer boost settings. 
     Although the present invention has been shown and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.