Abstract:
A three-point converter with NPC diodes disposed between bridge halves and a center tap of an intermediate circuit is proposed. A decoupling network is provided for the upper bridge half, a first input of which decoupling network is connected to a positive pole of the intermediate circuit and a first output of the decoupling network is connected to a positive pole of the three-point converter. Furthermore, provision is made of a further decoupling network for the lower bridge half, a first input of the further decoupling network is connected to a negative pole of the intermediate circuit and a first output of the further decoupling network is connected to a negative pole of the three-point converter. The remaining inputs of both of the decoupling networks are connected to the center tap of the intermediate circuit. The remaining outputs of both of the decoupling networks are connected via the NPC diodes to the upper and lower bridge halves. A commutation voltage for the main switches of the upper and lower bridge halves is decoupled from a halved intermediate circuit voltage (V dc /2) independently of one another by the decoupling networks.

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The invention relates to a three-point converter and to a method of operating the three-point converter. 
     The invention is associated with the field of three-point converters that are fed by voltage intermediate circuits. Converters of this type are used both in electrical drives and in filter and compensation installations involving high power levels. The protective circuit proposed is, in particular, a possibility for the realization of high-power converters in the medium-voltage range. 
     A topology of a neutral point clamped (NPC) three-point converter has already been generally known for a long time. It is also used industrially in the field of high power levels. IGBTs, GTO thyristors or integrated gate commutated thyristors (IGCT) are used as main switches in this case. 
     When GTO thyristors are used, it is necessary to limit the rate of current rise di/dt during turn-on and also the rate of voltage rise du/dt during turn-off across the switches. 
     When IGCTs are used, it is necessary to limit only the rate of current rise di/dt. For this purpose, switching load-relief networks, so-called snubbers, are disposed in the circuit; they ensure the abovementioned limitation and thereby generally reduce switching losses in the switches. 
     A number of examples of such configurations are described in Suh, J.-H. et al.: “A New Snubber Circuit for High Efficiency and Overvoltage Limitation in Three Level GTO Inverters”, IEEE Trans., On Industrial Electronics, Vol. 44, No. 2, April 1997. The limiting of the rates of voltage and current rise is achieved, in principle, by capacitors connected in parallel with the switches and, respectively, inductors connected in series as well as additional active and/or passive components which are always necessary. When GTO thyristors are used, the protective circuits must generally be implemented separately for each GTO or for each phase. The outlay on active and passive components is therefore high. Both in the case of conventional RCD snubbers and in the case of the improved variant proposed, the entire energy stored in the snubber is converted into heat via resistors. Problems which arise when conventional RCD snubbers are used, such as overvoltages across the GTO thyristors (caused by the series inductors) and unequal blocking voltage distribution between the GTOs, can only be minimized, but not solved, even with the improved snubber mentioned above. 
     An example of an industrially manufactured snubber is described in Komulainen, R.: “Inverter Protected in Respect of the Rates of Increase of Current and Voltage”, U.S. Pat. No. 4,566,051, published on Jan. 21, 1986. In this circuit, the entire energy (snubber energy) stored in the load-relief inductors and load-relief capacitors is fed back into the DC voltage intermediate circuit. However, this requires a high outlay on circuitry. 
     A further disadvantage of all known switching load-relief networks for three-point converters is that the switching losses due to the high commutation voltage (half the intermediate circuit voltage in the three-point converter) can be reduced only to a limited extent and with a high outlay on components. 
     For the topology of two-point converters, in addition to the diverse snubber circuits which are likewise used, principles are also known in which low-loss switching is achieved by a commutation voltage of almost zero. For this purpose, an electrical network for temporarily decoupling the commutation voltage from the intermediate circuit voltage during the switching operations is incorporated between the intermediate circuit capacitor and the bridge paths of the converter, as described e.g. in Salama, S, Tadros, Y.: “Quasi Resonant 3-Phase IGBT Inverter”, IEEE-PESC Conference Records, 1995. In this case, the commutation voltage can oscillate almost to zero by a resonant operation. 
     To summarize, it may be ascertained that the snubber circuits used to date in conventional NPC three-point converters ensure only a limited reduction of switching losses in the main switches on account of the functional principle of the snubber circuits. In many snubbers, the snubber energy is not fed back into the DC voltage intermediate circuit but rather is converted into a heat loss in the switches and the protective circuit. Furthermore, the outlay on components and the costs of conventional snubbers are considerable. 
     SUMMARY OF THE INVENTION 
     It is accordingly an object of the invention to provide a three-point converter and a method for its operation which overcomes the above-mentioned disadvantages of the prior art methods and devices of this general type, which realizes very low-loss switching of the main switches in the three-point converter. 
     With the foregoing and other objects in view there is provided, in accordance with the invention, a three-point converter, including: 
     a main positive pole and a main negative pole; an upper bridge half having main switches and a lower bridge half having main switches; 
     an immediate circuit having a center tap, a positive pole, a negative pole, and an intermediate circuit voltage; 
     upper neutral point clamped diodes (NPC diodes) disposed between and connecting the upper bridge half to the center tap and lower NPC diodes disposed between and connecting the lower bridge half to the center tap; 
     a first decoupling network connected to the upper bridge half and having inputs and outputs, one of the inputs of the first decoupling network is connected to the positive pole of the intermediate circuit and one of the outputs of the first decoupling network is connected to the main positive pole, remaining inputs of the inputs of the first decoupling network are connected to the center tap, remaining outputs of the outputs of the first decoupling network are connected via the upper NPC diodes to the upper bridge half; 
     a second decoupling network is connected to the lower bridge half and has inputs and outputs, one of the inputs of the second decoupling network is connected to the negative pole of the intermediate circuit and one of the outputs of the second decoupling network is connected to the main negative pole, remaining inputs of the inputs of the second decoupling network are connected to the center tap, remaining outputs of the outputs of the second decoupling network are connected via the lower NPC diodes to the lower upper bridge half; and 
     a commutation voltage for the main switches of the upper bridge half and the main switches of the lower bridge half are decoupled from a halved intermediate circuit voltage independently of one another by the first decoupling network and the second decoupling network. 
     The particular advantages that can be obtained by the invention are that the abovementioned disadvantages, for example generation of heat loss, high outlay on components, and high costs of the snubbers for three-point converters are avoided. The invention includes the use of the decoupling of the commutation voltage from the intermediate circuit voltage by two separate protective circuits in the form of the decoupling networks for the upper and lower bridge halves in the three-point converter in a separate manner. The two decoupling networks operate completely independently of one another. They ensure a commutation voltage of almost zero for their respective bridge half, while half the intermediate circuit voltage is present at the other bridge half. Overall, the circuit has a moderate outlay on active and passive components. The limiting of the rate of current rise di/dt and the rate of voltage rise du/dt is reliably ensured. In addition, the circuit affords protection for the case where the main switches are short-circuited, by limiting the rate of rise of the short-circuit current. 
     As already noted, independent commutation in the upper bridge half and in the lower bridge half is possible. This also advantageously permits direct commutations from the upper to the lower bridge half “positive voltage to negative voltage” and back. 
     Other features which are considered as characteristic for the invention are set forth in the appended claims. 
     Although the invention is illustrated and described herein as embodied in a three-point converter and a method for its operation, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. 
    
    
     The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagrammatic, circuit diagram of a three-phase circuit of a three-point converter; 
     FIG. 2 is a circuit diagram of decoupling networks; 
     FIG. 3 is a circuit diagram of a single-phase circuit for elucidating commutations; 
     FIGS. 4 a-k  are circuit diagrams of the commutation from T 11  to D 15 ; 
     FIGS. 5 a-k  are circuit diagrams of the commutation from D 15  and T 12  to D 14  and D 13 ; 
     FIGS. 6 a-m  are circuit diagrams of the commutation from D 14  and D 13  to D 15  and T 12 ; 
     FIGS. 7 a-m  are circuit diagrams of the commutation from D 15  to T 11 ; 
     FIGS. 8 a-k  are circuit diagrams of the commutation from T 11  and T 12  to D 14  and D 13 ; and 
     FIGS. 9 a-m  are circuit diagrams of the commutation from D 14  and D 13  to T 11  and T 12 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In all the figures of the drawing, sub-features and integral parts that correspond to one another bear the same reference symbol in each case. Referring now to the figures of the drawing in detail and first, particularly, to FIG. 1 thereof, there is shown a three-phase basic circuit diagram of the three-point converter. A three-phase bridge circuit contains main switches T 11 , T 12  and inverse diodes D 11 , D 12  (inverse diodes=reverse-connected parallel diodes) of an upper bridge half of a first phase, main switches T 13 , T 14  and inverse diodes D 13 , D 14  of a lower bridge half of the first phase, main switches T 21 , T 22  and inverse diodes D 21 , D 22  of the upper bridge half of a second phase, main switches T 23 , T 24  and inverse diodes D 23 , D 24  of the lower bridge half of the second phase, main switches T 31 , T 32  and inverse diodes D 31 , D 32  of the upper bridge half of a third phase and also main switches T 33 , T 34  and inverse diodes D 33 , D 34  of the lower bridge half of the third phase. The main switch and inverse diode circuits are connected to loads on an output side, the load inductors are designated by L 1 , L 2 , L 3 . 
     On an input side, the three-phase bridge circuit is connected to a decoupling network  1  of the upper bridge half and a decoupling network  2  of the lower bridge half. The decoupling network  1  is connected to a positive pole of an intermediate circuit and to a center tap  3  of the intermediate circuit. The decoupling network  2  is connected to a negative pole of the intermediate circuit and to the center tap  3 . 
     The upper bridge half of the first phase is connected via a neutral point clamped (NPC) diode D 15  (NPC diode=diode of the center tap) to the center tap  3  of two intermediate circuit capacitors C d /2 connected in series on the input side. The lower bridge half of the first phase is connected via an NPC diode D 16  to the center tap  3 . The upper bridge half of the second phase is connected via an NPC diode D 25  to the center tap  3  of two intermediate circuit capacitors C d /2 connected in series on the input side. The lower bridge half of the second phase is connected via an NPC diode D 26  to the center tap  3 . The upper bridge half of the third phase is connected via an NPC diode D 35  to the center tap  3  of two intermediate circuit capacitors C d /2 connected in series on the input side. The lower bridge half of the third phase is connected via an NPC diode D 36  to the center tap  3 . 
     A basic circuit diagram with the construction of the decoupling networks  1 ,  2  is illustrated in FIG.  2 . The decoupling network  1  has a resonant inductor L R1  connected to a positive pole of the intermediate circuit. A switch T R1  and an inverse diode D R1  are connected to a junction point of the inductor L R1  and the upper bridge half. The further terminals of the two constructional components are connected to a switch T C1 , an inverse diode D C1  and, via a resonant capacitor C R1 , to the center tap  3 . Further terminals of the switch T C1  and the inverse diode D C1  are connected via a charging capacitor C C1  to the center tap  3 . 
     The decoupling network  2  has a resonant inductor L R2  connected to a negative pole of the intermediate circuit. A charging capacitor C C2  and a resonant capacitor C R2  are connected to the junction point of the inductor L R2  and the lower bridge half. A further terminal of the charging capacitor C C2  is connected to a switch T C2  and an inverse diode D C2 . Further terminals of the switch T C2  and the inverse diode D C2  are connected to the further terminal of the resonant capacitor C R2  and also to a switch T R2  and an inverse diode D R2 . At their other ends, the switch T R2  and the inverse diode D R2  are connected to the center tap  3 . 
     The halved intermediate circuit voltages across the intermediate circuit capacitors C d /2 are designated by V dc /2, the voltages across the decoupling networks  1  and  2  are designated by V k1  and V k2 , respectively, and the voltages across the load are designated by V 1 , V 2 , V 3 . 
     The functioning of the decoupling of the commutation voltage from the intermediate circuit voltage by two separate protective circuits in the form of the three-pole decoupling networks  1  and  2  for the upper and lower bridge halves in the three-point converter is explained in detail below using the example of the circuit in FIG.  2 . The additional passive elements of the two circuits are the large charging capacitors C C1  and C C2 , whose voltages are kept virtually constant at a value of 1.2*V dc /2, and also the resonant inductors L R1  and L R2  and the resonant capacitors C R1  and C R2 , which are charged to the voltages of the charging capacitors C C1  and C C2 , respectively, in the quiescent state. In contrast to the circuit described in Salama, S, Tadros, Y.: Quasi Resonant 3-Phase IGBT Inverter, IEEE-PESC Conference Records, 1995, the commutation is always effected via an NPC diode. The circuits are controlled in such a way that during commutations from the upper bridge half to the center tap and back “positive voltage+←→zero voltage 0”, the upper decoupling network  1  is used, and for commutations from the center tap to the lower bridge half and back “zero voltage 0←→negative voltage −”, the lower decoupling network  2  is used. 
     Since the commutation operations in the upper and lower bridge halves are decoupled, it is possible for simultaneous commutation operations to take place in different phases of the converter. This also permits common commutations in the upper and lower bridge halves in a phase “positive voltage +←→negative voltage −”. 
     The single-phase circuit in FIG. 3 is used to explain the commutations. In this case, a current I LR1  through L R1 , a current I LR2  through L R2 , a current I T11  through T 11 , a current I T12  through T 12 , a current I D11  through D 11 , a current I D13  through D 13 , a current I D14  through D 14 , a current I D15  through D 15 , a current I D16  through D 16  and a load current I LOAD  are each specified. Eight different elementary commutations exist, to be precise four in the case of a positive load current I LOAD    
     (a) from T 11  to D 15 , 
     (b) from T 12  and D 15  to D 13  and D 14 , 
     (c) from D 13  and D 14  to T 12  and D 15 , and 
     (d) from D 15  to T 11 , and also four in the case of a negative load current I LOAD    
     (e) from D 11  and D 12  to T 13  and D 16 , 
     (f) from D 16  to T 14 , 
     (g) from T 14  to D 16 , and 
     (h) from T 13  and D 16  to D 11  and D 12 . 
     Commutation (e) is analogous to commutation (c), likewise (f) to (d), (g) to (a) and (h) to (b). For this reason, only the commutation operations (a) to (d) need be explained. The following description assumes a large load current. In the case of small load currents, there is a change in some instances in the conduction intervals between main switches and reverse-connected parallel diodes (inverse diodes) and/or the diodes of the center tap (NPC diodes). The commutation principle remains unaffected by this. The decoupling network  1  of the upper bridge half is used for the commutation operation (a). The commutation sequence and essential current and voltage profiles are illustrated in FIGS. 4 a-k.    
     In detail, the following is applicable: 
     FIG. 4 a : Before the commutation, 
     FIG. 4 b : Charging of the resonant inductor L R1 , 
     FIG. 4 c : Resonant discharge process of C R1 , 
     FIG. 4 d : Linear reduction of the resonant current via the NPC diode before the turn-off of T 11 , 
     FIG. 4 e : Resonant charging process of C R1 , 
     FIG. 4 f : Discharge of the resonant inductor L R1 , 
     FIG. 4 g : After commutation has concluded, 
     FIG. 4 h : Voltage profile of V k1 , 
     FIG. 4 i : Current profile of I LR1 , 
     FIG. 4 j : Current profile of I T11 , and 
     FIG. 4 k : Current profile of I D15 . 
     The commutation is started by the switches T C1  and T R1  being turned on and L R1  thereupon being charged virtually linearly by C C1 . After the turn-off of T C1 , an oscillation process between L R1  and C R1  begins. After the voltage across C R1  has reached zero, the resonant current commutates from C R1  and T R1  to D 15  and T 11 . The commutation voltage is now zero and T 11  can be turned off in a low-loss manner. The load current commutates virtually instantaneously, i.e. limited only by parasitic inductances in the switch and the diode, from T 11  to the diode D 15 , and also the current I LR1  to D R1  and C R1 . The rate of voltage rise across T 11  is consequently limited by C R1 . In the subsequent ring-back process, the capacitor C R1  is charged to the voltage of C C1  and, finally, the current in L R1  is reduced down to zero by C C1 . The commutation operation is thus ended. 
     Commutation (b) is carried out with the aid of the decoupling network  2  of the lower bridge half. The commutation sequence and essential current and voltage profiles are illustrated in FIGS. 5 a-k . In detail, the following are applicable: 
     FIG. 5 a : Before the commutation, 
     FIG. 5 b : Charging of the resonant inductor L R2 , 
     FIG. 5 c : Resonant discharge process of C R2 , 
     FIG. 5 d : Linear reduction of the resonant current via the NPC diode before the turn-off of T 12 , 
     FIG. 5 e : Resonant charging process of C R2 , 
     FIG. 5 f : Discharge of the resonant inductor L R2 , 
     FIG. 5 g : After commutation has concluded, 
     FIG. 5 h : Voltage profile of V k2 , 
     FIG. 5 i : Current profile of I LR2 , 
     FIG. 5 j : Current profile of I T12  and I D15 , and 
     FIG. 5 k : Current profile of I D14  and I D13 . 
     After the turn-on of T C2  and T R2 , a current is built up virtually linearly through L R2 , on account of which current, after the turn-off of T C2 , the voltage across C R2  oscillates towards zero in a resonant process with L R2 . Once the voltage across C R2  has become zero, the resonant current commutates from C R2  and T R2  to the path D 14 , D 13 , T 12  and D 15 . T 12  can now be turned off in a low-loss manner. The load current commutates virtually instantaneously to D 14  and D 13 . The difference formed from the load current and the resonant current in L R2  immediately before the turn-off of T 12  commutates at the same instant to D R2  and C R2  and thus forms the initial condition for the subsequent ring-back process, which charges C R2  to the voltage of C C2 . After the reduction of the resonant current component in L R2  by C C2 , the commutation operation is concluded. 
     Commutation (c) is carried out with the aid of the decoupling network  2  of the lower bridge half and is initiated by the turn-on of T C2  and T R2 . The commutation sequence and essential current and voltage profiles are illustrated in FIGS. 6 a-m.    
     In detail, the following are applicable: 
     FIG. 6 a : Before the commutation, 
     FIG. 6 b : Charging of the resonant inductor L R2 , 
     FIG. 6 c : Resonant discharge process of C R2 , 
     FIG. 6 d : Reduction of the resonant current via the NPC diode (turn-on of T 12 ), 
     FIG. 6 e : Commutation of the load current, 
     FIG. 6 f : Resonant charging process of C R2 , 
     FIG. 6 g : Discharge of the resonant inductor, 
     FIG. 6 h : After commutation has concluded, 
     FIG. 6 i : Voltage profile of V k2 , 
     FIG. 6 j : Current profile of I LR2 , 
     FIG. 6 k : Current profile of I D16 , 
     FIG. 6   1   : Current profile of I D14 , and 
     FIG. 6 m : Current profile of I D15  and I T12 . 
     Once again the inductor L R2  is charged virtually linearly. The resonant process begins after the turn-off of T C2 , during which resonant process the voltage across C R2  oscillates towards zero. Once the zero voltage has been reached, the resonant current commutates from C R2  and T R2  to D 14  and D 16  and is linearly reduced. T 12  can now be turned on in a low-loss manner. After the complete reduction of the resonant current through D 16 , the load current commutates, limited through L R2 , from D 14  and D 13  to D 15  and T 12 . Afterwards, C R2  is charged to the voltage of C C2  in a resonant process with L R2  and then the current through L R2  is reduced down to zero. 
     The sequence of commutation (d), which is carried out with the aid of the decoupling network  1  of the upper bridge half, and essential current and voltage profiles are illustrated in FIGS. 7 a-m . In detail, the following are applicable: 
     FIG. 7 a : Before the commutation, 
     FIG. 7 b : Charging of the resonant inductor L R1 , 
     FIG. 7 c : Resonant discharge process of C R1 , 
     FIG. 7 d : Linear reduction of the resonant current via the NPC diode (turn-on of T 11 ), 
     FIG. 7 e : Commutation of the load current, 
     FIG. 7 f : Resonant charging process of C R1 , 
     FIG. 7 g : Discharge of the resonant inductor, 
     FIG. 7 h : After commutation has concluded, 
     FIG. 7 i : Voltage profile of V k1 , 
     FIG. 7 j : Current profile of I LR1 , 
     FIG. 7 k : Current profile of I D11 , 
     FIG. 7   1   : Current profile of I D15 , and 
     FIG. 7 m : Current profile of I T11 . 
     To start the commutation operation, once again the switches of the upper bridge half T C1  and T R1  are turned on, L R1  is charged and, after the turn-off of T C1 , C R1  is discharged in an oscillation process down to the zero voltage. The resonant current then commutates from C R1  and T R1  to D 15  and D 11  and is linearly reduced. During the conduction of D 11 , T 11  can be turned on in a low-loss manner, whereupon, with the current zero crossing in L R1 , the load current, limited through L R1 , commutates from D 15  to T 11 . After the commutation of the load current has concluded, C R1  is charged to the voltage of C C1  again by a ring-back process and, finally, the resonant current component in L R1  is reduced by C C1 . 
     As a result of the overlap of commutation operations (a) and (b), and also (c) and (d), it is also possible to realize low-loss commutations directly from the upper to the lower bridge path, both of the decoupling networks  1 ,  2  being used for this purpose. 
     The sequence of the commutation from T 11  and T 12  to D 14  and D 13  and essential current and voltage profiles are illustrated in FIGS. 8 a-k . In detail, the following are applicable: 
     FIG. 8 a : Before the commutation, 
     FIG. 8 b : Charging of the resonant inductors, 
     FIG. 8 c : Resonant discharge process of C R1  and C R2 , 
     FIG. 8 d : Linear reduction of the resonant current before the turn-off of T 11  and T 12 , 
     FIG. 8 e : Resonant charging process of C R1 , and C R2 , 
     FIG. 8 f : Discharge of the resonant inductors, 
     FIG. 8 g : After commutation has concluded, 
     FIG. 8 h : Voltage profile of V k1  and V k2 , 
     FIG. 8 i : Current profile of I LR1  and I LR2 , 
     FIG. 8 j : Current profile of I T11  and I T12 , and 
     FIG. 8 k : Current profile of I D14  and I D13 . 
     The charging process of the resonant inductors L R1 and L R2  as well as the subsequent oscillation process proceed synchronously, with the result that the voltages V k1  and V k2  reach zero at the same instant. The resonant current thereupon commutates to the path D 14 , D 13 , T 12  and T 11 , if appropriate also to D 16  and D 15 . T 11  and T 12  are now turned off in a low-loss manner and the load current commutates virtually instantaneously to D 13  and D 14 . At the same instant, the current I LR1  commutates to D R1  and C R1  and the difference formed from the load current and the current I LR2  commutates to D R2  and C R2 . The ring-back process thereby initiated and the discharge of L R1  and L R2  conclude the commutation operation. 
     The commutation from D 14  and D 13  to T 11  and T 12  is illustrated in FIGS. 9 a-m . In detail, the following are applicable: 
     FIG. 9 a : Before the commutation, 
     FIG. 9 b : Charging of the resonant inductors, 
     FIG. 9 c : Resonant discharge process of C R1  and C R2 , 
     FIG. 9 d : Linear reduction of the resonant current (turn-on of T 11  and T 12 ), 
     FIG. 9 e : Commutation of the load current, 
     FIG. 9 f : Resonant charging process of C R1  and C R2 , 
     FIG. 9 g : Discharge of the resonant inductors, 
     FIG. 9 h : After commutation has concluded, 
     FIG. 9 i : Voltage profile of V k1  and V k2 , 
     FIG. 9 j : Current profile of I LR1  and I LR2 , 
     FIG. 9 k : Current profile of I D11 , 
     FIG. 9 l : Current profile of I D14 , and 
     FIG. 9 m : Current profile of I T11  and I T12 . 
     The commutation begins with the simultaneous charging of L R1  and L R2  and the simultaneous resonant discharge of C R1  and C R2 . Once the zero voltage has been reached, the resonant current commutates to the path D 14 , D 13  and D 12  in parallel with D 16  and D 15 , and also D 11 , and is linearly reduced. T 11  and T 12  can now be turned on in a low-loss manner, with the result that after the current zero crossing in L R1 , the load current, limited through L R1  and L R2 , can commutate from D 14  and D 13  to T 11  and T 12 . Subsequently, as a result of the simultaneous ring-back process, C R1  and C R2  are charged to the voltages of C C1  and C C2 , respectively, and the resonant current in L R1  and L R2  is thereupon linearly reduced. The commutation operation is thus ended. 
     The commutations can generally be differentiated, depending on the power gradient of the instantaneous power of the converter phase, into a commutation with a positive power gradient and a commutation with a negative power gradient. 
     In the case of commutations with a positive power gradient, the instantaneous power of the converter output phase after the commutation is greater than before the commutation. In the case of commutations with a negative power gradient, the instantaneous power after the commutation is less than before the commutation. The commutation operations are shorter than the commutations with a positive power gradient. In the case of commutations with a negative power gradient, an active component (GTO, IGCT or IGBT) turns the phase current off. Consequently, the current commutates virtually instantaneously from the component effecting active turn-off to the diode that accepts the current. In this case, the initial condition for the ring-back process is dependent on the level of the load current. In the case of commutations with a positive power gradient, the commutation duration (di/dt) is determined by the intermediate circuit voltage and the resonant inductance. The initial condition for the ring-back process is zero. 
     During the first phase of all the commutation operations, the charging of L R1  and/or L R2 , energy is released from the charging capacitor C C1  and/or C C2  to the respective resonant inductor and the intermediate circuit. The voltage across C C1  and/or C C2  decreases slightly. During the discharge of the resonant inductors until the conclusion of the commutation operations, energy is fed back into C C1  and/or C C2 . In this case, the quantity of energy fed back is dependent on the type of commutation and the magnitude of the load current. In order to keep the voltage across C C1  and/or C C2  constant at 1.2*V dc /2, feedback control is used. In the event of an increased voltage, it is possible for additional energy to be released, and the voltage decreased, by a lengthened charging phase of the resonant inductor at the beginning of each commutation. 
     On the other hand, as a result of an overlap phase during the switching of the main switches, additional energy can be stored in C C1  and/or C C2  and the voltage can be increased. 
     Using the example of the commutation operation (a), this means that once the zero voltage across C R1  has been reached, T 13  is immediately turned on but T 11  is turned off only with a delay. As a result, additional current is built up in L R1  and influences the ring-back process in such a way that the charging capacitor C C1  stores more energy after the conclusion of the entire oscillation process.