Abstract:
The present invention provides a Mitsubishi SEMI Equipment Communication (MSEC)/SEMI Equipment Communication Standard (SECS) protocol converter and conversion method thereof. The MSEC/SECS protocol converter and conversion method utilize an MSEC transceiver to transmit and receive MSEC signals, an SECS transceiver to transmit and receive SECS signals, an MSEC/SECS module to transform MSEC signals into SECS signals, an SECS/MSEC module to transform SECS signals into MSEC signals, and a control character transmission module to transmit control characters. With the MSEC/SECS protocol converter and conversion method, the computer host only needs the SECS interface to communicate the semiconductor apparatus with different protocols, which reduces the complexity and processing requirements of the computer host.

Description:
BACKGROUND OF INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a converter and a conversion method of semiconductor apparatus protocols, and more particularly, to a converter and a conversion method for converting signals between the MSEC protocol and the SECS protocol.  
         [0003]     2. Description of the Prior Art  
         [0004]     For a more efficient semiconductor process, semiconductor manufacturing factories use some protocols to control and manage semiconductor apparatus. These protocols include SEMI Equipment Communication Standard (SECS) protocol specified by the Semiconductor Equipment and Material Institution (SEMI) and Mitsubishi SEMI Equipment Communication (MSEC) protocol specified by the Mitsubishi company. A computer host needs different protocol interfaces to communicate the semiconductor apparatus having different protocols.  
         [0005]     Please refer to  FIG. 1 .  FIG. 1  is a diagram of a computer host  10  and semiconductor apparatus according the prior art. The computer host  10  connects to a plurality of SECS apparatus  22  and a plurality of MSEC apparatus  24 . The SECS apparatus  22  are the semiconductor apparatus that communicate using SECS protocol, and the MSEC apparatus  24  are the semiconductor apparatus that communicate using MSEC protocol. The SECS apparatus  22  and the MSEC apparatus  24  are both used to perform the specified semiconductor processes. The computer host  10  comprises an SECS interface  12  which connects to the SECS apparatus  22 , an MSEC interface  14  which connects to the MSEC apparatus  24 , and an application layer  16 . The SECS interface  12  and the SECS apparatus  22  transmit and receive SECS signals  32  using RS-232 ports, and the MSEC interface  14  and the MSEC apparatus  24  transmit and receive MSEC signals  34  using RS-232 ports. The application layer  16  processes data transmitted and received by the SECS interface  12  and the MSEC interface  14 .  
         [0006]     Because the SECS apparatus  22  and the MSEC apparatus  24  use different protocols, the computer host  10  must use different protocol interfaces to control the connected semiconductor apparatus. Because the computer host  10  can not use the unique protocol to control and manage semiconductor apparatus and the number of the SECS apparatus  22  and the MSEC apparatus  24  is rapidly increasing, integrating the SECS apparatus  22  and the MSEC apparatus  24  is a complicated process.  
       SUMMARY OF INVENTION  
       [0007]     It is therefore an objective of the claimed invention to provide a conversion method for semiconductor apparatus to convert between the MSEC and SECS protocols.  
         [0008]     It is another objective to provide an MSEC/SECS protocol converter applied to a semiconductor manufacture to solve the above-mentioned problem.  
         [0009]     According to the claimed invention, a conversion method of semiconductor deice protocol comprises inputting a first signal which is one of an MSEC signal or an SECS signal, judging if the first signal is a control character, outputting the first signal if the first signal is the control character, receiving the first signal, checking the checksum of the received first signal, transforming the first signal into a transformed first signal being an MSEC signal or an SECS signal, computing and updating the length and the checksum of the transformed first signal, and outputting the transformed first signal.  
         [0010]     According to the claimed invention, an MSEC/SECS protocol converter comprises a first transceiver, a second transceiver, an MSEC/SECS module, an SECS/MSEC module, and a control character transmission module. The first transceiver is used to transmit and receive MSEC signals, and the second transceiver is used to transmit and receive SECS signals. The MSEC/SECS module transforms MSEC signals into SECS signals, and the SECS/MSEC module transforms SECS signals into MSEC signals. When one of the first or second transceivers receives a control character, the control character transmission module directly transmits the received control character to the other transceiver.  
         [0011]     The present invention utilizes the MSEC/SECS protocol converter and the conversion method of semiconductor apparatus protocol to connect the semiconductor apparatus and the computer host to transmit the signals with different protocols. Thus, the computer host only needs the unique interface to transmit and receive signals, which reduces the complexity and processing requirements of the computer host.  
         [0012]     These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0013]      FIG. 1  is a diagram of a computer host and semiconductor apparatus according the prior art.  
         [0014]      FIG. 2  is a diagram of an MSEC/SECS protocol converter, a computer host, and semiconductor apparatus according the present invention.  
         [0015]      FIG. 3  is a block diagram of the MSEC/SECS protocol converter according to the present invention.  
         [0016]      FIG. 4  is a flowchart for transforming MSEC signals into SECS signals according to the present invention.  
         [0017]      FIG. 5  is a corresponding chart of the data structure when transforming MSEC signals into SECS signals according to the present invention.  
         [0018]      FIG. 6  is a flowchart for transforming SECS signals into MSEC signals according to the present invention.  
         [0019]      FIG. 7  is a corresponding chart of the data structure when transforming SECS signals into MSEC signals according to the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0020]     Please refer to  FIG. 2 .  FIG. 2  is a diagram of an MSEC/SECS protocol converter  50 , a computer host  40 , and semiconductor apparatus according the present invention. The computer host  40  connects to a plurality of SECS apparatus  52  and at least one MSEC apparatus  54  through the MSEC/SECS protocol converter  50 . The SECS apparatus  52  are the semiconductor apparatus that communicate using SECS protocol, and the MSEC apparatus  54  are the semiconductor apparatus that communicate using MSEC protocol. The MSEC/SECS protocol converter  50  converts signals between the MSEC and SECS protocols. The SECS apparatus  52  and the MSEC apparatus  54  are both used to perform the specified semiconductor processes. The computer host  40  transmits and receives SECS signals  62  to control operations of the SECS apparatus  52  and the MSEC apparatus  54 , and comprises an SECS interface  42  and an application layer  46 . The SECS interface  42 , the MSEC/SECS protocol converter  50 , and the SECS apparatus  52  transmit and receive SECS signals  62  using RS-232 ports. The application layer  46  processes the SECS signals transmitted and received by the SECS interface  42 . The MSEC signals  64  outputted by the MSEC apparatus  54  are converted into the SECS signals  62  through the MSEC/SECS protocol converter  50 , and are transmitted to the application  46  of the computer host  40  by the SECS interface  42 . On the other hand, the SECS signals  62  outputted by the SECS interface  42  of the computer host  40  are converted into the MSEC signals  64  through the MSEC/SECS protocol converter  50 , and are transmitted to the MSEC apparatus  54 . Thus, the MSEC apparatus  54  does not need to have setting changes to connect it through the MSEC/SECS protocol converter  50  to the control system having the SECS protocol.  
         [0021]     To describe the detailed conversion method of the MSEC/SECS protocol converter  50 , please refer to  FIG. 3 .  FIG. 3  is a block diagram of the MSEC/SECS protocol converter  50  according to the present invention. The MSEC/SECS protocol converter  50  comprises an MSEC transceiver  70 , an MSEC/SECS module  71 , an SECS transceiver  80 , an SECS/MSEC module  81 , and a control character transmission module  90 . The MSEC transceiver  70  and the SECS transceiver  80  transmit and receive the MSEC signals  64  and the SECS signals  62  shown in  FIG. 2 , respectively. Please refer to  FIG. 2  and  FIG. 3 . The MSEC/SECS module  71  transforms the MSEC signals  64  into the SECS signals  62 , and the SECS/MSEC module  81  transforms the SECS signals  62  into the MSEC signals  64 . The control character transmission module  90  is electronically connected to the MSEC transceiver  70  and the SECS transceiver  80  for transmitting the control characters defined in the protocols, including en-query (ENQ), end of transfer (EOT), acknowledge (ACK), and non-acknowledge (NAK).  
         [0022]     The MSEC/SECS module  71  comprises an MSEC collection module  72 , an MSEC check module  74 , an MSEC/SECS transform module  76 , and an MSEC/SECS computation module  78 . The MSEC collection module  72  is electronically connected to the MSEC transceiver  70  for collecting the MSEC signals that are not the control characters and checking the integrity of the collected MSEC signals according to the length of the MSEC signals. The MSEC check module  74  is electronically connected to the MSEC collection module  72  for checking the even check bit and the checksum. The MSEC/SECS transform module  76  is electronically connected to the MSEC check module  74  for transforming the header and data of MSEC signals into header data in the SECS format. The MSEC/SECS computation module  78  is electronically connected to the MSEC/SECS transform module  76  and the SECS transceiver  80  for computing and updating the length and the checksum of SECS signals transformed by the MSEC/SECS transform module  76 , and transmitting the SECS signals to the SECS transceiver  80 .  
         [0023]     The SECS/MSEC module  81  comprises an SECS collection module  82 , an SECS check module  84 , an SECS/MSEC transform module  86 , and an SECS/MSEC computation module  88 . The SECS collection module  82  is electronically connected to the SECS transceiver  80  for collecting the SECS signals that are not the control characters and checking integrity of the collected SECS signals according to the length of the SECS signals. The SECS check module  84  is electronically connected to the SECS collection module  82  for checking the even check bit and the checksum. The SECS/MSEC transform module  86  is electronically connected to the SECS check module  84  for transforming the header and data of SECS signals into those with MSEC format. The SECS/MSEC computation module  88  is electronically connected to the SECS/MSEC transform module  86  and the MSECS transceiver  70  for computing and updating the length and the checksum of MSEC signals transformed by the SECS/MSEC transform module  86 , and transmitting the MSEC signals to the MSEC transceiver  70 .  
         [0024]     Please refer to  FIG. 3  and  FIG. 4 .  FIG. 4  is a flowchart for transforming MSEC signals into SECS signals according to the present invention. The signal conversion flow comprises the following steps:  
         [0025]     Step  100 : Inputting an MSEC signal using the MSEC transceiver  70 .  
         [0026]     Step  102 : Judging if the inputted MSEC signal is a control character, including ENQ, EOT, ACK, and NAK, and performing step  103  if the MSEC signal is a control character or performing step  104  if the MSEC signal is not a control character.  
         [0027]     Step  103 : Transmitting the control character to the SECS transceiver  80  through the control character transmission module  90 , which is separate from the MSEC/SECS module  71  and the SECS/MSEC module  81 , transmitting the control character to the computer host by the SECS transceiver  80 , and performing step  100  to receive the next MSEC signal.  
         [0028]     Step  104 : Enabling and resetting a T1 timer  105  to judge if the MSEC collection module  72  has collected the MSEC signals in a specified period, and performing step  109  if it is overtime or performing step  106  if the MSEC signal is received completely.  
         [0029]     Step  106 : Disabling the T1 timer  105 , checking if the checksum of the MSEC signal is correct by using the MSEC check module  74 , and performing step  109  if the checksum is incorrect or performing step  108  if the checksum being correct.  
         [0030]     Step  108 : Checking if the even check bit is correct by using the MSEC check module  74 , and performing step  109  if the even check bit is incorrect or performing step  110  if the even check bit is correct.  
         [0031]     Step  109 : Outputting a control signal NAK to the MSEC apparatus through the MSEC transceiver  70  to make the MSEC apparatus re-output the MSEC signal to the MSEC/SECS protocol converter, and performing step  100 .  
         [0032]     Step  110 : Decoding the even check bit of the MSEC signal by using the MSEC/SECS transform module  76 . This involves removing the even check bit of the MSEC signal, and storing the even-check-bit decoded data in a corresponding portion of the SECS signal.  
         [0033]     Step  120 : Transforming the header of MSEC signal into that with SECS format by using the MSEC/SECS module  76  with an SECS apparatus identification (ID)  121  and an MSEC/SECS instruction ID conversion table  123 .  
         [0034]     Step  130 : Transforming the data portion of the MSEC signal into the SECS format by using the MSEC/SECS transform module  76 .  
         [0035]     Step  140 : Computing the length of the SECS signal transformed in step  120  and step  130  by using the MSEC/SECS computation module  78  to update the length of the SECS signal.  
         [0036]     Step  150 : Computing the checksum of the SECS signal transformed in step  120  and step  130  by using the MSEC/SECS computation module  78  to update the checksum of the SECS signal.  
         [0037]     Step  160 : Outputting the transformed SECS signal to the SECS transceiver  80  to transmit the transformed SECS signal to the computer host, and performing step  100  to receive the next MSEC signal.  
         [0038]     Please refer to  FIG. 5 .  FIG. 5  is a corresponding chart of the data structures when transforming MSEC signals into SECS signals as shown in  FIG. 4  according to the present invention. The step  120  of transforming the header shown in  FIG. 4  includes a transform step  122 , a transform step  124 , a transform step  126 , and a transform step  128 . The transform step  122  updates the first and second bytes of the header of the MSEC signal to an SECS apparatus ID defined by a user and reserves the reserve bit. The transform step  124  generates an SECS instruction ID to store in the third and fourth bytes of the header of the SECS signal according to the third byte and the data portion of the header of the MSEC signal and reserves the wait bit of the MSEC signal. The transform step  126  sets the fifth and sixth bytes of the header of the SECS signal to ASCII 80H and 01H, respectively. The transform step  128  sets the seventh to tenth bytes of the header of the MSEC signal to the seventh to tenth bytes of the header of the SECS signal. The transforming data step  130  includes a transforming step  132  and a transforming step  134 . The transforming step  132  sets the first byte of the data portion of the SECS signal to ASCII 41H, and the transform step  134  sets the second byte of the data portion of the SECS signal to the data length.  
         [0039]     Please refer to  FIG. 3  and  FIG. 6 .  FIG. 6  is a flowchart for transforming SECS signals into MSEC signals according to the present invention. The signal conversion flow comprises the following steps:  
         [0040]     Step  200 : Inputting an SECS signal by using the SECS transceiver  80 .  
         [0041]     Step  202 : Judging if the inputted SECS signal is a control character, and performing step  203  if the SECS signal is a control character or performing step  204  if the SECS signal is not a control character.  
         [0042]     Step  203 : Transmitting the control character to the MSEC transceiver  70  through the control character transmission module  90 , which is separate from the MSEC/SECS module  71  and the SECS/MSEC module  81 , transmitting the control character to the computer host using the MSEC transceiver  70 , and performing step  200  to receive the next SECS signal.  
         [0043]     Step  204 : Enabling and resetting a T1 timer  105  to judge if the SECS collection module  82  has collected the SECS signals in a specified period, and performing step  208  if it is overtime or performing step  206  if the SECS signal is received completely.  
         [0044]     Step  206 : Disabling the T1 timer  105 , checking if the checksum of the SECS signal is correct by using the SECS check module  84 , and performing step  208  if the checksum is incorrect or performing step  220  if the checksum is correct.  
         [0045]     Step  208 : Outputting a control signal NAK to the computer host through the SECS transceiver  80  to make the computer host re-output the SECS signal to the MSEC/SECS protocol converter, and performing step  200 .  
         [0046]     Step  210 : Transforming the header of the SECS signal into the MSEC format by using the SECS/MSEC transform module  86 .  
         [0047]     Step  220 : Transforming the data portion of the SECS signal into the MSEC format by using the SECS/MSEC module  86  with the SECS/MSEC instruction ID conversion table  123 .  
         [0048]     Step  230 : Encoding the data portion transformed in the step  220  by using the SECS/MSEC transform module  86  and the method of adding the even check bit to the transformed signal.  
         [0049]     Step  240 : Computing the length of the MSEC signal transformed in steps  210 ,  220 , and  230  by using the SECS/MSEC computation module  88  to update the length of the MSEC signal.  
         [0050]     Step  250 : Computing the checksum of the MSEC signal transformed in steps  210 ,  220 , and  230  by using the SECS/MSEC computation module  88  to update the checksum of the MSEC signal.  
         [0051]     Step  260 : Outputting the transformed MSEC signal to the MSEC transceiver  70  to transmit the transformed MSEC signal to the MSEC apparatus, and performing step  200  to receive the next SECS signal.  
         [0052]     Please refer to  FIG. 7 .  FIG. 7  is a corresponding chart of the data structures when transforming SECS signals into MSEC signals as shown in  FIG. 6  according to the present invention. The step  210  of transforming the header shown in  FIG. 6  includes a transform step  222 , a transform step  224 , a transform step  226 , and a transform step  228 . The transform step  222  updates the third and fourth bytes of the header of the SECS signal to ASCII 01H, and reserves the wait bit to store in the third and fourth bytes of the header of the MSEC signal. The transform step  224  sets the fifth byte of the header of the MSEC signal to 80H, and the transform step  226  sets the sixth byte of the header of the MSEC signal to one of ASCII 00H to FFH. The transform step  228  sets the seventh to tenth bytes of the header of the SECS signal to the seventh to tenth bytes of the header of the MSEC signal. The transforming data step  230  includes a transforming step  232 . The transforming step  232  transforms the instruction ID of the third and fourth bytes of the header of the SECS signal to store in the first and second bytes of the data portion of the MSEC signal. The step  230  encodes the instruction ID transformed in the step  232  and the even check bit of the data portion of the MSEC signal and stores the encoded data portion in the bytes being behind the third bytes of data portion of the MSEC signal.  
         [0053]     In the above-mentioned flowcharts of  FIG. 4  and  FIG. 6 , the MSEC/SECS conversion method includes inputting an MSEC signal or an SECS signal, judging if the MSEC signal or the SECS signal is a control character (directly outputting the control character if the MSEC signal or the SECS signal are the control character), receiving the MSEC signal or the SECS signal, checking the checksum of the collected MSEC signal or the SECS signal, transforming the MSEC signal or the SECS signal into a transformed SECS or MSEC signal, respectively, computing and updating the length and the checksum of the transformed MSEC or SECS signal, and outputting the transformed MSEC or SECS signal. What is different is the even check bit exists in the MSEC signal, which is needed to check the even check bit and decode in the transforming the MSEC signal into the SECS signal step. The even check bit does not exist in the SECS data, which is needed to encode in the step of transforming the SECS signal into the MSEC signal. In addition, the timer used to receive the MSEC signal and the SECS signal can be omitted or replaced by other programs such as loop programs.  
         [0054]     The present invention converter also uses the one-direction MSEC/SECS signal conversion method. That is, a converter is made to transform an MSEC signal into an SECS signal according to the conversion method of transforming the MSEC signal to the SECS signal, or a converter is made to transform an SECS signal to an MSEC signal according to the conversion method of transforming the SECS signal to the MSEC signal.  
         [0055]     In contrast to the prior art, a computer host using different protocols interfaces to transmit and receive signals having different protocols, but the present invention MSEC/SECS protocol converter and conversion method exchange the protocols of MSEC signals and SECS signals. Thus, the computer host only needs the SECS interface to transmit and receive signals, which reduces the complexity and processing requirements of the computer host. In addition, applying the present invention protocol converter or conversion method does not involve modifying the current apparatus that are connected to the computer host, which reduces much of the modification cost.  
         [0056]     Those skilled in the art will readily observe that numerous modifications and alterations of the apparatus may be made while retaining the teachings of the invention. Accordingly, that above disclosure should be construed as limited only by the metes and bounds of the appended claims.