Abstract:
An apparatus includes a package having a first surface and a conductive contact exposed at the first surface. A capacitor is inside the package. The capacitor has a first conductive contact exposed at a first surface of the capacitor. The first conductive contact has a first portion spanning a width of the first surface of the capacitor. The first surface of the capacitor is substantially parallel to the first surface of the package. A conductive path connects the first portion of the first conductive contact of the capacitor to the first conductive contact proximate the first surface of the package.

Description:
BACKGROUND  
         [0001]    The invention relates to an integrated circuit package having a capacitor.  
           [0002]    Decoupling capacitors, for example, are used to filter noise that is produced in computer circuits by inductive and capacitive parasitics of power supplies. Decoupling capacitors also may be used to dampen power system transients, for example, voltage overshoot or droop that occurs when a processor is shut down or powered up.  
           [0003]    Decoupling capacitors also are used to provide supplemental current to a die&#39;s “hot spots”, localized portions of a circuit die that require large amounts of current.  
           [0004]    A decoupling capacitor&#39;s response time to a power system transient may be limited by impedance (e.g., inductance and resistance) between the decoupling capacitor and the die.  
           [0005]    Decoupling capacitors may be surface mounted to a package upon which a die is mounted. Industry trends are directed to reducing device sizes and increasing packaging densities. Therefore, the amount of package real estate available to surface mount capacitors is becoming increasingly small. 
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0006]    [0006]FIG. 1 is a cross-sectional view of a die mounted to a package with a capacitor.  
         [0007]    FIGS.  2 A- 2 B are perspective views of capacitors.  
         [0008]    [0008]FIG. 3 is a perspective view of a capacitor in a package.  
         [0009]    [0009]FIG. 4 is a sectional plan view of a package containing multiple capacitors.  
         [0010]    [0010]FIG. 5 is a sectional plan view of a package containing multiple capacitors. 
     
    
     DETAILED DESCRIPTION  
       [0011]    As shown in FIG. 1, a package  32  has a first side  38  and a second side  40 . A die  30  is mounted on the first side  38  of the package  32 . The die  30  includes a silicon or other semiconductor substrate on which both active and passive components of an integrated circuit may be fabricated. The die  30  is supported by and electrically connected to vias  36  in the package  32  by die bumps  34 , which serve as electrical contacts. Other electrical connections may be used instead of die bumps  34 , such as wires. Vias  36  pass through the package  32  and electrically connect the die bumps  34  to contacts  12  on a capacitor  10  inside the package  32 .  
         [0012]    The capacitor  10  can be, for example, a low resistance, low inductance, multi-layer ceramic chip (MLCC) capacitor. The internal structure of MLCC capacitors typically includes multiple conductive layers insulated from each other. Each layer is typically connected to all of the contacts  12  on a capacitor  10  having a given polarity. Adjacent conductive layers are typically connected to opposite polarity contacts.  
         [0013]    The capacitor  10  may have an industry standard form factor which identifies a capacitor&#39;s geometric size, shape, and weight. Other types of capacitors may be used.  
         [0014]    Holes are typically drilled through the package  32  material. The walls of the holes may be plated with metal and filled with non-conductive epoxy to create the vias  36 . Alternatively, the holes may be completely filled with conductive material to create the vias  36 . The vias  36  provide conductive paths for the flow of current through the package  32 .  
         [0015]    The capacitor  10  can have four contacts  12  on each of two sides as shown, for a total of eight contacts. Each contact  12  completely spans one of two sides  20 ,  24  of capacitor  10  (see FIGS. 2A and 2B). The contacts  12  also partially span the top surface  14  and the bottom surface  16  of the capacitor  10 .  
         [0016]    The portion  15  of each contact  12  that spans the side surfaces  20 ,  24  are parallel to the first package side  38  next to the die bumps  34  and the second package side  40  next to package bumps  42 . The package bumps  42  are electrical contacts that serve as connection points for power sources V ss  and V cc . Other conductive connections, for example, wires may be used in place of the package bumps  42 .  
         [0017]    The surface area of the portion  15  of each contact  12  that spans one of the side surfaces  20 ,  24  of the capacitor  10  can be greater than the surface area of the portion  13 ,  17  of the contact  12  that spans either the top surface  14  or the bottom surface  16  of the capacitor  10 . Thus, multiple vias  36  can terminate at the portion  15  of each contact  12  that spans a side surface  20 ,  24  of the capacitor  10 . Multiple vias  36  can be connected in parallel to create a low impedance connection between each of the die bumps  34 , each of the contacts  12  on the capacitor  10  and each of the package bumps  42  as discussed in more detail with respect to FIG. 3.  
         [0018]    Although the illustrated example can be used in complementary metal oxide semiconductor (CMOS) applications, other voltages and combinations of voltages may be used. For example, in gate turnoff logic (GTL) applications, V ss  connections and ground connections are made to the package bumps  42 .  
         [0019]    The package  32  illustrated in FIG. 1 includes a core layer  44 , four buildup layers  46 , two conductive planes  48  and underfill  50 . The design and arrangement of the different layers and components inside the package can vary. For example, the package  32  may contain more than one core layer  44 . The core layer  44  is typically a preformed, reinforced, epoxy material, but may include other materials.  
         [0020]    The package  32  may contain more or fewer buildup layers  46 . Buildup layers  46  are formed of a material similar to core layer  44  material. Buildup layers  46  typically are not preformed, but are created by flowing epoxy onto a preformed core layer  44 .  
         [0021]    A package may contain one or more metal conductive planes  48 . The underfill  50 , which surrounds the capacitor  10 , may be an epoxy-based material and should be resistant to cracking.  
         [0022]    [0022]FIGS. 2A and 2B illustrate examples of capacitors that can be provided in the package  32  as described above. The capacitor  10 A has a standard form factor and eight alternating polarity contacts  12 . The term “alternating polarity” means that the polarity of each contact  12  is different from the polarity of adjacent contacts  12 . For example, one contact might be connected to a 5-volt power source and an adjacent contact might be connected to a ground connection.  
         [0023]    As shown in FIG. 2B, capacitor  10 B includes fourteen alternating polarity contacts  12 . In this example, the end caps  26  and  28  also serve as contacts.  
         [0024]    Capacitors may have more or fewer contacts  12  and may have different relative spacing between the contacts  12 . Adjacent contacts  12  on a single capacitor typically have different polarities, and contacts  12  are typically arranged on opposite sides of a capacitor. The body  11  of a capacitor is typically made of ceramic, but may be made of other materials.  
         [0025]    As shown in FIG. 3, each of the contacts  12  is connected to three vias  36 . Each set of three vias  36  begins on one end at a single contact  12  and terminates at either a single die bump  34  or a single package bump  42 . Generally, one or more vias  36  may be connected in parallel between each contact  12  on the capacitor  10  and each die bump  34  or package bump  42 .  
         [0026]    The maximum number of vias  36  that can be connected in this manner between a particular contact  12  and a particular die bump  34  or package bump  42  depends on the size of each via  36 , the apparent surface area of the contact  12 , and the apparent surface area of the particular die bump  34  or package bump  42 . The term “apparent surface area” refers to the surface area of the portion of a contact  12 , die bump  34 , or package bump  42  that is substantially perpendicular to and in the path of one or more vias  36  that terminate on that point. The arrangement of FIGS. 1 and 3 provides a relatively large apparent surface area for the contacts  12 . Thus, more vias  36  can be terminated at each contact  12 .  
         [0027]    As shown in FIG. 4, a package  32 A contains multiple capacitors  10 K,  10 L . . .  10 Z arranged side-by-side. Any number of capacitors  10 K,  10 L . . .  10 Z can be configured as shown. A die  30 , indicated by dashed lines, is mounted above the package  32 A.  
         [0028]    The contacts  12  of each capacitor  10 K,  10 L . . .  10 Z can be electrically insulated from the contacts  12  of neighboring capacitors by underfill  50  material and/or core material  44 . Alternatively, metal strips  52  may be formed directly on the core material  44  and underfill  50  to electrically connect contacts  12  of adjacent capacitors, such as shown for capacitors  10 K and  10 L. Similar connections can be made on the opposite side of the capacitors  10 K and  10 L. In that way the adjacent capacitors  10 K and  10 L can be connected in parallel.  
         [0029]    Additional vias  36  may be terminated directly onto the metal strip  52 . This can further increase the apparent surface area available for connecting vias  36  to a contact  12 .  
         [0030]    The package arrangement of FIG. 4 allows capacitors  10 K,  10 L . . .  10 Z to be lined up in such a way that many capacitors can be fit in a particular size package  32 A, and a relatively large capacitance can be obtained for a particular package size.  
         [0031]    As shown in FIG. 5, alternate embodiments may include capacitors  10  arranged in rows  60 A,  60 B . . .  60 K and columns  70 A . . .  70 B.  
         [0032]    The package  32  may provide one or more of the following advantages: higher capacitance, lower inductance and lower resistance between power supply connections and a die or other variable electrical load, and improved power system response to power system transient events.  
         [0033]    Improved power system stability and better overall power integrity can be achieved. The package also may provide large values of capacitance in relatively small spaces. Smaller components can be manufactured, resulting in a more efficient use of space.  
         [0034]    The package  32  can provide relatively low equivalent series inductance (ESL) and relatively low equivalent series resistance (ESR) conductive paths between a capacitor and a die. Additionally, the cost per unit of capacitance may be reduced because of the smaller amount of material needed to provide a particular capacitance.  
         [0035]    Furthermore, manufacturing the package  32  can be relatively simple because the package can incorporate industry standard, readily available components.  
         [0036]    Other implementations are within the scope of the following claims.