Abstract:
A plurality of thin-film transistors constituting an array are successively switched on by gate signals. Feed-through correction capacitances are respectively connected between an output terminal of each thin-film transistor switched on by a certain gate signal and a predetermined number of gate lines for supplying subsequent gate signals. A decrease in an output voltage of each thin-film transistor caused by transmission of a fall of the gate signal to the output terminal via a gate-source capacitance is compensated for by a rise of the subsequent gate signal which is transmitted to the output terminal via the feed-through correction capacitance.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a thin-film transistor array to be used as a driver or switching circuit in printers, contact-type image sensors, display devices and the like. 
     Referring to FIG. 1, there is shown an example of a conventional thin-film transistor array. 
     In FIG. 1, Q 1  to Q 3  represent thin-film transistors which form a thin-film transistor array; V G1  to V G3  represent gate signals; V D1  to V D3 , data signals; C L1  to C L3 , load capacitances; V O1  to V O3 , output signals; C GS1  to C GS3 , gate-source capacitances; S, a source; D, a drain; G, a gate. Although only three transistors are shown in FIG. 1, it is to be understood that a large number of transistors are arranged in practical use. 
     The operation of each thin-film transistor in such a thin-film transistor array will be described with reference to an arbitrary thin-film transistor (for example, Q 1 ). 
     An outline of the operation is as follows. When a thin-film transistor Q 1  is turned on by a gate signal V G1 , a load capacitance C L1  is charged by a data signal V D1 . A resultant voltage across the load capacitance C L1  is used as an output signal V O1 . 
     The detail of the operation will be described with reference to FIG. 2 which shows waveforms for explaining the operation of one thin-film transistor Q 1  in FIG. 1. In FIG. 2, the diagrams (a), (b) and (c) show respective waveforms of the data signal V D1 , gate signal V G1 , and output signal V O1 . 
     In the following, the operation is described with the passage of time. 
     (1) Operation from t 1  to t 2   
     The gate signal V G1  is turned to a high value V GG  by a pulse b 1 , so that the thin-film transistor Q 1  is switched on. At the same time, the data signal V D1  is turned to a high value V DD  by a pulse a. Accordingly, the load capacitance C L1  is charged by the data signal having the value V DD , and a resultant voltage across the load capacitance C L1  is outputted as an output signal V O1 . 
     The waveform of the output signal V O1  shown in FIG. 2(c) is drawn so as to jump by ΔV at the time t 1  relative to the preceding value. This is because when the gate signal V G1  rises to V GG , the rapid change of the voltage is transmitted to the source S through the gate-source capacitance C GS1  intrinsically existing between the gate G and source S to thereby increase a potential at the load capacitance C L1 . 
     This is called a feed-through phenomenon and the changed voltage ΔV is called a feed-through voltage. The value ΔV is expressed by the following equation: ##EQU1## 
     As the charging of the load capacitance C L1  progresses, the value of the output signal V O1  increases. Because the difference between the output signal value V O1  and the data signal value V GG  is reduced with the increase of the output signal value V O1 , a current flowing through the thin-film transistor Q 1  becomes small, so that the increase rate of the output signal V O1  becomes small. It is not long before the output signal V O1  reaches an output high-level peak V H . 
     This process forms a waveform c 1  in FIG. 2(c). The output signal V O1  is kept at the output high-level peak V H  until the gate signal V G1  falls at t 2 . 
     (2) Operation from t 2  to t 3   
     When the gate signal V G1  falls at the time t 2 , the rapid potential change is transmitted to the source S through the gate-source capacitance C GS1  to thereby decrease the potential at the load capacitance C L1 , i.e., the output signal V O1 . This decrease of the potential is also referred to as the feed-through voltage ΔV, as described above. 
     A settled value after the decrease of the potential is an output high level V OH . Because the thin-film transistor Q 1  is kept off until the gate signal V G1  is turned to the high value V GG  again at t 3 , the output signal V O1  is kept at the output high level V OH . Some operation corresponding to the output high level is carried out in an external system using the value V OH . 
     (3) Operation from t 3  to t 4   
     When a pulse b 2  of the gate signal V G1  rises at the time t 3 , the output signal V O1  increases instantaneously by the feed-through voltage ΔV due to the feed-through phenomenon. Because the data signal V D1  is, however, zero in a period from t 3  to t 4 , the load capacitance C L1  is discharged to reduce the output signal V O1  to zero rapidly. This process forms a waveform C 2  in FIG. 2(c). 
     (4) Operation at and after t 4   
     When the pulse b 2  of the gate signal V G1  falls at the time t 4 , the output signal V O1  decreases by the feed-through voltage ΔV due to the feed-through phenomenon, so that the output signal V O1  takes a minus peak. The minus peak is referred to as an output low-level peak V L . 
     Accordingly, relations between potentials around the thin-film transistor Q 1  immediately after the gate signal V G1  becomes zero at t 4  are as follows. The potential (0) at the gate G is positive relative to the potential (-ΔV) at the source S. The potential (0 as a value of the data signal V D1 ) at the drain D is also positive relative to the potential at the source S. 
     It is, however, commonly known that the source S and drain D of the thin-film transistor are symmetric in structure, and the source S and drain D can serve interchangeably. 
     Therefore, a current continues to flow through the thin-film transistor Q even after t 4 , so that the output signal V O1  increases gradually from the output low-level peak V L . Ultimately, the voltage between the source S and drain D is settled to the threshold voltage V th  of the thin-film transistor Q 1 , that is defined as a specific voltage level between the opposite ends (source S and drain D) of the thin-film transistor Q 1  with a voltage below which level no current can flow through the thin-film transistor Q 1 . The settled value is referred to as an output low level V OL . In short, V OL  =-V th . This process forms a waveform c 3  in FIG. 2(c). 
     An operation to be conducted when the output signal V O1  is low, is carried out in an external system using the output low level V OL . 
     A description of such a thin-film transistor array is found in the literature by Malcolm J. Thompson and Hsing C. Tuan, entitled &#34;Amorphous Si Electronic Devices and Their Applications&#34;, IEDM 86 pp. 192-195 (particularly, FIG. 8). 
     However, the following problems are caused by the feed-through phenomenon in the aforementioned conventional thin-film transistor arrays. 
     The first problem is that the output high level V OH  is reduced by the feed-through voltage ΔV from the given data signal value V D1  to a value often insufficient for a desired operation. To assure the desired operation, a voltage higher by the feed-through voltage ΔV than the output high level V OH  must be prepared as the data signal V D1 . 
     The second problem is that the output low level V OL  depends on the threshold voltage V th  of the thin-film transistor which changes with the passage of time during the operation of the thin-film transistor. Accordingly, the output low level V OL  cannot be stable. When the output low level V OL  is not stable, for example the following disadvantage arises. This is, in the case where the thin-film transistor array is used in an image processing device or the like to attain a tonal feature, the potential difference between the output high level and low level is not stabilized, causing erroneous results. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to solve the aforementioned problems. 
     To solve the above problems, the present invention provides a thin-film transistor array having a plurality of thin-film transistors successively switched on by gate signals continuously generated, in which feed-through correction capacitances are respectively connected between an output terminal of each thin-film transistor switched on by a certain gate signal and a predetermined number of gate lines for supplying subsequent gate signals. 
     In each thin-film transistor, some capacitance intrinsically exists between a gate and source (or between a gate and drain) because of its structure. Therefore, when a gate signal pulse falls, an output potential of each thin-film transistor is reduced through the intrinsic capacitance (feed-through phenomenon). 
     If, however, feed-through correction capacitances are provided so as to be respectively connected between the output terminal of each thin-film transistor switched on by a certain gate signal and a predetermined number (for example, two) of subsequent gate lines for supplying the predetermined number (for example, two) of gate signals, the decrease of the output potential caused by the fall of the certain gate signal can be instantly compensated for by an increase thereof caused by a rise of the gate signal following the certain gate signal. Length of a total period of such correction can be determined suitably by establishment of the predetermined number. 
     Other and further objects, features and advantages of the invention will appear more fully from the following description taken in connection with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram showing an example of a conventional thin-film transistor array; 
     FIGS. 2(a) to 2(c) show waveforms for explaining the operation of one thin-film transistor depicted in FIG. 1; 
     FIG. 3 is a diagram for explaining the basic concept of the present invention; 
     FIGS. 4(a) to 4(e) show waveforms for explaining the operation of one thin-film transistor depicted in FIG. 3; and 
     FIG. 5 is a diagram showing an embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 3 is a diagram for explaining the basic concept of the invention. Reference characters in FIG. 3 correspond to those in FIG. 1. In FIG. 3, C F12 , C F13  and C F23  represent feed-through correction capacitances. That is, FIG. 3 is different from FIG. 1 only in that the feed-through correction capacitances are added. 
     The function of the feed-through correction capacitances is to instantly cancel a decrease of the output signal value caused by a fall of a gate signal through the feed-through phenomenon by utilizing an increase thereof caused by a rise of a succeeding gate signal. Accordingly, there can be prevented over a predetermined period the output signal decrease having an amount of the feed-through voltage ΔV. 
     The invention assumes the case where the gate signals V G1  to V G3  take the same high level value V GG  and are provided from a shift register or the like continuously such that the gate signal V G2  is turned on at an instant when the gate signal V G1  is turned off, and similarly the gate signal V G3  is turned on at an instant when the gate signal V G2  is turned off. 
     In the following, the operation of each thin-film transistor is described in detail with reference to an arbitrary thin-film transistor (for example, Q 1 ) in connection with FIG. 4. FIG. 4 shows waveform diagrams for explaining the operation of one thin-film transistor in FIG. 3. FIGS. 4(a)-4(e) show a data signal V D1 , a gate signal V G1 , a gate signal V G2 , a gate signal V G3 , and an output signal V O1 , respectively. 
     The operation of a thin-film transistor array of FIG. 3 in the periods is the same as that of FIG. 1 except the gate signal changing periods where the feed-through phenomenon occurs. Therefore, the following description will be made only with respect to the gate signal changing periods. 
     (1) Operation at t 2   
     A pulse b 11  of the gate signal V G1  for the thin-film transistor Q 1  falls at t 2 , so that the output signal V O1  instantly drops (by ΔV) correspondly due to the feed-through phenomenon via the gate-source capacitance C GS1 . 
     On the other hand, a pulse b 21  of the gate signal V G2  for the adjacent thin-film transistor Q 2  rises at this moment. This potential rise of the pulse b 21  is transmitted to the output side of the thin-film transistor Q 1  via the feed-through correction capacitance C F12 . Because the high level value V GG  of the gate signal V G2  is equal to that of the gate signal V G1 , the output signal is increased, via the feed-through correction capacitance C F12 , by the same amount as the voltage drop caused by the fall of the gate signal V G1 . 
     Accordingly, the output signal V O1  is substantially kept at the output high-level peak V H , except an instant voltage drop at t 2 . In other words, the relation &#34;(output high level V OH )=(output high-level peak V H )&#34; is established substantially. A waveform of V O1  in this period is denoted by d 1  in FIG. 4(e). 
     (2) Operation at the Time t 3   
     The pulse b 21  of the gate signal V G2  for the thin-film transistor Q 2  falls at t 3 , so that the output signal V 01  drops instantly through the feed-through correction capacitance C F12 . 
     On the other hand, a pulse b 31  of the gate signal V G3  for the thin-film transistor Q 3  rises at this moment t 3 . The rise of the pulse b 31  is transmitted to the output side of the thin-film transistor Q 1  through the feed-through correction capacitance C F13 . Accordingly, the output signal V O1  is returned to the output high-level peak V H  in the same manner as at t 2 . 
     (3) Operation from t 4  to t 5   
     The pulse b 31  of the gate signal V G3  falls at the time t 4 , so that the fall of the pulse b 31  is transmitted to the output side of the thin-film transistor Q 1  through the feed-through correction capacitance C F13  to thereby reduce the output signal V O1 . 
     A gate signal rise at t 4  and a feed-through correction capacitance for transmitting the rise of the gate signal to the thin-film transistor Q 1  are required to cancel the voltage drop of the output signal. Since such a gate signal and feed-through correction capacitance are not provided in FIG. 3, the voltage drop of the output signal is not canceled in this case. This explains the fact that the output signal V O1  stays dropped by ΔV in a period from t 4  to t 5  in FIG. 4(e). The reason why the output signal is left in the drop state in this period will be described later. 
     (4) Operation from t 5  to t 6   
     A pulse b 12  of the gate signal V G1  rises at the time t 5 , so that the output voltage V O1  increases by ΔV due to the feed-through phenomenon via the gate-source capacitance C GS1 . 
     However, this time, since the value of the data signal V D1  is zero while the pulse b 12  exists, the output signal V O1  which has once increased is reduced to zero rapidly (waveform c 2 ). This state of zero voltage of the output signal is kept until the time t 6 . 
     (5) Operation at t 6  and at t 7   
     The output signal V O1  instantly drops but is immediately returned by the effect of the feed-through correction capacitance in the same manner as at t 2  and t 3 . Consequently, the value of the output signal V O1  is kept zero (waveform d 2  in FIG. 4(e)). 
     (6) Operation at and after t 8   
     At the time t 8  a pulse b 32  of the gate signal V G3  falls. At this moment t 8 , the output signal V O1  drops corresponding to the fall of the pulse b 32  in the same manner as at t 4 , and there is nothing to cancel the drop. 
     Accordingly, the output signal changes after t 8  in the similar manner as after the time t 4  in the conventional example shown in FIG. 2 (waveform c 3 ). That is, the value of the output signal instantly decreases by ΔV and then increases gradually to be ultimately settled to the threshold voltage V th  of the thin-film transistor Q 1 . 
     The output signal V O1  obtained as the result of the aforementioned operation is different, in the following points, from the output signal obtained in the prior art. 
     (1) The output high level V OH  coincides with the output high-level peak V H . Accordingly, there is no necessity of establishing the data signal V D1  made higher in anticipation of the drop ΔV due to the feed-through phenomenon. 
     (2) The output low level V OL  is kept zero, and hence stabilized. Accordingly, errors are reduced even when the thin-film transistor array is used in an image processing device or the like to attain a tonal feature. 
     In the prior art, on the contrary, the output low level V OL  is equal to the threshold voltage V th  of the thin-film transistor, and hence it changes widely, that is, is not stable during the operation. 
     (3) The period in which the output signal is kept at a predetermined value by compensation of the drop of the output signal due to the feed-through phenomenon can be determined by the pulse width of the gate signals and the number of the feed-through correction capacitances connected to the thin-film transistor of interest. 
     In the case of the configuration shown in FIG. 3, as shown in FIG. 4(e), a period of two pulse widths is added by connection of the two feed-through correction capacitances, so that in an approximate period of three pulse widths the output signal is held at V OH . 
     The length of this period is determined in consideration of the time required to complete an operation to be conducted by utilization of the output high level V OH  or output low level V OL . It is unnecessary to cancel the voltage drop after the completion of the operation. This is the reason why the voltage drop is not compensated for in the periods from t 4  to t 5  and after t 8 . 
     FIG. 5 is a diagram showing a specific embodiment of the present invention. In FIG. 5: Q represents thin-film transistors which form a thin-film transistor array; C L , load capacitances; C F , feed-through correction capacitances; G 1  to G M , gate lines; G M+1  to G M+H-1 , dummy gate lines; and D 1  to D n , data lines. 
     FIG. 5 shows an example of a thin-film transistor array composed of M blocks each containing n thin-film transistors Q controlled by a gate signal supplied from one gate line. Therefore, M gate lines G 1  to G M  are provided in this embodiment. 
     The period during which the voltage drop due to the feed-through phenomenon is compensated for is established to be a period of H gate signal pulses. Therefore, feed-through correction capacitances C F  are respectively connected between one block and H-1 succeeding gate lines. 
     Blocks at the end portion of the array have a shortage of succeeding gate lines. To solve this problem, the last block, for example, is connected to H-1 dummy gate lines via the feed-through correction capacitances C F .