Abstract:
A digital control switching regulator of the invention ON/OFF-controls switching elements by digital-controlled pulse width modulation signals and converts an input voltage to a desired output voltage. The switching regulator includes an input voltage detection circuit that includes: a voltage dividing circuit outputting a divided voltage of the input voltage; a comparator section comparing the divided voltage of the input voltage with a first reference voltage and a second reference voltage and outputting a first comparison signal and a second comparison signal indicating comparison results; and a control section controlling a dividing ratio of the voltage dividing circuit based on the first comparison signal and the second comparison signal to obtain the predetermined divided voltage, thereby outputting an input voltage digital signal corresponding to the input voltage. The input voltage digital signal controls controller coefficients for use in the digital control.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a switching regulator that performs voltage conversion by switching with a pulse width modulation signal (hereinafter referred to as a PWM signal), and in particular to a digital control switching regulator having an input voltage detection circuit and suited for control with a digital signal. 
         [0003]    2. Description of the Related Art 
         [0004]    In switching regulators in general, controller coefficients of a voltage conversion circuit are desired to be set at optimum values corresponding to variation of an input voltage and a load current. For carrying out the controller coefficient optimization, a control mode made by an analogue circuit has a problem in that the analogue circuit requires preparation of a hardware circuit device corresponding to setting values of the controller coefficients, and such a circuit is typically complicated and large-sized. 
         [0005]    Patent Document 1 discloses a switching regulator in a digital control mode to provide a technology to avoid the enlarged circuit size.  FIG. 8  shows an example of construction of a conventional digital control switching regulator, which is disclosed in Patent Document 1. 
         [0006]    Referring to  FIG. 8 , input ac power AC is, through an input filter  21 , fed to a rectifying and smoothing circuit  22  composed of a full-wave rectifying diode circuit  23  and a capacitor Ci, and supplied to a transformer unit  24  with a switching circuit. The transformer unit  24  with a switching circuit performs ON/OFF control by a switching element QN on the supplied power from the rectifying and smoothing circuit  22 . The ON/OFF output is coupled with an output circuit  26  through a transformer  25 . The output circuit  26  consisting of diodes D 1 , D 2 , inductor L, and capacitor Co converts the switching output that is supplied by the transformer unit  24  with a switching circuit to a dc voltage and outputs the converted output. The output voltage Vout is supplied to a load circuit  8 . 
         [0007]    The output from the output circuit  26  is taken out as an output voltage analogue signal AS 1 , and the output from an output current detection circuit  27  is taken out as an output current analogue signal AS 2 . The output voltage analogue signal AS 1  and the output current analogue signal AS 2  are fed to a digital control unit  28 . A control output from the digital control unit  28  is fed to the switching element QN, a component of the transformer unit  24  with a switching circuit. The switching element QN operates to determine a duty ratio, a ratio of ON time to OFF time in a switching period. 
         [0008]    The digital control unit  28  converts the input signals of the output voltage analogue signal AS 1  and the output current analogue signal AS 2  into an output voltage digital signal and an output current digital signal, and executes operation of a command value for determining the duty ratio of the transformer unit  24  with a switching circuit based on the output voltage digital signal and the output current digital signal together with input voltage information or load terminal voltage information. The input voltage information or the load terminal voltage information is estimated from the output voltage digital signal and the output current digital signal. 
         [0009]    The digital control unit  28  generates pulses based on the command value obtained by the operation and controls switching operation of the transformer unit  24  with a switching circuit by the fed pulses, thereby controlling an output voltage and an output current. 
         [0010]    The input voltage information necessary for executing the command value operation is estimated by the following formulas (1), (2), and (3). An equation in a discrete variable system applied to a digital processing in  FIG. 8  is represented by Formula (1) below: 
         [0000]      [Formula 1] 
         [0000]        Vi ( n −1)= L[i ( n )− i ( n− 1)]/ Tc+Vo ( n− 1)  (1)
 
         [0000]    wherein Vi(n) is a mean voltage between a time (n−1) and a time n at a position indicated in the output circuit  26  in  FIG. 8 , L is an inductance, i(n) and i(n−1) are inductor current values at a time n and a time (n−1), respectively, Tc is a sampling period, and Vo(n−1) is an output voltage at a time (n−1). 
         [0011]    Provided the sampling period Tc be k times the switching period T (k is an integer) and an ON time duration of the switch be Ton in the switching period T, the relation represented by the following Formula (2) holds between the mean voltage Vi(n−1) and the input voltage V(n−1). 
         [0000]      [Formula 2] 
         [0000]        Vi ( n= 1)= k·T on· V ( n− 1)/ Tc   (2)
 
         [0000]    From Formula (1) and Formula (2), an actual current i(n) at the time n is given by the following Formula (3). 
         [0000]      [Formula 3] 
         [0000]        i ( n )= i ( n− 1)+ Tc·[k·T on· V ( n− 1)/ Tc−Vo ( n− 1)]/ L   (3)
 
         [0012]    Thus, Patent Document 1 states that the optimum control can be carried out corresponding to variation of an input voltage and an output current by operational estimation of the input voltage based on the formulas (1), (2), and (3) using the detected values of output voltage analogue signal AS 1  and output current analogue signal AS 2 .
   [Patent Document 1] WO97/50165.   
 
         [0014]    The above-mentioned conventional digital control switching regulator, however, has the problems as follows. 
         [0015]    The digital control unit  28  performs the control by executing an operation for the command value to determine the duty ratio of the switching regulator based on the detected values of output voltage analogue signal AS 1  and output current analogue signal AS 2 . However, since the input voltage information used for executing the operation is an estimated value based on the output voltage and the output current, there is a problem of causing an error. An inductance value, which is necessary for the estimation operation, is generally decided by the user side and thus, an uncertain factor. Since the control is conducted by the operation that uses an estimated value and an uncertain factor, the digital control switching regulator cannot perform optimum control. 
       SUMMARY OF THE INVENTION 
       [0016]    In view of the above-described problems, it is an object of the present invention to provide a digital control switching regulator that performs optimum control based on input voltage information by means of provision of an input voltage detection circuit that accurately detects an input voltage thereby avoiding detection of an inductance value and an output current value. 
         [0017]    In order to accomplish the above object, a digital control switching regulator of the present invention comprises an input voltage detection circuit that includes: a voltage dividing circuit outputting a divided voltage of the input voltage; a comparator section comparing the divided voltage with a first reference voltage and a second reference voltage and outputting comparison signals indicating comparison results; and a control section controlling a dividing ratio of the voltage dividing circuit based on the comparison signals to obtain the predetermined divided voltage thereby outputting an input voltage digital signal that indicates a magnitude of the input voltage, the input voltage digital signal controlling controller coefficients for use in the digital control. 
         [0018]    The voltage dividing circuit comprises a resistance array having variable resistance circuits and a resistance element, the both provided between the input voltage and a ground potential, the voltage dividing circuit outputting a divided voltage of the input voltage from the resistance array. The comparator section comprises a first reference voltage source and a second reference voltage source, and a first comparison circuit and a second comparison circuit comparing the divided voltage with the first reference voltage and with the second voltage, respectively, to output the comparison signals. The control section controls the dividing ratio of the divided voltage based on the comparison signals for setting the divided voltage to lie between the first reference voltage and the second reference voltage, and generates the input voltage digital signal depending on the dividing ratio. 
         [0019]    The input voltage detection circuit further comprises a timer circuit setting a detection period for detecting the input voltage 
         [0020]    The resistance array comprises a series-connected circuit of a first variable resistance circuit, a second variable resistance circuit, and the resistance element. The voltage dividing circuit further comprises a switching element that is series-connected to the resistance array. The first variable resistance circuit and the second variable resistance circuit each comprises a plurality of series-connected pairs of a resistance element and a switch, the both being connected in parallel with each other, and the resistance element having a weighted resistance value. Each of the switches of the first variable resistance circuit and corresponding member of the switches of the second variable resistance circuit are complementarily ON/OFF-controlled by the input voltage digital signal. 
         [0021]    Embodiments of a digital control switching regulator of the present invention obtains accurate input voltage information by the input voltage detection circuit without detection of an inductance value and an output current value, thereby performing optimum control based on the input voltage information. As an additional effect, low power consumption is achieved by cutting off the current path in the voltage dividing circuit that composes the input voltage detection circuit except for the time of detection operation for the input voltage. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0022]      FIG. 1  shows an example of construction of a digital control switching regulator according to the present invention; 
           [0023]      FIG. 2  shows an embodiment example of an input voltage detection circuit of a digital control switching regulator according to the present invention; 
           [0024]      FIGS. 3(   a ) and  3 ( b ) show an embodiment example of resistance array composing an input voltage detection circuit in a digital control switching regulator of the present invention; 
           [0025]      FIG. 4  shows an embodiment example of resistance array in the case of four bits composing an input voltage detection circuit in a digital control switching regulator of the present invention; 
           [0026]      FIG. 5  shows transition of states in detection operation of an input voltage detection circuit in an embodiment example of digital control switching regulator of the present invention; 
           [0027]      FIG. 6  shows a relationship between a reference voltage and resolution of an input voltage detection circuit in an embodiment example of digital control switching regulator of the present invention; 
           [0028]      FIG. 7  shows an example of optimization of controller coefficients in a digital control circuit in an embodiment example of digital control switching regulator of the present invention; and 
           [0029]      FIG. 8  shows an example of construction of a conventional digital control switching regulator. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0030]    Some preferred embodiments of the digital control switching regulator according to the present invention will be described in the following with reference to the accompanying drawings. 
       Example 1 
       [0031]      FIG. 1  is a block diagram showing a construction of a digital control switching regulator in accordance with embodiments of the invention. Parts that are similar to those in the construction of the conventional switching regulator shown in  FIG. 8  are given the same symbols and detailed description is omitted. 
         [0032]    The example of the digital control switching regulator of  FIG. 1  has a construction in a voltage mode to convert an input voltage Vin into an output voltage Vout by controlling switching elements with a PWM signal. The digital control switching regulator comprises an input voltage detection circuit  1 , a subtractor  2 , an ND convertor circuit  3 , a digital control circuit  4 , a digital PWM circuit  5 , an output circuit  6  composed of a driving circuit  9  and a pair of switching elements QP and QN that are ON/OFF-controlled by the driving circuit  9 , and a smoothing circuit  7  composed of an inductor L and a capacitor Co. The symbol Vin represents a power source for inputting an input voltage Vin (the same symbol Vin is used for the input voltage and for the input power source) to the digital control switching regulator. The load circuit  8  is a load on the switching regulator. 
         [0033]    The input voltage detection circuit  1  as shown in  FIG. 1  is provided with a voltage dividing circuit  10 , a comparator section  11 , and a control section  12 , and outputs a binary input voltage digital signal Vin &lt;m:0&gt; that is converted from the detected input voltage Vin, in which m:0 represents 2 m  to 2 0 . The subtractor circuit  2  generates and outputs an error voltage Ve between a detected value of the output voltage Vout that is to be fed back and a reference voltage Vref, which is a target value. Here, the detected value of the output voltage Vout can be the detected output voltage itself, a divided output voltage, or a level-shifted output voltage and thus, the error voltage Ve can be (Vref−Vout), (Vref−K1*Vout), or (Vref−(Vout−K2)), wherein K1 and K2 are positive constants. The A/D convertor circuit  3  outputs a binary digital error signal e[n] that is converted from the error voltage Ve, in which [n] means that the signal is a value at an n-th switching period. The digital control circuit  4  executes operation and outputs a duty command signal d[n] for determining a duty ratio of a PWM signal by an operation according to a scheme of PID control (proportional-integral-and-derivative control) or PI control (proportional-and-integral control) based on the inputted digital error signal e[n] and the inputted input voltage digital signal Vin &lt;m:0&gt;. The digital PWM circuit  5  generates and outputs a PWM signal based on an inputted duty command signal d[n]. The output circuit  6  conducts ON/OFF control of the switching elements QP and QN according to the PWM signal. The smoothing circuit  7  makes the output from the output circuit  6  smooth and generates an output voltage Vout, which is supplied to the load circuit  8 . 
         [0034]      FIG. 2  shows an example of circuit construction of the input voltage detection circuit  1  according to embodiments of the invention. The input voltage detection circuit  1  as shown in  FIG. 2  comprises a voltage dividing circuit  10 , a comparator section  11 , and a control section  12 . 
         [0035]    The voltage dividing circuit  10  includes a series-connected circuit composed of a resistance array  17  and the switching element QS between an input voltage Vin and the ground potential GND, and outputs a divided voltage Vx from the resistance array  17 . 
         [0036]    The comparator section  11  includes two reference voltage sources for outputting two reference voltages Vref 1  and Vref 2 , and two comparator circuits  13  and  14 . The comparator circuit  13  compares the inputted divided voltage Vx with the reference voltage Vref 1  and outputs a compared signal a, and the comparator circuit  14  compares the inputted divided voltage Vx with the reference voltage Vref 2  and outputs a compared signal b. 
         [0037]    The control section  12  includes a control circuit  15  (which is a state machine) and a timer circuit  16 . The control circuit  15  controls a resistance value of the resistance array  17  of the voltage dividing circuit  10  with a binary digital signal based on the inputted comparison signals a and b so that the divided voltage Vx of the input voltage Vin has a value between the reference voltage Vref  1  and the reference voltage Vref 2 , and outputs a binary signal of input voltage digital signal Vin&lt;m:0&gt;. 
         [0038]    The timer circuit  16  outputs a period signal Timeup for controlling start and stop of detection operation of the input voltage Vin. Based on the period signal Timeup, the control circuit  15  outputs a gate signal Ng to ON/OFF control the switching element QS of the voltage dividing circuit  10 . On a time of detection operation of the input voltage, the gate signal Ng is made at the Hi (high) level to turn ON the switching element QS and produce electric current flow in the voltage dividing circuit  10  generating the divided voltage Vx. On a time of stopping the detection operation, the gate signal Ng is made at the Lo (low) level to turn OFF the switching element QS and cut off the electric current flow in the voltage dividing circuit  10  achieving low power consumption. 
         [0039]      FIGS. 3(   a ) and  3 ( b ) show an example of circuit construction of the resistance array  17  according to the invention. The resistance array  17  as shown in  FIG. 3(   a ) is composed of a variable resistance circuit R 2 , a variable resistance circuit R 1 , and a resistance element R 0  series connected between connection terminals Vp and Vn, and outputs a divided voltage Vx from the node between the variable resistance circuit R 2  and the variable resistance circuit R 1 . 
         [0040]    The divided voltage Vx in the voltage dividing circuit  10  of  FIG. 3(   a ) is given by the following Formula (4), wherein the ON resistance of the switching element QS is assumed negligible, and the resistance values are represented by the same symbols as those of the variable resistance circuits and the resistance element. 
         [0000]    
       
         
           
             
               
                 
                   [ 
                   
                     Formula 
                      
                     
                         
                     
                      
                     4 
                   
                   ] 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   Vx 
                   = 
                   
                     
                       
                         
                           R 
                            
                           
                               
                           
                            
                           0 
                         
                         + 
                         
                           R 
                            
                           
                               
                           
                            
                           1 
                         
                       
                       
                         
                           R 
                            
                           
                               
                           
                            
                           0 
                         
                         + 
                         
                           R 
                            
                           
                               
                           
                            
                           1 
                         
                         + 
                         
                           R 
                            
                           
                               
                           
                            
                           2 
                         
                       
                     
                      
                     Vin 
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
         [0041]    The input voltage Vin is represented by the following Formula (5) using the Formula (4). 
         [0000]    
       
         
           
             
               
                 
                   [ 
                   
                     Formula 
                      
                     
                         
                     
                      
                     5 
                   
                   ] 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   Vin 
                   = 
                   
                     
                       
                         
                           R 
                            
                           
                               
                           
                            
                           0 
                         
                         + 
                         
                           R 
                            
                           
                               
                           
                            
                           1 
                         
                         + 
                         
                           R 
                            
                           
                               
                           
                            
                           2 
                         
                       
                       
                         
                           R 
                            
                           
                               
                           
                            
                           0 
                         
                         + 
                         
                           R 
                            
                           
                               
                           
                            
                           1 
                         
                       
                     
                      
                     Vx 
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0042]    Formula (5) shows that the input voltage Vin can be obtained by controlling the variable resistance values R 1  and R 2  when the divided voltage Vx and the resistance value R 0  are fixed. 
         [0043]      FIG. 3(   b ) shows an example of detailed circuit construction of the resistance array  17 . The resistance array  17  of  FIG. 3(   b ) is composed of a variable resistance circuit R 2 , a variable resistance circuit R 1 , and a resistance element R 0  connected in series between the connection terminals Vp and Vn. Each of the variable resistance circuits R 2  and R 1  is composed of series-connected pairs of a resistance element and a switch that are parallel-connected. Those resistance elements have weighted resistance values r, 2r, . . . , 2 m r, wherein r is a resistance value of the resistance element R 0 . Those switches can be semiconductor switching elements such as PMOSFETs. 
         [0044]    Each of the switches s 20  to s 2   m  of the variable resistance circuit R 2  is ON/OFF controlled by the binary input voltage digital signal Vin&lt;m:0&gt; outputted from the control circuit  15 ; and each of the switches s 10  to s 1   m  of the variable resistance circuit R 1  is ON/OFF controlled by the binary input voltage digital signal Vin &lt;m:0&gt; that is outputted from the control circuit  15  and inverted by invertors INV 0  to INVm. Two switches s 2   i  and s 1   i  (i=0, 1, . . . , m) having the same weighting factor in the variable resistance circuit R 2  and the variable resistance circuit R 1  are ON/OFF-controlled in a complementary manner, which means that one of the switches s 2   i  and s 1   i  is in the ON state, the other is in the OFF state. In the ON state of the switch, the resistance element is short-circuited (the ON resistance of the semiconductor switching element is assumed negligible), and in the OFF state of the switch, the resistance element has the weighted resistance value. 
         [0045]    Thus, a resistance value of the resistance circuit of series-connected variable resistance circuit R 2  and variable resistance circuit R 1  can be variably controlled by combining ON and OFF states of the switches in the variable resistance circuits R 2  and R 1 . 
         [0046]    Next, the operation principle of the resistance array  17  is described in the following referring to  FIG. 4 . The construction example of  FIG. 4  is for a case of the input voltage digital signal of 4 bits, represented by Vin &lt;3:0&gt; (m=3) and controlled by four digital signal lines. In the case of four bits, weighted resistance values of the resistance elements composing the variable resistance circuit R 2  are 8r (2 3 r), 4r (2 2 r), 2r (2 1 r), and r (2 0 r); and weighted resistance values of the resistance elements composing the variable resistance circuit R 1  are, as same as those in the variable resistance circuit R 2 , 8r (2 3 r), 4r (2 2 r), 2r (2 1 r), and r (2 0 r). The input voltage digital signal Vin&lt;3:0&gt; is fed to the switches s 23  to s 20  of the variable resistance circuit R 2 , and via the invertors INV 3  to INV 0 , fed to the switches s 13  to s 10  of the variable resistance circuit R 1 . The switches s 23 , s 22 , s 21  and s 20  of the variable resistance circuit R 2  are controlled by the input voltage digital signals Vin &lt;3&gt;, Vin &lt;2&gt;, Vin &lt;1&gt;, and Vin &lt;0&gt;, and the switches s 13 , s 12 , s 11  and s 10  of the variable resistance circuit R 1  are controlled by the input voltage digital signals Vin &lt;3&gt;, Vin &lt;2&gt;, Vin &lt;1&gt;, and Vin &lt;0&gt; after inverted by the invertors INV 3 , INV 2 , INV 1 , and INV 0 . 
         [0047]    Here, such a situation is considered that the switch is in the ON state for the input voltage digital signal Vin &lt;m:0&gt;=0 (a Lo level) and the switch is in the OFF state for the input voltage digital signal Vin &lt;m:0&gt;=1 (a Hi level). 
         [0048]    In the case the input voltage digital signal Vin &lt;3:0&gt;=1000, for example, the states of the switches of the weighted resistance elements 8r, 4r, 2r, and r of the variable resistance circuit R 2  are s 23 : OFF, s 22 : ON, s 21 : ON, and s 20 : ON, resulting in the variable resistance value R 2 =8r. On the other hand, the states of the switches of the weighted resistance elements 8r, 4r, 2r, and r of the variable resistance circuit R 1  are s 13 : ON, s 12 : OFF, s 11 : OFF, and s 10 : OFF, resulting in the variable resistance value of R 1 =7r. Therefore, the divided voltage Vx and the input voltage Vin turn out to be as shown by the following Formulas (6) and (7). 
         [0000]    
       
         
           
             
               
                 
                   [ 
                   
                     Formula 
                      
                     
                         
                     
                      
                     6 
                   
                   ] 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   Vx 
                   = 
                   
                     
                       
                         
                           r 
                           + 
                           
                             7 
                              
                             r 
                           
                         
                         
                           r 
                           + 
                           
                             7 
                              
                             r 
                           
                           + 
                           
                             8 
                              
                             r 
                           
                         
                       
                        
                       Vin 
                     
                     = 
                     
                       
                         8 
                         16 
                       
                        
                       Vin 
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
             
               
                 
                   [ 
                   
                     Formula 
                      
                     
                         
                     
                      
                     7 
                   
                   ] 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   Vin 
                   = 
                   
                     
                       16 
                       8 
                     
                      
                     Vx 
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
         [0049]    Likewise, in the case Vin &lt;3:0&gt;=1001, the states of the switches of the weighted resistance elements 8r, 4r, 2r and r of the variable resistance circuit R 2  are s 23 : OFF, s 22 : ON, s 21 : ON, s 20 : OFF, resulting in the variable resistance value of R 2 =9r. On the other hand, the states of the switches of the weighted resistance elements 8r, 4r, 2r and r of the variable resistance circuit R 1  are s 13 : ON, s 12 : OFF, s 11 : OFF and s 10 : ON, resulting in the variable resistance value of R 1 =6r. Therefore, the divided voltage Vx and the input voltage Vin turn out to be as shown by the following Formulas (8) and (9). 
         [0000]    
       
         
           
             
               
                 
                   [ 
                   
                     Formula 
                      
                     
                         
                     
                      
                     8 
                   
                   ] 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   Vx 
                   = 
                   
                     
                       
                         
                           r 
                           + 
                           
                             6 
                              
                             r 
                           
                         
                         
                           r 
                           + 
                           
                             6 
                              
                             r 
                           
                           + 
                           
                             9 
                              
                             r 
                           
                         
                       
                        
                       Vin 
                     
                     = 
                     
                       
                         7 
                         16 
                       
                        
                       Vin 
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
             
               
                 
                   [ 
                   
                     Formula 
                      
                     
                         
                     
                      
                     9 
                   
                   ] 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   Vin 
                   = 
                   
                     
                       16 
                       7 
                     
                      
                     Vx 
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
         [0050]    As described above, fixing the divided voltage Vx and the resistance value R 0 , the input voltage Vin can be obtained by controlling the variable resistance values R 1  and R 2 . More specifically, for fixed values of divided voltage Vx and resistance value R 0 , resistance values of the variable resistance circuit R 1  and the variable resistance circuit R 2  are controlled by binary digital signals so that the divided voltage Vx satisfies an inequality: reference voltage Vref 2 &lt;divided voltage Vx&lt;reference voltage Vref 1 . 
         [0051]    Digital values of the digital signals are taken as the input voltage digital signal Vin&lt;m:0&gt;. Thus, the input voltage Vin can be converted to the input voltage digital signal Vin &lt;m:0&gt;. 
         [0052]    Next,  FIG. 5  shows transition of states illustrating operation of a control section  12  of the input voltage detection circuit  1  in the embodiment example of digital control switching regulator of the invention. 
         [0053]    When an enable signal Enable is set to the Lo level, the control circuit  15  (see also  FIG. 2 ) is in a standby state, in which the input voltage digital signal Vin &lt;m:0&gt; is set to an initial value 0, and the gate signal Ng is set to the Lo level. 
         [0054]    Upon transition of the enable signal Enable to the Hi level, the control circuit  15  shifts to State 1, in which the gate signal Ng changes to the Hi level, detection operation of the input voltage Vin starts, and a divided voltage Vx determined by the Formula (4) is outputted. 
         [0055]    In the condition of State 1, when the compared signal a=Lo level, and the compared signal b=Lo level, in which divided voltage Vx&lt;reference voltage Vref 1  and divided voltage Vx&lt;reference voltage Vref 2 , the control circuit  15  transitions to Decrement state, and repeats decrement operation (Vin&lt;m:0&gt;−1) on the input voltage digital signal Vin&lt;m:0&gt;. When the compared signals change to compared signal a=Lo level and compared signal b=Hi level, in which reference voltage Vref 2 &lt;divided voltage Vx&lt;reference voltage Vref 1 , the control circuit  15  transitions to Hold state and holds the input voltage digital signal Vin&lt;m:0&gt;. 
         [0056]    In the Hold state, the gate signal Ng is at the Lo level. The operation for detecting the input voltage Vin is halted and the electric current between the input voltage Vin and the ground potential GND is cut off to achieve low power consumption. 
         [0057]    When the compared signal a=Hi level, and the compared signal b=Hi level in the State 1, in which reference voltage Vref 1 &lt;divided voltage Vx and reference voltage Vref 2 &lt;divided voltage Vx, the control circuit  15  transitions to Increment state and repeats increment operation (Vin&lt;m:0&gt;+1) on the input voltage digital signal Vin&lt;m:0&gt;. As in the Decrement state, when the compared signals change to compared signal a=Lo level and compared signal b=Hi level, in which reference voltage Vref 2 &lt;divided voltage Vx&lt;reference voltage Vref 1 , the control circuit  15  transitions to the Hold state and holds the input voltage digital signal Vin&lt;m:0&gt;. 
         [0058]    When the compared signal a=Lo level and the compared signal b=Hi level in the State 1, in which reference voltage Vref 2 &lt;divided voltage Vx&lt;reference voltage Vref 1 , the control circuit  15  directly transitions to the Hold state and holds the input voltage digital signal Vin&lt;m:0&gt; at that moment. 
         [0059]    When the period signal Timeup from the timer circuit  16  changes to the Hi level, the Hold state is forced to transition to the State 1 again to resume the detection operation of the input voltage Vin. Thus, the input voltage Vin is periodically detected during operation of the switching regulator. When the period signal Timeup is made equal to the switching period T, for example, the input voltage Vin is detected in a pulse-by-pulse scheme. 
         [0060]    When the enable signal Enable is connected commonly to an enable signal or a reset signal of the switching regulator, the first detection operation of the input voltage is executed at the start up of the switching regulator and the detection operation during the steady state operation of the switching regulator is conducted at every periodical times determined by the period signal Timeup. 
         [0061]    Next, the operation of the input voltage detection circuit  1  is described for a specific example in the following. In this example, input voltage Vin=6 V, reference voltage Vref 1 =1.01 V, reference voltage Vref 2 =0.99 V, and resistance of the resistance element in the voltage dividing circuit  10  R 0 =r (Ω). In the case the enable signal (Lo active) of the switching regulator is common to the enable signal Enable of the input voltage detection circuit  1 , the control circuit  15  is in the Standby state during the enable signal Enable is at the Lo level and the input voltage digital signal Vin&lt;m:0&gt; is set at the initial value 0 (zero). In the situation the switch of the variable resistance circuit R 2  is in the ON state for the input voltage digital signal Vin &lt;m:0&gt;=0 (a Lo level) and the switch is in the OFF state for the input voltage digital signal Vin &lt;m:0&gt;=1 (a Hi level), every switch of the variable resistance circuit R 2  is in the ON state according to the zero value of the input voltage digital signal Vin&lt;m:0&gt;, resulting in a resistance value of the variable resistance circuit R 2 =0 (Ω). 
         [0062]    Upon change of the enable signal Enable into the Hi level, the control circuit  15  transitions to the State 1. Since the resistance value of the variable resistance circuit R 2 =0 (Ω) at this moment, the divided voltage Vx=the input voltage=6 V. Because the reference voltage Vref 1 &lt;divided voltage Vx and the reference voltage Vref 2 &lt;the divided voltage Vx, the compared signals become the compared signal a=Hi level and the compared signal b=Hi level. The control circuit  15  transitions to Increment state and increases the input voltage digital signal Vin&lt;m:0&gt;. 
         [0063]    When the input voltage digital signal Vin&lt;m:0&gt; is increased, the resistance value of the variable resistance circuit R 2  increases and the resistance value of the variable resistance circuit R 1  decreases, thus, the divided voltage Vx decreases. The control circuit  15  repeats the increment operation and when the divided voltage Vx becomes to a value satisfying the condition: the reference voltage Vref 2 =0.99 V&lt;the divided voltage Vx&lt;the reference voltage Vref 1 =1.01 V, the control circuit  15  transitions to the Hold state. 
         [0064]    The digital signal for ON/OFF control of the switches in the variable resistance circuit R 2  is the input voltage digital signal Vin&lt;m:0&gt; and inputted to the digital control circuit  4  for controlling the PWM duty ratio of the switching regulator. 
         [0065]    In the input voltage detection circuit  1 , when the periodically changing period signal Timeup becomes to the Hi level, the control circuit  15  transitions to the State 1 holding the input voltage digital signal Vin&lt;m:0&gt;, and the operation for detecting the input voltage is repeated in the manner as described above. 
         [0066]    The resolution Vrs of the input voltage detection circuit  1  in the present invention is determined by the maximum value of the input voltage Vin and the bit number m of the input voltage digital signal Vin&lt;m:0&gt;. In an example of the maximum value of the input voltage Vin (max)=12 V and the bit number m=8, the resolution Vrs is given by the Formula (10). 
         [0000]    
       
         
           
             
               
                 
                   [ 
                   
                     Formula 
                      
                     
                         
                     
                      
                     10 
                   
                   ] 
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   Vrs 
                   = 
                   
                     
                       
                         Vin 
                          
                         
                           ( 
                           max 
                           ) 
                         
                       
                       
                         2 
                         m 
                       
                     
                     = 
                     
                       
                         12 
                         256 
                       
                       = 
                       
                         46.9 
                          
                         
                             
                         
                          
                         mV 
                       
                     
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
         [0067]    Thus, change of one LSB (least significant bit) of the input voltage digital signal Vin&lt;8:0&gt; changes the divided voltage Vx by 46.9 mV. 
         [0068]    The reference voltage Vref 1  and the reference voltage Vref 2  must be set to satisfy the inequality of Formula (11). 
         [0000]      [Formula 11] 
         [0000]        V ref1 −V ref2 &gt;Vrs   (11)
 
         [0069]    The detection operation of the input voltage detection circuit  1  is conducted through increment or decrement operation on the resistance value of the resistance array  17  so as to satisfy the relationship: the reference voltage Vref 2 &lt;divided voltage Vx&lt;reference voltage Vref 1 . Consequently, as shown in  FIG. 6 , at least one voltage value of the divided voltage Vx must exist between the reference voltage Vref 1  and the reference voltage Vref 2 . In an example of: the maximum input voltage Vin (max)=12 V, the divided voltage Vx=1 V, and the bit number m=8, the resolution turns out to be Vrs=46.9 mV according to the Formula (10). Thus, reference voltages of Vref 1 =1.03 V and Vref 2 =0.97 V are allowable reference voltage values satisfying Formula (11). 
         [0070]    The following describes a control method in the control circuit  4  according to the input voltage digital signal Vin&lt;m:0&gt; detected by the input voltage detection circuit  1  in the invention. The control can be performed by a digital operation of the PID operation. A discrete digital PID operation is generally represented by Formula (12). 
         [0000]      [Formula 12] 
         [0000]        d[n]=d[n− 1 ]+A·e[n]+B·e[n− 1 ]+C·e[n− 2]  (12)
 
         [0000]    wherein d[n] and d[n−1] are duty command signals at the present switching period and at one period before, respectively; e[n], e[n−1], and e[n−2] are digital error signals at the present switching period, at one period before, and at two period before, respectively; and A, B, and C are controller coefficients. 
         [0071]    The input voltage Vin in a switching regulator may vary during operation like in a battery input power. Accordingly, the controller coefficients that are set in the initial design are to be reset to optimum values. A digital control switching regulator of the invention performs the optimum control of the controller coefficients by the input voltage digital signal Vin&lt;m:0&gt; detected in the input voltage detection circuit  1 . 
         [0072]      FIG. 7  shows an example of a control method of the controller coefficients. As shown in  FIG. 7 , the controller coefficients A, B, and C are stored preliminarily in the control circuit  4  corresponding to the input voltage digital signal Vin&lt;m:0&gt; in a table format. Controller coefficients A, B, and C are selected corresponding to the input voltage digital signal Vin&lt;m:0&gt; that is detected at every periodical time of the period signal Timeup, and operation control is conducted according to Formula (12) to perform optimum control responding to the variation of the input voltage Vin. 
         [0073]    The digital control of the digital control circuit  4  can be performed by a digital PI control in the same manner as the digital PID control described above. A discrete digital PI operation is generally represented by Formula (13). 
         [0000]      [Formula 13] 
         [0000]        d[n]=d[n− 1 ]+A·e[n]+B·e[n− 1]  (13)
 
         [0000]    wherein d[n] and d[n−1] are duty command signals at the present switching period and at one period before, respectively; e[n] and e[n−1] are digital error signals at the present switching period and at one period before, respectively; and A and B are controller coefficients. 
         [0074]    The controller coefficients A and B are preliminarily stored in the digital control circuit  4  in a table format as in  FIG. 7  corresponding to the input voltage digital signal Vin&lt;m:0&gt;. The controller coefficients A and B are selected that correspond to the input voltage digital signal Vin&lt;m:0&gt; detected at every periodical time of Timeup signal, and operation control is conducted according to Formula (13) performing an optimum control responding to variation of the input voltage Vin. 
         [0075]    As described previously, a digital control switching regulator of the invention comprises the input voltage detection circuit  1  and eliminates needs for detection of an output current value and an inductance value. An input voltage Vin is converted to an input voltage digital signal Vin&lt;m:0&gt;, which is used for controlling the controller coefficient of the digital control circuit  4  to the optimum value to perform optimum control responding to variation of the input voltage Vin. The input voltage detection circuit  1  is controlled by a gate signal Ng to cut off a current path in the voltage dividing circuit  10  when detection operation of the input voltage Vin is halted. Thus, low power consumption is also achieved. 
         [0076]    Although the present invention has been described relating to a preferred embodiment example, the invention is not limited to the example but wide variety of improvements and variations are possible as long as they do not deviate from the spirit and scope of the invention. 
         [0077]    This application is based on, and claims priority to, Japanese Patent Application No. 2010-049208, filed on Mar. 5, 2010, and Japanese Patent Application No. 2010-236393, filed on Oct. 21, 2010. The disclosure of each priority applications, in its entirety, including the drawings, claims, and the specification thereof, is incorporated herein by reference.