Abstract:
Digital mixers which permit mixing of asynchronous signals is constructed of Rapid Single Flux Quantum (RSFQ) logic elements. The logic elements may include an RSFQ non-destructive readout cell (NDRO), an RSFQ D flip-flop, an RSFQ XOR circuit, and an RSFQ T flip-flop. A binary tree arrangement of T flip-flops can be used to provide in-phase and quadrature phase-divided replicas of a reference signal. The mixing elements can be either an XOR circuit, a dual port NDRO circuit functioning as a multiplexer or an RS type NDRO functioning as an AND gate. The RSFQ logic elements utilize Josephson junctions which operate in superconducting temperature domains.

Description:
STATEMENT REGARDING FEDERALLY FUNDED RESEARCH  
       [0001]     This work was funded, at least in part, by ONR6.2D&amp;I contract number N00014-03-C-0082 and phase III SBIR Contract number N00014-03-C-0370, and contract number N00014-02-C-0005. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The invention described herein relates to the field of superconductivity, and more specifically relates to circuits and techniques for implementing digital quadrature mixers using Josephson junctions.  
         [0004]     2. Related Art  
         [0005]     Josephson junctions are quantum-mechanical circuit elements of superconducting devices. The Josephson effect in particular results from two superconductors acting to preserve long-range order across a barrier, such as an insulating barrier. With a thin enough barrier, the phase of the electron wave function in one superconductor maintains a fixed relationship with the phase of the wave function in another superconductor. This linking up of phases is called phase coherence.  
         [0006]     A Josephson junction is the interface between two superconducting materials separated by a non-superconducting barrier. A current may flow freely within the superconductors but the barrier prevents the current from flowing freely between them. However, a supercurrent may tunnel through the barrier depending on the quantum phase of the superconductors. The amount of supercurrent that may tunnel through the barriers is restricted by the size and substance of the barrier. The maximum value the supercurrent may obtain is called a critical current of the Josephson junction.  
         [0007]     Josephson junctions have two basic electrical properties. The first is that the junctions have inductive reactance. That is, similar to inductors, the voltage difference across the junction is related to the time rate of change of the current. The second is that a constant voltage across the junction will produce an oscillating current through the barrier, and vice versa. Thus, Josephson junctions convert a direct current voltage to an alternating current.  
         [0008]     A family of logic/memory devices were proposed using Josephson junctions the IEEE Transactions on Applied Superconductivity, Volume 1, Number 1, March 1991, by K. K. Likharev and V. K. Semenov in an article entitled, RSFQ Logic/Memory Family: A New Josephson junction Technology For Sub-Terahertz-Clock-Frequency Digital Systems. That article is hereby incorporated by reference in its entirety into specification of this application.  
         [0009]     RSFQ circuits are widely recognized as the fastest digital circuits in any electronic technology, and this is also true of RSFQ digital mixers. The digital mixers described in the present invention constitute the first practical circuits for the implementation of digital mixers in a complete RSFQ digital receiver system, and have been demonstrated for clock speeds up to 40 GHz.  
         [0010]     Prior art attempts at producing digital mixers in the superconducting domain required synchronism between an incoming signal and a reference signal.  
       BRIEF SUMMARY OF THE INVENTION  
       [0011]     The invention described herein is related to circuits and techniques for implementing digital mixers utilizing Josephson junction technology, which don&#39;t require synchronism between the incoming signal and a reference signal.  
         [0012]     The purpose of the invention is to provide a digital quadrature mixer, which overcomes the problems of the prior art. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]      FIG. 1  is an exemplary embodiment of an XOR based digital Mixer in accordance with one aspect of the invention.  
         [0014]      FIG. 2  is an exemplary embodiment of a streaming Mixer in accordance with one aspect of the invention.  
         [0015]      FIG. 3A  is a diagram of a dual port NDRO cell, which can be utilized for the multiplexer of  FIG. 2 .  
         [0016]      FIG. 3B  is a block diagram of the circuit of  FIG. 3A .  
         [0017]      FIG. 4  is a diagram of a digital Mixer utilizing an NDRO cell to perform AND functionality asynchronously.  
         [0018]      FIG. 5A  is a circuit diagram of a resettable T flip-flop used in connection with the circuits of  FIGS. 1, 2  and  4 .  
         [0019]      FIG. 6A  is a diagram of an RS-type NDRO cell used in the circuit of  FIG. 1 .  
         [0020]      FIG. 6B  is a Moore diagram of an RS-type NDRO cell used in  FIG. 6A .  
         [0021]      FIG. 7A  is a circuit diagram of an XOR cell used in  FIG. 1 .  
         [0022]      FIG. 7B  is a diagram of a Multiplexer/Demultiplexer cell used in the XOR cell of  FIG. 7B .  
         [0023]      FIG. 8A  is a circuit diagram of a D flip-flop used in the circuits of  FIGS. 1, 2  and  4 .  
         [0024]      FIG. 8B  is a Moore diagram of the circuit shown in  FIG. 8A .  
         [0025]      FIG. 9  is an exemplary layout of a digital I/Q Mixer illustrated in  FIG. 1 .  
         [0026]      FIG. 10  is an exemplary layout of a digital I/Q Mixer utilized in  FIG. 2 .  
         [0027]      FIG. 11  is an exemplary layout of a digital I/Q Mixer shown in  FIG. 4 .  
         [0028]      FIG. 12  is a block diagram of a correlation receiver using the streaming mixer in accordance with one aspect of the invention.  
         [0029]      FIG. 13  shows portions of the circuit of  FIG. 12  in more detail. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0030]     An important component of any digital receiver is a digital I/Q Mixer for converting narrowband (˜5 MHz) signals down from a few GHz. To achieve this goal with maximum efficiency the invention uses a circuit that is similar in principle to the Gilbert quadrature mixer. See article by B. Gilbert, “A Precise Four Quadrant Multiplier With Sub nanosecond Response,” IEEE. J. Solid-State Circuits, Vol. SC-3, pp. 365-373, Dec. 1968. The basic idea of this mixer is to use square waves as a local oscillator signal instead of sine waves. The mathematical representation of a square wave is G(t)=sign[sin(ω LO ·t)], where ω LO  is a local oscillator frequency. The digital version of such a mixer is comparably easy to implement in RSFQ in case of single-bit coding, such as at the output of a delta-sigma modulator.  
         [0031]     The first implementation of a square wave digital mixer in RSFQ is shown in  FIG. 1 . The right side of the device on the block diagram serves as a single-bit square wave generator with quadrature outputs. Although,  FIG. 1  is shown as a two channel I/Q Mixer, the principles if the invention apply to a single channel mixer as well. As shown, the binary tree of resettable T flip-flops creates two (I and Q) local oscillator signals with 90° relative phase shift. The T flip-flops control RS-type NDRO cells, which, in turn, create digital square waves turning on and off a stream of SFQ pulses. A modulated signal gets mixed with 90° shifted square waves in XOR cells, producing I channel and Q channel output products. An RS-type NDRO cell and a T flip-flop is used, instead of a T-type NDRO cell, in order to avoid a possible collision between the NDRO read-out pulse and reference pulse. Such a collision may cause a wrong phase shift between I and Q local oscillator signals. If such a problem occurs, the only way to correct it is by applying a RESET signal, and one would not want to do that too often. Despite its simple design, this version of the mixer has issues with timing, limiting its performance.  
         [0032]     To avoid this problem, we have designed a second novel mixer performing single-bit-stream XOR multiplication ( FIG. 2 ). In this case, we use the simple fact that A XOR 0=A and A XOR 1=  A . A Rapid Single-Flux-Quantum (RSFQ) D flip-flop with complementary outputs (DFFC) (schematics and optimal parameters are in Kirichenko et al., “A 4-bit Single Flux Quantum Decoder,” IEEE Transactions on Applied Superconductivity, Vol. 5, No. 2, p. 2857, June 1995), converts the modulated signal into a single-bit data stream along with its inverted (complementary) representation. Multiplexing direct and inverted data outputs to the proper channel, it performs digital Quadrature signal down-conversion. After the modulated signal passes through a D flip-flop with complementary outputs (DFFC), it becomes asynchronous. Multiplexing direct and inverted data outputs to the proper channel, we effectively perform digital I/Q signal down-conversion. The multiplexing is done by two multiplexer cells controlled by the same T flip-flop binary tree as in  FIG. 1 , providing a 90° phase shift between I and Q channels. Again this circuit can be applied to single channel mixing as well as to I/Q quadrature mixing.  
         [0033]     The multiplexer cell is shown in  FIG. 3 . This cell basically comprises a dual-port NDRO cell. From this cell, a designer can build either a demultiplexer by merging inputs A and B, or a multiplexer by merging outputs A and B. See article by Kirichenko et al., “A 4-bit Single Flux Quantum decoder,” IEEE Transactions on Applied Superconductivity, Vol. 5, No. 2, p. 2857, June 1995.  
         [0034]     We have designed and fabricated the  FIG. 3  version of the digital I/Q Mixer using the standard HYPRES 1 kA/cm 2  fabrication process. The same design was also converted to the standard HYPRES 4.5 kA/cm 2  fabrication process.  
         [0035]     The multiplexing is done by two 2×1 RSFQ switches. The basic switch cell shown in  FIG. 3A  comprises a dual-port RSFQ Non-Destructive Read-Out (NDRO) cell with merged outputs. Applying an SFQ pulse to the input “Set A” causes the switch to connect input terminal “In A” to the output terminal “Out A” and disconnect terminal “In B”. Applying an SFQ pulse to the input “Set B” causes the switch to connect input terminal “In B” to the output terminal “Out B” and disconnect terminal “In A”. The optimized parameters for the cell in  FIG. 3A  are in Table 1.  
                                         TABLE 1                           Optimized parameters for the dual-port NDRO cell, normalized to       reference values in the top row.            Crittcal                           current   0.125 mA   Inductance   2.54 pH   Bias current   0.125 mA               J1   2.94   L1   1.56   I1   1.92       J2   2.78   LQ1   0.60       J3   2.16   LQ2   1.22       J4   1.95   LJ1   0.03       J5   1.25   LJ4   0.04       J6   1.60   LJ5   0.06       J7   1.88   LJ6   0.29       J8   1.55   LJ7   0.50       J9   2.07   LJ8   0.01       J10   2.89   LJ9   0.51               LJ10   0.34                  
 
         [0036]     Both switches are controlled by a resettable T flip-flip binary tree. See description of T 1  cell in S. Polonsky, et al., “Single Flux Quantum T flip-flop and its possible applications”, IEEE trans. On Appl. Supercond., vol. 4, p. 9, 1994, for the schematics and optimal parameters of the resettable TFF. The TFF tree converts a periodic reference signal into a control sequence of the switches, effectively creating two 90-degree phase-shifted Local Oscillator square-wave signals of a half reference signal frequency.  
         [0037]      FIG. 4  is a diagram of a digital I/Q Mixer utilizing an NDRO cell to perform an AND function asynchronously. Like the other mixer designs, a reference clock drives a binary tree of T flip-flops with the outputs of the T flip-flop driving respective NDRO cells which perform an AND function with the data arriving from the delta-sigma modulator over a type D flip-flop.  
         [0038]     Each of the three mixers described heretofore have their advantages and drawbacks. The circuit shown in  FIG. 4 , employing an AND operation has a poor signal-to-noise ratio because of a DC component in the local oscillator. However, it is feasible for a multi-bit implementation.  
         [0039]     The digital I/Q Mixer employing XOR operation shown in  FIG. 1 , has good gain and a good signal-to-noise ratio but there is no obvious multi-bit implementation.  
         [0040]     The streaming I/Q Mixer shown in  FIG. 2 , takes care of timing and synchronization issues, but may be hard to design for multi-bit data streams. Thus, each of the three mixers described is preferred for a particular application.  
         [0041]     The XOR mixer shown in  FIG. 1 , utilizes a T flip-flop, an RS-type, NDRO, and XOR cell and a D flip-flop (single output).  
         [0042]     The streaming I/Q Mixer shown in  FIG. 2  utilizes the multiplexer shown in  FIG. 3  and a D flip-flop with complementary outputs.  
         [0043]     The AND gate mixer shown in  FIG. 4 , utilizes T flip-flops, a multiplexer, such as that shown in  FIG. 3 , and a D flip-flop with complementary outputs. Each of these elements utilized to construct the mixers described so far will now be described in more detail.  
         [0044]      FIG. 5  shows a circuit for construction of an SFQ resettable toggle flip-flop as used in the construction of the circuit of  FIG. 1 . The parameters for this schematic are found in the Polonsky article, S. Polonsky et al., “Single Flux, Quantum B Flip-flop and Its Possible Applications”, IEEE, vol. 4, no. 1, March 1994, p. 9.  
         [0045]     The normalized PSCAN units are normalized to 125 pA for junction critical currents in and bias current values I, and to 2.63 pA for inductance values L.  
         [0046]      FIG. 6A  is a diagram of an RS-type NDRO cell used in  FIG. 1 .  
         [0047]     This cell functions as a Non-Destructive Read-Out with a single bit memory. One can change the state of the NDRO by applying the Reset or Set inputs. If the cell is in state “1”, then the Read input pulse goes to the Output. If the cell is in state “0”, then the Read input pulse is prevented from going to the Output.  
         [0048]     The normalized PSCAN values for the circuit of  FIG. 6A  are as follows: J1=3.15, J2=2.19, J3=2.21, J4=2.63, J5=1.32, J6=2.34, J7=2.39, J8=2.54, J9=2.02, J10=2.13, I1=1.80, I2=2.42, I3=1.93, LQ1=0.16, LQ2=0.16, L1=1.37, L2=0.48, L3=0.10, L4=0.80, L5=0.53, L6=1.68, L7=0.66, L8=0.61, L9=0.32, LJ2=0.80, LJ3=0.49, LJ4=0.21, LJ5=0.16, LJ6=0.25, LJ7=0.19, XN=1.00.  
         [0049]      FIG. 7A  shows a circuit diagram of an XOR cell used in  FIG. 1 .  
         [0050]      FIG. 7B  is a diagram of a Multiplexer/Demultiplexer cell used in the XOR circuit of  FIG. 7A .  
         [0051]     This RSFQ logic circuit functions as a multiplexer or demultiplexer, combining two input pulse streams into a single output stream or conversely. This was described in the U.S. Pat. No. 5,982,219, invented by A. Kirichenko (1999).  
         [0052]     The normalized PSCAN values for the circuit of  FIG. 7B  are as follows: L1=4.51, L2=1.77, L3=0.37, L4=0.60, L5=0.30, L6=0.62, LC1=1.14, LC2=0.75.  
         [0053]      FIG. 8A  shows a circuit for an SFQ D flip-flop as used in the construction of the circuit of  FIGS. 1 and 4  in which the complementary output is not used, and in  FIG. 2  which uses the complementary output. If the data input is “1” (i.e., an SFQ pulse) then the True output gives “1” and the Complement gives “0”. If the data input is “0” (i.e., no SFQ pulse), then the True output gives “0” and the Complement gives “1”.  
         [0054]     The normalized PSCAN values for the circuit of  FIG. 8A  are as follows: I1=2.04, I2=4.45, I3=0.83, J2=1.41, J3=1.41, J4=1.96, J5=2.42, J6=2.94, J7=2.82, J8=2.43, J9=1.96, J10=1.00, L1=1.50, L2=0.30, L3=0.31, L4=0.74, L5=0.70, L6=2.28, L7=1.20, L8=1.20, L9=0.94, L10=2.00, L13=1.00, LJ2=0.08, LJ3=0.29, LJ4=0.19, LJ5=0.09, LJ7=0.45, LQ=0.23, LQ2=0.02.  
         [0055]      FIG. 8B  shows a Moore diagram of the D flip-flop used in  FIG. 1 .  
         [0056]      FIG. 9  is an exemplary layout of a digital I/Q Mixer of the type shown in  FIG. 1 .  
         [0057]      FIG. 10  is an exemplary layout of a digital I/Q Mixer of the type shown in  FIG. 2 .  
         [0058]      FIG. 11  is an exemplary layout of a digital I/Q Mixer of the type shown in  FIG. 4 .  
         [0059]      FIG. 12  is a block diagram of a correlation receiver using the streaming mixer of  FIG. 2  in accordance with one aspect of the invention.  
         [0060]     Turning to  FIG. 13 , Row analog RD input is applied to an analog digital converter (ADC) preferable to an oversampled delta modulator or delta sigma modulator. The output of the ADC is passed to a 5pl D flip-flop with complementary outputs and then to a multiplexer MUX. The output of the MUX is then passed to a claim of T flip-flops TFF 1 -TFF 13  in this example and the output (Digital Output) is taken from the last T flip-flop. The Digital Output is passed to another D flip-flop with complementary outputs to control the phase shift imported to a frequency reference by a string of inverters—T flip-flop (TFF  1 - 4 ) cells. The output of the last T flip-flop connects to the set/reset inputs of the multiplexer of the new streaming mixer.  
         [0061]     While various embodiments of the present invention have been illustrated herein in detail, it should be apparent that modifications and adaptations to those embodiments may occur to those skilled in the art without departing from the scope of the present invention as set forth in the following claims.