Abstract:
A ladder type clock network for reducing the skew of clock signals is provided. The clock network includes a buffer for buffering a clock signal, first delay units for delaying the output of the first buffer by a set time, second buffers connected to respective outputs of the first delay units, and second delay units connected to respective outputs of the second buffers. The first delay units and the second delay units consist essentially of the resistance and capacitance of lines through which the clock signal propagates. Accordingly, the skew of the internal clock signals is reduced, and internal clock signals having a stable duty with respect to variations in a semiconductor device manufacturing process, temperature, and power supply voltage, are generated.

Description:
[0001]    This application relies for priority upon Korean Patent Application No. 2000-55204, filed on Sep. 20, 2000, the contents of which are herein incorporated by reference in their entirety.  
         BACKGROUND OF THE INVENTION  
         [0002]    The present invention relates to a semiconductor integrated circuit, and more particularly to a clock network for reducing the skew of clock signals.  
           [0003]    In semiconductor integrated circuits, an external clock signal input to one pin is converted into a plurality of internal clock signals that propagate along different paths throughout the entire device. The internal clock signals are ideal when they have the same slew rates and duties, and have no skew. However, internal clock signals that are distant from a clock input pin can be delayed more than internal clock signals next to the clock input pin. This is an important issue in high speed operation of semiconductor integrated circuits, and so a phase blending method has been developed to solve the problem.  
           [0004]    [0004]FIG. 1 illustrates a conventional clock network in which a phase blending method is implemented. As shown in FIG. 1, the clock network  100  is a U-shaped clock network that receives an input clock signal CLK and generates a plurality of internal clock signals ICLK i , (where i is a number between 1 and 9). The input clock signal CLK is connected to a plurality of serially-connected first delay devices  110   a  through  110   f  through a buffer  101 , and the outputs of the delay devices  110   a  through  110   e  are connected to phase blenders  140   a  through  140   e , respectively. The last delay device  110   f  is in turn connected to a plurality of serially-connected second delay devices  130   a  through  130   f .  
           [0005]    The first delay devices  110   a  through  110   f  and the second delay devices  130   a  through  130   f  are manifested as the impedance of a line, e.g., a metal line.  
           [0006]    Outputs of the first delay devices  110   a  through  110   e  and the second delay devices  130   a  through  130   e  are input to respective phase blenders  140   a  through  140   e . Outputs of the phase blenders  140   a  through  140   e  provide the internal clock signals ICLK i .  
           [0007]    The first internal clock signal ICLK 1  is determined by the phase blender  140   a  as an intermediate waveform between a signal of a first up node UP 1 ,i.e., the signal output from the first delay device  110   a , and a signal of the first down node DN 1 , i.e., the signal output from the second delay device  130   a . In operation, the signal of a first down node DN 1  has passed the first up node UP 1 , the first delay devices  110   b  through  110   f , and the second delay devices  130   a  through  130   e .  
           [0008]    The second through ninth internal clock signals ICLK i  (where i is a number between 2 and 9) are generated in a similar manner.  
           [0009]    The phase blenders  140   a  through  140   e  are disclosed in B. W. Garlepp, “Portable Digital DLL for High Speed Interface”, IEEE, Journal of Solid State Circuits, May 1999. The phase blender of the this article is stable in a state in which two received clock signals slope slightly. However, when the clock signals have a greater slope, jitter is generated in the clock signals.  
           [0010]    In addition, since loads of the first delay devices  110   a  through  110   f  and the second delay devices  130   a  through  130   f  are different, a delay of the clock signals input to the phase blenders  140   a  through  140   e  is nonlinear. Furthermore, since the phase blenders  140   a  through  140   e  operate nonlinearly, a delay of the clock signals is even more nonlinear. As a result, the internal clock signals ICLK i  are inevitably skewed. Since the blended rate in the phase blenders  140   a  through  140   e  changes with the variation in the power supply voltage, the temperature, and the semiconductor device manufacturing process, the range of a skew value is similarly wide.  
           [0011]    Thus, a clock network which is capable of reducing the skew of the internal clock signals ICLK i  is required.  
         SUMMARY OF THE INVENTION  
         [0012]    To solve the above problems, it is an object of the present invention to provide a clock network for reducing the skew of clock signals.  
           [0013]    Accordingly, to achieve the above object, a clock network is provide that comprises a plurality of first delay units connected in a line, each operating to delay a clock signal by a first time; a plurality of buffers connected to respective outputs of the first delay units, the buffers operating to generate internal clock signals; and a plurality of second delay units connected in a line, each second delay unit being connected to an output of a respective one of the plurality of buffers.  
           [0014]    In addition, a clock network could also be provided that comprises a buffer for buffering a clock signal; a plurality of first delay units formed in a line for delaying an output of the first buffer by a first time; and a plurality of second delay units connected to respective outputs of the first delay units.  
           [0015]    In this clock network, respective outputs of first and second buffers are preferably connected via a plurality of buffers.  
           [0016]    A clock network may also be provided that comprises a first buffer for buffering a clock signal; a plurality of first delay units for delaying an output of the first buffer by a first time; a plurality of second buffers connected to respective outputs of the first delay units; and a plurality of second delay units connected to respective outputs of the second buffers.  
           [0017]    In each of these clock networks the first and second delay units preferably consist essentially of the resistance and capacitance of lines through which the clock signal propagates. In addition, the first delay units and the second delay units preferably have bilateral output characteristics.  
           [0018]    According to the present invention, the skew of the internal clock signals is reduced, and internal clock signals are generated that have a stable duty with respect to a variation in a semiconductor device manufacturing process, temperature, and power supply voltage.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]    The above object and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which:  
         [0020]    [0020]FIG. 1 illustrates a conventional clock network in which a phase blending method is implemented;  
         [0021]    [0021]FIG. 2 illustrates a ladder type clock network according to a preferred embodiment of the present invention; and  
         [0022]    [0022]FIG. 3 illustrates the flow of a first internal clock signal of FIG. 2. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0023]    The present invention will be described more fully below with reference to the accompanying drawings in which a preferred embodiment of the person invention is shown. Throughout the drawings, like reference numerals refer to like elements.  
         [0024]    [0024]FIG. 2 illustrates a ladder type clock network according to a preferred embodiment of the present invention. Referring to FIG. 2, a clock network  200  receives a clock signal CLK and generates internal clock signals ICLK i  (where i is a number between 1 and 9). The clock network  200  includes a first buffer  201 , a plurality of first delay units  210   a  through  210   j , a plurality of second buffers  220   a  through  220   i , and a plurality of second delay units  230   a  through  230   j .  
         [0025]    The first buffer  201  receives the clock signal CLK and transmits the clock signal CLK to the first delay unit  210   a . The first delay units  210   a  through  210   i  denote a kind of line load, e.g., a metal line having a certain sheet resistance value, and the first delay units  210   a  through  210   j  represent the resistance and capacitance of a metal line having a predetermined length. Output nodes UP 1  through UP 9  of the first delay units  210   a  through  210   j  are connected to the second buffers  220   a  through  220   i , respectively.  
         [0026]    The second delay units  230   a  through  230   j  are connected to output nodes DN 1  through DN 9  of the second buffers  220   a  through  220   i . The second delay units  230   a  through  230   j  are connected to the outputs of respective second buffers  220   a  through  220   i . The second delay units  230   a  through  230   j  are preferably much the same as the first delay units  210   a  through  210   j  and preferably have bilateral output characteristics. Each of the output nodes DN 1  through DN 9  of the second buffers  220   a  through  220   i  provides a respective internal clock signal ICLK i .  
         [0027]    The clock network  200  is referred to as a ladder type clock network, and its operation will be described with reference to FIG. 3, which illustrates the flow of the first internal clock signal ICLK 1 .  
         [0028]    There are nine signal paths provided to the first internal clock signal ICLK 1 . The first path is from the output node UP 1  to the buffer  220   a ; the second path is from the output node UP, though the delay unit  210   b , the buffer  220   b , and the delay unit  230   b ; the third path is from the output node UP 1  to the delay units  210   b  and  210   c , the buffer  220   c , and the delay units  230   c  and  230   b ; the fourth path is from the output node UP 1  through the delay units  210   b ,  210   c , and  210   d , the buffer  220   d , and the delay units  230   d ,  230   c  and  230   b ; the fifth path is from the output node UP 1  through the delay units  210   b ,  210   c ,  210   d , and  210   e , the buffer  220   e , and the delay units  230   e ,  230   d ,  230   c  and  230   b ; the sixth path is from the output node UP 1  through the delay units  210   b ,  210   c ,  210   d ,  210   e , and  210   f , the buffer  220   f , and the delay units  230   f ,  230   e ,  230   d ,  230   c  and  230   b ; the seventh path is from the output node UP 1  through the delay units  210   b ,  210   c ,  210   d , . . . , and  210   g , the buffer  220   g , and the delay units  230   g ,  230   f ,  230   e , . . . , and  230   b ; the eighth path is from the output node UP 1  through the delay units  210   b ,  210   c ,  210   d , . . . , and  210   h , the buffer  220   h , and the delay units  230   h ,  230   g ,  230   f , . . . , and  230   b ; and the ninth path is from the output node UP 1  through the delay units  210   b ,  210   c ,  210   d , . . , and  210   i , the buffer  220   i , and the delay units  230   i ,  230   h ,  230   g , . . . ,  230   b . Thus, the first internal clock signal CLK 1  is generated in the output node DN 1  by blending clock signals transmitted through these nine paths.  
         [0029]    Meanwhile, the ninth internal clock signal ICLK 9  is also provided by nine paths (although not shown in FIG. 3). These paths include a first path from the output node UP 1  through the delay units  210   b ,  210   c , . . . , and  210   i  and the buffer  220 i; a second path from the output node UP 1  through the delay units  210   b ,  210   c , . . . , and  210   h , the buffer  220   h , and the delay unit  230   i ; a third path from the output node UP 1  through the delay units  210   b ,  210   c , . . . , and  210   g , the buffer  220   g , and the delay units  230   h  and  230   i ; a fourth path from the output node UP 1  through the delay units  210   b ,  210   c , . . . , and  210   f , the buffer  220   f , and the delay units  230   g ,  230   h  and  230   i ; a fifth path from the output node UP 1  through the delay units  210   b ,  210   c ,  210   d , and  210   e , the buffer  220   e , and the delay units  230   f ,  230   g ,  230   h  and  230   i ; a sixth path from the output node UP 1  through the delay units  210   b ,  210   c , and  210   d , the buffer  220   d , and the delay units  230   e ,  230   f ,  230   g ,  230   h  and  230   i ; a seventh path from the output node UP 1  through the delay units  210   b  and  210   c , the buffer  220   c , and the delay units  230   d ,  230   e , . . . , and  230   i ; an eighth path from the output node UP 1  through the delay units  210   b , the buffer  220   b , and the delay units  230   c ,  230   d , . . . , and  230   i , and a ninth path from the output node UP 1  through the buffer  220   a , and the delay units  230   b ,  230   c , . . . , and  230   i . Thus, the ninth internal clock signal ICLK 9  is generated in the output node DN 9  also by blending clock signals transmitted through nine different paths.  
         [0030]    Besides the first internal clock signal ICLK 1  and the ninth internal clock signal ICLK 9 , the other internal clock signals ICLK 2  through ICLK 8  are also generated by blending the clock signals transmitted through nine different paths. Thus, the internal clock signal ICLK 1  of the conventional clock network shown in FIG. 1 is jittered by an output waveform due to a distance between two blended phases, and jitter increases, but in the present invention, closely arranged phases are blended together, thereby solving the problem of the conventional art.  
         [0031]    In this way, paths through which the internal clock signals ICLK 1  through ICLK 9  are generated are very similar, on average. Thus, there is no skew of the generated internal clock signals ICLK 1  through ICLK 9 .  
         [0032]    Since variations in parameters such as a semiconductor device manufacturing process, temperature, and a power supply voltage are averaged by paths through which the internal clock signals ICLK 1  through ICLK 9  propagate, change in duty and skew of the internal clock signals ICLK 1  through ICLK 9  is reduced.  
         [0033]    While this invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made thereto without departing from the spirit and scope of the invention as defined by the appended claims.