Abstract:
A solid-state image pickup device, including: a pixel section including at least one pixel circuit including a mechanism for converting an optical signal into an electric signal and accumulating the electric signal in response to exposure time; a pixel driving section configured to drive the pixel section to carry out signal accumulation and signal outputting; at least one different circuit section configured to carry out a process relating to accessing to the pixel section through the pixel driving section; and a control section configured to control, at least upon the signal accumulation of the pixel circuit, the pixel driving section so as to maintain the pixel circuit in a state wherein the pixel circuit accumulates the electric signal and control supply of a power supply voltage to the different circuit section.

Description:
CROSS REFERENCES TO RELATED APPLICATIONS 
       [0001]    The present invention contains subject matter related to Japanese Patent Application JP 2007-126150 filed with the Japan Patent Office on May 10, 2007, the entire contents of which being incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    This invention relates to a solid-state image pickup device represented by a CMOS image sensor and a camera system. 
         [0004]    2. Description of the Related Art 
         [0005]    In recent years, attention is paid to a CMOS image sensor as a solid-state image pickup device or image sensor in place of a CCD image sensor. 
         [0006]    This is because the CMOS image sensor overcomes various problems such as a problem that, since a plurality of power supply voltages are required for operation and a plurality of peripheral ICs must operate in combination, the system is much complicated. 
         [0007]    The CMOS image sensor has such a plurality of significant merits as described below. In particular, the CMOS image sensor can be fabricated using a fabrication process similar to that for fabrication of popular CMOS type integrated circuits and can be driven with a single power supply. Further, the CMOS image sensor allows mixed formation of analog circuits and logic circuits in the same chip using a CMOS process, and therefore, the number of peripheral ICs can be reduced. 
         [0008]    An output circuit of a CCD image sensor in most cases outputs a 1-channel (ch) output using a floating diffusion (FD) amplifier having an FD layer. 
         [0009]    In contrast, a CMOS image sensor includes an FD amplifier for each pixel and in most cases outputs such parallel column outputs by selecting a certain row of a pixel array and reading out the pixels in the row at the same time in a direction along the columns. 
         [0010]    This is because it is difficult for the FD amplifiers disposed in the pixels to have a sufficient driving capacity and, accordingly it, is necessary to use a low data rate. It is advantageous to use parallel processing. 
         [0011]    In the following, a popular CMOS image sensor is described. 
         [0012]      FIG. 1  shows an example of a pixel of a CMOS image sensor formed from four transistors. 
         [0013]    Referring to  FIG. 1 , the pixel  1  includes, for example, a photodiode  11  as a photoelectric conversion device. The pixel  1  further includes four transistors including a transfer transistor  12 , an amplification transistor  13 , a selection transistor  14  and a reset transistor  15  as active devices for the photodiode  11 . 
         [0014]    The photodiode  11  photoelectrically converts incoming light into charge, here, electrons, whose amount corresponds to the light amount of the incoming light. 
         [0015]    The transfer transistor  12  is connected to the photodiode  11  and a floating diffusion FD and transfers electrons produced by photoelectric conversion by the photodiode  11  to the floating diffusion FD when a driving signal is applied to the gate, that is, a transfer gate, thereof through a transfer control line LTx. 
         [0016]    The amplification transistor  13  is connected at the gate thereof to the floating diffusion FD. The amplification transistor  13  is connected to a signal line LSGN through the selection transistor  14  and cooperates with a constant current source outside the pixel to form a source follower. 
         [0017]    An address signal is applied to the gate of the selection transistor  14  through a selection control line LSEL, and if the selection transistor  14  is turned on, then the amplification transistor  13  amplifies the potential at the floating diffusion FD and outputs a voltage corresponding to the potential to the signal line LSGN. A voltage outputted from each pixel is outputted to a pixel output data parallel-serial processing section through the signal line LSGN. 
         [0018]    The reset transistor  15  is connected between a power supply line LVDD and the floating diffusion FD and resets the potential at the floating diffusion FD to the potential of the power supply line LVDD when a reset signal is applied to the gate of the reset transistor  15  through a reset control line LRST. 
         [0019]      FIG. 2  shows an example of a general configuration of a CMOS image sensor or solid-state image pickup device wherein such pixels as shown in  FIG. 1  are arrayed in a two-dimensional array. 
         [0020]    Referring to  FIG. 2 , the CMOS image sensor  20  shown includes a pixel array section  21 , an address decoder  22 , a pixel driving pulse generation circuit  23 , and a level shifter group  24 . The CMOS image sensor  20  further includes a pixel output data parallel-serial processing section  25 , an output circuit section  26 , a sensor control section  27 , and external power supplies  28  and  29  each in the form of a cell. 
         [0021]    In the CMOS image sensor  20 , a power supply voltage VDD is supplied to the address decoder  22 , pixel driving pulse generation circuit  23 , pixel output data parallel-serial processing section  25 , output circuit section  26  and sensor control section  27  in the inside of a chip from the power supply  28 . Meanwhile, another power supply voltage VDD is supplied to the level shifter group  24  and the pixel array section  21  from the power supply  29 . 
         [0022]    In the CMOS image sensor  20 , the sensor control section  27  generates an address for designating a pixel array row to be accessed and sends the address to the address decoder  22 . 
         [0023]    The address decoder  22  renders an output thereof corresponding to the designated pixel row active. Then, to the row designated by the address decoder  22 , a pixel reset pulse LRST and pixel readout pulses LTx and LSEL are supplied to the pixels  1  for each row from the pixel driving pulse generation circuit  23 . Image outputs from the pixels  1  are transferred for each row through the signal line LSGN to the pixel output data parallel-serial processing section  25 . 
         [0024]    Then, image data are outputted for one by one pixel from the pixel output data parallel-serial processing section  25 , and the output data are outputted to the outside of the chip through the output circuit section  26 . 
         [0025]    The sensor control section  27  is a control logic circuit which controls the series of operations. 
         [0026]    Referring to  FIG. 1  again, in order to reset the pixel, the transfer transistor  12  is turned on to sweep out charge accumulated in the photodiode  11 . Thereafter, the transfer transistor  12  is turned off, and the photodiode  11  converts a light signal into charge and accumulates the charge. 
         [0027]    Upon reading out, the reset transistor  15  is turned on to reset the floating diffusion FD, and then the reset transistor  15  is turned off and the voltage at the floating diffusion FD then is outputted through the amplification transistor  13  and the selection transistor  14 . The output in this instance is hereinafter referred to as P-phase output. 
         [0028]    Thereafter, the transfer transistor  12  is turned on to transfer the charge accumulated in the photodiode  11  to the floating diffusion FD, and the voltage at the floating diffusion FD at this time is outputted through the amplification transistor  13 . The output in this instance is hereinafter referred to as D-phase output. 
         [0029]    By setting the difference between the D-phase output and the P-phase output to an image signal, not only a dispersion of the DC component of the output of each pixel but also FD reset noise of the floating diffusion can be removed from the image signal. 
         [0030]    The operations described are carried out simultaneously for pixels of one row since, for example, the gates of the transfer transistors  12 , selection transistors  14  and reset transistors  15  are connected in a unit of a row. 
       SUMMARY OF THE INVENTION 
       [0031]    As seen in  FIG. 2 , the CMOS image sensor  20  requires not only the pixel array section  21  but also a large number of peripheral circuits. There is the possibility that leak current called dark current of the photoelectric conversion devices  11  of the pixels may be increased by heat generated by the peripheral circuits. It is known that dark current increases output signals of pixels and a dispersion of the output signals gives rise to appearance of a coarse image suffering from fixed pattern noise. Therefore, it is necessary to design the CMOS image sensor  20  such that heat of the peripheral circuits may not give rise to increase of dark current of the pixels. 
         [0032]    However, if signal accumulation is carried out for a long period of time, then also the dark current arising from heat of the peripheral circuits is accumulated, the problem of heat of the peripheral circuits becomes further significant. In such an instance, since the image sensor does not output a signal, current consumption can be suppressed by stopping circuit operation while the state wherein a signal is accumulated in the pixels continues. 
         [0033]    However, as a refinement of transistors progresses, off leak current of the transistors is increasing. 
         [0034]    Besides, in the CMOS image sensor  20 , since functions are integrated on the chip, the number of transistors increases and the leak current of the entire chip further increases. 
         [0035]    Therefore, such a situation that, even if the circuit operation is stopped, the heat generation by leak current reaches a level at which it has an influence on the display image may possibly occur. 
         [0036]    Besides, if refinement of the fabrication process for integrating higher functions further progresses in order to achieve higher functions of a CMOS image sensor, the leak current increases, and particularly where high speed operation is required, suppression of the leak current becomes difficult. Further, if the number of transistors to be integrated increases, heat generation further increases. 
         [0037]    As a result, in a digital still camera, particularly in a single-lens reflex camera wherein accumulation operation for a long period of time is required in a bulb mode or the like, increase of heat generation by leak current of peripheral circuits becomes a problem. 
         [0038]    As a technique for suppressing leak current of a transistor, a technique is available which modulates, when the operation speed of the transistor may be low, a substrate bias to raise the threshold voltage of the transistor to suppress leak current. 
         [0039]    This technique, however, is disadvantageous in that separate power supplies must be prepared for a source power supply for the transistor and a power supply for fixing the substrate and a countermeasure for modulating the substrate bias is required, which makes design of both of a chip and a system difficult. 
         [0040]    Therefore, it is demanded to provide a solid-state image pickup device and a camera system by which reduction of power consumption can be anticipated without complicating the design. 
         [0041]    According to an embodiment of the present invention, there is provided a solid-state image pickup device including a pixel section including at least one pixel circuit including a mechanism for converting an optical signal into an electric signal and accumulating the electric signal in response to exposure time, a pixel driving section configured to drive the pixel section to carry out signal accumulation and signal outputting, at least one different circuit section configured to carry out a process relating to accessing to the pixel section through the pixel driving section, and a control section configured to control, at least upon the signal accumulation of the pixel circuit, the pixel driving section so as to maintain the pixel circuit in a state wherein the pixel circuit accumulates the electric signal and control supply of a power supply voltage to the different circuit section. 
         [0042]    Preferably, the control section supplies, upon the signal accumulation of the pixel circuit, the power supply voltage to the pixel driving section and stops the supply of the power supply voltage to the processing section. 
         [0043]    Alternatively, the control section may supply, upon the signal accumulation of the pixel circuit, the power supply voltage to the pixel driving section and lowers the power supply voltage and supply the lowered power supply voltage to the different circuit section. 
         [0044]    Preferably, the pixel driving section maintains the pixel circuit in the state wherein the pixel circuit accumulates the electric signal in response to a control signal received from the control section. 
         [0045]    In this instance, preferably the pixel section, pixel driving section and different circuit section are integrated as an integrated circuit, and the control signal is supplied from the outside. 
         [0046]    Alternatively, the solid-state image pickup device may be configured such that the pixel section, pixel driving section and different circuit section are integrated as an integrated circuit, and the control signal is retained in the integrated circuit. 
         [0047]    Preferably, the solid-state image pickup device further includes a memory section configured to store a status of any of the circuits, to which the supply of the power supply voltage is stopped, before the power supply voltage is supplied, the control section controlling the memory to retain the stored substance of the memory section also when the different circuit section is in an inoperative state as a result of the control of the supply of the power supply voltage to the different circuit section. 
         [0048]    Preferably, the pixel circuit includes an active device configured to output the accumulated signal to a signal line, and the control section controls the potentials at a power supply line to which the active device is connected and the signal line so as to be equal to each other within the signal storage period. 
         [0049]    According to another embodiment of the present invention, there is provided a camera system including a solid-state image pickup device, an optical system configured to form an image of an image pickup object on the image pickup device, and a signal processing circuit configured to process an output image signal of the image pickup device, the solid-state image pickup device including a pixel section including at least one pixel circuit having a mechanism for converting an optical signal into an electric signal and accumulating the electric signal in response to exposure time, a pixel driving section configured to drive the pixel section to carry out signal accumulation and signal outputting, at least one different circuit section configured to carry out a process relating to accessing to the pixel section through the pixel driving section, and a control section configured to control, at least upon the signal accumulation of the pixel circuit, the pixel driving section so as to maintain the pixel circuit in a state wherein the pixel circuit accumulates the electric signal and control supply of a power supply voltage to the different circuit section. 
         [0050]    According to the embodiments of the present invention, during signal storage of the pixel circuit, the pixel driving section is kept in an operative state with the power supply voltage supplied thereto while supply of the power supply voltage of the different circuit section is stopped or the power supply voltage is set to and supplied with a lowered level such that the different circuit section is kept in an inoperative state. 
         [0051]    According to the embodiments of the present invention, reduction of the power consumption can be anticipated without inviting complication in design. Particularly, the power consumption during signal accumulation can be reduced including also leak current when a transistor used in the solid-state image pickup device and the camera system is in an off state. 
         [0052]    The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings in which like parts or elements denoted by like reference symbols. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0053]      FIG. 1  is a circuit diagram showing an example of a pixel of a CMOS image sensor formed from four transistors; 
           [0054]      FIG. 2  is a view showing an example of a popular configuration of a CMOS image sensor or solid-state image pickup device wherein such pixels as shown in  FIG. 1  are disposed in a two-dimensional array; 
           [0055]      FIGS. 3 to 8  are block diagrams showing an example of a configuration of CMOS image sensors or solid-state image devices to which the present embodiment is applied; and 
           [0056]      FIG. 9  is a block diagram showing an example of a configuration of a camera system in which any of the solid-state image pickup devices is incorporated. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First Embodiment 
       [0057]      FIG. 3  shows an example of a configuration of a CMOS image sensor or solid-state image pickup device according to a first embodiment of the present invention. 
         [0058]    Referring to  FIG. 3 , the CMOS image sensor  100  shown includes a pixel array section  101 , an address decoder  102 , a pixel driving pulse generation circuit  103 , a pixel driving section  104 , a pixel output data parallel-serial processing section  105 , and an output circuit section  106 . The CMOS image sensor  100  shown further includes a sensor control section  107 , external power supplies  108  and  109  each in the form of a cell, and switches  110  and  111 . 
         [0059]    Of the components mentioned, the pixel array section  101 , address decoder  102 , pixel driving pulse generation circuit  103 , pixel driving section  104 , pixel output data parallel-serial processing section  105 , output circuit section  106  and sensor control section  107  are integrated in an IC chip  112 . 
         [0060]    In the present embodiment, one, plural ones or all of the pixel array section  101 , address decoder  102 , pixel driving pulse generation circuit  103 , pixel output data parallel-serial processing section  105 , output circuit section  106  and sensor control section  107  other than the pixel driving section  104  correspond to different circuit sections. 
         [0061]    Further, the external power supplies  108  and  109 , the switches  110  and  111  and a controller not shown or the sensor control section  107  form a control section. 
         [0062]    The IC chip  112  has several terminals formed thereon and including power supply terminals TV 1  to TV 5  to which a power supply voltage VDD 1  is supplied from the external power supply  108  in the form of a cell, power supply terminals TV 6  and TV 7  to which a power supply voltage VDD 2  from the external power supply  109  in the form of a cell is supplied, power supply terminals TG 1  to TG 6  connected to a ground potential GND, an input terminal TI 1  to which, for example, a control signal SCTL is supplied, and an output terminal TO 1 . 
         [0063]    In the IC chip  112 , the power supply terminal TV 1  is connected to a power supply terminal Pow of the address decoder  102  and the pixel driving pulse generation circuit  103 , and the power supply terminal TV 2  is connected to a power supply terminal Pow of the pixel driving section  104  while the power supply terminal TV 3  is connected to a power supply terminal Pow of the output circuit section  106 . Further, the power supply terminal TV 4  is connected to a power supply terminal Pow of the pixel output data parallel-serial processing section  105 , and the power supply terminal TV 5  is connected to a power supply terminal Pow of the sensor control section  107 . 
         [0064]    Further, the power supply terminal TV 6  is connected to a power supply terminal Pow 2  of a level shifter group  1041  provided in the pixel driving section  104 , and the power supply terminal TV 7  is connected to power supply lines LVDD of the pixel array section  101 . 
         [0065]    The pixel array section  101  includes a plurality of pixel circuits  101 A arrayed in a matrix. It is to be noted that, in  FIG. 3 , the pixel circuits  101 A are arrayed in three rows and three columns for simplified illustration. 
         [0066]    In  FIG. 3 , an example of a pixel of the CMOS image sensor formed from four transistors. 
         [0067]    Each pixel circuit  101 A includes, for example, a photodiode  121  as a photoelectric conversion device, and further includes four transistors including a transfer transistor  122 , an amplification transistor  123 , a selection transistor  124  and a reset transistor  125  as active devices for the photodiode  121 . 
         [0068]    The photodiode  121  photoelectrically converts incoming light into charge, here electrons, whose amount corresponds to the light amount of the incoming light. 
         [0069]    The transfer transistor  122  is connected between the photodiode  121  and a floating diffusion FD and transfers electrons obtained by photoelectric conversion by the photodiode  121  to the floating diffusion FD when a driving signal is provided to the gate, that is, a transfer gate, of the transfer transistor  122  through a transfer control line LTx. 
         [0070]    The amplification transistor  123  is connected at the gate thereof to the floating diffusion FD. The amplification transistor  123  is connected to a signal line LSGN through the selection transistor  124  and cooperates with a constant current source outside the pixel to form a source follower. 
         [0071]    If an address signal is provided to the gate of the selection transistor  124  through the selection control line LSEL to turn on the selection transistor  124 , then the selection transistor  124  amplifies the potential at the floating diffusion FD and outputs a signal corresponding to the amplified potential to the signal line LSGN. The voltage outputted from each pixel is outputted to the pixel output data parallel-serial processing section  105  through the signal line LSGN. 
         [0072]    The operations mentioned are carried out in parallel for pixels of one row since the gates of, for example, the transfer transistors  122 , selection transistors  124  and reset transistors  125  are connected in a unit of a row. 
         [0073]    A reset control line LRST, a transfer control line LTx and a selection control line LSEL wired in the pixel array section  101  are wired as a set in a unit of a row of the pixel array. 
         [0074]    The reset control lines LRST, transfer control lines LTx and selection control lines LSEL are driven by the pixel driving section  104 . 
         [0075]    The pixel driving section  104  includes a level shifter group  1041  including a plurality of level shifters LS which are control line drivers to which a reset control line LRST, a transfer control line LTx and a selection control line SLEL are individually connected, and a control logic circuit group  1042  for controlling driving of the level shifters LS of the level shifter group  1041 . 
         [0076]    The level shifter group  1041  includes, for each row of the pixel array, three level shifters LS 1 , LS 2  and LS 3  to which a reset control line LRST, a transfer control line LTx and a selection control line LSEL are connected, respectively. 
         [0077]    The level shifter group  1041  is placed, upon power on when the power supply voltage VDD 2  from the external power supply  109  is supplied through the power supply terminal TV 6 , into and then retained in an operative state in response to the supply of the power supply voltage VDD 2  even if supply of the power supply voltage VDD 1  to other devices such as the address decoder stops when the power supply voltage VDD 2  is supplied. 
         [0078]    The control logic circuit group  1042  includes a plurality of NOR gates NR arrayed corresponding to the array of the level shifters LS of the level shifter group  1041  so as to control the input to the level shifters LS. 
         [0079]    Each of the NOR gates NR is connected at an output thereof to an input of a corresponding one of the level shifters LS serving as drivers, at a first input terminal thereof to a corresponding supply line for a driving pulse from the pixel driving pulse generation circuit  103  and at a second input terminal thereof commonly to the input terminal TI 1  of the IC chip  112 . 
         [0080]    To the input terminal TI 1 , a control signal SCTL, for example, from a controller not shown is supplied. 
         [0081]    If the control signal SCTL is supplied at the high level, then at least the transfer control lines LTx can be set to the low level irrespective of the pulse signal from the pixel driving pulse generation circuit  103 , and consequently, the pixel circuits  101 A can be held in a charge (signal) accumulation state. 
         [0082]    The switch  110  is connected at a fixed contact a thereof to the power supply terminals TV 1 , TV 3 , TV 4  and TV 5  of the IC chip  112 , at a movable contact b thereof to the positive electrode of the external power supply  108  and the power supply terminal TV 2 , and at a movable contact c thereof to the negative electrode of the external power supply  108  and the power supply terminals TG 1  to TG 6 . 
         [0083]    The switch  110  connects the fixed contact a to the movable contact b or c in response to a changeover signal SW, for example, from a controller not shown or the sensor control section  107 . 
         [0084]    In particular, upon ordinary general operation, the changeover signal SW is supplied to the switch  110  so as to connect the fixed contact a and the movable contact b to each other. Consequently, the power supply voltage VDD 1  from the external power supply  108  is supplied to the address decoder  102  and pixel driving pulse generation circuit  103 , pixel driving section  104 , pixel output data parallel-serial processing section  105 , output circuit section  106  and sensor control section  107  of the IC chip  112  through the power supply terminals TV 1  to TV 5 , respectively. 
         [0085]    On the other hand, within a charge accumulation period of the pixel array section  101 , the changeover signal SW is supplied to the switch  110  so as to connect the fixed contact a and the movable contact c to each other. Consequently, the power supply terminals TV 1 , TV 3 , TV 4  and TV 5  are connected to the ground potential. As a result, the supply of the power supply voltage VDD 1  from the external power supply  108  to the address decoder  102  and pixel driving pulse generation circuit  103 , pixel output data parallel-serial processing section  105 , output circuit section  106  and sensor control section  107  of the IC chip  112 , respectively, is stopped. 
         [0086]    The switch  111  is connected at a fixed contact a thereof to the power supply terminal TV 7  of the IC chip  112 , at a movable contact b thereof to the positive electrode of the external power supply  109  and the power supply terminal TV 6 , and at a movable contact c thereof to the negative electrode of the external power supply  108 . 
         [0087]    The switch  111  connects the fixed contact a thereof to the movable contact b or c in response to a changeover signal SW, for example, from the controller not shown or the sensor control section  107 . 
         [0088]    In particular, upon ordinary general operation, the changeover signal SW is supplied to the switch  111  so as to connect the fixed contact a and the movable contact b to each other. Consequently, the power supply voltage VDD 2  from the external power supply  109  is supplied to the power supply lines LVDD of the level shifter group  1041  in the pixel driving section  104  and the pixel array section  101  of the IC chip  112  through the power supply terminals TV 6  and TV 7 . 
         [0089]    On the other hand, within a charge accumulation period of the pixel array section  101 , the changeover signal SW is supplied to the switch  111  so as to connect the fixed contact a and the movable contact c to each other. Consequently, the power supply terminal TV 7  is connected to the ground potential. As a result, the supply of the power supply voltage VDD 2  from the external power supply  109  to the power supply lines of the pixel array section  101  of the IC chip  112  is stopped, and the power supply lines LVDD of the pixel array section  101  are held at the ground potential. 
         [0090]    In the CMOS image sensor  100  having such a configuration as described above, in normal general operation, the changeover signal SW is supplied to the switch  110  so as to connect the fixed contact a and the movable contact b thereof to each other. Consequently, the power supply voltage VDD 1  from the power supply  108  is supplied to the address decoder  102  and pixel driving pulse generation circuit  103 , pixel driving section  104 , pixel output data parallel-serial processing section  105 , output circuit section  106  and sensor control section  107  of the IC chip  112  through the power supply terminals TV 1  to TV 5 , respectively. 
         [0091]    Similarly, the changeover signal SW is supplied also to the switch  111  so as to connect the fixed contact a and the movable contact c to each other. Consequently, the power supply voltage VDD 2  from the power supply  109  is supplied to the level shifter group  1041  in the pixel driving section  104  and the power supply lines LVDD of the pixel array section  101  of the IC chip  112  through the power supply terminals TV 6  and TV 7 . 
         [0092]    In such a state as described above, the sensor control section  107  generates an address for designating a pixel array row to be accessed and sends the address to the address decoder  102 . 
         [0093]    The address decoder  102  renders an output thereof corresponding to the designated pixel row active. Consequently, a pixel reset pulse LRST and pixel readout pulses LTx and LSEL for each row are supplied from the pixel driving pulse generation circuit  103  to the pixel array section  101 , and image outputs from the pixel circuits  101 A are transferred to the pixel output data parallel-serial processing section  105  for each row through the signal line LSGN. 
         [0094]    Then, image data are outputted one by one pixel from the pixel output data parallel-serial processing section  105  and outputted to the outside of the chip through the output circuit section  106 . 
         [0095]    If the control signal SCTL is supplied at the high level to the input terminal TI 1 , then the pixel driving section  104  can set at least the transfer control lines LTx to the low level irrespective of the pulse signal from the pixel driving pulse generation circuit  103 , and the pixel circuits  101 A are fixed to a charge (signal) accumulation state. 
         [0096]    At this time, as described hereinabove, within a charge accumulation period of the pixel array section  101 , the changeover signal SW is supplied to the switch  110  so as to connect the fixed contact a and the movable contact b to each other. Consequently, the power supply terminals TV 1 , TV 3 , TV 4  and TV 5  are connected to the ground potential. As a result, the supply of the power supply voltage VDD 1  from the power supply  108  to the address decoder  102  and pixel driving pulse generation circuit  103 , pixel output data parallel-serial processing section  105 , output circuit section  106  and sensor control section  107  of the IC chip  112  is stopped. 
         [0097]    Similarly, the changeover signal SW is supplied to the switch  111  so as to connect the fixed contact a and the movable contact c to each other. Consequently, the power supply terminal TV 7  is connected to the ground potential. As a result, the supply of the power supply voltage VDD 2  from the power supply  109  to the power supply lines of the pixel array section  101  of the IC chip  112  is stopped, and the power supply lines LVDD of the pixel array section  101  are held at the ground potential. 
         [0098]    In this manner, even if the power supply to the circuits other than the pixel driving section  104  stops, the pixels are maintained in an accumulation state. At this time, leak current which is generated in the overall chip includes only leak current generated at the pixel driving section  104 . 
         [0099]    As described above, according to the CMOS image sensor  100  of the present embodiment, upon accumulation for a long period of time, heat generation arising from off leak current of the circuits integrated on the CMOS image sensor is suppressed. Consequently, generation of dark current by such heat generation and hence deterioration of the picture quality can be suppressed. 
         [0100]    Further, when compared with an alternative popular suppression technique of off leak current which utilizes a substrate bias effect, the suppression of heat generation can be applied only by turning on/off of the power supply, and the circuit configuration of a chip and the system configuration can be designed further readily. 
       Second Embodiment 
       [0101]      FIG. 4  shows an example of a configuration of a CMOS image sensor or solid-state image pickup device according to a second embodiment of the present invention. 
         [0102]    The CMOS image sensor  100 A according to the second embodiment is a modification to but is different from the CMOS image sensor  100  according to the first embodiment described above in that it includes variable power supplies  113  and  114  in place of the switches  110  and  111 . 
         [0103]    In particular, the fixed power supply  108  supplies a power supply voltage VDD 1  to the power supply terminal TV 2 ; the fixed power supply  109  supplies a power supply voltage VDD 2  to the power supply terminal TV 6 ; the variable power supply  113  supplies a variable power supply voltage VDD 3  to the power supply terminals TV 1 , TV 3 , TV 4  and TV 5 ; and the variable power supply  114  supplies a variable power supply voltage VDD 4  to the power supply terminal TV 7 . 
         [0104]    The variable power supplies  113  and  114  receive a control signal SCTL 2 , for example, from a controller not shown and supply an ordinary power supply voltage VDD upon normal operation but supplies, during a charge accumulation period, a power supply voltage lower than the power supply voltage such as VDD/2 to the object of the voltage supply. More particularly, the variable power supplies  113  and  114  supply a power supply voltage of such a low level that the address decoder  102 , pixel driving pulse generation circuit  103 , pixel output data parallel-serial processing section  105 , output circuit section  106  and sensor control section  107  of the IC chip  112  are kept in an inoperative stage, and preferably of such a low level that leak current of the transistors of the components can be suppressed. 
         [0105]    Also in this instance, if the control signal SCTL is supplied at the high level to the input terminal TI 1 , then the pixel driving section  104  can set at least the transfer control lines LTx to the low level irrespective of the pulse signal from the pixel driving pulse generation circuit  103 . Consequently, the pixel circuits  101 A are fixed to a charge or signal accumulation state. 
         [0106]    At this time, even if the power supply voltage to the address decoder  102 , pixel driving pulse generation circuit  103 , pixel output data parallel-serial processing section  105 , output circuit section  106  and sensor control section  107  other than the pixel driving section  104  is dropped, the pixels are maintained in an accumulation state. 
         [0107]    Also in the present second embodiment, an effect of suppressing leak current can be obtained by lowering the power supply voltage. When compared with the first embodiment wherein power supply is stopped completely, the restoration upon re-starting of power supply is carried out more quickly, it is possible to allow some circuit to continue its function. 
       Third Embodiment 
       [0108]      FIG. 5  shows an example of a configuration of a CMOS image sensor or solid-state image pickup device according to a third embodiment of the present invention. 
         [0109]    The CMOS image sensor  100 B according to the third embodiment is a modification to but is different from the CMOS image sensor  100  according to the first embodiment described above in that the control signal SCTL is not provided from a controller outside of the IC chip  112  but can be generated in the IC chip  112 . 
         [0110]    In particular, referring to  FIG. 5 , a memory  1043  is disposed in the pixel driving section  104 B to which the power supply voltage VDD 1  is supplied from the external power supply  108  such that information for maintaining the pixels in an accumulation state is retained in the memory  1043 . 
         [0111]    In this instance, the power supply voltage continues to be supplied also to the memory  1043 . 
         [0112]    For example, information of 1 or 0 of the memory  1043  is controlled by the sensor control section  107  to which the normal power supply voltage VDD 3  is supplied. 
         [0113]    With the CMOS image sensor  100 B of the present third embodiment, advantages similar to those achieved by the CMOS image sensor  100  of the first embodiment can be achieved. 
         [0114]    It is to be noted that the configuration of the CMOS image sensor  100 B of the third embodiment can be applied also to the CMOS image sensor  100 A of the second embodiment described above. 
       Fourth Embodiment 
       [0115]      FIG. 6  shows an example of a configuration of a CMOS image sensor or solid-state image pickup device according to a fourth embodiment of the present invention. 
         [0116]    Referring to  FIG. 6 , the CMOS image sensor  100 C according to the fourth embodiment is a modification to but is different from the CMOS image sensor  100  according to the first embodiment described above in that it includes a status holding memory  115  having a power supply terminal Pow connected to the power supply terminal TV 2  to which the power supply voltage VDD 1  is supplied normally is connected. 
         [0117]    In the example of  FIG. 6 , the sensor control section  107  has the status holding memory  115 , and the power supply voltage continues to be supplied to the status holding memory  115 . 
         [0118]    The reason why the status holding memory  115  is provided in the IC chip  112 C is described below. 
         [0119]    In the first embodiment, if supply of the power supply voltage to the circuits other than the pixel driving section is stopped, then also information which defines the operation status of the blocks to which the supply of the power supply voltage is stopped is lost. Therefore, after supply of the power supply voltage is re-started, it is necessary to start operation beginning with operation for restoring the operation status such as designation of operation, and much time may be required for restoration. 
         [0120]    Therefore, in the present fourth embodiment, the power supply voltage continues to be supplied to the status holding memory  115  which designates an operation thereby to eliminate the necessity for re-designation of operation. Consequently, after supply of the power supply voltage is re-started, the time before operation of the chip is started can be reduced. 
       Fifth Embodiment 
       [0121]      FIG. 7  shows an example of a configuration of a CMOS image sensor or solid-state image pickup device according to a fifth embodiment of the present invention. 
         [0122]    Referring to  FIG. 7 , the CMOS image sensor  100 D according to the fifth embodiment is a modification to but is different from the CMOS image sensor  100  according to the first embodiment described above in that it includes a shift register  116  in place of the address decoder  102  and the pixel driving section  104  is formed only from a level shifter group or driver group  1041 A. Further, the control signal SCTL supplied from the input terminal TI 1  is inputted to the pixel driving pulse generation circuit  103 D, and the power supply voltage VDD 1  from the external power supply  108  is normally supplied to the shift register  116  and the pixel driving pulse generation circuit  103 D. 
         [0123]    While, in the first to fourth embodiments described hereinabove, selection of a designated pixel row is carried out by the address decoder  102 , in the present fifth embodiment, selection of a pixel row is carried out by the shift register  116 . 
         [0124]    Since the pixel driving pulse generation circuit  103 D generates a driving pulse to a designated row, where an address decoder is used, a driving pulse is supplied only to a designated row. 
         [0125]    However, where the shift register  116  is used, all rows can be designated by successively sending “1” to shift-in signals. If the control signal SCTL for issuing an instruction to control a designated row to an accumulation state is provided from the outside through the input terminal TI 1  to the pixel driving pulse generation circuit  103 D, then the pixels of all rows can be designated to an accumulation state. 
         [0126]    Accordingly, in the present fifth embodiment, the power supply voltage continues to be supplied to the shift register  116  and the pixel driving pulse generation circuit  103 D. 
       Sixth Embodiment 
       [0127]      FIG. 8  shows an example of a configuration of a CMOS image sensor or solid-state image pickup device according to a sixth embodiment of the present invention. 
         [0128]    Referring to  FIG. 8 , the CMOS image sensor  100 E according to the sixth embodiment is a modification to but is different from the CMOS image sensor  100  according to the first embodiment described above in that, when a pixel output is not read out to a signal line LSGN such as within a charge accumulation period or the like, the potentials at the power supply lines LVDD of the pixel array section  101  and the signal lines LSGN are controlled so as to be equal to each other. 
         [0129]    In the present embodiment, a switch  117  is provided between a power supply line LVDD and each signal line LSGN. However, the arrangement of  FIG. 8  is an example to the sought end, and various modified forms are possible. For example, a configuration for setting the potential at a signal line LSGN equal to the potential at a power supply line LVDD may be additionally provided on the pixel output data parallel-serial processing section  105  side. 
         [0130]    In the pixel circuit  101 A, there is the possibility that off leak current may appear between a power supply line LVDD and an output signal line LSGN through the selection transistor  124 . 
         [0131]    Even if the off leak current amount per one pixel is small, there is the possibility that, as the number of pixels increases, unignorable leak current may appear with the entire pixel array. 
         [0132]    Therefore, within a waiting period within which a pixel output is not read out such as, for example, during accumulation for a long period of time, the off leak can be prevented not only by controlling the pixel power supply but also by controlling the power supply line LVDD and the signal line LSGN to the same potential. 
         [0133]    As described above, with the CMOS image sensor  100 E according to the present embodiment, upon accumulation for a long period of time, heat generation arising from off leak current of the circuits accumulated on the CMOS image sensor is suppressed. Consequently, generation of dark current by such heat generation and hence deterioration of the picture quality can be suppressed. 
         [0134]    Further, when compared with an alternative popular suppression technique of off leak current which utilizes a substrate bias effect, the suppression of heat generation can be applied only by turning on/off of the power supply or by voltage control, and the circuit configuration of a chip and the system configuration can be designed further readily. 
         [0135]    Further, while, in the third, fourth and fifth embodiments, the memory or shift register continues to be supplied with a power supply voltage, also in those cases, leak current from the memory or shift register can be suppressed by lowering the power supply voltage within a range within which the retained substance is not lost from the memory or shift register as in the second embodiment. 
         [0136]    Further, while, in the first to sixth embodiments, stopping of supply or dropping of the power supply voltage to be supplied to the pixel driving sections, particularly to the circuit groups other than the level shifter group  1041  is carried out similarly, the power supply systems in the chip may be classified more finely while similar control is applied individually to the individual systems. 
         [0137]    It is to be noted that, while the CMOS image sensors according to the embodiments are not restricted particularly, they may be configured, for example, as CMOS image sensors which incorporate an analog-digital converter (ADC) of the column parallel type. 
         [0138]    A solid-state image pickup device which exhibits such effects as described above can be applied as an image pickup device for a digital camera or a video camera. 
         [0139]      FIG. 9  shows an example of a configuration of a camera system to which a solid-state image pickup device according to any of the embodiments of the present invention is applied. 
         [0140]    Referring to  FIG. 9 , the camera system  200  shown includes an image pickup device  210  to which any of the CMOS image sensors  100  and  100 A to  100 E according to the embodiments of the present invention described hereinabove can be applied. The camera system  200  further includes an optical system for introducing incoming light to the pixel region of the image pickup device  210  to form an image of an image pickup object, for example, a lens  220  for forming an image of the incoming light or image light on an image pickup plane. The camera system  200  further includes a driving circuit (DRV)  230  for driving the image pickup device  210 , and a signal processing circuit (PRC)  240  for processing an output signal of the image pickup device  210 . 
         [0141]    The driving circuit  230  has a timing generator not shown for generating various timing signals including a start pulse and a clock pulse for driving the circuits in the image pickup device  210 , and drives the image pickup device  210  with predetermined timing signals. 
         [0142]    The signal processing circuit  240  carries out signal processes such as correlation double sampling (CDS) for an output signal of the image pickup device  210 . 
         [0143]    An image signal processed by the signal processing circuit  240  is recorded into a recording medium such as, for example, a memory. The image information recorded in the recording medium is hard copied by a printer or the like. Further, the image signal processed by the signal processing circuit  240  is displayed as moving pictures on a monitor formed from a liquid crystal display apparatus or the like. 
         [0144]    As described above, by incorporating any of the CMOS image sensors  100  and  100 A to  100 E described hereinabove as the image pickup device  210  in an image pickup apparatus such as a digital camera, a camera of high accuracy which exhibits low power consumption can be implemented. 
         [0145]    It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof. cm What is claimed is: