Abstract:
An apparatus comprising a plurality of buffers and a channel router circuit. The buffers may be each configured to generate a control signal in response to a respective one of a plurality of channel requests received from a respective one of a plurality of clients. The channel router circuit may be configured to connect one or more of the buffers to one of a plurality of memory resources. The channel router circuit may be configured to return a data signal to a respective one of the buffers in an order requested by each of the buffers.

Description:
[0001]    This application claims the benefit of U.S. Provisional Application No. 61/347,864, filed May 25, 2010 and is hereby incorporated by reference in its entirety. 
         [0002]    The present application may relate to co-pending application Ser. No. 12/857,716, filed Aug. 17, 2010 and Ser. No. 12/878,194, filed Sep. 9, 2010, which are each hereby incorporated by reference in their entirety. 
     
    
     FIELD OF THE INVENTION 
       [0003]    The present invention relates to memory storage generally and, more particularly, to a method and/or apparatus for implementing a system to partition one or more memory resources to be accessed by multiple requesters. 
       BACKGROUND OF THE INVENTION 
       [0004]    Conventional memory subsystems are designed to allow one requestor at a time to have access to a memory resource. In such systems, a tight coupling between the requestor and the memory subsystem is implemented. Tight coupling makes modification of any part of the memory subsystem difficult without impacting the other parts of the system. Similarly, such coupling does not allow different types of memories such as DRAM and SRAM to share a common address space. Furthermore, in such conventional approaches all requestors are assumed to be synchronous to the memory subsystem. Such an approach contributes to routing congestion due to the large number of possible long routes needed to access the different memory subsystems. 
         [0005]    It would be desirable to implement a method and/or apparatus for partitioning memory that is scalable to allow access to a large number of memory resources to provide, for example, improved system bandwidth by having any given requestor have parallel access to multiple memory subsystems. 
       SUMMARY OF THE INVENTION 
       [0006]    The present invention concerns a plurality of buffers and a channel router circuit. The buffers may be each configured to generate a control signal in response to a respective one of a plurality of channel requests received from a respective one of a plurality of clients. The channel router circuit may be configured to connect one or more of the buffers to one of a plurality of memory resources. The channel router circuit may be configured to return a data signal to a respective one of the buffers in an order requested by each of the buffers. 
         [0007]    The objects, features and advantages of the present invention include implementing a system that may (i) be expandable to a large number of memory resources, (ii) allow for shared access by a plurality of requestors to any memory resource, (iii) reduce area and/or implementation cost, (iv) allow parallel access by different or the same requestor to different memory resources, (vi) allow all the different memory resources to become part of the same memory map, (vii) allow independent arbitration for each memory resource, (viii) allow different criteria to be used in the arbitration for each memory resource and/or (ix) allow the same requestor logic and interface to be used to access dissimilar memory resources. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
           [0009]      FIG. 1  is a block diagram of a system in accordance with the present invention; 
           [0010]      FIG. 2  is a more detailed diagram of the system of  FIG. 1 ; 
           [0011]      FIG. 3  is a computer system with hard disk drives; 
           [0012]      FIG. 4  is a block diagram of a hard disk drive; and 
           [0013]      FIG. 5  is a block diagram of a hard disk controller. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0014]    Referring to  FIG. 1 , a block diagram of a system  100  is shown in accordance with a preferred embodiment of the present invention. The system  100  generally comprises a plurality of blocks (or circuits)  102   a - 102   n,  a block (or circuit)  104 , a plurality of blocks (or circuits)  106   a - 106   n,  a plurality of blocks (or circuits)  108   a - 108   n  and a plurality of blocks (or circuits)  110   a - 110   n.  The circuits  102   a - 102   n  may each be implemented as a buffer circuit. For example, the circuits  102   a - 102   n  may be implemented as First-In First-Out (FIFO) memory circuits. The circuit  104  may be implemented as a channel router circuit. The circuits  106   a - 106   n  may each be implemented as an arbiter circuit. The circuits  108   a - 108   n  may each be implemented as a protocol engine circuit. The circuits  110   a - 110   n  may each be implemented as a memory circuit. 
         [0015]    In one example, the memory circuits  110   a - 110   n  may be implemented as external memory circuits (e.g., on a separate integrated circuit from the circuits  102   a - 102   n  and the channel router circuit  104 ). In another example, the memory circuits  110   a - 110   n  may be implemented as internal memory circuits (e.g., implemented on an integrated circuit along with the circuits  102   a - 102   n  and the channel router circuit  104 ). In one example, the memory circuits  110   a - 110   n  may each be implemented as a dynamic random access memory (DRAM). The particular type of DRAM implemented may be varied to meet the design criteria of a particular implementation. In another example, the memory circuits  110   a - 110   n  may each be a double data rate (DDR) memory circuit. The memory circuits  110   a - 110   n  may be implemented as a variety of types of memory circuits. 
         [0016]    The circuits  102   a - 102   n  may each receive a respective one of a number of signals (e.g., CHANNEL_CLIENTa-n) from a number of clients (or requesters). The signals CHANNEL_CLIENTa-n may be request signals. The circuits  102   a - 102   n  may present a number of control signals (e.g., CMDa-CMDn) and a number of data signals (e.g., DATAa-DATAn) to the channel router circuit  104 . In one example, the control signals CMDa-CMDn may be implemented as command signals. The circuit  104  may present each of the control signals CMDa-CMDn to each of the arbiter circuits  106   a - 106   n.  The arbiter circuits  106   a - 106   n  may each present a signal (e.g., CMD_SEL) to one of the protocol engines  108   a - 108   n.  The signal CMD_SEL may represent one of the control signals CMDa-CMDn selected by the arbiter circuits  106   a - 106   n.    
         [0017]    The system  100  may allow simultaneous access to the memory circuits  110   a - 110   n  by two or more of the request signals CHANNEL_CLIENTa-n. Each of the request signals CHANNEL_CLIENTa-n may provide requests for access to one of the memory circuits  110   a - 110   n.  In one example, the arbiter circuits  106   a - 106   n  may have registered inputs and outputs. This may allow greatly reduced routing congestion. The partitioning may allow for simplicity and/or focus within the arbiter circuits  106   a - 106   n  and/or the protocol engine circuit  104 . Easy modifications and/or updates to a particular one of the subsystems may be implemented. 
         [0018]    The circuit  100  may provide a modular and/or scalable implementation. The circuit  100  may support 1 to N different memory circuits  110   a - 110   n.  The memory circuits  100   a - 100   n  may be implemented as a mix of similar and/or different memory types (e.g., SRAM, DRAM, etc.). Implementing different memory types may allow the cost of implementing a system to be reduced. For example, high bandwidth and/or low latency memories may be implemented in parallel with high capacity memories. The circuit  100  may support memory circuits  100   a - 100   n  that are implemented both internally and/or externally to the circuit  100 . The circuit  100  may support memory circuits  100   a - 100   n  that are interleaved by low address bits (e.g., dword, 64-byte, etc.) to increase effective bandwidth out of the memory subsystem. The particular number of memory circuits  110   a - 110   n  may be scaled to provide additional parallel paths. Such scaling may provide an increase in bandwidth. The circuit  100  may support 1 to N different requestors. The number of requestors may be the same number, or a different number, as the number of memory circuits  110   a - 110   n . The circuit  100  may support more than one FIFO per client to effectively provide more bandwidth from the requestor. From the perspective of the channel router circuit  104 , each of the FIFO circuits  102   a - 102   n  may be connected to a different requestor. While a particular requestor is waiting for access to the memory circuits  110   a - 110   n,  the requestor may process two bursts at a time and/or fill one or more of the FIFO circuits  102   a - 102   n.    
         [0019]    The circuit  100  may provide improved system bandwidth by having parallel access to one or more of the memory subsystems  110   a - 110   n . Implementing a channel router  104  may result in reduced congestion by reducing the number of long routes to each of the memory resource  110   a - 110   n . In one example, all of the memory resources  110   a - 110   n  may be configured to share a common address space. In another example, the circuit  100  may be expandable to a large number of memory resources. 
         [0020]    The FIFO circuits  102   a - 102   n  may allow each of the different requesters to operate at a frequency that is different from the frequency of the memory circuits  110   a - 110   n . Such an implementation may allow a loose coupling between the particular requestor and the memory circuits  110   a - 110   n.  The buffer circuits  102   a - 102   n  may provide arbitration latency absorption. The FIFO circuits  102   a - 102   n  may have a separate clock domain for the signals CMDa-n and the signal DATA. The signal CMD operates at a frequency of the corresponding arbiter circuits  106   a - 106   n.  The signal DATA may operate at a frequency of the protocol engine circuits  108   a - 108   n.  If the corresponding arbiter circuits  106   a - 106   n  and the corresponding protocol engine circuit  108   a - 108   n  have different frequencies, then the signal CMD_SEL may be an asynchronous signal configured to communicate the next command to perform. 
         [0021]    The channel router  104  may allow shared access to one or more of the memory circuits  110   a - 110   n . Area and/or cost may be minimized by reducing the number of signals for each memory. A client generally only has one copy that the channel router  104  broadcasts to all the arbiters  106   a - 106   n.  Each device may have a unique address. Part of the incoming address may be used as a selection term for the particular memory circuits  110   a - 110   n  being requested. For example, if only two of the memory circuits  110   a - 110   n  are being shared, then the most significant bit of the address may be used to select between the two memory circuits  110   a - 110   n  being shared. If there are more than two of the memory circuits  110   a - 110   n  being shared, then a variety of schemes may be used to select between the memory circuits  110   a - 110   n  by using a combination of address bits. 
         [0022]    The channel router  104  may present the signals CMDa-CMDn to one of the arbiters  106   a - 106   n.  The channel router  104  may also enable a selected data path based on the result of the arbitration. Parallel access to each of the different memory circuits  110   a - 110   n  by different requestors may allow for additional bandwidth. The channel router  104  may also resolve out of order data problems returned to the requestor if a requestor has outstanding requests to more than one memory circuit  110   a - 110   n . For example, the channel router  104  may hold off requests from a particular requestor for access to a different one of the memory circuits  110   a - 110   n  instead of the currently active memory circuit  110   a - 110   n  until the access to the active memory subsystem is complete. The channel router  104  may be implemented to provide an order of multiplexing that matches the physical layout of the integrated circuit. In one example, if the FIFO  102   a  and the FIFO  102   b  are near each other, then the channel router  104  may multiplex the outputs of the FIFO circuit  102   a  and the FIFO circuit  102   b  first and then multiplex this result with the remaining FIFO circuits  102   a - 102   n.  This may allow the channel router  104  to reduce the congestion for the multiple channel clients to access the multiple arbiters  106   a - 106   n.    
         [0023]    The arbiter circuits  106   a - 106   n  may perform independent arbitration for each of the memory circuits  110   a - 110   n.  The arbitration may be tuned to the particular type of memory implemented (e.g., banks of a DDR, minimizing read/write transitions, etc.). The arbiter circuits  106   a - 106   n  may determine which of the incoming requests to provide to the particular protocol engines  108   a - 108   n  next. The particular type of arbitration scheme implemented may be varied to meet the design criteria of the overall system. 
         [0024]    The protocol engine circuits  108   a - 108   n  may queue the command signals CMDa-CMDn in the order received by the arbiter circuits  106   a - 106   n.  The arbiter circuits  106   a - 106   n  may decide which of the command signals CMDa-CMDn the protocol engine circuits  108   a - 108   n  receives next. Any one of the protocol engine circuits  108   a - 108   n  may process the selected command signals CMD_SEL from a corresponding arbiter circuit  106   a - 106   n.  For example,  108   a  may process commands received from the arbiter  106   a.  The protocol engines  108   a - 108   n  may process the commands provided by the arbiters  106   a - 106   n.  The protocol engines  108   a - 108   n  may control writes and/or reads of data to/from the memory circuits  110   a - 110   n . The protocol engines  108   a - 108   n  may be configured to run the particular protocol used by each type of memory. 
         [0025]    The memory circuits  110   a - 110   n  may each be implemented using any memory type of addressable memory currently available or potentially available in the future. The memory circuits  110   a - 110   n  may be implemented as volatile memory. For example, the memory circuits  110   a - 110   n  may be implemented as RDRAM, SDRAM, DRAM, etc. The memory circuits  110   a - 110   n  may be implemented as volatile or non-volatile memory. In one example, the memory circuits  110   a - 110   n  may be implemented as flash memory. The memory circuits  110   a - 110   n  may be implemented as internal memory, external memory, or a combination. A mixture of a variety of types of memory circuits  110   a - 110   n  may be implemented. The memory circuits  110   a - 110   n  may write data in response to write command signals CMD_SEL received from the protocol engine circuit  104 . The memory circuits  110   a - 110   n  may provide read data in response to read command signals CMD_RD received from the protocol engine circuit  104 . 
         [0026]    Referring to  FIG. 2 , a more detailed diagram of the circuit  100  is shown. In addition to the circuits  102   a - 102   n,  the channel router circuit  104  and the memory circuits  110   a - 110   n,  the circuit  100  comprises a block (or circuit)  304  and a block (or circuit)  306 . The circuit  304  may be implemented as a memory controller circuit. The circuit  306  may be implemented as a DDR PHY interface circuit. The circuit  304  and the circuit  306  illustrate details of one of the data paths. 
         [0027]    The circuit  304  generally comprises the arbiter circuit  106   a,  the protocol engine  106 , a register interface circuit  310  and an internal memory controller circuit  312 . The internal memory controller circuit  312  may comprise another arbiter circuit  106   b , an SRAM interface control circuit  108   b  and an internal SRAM memory circuit  110   b.  The circuit  306  may comprise a register interface  318 , a DDR PHY subsystem  320  and a DDR pad circuit  322 . 
         [0028]    The protocol engine  108  may implement DDR 1 , DDR 2 , and/or DDR 3  protocol compliant with JEDEC standards. Other protocols, such as the DDR 4  standard, which is currently being worked on by JEDEC committees, may also be implemented. The protocol engine  108  may use various programmable parameters to allow support for the full JEDEC range of devices in accordance with various known specifications. Firmware may be used to drive the DDR initialization sequence and then turn control over to the protocol engine  108 . The protocol engine  108  may provide periodic refreshes that may be placed between quantum burst accesses. The protocol engine  108  control may support a prefetch low-power mode as an automatic hardware initiated mode and a self-refresh low-power mode as a firmware initiated mode. The protocol engine  108  may also bank interleave each access with the previous access by opening the bank while the prior data transfer is still occurring. Other optimizations may be provided by the protocol engine  108  to reduce the overhead as much as possible in the implementation of the DDR sequences. 
         [0029]    The subsystem  306  may be implemented as one or more hardmacro memory PHYs, such as the DDR 1 / 2  or DDR 2 / 3  PHYs. The subsystem  306  may be interfaced to the memory circuits  110   a - 110   n  through the DDR pads  322 . The DDR pads  322  may be standard memory I/F pads which may manage the inter-signal skew and timing. The DDR pads  322  may be implemented as modules that may either be used directly or provided as a reference to customer logic where the DDR pads  332  will be implemented. The DDR pads  322  may include aspects such as BIST pads, ODT, and/or controlled impedance solutions to make the DDR PHY  306  simple to integrate. 
         [0030]    The register interfaces  310  and  318  may allow the memory controller module  304  and DDR PHY  306  to reside on a bus for accessing registers within the subsystem. In one example, an ARM APB3 bus may be implemented. However, the particular type of bus implemented may be varied to meet the design criteria of a particular implementation. These registers may or may not directly allow access to the external memory  110   a  and/or the internal SRAM  110   b.  The signals CHANNEL_CLIENTa-n may initiate writes and/or reads to the external memory  110   a  and/or the internal SRAM  110   b.    
         [0031]    Referring to  FIG. 3 , a computer system  600  with a hard disk drive is shown. The system  600  may comprise a CPU subsystem circuit  602  and an I/O subsystem circuit  604 . The circuit  602  generally comprises a CPU circuit  606 , a memory circuit  608 , a bridge circuit  610  and a graphics circuit  612 . The circuit  604  generally comprises a hard disk drive  614 , a bridge circuit  616 , a control circuit  618  and a network circuit  620 . 
         [0032]    Referring to  FIG. 4 , a block diagram of a hard disk drive  614  is shown. The hard disk drive  614  generally comprises the DDR memory circuit  108 , a motor control circuit  702 , a preamplifier circuit  704  and a system-on-chip circuit  706 . The circuit  706  may comprise a hard disk controller circuit  700  and a read/write channel circuit  708 . The hard disk controller circuit  700  may transfer data between a drive and a host during read/write. The hard disk controller circuit  700  may also provide servo control. The motor control circuit  702  may drive a spindle motor and a voice coil motor. The preamplifier circuit  704  may amplify signals to the read/write channel circuit  708  and for head write data. 
         [0033]    Referring to  FIG. 5 , a block diagram of a hard disk controller  700  is shown. The hard disk controller  700  generally comprises the memory controller circuit  304 , a host interface client circuit  802 , a processor subsystem client circuit  804 , a servo controller client circuit  806  and a disk formatter client circuit  808 . In one example, the circuit  804  may be a dual ARM processor subsystem. However, the particular type of processor implemented may be varied to meet the design criteria of a particular implementation. The protocol engine circuit  106  located in the memory controller  304  may manage data movement between a data bus and host logic from the host interface client circuit  802 . The host interface client circuit  802  may process commands from the protocol engine  106 . The host interface client circuit  802  may also transfer data to and/or from the memory controller circuit  304  and the protocol engine  106 . The disk formatter client circuit  808  may move data between the memory controller circuit  304  and media. The disk formatter client circuit  808  may also implement error correcting code (ECC). The processor subsystem client circuit  804  may configure the registers in the memory controller  304  and block  306  for the purpose of performing initialization and training sequences to the memory controller  304 , the circuit  306 , the memory  110   a  and/or the memory  316   b    
         [0034]    As used herein, the term “simultaneously” is meant to describe events that share some common time period but the term is not meant to be limited to events that begin at the same point in time, end at the same point in time, or have the same duration. 
         [0035]    As would be apparent to those skilled in the relevant art(s), the signals illustrated in  FIGS. 1-5  represent logical data flows. The logical data flows are generally representative of physical data transferred between the respective blocks by, for example, address, data, and control signals and/or busses. The system represented by the circuit  100 , and the various sub-components, may be implemented in hardware, software or a combination of hardware and software according to the teachings of the present disclosure, as would be apparent to those skilled in the relevant art(s). 
         [0036]    The present invention may be implemented by the preparation of ASICs (application specific integrated circuits), Platform ASICs, FPGAs (field programmable gate arrays), PLDs (programmable logic devices), CPLDs (complex programmable logic device), sea-of-gates, RFICs (radio frequency integrated circuits), ASSPs (application specific standard products), monolithic integrated circuits, one or more chips or die arranged as flip-chip modules and/or multi-chip modules or by interconnecting an appropriate network of conventional component circuits, as is described herein, modifications of which will be readily apparent to those skilled in the art(s). 
         [0037]    While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention.