Abstract:
A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates generally to the field of semiconductor packaging, and more particularly to a wafer level package (WLP) with a substrate-less or TSV-less (TSV: Through Substrate Via) interposer and a method for manufacturing the same. 
         [0003]    2. Description of the Prior Art 
         [0004]    As known in the art, fan-out wafer-level packaging (FOWLP) is a packaging process in which contacts of a semiconductor die are redistributed over a larger area through a redistribution layer (RDL) that is typically formed on a substrate such as a TSV interposer. 
         [0005]    The RDL is typically defined by the addition of metal and dielectric layers onto the surface of the wafer to re-route the I/O layout into a looser pitch footprint. Such redistribution requires thin film polymers such as BCB, PI or other organic polymers and metallization such as Al or Cu to reroute the peripheral pads to an area array configuration. 
         [0006]    The TSV interposer is costly because fabricating the interposer substrate with TSVs is a complex process. Thus, forming FOWLP products that includes an interposer having a TSV interposer may be undesirable for certain applications. 
         [0007]    In wafer level packaging, the wafer and the dies mounted on the wafer are typically covered with a relatively thick layer of the molding compound. The thick layer of the molding compound results in increased warping of the packaging due to coefficient of thermal expansion (CTE) mismatch, and the thickness of the packaging. It is known that wafer warpage continues to be a concern. 
         [0008]    Warpage can prevent successful assembly of a die-to-wafer stack because of the inability to maintain the coupling of the die and wafer. Warpage issue is serious especially in a large sized wafer, and has raised an obstacle to a wafer level semiconductor packaging process that requires fine-pitch RDL process. Therefore, there remains a need in the art for an improved method of manufacturing wafer level packages. 
       SUMMARY OF THE INVENTION 
       [0009]    The present invention is directed to provide an improved semiconductor device and fabrication method that is capable of reducing the total used amount of molding compound on the interposer, thereby alleviating post-molding warpage. 
         [0010]    In one aspect of the invention, a semiconductor device includes an interposer having a first side and a second side opposite to the first side; at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps; at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area; a molding compound disposed on the first side, the molding compound covering the at least one active chip and the at least one dummy chip; and a plurality of solder bumps mounted on the second side. 
         [0011]    According to one embodiment of the invention, the dummy chip is mounted on the first side through a plurality of second bumps disposed on dummy pads within the peripheral area. 
         [0012]    According to another embodiment of the invention, the dummy chip is mounted directly on the first side with an adhesive. 
         [0013]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]    The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute apart of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings: 
           [0015]      FIG. 1  to  FIG. 8  are schematic diagrams showing an exemplary method for fabricating a wafer level package (WLP) with a substrate-less (or TSV-less) interposer according to one embodiment of the invention, wherein, 
           [0016]      FIG. 1  to  FIG. 7  are schematic, cross-sectional views of the intermediate product during the manufacturing process of the WLP; 
           [0017]      FIG. 8  is a top view showing the exemplary layout of the active chips and dummy chips on the RDL; and 
           [0018]      FIG. 9  to  FIG. 13  are schematic diagrams showing an exemplary method for fabricating a WLP with a substrate-less interposer according to another embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0019]    In the following detailed description of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments maybe utilized and structural changes may be made without departing from the scope of the present invention. 
         [0020]    The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled. 
         [0021]    One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale. The terms “die”, “semiconductor chip”, and “semiconductor die” are used interchangeable throughout the specification. 
         [0022]    The terms wafer and substrate used herein include any structure having an exposed surface onto which a layer is deposited according to the present invention, for example, to form the circuit structure such as a redistribution layer (RDL). The term substrate is understood to include semiconductor wafers, but not limited thereto. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. 
         [0023]    Please refer to  FIG. 1  to  FIG. 8 .  FIG. 1  to  FIG. 8  are schematic diagrams showing an exemplary method for fabricating a wafer level package (WLP) with a substrate-less (or TSV-less) interposer according to one embodiment of the invention. 
         [0024]    As shown in  FIG. 1 , a carrier  300  is prepared. The carrier  300  may be a releasable substrate material with an adhesive layer (not explicitly shown) . At least a dielectric layer or a passivation layer  310  is then formed on a top surface of the carrier  300 . The passivation layer  310  may comprise organic materials such as polyimide (PI) or inorganic materials such as silicon nitride, silicon oxide or the like. 
         [0025]    As shown in  FIG. 2 , subsequently, a redistribution layer (RDL)  410  is formed on the passivation layer  310 . The RDL  410  may comprise at least one dielectric layer  412  and at least one metal layer  414 . The dielectric layer  412  may comprise organic materials such as polyimide (PI) or inorganic materials such as silicon nitride, silicon oxide or the like, but not limited thereto. The metal layer  414  may comprise aluminum, copper, tungsten, titanium, titanium nitride, or the like. 
         [0026]    According to the illustrated embodiment, the metal layer  414  may comprise a plurality of bump pads  415   a  and dummy pads  415   b  exposed from a top surface of the dielectric layer  412 . The bump pads  415   a  are disposed within a chip mounting area, while the dummy pads  415   b  are disposed outside the chip mounting area such as a peripheral area around the chip mounting area. 
         [0027]    According to the illustrated embodiment, the dummy pads  415   b  are isolated, inactive pads, which are not electrically connected to other circuitry in the RDL  410 . In other words, no signal will pass through these dummy pads  415   b  during operation of the chip package. 
         [0028]    As shown in  FIG. 3 , a plurality of bumps  416   a  and  416   b  such as micro-bumps maybe formed on the RDL  410  for further connections. The bumps  416   a  may be directly formed on respective bump pads  415   a  in the metal layer  414 . The bumps  416   b  may be directly formed on respective dummy pads  415   b  in the metal layer  414 . In some embodiments, a passivation layer or a dielectric layer (not shown) may be formed on the RDL  410  before the formation fo the bumps  416   a  and  416   b.    
         [0029]    As shown in  FIG. 4 , after the formation of the bumps  416   a  and  416   b,  individual flip-chips or dies  420   a  with their active sides facing down toward the RDL  410  are then mounted on the RDL  410  through the bumps  416   a  to thereby forming a stacked chip-to-wafer (C2W) construction. These individual flip-chips or dies  420   a  are active integrated circuit chips with certain functions, for example, GPU (graphic processing unit), CPU (central processing unit), memory chips, etc. 
         [0030]    According to the illustrated embodiment, the dummy chips  420   b  are mounted in the peripheral area  104  around the chip mounting area  102  through the bumps  416   b.    FIG. 8  illustrates an example of the arrangement of the active chips  420   a  and the dummy chips  420   b.  For example, the dummy chips  420   b  may be dummy silicon chips, dies or pieces having dimensions or sizes similar to that of the chip  420   a , but not limited thereto. It is to be understood that other materials such as metal, glass or ceramic may be used. 
         [0031]    Optionally, an underfill (not shown) may be applied under each chip or die  420   a / 420   b.  Thereafter, a thermal process may be performed to reflow the bumps  416   a  and  416   b.    
         [0032]    As shown in  FIG. 5 , after the die-bonding process, a molding compound  500  is applied. The molding compound  500  covers the attached active chips  420   a  and the dummy chips  420   b  and the top surface of the RDL  410 . The molding compound  500  may be subjected to a curing process. The mold compound  500  may comprise a mixture of epoxy and silica fillers, but not limited thereto. 
         [0033]    Optionally, a top portion of the molding compound  500  may be polished away to expose a top surfaces of the active chips  420   a  and the dummy chips  420   b.    
         [0034]    Since most of the peripheral area around the chip mounting area is occupied by the dummy chips  420   b,  the used amount of the molding compound  500  is reduced, and therefore the warpage of the substrate or wafer is alleviated or avoided. According to the illustrated embodiment, these dummy chips  420   b  may also be referred to as warpage-control dummy chips. 
         [0035]    As shown in  FIG. 6 , after the formation of the molding compound  500 , the carrier  300  is removed or peeled off to expose the passivation layer  310 , thereby forming a TSV-less interposer  301 . The de-bonding of the carrier  300  may be performed by using a laser process or UV irradiation process, but not limited thereto. 
         [0036]    To peel off the carrier  300 , another temporary carrier substrate (not shown) may be attached to the molding compound  500 . After the de-bonding of the carrier  300 , openings may be formed in the passivation layer  310  to expose respective solder pads, and then solder bumps or solder balls  520  maybe formed on the respective solder pads. 
         [0037]    Thereafter, as shown in  FIG. 7 , a dicing process is performed to separate individual wafer level packages  10  from one another. 
         [0038]    Please refer to  FIG. 9  to  FIG. 13 .  FIG. 9  to  FIG. 13  are schematic diagrams showing an exemplary method for fabricating a wafer level package (WLP) with a substrate-less (or TSV-less) interposer according to another embodiment of the invention, wherein like numeral numbers designate like regions, layers or elements. 
         [0039]    As shown in  FIG. 9 , likewise, a redistribution layer (RDL)  410  is formed on the passivation layer  310 . The RDL  410  may comprise at least one dielectric layer  412  and at least one metal layer  414 . The dielectric layer  412  may comprise organic materials such as polyimide (PI) or inorganic materials such as silicon nitride, silicon oxide or the like, but not limited thereto. The metal layer  414  may comprise aluminum, copper, tungsten, titanium, titanium nitride, or the like. 
         [0040]    According to the illustrated embodiment, the metal layer  414  may comprise a plurality of bump pads  415  exposed from a top surface of the dielectric layer  412 . The bump pads  415  are disposed within a chip mounting area  102 . In general, no bump pads are formed within a peripheral area  104  around the chip mounting area  102 .A plurality of bumps  416  such as micro-bumps may be formed on the RDL  410  for further connections. The bumps  416  may be directly formed on respective bump pads  415  in the metal layer  414 . 
         [0041]    As shown in  FIG. 10 , after the formation of the bumps  416 , individual flip-chips or dies  420   a  with their active sides facing down toward the RDL  410  are then mounted on the RDL  410  through the bumps  416  to thereby forming a stacked chip-to-wafer (C2W) construction. Optionally, an underfill (not shown) may be applied under each chip or die  420   a.  Thereafter, a thermal process may be performed to reflow the bumps  416 . 
         [0042]    According to the illustrated embodiment, dummy chips  420   b  are mounted on the dielectric layer  412  of the RDL  410  within the peripheral area  104  around the chip mounting area  102  by using an adhesive  430 . 
         [0043]    As shown in  FIG. 11 , after the die-bonding process, a molding compound  500  is applied. The molding compound  500  covers the attached active chips  420   a  and the dummy chips  420   b  and the top surface of the RDL  410 . The molding compound  500  may be subjected to a curing process. Optionally, a top portion of the molding compound  500  may be polished away to expose a top surfaces of the active chips  420   a  and the dummy chips  420   b.    
         [0044]    As shown in  FIG. 12 , after the formation of the molding compound  500 , the carrier  300  is removed or peeled off to expose the passivation layer  310 , thereby forming a TSV-less interposer  301 . The de-bonding of the carrier  300  may be performed by using a laser process or UV irradiation process, but not limited thereto. 
         [0045]    To peel off the carrier  300 , another temporary carrier substrate (not shown) may be attached to the molding compound  500 . After the de-bonding of the carrier  300 , openings may be formed in the passivation layer  310  to expose respective solder pads, and then solder bumps or solder balls  520  maybe formed on the respective solder pads. The temporary carrier substrate is then removed. 
         [0046]    Thereafter, as shown in  FIG. 13 , a dicing process is performed to separate individual wafer level packages  10   a  from one another. 
         [0047]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.