Abstract:
A spread-period clock generator (SPC) counts basic clock pulses (XK) to generate output pulses (EQ) with varying periods, and has means (controlled by signal QS) for switching between a first mode, in which counting is carried out in response to the leading edges of the basic clock pulses (CK), and a second mode, in which counting is carried out in response to the trailing edges of the basic clock pulses (CK). Accordingly, if mode switching (signal QS) is carried out during a counting operation, the counting period is altered by a portion of a basic clock period (CK). Thus, the number of different periods of the output pulses can be increased without increasing the basic clock frequency (input WC, signal LK, CK).

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    This invention relates to a method and apparatus for generating pulse trains with variable interpulse intervals, for example to be employed to drive suitable waveform generators utilized in multi-user active sensor systems and particularly, but not exclusively, in automotive radar systems designed to perform functions of obstacle-detection and/or collision avoidance. 
         [0003]    2. Description of the Prior Art 
         [0004]    In a multi-user environment, active sensors may transmit their interrogating signals simultaneously and asynchronously so that not only must each receiver recognize and detect a response to its own transmitted signal, but it must be able to do so in the presence of all other transmitted signals. 
         [0005]    For example, in automotive applications, many similar obstacle-detection systems should be capable of operating in the same region, and also be capable of sharing the same frequency band. To avoid mutual interference, each sensor system should use a distinct signal, preferably uncorrelated with the signals employed by all other systems. Because it is not possible to predict which of the many similar systems will be operating in a particular environment, it is not practical to assign a distinct waveform to each of them. 
         [0006]    The problem of constructing a large set of distinct waveforms from a single underlying ‘template’ waveform can be solved, at least partly, by exploiting in a judicious way some random or pseudorandom mechanism in the process of the waveform construction. 
         [0007]    One practical approach may exploit the principle of driving a digital waveform generator by clock pulses with random (or pseudo-random) parameters. 
         [0008]    Although the same digital waveform generator will be employed for producing a plurality of waveforms, each waveform will be distinct, having resulted from a clock pulse train with different characteristics. In this context, the waveform generator itself can be viewed as a mapping device applied to convert a set of different realizations of a randomised pulse train into a corresponding set of distinct waveforms. 
         [0009]    The suitability of such obtained waveforms to multi-user applications will depend on the autocorrelation properties of the underlying ‘template’ waveform, and also on the statistical distribution of frequency (or period) of the employed clock generator. Therefore, the availability of clock generators with suitably randomised frequency or period is of practical importance in multi-user sensor environment. 
         [0010]    Commercially available, the so-called ‘spread-spectrum’, clock oscillators can provide clock pulses with uniform frequency jitter. Some of the available products are listed below:
       Dallas Maxim DS1086 Spread-Spectrum EconOscillator   Linear Technology. LTC6902 Multiphase Oscillator with Spread Spectrum Modulation   Epson SG-9001CA High-Frequency Crystal Oscillator with Spread Spectrum       
 
         [0014]    In some applications, however, such as those disclosed in European Patent Application No. 05256583.5, filed 24 Oct. 2005, it is the period, and not the frequency, that should be spread uniformly. Therefore, it would be advantageous to develop a technique for the generation of clock pulses with uniformly spread period. 
         [0015]    One possible configuration of a spread-period clock generator is based on a well-known technique of converting voltage levels into time intervals with the use of a comparator whose one input is driven by a sequence of voltage ramps while the other (reference) input is kept at a threshold level which varies from ramp-to-ramp. In the ramp sequence, a new voltage ramp is generated each time the threshold level has been exceeded by the previous ramp. As a result, a sequence of time-varying intervals is produced, each interval being determined by two consecutive time marks occurring at the times when the two comparator inputs are of the same level. 
         [0016]      FIG. 1  is a block diagram of a spread-period clock generator SPC disclosed in European Patent Application No. 05256583.5. The generator comprises a synchronous (K+1)-bit binary counter SBC driven by a suitable master clock generator CKG, a K-bit pseudorandom binary word generator BWG, a control unit CTU, a transition-matrix circuit TMX and a comparator CMR. Each state of the counter SBC can be regarded as a sign/magnitude representation of numbers: the most significant bit (MSB) represents the sign, and the remaining K bits constitute a binary representation of the magnitude. 
         [0017]    The generator SPC produces pulses SP with uniform distribution of interpulse intervals in such a way that during each full cycle of operation, each interval value occurs exactly once. However, on separate cycles, the interval values may appear in different order due to a suitable permutation implemented by the transition-matrix circuit TMX. 
         [0018]    Operations performed by the spread-period clock generator SPC to produce a single time interval are the following: 
         [0019]    1. At the start of each interval, the pseudorandom binary word generator BWG in response to a pulse at input CK supplies a non-negative K-bit word {IK, . . . , I 2 , I 1 } which is converted by the transition-matrix circuit TMX into another non-negative K-bit word {OK, . . . , O 2 , O 1 } of value RN; hence, RN can assume one of the following values: 0, 1, . . . , 2 K −1. 
         [0020]    2. The initial state of the counter SBC is set to some negative value −NV corresponding to the required shortest interpulse interval T min =(NV)T c , where T c  is the period of clock pulses supplied by the CKG. The longest interpulse interval T max  can be determined from T max =T min +(2 K −1)T c . 
         [0021]    3. The (K+1)-bit binary counter SBC is ‘counting up’ clock pulses obtained from the master clock generator CKG. Hence, its consecutive states are represented by the following values: −NV, −NV+1, -NV+2, . . . . Finally, as soon as the current state of the counter reaches the non-negative value RN, the comparator CMR produces a short pulse SP that:
       resets the counter SBC via input RS to its initial state −NV;   prompts the pseudorandom binary word generator BWG via input CK to supply a new K-bit word.       
 
         [0024]    The spread-period clock generator SPC operates continually, and the duration of each produced time interval is determined by time instants at which two consecutive pulses SP have occurred. 
         [0025]    Because consecutive states of the counter SBC approximate digitally a linearly rising ramp and because binary words supplied by the pseudorandom binary word generator BWG are uniformly distributed, the distribution of the time intervals between consecutive pulses SP produced by the comparator CMR will also be uniform. 
         [0026]    The pseudorandom binary word generator BWG may, for example, be a conventional K-stage shift register with linear feedback, an arrangement well known to those skilled in the art. In such a case, each word from the allowable range will occur exactly once during each cycle of operation, and the order of word appearance will depend on the form of employed feedback. A new word will be supplied in response to a pulse appearing at input CK. 
         [0027]    The operation of the circuit TMX can be explained by way of an example shown in  FIG. 2 . The pattern of 8 dots (K=8) in the 8×8 matrix corresponds to input-output connections realized by the circuit TMX. Therefore, in this case, O 1 =I 7 , O 2 =I 1 , . . . , O 7 =I 2  and O 8 =I 5 . Obviously, each column and each row of the matrix must contain exactly one dot. 
         [0028]    Although many different dot patterns can be devised for this application, it may be advantageous to utilize a dot pattern belonging to a class of patterns referred to as ‘K non-attacking queens’, such as the dot pattern shown in  FIG. 2 . Also, other well-known designs, such as those based on Costas arrays, may prove very useful in some specific applications. 
         [0029]    In accordance with the above disclosure, a different dot pattern may be used for different cycles of the binary word generator BWG. A particular dot pattern may be selected from a predetermined set of patterns in a deterministic or non-deterministic fashion. The pattern selection task is carried out by the control unit CTU. 
         [0030]    In addition to permutations obtained from changing the input-output connection matrix in the TMX, the form of feedback used by the generator BWG may also be varied. A particular feedback function can be selected from a predetermined set of functions in a deterministic or non-deterministic fashion. The feedback selection task is also carried out by the control unit CTU. 
         [0031]    Previously proposed spread-period clock generators are capable of producing interpulse time intervals that may only assume integral multiplies of the master clock period. For example, when the master clock frequency is equal to 100 MHz, intervals between generated pulses may only assume values: 10 ns, 20 ns, 30 ns, etc. However, in practical applications, it would be advantageous to generate time intervals of duration being integral multiplies of a fraction (e.g., a half) of the master clock period, while still utilizing flip-flops operating at the same original switching speed. 
       SUMMARY OF THE INVENTION 
       [0032]    Aspects of the present invention are set out in the accompanying claims. 
         [0033]    A spread-period clock generator according to the invention counts basic clock pulses to generate output pulses with varying periods, and has means for switching between a first mode, in which counting is carried out in response to the leading edges of the basic clock pulses, and a second mode, in which counting is carried out in response to the trailing edges of the basic clock pulses. Accordingly, if mode switching is carried out during a counting operation, the counting period is altered by a portion of a basic clock period. Thus, the number of different periods of the output pulses can be increased without increasing the basic clock frequency and without glitches occurring in the output. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0034]    An arrangement embodying the present invention will now be described by way of example with reference to the accompanying drawings. 
           [0035]      FIG. 1  is a block diagram of a spread-period clock generator SPC disclosed in European Patent Application No. 05256583.5. 
           [0036]      FIG. 2  is an example of a transition matrix used in the generator of  FIG. 1 . 
           [0037]      FIG. 3  is a block diagram of a spread-period clock generator according to the invention. 
           [0038]      FIG. 4   a  is a circuit diagram of a clock waveform resolver/recombiner of the spread-period clock generator of  FIG. 3 . 
           [0039]      FIG. 4   b  depicts waveforms generated in the clock waveform resolver/recombiner of  FIG. 4   a.    
           [0040]      FIG. 5  is a diagram of a timing/control unit of the spread-period clock generator of  FIG. 3 . 
           [0041]      FIG. 6  shows one example of a pseudorandom time-interval generator utilized by the spread-period clock generator of  FIG. 3 . 
           [0042]      FIG. 7  depicts the fifteen allowable states of a register of the time-interval generator of  FIG. 6 . 
           [0043]      FIG. 8   a  shows the waveforms at parts of the time-interval generator of  FIG. 6   
           [0044]      FIG. 8   b  shows the sequences of states of components of the time-interval generator of  FIG. 6 . 
           [0045]      FIG. 9  is a complete diagram of the spread-period clock generator of  FIG. 3 . 
           [0046]      FIG. 10  depicts a cyclic sequence of time intervals produced by the spread-period clock generator of  FIG. 3 . 
           [0047]      FIG. 11  depicts one complete cycle of a pulse train obtained experimentally from a spread-period clock generator constructed in accordance with the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0048]    A spread-period clock generator arranged to operate in accordance with the present invention is shown in  FIG. 3  and comprises three functional blocks: 
         [0049]    1. a clock waveform resolver/recombiner—block  100 ; 
         [0050]    2. a timing/control unit with a divide-by-four circuit—block  102 ; 
         [0051]    3. a pseudorandom time-interval generator—block  104 . 
         [0052]      FIG. 3  shows the flow of timing and control signals between the functional blocks to indicate their interdependence. For reference purposes, each box that represents a functional block contains symbols identifying main components, such as flip-flops, logic gates and other circuits employed by the block. 
       Pseudorandom Time-Interval Generator  104   
       [0053]    Block  104  is arranged to implement a pseudorandom time-interval generator which is used in the present embodiment to constitute a variable time-interval generator. In the following, only one specific implementation of block  104  will be discussed in more detail, mainly to facilitate the understanding of the present invention. However, it will be obvious to those skilled in the art that suitable alterations, modifications, and variations will lead to functionally equivalent systems. For example, an arrangement functioning as described with reference to  FIG. 1  could be used instead. 
         [0054]      FIG. 6  is one example of a pseudorandom time-interval generator which can be utilized by the present embodiment. The generator  104  includes a four-stage linear feedback shift register LFSR, a five-bit synchronous binary counter SBC and a comparator CMR. 
         [0055]    The register LFSR comprises four D-type flip-flops forming a shift register triggered by pulses Q 0 . The input of the shift register is driven by a feedback circuit FBL, which implements the following logic function 
         [0000]        FB=     S 0 ⊕    S 1 +    S 0 ·    S 1 ·    S 2 ·    S 3   
         [0000]    in which the second term is used to ensure self-start operation. Fifteen allowable states {S 3 , S 2 , S 1 , S 0 } of the register LFSR form one complete period of a cyclic sequence shown in  FIG. 7 . 
         [0056]    The synchronous binary counter SBC may be implemented as a conventional synchronous five-bit binary counter; however, the equivalent function can be performed by a four-bit synchronous binary counter followed by a single toggle flip-flop supplying the most significant bit C 4 . The counter SBC is driven by counter clock pulses XK. 
         [0057]    The counter SBC also uses a preset input PT to set the initial state of the counter to a predetermined state {C 0 }={C 4 , C 3 , C 2 , C 1 , C 0 }, where C 4  is the most significant bit (MSB) and CO is the least significant bit (LSB). The initial state {C 0 } is chosen from a set of ‘negative’ states (i.e., those with C 4 =1) in response to a suitable binary word applied to ‘preset select’ input PS. It is assumed that the preset action occurs on the rising edge of a pulse Q 0  appearing at input PT. 
         [0058]    The comparator CMR is a combinatorial circuit implementing the logic function 
         [0000]        EQ =  C4 ·    C 3⊕ S 3 ·    C 2⊕ S 2 ·    C 1⊕ S 1 ·    C 0⊕ S 0   
         [0059]    The comparator receives four input values {S 3 , S 2 , S 1 , S 0 } from the register LFSR, and another five input values {C 4 , C 3 , C 2 , C 1 , C 0 } from the counter SBC. An output pulse (logic) signal EQ is supplied to a timing/control unit. 
         [0060]    Varying time intervals are produced as follows: 
         [0061]    While the register LFSR remains in one of the 15 allowable states, the counter SBC is ‘counting up’ clock pulses XK, thereby changing its state in response to each such pulse. The counting process starts from a selected initial SBC state {C 0 }; then it runs continually, and terminates when the current counter state {C} reaches an LFSR state, denoted by {S*}, which remains steady during the entire counting process. At this time instant, i.e., when {C}≡{S*}, the comparator CMR changes its logic state from ‘0’ to ‘1’, and a pulse corresponding to this transition is sent via output EQ to the timing/control unit  104 . 
         [0062]    Next, the register LFSR is advanced by a pulse Q 0  to its next steady state {S*}, the counter SBC is preset via input PT to its original initial ‘negative’ state {C 0 }, and the entire procedure is repeated. 
         [0063]    The spread-period clock generator operates continually, and the duration of each produced time interval is determined by the time instants at which two consecutive pulses Q 0  have occurred at output VC. 
       Timing/Control Unit  102   
       [0064]    A circuit diagram of block  102  is shown in  FIG. 5 . Block  102  comprises four D-type flip-flops (FF 0 , FF 1 , FC 0 , FC 1 ), an inverting buffer IB, an AND gate (AND) and an auxiliary delay A. 
         [0065]    Flip-flops FF 0  and FF 1  supply signals Q 0  and Q 1  that are used by the AND gate to generate a pulse PP that follows in a synchronous manner pulse EQ obtained from block  104 . A sequence of pulses PP is employed as a clock signal by a divide-by-four circuit comprising flip-flops FC 0  and FC 1 . An output waveform SI of the divider circuit is used to control the mode of operation of the counter clock generator (see below). 
         [0066]    Block  102  also supplies a pulse Q 0  used in block  104  to perform ‘preset’ and ‘clock’ functions. 
       Clock Waveform Resolver/Recombiner  100   
       [0067]      FIG. 4   a  is a circuit diagram of a clock waveform resolver/recombiner  100 . All relevant waveforms are depicted in  FIG. 4   b.    
         [0068]    Block  100  comprises a master (or basic) clock generator MC, and a counter clock generator is formed by an inverting buffer BI, a non-inverting buffer BN, three D-type flip-flops (FZ 1 , FZ 2 , FFS) and three Exclusive-OR gates (XR 1 , XR 2 , XR 3 ). 
         [0069]    The flip-flop FZ 1  has a data input connected to its inverted output. The flip-flop FZ 2  has a data input connected to the output of flip-flop FZ 1 . The master clock waveform CK and its inverted version are used to clock flip-flops FZ 1  and FZ 2 , respectively, to produce binary waveforms Z 1  and Z 2  that can be regarded as two half-frequency ‘digital cosine/sine’ components of the master clock waveform. The waveform Z 1  has edges produced in response to the rising edges of the basic clock waveform CK, which is applied to the clock input of the flip-flop FZ 1 . The edges of the waveform Z 2  are produced in response to the trailing edges of the basic clock pulses CK, because the clock input of flip-flop FZ 2  receives inverted clock pulses  CK . 
         [0070]    The waveforms Z 1  and Z 2  are passed, respectively, through two Exclusive-OR gates, XR 1  and XR 2 , to produce corresponding components, Z 1 M and Z 2 D. The Exclusive-OR gate XR 2  has another input receiving a logic 0 level, so the component Z 2 D is simply a slightly delayed copy of Z 2 . The Exclusive-OR gate XR 1  has another input receiving a signal QS, so the component Z 1 M, in addition to being slightly delayed with respect to Z 1 , will either be a copy of Z 1  (when QS=0), or an inverted (negated) copy of Z 1  (when QS=1). 
         [0071]    The two waveforms Z 1 M and Z 2 D are combined by Exclusive-OR gate XR 3  to generate waveform XK. The reconstructed waveform XK obtained at the output of gate XR 3  will ‘mirror’ either the master clock waveform CK or its inversion. Thus, the rising edge of the counter clock pulses XK will be generated in response to the rising edge of the basic clock CK, or in response to the falling edge, depending on the mode of operation as controlled by the state of signal QS. Such an operation can be used to introduce a fixed delay step between consecutive rising edges of XK; those edges are shown symbolically in  FIG. 4   b  as a sequence of impulses XK*. The waveform XK is utilized by blocks  102  and  104  as a counter clock pulse train with a stepped delay. 
         [0072]    When the master clock waveform CK is symmetric (i.e., it has a unit mark/space ratio), the waveform Z 1  is a π/2 phase-delayed version of waveform Z 2 . Also, the value of the fixed delay step which can be introduced into the pulse train XK* is equal to one half of the period of the master clock MC. For example, for master clock frequency of 100 MHz, the delay step will be equal to 5 ns. 
         [0073]    The main role of gate XR 2  is to compensate for the propagation delay introduced by gate XR 1  in the path of component Z 1 ; however, gate XR 2  can also be employed to invert independently component Z 2 . 
         [0074]    The fixed delay step is introduced in the reconstructed waveform XK each time the waveform QS changes its state. The waveform QS is supplied by flip-flop FFS in synchronism with clock CK. The flip-flop HIS is driven by a signal SI obtained from the divide-by-four circuit of the timing/control unit  102 . 
         [0075]    The above-described spread-period generator, shown in full in  FIG. 9 , operates as follows. 
         [0076]    Each time the comparator CMR establishes that the counter SBC has reached the current set count established by the register LFSR, a signal EQ is sent to the timing/control unit  102 . This is clocked into the flip-flop FF 0  by the counter clock signal XK. The output of the flip-flop FF 0  forms the signal Q 0  used as described above to start a new counting cycle, in which the counter counts up to a new count set by the register LFSR. 
         [0077]    The signal Q 0  is also sent to the flip-flop FF 1 , which is clocked by an inverted version of the counter clock signal XK. The output of this flip-flop FF 1  is the signal Q 1  which is combined in the AND gate with signal Q 0  to provide the output signal PP. The signal PP is a pulse which appears once after each counting cycle. This is divided by four using the flip-flops FC 0  and FC 1 , and then delayed by delay A, to form signal SI. As indicated above, signal SI is clocked by the basic clock pulse CK in flip-flop FFS to form the signal QS used to switch the mode of the counter clock signal generator  100 . The signal SI is slightly delayed by the auxiliary delay A to ensure a suitable set-up time for flip-flop FFS. 
         [0078]    Because of this arrangement, a single cycle of the signal QS extends over four complete count operations, or cycles, of the counter SBC. Each state change of signal QS occurs shortly after the beginning of a new count cycle. The state changes occur in alternate count cycles, with no state change occurring in intervening count cycles (see  FIG. 4 ). 
         [0079]    Accordingly, for each steady state {S*} of the register LFSR, two different time intervals will be produced, in one of which a counter clock pulse XK is delayed by the change of state of the signal QS, and one in which no such delay occurs. Consequently, although one complete period of the linear-feedback shift register LFSR comprises 15 distinct states, the number of different time intervals produced by the system will be equal to 30 (also, because 15 and 2 are relative primes). 
         [0080]    In order to facilitate the understanding of the operation of the embodiment, a specific example will now be considered. 
       Example 
       [0081]    Assume that an initial ‘negative’ state {C 0 } of the counter SBC has been selected as 
         [0000]      {C 0 }={1 1 1 0 1} 
         [0082]    Neither of the first four ‘non-positive’ counter states 
         [0000]      {1 1 1 0 1}, {1 1 1 1 0}, {1 1 1 1 1}, {0 0 0 0 0} 
         [0000]    corresponds to one of the allowable ‘positive’ LFSR states; therefore, the shortest time interval will be obtained when {S*}={0 0 0 1}. The above four states will form the preamble associated with the selected initial SBC state {C 0 }, which will determine the duration of the shortest time interval. 
         [0083]    For example, if the frequency of the master clock MC equals 100 MHz, then the shortest time interval will be either 40 ns (if there is no delay in the pulse train XK) or 45 ns (if a delay step has been introduced into the pulse train XK). 
         [0084]    Similarly, because the greatest value represented by an allowable LFSR state {S*} is 
         [0000]      {S*}={1 1 1 1} 
         [0000]    the longest time interval produced by the system will be either 180 ns (if there is no delay in the pulse train XK) or 185 ns (if a delay step has been introduced into the pulse train XK). 
         [0085]      FIG. 8   a  depicts the waveforms produced by the shift register LFSR, the counter SBC and the comparator CMR. For reference purposes,  FIG. 8   b  shows the sequences of states of both counter SBC and register LFSR. 
         [0086]      FIG. 10  depicts a cyclic sequence of interval values produced by the spread-period generator (the corresponding LFSR states are also shown for reference). Inspection of the diagram shown in  FIG. 10  will reveal all the properties of the time intervals produced by the spread-period clock generator. The set counts successively established by the register LFSR are indicated in the outer circle and are presented in clockwise order. The intervals between output clocks are indicated by the inner two circles; the intervals in one inner circle occur in succession, followed by the intervals in the other inner circle. For each of the 15 set counts there are two intervals which differ by 5 nanoseconds. 
         [0087]      FIG. 11  depicts one complete cycle of a pulse train obtained experimentally from the spread-period clock generator constructed in accordance with the invention. The sequence of time intervals observed within a single cycle, {40, 115, 70, 55, . . . , 185, 100, 65}, measured in nanoseconds, follows the sequence of interval values shown in  FIG. 10 . 
         [0088]    For visualization purposes, all the interval values can be placed on a suitable Möbius band to display both ‘double-periodicity’ of the values and their mutual dependence. 
         [0089]    Both the shortest and the longest interval can be increased or decreased by the same amount by changing the initial ‘negative’ state {C 0 } of the counter SBC, thereby changing the preamble duration (as can be deduced from the state tables shown in  FIG. 8   b ). The initial state {C 0 }, chosen from a set of ‘negative’ states (i.e., those with C 4 =1), will be determined by a suitable binary word applied to ‘preset select’ input PS. 
         [0090]    Although it is desirable that the distribution of the intervals between the output clocks be uniform, as in the above embodiment, this is not essential. Also, the intervals may be ordered or may be selected in a random or psuedo-random manner. 
         [0091]    In the above arrangement, the basic clock signal CK is symmetric; however this is not essential. Accordingly, the phase difference between waveforms Z 1  and Z 2  may be different from π/2, in which case the magnitude of the introduced delay will depend on whether the signal QS changes to a high state or to a low state. 
         [0092]    In the above arrangement, either no additional delay or a single delay is introduced during each count cycle. Instead, multiple delays of varying number may be introduced during each cycle. Also, it is not essential for every one of the possible set counts to give rise to two or more different interpulse delays. 
         [0093]    The foregoing description of preferred embodiments of the invention has been presented for the purpose of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. In light of the foregoing description, it is evident that many alterations, modifications, and variations will enable those skilled in the art to utilize the invention in various embodiments suited to the particular use contemplated.