Abstract:
In a dead time control circuit, a delay circuit is connected to an input terminal and adapted to delay signals therethrough by a delay time corresponding to a dead time. A logic circuit has a first input connected via the delay circuit to the input terminal, a second input connected directly to the input terminal, and an output connected to an output terminal. The dead time having adjustable temperature characteristics.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a dead time control circuit used in a predriver for driving a half bridge circuit or a push-pull type output buffer for driving a load.  
         [0003]     2. Description of the Related Art  
         [0004]     In a push-pull type output buffer, two switching elements are connected between a power supply terminal and a ground terminal. When the switching elements are alternately turned ON and OFF to drive a load connected thereto, if the switching elements are simultaneously turned ON, a large penetration current flows through the push-pull type output buffer, so that the switching elements would be broken down.  
         [0005]     In order to avoid such a large penetration current, a simultaneous-OFF time or a dead time is introduced between the ON times of the switching elements. Generally, two dead time control circuits each corresponding to one of the switching elements are provided.  
         [0006]     A first prior art dead time control circuit is constructed by a delay circuit formed by two inverters connected in series for delaying an input signal and an AND circuit for receiving the input signal via the delay circuit and directly. This will be explained later in detail.  
         [0007]     In the above-described first prior art dead time control circuit, however, even when the delay time of the delay circuit fluctuates due to environmental factors such as temperature, power supply voltage, etc., it is impossible to adjust the delay time, i.e., the dead time.  
         [0008]     A second prior art dead time control circuit further includes a delay circuit formed by an external resistor and an external capacitor between the inverters of the first prior art dead time control circuit. Therefore, when the delay time fluctuates due to environmental factors, the delay time can be adjusted by the external resistor and the external capacitor. This also will be explained later in detail.  
         [0009]     The above-described second prior art dead time control circuit, however, is increased in size and manufacturing cost due to the external resistor and the external capacitor. Also, since the characteristics of the external resistor and the external capacitor per se fluctuate, it is impossible to accurately control the dead time.  
         [0010]     A third prior art dead time control circuit further includes two constant current sources connected to one of the inverters of the first prior art dead time control circuit, the constant current source including analogous circuit elements as in the other of the inverters. As a result, the response speed characteristic of one of the inverters is opposite to that of the other, so that the entire delay time of the dead time control circuit becomes stable. This also will be explained later in detail.  
       SUMMARY OF THE INVENTION  
       [0011]     In the above-described third prior art dead time control circuit, however, since the rising/falling characteristics of the output voltage have a positive temperature coefficient while the dead time determined by the two dead time control circuits has a negative temperature coefficient, a large penetration current would flow through the switching elements when the temperature is high.  
         [0012]     According to -the present invention, in a dead time control circuit, a delay circuit is connected to an input terminal and adapted to delay signals therethrough by a delay time corresponding to a dead time. A logic circuit has a first input connected via the delay circuit to the input terminal, a second input connected directly to the input terminal, and an output connected to an output terminal. The dead time having adjustable temperature characteristics. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]     The present invention will be more clearly understood from the description set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein:  
         [0014]      FIG. 1  is a circuit diagram illustrating a prior art digital audio apparatus;  
         [0015]      FIG. 2  is a circuit diagram illustrating a high-side dead time control circuit and a low-side dead time control circuit each as a first prior art dead time control circuit;  
         [0016]      FIG. 3  is a timing diagram for explaining the operation of the high-side dead time control circuit and the low-side dead time control circuit of  FIG. 2 ;  
         [0017]      FIG. 4  is a circuit diagram illustrating a high-side dead time control circuit and a low-side dead time control circuit each as a second prior art dead time control circuit;  
         [0018]      FIG. 5  is a circuit diagram illustrating a high-side dead time control circuit and a low-side dead time control circuit each as a third prior art dead time control circuit;  
         [0019]      FIG. 6  is a graph for showing the operating characteristics of the dead time control circuit of  FIG. 5 ;  
         [0020]      FIG. 7  is a circuit diagram illustrating a high-side dead time control circuit and a low-side dead time control circuit each as a first embodiment of the dead time control circuit according to the present invention;  
         [0021]      FIGS. 8A and 8B  are graphs for showing the operating characteristics of the dead time control circuits of  FIG. 7 ;  
         [0022]      FIG. 9  is a table for showing the operating characteristics of the dead time control circuits of  FIG. 7 ;  
         [0023]      FIG. 10  is a circuit diagram illustrating a first modification of the dead time control circuits of  FIG. 7 ;  
         [0024]      FIG. 11  is a circuit diagram illustrating a second modification of the dead time control circuits of  FIG. 7 ;  
         [0025]      FIG. 12  is a circuit diagram illustrating a high-side dead time control circuit and a low-side dead time control circuit each as a second embodiment of the dead time control circuit according to the present invention; and  
         [0026]      FIGS. 13, 14 ,  15  and  16  are circuit diagrams illustrating modifications of the dead time control circuits of  FIGS. 7, 10 ,  11  and  12 , respectively. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0027]     Before the description of the preferred embodiments, prior art dead time control circuits will be explained with reference to  FIGS. 1, 2 ,  3 ,  4 ,  5  and  6 .  
         [0028]     In  FIG. 1 , which illustrates a prior art digital audio apparatus, a pulse width modulator  100  powered by a relatively low power supply voltage such as 5V or 3V generates output voltages and transmits them to a high-side input terminal HI and a low-side input terminal LI of a predriver  200  powered by a relatively high power supply voltage such as 12V at its power supply terminal V DD . The predriver  200  generates output voltages at their high-side output terminal HO and low-side output terminal LO and transmits them to a half bridge circuit or a push-pull type output buffer  300  powered by a commercial power supply voltage such as 100V.  
         [0029]     The push-pull type output buffer  300  receives the output voltages at the high-side output terminal HO and the low-side output terminal LO of the predriver  200  to generate an output voltage OUT, thus driving a load  400 .  
         [0030]     The push-pull type output buffer  300  is constructed by two-enhancement-type N-channel MOS transistors  301 H and  301 L as switching elements connected in series between the power supply voltage terminal (100V) and the ground terminal GND.  
         [0031]     The common node between the MOS transistors  301 H and  301 L is connected to a high-side source terminal HS of the predriver  200  and the load  400 , and also is connected via a bootstrap capacitor  500  to a high-side bias terminal HB of the predriver  200 . Due to the presence of the bootstrap capacitor  500 , when the output voltage OUT is high, the voltage at the high-side source terminal HS is 100V and the voltage at the high-side bias terminal HB is 112V (=100V+12V), and, when the output voltage OUT is low, the voltage at the high-side source terminal HS is 0V and the voltage at the high-side bias terminal HB is 114V (=12V+V F ) where V F  is a forward voltage of the MOS transistor  301 L. That is, even when the MOS transistors  301 H and  301 L are turned ON and OFF, the voltage between the terminals of the bootstrap capacitor  500  can be maintained at 12V. In the push-pull type output circuit  300 , the MOS transistors  301 H and  301 L are alternately turned ON and OFF to drive the load  400 ; in this case, if the MOS transistors  301 H and  301 L are simultaneously turned ON, a large penetration current flows through the MOS transistors  301 H and  301 L, so that the MOS transistors  301 H and  301 L would be broken down. In order to avoid such a large penetration current, a simultaneous-OFF time or a dead time is introduced between the ON time of the MOS transistor  301 H and the ON time of the MOS transistor  301 L. That is, during such a dead time, the MOS transistors  301 H and  301 L are both turned OFF. For example, a rising timing of the voltage at one of the output terminals HO and LO is delayed as compared with a falling timing of the voltage at the other of the output terminals HO and LO.  
         [0032]     In order to provide a dead time, a high-side dead time control circuit HDTC 1  and a low-side dead time control circuit LDTC 1  as illustrated in  FIG. 2  are included in the predriver  200  of  FIG. 1 .  
         [0033]     In  FIG. 2 , the high-side dead time control circuit HDTC 1  is constructed by a delay circuit formed by CMOS inverters H 1  and H 2  connected in series and an AND circuit H 3  having a first input connected via the delay circuit (H 1 , H 2 ) to the high-side input terminal H 1 , a second input connected directly to the high-side input terminal HI and an output connected to the high-side output terminal HO. Similarly, the low-side dead time control circuit LDTC 1  is constructed by a delay circuit formed by CMOS inverters L 1  and L 2  connected in series and an AND circuit L 3  having a first input connected via the delay circuit (L 1 , L 2 ) to the low-side input terminal LI, a second input connected directly to the low-side input terminal LI and an output connected to the low-side output terminal LO. That is, the high-side dead time control circuit HDTC 1  has the same structure as the low-side dead time control circuit LDTC 1 .  
         [0034]     The CMOS inverter H 1  (H 2 , L 1  or L 2 ) is constructed by a p-channel MOS transistor H 11  (H 21 , L 11  or L 21 ) and an n-channel MOS transistor H 12  (H 22 , L 12  or L 22 ) connected in series between the power supply terminal V DD  and the ground terminal GND.  
         [0035]     The operation of the dead time control circuits HDTC 1  and LDTC 1  is explained next with reference to  FIG. 3 . Here, assume that a delay time of each of the delay circuits is defined by “d”.  
         [0036]     That is, a rising edge and a falling edge of the voltages at the input terminals HI and LI are both delayed by the delay time “d” to obtain voltages HI′ and LI′ which are supplied to first inputs of the AND circuits H 3  and L 3 , respectively. On the other hand, the voltages at the input terminals HI and LI are supplied directly to the second inputs of the AND circuits H 3  and L 3 , respectively. As a result, the AND circuits H 3  and L 3  delay only the rising edges of the voltages at the input terminals HI and LI to generate voltages at the output terminals HO and LO as shown in  FIG. 3 . Thus, a dead time D corresponding to the delay time “d” is generated between the voltages at the output terminals HO and LO.  
         [0037]     In the dead time control circuits HDTC 1  and LDTC 1  of  FIG. 2 , however, even when the delay time of each of the CMOS inverters H 1 , H 2 , L 1  and L 2  fluctuate due to the environmental factors such as the temperature, the power supply voltage, etc. to change the dead time D, it is impossible to adjust the dead time D.  
         [0038]     In  FIG. 4 , which illustrates a high-side dead time control circuit HDTC 2  and a low-side dead time control circuit LDTC 2  each as a second prior art dead time control circuit, a delay circuit H 4  formed by an external resistor and an external capacitor is connected between the inverters H 1  and H 2  by external terminals HT 1  and HT 2 , and, a delay circuit L 4  formed by an external resistor and an external capacitor is connected between the inverters L 1  and L 2  by external terminals LT 1  and LT 2 . Thus, the dead time D can be easily adjusted by changing time constants using the external resistors and the external capacitors of the delay circuits H 4  and L 4 . Note that the resistors of the delay circuits H 4  and L 4  can be internal elements; in this case, the time constants are changed by only the external capacitors.  
         [0039]     In the dead time control circuits HDTC 2  and HDTC 2  of  FIG. 4 , however, since the delay circuits H 4  and L 4  formed by the external resistors and the external capacitors are provided, the dead time control circuits HDTC 2  and LDTC 2  are substantially increased in size and manufacturing cost. Also, since the characteristics of the external resistors and the external capacitors of the delay circuits H 4  and L 4  per se greatly fluctuate, it is impossible to accurately adjust the dead time D. Particularly, it is impossible to accurately adjust the dead time D in a high speed digital amplifier where accuracy of the dead time D is required on the nanosecond order.  
         [0040]     In  FIG. 5 , which illustrates a high-side dead time control circuit HDTC 3  and a low-side dead time control circuit LDTC 3  each as a third prior art dead time control circuit (see: JP-6-216750-A), since the low-side dead time control circuit LDTC 3  has all the same structure as the high-side dead time control circuit HDTC 3 , only the high-side dead time control circuit HDTC 3  is illustrated in detail. Note that the high-side dead time control circuit HDTC 3  is realized by combining the circuits of  FIGS. 2, 3 ,  5 ,  6  and  7  of JP-6-216750-A.  
         [0041]     In the high-side dead time control circuit HDTC 3  of  FIG. 5 , an external capacitor H 5  is connected via an external terminal HT 3  to the output of the CMOS inverter H 1  of  FIG. 2 , and an external capacitor H 6  is connected via an external terminal HT 4  to the output of the CMOS inverter H 2  of  FIG. 2 .  
         [0042]     Also, in the high-side dead time control circuit HDTC 3  of  FIG. 5 , a constant current source H 7  is connected between the power supply terminal V DD  and the source of the p-channel MOS transistor H 21  of the CMOS inverter H 2  of  FIG. 2 , and a constant current source H 8  is connected between the source of the n-channel MOS transistor H 22  of the CMOS inverter H 2  and the ground terminal GND of  FIG. 2 .  
         [0043]     In the constant current source H 7 , an analogous voltage generating circuit  71  formed by a p-channel MOS transistor  711  analogous to the p-channel MOS transistor H 11  of the CMOS inverter H 1  and a current source  712  is provided, so that a voltage V 71  between the p-channel MOS transistor  711  and the current source  712  is analogous to the output voltage V 1  of the CMOS inverter H 1 . The voltage V 71  is converted by a voltage-to-current converter  72  into a current I 72 . That is, the voltage V 71  is followed by a voltage V 72  at an external terminal HT 5  through an operational amplifier  721 , so that the current I 72  flows through an external resistor  722  and a p-channel MOS transistor  723 . The current I 72  is supplied as an input current to a current mirror circuit  73  which generates an output current I 73 . The output current I 73  is supplied as an input current to a current mirror circuit  74  which generates an output current I 74  which is supplied to the source of the p-channel MOS transistor H 21  of the CMOS inverter H 2 . In this case, if the transistors of the current mirror circuit  73  have the same size ratio W/L (W: gate width, L: gate length) as each other and the transistors of the current mirror circuit  74  have the same ratio W/L as each other, 
 
 I   72 = I   73 = I   74 . 
 
         [0044]     If the p-channel MOS transistor H 11  of the CMOS inverter H 1 , i.e., the p-channel MOS transistor  711 , has a rapid response speed, the current I 74  becomes small to decrease the response speed of the p-channel MOS transistor H 21  of the CMOS inverter H 2 . On the other hand, if the p-channel MOS transistor H 11  of the CMOS inverter H 1 , i.e., the p-channel MOS transistor  711 , has a slow response speed, the current I 74  becomes large to increase the response speed of the p-channel MOS transistor H 21  of the CMOS inverter H 2 . Thus, the response speed characteristic of the p-channel MOS transistor H 11  of the CMOS inverter H 1  is opposite to the response speed characteristic of the p-channel MOS transistor H 21  of the CMOS inverter H 2 .  
         [0045]     Similarly, in the constant current source H 8 , an analogous voltage generating circuit  81  formed by an n-channel MOS transistor  811  analogous to the n-channel MOS transistor H 12  of the CMOS inverter H 1  and a current source  812  is provided, so that a voltage V 81  between the n-channel MOS transistor  811  and the current source  812  is analogous to the output voltage V 1  of the CMOS inverter H 1 . The voltage V 81  is converted by a voltage-to-current converter  82  into a current I 82 . That is, the voltage V 82  is followed by a voltage V 82  at an external terminal HT 6  through an operational amplifier  821 , so that the current I 82  flows through an external resistor  822  and an n-channel MOS transistor  823 . The current I 82  is supplied as an input current to a current mirror circuit  83  which generates an output current I 83 . The output current I 83  is supplied as an input current to a current mirror circuit  84  which generates an output current I 84  which is supplied to the source of the n-channel MOS transistor H 22  of the CMOS inverter H 2 . In this case, if the transistors of the current mirror circuit  83  have the same size ratio W/L as each other and the transistors of the current mirror circuit  84  have the same ratio W/L as each other, 
 
 I   82 = I   83 = I   84 . 
 
         [0046]     If the n-channel MOS transistor H 12  of the CMOS inverter H 1 , i.e., the n-channel MOS transistor  811 , has a rapid response speed, the current I 84  becomes small to decrease the response speed of the n-channel MOS transistor H 22  of the CMOS inverter H 2 . On the other hand, if the n-channel MOS transistor H 12  of the CMOS inverter H 1 , i.e., the n-channel MOS transistor  811 , has a slow response speed, the current I 84  becomes large to increase the response speed of the n-channel MOS transistor H 22  of the CMOS inverter H 2 . Thus, the response speed characteristic of the n-channel MOS transistor H 12  of the CMOS inverter H 1  is opposite to the response speed characteristic of the n-channel MOS transistor H 22  of the CMOS inverter H 2 .  
         [0047]     Therefore, in  FIG. 5 , when the delay time CMOS inverter H 1  decreases due to environmental factors such as temperature, power supply voltage, etc., the delay time of the CMOS inverter H 2  increases. As a result, the delay time of the entire delay circuit formed by the CMOS inverters H 1  and H 2  becomes stable.  
         [0048]     In  FIG. 5 , note that the delay time of the entire delay circuit can be adjusted by the external capacitors H 5  and H 6  and the external resistors  74  and  84 .  
         [0049]     In the dead time control circuits HDTC 3  and LDTC 3  of  FIG. 5 , however, as shown in  FIG. 6 , the rising/falling characteristics of the voltages at the high-side output terminal HO and the low-side output terminal LO have a positive temperature coefficient, while the dead time D has a negative temperature coefficient. As a result, as indicated by a hatched portion in  FIG. 6 , when the temperature is high, the dead time D is small while the output voltages at the high-side output terminal HO and the low-side output terminal LO are both high, so that a large penetration current would flow through the MOS transistors  301 H and  301 L of  FIG. 1 . Also, since the external capacitors H 5  and H 6  are provided, the dead time control circuits HDTC 3  and LDTC 3  are substantially increased in size and manufacturing cost.  
         [0050]     In  FIG. 7 , which illustrates a high-side dead time control circuit HDTC 4  and a low-side dead time control circuit LDTC 4  each as a first embodiment of the present invention, only the high-side dead time control circuit HDTC 4  is illustrated in detail, since the low-side dead time control circuit LDTC 4  has all the same structure as the high-side dead time control circuit HDTC 4 .  
         [0051]     In  FIG. 7 , the external capacitor H 5  connected to the external terminal HT 3 , the external capacitor H 6  connected to the external terminal HT 4  and the constant current source H 7  of  FIG. 5  are deleted to decrease the size and manufacturing cost. Also, the constant current source H 8  of  FIG. 5  is modified to a constant current source H 8 ′ where the analogous voltage generating circuit  81  of  FIG. 5  is replaced by a reference voltage generating circuit  81 ′ for generating a reference voltage V ref .  
         [0052]     The reference voltage generating circuit  81 ′ is constructed by a current mirror circuit  811 ′ formed by p-channel MOS transistors Qp 1 , Qp 2  and Qp 3  connected to the power supply terminal V DD , a current mirror circuit  812 ′ formed by n-channel MOS transistors Qn 1 , Qn 2  connected to the current mirror circuit  811 ′, a resistor R 1  and diodes D 1  connected in series between the transistor Qn 1  and the ground terminal GND, a diode D 2  connected between the transistor Qn 2  and the ground terminal GND, and a resistor R 2  and a diode D 3  connected in series between the transistor Qp 3  and the ground terminal GND.  
         [0053]     If the p-channel MOS transistors Qp 1 , Qp 2  and Qp 3  of the current mirror circuit  811 ′ have the same size ratio W/L as each other and the n-channel MOS transistors Qp 1  and Qp 2  of current mirror circuit  812 ′ have the same size ratio W/L as each other, a reference current I ref  is represented by  
               I   ⁢           ⁢   811     =     I   ⁢           ⁢   812                 =     I   ⁢           ⁢   813                 =         (       VF   ⁢           ⁢   2     -     VF   ⁢           ⁢   1       )     /   r     ⁢           ⁢   1                 =     I   ref               
 
         [0054]     where r 1  is a resistance value of the resistor R 1 ;  
         [0055]     VF 1  is a forward voltage of the diodes D 1 ; and  
         [0056]     VF 2  is a forward voltage of the diodes D 2 . Thus, the currents I 811 , I 812  and I 813  can be determined by the resistance value r 1  of the resistor R 1 . On the other hand, the reference voltage V ref  is represented by 
 
 V   ref   =VF   3 − r   2 · I   ref  
 
         [0057]     where VF 3  is a forward voltage of the diode D 3 .  
         [0058]     Generally, the forward voltage VF 3  has a negative temperature coefficient while the resistance value r 2  of the resistor R 2  has a positive temperature coefficient. Therefore, the temperature coefficient of the reference voltage V ref  is dependent upon the resistance value r 2  of the resistor R 2  as shown in  FIG. 8A . That is, according to the present invention, the absolute value of the resistance value r 2  of the resistor R 2  is made small as compared with the forward voltage VF 3  of the diode D 3 , so that the reference voltage V ref  has a negative temperature coefficient subjected to the negative temperature coefficient of the forward voltage VF 3  of the diode D 3 .  
         [0059]     The reference voltage V ref  is converted by the voltage-to-current converting circuit  82  into a current I 82  depending upon a ratio of the reference voltage V ref  to the resistance value of the resistor  822 . Since I 82 =I 83 =I 84 , the current flowing through the CMOS inverter H 2  is controlled by the current I 84 , so that the current flowing through the CMOS inverter H 2  has a negative temperature coefficient. Therefore, as the temperature increases, the current flowing through the CMOS inverter H 2  decreases so as to increase the delay time. Simultaneously, as the temperature increases, the current flowing through the CMOS inverter H 1  decreases so as to increase the delay time. Therefore, as the temperature increases, both the delay times of the CMOS inverters H 1  and H 2  are increased so that the dead time D is increased as shown in  FIG. 8B  which shows that the dead time D has a positive temperature coefficient.  
         [0060]     Thus, the temperature characteristics of the reference voltage V ref  and the dead time D in dependence upon the resistance value r 2  of the resistor R 2  are shown in  FIG. 9 .  
         [0061]     In  FIG. 10 , which illustrates a first modification of the dead time control circuits of  FIG. 7 , the constant current source H 8 ′ of  FIG. 7  is connected to the source of the MOS transistor H 12  of  FIG. 7 . The operation of the dead time control circuits of  FIG. 10  is similar to that of the dead time control circuits of  FIG. 7 , so that the temperature characteristics of the reference voltage V ref  and the dead time D in dependence upon the resistance value r 2  of the resistor R 2  are shown in  FIGS. 8A, 8B  and  9 .  
         [0062]     In  FIG. 11 , which illustrates a second modification of the dead time control circuits of  FIG. 7 , the constant current source H 8 ′ of  FIG. 7  is replaced by a constant current source H 8 ″ where the current mirror circuit  84  of the constant current source H 8 ′ of  FIG. 7  is deleted and the output of the current mirror circuit  83  of  FIG. 7  is connected directly to the source of the MOS transistor H 21  of the CMOS inverter H 2  of  FIG. 7 . Also, the operation of the dead time control circuits of  FIG. 11  is similar to that of the dead time control circuits of  FIG. 7 , so that the temperature characteristics of the reference voltage V ref  and the dead time D in dependence upon the resistance value r 2  of the resistor R 2  are shown in  FIGS. 8A, 8B  and  9 . Thus, the constant current source H 8 ″ can be decreased in size and manufacturing cost as compared with the constant current source H 8 ′ of  FIG. 7 .  
         [0063]     In  FIG. 11 , note that the constant current source H 8 ″ can be connected to the source of the MOS transistor H 11  of the CMOS inverter Hi in the same way as the constant current source H 8 ′ in  FIG. 10 .  
         [0064]     In  FIG. 12 , which illustrates a high-side dead time control circuit HDTC 5  and a low-side dead time control circuit LDTC 5  each as a first embodiment of the present invention, only the high-side dead time control circuit HDTC 5  is illustrated in detail, since the low-side dead time control circuit LDTC 5  has all the same structure as the high-side dead time control circuit HDTC 5 .  
         [0065]     In  FIG. 12 , the external capacitor H 5  connected to the external terminal HT 3 , the external capacitor H 6  connected to the external terminal HT 4  and the constant current source H 7  of  FIG. 5  are deleted, and the constant current source H 7  of  FIG. 5  is modified to a constant current source H 7 ′ where the analogous voltage generating circuit  71  of  FIG. 5  is replaced by a reference voltage generating circuit  71 ′ for generating a reference voltage V ref ′.  
         [0066]     The reference voltage generating circuit  71 ′ is constructed by a current mirror circuit  711 ′ formed by n-channel MOS transistors Qn 1 ′, Qn 2 ′ and Qn 3 ′ connected to the ground terminal GND, a current mirror circuit  712 ′ formed by p-channel MOS transistors Qp 1 ′, Qp 2 ′ connected to the current mirror circuit  711 ′, a resistor R 1 ′ and diodes D 1 ′ connected in series between the transistor Qp 1 ′ and the-power supply terminal V DD , a diode D 2 ′ connected between the transistor Qp 2 ′ and the power supply terminal V DD , and a resistor R 2 ′ and a diode D 3 ′ connected in series between the transistor Qn 3 ′ and the power supply terminal V DD .  
         [0067]     If the n-channel MOS transistors Qn 1 ′, Qn 2 ′ and Qn 3 ′ of the current mirror circuit  711 ′ have the same size ratio W/L as each other and the p-channel MOS transistors Qp 1 ′ and Qp 2 ′ of current mirror circuit  712 ′ have the same size ratio W/L as each other, a reference current I ref ′ is represented by  
               I   ⁢           ⁢   711     =     I   ⁢           ⁢   712                 =     I   ⁢           ⁢   713                 =         (       VF   ⁢           ⁢     2   ′       -     VF   ⁢           ⁢     1   ′         )     /   r     ⁢           ⁢     1   ′                   =     I   ref   ′               
 
         [0068]     where r 1 ′ is a resistance value of the resistor R 1 ′;  
         [0069]     VF 1 ′ is a forward voltage of the diodes D 1 ′; and  
         [0070]     VF 2 ′ is a forward voltage of the diodes D 2 ′. Thus, the currents I 711 , I 712  and I 713  can be determined by the resistance value r 1 ′ of the resistor R 1 ′. On the other hand, the reference voltage V ref ′ is represented by 
 
 V   ref   ′=VF   3 ′− r   2 · I   ref ′
 
         [0071]     where VF 3 ′ is a forward voltage of the diode D 3 ′.  
         [0072]     Generally, the forward voltage VF 3 ′ has a negative temperature coefficient while the resistance value r 2 ′ of the resistor R 2 ′ has a positive temperature coefficient. Therefore, the temperature coefficient of the reference voltage V ref ′ is dependent upon the resistance value r 2 ′ of the resistor R 2 ′ in the same way as V ref  in  FIG. 8A . That is, according to the present invention, the absolute value of the resistance value r 2 ′ of the resistor R 2 ′ is made small as compared with the forward voltage VF 3 ′ of the diode D 3 ′, so that the reference voltage V ref ′ has a negative temperature coefficient subjected to the negative temperature coefficient of the forward voltage VF 3 ′ of the diode D 3 ′.  
         [0073]     The reference voltage V ref ′ is converted by the voltage-to-current converting circuit  72  into a current I 72  depending upon a ratio of the reference voltage V ref ′ to the resistance value of the resistor  722 . Since I 72 =I 73 =I 74 , the current flowing through the CMOS inverter H 2  is controlled by the current I 74 , so that the current flowing through the CMOS inverter H 2  has a negative temperature coefficient. Therefore, as the temperature increases, the current flowing through the CMOS inverter H 2  decreases so as to increase the delay time. Simultaneously, as the temperature increases, the current flowing through the CMOS inverter H 1  decreases so as to increase the delay time. Therefore, as the temperature increases, both the delay times of the CMOS inverters H 1  and H 2  are increased so that the dead time D′ is increased in the same way as the dead time D in  FIG. 8B  which shows that the dead time D′ has a positive temperature coefficient.  
         [0074]     Thus, the temperature characteristics of the reference voltage V ref ′ and the dead time D′ in dependence upon the resistance value r 2 ′ of the resistor R 2 ′ are shown in the same way as in  FIG. 9 .  
         [0075]     In the above-described second embodiment as illustrated in  FIG. 12 , modifications similar to the modifications as illustrated in  FIGS. 10 and 11  to the first embodiment as illustrated in  FIG. 7  can be applied. That is, the constant current source H 7 ′ can be connected to the source of the MOS transistor H 11  of the CMOS transistor H 1 . Also, the current mirror circuit  77  is deleted so that the output of the current mirror circuit  73  can be connected to the source of the MOS transistor H 22  of the CMOS inverter H 2  while the power supply terminal V DD  can be connected directly to the source of the MOS transistor H 21  of the CMOS inverter H 2 .  
         [0076]     If the push-pull type output buffer  300  of  FIG. 1  is of a CMOS type where the enhancement-type n-channel MOS transistor  301 H is replaced by an enhancement-type p-channel MOS transistor  301 H′ as illustrated in  FIGS. 13, 14 ,  15  and  16  which correspond to  FIGS. 7, 10 ,  11  and  12 , respectively, the high-side dead time control circuit HDTC 4  or HDTC 5  is replaced by a high-side dead time control circuit HDTC 4 ′ or HDTC 5 ′ while the low-side dead time control circuit LDTC 4  or LDTC 5  is unchanged under the condition that the voltage at the high-side input terminal HI is the same as that at the low-side input terminal LI. That is, in the high-side dead time control circuit HDTC 4 ′ or HDTC 5 ′ of  FIGS. 13, 14 ,  15  and  16 , the AND circuit H 3  is replaced by an OR circuit H 3 ′.  
         [0077]     Note that the present invention can also be applied to a dead time control circuit where the number of inverters as a delay circuit can be 4, 6, . . . .