Abstract:
Disclosed is switching power supply that includes a pulse frequency modulation (PFM) mode of operation current feedback control. A reference current source is configured to output a reference current at one of several selectable levels. The level of the reference current may vary during operation of the current feedback control loop.

Description:
BACKGROUND 
       [0001]    Unless otherwise indicated, the foregoing is not admitted to be prior art to the claims recited herein and should not be construed as such. 
         [0002]    Switching power supplies, such as buck converters, boos converters, etc., may operation in pulse width modulation (PWM) mode. The output voltage can be regulated by varying the duty cycle or pulse width of a pulsed control signal. Switching efficiency, however, drops off at lower loads. Due to an increasing range of functionality provided in mobile computing devices (e.g., communication devices, computer tablets, etc.), low load conditions are becoming more common. Accordingly, switching using PWM mode only becomes increasingly less efficient. 
         [0003]    Switching power supply designs may include a pulse frequency modulation (PFM) mode of operation, sometimes referred to as “power saving mode.” Switching power supplies may operate in PFM mode to support certain functionality in a power management circuit when it is in a low power mode. In PFM mode, the frequency of the control pulses varies with load current and switching cycles are initiated only as needed to maintain the output voltage. The ability of the switching power supply to provide current in PFM mode is typically based on a preset PFM current limit value to improve efficiency under low load conditions. Increasing the current limit allows PFM mode to provide more power under low loads, but at the expense of increasing ripple artifacts in the output voltage. 
       SUMMARY 
       [0004]    In some embodiments according to the present disclosure a switching regulator may include an output stage comprising switching FETs. The switching regulator may include circuitry configured to enable switching of the output stage in response to changes in an output voltage of the circuit relative to a reference voltage. 
         [0005]    The switching regulator may further include switching circuitry to generate a control signal to drive the output stage in response to an output current of the output stage relative to the a reference current. 
         [0006]    The switching regulator may further include a reference circuit configured to generate the reference current. The reference circuit may be configured to change a level of the reference current from a first level to a second level in response to changes in the output current of the output stage relative to the reference current. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    With respect to the discussion to follow and in particular to the drawings, it is stressed that the particulars shown represent examples for purposes of illustrative discussion, and are presented in the cause of providing a description of principles and conceptual aspects of the present disclosure. In this regard, no attempt is made to show implementation details beyond what is needed for a fundamental understanding of the present disclosure. The discussion to follow, in conjunction with the drawings, makes apparent to those of skill in the art how embodiments in accordance with the present disclosure may be practiced. In the accompanying drawings: 
           [0008]      FIGS. 1A and 1B  illustrate examples of switching regulators in accordance with the present disclosure. 
           [0009]      FIG. 2  illustrate a PFM controller in accordance with the present disclosure. 
           [0010]      FIGS. 2A and 2B  illustrate variations of the PFM controller shown in  FIG. 2 . 
           [0011]      FIGS. 3 and 4  illustrate waveforms and timing diagrams of operation of the circuit shown in  FIG. 2 . 
           [0012]      FIG. 5  illustrates an embodiment of a current source controller in accordance with the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0013]    In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be evident, however, to one skilled in the art that the present disclosure as expressed in the claims may include some or all of the features in these examples, alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein. 
         [0014]    A pulse frequency modulated (PFM) controller in accordance with the present disclosure may be incorporated in a switching regulator; e.g., a buck converter, boost converter, etc.  FIG. 1A , for example, shows a buck converter  10  in accordance with the present disclosure. The buck converter  10  may include a PFM controller  102 . In some embodiments, the PFM controller  102  may regulate the output voltage V out  based on V out  and a current I L  across inductor L, and driving the power switches M 1  and M 2  accordingly. In other embodiments, the switch current (e.g., across M 1  or M 2 ) may be used for control purposes instead of inductor current. In some embodiments, the power switches M 1 , M 2  may be power FETs, although M 1  and M 2  may be any suitable power switch technology. 
         [0015]    In some embodiments, a PFM controller in accordance with the present disclosure may operate in conjunction with a pulse width modulated (PWM) controller in a switching regulator.  FIG. 1B , for example, shows a buck converter  12  comprising PFM controller  102  and a PWM controller. Outputs of the PWM controller and PFM controller  102  may be selectively provided by a drive selector to the driver circuitry to drive power switches M 1 , M 2 . In some embodiments, for example, the switching regulator may operate in PWM mode during certain load conditions, and then switch to PFM mode under lighter load conditions. 
         [0016]      FIG. 2  illustrates circuitry comprising a PFM controller  202  in accordance with some embodiments of the present disclosure. Merely for illustrative purposes, a buck converter configuration will be used to explain the PFM controller  202 . Persons of ordinary skill, however, will understand that the PFM controller  202  can be incorporated in any suitable switching regulator architecture. 
         [0017]    Switches M 1 , M 2  may constitute an output stage of the buck converter  20 . In some embodiments, the switches M 1 , M 2  may comprise power FET devices; e.g., MOSFETs. The gates of M 1 , M 2  may be driven by driver circuitry. The driver circuitry may receive a signal that serves as a control signal to control the switching of M 1  and M 2 . 
         [0018]    The PFM controller  202  may monitor an output voltage V out  of the buck converter  20 . In some embodiments, for example, the PFM controller  202  may comprise a voltage comparator  212  having an input that receives V out . In the buck converter  20  shown in  FIG. 2 , for example, a resistor divider network comprising resistors R 1 , R 0  may be used to sense V out , and provide a voltage V s  that is representative of V out  to the voltage comparator  212 . The voltage comparator  212  may receive a reference voltage V ref  and generate an output that switches between a first state and a second state (e.g., a square wave) when V s  becomes greater than V ref  and less than V ref . 
         [0019]    The PFM controller  202  may sense an output current of the output stage. In some embodiments, the PFM controller  202  may comprise a current comparator  214  having an input connected to a switching node SW of the output stage to receive a signal that is indicative of the output current of the output stage. It will be appreciated, of course, that the output current may be sensed in other ways depending on the particular configuration of the switching regulator. In the configuration shown in  FIG. 2 , for example, output current of the output stage may be sensed from the current I L  across inductor L, for example using resistor R L . 
         [0020]    The PFM controller  202  may comprise a current reference  216  connected to the current comparator  214 . The sense FET provides a scaled copy of the current in the main FET (e.g., M 1 ). In a particular embodiment, for example, the sense FET provide a scaling factor of 1/20,000. The current comparator  214  may receive a reference current I ref  from the current reference  216  and generate an output that switches between a first state and a second state (e.g., a square wave) as the output current becomes greater than I ref  and less than I ref . 
         [0021]    The outputs of voltage comparator  212  and current comparator  214  may connect to an AND gate  218 . In an embodiment, for example, the output of voltage comparator  212  may connect to AND gate  218  via an inverter  220 . The output of current comparator  214  may connect to AND gate  218  via a monostable multivibrator (one-shot)  222  and inverter  224 . In some embodiments, the positive boolean logic may be used, where TRUE is represented by a HI signal and FALSE is represented by a LO signal. In other embodiments, negative logic may be used. For purposes of the present disclosure, positive logic will be assumed. 
         [0022]    The PFM controller  202  may comprise an S-R flip flop  226  that operates in accordance with the truth table shown in  FIG. 2 . The output of AND gate  218  may connect to the S input of the flip flop  226  and the output of the one-shot  222  may connect to the R input of the flip flop  226 . An output Q of the flip flop  226  may serve as a control signal to the driver circuitry for switching M 1  and M  2 . For example, Q HI may turn ON M 1  and turn OFF M 2 , and vice versa Q LO may turn OFF M 1  and turn ON M 2 . 
         [0023]    The PFM controller  202  may comprise a current source controller  228 , having an input connected to the output Q of the flip flop  226  to control operation of the current source controller  228 . The current source controller  228  may include a reset input connected to the output of voltage comparator  212  to reset the current source controller  228  to an initial state. This aspect of the present disclosure will be explained in more detail. 
         [0024]    In accordance with the present disclosure, the current source  216  may comprise several selectable current levels: Iref 1 &lt;Iref 2 &lt;Iref 3 &lt;. . . &lt;Iref n . The current source controller  228  may connect to a control input of the current source  216  to select a level of the reference current I ref  used by current comparator  214 . As will be explained below, the input to the current source controller  228  can trigger a level change in the current source  216 . In some embodiments,  FIG. 2  for example, the trigger may come from the Q output of flip flop  226 . In other embodiments, the trigger for a level change may come from the output of the one-shot  222  as illustrated in  FIG. 2A , for example. The trigger for a level change may be based on the current comparator  214  as illustrated in  FIG. 2B , and so on. This aspect of the present disclosure will be explained in more detail. 
         [0025]      FIG. 3  is a high level illustration of operation of the PFM controller  202  shown in  FIG. 2 . The PFM controller  202  may operate to maintain the output voltage V out  of buck converter  10  between V max  and V min . In some embodiments, V max  and V min  may be based on the hysteresis (V hys ) of voltage comparator  212 . For example, V min  and V max  may be computed as follows: V min =S×V ref  and V max =S×(V ref +V hys ), where s is a scaling factor based the voltage divider circuit formed by R 1 , R 0 . In other embodiments, V min  and V max  may be computed as follows: V min =S×(V ref −0.5V hys ) and V max =s×(V ref +0.5V hys ). It will be appreciated, more generally, that V min  and V max  may be obtained in any suitable manner; e.g., using a reference other than voltage comparator  212 , using separate references, and so on. 
         [0026]    Referring to the waveforms and timing diagrams in  FIG. 3 , when the output voltage V out  falls below V min  at time t A , the voltage comparator  212  transitions from HI to LO, which enables various circuitry to restore V out  by switching M 1  and M 2 . Switching of M 1  and M 2  begins at time t A , where M 1  is turned ON and M 2  is turned OFF. Current begins to flow from V in , across inductor L, to charge output capacitor C o . Accordingly, the inductor current I L  begins to increase. The reference current I ref  serves to limit the current that flows across the inductor L. Accordingly, when inductor current I L  exceeds the reference current I ref , M 1  may be switched OFF and M 2  switched ON so that I L  decays as output capacitor C o  discharges through the load R load . After some time has passed, M 1  is again switched ON and M 2  is switched OFF, and inductor current I L  begins to increase and charges output capacitor C o  until I L  again exceeds I ref . This repeats until the output voltage V out  rises above V max . 
         [0027]    In accordance with the present disclosure, the current source  216  may be initially configured (e.g., at time t A ) to output a reference current I ref  at a first current level (e.g., Iref 1 ). The inductor current I L  exceeding the reference current I ref  may serve as an event that triggers a change in the reference current I ref  from one level to another level.  FIG. 3 , for example, shows that a change in level of the reference current I ref  from Iref 1  to Iref 2  to Iref 3  to Iref 4  can be triggered in synchrony with the inductor current I L  exceeding the reference current I ref . 
         [0028]    By gradually increasing the current limit from Iref 1  to Iref 4 , the PFM controller  202  can reduce the amount of excess energy that is stored in the inductor each time that M 1  turns OFF, which can reduce the amount of ripple in the output voltage V out . This approach allows a switching regulator in accordance with the present disclosure (e.g., buck converter  10 ,  FIG. 1 ) to deliver high current to a load in incremental fashion and reduce output ripple artifacts in the output voltage V out . 
         [0029]    When the output voltage V out  reaches V max  at time t B , the voltage comparator  212  transitions from LO to HI. In response, M 1  will turn OFF and M 2  will turn ON, allowing the inductor current I L  to decay to zero. In some embodiments, M 1  may be turned OFF and M 2  may be turned ON at a time subsequent to the voltage comparator  212  transitioning from LO to HI. In other embodiments, M 1  may be turned OFF and M 2  may be turned ON substantially at the time that voltage comparator  212  transitions from LO to HI. In some embodiments, switch M 2  may additionally be turned OFF after the inductor becomes zero (e.g., at time t B1 ). The period of time from t A  to t C  may be referred to as a cycle  302  of operation. The cycle may repeat when the output voltage V out  again falls below V min ; e.g., at time t C . 
         [0030]    The waveforms and timing diagrams in  FIG. 4  illustrate in more detail a cycle of operation, discussed in connection with circuitry shown in  FIG. 2 . When the output voltage V out  falls below V min  at time t A , the voltage comparator  212  transitions from H to LO. The transition to LO enables switching of M 1  and M 2 , to restore V out  to a level higher than V min  and less than V max . Thus at time t A , the one-shot  222  is LO and so the inputs to flip flop  226 , accordingly, are S=HI, R=LO. The output Q transitions from LO to HI, which can serve as a control signal to the driver circuitry to turn M 1  from OFF to ON and maintain M 2  OFF. Current begins to flow across inductor L to charge output capacitor C o . 
         [0031]    The current source controller  228  may set the reference current I ref  from current source  216  to an initial level (e.g., Iref 1 ). In some embodiments, for example, the transition of voltage comparator  212  from HI to LO may serve as a trigger for the current source controller  228  to reset the reference current I ref  to an initial level. 
         [0032]    During the period of time from t A  to t 1 , inductor current I L  increases until I L  exceeds Iref 1  at time t 1 . This event at time t 1  causes current comparator  214  to trigger, which in turn triggers the one-shot  222  to transition from LO to HI. The transition of the one-shot  222  from LO to HI resets the flip flop  226  (S=LO, R=HI), which sets Q to LO. In response to Q being LO, the driver circuitry turns OFF M 1  and turns ON M 2 . This state of the output stage allows the inductor current I L  to decay beginning from time t 1 . 
         [0033]    The one-shot  222  has a delay of Δt, and resets to LO after a period of time Δt has passed. Accordingly, at time t 2  (t 1 +Δt), the one-shot  222  resets to LO, which sets the flip flop  226  (S=HI, R=LO) and sets Q to HI. In response to Q being HI, the driver circuitry turns ON M 1  and turns OFF M 2 , thus allowing current to once again flow across inductor L at time t 2 . As known by those of ordinary skill, the delay Δt may be defined by a capacitor for the one-shot  222 . In some embodiments, the capacitor may have a fixed capacitance. In other embodiments, the capacitance may be selectable, allowing for Δt to be varied. 
         [0034]    In accordance with the present disclosure, the current source controller  228  may change the reference current I ref  from a first level (e.g., Iref 1 ) to a second level (e.g., Iref 2 ). In some embodiments, the current source controller  228  may change the level of reference current I ref  in response to transitions of the output Q of flip flop  226 . Referring to  FIG. 4 , for example, the level of reference current I ref  may change at some time after Q goes LO at time t 1 , but before time t 2 . Accordingly, when M 1  turns ON at time t 2 , the inductor current I L  will be compared to reference current I ref  at a new level (e.g., Iref 2 ). 
         [0035]    In other embodiments, the current source controller  228  may change the level of the reference current I ref  in response to triggers other than transitions of the output Q of flip flop  226 . For example, in  FIG. 2A , the current source controller  228  may use the output of the one-shot  222  as the trigger. In  FIG. 2B , the current controller  228  may use the output of the current comparator  214  as the trigger. In  FIG. 2B , a delay may be provided to delay the output of the current comparator  214  to the current source controller  228  so that the current comparator  214  uses the correct level of the reference current I ref . In some embodiments, for example, the delay should be sufficient to allow enough time for the one-shot  222  to trigger. 
         [0036]    Continuing with  FIG. 4  at time t 2 , the inductor current I L  increases until the level of I L  reaches Iref 2  at time t 3 . The current comparator  214  triggers at time t 3  and in response, M 1  turns OFF and M 2  turns ON in the manner explained above. The current source controller  228  may control the current source  216  to produce reference current I ref  at the next level (e.g., Iref 3 ) for the next round, at time t 4 , when M 1  is turned ON, and so on. 
         [0037]    The switching of M 1  and M 2  continues in this manner, incrementally charging output capacitor C o  until the voltage comparator  212  transitions from LO to HI at time t B  when the output voltage V out  reaches V max . At time t B , the S input of flip flop  226  goes LO in response to voltage comparator  212  transitioning from LO to HI. Since the R input to flip flop  226  is already LO (because the output of the one-shot  222  is LO), the output Q of flip flop  226  remains HI so M 1  remains ON and M 2  remains OFF. At time t 11 , when the inductor current I L  exceeds Iref 4 , the current comparator  214  triggers and the one-shot  222  goes HI, which resets flip flop  226  and Q goes LO. In response, M 1  turns OFF and M 2  turns ON. From time t 11 , the inductor current I L  is allowed to decay until I L  reaches zero at time t B1 . In some embodiments, M 2  may be turned OFF at time t B1 . The cycle may repeat in response to the voltage comparator  212  transitioning from HI to LO when the output voltage V out  falls below V min . 
         [0038]    As described above, in some embodiments of the present disclosure, the current source  216  may output a reference current I ref  at any one of a number of selectable levels during regulation of the output voltage V out .  FIG. 4 , for example, shows that the levels of reference current I ref  in a cycle may vary in stepwise fashion, from Iref 1  (initial level) to Iref 2  to Iref 3  to Iref 4 , and maxes out at Iref 4 . The level may reset to Iref 1  in a subsequent cycle. In other embodiments, the current source  216  may be configured to provide a different number of selectable levels of the reference current I ref . In some embodiments, a level change may occur with each triggering event (e.g., transition of Q from HI to LO) or after two or more triggering events. In other embodiments, the levels may continually increase to a maximum level, or may vary up and down from one level change to another. In other embodiments, the levels may vary in an arbitrary order, and so on. 
         [0039]    In some embodiments, the current source controller  228  may use a lookup table to store a predetermined sequence of level changes.  FIG. 5 , for example, shows an example of a current source controller  228  in accordance with the present disclosure. The current source controller  228  may comprise a counter  502 , a lookup table  504 , and control logic  506 . The control logic  506  may include a reset input to reset the state of the current source controller  228 . For example, in some embodiments, the reset input may connect to the output of voltage comparator  212 . The control logic  506  may include a trigger input to change the state of the current source controller  228  to a next state. In some embodiments, for example, the trigger input may be connected to the Q output of flip flop  226 . 
         [0040]    The lookup table  504  may store values V 1 -V n , and output a selected value from the lookup table  504  indexed by the counter  502 . A signal corresponding to the selected output value may be presented on output line  512 . The current source  216  may be configured to output the reference current I ref  at a level corresponding to the selected output value of the lookup table  504 . 
         [0041]    The control logic  506  may respond to a HI to LO transition on the reset input to set the state of the current source controller  228  to an initial state. For example, the control logic  506  may initialize the counter  502  to output ‘0’ so that the lookup table outputs a value V 1 . The control logic  506  may respond to a LO to H I transition on the trigger input. In response, the control logic  506  may increment the counter  502 , or decrement the counter  502 , or do nothing. In some embodiments, for example, the control logic  506  may increment the counter  502  in response to each trigger. In other embodiments, the control logic  506  may increment or decrement the counter  502  depending on its current output. In other embodiments, the control logic  506  may increment or decrement the counter  502  depending on its previous action, and so on. 
         [0042]    In some embodiments, the current source controller  228  may include an input  514  to receive data to be loaded into the lookup table  504 . The data may specify a set of current levels, allowing the reference current I ref  to be programmable with different current levels at different times. 
         [0043]    In some embodiments, the lookup table  504  may be a decoder that can decode the input from counter  502  to produce a value that the current source  216  can use to generate the reference current I ref . 
       Advantages and Technical Effect 
       [0044]    Output ripple in the voltage output of a switching regulator (e.g., buck converter  10 ,  FIG. 1 ) is largely determined by the excess energy stored in the inductor when the output voltage reaches the level being regulated and that excess energy is discharged. In accordance with the present disclosure, since the current limit in the regulator is initially lower, then at light loads, where the first few turn-on cycles could bring the output voltage to be higher than the regulated level, there is less energy stored in the inductor and thus less ripple effect. Maximum current can still be delivered, since the current limit incrementally increases to its maximum value. 
         [0045]    The above description illustrates various embodiments of the present disclosure along with examples of how aspects of the particular embodiments may be implemented. The above examples should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the particular embodiments as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents may be employed without departing from the scope of the present disclosure as defined by the claims.