Abstract:
A solid state disk (SSD) power supply system includes power supply switching circuit. The power supply switching circuit comprises a first power input to receive a first direct current (DC) voltage signal, a second power input connected to a super capacitor to receive a second DC voltage signal provided by the super capacitor, a switching chip connected to the first and second power inputs and configured to select the second DC voltage signals to output in a situation that the first power input is disabled to receive the first DC voltage signal, a voltage converting chip to receive the voltage signal output from the switching chip, and a voltage output to output an operation voltage to an SSD according to the voltage signal. The switching chip and the voltage converting chip respectively output a first and second test signals for testing a discharging time of the super capacitor.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure generally relates to solid state disk (SSD) power supply systems, and particularly to a SSD power supply system capable of detecting a discharging time of a super capacitor of the SSD power supply system. 
         [0003]    2. Description of Related Art 
         [0004]    Super capacitors, as a power down protection element, are employed in SSD power supply systems. When a main power supply to the SSD is turned off accidentally, the super capacitor will maintain a supply of power so that the SSDs have time to store data. However, if a super capacitor has undetected inherent defects, the reliability of the SSD is effectively non-existent. 
         [0005]    What is needed, therefore, is an SSD power supply system which can overcome the described limitations. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views, and all the views are schematic. 
           [0007]      FIG. 1  is a schematic block diagram of an SSD power supply system according to an exemplary embodiment, the SSD power supply system including a power supply switching circuit. 
           [0008]      FIG. 2  is a schematic block diagram of the power supply switching circuit of 
           [0009]      FIG. 1  connected to a detection device. 
           [0010]      FIG. 3  is a schematic circuit diagram of the detection device of  FIG. 2 . 
       
    
    
     DETAILED DESCRIPTION 
       [0011]    Reference will be made to the drawings to describe the embodiments in detail. 
         [0012]      FIG. 1  is a schematic block diagram of an SSD power supply system  1  according to an exemplary embodiment, the SSD power supply system  1  including a power supply switching circuit  10 . In one embodiment, the SSD power supply system  1  further includes a super capacitor  11  (not shown). The super capacitor  11  may be an electric double-layer capacitor. 
         [0013]    The switching circuit  10  includes a first power input  112 , a second power input  114 , a first capacitor C 1 , a second capacitor C 2 , a switching chip  110 , a voltage converting chip  130 , and a voltage output  132 . The power input  112  is connected to a direct current (DC) power supply (not labeled), and is grounded via the capacitor C 1 . The power input  114  is connected to the super capacitor  11 , and is grounded via the capacitor C 2 . The switching chip  110  includes a first voltage input pin “INA”, a second voltage input pin “INB”, a first voltage output pin “OUTA”, and a second voltage output pin “OUTB”. The voltage input pin “INA” is connected to the power input  112 , the voltage input pin “INB” is connected to the power input  114 , and the voltage output pins “OUTA” and “OUTB” are connected to the voltage converting chip  130 . The voltage converting chip  130  provides power to an SSD (not shown, e.g., an SSD of an electronic device) via the voltage output  132 . 
         [0014]    The switching chip  110  further includes a first test pin “PFAIL”, and the voltage converting chip  130  includes a second test pin “PGOOD”. When an external power supply provides normal power to the SSD via the DC power supply, the switching chip  110  enables the voltage input pin “INA”, but disables the voltage input pin “INB”. Therefore, when the power input  112  receives a first DC voltage signal from the external power supply, the capacitor C 1  filters the first DC voltage signal to a stable first DC voltage signal, and the stable first DC voltage signal is provided to the voltage input pin “INA”. The switching chip  110  outputs the first DC voltage signal to the voltage converting chip  130  via the voltage output pin “OUTA”, and the voltage converting chip  130  generates an operation voltage according to the first DC voltage signal and provides the operation voltage to power the SSD via the voltage output  132 . At the same time, the external power supply charges the super capacitor  11 . In addition, when the power input  112  receives the first DC voltage signal, the switching chip  110  outputs a first test signal in a high level state (e.g., a logic “1”) via the test pin “PFAIL” representing that the SSD is powered normally, and the voltage converting chip  130  outputs a second test signal in the high level state via the test pin “PGOOD” representing that the voltage converting chip  130  is in a normal operation state. 
         [0015]    When the external power supply stops providing power to the SSD, no DC voltage is provided to the power input  112 , that is, the voltage input pin “INA” is idle, and the switching chip  110  enables the voltage input pin “INB”. At the same time, the super capacitor  11  provides a second DC voltage signal to the voltage input pin “INB” via the power input  114 , the switching chip  110  outputs the second DC voltage signal to the voltage converting chip  130  via the voltage output pin “OUTB”, and the voltage converting chip  130  generates the operation voltage according to the second DC voltage signal and provides the operation voltage to power the SSD via the voltage output  132 . When the switching chip  110  enables the voltage input pin “INB” and disables the voltage input pin “INA”, the first test signal output from the test pin “PFAIL” changes to a low level state (e.g., a logic “0”) from the high level state, and the second test signal output from the test pin “PGOOD” of the voltage converting chip  130  maintains a high level. 
         [0016]    When a voltage value of the second DC voltage signal output from the super capacitor  11  decreases to a preset voltage value, the second test signal output from the test pin “PGOOD” also changes to a low level state. The preset voltage value is less than the operation voltage value of the voltage converting chip  130 . 
         [0017]      FIG. 2  is schematic block diagram of the power supply switching circuit  10  connected to a detection device  20 . The detection device  20  includes a time counting circuit  210  and a display unit  230  connected to the time counting circuit  210 . The test pins “PFAIL” and “PGOOD” are connected to the time counting circuit  210 . 
         [0018]    When the external power supply stops providing power to the SSD, the voltage input pin “INB” is enabled, and the super capacitor  11  discharges. At the same time, the first test signal output from the test pin “PFAIL” changes to the low level state from the high level state. The first test signal which is in the low level state enables the time counting circuit  210  to start counting, and the time being counted is simultaneously displayed on the display unit  230 . 
         [0019]    When the voltage value of the second DC voltage signal output from the super capacitor  11  decreases to the preset voltage value, the second test signal output from the test pin “PGOOD” changes to the low level state from the high level state. When receiving the second test signal which is in the low level state, the time counting circuit  210  stops counting. 
         [0020]      FIG. 3  is a schematic circuit diagram of the detection device  20 . In this embodiment, the time counting circuit  210  includes a micro control unit (MCU)  212 , capacitors C 3 , C 4 , C 5  and C 6 , a resistor R 1 , and a crystal oscillator X. The display unit  230  includes a display  232 . The display  232  may be a liquid crystal display, and has 6-bit display function to display the hour, minute, and second. The time counting circuit  210  is connected in series to the display  232 . 
         [0021]    The MCU  212  includes a first power pin “VCC”, a first ground pin “GND”, a reset pin “MCLR”, two control signal input pins “RA 0 ” and “RA 1 ”, two crystal oscillator pins “OCS 1 ” and “OCS 2 ”, and seven pins “RA 2 ” “RA 3 ” “RC 0 ”, “RC 1 ”, “RC 2 ”, “RC 3 ” and “RC 4 ”. The first power pin “VCC” is connected to a power source VCC, and is grounded via the capacitor C 3 . The power source VCC is connected to the reset pin “MCLR” via a delay circuit consisting of the resistor R 1  and the capacitor C 4 . The delay circuit can provide a reliable reset time to the MCU  212 . The first ground pin “GND” is grounded. The control signal input pins “RAO” and “RA 1 ” are respectively connected to the test pins “PFAIL” and “PGOOD”. The crystal oscillator X is connected between the two crystal oscillator pins “OCS 1 ” and “OCS 2 ”, and two terminals of the crystal oscillator X are grounded respectively via the capacitors C 5  and C 6 . 
         [0022]    The display  232  includes a second power pin “VCC”, a second ground pin “GND”, and seven pins “SDA”, “A 2 ”, “Al”, “A 0 ”, “RST”, “CS” and “SCK”. The second power pin “VCC” is connected to the power source VCC, and the second ground pin “GND” is grounded. The seven pins “SDA”, “A 2 ”, “A 1 ”, “A 0 ”, “RST”, “CS” and “SCK” of the display  232  are respectively connected to the seven pins “RA 2 ” “RA 3 ” “RC 0 ”, “RC 1 ”, “RC 2 ”, “RC 3 ” and “RC 4 ” of the MCU  212 . 
         [0023]    When the system  1  is powered off, the first test signal output from the test pin “PFAIL” changes to the low level state from the high level state. The first test signal which is in the low level state enables the time counting circuit  210  to start counting, and the time being counted is simultaneously displayed on the display  232 . 
         [0024]    When the voltage value of the second DC voltage signal output from the super capacitor  11  decreases to the preset voltage value, the second test signal output from the test pin “PGOOD” changes to the low level state from the high level state. When receiving the second test signal which is in the low level state, the time counting circuit  210  stops counting, and the time displayed on the display  232  is a discharging time of the super capacitor  11 . That is, the discharging time of the super capacitor  11  is shown to be from a first time when the first test signal changes to the low level state from the high level state, to a second time when the second test signal changes to the low level state from the high level state. 
         [0025]    Therefore, the power supply switching circuit  10  provides test signals to the detection device  20 , and the detection device  20  detects the discharging time of the super capacitor  11  according to a level change of the test signals. Thus, the SSD power supply system  1  employing the power supply switching circuit  10  and detection device  20  can detect the discharging time of the super capacitor  11  and determine whether the super capacitor  11  used for the SSD can be relied upon. 
         [0026]    In an alternative embodiment, the first test signal output from the switching chip  110  can be in the low level state, and when the external power supply stops providing power to the SSD, the first test signal changes to the high level state from the low level state. The first test signal which is in the high level state enables the time counting circuit  210  to start counting. The second test signal output from the voltage converting chip  130  can be in the low level state, and when the voltage value of the second DC voltage signal output from the super capacitor  11  decreases to the preset voltage value, the second test signal changes to the high level state from the low level state. The second test signal which is in the high level state makes the time counting circuit  210  stop counting. 
         [0027]    In other embodiments, the first and second signals can trigger the counting circuit  210  to start counting or make the time counting circuit  210  stop counting by changing other parameters but are not limited to level, such as frequency. 
         [0028]    It is believed that the present embodiments and their advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the spirit and scope of the embodiments or sacrificing all of their material advantages.