Abstract:
The present invention provides logic to write data to a multi-ported memory array. The memory array is comprised of a plurality of memory banks and a common write word line shared by the memory banks. The memory array includes a plurality of write buffers, wherein each write buffer is associated with one of the memory banks. The memory array further comprises a selector module for selecting a write buffer to write data into its associated memory bank. The memory array further includes a writing module within the write buffer for writing data into the selected memory bank by way of a signal to the memory bank.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates generally to writing data to a banked memory array and more particular to a technique for banking multi-ported register file structures with a common write line.  
         BACKGROUND OF THE INVENTION  
         [0002]    Multi-ported register file memory arrays are typically large structures because each port requires its own set of word and bit lines. Moreover, each set of word lines requires its own decoder and driver, while each set of bit lines requires its own driver and/or sense amplifier. As the number of ports increase, these requirements become more burdensome.  
           [0003]    This problem is further exaggerated when it is necessary to bank the register file memory array. Reading from the banked memory array does not pose a significant problem. A common read word line may connect to the banks of the memory array, and a column multiplexer on the bit lines. This configuration allows the common read word line to be asserted without causing a conflict. Writing to the banked memory array, however, poses more of a problem. A shared memory word line poses a problem in that data will be written into multiple banks, which cannot be allowed. This condition cannot be resolved with a column multiplexer either. One solution is to add a second set of write word lines to the array, such that there is a set in each bank. The area penalty associated with separate word lines for each bank is very severe because it increases the number of write lines and/or decoder and drivers in the array.  
         SUMMARY OF THE INVENTION  
         [0004]    The present invention addresses the above-described limitation by providing a technique for writing in a banked, multi-ported register file memory array using common write word lines. This technique provides a more efficient way of writing data into a banked, multi-ported memory without increasing penalty due to area in the memory array.  
           [0005]    According to another aspect of the present invention, a memory array is provided. The memory array comprises of a common write word line shared by a first memory bank and a second memory bank. The memory array also includes a first write buffer for buffering data to be written to the first memory bank. The memory array includes a second write buffer for buffering data to be written to the second memory bank. The memory array further comprises logic for receiving outputs from both of the first write buffer and second write buffer by writing data only into one of the first or second memory banks.  
           [0006]    According to another aspect of the present invention, a memory array is provided. The memory array is comprised of a plurality of memory banks and a common write word line shared by the memory banks. The memory array includes a plurality of write buffers, wherein each write buffer is associated with one of the memory banks. The memory array further comprises a selector module for selecting a write buffer to write data into its associated memory bank. The memory array further includes a writing module within the write buffer for writing data into the selected memory bank by way of a signal to the memory bank.  
           [0007]    According to another aspect of the present invention, in a banked memory array having a common write word line shared by the banks of the memory array and write buffers for each of the memory banks, a method for writing data into the banked memory array is provided. The method comprises the step of initializing the memory array to write data into one of a plurality of memory banks by activating the write word line. The method also comprises the step of selecting a write buffer to write data into a memory bank. The method further comprises the step of a writing module within the write buffer for writing data into the selected memory bank by way of a signal to the memory bank.  
           [0008]    According to another aspect of the present invention, a memory array is provided. The memory array comprises common write word lines. The memory includes a plurality of memory banks for storing data. The memory array also includes a plurality of write buffers, wherein each of the write buffers are associated with one of the memory banks. The memory array also comprises selector logic for selecting memory banks to write data by way of a set of signals to the memory bank. The memory array further comprises distinguisher logic within the write buffers for sending a different set of signals to one of the memory banks that are not selected by the selector logic to retain data.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    The aforementioned features and advantages, and other features and aspects of the present invention, will become understood with regard to the following description and accompanying drawings wherein:  
         [0010]    [0010]FIG. 1 illustrates a memory array for practicing an illustrative embodiment of the present invention;  
         [0011]    [0011]FIG. 2 illustrates write buffers  18  of FIG. 1 in more detail; and  
         [0012]    [0012]FIG. 3 illustrates a memory cell in more detail. 
     
    
     DETAILED DESCRIPTION  
       [0013]    The illustrative embodiment of the present invention employs a multi-port register file for banking multi-ported register file structures with common write word lines.  
         [0014]    [0014]FIG. 1 illustrates a memory array  12  that has two memory banks  14  and  16 . Each memory bank  14  or  16  includes a plurality of memory cells, organized into rows and columns, that store data bit values. The memory banks  14  and  16  share a common set of write word lines. More specifically, all of the memory cells in a particular row of bank  14  and  16  are driven by the common set of write word lines, one set for each write port that exists in the memory array. One of these write word lines is write word line  50  as illustrated in FIG. 1. The write word line  50  is used to enable data to be written into a particular row of memory cells in either bank  14  or  16 . Furthermore, each column of the memory array  12  is connected to a set of complementary write data bit lines  28 ,  30 ,  32 , and  34 , one set for each write port that exists in the memory array  12 .  
         [0015]    The illustrative embodiment uses two sets of write buffers  18  and  20 , one for bank  14  and the other for bank  16 . The write data buffers  18  and  20  drives each drive the complementary write data bit lines  28 ,  30 ,  32 , and  34  that are connected to each memory cell in a particular column of the memory array  12 . The write buffers  18  and  20  receive a common write data bit  24  as input, and drive complementary write data bit lines  28 ,  30 ,  32 , and  34  that are connected to the memory array  12 . The write data buffers  18  and  20  also receive write enable signals  25  and  27  respectively as input. The write enable signals  25  and  27  are used to cause data to be written into a particular bank of data in the memory array  12 . For example, if the write enable signal  25  and the write word line  50  are both asserted, write data buffer  18  is enabled, which will cause complementary data to be driven into write data bit lines  28  and  30 . The data on the complementary write bit lines  28  and  30  will then be written into the memory cell of column zero of bank  14  that is connected to write word line  50 .  
         [0016]    On the other hand, if write enable signal  27  is simultaneously deasserted, write data buffer  20  is disabled, which will cause both write data bit lines  32  and  34  to be driven high. Subsequently, the memory cell in column zero of bank  16  that is connected to write word line  50  will not be overwritten with new data because the memory cell is designed to retain data under the condition that both write data bit lines  32  and  34  are driven high. Therefore, this memory cell retains the data that already existed in the cell. If the write data buffer  20  was not disabled in this manner, the same data bit value would be overwritten into both banks  14  and  16 .  
         [0017]    Reading data values from this banked memory array  12  requires the use of a set of common word lines, one set for each read port that exists in the memory array. One of the read word lines  48  is illustrated in FIG. 1. Furthermore, each column in the memory array  12  is connected to set a set of read data bit lines  36 ,  38 ,  40 , and  42 , one set for each read port that exists in the memory array  12 .  
         [0018]    When read word line  48  is asserted, each of the memory cells in that row of the memory array  12  drives its corresponding complementary read data bits lines  36 ,  38 ,  40 , and  42  according to the data currently stored in the memory cell. In the illustrative embodiment, read data bit lines  36 ,  38 ,  40 , and  42  are driven by a memory cell in column zero of bank  14  and  16  respectively. The read column multiplexer  44  receives the data from the read data bit lines  36 ,  38 ,  40 , and  42  and allows only one complementary data value to pass to its output  8  and  10  according to the bank select input  45 . When the bank select input  45  is asserted high, the data from bank  14  is selected, otherwise bank  16  is selected. The sense amplifier  46  receives the output of the read column multiplexer and produces the appropriate data output value  47 .  
         [0019]    The use of common write word lines that connect both banks  14  ad  16  in the illustrative embodiment provides a more efficient way to write data into a banked memory array. The area penalty associated with the illustrative embodiment is minimal.  
         [0020]    [0020]FIG. 2 illustrates one of the write buffers  18  in more detail. For illustrative purposes, the write buffer  18  is shown. However, the write buffer  20  includes similar components and functionality as the write buffer  18 . The write data buffers  18  and  20  provide the necessary logic needed to drive the differential data into the banked memory array  12 . The write data buffer  18  receives a single data bit value as input and stores the data appropriately in a clocked latch  52  with complementary outputs. The latch  52  may be any variety of latches, including level-sensitive, edge-triggered, etc., relative to the clock that controls its timing. The latch  52  outputs are provided as input to NOR gates  58  and  60  respectively. NOR gates  58  and  60  also receive as input the output of inverter  56 , which is driven by the write enable signal  25 . The outputs of the NOR gates  58  and  60  are sent to inverters  62  and  64  respectively. Note that the output of inverter  62  is the information in the high write data bit line  28 , and the output of the inverter  64  is the information in the low write data bit line  30 .  
         [0021]    For example, if the input data bit  24  is high, the complementary latch outputs a 1 and 0 for the Q and {overscore (Q)} outputs respectively to the NOR gates  58  and  60 . If the write enable signal  25  is high, the output of inverter  56  is low, and output of inverters  62  and  64  is 1 and 0 respectively, which corresponds to a data value of ‘1’ being written into the memory array  12 .  
         [0022]    However, if write enable signal is low, the output of inverter  56  is high, which forces the outputs of NOR gates  58  and  60  to 0 regardless of the output of the latch  52 . Subsequently, the outputs of inverters  62  and  64  are both 1, which prevents data from being written into memory array  12 .  
         [0023]    [0023]FIG. 3 illustrates a detailed depiction of a memory cell. The differential data is divided among write data high bit line  90  and write data low bit line  92 . For example, differential data “1 1” signifies write data high bit line  90  has a bit value of 1 and the write data low bit line  92  has a value of 1. FIG. 3 illustrates the technique used by the illustrative embodiment to write and read data into a memory cell  98  of bank  14 . It should be appreciated that the present invention may include more than one memory cell and include different differential high and low word lines as well as multiple read and write ports. The write high bit line  90  is connected to the source of MOS transistor  74 , and the write data low bit line  92  is connected to the source of the MOS transistor  76 . The drain of MOS transistor  76  is connected to the right of side  102  of the storage node  100 . The drain of MOS transistor  74  is connected to the left side  98  of the storage node  100 . The gates of MOS transistors  74  and  76  are connected to the write word line  50 . The gate of the grounding MOS transistor  84  is connected to the left side  102  of the storage node  100 . The source of MOS transistor  84  is connected to ground. The drain of MOS transistor  84  is connected to the source of the MOS transistor  86 . The drain of MOS transistor  86  is connected to the read low bit line  94 , and the gate of MOS transistor  86  is connected to the read word line  48 . The gate of the grounding MOS transistor  88  is connected to the right side  98  of the storage node  100 . The source of the grounding MOS transistor  88  is connected to ground and the drain of the MOS transistor  88  is connected to the source of MOS transistor  82 . The gate of MOS transistor  82  is connected to the read word line  48 , and the drain of MOS transistor  82  is connected to the read high bit line  96 .  
         [0024]    If a write operation is requested for memory cell  98 , then the write word line  50  is set high. The write MOS transistors  74  and  76  are activated. The differential data bits in the write data high bit line  90  and write data low bit line  92  are “1 0” respectively. As stated in the discussion of FIG. 2, a 1 0 differential data pair designates that a high value is being written. The drain of MOS transistor  74  is set high, and, thus, the left side  102  of the storage node  100  is set high. The drain of MOS transistor  76  is set low and also the right side  98  of the storage node  100  is set low. Thus, the storage node  100  stores a high value.  
         [0025]    When the differential data pair has a 0 1, a low value is written into storage node  100 . MOS transistors  74  and  76  are activated. The differential data bit pair in the write data high bit line  90  and write data low bit line  92  are 0 1 respectively. As stated in the discussion of FIG. 2, a 0 1 differential data pair designates that a low value is being written. The drain of MOS transistor  74  is set low and thus the left side  102  of the storage node  100  is set low. The drain of MOS transistor  76  is set high and also the right side  98  of the storage node  100  is set high. Thus, the storage node  100  is storing a low value.  
         [0026]    When the differential data pair has a 1 1, the data values in memory  98  are retained. The write MOS transistors  74  and  76  are activated. The differential data bit pair in the write data high bit line  90  and write data low bit line  92  are  111  respectively. As stated in the discussion of FIG. 2, a 1 1 differential data pair designates that no data value is being written. This is accomplished by ratioing the sizes of the transistors in the memory cell for stability when the write data bit lines  90  and  92  are both similar. Essentially, memory cell  98  is sized to be written only under specific circumstances.  
         [0027]    The read bit lines  94  and  96  are pre-charged to a logical high value and the read word line  96  is driven to a logical high value. MOS transistors  74  and  76  are not activated. MOS transistors  82  and  86  are activated. If the storage node  100  is storing a high value, then the right side  98  of the storage node  100  is low and the left side  102  of the storage node  100  is high. The gate of grounding MOS transistor  86  is high to activate MOS transistor  86  and, hence, a low value is present on the read data low bit line  94 . The gate of grounding MOS transistor  88  is not activated. As a result, a high value is present at the source of the read MOS transistor  82 . Consequently, a high value is present at the read data high bit line  96 . The read data high and low bit lines  96  and  94  constitute a 1 and 0 if a high value is read from the storage node  100 . As stated above writing a high value requires a 1 0 differential data values, reading differential data of 1 0 from the memory cell  98  constitutes reading a high value.  
         [0028]    If the storage node  100  stores a low value, then the left side  102  of the storage node  100  is low and the right side  98  of the storage node  100  is high. The gate of grounding MOS transistor  84  is low. This deactivates MOS transistor  84  and creates a high voltage point at the source of the read MOS transistor  86 , resulting in a high value at the read data low bit line  94 . The gate of the grounding MOS transistor  88  is activated. This creates a low voltage point at the source of MOS transistor  82 . Consequently, setting a low value at the read data high bit line  96 . The read data high and low bit lines  96  and  94  constitute a 0 and 1 if a low value is read from the storage node  100 .  
         [0029]    Numerous modifications and alternative embodiments of the invention will be apparent to those skilled in the art in view of the foregoing description. Accordingly, this description illustrative only and is for the purpose of teaching those skilled in the art the best mode for carrying out the invention. Details of the structure may vary substantially without departing from the spirit of the invention, and exclusive use of all modifications that come within the scope of the appended claims is reserved. It is intended that the invention be limited only to the extent required by the appended claims and the applicable rules of law.  
         [0030]    Having described the invention, what is claimed as new and protected by Letters Patent is: