Abstract:
A power supply noise eliminating method eliminates power supply noise in a semiconductor integrated circuit having a plurality of first terminals coupled to a first power supply voltage and one or a plurality of second terminals coupled to a second power supply voltage which is different from the first power supply voltage. The power supply noise eliminating method includes the steps of (a) supplying the first power supply voltage to one of the first terminals, and (b) supplying the second power supply voltage to another one of the first terminals via an impedance circuit, thereby eliminating the power supply noise with respect to at least the first power supply voltage.

Description:
BACKGROUND OF THE INVENTION 
     The present invention generally relates to power supply noise eliminating methods and semiconductor devices, and more particularly to a power supply noise eliminating method for eliminating power supply noise of a semiconductor integrated circuit which carries out a high-speed operation, and to a semiconductor device which uses such a power supply noise eliminating method. 
     In this specification, the &#34;power supply noise&#34; includes ground noise. 
     Semiconductor integrated circuits are used in systems with respect to which there are demands to realize high-speed operation and high performance. For this reason, there are demands to further increase the operation speed and to increase the number of terminals of the semiconductor integrated circuits. However, in order to cope with such demands requiring high-speed operation and large number of terminals of the semiconductor integrated circuit, a signal varying speed dI/dt and a number N of varying signals both become large, and power supply noise which is proportional to N·dI/dt is generated at a power supply or ground. This power supply noise is also proportional to an inductance of the terminals connecting the inside and the outside of the semiconductor integrated circuit. Accordingly, in general, the length of the terminals is made short and the terminals are coupled in parallel, so as to reduce the power supply noise by reducing the inductance of the terminals. 
     The number N of varying signals tends to increase considerably as the bus width of the system using the semiconductor integrated circuit increases from 8 bits to 16 bits, from 16 bits to 32 bits, and from 32 bits to 64 bits, for example. In addition, the signal varying speed dI/dt also increases considerably from several ns to 1 ns or less. For this reason, the value of N·dI/dt has become several tens times larger in recent years, and the power supply noise had a tendency of increasing therewith. 
     Power supply terminals, including ground terminals, of the semiconductor integrated circuit have an inductance on the order of several nH, and the power supply noise is generated by a rapid change in the current. In order to reduce this power supply noise, n power supply terminals are provided, where n is an integer greater than 1, so as to reduce the power supply noise to 1/n. 
     FIG. 1 is a circuit diagram showing an equivalent circuit of a power supply part of the semiconductor integrated circuit. As may be seen from FIG. 1, when n terminals are provided, an inductance L is reduced to 1/n or, a current deviation dI/dt of a current .sub.Δ i is reduced to 1/n, thereby reducing a voltage Vn=L·dI/dt which corresponds to the power supply noise to 1/n. In FIG. 1, Vcc denotes a power supply voltage. 
     However, an equivalent circuit of the actual semiconductor integrated circuit having a semiconductor chip is as shown in FIG. 2. In FIG. 2, R denotes a resistance with respect to a D.C. current which flows regularly, and C denotes a static capacitance of the semiconductor chip viewed from the power supply terminal. Accordingly, the equivalent circuit shown in FIG. 2 has a construction shown in FIG. 3 when viewed from a current source of the current .sub.Δ i. 
     An impedance Z of a parallel resonant circuit made up of the inductance L, the resistance R and the static capacitance C shown in FIG. 3 can be described by the following formula. 
     
         Z=x+jy 
    
     
         =1/{1/jωL)+(1/R)+jωC} 
    
     The following formula can be obtained by eliminating ω from the above formula. 
     
         {x-(1/2)R}.sup.2 +y.sup.2 +{(1/2)R)}.sup.2 
    
     When this formula is illustrated, a complex plane representation shown in FIG. 4 is obtained. In FIG. 4, the ordinate indicates the imaginary number, and the abscissa indicates the real number. For example, the resistance R is 50 Ω, the inductance L is 2 nH, and the static capacitance C is 100 pF. 
     When FIG. 4 is illustrated in a ω-plane, a ω-plane representation shown in FIG. 5 is obtained. In FIG. 5, the ordinate indicates the amplitude, and the abscissa indicates the frequency. In addition, in FIG. 5, a solid line indicates the real number portion, and a dotted line indicates the imaginary number portion. A parallel resonance of the parallel resonant circuit occurs at a frequency ωp=1/√LC, and an impedance corresponding to the D.C. current can be seen when viewed from the current varying point. As may be seen from FIG. 5, the impedance sharply assumes a large value at the parallel resonance frequency ωp. In this example, the impedance has a peak, that is, the parallel resonance point occurs, at a position where the impedance is approximately 50 Ω. 
     Accordingly, the current deviation dI/dt as it is becomes the power supply voltage deviation. For example, if the current deviation dI/dt is 5 mA when the D.C. power supply current .sub.Δ i is 50 mA, a power supply voltage deviation Vn which is 1/10 the power supply voltage Vcc occurs at the parallel resonance frequency ωp of the parallel resonant circuit. 
     Conventionally, the power supply noise which occurs at the power supply or the ground and is proportional to N·dI/dt was reduced by reducing the inductance of the terminals connecting the inside and the outside of the semiconductor integrated circuit. However, a certain distance is inevitably required to connect the inside and the outside of the semiconductor integrated circuit, and there was a limit to increasing the number of terminals. For this reason, the inductance of the terminals does not become zero even if the length of the terminals is reduced within the possible range and the number of terminals is increased within the possible range, and there was a problem in that it was impossible to considerably improve the effect of reducing the power supply noise. 
     On the other hand, when viewed from the power supply terminals, the semiconductor integrated circuit has a static capacitance, and a parallel resonant circuit is formed by this static capacitance and the inductance of the power supply terminals when the current varies. As a result, the impedance becomes infinitely large at the parallel resonance frequency of the parallel resonant circuit, and there was a problem in that ringing noise is generated thereby. In addition, even if the inductance of the terminals is reduced, this would only increase the parallel resonance frequency of the parallel resonant circuit, and the parallel resonance point will not be eliminated. Hence, reducing the inductance of the terminals will not solve the problem of the ringing noise. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is a general object of the present invention to provide a novel and useful power supply noise eliminating method and semiconductor device, in which the problems described above are eliminated. 
     Another and more specific object of the present invention is to provide a power supply noise eliminating method which eliminates power supply noise of a semiconductor integrated circuit and also prevent ringing noise, and to a semiconductor device which employs such a power supply noise eliminating method. 
     Still another object of the present invention is to provide a power supply noise eliminating method which eliminates power supply noise in a semiconductor integrated circuit having a plurality of first terminals coupled to a first power supply voltage and one or a plurality of second terminals coupled to a second power supply voltage which is different from the first power supply voltage, comprising the steps of (a) supplying the first power supply voltage to one of the first terminals, and (b) supplying the second power supply voltage to another one of the first terminals via an impedance circuit, thereby eliminating the power supply noise with respect to at least the first power supply voltage. According to the power supply noise eliminating method of the present invention, it is possible to effectively reduce the power supply noise of the semiconductor integrated circuit using a simple circuit construction, and also prevent generation of ringing noise. 
     A further object of the present invention is to provide a semiconductor device comprising a semiconductor integrated circuit having a plurality of first terminals for receiving a first power supply voltage and one or a plurality of second terminals for receiving a second power supply voltage different from the first power supply voltage, and an impedance circuit coupled between one of the first terminals and the second power supply voltage, so that power supply noise with respect to at least the first power supply voltage is eliminated. According to the semiconductor device of the present invention, it is possible to effectively reduce the power supply noise of the semiconductor integrated circuit using a simple circuit construction, and also prevent generation of ringing noise. 
     Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing an equivalent circuit of a power supply part of a semiconductor integrated circuit; 
     FIG. 2 is a circuit diagram showing an equivalent circuit of an actual semiconductor integrated circuit having a semiconductor chip; 
     FIG. 3 is a circuit diagram showing an equivalent circuit of the circuit shown in FIG. 2 when viewed from a current source; 
     FIG. 4 is a diagram showing a complex plane representation of a formula which indicates an impedance of a parallel resonant circuit by eliminating ω from the formula; 
     FIG. 5 is a diagram showing a ω-plane representation of FIG. 4 in a ω-plane; 
     FIG. 6 is a system block diagram for explaining the operating principle of a semiconductor device according to the present invention employing a power supply noise eliminating method according to the present invention; 
     FIG. 7 is a circuit diagram showing a first embodiment of the semiconductor device according to the present invention; 
     FIG. 8 is a circuit diagram showing the construction of a semiconductor chip; 
     FIG. 9 is a perspective view showing a semiconductor chip portion; 
     FIG. 10 is a circuit diagram showing an equivalent circuit of a semiconductor integrated circuit shown in FIG. 7; 
     FIG. 11 is a diagram showing a complex plane representation of the first embodiment when a series resonance frequency due to an impedance circuit is selected to 10 times a parallel resonance frequency; 
     FIG. 12 is a diagram showing a ω-plane representation of FIG. 11 in a ω-plane; 
     FIG. 13 is a diagram showing a complex plane representation of the first embodiment when the series resonance frequency due to the impedance circuit is selected equal to the parallel resonance frequency; 
     FIG. 14 is a diagram showing a ω-plane representation of FIG. 13 in a ω-plane; 
     FIG. 15 is a diagram showing a complex plane representation of the first embodiment when the series resonance frequency due to the impedance circuit is selected equal to the parallel resonance frequency; 
     FIG. 16 is a diagram showing a ω-plane representation of FIG. 15 in a ω-plane; 
     FIG. 17 is a diagram showing x with respect to a ζ-axis; 
     FIG. 18 is a diagram showing y with respect to the ζ-axis; 
     FIG. 19 is a circuit diagram showing a second embodiment of the semiconductor device according to the present invention; 
     FIG. 20 is a circuit diagram showing a third embodiment of the semiconductor device according to the present invention; 
     FIG. 21 is a circuit diagram showing a fourth embodiment of the semiconductor device according to the present invention; 
     FIG. 22 is a circuit diagram showing a fifth embodiment of the semiconductor device according to the present invention; 
     FIG. 23 is a circuit diagram showing a sixth embodiment of the semiconductor device according to the present invention; and 
     FIG. 24 is a perspective view showing an on-chip capacitor portion of the sixth embodiment on an enlarged scale. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First, a description will be given of the operating principle of a semiconductor device according to the present invention employing a power supply noise eliminating method according to the present invention, by referring to FIG. 6. 
     A semiconductor device shown in FIG. 6 includes a semiconductor integrated circuit 1, terminals 3 through 6, and an impedance circuit 7. The semiconductor integrated circuit 1 includes a semiconductor chip 2 and the terminals 3 through 6. L1 and L2 respectively denote inductances of the terminals 3 and 4. In FIG. 6, the illustration of the inductances of the terminals 5 and 6 is omitted. Of course, the number of terminals of the semiconductor integrated circuit 1 is not limited to 4. 
     The terminals 3 and 4 are power supply terminals for supplying a first power supply voltage to the semiconductor chip 2. In addition, the terminals 5 and 6 are power supply terminals for supplying a second power supply voltage to the semiconductor chip 2. For example, the first power supply voltage is Vcc, and the second power supply voltage is ground GND. The impedance circuit 7 is coupled between the terminal 4 and the second power supply voltage, for example. A circuit similar to the impedance circuit 7 and coupled between the terminal 5 or 6 and the first power supply voltage may be provided in place of or in addition to the impedance circuit 7. However, for the sake of convenience, it is assumed that only the impedance circuit 7 is provided. 
     When viewed from the power supply terminal 4, a parallel circuit is formed by the inductance L2 and the impedance circuit 7 which are coupled in parallel, but a synthesized impedance of the terminal 4 becomes zero at the resonance frequency of the impedance circuit 7. For this reason, it is possible to effectively eliminate the power supply noise. 
     On the other hand, when viewed from the power supply terminal 4 or the like, the semiconductor chip 2 has a static capacitance, and a parallel resonant circuit is formed by this static capacitance and the inductance of the power supply terminal 4 when the current varies. As a result, the impedance becomes infinitely large at a parallel resonance frequency of the parallel resonant circuit, and ringing noise would originally occur. However, in the present invention, the synthesized impedance of the power supply terminal 4 becomes zero at the resonance frequency of the impedance circuit 4. Accordingly, it is possible to prevent the generation of the ringing noise by appropriately selecting the parallel resonance frequency and the resonance frequency of the impedance circuit 7. 
     The construction of the semiconductor device is not limited to that shown in FIG. 6 wherein the impedance circuit 7 is provided externally to the semiconductor integrated circuit 1. The impedance circuit 7 may be provided within the semiconductor integrated circuit 1 or, the impedance circuit 7 may be provided within the semiconductor chip 2. When the semiconductor device is constructed such that the impedance circuit 7 is provided within the semiconductor integrated circuit 1, it is possible to provide a built-in power supply noise eliminating means within the semiconductor device, that is, within the semiconductor package. 
     The construction of the impedance circuit 7 is not limited to a specific construction, as long as the impedance circuit 7 includes at least one of capacitor, inductor and resistor. 
     FIG. 7 shows a first embodiment of the semiconductor device according to the present invention. This first embodiment of the semiconductor device employs a first embodiment of the power supply noise eliminating method according to the present invention. In FIG. 7, those parts which are the same as those corresponding parts in FIG. 6 are designated by the same reference numerals, and a description thereof will be omitted. 
     In FIG. 7, the impedance circuit 7 is a series circuit including a capacitor C2 and a resistor R2 which are connected in series. In addition, the semiconductor chip 2 has a construction shown in FIG. 8. As shown in FIG. 8, the semiconductor chip 2 includes a logic circuit 20, an output circuit 21, the power supply terminals 3 through 5, an input terminal group 11, and an output terminal 12. Of course, the number of terminals is not limited to that shown in FIG. 8. 
     FIG. 9 shows a perspective view of the semiconductor chip portion. In FIG. 9, the semiconductor chip 2 is provided on a substrate 25, and electrodes 24 of the semiconductor chip 2 are connected to the corresponding terminals 3 through 5, 11 and 12 via bonding wires 28. Hence, the inductance of each terminal includes the inductance of the corresponding bonding wire 28. 
     An equivalent circuit of the semiconductor integrated circuit 1 shown in FIG. 7 becomes as shown in FIG. 10. In FIG. 10, R1 denotes a resistance with respect to the D.C. current which flows regularly, and C1 denotes a static capacitance of the semiconductor chip 2 when viewed from the power supply terminal. 
     In other words, between the two power supply terminals 3 and 4 for supplying the first power supply voltage to the semiconductor chip 2, this embodiment supplies the first power supply voltage Vcc from only the power supply terminal 3, and the other power supply terminal 4 is coupled to the second power supply voltage, that is, the ground GND, via the impedance circuit 7. Hence, it is possible to reduce the impedance of the power supply terminals 3 and 4 by cancelling the maximum value obtained by the parallel resonance by the minimum value obtained by the series resonance, so that the power supply noise is effectively reduced. 
     When the value of the inductance L1 shown in FIG. 7 is denoted by L, the resistance of the resistor R1 is denoted by R and the value of the static capacitance C1 is denoted by C, an impedance Z of the parallel resonant circuit made up of the inductance L1, the resistor R1 and the static capacitance C1 can be described by the following formula. 
     
         Z=x+jy 
    
     
         =1/{(1/jωL)+(1/R)+jωC} 
    
     The following formula is obtained by eliminating ω from the above formula. 
     
         {x-(1/2)R}.sup.2 +y.sup.2 ={(1/2)R}.sup.2 
    
     When this formula is illustrated, complex plane representations shown in FIGS. 11, 13 and 15 are obtained. 
     FIG. 11 shows the complex plane representation of this embodiment when the series resonance frequency ωs due to the impedance circuit 7 is selected to 10 times the parallel resonance frequency ωp. In FIG. 11, the ordinate indicates the imaginary number, and the abscissa indicates the real number. For example, the resistor R1 is 100 Ω, the resistor R2 is 10 Ω, the inductances L1 and L2 are both 2 nH, the static capacitance C1 is 100 pF, and the capacitor C2 is 1 pF. 
     When FIG. 11 is illustrated in a ω-plane, a ω-plane representation shown in FIG. 12 is obtained. In FIG. 12, the ordinate indicates the amplitude, and the abscissa indicates the frequency. In addition, in FIG. 12, a solid line indicates the real number portion, and a dotted line indicates the imaginary number portion. The parallel resonance of the parallel resonant circuit occurs at the frequency ωp=1√L1C1, and the impedance corresponding to the D.C. current can be seen when viewed from the current varying point. As may be seen from FIG. 12, the impedance sharply assumes a large value at the parallel resonance frequency ωp. In this particular case, the impedance has a peak, that is, the parallel resonance point occurs, at a position where the impedance is approximately 100 Ω. 
     FIG. 13 shows a complex plane representation of this embodiment when the series resonance frequency ωs due to the impedance circuit 7 is selected equal to the parallel resonance frequency ωp. In FIG. 13, the ordinate indicates the imaginary number, and the abscissa indicates the real number. In this case, the resistor R1 is 100 n, the resistor R2 is 10 Ω, the inductances L1 and L2 are both 2 nH, the static capacitance C1 is 100 pF, and the capacitor C2 is 100 pF. 
     When FIG. 13 is illustrated in a ω-plane, a ω-plane representation shown in FIG. 14 is obtained. In FIG. 14, the ordinate indicates the amplitude, and the abscissa indicates the frequency. In addition, in FIG. 14, a solid line indicates the real number portion, and a dotted line indicates the imaginary number portion. As may be seen from FIG. 14, the impedance gradually assumes a large value at the parallel resonance frequency ωp. In this particular case, the impedance has a peak, that is, the parallel resonance point occurs, at a position where the impedance is approximately 10 Ω. 
     FIG. 15 shows a complex plane representation of this embodiment when the series resonance frequency ωs due to the impedance circuit 7 is selected equal to the parallel resonance frequency ωp. In FIG. 15, the ordinate indicates the imaginary number, and the abscissa indicates the real number. In this case, the resistor R1 is 50 Ω, the resistor R2 is 5 Ω, the inductances L1 and L2 are both 2 nH, the static capacitance C1 is 100 pF, and the capacitor C2 is 100 pF. 
     When FIG. 15 is illustrated in a ω-plane, a ω-plane representation shown in FIG. 16 is obtained. In FIG. 16, the ordinate indicates the amplitude, and the abscissa indicates the frequency. In addition, in FIG. 16, a solid line indicates the real number portion, and a dotted line indicates the imaginary number portion. As may be seen from FIG. 16, the impedance gradually assumes a large value at the parallel resonance frequency ωp. In this particular case, the impedance has a peak, that is, the parallel resonance point occurs, at a position where the impedance is approximately 5 Ω. 
     When the relationships ω=ωo(1+ζ), ωo=1√LC and Q=R/ωoL stand in a vicinity of the parallel resonance frequency ωp, x and y can be calculated as follows. ##EQU1## Since ##EQU2## and 
     
         1+ζ-{1/(1+ζ)}≅1+ζ-(1-ζ)=2ζ 
    
     the following formula stands. 
     
         x+jy=1/ 1+j2Qζ) 
    
     
         =(1-j2Qζ)/{1+(2Qζ).sup.2 } 
    
     Accordingly, x and y can be obtained as follows. 
     
         x=R/ 1+(2Qζ).sup.2 ! 
    
     
         y=-2Qζ/ 1+(2Qζ).sup.2 !R 
    
     FIG. 17 shows x which is obtained from the above formula with respect to the ζ-axis. Similarly, FIG. 18 shows y which is obtained from the above formula with respect to the ζ-axis. 
     A solution by Laplace transform is obtained as follows. ##EQU3## Since 
     
         (1/LC)-(1/2CR).sup.2 =(1/LC){1-(LC)/4C.sup.2 R.sup.2)} 
    
     
         =(1LC){1-L/(4CR.sup.2)} 
    
     and 
     
         (C/L)R.sup.2 =Q.sup.2 
    
     the following formula can be obtained. 
     
         (1/LC){1-L/(4CR.sup.2)}=(1/LC) 1-{1/(2Q)}.sup.2 ! 
    
     
         =ωo.sup.2  1-{1(2W)}.sup.2! 
    
     Accordingly, Z can be obtained from the following simplified formula. 
     
         Z=(1/C) S/ {S+(1/2CR)}.sup.2 +{1-(1/2Q).sup.2 }ωo.sup.2!! 
    
     A step response can be obtained from the following formula when I=Io/S. 
     
         V=Z·I 
    
     
         =(Io/C) 1/ {S+(1/2CR)}.sup.2 +{1-(1/2Q).sup.2 }ωo.sup.2!! 
    
     The power supply noise Vn can be obtained from the following formula because (1/ωoC)=ωwoL. ##EQU4## 
     Next, a description will be given of a second embodiment of the semiconductor device according to the present invention which employs a second embodiment of the power supply noise eliminating method according to the present invention. FIG. 19 shows the second embodiment of the semiconductor device. In FIG. 19, those parts which are the same as those corresponding parts in FIG. 7 are designated by the same reference numerals, and a description thereof will be omitted. In FIG. 19, L3 and L4 respectively denote inductances of the power supply terminals 5 and 6. 
     Between the two power supply terminals 5 and 6 for supplying the second power supply voltage to the semiconductor chip 2, this embodiment connects only the power supply terminal 5 to the second power supply voltage, that is, the ground GND, and the other power supply terminal 6 is coupled to the first power supply voltage Vcc via the impedance circuit 7. Hence, it is possible to reduce the impedance of the power supply terminals 5 and 6 by cancelling the maximum value obtained by the parallel resonance by the minimum value obtained by the series resonance, so that the power supply noise is effectively reduced. 
     Next, a description will be given of a third embodiment of the semiconductor device according to the present invention which employs a third embodiment of the power supply noise eliminating method according to the present invention. FIG. 20 shows the third embodiment of the semiconductor device. In FIG. 20, those parts which are the same as those corresponding parts in FIGS. 7 and 19 are designated by the same reference numerals, and a description thereof will be omitted. 
     In this embodiment, the impedance circuit 7 is provided independently with respect to the power supply terminals 4 and 6. As a result, it is possible to effectively reduce the power supply noise with respect to the first power supply voltage Vcc and also effectively reduce the ground noise with respect to the second power supply voltage GND. 
     Next, a description will be given of a fourth embodiment of the semiconductor device according to the present invention which employs a fourth embodiment of the power supply noise eliminating method according to the present invention. FIG. 21 shows the fourth embodiment of the semiconductor device. In FIG. 21, those parts which are the same as those corresponding parts in FIG. 20 are designated by the same reference numerals, and a description thereof will be omitted. 
     In this embodiment, between the two power supply terminals 3 and 4 for supplying the first power supply voltage to the semiconductor chip 2, only the power supply terminal 3 is connected to the first power supply voltage Vcc, and the other power supply terminal 4 is coupled to the power supply terminal 6 via the impedance circuit 7. The power supply terminal 5 is connected to the second power supply voltage, that is, the ground GND. Hence, it is possible to reduce the impedance of the power supply terminals 3 through 6 by cancelling the maximum value obtained by the parallel resonance by the minimum value obtained by the series resonance, so that the power supply noise is effectively reduced with respect to both the power supply voltage Vcc and the ground GND. 
     Next, a description will be given of a fifth embodiment of the semiconductor device according to the present invention which employs a fifth embodiment of the power supply noise eliminating method according to the present invention. FIG. 22 shows the fifth embodiment of the semiconductor device. In FIG. 22, those parts which are the same as those corresponding parts in FIG. 21 are designated by the same reference numerals, and a description thereof will be omitted. 
     In this embodiment, between the two power supply terminals 3 and 4 for supplying the first power supply voltage to the semiconductor chip 2, only the power supply terminal 3 is connected to the first power supply voltage Vcc, and the other power supply terminal 4 is coupled to the power supply terminal 6 via the impedance circuit 7. The power supply terminal 5 is connected to the second power supply voltage, that is, the ground GND. Hence, it is possible to reduce the impedance of the power supply terminals 3 through 6 by cancelling the maximum value obtained by the parallel resonance by the minimum value obtained by the series resonance, so that the power supply noise is effectively reduced with respect to both the first power supply voltage Vcc and the ground GND. 
     Furthermore, between two power supply terminals 53 and 54 for supplying a third power supply voltage to the semiconductor chip 2, only the power supply terminal 53 is connected to the third power supply voltage V, and the other power supply terminal 54 is coupled to a power supply terminal 56 via the impedance circuit 7. A power supply terminal 55 is connected to the second power supply voltage, that is, the ground GND. Hence, it is possible to reduce the impedance of the power supply terminals 53 through 56 by cancelling the maximum value obtained by the parallel resonance by the minimum value obtained by the series resonance, so that the power supply noise is effectively reduced with respect to both the third power supply voltage V and the ground GND. 
     In each of the embodiments described above, one or more impedance circuits 7 are provided externally with respect to the semiconductor integrated circuit 1. However, each impedance circuit 7 may be provided within the semiconductor integrated circuit 1 or within the semiconductor chip 2. 
     Next, a description will be given of a sixth embodiment of the semiconductor device according to the present invention which employs a sixth embodiment of the power supply noise eliminating method according to the present invention. FIG. 24 shows the sixth embodiment of the semiconductor device. In FIG. 24, those parts which are the same as those corresponding parts in FIGS. 7 through 9 are designated by the same reference numerals, and a description thereof will be omitted. 
     In this embodiment, the impedance circuit 7 is provided within the semiconductor chip 2, that is, within the semiconductor integrated circuit 1. The semiconductor chip 2 includes electrodes 24-1 through 24-4, 24-10 and the like, and the electrodes 24-2 and 24-3 are coupled to each other via the impedance circuit 7. The capacitor C2 is realized by a on-chip capacitor, and the resistor R2 is realized by a general thin film resistor. FIG. 24 shows a perspective view of this on-chip capacitor portion on an enlarged scale. As shown in FIG. 24, the electrodes 24-10 and 24-1, the electrodes 24-1 and 24-2 and the like are connected via bonding wires 28. Accordingly, the connection of the semiconductor chip 2 and the impedance circuit 7 is realized at the electrode portions of the semiconductor chip 2 by wire-bonding. 
     Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention.