Abstract:
A power supply (ringer power supply) for a telephone exchange comprising a first switching circuit for receiving and subjecting direct current to high frequency switching by means of a switching element, a converter transformer connected to the switching circuit, a smoothing circuit connected to the secondary side of the converter transformer, a second switching circuit connected to the output stage of the smoothing circuit and used for switching the input current by means of a transistor bridge of a plurality of transistors for being alternately turned on, a direct-current bypassing diode connected between the input and output terminals of each transistor, a driving circuit for driving each of the transistors in accordance with a predetermined driving signal, and a driving signal generator circuit for generating the driving signal for setting timing to prevent the period during which a transistor is turned on from overlapping the one during which another transistor is subsequently turned on, permitting a reduction in the size of the converter transformer for switching purposes and the current transformer for detecting current.

Description:
This application is a continuation of application Ser. No. 924,809, filed Oct. 30, 1986, now abandoned. 
    
    
     The present application claims priority of Japanese Patent Application No. 60-245629 and No. 60-245630 filed on Oct. 31, 1985 respectively and No. 61-073155 filed on Mar. 31, 1986. 
     FIELD OF THE INVENTION AND RELATED ART STATEMENT 
     This invention relates to a power supply for a telephone exchange and, more particularly, to a power supply of the sort installed in a telephone exchange and used to ring telephones (hereinafter called the &#34;ringer power supply&#34;). 
     FIG. 39 shows the construction of a conventional telephone exchange. 
     The telephone exchange shown in FIG. 39 comprises a DC/AC inverter I for switching direct current derived from a DC power supply E 1  (-48 V) and converting it into a current of low frequency (20 Hz), an output transformer T of the DC/AC inverter, a telephone D, a relay R for switching the connection of the telephone D from the channel to the output transformer line and vice versa, a detection circuit L for detecting the off-hook state (the state in which the receiver is left off the cradle) of the telephone D and a control circuit CONT, which will be described later. 
     In the above telephone exchange, the control circuit CONT causes the relay R to make the connection of the telephone D to the terminal B when the telephone D is called up and an AC of 85 V/20 Hz is thus supplied from the output transformer T to the telephone D. The bell (whose resistance is 10 kΩ) of the telephone D is thereby called and the control circuit CONT causes the relay to make and brake the connection thereof to the terminals A, B at fixed intervals to ring the bell of the telephone D intermittently until the receiver is left off the cradle. 
     When the receiver of the telephone D is left off the cradle, the resistance of the bell is canceled, whereas the detection circuit L detects the voltage change accompanied by the charged state of a capacitor C. On receiving a signal from the detection circuit L, the control circuit CONT locks the armature of the relay to the terminal A. 
     Assuming a plurality of telephones D are connected to the telephone exchange, AC voltage supplied to each telephone D drops, thus making the detection circuit L incapable of properly detecting the on/off-hook state of the telephone D. 
     A DC power supply E 2  (-48 V) is accordingly connected between the output transformer T and the terminal B of the relay R in the conventional telephone exchange to bias the AC voltage. 
     However, the conventional ringer power supply has posed a problem in that the output transformer T of the DC/AC inverter I is extremely large-sized. A description will subsequently be given of the above problem of size. 
     The transformer core size S is generally expressed by 
     
         A.sub.e ×A.sub.w 
    
     where A e  (cm 2 )=cross-sectional area of the core; and A w  (cm 2 )=total window area. 
     Given the input voltage is V (volts); the switching frequency is fHz; the magnetic flux density is B(G); and the number of primary winding turns of the transformer is N p  in turns, the following equation is applicable: 
     
         V=4×f×B×A.sub.e ×N.sub.p ×10.sup.-8 
    
     On the other hand, the equation shown below holds between the primary and secondary windings, provided that the loss in the transformer is negligible: 
     
         N.sub.p ×I.sub.p =N.sub.s ×I.sub.s 
    
     where primary current=I p  in amps; secondary current=I s  in amps; and number of secondary winding turns=N s  turns. 
     Moreover 
     
         δ=(N.sub.p ×I.sub.p +N.sub.s ×I.sub.s)/A.sub.c 
    
     where A c  =total sectional area of the primary and secondary windings in cm 2  ; and δ=winding current density in amps per square meter. Given that the copper wire occupying factor is β (=A c  /A w ), 
     
         A.sub.c =β×A.sub.w =(2×N.sub.p ×I.sub.p)/δ 
    
     The above equation can be changed into 
     
         I.sub.p =(δ×β×A.sub.w)/(2×N.sub.p) 
    
     Given the maximum input of the transformer is P volt-amps (VA), 
     
         P=V×I.sub.p =2×δ×β×B×f×A.sub.e ×A.sub.w ×10.sup.-8 
    
     Accordingly, the core size is determined by 
     
         A.sub.e ×A.sub.w =P/(2×δ×β×B×f×10.sup.-8) 
    
     However, if a switching power transistor is operated at low frequencies, the above f becomes small and A e  ·A w , i.e., the transformer core size becomes large. 
     Furthermore, the superposition of the direct current on the output stage of the DC/AC inverter I (the output line of the output transformer) makes the size of the transformer of the DC/AC inverter I larger. 
     When the direct current is superposed on the output of the DC/AC inverter I, there develops such nonuniformity that the inverter transformer is unevenly magnetized for the following reasons: 
     A push-pull inverter is employed in this case as shown FIG. 40. 
     (1) When the transistor Q 1  is turned on, voltage V 2  is generated in the secondary coil of the transformer T. The secondary coil current I s1  becomes ##EQU1## where Z=impedance in the secondary circuit. 
     (2) When the transistor Q 2  is turned on, current I s2  flowing through the secondary circuit because of the voltage generated in the secondary coil of the transformer T becomes ##EQU2## 
     (3) Therefore, given that the collector currents of Q 1 , Q 2  are I p1 , I p2 , ##EQU3## provided the turn ratio of the transformer is 1:n. 
     (4) In consequence, voltage VT applied to the primary coil of the transformer is: 
     when Q 1  is turned on, 
     
         V.sub.T1 =E-I.sub.p1 (ν.sub.1 +ν.sub.t1) 
    
     when Q 2  is turned on likewise, 
     
         V.sub.T2 =E-I.sub.p2 (ν.sub.2 +ν.sub.t2) 
    
     where ν 1 , ν 2  =internal resistances of transistors Q 1 , Q 2  ; ν t1 , ν t2  =the primary coil of the transformer. Even though variation in the constant of the part on the primary side is negligible, V T1  &gt;V T2  and voltage ΔV T  =V T1  -V T2  as a DC voltage component is applied to the coil of the transformer every period of switching. DC magnetic flux is applied while Q 1  is held on and the core is unevenly magnetized. 
     The B-H curve of the transformer core will not form a loop centering around the origin (FIG. 41) but normally around a deflected point (FIG. 42) if alternating current is used for excitation after the superposition of direct current. In consequence, the saturated magnetic flux density of the transformer core must be made greater, which in turn makes the size of the transformer larger. 
     As shown in FIG. 43, to stabilize the output of the switching element of the DC/AC inverter I through duty factor feedback control, a current transformer CT must be installed on the primary or secondary side of the output transformer T. However, the existing problem is that, if the switching frequency is low, the size of the current transformer CT also becomes large. 
     OBJECT AND SUMMARY OF THE INVENTION 
     The present invention is intended to solve the above problems and it is therefore an object of the invention to provide a ringer power supply whose output transformer for switching and current transformers for detecting current are extremely small-sized. 
     The ringer power supply embodying the present invention comprises a first switching circuit for receiving and subjecting direct current to high frequency switching by means of a switching element, a converter transformer connected to the first switching circuit, a smoothing circuit connected to the secondary side of the converter transformer, a second switching circuit connected to the output stage of the smoothing circuit and used for switching the input current by means of a transistor bridge consisting of a plurality of transistors for being alternately turned on, a direct-current bypassing diode connected between the input and output terminals of each transistor, a driving circuit for driving each of the transistors in accordance with a predetermined driving signal, and a driving signal generator circuit for generating the driving signal for setting timing to prevent the period during which a transistor is turned on from overlapping the one during which another transistor is subsequently turned on. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing the construction of a ringer power supply embodying the present invention. 
     FIGS. 2 and 3 are diagrams illustrating examples of the filter used in the telephone exchange. 
     FIG. 4 is a diagram illustrating the off-hook state as a circuit. 
     FIGS. 5 and 6 are diagrams illustrating other examples of the filter used in telephone exchange. 
     FIG. 7 is a circuit diagram showing a first configuration of the inverter in the embodiment thereof. 
     FIG. 8 is a circuit diagram showing a configuration of the inverter in the second embodiment thereof. 
     FIG. 9(a) is a time chart showing the ON/OFF time relation between the transistors in the circuit of FIG. 7. 
     FIG. 9(b) is a time chart showing the ON/OFF time relation among the transistors in the circuit of FIG. 8. 
     FIG. 10 is a diagram showing a direct current flow in the circuit of FIG. 8. 
     FIG. 11 is a diagram showing the characteristics of the circuit of FIG. 10 different ratios of L/R. 
     FIGS. 12(a) and (b) show a current flow and circuit characteristics in accordance with period 2 in FIG. 9 (a). 
     FIGS. 13(a) and (b) show a current flow and circuit characteristics in accordance with period 3 in FIG. 9(a). 
     FIGS. 14(a) and (b) show a current flow and circuit characteristics in accordance with period 4 in FIG. 9(a). 
     FIG. 15(a) and (b) show a current variation in accordance with periods ○1 ˜ ○4  in FIG. 9(a). 
     FIG. 16(a) is a diagram illustrating the construction of the inverter circuit of this invention. 
     FIG. 16(b) is a diagram illustrating the operation of the switching transistor of the circuit in FIG. 16(a). 
     FIG. 16(c) is a diagram illustrating the current variations of the circuit in FIG. 16. 
     FIGS. 17 and 18 show the current flow and circuit characteristics in accordance with the period  ○1  in FIG. 16(b). 
     FIGS. 19 and 20 show the current flow and circuit characteristics in accordance with the period  ○2  in FIG. 16(b). 
     FIGS. 21 through 23 are showing the current flow and circuit characteristics in accordance with the period  ○3  in FIG. 16(b). 
     FIGS. 24 and 25 show the current flow and circuit characteristics in accordance with the period  ○4  in FIG. 16(b). 
     FIGS. 26 and 27 show the current flow and circuit characteristics in accordance with the period  ○5  in FIG. 16(a). 
     FIGS. 28 and 29 show the current flow and circuit characteristics in accordance with the period  ○6  in FIG. 16(a). 
     FIG. 30 is a diagram illustrating length of dead time of the transistors in the circuit of FIG. 3. 
     FIG. 31 is a circuit diagram showing a first configuration of the power supply circuit in the circuit of FIG. 8. 
     FIG. 32 is a circuit diagram showing a second configuration of the power supply circuit therein. 
     FIG. 33 is a circuit diagram showing a configuration of the driving circuit in the circuits of FIGS. 31 and 32. 
     FIGS. 34 through 36 are diagrams showing configurations of blocks of the driving signal generator circuit in the circuits of FIGS. 31 and 32, respectively. 
     FIG. 37 is a diagram illustrating the operation of the driving signal generator circuit therein. 
     FIG. 38 is a diagram illustrating the binary counter in the driving signal generator circuit. 
     FIG. 39 is a circuit diagram showing a conventional telephone exchange. 
     FIG. 40 is diagram illustrating the construction of the general push-pull type inverter. 
     FIGS. 41 and 42 are diagrams illustrating the reason that the transformer in the conventional telephone exchange inevitably becomes large-sized. 
     FIG. 43 is a diagram showing the position of a current transformer fitted in the conventional telephone exchange. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Referring now to the accompanying drawings, a power supply for a telephone exchange according to the present invention will be described. 
     FIG. 1 is a circuit diagram showing the overall construction of a power supply embodying the present invention. 
     In FIG. 1, there is shown an arrangement of a DC power supply E 1 , a switching circuit S mainly consisting of power transistors, a (converter) transformer T 1  connected to the switching circuit S, a current transformer CT for detecting current flowing through the primary coil N 1  or secondary coil N 2  of the transformer T 1 , a smoothing circuit R, a DC/AC inverter I formed with a transistor bridge without employing a transformer as will be described later, DC input terminals P and N of the DC/AC inverter I, and AC output terminals U 1 , U 2  of the DC/AC inverter I. According to this example, the output of the inverter I is assumed to be in the form of a square wave. When such a waveform is utilized, high frequency noise at the time of switching is conducted from the output to the telephone circuit and may interfere with the operation of other equipment. It is therefore necessary to use a filter for removing the high frequency noise shown by a symbol F of FIG. 2 when such a square wave output is produced. The circuit shown in FIG. 2 also includes resistors R a , R b  in an off-hook detection circuit shown in FIG. 39, a telephone D, a DC blocking capacitor C, an equivalent resistor R R  in a bell sounding circuit, a talking circuit R D  connected in parallel with C and R R  at the time of off-hook, C, R R  and R C  being contained in the telephone. E 2  is similar to what is shown in FIG. 39. Since the impedance in the telephone at the time of off-hook is ##EQU4## the circuit shown in FIG. 2 may be simplified as shown in FIG. 3 at the time of off-hook, where γ=R a  +R b  +R D . 
     The load circuit thus composed of R a , R b  and the telephone D allows over N units of telephone to be simultaneously called and, provided N units of telephones are in the off-hook state, the N units of telephones are practically connected in parallel in the portion right to the points A, B. 
     When the maximum load is applied, the inverter is subjected to the most severe operating condition. Accordingly, the operation thereof under the severe condition will subsequently be examined. 
     As shown in FIG. 4, the state in which a maximum load is applied at the time of off-hook is represented by impedance Z. In other words, the impedance Z is derived from a filter F and a load equivalent to what is multiplied by N (γ per unit) as shown in FIG. 23(b). The above description is based on the fact that the waveform of the voltage applied by the inverter to the load is square. However, it may be preferred to apply sine wave voltage, instead of square wave voltage, to the telephone circuit. In this case, e.g., a dominant wave resonant filter shown in FIG. 5 is required as the filter F of FIGS. 2, 3. Consequently, the filter elements are arranged so that the inductance and capacitance may satisfy the requirements: ω 2  L 1  C 1  =1, ω 2  L 2  C 2  =1, where ω=basic angular frequency. Since the input voltage waveform is square, however, high frequency waves are contained as shown in FIGS. 3, 5, 7 . . . The operation of the circuit elements shown in FIG. 5 may be examined by partly omitting those high frequency waves, i.e., ##EQU5## provided the degree of the high frequency is k. C 1  and L 2  can thus be omitted against L 1  and C 2  respectively, so that the circuit configuration is simplified as shown in FIG. 26. The filter of FIG. 5 is accordingly considered the same in configuration as the LC filter F of FIGS. 2, 3 when the high frequency component is examined. As to the short period of the switching operation of the inverter, it should be reviewed how the component of the current flowing through the inverter changes is examined. Consequently, the operation in the case of FIG. 6 can be deemed likewise if the load in FIGS. 2,3 is taken into consideration. 
     Referring to FIG. 3, the circuit in question will be examined further. As FIG. 4 shows a simplified version of what is shown in FIG. 3, it is only necessary to consider the configuration of FIG. 4 in reference to FIGS. 2, 3. In order to facilitate the understanding of the operation of the circuit in the following description of the waveform, L and γ in Z will be referred to while C is ignored. 
     In that circuit, the voltage from the DC power supply E 1  is converted by the switching elements of the switching circuit S into what has a square wave with a switching frequency of 15 kHz or more. 
     The square wave voltage is applied to the primary winding N 1  of the transformer T 1  and, after being subjected to voltage transformation, sent out of the secondary winding N 2 . 
     The voltage thus produced is supplied to the smoothing circuit R and converted into DC voltage. The DC voltage is further converted by the DC/AC inverter I into low frequency alternating current, which is sent out of U 1  and U 2  to the load circuit Z. 
     In the above-described embodiment, direct current having desired voltage is obtained through the high frequency (over 15 kHz) switching carried out by the DC/DC converter consisting of the switching circuit S, the transformer T 1  and the smoothing circuit R, whereas desired low frequency alternating current is obtained in the DC/AC inverter I formed with a transistor bridge, whereby the power supply can be made compact because only the small transformer T 1  for the DC/AC converter is required. 
     In the above-described embodiment, moreover, the current in the high frequency switching means switching circuits is detected by providing the current transformer on the primary or secondary side of the transformer T 1  and, to stabilize the output, the current is so controlled that it is rectified and smoothed before being fed back by an amplifier to the oscillation circuit of the DC/DC converter. 
     In other words, since the current transformer CT is in a high frequency portion of the circuit rather than a low frequency portion as in conventional power supplies, the transformer size can be minimized, which therefore contributes to making the power supply smaller. 
     FIG. 7 is a circuit diagram showing, in concrete terms, the configuration of the DC/AC inverter I of FIG. 1. 
     In FIG. 7, there is shown a so-called half-bridge type inverter consisting of input terminals P, N, capacitors C 1 , C 2  for halving the supply voltage, power transistors Q 1 , Q 2 , and diodes D 1 , D 2  respectively connected in parallel between the input and output terminals (the emitters and collectors) of the power transistors Q 1 , Q 1  to regenerate magnetic energy to be stored in the inductance L connected to the output side of the inverter and allows the DC component derived from the DC power supply E 2  to flow while it is superposed on the alternating current. 
     The input voltage is halved by the capacitors C 1 , C 2  of the same capacitance. 
     When the power transistors Q 1 , Q 2  are turned on and off, square waves with 1/2 of the input voltage as an amplitude are obtained from the output terminal (the emitter of the power transistor). 
     FIG. 8 is a diagram showing another example of the inverter of FIG. 1 consisting of input terminals P, N, power transistors Q 1  ˜Q 4 , diodes D 1  ˜D 4  are for regenerating magnetic energy to be stored in the inductance L connected derived from the DC power supply E 2  to flow while it is superposed on the alternating current. The above circuit is a full-bridge type inverter. 
     In that circuit, the input voltage is so applied to a load that the output terminal U 1  is made positive and the output terminal U 2  negative for the period during which the power transistors Q 1 , Q 4  are held on and that the former U 1  is made negative and the latter U 2  positive for the period during which the power transistors Q 2 , Q 3  is held on. The square wave voltage is thus generated at the output terminals U 1 , U 2 . 
     FIG. 9(a) is a time chart showing the ON-time relation between the power transistors Q 1 , Q 2  in the half-bridge type circuit of FIG. 7. 
     Both the power transistors Q 1 , Q 2  are held off during a &#34;dead time&#34;. The dead time is set up to avoid a short between the terminals P, N when the power transistors Q 1 , Q 2  are simultaneously turned on because of the storage time of each. 
     Referring to FIG. 9(a), the waveform of the current flowing through the circuit will be described. 
     1. During the period  ○1 : 
     Q 1  is turned on and the current given by ##EQU6## flows as shown in FIG. 10, where i.sub. ○4 f =final value of the current i.sub. ○4  in the preceding period  ○4 . Assuming that the period  ○1  continues from t=0 up to t=t 1  and the value i.sub. ○1  at t=t 1  is i.sub. ○1 f as the final value of i.sub. ○1 , ##EQU7## is considered generally applicable, ##EQU8## 
     FIG. 11 shows the difference between the waveforms when L/R is large and small, respectively. 
     2. During the period of  ○2 : FIGS. 12(a), (b) i.sub. ○2 flows through the route of FIG. (a) and expressed by ##EQU9## The final value is ##EQU10## 
     3. During the period of  ○3 : FIGS. 13(a), (b) 
     Q 2  is turned on and i.sub. ○3  flows the route of FIG. 13(a) and is expressed by ##EQU11## and, since the final value is considered, ##EQU12## 
     4. During the period  ○4 , FIGS. 14(a), (b) ##EQU13## the magnetic energy stored in the inductance L is expressed by (1/2)Li.sub. ○4  2 . 
     (i) When L/R is small; i.sub. ○4 = 0 at 0≦t≦t 4  halfway. Therefore, the magnetic energy will completely be released at the point of time i.sub. ○4 =0. No electromotive force for turning on D 1  exists in the circuit thereafter and D 1  is held off. 
     (ii) When L/R is large; i.sub. ○4 &lt;0 even at t=t 4  during the 0≦t≦t 4  period. 
     In this case, the magnetic energy of L has not completely been released and D 1  is held on during the t 4  period. 
     (iii) In consequence, ##EQU14## 
     5. The current waveforms during the periods  ○1 ˜ ○4 may be summarized as shown in FIGS. 15(a), (b). There is shown the DC current component by E 2  therein. 
     During the dead time the above diodes D 1 , D 2 , the magnetic energy stored in the inductance L on the output side is regenerated and fitted to allow the the direct current derived from the power supply E to flow at all times and thereby prevent the terminals U 2 , U 2  in the circuit being insulated from each other, so that the direct current derived from the power supply E 2  is always kept flowing therein. 
     FIG. 9(b) is a time chart showing the ON-time relation between the power transistors Q 1  ˜Q 4  in the full-bridge type circuit of FIG. 8. 
     In FIG. 9(b), (1/2)T indicates the half-period of the input pulse; T 12 , T 21  the dead time during which both the power transistors Q 1 , Q 2  are held off; and T 34 , T 43  the dead time during which both the power transistors Q 3 , Q 4  are held off. 
     In the above example of FIG. 7, the power transistors Q 1 , Q 2  are alternately repeatedly turned on and off. 
     On the contrary in the circuit of FIG. 8, it has been so arranged that the ON-time width of the power transistors Q 2 , Q 4  is shorter than that of the power transistors Q 1 , Q 3 . In other words, the ON-time of the power transistors Q 1 , Q 3  is given by 
     
         (1/2)T-(T.sub.12 +T.sub.21) or 
    
     
         (1/2)T-(T.sub.34 +T.sub.43) 
    
     The dead time thus provided prevents a short between the terminals P, N when the power transistors Q 1 , Q 2  or Q 3 , Q 4  are simultaneously turned on. In this case, the dead time may be provided for the power transistors Q 1 , Q 3  by holding the power transistors Q 2 , Q 4  on and off every (1/2)T. 
     Referring to FIGS. 16(a), (b), (c), the wave forms of the currents flowing through the inverter circuit will be described. 
     1. During the period  ○1 , FIGS. 17, 18. 
     When Q 1 , Q 4  are turned on, i 1  flows in accordance with the following equation: ##EQU15## 
     where i.sub. ○6  designates the final value of the current in the preceding period. 
     Generally, ##EQU16## 
     2. During the period  ○2 , FIGS. 19, 20. 
     Because of the magnetic energy contained in the inductance L, electromotive force is generated across the inductor with positive (+) and negative (-) polarity and the diode D 3  is turned on. ##EQU17## 
     The magnetic energy contained in the inductance L is expressed by 1/2Li.sub. ○2  2 . 
     (i) When L/R is small; i.sub. ○2 =0 at 0≦t≦t 2  halfway. Then D 3  is turned off. By the point of time i.sub. ○2 =0, the magnetic energy of L will have completely been released. The electromotive force of the inductor L thus becomes zero. 
     (ii) When L/R is large; 
     Even at t=t 2 , i ○2 &gt;0. In this case, D 3  is held on during the period t 2 . Consequently, ##EQU18## 
     3. During the period  3○ , FIGS. 21, 22, 23. (i) When i.sub. ○2 f=0, E 2  as electromotive force causes current to flow as shown in FIG. 21 (curve 1 of FIG. 23). ##EQU19## 
     (ii) When i.sub. ○2 f&gt; 0, electromotive force because of the energy of L so develops as to provide such polarity as shown in FIG. 2 and allow allow the regenerative current to flow in accordance with: ##EQU20## 
     When i.sub. ○3 =0 during the 0≦t≦t 3  period then, D 2  is turned off and returned to the state (i) (curve 2 of FIG. 23). D 2  will be held on as shown by a curve 3 of FIG. 23, provided i.sub..sub. ○3 &gt;0 is maintained. 
     4. During the period  ○4 , FIGS. 24, 25. 
     The final value i.sub. ○3 f during the above period 3 takes an individual value depending on the following state: solely (i) exists, (i)-(ii) or only (ii) is present, so that the final value may be determined. 
     The current during the period 4 is given by ##EQU21## 
     5. During the period  ○5 , FIGS. 26, 27. 
     Since Q 3  is held on, ##EQU22## 
     6. During the period  ○6 , FIGS. 28, 29. 
     Because of the electromotive force of the inductor, D 1 , D 4  are turned on. ##EQU23## 
     (i) When L/R is small, i.sub. ○6 =0 at 0≦t≦t 6  halfway. Then D 1 , D 4  are turned off (when E&gt;E 2 ) 
     (ii) When L/R is large, i.sub. ○6 &lt;0 at t=t 6 . In this case, D 1 , D 4  are held on during the period t 2 . 
     7. In summarizing the above description, the current waveform shown in FIG. 16(c) is obtained with the mean value of the direct current generated in E 2 . 
     The diodes D 1  ˜D 4  during the dead time, the magnetic energy stored in the inductance L on the output side is regenerated and simultaneously it is fitted therebetween so as to allow the direct current deriving from the power supply E 2  to flow therethrough at all times and thereby prevent the terminals U 1 , U 2  in the circuit being insulated from each other, so that the direct current derived from the power supply E 2  is allowed to flow therethrough at all times. 
     During the period t 2 , the transistors Q 1 , Q 3  are turned on and off respectively. As shown in FIG. 20, the direct current is not allowed to flow therethrough after the magnetic energy stored in the inductor L is completely released. As shown in FIG. 30, however, that period is 1/2 of the dead time Td and almost negligible as compared with the ON-time (25 ms) of the transistors Q 1 , Q 2 . 
     FIG. 31 is a circuit diagram showing a configuration of the power supply circuit for power transistors in the full-bridge type inverter of FIG. 8. 
     In the above example, power is obtained from a bias winding magnetically coupled to the primary winding of a converter transformer T 1 . 
     In FIG. 31, there is shown an arrangement of a DC power supply E 1 , a switching circuit of the above-described DC/AC converter, a transformer (converter transformer) T 1 , the primary winding N1 1  of the transformer T 1 , the secondary winding N 2  thereof, auxiliary winding N s1  ˜N s4  magnetically coupled to the primary winding N 1  of the transformer T 1 , rectifying diodes D A1  ˜D A4 , smoothing capacitors C A1  ˜C A4 , and driving circuits D Q1  ˜D Q4  for driving transistors Q 1  ˜Q 4 . The diodes D A1  ˜D A4  are shown connected to the bases of the power transitors Q 1  ˜Q 4  of the full-bridge inverter shown in FIG. 8, respectively. 
     There is also shown therein a driving signal generator circuit DRV including input terminals 1, 2 connected to the auxiliary winding N s4 , output terminals 3, 6 respectively connected to photodiodes P D1  ˜P D4  of a photocoupler, the photodiodes P D1  ˜P D4  being connected to the input terminal 1 through current limiting resistors R 1  ˜R 4  of the inverter and used for superposing the direct current. 
     The power supply voltage E 1  in FIG. 31 is converted by the switching circuit S into square wave voltage, which is applied to the primary winding N 1  of the transformer T 1 . 
     Transformed square wave voltages are respectively taken out of the auxiliary windings N s1  ˜N s4  and rectified by the diodes D A1  ˜D A4 . The rectified voltages are smoothed by the capacitors C A1  ˜C A4  and converted into DC voltages, which are supplied to the driving circuits D Q1  ˜D Q4  and the driving signal generator circuit DRV. 
     The driving circuits D Q1  ˜D Q4  receive the driving signals from the photocoupler and drive the power transistors Q 1  ˜Q 4 . 
     The driving signals will subsequently be described. 
     The voltage across the capacitor C A4  is supplied to the driving signal generator circuit DRV. 
     The signals in accordance with the time chart of FIG. 7 are generated in the driving signal generator circuit DRV (described later). 
     The signals are then sent out of the output terminals of the driving signal generator circuit DRV and used to drive the diodes P D1  ˜P D4  of the photocoupler. The phototransistor forming a counterpart to the photodiode is arranged in each of the driving circuits DQ Q1  ˜D Q4  (described later). 
     FIG. 32 is a circuit diagram showing another configuration of the power supply circuit for the power transistors. 
     A special switching circuit is provided in this case to generate power. 
     In FIG. 32, there is shown an arrangement of a DC power supply E 1 , a switching transistor Q A , a diode D p1  for protecting the circuit when the input power is inadvertently reversed, a starting resistor R p1  for starting the transistor Q A , a base resistor R p2  for the transistor Q A , a speed-up capacitor C p2 , a capacitor C p3  and a resistor R p3  constituting a snubber circuit, a converter transformer T A , the primary widing N p1  of the converter transformer T a , an auxiliary winding N p2  for driving the switching transistor Q A , the secondary windings N s1  ˜N s4  of the converter transformer T A , rectifying diodes D A1  ˜D A4 , smoothing capacitors C A1  ˜C A4 , and driving circuits D Q1  ˜D Q4  respectively connected to the power transistors Q 1  ˜Q 4 . 
     There is also shown therein a driving signal generator circuit DRV similar to what is shown in FIG. 31, the generator circuit including input terminals 1, 2 connected to the secondary winding to photodiodes P D1  ˜P D4  of a photocoupler. The photodiodes P D1  ˜P D4  are respectively connected to the input terminal 1 through current limiting resistors R 1  ˜R 4 . An illustration will also be omitted of diodes which should respectively be connected between the collectors and emitters of the power transistors Q 1  ˜Q 4  of the inverter and used for superposing the direct current. 
     The power supply voltage E 1  in FIG. 32 is converted by the switching circuit Q A  into square wave voltage, which is applied to the primary winding N p1  of the transformer T A . 
     Transformed square wave voltages taken out of the secondary windings N s1  ˜N s4  and rectified by the diodes D A1  ˜D A4 . The rectified voltages are smoothed by the capacitors C A1  ˜C A4  and converted into DC voltages, which are supplied to the driving circuits D Q1  ˜D Q4 , respectively. 
     FIG. 33 is a diagram showing a configuration of the driving circuits D Q1  ˜D Q4  in FIGS. 31, 32. In the following description, i represents 1˜4. 
     In FIG. 33, there is shown an arrangement of input terminals 1,2, output terminals 3, 4, a phototransistor PQ i , resistors R 5  i R 6  i,a transistor Q Di  and output terminals 3, 4. 
     The output terminals 3, 4 are connected between the base and emitter of the transistor Q 1  of the inverter I of FIG. 8. 
     In FIG. 12, the phototransistor P Qi  forms a counterpart to the photodiode P Di . 
     The signal of the phototransistor P Qi  is amplified by the driving transistor QD i  and used to drive the power transistor Q i  of the inverter I. 
     That is , the phototransistor P Qi  is held on and the driving transistor Q Di  is held off when the photodiode P Di  is turned on, whereby the power transistor Q 1  is turned on as the current flows in the power transistor Q i  through (terminal 1)-(resistor R 6  i)-(base of the power transistor Q 1 ). 
     To make the operational timing of the power transistor Q i  conform to what is shown in FIG. 9(b), accordingly, the driving current of the photodiode PD i  should be the one corresponding to the timing chart of FIG. 9(b). 
     A description will lastly be given of the configuration of the driving signal generator circuit DRV for causing the power transistor Q 1  (i=1˜4) to operate in conformance with the timing chart of FIG. 9(b). 
     The driving signal generator circuit DRV consists of an oscillation circuit (a) for producing a high frequency signal, a logical operation circuit (b) for converting the high frequency signal into a low frequency signal, and a transmission circuit (c) for transmitting the signal prepared in the logical operation circuit to the driving circuit of the power transistor. 
     FIG. 34 is a diagram showing the configuration of the above oscillation circuit. 
     As shown in FIG. 34, the oscillation circuit consists of three inverters INV 1  ˜INV 3  connected in series, a resistor R T1  connected to those inverters in parallel, a resistor R T2  connected thereto in series and a capacitor C T  connected thereto in parallel. 
     FIG. 35 is a diagram showing the configuration of the above logical operation circuit. 
     As shown in FIG. 35, the logical operation circuit consists of inverters INV 4  ˜INV 11 , NAND gates NAND 1  NAND 7 , NOR gates NOR 1  ˜NOR 4 , and a binary counter BC. 
     FIG. 36 is a diagram showing the configuration of the above transmission circuit. 
     As shown in FIG. 36, the transmission circuit consists of a Zener diode D 2 , transistor Q Z` , Q P , Q 11  ˜Q 14 . 
     Taking a case where the driving signals of the power transistors Q 1 , Q 2  as an example, the operation of the driving signal generator circuit DRV will subsequently be described. 
     Each driving signal is sent out of the terminal C as the output of the inverter INV 7  and the terminal D as the output of the inverter INV 8  in the logical operation circuit of FIG. 35. 
     The terminal C is connected to the base of the transistor Q 1  and the terminal D is connected to the base of the transistor Q 2 , whereby each terminal turns on each transistor at H level. 
     (1) When both the transistors Q 1 , Q 2  are turned off (equivalent to the period  ○1  in FIG. 37): 
     In the binary counter BC of FIG. 35, the output Q 3  (bit at the highest position) should be set at H level, whereas all the continuous output bits Q 1  (the lowest bit) Q 8  should be set at H or L level. 
     (2) When the transistors Q 1 , Q 2  are turned off and on, respectively (equivalent to the period of  ○2  of FIG. 37): 
     The output Q 9  of the binary counter BC should be set at H level, whereas all the continuous output bits Q 1  ˜Q 8  should be prevented from being set at H or L level. 
     (3) When the transistors Q 1 , Q 2  are turned on and off, respectively (equivalent to the period  ○3  FIG. 37: 
     The output Q 9  of the binary counter BC should be set at L level, whereas the outputs Q 1  ˜Q 8  may be set at any level. 
     (4) When both the transistors Q 1 , Q 2  are turned on: 
     This can never occur. 
     The above output patterns of the binary counter BC are obtained by dividing the high frequency signal the oscillation circuit inputs through the terminal A and converting the signal into a low frequency signal. 
     The period of the oscillation circuit shown in FIG. 13 is determined by 
     
         T=K·R.sub.T1 ·C.sub.T (where K=proportional constant) 
    
     As set forth above, the output of the ringer power supply has been defined as 20 Hz=50 ms. 
     The continuous output bits of the output Q 1  ˜Q 9  of the binary counter BC amount to 2 8  =256 counts of what is equivalent to one count is 
     
         50 (ms)/256≈195 (μs). 
    
     Accordingly, it is only necessary to set the values of the capacitor C T  and the resistor RT 1  so that the period T of the oscillation circuit may become 195 μs. In the circuit of FIG. 36, further, the transistor Q 2  is turned on when the output of a power supply V cc  of a logic IC becomes lower than the Zener voltage of the Zener diode D 2  (while the logic IC operates normally) and the clear terminal of the binary counter BC is set at Level and counting is thus started. Simultaneously, the transistor Q P  of the transistors Q 11  ˜Q 14  is turned on and the collectors connected to the power supply V cc . 
     On the other hand, the driving transistors Q 11  ˜Q 14  are separated from the power supply V cc  when the supply voltage V cc  becomes slower than the Zener voltage. 
     The reason for this is that, when the supply voltage V cc  is low, the power transistor is prevented from being damaged by a short resulting from the malfunction of the logic IC allowing a signal with a different timing to be applied to the base thereof. 
     Referring to FIG. 38, the method of arranging the continuous output bits in the binary counter BC will be described. 
     Although the outputs Q 1  ˜Q 9  have been arranged in FIG. 35, the period of the driving signal of the power transistor may be increased or decreased by increasing or decreasing the number of output bits without changing the period of the oscillation circuit. 
     In that case, it is not always needed to select the bit Q 1  of the lowest rank and, provided Q k  up to Q k+n  halfway are arranged, counting of 2 k+h-1  is provided. Then the time Q 1  up to Q k  are counted is the dead time 
     
         T.sub.c =2.sup.k ×T.sub.0 
    
     of the transistor Q 1 , Q 2  or Q 3 , Q 4  T 0  designates the period of the oscillation circuit. 
     Since the dead time of the ringer output is thus the sum of the dead time of the transistors Q 1 , Q 2  and Q 3 , Q 4 , 
     
         T.sub.d =2T.sub.0 
    
     In the cases of the embodiment of FIGS. 31, 32, the driving signal generator circuit DRV is insulated from the driving circuits D Q1  ˜D Q4 . However, the driving signal generator circuit DRV and the D Q2 , D Q4 , may be held at the same potential by obtaining the power supplied to the driving signal generator circuit DRV from, e.g. C A3 . With the arrangement thus made, the driving circuits D Q2  D Q4 .need not be insulated from the driving signal generator circuit DRV in terms of direct current, so that the photocoupler between the driving circuits D Q2 , D Q4  and 4th and 6th output terminals of the driving signal generator circuit DRV may be omitted. 
     As set forth above, low frequency switching essential to the prior art on the primary side of the transformer of the DC/AC inverter can be dispensed with. In consequence, the size of the converter transformer for switching purposes and the current transformer for detecting current is reducible.