Abstract:
Methods and apparatus are disclosed for inhibiting the unauthorized copying of ROM-resident computer software or the like, for example, the audio-visual display of an electronic video game. A protection circuit including encryption/decryption means is coupled between the microprocessor and the ROM-memory and is operable in a first mode to properly encrypt/decrypt the program information according to a first algorithm and in a second mode to prevent proper encryption/decryption. The address-data buses are monitored by the protection circuit to detect an invalid program event, such as may occur when a microprocessor emulator is used to attempt an unauthorized copying or &#34;dumping&#34; of the program information. Upon detection of the invalid program event or &#34;trap condition&#34;, the protection circuit switches to its second operating mode thereby to prevent copying of the decrypted program information.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates in general to methods and apparatus for inhibiting the unauthorized copying or &#34;pirating&#34; of computer software. More specifically, the invention finds particular utility in inhibiting the unauthorized copying of the ROM-resident audio-visual display information of electronic video games. 
     Typically, electronic systems using microprocessors are manufactured with standard small scale or medium scale integration components and standard microprocessors. The system may be duplicated simply by copying the printed circuit board foil pattern and then installing on the copied boards the same standard components as used in the original system. Programmed ROM&#39;s are easily duplicated using inexpensive EPROM devices. Those of ordinary skill in the art will recognize that such copying of the system and program involves only the most rudimentary &#34;reverse engineering&#34; procedures. Such copying has been rampant in the coin-operated video game industry. Contraband games have resulted in enormous economic loss to the original game creators and to the authorized manufacturers as well as substantial and unnecessary legal expense in litigation to enjoin the unauthorized reproduction of the copyrighted games. 
     Copying of the above kind may be impeded by utilizing one or more custom integrated circuits of a type that are not readily duplicated or reverse engineered. A prospective copier would not likely be able to find an off-the-shelf replacement for such custom circuits. However, a modestly ingenious copier would most likely be able to replace the custom component with its functional equivalent by examining the microprocessor program and/or by exercising the custom hardware with a microprocessor emulator to determine its performance parameters. 
     An essential step in all unauthorized copying schemes is the ability to duplicate the microprocessor program either by dumping the program through use of a microprocessor emulator or by directly duplicating the ROM-resident  software. Either of these alternatives is a comparatively simple procedure with state of the art electronic video games. 
     SUMMARY OF THE INVENTION 
     It is, therefore, a primary objective of the present invention to inhibit and, as a practical matter, to prohibit the unauthorized copying of computer software information. This result is achieved by encrypting the program information stored in the memory and by implementing encryption/decryption circuitry interposed between the memory and the central processor in a fashion such that any attempt to dump the decrypted program through use of a microprocessor emulator or the like is promptly detected and effectively foreclosed. 
     During routine system operation, the central processor typically accesses the program ROM in a non-sequential order due to jumps, branches, sub-routine calls, interrupts and the like in the software program. Also, not every address in the ROM memory is typically used in a given program. Stated differently, not every address in the ROM need have valid data. 
     By contrast, when an attempt is made to copy the computer software using a microprocesor emulator, the ROM memory is normally accessed in a sequential manner and in general every address is accessed. In any event, it is virtually impossible for the emulator even on iterative attempts to access the various memory addresses in the same order as called for by the program software. 
     In accordance with the methods and apparatus of the present invention, the system is adapted to recognize what is herein defined as a &#34;trap condition&#34;. For purposes of the present invention, a &#34;trap condition&#34; is defined as an invalid program event in the sense that such an event would not occur in the ordinary and correct operation of the program software. Such an invalid event may occur, for example, when the emulator accesses an address not used in the program or when it accesses one or more address locations in an order other than that called for by the program. The method and circuitry of the invention is adapted to recognize the invalid program event and to shift the system to a &#34;trap&#34;0 operating mode. The system thereafter will return to the central processor only invalid or incorrect data. 
     Accordingly, the present invention is directed in one aspect to a method of inhibiting the unauthorized copying of computer software comprising the steps of: (a) storing digital program information in preselected address locations of a memory means in an encrypted form according to a first predetermined algorithm; (b) providing a computer processor for performing preselected functions only in response to the decrypted program information stored in the memory means; (c) coupling the address and data buses of the computer processor to the memory means through an encryption/decryption means selectively operable in a first mode to encrypt/decrypt the program information according to the first predetermined algorithm; (d) monitoring at least one of the address and data buses to detect trap address information; and (e) switching the encryption/decryption means from the first operating mode to the second operating mode if a trap condition is detected by the monitoring means. 
     Another facet of the invention is directed to a computer system including a central processor for performing preselected functions in response to digital program information stored in encrypted form in a memory means and communicated between the central processor and the memory means on address and data buses. Specifically, in its apparatus form, the present invention is directed to the improvement comprising an encryption/decryption means, coupled between the central processor and the memory means selectively operable in a first mode for encrypting/decrypting the program information according to a first predetermined algorithm and in a second mode for preventing the encryption/decryption of the program information according to the first predetermined algorithm. Detection means are provided for monitoring at least one of the address and data buses to detect an invalid program event in the form of a &#34;trap condition&#34;. Switching means shifts the encryption/decryption means from the first operating mode to the second operating mode in response to detection of the invalid program event. 
     Other aspects of the present invention will be appreciated by those skilled in the art upon reading of the detailed disclosure of the present invention as hereinafter set forth. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     The features of this invention which are believed to be novel are set forth with particularity in the appended claims. The invention, together with its objects and the advantages thereof, may be best understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements in the figures and in which: 
     FIG. 1 is a block diagrammatic representation of a computer system including the software protection circuit of the invention interposed between the central processor and the program memory; 
     FIG. 2 is a functional block diagram of the protection circuit of FIG. 1; 
     FIG. 3 is a schematic circuit diagram of a preferred embodiment of trap address protection circuit of FIG. 2; and 
     FIG. 4 is a block diagram illustration of the encryption circuit portion of the block diagram of FIG. 2. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to FIG. 1, there is shown in block diagrammatic form the computer portion 10 of a software driven system, such as a coin operated electronic video game. The computer may comprise a conventional microprocesser 12 and any of a variety of well known memory means 14 for storing digital program information. 
     In accordance with the present invention, the microprocessor 12 is coupled to the program memory 14 through a protection circuit depicted by the block 16. As will presently be seen, the protection circuit 16 encrypts the address information going to the program memory and decrypts the data coming from the program memory. To this end, an address bus 18 inputs a non-encrypted address location from the microprocessor 12 to the protection circuit 16. An encrypted address bus 20 couples the protection circuit 16 to the program memory 14. Similarly, an encrypted data bus 22 is coupled from the program memory 14 to the protection circuit 16 while the decrypted data bus 24 at the output of circuit 16 is coupled to the microprocessor 12. Address and data buses 26 and 28 are coupled respectively from the address bus 18 and the data bus 24 to other system components such as input/output devices, RAM memory or more ROM memory. The remaining portion of the system is not depicted in detail since its particular construction forms no part of the present invention. Furthermore, it will be understood that the manner in which the illustrated computer may be coupled to various software driven systems such as a coin-operated electronic video game, is familiar to those of ordinary skill in the art. 
     As will presently be seen, the protection circuit 16 includes encryption/decryption means coupled between the central processor 12 and the memory means 14 and selectively operable in a first mode for encrypting/decrypting the program information according to a first predetermined algorithm. Thus, the program information stored within the memory means 14 is in an encrypted format. Unless the encryption algorithm is known direct copying of the program memory 14 as may be accomplished by any of a number of well-known electronic devices will yield only useless data. However, merely encrypting the data stored in the program memory 14 would not materially impede a would be copier if the decrypted program could be read out of the system by use of a microprocessor emulator in place of the microprocessor 12 or if the protection circuit itself was readily reverse engineerable. To avoid the first possibility it is a feature of the present invention that the encryption/decryption portion of the protection circuit 16 be operable in a second mode for preventing the encryption/decryption of the program information according to the first predetermined algorithm. To effectively foreclose the second possibility, the protection circuit 16 is preferable comprised of an integrated circuit logic array. It is extremely difficult and expensive to reverse engineer a circuit network of any significant complexity that is made in this fashion. Of course, those skilled in the art will recognize that other integrated circuit alternatives may be used to make the protection circuit difficult, if not virtually impossible, to reverse engineer. 
     An understanding of the construction and functioning of a preferred embodiment of the protection circuit 16 may be had by reference to FIG. 2 which depicts in a functional block diagram form the several constituents of circuit 16. More particularly, circuit 16 includes an encryption or mapping circuit 30 having as inputs the address and data buses 18,22 and as outputs the address and data buses 20,24. As will presently be described in greater detail, the illustrated encryption circuit 30 is selectively operable according to one or the other of two different encrypt/decrypt algorithms depending upon the binary state of the signal input to circuit 30 on the encrypt select bus 32. A first predetermined algorithm, corresponding to a first operating mode, is used during normal operation to properly encode and decode the program information in memory 14. The remaining algorithm, corresponding to the second operating mode, occurs whenever the encrypt select bus is activated, for example, by a binary one input on line 32. In such event, the data returned to the microprocessor 12 does not correspond to the decrypted data from memory 14 and the system malfunctions. 
     The encryption circuit 30 is switched from its first or normal operating mode to the second, invalid operating mode by a detection means 34 and a switching means 36 coupled in serial relation between address bus 18 and the encrypt select bus 32. The detection means 34 monitors at least one of the address and data buses, in the present case address bus 18 via input 38, to detect an invalid program event, i.e., a trap condition. The output signal of the detection means 34 is applied via conductor 40 and as a series connected inverter 42 to one input of a switching means 36 which, as here illustrated, may be a conventional binary flip-flop circuit. The switching means 36 switches the encryption circuit 30 from its first to its second operating mode whenever the inverter 42 applies a low or binary zero input to the flip-flop 36. Such an event occurs in the pesent embodiment when and only when a trap condition in the form of a trap address is sensed by detection means 34. 
     Since the switching means 36 is bi-stable, the encryption circuit 30 will continue in the second operating mode until and unless it is reset. To this end, there is provided a reset detection means 44 likewise coupled in the present embodiment to the address bus 18 by an input 46. The recognition by the reset detection circuit 44 of a predetermined reset signal on address bus 18 results in a reset signal being applied to the clear or reset input 48 of the switching means 36 through an inverted 50 thereby to reset the encryption circuit 30 to its first operating mode. The reset circuit 44 may be of similar construction and operation as that of the trap address detection circuit 34 excepting that the reset circuit is designed to respond only to a unique signal input. 
     Referring now to FIG. 3, an exemplary form of the detection means 34 of FIG. 2 is illustrated in greater detail. For simplicity, it has been assumed in the present example that the detection performed on four lines of the address bus 18, These four (4) lines are denoted by A0-A3 in the drawing. The number of lines on which the detection function is performed is up to the discretion of the designer. Each of these address lines is selectively coupled as inputs to three AND gates 52, 54 and 56. The singular outputs of each of the AND gates is coupled as an input to a NAND gate 58 whose output constitutes the signal conductor 40. More particularly, the address bus A0 is directly coupled to the AND gates 52 and 56 and by an inverter 60 to the AND gate 54. Address line A1 is directly coupled to AND gates 54 and 56 and by an inverter 62 to the gate 52. Address line A2 is directly coupled to AND gates 52 and 54 and by an inverter 64 to AND gate 56. Finally, address line A3 is directly coupled to AND gate 54 and by an inverter 66 to each of and gates 52 and 56. In the particular detection circuit illustrated, the output 40 is driven to its high or binary one state whenever any of the following three addresses are asserted on the address lines A0-A3; 0101, 1110, and 0011. 
     If any one of the three (3) addresses above-identified appears on the address lines A0-A3, a latch signal in the form of a bianry zero will be applied to the present input of the switching means 36 thereby to active the encrypt select bus 32. For all other addresses asserted by the microprocessor, the output 40 of the detection means 40 will remain in its non-activated or normal state. 
     Referring now to FIG. 4, there is depicted in diagrammatic form an exemplary encryption/decryption circuit 30. Specifically, in the present embodiment, there is interposed between the address buses 18,20 a pair of parallel PROM-type encoding networks represented by blocks 54 and 56. Networks 54, 56 are coupled respectively between parallel branches 18A, 18B and 20A, 20B of the input and output address buses 18,20. 
     Similarly, in the present embodiment there are disposed in parallel between data buses 22, 24 a pair of PROM decoding networks 58,60 coupled respectively between parallel branches 22A, 22B and 24A, 24B of the input and output data buses 22,24. Those skilled in the art will appreciate that encryption/decryption networks may be coupled in only one of the address and data buses, instead of both buses as shown. 
     The two encoding networks 54, 56 are alternatively and selectively operable in response to the binary signal input on encryption select bus 32. To this end, the encryption select bus 32 is coupled to an enabling input of network 56 through and inverter 62 and directly to a like enabling input of network 54 by conductor 66. Enabling inputs of networks 58, 60 are likewise coupled to conductors 66, 64, respectively, such that networks 54, 58 and 56, 60 are always enabled/disabled in unison. 
     The several encoding/decoding networks may be similar in basic construction, but, of course, are operable according to different preselected algorithms. For instance, the encryption/decryption algorithms may be as simple as swapping two address lines, or substantially more complex, such as one-to-one mapping implemented with a PROM as depicted schematically in FIG. 4. Furthermore, it will be recognized that more than two algorithms could be used in the encryption circuit such that each address location would have more than two data values corresponding to it. A further alternative is to jump between encryption algorithms during normal circuit operation. The switching between algorithms may be done in a predetermined, timed relation to operation of the microprocessor clock. Thus, the first predetermined algorithm may in fact be composed of a complex of sub-algorithms in the general case. Those of ordinary skill in the art will recognize the wide range of conventional alternatives available for implementation of the encoding/decoding networks 54, 56, 58 and 60. 
     The detection and reset circuits previously discussed may likewise take a wide range of alternative forms consistent with the teachings of the present invention. An attempted assertion of a single, normally unused address location may alone actuate the detection circuit or a more substantial deviation from normal program operation may be utilized. For example, the detection means may &#34;trap&#34; only in response to the assertion or failure to assert a sequence of addresses, and actuation of the &#34;trap&#34; may depend upon either the address combinations or their permutations. Those skilled in the art will appreciate that the detection and reset means may be implemented in the described and other forms by known techniques to satisfy a wide variety of economic constraints and security requirements. 
     In operation, the microprocessor 12 will communicate with the memory 14 through the protection circuit 16 to effect normal system operation as long as the program proceeds to access address locations and/or return data as contemplated by normal program operation. The encrypted form of the data in the program memory 14 protects against direct copying of the program information, unless the copier also succeeds in reverse engineering of the protection circuit 16. As previously indicated, it is a comparatively simple task to design and to implement the protection circuit 16 in a form that renders it difficult, if not virtually impossible, to reverse engineer. 
     A momentary deviation from normal microprocessor operation sensed by detection means 34 will latch switch means 36 to an on state thereby to enable encryption select bus 32. An enable signal on bus 32 will switch the encryption/decryption circuit 30 from its first to its second operating mode. Thereafter, only invalid data will be returned to the microprocessor 12. A deviation from normal microprocessor program operation is inevitable when an  emulator is substituted for microprocessor 12 in an attempt to &#34;dump&#34; or read the stored program in memory 14. 
     The protection circuit 16 is reset to its first operating mode only by a predetermined coded input on address bus 18. Thus, once the attempted copying of the program is detected the system is locked into a malfunction mode that effectively prohibits further efforts to decrypt the program memory. The system will continue in its first operating mode until and unless a deviation from normal program operation is again detected. 
     It will be understood that the invention may be embodied in other specific forms without departing from the spirit or central characteristics thereof. The present embodiments are to be considered as being illustrative and not as being restrictive, and the invention is not to be limited to the details herein but may be modified within the scope of the appended claims.