Abstract:
Vector-specific test circuitry is added to an existing circuit design to enable improved fault test coverage by an existing fault test. Each vector-specific test circuit is designed to produce a single output indicative of whether any faults were detected in a plurality of previously unobservable node states produced in response to an associated test vector.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates in general to circuit testers and relates more particularly to a method of utilizing a class of vector-specific test circuits to improve fault coverage without significantly increasing Input/Output (I/O) pin count and/or I/O pin sharing. 
     In all integrated circuit manufacturing processes, some fraction of integrated circuits (ICs) manufactured by such processes have one or more faults. The fraction of manufactured ICs that are good is referred to as the yield of the process. Because yields can be significantly below 100%, it is important to test these ICs for faults. Preferably, chips are tested after they are each mounted into the packaging that provides protection and interfacing for connection to other chips so that faults produced by the process of packaging the chips are tested along with the faults produced by the process of manufacturing the ICs. 
     One class of faults that are particularly important to test are the &#34;stuck-at faults&#34;. These faults occur because of opens and/or shorts that result in a given node being stuck at zero or stuck at one, even though, in proper operation of the IC, it should achieve each of these values under appropriate circumstances. 
     In general, fault testing involves two separate components: (1) controlling the voltage on various circuit nodes and (2) testing to see if the actual voltages on such nodes equal the expected values. The first of these two components is referred to as the controllability component of fault testing and the second is referred to as the observability component of fault testing. To be able to apply test signals to the IC and to observe the responses of the IC to these signals, the ICs typically contain signal inputs and outputs, referred to as test points, to enable input of test signals to the IC and output of signals from the nodes being observed. 
     The typical manner of testing circuits for faults is illustrated in the following examples of fault tests of random access memories (RAMs). A typical RAM test sequence consists of a first phase of writing data to the RAM and a second phase of reading this data from the RAM and comparing it with expected data. During the first phase, the fault tester produces a first sequence of addresses and, for each generated address, also produces a data word that is written to the location identified by the generated address. During the second phase, the fault tester generates the same sequence of addresses and, for each generated address, the actual data in the location identified by that address is compared with the data that is supposed to be in that location. 
     In one particular manner, this class of fault tests is particularly simple -namely, there is no problem in controlling or observing the state of each memory element of the RAM. The RAM can be fully tested by filling it with all possible different combinations of data and, for each combination of stored data, checking to see that each piece of stored data is correct. However, since the number of these combinations for a RAM containing N M-bit memory locations is 2 MN , even at the high clock rates available today, it would take an impracticably long time to enter all of these possible combinations. Therefore, carefully chosen subsets of these possible combinations are generated (typically in accordance with some algorithm) to test for particular classes of faults. RAM test algorithms are exemplified by the walking 1&#39;s, walking 0&#39;s, checkerboard and write address algorithms illustrated in FIGS. 1-4, respectively. 
     Fault testing of most circuits is more difficult and inherently less complete than is possible in fault tests of RAMs because of the difficulty and/or impossibility of controlling the value of every node that should be tested and of the difficulty and/or impossibility of observing the actual value that is stored on each such node. Fault simulation tests typically provide a list of those potential faults that are tested. However, whether because of limitations on the acceptable duration of fault tests or because of the inability to control and/or observe some of the circuit nodes of interest, fault tests will in general be incomplete. The fraction of possible faults that are actually tested by a given fault test is referred to as the &#34;fault coverage&#34; of such test. 
     In the article by Lawrence W. Goldstein, et al, entitled SCOAP: Sandia Controllability/Observability Analysis Program, a program is discussed that analyzes the controllability/observability problem of various circuits. Circuits are divided into two classes of circuits: combinational circuits in which the binary value of every node is uniquely determined at any given time by the data applied at that time on the input lines; and sequential (i.e., state-dependent) circuits that each includes memory elements (e.g., flipflops) so that, at any given time, the binary value of at least some of the circuit nodes depends not only on the input data at that time, but also on at least some previously applied input data and on the initial state of this circuit. Sequential circuits are particularly difficult to test because of the state-dependent nature of its response to test input. Fault tests for sequential circuits will therefore generally exhibit a lower fault coverage than will combinational circuits having a comparable number of components. 
     The article by Thomas W. Williams, et al entitled Design for Testability-A Survey, IEEE Transactions On Computers, vol. C-31, No. 1, January 1982, discusses a fault test technique, referred to as the Level-Sensitive Scan Design, that addresses the difficulty of testing sequential circuits. This technique utilizes a &#34;shift register latch&#34; to convert a network into a purely combinational circuit. 
     As circuit complexity and density has increased, the difficulty of generating test patterns and simulating faults has drastically increased. The article by Williams et al presents a number of other testing techniques and approaches, some of which are applicable to many circuits and others that are limited to narrow classes of circuits. One of these techniques addresses the problem that the duration of a fault test is approximately proportional to the number of logic gates to the power 3. In accordance with this technique, jumpers and/or gates are included in a circuit board to enable components on a circuit board to be isolated (i.e., &#34;partitioned&#34;). This enables each of these isolated components to be separately tested, thereby greatly reducing the time required for a fault test of the entire circuit board. For example, if the board consists of M components, each containing on the order of N logic gates, then a test of the entire circuit requires a time interval approximately proportional to (MN) 3 . In contrast to this, a test of the isolated components requires a time proportional to M*(N 3 ) which has reduced the test time by a factor of M 2 . 
     Because of the extremely large number of nodes of typical circuits manufactured today, it has gotten extremely difficult to access all of the nodes that need to be accessed either to apply test signals or that need to be observed to produce test output. It is also difficult to access all of these nodes through the limited number of test points that can be placed on a chip. As indicated in the article by Thomas W. Williams, et al, shift registers are often included in circuits to enable a string of test data to be output through a single output test point. 
     The problem of limited IC surface area available for input/output (I/O) test points is also addressed in U.S. Pat. No. 4,749,947 entitled Grid-Based, &#34;Cross-Check&#34; Test Structure For Testing Integrated Circuits, issued to Tuchar R. Gheewala on Jun. 7, 1988. This cross-check test structure utilizes a set of M horizontal probe lines that form a rectangular grid of intersections with a set of N vertical sense lines. This enables a rectangular array of MN test points, each located near one of these intersections, to be monitored. Only one probe line is activated at any given time. If the mth probe line is activated, then the test points adjacent to the mth row of intersections of the grid are each output to an associated one of the vertical sense lines. In other embodiments, the total number of input and output points required for fault testing can be reduced to 6 by use of various devices such as shift registers. 
     SUMMARY OF THE INVENTION 
     During testing by any given fault test, there are generally a plurality of nodes on which either the zero or the one state was produced at least once during this fault test, but this state was not observable. In accordance with the illustrated preferred embodiment, vector-specific test circuits are utilized to improve fault coverage without significantly increasing Input/Output (I/O) pin count and/or I/O pin sharing. Each of these vector-specific circuits has a plurality of inputs, each of which is connected to a node on which, at some time during the fault test, an unobservable state was produced. 
     In accordance with this testing method, each node is assigned a unique identifier (e.g., a unique number, letter, or x-y coordinate within the chip). Each of these nodes can be in one of two binary electrical states: the zero state or the one state. If the ith node is in the zero state, this will be referred to herein as the &#34;node state&#34; S i  =0 and if it is in the binary one state this will be referred to herein as the node state S i  =1. 
     During testing, a set of signal inputs, referred to herein as input test points T 1 , . . . , T M  of the circuit, are utilized to apply test signals to this circuit. At any given time, the set of values of these M test signals is referred to herein as a &#34;test vector&#34;. The jth of these test vectors is indicated herein as V j . Thus, if the binary value of the kth input test point is represented as T j   k , then the jth test vector can be represented as V j  =(T j   1 , T j   2 , . . . , T j   M ). 
     For sequential circuits, there are some fault tests that are state-dependent-that is, it is not only necessary to observe a certain node state, it is important to observe that node state at the time of application of a particular one of the test vectors. For state-independent fault tests, such as stuck-at fault tests, the observed node states can be observed at any time during the test. These latter types of state-independent fault tests are easier to implement. 
     During any particular fault test there may be some node states that are never expected to occur during this fault test even though such node state can occur during normal device operation. For example, during this particular test, there may be a node m that is expected to be in the node state S m  =1 at all times during the fault test. That the state S m  =0 is not produced at any time during this fault test is an issue of controllability. This issue is not addressed herein. What is addressed herein is the issue: for all node states that are produced by any given fault test, are any of these actually generated node states unobservable. If there are, then the circuit design is modified to include one or more vector-specific test circuits that make some of these previously unobservable node states observable. 
     To determine the number of such vector-specific circuits that are to be added to a given circuit and to determine the structure of these vector-specific circuits, a table is made that correlates all presently unobservable node states of the existing circuit with those test vectors that produce these unobservable node states. A decision is then made as to which of these unobservable node states are to be observed. Some of the node states selected to be made observable can be included because it is particularly important to observe that node state. However, in most cases, the set of node states that are selected to be made observable is determined by a desire to have some minimum level of fault coverage. 
     Because the number of input/output (I/O) test points on the IC will usually need to be increased to provide access to these vector-specific test circuits and because it is important to keep the number of additional I/O pins low, it is advantageous to achieve the desired level of fault coverage by adding only the minimal number of vector-specific circuits needed to achieve the desired fault coverage. If each of these vector-specific test circuits is to be coupled to an associated additional I/O test point, then the space available for such additional I/O test points can be the limiting device parameter that limits the number of vector-specific test circuits that can be added to the IC. 
     The number of vector-specific test circuits needed to achieve the desired level of fault coverage can be substantially minimized by the following procedure. First, those test vectors on this list are identified that produce the maximal number of unobservable node states. One of these vectors is selected and the list is modified to remove all references to those node states produced in response to this first selected test vector. On this modified list, those test vectors that produce the maximal number of unobservable node states are identified. One of these vectors is selected and the list is again modified in this manner. This procedure is repeated until the set of unobservable node states produced by this set of selected vectors exceeds the number of unobservable states that are to be made observable. 
     For each of these vectors, a vector-specific test circuit is added to the IC design to make these node states observable. These vector-specific circuits can have the form of a multiple input AND gate in which some of the inputs can be inverting inputs. The outputs of these AND gates are coupled to circuit output test points so that it can be determined whether these nodes all have their expected values. In other embodiments, data compression circuitry, such as shift registers, can be coupled to one or more of the inputs and/or outputs of these vector-specific test circuits to reduce the number of additional I/O test points required to access these vector-specific test circuits. These vector-specific test circuits can also have the form of other functional equivalents of such AND gate. 
     This class of vector-specific test circuits is particularly attractive because only a single output need be observed to check whether all of the node states made observable by this circuit indeed occur at the time of application of the associated test vector. Therefore, these circuits substantially reduce the number of I/O test points that need to be added to the circuit to be able to observe these newly observable node states. Because of the limited area of the chip, if each output of a vector-specific test circuit is to be separately observable, then the maximum number of I/O test points that can be fitted on the chip will determine the maximum number of vector-specific test circuits that can be added to the IC. However, several techniques are available to collect data from a multiplicity of such vector-specific circuits and output such data from the IC over a single I/O test point. For example, each output of a vector-specific circuit can be input to an associated bit of a shift register and then this data can be read by shifting it though a single output of the shift register. 
    
    
     DESCRIPTION OF THE FIGURES 
     FIG. 1 illustrates a walking 1&#39;s pattern in memory, 
     FIG. 2 illustrates a walking 0&#39;s pattern in memory, 
     FIG. 3 illustrates a checkerboard pattern in memory. 
     FIG. 4 illustrates a write-address pattern in memory, 
     FIG. 5 is a flow diagram of the method of FIGS. 6A-6C, 
     FIGS. 6A-6C illustrate a method of identifying a succession of test vectors that cooperatively enable a selected number of additional previously unobservable node states to be observed by a substantially minimal number of vector-specific test circuits. 
     FIG. 7 illustrates a particular vector-specific test circuit that tests a set of n previously unobservable node states during one test cycle. 
     FIGS. 8 and 9 illustrate alternate embodiments of the vector-specific test circuit of FIG. 7. 
     FIG. 10 illustrates an embodiment that utilizes a register that enables data from all vector-specific test circuits to be output from the IC through a single I/O test point. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     For any given circuit under test and for any given fault test used to test this circuit, the degree of fault coverage is increased to a selected level of fault coverage by the method illustrated in FIG. 5 and FIGS. 6A-6D. Typically, because of the inability to produce every node state that should be tested, in a typical fault test, there is inherently less than full fault coverage. This is a problem of controllability that is not addressed by the present invention. Likewise, in a typical fault test, it is possible to observe only a portion of all of the node states that are actually produced by the fault test. This is a problem of observability that is addressed by the present invention. 
     In accordance with the present invention, at least some of the unobservable node states that are actually produced are made observable by including in the circuit under test vector-specific circuits that enable testing of some of these node states. A systematic method of selecting these vector-specific circuits is presented and specific examples of these vector-specific circuits are illustrated. 
     In accordance with the method of selecting these vector-specific circuits, each unobservable node state s; that is produced by the given fault test is correlated with all test vectors v; that generate that node state (step a in FIG. 5). This correlation can take the form of a table (such as that illustrated in FIG. 6A) that correlates all presently unobservable node states with all vectors that produce any of these node states. In FIG. 6A, the unobservable node states s; that are actually generated by the fault test are listed along the vertical axis of this table and the complete set of test vectors v; that each generate at least one of the unobservable node states is listed along the horizontal axis of this table. The correlation between each of these node states and a test vector that generates that node state is indicated by the presence of an x at the intersection of the row representing that node state and the column representing that vector. 
     Those vectors are identified (step b in FIG. 5) that produce the greatest number of presently unobservable node states. Such vectors are referred to herein as &#34;maximal vectors&#34;. In FIG. 6B, the three maximal vectors are V 8 , V 37   and V 44 , each producing seven unobservable node states. 
     One of these maximal vectors is selected for use with an associated vector-specific test circuit to test for all of these previously unobservable node states (step c in FIG. 5). In this particular case, the maximal vector V 8  is selected, simply because it is the first listed of these vectors. As will be discussed below, other choices may actually turn out to be preferable. However, each of these choices will result in a selection of vectors and associated node states generated by these selected vectors which result in substantially minimizing the number of vector-specific circuits required to achieve a given choice of fault coverage. It should be noted that the threshold level of fault coverage is inherently limited by the inability to produce all of the node states that should be observed (i.e., the controllability issue) so that this determines the upper limit of fault coverage that can be achieved by the method and associated vector-specific circuitry presented herein. 
     This table is now modified to eliminate this vector and all of the node states that are now testable by the associated vector-specific test circuit when this vector is applied. That is, every row corresponding to one of these newly observable node states is eliminated from this table and the column corresponding to this vector is eliminated from this table (step d in FIG. 5). The elements that are to be deleted from this table are underlined in FIG. 6B. The table resulting from the deletion of these elements is illustrated in FIG. 6C. 
     A threshold level of fault coverage is selected (step h) at some time during the above-indicated steps. Typically, this level is selected before step a, but since this determination is not needed before this point in the design procedure, this decision can be put off to this point in the procedure. The dashed line connecting element h to elements a-g signifies that his is the preferred point of the connection from step a into the remainder of the flow diagram, but that step a could be connected to any other node of this flow diagram. 
     The level of fault coverage is now calculated for the modified circuit that includes the vector-specific test circuit that implements testing of the node states produced by vector V 8  and is compared with the threshold level (step e). If this level has not been reached, then steps a-e are repeated. If this level has been reached, then the vector-specific test circuit associated with each of these selected vectors are designed and incorporated into the circuit (step g). It is convenient to delay design and implementation of these vector-specific test circuits until all of the associated vectors have been selected, but each such circuit can alternatively be designed or designed and implemented at each pass around the loop a-f in FIG. 5. 
     In an alternate embodiment of this method, after step e, a step f is executed in which the number of vector-specific test circuits required to this point in the analysis is compared with some maximal number of such circuits that will be implemented. For example, because of surface area limitation for I/O test points for the outputs of these vector-specific test circuits, there may be some maximal number of circuits that either can be, or will be allowed to be implemented. 
     Another alternate embodiment of this method can implement a more reasoned approach in step c to selecting which maximal vector to utilize. For example, a computer program can easily evaluate the resulting fault coverage that will result along any path of selections that result from the various possible choices available in step 2. There will be one or more of these paths that result in the threshold being achieved with the fewest number of vector-specific test circuits or that achieves the highest level of fault coverage when the maximum allowed number of vector-specific test circuits is reached. 
     It is also possible to implement a procedure that circumvents the structured approach of FIG. 5 and replaces steps b and c by a new step of just selecting any vector without regard to its impact on fault coverage. This method can then be implemented for all possible paths of selection to produce a more complete set of data thereby enabling a true minimization of the number of vector-specific test circuits that are required to reach a selected level of fault coverage. 
     In a further variant of the method of FIG. 5, the maximal vectors are defined to include, in addition to those vectors of FIG. 5, any vector that produces a node state that is in some way critical, or, at least particularly important, to device operation. Thus, step b is modified to implement this definition of maximal vector. Step c is now modified to require that the maximal vector selected in this step be one of these &#34;critical maximal vectors&#34; if any are still among the set of maximal vectors. Otherwise, the procedure is as discussed above in regard to FIG. 5. 
     The preferred embodiment of the vector-specific test circuits is illustrated in FIG. 7 for vector V 8 . Since V 8  produces seven associated unobservable node states, this circuit is an AND gate 71 having seven inputs 72, each of which is coupled to an associated one of the nodes on which are produced the node states to be observed. Each node that is to be high (i.e., a &#34;1&#34; state) when this vector is applied by the fault test is coupled to an associated noninverting input of this AND gate. Each input to a node that is to be low (i.e., a &#34;0&#34; state) when this vector is applied by the fault test is coupled to an associated inverting input of this AND gate. Thus, the signal produced at an output 73 of this AND gate is high only if all of the node states observed by this AND gate are correct. Thus, this vector-specific test circuit enables all seven of these node states to be tested concurrently at the occurrence of the associated test vector and the result can be detected on a single output 73, thereby providing significant reduction in the number of output test points needed to observe these node states. 
     There are a number of circuits that are &#34;functional equivalents&#34; of the vector-specific test circuit of FIG. 7. One trivial example, is the same device modified to have an inverting output. 
     Another example of a functional equivalent is a NOR gate that is the Boolean logic equivalent of this AND gate. That is, according to Boolean logic: 
     
         A.sub.1 ®A.sub.2 ®(˜A.sub.3)®A.sub.4 =˜[(˜A.sub.1)⊕(˜A.sub.2)⊕A.sub.3 ⊕(˜A.sub.4)]                                    (1) 
    
     where ˜ represents the logical NOT operation, ® represents the logical AND operation and ⊕ represents the logical OR operation. In such NOR gate, each inverting input of the AND gate becomes a noninverting input of the NOR gate and each noninverting input of the AND gate becomes an inverting input of the NOR gate. This embodiment is illustrated in FIG. 8. It consists of a NOR gate 81 having three noninverting inputs 82 and four inverting inputs 82 and one inverting output 83. 
     Another functional equivalent of an AND gate is an AND gate in which a first subset of the inputs are applied directly to this AND gate and a second subset of the inputs are applied to an NOR gate having its output connected to a noninverting input of the AND gate. For example, FIG. 9 illustrates a functional equivalent of the vector-specific circuits of FIGS. 7 and 8. The three inverting inputs 72 of FIG. 7 become noninverting inputs 92 to a NOR gate 91 and the output 93 of this NOR gate is applied to a noninverting input of an AND gate 94. The four noninverting inputs 72 to AND gate 71 each becomes a noninverting input 95 of AND gate 94. The output signal is produced on an output 96. This embodiment has the advantage of simplicity and reduced size. Because these embodiments are all functional equivalents of an AND gate, the words &#34;AND gate&#34; herein will include not only a traditional AND gate, but in additional will include all functional equivalents that produce the response characteristic of an AND gate. The words &#34;vector-specific AND gate&#34; mean an AND gate having a noninverting input for each binary 1 node state that is to be observed at the occurrence of an associated test vector and has an inverting input for each binary 0 node state that is to be observed at the occurrence of this associated test vector. The words &#34;vector-specific AND gate&#34; also mean any functional equivalent of such AND gate. 
     As illustrated in FIG. 10, to reduce the number of output test points required to implement these vector-specific test circuits, a plurality of AND gates 1001A-1001Z each has its output connected to an input of an associated stage of a shift register 1002A-1002Z. This enables the information from all of these vector-specific test circuits to be output over only a single output line 1003.