Abstract:
Micromachined devices and methods for making the devices. The device includes: a first wafer having at least one via; and a second wafer having a micro-electromechanical-systems (MEMS) layer. The first wafer is bonded to the second wafer. The via forms a closed loop when viewed in a direction normal to the top surface of the first wafer to thereby define an island electrically isolated. The method for fabricating the device includes: providing a first wafer having at least one via; bonding a second wafer having a substantially uniform thickness to the first wafer; and etching the bonded second wafer to form a micro-electromechanical-systems (MEMS) layer.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. Provisional Application Nos. 61/273,538, entitled “Performance enhancements and fabrication method of micromachined integrated 6-axis inertial measurement device,” filed on Aug. 4, 2009, and 61/273,494, entitled “Micromachined inertial sensor devices and methods for making same,” filed on Aug. 4, 2009, which are hereby incorporated herein by reference in their entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    The present invention generally relates to inertial sensor devices and, more particularly, to micromachined inertial sensor devices and methods for making the devices. 
         [0003]    With the rapid advance of modern electronic technology, various electronic devices, such as navigation systems, cell phones, and electronic games, require sensors that can accurately determine motions of the devices at low cost with small form factor. Conventional techniques have been developed to bump micro-electro-mechanical-systems (MEMS) chips on ASIC wafers or integrate MEMS with ASIC wafers. However, majority of the existing MEMS sensors measure either acceleration or rotation, but not the  6  degrees-of-freedom (three independent accelerations and three independent rotations) of an object. As such, the existing ASIC wafers for detecting the motion of an object in 6 DOF have large form factors to accommodate multiple MEMS sensors and extra circuits or algorithms to handle the data received from the multiple sensors. Furthermore, fabrication of multiple MEMS and packaging/integration of MEMS with ASIC wafers increase the manufacturing cost of the sensor devices. Thus, there is a need for a single MEMS device that can detect the motion of an object in 6 DOF so that the overall form factor and manufacturing cost of a sensor device that contains the MEMS can be significantly reduced. 
       SUMMARY OF THE INVENTION 
       [0004]    In one embodiment of the present invention, a method for fabricating a device includes: providing a first wafer having at least one via; bonding a second wafer having a substantially uniform thickness to the first wafer; and etching the bonded second wafer to form a micro-electromechanical-systems (MEMS) layer. 
         [0005]    In another embodiment of the present invention, a device includes: a first wafer having at least one via; and a second wafer having a micro-electromechanical-systems (MEMS) layer and bonded to the first wafer. The via forms a closed loop when viewed in a direction normal to a top surface of the first wafer to thereby define an island electrically isolated. 
         [0006]    These and other features, aspects and advantages of the present invention will become better understood with reference to the following drawings, description, and claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1A  shows a schematic top view of a Global positioning System (GPS) having a multi-DOF device in accordance with an embodiment of the present invention; 
           [0008]      FIG. 1B  shows a schematic cross sectional view of the Global positioning System (GPS) taken along the line  1 B- 1 B; 
           [0009]      FIG. 1C  shows an enlarged cross sectional view of the multi-DOF device of  FIG. 1B ; 
           [0010]      FIGS. 2A-2J  show a process for fabricating a via wafer of  FIG. 1C  in accordance with another embodiment of the present invention; 
           [0011]      FIGS. 3A-3B  show a process for fabricating a device layer of  FIG. 1C  in accordance with another embodiment of the present invention; 
           [0012]      FIGS. 4A-4B  show a process for fabricating a cap wafer of  FIG. 1C  in accordance with another embodiment of the present invention; 
           [0013]      FIG. 5  shows a sensor unit that includes a cap wafer bonded to the device layer and the via wafer fabricated by the processes depicted in  FIGS. 2A-3B ; 
           [0014]      FIG. 6  shows the sensor unit of  FIG. 5 , where the cap wafer is processed to have a new thickness and a marker; 
           [0015]      FIG. 7  shows the sensor unit of  FIG. 6 , where the via wafer is processed to have a new thickness; 
           [0016]      FIGS. 8A-8C  show the process for making contacts on the via wafer of  FIG. 7 ; 
           [0017]      FIG. 9  shows a schematic diagram of a sensor unit, where the sensor unit includes a MEMS layer directly bonded to an ASIC wafer in accordance with another embodiment of the present invention; 
           [0018]      FIG. 10  shows the via/cap wafer of  FIG. 9  fabricated by the process described in conjunction with  FIGS. 2D-2J ; 
           [0019]      FIGS. 11A-11B  show a process for fabricating a device layer of  FIG. 9 ; 
           [0020]      FIG. 12  shows a sensor unit that includes an ASIC wafer that is metal-bonded to the device layer of  FIG. 11B ; 
           [0021]      FIGS. 13A-13D  show steps for processing the via wafer of  FIG. 12 ; 
           [0022]      FIG. 14  shows a step for processing the sensor of  FIG. 13D ; 
           [0023]      FIG. 15  shows a schematic diagram of a sensor unit in accordance with another embodiment of the present invention; 
           [0024]      FIG. 16  shows a schematic diagram of a sensor unit in accordance with yet another embodiment of the present invention; 
           [0025]      FIG. 17A-17F  show a process for fabricating a via wafer in accordance with still another embodiment of the present invention; 
           [0026]      FIG. 18  shows a sensor assembly having the via wafer of  FIG. 17F  bonded to a device layer in accordance with a further embodiment of the present invention; 
           [0027]      FIG. 19  shows a schematic top view of a via wafer in accordance with yet further another embodiment of the present invention; 
           [0028]      FIG. 20  shows a schematic cross sectional view of the via wafer of  FIG. 19 , taken along the line  1900 - 1900 ; and 
           [0029]      FIG. 21  shows a schematic top view of vias in accordance with still further another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0030]    The following detailed description is of the best currently contemplated modes of carrying out the invention. The description is not to be taken in a limiting sense, but is made merely for the purpose of illustrating the general principles of the invention because the scope of the invention is best defined by the appended claims. 
         [0031]      FIG. 1A  shows a top view of a Global Positioning System (GPS)  10  having a multi-DOF device (or sensor unit)  22 , where a lid  14  (shown in  FIG. 1B ) is taken off to reveal the inner structure of the GPS  10 . (Hereinafter, the GPS is used as an exemplary application having the multi-DOF device  22 . However, it should be apparent to those of ordinary skill in the art that the multi-DOF device may be applied to various types of electronic devices.) As depicted, the multi-DOF device  22  is bumped on an ASIC wafer  20  via bumps  30 , where the ASIC wafer communicates signals with a suitable device located outside the GPS  10  via wires  18  and contacts/vias  16 . As an alternative, the multi-DOF device  22  may be wire-bonded to ASIC wafer  20 . 
         [0032]    The GPS  10  may include other sensors, such as pressure sensor  24 , Z magnetic sensor  26 , and XY magnetic sensor  28 . The pressure sensor  24  may be connected to the ASIC wafer  20  via bumps  30 . The XY magnetic sensor  28  and Z magnetic sensor  26  may be wire-bonded to the ACIS wafer  20 . As an alternative, the XY-magnetic sensor  28  and Z magnetic sensor  26  may be bumped on the ASIC wafer  20 . A housing  12  and the lid  14  enclose the components of the GPS  10 . The ASIC wafer  20  and the magnetic sensors  26 ,  28  may be secured to the housing  12  via a suitable attaching material, such as glue. 
         [0033]      FIG. 10  shows an enlarged view of the multi-DOF device  22  of  FIG. 1B . As depicted, the multi-DOF device  22  includes a cap wafer  102 ; a device layer (or, equivalently, MEMS layer)  106  that includes MEMS structures; and a via wafer  108 . The cap wafer  102  may be metal bonded to the device layer  106  along the perimeter of the device layer, where the metal bonding  104  can generate thermal stress between the cap wafer  102  and the device layer  106  during operation. To isolate the device layer  106  from the thermal stress, a stress reducing groove  120  may be optionally formed around the perimeter of the device layer  106 . The metal bond  104  may be a non-high temperature fusion bond and enable the application of getter to maintain a long term vacuum and application of an anti-stiction coating to prevent stiction that could occur to low-g acceleration sensors. The via wafer  108  may be fusion bonded, such as silicon-silicon fusion bonded, to the device layer  106  along the perimeter of the device layer  106 , obviating thermal stress between the via wafer  108  and the device layer  106 . 
         [0034]    In another embodiment, a fusion bond, such as silicon-silicon fusion bond, may be used in place of the metal bond  104 . In still another embodiment, the device layer  106  may be metal bonded to the via wafer  108 . 
         [0035]    The via wafer  108  may include a protruding portion (or, equivalently, anchor)  103  that provides an anchoring (attaching) structure for the device layer  106 . The anchor  103  may be located near the center of the via device layer  106 . The anchor  103  may be fusion bonded to the device layer  106 , to thereby eliminate potential problems associated with metal fatigue. 
         [0036]    Sensors formed in the device layer  106  measure small changes in capacitance to detect angular displacements. As such, any external electric or magnetic field may affect the accuracy in the measurement of the angular displacements. To shield the external electric and magnetic fields, the device layer  106  and the cap wafer  102  are electrically connected to each other and preferably grounded. 
         [0037]    The via wafer  108  includes multiple regions separated by isolating trenches (or, equivalently, vias)  114 . The core  118  of each via  114  is filled with conductive non-crystalline material, such as polysilicon or metal. The core  118  is electrically insulated by dielectric material  116 , and can be electrically biased to the voltage at the electrode, to create a zero voltage differential and thereby to eliminate the shunt capacitance of the via. 
         [0038]    Each of the regions separated by the isolating trenches  114  has an electrical contact for data communication. For example, as depicted in  FIG. 10 , the via wafer  108  may include three contacts  110 ,  111 , and  112  that may be connected to an ASIC wafer by bumps or wire-bonds. In another example, the contact  110  may be an electrode contact that is connected to the via  114 , while the contact  111  may be an anchor contact electrically connected to the anchor  103 , and the contact  112  is a circular via contact electrically connected to the via  114 . 
         [0039]    The device layer  106  may include MEMS structures that function as gyroscopes and acceleration sensors. Electrical connections to the MEMS structure is achieved through anchors and by capacitive coupling between isolated regions of the via wafer  108  and the device layer  106 . Detailed description of the MEMS structure and its operation is disclosed in a copending U.S. patent application Ser. No. 12/849,742, entitled “Micromachined inertial sensor devices,” filed on Aug. 3, 2010, which is hereby incorporate herein by reference in its entirety. 
         [0040]    The dimension of the cap wafer  102 , the device layer  106 , and the via wafer  108  may vary according to the application of the multi-DOF device  22 . For example, the thicknesses of the cap wafer  102 , the device layer  106 , and via wafer  108  may be 350 μm, 60 μm, and 150 μm, respectively. Gaps on both top and bottom sides of the device layer  106  may be 2 μm, for instance. The metal bond  104  and the fusion bond (not shown in  FIG. 10 ) between the device layer  106  and the via wafer  108  may have a ring shape, and the width of the ring can be 75 μm to ensure hermetic sealing and structural strength. The width of the anchor  103  may be 5 μm. 
         [0041]    The multi-DOF device  22  may also include anti-stiction coating to reduce potential problems for acceleration sensors. In one embodiment, the gyros of the device layer  106  may require a high vacuum packaging to deliver a high Q factor. Also, the acceleration sensors of the device layer  106  may need relatively high vacuum to enable operation near critical damping for fast settling. Thus, during the sealing process (or, equivalently, during the bonding process of the device layer  106  to the cap wafer  102  and the via wafer  108 ), a getter material may be used to ensure vacuum level inside the device  22  below 2 mTorr over 5 years. In another embodiment, the device layer  106  may include an accelerometer that requires a certain level of gas pressure inside the cavity formed by the cap wafer  102  and the via wafer  108 , where the gas pressure may be different from the atmospheric pressure. In such a case, the sealing should be able to maintain the pressure difference during the life expectancy of the device  22 . 
         [0042]      FIGS. 2A-2J  show a process for fabricating the via wafer  108  of  FIG. 10 . As shown in  FIG. 2A , the process starts with a flat double-side-polished (DSP) wafer  200  having a predetermined thickness, preferably 725 μm. The wafer  200  may be made of P-type dopant silicon and its resistivity is equal to or less than 0.02 ohm-cm. To make one or more etch marker masks  210  (shown in  FIG. 2C ), a suitable etching technique using a photoresist layer may be applied. For instance, a photoresist layer  202  may be applied on the surface of the wafer  200 . Then, UV light passing through a mask  204  may be applied to the photoresist layer  202 , to thereby make a pattern on the photoresist layer  202 . Then, the soft portions  208  where the UV light was blocked by the mask may be washed away to expose the surface of the DSP wafer  200  according to the pattern layout of the mask  204 . Then, by a suitable etching technique, such as deep-reactive-ion-etching (DRIE) or reactive-ion-etching (RIE) technique, the DSP wafer  200  may be etched to generate the etch marker masks  210 . The etch marker masks  210  may be used to align the via wafer  108  to internal patterns after bonding and need to be etched deep enough to be visible after processing. 
         [0043]    Via openings  212  of  FIG. 2D  may be etched by the similar process described in conjunction with  FIGS. 2A-2C . For instance, the deep-reactive-ion-etching (DRIE) technique with a patterned photoresist layer may be used to etch the via openings  212 . The depth of each via opening  212  may be 150 μm and the width may be 10 μm, for instance. The slope of the side wall of each opening  212  is about 80-85 degrees, which is necessary for no seams or keyholes in polyfill. 
         [0044]    Upon making the masks  210  and the via openings  212 , the entire surface of the wafer  200  is oxidized to grow a 1-μm thick thermal oxide layer  216 , as shown in  FIG. 2E . The oxide layer  216  would form oxide liners  116  for the vias  114  ( FIG. 10 ). It should be apparent to those of ordinary skill in the art that the layer  216  may be formed of any other suitable dielectric material that can electrically insulate the core portions of the vias  114 . 
         [0045]    As depicted in  FIG. 2E , a conformal polysilicon layer  214  is deposited over the oxide layer  216 . The polysilicon may be low stress polysilicon deposited at the temperature of 585-600° C. 
         [0046]    As depicted in  FIG. 2F , portions of the polysilicon layer  214  on the top surface of the wafer  200  may be etched by a suitable etching technique, such as chemical-mechanical-polishing (CMP), standard RIE using plasma (SF6), or DRIE. The polysilicon layer  214  deposited on the lower surface of the wafer  200  may cause stress in the wafer  200 , and thus is entirely removed to expose the oxide layer  216  deposited over the mask  210 , 
         [0047]      FIG. 2G  shows a photoresist layer  218  deposited on the top surface of the oxide layer  216 , where the photoresist layer  218  may be patterned by the technique described in conjunction with  FIGS. 2A-2B . It is noted that the edges of each via  217  are located away from the actual via structure to eliminate the risk of stacking faults that can be generated on the bond surface  219  (shown in  FIG. 2H ). Then, as depicted in  FIGS. 2H-2I , portions of the oxide layer  216  are etched by a suitable etching technique, such as DRIE or standard RIE using SF6, that uses the patterned photoresist layer  218  as a mask. It is noted that the polysilicon of the via  217  is etched so that it is recessed below the bond surface  219 , as depicted in  FIG. 21 . It is noted that the top surface of the via wafer  200  is etched to form a cavity. Optionally, the cavity may be formed on the bottom surface of the device layer  106  (shown in  FIG. 1 ) so that portions of the bottom surface of the device layer  106  is spaced apart from the top surface of the via wafer  108 . 
         [0048]    After etching the oxide layer  216 , the remaining photoresist layer  218  may be stripped off of the top surface of the wafer  200 , as shown in  FIG. 21 . As a final step, portions of the oxide layer  216  remaining on the top and bottom surfaces of the wafer  200  may be removed by the buffered-oxide-etching (BOE) technique, as depicted in  FIG. 2J . 
         [0049]      FIGS. 3A-3B  show a process for fabricating the device layer  106  of  FIG. 10  in accordance with another embodiment of the present invention. As depicted in  FIG. 3A , a standard silicon wafer  300  is fusion bonded (such as silicon-silicon fusion bond) to the via wafer  200 . Then, the silicon wafer  300  may be ground to the thickness of 60 μm and polished by CMP technique. It is noted that a silicon-on-insulator (SOI) vendor could supply a wafer  300  that is processed to this stage. Then, a bond metal layer  302  may be deposited and patterned on the wafer  300 . Note that the bond metal layer  302  is needed if the bond  104  between the cap wafer  102  (shown in  FIG. 10 ) and the device layer  106  (shown in  FIG. 10 ) requires metal layers on both sides of the bond  104 . 
         [0050]    The silicon wafer  300  may be patterned and etched to form MEMS structures, as shown in  FIG. 3B . The steps described in conjunction with  FIGS. 2A-2C  could be used to pattern and etch the silicon wafer  300 . For instance, a photoresist layer may be deposited and patterned to cover the metal layer  302  and a suitable etching technique can be used to pattern the silicon wafer  300 . Then, the photoresist layer may be stripped off of the silicon wafer  300 . It may be needed to clean the silicon wafer  300  with N-Methyl Pyrrolidone (NMP) stripper to remove etch residues (outgassing) and to verify that all of the chemicals remaining in the cavities are removed. If necessary, the patterned silicon wafer  300  may be cleaned by the CO 2  snow cleaning technique or critical point dry (CPD) technique to remove the chemicals remaining in the device layer  300 . 
         [0051]    As disclosed in the previously cited application Ser. No. 12/849,742, the etched silicon wafer (or, micro-electromechanical-system layer)  300  may include micromachined integrated 6-axis inertial measurement device that can measure angular rates about three axes and accelerations about three axes simultaneously. 
         [0052]      FIGS. 4A-4B  show a process for fabricating the cap wafer  102  of  FIG. 10  in accordance with another embodiment of the present invention. As depicted in  FIG. 4A , a DSP wafer  400  is prepared, where the wafer may be a standard wafer having a thickness of 725 μm, for instance. Then, using a suitable etching technique, such as DRIE or RIE using a photoresist layer, a cap recess  402  having a predetermined depth, preferably 1-2 μm, is formed. Next, as depicted in  FIG. 4B , a bond metal layer  406  may be deposited and patterned on the wafer  400  using a suitable etching technique, such as RIE or DRIE with a photoresist layer. Note that the bond metal layer  406  is needed if the bond  104  between the cap wafer  102  (shown in  FIG. 10 ) and the device layer  106  (shown in  FIG. 10 ) requires metal layers on both sides of the bond. The metal bond  104  between the device layer  106  and the cap wafer  102  may include Au—Si, Cu—Cu, Au—Sn solder or other suitable materials for hermetic bonding. 
         [0053]      FIG. 5  shows a sensor unit  500  that includes the cap wafer  400  bonded to the device layer  300  and the via wafer  200  fabricated by the processes depicted in  FIGS. 2A-3B . As discussed above, the bond  502  (which is the same as the bond  104  in  FIG. 10 ) may be a metal bond. To pattern the bond  502 , a suitable etching technique, such as DRIE or RIE using a photoresist layer, may be used. The bond  502  may include Au—Si, Cu—Cu, Au—Sn solder or other suitable materials for hermetic bonding. If needed, a trench (not shown in  FIG. 5 ) may be used to constrain the bond metal, where the trench may be etched by DRIE technique on one or more of the three layers  200 ,  300 , and  400  to contain the eutectic flow. 
         [0054]    The cap wafer  400  may be ground to a predetermined thickness, preferably 350 μm and polished. Then, as shown in  FIG. 6 , the markers  606  formed on the via wafer  200  are transferred to the cap wafer  400  so that new markers  604  are formed in the cap wafer  400 . The transfer may be performed by a suitable etching technique, such as DRIE or RIE using a photoresist layer. (In the present document, an etching technique using a photoresist layer refers to the process similar to that described in conjunction with  FIGS. 2A-2C .) 
         [0055]      FIG. 7  shows a sensor unit  700 , where the via wafer  702  of the unit  700  is generated by grinding the via wafer  202  of  FIG. 6 . As depicted in  FIG. 7 , the bottom side (or, equivalently, the via side) of the via wafer  202  of  FIG. 6  is ground to the thickness of 150 μm and polished so that the vias  708  may be exposed. The device layer  704  and the cap wafer  706  may have thicknesses of 60 μm and 350 μm, respectively. 
         [0056]      FIGS. 8A-8C  show a process for making contacts on the via wafer  702  in accordance with another embodiment of the present invention. As depicted in  FIG. 8A , a dielectric film  804  may be deposited on the top surface of the via wafer  702 . The dielectric film may be a Plasma Enhanced Chemical Vapor Deposition (PECVD) film, Benzocyclobutene (BCB) film or any other suitable dielectric film. Then, as depicted in  FIG. 8B , the dielectric film  804  is patterned and etched by a suitable etching technique so that one or more contact openings  806  are formed in the areas isolated by vias  708 . Next, as depicted in  FIG. 8C , contacts  808  (or, equivalently, metal pads/traces) may be deposited and patterned by a suitable etching technique. For instance, a metal layer may be deposited and patterned by DRIE or RIE technique using a photoresist layer. The contacts  808  may be formed of under-bump metal so that the contacts  808  may be soldered to bumps  30  (in  FIG. 1B ). Since the bumps  30  are located on the edge of the ASCI wafer  20  to reduce stress on the electrodes of the ASIC wafer  20 , the contacts  808  corresponding to the bumps are also located on the edge of the via wafer  702 . The sensor unit  810  in  FIG. 8C  is one exemplary embodiment of the multi-DOF device  22 , where the sensor unit  810  is mounted on the ASIC wafer  20  by bumps  30 . 
         [0057]      FIG. 9  shows a schematic diagram of a sensor unit  900 , where a multi-DOF device layer (or, equivalently, a MEMS layer)  906  is directly bonded to an ASIC wafer  902  in accordance with another embodiment of the present invention. As depicted, the device layer  906 , which includes MEMS structures, is bonded to the ASIC wafer  902  by a wafer bond  904 , where the wafer bond  904  is a low temperature bond, such as metal bond, and may have a ring shape. The metal used for the bond  904  may be reused to form sensor and driver electrodes of the ASIC wafer  902 . To enable grounding of the device layer  906 , the bond  904  is electrically conductive and able to stand the thermal compression during operation. The ASIC wafer  902  may include integrated electronics and multi-layer metallization to reduce shunt capacitance. To enable a hermetic encapsulation, the bond  904  is located over the regions of the ASIC wafer  902  where there is no transistor. 
         [0058]    The device layer  906  is fusion-bonded to a via/cap wafer  908 . The anchor  910  of the via wafer is also fusion-bonded to the device layer  906  and electrically connected to the device layer  906 , where the anchor  910  is electrically isolated by trenches (or vias)  912 . Each via  912  includes a core  916  formed of a non-monocrystalline conducting material and electrically insulated by a dielectric layer  914 . 
         [0059]    The ASIC wafer  902  includes planarized poly-insulator electrodes for driving and sensing MEMS structures formed in the device layer  906 . The ASIC wafer  902  also includes diffused hermetic underpasses under the bond  904  to handle high level signals. 
         [0060]      FIG. 10  shows the via/cap wafer  908  of  FIG. 9 , where the via wafer  908  is fabricated by processing a flat DSP wafer via the steps described in conjunction with  FIGS. 2D-2J , with the difference that the via wafer  908  may not include any marker mask  210  ( FIG. 2C ). As such, the process for fabricating the via wafer  908  is not repeated for brevity. 
         [0061]      FIGS. 11A-11B  show a process for fabricating the device layer  906  of  FIG. 9  in accordance with another embodiment of the present invention. As depicted in  FIG. 11A , a standard silicon wafer  1102  is fusion bonded (such as silicon-silicon fusion bond) to the via wafer  908 . Then, the silicon wafer  1102  may be ground to the thickness of 60 μm and polished by CMP technique. It is noted that a silicon-on-insulator (SOI) vendor could supply a wafer  1102  that is processes to this stage. Then, a bond metal layer  1106  may be deposited and patterned on the wafer  1102 . Note that the bond metal layer  1106  is needed if the bond  904  between the ASIC wafer  902  (shown in  FIG. 9 ) and the device layer  906  (shown in  FIG. 9 ) requires metal layers on both sides of the bond. 
         [0062]    The silicon wafer  1102  may be patterned and etched to form MEMS structures, as shown in  FIG. 11B . The steps for processing the components  1102  and  1106  in  FIGS. 11A-11B  are similar to those in  FIGS. 3A-3B . As such, detailed description of the process in  FIGS. 11A-11B  is not repeated for brevity. 
         [0063]      FIG. 12  shows a sensor unit  1200  that includes an ASIC wafer  1201  that is metal bonded to the device layer  1102 . The metal bond  1202  is similar to the metal bond  502  in  FIG. 5 . As such, detailed description of the bond  1202  is not repeated for brevity. 
         [0064]      FIGS. 13A-13D  show the steps to process the via wafer  908  of  FIG. 12  and to make contacts on the via wafer in accordance with another embodiment of the present invention. As depicted in  FIG. 13A , the via wafer  1300  is fabricated by grinding the top side (or, equivalently, the via side) of the via wafer  908  (shown in  FIG. 12 ) to the thickness of 350 μm and polishing the top surface. The base oxide layer  1301  of the vias  1303  may be also polished since the conductors  1302  of the vias that may be exposed during the grinding process may be covered again by a dielectric layer  1304 , as shown in  FIG. 13B . The cores (or, conductors)  1302  of vias  1303  are preferably formed of polysilicon, which is a conducting material. 
         [0065]    As depicted in  FIG. 13B , a dielectric film  1304  may be deposited on the top surface of the via wafer  1300 . The dielectric film may be a Plasma Enhanced Chemical Vapor Deposition (PECVD) film, Benzocyclobutene (BCB) film, or any other suitable dielectric film. Then, as depicted in  FIG. 13C , the dielectric film  1304  is patterned and etched by a suitable etching technique so that one or more contact openings  1306  are formed in the areas isolated by vias  1303 . Next, as depicted in  FIG. 13D , contacts  1308  (or, equivalently, metal pads/traces) may be deposited and patterned by a suitable etching technique. For instance, a metal layer may be deposited and patterned by DRIE or RIE technique using a photoresist layer. If the contacts  1308  require ohmic contacts without doping or high temperature anneal, the wafer  1300  may be formed of low resistance silicon. 
         [0066]      FIG. 14  shows a schematic diagram of a multi-DOF sensor unit  1400  in accordance with another embodiment of the present invention. The sensor unit  1400  is obtained by etching down one side of the dielectric layer  1304 , the via wafer  1302 , and the device layer  1102  of  FIG. 13 , where the etching technique may be a conventional etching technique, such as DRIE or RIE using a photoresist layer. Upon etching, one or more bond pads  1402  of the ASIC wafer  1201  can be accessed for further connection thereto via a wire  1404 , for instance. The ASIC wafer  1201  may have a thickness of 410 μm, for instance. As an alternative, double wafer dicing may be used instead of etching down one side of the dielectric layer  1304 , the via wafer  1302 , and the device layer  1102  of  FIG. 13D . In this approach, it is required that all slurry be removed from traces  1308  and bond pads  1402  after dicing. It is noted that the MEMS structures of the device layer  1102  is hermetically sealed by bonding the device layer  1102  to the via wafer  1302  and the ASIC wafer  1201 . 
         [0067]      FIG. 15  shows a schematic diagram of a sensor unit  1500  in accordance with another embodiment of the present invention. As depicted, the sensor unit  1500  may include a cap wafer  1502 ; a device layer  1504  secured to the cap wafer  1502  by a fusion bond  1503 ; a via wafer  1508  secured to the device layer  1504  by a metal bond  1506 ; and an ASCI wafer  1512  secured to the via wafer  1508  by a metal bond  1510  or connected to the via wafer  1508  by bumps. The structure and functions of each component of the unit  1500  are similar to those of its counterpart of the multi-DOF sensor units  22  (shown in  FIG. 1C) and 900  (shown in  FIG. 9 ). As such, the description of the components is not repeated for brevity. 
         [0068]      FIG. 16  shows a schematic diagram of a sensor unit  1600  in accordance with another embodiment of the present invention. As depicted, the sensor unit  1600  may include a first cap wafer  1602 ; a device layer  1604  secured to the first cap wafer  1602  by a fusion bond  1603 ; a second cap wafer  1608  secured to the device layer  1604  by a metal bond  1606 ; and an ASIC wafer  1612  secured to the second cap wafer  1608  by a die attaching material  1610 . The second cap wafer  1608  may include one or more lateral vias  1616  that may be connected to pads  1614  of the ASIC wafer  1612  by a wire  1618 . The structure and functions of each component of the unit  1600  are similar to those of its counterpart of the sensor units  22  (shown in  FIGS. 1C) and 900  (shown in  FIG. 9 ). As such, the description of the components is not repeated for brevity. 
         [0069]      FIG. 17A-17F  show a process for fabricating a via wafer in accordance with another embodiment of the present invention. As depicted in  FIG. 17A , the process starts with a flat wafer  1700  having a predetermined bulk thickness, preferably 700 μm. The wafer  1700  includes a first silicon layer  1704 ; a buried oxide layer  1706 ; a second silicon layer  1708 ; and two protective oxide layers (or, equivalently, silicon dioxide layers)  1702 ,  1709  deposited on the top and bottom surfaces of the wafer. The first silicon layer (or, active layer)  1704  may have a thickness of 100-150 μm and its surface may have an arithmetical mean roughness (Ra) of 20 angstroms or less. The first silicon layer  1704  may include P-type dopant silicon, and its resistivity is equal to or less than 0.02 ohm-cm. The bow and warp of the wafer  1700  is less than 50 μm, and the TTV of the wafer is less than 5 μm. 
         [0070]    The bottom oxide layer  1709  may be etched to form an etch marker masks  1712 , as depicted in  FIG. 17B . The process steps for making the masks  1712  are similar to those for making the etch marker mask  210  ( FIG. 2C ), with the difference that the mask  1712  is formed by etching both the bottom oxide layer  1709  and the second silicon layer  1708 . To etch the bottom oxide layer  1709 , the conventional buffered-oxide-etch (BOE) technique may be used. Then, the second silicon layer  1708  may be etched by a suitable etching technique, such as DRIE using a patterned photoresist layer, to form the mask  1712 . 
         [0071]    It is noted that the bottom oxide layer  1709  should be thick enough to stress balance the internal oxide. The stress caused in the via wafer  1700  during the process associated with  FIGS. 17B-17E  can cause the via wafer to bend and/or warp. The thickness of the oxide layer  1709  is set to maintain the bow and warp of the via wafer below 50 μm upon completion of the process. 
         [0072]    As depicted in  FIG. 17B , the entire portion of the top oxide layer  1702  may be removed by the BOE technique. Then, the first silicon layer  1704  may be etched by a suitable etching technique, such as DRIE using a patterned photoresist layer, to form the via openings  1710 , and the etching may be performed down to the buried oxide layer  1706 . The shape and dimensions of the via openings  1710  are similar to those of the via openings  212  (shown in  FIG. 2D ). 
         [0073]    Next, as depicted in  FIG. 17C , thermal oxide layers  1714 ,  1715  are grown on the top and bottom surfaces of the wafer. Subsequently, conformal polysilicon layers  1716  are deposited on the oxide layers  1714  and  1715 , as depicted in  FIG. 17D . The conformal polysilicon layer  1716  is similar to the silicon layer  214  shown in  FIG. 2E  and formed of a low stress polysilicon. Then, as depicted in  FIG. 17E , the polysilicon layer deposited on the bottom oxide layer is removed. As an alternative, some portion of the bottom oxide layer  1715  may be also removed to balance the stress. 
         [0074]    Portions of the polysilicon layer  1716  formed over the top oxide layer  1714  may be removed in the same manner as described in conjunction with  FIG. 2F . The wafer shown in  FIG. 17E  is similar to the wafer shown in  FIG. 2F , with the difference that the wafer shown in  FIG. 17E  includes a buried oxide layer  1706 . The wafer in  FIG. 17E  may be further processed into a wafer  1720  in  FIG. 17F  via the steps similar to those described in conjunction with  FIGS. 2G-2J . As such, the description of the steps for processing the wafer  1720  is not repeated for brevity. 
         [0075]      FIG. 18  shows a sensor assembly  1800  having a via wafer  1802  bonded to a device layer  1804  in accordance with another embodiment of the present invention. As depicted in  FIG. 18 , the via wafer  1802  may be made by bonding the via wafer  1720  in  FIG. 17F  to the device layer  1804  and removing the second silicon layer  1708  by a suitable etching technique. The assembly  1800  is similar to that shown in  FIG. 8A , and thus, may be further processed into a multi DOF device (or sensor device)  22  (shown in  FIG. 10 ) via the steps described in conjunction with  FIGS. 8B-8C . It is noted that the via wafer  1720  in  FIG. 17F  may be used, after removing the second silicon layer  1708 , in place of the top oxide layer  1304  and the via wafer  1300  in  FIG. 13B . 
         [0076]      FIG. 19  shows a schematic top view of a via wafer  1900  in accordance with yet further another embodiment of the present invention. As depicted, the via wafer  1900  includes multiple regions separated by isolating trenches (or, equivalently, vias). For example, the vias  1904 ,  1906 ,  1908 , and  1910  respectively form isolated regions (or islands)  1903 ,  1907 ,  1909 , and  1911 , where these islands are electrically isolated from the region  1902 . In another example, the vias  1916  and  1918  respectively form isolated islands  1922  and  1924 . It is noted that the vias may have other suitable polygonal shapes and each via has a closed loop to define an isolated island. 
         [0077]      FIG. 20  shows a schematic cross sectional view of the via wafer  1900  of  FIG. 19 , taken along the line  1900 - 1900 . For the purpose of illustration, only a portion  1920  of the via wafer is shown in  FIG. 20 . As depicted, each of the vias  1916  and  1918  includes a conducting core and a dielectric layer for electrically insulating the core. A dielectric layer  1940  may be deposited on the bottom surface of the via wafer  1900 . The island  1922  and  1924 , isolated by the vias  1916  and  1918 , may be electrically connected to other electrical components (not shown in  FIG. 20 ) via traces  1926  and  1928 , respectively. Likewise, the region  1902  may be electrically connected to other electrical component (not shown in  FIG. 20 ) via a trace  1930 . Also, the core of the via  1916  may be electrically connected to other electrical component via a trace  1932 . 
         [0078]      FIG. 21  shows a schematic top view of vias in accordance with still further another embodiment of the present invention. As depicted, the vias  2100  and  2102  form two isolated islands  2106  and  2108 , where the two islands are electrically isolated from the region  2104 . Each of the islands  2106  and  2108  may be electrically connected to other electrical component via a trace (not shown in  FIG. 21 ). For instance, the island  2106  surrounding the inner island  2108  has a ring shape and is connected to the ground, while the inner island  2108  may function as a sensor and communicate the measured signal to a signal processor. By grounding the outer island  2106 , the inner island  2108  and the outer island  2106  may form a coaxial connection, i.e., the vias  2100  and  2102  form a pair of coaxial vias. 
         [0079]    As the vias  2100  and  2102  have the same cross sectional shape as the via  1916 , detailed description of the vias  2100  and  2102  is not repeated. It is noted that the vias shown in  FIGS. 19-21  may be included in the via wafers depicted in  FIGS. 1A-18 . It is also noted that the vias shown in  FIGS. 19-21  can be fabricated by the processes in  FIGS. 2A-2J ,  10 , and  17 A- 17 F. 
         [0080]    It should be understood, of course, that the foregoing relates to exemplary embodiments of the invention and that modifications may be made without departing from the spirit and scope of the invention as set forth in the following claims.