Abstract:
A circuit for generating a cyclic prefix of a symbol comprised of a sequence of time samples, the prefix being the reproduction of the last samples of the symbol at the beginning of the symbol, the symbol being obtained by inverse Fourier transform of complex coefficients corresponding to respective frequencies. The circuit includes a multiplier that shifts the phase of each complex coefficient by a value proportional to its frequency, a memory for storing the samples at the beginning of the symbol, and a multiplexer that copies at the end of the symbol the stored samples.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]    This application is a continuation of U.S. patent application Ser. No. 09/491,685, filed Jan. 26, 2000, now pending, which application is incorporated herein by reference in its entirety. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to discrete multitone modulation (DMT), and more specifically, to the generation of cyclic prefixes in a DMT modulation transmission. The DMT modulation is for example used by standards ADSL and ADSL-lite.  
           [0004]    2. Discussion of the Related Art  
           [0005]    In a DMT modulation, data coded in the form of complex frequency coefficients are, on the transmit side, translated into time samples by inverse fast Fourier transform (IFFT).  
           [0006]    [0006]FIG. 1 illustrates the IFFT of a group of N complex coefficients A 1 .e j φ1 to A N .e j φN. Each coefficient A i .e j φi, where i is included between 1 and N, is associated with a respective frequency or tone f i . The transform of a coefficient A i .e i φi is a sequence of digital samples in the time field, forming a section of a sinusoidal carrier of frequency f i , of amplitude A i , and of phase φ i . A first curve shows a sinusoid section of amplitude A 1 , of period 1/f 1  and of phase φ 1 , obtained by IFFT of a coefficient A 1 .e j φ1 associated with a frequency f 1 . A second and a third curves show sections of sinusoids obtained by IFFT of coefficients A 2 .e j φ2 and A N .e j φN, respectively associated with frequencies f 2  and f N .  
           [0007]    An IFFT of the group of coefficients A i .e j φi is formed by the sum of the sections of sinusoidal carriers obtained by IFFT of each of coefficients A i .e j φi for i included between 1 and N, this sum being called a “symbol”. The IFFT of N coefficients provides a symbol D t  formed of a succession of N complex digital samples S 1  to S N . It should be noted that the shape of the symbol D t  shown is not realistic, but aims at simplifying the under-standing of the present description.  
           [0008]    The time samples obtained by IFFT are converted into analog to be transmitted, for example, by a telephone line. On the receive side, the analog signal of the line is converted into digital, and the resulting samples are converted into complex frequency coefficients by fast Fourier transform (FFT).  
           [0009]    To suppress a number of problems due to interference between symbols appearing upon transmission of the symbols, a “cyclic prefix” (or guard interval) is interposed before each symbol. The cyclic prefix is the reproduction at the beginning of a symbol of the last samples of this symbol.  
           [0010]    [0010]FIG. 2 shows a conventional circuit  10  of introduction of a cyclic prefix of τ samples. The complex coefficients A i .e j φi for iε[1, N] are provided to an IFFT circuit  12 . IFFT circuit  12  generates from the group of complex coefficients a symbol D t  comprised of N time samples S 1  to S N . Symbol D t  is provided to a memory of FIFO type  14  and to a first input of a multiplexer  16 . The output of memory  14  is connected to a second input of multiplexer  16 .  
           [0011]    At a time t 1 , IFFT circuit  12  provides a first sample S 1  of symbol D t , and memory  14  is controlled in the write mode to store this sample and the following. Multiplexer  16  is switched to select the output of memory  14 , which provides a sample of a preceding symbol. This configuration of circuit  10  remains unchanged until a time t N−τ .  
           [0012]    At time t N−τ , memory  14  has ended providing the samples of the preceding symbol and it contains the samples of the current symbol D t , to the last sample preceding the cyclic prefix. IFFT circuit  12  starts providing the prefix samples, which samples, designated as S I  to S N , continue being stored in memory  14 . Meanwhile, multiplexer  16  is switched so that it transmits these prefix samples S I  to S N . This configuration of circuit  10  remains unchanged until a time t N .  
           [0013]    At time t N+1 , IFFT circuit  12  is stopped, memory  14  contains the entire current symbol D t  and the prefix has just been transmitted. Multiplexer  16  is switched again to transmit the samples S 1  to S N  provided by memory  14 , that is, symbol D t .  
           [0014]    At a time t N+τ+1 , IFFT circuit  12  is reactivated and it starts providing the samples of the next sample. Time t N+τ+1  corresponds for the next symbol to previously-described time t 1 .  
           [0015]    This configuration of circuit  10  remains unchanged until a time 2t N  when symbol D t  will have been transmitted after its cyclic prefix.  
           [0016]    Time 2t N+ 1 corresponds for the next symbol to previously-described time t N−τ.    
           [0017]    A major disadvantage of circuit  10  is that the introduction of the cyclic prefix results in a delay t N  (of N samples) in the transmission of symbol D t . In some applications, such as telephone communications or other real time communications, the introduction of such a delay is not acceptable.  
           [0018]    Besides, in prior art circuit  10 , since the number N of samples may be high, memory  14  may have a large size.  
         SUMMARY OF THE INVENTION  
         [0019]    An object of the present invention is to provide a cyclic prefix generation circuit that introduces a particularly low transmission delay.  
           [0020]    Another object of the present invention is to provide such a circuit that uses a memory of reduced size.  
           [0021]    To achieve these objects, the present invention provides a circuit for generating a cyclic prefix of a symbol comprised of a sequence of time samples, said prefix being the reproduction of the last samples of the symbol at the beginning of the symbol, the symbol being obtained by inverse Fourier transform of complex coefficients corresponding to respective frequencies, including means for shifting the phase of each complex coefficient by a value proportional to its frequency, a memory for storing the samples of the beginning of the symbol, and means for copying at the end of the symbol the stored samples.  
           [0022]    According to an embodiment of the present invention, the means for shifting the phase of the complex coefficients include a multiplier connected to multiply each complex coefficient by a complex value having a unity norm and a phase proportional to the frequency associated with each coefficient.  
           [0023]    According to an embodiment of the present invention, the memory is of FIFO type.  
           [0024]    According to an embodiment of the present invention, the means for copying the stored samples include a multiplexer, a first input and a second input of which are respectively connected to the input and to the output of the memory.  
           [0025]    The present invention further aims at a method for generating a cyclic prefix of a time symbol, said prefix being the reproduction of the last samples of the symbol at the beginning of the symbol, the symbol being obtained by inverse Fourier transform of complex coefficients corresponding to respective frequencies, that includes the steps of shifting the phase of each complex coefficient by a value proportional to the frequency with which it is associated, storing the samples of the beginning of the symbol, and copying the stored samples at the end of the symbol.  
           [0026]    The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0027]    [0027]FIG. 1, previously described, illustrates an IFFT of a group of complex coefficients;  
         [0028]    [0028]FIG. 2, previously described, illustrates the generation of a cyclic prefix by means of a circuit according to prior art;  
         [0029]    [0029]FIG. 3 illustrates an IFFT of a group of complex coefficients according to the present invention; and  
         [0030]    [0030]FIG. 4 illustrates an embodiment of a cyclic prefix generation circuit according to the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0031]    The present invention provides circularly shifting the samples of a symbol to which a cyclic prefix is desired to be added, this so that the last samples forming the symbol before shifting are at the beginning of the symbol after shifting, and thus directly form the prefix. By transmitting the symbol thus shifted, the prefix is first transmitted, followed by a portion of the symbol which only needs be completed by the prefix to restore the symbol. Thus, a delay equal to the prefix only is introduced in the transmission and it is sufficient to only store the prefix to be able to retransmit it to complete the symbol.  
         [0032]    The circular shifting of the symbol must correspond to a same circular shifting of all the sinusoids that form the symbol. For this purpose, each complex frequency coefficient is multiplied by a complex factor causing a time shift, corresponding to the desired circular shift.  
         [0033]    [0033]FIG. 3 is intended for illustrating this procedure in further detail. It illustrates the IFFT of a group of N complex coefficients A 1 .e j φ1 to A N .e j φN multiplied according to the present invention by respective shifting coefficients e jK 1 τ  to e jK N τ . Multiplying a coefficient A i .e j φi by a complex coefficient e jΔφ  amounts to modifying the phase φ i  by a value Δφ. Phase shift Δφ causes a circular shifting of the corresponding sinusoid section by a value Δφ/2πf i , where f i  is the frequency of the sinusoid section. This shift is not constant, but is a function of frequency f i .  
         [0034]    According to the present invention, the N complex coefficients A 1 .e j φ1 to A N .e j φN are phase-shifted so that the corresponding sinusoid sections are all circularly shifted by a same value, or by the same number τ of samples. For this purpose, each coefficient A i .e j φi is multiplied by a coefficient e jK i τ , where K i  is 2πf i . Thus, symbol D t ′ formed of the sum of the sinusoid sections corresponding to coefficients A i .e j φi.e jK i τ , where i varies from 1 to N, corresponds to the preceding symbol D t  having undergone a circular shifting by τ samples.  
         [0035]    Coefficients e jK i τ  are predetermined, and they can for example be stored in a ROM.  
         [0036]    [0036]FIG. 4 shows an embodiment of a circuit  20  for generating a cyclic prefix according to the present invention. This circuit is similar to that of FIG. 2, and same references designate same elements. According to the present invention, complex coefficients A i .e j φi for iε[1, N] are provided to IFFT circuit  12  via a complex multiplier  22 , a second input of which correspondingly receives the above-mentioned N coefficients e jK iτ.  
         [0037]    As seen in relation with FIG. 3, symbol D t ′ provided by the IFFT circuit of FIG. 4 corresponds to symbol D t  of FIG. 2 having undergone a circular shifting by τ samples. Thus, samples S 1 ′ to S J ′ of the first τ times of symbol D t ′ are samples S I  to S N  of the last τ times of symbol D t . Samples S 1 ′ to S J ′ of symbol D t ′ form the cyclic prefix of symbol D t , and the following samples of symbol D t ′ form the T-τ first samples of symbol D t . To complete symbol D t , it is enough to copy samples S 1 ′ to S J ′ after symbol D t ′. To achieve this, samples S 1 ′ to S J ′ will have been stored in memory  24 , which memory must only store τ samples instead of N-τ.  
         [0038]    At a time t 1 , IFFT circuit  12  provides the first sample S 1 ′ of symbol D t ′, and memory  24  is controlled in the write mode to store the samples generated by the IFFT circuit. Multiplexer  16  is switched to select the output of IFFT circuit  12 . This configuration of circuit  10  remains unchanged until a time t τ ; it enables storing samples S 1 ′ to S J ′ in memory  24  and providing at the output of multiplexer  16  the cyclic prefix, formed by samples S 1 ′ to S J ′.  
         [0039]    At time t τ+1 , memory  24 , which has just stored samples S 1 ′ to S J ′, is deactivated. The position of multiplexer  16  is not modified, and this configuration of circuit  10  is maintained until a time t N . Multiplexer  16  provides in this interval samples S J+1 ′ to S N ′ of symbol D t ′, which correspond to previously described samples S 1  to S I .  
         [0040]    At time t N+1 , IFFT circuit  12  is stopped, memory  24  is controlled in the read mode to provide the first sample S 1  that i contains, and multiplexer  16  is switched to select the output of memory  24 . This configuration of circuit  10  remains unchanged until a time t N+τ . In this interval, multiplexer  16  successively provides samples S 1 ′ to S J ′ read from memory  24 , which correspond to above mentioned samples S I+1  to S N .  
         [0041]    At time t N+τ+1 , IFFT circuit  12  is reactivated to provide the samples of the next symbol and the cycle just described is resumed as at time t 1 .  
         [0042]    The present invention enables generating the cyclic prefix of a symbol by only delaying the symbol by duration τ of the prefix. This is a time gain of t N−τ  with respect to prior art, which is particularly valuable in the case of real time transmissions.  
         [0043]    Further, memory  24  used according to the present invention is of reduced size, since it is used to only store the samples forming the prefix.  
         [0044]    Of course, the present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.