Abstract:
A circuit is for generating a signal that indicates whether or not an input current exceeds a pre-established threshold current and, in the affirmative case, that is representative of the difference between the input current and the threshold current. The circuit includes a diode-connected transistor biased with a first constant current in a saturation functioning condition, a sense transistor mirrored to the diode-connected transistor and biased in a linear (triode) functioning condition, a load transistor connected in series to the sense transistor, biased with a second constant current and the control terminal of which is connected in common with the respective terminals of the diode-connected transistor and of the sense transistor. The input current to be compared is injected to a common current node of the load transistor and of the sense transistor, and the output voltage is available on the other current node of the load transistor.

Description:
FIELD OF THE INVENTION 
     This invention relates in general to electronic components, and in particular to power management integrated circuits in which it is helpful to determine whether or not a current flowing through a power switch exceeds a certain threshold and, in the affirmative case, to generate a signal representative of the difference between the current and the threshold. 
     BACKGROUND OF THE INVENTION 
     In many applications it is desirable to monitor the current flowing in an electronic component, and to compare it with a reference value to determine whether or not the electronic component is working in an overcurrent condition. 
     Most power management circuits such as AC-DC converters, DC-DC converters, battery management circuits, linear regulators and the like usually have internal overcurrent protection/detection circuits. Also motor driver circuits usually have internal overcurrent protection/detection circuits to prevent damage and/or malfunction. 
     Commonly, a voltage representative of the current flowing in an output electronic component or in a load (such as motors, batteries, converters load) is produced on a series sense resistor Rsense, as illustrated in  FIGS. 1 and 2 . Of course, the use of a resistor increases the power dissipation and decreases the overall system efficiency. Moreover, monitoring circuits for reading the voltage drop on the sense resistor need dedicated pins. 
     To reduce disadvantages, the architecture of  FIG. 3  is often used. The power transistor supplying the current to the load is coupled with a scaled replica thereof (SenseFet) connected in parallel to the power transistor. Therefore, the current through the sense transistor SenseFet is a scaled replica of the current flowing through the power transistor PowerFet. 
     The replica current Isense may be compared with a reference current I REF  to determine whether or not the power transistor is in an overcurrent condition. The circuit for comparing the replica current should not alter the bias condition of the transistor SenseFet with respect to that of the transistor PowerFet, otherwise the sensed replica current Isense may not be proportional to the current Ipower flowing through the Power Fet. 
     A typical way to ensure this is to use the architecture illustrated in  FIG. 4 , comprising a voltage comparator for comparing the voltage drop on a sense resistor in series to the SenseFet with a threshold V(I REF ). 
     With this architecture, the result of the comparison is affected by fluctuations of the sense resistor, fluctuations of the V(I REF ), comparator offset, and PowerFet-SenseFet mismatch. 
     Some of these variations can be compensated, for example, by obtaining the threshold V(I REF ) with a voltage drop on a resistor of the same type of the one used as current sense resistor, as shown in  FIG. 5 . However, the result of the comparison remains affected by sense resistor—reference resistor mismatch, comparator offset, and PowerFet-SenseFet mismatch. 
     SUMMARY OF THE INVENTION 
     A circuit has been devised for generating a signal that indicates whether or not an input current exceeds a pre-established threshold current and, in the affirmative case, that is representative of the difference between the input current and the threshold current. The circuit disclosed herein has a simple architecture, occupies a reduced silicon area, and its functioning is relatively insensitive to temperature variations and to fluctuations of the bias current. 
     The circuit comprises a diode-connected transistor biased with a first constant current in a saturation functioning condition, a sense transistor mirrored to the diode-connected transistor and biased in a linear (triode) functioning condition, a load transistor connected in series to the sense transistor, biased with a second constant current and the control terminal of which is connected in common with the respective terminals of the diode-connected transistor and of the sense transistor. The input current to be compared is injected to a common current node of the load transistor and of the sense transistor, and the output voltage is available on the other current node of the load transistor. 
     When the input current drops below a certain pre-established threshold, the output voltage drops abruptly to 0. When the input current surpasses the threshold, the variations of the output voltage represent the difference between the sensed input current and the pre-established threshold current. 
     The proposed circuit may be used for realizing a logic current comparator that flags when the threshold current is exceeded, or for generating an analog voltage representative of the variations of the sensed input current when the threshold is exceeded. 
     In some embodiments, this circuit is made from CMOS components. High Voltage and Low Voltage, High Side and Low Side, P-channel and N-channel Power FET topologies are disclosed herein. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  depicts a common DC-DC Converter/Battery Charger, according to the prior art. 
         FIG. 2  depicts a common DC Motor driver, according to the prior art. 
         FIG. 3  depicts a sense MOSFET SenseFet coupled to a power MOSFET, according to the prior art. 
         FIG. 4  depicts a common current comparator coupled to a sense MOSFET SenseFet, according to the prior art. 
         FIG. 5  depicts a common current comparator coupled to a sense MOSFET SenseFet with a reference resistor matched with the sense resistor, according to the prior art. 
         FIG. 6  depicts a basic architecture of the circuit of the present invention. 
         FIG. 7  illustrates the functioning of the circuit of the present invention in two different working conditions. 
         FIG. 8  depicts an embodiment of the proposed logic current comparator of the present invention. 
         FIG. 9  depicts two Low Voltage CMOS topologies of the comparator of  FIG. 8 . 
         FIG. 10  depicts a Mixed Signal Low Side topology of the comparator of  FIG. 8 . 
         FIG. 11  depicts a Mixed Signal N-type High Side Power MOS topology of the comparator of  FIG. 8 . 
         FIG. 12  depicts a Mixed Signal P-type High Side Power MOS topology of the comparator of  FIG. 8 . 
         FIG. 13  depicts a test circuit for simulating the functioning of the comparator of  FIG. 8 . 
         FIG. 14  shows simulation results for bias current fluctuations of ±10% and temperature variations of 30-80-120 Celsius degrees for the circuit of the present invention. 
         FIG. 15  shows simulation results for bias current fluctuations of ±20% and temperature variations of 30-80-120 Celsius degrees for the circuit of the present invention. 
         FIG. 16  shows simulation results for bias current fluctuations of ±5% and temperature variations of 30-80-120 Celsius degrees for the circuit of the present invention. 
         FIG. 17  shows the convolution between a square waveform and a Gaussian pulse for the circuit of the present invention. 
         FIG. 18  compares performance of the proposed circuit (upper) and the prior comparator (lower) of  FIG. 5  for bias current fluctuations of ±10%. 
         FIG. 19  compares performance of the circuit of the present invention and the prior comparator of  FIG. 5  for bias current fluctuations of ±5%. 
         FIG. 20  compares layouts of the logic comparator of the present invention and of the prior comparator of  FIG. 5 . 
         FIG. 21  depicts a basic architecture of the circuit of the present invention and the equivalent circuit for small signals. 
         FIG. 22  depicts a feedback loop for controlling the drive voltage of the PowerFet that includes the circuit of  FIG. 21 . 
         FIG. 23  is a detailed view of an exemplary architecture of the circuit of  FIG. 22 . 
         FIG. 24  is an equivalent circuit for small signals of the circuit of  FIG. 23 . 
         FIG. 25  is a graph of the current I POWER  flowing through the PowerFet in function of the load resistance Rload, according to the present invention. 
         FIG. 26  is a graph of the drive voltage V OUTPUT  of the transistor M A  in function of the load resistance Rload, according to the present invention. 
         FIG. 27  is a graph of the difference Vε between the drive voltage V OUTPUT  of the transistor M A  and the respective voltage corresponding to the threshold current I TH  in function of the load resistance Rload, according to the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     An exemplary embodiment of the circuit of the present invention is illustrated in  FIG. 6 . The transistor M 1  is biased in a saturation functioning mode, the transistor Msense operates in the so-called triode region (linear region) of its functioning characteristic, and the gate-source voltage Vgs 2  at which the transistor M 2  enters in a saturation functioning mode is a design parameter. The equations that describe the functioning of the transistors in the saturation region (Eq. 1a) and in the linear functioning region (Eq. 1b) are: 
                 Saturation                           I   =         1   2     ·   μ   ·   Cox   ·     W   L     ·       (     Vgs   -   Vt     )     2       ⁢           ⁢   or       ⁢     
     ⁢     I   =       1   2     ·   K   ·     W   L     ·       (     Vgs   -   Vt     )     2         ⁢     
     ⁢       where   ⁢           ⁢   K     =       μ   ·     Cox   .     
     ⁢   Linear       ⁢           ⁢   region       ⁢     
     ⁢     I   =       μ   ·   Cox   ·     W   L     ·   Vds   ·     [       (     Vgs   -   Vt     )     -       1   2     ·   Vds       ]       ⁢           ⁢   or       ⁢     
     ⁢     I   =     K   ·     W   L     ·   Vds   ·     [       (     Vgs   -   Vt     )     -       1   2     ·   Vds       ]                 (     1   ⁢           ⁢   a     )               
being K=μ·Cox. If Vds is much smaller than Vgs−Vt
 
                   I   ≈     K   ·     W   L     ·   Vds   ·     (     Vgs   -   Vt     )               (     1   ⁢           ⁢   b     )               
wherein:
         Vgs is the gate-source voltage;   Vds is the drain-source voltage;   Vt is the Volt-equivalent of temperature;   W/L is the aspect ratio of the transistor; and   K is a process parameter.       

     In the above equations, second order effects (channel length modulation effect and body effect) have been neglected. The transistor M 2  is biased such to enter the saturation region when the current Isense attains a desired threshold current I TH . The equations that describe the functioning of the circuit of  FIG. 6 , when the current Isense has attained the threshold current, are: 
                     I   ⁢           ⁢   1     =       1   2     ·   K   ·       (     W   L     )     1     ·       (       Vgs   ⁢           ⁢   1     -   Vt     )     2               (   2   )                 I   ⁢           ⁢   2     =         1   2     ·   K   ·       (     W   L     )     2     ·       (       Vgs   ⁢           ⁢   2     -   Vt     )     2       =       1   2     ·   K   ·   N   ·       (     W   L     )     1     ·       (       Vgs   ⁢           ⁢   2     -   Vt     )     2                 (   3   )               
having supposed that the aspect ratio of M 2  is N times larger than the aspect ratio of M 1 , i.e.
 
     
       
         
           
             
               
                 ( 
                 
                   W 
                   L 
                 
                 ) 
               
               2 
             
             = 
             
               N 
               · 
               
                 
                   ( 
                   
                     W 
                     L 
                   
                   ) 
                 
                 1 
               
             
           
         
       
       
         
           
             
               
                 and 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 Isense 
               
               + 
               
                 I 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 2 
               
             
             ≈ 
             
               K 
               · 
               
                 
                   ( 
                   
                     W 
                     L 
                   
                   ) 
                 
                 sense 
               
               · 
               
                 Vds 
                 sense 
               
               · 
               
                 ( 
                 
                   
                     Vgs 
                     sense 
                   
                   ⁢ 
                   
                       
                   
                   - 
                   Vt 
                 
                 ) 
               
             
           
         
       
     
     Supposing that Isense&gt;&gt;I 2  in the variation range of interest of Isense and considering that Vgs 1 =Vgs sense , 
     
       
         
           
             
               
                 
                   Isense 
                   ≈ 
                   
                     K 
                     · 
                     
                       
                         ( 
                         
                           W 
                           L 
                         
                         ) 
                       
                       sense 
                     
                     · 
                     
                       Vds 
                       sense 
                     
                     · 
                     
                       ( 
                       
                         
                           Vgs 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                         ⁢ 
                         
                             
                         
                         - 
                         Vt 
                       
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     The threshold current I TH =Isense is the current that solves equations (2), (3) and (4). Considering that the drain-source voltage Vds sense  of the transistor Msense is equal to Vgs 1 -Vgs 2 : 
                   {                   I   ⁢           ⁢   1     =       1   2     ·   K   ·       (     W   L     )     1     ·       (       Vgs   ⁢           ⁢   1     ⁢           -   Vt     )     2                     I   ⁢           ⁢   2     =       1   2     ·   K   ·   N   ·       (     W   L     )     1     ·       (       Vgs   ⁢           ⁢   2     ⁢           -   Vt     )     2                     I   TH     ≈     K   ·       (     W   L     )     sense     ·     (       Vgs   ⁢           ⁢   1     ⁢           -     Vgs   ⁢           ⁢   2       )     ·     (       Vgs   ⁢           ⁢   1     ⁢           -   Vt     )               ⁢     
     ⁢   Being   ⁢           ⁢   I   ⁢           ⁢   1     =       M   ·   I     ⁢           ⁢   2       ;         (     W   L     )     sense     =     P   ·       (     W   L     )     1                   (   5   )               
wherein M is the ratio between the bias currents I 1  and I 2  and P is the ratio between the aspect ratios of Msense and M 1 , the threshold current I TH  beyond which the comparator of this disclosure generates an active flag is:
 
     
       
         
           
             
               
                 
                   
                     I 
                     TH 
                   
                   ≈ 
                   
                     
                       2 
                       · 
                       I 
                     
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       1 
                       · 
                       P 
                       · 
                       
                         ( 
                         
                           1 
                           - 
                           
                             1 
                             
                               
                                 N 
                                 · 
                                 M 
                               
                             
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
     The above equation shows that the threshold current I TH  is a function of the bias current I 1  and of certain CMOS geometrical ratios (P, N, M), that can be accurately determined with modern fabrication technologies. The more accurately the bias current I 1  and the geometrical ratios P, N and M are determined, the more accurately the threshold current will be fixed. 
     In order to better understand the functioning of the proposed circuit when the sensed current Isense varies, reference is made to  FIG. 7  that depicts the circuit of  FIG. 6  in two different functioning conditions. When the current Isense being monitored is lower than the threshold current ( FIG. 7   a ), the transistor M 2  is working in its linear functioning region. Therefore, its drain-source voltage Vds 2  is small, its gate-source voltage Vgs 2  is almost equal to the gate-source voltage Vgs 1  of the transistor M 1 , and thus the drain-source voltage Vds of the transistor Msense is substantially null. Therefore, the voltage V OUTPUT  on the node OUTPUT, that is the sum of the drain-source voltages Vds 2  of the transistor M 2  and Vds sense  of the transistor Msense, respectively, may be relatively small. 
     When the current Isense being monitored attains the threshold current I TH , the drain-source voltage Vds sense  of the transistor Msense is comparable with the gate-source voltage Vgs 1  of the transistor M 1 , hence the gate-source voltage Vgs 2  of the transistor M 2  is small, the transistor M 2  enters a saturation functioning condition, its drain-source voltage Vds 2  is relevant and thus the voltage V OUTPUT  is relatively large. 
     If the current Isense being monitored tends to surpass the pre-established threshold current I TH , the drain-source voltage Vds sense  of the transistor Msense will tend toward the gate-source voltage Vgs 1  of the transistor M 1 , hence the gate-source voltage Vgs 2  of the transistor M 2  will tend to decrease. Since M 2  is in a saturation condition, even a small reduction of its gate-source voltage Vgs 2  causes a relatively large increase of its drain-source voltage Vds 2 . Therefore, the voltage V OUTPUT  on the node OUTPUT will tend to increase abruptly. 
     By resuming, if the voltage V OUTPUT  is small, it can be interpreted as a low logic value flagging that the sensed current is smaller than the threshold I TH . If the voltage V OUTPUT  is large, it can be interpreted as a high logic value flagging that the sensed current has attained or surpassed the threshold current I TH . In addition, if the sensed current Isense tends to exceed the threshold current I TH , the voltage V OUTPUT  tends to increase rapidly. Therefore, the difference Vε between the voltage V OUTPUT  and its value corresponding to the functioning condition in which the sensed current Isense equals the threshold current I TH , represents with good accuracy eventual variations of the sensed current Isense above the threshold I TH . 
     The transistor M SENSE  is in its linear functioning region, thus it is used as a resistor, though it may not be substituted with a resistor or a diode-connected transistor without degrading the performances of the circuit in term of precision by which the threshold current is fixed. If the MOSFET M SENSE  in  FIG. 6  was replaced by a resistor R SENSE , as depicted in the book “Smart Power ICs: Technologies and Applications”, Springer series in Advanced Microelectronics, by Bruno Murari, Franco Bertotti and Giovanni A. Vignola, the following formula for the threshold current would be obtained: 
     
       
         
           
             
               
                 
                   
                     I 
                     TH 
                   
                   ≈ 
                   
                     
                       1 
                       
                         R 
                         SENSE 
                       
                     
                     · 
                     
                       
                         
                           2 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           
                             I 
                             1 
                           
                         
                         
                           
                             μ 
                             n 
                           
                           ⁢ 
                           
                             
                               
                                 C 
                                 OX 
                               
                               ⁡ 
                               
                                 ( 
                                 
                                   W 
                                   L 
                                 
                                 ) 
                               
                             
                             1 
                           
                         
                       
                     
                     · 
                     
                       ( 
                       
                         1 
                         - 
                         
                           1 
                           
                             
                               N 
                               · 
                               M 
                             
                           
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
     By comparing the above formula with equation (6), it can be immediately inferred that, using a resistor R SENSE  in place of the transistor M SENSE , the spread of the threshold current I TH  would depend upon the process spread of the parameter μ N C OX (W/L) 1  and of the resistance R SENSE . For this reason, the spread of the threshold current I TH  of the proposed circuit is outstandingly smaller than that obtainable using a resistor R SENSE . 
     It may also not be possible to use a diode-connected transistor in place of the transistor Msense, because diode-connected transistors work in saturation region and thus the voltage drop thereon is relatively large. 
     By contrast, with the proposed architecture depicted in  FIG. 6 , the transistor Msense is kept in its linear functioning region, thus its drain-source voltage is negligible, and the threshold current I TH  depends on geometrical parameters of the MOSFETs and on the bias current I 1 , that can be very accurately determined. 
     The proposed circuit may be provided with a logic comparator O VERCURRENT  D ETECTION , as shown in  FIG. 8 , for generating a flag for signaling the detection of an overcurrent condition. In practice, the logic comparator compares the voltage V OUTPUT  with its value corresponding to the condition Isense=I TH  and generates an active flag when the threshold I TH  is attained or surpassed. 
     The circuit of  FIG. 8  is a logic current comparator that allows a significant reduction of silicon area consumption, compared to the commonly used circuits composed of matched sense resistors and a voltage comparator. The saved silicon area is even larger than the known architecture in which the sense comparator is referred to a high voltage rail when used in High Side topologies. 
     Two topologies of the proposed logic current comparator, for a low voltage CMOS fabrication process, connected to a scaled replica S ENSE F ET  of the power transistor P OWER F ET , the current flowing therethrough is to be monitored, are depicted in  FIG. 9 . 
     In mixed signal technologies, the low side device is usually a N-type component, as exemplified in  FIG. 10 . In this case the topology of the logic current comparator can be the same as discussed above for a CMOS technology. 
     When a high side power switch POWER FET is needed in a mixed signal technology, it may be either an N-type or a P-type component and in this case the topology of the proposed logic current comparator is relatively more complex than as depicted in the exemplary embodiments of  FIGS. 11 and 12 . Test simulations carried out by the applicant showed that the precision of the proposed circuit depends mainly on the precision with which the bias current I 1  is determined. 
     The simulated circuit is depicted in  FIG. 13 . The mixed signal high side power MOS topologies of  FIGS. 11 and 12  can be easily recognized. The circled MOS components of the simulation circuit of  FIG. 13  are the M 1 -M 2 -Msense components of the topologies of  FIGS. 11 and 12 . The simulations were of a MonteCarlo type, with 200 runs for each temperature value (30-80-120 Celsius degrees). The abscissa is the current Isense. The low voltage supply V 4  on the line Va 3 , and the supply V 9  referred to the high voltage rail, both have a uniform distribution in a range from 3.15V to 3.45V. The dependence of the voltage VBULK on the threshold current is negligible. 
       FIG. 14  depicts simulation results with a bias current uniformly distributed in a ±10% range. For all the temperatures, the distribution of the threshold current remains substantially uniform within a variation range of about ±10% (26.3 mA±2.63 mA). 
       FIG. 15  depicts simulation results with a bias current uniformly distributed in a ±20% range. Even in this case, for the temperatures the distribution of the threshold current remains substantially uniform, within a variation range of about ±20% (26.3 mA±5.3 mA). 
       FIG. 16  depicts the simulation results with a bias current uniformly distributed in a ±5% variation range. It can be observed that in this case the distribution of the current threshold has a Gaussian-like shape. This could be explained considering that a 5% uniform distribution function has substantially the same width of the typical Gaussian distribution function of the parameters of the matching CMOS components. As schematically shown in  FIG. 17 , the distribution of the current threshold is approximately the convolution of the uniform distribution of the bias current and of the Gaussian distribution of the parameters of the matching CMOS components. Since in this case the two distributions have substantially the same width, the distribution of the current threshold has a Gaussian-like shape. 
       FIG. 18  compares the functioning of a) the logic current comparator of this invention with b) the commonly known comparator of  FIG. 5 , for fluctuations of ±10% of the bias current. The simulation shows how the Gaussian distribution spread of the matching CMOS components in the proposed logic comparator negligibly influences the precision with which the threshold I TH  is determined. The known comparator of  FIG. 5  has a larger number of basic components than the current comparator of this disclosure and its precision is more coarse. 
     This fact may be even better inferred from the simulations of  FIG. 19 , in which a bias current distributed in a ±5% range has been used. In this case, the Gaussian distribution of the matching CMOS components makes the proposed architecture more refined than the prior comparator of  FIG. 5 . 
     An exemplary layout of the proposed logic comparator and a layout of the comparator of  FIG. 5  are depicted in  FIGS. 20   a  and  20   b , respectively. The silicon area saving of proposed solution is evident, even if in the layout of  FIG. 20   a  the allocation of the used electronic components was not optimized and the so-called well pockets generation was not minimized. 
     As stated hereinbefore, the proposed circuit of  FIG. 6  may be used for monitoring the value of the sensed current Isense when it exceeds the threshold current I TH . In order to illustrate the functioning of the circuit in such a working condition, reference is made to  FIGS. 21   a  and  21   b , that depict the proposed circuit and its equivalent circuit for small signals, respectively. 
     Rout is the equivalent resistance “seen” from the node OUTPUT and the ground node, and the difference Vε between the present voltage V OUTPUT  and its value corresponding to the functioning condition in which the sensed current Isense equals the threshold current I TH , is given by the following equation:
 
 V ε=( i   SENSE   −I   TH )· R out
 
     The difference Vε may be used as an error signal in a feedback control loop, a basic architecture of which is depicted in  FIG. 22 , for controlling the drive voltage of the PowerFet. The voltage Vε is amplified by an amplifier A, that adjusts the voltage generated by a driver stage GATE DRIVER of the PowerFet. 
     A preferred embodiment of a feedback control loop is depicted in  FIG. 23 . The amplifier is a common source stage composed of a transistor M A  that is off when the voltage V OUTPUT  corresponds to a current Isense smaller than the threshold I TH , and that operates in a saturation condition when Isense attains or exceeds the threshold I TH . The current generator I 3  biases the transistor M 4  in a saturation condition as soon as the voltage V OUTPUT  corresponds to the value for which Isense=I TH . 
     The resistor R is preferably determined such to make the voltage drop I 3 *(R+R DL ), being R DL  the resistance of the switch M DL , smaller than the threshold voltage of the PowerFet, otherwise the PowerFet would be kept on. The capacitor Cc is not essential, though it is preferably used for making more stable the feedback loop. 
     An exemplary drive stage of the PowerFet may be the depicted half-bridge stage, the output terminal of which is coupled to the gate of the PowerFet through a bias resistor R. 
     The equivalent circuit for small signals of the feedback control loop of  FIG. 23  is depicted in  FIG. 24 , wherein R D  is the resistance of the upper or the lower switch M DH , M DL  of the half bridge stage, g msense  and g mA  are the transconductance of the SenseFet and of the transistor M A , respectively. The loop gain G LOOP  is:
 
 G   LOOP   =g   mA ·( r   oA ∥( R   DH   +R ))· g   msense   ·R   OUT  
 
     The functioning of the circuit of  FIG. 23  has been simulated for various values of the load Rload using typical test values for the fabrication parameters of the components of the circuit. The exemplary graphs of  FIGS. 25 to 27  have been obtained. In the graph of  FIG. 26  the vertical line represents the value of the load Rload for which the sensed current Isense attains the threshold I TH . For larger load resistances the sensed current Isense is smaller than the threshold I TH , for smaller load resistances the sensed current is larger than the threshold I TH . 
     The above-mentioned figures demonstrate that the voltage V OUTPUT  rises abruptly when the sensed current Isense becomes greater than the threshold I TH , and remains substantially constant even if the resistive load further decreases after the current Isense has attained the threshold I TH . The variations of the voltage V OUTPUT  for small values of the load resistance are due to the fact that the loop gain is not infinite. 
     Even if the depicted exemplary circuits use only MOS transistors, the same circuit architectures may be realized also with BJTs. 
     Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is understood that the invention is not to be limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included within the scope of the appended claims.