Abstract:
A receiving system for a multimedia data transmitted via an interface is disclosed. The receiving system includes a processor, a non-volatile storage device, and a receiver. The processor is utilized for configuring the receiving system. The non-volatile storage device, being coupled to the processor, is utilized for storing content protection keys and system information or video processing information. The receiver, being coupled to the non-volatile storage device, receives the content protection keys from the non-volatile storage device and performs a decryption operation upon the multimedia data according to the content protection keys.

Description:
BACKGROUND 
       [0001]    The present invention relates to a receiving system for multimedia data transmitted via an interface, and more particularly, to a receiving system for multimedia data transmitted via a High-Definition Multimedia Interface (HDMI). 
         [0002]    Recently, HDMI has become increasingly important in modern video display systems. It is used for transmitting digital visual/audio signals from DVD players, set-up boxes, and other visual/audio sources to television sets, projectors and other video display systems. Besides carrying visual/audio data, HDMI also has a built-in content protection technology, called High-bandwidth Digital Content Protection (HDCP), for encrypting visual/audio data. In order to decrypt protected visual/audio data transmitted from an HDMI transmitter, an HDMI receiver has to get High-bandwidth Digital Content Protection (HDCP) keys during an HDCP decryption operation, where the HDCP keys are usually pre-programmed in a programmable non-volatile memory (for example, an electrically erasable programmable read only memory (EEPROM)) disposed outside the HDMI receiver.  FIG. 1  is a simplified diagram of an example of a conventional receiving system  100 . The conventional receiving system  100  comprises an HDMI receiver  105 , a video processor  110 , a processor  115 , a memory  120  (e.g. a flash memory) and a programmable non-volatile memory  125  (e.g. an EEPROM). The HDMI receiver  105  receives multimedia data via Transition-Minimized Differential Signaling (TMDS) channels, performs the HDCP decryption operation by retrieving the HDCP keys from the programmable non-volatile memory  1   25 , and transmits decrypted multimedia data to the video processor  110 . The video processor  110  then performs video processing. The processor  115  retrieves information (e.g. system instructions and system data) from the memory  120  to configure the receiving system  100  when the receiving system  100  is powered on. Therefore, the receiving system  100  stores the HDCP keys and information referred by the processor  115  in memories  125  and  120  respectively, which requires large circuitry and complicated architecture. Even if the processor is embedded in the video processor, the programmable non-volatile memory is embedded in the HDMI receiver, or the video processor and HDMI receiver are integrated in a single chip, the cost of individually allocated memories  120 ,  125  cannot be reduced efficiently. 
       SUMMARY 
       [0003]    Receiving systems and related methods for multimedia data transmitted via an HDMI interface are therefore disclosed, wherein the HDCP keys and information referred by the processor are stored in a common storage device. 
         [0004]    In some embodiments, a receiving system comprises a processor for configuring the receiving system, a non-volatile storage device for storing content protection keys and information referred to by the processor, for example, the system codes for configuring the receiving system, and a receiver for receiving the content protection keys outputted from the non-volatile storage device and performing a decryption operation upon the multimedia data according to the content protection keys. The non-volatile storage device can be any existed memory in the system for storing system codes or video processing data 
         [0005]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]      FIG. 1  is a simplified diagram of a related art receiving system. 
           [0007]      FIG. 2  is a diagram of a receiving system according to a first embodiment of the present invention. 
           [0008]      FIG. 3  is a diagram of a receiving system according to a second embodiment of the present invention. 
           [0009]      FIG. 4  is a diagram of a receiving system according to a third embodiment of the present invention. 
           [0010]      FIG. 5  is a diagram of a receiving system according to a fifth embodiment of the present invention. 
           [0011]      FIG. 6  is a diagram of a receiving system according to a sixth embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0012]    Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. 
         [0013]      FIG. 2  is a diagram of a receiving system  200  according to a first embodiment of the present invention. The receiving system  200  comprises an HDMI receiver  205  capable of receiving incoming multimedia data via TMDS channels, a processor  215 , a non-volatile storage device  220  (e.g. a flash memory), and an HDMI key accessing apparatus  230 . The processor  215  may comprise a central processing unit (CPU), a micro-controller, or any computing unit. The HDMI key accessing apparatus  230  comprises a storage controller  235  (e.g. a flash controller), a buffer device  240 , and a multiplexer  245 . In this embodiment, the HDMI receiver  205  and the video processor are integrated in a single integrated circuit (i.e. a single chip)  250 . This one-chip-configuration is not meant to be taken as a limitation of the present invention. The HDMI key accessing apparatus  230  buffers the HDCP keys KEY HDCP  in the buffer device  240  read from the non-volatile storage device  220  via the storage controller  235 , and transmits the buffered HDCP keys KEY HDCP  to the HDMI receiver  205  in response to a request from the HDMI receiver  205 . The non-volatile storage device  220  stores the HDCP keys KEY HDCP , CPU instructions, and system information DATA S . The buffer device  240  may be implemented with a static random access memory (SRAM). After the system boots up, the processor  215  moves a copy of the HDCP keys KEY HDCP  from the non-volatile storage device  220  to the buffer device  240  via the storage controller  235  and multiplexer  245 . After the HDCP keys KEY HDCP  is copied to the buffer device  240 , the multiplexer  245  will be switched to connect the buffer device  240  and the HDMI receiver  205 . During the HDCP decryption operation, an HDCP decryption engine in the HDMI receiver  205  can access the HDCP keys KEY HDCP  from the on-chip buffer device  240 . 
         [0014]    In some embodiments, the HDMI receiver has the flexibility to acquire the HDCP keys from either the internal buffer device or external storage device (such as an EEPROM). For example, the HDMI receiver acquires the HDCP keys through an inter-integrated circuit (I 2 C) interface, where the external storage device is coupled to an I 2 C pin of the receiver system integrated circuit through an I 2 C bus, and the internal buffer device is couple to the HDMI receiver via an I 2 C slave port. 
         [0015]    Furthermore, in some other embodiments, the HDMI receiver  205  and the video processor are implemented in individual integrated circuits. The HDMI receiver  205  may retrieve the HDCP keys KEY HDCP  from the buffer device  240  via the multiplexer  245  and an I 2 C interface. Other transmission protocols such as serial protocol interface (SPI) and universal serial bus (USB) are also alternatives for the transmission between two ICs. 
         [0016]      FIG. 3  is a diagram of a receiving system  300  according to a second embodiment. The receiving system  300  comprises an HDMI receiver  305  capable of receiving incoming multimedia data via TMDS channels, a processor  315 , a non-volatile storage device  320  (e.g. a flash memory) storing an HDCP keys KEY HDCP  and system information DATAs referred to by the processor  315 , and an HDMI key accessing apparatus  330 . The HDMI key accessing apparatus  330  comprises a storage controller  335  (e.g. a flash controller), a direct memory access (DMA) controller  337 , a decryption engine  338 , a buffer device  340 , and a multiplexer  345 . Please note that, in this embodiment, the HDCP keys KEY HDCP  stored in the non-volatile storage device  320  are encrypted HDCP keys. The HDMI receiver  305 , processor  315 , HDMI key accessing apparatus  330 , and video processor are all integrated in a single integrated circuit  350 . However, encrypted keys or single IC are not meant to be taken as limitations of the present invention. 
         [0017]    As is well known by one skilled in the art, the DMA mode is activated to transfer data efficiently because no CPU intervention occurs. The processor  315  can be released to execute other operations. The DMA controller  337  obtains the encrypted HDCP keys from the non-volatile storage device  320  to the decryption engine  338  for decryption to generate decrypted HDCP keys. The decrypted HDCP keys will be buffered in the buffer device  340  and acquired by the HDMI receiver  305  for performing the decryption operation upon the multimedia data. In addition, the HDMI key accessing apparatus  330  can also be designed to buffer the HDCP keys KEY HDCP  read from the non-volatile storage device  320  automatically during a boot-up process of the receiving system  300 . 
         [0018]      FIG. 4  is a diagram of a receiving system  400  according to a third embodiment, the receiving system  400  comprises an HDMI receiver and video processor integrated circuit, a non-volatile storage device  420  (e.g. a flash memory) storing HDCP keys KEY HDCP  and system information DATA S , and a buffer device (e.g. a DRAM)  440 . The HDMI receiver and video processor IC comprises an HDMI receiver  405 , a processor  415 , a first storage controller  435  (e.g. a flash controller), and a second storage controller (e.g. a DRAM controller)  455 . The HDMI receiver  405  processor and the video processor are integrated in a single IC  450  in this embodiment, however, this circuitry architecture is not meant to be taken as a limitation of the present invention. Generally speaking, a video display system requires at least a DRAM to store video/audio processing data and CPU instructions. The buffer device  440  (i.e. a DRAM) can be used to buffer the HDCP keys copied from the non-volatile storage device  420  at boot time. The HDMI receiver  405  can access the HDCP keys KEY HDCP  from the buffer device  440  directly through the second storage controller  455 . In this embodiment, the buffer device  440  is not specified for buffering the HDCP keys KEY HDCP  only. For example, the buffer device  440  can be a video frame buffer storing video processing data accessed by the video processor. 
         [0019]      FIG. 5  shows another embodiment of implementing the HDMI receiver and video processor on different ICs, the receiving system  500  comprises an HDMI receiver  505 , a video processor  550 , and a non-volatile storage device  520  (e.g. a flash memory) storing both the HDCP keys KEY HDCP  and system information DATA S . In this embodiment, a buffer device (such as  240 ,  340 ,  440 ) may be eliminated since the HDMI receiver may access the HDCP keys from the non-volatile storage device  520  directly. The video processor  550  comprises a processor  515  and an HDMI key accessing apparatus  530 . The HDMI key accessing apparatus  530  comprises a storage controller  535 , a bus arbiter  555 , and a bus master  560 . The bus arbiter  555  selects either the processor  515  or the bus master  560  to get the bus authority to transmit/receive data or HDCP keys via a system bus  562  inside the video processor  550 . If the bus master  560  gets the bus authority, a copy of the HDCP keys KEY HDCP  stored in the non-volatile storage device  520  will be transmitted to the HDMI receiver  505  via the storage controller  535 , the system bus  562 , and an I 2 C bus  564 . An I 2 C slave port may be aided to transmit the HDCP keys between the HDMI receiver IC  505  and video processor IC  550 . If the processor  515  gets the bus authority, system instructions (i.e. the system information DATA S ) will be transmitted from the non-volatile storage device  520  to the processor  515  for processing. 
         [0020]      FIG. 6  is a diagram of a receiving system  600  according to a sixth embodiment, the receiving system  600  comprises a HDMI receiver  605  capable of receiving incoming multimedia data via TMDS channels, a processor  615 , a non-volatile storage device  620  (e.g. a system flash memory) storing HDCP keys KEY HDCP  and system information DATA S , and an HDMI key accessing apparatus  630 . The HDMI key accessing apparatus  630  comprises an arbiter  655 , and a multiplexer  665 . The HDMI receiver  605  or the processor  615  can access the non-volatile storage device  620  by issuing a request to the arbiter  655  to obtain authority. The arbiter  655  generates a selection signal to control the multiplexer  665  to arbitrate authority of accessing the non-volatile storage device  620  between the HDMI receiver  605  and the processor  615 , where the HDMI receiver  605  reads the HDCP keys KEY HDCP  from the non-volatile storage device  620  when obtaining authority, on the other hand, the processor  615  reads system information DATA S  (e.g. system instructions) from the non-volatile storage device  620  when obtaining authority. 
         [0021]    In the above embodiments, by storing the HDCP keys and information together in the non-volatile storage device, a dedicated storage device (such as an internal SRAM) can be saved and therefore the production cost of the receiving system will be greatly reduced. 
         [0022]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.