Abstract:
Provided is a self refresh oscillator which includes a plurality of inverters serially connected between an input terminal and an output terminal; a pull up driver for charging a first node in accordance with a level of the output terminal; a comparator for comparing a potential of the first node with a reference voltage and outputting the result to the input terminal; and a period adjusting unit for operating based on a level of the output terminal and adjusting an amount of current discharged into a ground of the first node in accordance with a temperature.

Description:
[0001]     This application relies for priority upon Korean Patent Application No. 2003-0083899 filed on Nov. 25, 2003, the contents of which are herein incorporated by reference in their entirety.  
       BACKGROUND  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a self refresh oscillator and, more particularly, to a self refresh oscillator that can reduce power consumption by varying a self refresh period in accordance with a temperature change.  
         [0004]     2. Discussion of Related Art  
         [0005]     In general, data stored in a DRAM cell are erased by a leakage current, so that the data in the cell are sensed and amplified, and then rewritten in the cell. This operation refers to refresh.  
         [0006]     There are three methods for performing the refresh operation, of which one is performed by inputting a row address from an external side, another (CBR refresh method) by inputting a control signal (i.e., CAS-Before-Ras (CBR) signal) for the refresh from the external side, and generating an address to be refreshed and then refreshing the address on an internal side, and the third, known as a hidden refresh method, by performing the CBR refresh in cooperation with normal operation.  
         [0007]     Recently, while an external control signal is applied to the device in a constant state and maintained without any changes, a CBR state is periodically made within the device to perform the refresh operation. This method is called “self refresh”.  
         [0008]     It is necessary to perform the refresh operation in the cell so as to prevent the data in the cell from being completely erased due to a leakage current generated in the cell. The leakage current is closely related to a temperature (i.e., whenever the temperature increases 10° C., the leakage current increases twice), and takes a major role in determining the refresh period.  
         [0009]     When the memory device is fabricated, the circuit thereof must be safely operated even in an extreme situation. For example, the time capable of maintaining the data in the cell is reduced to half for the temperature increase of 10° C. and to {fraction (1/32)} for the temperature increase of 50° C.  
         [0010]     For example, if the refresh operation should be performed at a constant period with safety even at a high temperature in regardless of the temperature change, which means that many and unnecessary refresh operations should be performed at a room temperature or at a relatively low temperature.  
         [0011]     In other words, for the safety of data in the case of having a constant refresh period in regardless of the temperature change, i.e., to have the memory device safely operate even at a high temperature, a lot of refresh operations are performed at a room temperature, which means that many and unnecessary powers be consumed even at a relatively low temperature.  
         [0012]      FIG. 1  shows a circuit diagram of a self refresh oscillator in accordance with the prior art.  
         [0013]      FIG. 1  shows the circuit for five self refresh oscillators in accordance with the prior art, and takes the form of a ring oscillator consisted of 5 staged inverters as a whole. Each inverter consists of a PMOS transistor connected to a VSS and an NMOS transistor connected to a VDD, and these transistors act as turn-on resistors for adjusting the period of the oscillator. The signal OSC_ON is one that controls turning on/off the oscillator, and the signals OSC and OSB are output signals.  
         [0014]     In this circuit, when the signal OSC_ON becomes high, the ring type oscillator starts to operate and output a pulse signal of a waveform having a constant period.  
         [0015]     The problem of the circuit is that the characteristic of the oscillator is constant in accordance with a temperature, so that the basic temperature characteristic of the DRAM cell is not significantly reflected.  
         [0016]      FIG. 2  shows a graph of the refresh characteristic in accordance with the temperature of the DRAM cell, and it can be seen that the refresh characteristic is good when the temperature is low and not good when high. Thus, the amount of consumed current needs to be decreased by increasing the refresh time at a low temperature. However, the pulse period generated in the ring oscillator at a low temperature is the same as that at a high temperature, so that the current for the refresh operation is more consumed at the low temperature in the prior art.  
         [0017]     Since the amount of current consumed for the refresh operation in the DRAM has a proportional relationship with how often the refresh operation is performed, the more the period for the refresh operation is lengthened, the less the amount of current consumed in the DRAM is decreased. However, if the refresh period is lengthened more than the effective value of the original refresh of the DRAM cell, data in the cell might be corrupted, so that it is important to set a proper refresh time and then determine a point where the data are not lost and the required current is small.  
         [0018]     The prior art has focused on the prevention of data loss and maintained the setting value even at a low temperature that had been used at a high temperature when the effective value was not good, so that it does not utilize the characteristic that the cell has a good effective value for the refresh at a relatively low temperature. In other words, the circuit diagram of the prior art cannot implement the method that the refresh period be shortened at a high temperature and relatively lengthened at a low temperature.  
         [0019]      FIG. 3  shows one of prior arts. The technology disclosed in  FIG. 3  uses three staged oscillators, which use subthreshold leak currents of PMOS transistor and NMOS transistor (T 1  and T 4 ) inserted between each of the stages.  
         [0020]      FIG. 4  shows a circuit diagram for another self refresh oscillator in accordance with the prior art, which models a DRAM cell and performs the refresh operation for the total cells when an electric potential of capacitors (VCP) modeling a leak current of the DRAM cell is lower than the reference voltage (VREF).  
         [0021]     As mentioned above, this prior art also has a problem that the characteristic of the oscillator is constant in accordance with the temperature, so that the basic temperature characteristic of the DRAM cell is not significantly reflected.  
       SUMMARY OF THE INVENTION  
       [0022]     Therefore, the present invention is directed to a self refresh oscillator having an increased refresh time at a low temperature than a high temperature to solve the above problems.  
         [0023]     The self refresh oscillator to solve the above mentioned purpose in accordance with the present invention includes, a plurality of inverters serially connected between an input terminal and an output terminal; a pull up driver for charging a first node in accordance with a level of the output terminal; a comparator for comparing a potential of the first node with a reference voltage and outputting the result to the input terminal; and a period adjusting unit for operating based on a level of the output terminal and adjusting an amount of discharged current to a ground of the first node in accordance with a temperature.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0024]     A more complete understanding of the present invention may be had by reference to the following description when taken in conjunction with the accompanying drawings in which:  
         [0025]      FIG. 1  shows a circuit diagram of a self refresh oscillator in accordance with the prior art;  
         [0026]      FIG. 2  shows a graph for explaining a temperature characteristic of  FIG. 1 ;  
         [0027]      FIG. 3  and  FIG. 4  show circuit diagrams of a self refresh oscillator in accordance with the prior art;  
         [0028]      FIG. 5  shows a circuit diagram of a self refresh oscillator in accordance with a first embodiment of the present invention;  
         [0029]      FIG. 6  shows a circuit diagram of a self refresh oscillator in accordance with a second embodiment of the present invention;  
         [0030]      FIG. 7  shows a circuit diagram of a self refresh oscillator in accordance with a third embodiment of the present invention;  
         [0031]      FIG. 8  shows a circuit diagram of a self refresh oscillator in accordance with a fourth embodiment of the present invention; and  
         [0032]     FIGS.  9  to  14  show graphs for explaining a characteristic of the self refresh oscillator in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0033]      FIG. 5  shows a circuit diagram of the self refresh oscillator in accordance with a first embodiment of the present invention.  
         [0034]     A comparator CMP 1  compares a given reference voltage Ref with a voltage of a node Node 1 . Inverters IV 1 , IV 2  and IV 3  transfer an output of the comparator CMP 1  to a PMOS transistor MP 1  and an NMOS transistor MN 3 . The PMOS transistor MP 1  is turned on in accordance with an output of the inverter IV 3  and acts as a switch for charging the node Node 1 , and the NMOS transistor MN 3  acts as a switch for discharging the voltage of the node Node 1  in accordance with the output of the inverter IV 3 . NMOS transistors MN 1  and MN 2  serially connected between the NMOS transistor MN 3  and the node Node 1  act as diodes. A capacitor C 1  temporarily stores the voltage of the node Node 1 .  
         [0035]     The reference voltage is set to an approximate value to the sum of threshold voltages Vt of the two NMOS transistors MN 1  and MN 2 . The output OUT becomes low at an initial state to turn on the PMOS transistor MP 1 , however if the NMOS transistor MN 3  is turned off, the capacitor C 1  is then charged to a level VDD. If the potential of the node Node 1  is higher than that of the reference voltage Ref when the electric potential charged in the capacitor C 1  is increased as shown in  FIG. 9 , the comparator CMP 1  outputs a low level and the output of the comparator CMP 1  is converted to a high level by the inverters IV 1  to IV 3 . From this moment, the voltage charged in the node Node 1  starts to be discharged through the NMOS transistors MN 1  to MN 3 .  
         [0036]     The discharge characteristic of the node Node 1  shows a fast discharge when the level of the node Node 1  is much higher than the sum of the threshold voltages Vt of the NMOS transistors MN 1  and MN 2 , however, the discharge is rapidly slowed when the level of the node Node 1  becomes closer to the sum of the threshold voltages Vt. When the level of the node Node 1  becomes lower than that of the predetermined reference voltage Ref, the output of the comparator CMP 1  changes its state from a low level to a high one. Since the output of the comparator CMP 1  is inverted to a low level by the inverters IV 1  to IV 3 , the capacitor is charged again with the voltage VDD.  
         [0037]     This operation is repeated to oscillate an output signal OUT, and the principle of the present invention is to make different a leaking time of the node Node 1  in accordance with a temperature change.  
         [0038]      FIG. 10  is a graph showing a relationship between a current and a temperature in the case that gates and drains of NMOS transistors such as the NMOS transistors MN 1  and MN 2  of  FIG. 5  are connected each other to act as diodes. When the temperature becomes low as shown in  FIG. 10 , the amount of current Ids becomes lower at a low Vgs compared to a case when the temperature is relatively high. This characteristic is the same as that a threshold voltage increases when the MOS transistors are turned on as the temperature becomes low.  
         [0039]     Therefore, in the present invention, the NMOS transistors are made to operate in a low Vgs region (i.e., a region close to the voltage Vt), so that many currents make the refresh period more shortened when the temperature is high, and a few currents makes it more lengthened when the temperature is low. In other words, when the reference voltage Ref level is set to make all of the NMOS transistors MN 1  and MN 2  operate at a level close to their threshold voltages, which act as leaking passages, as shown in  FIG. 9 , the temperature characteristics of the NMOS transistors MN 1  and MN 2  can be significantly seen. For its reference,  FIG. 9  shows levels of the reference voltage Ref and the node Node 1  at 25° C. and 85° C.  
         [0040]      FIG. 6  shows a circuit diagram of a self refresh oscillator in accordance with a second embodiment of the present invention.  
         [0041]      FIG. 6  differs from  FIG. 5  in that the inverter IV 2  of  FIG. 5  is replaced with a NAND gate ND 1  and the NAND gate ND 1  is made to invert a signal inputted in accordance with an oscillator enable signal OSC_On. In other words, when the oscillator enable signal OSC_On is low, an output OUT is fixed to a low level, so that the oscillation operation is stopped, however, when the oscillator enable signal OSC_On is high, a normal oscillation operation is performed.  
         [0042]      FIG. 7  shows a circuit diagram of a self refresh oscillator in accordance with a third embodiment of the present invention.  
         [0043]      FIG. 7  differs from  FIG. 6  in that capacitors C 2  and C 3  are inserted between the output of the comparator CMP 1  and the ground and between the output of the NAND gate ND 1  and the ground, respectively, so as to ensure a sufficient precharging time of the node Node 1 . In other words, the capacitors C 2  and C 3  for delay enable the level of the node Node 1  to be sufficiently increased to the VDD level by ensuring a sufficient turn on time for the PMOS transistor MP 1  when the voltage level of the node Node 1  is higher than that of the reference voltage Vref.  
         [0044]      FIG. 8  shows a circuit diagram of a self refresh oscillator in accordance with a fourth embodiment of the present invention.  
         [0045]      FIG. 8  is a modified example of  FIG. 6 . For simplicity of explanation, NMOS transistors MN 1  to MN 3  are referred to as a first period adjusting unit.  
         [0046]     In the fourth embodiment, the oscillation period can be adjusted with ease by connecting a plurality of period adjusting units to the first period adjusting unit in parallel.  
         [0047]     Sizes of the NMOS transistors of the first period adjusting unit are different from those of the NMOS transistors of the period adjusting units connected in parallel thereto. In other words, each size of the NMOS transistors of the period adjusting units is different from one another.  
         [0048]     In  FIG. 8 , the first period adjusting unit starts to operate when a control signal SEL 0  is high, and a period adjusting unit consisting of NMOS transistors MN 5  to MN 7  starts to operate when a control signal SEL 1  is high, and a period adjusting unit consisting of NMOS transistors MN 8  to MN 10  operates when a control signal SELn is high, thereby adjusting the oscillation period.  
         [0049]     FIGS.  11  to  14  show graphs for comparing and explaining characteristics of self refresh oscillators in accordance with the prior art and the present invention.  
         [0050]      FIG. 11  and  FIG. 12  show graphs for explaining a characteristic of an oscillator in accordance with the prior art, and the period of the oscillator output is 16 μs at 85° C. in  FIG. 11  and 17 μs at 25° C. in  FIG. 12 . This means that the output of the oscillator has almost no change in regardless of the temperature.  
         [0051]      FIG. 13  and  FIG. 14  show graphs for explaining a characteristic of an oscillator in accordance with the present invention, and the period of the oscillator output is 18 μs at 85° C. in  FIG. 13  and 75 μs at 25° C. in  FIG. 14 . Therefore, it can be seen that the output period of the oscillator becomes shortened when the temperature becomes higher, and vice versa.  
         [0052]     As mentioned above, when the effective value of the DRAM refresh increases, the current consumption can be reduced by properly adjusting the self refresh period to be lengthened in accordance with the present invention. In other words, the effective value of the refresh in the DRAM cell is significantly affected by the temperature, so that it is increased when the temperature becomes lower. However, by means of the circuit diagram of the present invention, the refresh period becomes lengthened when the temperature is lower, so that the consumed current can be reduced, and the circuit cannot be affected by the temperature at the same time.