Abstract:
A MOS-type solid-state imaging device is disclosed capable of high speed scanning. The imaging device includes a plurality of photodiodes arranged in a matrix form, a vertical scanning circuit, a horizontal scanning circuit, a first group of switching transistors and a second switching transistors. The imaging device enables multiple pixel signals to be simultaneously outputted without adversely effecting adjacent pixel signals during a scanning operations. A separating layer formed of an impurity layer held at a predetermined potential is embedded at least between two adjacent switching transistors, thereby separating the capacitive coupling between the two adjacent sets of switching transistors.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a MOS-type solid-state imaging device and, more particularly, to a solid-state imaging device for imaging a plurality of frames at high speeds. 
     A conventional MOS-type solid-state imaging device has a structure as shown in FIG. 3. This solid-state imaging device, formed by a semiconductor fabricating process, includes a light receiving region 1, a vertical scanning circuit 2 and a horizontal scanning circuit 3 for reading pixel signals. 
     The light receiving region 1 will be described first. A plurality of n +  -type impurity regions are embedded in matrix form in a p-type well layer arranged on a surface portion of an n-type semiconductor substrate forming a plurality of photodiodes P 11 , P 12 , . . . , P 21 , P 22 , . . . , P 31 , P 32 , . . . , as shown in FIG. 3. Signal read lines S 1 , S 2 , S 3 , S 4 , . . . and vertical scanning lines V 1 , V 2 , V 3 , . . . extend vertically and horizontally, respectively, between these photodiodes. The vertical scanning lines V 1 , V 2 , V 3 , . . . are connected to predetermined bit output contacts b 1 , b 2 , b 3 , . . . of the vertical scanning circuit 2 which is formed of shift registers. The signal read lines S 1 , S 2 , S 3 , S 4 , . . . are connected to an output terminal 4 through second switching transistors M 1  , M 2 , M 3 , M 4 , . . . . The gate contacts of the second switching transistors M 1 , M 2 , M 3 , M 4 , . . . are connected to predetermined bit output contacts h 1 , h 2 , h 3 , h 4  . . . of the horizontal scanning circuit 3, also formed of shift registers. 
     A first switching transistor is interposed between each photodiode and its corresponding signal read line, as exemplified by a switching transistor C 1  between the photodiode P 11  and the signal read line S 1 . The gate contacts of these first switching transistors are connected to the vertical scanning lines V 1 , V 2 , V 3 , . . . extending from the vertical scanning circuit 2. 
     To form an image with the MOS-type solid-state imaging device thus constructed, an image is read by scanning at timings as shown in FIG. 4. That is, after receiving an optical image within a predetermined exposure period, a high-level signal S V1  is applied from the first bit output contact b 1  of the vertical scanning circuit 2 for a predetermined period T, thereby turning on a group of switching transistors connected to the first vertical scanning line V 1 . Therefore, the pixel signals corresponding to the photodiodes P 11 , P 12 , . . . connected to the first vertical scanning line V 1  can be transmitted to the signal read lines S 1 , S 2 , S 3 , S 4 , . . . . In addition, within the same period T, a pulse signal S h  is applied from the lower to higher bits of the horizontal scanning circuit 3 at a predetermined period τ, causing the second switching transistors M 1 , M 2 , M 3 , M 4 , . . . to conduct sequentially s that the pixel signal of each of the photodiodes P 11 , P 12 , . . . will be outputted to the output terminal 4 as a periodic signal S(τ) every period τ. 
     Then, a high level signal S V2  is applied from the second bit output contact b: of the vertical scanning circuit 2 for the predetermined period T, thereby turning on a group of second switching transistors connected to the first vertical scanning line V 2 . Therefore, the pixel signals corresponding to the photodiodes P 21 , P 22 , . . . connected to the second vertical scanning line V 2  can be transmitted to the signal read lines S 1 , S 2 , S 3 , S 4 , . . . . In addition, within the same period T, the pulse signal S h  is applied from the lower to higher bits of the horizontal scanning circuit 3 at the predetermined period τ causing the second switching transistors M 1 , M 2 , M 3 , M 4 , . . . to conduct sequentially so that the pixel signal of each of the photodiodes P 21 , P 22 , . . . will be outputted to the output terminal 4 as the signal S(τ) every period τ. 
     By repeating the above-described vertical and horizontal scanning operations for the remaining photodiodes, pixel signals equivalent to a single frame are read as a signal S(τ). 
     The above MOS-type solid-state imaging device is adapted for reading pixel signals when a comparatively small number of pixels are scanned at a comparatively low speed. However, if a solid-state imaging device has a large number of pixels (photodiodes), and a large number of pixel signals must be read by the above vertical and horizontal scanning operations, then a very high speed horizontal scanning circuit is necessary, which is not technically feasible in the above imaging device. 
     To overcome this problem, the inventors of the present invention have researched and developed a solid-state imaging device that can horizontally scan simultaneously a set of plural pixels. This allows the solid-state imaging device to read an image at high speeds without requiring high speed horizontal scanning circuits. 
     A typical structure of such a solid-state imaging device will be described with reference to FIG. 5. In FIG. 5, reference numeral 2 designates a vertical scanning circuit consisting of shift registers, and reference number 3 designates a horizontal scanning circuit consisting of shift registers. Bit outputs b 1 , b 2 , . . . b n  of the vertical scanning circuit 2 are connected to vertical scanning lines V 1 , V 2 , . . . V n , respectively, while bit outputs h 1 , h 2 , . . . h m  of the horizontal scanning circuit 3 are connected to horizontal scanning lines l 1 , l 2 , . . . l m , respectively. 
     Further, a group of photodiodes, each of which forms a pixel, are connected, in a manner similar to that shown in FIG. 3, to predetermined signal read lines S 1 , S 2 , . . . S 16m , respectively, through switching transistors. The switching transistors conduct or do not conduct in accordance with the voltage of each of the vertical scanning lines V 1 , V 2 , . . . V n , while predetermined switching transistors M 11  -M 14 , M 21  -M 24 , . . . , M 4m1  -M 4m4  are connected to the terminals of the signal read lines S 1 , S 2 , . . . S 16m , respectively. 
     Here, as an example, the horizontal scanning line l 1  is commonly connected to the gate contacts of the switching transistors M 11  -M 14 . Each of the horizontal scanning lines l 1 , l 2 , . . . l m  has four switching transistors commonly connected thereto as a set through the gate contacts of the four switching transistors. First switching transistors of the respective sets of switching transistors (e.g., M 11 , M 21 , . . . ) are connected to a first output line 5; second switching transistors (e.g., M 12 , M 22 , . . . ) are connected to a second output line 6; third switching transistors (e.g., M 13 , M 23 , . . . ) are connected to a third output line 7; and fourth switching transistors (e.g., M 14 , M 24 , . . . ) are connected to a fourth output line 8; thereby outputting pixel signals S 1  (τ), S 2  (τ), S 3  (τ), and S 4  (τ) from the output lines 5, 6, 7, and 8 in parallel. 
     FIG. 6 shows a typical connection between the horizontal scanning line l 1  and the first set of switching transistors M 11  -M 14 , and the horizontal scanning line l 2  and the second set of switching transistors M 21  -M 24 . 
     The signal read lines S 1  -S 8  in the light receiving region is formed of a plurality of n +  -type impurity layers embedded in the p-type well layer, while the n +  -type impurity layers S 1  &#39;-S 8  &#39; are embedded while separated at a predetermined interval from the terminals of the read line forming the n +  -type impurity layers. The N-channel MOS-type switching transistors M 11  -M 14  are formed by laminating the horizontal scanning line l 1  (which is made of a polysilicon layer extending from the bit output contact h 1  of the horizontal scanning circuit 3) on an upper surface stretching between the n +  -type impurity layers S 1  -S 4  and S 1  &#39;-S 4  &#39;. The N-channel MOS-type switching transistors M 21  -M 24  are formed by laminating the horizontal scanning line l 2  (which is made of a polysilicon layer extending from the bit output h 2  of the horizontal scanning circuit 3) on the upper surface stretching between the n +  -type impurity layers S 5  -S 8  and S 5  &#39;-S 8  &#39;. 
     The n +  -type impurity layers S 1  &#39; and S 5  &#39; are connected to the first output line 5 through contacts (designated by   in the figure); the n +  -type impurity layers S 2  &#39; and S 6  &#39; are connected to the second output line 6 through contacts; the n +  -type impurity layers S 3  &#39; and S 7  &#39; are connected to the third output line 7 through contacts; and the n +  -type impurity layers S 4  &#39; and S 8  &#39; are connected to the fourth output line 8 through contacts. The output lines 5, 6, 7 and 8 are made of an aluminum layer. 
     Referring to FIG. 7, the solid-state imaging device having such a construction can read four pixel signals transmitted simultaneously as a set from the group of photodiodes to each signal read line. The four pixel signals are read in synchronism with the vertical scan timing of each signal S V1 , S V2 , S V3  . . . applied from the vertical scanning circuit 2 at a horizontal scanning period of the horizontal scanning circuit 3. Therefore, even if the horizontal scanning circuit 3 is not operated at high speeds, a substantially rapid scanning operation can still be achieved. Thus, this solid-state imaging devices can accommodate a large number of pixels. 
     Accordingly, the solid-state imaging device which horizontally scans a plurality of pixel signals simultaneously, as shown in FIG. 5, can read the pixel signals equivalent to each frame at high speeds, so that a plurality of frames can be formed into an image at high speeds. As an example, this device can be used to take the instantaneous motion of a rapidly changing object as a plurality of frames. 
     However, research and development has revealed that this device has the following problem that must be overcome. Specifically, when a horizontal scanning signal is applied sequentially from each bit output h 1 , h 2  . . . h m  of the horizontal scanning circuit 3 at a predetermined period τ during a horizontal scanning period so that four switching transistors grouped as a set corresponding to such bit output are caused to conduct and not to conduct sequentially for horizontal scanning, a voltage variation in the pixel signals of one set causes a voltage variation in the adjacent set due to inter-set capacitive coupling, thereby distorting the image. 
     This problem will be described in more detail with reference to FIG. 6. During a period in which the four pixel signals S 1  (τ), S 2  (τ), S 3  (τ), and S 4  (τ) are read in parallel by causing the first set of switching transistors M 11  -M 14  to conduct by a scanning signal from the first bit output h 1  of the horizontal scanning circuit 3, the second set of switching transistors M 21  -M 24  located adjacent thereto do not conduct. By causing the first set of switching transistors M 11  -M 14  not to conduct and the second set of switching transistors M 21  -M 24  to conduct, the four pixel signals S 1  (τ), S 2  (τ), S 3  (τ), and S 4  (τ) corresponding to the second set of switching transistors are read in parallel. In such a case, as the drain regions (n +  impurity regions) S 1  &#39;, S 2  &#39;, S 3  &#39;, and S 4  &#39; of the first set of switching transistors M 11  -M 14  are electrically initialized, their depletion layer capacitances are varied, thereby affecting the drain regions (n +   impurity regions) S 5  &#39;, S 6  &#39;, S 7  &#39;, and S 8  &#39; of the second set of switching transistors M 21  -M 24  which is adjacently located. Thus, this variation in the depletion layer capacitance acts as a voltage variation when the second set of pixel signals is read. 
     The same phenomenon is observed every time other sets of pixel signals are scanned at the predetermined period τ, thereby contaminating the image with noise. 
     Particularly, the pixel signals S 3  (τ) and S 4  (τ) passing through the switching transistors M 14  and M 21  (FIG. 6), which are most closely adjacent to each other among two adjacent sets of switching transistors, are most strongly affected, and as a result, vertically striped video noise is present in the reproduced image. 
     Further, such vertically striped video noise tends to increase with increasing the number of output lines to obtain rapid horizontal scanning and increasing the number of switching transistors within a set resulting from such increase in output lines. 
     That is, if the number of switching transistors in each set is increased, so is the number of switching transistors conducting and not conducting simultaneously every period τ, and as a result, the capacitive coupling between any two adjacent sets is likewise increased. Thus, the negative influence brought about on the image quality by the capacitive variation is aggravated. 
     SUMMARY OF THE INVENTION 
     The present invention has been made in view of such circumstances. Accordingly, an object of the present invention is to provide a MOS-type solid-state imaging device capable not only of eliminating the mutual influence between pixel signals during scanning, but also of achieving high speed scanning. 
     The invention is applied to a solid-state imaging device comprising: a plurality of photodiodes arrayed in matrix form in a light receiving region; a group of vertical scanning lines disposed in correspondence with each row of the photodiodes; a vertical scanning circuit for applying a vertical scanning signal to each vertical scanning line at a predetermined period; a group of signal read lines disposed in correspondence with each column of the photodiodes; a first group of switching transistors for transmitting pixel signals of the photodiodes to the group of signal read lines respectively by the vertical scanning signal; and a second group of switching transistors, disposed at a terminal of each signal read line, for transmitting pixel signals to an output line by causing the second group of switching transistors to sequentially conduct and not conduct in synchronism with a horizontal scanning signal applied from a horizontal scanning circuit at a predetermined period thereby to perform a horizontal scanning operation. Such a solid-state imaging device has a plurality of output lines, and each of the second group of switching transistors are connected to each of the plurality of output lines in correspondence with the order of arraying the output lines. In addition, the second group of switching transistors are divided into sets of plural switching transistors, which are made to correspond with the outputs of the horizontal scanning circuit in a one to one relationship, thereby causing the plural switching transistors within a set to be operated simultaneously by a horizontal scanning signal corresponding to that set so that a horizontal scanning operation is performed by the set of pixel signals. 
     Further, to achieve the object of the invention with the above solid-state imaging device, a separating layer formed of an impurity layer, which is held at a predetermined potential, is embedded at least between two adjacent switching transistors, each of which belonging to each of two adjacent sets of second switching transistors, thereby separating the capacitive coupling between the two adjacent sets of second switching transistors. 
     The separating layer may be provided every two adjacent second switching transistors irrespective of their being between two adjacent sets. 
     According to the solid-state imaging device of the present invention, a plurality of pixel signals are horizontally scanned simultaneously, thereby allowing a very high speed scanning operation. In addition, even if the pixel signals from a plurality of signal read lines are transmitted to a plurality of output lines simultaneously through the second group of switching transistors by causing these switching transistors to conduct and not to conduct in accordance with a scanning signal from the horizontal scanning circuit during horizontal scanning, the drain regions of these switching transistors are capacitively separated from each other at least by the predetermined set. This prevents variation between pixel signals, thus improving the image quality. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a partial plan view showing the structure of the main portion of a solid-state imaging device, which is an embodiment of the invention; 
     FIG. 2 is a partial longitudinal sectional view showing the structure of a specific portion shown in FIG. 1; 
     FIG. 3 is a diagram for explaining the construction of a first example of a conventional solid-state imaging device; 
     FIG. 4 is a timing chart showing the operation of the first conventional example; 
     FIG. 5 is a diagram for explaining the construction of a second example of a conventional solid-state imaging device; 
     FIG. 6 is a partial plan view showing the structure of the main portion of the second convectional example; and 
     FIG. 7 is a timing chart showing the operation of the second conventional example. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A solid-state imaging device, which is an embodiment of the invention, will now be described with reference to the accompany drawings. 
     This embodiment is a MOS-type solid-state imaging device having the same general structure as that shown in FIG. 5 and will be described with reference to FIGS. 1 and 2 in terms of differences from the conventional example. 
     Signal read lines S 1  -S 4 , S 5  -S 8 , S 9  -S 12 , . . . , that are adjacent to an array of a group of photodiodes (equivalent to a group of pixels) in matrix form, are formed by embedding an n +  -type impurity layer in a p-type well layer of a semiconductor substrate. The n+ impurity layers S 1  &#39;-S 4  &#39;, S 5  &#39;-S 8  &#39;, S 9  &#39;-S 12  &#39;, . . . are embedded while separated at a predetermined interval from the terminals of the signal read lines S 1  -S 4 , S 5  -S 8 , S 9  -S 12 , . . . . In the figures, only reference characters S 1  &#39;-S 4  &#39;, S 5  &#39;, S 9  &#39; are described as representatives. 
     In addition, four N-channel MOS-type switching transistors M 11  to M 14  that operate simultaneously are formed by laminating a horizontal scanning line l 1 , made of a polysilicon layer extending from a bit output h 1  of a horizontal scanning circuit 3, on the upper surface stretching between the n +  -type impurity layers S 1  -S 4  and S 1  &#39;-S 4  &#39;. Four N-channel MOS-type switching transistors M 21  to M 24  that operate simultaneously are formed by laminating a horizontal scanning line l 2 , made of the polysilicon layer extending from a bit output h 2  of the horizontal scanning circuit 3, on the upper surface stretching between the n +  -type impurity layers S 5  -S 8  and S 5  &#39;-S 8  &#39;. Four N-channel MOS-type switching transistors M 31  to M 34  that operate simultaneously are formed by laminating a horizontal scanning line l 3 , made of the polysilicon layer extending from a bit output h 3  of the horizontal scanning circuit 3, on the upper surface stretching between the n +  -type impurity layers S 9  -S 12  and S 9  &#39;-S 12  &#39;. Although not shown in the figures, other switching transistors for horizontal scanning are similarly constructed. 
     Further, the n +  -type impurity layers S 1  &#39;, S 5  &#39;, and S 9  &#39; and other similarly arrayed n +  -type impurity layers (not shown) are commonly connected to a first output line 5 formed of an aluminum layer through contacts (designated by  ); the n +  -type impurity layers S 2  &#39;, S 6  &#39;, and S 10  &#39; and other similarly arrayed n +  -type impurity layers (not shown) are commonly connected to a second output line 6 formed of the aluminum layer through contacts (designated by  ); the n +  -type impurity layers S 3  &#39;, S 7  &#39;, and S 8  &#39; and other similarly arrayed n +  -type impurity layers (not shown) are commonly connected to a third output line 7 formed of the aluminum layer through contacts (designated by  ); and the n +  -type impurity layers S 4  &#39;, S 8  &#39;, and S 12  &#39; and other similarly arrayed n +  -type impurity layers (not shown) are commonly connected to a fourth output line 8 formed of the aluminum layer through contacts (designated by  ). A portion sharing the signal read lines S 1  -S 4 , S 5  -S 8 , S 9  -S 12 , . . . in common correspond to the source contact regions of the switching transistors M 11  -M 14 , M 21  -M 24 , M 31  -M 34 , . . . , while the regions S 1  &#39;-S 4  &#39;, S 5  &#39;-S 8  &#39;, S 9  &#39;-S 12  &#39;, . . . correspond to the drain contact regions. 
     In addition, separating layers 9 (a shaded portion in the figures), formed of an n +  -type impurity substance, which are embedded between the regions S 1  &#39;-S 4  &#39;, S 5  &#39;-S 8  &#39;, S 9  --S 12  &#39;, . . . have a predetermined voltage V 1  applied thereto. 
     Therefore, the drain region and separating layer 9 of the switching transistor are constructed as shown in FIG. 2 (the longitudinal sectional structure in the vicinity of the switching transistors M 21  -M 31  shown in FIG. 1 is shown along the length of the output line 8). 
     The voltage V 1  is set to be greater than or equal to zero i.e., V 1  ≧0), and it is necessary to keep the voltage fixed so that the potential at the separating layers 9 will not vary. If the voltage V 1  is equal to or greater than a supply voltage V DD  for the solid-state imaging device (i.e., V 1  ≧V DD ), smear can be reduced, which is an advantage. 
     With reference to the depths of the impurity layer (e.g., S 5  &#39;-S 8  &#39;, S 9  &#39; in FIG. 2) constituting part of the switching transistor and the separating layer 9, a deeper separating layer 9 brings about a better effect, as shown in FIG. 2. However, the invention is not particularly limited thereto, and thus the object of the invention may be achieved by making the separating layer 9 shallower than the impurity layer. 
     When an image is horizontally scanned by the horizontal scanning circuit 3, a set of four switching transistors are sequentially put in conduction in synchronism with a horizontal scanning signal sequentially outputted from each bit output h 1 , h 2 , or h 3 , . . . . Thus, the pixel signals S 1  (τ), S 2  (τ), S 3  (τ), and S 4  (τ) for four pixels are read simultaneously so that a process similar to that shown in the timing chart of FIG. 7 will be performed. 
     Consequently, according to this embodiment, a plurality of pixel signals can be read simultaneously and globally by horizontal scanning, thereby allowing high speed signal reading. 
     In addition, the separating layers 9 are formed between the drain regions within the group of switching transistors for horizontal scanning reading (the second group of switching transistors), thereby separating the capacitive coupling between the drain regions of the two adjacent switching transistors. As a result, even if the capacitance of the depletion layer in the drain region is varied due to the operation of a switching transistor, the drain region of a switching transistor adjacent thereto will not be affected. 
     Therefore, no pixel signal variations can be caused during horizontal scanning as in the past, thus improving the video quality. 
     While four switching transistors are operated as a set with respect to each bit output h 1 , h 2 , h 3 , . . . of the horizontal scanning circuit 3 in this embodiment, the number of switching transistors within a set is not limited thereto but may be determined arbitrarily. 
     While the separating layer 9 is formed between the drain regions of all the switching transistors for horizontal scanning in this embodiment, the separating layer may also be formed at least between the drain regions of the two adjacent switching transistors, each belonging to each of the two adjacent sets thereof. Such an arrangement of separating layers is still effective in reducing the negative influence caused between the pixel signals read globally by the set. 
     As described above, according to the invention, a plurality of pixel signals are horizontally scanned simultaneously, thereby allowing a very high speed scanning operation to be performed. Further, even if a plurality of pixel signals are simultaneously transmitted from a plurality of signal read lines to a plurality of output lines through a second group of switching transistors by turning them on and off in accordance with a scanning signal from the horizontal scanning circuit during horizontal scanning, the drain regions can be capacitively separated from each other at least by the predetermined set of switching transistors. Therefore, the pixel signals are not varied from each other and thus the video quality can be improved. 
     Moreover, the device of the invention can image, in particular, a plurality of frames rapidly and clearly within a short period of time, and this provides an advantage in the field of high speed imaging, e.g., taking the instantaneous motion of a rapidly changing object as a still image consisting of a plurality of frames.