Abstract:
Structures and method for forming the same. The semiconductor structure comprises a photo diode that includes a first semiconductor region and a second semiconductor region. The first and second semiconductor regions are doped with a first and second doping polarities, respectively, and the first and second doping polarities are opposite. The semiconductor structure also comprises a transfer gate that comprises (i) a first extension region, (ii) a second extension region, and (iii) a floating diffusion region. The first and second extension regions are in direct physical contact with the photo diode and the floating diffusion region, respectively. The semiconductor structure further comprises a charge pushing region. The charge pushing region overlaps the first semiconductor region and does not overlap the floating diffusion region. The charge pushing region comprises a transparent and electrically conducting material.

Description:
BACKGROUND OF THE INVENTION 
   1. Technical Field 
   The present invention relates to CMOS (Complementary Metal Oxide Semiconductor) sensors, and more specifically, to the CMOS sensors that have charge pushing regions. 
   2. Related Art 
   A typical CMOS sensor comprises a photo diode and a transfer gate. After light is shined on the photo diode, free electrons are created in the photo diode. Then, those free electrons are transferred to a floating diffusion region through the transfer gate. It is desirable to transfer as many free electrons as possible to the floating diffusion region through the transfer gate. Therefore, there is a need for a structure and method to help transfer as many free electrons as possible from the photo diode to the floating diffusion region through the transfer gate. 
   SUMMARY OF THE INVENTION 
   The present invention provides a semiconductor structure, comprising (a) a photo diode that includes a first semiconductor region and a second semiconductor region, wherein the first semiconductor region is doped with a first doping polarity, wherein the second semiconductor region is doped with a second doping polarity, and wherein the first and second doping polarities are opposite; (b) a transfer gate that comprises (i) a first extension region, (ii) a second extension region, and (iii) a floating diffusion region, wherein the first extension region is in direct physical contact with the photo diode, and wherein the second extension region is in direct physical contact with the floating diffusion region; and (c) a charge pushing region, wherein the charge pushing region overlaps the first semiconductor region, wherein the charge pushing region does not overlap the floating diffusion region, and wherein the charge pushing region comprises a transparent and electrically conducting material. 
   The present invention provides a semiconductor structure operation method, comprising providing a semiconductor structure, which comprises (a) a photo diode that includes a first semiconductor region and a second semiconductor region, wherein the first semiconductor region is doped with a first doping polarity, wherein the second semiconductor region is doped with a second doping polarity, and wherein the first and second doping polarities are opposite, (b) a transfer gate that comprises (i) a first extension region, (ii) a second extension region, and (iii) a floating diffusion region, wherein the first extension region is in direct physical contact with the photo diode, and wherein the second extension region is in direct physical contact with the floating diffusion region, and (c) a charge pushing region, wherein the charge pushing region overlaps the first semiconductor region, wherein the charge pushing region does not overlap the floating diffusion region, and wherein the charge pushing region comprises a transparent and electrically conducting material; shining light on the photo diode; turning on the transfer gate; and applying a first voltage to the floating diffusion region of the transfer gate, a second voltage to the second semiconductor region of the photo diode, and a pushing voltage to the charge pushing region so as to help push free electrons from the photo diode to the floating diffusion region through the transfer gate. 
   The present invention provides a sensor array, comprising (a) a substrate; (b) N sensors on the substrate, wherein the N sensors are arranged in rows and columns, wherein each of the N sensors comprises (i) a photo diode that includes a first semiconductor region and a second semiconductor region, wherein the first semiconductor region is doped with a first doping polarity, wherein the second semiconductor region is doped with a second doping polarity, and wherein the first and second doping polarities are opposite, (ii) a transfer gate that comprises (α) a first extension region, (β) a second extension region, and (γ) a floating diffusion region, wherein the first extension region is in direct physical contact with the photo diode, and wherein the second extension region is in direct physical contact with the floating diffusion region, and (iii) a charge pushing region, wherein the charge pushing region overlaps the first semiconductor region, wherein the charge pushing region does not overlap the floating diffusion region, and wherein the charge pushing region comprises a transparent and electrically conducting material, (c) a contact contacting to first and second sensors of the N sensors. 
   The present invention provides a structure and method to help transfer as many free electrons as possible from the photo diode to the floating diffusion region through the transfer gate. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1A-1M  show cross-section views of a CMOS sensor going through different fabrication steps of a fabrication process, in accordance with embodiments of the present invention. 
     FIGS.  1 Ma and  1 Mb show top-down views of CMOS sensor arrays  100 . 1  and  100 . 2 , in accordance with embodiments of the present invention. 
     FIG.  1 Mc shows an operation of the CMOS sensor  100  of  FIG. 1M , in accordance with embodiments of the present invention. 
       FIGS. 2-6  show other embodiments of the CMOS sensor of  FIG. 1M , in accordance with embodiments of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIGS. 1A-1M  show cross-section views of a CMOS (Complementary Metal Oxide Semiconductor) sensor  100  going through different fabrication steps of a fabrication process, in accordance with embodiments of the present invention. 
   More specifically, in one embodiment, the fabrication process starts out with a p-substrate  110  (i.e., lightly doped with p-type dopants). Next, in one embodiment, STI (Shallow Trench Isolation) regions  115   a  and  115   b  are formed in the substrate  110 . Illustratively, the STI regions  115   a  and  115   b  can be formed by first creating two trenches at the two places where the STI regions  115   a  and  115   b  will be formed. Then, a dielectric material such as silicon dioxide is used to fill the two trenches so as to form the STI regions  115   a  and  115   b . Finally, the surface is polished to the original planar surface. 
   Next, with reference to  FIG. 1B , in one embodiment, a gate dielectric layer  116  is formed on top of the substrate  110  and the STI regions  115   a  and  115   b . More specifically, the gate dielectric layer  116  can be formed by thermal oxidation of the silicon on top of the structure  100  of  FIG. 1A . 
   Next, in one embodiment, a poly-silicon layer  118  is formed on top of the gate dielectric layer  116 . More specifically, the poly-silicon layer  118  can be formed by CVD of poly-silicon on top of the gate dielectric layer  116 . Next, in one embodiment, the gate dielectric layer  116  and the poly-silicon layer  118  are patterned so as to form a gate dielectric region  120  and a gate electrode region  125 , respectively, in  FIG. 1C . Illustratively, the gate dielectric region  120  and the gate electrode region  125  are formed by using a conventional lithographic and etching process. It should be noted that the gate dielectric region  120  and the gate electrode region  125  can be collectively referred to as a gate stack  120 , 125 . 
   Next, with reference to  FIG. 1D , in one embodiment, the gate stack  120 , 125  is used as a blocking mask to form extension regions  130   a  and  130   b (i.e., lightly doped with n-type dopants) in the substrate  110  by, illustratively, ion implantation. 
   Next, with reference to  FIG. 1E , in one embodiment, a dielectric layer  135  is formed on top of the structure  100  of  FIG. 1D . More specifically, in one embodiment, the dielectric layer  135  is formed by CVD of silicon dioxide on top of the structure  100  of  FIG. 1D . 
   Next, with reference to  FIG. 1F , in one embodiment, nitride spacers  140   a  and  140   b  are formed on sidewalls of the gate stack  120 , 125 . Illustratively, the nitride spacers  140   a  and  140   b  are formed by depositing a nitride material (e.g., silicon nitride) on top of the entire structure  100  of  FIG. 1E  and then etching back the deposited nitride material, resulting in the nitride spacers  140   a  and  140   b  on side walls of the gate stack  120 , 125 . 
   Next, with reference to  FIG. 1G , in one embodiment, an n-Si region  145  (i.e., lightly doped with n-type dopants) is formed in the substrate  110  by, illustratively, ion implantation. In one embodiment, the n-Si region  145  is implanted with a doping concentration similar to the doping concentration of the extension regions  130   a  and  130   b  and deeper than the extension regions  130   a  and  130   b . The n-Si region  145  and the p-substrate  110  form a PN junction, therefore, can be collectively referred to as a photo diode  110 , 145 . 
   Next, with reference to  FIG. 1H , in one embodiment, a drain region  150  is formed in the substrate  110  by, illustratively, ion implantation. In one embodiment, the drain region  150  (also called a floating diffusion region  150 ) is heavily doped with n-type dopants and deeper than the extension regions  130   a  and  130   b . It should be noted that the gate dielectric region  120 , the gate electrode region  125 , the extension regions  130   a  and  130   b  and the floating diffusion region  150  can be collectively referred to as a transfer gate  155 . 
   Next, with reference to  FIG. 1I , in one embodiment, a nitride layer  160  is formed on top of the structure  100  of  FIG. 1H . Illustratively, the nitride layer  160  can be formed by PECVD (Plasma Enhanced Chemical Vapor Deposition) of silicon nitride on top of the dielectric layer  135  and the nitride spacers  140   a  and  140   b.    
   Next, with reference to  FIG. 1J , in one embodiment, a charge pushing region  165  is formed by CVD of a transparent and conducting material on top of the nitride layer  160  followed by a lithographic and etching step. The lithographic and etching step is performed such that the charge pushing region  165  is only formed to the left and on top of a part of the gate electrode region  125  as shown in  FIG. 1J . In one embodiment, the charge pushing region  165  comprises any material which is transparent and electrically conducting, such as ITO (Indium Tin Oxide—InSnO 2 ). 
   Next, with reference to  FIG. 1K , in one embodiment, a nitride layer  170  is formed on top of the structure  100  of  FIG. 1J . Illustratively, the nitride layer  170  can be formed by PECVD of silicon nitride on top of the charge pushing region  165  and the exposed nitride layer  160 . 
   Next, with reference to  FIG. 1L , in one embodiment, a BPSG (boro phospho silicate glass) layer  175  is formed on top of the structure  100  of  FIG. 1K . More specifically, the BPSG layer  175  can be formed by CVD of BPSG material on top of the nitride layer  170 , and then, the top surface of the BPSG layer  175  can be polished by, illustratively, a CMP (chemical mechanical polishing) step. The resulting structure  100  is shown in  FIG. 1L . 
   Next, with reference to  FIG. 1M , in one embodiment, contacts  180   a  and  180   b  are formed in the structure  100  of  FIG. 1L . Illustratively, the contacts  180   a  and  180   b  can be formed in turn by using a conventional method. In one embodiment, the contacts  180   a  and  180   b  comprise tungsten. In one embodiment, the contacts  180   a  and  180   b  are electrically coupled to the charge pushing region  165  and the floating diffusion region  150 , respectively. In an alternative embodiment, before the contacts  180   a  and  180   b  are formed, liner layers (not shown) are formed on side walls and bottom walls of the trenches where the contacts  180   a  and  180   b  will be formed, respectively. It should be noted that a gate contact must be formed to give electrical access to the gate electrode region  125 , but for simplicity, this contact is not shown in  FIG. 1M . This contact can be seen in FIG.  1 Ma as contact  180   c.    
   FIG.  1 Ma shows a top-down view of a CMOS sensor array  100 . 1  which comprises multiple CMOS sensors similar to the CMOS sensor  100  of  FIG. 1M . More specifically, in FIG.  1 Ma, in one embodiment, there are four CMOS sensors  100   a ,  100   b ,  100   c , and  100   d  (similar to the CMOS sensor  100  of  FIG. 1M ) sharing two gate electrode regions  125   a  and  125   b  (similar to the gate electrode region  125  of  FIG. 1M ) and two charge pushing regions  165   a  and  165   b  (similar to the charge pushing region  165  of  FIG. 1M ). More specifically, the CMOS sensors  100   a  and  100   c  share the gate electrode region  125   a  and the charge pushing region  165   a . Similarly, the CMOS sensors  100   c  and  100   d  share the gate electrode region  125   b  and the charge pushing region  165   b . In one embodiment, the contact  180   a  is electrically coupled to the charge pushing region  165   a.    
   FIG.  1 Mb shows a top-down view of a CMOS sensor array  100 . 2  which comprises multiple CMOS sensors similar to the CMOS sensor  100  of  FIG. 1M . In one embodiment, the CMOS sensor array  100 . 2  is similar to the CMOS sensor array  100 . 1  of FIG.  1 Ma, except that the two charge pushing regions  165   a  and  165   b  of FIG.  1 Ma are connected together to form one charge pushing region  165   ab  in FIG.  1 Mb. In one embodiment, the contact  180   a  which is electrically coupled to the charge pushing region  165   ab , can be formed outside the CMOS sensor array  100 . 2 . 
   In one embodiment, FIG.  1 Mc shows an operation of the CMOS sensor  100  of  FIG. 1M . In general, the operation of the CMOS sensor  100  is as follows. First, a higher voltage is applied to the floating diffusion region  150 , a lower voltage is applied to the substrate  110 , and the transfer gate  155  is turned on. As a result, the photo diode  110 , 145  is reverse biased. Therefore, most free electrons in the photo diode  110 , 145  are pushed to the floating diffusion region  150  via the transfer gate  155 . Then, the transfer gate  155  is turned off. Next, light is shined on the photo diode  110 , 145  momentarily. As a result, electron-hole pairs (not shown) are created in a depletion region (not shown) of the photo diode  110 , 145 . The generated electrons remain preferentially in the depleted n− region  145  while the holes move to the depleted p− region  110 . Next, the transfer gate  155  is turned on, and the charge pushing region  165  is electrically coupled to a pushing voltage which is lower than the voltage of the substrate  110 . Therefore, most free electrons (e.g., an electron  190 ) in the depletion region (not shown) of the photo diode  110 , 145  are pushed to the floating diffusion region  150  along an electron path  195 . The more the pushing voltage is lower than the voltage of the substrate  110 , the more efficiently the photo-generated free electrons are pushed to the floating diffusion region  150 . In one embodiment, when the charge pushing region  165  is electrically coupled to a pushing voltage, a virtual p-type pinning layer  165 ′, specifically a hole inversion layer, is created in the n-Si region  145  and the extension region  140   a . The virtual p-type pinning layer  165 ′ (a) prevents the free electrons (e.g., the electron  190 ) from recombining near the top surface of the substrate  110  and thus lowering the signal strength, and (b) prevents interface states at the semiconductor surface from thermally generating electron-hole pairs (dark current) independently of the desired electron-hole pairs created by photon absorption. 
     FIG. 2  shows a cross-section view of a CMOS sensor  200 , in accordance with embodiments of the present invention. In one embodiment, the CMOS sensor  200  is similar to the CMOS sensor  100  of  FIG. 1M , except that after the step of forming the n-Si region  145 , a p+ region  145 ′ (also called a pinning region  145 ′) is formed in the substrate  110  by, illustratively, ion implantation (as shown in  FIG. 2 ). In one embodiment, the p+ region  145 ′ is implanted shallower than the extension regions  130   a  and  130   b . The p+ region  145 ′ prevents the free electrons (e.g., the electron  190  of FIG.  1 Mc) from recombining with holes (not shown) which reside near the top surface of the substrate  110 . In one embodiment, the charge pushing region  165  is formed only to the left of the transfer gate  155 . 
     FIG. 3  shows a cross-section view of a CMOS sensor  300 , in accordance with embodiments of the present invention. In one embodiment, the CMOS sensor  300  is similar to the CMOS sensor  100  of  FIG. 1M , except that the nitride layer  160 , which is present in structure  100  of  FIG. 1M , is not present in the CMOS sensor  300  of  FIG. 3 . As a result, the charge pushing region  165  in  FIG. 3  is closer to the n-Si region  145  than in  FIG. 1 . 
     FIG. 4  shows a cross-section view of a CMOS sensor  400 , in accordance with embodiments of the present invention. In one embodiment, the CMOS sensor  400  is similar to the CMOS sensor  300  of  FIG. 3 , except that after the step of forming the n-Si region  145 , the p+ region  145 ′ is formed in the substrate  110  by, illustratively, ion implantation (as shown in  FIG. 4 ). In one embodiment, the p+ region  145 ′ is implanted shallower than the extension regions  130   a  and  130   b . The p+ region  145 ′ prevents the free electrons (e.g., the electron  190  of FIG.  1 Mc) from recombining with holes (not shown) which reside near the top surface of the substrate  110 . In one embodiment, the charge pushing region  165  is formed only to the left of the transfer gate  155 . 
     FIG. 5  shows a cross-section view of a CMOS sensor  500 , in accordance with embodiments of the present invention. In one embodiment, the CMOS sensor  500  is similar to the CMOS sensor  300  of  FIG. 3 , except that after the step of forming the dielectric layer  135 , a trench  115 ′ is formed in the STI region  115   a  by using any conventional process (e.g., lithographic and then etching step). Therefore, in the ensuing steps of forming the charge pushing region  165  and the nitride layer  170 , a portion of the charge pushing region  165  and a portion of the nitride layer  170 , respectively, are formed on side walls and bottom walls of the trench  115 ′. As a result, the charge pushing region  165 , when being applied a pushing voltage which is lower than the voltage of the substrate  110 , helps push the free electrons (e.g., the electron  190  of FIG.  1 Mc) toward the floating diffusion region  150  via the transfer gate  155 . 
     FIG. 6  shows a cross-section view of a CMOS sensor  600 , in accordance with embodiments of the present invention. In one embodiment, the CMOS sensor  600  is similar to the CMOS sensor  500  of  FIG. 5 , except that after the step of forming the n-Si region  145 , the p+ region  145 ′ is formed in the substrate  110  by, illustratively, ion implantation (as shown in  FIG. 6 ). In one embodiment, the p+ region  145 ′ is implanted shallower than the extension regions  130   a  and  130   b . The p+ region  145 ′ prevents the free electrons (e.g., the electron  190  of FIG.  1 Mc) from recombining with holes (not shown) which reside near the top surface of the substrate  110 . In one embodiment, the charge pushing region  165  is formed only to the left of the transfer gate  155  as shown in  FIG. 6 . 
   While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.