Abstract:
This invention discloses a decoder circuit utilizing Josephson devices where Josephson AND gates, output lines connecting both terminals of each said Josephson device and an input signal line are provided in as many as 2 n  in number in the nth stage of plural stages. The Josephson AND gate turns ON with the logical product (AND) of the current flowing into the output line of said Josephson AND gate of the preceding stage and the current flowing into the input signal line of the pertinent stage and causes a current to flow into the respective output line.

Description:
This application is a continuation of application Ser. No. 290,976, filed Aug. 7, 1981, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     (1) Field of the Invention 
     This invention relates to a decoder circuit utilizing the Josephson device. 
     (2) Description of the Prior Art 
     The existing decoders of Josephson memory circuits are classified into several kinds, but each decoder is basically composed of a combination of current flip-flop circuits one of which is shown in FIG. 1. In the current flip-flop, when an input signal current S 1  is applied to the Josephson junction J 1  in the left side while a bias current I B  flows through the Josephson junction, this junction momentarily acquires a voltage state and the bias current I B  essentially flows through the junction J 2  in the right side. When an input current S 2  flows, on the contrary, to the junction J 2  in the right side, the bias current I B  essentially flows through the left side junction J 1 . In any case, the junctions J 1 , J 2  are connected in parallel, and when the one is in the voltage state, the other is in the supercurrent state. Therefore, when one is returned to the supercurrent state, the current path is switched. A combination of such current flip-flops forms the so called tree decoder as shown in FIG. 2 which is demonstrated in the IEEE J. Solid State Circ., Vol. SC-13, No. 5, PP. 591-600, 1978 by W. H. Henkels and H. Zappe. The circuit shown in FIG. 2 is an example of the 8-bit address decoder, where a current flows in one of the address lines AL 1  to AL 8  according to the 3-bit input signals A 1 , A 2 , A 3 . For example, when the address bit A 1  is 1, the junction J 1  becomes ON (voltage state) and the current I B  flows in the branch including the junction J 2 . When the address bit A 2  is 0, the inverted bit A 2  is 1 and therefore the junction J 6  becomes ON, causing the current I B  to flow into the branch including the junction J 5 . Moreover, when the address bit A 3  is 1, the junction J 11  becomes ON and the current flows in the address line AL 6  including the junction J 12  (AL 6  is selected). The desired one address line among 2 n  lines can be selected in this way with an input signal of n-bits. The loop decoder is also proposed in the IEEE J. Solid State Circ. Vol. SC-14, No. 4, PP. 699-707, 1979 by S. Faris as another type of decoder circuit. These decoder circuits are all composed of combinations of current flip-flop circuits or modified circuits. But the current flip-flop has as a load the superconducting loop inductance from the point of view of the Josephson junction. For this reason, such a decoder circuit has the disadvantage that if the address lines AL 1  to AL 8  become long, a longer period is required for switching the branch circuit of the current I B . In practice, the switching period is on the order of nanosecond and the decoder circuit utilizing such current flip-flops cannot sufficiently utilize the high speed characteristic (several 10 PS) of the Josephson device. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a decoder circuit which assures a high operation speed. It is another object of the present invention to provide a decoder circuit which has reduced the number of wirings and resultingly is suitable for realization of higher integration density. In the decoder circuit of the present invention for attaining such objects including the Josephson device is a Josephson AND gate, 2 n  output lines respectively connecting both ends of each Josephson device and the input signal lines are provided in the nth stage, so that each gate becomes ON with the logical product (AND) of the current flowing in the output line of the preceding stage and the input signal current flowing thereto, and a current flows into the respective output line. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows the equivalent circuit of the current flip-flop utilizing the Josephson devices. 
     FIG. 2 shows the equivalent circuit of the existing tree decoder circuit utilizing a current flip-flop shown in FIG. 1. 
     FIG. 3 shows an embodiment of the present invention. 
     FIG. 4 shows another embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 3 shows the equivalent circuit of an embodiment of the present invention, which is an example of the circuit where the 8-bit address lines AL 1  to AL 8  are selected by the 3-bit input signals A 1  to A 3 . In this example, the circuits, in which the Josephson devices respectively having the 2-input AND function are serially connected, are provided in three stages, where the 1st stage includes two devices J 1 , J 2  while the 2nd stage has four devices J 3  to J 6  and the 3rd stage has eight devices J 7  to J 14 . In the 1st stage, the input signal A is applied to the device J 1  while the inverted signal A 1  of the signal A 1  (A 1  &#39;s complement) is applied to the device J 2 , and moreover the signal I s  for starting the decoding is applied in common to the devices J 1  and J 2 . An output of device J 1  is given to the devices J 3  and J 4  in the 2nd stage, while an output of the device J 2  is given to the devices J 5  and J 6  of the 2nd stage. The input signal A 2  of the 2nd stage is applied to the devices J 3  and J 5 , while the complement A 2  is appplied to the devices J 4  and J 6 . At the 3rd stage an output of the device J 3  is applied to the devices J 7 , J 8  while an output of device J 4  is applied to the devices J 9 , J 10 , an output of device J 5  to the devices J 11 , J 12  and an output of device J 6  to the devices J 13 , J 14  as explained above. On the other hand, the input signal A 3  of the 3rd stage is applied to the devices J 7 , J 9 , J 11  and J 13 , and the complement A 3  to the devices J 8 , J 10 , J 12  and J 14 . These devices J 1  to J 14  are respectively 2-input Josephson AND gates and these become ON (voltage state) only when the two inputs are 1. The resistors R L1  to R L14  are load resistors and R 1  to R 3  are bias current dividing resistors. In this example, as the bias power supply, the desired bias current I B  is supplied as illustrated in common to each stage through the resistors R 1  to R 3 , but this may be changed as desired. For example, the bias power supply may be respectively provided to each stage. Then, the operation when (A 1 , A 2 , A 3 )=(1, 0, 1) will be explained below. When this input signal is given and the decoding start signal I s  is applied, the device J 1  is first switched to the voltage state (ON) when A 1  =1, I S  =1 and an output is given to the devices J 3  and J 4  in the 2nd stage. At this time, since A 2  =1, the device J 4  is switched ON in the 2nd stage and an output is given to the devices J 9  and J 10  in the 3rd stage. As a result, the device J 9  which receives said output and the signal of A 3  =1 is switched and thereby only the address line AL 3  is selected. In the above operation, it is important that the devices J 1  to J 14  all operate with the latch operation and do not operate in the form of the current flip-flop. Therefore, the resistance values of the load resistors R L1  to R L14  are provided to match the characteristic impedance of the wirings and outstanding high speed selection of the address lines AL 1  to AL 8  can be realized (improvement of high speed operation by one order of magnitude can be realized as compared with the operation speed of the current flip-flop type). Although power consumption is certainly increased due to the latch operation, such increment of power consumption is sufficiently small as to be negligible for practical operation because only the n ON gates actually consume power. In the above embodiment, the decoding start signal I s  is externally provided, but it can also be obtained by branching the bias current I B  also as the signal I s  on the signal line, or the signal I s  can be omitted when the device J 1  of the first stage is formed as an OR gate. In addition, the devices in each stage are connected in series in the above embodiment, but these can also be connected in parallel by dividing the bias current I B . Furthermore, even in the case of the series connection, it is desirable to insert a resistor between the elements in view of the realizing reliable operation of elements. For the devices J 1  to J 14 , a discrete junction element, a two-junction quantum interference device or a three-junction quantum interference device may be employed, so long as each plays the role of the 2-input AND function. FIG. 4 shows the equivalent circuit indicating a further embodiment of the present invention which is an example of the circuit wherein the 8-bit address lines AL 1  to AL 8  are selected by the 3-bit external input signal A 1  to A 3 . In this embodiment, the circuit has a staircase structure of three stages. In the 1st stage, 2 latch-type AND circuits (Josephson devices) J 1  to J 2  are provided, while four devices J 3  to J 6  are provided in the 2nd stage and eight devices J 7  to J 14  in the 3rd stage, thus 14 devices being provided in all. Each device is a 2-input AND circuit which receives an output of the preceding stage as the internal input signal and a respective one of the external input signals A 1  to A 3  and the complements A 1  to A 3  as the bias current, and switches to the ON (voltage) state when both inputs are 1. Namely, the external input signal A 1  causes a bias current to flow into the Josephson device J 1  and the A 1  &#39;s complement A 1  causes a bias current to flow into the device J 2 . The external input signal A 2  of the 2nd stage causes a bias current to flow into the devices J 3 , J 5  while the complement A 2  causes a bias current to flow into the devices J 4 , J 6 . In the same way, the external input signal A 3  of the 3rd stage causes a bias current to flow into the devices J 7 , J 9 , J 11 , J 13  while the complement A 3  causes the bias current to flow into the devices J 8 , J 10 , J 12  and J 14 . On the other hand, an output of the device J 1  is given to the devices J 3 , J 4  while an output of the device J 2  is given to the devices J 5 , J 6  respectively as the internal input signal. Similarly, an output of the device J 3  is applied to the devices J 7 , J 8  of the next stage, while an output of the device J 4  is to the devices J 9 , J 10 , an output of the device J 5  is to the devices J 11 , J 12 , an output of the device J 6  is to the devices J 13 , J 14 , respectively, as the internal input signals. Since no output of the preceding stage is given to the devices J 1  and J 2  of the 1st stage, the signal current I s  for starting the decoding is given to them. Operation when the external input signals A 1  =1, A 2  =0, A 2  =1, for example, are fed will now be explained. When I s  =1 is given after the external inputs A 1  to A 3  are given, the device J 1  wherein the two inputs A 1  and I s  are 1 is switched ON, outputting a signal to the devices J 3 , J 4  of the next stage. At this time, since A 2  =0 and resultingly A 2  =1, the device J 4  turns to voltage stage. In addition, an output of the device J 4  is given to the devices J 9  and J 10  of the 3rd stage, and since A 3  =1, the device J 9  switches and, as a result, only the address line AL 3  including a load resistor R L9  is selected. The gate used here switches only when both the bias current (here the external input signals A 1  to A 3  and the complements) and the input signal current (signal I s  or an output of a preceding stage) are given simultaneously, and moreover said gate performs the latch operation. The characteristic impedance of the interconnection is matched to the load resistors R L1  to R L14  and thereby an improvement of high speed characteristic by about one order of magnitude is expected as compared with the existing decoder circuit. For the devices J 1  to J 14 , not only the discrete junction device but also the two-junction quantum interference device or three junction quantum interference device, namely any Josephson device which has the AND function between the bias current and input signal may be used. Moreover, the decoding start signal I s  can be omitted if the devices J 1 , J 2  of the 1st stage are designed to be switched with the bias current. The Josephson junctions connected in series in each stage may also be connected in parallel. However, in the case of the parallel connection, the external input signal currents are increased as many times as the number of parallel connections. Therefore, the signal circuit must have a large driving capability. 
     As explained above, the present invention provides an advantage that the circuit can be formed with the strip lines terminated by the matching impedance because the latch type Josephson AND gates are used and moreover a high speed decoder circuit can be realized. 
     Particularly, the 2nd embodiment is superior in high density integration of elements because one of the two inputs is the bias current to be supplied to the Josephson junction and therefore only one signal line is required for field coupling to said junction and resultingly a lesser number of wirings are required.