Abstract:
A semiconductor device, includes: a connection member including a first pad formed on a principal surface thereof; a semiconductor chip including a circuit-formed surface on witch a second pad is formed, the chip mounted on the connection member so that the circuit-formed surface faces the principal surface; and a solder bump that connects the first and second pads and is made of metal containing Bi and Sn, wherein the bump includes a first interface-layer formed adjacent to the second pad, a second interface-layer formed adjacent to the first pad, a first intermediate region formed adjacent to either one of the interface-layers, and a second intermediate region formed adjacent to the other one of the interface-layers and formed adjacent to the first intermediate region; Bi-concentration in the first intermediate region is higher than a Sn-concentration; and a Sn-concentration in the second intermediate region is higher than a Bi-concentration.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2012-178509, filed on Aug. 10, 2012, and the prior Japanese Patent Application No. 2011-221364, filed on Oct. 5, 2011, the entire contents of which are incorporated herein by reference. 
       FIELD 
       [0002]    The embodiments discussed herein are related to a semiconductor device, an electronic device, and a method for manufacturing the same. 
       BACKGROUND 
       [0003]    With an increase in integration density of semiconductor elements and an increase in packaging density of electronic components, the number of input/output terminals of the semiconductor elements and the electronic devices using the same is increasing. For example, in a semiconductor element to be flip-chip mounted, the pitch between connection terminals is reduced and further the area of the connection terminals is also reduced. 
         [0004]    In order to achieve high-speed operation, severe demands are imposed on current semiconductor elements in which high-speed operation is desired. For example, in a current high-speed semiconductor element, such as a large scale integrated circuit (LSI), so-called low-K materials, such as porous silica, are used as an interlayer insulation film in order to reduce the parasitic capacitance between wiring patterns. However, the low-K materials have problems in that the materials generally have a low density corresponding to a low dielectric constant, and therefore the materials are mechanically vulnerable and are easily damaged due to thermal distortion during joining. For example, porous silica has an elastic modulus of 4 to 8 GPa, and the mechanical strength thereof is lower than that of conventional interlayer insulation materials, such as a silicon oxide film. 
         [0005]    Under such a situation, the high-speed semiconductor elements containing the low-K materials are desired to reduce thermal distortion of a substrate during joining by joining the connection terminals at a low temperature when manufacturing a semiconductor device by flip-chip mounting of a semiconductor chip. However, a generally-used lead-free solder for joining the connection terminals is used at a temperature of 217° C. or higher for joining, and is not suitable for joining at such a low temperature. Under such a situation, in mounting of the high-speed semiconductor elements containing the low-K materials, an eutectic Sn(tin)-Bi (bismuth) solder having a melting point of 139° C. or a solder in which a little amount of elements, such as Ag, Cu, and Sb, is added to Sn—Bi for the purpose of improving the mechanical characteristics, such as ductility, is used as a solder material capable of reducing thermal stress in many cases. 
         [0006]    As described above, the eutectic Sn—Bi solder has a melting point of 139° C. and may be mounted at a temperature lower by about 80° C. than, for example, an Sn—Ag—Cu solder (Melting point of 217° C.) which is a conventional lead-free solder. 
         [0007]    However, there is a demand in an actual electronic device such that, in order to secure the reliability of the electronic device, the electronic device is subjected to a temperature cycle test or a high temperature exposure test at an environmental temperature of about 150° C. considering the actual environment. However, when such a test is performed, the environmental temperature (150° C.) of the test exceeds the melting point (139° C.) of the Sn—Bi solder, which may cause a problem of re-melting of a junction portion or the like. 
         [0008]    In a semiconductor device or an electronic device having a configuration in which a large number of circuit boards and semiconductor chips are stacked, a problem may arise such that a portion, which is previously joined by reflowing solder bumps, melts in the reflow of solder bumps to be performed later in the semiconductor device or the electronic device. 
         [0009]    Examples of the above-described related art is disclosed in Kenichi YASAKA, Yasuhisa OHTAKE, et al., “Microstructural Changes in Micro-joins between Sn-58Bi Solders and Copper by Electro-migration” ICEP 2010 Proceedings FA2-1, pp. 475-478, and OHTAKE et al., “Electro-migration in Microjoints between Sn—Bi Solders and Cu”, 16th Symposium on Microjoining and Assembly Technology in Electronics, Feb. 2-3, 2010, Yokohama, pp 157-160. 
       SUMMARY 
       [0010]    According to an aspect of the embodiments, a semiconductor device includes: a first connection member that includes a first connection pad formed on a first principal surface of the first connection member; a fast semiconductor chip that includes a circuit-formed surface on which a semiconductor integrated circuit is formed and a second connection pad formed on the circuit-formed surface, the fast semiconductor chip mounted on the first connection member in such a manner that the circuit-formed surface faces the first principal surface; and a solder bump that connects the first connection pad to the second connection pad and is made of metal containing Bi and Sn, wherein the solder bump includes a first interface layer formed adjacent to the second connection pad, a second interface layer formed adjacent to the first connection pad, a first intermediate region formed adjacent to either one of the first interface layer or the second interface layer, and a second intermediate region formed adjacent to the other one of the first interface layer and the second interface layer and formed adjacent to the first intermediate region; a concentration of Bi in the first intermediate region is higher than a concentration of Sn in the first intermediate region; and a concentration of Sn in the second intermediate region is higher than a concentration of Bi in the second intermediate region. 
         [0011]    The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
         [0012]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0013]      FIG. 1A  is a plan view illustrating the configuration of a semiconductor device according to a first embodiment; 
           [0014]      FIG. 1B  is a cross sectional view along the IB-IB line of  FIG. 1A ; 
           [0015]      FIG. 1C  is a plan view illustrating an example of a wiring pattern formed in members of  FIG. 1A ; 
           [0016]      FIG. 2A  is a cross sectional view illustrating the structure of a solder bump for use in the first embodiment; 
           [0017]      FIG. 2B  is a cross sectional view illustrating the structure of a solder bump according to one modification of the first embodiment; 
           [0018]      FIG. 3A  is a view (No. 1) illustrating a formation process of the solder bump of  FIG. 2A ; 
           [0019]      FIG. 3B  is a view (No. 2) illustrating a formation process of the solder bump of  FIG. 2A ; 
           [0020]      FIG. 3C  is a view illustrating a formation process of the solder bump of  FIG. 2B ; 
           [0021]      FIG. 4  is a phase diagram of a Sn—Bi binary system; 
           [0022]      FIG. 5A  is a SEM image illustrating the initial state of a solder bump; 
           [0023]      FIG. 5B  is a SEM image illustrating the final state of a solder bump about Sample 1; 
           [0024]      FIG. 5C  is a SEM image illustrating the final state of a solder bump about Sample 2; 
           [0025]      FIG. 6  is a cross sectional view illustrating another modification of a solder bump; 
           [0026]      FIG. 7A  is a view (No. 1) explaining a first portion of a manufacturing process of a semiconductor device according to a second embodiment; 
           [0027]      FIG. 7B  is a view (No. 2) explaining a first portion of the manufacturing process of the semiconductor device according to the second embodiment; 
           [0028]      FIG. 7C  is a view (No. 3) explaining a first portion of the manufacturing process of the semiconductor device according to the second embodiment; 
           [0029]      FIG. 7D  is a view (No. 4) explaining a first portion of the manufacturing process of the semiconductor device according to the second embodiment; 
           [0030]      FIG. 8A  is another view (No. 1) explaining a second portion of the manufacturing process of the semiconductor device according to the second embodiment; 
           [0031]      FIG. 8B  is another view (No. 2) explaining the second portion of the manufacturing process of the semiconductor device according to the second embodiment; 
           [0032]      FIG. 8C  is another view (No. 3) explaining the second portion of the manufacturing process of the semiconductor device according to the second embodiment; 
           [0033]      FIG. 8D  is another view (No. 4) explaining the second portion of the manufacturing process of the semiconductor device according to the second embodiment; 
           [0034]      FIG. 8E  is another view (No. 5) explaining the second portion of the manufacturing process of the semiconductor device according to the second embodiment; 
           [0035]      FIG. 8F  is another view (No. 6) explaining the second portion of the manufacturing process of the semiconductor device according to the second embodiment; 
           [0036]      FIG. 9A  is another view (No. 1) explaining a third portion of the manufacturing process of the semiconductor device according to the second embodiment; 
           [0037]      FIG. 9B  is another view (No. 2) explaining the third portion of the manufacturing process of the semiconductor device according to the second embodiment; 
           [0038]      FIG. 9C  is another view (No. 3) explaining the third portion of the manufacturing process of the semiconductor device according to the second embodiment; 
           [0039]      FIG. 9D  is another view (No. 4) explaining the third portion of the manufacturing process of the semiconductor device according to the second embodiment; 
           [0040]      FIG. 10  is a cross sectional view illustrating the configuration of a semiconductor device according to a third embodiment; 
           [0041]      FIG. 11  is a cross sectional view illustrating the configuration of a semiconductor device according to a fourth embodiment; and 
           [0042]      FIG. 12  is a perspective view illustrating an electronic device according to a fifth embodiment. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
     First Embodiment 
       [0043]      FIG. 1A  is a plan view illustrating the configuration of a semiconductor device  20  according to a first embodiment.  FIG. 1B  illustrates a cross sectional view along the IB-IB line of  FIG. 1A . 
         [0044]    Referring to  FIG. 1A  and  FIG. 1B , the semiconductor device  20  has a circuit board  11  (fast connection member) and a semiconductor chip  21  (fast semiconductor chip), and the semiconductor chip  21  is flip-chip mounted on a mounting surface  11 A (first principal surface) of the circuit board  11 . 
         [0045]    When described in more detail, the semiconductor chip  21  has a circuit-formed surface  21 A on which a large scale integrated circuit (LSI) is formed. On the circuit formed surface  21 A, a large number of electrode pads  21   a  (second connection pads  21 a) containing copper (Cu), for example, are formed in a matrix shape. In contrast thereto, on the circuit board  11 , electrode pads  11   a  (fast connection pads  11   a ) corresponding to the electrode pads  21   a  and similarly containing copper are formed in a matrix shape, for example, on the mounting surface  11 A facing the circuit formed surface  21 A of the semiconductor chip  21 . 
         [0046]    The semiconductor chip  21  is mounted on the circuit board  11  in such a manner that the circuit formed surface  21 A faces the mounting surface  11 A of the circuit board  11 . The electrode pads  21   a  are electrically and mechanically connected to the corresponding electrode pads  11   a  by Sn—Bi solder bumps  31 A. 
         [0047]    On the mounting surface  11 A of the circuit board  11 , a large number of wiring patterns  11   b  each containing copper, for example, are formed as illustrated as the plan view of  FIG. 1C . Each wiring pattern  11   b  extends from the electrode pad  11   a  to the electrode pad  11   c  provided corresponding to the electrode pad  11   a  on the mounting surface  11 A. In the circuit board  11 , through via plugs  11 C schematically illustrated with the thick dashed line are formed corresponding to the electrode pads  11   c.  The through via plug  11 C extends from the mounting surface  11 A to a facing back surface  11 B (second principal surface) through the circuit board  11 .  FIG. 1C  is a plan view of the mounting surface  11 A of the circuit board  11  excluding the semiconductor chip  21 . In  FIG. 1C , the semiconductor chip  21  is illustrated with the thin dashed line corresponding to the excluded state. On the back surface  11 B, electrode pads  11   d  having a size larger than that of the electrode pads  11   a  are formed corresponding to the through via plugs  11 C in a substantially matrix shape, for example, with a larger pitch than the pitch of the electrode pads  11   a.  On each electrode pad  11   d,  solder bumps  11 D larger than the electrode pads  11   a  are formed. The electrode pad  11   d  may also be formed with copper and the solder bump  11 D may also be formed from the same Sn—Bi solder as that of the solder bump  31 A. 
         [0048]    In the semiconductor device  20  of such a configuration, the electrode pads  21   a  of the semiconductor chip  21  flip-chip mounted on the circuit board  11  are electrically connected to the solder bumps  11 D through the solder bumps  31 A, the electrode pads  11   a  on the mounting surface  11 A of the circuit board  11 , the wiring patterns  11   b  and the electrode pads  11   c  on the mounting surface  11 A, the through electrodes  11 C, and the corresponding electrode pads  11   d.  The circuit board  11  may be provided with other active elements or passive elements on the mounting surface  11 A, in the circuit board  11 , or further on the back surface  11 B. 
         [0049]      FIG. 2A  is a cross sectional view illustrating the configuration of the solder bump  31 A in detail. 
         [0050]    Referring to  FIG. 2A , in this embodiment, a first interface layer  31   a  containing a copper-tin (Cu—Sn) alloy is formed contacting the electrode pad  21   a  containing copper, a second interface layer  31   b  containing a copper-tin alloy is formed contacting the electrode pad  11   a  similarly containing copper, and a first intermediate region  31   c  containing Bi (bismuth) in a concentration of 85 wt % or more as the main ingredients is formed contacting the first interface layer  31   a  in a laminated state in the solder bump  31 A. Further, a second intermediate region  31   d  is formed between the first intermediate region  31   c  and the second interface layer  31   b.  The second intermediate region  31   d  containing a copper-tin alloy containing Sn in a high concentration is formed by a reaction of concentrated Sn (tin) into a neighborhood of the second interface layer  31   b  in the solder bump and the copper in the second interface layer  31   b.    
         [0051]    For example, when the solder bump  31 A has a diameter of about 100 μm, the first intermediate region  31   c  and the second intermediate region  31   d  have a thickness reaching 65 μm and 35 μm, respectively, for example. 
         [0052]      FIG. 2B  illustrates a modification of the embodiment of  FIG. 2A . In the modification of  FIG. 2B , the first intermediate region  31   c  is formed contacting the second interface layer  31   b  and the second intermediate region  31   d  is formed contacting the first interface layer  31   a.    
         [0053]    The fast and the second intermediate regions  31   c  and  31   d  illustrated as  FIG. 2A  and  FIG. 2B  are formed by joining the semiconductor chip  21  at a reflow temperature of 139□C, for example, onto the circuit board  11  using an eutectic Sn—Bi solder as the solder bump  31 A as described later, and then applying a direct current to the solder bump  31 A to induce electromigration and have a feature of having a melting point exceeding 215□C, for example, which is still higher than that of the original Sn—Bi solder. 
         [0054]    The fast and the second intermediate regions  31   c  and  31   d  illustrated as  FIG. 2A  and  FIG. 2B  are formed by joining the semiconductor chip  21 , for example, at a reflow temperature of 139° C. onto the circuit board  11  using an eutectic Sn—Bi solder as the solder bump  31 A, and subsequently applying a direct current to the solder bump  31 A to induce electromigration, consequently, the solder bump  31 A has a feature of having a melting point exceeding 215° C., for example, which is still higher than that of the original Sn—Bi solder, as described later. 
         [0055]    Therefore, it is noted that although the solder bump  31 A of  FIG. 2A  and  FIG. 2B  is formed at a low reflow temperature, the solder bump  31 A does not re-melt even when the environmental temperature increases almost to the reflow temperature later and the electrical and mechanical connection between the semiconductor chip  21  and the circuit board  11  is stably maintained. 
         [0056]    Hereinafter, formation processes of the structure of  FIG. 2A  are described with reference to  FIG. 3A  and  FIG. 3B . 
         [0057]    Referring to  FIG. 3A , the semiconductor chip  21  is joined onto the circuit board  11  by reflowing a Sn—Bi solder bump  31 Aa having a substantially eutectic composition at a temperature of 139° C. in a nitrogen gas atmosphere in this embodiment. By the heat treatment accompanied with the reflow, the first interface layer  31   a  is formed with a copper-tin alloy at a junction portion with the electrode pad  21   a  and the second interface layer  31   b  is similarly formed with a copper-tin alloy at a junction portion with the electrode pad  11   a  in the solder bump  31 Aa. Hereinafter, the state of  FIG. 3A  is referred to as an “initial state”. 
         [0058]    Next, as illustrated as  FIG. 3B , in this embodiment, a direct current I is applied to the solder bump  31 Aa using the electrode pad  21   a  as an anode and the electrode pad  31   b  as a cathode. It is known that when the direct current I is applied to the Sn—Bi solder, Bi concentrates to the anode side and Sn concentrates to the cathode side by electromigration (Microstructural Changes in Micro-joins between Sn-58Bi Solders and Copper by Electro-migration ICEP 2010 Proceedings FA2-1, pp. 475-478 and Otake, et al., 16th Symposium on “Microjoining and Assembly Technology in Electronics, Feb. 2-3, 2010, Yokohama). 
         [0059]    Then, in this embodiment, segregation is induced in the solder bump  31 Aa which is uniform at the beginning utilizing the electro migration phenomenon to form the first intermediate region  31   c  abundant in Bi and the second intermediate region  31   d  abundant in Sn. 
         [0060]      FIG. 4  is a phase diagram of a Sn—Bi binary system. 
         [0061]    Referring to  FIG. 4 , when the Sn—Bi solder has a substantially eutectic composition, the melting point is about 139° C. Accordingly, the structure of  FIG. 3A  may be formed by joining at such a low temperature without producing an excessive thermal stress in the Low-K materials and the like used in the semiconductor chip  21 . 
         [0062]    Furthermore, by performing the electrification process of  FIG. 3B , the concentration of Bi becomes higher in the first intermediate region  31   c  than that of the initial composition substantially corresponding to the eutectic composition, and thus the melting temperature of the first intermediate region  31   c  becomes higher than the melting temperature in the initial composition. Similarly, also in the second intermediate region  31   d,  the concentration of Sn becomes higher than that of the initial configuration, and also the melting temperature of the second intermediate region  31   d  becomes higher than that of initial configuration. More specifically, a preferable feature is obtained such that the melting temperature becomes higher in the solder bump  31 A in which segregation has occurred as described above than the melting temperature of the solder bump  31 Aa during joining. Hereinafter, the state of  FIG. 3B  is referred to as a “final state”. 
         [0063]      FIG. 5A  is a SEM (scanning electron microscope) image, corresponding to the initial state of  FIG. 3A , of the section along the VA-VA line of the solder bump  31 Aa before the application of the direct current I immediately after the reflow. 
         [0064]    Referring to  FIG. 5A , it is found that a characteristic organization is formed in an eutectic alloy where a bright domain abundant in Bi and a dark domain abundant in Sn are almost uniformly mixed in the solder bump  31 Aa. 
         [0065]    In contrast thereto,  FIG. 5B  illustrates the cross-sectional structure along the VB-VB line of  FIG. 3B  of the solder bump  31 A after electrification, i.e., in the final state. 
         [0066]    Referring to  FIG. 5B , an alloy (intermetallic compound) layer having a composition of Cu 6 Sn 5  is formed as the first interface layer  31   a  along the surface of the electrode pad  21   a.  Moreover, an alloy (intermetallic compound) layer having a composition of Cu 3 Sn is formed as the second interface layer  31   b  along the surface of the electrode pad  11   a.    
         [0067]    Furthermore, the first intermediate region  31   c  mainly containing Bi and substantially not containing Sn is formed in the shape of a layer adjacent to the first interface layer  31   a,  and a region mainly containing a Cu 6 Sn 5  alloy (intermetallic compound) and substantially not containing Bi is formed in the shape of a layer as a whole between the first intermediate region  31   c  and the second interface layer  31   b  to form the second intermediate region  31   d.  The organization of  FIG. 5B  is obtained when a direct current is applied in the structure of  FIG. 5A  at a current density of 1.0 to 2.0×10 8  Am −2  without heating from the electrode pad  21   a  to the electrode pad  11   a,  this is corresponding to Example 1 described later. 
         [0068]      FIG. 5C  represents the cross-sectional structure in the final state of another sample corresponding to Example 2 described later along the VC-VC line of the solder bump  31 A after electrification of  FIG. 3B . 
         [0069]    Referring to  FIG. 5C , an alloy (intermetallic compound) layer having a composition of Cu 6 Sn 5  is formed as the first interface layer  31   a  along the surface of the electrode pad  21   a  in the same manner as in the case of  FIG. 5B  and an alloy (intermetallic compound) layer having a composition of Cu 3 Sn is formed as the second interface layer  31   b  along the surface of the electrode pad  11   a.    
         [0070]    Furthermore, also in the organization of  FIG. 5C , the first intermediate region  31   c  mainly containing Bi and substantially not containing Sn is formed adjacent to the interface layer  31   a  in the shape of a layer. Furthermore, between the first intermediate region  31   c  and the second interface layer  31   b,  a region mainly containing a Cu 6 Sn 5  alloy (intermetallic compound) and substantially not containing Sn is formed in the shape of a layer to form the second intermediate region  31   d.  The organization of  FIG. 5C  is obtained when a direct current is applied in the structure of  FIG. 5A  at a current density of 1.0 to 2.0×10 8  Am −2  while heating the junction portions of the electrode pad  21   a  and the electrode pad  11   a  to be connected by the SnBi solder  31 Aa to 100° C. or higher from the electrode pad  21   a  to the electrode pad  11   a.    
         [0071]    The results described in  FIGS. 5B and 5C  illustrate that Cu moves by diffusion into the solder bump  31 Aa from the electrode pad  11   a  acting as the cathode with the application of the direct current and the Cu which moves by diffusion forms the interface layer  31   b  and the intermediate region  31   d  in the solder bump  31 A by a reaction with Sn present in the solder bump  31 Aa. The results of  FIGS. 5B and 5C  illustrate that Cu moves by diffusion into the solder bump  31 Aa from the electrode pad  21   a  acting as the anode with the application of the direct current and the Cu which moves by diffusion forms the interface layer  31   a  in the solder bump  31 A by a reaction with Sn present in the solder bump  31 Aa. 
         [0072]    Hereinafter, specific Examples are described. 
       Example 1 
       [0073]    The electrode pad  21   a  was formed on the circuit formed surface  21 A of the semiconductor chip  21  with a film thickness of 10 μm by electrolytic plating of a Cu film. The electrode pad  11   a  was formed on the mounting surface  11 A (fast principal surface) of the circuit board  11  also with a film thickness of 10 μm by electrolytic plating of a Cu film. Then, the semiconductor chip  21  was mounted on the circuit board  11  by reflowing the solder bump  31 A at a temperature of 139° C. in a nitrogen gas atmosphere corresponding to the process of  FIG. 3A  using a Sn—Bi solder containing a Bi composition in a proportion of 40 wt % to 70 wt % and having a substantially eutectic composition as the solder bump  31 Aa. 
         [0074]    Furthermore, using the electrode pad  21   a  as an anode and the electrode pad  11   a  as a cathode, the direct current I was applied to the solder bump  31 A from the anode  21   a  side to the cathode  11   a  side in that state over 5 hours, in other words, an electron flow e −  from the cathode  11   a  side to the anode  21   a  side was applied. In this experiment, the solder bump  31 Aa was not intentionally heated from the outside during the electrification. 
         [0075]    One obtained by such an experiment is the solder bump  31 A having the layer organization illustrated above in  FIG. 5B  in which segregation of Bi and Sn occurred. 
         [0076]    The semiconductor device  20  in which the semiconductor chip  21  was flip-chip mounted on the circuit board  11  thus obtained was confirmed for electrical connection, and then was subjected to 500 cycles of a temperature cycle test at temperatures between −5° C. and +125° C. Then, it was confirmed that an increase in resistance of the connecting portions was suppressed to 10% or lower by the solder bumps  31 A. Moreover, the same semiconductor device  20  was allowed to stand in an environment where the temperature was 121° C. and the humidity was 85% for 1000 hours, and then the resistance of the connecting portions was investigated. Then, it was confirmed that an increase in resistance was 10% or lower. 
       Example 2 
       [0077]    The electrode pad  21   a  was formed on the circuit formed surface  21 A of the semiconductor chip  21  with a film thickness of 10 μm by electrolytic plating of a Cu film. The electrode pad  11   a  was formed on the mounting surface  11 A of the circuit board  11  also with a film thickness of 10 μm by electrolytic plating of a Cu film. A flux was applied to the surface of the electrode pads  21   a  and  11   a,  and then the semiconductor chip  21  was mounted on the circuit board  11  by reflowing the solder bump  31 A at a temperature of 139° C. in a nitrogen gas atmosphere corresponding to the process of  FIG. 3A  using a Sn—Bi solder containing a Bi composition in a composition of 40 wt % to 70 wt % and having a substantially eutectic composition as the solder bump  31 Aa. 
         [0078]    Furthermore, using the electrode pad  21   a  as an anode and the electrode pad  11   a  as a cathode, the direct current I was applied to the solder bump  31 A from the anode  21   a  side to the cathode  11   a  side in that state over 5 hours, in other words, an electron flow e −  was applied from the cathode  11   a  side to the anode  21   a  side. In this experiment, the temperature of the solder bump  31 Aa was increased to a temperature of 100° C. or higher and 139° C. or lower, which was the original melting point, by heating from the outside during the electrification. 
         [0079]    One obtained by such an experiment is the solder bump  31 A having the layer organization illustrated above in  FIG. 5C  in which segregation of Bi and Sn occurred. 
         [0080]    The semiconductor device  20  in which the semiconductor chip  21  was flip-chip mounted on the circuit board  11  thus obtained was confirmed for electrical connection, and then was subjected to 500 cycles of a temperature cycle test at temperatures between −25° C. and +125° C. Then, it was confirmed that an increase in resistance of the connecting portions was suppressed to 10% or lower by the solder bumps  31 A. Moreover, the same semiconductor device  20  was allowed to stand in an environment where the temperature was 121° C. and the humidity was 85% for 1000 hours, and then the resistance of the connecting portions was investigated. Then, it was confirmed that an increase in resistance was 10% or lower. 
       Example 3 
       [0081]    Thus, in this embodiment, copper (Cu) can be used as the electrode pads  21   a  and  11   a.  However, in addition thereto, other metal elements forming an intermetallic compound with Sn, such as, nickel (Ni), can also be used. 
         [0082]    The electrode pad  21   a  was formed on the circuit formed surface  21 A of the semiconductor chip  21  with a film thickness of 10 μm by electrolytic plating of a nickel (Ni) film. The electrode pad  11   a  was formed on the mounting surface  11 A of the circuit board  11  also with a film thickness of 10 μm by electrolytic plating of a nickel film. A flux was applied to the surface of the electrode pads  21   a  and  11   a,  and then the semiconductor chip  21  was mounted on the circuit board  11  reflowing the solder bump  31 A at a temperature of 139° C. in a nitrogen gas atmosphere corresponding to the process of  FIG. 3A  using a Sn—Bi solder containing a Bi composition in a proportion of 40 wt % to 70 wt % and having a substantially eutectic composition as the solder bump  31 Aa. 
         [0083]    Furthermore, using the electrode pad  21   a  as an anode and the electrode pad  11   a  as a cathode, the direct current I was applied to the solder bump  31 A from the anode  21   a  side to the cathode  11   a  side in that state over 5 hours, in other words, an electron flow e −  was applied from the cathode  11   a  side to the anode  21   a  side. 
         [0084]    The semiconductor device  20  in which the semiconductor chip  21  was flip-chip mounted on the circuit board  11  thus obtained was confirmed for electrical connection, and then was subjected to 500 cycles of a temperature cycle test at temperatures between −25° C. and +125° C. Then, it was confirmed that an increase in resistance of the connecting portions was suppressed to 10% or lower by the solder bumps  31 A. Moreover, the same semiconductor device  20  was allowed to stand in an environment where the temperature was 121° C. and the humidity was 85% for 1000 hours, and then the resistance of the connecting portions was investigated. Then, it was confirmed that an increase in resistance was 10% or lower. 
       Example 4 
       [0085]    As described above, in this embodiment, although not only copper but nickel may be used as the electrode pads  21   a  and  11   a,  other metal elements forming an intermetallic compound with Sn, e.g., antimony (Sb), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), cobalt (Co), and the like may be used. 
         [0086]    The electrode pad  21   a  was formed on the circuit formation surface  21 A of the semiconductor chip  21  with a film thickness of 3 to 4 μm by electrolytic plating of a palladium (Pd) film. 
         [0087]    The electrode pad  11   a  was formed on the mounting surface  11 A of the circuit board  11  also with a film thickness of 3 to 4 μm by electrolytic plating of a palladium film. A flux was applied to the surface of the electrode pads  21   a  and  11   a,  and then the semiconductor chip  21  was mounted on the circuit board  11  by reflowing the solder bump  31 A at a temperature of 139° C. in a nitrogen gas atmosphere corresponding to the process of  FIG. 3A  using a Sn—Bi solder containing a Bi composition in a proportion of 40 wt % to 70 wt % and having a substantially eutectic composition as the solder bump  31 Aa. 
         [0088]    In this embodiment, an Sn—Bi alloy layer having a Sn concentration higher than that of the initial composition may also be formed as the second intermediate region  31   d  as illustrated as  FIG. 6  by reducing the current density during electrification or by reducing the electrification time. 
         [0089]    Furthermore, using the electrode pad  21   a  as an anode and the electrode pad  11   a  as a cathode, the direct current I was applied to the solder bump  31 A from the anode  21   a  side to the cathode  11   a  side in that state, in other words, an electron flow e −  was applied from the cathode  11   a  side to the anode  21   a  side over 3 hours. 
         [0090]    The semiconductor device  20  in which the semiconductor chip  21  was flip-chip mounted on the circuit board  11  thus obtained was confirmed for electrical connection, and then was subjected to 500 cycles of a temperature cycle test at temperatures between −25° C. and +125° C. Then, it was confirmed that an increase in resistance of the connecting portion was suppressed to 10% or lower by the solder bump  31 A. Moreover, the same semiconductor device  20  was allowed to stand in an environment where the temperature was 121° C. and the humidity was 85% for 1000 hours, and then the resistance of the connecting portion was investigated. Then, it was confirmed that an increase in resistance was 10% or lower. 
         [0091]    In this embodiment, the direction of applying the direct current is not limited to the direction from the electrode pad  21   a  to the electrode pad  11   a  as illustrated as  FIG. 3B  and may also be set to the direction from the electrode pad  11   a  to the electrode pad  21   a  illustrated as  FIG. 3C . In this case, the electrode pad  11   a  serves as an anode and the electrode pad  21   a  serves as cathode and, in the solder bump  31 A, a structure was formed such that the first intermediate region  31   c  was formed adjacent to the second interface layer  31   b  and the second intermediate region  31   d  was formed adjacent to the first interface layer  31   a  as described above with reference to  FIG. 2B . 
       Second Embodiment 
       [0092]    Hereinafter, a method for manufacturing the semiconductor device  20  according to a second embodiment is described with reference to  FIG. 7A  to  FIG. 7D ,  FIG. 8A  to  FIG. 8D ,  FIG. 9A ,  FIG. 9B ,  FIG. 10A ,  FIG. 10B , and  FIG. 11A  to  FIG. 11D . 
         [0093]    Referring to  FIG. 7A , on the circuit formed surface  21 A of the semiconductor chip  21 , a thin copper film or nickel film  21   s  is formed by a sputtering method, for example, as a seed layer for electrolytic plating with a film thickness of 50 nm to 200 nm. Furthermore, as illustrated as  FIG. 7B , a resist film R 1  having an opening portion R 1 A corresponding to the electrode pad  21   a  to be formed is formed on the seed layer  21   s.    
         [0094]    Then, by immersing the structure of  FIG. 7B  in an electrolytic plating bath of copper or nickel, and performing electrolytic plating using the seed layer  21   s  as an electrode, the electrode pad  21   a  containing copper or nickel is formed on the seed layer  21   s  corresponding to the opening portion R 1 A with a film thickness of 1 μm to 5 μm, for example, as illustrated as  FIG. 7C . 
         [0095]    Then, as illustrated as  FIG. 7D , by removing the resist film R 1 , the structure is obtained in which the electrode pad  21   a  is formed on the seed layer  21   s  covering the circuit formed surface  21 A of the semiconductor chip  21 . 
         [0096]    In contrast, a thin copper film or nickel film  11   s  is formed with a film thickness of 50 nm to 200 nm as a seed layer for electrolytic plating by a sputtering method, for example, on the mounting surface  11 A of the circuit board  11  as illustrated as  FIG. 8A . Then, as illustrated as  FIG. 8B , on the seed layer  11   s,  a resist film R 2  having an opening portion R 2 A corresponding to the electrode pad  11   a  to be formed is formed. 
         [0097]    By immersing the structure of  FIG. 8B  in an electrolytic plating bath of copper or nickel, and performing electrolytic plating using the seed layer  11   s  as an electrode, the electrode pad  11   a  containing copper or nickel is formed on the seed layer  11   s  corresponding to the opening portion R 2 A with a film thickness of 1 μm to 5 μm, for example, as illustrated as  FIG. 8C . 
         [0098]    Then, as illustrated as  FIG. 8D , by removing the resist film R 2 , the structure is obtained in which the electrode pad  11   a  is formed on the seed layer  11   s  covering the mounting surface  11 A of the circuit board  11 . 
         [0099]    Then, in this embodiment, as illustrated in  FIG. 8E , a resist film R 3  is formed on the structure of  FIG. 8D , and then the resist film R 3  is exposed and developed to form a resist pattern R 3 A as illustrated as  FIG. 8F , so that the resist pattern R 3 A protects a portion corresponding to the wiring pattern  11   b  formed on the mounting surface  11 A of the circuit board  11  previously described with reference to  FIG. 1C . 
         [0100]    Then, as illustrated as  FIG. 9A , a solder bump  31 Aa containing a Sn—Bi alloy and having an initial composition closer to the eutectic composition, for example, is supported on the electrode pad  21   a  in the structure of  FIG. 7D  through a flux layer. Then, the semiconductor chip  21  in which the solder bump  31 Aa is supported on the electrode pad  21   a  as described above is placed on the circuit board  11  in such a manner that the circuit formed surface  21 A faces the mounting surface  11 A of the circuit board  11 , and the solder bump  31 Aa is abutted on the electrode pad  11   a  on the mounting surface  11 A. 
         [0101]    Then, the solder bump  31 Aa of the initial composition is reflowed at a temperature of 139° C. in the state, and the semiconductor chip  21  is mounted on the circuit board  11  through the solder bump  31 Aa. 
         [0102]    Next, as illustrated as  FIG. 9B , a direct-current power supply  35  is connected between the seed layer  21   s  and the seed layer  11   s,  and then the direct current I is applied to the solder bump  31 Aa from the electrode pad  21   a  as an anode to the electrode pad  11   a  as a cathode, in other words, an electron flow e −  is applied from the electrode pad  11   a  as a cathode to the electrode pad  21   a  as an anode. 
         [0103]    As a result, as previously described with reference to  FIG. 3A  and  FIG. 3B , Bi concentrates to the electrode pad  21   a,  i.e., a side near the anode, in the solder bump  31 Aa of the initial composition to form the first intermediate region  31   c,  and Sn concentrates to the electrode pad  11   a,  i.e., a side near the cathode, to form the second intermediate region  31   d,  so that the solder bump  31 Aa of the initial composition changes to the solder bump  31 A. 
         [0104]    When the direction of the direct current I is reversed in the process of  FIG. 9B , the structure previously described with reference to  FIG. 2B  is obtained in which the second intermediate region  31   d  is formed adjacent to the first interface layer  31   a  and the first intermediate region  31   c  is formed adjacent to the second interface layer  31   b.    
         [0105]    Next, as illustrated as  FIG. 9C , the structure of  FIG. 9B  is immersed in an etchant  37 , for example, containing potassium hydrogensulfate as the main ingredients, for example, for 1 minute. Thus, the seed layer  21   s  and a portion of the seed layer  11   s  which is not protected by the resist pattern R 3 A are removed by etching. This etching is carried out only for removing the thin seed layers  21   s  and  11   s,  and the thick electrode pads  21   a  and  11   a  are not substantially affected. 
         [0106]    After pulling up from the etchant  37 , the resist pattern R 3 A is removed by, for example, a peeling liquid or the like, ashing in oxygen plasma, or the like to complete the semiconductor device  20  of the configuration in which the semiconductor chip  21  is electrically and mechanically connected onto the circuit board  11  through the solder bump  31 A and the predetermined wiring pattern  11   b  is formed on the mounting surface  11 A of the circuit board  11 . 
         [0107]    In this embodiment, any one of the processes of  FIG. 7A  to  FIG. 7D  and any one of the processes of  FIG. 8A  to  FIG. 8F  may be performed first, and may be simultaneously performed at the same time. 
         [0108]    Although the same wiring pattern is also formed on the back surface  11 B of the circuit board  11  in this embodiment, the explanation is omitted. 
         [0109]    According to the above-described embodiments, by joining a semiconductor chip and a circuit board or a first connection member and a second connection member by reflowing solder bumps containing a Sn—Bi alloy, and then applying a direct current to the solder bumps, a region where the Bi concentration is high and a region where the Sn concentration is high may be formed in such a manner as to be isolated from each other in the solder bumps. Therefore, the melting temperature of the solder bumps may be made higher than the initial melting temperature. 
       Third Embodiment 
       [0110]      FIG. 10  is a cross sectional view illustrating the outline of a semiconductor device  40  according to a third embodiment. 
         [0111]    Referring to  FIG. 10 , the semiconductor device  40  has a package substrate  41  having principal surfaces  41 A and  41 B forming the front surface and the back surface, respectively. An interposer  42  mounted on the principal surface  41 A of the package substrate  41  by Sn—Bi solder bumps  41   a,  and the interposer  42  is correspondent to the circuit board  11  in the embodiments above. Additionally, a large number of the semiconductor chips  21  mounted on the interposer  42  by solder bump arrays  431 A each containing the solder bumps  31 A, in which a large number of circuit patterns  42 Ckt are formed by a multilayer interconnection structure in the interposer  42 . Further, on the principal surface  41 B of the package substrate  41 , different solder bumps  41   b  for mounting on a system board or the like are formed. 
         [0112]    Further, although not illustrated, circuits by a multilayer interconnection structure are formed on the principal surfaces  41 A and  41 B of the package substrate  41 . 
         [0113]    When assembling such a semiconductor device  40 , in order to reduce thermal stress to the semiconductor chips  21 , the semiconductor chips  21  are mounted on the interposer  42  using a Sn—Bi solder having a usual eutectic composition in the solder bump arrays  431 A. Thereafter, when the interposer  42  is mounted on the package substrate  41 , or, furthermore, when the package substrate  41  is mounted on a system board or the like of an electronic device, later, a problem arises in that the solder bumps constituting the solder bump arrays  431 A re-malt with the heat treatment for reflowing the solder bumps  41   a  and  41   b.    
         [0114]    In order to solve the problem, in this embodiment, when the semiconductor chip  21  is mounted on the interposer  42 , a direct current is applied to the solder bump  31 A to isolate the bump  31 A to a region abundant in Bi, i.e., the first intermediate region  31   c,  and a region abundant in Sn, i.e., the second intermediate region  31   d,  as described in the embodiments above. Therefore, the melting temperature of the entire solder bump  31 A increases from the initial temperature in mounting, e.g., 139° C., to 215° C. or higher. Therefore, even when reflowing the solder bump  41   a  or  41   b  later, the solder bumps  31 A does not re-melt. 
         [0115]    Similarly, in this embodiment, also with respect to the solder bump  41   a,  the interposer  42  is mounted on the package substrate  41 , and then a direct current is applied to thereby isolate each solder bump  41   a  to a region abundant in Bi and a region abundant in Sn therein. Therefore, the melting temperature of the solder bump  41   a  becomes higher than the temperature during reflow, so that a problem of re-melting or the like of the solder bump  41   a  does not occur when mounting the package substrate  41 . Also when the semiconductor device  40  is subjected to a thermal cycle test and a high temperature exposure test, the connection does not become poor. 
         [0116]    Thus, according to this embodiment, in the configuration in which a large number of components are stacked while mounting by solder bumps, the melting temperature of the solder bumps may be increased after mounting, so that a high-reliable electronic device may be manufactured at a high yield. 
       Fourth Embodiment 
       [0117]      FIG. 11  is a cross sectional view illustrating the configuration of a semiconductor device  60  according to a fourth embodiment. 
         [0118]    Referring to  FIG. 11 , the semiconductor device  60  has a circuit board  61  having principal surfaces  61 A and  61 B, in which a semiconductor chip  62  is joined onto the principal surface  61 A of the circuit board  61  in a face-up state through a resin layer  62 C, i.e., the circuit formed surface on which a semiconductor integrated circuit is formed is the upper side, in other words facing a side opposite to the circuit board  61 . 
         [0119]    Furthermore, the semiconductor chip  21  is mounted on the semiconductor chip  62  in a face-down state through the solder bump array  431 A described above, and the semiconductor chip  62  is electrically connected to the circuit pattern formed on the principal surface  61 A of the circuit board  61  by bonding wires  62 A and  62 B. 
         [0120]    On the principal surface  61 A, the semiconductor chips  62  and  21  are sealed together with the bonding wires  62 A and  62 B with a sealing resin  63  and a large number of through vias  61   t  are formed in the circuit board  61 . The circuit pattern on the principal surface  61 A is electrically connected to the circuit pattern formed on the principal surface  61 B through the through vias  61   t.    
         [0121]    On the principal surface  61 B, a large number of solder bumps  61   b  are formed. The circuit board  61  is mounted on a system board, for example, of various electronic devices, such as a server, through the solder bumps  61   b.    
         [0122]    Also in this embodiment, the solder bumps  31 A constituting the solder bump array  431 A are electrified after reflowing at a low temperature of 139° C. as described above, and, as a result, the melting temperature increases to 215° C. or higher, for example. 
         [0123]    Therefore, even when the semiconductor device  60  is mounted on another substrate by reflowing the solder bumps  61   b  and even when the electronic device thus formed is subjected to various thermal cycle tests and high temperature exposure tests, the solder bumps  31 A constituting the solder bump array  431 A do not re-melt. 
         [0124]    Thus, according to this embodiment, a high-reliable semiconductor device may be manufactured at a high yield. 
       Fifth Embodiment 
       [0125]    The semiconductor devices according to various embodiments described above may be variously applied, e.g., from application to electronic devices for so-called high-end use, such as a server  70  having a system board  71 , as illustrated as  FIG. 12  to application to a circuit wiring board of electronic devices for popular use, such as cellular phones and digital cameras. 
         [0126]    Referring to  FIG. 12 , the semiconductor device  40  of  FIG. 10  or the semiconductor device  60  of  FIG. 11 , for example, is flip-chip mounted on the system board  71  together with a memory module  71 B and the like through the solder bumps  41   b  or  61   b  in a state where a heat dissipation member  71 A is supported. 
         [0127]    Preferable embodiments are described above but embodiments are not limited to specific embodiments and may be variously modified and altered within the scope of the claims. 
         [0128]    All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.