Abstract:
A three-dimensional package and a method of making the same including providing a wafer; forming at least one blind hole in the wafer; forming an isolation layer on the side wall of the blind hole; forming a conductive layer on the isolation layer; forming a dry film on the conductive layer; filling the blind hole with metal; removing the dry film, and patterning the conductive layer; removing a part of the metal in the blind hole to form a space; removing a part of the second surface of the wafer and a part of the isolation layer, to expose a part of the conductive layer; forming a solder on the lower end of the conductive layer, the melting point of the solder is lower than the metal; stacking a plurality of the wafers, and performing a reflow process; and cutting the stacked wafers, to form three-dimensional packages.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a package and a method of making the same, and more particularly to a three-dimensional package and a method of making the same. 
     2. Description of the Related Art 
     Referring to  FIG. 1 , it shows a schematic view of a three-dimensional package before reflow disclosed in U.S. Pat. No. 4,499,655. The conventional three-dimensional package  1  comprises a first unit  10  and a second unit  20 . The first unit  10  comprises a first wafer  11 , at least one first hole  12 , a first conductive layer  13  and a first solder  14 . The first wafer  11  has a first surface  111  and a second surface  112 . The first surface  111  has at least one first pad (not shown) and a first protection layer  113  exposing the first pad. The first hole  12  penetrates the first wafer  11 . The first conductive layer  13  is disposed on the side wall of the first hole  12  and covers the first pad and the first protection layer  113 . The first solder  14  is disposed in the first hole  12  and is electrically connected to the first pad via the first conductive layer  13 . The upper end of the first solder  14  extends above the first surface  111  of the first wafer  11 , and the lower end extends below the second surface  112  of the first wafer  11 . 
     The second unit  20  is stacked on the first unit  10 . The second unit  20  comprises a second wafer  21 , at least one second hole  22 , a second conductive layer  23  and a second solder  24 . The second wafer  21  has a first surface  211  and a second surface  212 . The first surface  211  has at least one second pad (not shown) and a second protection layer  213  exposing the second pad. The second hole  22  penetrates the second wafer  21 . The second conductive layer  23  is disposed on the side wall of the second hole  22  and covers the second pad and the second protection layer  213 . The second solder  24  is disposed in the second hole  22  and is electrically connected to the second pad via the second conductive layer  23 . The upper end of the second solder  24  extends above the first surface  211  of the second wafer  21 , and the lower end of the second solder  24  extends below the second surface  212  of the second wafer  21 . The lower end of the second solder  24  is aligned with and contacts the upper end of the first solder  14 . After performing a reflow process, the first unit  10  and the second unit  20  are joined to form a conventional three-dimensional package  1 , as shown in  FIG. 2 . 
     In the conventional three-dimensional package  1 , the first solder  14  and the second solder  24  are formed by disposing the first wafer  11  and the second wafer  21  above a solder bath, and the solder enters the first hole  12  and the second hole  22  according to the capillary phenomenon so as to form the first solder  14  and the second solder  24 . 
     The disadvantages of the conventional three-dimensional package  1  are described as follows. As the first solder  14  and the second solder  24  are formed according to the capillary phenomenon, the upper and the lower ends of the foregoing solders are in a hemispherical shape ( FIG. 1 ). As such, when the first unit  10  and the second unit  20  are aligned and joined, alignment becomes more difficult and the joining between the first unit  10  and the second unit  20  after reflow is not stable. Moreover, after the joining of the first unit  10  and the second unit  20 , the overall height cannot be effectively reduced due to the excess hemispherical solders. 
     Therefore, it is necessary to provide a three-dimensional package and a method of making the same to solve the above problems. 
     SUMMARY OF THE INVENTION 
     The main objective of the invention is to provide a method of making a three-dimensional package, which comprises the following steps: 
     (a) providing a wafer, having a first surface and a second surface, the first surface having at least one pad and a protection layer exposing the pad; 
     (b) forming at least one blind hole on the first surface of the wafer; 
     (c) forming an isolation layer on the side wall of the blind hole; 
     (d) forming a conductive layer covering the pad, the protection layer and the isolation layer; 
     (e) forming a dry film on the conductive layer, wherein the dry film has an opening at the position corresponding to the blind hole; 
     (f) filling the blind hole with a metal; 
     (g) removing the dry film and patterning the conductive layer; 
     (h) removing a part of the metal in the blind hole to form a space; 
     (i) removing a part of the second surface of the wafer and a part of the isolation layer, so as to expose a part of the conductive layer; 
     (j) forming a solder on the lower end of the conductive layer, wherein the melting point of the solder is lower than that of the metal; 
     (k) stacking a plurality of the wafers, and performing a reflow process; and 
     (l) cutting the stacked wafers, so as to form a plurality of three-dimensional packages. 
     As such, the lower end of the conductive layer is exposed below the second surface of the wafer. Therefore, during the reflow process after stacking, the lower end of the conductive layer and the solder thereon are inserted into the space of the lower wafer, so as to enhance the joint between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional package after joining. 
     Another objective of the present invention is to provide a three-dimensional package structure, which has a first unit and a second unit. The first unit comprises a first wafer, at least one first hole, a first isolation layer, a first conductive layer, a first metal and a first solder. 
     The first wafer has a first surface and a second surface. The first surface has at least one first pad and a first protection layer exposing the first pad. The first hole penetrates the first wafer. The first isolation layer is disposed on the side wall of the first hole. The first conductive layer covers the first pad, a part of the first protection layer, and the first isolation layer. The lower end of the first conductive layer extends below the second surface of the first wafer. The first metal is disposed in the first hole, and is electrically connected to the first pad via the first conductive layer. The first solder is disposed on the first metal in the first hole, wherein the melting point of the first solder is lower than that of the first metal. 
     The second unit is stacked on the first unit. The second unit comprises a second wafer, at least one second hole, a second isolation layer, a second conductive layer, a second metal and a second space. The second wafer has a first surface and a second surface. The first surface has at least one second pad and a second protection layer exposing the second pad. The second hole penetrates the second wafer. The second isolation layer is disposed on the side wall of the second hole. 
     The second conductive layer covers the second pad, a part of the second protection layer and the second isolation layer. The lower end of the second conductive layer extends below the second surface of the second wafer and contacts the upper end of the first solder. The second metal is disposed in the second hole and is electrically connected to the second pad via the second conductive layer. The second space is disposed on the second metal in the second hole. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a schematic view of the three-dimensional package before reflow disclosed in U.S. Pat. No. 4,499,655; 
         FIG. 2  shows a schematic view of the three-dimensional package after reflow disclosed in U.S. Pat. No. 4,499,655; 
         FIG. 3  shows a schematic flow chart of the method for making a three-dimensional package according to the first embodiment of the present invention; 
         FIGS. 4 to 17  show the schematic views of each step of the method for making a three-dimensional package according to the first embodiment of the present invention; 
         FIG. 18  shows a schematic flow chart of the method for making a three-dimensional package according to the second embodiment of the present invention; 
         FIGS. 19 to 20  show the schematic views of a part of the steps of the method for making a three-dimensional package according to the second embodiment of the present invention; and 
         FIG. 21  shows a cross-sectional view of the three-dimensional package according to the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to  FIG. 3 , it shows a schematic flow chart of the method for making a three-dimensional package according to the first embodiment of the present invention. Referring to  FIGS. 4 to 17 , the schematic views of each step of the method for making a three-dimensional package according to the first embodiment of the present invention are shown. First, referring to  FIGS. 3 and 4 , as shown in step S 301 , a wafer  31  is provided. The wafer  31  has a first surface  311  and a second surface  312 . The first surface  311  has at least one pad  32  and a protection layer  33  exposing the pad  32 . 
     Then, referring to  FIGS. 3 and 5 , as shown in step S 302 , at least one blind hole  34  is formed in the first surface  311  of the wafer  31 . In the present embodiment, the blind hole  34  is disposed beside the pad  32 . However, in other applications, the blind hole  34  can penetrate the pad  32 . 
     Next, referring to  FIGS. 3 and 6 , as shown in step S 303 , an isolation layer  35  is formed on the side wall of the blind hole  34 . 
     Afterward, referring to  FIGS. 3 and 7 , as shown in step S 304 , a conductive layer  36  is formed to cover the pad  32 , the protection layer  33 , and the isolation layer  35 . The conductive layer  36  is made of Ti, Cu, Cu/Ti alloy, or other metals. 
     Then, referring to  FIGS. 3 and 8 , as shown in step S 305 , a dry film  37  is formed on the conductive layer  36 . The dry film  37  has an opening  371  at the position corresponding to the blind hole  34 . 
     After that, referring to  FIGS. 3 and 9 , as shown in step S 306 , the blind hole  34  is filled with a metal  38  (e.g., copper). In the present embodiment, the blind hole  34  is filled with the metal  38  by plating. However, it should be understood that the blind hole  34  can be filled with the metal  38  by other manners. 
     Then, referring to  FIGS. 3 and 10 , as shown in step S 307 , the dry film  37  is removed, and the conductive layer  36  is patterned. 
     Afterward, referring to  FIGS. 3 and 11 , as shown in step S 308 , a part of the upper end of the metal  38  in the blind hole  34  is removed, so as to form a space  39 . In the embodiment, a part of the upper end of the metal  38  in the blind hole  34  is removed by etching. It should be understood that a part of the upper end of the metal  38  in the blind hole  34  is can be removed by other manners. 
     Then, as shown in step S 309 , a part of the second surface  312  of the wafer  31  and a part of the isolation layer  35  are removed to expose a part of the conductive layer  36 . Referring to  FIG. 12 , in the present embodiment, the second surface  312  of the wafer  31  is ground by means of backside grinding until the second surface  312  and the lower end of the isolation layer  35  are at the same level, i.e., the lower end of the isolation layer  35  is exposed on the second surface  312 . Then, the second surface  312  of the wafer  31  and the lower end of the isolation layer  35  are etched to expose the lower end of the conductive layer  36 . At this moment, the lower end of the conductive layer  36  extends below the second surface  312  of the wafer  31 , as shown in  FIG. 13 . However, it should be understood that in other applications, the second surface  312  of the wafer  31  can be directly etched to expose the lower end of the conductive layer  36 , without using the backside grinding method. 
     Afterward, referring to  FIGS. 3 and 14 , preferably, as shown in step S 310 , a barrier layer  40  is formed on the lower end of the conductive layer  36 , and covers the lower end of the exposed conductive layer  36 . The barrier layer  40  is Ni, Cr, Cr/Cu alloy, or other metals. It should be understood that this step is optional. 
     Next, referring to  FIGS. 3 and 15 , as shown in step S 311 , a solder  41  is formed on the lower end of the conductive layer  36 . The material of the solder  41  is different from the metal  38 . The material of the solder  41  includes but is not limited to Sn/Pb alloy, and the melting point thereof is lower than that of the metal  38 . The solder  41  is attached to the barrier layer  40  or the lower end of the exposed conductive layer  36 . 
     Then, referring to  FIGS. 3 and 16 , as shown in step S 312 , a plurality of the wafers  31  are stacked. The solder  41  of the upper wafer  31  is aligned to the space  39  of the conductive layer  36  of the lower wafer  31 . 
     Finally, referring to  FIGS. 3 and 17 , as shown in step S 313 , the reflow process is performed to make the wafers  31  joined by welding the conductive layer  36 , the solder  41  and the metal  38 . Finally, as shown in step S 314 , the stacked wafer  31  is cut to form a plurality of three-dimensional package structures  42 . Preferably, as shown in step S 315 , at least one solder ball  43  is formed below the three-dimensional package structure  42 . The solder ball  43  is disposed on the lower end of the conductive layer  36  in the lower wafer  31 . It should be understood that this step is optional. 
     Referring to  FIG. 18 , it shows a schematic flow chart of the method for making a three-dimensional package structure according to the second embodiment of the present invention. The steps S 401  to S 411  are identical to steps S 301  to S 311  of the first embodiment. The difference between this embodiment and the first embodiment is described as follows. Referring to  FIGS. 18 and 19 , as shown in step S 412 , the wafer  31  is cut to form a plurality of units  44 ,  45 . Then, in step S 413  the units  44 ,  45  are stacked, wherein the solder  41  of the upper unit  44  is aligned with the space  39  of the conductive layer  36  of the lower unit  45 . Finally, in step S 414  the reflow process is performed to form a plurality of three-dimensional package structures  42 , as shown in  FIG. 20 . The three-dimensional package structure  42  ( FIG. 20 ) made according to this embodiment is identical to the three-dimensional package structure  42  ( FIG. 17 ) made according to the first embodiment. 
     Preferably, in the step S 415 , at least one solder ball  43  is formed below the three-dimensional package structure  42 . The solder ball  43  is disposed on the lower end of the conductive layer  36  in the lower wafer  31 . It should be understood that this step is optional. 
     Referring to  FIG. 21 , it shows a cross-sectional view of the three-dimensional package structure according to the present invention. The three-dimensional package structure  5  in this figure is identical to the three-dimensional package structure  42  in  FIGS. 17 and 20 . However, for the convenience of illustration, the identical elements are identified by different reference numbers. The three-dimensional package structure  5  comprises a first unit  50  and a second unit  60 . The first unit  50  comprises a first wafer  51 , at least one first hole  52 , a first isolation layer  53 , a first conductive layer  54 , a first metal  55  and a first solder  56 . 
     The first wafer  51  is a wafer or a chip, and has a first surface  511  and a second surface  512 . The first surface  511  has at least one first pad  513  and a first protection layer  514  exposing the first pad  513 . The first hole  52  penetrates the first wafer  51 . In the present embodiment, the first hole  52  is disposed beside the first pad  513 . Alternatively, the first hole  52  can penetrate the first pad  513 . 
     The first isolation layer  53  is disposed on the side wall of the first hole  52 . The first conductive layer  54  covers the first pad  513 , a part of the first protection layer  514  and the first isolation layer  53 . The lower end of the first conductive layer  54  extends below the lower end of the second surface  512  of the first wafer  51 . Preferably, the first unit  50  further comprises a first barrier layer (not shown) covering the lower end of the first conductive layer  54 . 
     The first metal  55  (e.g., copper) is disposed in the first hole  52  and is electrically connected to the first pad  513  via the first conductive layer  54 . The first solder  56  is disposed on the first metal  55  in the first hole  52 . The material of the first solder  56  is different from the first metal  55 . The material of the first solder  56  includes but is not limited to Sn/Pb alloy, and the melting point thereof is lower than that of the first metal  55 . 
     The second unit  60  is stacked above the first unit  50 . The second unit  60  comprises a second wafer  61 , at least one second hole  62 , a second isolation layer  63 , a second conductive layer  64 , a second metal  65  and a second space  66 . The second wafer  61  is a wafer or a chip with a first surface  611  and a second surface  612 . The first surface  611  has at least one second pad  613  and a second protection layer  614  exposing the second pad  613 . The second hole  62  penetrates the second wafer  61 . In the present embodiment, the second hole  62  is disposed beside the second pad  613 . However, in other applications, the second hole  62  can penetrate the second pad  613 . 
     The second isolation layer  63  is disposed on the side wall of the second hole  62 . The second conductive layer  64  covers the second pad  613 , a part of the second protection layer  614 , and the second isolation layer  63 . The lower end of the second conductive layer  64  extends below the second surface  612  of the second wafer  61  and contacts the upper end of the first solder  56 . Preferably, the second unit  60  further comprises a second barrier layer (not shown) covering the lower end of the second conductive layer  64 . 
     The second metal  65  is disposed in the second hole  62  and is electrically connected to the second pad  613  via the second conductive layer  64 . The second space  66  is disposed above the second metal  65 . Moreover, if desired, the second space  66  of the second hole  62  is filled with a second solder (not shown). Preferably, the three-dimensional package structure  5  further comprises at least one solder ball  43  disposed on the lower end of the first conductive layer  54 . 
     In the three-dimensional package structure  5 , the lower end of the second conductive layer  64  is exposed below the second surface  612  of the second unit  60 . Therefore, during the reflow process, the lower end of the second conductive layer  64  and the solder thereon are “inserted” into the space on the first metal  55 , so as to enhance the joint between the second conductive layer  64  and the first metal  55 . Further, the first hole  52  and the second hole  62  can be designed as a taper shape to enhance the joining. Moreover, the lower end of the second conductive layer  64  is inserted into the space on the first metal  55 , so the overall height of the three-dimensional package structure  5  after joining can be effectively reduced. 
     While several embodiments of the present invention have been illustrated and described, various modifications and improvements can be made by those skilled in the art. The embodiments of the present invention are therefore described in an illustrative but not restrictive sense. It is intended that the present invention may not be limited to the particular forms as illustrated, and that all modifications which maintain the spirit and scope of the present invention are within the scope as defined in the appended claims.