Abstract:
A distributed electrostatic discharge protection circuit includes a plurality of electrostatic discharge protection elements and a current balancing network connecting the plurality of electrostatic discharge protection elements. The current balancing network is configured in a return path of the distributed electrostatic discharge protection circuit such that during an electrostatic discharge (ESD) event, the circuit provides predefined current density within each of the electrostatic discharge protection elements.

Description:
BACKGROUND 
     The present disclosure relates to electrostatic discharge protection, and more specifically, to electrostatic discharge protection circuits with magnetically coupled differential inputs and outputs. 
     The input and output speed of integrated circuits (ICs) constantly increases with each respective new generation of chips. Input/output (I/O) pins of large ICs can exceed 4 Tb of data per second of aggregated data transfer. ICs tend to build up electrostatic charges. Consequently, ICs are routinely configured with electrostatic discharge (ESD) protection circuits to mitigate chip damage caused by electrostatic charge buildup. However, at higher data transfer rates, capacitance of ESD protection elements may exceed allowable limits. Unfortunately, ESD devices have not scaled to keep up with increases in IC speed. In some conventional approaches, T-coils have been used to cancel out a portion of the capacitance. However, this may not be sufficient for ultra-wide band ICs. 
     SUMMARY 
     According to some embodiments, a distributed electrostatic discharge protection circuit includes a plurality of electrostatic discharge protection elements and a current balancing network connecting the plurality of electrostatic discharge protection elements. The current balancing network is configured in a return path of the distributed electrostatic discharge protection circuit such that during an electrostatic discharge (ESD) event, the circuit provides predefined current density within each of the electrostatic discharge protection elements. 
     According to other embodiments, a method for electrostatic discharge protection may include configuring a plurality of electrostatic discharge protection elements in a current balancing network having a plurality of electrostatic discharge protection elements, and grounding the electrostatic discharge protection elements via a return path of a distributed electrostatic discharge protection circuit such that during an electrostatic discharge (ESD) event the circuit provides predefined current density within each of the electrostatic discharge protection elements. 
     According to yet other embodiments, an apparatus may include a distributed electrostatic discharge protection circuit. The circuit may include a plurality of electrostatic discharge protection elements, and a current balancing network connecting the plurality of electrostatic discharge protection elements. The current balancing network is configured in a return path of the distributed electrostatic discharge protection circuit such that during an electrostatic discharge (ESD) event the circuit provides predefined current density within each of the electrostatic discharge protection elements. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIG. 1  illustrates a circuit diagram of a T-coil known in the art; 
         FIG. 2  depicts a conventional distributed electrostatic discharge protection circuit known in the art; 
         FIG. 3  depicts an electrostatic discharge current distribution differential input/output in accordance with an exemplary embodiment; 
         FIG. 4  depicts an electrostatic discharge current distribution differential input/output with coupled micro T-coils in accordance with an exemplary embodiment; 
         FIG. 5  depicts a graph of current/voltage characteristics of SCRs in accordance with an exemplary embodiment; and 
         FIG. 6  depicts a centralized trigger circuit in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  illustrates a circuit diagram of a conventional T-coil circuit. As previously discussed, ESD devices have not scaled to keep up with increases in IC speeds of newer manufacturing technologies. In some conventional approaches, T-coils have been used to cancel out a portion of the capacitance. However, this may not be sufficient for ultra-wide band ICs. Conventional T-coil circuits (e.g., T-coil circuit depicted in  FIG. 1 ) may include two magnetically coupled coils  2 , which may be configured to tune out ESD-diode capacitance over a wide frequency range. In some conventional applications, conventional T-coil circuits may include two or more ESD diodes  3  that may be connected at the center tap of each magnetically coupled coil  2 . Accordingly, magnetically coupled coils  2  may help protect the termination  4  from some (but not all) ESD damage. However, at higher data transfer rates, conventional T-coils ESD protection may become less effective for device capacitance mitigation. In some instances, the frequency range for the circuit may be extended but may not work as well if termination  4  has a moderately high capacitive component. 
     Other conventional approaches may include the use of distributed ESD protection circuits such as the circuit depicted with respect to  FIG. 2 . Many ESD protection circuits may include a plurality of diodes  5 , which may be distributed across transmission lines  6 . In conventional distributed ESD circuits, the on-chip transmission lines  6  may experience transmission loss that may be large for higher transmission rate applications. 
     Other approaches have attempted to distribute current through stacked diodes and resistors. However the signal loss of the stacked resistors has been shown to be less than optimal. For example, ESD circuits may be highly dependent on frequency, as current balance may lose effectiveness when used with more than one frequency, as shown in the example in  FIG. 2 . 
     In yet other conventional approaches, transmission lines  6  may be intervened by silicon controlled resistors (SCRs)  7  in an effort to balance current. In some configurations most ESD current may flow through SCR 1 , and significantly less through SCR 2 . Even less ESD current may flow through SCR 3 . 
     Referring now to  FIG. 3 , an electrostatic discharge current distribution network  400  (hereafter “current distribution network  400 ”) is depicted, in accordance with an exemplary embodiment. As previously discussed, high speed I/Os are often differential in nature. Accordingly, in some aspects, it may be advantageous to introduce magnetic couplings to exploit the differential nature of the circuit. Referring now to  FIG. 3 , current distribution network  400  may include a plurality of magnetic couplings L 1  and L 1 ′, L 2  and L 2 ′, L 3  and L 3 ′, and L 4  and L 4 ′ (depicted as couplings  402 / 402 ′,  404 / 404 ′,  406 / 406 ′, and  408 / 408 ′, respectively). Couplings  402  and  402 ′ may be comprised of a pair of coils magnetically coupled to one another. Similarly, coupling  404  may be coupled with  404 ′,  406  with  406 ′, and  408  may be coupled with  408 ′, which may also be coil pairs. 
     Accordingly, couplings  402 - 408  may be configured to balance the load on current distribution network  400 . Network  400  may further include a plurality of SCRs  410 ,  412 ,  414 ,  410 ′,  412 ′, and  414 ′, which may be intervened by inductor coils L g1  and L g2  ( 416  and  418 , respectively), which balance ESD currents in the ESD protection elements. Accordingly, the inductors may be configured in at least one chain of inductors. The bottom side of inductors  416  and  418  are part of the ground return path for all SCRs. By adding couplings  402 - 408 , the effective size of the current distribution network  400  may be reduced by a factor of 2. 
     In other aspects, an ESD protection circuit such as current distribution network  400  may be optimal because the magnetic couplings (e.g., couplings  402 - 408 ), may not have a bypass path for pulse energy to bypass the ESD elements (e.g., load configurations). In contrast, when magnetic couplings are configured as single T-coils as in  FIG. 3 , the pulse energy may bypass the ESD elements. 
     In other aspects, the inductors may be configured to form a Chebyshev low-pass filter. 
       FIG. 4  depicts an electrostatic discharge current distribution differential input/output with coupled micro T-coils  500  (hereafter “network  500 ”), in accordance with an exemplary embodiment. As shown in  FIG. 4 , it may be advantageous to place a small differential T-coil on each ESD element along with a coupled capacitor, where the t-coil is magnetically coupled to the corresponding T-coil on the complimentary signal path. The following T-coil pairs may be magnetically coupled ( 502 / 502 ′,  504 / 504 ′,  506 / 506 ′,  510 / 510 ′, etc.). Network  500  may further include a plurality of bridge capacitors  520 / 520 ′,  521 / 521 ′, and  520 / 522 ′, as designed in conventional T-coil configurations. The T-coil pairs may couple in a direction shown by a dot at a respective end of each T-coil. Accordingly, the magnetic couplings may transfer part of the ESD pulse to complementary inputs, which may allow some reduction in SCR (diode) size. In some aspects this configuration may results in a capacitance reduction, and increased bandwidth throughput. 
     Central triggering for the SCR feature may be highly beneficial in some embodiments because the snapback in SCR current/voltage characteristic could prevent all other SCRs from triggering if one of the SCRs triggers early. This may be due in part to voltage decreases below triggering. In some aspects, triggering could be implemented similar to a SCR power clamp. Accordingly, trigger voltage may be sensed not only on the voltage supply, but also on the signal pin.  FIG. 5  depicts a current/voltage characteristic plot for SCRs, according to some exemplary embodiments. Central triggering for the SCR feature is shown with respect to the snapback in an SCR IV-characteristic. In some embodiments, central triggering could prevent all other SCRs from triggering if one triggers early, since the voltage decreases below triggering. 
     In some aspects, centralized triggering can be made by replacing a diode triggered SCR by a FET triggered SCR. Accordingly, the trigger circuit may detect a short pulse, similar to a clamp.  FIG. 6  depicts a centralized trigger circuit  700 , in accordance with some embodiments. According to some embodiments, centralized trigger circuit  700  may include a plurality of SCRs  702  in connection with the node to be protected from ESD. Accordingly, trigger circuit  700  can detect, at ESD sense input points  704 , a short pulse beyond the ESD detection threshold. 
     The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.