Abstract:
A delay circuit has a first delay line propagating an input pulse from stage to stage in one direction, a second delay line propagating the previous input pulse from stage to stage in the opposite direction and a comparator operative compare output potential levels of the stages incorporated in the first delay line with output potential levels of the stages incorporated in the second delay line so as to determine if any pair of output potentials are consistent in logic level with one another; when the output potentials are consistent with one another, an output timing signal is produced, and the pulse repetition period of the output timing signal is exactly half as long as that of the input pulse signal.

Description:
FIELD OF THE INVENTION 
     This invention relates to a delay circuit and, more particularly, to a pincer movement delay circuit for producing an output signal different in pulse repetition period from an input signal. 
     DESCRIPTION OF THE RELATED ART 
     The present inventor proposed a synchronous delay circuit in Japanese Patent Publication of Unexamined Application (JPA) No. 8-237091. The prior art synchronous delay circuit produces a timing signal at a half of clock repetition period of a clock signal. FIG. 1 illustrates the prior art delay circuit already proposed by the present inventor. 
     The delay circuit comprises a first delay line  1 , a second delay line  2  and a transfer circuit  3  connected between the first delay line  1  and the second delay line  2 . The first delay line  1  is implemented by a series of delay elements, and the second delay line  2  is implemented by two series combination of delay elements. The transfer circuit  3  includes transfer gates arranged in parallel. The transfer gates have respective input nodes connected to the delay elements of the first delay line I and respective output nodes selectively connected to the delay elements of the two series combinations. 
     A clock signal CLK 1  is supplied from an input terminal  4  to a signal receiving circuit  5 , and the signal receiving circuit  5  produces a clock signal CLK 2  from the clock signal CLK 1 . The clock signal CLK 2  is directly supplied to the transfer circuit  3  as a control signal CTL 1 , and is supplied through a delay circuit  6  to the first delay line  1 . 
     The first delay line  1  rightwardly propagates the clock signal CLK 2  through the delay elements. The transfer circuit  3  is responsive to the control signal CTL 1  so as to selectively transfer a group of clock signals CLK 2  from the delay elements of the first delay line  1  to the delay elements of the second delay line  2 . The second delay line  2  leftwardly propagates the group of clock signals CLK 2  through the delay elements, and an OR gate  7  produces an output clock signal CLK 3  from the group of clock signals CLK 2 . 
     The second delay line  2  is designed to introduce delay half as long as the delay introduced by the first delay line  1 . Each clock pulse CLK 2  proceeds to a certain point of the first delay line  1  during the clock repetition period, and the next clock pulse CLK 2  causes the transfer circuit  3  to transfer the clock pulse CLK 2  to one of the two series combinations of the second delay line  2 . Then, the clock pulse CLK 2  is output from the second delay line  2  at the mid timing of the clock period. For this reason, the prior art delay circuit requires the first delay line  1  and the second delay line  2  exactly designed to introduce the two kinds of delay, and the Japanese Patent Publication of Unexamined Application proposes to regulate the number of the delay elements to 2:1. In other words, the output timing of the clock signal CLK 3  is dependent on the circuit configuration of the first and second delay lines  1  and  2 . However, even if the delay elements are selected to 2:1, the layout of the delay lines ½ are not taken into account, and a certain layout does not make the two kinds of delay time 2:1. This means that the output timing of the clock signal CLK 3  is offset from the mid point of the clock repetition period. 
     SUMMARY OF THE INVENTION 
     It is therefore an important object of the present invention to provide a delay circuit, which accurately produces an output pulse at a target timing. 
     In accordance with one aspect of the present invention, there is provided a delay circuit for producing an output timing signal from an input signal, and the delay circuit comprises a first delay line having a first node group implemented by a plurality of first nodes connected in series and propagating the input signal from an initial node of the first node group toward a final node of the first node group, a second delay line having a second node group implemented by a plurality of second nodes connected in series, propagating the input signal from an initial node of the second node group toward a final node of the second node group causing the initial node to the final node of the first node group to be respectively paired with the final node to the initial node of the second node group so as to form a plurality of node pairs and a comparator connected to the plurality of node pairs, and comparing outputs of the plurality of node pairs to see whether the outputs of any one of the plurality of node pairs are consistent with each other so as to determine a timing for producing the output timing signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features and advantages of the delay circuit will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which: 
     FIG. 1 is a circuit diagram showing the prior art delay circuit disclosed in Japanese Patent Publication of Unexamined Application No. 8-237091; 
     FIG. 2 is a schematic view showing a delay circuit according to the present invention; and 
     FIG. 3 is a circuit diagram showing the circuit configuration of the delay circuit. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring first to FIG. 2 of the drawings, a delay circuit embodying the present invention comprises a first delay line  11  for rightwardly propagating an input clock signal CLK 10 , a second delay line  12  for leftwardly propagating the clock signal CLK 10 , a transfer circuit  13  connected between the first delay line  11  and the second delay line  12  for transferring a group of clock signal CLK 10  from the first delay line  11  to the second delay line  12  and a comparator  14  connected to the first delay line  11  and the second delay line  12  for producing an output clock signal CLK 11 . The transfer circuit  13  is responsive to the next clock signal CLK 10  serving as a timing control signal CTL 10 , and transfers the group of clock signal CLK 10  from the first delay line  11  to the second delay line  12 . The second delay line  12  propagates the group of clock signals CLK 10  in the opposite direction to the first delay line  11 , and supplies the group of clock signals CLK 10  to the comparator  14 . The first delay line  11  supplies the next group of clock signals CLK 10  to the comparator  14 , and comparator  14  compares the clock signals CLK 10  with the next clock signals CLK 10 , and produces the output clock signal CLK 11  in the concurrent presence of the clock signal CLK 10  and the next clock signal CLK 10 . The comparator  14  is designed to produce the output clock signal CLK 11  at a certain timing when the clock repetition period of the output clock signal CLK 11  is half of the clock repetition period of the clock signal CLK 10 . 
     FIG. 3 illustrates the detailed circuit configuration of the delay circuit. A controller  15  and a wired-OR gate  16  are further incorporated in the delay circuit. In the following description, a high voltage level and a low voltage level are assumed to be equivalent to logic “1” level and logic “0” level, respectively. 
     The first delay line  11  includes NAND gates NA 11 , NA 12 , NA 13 , NA 14 , . . . and NOR gates NR 11 , NR 12 , NR 13 , NR 14 , . . . The NAND gates NA 11  to NA 14  . . . are alternated with the NOR gates NR 11  to NR 14  . . . , and the NAND gates NA 11  to NA 14  and the NOR gates NR 11  to NR 14  are connected in series to the next NOR gates NR 11  to NR 14  and the next NAND gates NA 11  to NA 14 . The NAND gates NA 11  to NA 14  and the NOR gates NR 11  to NR 14  serve as delay elements, respectively, and the NAND/NOR gates NA 11 /NR 11 /NA 12 /NR 12 /NA 13 /NR 13 /NA 14 /NR 14  in the first delay line  11  are numbered as the first delay element, the second delay element, the third delay element, . . . and the eighth delay element. 
     The NAND gate NA 11  has two input nodes. One of the two input nodes is connected to a positive power voltage line VDD, and is fixed to logic “1” level. For this reason, the NAND gate NA 11  is enabled at all times, and inverts a potential level/logic level at the other input node. The clock signal CLK 10  is supplied to the other input node, and, accordingly, the NAND gate NA 11  produces the complementary clock signal CLKB 10  at the output node thereof. A piece of delay is introduced between the arrival of the clock signal CLK 10  at the other input node and the production of the complementary clock signal CLKB 10  at the output node. The complementary clock signal CLKB 10  is supplied to the NOR gate NR 11  and the transfer circuit  13 . 
     The NOR gate NR 11  also has two input nodes. One of the two input nodes is connected to a ground line, and is fixed to logic “0” level. The other input node is connected to the output node of the NAND gate NA 11 . For this reason, the NOR gate NR 11  is enabled at all times, and inverts the potential level or logic level at the other input node. A piece of delay is introduced between the arrival of the complementary clock signal CLKB 10  at the input node and the reproduction of the clock signal CLK 10  at the output node thereof, and the reproduced clock signal CLK 10  is supplied to the NAND gate NA 12  and the transfer circuit  13 . 
     The positive high voltage level and the reproduced clock signal CLK 10  are supplied to the two input nodes of the NAND gate NA 12 , and supplies the complementary clock signal CLKB 10  to the NOR gate NR 12  and the transfer circuit  13 . The NAND gate NA 12  also introduces a piece of delay. 
     The transfer circuit  13  supplies an enable signal EBL 1  and the complementary enable signal EBLB 1  to the NOR gates NR 12 /NR 13 /NR 14  and the NAND gates NA 13 /NA 14 . The NOR gates NR 12 /NRl 3 /NR 14  become responsive to the clock/complementary clock signal CLK 10 /CLKB 10  in the presence of the enable signal of the low level, and the complementary enable signal EBLB 1  of the high level make the NAND gates NA 13 /NA 14  responsive to the clock/complementary clock signal CLK 10 /CLKB 10 . Thus, the NOR gates NR 12 /NR 13 /NR 14  and the NAND gates NA 13 /NA 14  concurrently become responsive to the clock/complementary clock signals CLK 10 /CLKB 10 . 
     The controller  15  includes a signal path  15   a  and an inverter IV 10 , and the signal path  15   a  and the inverter IV 10  are arranged in parallel. The signal path  15   a  is connected to an input clock signal line  17 , and the input node of the inverter IV 10  is also connected to the input clock signal line  17 . For this reason, the controller  15  produces a control signal CTL 10  of active low level and the complementary control signal CTLB 10  from the clock signal CLK 10 , and supplies the control signal CTL 10  and the complementary control signal CTLB 10  to the transfer circuit  13 . 
     When the control signal CTL 10  is in the low level and, accordingly, the complementary control signal CTLB 10  is in the high voltage level, the transfer circuit  13  supplies the enable signal EBL 1  of the active low level and the complementary enable signal EBLB 1  of the high level to the NOR gates NR 12 /NR 13 /NR 14  and the NAND gates NA 13 /NA 14 , and the clock signal/complementary clock signals CLK 10 /CLKB 10  are rightwardly propagated through the NOR/NAND gates NR 12 /NA 13 /NR 13 /NA 14 /NR 14 . 
     The transfer circuit  13  includes two-input NOR gates NR 21 /NR 22 /NR 23 /NR 24  and two-input NAND gates NA 21 /NA 22 /NA 23 /NA 24  arranged in parallel, and the NOR gates NR 21 /NR 22 /NR 23 /NR 24  are alternated with the NAND gates NA 21 /NA 22 /NA 23 /NA 24 , respectively. The control signal CTL 10  is supplied to the NAND gates NA 21 /NA 22 /NA 23 /NA 24 , and the complementary control signal CTLB 10  is supplied to the NOR gate NR 21 /NR 22 /NR 23 /NR 24 . The input nodes of the NOR gates NR 21 /NR 22 /NR 23 /NR 24  are respectively connected to the output nodes of the NAND gates NA 11 /NA 12 /NA 13 /NA 14 , and the input nodes of the NAND gates NA 21 /NA 22 /NA 23 /NA 24  are connected to the output nodes of the NOR gates NR 11 /NR 12 /NR 13 /NR 14 , respectively. The NOR/NAND gates NA 21 /NA 21 /NR 22 /NA 22 /NR 23 /NA 23 /NR 24 /NA 24  are numbered as first comparing element, the second comparing element, the third comparing element, . . . and the eighth comparing element, and the first comparing element to the eighth comparing element are respectively corresponding to the first delay element to the eighth delay element, respectively. 
     The control signal CTL 10  of the low level and the complementary control signal CTLB 10  of the high level make the NAND gates NA 21 /NA 22 /NA 23 /NA 24  and the NOR gates NR 21 /NR 22 /NR 23 /NR 24  responsive to the clock signal/complementary clock signal CLK 10 /CLKB 10 . The NAND gates NA 21 /NA 22 /NA 23 /NA 24  and the NOR gates NR 21 /NR 22 /NR 23 /NR 24  invert the clock signal/complementary clock signal CLK 10 /CLKB 10 , and supplies the inverted signals CLKB 10 /CLK 10  to the second delay line  12 . The NOR gates NR 21 /NR 22 /NR 23 /NR 24  and the NAND gates NA 21 /NA 22 /NA 23 /NA 24  supply the enable signal EBLI and the complementary enable signal EBLB 1  to the NOR gates NR 12 /NR 13 /NR 14  and the NAND gates NA 13 /NA 14 . Each of the NOR/NAND gates NR 21 /NA 21 /NR 22 /NA 22 /NR 23  supplies the enable/complementary enable signal EBL 1 /EBLB 1  to every third delay element from the corresponding delay element of the first delay line  11 . 
     The second delay line  12  includes two-input NAND gates NA 31 /NA 32 /NA 33 /NA 34  and two-input NOR gates NR 31 /NR 32 /NR 33 /NR 34 , and the NAND gates NA 31 /NA 32 /NA 33 /NA 34  are alternated with the NR gates NR 31 /NR 32 /NR 33 /NR 34 , respectively. The NAND gates NA 31 /NA 32 /NA 33 /NA 34  and the NOR gates NR 31 /NR 32 /NR 33 /NR 34  are connected in series to the next NOR gates NR 31 /NR 32 /NR 33 /NR 34  and the next NAND gates NA 31 /NA 32 /NA 33 /NA 34 . The NAND gates NA 24 /NA 23 /NA 22 /NA 21  supply the clock/complementary clock signals CLK 10 /CLKB 10  to the NAND gates NA 31 /NA 32 /NA 33 /NA 34 , and the NOR gates NR 24 /NR 23 /NR 22 /NR 21  supply the clock/complementary clock signals CLK 10 /CLKB 10  to the NOR gates NR 31 /NR 32 /NR 33 /NR 34 . The series of NAND/NOR gates NA 31 /NR 31 /NA 32 /NR 32 /NA 33 /NR 33 /NA 34 /NR 34  leftwardly propagates the clock/complementary clock signals CLK 10 /CLKB 10 , and the NAND/NOR gates NA 31 /NR 31 /NA 32 /NR 32 /NA 33 /NR 33 /NA 34 /NR 34  introduce pieces of delay into the propagation of the clock/complementary clock signals CLK 10 /CLKB 10 . The NAND/NOR gates NA 31 /NR 31 /NA 32 /NR 32 /NA 33 /NR 33 /NA 34 /NR 34  are numbered as the first delay element, the second delay element, . . . and the eighth delay element, and the eighth delay element to the first delay element in the second delay line  12  are corresponding to the first delay element to the eighth delay element of the first delay line  11 , respectively. Thus, the first delay element NA 11  to the eighth delay element NR 14  are respectively paired with the eighth delay element NA 31  to the first delay element NR 34 , and the eighth delay element NR 34  to the first delay element NA 11  in the first delay line  11  and the first delay element NA 31  to the eighth delay element NR 34  in the second delay line  12  form a first delay element pairs NR 14 /NA 31  to an eighth delay element pair NA 11 /NR 34 , respectively. 
     The comparator  14  includes two-input NAND gates NA 41 /NA 42 /NA 43 /NA 44  arranged in parallel, two-input NOR gates NR 41 /NR 42 /NR 43 /NR 44  alternated with the NAND gates NA 41 /NA 42 /NA 43  and inverters IV 41 /IV 42 /IV 43 /IV 44  connected in series to the NAND gates NA 41 /NA 42 /NA 43 /NA 44 , respectively. The output nodes of the NAND gates NA 31 /NA 32 /NA 33 /NA 34  are connected to the input nodes of the NAND gates NA 41 /NA 42 /NA 43 /NA 44 , respectively, and the output nodes of the NOR gates NR 14 /NR 13 /NR 12 /NR 11  are respectively connected to the other input nodes of the NAND gates NA 41 /NA 42 /NA 43 /NA 44 . On the other hand, the output nodes of the NOR gates NR 31 /NR 32 /NR 33 /NR 34  are connected to the input nodes of the NOR gates NR 41 /NR 42 /NR 43 /NR 44 , respectively, and the output nodes of the NAND gates NA 14 /NA 13 /NA 12  are respectively connected to the other input nodes of the NOR gates NR 41 /NR 42 /NR 43 /NR 44 . Thus, the first delay line  11  and the second delay line  12  supply the clock/complementary clock signals CLK 10 /CLKB 10  to the comparator  14 . The NAND/NOR gates NA 41 /NR 41 /NA 42 /NR 42 /NA 43 /NR 43 /NA 44  are numbered as the first comparing element, the second comparing element, . . . and the seventh comparing element, and the first comparing element NA 41  to the seventh comparing element NA 44  respectively compare the potential levels respectively supplied from the first delay element pair NR 14 /NA 31  to the seventh delay element pair NR 11 /NA 34 . 
     Each of the NOR gates NR 41  to NR 43  compares the potential levels at the output nodes of the delay elements in the first delay line  11  with the potential levels at the output nodes of the delay elements in the second delay line  12  to determine whether or not both input potential levels are corresponding to logic “0” level. If both potential levels correspond to logic “0” level, the NOR gate NR 41  to NR 43  produces a control signal CTL 11  of the positive high voltage level Vdd, and supplies it to the wired-OR gate  16 . 
     On the other hand, each of the NAND gates NA 41  to NR 44  compares the potential levels at the output nodes in the first delay line  11  with the potential levels at the output nodes in the second delay line  12  to determine whether or not both potential levels are corresponding to logic “1” level. If both potential levels correspond to logic “1” level, the NAND gate NA 41  to NA 44  produces a complementary control signal CTLB 11  of the low level, and supplies it to the associated inverter IV 41 /IV 42 /IV 43 . The inverters IV 41  to IV 43  produce the control signal CTL 11  from the complementary control signal CTLB 11 , and supply it to the wired-OR gate  16 . 
     The wired-OR gate  16  includes a current supplier  16   a , an output clock signal line  16   b , a discharging line  16   c  and n-channel enhancement type switching transistors SW 1 , SW 2 , SW 3 , SW 4 , SW 5 , SW 6  and SW 7  connected in parallel between the output clock signal line  16   b  and the discharging line  16   c . The n-channel enhancement type switching transistors SW 1 /SW 3 /SW 5 /SW 7  are gated by the inverters IV 41 /IV 42 /IV 43 /IV 44 , respectively, and the other n-channel enhancement type switching transistors SW 2 /SW 4 /SW 6  are respectively gated by the NOR gates NR 41 /NR 42 /NR 43 /NR 44 . 
     The current supplier  16   a  includes a p-channel enhancement type charging transistor CH 1  connected between the positive power voltage line VDD and the output clock signal line  16   b , a delay line  16   d  implemented by a series combination of inverters IV 51 /IV 52 /IV 53  and a two-input NAND gate NA 51  enabled by the delay line  16   d . One of the two input nodes of the NAND gate NA 51  is directly connected to the controller  15 , and the other input node is connected through the delay line  16   d  to the controller  15 . The control signal CTL 10  is supplied to the NAND gate NA 51  and the delay line  16   d . An odd number of inverters IV 51 /IV 52 /IV 53  form the delay line  16   d , and supplies an enable signal EBL 2  to the NAND gate NA 51 . The NAND gate NA 51  is enabled with the enable signal EBL 2  of the high voltage level, and changes a control signal CTL 12  to the low voltage level for certain time period after change of the control signal CTL 10  from the low voltage level to the high voltage level. The control signal CTL 12  of the low voltage level causes the p-channel enhancement type charging transistor CH 1  to turn on, and the p-channel enhancement type charging transistor CH 1  pulls up the output clock signal line  16   b  to the positive power voltage level Vdd. After the certain lapse of time, the delay line  16   d  changes the enable signal EBL 2  to the low voltage level, and the NAND gate NA 51  recovers the control signal CTL 12  to the inactive high level. Then, the output clock signal line  16   b  is isolated from the positive power voltage line VDD. 
     Thereafter, the n-channel enhancement type switching transistors SW 1  to SW 7  are gated by the comparator  14 , and the positive power voltage Vdd is discharged from the output clock signal line  16   b  through at least one of the n-channel enhancement type switching transistors SW 1  to SW 7  so as to change the potential level of the output clock signal CTL 11 . 
     Assuming now that a clock pulse CLK 10 - 1  and the next clock pulse CLK 10 - 2  change the input clock signal line  17  to the high voltage level at interval, the first delay line  11  propagates the clock pulse CLK 10 - 1  of the high voltage level from the first delay element NA 11  toward the eighth delay element NA 14 . The controller  15  supplies the control signal CTL 10  of the low level and the complementary control signal CTLB 10  of the high level to the NAND gates NA 21 /NA 22  and the NOR gates NR 21 /NR 22 /NR 23  between the trailing edge of the clock pulse CLK 10 - 1  and the leading edge of the next clock pulse CLK 10 - 2 . The control signal CTL 10  of the low level and the complementary control signal CTLB 10  of the high level disable the NAND gates NA 21 /NA 22 /NA 23 /NA 24  and the NOR gates NR 21 /NR 22 /NR 3 /NR 24 , and the comparator does not transfer the potential levels at the output node of the NAND/NOR gates NA 11  to NR 14  in the first delay line  11  to the second delay line  12 . However, the NOR gates NR 21 /NR 22 /NR 23  and the NAND gates NA 21 /NA 22  supply the enable signal EBL 1  of the low level and the complementary enable signal EBLB 1  of the high level to the associated NOR gates NR 12 /NR 13 /NR 14  and the associated NAND gates NA 13 /NA 14 , and allow the first delay line  11  to propagate the clock pulse CLK 10 - 1  and the complementary clock pulse CLKB- 1  from the delay element to the next delay element. 
     When the next clock pulse CLK 10 - 2  changes the input clock signal line  17  to the high voltage level, the controller  15  changes the control signal CTL 10  and the complementary control signal CTLB 10  to the high voltage level and the low voltage level, respectively, and enable the transfer circuit  13 . Then, the transfer circuit  13  inverts the potential levels at the output node of the first delay element NA 1  to the output node of the eighth delay element NR 14 , and supplies the inverted potential levels to the input node of the eighth delay element NR 34  to the input node of the first delay element NA 31 . 
     The second delay line  12  propagates the clock pulse/complementary clock pulse CLK 10 - 1 /CLKB 10 - 1  toward the eighth delay element NR 34 , and the potential level is sequentially changed from the first delay element NA 31  toward the eighth delay element NR 34 . On the other hand, the first delay line  11  propagates the clock pulse/complementary clock pulse CLK 10 - 2 /CLK 10 - 2  toward the eighth delay element NR 14 , and the potential level at the output node is sequentially changed from the first delay element NA 11  toward the eighth delay element NA 14 . The first delay element pair NR 14 /NA 31  to the seventh delay element pair NR 11 /NA 34  continuously supply the pairs of potential levels to the first comparing element NA 41  to the seventh comparing element NA 44 , and the first comparing element NA 41  to the seventh comparing element NA 44  compares the input potential levels to determine whether or not they are incident in logic level with each other. In this instance, a potential level supplied from the first delay line  11  is consistent in logic level with the corresponding potential level supplied from the second delay line  12  around a certain timing after lapse of time equal to the half of the pulse repetition period from the leading edge of the clock pulse CLK 10 - 2 , and the comparator  14  produces the control signal CTL 11 . 
     The current supplier  16   a  has already charged the output clock signal line  16   b , and the control signal CTL 11  causes the associated n-channel enhancement type switching transistor to turn on. Then, the output clock signal line  16   b  changes the potential level on the output clock signal line  16   b  to the low level, and the wired-OR gate  16  changes the output clock signal CLK 11  at the certain timing. 
     If the delay circuit is hierarchically multiplied, the delay circuit produces an output pulse signal at another timing {fraction (1/4, 3/4)}, . . . of the pulse repetition period of the input clock signal. 
     As will be appreciated from the foregoing description, the certain timing is determined by the comparator  14 , and the output clock signal is produced after lapse of time equal to one or more than one of equal parts equally divided from the change of the input signal. For this reason, it is not necessary to previously regulate the difference in time between the first delay line and the second delay line to the half of the pulse repetition period. 
     The NAND gates and the NOR gates form the first delay line  11 , the second delay line  12 , the transfer circuit  13  and the essential part of the cornparator  14 , and, for this reason, the piece of delay to be introduced in the signal propagation is easily calculable. 
     Although a particular embodiment of the present invention has been shown and described, it will be obvious to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention. 
     For example, the current supplier  16   a  may be replaced with a resistor. 
     The above-described embodiment is fabricated on the basis of the NAND function. Another delay circuit may be fabricated on the basis of the NOR function. 
     The above-described embodiment compares the potential levels supplied from the first delay line  11  with the potential levels supplied from the second delay line  12  for the certain timing. Another delay circuit may detect the certain timing by using the pulse edge. 
     The delay circuit may be fabricated on a part of a semiconductor integrated circuit device.