Abstract:
A switched-capacitor circuit for use in analog-to-digital conversion samples an input signal with respect to a reference voltage, without having to generate the reference voltage, by using charge redistribution. The switched-capacitor circuit prevents the need to dissipate power while producing the reference voltage. The switched-capacitor circuit is coupled to a comparator and to a logic circuit which provides control signals for switching. The switched-capacitor circuit comprises a plurality of capacitors arranged according to several embodiments.

Description:
TECHNICAL FIELD 
   This invention relates to switched-capacitor methods and apparatus, and more particularly, to switched-capacitor methods and apparatus used for sampling and/or processing of signals. 
   RELATED ART 
   Many systems employ switched-capacitor circuits (which make use of capacitors and switches) for sampling and/or processing of signals. For example, analog to digital converters (ADCs) often employ a switched-capacitor circuit to sample an analog voltage prior to analog to digital conversion. 
     FIG. 1  is a block diagram of a prior art ADC  20  that employs a switched-capacitor circuit to sample an analog voltage prior to analog to digital conversion. The ADC  20  includes a switched-capacitor circuit  22 , a comparator circuit  24  (referred to hereafter as comparator  24 ) and a control/output circuit  26  (referred to hereafter as control circuit  26 ). The switched-capacitor circuit  22  receives a differential input voltage, IN+, IN− (which is supplied via signal lines  28 ,  30 , respectively) and outputs a differential output voltage CP, CN. The differential output voltage CP, CN is supplied on signal lines  32 ,  34 , respectively, to the comparator  24 , which is further supplied with supply voltages, VDD and VSS. The output of the comparator  24  is supplied via a signal line  36  to the control circuit  26 , which provides control signals (represented by CONTROL) that are supplied on signal lines (represented by a signal line  38 ) provided to the switched-capacitor circuit  22 . The control circuit  26  also provides a multi-bit digital signal, DOUT, which is the output of the ADC  20 . The DOUT signal indicates a ratio of the magnitude of the differential input signal, IN+, IN−, compared to the magnitude of a differential reference voltage, REF+, REF−, which is supplied on signal lines  40 ,  42 . 
     FIG. 2  is a schematic diagram of a prior art switched-capacitor circuit  22 . For clarity, it has been assumed that the ADC  20  is a 4-bit ADC. The comparator  24  is shown in phantom. The switched-capacitor circuit  22  is made up of two circuit portions  50 ,  52 . The first portion  50  includes capacitors C 1 –C 4   x  and switches S 1 –S 4   x , S 9 . The capacitors C 1 –C 4  have binary-weighted capacitance values C/2, C/4, C/8, C/16, respectively. Capacitor C 4   x  has the same capacitance as C 4 , namely C/16, so that the sum capacitance of C 2 –C 4   x  equals the capacitance of C 1 . The second portion  52  includes capacitors C 5 –C 8   x  and switches S 5 –S 8   x , S 10  The capacitors C 5 –C 8  have binary-weighted capacitance values C/2, C/4, C/8, C/16, respectively. Capacitor C 8   x  has the same capacitance as C 8 , namely C/16, so that the sum capacitance of C 6 –C 8   x  equals the capacitance of C 5 . Capacitors C 1 , C 5  are associated with the MSB of the ADC  20 . Capacitors C 4 , C 8  are associated with the LSB of the ADC  20 . The switches S 1 –S 10  in the switched-capacitor circuit  22  are controlled by the control signals, CONTROL, supplied from the control circuit  26 . 
     FIG. 3  shows timing signals employed within the control circuit  26 . Each of the timing signals has two logic states represented by first and second voltage levels. The timing signals are shown on the same time axis however this does not signify that one attains different voltage levels than the others. 
   The operation of the ADC  20  is as follows. During a sampling interval ( FIG. 3 ), the switch S 9  is commanded to a closed state and switches S 1 –S 4   x  are commanded to a state that connects each of the capacitors C 1 –C 4   x , respectively, to the voltage IN+, thereby allowing the voltage IN+ to be sampled (with respect to voltage CM) in each of the capacitors C 1 –C 4   x . In addition, switch S 10  is in a closed state and switches S 5 –S 8   x  are in a state that connects each of the capacitors C 5 –C 8   x , respectively, to the voltage IN−, thereby allowing the voltage IN− to be sampled (with respect to voltage CM) in each of the capacitors C 5 –C 8   x . At the end of the sampling interval ( FIG. 3 ), the switches S 9 , S 10  are opened, thereby disconnecting the capacitors C 1 –C 4   x , C 5 –C 8   x  from voltage CM. A conversion interval ( FIG. 3 ) follows the sampling interval ( FIG. 3 ). During the conversion interval ( FIG. 3 ), the control circuit  26  commands switches S 1 –S 4   x , S 5 –S 8   x  to various states in accordance with a conversion algorithm, and monitors the resulting output signals from the comparator  24 . Note that the conversion interval and the sampling interval do not overlap one another in time. Finally, during an output interval, the control circuit  26  provides a multi-bit digital output signal DOUT based on output signals received from the comparator  24  during the conversion interval ( FIG. 3 ). This type of ADC is commonly referred to as a successive approximation ADC. 
   In charge redistribution converters, it is necessary to prevent the output voltage CP, CN from going beyond the supply range (i.e, &gt;VDD or &lt;VSS), and in order to simplify the design of the comparator  24 , it is desirable to ensure that the common mode voltage of CP and CN is within the common mode range of the comparator during the conversion interval. One way to achieve this is by making the magnitude of the voltage CM equal to ½ (VDD+VSS), so that the differential input voltage IN+, IN− is sampled with respect to ½ (VDD+VSS). Such a voltage is often readily available, i.e., voltage REF+ is often approximately equal to ½ (VDD+VSS). However, this is not always the case. For example, in some instances, REF+ has a magnitude close or equal to VDD, which is beneficial for improving the signal to noise ratio of the ADC, but makes REF+ unsuitable for use as voltage CM. 
   Consequently, additional circuitry is often used to generate a voltage equal to ½ (VDD+VSS). 
     FIG. 4  is a schematic block diagram of a switched-capacitor circuit  62  that includes circuitry to generate a voltage equal to ½ (VDD+VSS). As in  FIG. 2 , the comparator  24  is shown in phantom. The switched-capacitor circuit  62  is identical to the switched-capacitor circuit  22  ( FIG. 1 ) except for the addition of two resistors R 1 , R 2 , which are connected in series between the supply voltages VDD, VSS. Resistors R 1  and R 2  each have a resistance value R whereby the magnitude of the voltage generated at the center tap is equal to ½ (VDD+VSS). Additionally, it has been taught to use other voltages such as IN+, IN− or REF+, REF− instead of VDD, VSS, and to adjust the resistances of R 1  and R 2  to achieve the desired voltage on the center tap. One disadvantage of this circuit  62  is that the resistor string R 1 , R 2  dissipates a significant amount of power. 
   Notwithstanding the performance provided by the prior art switched-capacitor circuits described above, other switched-capacitor circuits for sampling and/or processing input signal(s) are sought. 
   SUMMARY OF THE INVENTION 
   In accordance with one aspect of the present invention, a system comprises a switched-capacitor circuit including a first capacitor, a second capacitor and at least one switch, the at least one switch being operable during a first time interval to: (1) connect the first capacitor between a first signal line having a first voltage and a second signal line having a second voltage, and (2) connect the second capacitor between the first signal line having the first voltage and a third signal line having a third voltage, the third voltage being different than the second voltage, and the at least one switch being operable during a second time interval to connect the first capacitor in parallel with the second capacitor. 
   In accordance with another aspect of the present invention, a system comprises a switched-capacitor circuit having a plurality of banks of capacitors and at least one switch, each of the plurality of banks of capacitors having a first capacitor and a second capacitor, the at least one switch being operable during a first time interval to: (1) connect the first capacitor of each bank between a first signal line having a first voltage and a second signal line having a second voltage, and (2) connect the second capacitor of each bank between the first signal line having the first voltage and a third signal line having a third voltage, the third voltage being different than the second voltage, and the at least one switch being operable during a second time interval to connect the first capacitor of each bank in parallel with the second capacitor of such bank. 
   In accordance with another aspect of the present invention, a system comprises a switched-capacitor circuit having a first group of capacitors, a second group of capacitors, and at least one switch, the first group of capacitors having at least one capacitor, the second group of capacitors having at least one capacitor, the at least one switch being operable during a first time interval to: (1) connect each capacitor of the first group of capacitors between a first signal line having a first voltage and a second signal line having a second voltage, and (2) connect each capacitor of the second group of capacitors between the first signal line having the first voltage and a third signal line having a third voltage, the third voltage being different than the second voltage, and the at least one switch being operable during a second time interval to connect each capacitor of the first group of capacitors in parallel with each capacitor of the second group of capacitors. 
   In accordance with another aspect of the present invention, a method comprises connecting, during a first time interval, a first capacitor between a first signal line having a first voltage and a second signal line having a second voltage, a second capacitor between the first signal line and a third signal line having a third voltage, the third voltage being different than the second voltage; and connecting, during a second time interval, the first capacitor in parallel with the second capacitor. 
   In accordance with another aspect of the present invention, a system comprises means for connecting, during a first interval, a first capacitor between a first signal line having a first voltage and a second signal line having a second voltage, and for connecting, during the first interval, a second capacitor between the first signal line having the first voltage and a third signal line having a third voltage, the third voltage being different than the second voltage; and means for connecting, during a second interval, the first capacitor in parallel with the second capacitor. 
   In accordance with another aspect of the present invention, a system comprises a switched-capacitor circuit having a first group of capacitors, a second group of capacitors, and at least one switch, the first group of capacitors having at least one capacitor, the second group of capacitors having at least one capacitor, the at least one switch being operable during a first time interval to: (1) connect at least one capacitor of the first group of capacitors between a first signal line having a first voltage and a second signal line having a second voltage, and (2) connect at least one capacitor of the second group of capacitors between the first signal line having the first voltage and a third signal line having a third voltage, the third voltage being different than the second voltage, and the at least one switch being operable during a second time interval to connect the at least one capacitor of the first group to the at least one capacitor of the second group such that the voltage across the at least one capacitor of the first group and the voltage across the at least one capacitor of the second group become equal to one another. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic block diagram of a prior art analog to digital converter (ADC) that includes a switched-capacitor circuit; 
       FIG. 2  is a schematic diagram of the switched-capacitor circuit of  FIG. 1 ; 
       FIG. 3  illustrates timing signals used in the control circuit of  FIG. 1 ; 
       FIG. 4  is a schematic diagram of another prior art switched-capacitor circuit; 
       FIG. 5  is a schematic diagram of a switched-capacitor circuit in accordance with one embodiment of the present invention; 
       FIG. 6  illustrates timing signals used in the control of the switched-capacitor circuit of  FIG. 5 ; 
       FIG. 7  is a block diagram of an ADC having a switched-capacitor circuit according to one embodiment of the present invention; 
       FIG. 8  is a schematic diagram of one embodiment of the switched-capacitor circuit of  FIG. 7 ; 
       FIG. 9  illustrates timing signals used in one embodiment of the control circuit of  FIG. 7 ; 
       FIG. 10  is a schematic diagram of another embodiment of the switched-capacitor circuit of  FIG. 7 ; 
       FIG. 11  is a schematic diagram of another embodiment of the switched-capacitor circuit of  FIG. 7 ; 
       FIG. 12  is a schematic diagram of another embodiment of the switched-capacitor circuit of  FIG. 7 ; and 
       FIG. 13  is a schematic diagram of a switched-capacitor circuit in accordance with one embodiment of the present invention; 
   

   DETAILED DESCRIPTION 
     FIG. 5  is a schematic diagram of a switched-capacitor circuit  80  in accordance with one embodiment of the present invention. The switched-capacitor sampling circuit  80  includes capacitors C 10 A, C 10 B and switches S 11 –S 14 . A voltage IN is supplied on a terminal  82  connected to a first terminal  84  of switch S 11 . A second terminal  86  of switch S 11  is connected to a first plate of capacitor C 10 A and to a first plate of capacitor C 10 B. A second plate of capacitor C 10 A is coupled to a first terminal  88  of switch S 12 , a second terminal  90  of which is coupled to a terminal  92  that supplies a voltage V 1 . A second plate of capacitor C 10 B is coupled to a first terminal  94  of switch S 13 , a second terminal  96  of which is coupled to a terminal  98  that supplies a voltage V 2  (not equal to V 1 ). Switch S 14  has first and second terminals,  100 ,  102 , the first terminal  100  being coupled to the second plate of capacitor C 10 B, the second terminal  102  being coupled to the second plate of capacitor C 10 B. 
   In this embodiment, the switches S 11 –S 14  comprise “voltage shorting” type switches that are controlled by timing signals P 4 –P 6  shown in  FIG. 6 . Each of the timing signals P 4 –P 6  has two logic states represented by first and second voltage levels. The timing signals P 4 –P 6  are shown on the same time axis. This does not, however, signify that one attains different voltage levels than the others. 
   The operation of the switched-capacitor circuit  80  is as follows. During a first portion  110  of a sampling interval ( FIG. 6 ), switch S 11  is commanded to a closed state to connect the first plate of each of the capacitors C 10 A, C 10 B to the terminal supplying the input voltage IN. Also, switches S 12 , S 13  are commanded to a closed state to thereby connect the second plate of the capacitors C 10 A, C 10 B, to the terminals supplying V 1  and V 2 , respectively. In this configuration, voltage IN is sampled (with respect to V 1 ) in capacitor C 10 A and sampled (with respect to V 2 ) in capacitor C 10 B. 
   During a second portion  112  of the sampling interval ( FIG. 6 ), switches S 12 , S 13  are commanded to an open state, thereby disconnecting the second plate of the capacitors C 10 A, C 10 B from the terminals supplying V 1  and V 2 , respectively. 
   During a third portion  114  of the sampling interval ( FIG. 6 ), switch S 14  is commanded to a closed state, thereby connecting the second plate of capacitor C 10 A to the second plate of capacitor C 10 B. Doing so puts capacitor C 10 A and C 10 B in parallel with one another. 
   If capacitors C 10 A, C 10 B each have a capacitance value of C/2, then in this state, the second plate of each of capacitors C 10 A, C 10 B has a voltage of ½ (V 1 +V 2 ) and the amount of charge stored by each of the capacitors C 10 A, C 10 B is equal to that which would have been stored by the capacitors C 10 A, C 10 B had the voltage IN been sampled with respect to ½ (V 1 +V 2 ). 
   Accordingly, if V 1 , V 2  are equal to VSS, VDD, respectively, then the voltage on the second plate of each of capacitors C 10 A, C 10 B is equal to ½ (VDD+VSS) and the amount of charge stored by each of the capacitors C 10 A, C 10 B is equal to that which would have been stored by the capacitors C 10 A, C 10 B had the voltage IN been sampled with respect to ½ (VDD+VSS). This result is similar to that obtained by the prior art switched-capacitor circuits  22  ( FIG. 2 ),  62  ( FIG. 4 ), which helps prevent the magnitude of the voltages CP, CN from going beyond a supply range (e.g., &gt;VDD or &lt;VSS), yet there is no need to provide the switched-capacitor circuit  80  with a voltage equal to ½ (VDD+VSS). 
   In some embodiments, switch S 12  comprises an NMOS device, switch S 13  comprises a PMOS device, and switch S 14  comprises a CMOS device, although any other types of switches may also be used. 
     FIG. 7  is a block diagram of an ADC  120  having a switched-capacitor circuit according to one embodiment of the present invention. The ADC  120  includes two circuit portions  122 ,  123 . The first circuit portion comprises a switched-capacitor circuit  122 . The second circuit portion  123  comprises a comparator circuit  124  (referred to hereafter as comparator  124 ) and a control/output circuit  126  (referred to hereafter as control circuit  126 ). The switched-capacitor circuit  122  receives a differential input voltage, IN+, IN− (which is supplied via signal lines  128 ,  130 , respectively), a differential reference voltage, REF+, REF− (which is supplied on signal lines  140 ,  142 ) and supply voltages VDD and VSS (which are supplied on signal lines  144 ,  146 , respectively). The switched-capacitor circuit  122  generates a differential output voltage CP, CN, which is supplied on signal lines  132 ,  134 , respectively, to the comparator  124 . The output of the comparator  124  is supplied via a signal line  136  to the control circuit  126 , which provides control signals (represented by CONTROL) that are supplied on signal lines (represented by a signal line  138 ) provided to the switched-capacitor circuit  122 . The control circuit  126  also provides a multi-bit digital signal, DOUT, which is the output of the ADC  120 . The DOUT signal indicates a ratio of the magnitude of the differential input signal, IN+, IN−, compared to the magnitude of the differential reference voltage, REF+, REF−. 
     FIG. 8  is a schematic diagram of one embodiment of the switched-capacitor circuit  122 . This embodiment of the switched-capacitor circuit  122  includes two circuit portions  150 ,  152 . The first circuit portion  150  includes a plurality of capacitor banks C 101 –C 104   x  and switches S 101 –S 104   x , S 109 A–S 109 B, S 111 . Each capacitor bank includes two capacitors. For example, capacitor bank C 101  includes capacitors C 101 A, C 101 B. Capacitor bank C 103  includes capacitors C 103 A, C 103 B. Capacitor bank C 104  includes capacitors C 104 A, C 104 B. 
   The capacitance of each capacitor bank is equal to the sum of the capacitance values in that particular bank. For example, the capacitance of capacitor bank C 101  is equal to C/2 (i.e., C/4+C/4). The capacitor banks C 101 –C 104  may have binary-weighted capacitance values C/2, C/4, C/8, C/16 respectively, as shown, but are not limited to such. Additionally, capacitor bank C 104   x  may have a capacitance value equal to C 104 , as shown, so that the sum capacitance of capacitor banks C 102 –C 104   x  equals that of C 101 , but is not limited to such. 
   The second switched-capacitor circuit  152  includes capacitor banks C 105 –C 108   x  and switches S 105 –S 108   x , S 110 A–S 110 B, S 112 . As with capacitor banks C 101 – 104 , each capacitor bank includes two capacitors. The capacitor banks C 105 –C 108  may have binary-weighted capacitance values C/2, C/4, C/8, C/16 respectively, as shown, but are not limited to such. Additionally, capacitor bank C 108   x  may have a capacitance value equal to C 108 , as shown, so that the sum capacitance of capacitor banks C 106 –C 108   x  equals that of C 105 , but is not limited to such. 
   The switches in the switched-capacitor circuit  122  are controlled by the control signals, CONTROL, supplied from the control circuit  126 . 
   The switches S 101 –S 108   x  are identical to one another. Each has three operating states. For example, switch S 101  connects the associated capacitor bank C 101  to IN+, REF+, or REF−. Switch S 105  connects the associated capacitor bank C 105  to IN−, REF+, or REF−. And so on. 
     FIG. 9  shows timing signals P 7 –P 9  employed within the control circuit  126 . Each of the timing signals P 7 –P 9  has two logic states represented by first and second voltage levels. These timing signals are merely representative if those actually used; in particular, two state signals are used for convenience even when controlling a three state switch, and any ambiguity will be clear from explicit statement or the context of the use. The timing signals P 7 –P 9  are shown on the same time axis however this does not signify that one attains different voltage levels than the others. 
   The operation is as follows. During a first portion of a sampling interval  180  ( FIG. 9 ), switches S 101 –S 104   x  are commanded to a state that connects each of the capacitors banks C 101 –C 104   x , respectively, to the voltage IN+. Switch S 109 A is commanded to a closed state thereby connecting the second plate of each of the capacitors C 101 A–C 104   x A to VSS. Switch S 109 B is commanded to a closed state thereby connecting the second plate of each of the capacitors C 101 B–C 104   x B to the voltage VDD. In this configuration, the voltage IN+ is sampled (with respect to voltage VSS) in each of the capacitors C 101 A–C 104   x A, and sampled (with respect to voltage VDD) in each of the capacitors C 101 B–C 104   x B. In addition, switches S 105 –S 108   x  are commanded to a state that connects each of the capacitors banks C 105 –C 108   x , respectively, to the voltage IN−. Switch S 110 A is commanded to a closed state thereby connecting the second plate of each of the capacitors C 105 A–C 108   x A to VSS. Switch S 110 B is commanded to a closed state thereby connecting the second plate of each of the capacitors C 105 B–C 108   x B to the voltage VDD. With this configuration, the voltage IN− is sampled (with respect to voltage VSS) in each of the capacitors C 105 A–C 108   x A, and sampled (with respect to voltage VDD) in each of the capacitors C 105 B–C 108   x B. 
   During a second portion of the sampling interval  182  ( FIG. 9 ), switches S 109 A–S 110 A, S 109 B–S 110 B are concurrently commanded to an open state, thereby disconnecting the second plate of the capacitors C 101 A–C 108   x A, C 101 B–C 108   x B, respectively, from the terminals supplying VSS and VDD. 
   During a third portion of the sampling interval  184  ( FIG. 9 ), switch S 111  is commanded to a closed state, thereby connecting the second plate of capacitors C 101 A–C 104   x A to the second plate of capacitors C 101 B–C 104   x B. In this configuration, the second plates of each of these capacitors C 101 A–C 104   x A, C 101 B–C 104   x B is equal to ½ (VDD+VSS) and the amount of charge stored by each of the capacitors C 101 A–C 104   x A, C 101 B–C 104   x B is equal to that which would have been stored by the capacitors C 101 A–C 104   x A, C 101 B–C 104   x B had the voltage IN+ been sampled with respect to ½ (VDD+VSS). In addition, switch S 112  is commanded to a closed state, thereby connecting the second plate of capacitors C 105 A–C 108   x A to the second plate of capacitors C 105 B–C 108   x B. In this configuration, the second plates of each of these capacitors C 105 A–C 108   x A, C 105 B–C 108   x B is equal to ½ (VDD+VSS) and the amount of charge stored by each of the capacitors C 105 A–C 108   x A, C 105 B–C 108   x B is equal to that which would have been stored by the capacitors C 105 A–C 108   x A, C 105 B–C 108   x B had the voltage IN− been sampled with respect to ½ (VDD+VSS). 
   A conversion interval  186  ( FIG. 9 ) follows the sampling interval. During the conversion interval  186 , the control circuit  126  commands switches S 101 –S 104   x , S 105 –S 108   x  to various states in accordance with a conversion algorithm, and monitors the resulting output signals from the comparator  124 . Finally, during an output interval  188  ( FIG. 9 ), the control circuit  126  provides a multi-bit digital output signal DOUT based on output signals received from the comparator  124  during the conversion interval  186  ( FIG. 9 ). The multi-bit digital output may be in the form of parallel data, e.g., provided by way of plurality of signal lines, serial data, e.g., provided by way of a single signal line, or any combination thereof, e.g., some parallel data and some serial data. 
   Although each of the capacitor banks are shown having two capacitors, the capacitor banks may have any number of capacitors. Furthermore, the capacitors within a capacitor bank need not be identical to one another in value. Moreover, although the above embodiments show a voltage that is, in effect, sampled with respect to ½ (VDD+VSS), the present invention is not limited to such. For example, other embodiments may, in effect, sample a voltage with respect to any voltage or voltages. 
   Although the inputs of the comparator  124  are shown connected to the switched-capacitor circuit  122  during the sampling interval ( FIG. 9 ), such connection during the sampling interval is not required. For example, in some embodiments, the inputs of the comparator  124  are disconnected from the switched-capacitor circuit during the sampling interval and may or may not be connected to another terminal (which may supply another voltage). 
     FIG. 10  is a schematic diagram of another embodiment of the switched-capacitor circuit  122 . This embodiment of the switched-capacitor circuit  122  includes two circuit portions  250 ,  252 . The first circuit portion  250  includes a plurality of capacitors C 201 –C 204   x  and switches S 201 –S 204   x , S 209 A–S 109 B. The capacitors C 201 –C 204  may have binary-weighted capacitance values C/2, C/4, C/8, C/16 respectively, as shown, but are not limited to such. Additionally, capacitor C 204   x  may have a capacitance equal to that of C 204 , as shown, so that the sum capacitance of C 202 –C 204   x  equals that of C 201 , but is not limited to such. The second circuit portion  252  includes a plurality of capacitors C 205 –C 208   x  and switches S 205 –S 208   x , S 210 A–S 210 B. The capacitors C 205 –C 208  may have binary-weighted capacitance values C/2, C/4, C/8, C/16 respectively, as shown, but are not limited to such. Additionally, capacitor C 208   x  may have a capacitance equal to that of C 208 , as shown, so that the sum capacitance of C 206 –C 208   x  equals that of C 205 , but is not limited to such 
   The operation of this embodiment of the switched-capacitor circuit  122  is as follows. During a first portion of a sampling interval  180  ( FIG. 9 ), switches S 201 –S 204   x  are commanded to a state that connects each of the capacitors C 201 –C 204   x , respectively, of the first circuit portion  250  to the voltage IN+. Switch S 209 A is commanded to a closed state thereby connecting the second plate of each a first group of these capacitors, i.e., capacitors C 202 –C 204   x , to VSS. Switch S 209 B is commanded to a closed state thereby connecting the second plate of a second group of these capacitors, i.e., capacitor C 201 , to the voltage VDD. In this configuration, the voltage IN+ is sampled (with respect to voltage VSS) in each of the first group of capacitors, i.e., capacitors C 202 –C 204   x , and sampled (with respect to voltage VDD) in the second group of capacitors, i.e., capacitor C 201 . In addition, switches S 205 –S 208   x  are commanded to a state that connects each of the capacitors C 205 –C 208   x , respectively, in the second circuit portion  252  to the voltage IN−. Switch S 210 A is commanded to a closed state thereby connecting the second plate of each a first group of these capacitors, i.e., C 206 –C 208   x , to VSS. Switch S 210 B is commanded to a closed state thereby connecting the second plate of a second group of these capacitors, i.e., C 205 , to the voltage VDD. In this configuration, the voltage IN− is sampled (with respect to voltage VSS) in each of the capacitors C 206 –C 208   x , and sampled (with respect to voltage VDD) in capacitor C 205 . 
   During a second portion of a sampling interval  182  ( FIG. 9 ), switches S 209 A–S 210 A, S 209 B–S 210 B are concurrently commanded to an open state, thereby disconnecting the second plate of the capacitors C 201 –C 208   x , from the terminals supplying VSS and VDD. 
   During a third portion of a sampling interval  184  ( FIG. 9 ), switch S 211  is commanded to a closed state, thereby connecting the second plate of capacitor C 201  to the second plate of capacitors C 202 –C 204   x . In this configuration, the second plates of each of these capacitors C 201 –C 204   x  is equal to ½ (VDD+VSS) and the amount of charge stored by each of the capacitors C 201 –C 204   x  is equal to that which would have been stored by the capacitors C 201 –C 204   x  had the voltage IN+ been sampled with respect to ½ (VDD+VSS). In addition, switch S 212  is commanded to a closed state, thereby connecting the second plate of capacitor C 205  to the second plate of capacitors C 206 –C 208   x . In this configuration, the second plates of each of these capacitors C 205 C 208   x  is equal to ½ (VDD+VSS) and the amount of charge stored by each of the capacitors C 205 –C 208   x  is equal to that which would have been stored by the capacitors C 205 –C 208   x  had the voltage IN− been sampled with respect to ½ (VDD+VSS). 
   Although the various embodiments of the switched-capacitor circuit  122  shown above each have a differential configuration, the present invention is not limited to such. Thus, some embodiments may employ a single-ended configuration. For example,  FIGS. 11 ,  12  show further embodiments of the switched-capacitor circuit of  FIG. 7 . The embodiment of  FIG. 11  is identical to the embodiment of  FIG. 8 , except that the embodiment of  FIG. 11  is a single-ended configuration, to receive a single-ended input, IN. The embodiment of  FIG. 12  is identical to the embodiment of  FIG. 10 , except that the embodiment of  FIG. 12  is a single-ended configuration, to receive a single-ended input, IN. 
   The term “switch” as used herein is defined as any type of switch. A switch may comprise a one or more elements that function as a switch. For example, a switch may include but is not limited to one or more active elements (for example one or more transistors) and may but need not employ MOS technology. 
   The term “capacitor” as used herein is defined as any type of capacitor. A capacitor may comprise one or more elements that provide capacitance. For example, a capacitor may include but is not limited to metal, polysilicon and double polysilicon, metal metal, metal poly, poly diffusion, semiconductors, junction capacitors, parallel plate technology, adjacent conductors, fringing capacitors, and/or any combination thereof. 
   Although the capacitor banks described above have binary-weighted capacitance values, this is not a requirement. For example, some embodiments may have four capacitor banks with equally-weighted capacitance values, e.g., C/4, C/4, C/4, C/4. 
   Furthermore, although the DOUT signal described above indicates a ratio of the magnitude of the differential input signal, IN+, IN−, compared to the magnitude of the differential reference voltage, REF+, REF−, ADCs are not limited to such. For example, an DOUT signal may simply represent a value that is related to, e.g., proportional to, the magnitude of the input signal. 
   In addition, it should be understood that although various embodiments above show a switched-capacitor circuit supplying one or more signals to the comparator  124  (which is a type of amplifier), the switched-capacitor circuits described herein are also useful in association with other types of circuits, e.g., non-comparator type amplifiers. For example, in some embodiments, a switched-capacitor circuit supplies one or more signal(s) to one or more non-comparator type amplifier(s). 
   Moreover, although the embodiments of the switched-capacitor circuits  122  shown in  FIGS. 8 ,  10  are suitable for a 4-bit ADC, these embodiments are merely illustrative. The present invention is not limited to 4-bit ADCs. Indeed, as stated above, switched-capacitor techniques are used in many systems. Thus, the switched-capacitor circuits and techniques described above are not limited to successive approximation ADCs, or even ADCs in general, but rather may be used in any type of system. 
   Note that, except where otherwise stated, terms such as, for example, “comprises”, “has”, “includes” and all forms thereof, are considered open-ended so as not to precluded additional elements and/or features. 
   Also note, except where otherwise stated, phrase such as, for examples, “in response to”, “based on” and “in accordance with” mean “in response at least to”, “based at least on” and “in accordance with at least”, respectively, so as to not preclude being responsive to, based on, or in accordance with more than one thing. 
   Moreover, except where otherwise stated, “connect to” means “connect directly to” or “connect indirectly to”. Further, although the capacitors C 10 A, C 10 B are shown connected directly to one another (neglecting switch S 14 ), the present invention is not limited to direct connections. For example, in other embodiments, there may be resistance(s) and/or one or more switches, in series with the capacitors C 10 A, C 10 B, such as for example, but not limited to, as shown in  FIG. 13 , which is a schematic diagram of another embodiment  280  of a switched capacitor circuit. The embodiment of  FIG. 13  is identical to the embodiment of  FIG. 5 , except that the embodiment of  FIG. 13  further includes resistors R 200 , R 201  and replaces switch S 11  with two switches S 211 A, S 211 B. As with switch S 11 , switches S 211 A, S 211 B, may for example, be commanded to a closed state during the first sampling interval and they may remain in the closed state during the second and third sampling intervals. 
   While there have been shown and described various embodiments, it will be understood by those skilled in the art that the present invention is not limited to such embodiments, which have been presented by way of example only, and that various changes and modifications may be made without departing from the spirit and scope of the invention. Accordingly, the invention is limited only by the appended claims and equivalents thereto.