Abstract:
Methods of forming trench isolation regions include the steps of forming a trench masking layer comprising a first material (e.g., polysilicon) on a semiconductor substrate and then etching a trench in the semiconductor substrate, using the trench masking layer as etching mask. A trench nitride layer comprising a second material different from the first material is then formed on a sidewall of the trench and on a sidewall of the trench masking layer. The trench is then filled with a trench insulating material (e.g., USG). The trench masking layer is then removed by selectively etching the trench masking layer with an etchant that selectively etches the first material at a higher rate than the second material. This step of removing the trench masking layer results in exposure of a protruding portion of the trench nitride layer but does not cause the trench nitride layer to become recessed. The trench insulating material and the trench nitride layer are then etched back to define the trench isolation region.

Description:
RELATED APPLICATION 
     This application is related to Korean Application No. 98-42300, filed Oct. 9, 1998, the disclosure of which is hereby incorporated herein by reference. 
     FIELD OF THE INVENTION 
     This invention relates to methods of forming integrated circuit devices, and more particularly to methods of forming electrical isolation regions in semiconductor substrates. 
     BACKGROUND OF THE INVENTION 
     Trench isolation techniques have been considered as alternatives to local oxidation of silicon (LOCOS) isolation techniques because trench isolation techniques provide fully recessed oxides, may be planarized, do not result in the formation of bird&#39;s beaks oxide extensions and typically do not suffer from field oxide thinning effects. Such trench isolation techniques are more fully described in U.S. Pat. No. 5,750,433 to Jo entitled “Methods of Forming Electrically Isolated Active Region Pedestals Using Trench-Based Isolation Techniques”, U.S. Pat. No. 5,753,562 to Kim entitled “Methods of Forming Semiconductor Devices In Substrates Having Inverted-Trench Isolation Regions Therein”, and U.S. Pat. No. 5,858,842 to Park entitled “Methods of Forming Combined Trench and Locos-Based Electrical Isolation Regions In Semiconductor Substrates, all assigned to the present assignee, the disclosures of which are hereby incorporated herein by reference. 
     Unfortunately, the performance of thermal oxidation steps when forming trench isolation regions may cause volume expansion defects and dislocations to form adjacent the sidewalls and corners of the trenches as migrating oxygen reacts with the silicon at the trench sidewall interfaces. As will be understood by those skilled in the art, these defects and dislocations can degrade the electrical characteristics of devices formed in active regions which extend adjacent the trench isolation regions. 
     To address these limitations associated with conventional trench isolation techniques, attempts have been made to add stress-relieving liners (e.g., ON and ONO liners) to the sidewalls and bottoms of trenches. Such attempts are disclosed in U.S. Pat. Nos. 4,631,803, 5,189,501, 5,190,889 and 5,206,182. Unfortunately, conventional processing techniques may cause removal of the stress relieving lining material and result in the formation of voids which can degrade the electrical isolation characteristics of the trench isolation regions. For example, as illustrated by FIGS. 1A-1B, conventional processing techniques may cause a trench nitride layer  10  to become recessed and the formation of a void as illustrated by highlighted region  14 . 
     In particular, FIG. 1A illustrates a trench isolation region at an intermediate stage of processing. This trench isolation region may be formed by thermally oxidizing a face of a substrate  1  to define a pad oxide layer  2  and then depositing a silicon nitride masking layer  4  on the pad oxide layer  2 . The silicon nitride masking layer  4  may then be patterned using conventional photolithographically defined etching steps. The silicon nitride masking layer  4  may then be used as an etching mask during the formation of a trench  6  in the substrate  1 . The sidewalls and bottom of the trench  6  may then be thermally oxidized to define a trench oxide layer  8 . A trench nitride layer  10  may then be deposited on the trench oxide layer  8  and on the silicon nitride masking layer  4 . The trench may then be filled with an electrically insulating material  12  (e.g., USG). A planarization step may then be performed, using the silicon nitride masking layer  4  as a planarization-stop. Then, as illustrated by FIG. 1B, an etching step can be performed using a wet etchant (e.g., phosphoric acid) to remove the silicon nitride masking layer  4 . Unfortunately, this etching step may also cause the trench nitride layer  10  to become recessed, as illustrated. The extent of this recession may be reduced by using thinner trench nitride layers  10 , however, the use of thinner trench nitride layers  10  may reduce the stress-relieving benefits provided by the trench nitride layers  10 . Such techniques to use thinner trench nitride layers  10  are more fully disclosed in U.S. Pat. No. 5,447,884. 
     Thus, notwithstanding the above-described methods of forming trench isolation regions, there continues to be a need for improved methods of forming trench isolation regions. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide improved methods of forming trench isolation regions in semiconductor substrates. 
     It is another object of the present invention to provide methods of forming trench isolation regions that inhibit the formation of dislocations and stresses in portions of a semiconductor substrate extending adjacent the trench isolation regions. 
     It is still another object of the present invention to provide methods of forming integrated circuit substrates having active devices therein that are not adversely influenced by defects within adjacent trench isolation regions. 
     These and other objects, advantages and features of the present invention are provided by methods of forming trench isolation regions that include the steps of forming a trench masking layer comprising a first material (e.g., polysilicon) on a semiconductor substrate and then etching a trench in the semiconductor substrate, using the trench masking layer as etching mask. A trench nitride layer comprising a second material different from the first material is then formed on a sidewall of the trench and on a sidewall of the trench masking layer. The trench is then filled with a trench insulating material (e.g., USG). The trench masking layer is then removed by selectively etching the trench masking layer with an etchant that selectively etches the first material at a higher rate than the second material. This step of removing the trench masking layer results in exposure of a protruding portion of the trench nitride layer but does not cause the trench nitride layer to become recessed. The trench insulating material and the trench nitride layer are then etched back to define the trench isolation region. 
     According to one aspect of the present invention, the step of forming a trench nitride layer is preceded by the step of forming a trench oxide layer on the sidewall of the trench and on a sidewall of the trench masking layer. In particular, the trench oxide layer is formed on a sidewall of the trench masking layer by thermally oxidizing the sidewall of the trench masking layer. The step of etching back the trench insulating material also preferably comprises the step of etching the trench insulating material and the trench oxide layer simultaneously, to expose a protruding portion of the trench nitride layer and then etching the protruding portion of the trench nitride layer. The step of forming a trench masking layer is also preferably preceded by the step of forming a pad oxide layer on a surface of the semiconductor substrate. The step of removing the trench masking layer is also preferably performed by exposing the trench masking layer to an etching solution comprising HNO 3 , CH 3 COOH, HF and deionized water. 
     To further reduce stress within the semiconductor substrate, the trench nitride layer preferably comprises a silicon-rich nitride layer as Si 3+α N 4 , where α&gt;0, having a thickness in a range between about 70 Å and 300 Å. 
     According to another embodiment of the present invention, a method of forming a trench isolation region comprises the steps of forming a first trench masking layer comprising polysilicon on a semiconductor substrate and forming a second trench masking layer comprising silicon nitride on the first trench masking layer. A trench is then etched into the semiconductor substrate, using the first trench masking layer as etching mask. A trench nitride layer is then formed on a sidewall of the trench and on sidewalls of the first and second trench masking layers. The trench is then filled with a trench insulating material (e.g., USG and PE-TEOS). The second trench masking layer is then removed using conventional etching techniques and this step also results in the removal of an upper protruding portion of the trench nitride layer. The first trench masking layer is then removed by selectively etching the first trench masking layer with an etchant that selectively etches polysilicon at a higher rate than silicon nitride. The trench insulating material and the trench nitride layer are then etched-back to define the trench isolation region. To further prevent recession of the trench nitride layer, the step of etching the trench may be preceded by a step to etch a recess in the first trench masking layer. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A-1B are cross-sectional views of intermediate structures that illustrate a conventional method of forming a trench isolation region. 
     FIGS. 2A-2C are cross-sectional views of intermediate structures that illustrate methods of forming trench isolation regions according to a first embodiment of the present invention. 
     FIGS. 3A-3D are cross-sectional views of intermediate structures that illustrate methods of forming trench isolation regions according to a second embodiment of the present invention. 
     FIGS. 4A-4H are cross-sectional views of intermediate structures that illustrate methods of forming trench isolation regions according to a third embodiment of the present invention. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. However, when a layer or region is described as being “directly on” another layer or region, no intervening layers or regions are present. Like numbers refer to like elements throughout. 
     Referring now to FIGS. 2A-2C, preferred methods of forming trench isolation regions according to a first embodiment of the present invention will be described. In particular, FIG. 2A illustrates the steps of forming a pad oxide layer  102  and a polysilicon layer  104  on a semiconductor substrate  100 . An anti-reflective layer (not shown) may also be formed on the polysilicon layer  104 . The pad oxide layer  102  may be formed by thermally oxidizing an upper surface of the substrate  100  and may have a thickness in a range between about 100 Å and 240 Å. The polysilicon layer  104  may be deposited on the pad oxide layer  102  using a low pressure chemical vapor deposition (LPCVD) technique or a plasma enhanced chemical vapor deposition (PECVD) technique, for example. 
     The deposited polysilicon layer  104  may have a thickness of about 3000 Å or less, and more preferably only about 800 Å. The anti-reflective layer may also comprise a silicon oxynitride layer (SiON) having a thickness of about 600 Å. As described more fully hereinbelow, the polysilicon layer  104  is used instead of a nitride layer (e.g., the silicon nitride layer  4  in FIG. 1A) because, among other things, it has a high degree of etching selectively relative to silicon nitride and because it typically induces less stress within the substrate  100  relative to a silicon nitride layer. The anti-reflective layer serves to improve the accuracy of photolithographically defined etching steps (by reducing critical dimension variation) and also serves as a masking layer during subsequent trench etching steps. 
     Using conventional photolithographically defined etching steps, the anti-reflective layer and the polysilicon layer  104  are then sequentially etched to expose the pad oxide layer  102 . The etched anti-reflective layer and the etched polysilicon layer  104  are then used as an etching mask during the step of etching the pad oxide layer  102  to expose the substrate  100  and then etching the substrate  100  to define a trench  106  therein. During these etching steps, the anti-reflective layer may also be completely etched. 
     Referring still to FIG. 2A, a thermal oxidation step is then performed to define a trench oxide layer  108  on the sidewalls and on the bottom of the trench  106 . In addition, according to a preferred aspect of the present invention, this thermal oxidation step also results in the oxidation of the exposed sidewalls of the polysilicon layer  104 . As a result of this thermal oxidation step, a trench oxide layer  108  having a preferred thickness in a range between about 30 Å and 110 Å may be formed. Because the bottom and top corners of the trench  106  may be susceptible to crystal defects caused by the thermal oxidation step, a trench nitride layer  110  may be formed as a stress-relief layer on the trench oxide layer  108 , as illustrated. According to another preferred aspect of the present invention, this trench nitride layer  110  preferably comprises a silicon-rich silicon nitride layer (e.g., Si 3+α N 4 , where α&gt;0). The use of a silicon-rich silicon nitride layer is advantageous because it reduces stress in the substrate  100  to a greater degree than a conventional silicon nitride layer Si 3 N 4 . The trench nitride layer  110  may be formed using a low pressure chemical vapor deposition technique (LPCVD). The trench nitride layer  110  is formed to have a thickness in a range between about 70 Å and 300 Å, and more preferably about 100 Å. As described more fully hereinbelow, the trench nitride layer  110  may be formed as a relatively thick layer because of the reduced likelihood of recession during subsequent process steps. 
     The trench  106  is then filled with a first electrically insulating material layer such as undoped silicate glass (USG) that is deposited using a plasma enhanced chemical vapor deposition technique (PECVD). To relieve stresses within the first electrically insulating material layer, an additional second insulating material layer, such as a plasma enhanced tetraethylorthosilicate (PE-TEOS) glass layer, may be deposited on the USG layer. These two material layers are illustrated as a composite trench insulation region  112 . As will be understood by those skilled in the art, the thickness of the USG layer is a function of the depth of the trench  106 . For example, for a trench depth of about 0.25 microns, the USG layer may be deposited to a thickness of about 5,000 Å and the PE-TEOS layer may be deposited to a thickness of about 1,000 Å. An annealing step is then preferably performed to densify the USG layer and thereby inhibit recession of the trench insulation region  112  during subsequent processing. This annealing step may be performed in a nitrogen ambient (N 2 ) at a temperature of about 1,000° C. to 1,200° C. A planarization step is then performed on the trench insulation region  112 , using the polysilicon layer  104  as an etch stop layer. This planarization step may include chemical mechanical polishing (CMP) and chemical etch-back steps. 
     Referring now to FIG. 2B, the polysilicon “masking” layer  104  is then removed using a wet or dry etching technique, for example. To perform a wet etching step, the polysilicon layer  104  may be exposed to an etching solution containing HNO 3 , CH 3 COOH, HF and deionized water. A chlorine-based chemistry (Cl 2 ) may also be used during a dry etching step. As illustrated by FIG. 2C, an upper portion of the trench insulation region  112 , the pad oxide layer  102  and exposed portion of the trench oxide layer  108  may then be removed using a chemical etchant solution such as LAL (NH 4 F+HF). The upper protruding portion of the trench nitride layer  110  may also be removed using conventional etching techniques. However, in contrast to the trench isolation region of FIG. 1B, the trench nitride layer  110  of FIG. 2C is not recessed. Thus, the trench nitride layer  110  may be formed as a relatively thick layer to provide additional stress reduction. As will be understood by those skilled in the art, active devices may then be formed in the active portions of the substrate that are electrically isolated from each other by the trench isolation regions. 
     Referring now to FIGS. 3A-3D, preferred methods of forming trench isolation regions according to a second embodiment of the present invention will be described. In particular, FIG. 3A illustrates the steps of forming a pad oxide layer  202 , a polysilicon layer  203  and a nitride (e.g., Si 3 N 4 ) masking layer  204  on a semiconductor substrate  200 . An anti-reflective layer (not shown) may also be formed on the nitride masking layer  204 . The pad oxide layer  202  may be formed by thermally oxidizing an upper surface of the substrate  200  and may have a thickness in a range between about 100 Å and 240 Å. The polysilicon layer  203  may be deposited on the pad oxide layer  202  and may have a thickness of about 800 Å. The nitride masking layer  204  may also be deposited to a thickness of about 700 Å. The anti-reflective layer may also comprise a silicon oxynitride layer (SiON) having a thickness of about 600 Å. 
     Using conventional photolithographically defined etching steps, the anti-reflective layer, the nitride masking layer  204  and the polysilicon layer  203  are then sequentially etched to expose the pad oxide layer  202 . The etched anti-reflective layer, nitride masking layer  204  and polysilicon layer  103  are then used as a trench etching mask  206  during the step of etching the pad oxide layer  202  to expose the substrate  200  and then etching the substrate  200  to define a trench  208  therein. During these etching steps, the anti-reflective layer may also be completely etched. 
     Referring still to FIG. 3A, a thermal oxidation step is then performed to define a trench oxide layer  210  on the sidewalls and on the bottom of the trench  208 . This thermal oxidation step also results in the oxidation of the exposed sidewalls of the polysilicon layer  203 . As a result of this thermal oxidation step, a trench oxide layer  210  having a preferred thickness in a range between about 30 Å and 110 Å may be formed. A trench nitride layer  212  may then be formed as a stress-relief layer on the trench oxide layer  210  and on sidewalls of the nitride masking layer  204 , as illustrated. The trench nitride layer  212  is formed to have a thickness in a range between about 70 Å and 300 Å, and more preferably about 100 Å. 
     The trench  208  is then filled with a first electrically insulating material layer such as undoped silicate glass (USG) that is deposited using a plasma enhanced chemical vapor deposition technique (PECVD). To relieve stresses within the first electrically insulating material layer, an additional second insulating material layer, such as a plasma enhanced tetraethylorthosilicate (PE-TEOS) glass layer, may be deposited on the USG layer. These two material layers are illustrated as a composite trench insulation region  214 . An annealing step is then preferably performed to densify the USG layer and thereby inhibit recession of the trench insulation region  214  during subsequent processing. This annealing step may be performed in a nitrogen ambient (N 2 ) at a temperature of about 1,000° C. to 1,200° C. A planarization step is then performed on the trench insulation region  214 , using the nitride masking layer  204  as an etch stop layer. This planarization step may include chemical mechanical polishing (CMP) and chemical etch-back steps. 
     Referring now to FIG. 3B, the nitride masking layer  204  may then be removed using a dry etching technique. During this dry etching step, upper portions of the trench insulation region  214  and the trench nitride layer  212  may also be removed. This dry etching step may include a main etching step using a mixed gas containing CF 3 , Ar, CHF 3  and O 2 , and an over-etch step using a mixed gas containing Ar and CHF 3 . Because of the presence of the underlying polysilicon layer  203 , the nitride masking layer  204  may also be removed using a wet etching step (e.g., phosphoric acid etching solution). As illustrated by FIG. 3C, the polysilicon layer  203  is then removed using a wet or dry etching technique, for example, as described above with respect to FIG.  2 B. Finally, as illustrated by FIG. 3D, an upper portion of the trench insulation region  214 , the pad oxide layer  202  and exposed portion of the trench oxide layer  210  may then be removed using a chemical etchant solution such as LAL (NH 4 F+HF). The upper protruding portion of the trench nitride layer  212  may also be removed using conventional etching techniques. 
     Referring now to FIGS. 4A-4H, preferred methods of forming trench isolation regions according to a third embodiment of the present invention will be described. In particular, FIG. 4A illustrates the steps of forming a pad oxide layer  302 , a polysilicon layer  303  and a nitride (e.g., Si 3 N 4 ) masking layer  304  on a semiconductor substrate  300 . An anti-reflective layer (not shown) may also be formed on the nitride masking layer  304 . The pad oxide layer  302  may be formed by thermally oxidizing an upper surface of the substrate  300  and may have a thickness in a range between about 100 Å and 240 Å. The polysilicon layer  303  may be deposited on the pad oxide layer  302  and may have a thickness of about 800 Å. The nitride masking layer  304  may also be deposited to a thickness of about 700 Å. The anti-reflective layer may also comprise a silicon oxynitride layer (SiON) having a thickness of about 600 Å. Using conventional photolithographically defined etching steps, the anti-reflective layer, the nitride masking layer  304  and the polysilicon layer  303  are then sequentially etched to expose the pad oxide layer  302 . 
     Then, as illustrated by highlighted region  307 , a selective etching step is then performed to laterally etch the polysilicon layer  303  and define a lateral recess therein having a recess width of about 200 Å to 700 Å. This selective lateral etching step may be performed as a dry etching step using a mixed gas containing SF 6  and Cl 2  or a wet etching step using a mixed solution of HNO 3 , CH 3 COOH, HF and deionized water. 
     Referring now to FIG. 4B, the resulting mask pattern  306  is used as an etching mask during the step of etching the pad oxide layer  302  to expose the substrate  300  and then etching the substrate  300  to define a trench  308  therein. Referring now to FIG. 4C, a thermal oxidation step is then performed to define a trench oxide layer  310  on the sidewalls and on the bottom of the trench  308 . This thermal oxidation step also results in the oxidation of the exposed sidewalls of the polysilicon layer  303 . A trench nitride layer  312  may then be formed as a stress-relief layer on the trench oxide layer  310  and on sidewalls of the nitride masking layer  304 , as illustrated. As illustrated by FIG. 4D, the trench  308  is then filled with a first electrically insulating material layer such as undoped silicate glass (USG) that is deposited using a plasma enhanced chemical vapor deposition technique (PECVD). To relieve stresses within the first electrically insulating material layer, an additional second insulating material layer, such as a plasma enhanced tetraethylorthosilicate (PE-TEOS) glass layer, may be deposited on the USG layer. These two material layers are illustrated as a composite trench insulation region  314 . An annealing step is then preferably performed to densify the USG layer and thereby inhibit recession of the trench insulation region  314  during subsequent processing. 
     As illustrated by FIG. 4E, a planarization step is then performed on the trench insulation region  314 , using the nitride masking layer  304  as an etch stop layer. Referring now to FIG. 4F, the nitride masking layer  304  may then be removed using a dry etching technique. During this dry etching step, portions of the trench insulation region  314  and trench nitride layer  312  may also be removed. This dry etching step may include a main etching step using a mixed gas containing CF 3 , Ar, CHF 3 , and O 2 , and an over-etch step using a mixed gas containing Ar and CHF 3 . Because of the presence of the underlying polysilicon layer  303 , the nitride masking layer  304  may also be removed using a wet etching step (e.g., phosphoric acid etching solution). As illustrated by highlighted region  315 , the lateral extensions of the trench insulation region  314  inhibit penetration of the etchant and removal of the trench nitride layer  312  from upper sidewalls of the trench  308 . 
     As illustrated by FIG. 4G, the polysilicon layer  303  is then removed using a wet or dry etching technique, for example, as described above with respect to FIG.  2 B. Here, because the high degree of etching selectivity between polysilicon and silicon nitride, the trench nitride layer  312  is not etched significantly during removal of the polysilicon layer  303 . Finally, as illustrated by FIG. 4H, an upper portion of the trench insulation region  314  and the pad oxide layer  302  are removed using a chemical etchant solution such as LAL (NH 4 F+HF). The upper protruding portion of the trench nitride layer  212  may also be removed using conventional etching techniques. Accordingly, a trench isolation region is formed to provide excellent electrical isolation between adjacent active regions within a substrate, with reduced susceptibility to stress related degradation of the electrical properties of the substrate. 
     In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.