Abstract:
The speed of a level shifter, which translates a first voltage in a first power domain to a second voltage in a second power domain, is increased by utilizing a first bipolar transistor to assist a first MOS transistor in pulling down the voltage on a first output node, and a second bipolar transistor to assist a second MOS transistor in pulling down the voltage on a second output node.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to level shifters and, more particularly, to a level shifter that provides high-speed operation between power domains that have a large voltage difference. 
     2. Description of the Related Art 
     A level shifter is a common circuit device that is used to translate a logic signal from a first power domain to a second power domain. A deep sub-micron digital circuit can represent a logic low with ground and a logic high with a voltage of, for example, 1.2 volts. When this circuit communicates with another circuit that represents a logic low with ground and a logic high with a voltage of, for example, 3.6 volts, a level shifter is used to shift the 1.2V logic high to a 3.6V logic high. 
       FIG. 1  shows a circuit diagram that illustrates a prior art level shifter  100 . As shown in  FIG. 1 , level shifter  100  includes an inverter that has a PMOS transistor M 1  and an NMOS transistor M 2 . PMOS transistor M 1  has a source connected to a first voltage source VDD 1 , such as 1.2V, a gate connected to an input node IN, and a drain. NMOS transistor M 2  has a drain connected to the drain of PMOS transistor M 1 , a source connected to ground, and a gate connected to the input node IN. 
     As further shown in  FIG. 1 , level shifter  100  also has an NMOS transistor M 3  and an NMOS transistor M 4 . NMOS transistor M 3  has a source connected to ground VSS, a drain connected to an inverted output node OUTbar, and a gate connected to the gates of transistors M 1  and M 2 . NMOS transistor M 4 , which is substantially the same size as NMOS transistor M 3 , has a source connected to ground VSS, a drain connected to an output node OUT, and a gate connected to the drains of transistors M 1  and M 2 . 
     Level shifter  100  further has a PMOS transistor M 5  and a PMOS transistor M 6 . PMOS transistor M 5  has a source connected to a second voltage source VDD 2 , such as 3.6V, a drain connected to the inverted output node OUTbar, and a gate connected to the output node OUT. PMOS transistor M 6 , which is substantially the same size as transistor M 5 , has a source connected to the second voltage source VDD 2 , a drain connected to the output node OUT, and a gate connected to the inverted output node OUTbar. 
     In operation, when a logic low, represented by ground, is present on the input node IN, PMOS transistor M 1  is turned on and NMOS transistors M 2  and M 3  are turned off. When PMOS transistor M 1  is turned on, the first supply voltage VDD 1  is placed on the gate of NMOS transistor M 4  which, in turn, turns on NMOS transistor M 4 . When NMOS transistor M 4  is turned on, the voltage on the output node OUT is pulled down to ground. Thus, the logic state on the output node OUT of level shifter  100  matches the logic state on the input node IN. 
     When the voltage on the output node OUT is pulled down to ground by NMOS transistor M 4 , PMOS transistor M 5  is turned on. When PMOS transistor M 5  is turned on, the second supply voltage VDD 2  is placed on the gate of PMOS transistor M 6  which, in turn, turns off PMOS transistor M 6 . 
     In addition, the second supply voltage VDD 2  is also placed on the inverted output node OUTbar. Thus, the logic state on the inverted output node OUTbar of level shifter  100  is the inverse of the logic state on the input node IN. Further, the voltage level of the logic high state has been level shifted up from 1.2V to 3.6V. 
     When the logic state on the input node IN transitions from a logic low to a logic high, PMOS transistor M 1  turns off and NMOS transistors M 2  and M 3  turn on. When NMOS transistor M 2  turns on, NMOS transistor M 2  pulls down the voltage on the gate of NMOS transistor M 4 , thereby turning off transistor M 4 . 
     When NMOS transistor M 3  turns on, NMOS transistor M 3  immediately saturates, sinking a peak current given by Equation 1:
 
 IDS   3 =min [( KW   3   /L   3 )( V   DD1   −V   TH ) 2 ; ( KW   5   /L   5 )( V   DD2   −V   TH ) 2   +I   EQ ],  EQ.1
 
where K=μC/2D, W 3  is the width of transistor M 3 , L 3  is the length of transistor M 3 , W 5  is the width of transistor M 5 , L 5  is the length of transistor M 5 , I EQ  is the equivalent current of recharging all the parasitic capacitance associated with node OUTbar, and V TH  is the threshold voltage. (IDS 3 =min[I3; I5] means the minimum of I3 and I5.)
 
     At this point, NMOS transistor M 3  sinks all of the current sourced by PMOS transistor M 5  and a current from the inverted output node OUTbar, thereby pulling down the voltage on the inverted output node OUTbar. As the voltage on the inverted output node OUTbar falls, PMOS transistor M 6  turns on when the gate-to-source voltage of transistor M 6  falls below the threshold voltage of transistor M 6 . 
     Ideally, NMOS transistor M 2  pulls down the voltage on the gate of NMOS transistor M 4  and turns off transistor M 4  before NMOS transistor M 3  can pull down the voltage on the inverted output node OUTbar to turn on PMOS transistor M 6 . This minimizes the amount of shoot-through current (the current sourced by PMOS transistor M 6  that is sunk by NMOS transistor M 4 ). 
     When NMOS transistor M 4  is turned off and PMOS transistor M 6  is turned on, PMOS transistor M 6  begins charging up the voltage on the output node OUT. Thus, at this point, NMOS transistor M 3  is pulling down the voltage on the inverted output node OUTbar while PMOS transistor M 6  is pulling up the voltage on the output node OUT. 
     Under normal operating conditions, as the voltage on the output node OUT continues to rise, PMOS transistor M 5  turns off when the gate-to-source voltage of PMOS transistor M 5  reaches the threshold voltage of PMOS transistor M 5 . When PMOS transistor M 5  turns off, NMOS transistor M 3  pulls the remaining voltage on the inverted output node OUTbar down to ground as PMOS transistor M 6  charges the voltage on the output node OUT up to the second supply voltage VDD 2 . 
     Thus, the logic state on the output node OUT of level shifter  100  is the same as the logic state on the input node IN. Further, the voltage level of the logic high state has been level shifted up from 1.2V to 3.6V. In addition, the logic low state is present on the inverse output node OUTbar. 
     The sizes of transistors M 3  and M 5  are defined to guarantee that NMOS transistor M 3  sinks all of the current sourced by PMOS transistor M 5  after PMOS transistor M 5  saturates. When the KW 5 /L 5  of PMOS transistor M 5  is not small enough in comparison with the KW 3 /L 3  of NMOS transistor M 3 , and the second supply voltage VDD 2  is large enough in comparison with the first supply voltage VDD 1 , then NMOS transistor M 3  can not overdrive the current of PMOS transistor M 5  and the circuit will never flip the states of nodes OUTbar and OUT. 
     Thus, a limitation on KW 5 /L 5  has to be applied from the upper side for a given VDD 1 /VDD 2  range and KW 3 /L 3 , causing the gm 5  of PMOS transistor M 5  to be substantially lower than the gm 3  of NMOS transistor M 3  if the circuit is designed to be working at a second supply voltage VDD 2  that is larger than the first supply voltage VDD 1  condition. 
     To insure that this condition is met, the saturation current IDS 3  can be set to be equal to the saturation current ISD 5  at the minimum possible value of the first supply voltage VDD 1  and the maximum possible value of the second supply voltage VDD 2 . In addition, to insure against a worst case condition, the gate voltage of PMOS transistor M 5  can be assumed to be zero volts. As a result, ISD 5 =(KW 5 /L 5 )(VDD 2 −V TH ) 2 . 
     Setting the saturation current IDS 3  to be equal to the saturation current ISD 5  provides:
 
( KW   3   /L   3 )( VDD   1 − V   TH ) 2 =( KW   5   /L   5 )( VDD   2 − V   TH ) 2 .
 
     Rearranging provides:
 
 W   3   L   5   /L   3   W   5 =( VDD   2 − V   TH ) 2 /( VDD   1 − V   TH ) 2 .
 
     Thus, by utilizing the above ratios, NMOS transistor M 3  is guaranteed to sink all of the current sourced by PMOS transistor M 5  after transistor M 5  saturates. In addition, since NMOS transistors M 3  and M 4  are substantially the same size, and since PMOS transistors M 5  and M 6  are substantially the same size, the same ratios used for transistors M 3  and M 5  are also used for transistors M 4  and M 6 . 
     One of the problems of level shifter  100  is that when level shifter  100  is used with a first supply voltage VDD 1  that is smaller than the second supply voltage VDD 2 , the W 5 /L 5  of PMOS transistor M 5  has to be enough smaller than the W 3 /L 3  of NMOS transistor M 3  to reduce the gm5 of PMOS transistor M 5 . 
     This can be done by increasing the length L 5  of PMOS transistor M 5 . However, as the channel length L 5  increases, the speed of operation decreases. As a result, there is a need for a level shifter that provides high-speed operation between power domains that have a large voltage difference. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram illustrating a prior art level shifter  100 . 
         FIG. 2  is a circuit diagram illustrating an example of a level shifter  200  in accordance with the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 2  shows a circuit diagram that illustrates an example of a level shifter  200  in accordance with the present invention. As shown in  FIG. 2 , level shifter  200  includes an input stage  210  and an output stage  212 . Input stage  210  is similar to level shifter  100  and, as a result, utilizes the same reference numerals to designate the elements that are common to both level shifters. As described in greater detail below, PMOS transistors M 5  and M 6  of level shifter  200  can be formed to source more current than PMOS transistors M 5  and M 6  of level shifter  100 . 
     As further shown in  FIG. 2 , output stage  212  includes an NMOS transistor M 7  and an NMOS transistor M 8 . NMOS transistor M 7  has a source connected to ground VSS, a drain, and a gate connected to the gate of NMOS transistors M 4 . NMOS transistor M 8 , which is substantially the same size as NMOS transistor M 7 , has a source connected to ground VSS, a drain, and a gate connected to the gate of transistor M 3 . 
     Output stage  212  further has a PMOS transistor M 9  and a PMOS transistor M 10 . PMOS transistor M 9  has a source connected to the second voltage source VDD 2 , a drain connected to the drain of NMOS transistor M 7 , and a gate connected to the inverted output node OUTbar. PMOS transistor M 10 , which is substantially the same size as transistor M 9 , has a source connected to the second voltage source VDD 2 , a drain connected to the drain of NMOS transistor M 8 , and a gate connected to the output node OUT. 
     In addition, output stage  212  has a PNP transistor Q 1  and a PNP transistor Q 2 . PNP transistor Q 1  has a base connected to the drains of transistors M 7  and M 9 , an emitter connected to the output node OUT, and a collector connected to ground VSS. PNP transistor Q 2 , which is substantially the same size as transistor Q 1 , has a base connected to the drains of transistors M 8  and M 10 , an emitter connected to the inverted output node OUTbar, and a collector connected to ground VSS. 
     In operation, when a logic low, represented by ground, is present on the input node IN, PMOS transistor M 1  is turned on and NMOS transistors M 2 , M 3 , and M 8  are turned off. When PMOS transistor M 1  is turned on, the first supply voltage VDD 1  is placed on the gates of NMOS transistors M 4  and M 7  which, in turn, turns on NMOS transistors M 4  and M 7 . 
     When NMOS transistor M 4  is turned on, the voltage on the output node OUT is pulled down to ground. When NMOS transistor M 7  is turned on, the voltage on the base of PNP transistor Q 1  is pulled down to ground. When the voltage on the base of PNP transistor Q 1  is pulled down to ground, PNP transistor Q 1  is turned on and also pulls the voltage on the output node OUT down to ground. Thus, as a result of NMOS transistor M 4  and PNP transistor Q 1 , the logic state on the output node OUT of level shifter  200  matches the logic state on the input node IN. 
     When the voltage on the output node OUT is pulled down to ground, PMOS transistors M 5  and M 10  are turned on. When PMOS transistor M 5  is turned on, the second supply voltage VDD 2  is placed on the gate of PMOS transistor M 6  which, in turn, turns off PMOS transistor M 6 . In addition, the second supply voltage VDD 2  is also placed on the inverted output node OUTbar. 
     Thus, the logic state on the inverted output node OUTbar of level shifter  200  is the inverse of the logic state on the input node IN, and is level shifted up from 1.2V to 3.6V. In addition, when PMOS transistor M 10  is turned on, the second supply voltage VDD 2  is placed on the base of PNP transistor Q 2  which, in turn, turns off PNP transistor Q 2 . 
     When the logic state on the input node IN transitions from a logic low to a logic high, PMOS transistor M 1  turns off and NMOS transistors M 2 , M 3 , and M 8  turn on. When NMOS transistor M 2  turns on, NMOS transistor M 2  pulls down the voltage on the gates of NMOS transistors M 4  and M 7 , thereby turning off transistors M 4  and M 7 . 
     When NMOS transistor M 3  turns on, NMOS transistor M 3  immediately saturates and sinks a current IDS 3  from the inverted output node OUTbar. When NMOS transistor M 8  turns on, NMOS transistor M 8  immediately saturates, sinking a current IDS 8 =KW 8 /L 8 (V GS −V TH ) 2 , where K=μC/2D, W 8  is the width of transistor M 8 , L 8  is the length of transistor M 8 , V GS  is the gate-to-source voltage, and V TH  is the threshold voltage. When V GS =VDD 1 , NMOS transistor M 8  completely turns on. As a result, the maximum achievable drain current of NMOS transistor M 8  is IDS 8 =KW 8 /L 8 (VDD 1 −V TH ) 2 . 
     At this point, NMOS transistor M 8  sinks all of the current sourced by PMOS transistor M 10  and a current from the base of PNP transistor Q 2 , thereby pulling down the voltage on the base of PNP transistor Q 2 . As the voltage on the base of PNP transistor Q 2  falls, PNP transistor Q 2  turns on and sinks a current IEC 2  from the inverted output node OUTbar. The current IEC 2  can reach a value of (h21)KW 8 /L 8 (VDD 1 −V TH ) 2 , where h21 is the current gain of transistor Q 2 . Since the drains of NMOS transistor M 8  and PMOS transistor M 10  are not connected to the output nodes (the load), NMOS transistor M 8  can turn on PNP transistor Q 2  relatively quickly. 
     When the voltage difference between the first and second supply voltages VDD 1  and VDD 2  is large enough, the falling voltage on the base of PNP transistor Q 2  causes PMOS transistor M 10  to saturate, outputting a current ISD 10 =KW 10 /L 10 (V SG −V TH ) 2 , where K=μC/2D, W 10  is the width of transistor M 10 , L 10  is the length of transistor M 10 , V SG  is the source-to-gate voltage, and V TH  is the threshold voltage. 
     The sizes of transistors M 8  and M 10  are defined to guarantee that NMOS transistor M 8  sinks all of the current sourced by PMOS transistor M 10  after PMOS transistor M 10  saturates. To insure that this condition is met, the saturation current IDS 8  can be set to be equal to the saturation current ISD 10 . In addition, to insure against a worst case condition, the gate voltage of PMOS transistor M 10  can be assumed to be zero volts. As a result, ISD 10 =(KW 10 /L 10 )(VDD 2 −V TH ) 2 +IbQ 2 , where IbQ 2 , which is required to overdrive NMOS transistor M 8 , is the maximum possible base current of transistor Q 2 . 
     Setting the saturation current IDS 8  to be equal to the saturation current ISD 10 +IbQ 2  provides:
 
 KW   8   /L   8 ( VDD   1 − V   TH ) 2   =KW   10   /L   10 ( VDD   2 − V   TH ) 2   +IbQ   2 ,
 
where IbQ 2 =(h21 −1 )KW 5 /L 5 (VDD 2 −V TH ) 2 .
 
     Rearranging provides:
 
 W   8   L   10   /L   8   W   10 =(1+( W   5   L   10   /L   5   W   10   h 21))( VDD   2 −V TH ) 2 /( VDD   1 −V TH ) 2 .
 
     Thus, by utilizing the above ratios, NMOS transistor M 8  is guaranteed to sink all of the current sourced by PMOS transistor M 10  and transistor Q 2  after transistor M 10  saturates. 
     As noted above, when both NMOS transistor M 3  and PNP transistor Q 2  are turned on, transistors M 3  and Q 2  sink currents IDS 3  and IEC 2  from the inverted output node OUTbar. The currents IDS 3  and IEC 2 , in turn, pull down the voltage on the inverted output node OUTbar. As the voltage on the inverted ouput node OUTbar falls, PMOS transistor M 9  turns on when the gate-to-source voltage of transistor M 9  falls below the threshold voltage of transistor M 9 . 
     When NMOS transistor M 7  is turned off and PMOS transistor M 9  is turned on, PMOS transistor M 9  pulls up the voltage on the base of PNP transistor Q 1 , thereby turning off PNP transistor Q 1 . Since the drains of NMOS transistor M 7  and PMOS transistor M 9  are not connected to the output nodes (the load), PMOS transistor M 9  can turn off PNP transistor Q 1  relatively quickly. 
     In addition to PMOS transistor M 9 , PMOS transistor M 6  also turns on as the voltage on the inverted output node OUTbar falls and the gate-to-source voltage of transistor M 6  falls below the threshold voltage of transistor M 6 . Ideally, NMOS transistor M 2  pulls down the voltage on the gate of NMOS transistor M 4  and turns off transistor M 4  before NMOS transistor M 3  and PNP transistor Q 2  can pull down the voltage on the inverted output node OUTbar to turn on PMOS transistor M 6 . This minimizes the amount of shoot-through current (the current sourced by PMOS transistor M 6  that is sunk by transistor M 4 ). 
     When NMOS transistor M 4  is turned off and PMOS transistor M 6  is turned on, PMOS transistor M 6  begins charging up the voltage on the output node OUT. Thus, at this point, NMOS transistor M 3  and PNP transistor Q 2  pull down the voltage on the inverted output node OUTbar while PMOS transistor M 6  pulls up the voltage on the output node OUT. 
     As above, when the voltage difference between the first and second supply voltages VDD 1  and VDD 2  is large enough, the falling voltage on the inverted output node OUTbar and the rising voltage on the output node OUT cause PMOS transistor M 5  to saturate and output a current ISD 5 . 
     As the voltage on the output node OUT continues to rise, PMOS transistors M 5  and M 10  turn off when the gate-to-source voltages of PMOS transistors M 5  and M 10  reach the threshold voltages of PMOS transistors M 5  and M 10 . When PMOS transistor M 5  turns off, NMOS transistor M 3  and PNP transistor Q 2  pull the remaining voltage on the inverted output node OUTbar down to ground as PMOS transistor M 6  charges the voltage on the output node OUT up to the second supply voltage VDD 2 . Thus, the logic high state on the output node OUT is the same as the logic high state on the input node IN, and is level shifted up from 1.2V to 3.6V. In addition, the logic low state is present on the inverse output node OUTbar. 
     One of the advantages of the present invention is that when the logic state on the input node IN transitions from a logic low to a logic high, PNP transistor Q 2  assists NMOS transistor M 3  in pulling down the voltage on the inverted output node OUTbar. As a result, NMOS transistor M 3  and PNP transistor Q 2  can sink a substantial amount of current from the inverted output node OUTbar, thereby significantly increasing the speed by which the voltage on the output node OUTbar is pulled down. 
     Another advantage of the present invention is that the size of PMOS transistor M 5  can be increased to source a larger amount of current when transistor M 5  saturates. Unlike the prior art, where the saturation current of PMOS transistor M 5  was limited by the saturation current of NMOS transistor M 3 , PMOS transistor M 5  can be sized to provide a larger saturation current because NMOS transistor M 3  and PNP transistor Q 2  both pull down the voltage on the inverted output node OUTbar. 
     As noted above, PMOS transistor M 5  and PMOS transistor M 6  are substantially the same size. As a result, PMOS transistor M 6  can also be formed to be larger which, in turn, substantially reduces the amount of time required to charge up the output node OUT. Thus, the present invention both reduces the amount of time required to pull down the voltage on the inverted output node OUTbar, and the amount of time required to pull up the voltage on the output node OUT. 
     A similar operation occurs when the logic state on the input node IN transitions from a logic high to a logic low. In this case, PMOS transistor M 1  turns on and NMOS transistors M 2 , M 3 , and M 8  turn off. When PMOS transistor M 1  turns on, PMOS transistor M 1  pulls up the voltage on the gates of NMOS transistors M 4  and M 7 , thereby turning on transistors M 4  and M 7 . 
     When NMOS transistor M 4  turns on, NMOS transistor M 4  immediately saturates and sinks a current IDS 4  from the output node OUT. When NMOS transistor M 7  turns on, NMOS transistor M 7  immediately saturates, sinking a current IDS 7 =KW 7 /L 7 (V GS −V TH ) 2 , where K=μC/2D, W 7  is the width of transistor M 7 , L 7  is the length of transistor M 7 , V GS  is the gate-to-source voltage, and V TH  is the threshold voltage. When V GS =VDD 1 , NMOS transistor M 7  completely turns on. As a result, the maximum achievable drain current of NMOS transistor M 7  is IDS 7 =KW 7 /L 7 (VDD 1 −V TH ) 2 . 
     At this point, NMOS transistor M 7  sinks all of the current sourced by PMOS transistor M 9  and a current from the base of PNP transistor Q 1 , thereby pulling down the voltage on the base of PNP transistor Q 1 . As the voltage on the base of PNP transistor Q 1  falls, PNP transistor Q 1  turns on and sinks a current IEC 1  from the output node OUT. Since the drains of NMOS transistor M 7  and PMOS transistor M 9  are not connected to the output nodes (the load), NMOS transistor M 7  can turn on PNP transistor Q 1  relatively quickly. 
     When the voltage difference between the first and second supply voltages VDD 1  and VDD 2  is large enough, the falling voltage on the base of PNP transistor Q 1  causes PMOS transistor M 9  to saturate, outputting a current ISD 9 =KW 9 /L 9 (V SG −V TH ) 2 , where K=μC/2D, W 9  is the width of transistor M 9 , L 9  is the length of transistor M 9 , V SG  is the source-to-gate voltage, and V TH  is the threshold voltage. 
     Like transistors M 8  and M 10 , the sizes of transistors M 7  and M 9  are defined to guarantee that NMOS transistor M 7  sinks all of the current sourced by PMOS transistor M 9  after PMOS transistor M 9  saturates. To insure that this condition is met, the saturation current IDS 7  can be set to be equal to the saturation current ISD 9  plus the base current of transistor Q 1 . In addition, to insure against a worst case condition, the gate voltage of PMOS transistor M 9  can be assumed to be zero volts. As a result, ISD 9 =(KW 9 /L 9 )(VDD 2 −V TH ) 2 . 
     Setting the saturation current IDS 7  to be equal to the saturation current ISD 9  plus the base current of transistor Q 1  provides W 7 L 9 /L 7 W 9 =(1+(W 6 L 9 /L 6 W 9 h21))(VDD 2 −V TH ) 2 /(VDD 1 −V TH ) 2 , where the ratio W 7 L 9 /L 7 W 9  equals the ratio W 8 L 10 /L 8 W 10 . Thus, by utilizing the above ratios, NMOS transistor M 7  is guaranteed to sink all of the current sourced by PMOS transistor M 9  after transistor M 9  saturates. 
     As noted above, when both NMOS transistor M 4  and PNP transistor Q 1  are turned on, transistors M 4  and Q 1  sink currents IDS 4  and IEC 1  from the output node OUT. The currents IDS 4  and IEC 1 , in turn, pull down the voltage on the output node OUT. As the voltage on the output node OUT falls, PMOS transistor M 10  turns on when the gate-to-source voltage of transistor M 10  falls below the threshold voltage of transistor M 10 . 
     When NMOS transistor M 8  is turned off and PMOS transistor M 10  is turned on, PMOS transistor M 10  pulls up the voltage on the base of PNP transistor Q 2 , thereby turning off PNP transistor Q 2 . Since the drains of NMOS transistor M 8  and PMOS transistor M 10  are not connected to the output nodes (the load), PMOS transistor M 10  can turn off PNP transistor Q 2  relatively quickly. 
     In addition to PMOS transistor M 10 , PMOS transistor M 5  also turns on as the voltage on the output node OUT falls and the gate-to-source voltage of transistor M 5  falls below the threshold voltage of transistor M 5 . Since transistor M 3  is connected to the input node IN, transistor M 3  is turned off before PMOS transistor M 5  turns on. As a result, no shoot through current from transistor M 5  to transistor M 3  exists when the logic state on the input node IN transitions to a logic low. 
     When NMOS transistor M 3  is turned off and PMOS transistor M 5  is turned on, PMOS transistor M 5  begins charging up the voltage on the inverted output node OUTbar. Thus, at this point, NMOS transistor M 4  and PNP transistor Q 1  pull down the voltage on the output node OUT while PMOS transistor M 5  pulls up the voltage on the inverted output node OUTbar. 
     When the voltage difference between the first and second supply voltages VDD 1  and VDD 2  is large enough, the falling voltage on the output node OUT and the rising voltage on the inverted output node OUTbar cause PMOS transistor M 6  to saturate and output a current ISD 6 . 
     As the voltage on the inverted output node OUTbar continues to rise, PMOS transistors M 6  and M 9  turn off when the gate-to-source voltages of PMOS transistors M 6  and M 9  exceed the threshold voltages of PMOS transistors M 6  and M 9 . When PMOS transistor M 6  turns off, NMOS transistor M 4  and PNP transistor Q 1  pull the remaining voltage on the output node OUT down to ground as PMOS transistor M 5  charges the voltage on the inverted output node OUTbar up to the second supply voltage VDD 2 . Thus, the logic low state on the output node OUT is the same as the logic low state on the input node IN. In addition, the logic high state is present on the inverse output node OUTbar, and is level shifted up from 1.2V to 3.6V. 
     The same advantages of the present invention apply when the logic state on the input node IN transitions low as when the logic state transitions high. In this case, PNP transistor Q 1  assists NMOS transistor M 4  in pulling down the voltage on the output node OUT. As a result, NMOS transistor M 4  and PNP transistor Q 1  can sink a substantial amount of current from the output node OUT, thereby significantly increasing the speed by which the voltage on the output node OUT is pulled down. 
     In addition, as noted above, the size of PMOS transistor M 5  can be increased to source a larger amount of current, thereby substantially reducing the amount of time required to charge up the inverted output node OUTbar. Thus, the present invention both reduces the amount of time required to pull up the voltage on the inverted output node OUTbar, and the amount of time required to pull down the voltage on the output node OUT. 
     Further, the beta of PNP transistor Q 1  can be adjusted to sink additional current to enable level shifter  200  to provide high speed operation when the third supply voltage, which is greater than the second supply voltage VDD 2 , is used in lieu of the second supply voltage VDD 2 . 
     It should be understood that the above descriptions are examples of the present invention, and that various alternatives of the invention described herein may be employed in practicing the invention. Thus, it is intended that the following claims define the scope of the invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.