Abstract:
Disclosed herein are a method and structure, in an integrated circuit having at least one delay locked loop circuit (DLL), for determining a Lock Latency value of a DLL output clock signal. The disclosed method includes temporarily disabling a first clock signal in response to the DLL doing at least one of approaching and acquiring lock; and then thereafter determining a Lock Latency value in response to examining a DLL output clock signal generated in response to the first clock signal.

Description:
FIELD OF THE INVENTION 
     This invention relates to semiconductor devices and more particularly, to digital delay locked loops for use in high frequency clock synchronization applications. 
     BACKGROUND OF THE INVENTION 
     In synchronous dynamic random access memory (SDRAM) applications, the inherent analog delay between an external, system or reference clock and the time output data is always a concern. Even a slight delay may be large enough to make a following clock cycle overlap the data, thus causing the data not to be ready at the output during one cycle. This inherent internal delay must therefore be selectively accelerated according to the necessary frequency to resolve the problem. This leads to a new problem of achieving synchronization between the internal clock, which controls the output path, and the correct edge of the external clock. This is often referred to as a “Lock Latency”, which is defined as relative time displacement between a given external clock edge (parent) and the associated internal DLL generated clock edge (child). 
     Conventional double data rate (DDR) synchronous dynamic random access memories (SDRAM) employ a plurality of delay locked loop circuits (DLL). These DLL circuits are employed to synchronize delay between two signals, such as the clock signal and a delayed clock signal. Analog delay locked loops have been employed in the past to perform the synchronization, which are comprised of a delay chain having the delay of its elements varied by analog bias voltages supplied by a phase detector. In digital systems such as memories, microprocessors and application specific integrated circuits, these types of delay locked loops introduce analog design complications in a mainly digital design, and therefore are avoided. Digital delay locked loops use a digitally adjustable delay line. Digital information is used to either include or exclude a certain number of delay elements within a delay chain. Although digital delay locked loops have a much higher jitter than analog delay locked loops, their ease of implementation in a digital system makes them the preferred solution in most digital applications. As digital delay locked loops become more prevalent, the need increases for a method and apparatus that can process transmitted/recieved signals synchronously with an I/O data stream. 
     SUMMARY OF THE INVENTION 
     Acccording to an aspect of the present invention, in an integrated circuit having at least one delay locked loop circuit (DLL), a method is provided for determining a Lock Latency value of a DLL output clock signal. Such method includes temporarily disabling a first clock signal in response to the DLL doing at least one of approaching and acquiring lock; and then thereafter determining a Lock Latency value in response to examining a DLL output clock signal generated in response to the first clock signal. 
     According to another aspect of the invention, a method and structure are provided for producing edge-aligned output signal(s) with respect to an external input clock (and each other when more than one output signal present). Such method can be applied in a double data rate (DDR) synchronous dynamic random access memory (SDRAM) environment with at least one delay locked loop circuit (DLL) and having one or more output signals and at least one external input clock. According to such aspect of the invention, a lock pulse generator is established using the external input clock. Any incoming signal(s) are then analyzed by using a Lock Latency mechanism to determine if the system has acquired lock. Then, a Lock Latency value is determined based on the incoming signal(s). The Lock Latency value is maintained until there is a frequency change in the external clock. The output signal(s) cycle(s) can then be altered based on the Lock Latency value when appropriate as to edge-align them with respect to the external input clock (and other output signal(s) when there is more than one output signal present). 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is an illustration of a lock detection circuit as per one embodiment of the present invention; and 
         FIG. 2  shows the associated timing diagram for FIG.  1 . 
         FIG. 3  is a timing diagram illustrating a method for distinguishing between Lock Latency values of 2 and 3, according to an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention provides in one embodiment a DDR SDRAM chip with the ability to ascertain the Lock Latency of it&#39;s on board Delay Locked Loop (DLL). 
     By design many DLL circuits create an external clock edge which is shifted (later) in time with respect to the parent externally supplied clock edge. Due to the cyclic nature of clocking signals, the magnitude of the insertion delay created by the DLL is quantized into multiples of clock cycles. For example, an external parent clock edge and it&#39;s associated internally generated DLL edge maybe displaced relative to each other by 2 clock cycles. In this case we would say the DLL has a Lock Latency of 2 (clock cycles). 
     In order to enhance performance and maintain functionality of the particular DLL, the knowledge of its Lock Latency is required. That is to say within each particular DLL architecture some values of Lock Latency are usable only and the problem is to know of the possible usable Lock Latency values, which one the DLL has settled on. Once the DDR SDRAM has knowledge of its current Lock Latency, it can auto-adjust internal circuits so that functionality is maintained over all possible valid Lock Latency values. 
     In the Double Data Rate (DDR) SDRAM memory chip, the data strobe signal (DQS) is transmitted/received synchronously with I/O Data for READ/WRITE operations respectively. The DQS signal is edge-aligned with output data for a memory READ operation and center-aligned with input data for a memory chip WRITE operation. Furthermore, DQS must switch one cycle earlier than associated I/O Data during a READ operation. Thus creating the required DOS Preamble as defined by the DDR specification. The focus here must be on the memory Read operation. Wherein the DDR SDRAM output signals (DQS and I/O Data), need to be edge-aligned not only with each other but also with the external input clock signals (CLK/CLKb). 
     In order to achieve the required edge alignments, DDR SDRAM chips employ an on board Delay Locked Loop (DLL). The DLL creates a precisely timed internal clock signal which is used by the Data Path/Output Driver circuits to create the required edge-alignment at the output data pins and the input clk pins. The internally generated DLL clock signal which meets these requirements is hereinafter referred to as a Latency Adjusted Clock. The edge alignment requirement imposes a constraint between the Latency Adjusted Clock and the externally supplied input clock (CLK/CLKb). The fact that they are linked by the alignment criteria which must be maintained over consecutive cycles, means that the signals have X (or X+360) degrees phase relationship with respect to each other. Wherein ‘X’ is phase shift required by the Latency Adjusted clock to produce the desired zero phase/tAC at the I/O pins. Since this is a periodic system, a phase relationship of X+(n*360 deg) where n=0, 1, 2, etc. are indistinguishable from a phase point of view. Note that in a cycle based system, 360 deg=1 cycle and n*360 deg=n*cycle and all would meet the zero tAC alignment criteria. However, it is important to point out that while n-cycles meets the zero phase requirement and n=1 vs. n=2, n=3, . . . , n=infinity cycles are indistinguishable from a phase relationship, not all values of ‘n’ are allowable solutions. Indeed, even though n=1 and n=2, or even taken to the limit, n=infinity, maybe indistinguishable in the frequency/phase domain, they are very much distinguishable in the time domain. Large values of ‘n’ are simply not feasible for a DLL that uses a Linear Delay Line. Simply because it can not afford the resources required to store the large time shifts dictated by large values of ‘n’. In addition, as ‘n’ increases so does the initial propagation delay through the DLL. Given today&#39;s DDR SDRAM spec and our current DLL architecture, if ‘n’&gt;2 the initial propagation through the DLL would cause a failure of the Active Power Down Exit specification of 1 cycle. The term ‘initial propagation’ is used to describe the propagation time associated with reinstating a full-speed steady-state signal within the DLL signal pathway. For performance reasons many of the current DLL architectures do not always maintain a full-rate or otherwise steady-state signal in all operational modes. 
     In some of the present DDR SDRAM specifications, the chip can operate at more than one frequency (i.e. 83 MHz to 166 MHz), the DLL can either be locked in 1 or 2 cycles and still meet the application specification. However, the determination of Lock by the DLL in 1 cycle, 2 cycles, or more cycles depends on a number of factors, such as:
         1) tAC delay=Total on chip delays=delay of the input clock receivers+Data Path circuits and clock tree wire delays+Off Chip Driver (OCD) delay+chip package delay+etc.;   2) Operating clock frequency—at higher frequencies, the DLL needs more time to compensate for the tAC delay therefore forcing the DLL to lock in 2, 3, or more cycles;   3) Insertion delay of the DLL—the larger the minimum Insertion delay associated with the Delay Line, the high the probability that the DLL will have to move to the next cycle of Lock to compensate for this insertion delay.       

     Taken as a collection of variables, the above itemized issues leads to an unknown Lock Latency within the DLL. That is, given one set of conditions, the resulting Lock Latency maybe 1, 2, 3 or more. It is therefore desirable to know what the Lock value is, so that the internal Data Path circuits can track and compensate for this variability and thus preserve functionality. Even though many of the current DLL architectures are capable of locking to values greater than 2, the only valid values in many of the current specifications (such as the JEDEC specifications) remain as a 1 or a 2. With this in mind, the embodiment of the invention shown in  FIGS. 1 and 2  described below only distinguishes between Lock Latency values of 1 and 2. However, following the description of this embodiment, it will be further described how the concepts of the present invention are applied to detect any number of different Lock Latency values. 
     In one embodiment of the present invention as shown in  FIG. 1 , a lock detection circuit is presented.  FIG. 2  provides an example of the associated timing diagram for FIG.  1 . The embodiment shown in  FIG. 1  illustrates the lock detection circuit in a DDR SDRAM environment. 
     In  FIG. 2 , before the DLL achieves a lock acquisition, only the VCLK pulse generator is running as shown at ( 210 ). When the DLL first locks, as shown at ( 120 ) in  FIG. 1 , the signal LOCKED is asserted high, shown at ( 220 ) in FIG.  2 . This signal, in turn, causes the signal DISABLE_PG to turn high at point  230  (after going through the electronic components shown in  FIG. 1  as  125 ,  126  and  127 ). In response, the VCLK pulse generator turns off for one complete cycle as shown at ( 212 ) in FIG.  2 . Also, in response to DISABLE_PG, a detection window is generated (LOCK_DETECT signal) as shown in  FIG. 1  at  140 , which is one cycle wide and shifted by a half cycle, as shown at ( 240 ) in FIG.  2 . During this detection window, the Lock Detection circuit examines the DLL output (shown at ( 150 ) in  FIG. 1 ) signal, DLL_OUT. If the DLL has a Lock Latency of one cycle as shown at ( 250 ) in  FIG. 2 , then the LOCK_ 2  signal stays low as shown at ( 270 ) in  FIG. 2 , indicating that there was no clock pulse present in the detection window. If the DLL has a Lock Latency of two cycles, the LOCK — 2 signal will go high, indicating the presence of a pulse in the detection window. The pulse is present because it is already in the delay line before the DISABLE_PG signal becomes active, and then a delayed version of it arrives in the DLL_OUT signal at a time when the detection window is open. After the DLL completely locks, the RF_LOCKED signal, shown at (180) in  FIG. 1 , is asserted high. This, in turn, completes the Lock Latency detection step. The resulting Lock Latency value is held by a latch. As such, the Lock Latency status is only assessed at DLL initialization time. 
     In the embodiment shown in  FIGS. 1 and 2 , it is preferable that the DDR SDRAM has a power up initialization procedure. During the initialization procedure, the DLL is given adequate clock cycles, preferably around 200 cycles, to establish a stable lock with the external clock. Once lock is achieved, the Lock Detection circuit will analyze the supplied signals and determine the Lock Latency. This information is latched and maintained until the DLL is reset. If the operating clock frequency is changed, the DLL needs to be reset and re-locked in order for the Lock Detection function to work properly. 
     The foregoing description relates to a circuit for distinguishing between Lock Latency values of 1 and 2. Modifications to the circuit will now be described for determining Lock Latency values greater than two. Conceptually, the method is to disable DLLIN (the input clock signal of the DLL) for at least as long as one cycle less than the maximum Lock Latency value, and then set up one or more detection windows to examine the DLL output clock signal, at different times, to distinguish between the Lock Latency values of interest. For example, if it is desired to distinguish between Lock Latency values of 1, 2, and 3, the DISABLE_PG signal  130  must remain high for two cycles of VCLK and at least two detection windows are needed, the first detection window to distinguish between Lock Latencies of 1 and 2, and the second detection window to distinguish between Lock Latencies of 2 and 3. Further, the DLL output clock signal must be examined in both detection windows. If, however, in a particular system design, a Lock Latency of 1 will not occur, but values of 2 and 3 are possible, there need not be a detection window to distinguish between Lock Latencies of 1 and 2, but only a detection window for distinguishing between values of 2 and 3. 
       FIG. 3  illustrates a timing diagram for distinguishing between Lock Latency values of 2 and 3. The method illustrated by this timing diagram is used in conjunction with the method exemplified in  FIG. 2  to detect Lock Latencies of 1, 2 and 3, as described as follows. As illustrated in  FIG. 3 , the DISABLE_PG signal  330  remains high for two cycles, instead of one cycle which is shown in FIG.  2 . This causes DLLIN  360  to turn off for two cycles of VCLK  210 . In this embodiment, it will be appreciated that this modified two cycle long signal DISABLE_PG  330  is the same signal for detemining Lock Latencies of 2 or 3, as shown in  FIG. 3 , and also used for determining Lock Latencies of 1 or 2 (FIG.  2 ), except as now modified to be two cycles long. 
     The second detection window (LOCK_DETECT — 3)  340 , varies from a first detection window (LOCK_DETECT)  240  of  FIG. 2  in that it starts later by one cycle of VCLK  210 , in order to check for presence of a later pulse in DLL_OUT at time  350 . Thus, when the Lock Latency of the DLL is 2, the DLLIN clock signal  360  will have no pulse present at time  312 . The absence of the DLLIN pulse, in turn, will be reflected in signal DLL_OUT still having no pulse present in the output, at time  350 , two cycles of the new output clock frequency later. In such case, the signal LOCK — 3 remains low, indicating a Lock Latency value of 2. If, at the same time, a pulse is present in the first detection window (LOCK_DETECT)  240 , then, as described above, the Lock Latency value is determined to be two, and LOCK — 2 ( 270 ) is raised to indicate the same. If however, no pulse is present in either detection window, LOCK_DETECT or LOCK_DETECT — 3), then the Lock Latency value is determined to be one, and neither LOCK — 2 nor LOCK — 3 are raised. 
     On the other hand, when the Lock Latency of the DLL is three, there will be a pulse at time  350  in the output clock signal DLL_OUT, because a pulse is present in the delay line already from a time prior to DISABLE_PG  330  being raised, and has now emerged in DLL_OUT. In such case, the pulse will be detected during the second detection window  340 , and the signal LOCK — 3 will be raised to indicate a Lock Latency value of three. 
     Those skilled in the art will understand the modifications to be made to the circuitry shown in  FIG. 1  to permit operation according to the timing diagram of FIG.  3 . In addition, it will be understood the modifications required for determining any arbitrary number of Lock Latency values, by making modifications, as described in the foregoing relative to FIG.  3 . 
     While the invention has been described in accordance with certain preferred embodiments thereof, those skilled in the art will understand the many modifications and enhancements which can be made thereto without departing from the true scope and spirit of the invention, which is limited only by the claims appended below.