Abstract:
A low-complexity, high accuracy model of a CPU power distribution system has been developed. The model includes models of multiple power converters that input to a board model. The board model then inputs to a package model. Finally, the package model inputs to a chip model. The model provides a high degree of accuracy with an acceptable simulation time.

Description:
BACKGROUND OF INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The invention relates generally to circuitry design, more specifically, the invention relates to modeling of power distribution systems for a central processing unit system.  
           [0003]    2. Background Art  
           [0004]    As today&#39;s computer systems operate at frequencies exceeding 1 GHz, the demands on internal power supplies also increase. For instance, as the technology is scaled smaller and faster, the power supply voltage must decrease. However, as the internal clock rates rise and more functions are integrated into microprocessors and application specific integrated circuits (ASICs), the total power consumed must increase. These demands require the internal power supply to respond quickly and reliably without significant overshoot, undershoot, or ringing of the supplied voltage.  
           [0005]    Obviously, the design of the power system is critical to meeting these stringent requirements. A critical part of the design process is the modeling of the system. Typically, a model is used to simulate the system&#39;s performance so that design decisions can be made based on its results. The key questions in developing a model are: (1) the level of complexity it will entail; and (2) the degree of accuracy it will provide with its results. As a general rule, a more complex model has greater accuracy in its results. However, a complex model may take several days of operation just to simulate a few micro-seconds of system time.  
           [0006]    [0006]FIG. 1 shows a prior art depiction of a central processing unit (CPU) power distribution system  10  with power system components that must be simulated by such a model. The main circuit board  12  itself is the central platform with the system power supply board  14  and system ground board  16  layered underneath. Attached to the surface of the board  10  is the circuit package  18  that holds the central processing unit  20  or “chip”. Also shown are various components of the power system including: high-capacity ceramic capacitors  22 ; an air-core inductor  24 ; a regulating integrated circuit  26 ; switching transistors  28 ; a mid-capacity tantalum capacitor  30 ; and low-capacity electrolytic capacitors  32 .  
           [0007]    Of these components, the model of the chip  20  is the most difficult to develop. The components on the chip that must be modeled include the current draw of the chip as well as its intrinsic capacitance. The current draw generally includes characteristics such as average, maximum, and minimum currents at different processes and speed grades. Additionally, the chip model should allow multiple different current spikes at different known magnitudes and frequencies.  
           [0008]    Modeling the current draw of the chip is accomplished by several methods including the use of transistors, resistors, or current sources. A transistor based model requires a tremendous amount of transistors to model the current performance over time. Additionally, the different transient currents must be included in the model. Also, the parasitic capacitance must be sized to be close to the actual value on the chip. The result is a complex circuit that does not scale well and has difficulty maintaining the proper amount of intrinsic capacitance. Finally, the circuit is so complicated that it has a simulation time that unacceptably long.  
           [0009]    A resistor based model uses resistance controlled voltage to model the current performance over time. It is relatively easy to determine the necessary voltage and resistance that causes the average, maximum, and minimum currents. The intrinsic capacitance is easily modeled as a voltage controlled capacitor. However, the current draw during transient sweeps is hard to control when attempting to overlay different frequency and magnitude spikes. An additional problem involves modeling transient currents. The voltage controlled resistors often cause the transient currents to have a higher than accurate frequency. The result is that while a resistor based model has a short simulation time, it is not accurate in certain circumstances.  
           [0010]    A current source based model uses explicit current sources to model the current performance over time. A voltage controlled capacitor is used to model the intrinsic capacitance. This model has an even faster simulation time than the resistor based model. However, the current sources cannot be used in the AC sweeps since they are not represented as resistors in the AC domain. As with the resistor based model, the current source based model has excellent simulation time but it is not accurate in certain circumstances.  
         SUMMARY OF INVENTION  
         [0011]    In some aspects, the invention relates to an apparatus for modeling a power system of a microprocessor based system, comprising: a plurality of power converter models; a board model that receives an output from the plurality of power converter models; a package model that receives an output from the board model; and a chip model that receives an output from the package model  
           [0012]    In other aspects, the invention relates to an apparatus for modeling a power system of a microprocessor based system, comprising: means for modeling a power converter; means for modeling a board that receives an output from the means for modeling a power converter; means for modeling a package that receives an output from the means for modeling a board; and means for modeling a chip that receives an output from the means for modeling a package.  
           [0013]    In other aspects, the invention relates to a method for modeling a power system of a microprocessor based system, comprising: modeling a plurality of power converters; modeling a board that receives an output from the plurality of power converter; modeling a package that receives an output from the board; and modeling a chip that receives an output from the package.  
           [0014]    In other aspects, the invention relates to an apparatus for modeling a power system of a microprocessor chip, comprising: a plurality of bump and grid models; a plurality of section models that receives a plurality of outputs from the plurality of bump and grid models; and a plurality of channel models that interconnect the plurality of section models.  
           [0015]    In other aspects, the invention relates to an apparatus for modeling a power system of a microprocessor chip, comprising: means for modeling a plurality of bumps and grids; means for modeling a plurality of sections that receives a plurality of outputs from the plurality of bumps and grids; and means for modeling a plurality of channels that interconnect the plurality of sections.  
           [0016]    In other aspects, the invention relates to a method for modeling a power system of a microprocessor chip, comprising: modeling a plurality of bump and grid components; modeling a plurality of chip sections that receives an output from the plurality of bump and grid components; and modeling a plurality chip channels that interconnect the plurality of chip sections.  
           [0017]    Other aspects and advantages of the invention will be apparent from the following description and the appended claims.  
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0018]    [0018]FIG. 1 shows a prior art depiction of a central processing unit (CPU) power distribution system with power system components.  
         [0019]    [0019]FIG. 2 shows a block diagram of a power system model in accordance with one embodiment of the present invention.  
         [0020]    [0020]FIG. 3 shows a circuit model of a DC to DC converter in accordance with one embodiment of the present invention.  
         [0021]    [0021]FIG. 4 shows a circuit model of a board in accordance with one embodiment of the present invention.  
         [0022]    [0022]FIG. 5 shows a circuit model for a bulk capacitor or a ceramic capacitor of the board model in accordance with one embodiment of the present invention.  
         [0023]    [0023]FIG. 6 shows a circuit model for a package model in accordance with one embodiment of the present invention.  
         [0024]    [0024]FIG. 7 shows a circuit model for a package capacitor of a package model in accordance with one embodiment of the present invention.  
         [0025]    [0025]FIG. 8 a  shows a block diagram of bump and grid models of a chip model in accordance with one embodiment of the present invention.  
         [0026]    [0026]FIG. 8 b  shows a block diagram of channel models and section models of a chip model in accordance with one embodiment of the present invention.  
         [0027]    [0027]FIG. 9 a  shows a circuit model for a bump and a grid of a chip model in accordance with one embodiment of the present invention.  
         [0028]    [0028]FIG. 9 b  shows a circuit model for a section segment of a chip model in accordance with one embodiment of the present invention.  
         [0029]    [0029]FIG. 9 c  shows a circuit model for a channel segment of a chip model in accordance with one embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION  
       [0030]    Exemplary embodiments of the invention will be described with reference to the accompanying drawings. Like items in the drawings are shown with the same reference numbers.  
         [0031]    [0031]FIG. 2 shows a block diagram  36  of a model for a power system in accordance with one embodiment of the present invention. The model begins with four DC to DC converters  38   a - 38   d  that are connected to the board  42 . The converters  38   a - 38   d  are each connected to the board  42  with a separate path or “via”. These vias are labeled V DC1    40   a , V DC2    40   b , V DC3    40   c , and V DC4    40   d . Once the vias  40   a - 40   d  reach the board  42 , they are combined into a single via labeled V BOARD    44 . This path  44  connects the board  42  to the package  46 . Finally, a via labeled V PACKAGE    48  connects the package  46  to the chip  50 . Each of the blocks for the DC to DC converters  38   a - 38   d , the board  42 , the package  46 , and the chip  50  represents a model of that specific component of the power system. Each of these models is made up of various circuitry devices that simulate the performance of the respective components. The selection of the specific values of these circuitry devices is accomplish by methods well known in the art. When models of the components  38   a - 38   d ,  42 ,  46 ,  50  are arranged and connected in the manner shown in FIG. 2, they will properly simulate the function and performance of the power system accurately and in an acceptable simulation timeframe.  
         [0032]    While FIG. 2 shows four DC to DC converters  38   a - 38   d , one board  42 , one package  46 , and one chip  50 , it is fully intended that the scope of this invention covers embodiments with differing numbers of each of these components. For example, in a parallel processing environment, the system may have a plurality of package and chip blocks. The end result is that different arrangements and numbers of the component blocks shown in FIG. 2 are dependent upon the components present in the system to be modeled and are not limited to the embodiment shown here. Nevertheless, it is conceivable that multiple components (e.g., multiple chips in a parallel processing system) could be modeled by a single component block by simply adjusting the values of the circuitry devices in the respective block to represent the cumulative characteristics of multiple components.  
         [0033]    [0033]FIG. 3 shows a schematic  52  of a circuit model of a DC-DC converter in accordance with one embodiment of the present invention. The schematic  52  includes a DC voltage supply source  54  that is connected in series to a resistor R FLAT    56  and an inductor L SLEW    58 . As shown in the figure, R FLAT    56  and L SLEW    58  and connected to each other in parallel. R FLAT    56  represents the equivalent series resistance (ESR) of the converter capacitor, while L SLEW    58  serves to limit the current flow from the voltage supply  54 . Both R FLAT    56  and L SLEW    58  are connected in series to L OUT    60  and R OUT    62  that represent the output inductance value and the output resistance value respectively. R OUT    62  is connected to board (not shown) through the via V DC#   40 . The values of each supply source  54 , each resistor  56 ,  62 , and each inductor  58 ,  60  are selected to accurately simulate the performance of its specific modeled component.  
         [0034]    [0034]FIG. 4 shows a schematic of a circuit model of a board in accordance with one embodiment of the present invention. Four separate vias  40   a - 40   d  are shown as inputs to the board. These vias, labeled V DC1    40   a , V DC2    40   b , V DC3    40   c , and V DC4    40   d , are connected to their respective DC to DC converter as shown in FIG. 2. On the board, each via  40   a - 40   d  is connected to its own pathway. The pathways are identical to each other and the are connected in parallel. The pathways for each via include three resistors connected in series: R BOARD1    68   a ; R BOARD2    70   a ; and R BOARD3    72   a . Also included is a bulk capacitor labeled C BULK    74   a  and a ceramic capacitor labeled CCERAMIC  76   a . The bulk capacitor  74   a  is connected to the system ground between R BOARD1    68   a  and R BOARD2    70   a , while the ceramic capacitor  76   a  is connected to the system ground between R BOARD2    70   a  and R BOARD3    72   a . In the pathway, R BOARD1    68   a  represents the resistance between the DC to DC converter and the bulk capacitor  74   a . R BOARD2    70   a  represents the resistance between the bulk capacitor  74   a  and the ceramic capacitor  76   a . R BOARD3    72   a  represents the resistance between the ceramic capacitor  76   a  and the perforated plane.  
         [0035]    The bulk capacitor C BULK    74   a  and a ceramic capacitor C CERAMIC    76   a  of the pathway are further modeled in the schematic  88  shown in FIG. 5 in accordance with one embodiment of the present invention. Both of these capacitors are modeled with a resistor  90 , an inductor  92  and a capacitor  94 , all connected in series. The resistor  90  and the inductor  92  represent the equivalent series resistance and inductance respectively of the bulk or ceramic capacitor  74   a  or  76   a . The capacitor  94  represents the actual capacitance value of the bulk or ceramic capacitor  74   a  or  76   a.    
         [0036]    Returning to FIG. 4, each pathway from the converters is tied to an inductor labeled L PLANE    78  that is connected in series with a resistor labeled R PLANE    80 . The inductor  78  and the resistor  80  represent the inductance and resistance of the perforated plane respectively. They in turn, are tied in series to an inductor labeled L VIA    82  that is connected in series with a resistor labeled R VIA    84 . The inductor  82  and the resistor  84  represent the inductance and resistance of the board via  44  respectively. The board via, labeled as V BOARD    44  connects the board to the package as shown in FIG. 2. In both FIGS. 4 and 5, the values of each resistor  68   a - d,    70   a - d,    72   a - d,    80 ,  84 , each inductor  78 ,  82 , and each capacitor  74   a - d,    76   a - d,    94  are selected to accurately simulate the performance of its specific modeled component.  
         [0037]    [0037]FIG. 6 shows a schematic  98  of a circuit model of a package in accordance with one embodiment of the present invention. The board via  44  connects to an inductor labeled L PACKAGE1    100  that is connected in series with a resistor labeled R PACKAGE1    102 . They in turn, are tied in series to an inductor labeled L PACKAGE2    104  that is connected in series with a resistor labeled R PACKAGE2    106 . A package capacitor, labeled C PACKAGE    108 , which is connected to the system ground between R PACKAGE1    102  and L PACKAGE2    104 . The inductor L PACKAGE1    100  and the resistor R PACKAGE1    102  represent the inductance and resistance of the package up to the package capacitor  108  respectively. The inductor L PACKAGE2    104  and the resistor R PACKAGE2    106  represent the inductance and resistance of the package after the package capacitor  108  respectively.  
         [0038]    The package capacitor C PACKAGE    108  is further modeled in the schematic  110  shown in FIG. 7 in accordance with one embodiment of the present invention. The capacitor  108  is modeled with a resistor  112 , an inductor  114  and a capacitor  116 , all connected in series. The resistor  112  and the inductor  114  represent the equivalent series resistance and inductance respectively of the package capacitor  108 . The capacitor  116  represents the actual capacitance value of the package capacitor  108 . In both FIGS. 6 and 7, the values of each resistor  102 ,  106 ,  112 , each inductor  100 ,  104 ,  114 , and each capacitor  108 ,  116  are selected to accurately simulate the performance of its specific modeled component.  
         [0039]    [0039]FIGS. 8 a  and  8   b  show a block diagram of a model of a chip in accordance with one embodiment of the present invention. FIG. 8 a  shows the connection from the package via  48  is split into parallel paths that connect to nine separate models  122   a - 122   i  for the bump and grid components of the chip. Each of the bump and grid components  122   a - 122   i  is then connect by a via  124   a - 124   i  to a designated section model. FIG. 8 b  shows a inter-connecting grid of nine section models  126   a - 126   i  and ten routing channel models  128   a - 128   l.  Each section model  126   a - 126   i  is connected to other adjacent section models through the routing channel models  128   a - 128   l.  The nine sections are arranged in a three-by-three grid with the ten channels serving as connections between each of the sections.  
         [0040]    While FIGS. 8 a  and  8   b  show nine bump and grid models  122   a - 122   i,  nine section models  126   a - 126   i,  and ten routing channels  128   a - 128   l,  it is fully intended that the scope of this invention covers embodiments with differing numbers of each of these components. For example, the chip could be represented by a four-by-four section model grid. The end result is that different arrangements and numbers of the component blocks shown in FIGS. 8 a  and  8   b  are dependent upon the components present in the system and are not limited to the embodiment shown here.  
         [0041]    [0041]FIG. 9 a  shows a schematic  130  of a circuit model of a bump and grid model in accordance with one embodiment of the present invention. The model includes an inductor labeled L BUMP    132  that is connected in series with a resistor labeled R BUMP    134 . They in turn, are tied in series to an inductor labeled L GRID    136  that is connected in series with a resistor labeled R GRID    138 . The inductor L BUMP    132  and the resistor R BUMP    134  represents the inductance and resistance of the bump respectively. The inductor L GRID    136  and the resistor R GRID    138  represent the inductance and resistance of the grid respectively.  
         [0042]    [0042]FIG. 9 b  shows a schematic  140  of a circuit model of a section model in accordance with one embodiment of the present invention. The section model, in general, represents a physical section of the chip. The model includes a load  132  that is connected a transistor labeled C LOCAL    144  and a voltage controlled capacitor labeled C INTRINSIC    146 . All of these devices are connected together in parallel. The load  132  represents a load model for that section of the chip. The load model may be a voltage controlled resistor for AC analysis or a current source for transient simulations. The transistor C LOCAL    144  represents the local high frequency capacitors. The capacitor C INTRINSIC    146  represents the intrinsic transistor capacitance of the section of the chip.  
         [0043]    [0043]FIG. 9 c  shows a schematic  150  of a circuit model of a channel model in accordance with one embodiment of the present invention. The model  150  includes an inductor labeled L CHANNEL1    152  that is connected in series with a resistor labeled R CHANNEL1    154 . They in turn, are tied in series to a resistor labeled R CHANNEL2    156  that is connected in series with an inductor labeled L CHANNEL2    158 . A transistor, labeled C CHANNEL    160 , is connected to the system ground between R CHANNEL1    154  and R CHANNEL2    156 . The inductors, L CHANNEL1    152  and L CHANNEL2    158 , and the resistors, R CHANNEL1    154  and R CHANNEL2    158 , represent the inductance and resistance between the connected sections respectively. The transistor C CHANNEL    160  represents the capacitance of the routing channels. In FIGS. 9 a ,  9   b , and  9   c , the values of each resistor  134 ,  138 ,  154 ,  156 , each inductor  132 ,  136 ,  152 ,  158 , each transistor  144 ,  160 , each load  142 , and each capacitor  146  are selected to accurately simulate the performance of its specific modeled component.  
         [0044]    The resulting model represents an advantage in modeling of power systems by providing a low complexity model with an excellent simulation time. The model further provides flexibility in accurately modeling the power system in AC analysis as well as providing analysis of transient signals such as current spikes of different magnitudes and frequencies.  
         [0045]    While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as disclosed herein. Accordingly, the scope of the invention should be limited only by the attached claims.