Abstract:
A semiconductor integrated circuit having an internal SRAM that includes at least one row in which a plurality of memory cells are arrayed, the semiconductor integrated circuit comprises: a first bit line and a second bit line that are connected to first ports of the memory cells; a third bit line and a fourth bit line that are connected to second ports of the memory cells; a first transistor and a second transistor respectively composing first ports of adjacent first and second memory cells and having shared impurity diffusion region connected to the first bit line via a first interconnection; a third transistor composing a second port of the first memory cell and having an impurity diffusion region connected to the third bit line via a second interconnection; a fourth transistor and a fifth transistor respectively composing the first ports of the first and second memory cells and having a shared impurity diffusion region connected to the second bit line via a third interconnection; a sixth transistor composing a second port of the first memory cell and having an impurity diffusion region connected to a fourth bit line via a fourth interconnection; a first write/read circuit that writes data to and reads data from the memory cells via the first port; and a second write/read circuit that writes data to and reads data from the memory cells via the second port; wherein the lengths of the second and fourth interconnection are shorter than the lengths of the first and third interconnection.

Description:
[0001]     The entire disclosure of Japanese Patent Application No. 2005-187729, filed Jun. 28, 2005 is expressly incorporated by reference herein.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Technical Field  
         [0003]     The present invention relates to a semiconductor integrated circuit with an internal dual-port static random access memory (SRAM) in which two ports, provided for each memory cell in the SRAM, can be respectively switched between writing data and reading data and used.  
         [0004]     2. Related Art  
         [0005]     A multi-port SRAM that can simultaneously read-write access a plurality of addresses is known as one type of SRAM. The multi-port SRAM described in JP-A-10-222983, an example of related art, includes a plurality of memory cells from which data can be read and to which data can be written; a read bit line pair that is placed in parallel on both sides of the memory cells in an array direction; a write bit line pair that is placed in parallel outside of the read bit line pair; a read word line for memory cell selection provided in correspondence with the read bit line pair; and a write word line for memory cell selection provided in correspondence with the write line pair.  
         [0006]     In the multi-port SRAM, the two bit lines composing the read bit line pair have an intersecting region in the middle. Thus, coupling noise due to the influence of coupling capacitance present between the read bit line pair and the write bit line pair is cancelled. This is advantageous in that error can be prevented when writing and reading simultaneously. At the same time, in accompaniment with the intersecting of the two bit lines, a write inverting circuit that inverts in advance the value of data to be written to a specified memory cell and a read inverting circuit that inverts in advance the value of data read from a specified memory cell must be newly added.  
         [0007]     Therefore, in JP-A-2003-78036, another example of related art, a multi-port SRAM that can quickly and stably output data read from a memory cell without the addition of a new circuit is described.  FIG. 7  is a block diagram of a configuration of the multi-port SRAM described in JP-A-2003-78036.  
         [0008]     The multi-port SRAM shown in  FIG. 7  includes: a write decoder  1  to which a write address is applied; a read decoder  2  to which a read address is applied; N number of memory cells MC 1  to MC N  that are arrayed in a row at predetermined intervals between the write decoder  1  and the read decoder  2 ; a sense amplifier  5  that reads data from a memory cell specified by the read address and outputs the data as read data; and a write driver  6  to which write data is applied that writes data to a memory cell specified by the write address.  
         [0009]     The write decoder  1  decodes the applied write address and activates only one word line among an N number of write word lines WW 1  to WW N . The read decoder  2  decodes the applied read address and activates only one word line among an N number of read word lines RW 1  to RW N .  
         [0010]     The memory cells MC 1  to MC N  are respectively connected to the write word lines WW 1  to WW N  that correspond with the output of the write decoder  1  and are also respectively connected to the read word lines RW 1  to RW N  that correspond with the output of the read decoder  1 . Two complementary read bit lines RB and /RB for reading data from each memory cell are placed in parallel on both sides of the memory cells MC 1  to MC N  in the array direction, thus forming a read bit line pair.  
         [0011]     The read bit lines RB and /RB forming the read bit line pair intersect almost in the center of the region in which the memory cells MC 1  to MC N  are arrayed. Each memory cell and the read bit line RB are connected via a connecting wire  3 . Each memory cell and the read bit line /RB are connected via a connecting wire  4 . The connecting wires  3  and the connecting wires  4  of the memory cells MC 1  to MC N/2 , which are the upper half of the N number of memory cells MC 1  to MC N , intersect.  
         [0012]     The read bit lines RB and /RB are connected to a sense amplifier  5 . The sense amplifier  5  amplifies a differential signal outputted from a memory cell specified by the read address and outputs a logic-level signal (read data).  
         [0013]     Two complementary write bit lines WB and /WB for writing data to the memory cells MC 1  to MC N  are placed in parallel on both sides of the read bit lines RB and /RB, thus forming a write bit line pair. Each memory cell and the write bit line WB are connected via a connecting wire  7 . Each memory cell and the write bit line /WB are connected via a connecting wire  8 .  
         [0014]     The write bit lines WB and /WB are connected to a write driver  6 . The write driver  6  writes data to a memory cell specified by the write address by outputting a differential signal to the memory cell based on the write data.  
         [0015]     In this way, the read bit lines RB and /RB intersect halfway and are switched left and right, and in correspondence, the connecting wires  3  and the connecting wires  4  intersect. Thus, data read from a memory cell can be output quickly and stably without the addition of a new circuit.  
         [0016]     However, in the multi-port SRAM, the capacities placed on the bit lines are generally unbalanced between the write bit line pair composing a first port and the read bit line pair composing a second port. This is not a problem when one port is used exclusively for writing and the other port is used exclusively for reading. However, when this configuration is applied to a dual-port SRAM in which each port is respectively switched between writing data and reading data and used, this a problem in that the operating speeds between the two ports differ.  
         [0017]     JP-A-10-222983 (page 1 and FIG. 1) and JP-A-2003-78036 (pages 3, 5 to 6, and FIG. 1) are examples of related art.  
       SUMMARY  
       [0018]     An advantage of the present invention is to provide a semiconductor integrated circuit with an internal dual-port static random access memory (SRAM) in which two ports, provided for each memory cell in the SRAM, can be respectively switched between writing data and reading data and used, and in which imbalance in characteristics between the two ports are improved.  
         [0019]     A semiconductor integrated circuit according to one aspect of the invention has an internal SRAM that includes at least one row in which a plurality of memory cells are arrayed, the semiconductor integrated circuit including: a first bit line and a second bit line that are connected to first ports of the memory cells; a third bit line and a fourth bit line that are connected to second ports of the memory cells; a first transistor and a second transistor respectively composing first ports of adjacent first and second memory cells and having a common impurity diffusion region connected to the first bit line via a first interconnection; a third transistor composing a second port of the first memory cell and having an impurity diffusion region connected to the third bit line via a second interconnection; a fourth transistor and a fifth transistor respectively composing the first ports of the first and second memory cells and having a common impurity diffusion region connected to the second bit line via a third interconnection; a sixth transistor composing a second port of the first memory cell and having an impurity diffusion region connected to a fourth bit line via a fourth interconnection; a first write/read circuit that writes data to and reads data from the memory cells via the first port; and a second write/read circuit that writes data to and reads data from the memory cells via the second port; in which the lengths of the second and fourth interconnection are shorter than the lengths of the first and third interconnection.  
         [0020]     The impurity diffusion region of the third transistor can be connected to the third bit line formed directly above the impurity diffusion region, and the impurity diffusion region of the sixth transistor can be connected to the fourth bit line formed directly above the impurity diffusion region. In addition, the second write/read circuit can be placed closer to the memory cells than the first write/read circuit.  
         [0021]     Furthermore, the memory cells can include a first group of consecutively arrayed memory cells and a second group of consecutively arrayed memory cells, and the first bit line and the second bit line can be sterically intersected between the first group of memory cells and the second group of memory cells.  
         [0022]     According to an aspect of the invention, the imbalance between the characteristics of the two ports can be improved if the length of the second interconnection and the fourth interconnection respectively connected to the impurity diffusion regions of the third transistor and the sixth transistor, to which relatively large capacities are placed, is formed shorter than the lengths of the first interconnection and the third interconnection respectively connected to the impurity diffusion regions of the first and second transistors and the fourth and fifth transistors, to which relatively small capacities are placed. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0023]     The invention will be described with reference to the accompanying drawings, wherein like numbers reference like elements.  
         [0024]      FIG. 1  is a block diagram showing a dual-port SRAM in a first embodiment of the present invention;  
         [0025]      FIG. 2  is a circuit diagram showing memory cells included in the dual-port SRAM shown in  FIG. 1 ;  
         [0026]      FIG. 3  is a circuit diagram showing a configuration of an A port write/read circuit shown in  FIG. 1 ;  
         [0027]      FIG. 4  is a diagram showing a layout of the dual-port SRAM shown in  FIG. 1 ;  
         [0028]      FIG. 5  is a block diagram showing a dual-port S in a second embodiment of the present invention;  
         [0029]      FIG. 6  is a diagram showing a layout of the dual-port SRAM shown in  FIG. 5 ; and  
         [0030]      FIG. 7  is a block diagram showing a configuration of a multi-port SRAM described in JP-A-2003-78036. 
     
    
     DESCRIPTION OF EXEMPLARY EMBODIMENTS  
       [0031]     Embodiments of the invention will be described.  
         [0032]      FIG. 1  is a block diagram showing a configuration of a dual-port SRAM embedded in a semiconductor integrated circuit according to a first embodiment of the invention. The dual-port SRAM includes a memory cell array composed of a plurality of SRAM cells arrayed in a matrix. In  FIG. 1 , N number of memory cells MC 1  to MC N  in a first row are is shown.  
         [0033]     The dual-port SRAM shown in  FIG. 1  includes: an A port decoder  10  to which a first address is applied; a B port decoder  20  to which a second address is applied; an N number of memory cells MC 1  to MC N  arrayed in a row at a predetermined interval between the A port decoder  10  and the B port decoder  20 ; an A port write/read circuit  30  that writes data to or reads data from a memory cell specified by the first address via an A port; a B port write/read circuit  40  that writes data to or reads data from a memory cell specified by the second address via a B port; a control circuit  50  that controls the A port write/read circuit  30 ; a control circuit  60  that controls the B port write/read circuit  40 ; and an I/O circuit  70  that inputs and outputs write data and read data to and from an external circuit.  
         [0034]     The A port decoder  10  decodes the applied first address and only activates a word line corresponding to the first address among an N number of A port word lines AW 1  to AW N . The B port decoder  20  decodes the applied second address and only activates a word line corresponding to the second address among an N number of B port word lines BW 1  to BW N .  
         [0035]     The memory cells MC 1  to MC N  are respectively connected to the corresponding word lines AW 1  to AW N  at the output-end of the A port decoder  10  and are also respectively connected to the corresponding word lines BW 1  to BW N  at the output-end of the B port decoder  20 . Bit lines AB and /AB composing an A port bit line pair and bit lines BB and /BB composing a B port bit line pair are placed in parallel on both sides of the memory cells memory cells MC 1  to MC N . The bit lines are connected to each memory cell, MC 1  to MC N .  
         [0036]     The bit lines AB and /AB composing the A port bit line pair are connected to the A port write/read circuit  30 . The A port write/read circuit  30 , controlled by the control circuit  50 , writes data to the memory cell specified by the first address, amplifies a differential signal output from the memory cell specified by the first address, and outputs a logic-level signal (read data).  
         [0037]     The bit lines BB and /BB composing the B port bit line pair are connected to the B port write/read circuit  40 . The B port write/read circuit  40 , controlled by the control circuit  60 , writes data to the memory cell specified by the second address, amplifies a differential signal output from the memory cell specified by the second address, and outputs a logic-level signal (read data)  
         [0038]     The A port write/read circuit  30  is connected to the I/O circuit  70  via an A port bus line. The B port write/read circuit  40  is connected to the I/O circuit  70  via a B port bus line. The I/O circuit  70  outputs write data inputted from an external circuit to the A port write/read circuit  30  or the B port write/read circuit  40  and outputs the read data inputted from the A port write/read circuit  30  or the B port write/read circuit  40  to an external circuit.  
         [0039]      FIG. 2  is a circuit diagram showing a configuration of the memory cells included in the dual-port SRAM shown in  FIG. 1 . In  FIG. 2 , only two memory cells, MC 1  and MC 2 , are shown. The memory cell MC 1  includes: a P-channel metal-oxide semiconductor (MOS) transistor QP 11  and an N-channel MOS transistor QN 11  that compose a first inverter; a P-channel MOS transistor QP 12  and an N-channel MOS transistor QN 12  that compose a second inverter; and N-channel MOS transistors QN  13  to QN  16  that operate as transmission gates. The output of the first inverter is connected to a first store node N 1  and the input is connected to a second store node N 2 . The output of the second inverter is connected to the second store node N 2  and the input is connected to the first store node N 1 .  
         [0040]     A source and drain path of the transistor QN 13  is connected between the bit line AB and the first store node N 1 . The source and drain path of the transistor QN 14  is connected between the bit line /AB and the second store node N 2 . The gates of the transistor QN 13  and the transistor QN 14  are connected to the word line AW 1 .  
         [0041]     A source and drain path of the transistor QN 15  is connected between the bit line BB and the first store node N 1 . A source and drain path of the transistor QN 16  is connected between the bit line /BB and the second store node N 2 . The gates of the transistor QN 15  and the transistor QN 16  are connected to the word line BW 1 . In the memory cell MC 1 , the transistors QN 13  and QN  14  compose the A port and the transistors QN 15  and QN 16  compose the B port.  
         [0042]     Similarly, the memory cell MC 2  includes: a P-channel MOS transistor QP 21  and an N-channel MOS transistor QN 21  that compose a first inverter; a P-channel MOS transistor QP 22  and a N-channel MOS transistor QN 22  that compose a second inverter; and N-channel MOS transistors QN  23  to QN  26  that operate as transmission gates. In the memory cell MC 2 , the transistors QN 23  and QN  24  compose the A port and the transistors QN 25  and QN 26  compose the B port.  
         [0043]     The source or drain of the transistor QN 13  included in the memory cell MC 1  (the source or drain connected to the bit line AB) and the source or drain of the transistor QN 23  included in the memory cell MC 2  (the source or drain connected to the bit line AB) are composed using a common impurity diffusion region, and thus, the source or drain capacity placed on one transistor is almost halved. In other words, with regards to junction capacity, the capacity placed on the A port bit line is smaller than the capacity placed on the B port bit lines. To simplify explanations, hereinafter, the source or drain connected to the bit line within the impurity diffusion region of the MOS transistor will be referred to as the source and the source or drain connected to the store node will be referred to as the drain.  
         [0044]     An operation in which data is written in the memory cells will be explained with reference to  FIG. 2 .  
         [0045]     When writing data in the memory cell MC 1  via the A port, the A port decoder  10  provides a high level signal to the word line AW 1  and the A port write/read circuit  30  provides, for example, a high level signal to the bit line AB and a low level signal to the bit line /AB. The transistors QN 13  and QN 14  are turned on by the high level signal applied to the word line AW 1 , the store node N 1  becomes the same high level as the bit line AB, and the store node N 2  becomes the same low level as the bit line /AB. One bit of data is stored in the memory cell MC 1  by the first and second inverters maintaining this state.  
         [0046]     Next, an operation in which data is read from the memory cells will be explained.  
         [0047]     When reading data from the memory cell MC 1  via the A port, the A port decoder  10  provides a high level signal to the word line AW 1  and the transistors QN 13  and QN 14  are turned on. As a result, the bit line AB becomes the same level as the store node N 1  and the bit line /AB becomes the same level as the store node N 2 . One bit of data stored in the memory cell MC 1  is read by the A port write/read circuit  30  performing differential amplification of the levels of the bit line AB and the bit line /AB.  
         [0048]      FIG. 3  is a circuit diagram showing a configuration of the A port write/read circuit included in the dual-port SRAM shown in  FIG. 1 . As shown in  FIG. 3 , the A port write/read circuit  30  includes: N-channel MOS transistors QN 1  and QN 2  that are turned on when a first column selection signal is activated to high level; an inverter  71  that inverts write data applied from the A port bus line; a latch circuit  72  that latches write data in synchronization with a write control signal and provides the latched data to the bit line AB; and a latch circuit  73  that latches inverted write data in synchronization with the write control signal and outputs the latched data to the bit line /AB.  
         [0049]     The A port write/read circuit  30  further includes: N-channel MOS transistors QN 3  and QN 4  that are turned on when the first column selection signal is activated to high level; and a differential amplifier (sense amplifier) composed of the P-channel MOS transistors QP 1  and QP 2  and the N-channel MOS transistors QN 5  to QN 7 . The sense amplifier operates when a read control signal is activated to a high level, generates read data by performing differential amplification on the levels of the bit line AB and the bit line /AB, and outputs the generated read data to the A port bus line. The configuration of the B port write/read circuit  40  is the same as that of the A port write/read circuit  30 .  
         [0050]     Next, a layout of the dual-port SRAM shown in  FIG. 1  will be explained.  
         [0051]      FIG. 4  is a diagram showing a layout of a portion of the constituent elements included in the dual-port SRAM shown in  FIG. 1 . In  FIG. 4 , insulating films are omitted to clarity the interconnections of each component.  
         [0052]     A plurality of gate electrodes, which are word lines BW 1 , AW 1 , and AW 2 , is formed on a semiconductor substrate via a gate insulating film. N-type impurity diffusion regions  11  to  14  and  21  to  24  are formed within the semiconductor substrate on both sides of the gate electrodes. A three-layer interconnection layer is further formed on the semiconductor substrate via an interlayer insulating film. Interconnections  31  to  34  are formed in the second layer of the interconnection layer. A port bit lines AB and /AB and B port bit lines BB and /BB are formed in the third layer of the interconnection layer.  
         [0053]     The impurity diffusion region  12  is equivalent to a shared drain of the transistors QN 15  and QN  13  shown in  FIG. 2  and is electrically connected to the store node N 1  of the memory cell MC 1 . The impurity diffusion region  14  is equivalent to the shared drain of the transistors QN 23  and QN  25  and is electrically connected to the store node N 1  of the memory cell MC 2 . The impurity diffusion region  11  is equivalent to the source of the transistor QN  15  and is electrically connected to the bit line BB via the interconnection  31 . The impurity diffusion region  13  is equivalent to the shared source of the transistors QN 13  and QN 23  and is electrically connected to the bit line AB via the interconnection  33 .  
         [0054]     Similarly, the impurity diffusion region  22  is equivalent to the shared drain of the transistors QN 16  and QN  14  shown in  FIG. 2  and is electrically connected to the store node N 2  of the memory cell MC 1 . The impurity diffusion region  24  is equivalent to the shared drain of the transistors QN  24  and QN  26  and is electrically connected to the store node N 2  of the memory cell MC 2 . The impurity diffusion region  21  is equivalent to the source of the transistor QN  16  and is electrically connected to the bit line BB via the interconnection  32 . The impurity diffusion region  23  is equivalent to the shared source of the transistors QN  14  and QN  24  and is electrically connected to the bit line /AB via the interconnection  34 .  
         [0055]     The sources of the transistors QN  13  and QN 23  electrically connected to the A port bit line AB are shared, whereas the source of the transistor QN  15  electrically connected to the B port bit line BB is independent. Thus, respective source capacities of the transistors QN 13  and QN 23  are about half of the source capacity of the transistor QN 15 .  
         [0056]     Furthermore, the sources of the transistors QN  14  and QN  24  electrically connected to the A port bit line /AB are shared, whereas the source of the transistor QN 16  electrically connected to the B port bit line /BB is independent. Thus, the respective source capacities of the transistors QN 14  and QN 24  are about half of the source capacity of the transistor QN 16 . Therefore, with regards to the junction capacity, the capacity placed on the A port bit line is smaller than the capacity placed on the B port bit line, as explained earlier.  
         [0057]     In accordance with the present embodiment, the interconnection connected between the B port bit line BB and the source of the transistor QN 15  and the interconnection connected between the B port bit line BB and the source of the transistor QN 16  are shortened by the B port bit lines BB and /BB being placed inside (preferably directly above the sources of the transistors QN 15  and QN 16 ). As a result, the wiring capacities placed on the bit lines BB and /BB are reduced.  
         [0058]     The A port bit lines AB and /AB are placed outside, and thus, the wiring capacities placed on the bit lines AB and /AB increase with the difference between the interconnections  31  and  32  and the interconnections  33  and  34  in the third layer of the interconnection layer. The wiring capacities are equivalent to about 15% of the total capacity placed on the bit lines.  
         [0059]     Furthermore, in accordance with the present embodiment, the wiring capacities of the B port bit lines BB and /BB are reduced by the B port write/read circuit  40  being placed closer to the memory cells than the A port write/read circuit  30 . Therefore, the difference in junction capacities can be compensated to a certain extent by the difference in wiring capacities.  
         [0060]     The amount of improvement in the bit line capacity balance according to the first embodiment was determined by simulation. A semiconductor integrated circuit in which the source of a transistor with a small junction capacity is connected to an inner bit line is assumed as a comparative example. Femtofarad (fF) is used as the capacity unit.  
       Comparative Example  
       [0000]     Bit line AB capacity: 378 fF  
         [0000]     Bit line BB capacity: 559 fF  
       First Embodiment  
       [0000]     Bit line AB capacity: 401 fF  
         [0000]     Bit line BB capacity: 461 fF  
         [0061]     The specifications of the dual-port SRAM are determined by the port with the poorer characteristics, and thus, it is preferable that the bit line capacities of the two ports are balanced. The ratio of the bit line capacities of the two ports in the comparative example is 1.48. However, the ratio of the bit line capacities of the two ports according to the first embodiment is 1.15, and thus, it is clear that the imbalance between the capacities of the two ports have been improved.  
         [0062]     Next, a second embodiment of the invention will be explained.  
         [0063]      FIG. 5  is a block diagram showing a partial configuration of the dual port S 1  embedded in the semiconductor integrated circuit according to the second embodiment of the invention. The dual-port SRAM differs from the dual-port SRAM according to the first embodiment, shown in  FIG. 1 , in layout only, and is the same as that in the first embodiment in other respects.  
         [0064]     According to the second embodiment, the A port bit lines AB and /AB intersect between any one row of memory cells (preferably almost in the center). As a result, cross-talk noise between the A port and the B port can be reduced.  FIG. 5  shows N number of memory cells MC 1  to MC N  in a first row. Here, N is an even number, and the bit lines AB and /AB sterically intersect between the N/2 memory cell MC N/2  and the (N/2+1) memory cell MC N/2+1 .  
         [0065]     In addition, with regards to the memory cells MC 1  to MC N/2 , two interconnections connecting each memory cell and the bit lines AB and /AB intersect. As a result, there is no need to provide a write inverting circuit that inverts in advance the value of data to be written in the memory cells MC 1  to MC N/2  and a read inverting circuit that inverts in advance the value of data read from the memory cells MC 1  to MC N/2 .  
         [0066]     Next, a layout of the dual-port SRAM shown in  FIG. 5  will be explained.  
         [0067]      FIG. 6  is a diagram showing a layout of a portion of the constituent elements included in the dual-port DRAM shown in  FIG. 5 . In  FIG. 6 , insulating films are omitted to clarify the interconnections of each component.  
         [0068]     A plurality of gate electrodes, which are word lines BW 1 , AW 1 , and AW 2 , is formed on a semiconductor substrate via a gate insulating film. A plurality of N-type impurity diffusion regions are formed within the semiconductor substrate on both sides of the gate electrodes. A three-layer interconnection layer is further formed on the semiconductor substrate via an interlayer insulating film. Interconnections  41  to  44  are formed in the second layer of the interconnection layer. A port bit lines AB and /AB and B port bit lines BB and /BB are formed in the third layer of the interconnection layer. The bit lines AB and /AB intersect, and thus, the placement of the bit lines AB and /AB are opposite of that shown in  FIG. 4 .  
         [0069]     The shared source of the transistors QN  13  and QN  23  shown in  FIG. 2  is electrically connected to the bit line AB via the interconnection  43 . The shared source of the transistors QN 14  and QN  24  is electrically connected to the bit line /AB via the interconnection  44 . The source of the transistor QN 15  is electrically connected to the bit line BB via the interconnection  41 . The source of the transistor QN 16  is electrically connected to the bit line BB via the interconnection  42 .  
         [0070]     The sources of the transistors QN 13  and QN 23  electrically connected to the A port bit line AB are shared, whereas the source of the transistor electrically connected to the B port bit line BB is independent. Thus, the source capacity of the transistor QN 13  is about half of the source capacity of the transistor QN 15 .  
         [0071]     Furthermore, the sources of the transistors QN  14  and QN  24  electrically connected to the A port bit line /AB are shared, whereas the source of the transistor QN 16  electrically connected to the B port bit line /BB is independent. Thus, the respective source capacities of the transistors QN 14  and QN 24  are about half of the source capacity of the transistor QN 16 . Therefore, with regards to the junction capacity, the capacity placed on the A port bit line is smaller than the capacity placed on the B port bit line, as explained earlier.  
         [0072]     In accordance with the present embodiment, the interconnection connected between the B port bit line BB and the source of the transistor QN 15  and the interconnection connected between the B port bit line BB and the source of the transistor QN 16  are shortened by the B port bit lines BB and /BB being placed inside (preferably directly above the sources of the transistors QN 15  and QN 16 ). As a result, the wiring capacities placed on the bit lines BB and /BB are reduced.  
         [0073]     The A port bit lines AB and /AB are placed outside, and thus, the wiring capacities placed on the bit lines AB and /AB increase with the difference between the interconnections  41  and  42  and the interconnections  43  and  44  in the third layer of the interconnection layer.  
         [0074]     Furthermore, in accordance with the present embodiment, the wiring capacities of the B port bit lines BB and /BB are reduced by the B port write/read circuit  40  being placed closer to the memory cells than the A port write/read circuit  30 . Therefore, the difference in junction capacities can be compensated to a certain extent by the difference in wiring capacities.  
         [0075]     The amount of improvement in the bit line capacity balance according to the second embodiment was determined by simulation. A semiconductor integrated circuit in which the source of a transistor with a small junction capacity is connected to an inner bit line is assumed as a comparative example.  
       Comparative Example  
       [0000]     Bit line AB capacity: 399 fF  
         [0000]     Bit line BB capacity: 559 fF  
       Second Embodiment  
       [0000]     Bit line AB capacity: 433 fF  
         [0000]     Bit line BB capacity: 461 fF  
         [0076]     The specifications of the dual-port SRAM are determined by the port with the poorer characteristics, and thus, it is preferable that the bit line capacities of the two ports are balanced. The ratio of the bit line capacities of the two ports in the comparison example is 1.40. However, the ratio of the bit line capacities of the two ports according to the first embodiment is 1.06, and thus, it is clear that the imbalance between the capacities of the two ports is improved.  
         [0077]     Designing of a semiconductor integrated circuit that has an internal dual-port SRAM is facilitated by the reduced difference in the characteristics between the two ports, and thus, designing period can be shortened. Furthermore, the operation timings of the two ports become closer due to the improvement in the imbalance in the timing at which the sense amplifier is turned on and the like, which determine the characteristics of data reading. As a result, changes in the characteristics due to process fluctuation, etc., can be reduced and the semiconductor integrated circuit will not be easily influenced by manufacturing variations.