Abstract:
A replica circuit includes: a first conductivity type first transistor; a first current path including a first conductivity type second transistor and a second conductivity type third transistor; a second current path including a first conductivity type fourth transistor configured so that current equivalent to a current flowing through the first transistor flows through the fourth transistor, and a second conductivity type fifth transistor configured so that current equivalent to a current flowing through the third transistor flows through the fifth transistor, the fourth transistor and the fifth transistor being connected in series; a second conductivity type sixth transistor configured so a current equivalent to a current flowing through the third transistor flows through the sixth transistor; a first control configured to supply a reference voltage to the drain of the first transistor; and a second control configured to supply the reference voltage to the drain of the fourth transistor.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the benefit of priority from prior Japanese Patent Application Nos. 2011-095069, filed on Apr. 21, 2011, and 2011-061513, filed on Mar. 18, 2011, the entire contents of both of which are incorporated herein by reference. 
       FIELD OF THE INVENTION 
       [0002]    The present invention relates to a replica circuit, a high-voltage detecting circuit, a high-voltage regulator circuit, and a non-volatile semiconductor memory device. The invention relates particularly to a replica detecting circuit that replicates a reference current by causing a current identical with the reference current and flowing through a certain transistor to flow through another transistor, and to a high-voltage detecting circuit using the replica detecting circuit. 
       BACKGROUND OF THE INVENTION 
       [0003]    A semiconductor device serving as a non-volatile memory, etc., is provided with a charge pump circuit used for data writing or deletion, which raises a source voltage VCC to generate a voltage VP higher than the source voltage VCC. The charge pump circuit detects an output high voltage, and stops a charge pumping operation when the detected voltage is higher than a given voltage while starts the charge pumping operation when the detected voltage is lower than the given voltage. The charge pump circuit performs negative feedback control in this manner to adjust the output high voltage to a target voltage. 
         [0004]      FIG. 8  depicts an example of a replica detecting circuit section making up a high-voltage detecting circuit used for controlling the operation of the charge pump circuit. 
         [0005]    A PMOS transistor MP 0  and a reference resistance Rref are connected in series between a node of a source voltage VCC and a node of a ground voltage VSS. A differential amplifier AMP 0  has a negative input terminal supplied with a reference voltage VREF and a positive input terminal connected to a connection point between the PMOS transistor MP 0  and the reference resistance Rref, that is, the drain of the PMOS transistor MP 0 . The output end of the differential amplifier AMP 0  is connected to the gate of the PMOS transistor MP 0 . 
         [0006]    A PMOS transistor MP 1  and an NMOS transistor MN 0  are connected in series between the node of the source voltage VCC and the node of the ground voltage VSS. The gate of the PMOS transistor MP 1  is connected to the gate of the PMOS transistor MP 0 . The PMOS transistor MP 1  and the PMOS transistor MP 0  are the same size (gate length and gate width) with each other. The gate of the NMOS transistor MN 0  is connected to a connection point between the PMOS transistor MP 1  and the NMOS transistor MN 0 , that is, the drain of the NMOS transistor MN 0 . 
         [0007]    A detection resistance element (having a resistance value equivalent to the resistance value of n reference resistances Rref connected in series, n representing a figure that may not be an integer) and an NMOS transistor MN 1  are connected in series between a high-voltage terminal VP and the node of the ground voltage VSS. The gate of the NMOS transistor MN 1  is connected to the gate of the NMOS transistor MN 0 . The NMOS transistor MN 1  and the NMOS transistor NM 0  are the same size (gate length and gate width) with each other. From a connection point between the detection resistance element and the NMOS transistor MN 1 , a detection terminal VDIV is lead out. 
         [0008]    This circuit operates in the following manner. A reference current Iref flowing through the PMOS transistor MP 0  and reference resistance Rref is controlled by negative feedback by the differential amplifier AMP 0  so that the relation VREF=Iref×Rref is satisfied. The PMOS transistor MP 1  and the PMOS transistor MP 0  have the gate common to each other and are the same size with each other. For this reason, a current close to the reference current Iref flows through a current path made up of the PMOS transistor MP 1  and the NMOS transistor MN 0 . The NMOS transistor MN 1  and the NMOS transistor MN 0  have the gate common to each other and are the same size with each other. For this reason, a current close to the reference current Iref flows through a current path made up of the detection resistance element and the NMOS transistor MN 1 . In this manner, current replication is carried out. As a result, a voltage at the detection terminal VDIV becomes close to a voltage given by VDIV=VP−n×Iref×Rref=VP−n×VREF. A variation ΔVP at the high-voltage terminal VP is substantially the same as a variation ΔVDIV at the detection terminal VDIV. Hence voltage detection more precise than voltage detection by simple resistance dividing is achieved. 
         [0009]    The circuit of  FIG. 8 , however, poses the following problem. As shown in  FIG. 9 , a reference current Rref  1  flows through a current path of an Iref converting circuit  50 , where the reference current Rref  1  is close to a reference current Rref 0  but is not identical therewith. This is because that due to a difference in current/voltage characteristics between the reference resistance Rref and the NMOS transistor MN 0  (whose gate and drain are connected in the form of diode connection), the PMOS transistor MP 0  and the PMOS transistor MP 1  have the same source voltage and gate voltage but different drain voltages. Similarly, a reference current Rref  2  flows through the NMOS transistor MN 1 , where the reference current Rref  2  is close to the reference current Rref 1  flowing through the NMOS transistor MN 0  but is not identical with the reference current Rref 1 . This is because that the NMOS transistor MN 0  and the NMOS transistor MN 1  have the same source voltage and gate voltage but different drain voltages. Hence the currents Iref 0 , Iref 1 , and Iref  2  are different in size from each other, thus not matching completely. This results in an error between the variation ΔVP at the high-voltage terminal VP and the variation ΔVDIV at the detection terminal VDIV. Japanese Patent Application Laid-Open Publication No. 2000-19200 is cited as a prior technical document related to this circuit. 
         [0010]    A semiconductor device serving as a non-volatile memory, etc., may be provided with a charge pump circuit that raises a source voltage VCC to generate a voltage VP higher than the source voltage VCC. 
         [0011]      FIG. 14(   a ) is a circuit diagram of a conventional charge pump circuit. NMOS transistors T 01 , T 11 , T 21 , T 31 , and T 41  are connected in series between the node of the source voltage VCC and a node supplied with the raised voltage VP. (While an example of series connection of five transistors is depicted, more than five transistors may be connected in series depending on the value of the raised voltage.) 
         [0012]    Each node between the transistors T 01  and T 11 , between the transistors T 11  and T 21 , between the transistors T 21  and T 31 , and between the transistors T 31  and T 41  is denoted as CPD 1 , CPD 2 , CPD 3 , and CPD 4 . Each node connected to each of the gates of the transistors T 01 , T 11 , T 21 , T 31 , and T 41  is denoted as CPG 0 , CPG 1 , CPG 2 , CPG 3 , and CPG 4 . 
         [0013]    Between the node of the source voltage VCC and the node CPG 0 , an NMOS transistor T 02  is connected, whose gate is connected to the node CPD 1 . Between the node CPD 1  and the node CPG 1 , an NMOS transistor T 12  is connected, whose gate is connected to the node CPD 2 . Between the node CPD 2  and the node CPG 2 , an NMOS transistor T 22  is connected, whose gate is connected to the node CPD 3 . Between the node CPD 3  and the node CPG 3 , an NMOS transistor T 32  is connected, whose gate is connected to the node CPD 4 . Between the node CPD 4  and the node CPG 4 , an NMOS transistor T 42  is connected, whose gate is connected to the high-voltage terminal VP. 
         [0014]    The node CPG 0  is connected to a capacitor C 00 , whose opposed electrodes are driven by a drive signal GCLK 2 . The node CPG 1  is connected to a capacitor C 12 , whose opposed electrodes are driven by a drive signal GCLK 1 . The node CPG 2  is connected to a capacitor C 22 , whose opposed electrodes are driven by the drive signal GCLK 2 . The node CPG 3  is connected to a capacitor C 32 , whose opposed electrodes are driven by the drive signal GCLK 1 . The node CPG 4  is connected to a capacitor C 42 , whose opposed electrodes are driven by the drive signal GCLK 2 . 
         [0015]    The node CPD 1  is connected to a capacitor C 11 , whose opposed electrodes are driven by the drive signal DCLK 1 . The node CPD 2  is connected to a capacitor C 21 , whose opposed electrodes are driven by the drive signal DCLK 2 . The node CPD 3  is connected to a capacitor C 31 , whose opposed electrodes are driven by the drive signal DCLK 1 . The node CPD 4  is connected to a capacitor C 41 , whose opposed electrodes are driven by the drive signal DCLK 2 . 
         [0016]      FIG. 14(   b ) depicts the waveforms of the drive signals DCLK 1 , DCLK 2 , GCLK 1 , and GCLK 2  that drive the above conventional charge pump circuit. These waveforms are so shaped that the positive pluses of the drive signal GCLK 1  are included in the positive pluses of the drive signal DCLK 1  and that the positive pluses of the drive signal GCLK 2  are included in the positive pluses of the drive signal DCLK 2 . 
         [0017]      FIG. 15(   a ) depicts a clock buffer circuit that generates the drive signal DCLK 1  of  FIG. 14(   b ),  FIG. 15(   b ) depicts a clock buffer circuit that generates the drive signal GCLK 1 ,  FIG. 15(   c ) depicts a clock buffer circuit that generates the drive signal DCLK 2 , and  FIG. 15(   d ) depicts a clock buffer circuit that generates the drive signal GCLK 2 . 
         [0018]    The clock buffer circuit of  FIG. 15(   a ), for example, is composed of inverters IN 11 , IN 12 , IN 13 , and IN 14  that are connected consecutively. Numerical values in  FIG. 15(   a ) (e.g., 3.2 μm and 1.6 μm for the inverter IN 11 ) represent the gate widths of PMOS transistors and NMOS transistors making up the inverters. (In the case of the inverter IN 11 , therefore, the gate width of the PMOS transistor is 3.2 μm and the same of the NMOS transistor is 1.6 μm.) 
         [0019]    The clock buffer circuit of  FIG. 15(   b ), similar to the clock buffer circuit of  FIG. 15(   a ), is composed of inverters IN 15 , IN 16 , IN 17 , and IN 18  that are connected consecutively. The gate widths of transistors making up the inverters of  FIG. 15(   b ), however, are smaller than those of  FIG. 15(   a ). For this reason, the clock buffer circuit of  FIG. 15(   a ) has a drive capability higher than that of the clock buffer circuit of  FIG. 15(   b ). 
         [0020]    The clock buffer circuits of  FIGS. 15(C) and 15(   d ) are equivalent to the clock buffer circuits of  FIGS. 15(   a ) and  15 ( b ), respectively. (The clock buffer circuit of  FIG. 15(C)  is composed of consecutively connected inverters IN 21 , IN 22 , IN 23 , and IN 24  and the clock buffer circuit of  FIG. 15(   d ) is composed of consecutively connected inverters IN 25 , IN 26 , IN 27 , and IN 28 .) 
         [0021]    When drive signals are generated using the clock buffer circuits of  FIG. 15  and the charge pump circuit of  FIG. 14(   a ) is driven by the generated drive signals, the actual waveforms of the drive signals DCLK 1 , GCLK 1 , DLCK 2 , and GCLK 2  turn out be waveforms shown in  FIG. 16 , which indicate the flagging of the drive signal DCLK 1 . This happens in the following manner. When the drive signal GCLK 1  in its low-level state (low voltage level VSS) changes into a high-level state (high voltage level VCC), the transistor T 11  becomes conductive, thus allowing a current to flow from the node CPD 1  to the node CPD 2 . As a result, a current also flows into the capacitor C 11 . This affects the drive signal DCLK 1 , causing it to dip. Meanwhile, a current inflow causes the drive signal DCLK 2  to rise. In the same manner, when the drive signal GCLK 2  in its low-level state (low voltage level VSS) changes into a high-level state (high voltage level VCC), the transistor T 21  becomes conductive, thus allowing a current to flow from the node CPD 2  to the node CPD 3 . As a result, a current also flows into the capacitor C 21 . This affects the drive signal DCLK 2 , causing it to dip. 
         [0022]    Such flagging and rising of the drive signals lead to a decline in the efficiency of the charge pump circuit. 
         [0023]    To suppress the flagging and rising of the drive signals DCLK 1  and DCLK 2  as much as possible, the clock buffer circuits of  FIGS. 15(   a ) and  15 ( c ) need a large drive capacity. In the example of  FIG. 15 , the gate widths of the transistors of the clock buffer circuits of  FIGS. 15(   a ) and  15 ( c ) are so determined that the clock buffer circuits of  FIGS. 15(   a ) and  15 ( c ) have a drive capacity 8 times that of the clock buffer circuits of  FIGS. 15(   b ) and  15 ( d ). 
         [0024]    Giving a large drive capacity to each of the clock buffer circuits that generate the drive signals DCLK 1  and DCLK 2 , however, poses a problem that an instantaneous peak current is generated.  FIG. 15  depicts the sum ICC of currents flowing from the node of the source voltage VCC toward the node of the ground voltage VSS in these clock buffer circuits. Because the clock buffer circuit that generates the drive signal DCLK 1  has a pull-up drive capacity much larger than that of the clock buffer circuit that generates the drive signal GCLK 1 , the change of the drive signal DCLK 1  from its low-level state to a high-level state (at t 3 ) causes an instantaneous large current to flow through the clock buffer circuit, and the change of the drive signal DCLK 2  from its low-level state to a high-level state (at t 7 ) causes an instantaneous large current to flow through the clock buffer circuit. 
         [0025]    Because the clock buffer circuit that generates the drive signal DCLK 1  has a pull-up drive capacity much larger than that of the clock buffer circuit that generates the drive signal GCLK 1 , the change of the drive signal DCLK 1  from its high-level state to a low-level state (at t 6 ) causes an instantaneous large current to flow through the clock buffer circuit, and the change of the drive signal DCLK 2  from its high-level state to a low-level state (at t 10 ) causes an instantaneous large current to flow through the clock buffer circuit. 
         [0026]    Such peak currents cause a local drop in the source voltage and a large current change di/dt that act as an inductor element, thus creating a noise source, which is a problem. Japanese Patent Application Laid-Open Publication No. 09-198887 is cited as a prior technical document related to these circuits. 
         [0027]    An object of the present invention is to provide a replica circuit capable of accurately replicating a current, a high-voltage detecting circuit capable of accurately detecting a high voltage using the replica circuit, and a high-voltage generating circuit and a non-volatile semiconductor memory device using the high-voltage generating circuit. 
         [0028]    Another object of the present invention is to provide a voltage converting circuit that suppresses flagging and rising of a drive signal and that reduces a peak current and to provide a semiconductor memory device having such a voltage converting circuit. 
       SUMMARY OF THE INVENTION 
       [0029]    In order to solve the above problems, according to one embodiment of the present invention, a replica circuit is provided, which comprises a first conductivity type first transistor; a first current path including a first conductivity type second transistor and a second conductivity type third transistor that are connected in series with each other; a second current path including a first conductivity type fourth transistor so configured that a current equivalent to a current flowing through the first transistor flows through the first conductivity type fourth transistor and a second conductivity type fifth transistor so configured that a current equivalent to a current flowing through the third transistor flows through the second conductivity type fifth transistor, the first conductivity type fourth transistor and the second conductivity type fifth transistor being connected in series with each other; a second conductivity type sixth transistor so configured that a current equivalent to a current flowing through the third transistor flows through the second conductivity type sixth transistor; a first control means that controls a gate voltage of the first transistor so that a drain voltage of the first transistor becomes substantially equal to a reference voltage; and a second control means that controls a gate voltage of the second transistor so that a drain voltage of the fourth transistor becomes substantially equal to the reference voltage. 
         [0030]    In this replica circuit, the gate of the first transistor and the gate of the fourth transistor may be connected in common to each other, and the drain and gate of the third transistor, the gate of the fifth transistor, and the gate of the sixth transistor may be connected in common to each other. 
         [0031]    In this replica circuit, the first control means may be a first differential amplifier supplied with the reference voltage and a drain voltage of the first transistor and having an output end connected to the gate of the first transistor, and the second control means may be a second differential amplifier supplied with the reference voltage and a drain voltage of the fourth transistor and having an output end connected to the gate of the second transistor. 
         [0032]    In order to solve the above problems, according to another embodiment of the present invention, a high-voltage detecting circuit is provided, which comprises a reference current path including a first resistance and a first conductivity type first transistor that are connected in series with each other; a first current path including a first conductivity type second transistor and a second conductivity type third transistor that are connected in series with each other; a second current path including a first conductivity type fourth transistor so configured that a current equivalent to a current flowing through the first transistor flows through the first conductivity type fourth transistor and a second conductivity type fifth transistor so configured that a current equivalent to a current flowing through the third transistor flows through the second conductivity type fifth transistor, the first conductivity type fourth transistor and the second conductivity type fifth transistor being connected in series with each other; a third current path including a second resistance and a second conductivity type sixth transistor so configured that a current equivalent to a current flowing through the third transistor flows through the second conductivity type sixth transistor, the second resistance and the second conductivity type sixth transistor being connected in series with each other between a high-voltage terminal and a reference voltage terminal; a first control means that controls a gate voltage of the first transistor so that a drain voltage of the first transistor becomes substantially equal to a reference voltage; and a second control means that controls a gate voltage of the second transistor so that a drain voltage of the fourth transistor becomes substantially equal to the reference voltage. 
         [0033]    In this high-voltage detecting circuit, the gate of the first transistor and the gate of the fourth transistor may be connected in common to each other, and the drain and gate of the third transistor, the gate of the fifth transistor, and the gate of the sixth transistor may be connected in common to each other. 
         [0034]    In this high-voltage detecting circuit, the first control means may be a first differential amplifier supplied with the reference voltage and a drain voltage of the first transistor and having an output end connected to the gate of the first transistor, and the second control means may be a second differential amplifier supplied with the reference voltage and a drain voltage of the fourth transistor and having an output end connected to the gate of the second transistor. 
         [0035]    The high-voltage detecting circuit may further comprise a comparing circuit that compares the reference voltage with a drain voltage of the sixth transistor. 
         [0036]    In order to solve the above problems, according to still another embodiment of the present invention, a non-volatile semiconductor memory device is provided, which comprises a high-voltage regulator circuit including a charge pump circuit which operates under control by an output signal from the high-voltage detecting circuit and has an output end connected to a high-voltage terminal; and a memory cell array consisting of a plurality of memory cells for writing or deleting data thereon. 
         [0037]    According to still another embodiment of the present invention, a voltage converting circuit is provided, which comprises a first transistor (T 11 ) connected to a first node (CPD 1 ) and to a second node (CPD 2 ), a first capacitor (C 11 ) connected between the first node (CPD 1 ) and a third node (DCLK 1 ); a second capacitor (C 12 ) connected between the gate of the first transistor and a fourth node (GCLK 1 ); a first buffer that drives the third node in response to a first control signal (DCLK 10 ); and a second buffer that drives the third node in response to a second control signal (GCLK 10 ). In the voltage converting circuit, the first buffer exerts a drive capacity at a voltage level change of the first control signal lower than a drive capacity at a voltage level change of the second control signal. 
         [0038]    The first buffer may have a first inverter (IN 34 ) and a second inverter (T 38 , T 39 ), both inverters having their output ends connected in common to the third node. The first inverter may drive the third node in response to the first control signal and the second inverter may drive the third node in response to both first and second control signals. 
         [0039]    The second inverter may have a second transistor (T 38 ), and the gate of a third transistor may be driven by a result of logical operation of the first and second control signals. 
         [0040]    The voltage converting circuit may further comprise a third transistor (T 12 ) connected between the first node and the gate of the first transistor. 
         [0041]    According to still another embodiment of the present invention, the voltage converting circuit is provided, which comprises a first transistor (T 11 ) connect to the first node (CPD 1 ) and to the second node (CPD 2 ); a second transistor (T 21 ) connect to the second node and to the third node (CPD 3 ); a first capacitor (C 11 ) connected between the first node and a fourth node (DCLK 1 ); a second capacitor (C 12 ) connected between the gate of the first transistor and a fifth node (GCLK 1 ); a third capacitor (C 21 ) connected between the second node and a sixth node (DCLK 2 ); a fourth capacitor (C 22 ) connected between the gate of the second transistor and a seventh node (GCLK 2 ); a first buffer that drives the fourth node in response to a first control signal (DCLK 10 ); a second buffer that drives the fifth node in response to a second control signal (GCLK 10 ); a third buffer that drives the sixth node in response to a third control signal (DCLK 10 ); and a fourth buffer that drives the seventh node in response to a fourth control signal (GCLK 10 ). In the voltage converting circuit, the first buffer exerts a drive capacity at a voltage level change of the first control signal lower than a drive capacity at a voltage level change of the second control signal, and the third buffer exerts a drive capacity at a voltage level change of the third control signal lower than a drive capacity at a voltage level change of the fourth control signal. 
         [0042]    The first buffer may have a first inverter (IN 34 ) and a second inverter (T 38 , T 39 ), both inverters having their output ends connected to the fourth node. The first inverter may drive the fourth node in response to the first control signal and the second inverter may drive the fourth node in response to the first, second, and fourth control signals. The third buffer may have a third inverter (IN 54 ) and a fourth inverter (T 58 , T 59 ), both inverters having their output ends connected to the sixth node. The third inverter may drive the sixth node in response to the third control signal and the fourth inverter may drive the sixth node in response to the third, fourth, and second control signals. 
         [0043]    The second inverter may have a third transistor (T 38 ) and a fourth transistor (T 39 ), and the gate of the third transistor may be driven by a result of logical operation of the first and second control signals and the fourth transistor may be driven by a result of logical operation of the first and fourth control signals. The fourth inverter may have a fifth transistor (T 58 ) and a sixth transistor (T 59 ), and the gate of the fifth transistor may be driven by a result of logical operation of the third and fourth control signals and the sixth transistor may be driven by a result of logical operation of the third and second control signals. 
         [0044]    The voltage converting circuit may further comprise a seventh transistor (T 12 ) connected between the first node and the gate of the first transistor, and an eighth transistor (T 22 ) connected between the second node and the gate of the second transistor. 
         [0045]    A non-volatile semiconductor memory device according to one embodiment of the present invention comprises a memory cell to which data is written by supplying a high voltage generated by the voltage converting circuit to a word line. 
         [0046]    A non-volatile semiconductor memory device according to another embodiment of the present invention comprises a memory cell to which data is written by supplying a high voltage generated by the voltage converting circuit to a well. 
         [0047]    According to one aspect of the present invention, an exact replica of a current can be provided, and an accurate high-voltage detecting circuit and a high-voltage generating circuit can be provided. 
         [0048]    According to another aspect of the present invention, a charge pump circuit can be provided, which suppresses flagging and rising of a drive signal and reduces a peak signal, and a semiconductor memory device can be provided, which has a voltage converting circuit functioning as such a charge pump circuit. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0049]      FIG. 1  is a functional block diagram of a non-volatile semiconductor memory device according to one embodiment of the present invention. 
           [0050]      FIG. 2  is a functional block diagram of a high-voltage regulator circuit according to one embodiment of the present invention. 
           [0051]      FIG. 3  is a functional block diagram of a high-voltage generating circuit according to one embodiment of the present invention. 
           [0052]      FIG. 4  is a circuit diagram of a charge pump circuit according to one embodiment of the present invention. 
           [0053]      FIG. 5  depicts the waveforms of signals for controlling a charge pump circuit according to one embodiment of the present invention. 
           [0054]      FIG. 6  is a circuit diagram of a replica detecting circuit according to one embodiment of the present invention. 
           [0055]      FIG. 7  is an explanatory diagram of an operation of a replica detecting circuit according to one embodiment of the present invention. 
           [0056]      FIG. 8  is a circuit diagram of a conventional replica detecting circuit. 
           [0057]      FIG. 9  is an explanatory diagram of an operation of the conventional replica detecting circuit. 
           [0058]      FIG. 10  is a circuit diagram of a clock buffer circuit according to one embodiment of the present invention. 
           [0059]      FIG. 11  is a circuit diagram of a clock buffer circuit according to one embodiment of the present invention. 
           [0060]      FIG. 12  is a waveform chart of voltages at nodes of a clock buffer circuit and a voltage converting circuit according to one embodiment of the present invention. 
           [0061]      FIG. 13  is a waveform chart showing voltages at nodes of a clock buffer circuit according to one embodiment of the present invention and the sum ICC of currents of the clock buffer circuit. 
           [0062]      FIG. 14  is a diagram of a conventional charge pump circuit and a waveform chart of drive signals for the charge pump circuit. 
           [0063]      FIG. 15  is an example of a clock buffer circuit for driving the conventional charge pump circuit. 
           [0064]      FIG. 16  is a waveform chart showing voltages at nodes of the clock buffer circuit for driving the conventional charge pump circuit and the sum ICC of currents of the clock buffer circuit. 
       
    
    
     DETAILED DESCRIPTION 
       [0065]    Modes for carrying out the present inventions will now be described as embodiments. The present invention is not limited by the following embodiments to be described. The following embodiments may be modified into various forms and the invention may be carried out in those modified forms. 
         [0066]      FIG. 1  is a block diagram of a non-volatile semiconductor memory device according to one embodiment of the present invention. This non-volatile semiconductor memory device may have a memory function only or may serve as a memory core used in combination with a CPU core, etc. The non-volatile semiconductor memory device operates with a single power supply that supplies a source voltage VCC (e.g., 1.8 V) and a ground voltage VSS. The non-volatile semiconductor memory is supplied with an address signal (ADDR), a control signal (CTRL), etc., and carries out data input/output through a DQ terminal. The address signal (ADDR) is supplied to an address buffer circuit (ADDR buffers), and a line address (X-ADDR) of the address signal (ADDR) is supplied to a line decoder (X-decoders) as a column address (Y-ADDR) of the address signal (ADDR) is supplied to a column decoder (Y-decoders). A memory cell array is composed of an array of PMOS transistors each having a charge accumulating layer (floating gate, nitrided film, etc.) and a control gate connected to each word line, which is driven by the line decoder (X-decoders). The PMOS transistors&#39; sources are connected to a common source line and their drains are connected to bit lines, anyone of which is selected by a column selecting gate (Y-select gates) that is driven by the column decoder (Y-decoders). The column selecting gate (Y-select gates) is a multiplexer circuit. A voltage of a bit line selected by the multiplexer circuit (or a current flowing through the selected bit line) is sensed by a sensing amplifier (sense amps) as readout data, which is latched by a page buffer circuit (page buffers), and is transferred by a writing-in data loading circuit (program data loading) through an input/output buffer circuit (I/O buffer) in accordance with an address in a page buffer (Page-ADDR), to the DQ terminal. 
         [0067]    Incoming writing-in data from the DQ terminal travels through the input/output buffer circuit (I/O buffer), and is latched by the page buffer circuit (page buffers), and then is held by a writing-in buffer circuit (program buffers). The data held by the writing-in buffer circuit is supplied to a bit line selected by the column selecting gate (Y-select gates), and is written to a selected memory cell. Data writing is carried out in such a way that zero voltage, a voltage equal to or higher than the source voltage VCC, a high voltage VP 1 , and a high voltage VP 2  are supplied to the bit line, the common source line, the word line, and a well, respectively, to generate an inter-band tunnel current, thus trapping electrons in the charge accumulating layer. The high voltages VP 1  and VP 2  are, for example, 7 v and 5 V. 
         [0068]    The above reading and writing operations are controlled by a state changing device (state machine) and a control circuit (CTRL ckt) that operate under control by the control signal (CTRL). 
         [0069]    A high-voltage regulator circuit is controlled by the state changing device (state machine) and the control circuit (CTRL ckt), and outputs the high voltages VP 1  and VP 2  and a negative voltage VN. The high voltage VP 1  and the negative voltage VN are supplied to the column decoder (X-decoders), while the high voltage VP 2  is supplied to a well bias control circuit (well bias CTRL). As describe above, when data writing is carried out, zero voltage, a voltage equal to or higher than the source voltage VCC, the high voltage VP 1 , and the high voltage VP 2  are supplied to the bit line, the common source line, the word line, and a well, respectively. 
         [0070]      FIG. 2  is a part of a functional block diagram of a high-voltage regulator circuit (high-voltage regulator) according to one embodiment of the present invention. When outputting three voltages of VP 1 , VP 2 , and VN, the high-voltage regulator circuit is composed of three similar circuits (in which a negative voltage generating circuit is provided by reversing the positive/negative of a positive voltage generating circuit and of an output signal.) 
         [0071]    The high-voltage regulator circuit (high-voltage regulator) includes a high-voltage generating circuit (PUMP), a voltage dividing circuit (voltage divider), a comparing circuit (comparator), and an oscillator. 
         [0072]    The high-voltage generating circuit (PUMP), the voltage dividing circuit (voltage divider), the comparing circuit (comparator), and the oscillator are activated in accordance with a circuit activating signal (EN). The comparing circuit (comparator) compares a reference signal (VREF) supplied from a bandgap reference potential generating circuit (bandgap reference) with a feedback voltage DVIV output from the voltage dividing circuit (voltage divider) to control the operation of the oscillator. The oscillator supplies a clock signal (CLK) to the high-voltage generating circuit (PUMP). When an output voltage from the high-voltage generating circuit (PUMP) becomes excessively high, negative feedback works to suspend supply of the clock signal (CLK) from the oscillator. When an output voltage from the high-voltage generating circuit (PUMP) drops below a given voltage value, supply of the clock signal (CLK) is restarted. 
         [0073]      FIG. 3  is a functional block diagram of the high-voltage generating circuit (PUMP). The high-voltage generating circuit (PUMP) includes a phase shift circuit (phase shifter), a clock buffer circuit (CLK buffers), and a charge pump circuit (CP). 
         [0074]    The clock signal (CLK) is supplied to the phase shift circuit (phase shifter), which generates four control signals DCLK 10 , GCLK  10 , DCLK  20 , and GCLK 20  having four different phases, which will be described in detail later with reference to  FIG. 5 . The phase shift circuit (phase shifter) is composed of a plurality of delay circuits. The clock buffer circuit (CLK buffer) receives the control signals DCLK 10 , GCLK  10 , DCLK  20 , and GCLK 20  and generates drive signals DCLK 1 , GCLK  1 , DCLK  2 , and GCLK 2 . The charge pump circuit (CP) receives drive signals DCLK 1 , GCLK  1 , DCLK  2 , and GCLK 2  and generates a high voltage (such as the high voltages VP 1 , VP 2  and the negative voltage VN.) 
         [0075]      FIG. 4  is a circuit diagram of the charge pump circuit (CP). NMOS transistors T 01 , T 11 , T 21 , T 31 , and T 41  are connected in series between a node supplied with the source voltage VCC and a node supplied with the raised voltage VP. 
         [0076]    Each node between the transistors T 01  and T 11 , between the transistors T 11  and T 21 , between transistors the T 21  and T 31 , and between the transistors the T 31  and T 41  is denoted as CPD 1 , CPD 2 , CPD 3 , and CPD 4 . Each node connected to the gate of each of the transistors T 01 , T 11 , T 21 , T 31 , and T 41  is denoted as CPG 0 , CPG 1 , CPG 2 , CPG 3 , and CPG 4 . 
         [0077]    Between the node of the source voltage VCC and the node CPG 0 , an NMOS transistor T 02  is connected, whose gate is connected to the node CPD 1 . Between the node CPD 1  and the node CPG 1 , an NMOS transistor T 12  is connected, whose gate is connected to the node CPD 2 . Between the node CPD 2  and the node CPG 2 , an NMOS transistor T 22  is connected, whose gate is connected to the node CPD 3 . Between the node CPD 3  and the node CPG 3 , an NMOS transistor T 32  is connected, whose gate is connected to the node CPD 4 . Between the node CPD 4  and the node CPG 4 , an NMOS transistor T 42  is connected, whose gate is connected to the node of the raised voltage VP. 
         [0078]    The node CPG 0  is connected to a capacitor C 00 , whose opposed electrodes are driven by the drive signal GCLK 2 . The node CPG 1  is connected to a capacitor C 12 , whose opposed electrodes are driven by the drive signal GCLK 1 . The node CPG 2  is connected to a capacitor C 22 , whose opposed electrodes are driven by the drive signal GCLK 2 . The node CPG 3  is connected to a capacitor C 32 , whose opposed electrodes are driven by the drive signal GCLK 1 . The node CPG 4  is connected to a capacitor C 42 , whose opposed electrodes are driven by the drive signal GCLK 2 . 
         [0079]    The node CPD 1  is connected to a capacitor C 11 , whose opposed electrodes are driven by the drive signal DCLK 1 . The node CPD 2  is connected to a capacitor C 21 , whose opposed electrodes are driven by the drive signal DCLK 2 . The node CPD 3  is connected to a capacitor C 31 , whose opposed electrodes are driven by the drive signal DCLK 1 . The node CPD 4  is connected to a capacitor C 41 , whose opposed electrodes are driven by the drive signal DCLK 2 . 
         [0080]      FIG. 5  depicts the waveforms of the control signals DCLK 10 , GCLK 10 , DCLK 20 , and GCLK 20  used for generating the drive signals DCLK 1 , GCLK 1 , DCLK 2 , and GCLK 2 . 
         [0081]      FIG. 6  is a circuit diagram of a replica detecting circuit according to one embodiment of the present invention. The replica detecting circuit is equivalent to the voltage dividing circuit (voltage divider) included in the high-voltage regulator circuit (high-voltage regulator) of  FIG. 2 . The replica detecting circuit includes a reference current generating circuit  10 , an Iref converting circuit  20 , a high-voltage shift circuit  30 , and a reference voltage generating circuit  40 . The reference voltage generating circuit  40  receives the source voltage VCC and the ground voltage VSS and generates a reference current VREF supplied to the reference current generating circuit  10  and to the Iref converting circuit  20 . The reference voltage generating circuit  40  is composed of, for example, a bandgap circuit, etc., so as to be able to constantly generate the fixed reference voltage VREF regardless of the fluctuation of temperatures and the source voltage VCC. 
         [0082]    The reference current generating circuit  10  is composed of a PMOS transistor MP 10 , a reference resistance Rref, and a differential amplifier AMP 10 . The PMOS transistor MP 10  and the reference resistance Rref are connected in series between the node of the source voltage VCC and the node of the ground voltage VSS. The differential amplifier AMP 10  has a negative input terminal supplied with the reference voltage VREF generated by the reference voltage generating circuit  40 , and a positive input terminal connected to a connection point between the PMOS transistor MP 10  and the reference resistance Rref, that is, the drain of the PMOS transistor MP 10 . The output end of the differential amplifier AMP 10  is connected to the gate of the PMOS transistor MP 10 . 
         [0083]    The Iref converting circuit  20  is composed of PMOS transistors MP 11  and MP 12 , NMOS transistors MN 10  and MN 11 , and a differential amplifier AMP 11 . The PMOS transistor MP 11  and the NMOS transistor MN 10  are connected in series between the node of the source voltage VCC and the node of the ground voltage VSS. The gate of the PMOS transistor MP 11  is connected to the gate of the PMOS transistor MP 10 . The PMOS transistor MP 11  and the PMOS transistor MP 10  are the same size (gate length and gate width) with each other. The PMOS transistor MP 12  and the NMOS transistor MN 11  are connected in series between the node of the source voltage VCC and the node of the ground voltage VSS. The gate of the NMOS transistor MN 11  is connected to its drain and to the gate of the NMOS transistor MN 10 . The NMOS transistor MN 11  and the NMOS transistor MN 10  are the same size (gate length and gate width) with each other. The differential amplifier AMP 11  has a positive input terminal supplied with the reference voltage VREF generated by the reference voltage generating circuit  40 , and a negative input terminal connected to a connection point between the PMOS transistor MP 11  and the NMOS transistor MN 10 , that is, the drain of the PMOS transistor MP 11 . The output end of the differential amplifier AMP 11  is connected to the gate of the PMOS transistor MP 12 . 
         [0084]    The high-voltage shift circuit  30  is composed of a detecting resistance element (having a resistance value equivalent to that of n reference resistances Rref connected in series) and an NMOS transistor MN 12 . The detecting resistance element nRef and the NMOS transistor MN 12  are connected in series between the high-voltage terminal VP and the node of the ground voltage VSS. The gate of the NMOS transistor MN 12  is connected to the gate of the NMOS transistor MN 11 . The NMOS transistor MN 11  and the NMOS transistor MN 12  are same size (gate length and gate width) with each other. A detection terminal VDIV is lead out from a connection point between the detecting resistance element nRef and the NMOS transistor MN 12 . 
         [0085]    The operation of the replica detecting circuit shown in  FIG. 6  will then be described referring to  FIG. 7 . 
         [0086]    A reference current Iref 10  flowing through a current path made up of the PMOS transistor MP 10  and the reference resistance Rref is controlled through negative feedback by the differential amplifier AMP 10  so that the relation VREF=Iref 10 ×Rref is satisfied. Specifically, when a drain voltage of the PMOS transistor MP 10  becomes lower than the reference voltage VREF, an output voltage from the differential amplifier AMP 10  lowers, which causes the reference current Iref  10  to increase, thus raising the drain voltage of the PMOS transistor MP 10 . When the drain voltage of the PMOS transistor MP 10  becomes higher than the reference voltage VREF, in contrast, an output voltage from the differential amplifier AMP 10  rises, which causes the reference current Iref  10  to decrease, thus lowering the drain voltage of the PMOS transistor MP 10 . In this manner, the drain voltage of the PMOS transistor MP 10  is kept equal to the reference voltage VREF. As a result, the reference current Iref 10  flowing through the current path is so controlled that the relation VREF=Iref 10 ×Rref is satisfied. 
         [0087]    In the Iref converting circuit  20 , the differential amplifier AMP 11  carries out negative feedback control to keep a drain voltage of the PMOS transistor MP 11  equal to the reference voltage VREF. Specifically, when the drain voltage of the PMOS transistor MP 11  becomes lower than the reference voltage VREF, an output voltage from the differential amplifier AMP 11  rises, which causes a current Iref  12  flowing through a current path made up of the PMOS transistor MP 12  and the NMOS transistor MN 11  to decrease and causes a current Iref  11  mirroring the current Iref  12  to decrease as well, thus raising the drain voltage of the PMOS transistor MP 11 . When the drain voltage of the PMOS transistor MP 11  becomes higher than the reference voltage VREF, in contrast, an output voltage from the differential amplifier AMP 11  lowers, which causes the current Iref  12  flowing through the current path made up of the PMOS transistor MP 12  and the NMOS transistor MN 11  to increase and causes the current Iref  11  mirroring the current Iref  12  to increase as well, thus lowering the drain voltage of the PMOS transistor MP 11 . In this manner, the drain voltage of the PMOS transistor MP 11  is kept equal to the reference voltage VREF. 
         [0088]    The PMOS transistor MP 11  and the PMOS transistor MP 10  have the gate common to each other and are the same size with each other. In addition, as describes above, the drain voltage of the PMOS transistor MP 11  is the reference voltage VREF and the drain voltage of the PMOS transistor MP 10  is also the reference voltage VREF. As a result, the current Iref  11  flowing through a current path made up of the PMOS transistor MP 11  and the NMOS transistor MN 10  becomes exactly the same in size as the reference current Iref  10 . 
         [0089]    The NMOS transistor MN 12  and the NMOS transistors MN 10  and MN 11  have the gate common to each other and are the same size with each other. For this reason, a reference current Iref  13  flowing through a current path made up of the detecting resistance element nRef and the NMOS transistor MN 12  becomes exactly the same in size as the reference current Iref  10  when a detection voltage VDIV matches the reference voltage VREF. Current replication is carried out in this manner. As a result, the detection voltage at the detection terminal VDIV becomes exactly the voltage given by the equation: VDIV=VP−n×Iref×Rref=VP−n×VREF. A variation ΔVP of the high voltage VP matches a variation ΔVDIV of the detection voltage VDIV. Hence extremely precise high voltage detection is achieved. 
         [0090]    Turning to  FIG. 2 , the detection voltage VDVI from the replica detecting circuit equivalent to the high-voltage dividing circuit (voltage divider) in the high-voltage regulator circuit (high-voltage regulator) is supplied to the comparing circuit (comparator). The comparing circuit is composed of, for example, a differential amplifier, which compares the detection voltage VDVI with the reference voltage VREF to detect the high voltage VP. Specifically, when the high voltage VP is higher than a voltage VRFE×(1+n), the detection voltage VDVI is higher than the reference voltage VREF, which makes an output signal from the comparing circuit (comparator) inactive. When the high voltage VP is lower than the voltage VRFE×(1+n), the detection voltage VDVI is lower than the reference voltage VREF, which makes an output signal from the comparing circuit (comparator) active. In this manner, connecting the comparing circuit (comparator) to the replica detecting circuit equivalent to the high-voltage dividing circuit (voltage divider) provides a high-voltage detecting circuit. 
         [0091]    Output from this high-voltage detecting circuit, i.e., output from the comparing circuit (comparator) is adjusted by controlling the operation of the oscillator. When the oscillator is active, it outputs an oscillating clock CLK, so that the high-voltage detecting circuit (PUMP) operates to raise the high voltage VP. When the oscillator is inactive, in contrast, the clock CLK stops oscillating, so that the high-voltage detecting circuit (PUMP) stops operating, thus lowering the high voltage VP. In this manner, the high voltage VP is kept under negative feedback control to maintain its voltage value REF×(1+n). 
         [0092]    As described above, the replica detecting circuit of the present invention makes up the high-voltage detecting circuit, which is used in the high-voltage regulator circuit. This enables accurate control of high voltage. 
         [0093]    As mentioned before, the memory cell array of  FIG. 1  is a matrix array of PMOS transistors each having a charge accumulating layer (floating gate, nitrided film, etc.). Data writing to the memory cell array is carried out in such a way that a high voltage VP 1  generated by the high-voltage regulator circuit (high-voltage regulator) is applied to the gate of the PMOS transistor, a high voltage VP 2  generated by the same circuit is applied to a well, and the ground voltage VSS is applied to the drain of the PMOS transistor to generate an inter-band tunnel current, thereby trap charges in the charge accumulating layer. This data writing method requires an extremely accurate high-voltage control, for which the high-voltage detecting circuit is preferable. 
         [0094]    While the above embodiment relates mainly to the high-voltage detecting circuit that detects a positive high voltage, a negative voltage detecting circuit that accurately detects a negative voltage can be provided by reversing the polarity of transistors of the replica detecting circuit. 
         [0095]    The above embodiment has been described on the assumption that the PMOS transistors MP 10  and MP 11  have the same size and that the NMOS transistors MN 10 , MN 11 , and MN 12  have the same size. However, the sizes, especially the gate widths, of the transistors may be made different from each other to vary the current drive capacities of the transistors. In such a case, the currents Iref 10  and Iref 13  maintain their proportional relation in correspondence to the proportional relation of the sizes of the transistors. 
         [0096]    Another embodiment of the present invention will then be described. 
         [0097]    Each of  FIGS. 10(   a ) and  10 ( b ) depicts a part of the clock buffer circuit (CLK buffers).  FIG. 10(   a ) depicts a circuit that generates the drive signal DCLK 1  and  FIG. 10(   b ) depicts a circuit that generates the drive signal GCLK 1 . The circuit that generates the drive signal DCLK 1  includes a series circuit consisting of inverters IN 31 , IN 32 , IN 33 , and IN 34  connected consecutively, a NAND gate (NAND 36 ) supplied with an output signal from the inverter IN 32  and the drive signal GCLK 1 , an inverter IN 35  supplied with the drive signal GCLK 2 , a NOR gate (NOR 37 ) supplied with an output signal from the inverter IN 32  and an output signal from the inverter IN 35 , a PMOS transistor T 38  driven by an output signal from the NAND 36 , and an NMOS transistor T 39  driven by an output signal from the NOR 37 . The circuit that generates the drive signal GCLK 1  includes inverters IN 41 , IN 42 , IN 43 , and IN 44  connected consecutively. Numerical values in  FIGS. 10(   a ) and  10 ( b ) (e.g., 3.2 μm and 1.6 μm for the inverter IN 31 ) represent the gate widths of PMOS transistors and NMOS transistors making up the inverters. (In the case of the inverter IN 31 , therefore, the gate width of the PMOS transistor is 3.2 μm and the same of the NMOS transistor is 1.6 μm.) The drive signal DCLK 1  is driven by two inverters consisting of the inverter IN 34  and an inverter circuit composed of the transistors T 38  and T 39 . The gate widths of the transistors T 38  and T 39  are determined to be, for example, 120 μm and 60 μm, respectively, which are relatively large. (These gate widths are larger than the gate widths of transistors making up the inverter N 34 , but do not always have to be larger than the gate widths of transistors making up the inverter N 34 . Any gate width is allowed as long as it contributes to an increase in the total driving force.) This gate width setting effectively suppresses flagging and rising of the drive signal DCLK 1 . 
         [0098]    Each of  FIGS. 11(   a ) and  11 ( b ) depicts a part of the clock buffer circuit (CLK buffers).  FIG. 11(   a ) depicts a circuit that generates the drive signal DCLK 2 , and  FIG. 11(   b ) depicts a circuit that generates the drive signal GCLK 2 . The circuit that generates the drive signal DCLK 2  includes a series circuit consisting of inverters IN 51 , IN 52 , IN 53 , and IN 54  connected consecutively, a NAND gate (NAND 56 ) supplied with an output signal from the inverter IN 52  and the drive signal GCLK 2 , an inverter IN 55  supplied with the drive signal GCLK 1 , a NOR gate (NOR 57 ) supplied with an output signal from the inverter IN 52  and an output signal from the inverter IN 55 , a PMOS transistor T 58  driven by an output signal from the NAND 56 , and an NMOS transistor T 59  driven by an output signal from the NOR 57 . The circuit that generates the drive signal GCLK 2  includes inverters IN 61 , IN 62 , IN 63 , and IN 64  connected consecutively. The drive signal DCLK 2  is also driven by two inverters consisting of the inverter IN 54  and an inverter circuit composed of the transistors T 58  and T 59 . The gate widths of the transistors T 58  and T 59  are determined to be relatively large. This gate width setting effectively suppresses flagging or rising of the drive signal DCLK 2 . 
         [0099]      FIG. 12  is a waveform chart of voltages at nodes of the clock buffer circuit (CLK buffers) and the charge pump circuit (CP).  FIG. 12  depicts the voltage waveforms of the control signals DCLK 10 , GCLK 10 , DCLK 20 , and GCLK 20 , the same of the drive signals DCLK 1 , GCLK 1 , DCLK 2 , and GCLK 2 , and the same at the nodes CPD 1 , CPD 2  (indicated by a dotted line), CPG 1 , and CPG 2  (indicated by a dotted line). 
         [0100]    When the control signal GCLK 20  goes low at a time t 1 , the drive signal GCLK 2  goes low in response thereto. When the control signal DCLK 20  goes low at a time t 2 , the drive signal DCLK 2  goes low in response thereto. 
         [0101]    When the control signal DCLK 10  goes high at a time t 3 , the inverters IN 31  to  34  response thereto, causing the drive signal DCLK 1  to go high. As a result, a voltage at the node CPD 1  is raised via the capacitor C 11 . At this point of time, the drive signal GCLK 1  remains low, which keeps an output signal from the NAND 36  high, thus leaving the transistor T 38  non-conductive. In other words, the drive signal DCLK 1  is driven only by the PMOS transistor (with a gate width of 40 μm) of the inverter IN 34 . An instantaneous current generated at a voltage rise at the node CPD 1 , therefore, is not so large, which will be described later. 
         [0102]    When the control signal GCLK 10  goes high at a time t 4 , the inverters IN 41  to  44  response thereto, causing the drive signal GCLK 1  to go high. As a result, a voltage at the node CPG 1  is raised via the capacitor C 12 , which turns the transistor T 11  conductive, so that a raised voltage at the node CPD 1  is transferred to the node CPD 2 . This charge migration (CM 1 ) gradually lowers the voltage at the node CPD 1  while gradually raising the voltage at the node CPD 2 . At this point of time, the drive signal GCLK 1  is high, which makes an output signal from the NAND 36  low, turning the transistor T 38  conductive. In other words, the drive signal DCLK 1  is driven at a high voltage level by the PMOS transistor (with a gate width of 40 μm) of the inverter IN 34  and by the transistor T 38  (with a gate width of 120 μm). Hence the flagging of the drive signal DCLK 1  turns out to be insignificant, as shown in  FIG. 12 , which indicates that the flagging is suppressed effectively. Meanwhile, at the same point of time, the drive signal DCLK 2  is driven at a low voltage level by the inverter IN 54  (with the transistor&#39;s gate width of 20 μm) and by the transistor T 59  (with a gate width of 60 μm). The rising of the drive signal DCLK 2  turns out to be insignificant, as shown in  FIG. 12 , which indicates that the rising is suppressed effectively. 
         [0103]    When the control signal GCLK 10  goes low at a time t 5 , the inverters IN 41  to  44  response thereto, causing the drive signal GCLK 1  to go low. As a result, the transistor T 11  becomes non-conductive, which leads to the end of transfer of the raised voltage at the node CPD 1  to the node CPD 2 . 
         [0104]    When the control signal DCLK 10  goes low at a time t 6 , the inverters IN 31  to  34  response thereto, causing the drive signal DCLK 1  to go low. At this point of time, the drive signal GCLK 2  remains low, which keeps an output signal from the NOR 37  low, thus leaving the transistor T 39  non-conductive. As a result, the drive signal DCLK 1  is driven only by the NMOS transistor (with a gate width of 20 μm) of the inverter IN 34 . An instantaneous current flowing through the clock buffer circuit, therefore, is not so large, which will be described later. 
         [0105]    When the control signal DCLK 20  goes high at a time t 7 , the inverters IN 51  to  54  response thereto, causing the drive signal DCLK 2  to go high. As a result, a voltage at the node CPD 2  is raised via the capacitor C 21 . At this point of time, the drive signal GCLK 2  remains low, which keeps an output signal from the NAND 56  high, thus leaving the transistor T 58  non-conductive. In other words, the drive signal DCLK 2  is driven only by the PMOS transistor (with a gate width of 40 μm) of the inverter IN 54 . An instantaneous current generated at a voltage rise at the node CPD 2 , therefore, is not so large, which will be described later. 
         [0106]    When the control signal GCLK 20  goes high at a time t 8 , the inverters IN 61  to  64  response thereto, causing the drive signal GCLK 2  to go high. As a result, a voltage at the node CPG 2  is raised via the capacitor C 22 , which turns the transistor T 21  conductive, so that a raised voltage at the node CPD 2  is transferred to the node CPD 3 . This charge migration (CM 2 ) gradually lowers the voltage at the node CPD 2  while gradually raising the voltage at the node CPD 3  (which is not depicted). At this point of time, the drive signal GCLK 2  is high, which makes an output signal from the NAND 56  low, turning the transistor T 58  conductive. In other words, the drive signal DCLK 2  is driven at a high voltage level by the PMOS transistor (with a gate width of 40 μm) of the inverter IN 54  and by the transistor T 58  (with a gate width of 120 μm). Hence the flagging of the drive signal DCLK 2  turns out to be insignificant, as shown in  FIG. 12 , which indicates that the flagging is suppressed effectively. Meanwhile, at the same point of time, the drive signal DCLK 1  is driven at a low voltage level by the inverter IN 34  (with the transistor&#39;s gate width of 20 μm) and by the transistor T 39  (with a gate width of 60 μm). The rising of the drive signal DCLK 1  turns out to be insignificant, as shown in  FIG. 12 , which indicates that the rising is suppressed effectively. 
         [0107]    At the time t 8 , the drive signal GDLK 2  turning into a high-level signal leads to a voltage rise at the node CPG 0  via the capacitor C 00 . As a result, the transistor T 01  becomes conductive, so that charges are transferred sequentially from the node of the source voltage VCC to the node CPD 1 . This charge migration (CM 3 ) gradually raises a voltage at the node CPD 1 . 
         [0108]    When the control signal GCLK 20  goes low at a time t 9 , the inverters IN 61  to  64  response thereto, causing the drive signal GCLK 2  to go low. As a result, the transistor T 21  becomes non-conductive, which leads to the end of transfer of the raised voltage at the node CPD 2  to the node CPD 3 . 
         [0109]    When the control signal DCLK 20  goes low at a time t 9 , the inverters IN 51  to  54  response thereto, causing the drive signal DCLK 2  to go low. At this point of time, the drive signal GCLK 1  remains low, which keeps an output signal from the NOR 57  low, thus leaving the transistor T 59  non-conductive. As a result, the drive signal DCLK 2  is driven only by the NMOS transistor (with a gate width of 20 μm) of the inverter IN 54 . An instantaneous current flowing through the clock buffer circuit, therefore, is not so large, which will be described later. 
         [0110]    When the control signal DCLK 10  goes high at a time t 11 , the same operation as the operation at the time t 3  is carried out. When the control signal GCLK 10  goes high at a time t 12 , the same operation as the operation at the time t 4  is carried out, in which operation charge migration occurs (CM 4 ). 
         [0111]      FIG. 13  is a waveform chart showing voltages at nodes of the clock buffer circuit and the sum ICC of currents of the clock buffer circuit. The current sum ICC represents the sum of currents flowing from the node of the source voltage VCC toward the node of the ground voltage VSS. At the time t 3  at which the drive signal DCLK 1  in its low-level state changes into a high-level state, the pull-up drive capacity of the clock buffer circuit that generates the drive signal DCLK 1  is not so large. As a result, an inflow of a large instantaneous current to the clock buffer circuit is prevented effectively. Likewise, when the drive signal DCLK 2  in its low-level state changes into a high-level state (t 7 ), an inflow of a large instantaneous current to the clock buffer circuit is prevented effectively. 
         [0112]    The pull-down drive capacity of the clock buffer circuit that generates the drive signal DCLK 1  is not so large when the drive signal DCLK 1  in its high-level state changes into a low-level state (t 6 ). At this time, therefore, an inflow of a large instantaneous current to the clock buffer circuit is prevented effectively. Likewise, when the drive signal DCLK 2  in its high-level state changes into a low-level state (t 10 ), an inflow of a large instantaneous current to the clock buffer circuit is prevented effectively. 
         [0113]    In this manner, a local drop in the source voltage can be avoided by dispersing peak currents. This prevents the arising of a problem that a large current change di/dt acting as an inductor element creates a noise source. 
       EXPLANATIONS OF LETTERS OR NUMERALS 
       [0000]    
       
         
           
               10  Reference current generating circuit 
               20  Iref converting circuit 
               30  High-voltage shift circuit 
               40  Reference voltage generating circuit 
             T 3 , t 6 , t 7 , t 10  time 
             DCLK 1 , GCLK 1 , DCLK 2 , GCLK 2  drive signal 
             ICC Sum of currents flowing through the clock buffer circuit