Abstract:
A method for fabricating buried decoupling capacitors in an integrated circuit is disclosed. The method forms decoupling capacitors by creating an opening within a substrate which has fin-like spacers, depositing a dielectric material over the spacers, depositing an electrode material over the dielectric material, depositing an insulative material over the electrode material, and forming integrated circuit components over the insulative material.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to the field of integrated circuits and, in particular, to a method of fabricating compact decoupling capacitors within integrated circuits.  
         BACKGROUND OF THE INVENTION  
         [0002]    Integrated circuits, particularly those used in computer systems, continuously become more powerful and operate at faster speeds. To supply power to circuit components, metal layers dedicated to power supply distribution are formed in the circuits in order to maintain a low inductive voltage drop. The inductive voltage drop can nevertheless be substantial, causing high frequency noise that is superimposed upon the power supply voltage. For future generations of components with multi-GHz chips, in particular, noise in the power and ground lines increasingly becomes a problem.  
           [0003]    Bypass capacitors or decoupling capacitors, which act as a charge reservoir, provide an effective way to suppress the power distribution noise. Additionally, decoupling capacitors provide better electrical performance of the integrated circuit. As a result of these benefits, decoupling capacitors are used in many circuit designs.  
           [0004]    Decoupling capacitors have been formed over underlying circuitry and/or device layers. For example, with reference to FIG. 1, circuits  10  have been formed having a substrate  2  and device containing layer  4 . Thereafter, a decoupling capacitor is formed by deposing dielectric layers  6 ,  8 , and  11 , and conductive layers  7  and  9 , wherein combined layers indicated by numeral  13  form a decoupling capacitor. As illustrated in FIG. 2, the capacitor plate(s) can be connected to the underlying components, or a power source, by forming a connective layer  15  which extends between a capacitor plate  9  and an underlying conductive layer  4 . Insulating surfaces  17  are provided to prevent electrical shorts between conductive layers  7  and  9 .  
           [0005]    The existing methods for fabricating decoupling capacitors, however, fall short of increasing industry demands that require new performance criteria from supporting components, such as better location within the integrated circuit and higher performance parameters in high-speed environments. What is needed is a method of fabricating decoupling capacitors that are compact, have high-performance characteristics, and are located strategically within the integrated circuit to decouple transient noise and other undesirable signals.  
         SUMMARY OF THE INVENTION  
         [0006]    The present invention discloses a method of fabricating compact decoupling capacitors that are buried in a substrate, and are located strategically to decouple transient noise and other undesirable signals.  
           [0007]    A method of forming decoupling capacitors for reducing undesirable noise in an integrated circuit is disclosed, comprising forming an opening within a substrate, where the opening contains fin-like spacers, depositing a dielectric material over the spacers, depositing an electrode material over the dielectric material, depositing an insulative material over the electrode material, and forming integrated circuit components over the insulative material.  
           [0008]    Additional features and advantages of the present invention will be more clearly apparent from the detailed description which is provided in connection with accompanying drawings which illustrate exemplary embodiments of the invention. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    [0009]FIG. 1 is a side-sectional view of a prior art integrated circuit containing a decoupling capacitor;  
         [0010]    [0010]FIG. 2 is a view of the integrated circuit of FIG. 1 at a subsequent stage of fabrication;  
         [0011]    [0011]FIG. 3 is a perspective view of a integrated circuit substrate in accordance with an embodiment of the present invention;  
         [0012]    [0012]FIG. 4 is a cross-sectional view taken along lines IV-IV of the integrated circuit substrate of FIG. 3.  
         [0013]    [0013]FIG. 5A is an exploded view of the fin-like structures of FIG. 4.  
         [0014]    [0014]FIG. 5B is a view of the fin-like structures of FIG. 5A at a subsequent stage of fabrication.  
         [0015]    [0015]FIG. 5C is a view of the fin-like structures of FIG. 5B at a subsequent stage of fabrication.  
         [0016]    [0016]FIG. 6 is a perspective view of the integrated circuit substrate of FIG. 4 at a subsequent stage of fabrication.  
         [0017]    [0017]FIG. 6A is a top view of the integrated circuit substrate of FIG. 6.  
         [0018]    [0018]FIG. 7 is a view of the integrated circuit substrate of FIG. 4 at a subsequent stage of fabrication.  
         [0019]    [0019]FIG. 7A is a top view of the integrated circuit substrate of FIG. 7.  
         [0020]    [0020]FIG. 8 is a side sectional view of an integrated circuit substrate in accordance with another embodiment of the present invention.  
         [0021]    [0021]FIG. 9 is a side view of the integrated circuit substrate of FIG. 8.  
         [0022]    [0022]FIG. 10 is a view of the integrated circuit substrate if FIG. 8 at a subsequent stage of application.  
         [0023]    [0023]FIG. 11 is a top view of the integrated circuit substrate of FIGS.  6  and/or  7  at a subsequent stage of fabrication.  
         [0024]    [0024]FIG. 12 is a side sectional view of the integrated circuit substrate of FIG. 11.  
         [0025]    [0025]FIG. 13 is a side sectional view of the integrated circuit substrate of FIG. 12 at a subsequent stage of fabrication.  
         [0026]    [0026]FIG. 14 is a side sectional view of the integrated circuit substrate of FIG. 13 at a subsequent stage of fabrication.  
         [0027]    [0027]FIG. 15 is a top view of the integrated circuit substrate of FIG. 14.  
         [0028]    [0028]FIG. 16 is a side sectional view of the integrated circuit substrate of FIG. 14 at a subsequent stage of fabrication.  
         [0029]    [0029]FIG. 17 is a top view of an integrated circuit substrate in accordance with an embodiment of the present invention.  
         [0030]    [0030]FIG. 18 is a side sectional view of a fin-like structure and covering material layers in accordance with another embodiment of the present invention.  
         [0031]    [0031]FIG. 19 is a diagram of a computer system according to an embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0032]    In the following detailed description, reference is made to various specific embodiments in which the invention may be practiced. These embodiments are described with sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be employed, and that structural and electrical changes may be made without departing from the spirit or scope of the present invention.  
         [0033]    The term “substrate” used in the following description may include any semiconductor-based structure that has a semiconductor surface. The term should be understood to include silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), silicon-on-nothing (SON), doped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. The semiconductor need not be silicon-based. The semiconductor could be silicon-germanium, germanium, or gallium arsenide. When reference is made to a “substrate” in the following description, previous process steps may have been utilized to form regions or junctions in or on the base semiconductor or foundation.  
         [0034]    Referring now to the drawings, where like elements are designated by like reference numerals, FIG. 3 depicts a portion of a substrate  30  which is formed by methods well known in the art. Preferably, the substrate  30  comprises a heavily doped silicon. The substrate  30  can be doped using Alcatel-Mietec&#39;s deep n-dope + drive process, or another suitable process. In the substrate  30  a microstructure  40  of silicon fins is fabricated utilizing deep anisotropic plasma etching, such as high etch rate bulk silicon etching. An exemplary deep plasma etching technique that can be utilized in the present invention is that disclosed by Tam Pandhumsoporn, et al., “High etch rate, deep anisotropic plasma etching of silicon for MEMS fabrication,” SPIE Vol. 3328, March 1998. As a result of the high etch rate bulk silicon etching, the fan-like structure  40  is formed in the silicon substrate  30 . A helpful illustration of the structure  40  is provided in FIG. 4, that depicts a cross-sectional view along line IV-IV of FIG. 3. FIG. 4 illustrates multiple fins or supports  50  formed in a fan-like pattern about a center of the circular opening of structure  40 . The structure  40  need not be circular and may, for example, be oval in shape.  
         [0035]    The resulting structure  40  is comprised of trenches or open spaces  45  that define a series of fins or supports  50 . Each fin  50  is a microstructure that will ultimately become a capacitor, as will be disclosed herein, so the number of fins  50  etched in the structure  40  will depend on multiple integrated circuit design goals and limitations. A structure  40  having a minimum often ( 10 ) fins  50  is recommended. The fins  50  formed by the above disclosed method have a thickness of approximately 30 microns, however, the thickness can be increased or decreased by the practitioner.  
         [0036]    With reference to FIGS.  5 A-C, formation of the capacitors in accordance with the present invention will be described. FIG. 5A illustrates three of the several fins  50  in the substrate  30  viewed from a perspective similar to that of FIG. 4. Unfilled spaces  45  are between, and define the fins  50 . The fins  50  comprise the bottom electrode, or cell plate, of the resulting capacitor. Next, with reference to FIG. 5B, a layer of dielectric material  55  is deposited over the fins  50  and substrate  30  utilizing a process such as Chemical Vapor Deposition (CVD) for conformal coating of the underlying layers. Another exemplary technique for depositing layer  55  is by low temperature Metal Organic Chemical Vapor Deposition (MOCVD) utilizing (BaSr)TiO 3  films. The MOCVD deposition of BST or BSTO films as a dielectric provides for additional benefits such as conformal coverage of underlying layers and prevention of oxidation. Because the present invention endeavors to form capacitors having high capacitance, it is preferable that the dielectric material have a high dielectric constant, such as 50 or greater, and a thickness of less than 1000 Angstroms. However, the dielectric layer  55  can comprise various materials with a lower dielectric constant and/or having a higher thickness without departing from the scope of the present invention, as comparable changes will affect only the electrical characteristics of the resulting capacitor.  
         [0037]    Thereafter, with reference to FIG. 5C, a top electrode layer  57  is deposited over the dielectric layer  55 . The top electrode layer  57  is preferably a metallic film of a noble metal such platinum. The top electrode layer  57  may have a thickness of less than one (1) micron, however, other thicknesses and materials may be used. The unfilled spaces  45 A between adjacent structures comprising layers  50 ,  55 , and  57  are reduced as compared to unfilled spaces  45  of FIGS. 5A and 5B.  
         [0038]    A perspective view of the resulting structure  40 , after deposition of layers  55  and  57 , is shown in FIGS. 6 and 6A. The substrate  30  is connected to fins  50 , not visible in FIGS. 6 and 6A, and functions as the ground plate of the resulting capacitor(s). The dielectric layer  55  separates both the substrate  30  and the fins  50  from the top electrode layer  57 . The unfilled spaces  45 A separate each individual structure comprising the fin  50 , dielectric  55 , and top electrode  57 . An alternative resulting structure  40  is illustrated in FIGS. 7 and 7A. Therein, unfilled spaces  45 B extend toward the center of the structure  40 . The size and shape of the unfilled spaces  45 A and  45 B will depend, among other factors, on the number of fins  50  etched into the substrate  30 , and the thickness of the fins  50  and the layers  55  and  57 . The structure  40  is completed by depositing into the unfilled spaces  45 A or  45 B an insulating material.  
         [0039]    In another embodiment of the present invention, illustrated in FIGS. 8 and 9, the fins  50  are etched, in accordance with techniques described above, to be separated from the interior wall  43  of structure  40 . This structure, in addition to openings  45  between individual fins  50 , has an opening  45 C between the fins  50  and the interior wall  43  of substrate  30 . Thereafter, utilizing techniques described above, dielectric layer  55  and top electrode layer  57  are deposited over the fins  50 , as shown in FIG. 10. The resulting structure  40  of this embodiment allows for each fin  50 , with layers  55  and  57 , to function as an individual capacitor.  
         [0040]    Next, with reference to FIGS. 11 and 12, the top of the structure  40  and substrate  30  is sealed with an insulative layer  60 . An exemplary material for layer  60  is photo-definable polyimide, such as PI 412 manufactured by Ciba-Geigy Corporation, that is spin-coated onto the surfaces. Alternatively, the insulative layer  60  material can be another insulator. The deposition of the insulative layer, and the deposition of an insulative material into spaces  45 A,  45 B, and  45 C as described above, can be accomplished in one process step. Alternatively, the insulative layer  60  can be deposited to cover only the structure  40 .  
         [0041]    The top surface  41  of structure  40  in FIG. 12, and in subsequent Figures showing a similar side-sectional view, is shown as extending above the top surface  31  of substrate  30 . This represents the added thickness of layers  55  and  57 , deposited over the fins  50 , if the top surfaces of the fins  50  and substrate  30  are elevationally similar, as shown in FIG. 4. The top surface  41  of the structure  40  can be made elevationally similar to or lower than the top surface  31  of substrate  30  by etching the top surfaces of fins  50  to be lower than the top surface  31  of substrate  30  during process steps previously described.  
         [0042]    To form electrical contact opening(s) in the structure  40 , a layer of photoresist  63  is formed over the insulating layer  60  to define openings  65 , as shown in FIG. 13. Thereafter, openings  67  are etched through the insulative layer  60  down to the top electrode layer  57 , and the photoresist layer  63  is subsequently removed, as shown in FIG. 14. An illustrative top view of the openings  67  is shown in FIG. 15. The opening  67 C would be formed if the center of the structure  40  is filled with the top electrode layer  57  in the process steps mentioned above. The quantity and locations of openings  67  to the top electrode layer  57  will be chosen by the practitioner according to the number and/or placement of electrical connections desired in the resulting integrated circuit. If the structure  40  is formed in accordance with the embodiment shown in FIGS. 8, 9, and  10 , openings  67  would be created over each individual capacitor structure.  
         [0043]    An example of a circuit made possible by the present invention is shown in FIG. 16, wherein an electrical via  80  connects the capacitor structure  40  with a voltage line, or a power supply interconnecting layer  75 . The layer  75  may, in turn, supply electrical power to a power layer  77  and various other components. In FIG. 16, layers  70  and  73  can be insulating layers, or layers containing different integrated circuit components, and the via  80  is electrically isolated from those layers.  
         [0044]    The number of capacitor structures  40  can be chosen by the practitioner to accommodate the desired integrated circuit, as illustrated in FIG. 17 that shows a substrate  30  with multiple capacitor structures  40 .  
         [0045]    In another embodiment of the present invention, illustrated in FIG. 18, the fins of structure  40  may be formed to have a larger surface on the top  91  of the fin  90 , resembling a “T” shape. Such structures may be achieved by undercutting and profiling utilizing the high etch rate bulk silicon etching process discussed above. These fins  90  offer the benefit of providing a greater surface area for the resulting capacitor structure, thus enabling a higher resulting capacitance than fins  50  that are uniform in thickness. The fin  90  would then be covered with a dielectric layer  93  and a top electrode layer  95  to complete the capacitor structure. Alternatively, the fins  90  can be undercut and profiled to have a variable thickness, increasing from bottom to top or vice versa.  
         [0046]    [0046]FIG. 19 illustrates a computer system  300  that may incorporate the benefits of the present invention. The system  300  has a memory circuit  321  coupled through bus  310  to a central processing unit (CPU)  302  for performing computer functions, such as executing software to perform desired tasks and calculations. One or more of the memory circuits  321  and CPU  302  may capacitors constructed in accordance with the present invention. One or more input/output devices  304 ,  306 , such as a keypad or a mouse, are coupled to the CPU  302  and allow an operator to manually input data thereto or to display or otherwise output data generated by the CPU  302 . One or more peripheral devices such as a floppy disk drive  312  or a CD ROM drive  314  may also be coupled to the CPU  302 . The computer system  300  also includes a bus  310  that couples the input/output devices  312 ,  314  and the memory circuit  321  to the CPU  302 .  
         [0047]    While exemplary embodiments of the invention have been described and illustrated, it should be apparent that many modifications can be made to the present inventions without departing from their spirit and scope. Accordingly, the invention is not limited by the foregoing description or drawings, but is only limited by the scope of the appended claims.