Abstract:
To generate quickly the several carry signals in a full adder circuit (for example a 40-bit circuit), the circuit is divided into a plurality of sub-circuits of a first type, in which complementary imaginary carry signals are generated parallel to each other. Carry look-ahead circuits are of a dual construction, each first carry look-ahead circuit receiving a logic &#34;0&#34; and each second carry look-ahead circuit receiving a login &#34;1&#34;. So the generated imaginary carry signals are complementary, from which the carry signal proper is selected with the aid of a multiplex switch. The multiplex switch is controlled by the carry signal generated in a preceding sub-circuit of the first type. Since a multiplex switch operates faster than 3-bit or 4-bit wide carry look-ahead circuits, which operate in parallel in groups, the carry signals are consequently generated faster.

Description:
This is a continuation of application Ser. No. 661,526, filed Oct. 15, 1984, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a full adder circuit for adding two n-bit binary numbers, i.e. to a full adder circuit divided into a plurality of cascaded sub-circuits of a first type having a plurality of bit inputs for receiving groups of bit signals having a significance progressing from m to k wherein m&lt;k≦n. The sub-circuit of a first type comprises two sub-circuits of a second type and a selection circuit, first and second sub-circuits of the second type, respectively receiving the respective logic values &#34;0&#34; and &#34;1&#34; at a carry signal input and generating at a carry signal output an imaginary carry signal having a significance k+1. These carry signal outputs are connected to inputs of the selection circuit, a further input of which is connected to an output of a preceding sub-circuit of the first type or a sub-circuit of the second type which is arranged in cascade with the sub-circuit of the first type, at which output a carry signal having a first significance (m) is generated for selecting, with the aid of the selection circuit, a carry signal having a higher significance (k+ 1) from the generated imaginary carry signals and for applying the selected carry signal to a carry signal output of the sub-circuit of the first type. 
     2. Description of the Prior Art 
     Such a logic circuit is described in a publication disclosed during the International Solid State Conference, Feb. 22nd 1984, pages 90, 91, 324 &#34;A CMOS Floating Point Multiplier&#34; by Masaru Kya. The 24 bit-full adder circuit used in the multiplier circuit comprises, arranged in cascade, sub-circuits of a first type which each comprise two parallel-operating (4, 5 or 6 bits) full adder sub-circuits of a second type, respective first and second sub-circuits of the second type receiving a logic signal &#34;0&#34; and &#34;1&#34;, respectively at their carry signal inputs. The two parallel-operating sub-circuits of the second type consequently generate complementary groups of sum signals and complementary imaginary carry signals. A first real carry signal is generated by a first full adder sub-circuit of the second type from the group of least significant bits of the two numbers to be added. The first real carry signal is applied to a multiplexing circuit of a sub-circuit of the first type, which is arranged in cascade with the first full adder sub-circuit of the second type by means of which a group of sum signals is selected from the complementary groups of sum signals applied to the multiplexing circuit. In addition, the sub-circuit of the first type comprises selection means to which the complementary imaginary carry signals are applied and also the first real carry signal. With the last-mentioned carry signal the correct carry signal of a higher significance is selected from the two imaginary carry signals, which in its turn is utilized as the &#34;first real&#34; transfer signal for a subsequent sub-circuit of the first type, arranged in cascade with the sub-circuit of the first type. Using such a full adder circuit it is possible to add together large binary numbers (for example 24-bit numbers) in a comparatively short time. 
     Due to the use of the dual full adder sub-circuits of the second type and the multiplexing circuit connected thereto, the circuit has the disadvantage that a comparatively large semiconductor surface is required. Moreover, the time necessary for adding together binary numbers of, for example, more than 32 to 40 bits, will increase because of the increasing number of series-arranged selection means (gate circuits) required therefor. 
     SUMMARY OF THE INVENTION 
     An object of the invention is to provide a full adder circuit in which the required semiconductor surface is less than in the prior art circuit and in which, in the same short time, or in an even shorter time, binary numbers (having for example 30 to 40 bits) can be added together. 
     A full adder circuit according to the invention is therefore characterized in that the sub-circuits of the second type are carry look-ahead circuits, outputs of which are connected to the carry signal input of the selection circuit whose further input is connected to a carry signal input of a single full adder for adding together two bits of the significance m. Thus, for each group of bits a single full adder generates a single correct sum so that each sub-circuit needs only one full adder. In contrast, the prior art needs two adders to generate two conditional sums for each sub-circuit. 
     A preferred embodiment of a full adder circuit according to the invention is characterized in that a carry look-ahead circuit includes at least two look-ahead units, the consecutive look-ahead units receiving significance-sequential sub-groups (m to 1, 1 to k) from a group of bit signals (wherein m&lt;1≦k) for generating imaginary carry signals having a progressing significance, the selection means including a selection circuit for every two look-ahead units producing imaginary carry signals with the same significance. Carry signal inputs of said selection circuit are connected to the outputs of the last-mentioned two look-ahead units and an output of said selection circuit is connected to an input of a full adder for adding together two bits having the same associated significance. A carry signal having a first significance generated in a preceding sub-circuit of the first type or in a sub-circuit of the second type is applied to a control input of each selection circuit in a sub-circuit of the first type for selecting a carry signal from the two imaginary carry signals applied to the selection circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will now be described in greater detail with reference to the examples illustrated in the accompanying drawing, in which drawing: 
     FIG. 1 shows a block diagram of a full adder circuit according to the invention, 
     FIG. 2 shows a more detailed circuit diagram of a full adder circuit in a preferred embodiment according to the invention, 
     FIG. 3 shows a circuit diagram of a further embodiment of a portion of the full adder circuit according to the invention, and 
     FIG. 4 shows a detail of a fourth embodiment of a portion of a full adder circuit according to the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows a block diagram of a 12-bit full adder circuit 1 according to the invention. The circuit 1 comprises four sub-circuits of the first type arranged in cascade. The sub-circuits of the first type each comprise two sub-circuits of the second type cla 11, 12; cla 21, 22; cla 31, 32 and cla 41, 42, a selection circuit S1, S2, S3, S4 and each three-bit full adders 11, 12, 13 and 14. In this example groups of bit signals a 0 , a 1 , a 2  ; b 0 , b 1 , b 2  . . . a 9 , a 10 , a 11  ; b 9 , b 10 , b 11  are applied to the sub-circuits of the second type cla 11, 12, . . . 41, 42 and to the full adders 11, 12, 13, 14 to determine the sum signals s 0 , s 1 , s 2 , s 3  . . . s 9 , s 10 , s 11  by the respective full adders 11, 12, 13, 14 which consequently also respectively receive carry signals C 0 , C 3 , C 6 , C 9 . The carry signal C 0  is applied from the outside and is usually a logic &#34;0&#34;, unless the full adder circuit 1 shown in FIG. 1 is arranged in cascade with a (similar) full adder circuit for adding together two binary numbers having a number of bits exceeding 12. The carry signals C 3 , C 6  and C 9  (and C 12 ) are generated in the circuit 1. Of two numbers A and B to be added together, three bits a 0 , b 0 , a 1 , b 1 , a 2 , b 2 , whose significance progresses from 0 to 2, are applied to the three-bit full adder 11. The full adder 12 receives the three bits a 3 , b 3  . . . a 5 , b 5  of the next higher significance of the numbers A and B and the full adder 13 receives the three bits a 6 , b 6  . . . a 8 , b 8  etc of a next higher significance. From each pair of applied bits a i , b i  of the same significance an inverted AND-signal a i  ·b i  and an inverted OR-signal a i  +b i  are formed, with which in combination with a carry signal C i  a sum signal s i  and a carry signal C i+1  of a higher significance are determined. The newly generated carry signal C i+1  is used again, in combination with the inverted AND-signal and OR-signal a i  ·b i , a i  +b i  to determine a sum signal s i+1  and a carry signal C i+2 . So as to avoid that for forming the sum signal s 11  (or s n  when two n-bit numbers are added together) all the carry signals C i  (i=0, . . . 11; or i=0, . . . n) must first be sequentially generated, carry look-ahead circuits cla 11, 12, 21, . . . 41, 42 are added to the full adders 11, 12, 13, 14. To generate the imaginary carry signals CC 3  and CC 3 , the inputs I 11  and I 12 , respectively receive a logic &#34;0&#34; level or a logic &#34;1&#34; level, respectively from respective look-ahead circuits cla 11 and cla 12. The look-ahead circuits cla 11, 12 both receive the inverted AND-signals and OR-signals a i  ·b i  and a i  +b i , the index i having the values 0, 1 and 2. The look-ahead circuits cla 11 and 12 generate imaginary carry signals CC 3  and CC 3  which are applied to selection circuit S1 in the form of, for example, a transfer-gate or a conventional logic gate circuit. Applied to a control input of the selection circuit S1 is the incoming carry signals C 0  of significance 0, with which one of the imaginary carry signals CC 3  and CC 3  is selected and applied as a look-ahead carry signal C 3  to the full adder circuit 12. 
     In this way the three-bit full adder 12 can already start generating sum signals s 3 , s 4  before the sum signal s 2  and a carry signal have been formed via the preceding full adder 11. The look-ahead circuits cla 21 and 22 receive the inverted AND- and OR-signals a i  ·b i  and a i  +b i , the index i having the values 3, 4 and 5. The circuits cla 21 and 22 generate imaginary carry look-ahead signals CC 6  and CC 6 , a logic &#34;0&#34; or a logic &#34;1&#34; level, respectively being applied to the carry signal inputs I 21  and I 22 , respectively of the respective look-ahead circuits cla 21 and cla 22. So the imaginary carry signals CC 6  and CC 6  are generated simultaneously with the imaginary carry signals CC 3  and CC 3 . With the look-ahead carry signal C 3  which is chosen with the aid of the incoming carry signal C 0 , the look-ahead carry signal C 6  of the higher significance (6) is selected with the aid of the selection circuit S2. The look-ahead carry signal C 6  is generated relative to the look-ahead carry signal C 3  already after one &#34;gate delay&#34; produced by one of the selection circuits S2. The look-ahead carry signal C 6  is applied to the three-bit full adder 13 and also to selection circuit S3, with which the look-ahead carry signal C 9  is chosen from two imaginary carry signals CC 9  and CC 9 , which are generated in a similar way as and simultaneously with the signals CC 3 , CC 3 , CC 6  and CC 6  by the circuits cla 31 and 32. Thus, after only one gate delay a look-ahead carry signal C 9  having significance 9 (selected via the selection circuit S3) will again be available. 
     Using the look-ahead carry signal C 9  the look-ahead carry signal C 12  is selected by means of the selection circuit S4 from the imaginary carry signals CC 12  and CC 12  generated in the above-described way by the look-ahead circuits cla 41 and 42. 
     From the foregoing it will be obvious that the sum signals s 0 , s 1 , . . . s 11  can be generated very quickly by the full adders 11, 12, 13 and 14, as the look-ahead carry signals C 3 , C 6 , C 9  required for the full adders 11, 12, 13, 14 are sequentially generated, always after a further gate delay. It will be obvious that the selection circuits S1, S2, S3, S4 used are always formed by a two-to-one multiplex circuit, that for each group of bits two look-ahead circuits are required and for each bit only one full adder is necessary, which results in an advantageous reduction of the semiconductor surface required for the full adder circuit according to the invention. For adding together binary numbers with more than 12 bits, it is only necessary to arrange two or more of the full adder circuits 1, shown in FIG. 1 in cascade. 
     FIG. 2 shows an embodiment of a 40-bit full adder circuit 2 according to the invention. The full adder circuit 2 comprises three sub-circuits of the first type SU1, SU2, SU3. The first sub-circuit SU1 comprises a cascade arrangement of four carry look-ahead circuits cl 0, 1, 2, 3 which at their inputs receive from the group of bit signals a 0 , b 0 , a 1 , b 1  . . . a 11 , b 11  applied to sub-circuit SU1 the respective sub-groups a 0 , b 0 , . . . b 2  ; a 3 , b 3  . . . b 5  ; a 6 , b 6  . . . b 8  ; a 9 , b 9 , . . . b 11 . The four sub-groups of bit signals are also applied to four cascade arrangements of three-bit full adders A0-2, A3-5, A6-8, A9-11, respectively. At its carry signal input the carry look-ahead circuit cl 0 receives a carry signal C 0  which generally has the logic value &#34;0&#34;. The sub-circuit of the first type SU1 is an adder circuit which is known per se and determines the sum signals s 0 , s 1 , s 2 , . . . s 11  and a carry signal C 12  from the received carrier signal and the received bit signals. The carry signal C 12  is applied to the carry signal input of a sub-circuit of the first type SU2. 
     The sub-circuit of the first type SU2 comprises a first sub-circuit of the second type cl 4, cl 5, cl 6, cl 7, a second sub-circuit of the second type cl 4&#39;, cl 5&#39;, cl 6&#39;, cl 7&#39;, a selection circuit K5, K6, K7, K8 and full adders A12-14, A15-17, A18-20, A21-23. Said sub-circuits of the second type are carry look-ahead circuits formed from a cascade arrangement of look-ahead sub-circuits cl 4, cl 5, cl 6, cl 7 and cl 4&#39;, cl 5&#39;, cl 6&#39;, cl 7&#39;, respectively. In addition to the above-mentioned carry signal C 12 , the sub-circuit of the first type SU2 receives the groups of bit signals a 12 , a 13 , . . . a 23  and b 12 , b 13 , . . . b 23  with a significance increasing from 12 to 23, inclusive of the two binary numbers A and B. The group of bit signals is divided into sub-groups a 12 , b 12 , a 13 , b 13 , a 14 , b 14  ; a 15 , b 15 , . . . b 17  ; a 18 , b 18 , . . . b 20  ; a 21 , b 21 , . . . b 23  which are applied to the respective look-ahead sub-circuits cl 4 and cl 4&#39;; cl 5 and cl 5&#39;; cl 6 and cl 6&#39;; cl 7 and cl 7&#39; and to the respective full adders A12-14, A15-17, A18-20, A21-23. The carry signal inputs of the look-ahead sub-circuits cl 4 and cl 4&#39;, respectively receive the logic values &#34;0&#34; and &#34;1&#34;, respectively. The look-ahead sub-circuits cl 4 and cl 4&#39;, respectively generate from the applied bit signals a 12 , b 12 , . . . b 14  and from the respective said logic values &#34;0&#34; and &#34;1&#34; the respective imaginary carry signals CC 15  and CC 15&#39;   with significance 15, which are applied respectively to the carry signal inputs of the look-ahead sub-circuit cl 5 and cl 5&#39;, respectively. In addition, the imaginary carry signals CC 15  and CC 15&#39;   are applied to a selection circuit K5, which under the control of the carry signals C 12  selects a real carry signal C 15  from the imaginary carry signals CC 15  and CC 15&#39; . The carry signal C 15  is applied to the carry signal input of the full adder A15. The full adder A12 receives the carry signal C 12  and forms therewith from the bit signals a 12  and b 12  in a manner known in itself the sum signal s 12  and an (internal) carry signal for full adder A13, which forms from the bit signal a 13 , b 13  the sum signal s 13  and also an (internal) carry signal C 14  for adder A14, which produces the sum signal s 14 . Likewise, the full adders A15-17 form the sum signals s 15 , s 16 , s 17  from the carry signal C 15  and the bit signals a 15 , b 15  . . . b 17 . 
     The look-ahead sub-circuits cl 5 and cl 5&#39; do not only receive the imaginary carry signals CC 15  and CC 15&#39;   but also the bit signals a 15 , b 15 , . . . b 17  and from them two imaginary carry signals CC 18  and CC 18&#39;   with significance 18. The imaginary carry signals CC 18  and CC 18&#39;  are applied to a selection circuit K6 and to the signal carry inputs of the look-ahead sub-circuits cl 6 and cl 6&#39;. Using the selection circuit K6 a carry signal C 18  is selected from the two imaginary carry signals CC 18  and CC 18&#39;  under the control of the carry signal C 12 , and is applied to the full adders A18-20. The full adders A18-20 produce the sum signals s 18 , s 19 , s 20  from the carry signal C 18  and the bit signals a 18 , b 18 , . . . b 20 . 
     The imaginary carry signals CC 18  and CC 18&#39;  are applied to the look-ahead sub-circuits cl 6 and cl 6&#39;, which receive in addition the signals a 18 , b 18 , . . . b 20  and produce the imaginary carry signals CC 21  and CC 21&#39;  from the received signals. The imaginary signals CC 21  and CC 21&#39;   are applied to a selection circuit K7, which selects under the control of the carry signal C 12  a carry signal C 21  and conveys it to the full adders A21-23. The full adders A21-23 form the sum signals s 21 , s 22  and s 23  from the carry signal C 21  and the bit signals a 21 , b 21 , . . . b 23 . In addition, the imaginary carry signals CC 21  and CC 21&#39;  are applied to the look-ahead sub-circuits cl 7 and cl 7&#39;, which further receive the bit signals a 21 , b 21 , . . . b 23  and generate the imaginary carry signals CC 24  and CC 24&#39;  from the signals applied. The imaginary carry signals CC 24  and CC 24&#39;  are applied to the selection circuit K8 which under the control of the carry signal C 12  selects the carry signal C 24 , which is applied to the subsequent sub-circuit of the first type SU3 (inter alia to the full adder A24 incorporated therein). 
     The sub-circuit of the first type SU3 comprises first and second sub-circuits of the second type cl 8 to cl 12 and cl 8&#39; to cl 12&#39;, selection means in the form of selection circuits K9 to K13, and full adders A24 to A39. The sub-circuit of the first type SU3 is substantially identical to the sub-circuit of the first type SU2. Four look-ahead sub-circuits of the second type cl 4 to cl 7 and cl 4&#39; to cl 7&#39; are always arranged in cascade in the sub-circuit of the first type SU2. In the sub-circuit of the first type SU3 always five look-ahead sub-circuits of the second type cl 8 to cl 12 and cl 8&#39; to cl 12&#39; are arranged in series. The respective carry signal inputs of look-ahead sub-circuits of the second type cl 8 and cl 8&#39; receive a logic &#34;0&#34; and a logic &#34;1&#34; signal, respectively. In addition, the look-ahead sub-circuits cl 8 and cl 8&#39; receive the bit signals a 24 , b 24 , . . . b 26 . From the signals received the look-ahead sub-circuits cl 8 and cl 8&#39; generate imaginary carry signals CC 27  and CC 27&#39; , which are applied to both the selection circuit K9 and the look-ahead sub-circuits cl 9 and cl 9&#39;. The latter circuits generate the imaginary carry signals CC 30  and CC 30&#39;  from the bit signals a 27 , b 27 , . . . b 29  and said signals CC 27  and CC 27&#39; . The imaginary carry signals CC 30  and CC 30&#39;  are applied to the selection circuit K10 and also to the subsequent look-ahead sub-circuits cl 10 and cl 10&#39;. As will be obvious from the foregoing, the look-ahead sub-circuits cl 10 and cl 10&#39; and the subsequent, similar circuits cl 11 and cl 11&#39;, cl 12 and cl 12&#39; generate the respective imaginary carry signals CC 33  and CC 33&#39; , CC 36  and CC 36&#39;  and CC 39  and CC 39&#39; , which are applied to the associated selection switches K11, K12 and K13, respectively. Using the carry signal C 24 , which controls the selection circuits K9 to K13, the desired carry signals C 27 , C 30 , C 33 , C 36  and C 39  are selected from said imaginary carry signals CC 27 , CC 27&#39;  . . . CC 39&#39;  and are applied to the full adders A24, A27, A30, A33, A36 and A39, respectively, which causes the sum signals s 24 , s 25 , . . . s 39  to be generated. 
     Adding together two binary numbers can be effected very quickly with the above-described 40-bit full adder circuit 2. A look-ahead sub-circuit cl i (0≦i≦12) has, for example, a time delay of τ c  ≈17 nsec. (time elapsed between the instant at which the input signals are presented and the carry signal is supplied). The selection circuits K j  (5≦j≦13) have a time delay τ s  ≈12 nsec., while a three-bit full adder (for example A24-26) has a time delay of τ a  ≈33 nsec. From the different time delays it can be derived that the carry signal C 12  is available after 4×τ c  =68 nsec., that the carry signals C 15 , C 18 , C 21  and C 24  are simultaneously available after 4×τ c  +τ s  =80 nsec., that the carry signals C 27 , C 30 , C 33 , C 36  and C 39  are simultaneously available after 4×τ.sub. c +2×τ s  =92 nsec., and that the sum signal S 38  is available as the last sum signal after 4×τ c  +2×τ s  +τ a  =125 nsec. It should be noted that the imaginary signals CC 24 , CC 24&#39;  and CC 39 , CC 39&#39;  are only available after 4×τ c  =68 nsec. and 5×τ c  =85 nsec., respectively, which (in practice) must preferably be substantially at the instants at which the respective controlling carry signals C 12  and C 24  become available, (for C 12  : 4×τ c  =68 nsec., for C 24  : 4×τ c  τ s  =80 nsec.). 
     FIG. 3 shows a preferred embodiment of a sub-circuit of the first type SU2&#39; of an adder circuit according to the invention, which can be substituted for the sub-circuit of the first type SU2 of FIG. 2, without further measures. Corresponding components in FIGS. 2 and 3, have been given the same reference numerals. For the sake of clarity, FIG. 3 does not show the bit signals to be applied and the inputs for those bit signals. In the sub-circuit SU2&#39; imaginary carry signals CC i  and CC i&#39;  (i=15, 18, 21, 24) are generated simultaneously and are consequently all available after 17 nsec. The imaginary carry signals CC 15  and CC 15&#39;  are applied to the selection circuit K5 (which is the same situation as described with reference to FIG. 2). The imaginary carry signal CC 15  is further applied to the selection switches K6b and K6a. Depending on whether the signal CC 15  has the logic values &#34;0&#34; or &#34;1&#34;, the selection switch K6a or K6b respectively applies the respective imaginary carry signals CC 18&#39;  or CC 18  and CC 18  or CC 18&#39;  to the respective inputs a 6  and b 6  of the selection circuit K6. The signal CC 18  or CC 18&#39;  at the input b 6  of selection circuit K6 also controls the selection switches K7a and K7b, which receive the imaginary signals CC 21  and CC 21&#39;  at their inputs. Depending on whether the logic value &#34;0&#34; or &#34;1&#34; is present at the input b 6  the selection switch K7a or K7b, respectively applies the respective imaginary carry signals CC 21&#39;  or CC 21  and CC 21  or CC 21&#39;  to the respective inputs a 7  and b 7  of the selection circuit K7. The signal CC 21  or CC 21&#39;  at the input b 7  controls in the same way as described above the selection switches K8a and K8b. From the foregoing it follows that the imaginary carry signals CC 24  and CC 24&#39;  are available at the inputs a 8  and b 8  of the selection circuit K8 after 1×τ c  +3× τ s  =53 nsec.; so that the carry signal C 24  is already available after 65 nsec. So the full adder circuit shown in FIG. 2 can be operated faster when the sub-circuit SU2&#39; of FIG. 3 is used in FIG. 2 and the carry signal C 12  is generated more quickly, (15 nsec. more quickly). This faster generation of carry signal C 12  can be accomplished by using in FIG. 2 the full adder circuit 1 of FIG. 1, instead of sub-circuit SU1, a logic value &#34;0&#34; being applied to the carry signal input for the signal C 0 . The carry signal C 12  is then already available in FIG. 1 after ≈1×τ c  +3×τ s  =53 nsec. (as the selection circuit S1 is always in the same position). 
     It should be noted that the sub-circuit SU3 of FIG. 2 can also be replaced by a similar circuit as shown in FIG. 3 which again results in some gain in time for generating the sum signals S 36  to S 39 . In addition, it should be noted that for assembling still larger binary numbers (for example 80 bits and more) it is advisable to introduce a third multiplexed level (32&#39;a, K32&#39;b form the second level, K32a, b form the first level) between the look-ahead sub-circuits cl i (see FIG. 4, i=32) and the full adders (A70-72). The third level (K32) is controlled by the carry signal C 39  generated in the sub-circuit SU3 (FIG. 2) so that all of the carry signals of a higher significance (higher than 40) are already available after a single delay τ s  (12 nsec.). This makes it possible to add together, for example, two 80 bit numbers in approximately 150 nsec. For the sake of clarity it should be noted that then two further (third and fourth) selection switches K32&#39;a, b must be provided in each selection circuit (K32 as shown in FIG. 4), the a-input and b-input, respectively of the selection circuit K32 being connected to the outputs of the selection switches (K32&#39;a, b) and the a-input and b-input, respectively of the third and fourth selection switches (K32&#39;a, b) being connected to the outputs of the respective selection switches K32a, K32b and K32b, K32a. In the example illustrated by FIG. 4 the starting point is the situation in which the sub-circuits SU1, SU2, SU3, SU4 and SU5 (not shown) have respective &#34;widths&#34; of 12, 12, 15, 18, and 21 bits, so that the carry signal C 39  (12+12+15) generated in sub-circuit SU3 controls the third multiplex level (K32) of the sub-circuits SU4 and SU5 and the imaginary carry signal CC 57  (12+12+15+18) generated in sub-circuit SU4 controls the second level (k32&#39;a, b) in the sub-circuit SU5, the signal CC 57  being obtained from the b-input of the selection circuit K19 of the sub-circuit SU4 (the carry signal immediately above the 3 rd  level). 
     The circuits described in the foregoing are formed from full adders, carry look-ahead circuits and multiplex circuits (always choice 1 out of 2), which are all circuits which are known per se and are preferably integrated on a semiconductor substrate, the full adder circuit forming part of a more extensive circuit (multipliers, etc.).