Abstract:
A sigma-delta modulator converting digital input signals x(k) includes a first feedback loop of a spectrally formed output signal y(k) of the sigma-delta modulator and a second feedback loop of a spectrally formed differential signal e(k), obtained from an intermediate signal u(k) and the output signal y(k). The intermediate signal u(k) constitutes the differential signal of the input signal x(k) and the total signal r(k) of the first and second feedback loops. A quantizer determines the output signal y(k) based on the intermediate signal u(k), whereby k is the discrete independent time variable. The sigma-delta converter generates a skew between the output signal y(k) and the input signal x(k).

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is based on and hereby claims priority to European Application No. 01130334.4 filed on Dec. 19, 2001, the contents of which are hereby incorporated by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The invention relates to a sigma-delta modulator for converting broadband digital input signals.  
         [0004]     2. Description of the Related Art  
         [0005]     In digital-to-analog converters, as used, for instance, in digital radio communication systems, a digital input signal having 2 N  signal statuses and a fixed sampling frequency f a  is customarily converted into an analog signal needing to tally as closely as possible with the digital signal in the −f a /2 to +f a /2 frequency range.  
         [0006]     The number of signal statuses requiring to be implemented by analog circuitry poses a substantial problem especially when the bit widths N are large. The digital signal is for this reason interpolated by digital filters and what are termed sigma-delta modulators are employed in the digital-to-analog converters which significantly reduce the digital signal&#39;s bit width with an increased sampling frequency and transform the quantizing noise increased thereby into previously unused frequency ranges. Structures of sigma-delta modulators achieving forming of the noise signal by higher-order IIR (Infinite Impulse Response) filters are particularly efficient here.  
         [0007]     A digital-to-analog converter employing an IIR filter as the interpolation element and one or more sigma-delta modulators for converting the interpolated signals is described in, for example, U.S. Pat. No. 5,786,779.  
         [0008]     A cascaded sigma-delta modulator for a digital-to-analog converter is furthermore presented in DE 197 22 434 C1. S. R. Norswothy, R. Schreier, G. Temes: “Delta-Sigma Data Converters, Theory, Design and Simulation”, IEEE Press 1997, ISBN 0-7803-1045-4, contains a detailed description of the design of sigma-delta modulators and their mode of operation.  
         [0009]     Two approaches are now taken in the sigma-delta modulators to achieve a noise forming:  
         [0010]     According to a first approach, higher-order feedback loops are used which permit a reduction to up to two signal statuses (1-bit signaling technique). However, upward of order-3 noise forming these can lead to possible instabilities in the case of high input signals; overshooting of the value range of internal status memories very easily occurs. To counter this, an amplitude-reduced input signal and status memories having clipping characteristics are used in practice as a result of which empirically ascertainable circuit stability can be achieved.  
         [0011]     According to a second approach, first- and/or second-order cascaded structures are used which, being of multi-stage design, have stable operating characteristics.  
         [0012]     The sigma-delta modulator for converting digital input signals x(k) can include a first feedback loop of a spectrally formed output signal y(k) of the sigma-delta modulator and a second feedback loop of a spectrally formed differential signal e(k) obtained from an intermediate signal u(k) and from the output signal y(k), with the intermediate signal u(k) being the differential signal of the input signal x(k) and the total signal r(k) of the first and second feedback loops, with a quantizer determining the output signal y(k) based on the intermediate signal u(k), and with k being the discrete independent time variable.  
         [0013]     A cascaded sigma-delta modulator having the advantages, on the one hand, of a cascaded approach&#39;s stability in terms of operating characteristics and easier implementability and, on the other hand, the advantages of a small number of stages of a higher-order feedback loop has been described in DE 199 37 246 A1. The number of signal statuses can be reduced to up to two—corresponding to 1 bit—by incorporating an additional logic. Complex clipping circuitry is eliminated without impairing circuit stability. Owing to the circuit&#39;s modularity, an existing structure of an i-th order sigma-delta modulator can be expanded into an i+1-th order circuit by simply an additional logic stage.  
         [0014]     Through the cascading of several first-order modulators the quantizing noise in the low frequency range is evaluated particularly intensely in the target function used. The quantized signal needs to exhibit extreme variations in the time domain in order to transform the quantizing noise into the frequency range. The possibility for this is not provided in the case of, for instance, a two-stage signal and is suppressed by the structure according to DE 199 37 246 A1. Consequently, although noise forming has a higher order as a result of cascading, there is only a limited increase in the frequency range with a specific signal-to-noise ratio at a specified measuring bandwidth, especially in the case of a desired relatively low signal-to-noise ratio.  
       SUMMARY OF THE INVENTION  
       [0015]     An aspect of the present invention is therefore to increase stability in the case of sigma-delta modulators or the cascading of sigma-delta modulators and thus generate sigma-delta modulators having a greater useful-signal bandwidth.  
         [0016]     According to the invention the sigma-delta converter generates a skew between the output signal y(k) and input signal x(k).  
         [0017]     Owing to the skew between x(k) and u(k) or, as the case may be, y(k), the sigma-delta modulator&#39;s result is not based exclusively on the momentary value of x(k) but, instead, several time-shifted values are used for the quantizer&#39;s decision on an output signal. The sigma-delta modulator&#39;s decision is consequently less arbitrarily subject to the momentary status and the quantizing noise in the useful band can be reduced. This makes the sigma-delta converter&#39;s characteristics more stable so that, with increasing stability, signals with a greater useful-signal bandwidth can also be processed.  
         [0018]     In a development of the invention at least one delay element for generating a skew between the output signal y(k) and input signal x(k) is provided, with the at least one delay element creating a skew between clock cycles dependent on the discrete time variable k, a clock cycle being the difference between two succeeding time variables k and k−1. The delay element makes it possible to control how many succeeding, which is to say time-shifted values, are used for the quantizer&#39;s decision on an output signal. This means that the temporal mean-taking depth can be varied by using the delay element. The use of delay elements to time-shift the signals also allows the sigma-delta modulator&#39;s causality to be retained.  
         [0019]     In a technical implementation the at least one delay element can be arranged in such a way that the input signal x(k) is delayed before the differential signal is formed from the input signal x(k) and total signal r(k) of the first and second feedback loops.  
         [0020]     An evaluation unit is advantageously connected upstream of the quantizer with the result signal p(k) from the evaluation unit being routed to the quantizer as an input signal. From the sigma-delta modulator&#39;s viewpoint the quantizer&#39;s decision is thus made on the basis not only of a momentary value but also of “future” or “past” values; mean-taking is performed on adjacent input values so that the sigma-delta modulator&#39;s decision is not subject to the peak values of momentary statuses. Mean-taking in the evaluation unit can be selected to suit the sigma-delta modulator&#39;s required embodiment. The peak values smoothed through mean-taking result in the spectral range to limiting of the quantizing noise to a smaller spectral range as the values that can change quickly over their time curve (large frequency) are re-evaluated through the mean-taking. A greater useful bandwidth not disrupted by the spectral influences of the quantizing noise is thus spectrally available to the useful signals. Mean-taking of the predicator therefore results in a reduction in the quantizing noise because the peak values are smoothed, and the reduction in the quantizing noise implies a greater useful-signal bandwidth. The evaluation unit may also be referred to as a predicator.  
         [0021]     The evaluation unit can in particular include inputs for the input signal x(k), for the intermediate signal u(k), and for the output signal y(k), and an output for the result signal p(k). The inputs enable the evaluation algorithm of the evaluation unit to be made dependent on all the parameters available as a rule in a sigma-delta modulator. The parameters depend in particular on the spectral forming of the feedback signals by filters which can be selected to suit the sigma-delta modulator&#39;s required embodiment. The evaluation algorithm may also be referred to as a predication algorithm.  
         [0022]     In a development of the invention the quantizer images its input signal p(k) onto an output signal y(k) having four, preferably two signal statuses. The stability of the sigma-delta modulator according to the invention is also increased when the number of signal statuses of the output signal is small. As the maximum reduction in signal statuses to only two output signal statuses leads particularly frequently and markedly to instabilities in the known sigma-delta-modulators, the maximum reduction in signal statuses of the output signal is the present invention&#39;s most effective application.  
         [0023]     At least two sigma-delta modulators are arranged particularly advantageously in cascaded fashion, with at least one cascade stage including a sigma-delta modulator having an evaluation unit or predicator. The cascaded sigma-delta modulators can in particular be arranged in such a way that the differential signal is decoupled in the sigma-delta modulator of the cascade stage i, with 1≦i≦(number of cascade stages minus one), and is used in the cascade stage i+1 as an input signal. A likewise increased, structurally engendered, stability of the sigma-delta converter can be achieved as a result of cascading the sigma-delta modulators. Cascaded sigma-delta converters furthermore make it possible to increase the maximum dynamic amplitude of the input signal x(k). Alongside increased stability in terms of operating characteristics, cascading also results in easier implementability because the order of the sigma-delta modulator can be reduced owing to cascading. A sigma-delta modulator having i cascade stages is expanded into a sigma-delta modulator having i+l cascade stages simply by adding a cascade stage without modifying the structure of preceding stages.  
         [0024]     The sigma-delta modulators according to the invention can basically be used in any suitable sigma-delta converters.  
         [0025]     The sigma-delta modulators according to the invention can on the one hand be used for digital-to-analog conversion. In this case, for digital-to-analog conversion the sigma-delta converters include a sigma-delta modulator according to the invention as described above and, connected downstream of this, a digital-to-analog converter.  
         [0026]     The sigma-delta modulators according to the invention can, on the other hand, also be used for analog-to-digital conversion. In this case, for analog-to-digital conversion the sigma-delta converters include an analog-to-digital converter and, connected downstream of this, a sigma-delta modulator according to the invention as described above. The delay element can in this case be embodied employing, for instance, SC (Switched Capacitor) technology.  
         [0027]     With regard to an economical and technically flexible mode of production, the sigma-delta converter can be manufactured using CMOS (Complementary Metal-Oxide-Silicon) technology. This applies to both digital-to-analog and analog-to-digital conversion.  
         [0028]     The sigma-delta converters according to the invention for digital-to-analog conversion and also for analog-to-digital conversion are eminently suitable for use in a radio communication system. The sigma-delta converter is used in particular for digital-to-analog conversion in radio communication transmitting devices and also for analog-to-digital conversion in radio communication receiving devices. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0029]     These and other objects and advantages of the present invention will become more apparent and more readily appreciated from the following description of the preferred embodiments, taken in conjunction with the accompanying drawings of which:  
         [0030]      FIG. 1  is a block diagram of a sigma-delta modulator according to the related art,  
         [0031]      FIG. 2  is a block diagram of a sigma-delta modulator according to the invention having an evaluation unit,  
         [0032]      FIG. 3  is a block diagram of a cascaded sigma-delta modulator according to the invention,  
         [0033]     FIGS.  4 ( a )- 4 ( c ) are waveforms for an example of a decision algorithm according to the related art, and  
         [0034]     FIGS.  5 ( a )- 5 ( c ) are waveforms for an example of a corresponding decision algorithm according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0035]     Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout.  
         [0036]      FIG. 1  shows the structure of a sigma-delta modulator according to the related art. Using the two filters 1-H(z) and 1-G(z), the useful signal x(k) is spectrally formed according to the signal transmission function  
         STF   ⁡     (   z   )       =     1     G   (   z             
 and the noise e(k) of the quantizer Q produced from the differential signal of the output signal y(k) and of the intermediate input signal u(k) of the quantizer is spectrally formed according to the noise transmission function  
         NTF   ⁡     (   z   )       =       H   (   z       G   (   z             
         [0037]     The intermediate signal u(k) is here produced as the differential signal from the input signal x(k) and the fed-back total signal r(k) from the useful signal y(k) formed with 1-G(Z) and the noise signal e(k) of the quantizer Q formed with 1-H(z).  
         [0038]     What is essential now is that the decision of the quantizer Q is made based on the momentary value of the intermediate signal u(k) and hence x(k). This results in significant instabilities if the sigma-delta modulator is of higher order and the noise transmission function is poorly selected.  
         [0039]     According to the invention the decision algorithm of the sigma-delta modulators is now expanded to include a decision unit—referred to below as predicator P—with a predication algorithm, which has been embodied in  FIG. 2 . The input signal x(k) is hereby delayed by a certain length of time, indicated by the delay element Z. The delay element Z causes a v-times delay by the time pulse z −1  and is therefore symbolized by z −v . The non-delayed input signal x(k), as well as the delayed intermediate signal u(k) and output signal y(k) of the quantizer Q are routed to the predicator P and hence to the predication algorithm, whose output signal p(k) determines the statuses assumed by the quantizer Q.  
         [0040]     The advantage of this method compared to the related art is that, from the sigma-delta algorithm&#39;s viewpoint, the decisions of the quantizer Q are made based also on future data. The causality continues to be ensured on account of the delay element Z shown in  FIG. 2 . The decisions are consequently subject less arbitrarily to the momentary status and the quantizing noise in the useful band can be reduced.  
         [0041]     The application according to the invention of the predication algorithm will be described below with the aid of two examples.  
         [0042]     The first application proceeds from a known special case of a sigma-delta modulator shown in  FIG. 1 : G(z)=1 and H(z)=(1−z −1 ) 3 . This choice of noise transmission function results in malfunctioning of a known sigma-delta modulator.  
         [0043]     The following predication values can be calculated with v=2 the number of shifted time pulses and 1−H(z)=3z −1 −3z −2 +z −3 : 
 
 u ( k )= x ( k −2)+3 e ( k −1)−3 e ( k −2)+ e ( k −3) 
 
{circumflex over ( u )} +1 ( k )= x ( k −1)+3 u ( k )−3 e ( k −1)+ e ( k −2) 
 
{circumflex over ( u )} +2 ( k )= x ( k )+3  û   +1 ( k )−3 u ( k )+ e ( k −1) 
 
 Thus with 
 
 e ( k )= u ( k )− y ( k ) 
 
 e ( k +1)= û   +1 ( k )−3 y ( k )− y ( k +1) 
 
 e ( k +2)= û   +2 ( k )−6 y ( k )−3 y ( K +1)− y ( k +2) 
 
 not only the current output value of the sigma-delta modulator but also the value range of future input signals x(k) and decisions goes into the decision process. If the sigma-delta modulator has a two-stage output signal y(k) it is possible, for example, to take  
         y   ⁡     (   k   )       =     {         1       for                 u   ^       +   2       ⁡     (   k   )       ≥   0     ⁢                       -   1         for               u   ^       +   2       ⁡     (   k   )       &lt;   0                 
 
 as the basis for the decision. y(k) is therefore selected such that y(k+1) and y(k+2) can largely compensate it again in the next time steps. The previously unstable sigma-delta modulator is thus stabilized. The essential modification of the sigma-delta modulator compared to the known approach includes the newly added skew of the input signal with respect to the output signal. In the example considered above, these are 2 time pulses (v=2). 
 
         [0044]     For û +2 (k) it is possible to derive a recursion formula facilitating an efficient implementation: 
 
 û   +2 ( k )= x ( k )+3 û   +2 ( k −1)−3 û   +2 ( k −2) û   +2 ( k −3)+10 y ( k −1)−15 y ( k −2)+6 y ( k −3) 
 
         [0045]     The following is advantageous in the case of a three-stage signal having three signal statuses 1, 0, −1:  
         y   ⁡     (   k   )       =     {         1       for           (           u   ^       +   1       ⁡     (   k   )       ≥   1     )     ⋀     (           u   ^       +   2       ⁡     (   k   )       ≥   0     )                 -   1         for           (           u   ^       +   1       ⁡     (   k   )       &lt;     -   1       )     ⋀     (           u   ^       +   2       ⁡     (   k   )       &lt;   0     )               0       otherwise                           
 
         [0046]     What remains problematical despite the predication P is the sigma-delta modulator&#39;s maximum dynamic amplitude, which in the above example is 0.5. For this reason a sigma-delta modulator having the advantages of the stability in terms of operating characteristics and easier implementability of a cascaded approach having the advantages of a small number of stages of a higher-order feedback loop was presented in DE 199 37 246 A1. As a result of the use of a predication algorithm introduced in this patent application in at least one cascade stage, the above described variations in the quantized signal in the time domain only occur to a reduced extent; the bandwidth of the last cascade stages is extended.  
         [0047]      FIG. 3  shows a conditioned cascaded sigma-delta algorithm. The quantizing error of one modulator is here made available to the next as an input signal.  
         [0048]     The mode of operation of the conditioned cascaded sigma delta-modulator is described below with the aid of the application of a 1-bit output signal for the case of a third-order sigma-delta modulator. The third stage, considered below, of the conditioned cascaded sigma-delta modulator receives e 2 (k) as an input signal and, for stability reasons, has been used in the exemplary application presented in DE 199 37 246 A1 only with a three-stage sigma-delta output signal.  
             y   ^     3     ⁡     (   k   )       =     {                 y   ^     3     ⁡     (   k   )       +   1         for         (       (           x   ~     3     ⁡     (   k   )       ≥   1     )     ⋀     (         y   2     ⁡     (   k   )       -                                                       y   ~     3     ⁡     (     k   -   1     )       &lt;   1     )     ⋀     (         y   2     ⁡     (     k   +   1     )       =                                                 1   )     ⋀     (           y   ~     3     ⁡     (   k   )       &lt;   1     )       )     ⋀                                       (       (     1   &gt;         x   ~     3     ⁡     (   k   )       ≥     -   1       )     ⋀                                                     (         y   2     ⁡     (   k   )       -   y       ~     3     ⁢     (     k   -   1     )       &lt;   1     )     ⋀                                           (         y   2     ⁢     (     k   +   1     )       =   1     )     ⋀     (           y   ^     3     ⁡     (   k   )       &lt;   0     )       )                     y   ^     3     ⁡     (   k   )       -   1         for         (     (           x   ~     3     ⁡     (   k   )       &lt;       -   1     ⋀     (         y   2     ⁡     (   k   )       -                                                           y   ~     3     ⁡     (     k   -   1     )       &gt;     -   1       )     ⋀     (         y   2     ⁡     (     k   +   1     )       &lt;                                                 1   )     ⋀     (           y   ^     3     ⁡     (   k   )       &gt;     -   1       )       )     ⋀                                       (       (     1   &gt;         x   ~     3     ⁡     (   k   )       ≥     -   1       )     ⋀     (         y   2     ⁡     (   k   )       -                                                       y   ~     3     ⁡     (     k   -   1     )       &gt;     -   1       )     ⋀                                           (         y   2     ⁢     (     k   +   1     )       &lt;   1     )     ⋀     (           y   ^     3     ⁡     (   k   )       &gt;   0     )       )                   y   ^     3     ⁡     (   k   )             otherwise   ⁢                                     
 
         [0049]      FIG. 4  illustrates the problem occurring here for the application presented in DE 199 37 246 A1.  FIG. 4   a ) shows an exemplary curve of the input signal of the third stage. The signal is totaled by the digital integrator contained implicitly in the sigma-delta modulator (Σ k e 2 (k) in  FIG. 4   b )). It can be seen that large numerical values can occur for the integrated signal. The decision-maker&#39;s output signal ŷ 3 (k) should ideally now counter this characteristic. However, not all instants in time are permitted for a status change from ŷ 3 (k) owing to the secondary condition&#39;s requiring the output signal y(k) to be two-stage. The permitted changeover instants are indicated by arrows in  FIG. 4   b ) as an example. An upward-pointing arrow indicates that the change from ŷ 3 (k)=−2 to ŷ 3 (k)=0 or, as the case may be, from ŷ 3 (k)=0 to ŷ 3 (k)=2 is permitted. A downward-pointing arrow correspondingly indicates that the change from ŷ 3 (k)=2 to ŷ 3 (k)=0 or, as the case may be, from ŷ 3 (k)=0 to ŷ 3 (k)=−2 is permitted.  
         [0050]      FIG. 4   c ) shows the characteristic in the signal (Σ k e 2 (k)−y 2 (k) when the possible switching actions occur favorably. The error signal of the third stage can be seen to be reduced.  FIG. 4   c ) illustrates, in contrast to this, the case where the switching action is only permitted with a delay, as a result of which the error signal exhibits a high degree of overshooting.  
         [0051]      FIG. 5  proceeds from the same output signal of the second stage and the same decision instants as in  FIG. 4 . However, the decision-maker now operates using a predication algorithm: 
   {tilde over (x)}   3p ( k )= {tilde over (x)}   3 ( k )+ e   2 ( k+ 1)− ŷ   3 ( k −1)    {tilde over (x)}   3p1 ( k )= {tilde over (x)}   3p ( k )+ e   2 ( k+ 2)− ŷ   3 ( k −1)    {tilde over (x)}   3p2 ( k )= {tilde over (x)}   3p1 ( k )+ e   2 ( k+ 3)− ŷ   3 ( k −1)    {tilde over (x)}   3p3 ( k )= {tilde over (x)}   3p2 ( k )+ e   2 ( k+ 4)− ŷ   3 ( k −1)              y   ^     3     ⁡     (   k   )       =     {                 y   ^     3     ⁡     (   k   )       +   1         for         (       (         x   3     ⁡     (   k   )       ≥   1     )     ⋀     (         x     3   ⁢   ρ       ⁡     (   k   )       ≥   1     )     ⋀                                           (         x     3   ⁢   ρ1       ⁡     (   k   )       ≥   1     )     ⋀     (         x     3   ⁢   ρ2       ⁡     (   k   )       ≥   1     )     ⋀                                         (         x     3   ⁢   ρ3       ⁡     (   k   )       ≥   2     )     ⋀     (         y   2     ⁢     (   k   )       -                                                     y   ~     3     ⁡     (     k   -   1     )       &lt;   1     )     ⋀     (         y   2     ⁢     (     k   +   1     )       =                                                 1   )     ⋀     (           y   ^     3     ⁡     (   k   )       &lt;   1     )       )     ⋀                                       (       (     1   &gt;       x   3     ⁡     (   k   )       ≥     -   1       )     ⋀                                           (           y   2     ⁡     (   k   )       -         y   ~     3     ⁡     (     k   -   1     )         &lt;   1     )     ⋀                                           (         y   2     ⁡     (     k   +   1     )       =   1     )     ⋀     (           y   ^     3     ⁡     (   k   )       &lt;   0     )       )                     y   ^     3     ⁡     (   k   )       -   1         for         (       (         x   3     ⁡     (   k   )       &lt;     -   1       )     ⋀                                           (         x     3   ⁢   p       ⁢     (   k   )       &lt;     -   1       )     ⋀                                         (         x     3   ⁢   p1       ⁡     (   k   )       &lt;     -   1       )     ⋀                                         (         x     3   ⁢   p2       ⁡     (   k   )       &lt;     -   1       )     ⋀                                         (         x     3   ⁢   p3       ⁡     (   k   )       &lt;     -   2       )     ⋀     (         y   2     ⁢     (   k   )       -                                                     y   ~     3     ⁡     (     k   -   1     )       &gt;     -   1       )     ⋀     (         y   2     ⁢     (     k   +   1     )       &lt;                                                 1   )     ⋀     (           y   ^     3     ⁡     (   k   )       &gt;     -   1       )       )     ⋀                                       (       (     1   &gt;       x   3     ⁡     (   k   )       ≥     -   1       )     ⋀     (         y   2     ⁢     (   k   )       -                                                       y   ~     3     ⁡     (     k   -   1     )       &gt;     -   1       )     ⋀                                           (         y   2     ⁡     (     k   +   1     )       &lt;   1     )     ⋀     (           y   ^     3     ⁡     (   k   )       &gt;   0     )       )                   y   ^     3     ⁡     (   k   )           otherwise                             
         [0052]     Possible overshooting in the error signal  1  is thus determined in advance and so avoided.  FIGS. 5    b ) and  5   c ) show as a dashed line the thresholds for the integrated error which have to be exceeded for a permitted switching action also to be performed.  
         [0053]     The invention has been described in detail with particular reference to preferred embodiments thereof and examples, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention.