Abstract:
A semiconductor device includes semiconductor substrate, a plurality of element forming regions formed on the semiconductor substrate, and an interconnect for connecting the plurality of element forming regions to one another. A concave portion whose upper surface is lower than that of the surfaces of the element forming regions connected by use of the interconnect is formed in the surface of the semiconductor substrate under the interconnect.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2005-246331, filed Aug. 26, 2005, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a semiconductor device for high speed operation.  
         [0004]     2. Descriptions of the Related Art  
         [0005]     Recently, the minimum line width in a process of manufacturing semiconductor devices has been reduced, and dielectric or insulating films have been thinner. In addition, transmission signals in the semiconductor device have flown at a higher speed and had higher frequencies. Accordingly, it becomes prominent that the transmission signals deteriorate due to influence of parasitic elements.  
         [0006]     As for a method of reducing the influence of parasitic elements, a low-permittivity insulator is used as an interlayer dielectric between interconnects and a substrate. In addition, a method has been proposed of enlarging a thickness of an interlayer dielectric between the interconnects and the substrate has a larger thickness, in other words, of designing the distance between interconnects and a semiconductor substrate to be larger (for example, refer to Japanese Patent Application Laid-Open No. 2002-57215 and Japanese Patent Application Laid-Open No. Hei 5-211243).  
         [0007]     Although each of the methods can provide an effect of reducing the influence of the parasitic elements, the methods cause the height of space necessary for interconnects to become larger. Hence, there is a problem that such methods are not suitable for a manufacturing process using the smaller minimum line width.  
       SUMMARY OF THE INVENTION  
       [0008]     According to a first aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a plurality of element forming regions formed on the semiconductor substrate; and an interconnect for connecting the plurality of element forming regions to one another, wherein a concave portion whose upper surface is lower than that of the surfaces of the element forming regions connected by use of the interconnect is formed in the surface of the semiconductor substrate under the interconnect. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]      FIG. 1  is a cross sectional view of a semiconductor device of a first example, taken along the line A-A′ shown in  FIG. 3 .  
         [0010]      FIG. 2  is a top view of a semiconductor device of the present invention.  
         [0011]      FIG. 3  is an enlarged view of a part of the semiconductor device of  FIG. 2 .  
         [0012]      FIG. 4  is a view illustrating an equivalent circuit indicating a parasitic element of the semiconductor device of the first example.  
         [0013]      FIG. 5  is a cross sectional view of a semiconductor device of a second example, taken along the line A-A′ shown in  FIG. 3 .  
         [0014]      FIG. 6  is a view illustrating an equivalent circuit indicating a parasitic element of the semiconductor device of the second example.  
         [0015]      FIG. 7  is a cross sectional view of a semiconductor device of a third example, taken along the line A-A′ shown in  FIG. 3 .  
         [0016]      FIG. 8  is illustrating an equivalent circuit indicating a parasitic element of the semiconductor device of the second example.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
     First Example  
       [0017]     By referring to FIGS.  1  to  4 , descriptions will be provided for a semiconductor device of a first example of the present invention.  
         [0018]      FIG. 1  is a cross sectional view of a semiconductor device of the first example, taken along the line A-A′ shown in  FIG. 3 .  FIG. 2  is a top view of the semiconductor device of the first example.  FIG. 3  is an enlarged view of a part of the semiconductor device of  FIG. 2 .  
         [0019]     As illustrated in FIGS.  1  to  3 , the semiconductor device of the first example includes a first MOS transistor  2 , a second MOS transistor  3 , an interconnect  4 , a first gate control circuit  5 , a second gate control circuit  6 , and an interlayer dielectric  13 , all of which are on a semiconductor substrate such as a silicon substrate  1 .  
         [0020]     Each of the first and second MOS transistors  2  and  3  is a device forming region formed on the silicon substrate  1 , and functions as a transistor.  
         [0021]     The transistor  2  includes a first source  7 , a first gate  8  and a first drain  9 . The transistor  3  includes a second source  10 , a second gate  11  and a second drain  12 .  
         [0022]     The first gate control circuit  5  is connected to the first gate  8 , and makes an on/off control of the transistor  2 . The second gate control circuit  6  is connected to the second gate  11 , and makes an on/off control of the transistor  3 .  
         [0023]     The first drain  9  and the second source  10  are connected to each other via the interconnect  4 . The first source  7  and the second drain  12  are connected respectively to other elements not illustrated in  FIG. 3  via interconnects not illustrated in  FIG. 3 .  
         [0024]     In the semiconductor device of the first example, the width W of the interconnect  4  is 90 nm, and the distance D between the first drain  9  and the second source  10  is approximately 400 nm.  
         [0025]     A concave portion  20  is formed in the upper surface of the silicon substrate  1  under the interconnect  4 . The concave portion  20  has a linear groove shape. The width of the concave portion  20  is approximately 90 nm which is approximately equal to the width W of the interconnect  4 . The length of the concave portion  20  is approximately 400 nm which is approximately equal to the distance D between the first drain  9  and the second source  10 . The depth of the concave portion  20  is approximately 25 nm which is approximately equal to each of the depths of the first drain  9  and the second source  10 . The concave portion  20  is formed by etching, for example, by anisotropic etching, the upper surface of the silicon substrate  1  to a predetermined depth.  
         [0026]     The distance d 0  between the upper surface of the silicon substrate  1  and the lower surface of the interconnect  4  is approximately 250 nm. The distance d 1  between the bottom surface of the concave portion  20  in the upper surface of the silicon substrate  1  and the lower surface of the interconnect  4  is approximately 275 nm.  
         [0027]     Subsequently, with reference to  FIG. 4  and equations, descriptions will be provided for an effect of the concave portion  20 .  
         [0028]      FIG. 4  is a view illustrating an equivalent circuit indicating a parasitic element of the case where a transmission signal flows from the first drain  9  to the second source  10  through the interconnect  4 . The transmission signal flows from an input terminal  30  to an output terminal  31 , both located on the interconnect  4 .  
         [0029]     The interconnect  4  is shown as a first resistance component  33  of a resistance value R 1 . The distance between the lower surface of the interconnect  4  and the bottom surface of the concave portion  20  is shown as a capacitor component  34  of a capacitor C 1 . The silicon substrate  1  is shown as a second resistance component  35  of a resistance value R 2 .  
         [0030]     The capacitance C of the capacitor is represented by 
 
 C =ε×( s/d ),
 
 where s, d, ε denote respectively the area of electrodes of a capacitor, the distance between the electrodes of the capacitor, and the permittivity of a dielectric interposed between the electrodes of the capacitor. In other words the capacitance of the capacitor is inversely proportional to the distance between the electrodes. 
 
         [0031]     Since the concave portion  20  is formed in the semiconductor device of the first example, the distance d 1  between the lower surface of the interconnect  4  and the bottom surface of the concave portion  20  is 10% longer than the distance d 0  between the lower surface of the interconnect  4  and the upper surface of the silicon substrate  1 . Here, let C 0  denote the capacitance of the capacitor of the case where the concave portion  20  is not formed. The capacitance C 1  of the first capacitor component  34  is 9% smaller than the capacitance C 0 , when the capacitance C 1  is calculated back to based on the fact that d 1  is approximately 10% longer than d 0 .  
         [0032]     As shown in  FIG. 4 , V in  and V out  denote respectively a voltage applied to the input terminal  30  and a voltage outputted from the output terminal  31 . In the case where the transmission signal flows through the interconnect  4 , the equivalent circuit including the parasitic element functions as a low-pass filter. In other words, V in  is attenuated due to the influence of the low-pass filter, and the attenuated V in  is outputted as V out .  
         [0033]     When H 1  denotes the transfer function of the low-pass filter, H 1  is represented by, 
 
 H 1 =V   out   /V   in .
 
 Here, when the denominator of the transfer function is 0, the frequency is the cutoff frequency. When the cutoff frequency is defined as Fp, Fp of the semiconductor device of the first example is represented as follows,  
             Fp   =       1     2   ⁢   π   ⁢           ⁢       C   1     ⁡     (       R   1     +     R   2       )           .             (   1   )             
 
         [0034]     As can be seen from the equation (1), the cutoff frequency Fp is inversely proportional to the capacitance C 1 . In other words, the smaller the capacitance C 1  becomes, the higher the cutoff frequency Fp becomes. This means that Fp shifts toward a higher frequency.  
         [0035]     When the transmission signal contains a rectangular wave, rise and fall times of a transmission signal generally need to be shorter in order to ensure a sampling time, as a rate of the transmission signal becomes faster. In other words, the shorter rise and fall times of the transmission signal allows the transmission signal to contain a higher frequency component. That is, as the transmission signal flows at a higher speed, even the higher frequency component needs to flow through the interconnect  4 .  
         [0036]     In the semiconductor device of the first example, the capacitance C 1  of the first capacitor component  34  is 9% smaller than that of the case where the concave portion  20  is not formed. Accordingly, as can be seen from the equation (1), the cutoff frequency is 10% higher. This allows the frequency component of the approximately 10% higher frequency to flow through the interconnect  4 . Consequently, the faster transmission signal flows through the interconnect  4  than that of the case where the concave portion  20  is not formed.  
         [0037]     As described above, since the semiconductor device of the first example has a configuration in which the upper surface of the silicon substrate  1  is etched, it is not necessary to build up, for example, an interlayer dielectric to a height more than that of a usually formed interlayer dielectric. Accordingly, the semiconductor device is suitable for the manufacturing process using the smaller minimum line-width.  
         [0038]     In addition, the concave portion  20  may be formed together with a different portion such as an element isolation region in one manufacturing step, by using, for example, the anisotropic etching technique. Accordingly, the concave portion  20  may be formed without adding an additional step to the steps of predetermined manufacturing processes.  
         [0039]     The capacitance C 1  may be changed depending on the depth of the concave portion  20 . The semiconductor device of the first example has a configuration in which the capacitance C 1  is 9% lower than that of the case where the concave portion  20  is not formed. However, another arbitral capacitance may be adopted.  
         [0040]     The first example shows the example of the semiconductor device in which the concave portion  20  has the liner groove shape. However, any shape may be adopted, as long as the concave portion  20  is formed by etching down the upper surface of the silicon substrate  1  under the interconnect  4  to obtain the similar effect.  
         [0041]     The first example shows the example of the semiconductor device in which the concave portion  20  has the width approximately equal to the width W of the interconnect  4 , and has the length approximately equal to the distance D between the first drain  9  and the second source  10 . However, the concave portion  20  may have a shape with a larger or smaller width and a shorter length than those of the first example, as long as the concave portion  20  is formed by etching down the upper surface of the silicon substrate  1  under the interconnect  4  to obtain the similar effect.  
       Second Example  
       [0042]     By referring to  FIGS. 2, 3 ,  5  and  6 , descriptions will be provided for a semiconductor device of a second example of the present invention.  
         [0043]      FIG. 5  is a cross sectional view of a semiconductor device of the second example, taken along the line A-A′ shown in  FIG. 3 .  FIG. 2  is a top view of the semiconductor device of the second example.  FIG. 3  is an enlarged view of a part of the semiconductor device of  FIG. 2 .  
         [0044]     As illustrated in  FIGS. 2, 3  and  5 , the semiconductor device of the second example includes a first MOS transistor  2 , a second MOS transistor  3 , an interconnect  4 , a first gate control circuit  5 , a second gate control circuit  6  and an interlayer dielectric  13 , all of which are on a silicon substrate  1  as in the case of the first example. Descriptions of the configuration of these circuits are omitted here, since the configuration is the same as that of the first example.  
         [0045]     A concave portion is provided in the upper surface of the silicon substrate  1  under the interconnect  4 . A resistive load part  21  is formed in the concave portion. The resistive load part  21  is a resistive region formed along the interconnect  4 . The upper surface of the resistive load part  21  is in the same plane as the upper surface of the silicon substrate  1 .  
         [0046]     The width of the resistive load part  21  is approximately 90 nm which is approximately equal to the width W of the interconnect  4 . The length of the resistive load part  21  is approximately 400 nm which is approximately equal to a distance D between the first drain  9  and the second source  10 . The thickness of the resistive load part  21  is approximately 25 nm which is approximately equal to the depths of the first drain  9  and the second source  10 .  
         [0047]     The resistive load part  21  is a region having a resistance higher than that of the silicon substrate  1 . In the semiconductor device of the second example, the silicon substrate  1  is p-type silicon and has a resistance of 10 0  Ω·cm, while the resistive load part  21  has a resistance of 10 4  Ω·cm.  
         [0048]     The resistive load part  21  is formed, for instance, by etching the silicon substrate  1 , and then, by burying an insulator or a high-load substance in the etched portion. Alternatively, the resistive load part  21  may be formed by directly doping the silicon substrate with a high resistance substance by ion implantation, and then, by annealing the substrate  1 .  
         [0049]     Subsequently, descriptions will be provided for an effect of the resistive load part  21  with reference to  FIG. 6  and equations.  
         [0050]      FIG. 6  is a view illustrating an equivalent circuit indicating a parasitic element of the case where a transmission signal flows from the first drain  9  to the second source  10  through the interconnect  4 . The transmission signal flows from an input terminal  30  to an output terminal  31  through the interconnect  4 .  
         [0051]     The interconnect  4  is shown as a first resistance component  33  of a resistance value R 1 . The distance between the interconnect  4  and the silicon substrate  1  is shown as a capacitor component  36  of a capacitance C 2 . The silicon substrate  1  is shown as a third resistance component  37  of a resistance value R 3 .  
         [0052]     Here, V in  and V out  respectively denote a voltage applied to the interconnect  4  and a voltage outputted from the interconnect  4 . In the case where a signal flows from the first drain  9  to the second source  10  through the interconnect  4 , the equivalent circuit including the parasitic element function as a low-pass filter as in the case of the first example.  
         [0053]     As illustrated in  FIG. 6 , V in  and V out  denote respectively a voltage applied to the input terminal  30  and a voltage outputted from the output terminal  31 . In this case, the equivalent circuit including the parasitic element functions as the low-pass filter. In other words, V in  is attenuated due to the influence of the low-pass filter, and the attenuated V in  is outputted as V out .  
         [0054]     Let H 2  be the transfer function of the low-pass filter. The transfer function is represented by 
 
 H 2 =V   out   /V   in .
 
 Here, let f denotes a frequency. If ω2πf and s=jω, H 2 (s)is calculated by  
               H   ⁢           ⁢   2   ⁢     (   s   )       =         V   out       V   in       =         1   +       sC   2     ⁢     R   3           1   +       sC   2     ⁡     (       R   1     +     R   3       )           .               (   2   )             
 
         [0055]     With regard to the equation, the impedance 1/sC 2  of the capacitance C 2  is close to 0 in a higher frequency domain above the cutoff frequency Fp described in the first example. For this reason, the value of V out  may be calculated by the following equation:  
               V   out     =         R   3         R   1     +     R   3         ·       V   in     .               (   3   )             
 
         [0056]     As shown in the equation (3), V out  is obtained by dividing V in  by the first and third resistance components  33  and  37  In other words, as the third resistance component  37  increases, V out  increases.  
         [0057]     In the semiconductor device of the second example, the resistance value R 3  of the third resistance component  37  is larger than that of the case where the resistive load part  21  is not formed. For this reason, V out  becomes larger in the higher frequency domain above the cutoff frequency. This facilitates the flow of the higher frequency component through the interconnect  4 , and the transmission signal is transmitted at a high speed with little attenuation as compared with the case where the resistive load part  21  is not formed.  
         [0058]     Moreover, the semiconductor device of the second example makes it possible to further facilitate the flow of the frequency component in the higher frequency domain above the cutoff frequency.  
         [0059]     The semiconductor device of the second example has a configuration in which the resistive load part  21  is buried in the upper surface of the silicon substrate  1 . Hence, it is not necessary to build up an interlayer dielectric to a height more than that of a usually formed interlayer dielectric. Accordingly, the semiconductor device is particularly suitable for a manufacturing process using the smaller minimum line-width.  
         [0060]     In addition, the resistive load part  21  may be formed together with, for example, an element isolation region in a single manufacturing step, by using the anisotropic etching technique or the ion implantation method. Accordingly, the resistive load part  21  may be formed without adding an additional step to the steps of predetermined manufacturing processes.  
         [0061]     In addition, the resistance of the resistive load part  21  may be changed by changing a material of the high-load substance to be used or the shape of the resistive load part  21 . In the semiconductor device of the second example, the resistance of the resistive load part  21  is 10 4  Ω·cm, but another arbitral value of resistance may be adopted.  
         [0062]     The second example shows the example of the semiconductor device in which the resistive load part  21  is formed along the interconnect  4 . However, another arbitral shape may be adopted as long as the resistive load part  21  is formed under the interconnect  4  to obtain the similar effect.  
         [0063]     The second example shows the example of the semiconductor device in which the resistive load part  21  has the width approximately equal to the width W of the interconnect  4  and the length approximately equal to the distance D between the first drain  9  and the second source  10 . However, the resistive load part  21  may have a shape with a larger or smaller width and with a shorter length than those of the first example, as long as the resistive load part  21  is formed under the interconnect  4  to obtain the similar effect.  
         [0064]     In addition, in the second example, the example of the semiconductor device has the configuration, in which the resistive load portion  21  is buried in the upper surface of the silicon substrate  1 . However, it is also possible to adopt a configuration obtained by forming a concave portion in the upper surface of the silicon substrate  1  and by depositing the resistive load part  21  in the concave portion.  
       Third Example  
       [0065]     By referring to  FIGS. 2, 3 ,  7  and  8 , descriptions will be provided for a semiconductor device of a third example of the present invention.  
         [0066]      FIG. 7  is a cross sectional view of a semiconductor device of the third example taken along the line A-A′ shown in  FIG. 3 .  FIG. 2  is a top view of the semiconductor device of the second example.  FIG. 3  is an enlarged view of a part of the semiconductor device of  FIG. 2 .  
         [0067]     As illustrated in  FIGS. 2, 3  and  7 , the semiconductor device of the third example includes a first MOS transistor  2 , a second MOS transistor  3 , an interconnect  4 , a first gate control circuit  5 , a second gate control circuit  6 , and an interlayer dielectric  13 , all of which are on a semiconductor substrate  1 , as in the case of the first example. Descriptions for the configuration of the circuits are omitted here, since the configurations is the same as that of the first example.  
         [0068]     A concave portion  20  is formed in the upper surface of the silicon substrate  1  under the interconnect  4 . As in the case of the first example, the concave portion  20  has a linear groove shape and has a width, a length and a thickness which are approximately 90 nm, approximately 400 nm and approximately 25 nm, respectively.  
         [0069]     A resistive load part  23  is formed in the bottom surface of the concave portion  20 . As in the case of the resistive load part  21  described in the second example, the resistive load part  23  is formed along the interconnect  4 , and is a resistive region having a resistance higher than that of the silicon substrate  1 . The resistive load part  23  has a width, a length and a thickness which are approximately 90 nm, approximately 400 nm and approximately 25 nm, respectively.  
         [0070]     In the semiconductor device of the third example, the silicon substrate  1  is p-type silicon and has a resistance of 10 0  Ω·cm, while the resistive load part  23  has a resistance of 10 4  Ω·cm.  
         [0071]     As in the case of the first example, the concave portion  20  is formed by etching the upper surface of the silicon substrate  1  to a predetermined depth by, for instance, anisotropic etching.  
         [0072]     After the concave portion  20  is formed, the resistive load part  23  is formed, for instance, by etching the silicon substrate  1  under the concave portion  20 , and then, by burying an insulator or a high-load substance in the etched portion. Alternatively, the resistive load part  23  may be formed by directly doping the silicon substrate  1  with a high resistance substance by ion implantation, and then, by annealing the silicon substrate  1 .  
         [0073]     As in the case of the first example, the distance d 0  between the silicon substrate  1  and the lower surface of the interconnect  4  is approximately 250 nm, and the distance d 1  between the silicon substrate  1  and the bottom surface of the concave portion  20  is approximately 275 nm.  
         [0074]     Descriptions will be provided below for an effect of the resistive load part  23  with reference to  FIG. 8  and equations.  
         [0075]      FIG. 8  is a view illustrating an equivalent circuit indicating a parasitic element of the case where a transmission signal flows from the first drain  9  to the second source  10  through the interconnect  4 . The transmission signal flows from an input terminal  30  to an output terminal  31  through the interconnect  4 .  
         [0076]     The interconnect  4  is shown as a first resistance component  31  of a resistance value R 1 . The distance between the interconnect  4  and the silicon substrate  1  is shown as a capacitor component  34  of a capacitance C 1 . The silicon substrate  1  having the resistive load part  23  is shown as a third resistance component  37  of a resistance value R 3 .  
         [0077]     Here, V in  and V out  respectively denote a voltage applied to the interconnect  4  and a voltage outputted from the interconnect  4 . In the case where a transmission signal flows from the first drain  9  to the second source  10  through the interconnect  4 , the equivalent circuit including the parasitic element functions as a low-pass filter as in the case of the first and second examples.  
         [0078]     In the semiconductor device of the third example, the capacitance C 1  of the first capacitor component  34  is 9% smaller than that of the case where the concave portion  20  is not formed. Accordingly, as described in the first example, the faster transmission signal flows through the interconnect  4  than that of the case where the concave portion  20  is not formed.  
         [0079]     In the semiconductor device of the third example, the resistance value R 3  of the third resistive component  37  is larger than that of the case where the resistive load part  23  is not formed. Hence, this facilitates the flow of the frequency component through the interconnect  4  in the higher frequency domain above the cutoff frequency, as is the case with the effect of the resistive load part  21  described in the second example. Thus, the transmission signal is transmitted at a high speed with little attenuation as compared with the case where the resistive load part  23  is not formed.  
         [0080]     As described above, the transmission signal is transmitted at a high speed with little attenuation in the higher frequency domain above the cutoff frequency in the semiconductor device of the third example. In addition, the cutoff frequency shifts toward the higher frequency. In other words, the semiconductor device of the third example makes it possible to facilitate the flow of the higher frequency component through the interconnect  4 .  
         [0081]     Since the semiconductor device of the third example has a configuration in which the upper surface of the silicon substrate  1  is etched down to form the concave portion  20 , it is not necessary to build up, for example, an interlayer dielectric to a height more than that of a usually formed interlayer dielectric. In addition, since the resistive load part  23  is buried in the bottom surface of the concave portion  20 , it is also not necessary to build up an interlayer dielectric to a height more than that of a usually formed interlayer dielectric. Accordingly, the semiconductor device is especially suitable for the manufacturing process using the smaller minimum line-width.  
         [0082]     In the semiconductor device of the third example, the concave portion  20  and the resistive load part  23  may be formed together with, for example, an element isolation region in a single manufacturing step, by using the anisotropic etching technique or the ion implantation method. Thereby, the concave portion  20  and the resistive load part  23  may be formed together with a different part in a single step as in the case of the second first and second examples without adding an additional step to the steps of predetermined manufacturing processes.  
         [0083]     Furthermore, the capacitance C 1  may be changed depending on the depth of the concave portion  20  as in the case of the first example. Accordingly, another arbitral capacitance may be adopted, although the semiconductor device of the third example has a configuration in which the capacitance C 1 , is 9% smaller than that of the case where the concave portion  20  is not formed.  
         [0084]     As in the case of the second example, the resistance of the resistive load part  23  may be changed by changing a material of the high-load substance to be used or the shape of the resistive load part  23 . Accordingly, another arbitral value may be adopted, although the resistance of the resistive load part  23  is 10 4  Ω·cm in the semiconductor device of the third example.  
         [0085]     The third example shows the example of the semiconductor device in which the concave portion  20  has the liner groove shape. However, any arbitral shape may be taken, as long as the concave portion  20  is formed by etching down the upper surface of the silicon substrate  1  under the interconnect  4  to obtain the similar effect.  
         [0086]     The third example shows the example of the semiconductor device in which the concave portion  20  has the width approximately equal to the width W of the interconnect  4  and the length almost equal to the distance D between the first drain  9  and the second source  10 . However, the concave portion  20  may have a shape with a larger or smaller width and a shorter length than those of the third example, as long as the concave portion  20  is formed by etching down the upper surface of the silicon substrate  1  under the interconnect  4  to obtain the similar effect.  
         [0087]     The third example shows the example of the semiconductor device in which the resistive load part  23  is formed along the interconnect  4 . However, another arbitral shape may be adopted as long as the resistive load part  23  is formed under the interconnect  4  to obtain the similar effect.  
         [0088]     The third example shows the example of the semiconductor device in which the resistive load part  23  has the width approximately equal to the width W of the interconnect  4  and the length almost equal to the distance D between the first drain  9  and the second source  10 . However, the resistive load part  23  may have a shape with a larger or smaller width and a shorter length than those of the third example, as long as the resistive load part  23  is formed under the interconnect  4  to obtain the similar effect.  
         [0089]     Furthermore, the third example shows the example that the resistive load part  23  is configured by being buried in the bottom surface of the concave portion  20  in the silicon substrate  1 . However, the resistive load part  23  may be configured by etching the bottom surface of the concave portion, and then, by depositing the resistive load part  23 .  
       (Other Embodiments)  
       [0090]     In each of the semiconductor devices of the first to the third examples of the present invention, the first source  7 , the first drain  9 , the second source  10  and the second drain  12  are formed in this order, from left to right, as illustrated in FIGS.  1  to  8 . However, it is also possible to have a configuration in which the positions of the sources are replaced respectively with the positions of the corresponding drains. That is, the configuration may be adopted as well in which the first drain  9 , the first source  7 , the second drain  12 , and the second source  10  are formed in this order, from left to right.  
         [0091]     In each of the first to third examples, the example of the semiconductor device including the MOS transistor is shown. However, the semiconductor device may consist of a capacitor or a bipolar transistor which have a trench-structure.  
         [0092]     Each of the semiconductor devices of the first to third examples of the present invention includes the interlayer dielectric  13 . However, the semiconductor device may be configured by using a substance having a lower permittivity in place of the interlayer dielectric  13  to further reduce the capacitances C 1  and C 2  respectively of the first and second capacitor components  34  and  36 .  
         [0093]     In each of the semiconductor devices of the first to third examples of the present invention, the concave portion  20 , the resistive load part  21  and the resistive load part  23  are formed in the surface of the silicon substrate  1 . However, it is also possible to have a configuration in which the concave portion  20 , the resistive load part  21  and the resistive load part  23  are formed in a region in, for example, a p-type well or an n-type well in the semiconductor substrate as long as they are provided under the interconnect  4 .  
         [0094]     Each of the semiconductor devices of the first to third examples of the present invention has a multilevel interconnect structure. Although each of the examples illustrates only the region around the interconnect  4  of the semiconductor device, it is also possible to have a configuration in which an unillustrated interconnect is provided above the interconnect  4 .  
         [0095]     Each of the semiconductor devices of the first to third examples of the present invention may be configured of the interconnect  4  made of an arbitral interconnect material in addition to aluminum interconnect, aluminum-copper interconnect or copper interconnect.  
         [0096]     Each of the first to third examples of the present invention shows, for instance, the lengths and widths of the interconnect  4  and the concave portion  20  of the semiconductor device  20 . However, a different length and a different width of each of the interconnect  4  and the concave portion  20  may be adopted to configure the semiconductor device depending on a generation of manufacturing processes to be used or a type of circuit to be used.  
         [0097]     Although the present invention has been described with the examples and embodiments as described above, the descriptions and drawings constituting a part of the disclosure simply illustrate the devices and the methods for embodying the technical idea of the invention. Accordingly, the technical idea of the present invention does not limit the configuration of the components, positions thereof and the like to those described in the above examples and embodiments. Various modifications may be made to the technical idea of the present invention within the scope of claims.