Abstract:
An integrated circuit providing high equivalent capacitance ranging from a few tens of picofarads to a few nanofarads is presented. The integrated circuit includes active integrated circuit components, requires no external capacitor, and is substantially insensitive to transistor current gain variations. The high capacitance integrated circuit can be advantageously used to provide, for example, timing delay and servo loop compensation.

Description:
BACKGROUND OF THE INVENTION 
   This invention relates to integrated circuits. More particularly, this invention relates to integrated circuits that provide high capacitance. 
   Very often, electrical circuits require a high capacitance ranging from a few tens of picofarads to a few thousand picofarads (i.e., nanofarads). Such high capacitance is used, for example, to compensate a servo loop or to delay signal timing. However, integrated circuits typically can provide capacitance only in the tens of picofarads because of the practicalities and economics of integrated circuit fabrication. 
   A common solution is to add an external or discrete capacitor to an integrated circuit requiring high capacitance. However, this requires a connection from the external capacitor to an integrated circuit package pin, which in many instances may not be available. Moreover, physical space for the addition of an external capacitor may also not be available depending on the component density and packaging of the system or device in which the integrated circuit is used. 
   As used herein, the term “integrated circuit” does not necessarily refer to a complete integrated circuit chip, but can instead refer to an integrated circuit portion of an integrated circuit chip. However, an integrated circuit does not refer to more than one integrated circuit chip. 
   Another known solution is to use area ratios of transistors on an integrated circuit to effectively “multiply” existing capacitance in the circuit to provide a desired high equivalent capacitance. However, capacitance multiplication is very sensitive to variations in transistor current gain, which in turn is sensitive to process variations and operating temperatures. Thus, known integrated multiplier circuits cannot be reliably fabricated with a specific effective capacitance, nor is an effective capacitance of known multiplier circuits likely to remain constant during subsequent circuit operation. Furthermore, only low multiplication factors (less than about 40) are possible because of transistor size limitations on integrated circuits. 
   In view of the foregoing, it would be desirable to be able to provide an integrated circuit having a high equivalent capacitance that does not require additional components external to the integrated circuit. 
   It would also be desirable to be able to provide an integrated circuit having a specified high equivalent capacitance that is substantially unaffected by transistor current gain variations. 
   SUMMARY OF THE INVENTION 
   It is an object of this invention to provide an integrated circuit having a high equivalent capacitance that does not require additional components external to the integrated circuit. 
   It is also an object of this invention to provide an integrated circuit having a specified high equivalent capacitance that is substantially unaffected by transistor current gain variations. 
   In accordance with the invention, an integrated circuit having high equivalent capacitance is provided. The effective capacitance is internal to the circuit, which includes simple active circuit elements. Advantageously, capacitance magnification provided by the circuit is high, specifiable, reliably fabricated, and substantially insensitive to transistor current gain variations. Moreover, capacitance magnification according to the invention is not limited by the physical sizes of the transistors in the integrated circuit. While the integrated circuit of the invention includes transistors for area ratio capacitance magnification, that magnification is amplified by additional transistors providing output current feedback. Furthermore, the capacitance magnification is buffered against the effects of transistor current gain variations. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects and advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which: 
       FIG. 1  is a simplified diagram of a known method of providing an integrated circuit with high capacitance; 
       FIG. 2  is a circuit diagram of a known capacitance multiplier circuit; 
       FIG. 3  is a circuit diagram of an embodiment of an integrated circuit having a high equivalent capacitance according to the invention; 
       FIG. 4  is a circuit diagram of an application of the circuit of  FIG. 3  according to the invention; 
       FIG. 5  is a circuit diagram of the application of  FIG. 4  showing an equivalent circuit for the circuit of  FIG. 3 ; and 
       FIG. 6  is a circuit diagram of another embodiment of an integrated circuit having a high equivalent capacitance according to the invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1  shows a known solution to providing high capacitance to an integrated circuit. Circuit  100  includes an integrated circuit (“IC”)  102  coupled to an external capacitor  104 . IC  102  can provide one or more dedicated or programmable functions. Capacitor  104  can have any appropriate value as required by IC  102  or the application of circuit  100 . A disadvantage of this circuit is that an input/output (“I/O”) pin in the package (e.g., a chip module) of IC  102  is needed to connect capacitor  104  to IC  102 . As is known, however, unused I/O pins can be rare in high density integrated circuit packages. Similarly, space for capacitor  104  on the card or board on which IC  102  is mounted also may not be available in view of the high component densities and compact sizes of electronic devices today. 
     FIG. 2  shows a known capacitance multiplier circuit  200 . Circuit  200  includes current sources  201  and  203 , capacitor  204 , NPN transistors  206  and  208 , and output node  210 . The physical size of the emitter of transistor  208  is N times as large as the size of the emitter of transistor  206 . Theoretically, the capacitance of capacitor  204  can be effectively multiplied N+1 times if transistor  208  has very high current gain (β). Looking into circuit  200  from output node  210 , the equivalent capacitance is
   C   EQ200 =(1 +A )· C   204   (1) 
where A is the incremental current gain dI 2 /dI 1  (dI 1  flows through capacitor  204 ). Currents I 1  and I 2  are bias currents that are needed only if C EQ200  sources current. To calculate A:
 V BE206 =V BE208   (2)   I   S208   =N·I   S206   (3) 
where V BE  is transistor base-to-emitter voltage and I S  is transistor saturation current.
 
                     vt   ·   ln     ⁢       I     C   ⁢           ⁢   206         I     S   ⁢           ⁢   206           =       vt   ·   ln     ⁢       I     C   ⁢           ⁢   208         I     S   ⁢           ⁢   208                   (   4   )                   I     C   ⁢           ⁢   206         I     C   ⁢           ⁢   206         =       I     C   ⁢           ⁢   208         I     S   ⁢           ⁢   208                 (   5   )               
where Vt is transistor thermal voltage (kT/q=26 millivolts at room temperature), ln is the natural logarithm, and I C  is collector current.
 
   
     
       
         
           
             
               
                 
                   
                     
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                       I     S   ⁢           ⁢   208         I     S   ⁢           ⁢   206         ⁢     I   1       =     1   +         I     S   ⁢           ⁢   208         I     S   ⁢           ⁢   206         ⁢     1   β     ⁢     I   2                 (   7   )               
where β is current gain. Taking the first derivative yields:
 
                     ⅆ     I   2         ⅆ     I   1         =         Is   208       Is   206         1   +         Is   208       Is   206       ⁢     1   β                   (   8   )                 N     1   +     N   β         =   A           (   9   )               
Accordingly, A approaches N only if β is much larger than N. As β becomes smaller, A becomes smaller. At β=N, A is equal to one-half N.
 
   Integrated circuit process variations and operating temperature ranges, however, can cause β to vary typically by 3×. Thus, assuming a β ranging from 50 to 150, the tolerance on the value of C EQ200  can be 30% due to β variation alone, limiting N to 21. Accordingly, high β sensitivity limits the capacitor multiplication factor A to very low values, typically 10 to 20. Even with a transistor  208  base current cancellation circuit (known in the art), the theoretical maximum multiplication factor is only N, and N is typically less than 40 because of transistor size limitations in integrated circuits. In other words, the maximum multiplication factor A cannot be greater than the transistor  208 / 206  size ratio N. 
     FIG. 3  shows an embodiment of a capacitance magnification circuit according to the invention. Circuit  300  provides a well controlled high internal equivalent capacitance that does not have high β sensitivity. Moreover, the capacitance magnification factor is not limited by the transistor physical size ratio N, as in known circuits. Circuit  300  preferably includes current sources  301  and  303 , capacitor  304 , NPN transistors  305 ,  306 ,  307 ,  308 , and  312 , output node  310 , and multi-collector PNP transistors  314  and  316 . Transistors  305  and  306  preferably have emitters of equal size (represented by “1×”), while transistor  307  has an emitter “D” times as large, and transistor  308  has an emitter “N” times as large, as the emitters of transistors  305  and  306 . As shown, a first collector of transistor  314  is preferably (N·k) times larger than the second collector of transistor  314 , and a first collector of transistor  316  is preferably twice as large as the second collector of transistor  316 . Currents I 1 , I 3 , and I 4  provide DC bias that enables circuit  300  to source and sink current. The base-to-emitter voltages (V BE ) of transistors  305  and  306  stack up to become the input voltage to transistor  307 . The V BE  of transistor  307  is constant. Output transistor  308  has a current gain in accordance with:
   V   BE305   +V   BE306   −V   BE307   =V   BE308   (10) 
Transistor  316  generates current I 4  from current I 3 . Looking into circuit  300  from output node  310 , output current is distributed into two paths, one including capacitor  304  and the other including the collector of transistor  308 . Any AC current I C1  flowing through capacitor  304  also flows through transistors  305  and  306 . This incremental current change dI 1  on DC bias current I 1  causes a change in the base-to-emitter voltages of transistors  305  and  306 . These V BE  changes cause I C4  to change (I C3  is constant) with an incremental current gain of:
 
                 A   =       ⅆ     I   4         ⅆ     I   1                 (   11   )               
where dI 4  is the incremental change on DC bias current I 4 . With current gain A, equivalent capacitance C EQ300  is:
   C   EQ300 =(1 +A )· C   304   (12) 
Advantageously, a magnification factor much larger than size ratio N is achieved by feeding back a current (shown as k·I 4  in  FIG. 3 ), which is a function of output current I 4 , from current mirror transistor  312  and turnaround transistor  314  to input transistor  306 . This regenerative process significantly amplifies gain factor A. C EQ300  can be determined by the following equations:
   V   BE305   +V   BE306   =V   BE307   +V   BE308   (13) 
                       vt   ·   ln     ⁢       I   1       I     S   ⁢           ⁢   305           +       vt   ·   ln     ⁢         I   1     +     k   ·     I   4           I     S   ⁢           ⁢   306             =         vt   ·   ln     ⁢       I   3       I     S   ⁢           ⁢   307           +       vt   ·   ln     ⁢       I   4       I     S   ⁢           ⁢   308                     (   14   )                 let   ⁢           ⁢   W     =         I     S   ⁢           ⁢   307       -     I     S   ⁢           ⁢   308             I     S   ⁢           ⁢   305       -     I     S   ⁢           ⁢   306                   (   15   )                   I   1     ⁡     (       I   1     +     k   ·     I   4         )       =       1   W     ⁢     (       I   3     ·     I   4       )               (   16   )               
Taking the first derivative yields:
 
                     2   ⁢       I   1     ·     dI   1         +     k   ·     I   4     ·     dI   1       +     k   ·     I   1     ·     dI   4         =         I   3     W     ⁢       dI   4     ⁢     
     (       I   3     ⁢           ⁢   is   ⁢           ⁢   a   ⁢           ⁢   constant     )               (   17   )                   ⅆ     I   4         ⅆ     I   1         =     A   =       2   ⁢       I   1     ·     +   k     ·     I   4               I   3     W     -     k   ·     I   1                     (   18   )               
where again V BE  is transistor base-to-emitter voltage, Vt is transistor thermal voltage, I C  is collector current, and I S  is saturation current. Currents I 1 , I 3 , and I 4  are DC bias currents that flow only if C EQ300  sources current.
 
   The following example illustrates the capacitance magnification effect of circuit  300 . Let capacitor  304 =5 pf, I 4 =20 μA, I 3 =10 μA, I 1 =0.75 μA, N=10, and D=5. To balance current density and satisfy equation (13), transistor  306  collector current is 5.33 μA, which results in feedback current k·I 4 =(5.33 μA−I 1 )=4.58 μA and k=4.58/20=0.229. From the given values and W=N·D=50, magnification factor A can be calculated from equation (18) as follows: 
                     ⅆ     I   4         ⅆ     I   1         =     A   =           2   ⁢     (   0.75   )       +   4.58         10   50     -       (   .229   )     ⁢     (   0.75   )           =   215               (   19   )               
The equivalent capacitance of circuit  300  can now be calculated as follows:
   C   EQ300 =(1+215)·5 pf=1080 pf  (20) 
Thus, with N equal to only 10 and circuit  300  including only a few more 1×-sized transistors than in known circuit  200 , magnification A for this example is about 10 to 20 times greater than that for known circuit  200 , where A is limited to the value of size ratio N. Moreover, magnification factor A can be increased further in accordance with equation (18).
 
   Note that the invention is not limited by or to the values used in the above example. Other component values based on, for example, transistor parameters of a specific process or a particular capacitance application can also be used in accordance with the invention. 
   The sensitivity of magnification factor A to the current gain of transistor  308  is reduced by an order of magnitude (and thus to a negligible level) because of the buffering effect of transistor  307  (recall that the V BE  of transistor  307  is constant). Thus, changes in output current I 4  have little to no effect on gain-setting transistors  305  and  306 . 
   Advantageously, variations in magnification factor A are caused primarily by only transistor size mismatching—which is uncommon in state of the art integrated circuit fabrication where transistor size matching can be done with a high degree of accuracy. 
     FIG. 4  shows a particularly useful application of circuit  300 . A transconductance amplifier  420  is coupled via a resistor  422  to capacitance output node  410 . The equivalent capacitance looking into output node  410  (shown representationally in  FIG. 5  as capacitor C EQ400 ) advantageously provides internal loop compensation for a feedback system including transconductance amplifier  420 . Internal compensation prevents oscillation in closed loop amplifier circuits. Circuit  400  also includes current sources  401  and  403 , capacitor  404 , NPN transistors  405 ,  406 ,  407 ,  408 , and  412 , output node  410 , and multi-collector PNP transistors  414  and  416 . In this embodiment, a first collector of transistor  414  is 2.3 times larger than the second collector of transistor  414 , as shown in  FIG. 4 . Transistors  405  and  406  have emitters of equal size, while transistor  407  has an emitter D times as large, and transistor  408  has an emitter N times as large, as the emitters of transistors  405  and  406 . Currents I 1 , I 3 , and I 4  provide DC bias. 
     FIG. 6  shows another embodiment of a capacitance magnification circuit according to the invention. Circuit  600  provides a well controlled high internal equivalent capacitance that does not have high β sensitivity. Moreover, the capacitance magnification factor is not limited by the transistor physical size ratio N. Circuit  600  includes current sources  601  and  603 , capacitor  604 , NPN transistors  605 ,  606 ,  607 ,  608 , and  612 , output node  610 , and multi-collector PNP transistors  614  and  616 . 
   Circuit  600  differs from circuit  300  in that the output current feedback path  615  from the larger collector of transistor  614  is coupled to the base and collector of transistor  605  instead of the base and collector of transistor  606  as in circuit  300 . The performance of circuit  600 , however, is substantially similar to that of circuit  300 . Equivalent capacitance C EQ600  is:
 
 C   EQ600 =(1 +A )· C   604   (21)
 
where A can be determined from:
 
 V   BE605   +V   BE606   =V   BE607   +V   BE608   (22)
 
                       Vt   ·   ln     ⁢         I   1     +     k   ·     I   4           Is   605         +       Vt   ·   ln     ⁢         I   1     +     k   ·     I   4           Is   606           =         Vt   ·   ln     ⁢       I   3       Is   607         +       Vt   ·   ln     ⁢       I   4       Is   608                   (   23   )                 let   ⁢           ⁢   W     =         Is   607     ·     Is   608           Is   605     ·     Is   606                 (   24   )                   (       I   1     +     k   ·     I   4         )     2     =       1   W     ⁢     (       I   3     ·     I   4       )               (   25   )                   I   1   2     +     2   ⁢     k   ·     I   1     ·     I   4         +       k   2     ·     I   4   2         =           ⁢       1   W     ⁢     (       I   3     ·     I   4       )               (   26   )               
Taking the first derivative yields:
 
   
     
       
         
           
             
               
                 
                   
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   Thus it is seen that integrated circuits having high internal equivalent capacitance are provided. One skilled in the art will appreciate that the invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the invention is limited only by the claims which follow.