Abstract:
A dual damascene process for low-k or ultra low-k dielectric such as organo-silicate glass (OSG). After the via ( 112 ) etch, a trench ( 121 ) is etched in the OSG layer ( 108 ) using a less-polymerizing fluorocarbon added to an etch chemistry comprising a fluorocarbon and low N 2 /Ar ratio. The low N 2 /Ar ratio controls ridge formation during the trench etch. The combination of a less-polymerizing fluorocarbon with a higher-polymerizing fluorocarbon achieves a high etch rate and defect-free conditions.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS: 
     This application claims priority under 35 USC §119(e)(1) of provisional application nos. 60/231,813 filed Sep. 11, 2000. 
     The following co-pending application is related and hereby incorporated by reference: U.S. patent application Ser. No. 09/521,325, filed Mar. 9, 2000 by Tsu et al. 
    
    
     FIELD OF THE INVENTION 
     The invention is generally related to the field of forming interconnect layers in integrated circuits and more specifically to dual damascene interconnect processes with Cu and low-k dielectrics. 
     BACKGROUND OF THE INVENTION 
     As the density of semiconductor devices increases, the demands on interconnect layers for connecting the semiconductor devices to each other also increase. Therefore, there is a desire to switch from the traditional aluminum metal interconnects to copper interconnects. Unfortunately, suitable copper etches for a semiconductor fabrication environment are not readily available. To overcome the copper etch problem, damascene processes have been developed. 
     In a conventional interconnect process, the aluminum (and any barrier metals) are deposited, patterned, and etched to form the interconnect lines. Then, an interlevel dielectric (ILD) is deposited and planarized. In a damascene process, the ILD is formed first. The ILD is then patterned and etched. The metal is then deposited over the structure and then chemically-mechanically polished to remove the metal from over the ILD, leaving metal interconnect lines. A metal etch is thereby avoided. 
     One prior art damascene process, a dual damascene process, is described with reference to FIGS. 1A-E. Referring to FIG. 1A, a silicon nitride layer  12  is deposited over a semiconductor body  10 . Semiconductor body  10  will have been processed through a first metal interconnect layer. A via level dielectric  14  is deposited over silicon nitride layer  12 . Via dielectric layer  14  comprises FSG (fluorine-doped silicate glass). Another silicon nitride layer  18  is deposited over via level dielectric  14  and a second, trench level dielectric  20  is deposited over silicon nitride layer  18 . A via  22  is then patterned and etched through the trench level dielectric  20 , silicon nitride layer  18  and via level dielectric  14 . Silicon nitride layer  12  is used as an etch-stop. 
     Referring to FIG. 1B, a spin-on organic barc (bottom anti-reflection coating)  24  is deposited to fill a portion of via  22 . The result is approximately 600 Å of barc over dielectric  20  and a thickness of ˜2000-2500 Å inside the via  22 . Barc  24  protects via  22  during the subsequent trench etch. Next, the trench pattern  26  is formed on the structure as shown in FIG.  1 C. Trench pattern  26  exposes areas of trench level dielectric  20  (with about 600 Å of barc on top of dielectric  20 ) where the metal interconnect lines are desired. Referring to FIG. 1D, the trench etch to remove portions of FSG layer  20  is performed. Oxide ridges  28  may undesirably form on the edges of via  22 . Pattern  26  is removed as shown in FIG.  1 E. Oxide ridges impair device reliability due to the fact that it is difficult to ensure that a metal barrier completely covers the oxide ridges. 
     Newer technologies are switching to even lower-k dielectrics such as organo-silicate glass (OSG) in place of FSG. Dual damascene processes for working with the newer dielectrics are needed. 
     SUMMARY OF THE INVENTION 
     A dual damascene process for low-k and ultra-low-k dielectrics is disclosed herein. After the via etch, a trench is etched using a less-polymerizing fluorocarbon added to an etch chemistry comprising a fluorocarbon and low N 2 /Ar ratio. The low N 2 /Ar ratio controls ridge formation during the trench etch. The combination of a less-polymerizing fluorocarbon with a high-polymerizing fluorocarbon achieves a high etch rate and defect-free conditions. 
     An advantage of the invention is providing a dual damascene process that avoids or minimizes the formation of via ridges while maintaining a high etch rate and good CD control. 
     This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings: 
     FIGS. 1A-1E are cross-sectional diagrams of a prior art dual damascene process at various stages of fabrication; 
     FIGS. 2A-2E are cross-sectional diagrams of a dual damascene process according to the invention at various stages of fabrication; 
     FIG. 3 is a cross-sectional drawing of a trench/via with oxide ridges; 
     FIG. 4 is a cross-section drawing of a trench/via without oxide ridges but with a low etch rate chemistry; 
     FIG. 5 is a cross-sectional diagram of a trench/via etched according to the invention with no oxide ridges and high etch rate when a less-polymerizing fluorocarbon was added to the trench etch chemistry. 
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     The invention will now be described in conjunction with a dual damascene copper interconnect process. It will be apparent to those of ordinary skill in the art that the benefits of the invention can be applied to other fabrication processes such as other dual damascene processes. 
     A fabrication process according to an embodiment of the invention will now be discussed with reference to FIGS. 2A-2E. A semiconductor body  100  is processed through the formation of a first interconnect layer  102  as is known in the art. (Although referred to herein as the first interconnect layer  102 , layer  102  may be any interconnect layer except the uppermost interconnect layer.) An etch-stop layer  104  is deposited over the first interconnect layer  102 . Etch-stop layer  104  typically comprises silicon nitride, but other suitable etch-stop layers are known in the art (e.g., SiC). As an example, the thickness of etch-stop layer  104  may be on the order of 1000 Å (e.g.,  500 Å-1000 Å).    
     The via level dielectric  106  (sometimes referred to as interlevel dielectric-ILD) and trench level dielectric  108  (sometimes referred to as intrametal dielectric-IMD) are formed over etch-stop layer  104 . As shown in FIG. 2A, ILD  106  and IMD  108  can be a single layer. In the preferred embodiment, OSG is the material used for ILD  106  and IMD  108 . OSG is a low-k material having a dielectric constant in the range of 2.7-3.0. Alternatively, ILD  106  and IMD  108  may comprise a low-k (&lt;3.5) or an ultra-low-k (&lt;2.7) dielectric. The combined thickness of ILD  106  and IMD  108  may be approximately 9000 Å. 
     An etch-stop layer is not necessary between ILD  106  and IMD  108 . However, one could be included if desired. Eliminating the etch-stop layer between the ILD  106  and IMD  108  has the advantage of reducing parasitic capacitance. 
     Sometimes a capping layer  110  is formed over IMD  108 . As an example, oxide capping layer may be deposited using a plasma enhanced tetraethyoxysilane (PETEOS) process. In the preferred embodiment, the thickness of oxide capping layer is approximately 1500 Å. Silicon nitride could also be used as a capping layer. It should be noted that a barc layer is often used under the resist for both via and trench pattern. In the preferred embodiment, no hardmask is used. 
     Referring to FIG. 2A, vias  112  are etched through the barc and the capping layer  110  (if present), IMD  108 , and ILD  106 . The via etch-stops on etch-stop layer  104 . Vias  112  are formed in areas where connection is desired between two metal interconnect layers. If an additional etch-stop layer was included between IMD  108  and ILD  106 , the via etch also etches through this additional etch-stop layer. In the preferred embodiment, the via etch chemistry comprises C 5 F 8 , N 2  and CO. 
     Referring to FIG. 2B, a spin-on barc  114  is coated to fill a portion of via  112 . The result is approximately  850 A of barc over capping layer  110  and a thickness of ˜4500 Å-7000 Å inside the via  112  (the barc thickness inside the via depends on the via density.). Barc  114  protects the bottom of via  112  during the subsequent trench etch. 
     Still referring to FIG. 2B, the trench pattern  120  is formed. Trench pattern  120  exposes the areas where metal interconnect lines of a second or subsequent metal interconnect layer are desired. 
     Next, the trench  121  etch is performed to etch IMD  108  as shown in FIG.  2 C. In the preferred embodiment, a timed etch is used. If, however, an additional trench etch-stop layer is formed, between ILD  106  and IMD  108 , an endpoint etch could be used. It should be noted however, that the incorporation of a silicon-nitride etch-stop layer increases the parasitic capacitance between metal interconnect layers. 
     The trench etch comprises an etch chemistry of a less-polymerizing fluorocarbon with a more-polymerizing fluorocarbon, nitrogen and argon. A low N 2 /Ar ratio (&lt;1:3) is used. A less-polymerizing fluorocarbon refers to a C:F ratio of less than 1:3. Examples of less-polymerizing fluorocarbons include CF 4 , NF 3 , C 2 F 6 , and C X F 3X+y  (Y&gt;=0). Examples of more-polymerizing fluorocarbons include C 4 F 8 , C 5 F 8 , C 4 F 6 , C X H Y F 2X+Z  (Z&gt;=0, Y&gt;=0). 
     The etch chemistry for the trench etch is critical. One proposed etch for etching OSG is C 4 F 8 /N 2 /Ar. C 4 F 8  is a higher-polymerizing fluorocarbon. A high N 2 /Ar ratio results in high etch rate. However, when a high N 2 /Ar ratio is used, oxide ridges  130  form around the vias, as shown in FIG. 3. 10 sccm of C 4 F 8  and a N 2 /Ar ratio of 300:100 results in an etch rate of approximately 4600 Å/min. Oxide ridges  130  remain even after clean-up and significantly impact reliability. When the subsequently deposited metal barriers are formed, it is difficult to ensure that oxide ridges  130  are completely covered. In addition, oxide ridges may fall into the vias during subsequent processes (e.g., pre-sputter etch), resulting in poor metal barrier coverage. 
     A low N 2 /Ar ratio eliminates the oxide ridges as shown in FIG.  4 . Unfortunately, the etch rate also reduces significantly. When 10 sccm of C 4 F 8  is used with a N 2 /Ar ratio of 50:450, the etch rate reduces to approximately 1350 Å/min. The low etch rate reduces throughput. 
     The etch chemistry according to the invention, combines a less-polymerizing fluorocarbon, such as CF 4  with a higher-polymerizing fluorocarbon, such as C 4 F 8 , and low N 2 /Ar ratio. The low N 2 /Ar ratio eliminates the oxide ridges, as shown in FIG.  5 . The combined fluorocarbons improve etch rate without increasing oxide ridges or increasing CD bias. A 10 sccm C 4 F 8 , N 2 :Ar=100:400 and 30 sccm CF 4  etch chemistry results in no oxide ridges, an etch rate of approximately 3480 Å/min and a CD bias of approximately  0.003 μm.    
     Because CF 4  is a less-polymerizing fluorocarbon, adding it to the etch chemistry increases the etch rate significantly. However, it does not increase the CD bias or cause the formation of ridges. Thus, the etch rate and ridge formation can be controlled independently. Furthermore, by adjusting the flow rates of the two fluorocarbons, various C:F ratios can be achieved. This is not possible with a single fluorocarbon. 
     Referring to FIG. 2D, the resist and barc from trench pattern  120  is removed, for example, by ashing. (If the capping layer is thin (e.g., &lt;500 Å), it can be removed during etch-stop layer etch. However, if the capping layer is &gt;500 Å, it is removed during metal CMP.) 
     Processing then continues with the formation of the second metal interconnect layer  122 , as shown in FIG.  2 E. (Although referred to as the second metal interconnect layer, layer  122  can be any metal interconnect layer other than the lowest interconnect layer.) Typically, a barrier layer  124 , such as tantalum-nitride (TaN) is deposited first. Due to the fact that no oxide pillars are formed, it is fairly easy to form a continuous barrier layer  124  in the trench/via. This advantage also increases the process margin. A purpose of the barrier layer is to prevent diffusion of the subsequently formed metal into the IMD/ILD. Breaks in the barrier layer allow metal diffusion and thus reduce yield and reliability. The invention thus improves both the yield and reliability by preventing the formation of oxide ridges and reducing defects in the via. It also improves trench etch throughput. 
     After the barrier layer  124 , a copper seed layer is typically formed. This is followed by the formation of the copper interconnect  126  and a top nitride (Si 3 N 4 ) capping layer  128 . The above process can then be repeated to form subsequent metal interconnect layers. 
     While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.