Abstract:
Disclosed is a ferroelectric random access memory including a plurality of bit lines extending in one direction, a plurality of plate electrode lines extending in another direction perpendicular to the one direction, a plurality of word lines extending in the same direction as the plate electrode lines, and a plurality of unit cells arranged in an M×N array. The unit cells are grouped into a plurality of unit cell groups, each unit cell group consists of a plurality of unit cells connected to associated bit lines such that the unit cells are interlaced in a row direction or in a column direction. A dummy cell group consists of a plurality of dummy cells each connected to an associated one of the bit lines at an optional position on the associated bit line. A switching transistor group consists of a plurality of switching transistors each serving to switch a connection between associated ones of the unit cells on an associated one of the bit lines, and to switch an input-to-input/output-to-output coupling between two associated dummy cells, in response to a control signal externally applied. When data is read from an optional one of the unit cells on a selected one of the bit lines, an average voltage between voltages respectively outputted from those of the dummy cells connected to two bit lines neighboring to the selected bit line is applied to the neighboring bit lines as a reference voltage required for a comparison with a voltage corresponding to the read-out data.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application claims the priority of Korean patent application Ser. No. 99-42044 filed on Sep. 30, 1999. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a ferroelectric memory device, and more particularly to a ferroelectric random access memory device fabricated using a ferroelectric material having a perovskite structure to obtain an enhanced reliability when data is read out. 
     2. Description of the Related Art 
     As well known, semiconductor memory devices are classified into volatile memory devices and non-volatile memory devices in accordance with whether or not information is lost when power is off. A dynamic random access memory (DRAM), which is a volatile memory, is configured to keep information only in a power-on state even though it has a high operating speed. Such a DRAM also has a drawback in that the consumption of power is excessive because refreshing of data should be carried out at intervals of a certain time in order to prevent data from being lost due to leakage current from a charge transfer transistor coupled to a capacitor. Meanwhile, EEPROMs and flash memories, which are non-volatile memories, have drawbacks of a low operating speed and an excessive power consumption even though data can kept in a power-off state. 
     On the other hand, a ferroelectric random access memory (FeRAM) has advantages in that they have an operating speed similar to that of DRAMs while exhibiting a reduced power consumption. Such an FeRAM is a non-volatile memory capable of keeping data even in a power-off state, like EEPROMs and flash memories. By virtue of these advantages, such an FeRAM has recently been recognized as a substitutive memory for DRAMs, EEPROMs, flash memories, and other semiconductor memories. In accordance with such a recognition, active research and development have been made for FeRAMs in many companies and research institutes in the world. 
     Such an FeRAM uses a capacitor made of a ferroelectric film, such as PZT(Pb(Zr,Ti)O 3  or SBT(SrBi 2 Ta 2 O 9 ), having spontaneous polarization characteristics capable of maintaining a polarization generated in accordance with an application of a certain voltage, even after power is off. Such an FeRAM utilizes the hysteretic characteristic of a ferroelectric depicted in FIG.  1 . 
     Referring to FIG. 1, the ferroelectric is polarized when a voltage V applied to the ferroelectric is increased in a plus (+) direction, so that it exhibits a maximum polarized value Qmax at a maximum voltage. When the applied voltage is cut off, the residual polarization of the ferroelectric corresponds to “Qr”. This residual polarization value Qr corresponds to data “1”. When the voltage V is decreased in a minus (−) direction, the ferroelectric is polarized in an opposite direction, so that it exhibits a minimum polarized value Qmin at a minimum voltage. When the applied voltage is cut off in this state, the residual polarization of the ferroelectric corresponds to “−Qr”. This residual polarization value −Qr corresponds to data “0”. 
     Here, the “+” and “−” directions of the voltage V are indicative of different relative potential relations between the upper and lower electrodes of the capacitor, respectively. The “+”, direction means that the upper electrode has a potential relatively higher than that of the lower electrode. The “−” direction means that the upper electrode has a potential relatively lower than that of the lower electrode. 
     This will be described in more detail, in conjunction with FIG. 5 which is a circuit diagram illustrating the equivalent circuit of a conventional FeRAM. In order to store data “1” in a capacitor of a unit cell UC in the circuit of FIG. 5, a potential, which is higher than that applied to a plate electrode, is applied to a bit line in an ON state of a charge transfer transistor, thereby causing a ferroelectric to be spontaneously polarized. After the spontaneous polarization of the ferroelectric, the charge transfer transistor is turned off, so that data “1” is stored. On the other hand, data “0” is stored by applying, to the bit line, a potential lower than the potential applied to the plate electrode in the ON state of the charge transfer transistor, thereby spontaneously polarizing the ferroelectric, and then turning off the charge transfer transistor. 
     When data stored in the capacitor is to be read out from the memory, the charge transfer transistor is turned off in a state in which a potential higher than that applied to the plate electrode is applied to the bit line. As a result, a charge dQ 1  is discharged into the bit line when the data stored in the capacitor is “1”. When the data stored in the capacitor is “0”, a charge dQ 0  is discharged into the bit line. That is, the potential of the bit line varies in accordance with the value of the data stored in the capacitor because the charge discharged into the bit line varies in accordance with the value of the stored data. 
     When the data stored in the capacitor is “1”, the potential variation V 1  of the bit line corresponds to “dQ 1 /(Cb+Cs)” (V 1 =dQ 1 /(Cb+Cs)). On the other hand, the data stored in the capacitor is “0”, the potential variation V 0  of the bit line corresponds to “dQ 0 /(Cb+Cs)” (V 0 =dQ 0 /(Cb+Cs)). Therefore, it is possible to determine the data (“1” or “0”) by comparing the potential of the bit line, outputted at an output terminal (not shown) of the memory, with a reference potential. 
     The conventional FeRAM shown in FIG. 5 consists of unit cells UC each having a 1T/1C structure including one transistor and one capacitor. 
     Referring to FIG. 5, the FeRAM includes M×N unit cells. Each unit cell UC consists of one transistor (a charge transfer transistor), and one capacitor. The transistor of each unit cell UC is coupled at a gate thereof to an associated one of word lines WL 0 , WL 1 , and WL 2 , at a drain (or a source) thereof to an associated one of bit lines BL 0  and BL 1 , and at a source (a drain) thereof to one end of the capacitor included in the unit cell DC. The other end of the capacitor is connected to an associated one of plate electrode lines PL 0 , PL 1 , and PL 2 . Each bit line BL 0  or BL 1  is coupled at one end thereof to an associated one of comparators C 0  and C 1 . 
     The above mentioned conventional FeRAM also includes a reference voltage generating circuit. This reference voltage generating circuit includes two switching transistors ST 0  and ST 1 , and two dummy cells DC 0  and DC 1 . Each of the dummy cells DC 0  and DC 1  consists of one transistor (a charge transfer transistor), and one capacitor. Respective transistors of the dummy cells DC 0  and DC 1  are coupled at their drains (or sources) to dummy bit lines DBL and /DBL, and coupled to each other via switching transistors ST 0  and ST 1  respectively connected to the dummy bit lines DBL and /DBL, thereby forming a common output. The common output from the switching transistors ST 0  and ST 1  is coupled to the other input of each of the comparators C 0  and C 1 . 
     That is, each of the comparators C 0  and C 1  is coupled at one input thereof to an associated one of the bit lines BL 0  and BL 1 , and at the other input thereof to the common output of the dummy bit lines DBL and /DBL. Accordingly, each comparator C 0  or C 1  determines data (“0” or “1”) outputted from an optional unit cell UC by comparing the voltage of the unit cell UC, applied thereto via the associated bit line, with a reference voltage applied thereto from the common output of the switching transistors ST 0  and ST 1 . 
     Although the conventional FeRAM having the 1T/1C structure has an advantage in terms of a high integration in that it has a small unit cell size, there is a problem in that there may be a RC delay and a drop of the reference voltage because the data determination is carried out by comparing the potential of each bit line with the reference voltage transmitted from the reference voltage generating circuit via an interconnection line having a length different from that of the bit line. Such a problem is a main factor causing errors in the determination of output data. 
     FIG. 6 is an equivalent circuit diagram illustrating a part of a conventional FeRAM having a 2T/2C structure consisting of two transistors and two capacitors. 
     The FeRAM shown in FIG. 6 configures each unit cell UC by two transistors (charge transfer transistors) and two capacitors in such a fashion that a reference voltage to be compared with the potential of a bit line adjacent to the unit cell UC is generated from the unit cell UC, as compared to the FeRAM of FIG. 5 including a separate reference voltage generating circuit. 
     Since each unit cell UC generates a reference voltage to be compared with the potential of a bit line adjacent thereto, the FeRAM having the 2T/2C structure can eliminate the problems involved in the FeRAM having the 1T/1C structure, that is, an RC delayer and a drop of the reference voltage. 
     However, the FeRAM having the 2T/2C structure has an increased unit cell size because two charge transfer transistors are formed for each unit cell. As a result, this FeRAM has a fatal problem in that it is impossible to achieve a high integration. 
     SUMMARY OF THE INVENTION 
     A first object of the invention is to provide an FeRAM capable of enhancing the reliability in the determination of data read out, and easily achieving a high integration. 
     A second object of the invention is to provide an FeRAM capable of achieving a reliable data determination and a high integration while obtaining an increase in capacitance. 
     In accordance with one aspect, the present invention provides a ferroelectric random access memory comprising a plurality of bit lines extending in one direction, a plurality of plate electrode lines extending in another direction perpendicular to the one direction, a plurality of word lines extending in the same direction as the plate electrode lines, and a plurality of unit cells arranged in an M×N array while being connected to associated ones of the lines, each of the unit cells consisting of one transistor and one capacitor, wherein the unit cells are grouped into a plurality of unit cell groups, each of the unit cell groups consisting of a plurality of unit cells connected to associated ones of the bit lines, respectively, in such a fashion that they are arranged in an interlaced fashion in a row direction or in a column direction, those of the bit lines connected to each of the bit lines being connected together in series; further comprising: a dummy cell group consisting of a plurality of dummy cells each connected to an associated one of the bit lines at an optional position on the associated bit line, each of the dummy cells consisting of one transistor and one capacitor; and a switching transistor group consisting of a plurality of switching transistors each serving to switch a connection between associated ones of the unit cells on an associated one of the bit lines, and to switch an input-to-input/output-to-output coupling between two associated ones of the dummy cells, in response to a control signal externally applied thereto; whereby when data is read out from an optional one of the unit cells on a selected one of the bit lines, an average voltage between voltages respectively outputted from those of the dummy cells connected to two bit lines neighboring to the selected bit line is applied to the neighboring bit lines as a reference voltage required for a comparison with a voltage corresponding to the read-out data. 
     In accordance with another aspect, the present invention provides a ferroelectric random access memory comprising a plurality of bit lines extending in one direction, a plurality of word lines in another direction perpendicular to the one direction, and a plurality of unit cells arranged in an M×N array while being connected to associated ones of the lines, each of the unit cells consisting of one transistor and one capacitor, wherein the unit cells are grouped into a plurality of unit cell groups, each of the unit cell groups consisting of a plurality of unit cells connected to associated ones of the bit lines, respectively, in such a fashion that they are arranged in an interlaced fashion in a row direction or in a column direction, those of the bit lines connected to each of the bit lines being connected together in series; further comprising: a dummy cell group consisting of a plurality of dummy cells each connected to an associated one of the bit lines at an optional position on the associated bit line, each of the dummy cells consisting of one transistor and one capacitor; a switching transistor group consisting of a plurality of switching transistors each serving to switch a connection between associated ones of the unit cells on an associated one of the bit lines, and to switch an input-to-input/output-to-output coupling between two associated ones of the dummy cells, in response to a control signal externally applied thereto; a common plate electrode line, to which respective plate electrodes of the unit cells and respective plate electrodes of the dummy cells are connected in common, the common plate electrode line being applied with a predetermined voltage; whereby when data is read out from an optional one of the unit cells on a selected one of the bit lines, an average voltage between voltages respectively outputted from those of the dummy cells connected to two bit lines neighboring to the selected bit line is applied to the neighboring bit lines as a reference voltage required for a comparison with a voltage corresponding to the read-out data. 
     In accordance with another aspect, the present invention provides a ferroelectric random access memory comprising a plurality of bit lines extending in one direction, a plurality of word lines in another direction perpendicular to the one direction, and a plurality of unit cells arranged in an M×N array while being connected to associated ones of the lines, each of the unit cells consisting of one transistor and one capacitor, wherein the unit cells are grouped into a plurality of unit cell groups, each of the unit cell groups consisting of a plurality of unit cells connected to associated ones of the bit lines, respectively, in such a fashion that they are arranged in an interlaced fashion in a row direction or in a column direction, those of the bit lines connected to each of the bit lines being connected together in series; further comprising: a dummy cell group consisting of a plurality of dummy cells each connected to an associated one of the bit lines at an optional position on the associated bit line, each of the dummy cell consisting of one transistor and one capacitor; a switching transistor group consisting of a plurality of switching transistors each serving to switch an input-to-input/output-to-output coupling between respective dummy cells connected to two of the bit lines neighboring to each other in an interlaced fashion, the switching transistor applying an output thereof to a selected one of the two neighboring bit lines in response to a control signal externally applied thereto; a common plate electrode line, to which respective plate electrodes of the unit cells and respective plate electrodes of the dummy cells are connected in common, the common plate electrode line being applied with a predetermined voltage; whereby when data is read out from an optional one of the unit cells on a selected one of the bit lines, an average voltage between voltages respectively outputted from those of the dummy cells connected to two bit lines neighboring to the selected bit line is applied to the neighboring bit lines as a reference voltage required for a comparison with a voltage corresponding to the read-out data. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above objects, and other features and advantages of the present invention will become more apparent after a reading of the following detailed description when taken in conjunction with the drawings, in which: 
     FIG. 1 is a hysteretic characteristic diagram illustrating polarization characteristics of a ferroelectric film; 
     FIG. 2 a  is an equivalent circuit diagram illustrating a part of an FeRAM in accordance with a first embodiment of the present invention; 
     FIG. 2 b  is an equivalent circuit diagram illustrating a part of an FeRAM according to a first modified embodiment from the first embodiment of the present invention; 
     FIG. 2 c  is an equivalent circuit diagram illustrating a part of an FeRAM according to a second modified embodiment from the first embodiment of the present invention; 
     FIG. 3 a  is an equivalent circuit diagram illustrating a part of an FeRAM in accordance with a second embodiment of the present invention; 
     FIG. 3 b  is an equivalent circuit diagram illustrating a part of an FeRAM according to a first modified embodiment from the second embodiment of the present invention; 
     FIG. 3 c  is an equivalent circuit diagram illustrating a part of an FeRAM according to a second modified embodiment from the second embodiment of the present invention; 
     FIG. 3 d  is an equivalent circuit diagram illustrating a part of an FeRAM according to a second modified embodiment from the third embodiment of the present invention; 
     FIG. 4 a  is an equivalent circuit diagram illustrating a part of an FeRAM in according with a third embodiment of the present invention. 
     FIG. 4 b  is an equivalent circuit diagram illustrating a part of an FeRAM according to a second modified embodiment from the second embodiment of the present invention; 
     FIG. 5 is a circuit diagram illustrating the equivalent circuit of a Conventional FeRAM having a 1T/1C structure; and 
     FIG. 6 is a circuit diagram illustrating the equivalent circuit of Another conventional FeRAM having a 2T/2C structure. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The important technical idea of the present invention is to provide an FeRAM according to this embodiment, which consists of M×N unit cells, each unit cell having a 1T/1C structure consisting of one transistor and one capacitor. In order to generate a reference voltage for a determination of data read out on a bit line in this FeRAM, dummy cells are used, which are respectively connected to bit lines neighboring to that bit line while having a potential inverse to the potential of the bit line. In accordance with such technical means, data read out from an optional unit cell is determined by comparing a voltage outputted from a bit line, on which the data from that unit cell is read out, with a reference voltage outputted from bit lines neighboring to that bit line while having a potential inverse to the potential of the bit line. Accordingly, it is possible to greatly enhance the reliability in the determination of data read out from the unit cells of the memory while achieving a high integration of the memory. Thus, the first object of the present invention can be easily accomplished by virtue of the above mentioned technical means. 
     Alternatively, another technical means may be used, in which a single plate electrode is used in common for memory cells, in place of plate electrode lines separated from one another in a row or column direction. By virtue of such technical means, the second object of the present invention to achieve an increase in capacitance within a given area can be accomplished. 
     Alternatively, the FeRAM may use a configuration in which dummy data is stored and read out only using switching transistors each adapted to two bit lines neighboring to each other in an interlaced fashion. In this case, it is possible to more simplify the memory arrangement. 
     Now, preferred embodiments of the present invention will be described in detail, in conjunction with the annexed drawings. 
     [First Embodiment] 
     FIG. 2 a  is an equivalent circuit diagram illustrating a part of an FeRAM in accordance with a first embodiment of the present invention. 
     Referring to FIG. 2 a , the FeRAM according to this embodiment includes M×N unit cells arranged in rows and columns in an interlaced fashion, like the black or white pattern of a chess plate. A plurality of unit cells arranged in the same row are connected together in series by one of bit lines arranged in pair. The bit lines of each bit line pair operate alternatingly in such a fashion that when data is read out on one bit line, the other bit line serves as an inverted bit line providing a reference voltage. 
     The FeRAM according to this embodiment extends in a row direction in such a fashion that a plurality of unit cells are arranged in an M×N matrix array in which a plurality of word lines WL 0  to WL 3  and a plurality of plate electrode lines PL 0  to PL 3  each connected to a plurality of unit cells arranged in the same column cross a plurality of bit lines arranged in pair. Each bit line pair consists of one bit line and one inverted bit line. In FIG. 2 a , “BL 0 ” and “/BL 0 ” denote the bit lines of one bit line pair, and “BL 1 ” and “/BL 1 ” denote the bit lines of another bit line pair. 
     In the FeRAM according to this embodiment, each unit cell denoted by the reference character UC has a 1T/1C structure consisting of one transistor (a charge transfer transistor) and one capacitor. A dummy cell DC 0 , DC 0 ′, DC 1 , or DC 1 ′, which consists of one transistor (a charge transfer transistor) and one capacitor, is coupled to an associated one of the bit lines BL 0 , BL 0 ′, BL 1 , and BL 1 ′ at one side of the associated bit line (the right side of FIG. 2 a ). 
     The transistor of each unit cell UC is coupled at a gate thereof to an associated one of the word lines WL 0 , WL 1 , WL 2 , and WL 3 , at a drain (or a source) thereof to an associated one of the bit lines (inverted bit lines) BL 0 , BL 0 ′, BL 1 , and BL 1 ′, and at a source (a drain) thereof to one end of the capacitor included in the unit cell UC. The other end of the capacitor is connected to an associated one of plate electrode lines PL 0 , PL 1 , PL 2 , and PL 3 . 
     The transistors of the dummy cells DC 0 , DC 0 ′, DC 1 , and DC 1 ′ are coupled in common at their gates to a dummy word line DWL, and coupled at their drains (or sources) to the bit lines (or inverted bit lines) BL 0 , BL 0 ′, BL 1 , and BL 1 ′, respectively. The transistor of each dummy cell DC 0 , DC 0 ′, DC 1 , or DC 1 ′ is also coupled at its source (or its drain) to one end of the capacitor included in the dummy cell. The other end of the capacitor is connected to a dummy plate electrode lines DPL 0  or DPL 1 . In the illustrated case, respective capacitors of the dummy cells DC 0 ′ and DC 1  connected to the bit lines /BL 0  and BL 1  are connected to the dummy plate electrode DPL 0  whereas respective capacitors of the dummy cells DC 0  and DC 1 ′ connected to the bit lines /BL 0  and BL 1  are connected to the dummy plate electrode DPL 1 . 
     A switching transistor is arranged on each bit line between the portion of the bit line, to which unit cells are coupled, and the portion of the bit line, to which an associated one of the dummy cells are coupled. In the illustrated case, a switching transistor ST 0  is arranged on the bit line /BL 0  between the portion of the bit line /BL 0 , to which the unit cells C 10 ′ and C 30 ′ are coupled, and the portion of the bit line /BL 0 , to which the dummy cell DC 0 ′ is coupled. A switching transistor ST 1  is arranged on the bit line /BL 1  between the portion of the bit line /BL 1 , to which the unit cells C 11 ′ and C 31 ′ are coupled, and the portion of the bit line /BL 1 , to which the dummy cell DC 1 ′ is coupled. A switching transistor ST 2  is arranged on the bit line BL 0  between the portion of the bit line BL 0 , to which the unit cells C 00  and C 20  are coupled, and the portion of the bit line BL 0 , to which the dummy cell DC 0  is coupled. A switching transistor ST 3  is arranged on the bit line BL 1  between the portion of the bit line BL 1 , to which the unit cells C 01  and C 21  are coupled, and the portion of the bit line BL 1 , to which the dummy cell DC 1  is coupled. A switching transistor is also coupled between neighboring bit lines or neighboring inverted bit lines. In the illustrated case, a switching transistor ST 4  is coupled at its source and drain to the bit lines /BL 0  and /BL 1 , respectively. A switching transistor ST 5  is coupled at its drain and source to the bit lines BL 0  and BL 1 , respectively. 
     The switching transistors ST 0  and ST 1  are coupled in common at their gates to a control line CL 0 . The switching transistors ST 2  and ST 3  are coupled in common at their gates to a control line CL 1 . The switching transistor ST 4  is coupled at its gate to a control line CL 2 . The switching transistor ST 5  is coupled at its gate to a control line CL 3 . When data is to be stored or read out, a switching control signal from an external unit is applied to respective gates of the switching transistors ST 0  to ST 5 . 
     As apparent from the above description, in the FeRAM according to this embodiment, each unit cell has a 1T/1C structure consisting of one transistor and one capacitor. In order to generate a reference voltage for a determination of data read out on a bit line in this FeRAM, dummy cells are used, which are respectively connected to bit lines neighboring to that bit line while having a potential inverse to the potential of the bit line. In accordance with this configuration, data read out from an optional unit cell is determined by applying, to a comparator C 0  or C 1 , a voltage outputted from a bit line, on which the data from that unit cell is read out, along with a reference voltage outputted from bit lines neighboring to that bit line while having a potential inverse to the potential of the bit line, thereby comparing the applied voltages. 
     The procedures for storing data in the FeRAM having the above mentioned configuration according to this embodiment and reading out the stored data will be described in detail. 
     For the convenience and best understanding of description, it is assumed in the following description that a high voltage corresponds to “Vcc”, a low voltage corresponds to 0 V, the potential variation of a bit line when output data is “1” corresponds to “V 1 ”, and the potential variation of the bit line when output data is “0” corresponds to “V 0 ”. Since the same data storing and reading procedures are carried out in all unit cells, these procedures will be described only in conjunction with one unit cell, for example, the unit cell C 00 . 
     First, the procedure for storing data “1” in the unit cell C 00  will be described. In order to store data, the word line WL 0 , dummy word line OWL, and two control lines CL 0  and CL 1  are switched to their ON states, respectively. In this state, “Vcc” is applied to the bit line BL 0  and the bit line BL 1  associated the unit cell C 01  neighboring to the unit cell C 00  whereas “0 V” is applied to the bit line /BL 0  and the bit line BL 1 . “0 V” is also applied to the plate electrode line PL 0  and the dummy plate electrode line DPL 1 . “Vcc” is also applied to the dummy plate electrode line DPL 0 . Due to a potential difference resulting from such a voltage application, the ferroelectric film included in the unit cell C 00  is polarized in a plus (+) direction. Accordingly, data “1” is stored. 
     As a result, data “1, 0, 0, 1” are stored in respective dummy cells DC 0 , DC 0 ′, DC 1 , and DC 1 ′ connected to the bit lines BL 0 , /BL 0 , BL 1 , and /BL 1  in accordance with voltages applied thereto. When data is to be read out from an optional unit cell, the data stored in an associated one of the dummy cells DC 0 , DC 0 ′, DC 1 , and DC 1 ′ is used to generate a reference voltage required for a comparison with the voltage on the associated bit line. 
     That is, the reference voltage required for a comparison with the voltage on the bit line BL 0  corresponds to an average voltage between the dummy cells DC 0 ′ and DC 1 ′. The reference voltage required for a comparison with the voltage on the bit line /BL 0  corresponds to an average voltage between the dummy cells DC 0  and DC 1 . The reference voltage required for a comparison with the voltage on the bit line BL 1  corresponds to an average voltage between the dummy cells DC 0 ′ and DC 1 ′. The reference voltage required for a comparison with the voltage on the bit line /BL 1  corresponds to an average voltage between the dummy cells DC 0  and DC 1 . 
     Alternatively, the storing of data “1” in the unit cell C 00  may be carried out in a fashion different from the above mentioned procedure. That is, in order to store data, the word line WL 0 , dummy word line DWL, and two control lines CL 0  and CL 1  are switched to their ON states, respectively. In this state, “Vcc” is applied to the bit line BL 0  and /BL 0  whereas “0 V” is applied to the bit lines BL 1  and /BL 1 . “0 V” is also applied to the plate electrode line PL 0  and the dummy plate electrode line DPL 0 . “Vcc” in also applied to the dummy plate electrode line DPL 1 . Due to a potential difference resulting from such a voltage application, the ferroelectric film included in the unit cell C 00  is polarized in a plus (+) direction. Accordingly, data “1” is stored. 
     As a result, data “1, 0” are stored in respective dummy cells DC 0 ′ and DC 1 ′ connected to the bit lines /BL 0  and /BL 1  in accordance with voltages applied thereto, as compared to the above mentioned procedure. When data is to be read out from an optional unit cell, the data stored in an associated one of the dummy cells DC 0 ′ and DC 1 ′ is used to generate a reference voltage required for a comparison with the voltage on the associated bit line. 
     Now, the procedure for storing data “0” in the unit cell C 00  will be described. In order to store data, the word line WL 0 , dummy word line DWL, and two control lines CL 0  and CL 1  are switched to their ON states, respectively. In this state, “0 V” is applied to the bit lines BL 0  and /BL 1  whereas “Vcc” is applied to the bit lines /BL 0  and BL 1 . “Vcc” is also applied to the plate electrode line PL 0  and the dummy plate electrode line DPL 1 . “0 V” is also applied to the dummy plate electrode line DPL 0 . Due to a potential difference resulting from such a voltage application, the ferroelectric film included in the unit cell C 00  is polarized in a minus (−) direction. Accordingly, data “0” is stored. 
     As a result, data “0, 1, 1, 0” are stored in respective dummy cells DC 0 , DC 0 ′, DC 1 , and DC 1 ′ connected to the bit lines BL 0 , /BL 0 , BL 1 , and /BL 1  in accordance with voltages applied thereto. When data is to be read out from an optional unit cell, the data stored in an associated one of the dummy cells DC 0 , DC 1 ′, DC 1 , and DC 1 ′ is used to generate a reference voltage required for a comparison with the voltage on the associated bit line, as in the above mentioned case associated with data “1”. 
     Alternatively, the storing of data “0” in the unit cell C 00  may be carried out in a fashion different from the above mentioned procedure. That is, in order to store data, the word line WL 0 , dummy word line DWL, and two control lines CL 0  and CL 1  are switched to their ON states, respectively. In this state, “0 V” is applied to the bit line BL 0  and /BL 0  whereas “Vcc” is applied to the bit line BL 1  and /BL 1 . “Vcc” is also applied to the plate electrode line PL 0  and the dummy plate electrode line DPL 0 . “0 V” is also applied to the dummy plate electrode line DPL 1 . Due to a potential difference resulting from such a voltage application, the ferroelectric film included in the unit cell C 00  is polarized in a minus (−) direction. Accordingly, data “0” is stored. 
     As a result, data “0, 1” are stored in respective dummy cells DC 0 ′ and DC 1 ′ connected to the bit lines /BL 0  and /BL 1  in accordance with voltages applied thereto, as compared to the above mentioned procedure. When data is to be read out from an optional unit cell, the data stored in an associated one of the dummy cells DC 0 ′ and DC 1 ′ is used to generate a reference voltage required for a comparison with the voltage on the associated bit line, as in the above mentioned case associated with data “1”. 
     As apparent from the above description, in the FeRAM according to this embodiment, data “1, 0, 0, 1” or data “0, 1, 1, 0” are stored in respective dummy cells DC 0 , DC 0 ′, DC 1 , and DC 1 ′ connected to the bit lines BL 0 , /BL 0 , SL 1 , and /BL 1  in accordance with voltages applied to those lines when data “1” is inputted to the unit cell C 00 . When data “0” is inputted to the unit cell C 00 , data “0, 1, 1, 0” or data “1, 0, 0, 1” are stored in respective dummy cells DC 0 , DC 0 ′, DC 1 , and DC 1 ′ connected to the bit lines BL 0 , /BL 0 , BL 1 , and /BL 1  in accordance with voltages applied to those lines. 
     The procedure for reading out data “1” or “0” stored in the unit cell C 00  in accordance with the above mentioned procedure will now be described. 
     First, “Vcc” is applied to the bit line BL 0 , /BL 0  and /BL 1 , and “0 V” is applied to the bit line BL 1 . Thereafter, the word line WL 0 , dummy word line DWL, and control line CL 0  are switched to their ON states, respectively. When “0 V” is applied to the plate electrode line PL 0  and the dummy plate electrode lines DPL 0  and DPL 1  in this state, a potential variation of “V 1 ” or “V 0 ” occurs on the bit line BL 0  in accordance with the data stored in the unit cell C 00 . That is, where data “1” is stored, the potential variation of the bit line BL 0  corresponds to “V 1 ”. On the other hand, where data “0” is stored, the potential variation of the bit line BL 0  corresponds to “V 0 ”. 
     When the control line CL 2  is subsequently switched to its ON state, the switching transistor ST 4  is switched to its ON state. As a result, the average value between the dummy data stored in the dummy cell DC 0 ′ and the dummy data stored in the dummy cell DC 1 ′ is applied to the inverted bit line /BL 0  as a reference voltage. 
     The reference voltage from the inverted bit line /BL 0  is applied to the comparator C 0  which also receives the voltage from the bit line BL 0 . Based on those voltages, the comparator C 0  determines data read out from the unit cell C 00 . That is, when the voltage outputted from the bit line BL 0  is higher than the reference voltage outputted from the inverted bit line /BL 0 , the data read out from the unit cell C 00  is determined to be data “1”. On the other hand, when the voltage outputted from the bit line BL 0  is not higher than the reference voltage outputted from the inverted bit line /BL 0 , the data read out from the unit cell C 00  is determined to be data “0”. 
     As apparent from the above description, in the FeRAM according to this embodiment, which consists of M×N unit cells, each unit cell has a 1T/1C structure consisting of one transistor and one capacitor. In order to generate a reference voltage for a determination of data read out on a bit line in this FeRAM, dummy cells are used, which are respectively connected to bit lines neighboring to that bit line while having a potential inverse to the potential of the bit line. In accordance with this configuration, data read out from an optional unit cell is determined by comparing a voltage outputted from a bit line, on which the data from that unit cell is read out, with a reference voltage outputted from bit lines neighboring to that bit line while having a potential inverse to the potential of the bit line. Accordingly, it is possible to greatly enhance the reliability in the determination of data read out from the unit cells of the memory while achieving a high integration of the memory. 
     FIG. 2 b  is an equivalent circuit diagram illustrating a part of an FeRAM according to a first modified embodiment from the first embodiment of the present invention. 
     Referring to FIG. 2 b , this first modified embodiment has the same configuration and arrangement as those of the first embodiment, except that the arrangement of the dummy cells DC 0 , DC 0 ′, DC 1 , and DC 1 ′ connected to respective bit lines have the same arrangement as that of the unit cells, that two dummy word lines DWL 0  and DWL 1  are used, in place of the single dummy word line DWL in the first embodiment, in such a fashion that one of the dummy word lines, that is, the dummy word line DWL 1 , is associated with the bit lines BL 0  and BL 1  (or the inverted bit lines) in odd rows (or even rows) whereas the other dummy word line, that is, the dummy word line DWL 2 , is associated with the inverted bit lines /BL 0  and /BL 1  (or the bit lines) in even rows (or odd rows). 
     In order to implement the arrangement of the dummy cells identical to that of the unit cells, the bit lines of one bit line pair, which consists of one bit line and one inverted bit line, for example, the bit lines BL 1  and /BL 1 , cross each other in front of nodes thereof connected to the dummy cells DC 1  and DC 1 ′ in such a fashion that the bit line BL 1  is connected to the dummy cell DC 1 ′ whereas the bit line BL 1 ′ is connected to the dummy cell DC 1 . 
     In the FeRAM according to the first modified embodiment, the procedures for inputting data “1” or “0” to an optional unit cell, and reading out data stored in the optional unit cell are the same as those in the first embodiment. Accordingly, no further description will be made in conjunction with those procedures. 
     Although the FeRAM according to the first modified embodiment has slightly different configurations from those of the first embodiment in that the arrangement of the dummy cells is the same as the arrangement of the unit cells, and that two separate word lines are used in place of a single word line, the same effect as that of the first embodiment can be obtained. 
     is FIG. 2 c  is an equivalent circuit diagram illustrating a part of an FeRAM according to a second modified embodiment from the first embodiment of the present invention. 
     Referring to FIG. 2 c , this second modified embodiment has the same arrangement as that of the first embodiment, except that the dummy cells DC 0 , DC 0 ′, DC 1 , and DC 1 ′ and switching transistors ST 0  to ST 5  are arranged at optional positions between unit cells neighboring to each other in a row direction, respectively. For such an arrangement, each bit line, on which a plurality of unit cells are connected, is divided into two separate portions. One dummy cell and one switching transistor are connected to one of the separate bit line portions. The separate bit line portions of each bit line are connected to each other by an interconnection line ICL 0 , /ICL 0 , ICL 1 , and /ICL 1 . 
     In the FeRAM according to the second modified embodiment, the procedures for inputting data to an optional unit cell, and reading out data stored in the optional unit cell are the same as those in the first embodiment. Accordingly, no further description will be made in conjunction with those procedures. 
     This second modified embodiment illustrates the fact that the dummy cells may be arranged at optional positions between unit cells neighboring to each other in a row direction, respectively. 
     Although the FeRAM according to the second modified embodiment has slightly different configurations from those of the first embodiment in that the dummy cells are arranged at optional positions between unit cells neighboring to each other in a row direction, respectively, the same effect as that of the first embodiment can be obtained by dividing each bit line into two separate portions, and appropriately connecting the separate bit line portions by an interconnection line. 
     [Second Embodiment] 
     FIG. 3 a  is an equivalent circuit diagram illustrating a part of an FeRAM in accordance with a second embodiment of the present invention. 
     Referring to FIG. 3 a , the FeRAM according to this embodiment is substantially identical to the first embodiment in terms of the arrangements of diverse lines including bit lines, word lines, dummy word line, and control lines, and unit cells, dummy cells, and switching transistors arranged in an interconnected fashion by those lines. However, the FeRAM according to this embodiment is different from the first embodiment in that a common plate electrode line is used, in place of separate plate electrode lines. 
     That is, the FeRAM according to the first embodiment uses separate plate electrode lines corresponding to respective columns, and separate dummy plate electrode lines corresponding to respective columns, in order to selectively apply a high voltage Vcc or a low voltage 0 V to respective plate electrodes of the unit cells and dummy cells. However, the FeRAM according to the second embodiment uses a configuration in which a single plate electrode line connected in common to all plate electrodes of the unit cells and dummy cells is used, so that a voltage of a certain level, for example, “Vcc/2”, is applied to respective plate electrodes of the unit cells and dummy cells. 
     In order to avoid an unnecessarily repeated description for the second embodiment, no description will be made in conjunction with the whole arrangement of the FeRAM according to this embodiment. In the following description, only the procedure for storing data in the FeRAM according to this embodiment using the common plate electrode line, and reading out the stored data will be described. 
     For the convenience and best understanding of description, it is assumed in the following description that a high voltage corresponds to “Vcc”, and a low voltage corresponds to 0 V. Also, it is assumed that a voltage Vp having a voltage level substantially intermediate between the high voltage and low voltage, for example, “Vcc/2”, is applied to all plate electrodes. It is also assumed that , the potential variation of a bit line when output data is “1” corresponds to “V 1 ”, and the potential variation of the bit line when output data is “0” corresponds to “V 0 ”. Since the same data storing and reading procedures are carried out in all unit cells, these procedures will be described only in conjunction with one unit cell, for example, the unit cell C 00 . 
     First, the procedure for storing data “1” in the unit cell C 00  will be described. In order to store data, the word line WL 0 , dummy word line DWL, and two control lines CL 0  and CL 1  are switched to their ON states, respectively. In this state, “Vcc” is applied to the bit line BL 0  and the bit line /BL 1  associated the unit cell C 01  neighboring to the unit cell C 00  whereas “0 V” is applied to the bit line /BL 0 . “VP” is applied to the bit line BL 1 . “Vp” is also applied to plate electrodes PL via the common plate electrode line. Due to a potential difference resulting from such a voltage application, the ferroelectric film included in the unit cell C 00  is polarized in a plus (+) direction. Accordingly, data “1” is stored. 
     As a result, data “1, 0, 1” are stored in respective dummy cells DC 0 , DC 0 ′, and DC 1 ′ connected to the bit lines BL 0 , /BL 0 , and /BL 1  in accordance with the voltages “Vcc” and “0 V” applied thereto. When data is to be read out from an optional unit cell on the bit line BL 0 , the data stored in the dummy cells DC 0 ′ and DC 1 ′ are used to generate a reference voltage required for a comparison with the voltage on the bit line BL 0 . 
     That is, the reference voltage required for a comparison with the voltage on the bit line BL 0  corresponds to an average voltage between the dummy cells DC 0 ′ and DC 1 ′. The reference voltage required for a comparison with the voltage on the bit line /BL 0  corresponds to an average voltage between the dummy cells DC 0  and DC 1 . The reference voltage required for a comparison with the voltage on the bit line BL 1  corresponds to an average voltage between the dummy cells DC 0 ′ and DC 1 ′. The reference voltage required for a comparison with the voltage on the bit line /BL 1  corresponds to an average voltage between the dummy cells DC 1  and DC 1 . 
     Alternatively, the storing of data “1” in the unit cell C 00  may be carried out in a fashion different from the above mentioned procedure. That is, in order to store data, the word line WL 0 , dummy word line DWL, and two control lines CL 0  and CL 1  are switched to their ON states, respectively. In this state, “Vcc” is applied to the bit line BL 0  and /BL 0  whereas “0 V” is applied to the bit lines BL 1  and /BL 1 . “0 V” is also applied to the bit line /BL 1 . “Vp” is applied to the bit line /BL 1 . “Vp” is also applied to the plate electrodes PL. Due to a potential difference resulting from such a voltage application, the ferroelectric film included in the unit cell C 00  is polarized in a plus (+) direction. Accordingly, data “1” is stored. 
     As a result, data “1, 1, 0” are stored in respective dummy cells DC 0 , DC 0 ′, and DC 1 ′ connected to the bit lines BL 0 , /BL 0 , and /BL 1  in accordance with the voltages “Vcc” and “0 V” applied thereto. When data is to be read out from an optional unit cell on the bit line BL 0 , the data stored in the dummy cells DC 0 ′ and DC 1 ′ are used to generate a reference voltage required for a comparison with the voltage on the bit line BL 0 . 
     Now, the procedure for storing data “0 ” in the unit cell C 00  will be described. In order to store data, the word line WL 0 , dummy word line DWL, and two control lines CL 0  and CL 1  are switched to their ON states, respectively. In this state, “0 V” is applied to the bit line BL 0  and /BL 1  whereas “Vcc” is applied to the bit line /BL 0 . Also, “Vp” is applied to the bit line BL 1 . “Vp” is also applied to the plate electrodes PL. Due to a potential difference resulting from such a voltage application, the ferroelectric film included in the unit cell C 00  is polarized in a minus (-) direction. Accordingly, data “0” is stored. 
     As a result, data “0, 1, 0” are stored in respective dummy cells DC 0 , DC 0 ′, and DC 1 ′ connected to the bit lines BL 0 , /BL 0 , and /BL 1  in accordance with the voltages “0 V” and “Vcc” applied thereto. When data is to be read out from an optional unit cell on the bit line BL 0 , the data stored in the dummy is cells DC 0 ′ and DC 1 ′ are used to generate a reference voltage required for a comparison with the voltage on the bit line BL 0 . 
     Alternatively, the storing of data “0” in the unit cell C 00  may be carried out in a fashion different from the above mentioned procedure. That is, in order to store data, the word line WL 0 , dummy word line DWL, and two control lines CL 0  and CL 1  are switched to their ON states, respectively. In this state, “0 V” is applied to the bit line BL 0  and /BL 0  whereas “Vcc” is applied to the bit line /BL 1 . Also, “Vp” is applied to the bit line BL 1 . “Vp” is also applied to the plate electrodes PL. Due to a potential difference resulting from such a voltage application, the ferroelectric film included in the unit cell C 00  is polarized in a minus (−) direction. Accordingly, data “0” is stored. 
     As a result, data “0, 0, 1” are stored in respective dummy cells DC 0 , DC 0 ′, and DC 1 ′ connected to the bit lines BL 0 , /BL 0 , and /BL 1  in accordance with the voltages “Vcc” and “0 V” applied thereto, as compared to the above mentioned procedure. When data is to be read out from an optional unit cell on the bit line BL 0 , the data stored in the dummy cells DC 0 ′ and DC 1 ′ are used to generate a reference voltage required for a comparison with the voltage on the bit line BL 0 . 
     As apparent from the above description, in the FeRAM according to this embodiment, data “1, 0, 1” or data “1, 1, 0” are stored in respective dummy cells DC 0 , DC 0 ′, and DC 1 ′ connected to the bit lines BL 0 , /BL 0 , and /BL 1  in accordance with voltages applied to those lines when data “1” is inputted to the unit cell C 00 . When data “0” is inputted to the unit cell C 00 , data “0 0, 1, 0” or data “0, 0, 1” are stored in respective dummy cells DC 0 , DC 0 ′, and DC 1 ′ connected to the bit lines BL 0 , /BL 0 , and /BL 1  in accordance with voltages applied to those lines. 
     The procedure for reading out data “1” or “0” stored in the unit cell C 00  in accordance with the above mentioned procedure will now be described. 
     First, “Vcc” is applied to the bit line BL 0 , /BL 0  and /BL 1 , and “Vp” is applied to the bit line BL 1 . Thereafter, the word line WL 0 , dummy word line DWL, and control line CL 0  are switched to their ON states, respectively. When “Vp” is applied to the plate electrodes PL in this state, a potential variation of “V 1 ” or “V 0 ” occurs on the bit line BL 0  in accordance with the data stored in the unit cell C 00 . That is, where data “1” is stored, the potential variation of the bit line BL 0  corresponds to “V 1 ”. On the other hand, where data “0” is stored, the potential variation of the bit line BL 0  corresponds to “V 0 ”. 
     When the control line CL 2  is subsequently switched to its ON state, the switching transistor ST 4  is switched to its ON state. As a result, the average value between the dummy data stored in the dummy cell DC 0 ′ and the dummy data stored in the dummy cell DC 1 ′ is applied to the inverted bit line /BL 0  as a reference voltage. 
     The reference voltage from the inverted bit line /BL 0  is applied to the comparator C 0  which also receives the voltage from the bit line BL 0 . Based on those voltages, the comparator C 0  determines data read out from the unit cell C 00 . That is, when the voltage outputted from the bit line BL 0  is higher than the reference voltage outputted from the inverted bit line /BL 0 , the data read out from the unit cell C 00  is determined to be data “1”. On the other hand, when the voltage outputted from the bit line BL 0  is not higher than the reference voltage outputted from the inverted bit line /BL 0 , the data read out from the unit cell C 00  is determined to be data “0”. 
     As apparent from the above description, in the FeRAM according to this embodiment, which consists of M×N unit cells, each unit cell has a 1T/1C structure consisting of one transistor and one capacitor. In order to generate a reference voltage for a determination of data read out on a bit line in this FeRAM, dummy cells are used, which are respectively connected to bit lines neighboring to that bit line while having a potential inverse to the potential of the bit line. In accordance with this configuration, data read out from an optional unit cell is determined by comparing a voltage outputted from a bit line, on which the data from that unit cell is read out, with a reference voltage outputted from bit lines neighboring to that bit line while having a potential inverse to the potential of the bit line. Accordingly, in accordance with this embodiment, the same effects as those in the above mentioned first embodiment are obtained. That is, it is possible to greatly enhance the reliability in the determination of data read out from the unit cells of the memory while achieving a high integration of the memory. 
     Since the configuration for connecting in common the plate electrodes of unit cells and dummy cells is used in accordance with this embodiment, an additional effect is obtained in that the capacitance in each unit cell is increased within a given area. 
     FIG. 3 b  is an equivalent circuit diagram illustrating a part of an FeRAM according to a first modified embodiment from the second embodiment of the present invention. 
     Referring to FIG. 3 b , this first modified embodiment has the same configuration and arrangement as those of the second embodiment, except that the arrangement of the dummy cells DC 0 , DC 0 ′, DC 1 , and DC 1 ′ connected to respective bit lines DC 0 , DC 0 ′, DC 1 , and DC 1 ′ have the same arrangement as that of the unit cells, that two dummy word lines DWL 0  and DWL 1  are used, in place of the single dummy word line DWL in the second embodiment, in such a fashion that one of the dummy word lines, that is, the dummy word line DWL 1 , is associated with the bit lines BL 0  and BL 1  (or the inverted bit lines) in odd rows (or even rows) whereas the other dummy word line, that is, the dummy word line DWL 2 , is associated with the inverted bit lines /BL 0  and /BL 1  (or the bit lines) in even rows (or odd rows). 
     In the FeRAM according to the first modified embodiment, the procedures for inputting data “1” or “0” to an optional unit cell, and reading out data stored in the optional unit cell are the same as those in the second embodiment. Accordingly, no further description will be made in conjunction with those procedures, in order to avoid an unnecessarily repeated description. 
     Although the FeRAM according to the first modified embodiment has slightly different configurations from those of the second embodiment in that the arrangement of the dummy cells is the same as the arrangement of the unit cells, and that two separate word lines are used in place of a single word line, the same effect as that of the second embodiment can be obtained. 
     FIG. 3 c  is an equivalent circuit diagram illustrating a part of an FeRAM according to a second modified embodiment from the second embodiment of the present invention. 
     Referring to FIG. 3 c , this second modified embodiment has the same configuration and arrangement as those of the second embodiment, except that the unit cells of the same row connected in series on each of bit lines BL 0 , /BL 0 , BL 1 , and /BL 1  are arranged in pair, and that the dummy cells DC 0 , DC 0 ′, DC 1 , and DC 1 ′ have the same arrangement as that of the unit cells. In order to implement such an arrangement according to the second modified embodiment, two dummy word lines DWL 0  and DWL 1  are used, in place of the single dummy word line DWL in the second embodiment, in such a fashion that one of the dummy word lines, that is, the dummy word line DWL 1 , is associated with the bit lines BL 0  and BL 1  (or the inverted bit lines) in odd rows (or even rows) whereas the other dummy word line, that is, the dummy word line DWL 2 , is associated with the inverted bit lines /BL 0  and /BL 1  (or the bit lines) in even rows (or odd rows). 
     In the FeRAM according to this second modified embodiment, the procedures for inputting data “1” or “0” to an optional unit cell, and reading out data stored in the optional unit cell are the same as those in the second embodiment. Accordingly, no further description will be made in conjunction with those procedures, in order to avoid an unnecessarily repeated description. 
     Although the FeRAM according to the first modified embodiment has slightly different configurations from those of the second embodiment in that the unit cells of the same row connected in series on each bit line are arranged in pair, that the dummy cells have the same arrangement as that of the unit cells, and that two dummy word lines are used, in place of a single dummy word line, the same effect as that of the second embodiment can be obtained. 
     FIG. 3 d  is an equivalent circuit diagram illustrating a part of an FeRAM according to a second modified embodiment from the third embodiment of the present invention. 
     Referring to FIG. 3 d , this third modified embodiment has the same arrangement as that of the second embodiment, except that the dummy cells DC 0 , DC 0 ′, DC 1 , and DC 1 ′ and switching transistors ST 0  to ST 5  are arranged at optional positions between unit cells neighboring to each other in a row direction, respectively. For such an arrangement, each bit line, on which a plurality of unit cells are connected, is divided into two separate portions. One dummy cell and one switching transistor are connected to one of the separate bit line portions. The separate bit line portions of each bit line are connected to each other by an interconnection line ICL 0 , /ICL 0 , ICL 1 , and /ICL 1 . 
     In the FeRAM according to the third modified embodiment, the procedures for inputting data to an optional unit cell, and reading out data stored in the optional unit cell are the same as those in the second embodiment. Accordingly, no further description will be made in conjunction with those procedures. 
     This third modified embodiment illustrates the fact that the dummy cells may be arranged at optional positions between unit cells neighboring to each other in a row direction, respectively. 
     Although the FeRAM according to the third modified embodiment has slightly different configurations from those of the second embodiment in that the dummy cells are arranged at optional positions between unit cells neighboring to each other in a row direction, respectively, the same effect as that of the second embodiment can be obtained by dividing each bit line into two separate portions, and appropriately connecting the separate bit line portions by an interconnection line. 
     [Third Embodiment] 
     FIG. 4 a  is an equivalent circuit diagram illustrating a part of an FeRAM in accordance with a third embodiment of the present invention. 
     Referring to FIG. 4 a , the FeRAM according to this embodiment is identical to respective first modified embodiments from the above mentioned embodiments of the present invention. That is, in this embodiment, each unit cell has a 1T/1C structure consisting of one transistor and one capacitor. In order to generate a reference voltage for a determination of data read out on a bit line in this FeRAM, dummy cells are used, which are respectively connected to bit lines neighboring to that bit line while having a potential inverse to the potential of the bit line so that for a determination of data read out from an optional unit cell, a voltage outputted from a bit line, on which the data from that unit cell is read out, is compared with a reference voltage outputted from bit lines neighboring to that bit line while having a potential inverse to the potential of the bit line. The dummy cells also have the same arrangement as that of the unit cells. In order to implement such configurations and arrangements according to this embodiment, two dummy word lines DWL 0  and DWL 1  are used, in place of the single dummy word line DWL in the second embodiment, in such a fashion that one of the dummy word lines, that is, the dummy word line DWL 1 , is associated with the bit lines BL 0  and BL 1  (or the inverted bit lines) in odd rows (or even rows) whereas the other dummy word line, that is, the dummy word line DWL 2 , is associated with the inverted bit lines /BL 0  and /BL 1  (or the bit lines) in even rows (or odd rows). 
     However, the FeRAM according to this embodiment is different from the FeRAM according to each of the first modified embodiments from the above mentioned embodiments in which switching transistors are arranged on the bit lines, respectively, and another switching transistors are provided to connect bit lines neighboring to each other in an interlaced fashion. That is, the FeRAM according to this embodiment only includes switching transistors each adapted to connect bit lines neighboring to each other in an interlaced fashion. Each switching transistor adapted to connect bit lines neighboring to each other in an interlaced fashion serves to store dummy data in dummy cells respectively connected to those bit lines when a bit line neighboring to those bit lines is selected to store data therein, while outputting, as a reference voltage, an average voltage between the connected bit lines when the bit line stored with the data is selected to read out the stored data. 
     In order to avoid an unnecessarily repeated description for the third embodiment, no description will be made in conjunction with the whole arrangement of the FeRAM according to this embodiment. In the following description, only the procedure for storing data in the FeRAM according to this embodiment using a simplified switching transistor arrangement, and reading out the stored data will be described. 
     For the convenience and best understanding of description, it is assumed in the following description that a high voltage corresponds to “Vcc”, and a low voltage corresponds to 0 V. Also, it is assumed that a voltage Vp having a voltage level substantially intermediate between the high voltage and low voltage, for example, “Vcc/2”, is applied to all plate electrodes. It is also assumed that, the potential variation of a bit line when output data is “1” corresponds to “V 1 ”, and the potential variation of the bit line when output data is “0” corresponds to “V 0 ”. Since the same data storing and reading procedures are carried out in all unit cells, these procedures will be described only in conjunction with one unit cell, for example, the unit cell C 00 . 
     First, the procedure for storing data “1” in the unit cell C 00  will be described. In order to store data, the word line WL 0  and dummy word line DWL 0  are switched to their ON states, respectively. In this state, “Vcc” is applied to the bit line BL 0  and the bit line /BL 1  associated the unit cell C 01  neighboring to the unit cell C 00  whereas “0 V” is applied to the bit line /BL 0 . “Vp” is applied to the bit line BL 1 . “Vp” is also applied to plate electrodes PL via a common plate electrode line. Due to a potential difference resulting from such a voltage application, the ferroelectric film included in the unit cell C 00  is polarized in a plus (+) direction. Accordingly, data “1” is stored. 
     As a result, data “0, 1” are stored in respective dummy cells DC 0 ′ and DC′ connected to the bit lines /BL 0  and /BL 1  in accordance with the voltages “Vcc” and “0 V” applied thereto. When data is to be read out from an optional unit cell on the bit line BL 0 , the data stored in the dummy cells DC 0 ′ and DC 1 ′ are used to generate a reference voltage required for a comparison with the voltage on the bit line BL 0 . 
     That is, the average voltage between the dummy cells DC 0 ′ and DC 1 ′ is used as a reference voltage required for a comparison with the voltage on the bit line BL 0  when data is to be read out from an optional unit cell on the bit line BL 0 . 
     Alternatively, the storing of data “1” in the unit cell C 00  may be carried out in a fashion different from the above mentioned procedure. That is, in order to store data, the word line WL 0  and dummy word line DWL 0  are switched to their ON states, respectively. In this state, “Vcc” is applied to the bit line BL 0  and /BL 0  whereas “0 V” is applied to the bit line /BL 1 . Also, “Vp” is applied to the bit line BL 1 . “Vp” is also applied to the plate electrodes PL. Due to a potential difference resulting from such a voltage application, the ferroelectric film included in the unit cell C 00  is polarized in a plus (+) direction. Accordingly, data “1” is stored. 
     As a result, data “1, 0” are stored in respective dummy cells DC 0 ′and DC 1 ′ connected to the bit lines /BL 0  and /BL 1  in accordance with the voltages “Vcc” and “0 V” applied thereto. When data is to be read out from an optional unit cell on the bit line BL 0 , the data stored in the dummy cells DC 0 ′ and DC 1 ′ are used to generate a reference voltage required for a comparison with the voltage on the bit line BL 0 . 
     Now, the procedure for storing data “0” in the unit cell C 00  will be described. In order to store data, the word line WL 0  and dummy word line DWL 0  are switched to their ON states, respectively. In this state, “0 V” is applied to the bit line BL 0  and /BL 1  whereas “Vcc” is applied to the bit line /BL 0 . Also, “Vp” is applied to the bit line BL 1 . “Vp” is also applied to the plate electrodes PL. Due to a potential difference resulting from such a voltage application, the ferroelectric film included in the unit cell C 00  is polarized in a minus (−) direction. Accordingly, data “0” is stored. 
     As a result, data “1, 0” are stored in respective dummy cells DC 0 ′ and DC 1 ′ connected to the bit lines /BL 0  and /BL 1  in accordance with the voltages “0 V” and “Vcc” applied thereto. When data is to be read out from an optional unit cell on the bit line BL 0 , the data stored in the dummy cells DC 0 ′ and DC 1 ′ are used to generate a reference voltage required for a comparison with the voltage on the bit line BL 0 . 
     That is, the average voltages between the dummy data outputted from the dummy cell DC 0 ′ and the dummy data outputted from the dummy cell DC 1 ′ is used as a reference voltage required for a comparison conducted for a data determination when data is read out from an optional unit cell on the bit line BL 0 . 
     Alternatively, the storing of data “0” in the unit cell C 00  may be carried out in a fashion different from the above mentioned procedure. That is, in order to store data, the word line WL 0  and dummy word line DWL 0  are switched to their ON states, respectively. In this state, “0 V” is applied to the bit line BL 0  and /BL 0  whereas “Vcc” is applied to the bit line /BL 1 . Also, “Vp” is applied to the bit line BL 1 . “Vp” is also applied to the plate electrodes PL. Due to a potential difference resulting from such a voltage application, the ferroelectric film included in the unit cell C 00  is polarized in a minus (−) direction. Accordingly, data “0” is stored. 
     As a result, data “0, 1” are stored in respective dummy cells DC 0 , DC 0 ′, and DC 1 ′ connected to the bit lines /BL 0  and /BL 1  in accordance with the voltages “0 V” and “Vcc” applied thereto. When data is to be read out from an optional unit cell on the bit line BL 0 , the data stored in the dummy cells DC 0 ′ and DC 1 ′ are used to generate a reference voltage required for a comparison with the voltage on the bit line BL 0 . 
     As apparent from the above description, in the FeRAM according to this embodiment, data “0, 1” or data “1, 0” are stored in respective dummy cells DC 0 ′ and DC 1 ′ connected to the bit lines /BL 0  and /BL 1  in accordance with voltages applied to those lines when data “1” is inputted to the unit cell C 00 . When data “0” is inputted to the unit cell C 00 , data “1, 0” or data “0, 1” are stored in respective dummy cells DC 0 ′ and DC 1 ′ connected to the bit lines /BL 0  and /BL 1  in accordance with voltages applied to those lines. 
     The procedure for reading out data “1” or “0” stored in the unit cell C 00  in accordance with the above mentioned procedure will now be described. 
     First, “Vcc” is applied to the bit line BL 0 , /BL 0  and /BL 1 , and “Vp” is applied to the bit line BL 1 . Thereafter, the word line WL 0  and dummy word line DWL 0  are switched to their ON states, respectively. When “Vp” is applied to the plate electrodes PL in this state, a potential variation of “V 1 ” or “V 0 ” occurs on the bit line BL 0  in accordance with the data stored in the unit cell C 00 . That is, where data “1” is stored, the potential variation of the bit line BL 0  corresponds to “0 V”. On the other hand, where data “0” is stored, the potential variation of the bit line BL 0  corresponds to “V 0 ”. 
     When a control line RCL 0  is subsequently switched to its ON state, the switching transistor ST 0  connected to the control line RCL 0  is switched to its ON state. As a result, the average value between the dummy data stored in the dummy cell DC 0 ′ and the dummy data stored in the dummy cell DC 1 ′ is applied to the inverted bit line /BL 0  as a reference voltage. 
     The reference voltage from the inverted bit line /BL 0  is applied to the comparator C 0  which also receives the voltage from the bit line BL 0 . Based on those voltages, the comparator C 0  determines data read out from the unit cell C 00 . That is, when the voltage outputted from the bit line BL 0  is higher than the reference voltage outputted from the inverted bit line /BL 0 , the data read out from the unit cell C 00  is determined to be data “1”. On the other hand, when the voltage outputted from the bit line BL 0  is not higher than the reference voltage outputted from the inverted bit line /BL 0 , the data read out from the unit cell C 00  is determined to be data “0”. 
     As apparent from the above description, in the FeRAM according to this embodiment, which consists of M×N unit cells, each unit cell has a 1T/1C structure consisting of one transistor and one capacitor. In order to generate a reference voltage for a determination of data read out on a bit line in this FeRAM, dummy cells are used, which are respectively connected to bit lines neighboring to that bit line while having a potential inverse to the potential of the bit line. In accordance with this configuration, data read out from an optional unit cell is determined by comparing a voltage outputted from a bit line, on which the data from that unit cell is read out, with a reference voltage outputted from bit lines neighboring to that bit line while having a potential inverse to the potential of the bit line. Accordingly, in accordance with this embodiment, the same effects as those in the above mentioned embodiments are obtained. That is, it is possible to greatly enhance the reliability in the determination of data read out from the unit cells of the memory while achieving a high integration of the memory. 
     Since the configuration for connecting in common the plate electrodes of unit cells and dummy cells is used in accordance with this embodiment, an additional effect is obtained in that the capacitance in each unit cell is increased within a given area, as in respective first modified embodiments of the above mentioned embodiments. 
     Furthermore, the FeRAM according to this embodiment provides another advantage in that a simplification in arrangement is achieved, as compared to the FeRAM according to respective first modified embodiment of the above mentioned embodiments, because the arrangement for storing and reading out dummy data is implemented only using the switching transistors adapted to connect bit lines neighboring to each other in an interlaced fashion. 
     FIG. 4 b  is an equivalent circuit diagram illustrating a part of an FeRAM according to a second modified embodiment from the second embodiment of the present invention. 
     Referring to FIG. 4 b , this second modified embodiment has the same configuration and arrangement as those of the above mentioned embodiments, except that the unit cells connected in series on each of the bit lines BL 0 , /BL 0 , BL 1 , and /BL 1  are arranged in pair. 
     In the FeRAM according to the first modified embodiment, the procedures for inputting data “1” or “0” to an optional unit cell, and reading out data stored in the optional unit cell are the same as those in the second embodiment. Accordingly, no further description will be made in conjunction with those procedures, in order to avoid an unnecessarily repeated description. 
     Although the FeRAM according to the first modified embodiment has slightly different configurations from those of the second embodiment in that the unit cells connected in series on each of the bit lines are arranged in pair, the same effect as that of the third embodiment can be obtained. 
     As apparent from the above description, in the FeRAM according to this embodiment, which consists of M×N unit cells, each unit cell has a 1T/1C structure consisting of one transistor and one capacitor. In order to generate a reference voltage for a determination of data read out on a bit line in this FeRAM, dummy cells are used, which are respectively connected to bit lines neighboring to that bit line while having a potential inverse to the potential of the bit line. In is accordance with this configuration, data read out from an optional unit cell is determined by comparing a voltage outputted from a bit line, on which the data from that unit cell is read out, with a reference voltage outputted from bit lines neighboring to that bit line while having a potential inverse to the potential of the bit line. Accordingly, it is possible to greatly enhance the reliability in the determination of data read out from the unit cells of the memory while achieving a high integration of the memory. 
     Since a single plate electrode is connected in common to memory cells, using a common plate electrode line in place of plate electrode lines separated from one another in a row or column direction, it is possible to achieve an increase in capacitance within a given area. 
     Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.