Abstract:
A method and apparatus for processing data in a system comprising a central processing unit (CPU), a system memory, and a graphics processing unit (GPU) includes determining whether the GPU is an integrated graphics processor (IGP). Based upon a determination that the GPU is an IGP, data stored in the system memory is accessed by the GPU without copying the data to a memory on the GPU. Processing is performed on the data in the GPU.

Description:
FIELD OF INVENTION 
     This application is related to processing data. 
     BACKGROUND 
     In media transcoder software, (e.g., decoding and encoding software), a graphics processor unit (GPU) may be used to “load-balance” the encoding process by performing a task such as motion estimation (ME). The GPU performs a search, (e.g., “best search”), comparing two blocks of memory that are already decoded and resident in application memory, a reference frame, and a current frame. When a best match is found, the GPU returns motion vectors that describe, (i.e., point to), the best match in the reference frame. 
     Historically, ME was performed on discrete GPUs that were resident on a peripheral component interconnect-express (PCIe) or similar system bus. In order to do the motion estimation, the blocks of memory previously described were copied from the application memory, over to the video memory local to the GPU, (e.g., on the PCIe bus). The GPU operates on this video memory. In systems where the GPU resides on a video card that is only accessible over an external bus, such as an accelerated graphics port (AGP), peripheral component interconnect (PCI), or the PCIe bus, the GPU is separate from the motherboard and CPU, and does not have access directly to the system memory. In a system having an integrated graphics processor (IGP), (e.g., a system including an Advanced Micro Devices, Inc. (AMD) RS880 chipset), the GPU may be integrated into the motherboard and has access directly to the system memory via a physical connection to the central processing unit (CPU), which may include the system&#39;s main memory controller. Accordingly, the IGP may access the system memory via the CPU or the video memory that is attached directly to the IGP. 
     Accordingly, it would be beneficial to provide a method and apparatus that is capable of data copy elimination by using the system memory, for example where an IGP uses the same dynamic random access memory (DRAM) as the CPU. 
     SUMMARY 
     A method and apparatus for processing data in a system comprising a central processing unit (CPU), a system memory, and a graphics processing unit (GPU) is disclosed. The method includes determining whether the GPU is an integrated graphics processor (IGP). Based upon a determination that the GPU is an IGP, data stored in the system memory is accessed by the GPU without copying the data to a memory on the GPU. Processing is performed on the data in the GPU. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is an example functional block diagram of a system including an IGP; and 
         FIG. 2  is an example flow diagram of a method for performing a data processing function. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Where the GPU and CPU may share the same physical system memory, such as in the case where the GPU is an IGP, the GPU may access this system memory in order to perform operations on data. Accordingly, it is not necessary to make a copy of the data from the system memory.  FIG. 1  is an example functional block diagram of a system  100  including an IGP. In a system that includes an IGP, the IGP may be a graphics chip that is integrated, (e.g., by direct attachment), to the motherboard as opposed to a video processor chip on a video card that is only accessible over an external bus, such as an AGP, PCI, or PCIe bus. Alternatively, an IGP as described herein may include a GPU that is integrated into the same chip as the CPU, for example on an accelerated processing unit (APU)—those processors that include both a central processing unit and a graphics processing unit. 
     The system  100  includes, for example, a CPU  110 , memory units  120  (e.g., DDR CH 1   120   1  and DDR CH 2   120   2 ), and GPU  130 . The system  100  may also include a PCIe graphic device  140  and a PCIe graphic device memory  150  accessible over a PCIe bus  180 . Together, the PCIe graphic device  140  and the PCIe graphic device memory  150  may be referred to as a PCIe processing unit  160 . The CPU  110  of the present example includes a CPU 0 , CPU 1 , Caches, Crossbar, and an Integrated Memory Controller. The GPU  130  includes a CPU bus interface  131 , a 2-D engine  132 , a display refresh  133 , universal video decode (UVD)  134 , 3-D engine  135 , and PCIe bus controller  136 . The GPU  130  communicates with the CPU  110  over a CPU bus  170  and shares access to the memory units  120 . The PCIe graphic device  140  may also include a UVD, 3-D and 2-D engine, and a display refresh and is in communication with the PCIe graphic device-memory  150 . The PCIe graphic device  140  may communicate with the PCIe bus controller  136  of the GPU  130  over the PCIe bus  180 . Together, the components of the system  100  may utilize a CPU ID application programming interface (API) and a compute abstraction layer (CAL) API to utilize accelerators in the system. 
     The CPU  110  and GPU  130  may be integrated into the same chip, or die, and therefore may be considered an APU. In this case, the GPU  130  may be referred to as an IGP. 
       FIG. 2  is an example flow diagram of a method  200  for performing a data processing function. In step  210 , a determination is made whether the system, (e.g., system  100 ), includes an integrated accelerator device, (e.g., an IGP included on the motherboard of the system  100 ). Using the example of system  100 , the integrated accelerator device may include the GPU  130 . This determination may be performed using a chipset identification (ID), CPUID or other operating system (OS) API function. For example, this determination may be made by examining the chipset documentation to verify that there are areas in memory sharable with the CPU  110 , or by using a “memory-test”, where a pattern is written into the CPU system memory  120 , and subsequently, the GPU  130  is programmed to verify this pattern, or vice-versa, that both processors are using the same physical address. 
     In one example, where CPUID and CAL APIs are utilized, the CPUID API may provide a family, model, and stepping value of the CPU  110 . The CAL API may then determine a count of devices that share memory with the CPU  110 . 
     If an integrated accelerator device is in use (step  220 ), an indicator, such as a CPU_IGP Shared Memory Bit may be set equal to “1” to indicate the existence of an IGP, whereas if an integrated accelerator device is not in use, then the CPU_IGP Shared Memory Bit may be set to “0” to indicate an IGP is not in use. Since the data is currently in the system memory  120 , the setting of the CPU_IGP Shared Memory Bit indicates whether or not the data is to be copied to the PCIe accelerator device in order to perform processing on the data. 
     For example, when performing motion estimation, raw data such as YUV data of previous or future pictures are to be encoded. The accelerators, (e.g., GPU  130 ), that are sharing memory with the CPU  110  divide or sub-divide the block of raw data of the current block to be encoded into sub-blocks, (e.g., 16×16 pixels). The accelerators search the previous or future picture frames for the block of data that best matches the current block to be encoded. In other applications that share memory, the data operated on by the accelerators could be large matrices of floating point data that may be used to transform a three-dimensional (3D) X, Y, Z, W vertex (3D point). 
     Accordingly, in the present example, if the CPU_IGP Shared Memory Bit is “1”, indicating the presence of an IGP in use in step  220 , then the data pointer in the system memory is saved without copying the data to the PCIe processing unit  160  (step  230 ). The data pointer saved in the system memory is abstracted by the handle for processing. This handle may be the numeric value that the API assigns to the application to represent a resource, such as a block of memory. The application uses the handle to operate on, and represent the block of memory, and the handle is a structure that contains values such as the memory address of the resource. The CPU  110 , or GPU  130 , utilizes this to operate on the memory. The memory address to the resource referred to is the data pointer. 
     For example, the CPU&#39;s  110  and IGP&#39;s (GPU  130 ) memory address space might be located in the system memory  120  from address 0x000000 to 0x0FFFFF (hexidecimal). The PCIe processing unit&#39;s  160  memory address space) might be located from 0x100000 to 0x1FFFFF (hexidecimal). Both address-spaces in this example are 1 megabyte in size. On IGP systems that may employ this application, both CPU and IGP GPU address spaces may be in the same physical DRAM chip, such as both in DDR CH 1   120   1  or both in DDR CH 2   120   2 , or the address spaces may be on different DRAM chips on the system board. For example, the CPU&#39;s  110  address space is on DDR CH 1   120   1  and the IGP GPU&#39;s  130  address space is on DDR CH 1   120   2 . The GPU  130  in these cases has read/write access to the system memory  120  at the same physical address as that used by the CPU  110 . 
     Alternatively in the present example, if the CPU_IGP Shared Memory Bit is “0” in step  220 , (i.e., an IGP is not in use), data is copied to the PCIe processing unit  160  using the data pointer to the PCIe graphic-device memory  150  (step  240 ). The data pointer to the PCIe graphic-device memory  150  is obtained from the handle for processing in this example. 
     In step  250 , the data is processed on the accelerator using the handle to the memory, (i.e.,  120  or  150 ), supplied in either steps  230  or  240 . For example, motion estimation, or other processes as described above, may be performed on the data in step  250 . It is then determined whether the data needs to be copied back to the system memory  120  (step  260 ). In the present example, the determination may be that the data does not need to be copied back to the system memory  120  if the CPU_IGP Shared Memory Bit was set to “1”, or does need to be copied back into the system memory if the CPU_IGP Shared Memory Bit was set to “0”. 
     If the data needs to be copied back into the system memory in step  260 , (e.g., the CPU_IGP Shared Memory Bit was set to “0”), the data is copied from the PCIe processing unit  160  back to the system memory (step  270 ). This may be performed by using the pointer to the PCIe graphic-device memory  150  and the handle for processing. The next batch of data is then processed (step  280 ), if such a batch exists, by returning to step  210 . 
     If the data does not need to be copied back into the system memory in step  260 , (e.g., the CPU_IGP Shared Memory Bit was set to “1”), then since the copying of the data from the PCIe processing unit  160  to the system memory step may be skipped, the next batch of data may then be processed (step  280 ), if such a batch exists, by returning to step  210 . Since the copying step is skipped, a time savings may occur. 
     One example of performing the method  200  is by modifying code to provide for the GPU  130  to access the data in the system memory  120  without having to copy the data in the system memory  120  when the GPU is an IGP. For example, where the GPU  130  is an IGP, code may be executed that skips a step of copying the data from the system memory  120  to memory of the GPU  130 . Alternatively, when the GPU is not an IGP, code may be executed that causes the data to be copied first to the GPU memory and then back to the system memory after processing of the data. Also, although for example purposes, the PCIe graphic device  140  communicates over the PCIe bus, a PCIe graphic device that may have access directly to the system memory  120  may utilize the above method  200 . In this example however, there may be a difference in bandwidth compared to that of an IGP device. 
     Although features and elements are described above in particular combinations, each feature or element can be used alone without the other features and elements or in various combinations with or without other features and elements. The methods or flow charts provided herein may be implemented in a computer program, software, or firmware incorporated in a computer-readable storage medium for execution by a general purpose computer or a processor. Examples of computer-readable storage mediums include a read only memory (ROM), a random access memory (RAM), a register, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks, and digital versatile disks (DVDs). 
     Suitable processors include, by way of example, a general purpose processor, a special purpose processor, a conventional processor, a digital signal processor (DSP), a plurality of microprocessors, one or more microprocessors in association with a DSP core, a controller, a microcontroller, Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) circuits, any other type of integrated circuit (IC), and/or a state machine. Such processors may be manufactured by configuring a manufacturing process using the results of processed hardware description language (HDL) instructions (such instructions capable of being stored on a computer readable media). The results of such processing may be maskworks that are then used in a semiconductor manufacturing process to manufacture a processor which implements aspects of the present invention.