Abstract:
In one embodiment the present invention includes a method of fabricating a quad flat no-lead (QFN) chip package. The method includes forming a stamped lead frame; forming a die pad and a lead shrink on one side of the stamped lead frame; mounting a die on the die pad; performing wire bonding; encapsulating the die and the wire bond with a molding compound; removing the stamped lead frame after encapsulating; and sawing the molding compound after the stamped lead frame has been removed. Such method results in improved quality of wire leads, improved lifespan of cutting blades, and reduction of burrs as compared to many existing methods of fabricating QFN chip packages.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    Not applicable. 
       BACKGROUND 
       [0002]    The present invention relates to quad flat no-lead (QFN) microchip package fabrication processes, and in particular, to extending the life of cutting blades used in QFN package fabrication processes. 
         [0003]    Existing QFN packages are often made using the following procedure. A lead frame is provided. Often the lead frame has a special tape on one side. The tape is used for wire bond vacuum and to provide support for the lead frame. Next, the dies are placed on the lead frame, and wire bonding is performed. Then, a molding compound is applied to encapsulate the lead frame, the dies, and the wire leads. Finally, the encapsulated dies are sawed apart into individual QFN package units. 
         [0004]    The thickness of current lead frames may vary; common thicknesses include 0.127 um, 0.152 um, and 0.203 um. The lead frame material may be a copper alloy material such as Olin C7025. The special tape used may vary as well. Common types of tape include Nitto tape and Hitachi tape. 
         [0005]    A number of problems arise from the above-described fabrication process. First, problems arise relating to the special tape. If the lead frame includes one type of special tape, the tape often outgases due to the temperatures involved in the wire bonding process, and the outgas negatively affects the wire bonding quality. If the lead frame includes another type of special tape, warpage issues arise during lead frame production. 
         [0006]    Second, since the lead frame is encapsulated within the molding compound, during the sawing process the saw must also cut the lead frame. The metal structure of the lead frame reduces the lifespan of the saw blade. 
         [0007]    Third, sawing the metal lead frame often results in burrs. Burrs are undesirable because they may cause quality and reliability issues when the device is used on the circuit board. Specifically, the burrs may contribute to short circuits during device testing. 
         [0008]    Thus, there is a need for an improved QFN package fabrication processes. The present invention solves these and other problems by using a different type of lead frame. 
       SUMMARY 
       [0009]    Embodiments of the present invention improve upon the process of fabricating quad flat no-lead (QFN) chip packages. In one embodiment, the present invention includes a method of fabricating a chip package. The method includes forming a stamped lead frame; forming a die pad and a lead shrink on one side of the stamped lead frame; mounting a die on the die pad; performing wire bonding; encapsulating the die and the wire bond with a molding compound; removing the stamped lead frame after encapsulating; and sawing the molding compound after the stamped lead frame has been removed. 
         [0010]    In another embodiment, the present invention includes a chip package produced by the above method. 
         [0011]    The above method increase the lifespan of the saw blades as compared to many existing methods of fabricating QFN chip packages, among other benefits. 
         [0012]    The following detailed description and accompanying drawings provide a better understanding of the nature and advantages of the present invention. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]      FIG. 1  is a block diagram of a method of fabricating a QFN chip package according to an embodiment of the present invention. 
           [0014]      FIG. 2  is a perspective view of a stamped lead frame according to an embodiment of the present invention. 
           [0015]      FIG. 3  is a top perspective view of a lead frame according to an embodiment of the present invention. 
           [0016]      FIG. 4  is a bottom perspective view of the lead frame shown in  FIG. 3 . 
           [0017]      FIG. 5  is a cross-sectional view of the lead frame shown in  FIG. 3 . 
           [0018]      FIG. 6  is a top perspective view of a lead frame and related structures according to an embodiment of the present invention. 
           [0019]      FIG. 7  is a top perspective view of a lead frame and related structures according to an embodiment of the present invention. 
           [0020]      FIG. 8  is a top perspective view of a lead frame and related structures according to an embodiment of the present invention. 
           [0021]      FIG. 9  is a top perspective view of a lead frame and related structures according to an embodiment of the present invention. 
           [0022]      FIG. 10  is a bottom perspective view of a strip block according to an embodiment of the present invention. 
           [0023]      FIG. 11  is a bottom perspective view of a strip block according to an embodiment of the present invention. 
           [0024]      FIG. 12  is a top perspective view of a QFN package unit according to an embodiment of the present invention. 
           [0025]      FIG. 13  is a bottom perspective view of the QFN package unit of  FIG. 12 . 
           [0026]      FIG. 14  is cut-away top perspective view of the QFN package unit of  FIG. 12 . 
           [0027]      FIG. 15  is a cross-sectional view of the QFN package unit of  FIG. 12 . 
       
    
    
     DETAILED DESCRIPTION 
       [0028]    Described herein are techniques for QFN chip package fabrication processes. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention as defined by the claims may include some or all of the features in these examples alone or in combination with other features described below, and may further include obvious modifications and equivalents of the features and concepts described herein. 
         [0029]    The following description describes various methods and processes. Although the particular method steps are discussed in a particular order, such discussion is mainly for clarity of presentation. It should be recognized that such order may be varied, and some steps may be performed in parallel. One step need only follow another step when the other step must be completed before the one step begins. 
         [0030]      FIG. 1  is a block diagram of a method  100  of fabricating a QFN chip package according to an embodiment of the present invention.  FIGS. 2-15  are various illustrative diagrams that are further described with reference to the method steps to which they most closely relate. 
         [0031]    In step  102 , the lead frame is formed from a thin metal material, such as a copper alloy material. Holes are stamped in the thin metal material to form the lead frame. Suitable materials for the lead frame include Olin C7025 and EFTEC 64T. Various thicknesses of the lead frame are appropriate, with a range of approximately 0.10 mm to 0.30 mm. 
         [0032]      FIG. 2  is a perspective view of a stamped lead frame  200 . The stamped lead frame  200  includes a number of holes  202 . The holes  202  may be different sizes, as appropriate, for the various types of structures that are to be formed on the lead frame  200 . For example, the holes corresponding to the die pads may be larger than those for the lead shrinks (discussed more filly below). The lead frame size is determined by the mold chase. It can be changed from small size to large size. The numbers and sizes for the holes are determined by the QFN unit pin size and layout. 
         [0033]    In step  104 , the die pads and lead shrinks are formed on one side of the stamped lead frame. This side may be referred to as the top side. The die pads are used in die placement (discussed below). The lead shrinks connect to the wire leads (discussed below). 
         [0034]      FIG. 3  is a top perspective view of the lead frame  200  showing the die pads  204  and the lead shrinks  206 .  FIG. 4  is a bottom perspective view of the lead frame  200  shown in  FIG. 3 .  FIG. 5  is a cross-sectional view of the lead frame  200  shown in  FIG. 3 . 
         [0035]    In step  106 , epoxy is applied to the die pads.  FIG. 6  is a top perspective view of the lead frame  200  showing the epoxy  208  having been applied to the die pads  204 . 
         [0036]    In step  108 , the dies are mounted on the die pads via the epoxy.  FIG. 7  is a top perspective view of the lead frame  200  showing the dies  210  having been mounted on the die pads  204 . 
         [0037]    In step  110 , wire bonding is performed. In wire bonding, a wire is extruded to connect a pad on one of the dies to a corresponding one of the lead shrinks. In this manner, an electrical connection is made between the die and the lead shrink. Such wires may be referred to as wire leads. Wire leads may be made from conductive materials, such as gold. 
         [0038]      FIG. 8  is a top perspective view of the lead frame  200  showing the wire leads  212  having been connected between the dies  210  and the lead shrinks  206 . As the lead frame does not include mounting tape, there is no outgassing involved from the tape resulting from the temperatures involved in wire bonding. Thus, the wire bonding quality is improved as compared to wire bonding performed when the lead frame includes mounting tape. 
         [0039]    In step  112 , encapsulation is performed. Encapsulation involves applying a molding compound to encapsulate the dies, the wire leads, and the other parts that are to be internal in the completed QFN package. Epoxy may be used as the molding compound. The molding compound is applied to the side of the lead frame where the dies and wire leads have been attached, which may be referred to as the top side. The resulting encapsulated structure that includes the dies may be referred to as a strip or a strip block. 
         [0040]      FIG. 9  is a top perspective view of the lead frame  200  showing the molding compound  214  having been applied. As can be seen, the molding compound  214  encapsulates the dies  210  and the wire leads  212 . Referring back to  FIG. 5 , note the small concavity space around the die pads  204  and the lead shrinks  206  on the top side of the lead frame  200 . The small concavity space allows the molding compound  214  to fill in and lock in the die pads  204  and the lead shrinks  206 . 
         [0041]    In step  114 , the lead frame is removed from the strip block. As the lead frame is made from a thin metal material, the lead frame peels away easily.  FIG. 10  is a bottom perspective view of the strip block  216  with the lead frame having been removed. With the lead frame removed, the die pads  204  and the lead shrinks  206  are exposed. The die pads  204  and the lead shrinks  206  have a fixed standoff from the molding compound surface due to their original placement on the lead frame. Such a standoff may vary depending upon the thickness of the lead frame, and upon the distance of the lead in the frame. Desirable ranges for the standoff are between approximately  0 . 02  mm and  0 . 10  mm. The standoff offers good solderability once the QFN packages have been separated into individual units. The exposed die pads  204  and lead shrinks  206  may be plated at this point. 
         [0042]    In step  116 , strip testing may be performed. Strip testing involves testing the electrical connections of the strip block prior to the dies being separated into individual QFN units. Marking may also be performed at this stage. 
         [0043]    In step  118 , the strip block is sawed to separate the encapsulated dies into individual package units.  FIG. 11  is a bottom perspective view of the strip block  216  being sawed by a saw blade  218 . Since the lead frame has been removed, the saw blade  218  need not cut through the lead frame as it cuts the strip block  216 . Thus, the lifespan of the saw blade  218  is improved as compared to saw blades that also cut the lead frame when cutting a strip block. In addition, since the lead frame has been removed, sawing the strip block does not result in metal burrs being produced. Thus, QFN packages manufactured in accordance with the above method have reduced short-circuiting test issues as compared to QFN packages produced with burrs. 
         [0044]      FIG. 12  is a top perspective view of a QFN package unit  220  resulting from the strip block  216  having been sawed into individual units.  FIG. 13  is a bottom perspective view of the QFN package unit  220 . The die pad  204  and the lead shrinks  206  can be seen. 
         [0045]      FIG. 14  is cut-away top perspective view of the QFN package unit  220 . The molding compound has been cut away to show the die pad  204 , the lead shrinks  206 , the wire leads  212 , and the die  210 . 
         [0046]      FIG. 15  is a cross-sectional view of the QFN package unit  220 . The molding compound  214 , the die pad  204 , the lead shrinks  206 , the wire leads  212 , and the die  210  can be seen. 
         [0047]    As can be seen from the above description, embodiments of the present invention improve upon QFN chip package fabrication processes. First, wire bonds have improved quality. Second, the lifespan of the saw blades is increase. Third, the packages have no burrs. 
         [0048]    Although the above description of the preferred embodiments has focused on QFN chip packages, such discussion is mainly for illustrative purposes. Similar principles may be applied to other types of chip packaging processes as desired. 
         [0049]    The above description illustrates various embodiments of the present invention along with examples of how aspects of the present invention may be implemented. The above examples and embodiments should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the present invention as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents will be evident to those skilled in the art and may be employed without departing from the spirit and scope of the invention as defined by the claims. The terms and expressions that have been employed here are used to describe the various embodiments and examples. These terms and expressions are not to be construed as excluding equivalents of the features shown and described, or portions thereof, it being recognized that various modifications are possible within the scope of the appended claims.