Abstract:
A clock generator circuit which produces a clock signal which may have an adjustable steady state duty cycle and which has the same frequency as a crystal frequency. The clock generator circuit includes a drive circuit coupled to the crystal which converts the first signal to a clock signal, and a duty cycle control circuit which generates a feedback signal to cause the duty cycle to automatically change to the steady state duty cycle. The clock generator circuit of the present invention may also include an output pad for allowing a measuring instrument to determine the duty cycle.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to circuits which generate clock signals, and more specifically to a circuit and method for generating a clock signal. 
     Digital systems typically require one or more clock signals which synchronize activities performed by different functional parts within the systems. It is desirable in such systems that the clock signals have fifty percent duty cycles. The term &#34;duty cycle&#34; is well known to mean the ratio of pulse width to total cycle time. Thus, for a fifty percent duty cycle clock signal, the clock signal is high for half the cycle time. 
     Known methods of generating a clock signal having a fifty percent duty cycle involve generating a signal having a frequency equal to twice the desired frequency and dividing the signal by two to remove any duty cycle distortion. 
     These methods suffer from high cost. For example, a 100 MHz crystal is more expensive than a 50 MHz crystal. These systems also consume high amounts of power, produce high amounts of radio frequency (RF) radiation, and degrade system performance. Finally, they produce clock signals whose duty cycles are difficult to measure during production testing. 
     Therefore, it would be desirable to provide a circuit and method for generating a clock signal which do not suffer from the disadvantages above. It would also be desirable that the circuit and method produce a clock signal having a steady state duty cycle which is not limited to fifty percent. 
     SUMMARY OF THE INVENTION 
     In accordance with the teachings of the present invention, a circuit and method for generating a clock signal are provided. The clock generator circuit includes a crystal which generates a first signal having a frequency, and a control circuit coupled to the crystal converts the first signal into a clock signal which has the same frequency as the first signal and which has a duty cycle and a steady state duty cycle. 
     Thus, it is a feature of the present invention that the crystal frequency and the clock frequency are the same; no frequency divider is required. 
     The control circuit includes a drive circuit coupled to the crystal which converts the first signal to a clock signal and which has a clock signal output and a feedback signal input, and a duty cycle control circuit, which is coupled between the clock signal output and the feedback signal input, and which generates the feedback signal to cause the duty cycle to automatically change to the steady state duty cycle. 
     Thus, it is a feature of the present invention that variations from a steady state duty cycle are automatically corrected. 
     The clock generator circuit of the present invention may also include a circuit element which changes the steady state duty cycle to a new steady state duty cycle. The steady state duty cycle may be changed without changing the circuit. 
     Finally, the clock generator circuit may also include an output pad for allowing a measuring instrument to determine the duty cycle. 
     It is accordingly an object of the present invention to provide a circuit and method for generating a clock signal. 
     It is another object of the present invention to provide a circuit and method for generating a clock signal which do not use a frequency divider. 
     It is another object of the present invention to provide a circuit and method for generating a clock signal which has the same frequency as a crystal within the circuit. 
     It is another object of the present invention to provide a circuit and method for generating a clock signal which automatically adjusts the duty cycle to a steady state duty cycle. 
     It is another object of the present invention to provide a circuit and method for generating a clock signal in which the steady state duty cycle is adjustable without modification to the circuit. 
     It is another object of the present invention to provide a circuit and method for generating a clock signal which provides for measurement of the duty cycle. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Additional benefits and advantages of the present invention will become apparent to those skilled in the art to which this invention relates from the subsequent description of the preferred embodiments and the appended claims, taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a diagram of the circuit of the present invention; 
     FIGS. 2(A), 2(B) and 2(C) are a waveform diagram illustrating the operation of the circuit of the present invention; and 
     FIG. 3 is a block diagram of a system incorporating the circuit of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring now to FIG. 1, clock signal generator 10 includes crystal 12 and control circuit 14. 
     Crystal 12 produces a signal CLOCK --  IN to control circuit 14. Signal CLOCK --  IN is substantially constant in frequency. 
     Control circuit 14 includes driver circuit 16 and duty cycle control circuit 18. 
     Driver circuit 16 amplifies signal CLOCK --  IN , converts signal CLOCK --  IN to signal CLOCK --  OUT, and adjusts the duty cycle of signal CLOCK --  OUT in response to control signals from duty cycle control circuit 18. Driver circuit 16 includes field effect transistors (FETs) MP1, MP2, MN1, and MN2, which are connected in series between Vdd and ground. FETs MP1 and MP2 are p-channel FETs. FETs MN1 and MN2 are n-channel FETs. The gates of FETs MP2 and MN1 are also connected with each other and with an input terminal providing signal CLOCK --  IN . A center tap between FETs MP2 and MN1 provides output clock signal CLOCK --  OUT. The gates of FETs MP1 and MN2 are connected together and to a bias voltage Vb from duty cycle control circuit 18. 
     Duty cycle control circuit 18 monitors the voltage Vc of signal CLOCK --  OUT at the connection of FETs MN1 and MP2 and produces bias voltage Vb at the gates of FETs MP1 and MN2 to control the duty cycle of signal CLOCK --  OUT. 
     With reference to FIGS. 2(A), 2(B) and 2(C), the following can be said about the relationship between bias voltage Vb and voltage Vdd for a fifty percent duty cycle: 
     1. When bias voltage Vb is half of voltage Vdd, the charge current through FETs MP1 and MP2 is the same as the discharge current through FETs MN1 and MN2. The rise and fall times of signal CLOCK --  OUT are the same and a fifty percent duty cycle results (waveform (a)). 
     2. When bias voltage Vb is larger than half of voltage Vdd, the charge current is smaller than the discharge current. The rise time is greater than the fall time and a less than fifty percent duty cycle results (waveform (b)). 
     3. When bias voltage Vb is smaller than half of voltage Vdd, the charge current is larger than the discharge current. The rise time is less than the fall time and a greater than fifty percent duty cycle results (waveform (c)). 
     Referring back to FIG. 1, duty cycle control circuit 18 includes differential amplifier DA1, and resistors R1-R4, FETs MN3, MP3, MN4, and MP4, and capacitors C1 and C2. Differential amplifier DA1 has a gain G. 
     Resistors R1 and R2, FETs MN3 and MP3, and capacitor C2 form a first adjustment circuit which is connected between ground and a first input of amplifier DA1. Resistors R1 and R2, and FETs MN3 and MP3 are connected in series between voltage Vdd and ground. A tap point between resistors R1 and R2 provides voltage V1 to amplifier DA1. The gate of FET MP3 is connected to ground. The gate of MN3 is connected to voltage Vdd. 
     Capacitor C1 is a decoupling capacitor which filters out any noise from voltage Vdd and ground and reduces any overshoot in feedback response. 
     Resistors R3 and R4, FETs MN4 and MP4, and capacitor C1 form a second adjustment circuit which is connected between the output clock terminal of driver circuit 16 and a second input of amplifier DA1. Resistors R3 and R4, and FETs MN4 and MP4 are connected in series between voltage Vdd and ground. A tap point between resistors R3 and R4 provides voltage V2 to amplifier DA1. The gates of FETs MP4 and MN4 are connected with each other and with the output clock terminal of driver circuit 16. 
     Capacitor C2 is a decoupling capacitor which filters out any noise from voltage Vdd and ground and reduces any overshoot in feedback response. 
     Bias voltage Vb is determined by the input voltages of differential amplifier DA1: 
     
         Vb=Vdd/2+G(V1-V2) 
    
     If the resistances of FETs MP3 and MN3 are much smaller than resistors R1 and R2, and the resistances of FETs MP4 and MN4 are much smaller than resistors R3 and R4, then voltages V1 and V2 are determined by the following equations: 
     
         V1=Vdd.R2/(R1+R2), 
    
     
         V2=Vdd.R4/(R3+R4). 
    
     For a fifty percent duty cycle, resistor R1 equals resistor R2 and resistor R3 equals resistor R4. Thus, 
     
         V1=V2=Vdd/2 
    
     The amounts of charge being transported from voltage Vdd to voltage V2 and from voltage V2 to ground during each clock cycle are: 
     
         Q1=[(Vdd-V2)/R3].T.(1-D), 
    
     
         Q2=[(V2-0)/R4].T.D, 
    
     where T is the clock cycle time and D is the duty cycle of signal CLOCK --  OUT. 
     Charge Q1 equals charge Q2 under steady state conditions. Thus, 
     
         V2=(1-D).Vdd. 
    
     Thus, voltage V2 is directly proportional to (1-D) of signal CLOCK --  OUT. Since V1=V2=Vdd/2 for R1=R2 and R3=R4, the duty cycle D must equal fifty percent. 
     Advantageously, duty cycle control circuit 18 is capable of generating a fifty percent duty cycle without using an expensive crystal, having a frequency of twice the clock frequency, in combination with a divide-by-two circuit. 
     It is a feature of the present invention that duty cycle control circuit 18 seeks a steady state duty cycle D. If the instantaneous duty cycle were larger than D, voltage V2 would be smaller than V1. Consequently, bias voltage Vb would be larger than D.Vdd, which, in turn, would reduce the duty cycle towards D. 
     It is another feature of the present invention that duty cycle control circuit 18 may also be used to adjust the steady state duty cycle D to any number other than fifty percent. Steady state duty cycle D may be adjusted by adjusting resistors R1-R4 as follows: 
     
         R3=R4 and 
    
     
         R2=(1-D)(R1+R2) 
    
     If the desired duty cycle D is very much larger or smaller than fifty percent, several adjustment circuits may be cascaded to achieve the desired duty cycle D without suffering from a very slow rise or fall time. 
     Finally, it is another feature of the present invention that duty cycle control circuit 18 provides an easy and cost-effective way to determine the duty cycle D of signal CLOCK --  OUT. Since voltage V2 is directly proportional to (1-D) and voltage Vdd is known, duty cycle D is determined by measuring voltage V2 at bonding pad 22. 
     Referring to FIG. 3, control circuit 14 of the present invention is suited for use within any system 30 within a computer. System 30 also includes a logic element 32 which employs signal CLOCK --  OUT. 
     Although the present invention has been described with particular reference to certain preferred embodiments thereof, variations and modifications of the present invention can be effected within the spirit and scope of the following claims.