Abstract:
The prevent disclosure discloses a structure of thermal resistive layer and the method of forming the same. The thermal resistive structures, formed on a plastic substrate, comprises a porous layer, formed on said plastic substrate, including a plurality of oxides of hollow structure, and a buffer layer, formed on said porous layer, wherein said porous layer can protect said plastic substrate from damage caused by the heat generated during manufacturing process. With the structure and method disclosed above, making a thin film transistor and forming electronic devices on the plastic substrate in the technology of Low Temperature PolySilicon, i.e. LTPS, without changing any parameters is possible.

Description:
CROSS REFERENCE TO RELATED PATENT APPLICATION 
       [0001]    This application is a divisional application of U.S. patent application Ser. No. 12/630,204 filed on Dec. 03, 2009, which claims the foreign priority of Taiwanese patent application 093133566 filed on Nov. 4, 2004, which also is a divisional application of U.S. patent application Ser. No. 11/023,569 filed on Dec. 29, 2004. 
     
    
     TECHNICAL FIELD 
       [0002]    The present disclosure relates to a structure of thermal resistive layer and the method of forming the same. More particularly, the disclosure relates to utilize a plurality of oxides of hollow structure to form a thermal resistive layer on a plastic substrate to prevent the substrate from damage caused by the heat generated during manufacturing process. 
       BACKGROUND 
       [0003]    There are two important aspects while developing the future flat display, one is how to manufacture a flexible, light, and thin display panel, and the other is how to manufacture electronic elements with higher electrons mobility and higher response speed for display panel. But the conventional flat displays are using the glass material as base substrates, which is superior in large area manufacturing and mass production; however, the feature of light, thin and flexible may be difficult to be put into practice for glass substrate, therefore, finding an appropriate material is essential. As to the other aspect, Low Temperature PolySilicon, i.e. LTPS technology, can achieve the objective; therefore, the thin film transistors formed by process of LTPS gradually becomes a solution to be substituted for the process forming amorphous thin film transistors. 
         [0004]    Among the materials nominated for the purpose to make a flexible, light, and thin display, plastic substrate is substantially win the engineers&#39; gaze, nevertheless, some plastic substrate may not withstand the damage caused by heat generated during the manufacturing process in LTPS manufacturing process. This is because, during such process, a laser annealing with processing temperature more than 600-Celsius degree, which is almost higher than the glass transition temperature of plastic substrate, is necessary to be utilized to transform the amorphous silicon into poly-crystalline silicon. 
         [0005]    Although some plastic substrates may not be capable of bearing such high temperature, overall speaking, compared with other materials, the plastic substrates still have many merits that engineers can&#39;t give up; therefore, there are still many efforts that scientists and engineers dedicate to carry on such as U.S. Pat. No. 5,817,550 and U.S. Pat. No. 6,680,485. In the U.S. Pat. No. 5,817,550, it disclosed a method utilizing a low energy laser, which is to form poly-crystalline silicon on a plastic substrate. In such method, at first, a silicon dioxide is formed on a plastic substrate, and then an amorphous layer was deposited on said silicon dioxide layer. Subsequently, a short-pulse XeC1 Excimer Laser (308 nm) is used to transform said amorphous silicon layer into poly-crystalline silicon in no more than 100 ns. Another U.S. Pat. No. 6,680,485 discloses a method utilizing a low energy laser to form poly-crystalline silicon on a low-temperature plastic substrate, wherein a specific thickness around 0.1 to 5.0 micrometer of silicon dioxide is formed, and then a specific thickness around 10 to 500 nanometer is formed on said silicon dioxide layer. Subsequently, a short-pulse XeC1 Excimer Laser (308 nm) is used to transform said amorphous silicon layer into poly-crystalline silicon with processing temperature no more than 250-Celsius degree. 
         [0006]    Hence, it is necessary to develop a structure of thermal resistive layer for plastic substrate and manufacturing method. 
       SUMMARY 
       [0007]    The prevent disclosure discloses a method for forming a structure of thermal resistive layer on a plastic substrate comprising the steps of: 
         [0008]    forming a material layer on said plastic substrate; 
         [0009]    transforming said material layer into a porous template layer with a specific thickness by anodizing ; and 
         [0010]    forming a buffer layer on said porous template layer. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The drawings, incorporated into and form a part of the disclosure, illustrate the embodiments and method related to this disclosure and will assist in explaining the detail of the disclosure. 
           [0012]      FIG. 1A  is a cross-section view illustrating a preferred embodiment according to the principle of the disclosure. 
           [0013]      FIG. 1B  is a cross-section view illustrating another preferred embodiment according to the principle of the disclosure. 
           [0014]      FIG. 2A  is a schematic view illustrating the sphere shape of oxide of hollow structure. 
           [0015]      FIG. 2B  is a schematic view illustrating the disk shape of oxide of hollow structure. 
           [0016]      FIG. 2C  is a schematic view illustrating the column shape of oxide of hollow structure. 
           [0017]      FIG. 3A  through  FIG. 3D  are cross-section views illustrating the forming flow of a preferred embodiment according to the principle of the disclosure. 
           [0018]      FIG. 4A  to  FIG. 4F  are cross-section views illustrating the forming flow of another preferred embodiment according to the principle of the disclosure. 
           [0019]      FIG. 5A  to  FIG. 5F  are cross-section views illustrating the flow forming a type of top gate transistor on a structure of thermal resistive layer formed on a plastic substrate. 
           [0020]      FIG. 6A  to  FIG. 6F  are cross-section views illustrating the flow forming a type of bottom gate transistor on a structure of thermal resistive layer formed on a plastic substrate. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    Referring to  FIG. 1A , the figure is a cross-section view illustrating a preferred embodiment according to the principle of the disclosure. The prevent disclosure discloses a structure of thermal resistive layer  1  comprising a plastic substrate  11 , a porous layer  12 , including a plurality of oxides of hollow structure  121 , and a buffer layer  13 , which is silicon dioxide in this embodiment. The oxides of hollow structure  121  are materials selected from a group consisting of silicon oxide, titanium oxide, zinc oxide, and aluminum oxide and the shape of said oxides of hollow structure  121  are structures selected from a group consisting of sphere  32   a , as illustrated in  FIG. 2A , disk  32   b , as illustrated in  FIG. 2B , column  32   c , as illustrated in  FIG. 2C , wherein distribution of said column shape  32   c  of said oxides of hollow structure  121  can be selected from a group consisting of standing and lying flat on said plastic substrate. By means of utilizing said porous layer  12 , the damage, caused by heat generated from manufacturing process, to said plastic substrate  11  can be prevented. 
         [0022]    Please continuing to refer to  FIG. 1B , the figure is a cross-section view illustrating another preferred embodiment according the principle of the disclosure. The embodiment according to this disclosure discloses a structure of thermal resistive layer  2  comprising a plastic substrate  21 , a conductive layer  22 , substantially a material of indium tin oxide (ITO) in this embodiment to increase uniformity of a porous layer  24  that will be mentioned later, formed on said plastic substrate  21 , a template layer  23 , a material selected from a group consisting of silicon, titanium, zinc and aluminum, formed on said conductive layer  22 , a porous layer  24 , including a plurality of oxides of hollow structure  241  and being selected from a group consisting of silicon oxide, zinc oxide, titanium oxide, and aluminum oxide, formed on said template layer  23 , a planarization layer  25 , formed on said porous layer  24  so as to smooth the surface of said porous layer  24 , and a buffer layer  26 , substantially a material of silicon dioxide, formed on said planarization layer  25 , which is a material selected from the group consisting of polymer, and inorganic materials. 
         [0023]    From the content described above, it is easy to understand the structure of thermal resistive layer according to the present disclosure. In the following description, the manufacturing method to form said structure is disclosed in detail. 
         [0024]    Please referring to the  FIG. 3A  through  FIG. 3D , the figures are cross-section views illustrating the forming flow of a preferred embodiment according to the principle of the disclosure. The process, forming a structure of thermal resistive layer, comprising the following steps starting from the step shown in  FIG. 3A , an anodized template  41  including a plurality of mold holes  41  a is provided, wherein said anodized template is a material selected from the group consisting of silicon, titanium, zinc and aluminum. Then the process continues to the step shown in  FIG. 3B , wherein a plurality of oxides of hollow structure  43  are formed in said plurality of mold holes  41   a  of said anodized template  41  through the process of electrochemistry, chemical vapor deposition (CVD), or sol-gel. Said oxide of hollow structure is a material selected from the group consisting of silicon oxide, titanium oxide, zinc oxide, and aluminum oxide and the shape of said oxide of hollow structure is selected from the group consisting of sphere, column, and disk. Afterwards, said anodized template  41  is removed, as shown in  FIG. 3C , by etching. The process continues to the step shown in  FIG. 3D , wherein said oxides of hollow structure  43  are processed by sol-gel and then are coated on said plastic substrate  44  by spin coating to form a porous layer  45 . Finally, a buffer layer  46  is formed on said porous layer  45 , wherein said buffer layer is substantially a silicon oxide. 
         [0025]    Please referring to the  FIG. 4A  through  FIG. 4F , the figures are cross-section views illustrating the forming flow of another preferred embodiment according to the principle of the disclosure. For more detail, the process, forming a structure of thermal resistive layer, is illustrated and explained in the following description. The process starts from providing a plastic substrate  51 , shown in  FIG. 4A , then, as shown in  FIG. 4B , a conductive layer  52  formed on said plastic substrate  51  is implemented. In this embodiment, said conductive layer  52  is substantially a material of indium tin oxide (ITO). The process proceeds to the step shown in  FIG. 4C , wherein a material layer  53  is formed on said conductive layer  52 . Said material layer  53  is a material selected from the group consisting of silicon, titanium, zinc, and aluminum; thereafter, as shown in  FIG. 4D , said material layer  53  is transformed into a porous template layer  54  with a plurality of oxides of hollow structure  54   a  by anodizing, wherein said oxides of hollow structure  54   a  are material selected from the group consisting of silicon oxide, titanium oxide, zinc oxide, and aluminum oxide and the shape of said oxides of hollow structure  54   a  are selected from the group consisting of sphere, column, and disk. In order to increase adhesion of said oxides of hollow structure  54   a , a plate  54   b , transformed from said material layer  53  by anodizing, with a specific thickness is kept. The process continue to the step shown in  FIG. 4E , wherein a planarization layer  56 , a material selected from the group consisting of polymer, and inorganic material, is formed through spin coating on said porous template layer  54 . Finally, as illustrated in  FIG. 4F , said buffer layer  57  is formed on said planarization layer  56 , wherein said buffer layer  57  is substantially a silicon oxide. The purpose to form said conductive layer  52  is to increase uniformity of said porous template layer  54  and to ensure said material layer  53  to be completely oxidized during anodizing. 
         [0026]    In the following explanation, two examples are illustrated to help understand how to form a poly-crystalline silicon thin film transistor on plastic substrate. 
         [0027]    Please referring to  FIG. 5A  through  FIG. 5F , these figures are cross-section views illustrating the flow forming a type of top gate transistor on a structure of thermal resistive layer formed on a plastic substrate. The example illustrates the progress of the flow to form a top gate transistor. As illustrated in  FIG. 5A , a porous layer  62 , having surface roughness under 5 nanometer and also including a plurality of oxides of hollow structure  62   a , is formed on a plastic substrate  61  so as to prevent said plastic substrate  61  from heat damage caused during processing and, on the other hand, to smooth the surface of said plastic substrate  61  so that electronic devices can be manufactured without any problem. Afterwards, as illustrated in  FIG. 5B , a buffer layer  63  is formed on said porous layer  62 , and then an amorphous silicon layer  64  is formed on said buffer layer  63 . Next, as shown in  FIG. 5C , said amorphous silicon layer  64  is transformed into poly-crystalline silicon layer  65  through the laser annealing  9 . 
         [0028]    Referring to  FIG. 5D , by means of ion implanting, a pair of source/drain region  65   a  is formed by selecting N-type doped or P-type doped on said poly-crystalline silicon layer  65 . Thereafter, as illustrated in  FIG. 5E , a gate dielectric layer  66  is deposited and then a gate metal electrode  67  is formed. Afterwards, as shown in  FIG. 5F , an interlayer  68  is formed and then contact holes opposite to the said pair of source/drain regions  65   a  are formed so that metal interconnect  69  can be formed. The purpose of forming said buffer layer  63  is to assist nucleation reaction of silicon seeds to be formed easily on said buffer layer  63  so that forming said amorphous silicon layer  64  would become more smoothly, and to prevent the impurities in the layers formed before said buffer layer  63  from penetrating into said amorphous layer  64 . 
         [0029]    Please referring to  FIG. 6A  through  FIG. 6F , these figures are cross-section views illustrating the flow forming a type of bottom gate transistor on a structure of thermal resistive layer formed on a plastic substrate. The following example illustrated the progress of the flow to form a bottom gate transistor. As illustrated in  FIG. 6A , a porous layer  72 , having surface roughness under 5 nanometer and also including a plurality of oxides of hollow structure  72   a , is formed on a plastic substrate  71  to prevent said plastic substrate  71  from heat damage caused by processing and, on the other hand, to smooth the surface of said plastic substrate  71  so that electric devices can be manufactured without any problem. Afterwards, as illustrated in  FIG. 6B , a buffer layer  73  is formed on said porous layer  72 . 
         [0030]    In the next step, as shown in  FIG. 6C , a gate metal electrode layer  74  is formed, and then a gate dielectric layer  75  is deposited on said gate metal electrode layer  74 . Afterwards an amorphous layer  76  is formed on said gate dielectric layer  75 . Referring to  FIG. 6D , said amorphous silicon layer  76  is transformed into poly-crystalline silicon layer  77  through the laser annealing  9 . Subsequently, as illustrated in  FIG. 6E , by means of ion implanting, pair of source/drain regions  77   a  are formed by selecting N-type doped or P-type doped on said poly-crystalline silicon layer  77 . Thereafter, as shown in  FIG. 6F , an interlayer  78  is formed subsequently, and then contact holes opposite to the said pair of source/drain regions  77   a  are formed so that metal interconnect  79  can be formed. The purpose of forming said buffer layer  73  is to assist nucleation reaction of silicon seeds to be formed easily on said buffer layer  73  so that forming said amorphous silicon layer  76  would become more smoothly, and to prevent the impurities in the layers formed before said buffer layer  73  from penetrating into said amorphous layer  76 . 
         [0031]    The disclosed embodiments provide a structure of thermal resistive layer and the method of forming the same, utilizing oxides of hollow structure to form a thermal resistive layer on a plastic substrate, to increase the capability of heatproof, so as to achieve the objective of forming PolySilicon thin film on the plastic substrate. 
         [0032]    The disclosed embodiments also provide a structure of thermal resistive layer and the method of forming the same, utilizing oxides of hollow structure formed on a plastic substrate, so as to achieve the objective of making thin film transistor flat display with characteristics of tiny, light, thin and flexible. 
         [0033]    The disclosed embodiments further provide a structure of thermal resistive layer and the method of forming the same, making high efficiency electronic elements, so as to lower manufacturing cost. 
         [0034]    The disclosed embodiments still further provide a structure of thermal resistive layer and the method of forming the same, a porous layer is formed to smooth the surface of the plastic substrate. 
         [0035]    While the present disclosure has been described and illustrated herein with reference to the preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and the scope of the disclosure.