Abstract:
A programmable edge defined output buffer clocks a first logic state to a first node when an input signal is in a first condition and a second logic state to a second node when the input signal is in a second condition. A programmable coupling circuit is programmable to couple the first and second nodes to an input of an amplifier. The programming selection determines in response to which signals will the first and second nodes be coupled to the input of the amplifier.

Description:
FIELD OF THE INVENTION 
     The subject invention relates to synchronization circuits, and more particularly, to programmable edge defined output buffer circuits. 
     BACKGROUND OF THE INVENTION 
     In synchronizing signal outputs, it has been found desirable to clock different logic states on different clocks. A certain signal may be a logic high or a logic low, but is to be received only at certain predetermined times. When that predetermined time is may actually depend on what the logic state of the signal is. For example, it may be desirable to receive the signal on a first clock if the signal is a logic high, but on a second signal if the signal is a logic low. U.S. Pat. No. 4,379,241, Pumo, teaches an edge defined output buffer for achieving this result. In designing a large scale integrated circuit, there may be numerous such situations in which signals are to be clocked but at different times depending on the logic state. Some such signals may have the logic high clocked on a first clock, and the logic low on a second clock. Whereas, other such signals would have the low clocked on the first clock, and the logic high clocked on the second clock. Furthermore, in the course of design, changes may be made as to when such logic states are clocked. These changes may in fact occur relatively late in the design. Such changes can cause costly delays, particularly in laying out the integrated circuit. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide an improved edge defined output buffer. 
     Another object of the invention is to provide an edge defined output buffer with improved flexibility. 
     Yet another object of the invention is to provide an edge defined output buffer with programmable edge selectivity. 
     These and other objects of the invention are achieved in a programmable output buffer. A first coupling circuit couples a first logic state to a first node when a first signal is in a first condition. A second coupling circuit couples a second logic state to a second node when the first signal is in a second condition. An output amplifier has an input and an output. A first programming terminal is capable of being programmed to be coupled to the input of the amplifier. A second programming terminal is capable of being programmed to be coupled to the input of the amplifier. A third coupling circuit couples the first logic state from the first node to the first programming terminal in response to a first clock signal. A fourth coupling means couples the second logic state from the second node to the second programming terminal in response to a second clock signal. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a programmable edge defined output buffer according to a preferred embodiment of the invention; and 
     FIG. 2 is a table showing the programming permutations of the programmable buffer of FIG. 1. 
    
    
     DESCRIPTION OF THE INVENTION 
     Shown in FIG. 1 is a programmable edge defined output buffer 10 comprised of a transistor 11, a transistor 12, a transistor 13, a transistor 14, a transistor 15, a transistor 16, a transistor 17, an inverter 18, a programmable connecting line 19, a programmable connecting line 20, and an amplifier 21. Transistors 11-17 are N channel insulated gate field effect transistors (IGFETs). Transistors 12-14 are natural transistors having a threshold voltage very near zero volts. Transistors 11 and 15-17 are enhancement mode transistors having a threshold voltage between 0.6 and 0.8 volt. 
     Transistor 11 has a control electrode for receiving a clock signal PH1, a first current electrode for receiving an input signal VI, and a second current electrode connected to a node 22. Transistor 11 takes advantage of the bilateral nature of IGFETs by having the first and second current electrodes each vary between functioning as a source or drain. Inverter 18 has an input connected to node 22, and an output. Transistor 12 has a control electrode connected to the output of inverter 18, a drain connected to a positive power supply terminal for receiving, for example, 5 volts, and a source connected to a node 23. Programmable connecting line 19 is a conductor, such as polysilicon or aluminum, connected between node 23 and a programming terminal 24. Transistor 13 has a drain connected to node 23, a gate for receiving a clock signal CA, and a source connected to a programming terminal 25. Transistor 14 has a drain connected to node 23, a gate for receiving a clock signal CB, and a source connected to a programming terminal 26. Programmable connecting line 20 is a conductor, such as polysilicon or aluminum, connected between a node 27 and a programming terminal 28. Transistor 15 has a gate for receiving signal CB, a drain connected to a programming terminal 29, and a source connected to a node 27. Transistor 16 has a drain connected to a programming terminal 30, a gate for receiving signal CA, and a source connected to node 27. Transistor 17 has a drain connected to node 27, a gate connected to node 22, and a source connected to ground. Amplifier 21, has an input connected to a programming terminal 31 for receiving an output signal VO, and an output for providing a buffered output signal BVO. 
     When the condition of clock signal PH1 is a logic high, signal VI is coupled to node 22. When node 22 is a logic high, transistor 17 is conducting, causing node 27 to be a logic low, and inverter 18 provides a logic low to transistor 12 causing transistor 12 to be non-conducting. Transistor 12 in such case does not effect the logic state at node 23. When node 22 is a logic low, inverter 18 provides a logic high to transistor 12 causing transistor 12 to provide a logic high at node 23, and transistor 17 is not conducting so that the logic state at node 27 is not effected by transistor 17. Signal PH1 at a logic high is considered a PH1 time. Consequently, during PH1 time, if the condition of signal VI is a logic high, node 27 is a logic low, and node 23 is unaffected. During a PH1 time in which the condition of signal VI is a logic low, node 23 is a logic high, and node 27 is unaffected. Programming terminals 24-26 and 28-30 are selectively connected to terminal 31 to determine when signal VO becomes the inverse of the logic state of signal VI. Terminals 24-26 are used for selecting when signal VO will become a logic high in the cases in which node 23 is a logic high. Terminals 28-30 are used for selecting when signal VO will become a logic low in the cases in which node 27 is a logic low. 
     For the case in which node 23 is a logic high, connecting programming terminal 24 to programming terminal 31 will cause signal VO to be a logic high in response to signal PH1 switching to a logic high. Connecting programming terminal 25 to programming terminal 31 will result in signal VO becoming a logic high when signal CA switches to a logic high. Connecting programming terminal 26 to programming terminal 31 will result in signal VO becoming a logic high when signal CB switches to a logic high. Both programming terminals 25 and 26 can be connected to programming terminal 31 to result in signal VO becoming a logic high when either signal CA or CB switches to a logic high. 
     For the case in which node 27 is a logic low, connecting programming terminal 28 to programming terminal 31 results in signal VO becoming a logic low when signal PH1 becomes a logic low. Connecting programming terminal 29 to programming terminal 31 results in signal VO becoming a logic low when signal CB switches to a logic low. Connecting programming terminal 30 to programming terminal 31 results in signal VO becoming a logic low when signal CA switches to a logic low. Both programming terminals 29 and 30 can be connected to programming terminal 31 to result in signal VO becoming a logic low when either signal CA or signal CB switches to a logic high. 
     Terminals 24-26 and 28-30 can be programmed to be connected to terminal 31 by any conventional technique. Such techniques include using polysilicon metal to connect selected transistor output of transistors 12, 13, 14, 15, 16, and 17 to the input of amplifier 21. Another technique is to have the drains of selected transistors 15-17 formed in a common region of the substrate with sources of selected transistors 12-14. Such common region is then connected by metal or polysilicon to the input of amplifier 31. Unselected sources and drains would remain distinct regions. Field oxide would separate regions not selected to be in the common region. Furthermore, any of unselected transistors 13-16 need not even be formed. 
     Thus it is shown that an input signal, signal VI, can be clocked on various clock edges. Signal VI is clocked in inverted form as signal VO and further buffered by amplifier 21 to become signal BVO. Logic low signal VI is clocked to the input of amplifier 21 as a logic high by signal PH1 being a logic high when the source of transistor 12 is programmed to be connected to the input of amplifier 21; by signal PH1 being a logic high and signal CA being a logic high when the source of transistor 13 is programmed to be connected to the input of amplifier 21; by signal PH1 and signal CB being a logic high when the source of transistor 14 is programmed to be connected to the input of amplifier 21; and by signal PH1 and either signal CA or signal CB when the sources of transistors 13 and 14 are programmed to be connected to the input of amplifier 21. Logic high signal VI is clocked to the input of amplifier 21 by signal PH1 being a logic high when the drain of transistor 17 is programmed to be connected to the input of amplifier 21; by signal PH1 and signal CA being a logic high when the drain of transistor 16 is programmed to be connected to the input of amplifier 21; by signal PH1 and signal CB when the drain of transistor 15 is programmed to be connected to the input of amplifier 21; and by signal PH1 and either signal CA or signal CB when the drains of transistors 15 and 16 are programmed to be connected to the input of amplifier 21. These programming permutations are shown in a table in FIG. 2. 
     For the embodiment shown in FIG. 1, signal PH1 is of sufficiently high frequency that capacitance of node 22 is sufficient to maintain the logic state thereat when signal PH1 is a logic low. The logic state of node 22 can change only when signal PH1 is a logic high. If necessary, node 22 could be latched. This could be achieved by a conventional retainer circuit. One way would be to have a small inverter with an input connected to the output of inverter 18, and an output connected to node 22. Because node 22 retains its logic state while signal PH1 is a logic low, signal VO can change state after signal PH1 switches to a logic low. Because node 22 can only change state when signal PH1 is a logic high, signal PH1 is still required to be a logic high to effect a logic state change on signal VIO although the actual logic state change of signal VO may occur after the following logic low of signal PH1.