Abstract:
A decoder circuit for decoding different combinations of supplied original input address bits, comprising at least one predecode circuit responsive to the original input address bits for producing predecoded signal bits from the input address bits, and a plurality of decoder units including at least one decoder unit responsive to at least two different combinations of the original input address bits, wherein the decoder units comprises a decoder unit responsive to selected ones of the predecoded signal bits alone and a decoder unit responsive to at least one of the predecoded signal bits and at least one of the original input address bits.

Description:
FIELD OF THE INVENTION 
     The present invention relates to semiconductor devices and, more particularly, to a decoder circuit for use in a semiconductor memory device such as a read-only memory (ROM) or a random-access memory (RAM) which per se is well known in the art. 
     BACKGROUND OF THE INVENTION 
     A certain type of address decoder circuit for use in a semiconductor memory device such as a ROM or RAM device consists of decoder units of a number less than the number of the possible combinations of the bits forming an address signal to be supplied to the decoder circuit. A typical example of such a decoder circuit is the one used for a ROM device which is incorporated in a microprocessor to store microprogramming codes therein. Such a decoder circuit is directly responsive to the original input address signals so that, where each of the original input address signal consists of six bits, a maximum of 2 6  =64 different combinations or sequences of bits could be used in the decoder circuit. In comparison with such a large number of possible decoder outputs, the decoder circuit actually has a far smaller number of outputs such as, for example, only twelve outputs and, for this reason, requires the provision of a disproportionately large number of active devices or transistors. Such a large number of active devices used in the decoder circuit inevitably results in correspondingly large amounts of capacitances provided by the diffusion regions of the individual active devices and accordingly in reduction in the switching speed achievable of the decoder circuit. 
     An address decoder circuit of the described type thus sometimes uses a predecode scheme for the purpose of reducing the number of the transistors to be used in the decoder circuit and thereby increasing the switching speed achievable of the circuit. The decoder circuit to implement such a scheme comprises a suitable number of 2-bit predecode circuits which are directly responsive to the original input signal bits. Each of these 2-bit predecode circuits is operative to predecode neighboring two of the original input address bits by producing a total of four different logic ANDs of the two bits and the inverted versions of the two bits. The predecoded signal bits thus produced by the 2-bit predecode circuits are used in some of the decoder units so that only one of the two original input address bits which have resulted in each of the predecoded signal bits is effective in the particular decoder unit with the other of the two bits virtually neglected from use. The result is accordingly that there exits address bits which are not used in the decoder circuit. Such a scheme of the decoder circuit inevitably results in irregularities in the geometrical topology of the decoder circuit fabricated on a semiconductor chip. 
     It is, thus, an important object of the present invention to provide an improved decoder circuit which is composed of a minimized number of active devices to achieve an increased switching speed of the decoder circuit. 
     It is another important object of the present invention to provide an improved predecode decoder circuit which effectively uses the original input address bits supplied to the decoder circuit. 
     SUMMARY OF THE INVENTION 
     In accordance with one outstanding aspect of the present invention, there is provided a decoder circuit for decoding different combinations of supplied original input signal bits, comprising (a) at least one predecode circuit responsive to the original input signal bits for producing predecoded signal bits from the input signal bits, and (b) a plurality of decoder units including at least one decoder unit responsive to at least two different combinations of the original input signal bits, characterized in that the decoder units comprises a decoder unit responsive to the combination of at least one of the predecoded signal bits and at least one of the original input signal bits. 
     In accordance with another outstanding aspect of the present invention, there is provided a decoder circuit for decoding different combinations of supplied original input signal bits, comprising (a) at least one predecode circuit responsive to the original input signal bits for producing predecoded signal bits from the input signal bits, and (b) a plurality of decoder units including at least one decoder unit responsive to at least two different combinations of the original input signal bits, wherein the decoder units comprises a decoder unit responsive to selected ones of the predecoded signal bits alone and a decoder unit responsive to at least one of the predecoded signal bits and at least one of the original input signal bits. 
     In accordance with still another outstanding aspect of the present invention, there is provided a semiconductor decoder circuit including a plurality of decoder units for decoding different combinations of supplied original input signal bits, comprising (a) a first set of signal lines formed on a semiconductor structure, the first set of signal lines comprising a first group of signal lines connected to a source of a first predetermined voltage and a second group of signal lines connected to a source of a second predetermined voltage, (b) a second set of signal lines formed on a semiconductor structure and extending substantially at right angles to the first set of signal lines, the second set of signal lines comprising a third group of signal lines respectively responsive to predecoded signal bits predecoded from selected ones of the original input signal bits and a fourth group of signal lines respectively responsive to selected ones of the original input signal bits, (c) a first set of field-effect transistors selectively connected in series to the source of the first predetermined voltage along each of the signal lines of the first group, each of the first set of field-effect transistors being of one channel conductivity type, and (d) a second set of field-effect transistors selectively connected in parallel to the source of the second predetermined voltage along each of the signal lines of the second group, each of the second set of field-effect transistors being of the channel conductivity type opposite to the one channel conductivity type, each of the second set of field-effect transistors having their gates selectively connected to the signal lines of the third and fourth groups, (e) the first set of field-effect transistors arranged along each of the signal lines of the first group and the second set of field-effect transistors arranged along each of the signal lines of the second group implementing each of the decoder units. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The drawbacks of a prior-art address decoder circuit and the features and advantages of a decoder circuit according to the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which: 
     FIG. 1 is a circuit diagram showing a typical known example of an address decoder circuit used for a ROM device storing microprogramming codes in a microprocessor; 
     FIGS. 2A and 2B are address maps depicting the schedules in accordance with which the decoder units of the decoder circuit shown in FIG. 1 are to produce output signal bits in response to the original address bits input to the decoder circuit, FIG. 2A showing such schedules in non-matrix form and FIG. 2B showing similar schedules in matrix form; 
     FIG. 3 is a circuit diagram showing a preferred example of an address decoder circuit which implements a two-bit predecode scheme; 
     FIG. 4 is a schematic diagram showing the logical configuration of a preferred embodiment of a decoder circuit according to the present invention; and 
     FIG. 5 is a circuit diagram showing a preferred example of the circuit arrangement implementing the logical configuration of the embodiment illustrated in FIG. 4. 
    
    
     DESCRIPTION OF THE PRIOR ART 
     As has been noted at the outset of the description, a certain type of address decoder circuit for use in a semiconductor memory device consists of decoder units of a number less than the number of the possible combinations of the bits forming an address signal to be supplied to the decoder circuit. FIG. 1 of the drawings shows a typical example of such a decoder circuit. The decoder circuit herein shown is used for a ROM device incorporated in a microprocessor for storing microprogramming codes therein and is by way of example assumed to be designed for use with a 12-word ROM device (not shown). The decoder circuit is made up of a number of n-channel field-effect transistors respectively denoted by N 01  to N 27  and p-channel field-effect transistors respectively denoted by P 01  to P 27 . These n-channel and p-channel N 01  to N 27  and P 01  to P 27  are arranged to form twelve decoder units D 0 , D 1 , D 2 , ... D 11  each including a plurality of full CMOS (complementary metal-oxide-semiconductor) inverters implemented by the field-effect transistors N 01  to N 27  and P 01  to P 27 . The decoder units D 0 , D 1 , D 2 , ... D 11  further include logic inverters I 0  to I 11 , respectively, which provide output address bits of the individual decoder units D 0  to D 11 , respectively. The decoder units D 0  to D 11  are responsive directly to original, viz., supplied address signals through a total of twelve signal input lines which consist of six lines respectively responsive to supplied address bits A 0  to A 5  and six lines respectively responsive to the inverted versions A 0  to A 5  of the supplied address bits A 0  to A.sub. 5. Each of the decoder units D 0  to D 11  consists of n-channel MOS field-effect transistors connected in series between ground and each of the logic inverters I 0  to I 11  and p-channel MOS field-effect transistors connected in parallel between a source of a supply voltage V CC  and each of the inverters I 0  to I 11  as shown. The logic inverters I 0  to I 11  of the decoder units D 0  to D 11  are respectively connected to the word lines of the memory cell array (not shown). 
     The n-channel field-effect transistors N 01  to N 27  and p-channel field-effect transistors P 01  to P 27  forming the decoder circuit are arranged so that the individual decoder units D 0  to D 11  of the decoder circuit are operative to produce output address bits O 1  to O 11  in response to the supplied address bits A 0  to A 5  and A 0  to A 5  in accordance with the schedules represented by an address map depicted in non-matrix form in FIG. 2A and in matrix form in FIG. 2B. The sign &#34;X&#34; in the non-matrix address map shown in FIG. 2A indicates an indeterminate or variable bit which may be of either logic &#34;0&#34; or &#34;1&#34; value. In the matrix address map shown in FIG. 2B, the axis of abscissa represents binary digits 000, 001, 011, . . . 111 (increasing from left to right) coded by the lower three of the six supplied address bits A 0 , A 1 , A 2 , ... A 5  while the axis of ordinate represents binary digits (000, 001, 011, . . . 111 (increasing downwardly) coded by the upper three of the address bits A 0  to A 5 . As will be seen from these address maps, each of the decoder units D 2  and D 7  of the address decoder circuit is operable for selecting one of two different sequences of address bits 000010 and 000011 (D 2 ) or 100100 and 100101 (D 7 ). On the other hand, each of the decoder units D 3  and D 6  is operable for selecting any one of four different sequences of address bits 000000, 000001, 000010 and 000011 (D 3 ) or 100000, 100001, 100011 (D 6 ). Furthermore, each of the decoder units D 4 , D 5 , D 11  and D 12  is operable for selecting any one of a total of eight different sequences of address bits. 
     When an original input signal A 0  A 1  A 2  A 3  A 4  A 5  in the form of, for example, 00001X is supplied to the decoder circuit shown in FIG. 1, all the n-channel field-effect transistors N 13 , N 14 , N 15 , N 16  and N 17  forming part of the decoder unit D 2  are turned on and all the associated p-channel field-effect transistors P 13 , P 14 , P 15 , P 16  and P 17  of the decoder unit D 2  remain in non-conduction states. Under this condition, the decoder unit D 2  produces a logic &#34;1&#34; bit at the output terminal of the inverter I 2  as the output signal bit O 2  of the decoder unit D 2 . 
     The known address decoder circuit thus constructed is directly responsive to the original input address signals, each of which consists of six bits yielding a maximum of 2 6  =64 different combinations or sequences of bits. In comparison with such a large number of possible decoder outputs, the decoder circuit actually has only twelve outputs and, as a corollary of this, necessitates a disproportionately large number of active devices or transistors. As a matter of fact, the decoder unit D 0  which uses all the supplied address bits A 0 , A 1 , A 2 , . . . A 5  available is composed of a total of twelve transistors which consist of the three series connected n-channel field-effect transistors N 01  to N 06  and the three parallel connected p-channel field-effect transistors N 01  to N 06  and P 01  to P 06 . Even each of the decoder units D 10  and D 11  (as well the decoder units D 5  and D 6 , not shown) which uses the minimum number of input address bits is composed of a total of six field-effect transistors N 22  to N 24  and P 22  to P 24  or N 25  to N 27  and P 25  to P 27 . Such a large number of field-effect transistors used in the decoder circuit inevitably results in correspondingly large amounts of capacitances provided by the source and drain diffusion regions of the transistors and accordingly in reduction in the switching speed achievable of the decoder circuit. This drawback of a known address decoder circuit is pronounced in a static decoder circuit implemented by full CMOS configuration as in the case of the prior-art decoder circuit shown in FIG. 1. Whichever of NAND-based logics or NOR-based logics may be adopted in such a full CMOS address decoder circuit, either the n-channel field-effect transistors or the p-channel field-effect transistors implementing the decoder circuit must be connected in series. The larger the number of the series connected field-effect transistors, the lower the performance efficiencies of the individual transistors and accordingly the lower the switching speed of the entire decoder circuit. 
     Thus, an address decoder circuit of the type shown in FIG. 1 sometimes uses a predecode scheme for the purpose of reducing the number of the transistors to be used in the decoder circuit and thereby increasing the switching speed achievable of the circuit. FIG. 3 of the drawings shows a preferred example of an address decoder circuit which implements such a predecode scheme. 
     The decoder circuit herein shown is arranged to produce output address bits O 0  to 0 11  responsive to original input address bits A 0 , A 1 , A 2 , . . . A 5  also in accordance with the schedules represented by the address map of FIGS. 2A or 2B. The decoder circuit is also assumed to comprise a total of twelve decoder units including the shown decoder units D 2 , D 10  and D 11  which are formed by n-channel field-effect transistors N 28  to N 36  and p-channel field-effect transistors P 28  to P 36  and which include logic inverters including the inverters I 2 , I 10  and I 11 , respectively. The decoder circuit further comprises first, second and third 2-bit predecode circuits PD 1 , PD 2  and PD 3  which are directly responsive to the original input signal bits A 0 , A 1 , A 2 , ... A 5 . Each of these 2-bit predecode circuits PD 1 , PD 2  and PD 3  is operative to predecode neighboring two bits (A 2i  and A 2i+1  where i=0, 1 or 2) of the supplied original input address bits A 0 , A 1 , A 2 , . . . A 5 . The first 2-bit predecode circuit PD 1  is responsive to the lower two A 0  and A 1  of the original input address bits A 0 , A 1 , . . . A 5  to produce four different output bits B 00 , B 01 , B 02  and B 03  respectively representative of the logic ANDs A 0  ·A 1 , A 0  ·A 1  ·A 0  ·A 1  and A 0  ·and 1 of the input bits A 0  and A 1  and the respective inverted versions thereof. The second 2-bit predecode circuit PD 2  is responsive to the intermediate two A 2  and A 3  of the original input address bits A 0  to A 5  to produce four different output bits B 10 , B 11 , B 12  and B 13  respectively representative of the logic ANDs A 2  ·A 3 , A 2  ·A 3 , A 2  ·A 3  of the input bits A 2  and A 3  and the respective inverted versions thereof. The third 2-bit predecode circuit PD 3  is responsive to the intermediate two A 4  and A 5  of the original input address bits A 0  to A 5  to produce four different output bits B 20 , B 21 , B 22  and B 23  respectively representative of the logic ANDs A 4  ·A 5 , A 4  ·A 5 , A 4  ·A 5  and A 4  ·A 5  of the input bits a4 and A 5  and the respective inverted versions thereof. 
     When an original input signal A 0  A 1  A 2  A 3  A 4  A 5  in the form of, for example, 00001X is supplied to the decoder circuit thus constructed and arranged, the output bits B 02 , B 03 , B 10  and B 20  respectively representative of the logic ANDs A 0  ·A 1 , A 0  ·A 1 , A 2  ·A 3  and A 4  ·A 5  of the supplied address bits assume logic &#34;X&#34;, &#34;X&#34;, &#34;1&#34; and &#34;1&#34; states. Of the field-effect transistors forming part of the decoder unit D 2 , for example, of the circuit shown in FIG. 3, the series connected n-channel field-effect transistors N 30  and N 31  and one of the parallel connected n-channel field-effect transistors N 28  and N 29  are thus turned on and the series connected p-channel field-effect transistors P 30  and P 31  and one of the parallel connected p-channel field-effect transistors P 28  and P 29   are held in non-conduction states. Under this condition, the decoder unit D 2  produces a logic &#34;1&#34; signal at the output terminal of the inverter I 2  as the output signal bit O 2  of the decoder unit D 2  as in the prior-art address decoder circuit shown in FIG. 1. 
     In the decoder unit D 2  of the circuit shown in FIG. 3, the predecoded signal bits B 02  and B 03  produced by the first 2-bit predecode circuit PD 1  are supplied to the parallel combination of the n-channel field-effect transistors N 28  and N 29  of the decoder unit D 2  to produce a logic sum or OR, viz., (A 0  ·A 1  +A 0  ·A 1 )=A 1  of the supplied bits. The predecoded signal bits B 02  and B 03  are also supplied to the series combination of the p-channel field-effect transistors P 28  and P 29  of the decoder unit D 2  to produce a logic OR, viz., (A 0  ·A 1 )+(A 0  ·A 1 )=A 1  of the supplied bits. Likewise, the predecoded signal bits B 10  and B 12  produced by the second 2-bit predecode circuit PD 2  are supplied to the parallel connected n-channel field-effect transistors N 32  and N 33  and series connected p-channel field-effect transistors P 32  and P 33  of the decoder unit D 10  to produce a logic OR, viz., (A 2  ·A 3  +A 2  ·A 3 )=A 2  and a logic OR, viz., (A 2  ·A 3 )+(A 2  ·A 3 ) =A 2  of the supplied bits. In the decoder unit D 11 , furthermore, a logic OR, viz., (A 2  ·A 3  +A 2  ·A 3 ) =A 2  is produced in response to the predecoded signal bits B 10  and B 12  produced by the second 2-bit predecode circuit PD 2 . 
     In the decoder circuit shown in FIG. 3, the neighboring two A 2i  and A 2i  of the supplied original input address bits A 0 , A 1 , A 2 , ... A 5  are thus predecoded by each of the of 2-bit predecode circuits PD 1 , PD 2  and PD 3  into signal bits B 00  to B 23  each of which is provided by the logic AND of the supplied address bit A 2i  or the inverted version thereof and the supplied address bit A 2i+1  or the inverted version thereof. The predecoded signal bits B 00  to B 23  are used in the decoder units D 2 , D 3 , D 4 , D 5 , D 6 , D 7 , D 10  and D 11  so that only one of the two original input address bits such as, for example, the address bit A 1  for the decoder unit D 2  or the address bit A 2  for the decoder unit D 10  or D 11  is effective in the particular decoder unit. This means that the other of the two bits A 2i  and A 2i  is virtually neglected from use. Such a scheme of the decoder circuit results in irregularities in the geometrical topology of the decoder circuit fabricated on a semiconductor chip because of the fact that the individual decoder units D 0 , D 1 , D 2 , . . . D 11  each of which should be configured by active devices and interconnections patterned with irregularity will differ in topology from one circuit to another. 
     The present invention contemplates elimination of such a problem inherent in a two-bit predecode decoder circuit of the described nature. Accordingly, the goal of the present invention is to provide an improved decoder circuit which is composed of a minimized number of active devices to achieve an increased switching speed of the decoder circuit and which effectively uses the original input address bits supplied to the decoder circuit, as previously noted. 
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 4 of the drawings shows the logical configuration of a preferred embodiment of a decoder circuit according to the present invention. The decoder circuit herein shown is also assumed to be designed for use with a 12-word ROM device (not shown) by way of example and thus comprises twelve decoder units D 0 , D 1 , D 2 , . . . D 11 . The decoder units D 0 , D 1 , D 2 , . . . D 11  in turn comprise two-input and three-input logic NAND gates G 0 , G 1 , G 2 , . . . G 11 , respectively, and logic inverters I 0 , I 1 , I 2 , ... I 11  respectively connected to the output terminals of the NAND gates G 0 , G 1 , G 2 , . . . G 11  to provide output address bits of the individual decoder units D 0  to D 11 . 
     The decoder circuit embodying the present invention further comprises first, second and third 2-bit predecode circuits PD 1 , PD 2  and PD 3  which are directly responsive to original input signal bits A 0 , A 1 , A 2 , . . . A 5  and the inverted versions A 0 , A 1 , A 2 , . . . A 5 , respectively, thereof. Each of these 2-bit predecode circuits PD 1 , PD 2  and PD 3  is operative to predecode neighboring two bits A 2i  and A 2i+1  of the supplied original input address bits A 0 , A 1 , A 2 , . . . A 5  similarly to their counterparts in the decoder circuit described with reference to FIG. 3. Thus, the first 2-bit predecode circuit PD 1  is responsive to the lower two A 0  and A 1  of the original input address bits A 0 , A 1 , . . . A 5  to produce four different output bits B 00 , B 01 , B 02  and B 03  respectively representative of the logic ANDs A 0  ·AHD 1, A 0  ·A 1 , A 0  ·A 1  and A 0  ·A 1  of the input address bits A 0  and A 1  and the respective inverted versions thereof. The second 2-bit predecode circuit PD 2  is responsive to the intermediate two A 2  and A 3  of the original input address bits A 0  to A 5  to produce four different output bits B 10 , B 11 , B 12  and B 13  respectively representative of the logic ANDs A 2  ·A 3 , A 2  ·A 3 , A 2  ·A 3  and A 2  ·A 3  of the input address bits A 2  and a3 and the respective inverted versions thereof. The third 2-bit predecode circuit PD 3  is responsive to the intermediate two A 4  and A 5  of the original input address bits A 0  to A 5  to produce four different output bits B 20 , B 21 , B 22  and B 23   respectively representative of the logic ANDs A 4  ·A 5 , A 4  ·A 5 , A 4  ·A 5  ·A 5  of the input address bits A 4  and A 5  and the respective inverted versions thereof. The decoder circuit thus comprising the twelve NAND gates G 0  to G 11  are responsive to the original input address bits A 0  to A 5  and the respective inverted versions of these bits and to the signal bits B 00  to B 23  through a total of twelve input lines as shown. The individual decoder units D 0  to D 11  are implemented by full CMOS configuration and are operative to produce output address bits O 1  to O 11  in response to the supplied address bits A 0  to A 5  and A 0  to AHD 5 basically also in accordance with the schedules represented by the address maps depicted in FIGS. 2A and 2B. 
     FIG. 5 shows an example of the transistor circuit arrangement implementing the logical configuration of the decoder circuit thus constructed. 
     As shown, the three-input NAND gate G 0  of the decoder unit D 0  comprises three n-channel field-effect transistors N 40 , N 41  and N 42  connected in series between the logic inverter I 0  and ground and three p-channel field-effect transistors P 40 , P 41  and P 42  connected in parallel between the logic inverter I 0  and a source of a supply voltage V CC . The field-effect transistors N 40  and P 40  have their gates responsive to the predecoded signal bit B 00 , the field-effect transistors N 41  and P 41  have their gates responsive to the predecoded signal bit B 10 , and the field-effect transistors N 42  and P 43  have their gates responsive to the predecoded signal bit B 20 . 
     The three-input NAND gate G 1  of the decoder unit D 1  comprises three n-channel field-effect transistors N 43 , N 44  and N 45  connected in series between the logic inverter I 1  and ground and three p-channel field-effect transistors P 43 , P 44  and P 45  connected in parallel between the logic inverter I 1  and the source of the supply voltage V CC . The field-effect transistors N 43  and P 43  have their gates responsive to the predecoded signal bit B 01 , the field-effect transistors N 44  and P 44  have their gates responsive to the predecoded signal bit B 10 , and the field-effect transistors N 45  and P 45  have their gates responsive to the predecoded signal bit B 20 . 
     The three-input NAND gate G 2  of the decoder unit D 2  comprises three n-channel field-effect transistors N 46 , N 47  and N 48  connected in series between the logic inverter I 2  and ground and three p-channel field-effect transistors P 46 , P 47  and P 48  connected in parallel between the logic inverter I 2  and the source of the supply voltage V CC . The field-effect transistors N 46  and P 46  have their gates responsive to the predecoded signal bit B 10 , the field-effect transistors N 47  and P 47  have their gates responsive to the predecoded signal bit B 20 , and the field-effect transistors N 48  and P 48  have their gates responsive to the original input address bit A 1 . 
     The two-input NAND gate G 3  of the decoder unit D 3  comprises two n-channel field-effect transistors N 49  and N 50   connected in series between the logic inverter I 3  and ground and two p-channel field-effect transistors P 49  and P 50  connected in parallel between the logic inverter I 3  and the source of the supply voltage V CC . The field-effect transistors N 49  and P 49  have their gates responsive to the predecoded signal bit B 11  and the field-effect transistors N 50  and P 50  have their gates responsive to the predecoded signal bit B 20 . 
     As will be seen from FIG. 4, each of the two-input NAND gates G 4 , G 5  and G 6  of the decoder units D 4 , D 5  and D 6 , respectively, comprises two n-channel field-effect transistors connected in series between each of the logic inverters I 4 , I 5  and I 6  and ground and two p-channel field-effect transistors connected in parallel between each of the logic inverters I 4 , I 5  and I 6  and the source of the supply voltage V CC . One pair of n-channel and p-channel field-effect transistors of the NAND gate G 4  have their gates responsive to the predecoded signal bit B 20  and the other pair of n-channel and p-channel field-effect transistors of the NAND gate G 4  have their gates responsive to the original input address bit A 3 . One pair of n-channel and p-channel field-effect transistors of the NAND gate G 5  have their gates responsive to the predecoded signal bit B 21  and the other pair of n-channel and p-channel field-effect transistors of the NAND gate G 5   have their gates also responsive to the original input address bit A 3 . Furthermore, one pair of n-channel and p-channel field-effect transistors of the NAND gate G 6  have their gates responsive to the predecoded signal bit B 10  and the other pair of n-channel and p-channel field-effect transistors of the NAND gate G 5  have their gates responsive to the predecoded signal bit B 22 . 
     As will be further seen from FIG. 4, each of the three-input NAND gates G 7 , G 8  and G 9  of the decoder units D 7 , D 8  and D 9 , respectively, comprises three n-channel field-effect transistors connected in series between each of the logic inverters I 7 , I 8  and I 9  and ground and two p-channel field-effect transistors connected in parallel between each of the logic inverters I 7 , I 8  and I 9  and the source of the supply voltage V CC . One pair of n-channel and p-channel field-effect transistors of the NAND gate G 7  have their gates responsive to the predecoded signal bit B 11 , another pair of n-channel and p-channel field-effect transistors of the NAND gate G 7  have their gates responsive to the predecoded signal bit B 22 , and the remaining pair of n-channel and p-channel field-effect transistors of the NAND gate G 7  have their gates responsive to the inverted address bit A 1 . One pair of n-channel and p-channel field-effect transistors of the NAND gate G 8  have their gates responsive to the predecoded signal bit B 02 , another pair of n-channel and p-channel field-effect transistors of the NAND gate G 8  have their gates responsive to the predecoded signal bit B 11 , and the remaining pair of n-channel and p-channel field-effect transistors of the NAND gate G 8  have their gates responsive to the predecoded signal bit B 22 . Furthermore, one pair of n-channel and p-channel field-effect transistors of the NAND gate G 9  have their gates responsive to the predecoded signal bit B 03 , another pair of n-channel and p-channel field-effect transistors of the NAND gate G 9  have their gates responsive to the predecoded signal bit B 11 , and the remaining pair of n-channel and p-channel field-effect transistors of the NAND gate G 8  have their gates responsive to the predecoded signal bit B 22 . 
     As shown in FIG. 5, the two-input NAND gate G 10  of the decoder unit D 10  comprises two n-channel field-effect transistors N 51  and N 52  connected in series between the logic inverter I 10  and ground and two p-channel field-effect transistors P 51  and P 52  connected in parallel between the logic inverter I 10  and the source of the supply voltage V CC . The field-effect transistors N 51  and P 51  have their gates responsive to the predecoded signal bit B 23  and the field-effect transistors N 52  and P 52  have their gates responsive to the inverted address bit A 2 . Lastly, the two-input NAND gate G 11  of the decoder unit D 11  comprises two n-channel field-effect transistors N 53  and N 54  connected in series between the logic inverter I 11  and ground and two p-channel field-effect transistors P 53  and P 54  connected in parallel between the logic inverter I 11  and the source of the supply voltage V CC . The field-effect transistors N 53  and P 53  have their gates also responsive to the predecoded signal bit B 23  and the field-effect transistors N 54  and P 54  have their gates responsive to the original input address bit A 2  as shown. 
     It may be herein noted that FIG. 5 herein presented shows not only the general circuit arrangement or interconnections between the individual transistors used but also a preferred example of the layout of the transistors arranged in rows and columns on a semiconductor integrated circuit chip in conjunction with the terminals providing the supply voltage source and ground lines. 
     The active devices of the decoder circuit being thus arranged, the respective NAND gates G 0  to G 11  of the decoder units D 0  to D 11  are operative to produce output bits O 0  to O 11  in accordance with the schemes represented by the following Boolean expressions: 
     O 0  =(A 0  ·A 1 )·(A 2  ·A 3 )·(A 4   5 )=A 0  ·A 1  ·A 2  ·A 3  ·A 4  ·A 5  O 1  =(A 0  ·A 1 )·(A 2  ·A 3 )·(A 4  ·A 5 )=A 0  ·A 1  ·A 2  ·A 3  ·A 4  ·A 5   
     O 2  =A 1  ·(A 2  ·A 3 )·(A 4  ·A 5 )=A 1  ·A 2  ·A 3  ·A 4  ·A 5   
     O 3  =(A 2  ·A 3 )·(A 4  ·A 5 )=A 2  ·A 3  ·A 4  ·A 5   
     O 4  =A 3  ·(A 4  ·A 5 )=A 3  ·A 4  ·A 5   
     O 5  =A 3  ·(A 4  ·A 5 )=A 3  ·A 4  ·A 5   
     O 6  =(A 2  ·A 3 )·(A 4  ·A 5 )=A 2  ·A 3  ·A 4  ·A 5   
     O 7  =A 1  ·(A 2  ·A 3 )·(A 4  ·A 5 )=A 1  ·A 2  ·A 3  ·A 4  ·A 5   
     O 8  =(A 0  ·A 1 )·(A 2  ·A 3 )·(A 4  ·A 5 )=A 0  ·A 1  ·A 2  ·A 3  ·A 4  ·A 5   
     O 9  =(A 0  ·A 1 )·(A 2  ·A 3 )·(A 4  ·A 5 )=A 0  ·A 1  ·A 2  ·A 3  ·A 4  ·A 5   
     O 10  =A 2  ·(A 4  ·A 5 )=A 2  ·A 4  ·A 5   
     O 11  =A 2  ·(A 4  ·A 5 )=A 2  ·A 4  ·A 5   
     As will be seen from the address maps of FIGS. 2A and 2B, the address bits O 0  to O 11  produced by the individual decoder units D 0  to D 11 , viz., appearing at the output terminals of the logic inverters I 0  to I 11 , respectively, assume logic &#34;0&#34; values as follows: 
     The output address bit O 0  assumes a logic &#34;0&#34; value when all of the original input address bits A 0  to A 5  are of logic &#34;0&#34;. The output address bit O 1  assumes a logic &#34;0&#34; value when the original input address bit A 0  is of a logic &#34;1&#34; value and each of the remaining original input address bits A 1  to A 5  is of a logic &#34;0&#34; value. The output address bit O 2  assumes a logic &#34;0&#34; value without respect to the original input address bit A 0  when the original input address bit A 1  is of a logic &#34;1&#34; value and each of the remaining original input address bits A 2  to A 5  is of a logic &#34;0&#34; value. The output address bit O 3  assumes a logic &#34;0&#34; value without respect to the original input address bits A 0   and A 1  when the original input address bit A 2  is of a logic &#34;1&#34; value and each of the remaining original input address bits A 3  to A 5  is of a logic &#34;0&#34; value without respect to the bit O 4  assumes a logic &#34;0&#34; value without respect to the original input address bits A 0  to A 2  when the original input address bit A 3  is of a logic &#34;1&#34; value and each of the remaining original input address bits A 4  and A 5  is of a logic &#34;0&#34; value. The output address bit O 5  assumes a logic &#34;0&#34; value without respect to the original input address bits A 0  to A 2  when each of the original input address bits A 3  and A 4  is of a logic &#34;1&#34; value and the remaining original input address bit A 5  is of a logic &#34;0&#34;  value. The output address bit O 6  assumes a logic &#34;0&#34; value without respect to the original input address bits A 0  and A 1  when each of the original input address bits A 2  to A 4  is of a logic &#34;0&#34; value and the remaining original input address bit A 5  is of a logic &#34;1&#34; value. The output address bit O 7  assumes a logic &#34;0&#34; value without respect to the original input address bit A 0  when the original input address bits A 1 , A 3  and A 4  is of a logic &#34;0&#34; value and each of the remaining original input address bits A 2  and A 5  is of a logic &#34;1&#34; value. The output address bit O 8  assumes a logic &#34;0&#34; value when each of the original input address bits A 0 , A 3  and A 4  is of a logic &#34;0&#34; value and each of the remaining original input address bits A 1 , A 2  and A 5  is of a logic &#34;1&#34; value. The output address bit O 9  assumes a logic &#34;0&#34; value when each of the original input address bits A 0 , A 1 , A 2  and A 5  is of a logic &#34;1&#34; value and each of the remaining original input address bits A 3  and A 5  is of a logic &#34;0&#34; value. The output address bit O 10  assumes a logic &#34;0&#34; value without respect to the original input address bits A 0 , A 1  and A 3  when the original input address bit A 2  is of a logic &#34;0&#34; value and each of the remaining original input address bits A 4  and A 5  is of a logic &#34;1&#34; value. The output address bit O 11  assumes a logic &#34;0&#34; value without respect to the original input address bits A 0 , A 1  and A 3  when all the remaining input address bits A 2 , A 4  and A 5  are of logic &#34;1&#34; values. 
     Thus, each of the decoder units D 0 , D 1 , D 8  and D 9  is responsive to all of the six supplied original input address bits A 0  to A 5 . Accordingly, each of these decoder units D 0 , D 1 , D 8  and D 9  is responsive to a single unique sequence or combination of the input address bits and is accordingly comprised of a three-input NAND gate responsive to three of the predecoded signal bits alone. Each of the decoder units D 2  and D 7  is not responsive to one of the supplied original input address bits A 0  to A 5  and is thus responsive to two different sequences or combinations of the input address bits. Each of these two decoder units D 2  and D 7  may therefore be comprised of a three-input NAND gate responsive to two of the predecoded signal bits and one of the original input address bits. Each of the decoder units D 3  and D 6  is not responsive to two of the supplied original input address bits A 0  to A 5  and is thus responsive to four different sequences or combinations of the input address bits and may therefore be comprised of a two-input NAND gate for being responsive to two of the predecoded signal bits alone. Each of the decoder units D 4 , D 5 , D 10  and D 11  is not responsive to three of the supplied original input address bits A 0  to A 5  and is responsive to eight different sequences or combinations of the input address bits. Each of these decoder units D 4 , D 5 , D 10  and D 11  may therefore be also comprised of a two-input NAND gate for being responsive to one of the predecoded signal bits and one of the original input address bits. 
     From the above discussion it will have been understood that the decoder units D 0  to D 11  of the decoder circuit embodying the present invention are broken down to four different categories which consist of a first category including the decoder units D 0 , D 2 , D 8  and D 9  each including a three-input NAND gate responsive to predecoded signal bits alone, a second category including the decoder units D 3  and D 6  each including a two-input NAND gate also responsive to predecoded signal bits alone, a third category including the decoder units D 2  and D 7  each including a three-input NAND gate responsive to predecoded signal bits and an original input address bit, and a fourth category including the decoder units D 4 , D 5 , D 10  and D 11  each including a two-input NAND gate responsive to a predecoded signal bit and an original input address bit. In each of the decoder units D 2  and D 7  which fall within the third category, the original input address bit used directly by the decoder unit is selected from the bits other than those which have resulted in the two predecoded signal bits used by the decoder unit. In each of the decoder units D 4 , D 5 , D 10  and D 11  which fall within the fourth category, the original input address bit used is also selected from the bits other than those which have resulted in the single predecoded signal bit used by the decoder unit. 
     As will have been seen from the foregoing description, the decoder circuit embodying the present invention is characterized in that, inter alia, the predecoded signal bits are used in combination with the original input address bits in most of the decoder units such as the decoder units D 2 , D 4 , D 5 , D 7 , D 10  and D 11 . For this reason, each of the decoder units D 0  to D 11  of the decoder circuit embodying the present invention can be implemented by a two-input or three-input NAND gate and can accordingly be composed of only two or three CMOS transistor pairs in addition to the associated logic converter. Such a configuration of the decoder circuit embodying the present invention is prominently contrasted by a prior-art address decoder circuit which includes more than three CMOS transistor pairs as described with reference to FIG. 1. A decoder circuit according to the present invention is thus advantageous for its simplicity of construction and accordingly for the reduced switching time achievable of the decoder circuit over a prior-art decoder circuit of the described nature. The reduction in the number of series connected n-channel field-effect transistors of each of the decoder units significantly contributes to reduction in the transconductance (g m ) of the decoder unit as a whole and will make it possible further reduce the switching time of the decoder circuit. 
     While the predecode circuits used in the described embodiment of a decoder circuit have been assumed to be of the two-bit predecode type, any other types of predecode circuits such as six-bit or three-bit predecode circuits may alternatively be used in a decoder circuit according to the present invention. 
     Furthermore, all of the input lines for the original input address bits and the inverted versions thereof have been shown connected to the decoder circuit but, if desired, only those for the original input address bits A 1 , A 2  and A 3  and the inverted version A 2  of the original input address bit A 2  which are used directly by the decoder circuit may be connected to the decoder circuit. In this instance, the other input lines may be connected only to the predecode circuit PD 1 , PD 2  and PD 3  without being extended far to the decoder units per se.