Abstract:
A clock driver for a resonant clock network includes a delay circuit that receives and supplies a delayed clock signal. A first transistor is coupled to receive a first pulse control signal and supply an output clock node of the clock driver. An asserted edge of the first control signal is responsive to the falling edge of the delayed clock signal. A second transistor is coupled to receive a second control signal and to supply the output clock node of the clock driver. An asserted edge of the second control signal is responsive to a rising edge of the delayed clock signal.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The disclosed embodiments relate to clocking in integrated circuits and more particularly to pulse drive systems for clock drivers. 
         [0003]    2. Description of the Related Art 
         [0004]    Clock distribution networks account for a significant portion of overall power consumption in most high performance digital circuits today due to the large parasitic capacitance that is connected to the clock network. One aspect of efficient clock distribution is to ensure efficiency in various aspects of the clock system. 
       SUMMARY OF EMBODIMENTS 
       [0005]    In some embodiments, an apparatus includes a delay circuit coupled to receive a clock signal and supply a delayed clock signal. A first transistor is coupled to receive a first pulse control signal and supply an output clock node to generate an output clock signal based in part on the first pulse control signal. An asserted edge of the first control signal is responsive to a falling edge of the delayed clock signal. A second transistor is coupled to receive a second control signal and to supply the output clock node to generate the output clock signal based in part on the second pulse control signal. An asserted edge of the second control signal is responsive to a rising edge of the delayed clock signal. 
         [0006]    In another embodiment, a method includes delaying a clock signal in a delay circuit supplying a delayed clock signal, asserting a first pulse control signal responsive to a falling edge of the delayed clock signal, supplying the first pulse control signal to a first transistor as a first gate signal, asserting a second pulse control signal responsive to a rising edge of the delayed clock signal, and supplying the second pulse control signal to the second first transistor as a second gate signal. 
         [0007]    In another embodiment, a non-transitory computer-readable medium stores a computer readable data structure encoding a functional description of an integrated circuit. The integrated circuit includes a resonant clock network, a delay circuit coupled to receive a clock signal and supply a delayed clock signal, a first transistor coupled to receive a first pulse control signal as a first gate signal and supply an output clock node, wherein an asserted edge of the first control signal is responsive to a falling edge of the delayed clock signal. A second transistor is coupled to receive a second control signal as a second gate signal and to supply the output clock node, wherein an asserted edge of the second control signal is responsive to a rising edge of the delayed clock signal. A first current carrying terminal of the first transistor is coupled to a first power supply and a second current carrying terminal of the first transistor is coupled to a clock output signal node. A first carrying terminal of the second transistor is coupled to a second power supply and a second current carrying terminal of the second transistor is coupled to the clock output signal node. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    The embodiments disclosed herein may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings. 
           [0009]      FIG. 1  illustrates a simplified model of a resonant clock network, according to some embodiments. 
           [0010]      FIG. 2  illustrates the waveforms associated with the clock driver of  FIG. 1 , according to some embodiments. 
           [0011]      FIG. 3  illustrates a simplified model of an enhanced resonant clocking system referred to as pulse-mode drive, according to some embodiments. 
           [0012]      FIG. 4  illustrates waveforms that may be associated with the pulse mode drive of  FIG. 3 , according to some embodiments. 
           [0013]      FIG. 5  illustrates an approach for pulse mode drive that uses an inverting delay chain to generate a pulse whose width is equal to the delay through the delay chain, according to some embodiments. 
           [0014]      FIG. 6  illustrates a timing diagram associated with the pulse mode drive system shown in  FIG. 5 , according to some embodiments. 
           [0015]      FIG. 7  illustrates a pulse mode drive embodiment that uses a non-inverting delay chain to generate an output pulse having a duty cycle in which the relationship between the input duty cycle and the implemented delay is subtractive, according to some embodiments. 
           [0016]      FIG. 8  illustrates a timing diagram associated with the embodiment of  FIG. 7 , according to some embodiments. 
       
    
    
       [0017]    The use of the same reference symbols in different drawings indicates similar or identical items. 
       DETAILED DESCRIPTION 
       [0018]    One promising technique to implement more energy-efficient clock distribution is the use of resonant clocking.  FIG. 1  illustrates a simplified model of a resonant clock system  100 , according to some embodiments. A distinct feature of the resonant clock system  100  is the use of an inductance (L)  101  that is connected in parallel with the parasitic network capacitance  102  of clock network  103 . In contrast with a conventional clock network, where all the charge, and therefore energy per cycle, is provided by the power supply, the approach illustrated in  FIG. 1  uses LC resonance between the parasitic network capacitance  102  and the inductance (L)  101  to enable efficient energy transfer between these two components. The role of the clock driver is to replenish only the energy lost in the parasitic resistance  104  of the LC system. For an ideal inductor and interconnect, with no parasitic resistance, the clock network would oscillate with zero energy dissipation. 
         [0019]    The energy losses in the resonant clock network of  FIG. 1  occur in the resistance of the inductor  101 , the resistance  104  of the clock network  103 , as well as the resistance of the clock driver  105 .  FIG. 2  shows the waveforms associated with the clock driver control signal pClkX and the output clock signal rclk at node  106  of  FIG. 1 . The losses across the conducting transistor of the clock driver are equal to the product of the voltage across the transistor and the current through the transistor (V FET *I FET ). Note that the clock driver conducts during the entire transition of the output clock signal rclk waveform, resulting in continuous energy dissipation as a portion of the current flows through the device contributing to the discharge of the output clock signal rclk node. These losses in the driver are referred to as conduction losses. 
         [0020]      FIG. 3  shows a simplified model of an enhanced resonant clocking system henceforth referred to as pulse-mode drive, according to some embodiments. The pull-up device  301  and the pull-down device  303  of the clock driver  305  are driven by two separate pulse control signals, pClkXn and pClkXp.  FIG. 4  shows the waveforms of pClkXn, pClkXp and the clock signal rclk. Choosing the pulse duty cycle controls the duration for which the devices in the clock driver conduct. Thus, pulse mode drive is able to arrive at a more optimal tradeoff between switching losses (determined by the driver size) and conduction losses (determined by the resistance of the driver and the magnitude of current flowing through it), and in doing so, reduces conduction losses and improves the efficiency of the clock waveform. 
         [0021]    Referring to  FIG. 5 , the typical approach for pulse mode drive uses an inverting delay chain  501  to generate a pulse whose width is equal to the delay through the delay chain. The signals that drive the final stage of the clock driver, the pulse control signals pClkXp and pClkXn, are generated using a combination of an inverting delay chain  501  and NAND gate  503  and NOR gate  505 . 
         [0022]      FIG. 6  illustrates a timing diagram associated with the pulse mode drive system shown in  FIG. 5 . Note that the pulse width  601  and  603  of the signals that drive the final stage of the clock driver are equal to the delay (τ)  605  of the delay chain. Note also that the inverting delay chain output determines the de-asserting edge of the pulse control signals pClkXn and pClkXp (e.g., the falling edge of pulse control signal pClkXn, the rising edge of pulse control signal pClkXp). For example, pulse control signal pClkXn, which drives the NFET device  507  of the clock driver  511 , returns to zero due to the rising edge of the clk_dx signal, which is the inverted and delayed version of the clock signal clk. However, the approach of  FIG. 5  can cause problems in modern microprocessor systems associated, e.g., with jitter, driver efficiency, process variation, duty cycle, and voltage scaling. Accordingly, improvements in pulse-mode drive control are desirable. 
         [0023]    One way to improve the pulse drive system is to change the mechanism by which the delay chain impacts the duty cycle of the pulses that drive the clock driver. As described in more detail herein, some embodiments provide a more effective method for pulse mode drive that enables efficient resonant clock operation, is robust to process variation, supports multi-core supply voltage scaling, and supports clock duty cycle tuning for performance optimization in a microprocessor system. 
         [0024]    An embodiment of such a system is illustrated in  FIG. 7 . As shown in  FIG. 7 , the clock driver  700  uses a non-inverting delay chain  701  along with OR gate  703  and AND gate  705  to implement the pulse control signals pClkXp and pClkXn in  FIG. 7 , which respectively drive P-channel field effect transistor (pFET)  707  and N-channel field effect transistor (nFET)  709 . The clock driver  700  outputs the output clock signal rclk to the resonant clock network  706 . As seen from the waveforms of  FIG. 8 , the relationship between input duty cycle and the implemented delay is subtractive with regards to the generation of the output pulse duty cycle. The clock driver  700  delays asserting the edge of the pulse signals (rising edge of pClkXn for nFET  709 , and the falling edge of pClkXp for pFET  707 ) by an amount of time equal to the delay of the delay chain. Subsequently an edge of the input clock signal “clk” de-asserts the appropriate pulse signal (e.g., the pulse control signals pClkXp or pClkXn). For example, edge  805  of the input clock signal clk causes pulse control signal pClkXn to deassert at  807 . Similarly, edge  809  of the input clock signal clk causes the pulse control signal pClkXp to deassert (the rising edge (de-asserting edge) of the PFET pulse control signal pClkXp turns off PFET  707 ). While the actual circuit implementation of a particular embodiment may vary, the concept is to use the delay element to subtract from the input duty cycle to result in the output duty cycle. Thus, for the pulse control signal pClkXn, the pulse width is (DT−τ). That is, the delay τ is subtracted from the high portion (DT) of the input clock signal clk. For the pulse control signal pClkXp, the pulse width is (T−DT−τ). That is the delay τ is subtracted from the low portion (T−DT) of the clock signal clk, where T is the period of the input clock signal clk. Thus, the pulse width of the signals that drive the final stage of the clock driver are equal to the pulse width of the input, minus the delay of the delay chain, i.e., the output duty cycle is a function of input duty cycle, delay-chain delay and cycle time. That is in contrast to the approach illustrated in  FIGS. 5  and  6  where the output duty cycle is a function only of the delay chain delay and the cycle time. 
         [0025]    In contrast to the pulse drive system illustrated in  FIGS. 5 and 6 , which uses the delayed clock to control the de-asserting edge of the pulse, the embodiment shown in  FIG. 7  uses the delay chain output to determine the asserting edge of the clock (rising signal at the gate terminal at the NFET of the final stage or falling edge at the gate terminal of the PFET of the final stage). 
         [0026]    To maintain an efficiently driven, full amplitude clock waveform, the pulse duty cycle typically needs to be in the 30-40% range. A 30-40% duty cycle for the control pulses is desirable for reduced jitter degradation. To obtain the required 30-40% duty cycle range, the delay chain delay implemented in the embodiment of  FIG. 7  can be equal to around 10-20% of the duty cycle of the input clock signal clk. In contrast, in the approach of  FIG. 5 , a pulse whose width is equal to the delay of the delay chain, requires a delay chain that has a delay equal to 30-40% of the duty cycle. Implementing such a delay is more susceptible to process variation, and addressing this susceptibility results in a degradation of the efficiency of the clock drivers. The reduced delay chain delay in the embodiment of  FIG. 7  reduces energy dissipation in the driver, which improves the overall energy efficiency of the driver  700  as compared to the approach shown in  FIG. 5 . 
         [0027]    The embodiment illustrated in  FIG. 7  has reduced susceptibility to process variation. Using a shorter delay chain, and having the delayed signal determine the asserting edge of the pulse (as opposed to the critical de-asserting edge) reduces the susceptibility of the clock driver signals to process variation. In contrast, maintaining a long delay chain, as in the approach of  FIG. 5 , to achieve the required duty cycle, and having this delay chain determine the timing of the de-asserting edge of the pulse drive signals that drive the clock driver, results in susceptibility to process variation in the delay chain devices. Clock drivers are typically distributed over the entire processor so multiple delay chains exist. In resonant clocked systems, the de-asserting edge of the clock driver determines the clock transition. Therefore variability between delay chains results in clock skew that degrades system performance. Mitigating susceptibility to process variation requires either using only one or a few delay chains and distributing the delayed clock all over the processor, which is energy inefficient, or designing a process variation tolerant delay chain, which results in significant design complexity. 
         [0028]    Modern microprocessors also have to meet phase timing paths arising from the use of dynamic logic or latch-based-designs, which rely on the two phases of the clock to perform computation. A common performance optimization is therefore to vary the duty cycle of the PLL, which propagates to the output of the drivers, and allows for improved performance. The embodiment illustrated in  FIG. 7  supports duty cycle modulation. Since the duty cycle of the pulse signals are a function of both the duty cycle of the input clock signal clk, and the delay-chain delay τ, a change in the duty cycle of the input clock signal clk propagates through the clock driver  700  and varies the duty cycle of the output clock signal rclk. By doing so, the embodiment of  FIG. 7  supports duty cycle modulation of the phase-locked loop (PLL) clock to improve processor performance, which is not possible with the approach of  FIG. 5  since the duty cycle of the pulse control signals pClkXp and pClkXn is a function only of the delay in the delay chain. 
         [0029]    Most existing microprocessors use a common power supply plane to power all their cores, so that the voltage that is applied to the cores is determined by the core running at the maximum frequency. Often this implies that a core is made to run at a voltage higher than dictated by its frequency (because some other core is running faster). In the pulse drive system of  FIG. 5 , however, such a voltage will cause the pulse to shrink and have a detrimental effect on the clock waveform (slew, skew, and amplitude) and therefore performance. That is, the pulse duty cycle of the clock driver signals shrinks with increasing voltage. This is due to the fact that increased voltage shrinks the delay of the delay chain. For a constant clock period, that implies a reduced duty cycle. In contrast, the embodiment of  FIG. 7  avoids duty cycle shrinking when the processor core runs at a voltage higher than required for its frequency. Increased voltage reduces the subtractive delay-chain delay, which results in a higher duty cycle. Thus, the duty cycle of the clock driver signals in  FIG. 7  increases with increasing voltage. At a higher voltage, the widening pulse drive signals of  FIG. 7  may result in possibly wasted energy. However, the clock waveform is guaranteed to be robust, and does not degrade. 
         [0030]    While the description has contemplated being used in clock networks of microprocessors, embodiments are not limited to microprocessors. Instead the concepts and advantages described herein apply to integrated circuits in general, where voltage margining is required to ensure robust operation in the field. 
         [0031]    While circuits and physical structures have been generally presumed in describing embodiments of the invention, it is well recognized that in modern semiconductor design and fabrication, physical structures and circuits may be embodied in a computer readable medium as data structures for use in subsequent design, simulation, test, or fabrication stages. For example, such data structures may encode a functional description of circuits or systems of circuits. The functionally descriptive data structures may be, e.g., encoded in a register transfer language (RTL), a hardware description language (HDL), in Verilog, or some other language used for design, simulation, and/or test. Data structures corresponding to embodiments described herein may also be encoded in, e.g., Graphic Database System II (GDSII) data, and functionally describe integrated circuit layout and/or information for photomask generation used to manufacture the integrated circuits. Other data structures, containing functionally descriptive aspects of embodiments described herein, may be used for one or more steps of the manufacturing process. 
         [0032]    Computer-readable media include tangible computer readable media, e.g., a disk, tape, or other magnetic, optical, or electronic storage medium. In addition to computer-readable medium having encodings thereon of circuits, systems, and methods, the computer readable media may store instructions as well as data that can be used to implement embodiments described herein or portions thereof. The data structures may be utilized by software executing on one or more processors, firmware executing on hardware, or by a combination of software, firmware, and hardware, as part of the design, simulation, test, or fabrication stages. 
         [0033]    The description of the invention set forth herein is illustrative, and is not intended to limit the scope of the invention as set forth in the following claims. For example, embodiments of the invention are not limited in scope to microprocessors. Rather, the solution described herein applies to integrated circuits in general, where voltage margining is required to ensure robust operation in the field. Other variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein, without departing from the scope of the invention as set forth in the following claims.