Abstract:
A semiconductor device has a gate multiple doping regions on both sides of the gate. The gate can be shared by a transistor and a capacitor.

Description:
RELATED APPLICATIONS 
       [0001]    This application is a continuation of U.S. application Ser. No. 12/102,637, filed 14 Apr. 2008, entitled Single Gate Nonvolatile Memory Cell with Transistor and Capacitor. This application is incorporated herein by reference. 
     
    
     BACKGROUND 
       [0002]    1. Field 
         [0003]    The technology is related to nonvolatile memory integrated circuits, and in particular nonvolatile memory integrated circuits with single gate memory cells including both a transistor and a capacitor. 
         [0004]    2. Description of Related Art 
         [0005]    An example of nonvolatile memory cells, such as one time programming (OTP) memory cells is the single gate memory cell which includes both a transistor and a capacitor. Examples of such nonvolatile memory cells are described in U.S. Pat. Nos. 6,054,732; 6,875,648; 6,025,625; and 5,896,315; as well as US Patent Application Publication No. 2006/0022255. 
       SUMMARY 
       [0006]    One aspect of the technology is a semiconductor device with a gate and multiple doping regions on both sides of the gate. 
         [0007]    The first doping regions, third doping regions, and fourth doping regions have a first doping type. The second doping regions have a second doping type opposite to the first doping type 
         [0008]    In some embodiments the device includes a transistor and a capacitor controlled by the gate. 
         [0009]    In some embodiments the device includes a transistor having the first doping regions, the second doping regions, the third doping regions, and the fourth doping regions. 
         [0010]    Some embodiments include a well of the second doping type, wherein the first doping regions, the second doping regions, the third doping regions, and the fourth doping regions are in the well of the second doping type. 
         [0011]    In some embodiments the fourth doping regions define source and drain regions on opposite sides of the gate. 
         [0012]    In some embodiments the first doping regions, the second doping regions, and the third doping regions overlap source and drain regions of the device. 
         [0013]    Some embodiments include an epitaxial layer of the second doping type, wherein the device is on the epitaxial layer. 
         [0014]    Some embodiments include spacers adjacent to the gate, the spacers partly covering the first doping regions, the second doping regions, and the third doping regions. 
         [0015]    In some embodiments the device is a one time programming device. 
         [0016]    Another aspect of the technology is a semiconductor device with a gate shared by a transistor and a capacitor, and multiple doping regions on both sides of the gate. 
         [0017]    First doping regions have a first doping type. Second doping regions have a second doping type opposite to the first doping type. 
         [0018]    Some embodiments include a well of the second doping type, wherein the first doping regions and the second doping regions are in the well of the second doping type. 
         [0019]    In some embodiments the first doping regions and the second doping regions are in a well of the second doping type. 
         [0020]    In some embodiments the first doping regions define source and drain regions on opposite sides of the gate. 
         [0021]    In some embodiments the second doping regions overlap source and drain regions of the transistor. 
         [0022]    In some embodiments the first doping regions and the second doping regions overlap source and drain regions of the transistor. 
         [0023]    Some embodiments include an epitaxial layer of the second doping type, wherein the transistor and the capacitor are on the epitaxial layer. 
         [0024]    Some embodiments include spacers adjacent to the gate, the spacers partly covering the first doping regions, the second doping regions, and the third doping regions. 
         [0025]    In some embodiments the device is a one time programming device. 
         [0026]    In some embodiments the capacitor includes a plurality of contacts to control a body voltage of the capacitor. 
         [0027]    Some embodiments include wells. A first well has the first doping type, wherein the capacitor is on the first well. A second well has the second doping type, wherein the transistor is on the second well. 
         [0028]    One aspect of the technology is a nonvolatile memory integrated circuit, comprising a semiconductor substrate, and a nonvolatile memory device on the semiconductor substrate. The nonvolatile memory device includes a transistor on the semiconductor substrate and a capacitor on the semiconductor substrate. The transistor is controlled by a gate region, a source region, and a drain region. The capacitor is controlled by a gate region. The transistor has multiple doping regions. One doping region is positioned on both sides of the gate region and defines the source and drain regions, and has a doping type such as n-type. There at least three more doping regions, which are positioned on both side of the gate region, and overlap the source and drain regions, two of which have the same doping type as the source and drain regions (such as n-type) and the third which has the opposite doping type as the source and drain regions (such as p-type). A shared floating gate connects the gate region of the transistor and the gate region of the capacitor. 
         [0029]    In some embodiments, the substrate has a doping type opposite (e.g., p-type) to that of the source and drain regions. 
         [0030]    Some embodiments further comprise an epitaxial layer having a doping type opposite (e.g., p-type) to that of the source and drain regions. In various embodiments, the epitaxial layer acts as the base for structures such as the transistor and the capacitor. 
         [0031]    Various embodiments have a well with a doping type opposite (e.g., p-type) to that of the source and drain regions, the same (e.g., n-type) as that of the source and drain regions, or both such wells. Some embodiments have a transistor on one such well, a capacitor on one such well, both the transistor and capacitor in one such well, and both the transistor and capacitor in different such wells. 
         [0032]    Some embodiments include spacers adjacent to the gate region of the transistor, which partly cover the doping regions besides the source and drain regions. 
         [0033]    Some embodiments include control circuitry applying bias arrangements of memory operations to the nonvolatile memory device(s). 
         [0034]    Another aspect of the technology is a nonvolatile memory integrated circuit with multiple nonvolatile memory devices including a transistor and a capacitor described herein. 
         [0035]    Another aspect of the technology is a method of making nonvolatile memory integrated circuits described herein. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0036]      FIG. 1  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular implanting an n-well. 
           [0037]      FIG. 2  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular implanting a p-well. 
           [0038]      FIG. 3  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular growing isolation oxide between structures. 
           [0039]      FIG. 4  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular growing gate oxide for the transistor and the capacitor. 
           [0040]      FIG. 5  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular depositing polysilicon and WSi. 
           [0041]      FIG. 6  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular etching polysilicon and WSi to define the gate regions. 
           [0042]      FIG. 7  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular implanting N− doping regions (having the same doping type as the N+ source and drain regions to be formed), on both sides of the gate region of the transistor and overlapping the source and drain regions to be formed. 
           [0043]      FIG. 8  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular implanting two additional doping regions on both sides of the gate region of the transistor and overlapping the source and drain regions to be formed, one having the opposite (P) doping type as the source and drain regions to be formed, and another one having the same (N) doping type as the source and drain regions to be formed. 
           [0044]      FIG. 9  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular depositing a layer of oxide. 
           [0045]      FIG. 10  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular etching the layer of oxide to form sidewall spacers by the gate region. 
           [0046]      FIG. 11  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular implanting the source and drain regions (N+) on either side of the gate region of the transistor, and regions having the same doping type (N+) on either side of the gate region of the capacitor. 
           [0047]      FIG. 12  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular implanting a region having the opposite doping type (P+) as the source and drain regions. 
           [0048]      FIG. 13  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular depositing the single gate connecting the gate regions of the transistor and the capacitor. 
           [0049]      FIG. 14  shows a top view of a single gate memory cell with a transistor and a capacitor in different wells having different doping types. 
           [0050]      FIGS. 14A-C  show cross-sectional views of the single gate memory cell with the transistor and the capacitor in different wells having different doping types, of  FIG. 14 . 
           [0051]      FIG. 15  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular implanting a p-well, and resembles the step of  FIG. 2 . 
           [0052]      FIG. 16  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular growing isolation oxide between structures, and resembles the step of  FIG. 3 . 
           [0053]      FIG. 17  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular growing gate oxide for the transistor and the capacitor, and resembles the step of  FIG. 4 . 
           [0054]      FIG. 18  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular depositing polysilicon and WSi, and resembles the step of  FIG. 5 . 
           [0055]      FIG. 19  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular etching polysilicon and WSi to define the gate regions, and resembles the step of  FIG. 6 . 
           [0056]      FIG. 20  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular implanting N− doping regions (having the same doping type as the N+ source and drain regions to be formed), on both sides of the gate region of the transistor and overlapping the source and drain regions to be formed, and resembles the step of  FIG. 7 . 
           [0057]      FIG. 21  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular implanting two additional doping regions on both sides of the gate region of the transistor and overlapping the source and drain regions to be formed, one having the opposite (P) doping type as the source and drain regions to be formed, and another one having the same (N) doping type as the source and drain regions to be formed, and resembles the step of  FIG. 8 . 
           [0058]      FIG. 22  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular depositing a layer of oxide, and resembles the step of  FIG. 9 . 
           [0059]      FIG. 23  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular etching the layer of oxide to form sidewall spacers by the gate region, and resembles the step of  FIG. 10 . 
           [0060]      FIG. 24  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular implanting the source and drain regions (N+) on either side of the gate region of the transistor, and regions having the same doping type (N+) on either side of the gate region of the capacitor, and resembles the step of  FIG. 11 . 
           [0061]      FIG. 25  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular implanting a region having the opposite doping type (P+) as the source and drain regions, and resembles the step of  FIG. 12 . 
           [0062]      FIG. 26  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular depositing the single gate connecting the gate regions of the transistor and the capacitor, and resembles the step of  FIG. 13 . 
           [0063]      FIG. 27  shows a top view of a single gate memory cell with a transistor and a capacitor in the same well. 
           [0064]      FIGS. 27A-C  show cross-sectional views of the single gate memory cell with the transistor and the capacitor in different wells having different doping types, of  FIG. 27 . 
           [0065]      FIG. 28  shows a cross-sectional view of a single gate memory cell with a transistor and a capacitor in different wells having different doping types, and resembles  FIG. 13 , but includes an epitaxial surface. 
           [0066]      FIG. 29  shows a cross-sectional view of a single gate memory cell with a transistor and a capacitor in the same well, and resembles  FIG. 26 , but includes an epitaxial surface. 
           [0067]      FIG. 30  shows an example of a nonvolatile memory integrated circuit with a memory array of single gate memory cells with a transistor and a capacitor. 
       
    
    
     DETAILED DESCRIPTION 
       [0068]      FIG. 1  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular implanting an n-well  8 . 
         [0069]      FIG. 2  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular implanting a p-well  12 . 
         [0070]      FIG. 3  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular growing isolation oxide  16  between structures. 
         [0071]      FIG. 4  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular growing gate oxide  20  for the transistor and the capacitor. 
         [0072]      FIG. 5  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular depositing polysilicon  24  and WSi  28 . 
         [0073]      FIG. 6  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular etching polysilicon and WSi to define the gate regions  32 ,  36 , and  40  of the transistor and  33 ,  37 , and  41  of the capacitor. 
         [0074]      FIG. 7  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular implanting N− doping regions  44  and  45  (having the same doping type as the N+ source and drain regions to be formed), on both sides of the gate region of the transistor and overlapping the source and drain regions to be formed. 
         [0075]      FIG. 8  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular implanting two additional doping regions on both sides of the gate region of the transistor and overlapping the source and drain regions to be formed, one ( 48  and  49 ) having the opposite (P) doping type as the source and drain regions to be formed, and another one ( 52  and  53 ) having the same (N) doping type as the source and drain regions to be formed. 
         [0076]      FIG. 9  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular depositing a layer of oxide  58 . 
         [0077]      FIG. 10  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular etching the layer of oxide to form sidewall spacers  60  and  61  by the gate region of the transistor and sidewall spacers  62  and  63  by the gate region of the capacitor. 
         [0078]      FIG. 11  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular implanting the source and drain regions (N+)  64  and  65  on either side of the gate region of the transistor, and regions  66  and  67  having the same doping type (N+) on either side of the gate region of the capacitor. 
         [0079]      FIG. 12  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular implanting a region  68  having the opposite doping type (P+) as the source and drain regions. 
         [0080]      FIG. 13  shows a cross-sectional view of part of the process of  FIGS. 1-13  of making a single gate memory cell with a transistor and a capacitor in different wells having different doping types, in particular depositing the single gate  72  connecting the gate regions of the transistor and the capacitor. 
         [0081]      FIG. 14  shows a top view of a single gate memory cell with a transistor and a capacitor in different wells having different doping types. Oxide definition window  82  partly covers P+ implant window  100 . Oxide definition window  81  partly covers N+ implant window  96 . N+ implant window  96  partly covers N− doping window  84 , P doping window  88 , and N doping window  92 . Oxide definition window  80  partly covers N+ implant window  97 . N+ implant window  97  partly covers N− well implant window  76 . Floating gate  72  overlaps both oxide definition windows  80  and  81 . Cross-sectional lines  14 A′- 14 A′,  14 B′- 14 B′, and  14 C′- 14 C′ designate the cross-sectional views of  FIGS. 14A-14C . 
         [0082]      FIGS. 14A-C  show cross-sectional views of the single gate memory cell with the transistor and the capacitor in different wells having different doping types, of  FIG. 14 .  FIG. 14A  shows the cross-section corresponding to cross-sectional line  14 A′- 14 A′ in  FIG. 14 .  FIG. 14B  shows the cross-section corresponding to cross-sectional line  14 B′- 14 B′ in  FIG. 14 .  FIG. 14C  shows the cross-section corresponding to cross-sectional line  14 C′- 14 C′ in  FIG. 14 . 
         [0083]      FIG. 15  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular implanting a p-well  12 , and resembles the step of  FIG. 2 . 
         [0084]      FIG. 16  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular growing isolation oxide  16  between structures, and resembles the step of  FIG. 3 . 
         [0085]      FIG. 17  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular growing gate oxide  20  for the transistor and the capacitor, and resembles the step of  FIG. 4 . 
         [0086]      FIG. 18  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular depositing polysilicon and WSi  24  and  28 , and resembles the step of  FIG. 5 . 
         [0087]      FIG. 19  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular etching polysilicon and WSi to define the gate regions  32 ,  36 , and  40  of the transistor and  33 ,  37 , and  41  of the capacitor, and resembles the step of  FIG. 6 . 
         [0088]      FIG. 20  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular implanting N− doping regions  44  and  45  (having the same doping type as the N+ source and drain regions to be formed), on both sides of the gate region of the transistor and overlapping the source and drain regions to be formed, and resembles the step of  FIG. 7 . 
         [0089]      FIG. 21  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular implanting two additional doping regions on both sides of the gate region of the transistor and overlapping the source and drain regions to be formed, one ( 48  and  49 ) having the opposite (P) doping type as the source and drain regions to be formed, and another one ( 52  and  53 ) having the same (N) doping type as the source and drain regions to be formed, and resembles the step of  FIG. 8 . 
         [0090]      FIG. 22  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular depositing a layer of oxide  58 , and resembles the step of  FIG. 9 . 
         [0091]      FIG. 23  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular etching the layer of oxide to form sidewall spacers  60  and  61  by the gate region of the transistor and sidewall spacers  62  and  63  by the gate region of the capacitor, and resembles the step of  FIG. 10 . 
         [0092]      FIG. 24  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular implanting the source and drain regions  64  and  65  (N+) on either side of the gate region of the transistor, and regions  66  and  67  having the same doping type (N+) on either side of the gate region of the capacitor, and resembles the step of  FIG. 11 . 
         [0093]      FIG. 25  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular implanting a region  68  having the opposite doping type (P+) as the source and drain regions to be formed, and resembles the step of  FIG. 12 . 
         [0094]      FIG. 26  shows a cross-sectional view of part of the process of  FIGS. 15-26  of making a single gate memory cell with a transistor and a capacitor in the same well, in particular depositing the single gate  72  connecting the gate regions of the transistor and the capacitor, and resembles the step of  FIG. 13 . 
         [0095]      FIG. 27  shows a top view of a single gate memory cell with a transistor and a capacitor in the same well. Oxide definition window  82  partly covers P+ implant window  100 . Oxide definition window  81  partly covers N+ implant window  96 . N+ implant window  96  partly covers N− doping window  84 , P doping window  88 , and N doping window  92 . Oxide definition window  80  partly covers N+ implant window  97 . Floating gate  72  overlaps both oxide definition windows  80  and  81 . Cross-sectional lines  27 A′- 27 A′,  27 B′- 27 B′, and  27 C′- 27 C′ designate the cross-sectional views of  FIGS. 27A-27C . 
         [0096]      FIGS. 27A-C  show cross-sectional views of the single gate memory cell with the transistor and the capacitor in different wells having different doping types, of  FIG. 27 .  FIG. 27A  shows the cross-section corresponding to cross-sectional line  27 A′- 27 A′ in  FIG. 27 .  FIG. 27B  shows the cross-section corresponding to cross-sectional line  27 B′- 27 B′ in  FIG. 27 .  FIG. 27C  shows the cross-section corresponding to cross-sectional line  27 C′- 27 C′ in  FIG. 27 . 
         [0097]      FIG. 28  shows a cross-sectional view of a single gate memory cell with a transistor and a capacitor in different wells having different doping types, and resembles  FIG. 13 , but includes an epitaxial surface  104 . 
         [0098]      FIG. 29  shows a cross-sectional view of a single gate memory cell with a transistor and a capacitor in the same well, and resembles  FIG. 26 , but includes an epitaxial surface  104 . 
         [0099]    Table 1 below shows experimental data for exemplary nonvolatile memory cells as described herein, with 5V one time programming cells. According to the upper part of the table, process  1  has just implant  44 , 45 , process  2  has two sets of implants  44 , 45 , process  3  has implants  44 , 45 ; and  52 , 53 , and process  4  has implants  44 , 45 ;  48 , 49 ; and  52 , 53 . Vt is threshold voltage. BVD is breakdown voltage or punch through voltage of a long channel. Ids is channel current. Isb is substrate current, and is an indicator for hot carriers that program the memory cell. Vpt is punch through or voltage breakdown voltage of a short channel. Id is leakage current. 
         [0000]    
       
         
               
             
               
               
               
               
               
             
               
               
               
               
               
             
               
             
               
               
               
               
               
             
               
             
               
               
               
               
               
             
               
             
               
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 5 V one time programming cells 
               
             
          
           
               
                   
                 Process 1 
                 Process 2 
                 Process 3 
                 Process 4 
               
               
                   
                   
               
             
          
           
               
                 Implant 44, 45 (e.g., N- 
                 X 
                 X 
                 X 
                 X 
               
               
                 LDD) 
               
               
                 2 nd  implant 44, 45 
                   
                 X 
               
               
                 (e.g. N-LDD) 
               
               
                 Implant 52, 53 (e.g., 
                   
                   
                 X 
               
               
                 N-hot carrier) 
               
               
                 Implants 48, 49, 52, 53 
                   
                   
                   
                 X 
               
               
                 (e.g., P-pocket, N-hot 
               
               
                 carrier) 
               
             
          
           
               
                 Sample 1 Data: W/L 20 um/20 um 
               
             
          
           
               
                 Vt (V) 
                 0.75 
                 0.74 
                 0.76 
                 0.76 
               
               
                 BVD (V) 
                 11.5 
                 12.3 
                 10.6 
                 10.1 
               
             
          
           
               
                 Sample 2 Data: W/L 20 um/0.5 um 
               
             
          
           
               
                 Vt (V) 
                 0.72 
                 0.63 
                 0.77 
                 0.76 
               
               
                 Ids (mA) Vgs = Vds = 
                 9.11 
                 12.8 
                 10.7 
                 11.2 
               
               
                 5 V 
               
               
                 Isb (uA) Vds = 5.5 V 
                 −58.2 
                 −308.8 
                 −341.6 
                 −517 
               
               
                 Vpt (V) @ 100 nA 
                 11.5 
                 5.5 
                 10.6 
                 10.1 
               
               
                 Id (pA) Vd = 6 V 
                 22.1 
                 4 × 10 −6   
                 53.3 
                 57.4 
               
             
          
           
               
                 Sample 3 Data: W/L 20 um/0.45 um 
               
             
          
           
               
                 Vpt (V) @ 100 nA 
                 11.5 
                 2.4 
                 10.6 
                 10.1 
               
               
                   
               
             
          
         
       
     
         [0100]    Table 2 below shows experimental data for exemplary nonvolatile memory cells as described herein, with 3V one time programming cells. 
         [0000]    
       
         
               
             
               
               
               
               
               
             
               
               
               
               
               
             
               
             
               
               
               
               
               
             
               
             
               
               
               
               
               
             
               
             
               
               
               
               
               
             
           
               
                 TABLE 2 
               
             
             
               
                   
               
               
                 3 V one time programming cells 
               
             
          
           
               
                   
                 Process 1 
                 Process 2 
                 Process 3 
                 Process 4 
               
               
                   
                   
               
             
          
           
               
                 Implant 44, 45 (e.g., N- 
                 X 
                 X 
                 X 
                 X 
               
               
                 LDD) 
               
               
                 2 nd  implant 44, 45 
                   
                 X 
               
               
                 (e.g. N-LDD) 
               
               
                 Implant 52, 53 (e.g., 
                   
                   
                 X 
               
               
                 N-hot carrier) 
               
               
                 Implants 48, 49, 52, 53 
                   
                   
                   
                 X 
               
               
                 (e.g., P-pocket, N-hot 
               
               
                 carrier) 
               
             
          
           
               
                 Sample 1 Data: W/L 20 um/20 um 
               
             
          
           
               
                 Vt (V) 
                 0.55 
                 0.56 
                 0.56 
                 0.56 
               
               
                 BVD (V) 
                 12.2 
                 11.6 
                 9.9 
                 9.6 
               
             
          
           
               
                 Sample 2 Data: W/L 20 um/0.5 um 
               
             
          
           
               
                 Vt (V) 
                 0.55 
                 0.50 
                 0.54 
                 0.61 
               
               
                 Ids (mA) Vgs = Vds = 
                 7.2 
                 9.8 
                 9.2 
                 8.7 
               
               
                 3 V 
               
               
                 Isb (uA) Vds = 3.3 V 
                 −4 
                 −11.14 
                 −16.08 
                 −19.95 
               
               
                 Vpt (V) @ 100 nA 
                 12 
                 5.8 
                 9.9 
                 9.6 
               
               
                 Id (pA) Vd = 4 V 
                 27 
                 3034 
                 62 
                 17 
               
             
          
           
               
                 Sample 3 Data: W/L 20 um/0.45 um 
               
             
          
           
               
                 Vpt (V) @100 nA 
                 12 
                 2.5 
                 7.4 
                 9.6 
               
               
                   
               
             
          
         
       
     
         [0101]    Tables 1 and 2 show that Isb has the largest magnitude for process  4  with implants  44 , 45 ;  48 , 49 ; and  52 , 53 . Because Isb or substrate current, is an indicator for hot carriers that program the memory cell, process  4  is associated with high programmability of the nonvolatile memory cells. Process  3  is also associated with high substrate current and high programmability of the nonvolatile memory cells, though not as much as process  4 . Process  4  is also associate with good short channel effects, as shown by the high Vpt punch through voltage for sample  3 . Processes  3  and  4  have good short channel effects, for sample  2 . 
         [0102]    Table 3 below shows example ranges of the various implants. The energies are greater than 20 keV. Also, an example wafer resistance range is 8-100 ohms. 
         [0000]    
       
         
               
             
               
               
               
             
           
               
                 TABLE 3 
               
               
                   
               
               
                 Implantation Dosages 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 Implant 8 (e.g., n-well) 
                 10 11 -10 13  cm −2   
               
               
                   
                 Implant 12 (e.g., p-well) 
                 10 11 -10 13  cm −2   
               
               
                   
                 Implant 44, 45 (e.g. N-LDD) 
                 10 12 -10 13  cm −2   
               
               
                   
                 Implant 48, 49 (e.g., P-pocket) 
                 10 11 -10 14  cm −2   
               
               
                   
                 Implant 52, 53 (e.g., N-hot carrier) 
                 10 12 -10 14  cm −2   
               
               
                   
                 Implant 64, 65 (e.g., N+ source, drain) 
                        10 15  cm −2   
               
               
                   
                   
               
             
          
         
       
     
         [0103]      FIG. 30  shows an example of a nonvolatile memory integrated circuit with a memory array of single gate memory cells with a transistor and a capacitor. The integrated circuit  3050  includes a memory array  3000  implemented using programmable memory cells, each cell being a single gate FET and capacitor cell as described herein, with at least four doping regions in the transistor. A row decoder  3001  is coupled to a plurality of word lines  3002  arranged along rows in the memory array  3000 . A column decoder  3003  is coupled to a plurality of bit lines  3004  arranged along columns in the memory array  3000 . Addresses are supplied on bus  3005  to column decoder  3003  and row decoder  3001 . Sense amplifiers and data-in structures in block  3006  are coupled to the column decoder  3003  via data bus  3007 . Data is supplied via the data-in line  3011  from input/output ports on the integrated circuit  3050 , or from other data sources internal or external to the integrated circuit  3050 , to the data-in structures in block  3006 . Data is supplied via the data-out line  3015  from the sense amplifiers in block  3006  to input/output ports on the integrated circuit  3050 , or to other data destinations internal or external to the integrated circuit  3050 . A bias arrangement state machine  3009  controls the application of bias arrangement supply voltages  3008 . 
         [0104]    Another embodiment uses p-channel transistors, and accordingly exchanges the p-regions for n-regions, and exchanges the n-regions for p-regions. 
         [0105]    Examples of operation are described as follows. 
         [0106]    An embodiment of  FIG. 13  has the following example operations with example voltage settings: 
         [0107]    Channel F-N erase to low threshold voltage (electrons directed from the gate region of the transistor into the p-well  12 ) 
         [0000]    
       
         
               
               
               
             
           
               
                   
                   
               
               
                   
                 Terminal 
                 Voltage 
               
               
                   
                   
               
             
             
               
                   
                 Control gate 67 
                 Sufficiently− 
               
               
                   
                 Drain 64 
                 Floating 
               
               
                   
                 Source 65 
                 Sufficiently+ 
               
               
                   
                 Bulk 68 
                 Sufficiently+ 
               
               
                   
                   
               
             
          
         
       
     
         [0108]    Edge F-N erase to low threshold voltage (electrons directed from the gate region of the transistor into the p-well  12  in the direction of the source ( 65 )) 
         [0000]    
       
         
               
               
               
             
           
               
                   
                   
               
               
                   
                 Terminal 
                 Voltage 
               
               
                   
                   
               
             
             
               
                   
                 Control gate 67 
                 Sufficiently− 
               
               
                   
                 Drain 64 
                 Floating 
               
               
                   
                 Source 65 
                 Sufficiently+ 
               
               
                   
                 Bulk 68 
                 Ground 
               
               
                   
                   
               
             
          
         
       
     
         [0109]    Channel F-N program to high threshold voltage (electrons directed from the p-well  12  into the gate region of the transistor) 
         [0000]    
       
         
               
               
               
             
           
               
                   
                   
               
               
                   
                 Terminal 
                 Voltage 
               
               
                   
                   
               
             
             
               
                   
                 Control gate 67 
                 Sufficiently+ 
               
               
                   
                 Drain 64 
                 Floating 
               
               
                   
                 Source 65 
                 Sufficiently− 
               
               
                   
                 Bulk 68 
                 Sufficiently− 
               
               
                   
                   
               
             
          
         
       
     
         [0110]    Hot electron program to high threshold voltage (electrons directed from the p-well  12  into the gate region of the transistor) 
         [0000]    
       
         
               
               
               
             
           
               
                   
                   
               
               
                   
                 Terminal 
                 Voltage 
               
               
                   
                   
               
             
             
               
                   
                 Control gate 67 
                 Sufficiently+ 
               
               
                   
                 Drain 64 
                 Sufficiently+ 
               
               
                   
                 Source 65 
                 Ground 
               
               
                   
                 Bulk 68 
                 Ground 
               
               
                   
                   
               
             
          
         
       
     
         [0111]    An embodiment of  FIG. 26  has the following example operations with example voltage settings: 
         [0112]    Channel F-N erase to low threshold voltage (electrons directed from the gate region of the transistor into the p-well  12 ) 
         [0000]    
       
         
               
               
               
             
           
               
                   
                   
               
               
                   
                 Terminal 
                 Voltage 
               
               
                   
                   
               
             
             
               
                   
                 Control gate 67 
                 Sufficiently− 
               
               
                   
                 Drain 64 
                 Floating 
               
               
                   
                 Source 65 
                 Sufficiently+ 
               
               
                   
                 Bulk 68 
                 Sufficiently+ 
               
               
                   
                   
               
             
          
         
       
     
         [0113]    Edge F-N erase to low threshold voltage (electrons directed from the gate region of the transistor into the p-well  12  in the direction of the source ( 65 )) 
         [0000]    
       
         
               
               
               
             
           
               
                   
                   
               
               
                   
                 Terminal 
                 Voltage 
               
               
                   
                   
               
             
             
               
                   
                 Control gate 67 
                 Sufficiently− 
               
               
                   
                 Drain 64 
                 Floating 
               
               
                   
                 Source 65 
                 Sufficiently+ 
               
               
                   
                 Bulk 68 
                 Ground 
               
               
                   
                   
               
             
          
         
       
     
         [0114]    Channel F-N program to high threshold voltage (electrons directed from the p-well  12  into the gate region of the transistor) 
         [0000]    
       
         
               
               
               
             
           
               
                   
                   
               
               
                   
                 Terminal 
                 Voltage 
               
               
                   
                   
               
             
             
               
                   
                 Control gate 67 
                 Sufficiently+ 
               
               
                   
                 Drain 64 
                 Floating 
               
               
                   
                 Source 65 
                 Sufficiently− 
               
               
                   
                 Bulk 68 
                 Sufficiently− 
               
               
                   
                   
               
             
          
         
       
     
         [0115]    Hot electron program to high threshold voltage (electrons directed from the p-well  12  into the gate region of the transistor) 
         [0000]    
       
         
               
               
               
             
           
               
                   
                   
               
               
                   
                 Terminal 
                 Voltage 
               
               
                   
                   
               
             
             
               
                   
                 Control gate 67 
                 Sufficiently+ 
               
               
                   
                 Drain 64 
                 Sufficiently+ 
               
               
                   
                 Source 65 
                 Ground 
               
               
                   
                 Bulk 68 
                 Ground 
               
               
                   
                   
               
             
          
         
       
     
         [0116]    In some embodiments, multiple control gates, such as  66  and  67  both receive the control gate voltage for more uniform voltage control of the capacitor region. 
         [0117]    While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.