Abstract:
A charge pump circuit is disclosed. The charge pump circuit comprises a transfer capacitor receiving a first clock phase and a driving capacitor receiving a second clock phase, the second clock phase opposite to the first clock phase. The circuit includes a first switch coupling an input node to the transfer capacitor. The first switch being controlled by the driving capacitor. The circuit further includes a second switch coupling the input node to the driving capacitor. The second switch being controlled by the transfer capacitor. The circuit also includes a third switch coupling the transfer capacitor to an output node. The third switch being controlled by the driving capacitor. The third switch operating in phase opposition to the first switch. The circuit finally includes a charge storage capacitor coupled to the output node.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application is related to U.S. patent application Ser. No. 13/071,374, filed on Mar. 24, 2011, entitled “HIGH-VOLTAGE MEMS APPARATUS AND METHOD”, which is incorporated herein by reference. 
     FIELD OF THE INVENTION 
     The present invention relates generally to integrated circuits and more particularly to the generation of boosted voltages using a charge pump circuit. 
     BACKGROUND OF THE INVENTION 
     Many electronic systems rely on the use of boosted voltages in excess of a given supply voltage. For example, micro-electromechanical systems (MEMS) may use boosted voltage to bias a proof mass to improve the sensitivity of a MEMS sensor. In some cases, a boosted voltage may be used to supply a high-voltage driver to allow for application of increased electrostatic force to actuate a MEMS device. 
     A class of voltage boosters known as charge pumps provides elevated voltage depositing charge onto storage capacitors arranged in a sequential chain of individual pumping stages. Voltage is boosted to increasing levels along the chain, and voltages well in excess of the input supply can be produced. Desirable characteristics of charge pumps include low parasitics, high pumping efficiency and low ripple. It is also desirable to be able to generate large voltages without exceeding the breakdown voltage of the devices used in the charge pump chain. For compatibility with low-cost manufacturing processes, it is sometimes desirable to have charge pumps in which devices with comparatively low breakdown voltages may nonetheless be used in the individual pumping stages to produce very large output voltages. For example, in some situations it may be desirable to produce a bias voltage in excess of 20V using devices rated to only 2V. In such cases, a large number of stages may be employed to achieve the required voltage boosting ratio. Thus, to further minimize cost, it is desirable to minimize the number of components required for the individual charge pump stages. 
     Thus, there is a need for charge pumps providing high efficiency and low ripple in a manner compatible with the use of relatively low breakdown voltage components wherein the number of components required for each pumping stage is minimized. The present invention addresses such a need. 
     SUMMARY OF THE INVENTION 
     A charge pump circuit is disclosed. The charge pump circuit comprises a transfer capacitor receiving a first clock phase and a driving capacitor receiving a second clock phase, the second clock phase opposite to the first clock phase. The circuit includes a first switch coupling an input node to the transfer capacitor. The first switch being controlled by the driving capacitor. The circuit further includes a second switch coupling the input node to the driving capacitor. The second switch being controlled by the transfer capacitor. The circuit also includes a third switch coupling the transfer capacitor to an output node. The third switch being controlled by the driving capacitor. The third switch operating in phase opposition to the first switch. The circuit finally includes a charge storage capacitor coupled to the output node. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a prior-art charge pump providing a boosted output voltage. 
         FIG. 2  illustrates a first embodiment of a charge pump according to the present invention. 
         FIG. 3  illustrates a second embodiment of a charge pump according to the present invention. 
         FIG. 4  illustrates more details of the embodiment of  FIG. 3  related to the bulk connections of the transistors therewithin. 
         FIG. 5  a charge pump system that includes cascaded N cascaded charge pump stages with alternating stages operating on alternating clock phases. 
     
    
    
     DETAILED DESCRIPTION 
     The present invention relates generally to generating boosted voltages using a charge pump. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein. 
     An exemplary charge pump  100  known in the art is illustrated in  FIG. 1 . The charge pump  100  produces a boosted output voltage, V OUT , in excess of an input supply voltage, V DD . The steady-state operation of the charge pump  100  can be described with reference to two basic operating periods. In a first operating period, phase 1, stage  101  is in a charging phase while stage  111  is in a pumping phase. In phase 1, transfer capacitor  106  charges to V DD  potential from the input supply when signal ph 1   d  goes high. Driving capacitor  107  was previously charged to V DD  potential so that when signal ph 1   d  goes high, the gate of NMOS switch  102  drives up to a potential close to 2*V DD  so that the switch is strongly on. In the second operating period, phase 2, node A is boosted high to 2*V DD  and when signal ph 2   d  goes high, transfer capacitor  116  charges to 2*V DD  potential via NMOS switch  112 . Driving capacitor  117  was previously charged to 2*V DD  potential so that when signal ph 2   d  goes high, the gate of NMOS switch  112  is boosted to a potential close to 3*V DD  so that the switch is strongly on. During phase 2, driving capacitor  107  is refreshed from the input supply via NMOS switch  103 . During the next phase 1 interval, node B is boosted high to 3*V DD , transferring charge to the charge storage capacitor  126  via diode-connected NMOS device  122 . The steady-state voltage at V OUT  is therefore equal to 3*V DD  minus a diode voltage, provided that there is no static load current. To generalize for a system of N stages, the steady-state output voltage is equal to (N+1)*V DD  minus a diode voltage, provided that there is no static load current. 
     The exemplary prior-art charge pump  100  of  FIG. 1  has several limitations. First, the output voltage, V OUT , is reduced by one diode drop compared to the maximum voltage at node B. The diode drop reduces the efficiency of the charge pump  100 . Second, the swing at nodes A and B is V DD , and the peak swing at these nodes occurs on opposite phases so that the NMOS devices  102 - 103  and  112 - 113  must withstand relatively large voltages as high as 2*V DD  across their terminals. These large voltages can pose a reliability hazard unless the devices are rated to a voltage in excess of this value. Third, for proper operation the charge pump  100  requires a relatively complex clocking scheme employing four clocks with edges arranged in a specific phase relationship to provide optimal pumping efficiency. The required relationship is illustrated qualitatively in  FIG. 1 . Finally, nodes X and Y in the circuit do not have proper discharge paths so that when the charge pump  100  is disabled, charge may be trapped at these nodes while nodes A and B can discharge through diode  122 . The charge trapping can pose a serious reliability hazard, particularly in charge pumps with many cascaded stages. 
       FIG. 2  illustrates a first embodiment of a charge pump  200  according to the present invention. This embodiment addresses the first three of the above-identified limitations. In this embodiment, PMOS devices  204  and  214  are introduced, allowing NMOS diode  122  to be removed. Thus, all stages in the charge pump  200  chain operate based on switches and no efficiency is lost due to charging the output through a diode. Charge storage capacitors  208  is inserted at node A to store the output charge of the first stage  201 . In steady-state operation, node A settles to a fixed potential of 2*V DD  since node A is not clocked. Since node A has a fixed voltage of 2*V DD  and node X swings between V DD  and 2*V DD , none of the devices  202 - 204  of the first stage  201  see terminal voltages in excess of V DD . Thus, the required voltage rating of the devices is half that of the charge pump  100  shown in  FIG. 1 . The introduction of PMOS devices  204  and  214  and charge storage capacitor  208  reduces the stage-to-stage interaction so that a simple two-phase clocking scheme is sufficient. The steady-stage output voltage, VOUT, is 3*V DD  for the embodiment of  FIG. 2 . Generalizing to an arrangement of N stages, one expects an output voltage of (N+1)*V DD , provided that there is no static load current. 
       FIG. 3  illustrates a second embodiment of a charge pump  300  according to the present invention. The final limitation of the charge pump  100  of  FIG. 1  is addressed by this embodiment. In this embodiment, clamp diodes  305  and  315  are introduced to provide discharge paths to nodes X and Y. When the charge pump  300  is powered down and node V OUT  discharges, clamp diodes  305  and  315  clamp nodes X and Y to nodes A and V OUT  so that devices  302 - 304  and  312 - 314  never experience voltages in excess of V DD , their required voltage rating for steady-state operation. During steady-state operation, clamp diodes  305  and  315  conduct no current and are therefore in the off state. 
     The discussion of the embodiments of  FIGS. 2 and 3  has so-far focused on steady-state behavior. The start-up behavior of the present invention can be understood with reference to  FIG. 4  which shows the embodiment of  FIG. 3  with added details concerning the bulk connections of the NMOS devices  402 - 403 ,  412 - 413  and PMOS devices  404  and  414 . For all of these devices, the bulk is connected to the source so that all of the parasitic diodes  422 - 424 ,  432 - 434  associated with the sources and drains of the devices are reverse-biased in steady-state operation. However, during start-up, these parasitic diodes assist with initial charge pumping. As can be seen in  FIG. 4 , parasitic diodes  422 - 424  and clamp diode  405  in the first stage  401  form a diode bridge. Similarly, parasitic diodes  432 - 434  and clamp diode  415  in the second stage  411  form another diode bridge. During start-up, there is initially insufficient voltage for all switches to act robustly. During start up, pumping occurs via the diode bridges, with upper and lower halves of the bridge delivering charge during opposite phases. After several cycles, enough voltage has built up at the internal node A and output node VOUT for the switches to start turning on normally. In steady-state operation, the flow of charge occurs by switch operation, and the parasitic diodes  422 - 424 ,  432 - 434  and clamp diodes  405 ,  415  remain off. 
     Multiple stages according to the present invention may be cascaded to produce higher output voltages. An embodiment of the present invention shown in  FIG. 5  cascades N charge pump stages with alternating stages operating on alternating clock phases. By a cascade of N stages  541 - 545 , a steady-state output voltage of (N+1)*V DD  may be produced, provided that there is negligible load current. The intermediate voltages at nodes A, B, C, D, etc. are sequentially boosted by V DD  volts per stage. Each of the individual stages  541 - 545  comprises an arrangement of devices such as shown in  FIG. 4 , including two NMOS devices (such as  402 - 403 ) with associated parasitic diodes (such as  422 - 423 ), one PMOS device (such as  404 ) with associated parasitic diode (such as  424 ), one clamp diode (such as  405 ), one charge transfer capacitor (such as  406 ) and one driving capacitor (such as  407 ). 
     A charge pump comprising a cascade of multiple stages as shown in  FIG. 5  may be employed in a system such as that shown in  FIG. 6 . In this embodiment, a cascade of N stages  601 - 604  produces a bias voltage, V BIAS , for a MEMS device  651 . The N stages  601 - 604  may be contained in corresponding high-voltage isolation regions  611 - 614  located within a common substrate  681 . The bias voltage, V BIAS , is monitored by controller  661  via an attenuator  671  comprising resistors  672 - 673 . The controller  661  produces the two clock phases necessary for driving the cascade of N stages  601 - 604 . By adjusting the clock pulse density or frequency of the two clock phases, the controller may adjust the drive current supplied to the attenuator  671  by the cascade of N stages  601 - 604  and thereby regulate the bias voltage, V BIAS , to a fixed voltage. By these means, a regulated high-voltage bias is provided for the MEMS device. 
     For testing the drive current capability of the charge pump, a cascoded arrangement of NMOS devices  620 - 624  is provided to convey a programmable test current supplied by current source  641  to the V BIAS  node at the output of the cascade of N stages  601 - 604 . The NMOS devices  621 - 624  sit within corresponding high-voltage isolation regions  631 - 634 . By these means, the charge pump system may be tested without the need to directly observe the high voltage bias node. 
     It should be noted that none of the transistors used in the N-stages  601 - 604  or the controller circuitry  661  or the cascoded NMOS devices  620 - 624  are required to tolerate high voltages. The transistors used in the N-stages  601 - 604  are only required to tolerate terminal voltages as high as V DD . The high-voltage bias, V BIAS , is coupled to the controller through attenuator  671  so that the reduced attenuator output voltage is also within the voltage rating of the transistors used in controller  661 . High-voltage isolation regions  611 - 614  and  631 - 634  ensure that parasitic diode breakdown to the common substrate  681  is also avoided. Advantageously, by these means a high-voltage bias for the MEMS device is provisioned without the need to employ transistors with a high voltage rating. 
     Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.