Abstract:
One embodiment of the present invention provides a system that facilitates selectively increasing the operating frequency of an electronic circuit, such as a computer system. The system begins by operating in a low-power state with the frequency and voltage of the electronic circuit set to low levels. Upon recognizing the need for performance beyond the low power level, the electronic circuit enters the first-intermediate power state. In this first-intermediate power state, the frequency and voltage are set to first-intermediate levels. Upon recognizing the need for performance beyond the first-intermediate power state, the electronic circuit enters the maximum-sustainable power state. In this power state, the frequency and voltage are set to maximum sustainable levels. Upon recognizing the need for performance beyond the maximum-sustainable power state, the electronic circuit temporarily enters a boosted power state beyond the maximum-sustainable power state. In this boosted power state, the frequency and voltages are set to levels beyond the maximum sustainable levels.

Description:
RELATED APPLICATION  
       [0001]    The present application is a continuation-in-part of, and hereby claims priority under 35 U.S.C. §120 to, a co-pending non-provisional application by William C. Athas, entitled, “Method and Apparatus for Increasing the Operating Frequency of an Electronic Circuit,” having Ser. No. 09/991,092, and filing date of 16 Nov. 2001 (Attorney Docket No. APL-P2682).  
     
    
     
       BACKGROUND  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to the design of electronic circuits. More specifically, the present invention relates to a method and apparatus for selectively increasing the operating frequency of an electronic circuit.  
           [0004]    2. Related Art  
           [0005]    As computer system performance continues to increase at an exponential rate, the circuitry within the computer systems is forced to keep pace with ever-faster frequencies. These faster frequencies mean that the circuitry switches more often, which causes the circuit to consume more power. As the circuitry consumes more power, it produces more heat.  
           [0006]    This heat must somehow be removed so that the temperature within the computer circuits does not exceed a maximum operating temperature. To this end, computer systems typically include a number of heat-dissipating components, such as heat sinks, cooling fans and heat pipes to dissipate thermal energy.  
           [0007]    Unfortunately, providing these heat-dissipating components within a computer system can present a number of problems. First, these heat-dissipating components can significantly increase the volume and weight of a computer system, which is especially a problem for portable computer systems in which volume and weight must be minimized. Second, providing these heat-dissipating components can significantly increase the manufacturing cost of a computer system. Third, providing these heat-dissipating components can reduce reliability of a computer system, because components such as cooling fans, can fail. Furthermore, some of these components such as cooling fans, consume extra power and can thereby decrease battery life in a portable computer system.  
           [0008]    In order to reduce the power consumption, many portable computer systems enter a power conservation mode whenever the computer system is not busy. During this power conservation mode, the computer system operates at reduced frequency and voltage levels to minimize the amount of power consumed by the computer system, and to thereby increase battery life. When the computer system becomes busy again, the frequency is increased to a maximum sustainable frequency. For many portable computer systems, this maximum sustainable frequency is determined by the capacity of the computer system to dissipate heat.  
           [0009]    Note that this maximum sustainable frequency is determined by assuming that the computer system will operate continuously at this frequency. Most computer applications, however, do not perform computational work continuously. In fact, most applications tend to perform computational work for short, concentrated bursts between long idle periods when the computer system is waiting for user input. Hence, the maximum sustainable operating frequency is typically too conservative because it is based on the worst-case assumption that an application performs computational work continuously.  
           [0010]    What is needed is a method and an apparatus for selectively increasing the operating frequency of a computer system.  
         SUMMARY  
         [0011]    One embodiment of the present invention provides a system that facilitates selectively increasing the operating speed of an electronic circuit, such as a computer system, in order to balance power consumption with performance. The system begins in a low-power state with the frequency and voltage of the electronic circuit set to low levels. Upon recognizing the need for performance beyond the low power level, the electronic circuit enters the first-intermediate power state. In this first-intermediate power state, the frequency and voltage are set to first-intermediate levels. Upon recognizing the need for performance beyond the first-intermediate power state, the electronic circuit enters a maximum-sustainable power state. In this power state, the frequency and voltage are set to maximum sustainable levels. Upon recognizing the need for performance beyond the maximum-sustainable power state, the electronic circuit temporarily enters a boosted power state beyond the maximum-sustainable power state. In this boosted power state, the frequency and voltages are set to levels beyond the maximum sustainable levels.  
           [0012]    In a variation of this embodiment, the electronic circuit resides for preset time intervals in the low-power state, the first-intermediate power state, and the maximum-sustainable power state, before transitioning to other states.  
           [0013]    In a further variation, the electronic circuit resides in the boosted power state either for a preset time interval or until the electronic circuit exceeds a maximum thermal energy level.  
           [0014]    In a further variation, the electronic circuit returns to the maximum-sustainable power state after residing in the boosted power state.  
           [0015]    In a further variation, the electronic circuit activates a busy signal when the electronic circuit is busy performing computational work.  
           [0016]    In a further variation, the electronic circuit returns to the low-power state from a given state if the busy signal is deactivated while the electronic circuit is in the given state.  
           [0017]    In a further variation, the electronic circuit recovers computational work lost because of the lower operating speeds in the low-power state and the first-intermediate power state by temporarily operating above maximum sustainable frequency and voltage in the boosted power state.  
           [0018]    In a further variation, upon recognizing the need for performance beyond the first-intermediate power state, the electronic circuit enters a second-intermediate power state before entering the maximum-sustainable power state.  
           [0019]    In a further variation, upon recognizing the need for more performance beyond the second-intermediate power state, the electronic circuit enters one or more additional power states before entering the maximum-sustainable power state.  
           [0020]    In a further variation, if the thermal energy of a cooling system associated with the electronic circuit exceeds a maximum level, the electronic circuit does not enter the boosted power state but instead enters the maximum-power state.  
           [0021]    In a further variation, the thermal energy of the cooling system is determined by measuring the temperature of a heat sink within the cooling system. 
       
    
    
     BRIEF DESCRIPTION OF THE FIGURES  
       [0022]    [0022]FIG. 1 illustrates a computer system in accordance with an embodiment of the present invention.  
         [0023]    [0023]FIG. 2 illustrates a state-diagram of the transition between power states of the electronic circuit in accordance with an embodiment of the present invention.  
         [0024]    [0024]FIG. 3A illustrates four possible power states of the electronic circuit in accordance with an embodiment of the present invention.  
         [0025]    [0025]FIG. 3B presents a table illustrating the computational work done by the electronic circuit in a given time in accordance with the power states of FIG. 3A.  
     
    
     DETAILED DESCRIPTION  
       [0026]    The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.  
         [0027]    The data structures and code described in this detailed description are typically stored on a computer readable storage medium, which may be any device or medium that can store code and/or data for use by a computer system. This includes, but is not limited to, magnetic and optical storage devices such as disk drives, magnetic tape, CDs (compact discs) and DVDs (digital versatile discs or digital video discs), and computer instruction signals embodied in a transmission medium (with or without a carrier wave upon which the signals are modulated). For example, the transmission medium may include a communications network, such as the Internet.  
         [0028]    Computer System  
         [0029]    [0029]FIG. 1 illustrates a computer system  100  in accordance with an embodiment of the present invention. Computer system  100  can generally include any type of computer system, including, but not limited to, a computer system based on a microprocessor, a mainframe computer, a digital signal processor, a portable computing device, a personal organizer, a device controller, and a computational engine within an appliance.  
         [0030]    Computer system  100  includes a number of components, including one or more computational engines, such as microprocessors, located within processor complex  111 . These processors are coupled to memory  116  through memory controller  115 . Memory controller  115  can include any type of circuitry that coordinates accesses to memory  116 . Memory  116  can include any type of random access memory for storing code and data to be accessed by processors within processor complex  111 .  
         [0031]    Computer system  100  also includes components related to controlling temperature. These components include heat sink  112 , thermal sensor  114  and thermal energy level signal  102 . Heat sink  112  dissipates heat from processor complex  111 . Note that heat sink  112  can additionally dissipate heat from other heat-producing components within computer system  100 . Thermal sensor  114  is coupled to heat sink  112 . Thermal sensor  114  provides a measurement of the thermal energy level of heat sink  112  to power management unit  110  through thermal energy level signal  102 .  
         [0032]    Power management unit  110  controls the operating frequency and supply voltage for processor complex  111 . Power management unit  110  raises or lowers the frequency and voltage levels for computer system  100  in response to signals received from power management unit control  101 , thermal energy level signal  102  and processor busy signal  103 . Power management unit  110  does so by communicating with a special-purpose frequency/voltage controller  108 , which sets the DC voltage for switching regulator  104  and selects the output frequency for programmable clock frequency generator  106 .  
         [0033]    Processor complex  111  also communicates processor busy signal  103  to power management unit  110 . Processor busy signal  103  is asserted when processor complex  111  is performing a computational task. Otherwise, processor busy signal  103  is not asserted.  
         [0034]    Programmable clock frequency generator  106  can be implemented in a number of ways. One implementation uses multiple phase-lock loops (PLLs). Another implementation uses a single PLL, which includes divided outputs for the different frequencies (e.g., divide-by-two).  
         [0035]    In an alternative embodiment of the present invention, some or all of the power management unit  110 , frequency/voltage controller  108 , switching regulator  104  and programmable clock frequency generator  106  are implemented within processor complex  111  through software.  
         [0036]    When the processors are not executing computationally intensive tasks, the system operates processor complex  111  at low frequency and voltage levels. Note that for typical users and applications, the ratio between idle or near-idle time and computationally intensive time is high. Processor complex  111  therefore generally operates at the lower frequency and voltage for a significant portion of its overall operating time.  
         [0037]    Heat sink  112  has sufficient capacity to dissipate the thermal energy generated by processor complex  111  while processor complex  111  is operating at a maximum-sustainable speed. When processor complex  111  is operating at lower speeds the excess thermal energy dissipation capacity of the heat sink  112  leads to a lower operating temperature.  
         [0038]    Process of Selectively Controlling Operating Frequency and Voltage  
         [0039]    [0039]FIG. 2 presents a flowchart illustrating the process of controlling an operating frequency and voltage for an electronic circuit in accordance with an embodiment of the present invention.  
         [0040]    The process starts with the electronic circuit operating in a low-power state ( 200 ). In the low-power state, the electronic circuit is operating with low voltage and frequency (for example, a voltage of 1.1V and a frequency of 800 MHz), thereby minimizing power consumption.  
         [0041]    When the electronic circuit starts to perform computational work, timer[ 1 ] is activated ( 201 ). While timer[ 1 ] is counting down, the electronic circuit continues to operate in the low-power state.  
         [0042]    When timer[ 1 ] expires, the electronic circuit enters a first-intermediate state by increasing the voltage to a first-intermediate voltage, such as 1.2 V, increasing the frequency to a first-intermediate frequency, such as 1 GHz. and starting timer[ 2 ] ( 202 ). In the first-intermediate state, the power consumption of the electronic circuit is below its maximum level, but the performance is also below its maximum level.  
         [0043]    When timer[ 2 ] expires, the electronic circuit enters the maximum-sustainable power state by increasing the voltage to a maximum sustainable voltage, such as 1.3 V, increasing the frequency to a maximum sustainable frequency, such as 1.2 GHz, and starting timer[N] ( 203 ). In the maximum-sustainable power state, the power consumption and performance of the electronic circuit are at the highest levels that the circuit can maintain continuously.  
         [0044]    When timer[N] expires, if the thermal energy level of the electronic circuit is above a threshold value, the circuit remains in the maximum-sustainable power state ( 205 ). Alternatively, if the thermal energy level is below the threshold value when timer[N] expires, the electronic circuit enters the boosted power state by increasing the voltage to a voltage that exceeds the maximum sustainable voltage, such as 1.5 V, increasing the frequency to a frequency that exceeds the maximum sustainable frequency, such as 1.5 GHz, and starting a boosted power state timer ( 204 ). In this boosted power state, the power consumption and performance of the electronic circuit are above maximum sustainable levels. Note that the electronic circuit can only operate in this boosted power state for a limited time because the thermal energy of the electronic circuit exceeds the heat removing capacity of the cooling system. The thermal energy level of the system will consequently rise until it exceeds a threshold value.  
         [0045]    If the thermal energy level exceeds the threshold value while the electronic circuit is operating in the boosted power state, the electronic circuit immediately exits the boosted power state and returns to a maximum-sustainable power state ( 205 ).  
         [0046]    When the boosted power state timer expires, the electronic circuit reenters the maximum-sustainable power state by decreasing the voltage to a maximum sustainable voltage, such as 1.3 V, and decreasing the frequency to a maximum sustainable frequency, such as 1.2 GHz ( 205 ).  
         [0047]    Regardless of the state of operation, whenever the electronic circuit is no longer performing computational work, the electronic circuit immediately returns to the low-power state ( 200 ).  
         [0048]    Note that the single intermediate state can include one or more additional intermediate states, with different voltage and frequency levels.  
         [0049]    Balancing Circuit Performance and Power Savings  
         [0050]    [0050]FIG. 3A presents a graph of power level versus time in accordance with one embodiment of the present invention. The power-level axis of the graph indicates the operating power level of the electronic circuit as a percentage of the maximum sustainable level. The time axis indicates the progression of time.  
         [0051]    [0051]FIG. 3B presents a tabular form of the information presented graphically in FIG. 3A. The “Interval” and “Power Level” headings in FIG. 3B relate directly to the axis on in FIG. 3A. The “Power State” heading in FIG. 3B relates to the power state name associated with a given “Power Level.” The “Interval Time” shows the time that the electronic circuit resides in the associated “Power State.” The “Performance Level” heading in FIG. 3B shows the performance level of the electronic circuit as a percentage of the maximum sustainable performance level. The “Interval Gain or Loss” and the “Net Gain or Loss” in FIG. 3B are effective computational work gains and losses with respect to the possible computational work that could be completed by running the electronic circuit in the maximum-sustainable power state for the same time interval.  
         [0052]    In a given time interval, the electronic circuit performs an amount of computational work that is proportional to the operating frequency of the electronic circuit. Note that power level is approximately related to frequency by P∝V 2 f. Since power is proportional to frequency, the power level associated with a given power state is directly correlated to the amount of computational work that the electronic circuit can perform in that power state.  
         [0053]    As shown in FIG. 3B, in the “T1” interval, the electronic circuit initially operates in the low-power state. The system stays in the low-power state for 10 ms and operates at 25% power and 50% performance as illustrated in FIG. 3A. The effective computational work lost while operating in the low-power state is 5 ms, as shown in the “Interval Gain or Loss” column of interval “T1” of FIG. 3B. In other words, the electronic circuit has to run for an additional 5 ms in the maximum-sustainable power state to compensate for the work lost while executing in the low-power state.  
         [0054]    In the “T2” interval of FIG. 3B, the electronic circuit enters a first-intermediate power state. The system operates stays in the first-intermediate power state for 10 ms and operates at 50% power and 70% performance as illustrated in FIG. 3A. While operating in the first-intermediate power state, the electronic circuit loses 3 ms of computational work. The electronic circuit is now 8 ms behind, as shown in the “Net Gain or Loss” column for interval “T2” in FIG. 3B.  
         [0055]    In the “T3” interval of FIG. 3B, the electronic circuit enters the maximum-sustainable power state. The system stays in the maximum-sustainable power state for 10 ms and operates at 100% power and 100% performance as illustrated in FIG. 3A. Since the electronic circuit is operating in the maximum-sustainable power state, no computational work is lost. The electronic circuit remains 8 ms behind, as shown in the “Net Gain or Loss” column for interval “T3” in FIG. 3B.  
         [0056]    In the “T4” interval of FIG. 3B, the electronic circuit enters the boosted power state. The system stays in the boosted power state for 40 ms and operates at 145% power and 120% performance as illustrated in FIG. 3A. The computational work gained by operating in the boosted power state is 8 ms. Hence, the electronic circuit has recovered the computational work lost in the preceding states and is 0 ms behind, as shown in the “Net Gain or Loss” column for interval “T4” in FIG. 3B.  
         [0057]    The foregoing descriptions of embodiments of the present invention have been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit the present invention to the forms disclosed. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. Additionally, the above disclosure is not intended to limit the present invention. The scope of the present invention is defined by the appended claims.