Abstract:
A digital-to-analog converter includes a ladder circuit and transistors. A control voltage generating circuit is coupled to the transistors in a feedback configuration to control current flowing through the transistors. The control voltage generating circuit includes an operational amplifier coupled to a transistor. Using the control voltage generating circuit, the digital-to-analog converter of the present invention produces an analog output voltage resistant to variation in the DC forward current gain of the transistors.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a digital to analog converter (hereinafter referred to as D/A converter) suitable for integration. 
     2. Description of the Prior Art 
     FIG. 3 is an example of a circuit for showing an operational principle of a conventional D/A converter. The circuit comprises a ladder circuit comprising resistors and switching circuits. In FIG. 3, the circuit comprises a direct current reference voltage source 21 having a voltage V, resistors 311˜317 having resistances R or 2R, switches 331, 332, 333, 334 (S 1 , S 2 , . . . Sn) switched according to inputted bit information, constant current sources I 321, 322, 323, 324, an output voltage Vout of the D/A converter, an output terminal 70 from which an output voltage Vout is outputted, input terminals 341, 342, 343, 344, and binary digital input signals b 1 , b 2 , b n-1 , b n , respectively, inputted into the input terminals 341, 342, 343, 344. Here, the switches S 1 , S 2 , . . . Sn turn on when the binary digital input signals b 1 , b 2 , . . . b n-1 , b n  are &#34;1&#34;, and turn off when the binary digital input signals b 1 , b 2 , . . . b n-1 , b n  are &#34;0&#34;. 
     An operation of the D/A converter is explained below. FIG. 3 shows an example of an ideal D/A converter. First, in order to obtain the analog voltage Vout, impedances of respective nodes shown in FIG. 4 are obtained. FIG. 4 shows an example of a ladder circuit. 
     In FIG. 4, respective impedance of the right part of the ladder circuit seen from a point B1 and a point C1 is R, and impedance at a node A is considered to be a parallel circuit comprising the resistance R and a resistance 2R, which obtains the following equation: 
     
         R//2R=(2/3)·R 
    
     (i) In case that the respective input digital data signals b 1 , b 2 , b n-1 , b n  are 1, 0, 0, 0 as shown in FIG. 5, the output voltage is obtained as follows according to the above mentioned result. In FIG. 5, the switch S 1  turns on since the input digital signal b 1  is &#34;1&#34;, while all of other switches S 2 , . . . S n-1 , S4 turn off since all the input digital signals b 2 , . . . b n-1 , b n  are &#34;0&#34;. 
     Therefore, a voltage drop V A  between the direct current reference voltage source 21 and the node A caused by the resistor 311 is obtained as follows. 
     
         V.sub.A =(2/3)·R·I 
    
     Thus, voltage drops V B , V C , V D  after the stages of the node B are obtained as follows, respectively, ##EQU1## 
     Where, the voltage drop V C-1  is a voltage drop at an immediately preceding node to a node of the voltage drop V C . Thus, the voltage drops at respective resistors decrease by 1/2 as it goes down to the respective nodes B, C, and D. Therefore, the analog output voltage Vout at the output terminal 70 is obtained by a general equation (1). 
     
         Vout=V-V.sub.D =(1/2.sup.n-1)·(2/3)·R·I·b.sub.1( 1) 
    
     Where, n is a positive integer number such as 1, 2, 3 . . . . 
     (ii) Next, the output voltage, when the input digital signals b 1 , b 2 , b n-1 , b n , are 0, 1, 0, 0, respectively, as shown in FIG. 6, is obtained as follows. In FIG. 6, the switch S 2  turns on since the input digital signal b 2  is &#34;1&#34;, while all other switches S 1 , . . . S n-1 , Sn turn off since all the input digital signals b 1 , . . . , b n-1 , b n  are &#34;0&#34;. 
     Therefore, the voltage drop V B  between the direct current reference voltage source 21 and the node B of the resistor 311 is obtained as follows. 
     
         V.sub.B =(2/3)·R·I 
    
     Then, the voltage drops V C , V D  after the states of the node C are obtained, respectively, as follows. 
     
         V.sub.C =1/2×V.sub.C-1 
    
     
         V.sub.D =1/2×V.sub.C 
    
     Where, a voltage drop V C-1  is a voltage drop at an immediately preceding node to the node C. 
     Thus, the voltage drops at respective resistors decrease by 1/2 as it goes down to the respective nodes B, C, and D. Therefore, the analog output voltage Vout at the output terminal 70 is obtained by a general equation (2). 
     
         Vout=V-(1/2.sup.n-2)·(2/3)·R·I·b.sub.2( 2) 
    
     Where, n is a positive integer number such as 1, 2, 3 . . . . 
     (iii) Next, the output voltage, when the input digital signals b 1 , b 2 , b n-1 , b n  are 0, 0, 1, 0, respectively, as shown in FIG. 7, is obtained as follows. In FIG. 7, the switch S n-1  turns on since the input digital signal b 3  is &#34;1&#34;, while all other switches S 1 , S 2 , Sn turn off since all the input digital signals b 1 , b 2 , b n  are &#34;0&#34;. 
     Therefore, the voltage drop V C  between the direct current reference voltage source 21 and a node C of the resistor 315 is obtained as follows. 
     
         V.sub.C =(2/3)·R·I 
    
     Then, the voltage drop V D  at a node D is obtained as follows. 
     
         V.sub.D =1/2×V.sub.C 
    
     Thus, the voltage drops at respective resistors decrease by 1/2 as it goes down to the respective nodes C, D. Therefore, the analog output voltage Vout at the output terminal 70 is obtained by a general equation (3). 
     
         Vout=V-(1/2.sup.n-2)·(2/3)·R·I·b.sub.3( 3) 
    
     Where, n is a positive integer number, such as 1, 2, 3 . . . . 
     (iv) Next, the output voltage, when the input digital signals b 1 , b 2 , b 3 , b n  are 0, 0, 0, 1, respectively, as shown in FIG. 8, is obtained as follows. In FIG. 8, the switch S n  turns on since only the input digital signal b n  is &#34;1&#34;, while all other switches S 1 , S 2 , S n-1  turn off since all the input digital signals b 1 , b 2 , b 3  are &#34;0&#34;. 
     Therefore, the voltage drop V D  between the node C of the resistor 317 and the direct current reference voltage source 21 is obtained as follows. 
     
         V.sub.D =(2/3)·R·I 
    
     Thus, the voltage drops at respective resistors decrease by 1/2 as it goes down to the respective nodes C, D. Therefore, the output voltage Vout at the output terminal 70 is obtained by a general equation (6). 
     
         Vout =V-(1/2.sup.0)·(2/3)·R·I·b.sub.n( 4) 
    
     Where, n is a positive integer number, such as 1, 2, 3 . . . . 
     According to the above mentioned results, the output voltage Vout is obtained by combining the equations (1)˜(4). 
     
         Vout=V-(2/3)·R·I·{b.sub.n +(1/2.sup.1)·b.sub.n-1 + . . . +(1/2.sup.n-1)·b.sub.1 }=V-(2/3)·R·I·(1/2.sup.n-1)·{2.sup.n-1 ·b.sub.n +2.sup.n-2 ·b.sub.n-1 . . . +2.sup.0 ·b.sub.1 }                                       (6) 
    
     FIG. 9 shows a relationship between the input digital data signals (b1, b2, b3, b4) and the analog output signal Vout, when a value of n of above mentioned digital signals b 1 , b 2 , b 3 , . . . b n  is 4, for example. 
     As shown in FIG. 3, when the digital signals b 1 , b 2 , b 3 , b 4  are 0, 0, 0, 0, respectively, the output voltage Vout is equal to the voltage V of the direct current reference voltage source 21, since no current flows through S 1 , S 2 , S 3 , nor S4, respectively. 
     On the other hand, when the digital signals b 1 , b 2 , b 3 , b 4  are 1, 0, 0, 0 as shown in FIG. 5, the output voltage Vout is obtained by substituting 4 for n in the above equation (1). ##EQU2## 
     Where, ΔV is equal to (2/3) R·I and shows a value of a constant voltage drop. 
     Next, when the digital signals b 1 , b 2 , b 3 , b 4  are 0, 1, 0, 0 as shown in FIG. 6, the output voltage Vout is obtained by substituting 4 for n in the above equation (2). ##EQU3## 
     Next, when the digital signals b 1 , b 2 , b 3 , b 4  are 0, 0, 1, 0 as shown in FIG. 7, the output voltage Vout is obtained by substituting 4 for n in the above equation (3). ##EQU4## 
     Then, the output voltage Vout when the digital signals b 1 , b 2 , b 3 , b 4  are 0, 0, 0, 1 as shown in FIG. 8 is obtained by substituting 4 for n in the above equation (4). ##EQU5## 
     Furthermore, when the digital signals b 1 , b 2 , b 3 , b 4  are 1, 1, 0, 0, for example, the output voltage Vout is obtained as follows by superposing the above equation (7) and the above equation (8). 
     
         Vout=V-(1/8)ΔV-(1/4)ΔV 
    
     Furthermore, when the digital signals b 1 , b 2 , b 3 , b 4  are 1, 1, 1, 0, for example, the output voltage Vout is obtained by superposing the above equations (7), (8), (9). 
     
         Vout=V-(1/8)ΔV-(1/4)ΔV-(1/2)ΔV           (11) 
    
     By repeating the above operations, a step output voltage Vout as shown in FIG. 10 is obtained. In FIG. 10, when a combination of the switches S 1 , S 2 , . . . Sn in a horizontal axis is (0, 0, 0, 0), for example, an analog voltage in a vertical axis is V. And, when the combination of the switches S 1 , S 2 , . . . Sn in the horizontal axis is (0, 1, 0, 0), the analog voltage in the vertical axis is V-ΔV. Where, each unit voltage in the vertical axis is equal to ΔV. Furthermore, when the combination of the switches S 1 , S 2 , . . . Sn in the horizontal axis is (1, 1, 1, 1), the analog voltage in the vertical axis shows the lowest voltage VL. By increasing the number of stages of the switches, it is possible to reduce the unit voltage ΔV (=(2/3)RI), and obtain a smooth analog voltage. Here, the number of the switches is decided by the system requirement. In FIG. 10, the switch marked with a circle means &#34;turns on&#34;, while the switch with no mark means &#34;turned off&#34;. &#34;On-off&#34; of the respective switches correspond to digital values at the bottom of the matrix table. 
     FIG. 9 shows an example in which the conventional D/A converter of FIG. 3 is realized in an actual IC circuit. In FIG. 9, the D/A converter comprises direct current reference voltage sources 21 and 22 (each having a voltage V and a voltage Vref), resistors 43˜53 (each having resistances R, 2R or R E ), and switching transistors (Q1a, Q1b), (Q2a, Q2b) . . . (Qna, Qnb), corresponding to the switches S 1 , S 2 , . . . Sn of FIG. 3, respectively. The D/A converter further comprises an output terminal 70 from which an analog output voltage Vout is outputted, input terminals 11, 12, 13, 14, binary digital input signals b 1 , b 2 , b n-1 , b n  inputted into the input terminals 11, 12, 13, 14, respectively, and the analog output voltage Vout of the D/A converter. 
     Bit information of the digital signals b 1 , b 2 , . . . b n  is inputted into the input terminals 11, 12, 13, 14. Binary number logical voltages of &#34;1 or high&#34; or &#34;0 or low&#34; are used as this bit information. For example, when b 1  is equal to 1 and V b1  &gt;&gt;Vref, where V b1  is a voltage applied to a base of the transistor Q1b and Vref is a voltage of the direct current reference voltage source 22, the transistor Q1b turns on, while the transistor Q1a turns off, and then no current flows through the transistor Q1a. 
     When b 1  is equal to 0 and V b1  &lt;&lt;Vref, where V b1  is a voltage applied to a base of the transistor Q1b and Vref is a voltage of the direct current reference voltage source 22, the transistor Q1b turns off, while the transistor Q1a turns on, and therefore, a current I C  flows through the transistor Q1a. 
     As is clear from the above explanation, turning on of the transistor Q1a is equivalent to turning on of the switch S 1  of FIG. 3, therefore, a voltage at a node A of FIG. 9 is the same as that of FIG. 3 as follows. 
     
         V.sub.A =(2/3)·R·I 
    
     In the same way, any one of the digital voltage &#34;1&#34; or &#34;0&#34; is applied to the input terminals 11, 12, 13, 14 as digital signals b 2 , b 3 , . . . b n . By substituting the current I C  flowing through the respective transistors Q1a, Q2a, . . . Qna by a current I, the above mentioned equation (6) is obtained in the same way as in FIG. 3. 
     It is generally known that a relationship between a base current I B  and a collector current I C  is expressed as follows. 
     
         I.sub.C /I.sub.B =h.sub.FE 
    
     Therefore, the collector current I C  of the switching transistor Q1a is obtained as follows. 
     
         I.sub.C =(Vref-V.sub.BE)·h.sub.FE /{R.sub.E ·(1+h.sub.FE)}(12) 
    
     Assuming I C  =I and the equation (12) is substituted for the equation (6), the following equation is obtained. 
     
         Vout=V-(2/3)·R·(1/2.sup.n-1)· (Vref-V.sub.BE).multidot.h.sub.FE /{R.sub.E ·(1+h.sub.FE)}!·{2.sup.n-1 ·b.sub.n +2.sup.n-2 ·b.sub.n-1 + . . . +2.sup.0 ·b.sub.1 }                                       (13) 
    
     Since the equation (13) contains the term of h FE  /{R E  ·(1+h FE )}, the output voltage Vout depends on h FE  of the transistors. Therefore, it has been difficult to obtain the output voltage Vout as initially designed because of the dispersion caused during manufacturing or by the variation of the temperature. 
     FIG. 11 shows a temperature characteristic in relation to the digital bit input and the analog output voltage Vout in the D/A converters. Since the output voltage Vout depends on h FE  of the transistors in the conventional D/A converter as explained above, the output voltage Vout decreases for the same digital input value if the operation temperature of the D/A converter changes from T° C. to T1° C., for example. 
     Furthermore, since each h FE  of the transistors is different because of dispersion caused by the difference of the manufacturing lot, the problem has occurred in that the output voltage Vout of the D/A converter differs from that of another D/A converter even though they operate at the same temperature. 
     SUMMARY OF THE INVENTION 
     The present invention aims to solve the above mentioned problems. The present invention provides the D/A converter which does not depend on h FE  of the transistor, by adding a control circuit comprising resistors and transistors and an operational amplifier to the conventional D/A converter circuit, by comparing an output of the above mentioned control circuit with a voltage of the reference direct current source by the operational amplifier, and by providing an output of the operational amplifier to the input of the control circuit and the D/A converter. 
     According to one aspect of the invention, a digital to analog converter includes a ladder circuit comprising resistive elements. Each resistive element includes a first end connected to a first end connected to a first. direct current reference voltage source and a second end. A plurality of switching elements are connected the second ends of the resistors. The switching elements are turned on or turned off by digital bit inputs, comprises. A control voltage generating circuit includes a transistor having the same characteristics as the switching elements in the digital to analog converter and an operational amplifier for comparing a voltage of the transistor with a reference voltage of a second direct current reference voltage source by feeding back the voltage of the transistor. An output of the operational amplifier is used for controlling the switching elements of the digital to analog converter. 
     According to another aspect of the invention, a digital to analog converter has a control voltage generating circuit, which comprises: a transistor includes a first electrode connected to the first direct current reference voltage source through a resistor and a second electrode connected to ground through a resistor and an operational amplifier. The operational amplifier includes a non-inverted terminal connected to the first electrode of the transistor, an inverted electrode connected to a second direct current reference voltage source, and an output terminal commonly connected to a third electrode of the transistor and control electrodes of the plurality of switching elements of the digital to analog converter. An analog output is obtained from a first electrode of the last stage switching element by turning on or turning off the plurality of switching elements in response to the digital bit inputs. 
     According to further aspect of the invention, a digital to analog converter having a ladder circuit includes resistive elements. Each resistive element includes a first end connected to a first direct current reference voltage source and a second end. A plurality of switching elements are connected to the second ends. The switching elements comprise first and second transistors. The first transistors have first electrodes connected to nodes on corresponding stages of the ladder circuit, second electrodes connected to ground through resistors, and third electrodes to which control voltages are applied. The second transistors have first electrodes directly connected to the first direct current reference voltage source, second electrodes commonly connected to the second electrodes of the second switching elements, and third electrodes into which digital inputs are inputted. A control voltage generating circuit comprises a transistor having a first electrode connected to the first direct current reference voltage source through a resistor and a second electrode connected to ground through a resistor and an operational amplifier. The operational amplifier includes a non-inverted terminal connected to the first electrode of the transistor, an inverted terminal connected to a second direct current reference voltage source, and an output terminal commonly connected to the third electrode of the transistor and the third electrodes of the second plurality of switching elements. An wherein an analog output is obtained from a first electrode of the last stage switching clement by turning on or turning off the plurality of switching elements in response to the plurality of digital bit inputs through the third switching elements. 
     According to further aspect of the invention, a digital to analog converter having a ladder circuit includes a plurality of resistive elements. Each resistive element includes a first end connected to a first direct current reference voltage source and a second end. A plurality of switching elements are connected to the second end. The switching elements are turned on or turned off by digital bit inputs. An operational amplifier compares a voltage fed back from the last stage switching element with a voltage of a second direct current reference voltage source. A transistor having same characteristic as that of the switching elements in the digital to analog converter is coupled to the operational amplifier. Output of the operational amplifier is used for controlling the switching elements of the digital to analog converter and the transistor. 
     According to further aspect of the invention, a digital to analog converter comprises an operational amplifier having a non-inverted terminal connected to a first electrode of the switching element on the last stage. A inverted terminal of the operational amplifier is connected to the second direct current reference voltage source. A transistor includes first and second electrodes. The first electrode is connected to the first direct current reference voltage source through a resistor. The second electrode connected to ground through a resistor. An output terminal of the operational amplifier is commonly connected to control electrodes of the plurality of switching elements in the digital to analog converter and a control electrode of the transistor. An analog output is obtained from the first electrode of the transistor by turning on or turning off the plurality of switching elements by the plurality of digital bit inputs. 
     According to further aspect of the invention, a digital to analog converter includes a ladder circuit comprising resistive elements. Each resistive element includes a first end connected to a first direct current reference voltage source. A first plurality of switching elements are connected to respective nodes of the ladder circuit which are not connected to the first direct current reference voltage source. The first switching elements comprise first and second transistors. The first transistors have first electrodes connected to respective nodes of the ladder circuit, second electrodes connected to ground through resistors, and third electrodes to which control voltages are applied. The second transistors comprise first electrodes directly connected to the first direct current reference voltage source, second electrodes commonly connected to the second electrodes of the second switching elements, and third electrodes into which digital inputs are inputted. An operational amplifier includes a non-inverted terminal connected to the first electrodes of the first transistors and an inverted terminal connected to a second direct current reference voltage source. A transistor includes a first electrode connected to the first direct current reference voltage source through a resistor, a second electrode connected to ground through a resistor. An output terminal of the operational amplifier is commonly connected to the third electrodes of the second plurality of switching elements and a third electrode of the transistor. An analog output is obtained from the first electrode of the transistor by turning on or turning off the second plurality of switching elements by the plurality of digital bit inputs through the third switching elements. 
     Preferably, the switching elements and the transistor in the D/A converter are comprised of bipolar transistors, where the first electrodes are collector, the second electrodes are emitters, and the third electrodes are bases. 
     Preferably, the switching elements and the transistor in the D/A converter are comprised of MOS transistors, where the first electrodes are drains, the second electrodes are sources, and the third electrodes are gates. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a D/A converter of a first embodiment of the present invention. 
     FIG. 2 shows a D/A converter of a second embodiment of the present invention. 
     FIG. 3 is a circuit configuration for explaining an operational logic of a D/A converter. 
     FIG. 4 is a circuit configuration for obtaining impedances at respective nodes in FIG. 3. 
     FIG. 5 is a circuit configuration for explaining an operational logic of a D/A converter. 
     FIG. 6 is a circuit configuration for explaining an operational logic of a D/A converter. 
     FIG. 7 is a circuit configuration for explaining an operational logic of a D/A converter. 
     FIG. 8 is a circuit configuration for explaining an operational logic of a D/A converter. 
     FIG. 9 shows an example in which the D/A converter of FIG. 3 is realized in an actual IC circuit. 
     FIG. 10 shows a relationship between a digital bit input and an analog output voltage Vout in a D/A converter. 
     FIG. 11 shows a temperature characteristic of a digital bit input and an analog output voltage Vout in D/A converters. 
     FIG. 12 shows an example of a circuit configuration of a direct current reference voltage source used in a D/A converter. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Embodiment 1 
     FIG. 1 shows a circuit configuration of a first embodiment of the present invention. In FIG. 1, a D/A converter comprises a direct current reference voltage sources 21, 22 (each having a voltage V and a voltage Vref), an operational amplifier 30, a transistor Qr, resistances Rr and R Er , resistors 43˜53 (each having resistances R, 2R, and RE), switching transistors Q1a, Q1b, Q2a, Q2b . . . Qna, Qnb, bit information input terminals b 1 , b 2 , . . . b n , an output terminal 70, a control circuit 110, and resistors 41, 42 (each having resistances Rr and R Er ). The elements having the same reference numbers in FIG. 1 are the same portions or the corresponding portions in FIG. 9. Accordingly the detailed explanation of the same portions is omitted. 
     In FIG. 1, an emitter of the transistor Qr in the control circuit 110 is connected to ground through the resistance R Er . A collector of the transistor Qr is connected to the direct current reference voltage source 21 through the resistance Rr and to a non-inverted input terminal of the operational amplifier 30. The direct current reference voltage source 22 having the voltage Vref is connected to an inverted input terminal of the operational amplifier 30. An output of the operational amplifier 30 is connected to a base of the transistor Qr and also to respective bases of the transistors Q1a, Q2a, . . . Qna which constitute the D/A converter. 
     The transistors Q1a, Q2a, . . . Qna have respective collectors connected to the direct current reference voltage source 21 through the resistors 43, 46, 49, 52 and respective emitters connected to ground through the resistances R E . The transistors Q1b, Q2b, . . . Qnb have respective collectors connected directly to the direct current reference voltage source 21, respective emitters connected to ground together with the emitters of the transistors Q1a, Q2a, . . . Qna through the respective resistances R E , and respective bases connected to the digital input terminals b 1 , b 2 , b n-1 , b n  into which one of binary digital input signals &#34;1&#34; and &#34;0&#34; is inputted. 
     In the operational amplifier 30 of the circuit configuration mentioned above, an output voltage V3 varies so that a collector voltage V2 of the transistor Qr at a node E is equal to the voltage Vref of the direct current reference voltage source. The output voltage V3 of the operational amplifier 30 is provided to all of the bases of the transistors Q1a, Q2a . . . Qna which constitute the D/A converter. 
     The way to obtain an analog output voltage Vout in the D/A converter of the present invention is explained below. In FIG. 1, a collector current I Cr  of the transistor Qr is obtained in the first place before computing the output voltage Vout. The output voltage V3 of the operational amplifier 30 is obtained as follows. 
     
         V3=A(V2-Vref) 
    
     Therefore, the voltage V2 of the non-inverted terminal of the operational amplifier 30 is obtained as follows. 
     
         V2=(V3/A)+Vref 
    
     On the assumption that an amplification factor A of the operational amplifier 30 is infinity (A=∞), the voltage V2 is obtained according to the above equation as follows. 
     
         V2=Vref 
    
     Furthermore, the voltage V2 is obtained by subtracting a voltage drop of the resistance Rr caused by the current I Cr  flowing through the transistor Qr from a voltage V of the direct current reference voltage source 21. 
     
         V2=V-Rr·I.sub.Cr 
    
     The current I Cr  is obtained by substituting Vref for V2 in the above equation as follows. 
     
         V-Vref=Rr·I.sub.Cr 
    
     Therefore, 
     
         I.sub.Cr =(V-Vref)/Rr                                      (14) 
    
     Where, A is an amplification factor of the operational amplifier 30, and V is a reference voltage of the direct current reference voltage source 21. 
     It is apparent from the equation (14) that the collector current I Cr  of the transistor Qr does not depend on h FE  of the transistor Qr, but is dominated only by the resistance. 
     On the other hand, since the output voltage V3 of the operational amplifier 30 is provided to the respective bases of the transistors Q1a, Q2a, . . . Qna which constitute the D/A converter, the respective collector currents I C  of the transistors Q1a, Q2a, . . . Qna are proportional to the collector current I Cr  of the transistor Qr. Assuming α is a proportional constant, the collector current I Cr  is expressed by the following equation (15). 
     
         I.sub.C                                                    (15) 
    
     Therefore, the output voltage Vout of the D/A converter is obtained as follows using the equations (6), (14), if substituted I for I C . ##EQU6## 
     By using elements of the same characteristics (constructed in the same diffusion condition, for example) such as the same resistance values R and Rr, dispersion caused during manufacturing and a temperature coefficient are of the same inclination. Therefore, (R/Rr) becomes constant. 
     Therefore, the equation (16), the analog output voltage Vout of the D/A converter is determined only by the voltages V, Vref of the direct current reference voltage sources, but not depending on h FE  of the transistor. 
     FIG. 11 shows a temperature characteristic of the analog output voltage Vout for the digital bit input in the D/A converter of the present invention as well as the temperature characteristic of the analog output voltage Vout for the digital bit input in the conventional D/A converter. As explained above, since the output voltage Vout of the D/A converter of the present invention does not depend on h FE  of the transistor, the variation of the output voltage Vout is very small even if the temperature of the D/A converter changes from T° C. to T1° C. 
     Since the output voltage Vout of the present invention is not influenced by h FE  of the transistor as explained above, it is advantageous that the analog output voltage Vout varies little even if h FE  of the transistor varies because of dispersion caused during manufacturing or even if the D/A converter in the apparatus is exchanged for another one. 
     The direct current reference voltage sources 21, 22 may be substituted by band-gap reference voltage generating circuits shown in FIG. 12. In FIG. 12, the band-gap reference voltage generating circuit comprises resistors 401, 402, 403, voltage sources 421, 422, transistors Q10, Q11, Q12, a constant current source 410, and an output terminal 430 of the direct current reference voltage source. In FIG. 12, output voltage Vref is obtained as follows. 
     
         Vref=(R2/R3)·(kT/q)·1n(n·R2/R1)+V.sub.BE3 
    
     In the above equation, the output voltage Vref is determined by R2/R3, R2/R1, and V BE3 , since (kT/q) is constant. If these resistive elements 401˜403 are formed on the same substrate, since resistive varying components of resistors R1, R2, R3 caused by temperature have the same temperature coefficient, the ratios of the resistors R2/R3 and R2/R1 are independent of the temperature. In addition, since V BE3  is a base-emitter voltage of the transistor Q11 and is constant, the output voltage Vref is constant. Since this band-gap reference voltage generating circuit is well known as a constant voltage source, further explanation is omitted. 
     Embodiment 2 
     FIG. 2 shows a D/A converter of a second invention of the present invention. The D/A converter comprises a transistor Qo, resistances R E  &#39;, RL, and an analog output voltage Vout of the D/A converter. The elements having the same reference numbers in FIG. 2 are the same portions or the corresponding portions in FIG. 1. Accordingly the detailed explanation of the same portions is omitted. 
     In FIG. 2, a collector of a transistor Qna is connected to a non-inverted input terminal of an operational amplifier 30. A direct current reference voltage source 22 having a reference voltage Vref is connected to an inverted input terminal of the operational amplifier 30. Output of the operational amplifier 30 is provided to respective bases of transistors Q1a, Q2a, . . . Qna which constitute the D/A converter. An output voltage V4 of the operational amplifier 30 is also provided to a base of the transistor Qo. An output terminal 70 is a terminal from which the output voltage Vout is outputted. Binary digital input signals b 1 , b 2 , b 3 , b n  are inputted into input terminals 11, 12, 13, 14, respectively. 
     The transistors Q1a, Q2a, . . . Qna have respective collectors connected to a direct current reference voltage source 21 through the respective resistors 43, 46, 49, 52 and respective emitters connected to ground through resistances R E . Transistors Q1b, Q2b, . . . Qnb have respective collectors directly connected to the direct current reference voltage source 21, emitters connected to ground together with the emitters of the transistors Q1a, Q2a . . . Qna through the resistances R E , and respective bases connected to the digital input terminals 11˜14 into which one of binary digital input signals &#34;1&#34; and &#34;0&#34; is inputted. 
     Here, the respective transistors Q1a, Q2a . . . Qna turn on when the respective binary digital input signals b 1 , b 2 , . . . b n  are &#34;1&#34; and turn off whcn the respective binary digital input signals b 1 , b 2 , . . . b n  are &#34;0&#34;. 
     In the operational amplifier 30 of the circuit configuration explained above, the output voltage V4 of the operational amplifier 30 varies so that a collector voltage Vo of the collector (at a node D) of the transistor Qna becomes equal to the voltage Vref of the direct current reference voltage source 22. The output voltage V4 of the operational amplifier 30 is provided to all of the bases of the transistors Q1a, Q2a, . . . Qna which constitute the D/A converter. 
     The transistor Qo has a collector connected to the direct current reference voltage source 21 through the resistance RL and an emitter connected to ground through the resistance R E  &#39;. 
     By connecting the operational amplifier 30 as shown in FIG. 2, the output voltage V4 of the operational amplifier 30 is controlled so that the output terminal voltage Vo of the transistor Qna is equal to the voltage Vref of the direct current reference voltage source 22. This output voltage V4 of the operational amplifier 30 is also provided to the base of the transistor Qo. 
     The output voltage Vout of the D/A converter in FIG. 2 is computed as follows. First, the output voltage V4 of the operational amplifier 30 is decided. The output voltage Vo of the transistor Qna is fed back to the non-inverted terminal of the operational amplifier 30, and the output voltage Vo of the transistor Qna is thereby controlled to be equal to the voltage Vref of the direct current reference voltage source 22. Therefore, an equation (17) is obtained. 
     
         Vo=Vref                                                    (17) 
    
     By substituting the equation (17) for the equation (13) and assuming Vref=V4, an equation (18) is obtained. 
     
         Vo=Vref=V-(2/3)·R·(1/2.sup.n-1)· (V4-V.sub.BE).multidot.h.sub.FE /{R.sub.E &#39;·(1+h.sub.FE)}!·{2.sup.n-1 ·b.sub.n +2.sup.n-2 ·b.sub.n-1 + . . . +2.sup.0 b.sub.1 })                                                        (18) 
    
     Therefore, the output voltage V4 of the operational amplifier 30 is obtained as an equation (19) by deforming the equation (18). 
     
         V4=(3/2)·2.sup.n-1 ·(V-Vref)·(R.sub.E &#39;/R)·{(1+h.sub.FE)/h.sub.FE }/B+V.sub.BE         (19) 
    
     Where, B=2 n-1  ·b n  +2 n-2  ·b n-1  + . . . +2 0  ·b 1   
     On the other hand, a collector current Io of the transistor Qo is obtained as follows by substituting Io for I C  and V4 for Vref in the equation (12). 
     
         Io=(V4-V.sub.BE)·h.sub.FE /{R.sub.E &#39;·(1+h.sub.FE)}(20) 
    
     An equation (21) is obtained by substituting the equation (19) for the equation (20). 
     
         Io=(1/R.sub.E &#39;)·/{(3/2)·2.sup.n-1 ·(V-Vref)·(R.sub.E &#39;/R)·((1+h.sub.FE)/h.sub.FE)/B+V.sub.BE -V.sub.BE }·h.sub.FE /{R.sub.E &#39;·(1+h.sub.FE)}=(3/2)·2.sup.n-1 ·(V-Vref)·(1/R)·(1/B)          (21) 
    
     Therefore, the analog output terminal voltage Vout of the D/A converter is obtained as follows. 
     
         Vout=V-RL·Io                                      (22) 
    
     An equation (23) is obtained by substituting the equation (21) for the equation (22). ##EQU7## 
     In the equation (23), by using elements of the same characteristics (constructed in the same diffusion condition, for example) such as the same resistance values R and RL, dispersion caused during manufacturing and a temperature coefficient are of the same inclination. Therefore, (R/Rr) becomes constant. In this way, it is apparent from the equation (23) that the output terminal voltage Vout does not depend on h FE  of the transistors, since the output terminal voltage Vout is determined only by the voltages V, Vref of the respective direct current reference voltage sources 21, 22.