Abstract:
In a broadcasting satellite converter adapted to be connected to a BS tuner and fed with a power supply voltage signal from the broadcasting satellite tuner, a receiver circuit includes a mixer, and a plurality of local oscillators connected to the mixer to convert broadcasting satellite signals into intermediate frequency signals. The receiver circuit is controlled by a control circuit including a detector circuit and a selector circuit. The detector circuit detects whether a band switching pulse signal is superimposed on the pulse signal, and has a period counting circuit that produces numerical count data representing a period of a frequency of the band switching pulse signal. The selector circuit selectively drives one of the local oscillators in accordance with the numerical count data obtained in the detector circuit.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a converter, called a broadcasting satellite (BS) converter in this field, which is used to receive BS signals in a satellite broadcasting system, and more particularly relates to an improvement of a control circuit incorporated in the BS converter to select either a high frequency band or a low frequency band included in a reception frequency band used in the satellite broadcasting system.  
         [0003]     2. Description of the Related Art  
         [0004]     A reception system of a satellite broadcasting system includes a low noise down converter block (LNB) provided in a parabola antenna, and a set top box (STB) connected to the LNB through the intermediary of a coaxial cable. In this specification, the LNB will be referred to as a broadcasting satellite (BS) converter, and the STB will be referred to as a broadcasting satellite (BS) tuner.  
         [0005]     In recent years, a reception frequency band used in a satellite broadcasting system has been widened to accommodate digitization of the satellite broadcasting system and an increase in the number of channels thereof. For example, the widened reception frequency band is defined as one between 10.7 GHz and 12.75 GHz, and it is impossible to receive all broadcasting satellite (BS) signals (microwaves), included in the widened reception frequency band, with only one parabola antenna and one BS converter. In other words, it is necessary to prepare two parabola antennas and two BS converters before all the BS signals can be received and processed. Namely, the reception frequency band is divided into a low frequency band of 10.7 GHz to 11.7 GHz and a high frequency band of 11.7 GHz to 12.75 GHz, and the two parabola antennas and two BS converters are arranged for receiving and processing the respective low and high frequency bands.  
         [0006]     JP-A-H08-293812, corresponding to U.S. Pat. No. 5,649,311, discloses a prior art BS converter which is constituted so as to receive and process all the BS signals included in the reception frequency band. Namely, according to JP-A-H08-293812, it is possible to receive and process all the BS signals with a single parabola antenna and BS converter.  
         [0007]     This prior art BS converter is provided with a reception circuit for receiving and processing all the BS signals, and a control circuit for controlling the reception circuit. The reception circuit includes a mixer, and first and second local oscillators connected to the mixer. The first local oscillator inputs a first local frequency signal to the mixer, and the second local oscillator inputs a second local frequency signal to the mixer. The first local frequency signal features a lower frequency than that of the second local frequency signal. The control circuit selects which local oscillator should be driven.  
         [0008]     In particular, when a television set, which is connected to the BS converter through the intermediary of the BS tuner and the coaxial cable, is tuned to a channel to receive a BS signal included in the low frequency band of 10.7 GHz to 11.7 GHz, only the first local oscillator is driven by the control circuit so that the BS signals included in the low frequency band of 10.7 GHz to 11.7 GHz are converted into intermediate frequency signals featuring a frequency of 950 MHz to 2150 MHz.  
         [0009]     On the other hand, when the television set is tuned to a channel to receive a BS signal included in the high frequency band of 11.7 GHz to 12.75 GHz, only the second local oscillator is driven by the control circuit so that the BS signals included in the high frequency band of 11.7 GHz to 12.75 GHz are converted into intermediate frequency signals featuring a frequency of 950 MHz to 2150 MHz.  
         [0010]     Thus, by using the prior art BS converter, it is possible to receive and process all the BS signals by the single parabola antenna and BS converter. Nevertheless, the prior art BS converter is not satisfactory in that it is impossible to obtain reliable operation.  
         [0011]     In particular, when the television set is tuned to a channel to receive a BS signal included in the high frequency band of 11.7 GHz to 12.75 GHz, a band switching pulse signal featuring a duty factor of 50% is superimposed on a power supply voltage signal which is fed from the BS tuner to the BS converter through the coaxial cable. The control circuit includes a detector circuit for detecting whether the band switching pulse signal is superimposed on the power supply voltage signal, and a selector circuit for selectively driving the second local oscillator when the band switching pulse signal is detected by the detector circuit.  
         [0012]     However, in this prior art, the detector circuit is susceptible to large amplitude noise, such as a spike noise or the like. As a result, a malfunction of the detector circuit may occur. Namely, the control circuit may mistakenly select which local oscillator should be driven, as explained in detail hereinafter.  
         [0013]     Also, in the above-mentioned prior art, a band switching time, which is defined as a period of time measured from a time at which the television set is tuned to a channel to receive a BS signal included in the high frequency band to a time at which a picture is displayed on a screen of the television set based on the tuned channel, is relatively long. Namely, it takes a relatively long time to detect the band switching pulse signal by the detector circuit, as explained in detail hereinafter.  
       SUMMARY OF THE INVENTION  
       [0014]     Therefore, an object of the present invention is to provide a broadcasting satellite (BS) converter used to receive and process BS signals in a satellite broadcasting system, which is constituted such that it is possible to obtain a satisfactorily reliable operation.  
         [0015]     Another object of the present invention is to provide such a BS converter featuring a detector circuit which is constituted such that it is possible to rapidly detect superimposition of a band switching pulse signal on a power supply voltage signal.  
         [0016]     Another object of the present invention is to provide a control circuit that controls a receiver circuit included in such a BS converter.  
         [0017]     Yet another object of the present invention is to provide a detector circuit used in such a control circuit, which is not susceptible to various noises.  
         [0018]     In accordance with a first aspect of the present invention, there is provided a broadcasting satellite (BS) converter adapted to be connected to a broadcasting satellite tuner and fed with a pulse signal from the broadcasting satellite tuner. The BS converter comprises a receiver circuit including a mixer, and a plurality of local oscillators connected to the mixer to convert broadcasting satellite signals into intermediate frequency signals, and a control circuit that controls the receiver circuit. The control circuit includes a detector circuit that detects whether a band switching pulse signal is superimposed on the pulse signal. The detector circuit includes a period counting circuit that produces numerical count data representing a period of a frequency of the band switching pulse signal. The control circuit further includes a selector circuit that selectively drives one of the local oscillators in accordance with the numerical count data obtained in the detector circuit.  
         [0019]     In accordance with a second aspect of the present invention, there is provided a control circuit that controls a plurality of local oscillators, included in a receiver circuit of a broadcasting satellite converter, with a band switching pulse signal superimposed on a pulse signal fed from a broadcasting satellite tuner to the receiver circuit. The control circuit comprises a detector circuit that detects whether the band switching pulse signal is superimposed on the pulse signal, and the detector circuit includes a period counting circuit that produces numerical count data representing a period of a frequency of the band switching pulse signal. The control circuit further includes a selector circuit that selectively drives one of the local oscillators in accordance with the numerical count data obtained in the detector circuit.  
         [0020]     In accordance with a third aspect of the present invention, there is provided a detector circuit that detects whether a band switching pulse signal is superimposed on a pulse signal fed from a broadcasting satellite tuner to a receiver circuit of a broadcasting satellite converter. The detector circuit comprises a period counting circuit that produces numerical count data representing a period of a frequency of the band switching pulse signal.  
         [0021]     The period counting circuit may include an oscillator that outputs a series of clock pulses having a higher frequency than that of the band switching pulse signal, and a counter that counts the clock pulses output from the oscillator during the period of the frequency of the band switching pulse signal for the production of the numerical count data. In this case, the period counting circuit may further include a reset circuit that resets the counter when the counting of the clock pulses during the period of the frequency of the band switching pulse signal is completed.  
         [0022]     On the other hand, the period counting circuit may include an oscillator that outputs a series of clock pulses having a higher frequency than that of the band switching pulse signal, a first counter that counts the clock pulses output from the oscillator during a first level duration of the band switching pulse signal to thereby produce a first piece of numerical count data representing the first level duration of the band switching pulse signal, and a second counter that counts the clock pulses output from the oscillator during a second level duration of the band switching pulse signal to thereby produce a second piece of numerical count data representing the second level duration of the band switching pulse signal, with the first and second pieces of numerical count data forming the numerical count data. In this case, the period counting circuit may further include a first reset circuit that resets the first counter when the counting of the clock pulses during the first level duration of the band switching pulse signal is completed, and a second reset circuit that resets the second counter when the counting of the clock pulses during the second level duration of the band switching pulse signal is completed.  
         [0023]     The detector circuit may further comprise a high pass filter that is constituted such that the band switching pulse signal is allowed to pass therethrough, and a level detector circuit that detects a peak voltage of the band switching pulse signal so as to wave-shape the band switching pulse signal, the production of the numerical count data being carried out based on the wave-shaped band switching pulse signal. Preferably, the level detector circuit includes a comparator featuring a hysteresis characteristic for the wave-shaping of the band switching pulse signal.  
         [0024]     The detector circuit may further comprise a frequency determination circuit that determines whether the numerical count data is derived from the frequency of the band switching pulse signal. The frequency determination circuit may be formed as either a logic matrix circuit or a window-type digital comparator circuit. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0025]     The above objects and other objects will be more clearly understood from the description set forth below, with reference to the accompanying drawings, wherein:  
         [0026]      FIG. 1  is a block diagram of a prior art broadcasting satellite converter;  
         [0027]      FIG. 2  is a circuit diagram of a prior art detector circuit used in the prior art broadcasting satellite converter shown in  FIG. 1 ;  
         [0028]      FIG. 3A  is a graph showing a frequency/amplitude characteristic of a band pass filter used in the prior art detector circuit shown in  FIG. 2 ;  
         [0029]      FIG. 3B  is a graph showing a band switching time characteristic of the prior art detector circuit shown in  FIG. 2 ;  
         [0030]      FIG. 4  is a circuit diagram of a detector circuit, used in a first embodiment of a broadcasting satellite converter according to the present invention, which is substituted for the prior art detector circuit shown in  FIG. 1 ;  
         [0031]      FIG. 5  is a circuit diagram of both a period counting circuit and a frequency determination circuit included in the detector circuit shown in  FIG. 4 ;  
         [0032]      FIGS. 6A through 6H  are timing diagrams to explain an operation of the detector circuit shown in  FIG. 4 , when a band switching pulse signal is superimposed on a power supply voltage signal;  
         [0033]      FIG. 7A  is a graph showing a frequency/amplitude characteristic of the detector circuit shown in  FIG. 4 ;  
         [0034]      FIG. 7B  is a graph showing a band switching time characteristic of the detector circuit shown in  FIG. 4 ; and  
         [0035]      FIG. 8  is a circuit diagram of a frequency determination circuit which is included in a detector circuit used in a first embodiment of the broadcasting satellite converter according to the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0036]     Before description of an embodiment of the present invention, for better understanding of the present invention, a prior art broadcasting satellite (BS) converter, as disclosed in JP-A-H08-293812, will be now explained with reference to  FIGS. 1 and 2 .  
         [0037]     This prior art BS converter, generally indicated by reference  10 , is provided with a feed horn  12  associated with an exterior parabola antenna (not shown), and is connected to an interior broadcasting satellite (BS) tuner  14  through a coaxial cable  16 .  
         [0038]     The BS converter  10  comprises a power source circuit  18 , a receiver circuit  20 , a control circuit  22 , and a selector circuit  24 . In operation, a power supply voltage signal is fed from the BS tuner  14  to the BS converter  10  through the coaxial cable  16 , and is input to the power source circuit  18  and the selector circuit  24 . Although the power supply voltage signal is switched between a low voltage (e.g. 13 volts) and a high voltage (e.g. 18 volts) for the reasons stated in detail hereinafter, the power source circuit  18  always generates a constant power supply voltage (e.g. 4 volts) for operating the receiver circuit  20 , the control circuit  22 , and the selector circuit  24 .  
         [0039]     As shown in  FIG. 1 , the receiver circuit  20  includes a set of first and second primary amplifiers  26 V and  26 H, a secondary amplifier  28 , a mixer  30 , a set of first and second local oscillators  32 L and  32 H, and an amplifier  34 .  
         [0040]     Broadcasting satellite (BS) signals (microwaves), which are transmitted from a satellite, are converged on the feed horn  12  by the parabola antenna, and each of the BS signals is separated into a vertically polarized wave and a horizontally polarized wave. The vertically-polarized waves are fed to the first primary amplifier  26 V, and are amplified and output to the secondary amplifier  28  as BS signals featuring the vertical polarization. On the other hand, the horizontally-polarized waves are fed to the second primary amplifier  26 H, and are amplified and output to the secondary amplifier  28  as BS signals featuring the horizontal polarization. Note, as already stated above, the BS signals are included in a widened reception frequency band which is defined as one between 10.7 GHz and 12.75 GHz.  
         [0041]     In operation, only one of the first and second primary amplifiers  26 V and  26 H is driven, and the selector circuit  24  selects which primary amplifier  26 V or  26 H should be driven.  
         [0042]     In particular, for example, while a television set (not shown), connected to the BS tuner  14 , is tuned to a channel to receive a BS signal featuring the vertical polarization, the power supply voltage signal, input to the selector switch  24 , is switched from the high voltage (18 volts) to the low voltage (13 volts). At this time, a first drive control signal, which is output from the selector circuit  24  to the first primary amplifier  26 V, is maintained at a high level so that the first primary amplifier  26 V is driven. On the other hand, a second drive control signal, which is output from the selector circuit  24  to the second primary amplifier  26 H, is maintained at a low level so that the second primary amplifier  26 H is not driven. Namely, when the power supply voltage signal is switched from the high voltage (18 volts) to the low voltage (13 volts), only the first primary amplifier  26 V is driven by the selector circuit  24 .  
         [0043]     When the television set, connected to the BS tuner  14 , is tuned to a channel to receive a BS signal featuring the horizontal polarization, the power supply voltage signal, input to the selector switch  24 , is switched from the low voltage (13 volts) to the high voltage (18 volts). At this time, the first drive control signal, which is output from the selector circuit  24  to the first primary amplifier  26 V, is changed from the high level to a low level so that the driving of the first primary amplifier  26 V is stopped. On the other hand, the second drive control signal, which is output from the selector circuit  24  to the second primary amplifier  26 H, is changed from the low level to a high level so that the second primary amplifier  16 H is driven. Namely, when the power supply voltage is switched from the low voltage (13 volts) to the high voltage (18 volts), only the second primary amplifier  26 H is driven the selector circuit  24 .  
         [0044]     In short, the power supply voltage signal, which is switched between the low voltage (13 volts) and the high voltage (18 volts), serves as a pulse signal for selecting which primary amplifier  26 V or  26 H should be driven.  
         [0045]     Either the BS signals featuring the vertical polarization or the BS signals featuring the horizontal polarization are fed to the secondary amplifier  28 , and then the amplified BS signals are fed to the mixer  20  in which the BS signals are mixed with one of a first local frequency signal and a second local frequency signal which are output from the respective first and second local oscillators  32 L and  32 H. The first local frequency signal has a lower frequency than that of the second local frequency signal. When the BS signals are mixed with the first local frequency signal output from the first local oscillator  32 L, a part of the BS signals, which are included in a low frequency band of 10.7 GHz to 11.7 GHz, are converted into intermediate frequency signals BS-IF ( FIG. 1 ). When the BS signals are mixed with the second local frequency signal output from the second local oscillator  32 H, the remaining part of the BS signals, which are included in a high frequency band of 11.7 GHz to 12.75 GHz, are converted into intermediate frequency signals BS-IF ( FIG. 1 ).  
         [0046]     In either event, the intermediate frequency signals BS-IF are fed from the mixer  10  to the amplifier  34 , and the amplified intermediate frequency signals BS-IF are fed to the BS tuner  14  through the coaxial cable  16 . Note, for example, the intermediate frequency signals BS-IF have a frequency of 1 GHz.  
         [0047]     The control circuit  22  selects which local oscillator  32 L or  32 H should be driven. As shown in  FIG. 1 , the control circuit  22  includes a detector circuit  36  for detecting whether a band switching pulse signal is superimposed on the power supply voltage signal (13 volts or 18 volts), and a selector circuit  38  for selecting which local amplifier  32 L or  32 H should be driven on the basis of a detection result obtained in the detector circuit  36 . Note, the band switching pulse signal is defined as a tone signal having a frequency of 22±4 kHz.  
         [0048]     In particular, when the television set, connected to the BS tuner  14 , is tuned to a channel to receive a BS signal included in the low frequency band of 10.7 GHz to 11.7 GHz, the band switching pulse signal is not superimposed on the power supply voltage signal (13 volts or 18 volts) in the BS tuner  14 , and thus the band switching pulse signal cannot be detected by the detector circuit  36 . At this time, a first drive control signal, which is output from the selector circuit  38  to the first local frequency oscillator  32 L, is maintained at a high level so that the first local frequency oscillator  32 L is driven. On the other hand, a second drive control signal, which is output from the selector circuit  38  to the second local frequency oscillator  32 H, is maintained at a low level so that the second local frequency oscillator  32 H is not driven.  
         [0049]     In short, while the band switching pulse signal is not superimposed on the power supply voltage signal (13 volts or 18 volts), only the first local frequency oscillator  32 L is driven so that the BS signals, included in the low frequency band of 10.7 GHz to 11.7 GHz, are converted into the intermediate frequency signals BS-IF.  
         [0050]     When the television set, connected to the BS tuner  14 , is tuned to a channel to receive a BS signal included in the high frequency band of 11.7 GHz to 12.75 GHz, the band switching pulse signal is superimposed on the power supply voltage signal (13 volts or 18 volts) in the BS tuner  14 , and thus the band switching pulse signal can be detected by the detector circuit  36 . At this time, the first drive control signal, which is output from the selector circuit  38  to the first local frequency oscillator  32 L, is changed from the high level to a low level so that the driving of the first local frequency oscillator  32 L is stopped. On the other hand, the second drive control signal, which is output from the selector circuit  38  to the second local frequency oscillator  32 H, is changed from the low level to a high level so that the second local frequency oscillator  32 H is driven.  
         [0051]     In short, while the band switching pulse signal is superimposed on the power supply voltage signal (13 volts or 18 volts), only the second local frequency oscillator  32 H is driven so that the BS signals, included in the high frequency band of 11.7 GHz to 12.75 GHz, are converted into the intermediate frequency signals BS-IF.  
         [0052]      FIG. 2  shows a circuit diagram of the detector circuit  36 . As shown in this drawing, the detector circuit  36  includes a capacitor  40 , a band pass filter  42 , an amplifier  44 , a rectifier circuit  46 , an integrating circuit or low pass filter  48 , and a comparator  50 .  
         [0053]     For example, when the band switching pulse signal having the frequency of 22±4 kHz is superimposed on the power supply voltage signal (13 volts or 18 volts) in the BS tuner  14  by tuning the television set to a channel to receive a BS signal included in the high frequency band of 11.7 GHz to 12.75 GHz, the band switching pulse signal is input together with the intermediate frequency signals BS-IF to the band pass filter  42  through the capacitor  40 , but only the band switching pulse signal is allowed to pass through the band pass filter  42 . Then, the band switching pulse signal is input to the amplifier  44  so as to be amplified to a given voltage level.  
         [0054]     The amplified band switching pulse signal is rectified by the rectifier circuit  46 , and then an amplitude of the rectified band switching pulse signal is detected by the low pass filter  48 . Namely, both the rectifier circuit  46  and the low pass filter  48  function as an amplitude detector for detecting the amplitude of the band switching pulse signal, so that the detected amplitude is output as an amplitude voltage signal from the low pass filter  48  to the comparator  50 .  
         [0055]     In the comparator  50 , the amplitude voltage signal is compared with a predetermined reference voltage. The amplitude voltage signal, derived from the band switching pulse signal, is higher than the reference voltage of the comparator  50 , so that a high level signal is output from the comparator  50  to the selector circuit  38 . At this time, the drive control signal, which is output from the selector circuit  38  to the second local oscillator  32 H, is changed from the low level to the high level, whereas the drive control signal, which is output from the selector circuit  38  to the first local oscillator  32 L, is changed from the high level to the low level.  
         [0056]     Thus, as stated above, only the second local oscillator  32 H is driven so that the conversion of the BS signals, included in the high frequency band of 11.7 GHz to 12.75 GHz, into the intermediate frequency signals BS-IF is carried out.  
         [0057]     Of course, when the band switching pulse signal having the frequency of 22±4 kHz is not superimposed on the power supply voltage signal (13 volts or 18 volts), i.e. when the television set is tuned to a channel to receive a BS signal included in the low frequency band of 10.7 GHz to 11.7 GHz, the amplitude voltage signal, which is output from the low pass filter  48 , is lower than the reference voltage of the comparator  50 , so that a low level signal is output from the comparator  50  to the selector circuit  38 . At this time, the drive control signal, which is output from the selector circuit  38  to the first local oscillator  32 L, is changed from the low level to the high level, whereas the drive control signal, which is output from the selector circuit  38  to the second local oscillator  32 H, is changed from the high level to the low level.  
         [0058]     Thus, as stated above, only the first local oscillator  32 L is driven so that the conversion of the BS signals, included in the low frequency band of 10.7 GHz to 11.7 GHz, into the intermediate frequency signals BS-IF is carried out.  
         [0059]     In this prior art, the band pass filter  42  may have a frequency/amplitude characteristic as shown in a graph of  FIG. 3A . As is apparent from this graph, each of the side bands of the amplitude characteristic features a gradual slope, and thus the detector circuit  36  is susceptible to a noise having a large amplitude, such as a spike noise or the like, which is generated when the power supply voltage signal is switched between the low voltage (e.g. 13 volts) and the high voltage (e.g. 18 volts) or which is generated from internal combustion engines of motorcycles or automobiles. Of course, when the spike noise is introduced in the detector circuit  36 , a malfunction of the detector circuit  36  may occur. Namely, the control circuit  22  may mistakenly select which local oscillator  32 L or  32 H should be driven.  
         [0060]     Also, in addition to the side bands of the amplitude characteristic featuring the gradual slope, since the band switching pulse signal has a small peak value of 0.6±0.2 volts, a sensitivity of the detector circuit  36  for detecting the band switching pulse signal (22±4 kHz) is inferior.  
         [0061]     In short, in the prior art BS converter, it is impossible to obtain a satisfactorily reliable operation of the BS converter  10 .  
         [0062]     Note, in the above-mentioned prior art BS converter  10 , although a low pass filter may be substituted for the band pass filter  42 , the low pass filter is also susceptible to a noise having a large amplitude, such a spike noise or the like.  
         [0063]     Also, in the above-mentioned prior art, as shown in a graph of  FIG. 3B , the detector circuit  36  may have a band switching time characteristic with respect to a level of the band switching pulse signal (BSPS) output from the rectifier circuit  46 . As stated hereinbefore, the band switching time is defined as a period of time measured from a time at which the television set is tuned to a channel to receive a BS signal included in the high frequency band to a time at which a picture is displayed on a screen of the television set based on the tuned channel. As is apparent from the graph of  FIG. 3B , the smaller the level of the band switching pulse signal, the longer the band switching time. In short, it takes a relatively long time to detect the band switching pulse signal by the prior art detector circuit  36 .  
       First Embodiment  
       [0064]     Next, with reference to  FIG. 4 , a first embodiment of a broadcasting satellite (BS) converter according to the present invention is explained below.  
         [0065]     When this embodiment of the BS converter according to the present invention is illustrated in a block diagram, it is substantially identical to the block diagram shown in  FIG. 1 , except that a detector circuit, generally indicated by reference  52  in  FIG. 4 , is substituted for the detector circuit  36  shown in  FIG. 2 .  
         [0066]     As shown in  FIG. 4 , the detector circuit  52  includes a capacitor  54 , an amplifier circuit  56 , a level detector circuit  58 , a period counting circuit  60 , and a frequency determination circuit  62 .  
         [0067]     The capacitor  54  prevents the inputting of the power supply voltage signal (13 volts or 18 volts) to the detector circuit  52 . The amplifier circuit  56  includes an amplifier  56 A, and resistors associated with the amplifier  56 A. Namely, both the capacitor  54  and the amplifier circuit  56  form a high pass filter, so that a high frequency signal is allowed to be input to the level detector circuit  58 .  
         [0068]     Note, such a high frequency signal may be the band switching pulse signal (22±4 kHz) superimposed on the power supply voltage signal or a spike noise superimposed on the power supply voltage signal.  
         [0069]     The level detector circuit  58  includes a comparator  58 A featuring a hysteresis characteristic, and resistors associated with the comparator  58 A. The level detector circuit  58  removes noises from the high frequency signal, and wave-shapes the high frequency signal output from the amplifier circuit  56 . The wave-shaped high frequency signal is output from the level detector circuit  58  to the period counting circuit  60 .  
         [0070]     The period counting circuit  60  includes a first binary counting circuit  60 A, a second binary counting circuit  60 B, a free-running oscillator (OSC)  60 A, and a one-half frequency divider  60 B.  
         [0071]     The wave-shaped high frequency signal is input to both the first and second binary counting circuits  60 A and  60 B. In this embodiment, the free-running oscillator  60 C outputs a series of clock pulses having a frequency of 440 kHz to the one-half frequency divider  60 B, in which the series of clock pulses having a frequency of 440 kHz is converted into a series of clock pulses having a frequency of 220 kHz. As shown in  FIG. 4 , the series of clock pulses having the frequency of 220 kHz is also input to both the first and second binary counting circuits  60 A and  60 B.  
         [0072]     In the first binary counting circuit  60 A, during a high level duration of the wave-shaped high frequency signal, a number of the clock pulses (220 kHz), input to the first binary counting circuit  60 A, is counted, and the counted clock pulses are output as 4-bit data from the first binary counting circuit  60 A, with the 4-bit data representing the high level duration of the wave-shaped high frequency signal.  
         [0073]     On the other hand, in the second binary counting circuit  60 B, during a low level duration of the wave-shaped high frequency signal, a number of the clock pulse (220 kHz), input to the second binary counting circuit  60 B, is counted, and the counted clock pulses are output as 4-bit data from the first binary counting circuit  60 B, with the 4-bit data representing the low level duration of the wave-shaped high frequency signal.  
         [0074]     The frequency determination circuit  62  includes a first logic matrix circuit  62 A, a second logic matrix circuit  62 B, and an AND-gate  62 C. Note, the first and second logic matrix circuit  62 A and  62 B are essentially identical to each other.  
         [0075]     The first logic matrix circuit  62 A determines whether the 4-bit data, output from the first binary counting circuit  60 A, is derived from the band switching pulse signal (22±4 kHz). When it is determined by the first logic circuit  62 A that the 4-bit data is derived from the band switching pulse signal, the first logic circuit  62 A outputs a high level signal to the AND-gate  62 C. When it is determined by the first logic circuit  62 A that the 4-bit data is not derived from the band switching pulse signal, the first logic circuit  62 A outputs a low level signal to the AND-gate  62 C.  
         [0076]     On the other hand, the second logic matrix circuit  62 B determines whether the 4-bit data, output from the second binary counting circuit  60 B, is derived from the band switching pulse signal (22±4 kHz). When it is determined by the second logic circuit  62 B that the 4-bit data is derived from the band switching pulse signal, the second logic circuit  62 B outputs a high level signal to the AND-gate  62 C. When it is determined by the second logic circuit  62 B that the 4-bit data is not derived from the band switching pulse signal, the second logic circuit  62 B outputs a low level signal to the AND-gate  62 C.  
         [0077]      FIG. 5  shows the period counting circuit  60  and the frequency determination circuit  62  in detail.  
         [0078]     The first binary counting circuit  60 A includes an AND-gate  64 A, a binary counter  66 A, a latch circuit  68 A, a reset circuit  70 A, and a buffer  72 A, and these elements are arranged as shown in  FIG. 5 .  
         [0079]     On the other hand, the second binary counting circuit  60 B includes an inverter  63 B, an AND-gate  64 B, a binary counter  66 B, a latch circuit  68 B, a reset circuit  70 B, and a buffer  72 B, and these elements are arranged as shown in  FIG. 5 .  
         [0080]     The first logic matrix circuit  62 A includes four inverters  74 A 1 ,  74 A 2 ,  74 A 3  and  74 A 4 , five AND-gates  76 A 1 ,  76 A 2 ,  76 A 3 ,  76 A 4  and  76 A 5 , and an OR-gate  78 A, and these elements are arranged as shown in  FIG. 5 .  
         [0081]     On the other hand, the first logic matrix circuit  62 B includes four inverters  74 B 1 ,  74 B 2 ,  74 B 3  and  74 B 4 , five AND-gates  76 B 1 ,  76 B 2 ,  76 B 3 ,  76 B 4  and  76 B 5 , and an OR-gate  78 V, and these elements are arranged as shown in  FIG. 5 .  
         [0082]     Next, with reference to a timing chart of  FIG. 6 , an operation of the detector circuit  52  will be now explained below.  
         [0083]     For example, when the band switching pulse signal having the frequency of 22±4 kHz is superimposed on the power supply voltage signal (13 volts or 18 volts) in the BS tuner  14  by tuning the television set to a channel to receive a BS signal included in the high frequency band of 11.7 GHz to 12.75 GHz, the band switching pulse signal is input to the amplifier circuit  56  through the capacitor  54 . Namely, the band switching pulse signal is amplified to a given voltage level by the amplifier  56 A, and the amplified band switching pulse signal is input to the level detector circuit  58 .  
         [0084]     In the level detector circuit  58 , the amplified band switching pulse signal is compared with a predetermined threshold voltage by the comparator  58 A. Since the threshold voltage is previously set so as to be lower than a peak voltage of the amplified band switching pulse signal, a pulse signal, having substantially the same frequency as that (22±4 kHz) of the band switching pulse signal, is output from the level detector circuit  58 .  
         [0085]     Thus, although the pulse signal, which is output from the level detector circuit  58 , may be referred to as a band switching pulse signal, this band switching pulse signal is free from the various noises involved in the original band switching pulse signal, due to the hysteresis characteristic of the comparator  58 A. In short, the band switching pulse signal is wave-shaped by the comparator  58 A, and the wave-shaped band switching pulse signal is output to both the first and second binary circuits  60 A and  60 B of the period counting circuit  60 .  
         [0086]     Note, the wave-shaped band switching pulse signal may have a duty factor of approximately 50%, because the original band switching pulse signal features a duty factor of 50%, as already stated hereinbefore. Namely, the wave-shaped band switching pulse features a high level duration and a low level duration which are equal to each other, as is apparent from the timing chart of  FIG. 6 .  
         [0087]     In the first binary counting circuit  60 A, the wave-shaped band switching pulse signal is input to one input terminal of the AND-gate  64 A and an input terminal of the reset circuit  70 A, as shown in a timing diagram of  FIG. 6A .  
         [0088]     On the other hand, in the second binary counting circuit  60 B, the wave-shaped band switching pulse signal is input to one input terminal of the AND-gate  64 B through the inverter  63 B, and to an inverted input terminal of the reset circuit  70 B. Namely, the wave-shaped band switching pulse is input as an inverted band switching pulse signal to both the AND-gate  64 B and the reset circuit  70 B, as shown in a timing diagram of  FIG. 6B .  
         [0089]     Further, the series of clock pulses (220 kHz) is input from the one-half frequency divider  60 D to both the other input terminals of the AND gates  64 A and  64 B, as shown in a timing diagram of  FIG. 6C .  
         [0090]     In the first binary counting circuit  60 A, during a high level duration of the wave-shaped band switching pulse signal ( FIG. 6A ), the clock pulses (220 kHz), which are output from the one-half frequency divider  60 D, pass through the AND-gate  64 A, and are input to the binary counter  66 A. The binary counter  66 A successively counts the clock pulses ( 220  kHz) passing through the AND-gate  64 A, and a number of the counted clock pulses is output as 4-bit data from the binary counter  66 A to the latch circuit  68 A.  
         [0091]     Note, while the first binary counting circuit  60 A is subjected to a high level duration of the wave-shaped band switching pulse signal ( FIG. 6A ), the second binary counting circuit  60 B is subjected to a low level duration of the inverted band switching pulse signal ( FIG. 6B ), so that the clock pulses (220 kHz), which are output from the one-half frequency divider  60 D, cannot pass through the AND-gate  64 B.  
         [0092]     The reset circuit  70 A is constituted so as to output a reset signal at an end of the high level duration of the wave-shaped band switching pulse signal, i.e. at a falling edge of the pulse of the wave-shaped band switching pulse signal, as shown in a timing diagram of  FIG. 6D .  
         [0093]     The reset signal ( FIG. 6D ) is output from the reset circuit  70 A to the binary counter  66 A through the buffer  72 A, to thereby reset the binary counter  66 A. Also, the reset signal ( FIG. 6D ) is output as a latch timing signal to the latch circuit  68 A, so that the 4-bit data is latched in the latch circuit  68 A. Thus, the latched 4-bit data representing the high level duration of the wave-shaped band switching pulse signal is output to the second logic matrix circuit  62 A of the frequency determination circuit  62 .  
         [0094]     In short, in the first binary counting circuit  60 A, the counting of the clock pulses (220 kHz) is started at a beginning of a high level duration of the wave-shaped band switching pulse signal, i.e. at a rising edge of a pulse of the wave-shaped band switching pulse signal, and is stopped at an end of the high level duration of the wave-shaped band switching pulse signal, i.e. at a falling edge of the high level duration of the wave-shaped band switching pulse signal.  
         [0095]     After the latch timing signal is output from the reset circuit  70 A, the second binary counting circuit  60 B is subjected to the high level duration of the inverted band switching pulse signal ( FIG. 6B ). Thus, the clock pulses (220 kHz), which are output from the one-half frequency divider  60 D, pass through the AND-gate  64 B, and are input to the binary counter  66 B. The binary counter  66 B successively counts the clock pulses (220 kHz) passing through the AND-gate  64 B, and a number of the counted clock pulses is output as 4-bit data from the binary counter  66 B to the latch circuit  68 B.  
         [0096]     Similar to the reset circuit  70 A, the reset circuit  70 B is constituted so as to output a reset signal at an end of the high level duration of the inverted band switching pulse signal, i.e. at a falling edge of the pulse of the wave-shaped band switching pulse signal, as shown in a timing diagram of  FIG. 6E .  
         [0097]     The reset signal ( FIG. 6E ) is output from the reset circuit  70 B to the binary counter  66 B through the buffer  72 B, to thereby reset the binary counter  66 B. Also, the reset signal ( FIG. 6E ) is output as a latch timing signal to the latch circuit  68 B, so that the 4-bit data is latched in the latch circuit  68 B. Thus, the latched 4-bit data, which represents the high level duration of the inverted band switching pulse signal ( FIG. 6B ), i.e. the low level duration of the wave-shaped band switching pulse signal ( FIG. 6A ), is output to the second logic matrix circuit  62 B of the frequency determination circuit  62 .  
         [0098]     In short, in the second binary counting circuit  60 B, the counting of the clock pulses (220 kHz) is started at a beginning of a high level duration of the inverted band switching pulse signal, i.e. at a rising edge of a pulse of the inverted band switching pulse signal, and is stopped at an end of the high level duration of the inverted band switching pulse signal, i.e. at a falling edge of the high level duration of the inverted band switching pulse signal.  
         [0099]     Since the clock pulses (220 kHz), which are output from the one-half frequency divider  60 D, have a frequency which is approximately ten times that of the wave-shaped band switching pulse signal ( FIG. 6A ) having the frequency of 22±4 kHz, the number of clock pulses (220 kHz), which is counted by the binary counter  66 A during the high and low level duration of the wave-shaped band switching pulse signal, may be 10±2. Similarly, the number of clock pulses (220 kHz), which is counted by the binary counter  66 B during the low and low level duration of the wave-shaped band switching pulse signal, may be 10±2. In short, when the band switching pulse signal (22±4 kHz) is superimposed on the power supply voltage signal (13 volts or 18 volts), the 4-bit data, which are output from each of the latch circuits  68 A and  68 B, may have any one of five 4-bit data [1000], [1001], [1010], [1011] and [1100].  
         [0100]     In the frequency determination circuit  62 , each of the first and second logic matrix circuits  62 A and  62 B is constituted such that each of the 4-bit data [1000], [1001], [1010], [1011] and [1100] is converted into 4-bit data [1111].  
         [0101]     In particular, for example, when the 4-bit data [1000] is input from the latch circuit  68 A to the first logic matrix circuit  62 A, the 4-bit data [1000] is converted into 4-bit data [1111] due to the existence of the inverters  74 A 2 ,  74 A 3  and  74 A 4 , and then the 4-bit data [1111] is input to the AND-gate  76 A 1 , so that a high level signal is output from the AND-gate  76 A 1  to the OR-gate  78 A.  
         [0102]     Also, for example, when the 4-bit data [1010] is input from the latch circuit  68 A to the first logic matrix circuit  62 A, the 4-bit data [1010] is converted into 4-bit data [1111] due to the existence of the inverters  74 A 2  and  74 A 4 , and then the 4-bit data [1111] is input to the AND-gate  76 A 3 , so that a high level signal is output from the AND-gate  76 A 3  to the OR-gate  78 A.  
         [0103]     Similarly, for example, when the 4-bit data [1001] is input from the latch circuit  68 B to the second logic matrix circuit  62 B, the 4-bit data [1001] is converted into 4-bit data [1111] due to the existence of the inverters  74 B 2  and  74 B 3 , and then the 4-bit data [1111] is input to the AND-gate  76 B 2 , so that a high level signal is output from the AND-gate  76 B 2  to the OR-gate  78 B.  
         [0104]     Further, for example, when the 4-bit data [1100] is input from the latch circuit  68 B to the second logic matrix circuit  62 B, the 4-bit data [1100] is converted into 4-bit data [1111] due to the existence of the inverters  74 B 3  and  74 B 4 , and then the 4-bit data [1111] is input to the AND-gate  76 B 5 , so that a high level signal is output from the AND-gate  76 B 5  to the OR-gate  78 B.  
         [0105]     Thus, when the band switching pulse signal (22±4 kHz) is superimposed on the power supply voltage signal (13 volts or 18 volts), a high level signal is output from any one of the AND-gates  76 A 1 ,  76 A 2 ,  76 A 3 ,  76 A 4  and  76 A 5  to the OR-gate  78 A, so that a high level signal is output from the OR-gate  78 A to the AND-gate  62 C, as shown in a timing diagram of  FIG. 6F .  
         [0106]     Similarly, when the band switching pulse signal (22±4 kHz) is superimposed on the power supply voltage signal (13 volts or 18 volts), a high level signal is output from any one of the AND-gates  76 B 1 ,  76 B 2 ,  76 B 3 ,  76 B 4  and  76 B 5  to the OR-gate  78 B, so that a high level signal is output from the OR-gate  78 B to the AND-gate  62 C, as shown in a timing diagram of  FIG. 6G .  
         [0107]     Accordingly, when the respective high level signals are input from the OR-gates  78 A and  78 B to the AND-gate  62 C, a high level signal is output from the AND-gate  62 C to the selector circuit  38 , as shown in a timing diagram of  FIG. 6H .  
         [0108]     Therefore, similar to the above-mentioned prior art BS converter shown in  FIG. 1 , when the television set, connected to the BS tuner  14 , is tuned to a channel to receive a BS signal included in the high frequency band of 11.7 GHz to 12.75 GHz, i.e. when the band switching pulse signal is superimposed on the power supply voltage signal (13 volts or 18 volts) in the BS tuner  14 , the first drive control signal, which is output from the selector circuit  38  to the first local frequency oscillator  32 L, is changed from the high level to the low level so that the driving of the first local frequency oscillator  32 L is stopped. On the other hand, the second drive control signal, which is output from the selector circuit  38  to the second local frequency oscillator  32 H, is changed from the low level to a high level so that the second local frequency oscillator  32 H is driven.  
         [0109]     In short, while the band switching pulse signal (22±4 kHz) is superimposed on the power supply voltage signal (13 volts or 18 volts), only the second local frequency oscillator  32 H is driven so that the BS signals, included in the high frequency band of 11.7 GHz to 12.75 GHz, are converted into the intermediate frequency signals BS-IF.  
         [0110]     While the band switching pulse signal is not superimposed on the power supply voltage signal (13 volts or 18 volts) in the BS tuner  14 , i.e. while the television set is tuned to a channel to receive a BS signal included in the low frequency band of 10.7 GHz to 11.7, a low frequency spike noise having a lower frequency than that (22±4 kHz) of the band switching pulse signal may be superimposed on the power supply voltage signal.  
         [0111]     In this case, the 4-bit data, which is output from at least one of the latch circuits  68 A and  68 B, has a larger value than the 4-bit data [1100], and thus the high level signal cannot be output from the AND-gate  62 C to the selector circuit  38 . Namely, although the low frequency spike noise having the lower frequency than that (22±4 kHz) of the band switching pulse signal is superimposed on the power supply voltage signal (13 volts or 18 volts), the detector circuit  52  does not recognize the low frequency spike noise as the band switching signal.  
         [0112]     Also, while the band switching pulse signal is not superimposed on the power supply voltage signal (13 volts or 18 volts) in the BS tuner  14 , i.e. while the television set is tuned to a channel to receive a BS signal included in the low frequency band of 10.7 GHz to 11.7, a high frequency spike noise having a higher frequency than that (22±4 kHz) of the band switching pulse signal may be superimposed on the power supply voltage signal.  
         [0113]     In this case, the 4-bit data, which is output from at least one of the latch circuits  68 A and  68 B, has a smaller value than the 4-bit data [1000], and thus the high level signal cannot be output from the AND-gate  62 C to the selector circuit  38 . Namely, although the high frequency spike noise having the higher frequency than that (22±4 kHz) of the band switching pulse signal is superimposed on the power supply voltage signal (13 volts or 18 volts), the detector circuit  52  does not recognize the high frequency spike noise as the band switching signal.  
         [0114]     In this first embodiment, the detector circuit  52  may have a frequency/amplitude characteristic as shown in a graph of  FIG. 7A . As shown in this graph, the frequency/amplitude characteristic features a rectangular profile, the sides of which are defined by the frequencies of 18 kHz and 26 kHz, and thus the detector circuit  52  is not susceptible to various noises, resulting in a satisfactorily reliable operation of the BS converter according to the present invention.  
         [0115]     Also, according to the present invention, whenever the band switching pulse signal (22±4 kHz) is superimposed on the power supply voltage signal (13 volts or 18 volts), it is possible to securely detect the superimposition of the band switching pulse signal on the power supply voltage signal, and thus a sensitivity of the detector circuit  52  for detecting the band switching pulse signal is superior to the case of the above-mentioned prior art BS converter.  
         [0116]     Also, according to the present invention, as shown in a graph of  FIG. 7B , the detector circuit  52  may have a band switching time characteristic with respect to a level of the wave-shaped band switching pulse signal (BSPS) output from the level detector circuit  58 . As already stated, the band switching time is defined as a period of time measured from a time at which the television set is tuned to a channel to receive a BS signal included in the high frequency band to a time at which a picture is displayed on a screen of the television set based on the tuned channel. As is apparent from the graph of  FIG. 7B , the band switching time may be substantially zero, because the frequency (22±4 kHz) of the band switching pulse signal, superimposed on the power supply voltage signal, is directly detected by the detector circuit  52  without utilizing the level of the wave-shaped band switching pulse signal. Thus, according to the present invention, as soon as the television set is tuned to a channel to receive a BS signal included in the high frequency band, it is possible to display a picture on a screen of the television set based on the tuned channel.  
       Second Embodiment  
       [0117]     Next, with reference to  FIG. 8 , a second embodiment of the broadcasting satellite (BS) converter according to the present invention is explained below.  
         [0118]     In the second embodiment, another frequency determination circuit  80  is substituted for the frequency determination circuit  62  shown in  FIG. 5 .  
         [0119]     As shown in  FIG. 8 , the frequency determination circuit  80  includes a first window-type digital comparator circuit  82 A, a second window-type digital comparator circuit  82 B, and an AND-gate  84 .  
         [0120]     The first window-type digital comparator circuit  82 A includes a pair of digital comparators  86 A and  88 A, a pair of registers  90 A and  92 A, and an AND-gate  94 A, and these elements are arranged as shown in  FIG. 8 . Similarly, the second window-type digital comparator circuit  82 B includes a pair of digital comparators  86 B and  88 B, a pair of registers  90 B and  92 B, and an AND-gate  94 B, and these elements are arranged as shown in  FIG. 8 . Note, the first and second window type digital comparator circuits  82 A and  82 B are identical to each other.  
         [0121]     In the first window-type digital comparator circuit  82 A, the digital comparators  86 A and  88 A are connected to the latch circuit  68 A of the first binary counting circuit  60 A so as to receive 4-bit data output from the latch circuit  68 A. Also, a high 4-bit threshold data [1101] is set in the resistor  90 A, and a low 4-bit threshold data [1000] is set in the resistor  92 A. Note, in this second embodiment, the BS converter ( 10 ) includes a system controller (not shown), by which the respective settings of the 4-bit data [1101] and [1000] in the resistors  90 A and  92 A are carried out.  
         [0122]     When 4-bit data is input from the latch circuit  68 A to both the digital comparators  86 A and  88 A, it is compared with the high 4-bit threshold data [1101] and low 4-bit threshold data [1000] by the respective digital comparators  86 A and  88 A.  
         [0123]     In particular, when the 4-bit data output from the latch circuit  68 A is equal to or larger than the high 4-bit threshold data [1101] set in the resistor  90 A, the digital comparator  86 A outputs a low level signal to the AND-gate  94 A. When the 4-bit data is smaller than the high 4-bit threshold data [1101], the digital comparator  86 A outputs a high level signal to the AND-gate  94 A. On the other hand, when the 4-bit data output from the latch circuit  68 A is equal to or larger than the low 4-bit threshold data [1000] set in the resistor  92 A, the digital comparator  88 A outputs a high level signal to the AND-gate  94 A. When the 4-bit data is smaller than the low 4-bit threshold data [1000], the digital comparator  86 A outputs a low level signal to the AND-gate  94 A.  
         [0124]     In short, only when the 4-bit data output from the latch circuit  68 A falls within the range from the 4-bit data [1000] to [1100], i.e. only when the 4-bit data represents a high level duration of the wave-shaped band switching pulse signal (22±4 kHz), do the respective digital comparators  86 A and  88 A output the high level signals to the AND-gate  94 A, and then this AND-gate  94 A outputs a high level signal to the AND-gate  84 .  
         [0125]     In the second window-type digital comparator circuit  82 B, the digital comparators  86 B and  88 B are connected to the latch circuit  68 B of the second binary counting circuit  60 B so as to receive 4-bit data output from the latch circuit  68 B. Also, a high 4-bit threshold data [1101] is set in the resistor  90 B, and a low 4-bit threshold data [1000] is set in the resistor  92 B. Note, the respective settings of the 4-bit data [1101] and [1000] in the resistors  90 B and  92 B are carried out by the aforesaid system controller (not shown).  
         [0126]     When 4-bit data is input from the latch circuit  68 B to both the digital comparators  86 B and  88 B, it is compared with the high 4-bit threshold data [1101] and low 4-bit threshold data [1000] by the respective digital comparators  86 B and  88 B.  
         [0127]     In particular, when the 4-bit data output from the latch circuit  68 B is equal to or larger than the high 4-bit threshold data [1101] set in the resistor  90 B, the digital comparator  86 B outputs a low level signal to the AND-gate  94 B. When the 4-bit data is smaller than the high 4-bit threshold data [1101], the digital comparator  86 B outputs a high level signal to the AND-gate  94 B. On the other hand, when the 4-bit data output from the latch circuit  68 B is equal to or larger than the low 4-bit threshold data [1000] set in the resistor  92 B, the digital comparator  88 B outputs a high level signal to the AND-gate  94 B. When the 4-bit data is smaller than the low 4-bit threshold data [1000], the digital comparator  86 B outputs a low level signal to the AND-gate  94 B.  
         [0128]     In short, only when the 4-bit data output from the latch circuit  68 B falls within the range from the 4-bit data [1000] to [1100], i.e. only when the 4-bit data represents a low level duration of the wave-shaped band switching pulse signal (22±4 kHz), do the respective digital comparators  86 B and  88 B output the high level signals to the AND-gate  94 B, and then this AND-gate  94 B outputs a high level signal to the AND-gate  84 .  
         [0129]     When the respective AND-gate  94 A and  94 B output the high level signals to the AND-gate  84 , i.e. when it is confirmed that the band switching pulse signal (22±4 kHz) is superimposed on the power supply voltage signal (13 volts or 18 volts), the AND-gate  84  outputs a high voltage signal to the selector circuit  38 . Thus, similar to the above-mentioned first embodiment, it is possible to properly control the operations of the first and second local frequency oscillators  32 L and  32 H.  
         [0130]     In the above-mentioned embodiments of the present invention, although the band switching pulse signal (22±4 kHz) is superimposed on the power supply voltage signal ( 13  volts or 18 volts), no influence can be exerted on the intermediate frequency signals BS-IF by the superimposed band switching pulse signal, because the frequency of the band switching pulse signal is sufficiently lower than that (950 to 2150 MHz) of the intermediate frequency signal BS-IF.  
         [0131]     Finally, it will be understood by those skilled in the art that the foregoing description is of a preferred embodiment of the device, and that various changes and modifications may be made to the present invention without departing from the spirit and scope thereof.