Abstract:
This invention provides a signal synchronizer that is capable of minimizing the effects of multi-path reception. The signal synchronizer provides signal samples from a first signal source and a second signal source for generating an output signal. The signal synchronizer includes a memory for storing signal samples obtained from a first signal source and for storing signal samples obtained from a second signal source. Circuitry in the synchronizer determines a signal transit time difference between the first signal source and the second signal source. A readout controller then determines a memory offset from the signal transit time difference. The memory offset specifies a location in the memory from which to begin reading the signal samples obtained from the second signal source.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to European patent application 04004065.1 filed on Feb. 23, 2004, which is incorporated into this application in its entirety. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to the field of communications and signal processing. In particular, the invention relates to a technique for eliminating artifacts in an output signal produced, for example, by systems employing multipath reception techniques. 
     2. Related Art 
     Multipath reception relates to obtaining and processing radio signals from one of multiple transmission paths or channels. Generally, the term multipath reception is applied to systems that incorporate multiple antennas (for spatial or antenna diversity) and systems that receive signals on multiple frequency channels (for frequency diversity). 
     In motor vehicles the radio system may employ antenna diversity in the form of multiple spatially separated antennas. For example, one antenna may be built into a window, while another antenna may rise from an exterior surface of the motor vehicle. When the antenna diversity radio system operates, a receiver system selects one of the antennas as the source of radio signals for processing based on predefined criteria. For example, the criteria may be received signal strength, interference or noise level, signal to noise ratio, or other signal quality criteria. In other words, the receiver system generally selects the best signal available for processing. 
     Frequency diversity systems also attempt to receive and process the highest quality signal. However, these systems generally include multiple radio receivers; one radio receiver functions as the operating receiver, and another receiver functions as a search and check receiver. The operating receiver stays tuned to the frequency of interest to receive and process the received radio signal. On the other hand, the search and check receiver searches for alternate reception frequencies that offer higher signal quality. 
     If the check receiver finds an alternate reception frequency, the operating receiver tunes to the alternate reception frequency and begins processing the received signal. Alternatively, the check receiver and the operating receiver may switch roles. In other words, the check receiver remains tuned to the alternate reception frequency and assumes the role of the operating receiver. The prior operating receiver then assumes the role of the check receiver and begins searching for alternative reception frequencies offering higher signal quality. In automobile radios, the operating receiver is sometimes referred to as the “audio receiver,” while the check receiver is sometimes referred to as the “background receiver.” 
     In the past, a change to a new radio signal source often introduced noticeable artifacts into the output signal produced by the radio system. One source of artifacts was the significant variation in propagation delay experienced by radio signals in reaching the radio system, either at different antennas, or at a different frequency. Due to the variation in propagation delay, there was no expectation that the new signal source would be aligned in time with the previously received and processed signal source. Thus, the switch to a new antenna or a new frequency resulted in artifacts caused by repetition or omission of information. When the output signal was a music program, for example, the artifacts detracted from the perceived quality of the program. Therefore, there is a need for additional improvements in the systems used for multipath reception that do not suffer from the shortcomings set forth above. 
     SUMMARY 
     This invention provides a signal synchronizer that minimizes the effects of multi-path reception. The signal synchronizer provides signal samples for generating an output signal (e.g., a music program). The signal synchronizer includes a memory for storing signal samples obtained from a first signal source and for storing signal samples obtained from a second signal source. Circuitry in the synchronizer determines a signal transit time difference between the first signal source and the second signal source. A readout controller then determines a memory offset from the signal transit time difference. The memory offset specifies a location in the memory from which to begin reading the signal samples obtained from the second signal source and thereby eliminates at least a portion of signal transit time effects on the output signal. 
     Other systems, methods, features and advantages of the invention will be or will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
       The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. In the figures, like reference numerals designate corresponding parts throughout the different views. 
         FIG. 1  is a block diagram illustrates a multi-path signal front-end that helps to minimizes artifacts caused in an output signal by unequal signal transit times. 
         FIG. 2  is a block diagram illustrating various memory location in the signal front-end shown in  FIG. 1  that store signal samples obtained from a first signal source and a second signal source. 
         FIG. 3  is a block diagram illustrating memory location in the signal front-end shown in  FIG. 1  that store signal samples obtained from a first signal source and a second signal source. 
         FIG. 4  is a flow chart illustrating a method for minimizing artifacts in an output signal. 
     
    
    
     DETAILED DESCRIPTION 
     In  FIG. 1 , a multi-path signal front-end  100  is coupled to a first antenna  102  and a second antenna  104  through the first and second antenna inputs  106 ,  108 . The front-end  100  includes a receiver section  110 , a memory section  112 , and support circuitry  114 . A controller  132  coordinates the operation of the front-end  100 . The receiver section  110  includes the first receiver  116  and the second receiver  118 , while the memory section  112  includes the first shift register memory  120  and the second shift register memory  122 . The support circuitry  114  includes the comparison circuitry  124 , the estimator circuitry  126  and the switch  128  and the pause detector  130 . The output connection  134  provides selected signal samples to additional processing blocks (not shown) in order to produce an output signal (e.g., a music program). 
     The controller  132  connects to the general-purpose memory  136  that may store a reception program  138 . The reception program  138  coordinates the operation of the front-end  100  and works with the controller  132  to help minimize artifacts caused in an output signal by unequal signal transit times. The reception program  138  may also include instructions that will lead the controller  132  to employ the circuitry set forth above to determine a signal transit time difference between two signal sources and to output signal samples to compensate for that signal transit time difference when switching signal sources. 
     The receivers generally include mixers, demodulators and digitizers that produce signal samples from signal sources received on the antennas  102  and  104 . The signal samples obtained from the first receiver  116  are shifted through the first shift register memory  120 , while the signal samples obtained from the second receiver  118  are shifted through the second shift register memory  122 . 
     However, two physically separate receivers are not necessarily needed. Rather, a single receiver that demodulates multiple channels in bulk may be used to obtain signal samples from multiple signal sources. Similarly, the memory section need not employ shift registers, but may instead use general purpose DRAM or other well known memory types and their derivatives interoperating with the controller  132 . 
     More generally, one skilled in the art will appreciate that all or part of the memory system may be stored on or read from other tangible media. For example, secondary storage devices such as hard disks, floppy disks, and CD-ROMS; or other forms of ROM or RAM either currently known or later developed derivatives. Although specific components of the front-end  100  are described, one skilled in the art will appreciate that a front-end suitable for use wit methods, systems, and articles of manufacture consistent with the invention may contain additional or different components. For example, the controller  132  may be a microprocessor, microcontroller, application specific integrated circuit (“ASIC”), discrete or a combination of other types of circuits acting as a central processing unit. In addition, the memories may be RAM, DRAM, SDRAM, or any other type of read/writeable memory. 
     In one embodiment, one receiver may be the operating receiver, while the other receiver may be a search receiver. The operating receiver may act as the receiver that tunes to the program of interest and generates signal samples for that program. The search receiver may act as the receiver that scans alternate reception frequencies for the program of interest and that provides representative signal samples for signal quality metric analysis. If the alternate reception frequency provides better signal quality, then the operating receiver changes to the alternate reception frequency for continued reception of the program, while the search receiver continues to scan alternate reception frequencies. Signal samples from the search receiver are used, as described in more detail below, to generate the output signal until the operating receiver has completed its frequency change. 
     In another embodiment, the receivers may switch roles between the search receiver and the operating receiver. Thus, when an alternate reception frequency with better signal quality is located, the search receiver that found the alternate reception frequency stays tuned to that frequency and becomes the operating receiver. The prior operating receiver then becomes the search receiver. 
       FIG. 1  also illustrates that the signal samples present on the output connection  134  depend on the operation of the support circuitry  114 . In particular, the switch  128  allows signal samples to be taken from either the first signal source or the second signal source onto the output connection  134 . In general, the output connection  134  carries signal samples from the signal source that is experiencing the best signal quality. However, when an alternate reception frequency is found that offers better signal quality, the controller changes the switch  128  so that signal samples from the alternate signal source are placed on the output connection  134 . 
     Although the switch  128  is illustrated as a separate element, it may be implemented in many ways. For example, the switch may be a mulitplexer, or the output of a general-purpose data bus on which the controller  132  places the appropriate signal samples for generation of the output signal. 
     In doing so, the controller  132  may use the comparison circuitry  124  and estimator circuitry  126  to determine a signal transit time differential (e.g., in terms of a number of signal samples or in terms of units of time) based on the signal samples obtained from the first and second signal sources. For example, the comparison circuitry  124  may be a cross-correlator that correlates the contents of the shift registers  120  and  122 . The estimator circuitry  126  may be comparison circuitry that identifies at what shift value the correlation peak exists. Thus, as the comparison circuitry  124  outputs correlation values, the estimator circuitry  126  may search for the correlation peak in the correlation values. The shift value that produces the correlation peak approximately gives the signal transit time. As also shown in  FIG. 2 , the shift registers  120 ,  122 , support circuitry  114 , and controller  132  may act as a signal synchronizer. 
       FIG. 2  is a block diagram illustrating a diagram  200  of the shift registers  120  and  122 . As shown, the shift registers have 23 storage locations, but more or less storage locations may be provided. The numbers in each storage location indicate sequentially stored signal samples of a program of interest obtained by the first receiver  116 , in the case of the first shift register  120 , and by the second receiver  118 , in the case of the second shift register  122 . The operating point for the first shift register  120  may be the memory element  202 , while the operating point for the second shift register  122  may be the memory element  204 . Note that because of unequal signal transit times between the first signal source and the second signal source, the signal samples are not obtained and stored in corresponding locations in each shift register  120 ,  122 . 
     Signal samples are read out of the shift registers  120  and  122  at the preset operating point in each shift register. As signal samples shift through the shift registers, different signal samples appear at the operating point, and different signal samples are thereby transferred to the output connection  134 . The controller  132  may set the operating point by asserting control signals to the shift registers, or by directly retrieving signal samples from memory and placing them on the output connection  134 . For example, the operating point for the first shift register, as shown in  FIG. 2 , is memory location  12 , where the ninth signal sample obtained from the first signal source may be currently stored. The operating point may be set to any memory location in each shift register. However, setting the operating point to a central memory location or stage is advantageous. In general, in a shift register of length L, the operating point may be set to (Ta*L)/2, wherein Ta is the time interval between signal samples. 
       FIG. 2  also shows an example where the second signal source leads (or arrives before) the first signal source by as many as three sample periods. Thus, additional signal samples of the second signal source are present in the second shift register  122  and the signal samples that are common to both the first shift register  120  and the second shift register  122  are advanced in position in the second shift register  122 . If the front-end  100  were to directly switch to the second signal source and read signal samples from the second shift register  122  at the same operating point (location  12 ) for the first shift register  120 , the front-end would omit signal samples  10  and  11 . The result may be the introduction of artifacts into the output signal because the next signal sample should be sample  10 , not sample  12 . Because the second signal source is arriving  3  sample periods earlier, signal sample  10  is present at memory location  10  in the second shift register  122 . 
       FIG. 3  is a block diagram illustrating a similar situation as depicted in  FIG. 2 , except that the second signal source arrives seven samples in time behind the first signal source. Thus, if the front-end  100  were to switch directly to the second signal source at operating point  12 , the output signal would repeat signal samples  3 ,  4 ,  5 ,  6 ,  7 ,  8 , and  9 . In other words, the output signal would create duplicated information artifacts in the output signal. Instead, the operating point for the second shift register is offset from the operating point  12 . More specifically, the operating point  302  for the second shift register is offset seven locations to memory location  19  in the second shift register  122 . 
     The front-end  100  helps eliminate such artifacts that would otherwise arise in the output signal. To that end, the front-end  100  determines the transit time difference between the first and second signal sources. In one embodiment, the front-end  100  uses the comparison circuitry  124  and estimator circuitry  126  to perform a cross-correlation on the signal samples. The peak in the correlation will occur when the two sets of signal samples are most closely matched. 
     In  FIG. 2 , the comparison circuitry  124  and estimator circuitry  126  will find that the maximum of the cross correlation function occurs at a shift of three sampling periods. Thus, the controller  132 , when switching to the second signal source, synchronizes to the new signal source by setting the operating point for the second shift register to memory location  10 , where the next signal sample (sample  10 ) is stored for the program of interest. As a result, the output signal does not repeat signal samples  10  and  11 , and no artifacts are created by omitting information. 
     Similarly, with regard to  FIG. 3  and a late signal, the comparison circuitry  124  and estimator circuitry  126  will find that the maximum of the cross correlation function occurs at a shift of seven sampling periods. Thus, the controller  132 , when switching to the second signal source, synchronizes to the new signal source by setting the operating point for the second shift register to memory location  19 , where the next signal sample (sample  10 ) is stored for the program of interest. As a result, the output signal does not repeat signal samples  10  and  11 , and no artifacts are created by repeating information. 
     When a shift register operating point has been initially established away from a center stage of the shift register, the controller  132  may move the operating point back toward the center to assist with correlation and further synchronizations when the source signal is again switched. In order to move the operating point, the controller  132  may insert or remove (or discard without storing) signal samples in the shift registers. For example, referring back to  FIG. 2 , and assuming that the operating point is memory location  10  in the second shift register  122 , the controller  132  may move the operating point back to memory location  12  by removing two signal samples from the second shift register  122 . The controller  132  may remove silence signal samples, for example, or discard without storing two silence signal samples, so that the operating point moves back to memory location  10 . 
     The pause detector  130  may be used to detect silence samples. For example, the pause detector  130  may incorporate comparison circuitry that compares a signal sample to a predetermined silence threshold to determine if the signal sample falls below the threshold. The pause detector  130  provides the result of the comparison to the controller  132 . 
     Similarly, assuming that the operating point is memory location  19  in the second shift register  122  as shown in  FIG. 3 , the controller  132  may move the operating point back to memory location  12  by inserting seven signal samples into the second shift register  122 . The controller  132  may insert silence signal samples, for example, detected by the pause detector  130 . 
     The controller  132  may be implemented as discrete circuitry, or as a general-purpose microcontroller executing instructions from a memory. The correlation, estimation, and pause detection functions may thus be implemented as software functions (performed by the controller  132 ), as separate hardware elements, or as circuit blocks in one or more integrated circuit packages. Furthermore, the shift registers  120 ,  122  may be replaced with other types of memories, such as a single block of DRAM, with signal sample indexing performed by the controller  132 . Also note that the signal sources may be received by one antenna (where the signal sources are separated in frequency), multiple antennas (where the signal sources are separated spatially), or by both. One, two, or more than two receivers may be provided to receive the signal samples. 
       FIG. 4  is a flow chart  400  of the steps performed by the front-end  100 . For example, the flow diagram  400  may represent the steps that the controller  132  executes, coordinates, or generates control signals for, in accordance with the reception program  138 . The shift registers  120 ,  122  store signal samples obtained from the first and second signal sources (step  402 ). The first shift register  120 , for example, then provides signal samples from the first signal source from an operating point in the first shift register  120  (step  404 ). Meanwhile, the controller  132  evaluates signal quality metrics on the signal samples to determine which signal source has, as examples, the best signal to noise ratio, the best reception level, the lowest bit error rate, or the like (step  406 ). In other words, the controller  132  uses one or more metrics to determine whether a better quality signal source is available for a given program of interest (step  406 ). 
     If so, the support circuitry performs a cross-correlation to determine a signal transit time difference between the first and second signal sources (step  408 ). Based on the signal transit time difference, the second shift register  122  provides signal samples from an operating point in the second shift register  122 . The controller  132  may then more the operating point toward a central stage in the second shift register  122 . To that end, the pause detector  130  may compare for silence samples (step  410 ), and the controller  132  may insert or remove silence samples in the second shift register  122  (step  412 ). 
     While various embodiments of the invention have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible that are within the scope of this invention.