Abstract:
A method for forming a group of structures in a semiconductor device includes forming a conductive layer on a substrate, where the conductive layer includes a conductive material, and forming an oxide layer over the conductive layer. The method further includes etching at least one opening in the oxide layer, filling the at least one opening with the conductive material, etching the conductive material to form spacers along sidewalls of the at least one opening, and removing the oxide layer and a portion of the conductive layer to form the group of structures.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to semiconductor manufacturing and, more particularly, to forming fins in FinFET devices. 
     BACKGROUND OF THE INVENTION 
     The escalating demands for high density and performance associated with ultra large scale integration semiconductor devices require design features, such as gate lengths, below 100 nanometers (nm), high reliability, and increased manufacturing throughput. The reduction of design features below 100 nm challenges the limitations of conventional methodology. 
     For example, when the gate length of conventional planar metal oxide semiconductor field effect transistors (MOSFETs) is scaled below 100 nm, problems associated with short channel effects, such as excessive leakage between the source and drain, become increasingly difficult to overcome. In addition, mobility degradation and a number of process issues also make it difficult to scale conventional MOSFETs to include increasingly smaller device features. New device structures are therefore being explored to improve FET performance and allow further device scaling. 
     Double-gate MOSFETs represent new structures that have been considered as candidates for succeeding existing planar MOSFETs. In double-gate MOSFETs, two gates may be used to control short channel effects. A FinFET is a double-gate structure that exhibits good short channel behavior. A FinFET includes a channel formed in a vertical fin. The FinFET structure may be fabricated using layout and process techniques similar to those used for conventional planar MOSFETs. 
     SUMMARY OF THE INVENTION 
     Implementations consistent with the principles of the invention form multiple fins in FinFET devices. By using spacers for forming the fins, narrow fins may be formed beyond the limits of lithography. 
     In accordance with the purpose of this invention as embodied and broadly described herein, a method for forming fins in a FinFET is provided. The method includes forming an oxide layer on a silicon on insulator (SOI) wafer, creating at least one opening in the oxide layer, forming silicon in the at least one opening, etching the silicon to form spacers, the spacers being adjacent sidewalls of the opening, and removing the oxide layer and silicon located below the oxide layer to form the fins. 
     In another implementation consistent with the present invention, a method of manufacturing a semiconductor device is provided. The method includes depositing an oxide layer over a conductive layer, where the conductive layer includes conductive material. The method further includes etching at least one opening in the oxide layer, where the at least one opening has two sidewalls, filling the at least one opening with the conductive material, forming spacers adjacent the two sidewalls of the at least one opening, removing the oxide layer and a portion of the conductive layer to form fin structures, forming a source region and a drain region, depositing a gate material over the fin structures, and patterning and etching the gate material to form at least one gate electrode. 
     In yet another implementation consistent with the principles of the invention, a method for forming a group of structures on a wafer including a conductive layer that includes conductive material is provided. The method includes forming a conductive layer on a substrate, where the conductive layer includes a conductive material, forming an oxide layer over the conductive layer, etching at least one opening in the oxide layer, filling the at least one opening with the conductive material, etching the conductive material to form spacers along sidewalls of the at least one opening, and removing the oxide layer and a portion of the conductive layer to form the group of structures. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate an embodiment of the invention and, together with the description, explain the invention. In the drawings, 
     FIG. 1 illustrates an exemplary process for forming fins in a FinFET device in an implementation consistent with the principles of the invention; and 
     FIGS. 2-8 illustrate exemplary views of a FinFET device fabricated according to the processing described in FIG.  1 . 
    
    
     DETAILED DESCRIPTION 
     The following detailed description of implementations consistent with the present invention refers to the accompanying drawings. The same reference numbers in different drawings may identify the same or similar elements. Also, the following detailed description does not limit the invention. Instead, the scope of the invention is defined by the appended claims and their equivalents. 
     Implementations consistent with the principles of the invention form multiple fins in FinFET devices. Having multiple fins enables the resulting semiconductor device to increase the channel width per device as compared to single fin FinFET designs. 
     EXEMPLARY PROCESSING 
     FIG. 1 illustrates an exemplary process for fabricating a FinFET in an implementation consistent with the principles of the invention. FIGS. 2-8 illustrate exemplary cross-sectional views of a FinFET fabricated according to the processing described in FIG.  1 . 
     With reference to FIGS. 1 and 2, processing may begin by depositing an oxide layer  230  on a thin silicon on insulator (SOI) structure (act  105 ). In one implementation consistent with the principles of the invention, oxide layer  230  may have a thickness ranging from about 500 Å to about 1000 Å. In other implementations consistent with the present invention, layer  230  may consist of other films or materials that may be deposited or grown. 
     The SOI structure includes a silicon substrate  200 , a buried oxide layer  210 , and a silicon layer  220  formed on buried oxide layer  210 . Buried oxide layer  210  and silicon layer  220  may be formed on substrate  200  in a conventional manner. In an exemplary implementation, buried oxide layer  210  may include a silicon oxide and may have a thickness ranging from about 1500 Å to about 3000 Å. Silicon layer  220  may include monocrystalline or polycrystalline silicon having a thickness ranging from about 200 Å to about 500 Å. 
     In alternative implementations consistent with the present invention, substrate  200  and silicon layer  220  may include other materials, such as germanium, or combinations of materials, such as silicon-germanium. Buried oxide layer  210  may also include other dielectric materials. 
     Once oxide layer  230  has been deposited, one or more openings  300  may be created in oxide layer  230 , as illustrated in FIG. 3 (act  110 ). Only one opening  300  is illustrated in FIG. 3 for simplicity. To create opening  300 , a material may be deposited and patterned to form a mask (not shown) over oxide layer  230 . The mask may be deposited and patterned in any conventional manner. Oxide layer  230  may then be etched to form opening  300 , with the etching terminating on silicon layer  220 , as illustrated in FIG.  3 . In an exemplary implementation, the width of opening  300  may range from about 1000 Å to about 2500 Å. It should be understood, however, that the particular width of opening  300  may vary based on the particular circuit requirements associated with the fins in the FinFET device that will be formed, and the capability of the lithographic system defining it. 
     After opening  300  has been formed, silicon  410  may be selectively grown to fill opening  300 , as illustrated in FIG. 4 (act  115 ). For example, a selective epitaxial growth (SEG) of the silicon in silicon layer  220  may be performed to fill the opening  300 . During the SEG process, some silicon may grow over the top of opening  300 , as illustrated in FIG. 4. A chemical-mechanical polish (CMP) or other similar technique may be performed, if necessary, to planarize the upper surface of the semiconductor device and to remove any silicon  410  that grew above the top surface of oxide layer  230 , as illustrated in FIG. 5 (act  120 ). 
     Next, silicon  410  may be etched (e.g., via a dry etch technique) in a conventional manner to form spacers  610  on the sidewalls of opening  300 , as illustrated in FIG. 6 (act  125 ). In one implementation, the width of each spacer  610  may range from about 200 Å to about 500 Å. However, the particular width of spacers  610  may be set based on the characteristic slope associated with the forming dry etch. As illustrated in FIG. 6, the portion of silicon layer  220  below the remaining portions of oxide layer  230  are denoted as field silicon  620 . 
     After the formation of spacers  610 , two fins  710  and  720  may be formed by removing the remaining oxide layer  230  and field silicon  620 , as illustrated in FIG. 7 (act  130 ). The remaining oxide layer  230  may be removed, for example, by etching or some other conventional technique. Field silicon  620  may be removed via, for example, a highly anisotropic dry etch or some other well known technique. As illustrated in FIG. 7, the two fins  710  and  720  are formed parallel to each other. The distance between fins  710  and  720  may vary based on the particular circuit requirements associated with the fins and FinFET device that will be formed. In one implementation, a portion of the top of fins  710  and  720  may be lost when field silicon  620  is removed. The height of fins  710  and  720  may be roughly about 700 Å to 1500 Å. 
     After fins  710  and  720  are formed, conventional fabrication processing can be performed to complete the transistor. For example, a gate dielectric may be formed on the side surfaces of fins  710  and  720 , followed by the formation of a protective dielectric layer, such as a silicon nitride or silicon oxide, on the top surface of fins  710  and  720 . Source/drain regions may then be formed at the respective ends of the fins  710  and  720 , followed by formation of one or more gates. For example, a silicon layer, germanium layer, combinations of silicon and germanium or various metals may be used as the gate material. The gate material may then be patterned and etched to form the gate electrodes. For example, FIG. 8 illustrates a top view of a semiconductor device consistent with the principles of the invention after the source/drain regions and gate electrodes arc formed. As illustrated, the semiconductor device may include a double gate structure with fins  710  and  720 , source drain regions  810  and  820 , and gate electrodes  830  and  840 . 
     The source/drain regions  810  and  820  may then be doped with impurities, such as n-type or p-type impurities, based on the particular end device requirements. In addition, sidewall spacers may optionally be formed prior to the source/drain ion implantation to control the location of the source/drain junctions based on the particular circuit requirements. Activation annealing may then be performed to activate the source/drain regions  810  and  820 . 
     While the above-described processing focused on the formation of two fins, implementations consistent with the present invention are not so limited. In fact, methodology consistent with the principles of the invention may be used to form any number of fins, based on the particular circuit requirements. For example, if more than two fins are to be formed, multiple openings  300  may be formed in oxide layer  230  (FIG.  3 ). The processing for forming the fins may then proceed as described above with respect to acts  115  to  130 . 
     Thus, in accordance with the present invention, a FinFET device may be formed with multiple fins. Having multiple fins enables the resulting semiconductor device to increase the channel width per device as compared to single fin FinFET designs. 
     CONCLUSION 
     Implementations consistent with the principles of the invention form multiple fins in FinFET devices. Moreover, narrow fins may be formed without requiring lithography limiting processes. 
     The foregoing description of exemplary embodiments of the present invention provides illustration and description, but is not intended to be exhaustive or to limit the invention to the precise form disclosed. Modifications and variations are possible in light of the above teachings or may be acquired from practice of the invention. For example, in the above descriptions, numerous specific details are set forth, such as specific materials, structures, chemicals, processes, etc., in order to provide a thorough understanding of the present invention. However, the present invention can be practiced without resorting to the details specifically set forth herein. In other instances, well known processing structures have not been described in detail, in order not to unnecessarily obscure the thrust of the present invention. In practicing the present invention, conventional deposition and etching techniques may be employed, and hence, the details of such techniques have not been set forth herein in detail. 
     While a series of acts has been described with regard to FIG. 1, the order of the acts may be varied in other implementations consistent with the present invention. Moreover, non-dependent acts may be implemented in parallel. 
     No element, act, or instruction used in the description of the present application should be construed as critical or essential to the invention unless explicitly described as such. Also, as used herein, the article “a” is intended to include one or more items. Where only one item is intended, the term “one” or similar language is used. 
     The scope of the invention is defined by the claims and their equivalents.