Abstract:
A process for measuring depth of a source and drain of a MOS transistor. The MOS transistor is formed on a semiconductor substrate on which a trench capacitor is formed and a buried strap is formed between the MOS transistor and the trench capacitor. The process includes the following steps. First, resistances of the buried strap at a plurality of different depths are measured. Next, a curve correlating the resistances with the depths is established. Next, slopes of the resistance to the depth for the curve are obtained. Finally, a depth corresponding to a minimum resistance before the slope of the resistance to the depth reaches to zero is obtained.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a process for measuring the depth of a source and drain, and more particularly to a process for measuring the depth of a source and drain in a DRAM by measuring resistances of the buried strap between the trench capacitor and transistor at different depths.  
           [0003]    2. Description of the Prior Art  
           [0004]    Presently, dynamic random access memory (DRAM) is widely used. Generally, a DRAM cell includes a transistor and a capacitor. FIG. 1 shows a circuit diagram of a DRAM cell, in which a drain of an NMOS transistor  10  is connected to a storage electrode of a capacitor  20 , a gate of the NMOS transistor is connected to a word line (WL), and a source is connected to a bit line (BL). In addition, an opposed electrode of the capacitor is connected to a constant voltage source. A dielectric layer is located between the storage electrode and opposed electrode. The NMOS transistor acts as a switch to control the charged or discharged state of the capacitor, thus generating the logic level of memory cell.  
           [0005]    In the DRAM manufacturing process, a two-dimensional capacitor called a planar-type capacitor is mainly used for a conventional DRAM having a storage capacity less than 1M (mega=million) bits. In the case of a DRAM having a memory cell using a planar type capacitor, electric charges are stored on the main surface of a semiconductor substrate, and thus the main surface is required to have a large area. This type of a memory cell is therefore not suited to a DRAM having a high degree of integration.  
           [0006]    For a highly integrated DRAM, such as a DRAM with more than 4M bits of memory, a three-dimensional capacitor, such as a stacked-type or a trench-type capacitor, has been introduced. With stacked-type or trench-type capacitors, it has been made possible to obtain a larger memory within a similar volume. In the trench capacitor manufacturing process, insulator (such as silicon oxide/silicon oxynitride or silicon oxide/silicon oxynitride/silicon oxide) and conductor (such as heavily N-doped polysilicon) are formed by many times of deposition and etching to complete the structure. Generally, first, a photoresist mask is formed on a semiconducting substrate. The photoresist layer and semiconducting substrate are then etched to form a trench. Next, a storage electrode layer and a dielectric layer are successively formed in the trench. Finally, conducting material is filled in the trench to complete the trench capacitor.  
           [0007]    In L. Nesbit, et al., “A 0.6 μm 256 Mb Trench DRAM Cell With Self-aligned Buried Strap (BEST)”, 1993 IEDM, pp. 627-630, 1993, it is described a process for fabricating a trench capacitor in a DRAM cell. Detailed descriptions on the process for fabricating the trench capacitor can be referred to FIGS. 2 a  to  2   f.    
           [0008]    Referring to FIG. 2 a , first, an epitaxial layer  210  is formed on a P-type semiconducting substrate  200 , and a first pad layer  220  and a second pad layer  221  are successively formed on the epitaxial layer  210 . For example, the first pad layer  220  is silicon oxide, and the second pad layer  221  is silicon nitride.  
           [0009]    Subsequently, a hard mask (not shown) with an opening is formed on the second pad layer  221 . For example, the hard mask is BSG (boron-silicate glass), nitride, or a combination thereof. The combination of BSG and nitride improves the trench quality and easily controls the conditions such as depth.  
           [0010]    Subsequently, the second pad layer  221 , the first pad layer  220 , the epitaxial layer  210 , and the semiconducting substrate  200  are successively etched using the hard mask as a mask, forming a first trench  230  down into the P-type semiconducting substrate  200 .  
           [0011]    Subsequently, referring to FIG. 2 b , arsenic ions are diffused into the inner walls of the trench  230  by ion implantation to form a strorage electrode layer  240 , which will serve as an electrode plate of a trench capacitor.  
           [0012]    Subsequently, silicon oxide/silicon nitride (ON) is conformally formed on the second pad layer  221  and the trench  230  by chemical vapor deposition (CVD) to form a dielectric layer  250  and a second trench  231 .  
           [0013]    Subsequently, referring to FIGS. 2 b  and  2   c  together, polysilicon heavily doped with arsenic (not shown) is deposited on the dielectric layer  250  to fill in the trench  231 . Next, the heavily doped polysilicon is planarized to expose the surface of the dielectric layer  250 . The residual heavily doped polysilicon is etched to form a first conducting layer  260 .  
           [0014]    Subsequently, the exposed dielectric layer  250  is etched using the second pad layer  221  as a mask to form a dielectric layer  250   a , which serves as the dielectric material between two electrode plates of the trench capacitor. A third trench  232  is formed simultaneously.  
           [0015]    Subsequently, referring to FIG. 2 d , a collar insulating layer  270  is formed on the sidewalls of the third trench  232 . A second conducting layer  261  is formed to fill in the third trench  232 . The collar insulating layer  270  can be silicon oxide, which serves as insulation and prevents current leakage. The second conducting layer  261  can be polysilicon heavily doped with arsenic and formed by deposition.  
           [0016]    Subsequently, referring to FIG. 2 e , the collar insulating layer  270  and the second conducting layer  261  are selectively etched to form a collar insulating layer  270   a  and a second conducting layer  261   a  in the third trench  232 . A fourth trench  233  is formed simultaneously.  
           [0017]    Finally, referring to FIG. 2 f , polysilicon heavily doped with arsenic (not shown) is deposited on the second pad layer  221  to fill in the fourth trench  233 , which is then planarized to expose the second pad layer  221  to form a third conducting layer  262 . The first, second, and third conducting layers  260 ,  261   a , and  262 , the dielectric layer  250   a , the collar insulating layer  270   a , and the storage electrode layer  240  constitute together a trench capacitor.  
           [0018]    In the DRAM manufacturing process, if the depth of source and drain does not reach the desired depth, the breakdown voltage of DRAM cell is decreased. Consequently, when the voltage applied to the gate has not reach the predetermined voltage, the DRAM cell is undesirably switched on. However, there is no effective way to measure the depth of source and drain until now.  
         SUMMARY OF THE INVENTION  
         [0019]    The object of the present invention is to provide a process for measuring the depth of a source and drain of a MOS transistor in a simple and quick way.  
           [0020]    According to a first aspect of the present invention, the MOS transistor is formed on a semiconducting substrate on which a trench capacitor is formed, a buried strap is formed between the MOS transistor and the trench capacitor. The process for measuring the depth of a source and drain of the MOS transistor includes the following steps. First, resistances of the buried strap at a plurality of different depths are measured. Next, a curve correlating the resistances with the depths is established. Next, slopes of the resistance to the depth for the curve are obtained. Finally, a depth corresponding to a minimum resistance before the slope of the resistance to the depth reaches to zero is obtained.  
           [0021]    According to another aspect of the present invention, the MOS transistor is formed on a semiconducting substrate on which a trench capacitor is formed, a buried strap is formed between the MOS transistor and the trench capacitor, the buried strap is below the semiconducting substrate by a first length and has a second length, the buried strap is adjacent to a source of the MOS transistor, and the source has a third length. The process for measuring the depth of a source and drain of the MOS transistor includes the following steps. First, resistances of the buried strap at a plurality of different depths over the second length are measured. Next, a curve correlating the resistances with the depths is established. Next, slopes of the resistance to the depth for the curve are obtained. Next, a depth corresponding to a minimum resistance before the slope of the resistance to the depth reaches to zero is obtained. Finally, the first length is subtracted from the corresponding depth to obtain the third length. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]    The present invention will become more fully understood from the detailed description given hereinbelow and theccompanying drawings, given by way of illustration only and thus not intended to be limitative of the present invention.  
         [0023]    [0023]FIG. 1 shows a circuit diagram of a DRAM cell.  
         [0024]    [0024]FIGS. 2 a  to  2   f  are cross-sections illustrating the process flow of fabricating a trench capacitor according to a conventional process.  
         [0025]    [0025]FIGS. 3 a  to  3   f  are cross-sections illustrating the process flow of fabricating a trench capacitor according to the present invention.  
         [0026]    [0026]FIG. 3 g  is a cross-section of a structure including a trench capacitor connected to a transistor according to the present invention.  
         [0027]    [0027]FIG. 4 is a diagram of the depth versus resistance of a buried strap according to an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0028]    [0028]FIGS. 3 a  to  3   f  are cross-sections illustrating the process flow of forming a trench capacitor according to the present invention.  
         [0029]    Referring to FIG. 3 a , first, a semiconducting substrate  300  is provided. An epitaxial layer  310  is formed on the semiconducting substrate  300 , and a first pad layer  320  and a second pad layer  321  are successively formed on the epitaxial layer  310 . For example, the semiconducting substrate  300  is a P-type semiconducting substrate, the first pad layer  320  is silicon oxide, and the second pad layer  321  is silicon nitride.  
         [0030]    Subsequently, a hard mask (not shown) with an opening is formed on the second pad layer  321 . For example, the hard mask is BSG (boron-silicate glass), nitride, or a combination thereof. The combination of BSG and nitride improves the trench quality and easily controls the conditions such as depth. The second pad layer  321 , the first pad layer  320 , the epitaxial layer  310 , and the semiconducting substrate  300  are successively etched using the hard mask as a mask, forming a first trench  330  down into the semiconducting substrate  300 .  
         [0031]    Subsequently, referring to FIG. 3 b , arsenic ions are diffused into the inner walls of the trench  330  by ion implantation to form a strorage electrode layer  340 , which will serve as an electrode plate of a trench capacitor.  
         [0032]    Subsequently, silicon oxide/silicon nitride (ON) is conformally formed on the second pad layer  321  and the trench  330  by chemical vapor deposition (CVD) to form a dielectric layer  350  and a second trench  331 . The dielectric layer  350  is, for example, silicon oxide.  
         [0033]    Subsequently, referring to FIGS. 3 b  and  3   c  together, polysilicon heavily doped with arsenic (not shown) is deposited on the dielectric layer  350  to fill in the trench  331 . Next, the heavily doped polysilicon is planarized to expose the surface of the dielectric layer  350 . The residual heavily doped polysilicon is etched to form a first conducting layer  360 .  
         [0034]    Subsequently, the exposed dielectric layer  350  is etched using the second pad layer  321  as a mask to form a dielectric layer  350   a , which serves as the dielectric material between two electrode plates of the trench capacitor. A third trench  332  is formed simultaneously.  
         [0035]    Subsequently, referring to FIG. 3 d , a collar insulating layer  370  is formed on the sidewalls of the third trench  332 . A second conducting layer  361  is formed to fill in the third trench  332 . The collar insulating layer  370  can be silicon oxide, which serves as insulation and prevents current leakage. The second conducting layer  361  can be polysilicon heavily doped with arsenic and formed by deposition.  
         [0036]    Subsequently, referring to FIG. 3 e , the collar insulating layer  370  and the second conducting layer  361  are selectively etched to form a collar insulating layer  370   a  and a second conducting layer  361   a  in the third trench  332 . A fourth trench  333  is formed simultaneously.  
         [0037]    Finally, referring to FIG. 3 f , polysilicon heavily doped with arsenic (not shown) is deposited on the silicon nitride layer  321  to fill in the fourth trench  333 , which is then planarized to expose the second pad layer  321  to form a third conducting layer  362 . The first, second, and third conducting layers  360 ,  361   a , and  362 , the dielectric layer  350   a , the collar insulating layer  370   a , and the storage electrode layer  340  constitute together a trench capacitor  400 .  
         [0038]    [0038]FIG. 3 g  shows a structure including the trench capacitor  400  and a transistor  500  on the semiconducting substrate  300 .  
         [0039]    In the transistor  500 , a gate dielectric layer  391  and a gate  390  are formed on the epitaxial layer  310 . A source  392  and a drain  393  are formed in the epitaxial layer  310  along the two sides of the gate  390 . The source  392  connects to the trench capacitor  400  by a buried strap (BS)  381 , which is formed by diffusion of the trench capacitor  400 . The gate  390  can be P-type polysilicon, the gate dielectric layer  391  can be oxide or low dielectric constant material, and the source and drain  392  and  393  can be N-type diffusion regions such as arsenic implantation regions.  
         [0040]    Subsequently, the procedures of measuring the depth of source/drain according to the embodiment of the present invention are described.  
         [0041]    (a) First, a voltage is applied to the gate  390  in order to switch on the DRAM. Electrons move from the drain  393  to the source  392  and into the trench capacitor  400 .  
         [0042]    (b) The resistance of the buried strap  381  is related to the area of the buried strap  381  by the following formula (F1):  
         BSRC α (ρ·L/A)  (F1)  
         
       A=D×H  
     
         [0043]    wherein BSRC indicates the resistance, p the material properties, L the length, A the cross-sectional area, D the width of the cross-sectional area, and H the depth of the cross-sectional area of the buried strap  381 .  
         [0044]    In this embodiment, the material properties of the buried strap  381  is constant, and the length is constant. Therefore, only the cross-sectional area of the buried strap  381  influences the resistance. Moreover, the width of the cross-sectional area of the buried strap  381  is also constant. Therefore, only the depth of the cross-sectional area of the buried strap  381  influences the resistance of the buried strap  381 .  
         [0045]    (c) Subsequently, the resistances of the buried strap  381  at different depths are measured.  
         [0046]    For example, the resistances of the buried strap  381  at depths of 500 Å, 700 Å, 900 Å, 1100 Å, and 1300 Å are measured to be 13.0 KΩ, 12.3 KΩ, 10.8 KΩ, 10.7 KΩ, and 10.5 KΩ respectively. The depth vs. resistance diagram for the buried strap is depicted as FIG. 4. It can be seen from FIG. 4 that when the depth H of the buried strap  381  increases up to a critical depth 900 Å, no matter how much the depth increases, the measured resistance of the buried strap  381  does not change significantly and is about 10.7 K. Also, no matter what is the total depth of the buried strap  381  is, the critical depth does not change. Accordingly, the critical depth is the depth of the source  392  and drain  393 .  
         [0047]    In addition, when the buried strap  381  is below the semiconducting substrate by a length h 1 . The actual depth (h 3 ) of the source  392  is obtained by subtracting the length h 1  from the critical depth.  
         [0048]    According to the process of the present invention, it is very simple and quick to measure the depth of the source and drain. Thus, the quality of DRAM can be effectively controlled.  
         [0049]    The foregoing description of the preferred embodiments of this invention has been presented for purposes of illustration and description. Obvious modifications or variations are possible in light of thebove teaching. The embodiments were chosen and described to provide the best illustration of the principles of this invention and its practical application to thereby enable those skilled in thert to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the present invention as determined by theppended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.