Abstract:
A power supply voltage detection device includes a reference voltage generating circuit, an integrator circuit, a lower limit comparator, and an upper limit comparator. The reference voltage generating circuit generates lower and upper limit reference voltages by resistance-dividing a power supply voltage. The integrator circuit integrates comparative voltages extracted by resistance-dividing the power supply voltage. The lower limit comparator compares the lower limit reference voltage from the reference voltage generating circuit with an output voltage from the integrator circuit to detect that the power supply voltage becomes equal to or lower than a lower limit. The upper limit comparator compares the upper reference voltage from the reference voltage generating circuit with an output voltage from the integrator circuit to detect that the power supply voltage becomes equal to or higher than an upper limit.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a power supply voltage detection device for detecting abrupt variations in power supply voltage due to external noise and the like in an apparatus such as a microcomputer. 
     A conventional apparatus such as a microcomputer malfunctions owing to abrupt variations in power supply voltage. For this reason, a power supply voltage detection circuit detects that the power supply voltage falls outside a rated range, and the apparatus is reset upon detection of a power supply voltage variation. 
     FIG. 6 shows a conventional power supply voltage detection circuit. Referring to FIG. 6, the power supply voltage detection circuit is constituted by a lower limit comparator 11 for detecting when a power supply voltage VDD becomes equal to or lower than a rated lower limit Vref1, an upper limit comparator 12 for detecting when the power supply voltage VDD becomes equal to or higher than a rated upper limit Vref2, an AND gate 13 for ANDing an output VO11 from the lower limit comparator 11 and an output VO12 from the upper limit comparator 12, and resistors R11 and R12. 
     A reference voltage Vref1&#39; input to the lower limit comparator 11 and a reference voltage Vref2&#39; input to the upper limit comparator 12 are set with respect to the rated lower limit Vref1 and the rated upper limit Vref2 of the power supply voltage VDD as follows: 
     
         Vref1&#39;=Vref1×R12/(R11+R12) 
    
     
         Vref2&#39;=Vref2×R12/(R11+R12) 
    
     The operation of the power supply voltage detection circuit having the above arrangement will be described with reference to FIGS. 7A to 7D. Referring to FIG. 7A, when the power supply voltage VDD abruptly drops to become equal to or lower than the rated lower limit Vref1 owing to external noise or the like, the output VO11 from the lower limit comparator 11 is set at &#34;L&#34; level (Low level), as shown in FIG. 7B. As a result, an output VO13 from the AND gate 13 is also set at &#34;L&#34; level. 
     When the power supply voltage VDD abruptly rises to become equal to or higher than the rated upper limit Vref2, the output VO12 from the upper limit comparator 12 is set at &#34;L&#34; level, as shown in FIG. 7C. As a result, the output VO13 from the AND gate 13 is also set at &#34;L&#34; level, as shown in FIG. 7D. That the power supply voltage VDD becomes equal to or lower than the rated lower limit Vref1 or equal to or higher than the rated upper limit Vref2 can be detected in this manner. 
     Some apparatus such as a microcomputer operates in a wide operating voltage range and can be used with a plurality of power supply voltage ratings (e.g., operable at power supply voltages VDD of 5 V, 3 V, . . .). Obviously, in this case, when the power supply voltage VDD is changed, the rated lower limit Vref1 and the rated upper limit Vref2 also vary accordingly. 
     In the conventional power supply voltage detection circuit, however, the reference voltage Vref1&#39; for detecting when the power supply voltage VDD becomes equal to or lower than the rated lower limit Vref1 must be applied, together with the reference voltage Vref2&#39; for detecting when the power supply voltage VDD becomes equal to or higher than the rated upper limit Vref2. For this reason, when the rating of the power supply voltage VDD changes, the reference voltages Vref1&#39; and Vref2&#39; must be set again in accordance with the rated lower limit Vref1 and the rated upper limit Vref2. 
     Although this circuit is designed to detect abrupt variations in power supply voltage due to external noise and the like, the circuit also detects moderate variations in power supply voltage (the output VO13 from the AND gate 13 is set at &#34;L&#34; level) during a power-on period (a period PON in FIGS. 7A to 7D) or power-off period. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a power supply voltage detection device in which the reference voltages need not be re-generated in accordance with the power supply voltage. 
     It is another object of the present invention to provide a power supply voltage detection device which can detect only abrupt variations in power supply voltage due to external noise and the like. 
     In order to achieve the above objects, according to the present invention, there is provided a power supply voltage detection device comprising reference voltage generating means for generating lower and upper limit reference voltages by resistance-dividing a power supply voltage, integrator means for integrating comparative voltages extracted by resistance-dividing the power supply voltage, lower limit comparison means for comparing the lower limit reference voltage from the reference voltage generating means with an output voltage from the integrator means to detect when the power supply voltage becomes equal to or less than a lower limit, and upper limit comparison means for comparing the upper reference voltage from the reference voltage generating means with an output voltage from the integrator means to detect when the power supply voltage becomes equal to or greater than an upper limit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing a power supply voltage detection circuit according to an embodiment of the present invention; 
     FIGS. 2A to 2C are timing charts showing the operation of the power supply voltage detection circuit in FIG. 1 when the power supply voltage drops; 
     FIGS. 3A to 3C are timing charts showing the operation of the power supply voltage detection circuit in FIG. 1 when the power supply voltage rises; 
     FIGS. 4A to 4D are timing charts showing the operation of the power supply voltage detection circuit in FIG. 1 when external noise is superimposed on the power supply voltage; 
     FIG. 5 is a graph of the voltage characteristics of the power supply voltage detection circuit in FIG. 1, showing its operation during a power-on period; 
     FIG. 6 is a block diagram showing a conventional power supply voltage detection circuit; and 
     FIGS. 7A to 7D are timing charts showing the operation of the conventional power supply voltage detection circuit. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The present invention will be described in detail below with reference to the accompanying drawings. 
     FIG. 1 shows a power supply voltage detection circuit according to an embodiment of the present invention. Referring to FIG. 1, the power supply voltage detection circuit is constituted by a lower limit comparator 11 for detecting when a power supply voltage VDD becomes equal to or lower than a rated lower limit Vref1, an upper limit comparator 12 for detecting when the power supply voltage VDD becomes equal to or higher than a rated upper limit Vref2, an OR gate 13 for ORing an output VO1 from the lower limit comparator 11 and an output VO2 from the upper limit comparator 12, a reference voltage generating circuit 14 for generating a lower limit reference voltage, an upper limit reference voltage, and a divided voltage by resistance-dividing the power supply voltage VDD, and an integrator circuit for integrating the divided voltage output from the reference voltage generating circuit 14 and outputting the resultant voltage to the lower limit comparator 11 and the upper limit comparator 12. 
     The lower and upper limit reference values output from the reference voltage generating circuit 14 are respectively output to the lower limit comparator 11 and the upper limit comparator 12. Each of the lower limit comparator 11 and the upper limit comparator 12 is constituted by an operational amplifier having an inverting input terminal and a non-inverting input terminal. 
     The reference voltage generating circuit 14 is constituted by resistors R1 to R4 for resistance-dividing the power supply voltage VDD. A node A of the resistors R1 and R2 is connected, as a point at which a reference voltage VA is generated, to the inverting input terminal of the lower limit comparator 11. A node B of the resistors R3 and R4 is connected, as a point at which a reference voltage VB is generated, to the non-inverting input terminal of the upper limit comparator 12. The integrator circuit 15 is constituted by a resistor R5 and a capacitor C1. The integrator circuit 15 integrates the voltages at the node of the resistors R2 and R3, and supplies the integral output generated at a point C to the non-inverting input terminal of the lower limit comparator 11 and the inverting input terminal of the upper limit comparator 12. 
     When the value of the resistor R3 is set to be larger than that of the resistor R5, the relationship between the power supply voltage VDD, the reference voltages VA and VB, and a voltage VC at the point C is expressed as 
     VDD&gt;VA&gt;VC&gt;VB 
     The operation to be performed when the power supply voltage VDD abruptly drops will be described next with reference to FIGS. 2A to 2C. When the power supply voltage VDD which has been set in the range of the rated lower limit Vref1 to the rated upper limit Vref2 abruptly drops, the reference voltages VA and VB at the points A and B and the voltage VC at the point C also drop accordingly. At this time, the voltage VC at the point C drops more moderately than the reference voltage VA at the point A because the capacitor C1 is discharged. At time t1, the relationship in magnitude between the reference voltage VA at the point A and the voltage VC at the point C is reversed, and the voltage VC becomes higher than the reference voltage VA. 
     With this operation, the output VO1 from the lower limit comparator 11 is set at &#34;H&#34; level, as shown in FIG. 2B, and an output VO3 from the OR gate 13 is also set at &#34;H&#34; level, as shown in FIG. 2C. As a result, that the power supply voltage VDD becomes equal to or lower than the rated lower limit Vref1 can be detected from the output VO3 from the OR gate 13 which has changed to &#34;H&#34; level. 
     The operation to be performed when the power supply voltage VDD abruptly rises will be described next with reference to FIGS. 3A to 3C. As shown in FIG. 3A, when the power supply voltage VDD which has been set in the range of the rated lower limit Vref1 to the rated upper limit Vref2 abruptly rises, the reference voltages VA and VB at the points A and B and the voltage VC at the point C also rise accordingly. At this time, the voltage VC rises more moderately than the reference voltage VB at the point B because the capacitor C1 is charged. At time t2, the relationship in magnitude between the reference voltage VB at the point B and the voltage VC at the point C is reversed, and the voltage VC becomes lower than the reference voltage VB. 
     With this operation, the output VO2 from the upper limit comparator 12 is set at &#34;H&#34; level, as shown in FIG. 3B, and the output VO3 from the OR gate 13 is also set at &#34;H&#34; level, as shown in FIG. 3C. As a result, that the power supply voltage VDD becomes equal to or higher than the rated upper limit Vref2 can be detected from the output VO3 from the OR gate 13 which has changed to &#34;H&#34; level. 
     The operation to be performed when external noise is applied to the power supply voltage VDD is the same as that shown in FIGS. 2A to 2C and 3A to 3C. More specifically, the operation to be performed when external noise N1 in FIG. 4A is superimposed is the same as that to be performed when the power supply voltage VDD abruptly changes (drops) below the time constant, at the time of discharging, which is determined by the resistors R3 to R5 and the capacitor C1. In this case, as shown in FIGS. 4B and 4D, both the output VO1 from the lower limit comparator 11 and the output VO3 from the OR gate 13 are set at &#34;H&#34; level. 
     The operation to be performed when external noise N2 in FIG. 4A is superimposed is the same as that to be performed when the power supply voltage VDD abruptly changes (rises) beyond the time constant, at the time of charging of the capacitor C1, which is determined by the resistors R1, R2, and T5 and the capacitor C1. In this case, as shown in FIGS. 4C and 4D, both the output VO2 from the upper limit comparator 12 and the output VO3 from the OR gate 13 are set at &#34;H&#34; level. 
     FIGS. 2A to 2C, 3A to 3C, and 4A to 4D show cases wherein 1/ω (ω=2πf; f is the frequency) is smaller than the time constant. 
     FIG. 5 shows the operation to be performed when the power supply voltage VDD moderately changes. Referring to FIG. 5, when the power supply voltage VDD moderately rises, since the relationship in magnitude between the voltage VC and the reference voltage VA or VB is not reversed, both the outputs VO1 and VO2 from the upper limit comparators 11 and 12 are kept at &#34;L&#34; level. Consequently, the output VO3 from the OR gate 13 is also kept at &#34;L&#34; level. A similar operation is performed when the power supply voltage VDD moderately drops. 
     A time constant is set in the charger/discharger circuit constituted by the resistors R1 to R5 and the capacitor C1 such that the relationship in magnitude between the voltage VC and the reference voltage VA or VB is reversed when the power supply voltage VDD abruptly changes to become equal to or lower than the rated lower limit Vref1 or become equal to or higher than the rated upper limit Vref2 owing to noise or the like. At the same time, a time constant is set such that the above relationship in magnitude between the respective voltages does not change when the power supply voltage VDD moderately changes upon power-on or power-off operation. With this setting, only abrupt variations in the power supply voltage VDD can be detected. 
     In addition, the reference voltages VA and VB automatically vary in accordance with changes in power supply voltage ratings. Unlike in the conventional power supply voltage detection circuit, therefore, when the power supply voltage VDD is changed, the reference voltages need not be set again. 
     As has been described above, according to the present invention, since the degree of change in power supply voltage is determined by the time constant circuit, only abrupt variations in power supply voltage due to external noise and the like can be detected. In addition, since the upper and lower limit reference voltages are generated by resistance-dividing the power supply voltage, the reference voltages need not be set again in accordance with changes in power supply voltage ratings.