Abstract:
A novel circuit combination comprised of small scale integrated (SSI) and medium scale integrated (MSI) integrated circuits (IC) for the filtering and passing of a selected pass band of passable frequencies and of a selected amplitude is disclosed. The novel circuit combination is a special-purpose bandpass digital filter of programmable low and high frequency limits that is determined by the sample time T S  duration and the programmable low F L  and high F H  frequencies of the passable analog signal frequency having a nominal carrier signal frequency F A . The analog signal is initially tested for a minimal amplitude and converted to a binary digital signal. The pulses of the binary digital signal are counted over the sample time T S . If the number of pulses N A  counted, i.e., the analog signal frequency F A  (where frequency F A  = N A  /T S , similarly, any frequency F X  = N X  /T S ), over the sample time T S  is within the passable bandpass, i.e., passable (F L  ≦F A  &lt;F H ), a first binary signal is generated. Alternatively, if the number of pulses N A  counted over the sample time T S  is without the bandpass, i.e., not passable (F L  &gt;F A  ≧F H ), a second binary signal is generated. The first binary signal is ANDed with the binary digital signal for gating out the binary digital signal to user equipment, while, alternatively, the second binary signal inhibits the gating of the binary digital signal to user equipment. Sample times continue throughout the detection-comparing operation to ensure a continuous filtering process.

Description:
BACKGROUND OF THE INVENTION 
     The present invention is considered to be an improvement invention of our U.S. Pat. No. 3,845,399, titled Digital Filter of An Analog Signal. 
     SUMMARY OF THE INVENTION 
     In the digital filter of the present invention, an analog input signal of a frequency F A  is initially tested for minimum amplitude and is then converted to a binary digital waveform which is edge-detected to provide an edge pulse for every cycle of the analog input signal. A continuously running sample time generator generates a timing base signal or a single sample time pulse every T S  seconds, and the edge pulses are counted and compared to the bandpass over the sample time T S  by a binary counter and comparator. If the edge pulse count is within the bandpass at the end of this sample time T S  the binary counter and comparator set a flip-flop to a True state. This flip-flop is sampled at the end of this sample time T S  and the True output is transferred to a storage element which is then switched to the True state. The condition of the storage element remains in this True state throughout the first next following sample time T S  to enable an AND gate that gates out the binary digital waveform to user equipment. 
     Concurrently, during this first next following sample time T S  the counting-comparator procedure is repeated with the binary counter the number of edge pulses from the edge detector. If the number of edge pulses counted is within the bandpass, i.e., F L  ≦ F A  &lt; F H , the binary counter and comparator continue coupling a True condition to the storage element with the binary counter reset, as before, by each sample time pulse. If during this first next following sample time T S  the counter and comparator count a number of pulses without the bandpass, i.e., F L  &gt;F A  ≧F H , the binary counter and comparator set the flip-flop to a False state indicating that the analog input signal is of a frequency without the bandpass. At the end of this first next following sample time T S , the False output of the flip-flop is transferred to the storage element which is then switched to its False state. The condition of the storage element remains in its False state throughout the second next following sample time T S  to disable the AND gate from gating out the binary digital waveform to user equipment. The detecting-comparing operation continues over successive sample times T S  with the binary digital waveform gated out or not gated out to user equipment as a function of the determination that the analog input signal of frequency F A  of the immediately next previous sample time T S  was within or was without the bandpass, respectively. The limits of the bandpass, i.e., the low N L  and the high N H  numbers of the pulses that define the lower and upper limits of the bandpass N L  ≦N A  &lt;N H , are programmably set into registers, which limits are, in turn, coupled to the comparator as binary coded bits. This permits the programmable change of the lower and upper limits of the bandpass in contrast to the fixed limits of the bandpass of U.S. Pat. No. 3,845,399. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of the special-purpose bandpass digital filter of the present invention. 
     FIG. 2 is a logic level drawing of the converter edge detector, time base generator, counter-comparator register and memory element of the digital filter of FIG. 1. 
     FIG. 3a and FIG. 3b are a logic level drawing and the timing diagram therefor of the time base generator of the digital filter of FIG. 1. 
     FIG. 4, comprised of FIGS. 4a and 4b, is a logic level drawing of the counter-comparator of the digital filter of FIG. 1. 
     FIG. 5, comprised of FIGS. 5a and 5b, is a timing diagram illustrating the operation of the digital filter of FIG. 1. 
     FIG. 6 is a plot of the output of the digital filter of FIG. 1 when using the counter of FIG. 4. 
     FIG. 7 is a block diagram of a second embodiment of the special-purpose bandpass digital filter of the present invention. 
     FIG. 8 is a plot of the output of the digital filter of FIG. 7. 
     FIG. 9 is a block diagram of a third embodiment of the special-purpose bandpass digital filter of the present invention. 
     FIG. 10 is a plot of the output of the digital filter of FIG. 9. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     With particular reference to FIG. 1 there is presented a block diagram of the special-purpose passband digital filter of the present invention, the elements thereof being illustrated in detail at their logic level in FIGS. 2, 3a and 4. The special-purpose digital filter of the present invention basically establishes a fixed sample time T S  during which the actual number N A  of cycles or pulses of a binary digital signal that is derived from a sampled analog signal is counted. The number N A  is continuously being compared over the sample time T S  to the minimum number N L  and the maximum number N H  of cycles or pulses of the binary digital signal that defines the bandpass width of the digital filter. During the sample time, when it is first determined that the counted number of pulses is equal to the minimum number, i.e., N A  = N L , a first signal is generated that sets a flip-flop in a counter-comparator register to a True state from an initial False state. The counter continues counting and if prior to the end of the sample time the counted number of pulses equals the maximum number of pulses, i.e., N A  = N H , a second signal is generated that sets the flip-flop back into its original False state. At the end of the sample time the True or False state of the flip-flop is gated into a memory element, the associated True or False output of which enables or disables an AND gate to couple or to not couple the binary digital signal to user equipment. 
     Referring to the block diagram of FIG. 1 and the signal waveforms of FIG. 5, the analog signal A of a frequency F A  is coupled to converter 10. Signal A is initially coupled to amplifier 10-1 which is an isolation and threshhold detector which compares signal A to a threshhold level and if signal A is above the threshhold level couples signal A to converter 10-2. Converter 10-2 converts the analog signal A of the frequency F A  to the binary digital signal B which is, in turn, via line 10-3, coupled as a first input to AND gate 70. The binary digital signal B is also coupled, via line 10-4, to edge detector 20 which produces, as an output therefrom, signal C which consists of a single short duration output pulse for every complete input cycle, i.e., for each positive transition, of signal B and, correspondingly, signal A. Signal C is, in turn, via line 20-2, coupled to counter-comparator 30. At binary counter 30-1, the pulses of signal C, beginning at time t 0  which is the beginning of the given sample time T S  over which the signal A is to be sampled, are counted with the running total count therefrom being coupled, in parallel, to lower band edge detector 30-2, via line 30-8, and upper band edge detector 30-3, via line 30-9. 
     The binary counter 30-1, beginning at time t 0  which is the start of the given sample time over which the analog signal A is to be sampled, counts and accumulates the actual number N A  of the binary digital signal B. When lower band edge detector 30-2 determines within the given sample time T S  that the actual number N A  of pulses that have been counted by binary counter 30-1 is equal to the minimum number of the bandpass, i.e., N A  = N L , lower band edge detector 30-2 generates a signal G that is coupled, via line 30-6, to flip-flop 50-2 of counter-comparator register 50. Signal G sets flip-flop 50-2 to its True state from its initial False state. The binary counter 30-1 continues counting the actual number N A  of pulses during the given sample time from time t 0  through t 1  and if prior to the end of the given sample time, as at t 1 , the actual number N A  of pulses has reached the minimum number of pulses just in excess of the band width, i.e., N A  = H H , the upper band edge detector 30-3 generates a signal H which is coupled via line 30-7, as a first input to NAND 50-3 which signal H resets flip-flop 50-2 back into its original False state (if previously switched into its True state by signal G). 
     Concurrently at time t 0 , time base generator 40-1 of sample time generator 40, which time base generator 40-1 is a continuously running oscillator of a frequency F = 1/T S  generates a sample time pulse signal D and through inverter 40-2 the sample timing pulse signal E which is coupled, in parallel, via line 40-3, to trailing edge detector 50-1 of counter-comparator register 50 and, via line 40-4, to inverter 60-2 of memory element 60. Trailing edge detector 50-1 generates signal F, which is a relatively short duration pulse at each positive transition of trailing edge of signal E, and which signal F is, in turn, coupled, in parallel, to binary counter 30-1 of counter comparator 30, via line 50-5, and to NAND 50-3 of counter-comparator register 50 via line 50-9. Signal F is a second input at NAND 50-3 and enables the signal H, if present, to, via inverter 50-4, set flip-flop 50-2 back into its False state from its True state established by the previous, in time, signal G. Signal F also resets binary counter 30-1 back to its initial state at the end of a given sample time as at time t 1 , while signal E via line 40-4 and inverter 60-2 gates the state of flip-flop 50-2 into edge triggered flip-flop 60-1 of memory element 60. The output of memory element 60 is, in turn, via line 60-3, coupled as a second input to AND 70. Thus, whenever flip-flop 50-2 is in its True state at the beginning of a sample time T S , its True output at AND 70 enables the binary digital signal B to be gated therethrough as signal O and thence to be coupled to user equipment. Conversely, whenever flip-flop 50-2 is in its False state at the beginning of a sample time T S , its False output at AND 70 disables the binary digital signal B from being gated therethrough. 
     Referring in particular to the logic level drawings of FIGS. 2, 3a and 4, the elements thereof are commercially available SSI or MSI IC elements, the operating characteristics of which are well understood by those of ordinary skill in the art. With more particular reference to FIG. 4, counter-comparator 30 is comprised of counter 30-1 which is constructed of eight flip-flops, e.g., Motorola MC 945, intercoupled in a manner as more detailed with particular respect to stage 0 thereof. Signal C, via line 20-2, triggers counter 30-1, one count per pulse of signal B, the counts of which are coupled from the outputs of the respective stages 0 through 7 of counter 30-1 to the respective input lines of lower band edge detector 30-2 (formed of, e.g., two TI Comparators SN 7485, 30-2a and 30-2b) and upper band edge detector 30-3 (formed of, e.g., two Comparators SN 7485, 30-3a and 30-3b). 
     Also provided are two associated registers, or, e.g., sets of switches, 30-4 and 30-5 for coupling the respective binary coded bits L 0  through L 7 , represented by the respectively associated voltage levels of logic 1 or 0, of register 30-4 to the respective inputs of lower band edge detector 30-2 and for coupling the respective binary coded bits H 0  through H 7  of register 30-5 to the respective inputs of upper band edge detector 30-3. Thus, the changing or actual count N A  as counted by and accumulated in counter 30-1 is coupled, in parallel, to lower band edge detector 30-2 and upper band edge detector 30-3 while, concurrently, the minimum number of pulses of the bandpass N L , as represented by the bits L 0  through L 7 , and the minimum number of pulses just in excess of the bandpass N H , as represented by bits H 0  through H 7 , are being compared thereto by lower band edge detector 30-2 and upper band edge detector 30-3, respectively. Thus, as explained hereinabove, with counter 30-1 starting to count and accumulate the actual count N A  from an initial cleared state or 0 count at the beginning of a sample time T S , as at time t 0 , lower band edge detector 30-2 compares the actual count N A  to the count N L  and when, and if, N A  = N L  it generates and couples a signal G to its associated single output line 30-6. As counter 30-1 continues its counting and accumulating of the actual count N A , if prior to the start of the next following sample time T S , as at time t 1 , upper band edge detector 30-3 compares the actual count N A  to the count N H  and when, and if, N A  = N H  it generates and couples a signal H to its single associated output line 30-7. Signal F, via line 50-5, is utilized to reset or clear counter 30-1 at the start of each sample time T S  for the next count-compare operation during the next following sample time T S . 
     With particular reference to FIG. 5 there is presented a timing diagram for a typical set of waveforms that may be associated with the digital filter of FIG. 1. In this exemplary illustration of typical waveforms it is assumed that the minimum number of pulses of the bandpass N L  = 6 and, accordingly, the configuration of the bits coupled to and stored in register 30-4 of FIG. 4 is as follows: 
     
         ______________________________________L.sub.7, L.sub.6,         L.sub.5,                 L.sub.4,                       L.sub.3,                             L.sub.2,                                   L.sub.1,                                         L.sub.00     0       0       0     0     1     1     0.______________________________________ 
    
     It is also assumed that the minimum number of pulses just in excess of the bandpass N H  = 20, and, accordingly, the configuration of the bits in register 30-5 of FIG. 4 is as follows: 
     
         ______________________________________H.sub.7, H.sub.6,         H.sub.5,                 H.sub.4,                       H.sub.3,                             H.sub.2,                                   H.sub.1,                                         H.sub.00     0       0       1     0     1     0     0.______________________________________ 
    
     Using this assumed bandpass of N L  = 6 and N H  = 20, it can be seen that during the sample time T S  of from time t 0  through t 1 , lower band edge detector 30-2 detects an actual count N A  = N L  = 6 while upper band edge detector 30-3 does not detect the minimum number of pulses just in excess of the bandpass N A  = N H  = 20 prior to the end of the sample time T S  as at time t 1 . Accordingly, at the beginning of the first next following sample time T S , as at time t 1 , AND 70 is enabled by the True output, signal I, of memory element 60 whereby the binary digital signal B of signal O is emitted therefrom during this first next following sample time T S  as from time t 1  through time t 2 . 
     During the first next following sample time T S  as from time t 1  through time t 2 , lower band edge detector 30-2 detects an actual count N A  = N L  = 6 such that the so-generated signal G sets the flip-flop 50-2 into its True state. However, prior to the end of the first next following sample time T S  as at time t 2  upper band edge detector 30-3 detects an actual count N A  = N H  = 20 such that upper band edge detector 30-3 generates a signal H which resets flip-flop 50-2 back into its initial False state. Now, at the end of the first next following sample period T S  as at time t 2  the False state of flip-flop 50-2 is gated into edge triggered flip-flop 60-1 by signal E via inverter 60-2 such that memory element 60 couples its False state of signal I as a second input to AND 70 disabling the gating of the binary digital signal B to its output line as signal O. 
     During the second next following sample time T S  as from time t 2  through t 3 , lower band edge detector 30-2 detects the actual count N A  = N L  = 6 whereby it generates the signal G setting flip-flop 50-2 into its True state. Binary counter 30-1 continues its counting and accumulating of the pulses of the binary digital signal B and prior to the end of the second next following sample time T S , as at time t 3 , it does not detect the minimum number of pulses just in excess of the bandpass N A  = N H  = 20 such that no signal H is, during this second next following sample time T S , coupled to NAND 50-3 which, via inverter 50-4, would have cleared flip-flop 50-2 back to its False state. Thus, at the end of the second next following sample time T S  as at time t 3 , flip-flop 50-2 is in its True state such that the signal E via line 40-4 and inverter 60-2 gates the True state of flip-flop 50-2 into edge triggered flip-flop 60-1 such that the True output of memory element 60 of signal I is coupled as a second input to AND 70 to enable the digital signal B to be gated therethrough as the signal O. 
     With particular reference to FIG. 6 there is presented an illustration of the bandpass characteristics of the digital filter of FIG. 1 using the eight stage counter 30-1 of FIG. 4. Using an eight stage counter, and without an intervening resetting or clearing signal F, it is to be appreciated that the counter 30-1 would continuously cycle through its count 0 through 255 to start over at an equivalent count of 256 through 511 and then to start over and count through 512 through 767, the counting sequence to continue until terminated by a resetting or clearing signal F. However, even though the digital filter of FIG. 1, as implemented by the detail logic of FIGS. 2, 3a and 4, has the cyclical or periodic bandpass characteristics of FIG. 6 (the periodic characteristic repeats at a frequency F S  = 2 N  /T S  where N is the number of stages in counter 30-1 of FIG. 4), it is to be appreciated that the expected analog signal A that is to be sampled by the digital filter of FIG. 1 will not have an expected N H  or F H  above the capability of the counter 30-1, i.e., N H  ≦255. Of course, it is to be appreciated that the upper limit N H  of the particular counter-comparator 30 may be increased by the addition of additional comparators, e.g., 30-2c and 30-3c and the necessary, e.g., four stages, 8, 9, 10, 11 to counter 30-1 with the necessary addition of the additional, e.g., four stages to registers 30-4 and 30-5. It is to be appreciated further that the output of this filter is a constant level digital signal set by logic gate 70 of FIG. 1, assuming that the input signal meets the amplitude and passband requirements of the circuit. This signal may subsequently be amplified or filtered to obtain and arbitrary level sinusoidal signal, if required. 
     With particular reference to FIGS. 7 and 8 there are presented a block diagram of a second embodiment of the special-purpose bandpass digital filter of the present invention and a plot of the output signal O thereof. In this second embodiment, counter-comparator 30a includes a single binary counter 30-1 which is, in turn, coupled in parallel to K upper band edge detectors 30-3 1  through 30-3 k  and to K lower band edge detectors 30-2 1  through 30-2 k . The outputs of each of the lower band edge detectors 30-2 1  through 30-2 k  and the output signal F of trailing edge detector 50-1 are coupled via OR 50-12 to the Set input of FF 50-2 while, correspondingly, the outputs of each of the upper band edge detectors 30-3 1  through 30-3 k  are coupled via OR 50-10 to the Reset input of FF 50-2. This produced the multiple bandpass characteristics of FIG. 8 having the multiple passbands that extend to F X  = 0 or DC and in which the band edge frequencies F Lk  and F Hk  are related to the band edge detector comparator numbers N Lk  and N Hk  by F Lk  = N Lk  /T S  and F Hk  = N Hk  /T S . 
     With particular reference to FIGS. 9 and 10 there are presented a block diagram of a third embodiment of the special-purpose bandpass digital filter of the present invention and a plot of the output signal O thereof. In this third embodiment, counter-comparator 30b includes a single binary counter 30-1 which is, in turn, coupled in parallel to K upper band edge detectors 30-3 1  through 30-3 k  and K lower band edge detectors 30-2 1  through 30-2 k . The outputs of each of the upper band edge detectors 30-3 1  through 30-3 k  and the output signal F of trailing edge detector 50-1 are coupled via OR 50-10 to the Reset input of FF 50-2 while, correspondingly, the outputs of each of the lower band edge detectors 30-2 1  through 30-2 k  are coupled via OR 50-12 to the Set input of FF 50-2. This produces the multiple bandpass characteristics of FIG. 10 having the multiple passbands that do not extend to F X  = 0 and in which the band edge frequencies are related to the band edge detector comparator numbers as in FIGS. 7 and 8.