Abstract:
In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. An input driver is connected to the input of two transfer gates. The output of one transfer gate is connected to an I/O of a first latch and the output of the second transfer gate is connected to the I/O of a second latch. The I/O of the first latch is connected to a first input of a tristatable input inverter. The I/O of the second latch is connected to a second input of the tristatable input inverter. The output of the tristatable input inverter is connected to the I/O of a third latch and the input of an output driver.

Description:
FIELD OF THE INVENTION 
   This invention relates generally to latch design. More particularly, this invention relates to improving soft error immunity in latches. 
   BACKGROUND OF THE INVENTION 
   High-energy neutrons lose energy in materials mainly through collisions with silicon nuclei that lead to a chain of secondary reactions. These reactions deposit a dense track of electron-hole pairs as they pass through a p-n junction. Some of the deposited charge will recombine, and some will be collected at the junction contacts. When a particle strikes a sensitive region of a latch, the charge that accumulates could exceed the minimum charge that is needed to “flip” the value stored on the latch, resulting in a soft error. 
   The smallest charge that results in a soft error is called the critical charge of the latch. The rate at which soft errors occur (SER) is typically expressed in terns of failures in time (FIT). 
   A common source of soft errors are alpha particles which may be emitted by trace amounts of radioactive isotopes present in packing materials of integrated circuits. “Bump” material used in flip-chip packaging techniques has also been identified as a possible source of alpha particles. 
   Other sources of soft errors include high-energy cosmic rays and solar particles. High-energy cosmic rays and solar particles react with the upper atmosphere generating high-energy protons and neutrons that shower to the earth. Neutrons can be particularly troublesome as they can penetrate most man-made construction (a neutron can easily pass through five feet of concrete). This effect varies with both latitude and altitude. In London, the effect is two times worse than on the equator. In Denver, Colo. with its mile-high altitude, the effect is three times worse than at sea-level San Francisco. In a commercial airplane, the effect can be 100-800 times worse than at sea-level. 
   Radiation induced soft errors are becoming one of the main contributors to failure rates in microprocessors and other complex ICs (integrated circuits). Several approaches have been suggested to reduce this type of failure. Adding ECC (Error Correction Code) or parity in data paths approaches this problem from an architectural level. Adding ECC or parity in data paths can be complex and costly. 
   At the circuit level, SER may be reduced by increasing the ratio of capacitance created by oxides to the capacitance created by p/n junctions. The capacitance in a latch, among other types, includes capacitance created by p/n junctions and capacitance created by oxides. Since electron/holes pairs are created as high-energy neutrons pass through a p/n junction, a reduction in the area of p/n junctions in a latch typically decreases the SER. Significant numbers of electron/hole pairs are not created when high-energy neutrons pass through oxides. As a result, the SER may typically be reduced by increasing the ratio of oxide capacitance to p/n junction capacitance in a SRAM cell. 
   There is a need in the art to reduce the SER in latches. An embodiment of this invention reduces the SER in latches while adding only a small increase in physical size of the latch and a small increase in the delay time through the latch. 
   SUMMARY OF THE INVENTION 
   In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. An input driver is connected to the input of two transfer gates. The output of one transfer gate is connected to an I/O of a first latch and the output of the second transfer gate is connected to the I/O of a second latch. The I/O of the first latch is connected to a first input of a tristatable input inverter. The I/O of the second latch is connected to a second input of the tristatable input inverter. The output of the tristatable input inverter is connected to the I/O of a third latch and the input of an output driver. The output of the output driver is the output of the triple redundant latch. 
   This preferred embodiment allows a reduction in the size of a triple redundant latch with only a small increase in the delay time through the latch. 
   Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic of a triple redundant latch. Prior Art 
       FIG. 2  is a schematic of an improved triple redundant latch. 
       FIG. 3  is a schematic of an improved triple redundant latch. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1  is a schematic of a triple redundant latch. The input,  100 , to the triple redundant latch is connected to the input of transfer gates, TG 1 , TG 2 , and TC 3 . Control signal,  102 , is connected to transfer gates, TG 1 , TG 2 , and TG 3 . Control signal,  102 , controls when the signal on the input of transfer gates, TG 1 , TG 2 , and TG 3  is transferred to the outputs,  104 ,  106 , and  108  of transfer gates, TG 1 , TG 2 , and TG 3  respectively. The signal presented to outputs,  104 ,  106 , and  108 , is stored in LATCH 1 , LATCH 2 , and LATCH 3  respectively. 
   After control signal,  102 , is turned off, the signal on LATCH 1  drives the input of inverter, INV 1 . After control signal,  102 , is turned off, the signal on LATCH 2  drives the input of inverter, INV 2 . After control signal,  102 , is turned off, the signal on LATCH 3  drives the input of inverter, INV 3 . The output,  110 , of inverter, INV 1 , drives an input to AND 1  and an input to AND 2 . The output,  112 , of inverter, INV 2 , drives an input to AND 1  and an input to AND 3 . The output,  114 , of inverter, INV 3 , drives an input to AND 2  and an input to AND 3 . The output,  116 , of AND 1  drives an input of OR 1 . The output,  118 , of AND 2  drives an input of OR 1 . The output,  120 , of AND 3  drives an input of OR 1 . The output of the triple redundant latch is the output,  122  of OR 1 . 
   A triple redundant latch reduces soft errors by storing the same data in three different latches. For example, when the control signal,  102  is on, a logical high value may be driven from the inputs,  100 , of transfer gates, TG 1 , TG 2 , and TG 3  to the outputs,  104 ,  106 , and  108 , of transfer gates, TG 1 , TG 2 , and TG 3  respectively. After turning control signal  102  off, a logical high value is stored in latches, LATCH 1 , LATCH 2 , and LATCH 3 . The stored high value on LATCH 1  drives the input of inverter, INV 1 , and produces a logical low value on the output,  110 , of inverter, INV 1 . The stored high value on LATCH 2  drives the input of inverter, INV 2 , and produces a logical low value on the output,  112 , of inverter, INV 2 . The stored high value on LATCH 3  drives the input of inverter, INV 3 , and produces a logical low value on the output,  114 , of inverter, INV 3 . 
   Since the output,  110 ,  112 , and  114  of inverters, INV 1 , INV 2 , and INV 3 , respectively, are low, all the inputs,  110 ,  112 , and  114  to AND 1 , AND 2 , and AND 3  respectively are a logical low value. Since all the inputs,  110 ,  112 , and  114 , to AND 1 , AND 2 , and AND 3  respectively are a logical low value, the output,  116 ,  118 , and  120  of AND 1 , AND 2 , and AND 3  respectively are a logical low value. Since the output,  116 ,  118 , and  120  of AND 1 , AND 2 , and AND 3 , respectively are a logical low value, all the inputs of OR 1  are a logical low value. Since all the inputs,  116 ,  118 , and  120  to OR 1  are logical low value, the output,  122 , is logical low value. 
   If a soft error occurs, for example, in LATCH 2 , and changes the stored logical value from a logical high value to a logical low value, a logical low value is now presented to the input,  106 , of inverter, INV 2 . The output,  112 , of inverter, INV 2 , presents a logical high value to an input of AND 1  and AND 3 . Since, in this example, the other input,  110  to AND 1  and the other input,  114 , to AND 3 , is a logical low value, the output,  116  and  120  of AND 1  and AND 3  respectively remains a logical low value and the output,  122 , does not change. This example illustrates how a single soft error in one latch does not change the original stored value in a triple redundant latch. 
   As a further example, assume, in addition to the soft error in LATCH 2 , there is an additional soft error in LATCH 3 . Now, the input,  108 , to inverter, INV 3 , is a logical low value and as a result, the output,  114 , of inverter, INV 3 , is a logical high value. A logical high value in now presented to an input,  114 , of AND 2 , and to an input,  114 , of AND 3 . Since a logical low and logical high valued are presented on the inputs of AND 1 , the output,  116  of AND 1  is still a logical low value. Since a logical low and logical high valued are presented on the inputs of AND 2 , the output,  118  of AND 2  is still a logical low value. However, since inputs,  112  and  114 , to AND 3  are a logical high value, the output,  120 , is a logical high value. Since input,  120 , to OR 1  is a logical high value, the output,  122 , changes from a logical low value to a logical high value. This example illustrates how soft errors in two latches of a triple redundant latch does change the original stored value of the triple redundant latch. 
   A triple redundant latch prevents a single soft error from changing the original value stored in the latch. However, this comes at the cost of additional circuitry which results in a physically larger latch. In addition, a triple redundant may introduce time delay in the delay path of the latch. As consequence, a triple redundant latch is usually larger and slower than a single latch. 
     FIG. 2  is a schematic of an improved triple redundant latch. An input driver,  218 , receives a signal at its input,  200 , and drives a signal from its output,  202 , to the inputs,  202 , of transfer gates, TG 1 ,  220 , and TG 2 ,  222 . In addition, a tristatable input inverter, a cross-coupled NAND gate, and a cross-coupled NOR gate may used in place of a transfer gate. If the control signal,  204  is on, the signal at the input,  202 , of transfer gates, TG 1 ,  220 , and TG 2 ,  222  is transferred to the output,  206 , of transfer gate, TG 1 ,  220  and to the output,  208 , of transfer gate, TG 2 ,  222 . The same signal is stored in LATCH 1 ,  224 , and LATCH 2 ,  226 . 
   After control input,  204 , is turned off, LATCH 1 ,  224 , and LATCH 2 ,  226  retain the same signal. The signal stored in LATCH 1 ,  224 , and LATCH 2 ,  226 , is then applied to the inputs of the tristatable input inverter,  228 . A tristatable input inverter,  228 , actively drives a logical high value on the output,  214 , when both inputs,  206  and  208 , are logical low values. A tristatable input inverter,  228 , actively drives a logical low value on the output,  214 , when both inputs,  206  and  208 , are logical high values. When the inputs,  206  and  208 , have opposite logical values, the output,  214 , of the tristable input inverter,  228 , is tristated. 
   In this example, if neither of the latches, LATCH 1 ,  224 , and LATCH 2 ,  226 , is disturbed, then a signal of the same sense is presented on each of the two inputs,  206  and  208 , of the tristatable input inverter,  228 . For example, if a logical high value is stored in each latch, LATCH 1 ,  224 , and LATCH 2 ,  226 , then a logical high value is presented on each of the inputs of the tristatable input inverter,  228 . In this example, since both inputs,  206  and  208 , are a logical high value, the output,  214 , of the tristatable input inverter,  228 , is a logical low value. The logical low value on the output,  228 , of the tristatable input inverter,  228 , is then stored in the latch, LATCH 3 ,  230 . In this example, the logical low value presented to input,  214 , of the output driver,  232 , is driven to the output,  216 , of the output driver,  232 . Depending on the particular application, the output,  216 , of the output driver may or may not be the same sense as the input,  214 , to the output driver,  232 . 
   If in this example where a logical high value is stored in latches, LATCH 1 ,  224  and LATCH 2 ,  226 , LATCH 1 ,  224 , for example, is flipped to a logical low value by a soft error event, a logical low value is then presented to input,  206 , of the tristatable input inverter,  228 . Input,  208 , remain a logical high value. When the inputs,  206  and  208 , are the opposite sense, the output,  214 , of the tristatable input inverter,  228 , is tristated. Because the output,  214 , of the tristatable input inverter,  228 , is tristated, the logical value on node  214 , remains a logical low value. Because the logical value on node  214  remains a logical low value, the triple redundant latch retains the original value stored in it. 
   In this example, a single soft error did not change the original value stored in the triple redundant latch. 
   If, however, a soft error event changes the value stored in LATCH 1 ,  224  and another softer error event changes the value stored in LATCH 2 ,  226 , the triple redundant latch will change from its original value. For example, if a logical high value is stored in the triple redundant latch, LATCH 1 ,  224 , and LATCH 2 ,  226  each will retain a logical high value and LATCH 3 ,  230 , will retain a logical low value. If a soft error event changes the logical value stored in LATCH 1 ,  224 , from a logical high value to a logical low value and another soft error event changes the logical value stored in LATCH 2 ,  226 , from a logical high value to a logical low value, the inputs,  206  and  208 , into the tristatable input inverter,  228 , change from logical high values to logical low values. As a result of having logical low values on the inputs,  206  and  208 , of the tristatable input inverter,  228 , the output,  214 , of the tristatable input inverter,  228 , is a logical high value. Since the output,  214 , is a logical high value, the value stored on LATCH 3 ,  230 , changes from a logical low value to a logical high value. In this example, the original value stored in the triple redundant latch is changed from a logical high value to a logical low value. 
   In addition to improving the soft error rate of a latch, the triple redundant latch shown in  FIG. 2 , also reduces the physical size of a triple redundant latch because it uses fewer transistors. The triple redundant latch shown in  FIG. 2  also reduces the delay time through a triple redundant latch because the number of logic delays has been reduced. 
     FIG. 3  is a schematic of an improved triple redundant latch.  FIG. 3  contains the same basic blocks that  FIG. 2  contains; input driver,  330 , transfer gate  1 ,  332 , transfer gate  2 ,  334 , LATCH 1 ,  336 , LATCH 2 ,  338 , tristatable input inverter,  340 , LATCH 3 ,  344 , and output driver,  346 . An embodiment of an input driver,  330 , for the triple redundant latch contains a PFET, MP 1  and an NFET, MN 1 . In this embodiment, the source of the PFET, MP 1  is connected to VDD, the drain,  302 , is connected to the output of the input driver,  330 , and the drain of the NFET, MN 1 . The gates,  300 , of the PFET, MP 1 , and the NFET, MN 1 , are connected to the input of the input driver,  330 . The source of the NFET, MN 1 , is connected to GND. 
   An embodiment of a transfer gate  1 ,  332 , for the triple redundant latch contains a PFET, MP 2  and an NFET MN 2 . In this embodiment, the drains of PFET, MP 2 , and NFET, MN 2 , are connected to the input,  302 , of transfer gate  1 ,  332 . The sources of PFET, MP 2 , and NFET, MN 2 , are connected to the output,  312 , of transfer gate  1 ,  332 . The gate of PFET, MP 2 , is connected to the control input,  306 , of transfer gate  1 ,  332 . The gate of NFET, MN 2 , is connected to the control input,  304 , of transfer gate  1 ,  332 . 
   An embodiment of a transfer gate  2 ,  334 , for the triple redundant latch contains a PFET, MP 3  and an NFET MN 3 . In this embodiment, the drains of PFET, MP 3 , and NFET, MN 3 , are connected to the input,  302 , of transfer gate  2 ,  334 . The sources of PFET, MP 3 , and NFET, MN 3 , are connected to the output,  314 , of transfer gate  2 ,  334 . The gate of PFET, MP 3 , is connected to the control input,  306 , of transfer gate  2 ,  334 . The gate of NFET, MN 3 , is connected to the control input,  304 , of transfer gate  1 ,  334 . 
   An embodiment of LATCH 1 ,  336 , for the triple redundant latch contains PFET, MP 4 , NFET, MN 4 , PFET, MP 5 , and NFET, MN 5 . In this embodiment, the drains of PFET, MP 4 , and NFET, MN 4 , and the gates of PFET, MP 5  and NFET, MN 5 , are connected to I/O,  312 , of LATCH 1 ,  336 . The drains of PFET, M 5 , and NFET, MN 5 , and the gates of PFET, MP 4  and NFET, MN 4 , are connected to node,  316 , of LATCH 1 ,  336 . The sources of PFETs, MP 4  and MP 5 , are connected to VDD. The sources of NFETs, MN 4  and MN 5 , are connected to GND. 
   An embodiment of LATCH 2 ,  338 , for the triple redundant latch contains PFET, MP 6 , NFET, MN 6 , PFET, MP 7 , and NFET, MN 7 . In this embodiment, the drains of PFET, MP 6 , and NFET, MN 6 , and the gates of PFET, MP 7  and NFET, MN 7 , are connected to I/O,  314 , of LATCH 2 ,  338 . The drains of PFET, MP 7 , and NFET, MN 7 , and the gates of PFET, MP 6  and NFET, MN 6 , are connected to node,  318 , of LATCH 2 ,  338 . The sources of PFETs, MP 6  and MP 7 , are connected to VDD. The sources of NFETs, MN 6  and MN 7 , are connected to GND. 
   An embodiment of a tristatable input inverter,  340 , for the triple redundant latch contains PFET, MP 8 , PFET, MP 9 , NFET, MN 8 , and NFET, MN 9 . In this embodiment, the drains of PFET, MP 9 , and NFET, MN 8 , are connected to the output,  320 , of the tristatable input inverter,  340 . The drain of PFET, MP 8 , and the source of PFET, MP 9  are connected to node,  326 . The drain of NFET, MN 9 , and the source of NFET, MN 8  are connected to node,  328 . The gate of PFET, MP 8 , and the gate of NFET, MN 9 , are connected to an input,  312 , of tristatable input inverter,  340 . The gate of PFET, MP 9 , and the gate of NFET, MN 8 , are connected to an input,  314 , of tristatable input inverter,  340 . The source of PFET, MP 8  is connected to VDD. The sources of NFET, MN 9 , are connected to GND. 
   An embodiment of LATCH 3 ,  344 , for the triple redundant latch contains PFET, MP 10 , NFET, MN 10 , FET, MP 11 , and NFET, MN 1 . In this embodiment, the drains of PFET, MP 10 , and NFET, MN 10 , and the gates of PFET, MP 11  and NFET, MN 11 , are connected to I/O,  320 , of LATCH 3 ,  344 . The drains of PFET, MP 11 , and NFET, MN 11 , and the gates of PFET, MP 10  and NFET, MN 10 , are connected to node,  322 , of LATCH 3 ,  344 . The sources of PFETs, MP 10  and MP 1 , are connected to VDD. The sources of NFETs, MN 10  and MN 11 , are connected to GND. 
   An embodiment of an output driver,  346 , for the triple redundant latch contains a PFET, MP 12  and an NFET, MN 12 . In this embodiment, the source of the PFET, MP 12  is connected to VDD, the drain,  324 , is connected to the output of the output driver,  346 , and the drain of the NFET, MN 12 . The gates,  320 , of the PFET, MP 12 , and the NFET, MN 12 , are connected to the input of the input driver,  346 . The source of the NFET, MN 12 , is connected to GND. 
     FIG. 3  is a schematic of an improved triple redundant latch. An input driver,  330 , receives a signal at its input,  300 , and drives a signal from its output,  302 , to the inputs,  302 , of transfer gate  1 ,  332 , and transfer gate  2 ,  334 . If control signal,  304  is a logical high value and control signal,  306 , is a logical low value, the signal at the input,  302 , of transfer gate  1 ,  332 , and transfer gate  2 ,  334  is transferred to the output,  312 , of transfer gate  1 ,  332  and to the output,  314 , of transfer gate  2 ,  334 . The same signal is stored in LATCH 1 ,  336 , and LATCH 2 ,  338 . 
   After control input,  304 , is driven to a logical low value, and control input,  306 , is driven to a logical high value, LATCH 1 ,  336 , and LATCH 2 ,  338  retain the same signal. The signal stored in LATCH 1 ,  336 , and LATCH 2 ,  338 , is then applied to the inputs of the tristatable input inverter,  340 . If neither of the latches, LATCH 1 ,  336 , and LATCH 2 ,  338 , is disturbed, then a signal of the same sense is presented on each of the two inputs,  312  and  314 , of the tristatable input inverter,  340 . For example, if a logical high value is stored in each latch, LATCH 1 ,  336 , and LATCH 2 ,  338 , then a logical high value is presented on each of the inputs,  312  and  314 , of the tristatable input inverter,  340 . In this example, since both inputs,  312  and  314 , are a logical high value, the output,  320 , of the tristatable input inverter,  340 , is a logical low value. The logical low value on the output,  320 , of the tristatable input inverter,  340 , is then stored in the latch, LATCH 3 ,  344 . In this example, the logical low value presented to input,  320 , of the output driver,  346 , is driven to a logical one at the output,  324 , of the output driver,  346 . 
   If in this example where a logical high value is stored in latches, LATCH 1 ,  336  and LATCH 2 ,  338 , LATCH 1 ,  336 , for example, is flipped to a logical low value by a soft error event, a logical low value is then presented to input,  312 , of the tristatable input inverter,  340 . Input,  314 , remain a logical high value. When the inputs,  312  and  314 , are the opposite sense, the output,  320 , of the tristatable input inverter,  340 , is tristated. Because the output,  320 , of the tristatable input inverter,  340 , is tristated, the logical value on node  320 , remains a logical low value. Because the logical value on node  320  remains a logical low value, the triple redundant latch retains the original value stored in it. 
   In this example, a single soft error did not change the original value stored in the triple redundant latch. 
   If, however, a soft error event changes the value stored in LATCH 1 ,  336  and another softer error event changes the value stored in LATCH 2 ,  338 , the triple redundant latch will change from its original value. For example, if a logical high value is stored in the triple redundant latch, LATCH 1 ,  336 , and LATCH 2 ,  338  each will retain a logical high value and LATCH 3 ,  344 , will retain a logical low value. If a soft error event changes the logical value stored in LATCH 1 ,  336 , from a logical high value to a logical low value and another soft error event changes the logical value stored in LATCH 2 ,  338 , from a logical high value to a logical low value, the inputs,  312  and  314 , into the tristatable input inverter,  340 , change from logical high values to logical low values. As a result of having logical low values on the inputs,  312  and  314 , of the tristatable input inverter,  340 , the output,  320 , of the tristatable input inverter,  340 , is a logical high value. Since the output,  340 , is a logical high value, the value stored on LATCH 3 ,  344 , changes from a logical low value to a logical high value. In this example, the original value stored in the triple redundant latch is changed from a logical high value to a logical low value. 
   In addition to improving the soft error rate of a latch, the triple redundant latch shown in  FIG. 3 , also reduces the physical size of a triple redundant latch because it uses fewer transistors. The triple redundant latch shown in  FIG. 3  also reduces the delay time through a triple redundant latch because the number of logic delays is reduced. 
   The foregoing description of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.