Abstract:
A method and device for switching power semi-conductors on and off, especially for IGBTs and MOS-FETs with inductive loads, and how they would be employed with torque-variable asynchronous machines, in ignition systems for spark ignition engines, in switch mode power supplies and power factor controllers. During a switching operation of the power semiconductor, a voltage across the semiconductor and the current through the semiconductor are measured, a time function of the voltage as well as a time function of the current are controlled, and the control of the voltage time function and the control of the current time function are effected essentially one after the other.

Description:
RELATED APPLICATIONS 
   This application claims the right of priority under 35 U.S.C. §120, as authorized by 35 U.S.C. §365(c) to International Application No. PCT/EP01/14226 filed on Dec. 5, 2001 by the same inventors (published under PCT Article 21(2) in German and not English), which claims priority to Application No. 100 61 563.5 filed in Germany on Dec. 6, 2000, both of which are incorporated herein by reference in their entirety. 

   FIELD OF THE INVENTION 
   The present invention relates to the field of switching power semiconductors. More specifically, the invention is related to methods and apparatuses for switching power semiconductors, in particular power transistors, insulated gate bipolar transistors (IGBTs) and metal oxide field effect transistors (MOS-FETs). 
   The present invention is preferably used for controlling electric induction motors at variable speeds, for operating ignition circuits in internal combustion engines, and for operating switched-mode power supplies and power-factor-controllers. 
   BACKGROUND OF THE INVENTION 
   It is well-known in the art to use power semiconductors of the type specified above for various control purposes, as described in an article by Rüedi, Heinz et al. “Dynamic Gate Controller—A new IGBT gate unit for high current/high voltage IGBT modules”, Power Conversion, June 1995 Proceedings, pages 241 through 249. A method for operating an ignition system and a corresponding ignition circuit is described in an article of Lokuta, Fred et al. “Damit es richtig zündet”, Design &amp; Elektronik, No. 25/26 of Dec. 10, 1996, pages 52 through 54. 
   A switch-mode power supply of the above-mentioned kind is described in the data sheet “LT1533” from the Linear Technology Company of January 1999. 
   Power-factor-controllers (PFCs) are well-known in the art in various configurations, for example from an article by Noon, James, “PFC controllers optimised for functional requirements”, PCIM Europe, No. 4, 2000, pages 22 through 25, from another article by the same author “Netzschwankungen korrigieren”, Leistungselektronik &amp; Stromversorgung, April 2000, pages 40 through 43, from an article by Goddard, Thomas, “Controller combines ‘Green’ mode with PFC and PWM”, Power Electronics Engineering Europe, June 1999, pages 12 through 16, as well as from a data sheet “BiMOS PFC/PWM Combination Controller” from the UNITRODE Company of August 1999. 
   IGBTs and power MOS-FETs are conventional semiconductor components which are distributed from various suppliers, either as single elements or as modules combining a plurality of such IGBTs (cf. data sheet “Neue lötbare Sixpacks der IGBT Plus-Serie Econo Plus” from the Toshiba Company of June 1998). 
   As already mentioned, such IGBTs and MOS-FETs are typically used for switched-mode power supplies, power-factor-controllers, ignition systems for internal combustion engines and for inverters controlling electrical motors. 
   For controlling such power semiconductors various driver circuits have been proposed. 
   German disclosure document DE 34 20 312 C2 discloses a control circuit for a deflection power transistor as used in a deflection circuit of a television set. The control circuit is provided with a sensor arrangement providing an actual signal being proportional to the instantaneous value of the transistor main current. The actual value signal is fed to the control circuit in order to control the switching-on base current to a predetermined value during its entire rise and as a function of the actual value signal. 
   In a doctoral thesis by Gerster, Christian “Reihenschaltung von Leistungshalbleitern mit steuerseitig geregelter Spannungsverteilung”, published in “Series in Microelectronics”, Vol. 50, Hartung-Gorre Verlag Konstanz, 1995, various methods for controlling the switching behavior of series-connected power semiconductors, for example IGBTs, are described. In this connection reference is made to so-called “Snubber”-circuits, being essentially circuits for limiting a voltage rise. 
   Further driver circuits for IGBTs are disclosed in articles by Edelmoser, K. H. et al. “Floating, flexible and intelligent gate driver circuit for IGBT half-bridge modules up to 1,200 V, 100 A”, Power Conversion, April 1992 Proceedings, pages 96 through 106, as well as in an article by Bösterling, Werner et al., “Nonproblematic gate drive of IGBT-modules”, Power Conversion, April 1992 Proceedings, pages 87 through 95. 
   As already mentioned above, IGBTs are today conventionally used in electrical inverters. They generate a frequency variable 3-phase voltage from a DC voltage for operating electrical motors at variable speeds, in particular induction motors, being also designated as “asynchronous motors”. In contrast to thyristors, having been used in earlier times, IGBT transistors may be switched on and off at their gate at any desired moment in time. 
   In order to effect a switching-on and a switching-off of the IGBTs in a timely controlled manner, the inverters comprise a microcontroller or a control unit. The output signals of these circuits are at 0/5 V or at −5 V/15 V and, therefore, below the control level of commercial IGBTs being at 0/15 V. Further, the output current of these circuits is too low in order to effect a direct coupling to the IGBTs. For these reasons, it is necessary to use a drive circuit. Drive circuits of a type being of interest for the present application generally have a very low impedance output and, therefore, may supply high output currents of the order of several amps. In such a way, commercial IGBT transistors for the above-mentioned applications may be brought into the operational states “ON” and “OFF”. 
   In order to effect the afore-mentioned switching operations as quickly as possible, the edge steepness of the collector emitter voltage U CE  and for the collector current I C  should be as high as possible. With short switching-over times low switching-over losses are obtained. On the other hand, the edge steepness of the two afore-mentioned variable quantities may not be selected too high, because in practice there exist limiting side conditions. For example, the variation of the collector-emitter voltage vs. time dU CE /dt must be limited because otherwise inadmissibly high displacement currents appear within the isolation of the motor. The time variation dU CE /dt of the collector-emitter voltage as well as time variation of the collector current dI C /dt must also be limited because otherwise inadmissibly high electromagnetic radiation occurs. Finally, a too high time variation dI C /dt of the collector current in connection with the parasitic inductance could cause an excess voltage at the IGBT. 
   For these reasons the edge steepness or the time function, respectively, of dU CE /dt and dI C /dt must be held low. On the other hand, this is the phase in which switching losses occur, which, in turn, determine the dissipated heat within the IGBT and, hence, shall also be small. 
   Prior art drive circuits use passive networks between the driver output and the IGBT gate and the given parameters are tuned to one another. In the above-mentioned article by Bösterling et al. two different approaches are described, one of which (FIG. 5 a  on page 91) suggesting a fixed resistor within the gate circuit of the IGBT, whereas the other approach (FIG. 6 b  on page 91) suggests to control the gate of the IGBT via two distinct resistors, each of which being adapted to be switched into the gate circuit via a transistor. Whereas, therefore, in the first mentioned approach one and the same resistor is provided for the switching-on process and for the switching-off process, the second approach utilizes two distinct resistances, wherein the resistor for the switching-off process is generally dimensioned smaller as compared to the resistor for the switching-on process. 
   This concept, however, has the disadvantage that the resistor or the resistors, respectively, may only be dimensioned according to the power semiconductor data sheet, wherein changes in the operational conditions (e.g. varying temperature), as well as in particular variations in the load may result in partially drastical deteriorations of the operational performance. 
   The article by McNeill, Neville et al. “Assessment of Off-State Negative Gate Voltage requirements for IGBTs”, IEEE Transactions On Power Electronics, Vol. 13, pages 436 through 440, 1998, comprises a general report about a potential parasitic switching-on of the switched-off IGBT due to a feedback capacity, when the first derivative of the collector-emitter voltage assumes positive values. 
   An article by Musumeci, S. et al. “A New Adaptive Driving Technique for High Current Gate Controlled Devices”, IEEE Transactions, pages 480 through 486, 1994, discloses a circuit attempting to limit the first derivative of the collector current, in order to limit EMV interferences. For that purpose two switchable voltage sources are used. A close-loop control is not provided. 
   The prior art drive circuits, therefore, have various disadvantages: 
   With a fixedly dimensioned passive network it is only possible to determine a function U CE (t) or I C (t) for one specific load. The respective other function I C (t) or U CE (t) follows automatically therefrom. Depending on the particular load of the circuit, the two time functions will vary. Moreover, the two functions are approximately highly non-linear and do not show a constant dU CE /dt and dI C /dt which, however, would be desirable due to the load on the isolation and the electromagnetic radiation. 
   Furthermore, the edge steepnesses or the time functions dU CE /dt and dI C /dt, respectively, may not be set independently one from another. By means of appropriate networks, however, they may be set differently for the switching-on process and for the switching-off process. 
   With standard dimensioning of conventional drive networks about 25% to 30% excess voltage appears at the collector-emitter voltage U CE  during the switching-off, as compared with the supply voltage. This generally requires a higher voltage class of the IGBT and, therefore, additional costs. 
   Another disadvantage of prior art drive circuits consists in that the maximum values of dU CE /dt and dI C /dt only appear over a short period of time during the switching process. Considering that the dimensioning is made depending on these threshold values, a higher dissipated power results, as compared with a switching at constant dU CE /dt and dI C /dt. 
   Finally, conventional drive circuits have the disadvantage that certain components determining the transient behavior are partially located ahead of the gate and partially at the IGBT output. These components are, therefore, exposed to high voltage. This results in high currents, and, therefore, power components at additional costs are required. 
   The article by Rüedi “Dynamic Gate Controller . . . ”, mentioned at the outset, discloses a topology for an IGBT. A drive circuit comprises a controller for the time function of the collector-emitter voltage U CE  as well as the time function of the collector current I C  and, finally, a monitoring circuit for the collector-emitter voltage U CE . The signals generated by these modules are combined in a sum node and are used for controlling the IGBT gate. Nothing is disclosed about the exact design, function and cooperation of these modules. The article, further, comprises no evidence about the effectivity of the disclosed method, for example by means of current-voltage curves. 
   German disclosure document DE 196 10 895 A1 discloses a method for controlling the switching-on process of an IGBT as well as an apparatus for carrying out said method. Although a network is used at the input of the IGBT, the network being designated as a current source, the network is functionally converted into a voltage source by feeding back the input of the network to the inverting input of an output stage (operational amplifier) being arranged ahead of the network. This prior art method also starts from predetermined parameters (characteristic curves) of the IGBT, and the collector current is not measured. As a consequence, the disclosed control is again only valid for one specific point of operation of the IGBT and does not take into account variations in ambient or load conditions. 
   U.S. Pat. No. 5,390,070 discloses a gated power output stage for inductive loads. The output stage comprises a power semiconductor, wherein both the switched current and the voltage across the power semiconductor are individually detected. From the detected time functions the first derivative is derived wherein the current signal is inverted prior to generating the first derivative. In a sum node the functions corresponding to the first derivatives are superimposed to the control square wave signal for the control electrode of the power semiconductor and the power semiconductor is controlled by means of that superimposed signal. By doing so the high rising and falling speeds, respectively, of the current signal and of the voltage signal shall be reduced. 
   This prior art power output stage allows an independent setting within the two control circuits of the current signal and the voltage signal, however, no close loop-control starting from a predetermined desired value is used, so that the current function on the one hand and the voltage function on the other hand may not be controlled individually. 
   Finally European patent specification 493 185 discloses a control circuit for a force commutated power transistor. This circuit corresponds essentially to the approach described in the above-mentioned article by Rüedi. 
   British disclosure document 2 318 467 A discloses a control circuit for a MOS-FET with inductive load. The circuit is provided with a cross-over switch enabling to connect the gate electrode of the MOS-FET with two different fixed resistors. According to the corresponding description the MOS-FET shall thus be controlled by a signal corresponding to the drain current flowing through the MOS-FET or, alternately, by a signal corresponding to the drain-source voltage across the MOS-FET. Further, it is indicated that both an open-loop control or a close-loop control might be used, however, there is no enabling disclosure how this could be done in practice because the given examples are inoperative and the associated description is incorrect. 
   U.S. Pat. No. 5,926,012 A discloses a circuit in which the first derivative of the collector current and the first derivative of the collector-emitter voltage of a transistor are detected. These variable quantities are each fed to a comparator which is also supplied with a reference value. The output of the comparators, hence, generate a logical signal “0” or “1”, depending on whether the measured value is above or below the reference value. These digital output signals “0” or “1” are then fed to an open-loop control circuit (FIGS. 6 through 10). 
   International patent disclosure document WO 00/27032 A discloses a circuit in which certain constant currents are superimposed to the gate current of a MOS-FET. FIG. 3 shows four distinct switches for four distinct current sources by means of which the gate current may be increased or decreased. The switches are operated as a function of certain threshold values so that the gate current is varied stepwise. Therefore, no continuous close-loop control is provided. 
   It is, therefore, an object underlying the invention to improve a method and an apparatus of the type specified at the outset which avoids the afore-described disadvantages. In particular, the desired switching behavior of the IGBT shall be made possible with the use of components belonging to the lowest possible power class and, hence, the lowest possible costs, by individually controlling the time functions of the collector-emitter voltage dU CE /dt and the collector current dI C /dt. Moreover, the electromagnetic radiation shall be limited to a minimum. Further, the excess voltage during the switching-off shall be reduced to a minimum, so that the admissible voltage range of the power transistor may be used to the widest possible extent. Finally, the overall dissipated power during a switching operation shall be substantially smaller as compared to conventional solutions. Moreover, it shall be possible to monolithically integrate the circuit. Finally, the control stability shall be improved. 
   SUMMARY OF THE INVENTION 
   The afore-mentioned and other objects of the invention are achieved by a method of switching power semiconductors wherein during a switching operation of the power semiconductor,
         a) a voltage (U CE ; U DS ) across said power semiconductor as well as a current (I C ; I D ) flowing through the power semiconductor are measured,   b) a time function (dU CE /dt; dU DS /dt) of the voltage (U CE ; U DS ) as well as a time function (dI C /dt; dI D /dt) of the current (I C ; I D ) are controlled, and   c) the control of the voltage time function (dU CE /dt; dU DS /dt) and the control of the current time function (dI C /dt; dI D /dt) are effected essentially one after the other,   wherein, further,   d) for controlling the voltage time function (dU CE /dt; dU DS /dt),
           a first signal (I soll ) corresponding to a desired value ([dU CE /dt]; [dU DS /dt]) of the voltage time function (dU CE /dt; dU DS /dt) and a second signal (I ist ) corresponding to an actual value (dU CE /dt; dU DS /dt) of the voltage time function (dU CE /dt; dU DS /dt) are generated,   the first signal (I soll ) and the second signal (I ist ) are subtracted one from the other,   a first difference signal (I ist −I soll ) between the first and the second signals (I ist , I soll ) is converted into a first control signal (ΔU dU ), and   
           e) for controlling the current time function (dI C /dt; dI D /dt),
           a third signal (I soll ) corresponding to a desired value ([dI C /dt]; [dI D /dt]) of the current time function (dI C /dt; dI D /dt) and a fourth signal (I ist ) corresponding to an actual value (dI C /dt; dI D /dt) of the current time function (dI C /dt; dI D /dt) are generated,   the third signal (I soll ) and the fourth signal (I ist ) are subtracted one from the other,   a second difference signal (I ist −I soll ) between the third and the fourth signals (I ist , I soll ) is converted into a second control signal (ΔI dI ).   
               

   The objects are further achieved by a method of switching power semiconductors wherein during a switching operation of the power semiconductor,
         a) a voltage (U CE ; U DS ) across the power semiconductor as well as a current (I C ; I D ) flowing through the power semiconductor are measured,   b) a voltage time function (dU CE /dt; dU DS /dt) as well as a current time function (dI C /dt; dI D /dt) are controlled, and   c) the control of the voltage time function (dU CE /dt; dU DS /dt) and the control of said current time function (dI C /dt; dI D /dt) are effected essentially one after the other,   wherein, further,   d) for controlling the voltage time function (dU CE /dt; dU DS /dt),
           a first signal (I soll ) corresponding to a desired value ([dU CE /dt]; [dU DS /dt]) of the voltage time function (dU CE /dt; dU DS /dt) and a second signal (I ist ) corresponding to an actual value (dU CE /dt; dU DS /dt) of the voltage time function (dU CE /dt; dU DS /dt) are generated,   the first signal (I soll ) and the second signal (I ist ) are subtracted one from the other,   a first difference signal (I ist −I soll ) between the first and the second signals (I ist , I soll ) is compared with a first reference signal (0), and   
            if the first difference signal (I ist −I soll ) is above the first reference value (0), the first difference signal (I ist −I soll ) is processed as a first control signal (ΔU dU ), whereas    if the first difference signal (I ist −I soll ) is below the first reference signal (0), a zero signal is processed as the first control signal (ΔU dU ), and   e) for controlling the current time function (dI C /dt; dI D /dt),
           a third signal (I soll ) corresponding to a nominal value ([dI C /dt]; [dI D /dt]) of the current time function (dI C /dt; dI D /dt) and a fourth signal (I ist ) corresponding to an actual value (dI C /dt; dI D /dt) of the current time function (dI C /dt; dI D /dt) are generated,   the third signal (I soll ) and the fourth signal (I ist ) are subtracted one from the other,   a second difference signal (I ist −I soll ) between the third and the fourth signals (I ist , I soll ) is compared with a second reference signal (0), and   
            if the second difference signal (I ist −I soll ) is above the second reference value (0), the second difference signal (I ist −I soll ) is processed as a second control signal (ΔI dI ), whereas    if the second difference signal (I ist −I soll ) is below the second reference signal (0), a zero signal is processed as the second control signal (ΔI dI ).       

   Moreover, the objects are achieved by an apparatus for switching power semiconductors comprising:
         a) means for measuring a voltage (U CE ; U DS ) across the power semiconductor as well as a current (I C ; I D ) flowing through the power semiconductor,   b) driver means for controlling a time function (dU CE /dt; dU DS /dt) of the voltage (U CE ; U DS ) as well as a time function (dI C /dt; dI D /dt) of the current (I C ; I D ), the controlling of the time functions (dU CE /dt, dI C /dt; dU DS /dt, dI D /dt) being effected one after the other, wherein the driver means comprises:   voltage time function (dU CE /dt; dU DS /dt) control means having
           means for generating a first signal (I soll ) corresponding to a desired value ([dU CE /dt]; [dU DS /dt]) of the voltage time function (dU CE /dt; dU DS /dt) and a second signal (I ist ) corresponding to an actual value (dU CE /dt, dU DS /dt) of the voltage time function (dU CE /dt; dU DS /dt),   means for subtracting the first signal (I soll ) and the second signal (I ist ) one from the other,   means for converting a first difference signal (I ist −I soll ) between the first and the second signals (I ist , I soll ) into a first control signal (ΔU dU ), and   
           current time function (dI C /dt, dI D /dt) control means having
           means for generating a third signal (I soll ) corresponding to a desired value ([dI C /dt]; [dI D /dt]) of the current time function (dI C /dt; dI D /dt) and a fourth signal (I ist ) corresponding to an actual value (dI C /dt; dI D /dt) of the current time function (dI C /dt; dI D /dt),   means for subtracting the third signal (I soll ) and the fourth signal (I ist ) one from the other,   means for converting a second difference signal (I ist −I soll ) between the third and the fourth signals (I ist , I soll ) into a second control signal (ΔI dI ).   
               

   Moreover, the objects underlying the invention are likewise achieved by an induction motor, an ignition system, and a power factor controller, respectively, all of them having means for generating from a DC supply voltage a three-phase frequency variable voltage, or a gated output ignition voltage, or a DC output voltage, respectively, by switching power semiconductors, and comprising the measuring means and the driver means as mentioned before. 
   The objects underlying the invention are thus entirely achieved. 
   According to the invention the time functions dU CE /dt and dI C /dt are controlled independently from one another. A sequence control controls the entire switching-on process and the switching-off process and guarantees at any time (also in the event of a malfunction, for example in the event of a short circuit cut-off) that both controls are solely effective during the required period of time within the time functions and do never affect each other. 
   This control of the power semiconductors, therefore, achieves the desired EMV behavior as well as the desired protection of the isolation. Experiments have evidenced that the excess voltage during the switching-off process could be reduced to less than 5% so that it is possible to take fully advantage of the admissible voltage range of the power transistor, as already mentioned. Further, it could be confirmed that the dissipated power during the switching process is substantially smaller as compared with prior art solutions in which the same limit steepness had been set. 
   Within the scope of the present invention it is particularly preferred when transistors are used as power semiconductors, in particular insulated gate bipolar transistors (IGBTs). In that case the input voltage is the gate-emitter voltage U GE , the output voltage is the collector-emitter voltage U CE  and the output current is the collector current I C . 
   In this case it is further preferred for control purposes to use the collector-emitter voltage U CE  of the transistor as control voltage and the collector current I C  of the transistor as the control current. 
   As an alternative, however, the power semiconductor may also be configured as a MOS-FET power semiconductor. In that case the input voltage is the gate-source voltage U GS , the output voltage is the drain-source voltage U DS  and the output current is the drain current I D . 
   Accordingly, for control purposes the drain-source voltage U DS  is used as the control voltage and the drain current I D  of the MOS-FET as the control current. 
   If in the scope of the present invention the term “time function” of a voltage or of a current is used, this term shall preferably mean the first time derivative of the voltage function or of the current function, respectively. However, this is not to be understood as a liming feature. Instead, the invention allows to derive other variable quantities from the voltage and the current functions, for example the second time derivative, an integrated time function or the like. 
   For controlling the time function during switching-on and switching-off of the power semiconductor it is particularly preferred to control the current time function first and the voltage time function second during the switching-on of the power semiconductor. 
   Accordingly, when the power semiconductor is switched-off, the voltage time function is preferably controlled first and the current time function second. 
   These approaches take advantage of the fact that the afore-mentioned quantities for the voltage value and the current value, respectively, do significantly change during the afore-mentioned periods of time, and, hence, are particularly suitable for a separate control. 
   According to the invention, various criteria have been developed in order to effect a switching-over from the current time function to the voltage time function for a switching-on process of the power semiconductor and, for a switching-off of the power semiconductor to switch-over from the voltage time function control to the current time function control. The following criteria may be used alternately or cumulatively. 
   For the switching-on of the power semiconductor the criteria are as follows: 
   a) the current reaches a maximum value; 
   b) the current time function drops by a predetermined amount; 
   c) the voltage drops by a predetermined amount; 
   d) the voltage time function drops by a predetermined amount, in particular when the first derivative of the collector-emitter voltage falls below a predetermined negative threshold value, or the absolute value of the first derivative of the collector-emitter voltage exceeds a predetermined positive threshold value; 
   e) the power semiconductor is an IGBT, and the gate-emitter voltage reaches a predetermined value; 
   f) the power semiconductor is an IGBT, and the time function of the gate-emitter voltage drops by a predetermined amount; 
   g) the power semiconductor is a MOS-FET, and the gate-source voltage reaches a predetermined value; and 
   h) the power semiconductor is a MOS-FET, and the time function of the gate-source voltage drops by a predetermined amount. 
   For the switching-off of the power semiconductor the criteria are as follows: 
   a) the voltage reaches a predetermined value; 
   b) the voltage time function drops by a predetermined amount; 
   c) the current drops by a predetermined amount; 
   d) the absolute value of the current time function drops, in particular when the first derivative of the collector-emitter voltage falls below a predetermined negative threshold value or if the absolute value of the first derivative of the collector-emitter voltage exceeds a predetermined positive value by a predetermined amount; 
   e) the power semiconductor is an IGBT and the gate-emitter voltage reaches a predetermined value; 
   f) the power semiconductor is an IGBT and, when the first derivative of the gate-emitter voltage first assumes a negative value and then a substantially smaller value, and finally falls below a predetermined value, the moment in time when it falls below that predetermined value; 
   g) the power semiconductor is a MOS-FET and the gate-source voltage reaches a predetermined value; 
   h) the power semiconductor is a MOS-FET and, when the first derivative of the gate-source voltage first assumes a negative value and then a substantially smaller value, and finally falls below a predetermined value, the moment in time when it falls below that predetermined value. 
   All these measures and the criteria have the advantage to exactly determine the moments in time when the switching-over from the control of the one parameter to the control of the respective other parameter shall be effected. 
   In a preferred embodiment of the inventive method a signal corresponding to a desired value of the voltage time function and a signal corresponding to an actual value of the voltage time function are generated for controlling the voltage. These signals are compared with one another and the difference is again compared with a reference value. If the reference value is exceeded, the difference is processed as a control signal, whereas when the difference falls below the reference value, a zero signal is processed as the control signal. 
   Correspondingly, it is preferred when for controlling the current a signal corresponding to a desired value of the current time function and a signal corresponding to the actual value of the time function are generated. These signals, too, are compared with one another and the difference is again compared with a reference value. If the reference value is exceeded, the difference is processed as the control signal, whereas when the difference falls below the reference value, a zero signal is processed as the control signal. 
   Both concepts for controlling the collector-emitter voltage and the collector current, respectively, have the advantage that the afore-mentioned control circuits may be designed with simple and cheap elements and in simple configurations. 
   In this context it is preferred when the desired values may be set, for example by means of adjustable resistors. 
   According to the invention two further types of methods for controlling the voltage time function and the current time function are preferred, which may also be used independently from other features of the present invention. 
   On the one hand, it is preferred for controlling the voltage time function to generate a signal corresponding to a desired value of the voltage time function and a signal corresponding to the actual value of the voltage time function, to compare these signals with one another and to again compare the difference with a reference value. If the reference value is exceeded, the difference is processed as a control signal and the control signal is transformed non-linearily. 
   Correspondingly, it is preferred when for controlling the current time function a signal corresponding to a desired value of the current time function and a signal corresponding to the actual value of the current time function are generated, these signals are compared with one another and the difference is again compared with a reference value. If the reference value is exceeded, the difference is further processed as a control signal, and the control signal is transformed non-linearily. 
   These measures have the advantage that extreme non-linearities of certain power semiconductors, in particular the non-linearity of IGBTs, may effectively be compensated for, as well as the transfer characteristics of the control circuit consisting of the IGBT and its associated drive circuit. 
   Moreover, the invention prefers to limit the voltage to a predetermined threshold value. 
   This measure has the advantage that damages across the collector-emitter path and the drain-emitter path, respectively, are effectively avoided. 
   According to further embodiments of the invention the current is limited to a predetermined threshold value when the power semiconductor is switched-on. Alternately, it may be provided that the power semiconductor be cut-off when the current exceeds a predetermined threshold value. 
   Seen as a whole, these afore-mentioned measures have the advantage that the inventive apparatus operates safely with respect to excess voltages and with respect to short circuits so that the standard malfunction situations have all been taken care of. 
   According to further embodiments of the invention, the features of which may also be used independently from the other features of the present invention, the power semiconductor is controlled by means of an output stage, wherein the output stage is operated as a current output stage at lease over certain periods of time. 
   This measure has the advantage that the stability of the control circuit is increased by using a current output stage instead of a voltage output stage. The dominant cut-off frequency of the transfer function of an open control circuit is determined by the steepness of the controlled current source and the input capacity of the power semiconductor, when a current output stage is used, whereas the other cut-off frequencies, in contrast, are located at substantially higher frequencies. When, in contrast, for controlling a power semiconductor a voltage output stage is used, the poles of the loop amplification are not separated, so that there is a risk that the control circuit oscillates. 
   The invention, insofar, is contrasted to prior art driver circuits utilizing a low-impedance control directly or via resistors (typically between 5 and 100 Ω) between the driver output and the power semiconductor gate. The circuit according to the invention namely has a controlled current source in its output with a particularly high output impedance of typically more than 10 Ω. In that case the output stage, as already explained, is transferred from the “ON” to the “OFF” state after the switching-over process. For the static output condition it then assumes a predetermined voltage state at its output. The output stage, therefore, is novel with its two distinct characteristics related to its output behavior. For that purpose, the output stage, as also already mentioned, changed from a high-impedance to a low-impedance output resistance after the switching-off process, i.e. the output stage is latched. The latching is effected in order to avoid that the IGBT changes its output stage due to interferences. 
   Within this group of embodiments it is particularly preferred when the output stage is essentially operate as a current output stage during the switching process. 
   This measure has the advantage that the afore-explained advantages become effective in particular during the period of time of the transients, when the power semiconductors have to be switched-over. 
   As a supplemental measure it is further preferred when the output stage is operated as a voltage output stage in the absence of a switching process. 
   This measure has the advantage of defined operational conditions for the subsequent stationary condition of the power semiconductor. This is particularly suitable when two power semiconductors are switched in series and switch reciprocally. In that situation it must be guaranteed that the switching of the one power semiconductor does not cause an inadvertent switching of the other power semiconductor. 
   Accordingly, within this group of embodiments it is preferred when the power semiconductor is switched to-and-fro between two fixed states by means of the current output stage during the switching process. 
   If we now consider the two situations in which the power semiconductor changes from a state “OFF” into a state “ON”, it will in both cases be controlled by the current output stage with low-impedance and with constant voltage. 
   For effecting a change in the state of the current output stage, various criteria have been developed within the scope of the present invention which, again, may be used alternately or cumulatively, i.e. in any conceivable combination. 
   For a transition into a state “OFF” of the power semiconductor, i.e. a transition from a high-impedance output resistance to a low-impedance output resistance with fixed output voltage, the criteria are as follows: 
   a) approaching a minimum current value; 
   b) the absolute value of the current time function falls by a predetermined amount; 
   c) the power semiconductor is an IGBT and the gate-emitter voltage falls by a predetermined amount; 
   d) the power semiconductor is a MOS-FET and the gate-source voltage falls by a predetermined amount. 
   For a change into a state “ON” of the power semiconductor, i.e. a transition from a high-impedance output resistance to a low-impedance output resistance with fixed output voltage, the criteria are as follows: 
   a) approaching a minimum voltage value by a predetermined amount; 
   b) the absolute value of the voltage time function falls by a predetermined amount; 
   c) the power semiconductor is an IGBT and the gate-emitter voltage rises by a predetermined amount; 
   d) the power semiconductor is a MOS-FET and the gate-source voltage rises by a predetermined amount. 
   As already mentioned, the invention provides a driver with a sequence control for switching between the various controls of the above-mentioned parameters. The sequence control is provided according to the invention for controlling the current time function first and the voltage time function second when switching-on the power semiconductor, whereas for switching the power semiconductor off, the voltage time function is controlled first and the current time function is controlled second. 
   According to a preferred variation of the inventive apparatus, circuit means are provided for detecting and evaluating the voltage time function and the current time function and for generating control signals from this evaluation. In that case the sequence control comprises: 
   a) a first output for switching the power semiconductor on; 
   b) a second output for switching the power semiconductor off: 
   c) a first cross-over switch for feeding to the first and the second output the first control signal and the second control signal, respectively, the first cross-over switch being adapted to be operated by a first switching signal; and 
   d) a second cross-over switch between the first cross-over switch and the first and the second output for connecting the first or the second output with the first cross-over switch, the second cross-over switch being adapted to be operated by a second switching signal. 
   This embodiment of the circuitry enables the implementation of the various methods discussed in detail above, and further has the advantages of a high safety against interferences at low control voltages, as will be described below in further detail. 
   According to a variation of the afore-mentioned circuitry, the driver comprises differentiating stages for generating the first derivative of the voltage and of the current, respectively, for evaluating the voltage time function and the current time function. 
   Moreover, it is preferred when the driver comprises control stages for generating control signals from the evaluation, the control signals comprising a subtracting stage for generating a comparison between a desired value and an actual value of the voltage time function and of the current time function. 
   In the case of a voltage control the driver preferably comprises control stages for generating control signals from the evaluation, the control stages comprising characteristic line stages generating for a negative input signal a constant output signal and for a positive input signal an output signal falling from a constant value down to zero and remaining zero thereafter. 
   Accordingly, in the case of a control of the current time function it is preferred when the driver comprises control stages for generating control signals from the evaluation, the control stages comprising a characteristic line stage which for a negative input signal generates a positive constant output signal, and for a positive input signal generates an output signal falling from the positive constant value down to zero and below zero thereafter. 
   Moreover it is preferred when the driver comprises dividing stages for generating control signals from the evaluation. 
   When the afore-mentioned alternatives are implemented all together, this is preferably effected by arranging within the signal flow the differentiating stages first, followed by the subtracting stages, followed by the characteristic curve stages, and followed by dividing stages. 
   Finally it is preferred when the driver comprises a linearizing stage for generating control signals from the evaluation, the linearizing stage being preferably configured according to the so-called translinear principle according to Gilbert. 
   In a practical setup for the above-mentioned circuits the first cross-over switch is configured by transistors having base electrodes, the base electrodes being held at a constant potential by means of a clamping circuit. 
   For all conceivable applications of the invention it holds equally true that the invention is directed to a method of operating a corresponding apparatus, circuit or the like, but also relates to an apparatus, circuit or the like itself. 
   As was already mentioned, the invention may be utilized advantageously for various fields of application. 
   First, inverters have to be mentioned, as are used for operating induction motors, also referred to as “asynchronous motors” with variable speed, in which a frequency-variable three-phase voltage is generated by switching power semiconductors on and off. 
   Another preferred field of application are ignition circuits for internal combustion engines as used in motor vehicles. In these circuits a pulsed output voltage for ignition purposes is generated from an input DC voltage by switching power transistors on and off. 
   Finally, the invention is generally applicable for so-called switched-mode power supplies which are standard component in various electrical and electronic apparatuses. In this connection an application for so-called power-factor-controllers (PFC) is also to be taken into account. Such PFCs are conventionally used as an input stage for switched-mode power supplies for drawing a strictly sinusoidal voltage and current, respectively, from the mains supply. Here, too, the invention may be used with considerable advantages. 
   Further advantages will become apparent from the description and the enclosed drawing. 
   It goes without saying that the afore-mentioned features and those that will be explained hereinafter may not only be used in the particularly given combination, but also in other combinations or alone without leaving the scope of the present invention. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1A through 1C  show simplified circuit diagrams for explaining the control of a power semiconductor according to the prior art; 
       FIG. 2A  shows a highly schematic circuit diagram of an embodiment of the invention, namely an apparatus for operating an induction motor at variable speeds; 
       FIG. 2B  shows a highly schematic circuit diagram of an embodiment of a switched-mode power supply arranged behind a power-factor-controller (PFC); 
       FIGS. 3A and 3B  show diagrams for explaining the time function of the collector emitter voltage dU CE /dt and the collector current dI C /dt during the switching-on ( FIG. 3A ) and during the switching-off ( FIG. 3B ) of a power semiconductor according to the prior art; 
       FIGS. 3C and 3D  show diagrams corresponding to those of  FIGS. 3A and 3B , however, for explaining the method according to the present invention; 
       FIG. 4  is a highly schematic block diagram of an embodiment of a driver according to the present invention, as may be used in a circuit according to  FIG. 2 ; 
       FIG. 5  is a circuit diagram of an embodiment of a sequence control as can be used in a driver as shown in  FIG. 4 ; 
       FIG. 6  is a block diagram of a circuit for controlling the time function of the collector emitter voltage dU CE /dt as may be used as a non-linear stage in the driver circuit of  FIG. 4 ; 
       FIG. 7  is a detailed circuit diagram of an embodiment of the control circuit of  FIG. 6 ; 
       FIG. 8  shows two equivalent circuits for explaining a linearizing process for a non-linear power semiconductor; 
       FIG. 9  is a detailed circuit diagram of an embodiment of a liearizing stage as may be used in the circuit of  FIG. 8 ; 
       FIG. 10  is a diagram, similar to that of  FIG. 6  and showing a circuit for controlling the time function of the collector current dI C /dt; 
       FIG. 11  is a detailed circuit diagram similar to that of  FIG. 7 , however for a control circuit as may be used in the circuit of  FIG. 10 ; 
       FIG. 12  is a wiring diagram for explaining potential malfunctions when switching two series-connected power semiconductors under inductive load; 
       FIG. 13  is a detailed circuit diagram for an embodiment of an output stage as may be used in the circuit of  FIG. 4 ; and 
       FIG. 14  is another circuit, similar to that of  FIG. 2A  showing a drive circuit for an IGBT. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1  on a highly schematic level shows a block diagram with a power semiconductor  1  which may be either an IGBT or a MOS-FET. A current I flows through power semiconductor  1  and a voltage U appears across the latter. For an IGBT, the input capacitance of the power semiconductor  1  corresponds to the gate-emitter capacitance C GE  in parallel to the effective feed-back capacitance C CG . The effective feedback capacitance C CG  is a function of the collector emitter voltage U CE . 
   For a MOS-FET the input capacitance of semiconductor  1  corresponds to the gate-source capacitance C GS . 
   Power semiconductor  1  is inputted via a network  2 , two prior art embodiments of which being shown in  FIGS. 1B and 1C . 
   Network  2  is controlled by an output stage  3  which, in turn, receives its signals from a micro-controller  4 . 
   Micro-controller  4  conventionally has a supply voltage of 5 V and outputs control signals at TTL-level. Output stage  3  has a supply voltage of conventionally 0/15 V or −5/15 V. The control signals from micro-controller  4  are processed within output stage  3  which generates switch-over signals switching between 0 V and 15 V or between −5 V and 15 V, respectively. 
   Network  2  is provided to avoid that power semiconductor  1  or its input capacitance C GE  or C GS , respectively, are not subjected to too high voltage jumps. In the simplest prior art case as shown in  FIG. 1B , network  2   a  solely consists of an Ohmic resistance R. In that case the input capacitance is slowly charged or discharged, respectively, via the R C -member consisting of resistance R and the capacitance. These events, therefore, are basically the same in the event of switching-on and in the event of switching-off power semiconductor  1 . 
   Considering that this prior art approach does not show sufficient precision, one has suggested the alternate network  2   b  of  FIG. 1C  in which two resistances R E  and R A  are switched in parallel, however, with a diode D being arranged in the path of resistance R o . Accordingly, during the switching-on of power semiconductor  1  only resistance R E  is active, whereas during switching-off the parallel circuit of R E  and R A  becomes effective. 
   Although in this prior proposal one has differentiated between the switching-on and the switching-off, this holds true only for one specific point of operation so that there are no optimum conditions when the operational conditions change. 
     FIG. 2A  shows a first embodiment of a circuitry  10  according to the present invention on a highly schematic level. Circuitry  10  shows an inverter as used for inverting a direct current voltage U 0  into a frequency-variable three-phase voltage. Circuitries  10  of the type shown are typically used for operating electric motors at variable speed. 
   Circuitry  10  comprises a DC terminal with a voltage U 0  supplying a DC line  12 . Analogously, reference numeral  13  designates a ground terminal being connected to a ground line  14 . 
   In the depicted embodiment, power semiconductors, more specifically power transistors  16   a ,  16   b  and  18   a ,  18   b  and  20   a ,  20   b , respectively, are switched in series and in pairs between DC line  12  and ground line  14 . Power transistors  16  through  20  may be of various types. Without restricting the scope of the present invention in any way, the following description shall be based mainly on the example of so-called insulated gate bipolar transistors (IGBTs). However, it goes without saying that also other types of power semiconductors may be used within the scope of the present invention, for example MOS-FETs (cf.  FIG. 2B ). 
   Between the IGBTs  16   a / 16   b ,  18   a / 18   b ,  20   a / 20   b , switched in series, terminals  22 ,  24  and  26  are arranged, the latter being connected to field windings of an electric motor, for example an induction motor, also referred to as “asynchronous motor”. In  FIG. 2A , these field windings are designated with u, v and w. 
   Further, all of the IGBTs are bridged by means of free wheeling diodes  28 . Any of the six IGBTs  16   a  through  20   b  are each connected to a driver  30  via their control terminal. Drivers  30 , in turn, are connected at their input with a micro-controller  32 , namely via a data line  34 . 
   In the upper left corner of  FIG. 2A  it is indicated that drivers  30  may further be subjected at their input to signals from special sensors and signal lines. These signals correspond to a voltage, preferably the collector emitter voltage U CS  and to a current, preferably the collector current I C . However, within the scope of the present invention one may also utilize other voltage or current signals of the power semiconductor (IGBT or MOS-FET, respectively). The afore-mentioned signals are evaluated and also partially transformed for that purpose, as will be described in further detail below. 
   Micro-controller  32  generates a switching signal by which the IGBTs  16   a  through  20   b  are brought into their operational conditions “ON” and “OFF”, respectively. 
   If in the scope of the present invention the term “switching” is used, this shall mean a switching operation within the power semiconductor (IGBT or MOS-FET, respectively), i.e. the change between the conditions “ON” and “OFF”. 
   The term “switching-over”, in contrast, shall relate to a process according to which within a switching process of the type specified before a transition is effected from a first internal control concept to a second internal control concept, as will be explained in further detail below. 
     FIG. 2B  shows another circuitry  36  on a highly schematical level. Circuitry  36  comprises a switched-mode power supply  37  arranged behind a so-called power-factor-controller (PFC)  38 . Circuitry  36  is used for converting a first DC voltage U E  into a second DC voltage U A . Circuitry  36  may, for example, be utilized within power supplies of television sets, computers and other electronic apparatuses, namely, for all applications where a constant output DC voltage shall be generated from a (constant or not constant) input DC voltage. 
   For that purpose circuitry  36  is provided with a first DC terminal  39 , carrying a first DC voltage U E , as well as with a second DC terminal  40 , carrying a second DC voltage U A . 
   PFC  38  comprises an inductance  42  connected to first DC terminal  39 . A diode  43  connects inductance  42  with switched-mode power supply  37 . A power transistor  34  is connected between an inductance  42  and diode  43  and is switched to ground. In the depicted embodiment power transistor  34  is a MOS-FET; as an alternative, an IGBT could also be used. MOS-RET  44  is controlled by a driver  45  which, in turn, is connected to a PFC control unit  46 . Behind diode  43 , a capacitor  47  is connected to ground. 
   The control within control unit  46  of PFC  38  is designed such that the current, drawn at first DC terminal  39  from first voltage U E  and switched by means of power transistor  44  is influenced such that its envelope has the shape of a sine half wave. This guarantees that power is drawn from the mains supply with a sine wave. 
   Switched-mode power supply  37  comprises a transformer  48  having a primary winding  48   a  being bridged by means of a diode  49  and being connected to ground via a power transistor  50 . Power transistor  50  is likewise controlled by a driver  51  which, in turn, is connected to a control unit, namely a DC/DC control unit  52 . DC/DC control unit  52  is, further, connected to second DC Terminal  40 . In the depicted embodiment power transistor  50  is also a MOS-FET, however, could alternately be an IGBT. The secondary winding  48   b  of transformer  48  is connected to second DC terminal  40  via a diode  53 . The latter is, further, connected to ground via a capacitor  54 . 
   As will be described in further detail below, MOS-FETs  44  and  50  (exactly like IGBTs  16  through  20  in  FIG. 2A ) are controlled such that they are switched according to the criteria described in detail in the introductory part of the description, when switched, i.e. when they change from the condition “ON” into the condition “OFF” or vice versa. In the circuit of  FIG. 2   b  this is effected by PFC control unit  46  for MOS-FET  44  and DC/DC control unit for MOS-FET  50 , in cooperation with driver  45  and driver  51 , respectively. 
   In contrast to conventional circuits, as explained in  FIG. 1 , a hard and uncontrolled switching is avoided which could occur when during the beginning of the switching operation the capacity input of the power semiconductor is subjected to a voltage jump of e.g. 0 to 15 V causing a spontaneous high current flowing into the input electrode of the power semiconductor. This, in turn, causes harmonics to be generated which, in turn, give rise to electromagnetic radiation. When motors are operated ( FIG. 2A ), displacement currents within the motor winding are generated. If, in contrast, the switching process would be slowed down, for example by means of the resistors shown in  FIGS. 1B and 1C , this would give rise to dissipated power losses. 
   The current and voltage curves according to the prior art on the one hand and as obtained with the present invention on the other hand, respectively, are depicted in  FIGS. 3A and 3B  (prior art) and in  FIGS. 3C and 3D  (present invention). 
     FIGS. 3A through 3C  show the uncontrolled and the controlled curves, respectively, of the collector-emitter-voltage U CE , the collector current I C , and the gate-emitter voltage U GE  of an IGBT, all versus time t. 
     FIG. 3A  shows the uncontrolled switching-on process of an IGBT and  FIG. 3B  shows the corresponding uncontrolled switching-off process. In contrast,  FIGS. 3C and 3D  show the controlled switching-on process and switching-off process, respectively, of an IGBT. 
   The term “time function” in the context of the present invention shall preferably, but not exclusively, mean the first derivative versus time of the respective quantity. Hereinafter, the first derivative is also identified as “edge steepness” or as “transient”. 
   Considering now the switching-on process according to  FIG. 2A  (prior art, uncontrolled) and  FIG. 2C  (invention, controlled), one can identify curve  60  in FIG.  2 A and  60 ′ in  FIG. 2C , respectively, as the principal curve of collector-emitter voltage U CE . Curves  61  and  61 ′, respectively, represent the principal curve of the gate-emitter voltage U GE . Finally, curves  62  and  62 ′, respectively, show the principal curve of the collector current I C , all versus time t. 
   The switching-on process of the IGBT is initiated at t 1  and t 1 ′, respectively. The curves  62  and  62 ′ for collector current I C  in both cases rise from a zero value up to an operational value of e.g. about 38 A. Within curves  62  and  62 ′ there is an overshoot  66  and  66 ′ at about t 2  and t 2 ′, respectively, being caused by charge carriers of over-flooded free-wheeling diode  28  (cf.  FIG. 2A ) for the inductive load that must first be removed. This effect occurs in all such diodes. 
   The inclination of gate-emitter voltage U GE  according to curves  61  and  61 ′ is positive for t&lt;t 2  and t′&lt;t 2 ′, respectively. There is a local maximum value at t 2  and t 2 ′. During overshoot  66  and  66 ′ free-wheeling diode  28  begins to receive inverse voltage. Collector-emitter voltage U CE  according to curves  60  and  60 ′ begins to drop from t 2  and t 2 ′, respectively, on, until it drops down to zero at t 3  and t 3 ′, respectively. 
   During this period of time, gate-emitter voltage U GE  according to curves  61  and  61 ′ remains almost constant. Already at t 1  and t 1 ′ curves  60  and  60 ′ show a sudden voltage drop  64  and  64 ′. Voltage drop  64  and  64 ′ occurs due to a parasitic inductance L P  ( FIG. 2A ) within the intermediate circuit U 0 . Voltage drop  64  and  64 ′, however, is only associated to a minor change vs. time dU CE /dt. 
   For the sequence controlled, i.e. for the control of collector-emitter voltage U CE  and of collector current I C  one now has to detect the proper moment in time t 2  and t 2 ′, respectively, and to use same for control purposes. 
   In  FIGS. 3A and 3C , respectively, I designates the period of time between t 1  or t 1 ′, respectively, and t 2  or t 2 ′, respectively, whereas II designates the period of time between t 2  or t 2 ′, respectively, and t 3  or t 3 ′, respectively. 
   According to the present invention, the time function of collector current I C , i.e. preferably the first derivative dI C /dt of collector current I C  shall be controlled during period of time I, whereas the time function of collector-emitter voltage U CE , preferably the first derivative dU CE /dt of collector-emitter voltage U CE  shall be controlled during period of time II. 
   Whereas the moments in time t 1  and t 3  or t 1 ′ and t 3 ′, respectively, may be determined by a simple comparison with the respective zero value, an appropriate criterion must be found for detecting t 2  when a switch-over between an I C  control and a U CE  control shall be effected. 
   Starting from the saturation voltage at t 4  or t 4 ′, respectively, i.e. at the beginning of a period of time III, collector-emitter voltage U CE  starts to rise. If the latter reaches the intermediate current voltage of e.g. 700 V, free-wheeling diode  28  begins to conduct and collector current I C  begins to drop. This is the switch-over moment in time t 5  or t 5 ′, respectively, at which a switch-over from the control of the time function of the voltage to the control of the time function of the current shall be effected. During the subsequent period of time IV collector-emitter voltage U CE  first rises due to the parasitic inductance L P  within intermediate circuit U 0 , as shown in  FIG. 3B  or  3 D, respectively, at  68  or  68 ′, respectively. Gate-emitter voltage U GE  first drops but then remains constant during the period of time III (the so-called “Miller-plateau”). During period of time IV it leaves the plateau and then drops further down to zero. 
   During the switching-off process the sequence control must properly detect t 5  of t 5 ′, respectively. 
   As already mentioned in the introductory portion of the description, one may start from the following criteria, either alternately or cumulatively, with regard to the switching-on process:
         a) current I C  or I D , respectively, reaches a maximum value;   b) the time function of current I C  or I D , respectively, drops by a predetermined amount;   c) voltage U CE  or U DE , respectively, drops by a predetermined amount, in particular when the first derivative of collector-emitter voltage dU CE /dt falls below a predetermined negative threshold value, or the absolute value of the first derivative of collector-emitter voltage |dU CE /dt| exceeds a predetermined positive threshold value;   d) the time function of voltage U CE  or U DS , respectively, drops by a predetermined amount;   e) the power semiconductor is an IGBT, and the gate-emitter voltage U GE  reaches a predetermined value;   f) the power semiconductor is an IGBT, and the time function of the gate-emitter voltage U GE  drops by a predetermined amount;   g) the power semiconductor is a MOS-FET, and the gate-source voltage U GS  reaches a predetermined value;   h) the power semiconductor is a MOS-FET, and the time function of the gate-source voltage U GS  drops by a predetermined amount.       

   In the case of a switching-off of the power semiconductor, the following criteria may be used analogously:
         a) voltage U CE  or U DS , respectively, reaches a maximum value;   b) the time function of voltage U CE  or U DS , respectively, drops by a predetermined amount;   c) current I C  or I D , respectively, drops by a predetermined amount;   d) the absolute value of the time function of current I C  or I D , respectively, drops by a predetermined amount, in particular when the first derivative of the collector-emitter voltage dU CE /dt falls below a predetermined negative threshold value, or the absolute value of the first derivative of collector-emitter voltage |dU CE /dt| exceeds a predetermined positive threshold value;   e) the power semiconductor is an IGBT, and the gate-emitter voltage U GE  reaches a predetermined value;   f) the power semiconductor is an IGBT, and, when the first derivative of the gate-emitter voltage dU GE /dt first assumes a negative value and, subsequently, a considerably smaller value and, finally, falls below a predetermined value, the moment in time of the falling below the predetermined value;   g) the power semiconductor is a MOS-FET and the gate-source voltage U GS  reaches a predetermined value;   h) the power semiconductor is a MOS-FET, and, when the first derivative of the gate-source voltage dU GS /dt first assumes a negative value and, subsequently, a considerably smaller value and, finally, falls below a predetermined value, the moment in time when it falls below the predetermined value.       

   As soon as one or more of the afore-mentioned criteria are fulfilled, depending on the particular case, the following steps are taken:
         during the switching-on of power semiconductor  1  or  16 ,  18 ,  20 , respectively, or  44 ,  50 , respectively, the time function of current I C  or I D , respectively, is controlled first and the time function of voltage U CE  or U DS , respectively, is controlled subsequently;   during the switching-off of power semiconductor  1  or  16 ,  18 ,  20 , respectively, or  44 ,  50 , respectively, the time function of voltage U CE  or U DS , respectively, is controlled first and the time function of current I C  or I D , respectively, is controlled subsequently.       

     FIG. 4  shows the basic structure of driver circuit  30 . 
   In the block diagram of  FIG. 4  reference numeral  70  designates a supply voltage module. Supply voltage module  70  is connected to a DC line  71 . 
   For controlling the time function, preferably the first derivative of collector-emitter voltage dU CE /dt a first differentiating stage  72  is provided. First differentiating stage  72  is fed at its input with a signal corresponding to collector-emitter voltage U CE . First differentiating stage  72  generates an actual signal, preferably as a current signal I ist . 
   Within the control circuit there is further provided a first desired value stage  74  in which a predetermined nominal or desired value for the time function collector-emitter voltage [dU CE /dt] may be set, likewise as current signal I soll . Within an electronic circuit this may be effected e.g. by means of a potentiometer or the like. 
   The output signals of first differentiating stage  72  and of first desired value stage  74  are fed to a first control stage  76 . First control stage  76  generates a difference signal I ist −I soll . The difference signal I ist −I soll  is fed to a non-linear stage NL, the output of which being likewise a current signal ΔI dU/dt . A signal corresponding to collector-emitter voltage U CE  is also fed to non-linear stage NL, as will be described further below. Non-linear stages NL are shown with further details in  FIGS. 6 and 10 . 
   Analogously a control circuit is provided for collector current I C . 
   A second differentiating stage  78  receives a signal corresponding to collector current I C  and generates its first derivative dI C /dt. 
   A corresponding nominal or desired value [dI C /dt] is generated in a second desired value stage. Both values are again fed to a second control stage  62  in which the difference signal I ist −I soll  is again transferred via a non-linear stage NL to the output as a current signal ΔI dI/dt . Further, also in this case a signal corresponding to collector current I C  is fed to non-linear stage NL. 
   A third differentiating stage  81  transforms input value U GE  into output value dU GE /dt. 
   Both output signals ΔI dU/dt  and ΔI dI/dt  are fed to a sequence control  84  effecting the switch-over for the controls, as described above in connection with  FIGS. 3A through 3D . Sequence control  84  comprises internal logics  84   a  generating switching signals for switches S 1  and S 2  according to the above-explained criteria for the switching process of the power semiconductors. In  FIG. 4  this is indicated with dashed lines within sequence control  84 . 
   Sequence control  84 , hence, comprises cross-over switch S 1  for activating either the dU CE /dt control or the dI C /dt control, as well as cross-over switch S 2  for the switching-on and the switching-off of the power semiconductor (IGBT). Sequence control  84 , further, comprises evaluation means for the physical conditions of the power semiconductor and of the operational state ON/OFF for controlling cross-over switches S 1  and S 2 , as well as a feedback in the event of a malfunction. 
   Sequence control  84  comprises a plurality of inputs for input signals U CE , I C  and U GE , the inputs being connected to blocks  72 ,  76 ,  78 ,  81  and  82 . Moreover, another input  83  is provided as well as outputs  85   a ,  85   b , and  85   c  being connected to inputs  87   a ,  87   b , and  87   c  of an output stage  88 . Within sequence control  84  the signals are guided essentially via cross-over switches S 1  and S 2 . 
   Within sequence control  84  cross-over switch S 1  switches either control signal ΔI dU/dt  for the time function of the voltage or control signal ΔI dI/dt  for the time function of the current (both being current signals) to cross-over switch S 2 . Cross-over switch S 2  feeds the control signal selected by cross-over switch S 1  either to output  85   a  or to output  85   b  of sequence control  84 . 
   Cross-over switch S 1  is actuated by logics  84   a  at t 2 ′ or t 5 ′, respectively. These moments in time are generated from the time functions of signals U CE , dU CE /dt, I C , dI C /dt, U GE  and dU GE /dt, as explained above, wherein these signals are directly fed to sequence control  84 , as may also be taken from  FIG. 4  where corresponding signal lines are clearly shown. 
   An interface  86  is connected to further input  83  of sequence control  84 . An input of interface  86  is connected to micro-controller  82  via a data line  34 . The output of output stage  88  is designated at  89 . The output of output stage  88  carries a control signal I C  for the power semiconductor, i.e. for the IGBT or the MOS-FET. 
   The depiction in  FIG. 4  is not to be understood to comprise all conceivable functions. Instead, further open-loop or close-loop control circuits may be provided. For example, one could provide a supply voltage control or a temperature control for driver  30 . Further, one might control collector-emitter voltage U CE  and/or collector current I C  with respect to e.g. maximum values I Cmax  or minimum values I Cmin . By doing so one could for example limit collector-emitter voltage U CE  to a maximum value U CEmax . Further, it would be possible in that way to limit collector current I C  to a maximum value I Cmax  in the event of a short circuit or to switch the IGBT entirely off when collector current I C  exceeds a predetermined threshold value I Cmax . 
   In that connection one could of course also generate indicator signals that could be processed via interface  86 . 
   Interface  86  could be connected to micro-controller  32  via opto-couplers in order to separate potentials. Interface  86  receives corresponding control signals from micro-controller  32  and generates signals for input  83  of sequence control  84  to control cross-over switch S 2  bringing the IGBT into the states “ON” or “OFF”. 
   In the context of the present invention sequence control  84  has various objects going far beyond the objects known from prior art. 
   According to the condition of micro-controller  32  sequence control  84  controls output stage  88  so that the latter supplies a positive or a negative current to the control terminal of the power semiconductor or the IGBT, respectively. Sequence control  84 , further, guarantees that the dU CE /dt control and the dI C /dt control are never operative simultaneously but that only the one or the other control is activated according to the prevailing time function or transient, instead. Therefore, the two controls can never affect each other. Any failure in collector current I C  during the dU CE /dt control or any failure of collector-emitter voltage U CE  during the dI C /dt control, respectively, are, therefore, effectively suppressed. The voltage transient and the current transient may, therefore, be controlled independently from one another. 
   Via output  85  sequence control  84  provides information to output stage  88  indicating the state (latched or unlatched) which output stage  88  shall assume. 
   Sequence control  84 , further, minimizes delay times, i.e. on the one hand the period of time between an order “ON” or “OFF”, respectively, from micro-controller  32  and the occurrence of the current or voltage transient, respectively, and, on the other hand, the period of time after the transients and the moment in time when the maximum or the minimum input voltage of the power transistor is reached. 
   As a matter of principle, sequence control  84 , finally, may automatically and in a controlled manner disconnect the power transistor or may supply an error signal to micro-controller  32  via interface  86  in the event that a short circuit or another malfunction occurs. 
   Within blocks  72 ,  74  and  76  the dU CE /dt control controls the voltage transient dU CE /dt to a value having been set by desired value [dU CE /dt]. The amount of desired value [dU CE /dt] may, as already mentioned, be set by means of a resistor. The desired value dU CE /dt is preferably detected by means of a capacitor. The capacitor is preferably connected with one terminal to the collector of the power transistor and with its other terminal to the low-impedance input of first differentiating stage  72  of driver circuit  30 . 
   Speaking in more exact terms, first control stage  76  operates as a limiter. During voltage transient dU CE /dt the power transistor is fed with a constant current, being set such that in the absence of a control the desired value would only be slightly exceeded, i.e. by e.g. about 10% to 20%. In the presence of the control transient dU CE /dt, however, it is limited to the set desired value. This control principle is highly advantageous because the transitions from the dU CE /dt control to the dI C /dt control may be configured easier and more steadily. 
   Another important feature of first control stage  76  consists in that an inverse correction circuit is utilized within the control circuit linearizing the non-linear transfer characteristics of the power transistor (cf. the description of  FIGS. 8 and 9  below). This results in an excellent control also at low collector-emitter voltage levels. Using the linearization is of particular importance for the present invention and may, hence, also be used without the remaining features of the invention. 
   For the dI C /dt within the blocks  78 ,  80  and  82  the same holds true, mutatis mutandis, that was explained before in connection with the dU CE /dt control within blocks  72 ,  74  and  76 . The desired value dI C /dt within second desired value stage  80  is likewise preferably set by means of a resistor. The detection of the desired value is preferably effected by means of a parasitic inductance. An additional current sensor could also be used, however, would not be required generally. 
   In contrast to the controls according to the prior art and further to the low-impedance output stage with two fixed voltages for the “ON” and the “OFF” state, respectively, output stage  88  is configured as a current controlled current output stage during the transient phases which may be latched according to the above-explained criteria. Here we also have an important aspect of the invention that may be used alone, i.e. without the remaining features of the invention. Using a current output stage during the switching process of the power transistors and a voltage output stage during the stationary state of the power transistors has several advantages: 
   First, the voltage transients and current transients depend on the input current and not on the input voltage of the power transistor, for example the IGBT. Therefore, no additional components are required between the output of driver  30  and the control input of the IGBT (cf above network  2  or  2   a , respectively, and  2   b  in  FIGS. 1A ,  1 B and  1 C). 
   Further, the stability of the controlled circuitry of driver  30  is essentially improved. 
   Furthermore one takes advantage of the fact that currents may generally processed much faster as compared to voltages. 
   Finally, by using a current output stage during the switching process and a voltage output stage in the absence of a switching process, one can avoid an erroneous switching of a power transistor that should be in a stationary state, when such power transistors are switched in series (cf. further below in connection to  FIG. 12 ). 
     FIG. 5  shows a detailed circuit diagram of an embodiment of cross-over switches S 1  and S 2  within sequence control  84  ( FIG. 4 ). 
   In the circuit of  FIG. 5  cross-over switch  51  is configured by transistors T 1  through T 6  having currents ΔI dU/dt  and ΔI dT/dt  being supplied by control stages  76  and  82 , respectively. The outputs of differential amplifiers T 3 /T 4  and T 5 /T 6  are connected with corresponding interleaving to two differential amplifiers T 7 /T 8  and T 9 /T 10  operating as switches and corresponding to cross-over switch S 2 . The switch voltage U on/off  for differential amplifiers T 7 /T 8  and T 9 /T 10  is generated by interface  86  and supplied to corresponding inputs  83   a  and  83   b . Voltage U on/off  switches currents I on  of I off  to outputs  85   a  and  85   b  towards final stage  88 . 
   Differential amplifiers T 3 /T 4  and T 5 /T 6  must be switched-over during the switching process in a fast and clean manner. They are controlled by another differential amplifier T 1 /T 2 , being switched by means of a voltage U schalt . Transistors T 1  and T 2  are commonly connected with their emitters to a current source I 0 . The collectors are connected with an input terminal U H2  via equally dimensioned resistors R 0 . Another input terminal U H1  is connected to the collector of transistor T 1  via a diode D 1 , as well as to the basis of transistors T 3  and T 6 . The collector of transistor T 2  is connected to the basis of transistors T 4  and T 5 . A voltage difference ΔU appears between the collectors of transistors T 1  and T 2 . 
   Let us disregard diode D 1  for a moment. At the beginning of the switching process U schalt  may, for example, be 1 V and output voltage ΔU at differential amplifier T 1 /T 2  be positive. When switching the IGBT on, current I dI/dt   will flow through transistors T 5  and T 7 . Accordingly, I on =I dI/dt . If now during the switching-on process ( FIG. 3C ) the moment in time t 2 ′ for switching-over is detected, voltage U schalt  is, e.g. switched to −1 V and, accordingly, I on =I dU/dt . During the switching-off process ( FIG. 3D ) we first have I off =I dU/dt  and, after the moment in time t 3 ′ for switching-over, we have I off =I dI/dt , so that a correct transition between the two controls has been effected. 
   Diode D 1  has the following function: 
   If the base potential of transistor T 1  is increased quickly, a parasitic error current will flow, caused by the parasitic capacitances through the collector transistor T 1 . In order to avoid that the potential change at this collector will not drop by more than 60 mV, voltage ΔU is clamped by means of D 1  and the applied voltages U H1  and U H2 , mentioned above. 
   We have, therefore, essentially three points, which are essential to obtain an optimum in the switching characteristics of cross-over switch S 1 : 
   First, it is important that the critical differential amplifier T 3 /T 4  and T 5 /T 6  are controlled differentially. Second, it is important that voltage ΔU be held as small as possible. is important that voltage ΔU be held as small as possible. Third, it is important to clamp voltage ΔU by means of diode D 1 . 
     FIG. 6  shows the control of the time function of collector-emitter voltage U CE  in further details, in particular its first derivative dU CE /dt. The elements shown in  FIG. 6  correspond to the non-linear circuitry NL within first control stage  76  of  FIG. 4 . 
   In  FIG. 6  one may see a subtracting stage  91  connected to two lines  90  and  92 . Line  90  carries an actual signal corresponding to the voltage transient dU CE /dt, whereas line  92  carries a desired signal corresponding to voltage transient dU CE /dt. 
   It is, therefore, possible to draw a difference signal at the output of subtracting stage  91  and, hence, via line  94 , corresponding to the difference between the actual value and the desired value. The difference signal is generated as a current signal I dU . 
   Difference signal I dU  is now fed via line  94  to a characteristic curve stage  96 . Characteristic curve stage  96  has a characteristic, according to which negative input values I DE  are transformed into a constant value of an output signal ΔI dU , whereas positive input values I dU  are transformed to an output value ΔI dU  falling down linearly to a zero value and remaining at that zero value. 
   The output signal ΔI dU  mentioned before is transferred from characteristic curve stage  96  to a dividing stage  106  via a line  98 . 
   For otherwise controlling dividing stage  106  a signal corresponding to the collector-emitter voltage U CE  is fed via a line  100  and is supplied to a linearizing stage  102 . In the embodiment shown the linearizing stage  102  has a parabolic characteristic curve symmetric to the abscissa. Accordingly, the input variable quantity U CE  is transformed into a degressively decreasing output variable quantity ΔI UCE . The output variable quantity ΔI UCE  is fed to dividing stage  106  via a line  104 , as a second input variable quantity. 
   Within dividing stage  106 , therefore, the output signal ΔI dU/dt  is generated and outputted to a line  108 , and further on fed to sequence control  84  ( FIG. 4 ). Blocks  96 ,  102  and  106 , therefore, together configurate the non-linear stage NL of first control stage  76  of  FIG. 4 . 
   The control principle of the circuit shown in  FIG. 6  is as follows: 
   The desired value signal appearing on line  92  is subtracted from the actual value signal on line  90  by means of subtracting stage  91 . If the resulting difference is positive, the output signal ΔI dU  at the output of characteristic curve stage  96  decreases. Accordingly, ΔI dU/dt  at the output of dividing stage  106  is likewise decreased. Therefore, gate current I G  of the IGBT is also reduced to the required value. 
   The controller, therefore, operates as a limiter. This control principle has the advantage that during the transition between the dU CE /dt control and the dI C /dt control, and vice versa, the two control principles do not interfere. 
     FIG. 7  shows a detailed circuit diagram for the block diagram of  FIG. 6 . 
   Input voltage U CE  generates a current through a capacitor C U  being proportional to the first derivative dU CE /dt, i.e. to the voltage transient. During the switching-off process this current flows from capacitor C U  via a diode D 3  to ground. During the switching-on process, however, the current flows from capacitor C U  via a transistor T 12a  which, together with a transistor T 12b  and the afore-mentioned diode D 3  configurates a rectifier. For the actual current signal we have:
 
 I   ist   =C   u   ·|dU   CE   /dt|. 
 
   This current I ist  is now compared with the desired value current signal I soll . If current I ist  in its absolute value is higher than current I soll , the difference flows through diode D 2  and reduces the mother current I 0  which is fed to the circuitry of  FIG. 7  from supply voltage U s . 
   In  FIG. 7 , one may further see that the current signal ΔI dU  may be taken from the collector of a transistor T 11 , the emitter of which being connected to diode D 2 . 
     FIG. 8  shows an equivalent circuit for principally explaining the function of linearizing stage  102  ( FIG. 6 ). The block shown in  FIG. 8  and having terminals  98  and  111  corresponds to the blocks  102  and  106  in  FIG. 6 .  FIG. 9 , insofar, shows a circuit diagram for an embodiment of such a linearizing stage  102  together with dividing stage  106 . 
   In  FIG. 13  reference numerals  110 ,  111  and  112  indicate the collector-, the gate- and the emitter-terminals of an IGBT  114 . 
   Whereas the left side of  FIG. 8  shows the circuitry of IGBT  114  with linearizing stage  102 , dividing stage  106  and output stage  88 , the right side of  FIG. 7  shows an equivalent circuit of the left side in which like elements are designated with like reference numerals, however, with the addition of an apostrophe. 
   During the voltage transient dU CE /dt the gate-voltage at IGBT  114  remains constant. In the prior art this effect is identified as “Miller-plateau”. The entire input current I G  then flows away via capacitor C CG  and determines the voltage transient dU CE /dt. Capacitance C CG  is essentially composed from a barrier capacitance and, hence, depends on the collector-emitter voltage U CE . The following equation applies: 
   
     
       
         
           
             
               ⅆ 
               
                 U 
                 CE 
               
             
             / 
             
               ⅆ 
               t 
             
           
           = 
           
             
               
                 I 
                 G 
               
               
                 C 
                 CG 
               
             
             = 
             
               k 
               · 
               
                 
                   U 
                   CE 
                 
               
               · 
               
                 I 
                 G 
               
             
           
         
       
     
   
   The factor k depends on the type of power transistor used, however, it is relatively independent (&lt;10%) of the temperature and the variation of properties between individual transistors. The voltage transient dU CE /dt depends on the magnitude of input current I G  and not on the input voltage. This, too, is a reason why in contrast to controls according to the prior art in which a voltage source is provided at the output of the driver, the control according to the present invention uses a current output stage  88 . 
   Linearizing stage  102  together with differentiating stage  106  comprise a non-linear circuit. The latter requires the magnitude of the collector-emitter voltage U CE  and is subjected to the transfer function:
 
 dI   dU/dt   ˜ΔI   dU   /√{square root over (U     CE     )} 
 
   As already mentioned, the left side of  FIG. 8  shows the IGBT  114  with separate linearization, whereas the right side shows an IGBT′ modified by linearization, as an equivalent circuit diagram. Modified IGBT  114 ′ has a constant collector-gate capacitance C CG ′. In view of this capacitance C CG ′ a constant dU CE /dt is obtained when the gate-current I G ′ is likewise constant. 
   The non-linear circuit for linearizing stage  102  as well as the differentiating stage  106  are preferably configurated according to the so-called “translinear principle” described by Gilbert. Further details may be found in an article from Gilbert, Barrie, “Translinear circuits: An historical overview”, Boston, Mass., 1996, pages 95 through 118, as well in U.S. Pat. No. 6,104,244 A1. 
   When utilizing the translinear principle, one has the advantage that the required transfer properties are obtained with a minimum number of components and without using feedbacks (stability safety) and by only processing currents (high cut-off frequency). 
   The circuit diagram of  FIG. 9  shows a transistor T 13  being connected with its collector to a supply voltage U s . The emitter of transistor T 13  is connected to a current source through which a mother current I 0  flows and which, in turn, is connected to ground. The base-emitter path of transistor T 13  is bridged by the collector base path of a transistor T 14  being cascaded towards ground via another transistor T 15 . Still another transistor T 16  has its collector connected to supply voltage U s  and having its emitter supplied with a signal (current  119 ) corresponding to the collector-emitter voltage U CE . The base of transistor T 16  is connected to the base of transistor T 13 , the node between these bases, in turn, being connected to line  98 . 
   A line interconnects the emitter of transistor T 16  with the base of transistor T 17 , the collector of which being connected to supply voltage U s , whereas its emitter is connected to line  108  via a cascaded transistor T 18 . The bases of transistors T 15  and T 10  are interconnected. They are on a potential U 0  above ground. 
   The circuit shown in  FIG. 9  is designed according to the translinear principle. The input current ΔI dU  is equal to the sum of the currents into the bases of transistors T 13  and T 14  and the collector current of transistor T 4 . Mother current I 0  be assumed as being constant. The current  119 , as already mentioned, must be considered to be proportional to collector-emitter voltage U CE  of the IGBT. 
   When making the tour around the base-emitter voltages of the six identical transistors T 13  through T 18  and if the base currents are neglected, the following equation is obtained:
 
 dI   dU/dt   ˜√{square root over (I     0     ·)}Δ   I   dU   /√{square root over (U     CE     )} 
 
   Practice has shown that the deviations from the desired control may be brought down to a value of below 10% also for very low collector-emitter voltages U CE  when the non-linear circuit of  FIG. 9  is used. 
     FIG. 10  in a depiction very similar to that of  FIG. 6  shows the principle for a control of the collector current I C . 
   In that case, too, a subtracting stage  121  is supplied with an actual value via a line  120  and with a desired value via a line  122 . At the output of a subtracting stage  121  we have a difference signal configured as a current signal I dI  on a line  124 . The difference signal is fed to a characteristic curve stage  126 . 
   In contrast to the characteristic curve of characteristic curve stage  96  in  FIG. 6 , the characteristic curve in the characteristic curve stage  126  of  FIG. 10  is configured such that for positive values of input signal I dI  the output signal ΔI dT  drops from a constant value down to zero but then, further, drops beyond zero down to further negative values. 
   Output signal ΔI dI  appears on a line  128  connected to a dividing stage  136 . 
   A signal corresponding to collector current I C  is fed to a linearizing stage  132  via a line  130 . Here we have a portion of the linearizing stage that had been designated by NL within the second control stage  82  of  FIG. 4 . The characteristic curve within linearizing stage  132  is different from the characteristic curve within linearizing stage  102  of  FIG. 6  because it is parabolic and opening downwardly. 
   A current signal ΔI IC  appears at the output of linearizing stage  132  and is likewise fed to dividing stage  136 . The control signal ΔI dI/dt  appears at its output, i.e. on a line  138 . 
   The principle of control according to  FIG. 10  corresponds to the principle of control according to  FIG. 6 . 
   Detection of the actual value for collector current I C  (c.f. block  78  in  FIG. 4 ) may preferably be effected by means of a parasitic inductance L P  (being designated by L E1  in  FIG. 14  further below). 
   The non-linear properties of the IGBT in the current transient dI C /dt during the switching-on and the switching-off process may be described as follows:
 
 dI   C   /dt˜√{square root over (I     C     )}·   I   G 
 
   Analogously to the dU CE /dt control stages  132  and  136  are used, the transfer function of which having an identical structure. It is mandatory that:
 
Δ I   dI/dt   ˜ΔI   dt   /√{square root over (I     C     )} 
 
   The non-linear circuit for that transfer function should likewise be realized according to the above-mentioned translinear principle according to Gilbert. 
   Experimental results have shown that when the dI C /dt control is used, the excess voltage during the switching-off process, being composed from the product of dI C /dt and the entire parasitic inductance within the intermediate circuit, may be reduced from 30% to less than 5%. Therefore, an additional functional block effecting an excess voltage limitation is not necessary in these cases. 
     FIG. 11  shows a practical partial embodiment of the structure shown in  FIG. 10  (cf. the practical embodiment of  FIG. 7  for the control structure of  FIG. 6 ). 
   In the circuit of  FIG. 11  the voltage drop at the parasitic inductance is detected at the terminals indicated with ( 2 ) and ( 7 ) in  FIG. 14 . Terminal ( 2 ) is shown in  FIG. 11 . The voltage drop is converted into a current by means of a resistor R I  which, when the voltage is positive, is converted via transistors T 21  and T 22  as well as via a diode D 6 , whereas for a negative voltage it is converted via a transistor T 20  into a current I ist . The current I soll  is subtracted therefrom. When the current difference is above zero, it flows at the node of the circuit, corresponding to subtracting stage  121 , further via diode D 5  and reduces mother current I 0  and, consequently, current ΔI dI  which, via a line  124 , is transferred to dividing stage  136 . 
     FIG. 12  illustrates that a problem may occur when two power transistors are connected in series and an inductive load L is applied to the center terminal between the two power semiconductors. 
   In the circuit of  FIG. 12  it be assumed that the lower power semiconductor be controlled at its input by a current source SQ 1  which may correspond to a current output stage. In that event a current flows via capacitance C CG  between the collector and the gate of this power semiconductor with the consequence that a voltage rise dU/dt appears at the terminal of the inductive load L. This voltage rise dU/dt may become effective with respect to the capacitance C GE  between the gate and the emitter of the upper power semiconductor provided that the latter is also controlled from a current source SQ 2 . This is because an undesired switching may be effected with the upper power semiconductor that should be in a non-switching stationary state. 
   In order to avoid this undesired effect, the present invention provides for an output stage which only acts as a current output stage during the switching process, i.e. in the course of the transient, whereas it acts as a voltage output stage in the absence of a switching process. 
     FIG. 13  shows a practical embodiment of a current output stage  88 . 
   In contrast to output stages of the prior art with low-impedance output, the power output stage  88  according to the invention has the essential advantage that the stability of the control circuit is increased and that additional component (cf.  FIGS. 1B and 1C ) between the output of driver  30  and the control terminal of the power transistor may be deleted. 
   In the embodiment of  FIG. 13  an output stage  88  is shown having a current amplification of between 15 and 20. Output stage  88  comprises current inputs I on  and I off  according to the inputs  87   a  and  87   b  of output stage  88  from  FIG. 4 . Further, it comprises a current output I G  corresponding to the output  89  in  FIG. 4 . 
   Within the circuitry of  FIG. 13  transistors T 23  through T 26  as well as T 32  through T 35  operate as a so-called “Widlar” current source. In order to obtain an acceptable compromise between cut-off frequency and linearity, not more than three output transistors should be used in a current mirror. The resistance ratio R 1 /R 2  and R 3 /R 4  should not exceed 6. In order to eliminate the Miller-effect, transistors T 27  and T 31  are superimposed to output stage transistors T 24  through T 26  and T 33  through T 35 , respectively, in a common-base circuit. Diodes D 7  through D 10  prevent that transistors T 27  through T 31  are saturated. 
   The cut-off frequency of output stage  88  may be increased for the switching-on process of the IGBT, by deleting transistor T 26  and corresponding resistor R 2 . The overall amplification of output stage  88  may then be corrected via the resistance ratio R 5 /R 6 . The critical point, however, is that the dissipated power of transistor T 28  may quickly exceed the allowed limit. 
   Finally,  FIG. 14  shows a further practical embodiment of an inventive arrangement shown as a block diagram. 
   One can see driver  30 ′ corresponding essentially to driver  30  according to the preceding description. As a consequence, it comprises a first control stage  76 ′, a second control stage  82 ′, a sequence control  84 ′ as well as an output stage  88 ′. 
     FIG. 14 , further, illustrates how the various open-loop and close-loop control stages  76 ′ and  82 ′ obtain their respective input signals. For example, first control stage  76 ′ is connected via a capacity C U  to the emitter of two IGBTs integrated into a common IGBT module  140 , such that the capacity C U  generates a derivative in time of the collector-emitter voltage U CE  to which it is exposed. Voltage U CE  itself is fed to control stage  76 ′ via a resistor R U . 
   In a corresponding manner, second control stage  82 ′ receives its input signal via a resistor R I  being connected to the emitter of the lower IGBT. 
   A typical application of IGBT module  140  is in connection with an inverter for a motor control. It comprises at least two IGBTs switched as a half bridge or six such IGBTs with corresponding free-wheeling diodes as a full bridge. Besides the three main terminals “intermediate circuit” (terminal  3 ), “motor” (terminal  1 ) and “ground” (terminal  2 ) there are four terminals (terminals  4  through  7 ) for connecting the two required drivers. The voltages U LE1  and U LE2  that can be detected at the prevailing emitter ( 1  or  2 ) and auxiliary emitter ( 5  or  7 ) are proportional to the derivative of the collector current and are utilized for detecting the actual value. These signals may, therefore, be utilized as input signals for the circuit of  FIG. 11 , for example. Within the drive circuit the voltages U LE1  and U LE2  are directly converted into the current I ist  at the input. 
   The circuitry of driver  30  needs to be supplied only with one positive voltage source. The negative supply voltage may be realized by means of switched capacitors. Therefore, one would connect the high-side driver according to the bootstrap method in order to avoid high voltage technology. This procedure belongs to the prior art of voltage supply for high-side drivers within inverters and, hence, need not be explained again in the present context.