Abstract:
A differential amplifier and method including a differential pair of input MOS transistors coupled to a common tail current source and a pair of MOS load transistors, with the amplifier outputs being disposed intermediate the input and load transistors. Biasing circuitry is included to maintain the load transistors in the linear region of operation. Reset transistors can be used to periodically reset the amplifier by connecting the outputs directly to the inputs.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to differential amplifiers and in particular to FET differential amplifiers capable of providing good performance at reduced supply voltages. 
     DESCRIPTION OF RELATED ART 
     Many data conversion circuits, including Analog-To-Digital Converters and Digital-To-Analog Converters, operate utilizing comparator circuitry which includes fully differential amplifiers. FIG. 1 is a diagram of a conventional fully differential comparator circuit which provides a comparator output Out indicative of the relative magnitude of an analog input having a positive component IN+ and a negative component IN− and a reference having a positive component REF+ and a negative component REF−. 
     The FIG. 1 comparator circuit including two fully differential amplifiers A 1  and A 2  which drive a regenerative latch circuit B 1 . FIGS. 2A,  2 B,  2 C,  2 D and  2 E are timing diagrams of timing signals Clk, R, I, M and C, respectively, for controlling operation of the FIG. 1 comparator circuit. When signal Clk is high, timing signal R (FIG. 2B) is active so that the switches associated with signal R will be turned on. This will cause the inverting input and the non-inverting input of each amplifier A 1  and A 2  to be connected directly to the non-Attorney inverting and inverting output, respectively, of each amplifier. This causes the closed loop gain of amplifiers A 1  and A 2  to be unity, with the amplifier inputs (and outputs) being at the threshold voltage of each amplifier. In addition, signal R will short the inputs of latch circuit B 1  together. 
     Timing signal I (FIG. 2C) is also active when Clk is high so that the negative component of the differential analog signal being compared, IN−, is coupled to input capacitor C 1  and the positive component IN+ is coupled to input capacitor C 2 . At this point, capacitors C 1  and C 2  have a stored voltage that corresponds to the magnitude of the analog inputs IN− and IN+. Capacitors C 3  and C 4  will have a stored voltage that corresponds to the magnitude of the difference between threshold voltages of amplifiers A 1  and A 2 . 
     When clock Clk goes low, signals R and I go inactive followed by signal M going active. Among other things, this causes the switches shorting the amplifier inputs to the outputs to open. The amplifiers A 1  and A 2  are thus operating open loop. In addition, input capacitor C 1  is coupled to reference voltage Ref− and input capacitor C 2  is coupled to reference voltage component Ref+. Thus, the change in voltage at the inverting input of amplifier A 1  will be the difference between the magnitude of reference voltage Ref− and input IN− and the change in voltage at the non-inverting input will be the difference in magnitude of reference voltage Ref+ and IN+. 
     The differences will be amplified by amplifier A 1 , with the output being proportional to the difference between input IN+/IN− and Ref+/Ref−. Amplifier A 2  functions to amplify the difference voltage further. Finally, just as clock Clk goes high, and before signals R and I become active again, signal C goes active thereby latching the difference voltage presented at the inputs of the latch circuit B 1 . The digital output of latch circuit B 1  will be either a “1”, or a “0” depending upon the relative magnitudes of IN+/IN− and Ref+/Ref−. 
     The gain of the differential amplifiers A 1  and A 2  are each typically 5-20. The gain of these cascaded amplifiers operate to reduce the input-referred offset voltage arising from the device mismatch in regenerative latch circuit B 1 . FIG. 3 shows a typical implementation of a prior art differential amplifier together with the NMOS reset switches which connect the inputs and outputs together. The amplifier circuit includes differential input NMOS transistors  12 A and  12 B connected to a tail current source which includes NMOS transistor  10 . Diode-connected PMOS transistors  14 A and  14 B form the load circuit, with NMOS transistors  16 A and  16 B forming the reset switches. 
     The open-loop gain of the FIG. 3 amplifier is approximately equal to the ratio of the transconductance (gm) of the NMOS input transistors  12 A/ 12 B to the transconductance of the PMOS load transistors. Thus, the gain can be expressed as follows: 
      G=gm I/gm   L   (1) 
     where G is the amplifier gain, gm I  is the transconductance of the input transistors  12 A/ 12 B and gm L  is the transconductance of the load transistors  14 A/ 14 B. 
     Since transistors  12 A/ 12 B and  14 A/ 14 B all operate in the saturation region, the transconductance of these transistors can be expressed as follows: 
     
       
         gm=2I DS /(V GS −V t )  (2) 
       
     
     where I DS  is the drain-source current, V GS  is the gate-source voltage and V t  is the transistor threshold voltage. 
     Combining equations (1) and (2), the amplifier gain can be expressed as follows: 
     
       
         G =(V GSL −V tL )/(V GSI −V tI )  (3) 
       
     
     where V GSL  and V GSI  are the gate-source voltage of transistors  14 A/ 14 B and  12 A/ 12 B, respectively, and v tL  and V tI  are the threshold voltages of transistors  14 A/ 14 B and  12 A/ 12 B, respectively. 
     The numerator and denominator of equation (3) are each sometimes referred to as the gate drive voltage, that is, the degree to which the gate-source voltage exceeds the threshold voltage. The gain G can be considered to be approximately equal to the ratio of the gate drive voltage of the load transistors  14 A/ 14 B to the gate drive voltage of the input transistors  12 A/ 12 B. 
     In a typical configuration, the gate drive voltage of the input transistors  12 A and  12 B has a practical minimum value of 150-200 mV in order to preserve a reasonable input capacitance. The maximum gate drive of the load transistors  14 A and  14 B is limited by the magnitude of the supply voltage VDD. A supply voltage VDD of +5 volts typically supports a gain of about 7-10 for the FIG. 3 circuit. 
     For CMOS processes where the magnitude of the threshold voltage Vt for the NMOS and PMOS transistors is about 0.75 volts, the FIG. 3 amplifier topology is unsuitable for operation at significantly lower supply voltages VDD, such as +2.7 volts. There is a need for an amplifier design that is suitable for comparator circuit and other applications capable of operating at reduced supply voltages. As will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings, the present invention addresses this shortcoming of the prior art by providing an amplifier capable of good performance at reduced supply voltages. 
     SUMMARY OF THE INVENTION 
     A differential amplifier and related method are disclosed. The amplifier includes first and second MOS transistors, typically NMOS transistors, having their respective sources coupled to a tail current source. The gates of the first and second MOS transistors function as the differential input to the amplifier. 
     Third and fourth MOS transistors, typically PMOS transistors, are connected as loads, with the third load transistor and the first input transistor having their respective drain-source paths connected in series to form a first current path and with the fourth load transistor and the second input transistor having their respective drain-source paths connected in series to form a second current path. Biasing circuitry is provided to cause the load transistors to operate in the linear region of operation as opposed to the saturation region of operation. This feature increases the gain of the amplifier at low voltage operation. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a conventional multistage offset cancelling comparator circuit of the type suitable for incorporating amplifiers in accordance with the present invention. 
     FIGS. 2A-2E are timing diagrams for the various signals used to control the operation of the FIG. 1 comparator circuit. 
     FIG. 3 is a circuit diagram of a conventional amplifier used on the FIG. 1 comparator circuit. 
     FIG. 4 is a circuit diagram of a first embodiment of an amplifier in accordance with the present invention. 
     FIG. 5 is a circuit diagram of a second embodiment of an amplifier in accordance with the present invention. 
     FIG. 6 is a circuit diagram of a third embodiment of an amplifier in accordance with the present invention. 
     FIG. 7 is a circuit diagram of a fourth embodiment of an amplifier in accordance with the present invention. 
     FIG. 8 is a circuit diagram of a fifth embodiment of an amplifier in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring again to the Drawings, FIG. 4 depicts an amplifier in accordance with one embodiment of the present invention. It should be noted that the terms MOS, PMOS and NMOS are intended to encompass, in the present application, all types of field effect transistors (FETs) as opposed to bipolar transistors. By way of example, a PMOS transistor would include all types of PFETs including PMOS and PJFET devices. The amplifier includes NMOS transistors  20 A and  20 B which form a differential pair, having common source connections to a tail current source comprising transistor  18  which produces an output current I. The load transistors  22 A and  22 B are PMOS devices having their gates connected to a common bias voltage BIAS 2 . The load transistors  22 A and  22 B are biased to operate in the linear region rather than the saturation region. 
     The gain of the FIG. 4 circuit can be expressed as follows: 
     
       
         G=gm I /gds L   (4) 
       
     
     where gm I  is the transconductance of input transistors  20 A/ 20 B and gds L  is the drain-source conductance of the load transistors  22 A/ 22 B operating in the linear region. 
     Assuming that the load transistors  22 A/ 22 B are operating well within the linear region, gds L  can be approximated as the drain-source current I DS  divided by the drain-source voltage V DS . Setting gds L  equal to I DSL /V DSL  in equation (4) and setting gm I  equal to 2I DSI /(V GSI −V tI ), and assuming that I DSL  and I DSI  are equal, the gain of the FIG. 4 amplifier can be expressed as follows: 
     
       
         G=2V DSL /(V GSI −V tI )  (5) 
       
     
     Comparing the gain expression of equation (5) of the present invention with equation (3) of the prior art amplifier, it can be seen that a gain comparable or higher that the prior art amplifier can be achieved at a much lower supply voltage. This improvement is attributable to the factor of 2 in the gain as shown in equation (5). It is also attributable to the fact that the threshold voltage of the PMOS load transistors  22 A and  22 B does not reduce the headroom as it does in the FIG. 3 circuit. 
     Note that the reset switches  24 A and  24 B of the FIG. 4 amplifier are PMOS devices as opposed to the NMOS devices used in the prior art circuit of FIG.  3 . Thus, the control signals R bar must be of the opposite polarity. PMOS switches are used because the drain-source voltage V DS  of the load transistors  22 A and  22 B must be kept relatively low to maintain the transistors well inside the linear region. Typically, the drains of transistors  22 A and  22 B must be fairly close to the supply voltage VDD, about 0.5 volts, thereby requiring the reset switches  24 A and  24 B to be PMOS devices. 
     The circuitry for producing bias voltage BIAS 2  for biasing the load transistors  22 A and  22 B in the linear region includes a PMOS transistor  30  which is matched to transistors  22 A and  22 B. A transistor  26 , having a channel width to length ratio W/L one-half that of transistor  18 , has a gate connected to the same bias voltage, BIAS 1 , that is connected to the gate of tail current source transistor  18 . Thus, transistor  26  will conduct one-half the current of transistor  18  and transistor  30  will conduct the same current as transistors  22 A and  22 B. A diode-connected PMOS transistor  28  is connected between the gate and drain of transistor  30  and reduces the drain-source voltage of transistor  30  thereby forcing transistor  30  to operate in the linear region. When transistor  28  is sized correctly and assuming that the differential input voltage is zero, transistors  30 ,  22 A and  22 B will remain in the linear region and have approximately the same drain-source voltage over process, supply voltage variations and temperature variations so that the gain will remain well controlled. 
     FIG. 5 illustrates one possible enhancement to the FIG. 4 amplifier. The channel widths of the PMOS load transistors  22 A and  22 B are reduced by ½ so that the drain-source current I DSL  will be reduced by the same amount. Current sources  32 A and  32 B are connected in parallel with the load transistors so that the original current level I DS  /2 is maintained in the input transistors  20 A and  20 B, namely, one-half of the I DS  of transistor  18 . The tail current source which includes transistor  18  will continue to produce a current I. Thus, setting gds L  equal to I/4V DSL  in equation (4) and setting gm I  equal to I/(V GSI −V tI ) the gain of the FIG. 5 amplifier can be expressed as follows: 
     
       
         G=4V DSL /(V GSI −V tI )  (6) 
       
     
     As can be seen by comparing equations (5) and (6), the gain G has doubled. Gain increases other than by 2 can be achieved by reducing the size of the PMOS transistors  22 A and  22 B and the magnitude of I DSL  by amounts other than a factor of 2. 
     One drawback to the use of PMOS reset transistors  24 A and  24 B of FIGS. 4 and 5 is due to the fact that PMOS transistors inject approximately 3 to 4 times more charge when they are opened as compared to NMOS transistors since the PMOS transistors must be approximately 3 to 4 times as large as the NMOS transistors in order to produce the same on resistance. FIG. 6 is an enhancement of the FIG. 5 circuit which addresses this drawback. Diode connected NMOS transistors  36 A and  36 B are connected in series with the load transistors  22 A and  22 B. This reduces the common-mode input and output voltages of the amplifier from about 0.5 volts below supply VDD to about VDD/2. At this reduced voltage, it is possible to use NMOS transistors  34 A and  34 B as the reset switches rather than PMOS devices. 
     Centering the common-mode input and output voltages provides a further advantage over the amplifiers of FIGS. 4 and 5. When the comparator circuit, such as shown in FIG. 1, is driven by a differential input (IN+ and IN−) which is significantly different from the differential reference voltage (Ref+ and Ref−), the amplifier inputs will be driven widely apart. If the common-mode voltage is near the supply voltage, as is the case of the FIGS. 4 and 5 amplifiers, one of the amplifier inputs will be boosted well above the supply voltage VDD. This could potentially cause the drain of the PMOS reset transistors  24 A and  24 B of the FIGS. 4 and 5 circuits to become forward biased relative to the n-well in which the drains are disposed. Centering the common-mode input voltage between supply VDD and ground provides the maximum allowable swing (in both directions) for the amplifier inputs. 
     The diode-connected NMOS transistors  36 A and  36 B reduce the headroom available for the NMOS differential pair  20 A and  20 B and tail current source transistor  18 . By minimizing the voltage drop across the diode-connected NMOS transistors  36 A and  36 B through the use of large ratio of channel width to length, robust operation can be achieved over process and temperature corners for a minimum supply voltage V DD  as low as +2.7 volts. 
     FIG. 7 depicts an enhancement of the amplifier circuit of FIG.  6 . Diode-connected NMOS transistors  38 A and  38 B are connected in parallel with load transistors  22 A and  22 B. Transistors  38 A and  38 B act as clamps to reduce the maximum output voltage swing thereby decreasing the time needed to reset the amplifier and limiting the signal amplitude presented to the next element in the signal path. NMOS clamps are used because their parasitic capacitance is about three to four times lower compared to PMOS clamps with the same clamp resistance. Simulation has verified that clamp transistors  38 A and  38 B remain off until a very large differential output voltage is developed. 
     A still further embodiment of the subject invention is shown in FIG.  8 . Each output of the internal differential amplifier stage drives a source follower stage, with one stage including output transistor  42 A connected to a current source transistor  44 A and the second stage including output transistor  42 B connected to a current source transistor  44 B. The source follower output buffers increase the open loop bandwidth of the amplifier by about 30%. The currents and device widths of the basic amplifier circuit have been scaled by 50%. Thus, an increase in bandwidth is achieved without an increase in power consumption as compared to the FIG. 7 circuit. 
     Note that the reset transistors  34 A and  34 B are no longer connected directly between the output and the input of the FIG. 8 circuit. If the switches were connected directly between the inputs and outputs, there would be excessive loop delay during reset, resulting in instability. Note also that the equal sharing of current between the input and output stages of the FIG. 8 circuit approximately optimizes the tradeoff between resetting speed, which is determined by the input stage current, and open loop bandwidth, which is predominately determined by the output stage current. Thus, the FIG. 8 amplifier combines improved open-loop bandwidth with all of the advantages previously noted with respect to the amplifiers of FIGS. 3-7, including a well controlled gain at low voltage, NMOS reset switches, a mid-supply common-mode input voltage and output swing clamps. 
     In conclusion, various embodiments of an improved differential amplifier have been disclosed. Although these embodiments have been described in some detail, it is to be understood that certain changes can be made by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.