Abstract:
A servo controller for an embedded disk controller comprises a read channel interface that includes a programmable control logic that receives a servo field detected signal from a module that detects a servo field start bit. A memory in the read channel interface is enabled by the programmable control logic for receiving servo field data from a read channel device, wherein the programmable control logic is configured to operate in a first mode and a second mode allowing the servo controller to process servo data from the read channel device. The servo controller processes the servo data using first and second data widths during the first and second modes, respectively.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation of U.S. patent application Ser. No. 10/385,405, filed on Mar. 10, 2003, and related to the following U.S. patent applications: U.S. patent application Ser. No. 10/384,991, filed Mar. 10, 2003; U.S. patent application Ser. No. 10/385,022, filed Mar. 11, 2003 (now U.S. Pat. No. 6,936,649, issued Aug. 30, 2005); U.S. patent application Ser. No. 10/385,042, filed Mar. 10, 2003; U.S. patent application Ser. No. 10/385,056, filed Mar. 10, 2003; U.S. patent application Ser. No. 10/385,992, filed Mar. 10, 2003; and U.S. patent application Ser. No. 10/385,039, filed Mar. 10, 2003. The disclosures of the above applications are incorporated herein by reference. 

   FIELD OF THE INVENTION 
   The present invention relates generally to storage systems, and more particularly to disk drive servo controllers. 
   BACKGROUND OF THE INVENTION 
   Conventional computer systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and disk drives. In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system. 
   The main memory is typically smaller than disk drives and may be volatile. Programming data is often stored on the disk drive and read into main memory as needed. The disk drives are coupled to the host system via a disk controller that handles complex details of interfacing the disk drives to the host system. Communications between the host system and the disk controller is usually provided using one of a variety of standard I/O bus interfaces. 
   Typically, a disk drive includes one or more magnetic disks. Each disk (or platter) typically has a number of concentric rings or tracks (platter) on which data is stored. The tracks themselves may be divided into sectors, which are the smallest accessible data units. A positioning head above the appropriate track accesses a sector. An index pulse typically identifies the first sector of a track. The start of each sector is identified with a sector pulse. Typically, the disk drive waits until a desired sector rotates beneath the head before proceeding with a read or writes operation. Data is accessed serially, one bit at a time and typically, each disk has its own read/write head. 
     FIG. 1  shows a disk drive system  100  with platters  101 A and  101 B, an actuator  102  and read/write head  103 . Typically, multiple platters/read and write heads are used. Platters  101 A- 101 B have assigned tracks for storing system information, servo data and user data. 
   The disk drive is connected to the disk controller that performs numerous functions, for example, converting digital to analog data signals, disk formatting, error checking and fixing, logical to physical address mapping and data buffering. To perform the various functions for transferring data, the disk controller includes numerous components. 
   To access data from a disk drive (or to write data), the host system must know where to read (or write data to) the data from the disk drive. A driver typically performs this task. Once the disk drive address is known, the address is translated to cylinder, head and sector, based on platter geometry and sent to the disk controller. Logic on the hard disk looks at the number of cylinders requested. Servo controller firmware instructs motor control hardware to move read/write heads  103  to the appropriate track. When the head is in the correct position, it reads the data from the correct track. 
   Typically, read and write head  103  has a write core for writing data in a data region, and a read core for magnetically detecting the data written in the data region of a track and a servo pattern recorded on a servo region. 
   A servo system  104  detects the position of head  103  on platter  101 A according to the phase of a servo pattern detected by the read core of head  103 . Servo system  104  then moves head  103  to the target position. 
   Servo system  104  servo-controls head  103  while receiving feedback for a detected position obtained from a servo pattern so that any positional error between the detected position and the target position is negated. 
   Typically, a servo controller in system  104  communicates with a data recovery device. One such device is shown in  FIG. 3 , as the “read channel device  303 ”. An example of such a product is “88C7500 Integrated Read channel” device sold by Marvell Semiconductor Inc®. 
   Typically, servo information is recorded in fixed amounts for a given product. In conventional systems, all the elements of servo fields are “hard-wired” to include details of interface timing between the servo controller and the read channel device  303 . The conventional approach has drawbacks. For example, the servo controller design must be modified each time the format of any of the servo data elements changes. Also, if the interface between the read channel device  303  and servo controller ( 303 A,  FIG. 4 ) changes, the servo controller must be modified. 
   Therefore, what is desired is an efficient controller that can accommodate multiple interfaces and also future changes in servo field formats. 
   SUMMARY OF THE INVENTION 
   A servo controller for an embedded disk controller comprises a read channel interface that includes a programmable control logic that receives a servo field detected signal from a module that detects a servo field start bit. A memory in the read channel interface is enabled by the programmable control logic for receiving servo field data from a read channel device, wherein the programmable control logic is configured to operate in a first mode and a second mode allowing the servo controller to process servo data from the read channel device. 
   In other features of the invention, the first mode is an m wire mode, the second mode is an n wire mode, m and n are integers, and m≠n. In the first mode the servo controller processes the servo data at a first data width and in the second mode the servo controller processes the servo data at a second data width. A filter receives unfiltered servo data from the memory. A counter receives the servo field detected signal. The programmable control logic may be configured by a processor in the embedded disk controller. 
   A method for collecting servo field data from programmable devices in embedded disk controllers comprises receiving a servo field detection signal at a programmable control logic in a read channel interface in a servo controller, wherein the programmable control logic is configured to operate both in a first mode and a second mode allowing the servo controller to process servo data from a read channel device, receiving control signal for capturing servo field data, and organizing servo field data. 
   In other features of the invention, the first mode is an m wire mode, the second mode is an n wire mode, m and n are integers, and m≠n. In the first mode the servo controller processes the servo data at a first data width and in the second mode the servo controller processes the servo data at a second data width. The programmable control logic in the read channel interface receives the servo field detection signal from a detect module. A memory in the read channel interface receives the control signal from the programmable control logic. The memory sends unfiltered servo field data to a bitmap filter. 
   A servo controller for an embedded disk controller comprises read channel interface means that includes a programmable control logic for receiving a servo field detected signal from a module that detects a servo field start bit and memory means in the read channel interface that is enabled by the programmable control logic for receiving servo field data from a read channel device, wherein the programmable control logic is configured to operate in a first mode and a second mode allowing the servo controller to process servo data from the read channel device. 
   In other features of the invention, the first mode is an m wire mode, the second mode is an n wire mode, m and n are integers, and m≠n. In the first mode the servo controller processes the servo data at a first data width and in the second mode the servo controller processes the servo data at a second data width. The servo controller further comprises filter means for receiving unfiltered servo data from the memory means. The servo controller further comprises counter means for receiving the servo field detected signal. The programmable control logic may be configured by a processor in the embedded disk controller. 
   This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof in connection with the attached drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing features and other features of the present invention will now be described. In the drawings, the same components have the same reference numerals. The illustrated embodiment is intended to illustrate, but not to limit the invention. The drawings include the following Figures: 
       FIG. 1  shows a block diagram of a disk drive; 
       FIG. 2  is a block diagram of an embedded disk controller system, according to one aspect of the present invention; 
       FIG. 3  is a block diagram showing the various components of the  FIG. 3  system and a two-platter, four-head disk drive, according to one aspect of the present invention; 
       FIG. 4  is a block diagram of a servo controller, according to one aspect of the present invention; 
       FIG. 5  is a block diagram of a read channel interface, according to one aspect of the present invention; 
       FIGS. 6A and 6B  are timing diagrams for two-wire and three-wire interface systems, respectively, according to one aspect of the present invention; and 
       FIG. 7  shows a flow diagram of executable process steps, according to one aspect of the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   To facilitate an understanding of the preferred embodiment, the general architecture and operation of an embedded disk controller will be described initially. The specific architecture and operation of the preferred embodiment will then be described. 
     FIG. 2  shows a block diagram of an embedded disk controller system  200  according to one aspect of the present invention. System  200  may be an application specific integrated circuit (“ASIC”). 
   System  200  includes a microprocessor (“MP)  201  that performs various functions described below. MP  201  may be a Pentium® Class processor designed and developed by Intel Corporation® or an ARM processor. MP  201  is operationally coupled to various system  200  components via buses  222  and  223 . Bus  222  may be an Advanced High performance (AHB) bus as specified by ARM Inc. Bus  223  may an Advanced Peripheral Bus (“APB”) as specified by ARM Inc. The specifications for AHB and APB are incorporated herein by reference in their entirety. 
   System  200  is also provided with a random access memory (RAM) or static RAM (SRAM)  202  that stores programs and instructions, which allows MP  201  to execute computer instructions. MP  201  may execute code instructions (also referred to as “firmware”) out of RAM  202 . 
   System  200  is also provided with read only memory (ROM)  203  that stores invariant instructions, including basic input/output instructions. 
   System  200  is also provided with a digital signal processor (“DSP”)  206  that controls and monitors various servo functions through DSP interface module (“DSPIM”)  208  and servo controller interface  210  operationally coupled to a servo controller (“SC”)  211 . 
   DSPIM  208  interfaces DSP  206  with MP  201  and allows DSP  206  to update a tightly coupled memory module (TCM)  205  (also referred to as “memory module”  205 ) with servo related information. MP  201  can access TCM  205  via DSPIM  208 . 
   Servo controller interface (“SCI”)  210  includes an APB interface  213  that allows SCI  210  to interface with APB bus  223  and allows SC  211  to interface with MP  201  and DSP  206 . 
   SCI  210  also includes DSPAHB interface  214  that allows access to DSPAHB bus  209 . SCI  210  is provided with a digital to analog and analog to digital converter  212  that converts data from analog to digital domain, and vice-versa. Analog data  220  enters module  212  and leaves as analog data  220 A to a servo device  221 . 
   SC  211  has a read channel device (RDC) serial port  217 , a motor control (“SVC”) serial port  218  for a “combo” motor controller device, a head integrated circuit (HDIC) serial port  219  and a servo data (“SVD”) interface  216  for communicating with various devices. 
     FIG. 3  shows a block diagram with disk  100  coupled to system  200 , according to one aspect of the present invention.  FIG. 3  shows a read channel device  303  that receives signals from a pre-amplifier  302  (also known as head integrated circuit (HDIC)) coupled to disk  100 . As discussed above, one example of a read channel device  303  is manufactured by Marvell Semiconductor Inc.®, Part Number 88C7500, while pre-amplifier  302  may be a Texas instrument, Part Number SR1790. Pre-amplifier  302  is also operationally coupled to SC  211 . Servo data (“SVD”)  305  is sent to SC  211 . 
   A motor controller  307  (also referred to as device  307 ), (for example, a motor controller manufactured by Texas Instruments (D, Part Number SH6764) sends control signals  308  to control actuator movement using motor  307 A. It is noteworthy that spindle  101 C is controlled by a spindle motor (not shown) for rotating platters  101 A and  101 B. SC  211  sends plural signals to motor controller  307  including clock, data and “enable” signals to motor controller  307  (for example, SV_SEN, SV_SCLK and SV_SDAT). 
   SC  211  is also operationally coupled to a piezo controller  509  that allows communication with a piezo device (not shown). One such piezo controller is sold by Rolm Electronics®, Part Number BD6801FV. SC  211  sends clock, data and enable signals to controller  509  (for example, SV_SEN, SV_SCLK and SV_SDAT). 
     FIG. 4  shows a block diagram of SC  211 , according to one aspect of the present invention.  FIG. 4  shows SC  211  with a serial port controller  404  for controlling various serial ports  405 - 407 . 
   SC  211  also has a servo-timing controller (“STC”)  401  that automatically adjusts the time base when a head change occurs. Servo controller  211  includes an interrupt controller  411  that can generate an interrupt to DSP  206  and MP  201 . Interrupts may be generated when a servo field is found (or not found) and for other reasons. SC  211  includes a servo-monitoring port  412  that monitors various signals to SC  211 . 
   SC  211  uses a pulse width modulation unit (“PWM”)  413  for supporting control of motor  307 A PWM, and a spindle motor PWM  409  and a piezo PWM  408 . 
   MP  201  and/or DSP  206  use read channel device  303  for transferring configuration data and operational commands through SC  211  (via read channel interface  303 A). 
     FIG. 5  is a block diagram of read channel interface (also referred to as Interface  303 A)  303 A. Serial data ( 505  and  506 ) from read channel device  303  is sent to serial register  503  and a start detect module  500 . Start detect module  500  sends a signal  516  to a counter  501  and control logic  502 . Signal  516  is generated after a servo field start bit is detected. 
   Control logic  502  includes a state machine (not shown) that may be configured by signal  515 . Signal  515  includes gray code, Position Error Signal (“PES”), run out correction (“ROC”) and Recovered Service field (“RSF”) configuration information. As is well known in the art, gray code is the front portion of the data as read from a media. MP  201  or DSP  206  may send signal  515 . 
   Servo field search signal  514  is received from DSP  206  or from timer hardware, by a synchronizer  505 . Signal  514  indicates the time to begin the search for servo field data. Synchronizer  505  then synchronizes signal  514  with serial data clock  512 . Synchronized signal  513  and serial data clock  512  are sent to control logic  502 . 
   Control logic generates signal  510  that is sent to serial register  503 . Signal  510  enables serial register  503  to receive data from read channel device  303 . Serial register  503  transfers unfiltered data  507  to a bitmap filter  504  that filters data  507  to generate servo data  508  that can be read by DSP  206  or MP  201 . DSP  206  or MP  201  using firmware and through signal  509  may set filter  504 . 
   Control logic  502  can operate under plural modes by using signal  511 . For example, control logic  502  may operate under a two-wire mode (one clock/one data) or three-wire mode (one clock/two data). Control logic  502  also sends a signal  518  to start detect module  500  that requests start detect module  500  to look for servo data. 
     FIGS. 6A and 6B  show timing diagrams for two-wire and three-wire systems, according to one aspect of the present invention. 
     FIG. 7  is a flow diagram of executable process steps, according to one aspect of the present invention. 
   In step S 701 , serial register  503  receives clock signal  512  and serial data ( 505  and  506 ). 
   In step S 700 , control logic  502  receives control signal  515  from MP  201  and/or DSP  206 . Signal  515  includes gray code, PES, ROC and RSF configuration information. 
   In step S 702 , control logic  502  generates signal  510  that enables serial register to capture data. 
   In step S 703 , data is organized so that MP  201  and/or DSP  206  can read it. In one aspect, unfiltered servo data  507  is sent to a bit map filter  504  that filters the data and generates servo data  508  so that it can be read by DSP  206  or MP  201 . 
   In one aspect of the present invention, elements of the servo fields are programmable and can be adjusted by firmware. Hence, hardware changes are not required to keep up with format changes. In another aspect of the present invention, both two and three wire systems may be used without using any additional circuits. 
   Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and not limiting. For example, the term signal as used herein includes commands. Many other applications and embodiments of the present invention will be apparent in light of this disclosure and the following claims.