Abstract:
A peak-buck peak-boost current mode control structure and scheme for a synchronous four-switch and non-synchronous two-switch buck-boost regulators sense input and output voltages to smoothly transition between buck mode, buck-boost mode, and boost mode for high power efficiency and low output ripples. With the inductor current sensing, the control scheme achieves the best performance in continuous conduction and discontinuous condition mode operations.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application is related to and claims priority of U.S. provisional patent application (“Provisional Application I”), Ser. No. 62/088,433, entitled “Peak-Buck Peak-Boost Current-Mode Control for Switched Step-up Step-down Regulators,” filed on Dec. 5, 2014. The disclosure of Provisional Application I is hereby incorporated by reference in its entirety. 
         [0002]    The present application is also related to U.S. provisional patent application (“Provisional Application II”), Ser. No. 62/054,587, entitled “DCR inductor current sensing for 4 switch buck-boost converters,” filed on Sep. 24, 2014. The disclosure of the Provisional Application II is hereby incorporated by reference in its entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0003]    1. Field of the Invention 
         [0004]    The present invention relates to switched step-up step-down regulators, and more particularly, to the control of such switched step-up step-down regulators using a current-mode control scheme. 
         [0005]    2. Discussion of the Related Art 
         [0006]    Step up-step down or buck-boost switching regulators handle input voltages that can be above, below, or equal to the output voltage.  FIGS. 1 and 2  are schematic diagrams which show a synchronous four-switch buck-boost regulator and a non-synchronous two-switch buck-boost regulator, respectively. In each of the buck-boost regulators of  FIGS. 1 and 2 , the output voltage is regulated by sequentially activating or deactivating switches S A , S B , S C  and S D . For example, three types of control schemes may be applied to these buck-boost regulators: (a) a hysteretic mode control scheme, disclosed in U.S. Pat. No. 6,348,779 (“Sluijs”); (b) a voltage mode control scheme, disclosed in U.S. Pat. No. 6,087,816 (“Volk”), U.S. Pat. No. 6,166,527 (“Dwelley”) and U.S. Pat. No. 7,116,085 (“Ikezawa”); and (c) a current mode control scheme, disclosed in U.S. Pat. No. 7,256,570 (“Zhou”), U.S. Pat. No. 7,298,119 (“Amram Summit”), U.S. Pat. No. 7,394,231 (“Flatness”), and U.S. Patent Application Publication 2011/0279098 (“Ren”). 
         [0007]    Hysteretic mode control schemes, e.g., those disclosed in Sluijs, typically switch among different operating states based on monitoring an output voltage using a window comparator. Disadvantages of a hysteretic mode control scheme include: the varying switching frequency is load-dependent, high output voltage ripples, and high noise mode transition. 
         [0008]    Voltage mode control schemes, e.g., those disclosed in Volk, Dwelley and Ikezawa, are widely used in commercial buck-boost regulators. Voltage mode control schemes offer fixed switching frequency, low output voltage ripples, and low noise mode transition. However, the voltage mode control schemes typically run in forced continuous conduction mode, in which the inductor current can flow from the output terminal to the input terminal. The forced continuous conduction mode operation is not suitable for some applications (e.g., a battery charger application) that do not allow reverse currents. For such applications, a pulse-skip or burst discontinuous conduction mode operation handles the reverse current, when present. However, mode transitions in these control schemes generate large output transient ripples in the output load. Other disadvantages of the voltage mode control schemes include difficulty in compensating for a wide V IN  range and no paralleling output capability. 
         [0009]    The current mode control schemes, e.g., those disclosed in Zhou, Amram Summit, Flatness and Ren, allow easy compensation and parallel outputs.  FIG. 3  illustrates a conventional peak current mode control scheme as applied to a synchronous four-switch buck-boost regulator (e.g., the synchronous four-switch buck-boost regulator of  FIG. 1 ). In the peak current mode scheme of  FIG. 3 , switches S A  and S C  are activated at the beginning of every clock pulse, allowing the inductor current of inductor L to be sensed by a comparator receiving a voltage across resistor R S . When the comparator output voltage switches polarity, switches S A  and S C  are deactivated and switches S B  and S D  are activated until the next clock pulse. This peak current mode scheme does not have a mode transition. However, the disadvantages of the current mode control scheme include high inductor current ripples and low power efficiency. 
         [0010]      FIG. 4  illustrates another current mode control scheme—the valley-buck peak-boost current mode scheme. The valley-buck peak-boost control scheme achieves low inductor current ripples, low output voltage ripples, and high power efficiency. Under the valley-buck peaK-boost control scheme, based on the inductor current sensed in ground sensing R S  resistor, the regulator runs in a valley current mode control scheme for a step-down operation and a peak current mode control scheme for a step-up operation. The valley-buck peak-boost control scheme is advantageous for operating in a continuous conduction mode because of its symmetry. However, without a reverse current detection capability under boost operations (when switches S A  and S D  are activated), the pulse-skip or burst mode discontinuous conduction operations are problematic. In addition, the valley current mode control scheme during step-down operations may present a current-runaway condition, as no peak current limit is enforced. 
       SUMMARY 
       [0011]    According to one embodiment of the present invention, a peak-buck peak-boost current mode control scheme is applied to a synchronous four-switch buck-boost regulator or a non-synchronous two-switch buck-boost regulator. Such a peak-buck peak-boost current mode control scheme, which uses a single inductor sensing resistor to detect the inductor current, is capable of handling a reverse current, while achieving the benefits of low inductor current ripples, low output voltage ripples, and high power efficiency. 
         [0012]    The control scheme of the present invention is applicable to both continuous conduction and discontinuous conduction operations, including pulse skip discontinuous conduction mode and burst mode discontinuous conduction mode operations. The peak-buck peak-boost current mode control scheme of the present invention may be applied to synchronous two-switch buck regulators, synchronous two-switch boost regulators, non-synchronous single-switch buck regulators and non-synchronous single-switch boost regulators. 
         [0013]    According to one embodiment of the present invention, a peak-buck peak-boost control circuit for a voltage regulator may include (i) a mode selection circuit generating control signals representing (a) a first control state in which the input voltage is greater than the output voltage by at least a predetermined value; (b) a second control state in which the input voltage is greater than the output voltage less than or equal to the predetermined value; (c) a third control state in which the output voltage is greater than the input voltage by less than or equal to a second predetermined value; (d) a fourth control state in which the output voltage is greater than the input voltage by at least the predetermined value; and (ii) switch control signal generation circuit for generating control signals for operating switches in the voltage regulator, such that the voltage regulator is configured as (a) the buck regulator in the first control state, (b) a buck-boost regulator in the second and third control states, and (c) a boost regulator in the fourth control state. 
         [0014]    The mode selection circuit may incorporate hysteresis for transitioning between the first and second control states, or for transitioning between the third and fourth control states. The output voltage may be provided as a scaled feedback signal. The voltage regulator may include an inductor and the peak-buck and peak-boost control scheme may use a ramping voltage signal to determine a peak value in a current flowing in the inductor. The peak value may be determined from the ramping voltage and an error signal derived from the output voltage. The occurrence of the peak value may be used to control switches in an output side of the voltage regulator. The error signal may be an amplified difference between a reference voltage and the output voltage. A compensation circuit receiving the error signal may be provided for ensuring loop stability in the voltage regulator. 
         [0015]    The peak-buck peak-boost control scheme of the present invention may also determine an occurrence of the peak current using the ramping voltage, an offset voltage and an error signal derived from the output voltage. The offset voltage may be derived from a difference in voltage at two time points of the ramping voltage. The two time points are specific time points within a switching cycle of the peak-buck peak-boost control circuit. The occurrence of the peak value may be used to control switches in an input side of the voltage regulator. 
         [0016]    The current mode control scheme of the present invention may also be used in conjunction with any inductor current-sensing method disclosed in provisional Application II. 
         [0017]    The present invention is better understood upon consideration of the detailed description below in conjunction with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]      FIG. 1  is a schematic diagram which shows a synchronous four-switch buck-boost regulator. 
           [0019]      FIG. 2  is a schematic diagram which shows a non-synchronous two-switch buck-boost regulator. 
           [0020]      FIG. 3  illustrates a conventional peak current mode control scheme as applied to a synchronous four-switch buck-boost regulator (e.g., the synchronous four-switch buck-boost regulator of  FIG. 1 ). 
           [0021]      FIG. 4  illustrates a valley-buck peak-boost current mode control scheme as applied to a synchronous four-switch buck-boost regulator (e.g., the synchronous four-switch buck-boost regulator of  FIG. 1 ). 
           [0022]      FIG. 5  shows synchronous four-switch buck-boost regulator  500  being controlled under a peak-buck peak-boost current mode control scheme, according to one embodiment of the present invention. 
           [0023]      FIG. 6  shows non-synchronous two-switch buck-boost regulator  600  being controlled under a peak-buck peak-boost current mode control scheme, according to one embodiment of the present invention. 
           [0024]      FIG. 7  is a block diagram showing schematically control circuit  700 , which implements a peak-buck peak-boost current mode control scheme, in accordance with one embodiment of the present invention. 
           [0025]      FIG. 8( i )  illustrates operating mode determination in selection circuit  720  and  FIGS. 8 ( ii )- 8 ( iv ) show the logic values of control signals ON_BUK, ON_BST, PK_BUK and PK_BST, respectively, relative to the ratio V IN /V OUT , according to one embodiment of the present invention. 
           [0026]      FIG. 9  shows waveforms of clock signals, CLK_A, CLK_B, and CLK_C, slope compensation signal V SLP  and slope compensation offset signal V OS , according to one embodiment of the present invention. 
           [0027]      FIG. 10  shows flow chart  1000  illustrating the operations of buck logic circuit  721  and boost logic circuit  722  of  FIG. 7  under a continuous conduction mode, in accordance with one embodiment of the present invention. 
           [0028]      FIG. 11  shows flow chart  1100  illustrating the operations of buck logic circuit  721  and boost logic circuit  722  of  FIG. 7  under a discontinuous conduction mode, in accordance with one embodiment of the present invention. 
           [0029]      FIG. 12  shows the waveforms of control signals CLK_A, CLK_B, CLK_C, A, B, C and D and current I L  in inductor L, under the operating condition in which input voltage V IN  is much higher than output voltage V OUT , in accordance one embodiment of the present invention. 
           [0030]      FIG. 13  shows the waveforms of control signals CLK_A, CLK_B, CLK_C, A, B, C and D and current I L  in inductor L, under the operating condition in which input voltage V IN  is slightly higher than output voltage V OUT , in accordance one embodiment of the present invention. 
           [0031]      FIG. 14  shows the waveforms of control signals CLK_A, CLK_B, CLK_C, A, B, C and D and current I L  in inductor L, under the operating condition in which input voltage V IN  is much lower than output voltage V OUT , in accordance one embodiment of the present invention. 
           [0032]      FIG. 15  shows the waveforms of control signals CLK_A, CLK_B, CLK_C, A, B, C and D and current I L  in inductor L, under the operating condition in which input voltage V IN  is slightly lower than output voltage V OUT , in accordance one embodiment of the present invention. 
           [0033]      FIG. 16  shows the waveforms of control signals CLK_A, CLK_B, CLK_C, A, B, C and D and current I L  in inductor L, under the operating condition in which input voltage V IN  is equal output voltage V OUT  in peak-buck buck-boost mode, in accordance one embodiment of the present invention. 
           [0034]      FIG. 17  shows the waveforms of control signals CLK_A, CLK_B, CLK_C, A, B, C and D and current I L  in inductor L, under the operating condition in which input voltage V IN  is equal output voltage V OUT  in peak-boost buck-boost mode, in accordance one embodiment of the present invention. 
       
    
    
       [0035]    To facilitate cross-referencing among the figures, like elements are assigned like reference numerals. 
       DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0036]      FIGS. 5 and 6  show control circuits  501  and  601  controlling synchronous four-switch buck-boost regulator  500  and non-synchronous two-switch buck-boost regulator  600 , respectively, under a peak-buck peak-boost current mode control scheme, according to one embodiment of the present invention. As shown in  FIGS. 5 and 6 , control circuits  501  and  601  each receive its respective input voltage V IN  and its respective output voltage V OUT . Although  FIGS. 5 and 6  each show direct sensing of voltages V IN  and V OUT , other methods may also be used, such as indirect sensing of V IN  and V OUT  and sensing scaled versions of VI N  and V OUT . Further,  FIGS. 5 and 6  show buck-boost regulators  500  and  600  sensing the current in inductor L through sensing a voltage drop across single resistor R S . However, other current sensing methods may also be used, such as direct-current resistance (DCR) sensing, FET drain-source (V DS ) sensing, or by the use of two resistors (i.e., one resistor provided between switch S A  and the terminal receiving voltage V IN , and the other resistor provided between switch S B  and the ground reference. 
         [0037]      FIG. 7  is a block diagram showing schematically control circuit  700 , which implements a peak-buck peak-boost current mode control scheme, in accordance with one embodiment of the present invention. Control circuits  501  and  601  of  FIGS. 5 and 6  may each be implemented by control circuit  700 . Control circuit  700  provides output signals A, B, C and D, for controlling switches S A , S B , S C  and S D  of a synchronous four-switch buck-boost regulator, respectively. In the case of controlling a non-synchronous two-switch buck-boost regulator, such as shown in  FIG. 6 , signals B and D may be simply ignored. As shown in  FIG. 7 , control circuit  700  receives input signals V IN , V OUT , LSP, LSN, and V FB . Signals LSP and LSN provide the voltage drop across sensing resistor R S  and signal V FB  is a scaled voltage representing output voltage V OUT . 
         [0038]    Control circuit  700  operates a regulator under one of four operating modes: (a) when input voltage V IN  is much higher than output voltage V OUT ; (b) when input voltage V IN  is much lower than output voltage V OUT ; (c) when input voltage V IN  is slightly higher than output voltage V OUT , and (d) when input voltage V IN  is slightly lower than output voltage V OUT . When input voltage V IN  is much higher than output voltage V OUT , the regulator is operated under a pure buck mode with peak-buck current mode control (“peak-buck buck mode”). When input voltage V IN  is much lower than output voltage V OUT , the regulator is operated under a pure boost mode with peak-boost current mode control (“peak-boost boost mode”). When input voltage V IN  is slightly higher than output voltage V OUT , the regulator is operated under a buck-boost mode with peak-buck current mode control (“peak-buck buck-boost mode”). When input voltage V IN  is slightly lower than output voltage V OUT , the regulator is operated under a buck-boost mode with peak-boost current mode control (“peak-boost buck-boost mode”). 
         [0039]    Based on the values of input signal V IN  and output signal V OUT , mode selection circuit  720  ( FIG. 7 ) determines which of the aforementioned four operative modes to operate the regulator. The selected operating mode is communicated to the remainder of control circuit  700  by the states of the control signals ON_BST, ON_BUK, PK_BUK and PK_BST which are generated by mode selection circuit  720 .  FIG. 8( i )  illustrates operating mode determination in selection circuit  720  and  FIGS. 8 ( ii )- 8 ( iv ) show the logic values of control signals ON_BUK, ON_BST, PK_BUK and PK_BST, respectively, relative to the ratio V IN /V OUT , according to one embodiment of the present invention. Mode selection circuit  720  may include three comparators to generate control signals ON_BST, ON_BUK, PK_BUK and PK_BST, as control signals PK_BUK and PK_BST have complementary values. As shown in  FIG. 8 ( iv ), when ratio V N  is greater than 1, control signal PK_BUK is set to value ‘1’ (and, correspondingly, control signal PK_BST is set to ‘0’) and one of the two “peak-buck” current operating modes is activated. Conversely, when ratio V IN /V OUT  is less than 1, control signal PK_BST is set to value ‘1’ (and, correspondingly, control signal PK_BUK is set to ‘0’) and one of the two peak-boost current operating modes is activated. Control signal ON_BUK is set to ‘1’ to indicate that a buck phase (i.e., during which both switches S B  and S D  are activated) is selected. Likewise, control signal ON_BST is set to ‘1’ to indicate that a boost phase (i.e., during which both switches S A  and S C  are activated) is selected. As shown in  FIG. 8 , hysteresis is provided to avoid oscillation between mode transitions. For example, as shown in  FIG. 8 ( ii ), control signal ON_BUK remains at value ‘0’ until the increasing ratio V IN /V OUT  reaches 0.9. Conversely, control signal ON_BUK remains at value ‘1’ until the decreasing ratio V IN /V OUT  reaches 0.8. Similarly, as shown in  FIG. 8 ( iii ), control signal ON_BST remains at value ‘1’ until the increasing ratio v reaches 1.25. Conversely, control signal ON_BST remains at value ‘0’ until the decreasing ratio V IN /V OUT  reaches 1.11. As a result, mode transitions between “peak-buck buck mode” and “peak buck buck-boost mode” and between “peak-boost buck-boost mode” and “peak-boost boost mode” follow the hystereses in control signals ON_BST and ON_BUK, respectively. 
         [0040]    As shown in  FIG. 7 , oscillator circuit  710  generates clock signals, CLK_A, CLK_B, and CLK_C, slope compensation signal Vst L  and slope compensation offset signal V OS .  FIG. 9  shows waveforms of clock signals, CLK_A, CLK_B, and CLK_C, slope compensation signal V SLP  and slope compensation offset signal V OS , according to one embodiment of the present invention. As shown in  FIG. 9 , the rising edge of clock signal CLK_A marks the beginning of a switching period. The rising edge of clock signal CLK_C marks a 10% switching period delay, while the rising edge of clock CLK_B marks a 90% switching period delay. Compensation signal V SLP  may be provided either as a linear slope compensation (solid trace) or as a nonlinear slope compensation (dashed trace). In either case, slope compensation offset signal V OS  is provided as a voltage difference between the values of slope compensation signal V SLP  at the 10% switching period delay and at the 90% switching period delay. 
         [0041]    In each of regulator circuits  500  and  600 , current I L  in inductor L is sensed through sense resistor R S . As shown in  FIG. 7 , amplifier  702  receives and amplifies (with a fixed gain) a differential signal represented by the difference between signals LSP and LSN to provide single-ended signal  703 . Output voltage V OUT  is sensed and scaled to provide feedback signal V FB  by a voltage divider formed by resistors R FB1  and R FB2 . Feedback signal V FB  is provided to error amplifier  704 , which generates an error signal V C . Signal V C  represents a voltage difference between reference signal V REF  and feedback signal V FB . 
         [0042]    Compensation network  711  provides loop stability based on error signal V C . The output signals from amplifier  702  and error amplifier  704 , slope compensation signal V SLP , and slope compensation offset signal V OS  are provided to buck current comparator  705  and boost current comparator  706 . According to the operating mode set by mode selection circuit  720 , buck logic circuit  721  and boost logic circuit  722  provide control signals A, B, C and D, which are used to the respective control switches S A , S B , S C , and S D  in circuits  500  and  600 . 
         [0043]    The control schemes of the present invention are applicable to continuous conduction mode and pulse-skip and burst discontinuous conduction modes.  FIG. 10  shows flow chart  1000  illustrating the operations of buck logic circuit  721  and boost logic circuit  722  of  FIG. 7  under a continuous conduction mode, in accordance with one embodiment of the present invention. 
         [0044]      FIGS. 12-17  show the waveforms of control signals CLK_A, CLK_B, CLK_C, A, B, C and D and current I L  in inductor L, under various operating conditions, in accordance with one embodiment of the present invention. When control switch A, B, C or D is activated, the corresponding switch S A , S B , S C  and S D  is conducting. In each of these figures, the shoot-through protection dead times between control signals A and B, and between control signals C and D (which would be understood to be present by those of ordinary skill in the art) are not shown so as to simplify the detailed description herein. 
         [0045]    As shown in  FIG. 10 , control signal CLK_A determines the timing of each cycle, which begins at the rising edge of control signal CLK_A (step  1002 ). Based on the determinations at steps  1003 - 1005 , based on the logic values of control signals PK_BUK, PK_BST, ON_BST and ON_BUK control circuit  700  generates switch control signals A, B, C and D to operate switches S A , S B , S C  and S D . As mentioned above, when input voltage V IN  is much higher than output voltage V OUT  (PK_BUK=‘1’, ON_BUK=‘1’, and ON_BST=‘0’), the regulator is operated under the peak-buck buck mode, according to steps  10014 - 1015 .  FIG. 12  shows the waveforms of control signals CLK_A, CLK_B, CLK_C, A, B, C and D and current I L  in inductor L. Under this mode, switch control signal C is deactivated and switch control signal D is activated throughout the switching cycle. Switch control signals A and B are alternatingly activated and deactivated according to peak-buck current mode control. Specifically, at step  1014 , switch control signal A is activated, leading to ramping up of inductor current I L  until the voltage difference between signals LSP and LSN (representing current I L  in inductor L) reaches V C −V SLP +V OS , at which time buck current comparator  705  transitions its output state. When that voltage threshold is reached, switch control signal A is deactivated and switch control signal B is activated (step  1015 ). This state is maintained until the beginning of the next switching cycle (step  1016 ). 
         [0046]    When input voltage V IN  is slightly higher than output voltage V OUT , the regulator is operated under peak-buck buck-boost mode (PK_BUK=‘1’, ON_BUK=‘1’, and ON_BST=‘1’) according to steps  1011 - 1013 .  FIG. 13  shows the waveforms of control signals CLK_A, CLK_B, CLK_C, A, B, C and D and current I L  in inductor L, under peak-buck buck-boost mode. As shown in  FIG. 13 , at the beginning of the cycle (step  1011 ), switch control signals A and C are activated, and switch control signals B and D are deactivated, to provide a fixed boost phase to inductor current I L . At step  1012 , at the rising edge of control signal CLK_C (at the beginning 10% of the switching cycle), switch control signal C is deactivated and switch control signal D is activated to allow a slower ramp in inductor current I L  until the voltage difference between signals LSP and LSN (representing current I L  in inductor L) reaches V C −V SLP +V OS , at which time buck current comparator  705  transitions its output state. When buck current comparator  705  transitions its output state, switch control signal A is deactivated and switch control signal B is activated until the beginning of the next switching cycle (step  1013 ). 
         [0047]    When input voltage V IN  is much lower than output voltage V OUT  (PK_BST=‘1’, ON_BUK=‘0’, and ON_BST=‘1’), the regulator is operated under the peak-boost boost mode, according to steps  1006 - 1007 .  FIG. 14  shows the waveforms of control signals CLK_A, CLK_B, CLK_C, A, B, C and D and current I L  in inductor L, under the peak-boost boost mode. As shown in  FIG. 14 , switch control signal A is activated and switch control signal B is deactivated for the entire switching cycle. At steps  1006 - 1007 , switch control signals C and D are alternatingly activated and deactivated according to peak-boost current mode control. At the beginning of the cycle, i.e., at the rising edge of clock signal CLK_A, switch control signal C is activated to allow inductor current I L  to ramp up. When the voltage difference between signals LSP and LSN (representing inductor current I L ) reaches V C −VS LP , boost current comparator  706  transitions its output state, switch control signal C is deactivated and switch control signal D is activated until the next switching cycle (step  1007 ). 
         [0048]    When input voltage V IN  is slightly lower than output voltage V OUT  (PK_BST=‘1’, ON_BUK=‘1’, and ON_BST=‘1’), the regulator is operated under a peak-boost buck-boost mode, according to steps  1008 - 1010 .  FIG. 15  shows the waveforms of control signals CLK_A, CLK_B, CLK_C, A, B, C and D and current I L  in inductor L, under the peak-boost buck-boost mode. As shown in  FIG. 15 , switch control signal A is activated for the beginning 90% of the switching cycle (i.e., switch control signal A is activated at the rising edge of clock signal CLK_A and deactivated at the rising edge of clock signal CLK_B). At the beginning of the cycle (i.e., at the rising edge of clock signal CLK_A), both switch control signals A and C are activated according to step  1008 , so that inductor current I L  ramps up. When the voltage difference between signals LSP and LSN (representing inductor current I L ) reaches V C −V SLP , boost current comparator  706  transitions its output state. At that time, according to step  1009 , switch control signal C is deactivated and switch control signal D is activated. At the rising edge of clock signal CLK_B, i.e., at 90% of the cycle, switch control signal A is deactivated and switch control signal B is activated until the next switching cycle (step  1010 ). 
         [0049]    In either peak-buck buck-boost mode (i.e., the operating condition of  FIG. 13 ) or peak-boost buck-boost mode (i.e., the operating condition of  FIG. 15 ), V IN  may become equal to output voltage V OUT . In either case, inductor current I L  is flat when both switch control signals A and D are activated.  FIG. 16  shows the waveforms of control signals CLK_A, CLK_B, CLK_C, A, B, C and D and current I L  in inductor L, under the operating condition in which input voltage V IN  is equal to output voltage V OUT  in peak-buck buck-boost mode, in accordance one embodiment of the present invention.  FIG. 17  shows the waveforms of control signals CLK_A, CLK_B, CLK_C, A, B, C and D and current I L  in inductor L, under the operating condition in which input voltage V IN  is equal to output voltage V OUT  in peak-boost buck-boost mode, in accordance one embodiment of the present invention. As buck current comparator  705  compares the voltage representing inductor current I L  with the voltage sum of signals V C  and V OS , while boost current comparator  706  compares the voltage representing inductor current I L  with of voltage of signal V C , signal V C  is stable regardless whether control transitions from peak-buck current mode control to peak-boost current mode control, or in the opposite direction. Thus, a regulator of the present invention has low-noise control transitions. 
         [0050]      FIG. 11  shows flow chart  1100  illustrating the operations of buck logic circuit  721  and boost logic circuit  722  of  FIG. 7  under a discontinuous conduction mode, in accordance with one embodiment of the present invention. According to  FIG. 11 , if inductor current I L  falls below zero (“reverse current”; i.e., current flowing from the output side to the input side), all switch control signals may be deactivated to open all four switches during the peak-buck buck-boost mode or the peak-boost buck-boost mode (step  1102 ). Alternatively, in peak-buck buck mode, switch control signal B may be deactivated to open switch B (step  1103 ). Similarly, in peak-boost boost mode, switch control signal D may be deactivated to open switch D (step  1101 ). 
         [0051]    The above detailed description is provided to illustrate the specific embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is set forth in the claims.