Abstract:
A method of improving network interface reliability uses a fail-over mechanism. When one network card becomes disabled, a second network card takes its place. A mid-plane separates the network card into a transition portion and a main portion. Cables are connected to the transition portion, and allows input and output from a particular network card to be re-routed to another network card without the need to physically alter the external cables.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The described invention relates to the field of network communications. In particular, the invention relates to a method for improving reliability of a network system by using a fail-over mechanism that employs redundant network cards.  
           [0003]    2. Description of Related Art  
           [0004]    In a typical chassis system, numerous circuit boards are plugged into the backside of the chassis. Network connections are attached either directly to network communication circuit boards (“network cards”) or to the front of the chassis where the connectors allow signals to be passed through the chassis to network circuit cards inside.  
           [0005]    Replacing a failed network card in a system may take a significant amount of time and may cause unacceptable service interruptions to customers. Additionally, the replacement process may involve removing various attached cables, fitting the replacement board, and reattaching the network cables properly. This gives rise to the possibility of wiring errors, which can further interrupt network service.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]    [0006]FIG. 1 is an exemplary midplane system having a chassis with transition and main network cards.  
         [0007]    [0007]FIG. 2 is an exemplary edge connector of a network card for plugging into the midplane.  
         [0008]    [0008]FIG. 3 is a block diagram showing components on a main network card.  
         [0009]    [0009]FIG. 4 shows a schematic diagram of I/O signals coupled to a first main card and its associated backup main card.  
         [0010]    [0010]FIG. 5 shows one mechanism for switching between a primary main card and a backup main card.  
         [0011]    [0011]FIG. 6 shows one example of multiple primary main cards providing I/O signals to a common backup main card.  
         [0012]    [0012]FIG. 7 shows an example of multiple main cards providing I/O signals to multiple backup cards.  
     
    
     DETAILED DESCRIPTION  
       [0013]    One architecture that allows easier replacement of network cards uses a midplane system as shown in FIG. 1. In particular, chassis  100  contains midplane  102 . Midplane  102  is a circuit board that provides jacks for plug-in cards such as main cards  104   a - n  and transition cards  106   a - n  to plug into. Unlike a standard chassis system in which all cables are passed through the chassis directly to the network card, a midplane system uses transition cards that allow for easy loading and removal of network (main) cards without having to tamper with the cabling and the assembly of the system.  
         [0014]    Main cards  104   a - n  contain active electrical components, such as the processing engines, and have a higher failure rate than passive components. Conversely, transition cards  106   a - n  contain primarily passive electrical components (e.g., resistors, capacitors, inductors) and mostly provide Input/Output (hereinafter I/O) termination; transition cards have a lower failure rate than the main cards. This deliberate separation of functionality is an attempt to maintain a high level of fault tolerance for the midplane system. More specifically, replacing a transition card  106   a - n  likely involves reconfiguring I/O and rearranging physical cabling, which are both time-consuming and susceptible to errors. Therefore, implementing a transition card  106   a - n  with a low failure rate is likely to result in infrequent changes of the card and a reduced probability of encountering undesirable delays and errors that are associated with the card changes. On the other hand, unlike a transition card  106   a - n , swapping out a main card  104   a - n  does not involve the mentioned reconfiguration and rearrangement. Thus, placing core processing on an easily exchangeable network communication card, such as main card  104   a - n , helps to avoid disrupting operations of the midplane system.  
         [0015]    Referring to FIG. 1, a transition card  106   a  is coupled to network I/O  108   a  via cable interfaces. Transition card  106   a  is also coupled to main card  104   a  via the midplane  102  which allows I/O signals to be passed through from one side to the other. Midplane  102  may also allow signals to be routed to other transition or main cards plugged in to the chassis  100 . In one embodiment, connectors  110  between transition cards may also be employed so that common signals are provided to multiple transition cards. Similarly, transition card  106   b  is coupled to network I/O  108   b  and to main card  104   b  via the midplane  102 , and so forth.  
         [0016]    In one embodiment, each of the main cards  104   a -n communicate via a Compact PCI (cPCI) bus. (The cPCI specification is published by the PCI Industrial Computers Manufacturer&#39;s Group.) The cPCI bus allows the main cards to be hot-swapped, i.e., removed and replaced without the need to power down the chassis  100 .  
         [0017]    [0017]FIG. 2 shows an exemplary edge connector of a main card for plugging into the midplane. In one embodiment, the connector comprises five sets of I/O pins for providing various I/O signals. Referring to FIG. 2, a first set of pins  151  provides the signals for a 32-bit cPCI bus. A second set of pins  152  provides the signals for a 64-bit extension to the cPCI bus. A third set of pins  153  allow I/O signals to pass through the midplane from transition cards to corresponding main cards. This set of signals  153  can be used for Ethernet signals, or can be custom-defined between the transition board and the main board. A fourth set of signals  154  allows a second bus to be used to communicate with other network (main and/or transition cards) cards via the midplane. For example, a computer telephony bus such as H.110 may be employed. A fifth set of pins  155  also allows I/O signals to pass through the midplane from transition cards to corresponding main cards. In one embodiment, tip and ring signals are passed through the fifth set of pins  155 . In one embodiment, a transition card is coupled to its main card through the third, fourth, and fifth set of pins ( 153 - 155 ) described above.  
         [0018]    [0018]FIG. 3 is a block diagram showing exemplary components on a main network card. In one embodiment, a microcontroller  201  is coupled to a T 1  Framer Line Interface Unit (LIU)  202  to provide processing and network functionalities. The T1 protocol (also called DS1) is specified by the American National Standards Institute (latest revision T1.403.00, 403.01, 403.02-1999). A watch dog timer (WDT)  203  is coupled to the microcontroller  201 . The microcontroller  201  programs the WDT  203  to a predetermined reset value, then starts the WDT  203  counting down. The microcontroller  201  then periodically resets the WDT  203  so that it starts counting down from the reset value again. If a problem occurs preventing the microcontroller  201  from resetting the WDT  203  such that the WDT  203  counts all the way down to zero, then the WDT  203  signals that an error occurred. In one embodiment, when the WDT  203  times out, it signals a failure to the microcontroller  201  as well as a logic device such as Complex Programmable Logic Device (CPLD)  204 .  
         [0019]    When the CPLD  204  detects a failure, e.g., from the time out of the WDT  203 , the CPLD  204  sends a fail signal to its transition board. The CPLD  204  also disables its own transmitter by turning off the Output Enable (OE) to the main card&#39;s transmitter (not shown), and the CPLD  204  sends a fail signal to the microcontroller  201 .  
         [0020]    [0020]FIG. 4 shows a schematic diagram of I/O signals coupled to a first main card  340  and its associated backup main card  350 . In one embodiment, the backup main card  350  is dedicated as a backup solely for main card  340 . For example, main card  104   b  can be a dedicated backup card for main card  104   a , main card  104   d  can be the backup card for main card  104   c , and so forth.  
         [0021]    Referring to FIG. 4, the transmitted signals  300 , i.e., the I/O signals that are transmitted out of the chassis, have a tip and a ring component. In one embodiment, the tip component of transmitted signals  300  is coupled via capacitors  305  to both the tip component of the main card&#39;s transmitter  310  and the tip component of the backup main card&#39;s transmitter  320 . Similarly, the ring component of transmitted signals  300  is coupled via capacitors  306  to both the ring component of the main card&#39;s transmitter  310  and the ring component of the backup main card&#39;s transmitter  320 .  
         [0022]    The received signals  302 , i.e., the I/O signals that are received into the chassis, also have tip and ring components. The tip component of the received signals  302  is coupled directly to the tip components of the main card&#39;s receiver  312  and to the tip component of the backup main card&#39;s receiver  322 . The ring component of the received signals  302  is coupled directly to the ring component of the main card&#39;s receiver  312  and to the ring component of the backup main card&#39;s receiver  322 . No capacitor is needed to couple the received signals  302  to the receivers  312 / 322  of the main card  340  and the backup main card  350 .  
         [0023]    In one embodiment, passive components such as capacitors  305  and  306  are placed on the transition cards and the active components such as transmitters and receivers are implemented on the main cards. A synchronous clock is provided to both the main card and the backup main card. Network I/O cables need not be redundantly attached to multiple circuit boards of the chassis since the network I/O signals can be routed internally through the chassis either via the midplane or via connectors coupling the transition boards together. With the circuitry configured as in FIG. 4, a dedicated backup main card is able to operatively mimic the main card since it receives the same inputs. The backup main card&#39;s output is simply disabled through the output enable (OE) of the backup main card&#39;s transmitter  320 . However, when a failure is detected the OE of the main card&#39;s transmitter is disabled and the OE of the backup main card&#39;s transmitter is enabled. This allows nearly instantaneous swapping of network operations between the main card and the backup main card. For example, on a T1 line, switching is done within a 125 microsecond, which is a small enough delay as to not cause a frame loss error. This dedicated backup architecture is referred to as a 1+1 architecture, i.e., one backup card for each primary main card.  
         [0024]    [0024]FIG. 5 shows one mechanism for switching between a primary main card and a backup main card. In one embodiment, the CPLD on the primary main card provides a signal whether the primary main card should be active (“ONLINE”, e.g., digital 1) or disabled (“OFFLINE”, e.g., digital 0). The backup card&#39;s CPLD provides a similar signal. The OE&#39;s of the primary main card and its backup card are coupled through a flip-flop circuit such that only one OE is active at a time. In this embodiment, once the primary main card is disabled, the primary main card will not be able to assert its OE again until it is ONLINE again and the backup card is OFFLINE.  
         [0025]    In an alternate embodiment, one backup main card  350  serves as backup for multiple main cards. Hardware and software are used to route the appropriate signals from a failed main card to the backup main card  350 . However, since it is not known which of the multiple main cards will fail, it not possible for the backup main card to operatively mimic the failed card as in the dedicated backup architecture. Thus, there is a relatively long delay when the backup card  350  takes over for a failed card. In one embodiment, this delay is around the time of one frame sync.  
         [0026]    [0026]FIG. 6 shows one example of multiple main cards providing I/O signals to a common backup card. In this example, when a failure occurs on a main card, gates on the corresponding transition card enable its I/O signals to pass through to the backup main and transition card. An N+1 architecture has N primary main cards and one backup card.  
         [0027]    [0027]FIG. 7 shows an example of multiple main cards providing I/O signals to multiple backup cards. Hardware and software determine which backup card to enable first and route the appropriate I/O signals from a failed main card to the appropriate backup main cards  350 . This is called an N+M architecture, where N is the number of primary main cards and M is the number of backup cards.  
         [0028]    Thus, a method of improving network reliability has been described. However, the specific embodiments and methods described herein are merely illustrative. Numerous modifications in form and detail may be made without departing from the scope of the invention as claimed below. For example, although the previous description describes an embodiment using a cPCI bus to communicate between the network communication cards, a different communication bus may be employed. Similarly, protocols other than the T1 protocol may be employed. The invention is limited only by the scope of the appended claims.