Abstract:
A method is disclosed for selecting a semiconductor chip in a stack of semiconductor chips interconnected by through-lines by receiving selection signals at the first terminals located on a first surface of the semiconductor chip, connecting each first terminal to a selected second terminal located on a second surface of the semiconductor chip where each selected second terminal is not aligned with the first terminal to which it is connected, and generating an internal signal based on a selected one of the received selection signals.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. application Ser. No. 13/740,689, filed Jan. 14, 2013, now U.S. Pat. No. 9,048,239, issued Jun. 2, 2015, which is a continuation of U.S. application Ser. No. 13/094,214, filed Apr. 26, 2011, now U.S. Pat. No. 8,907,463, issued Dec. 9, 2014, which is a continuation of U.S. application Ser. No. 12/759,198, filed Apr. 13, 2010, now U.S. Pat. No. 7,952,201, issued May 31, 2011, which is a continuation of U.S. application Ser. No. 11/418,094, filed May 5, 2006, now U.S. Pat. No. 7,745,919, issued Jun. 29, 2010, which claims priority to Japanese Application No. 2005-136659, filed May 9, 2005, the disclosures of which are incorporated herein in their entireties by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates to a semiconductor device comprising semiconductor chips stacked and, particularly, to a chip selection or designation technique. 
     Various techniques for chip selection or designation in multi-chip semiconductor device are known using a plurality of through-lines that are pierced through multiple chips. For example, known techniques are disclosed in U.S. Pat. No. 6,448,661 and U.S. Pat. No. 6,649,428, which are incorporated herein by reference in their entireties. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a new arrangement of a plurality of through-lines in a semiconductor device. 
     According to one aspect of the present invention, a semiconductor device comprises a plurality of semiconductor chips and a predetermined number of through-lines. Each of the through-lines constitutes an electrical path shared by the plurality of the semiconductor chips. The semiconductor chips are stacked along a predetermined direction. The through-lines are arranged in accordance with a predetermined configuration and are pierced through the semiconductor chips. The predetermined configuration is represented by a predetermined simple directed cycle in a plane perpendicular to the predetermined direction. The predetermined simple directed cycle consists of the predetermined number of nodes and the predetermined number of directed edges each of which connects two nodes among the predetermined number of the nodes. 
     An appreciation of the objectives of the present invention and a more complete understanding of its structure may be had by studying the following description of the preferred embodiment and by referring to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a view schematically showing a structure of a semiconductor device in accordance with a first embodiment of the present invention; 
         FIG. 2  is a table for use in describing an example of a chip selection or designation method; 
         FIG. 3  is a table for use in describing another example of a chip selection or designation method; 
         FIG. 4  is a view schematically showing a structure of an interface chip included in the semiconductor device of  FIG. 1 ; 
         FIG. 5  is a table showing an assertion rule which is used in a through-line assertion circuit included in the interface chip of  FIG. 4 ; 
         FIG. 6  is a view schematically showing an example of the through-line assertion circuit of  FIG. 4 ; 
         FIG. 7  is a view schematically showing another example of the through-line assertion circuit of  FIG. 4 ; 
         FIG. 8  is a view schematically showing through-lines in accordance with the first embodiment; 
         FIG. 9  is a view schematically showing a structure of a semiconductor chip of the first embodiment; 
         FIG. 10  is a view showing various types of simple directed cycle graphs; 
         FIG. 11  is a transparent view showing a part of a semiconductor chip according to a second embodiment of the present invention; 
         FIG. 12  is a transparent view showing another part of the semiconductor chip of  FIG. 11 ; 
         FIG. 13  is a transparent view showing a part of a semiconductor device of the second embodiment, wherein the semiconductor chips of  FIG. 11  are stacked; 
         FIG. 14  is a view schematically showing through-lines in accordance with the second embodiment; 
         FIG. 15  is a view schematically showing a structure of a semiconductor chip of the second embodiment; 
         FIG. 16  is a view schematically showing another structure of a semiconductor chip of the second embodiment; 
         FIG. 17  is a view schematically showing an identification generation circuit included in the semiconductor chip of a third embodiment; 
         FIG. 18  is a view schematically showing a signal generation circuit connected to the identification generation circuit of  FIG. 17 ; 
         FIG. 19  is a time chart showing an operation of the signal generation circuit of  FIG. 18 ; and 
         FIG. 20  is a view showing another identification generation circuit in accordance with a combination of the first and the third embodiments. 
     
    
    
     While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. 
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     A semiconductor device according to a first embodiment of the present invention is a dynamic random access memory (DRAM) device and comprises a plurality of DRAM chips  10 - 80  as a plurality of semiconductor chips and an interface chip  100 , as shown in  FIG. 1 . However, the present invention is not limited to the DRAM device but may be another semiconductor device comprising a plurality of semiconductor chips other than DRAM chips. 
     In the illustrated DRAM device, eight DRAM chips  10 - 80  are stacked on the interface chip  100 . The DRAM device is provided with a plurality of through-lines each of which is pierced through the DRAM chips  10 - 80  so that each through-line constitutes an electrical path shared by the DRAM chips  10 - 80 ; the through-lines are used for selecting, designating or identifying each DRAM chips  10 - 80 . 
     The through-lines are grouped into a plurality of through-line groups. Each through-line group consists of through-lines whose number is unique to the through-line group. The numbers of the through-lines belonging to the through-line groups are mutually “coprime” to each other. The term “coprime” is used in mathematical meaning and is equal to “relatively prime”; for example, two integers x and y are coprime or relatively prime if their greatest common divisor is 1. Likewise, if the greatest common divisor of integers x, y and z is 1, the integers x, y and z are coprime. 
     To be noted here that the number of possible combinations of coprime numbers is larger than the total number of the coprime numbers. Based on the relation in number, a larger number of semiconductor chips are distinguished designated by using a smaller number of through-lines, in accordance with the present embodiment. For example, seven through-lines are grouped into two through-line groups; one through-line group consists of four through-lines X 1 -X 4 , while the other consists of three through-lines Y 1 -Y 3 . If one through-line is selected for each through-line group and is asserted, the number of possible combinations of the asserted through-lines becomes twelve. Thus, the grouping of seven through-lines into four through-lines and three through-lines provides distinguishablity of twelve semiconductor chips, as shown in  FIG. 2 . Furthermore, if nine through-lines are grouped into two groups, four through-lines X 1 -X 4  and five through-lines Y 1 -Y 5 , twenty semiconductor chips become designatable by selecting and asserting one through-line for each through-line groups, as shown in  FIG. 3 . Likewise, if ten through-lines are grouped into three groups, 2, 3 and 5 through-lines, respectively, thirty semiconductor chips (30=2×3×5) become distinguishable. 
     In this embodiment, there are seven through-lines in total, and they are grouped into two through-line groups, through-lines X 1 - 4  and through-lines Y 1 -Y 3 . On the other hand, as mentioned above, there are eight DRAM chips  10 - 80 . In this embodiment, three bank addresses BA 0 , BA 1 , BA 2  are used for selection/designation of one DRAM chip among the DRAM chips  10 - 80 . In other words, the bank addresses serve as designation signals for designation of DRAM chips in this embodiment. 
     With reference to  FIG. 4 , the interface chip  100  comprises a through-line assertion circuit  110  operable in accordance with a truth table of  FIG. 5 ; the truth table defines the relation between the bank addresses BA 0 -BA 2  and the asserted through-lines X 1 -X 4  and Y 1 -Y 3 . The through-line assertion circuit  110  is adapted to select a combination of a through-line X 1 , X 2 , X 3  or X 4  and another through-line Y 1 , Y 2  or Y 3  on the basis of the bank addresses BA 0 -BA 2 , and to assert the selected combination. As understood from  FIG. 2 , there is a possibility of designation of twelve DRAM chips at maximum. Therefore, if there is a further bank address BA 3  and if the bank address BA 3  is also used for designation of DRAM chips, twelve DRAM chips can be distinguished by using seven through-lines X 1 -X 4  and Y 1 -Y 3 . In other words, the input number and/or the output number as to the through-line assertion circuit  110  are not limited to the present embodiment. 
     With reference to  FIG. 6 , there is shown an example of the through-line assertion circuit  110   a , which comprises a MOD3 circuit and a MOD4 circuit and a plurality of primitive elements or gates. The illustrated through-line assertion circuit  110   a  has an ability of twelve chip designation if the further bank address BA 3  is delivered to the MOD3 circuit and the MOD4 circuit. 
     With reference to  FIG. 7 , there is shown another example of the through-line assertion circuit  110   b , which consists of a smaller number of primitive gates. The illustrated through-line assertion circuit  110   b  is able to designate only eight chips. 
     With reference to  FIGS. 8 and 9 , the DRAM chips  10 - 80  have terminals arranged in accordance with the same configuration; in  FIGS. 8 and 9 , each terminal is depicted with  4 A,  4 B,  4 C or  4 D and its subscript of a layer number of the DRAM chip to which the terminal belongs. As apparent from  FIGS. 8 and 9 , the terminals  4 A 1 - 4 A 8 ,  4 B 1 - 4 B 8 ,  4 C 1 - 4 C 8 , and  4 D 1 - 4 D 8  are arranged in accordance with a rectangular configuration in each DRAM chip  10 - 80 , and each of the through-lines X 1 -X 4  extends in a straight form. Similarly, other terminals associated with the other group of the through-lines Y 1 -Y 3  are arranged in accordance with a triangular configuration in each DRAM chip  10 - 80 , and each of the through-lines Y 1 -Y 3  extends in a straight form. 
     Because the through-lines have the straight forms, the asserted terminals corresponding to each DRAM chip  10 - 80  are different from those of the other DRAM chips, as shown in  FIG. 9 . Therefore, each of the DRAM chip  10 - 80  has an internal signal generation circuit  11 ,  21 ,  31  which is adapted to generate an internal signal  11   a ,  21   a ,  31   a  on the basis of the unique combination of the asserted terminals for each DRAM chip, wherein the internal signal  11   a ,  21   a ,  31   a  is indicative of selection of the DRAM chip where the internal signal generation circuit  11 ,  21 , is provided. In other words, the DRAM chips  10 - 80  require layer-specific internal signal generation circuits so that the DRAM chips  10 - 80  have different structures than each other. For example, the internal signal generation circuit  11  provided for the DRAM chip  10  is connected to the terminals  4 A 1  and  3 A 1 ; the internal signal generation circuit  21  provided for the DRAM chip  20  is connected to the terminals  4 A 2  and  3 A 2 ; and the internal generation circuit  31  provided for the DRAM chip  30  is connected to the terminals  4 A 3  and  3 A 3 . 
     A DRAM device according to a second embodiment of the present invention is a modification of the DRAM device of the first embodiment. The DRAM device of the second embodiment comprises an interface chip and a plurality of DRAM chips, wherein the interface chip is the same one as that of the first embodiment, while the DRAM chips are different from those of the first embodiment and have the same structure as each other, as described in detail below. 
     In the following description, the terminology in graph theory is used; the words are briefly explained here. A cycle is a word used in graph theory and is a closed path whose start node and end node are the same. A directed cycle consists of nodes and directed edges or arcs. In other words, a directed cycle includes no undirected edges; all nodes included in the simple directed cycle are ordered. A simple directed cycle is a directed cycle with no repeated nodes. In other words, the number of nodes is equal to the number of directed edges in a simple directed cycle. 
     Various simple directed cycles are illustrated in  FIG. 10 . The first one has two nodes  2 A and  2 B. The second one has three nodes  3 A- 3 C. In theory, the third one is also a simple directed cycle in which the nodes  5 A,  5 E,  5 B,  5 D,  5 C are repeatedly ordered in this order. Furthermore, the fourth one is a simple directed cycle, too, wherein the nodes  5 A- 5 C are physically arranged on a common straight line. 
     With reference to  FIG. 11 , each of the DRAM chips comprises components constituting the through-lines X 1 -X 4 . In detail, each DRAM chip has lower and upper surfaces and comprises four lower terminals  4 A- 4 D, four upper terminals  4 A′- 4 D′ and four connection portions. The lower terminals  4 A- 4 D are formed on the lower surface of the DRAM chip. On the other hand, the upper terminals  4 A′- 4 D′ are formed on the upper surface of the DRAM chip. The lower terminals  4 A- 4 D are arranged in correspondence with the upper terminals  4 A′- 4 D′, respectively. In other words, the upper terminals  4 A′- 4 D′ are arranged above the lower terminals  4 A- 4 D, respectively. However, the upper terminals  4 A′,  4 B′,  4 C′,  4 D′ are not connected to the lower terminals  4 A,  4 B,  4 C,  4 D, respectively, but are connected by the connection portions  4 B″,  4 C″,  4 D″,  4 A″ to the lower terminals  4 B,  4 C,  4 D,  4 A, respectively, as shown in  FIG. 11 . In other words, there is a simple directed cycle which circulates according to the order “ 4 D- 4 C- 4 B- 4 A- 4 D”, and each of the connection portions  4 B″,  4 C″,  4 D″,  4 A″ connects one of the lower terminals  4 B,  4 C,  4 D,  4 A and one of the upper terminals  4 A′,  4 B′,  4 C′,  4 D′ in accordance with one of the directed edges  150 . The first directed edge  151  corresponding to the connection portion  4 B″ has start and end nodes which correspond to the lower terminal  4 B and the upper terminal  4 A′, respectively. The second directed edge  152  corresponding to the connection portion  4 C″ has start and end nodes which correspond to the lower terminal  4 C and the upper terminal  4 B′, respectively. The directed edge corresponding to the connection portion  4 D″ has start and end nodes which correspond to the lower terminal  4 D and the upper terminal  4 C′, respectively. The directed edge corresponding to the connection portion  4 A″ has start and end nodes which correspond to the lower terminal  4 A and the upper terminal  4 D′, respectively. 
     Likewise, each of the DRAM chips further comprises components constituting the through-lines Y 1 -Y 3 , as shown in  FIG. 12 . In detail, each DRAM chip further comprises three lower terminals  3 A- 3 C, three upper terminals  3 A′- 3 C′ and three connection portions  3 A″- 3 C″. The lower terminals  3 A- 3 C are formed on the lower surface of the DRAM chip. On the other hand, the upper terminals  3 A′- 3 C′ are formed on the upper surface of the DRAM chip. The lower terminals  3 A- 3 C are arranged in correspondence with the upper terminals  3 A′- 3 C′, respectively. The upper terminals  3 A′,  3 B′,  3 C′ are connected by the connection portions  3 B″,  3 C″,  3 A″ to the lower terminals  3 B,  3 C,  3 A, respectively, as shown in  FIG. 12 . In other words, there is a simple directed cycle which circulates according to the order “ 3 C- 3 B- 3 A- 3 C”, and each of the connection portions  3 B″,  3 C″,  3 A″ connects one of the lower terminals  3 B,  3 C,  3 A and one of the upper terminals  3 A′,  3 B′,  3 C′ in accordance with one of the directed edges. The directed edge corresponding to the connection portion  3 B″ has start and end nodes which correspond to the lower terminal  3 B and the upper terminal  3 A′, respectively. The directed edge corresponding to the connection portion  3 C″ has start and end nodes which correspond to the lower terminal  3 C and the upper terminal  3 B′, respectively. The directed edge corresponding to the connection portion  3 A″ has start and end nodes which correspond to the lower terminal  3 A and the upper terminal  3 C′, respectively. 
     As shown in  FIG. 13 , the DRAM chips with the above-mentioned structures are stacked so that the through-lines X 1 -X 4  as well as the through lines Y 1 -Y 3  are formed as shown in  FIG. 14 . In detail, the DRAM chip  20  is stacked on the DRAM chip  10  so that the lower terminals  4 A 2 - 4 D 2  of the DRAM chip  20  are mounted and connected to the upper terminals  4 A′ 1 - 4 D′ 1  of the DRAM chip  10 ; the lower terminals  4 A 3 - 4 D 3  of the DRAM chip  30  are connected to the upper terminals  4 A′ 2 - 4 D′ 2  of the DRAM chip  20 ; the lower terminals  4 A 4 - 4 D 4  of the DRAM chip  40  are connected to the upper terminals  4 A′ 3 - 4 D′ 3  of the DRAM chip  30 . Thus, the through-lines X 1 -X 4  are formed by the lower terminals  4 A n - 4 D n , the upper terminals  4 A′ n - 4 D′ n  and the connection portions  4 A″ n - 4 D″ n . The other through-lines Y 1 -Y 3  are also formed simultaneously upon the stacking the DRAM chips. 
     Thus obtained through-lines X 1 -X 4  have helix forms, respectively, as shown in  FIG. 14 . Especially, each of the helix form is a polygonal helix. In detail, a polygon is a closed planar path composed of a finite number of sequential line segments. The straight line segments that make up the polygon are called its sides or edges and the points where the sides meet are the polygon&#39;s vertices. A simple polygon is a polygon that has a single, non-intersecting boundary. A polygonal helix is a helix that has a polygon form as seen along its helical axis. 
     With reference to  FIG. 15 , the DRAM chips  10 ,  20 ,  30  have the same structure as each other. In detail, the DRAM chips  10 ,  20 ,  30  have the same structured internal signal generation circuits  12 ,  22 ,  32  adapted to generate an internal signals  12   a ,  22   a ,  32   a , respectively. 
     To be noted here that in this embodiment, each of the through-lines X 1 -X 4 , Y 1 -Y 3  does not have a straight form and passes through the terminals corresponding to the different positions on the DRAM chips, respectively, as shown in  FIGS. 14 and 15 . For example, the through-line X 1  passes through the terminal  4 A 1  of the DRAM chip  10 , the terminal  4 D 2  of the DRAM chip  20  and the terminal  4 C 3  of the DRAM chip  30 ; the through-line X 2  passes through the terminal  4 B 1  of the DRAM chip  10 , the terminal  4 A 2  of the DRAM chip  20  and the terminal  4 D 3  of the DRAM chip  30 ; the through-line X 3  passes through the terminal  4 C 1  of the DRAM chip  10 , the terminal  4 B 2  of the DRAM chip  20  and the terminal  4 A 3  of the DRAM chip  30 ; and the through-line X 4  passes through the terminal  4 D 1  of the DRAM chip  10 , the terminal  4 C 2  of the DRAM chip  20  and the terminal  4 B 3  of the DRAM chip  30 . Likewise, the through-line Y 1  passes through the terminal  3 A 1  of the DRAM chip  10 , the terminal  3 C 2  of the DRAM chip  20  and the terminal  3 B 3  of the DRAM chip  30 ; the through-line Y 2  passes through the terminal  3 B 1  of the DRAM chip  10 , the terminal  3 A 2  of the DRAM chip  20  and the terminal  3 C 3  of the DRAM chip  30 ; and the through-line Y 3  passes through the terminal  3 C 1  of the DRAM chip  10 , the terminal  3 B 2  of the DRAM chip  20  and the terminal  3 A 3  of the DRAM chip  30 . 
     With reference to  FIGS. 5, 14 and 15 , each of the DRAM chips is designated or selected when the combination of the terminals  4 A n  and the terminal  3 A n  is asserted, where n is integer of 1 to 8 and corresponds to a layer number of the DRAM chip  10 - 80 . The terminals  4 A n  and the terminal  3 A n  are referred to as specific terminals. The specific terminals  4 A n  and  3 A n  are positioned at particular vertices on the rectangle configuration and the triangle configuration, respectively. On each DRAM chip  10 ,  20 ,  30 , the internal signal generation circuit  12 ,  22 ,  32  is coupled to the specific terminals  4 A n  and  3 A n  and is adapted to generate the internal signal  12   a ,  22   a ,  32   a  based on the specific terminals  4 A n  and  3 A n . In this embodiment, the internal signal generation circuits  12 ,  22 ,  32  are also connected to the terminals  4 B n - 4 D n  and the terminals  3 B n  and  3 C n  in the same manner for every DRAM chip. The thus-structured internal signal generation circuit  12 ,  22 ,  32  does not generate the internal signal  12   a ,  22   a ,  32   a  when the terminal  4 B n - 4 D n  or the terminal  3 B n ,  3 C n  is asserted even if the specific terminals  4 A n  and  3 A n  is asserted. Thus, the internal signal generation circuits  12 ,  22 ,  32  can prevent incorrect actions and have high-reliability. 
     The internal signal generation circuits  13 ,  23 ,  33  can be simplified as shown in  FIG. 16 . wherein each of the internal signal generation circuits  13 ,  23 ,  33  is connected only to the specific terminals  4 A n  and  3 A n  and is adapted to generate the internal signal only on the basis of the monitoring results of the specific terminals  4 A n  and  3 A n . 
     A DRAM device according to a third embodiment of the present invention comprises a different interface chip which a through-line assertion circuit is not provided for and, when the DRAM device is used, one of the through-lines X 1 -X 4  and one of the through-lines Y 1 -Y 3  are fixedly asserted. In this embodiment, only the through-line X 1  and the through-line Y 1  are fixedly asserted, for example, by supplying the through-line X 1  and the through-line Y 1  with VDD, while by supplying the through-line X 2 -X 4  and the through-line Y 2 , Y 3  with GND. In this case, because the combination of the asserted terminals is unique to each DRAM chips, the DRAM chip can acknowledge its layer number by checking the combination of the asserted terminals. 
     With reference to  FIG. 17 , an identification generation circuit  105  is provided for each DRAM chip. The identification generation circuit  105  is connected to the terminals  4 A- 4 D and the terminals  3 A- 3 C. The identification generation circuit  105  is adapted to generate an identification signal ID 1 -ID 8  on the basis of the combination of the asserted terminals  4 A- 4 D,  3 A- 3 C, wherein the identification signal ID 1 -ID 8  is indicative of the layer number of the DRAM chip. 
     With reference to  FIG. 18 , a signal generation circuit  106  comprises a p-ch transistor  106   b , two-inputs NAND circuits  106   c , eight in number, and a latch circuit  106   d . The p-ch transistor  106   b  is connected between the power supply and the point  106   a  and is used for pre-charging the point  106   a  in response to a pre-charge signal α. The pre-charge signal α is changed into low state when the point  106   a  is to be pre-charged. Each of the NAND circuits  106   c  is connected between the point  106   a  and the ground (GND). The latch circuit  106   d  holds a level of the point  106   a  and transmits the level to an internal signal line  106   e.    
     One of the inputs for each NAND circuits  106   c  is a corresponding one of the identification signals ID 1 -ID 8 ; the other is a layer designation signal indicative of a layer number of the DRAM chip to be designated. The layer designation signal is shown as BA 0 N 1 N 2 N, BA 0 T 1 N 2 N, BA 0 N 1 T 2 N, BA 0 T 1 T 2 N, BA 0 N 1 N 2 T, BA 0 T 1 N 2 T, BA 0 N 1 T 2 T, or BA 0 T 1 T 2 T, where “N” indicates “NOT” (=false:0), while “T” indicates “TRUE” (=1). For example, if only the first layer DRAM chip is to be designated, the layer designation signal BA 0 N 1 N 2 N is asserted, while the other layer designation signals are negated. Likewise, if only the second layer DRAM chip is to be designated, the layer designation signal BA 0 T 1 N 2 N is asserted, while the other layer designation signals are negated. The layer designation signals are obtained by decoding the encoded designation signals, i.e. the bank signals BA 0 -BA 2  in this embodiment. The decoding may be carried out by the interface chip or by each DRAM chip. 
     With further reference to  FIG. 19 , explanation is made about an operation of the signal generation circuit  106  which is embedded in the first layer DRAM chip  10 . The identification generation circuit  105  of the DRAM chip  10  generates ID 1  of low level and ID 2 -ID 8  of high levels. Before the chip selection/designation, the pre-charge signal α is asserted so that the point  106   a  is pre-charged to have the high level. The pre-charged level is held by the latch circuit  106   d  and is transmitted to the internal signal line  106   e . Under that state, when the first layer DRAM chip  10  is designated with the asserted layer designation signal BA 0 N 1 N 2 N, the corresponding NAND circuit  106   c  turns ON so that the level of the point  106   a  is changed into the low level. The change of the point  106   a  is transmitted to the internal signal line  106   e . Thus, the illustrated internal signal generation circuit  106  asserts the internal signal line  106   e  only upon the match between the layer number of the identification signal and the designated layer number. 
     The preferred embodiments described above can be modified in various manner. For example, the conceptual combination of the first and the third embodiments allows the DRAM chips to have the same structure as each other even if each of the through-lines has a straight form as shown in  FIG. 8 .  FIG. 20  shows an example of another identification generation circuit  105   a  which allows the conceptual combination of the first and the third embodiments. The DRAM chips can have the same structure as each other; each of the DRAM chips comprises the identification generation circuit  105   a  shown in  FIG. 20  and internal signal generation circuit  106  shown in  FIG. 18 . In the preferred embodiments, the through-lines are grouped into two or more groups but may form only a single group. In the preferred embodiments, the bank addresses are used as designation signals, but other signals including a chip-select signal may be used. In the preferred embodiment, only one DRAM chip is designated, but two or more DRAM chips can be designated simultaneously, as apparent from their structures. 
     While there has been described what is believed to be the preferred embodiment of the invention, those skilled in the art will recognize that other and further modifications may be made thereto without departing from the sprit of the invention, and it is intended to claim all such embodiments that fall within the true scope of the invention.