Abstract:
A method and apparatus for converting an N-bit digital word to an analog voltage signal. A first circuit converts the MSBs of the N-bit word and a second circuit converts the LSBs. The first circuit includes a resistor array in series between reference nodes and a switch matrix providing a node voltage to a first buffer input responsive to an indication of the MSBs of the N-bit word wherein the buffer output provides the analog voltage signal. The second circuit includes a current device electrically isolated from the resistors of the first circuit and coupled to a second buffer input which is further coupled in a feedback arrangement with the buffer output. The current device provides a select current whereby the resistance of the feedback loop and the select current are cooperably modify the analog voltage signal incrementally corresponding to the LSBs of the N-bit digital word.

Description:
BACKGROUND OF THE INVENTION 
     1. Technical Field of the Invention 
     The present invention relates to a digital-to-analog converter and, more particularly, to a resistor string digital-to-analog converter. 
     2. Description of Related Art 
     String digital-to-analog converters (DAC) are a type of DAC that includes a plurality of resistors connected in series between a high and low supply voltage. Connecting nodes or tap points between the resistors are selectively switched to an output node in response to the digital input. The resistor string acts as a large voltage divider with each tap point of the string being at a different voltage value. A switch matrix selects one of the tap points to the output node depending on the digital word input to the DAC. The voltage of the tap point is a monotonic analog representation of the digital input. 
     Referring now to FIG. 1 there is illustrated a prior art 3-bit resistor string DAC which consists of 2 3  or 8 resistors connected in series between two reference voltages. The lower node of each resistor is selectively switched by the switch matrix to the input of the output buffer in response to a decoded digital input word. Thus, the input voltage to the output buffer is the voltage drop across the associated resistive elements of the resistor string in which the voltage drop across each resistor is VRP-VRN/8. 
     Generally, an N-bit resistor string DAC consists of 2 resistors and the number of switches range from 2 N  to 2(2 N )-2, depending on the complexity of the decoder. For example, a 10-bit DAC would require 1024 resistors and 1024 tap points with 1024 associated switches. This type of DAC, however, suffers from the spacing requirements. Because of the spacing requirement for such a large number of resistors and switches, this DAC arrangement is particularly impractical for eight bit applications and larger. Not only does the die area increase rapidly with the number of bits, but the speed is also limited by the parasitic capacitances associated with the large number of switches. 
     One approach to reduce the number of resistors and switches in a string DAC is described in U.S. Pat. No. 5,808,576, issued Sep. 15, 1998, entitled “Resistor String Digital-To-Analog Converter”. Here, the resistor string is partitioned into a most significant bit (MSB) portion and a least significant bit (LSB) portion in which the LSB portion comprises a pair of variable resistors with one located on the top portion of the MSB portion and the other located on the lower portion of the MSB portion. 
     In the 576 patent, the values of the resistor bank can be shifted up or down by switching in the variable resistors. However, the variable resistors are also realized as resistor banks. Although this approach offers significant advantages over the conventional approach, a superior DAC can be realized by isolating the MSB and LSB portions and by further reducing the number of resistors and associated switches. 
     SUMMARY OF THE INVENTION 
     The present invention achieves technical advantages as a method and apparatus for converting an N-bit digital word to an analog voltage signal in which a first circuit provides for conversion of the most significant bits of the N-bit digital word and a second circuit provides for the conversion of the least significant bits. The first circuit includes an array of resistors coupled in series between reference nodes and a switch matrix for providing a node voltage to a first input of a buffer responsive to an indication of the most significant bits of the N-bit digital word in which the buffer output provides the analog voltage signal. The second circuit includes a current device electrically isolated from the resistors of the first circuit and coupled to a second input of the buffer in which the second input is coupled in a feedback arrangement with the buffer output. The current device is operable to provide a select current such that the resistance of the feedback loop and the current are cooperable to modify the analog voltage signal by an amount corresponding to the least significant bits of the N-bit digital word. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention, reference is made to the following detailed description taken in conjunction with the accompanying drawings wherein: 
     FIG. 1 illustrates a conventional string digital-to-analog converter; 
     FIG. 2 illustrates another conventional string digital-to-analog converter; 
     FIG. 3 illustrates the LSB resistor banks of the conventional string digital-to-analog converter illustrated in FIG. 2; 
     FIG. 4 illustrates a resistor string DAC in accordance with an exemplary embodiment of the present invention; 
     FIG. 5 illustrates a graph of simulated results for the DAC illustrated in FIG. 4; and 
     FIGS. 6A and 6B illustrate[s] an electrical schematic for an 8-bit DAC in accordance with an exemplary embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The numerous innovative teachings of the present application will be described with particular reference to the presently preferred exemplary embodiments. However, it should be understood that this class of embodiments provides only a few examples of the many advantageous uses and innovative teachings herein. In general, statements made in the specification of the present application do not necessarily delimit any of the various claimed inventions. Moreover, some statements may apply to some inventive features, but not to others. 
     Throughout the drawings, it is noted that the same reference numerals or letters will be used to designate like or equivalent elements having the same function. Detailed descriptions of known functions and constructions unnecessarily obscuring the subject matter of the present invention have been omitted for clarity. 
     For an 8-bit resistor string DAC, prior analog architectures generally have 2 8  elements, each one representing a bit of information. This requires 256 resistors and 256 switches in order to bring each of the associated analog outputs to an amplifier for output. A problem with this type of architecture is that such a large number of elements requires a large amount of space. One improved approach is to partition the design between two sets of different weighted elements as described in U.S. Pat. No. 5,808,576, issued Sep. 15, 1998, entitled “Resistor String Digital-To-Analog Converter”, the description of which is hereby incorporated by reference. 
     Here, as shown in FIG. 2, the resistor string is partitioned into a most-significant-bit (MSB) portion (i.e. resistor string  10 - 16 ) and a least-significant-bit (LSB) portion (i.e. variable resistors RTOP and RBOT) with reference voltages VRP and VRN applied at the ends. A switch matrix  20  selects one of the node voltages to an input of an output buffer  22 . LSB elements RTOP and RBOT are operable to shift the voltage of the MSB resistor string up or down by a voltage defined by the digital bits which are mapped to their appropriate LSB segments. This is done such that the voltage difference between the top and bottom of the MSB resistor string remains constant. This shifting while maintaining constant difference is achieved by connecting an LSB segment in the RTOP (FIG. 3) at the same time one is disconnected in the RBOT (or vice versa), thus maintaining a constant total resistance for all digital codes. 
     LSB elements RTOP and RBOT are realized as respective resistor banks, as shown in the 576 patent and reproduced here as FIG.  3 . With this described approach, the number of resistors used in the DAC can be reduced to less than half of prior designs. However, with this approach, only one of the LSB elements RTOP and RBOT are used at any one time while the other one sits with no effect. 
     An improved DAC can be realized by eliminating the resistors of the LSB elements RTOP and RBOT and the associated switches. For example, in an 8-bit DAC with a 5-3 partitioned architecture (i.e. 5 MSB weighted bits and 3 LSB weighted bits) generally includes 56 unit resistors and switches in the LSB resistor banks. The switches in the ground signal path in these resistor banks arrangements tend to be large to minimize associated thermal drift problems. The resistors of LSB elements RTOP and RBOT are eliminated in accordance with an embodiment of the present invention, without sacrificing resolution, by adjusting the voltage of the output amplifier via a controlled current. In accordance with the present invention, switches are eliminated in the resistor path between voltage reference and ground altogether, completely eliminating their contribution to drift over temperature. In the past, the ground side switches have been NMOSFETS as large as 100 μm wide and 0.8 μm long. 
     Referring now to FIG. 4 there is illustrated a modified partitioned resistor string DAC in accordance with an exemplary embodiment of the present invention. The LSB portion (i.e. current device  430 ) of the DAC is electrically separated or isolated from the MSB portion (i.e. resistor string  410 ) in which the gain amplifier  420  (output buffer) enables sensing of the tapped voltage from the MSB resistor string  410  for application of a corresponding output without drawing current from any of the resistors. The MSB resistor string  410  also includes a switch matrix for selecting the appropriate voltage. In addition, the MSB resistor string  410  can include a decoder  620  (see FIGS. 6A and 6B) for selecting the appropriate switches responsive to a signal indicative of the most significant bits of the digital word. 
     A positive terminal of the gain amplifier  420  is coupled to the MSB resistor string tap (V TAP ), and resistors R 1  and R 2  enable feedback around the amplifier  420 . R 1  is connected between the output (V OUT ) and the negative input (V X ) of the amplifier  420 . R 2  is connected between V X  and electrical ground and current device  430  is coupled to V X . It is worth noting that the 576 patent and other conventional approaches do not use the negative terminal for conversion of the digital signal. 
     Current device  430  is operable to enable the LSB process of the differential in the analog conversion by controllably forcing current into or out of V X  advantageously adjusting V OUT  for each MSB resistor tap. Current device  430  receives a signal indicative of the LSBs of an N-bit digital word to be converted and, in response, applies a corresponding current into the feedback loop of the output amplifier. Further, current device  430  comprises a number of current sources (I 0 ) coupled in parallel and connected to a positive supply in which the current sources I 0  are either switched in or switched out to node V X . The switches for the current sources (see item  430  of FIGS. 4, [and]  6 A and  6 B) switch current into a virtual ground, and their resistance effect is negligible. In one embodiment of the present invention, these switched are PMOSFETS which are 2 μm wide and 0.4 μm long. Current device  430  can also include a decoder circuit  610  (see FIGS. 6A and 6B) for selecting current sources I 0  responsive to the LSB signal. 
     In accordance with the present invention, an 8-bit partitioned DAC, for example, has 3-bits assigned to the LSB portion and at least 2 L −1 corresponding current sources I 0  in which L is the number of bits assigned to the LSB portion of the DAC. Thus, 2 3 −1 or 7 current sources I 0  are used in this 8-bit DAC. The current sources I 0  can include MOS devices and, more particularly, PMOS devices (see FIGS.  6 A and  6 B). PMOS devices and their associated switches are small compared to resistor elements and their associated switches. 
     The current sources I 0  are matched, in other words, the current sources each provide an approximately equal amount of current (I LSB ). The value of I LSB  and R 1  are chosen such that the current from one source passing through resistor R 1  equals an LSB of voltage change. For the 5-3 partitioned 8-bit DAC, I LSB ×R 1 =LSB which is approximately equal to ⅛ th the drop across an MSB resistor (R 0 ). The ratio of R 1  and (R 1 +R 2 ) form the feedback factor found in classic control theory. The closed loop gain of the amplifier in this non-inverting configuration is 1+R 1 /R 2  as can be found in current textbooks on electronic design. 
     Assuming the voltage at V TAP  is equal to V X , which is the standard assumption made for a high gain amplifier such as amplifier  420 , the closed form expression for Vout can be calculated as follows: 
     
       
           V   TAP   =V   X , 
       
     
     
       
         
           
             
               
                 
                   
                     
                       V 
                       OUT 
                     
                     - 
                     
                       V 
                       X 
                     
                   
                   
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                     1 
                   
                 
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                   LSB 
                 
               
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                   X 
                 
                 
                   R 
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                       OUT 
                     
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                       TAP 
                     
                   
                   
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                   LSB 
                 
               
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                     LSB 
                   
                 
               
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                         1 
                       
                       
                         R 
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                  
                 
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             where 
           
         
         
           
             
               V 
               OUT 
             
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                   ( 
                   
                     
                       
                         R 
                         1 
                       
                       
                         R 
                         2 
                       
                     
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                   R 
                   1 
                 
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                     I 
                     LSB 
                   
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     Further, because the reference amplifier is not isolated from the LSB switching in the prior string DACs, it suffers from transient load changes during switching, which limits code transition speed and DAC settling. With the present design, the reference amplifier  440  is completely isolated from the LSB switching of current device  430  because currents are injected into the negative feedback node V X  of the gain amplifier  420  rather than through any resistors that are seen in the output path of the reference amplifier  440 . 
     Referring now to FIG. 5 there is shown a graphical representation of simulated results for the 8-bit DAC. As the digital input code is changed over time, an analog waveform is received at the output. The analog waveform is plotted on the Y-axis and labeled “volts”. Since the digital code is changed as a function of time, the X-axis, rather than representing digital code, is labeled time and in this case milliseconds. A DAC with good characteristics should exhibit a linear sweep at the output for a linear sweep of the digital code at the input. FIG. 5 generally illustrates that the analog output corresponds to approximately a 1-for-1 output with the digital input. 
     Although a preferred embodiment of the method and system of the present invention has been illustrated in the accompanied drawings and described in the foregoing Detailed Description, it is understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications, and substitutions without departing from the spirit of the invention as set forth and defined by the following claims.