Abstract:
The invention provides methods and apparatus for improving the direct current (DC) offset performance of an oversampling analog-to-digital (A/D) converter, including A/D converters that include an oversampling quantizer such as a single or multi-bit Δ-Σ modulator, successive approximation quantizer, flash quantizer, pipelined quantizer or other suitable oversampling quantizer. The invention also relates to methods for providing a wide-band attenuation in the digital output of an A/D converter using a limited number of components.

Description:
FIELD OF THE INVENTION 
     The present invention relates to oversampling analog-to-digital converters. More particularly, the present invention relates to methods and apparatus for improving the direct current (DC) offset and offset drift performance of an oversampling analog-to-digital converter. 
     BACKGROUND OF THE INVENTION 
     Converting a continuous-time analog signal to a discrete-time digital representation typically requires anti-alias filtering, sampling and quantization. An anti-aliasing filter ensures that analog input signal is properly band-limited prior to sampling. A sampler captures samples of the filtered input signal at discrete time intervals T=1/F s , where F s  is the sampling frequency. Sampling frequency F s  typically is selected as at least twice the bandwidth of the filtered analog input signal. A quantizer converts the samples to a discrete set of values. Conventional analog-to-digital (A/D) converters typically perform sampling and quantization, whereas separate discrete components or integrated circuits perform anti-aliasing. 
     Oversampling A/D converters, in contrast, sample an analog input signal at a rate NF s  that is many times greater than twice the bandwidth of the analog input signal. An oversampling converter typically includes an anti-alias filter, a sampler and modulator (quantizer), and a digital filter. The sampler and quantizer operate at the elevated rate NF s . The digital filter, typically called a decimator, provides low-pass filtering to suppress signals above F s /2, and sample-rate reduction to lower the sample rate to the desired rate F s . As a result of the higher input sampling rate, over-sampling converters have less stringent anti-alias filter requirements than traditional converters. In addition, oversampling converters permit lower quantization noise power, and hence improved signal-to-noise ratio compared to traditional converters. 
     One key requirement for oversampling A/D converters is low DC offset. If the input to an oversampling A/D converter is zero (e.g., 0 volts), the output of the converter ideally is a digital code corresponding to zero. As a result of component mismatches, however, the output of a real A/D converter to a zero input is a digital code that corresponds to a value other than zero. The magnitude of the converter&#39;s input-referred DC offset is the magnitude of the DC input signal that causes the A/D converter to produce a zero output. The DC offset of the converter may vary with time and temperature. This phenomenon typically is called “offset drift.” Another key requirement for oversampling A/D converters is low offset drift with time and temperature. 
     Previously known techniques have been used to improve the DC offset performance of A/D converters. For example, Donald A. Kerth et al., “An Oversampling Converter for Strain Gauge Transducers,” IEEE J. Solid State Circuits, 27(12):1689-96 (December 1992), describes an oversampling Δ-Σ A/D converter architecture that uses chopper-stabilized amplifiers to substantially reduce the overall DC offset of the converter. Nevertheless, the non-ideal chopper amplifier switches contribute DC offset and offset drift proportional to the chopper frequency, which corresponds to the relatively high sampling frequency of the Δ-Σ modulator. Although digital calibration techniques may be used to remove residual DC offset, such techniques are ineffective for correcting offset drift. Further, to increase the converter&#39;s resolution, the sampling frequency of the Δ-Σ modulator may be increased. Such increases, however, require that the chopper frequency also must increase, which increases residual offset and offset drift. 
     An improved offset performance A/D converter is described in Damien McCartney et al., “A Low-Noise Low Drift Transducer ADC,” IEEE J. Solid State Circuits, 32(7):959-967 (July 1997) (“McCartney”). The architecture of the McCartney converter is shown in FIG.  1 . Converter  10  includes analog chopper  12 , buffer amplifier  14 , Δ-Σ modulator  16 , digital chopper  18 , Sinc 3  filter and decimator  20 , and FIR filter  22 . Analog chopper  12  chops analog input signal V IN  with a square wave of frequency f chop . For example, as described by McCartney, if V IN  is a differential signal, analog chopper  12  may be implemented as a multiplexer that successively reverses the polarity of V IN . Buffer amplifier  14  isolates the chopped analog input signal from the succeeding switched capacitor circuitry, and may provide adjustable gain. Δ-Σ modulator  16  samples the output of buffer amplifier  14  at a frequency f mod  that is much higher than chop frequency f chop , and provides a digital data stream at its output. For example, f mod =2×N×f chop , where N is the oversampling ratio of Δ-Σ modulator  16 . Digital chopper  18  is phase-synchronized with analog chopper  12 , and chops the digital data output of Δ-Σ modulator  16  to provide a digital data steam at a rate f mod . Sinc 3  filter and decimator  20  filter and decimate the output data stream of digital chopper  18  to provide a digital stream x (n) at a rate f mod /N. 
     If chopper frequency f chop  equals f mod /(2×N), then successive samples x(n) provided at the output of Sinc 3  filter and decimator  20  are digital representations of the analog signals (V IN +V OS ) and (V IN −V OS ), where V OS  is the input-referred offset of buffer amplifier  14  and Δ-Σ modulator  16 . For example, x(n) for n=0, −1, −2, 3, −4, may be expressed as: 
     
       
           x (0)=( V   IN (0)+ V   OS (0) 
       
     
     
       
           x (−1)=( V   IN (−1)− V   OS (−1)) 
       
     
     
       
           x (−2)=( V   IN (−2)+ V   OS (−2)) 
       
     
     
       
           x (−3)=( V   IN (−3)− V   OS (−3)) 
       
     
     
       
           x (−4)=( V   IN (−4)+ V   OS (−4))  (1) 
       
     
     where V IN (n), n=0, −1, −2, −3, −4, . . . , are samples of input signal V IN , and V OS (n), n=0, −1, −2, −3, −4, . . . , are samples of input-referred offset V OS . 
     FIR filter  22  removes V OS  from output x(n) of Sinc 3  filter and decimator  20  and provides digital output signal y(n) at rate f chop . If FIR filter  22  has L coefficients h(n), n=0, 1, 2, . . . , L−1, output y(n) may be expressed as:                y        (   n   )       =       ∑     k   =   0       L   -   1                         h        (   k   )       ×     (     n   -   k     )                 (   2   )                                
     For example, if L=2, output y(n) may be expressed as: 
     
       
           y ( n )= h (0) x ( n )+ h (1) x ( n− 1)  (3) 
       
     
     For n=0, y(0) equals:                      y        (   0   )                  =         h        (   0   )       ×     (   0   )       +       h        (   1   )       ×     (     -   1     )                                  =       h        (   0   )            [         V   IN          (   0   )       +       V   OS          (   0   )         ]                       (     4      a     )                            +       h        (   1   )            [         V   IN          (     -   1     )       -       V   OS          (     -   1     )         ]                 (     4      b     )                                
     If f chop  is many times higher than twice the bandwidth of V IN  and V OS , then 
     
       
           V   IN (0)≈ V   IN (−1)  (5a) 
       
     
     
       
           V   OS (0)≈ V   OS (−1)  (5b) 
       
     
     Ideally, y(n) contains no offset V OS , such that 
     
       
           y ( n )= V   IN  ( n )  (6) 
       
     
     Combining equations (4b), (5) and (6), impulse response coefficients h(0)=+0.5 and h(1)=+0.5. 
     An alternative embodiment of the converter of FIG. 1 is shown in FIG.  2 . Circuit 30 includes excitation source  32 , analog chopper  34 , sensor  36  and A/D converter  38 . Excitation source provides analog excitation input signal E IN , and sensor  36  may be, for example, a resistor bridge strain gauge used in an industrial weigh scale. Analog excitation input signal E IN  typically is a DC signal. Analog chopper  34  chops analog excitation input signal E IN , and provides the chopped signal to resistor bridge  36 . The analog output of resistor bridge  36  is the input to A/D converter  38 . A/D converter  38  includes chop synch  40 , which provides analog chopper  34  with a clock signal of the correct polarity and phase to synchronize analog chopper  34  to A/D converter  38 . By including sensor  36  in the chop loop, circuit  30  removes offsets in sensor  36  caused by thermal electromotive force (EMF) or leakage current. As described by McCartney, Δ-Σ modulator  16  may be implemented as a 1-bit Δ-Σ modulator, and digital chopper  18  may be implemented as an exclusive-OR gate. 
     To provide lower quantization error, it may be desirable to implement Δ-Σ modulator  16  as a multi-bit Δ-Σ modulator (i.e., a modulator that provides a multi-bit digital output data stream). Alternatively, it may be desirable to implement modulator  16  using other oversampling quantizer architectures (e.g., successive approximation, flash, or pipelined quantizers) that provide multi-bit digital representations of the signal applied to the quantizer&#39;s input. In such multi-bit implementations, digital chopper  18  may not be implemented using a simple exclusive-or gate, but instead requires more complex circuitry. 
     It therefore would be desirable to provide an oversampling analog-to-digital converter that includes a multi-bit quantizer and that has reduced DC offset and offset drift. 
     It also would be desirable to provide an oversampling analog-to-digital converter that includes a multi-bit Δ-Σ modulator and that has reduced DC offset and offset drift. 
     It further would be desirable to provide an oversampling analog-to-digital converter that has reduced DC offset and offset drift, but that does not require a digital chopper stage. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of this invention to provide an oversampling analog-to-digital converter that includes a multi-bit quantizer and that has reduced DC offset and offset drift. 
     It also is an object of this invention to provide an oversampling analog-to-digital converter that includes a multi-bit Δ-Σ modulator and that has reduced DC offset and offset drift. 
     It further is an object of this invention to provide an oversampling analog-to-digital converter that has reduced DC offset and offset drift, but that does not require a digital chopper stage. 
     In accordance with these and other objects of the present invention, an oversampling A/D converter is provided that includes an analog chopper, a buffer amplifier, an oversampling quantizer (such as a single or multi-bit Δ-Σ modulator, successive approximation quantizer, flash quantizer, pipelined quantizer or other suitable oversampling quantizer), a first digital filter and decimator, and a second digital filter and decimator. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above-mentioned objects and features of the present invention can be more clearly understood from the following detailed description considered in conjunction with the following drawings, in which the same reference numerals denote the same structural elements throughout, and in which: 
     FIG. 1 is a block diagram of a previously known A/D converter circuit; 
     FIG. 2 is a block diagram of another previously known A/D converter circuit; 
     FIG. 3 is a block diagram of an A/D converter circuit of this invention; 
     FIG. 4 is a schematic diagram of exemplary analog chopper circuitry of FIG. 3; and 
     FIG. 5 is a block diagram of another A/D converter circuit of this invention. 
     FIG. 6 is a diagram of frequency response of a circuit according to the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 3, an improved A/D converter in accordance with principles of the present invention is described. A/D converter  50  includes analog chopper  12 ′, buffer amplifier  14 , quantizer  52 , digital filter and decimator 1    54 , FIR filter  56  and decimator 2    58 . 
     Analog chopper  12 ′ chops analog input signal V IN  with a square wave of frequency f chop , which successively reverses the polarity of V IN . Analog chopper  121  may be implemented using any well-known analog chopping circuitry. For example, as shown in FIG. 4, if input signal V IN  is a differential signal V IN =(V IN   + −V IN   − , analog chopper  12 ′ may be implemented using cross-coupled switches  24 ,  25 ,  26 , and  27 . Switch  24  is controlled by chop signal Q, and is coupled between V IN   +  and V COUT   + . Switch  25  is controlled by chop signal Q, and is coupled between V IN   −  and V COUT   − . Switch  26  is controlled by complementary chop signal {overscore (Q)}, and is coupled between V IN   +  and V COUT   − . Switch  27  is controlled by complementary chop signal {overscore (Q)}. and is coupled between V IN   −  and V COUT   + . Chop signals Q and {overscore (Q)} are complementary logic signals of frequency f chop . For example, when Q is HIGH and {overscore (Q)} is LOW, V COUT   + =V IN   + , and V COUT   − =V IN   − . When {overscore (Q)} is HIGH and Q is LOW, V COUT   + =V IN   −  and V COUT   − =V IN   + . Analog chopper 12′ alternatively may be implemented using multiplexer circuitry as described by McCartney, analog multiplier circuitry, or any other suitable analog chopper circuitry. 
     Buffer amplifier  14  couples the output of analog chopper  12 ′ to quantizer  52 , which may be any conventional oversampling quantizer, such as a single or multi-bit Δ-Σ modulator, successive approximation quantizer, flash quantizer, pipelined quantizer, or other suitable oversampling quantizer. Quantizer  52  provides a digital output at a rate f quant  that is substantially higher than f chop . 
     The digital output of quantizer  52  is the input to digital filter and decimator 1    54 , which includes a digital filter and a decimator that reduces the output data rate by a factor of M. For example, digital filter and decimator 1    54  may be implemented using Sinc 3  filter and decimator  20  (FIG.  1 ), in which M equals the oversampling ratio N of quantizer  52 . Alternatively, digital filter and decimator 1    54  may be any other suitable digital filter and decimator. 
     Digital filter and decimator 1    54  provide an output sequence x′(n) at a rate f quant /M. If control frequency f chop  to analog chopper  12 ′ equals f quant /(2×M) then successive output samples x′(n) of digital filter and decimator 1    54  are digital representations of the analog signals (V IN +V OS ) and −(V IN −V OS ), where V OS  is the input-referred offset of buffer amplifier  14  and quantizer  52 . For example, x′(n) for n=0, −1, −2, 3, −4 may be expressed as: 
     
       
           x′ (0)=+( V   IN (0)+ V   OS (0)) 
       
     
     
       
           x′ (−1)=−( V   IN (−1)− V   OS (−1)) 
       
     
     
       
           x′ (−2)=+( V   IN (−2)+ V   OS (−2)) 
       
     
     
       
           x′ (−3)=−( V   IN (−3)− V   OS (−3)) 
       
     
     
       
           x′ (−4)=+( V   IN (−4)+ V   OS (−4))  (7) 
       
     
     Comparing equations (1) and (7), sequence x′(n) may be expressed as: 
     
       
           x′ ( n )=(−1) n   x ( n ),  n= 0, −1, −2,  (8) 
       
     
     FIR filter  56  removes V OS  from sequence x(n) If FIR filter  56  has L coefficients h′(n), n=0, 1, 2, . . . , L−1, output z′(n) of FIR filter  56  may be expressed as:                  z   ′          (   n   )       =       ∑     k   =   0       L   -   1                           h   ′          (   k   )            ×   ′          (     n   -   k     )                 (   9   )                                
     Combining equations (8) and (9), output z′(n) may be expressed as:                  z   ′          (   n   )       =         (     -   1     )     n            ∑     k   =   0       L   -   1                           (     -   1     )       -   k              h   ′          (   k   )       ×     (     n   -   k     )                   (   10   )                                
     Decimator 2    58  reduces the data rate by a factor P, which is an even integer greater than or equal to 2. That is, from every block of P successive samples z′(n), decimator 2    58  provides the first sample at its output y′(n), and discards the remaining P−1 samples. Output y′(n) is at a rate f quant /(M×P). For example, if P=2, output y′(n) is at a rate f chop . 
     Because P is an even integer, the phase relation between analog chopper  12 ′ and decimator 2    58  may be set so that y′(n) is chosen for n always even or n always odd. If n is even, output y′(n) may be expressed as:                  y   ′          (   n   )       =       ∑     k   =   0       L   -   1                           (     -   1     )       -   k              h   ′          (   k   )       ×     (     n   -   k     )                 (   11   )                                
     Ideally, y′(n) contains no offset V OS , such that 
     
       
           y′ ( n )= V   IN  ( n )  (12) 
       
     
     From equations (2), (6), (11) and (12), therefore,                  ∑     k   =   0       L   -   1                         h        (   k   )       ×     (     n   -   k     )         =       ∑     k   =   0       L   -   1                           (     -   1     )       -   k              h   ′          (   k   )       ×     (     n   -   k     )                 (   13   )                                
     and therefore coefficients h′(n) may be expressed as: 
       h′ ( n )=(−1) n   h ( n ),  n= 0, 1, 2, . . . ,  L− 1  (14) 
     Thus, for n even, coefficients h′(n) of FIR filter  56  equal coefficients h(n) of prior art FIR filter  22 , but with the sign reversed for all odd coefficients. 
     Alternatively, if n is odd, output y′(n) may be expressed as:                  y   ′          (   n   )       =       ∑     k   =   0       L   -   1                           (     -   1     )       -     (     k   -   1     )                h   ′          (   k   )       ×     (     n   -   k     )                 (   15   )                                
     Ideally, y′(n) contains no offset V OS , such that 
     
       
           y′ ( n )= V   IN ( n )  (16) 
       
     
     From equations (2), (6), (15) and (16), therefore,                  ∑     k   =   0       L   -   1                         h        (   k   )       ×     (     n   -   k     )         =       ∑     k   =   0       L   -   1                           (     -   1     )       -     (     k   -   1     )                h   ′          (   k   )       ×     (     n   -   k     )                 (   17   )                                
     and therefore coefficients h′( n ) may be expressed as: 
     
       
           h′ ( n )=(−1) (n 1)   h ( n ),  n= 0, 1, 2, . . . ,  L− 1  (18) 
       
     
     Thus, for n odd, coefficients h′(n) of FIR filter  56  equal coefficients h(n) of prior art FIR filter  22 , but with the sign reversed for all even coefficients. 
     FIG. 5 illustrates another converter circuit of this invention that includes a sensor within the chopped conversion chain. Circuit  60  includes excitation source  32 , analog chopper  34 ′and sensor  36 , and A/D converter  62 . A/D converter  62  includes chop synch  40  (as in FIG.  2 ), and includes buffer amplifier  14 , quantizer  52 , digital filter and decimator 1    54 , FIR filter  56  and decimator 2    58  (as in FIG.  3 ). Converter  60  reduces thermal EMF errors due to sensor interconnects and also reduces offset, offset drift and 1/f noise errors produced by buffer amplifier  14  and quantizer  52 . 
     In another aspect of the invention, a method of attenuating a converted digital signal over a wide null band—e.g., from 48 Hz to 62 Hz—is provided. Using conventional methods to produce a wide null band requires complex filter circuitry that is difficult to fabricate and occupies a substantial amount of die space. In a method for producing a wide null band according to the invention, the band is produced using substantially fewer components and less complex circuitry than by conventional methods. 
     Two examples of circuits which can be used to implement the method according to the invention are shown in FIGS. 1 and 3. To produce the desired null band, this method requires only a cascade connection of the two digital filters/decimators. Therefore, the method of the invention can operate with or without the second digital chopper  18  (as in the circuit shown in FIG. 1) or by modifying the sign of the coefficients of the second digital filter/decimator (as in the circuit in FIG.  3 ). 
     More specifically, the circuit shown in FIG. 1 can be used in a method according to the invention by implementing FIR filter  22  with two equal coefficients of ½{h(0)=h(1)=0.5} and, filter  20  as a sinc 4  filter. Alternatively, the method can be implemented using the circuit shown in FIG.  3 . To accomplish this, the digital filter/decimator  54  can be implemented as a sinc 4  with an impulse response of total length 4*k and a decimation factor M=4*k (F 1 =Fs/(4*k)) and the digital filter/decimator  58  can be implemented as an FIR of length  2  with coefficients h(0)=−h(1)=0.5 or h(0)=−h(1)=−0.5 and decimation factor P=2 (Fout=Fs/(8*k)). The actual value of k typically has little influence over the described invention. Nevertheless, a common value selected in such configurations is k=256. The notch, or center, frequency Fo can again be defined as Fo=Fs/k. 
     The attenuation of the input signal magnitude around the notch frequency, Fo, due to such an implementation can be written as:                      H        (   f   )       =                20   ×     log   10                   (       sin        (     π   ×     f   /   Fo       )         k   ×     sin        (     π   ×     f   /   k     ×   Fo     )           )     4     ×                                      sin        (     8   ×   π   ×     f   /   Fo       )         2   ×     sin        (     4   ×   π   ×     f   /   Fo       )                              (   19   )                                
     It should be noted that the method according to invention is not limited to these particular circuit configurations but, rather, these are only exemplary configurations of circuits that produce the results required by the method of the invention. 
     FIG. 6 shows one preferable frequency response that is obtainable according to the method of the invention. In this particular response, an Fclk signal is selected such that Fs=55*k Hz, which provides a corner frequency of Fo=Fs/k=55 Hz. It is shown in FIG. 6, that an implementation according to the invention provides better than about 87 dB of input perturbation rejection in a frequency range of 48 Hz (=50 Hz−4%) to 62.5 Hz (=60 Hz+4%), or about+−14% of the corner frequency. For many applications, this level of rejection is sufficient. Furthermore, in this particular embodiment, attenuation that extends about +−14% around a center frequency of about 55 Hz, or other center frequency chosen to provide coverage of the 50 Hz and 60 Hz power line frequencies, also provides a substantial advantage. It should be noted that the invention is not limited to this particular range. 
     Persons skilled in the art further will recognize that the circuitry of the present invention may be implemented using circuit configurations other than those shown and discussed above. All such modifications are within the scope of the present invention, which is limited only by the claims that follow.