Abstract:
The invention relates to an electronic circuit comprising differential signal input means, a combining stage, a discriminating stage and differential signal output means. The discriminating stage comprises four transistors (Q 8 , Q 9 , Q 10 , Q 11 ) each having first electrodes ( 83, 93, 103, 113 ) and second electrodes ( 81, 91, 101, 111 ) and a respective gate electrode ( 82, 92, 102, 112 ). The first electrodes of said four transistors are connected to a common node. The combining stage is arranged to convert differential input signals into gate signals applied to the gate electrodes of some of said four transistors respectively.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to electronic circuits, in particular to electronic circuits for providing a logic gate operating at high speed under low power supply voltage.  
       BACKGROUND OF THE INVENTION  
       [0002]     There is a growing need to lower the operating voltage of logic circuits, for example in order to reduce power consumption. This can be achieved by not stacking differential pairs in a logic circuit. U.S. Pat. No. 5,751,169 describes such a circuit where a first differential pair provides an amplified level-shifted output in response to a first differential input and a second differential pair provides an amplified output in response to a second differential input, these two outputs providing “exclusionary” signals processed by a comparator stage. Using such single stacks of differential pairs of transistors enables to reduce the necessary operative voltage. Nevertheless, in that patent, the “exclusionary” signals are not symmetric because of the level shift in the first pair. As a result, the operating speed of the logic circuit is limited since the comparator stage is not controlled in a differential mode.  
       OBJECT AND SUMMARY OF THE INVENTION  
       [0003]     It is an object of the invention to provide an electronic circuit able to provide a logic gate function under low power supply voltage.  
         [0004]     The invention provides an electronic circuit comprising differential signal input means, a combining stage, a discriminating stage and differential signal output means, wherein the discriminating stage comprises four transistors each having respective first and second electrodes and a respective gate electrode for controlling a current flow between said first and second electrodes, wherein the first electrodes of said four transistors are connected to a common node, wherein the differential signal output means comprise a pair of differential output terminals each connected to at least one of the second electrodes of said four transistors, and wherein the combining stage is arranged to convert differential input signals received by the differential signal input means into gate signals respectively applied to the gate electrodes of at least some of said four transistors.  
         [0005]     Such an electronic circuit providing differential signal output means enables efficient operation even under low power supply voltage conditions.  
         [0006]     Specific embodiments of the invention are defined in dependent claims.  
         [0007]     The feature of claim  2  enables selecting a pair of transistors among the transistors of the discriminating stage.  
         [0008]     The features of claim  3  enable an easy discrimination.  
         [0009]     The features of claim  4  make sure that only one of the transistors of discriminating stage has the highest base level.  
         [0010]     Claim  5  reveals a combining stage for providing appropriate signals to gate electrodes of the discriminator stage circuit.  
         [0011]     In the particular embodiment set forth in claim  6 , an AND or NOR gate is provided.  
         [0012]     In the particular embodiment set forth in claim  7 , an OR or NAND gate is provided.  
         [0013]     In the particular embodiment set forth in claim  8 , a XOR gate is provided.  
         [0014]     In the embodiment of claim  9 , combining stage and discriminating stage are adapted to provide a latch circuit.  
         [0015]     In the particular embodiment set forth in claim  10 , the circuit latches data from the input signal according to a latch signal.  
         [0016]     According to the embodiment of claim  11 , it is possible to combine logic gates to realise a complex logic circuit.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]     These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter with reference to the drawing figures in which:  
         [0018]      FIG. 1  is a diagrammatic view of the discriminating stage,  
         [0019]      FIGS. 2   a ,  2   b ,  2   c  and  2   d  are diagrammatic views of signal waveforms for the circuit of  FIG. 1 ,  
         [0020]      FIG. 3  is a circuit diagram of a combining stage according to the invention,  
         [0021]      FIG. 4  is a circuit diagram of a discriminating stage performing an AND function according to the invention,  
         [0022]      FIG. 5  is a circuit diagram of a discriminating stage performing an OR function according to the invention,  
         [0023]      FIG. 6  is a circuit diagram of a discriminating stage performing an XOR function according to the invention,  
         [0024]      FIG. 7  is a circuit diagram of a latch circuit according to the invention, and  
         [0025]      FIG. 8  is a diagrammatic view of more complex logic circuit. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0026]     The invention is carried out by using a discriminating stage circuit as shown in  FIG. 1 . The discriminating stage circuit comprises a first pair of transistors, consisting of transistors Q 8  and Q 11 , and a second pair of transistors, consisting of transistors Q 9  and Q 10 . All transistors are preferably identical, being of the same type and size. They can for example be npn-type bipolar transistors as shown in  FIG. 1 . In this embodiment, each transistor Q 8 , Q 9 , Q 10  and Q 11  includes an emitter  83 ,  93 ,  103 ,  113 , a collector  81 ,  91 ,  101 ,  111  and a base  82 ,  92 ,  102 ,  112  respectively to gate current along the collector-emitter path. The four emitters are connected together to a common node. A current sink  1  is connected between that node and a V dd  power supply terminal. A DC voltage V cc -V dd  is applied between that terminal and a V cc  supply terminal not shown in  FIG. 1 . Also not shown in  FIG. 1  are resistors connected between the V cc  supply terminal and the collectors  81 ,  91 ,  101 ,  111  of the four transistors Q 8 , Q 9 , Q 10 , Q 11 . These resistors have matched resistance values. Their exact connections depend on the application of the circuits. Examples will be described further on.  
         [0027]     When several transistors are connected together by a common emitter terminal, current flows only through the transistor that has the highest base voltage level. To use such a circuit as a discriminating stage of a logic circuit, one needs to ensure that only one of the four transistors has the highest (or lowest) base voltage for all possible combinations of the two input signals to be compared. This is achieved by the invention as described hereinafter.  
         [0028]     The bases of the two pairs of transistors of the discriminating stage are driven in the following way: A first differential input signal is used to discriminate which of the two pairs will include the conducting transistor. A second differential input signal is used to discriminate between the two transistors of the pair elected by the first differential input signal. Simultaneously, the second differential input signal also discriminates between the two transistors of the other pair.  
         [0029]     The bases  82 ,  92 ,  102 ,  112  of the transistors of the discriminating stage may be driven by tri-state voltage signals as illustrated in  FIG. 2 . These signals are derived from input differential signals a-aq, and b-bq where xq denotes the logic complement of x. In  FIG. 2   a , the first input signal b is shown as a solid line, and the complementary signal bq is shown as a dashed line. In  FIG. 2   b , the second input signal a is shown as a solid line, and the complementary signal aq is shown as a dashed line. Each signal alternately has a high level and a low level depending on the logic values that it conveys.  
         [0030]     The input signals are combined in a combining stage an example of which is given in  FIG. 3 , so that the transistors of the discriminating stage have their respective bases driven by composite signals of first and second input signals b, a and complementary signals bq, aq as depicted in  FIGS. 2   c  and  2   d.    
         [0031]     The bases  92 ,  102  of the transistors Q 9 , Q 10  are shown in  FIG. 2   c  in solid and dashed lines respectively. Their common part (in dash-dotted lines) is proportional to the second differential input signal (a-aq) and their differential part is proportional to the first differential input signal (b-bq).  
         [0032]     The bases  112 ,  82  of the transistors Q 11 , Q 8  are shown in  FIG. 2   d  in solid and dashed lines respectively. Their common part (in dash-dotted lines) is proportional to the first differential input signal (b-bq) and their differential part is proportional to the second differential input signal (a-aq).  
         [0033]     The three voltage levels of the signals applied to the transistor bases are V cc , V cc -RI, and V cc -2RI, where R and I are predetermined resistance and current values.  
         [0034]     A combining stage, shown on  FIG. 3 , is adapted to apply the three-state voltage levels to the bases  82 ,  92 ,  102  and  112  of the respective transistors Q 8 , Q 9 , Q 10 , Q 11  of  FIG. 4 , based on first input signal b and its complementary input signal bq, and on second input signal a and its complementary input signal aq.  
         [0035]     All possible combinations of input signals a and b are shown in  FIGS. 2   a  and  2   b.    
         [0036]     In  FIG. 2   c , the base  102  of the transistor Q 10  will have its highest base voltage level V cc  when both differential input signals are high. If one of the differential input signals is low, the voltage level of the base  102  of the transistor Q 10  will decrease by RI to V cc -RI. If both differential input signals are low, the voltage level of the base  102  of the transistor Q 10  will again decrease by RI to V cc -2RI.  
         [0037]     Still in  FIG. 2   c , the base  92  of the transistor Q 9  will have its highest base voltage level V cc  when a-aq is high and b-bq is low. If either one of a-aq and b-bq changes in voltage level, the voltage level of the base  92  of the transistor Q 9  will decrease by RI to V cc -RI. If the voltage level of the second differential input signal a-aq is low and the voltage level of the first differential input signal b-bq is high, the voltage level of the base  92  of the transistor Q 9  will again decrease by RI to V cc -2RI.  
         [0038]     In  FIG. 2   d , the base  112  of the transistor Q 11  will have its highest base voltage level V cc  when b-bq is high and a-aq is low. If either one of a-aq and b-bq changes in voltage level, the voltage level of the base  112  of the transistor Q 11  will decrease by RI to V cc -RI. If the voltage level of the second differential input signal a-aq is high and the voltage level of the first differential input signal b-bq is low, the voltage level of the base  112  of the transistor Q 11  will again decrease by RI to V cc -2RI.  
         [0039]     Still in  FIG. 2   d , the base  82  of the transistor Q 8  will have its highest base voltage level V cc  when both a-aq and b-bq are low. If one of the differential input signals is high, the voltage level of the base  82  of the transistor Q 8  will decrease by RI to V cc -RI. If both differential input signals are high, the voltage level of the base  82  of the transistor Q 8  will again decrease by RI to V cc -2RI.  
         [0040]     Accordingly, only one of the four transistor bases is at the highest voltage level for a given combination of input signals a and b, electing the conductive transistor of the discriminating stage.  
         [0041]     The circuit of  FIG. 3  is only an illustrative example of a suitable way of performing a combination such that a first pair of transistors of the discriminating stage is driven by a signal that has a common mode which is driven by one differential input signal and a differential mode driven by a second differential input signal, while a second pair of transistors of the discriminating stage is driven by a signal that has a common mode which is driven by the second differential input signal and a differential mode driven by the first differential input signal.  
         [0042]     Such discriminating stage can be used in order to provide logic circuits. One has to ensure that, given two input signals to be compared, one of a given set of transistors of the discriminating stage connected to a first output terminal will have its base at the highest voltage value if the intended comparison is positive, while one of another set of transistors of the discriminating stage connected to a second output terminal has its base at the highest voltage level if the comparison is negative. Purely illustrative examples are given in the following. Due to the resistors connected between the power supplies and the collectors of the transistors of the discriminating stage, the voltage level of the collector of the ON transistor will be lower than the voltage level of the collectors of the other transistors of the discriminating stage.  
         [0043]      FIG. 4  represents a discriminating stage providing a simplified AND logic circuit. Transistors Q 8 , Q 9  and Q 11  have a common collector terminal  81  connected to a first differential output terminal o, while transistor Q 10  has an individual collector terminal  101  connected to a second differential output terminal oq. A resistor R 5  is connected between power supply  2  providing a voltage level of value V cc  and a common collector terminal for transistors Q 8 , Q 9  and Q 11 . A resistor R 6  is connected between power supply  2  and the collector terminal of transistor Q 10 .  
         [0044]     The voltage levels of the bases of the transistors of the discriminating stage are defined by the combining circuit (on  FIG. 3 ) in the following way: 
        if first and second differential input signals a-aq and b-bq are high, the transistor Q 10  will have the highest base voltage level and current will flow through Q 10 . The second differential output terminal will have voltage level V cc -RI. In the meantime, the first differential output terminal has voltage level V;     if any of a-aq and b-bq is low, one of transistors Q 8 , Q 9  and Q 11  will have the highest base voltage level, and no current will flow through Q 10 . The first differential output terminal will have voltage level V cc -RI. In the meantime, the second differential output terminal has voltage level V.        
 
         [0047]     In order to do so, the combining stage of  FIG. 3  is arranged in the following way: 
        the base terminals of the transistors Q 0  and Q 1  receive the first input signal b,     the base terminals of the transistors Q 2  and Q 3  receive the first complementary input signal bq,     the base terminals of the transistors Q 4  and Q 6  receive the second input signal a,     the base terminals of the transistors Q 5  and Q 7  receive the second complementary input signal aq,     Q 0 , Q 1 , Q 2  and Q 3  share a common emitter terminal, connected to a 2I current sink  5 ,     Q 4 , Q 5 , Q 6  and Q 7  share a common emitter terminal, connected to a 2I current sink  6 ,     a first resistor R 1  is connected between the power supply  4  and a common collector terminal for the transistors Q 0  and Q 4 ,     a second resistor R 2  is connected between the power supply  4  and a common collector terminal for the transistors Q 1  and Q 5 ,        
 
         [0056]     a third resistor R 3  is connected between the power supply  4  and a common collector terminal for the transistors Q 2  and Q 6 , 
        a fourth resistor R 4  is connected between the power supply  4  and a common collector terminal for the transistors Q 3  and Q 7 , (R 1 , R 2 , R 3 , R 4 , R 5  and R 6  having for example matched resistance values equal to R),     the base of transistor Q 8  is connected to a common collector terminal  41  of transistors Q 0  and Q 4 ,     the base of transistor Q 9  is connected to a common collector terminal  61  of transistors Q 2  and Q 6 ,     the base of transistor Q 10  is connected to a common collector terminal  71  of transistors Q 3  and Q 7 ,     the base of transistor Q 11  is connected to a common collector terminal  51  of transistors Q 1  and Q 5 .        
 
         [0062]     If the first differential input signal b-bq is high, the transistors Q 2  and Q 3  will be off and thus the voltage level of their collector terminal will be higher. The pair of transistors Q 9 -Q 10  of the discriminating stage, whose bases are connected to the collector terminals of transistors Q 2  and Q 3 , respectively, is selected. Then, if the second differential input signal a-aq is high, the transistor Q 7  will also be off and no current at all will flow through the resistor R 4 . The base terminal of transistor Q 10 , which is connected to the common collector terminal of transistors Q 7  and Q 3  has the highest voltage level of all four transistors of the discriminating stage.  
         [0063]     Matter-of-factly, if the first and second differential input signals are high, Q 7  and Q 3  are off, no current flows through the resistor R 4 , the collector terminal of transistor Q 7  and the base terminal of transistor Q 10  are at level V. The transistor Q 6  is on and the transistor Q 2  off, so the base terminal of transistor Q 9  is at level V-RI. Similarly, the transistors Q 0  and Q 4  are on, thus the base terminal of transistor Q 8  is at level V-2RI. The transistor Q 1  is on and the transistor Q 5  off, thus the base terminal of transistor Q 11  is at level V-RI.  
         [0064]     Current therefore flows through transistor Q 10 , and the second differential output terminal has voltage level V-RI, indicating both first and second differential input signals are high. If any of the first and second differential input signals is low, either Q 8 , Q 9  or Q 11  will be the transistor with the highest base voltage level, as seen in Table 1. The first output terminal has voltage level V-RI, indicating that either first or second differential input signals or both are low. Accordingly, a NOR logic gate is readily achieved by the same circuit.  
                                                                         TABLE 1                                   On   Off   aq′   aq″   a″   a′                                    a = 1, b = 1   Q0 Q1   Q2 Q3   Vcc-   Vcc-RI   Vcc   Vcc-RI           Q4 Q6   Q5 Q7   2RI       a = 1, b = 0   Q2 Q3   Q0 Q1   Vcc-RI   Vcc-2RI   Vcc-RI   Vcc           Q4 Q6   Q5 Q7       a = 0, b = 1   Q0 Q1   Q2 Q3   Vcc-RI   Vcc   Vcc-RI   Vcc-           Q5 Q7   Q4 Q6               2RI       a = 0, b = 0   Q2 Q3   Q0 Q1   Vcc   Vcc-RI   Vcc-   Vcc-RI           Q5 Q7   Q4 Q6           2RI                  
 
         [0065]     All logic functions can be readily achieved using the same combining stage of  FIG. 3 .  FIG. 5  shows an exemplary discriminating stage providing a logic OR according to the teachings of the invention. Compared to the logic AND from  FIG. 4 , only few changes are performed in the discriminating stage, which is adapted so that if either first or second differential input signal is high, the second differential output terminal has voltage level V-RI. In order to do so, the connections of bases of transistors Q 8  and Q 10  are exchanged so that transistor Q 10  gets the higher base voltage level when both differential input signals are low. Accordingly, a NAND gate is readily achieved by the same circuit.  
         [0066]     Discriminating stage of  FIG. 4  and  FIG. 5  can be made symmetric by connecting two additional passive collectors, only used as resistive elements, on output terminals oq and o respectively.  
         [0067]      FIG. 6  shows an exemplary discriminating stage providing a logic XOR Compared to the logic OR from  FIG. 5 , few changes are performed in the discriminating stage only, which is adapted in a way that, if the first and second differential input signals are simultaneously high or low, the base of one of transistors Q 8  or Q 9  will have the higher voltage level, whereas in other cases, the base of one of transistors Q 10  or Q 11  will have the higher voltage level. As an additional feature of the invention, the logic XOR provided here is perfectly symmetric with respect to the two differential inputs, unlike state of the art XORs.  
         [0068]     The inventive circuit could therefore be used in many logic circuits, of which the circuits described hereinabove are but a few examples.  
         [0069]     The circuit could also be used in order to realise a latch circuit, of which an example is given in  FIG. 7 : 
        the transistors Q 0 , Q 1 , Q 2  and Q 3  share a common emitter terminal which is connected to a 2I current sink  5 ,     a latch control signal clk is input to the base terminals of transistors Q 0  and Q 1 ,     a complementary latch control signal clkq is input to the base terminals of transistors Q 2  and Q 3 ,     a resistor R 1 , R 2  is connected between the power supply  4  and the collector terminals of transistors Q 0  and Q 1  respectively,     a resistor R 3 , R 4  is connected between the power supply  2  and the collector terminals of transistors Q 2  and Q 3  respectively,     the transistors Q 4  and Q 5  have a common emitter terminal connected to an I current sink  6 ,     the base terminals of transistors Q 4  and Q 5  receive an input data signal (d) and a complementary input data signal (dq) respectively,     the resistors R 1  and R 2  connect the collector terminals of transistors Q 4  and Q 5 , respectively, to the power supply  4 . The transistors Q 4  and Q 5  thus share a common collector terminal with the transistors Q 0  and Q 1  respectively,     the transistors Q 8 , Q 9 , Q 10  and Q 11  have a common emitter terminal connected to an I current sink  1 ,     resistor R 3  connects the common collector terminal of transistors Q 8  and Q 9 , where the complementary output signal is taken, to the power supply  2 ,     resistor R 4  connects the common collector terminal of transistors Q 10  and Q 11 , where the output signal is taken, to the power supply  2 ,     the base terminals of transistors Q 9  and Q 10  receive the output signal and the complementary output signal from the collector terminals of transistors Q 11  and Q 8 , respectively,     the base terminals of transistors Q 8  and Q 11  receive signals from the collector terminals of transistors Q 5  and Q 4 , respectively.        
 
         [0083]     Thus, in a first state of the differential latch control signals, the signals input to the base terminals of transistors Q 8  and Q 11  by the combining stage have voltage levels higher than the signals input to the bases of transistors Q 9  and Q 10  by the discriminating stage itself. In a second state of the differential latch control signals, the signals input to the bases of transistors Q 8  and Q 11  by the combining stage have voltage levels lower than the signals input to the bases of transistors Q 9  and Q 10  by the discriminating stage itself. In that state, changing the differential input data signal will not change the conducting transistor from Q 8 , Q 9 , Q 10  and Q 11 . Data is thus latched until the state of the latch control signals changes.  
         [0084]     In some complex logical function, the discriminating stage can be used as a next stage driver as shown on the non-limitative example of  FIG. 8 . In this embodiment, gate signals applied to discriminating stage can be more complex combinations of more than two differential input signals.  FIG. 8  includes a first pre-discriminating stage identical to the circuit of  FIG. 6 . Differential input signals  1   b - 1   bq  and  1   a - 1   aq  are input to the first pre-discriminating stage in the way already described, and combined signals are input to respective bases of four transistors Q 18 , Q 19 , Q 110  and Q 111  of a first pre-discriminating stage. Two different resistors taken from R 31 , R 32 , R 33  and R 34  are connected between the power supply  34  and the collector terminal of each of these transistors respectively. Collector terminals of transistors Q 18  and Q 19  are each connected to first  3   a ′ and third  3   aq ″ intermediate terminals, the collector terminals of transistors Q 110  and Q 111  are each connected to second  3   a ′ and fourth  3   a ″ intermediate terminals.  
         [0085]     The circuit also includes a second pre-discriminating stage identical to that of  FIG. 6 . Differential input signals  2   b - 2   bq  and  2   a - 2   aq  are input to the second pre-discriminating stage in the way already described, and combined signals are input to respective bases of four transistors Q 28 , Q 29 , Q 210  and Q 211  of a second pre-discriminating stage. Two different resistors taken from R 31 , R 32 , R 33  and R 34  are connected between the power supply  34  and the collector terminal of each of these transistors respectively. The collector terminals of transistors Q 28  and Q 29  are each connected to first  3   aq ′ and second  3   a ′ intermediate terminals. The collector terminals of transistors Q 210  and Q 211  are each connected to third  3   aq ″ and fourth  3   a ″ intermediate terminals.  
         [0086]     The discriminating stage includes four transistors Q 8 , Q 9 , Q 10 , Q 11  connected in that example in the way used for the XOR gate of  FIG. 5 . The base terminals of the four transistors of the discriminating stage are connected to a respective one of the intermediate terminals.  
         [0087]     If  1   a - 1   aq  and  1   b - 1   aq  are high, transistors Q 17  and Q 13  of first pre-discriminating stage will be blocked, and Q 111  will have the highest base voltage level. Current will flow through Q 111 , which is connected to intermediate terminals  3   a ′ and  3   a ″ through the resistors R 32  and R 34 , and  3   a ′ and  3   a ″ voltage levels will decrease.  
         [0088]     If  2   a - 2   aq  and  2   b - 2   bq  are high, Q 27  and Q 23  of second pre-discriminating stage will be blocked, and Q 211  will have the highest base voltage level. Current will flow through Q 211 , which is connected to intermediate terminals  3   aq ″ and  3   a ″ through the resistors R 33  and R 34 , and  3   aq ″ and  3   a ″ voltage levels will decrease.  
         [0089]     Thus, no current is flowing through resistor R 31  associated to signal  3   aq ′, and the base terminal of Q 10 , which is connected to the intermediate terminal receiving signal  3   aq ′, will have the highest voltage level. Q 10  is thus on and current will flow through Q 10 . Voltage level of output terminal o will thus be lower than voltage level of second output terminal oq.  
         [0090]     Other states of input signals  1   a ,  1   b ,  2   a  and  2   b  and will provide different differential output signals in differential output terminals. By changing the connections in the first and second pre-discriminating stages and in the discriminating stage, any logic circuit can thus be provided for two or more input signals.  
         [0091]     Though a particular arrangement is presented, a similar circuit can combine any kind of logic or latch gates as previously described into a combined logic function of three and more differential input signals at high speed even under low power supply voltage.