Abstract:
A method of manufacturing a twin-ONO-type SONOS memory using a reverse self-alignment process, wherein an ONO dielectric layer is formed under a gate and physically separated into two portions using a reverse self-alignment process irrespective of photolithographic limits. To facilitate the reverse self-alignment, a buffer layer and spacers for defining the width of the ONO dielectric layer are adopted. Thus, the dispersion of trapped charges during programming and erasing can be appropriately adjusted, thus improving the characteristics of the SONOS. The present invention prevents the redistribution of charges in time after the programming and erasing operations.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a method of manufacturing a semiconductor memory device. More particularly, the present invention is directed to a method of manufacturing a twin-ONO-type SONOS memory device, which can function as a 2-bit operating memory device with asymmetric programming, using a reverse self-alignment process. 
   2. Description of the Related Art 
   In recent years, nonvolatile semiconductor memory devices have been used in various applications. Nonvolatile semiconductor memory devices can not only electrically erase and program data but also retain data even during interruption of power supply. An example of a nonvolatile semiconductor memory device is a flash memory cell. 
   Conventionally, stack-gate-type flash memories, in which floating gates and control gates are stacked, have been developed and produced in mass. Floating gates are intended for programming charges, and control gates are intended for controlling the floating gates. 
   As capacitances of memory devices become larger and the number of gate arrays required for forming complicated circuits increases, techniques of forming fine patterns with a sub-0.10-μm linewidth become indispensable. Although conventional stack-gate-type nonvolatile memory cells have been constantly scaled down, photolithographic and etching processes for forming hyperfine devices are about to reach the technical limits. That is, in addition to scaling vows, patterning a structure in which a floating gate and a control gate are stacked becomes complicated due to a high step difference or a high aspect ratio. 
   On the other hand, research on SONOS (or MONOS) nonvolatile cells with trapped charges has also progressed to develop single-gate structures such as MOSFETs. 
     FIG. 1  illustrates a schematic cross-sectional view of a typical SONOS memory cell. 
   Referring to  FIG. 1 , to form a SONOS (or MONOS) cell, a source and a drain  15  are formed in a semiconductor substrate  10 , such as a p-Si substrate, and then an oxide-nitride-oxide (ONO) dielectric layer  20  and a gate  30  are sequentially formed on the semiconductor substrate  10 . The SONOS cell uses the ONO dielectric layer  20  in place of a gate oxide layer of a transistor. In the SONOS cell, a floating gate for programming charges is replaced by the ONO dielectric layer  20 . Thus, electrons or holes are injected into a silicon nitride layer  23  sandwiched between thin silicon oxide layers  21  and  25  included in the ONO dielectric layer  20 . 
   Since the ONO dielectric layer  20  is about 10 to 20 nm thick, the step difference is not very much. Therefore, scaling down the SONOS cell within a permitted photolithographic limit is relatively easy. Also, a number of additional processes related to the floating gates can be omitted, thus simplifying the entire manufacturing process. 
   Meanwhile, for several years, some manufacturers have adopted SONOS memories for obtaining highly integrated nonvolatile memory devices. These manufacturers proposed and attempted to manufacture 2-bit SONOS memories that use asymmetric programming without floating gates. 
     FIG. 2  is a schematic diagram illustrating the operations of a typical 2-bit memory device when a voltage V DS  is applied from a drain to a source in the memory device. 
   Referring to  FIG. 2 , a 2-bit memory technique enables the 2-bit memory device to be twice as much integrated as a conventional stack-gate-type flash device having the same area. A 2-bit memory operation comprises: (i) forwardly injecting electrons into a portion of a silicon nitride layer  23  positioned at an edge of a gate  30  by applying a high voltage to a control gate  30  and one of source and drain junctions  15  of a transistor, i.e., by using channel hot electron injection (CHEI), and (ii) reversely reading data by applying a voltage to the gate  30  and the other source and drain. 
   An erasing operation comprises applying a high voltage to a drain junction  15  and grounding the gate  30  and a substrate  10  bulk. Thus, the programmed electrons in the silicon nitride layer  23  are combined with holes using band-to-band tunneling (BtBT) in an overlap region between the gate  30  and a junction  15 . 
   In an asymmetric charge trap operation, when the linewidth of the gate is relatively high, a spatial interval between programmed traps is sufficient enough that no serious problem occurs in the 2-bit operation. However, as the linewidth of the gate  30  is reduced to about 0.10 μm or less, the 2-bit memory characteristics may be degraded. This is because the charges trapped in the ONO dielectric layer  20  by the CHEI have a certain degree of dispersion, which increases with operation time. 
   Inset of  FIG. 3A  illustrates a spatial distribution graph of charges in a typical SONOS, the charges being injected into the silicon nitride layer  23  after memory programming. Variation of drain current with gate voltage in a fresh cell and in an already programmed cell is illustrated in  FIG. 3A .  FIG. 3B  illustrates a retention characteristic of a typical SONOS, which results from a redistribution of injected charges with operation time (t). 
   In a typical SONOS, in programming by CHEI, charges are injected into the silicon nitride layer. The distribution graph of the charges is obtained using a simulation model as shown in  FIG. 3A . That is, charge distribution in each of a fresh cell and a programmed cell is obtained by simulation fitting. Referring to  FIG. 3B , since the injected charges are redistributed in time (t), the charge retention characteristic is degraded. The decay rate N(t) of a distribution center can be expressed by the equation shown in  FIG. 3B . Referring to  FIG. 3B , as time t tends to t′, the height of the distribution graph decreases, raising the degree of dispersion. 
   If, in a SONOS, charges are scattered after programming and charges programmed in a central channel region are not completely erased in repetition of programming and erasing, residual charges may be accumulated on the channel region. The accumulated charges may deteriorate the SONOS endurance. Similarly, after hole charges are programmed, accumulated holes may make the endurance of the device poor. 
     FIGS. 4A and 4B  are graphs illustrating the endurance of a typical SONOS. Variation of cell threshold voltage with number of programming and erasing cycles is illustrated in  FIGS. 4A and 4B . 
   In  FIG. 4A , initially, a substrate bulk and a source of a SONOS cell are grounded. After programming and erasing are repeated, the endurance curve is obtained as shown in  FIG. 4A . Here, the programming is performed by applying 11 V and 6 V to a gate and a drain, respectively, for 100 μs, and the erasing is performed by applying 0V, 10V, 10V, and 0V to the gate, the drain, the source, and the substrate bulk, respectively, for 100 μs. Reference numeral  41  denotes a case where the cell is turned on, while reference numeral  45  denotes a case where the cell is turned off. 
   In  FIG. 4B , only erasing conditions are changed from the case of  FIG. 4A . That is, erasing is performed by applying 0V, 10V, 4V, and 0V to a gate, a drain, a source, and a substrate bulk, respectively. Here, an electric field is formed between the source and the drain so that holes formed by band-to-band tunneling (BtBT) can be efficiently injected into a central channel region. Reference numeral  43  denotes a case where a cell is turned on, while reference numeral  47  denotes a case where the cell is turned off. 
   Based on the results, it can be inferred that a tail of electron dispersion exists in the central channel region at a certain level. Although there is a possibility that the distribution of electrons or holes in an ONO dielectric layer can be minimally adjusted by optimization of process conditions or by appropriate control of driving voltage, shorter and shorter gate lengths cannot assure the 2-bit characteristics anymore. 
   SUMMARY OF THE INVENTION 
   With a view towards minimizing or avoiding the shortcomings and problems of the prior art, the present invention provides a method of manufacturing a 2-bit SONOS memory using channel hot electron injection (CHEI), in which, in the sub-100-nm regime, a charge distribution of an ONO dielectric layer can be appropriately adjusted during programming and erasing. 
   According to an aspect of the present invention, there is provided a method of manufacturing a SONOS memory, in which ONO dielectric layers disposed under a gate are physically separated from each other to form a precisely symmetric structure. 
   According to an embodiment of the present invention, there is provided a method of manufacturing a SONOS memory comprising the steps of forming a silicon oxide-silicon nitride-silicon oxide (ONO) dielectric layer on a substrate, forming a buffer layer on the ONO dielectric layer, the buffer layer having a trench exposing a portion of the surface of the ONO dielectric layer, forming first conductive spacers on inner walls of the trench, separating the ONO dielectric layer into two portions by selectively removing the exposed portion of the ONO dielectric layer using the first conductive spacers as an etch mask, forming a gate dielectric layer on the exposed substrate resulting from the separation of the ONO dielectric layer, the gate dielectric layer extended onto exposed sidewalls of the separated ONO dielectric layer and the first conductive spacers inside the trench and also onto top surface of the buffer layer, forming a second conductive layer on the gate dielectric layer to fill a gap between the inner walls of the trench, removing the gate dielectric layer exposed by the second conductive layer, removing the buffer layer using the first conductive spacers as an etch mask, and patterning the two-separated ONO dielectric layers by selectively removing a portion of each of the separated ONO dielectric layer, which is exposed by the removal of the buffer layer, using the first conductive spacers as an etch mask. 
   According to a feature of the present invention, the gate dielectric layer is preferably formed of silicon oxide using thermal oxidation or chemical vapor deposition techniques. 
   According to another feature of the present invention, a process for forming the second conductive layer comprises the steps of depositing the second conductive layer on the gate dielectric layer to fill a gap between inner walls of the trench completely, and exposing a portion of the gate dielectric layer, which is extended onto the buffer layer, by etching the second conductive layer using an etchback process or chemical mechanical polishing or both. 
   According to yet another feature of the present invention, the etching of the second conductive layer is preferably performed until a top surface of the second conductive layer is at a lower level than a top surface of the first conductive spacers. 
   According to still another feature of the present invention, the method of manufacturing a SONOS memory further comprises forming a first diffusion layer by implanting impurity ions into a portion of the substrate outside the trench, which is exposed by patterning the two-separated ONO dielectric layers, forming second insulating spacers on exposed sidewalls of the patterned two-separated ONO dielectric layers and the first conductive spacers, and forming a second diffusion layer by implanting impurity ions into the first diffusion layer using the second insulating spacers as an ion implantation mask. 
   According to another feature of the present invention, the second insulating spacers may be formed of one of silicon oxide and silicon nitride using chemical vapor deposition or thermal oxidation techniques. 
   According to yet another feature of the present invention, the method of manufacturing a SONOS memory further comprises the step of performing a silicidation process for selectively forming a first silicide layer on the first conductive spacers and the second conductive layer for connecting the first conductive spacers with the second conductive layer and selectively forming a second silicide layer on the second diffusion layer. 
   According to still another feature of the present invention, the first conductive spacers and the second conductive layer may be formed of conductive silicon. 
   According to another embodiment of the present invention, there is provided a method of manufacturing a SONOS memory comprising the steps of forming a silicon oxide-silicon nitride-silicon oxide (ONO) dielectric layer on a substrate, forming a first conductive layer on the ONO dielectric layer, forming a buffer layer on the first conductive layer, the buffer layer having a trench exposing a portion of the surface of the first conductive layer, forming first insulating spacers on inner walls of the trench, separating the first conductive layer and underlying ONO dielectric layer into two portions by sequentially removing the exposed portion of the first conductive layer and the ONO dielectric layer disposed thereunder using the first insulating spacers as an etch mask, forming a gate dielectric layer on the exposed substrate resulting from the separation of the ONO dielectric layer, the gate dielectric layer extended onto exposed sidewalls of the separated first conductive layer and underlying ONO dielectric layer and the first insulating spacers inside the trench and also onto top surface of the buffer layer, forming a second conductive layer on the gate dielectric layer to fill a gap between the inner walls of the trench, removing the gate dielectric layer exposed by the second conductive layer, removing the buffer layer using the first insulating spacers as an etch mask, and patterning the two-separated first conductive layers and the underlying ONO dielectric layers by sequentially and selectively removing a portion of each of the first conductive layer, which is exposed by removing the buffer layer, and a portion of each of the separated ONO dielectric layer disposed thereunder using the first insulating spacers as an etch mask. 
   According to a feature of the present invention, the gate dielectric layer is extended onto the first insulating spacers until the first insulating spacers are insulated from the second conductive layer to allow the second conductive layer and the two-separated and patterned first conductive layers to function as independent gates. 
   According to another feature of the present invention, a process for forming the second conductive layer comprises the steps of depositing the second conductive layer on the gate dielectric layer to fill a gap between the inner walls of the trench completely, and exposing a portion of the gate dielectric layer, which is extended onto the buffer layer by etching the second conductive layer using an etchback process or chemical mechanical polishing or both. 
   According to yet another feature of the present invention, the etching of the second conductive layer is preferably performed until a top surface of the second conductive layer is at a lower level than a top surface of the first insulating spacers. 
   According to still another feature of the present invention, the method of manufacturing a SONOS memory further comprises the steps of forming a first diffusion layer by implanting impurity ions into a portion of the substrate outside the trench, which is exposed by patterning the two-separated first conductive layers and the underlying ONO dielectric layers, forming second insulating spacers on exposed sidewalls of the patterned two-separated ONO dielectric layers, the second insulating spacers extending onto exposed sidewalls of the first conductive layers and the first insulating spacers, and forming a second diffusion layer by implanting impurity ions into the first diffusion layer using the second insulating spacers as an ion implantation mask. 
   According to another feature of the present invention, the method of manufacturing a SONOS memory further comprises the step of performing a silicidation process for selectively forming a first silicide layer on the second conductive layer and selectively forming a second silicide layer on the second diffusion layer. 
   According to yet another feature of the present invention, the method of manufacturing a SONOS memory further comprises the steps of forming a capping insulating layer on the second conductive layer before removing the gate dielectric layer exposed by the second conductive layer, and removing the capping insulating layer before performing the silicidation process. 
   According to still another feature of the present invention, the first conductive layer and the second conductive layer are preferably formed of conductive silicon. 
   According to another feature of the present invention, the capping insulating layer may be formed by oxidizing a top surface of the second conductive layer formed of conductive silicon to a predetermined depth. 
   According to yet another feature of the present invention, the first insulating spacers are preferably made of a material having etch selectivity with respect to the buffer layer. 
   According to yet another embodiment of the present invention, there is provided a method of manufacturing a SONOS memory comprising the steps of forming a silicon oxide-silicon nitride-silicon oxide (ONO) dielectric layer on a substrate, forming a buffer layer on the ONO dielectric layer, the buffer layer having a trench exposing a portion of the surface of the ONO dielectric layer, forming first insulating spacers on inner walls of the trench, separating the ONO dielectric layer into two portions by selectively removing the exposed portion of the ONO dielectric layer using the first insulating spacers as an etch mask, selectively removing the first insulating spacers, exposing a portion of the silicon nitride layer by selectively removing upper silicon oxide layer of a portion of the separated ONO dielectric layer, which is exposed by removing the first insulating spacers, forming a gate dielectric layer on the substrate, which is exposed by the separation of the ONO dielectric layer, the gate dielectric layer extended onto the silicon nitride layer and the buffer layer, forming a conductive layer on the gate dielectric layer to fill a gap between the inner walls of the trench, removing a portion of the gate dielectric layer, which is exposed by the conductive layer, removing the buffer layer using the conductive layer as an etch mask, and patterning the two-separated ONO dielectric layers by selectively removing a portion of the ONO dielectric layer, which is exposed by removing the buffer layer, using the conductive layer as an etch mask. 
   According to a feature of the present invention, the first insulating spacers are preferably sacrificial layers formed of an insulating material other than the buffer layer or a photoresist material. 
   According to another feature of the present invention, the method of manufacturing a SONOS memory further comprises the steps of forming a first diffusion layer by implanting impurity ions into a portion of the substrate outside the trench, which is exposed by patterning the two-separated ONO dielectric layers, forming second insulating spacers on the exposed sidewalls of the patterned two-separated ONO dielectric layers, the second insulating spacers extending onto an exposed sidewall of the gate dielectric layer surrounding the first conductive layer, and forming a second diffusion layer by implanting impurity ions into the first diffusion layer using the second insulating spacers as an ion implantation mask. 
   According to yet another feature of the present invention, the gate dielectric layer is preferably formed of silicon oxide using thermal oxidation or CVD techniques. 
   According to still another feature of the present invention, the conductive layer is preferably formed of conductive silicon. 
   According to another feature of the present invention, a process for forming the conductive layer comprises the steps of depositing the conductive layer on the gate dielectric layer to fill a gap between the inner walls of the trench completely, and exposing a portion of the gate dielectric layer, which is extended onto the buffer layer by etching the conductive layer using an etchback process or chemical mechanical polishing or both. 
   According to still another embodiment of the present invention, there is provided a method of manufacturing a SONOS memory comprising the steps of forming a first buffer layer on a substrate, forming a second buffer layer on the first buffer layer, the second buffer layer having an etch selectivity with respect to the first buffer layer and including a trench exposing a portion of the surface of the first buffer layer, removing the portion of the first buffer layer on a bottom part of the trench until the substrate disposed thereunder is exposed, forming a silicon oxide-silicon nitride-silicon oxide (ONO) dielectric layer on the exposed substrate surface and inner walls of the trench, forming first conductive spacers on the ONO dielectric layer formed on the inner walls of the trench, separating the ONO dielectric layer into two portions by selectively removing the ONO dielectric layer using the first conductive spacers as an etch mask until the substrate disposed thereunder is exposed, forming a gate dielectric layer on the exposed substrate resulting from the separation of the ONO dielectric layer, the gate dielectric layer extended onto exposed sidewalls of the first conductive spacers and top surface of the second buffer layer, forming a second conductive layer on the gate dielectric layer to fill a gap between both sidewalls of the trench, removing the gate dielectric layer exposed by the second conductive layer, removing the second buffer layer using the first conductive spacers as an etch mas, and patterning the two-separated dielectric layer by selectively removing a portion of the dielectric layer, which is exposed by removing the buffer layer, using the first conductive spacers as an etch mask. 
   According to a feature of the present invention, a process for forming the second conductive layer comprises the steps of depositing the second conductive layer on the gate dielectric layer to fill a gap between inner walls of the trench completely, and exposing a portion of the gate dielectric layer, which is extended onto the second buffer layer, by etching the second conductive layer using an etchback process or chemical mechanical polishing or both. 
   According to another feature of the present invention, the etching of the second conductive layer is preferably performed until a top surface of the second conductive layer is at a lower level than a top surface of the first conductive spacers. 
   According to yet another feature of the present invention, the method of manufacturing a SONOS memory further comprises the steps of forming a first diffusion layer by implanting impurity ions into a portion of the substrate, which is exposed by patterning the ONO dielectric layer, forming second insulating spacers on exposed sidewalls of patterned ONO dielectric layer, the second insulating spacers extending onto an exposed sidewall of the upper oxide layer of the ONO dielectric layer surrounding the first conductive spacers, and forming a second diffusion layer by implanting impurity ions into the first diffusion layer using the second insulating spacers as an ion implantation mask. 
   According to still another feature of the present invention, the method of manufacturing a SONOS memory further comprises the step of performing a silicidation process for selectively forming a first silicide layer on the first conductive spacers and the second conductive layer for connecting the first conductive spacers with the second conductive layer and selectively forming a second silicide layer on the second diffusion layer. 
   According to the present invention, even if the linewidth of a memory gate is reduced to 0.10 μm or less, a SONOS memory with stable 2-bit characteristics can be manufactured. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail preferred embodiments thereof with reference to the attached drawings in which: 
       FIG. 1  is a schematic diagram illustrating a cross-sectional view of a typical SONOS memory cell; 
       FIG. 2  is a schematic diagram illustrating operations of a typical 2-bit memory device; 
       FIG. 3A  illustrates a distribution graph of charges, which are injected into a silicon nitride layer after programming, in a typical SONOS; 
       FIG. 3B  illustrates a retention characteristic of a typical SONOS, which results from redistribution of injected charges in time (t); 
       FIGS. 4A and 4B  are graphs illustrating an endurance curve of a typical SONOS; 
       FIGS. 5A through 5K  are schematic cross-sectional views illustrating a twin-ONO-type SONOS memory according to a first embodiment of the present invention; 
       FIGS. 6A through 6J  are schematic cross-sectional views illustrating a twin-ONO-type SONOS memory according to a second embodiment of the present invention; 
       FIGS. 7A through 7K  are schematic cross-sectional views illustrating a twin-ONO-type SONOS memory according to a third embodiment of the present invention; 
       FIGS. 8A through 8J  are schematic cross-sectional views illustrating a twin-ONO-type SONOS memory according to a fourth embodiment of the present invention; and 
       FIGS. 9A and 9B  illustrate charge distributions using a simulation model, which explain advantages of the twin-ONO-type SONOS memory according to the embodiments of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Korean Patent Application No. 2003-20444, filed on Apr. 1, 2003, and entitled: “Method of Manufacturing Twin-ONO-Type SONOS Memory Using Reverse Self-Alignment Process”, is incorporated by reference herein in its entirety. 
   The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like numbers refer to like elements throughout. 
   The nitride layer in the ONO dielectric layers is intended for the purpose of charge trapping. Such charge trapping layers have charge trapping sites that have good trapping ability for both electrons and holes. Though the exemplary embodiments of the present invention are described below using the nitride layer, e.g., silicon nitride layer, as the charge-trapping layer, any other insulating material having a charge trapping property may be used as the charge trapping layer and are also included within the scope of this invention. For example, an oxide layer with defects, an Al 2 O 3  layer etc. may also be used as the charge-trapping layer. 
   The present invention will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. 
   According to the embodiments of the present invention, in the sub-100-nm regime, a 2-bit SONOS memory using CHEI includes two portions of ONO dielectric layers disposed under a gate, which are physically separated from each other in order to appropriately adjust dispersion of electrons or holes generated during repeated programming and erasing cycles. Thus, by appropriately adjusting the thickness of a gate oxide layer formed on a portion of a substrate between the two-separated ONO dielectric layers, a short channel phenomenon can be minimized. 
   Also, the embodiments of the present invention provide a series of processing methods for manufacturing a next-generation 2-bit SONOS memory through a reverse self-alignment process using spacers. This leads to solutions not only to the alignment error between a gate and an ONO dielectric layer, which gets more serious with a reduction in the gate linewidth, but also to limitations on the minimum linewidth required for photolithography. Also, an ONO dielectric layer to be disposed under a gate can be separated into two portions to form a precisely symmetric structure. 
   The embodiments of the present invention can be categorized into two groups according to structural types. The first group belongs to a single-gate structure, in which while the total gate dimension remains the same as in a conventional structure, and the ONO dielectric layer is separated into two portions instead of a single ONO dielectric layer in the conventional structure. The second group belongs to a triple-gate structure, in which the linewidth and the total gate dimension are the same as those of the single-gate SONOS. The triple-gate structure includes two gates disposed on two-separated ONO dielectric layers and a third (intermediate) gate formed on a silicon oxide layer disposed between the two-separated ONO dielectric layers. In the triple-gate structure, different amounts of voltages can be applied to the 3 gates. 
   Embodiment 1: a Twin-ONO-type SONOS with a Single Gate 
     FIGS. 5A through 5K  are schematic cross-sectional views illustrating a twin-ONO-type SONOS memory according to a first embodiment of the present invention. 
   Referring to  FIG. 5A , as a starting material for manufacturing a SONOS memory, a p-type substrate is prepared. For example, as shown in  FIG. 5A , a silicon ( 120 )-on-insulator ( 110 ) (SOI) substrate is prepared. Here, the SOI substrate exhibits p-type conductivity and serves as a p-type substrate. However, a typical bulk silicon substrate may be substituted for the SOI substrate. Afterwards, a field region is formed using a device isolation technique on the silicon layer  120 , to define an active region. The device isolation technique may be, for example, a shallow trench isolation, a self-aligned shallow trench isolation, or a LOCOS. 
   Referring to  FIG. 5B , an oxide-silicon-oxide (ONO) dielectric layer  500  is formed on a Si channel region of the silicon layer  120 . The ONO dielectric layer  500  can be formed by a known method and substantially includes a silicon oxide layer  500   a , a silicon nitride layer  500   b , and a silicon oxide layer  500   c , which are sequentially stacked. Each of the silicon oxide layers  500   a  and  500   c  may be formed of a thermal oxide layer, a chemical-vapor-deposition (CVD) layer, or a combination thereof. Afterwards, the silicon oxide layers  500   a  and  500   c  may be thermally treated to obtain a dense and stable resultant structure. Here, the thermal treatment may be performed at a temperature of about 700° C. to 1100° C. 
   A buffer layer  600  may be formed on the entire surface of the ONO dielectric layer  500 . Afterwards, the buffer layer  600  is patterned using photolithographic and etching processes so as to form a trench  601 , which exposes a lengthy upper portion of the ONO dielectric layer  500 , in the buffer layer  600 . The etching process may be an isotropic etching process or an anisotropic etching process. 
   The buffer layer  600  is used to physically separate the ONO dielectric layer  500  of the SONOS into two portions, which will be selectively removed again later. Accordingly, to serve as an appropriate sacrificial layer, the buffer layer  600  is preferably formed of an insulating material having a sufficient etch selectivity with respect to the ONO dielectric layer  500 . 
   Referring to  FIG. 5C , first conductive spacers  700  are formed on the inner walls of the trench  601 . To form the first conductive spacers  700 , a conductive material is deposited to a predetermined thickness and then anisotropically etched using an etchback process. The conductive material for the first conductive spacers  700  is, for example, conductive polysilicon or conductive amorphous silicon, which are widely used for a gate of a SONOS. To endow conductivity to polysilicon or amorphous silicon, an ion implantation process may be further implemented or doping may be performed in-situ during the deposition process. 
   Referring to  FIG. 5D , a portion of the ONO dielectric layer  500 , which is still exposed after forming the first conductive spacers  700 , is removed using the first conductive spacers  700  as an etch mask. Preferably, an anisotropic etch process is used to finely control the linewidth of the removed portion. The linewidth of the etched portion is determined by the linewidth of the trench  601  and the linewidth of the first conductive spacers  700 . The etching process allows the silicon layer  120  of the SOI substrate to be exposed. As a result, a central portion of the ONO dielectric layer  500  is removed, thus separating the ONO dielectric layer  500  into two portions. 
   Referring to  FIG. 5E , a gate dielectric layer  800  is formed on the silicon layer  120  and the resulting structure shown in  FIG. 5D . For example, the gate dielectric layer  800  may be formed of silicon oxide using thermal oxidation or CVD. The gate dielectric layer  800  is formed along the profile of the first conductive spacers  700  such that a concave portion  801  is formed between the first conductive spacers  700 . Substantially, the gate dielectric layer  800  may be used as a gate oxide layer between the two-separated ONO dielectric layers. Also, by adjusting the thickness of the gate dielectric layer  800 , a short channel effect can be reduced in the SONOS. 
   Referring to  FIG. 5F , a second conductive layer (not shown) is formed on the gate dielectric layer  800  all over the substrate to fill the concave portion  801 , i.e., a gap between the first conductive spacers  700 . The second conductive layer may be formed of various conductive materials, for example, conductive polysilicon or amorphous silicon. To endow conductivity to polysilicon or amorphous silicon, an ion implantation process may be further implemented or in-situ doping may be performed during the deposition process. Afterwards, the second conductive layer is etched using an etchback process to form second conductive layer  900 , as shown in  FIG. 5F , whose top surface is at a lower level than the top surface of the first conductive spacers  700  and limited to inside the trench  601 . The etchback process may use an anisotropic etch process or CMP or both. This etchback process also exposes the gate dielectric layer  800  at either side of the second conductive layer  900 . 
   Referring to  FIG. 5G , a portion of the gate dielectric layer  800 , which is exposed by the second conductive layer  900 , is selectively removed to expose the top surface of the first conductive spacers  700  and the top surface of the buffer layer ( 600  of  FIG. 5F ). Here, the etch process may be a first wet etch process. Afterwards, the buffer layer  600 , exposed by the selective removal of a portion of the gate dielectric layer  800 , is also selectively removed until the top surface of the ONO dielectric layer  500  is exposed. To ensure selective removal, the buffer layer  600  is preferably formed of a material having a sufficient etch selectivity with respect to the first conductive spacers  700  and the second conductive layer  900 . For example, this etch process may be a second wet etch process that is different from the first wet etch process. Thus, a portion of the ONO dielectric layer  500 , which is adjacent to the first conductive spacers  700 , is exposed. 
   Referring to  FIG. 5H , the portion of the ONO dielectric layer  500 , which is exposed by the first conductive spacers  700 , is selectively removed using the first conductive spacers  700 ,and the second conductive layer  900  as an etch mask. Thus, twin ONO dielectric layers  500  of the SONOS are patterned. These twin ONO dielectric layers  500  form a symmetric structure through a reverse self-alignment process using the first conductive spacers  700  and the buffer layer  600 . Since the gate dielectric layer  800  is positioned between the twin ONO dielectric layers  500 , the ONO dielectric layer  500  is physically separated into two portions. 
   Referring to  FIG. 5I , impurity ions are implanted into the silicon layer  120  of the SOI substrate, which is exposed by patterning the twin ONO dielectric layers  500 , so as to form a first diffusion layer  121 . When the silicon layer  120  is a p-type substrate, the first diffusion layer  121  may be formed of n-type impurity ions, and when the silicon layer  120  is an n-type substrate, the first diffusion layer  121  may be formed of p-type impurity ions. 
   Referring to  FIG. 5J , second insulating spacers  750  are formed on the exposed sidewalls of the first conductive spacers  700 . The second insulating spacers  750  are formed of an insulating material, such as silicon nitride or silicon oxide, using thermal oxidation or CVD followed by an anisotropic etch process. Impurity ions are implanted into the exposed first diffusion layer  121  (formed earlier in silicon layer  120 , as shown in  FIG. 5I ) using the second insulating spacers  750  as an ion implantation mask, thereby forming a second diffusion layer  125 . The first diffusion layer  121  and the second diffusion layer  125  together serve as a source and a drain of a SONOS memory cell. 
   Referring to  FIG. 5K , a first silicide layer  910  is formed to electrically connect the first conductive spacers  700  and the second conductive layer  900 , and a second silicide layer  920  is formed for being electrically connected to the first diffusion layer  121  through the second diffusion layer  125 . If the first conductive spacers  700  and the second conductive layer  900  are preferably formed of conductive polysilicon, the first suicide layer  910  and the second silicide layer  920  are selectively formed using silicidation. 
   Afterwards, subsequent processes can follow a typical method of manufacturing a semiconductor device. 
   Thus, the afore-described processes result in the formation of two-separated and symmetric twin ONO dielectric layers  500  as shown in  FIG. 5K . Thus, dispersion of electrons and holes, which are generated during programming and erasing, can be adjusted appropriately. Also, the gate dielectric layer  800 , formed between the two-separated ONO dielectric layers  500 , can function as a gate oxide layer of the second conductive layer  900 . Here, the thickness of the gate dielectric layer  800  can be adjusted independent of the thickness of the ONO dielectric layer  500 . Thus, since the thickness of the gate dielectric layer  800  or the gate oxide layer can be appropriately adjusted, a short channel phenomenon can be reduced. 
   Further, in the first embodiment described with reference to  FIGS. 5A through 5K , a reverse self-alignment process is used so as to overcome photolithographic limitations of the minimal linewidth. Thus, the symmetric twin ONO dielectric layers  500  can be effectively formed. 
   Embodiment 2: a Twin-ONO-type SONOS with 3 Gates 
   The second embodiment, unlike the first embodiment, deals with a triple-gate-type SONOS memory device. The same reference numerals in the first and second embodiments represent the same element. 
     FIGS. 6A through 6J  are schematic cross-sectional views illustrating a twin-ONO-type SONOS memory according to the second embodiment of the present invention. 
   Referring to  FIG. 6A , as described with reference to  FIG. 5A , a silicon ( 120 )-on-insulator ( 110 ) substrate is prepared as a starting material to manufacture a SONOS memory. Afterwards, as described with reference to  FIG. 5B , an ONO dielectric layer  500  for a memory is formed on a Si channel region of the silicon layer  120 . 
   A first conductive layer  550  is formed on the ONO dielectric layer  500 . The first conductive layer  550  may be formed of various conductive materials, for example, conductive polysilicon or amorphous silicon. As described with reference to  FIG. 5B , a buffer layer  600  is formed on the entire surface of the first conductive layer  550 . Afterwards, the buffer layer  600  is patterned using photolithographic and etching processes so as to form a trench  601 , which exposes a lengthy portion of the top surface of the first conductive layer  550 , in the buffer layer  600 . 
   Referring to  FIG. 6B , first insulating spacers  701  are formed on the inner walls of the trench  601 . The first insulating spacers are preferably formed of an insulating material that is other than the buffer layer  600  and has a sufficient etch selectivity with respect to the buffer layer  600 . To form the first insulating spacers  710 , an insulating material is deposited to a predetermined thickness and then anisotropically etched using an etchback process. 
   Referring to  FIG. 6C , a portion of the first conductive layer  550 , which is exposed by the first insulating spacers  710 , and then a portion of the ONO dielectric layer  500 , which is originally under the first conductive layer  550 , are removed using the first insulating spacers  710  as an etch mask. Preferably, an anisotropic etch process is used to finely control the linewidth of the removed portions. The linewidth of the etched portion is determined by the linewidth of the trench  601  and the linewidth of the first insulating spacers  710 . The etching process allows the silicon layer  120  of the SOI substrate to be exposed. 
   Referring to  FIG. 6D , as also described with reference to  FIG. 5E , a gate dielectric layer  800  is formed on the silicon layer  120  such that a concave portion  801  is formed between the first insulating spacers  710 . 
   Referring to  FIG. 6E , as also described with reference to  FIG. 5F , a second conductive layer is formed (not shown) all over on the gate dielectric layer  800  to fill the concave portion  801 , i.e., a gap between the first insulating spacers  710 . The second conductive layer is preferably formed of conductive silicon. Afterwards, the second conductive layer is etched using an etchback process to form the second conductive layer  900  shown in  FIG. 5F . The etching is done until the top surface of the second conductive layer  900  is at a lower level than the top surface of the first insulating spacers  710 . This etching step also exposes the gate dielectric layer  800  at either side of the second conductive layer  900 . The etchback process may use an anisotropic etch process or CMP or both. 
   Referring to  FIG. 6F , a capping insulating layer  950  is formed on the second conductive layer  900  and connected to the exposed gate dielectric layer  800 . When the second conductive layer  900  is preferably formed of conductive polysilicon, then the capping insulating layer  950  can be formed by oxidizing the top surface of the second conductive layer  900  to a predetermined depth. 
   Referring to  FIG. 6G , a portion of the gate dielectric layer  800 , which is exposed at either side of the capping insulating layer  950 , is selectively removed to expose the top surface of the first insulating spacers  710  and the top surface of the buffer layer ( 600  of  FIG. 6F ). Here, the etch process may be a first wet etch process. Afterwards, the buffer layer  600 , which is exposed by the first insulating spacers  710  after the selective removal of a portion of the gate dielectric layer  800 , is also selectively removed until the top surface of the first conductive layer  550  is exposed. Here, the buffer layer  600  is preferably removed having a sufficient etch selectivity with respect to the first insulating spacers  710  and the capping insulating layer  950 . For example, this etch process may be a second wet etch process that is different from the first wet etch process. 
   Referring to  FIG. 6H , the portion of the first conductive layer  550 , which is exposed by the first insulating spacers  710 , is selectively removed using the first insulating spacers  710  as an etch mask. Thus, the first conductive layer  550  is patterned, and patterned portions of the first conductive layer  550  become a first gate  551  and a second gate  553 . 
   A portion of the ONO dielectric layer  500 , which is exposed adjacent to the first gate  551  and the second gate  553 , is then selectively removed. Thus, as also described with  FIG. 5H , twin ONO dielectric layers  500  of the SONOS are patterned. Afterwards, as also described with reference to  FIG. 5I , impurity ions are implanted into the silicon layer  120  of the SOI substrate, which is exposed by patterning the twin ONO dielectric layers  500 , so as to form a first diffusion layer  121 . 
   Referring to  FIG. 6I , second insulating spacers  750  are formed on the exposed sidewalls of the first insulating spacers  710 , the sidewalls of the first and second gates  551  and  553  and the underlying twin ONO dielectric layers  500 . To form the second insulating spacers  750 , an insulating material is deposited and then etched using an anisotropic etch process. Impurity ions are implanted into the exposed silicon layer  120 , thereby forming a second diffusion layer  125 . Afterwards, the capping insulating layer ( 950  of  FIG. 6H ), which may remain on the second conductive layer  900 , is selectively removed until the top surface of the second conductive layer  900  is exposed. The second conductive layer  900  becomes a third gate independent of the first gate  551  and the second gate  553 . 
   Referring to  FIG. 6J , a third silicide layer  950  is formed for being electrically connected to the second conductive layer  900 , and a second silicide layer  920  is formed for being electrically connected to the first diffusion layer  121  through the second diffusion layer  125 . If the second conductive layer  900  is preferably formed of conductive polysilicon, the third silicide layer  950  and the second silicide layer  920  are selectively formed using silicidation. 
   Afterwards, subsequent processes can follow a typical method of manufacturing a semiconductor device. 
   Thus, in the second embodiment of the present invention, by using the afore-described processes with reference to  FIGS. 6A through 6J , two-separated and symmetric twin ONO dielectric layers  500  as well as 3 independent gates are formed. 
   Embodiment 3: an Example Twin-ONO-type SONOS with a Single Gate 
   The third embodiment of the present invention, unlike the first embodiment, deals with a transformed SONOS memory with a single gate. The same reference numerals in the first, second and third embodiments represent the same element. 
     FIGS. 7A through 7K  are schematic cross-sectional views illustrating a twin-ONO-type SONOS memory according to the third embodiment of the present invention. 
   Referring to  FIG. 7A , as described with reference to  FIG. 5A , a silicon ( 120 )-on-insulator ( 110 ) substrate is prepared as a starting material to manufacture a SONOS memory. Then, a first buffer layer  630  and a second buffer layer  600  are formed. As also described with reference to  FIG. 5B , the second buffer layer  600  is used as a sacrificial layer during patterning of a subsequent ONO dielectric layer  500 . The first buffer layer  630  is used to prevent etching damage of the silicon layer  120  during patterning or removal of the second buffer layer  600 . The second buffer layer  600  can function as a pad layer or an etch stopper. Thus, the first buffer layer  630  may be formed of an insulating material that is other than the second buffer layer  600  and has an etch selectivity with respect to the second buffer layer  600 . 
   Thereafter, as also described with reference to  FIG. 5B , the second buffer layer  600  is patterned using an anisotropic etch process, thereby forming a trench  601 . 
   Referring to  FIG. 7B , a portion of the first buffer layer ( 630  of  FIG. 7A ), which may remain on the bottom part of the trench  601 , is removed using a wet etch process until the top surface of the silicon layer  120  is exposed. Afterwards, an ONO dielectric layer  500  for a memory is stacked on a Si channel region of the silicon layer  120  and on the sidewalls of the trench  601  of the second buffer layer  600 . Here, the ONO dielectric layer  500  can be formed by a known method. Substantially, as also described with reference to  FIG. 5B , each of silicon oxide layers  500   a  and  500   c  may be formed of a thermal oxide layer or a CVD layer. The oxide layer  500   a  shown in  FIGS. 7B–7K  is formed by a thermal oxidation step. Due to this reason, the oxide layer  500   a  is not formed on the sidewalls of the trench  601  in the second buffer layer  600 , which may be a nitride layer. The nitride layer  500   b  and the oxide layer  500   c  may be formed by a CVD process, resulting the presence of these two layers on the sidewalls of the trench  601 . 
   Referring to  FIG. 7C , as also described with reference to  FIG. 5C , first conductive spacers  700  are formed on the ONO dielectric layer  500  formed on the inner walls of the trench  601 . The first conductive spacers may be formed of conductive silicon. 
   Referring to  FIG. 7D , a portion of the ONO dielectric layer  500 , which is exposed by the first conductive spacers  700 , is selectively removed using the first conductive spacers as an etch mask. As described with reference to  FIG. 5D , an anisotropic etch process is preferably used. Thus, a silicon layer  120  of the SOI substrate is exposed. The anisotropic etch process also removes ONO dielectric layers formed on a top surface of the second buffer layer  600  exposing the top surface of the second buffer layer  600 . 
   Referring to  FIG. 7E , as also described with reference to  FIG. 5E , a gate dielectric layer  800  is formed on the exposed silicon layer  120  such that a concave portion  801  is formed between the first conductive spacers  700 . Here, the gate dielectric layer  800  can be extended onto the second buffer layer  600 , which will be exposed during an etch process as described with reference to  FIG. 7D . The gate dielectric layer is formed of silicon oxide using thermal oxidation or CVD. 
   Referring to  FIG. 7F , as described with reference to  FIG. 5F , a second conductive layer  900  is formed on the gate dielectric layer  800  to fill the concave portion  801 , i.e., a gap between the first conductive spacers  700 . The top surface of the second conductive layer  900  is formed at a lower level than the top surface of the first conductive spacers  700 , using the same procedure as described with reference to  FIG. 5F . The second conductive layer may be formed of conductive silicon. 
   Referring to  FIG. 7G , as described with reference to  FIG. 5G , a portion of the gate dielectric layer  800 , which is exposed by the second conductive layer  900 , is selectively removed using a first wet etch process to expose the top surface of the first conductive spacers  700  and the top surface of the second buffer layer ( 600  of  FIG. 7F ). Afterwards, as also described with reference to  FIG. 5G , the second buffer layer  600 , which is exposed by the selective etching of the gate dielectric layer  800 , is selectively removed using a second wet etch process. Here, if the second buffer layer  600  is preferably formed of an insulating material that is similar to a silicon nitride layer  500   b  of the ONO dielectric layer  500 , for example, silicon nitride, while the second buffer layer  600  is being removed, a portion of the exposed silicon nitride layer  500   b  of the ONO dielectric layer  500  may also be removed. Nevertheless, an ONO dielectric layer portion, which is touching the silicon layer  120  and is used as a substantial gate ONO dielectric layer  500  in the SONOS, can be protected by the upper silicon oxide layer  500   c  of the ONO dielectric layer  500 . 
   Referring to  FIG. 7H , a portion of the ONO dielectric layer  500 , which is exposed by the first conductive spacers  700 , (i.e., a portion of the lower silicon oxide layer  500   a  and the remaining portion of the first buffer layer  630 ) is selectively removed using the first conductive spacers  700  and the second conductive layer  900  as an etch mask. Thus, twin ONO dielectric layers  500  of the SONOS are patterned. Unlike in the first embodiment, even after the ONO dielectric layer  500  is patterned, the silicon oxide layer  500   c  of the ONO dielectric layer  500  is still extended to the sidewalls of the first conductive spacers  700 . Nevertheless, the patterned ONO dielectric layer  500  is used as a substantial ONO dielectric layer of the SONOS as in the first embodiment. 
   Referring to  FIG. 7I , as also described with reference to  FIG. 5I , impurity ions are implanted into the silicon layer  120  of the SOI substrate, which is exposed by patterning the twin ONO dielectric layers  500 , so as to form a first diffusion layer  121 . 
   Referring to  FIG. 7J , as also described with reference to  FIG. 5J , second insulating spacers  750  are formed on the upper silicon oxide layer  500   c  of the ONO dielectric layer  500 , which is extended to the sidewalls of the first conductive spacers  700 . Afterwards, as also described with reference to  FIG. 5J , impurity ions are implanted into the exposed silicon layer  120  using the second insulating spacers  750  as an ion implantation mask, thereby forming a second diffusion layer  125 . 
   Referring to  FIG. 7K , as also described with reference to  FIG. 5K , a first silicide layer  910  is formed to electrically connect the first conductive spacers  700  to the second conductive layer  900 , and a second silicide layer  920  is formed and is electrically connected to the first diffusion layer  121  through the second diffusion layer  125 . 
   Afterwards, subsequent processes can follow a typical method of manufacturing a semiconductor device. 
   Thus, in the third embodiment of the present invention, by using the afore-described processes with reference to  FIGS. 7A through 7K , two-separated and symmetric twin ONO dielectric layers  500  are formed. 
   Embodiment 4: Another Twin-type SONOS Example with a Single Gate 
   The fourth embodiment of the present invention, unlike the first embodiment and the third embodiment, deals with another transformed example of a SONOS with a single gate. The same reference numerals in the first and fourth embodiments represent the same element. 
     FIGS. 8A through 8J  are schematic cross-sectional views illustrating a twin-ONO-type SONOS memory according to a fourth embodiment of the present invention. 
   Referring to  FIG. 8A , as also described with reference to  FIG. 5A , a silicon ( 120 )-on-insulator ( 110 ) substrate is prepared as a starting material to manufacture a SONOS memory. Afterwards, as also described with reference to  FIG. 5B , an ONO dielectric layer  500  is formed, and a buffer layer  600  having a trench  601  is formed on the SOI substrate where the ONO dielectric layer  500  is formed. Next, first insulating spacers  770  are formed on the inner walls of the trench  601 . Here, unlike the first conductive spacers  700  shown in  FIG. 5C , the first insulating spacers  770  may be formed of an insulating material other than the buffer layer  600  or a photoresist material. The first insulating spacers  770  are used as a sacrificial layer unlike the first insulating spacers  710  in the second embodiment. 
   Referring to  FIG. 8B , as also described with reference to  FIG. 5D , a portion of the ONO dielectric layer  500 , which is exposed by the first insulating spacers  770 , is removed using the first insulating spacers  770  as an etch mask, so as to separate the ONO dielectric layer  500  into two portions. 
   Referring to  FIG. 8C , the first insulating spacers  770  are removed. 
   Referring to  FIG. 8D , a portion of the upper silicon oxide layer  500   c , which is exposed by removing the first insulating spacers  770 , is selectively removed using the buffer layer  600  as an etch mask, so as to expose a portion of the silicon nitride layer  500   b.    
   Referring to  FIG. 8B , as also described with reference to  FIG. 5E , a gate dielectric layer  800  is formed to cover the exposed silicon layer  120 , exposed silicon nitride layer  500   b  and the buffer layer  600 . For example, the gate dielectric layer  800  may be formed of silicon oxide using thermal oxidation or CVD. 
   Referring to  FIG. 8F , a conductive layer  930  is formed on the gate dielectric layer  800  to fill a gap in the buffer layer  600 . The conductive layer may be formed of various conductive materials, such as conductive polysilicon. The conductive layer  930  is formed by blanket deposition followed by etching using an etchback process or CMP or both, so that the conductive layer  930  is limited to inside the trench  601 . 
   Referring to  FIG. 8G , as also described with reference to  FIG. 5G , a portion of the gate dielectric layer  800 , which is exposed by the conductive layer  930 , is selectively removed until the top surface of the buffer layer ( 600  of  FIG. 8F ) is exposed. Here, a first wet etch process is preferably used. Afterwards, as also described with reference to  FIG. 5G , the exposed buffer layer  600  is selectively removed using a second wet etch process, thereby exposing the top surface of the ONO dielectric layer  500 . 
   Referring to  FIG. 8H , an exposed portion of the ONO dielectric layer  500  is selectively removed using the conductive layer  930  and the gate dielectric layer  800  as an etch mask. Thus, twin ONO dielectric layers  500 ′ of the SONOS are patterned. Substantially, the twin ONO dielectric layers  500 ′ are composed of new elements, i.e., the remaining portion  800   a  of the gate dielectric layer  800 , the silicon nitride layer  500   b , and the lower silicon oxide layer  500   a.    
   Referring to  FIG. 8I , as described with reference to  FIG. 5I , impurity ions are implanted into the silicon layer  120  of the SOI substrate  120 , which is exposed by patterning the twin ONO dielectric layers  500 ′, thereby forming a first diffusion layer  121 . 
   Referring to  FIG. 8J , second insulating spacers  750  are formed on the exposed sidewalls of the gate dielectric layer  800 . To form the second insulating spacers  750 , for example, a silicon nitride layer is deposited and then etched using an anisotropic etch process. As also described with reference to  FIG. 5J , impurity ions are implanted into the exposed first diffusion layer  121  using the second insulating spacers  750  and the layers inside the spacers as an ion implantation mask, thereby forming a second diffusion layer  125 . 
   Thus, in the fourth embodiment of the present invention, as described above with reference to  FIGS. 8A through 8J , a gate is formed of the conductive layer  930 , and a SONOS cell including two-separated twin ONO dielectric layers  500 ′ is formed. 
   Afterwards, subsequent processes can follow a typical method of manufacturing a semiconductor device. 
   In the afore-described embodiments, a 2-bit SONOS memory using CHEI can be manufactured by physically separating an ONO dielectric layer disposed under a gate using reverse spacers. By separating the ONO dielectric layer into twin portions, dispersion of electrons and holes, which may be obtained from programming and erasing, can be adjusted appropriately. Also, since the thickness of a gate dielectric layer, which is formed between the two-separated ONO dielectric layers, can be adjusted appropriately, a short channel phenomenon can be suppressed. 
     FIGS. 9A and 9B  illustrate charge distributions using a simulation model, and explain advantages of the twin-ONO-type SONOS memory according to the embodiments of the present invention. 
   In both  FIGS. 9A and 9B , it is considered that the linewidth of a gate is 0.12 μm, and 5 V and 3 V are applied to the gate and the drain, respectively (here, all the other connections are grounded). Next, programming is performed by applying a stress for 1 μs, and in this state, the degree of dispersion of trapped charges is measured using a simulation model. 
     FIG. 9A  illustrates measurement results of two-separated ONO dielectric layers (i.e., ONO(400 Å) layer/O(400 Å) layer/ONO(400 Å) layer) according to the embodiments of the present invention. On the other hand,  FIG. 9B  shows measurement results of a conventional structure, in which an ONO dielectric layer (i.e., an ONO (400 Å) layer) is extended over the entire channel region between the source/drain junctions. 
   While  FIG. 9B  illustrates expansive dispersion of trapped charges due to a short channel length of 0.12 μm,  FIG. 9A  illustrates artificially controlled dispersion of programmed charges due to the physical separation of the ONO dielectric layer. In  FIG. 9B , tailed charges hinder 2-bit operations. Also, the repeated programming and erasing cycles bring about accumulation of charges in a central channel region between junctions, thereby degrading endurance of the SONOS. Further, as charges are redistributed toward the channel region during a read operation after the programming, the retention characteristic gets worse. Contrary to this, referring to  FIG. 9A , the present invention can ameliorate the 2-bit operations, endurance, and retention characteristic. 
   Meanwhile, in the present embodiments, reverse spacers are formed using a buffer layer with a trench. Thus, even without increasing its dimension in the direction of a gate length, an ONO dielectric layer to be disposed under the spacers can be separated into twin portions to form a precisely symmetric structure. As a result, a 2-bit SONOS with a single gate and two ONO dielectric layers can be obtained using a reverse self-alignment process irrespective of photolithographic limits. Also, after insulating spacers are formed on both sidewalls of a gate, silicidation is carried out to reduce resistances of the gate and junction diffusion regions. 
   As a consequence, even if the linewidth of a memory gate is 0.10 μm or less, a SONONS nonvolatile memory device with a stable 2-bit characteristic can be manufactured. 
   Preferred embodiments of the present invention have been disclosed herein and, although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. For example, the nitride layer in the ONO dielectric layers as described above is used as a charge trapping layer. Such charge trapping layers have charge trapping sites that have good trapping ability for both electrons and holes. While the above description of the present invention is described with reference to a silicon nitride layer, any other insulating material having a charge trapping property, such as an oxide layer with defects, an Al 2 O 3  layer etc., may be used as the charge trapping layer and are also included within the scope of this invention. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.