Abstract:
A device for powering an electronic circuit that applies at least a first voltage or a second voltage, different from the first voltage, to the electronic circuit. The device includes a performance monitor that receives an item of information defining a constraint and determines a first duration and a second duration, such that the operation of the electronic circuit at a first frequency associated with the first voltage for the first duration, and at a second frequency associated with the second voltage for the second duration, complies with the constraint. The device applies the first voltage and the first frequency to the circuit for the first duration and the second voltage and the second frequency for the second duration.

Description:
PRIORITY CLAIM 
       [0001]    This application is a nationalization under 35 U.S.C. 371 of PCT Application No. PCT/FR2009/050369, filed Mar. 6, 2009, which claims priority to French Patent Application No. 0851471, filed Mar. 6, 2008, and incorporated by reference herein. 
     
    
     TECHNICAL FIELD 
       [0002]    The present invention relates to a device for powering an electronic circuit, in particular a digital circuit, and an associated method. 
       BACKGROUND 
       [0003]    In order to optimize the supply of power to an electronic circuit (in particular in the case of digital circuits), it has been proposed to adapt the supply of power to the performance required at a given time in the operation of the electronic circuit. 
         [0004]    The current design of numerous electronic circuits, in particular digital electronic circuits (and notably those produced in CMOS technology), is such that the energy consumed to perform a given set of operations increases with the power supply voltage used, which is imposed by the frequency at which the circuit is required to operate. 
         [0005]    It has thus appeared possible to optimize power consumption by adapting the supply voltage to a level as low as possible but sufficient to ensure reliable operation at the required level of performance (i.e. at the required clock frequency in the case of a synchronous circuit). 
         [0006]    The paper “ Low - Power Operation Using Self - Timed Circuits and Adaptive Scaling of the Supply Voltage ” by L. S. Nielsen et al. in the journal IEEE VLSI volume 2, number 4, December 1994, thus introduces the concept of adaptive voltage scaling in the context of asynchronous logic systems. 
         [0007]    Adapting the supply voltage to the operating frequency of synchronous digital circuits has also been proposed, notably in the papers “ A Dynamic Voltage Scaled Microprocessor System ”, by T. D. Burd et al., in the journal IEEE JSSC volume 35, number 11, November 2000, and “ Closed - Loop Adaptive Voltage Scaling Controller for Standard - Cell ASICs ”, by S. Dhar et al., in proceedings of ISLPED, August 2002. 
         [0008]    Other solutions have been proposed more recently in the same line of thinking, notably in the paper “ Dynamic Voltage and Frequency Management for a Low - Power Embedded Microprocessor ”, by M. Nakai et al., in the journal IEEE JSSC volume 40, number 1, January 2005, and in the paper “ Next Generation SoC Power Management ”, by J. Pennanen et al., in the journal Electronics Product Design, March 2007. 
         [0009]    Although these systems make it possible to optimize electrical power consumption by adapting the supply voltage to the performance constraints of the electronic circuit (generally expressed in terms of the operating frequency required by the applications implemented by the electronic circuit), on the other hand, because of their design, they require a power supply module able to deliver a voltage variable over a continuous range of values throughout operation, generally implemented in the form of a DC-DC converter. 
         [0010]    The presence of such a module causes problems regardless of the technology envisaged: the use of external choppers is naturally not suited to the integration of all the components in an integrated circuit; because of the presence of numerous passive components, the use of internal choppers is very costly (in terms of substrate area or because of the processes used); as for linear converters, they suffer from low efficiency. 
       SUMMARY 
       [0011]    In the above context, the invention proposes a device for powering an electronic circuit able to apply at least a first voltage or a second voltage different from the first voltage to the electronic circuit, characterized in that it comprises: 
         [0012]    means for determining a first frequency associated with the first voltage as a function of at least one operating parameter of the circuit; 
         [0013]    means for receiving information defining a constraint; 
         [0014]    means for determining a first duration and a second duration which are such that the operation of the circuit at the first frequency for the first duration and at a second frequency associated with the second voltage for the second duration complies with said constraint; 
         [0015]    application means able to apply to the circuit the first voltage and the first frequency for the first duration and the second voltage and the second frequency for the second duration. 
         [0016]    Thus the mean operating point of the circuit may be adjusted according to the relative weighting of the first duration and the second duration, within a continuous set of operating points, in order to be adapted optimally to the constraint received, at the same time as using a discrete number (generally two) available voltages and taking account of the operating conditions of the circuit. 
         [0017]    It may also be provided that the means for determining the first frequency are able to determine the second frequency as a function of at least one operating parameter of the circuit, in order also to use a second frequency optimized in the light of the current operating conditions. 
         [0018]    The above means may use means for measuring said parameter in the electronic circuit, examples of which are given in the description given hereinafter. 
         [0019]    For example, the information is a target frequency and the determination means are adapted to determine the first duration and the second duration so that the circuit operates at a mean effective frequency higher than the target frequency. 
         [0020]    In one embodiment that may be envisaged, the application means are able to execute periodically a period (i.e. a cycle) formed successively of the application of the first voltage and the first frequency and application of the second voltage and the second frequency. The cyclic ratio (i.e. the relative duration of application of the first frequency and the first voltage compared to the total duration of the period) is then directly linked to the mean effective frequency, as explained hereinafter. 
         [0021]    In practice, the means for determining the first duration and the second duration may be able to determine a ratio between the first duration and the second duration as a function at least of the first frequency (directly linked to the cyclic ratio just mentioned). This influences the mean effective frequency. 
         [0022]    For example, said operating parameter represents an instantaneous operating condition of the circuit, which makes it possible to update the first and second durations (for example their ratio linked to the cyclic ratio) regularly and dynamically. 
         [0023]    The means for determining the first frequency may be able to determine the second frequency as a function of at least one instantaneous operating condition of the circuit. 
         [0024]    It may then be provided that the means for determining the first duration and the second duration are able to determine a ratio between the first duration and the second duration as a function of the first frequency and the second frequency (directly linked to the cyclic ratio), and dynamically, as indicated above. 
         [0025]    In one embodiment that may be envisaged, the application means comprise a frequency selector receiving a first clock signal having the first frequency and a second clock signal having the second frequency and applying to the electronic circuit the first clock signal during the first duration and the second clock signal during the second duration. 
         [0026]    In another embodiment that may be envisaged, the application means comprise a clock generator able to generate and to apply to the electronic circuit a first clock having the first frequency during the first duration and a second clock having the second frequency during the second duration. 
         [0027]    The application means may comprise a voltage selector receiving the first voltage and the second voltage and applying to the electronic circuit the first voltage during the first duration and the second voltage during the second duration. 
         [0028]    In one possible embodiment, the voltage selector comprises: 
         [0029]    means for applying to the electronic circuit a voltage variable from a value equal to the first voltage to a value equal to the second voltage; 
         [0030]    means for selecting application of the second voltage to the electronic circuit when the variable voltage reaches the second voltage. 
         [0031]    The voltage selector may then comprise: 
         [0032]    means for applying the variable voltage to the electronic circuit when the second voltage is applied; 
         [0033]    means for eliminating the application of the second voltage when the variable voltage is applied; 
         [0034]    means for commanding the variable voltage from a value equal to the second voltage to a value equal to the first voltage. 
         [0035]    In this case the variable voltage is applied only during transition phases between the first voltage and the second voltage (phases of short duration compared to the total duration of operation); this variable voltage may then be generated by means of a linear converter, for example, without notable consequences for the efficiency over the total duration of operation. 
         [0036]    The constraint is temporal, for example (and in this case expressed in the form of a time or a frequency), although other possibilities may be envisaged, such as a mean power consumption constraint. 
         [0037]    The electronic circuit is in practice often a digital circuit, for example implemented in CMOS technology. 
         [0038]    The invention also proposes, in a manner that is novel in itself, a device for powering an electronic circuit able to apply to the electronic circuit at least a first voltage or a second voltage different from the first voltage, characterized in that it comprises: 
         [0039]    means for receiving information defining a constraint; 
         [0040]    means for determining a first number of clock cycles and a second number of clock cycles such that the operation of the circuit at a first frequency associated with the first voltage during the first number of clock cycles and at a second frequency associated with the second voltage during the second number of clock cycles complies with said constraint; 
         [0041]    application means able to apply the first voltage and the first frequency to the circuit during the first number of clock cycles and the second voltage and the second frequency during the second number of clock cycles. 
         [0042]    There may further be provided in this case synchronization means able to synchronize (the start of) the application of the first voltage and (the start of) a process to be effected with said constraint. 
         [0043]    The total number of clock cycles necessary for the process is then predetermined, for example; the constraint may in practice be the time in which it is required to effect the process. 
         [0044]    The optional features referred to above also apply in this context. There may further be provision here for the frequencies mentioned above to be predetermined (for example when designing the system or during a phase of calibrating the circuit) in order to ensure reliable operation thereof taking account of variations and drift that may be envisaged, and where applicable stored in the determination means, still with the aim of minimizing the energy consumed by the circuit. 
         [0045]    The invention further proposes a method of powering an electronic circuit by means of at least a first voltage or a second voltage different from the first voltage, characterized in that it comprises the following steps: 
         [0046]    determining a first frequency associated with the first voltage as a function of at least one operating parameter of the circuit; 
         [0047]    receiving information defining a constraint; 
         [0048]    determining a first duration and a second duration such that operation of the circuit at the first frequency during the first duration and at a second frequency associated with the second voltage during the second duration complies with said constraint; 
         [0049]    applying to the circuit the first voltage and the first frequency during the first duration and the second voltage and the second frequency during the second duration. 
         [0050]    The following steps may further be envisaged, to vary the powering of the circuit dynamically: 
         [0051]    periodically measuring the operating parameter; 
         [0052]    periodically determining the first frequency as a function of the measured parameter. 
         [0053]    It may thus be provided periodically determining a ratio between the first duration and the second duration as a function of the first frequency determined as a function of the measured parameter. 
     
    
     
       BRIEF DESCRIPTION OF DRAWING 
         [0054]    Other features and advantages of the invention will become more apparent in the light of the following description given with reference to the appended drawings, in which: 
           [0055]      FIG. 1  represents the main components of a system conforming to the teaching of the invention; 
           [0056]      FIG. 2  represents a first example of application of such a system; 
           [0057]      FIG. 3  illustrates the supply voltage and clock frequency variations present when using the  FIG. 2  system; 
           [0058]      FIG. 4  represents a second example of application of the invention; 
           [0059]      FIG. 5  shows timing diagrams illustrating the operation of the system from  FIG. 4 . 
       
    
    
       [0060]      FIG. 1  represents the components of a device for powering a functional core  10 , for example a synchronous electronic circuit implemented in CMOS digital logic. 
       DETAILED DESCRIPTION 
       [0061]    The components of this device described hereinafter may be combined in the same integrated circuit as the functional core  10 , and consequently implemented in CMOS technology. Alternatively, some or all of these components could be produced in the form of a module external to the functional core  10 . 
         [0062]    Moreover, the power supply device is described hereinafter in the form of functional components. Nevertheless, in some embodiments a plurality of functions could be implemented by the same component. 
         [0063]    It is considered here that any synchronous digital circuit is capable of operating at a maximum frequency F real     —     max , that this frequency cannot be measured directly, and that it varies in time according to intrinsic and extrinsic factors. The intrinsic factors are the variability of the fabrication process and ageing; the extrinsic factors are supply voltage and temperature. 
         [0064]    It is also considered that operating the circuit faster than this frequency causes delay faults that lead to corruption of the operation of the circuit. 
         [0065]    The power supply device from  FIG. 1  comprises an adaptation controller  12  which receives on the one hand a high voltage V high  and a low voltage V low  and on the other hand drives probes  30 ,  31 ,  32  physically situated within the core  10  in order to measure operating parameters thereof. 
         [0066]    Communication between the probes  30 ,  31 ,  32  and the adaptation controller  12  (notably to drive the probes and to feed the value of the monitored parameters back to the controller) can be effected by any appropriate means, for example using analogue or digital signals or any combination of those signal types. 
         [0067]    The adaptation controller  12  thus drives the probes  30 ,  31 ,  32  and collects the values of the operating parameters measured by those probes, notably with the aim of comparing those values with calibration values stored for example in a non-volatile memory associated with the adaptation controller or with values produced by reference sources (typically reference frequency, voltage or current). 
         [0068]    On the basis of the measured values, and where applicable the comparisons effected, the adaptation controller then estimates for each of the supply voltages envisaged in the device (in particular, for the high voltage V high  and the low voltage V low  here) what maximum frequency F practical     —     max  may be used in practice without degrading reliable operation of the system. 
         [0069]    This estimation of a frequency associated with each supply voltage value may be performed using known techniques of determining voltage-frequency pairs enabling reliable operation of the system as described in the paper, for example by simulation or by calibration by means of a speed test carried out after fabrication of the circuit. Note however that here there is provision for determining an operating frequency for each available voltage supply rather than adaptation of the voltage to a required frequency. 
         [0070]    In practice, estimation may be based on a pessimistic estimate of the maximum frequency F real     —     max  mentioned above obtained by simulation, followed by determining by means of measurements if the instantaneous operating conditions are favorable or not, and, finally, calculating for each voltage supply a frequency F estim     —     max  as close to an optimistic estimate of the frequency F real     —     max  that these operating conditions allow taking into account the relative inaccuracy of the measurements. 
         [0071]    Moreover, to compensate the evolution in time of the sources of variation, the estimation of the maximum practical frequencies F estim     —     max  associated with each supply voltage must be carried out at regular intervals, with a period depending on the time constants of the variations to be compensated. 
         [0072]    On the basis of practical maximum frequencies F estim     —     max  determined as indicated above, the adaptation controller  12  commands clock generators  16 ,  18  (to be precise a first clock generator  16  associated with the low voltage V low  and a second clock generator  18  associated with the high voltage V high  here) in order for each of the latter to provide an output clock signal (respectively H low  and H high  here) having the frequency determined by the adaptation controller  12 . 
         [0073]    A performance controller  22  receives the clock signals H low , H high  and determines the respective frequency (F low , F high ) of each of these signals, for example using a reference frequency signal F ref . The performance controller  22  could alternatively also receive the frequency values associated with each supply voltage directly from the adaptation controller  12 . The solution proposed in  FIG. 1  nevertheless enables the performance controller  22  to operate on the clock signals actually generated, as applied to the core  10  as described hereinafter. 
         [0074]    The performance controller also receives information C representing a performance constraint, for example a frequency or time constraint, to be complied with by the power supply device. This constraint is determined by the application (in the “software” sense) implemented by the core  10 , for example, notably as a function of the requirements of that application. 
         [0075]    As a function of the measured frequencies F low  and F high  of the signals H low  and H high  and the constraint information C, the performance controller  22  determines the respective durations of application of the two supply voltages, for example here in the form of the ratio X between the time of application of the high voltage V high  and the cumulative time of application of the two voltages, making it possible to comply optimally with the constraint defined in the information C. 
         [0076]    If C is a constraint F target  expressed in frequency form, the system may be dimensioned so that this frequency constraint F target  is between the values of F low  and F high  that may be envisaged, which makes it possible to obtain a ratio X between 0 and 1. 
         [0077]    The performance controller  22  may also impose operation at the high voltage V high  and at the corresponding frequency F high  if the constraint C will not be reached despite continuous operation at the latter frequency F high  (i.e. a ratio X=1) and that the constraint therefore cannot be complied with (for example if F target  F high ), in this case the device may indicate to the entity sending the constraint C that the constraint cannot be complied with, the entity sending the constraint being able either to modify the operation of the core  10  in order to reduce the constraint C or to command an increase in the voltage V high  in systems where this voltage is adjustable. 
         [0078]    If the constraint C is less than the frequency F low  associated with the low voltage V low , it is furthermore possible to operate continuously at the low voltage V low , and the associated frequency F low  (X=0) or to command the clock generator  16  to reduce the frequency (whilst retaining the low voltage V low , which does not cause any operating problems) or to switch the power supply into a standby state for part of the time, enabling this constraint C lower that F low  to be complied with. 
         [0079]    The ratio X determined by the performance controller  22  is transmitted to a transition sequencer  24  that drives a voltage selector  14  and a frequency selector  20  (respectively by means of a voltage command hop e  and a frequency command hop F ) so that the selectors  14 ,  20  respectively apply the high voltage V high  and the associated clock signal H high  for the duration defined by the performance controller  22  (here a proportion X of the time) and the low voltage V low  and the associated clock signal H low  for another duration also defined by the performance controller  22 , here the remaining time (i.e. a proportion 1−X of the time). 
         [0080]    In this context, the transition sequencer  24  ensures in particular that the low voltage V low  and the clock signal H high  associated with the high voltage V high  are never applied simultaneously, in particular during the transition phases, which would be problematic for the operation of the circuit. 
         [0081]    The voltage selector  14  receives on the one hand the voltage V high  and on the other hand the voltage V low  and applies one of these two voltages to the core  10  as a function of the command signal hop v . Similarly, the frequency selector  20  receives the clock signals H low  and H high  separately and applies one of these clock signals to the core  10  according to the command hop F . In  FIG. 1 , V core  is the voltage applied to the core  10  by the voltage selector  14  and H core  is the clock signal at the frequency F core  applied to the core  10  by the frequency selector  20 . 
         [0082]    In the practical implementation chosen for the selectors  14 ,  20 , continuous operation of the core  10  could be retained during transition phases between the two voltage values that have just been indicated or, conversely, the operation of the core  10  could be interrupted during these transitions, for example by means of synchronization information (synchro) exchanged between the core  10  and the transition sequencer  24 . In this latter case, the performance controller  22  takes account of the duration of interruption of the operation of the core  10  in determining the various durations of application of each voltage, with the aim of complying with the constraint C. 
         [0083]    Accordingly, although it uses the available voltages (only two voltages V high  and V low  here), the powering device may operate in an optimized manner adapted to a constraint C (which may for its part vary over a continuous range of values) thanks to the variable weighting of the time of use of one voltage supply relative to the other and the resulting variable (and thus adaptable to the constraint) performance. 
         [0084]      FIG. 2  represents an embodiment of the invention in an application in which the constraint to be complied with is expressed in the form of an operating frequency required by the process implemented by the digital core  110 . 
         [0085]    Each component of  FIG. 2  has been assigned a reference number increased by 100 relative to the component having the same function in  FIG. 1 . 
         [0086]    In this embodiment, an adaptation controller  112  drives a voltage probe  130  and a temperature probe  131 . 
         [0087]    The voltage probe  130  measures the supply voltage actually received by the core  110 , in particular allowing for local voltage drops caused by the resistivity of the power supply grid. 
         [0088]    The voltage measured by the probe  130  is compared to a reference voltage V ref  and can thus be converted in the adaptation controller  112  into a digital value representing this measured voltage. 
         [0089]    The temperature probe  131  also makes it possible to obtain digital information representing the value of the measured temperature. To this end, the temperature probe  131  in practice measures the voltage at the terminals of the diode forward-biased by a reference current, for example (the voltage at the terminals of the diode varying as a function of temperature); in this case the measured voltage may equally be converted into the form of digital temperature information in the adaptation controller  112 . 
         [0090]    The core  110  being subjected to two different supply voltages, as explained in detail hereinafter, the adaptation controller  112  must be able to distinguish between the various power supply phases in order to determine to which required voltage the measured voltage corresponds. To this end, communication may for example be provided between the adaptation controller  112  and the transition sequencer  124  described hereinafter (as represented in dashed line in  FIG. 2 ) or other components holding information on the applied voltage (such as the voltage selector  114  for example). Alternatively, the adaptation controller  112  may determine the supply voltage concerned (V high  or V low ) as a function of the measured voltage and a threshold (equal to V low , for example, because the measured voltage will in theory be less than the applied voltage because in particular of the voltage drops referred to above). 
         [0091]    The adaptation controller  112  may also consider invalid any measurement during which the measured voltage varies significantly (to avoid the situation in which the measurement is effected during the transition phase between the two supply voltages as described hereinafter). 
         [0092]    On the basis of the measured temperature and the measured effective supply voltages (one measured value for each possible supply voltage, here V high  and V low ), the adaptation controller  112  determines the maximum practical frequencies F max     —     estim     —     high  and F max     —     estim     —     low  respectively associated with the high voltage V high  and the low voltage V low , for example using tables stored in a non-volatile memory associated with the adaptation controller  112  or as a function of formulas determined by the characteristics of the technology used. 
         [0093]    In the case of using tables storing the maximum practical frequency values associated with measured voltage-temperature pairs, it is possible to carry out during a phase of starting up the digital circuit tests aiming to determine the maximum reliable operating frequency of the core  110  at room temperature and for a plurality of voltages, with the aim of partially updating the aforementioned table. These tests (generally called “auto-tests”) consist for example in verifying correct operation of the core  110  at increasing frequencies in order to retain the highest frequency that achieves reliable operation of the core  110 , preferably retaining a margin of uncertainty to combat any drift in the system. 
         [0094]    The maximum practical frequencies F max     —     estim     —     low  and F max     —     estim     —     high  determined in this way and respectively associated with the low voltage V low  and the high voltage V high  are respectively transmitted to a first clock generator  116  and a second clock generator  118 . 
         [0095]    Each of the clock generators  116 ,  118  is of the frequency-locked loop (FLL) type, for example, produced by means of a voltage-controlled local oscillator with low jitter and a control loop that slaves the generated frequency to the frequency set point received and to a reference frequency F ref  received by each of the clock generators  116 ,  118 . 
         [0096]    Each of the clock generators  116 ,  118  sends a performance controller  122  information representing the frequency currently generated by this clock generator (information designated F low  for the clock generator  116  and F high  for the clock generator  118 ). 
         [0097]    The clock signals H low  and H high  respectively generated by the first clock generator  116  and by the second clock generator  118  are applied to the input of a frequency selector  120  the operation of which is described hereinafter. 
         [0098]    The performance controller  122  therefore receives information representing the frequencies respectively generated by the first generator  116  and the second generator  118 , i.e. respectively associated with the low voltage V low  and the high voltage V high . The performance controller  122  also receives, for example in the form of digitally coded information, the operating frequency F target  required by the process implemented by the core  110  (which in the present application expresses the constraint with which the power supply device must comply). 
         [0099]    The ratings of the circuit at the design stage are such that this frequency constraint F target  is between the frequencies F low  and F high  of the clocks H low  and H high  and the performance controller  122  can thus determine a proportion X (in percent) of the total calculation time such that the mean effective frequency F eff =X·F high +(1−X). The frequency F low  must be higher than the target frequency F target . 
         [0100]    The mean effective frequency F eff  obtained by causing the core  110  to operate for a proportion X of the total time at the frequency F high  and the rest of the time at the frequency F low  is therefore higher than the target and thus makes it possible to comply with the constraint defined thereby. 
         [0101]    For example, F eff  is chosen to be sufficiently higher than F target  (for k or example from 1% to 10% higher) to take account of periods of transition between two phases of operation (in some cases the operation of the core  110  may be interrupted during these transition periods). 
         [0102]    The proportion X determined in this way is transmitted to the hop sequencer  124  that drives on the one hand the frequency selector  120  (by means of the command hop F ) to apply successively to the circuit  110  the two clocks H high  and H low  in order to obtain the time proportions just defined, as shown in  FIG. 3 , and on the other hand the voltage selector  114  (under the control of the signal hop v ) so that the latter applies the voltage V high  to the core  110  simultaneously with the clock H high  and the low voltage V low  simultaneously with the clock H low  (see also  FIG. 3 ), which optimizes power consumption at all times. 
         [0103]      FIG. 3  (in which F core  denotes the frequency of the clock H core  applied to the core  110  by the frequency selector  120 ) shows one example of possible operation obtained by means of the hop sequencer  124 : in this example, the hop sequencer  124  operates with a period T hop . At a time t=0, the sequencer  124  commands the selectors  114 ,  120  to go from a mode of operation at the voltage V low  and at the frequency F low  to a mode of operation at the voltage V high  and at the frequency F high , switching the voltage first by means of the selector  114  and then the frequency by means of the frequency selector  120 . 
         [0104]    At a time t=X·T hop , the sequencer  124  commands the selectors  114 ,  120  to go from the mode at voltage V high  and frequency F high  to the mode at voltage V low  and frequency F low , switching the frequency first and then the voltage. 
         [0105]    Because of the periodic operation mentioned above, the hop sequencer effects at time t=T hop  the same operation as at time t=0, and so on. 
         [0106]    Clearly, by exception, the hop sequencer  124  commands the selectors  114 ,  120  to ensure constant operation at the voltage V high  and the frequency F high  if the proportion X has the value 100%, whereas it commands constant operation at the voltage V 10  and the frequency F low  if the proportion X has the value 0. 
         [0107]    The voltage selector  114  is for example of the type described in the paper “ A Power Supply Selector for Energy -  and Area - Efficient Local Dynamic Voltage Scaling ”, by S. Miermont et al., in the proceedings of PATMOS, September 2007. The frequency selector  120  is for example of the “glitch-free” type described in U.S. Pat. No. 6,501,304. 
         [0108]    Such a voltage selector makes it possible, during a transition phase, to apply to the electronic circuit a voltage variable from a value equal to a first voltage (V low  or V high ) to a value equal to the other voltage, and then to select application of the other voltage to the electronic circuit when the variable voltage has reached that other voltage, which enables continuous powering of the electronic circuit. 
         [0109]    This voltage selector makes it possible to manage the inverse transition phases by applying the variable voltage to the electronic circuit when that other voltage is applied, removing the other voltage when the variable voltage is applied, and commanding the variable voltage to go from a value equal to this other voltage to a value equal to the first voltage. 
         [0110]    The operation that has just been described thus makes possible powering of the core  110  at the mean effective frequency F eff  referred to above, whilst optimizing at all times the voltage-frequency pair used, using only two voltage supplies. Note in this regard that the variable voltage the use of which is proposed in the example described above is used only during the brief transition phases and that recourse may therefore be had to a linear converter for the generation of this variable voltage without significant consequences as to the electrical efficiency (the voltage generated by the converter during operating phases to the voltage V high  corresponding to the maximum voltage of the latter and therefore not involving resistive losses). 
         [0111]      FIG. 4  represents an embodiment of the invention applied to the case where the functional core (referenced  210  here) is a block receiving input data periodically (i.e. every T data ) and then having a maximum time T target  (sometimes referred to as the “block latency”) available for processing this input data (this processing necessitating N clock cycles) and communicating the processed data to the next block. 
         [0112]    In  FIG. 4 , components having a function corresponding to a component from  FIG. 1  carry a reference number increased by 200 relative to that component in  FIG. 1 . 
         [0113]    The probes  230 ,  231 ,  232  used in this embodiment are ring oscillators as described for example in the paper “ Product - Representative ‘at Speed’ Test Structures for CMOS Characterization ”, by B. M. Ketchen et al., in IBM Journal of Research and Development, volume 50, No. 4/5, July 2005. 
         [0114]    In practice an oscillator  230  with “long wire” connections, an oscillator  231  based on transistors with a high threshold voltage, and an oscillator  232  based on transistors with a low threshold voltage are used, for example. An oscillator with capacitive components could equally be used, for example. 
         [0115]    An adaptation controller  212  regularly measures the frequency of each of the oscillators  230 ,  231 ,  232 , notably using a reference frequency F ref1 . Operation of the core  210  is simulated at the design stage to determine the variations of its maximum operating frequency as a function in particular of supply voltage and temperature. The variations of the frequency of each of the oscillators referred to above as a function of the same parameters (supply voltage and temperature in particular) are also known, for example thanks to the same type of simulation, so that it is possible to determine the maximum usable frequencies F max     —     estim     —     high  and F max     —     estim     —     low  at the high voltage V high  and the low voltage V low , respectively, as a function of the different frequencies of the oscillators  230 ,  231 ,  232  (for example, using a simplified model, a weighted sum). Monte-Carlo type simulations may be used in this context, for example. 
         [0116]    The operating frequencies F max     —     estim     —     high  and F max     —     estim     —     low  each associated with one of the fixed supply voltages V high  and V low  are transmitted on the one hand to a clock generator  220  (for example implemented by means of a phase-locked loop (PLL) receiving a reference signal F ref2 ) and on the other hand a performance controller  222 . 
         [0117]    On the basis of this information F max     —     estim     —     high  and F max     —     estim     —     low  and information T target  representing the latency of the block, the performance controller  222  determines the number of clock cycles in which the core  210  must operate at the high frequency F max     —     estim     —     high  (among the N clock cycles necessary for processing the data as mentioned above), also taking account of the transition time T transition  necessary to change from one mode of operation to the other, so that the processing time does not exceed the target time T target . This amounts to saying that the performance controller  222  determines the number K that satisfies the equation: 
         [0000]    
       
         
           
             
               T 
               target 
             
             = 
             
               
                 K 
                 
                   F 
                   
                     max_estim 
                      
                     _high 
                   
                 
               
               + 
               
                 
                   N 
                   - 
                   K 
                 
                 
                   F 
                   
                     max_estim 
                      
                     _low 
                   
                 
               
               + 
               
                 T 
                 transition 
               
             
           
         
       
     
         [0118]    The number K of operating cycles at the frequency F max     —     estim     —     high  (and the voltage V high ) is communicated by the performance controller  222  to a hop sequencer  224  that commands the clock generator  220  by means of a signal hop F  so that the generator  220  operates at the frequency F— max     —     estim     —     high  (received from the adaptation controller  212 ) during the first K clock cycles of the processing and at the frequency F max     —     estim     —     low  (also received from the adaptation controller  212 ) during the next N-K cycles. To this end the operation of the hop sequencer  224  and that of the core  210  are synchronized, for example by exchanging synchronization information (denoted synchro in  FIG. 4 ). 
         [0119]    As mentioned above, a transition phase of duration T transition  may be provided to take account of the time constant of the control loop of the generator  220 ; in this case the operation of the core  210  will be interrupted during this transition phase, for example, and the N clock cycles will thus be formed of K cycles before the transition period and N-K cycles after the transition period, as represented in  FIG. 5 . 
         [0120]    The hop sequencer  224  also commands a voltage selector  214  to apply the high voltage V high  during the first K clock cycles and the low voltage V low  the rest of the time, and thus notably at the end of processing the data (N-K cycles) and during phases of waiting for the next data to be processed (latency time T target  elapsed but reception time T data  not elapsed), as seen clearly in  FIG. 5  (in which A represents the activity of the core  210  and the transition time T transition  is ignored). 
         [0121]    The voltage selector  214  is for example of the type described in the paper “ VDD - Hopping Accelerator for On - Chip Power Supplies Achieving Nano - Second Order Transient Time ”, by K. Onizuka et al., in proceedings of the ASSCC, November 2005, which in particular makes interruption of the block possible during the transition referred to above. 
         [0122]    The foregoing embodiments are merely possible examples of implementation of the invention. 
         [0123]    For example, although a temporal constraint is envisaged hereinabove (expressed in the form of a frequency for a latency time to be complied with), the constraint could therefore be of a different kind; for example, it could be a mean power consumption constraint (the duration of operation at the high frequency being limited so as to comply with this constraint).