Abstract:
There is provided a testing apparatus for testing a memory-under-test, having a pin electronics section for inputting/receiving signals to/from the memory-under-test, a pattern generating section for inputting a test pattern to the memory-under-test via the pin electronics section and a judging section for receiving an output signal of the memory-under-test via the pin electronics section to judge whether or not the memory-under-test is defect-free based on the output signal, wherein the pin electronics section has an internal circuit for inputting/receiving the signal to/from the memory-under-test, a first transmission line for connecting the internal circuit with the memory-under-test and a first switch for connecting the first transmission line with earth potential when the memory-under-test is not tested and for disconnecting the first transmission line from the earth potential in testing the memory-under-test.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a testing apparatus and a testing method for testing a memory-under-test such as a semiconductor memory.  
         [0003]     More specifically, the invention relates to a testing apparatus for conducting a writing test of the memory-under-test.  
         [0004]     2. Related Art  
         [0005]     Conventionally, as a semiconductor memory, there have been known a flash memory and the like. While the semiconductor memory may be used for various uses, it requires a certain data write time in accordance to its use. Here, the data write time means a time required for finishing a writing process of predetermined data in writing the data into the semiconductor memory.  
         [0006]     A case of using such semiconductor memory for storing image data of a digital video camera will be explained below for example. In transferring data of VGA image (about 310,000 pixels) in shooting video image, its data amount per frame is about 5 Mb. The data amount per frame is reduced to 242 Kb for example by compressing the data.  
         [0007]     When a number of frames of the video image is supposed to be 30 frame per second, a transfer time per frame is about 33 ms. However, because the data transfer time contains a time for verifying operation and the like, all of that time cannot be used for writing data. Then, 8 ms in the transfer time of each frame is appropriated to the time for writing data for example. That is, in the case described above, it is necessary to be able to write the data of 242 Kb to the semiconductor memory per 8 ms.  
         [0008]     If a storage capacity of the semiconductor memory per page is 2 KB, 15 pages are necessary in order to store the data of one frame. Accordingly, in the case described above, the semiconductor memory is required to be able to write 15 pages in 8 ms.  
         [0009]     There has been known a test for measuring the data writing time as described above as an item for testing a memory-under-test such as the semiconductor memory. In this test, predetermined data is written into each page of the memory-under-test to measure the write time per page.  
         [0010]     In the conventional testing apparatus, the write time per page is specified as a testing specification. For the semiconductor memory that is required to be able to write 15 pages in 8 ms like the case described above, 8 ms/15=530 μs is specified as the write time per page.  
         [0011]     Then, when the write time per page is larger than the specified value, a block containing that page is judged to be a defective block. The block is a unit in writing data and 15 pages is assumed to be one block for example in this case.  
         [0012]     Writing of data into the defective block is inhibited when the defective block is packaged. The memory-under-test having such defective blocks by a certain number or more is discriminated as a defective product.  
         [0013]     Semiconductor memories that meet with the specification required in packaging are selected through such test.  
         [0014]     However, while the specification required in packaging demands to be able to write 15 pages in 8 ms, the conventional test demands to be able to write each page in 530 μs. The specified value in the conventional test is equal to the specification required in packaging when seen from the point of view of unit of block.  
         [0015]     However, the write time per page of the semiconductor memory is not constant and varies per page. Therefore, the condition of the specified value required in the conventional test is harder than the specification required in packaging. That is, while the specification required in packaging demands an average write time of the pages contained in the block to be 530 μs or less for example, the conventional test demands the write time of all of the pages contained in the block to be 530 μs or less.  
         [0016]     As a result, the conventional test ends up rejecting such a semiconductor memory that is supposed to have no problem in packaging, as a defective product. Due to that, the conventional test is dropping the production yield of semiconductor memories.  
         [0017]     Accordingly, it is an object of the invention to provide a testing apparatus and a testing method that are capable of solving the above-mentioned problem. This object may be achieved through the combination of features described in independent claims of the invention.  
         [0018]     Dependent claims thereof specify preferable embodiments of the invention.  
       SUMMARY OF THE INVENTION  
       [0019]     In order to solve the above-mentioned problem, a first aspect of the invention provides a testing apparatus for testing a memory-under-test, having a writing section for writing preset test data into each page of the memory-under-test to test the memory-under-test and a fail memory unit for storing the test result of the memory-under-test, wherein the fail memory unit further includes a write time measuring section for measuring a write time required for writing the test data per page, an integrating section for integrating the write time across a plurality of pages set in advance and a judging section for judging whether or not the memory-under-test is defect-free by comparing a value integrated by the integrating section with an expected value set in advance.  
         [0020]     The integrating section may integrate the write time per page group having a number of pages set in advance and the judging section may judge whether or not the page group is defect-free based on an integral value of the write time per page group.  
         [0021]     The fail memory unit may further include a fail memory for storing the judgment result for each page group while correlating with each page group. The fail memory unit may further include a subtracting section for inputting a differential value obtained by subtracting an average specification value set in advance from the write time to each page measured by the write time measuring section to the integrating section and the judging section may judge whether or not each page group is defect-free based on whether or not an integral value of the differential value is smaller than zero.  
         [0022]     The judging section may include a first judger for judging whether or not the integral value of the write time to each page group is larger than an integral expected value set in advance per page group and a second judger for judging whether or not the write time to each page contained in each page group is larger than an absolute specification value set in advance.  
         [0023]     The judging section may further include a third judger for judging, for each page group, that the page group is a defect-free block when the integral value of the write time is smaller than the integral expected value and the write time of all of the pages contained in the page group is smaller than the absolute specification value.  
         [0024]     The fail memory unit may further include an integral expected value register for storing the integral expected value in advance to feed to the first judger and an absolute specification value register for storing the absolute specification value in advance to feed to the second judger.  
         [0025]     The fail memory unit may further include a page group control section for enabling the integrating section to integrate while excluding the write time of that page and for incrementing a page number of the last page in the page group by one when the second judger judges that the write time of either one of the pages is larger than the absolute specification value.  
         [0026]     The fail memory unit may further include a third judger that judges, for each page, that the pertinent page is defect-free when the integral value of the page group to which the page belongs is judged to be less than the integral expected value and the write time is judged to be less than the absolute specification value and a fail memory for storing the judgment result for each page by correlating with the page.  
         [0027]     The fail memory unit may further include a page number register for storing the page number set in advance, a counter for counting a number of pulses of an enable signal synchronized almost with a write cycle of the test data of the writing section and a resetting section for resetting the integral value of the integrating section and the counted value of the counter when the counted value of the counter coincides with the page number stored in the page number register, and when the write time of either one of the pages is judged to be larger than the absolute specification value by the second judger, the page group control section may stop the counter from counting by one pulse of the enable signal and may inhibit the integrating section from integrating the write time of that page.  
         [0028]     The fail memory unit may further include first and second integrating sections provided in parallel, and the first page group for which the first integrating section integrates the write time and the second page group for which the second integrating section integrates the write time may have pages partially overlapping each other.  
         [0029]     The judging section may judge that the memory-under-test is defect-free when all of the values integrated by the first and second integrating sections are smaller than the expected value.  
         [0030]     A second aspect of the invention provides a testing method for testing a memory-under-test, having a writing step of writing preset test data to each page of the memory-under-test to test the memory-under-test and a storage step of storing the test result of the memory-under-test, wherein the storage step further has a write time measuring step of measuring a write time required for writing the test data per each of the pages, an integration step of integrating the write time across the plurality of pages set in advance and a judging step of judging whether or not the memory-under-test is defect-free by comparing the value integrated in the integration step with an expected value set in advance.  
         [0031]     It is noted that the summary of the invention described above does not necessarily describe all necessary features of the invention. The invention may also be a sub-combination of the features described above. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0032]      FIG. 1  is a diagram showing one exemplary configuration of a testing apparatus according to an embodiment of the invention.  
         [0033]      FIG. 2  is a diagram showing one exemplary configuration of a fail memory unit.  
         [0034]      FIG. 3  is a chart showing one exemplary operation of the fail memory unit explained in connection with  FIG. 2 .  
         [0035]      FIGS. 4A and 4B  are charts showing exemplary test results, wherein  FIG. 4A  shows the test result of a conventional testing apparatus and  FIG. 4B  shows the test result of the testing apparatus explained in connection with  FIGS. 1 through 3 .  
         [0036]      FIG. 5  is a diagram showing another exemplary configuration of the fail memory unit.  
         [0037]      FIG. 6  is a chart showing one exemplary operation of the fail memory unit explained in connection with  FIG. 5 .  
         [0038]      FIG. 7  is a diagram showing a still other exemplary configuration of the fail memory unit.  
         [0039]      FIG. 8  is a table showing one exemplary operation of the fail memory unit explained in connection with  FIG. 7 .  
         [0040]      FIG. 9  is a diagram showing a still other exemplary configuration of the fail memory unit.  
         [0041]      FIG. 10  is a table showing one exemplary operation of the fail memory unit explained in connection with  FIG. 9 .  
         [0042]      FIG. 11  is a diagram showing a still other configuration of the fail memory unit.  
         [0043]      FIG. 12  is a table showing one exemplary operation of the fail memory unit shown in  FIG. 11 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0044]     The invention will now be described based on preferred embodiments, which do not intend to limit the scope of the invention, but exemplify the invention. All of the features and the combinations thereof described in the embodiments are not necessarily essential to the invention.  
         [0045]      FIG. 1  is a diagram showing one exemplary configuration of a testing apparatus  100  according an embodiment of the invention. The testing apparatus  100  is an apparatus for testing a memory-under-test (MUT)  200  such as a semiconductor memory and has a pattern generating section  10 , a waveform control section  12 , a timing generating section  14 , a comparator  16 , a pin electronics section  18  and a fail memory unit  30 .  
         [0046]     The pattern generating section  10  generates a test pattern for testing the MUT  200  in accordance to a program set by a user for example.  
         [0047]     Signals and the like inputted to the MUT  200  are generated based on the test pattern.  
         [0048]     Based on the test pattern fed from the pattern generating section  10 , the waveform control section  12  generates a test signal to be inputted to the MUT  200 . For example, the waveform control section  12  generates a test signal indicating voltage level corresponding to the test pattern in synchronism with a timing clock fed from the timing generating section  14 . The timing generating section  14  generates the timing clock to be inputted to the waveform control section  12 .  
         [0049]     The pin electronics section  18  transmits/receives signals to/from the MUT  200 . The pin electronics section  18  has a driver  20  and a comparator  22 . The driver  20  inputs the test signal generated by the waveform control section  12  to the MUT  200 . In measuring a data write time of the MUT  200  for example, the pattern generating section  10 , the waveform control section  12  and the driver  20  function as a writing section for writing test data set in advance into each page of the MUT  200  to test the MUT  200 .  
         [0050]     The comparator  22  receives a signal outputted out of the MUT  200 .  
         [0051]     The comparator  16  converts the output signal of the MUT  200  into a binary signal by comparing whether or not signal level of the output signal is larger than a preset reference voltage level. The comparator  16  compares the signal level of the output signal with the reference voltage level corresponding to the timing signal fed from the timing generating section  14 . The comparator  16  may also compare the output signal converted into the binary signal with an expected value signal fed as described later.  
         [0052]     In measuring the data write time of the MUT  200  or example, the comparator  16  receives a ready/busy signal (hereinafter referred to as a RY/BY signal) of the MUT  200  as the output signal and detects whether or not the RY/BY signal indicates a predetermined expected value.  
         [0053]     The RY/BY signal is a signal that indicates a first logical value during a writing process of the input data and indicates a second logical value when it become ready to write next input data by finishing the writing process of the input data.  
         [0054]     Then it becomes possible to measure the data write time of each page of the MUT  200  by measuring a time when the RY/BY signal indicates the second logical value from the start of writing of the input data into each page of the MUT  200 . The fail memory unit  30  may carry out this measurement for example.  
         [0055]     The fail memory unit  30  stores the test result of the MUT  200 .  
         [0056]     For example, the fail memory unit  30  stores the data write time per page described above.  
         [0057]      FIG. 2  is a diagram showing one exemplary configuration of the fail memory unit  30 . When preset test data is written into each page of the MUT  200 , the fail memory unit  30  measures and stores the time required for writing the test data. The fail memory unit  30  of this embodiment has a write time measuring section  32 , an integrating section  34 , an integral expected value register  36 , a judging section  38 , a fail memory  40  and a bad block counter  42 .  
         [0058]     The write time measuring section  32  measures the write time required for writing the test data per page. The write time measuring section  32  may measure the write time based on the comparison result of the comparator  16 . For example, the write time measuring section  32  may receive a notice from the pattern generating section  10  that writing of the test data is started and may measure a period of time until when the RY/BY signal indicates the second logical value after receiving the notice. This measurement may be carried out by counting a system clock or the like of the testing apparatus  100  during that period of time for example.  
         [0059]     The integrating section  34  integrates the write time measured by the write time measuring section  32  across a plurality of pages set in advance. For example, the integrating section  34  may integrate the write time per page group having a preset number of pages. The page group may be a page block set in advance for the MUT  200 . A number of pages contained in each page block may be determined in accordance to a specification of the MUT  200  required in packaging it.  
         [0060]     The pattern generating section  10  feeds an enable signal and a reset signal to the integrating section  34 . The enable signal is a signal for controlling whether the integration of write time should be permitted or inhibited and the reset signal is a signal for initializing an integral value of write time in the integrating section  34 . For example, the pattern generating section  10  may permit the integrating section  34  to integrate the write time in carrying out the test for measuring the write time. The pattern generating section  10  also initializes the integral value in the integrating section  34  every time when a write time of a page group is integrated.  
         [0061]     The judging section  38  judges whether or not the MUT  200  is defect-free by comparing the value integrated by the integrating section  34  with the expected value set in advance. For example, the judging section  38  may judge whether or not the page group is defect-free based on the integral value of the write time per page group. In this case, the integral expected value register  36  stores the integral expected value per page group. The judging section  38  may judge that the page group is defective when the write time integrated by the integrating section  34  is larger than the integral expected value.  
         [0062]     The pattern generating section  10  feeds an enable signal also to the judging section  38 . This enable signal is a signal for controlling whether or not the judging section  38  is enabled to judge whether or not the page group is defect-free. When the integrating section  34  integrates the write time of a predetermined number of pages for example, the pattern generating section  10  may enable the judging section  38  to compare the integral value with the integral expected value.  
         [0063]     The fail memory  40  stores the judgment result of each page group while correlating with each page group. For example, each address of the fail memory  40  corresponds to each page group of the MUT  200  and the fail memory  40  stores each judgment result in the corresponding address. The pattern generating section  10  may control the fail memory  40  in which address it stores the judgment result for example. The judgment result stored in the fail memory  40  may be used as mask data of the corresponding page group. For example, it is possible to inhibit the use of the defective page group by using the judgment result in actually using the MUT  200 .  
         [0064]     It is also possible to omit a test of the defective page group in testing the MUT  200 .  
         [0065]     The bad block counter  42  counts a number of page groups judged to be defective by the judging section  38 . When the counted value becomes larger than a certain value set in advance, the bad block counter  42  notifies the pattern generating section  10  of that. Receiving that notice, the pattern generating section  10  stops the test of the MUT  200 .  
         [0066]     Such configuration enables the test conforming to the specification required in actually using the MUT  200  to be carried out.  
         [0067]     Therefore, it can improve the yield of the MUT  200  as compared to the conventional testing apparatus.  
         [0068]      FIG. 3  is a chart showing one exemplary operation of the fail memory unit  30  explained in connection with  FIG. 2 . A waveform of each page in  FIG. 3  is one exemplary waveform of the RY/BY signal when test data is written into that page. In this example, the RY/BY signal indicates a logic L during the test data writing process and indicates a logic H when it becomes ready to write the next test data after finishing the test data writing process.  
         [0069]     In this example, each page group (page block) has N pages, respectively. Still more, an integral expected value for one page group is assumed to be N×600 μs in this example. In this case, the conventional testing apparatus judges that the page group is defect-free when the data write time of all of the pages is 600 μs or less. The data write time of the page  1  and page  2  is larger than 600 μs in the example shown in  FIG. 3 , so that the conventional testing apparatus judges that this page group is defective.  
         [0070]     In contrary to that, the fail memory unit  30  explained in connection with  FIG. 2  integrates the data write time of the pages contained in the respective page groups and compares the integral value Σ with the integral expected value N×600 μs. Therefore, even if the page group contains a page whose data write time is larger than the average value (600 μs in this example) per page of the integral expected value, the page group is judged to be defect-free if the data write time of the whole page group is smaller than the integral expected value.  
         [0071]      FIGS. 4A and 4B  are charts showing exemplary test results, wherein  FIG. 4A  shows the test result of the conventional testing apparatus and  FIG. 4B  shows the test result of the testing apparatus  100  explained in connection with  FIGS. 1 through 3 .  
         [0072]     In  FIGS. 4A and 4B , an axis of abscissa represents the data write time of each page and an axis of ordinate represents a number of pages corresponding to each data write time.  
         [0073]     As shown in  FIG. 4A , the conventional testing apparatus requires the write time of all of the pages to be a value obtained by dividing the expected value of write time of the whole page group by the number of pages, e.g., 600 μs or less, for example. Therefore, even if the write time required in actual use is met as the whole page group, there has been a case when the page group is judged to be defective.  
         [0074]     In contrary to that, the testing apparatus  100  compares an average value of the write time of the pages contained in the page group with a value obtained by dividing the expected value of the write time of the whole page group by a number of pages. Therefore, the testing apparatus  100  can accurately select the semiconductor memories that meet with the write time required in actual use as the whole page group.  
         [0075]      FIG. 5  is a diagram showing another exemplary configuration of the fail memory unit  30 . The fail memory unit  30  of this embodiment has an average specification register  44  and a subtracting section  46  in addition to the configuration of the fail memory unit  30  shown in  FIG. 2 . The other components have the same functions with the components denoted by the same reference numerals in  FIG. 2 .  
         [0076]     The average specification register  44  stores an average specification value set in advance. The average specification value is a value obtained by dividing an expected value set in advance for the integrated write time of the page group by a number of pages contained in the page group.  
         [0077]     The subtracting section  46  calculates a differential value by subtracting the average specification value from the write time to each page measured by the write time measuring section  32  and inputs it to the integrating section  34 . When the data write time of a certain page is 58 μs and the average specification value is 600 μs for example, the subtracting section  46  inputs −20 μs to the integrating section  34  as the differential value of the write time of that page.  
         [0078]     Still more, in this case, the integral expected value register  36  stores 0 μs as the integral expected value. That is, the judging section  38  judges whether or not each page group is defect-free based on whether or not the integral value of the differential values calculated by the integrating section  34  is smaller than zero.  
         [0079]     The fail memory unit  30  of the present embodiment can reduce the value inputted to the integrating section  34 . That is, it can reduce a bit number of the value calculated by the integrating section  34 .  
         [0080]     Therefore, it enables the circuit scale of the integrating section  34  and others to be reduced.  
         [0081]      FIG. 6  is a chart showing one exemplary operation of the fail memory unit  30  explained in connection with  FIG. 5 . The fail memory unit  30  subtracts the average specification value from the data write time of each page and integrates the differential value as described above. Therefore, it is capable of reducing the bit number of the data (differential value) inputted to the integrating section  34  and the bit number of the data (integral value) outputted out of the integrating section  34 .  
         [0082]      FIG. 7  is a diagram showing a still other exemplary configuration of the fail memory unit  30 . The fail memory unit  30  of this embodiment has an absolute specification value register  52  in addition to the configuration of the fail memory unit  30  shown in  FIG. 5 .  
         [0083]     Still more, the judging section  38  of this embodiment has a first judger  50 , a second judger  48  and a third judger  54 . The other components have almost the same functions with the components denoted by the same reference numerals in  FIG. 5 .  
         [0084]     The absolute specification value register  52  stores an absolute specification value set in advance. The absolute specification value register  52  stores the absolute specification value that is larger than the average specification value. The integral value of write time of page group is questioned in the semiconductor memory such as the data flash memory as described above, so that normally the write time per page is not necessary. However, it is a problem from the point of view of design of a device if there exits a page that requires an obviously and abnormally large write time. It is because such page may have some structural failure.  
         [0085]     Therefore, the fail memory unit  30  of this embodiment detects an abnormality of each page by using the absolute specification value to select a page that requires an abnormally large write time due to the structural failure. The second judger  48  judges whether or not each page is defect-free by judging whether or not the data write time of each page measured by the write time measuring section  32  is larger than the absolute specification value stored in the absolute specification value register  52 .  
         [0086]     Further, the first judger  50  judges per page group whether or not the integral value of the data write time to each page group is larger than the integral expected value set in advance. Then, for the respective page groups, the third judger  54  judges that the page group is a defect-free block when the integral value of the data write time is smaller than the integral expected value and the data write time of all of the pages contained in that page group is smaller than the absolute specification value. The third judger  54  also judges, for each page group, that the page group is a defective block when the integral value of the data write time is larger than the integral expected value or when the data write time of any page contained in the page group is larger than the absolute specification value.  
         [0087]      FIG. 8  is a table showing one exemplary operation of the fail memory unit  30  explained in connection with  FIG. 7 . In FIG.  8 , First Judgment indicates the judgment result of each page group in the first judger  50  and Second Judgment indicates the judgment result of each page in the second judger  48 .  
         [0088]     In this example, the MUT  200  has three page blocks, each page block has two page groups and each page group has 16 pages, respectively.  
         [0089]     Still more, this example will be explained on the assumption that the integral expected value of data write time per page group is 16×600 μs and that the absolute specification value is 1000 μs. The fail memory unit  30  of this example judges the page block to be defect-free when all of the page groups contained in the page block are defect-free.  
         [0090]     Whether or not the page group is defect-free is judged by the method explained in FIGS.  2  through  FIG. 7 .  
         [0091]     As shown in  FIG. 8 , the data write time of the second page is 1020 μs, which is larger than the absolute specification value. Therefore, Second Judgment corresponding to the second page becomes fail (logical value 1). In this case, this page group is judged to be a defective block even if the integral value of the data write time of the first page group is smaller than the integral expected value and First Judgment indicates Pass (logical value 0). Therefore, the first page block is judged to be a defective block and the fail memory  40  stores the logical value 1 as block mask data corresponding to this page block.  
         [0092]     Still more, as shown in  FIG. 8 , the integral values of the data write time of the third and fourth page groups contained in the second page block are smaller than the integral expected value, respectively. The data write time of the pages contained in each page group is also smaller than the absolute specification value, respectively.  
         [0093]     In this case, the both First and Second Judgments indicate Pass (logical value 0) and this page block is judged to be a defect-free block.  
         [0094]     Still more, the integral value of the data write time of the sixth page group is larger than the integral expected value as shown in  FIG. 8 . In this case, the third page block containing this page group is judged to be a defective block. Such control allows the MUT  200  that meets with the specification required in the actual use and that is structurally defect-free to be selected.  
         [0095]      FIG. 9  is a diagram showing a still other exemplary configuration of the fail memory unit  30 . The fail memory unit  30  of this embodiment has an AND circuit  56 , a page group control section  70  and an OR circuit  65  in addition to the configuration of the fail memory unit  30  shown in  FIG. 7 . The other components have almost the same functions with the components denoted by the same reference numerals in  FIG. 7 .  
         [0096]     When the second judger  48  judges that the data write time of either page is larger than the absolute specification value, the page group control section  70  causes the integrating section  34  to integrate while excluding the write time of that page and to increment the page number of the last page of that page group by one. It also stores data masking that page to inhibit the use of that page. Even if a page contained in the page group partially has a trouble, the other pages having no problem may be effectively utilized by such configuration.  
         [0097]     In this example, the page group control section  70  has a counter  58 , a comparator  60  and a page number register  62 . The page number register  62  stores page numbers to be contained in the page group.  
         [0098]     When one page group contains  16  pages, the page number register  62  stores  16  as the page number.  
         [0099]     The counter  58  counts the page number whose data write time has been measured by the write time measuring section  32 . For example, the driver  20  inputs the test data to the MUT  200  with a writing cycle set in advance and the write time measuring section  32  measures the data write time of each page almost in synchronism with the writing cycle.  
         [0100]     The counter  58  may count pulses of an enable signal specifying this writing cycle. The enable signal may be fed to the counter  58  via the AND circuit  56 .  
         [0101]     The comparator  60  enables the first judger  50  to carry out the judging process when the page number stored in the page number register  62  coincides with the counted value outputted out of the counter  58 .  
         [0102]     The comparator  60  also functions as a resetting section for resetting the counted value of the counter  58  and the integral value of the integrating section  34  to initial values when the page number stored in the page number register  62  coincides with the counted value outputted out of the counter  58 . The first judgment using the integral value of the write time may be carried out through such control per predetermined page number, i.e., per page group.  
         [0103]     The OR circuit  65  also sequentially receives the judgment result for each page in the second judger  48 . The OR circuit  65  outputs OR of the judgment result and the mask data outputted out of the fail memory  40 . This mask data may be data stored in advance for that page group.  
         [0104]     For example, when the page group has been judged to be a defective block by a test previously carried out, the fail memory  40  stores Fail (logical value 1) as mask data for that page group. That is, the OR circuit  65  outputs the logical value 1 when at least either one of the judgment result of the second judger  48  for that page and the mask data for that page group indicates the logical value 1.  
         [0105]     The AND circuit  56  outputs AND of a signal obtained by inverting a signal outputted out of the OR circuit  65  and the enable signal fed from the pattern generating section  10 . That is, the AND circuit  56  outputs the logical value 0 when the OR circuit  65  outputs the logical value 1. The signal outputted out of the AND circuit  56  is used as an enable signal for controlling the integrating section  34  and the counter  58 . That is, during when the OR circuit  65  outputs the logical value 1, the AND circuit  56  stops the counting process of the counter  58  and the integrating process of the integrating section  34 .  
         [0106]     When the second judger  48  judges that the data write time of either page is larger than the absolute specification value, it becomes possible to stop the counting process of the counter  58  by one pulse of the enable signal and to inhibit the integrating section  34  from integrating the write time of the page through such control. That is, it allows the page number of the last page of the page group to be incremented by one and allows the integrating section  34  to integrate while excluding the write time of that page.  
         [0107]      FIG. 10  is a table showing one exemplary operation of the fail memory unit  30  explained in connection with  FIG. 9 . In  FIG. 10 , First Judgment indicates the judgment result for each page group of the first judger  50  and Second Judgment indicates the judgment result of each page of the second judger  48 . A case when the MUT  200  has three page groups and a number of pages of each page group is  8  will be explained in this example. Still more, this example will be explained on the assumption that the integral expected value of data write time per page group is 8×600 μs and that the absolute specification value is 1000 μs.  
         [0108]     As shown in  FIG. 10 , the data write time of the tenth page is 1560 μs and is larger than the absolute specification value. In this case, the fail memory unit  30  shown in  FIG. 7  judges that the page group containing this page is defective. In contrary to that, the fail memory unit  30  shown in  FIG. 9  judges that this page is defective and masks this page. At this time, the other pages contained in the page group are not masked.  
         [0109]     Then, the fail memory unit  30  increments the page number of the last page of the page group containing this page by one (in this example, the fail memory unit  30  increments the last page of the second page group from the 16 th  page to the 17 th  page. Such process allows the pages having no problem to be utilized effectively.  
         [0110]      FIG. 11  is a diagram showing a still other configuration of the fail memory unit  30 . The fail memory unit  30  of this embodiment has a plurality of integrating sections ( 34 - 1  through  34 -N, generically referred to as  34  hereinafter) provided in parallel. The judging section  38  also has a plurality of comparators ( 64 - 1  through  64 -N, generically referred to as  64  hereinafter) provided in parallel and an OR circuit  66 .  
         [0111]      FIG. 12  is a table showing one exemplary operation of the fail memory unit  30  shown in  FIG. 11 . A case when each page group has 8 pages will be explained in this example. The fail memory unit  30  may have the same number of integrating sections  34  and the comparators  64  with the number of pages of the page group. This example may be explained on the assumption that the integral expected value of the data write time per page group is 8×600 μs.  
         [0112]     The respective integrating sections  34  integrate the data write time of the page group each having 8 pages. Here, the page group corresponding to the respective integrating sections  34  may have pages partially overlapped. For example, the page group corresponding to the respective integrating sections  34  may be what its starting page is different by one page each as shown in  FIG. 12 .  
         [0113]     The comparator  64  compares an integral value outputted out of the corresponding integrating section  34  with an integral expected value set in advance. Then, when all of the integral values outputted out of the plurality of comparators  64  is smaller than the integral expected value, the OR circuit  66  outputs a signal (logical value 0) indicating that the MUT  200  is defect-free. In  FIG. 12 , the integral value outputted out of the integrating section  34 - 4  is larger than the integral expected value, so that the OR circuit  66  outputs a signal (logical value 1) indicating that the MUT  200  is defective. Such test allows the MUT  200  that meets with the specification to be selected even when the page group is divided in any manner.  
         [0114]     Although the invention has been described by way of the exemplary embodiments, it should be understood that those skilled in the art might make many changes and substitutions without departing from the spirit and scope of the invention.  
         [0115]     It is obvious from the definition of the appended claims that the embodiments with such modifications also belong to the scope of the invention.  
         [0116]     As it is apparent from the above description, the invention allows the MUTs  200  that meet with the required specification in the actual use to be selected with a better yield.