Abstract:
A variable-gain amplifier with a differential input and differential output, including an attenuator block, receiving an input voltage and providing, on several outputs, voltages, each of which is equal to the attenuated input voltage; differential transconductor elements, each having a first input connected to a respective output of the attenuator block, and generating first and second positive currents and first and second negative currents; a current source assembly adapted to controlling the transconductance of each differential transconductor element according to an analog control signal; and an output block converting first and second input currents into a differential output voltage and providing a second input of each differential transconductor element with a feedback voltage depending on the output voltage.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a variable-gain amplifier, and in particular to such an amplifier with differential input and output, the gain of which varies exponentially as a response to an analog control voltage, and having a small harmonic distortion and reduced noise. 
   2. Description of the Related Art 
     FIG. 1  schematically shows an amplifier, which can be made in integrated circuit form, having a gain that varies exponentially as a response to an analog control voltage Vcom. The amplifier is intended for receiving a differential voltage V 1 in-V 2 in and for providing as a response a differential voltage V 1 out-V 2 out. 
   Voltage V 1 in is provided to an attenuator network AT 1  referenced to a ground potential GND and having n output nodes O 1   i  (i ranging between 1 and n). Each output node O 1   i  generates a control voltage equal to input voltage V 1 in attenuated according to a predetermined ratio, for example 2 i  when network AT 1  is an R/2R network. The amplifier includes a first assembly of transconductor elements G 1   i  controllable by a current and formed, for example, of two bipolar transistors connected as shown. Each transconductor element G 1   i  receives on a first input the voltage generated by the node O 1   i  of same rank i. Each transconductor element G 1   i  is provided for providing a positive current I 1   +  on a current output terminal  2  and a negative current I 1   −  on a current output terminal  4 . Output terminals  2  and  4  respectively form the first and second input terminals of an output block  6 . Output block  6  includes a current-to-voltage conversion element  8  having two input terminals and one output terminal. The two input terminals of converter  8  correspond to the two input terminals of block  6 . Two current sources CS 1 , CS 2  are arranged between a supply voltage VDD and respectively the first and second input terminals of block  6 . The output terminal of converter  8  is connected to potential GND via a dividing bridge formed of two resistors R 1 , R 2 , the junction point of which is connected to provide a feedback signal to a second input of each transconductor element G 1   i . The output terminal of converter  8  provides a voltage V 1 out. The amplifier further includes an assembly of controllable current sources  10  having n output terminals S 1   i . Each output terminal S 1   i  is connected to control the transconductance of the transconductor element G 1   i  of same rank i. The assembly of current sources  10  is controlled by an analog control voltage Vcom. 
   Voltage V 2 in is provided to an attenuator network AT 2  identical to network AT 1 , referenced to potential GND, and having n output nodes O 2   i . The amplifier includes a second assembly of transconductor elements G 2   i  controllable by a current, each of which receives on a first input the voltage generated by the node O 2   i  of same rank i. Each transconductor element G 2   i  is provided to provide a positive current I 2   +  on a current output terminal  12  and a negative current I 2   −  on a current output terminal  14 , respectively forming the first and second input terminals of an output block  16 . Output block  16  includes a current-to-voltage conversion element  18 , having its two input terminals connected to the two input terminals of block  16 . Two current sources CS 3 , CS 4  are respectively arranged between supply voltage VDD and the first and second input terminals of block  16 . The output of converter  18  is connected to potential GND via a dividing bridge formed of two resistors R 3 , R 4 , the junction point of which is connected to provide a feedback signal to a second input of each transconductor element G 2   i . The output terminal of converter  18  provides a voltage V 2 out. Assembly  10  of current sources includes n output terminals S 2   i , each of which is connected to a transconductor element of same rank i. 
   Attenuator networks AT 1  and AT 2  form a differential attenuator block receiving differential input signal V 1 in-V 2 in. Each pair of output nodes O 1   i , O 2   i  of the differential attenuator block provides a control voltage to the pair of transconductor elements G 1   i , G 2   i  of same rank. Each pair of transconductor elements G 1   i , G 2   i  forms a differential transconductor element. Output blocks  6  and  16  form a differential output block receiving the currents provided by each differential transconductor element G 1   i , G 2   i  and generating the differential output signal V 1 out-V 2 out. The output pairs S 1   i , S 2   i  of current source assembly  10  generate matched pairs of control currents to control each differential transconductor element G 1   i , G 2   i . The amplifier described hereabove is the object of a still unpublished French patent application and does not belong to the state of the art. 
   For such an amplifier to have a satisfactory operation, current-to-voltage conversion elements  8  and  18  must be matched. If not, the amplifier half which receives voltage V 1 in and generates voltage V 1 out and the amplifier half which receives voltage V 2 in and generates voltage V 2 out have different gains and bandwidths, which causes a distortion of the amplifier output signal. In practice, it is difficult to form two matched current-to-voltage converters  8  and  18 . 
   Further, current source pairs CS 1 , CS 2 , and CS 3 , CS 4  operate in a decorrelated manner, which can contribute to increasing the noise level of the amplifier. 
   Further, each of voltage signals V 1 out and V 2 out is generated by a non-symmetrical amplifier which does not suppress the distortion due to the harmonic of second order. 
   BRIEF SUMMARY OF THE INVENTION 
   The disclosed embodiments of the present invention provide a variable-gain amplifier with a differential input and output, the gain of which varies exponentially as a response to an analog control voltage, and which exhibits a small harmonic distortion and low noise. 
   To achieve the foregoing, an embodiment of the present invention especially provides a variable-gain amplifier with differential input and output, including an attenuator block referenced to the common mode voltage of the amplifier output, receiving an input voltage and adapted to providing, on several outputs, voltages, each of which is equal to the input voltage attenuated according to a predetermined ratio; differential transconductor elements controllable by a current, each differential transconductor element having a first input connected to an output of the attenuator block, each differential transconductor element generating first and second positive currents and first and second negative currents; a current source assembly adapted to controlling the transconductance of each differential transconductor element according to an analog control signal; and an output block converting first and second input currents into a differential output voltage and providing a second input of each differential transconductor element with a feedback voltage depending on the output voltage, the first input current being equal to the sum of the first positive currents and of the second negative currents and the second input current being equal to the sum of the second positive currents and of the first negative currents. 
   According to an embodiment of the present invention, the attenuator block includes two attenuator networks of R/2R type respectively receiving first and second input voltages, each output of the attenuator block including an output node of each attenuator network, the output node generating an attenuated voltage equal to the input voltage received by said network, attenuated according to the predetermined ratio specific to said output; each differential transconductor element includes two pairs of bipolar transistors, the emitters of the transistors of a first pair being connected to a first current control terminal of the differential transconductor element, and the emitters of the transistors of the second pair being connected to a second current control terminal of the differential transconductor element, the first input of the differential transconductor element being formed by the bases of the first two transistors of the two transistor pairs, the second input of the differential transconductor element being formed by the bases of the two second transistors of the two transistor pairs, the two bases forming the first input of the differential transconductor element being respectively connected to the output nodes of the output of the attenuator block connected to the differential transconductor element, the two bases forming the second input of the differential transconductor element being submitted to the feedback voltage, the collectors of the first transistors generating the first and second positive currents, and the collectors of the second transistors generating the first and second negative currents; and the current source assembly includes pairs of control terminals connected to the first and second current control terminals of each differential transconductor element. 
   According to an embodiment of the present invention, the output block includes: a current-to-voltage conversion element having first and second input terminals respectively provided for receiving the first and second input currents, generating the common mode voltage on a common mode output terminal, and respectively generating first and second output voltages on first and second output terminals, first and second resistive dividing bridges respectively arranged between the first and second output terminals of the current-to-voltage conversion element and the common mode voltage, the midpoint of the first and second resistive dividing bridges generating the feedback voltage; and first and second current sources respectively arranged between a supply voltage and the first and second input terminals of the output block. 
   According to an embodiment of the present invention, the current-to-voltage conversion element includes: first and second identical P-type MOS transistors, having their sources connected to the supply voltage, having their gates connected to each other, having their respective drains connected to the first and second input terminals of the current-to-voltage conversion element; third and fourth identical P-type MOS transistors, having their sources connected to the supply voltage, having their respective gates connected to the respective drains of the first and second MOS transistors, having their respective drains connected to the first and second output terminals of the current-to-voltage conversion element; third and fourth current sources arranged between the respective drains of the third and fourth transistors and a first reference voltage; two identical resistors each connected between the respective drains of the third and fourth transistors and the common mode output terminal; and a differential amplifier having a first input connected to the common mode output terminal, having a second input connected to a second reference voltage, and having its output connected to the gates of the first and second transistors. 

   
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
     The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments, in conjunction with the accompanying drawings, wherein: 
       FIG. 1 , previously described, schematically shows a conventional variable-gain amplifier; 
       FIG. 2  schematically shows a variable-gain amplifier according to the present invention; 
       FIG. 3  schematically shows an embodiment of the current-to-voltage conversion element of  FIG. 2 ; and 
       FIG. 4  schematically shows an embodiment of the controllable current source assembly of FIG.  2 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Only those elements necessary to the understanding of the present invention have been shown in the following drawings. Same reference numbers represent the same elements in the previous drawing and in the following drawings. 
     FIG. 2  schematically shows an embodiment of a variable-gain amplifier according to the present invention, intended for receiving a differential voltage V 1 in-V 2 in and for providing as a response a differential voltage V 1 out-V 2 out. The amplifier includes a first attenuator network AT 1  of R/2R type receiving voltage V 1 in on an input terminal and having n output nodes O 1   i . According to the present invention, attenuator network AT 1  is referenced to common mode voltage VCM of the amplifier output. The amplifier includes a first assembly of transconductor elements G 1   i  controllable by a current, each of which receives on a first input the voltage generated by the node O 1   i  of same rank i. Each transconductor element G 1   i  includes a pair of bipolar transistors, the emitters of which are connected to a current control terminal of element G 1   i . The base of a first transistor forms a first input of element G 1   i . The base of the second transistor forms a second input of element G 1   i . The collector of the first transistor provides a positive current I 1   +  to a current output terminal  2 . The collector of the second transistor provides a negative current I 1   −  to a current output terminal  4 . The amplifier includes a second attenuator network AT 2  identical to network AT 1 , receiving voltage V 2 in on an input terminal, having n output nodes O 2   i , and referenced to voltage VCM. The amplifier includes a second assembly of transconductor elements G 2   i  controllable by a current, each of which receives on a first input the voltage generated by the node O 2   i  of same rank i. Each transconductor element G 2   i  includes a pair of bipolar transistors having their emitters connected to a current control terminal of element G 2   i . The base of a first transistor forms a first input of element G 2   i . The base of the second transistor forms a second input of element G 2   i . The collector of the first transistor provides a positive current I 2   +  to a current output terminal  12 . The collector of the second transistor provides a negative current I 2   −  to a current output terminal  14 . 
   The transconductor elements G 1   i  and G 2   i  of same rank form a differential transconductor element G 1   i , G 2   i . The transconductance of each differential transconductor element G 1   i , G 2   i  is controlled by the output pairs S 1   i , S 2   i  of a controllable current assembly  10  connected to the current control terminals of the differential transconductor element. An example of forming of current source assembly  10  is described hereafter. 
   According to this embodiment of the present invention, the amplifier includes a single output block  26  having first and second input terminals IN 1 , IN 2  and including a current-to-voltage conversion element  28 . Current-to-voltage conversion element  28  has first and second input terminals IN 1 ′ and IN 2 ′ respectively connected to terminals IN 1  and IN 2 . Current-to-voltage conversion element  28  further includes first and second output terminals OUT 1 , OUT 2  and a common mode output terminal generating voltage VCM. Terminal IN 1  is connected to current output terminals  2  and  14 . Terminal IN 1  receives a first input current equal to the sum of the positive currents I 1   +  generated by transconductor elements G 1   i  and of the negative currents I 2   −  generated by transconductor elements G 2   i . Terminal IN 2  is connected to current output terminals  4  and  12 . Terminal IN 2  receives a second input current equal to the sum of the negative currents I 1   −  generated by transconductor elements G 1   i  and of the positive currents I 2   +  generated by transconductor elements G 2   i . A current source CS 5  is arranged between terminal IN 1  and a supply voltage VDD. A current source CS 6  is arranged between terminal IN 2  and supply voltage VDD. The first output terminal OUT 1  of element  28  is connected to voltage VCM via a first dividing bridge formed of two resistors R 1 , R 2 . The midpoint of the first dividing bridge is connected to provide a feedback signal to the second input terminal of each transconductor element G 1   i . The second output terminal OUT 2  of element  28  is connected to voltage VCM via a second dividing bridge formed of two resistors R 3 , R 4 . The midpoint of the second dividing bridge is connected to provide a feedback signal to the second input terminal of each transconductor element G 2   i . Output terminal OUT 1  provides output voltage V 1  out and output terminal OUT 2  provides output voltage V 2 out. 
   The amplifier generates differential voltage signal V 1 out-V 2 out from differential voltage signal V 1 in-V 2 in by means of a single current-to-voltage conversion element  28 , which enables suppressing distortion problems due to the difficulties of matching the two current-to-voltage conversion elements of a conventional amplifier. 
   The first and second input terminals IN 1  and IN 2  of current-to-voltage conversion element  28  are each connected to a single current source, respectively CS 5  and CS 6 . The two current sources CS 5  and CS 6  replace the two current source pairs CS 1 , CS 2  and CS 3 , CS 4  operating in a decorrelated way of a conventional amplifier, which enables reducing the noise coming from power supply VDD. 
   The amplifier according to this embodiment of the present invention is a symmetrical assembly that eliminates the second harmonic term from output signal V 1 out-V 2 out. 
   The input of the amplifier is a differential signal referenced to common mode voltage VCM. As a result, for a given dynamic range, a lower supply voltage than in the case of two input terminals referenced to ground can be used. 
     FIG. 3  schematically shows an embodiment of a current-to-voltage conversion element  28 . Two identical P-type MOS transistors T 1  and T 2  have their sources connected to voltage VDD and their gates connected to each other. The respective drains of transistors T 1  and T 2  are connected to terminals IN 1 ′ and IN 2 ′. Two identical P-type MOS transistors T 3  and T 4  have their sources connected to voltage VDD and their respective gates connected to terminals IN 1 ′ and IN 2 ′. The respective drains of transistors T 3  and T 4  are connected to terminals OUT 1  and OUT 2 . Current sources CS 7  and CS 8  are respectively arranged between the respective drains of transistors T 3  and T 4  and a ground voltage GND. The drain of each of transistors T 3  and T 4  is connected to the common mode output terminal by a resistor R. A differential amplifier  30  has a first input connected to the common mode output voltage and a second input connected to a reference voltage Vref. The output of amplifier  30  is connected to the gates of transistors T 1  and T 2 . 
     FIG. 4  schematically shows an embodiment of controllable current source assembly  10 . Current source assembly  10  includes n pairs of output terminals S 1   i , S 2   i  and two control terminals A and B. Control voltage Vcom is provided across terminals A and B. Each output terminal S 1   i , S 2   i  is respectively connected to the drain of N-channel MOS transistors T 1   i , T 2   i . Transistors T 1   i  and T 2   i  are matched. The source of transistors T 1   i , T 2   i  is connected to ground (GND). Transistor pair T 1   i , T 2   i  is associated with an N-channel MOS transistor T 3   i  and with a P-channel MOS transistor T 4   i . The source of transistor T 3   i  is grounded. The gate and drain of transistor T 3   i  are interconnected. The gate of transistors T 1   i , T 2   i  is connected to the gate of transistor T 3   i  so that two matched currents depending on the current in transistor T 3   i  run through transistors T 1   i  and T 2   i . The drain of transistor T 3   i  is connected to the drain of transistor T 4   i , so that these transistors are in series. The source of transistor T 4   i  is connected to supply voltage VDD via a single constant current source CS 9 . The gate of transistor T 4   i  is connected to a node Ni of a control means  32  formed of resistors R′ and of current sources CS′. In control means  32 , the first node N 1  is coupled to terminal A, the last node Nn is coupled to terminal B, each node Nj (j ranging between 1 and n−1) is connected to node Nj+1 via a resistor R′ and each node Nj (j ranging from 2 to n−1) is connected to a first terminal of a constant current source CS′ specific to this node. Control means  32  is provided to successively progressively turn on, then progressively turn off, each transistor T 4   i  when voltage Vcom undergoes a predetermined variation, so that the sum of the currents flowing through transistors T 4   i  is substantially constant. Each output terminal S 1   i , S 2   i  provides a current depending on the current flowing through transistor T 4   i.    
   The disclosed embodiments of the present invention may have various alterations, modifications, and improvements that will readily occur to those skilled in the art. The present invention has been described in relation with a particular controllable current source assembly  10 , but those skilled in the art may adapt the present invention to a current source assembly having an equivalent function. For example, such an assembly may be obtained by doubling the current source assembly used to control the variable-gain amplifier with a non-differential input and output described in U.S. Pat. No. 5,077,541. 
   The present invention has been described in relation with a differential attenuator block using R/2R dividing networks, but those skilled in the art may adapt the same to other attenuator blocks having different attenuation ratios. 
   The present invention has also been described in relation with a specific current-to-voltage conversion element  28 , but those skilled in the art may adapt the present invention to any equivalent current-to-voltage conversion element. 
   In the foregoing description, first input IN 1  of block  26  receives the sum of the positive currents I 1   +  generated by transconductor elements G 1   i  and of the negative currents I 2   −  generated by transconductor elements G 2   i . Similarly, the second input IN 2  of block  26  receives the sum of the negative currents I 1   −  generated by transconductor elements G 1   i  and of the positive currents I 2   −  generated by transconductor elements G 2   i . However, those skilled in the art may adapt the present invention to the case where the first input IN 1  of block  26  receives the sum of the negative currents I 1   −  generated by the transconductor elements G 1   i  and of the positive currents I 2   +  generated by the transconductor elements G 2   i , and where the second input IN 2  of block  26  receives the sum of the positive currents I 1   +  generated by the transconductor elements G 1   i  and of the negative currents I 2   −  generated by the transconductor elements G 2   i.    
   Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereof.