Abstract:
An electronic timepiece comprising a connecting system for connecting a plurality of electronic cells in parallel without undesirable mutual influences such as mutual charging and discharging.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to an electronic timepiece and more particularly to an electronic timepiece driven by the electric power from a plurality of electric cells. 
     2. Technical Considerations and Prior Art 
     Many attempts have been made to provide an electronic timepiece having a plurality of electric batteries or cells for the purpose of obtaining increased electric power. However, there are problems in mutual charging or discharging and in increased power consumption when using features in addition to the usual fundamental timepiece function, when two or more cells are connected in parallel. 
     On the other hand, the parallel connection of cells can be advantageous in the facts that the handling of signals can be done at a lower voltage due to the increase in the current level without a change in the voltage and therefore the timepiece can include many additional functions and features. 
     SUMMARY OF THE INVENTION 
     A primary object of this invention is to provide an electronic timepiece which has improved reliability and a long continuous working period by solving the above-described problems associated with the parallel connection of electric batteries or cells. 
     In the electronic timepiece according to this invention, the terminal voltages of each cell are detected. Furthermore, the levels of power consumption in each of the components or sections of the timepiece are determined and the resulting levels are used to set the paths of the electric current from the cells to the components. 
     The principle of this invention may be applied to timepiece having a single cell as well as one of the countermeasure in that the continuous time display function is changed to the intermittent function in order to decrease the power consumption when the current flow to the time display mechanism increases to a higher level than of normal conditions. 
     The timepiece of this invention may be constituted so that the main component of the timepiece is formed separately from optional means or optional attachments, such as alarm devices with one or more electric cells. Such construction can meet with the various requirement by the user. 
     Discussing now the capacity of cells, the improved cells such as a mercury or silver cells which have a terminal voltage of about 1.5 volts and a capacity of 200 mA per hour can drive continuously the main component of an electronic timepiece for one to three years with the average current flow of 5 to 15 μA. On the other hand, a typical buzzer for alarm requires the working current to flow at about 1 to 5 mA at 1.5V, so that the electronic timepiece having a buzzer can be driven only 20 to 200 hours. 
     One of the most rational approaches is to provide two groups of cells, one being used for the main component and the other for an optional or additional component such as an alarm and being used to connect the cells of the groups to each other in a suitable manner, thereby improving reliability by using the power from the cells at a desirable distribution ratio between the main and optional components. 
     Examples of the optional components which can be used in the timepiece according to this invention include alarm devices, high accuracy time pace signal generators, automatic time correcting devices, calculating means, paging devices, data bank devices and a schedule timer devices. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram showing the paths of electric current between electric cells, a main component and optional component of the electronic timepiece according to this invention; 
     FIG. 2 is a circuit diagram of the timepiece embodying this invention; 
     FIG. 3 is a circuit diagram of a second embodiment of a timepiece according to this invention; and 
     FIG. 4 is a circuit diagram of a third embodiment of a timepiece according to this invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to the drawing, FIG. 1 shows schematically the possible paths electric current between time keeping means TK, an optional componet OPT and a pair of electric cells B 1  and B 2 . The term &#34;time keeping means&#34; is intended to mean a main component or section of the timepiece which may comprise a time pace signal generator, a time unit signal generator and a time display mechanism. Assuming that the time keeping means TK consumes a relatively small power at the constant rate and that the optional means consumes a relatively large amount of power on demand, the relation between the connections C 1 , C 2 . . . C 6  is that it is advantageous to use the optional meams OPT and the cell B 2  together with the time keeping means TK and the cell B 1  in the operation of the timepiece under such condition that the operation of the time keeping device according to preference is given in the following Table 1. 
     
                                           Table 1__________________________________________________________________________Functions of State   Values of Functions                              Notes__________________________________________________________________________J.sub.1 = 1 : V.sub.2 - V.sub.1 &gt; ΔV             J.sub.1                0 0 0 0 1 1 B.sub.1 consumedJ.sub.2 = 1 : V.sub.1 - V.sub.2 &gt; ΔV             J.sub.2                0 0 1 1 0 0 B.sub.2 consumedJ.sub.3 = 1 : OPT demanded in operation             J.sub.3                0 1 0 1 0 1J.sub.4 =  1 : TK demanded in operation             J.sub.4                1 1 1 1 1 1Functions of Connections         RoutesC.sub.1 = 1 : B.sub.1 ##STR1##         C.sub.1                1 1 1 1 0 0 regular routeC.sub.2 = 1 : B.sub.2 ##STR2##         C.sub.2                (1)                  (1)                    0 0 1 1 auxiliary routeC.sub.3 = 1 : B.sub.1 ##STR3##         C.sub.3                0 0 0 0 0 0 auxiliary routeC.sub.4 = 1 : B.sub.2 ##STR4##         C.sub.4                0 1 0 (0)                        0 (1)                            regular routeC.sub.5 = 1 : B.sub.2 ##STR5##         C.sub.5                0 0 0 0 0 0 charging-discharging  routeC.sub.6 = 1 : B.sub.1 ##STR6##         C.sub.6                0 0 0 0 0 0 charging-discharging  route  States             a b c d e f__________________________________________________________________________ 
    
     In Table 1, 
     State a represents a state in which a power to TK is supplied from only B 1  or can be supplied from both B 1  and B 2 . 
     State b represents a state in which power to OPT is supplied from only B 2 . 
     State c represents a state in which B 1  is consumed and a power to TK is supplied from B 1 . 
     State d represents a state in which B 2  is consumed and TK is kept in operation being supplied power from B 1  and the operation of OPT is stopped. 
     State e represents a state in which B 1  is consumed and a power to TK is supplied from especially B 2 . 
     State f represents a state in which B 1  is consumed and a power to TK is supplied and a power to OPT is supplied possibly from B 2 . 
     In Table 1 the indication &#34;1&#34; and &#34;0&#34;, respectively, shows a value for the function of state or connection and the indication &#34;(1)&#34; and &#34;(0)&#34;  is a value showing the case in which the value 1 and 0 can be chosen, but in which the indicated value is preferable. 
     Table 2 below shows examples of the preferable connection by using logical equations. 
     
                       Table 2______________________________________Case 1         Case 2       Case 3______________________________________C.sub.1 = J.sub.1          C.sub.1 = J.sub.1                       C.sub.1 = J.sub.1C.sub.2 = J.sub.2          C.sub.2 = J.sub.2                       C.sub.2 = J.sub.1C.sub.3 = 0    C.sub.3 = 0  C.sub.3 = 0C.sub.4 = J.sub.2.sup..J.sub.3          C.sub.4 = J.sub.3                       C.sub.4 = J.sub.3C.sub.5 = 0    C.sub.5 = 0  C.sub.5 = 0C.sub.6 = 0    C.sub.6 = 0  C.sub.6 = 0______________________________________ 
    
     In the circuit shown in FIG. 2 each of the electric cells B 1  and B 2  is a sivler oxide cell having a terminal voltage of 1.5 volts, the positive terminal thereof being mutually connected through a diode D 1  which has a small forward voltage drop characteristic, such as with a germanium or copper oxide diode. Also, the time keeping means TK is formed as a CMOS integrated circuit which can operate at a minimum voltage of 1.35 volts and has a power consumption rate of 3μA at 1.5 volts as well as the optional means OPT can operate at a minimum voltage of 1.35 volts and has a normal power consumption rate of 3μA and a working power consumption rate of 2mA. 
     When the capacity of the cell B 2  has been decreased in comparison with that of the cell B 1 , the relation between the terminal voltages V 1  and V 2  of the cells B 1  and B 2  may be designated as follows: 
     
         V.sub.1 - V.sub.2 = ΔV ≧ 0 
    
     in this case the diode D 1  is biased in the reverse direction and interrupts the electric current flowing from the cell B 1  to the cell B 2  and also the current from the cell B 1  to the optional means OPT, so that the cell B 1  can be prevented from the superfluous power consumption which may be required by the optional means OPT. On the contrary, when the cell B 1  is more consumed than the cell B 2  the electric current from the cell B 2  flows through the diode D 1  which is now forward biased to the cell B 1  thereby preventing the optional means OPT from operating defectively. The useful effects set forth above are secured except in rare cases such as when there is short-circuiting of the inside cell. 
     The diode D 1  used in the embodiment shown in FIG. 2 may be replaced with a resistor having a resistance of, for example, 1 to 10 KΩ. In this case a good switching operation by means of the resistor is performed owing to the large ratio of the current flow between the time keeping means and the optional means OPT as well as in the resistance values between the cells and the resistance. Furthermore, the continuous working period of the time keeping means TK would be extended in comparison with the case using the cell B 1  only due to the fact that the time keeping means TK is operated by power from both cells B 1  and B 2  unless the optional means OPT is in operation. 
     FIG. 3 shows another embodiment of this invention in which a P channel field-effect transistor P of the enhancement type is used as a switching element in lieu of the diode D 1  of FIG. 2, the same or similar parts used in the embodiment shown in FIG. 2 being denoted by the same reference numerals and the detailed description thereof being omitted. 
     Under the normal condition a 0 level signal is supplied to the gate G of the transmitter P to turn it on. Accordingly, the electric cells B 1  and B 2  are mutually connected through the transistor P which has an ON-resistance Ron where the value of Ron is 300Ω and the internal resistance of both cells B 1  and B 2  is 100Ω, ratio. The between the current from the cell B 1  to the time keeping means TK and the current from the cell B 2  to the time keeping means TK is rated at about 4:1, thereby obtaining a 25% longer continuous working period of the time keeping means TK in the case that the cell B 1  is used alone. In the event of the terminal voltage V 1  of the cell B 1  becoming lower than that of the cell B 2  or the internal resistance of the cell B 1  becoming larger than that of the cell B 2 , the more stable and accurate operation of the time keeping means TK is expected. When the optional means OPT starts its own operation, an &#34;1&#34; level signal is supplied to the gate of the transistor P to cut off the route between the cells B 1  and B 2 . Accordingly, no electric current flow occurs from the cell B 1  to the cell B 2  or from the cell B 1  to the optional means OPT. 
     The embodiment shown in FIG. 3 gives rise to a practical advantage in that a timepiece having a plurality of cells connected in parallel can be formed with a simpler construction because short-circuiting of a cell cannot occur. 
     In FIG. 4 there is shown a further embodiment of this invention including means for connecting the cells B 1  and B 2 , other than that described as above, which can perform such operation that the time keeping means TK receives the power either from the cells B 1  and B 2  when the terminal voltage V 1  and V 2  are substantially equal or from one of the cells B 1  or B 2  when the difference ΔV between the voltage V 1  and V 2  is larger than a predetermined value. Furthermore the optional means OPT receives a power only from the cell B 2  until the cell B 2  is fully used. The selected mode of the connection in the system shown in FIG. 1 is given below: 
     
         C.sub.1 = J.sub.1 
    
     
         c.sub.2 = j.sub.1.j.sub.2 
    
     
         c.sub.4 = 1 
    
     
         c.sub.3 = c.sub.5 = c.sub.6 = 0 
    
     in the system shown in FIG. 4 differencial amplifiers A 1  and A 2  generate logical output signals J 1  and J 2  having the level 1, respectively, when the voltages at the input terminals denoted by (+) and (-) have the following relation: 
     
         V.sub.(.sub.+) - V.sub.(.sub.-) &gt; ΔV 
    
     where: ΔV has a predetermnined value larger than zero. 
     The outputs J 1  and J 2  will take a level &#34;0&#34; in case other than the above. 
     The differential amplifiers A 1  and A 2  may be operated continuously or intermittently. In the latter case the amplifiers are controlled by the signal prepared by using the signal from the time keeping means TK and the outputs J 1  and J 2  are stored in a suitable memory and taken therefrom on demand. The combinations of the outputs J 1 , J 2  and J 3  are as follows: 
     
         J.sub.1 + J.sub.2 = 0 . . . V.sub.1 ≈ V.sub.2 
    
     
         j.sub.1 . j.sub.2 =  1 . . . v.sub.1 &gt; v.sub.2 
    
     
         j.sub.1 . j.sub.2 = 1 . . . v.sub.1 &lt; v.sub.2 
    
     the optional means OPT has a function to generate an output signal J 3  of level 0 when OPT is in the operating state and level 1 at other times. The signals J 1 , J 2  and J 3  are used to control a pair of P-channel switching transistors P 1  and P 2  in accordance with the level thereof, the relation between the level of the signals and the state of the transistors being given below: 
     
         P.sub.1 = J.sub.1 
    
     
         p.sub.2 = j.sub.2.j.sub.3 
    
     the signals J 1  and J 2  may be utilized for the display of the capacity of the cells B 1  and B 2 , respectively. 
     For the purpose of preventing the time keeping means TK from malfunction, it is recommended that a capacitor is connected between the point X and the negative terminal of the cell B 1 . It is preferred to form a positive feedback loop from the output terminal to the input terminal of each of the differencial amplifiers A 1  and A 2  in order to obtain output signals having a hysteresis characteristic. 
     The preferred form the timepiece according to this invention has a space provided for enclosing a plurality of cells and a connecting system as described above in the interior of the casing. Alternatively, the timepiece may have a set of external connecting terminals to which the respective terminals of one or more additional electric cells and/or a connecting system is connectable. Such arrangement makes it possible to subjoin an additional cell or cells without opening the sealed casing of the timepiece. 
     Furthermore, the timepiece of this invention may be provided with means for connecting an optional component including a cell or cells therefor. In this case the timepiece can be formed comprising a main component and a cell or cells therefor, which is capable of being prepared as of a standard type to which one or more optional components with a cell therefor are connected on demand. 
     Preferably, the connecting system according to this invention is constituted in the form of a CMOS integrated circuit with or without the main component of the timepiece, the details being apparent to those skilled in the art.