Abstract:
There is provided a test device for a liquid crystal display device in which a liquid crystal display unit has liquid crystal display elements arranged in matrix, and thin film transistors have their respective drains connected to the liquid crystal display elements, their respective gates commonly connected to row lines, and their respective sources commonly connected to column lines, the transistors arranged in the same row sharing the line of that row, the transistors arranged in the same column sharing the line of that column, the rows of the lines being controlled by a row driver, and the columns of the lines being supplied with multi-level voltage depending upon gradation of a display image by a column driver; the test device comprising a comparator circuit provided in each of either the rows or columns of the lines for detecting which of the rows or columns of the lines is selected, an encoder circuit receiving the detection result from the comparator circuit and scanning bi-directionally from head to tail or vice versa of the rows or columns of the lines to obtain the number of the selected row or column line, a plurality of bus lines constituting a bus being varied in voltage level depending upon the obtained number of the selected row or column line and encoding the voltage level in relation with the number, and a read-out circuit reading the voltage level of the bus lines from the encoder circuit to determine if the encoded number is identical with the number of the selected row or column line, wherein the comparator circuit, the encoder circuit, and the read-out circuit being built in the same substrate as the liquid crystal display elements.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of Invention 
         [0002]    The present invention relates to a liquid crystal display device test circuit, a liquid crystal device incorporated with the same, and a test method for the liquid crystal device. 
         [0003]    2. Related Art 
         [0004]    Among a variety of liquid crystal display devices, especially a thin film transistor (TFT) liquid crystal display device is comprised of liquid crystal display elements arranged in matrix on a glass substrate, thin film transistors (TFTs) having their respective drains connected to the liquid crystal display elements, row lines each of which is commonly connected to gates of the TFTs in a row and is controlled by a row driver, and column lines each of which is commonly connected to sources of the TFTs in a column and is controlled by a column driver to receive multi-level voltage depending upon gradation of an image to be displayed, and typically, the TFTs, the row lines, the column lines, and other components are built up through the amorphous silicon process technology. 
         [0005]    In general, after these primary components of the liquid crystal display elements are formed, a process of attachment of color filter glass is followed by injecting liquid crystal to complete the device, and thereafter, the finished device undergoes a lighting-up test. During the lighting-up test, a row decoder activates a target row line to turn on the TFTs, gates of which are connected to the target row line. And voltages depending upon the brightness of an image to be displayed are applied by the column driver to the data (column) lines to which sources of the TFTs are connected. The voltages are supplied through the TFT to a pixel electrode connected to the drain of the TFT, and thus, the liquid crystal is varied in transmissivity to give the desired display. Pass or fail on the lighting-up test is judged by visual inspections. 
         [0006]    In this way, since the lighting-up test is carried out on the device completely finished, it is a sheer waste of the device manufacturing process when some defects are observed after all. 
         [0007]    On the other hand, the recent development of the low temperature poly silicon (LTPS) process technology has boosted up numbers of circuits implemented on an array glass, and the boosting popularity of much larger liquid crystal display devices in the market, as well, will probably cause an increase in a rejection rate of the products far beyond the current figure. 
         [0008]    Considering these situations, an improvement is disclosed where, for the device before completion, in order to perform a test of an image display, signals from all the points to be inspected are taken out to peripheral parts of an array substrate provided with a numerous analog switches, and an external test signal is applied to the device so as to detect off leak malfunction (see Patent Document 1 listed below). 
         [0009]    Patent Document 1: Japanese Patent Preliminary Publication No. 2001-330639. 
         [0010]    Such a prior art, however, utilizes two Off level voltages and a way of increasing leak current to detect off leak malfunction, and a minute current variation due to the off leak malfunction cannot be assuredly detected by this embodiment. In addition, a numerous terminals and analog switches must be provided in the peripheral parts of the liquid crystal display device for the purpose of detecting the malfunction betray the desires of downsizing and reduction of the space. 
       SUMMARY OF THE INVENTION 
       [0011]    Accordingly, it is an object of the present invention to provide a test circuit of a simplified structure capable of detecting malfunction of a liquid crystal display device, and also provide a liquid crystal display device incorporated with such a test circuit. 
         [0012]    According to one aspect of the present invention, there is provided 
         [0013]    a test device for a liquid crystal display device in which a liquid crystal display unit has liquid crystal display elements arranged in matrix, and thin film transistors have their respective drains connected to the liquid crystal display elements, their respective gates commonly connected to row lines, and their respective sources commonly connected to column lines, the transistors arranged in the same row sharing the line of that row, the transistors arranged in the same column sharing the line of that column, the rows of the lines being controlled by a row driver, and the columns of the lines being supplied with multi-level voltage depending upon gradation of a display image by a column driver; the test device comprising: 
         [0014]    a comparator circuit provided in each of either the rows or columns of the lines for detecting which of the rows or columns of the lines is selected, 
         [0015]    an encoder circuit receiving the detection result from the comparator circuit and scanning bi-directionally from head to tail or vice versa of the rows or columns of the lines to obtain the number of the selected row or column line, a plurality of bus lines constituting a bus being varied in voltage level depending upon the obtained number of the selected row or column line and encoding the voltage level in relation with the number, and 
         [0016]    a read-out circuit reading the voltage level of the bus lines from the encoder circuit to determine if the encoded number is identical with the number of the selected row or column line, 
         [0017]    said comparator circuit, said encoder circuit, and said read-out circuit being built in the same substrate as the liquid crystal display elements. 
         [0018]    According second aspect of the invention, there is provided a liquid crystal display device, comprising 
         [0019]    a liquid crystal display unit including liquid crystal display elements arranged in matrix, thin film transistors having their respective drains connected to the liquid crystal display elements, row lines commonly connected to gates the thin film transistors, and column lines commonly connected to sources of the thin film transistors, the transistors arranged in the same row sharing the line of that row, the transistors arranged in the same column sharing the line of that column, the rows of the lines being controlled by a row driver, and the columns of the lines being supplied with multi-level voltage depending upon gradation of a display image by a column driver; 
         [0020]    a comparator circuit provided in each of either the rows or columns of the lines for detecting which of the rows or columns of the lines is selected; 
         [0021]    an encoder circuit receiving the detection result from the comparator circuit and scanning bi-directionally from head to tail or vice versa of the rows or columns of the lines to obtain the number of the selected row or column line, a plurality of bus lines constituting a bus being varied in voltage level depending upon the obtained number of the selected row or column line and encoding the voltage level in relation with the number; and 
         [0022]    a read-out circuit reading the voltage level of the bus lines from the encoder circuit to determine if the encoded number is identical with the number of the selected row or column line; 
         [0023]    said liquid crystal display unit, said comparator circuit, said encoder circuit, and the read-out circuit being built in the same substrate as the liquid crystal display elements. 
         [0024]    According to a third aspect of the invention, there is provided a method for testing a liquid crystal display device in which liquid crystal display elements are arranged in matrix, and thin film transistors have their respective drains connected to the liquid crystal display elements, their respective gates commonly connected to row lines, and their respective sources commonly connected to column lines, the transistors arranged in the same row sharing the line of that row, the transistors arranged in the same column sharing the line of that column, the rows of the lines being controlled by a row driver, and the columns of the lines being supplied with multi-level voltage depending upon gradation of a display image by a column driver; the method comprising the steps of 
         [0025]    detecting which of the rows or columns of the lines is selected, 
         [0026]    with reference to the detection result in the step of detecting, scanning bi-directionally from head to tail or vice versa of the rows or columns of the lines to specify the number of the selected row or column line, 
         [0027]    varying a plurality of bus lines in voltage level depending upon the specified number of the selected row or column line and encoding the voltage level in relation with the number, and 
         [0028]    reading the encoded voltage level of the bus lines to determine if the encoded number is identical with the number of the selected row or column line. 
         [0029]    In accordance with the present invention, a test circuit of a simplified structure for testing a liquid crystal display device is provided in the same substrate as liquid crystal display elements, and hence, such a test circuit ensures to check states of wirings and operations of TFTs without visual inspections before filling of the liquid crystal. 
         [0030]    Moreover, in a liquid crystal display device according to the present invention, liquid crystal display elements and a test circuit of a simplified structure are provided in the same substrate, and this ensures to check states of wirings and operations of TFTs without visual inspections before these components are embedded in liquid crystal, which eventually brings about a reduction of the manufacturing cost and effectively avoids an increase in the required area for the test circuit. 
         [0031]    Furthermore, since a test method for a liquid crystal display device according to the present invention includes the steps of detecting selected row or column line, scanning bi-directionally from top to bottom or vise versa of the rows or column lines to obtain the line number of the selected one of the rows or column lines, encoding a voltage level at a batch of bus lines that constitute a bus so as to be related to the detected number of the selected row or column line, and detecting if the encoded number on the batch of bus lines is identical with the number of the selected row or column line obtained as a result of the bi-directional scanning, so as to produce a signal indicating the number, and therefore, operations of TFTs and states of wirings can be checked without using an external test device even before the components are embedded in the liquid crystal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0032]    The invention will become more fully understood from the detailed description given herein below illustration only, and thus is not limitative of the present invention, and wherein: 
           [0033]      FIG. 1  is a schematic block diagram showing the entire structure of a test circuit incorporated liquid crystal display device according to the present invention; 
           [0034]      FIG. 2  is a circuit diagram illustrating an exemplary configuration of a comparator and an operation of the same upon receiving a High level signal; 
           [0035]      FIG. 3  is a timing chart illustrating the operation in  FIG. 2 ; 
           [0036]      FIG. 4  is a circuit diagram showing an operation of the comparator configured as in  FIG. 2  upon receiving a Low level signal; 
           [0037]      FIG. 5  is a timing chart illustrating the operation in  FIG. 4 ; 
           [0038]      FIG. 6  is a circuit diagram showing an operation of the comparator configured as in  FIG. 2  upon receiving an invalid intermediate level signal; 
           [0039]      FIG. 7  is a timing chart illustrating the operation in  FIG. 6 ; 
           [0040]      FIG. 8  is a circuit diagram showing an exemplary configuration of an encoder; 
           [0041]      FIG. 9  is a circuit diagram showing an exemplary configuration of a top dummy encoder; 
           [0042]      FIG. 10  is a circuit diagram showing an exemplary configuration of a bottom dummy encoder; 
           [0043]      FIG. 11  is a circuit diagram showing an exemplary configuration of a read-out interface; and 
           [0044]      FIG. 12  is a flow chart schematically illustrating a test procedure on the liquid crystal display device, using the test circuit according to the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0045]    The present invention will be apparent from the following detailed description, which proceeds with reference to the accompanying drawings, wherein the same references relate to the same elements. 
         [0046]    Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. 
         [0047]      FIG. 1  is a schematic block diagram showing a configuration of a liquid crystal display device incorporated with a liquid crystal display device test circuit, and all of the components shown herein are formed in the identical substrate. 
         [0048]    Examples detailed below represent some configuration suitable to test row lines. 
         [0049]    A liquid crystal display device  10  includes, as well known in the art, liquid crystal display elements arranged in matrix form, with each having its pixel electrode connected to a drain of a thin film transistor (TFT). The TFTs arranged in rows share row lines  2   l  to  2   n , having their respective gates commonly connected to these lines, and a selection from the row lines  2   l  to  2   n  is performed by a row driver  1 . The row driver  1  produces signals of two levels, namely, select and non-select, to the row line(s) that are to be activated for display. 
         [0050]    On the other hand, not shown in the drawings for simplification but well known in the art, the TFTs arranged in columns share column lines, have their respective sources commonly connected to these lines. Levels of voltage corresponding to the brightness of the display pixels are produced to the column lines by a column driver, and they are written in the associated pixel electrodes through the TFTs. In this way, transmissivity of liquid crystal is varied to attain an image with gradation. 
         [0051]    An operation where the row lines are selected will be described below. 
         [0052]    In  FIG. 1 , part depicted on the right of the liquid crystal display  10  is a liquid crystal display test circuit according to the present invention. 
         [0053]    Comparators  11   l  to  11   n  are connected to the row lines  2   l  to  2   n , respectively, and outputs from the comparators  11   l  to  11   n  are applied to encoders  12   l  to  12   n , respectively. A top dummy encoder  13  arranged in the upper side of the encoders  12   l  to  12   n  in stack while a bottom dummy encoder  14  arranged in the lower side of them. These encoders share a read-out bus  15  in producing their respective outputs to a read-out interface  16  from which produced are the numbers of lines that are to be activated. 
         [0054]      FIGS. 2 ,  4  and  6  show a configuration of the comparators  11   l  to  11   n  and a determination procedure in the same while  FIGS. 3 ,  5  and  7  are timing charts illustrating logic variations depending on the determination operation. 
         [0055]    In these comparators, there are provided transistors Q 1  and Q 2  in series where the transistor Q 1  has an inverting gate supplied with input voltage V IN  and has a threshold voltage of V thP  while the transistor Q 2  has an inverting gate supplied with an inverted sample signal. The couple of the transistors have their one terminal point connected to a high voltage V H  and the other terminal point or an associated node A connected to one input of an AND gate and one input of an exclusive OR (XOR) gate. Between the node A and a low voltage VL, there is provided a transistor Q 5  having a gate supplied with an inverted sample signal, so as to ensure initializing the node A with a low level. 
         [0056]    On the other hand, transistors Q 3  and Q 4  are connected in series, and the transistor Q 3  has its gate supplied with the input voltage V IN  and has a threshold value of V thN  while the transistor Q 4  has its gate supplied with a sample signal. The couple of the transistors Q 3  and Q 4  have their one terminal point connected to a low voltage V L  and the other terminal point or an associated node B connected to the other input of the AND gate and the other input of the exclusive OR (XOR) gate. Between the node B and the high voltage V H , there is provided a transistor Q 6  having its gate supplied with an inverted sample signal, so as to ensure initializing the node B with a high level. 
         [0057]    An output of the AND gate is connected to an inverting circuit of which output is a HI/LO signal indicating whether an output signal from the AND gate is at high level or low level, and an output signal from the XOR gate becomes invalid. 
         [0058]    The comparator circuit  11  uses two reference levels for inversion of input signals to determine which of the three levels the inverted input signals reach. Specifically, a potential level higher or sufficiently higher than the threshold value V thP  decreased from the high voltage V H  (V H −V thP ) is deemed to be High, a potential level lower or sufficiently lower than the threshold value V thN  raised from the low voltage V L  (V L +V thN ) is deemed to be Low, and an intermediate level is judged as being Invalid. In this way, excluding an event where the signal of such an intermediate and therefore unstable level appears in the rows and column lines, only the signals at sufficiently high or sufficient low level can be utilized. 
         [0059]    An operation to produce comparator outputs depending upon the levels of the input signals will be described on the case-by-case basis. It is now assumed that during the judgment, applied to the related gates are the sample signal Sample that is High in level and the inverted sample signal/Sample that is Low. 
         [0060]    First, referring to  FIGS. 2 and 3 , a case where the level of the input signal is greater than V H −V thP  will be described. 
         [0061]    In this case, the transistor Q 2  is turned on while the transistor Q 1  is not, and therefore the node A keeps Low in voltage level. The transistors Q 3  and Q 4 , however, are turned on, and hence, the node B turns to Low. Thus, as a result of logic operations, the HI/LO output signal is High while the Invalid output signal is Low, and therefore, it is determined that the input signal is a valid High signal. 
         [0062]    Next, with reference to  FIGS. 4 and 5 , another case where the input signal level is smaller than V L +V thN  will be described. 
         [0063]    In this case, the transistors Q 1 , Q 2  and Q 4  are turned on, and the nodes A and B are turned to High. Hence, the HI/LO output signal is Low while the Invalid output signal is Low, and therefore, it is determined that the input signal is a valid Low signal. 
         [0064]    Furthermore, still another case where the input signal level is greater than V L +V thN  and smaller than V H −V thP  will be described in conjunction with  FIGS. 6 and 7 . 
         [0065]    In this case, all the transistors Q 1  to Q 4  are turned on, and the node A is inverted to High while the node B is to Low. Thus, the HI/LO output signal is High while the Invalid output signal is High in level, and therefore, it is determined that the input signal is of an invalid level. 
         [0066]    As has been described, the comparator circuit  11  is capable of assuredly judging the three levels of High, Low, and Invalid, depending upon the level of the input signals, to transfer the results to an encoder circuit in the subsequent state. 
         [0067]      FIG. 8  is a circuit diagram showing a configuration of an encoder circuit  12 . The encoder circuit  12  employs a so-called “encyclical style” in encoding the numbers of rows only when a Down Scan signal from an encoder of a leading or upper row, or a Up Scan signal from an encoder of a trailing or lower row is High in level. 
         [0068]    The encoder circuit  12  has three parts, namely, a scan control logic circuitry  121 , a line buffer  122 , and a hardwire encoding unit  123 . 
         [0069]    In the scan control logic circuitry  121 , the HI/LO output from the comparator is supplied to an inverter  1211  and an AND gate  1215 , respectively. The inverter  1211  produces an output signal to AND gates  1212  and  1214 , respectively. On the other hand, since the Down Scan signal from the encoder of an upper row is supplied to the AND gate  1212 , an output from the AND gate  1212  is transferred as the Down Scan signal to the encoder of a succeeding lower row. Specifically, when the output from the comparator is Low, the AND gate receiving the Down Scan signal behaves to send the Down Scan signal to the encoder of the succeeding lower row. Contrary to this, when the output from the comparator is High, the Down Scan signal to the succeeding lower row would not be produced. 
         [0070]    Similarly, since the Up Scan signal from the lower row is supplied to the AND gate  1214 , the AND gate  1214 , receiving the Up Scan signal when the output from the comparator is Low, produces the Up Scan signal to the leading or upper row. 
         [0071]    The Down Scan signal from the upper row and the Up Scan signal from the lower row are applied to the OR gate  1213 , and the OR gate  1213  produces output signals to the remaining input terminals of the AND gates  1215  and  1216 . 
         [0072]    The AND gate  1215  generates an encoding signal when the output from the comparator is High and either the Down Scan signal or the Up Scan signal is High. The encoding signal causes a transistor  1222  in the line buffer  122  to turn on, and resultantly potentials at lines A 1 , A 4  and A 6  in the read-out bus and connected to the transistor is decreased down to a potential level V SS . An inverter  1217  inverts the output from the AND gate  1215  to produce an inverted signal to a gate of a transistor  1221  having its one terminal connected to V DD , and hence, potentials at lines A 0 , A 2 , A 3 , A 5  and A 7  connected to the other terminal of the transistor  1221  are raised up to the voltage level V DD . The hardwire encoder  123  are connected in advance to V DD  and V SS  depending upon the row number designated to the selected row line. In this case, the row number decoded as the bus number is 10110101 (i.e., 181 in decimal number). 
         [0073]    An invalid signal from the comparator is applied to the remaining input terminal of the AND gate  1216 , and hence, an inverter  1218  inverts an output signal from the AND gate  1216  when the invalid signal is High in level and the Down Scan signal or the Up Scan signal is High. The inverted signal from the transistor  1223  is transferred to a gate of a transistor  1223  having its one terminal connected to V DD , and an invalid signal line connected to the other terminal of the transistor turns to High, which leads to a determination that the output from the comparator is invalid. In this case, also, the decoded signal about the bus lines related with the row number can be obtained when a High/Low signal from the comparator is High, so as to let the user know which lines the output signal from the comparator becomes invalid in. Simultaneously, when the High/Low signal output from the comparator is High, the Up Scan signal and the Down Scan signal are prevented from being transferred to the next line. 
         [0074]    In the circuit  12 , as has been described, upon receiving a valid High signal from the comparator  11 , an output representing the row number is produced in the read-out bus, and if the output from the comparator is not High, the received Up Scan signal or the received Down Scan signal is transferred to the subsequent row. When the output from the comparator is invalid, the Invalid signal line is activated. 
         [0075]    In this concept of the circuit, the presence of the Up Scan signal or the Down Scan signal is presumed, and signal processing in the uppermost or lowermost encoder will be a matter of interest. In order to implement a satisfactory arrangement, proposed below will be a top dummy encoder depicted in the uppermost position in  FIG. 9  and a bottom dummy encoder depicted in the lowermost position in  FIG. 10 . 
         [0076]    The top dummy encoder  13  shown in  FIG. 9  also includes a scan control logic circuitry  131 , a line buffer  132 , and a hardwire encoder  133 , but since this encoder is a dummy, no output from the comparator is applied to it. No Down Scan signal is generated in this encoder. 
         [0077]    In the scan control logic circuitry  131 , the Up Scan signal is applied to a line of a lower row first, and this signal is directly passed to the line buffer  132  to make a transistor  1321  turn on, which results in all the read-out bus lines connected thereto being decreased in potential level down to V SS . Thus, the decoded row number as the numbers of the bus lines are 00000000 (0 in decimal number). 
         [0078]    An inverter  1311  in the scan control logic circuitry  131  inverts the Up Scan signal, and the inverted signal is transferred to a gate of a transistor  1223  having its one terminal connected to V DD . Thus, a High signal is produced to an Invalid signal line connected to the remaining input terminal of the transistor  1223 , and this clarifies that the dummy encoder does not produce the number of the row line unlike the ordinary encoders. 
         [0079]    The bottom dummy encoder shown in  FIG. 10  has a similar configuration to that of the top dummy encoder shown in  FIG. 9 , and branch lines in a scan control logic circuitry  141  let the Down Scan signal applied thereto pass to inverters  1411  and  1412 , and the signals inverted in the inverters are respectively transferred to gates of transistors  1421  and  1422  in a line buffer  142 . These transistors have their respective ones of terminals connected to V DD , and the transistor  1421  is turned on to raise a voltage level at the signal lines connected to the other terminal up to V DD  while the transistor  1422  is turned on to turn the invalid signal line to High in voltage level. In this way, the number of the row line decoded as the numbers of the bus lines are 11111111 (255 in decimal number), and this clarifies that the dummy encoder does not produce the number of the row unlike the ordinary encoders. 
         [0080]      FIG. 11  depicts a configuration of the interface  16 . In this circuit, there are nine flip flops FF 1  to FF 8  that receive a scan clock signal SCLK in synchronization with a clock, and FF 1  has its data terminal connected to the Invalid signal line. An output terminal of the FF 1  or the read-out bus line A 0  is selected by a switch SW 1 , and either of them is connected to a data input terminal of FF 1 . The remaining flip flops and bus lines are connected in the similar manner, and the last one of the flip flops, FF 8 , has its input terminal connected to either of an output of FF 7  in the previous stage or the read-out bus line A 7  which is selected by a switch SW 8 . The switches SW 1  to SW 8  are connected to the read-out buses during the first half of each row line reading cycle for either the up scanning or the down scanning so as to store the state of each bus line, namely, High or Low, in the related flip flop, and each of the switches is connected to the output of the flip flop in the previous stage during the latter half of the reading cycle, so as to serve as a shift register, thereby eventually producing SDATA containing serial data on the number of the activated row and column lines as a result of sequential outputs and relays. 
         [0081]    The SDATA is to be obtained for both the down scanning and the up scanning and then analyzed through a comparison of two of the results to judge pass or fail of the product. 
         [0082]      FIG. 12  is a flow chart simply illustrating the aforementioned procedure. First, one of the lines (in rows) is activated (Step S 1 ), and the down scanning is carried out (Step S 2 ) to obtain SDATA (Step S 3 ). For instance, executing the down scanning with the line of the third row being activated, SDATA indicating that the third row is being activated can be obtained if the device is in normal condition. 
         [0083]    Then, the up scanning is carried out (Step S 4 ) to produce SDATA (Step S 5 ). In this case, also, the device in normal condition eventually produces SDATA indicating that the third row is being activated. If the data SDATA obtained at Steps S 3  and S 5  are not identical with each other, or if the invalid signal is produced, the detection gives a result of error. 
         [0084]    An actual procedure for such an error detection will be described, returning to  FIG. 1 . 
         [0085]    Above all, it is assumed that no particular abnormality occurs in the device, and the row driver  1  selects the line of the 26 th  row. First, the down scanning is initiated from the top dummy encoder sequentially through the succeedingly upper rows till the 26 th  row in which the comparator  11   26  produces a High signal. This state of the signal activates the encoder  12   26 , and the hardwire encoder produces a sequence of data consisting of 1 for High level and 0 for Low level, and resultantly, passed to the read-out bus is a sequence of binary numbers of 00011010 or 26 in decimal manner. The binary data is produced from the read-out interface  16 . 
         [0086]    Then, the up scanning is initiated from the bottom dummy encoder sequentially through the succeedingly lower rows till the 26 th  row in which the comparator  11   26  produces a High signal. This state of the signal permits the read-out interface  16  to produce a sequence of binary data of 00011010. This binary number is identical to the resultant data from the down scanning, and therefore, it is judged that the line of the 26 th  row is normal. 
         [0087]    Next, it is assumed that the line of the 26 th  row is selected similar to the previous case but with some abnormality that the output from the comparator is passed to the line of the 25 th  row independent of the selection of the line. 
         [0088]    As has been described, the down scanning is initiated from the top dummy encoder sequentially through the succeedingly upper rows till the 25 th  row in which the comparator  11   25  produces a High signal. This state of the signal activates the encoder  12   25 , and the hardwire encoder produces a sequence of binary data consisting of 1 for High level and 0 for Low level, and resultantly, passed to the read-out bus is a sequence of binary numbers of 00011001 or 25 in decimal manner. The binary data is produced from the read-out interface  16 . 
         [0089]    Then, the up scanning is initiated from the bottom dummy encoder sequentially through the succeedingly lower rows till the 26 th  row in which the comparator  11   26  produces a High signal. This state of the signal permits the read-out interface  16  to produce a sequence of binary data of 00011010. This binary number is identical to the resultant data from the down scanning, and therefore, it is judged that the line of the 26 th  row is normal. 
         [0090]    In this situation, two of the read-out data are not identical, and thus, given is a judgment of “abnormal”. 
         [0091]    Additionally, when it is contradictorily found that no row line is selected despite the fact that the row driver  1  has selected one, an attempt to execute the down scanning results in the bottom dummy decoder generating a sequence of binary numbers of 11111111 or 256 in decimal manner, which leads to a judgment of “abnormal”. As a result of the up scanning, the top dummy encoder produces a sequence of binary numbers of 00000000 or 0 in decimal manner, and this also leads to a judgment of “abnormal”. 
         [0092]    As has been described, in accordance with the present invention, a simplified test circuit is built in the same substrate as the liquid crystal display elements, and this ensures to check states of wirings and operations of TFTs without visual inspections even before these components are embedded in liquid crystal. In this case, the test circuit that is to be built in is simplified in structure and occupies a smaller area in comparison with a driver, that is, the required area for the test circuit is not so much as taking up the effective area of the liquid crystal display device, as a whole. 
         [0093]    The circuitries described above are by way of examples only, and any person skilled in the art will be able to envision other circuit configurations that can attain the similar functions, from their knowledge of the state of the art. 
         [0094]    For example, although the test is carried out handling the row lines as base units in the aforementioned embodiments, the base unit may be replaced with the column lines among which any particular one is to be selected by a column driver to undergo the inspections on the above-mentioned test circuit provided therein for detecting abnormality. In such a case, typically, analog signals of multi-levels are applied to the column lines depending upon the brightness of the pixels, but in the test method according to the present invention, since a comparator circuit merely functions to judge if the selected line is activated, the column driver may produce simply two levels of voltage, namely, High and Low, to the selected column. 
         [0095]    The test circuits may be provided for both the rows and columns of the lines to make the inspections perfect. 
         [0096]    Although the invention has been described with reference to specific embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as alternative embodiments, will be apparent to persons skilled in the art. It is, therefore, contemplated that the appended claims will cover all modifications that fall within the true scope of the invention.