Abstract:
A base chip including first to Nth delay units coupled in series, where N is a natural number equal to or larger than 2, wherein when the number of stacked chips over the base chip is 1, the base chip is suitable for delaying a refresh signal, and generating first to Xth delayed refresh signals using the first to Xth delay units among the first to Nth delay units, where X is a natural number having a relation of N&gt;X≧1, and when the number of stacked chips over the base chip is 2, the base chip is suitable for delaying the refresh signal, and generating first to Yth delayed refresh signals using the first to Yth delay units among the first to Nth delay units, where Y is a natural number having a relation of N≧Y&gt;X.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application claims priority of Korean Patent Application No. 10-2015-0181523, filed on Dec. 18, 2015, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Field 
         [0003]    Exemplary embodiments of the present invention relate to a base chip and a semiconductor package including the same. 
         [0004]    2. Description of the Related Art 
         [0005]    A memory cell of a semiconductor memory device includes a transistor serving as a switch and a capacitor for storing an electric charge representing data. More specifically, according to whether or not an electric charge is stored in the capacitor of the memory cell or whether the terminal voltage of the capacitor is high or low, the data is determined to be high (logic 1) or low (logic 0). 
         [0006]    In principle, since data is stored as an accumulated electric charge, no power is consumed for maintaining the stored data. However, in practice, an initial charge stored in the capacitor may degrade due to a leakage current caused by the PN junction of a metal oxide semiconductor (MOS) transistor. As a result the data may be lost. In order to prevent such a data loss, the stored data in the memory cell must be read, and the memory cell must be recharged according to the read information, before the data is lost. Such an operation must be periodically repeated to retain the data. The process of recharging the memory cell is commonly known as a refresh operation. 
         [0007]    In general, a semiconductor memory device performs a refresh operation by periodically activating a word line, in order to retain data stored in memory cells coupled to the word line. A semiconductor memory device includes a plurality of memory banks each having a plurality of word lines. When all memory banks of the semiconductor memory device simultaneously activate word lines in order to perform a refresh operation, the peak current used in the semiconductor memory device may significantly rise. 
         [0008]      FIG. 1  is a diagram illustrating a plurality of memory banks BK 0  to BK 15  included in a semiconductor memory device.  FIGS. 2A to 2C  are diagrams for illustrating a piled refresh operation. 
         [0009]    Referring to  FIG. 1 , the memory banks BK 0  to BK 15  may perform a refresh operation when corresponding refresh signals among a plurality of refresh signals REF 0  to REF 15  are activated. 
         [0010]    Referring to  FIG. 2A , the refresh operations of the memory banks BK 0  to BK 15  included in the semiconductor memory device are performed at the same time. Thus, the peak current used in the semiconductor memory device is very high. 
         [0011]    Referring to  FIG. 28 , the plurality of memory banks BK 0  to BK 15  included in the semiconductor memory device is divided into four groups, and refresh operations of the four groups are sequentially performed. Thus, the peak current used in the semiconductor memory device is lowered compared to the case of  FIG. 2A . 
         [0012]    Referring to  FIG. 2C , the plurality of memory banks BK 0  to BK 15  included in the semiconductor memory device is divided into 16 groups, and refresh operations of the 16 groups are sequentially performed. Thus, the peak current used in the semiconductor memory device is lowered even more compared to the cases of  FIGS. 2A and 28 . 
         [0013]      FIG. 3  is a diagram illustrating a semiconductor package including a plurality of chips, a base chip BASE and a plurality of core chips CORE 0  to CORE 3 . 
         [0014]    Referring to  FIG. 3 , the plurality of core chips CORE 0  to CORE 3  each core chip including a plurality of memory banks (not shown) are sequentially stacked over the base chip BASE. The base chip BASE performs communication between the semiconductor package and an external device. The base chip BASE may generate signals for controlling the plurality of core chips CORE 0  to CORE 3  in response to a command received from the external device, and transmit the generated signals to the respective core chips through a plurality of Through Silicon Vias (TSVs). In this example, the signals for controlling the plurality of core chips CORE 0  to CORE 3  may include a signal for controlling the above-described refresh operation. 
         [0015]    In the semiconductor package, the number of memory banks which must be controlled by the base chip BASE may differ according to the number of stacked core chips. Furthermore, when the number of TSVs is increased to control the memory banks, the area of the chip may be significantly increased. 
       SUMMARY 
       [0016]    Various embodiments are directed to a base chip capable of generating signals for controlling refresh operations of memory banks according to the number of stacked core chips, while reducing the number of the Through Silicon Vias (TSVs) required for transmitting the signals, and a semiconductor package including the same. 
         [0017]    In an embodiment, there is provided a base chip including first to Nth delay units coupled in series, where N is a natural number equal to or larger than 2, wherein when the number of stacked chips over the base chip is 1, the base chip is suitable for delaying a refresh signal, and generating first to Xth delayed refresh signals using the first to Xth delay units among the first to Nth delay units, where X is a natural number having a relation of N&gt;X≧1, and when the number of stacked chips over the base chip is 2, the base chip is suitable for delaying the refresh signal, and generating first to Yth delayed refresh signals using the first to Yth delay units among the first to Nth delay units, where Y is a natural number having a relation of N≧Y&gt;X. 
         [0018]    In an embodiment, a semiconductor system may include: a base chip including first to Nth delay units coupled in series where N is a natural number equal to or larger than 2; and one or more first core chips sequentially stacked over the base chip, each core chip including first to Xth banks, and suitable for generating stack information regarding core chips stacked over the base chip based on the first value, wherein when the stack information indicates a first value, the base chip is suitable for delaying a refresh signal, and generating first to Xth delayed refresh signals using the first to Xth delay units among the first to Nth delay units, where X is a natural number having a relation of N&gt;X≧1, and when the stack information indicates a second value, the base chip is suitable for delaying the refresh signal, and generating first to Yth delayed refresh signals using the first to Yth delay units among the first to Nth delay units, where Y is a natural number having a relation of N≧Y&gt;X. 
         [0019]    In an embodiment, a semiconductor package may include: a base chip including a plurality of delay units coupled in series; and one or more core chips sequentially stacked over the base chip, and each including one or more bank, the base chip is suitable for delaying a refresh signal, and generating a plurality of delayed refresh signals, using delay units of which the number is set according to the number of stacked core chips, among the plurality of delay units. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]      FIG. 1  is a diagram illustrating a plurality of memory banks BK 0  to BK 15  included in a conventional semiconductor memory device. 
           [0021]      FIGS. 2A to 2C  are diagrams illustrating a conventional piled refresh operation. 
           [0022]      FIG. 3  is a diagram for illustrating a conventional semiconductor package including a plurality of chips BASE and CORE 0  to CORE 3 . 
           [0023]      FIG. 4  is a configuration diagram of a base chip according to an embodiment of the present invention. 
           [0024]      FIG. 5A  is a timing diagram illustrating the operation of the base chip of  FIG. 4 , when one core chip is stacked over the base chip. 
           [0025]      FIG. 5B  is a timing diagram illustrating the operation of the base chip of  FIG. 4 , when two core chips are stacked over the base chip. 
           [0026]      FIG. 6A  is a diagram illustrating a semiconductor system according to a first embodiment of the present invention. 
           [0027]      FIG. 6B  is a diagram illustrating a semiconductor system according to a second embodiment of the present invention. 
           [0028]      FIG. 7  is a configuration diagram of a core chip shown in  FIG. 6A . 
           [0029]      FIG. 8  is a configuration diagram of a second core chip shown in  FIG. 6B . 
           [0030]      FIG. 9  is a configuration diagram of a base chip according to another embodiment of the present invention. 
           [0031]      FIG. 10A  is a diagram illustrating a semiconductor system including a core chip according to a first embodiment of the present invention. 
           [0032]      FIG. 10B  is a diagram for illustrating a semiconductor system including a core chip according to a second embodiment of the present invention. 
           [0033]      FIG. 10C  is a diagram for illustrating a semiconductor system including a core chip according to a third embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0034]    Various embodiments will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. 
         [0035]    It will be understood that, although the terms “first”, “second”, “third”, and so on may be used herein to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element described below could also be termed as a second or third element without departing from the spirit and scope of the present disclosure. 
         [0036]    It will be further understood that when an element is referred to as being “connected to”, or “coupled to” another element, it can be directly on, connected to, or coupled to the other element, or one or more intervening elements may be present. 
         [0037]    In addition, it will also be understood that when an element is referred to as being “between” two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. 
         [0038]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. 
         [0039]    As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. 
         [0040]    It will be further understood that the terms “comprises”, “comprising”, “includes”, and “including” when used in this specification, specify the presence of the stated elements but do not preclude the presence or addition of one or more other elements. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
         [0041]    Unless otherwise defined, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
         [0042]    In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. The present disclosure may be practiced without some or all of these specific details. In other instances, well-known process structures and/or processes have not been described in detail in order not to unnecessarily obscure the present disclosure. 
         [0043]    In the following descriptions, a first refresh operation may indicate a normal refresh operation of sequentially refreshing all word lines (or all memory cells) included in a cell array (memory banks or the like) once during a refresh period tRFC defined in the specification, and a second refresh operation may indicate a smart refresh operation of additionally refreshing a word line one or more times during the refresh period, the word line satisfying a predetermined condition. 
         [0044]    Referring now to  FIG. 4  a base chip according to an embodiment of the present invention is provided. 
         [0045]    Accordingly, the base chip is generally designated with numeral  400  and may include first to eighth delay units DEL 1  to DEL 8 , a refresh counter  410 , a bank active signal generation unit  420 , first to eighth target address generation units  430 _ 1  to  430 _ 8 , an address selection unit  440 , a select signal generation unit  450 , and an identifier (ID) generation unit  460 . 
         [0046]    The first to eighth delay units DEL 1  to DEL 8  may be coupled in series. The first delay unit DEL 1  may receive a refresh signal REF which is activated when a refresh command is received. The first to fourth delay units DEL 1  to DEL 4  may be enabled in response to a first select signal SEL&lt; 1 &gt;, and the fifth to eighth delay units DEL 5  to DEL 8  may be enabled in response to a second select signal SEL&lt; 2 &gt;. When one core chip is stacked over the base chip, only the first select signal SEL&lt; 1 &gt; may be activated. When two core chips are stacked over the base chip, the first and second select signals SEL&lt; 1 : 2 &gt; may be activated. 
         [0047]    When one core chip is stacked over the base chip, the first to fourth delay units DEL 1  to DEL 4  may be enabled to generate first to fourth delayed refresh signals REFD 1  to REFD 4  by delaying the refresh signal REF by different delay values. When two core chips are stacked over the base chip, the first to eighth delay units DEL 1  to DEL 8  may be enabled to generate first to eighth delayed refresh signals REFD 1  to REFD 8  by delaying the refresh signal REF by different delay values. 
         [0048]    The refresh counter  410  may generate a counting address CNT_ADD by performing counting in response to the delayed refresh signal REFD 4  or REFD 8  which is finally activated among the plurality of delayed refresh signals REFD 1  to REFD 8 . When only the first select signal SEL&lt; 1 &gt; of the first and second select signals SEL&lt; 1 : 2 &gt; is activated, a selector  401  may select the fourth delayed refresh signal REFD 4  between the fourth and eighth delayed refresh signals REFD 4  and REFD 8 , and output the selected refresh signal REFD 4  as an output refresh signal OUT_REFD. When both of the first and second signals SEL&lt; 1 : 2 &gt; are activated, the selector  401  may select the eighth delayed refresh signal REFD 8  between the fourth and eighth delayed refresh signals REFD 4  and REFD 8 , and output the selected refresh signal REFD 8  as an output refresh signal OUT_REFD. 
         [0049]    The refresh counter  410  may perform counting in response to the output refresh signal OUT_REFD of the selector  401 , and increase the value of the counting address CNT_ADD by 1. When the value of the counting address CNT_ADD is increased by 1, it may indicate that, currently, the counting address CNT_ADD is changed to select a (K+1)th word line (e.g., at a (T+1) time) in case where the Kth word line was selected previously (e.g., at a (T) time). When a second refresh signal SR which is activated during the second refresh operation is activated, the refresh counter  410  may not perform counting even though the output refresh signal OUT_REFD of the selector  401  is activated. 
         [0050]    The bank active signal generation unit  420  may generate a plurality of bank active signals RACT&lt; 1 : 8 &gt; for controlling active operations of a plurality of banks. The bank active signal generation unit  420  may activate a bank active signal corresponding to a bank address BA_ADD when an active command ACT is activated. The bank active signal generation unit  420  may activate a bank active signal corresponding to an activated delayed refresh signal among the first to eighth delayed refresh signals REFD 1  to REFD 8 , during a predetermined period. The first to eighth delayed refresh signals REFD 1  to REFD 8  may correspond to the first to eighth bank active signals RACT&lt; 1 : 8 &gt;, respectively. 
         [0051]    The first to eighth target address generation units  430 _ 1  to  430 _ 8  may generate corresponding target addresses among first to eighth target addresses TAR_ADD 1  to TAR_ADD 8 . More specifically, when the first select signal SEL&lt; 1 &gt; and the second refresh signal SR are activated, the first to fourth target address generation units  430 _ 1  to  430 _ 4  may generate and output the first to fourth target addresses TAR_ADD 1  to TAR_ADDR 4  in response to the corresponding bank active signals among the first to fourth bank active signals RACT&lt; 1 : 4 &gt;. 
         [0052]    Furthermore, when the second select signal SEL&lt; 2 &gt; and the second refresh signal SR are activated, the fifth to eighth target address generation units  430 _ 5  to  430 _ 8  may generate and output the fifth to eighth target addresses TAR_ADD 5  to TAR_ADDR 8  in response to the corresponding bank active signals among the fifth to eighth bank active signals RACT&lt; 5 : 8 &gt;. 
         [0053]    At this time, the Kth target address generation unit  430 _K may output the Kth target address TAR_ADDK at a period between the point of time that the Kth bank active signal RACT&lt;K&gt; is activated and the point of time that the (K+1)th bank active signal RACT&lt;K+1&gt; is activated. 
         [0054]    The first to fourth target address generation units  430 _ 1  to  430 _ 4  may store an input address IN_ADD when corresponding detection signals among first to fourth detection signals DET 1  to DET 4  are activated in case where the first select signal SEL&lt; 1 &gt; is activated. The fifth to eighth target address generation units  430 _ 5  to  430 _ 8  may store an input address IN_ADD when corresponding detection signals among fifth to eighth detection signals DET 5  to DET 8  are activated in case where the second select signal SEL&lt; 2 &gt; is activated. Each of the first: to eighth detection signals DET 1  to DET 8  may be activated when a word line of which the active number or frequency is equal to or more than a reference number or frequency occurs in a corresponding memory bank (e.g., BK 0 -BK 15  in  FIG. 1 ). In order to detect a word line of which the active number or frequency is equal to or more than the reference number or frequency in the memory device, a predetermined algorithm may be used. 
         [0055]    The first to eighth target address generation units  430 _ 1  to  430 _ 8  may generate the first to eighth target addresses TAR_ADD 1  to TAR_ADD 8  by adding or subtracting a predetermined value to or from the stored addresses, respectively. For example, the first to eighth target address generation units  430 _ 1  to  430 _ 8  may generate the first to eighth target addresses TAR_ADD 1  to TAR_ADD 8  by adding or subtracting 1 to or from the stored addresses, respectively. 
         [0056]    During an active operation in which the refresh signal REF is deactivated, the address selection unit  440  may select an input address IN_ADD inputted through a first input terminal IN 1  and output the selected input address IN_ADD as the selected address SEL_ADD. During the first refresh operation in which the refresh signal REF is activated and the second refresh signal SR is deactivated, the address selection unit  440  may select a counting address CNT_ADD inputted through a second input terminal IN 2 , and output the selected counting address CNT_ADD as the selected address SEL_ADD. During the second refresh operation in which the refresh signal REF is activated and the second refresh signal SR is activated, the address selection unit  440  may select a target address inputted through a third input terminal IN 3 , and output the selected target address as the selected address SEL_ADD. The target address inputted through the third input terminal IN 3  may include the first to fourth target addresses TAR_ADD 1  to TAR_ADD 4  or the first to eighth target addresses TAR_ADD 1  to TAR_ADD 8 . 
         [0057]    The select signal generation unit  450  may activate only the first select signal SEL&lt; 1 &gt; when the value of stack information STACK&lt; 1 : 0 &gt; is ‘01’, and activate both of the first and second select signals SEL&lt; 1 : 2 &gt; when the value of the stack information STACK&lt; 1 : 0 &gt; is ‘10’. The ID generation unit  460  may generate and output ID information ID&lt; 1 : 0 &gt; having a value of ‘00’. 
         [0058]    The base chip of  FIG. 4  can supply a proper number of delayed refresh signals by changing the number of delay units which are used according to the number of core chips stacked over the base chip. Thus, the base chip may perform a proper piled refresh operation according to the number of stacked core chips. 
         [0059]      FIG. 5A  is a timing diagram illustrating the operation of the base chip of  FIG. 4 , when one core chip is stacked over the base chip. 
         [0060]    Referring to  FIG. 5A , when one core chip is stacked over the base chip, the first select signal SEL&lt; 1 &gt; may be maintained in an active state (e.g., high), and the second select signal SEL&lt; 2 &gt; may be maintained in an inactive state (e.g., low). 
         [0061]    When the refresh signal REF is activated in a state where only the first select signal SEL&lt; 1 &gt; is activated, the first to fourth delayed refresh signals REFD 1  to REFD 4  may be sequentially activated, and the first to fourth bank active signals RACT&lt; 1 : 4 &gt; may be sequentially activated during a predetermined period, in response to the first to fourth delayed refresh signals REFD 1  to REFD 4 . 
         [0062]    At this time, when the second refresh signal SR is deactivated, the counting address CNT_ADD may be outputted as the selected address SEL_ADD, while when the second refresh signal SR is activated, the first to fourth target addresses TAR_ADD 1  to TAR_ADD 4  may be sequentially outputted as the selected address SEL_ADD. 
         [0063]    The fifth to eighth delayed refresh signals REFD 5  to REFD 8 , the fifth to eighth bank active signals RACT&lt; 5 : 8 &gt;, and the fifth to eighth target addresses TAR_ADD 5  to TAR_ADD 8  may be maintained in an inactive state. 
         [0064]      FIG. 5B  is a timing diagram for illustrating the operation of the base chip of  FIG. 4 , when two core chips are stacked over the base chip. 
         [0065]    Referring to  FIG. 5B , when two core chips are stacked over the base chip, the first and second select signals SEL&lt; 1 : 2 &gt; may be maintained in an active state (e.g., high). 
         [0066]    When the refresh signal REF is activated in a state where the first and second select signals SEL&lt; 1 : 2 &gt; are activated, the first to eighth delayed refresh signals REFD 1  to REFD 8  may be sequentially activated, and the first to eighth bank active signals RACT&lt; 1 : 8 &gt; may be sequentially activated during a predetermined period, in response to the first to eighth delayed refresh signals REFD 1  to REFD 8 . 
         [0067]    At this time, when the second refresh signal SR is deactivated, the counting address CNT_ADD may be outputted as the selected address SEL_ADD, while when the second refresh signal SR is activated, the first to eighth target addresses TAR_ADD 1  to TAR_ADD 8  may be sequentially outputted as the selected address SEL_ADD. 
         [0068]      FIG. 6A  is a diagram for illustrating a semiconductor system according to a first embodiment of the present invention. 
         [0069]    Referring to  FIG. 6A , the semiconductor system may include a base chip  610   a  and a core chip  620   a  stacked over the base chip  610   a . The base chip  610   a  of  FIG. 6A  may include the base chip described with reference to  FIG. 4 . 
         [0070]    The first to fourth bank active signals RACT&lt; 1 : 4 &gt;, the first to fourth target addresses TAR_ADD 1  to TAR_ADD 4 , and the chip ID information ID&lt; 0 : 1 &gt;, which are generated from the base chip  610   a , may be transmitted to the core chip  620   a  through one or more of a plurality of TSVs. Furthermore, the stack information STACK&lt; 1 : 0 &gt; generated from the core chip  620   a  may be transmitted to the base chip  610   a  through one or more of the plurality of the TSVs. For reference, the number of TSVs illustrated in  FIG. 6A  is only an example, and an actual semiconductor system may include a larger number of TSVs than illustrated in  FIG. 6A . 
         [0071]      FIG. 6B  illustrates a semiconductor system according to a second embodiment of the present invention. 
         [0072]    Referring to  FIG. 6B , the semiconductor system may include a base chip  610   b  and two core chips  620   b  and  630   b  stacked over the base chip  610   b . The base chip  610   b  of  FIG. 6B  may include the base chip described with reference to  FIG. 4 . 
         [0073]    The first to eighth bank active signals RACT&lt; 1 : 8 &gt;, the first to eighth target addresses TAR_ADD 1  to TAR_ADD 8 , and the chip ID information ID&lt; 1 : 0 &gt;, which are generated from the base chip  610   b , may be transmitted to the first or second core chip  620   a  or  630   a  through one or more of a plurality of TSVs. Furthermore, the stack information STACK&lt; 1 : 0 &gt; generated from the second core chip  630   b  may be transmitted to the base chip  610   b  through one or more of the plurality of TSVs. For reference, the number of TSVs illustrated in  FIG. 6B  is only an example, and an actual semiconductor system may include a larger number of TSVs than illustrated in  FIG. 6B . 
         [0074]      FIG. 7  is a configuration diagram of the core chip  620   a  in  FIG. 6A . 
         [0075]    Referring to  FIG. 7 , the core chip  620   a  may include first to fourth memory banks BK 1  to BK 4 , an addition unit  710 , and a stack information transmission unit  720 . 
         [0076]    The first to fourth memory banks BK 1  to BK 4  may include a plurality of word lines (not illustrated in  FIG. 7 ), a plurality of bit lines (not illustrated in  FIG. 7 ), and a plurality of memory cells (not illustrated in  FIG. 7 ) coupled between the plurality of word lines and the plurality of bit lines. The first to fourth memory banks BK 1  to BK 4  may each perform an active operation in response to corresponding bank active signals among the first to fourth bank active signals RACT&lt; 1 : 4 &gt;, respectively. The first to fourth memory banks BK 1  to BK 4  may each activate and precharge a word line corresponding to an address SEL_ADD transmitted from the base chip  610   a  in response to the bank active signals RACT&lt; 1 : 4 &gt;, respectively. For example, in response to a bank active signal RACT&lt; 1 &gt;, the first memory bank BK 1  may activate and precharge a word line corresponding to an address SEL_ADD transmitted from the base chip  610   a.    
         [0077]    The addition unit  710  may generate a chip ID 1 &lt; 1 : 0 &gt; by adding 1 to the ID information ID&lt; 1 : 0 &gt;. Since the value of the ID information ID&lt; 1 : 0 &gt; transmitted from the base chip  610   a  is ‘00’, the chip ID 1 &lt; 1 : 0 &gt; generated from the core chip  620   a  may have a value of ‘01’. 
         [0078]    When no chips are stacked over the core chip  620   a  (EN 1  is activated), the stack information transmission unit  720  may transmit the chip ID ID 1 &lt; 1 : 0 &gt; as the stack information STACK&lt; 1 : 0 &gt; to the base chip  610   a . For reference, the first core chip  620   b  of  FIG. 6B  may be configured and operated in the same manner as the core chip  620   a  of  FIG. 6A . 
         [0079]      FIG. 8  is a configuration diagram of the second core chip  630   b  in  FIG. 6B . 
         [0080]    Referring to  FIG. 8 , the second core chip  630   b  may include fifth to eighth memory banks BK 5  to BK 8 , an addition unit  810 , and a stack information transmission unit  820 . 
         [0081]    The fifth to eighth memory banks BK 5  to BK 8  may each include a plurality of word lines (not illustrated in  FIG. 8 ), a plurality of bit lines (not illustrated in  FIG. 8 ), and a plurality of memory cells (not illustrated in  FIG. 8 ) coupled between the plurality of word lines and the plurality of bit lines. The fifth to eighth memory banks BK 5  to BK 8  may each perform an active operation in response to corresponding bank active signals among the fifth to eighth bank active signals RACT&lt; 5 : 8 &gt;, respectively. The fifth to eighth memory banks BK 5  to BK 8  may each activate and precharge a word line corresponding to an address SEL_ADD transmitted from the base chip  610   b  in response to the bank active signals RACT&lt; 5 : 8 &gt;, respectively. For example, the fifth memory bank BK 5  may activate and precharge a word line corresponding to an address SEL_ADD transmitted from the base chip  610   b  in response to the bank active signal RACT&lt; 5 &gt;. 
         [0082]    The addition unit  810  may generate a chip ID ID 2 &lt; 1 : 0 &gt; by adding 1 to the chip ID ID 1 &lt; 1 : 0 &gt; transmitted from the first core chip  62   b . Since the chip ID ID 1 &lt; 1 : 0 &gt; transmitted from the first core chip  620   b  has a value of ‘01’, the chip ID ID 2 &lt; 1 : 0 &gt; generated from the second core chip  630   b  may have a value of ‘10’. 
         [0083]    When no chips are stacked over the core chip  630   b  (EN 2  is activated), the stack information transmission unit  820  may transmit the chip ID ID 2 &lt; 1 : 0 &gt; as the stack information STACK&lt; 1 : 0 &gt; to the base chip  610   b . For example, when the second core chip  630   b  is stacked over the first core chip  620   b , the enable signal EN 1  may be deactivated, and the stack information transmission unit  720  of the first core chip  620   b  may not output the chip ID ID 1 &lt; 1 : 0 &gt; as the stack information STACK&lt; 1 : 0 &gt;. 
         [0084]    Referring to  FIGS. 6A to 8 , a piled refresh may be controlled according to the number of core chips stacked in the semiconductor system. For example, when the number of stacked core chips is 1, a 4-piled refresh may be performed, while when the number of stacked core chips is 2, an 8-piled refresh may be performed. Thus, since the target addresses, which are to be transmitted to the respective memory banks, are outputted (refer to  FIGS. 5A and 5B ) at separate points of time, all necessary addresses may be transmitted to all of the memory banks, even though there exist only a set of TSVs for transmitting the addresses. Hence, the number of TSVs may be decreased thus reducing the area of each semiconductor chip. 
         [0085]      FIG. 9  is a configuration diagram: of a base chip, according to another embodiment of the present invention. 
         [0086]    Referring to  FIG. 9 , the base chip may include an identifier (ID) generation unit  901  and first to eighth channel control units  910  to  980 . The ID generation unit  901  may generate and output ID information ID&lt; 2 : 0 &gt; having a value of ‘000’. 
         [0087]    The first channel control unit  910  may include first to 32nd delay units DEL 1  to DEL 32 , a refresh counter  911 , a bank active signal generation unit  912 , first to 32nd target address generation units  913 _ 1  to  913 _ 32 , and an address selection unit  914 . The second to eighth channel control units  920  to  980  may have the same configuration as the first channel control unit  910 . 
         [0088]    The first to 32nd delay units DEL 1  to DEL 32  may be coupled in series, and the first delay unit DEL 1  may receive a refresh signal REF which is activated when a refresh command is received. The first to eighth delay units DEL 1  to DEL 8  may be enabled when two core chips are stacked over the base chip (i.e., T 2 HI is activated), the ninth to 16th delay units DEL 9  to DEL 16  may be enabled when four core chips are stacked over the base chip (i.e., T 2 HI and T 4 HI are activated), and the 17th to 32nd delay units DEL 17  to DEL 32  may be enabled when eight core chips are stacked over the base chip (i.e., T 2 HI, T 4 HI, and T 8 HI are activated). 
         [0089]    When two core chips are stacked over the base chip (first embodiment), the first to eighth delay units DEL 1  to DEL 8  may be enabled to generate first to eighth delayed refresh signals REFD 1  to REFD 8  by delaying a refresh signal REF by different delay values. 
         [0090]    When four core chips are stacked over the base chip (second embodiment), the first to 16th delay units DEL 1  to DEL 16  may be enabled to generate first to 16th delayed refresh signals REFD 1  to REFD 16  by delaying the refresh signal REF by different delay values. 
         [0091]    When eight core chips are stacked over the base chip (third embodiment), the first to 32nd delay units DEL 1  to DEL 32  may be enabled to generate first to 32nd delayed refresh signals REFD 1  to REFD 32  by delaying the refresh signal REF by different delay values. 
         [0092]    The refresh counter  911  may generate a counting address CNT_ADD by performing counting in response to the delayed refresh signal REFD 8 , REFD 16 , or REFD 32  which is finally activated among the plurality of delayed refresh signals. The selector  915  may select and output the eighth delayed refresh signal REFD 8  when only T 2 HI is activated, select and output the 16th delayed refresh signal REFD 16  when T 2 HI and T 4 HI are activated, and select and output the 32nd refresh signal REFD 32  when T 2 HI, T 4 HI, and T 8 HI are activated. 
         [0093]    The refresh counter  911  may be configured and operated in the same manner as the refresh counter  410  of  FIG. 4 . 
         [0094]    The bank active signal generation unit  912  may generate a plurality of bank active signals RACT&lt; 1 : 32 &gt; for controlling active operations of a plurality of banks. The bank active signal generation unit  912  may activate a bank active signal corresponding to a bank address BA_ADD when an active command ACT is activated. The bank active signal generation unit  912  may activate a bank active signal corresponding to an activated delayed refresh signal among the first to 32nd delayed refresh signals REFD 1  to REFD 32 , during a predetermined period. The first to 32nd delayed refresh signals REFD 1  to REFD 32  may correspond to the first to 32nd bank active signals RACT&lt; 1 : 32 &gt;, respectively. 
         [0095]    The first to 32nd target address generation units  913 _ 1  to  913 _ 32  may generate corresponding target addresses among first to 32nd target addresses TAR_ADD 1  to TAR_ADD 32 , when the second refresh signal SR is activated. 
         [0096]    More specifically, when T 2 HI is activated, the first to eighth target address generation units  913 _ 1  to  913 _ 8  may generate and output the first to eighth target addresses TAR_ADD 1  to TAR_ADD 8  in response to the first to eighth bank active signals RACT&lt; 1 : 8 &gt;, respectively. Furthermore, when T 4 HI is activated, the ninth to 16th target address generation units  913 _ 9  to  913 _ 16  may generate and output the ninth to 16th target addresses TAR_ADD 9  to TAR_ADD 16  in response to the ninth to 16th bank active signals RACT&lt; 9 : 16 &gt;, respectively. Furthermore, when T 8 HI is activated, the 17th to 32nd target address generation units  913 _ 17  to  913 _ 32  may generate and output the 17th to 32nd target addresses TAR_ADD 17  to TAR_ADD 32  in response to the 17th to 32nd bank active signals RACT&lt; 17 : 32 &gt;, respectively. 
         [0097]    For example, a Kth target address generation unit  913 _K may output the Kth target address TAR_ADDK between the point of time that the Kth bank active signal RACT&lt;K&gt; is activated and the point of time that the (K+1)th bank active signal RACT&lt;K+1&gt; is activated. 
         [0098]    The first to eighth target address generation units  913 _ 1  to  913 _ 8  may store an input address IN_ADD when corresponding detection signals among first to eighth detection signals DET 1  to DET 8  are activated in case where T 2 HI is activated. The ninth to 16th target address generation units  913 _ 9  to  913 _ 16  may store an input address IN_ADD when corresponding detection signals among ninth to 16th detection signals DET 9  to DET 16  are activated in case where T 4 HI is activated. The 17th to 32nd target address generation units  913 _ 17  to  913 _ 32  may store an input address IN_ADD when corresponding detection signals among 17th to 32nd detection signals DET 17  to DET 32  are activated in case where T 8 HI is activated. 
         [0099]    The first to 32nd target address generation units  913 _ 1  to  913 _ 32  may generate the first to 32nd target addresses TAR_ADD 1  to TAR_ADD 32  by adding or subtracting a predetermined value to or from the stored addresses. For example, the first to 32nd target address generation units  913 _ 1  to  913 _ 32  may generate the first to 32nd target addresses TAR_ADD 1  to TAR_ADD 32  by adding or subtracting 1 to or from the stored addresses. 
         [0100]    During an active operation in which the refresh signal REF is deactivated, the address selection unit  914  may select an input address IN_ADD inputted through a first input terminal IN 1  and output the selected input address as the selected address SEL_ADD. During the first refresh operation in which the refresh signal REF is activated and the second refresh signal SR is deactivated, the address selection unit  914  may select a counting address CNT_ADD inputted through a second input terminal IN 2  and output the select counting address as the selected signal SEL_ADD. During the second refresh operation in which the refresh signal REF is activated and the second refresh signal SR is activated, the address selection unit  914  may select a target address inputted through a third input terminal IN 3  and output the selected target address as the selected address. The address inputted through the third input terminal IN 3  may include the first to eighth target addresses TAR_ADD 1  to TAR_ADD 8 , the first to 16th target addresses TAR_ADD 1  to TAR_ADD 16 , or the first to 32nd target addresses TAR_ADD 1  to TAR_ADD 32 . 
         [0101]    The second to eighth channel control units  920  to  980  may have the same configuration as the first channel control unit  910 . Each of the first to eighth channel control units  910  to  980  may independently control the operation of a channel including a plurality of memory banks. The first to eighth channel control units  910  to  980  may be independently operated while exchanging signals such as commands, addresses, and data with the outside of the semiconductor system. 
         [0102]    In the above descriptions, T 2 HI, T 4 HI, and T 8 HI represent stack information indicating how many core chips are stacked over the base chip. When two core chips are stacked, T 2 HI may be activated. When four core chips are stacked, T 2 HI and T 4 HI may be activated. When eight core chips are stacked, T 2 HI, T 4 HI, and T 8 HI may be activated. 
         [0103]    The base chip of  FIG. 9  may supply a proper number of delayed refresh signals by changing the number of delay units which are used according to the number of core chips stacked over the base chip. Thus, the base chip may perform a proper piled refresh operation according to the number of stacked core chips. 
         [0104]      FIG. 11A  illustrates a semiconductor system including a core chip according to a first embodiment of the present invention. 
         [0105]    Referring to  FIG. 10A , the semiconductor system may include a base chip  1010   a  and first and second core chips  1020   a  and  1030   a  which are sequentially stacked over the base chip  1010   a.    
         [0106]    The first core chip  1020   a  may include bank groups CH 1 _BG 1 , CH 3 _BG 1 , CH 5 _BG 1 , and CH 7 _BG 1  corresponding to first, third, fifth, and seventh channels. The second core chip  1030   a  may include bank groups CH 2 _BG 1 , CH 4 _BG 1 , CH 6 _BG 1 , and CH 8 _BG 1  corresponding to second, fourth, sixth, and eighth channels. The first core chip  1020   a  may include an addition units A 1 , an operation units O 1 , and a transmission unit T 1 . The second core chip  1030   a  may include an addition units A 2 , an operation units O 2 , and a transmission unit T 2 . Hereafter, let us suppose, as an example, that each of the bank groups includes eight memory banks. 
         [0107]    The bank groups corresponding to the first to eighth channels may be controlled by the first to eighth channel control units  910  to  980  of the base chip  1010   a  in  FIG. 9 , respectively. Hereafter, the operation of the semiconductor system will be described, while focused on the first channel. 
         [0108]    The first to eighth bank active signals RACT&lt; 1 : 8 &gt; and the first to eighth target addresses TAR_ADD 1  to TAR_ADD 8 , which are generated through the base chip  1010   a , may be transmitted to the first core chip  1020   a  through TSVs. For reference, the number of TSVs illustrated in  FIG. 10A  is only an example, and an actual semiconductor system may include a larger number of TSVs than illustrated in  FIG. 10A . 
         [0109]    For reference, a method for generating stack information T 4 HI and T 8 HI will be described below with reference to  FIG. 10C . 
         [0110]      FIG. 10B  is a diagram for illustrating a semiconductor system including a core chip according to a second embodiment of the present invention. 
         [0111]    Referring to  FIG. 10B , the semiconductor system may include a base chip  1010   b  and first to fourth core chips  1020   b  to  1050   b  which are sequentially stacked over the base chip  1010   b . The first to fourth core chips  1020   b  to  1050   b  may include addition units A 1  to A 4 , operation units O 1  to O 4 , and transmission units T 1  to T 4 , respectively. 
         [0112]    The first and second core chips  1020   b  and  1030   b  may be configured and operated in the same manner as the first and second core chips  1020   a  and  1030   a , respectively. 
         [0113]    The third core chip  1040   b  may include bank groups CH 1 _BG 2 , CH 3 _BG 2 , CH 5 _BG 2 , and CH 7 _BG 2  corresponding to the first, third, fifth, and seventh channels. The fourth core chip  1050   b  may include bank groups CH 2 _BG 2 , CH 4 _BG 2 , CH 6 _BG 2 , and CH 8 _BG 2  corresponding to the second, fourth, sixth, and eighth channels. 
         [0114]    The ninth to 16th bank active signals RACT&lt; 9 : 16 &gt; and the ninth to 16th target addresses TAR_ADD 9  to TAR_ADD 16 , which are generated from the base chip  1010   b , may be transmitted to the third core chip  1040   a  through TSVs. For reference, the number of TSVs illustrated in  FIG. 10B  is only an example, and an actual semiconductor system may include a larger number of TSVs than illustrated in  FIG. 10B . 
         [0115]    For reference, the method for generating stack information T 4 HI and T 8 HI will be described below with reference to  FIG. 10C . 
         [0116]      FIG. 10C  is a diagram for illustrating a semiconductor system including a core chip according to a third embodiment of the present invention. 
         [0117]    Referring to  FIG. 10C , the semiconductor system may include a base chip  1010   c  and first to eighth core chips  1020   c  to  1090   c  which are sequentially stacked over the base chip  1010   c . The first to eighth core chips  1020   c  and  1090   c  may include addition units A 1  to A 8 , operation units O 1  to O 8 , and transmission units T 1  to T 8 , respectively. 
         [0118]    The first to fourth core chips  1020   c  to  1050   c  may be configured and operated in the same manner as the first to fourth core chips  1020   b  to  1050   b , respectively. 
         [0119]    The fifth core chip  1060   c  may include bank groups CH 1 _BG 3 , CH 3 _BG 3 , CH 5 _BG 3 , and CH 7 _BG 3  corresponding to the first, third, fifth, and seventh channels. The sixth core chip  1070   c  may include bank groups CH 2 _BG 3 , CH 4 _BG 3 , CH 6 _BG 3 , and CH 8 _BG 3  corresponding to the second, fourth, sixth, and eighth channels. The seventh core chip  1080   c  may include bank groups CH 1 _BG 4 , CH 3 _BG 4 , CH 5 _BG 4 , and CH 7 _BG 4  corresponding to the first, third, fifth, and seventh channels. The eighth core chip  1090   c  may include bank groups CH 2 _BG 4 , CH 4 _BG 4 , CH 6 _BG 4 , and CH 8 _BG 4  corresponding to the second, fourth, sixth, and eighth channels. 
         [0120]    The 17th to 24th bank active signals RACT&lt; 17 : 24 &gt; and the 17th to 24th target addresses TAR_ADD 17  to TAR_ADD 24 , which are generated from the base chip  1010   c , may be transmitted to the fifth core chip  1060   c  through TSVs. The 25th to 32nd bank active signals RACT&lt; 25 : 32 &gt; and the 25th to 32nd target addresses TAR_ADD 25  to TAR_ADD 32 , which are generated through the base chip  1010   c , may be transmitted to the seventh core chip  1080   c  through TSVs. 
         [0121]    It is noted that the number of TSVs illustrated in  FIG. 10C  is only an example, and an actual semiconductor system may include a larger number of TSVs than illustrated in  FIG. 10C . 
         [0122]    Hereafter, the method for generating stack information T 2 HI, T 4 HI, and T 8 HI will be described with reference to  FIG. 10C . 
         [0123]    The first to eighth core chips  1020   c  and  1090   c  may include addition units A 1  to A 8 , operation units O 1  to O 8 , and transmission units T 1  to T 8 , respectively. In order that all of the eight channels included in the semiconductor system are used, two or more core chips need to be stacked. Thus, when a packaging process for the semiconductor system is completed, T 2 HI may be unconditionally activated. 
         [0124]    Each of the addition units A 1  to A 8  may receive ID information ID&lt; 2 : 0 &gt;, a chip ID ID 1 &lt; 2 : 0 &gt;, . . . , and ID 7 &lt; 2 : 0 &gt; outputted from the chip stacked under the chip including the corresponding addition unit, and generate the corresponding chip ID by adding 1 to the received ID information or chip ID. 
         [0125]    When information inputted to each of the operation units O 1  to O 8  is IDK&lt; 2 : 0 &gt;, a first operation value OV 1 &lt; 1 &gt;, . . . , or OV 8 &lt; 1 &gt; of the operation unit may be calculated through an equation of OUT&lt; 1 &gt;=IDK&lt; 0 &gt;*IDK&lt; 1 &gt;, and a second operation value OV 1 &lt; 2 &gt;, . . . , or OV 8 &lt; 2 &gt; of the operation unit may be calculated through an equation of OUT&lt; 2 &gt;=IDK&lt; 0 &gt;*IDK&lt;l&gt;*IDK&lt; 2 &gt;. 
         [0126]    The chip information ID&lt; 2 : 0 &gt; may be inputted to the operation unit O 1 , the chip ID ID 2 &lt; 2 : 0 &gt; may be inputted to the operation unit O 2 , the chip ID ID 2 &lt; 2 : 0 &gt; may be inputted to the operation unit O 3 , the chip ID ID 4 &lt; 2 : 0 &gt; may be inputted to the operation unit O 4 , the chip ID ID 4 &lt; 2 : 0 &gt; may be inputted to the operation unit O 5 , the chip ID ID 6 &lt; 2 : 0 &gt; may be inputted to the operation unit O 6 , the chip ID ID 6 &lt; 2 : 0 &gt; may be inputted to the operation unit O 7 , and the chip ID ID 8 &lt; 2 : 0 &gt; may be inputted to the operation unit O 8 . 
         [0127]    Each of the transmission units T 1  to T 8  may include two tri-state buffers (not illustrated in  FIG. 10C ). The transmission units T 1  to T 8  may output first output signals OUT 1 &lt; 1 &gt; to OUT 8 &lt; 1 &gt; indicating a high-impedance state when the first operation values OV 1 &lt; 1 &gt; to OV 1 &lt; 8 &gt; are 0, respectively. The transmission units T 1  to T 8  may output the first output signals OUT 1 &lt; 1 &gt; to OUT 8 &lt; 1 &gt; at a high level when the first operation values OV 1 &lt; 1 &gt; to OV 1 &lt; 8 &gt; are 1, respectively. The high-impedance state may indicate a state in which no values are outputted. Furthermore, the transmission units T 1  to T 8  may output second output signals OUT 1 &lt; 2 &gt; to OUT 8 &lt; 2 &gt; indicating a high-impedance state when the second operation values OV 2 &lt; 1 &gt; to OV 2 &lt; 8 &gt; are 0, respectively. The transmission units T 1  to T 8  may output the second output signals OUT 1 &lt; 2 &gt; to OUT 8 &lt; 2 &gt; at a high level when the second operation values OV 2 &lt; 1 &gt; to OV 2 &lt; 8 &gt; are 1, respectively. 
         [0128]    In the above-described configuration, when the number of stacked core chips is less than four, T 4 HI and T 8 HI may be deactivated ( FIG. 10A ). When the number of stacked core chips is between 4 and 7, T 4 HI may be activated, and T 8 HI may be deactivated ( FIG. 10B ). When the number of stacked core chips is eight, T 4 HI and T 8 HI may be activated ( FIG. 10C ). 
         [0129]    According to an embodiment of the present invention, the base chip and the semiconductor package may adjust the number of signals for controlling refresh according to the number of core chips stacked over the base chip, and sequentially activate the signals, thereby minimizing the number of TSVs for transmitting the signals. 
         [0130]    Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and/or scope of the invention as defined in the following claims.