Abstract:
A hot-carrier injection (HCI) test that permits rapid screening of integrated circuit wafers susceptible to possible HCI-induced failures is disclosed. A method is described that determines transistor stress voltages that results in a transistor HCI-induced post-stress drain current differing from a pre-stress drain current within a desired range. These stress voltages are determined using a wafer with acceptable HCI susceptibility. Additional wafers to be tested are first tested using a described method that uses the determined transistor stress voltages to quickly screen the wafers for HCI susceptibility and, if HCI susceptibility is found, then additional conventional HCI testing may be applied to the susceptible wafers.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to integrated circuit testing, and, in particular, to hot-carrier injection testing of transistors in integrated circuit wafers or the like. 
       BACKGROUND 
       [0002]    As integrated circuit device features continue to shrink beyond 90 nm, the electrical characteristics of transistors with 90 nm and smaller gate lengths have become less than ideal. For example, leakage current and susceptibility to damage of transistor gate dielectric increases as the transistors get smaller. Further, merely using the integrated circuit results in the threshold voltage of the transistors (the voltage applied to the gate of a transistor at which the transistor begins to conduct) in the integrated circuit shifting (aging) that becomes more pronounced with smaller device dimensions. Unfortunately, the shift in threshold voltage is a significant factor in limiting the useful lifetime of an integrated circuit because the threshold voltage shift by the transistors eventually lead to the transistors possibly becoming unresponsive to signals applied to the gates thereof, leading to the functional failure of the integrated circuit. 
         [0003]    One significant contributor to transistor threshold voltage shift is damage to the transistor due to current injection. This phenomenon is known as hot-electron injection or hot-hole injection depending if the affected transistor is an n-channel or p-channel transistor, respectively, and is referred to generically as hot-carrier injection (HCI). 
         [0004]    HCI is a slow process during normal operation but the effect thereof is cumulative over the lifetime of the integrated circuit. Therefore, testing production integrated circuits while still in wafer form requires a technique to accelerate the effects of HCI over a relatively short time period, measuring transistor performance during the testing period, and then extrapolating from changes in the transistor performance to get a projection of the device lifetime. If the projected lifetime is less than a particular value, e.g., 15 years, the wafer is rejected for being overly susceptible to HCI. Various HCI testing techniques have been proposed and adopted, such as that described in “Procedure for Measuring N-Channel MOSFET Hot-Carrier-Induced Degradation Under DC Stress,” JESD28A, published December 2001 (along with corresponding JESD60A for p-channel transistors, published September 2004) by JEDEC Solid State Technology Association, Arlington, Va., USA, both of which are incorporated by reference herein in their entirety. However, the JEDEC test requires multiple hours to perform, an impractical test technique for testing each wafer on a production line. Instead, statistical sampling of selected wafers is used to project device lifetimes of entire production runs (production lots). This may lead to overly optimistic lifetime estimations (with resulting high field failures) or rejecting many wafers that are otherwise satisfactory absent additional, time consuming testing, both of which are costly. 
       SUMMARY 
       [0005]    In one embodiment, the present invention is a method of hot-carrier injection screening a wafer, the method comprising: providing a wafer having at least one MOSFET thereon, the MOSFET having at least a gate, a drain, and a threshold voltage; applying a gate test voltage to the gate and a drain test voltage to the drain of the MOSFET and measuring an initial current flow in the drain; applying, during a stress time period, a gate stress voltage to the gate and a drain stress voltage to the drain of the MOSFET; and applying, at a time subsequent to the stress time period, the gate test voltage to the gate and the drain test voltage to the drain of the MOSFET and measuring a test current flow in the drain. If the test current flow differs from the initial current flow by less than a first selected amount, the wafer passes the hot-carrier injection screen, and the drain test voltage is less than the threshold voltage. 
         [0006]    In another embodiment, the present invention comprises the steps of: selecting one wafer from the plurality of wafers, each wafer having a plurality of MOSFETs thereon and each of the MOSFETs having at least a gate, a drain, and a threshold voltage; selecting one of the plurality of MOSFETs on the selected wafer; applying a gate test voltage to the gate of the selected MOSFET and a drain test voltage to the drain of the selected MOSFET and measuring an initial current flow in the drain of the selected MOSFET; applying, during a stress time period, a gate stress voltage to the gate of the selected MOSFET and a drain stress voltage to the drain of the selected MOSFET; applying, at a time subsequent to the stress time period, the gate test voltage to the gate and the drain test voltage to the drain of the selected MOSFET and measuring a test current flow in the drain of the selected MOSFET; adjusting at least one of the gate and drain stress voltages if the test current flow differs from the initial current flow by less than a selected minimum amount or more than a selected maximum amount. The step of applying, during a stress time period, a gate stress voltage, the step of applying, during a stress time period, a gate stress voltage, and the step of adjusting at least one of the gate and drain stress voltages are repeated with another MOSFET selected from the plurality of MOSFETs until the test current flow differs from the initial current flow greater than the selected minimum amount and less than the selected maximum amount. Preferably, the selected wafer has MOSFETs with acceptable HCI susceptibility. Then at least one of the remaining wafers is hot-carrier injection screened using the stress voltages determined above. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    The aspects, features, and advantages of the present invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements. 
           [0008]      FIG. 1  is a simplified diagram of an exemplary testing apparatus for performing hot-carrier injection (HCI) screening of transistors on a wafer according to one embodiment of the invention; 
           [0009]      FIG. 2  is a simplified flowchart illustrating an exemplary HCI screening test utilizing the test apparatus of  FIG. 1 , according to another embodiment of the invention: 
           [0010]      FIG. 3  is a simplified flowchart illustrating an exemplary process to determine stress voltages for an HCI test utilizing the test apparatus of  FIG. 1  and as used in the HCI screening test of  FIG. 2 , according to another embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0011]    As is well understood in the art, wafers, such as silicon wafers with diameters of 150 mm or more, have formed therein many integrated circuits laid out across the wafer. Once the wafer is completely fabricated and before the integrated circuits therein are separated from each other (“singulated”), the wafer is subject to extensive testing to determine the functionality of each of the integrated circuits. Prior to the functionality testing, parametric testing of the wafer generally occurs to determine if the processing steps used to form the integrated circuits occurred correctly and within desired tolerances. When a new process is qualified, in addition to conventional parametric tests, the conventional HCI test as described above is done. 
         [0012]    To perform the HCI test, the wafer is placed in a probing station within a conventional testing apparatus (herein a “test set”). The test set, under control of processor, performs the various tests in sequence. A simplified schematic diagram of a conventional test set configured to perform testing of a wafer for hot-carrier injection (HCI) defects is shown in  FIG. 1 , in accordance with an exemplary embodiment of the invention. Here, an exemplary wafer  100  has a plurality of transistors  102   1 - 102   N , each capable of being probed from an exemplary external test set  104  (greatly simplified in this example). As is well understood in the art, test set  104  has probes (not shown) that are capable of contacting (probing) individual transistors on the wafer  100  for testing. The test set  104  has the equivalent of a double-pole, double-throw switch  106  under control of processor  108 . The switch  106  couples either conventional variable voltage sources V Gstress , V Dstress  or conventional variable voltage sources V Gtest , V Dtest  (in series with ammeter  110 ) to the gate and drain, respectively, to a selected one of the transistors  102   1 - 102   N  being tested, herein referred to as a transistor under test (TUT). For purposes here, transistor  102   1  is the TUT since it is shown being probed by tester  104 ; it is understood that any one of the transistors  102   1 - 102   N  may be the TUT. Along with the switch  106 , the four conventional variable voltage sources are also under the control of the processor  108 . Ammeter  110 , readable by the processor  108 , measures the drain current of the TUT when coupled by switch  106  to the TUT. It is understood that the voltage sources V Gstress  and V Dstress  may be combined. Further, switch  106  may be removed and two variable voltage sources, one coupled to the gate and one coupled to the drain of the TUT, may be used to supply both the stress and test voltages to the TUT. For purposes here, reference herein to a voltage source and the voltage it produces are used interchangeably, e.g., V Dstress  refers to both the variable voltage source V Dstress  and the voltage supplied thereby. 
         [0013]    As will be explained in more detail below in connection with  FIG. 2 , the switch  106  may be configured to apply variable voltage sources V Gstress  and V Dstress  to “stress” the TUT (e.g., transistor  102   1 ) with excessive gate and drain voltages, and is configured to apply variable voltage sources V Gtest , V Dtest  to test the TUT using voltages equal to or less than voltages which the transistors in the integrated circuit  100  are designed to be operated (hereinafter referred to as Vdd). Generally, Vdd is dependent on the process technology used to fabricate the wafer  100 ; for example, Vdd may be 1.8 volts for a 90 nm process technology, 1.2 volts for 65 nm process technology, etc. For HCI testing, the voltages from variable voltage sources V Gstress  and V Dstress  are generally significantly greater than Vdd and are applied to the TUT for an amount of time to result in a change in the DC operating characteristics of the TUT, as described in the above-referenced JEDEC test standard. Typically, the amount of time for the initial stress the TUT is about 10 seconds. Subsequent stress times (if subsequent TUT stress needed) typically increase geometrically. The voltages of the variable voltage sources V Gtest , V Dtest , V Gstress , and V Dstress  may be determined as described below in connection with  FIG. 3 . 
         [0014]    Referring to  FIG. 2 , an exemplary HCI screening test  200  utilizing the test set configuration of  FIG. 1 , according to another embodiment of the invention, is illustrated. By the judicious choice of stress and test voltages, a simple, fast HCI screening test can be done on an integrated circuit wafer to determine if the transistors thereon are not too susceptible to HCI without the need for a conventional, time consuming, HCI test. If, however, the screening indicates that the integrated circuit wafer might be susceptible to HCI, the wafer may then be subjected to the more definitive and conventional HCI testing, such as the JEDEC technique referred to above. 
         [0015]    Beginning with step  202 , one of the transistors  102   1 - 102   N  ( FIG. 1 ) is chosen to be the TUT (in this example, transistor  102   1  is the TUT) and is probed by the test set  104 . It is understood that this TUT has not been previously stressed. In step  204 , the nominal drain current (Id 0 ) of the TUT is measured by ammeter  108  for a gate voltage (V Gtest ) of Vdd (the nominal operating or design voltage of the transistors  102   1 - 102   N ) and a drain voltage (V Dtest ) of, in this example, approximately 0.1 volts. The drain voltage V Dtest  is preferably less than a nominal threshold voltage of the transistors  102   1 - 102   N . It has been discovered that performing the HCI drain current test step  204  using a very low drain voltages has the advantage of enhancing the effects of stress on the TUT and a drain voltage of approximately 0.1 volts has been found to be low enough for 45 nm gate length transistors to give good results without the drain current having so much noise that the test becomes unreliable. It is understood that the drain voltage may be less than 0.1 volts as device geometries get smaller, or greater than 0.1 volts as may be required. 
         [0016]    Next, in step  206 , the TUT is stressed for a nominal 10 seconds by applying approximately equal gate and drain voltages that exceed Vdd. Generally, the TUT is most stressed when the gate voltage (V Gstress ) and drain voltage (V Dstress ) is the same and significantly exceed Vdd, but it is understood that the gate and drain voltages may be different. As will be discussed in more detail below in connection with  FIG. 3 , the desired V Gstress  and V Dstress  voltages may be determined to achieve a desired amount of stress effect in the TUT, the TUT not being significantly susceptible to HCI. Here, V Gstress  and V Dstress  are greater than Vdd and, and in this example, about 1.5 Vdd. Other time periods may be used instead of 10 seconds but this time interval makes it possible to use this technique in an HCI screening application on many transistors without a prohibitively long test time while being sufficiently long to result in measurable shifts in the electrical characteristics of the TUT with the voltages given above. 
         [0017]    In step  208 , the drain current (Id 10 ) of the TUT post-stress is measured using the same gate and drain voltages as used in step  204 . The change in drain current is determined and normalized (ΔId) in step  210  and, in step  212 , the results compared to a drain current change threshold, Ith, to determine if the change in drain current post-stress is so high that further HCI testing is needed (step  214 ) or the wafer passes HCI screening in step  216  and the wafer undergoes further parametric and functional testing. The threshold current change Ith is, in this example, approximately 4% but can be another amount depending on the desired lifetime of the wafer  100  and the level of stress applied in step  206 , as is well known in the art. 
         [0018]    The additional HCI testing in step  214  may be similar to that disclosed in the JEDEC documents referred to above. This additional, conventional HCI testing generally comprises repeating the stress and test steps ( 206 - 210 ) for successively longer stress time periods until an accumulated stress time is met or exceeded or the drain current Id 10  differs from the initial current flow Id 0  by greater than a selected amount, e.g., 10%. Advantageously, the short HCI screening test  200  allows HCI testing of all wafers without the need for the time consuming conventional HCI testing unless the screening test indicates otherwise. 
         [0019]    The process steps  300  illustrated in  FIG. 3  may be used to determine the desired V Gstress  and V Dstress  voltages. In this embodiment and because all transistors have some amount of HCI susceptibility, the stress voltages are selected such that the change in drain current (ΔId), resulting from the application of the stress voltages, is within a desired range for a “nominal” transistor (i.e., a transistor without significant HCI susceptibility as determined by, for example, a wafer using conventional HCI test described above), here between 2% and 3%. It is understood that the range of 2% to 3% is only exemplary and other values may be used instead. Generally, the range values are chosen to be large enough that a consistently measurable value of current change occurs but is less than the drain current change threshold, Ith, as discussed above in connection with step  212 . 
         [0020]    Beginning with step  302 , an integer index value i (1≦i≦N), used in later steps, is initialized. In step  304 , a first transistor, such as transistor  102   1  in  FIG. 1 , is chosen as the TUT. It is understood that this TUT has not been previously stressed. Steps  306 ,  308 ,  310 , and  312  are the same as, and correspond to, the steps  204 ,  206 ,  208 , and  210 , as described above, but, in step  308 , the stress voltages V Gstress , V Dstress  are approximately 1.5 Vdd in this example, but other voltages may be used as well. In steps  314  and  316 , the normalized drain current change, ΔId, is checked to see if it is within the desired range, here between 2% and 3%. If ΔId is above or below the desired range as determined in steps  314  and  316 , the stress voltages are lowered or increased, respectively, in steps  318 - 332 . In more detail, in step  318 , the index i is incremented and a new, unstressed transistor is chosen as the TUT in step  320 , and the initial (pre-stress) drain current is measured for the new TUT in step  322 . Then the stress voltages are incrementally decreased in step  324  and the stress/test steps  310 - 314  are repeated but using different transistors (as selected in step  320 ) as the TUT until the ΔId is less than or equal to 3%. Similarly, in step  326 , the index i is incremented and a new, unstressed transistor is chosen as the TUT in step  328 , and the initial (pre-stress) drain current is measured for the new TUT in step  330 . Then the stress voltages are incrementally increased in step  332  and the stress/test steps  310 - 316  are repeated but using different transistors (as selected in step  328 ) as the TUT until the ΔId is more than or equal to 2%. If the ΔId is between 2% and 3% inclusive, then, in step  334 , the final (adjusted) stress voltages may then be used in the HCI screening test  200 , described above, or for the conventional HCI test described above. 
         [0021]    It is understood that while the stress voltages V Gstress  and V Dstress  are shown as having the same voltage in the embodiments described above, they may have different voltages. For example, the gate stress voltage, V Gstress , may be fixed at, for example, Vdd, while V Dstress  is adjusted in accordance with the process steps  300 . Further, the order of the steps may be changed and other steps added, as desired. 
         [0022]    It is understood that while the embodiment shown herein is for testing an integrated circuit, the invention may be used in any application where hot-carrier injection testing is needed or desired, e.g., in power transistors for power amplifiers, etc. 
         [0023]    For purposes of this description and unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value of the value or range. Further, signals and corresponding nodes, ports, inputs, or outputs may be referred to by the same name and are interchangeable. Additionally, reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the terms “implementation” and “example.” 
         [0024]    Also for purposes of this description, the terms “couple,” “coupling,” “coupled,” “connect,” “connecting,” or “connected,” refer to any manner known in the art or later developed in which a signal is allowed to be transferred between two or more elements and the interposition of one or more additional elements is contemplated, although not required. Conversely, the terms “directly coupled,” “directly connected,” etc., imply the absence of such additional elements. 
         [0025]    It is understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this invention may be made by those skilled in the art without departing from the scope of the invention as expressed in the following claims. 
         [0026]    The use of figure numbers and/or figure reference labels in the claims is intended to identify one or more possible embodiments of the claimed subject matter in order to facilitate the interpretation of the claims. Such use is not to be construed as necessarily limiting the scope of those claims to the embodiments shown in the corresponding figures. 
         [0027]    Although the elements in the following method claims, if any, are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.