Abstract:
This description relates to a method for fabricating a magnetoresistive random access memory (MRAM) device having a plurality of magnetic tunnel junction (MTJ) units. The method includes forming a bottom conductive layer, forming an anti-ferromagnetic layer and forming a tunnel layer over the bottom conductive layer and the anti-ferromagnetic layer. The method further includes forming a free magnetic layer, having a magnetic moment aligned in a direction that is adjustable by applying an electromagnetic field, over the tunnel layer and forming a top conductive layer over the free magnetic layer. The method further includes performing at least one lithographic process to remove portions of the bottom conductive layer, the anti-ferromagnetic layer, the tunnel layer, the free magnetic layer and the top conductive layer that is uncovered by the photoresist layer until the bottom conductive layer is exposed and removing portions of at least one sidewall of the MTJ unit.

Description:
BACKGROUND 
       [0001]    The present disclosure relates generally to magnetoresistive random access memory (MRAM), and more particularly to MRAM cells having magnetic tunnel junction (MTJ) units with continuous tunnel layers. 
         [0002]    MRAM is a type of memory device containing an array of MRAM cells that store data using resistance values instead of electronic charges. Each MRAM cell includes a magnetic tunnel junction (MTJ) unit whose resistance can be adjusted to represent a logic state “0” or “1.” MTJ is a critical component of an MRAM device and the formation of an MTJ is important to any MRAM product. 
         [0003]    Conventionally, the MTJ unit is comprised of a fixed magnetic layer, a free magnetic layer, and a tunnel layer disposed there between. The resistance of the MTJ unit can be adjusted by changing a direction of a magnetic moment of the free magnetic layer with respect to that of the fixed magnetic layer. When the magnetic moment of the free magnetic layer is parallel to that of the fixed magnetic layer, the resistance of the MTJ unit is low, whereas when the magnetic moment of the free magnetic layer is anti-parallel to that of the fixed magnetic layer, the resistance of the MTJ unit is high. The MTJ unit is coupled between top and bottom electrodes, and an electric current flowing through the MTJ from one electrode to another can be detected to determine the resistance, and therefore the logic state of the MTJ. 
         [0004]      FIG. 1  is a cross-sectional view of a typical MRAM cell  100  comprised of a MTJ unit  102  coupled to a bit line  104  through a top electrode  106 , and to a source/drain doped region  108  of a MOS device  116  through a bottom electrode  110  and a contact  112 . A write line  114  is located underneath the MTJ unit  102  for generating an electromagnetic field to change the resistance of the MTJ unit  102  during a write operation. During a read operation, the MOS device  116  is selected to pass a current through the bit line  104 , the top electrode  106 , the MTJ unit  102 , the bottom electrode  110 , and the contact  112  to a source/drain doped region  118 . A current detected at the bit line  104  is compared with a reference to determine whether the resistance of the MTJ unit  102  represents a high or low state. Because MRAM does not utilize electric charges for data storage, MRAM consumes less power and suffers less from current leakage than other types of memory, such as static random access memory (SRAM), dynamic random access memory (DRAM) and flash memory. 
         [0005]      FIGS. 2-4  are cross-sectional views of a MTJ unit during a fabrication process. Referring to  FIG. 2 , a stack of a bottom conductive layer  202 , an anti-ferromagnetic layer  204 , a pinned layer  206 , a tunnel layer  208 , a free magnetic layer  210  and a top conductive layer  212  is formed above a semiconductor substrate (not shown in the figure). The anti-ferromagnetic layer  204  fixes a magnetic moment of the pinned layer  206  in one direction, a magnetic moment of the free magnetic layer  210  can be changed by applying external electromagnetic forces. A photoresistor layer  214  is formed on the top conductive layer  212  to define a width of the MTJ unit being fabricated. 
         [0006]    An etching processing using the photoresistor layer  214  as a mask is performed to remove parts of the top conductive layer  212  not covered by the photoresistor layer  214 . The photoresistor layer  214  is then stripped after the etching process reaches a top surface of the free magnetic layer  210 , resulting in a structure as depicted in  FIG. 3 . 
         [0007]    Another etching process, preferably dry etching, is performed using the top conductive layer  212  as a hard mask to remove portions of the free magnetic layer  210 , the tunnel layer  208 , the pinned layer  206  and the anti-ferromagnetic layer  204  not covered by the top conductive layer  212  in order to separate a MTJ unit from its neighboring units. The etching process stops when at a top surface of the bottom conductive layer  202 , resulting in a structure as depicted in  FIG. 4 . 
         [0008]    One drawback of the conventional etching process used in forming the MTJ unit is that the MTJ unit is susceptible to a short circuit reliability issue. The etching process is often performed in a chamber where plasma is introduced to bombard a surface of the MTJ unit being fabricated. As a result, there may be residual conductive materials remaining on sidewalls of the completed MTJ unit as depicted in  FIG. 4 . These residual conductive materials may conduct a current between the bottom conductive layer  202  and the top conductive layer  212  bypassing the tunnel layer  208 , thereby causing the MTJ unit to fail. 
         [0009]    Another drawback of the conventional etching process used in forming the MTJ unit is that the top conductive layer  212  and the photoresistor layer  214  are thick. The MTJ unit is relatively deep for purposes of etching as it is comprised of layers including the free magnetic layer  210 , the tunnel layer  208 , the pinned layer  206 , and the anti-ferromagnetic layer  204 . Because the top conductive layer  212  acts as a hard mask the top conductive layer  212  is consumed during the etching process. The top conductive layer  212  is sufficiently thick to ensure that enough of the top conductive layer  212  will remain on the free magnetic layer  210  after the etching. Likewise, the photoresistor layer  214  is sufficiently thick to ensure that enough of the photoresistor layer  214  will remain on the top conductive layer  212  after etching. This poses a challenge to MRAM fabrication, especially when MRAM continues to shrink in size beyond 45 nm of conductor width. 
         [0010]    Yet another drawback of the conventional etching process in forming the MTJ unit is that the top surface of the top conductive layer  212  may become rounded by the etching, thereby increasing the difficulty of forming a contact thereon. During the etching process, the corners of the top conductive layer  212  are etched faster than other parts. As a result, properly forming a contact on the conductive layer  212  is more difficult, and thus increases reliability issues. 
         [0011]    As such, what is needed is a method of fabricating MRAM that addresses the short circuit and mask thickness issues present in the conventional process. 
       SUMMARY 
       [0012]    The present disclosure is directed to MRAM technology. One embodiment includes a method for fabricating a magnetoresistive random access memory (MRAM) device having a plurality of memory cells. The method includes forming a fixed magnetic layer having magnetic moments fixed in a predetermined direction; forming a tunnel layer over the fixed magnetic layer; forming a free magnetic layer, having magnetic moments aligned in a direction that is adjustable by applying an electromagnetic field, over the tunnel layer; forming a hard mask on the free magnetic layer partially covering the free magnetic layer; and unmagnetizing portions of the free magnetic layer uncovered by the hard mask for defining one or more magnetic tunnel junction (MTJ) units. 
         [0013]    The construction and method of operation together with additional objectives and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]      FIG. 1  is a cross-sectional view of a typical MRAM cell. 
           [0015]      FIGS. 2-4  are cross-sectional views of a MTJ unit during a conventional fabrication process. 
           [0016]      FIGS. 5-7  are cross-sectional views of a MTJ unit during a fabrication process in accordance with at least one embodiment. 
           [0017]      FIG. 8  and  FIG. 9  are cross-sectional views of two neighboring MRAM cells fabricated in accordance with at least one embodiment. 
       
    
    
     DESCRIPTION 
       [0018]    This disclosure is directed to a method of fabricating a MRAM device. The following merely illustrates various embodiments of the present invention for purposes of explaining the principles thereof. It is understood that those skilled in the art will be able to devise various equivalents that, although not explicitly described herein, embody the principles of this invention. 
         [0019]      FIGS. 5-7  are cross-sectional views of a MTJ unit during a fabrication process of a MRAM device in accordance with at least one embodiment. Referring to  FIG. 5 , a stack of a bottom conductive layer  402 , an anti-ferromagnetic layer  404 , a pinned layer  406 , a tunnel layer  408 , a free magnetic layer  410  and a top conductive layer  412  is formed above a semiconductor substrate (not shown in the figure). The anti-ferromagnetic layer  404  fixes a magnetic moment of the pinned layer  406  in one direction, whereas a magnetic moment of the free magnetic layer  410  can be changed by applying external electromagnetic forces. A photoresistor layer  414  is formed on the top conductive layer  412  to define a width of the MTJ unit. 
         [0020]    The stack of bottom conductive layer  402 , anti-ferromagnetic layer  404 , pinned layer  406 , tunnel layer  408 , free magnetic layer  410  and top conductive layer  412  can be formed by semiconductor processing technology such as chemical vapor deposition (CVD); plasma enhanced chemical vapor deposition (PECVD), sputtering, or electroplating. The top and bottom conductive layers  412  and  402  contain materials, such as tantalum, aluminum, copper, titanium, tungsten, TiN, or TaN. The tunnel layer contains, for example, Al 2 O 3 , MgO, TaOx, or HfO. The photoresistor layer  414  can be formed by photolithography including photoresistor coating, exposing, baking, and developing. 
         [0021]    A reactive ion etching is performed using carbon tetrafluoride as reactants to remove portions of the top conductive layer  412  not covered by the photoresistor layer  414  until the free magnetic layer  410  underlying the top conductive layer  412  is exposed. The photoresistor layer  414  is then removed resulting in a structure as depicted in  FIG. 6 . Thereafter, another etching process is conducted, using the top conductive layer  412  as a hard mask, to remove portions of the free magnetic layer  410 , the tunnel layer  408 , the pinned layer  406 , the anti-ferromagnteic layer  404 , until the bottom conductive layer  402  is exposed. This second etching process forms an MTJ unit that is depicted in  FIG. 7 . 
         [0022]    Referring to  FIG. 8 , a sidewall-removal process is performed to remove portions of sidewalls of the MTJ unit between the top conductive layer  412  and the bottom conductive layer  402 . The removal of the MTJ sidewalls can be done using a dry etching process, such as a plasma etching process. The removal of the MTJ sidewalls can also be done using a wet etching method. 
         [0023]    Various dry etching processes involving the use of gaseous plasmas are known. In at least one embodiment, for example, the MTJ unit is dry etched by using plasma containing a gas comprising fluorine. In at least one embodiment, the plasma etching uses a gas mixture comprising sulfur hexafluoride (SF6), oxygen (O 2 ) m  and trifluoromethane (CHF3). A similar gas mixture containing these three reactant gases has been used for etching polysilicon in a decoupled plasma source (DPS) reactor, manufactured by Applied Materials, Inc., of Santa Clara, Calif. The plasma gas in at least one embodiment comprises a gas mixture of fluoride (such as CFHx, SFx), Argon, alcohol (such as methanol), nitrogen, hydrogen, and oxygen. In at least one embodiment, the Argon gas flow rates for the main etch step is between 20 to 100 sccm. A suitable radio frequency with a power of about between 100 to 500 W is applied. The plasma chamber pressure is maintained at approximately 3 to 20 mTorr. In at least one embodiment, the nitrogen gas flow rate is between 50 to 200 sccm; the power is set at between 300 to 3000 W, and the plasma chamber pressure is maintained at approximately 2 to 30 mTorr. 
         [0024]    In addition to plasma etching, other dry etching methods can be used as well. For example, ion beam etching is another dry etching option that can be used to remove MTJ sidewalls. One such method, known as ion milling, is described here as an example. Wafers are placed on a holder in a vacuum chamber and a stream of argon gas is introduced into the chamber. Upon entering the chamber, the argon is subjected to a stream of high-energy electrons from a set of cathode and anode electrodes. The electrons ionize the argon atoms to a high-energy state having a positive charge. The wafers are held on a negatively biased holder that attracts the positive argon ions. As the argon ions travel to the wafer holder the argon ions accelerate, picking up energy. At the wafer surface the argon ions crash into the exposed wafer layer and remove small amounts of material from a wafer surface. During this process, no chemical reaction occurs between the argon ions and the wafer material. Material removal (etching) using ion milling is highly directional. 
         [0025]    In addition to dry etching, the MTJ sidewall material can also be removed by using a wet etching process. In some embodiments, inorganic cleaning solutions, such as HF, APM, SPM, HNO3 or acetic acid can be used as wet etchants. For example a concentration of a wet etchant chemical, such as HF, can be from about 0.02% to about 1%. And an operating temperature for the wet etching process can be from 20 to 60 Celsius. The wet etching process can also be conducing as a solvent cleaning solution. In at least one embodiment, the solvent cleaning solution comprises of a mixture of a surfactant, a chelating agent, an inhibitor and water. 
         [0026]      FIG. 8  depicts the resultant MTJ unit after a portion of the sidewalls has been removed by the etching processes described above. As  FIG. 8  depicts, after the damaged portion of the MTJ sidewall has been removed, the diameter of the portion of the MTJ unit below the top conductive layer  412  is smaller than the diameter of the conductive layer  412 . 
         [0027]      FIG. 9  is a cross-sectional view of the MTJ unit after a capping later 413 is placed encapsulating the MTJ unit. In at least one embodiment, the capping layer  413  is made of NiFeHf and has a thickness from about 15 to 50 Angstroms. In some embodiments, the capping layer has a thickness of 45 Angstroms. By employing the capping layer  413  comprised of a NiFeHf layer that contacts the conductive layer  412 , the conductive layer  412  is less oxygen contaminated and has higher conductivity, thereby improving micro-electromechanical system (MEMS) resistance ratio ΔR/R. The oxygen gettering capability of NiFeHf is achieved because Hf has a higher oxidation potential than Ni and Fe in the top conductive layer  412 . Another benefit of a NiFeHf capping layer  413  is that a “dead layer” between the top conductive layer  412  and the capping layer  413  is substantially eliminated. The “dead layer” is a 3 to 6 Angstrom thick interface between the top conductive layer  412  and the capping layer  413  wherein some intermixing of layers has occurred. For example, in conventional Ru or Ta capping layers, Ru and Ta may migrate into a NiFe free layer and thereby reduce the magnetic moment of the free layer and dR/R of the MTJ. The “dead layer” is indicative of poor lattice matching between the free layer and adjoining the capping layer. By reducing the dead layer and thereby increasing the effective volume of the free layer, the NiFeHf layer promotes a more thermally stable device since volume of the free layer is directly related to the thermal stability factor. In at least one embodiment, the capping layer  413  can be made from other NiFeM materials, where M is a metal such as Zr or Nb that has an oxidation potential greater tan that of Ni and Fe. 
         [0028]    In at least one embodiment, the capping layer  413  may be a composite layer having a NiFeHf layer that contacts the NiFe free layer, and one or more other layers formed on the NiFeHf layer. In at least one embodiment, the capping layer  413  may have a NiFeHf/Ta configuration. Optionally, the capping layer  413  may have a configuration represented by NiFeHf/Ta/Ru. In at least one embodiment, a thickness of the Ta layer may vary from 10 to 50 Angstroms, and a thickness of the Ru layer may vary from 30 to 100 Angstroms. Optionally, other elements such as Zr or Nb that have a higher oxidation potential than Ni and Fe may be incorporated in a NiFeM/Ta capping layer configuration. 
         [0029]    After all of the MTJ layers have been formed, a hard mask having a thickness of from 400 to 600 Angstroms is deposited on the capping layer  413  in the same sputter deposition tool. In some embodiments, the hard mask has a thickness of 500 Angstroms. In at least one embodiment, a Ta hard mask is formed on the NiFeHf capping layer  413 . 
         [0030]    One advantage of the method for fabricating the MRAM devices is that the reliability of the memory structure resulted from such method can be improved as opposed to the structure made by the conventional manufacturing process. As discussed above, the method eliminates the etching process during the construction of MTJ units, and therefore avoids the material residue problem that is often seen on the sidewalls of the MTJ units made by conventional methods. This eliminates the short circuit problems for MTJ units, and therefore improves the reliability of the MRAM devices. 
         [0031]    The above disclosure provides many different embodiments or embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims. 
         [0032]    Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.