Abstract:
The present invention discloses a mute circuit of an audio device for suppressing audio signals during the transients of power switching. A mute circuit for an amplifier having at least an audio output terminal includes at least one bypass device, each of which has a controlling terminal and is capable of providing a path from the audio output terminal to a ground when the controlling terminal is turned on; a power-on controlling circuit for turning on the controlling terminal of the bypass device during a first period of time after a power-on transient; a fixed-voltage supply for stopping the amplifier during the power-on transient according to a control of a controlling terminal of an input/output port; and a power-off controlling circuit for turning on the controlling terminal of the bypass device by utilizing a voltage of a capacitor during a second period of time after a power-off transient.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a controlling circuit for an audio signal, and more particularly, to a mute circuit for suppressing audio signals during power switching.  
         [0003]     2. Description of the Prior Art  
         [0004]      FIG. 1  is a diagram of a prior art audio signal circuit in an audio device. An audio device  10  (such as a player) contains a core processor, the microprocessor  12 , for receiving many types of audio-video data  20 , and for transmitting the audio data  22 , portion of the audio-video data  20 , to the audio chip  14  and the video data portion of the audio-video data  20  to the video chip (not shown).  
         [0005]     The audio chip  14  divides the audio data  22  into at least a left channel signal L′ and a right channel signal R′, and sometimes into more channel signals. These signals are sent to the pre-amplifier  16  to be amplified, which then further sends these signals outside the device  10  to the post-amplifier and the speakers (not shown).  
         [0006]     A problem in the available players and stereos has not been solved completely for a long time—a transient noise occurs during power switching. During the transient when the power switches on or off, there are inevitable noises attached to the audio signals since the power supply is not in a steady state. When these audio signals are amplified and sent out by the speakers, there will be annoying sounds.  
         [0007]     Although there are chips for suppressing the noises, which occur during power switching to solve the above-mentioned problem, using these kinds of chips increases the costs of the players, and these kinds of chips do not erase the noises completely, instead merely suppressing the noises.  
       SUMMARY OF THE INVENTION  
       [0008]     It is therefore one of the objectives of the present invention to provide a mute circuit for audio devices. During the transient of switching on or off, the audio signals are bypassed to the ground to avoid transmitting them to the post-amplifier.  
         [0009]     According to one preferred embodiment of the present invention, a mute circuit for an amplifier having at least an audio output terminal is disclosed. The mute circuit includes: at least one bypass device, each of which has a controlling terminal, such that when the controlling terminal is turned on, the bypass device provides a path from the audio output terminal to a ground; a power-on controlling circuit for turning on the controlling terminal of the bypass device during a first period of time after a power-on transient; a fixed-voltage supply for stopping the amplifier during the power-on transient according to a control of a controlling terminal of an input/output port; and a power-off controlling circuit for turning on the controlling terminal of the bypass device during a second period of time by using a voltage of a capacitor after a power-off transient.  
         [0010]     It is one advantage of the present invention that a mute circuit is provided to eliminate noise occurring during a power-on or power-off transient. As a result, there will be no spurious noises sent out by the speakers when the audio device is turned on or off.  
         [0011]     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]      FIG. 1  is a diagram of a prior art audio signal circuit in an audio device.  
         [0013]      FIG. 2  is a mute circuit according to the present invention.  
         [0014]      FIG. 3  is a diagram of a voltage stabilizer shown in  FIG. 2 .  
         [0015]      FIG. 4  is a diagram of a charge/discharge circuit shown in  FIG. 2 . 
     
    
     DETAILED DESCRIPTION  
       [0016]      FIG. 2  shows a mute circuit for an audio device of the present invention. An audio device  30  contains a core processor, the microprocessor  32 , which receives audio-video data  20  of many specifications, and transmits the audio data  22 , portion of the audio-video data  20 , to an audio chip  34  and the video data portion of the audio video data  20  to a video chip (not shown).  
         [0017]     The audio chip  34  divides the audio data  22  into at least the left channel signal L′ and the right channel signal R′, and sometimes into more channel signals. These signals are sent to the pre-amplifier  36  to be amplified, which subsequently sends them to the post-amplifier and the speakers (not shown).  
         [0018]     According to one preferred embodiment of the present invention, two bypass transistors B 1  and B 2  are respectively coupled to the left channel output and right channel output of the pre-amplifier  36 . The two bypass transistors B 1  and B 2  are NPN bipolar junction transistors on which the collectors are coupled to the outputs of the pre-amplifier  36 , the emitters are coupled to the ground, and the bases are used to switch the states of the bypass transistors B 1  and B 2  between on and off.  
         [0019]     A power-on controlling circuit  50  is used to switch the bypass transistors B 1  and B 2  to an on state and then an off state when the power switches on. The power-on controlling circuit  50  contains a reset circuit  52  and a first switch transistor T 1  used as a switch. The reset circuit  52  is connected to a 5-volt power supply voltage to monitor the changes of the 5-volt power supply voltage when the audio device is turned on. The reset circuit  52  sends out a low level signal when the output of the 5-volt power supply voltage is lower than 4.38 volts, and sends out a high level signal when the output of the 5-volt power supply voltage is higher than 4.38 volts. The first switch transistor T 1  is a PNP bipolar junction transistor on which the emitter is coupled to the power supply, the base is coupled to the output of the reset circuit  52  through a first resistor R 1 , and the collector is coupled to the positive terminal of a Schottky diode D 1 . The negative terminal of the Schottky diode D 1  is coupled to the bases of the bypass transistors B 1  and B 2  through a second resistor R 2 .  
         [0020]     A fixed-voltage supply  60  is used for powering the pre-amplifier  36 . The fixed-voltage supply  60  receives a 12-volt power supply voltage and transmits it to a voltage stabilizer  64  through a second switch transistor T 2 . The voltage stabilizer  64  receives a 12-volt power supply voltage and then outputs a voltage of 10 volts to power the pre-amplifier  36 . The second switch transistor T 2  is a PMOS transistor on which the source is coupled to the 12-volt power supply voltage, the gate is coupled to the 12-volt power supply voltage through a third resistor R 3 , and the drain is coupled to the voltage stabilizer  64 .  
         [0021]     The on and off of the second switch transistor T 2  are controlled by a controlling terminal of an I/O (input-output) port of the microprocessor  32 . The controlling terminal of an I/O port can be any I/O port of the microprocessor  32 , which is normally at a low level. The controlling terminal of the I/O port is coupled to the gate of a pull down transistor M 1 , which is an NMOS transistor on which the drain is coupled to the gate of the second switch transistor T 2  and the source is coupled to the ground.  
         [0022]     A power-off controlling circuit  80  contains a fourth resistor R 4  connected between the drain of the pull down transistor M 1  and the base of a third switch transistor T 3 . The third switch transistor T 3  is a PNP bipolar transistor, on which the emitter is coupled to the 12-volt power supply voltage, and the collector is coupled to a charge/discharge circuit  83 . The charge/discharge circuit  83  outputs a high voltage when the third switch transistor T 3  switches on, and outputs a low voltage when the third switch transistor T 3  switches off. In addition, there is a second Schottky diode D 2  on which the positive terminal is coupled to the 12-volt power supply voltage, and the negative terminal is coupled to the ground through a first capacitor C 1 . The fourth switch transistor T 4  is a PMOS transistor on which the gate is coupled to the output of the charge/discharge circuit  83 , the source is coupled to the negative terminal of the first Schottky diode D 1 , and the drain is coupled to the bases of the bypass transistors B 1  and B 2  through a fifth resistor R 5 .  
         [0023]      FIG. 3  is a diagram of the voltage stabilizer  64  shown in  FIG. 2 . The voltage stabilizer  64  contains an inductor L, one terminal of which is coupled to the drain of the second switch transistor T 2 ; the second capacitor C 2  and the third capacitor C 3 , which are connected in parallel, couple the other terminal of the inductor L to the ground. The sixth, seventh, and eighth resistors R 6 , R 7  and R 8 , which are connected in serial, are connected in parallel with the third capacitor C 3 . The positive terminal of the shunt regulator SR is coupled to the ground, the negative terminal is coupled to the node between the sixth and the seventh resistors R 6  and R 7 , and the reference terminal is coupled to the node between the seventh and the eighth transistors R 7  and R 8 . As a result, when the second switch transistor T 2  switches on, by the action of the shunt regulator SR and the voltage division of the sixth, seventh and eighth resistors R 6 , R 7  and R 8 , the node between the sixth and the seventh resistors R 6  and R 7  provides a steady voltage of 10 volts.  
         [0024]      FIG. 4  is a diagram of the charge/discharge circuit  83  shown in  FIG. 2 . A ninth resistor R 9  is connected between the collector of the third switch transistor T 3  and the ground. The series of the tenth resistor R 10  and the fourth capacitor C 4  is connected in parallel with the ninth resistor R 9 . The negative terminal of the third Schottky diode D 3  is coupled to the node between the ninth and the tenth resistors R 9  and R 10 , and the positive terminal, which is also the output terminal of the charge/discharge circuit  83 , is coupled to the node between the tenth resistor R 10  and the fourth capacitor C 4 . When the third switch transistor T 3  switches on, the tenth resistor R 10  along with the fourth capacitor C 4  form an RC charging circuit, and the fourth capacitor C 4  receives a 12-volt power supply voltage when the RC charging circuit is in the steady state. At this time, the output terminal of the charge/discharge circuit  83  is high. Similarly, when the third switch transistor T 3  switches off, the charge on the fourth capacitor C 4  is dissipated rapidly through the third Schottky diode D 3  and the ninth resistor R 9 . At this time, the output terminal of the charge/discharge circuit  83  is low.  
         [0025]     According to the present invention, the mute circuit behaves as follows when the power switches on, during normal operation, and when the power switches off.  
       EXAMPLE 1  
     During the Transient when the Audio Device is Powered on  
       [0026]     Because the controlling terminal of the I/O port is normally low, the pull down transistor M 1  turns off and hence the gate of the second switch transistor T 2  is connected to the 12-volt power supply voltage. As a result, the second switch transistor T 2  also turns off so that the voltage stabilizer  64  cannot be powered by 12-volt power supply voltage, and therefore, the pre-amplifier  36  receives no power. Consequently, the pre-amplifier  36  will output no sound during the transient when the power switches on.  
         [0027]     It is also important to avoid the situation where the pre-amplifier  36  still outputs noise after the audio device is powered on. When the 5-volt power supply voltage changes from 0 to 4.38 volts (the first period of time), because the 5-volt power supply voltage in the power-on controlling circuit  50  is not stable during the transient when the audio device is powered on, the reset circuit  52  sends a low level signal to the first switch transistor T 1  to turn on the first switch transistor T 1 . That is, the controlling terminals of the bypass transistors B 1  and B 2  receive an increasing voltage, so the bypass transistors B 1  and B 2  turn on, conducting all signals from the audio output terminal of the pre-amplifier  36  to the ground. As a result, during the transient when the audio device is powered on, by not powering the pre-amplifier  36  and conducting all signals from the audio output terminal of the pre-amplifier  36  to the ground, all signals are blocked from being sent to the post-amplifier (not shown).  
         [0028]     When the output of the 5-volt power supply voltage exceeds 4.38 volts, the reset circuit  52  sends a high level signal to the first switch transistor T 1  to turn off the first switch transistor T 1  so that the bypass transistors B 1  and B 2  turn off as well. As a result, all signals from the audio output terminal of the pre-amplifier  36  are sent to the post-amplifier (not shown).  
       EXAMPLE 2  
     When the Audio Device  30  is Running  
       [0029]     The controlling terminal of the I/O port sends a high level signal to turn on the pull down transistor M 1 —coupling the gate of the second switch transistor T 2  to the ground. As a result, the second switch transistor T 2  also turns on so that the 12-volt power supply voltage will power the voltage stabilizer  64 , and consequently the pre-amplifier  36  will operate.  
         [0030]     Moreover, because the pull down transistor M 1  is turned on, the third switch transistor T 3  is also turned on. As a result, the charge/discharge circuit  83  sends out a high level signal to turn off the fourth switch transistor T 4 . As a result, when the audio device is running, the bypass transistors B 1  and B 2  are off, and the first capacitor C 1  is charged to 12 volts through the second Schottky diode D 2 .  
       EXAMPLE 3  
     During the Transient When the Audio Device is Powered Off  
       [0031]     The third switch transistor T 3  is turned off, the charge/discharge circuit  83  sends out a low level signal to turn on the fourth switch transistor T 4 , and the bypass transistors B 1  and B 2  are turned on by the voltage of the first capacitor C 1 . Before the charge of the first capacitor C 1  vanishes (the second period of time), i.e., when the bypass transistors B 1  and B 2  are still on, all signals from the audio output terminal of the pre-amplifier  36  are coupled to the ground. As a result, during the transient when the audio device is powered off, all signals on the audio output terminal of the pre-amplifier  36  are blocked from being sent to the post-amplifier (not shown).  
         [0032]     In summary, in the present invention, the power-on controlling circuit  50  turns on the bypass transistors B 1  and B 2  during the transient when the audio device is powered on, so the audio signals are coupled to the ground through the bypass path. This prevents the spurious noises generated by the pre-amplifier  36  from being sent to the post-amplifier. Moreover, right after the audio device  30  is powered on, the fixed-voltage supply  60  uses the controlling terminal of the I/O port to stop powering the pre-amplifier  36  in order to eliminate the noises. Finally, during the transient when the audio device is powered off, the power-off controlling circuit  80  turns on the bypass transistors B 1  and B 2  when the fourth switch transistor T 4  is turned on, using the voltage of the first capacitor C 1 . This prevents the spurious noises generated by the pre-amplifier  36  from being sent to the post-amplifier.  
         [0033]     In conclusion, the present invention provides a mute circuit for coupling the signals from the audio output terminals of the pre-amplifier to the ground to prevent them from being sent to the post-amplifier during the transients when an audio device is powered on or off.  
         [0034]     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.