Abstract:
A liquid crystal display is capable of displaying intermediate, partial or half tones of images, while at the same time preventing the occurrence of flicker and the decay of the liquid crystal panel. The display operation for data to be displayed in an intermediate tone has one or more lines of a repeating frame of display data that are prohibited from being displayed during in each frame. Such inhibited display lines are designated differently on a sequential basis over consecutive frames, and the sequence of designation is varied in successive frames in accord with changing patterns.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a method and an apparatus for liquid crystal display capable of displaying intermediate tones partial tones or half tones of images. 
     A known method for displaying an intermediate tone that is less than a normal or full tone of an image on a liquid crystal display panel employs a fast blinking operation as disclosed, for example, in JP-A-58-57192. This conventional technique will first be described using FIGS. 7 through 10. 
     FIG. 7 shows in block diagram the conventional liquid crystal display apparatus, which includes a display address generating circuit 1, memories 2 and 3, a switching signal generating circuit 4, a memory switching circuit 5, a display data forming circuit 6, and a liquid crystal display panel 7. 
     In the arrangement, a display address 8 issued by the display address generating circuit 1 is received by the memory 2 and memory 3 simultaneously, and the memories 2 and 3 read out character codes. The switching signal generating circuit 4 provides a switching signal to the memory switching circuit 5, and when the signal is &#34;high&#34;, a character code read out of the memory 2 is fed to the display data forming circuit 6 by way of the memory switching circuit 5, while when the switching signal is &#34;low&#34;, a character code read out of the memory 3 is fed through the memory switching circuit 5 to the display data forming circuit 6. The switching signal alternates its binary levels in every display period for consecutive frames on the liquid crystal display panel 7, so that when the memory 2 is selected by the memory switching circuit 5 to supply its contents to the display data forming circuit 6 at the time of displaying the first frame, the memory 3 is selected next at the time of displaying the second frame. The display data forming circuit 6 forms a supplied character code into a character pattern and delivers it as a display data 9 to the liquid crystal panel 7. 
     Supposing characters &#34;A&#34;, &#34;B&#34; and &#34;C&#34; are displayed on the liquid crystal panel 7 with the character &#34;B&#34; being displayed in an intermediate tone, the memory 2 stores codes A, B and C representing characters &#34;A&#34;, &#34;B&#34; and &#34;C&#34;, whereas the memory 3 stores only character codes A and C. On this account, when the memory switching circuit 5 selects the memories 2 and 3 alternately, the characters &#34;A&#34;, &#34;B&#34; and &#34;C&#34; are displayed in the first frame as shown in FIG. 9A, while only characters &#34;A&#34; and &#34;C&#34; are displayed in the second frame as shown in FIG. 9B. Accordingly, the characters &#34;A&#34; and &#34;C&#34; are displayed in every frame, while the character &#34;B&#34; is displayed in every two frame, resulting in an intermediate tone for the character &#34;B&#34; as shown in FIG. 9C. However, when the display apparatus operates at a typical frame frequency of 60 Hz, the character &#34;B&#34; appears iteratively at 30 Hz, which causes a pronounced flicker as a result of the intermediate tone display. 
     Application of a d.c. voltage to liquid crystal brings on electrolysis, which impairs the operating life of the device. Therefore, an alternating display data signal must be supplied to the liquid crystal panel so as to avoid a defect caused by d.c. voltage application. For this reason, the liquid crystal panel 7 is given an alternating signal so that the display data signal has alternate polarities for consecutive frames, although this aspect is not shown in FIG. 7. Namely, the first, third and fifth frames have display data signals with a positive polarity, while the second, fourth and sixth frames have display signals with a negative polarity, as shown in FIG. 10. 
     In the prior art liquid crystal display apparatus producing an intermediate tone, as illustrated in FIG. 7, no display data signal is supplied in even-numbered frames to the display area where the character &#34;B&#34; is to be displayed in an intermediate tone, and the display data signals for these frames have polarities of &#34;+&#34;, &#34;±0&#34;, &#34;+&#34;, &#34;±0&#34;, &#34;+&#34;, and so on as shown in FIG. 10. This portion of the liquid crystal panel is applied with the voltage signal only in odd-numbered frames with a positive polarity invariably, and this means the application of a d.c. voltage to liquid crystal due to the integration effect, resulting in an impaired service life of the liquid crystal display panel. 
     SUMMARY OF THE INVENTION 
     An object of this invention is to overcome the foregoing prior art problem and provide a method and an apparatus for liquid crystal display capable of displaying intermediate tones of images while preventing the occurrence of flicker and impairment of characteristics of the liquid crystal panel. 
     In accordance with this invention, an intermediate tone or half tone of an image may be displayed by cancelling one or more lines of each frame through generation of a prohibit signal. The prohibited line of the frame is shifted in consecutive frames, and the order or sequence of shift is varied over a group of frames. This operational scheme provides an intermediate tone of image depending on the number of times of display for display data on each line without a significant flicker of display and without the application of a d.c. voltage to the liquid crystal panel. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing the liquid crystal display apparatus embodying the present invention; 
     FIG. 2 is a block diagram showing a specific arrangement of the principal portion of the apparatus shown in FIG. 1; 
     FIGS. 3A, 3B and 3C are timing charts used to explain the operation of the arrangement shown in FIG. 2; 
     FIGS. 4A through 4B and FIGS. 5A through 5E are diagrams explaining the intermediate tone display on the liquid crystal display panel; 
     FIG. 6 is a table showing the polarity of the application voltage to the liquid crystal panel shown in FIG. 1; 
     FIG. 7 is a block diagram showing a conventional liquid crystal display apparatus; 
     FIGS. 8A and 8B are diagrams showing the contents of the memories in the arrangement of FIG. 7; 
     FIGS. 9A, 9B and 9C are diagrams used to explain the intermediate tone display implemented by the conventional apparatus shown in FIG. 7; and 
     FIG. 10 is a table explaining the polarity of the liquid crystal application voltage produced by the arrangement shown in FIG. 7. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     An embodiment of this invention will now be described with reference to the drawings. FIG. 1 shows in block diagram an embodiment of the inventive liquid crystal display apparatus, which includes a display memory 10, an attribute memory 11, an oscillator 12, a timing signal generating circuit 13, a frame counter 14, a line counter 15, a display control circuit 16, a gate circuit 17, and other functional blocks equivalent to those shown in FIG. 7 as referred to by the common symbols. 
     In the arrangement of FIG. 1, the display memory 10 stores codes of characters to be displayed, while the attribute memory 11 stores data indicative of whether each character stored in the display memory 10 is to be displayed in an intermediate tone. The display address generating circuit 1 produces a display address 8 in synchronism with the clock provided by the oscillator 12, and it is fed to the display memory 10 and attribute memory 11. The display memory 10 responds to the display address 8 to read out a character code 9A to the display data forming circuit 6, which forms a display data 9 representing a character pattern of the character to be displayed. The attribute memory 11 reads out an attribute signal 20 indicating whether the display data 9 produced by the display data forming circuit 6 is to be displayed in an intermediate tone. The attribute signal 20 has a &#34;high&#34; level for a character to be displayed in intermediate tone and has a &#34;low&#34; level for a character to be displayed in normal fashion. 
     The timing signal generating circuit 13 responds to the clock from the oscillator 12 to produce a frame pulse signal 18 indicative of the beginning of a frame and a line pulse signal 19 indicative of the beginning of a line. Assuming the number of lines of a frame on the liquid crystal panel 7 to be 200, for example, the timing signal generating circuit 13 produces a frame pulse signal 18 at every 200 line pulse signals 19. The frame pulse signal 18 and line pulse signal 19 are supplied to the liquid crystal panel 7 so as to establish the synchronism of display, and at the same time these signals 18 and 19 are fed to the frame counter 14 and line counter 15, respectively. 
     Count values of the frame counter 14 and line counter 15 are fed to the display control circuit 16, which specifies a line number dependent on the count value in response to a rise of the attribute signal 20 from the attribute memory 11, and produces a display inhibit signal 21 at a timing of output of the display data forming circuit 6 of display data 9 for a character to be displayed in intermediate tone with this line number. The display inhibit signal 21 has a &#34;low&#34; level, causing the gate circuit 17 to be disabled so that the display data 9 for the specified line is not delivered to the liquid crystal panel 7. Each frame has a different line of display data 9 blocked by the gate circuit 17, and therefore the specified character is displayed in intermediate tone. 
     FIG. 2 shows a specific circuit arrangement of the frame counter 14, line counter 15, display control circuit 16 and gate circuit 17 shown in FIG. 1. The arrangement includes a 1/4 frequency division circuit 23, a shift register 24 used for setting, a shift register 25 used for frame control, logical AND gates 26-29, a logical OR gate 30, a logical NAND gate 31, a shift register 32 used for line control, and a set of AND gates 33. Circuit portions corresponding to those in FIG. 1 are given the common symbols. 
     The operation of the above circuit arrangement will be described using FIG. 3 with the assumption that a character consists of eight lines, the display data forming circuit 6 produces 8-bit display data 9, and the shift registers 24, 25 and 32 have each a 4-bit arrangement. However, the numbers of bits, such as eight bits and four bits, have nothing to do with the following explanation. 
     It is assumed that the 1/4 frequency division circuit 23 has received a frame pulse 18 at  ○1  and produces a clock pulse 44 as shown in FIG. 3A. By this clock pulse, the frame control shift register 25 is initialized by being supplied with the contents of the initial setting shift register 24. The shift register 25 is assumed to be initialized with its output 36 providing a &#34;high&#34; level and outputs 37-39 providing a &#34;low&#34; level. The initial setting shift register 24 has had a &#34;high&#34; output 34 and other &#34;low&#34; outputs, but after initialization of the frame control shift register 25 it is shifted by one bit by the clock pulse 44 to have its output 34 reversing to &#34;low&#34;, output 35 reversing to &#34;high&#34; and other outputs remaining a &#34;low&#34; level preparing for the next initialization. The frame control shift register 25 has its outputs 36-39 unchanged until the entry of the next frame pulse signal 18. 
     After the frame control shift register 25 has been initialized in response to the frame pulse signal 18 at  ○1 , a line pulse signal 19 at ○1  comes in to cause the line control shift register 32 to provide a &#34;high&#34; output 40 and &#34;low&#34; outputs 41-43, for example, as shown in FIG. 3B, which, together with the &#34;high&#34; output 36 and &#34;low&#34; outputs 37-39 of the frame control shift register 25, causes the display control circuit 16 to have only &#34;high&#34; output on the logical AND gate 26 and then have a &#34;high&#34; signal 45 at the output of the logical OR gate 30. The line control shift register 32 makes a cycle of a &#34;high&#34; output iteratively upon receiving four line pulse signals 19, causing the logical AND gate 26 to produce a &#34;high&#34; output and then the logical OR gate 30 to produce a &#34;high&#34; output signal 45 at each entry of the first, fifth, or generally the 1+4N th (N=0, 1, 2, . . . ) line pulse signals 19. 
     Assuming that the attribute memory 11 (FIG. 1) is providing a &#34;high&#34; attribute signal 20 with the intention of an intermediate tone display, the logical NAND gate 31 produces a display inhibit signal 21 (a &#34;low&#34; level signal) in each display period for the first, fifth, or generally the 1+4N th (N=0, 1, 2, . . . ) lines of the first frame. Consequently, the display data 9 to the liquid crystal panel 7 is blocked by the logical AND gates 33 in the gate circuit 17, and therefore the first and fifth lines of a character pattern &#34;A&#34; are kept blank in the first frame. 
     Next, when a frame pulse signal 18 at  ○2  has entered the frame counter 14, the frame control shift register 25 shifts its contents by one bit, providing a &#34;high&#34; output 37 and &#34;low&#34; outputs 36, 38 and 39, as shown in FIG. 3A. In this state, when a line control pulse signal 19 at ○1  comes in, the line control shift register 32 produces a &#34;high&#34; output 40 and &#34;low&#34; outputs 41-43. Consequently, the display control circuit 16 has &#34;low&#34; signals at the output of the logical AND gates 26-29, as shown in FIG. 3C. 
     At entry of the next line pulse signal 19 at  ○2 , the line control shift register 32 has its output 41 becoming &#34;high&#34; and outputs 40, 42 and 43 becoming &#34;low&#34;, causing the display control circuit 16 to have a &#34;high&#34; signal at the output of the logical AND gate 27 and then a &#34;high&#34; output 45 on the logical OR gate 30. Since the line control shift register 32 rotates a &#34;high&#34; output around its outputs 40-43 by receiving four line pulse signals 19, the logical OR gate 30 produces a &#34;high&#34; output 45 at the second, sixth, or generally the 2+4N th (N=0, 1, 2, . . . ) lines. At this time, the attribute memory 11 is providing a &#34;high&#34; attribute signal 20 with the intention of intermediate tone display, and therefore the logical NAND gate 31 produces a display inhibit signal 21 (a &#34;low&#34; level signal) in each display period for the second, sixth, or generally the 2+4N th (N=0, 1, 2, . . . ) lines of the second frame. Consequently, the second and sixth lines of the character pattern &#34;A&#34; are kept blank in the second frame as shown in FIG. 4B. It should be noted that the first line is not involved inherently for displaying the character &#34;A&#34;. 
     In the same manner, when the frame pulse signal 18 at  ○3  or ○4  has entered the frame counter 14 as shown in FIG. 3A, the third and seventh lines are kept blank in the third frame as shown in FIG. 4C, or the fourth and eighth lines are kept blank in the fourth frame as shown in FIG. 4D. 
     Accordingly, by scattering blank lines over frames, the character &#34;A&#34; appears in an intermediate tone on the display panel as shown in FIG. 4E, and in this case flicker is less noticeable because only part of a character pattern is disactivated. 
     These are the case of 4-frame period, i.e., a character is divisionally eliminated from display in a length of four frames. Next, when a frame pulse signal 18 at  ○5  has entered the frame counter 14, the 1/4 frequency division circuit 23 produces a clock pulse 44 as shown in FIG. 3A, causing the initial setting shift register 24 to transfer its contents to the frame control shift register 25, and consequently it is initialized to have a &#34;high&#34; output 37 and &#34;low&#34; outputs 36, 38 and 39. This clock pulse 44 operates on the initial setting shift register 24 to advance by one bit for the subsequent initializing operation. 
     The remaining operation of the line control shift register 32 for the fifth frame is exactly identical to the previous case, and the line control shift register 32 produces a &#34;high&#34; output 40 in response to the line pulse signal 19 at  ○1  and produces a &#34;high&#34; output 41 in response to the line pulse signal 19 at  ○2 , as shown in FIG. 3C. Accordingly, with the output of the line control shift register 32 becoming &#34;high&#34; for the second, sixth, or generally the 2+4N th (N=0, 1, 2, . . . ) lines of the fifth frame, the display control circuit 16 provides the display inhibit signal 21 (a &#34;low&#34; level signal) as in the previous case. Consequently, the second and sixth lines of the character &#34;A&#34; are kept blank in the fifth frame, as shown in FIG. 5A. In the same manner, the third and seventh lines are blank in the sixth frame (FIG. 5B), the fourth and eighth lines are blank in the seventh frame (FIG. 5C), and the first and fifth lines are blank in the eighth frame (FIG. 5D), resulting in an intermediate tone display for the character &#34;A&#34; as shown in FIG. 5E. It is not necessary for the ninth, tenth, 11th and 12th frames to have blanking on their third and seventh lines, the fourth and eighth lines, the first and fifth lines, and the second and sixth lines, respectively, but instead blank lines may preferably be set irregularly such as the first and eighth lines, the second and fifth lines, the third and sixth lines, and the fourth and seventh lines, respectively, so that flicker is alleviated more effectively. 
     As described above, by changing the correspondence between the line numbers of blank lines and the frame number at every fourth frame sequentially, the character &#34;A&#34; can be displayed in an intermediate tone. 
     The following describes using FIG. 6 the fact that a d.c. voltage component is not applied to the liquid crystal panel, as opposed to the prior art liquid crystal display apparatus as shown in FIG. 7. The explanation is focused on the operation of a specific line (the fifth line). 
     The alternating signal is applied to the liquid crystal panel so that consecutive frames have a positive and negative polarities alternately, as in the conventional technique. The first frame has a positive signal, but this line is made blank by the gate circuit 17 (FIG. 1) and neither positive or negative voltage is applied to the liquid crystal panel 7. In the second frame, the signal reverses to negative, enabling the gate circuit 17 to display the line, and a display data signal with a negative polarity is applied to the liquid crystal panel 7. In the same way, the polarity of signal applied to liquid crystal is determined successively. FIG. 6 shows the case in which the ninth through 16th frames have blank display lines on the third and seventh lines, the fourth and eighth line, the first and fifth lines, the second and sixth lines, the fourth and eighth lines, the first and fifth lines, the second and sixth lines, and the third and seventh lines, respectively. Accordingly, the liquid crystal panel 7 is applied with display data signals having polarities of &#34;+&#34;, &#34;-&#34; and &#34;±0&#34; . Although the polarity shift cycle is two frames, as shown in FIG. 6, the appearance of blanking frame is not periodical. In other words, the display inhibit signal for prohibiting a display data from appearing on the liquid crystal panel is produced at intervals different from a common multiple with the alternating period of the application voltage. Nonetheless, as will be appreciated from the figure, one frame out of four is certainly given the polarity &#34;±0&#34;. On this account, voltages applied to liquid crystal are averaged out to zero, and no d.c. voltage component is applied to the liquid crystal panel 7. 
     The foregoing embodiment implements intermediate tone display by making a specific line blank once in four frames. The present invention is not confined to this scheme, but instead it is possible to have intermediate tone display in different contrast than the above embodiment by changing the operating condition in such a way that a display line is made blank twice in four frames, or once in five frames. Accordingly through the provision of several blanking frame rates and by combining these operating conditions, display in several intermediate tones is made possible. This can be achieved, for example, by defining a first tone to be done by blanking a line once in four frames, a second tone to be done by blanking a line once in five frames, a third tone to be done by blanking a line twice in four frames, and so on, and by selecting a tone control in response to the output of the attribute memory 11. 
     According to this invention, as described above, intermediate tone display with less noticeable flicker is achieved, the liquid crystal panel is prevented from d.c. voltage application so that it retains the performance and life, and several intermediate tones of display can be produced selectively.