Abstract:
A boot swap method for multiple processor computer systems utilizes a baseboard management controller (BMC) to manage the abnormal booting problem of multiple processor computer systems. According to the usage state of the central processing unit (CPU) or the basic input/output system (BIOS) stored in read only memory (ROM), a CPU switching procedure or an ROM switching procedure is executed to select an available CPU and BIOS for booting. The method can greatly increase the system stability.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of Invention  
         [0002]     The invention relates to a method for managing the problem of abnormal booting in a multiple processor computer system. More particularly, the invention relates to a method that uses a baseboard management controller (BMC) to switch among central processing units (CPUs) or read only memory (ROM), thereby managing the problem of abnormal booting.  
         [0003]     2. Related Art  
         [0004]     Based upon the design concept of highly available systems, it is necessary to have a backup system in order to maintain the normal functioning of the system without any manual problem shooting. This is the main reason for the existence of multiple processor systems. A multiple processor computer system such as a server has several CPUs. Therefore, the system has a higher efficiency and can replace a defective CPU if any error occurs.  
         [0005]     The booting procedure for a multiple processor computer system is done by assigning a CPU as the boot CPU (boot strap processor) to process BIOS commands during booting process, initializing the computer system and loading in the operating system (OS). The boot BIOS is stored in the BIOS ROM. Other CPUs during the booting process are defined as application processors and set in the wait state.  
         [0006]     When the boot CPU cannot boot, a conventional method is to encode in the BIOS a CPU switching program so that the system can switch from the boot CPU to another application processor. The switching mechanism is shown in  FIG. 1 .  
         [0007]     Another possible problem is that after the boot CPU has been switched to all other CPUs the system and the boot BIOS still cannot boot. This happens when the BIOS ROM is out of order. To solve the BIOS disorder problem, one or even many backup ROM&#39;s are proposed as the substitute solution. The backup BIOS stored in a backup ROM is used to restart the booting process. The switching mechanism is shown in  FIG. 2 .  
         [0008]     However, the drawback of the above-mentioned method is that one has to encode a special BIOS to switch the CPUs or to design the ROM boot swap to switch between the BIOSs stored in ROMs. Its electronic circuit is more complicated.  
       SUMMARY OF THE INVENTION  
       [0009]     In view of the foregoing, the invention provides a boot swap method for multiple processor computer systems. It uses a BMC to manage the booting process, to determine whether the CPU and BIOS is malfunctioning, and to execute necessary operations. The method includes the following steps. First, a BMC is used to confirm the abnormality of a booting process. A CPU switching procedure is executed and the system is rebooted. When the CPU switching procedure fails, a ROM switching procedure is executed to reboot the system. The CPU switching procedure swaps between a boot CPU and at least one application CPU via the BMC. The ROM switching procedure swaps between the boot BIOS stored in a boot ROM and a backup BIOS stored in at least one backup ROM.  
         [0010]     Using the invention, the BMC can manage the booting problem. The system BIOS and ROM do not require extra designs. The stability of the system can be enhanced too. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]     The invention will become more fully understood from the detailed description given hereinbelow illustration only, and thus are not limitative of the present invention, and wherein:  
         [0012]      FIGS. 1 and 2  explain the boot swap mechanism of a multiple processor system in the prior art;  
         [0013]      FIG. 3  shows the boot swap mechanism that uses the BMC to manage a multiple processor system according to the invention;  
         [0014]      FIG. 4  shows the CPU switching procedure of the invention; and  
         [0015]      FIG. 5  shows the ROM switching procedure of the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0016]     The disclosed method mainly utilizes a baseboard management controller (BMC) to manage the booting process, to determine whether the CPU or BIOS is out of order, and to switch to another CPU or BIOS.  
         [0017]     The BMC is originally applied to the intelligent platform management interface (IPMI). It controls the interface between the system management software and the platform management hardware, provides the functions of automatic monitoring, event recording, and control recovering, and can function as the network gate among the system management software, the intelligent platform management bus (IPMB) and the intelligent chassis management bus (ICMB).  
         [0018]     The reason that the invention can use the BMC to manage system disorder problems is because the system can use a low pin count (LPC) interface to obtain the information regarding to the system state via the BMC.  
         [0019]     The invention is another whole new application of the BMC. With reference to  FIG. 3 , the basic execution priority is first performing CPU swap and rebooting and, if failed, then performing ROM swap and reboot.  
         [0020]     After the system power is turned on, the first step confirms if the BMC does not receive a booted message from the boot BIOS (step  110 ). If the booted message has been received, it means that the system is booted and functioning normally (step  120 ). The BMC is powered by a system backup power supply. Therefore, before the system power is turned on, the BMC is ready. This is why the BMC can be turned on as the system power is on and receive the booting state transmitted from the BIOS.  
         [0021]     Afterwards, the system confirms whether the CPU switching procedure and the ROM switching procedure are both completed (step  130 ). If the system has completed the CPU switching procedure and the ROM switching procedure while the system still cannot be turned on, it means all CPUs have errors and the system cannot operate (step  140 ). The only solution is manual problem shooting, such as replacing the CPUs.  
         [0022]     The system confirms whether the CPU switching procedure is completed (step  150 ). If not, the system immediately performs the CPU switching procedure (step  160 ).  
         [0023]     The CPU switching procedure in step  160  includes two detailed steps: changing the SMI (System Management Interrupt) states of all the CPUs so as to separate the BSP CPU from the CPU bus (step  161 ). (The BSP CPU refers to the bootstrap processor, the default processor for booting the computer. In the CPU switching procedure, it should be replaced as the previous CPU used for booting); generating a CPU swap signal and a reboot signal from the BMC to the boot BIOS or the backup BIOS (step  162 ). After the system is rebooted, it returns to step  110  to confirm the booting state.  
         [0024]     If in step  150  the CPU has been switched, the system then performs the ROM switching procedure (step  170 ). This procedure switches the default booting BIOS from the boot BIOS in the BIOS ROM to a backup BIOS in a backup ROM. The backup BIOS is then used to turn on the system. More explicitly, the BMC generates a ROM switching signal to a complex programmable logic device (CPLD) to switch to the backup ROM. The system generates a system reboot signal to the backup BIOS in the backup ROM. Once the system is rebooted, it returns to step  110  to confirm the booting state.  
         [0025]      FIG. 4  explains the procedures executed in the BMC when performing the CPU swap. SMI 1  and SMI 2  are two system management interrupts (SMI&#39;s) on the BMC. SWAP refers to the switching state. STBY_PGD, ROM_SWAP, STATE_CHANGE, SYS_PGD, and CPU_SWAP are functional parameters of the control program in the BMC. STBY_PGD is the standby state. ROM_SWAP is the ROM swap state. STATE_CHANGE refers to the state change. SYS_PGD is the system reboot state. CPU_SWAP is the CPU swap state. The CPU swap in the drawing contains four states, making the BMC know to which CPU the system has switched. The execution contents of each state are described as follows:  
         [0026]     (1) The execution contents of the first state include: 
        a. Set SMI 1  at LOW (low voltage);     b. Set SMI 2  at HIGH (high voltage);     c. Set SWAP to the second state;     d. Set STATE_CHANGE as CHANGE.        
 
         [0031]     (2) The execution contents of the second state include: 
        a. Set SMI 1  at HIGH;     b. Set SMI 2  at LOW;     c. Set SWAP to the third state;     d. Set STATE_CHANGE as CHANGE.        
 
         [0036]     (3) The execution contents of the third state include: 
        a. Set SMI 1  at LOW;     b. Set SMI 2  at LOW;     c. Set SWAP to the fourth state;     d. Set STATE_CHANGE as CHANGE.        
 
         [0041]     (4) The execution contents of the fourth state include: 
        a. Set SWAP to the fourth state;     b. Set STATE_CHANGE as CHANGE.        
 
         [0044]      FIG. 5  shows the detailed steps of using the BMC to perform ROM swap. BACKUPROM represents the backup ROM state. According to the invention, the backup ROM can be in either the normal state of the backup state. ROMswitch represents the functional parameters of the ROM switching state.  
         [0045]     Following the CPU and ROM procedure outlined in  FIGS. 4 and 5 , when the booting process encounter abnormality the BMC first performs the CPU swap in  FIG. 4 . If the booting process is still unsuccessful, the ROM swap in  FIG. 5  is then executed.  
         [0046]     Certain variations would be apparent to those skilled in the art, which variations are considered within the spirit and scope of the claimed invention.