Abstract:
A technique includes detecting a phase difference between an input signal and a first signal. A second signal is generated that has a fundamental frequency indicative of the phase difference. The second signal is modulated to produce the first signal.

Description:
BACKGROUND  
         [0001]    The invention generally relates to a phase locked loop.  
           [0002]    A phase locked loop (PLL) is used for purposes of synchronizing the phases of two signals together. For example, FIG. 1 depicts a typical PLL  5  that includes a Voltage Controlled Oscillator (VCO)  7 , a loop filter  9  and a phase detector  10 . The phase detector  10  includes an input terminal  13  that receives an input signal that is “locked” onto by the PLL  5 . In this manner, the phase detector  10  compares the input signal with an output signal (of the PLL  5 ) that is generated by the VCO  7  at its output terminal  11 . Based on the detected phase difference between the input and output signals, the phase detector  10  generates a control signal that propagates through the loop filter  9  to the input terminal  8  of the VCO  7 . The VCO  7  controls the frequency of the output signal based on the voltage level of the control signal. Due to this closed loop control, the PLL  5  “locks” onto the phase of the input signal so that the output signal has a predefined phase relationship (a zero, ninety or one hundred eighty degree relationship, as examples) with respect to the input signal.  
           [0003]    The VCO  7 , in its steady state, typically operates at a frequency that is either the same or an integer multiple of the frequency of the input signal. Thus, typically, the output signal has a frequency that is the same as or an integer multiple of the input signal. However, such an arrangement may be subject to noise. In this manner, for a typical oscillator, such as an inductor capacitor (LC)-based tank circuit, the oscillator output noise spectrum (i.e., the noise that is present in the oscillator&#39;s output signal) may be defined by the following equation:  
                        H        (     δ                 ω     )            2     ≈       1     4          π   2     ·   Q                (       ω   o       δ                 ω       )     2         ,           Eq   .              1                               
 
           [0004]    where “|H(δω)| 2 ” represents the output noise spectrum of the oscillator, “Q” represents the Q factor of the inductor, “ ω   o ” represents the resonant frequency of the oscillator and “δω” represents the spectral frequency.  
           [0005]    As depicted in FIG. 2 in a graph of the oscillator&#39;s output noise versus frequency, the oscillator is highly susceptible to external noise at the resonant frequency, the fundamental frequency of operation of the oscillator. This external noise may be introduced by, for example, the substrate in which the oscillator is fabricated and may also be attributable to the power supply that powers the oscillator. Furthermore, the extent of the introduced external noise is specifically dependent upon the integrated circuit fabrication technology. For example, in complementary metal-oxide-semiconductor (CMOS) fabrication, the noise may be attributable to substrate coupling, which modulates the threshold voltage of the metal oxide semiconductor field-effect-transistors (MOSFETs) of the oscillator, and the noise may also be attributable to, for example, capacitive coupling effects present at the source and drain terminals of the MOSFETs of the oscillator.  
           [0006]    Regardless of the sources of the noise, in a typical PLL, the presence of noise in the output signal from the oscillator introduces a phase noise, or jitter, between the input and output signals of the PLL, thereby adversely affecting operation of the PLL.  
           [0007]    Thus, there is a continuing need for an arrangement to address one or more of the problems that are stated above. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWING  
       [0008]    [0008]FIG. 1 depicts a phase locked loop of the prior art.  
         [0009]    [0009]FIG. 2 depicts an output noise spectrum for a typical oscillator.  
         [0010]    [0010]FIG. 3 is an illustration of a spectral distribution of an output signal of a phase locked loop according to an embodiment of the invention.  
         [0011]    [0011]FIG. 4 is a schematic diagram of a phase locked loop according to an embodiment of the invention.  
         [0012]    [0012]FIGS. 5 and 6 are schematic diagrams of single sideband modulators according to embodiments of the invention.  
         [0013]    [0013]FIG. 7 is a schematic diagram of a computer system according to an embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0014]    For purposes of reducing jitter, a voltage controlled oscillator (VCO) of a phase locked loop (PLL) in accordance with an embodiment of the invention has a fundamental frequency of operation (i.e., a resonant frequency) that is slightly offset from the fundamental frequency of an output signal of the PLL. Due to this offset, the noise in the output signal of the PLL is significantly reduced, as compared to the noise present in the output signal if the output signal had the same fundamental frequency as the VCO. As described below, in some embodiments of the invention, single sideband modulation (SSM) is used to produce this frequency offset.  
         [0015]    More specifically, referring to FIG. 4, an embodiment  50  of a PLL in accordance with the invention generates an output signal called V OUT . The PLL  50  includes a VCO  62  that generates in-phase and quadrature sinusoidal signals in response to a phase comparison that is made by a phase detector  54  (of the PLL  50 ) that is coupled to the VCO  62 . Thus, the frequencies of these signals are controlled by the phase difference that is indicated by the phase detector  54 . In this manner, the phase detector  54  has a first input terminal  56  that receives an input signal (called “V IN ”) of the PLL  50  and a second input terminal  58  that receives the V OUT  signal. The phase detector  54  compares the V IN  and V OUT  signals and in response to this comparison, produces a control signal on a control signal line  53 . A loop filter  52  is coupled between the control signal line  53  and an input terminal  64  of the VCO  62 .  
         [0016]    Unlike conventional PLLs, the PLL  50  includes an additional component, a modulator  60 , that modulates the in-phase and quadrature signals that are provided by the VCO  62  to produce the V OUT  output signal. This modulation, in turn, causes the fundamental frequency (called “ 107   OUT ”) of the V OUT  signal to be offset from a fundamental frequency (called “ ω   0 ”), or resonant frequency, of the VCO  62 . As noted above, due to this frequency shift, noise in the V OUT  signal is significantly reduced, as compared to the conventional arrangement in which the fundamental frequency of the V OUT  signal is equal to  ω   0 . Thus, due to the frequency offset, potential jitter at the phase detector  54  is circumvented by the reduction of noise in the V OUT  signal. With the addition of the modulator  60 , an oscillator  65  is effectively formed from the VCO  62  and the modulator  60 . However, this oscillator  65  has a resonant frequency of  ω   0 , a frequency that is offset from the  ω   OUT  fundamental frequency of the V OUT  signal.  
         [0017]    As an example, in some embodiments of the invention, the V IN  and V OUT  signals may be clock signals.  
         [0018]    In some embodiments of the invention, the modulator  60  uses single sideband (SSB) modulation, a modulation in which signals with two different fundamental frequencies are multiplied together to create frequency components at the sum and difference frequencies. In this manner, one of these fundamental frequencies is the  ω   0  frequency, the resonant or fundamental frequency of operation of the VCO  62 , and the modulator  62  generates the other fundamental frequency by dividing the  ω   0  frequency. In this manner, as described below, in some embodiments of the invention, this division may be accomplished by a frequency divider circuit such that the modulator  60  produces in-phase and quadrature signals that each have a fundamental frequency that is equal to the  ω   0  frequency divided by some programmable integer. It is noted that in other embodiments of the invention, integer division may not be used.  
         [0019]    In the SSB modulation performed by the modulator  60  in some embodiments of the invention, the product of the modulation (the V OUT  signal) has the following time relationship:  
                 V   OUT     =       (       sin        (     ω                 ot     )       ·     cos   (         ω                 ot     n     +     π   2       )       )     ±     (       sin   (       ω                 ot     +     π   2       )     ·     cos   (       ω                 ot     n     )       )         ,           Eq   .              2                               
 
         [0020]    wherein “ ω   0 ” is the fundamental frequency of operation of the oscillator  60 , and “n” represents an integer.  
         [0021]    Due the SSB modulation, the following relationship is formed between  ω   OUT , the frequency of the V OUT  signal, and  ω   0 :  
               ω   OUT     =       ω   0     ±       ω   0     n               Eq   .              3                               
 
         [0022]    Alternatively, in some embodiments of the invention, the lower frequency that is used for purposes of modulating the  ω   0  frequency is not produced by a frequency divider. Instead, for these embodiments of the invention, the lower frequency is produced by a fixed frequency oscillator that generates quadrature and in-phase output signals at a frequency that is independent from the  ω   0  frequency. Thus, for these embodiments, this fixed frequency oscillator operates independently from the VCO  62 . Therefore, for these embodiments, the  ω   OUT  frequency is defined by the following relationship:  
           ω   OUT = ω   0 ± ω   OFFSET ,   Eq. 4  
         [0023]    where “ ω   OFFSET ” represents the frequency of the fixed frequency oscillator. Other variations are possible.  
         [0024]    Referring to FIG. 3, due to the SSB modulation, unwanted sidebands  15  (sidebands  15   a ,  15   b  and  15   c  depicted as examples) in the V OUT  signal are substantially diminished to smaller magnitude sidebands  16  (sidebands  16   a,    16   b  and  16   c,  depicted as examples), as compared to the V OUT  signal being produced directly from the VCO  62 .  
         [0025]    As depicted in FIG. 3, in some embodiments of the invention, phase discrimination is used to produce the single sideband. In some embodiments of the invention, this phase discrimination results in high side mixing, a mixing that produces a desired sideband  20  that is located at a frequency of  ω   0 + ω   0 /n. For these embodiments, the SSB modulation diminishes the  ω   0  frequency spectral component and spectral components less than the  ω   0  frequency. However, in other embodiments of the invention, the other sideband is selected. In this manner, in other embodiments of the invention, the  ω   0  spectral component as well as spectral components located at frequencies greater than the  ω   0  frequency, may be diminished, i.e., the SSB modulation may produce low side mixing.  
         [0026]    The VCO  62  furnishes both an in-phase signal and a quadrature signal (a signal that has the same frequency as the quadrature signal but is shifted by 90° in phase relative to the in-phase signal) to the modulator  60 . In this manner, referring to FIG. 5, an embodiment of the modulator  60  in accordance with the invention includes a mixer  74  that receives the in-phase signal from the VCO  62  at its input terminal  70 . Another mixer  82  of the modulator  60  receives the quadrature signal from the VCO  62  at its input terminal  72 . The mixer  74  multiplies the in-phase signal with a lower frequency version of this in-phase signal that is present at the mixer&#39;s input terminal  78 . Similarly, the mixer  82  multiplies the quadrature signal with a lower frequency version of this quadrature signal that is present at the mixer&#39;s input terminal  80 .  
         [0027]    The signals present on the input terminals  78  and  80  are produced by a frequency divider circuit  76 , a circuit that receives the in-phase and quadrature signals that are provided by the VCO  62 . In this manner, the frequency divider circuit  76  divides the frequency of the in-phase signal by a programmable integer (called “n”) to produce the signal at the input signal line  78 , and the frequency divider  76  divides the frequency of the quadrature signal to produce the signal at the input terminal  80 . The value for “n” may be established by writing to a register  69  of the modulator  60 . This register  69  may be accessed via data, address and control lines  67 .  
         [0028]    The output signals that are generated by the mixers  74  and  82  due to the above-described multiplications are summed together by an adder  90  of the modulator  60 . An output terminal  92  of the adder  90  provides the V OUT  signal.  
         [0029]    Due to the SSB modulation, the phase of the V OUT  signal is shifted by approximately 90 degrees relative to the V IN  signal, i.e., the V OUT  signal is a quadrature signal with respect to the V IN  signal, a signal that may be labeled an “in-phase” signal. It may be desirable to produce a V OUT  signal that is in phase with the V IN  signal. For example, such is the case for a half rate receiver, circuit that uses both quadrature and in-phase clock signals. Referring to FIG. 6, for purposes of producing an in-phase version of the V OUT  signal, in some embodiments of the invention, another modulator  100  may be used to take advantage of some of the signals that produced by the modulator  60  for purposes of generating a signal that is in phase with the V IN  signal.  
         [0030]    The modulator  100  has a similar design to the modulator  60 , with the exception that the modulator  100  does not have the frequency divider circuit  76  of the modulator  60 . Instead, modulator  100  uses the frequency divided in-phase and quadrature signals that are provided by the frequency divider  76 . In this manner, the modulator  100  includes a mixer  102  that includes an input terminal  104  that receives the same signal as the input terminal  78  of the mixer  74 . However, the mixer  102  multiplies the signal present at the input terminal  104  with the V OUT  signal. The modulator  100  also includes a mixer  110  that receives at its input terminal  112  the same signal as the input terminal  80  of the mixer  82 . However, the mixer  110  multiplies the signal present at the input terminal  112  with a signal that is received at its input terminal  122  and is effectively the V OUT  signal shifted by ninety degrees. I.e., the mixer  110  multiplies the signal on its input terminal  112  with the inverted in-phase signal that is provided by the VCO  62 . The output terminals of the two mixers  102  and  110  produce signals that are combined by an adder  116  of the modulator  100 , and the output terminal  120  of the adder  116  furnishes an output signal that is in phase with the V IN  signal. Thus, the output signal present at the output terminal  120  is an in-phase signal, and the V OUT  signal is a quadrature signal relative to the signal present at the output terminal  120 .  
         [0031]    Referring to FIG. 7, in some embodiments of the invention, the PLL  50  may be used in a computer system  200 . For example, the PLL  50  may be located near or on a processor  202  (a microprocessor, for example) to provide a clock signal (i.e., the V OUT  signal) to the processor  202  in response to another clock signal (i.e., the V IN  signal) that is received by the PLL  50 . Many such PLLs may be used throughout the computer system  200 .  
         [0032]    Besides the PLL  50 , the computer system  200  may include, for example, a memory I/O hub, or north bridge  206 , that is coupled to a local bus  204  along with the processor  202 . The north bridge  206  serves as an interface between a system memory bus  208 , the local bus  204  and Accelerated Graphics Port (AGP) bus  212  and a hub link to an I/O hub, or south bridge  220 . The AGP is described in detail in the Accelerated Graphics Port Interface Specification, Revision 1.0, published on Jul. 31, 1996, by Intel Corporation of Santa Clara, Calif.  
         [0033]    The south bridge  220 , in turn, provides interfaces to a Peripheral Component Interconnect (PCI) bus  240  and an I/O expansion bus  223 . The PCI Specification is available from The PCI Special Interest Group, Portland, Oreg. 97214. An I/O controller  230  may be coupled to the I/O expansion bus  223  and receive input from a keyboard  234  and a mouse  232 . The I/O controller  230  may also control operation of a floppy disk drive  238 . The south bridge  220 , for example, controls operation of a CD-ROM drive  221  and controls operation of a hard disk drive  225 . The PCI bus  240  may be coupled to, for example, a network interface card (NIC)  250  that provides an interface to a network for the computer system  200 . Other variations are possible.  
         [0034]    While the present invention has been described with respect to a limited number of embodiments, those skilled in the art, having the benefit of this disclosure, will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.