Abstract:
A DC bias feedback circuit stabilizes the I ds  of an active MESFET with respect to process-dependent I dss  variations to improve yield and reduce the effect of process variations.

Description:
BACKGROUND OF THE INVENTION 
     The saturation current with no applied gate voltage, I dss , between the source and drain of a field effect transistor (FET) is an important parameter of an FET. The value of I dss  for a particular FET is process dependent. The value of source drain current when a gate voltage is applied, I ds  is dependent on the characteristic I dss  of the device; as I dss  increases so does I dss . 
     Various techniques, such as carefully controlling process variables or using large source resistors for biasing, have been proposed to limit the variation or effect of variation of I dss . However, controlling I dss  in process lowers yield and using large resistors increases power dissipation. 
     Accordingly, techniques to increase the I dss  window are needed to increase yield. 
     SUMMARY OF THE INVENTION 
     According to one aspect of the invention, a negative feedback circuit compensates for process variations in I dss  to improve I ds  stability and process independence. 
     According to another aspect of the invention, a compensating current source is coupled to the source terminal of an FET to compensate for process variations in I dss . 
     Other features and advantages of the invention will be apparent in view of the following detailed description and appended drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of an embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A preferred embodiment of the invention is depicted in the circuit diagram of FIG. 1. Referring to FIG. 1, an active FET 10 has source, drain, and gate terminals 12, 14, and 16. The drain terminal 14 is coupled to a first terminal of a drain resistor Rd with the second terminal of Rd coupled to the VDD terminal of a power supply (not shown). The source terminal is coupled to a compensating current source 20. 
     The compensating current source 20 includes a second FET 22 matched to the active FET 10 and has its drain terminal 24 coupled to the source terminal 12 of the active FET 10 and to ground through a bypass capacitor 25. The source terminal 26 of the second FET 22 is coupled to the first terminal of a source resistor Rs with the second terminal of Rs coupled to ground. The first terminal of Rs is also coupled to the gate terminal 28 of the second FET through a capacitor 30. 
     The gate voltage of the second FET is set by a compensating voltage divider 32 including resistor R3 and R4 coupled at an output node 33. A first terminal of the compensating voltage divider 32 is coupled to the first terminal of the drain resistor Rd and the second terminal of the voltage divider 32 is coupled to ground. The output node 33 is coupled to the gate terminal 28 of the second FET 22. A bias generating voltage divider 34 is formed of resistors Ri and R2 and provide the bias voltage for the first FET 10. 
     The operation of the circuit depicted in FIG. 1 will now be described. The DC gate voltages of the active and second FETs 10 and 22 are determined by the bias and compensating voltage dividers. The values of R1, R2, R3, and R4 are selected generate bias voltages to set the steady state of I ds  to a selected value. However, as described above, process-dependent variations of I dss  will cause the value of the actual I ds  to vary from the selected value. 
     As is well known, the voltage drop across Rd is proportional to the I ds  flowing through the active FET 10 and the I ds  of both the active FET 10 and the second FET 22 must be the same because of the series connection. Thus, if the actual value of I ds  is greater than the selected value because of an undesired increase of Id dss  then the voltage at the second terminal of Rd decreases. This decrease of voltage decreases the current flow through the compensating voltage divider 32 and decreases the gate voltage on the second FET 22. The I ds  flowing through the second FET 22 is thus decreased which in turn reduces the I ds  flowing through the active FET 10. Accordingly, the compensating current source 20 compensates the actual I ds  to approximate the selected value of I ds . 
     Conversely, if the value of the I ds  of the active FET 10 is less than the selected value because of an undesired decrease in the value if I dss  then the voltage at the second terminal of Rd increases. As described above, this voltage increase causes the I ds  of the second transistor 22 to increase to compensate the actual value of I ds  to approximate the selected value of I ds . 
     Thus the compensating current source 20 always shifts I ds  toward a stable, selected value. The inclusion of the compensating current source compensates for process variations in I dss  to increase yield. Depending on the supply voltage, the resistance of R3, R4, and Rs are selected to provide a 50% improvement in I ds  variations with respect to I dss  variations. 
     The invention has now been described with reference to the preferred embodiments. Alternatives and substitutions will now be apparent to persons of ordinary skill in the art. Accordingly, it is not intended to limit the invention except as provided by the appended claims.