Abstract:
A clock tracking circuit and method uses a clock compensation signal to compensate for timing marks on a media disk. The clock compensation signal may compensate for at least one of improper clock track closure and written-in jitter of the timing marks used to produce the measured clock signal. The clock compensation signal may be used to control a controllable oscillator used to generate the clock signal that thereby provides a compensated clock signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims benefits from U.S. Provisional Patent Application No. 60/667,081 filed Apr. 1, 2005, the contents of which are hereby incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention relates generally to computer devices, and more particularly to a clock tracking circuit for use in a disk drive servo controller and related methods.  
       BACKGROUND OF THE INVENTION  
       [0003]     Data on modern computer disks is stored along circular tracks that are written and read by servo controlled, magnetic read/write heads. In order to allow for precise guidance of the read/write heads, disks are further coded with guide tracks. Typically, such guide tracks encode clock signals at defined intervals, and are placed on the disk surface during the manufacturing process. In order to allow for uniform guidance, clock signals are evenly spaced in the clock track. Even spacing can be assured by producing a clock signal at controlled, even, intervals. However, unless the period of rotation is an integer multiple of the nominal interval between two clock signals, the distance between the last clock signal and the first clock signal on the track will not be equal. Such a clock track is said not to be “closed”, and causes jitter in any clock recovered from the track.  
         [0004]     To ensure precise tracking, each time a clock track is written on a disk, clock track closure is ensured. To accomplish this, a clock track is currently re-written as many times as necessary to guarantee satisfactory clock track closure. This may be time-consuming and increases manufacturing throughput time.  
         [0005]     Additionally, even once clock track closure is achieved, a clock track typically continues to include written-in jitter. Written-in jitter results in phase-in error of propagated servo-patterns. This in turn affects the quality (linearity) of the position error signal.  
         [0006]     Written-in jitter is particularly acute, when media level servo track writers (MLSTW) are used in the production of disks. Currently, a clock track is written on a reference disk that is used each time a new set of disks is loaded on the MLSTW. When the reference disk is loaded on MLSTW, the offset of the disk will be different from the offset when the disk was written, and therefore the center of the written clock track on the disks will change. This will result in repeatable jitter of the read-back clock signal on the produced disks. This repeatable jitter has to be compensated to ensure precise propagation of the servo patterns on the blank disks.  
         [0007]     Accordingly, there is a need for a clock tracking circuit that may more effectively compensate for various types of clock jitter, including jitter attributable to incorrect clock track closure, and written-in jitter.  
       SUMMARY OF THE INVENTION  
       [0008]     This invention proposes a method which can compensate the clock track closure without need for repetitive writing of the clock track. The method may also be used to compensate for written-in jitter of the clock track, hence significantly improving the quality of the position error signal and tracking.  
         [0009]     Conveniently, the proposed method can be also be used to compensate repeatable jitter when a separate reference disk, with prewritten clock track, is used in MLSTWs. The same method used for compensation of written-in jitter can be used to compensate this repeatable jitter.  
         [0010]     In accordance with an embodiment of the present invention, a clock compensation signal is injected in a clock tracking circuit to compensate for at least one of improper clock track closure and written-in jitter of said timing marks on a clock signals.  
         [0011]     In accordance with an aspect of the present invention, there is provided a method of generating a compensated clock signal from a clock track on a disk. The clock track includes a plurality of timing marks. The method includes reading the timing marks from the clock track on the disk; producing a raw clock signal as a result; forming a difference between the raw clock signal and the compensated clock signal; adding a clock compensation signal to the difference to form a compensated error signal; and controlling an oscillator using the compensated error signal to generate said compensated clock signal.  
         [0012]     In accordance with another aspect of the present invention, a method of writing a clock track to media disks is provided. The method includes loading the media disks in a media level servo track writer; loading a reference clock disk containing timing marks on a clock track in the media level servo track writer; reading the timing marks from the clock track on the reference clock disk; producing a raw clock signal as a result; forming a difference between the raw clock signal and a compensated clock signal; adding a clock compensation signal to the difference to form said compensated error signal; controlling an oscillator using the compensated error signal to generate the compensated clock signal; and writing a clock track using said compensated clock signal to each of the plurality of disks.  
         [0013]     In accordance with yet another aspect of the present invention there is provided a clock tracking circuit, for forming a reference clock from timing marks in a clock track on a media disk. The tracking circuit includes a phase detector to determine a phase difference between a measured clock signal and a generated clock signal; an adder, receiving a signal derived from the phase difference and a clock compensation signal; a clock compensation signal generator to generate the clock compensation signal for each of the timing marks; and a controllable oscillator, controlled by an output of the adder to generate the compensated clock signal.  
         [0014]     Other aspects and features of the present invention will become apparent to those of ordinary skill in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]     In the figures which illustrate by way of example only, embodiments of the present invention,  
         [0016]      FIG. 1  is a schematic diagram of computer disk surface, including various clock timing marks;  
         [0017]      FIG. 2  is a schematic of a conventional phase-locked-loop controller used to track a clock track of a media disk;  
         [0018]      FIG. 3A  illustrates a clock tracking error signal, including error attributable to a clock track that is not closed;  
         [0019]      FIG. 3B  is a histogram of the clock output in the presence of the error signal of  FIG. 3A ;  
         [0020]      FIG. 4  is a schematic of a controller used to track a clock track of a computer disk, exemplary of an embodiment of the present invention;  
         [0021]      FIG. 5A  illustrates a clock tracking error signal, including a clock error compensation signal, provided in manners exemplary of an embodiment of the present invention;  
         [0022]      FIG. 5B  is a histogram of the clock output in the presence of the error signal of  FIG. 5A ;  
         [0023]      FIG. 6  is a schematic diagram of computer disk surface, including various clock timing marks that include written-in jitter;  
         [0024]      FIG. 7  is a schematic of a controller used to track a clock track of a computer disk, exemplary of an embodiment of the present invention;  
         [0025]      FIG. 8A  illustrates a clock tracking error signal, including error attributable to written-in error;  
         [0026]      FIG. 8B  illustrates a clock tracking error signal, including a clock error compensation signal, provided in manners exemplary of an embodiment of the present invention;  
         [0027]      FIG. 9A  is a histogram of the clock output in the presence of the error signal of  FIG. 8A ; and  
         [0028]      FIG. 9B  is a histogram of the clock output in the presence of the error signal of  FIG. 9B . 
     
    
     DETAILED DESCRIPTION  
       [0029]      FIG. 1  schematically illustrates a disk surface  10 , including a clock track  12 . Clock track  12 , has coded therein timing marks  14 , used to generate a reference clock signal having a frequency f c . Timing marks  14  are written at periodic intervals of 1/f c , and are thus evenly spaced.  
         [0030]     The number of timing marks N written on track  12  in one revolution is 
 
N=T s f c    (1) 
 
 where T s  is the period of spindle motor rotation and f c  is the frequency of the reference clock signal used to write the clock track. 
 
         [0031]     The nominal distance d i  between two adjacent timing marks t i  and t i-1  is 
 
 d   i =ω i   /f   c    (2) 
 
 where ω i  is the angular rotating speed while writing the corresponding timing mark t i . If t N-1  is the last timing mark and t 0  is the first timing mark then the angular distance between these two marks represents the clock closure d N , and is given by  
               d   N     =       2   ⁢   π     -       ∑     i   =   1       N   -   1       ⁢     d   i                 (   3   )             
 
         [0032]     If the period of rotation is not an integer multiple of the nominal interval between two clock signals, the angular distance between the last timing mark t N-1  and the first timing mark t 0  will not be the same as the nominal distance between the remaining timing marks (t i  and t i-1 ) and will, in fact, be shorter.  
         [0033]     Typically, the clock signal is tracked using a conventional phase-locked-loop  20  illustrated in  FIG. 2 . As illustrated, phase locked loop  20  includes a phase detector  22  and a voltage controlled oscillator (VCO)  26 . A divider  28  frequency scales (i.e. divides) the output of VCO  26 . Phase detector  22  produces an error signal proportional to the phase difference between the reference clock signal y r  and the divided form of the output of VCO  26 . The error signal is filtered by a low pass filter  24  to provide a control signal y t  used to control the frequency of VCO  26 . In operation, PLL  20  strives to reduce the filtered error signal y t , and thus will ultimately track the reference clock signal y r . Phase locked loops are discussed generally in Dan Wolaver, Phase-Locked Loop Circuit Design (Prentice Hall Advanced Reference Series, 1991).  
         [0034]     Now, incorrect closure of d N  will disturb the operation of conventional PLL  20  when tracking the clock signal as, for example, illustrated by measured results shown in  FIG. 3A . In these results the clock closure error is about 10%. The measured disturbance in input y t  to VCO  26  caused by the incorrect closure is illustrated. This, in turn results in frequency jitter in the divided output of the VCO  26 , y, as illustrated in the frequency histogram of  FIG. 3B .  
         [0035]     As noted, currently correct closure d N  is obtained by repeatedly re-writing the clock track until the closure period T N  meets specified requirement (typically, closure period must be T N =(1/f c )+/−0.1%).  
         [0036]      FIG. 4  accordingly illustrates a clock tracking circuit  40 , in the form of a PLL, exemplary of an embodiment of the present invention. Clock tracking circuit  40  includes a phase detector  42 , a summing block (summer)  44 , a clock compensation signal generator  52 , a low pass filter  46 , a VCO  48 , and a 1/M frequency divider  50 . A processor  60  is in communication with VCO  48 , and processor memory  62 . Processor  60  may take the form of a microcontroller, microprocessor, or the like. Memory  62  may store values assessed by processor  60 , and instructions causing clock tracking circuit  40  to function in manners exemplary of embodiments of the present invention.  
         [0037]     In one exemplary of embodiment of the present invention, incorrect closure d N  may be compensated using a compensation signal cy i  injected at summer  44  as shown in  FIG. 4 .  
         [0038]     In order to form cy i , the incorrect closure d N  may be measured and stored, using processor  60 . Specifically, the disk read/write head may, for example, read the written timing marks t i  from the disk media and use the read signal as a reference clock signal y r  for PLL circuit in  FIG. 2 . Now, the frequency of the nominal reference clock signal may be determined by processor  60  as f c , the period of rotation (T s ) may be measured, and the number N of written timing marks t i  may be calculated as the integer (T s f c ). Once N is known, the charge pump of PLL (not specifically illustrated) may be used to measure d N , to calculate Δd N =d N /(N−2). Δd N  may then be stored in processor memory  62 , for later use.  
         [0039]     Now using Δd N , a compensation signal cy i  may be generated by clock compensation generator  52 , for each timing mark t i . The compensation signal for the i th  timing mark takes the form, 
 
cy i =iΔd N    (4) 
 
 where Δd N  is,  
                 Δ   ⁢   d     N     =       d   N       N   -   2               (   5   )             
 
 This compensation signal effectively shifts the angular position of each timing mark t i  by an angle iΔd N . The compensation signal cy i  for each timing mark may alternately be generated by processor  60  and stored in memory  62 , removing any need for generator  52  to form cy i  from Δd N . 
 
         [0040]     Hence, the position of compensated timing marks will be  
               ct   i     =         t   i     +     cy   i       =       t   i     +     i   ⁢       d   N       N   -   2                     (   6   )             
 
         [0041]     As a result, the incorrect closure d N  may be eliminated by redistribution of the closure distance d N  among all other timing marks. The compensated timing marks are shown as ct i  in  FIG. 1 .  
         [0042]     Compensated timing marks ct i  may be written to track  12 , in place of timing marks t i . Such a disk may later be used as a reference clock disk in an MLSTW (as described below), or in a disk drive used to store data. Alternatively, clock tracking circuit  40  may be used to generate a compensated reference clock, y, taken at the output of frequency divider  50 .  
         [0043]      FIG. 5A  shows the compensated error signal y t  to VCO  48 , after the injection of the compensation signal cy i . As illustrated, the transient disturbance caused by incorrect closure is effectively eliminated.  FIG. 5B  shows measured frequency histogram of the compensated reference clock, taken from the divided output of the VCO, y. As compared to  FIG. 3B , the frequency jitter is significantly reduced.  
         [0044]     Conveniently, once the closure of the clock track has been compensated, written-in (repeatable) jitter of the clock track may optionally also be compensated, by clock compensation circuit  52 .  
         [0045]     Specifically, if the rotational speed during writing of the clock track is constant then the distance between any two adjacent timing marks will be constant and equal to d given by  
             d   =     l   N             (   7   )             
 
 where l is circumferential length of the clock track and N is total number of timing marks written on the track. 
 
         [0046]     This will result in near zero jitter of the clock track. However, due to the variation of the speed of the spindle motor during writing of the clock track, the distance between two adjacent timing marks will vary which results in written-in (repeatable) jitter of the clock track.  
         [0047]      FIG. 6  accordingly illustrates unequal distribution of the timing marks ct 0 , ct 1 , ct 2 , . . . caused by the jitter. If the value of correct distance between two timing marks is d, and if cd i =ct i −ct i-1  is a distance between two adjacent marks, then the position of the corrected timing mark jt i =i·d (i=1 . . . N−1) can be found by shifting the timing mark ct i  by distance Δcd i =(ct i −jt i ).  
         [0048]     Therefore, if the value of required compensation for each timing mark can be found, the written-in (repeatable) jitter can be compensated, and injected at summer  44 , in much the same way as cy i  is injected.  FIG. 7  accordingly illustrates a modified tracking circuit  40 ′, in the form of a PLL. Tracking circuit  40 ′, like tracking circuit  40  of  FIG. 4 , includes a phase detector  42 , a summer  44 , a low pass filter  46 , and a VCO  48 , processor  60 , and processor memory  62 .  
         [0049]     When tracking circuit  40  ( FIG. 4 ) is synchronized, the output y of VCO  48 , divided by divider  50  follows the reference clock signal y r  that is read-back from the disk. Now, the read-back reference clock signal y r  contains both written-in (repeatable) jitter and non-repeatable jitter. As noted, written-in (repeatable) jitter is caused by jitter that was introduced into the track during the writing process of the clock track. Non-repeatable jitter is mainly caused by the variation of the spindle motor speed during the reading process of the written clock track. Tracking circuit  40 ′ will follow both written-in (repeatable) and non-repeatable jitter of the clock track.  
         [0050]     Therefore, the reference clock signal, y r , generated from the clock track, can be represented as a sum of a jitter-free clock signal y f , a written-in (repeatable) jitter signal RRO(y r ), and a non-repeatable jitter signal NRRO(y r ): 
 
 y   r   =y   f   +NRRO ( y   r )+ RRO ( y   r )   (8) 
 
         [0051]     Now, written-in (repeatable) jitter RRO(y r ), may be found by measuring signal y m  proportional to this jitter at the output of phase detector  42  as shown in  FIG. 7 . Then, repeatable part RRO(y m ) of the measured signal y m  may be found by synchronous averaging of y m .  
         [0052]     Specifically, the relationship between the clock signal y r  and the measured signal y m  may be given by, 
 
 y   r =(1+ PC ) y   m    (9) 
 
 where C is the transfer function of the low pass filter  46  and P is the transfer function of the voltage-controlled oscillator (VCO). 
 
         [0053]     Hence, the written-in (repeatable) jitter RRO(y r ) of the clock track may be found as 
 
 RRO ( y   r )=(1+ PC ) RRO ( y   m )   (10) 
 
         [0054]     After substituting y f (i)=jt i =i·d, RRO(y r (i))=Δcd i , for i=1 . . . N−1, into equation (8) and (9),  
                 y   r     ⁡     (   i   )       =       i   ·   d     +       Δ   ⁢   cd     i     +     NRRO   ⁡     (       y   r     ⁡     (   i   )       )                 (   11   )                         y   m     ⁡     (   i   )       =       1     1   +   PC       ⁡     [         y   r     ⁡     (   i   )       -     i   ·   d       ]                   =       1     1   +   PC       ⁡     [         Δ   ⁢   cd     i     +     NRRO   ⁡     (       y   r     ⁡     (   i   )       )         ]                     (   12   )                       RRO   ⁡     (       y   m     ⁡     (   i   )       )       =       1   W     ⁢       ∑     w   =   1     W     ⁢       y   m     ⁡     (     i   ,   w     )                       =       1     1   +   PC       ⁡     [         Δ   ⁢   cd     i     +       1   W     ⁢       ∑     w   =   1     W     ⁢     NRRO   ⁡     (       y   r     ⁡     (   i   )       )             ]                   =       1     1   +   PC       ⁢     (       Δ   ⁢   cd     i     )                     (   13   )             
 
 where y m (i,w) is measured signal corresponding to the ct i -th timing mark at the w-th revolution and is sampled during W revolutions. 
 
         [0055]     Then compensation signal jy i  may be formed by measuring y m (i,w) for W revolutions. Processor  60  may then calculate jy i , for each timing mark t i . The calculated compensation signal jy i  may then be stored in memory for later use by clock compensation circuit  52 ′ and injected at summer  44 , as illustrated in  FIG. 7 .  
                     jy   i     =     RRO   ⁡     (       y   r     ⁡     (   i   )       )                   =       Δ   ⁢   cd     i                 =       (     1   +   PC     )     ⁢     RRO   ⁡     (       y   m     ⁡     (   i   )       )                     =       (     1   +   PC     )     ⁢     1   W     ⁢       ∑     w   =   1     W     ⁢       y   m     ⁡     (     i   ,   w     )                         (   14   )             
 
         [0056]     The overall transfer function of the system when the compensation signal jy i  is injected is given,  
             y   =         PC     1   +   PC       ⁢     y   r       -       PC     1   +   PC       ⁢     jy   i                 (   15   )             
 
 where y is divided output from VCO  48 . 
 
         [0057]     If jy i =RRO(y r ), then equation (15) becomes,  
                   y   =         PC     1   +   PC       ⁢     (       y   f     +     NRRO   ⁡     (     y   r     )       +     RRO   ⁡     (     y   r     )         )       -       PC     1   +   PC       ⁢     RRO   ⁡     (     y   r     )                       =       PC     1   +   PC       ⁢     (       y   f     +     NRRO   ⁡     (     y   r     )         )                     (   16   )             
 
         [0058]     As shown by equation (16), after compensation, the written-in (repeatable) jitter of the clock track will be cancelled out and VCO  48  will follow only the non-repeatable jitter caused mainly by spindle motor speed variation.  
         [0059]     Consequently, the divided output of VCO  48 , y, will not contain any written-in (repeatable) jitter and can be used as a reference to propagate jitter-free clock track on the disk.  
         [0060]     As will now be appreciated, as repeatable written in jitter and jitter resulting from incomplete track closure are additive, compensation circuits  52  and  52 ′ may be combined, and values cy i  and jy i  may be stored in memory  62 , and injected as components by a single compensation circuit  52  or  52 ′.  
         [0061]     During experimental tests written-in (repeatable) jitter of +/−0.2% was introduced into 1 MHz signal.  
         [0062]      FIG. 8A  illustrates the measured filtered error signal (VCO input signal y t ) before the compensation. Effect of written-in (repeatable) jitter is clearly visible, and since this signal represents input to VCO  48 , it will cause repeatable jitter of VCO output.  FIG. 8B  illustrates measured input signal y t  to VCO  48  after the compensation. The effect of written-in (repeatable) jitter is cancelled and PLL follows only the non-repeatable jitter.  
         [0063]      FIG. 9A  shows frequency histogram of the divided VCO output y before written-in (repeatable) jitter compensation and  FIG. 9B  after the compensation. Clearly, the written-in (repeatable) jitter was eliminated.  
         [0064]     Using tracking circuits  40  and  40 ′ and associated methods, a clock track with good closure and minimum written-in error can be propagated on the disk.  
         [0065]     Specifically, a clock track is written to a reference clock disk. The reference clock disk is subsequently used in MLSTW for the generation of the reference clock signal. When the reference clock disk is loaded on MLSTW each time a new set of blank disk is loaded, the offset of the reference clock disk will be different from the offset when the reference clock disk was written, and therefore the center of the written clock track will change. This will result in repeatable jitter of the read-back clock signal, as described above. This repeatable jitter may be compensated using tracking circuit  40 ′ and the associated method to ensure precise propagation of the servo patterns on the blank disks. This repeatable jitter is somewhat different from the written-in (repeatable) jitter described above, due to the variation of the speed of the spindle motor during writing of the clock track. The written-in (repeatable) jitter caused by the variation of the speed of the spindle motor when writing the clock track on the reference clock disk is already compensated during the writing process of the reference clock disk.  
         [0066]     Of course, the above described embodiments are intended to be illustrative only and in no way limiting. The described embodiments of carrying out the invention are susceptible to many modifications of form, arrangement of parts, details and order of operation. The invention, rather, is intended to encompass all such modification within its scope, as defined by the claims.