Abstract:
A semiconductor device is provided in which two adjacent cell lines extending in a word line direction are connected by one word line. Additionally, A semiconductor device comprising: word lines; bit lines which are disposed to cross the word lines; a plurality of cell lines extending in a word line direction; and a word line provided to share one cell line and the other cell line, of a pair of cell lines comprising two adjacent cell lines, wherein a distance between two adjacent cell lines in the pair of cell lines is smaller than a distance between two adjacent cell lines between one pair of cell lines and the other pair of cell lines.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a semiconductor device. 
         [0003]    Priority is claimed on Japanese Patent Application No. 2008-248720, filed Sep. 26, 2008, the content of which is incorporated herein by reference. 
         [0004]    2. Description of Related Art 
         [0005]    The chip size of semiconductor devices, particularly memory devices, has been reduced every year from the viewpoint of cost reduction. In DRAM (Dynamic Random Access Memory), a 4F 2 -cell structure has been proposed to satisfy this demand. 
       SUMMARY 
       [0006]    In one embodiment, there is provided a semiconductor device that includes at least: word lines; and bit lines which are disposed to cross the word lines, wherein two adjacent cell lines extending in a word line direction are connected by one word line. 
         [0007]    Moreover, in another embodiment, there is provided a semiconductor device that includes at least: word lines; bit lines which are disposed to cross the word lines; cell lines extending in a word line direction; and word lines provided to share one cell line and the other cell line, of a pair of cell lines comprising two adjacent cell lines, wherein a distance between two adjacent cell lines in the pair of cell lines is smaller than a distance between two adjacent cell lines between one pair of cell lines and the other pair of cell lines. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    The above features and advantages of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which: 
           [0009]      FIG. 1  is a plan view illustrating a cell transistor structure of a semiconductor device according to a first embodiment; 
           [0010]      FIGS. 2A to 2D  are views for explaining a layout of the semiconductor device according to the first embodiment,  FIG. 2A  is a plan view,  FIG. 2B  is a cross-sectional view taken along the line A-A′ shown in  FIG. 2A ,  FIG. 2C  is a cross-sectional view taken along the line B-B′ shown in  FIG. 2A , and  FIG. 2D  is a cross-sectional view taken along the line C-C′ shown in  FIG. 2A ; 
           [0011]      FIGS. 3A to 3G  are schematic cross-sectional views for explaining a method of producing the semiconductor device according to the first embodiment; 
           [0012]      FIGS. 4A and 4B  are plan views for explaining the forming of a capacitor of a semiconductor device according to a second embodiment; 
           [0013]      FIG. 5A  is a plan view illustrating the forming of a first contact hole of the semiconductor device according to the second embodiment, and  FIG. 5B  is a cross-sectional view taken along the line D-D′ shown in  FIG. 5A  to explain the forming of a first bit line; 
           [0014]      FIG. 6A  is a plan view for explaining the forming of a second contact hole of the semiconductor device according to the second embodiment, and  FIG. 6B  is a cross-sectional view taken along the line E-E′ shown in  FIG. 6A  to explain the forming of a second bit line; 
           [0015]      FIG. 7  is a plan view illustrating the known cell transistor structure in which 4F 2 -cell transistors are arranged in a word wiring direction; and 
           [0016]      FIGS. 8A to 8C  are views for explaining the known 4F 2  layout,  FIG. 8A  is a plan view,  FIG. 8B  is a cross-sectional view taken along the line F-F′ shown in  FIG. 8A , and  FIG. 8C  is a cross-sectional view taken along the line G-G′ shown in  FIG. 8A . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0017]    Before describing the present invention, the related art will be explained again in detail with reference to  FIGS. 7 ,  8 A,  8 B and  8 C, in order to facilitate the understanding of the present invention. 
         [0018]    Several kinds of 4F 2 -cell structures have been proposed up to now. For example,  FIG. 7  shows a schematic plan view of a cell transistor structure  150  having cell lines  152  where the known 4F 2 -cell transistors  151  are arranged in a word wiring direction. More specifically, as shown in  FIGS. 8A to 8C , there is a cell transistor structure  151  in which an oxidized gate film  102  is formed in an outer periphery of a silicon post  101  having a lengthwise ratio and a breadthwise ratio different from each other and word lines  103 A and  103 B are magnetically and conformably formed by an etch-back process after forming a gate electrode  103 . In Japanese Unexamined Patent Application, First Publication, No. 2004-96095, a layout is disclosed in which memory cells arranged in two lines are driven by one word line. 
         [0019]    The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes. 
         [0020]    Hereinafter, a semiconductor device according to the present invention will be described with reference to the drawings. 
         [0021]    In the drawings used in the following description, specific parts may be enlarged for convenience to easily represent characteristics. Dimensions, ratios, and the like of constituent elements may not be equal to the actual ones. Materials, dimensions, and the like in the following description are examples, and the present invention is not limited thereto. The present invention may be appropriately modified within the scope of the invention. 
       FIRST EMBODIMENT 
       [0022]    In the embodiment, a case of applying the present invention to cell transistors arranged on a silicon substrate will be described by way of example. 
         [0023]      FIGS. 1 and 2A  are plan views illustrating a semiconductor device on which cell transistors are arranged according to the first embodiment. As shown in  FIGS. 1 and 2A , in a semiconductor device  50  according to the embodiment, cell lines (L 4n+1  to L 4n+4 ) extend in word lines  3 A and  3 B, and two adjacent cell lines (L 4n+1  and L 4n+2 , or L 4n+3  and L 4n+4 ) are connected by one word line  3 A or  3 B. Here, “n” in the transcription of the cell lines indicates an integer. 
         [0024]    More specifically, in the 4F 2  arrangement of the cell transistors  51  in the extending direction of the word lines  3 A and  3 B of the semiconductor device  50 , the cell line L 4n+2  (line 4n+2 ) and the cell line L 4n+3  (line 4n+3 ) are shifted in the extending direction of the word line  3  by a width F of a minimum process dimension. The cell line L 4n+2  and the cell line L 4n+3  are shifted in the direction of the cell line L 4n+1  (line 4n+1 ) and the cell line L 4n+4  (line 4n+4 ) by the width F, thereby connecting the cell line L 4n+1  and the cell line L 4n+2  by the same word line  3 A and connecting the cell line L 4n+3  and the cell line L 4n+4  by the same word line  3 B. 
         [0025]    As described above, one of the adjacent cell lines is shifted, thereby constituting a pair of cell lines  2 L 2+1  and a pair of cell lines  2 L 2+2  sharing the word lines  3 A and  3 B. In the pair of cell lines, the cell transistors  51  of two adjacent cell lines are disposed in a zigzag formation. 
         [0026]    For example, longitudinal MOS transistors can be applied as the cell transistors  51  according to the embodiment, as shown in  FIGS. 2A to 2D . 
         [0027]    The cell transistor  51  at least includes a silicon post  1  and a gate electrode  3  coating a side face of the silicon post  1  through a gate insulating film  2 . More specifically, the gate insulating film  2  is formed in a periphery of the silicon post  1  having a lengthwise ratio and a breadthwise ratio different from each other, and it is covered with the gate electrode  3 . The cell transistor  51  has one impurity diffusion layer area (not shown) that becomes a source diffusion layer or a drain diffusion layer at an upper part of the silicon post  1 , and has another impurity diffusion layer area (not shown) that becomes a source diffusion layer or a drain diffusion layer at a lower part of the silicon post  1 . 
         [0028]    As shown in  FIG. 2A , the silicon posts  1  of the cell line L 4n+2  and the cell line L 4n+3  are shifted in the extending direction of the word lines  3 A and  3 B by the width F of the minimum process dimension. The cell line L 4n+2  is shifted to the cell line L 4n+1 , and the cell line L 4n+3  is shifted to the cell line L 4n+4 . Accordingly, a distance a between two adjacent cell lines (e.g., cell line L 4n+1  and cell line L 4n+2 , cell line L 4n+3  and cell line L 4n+4 ) in one pair of cell lines is smaller than a distance b between two adjacent cell lines (e.g., cell line L 4n+2  and cell line L 4n+3 ) between the pair of cell lines and the pair of cell lines ( 2 L 2n+1  and  2 L 2n+2 ). 
         [0029]    The silicon posts  1  having such a layout are applied as the cell transistors  51 . Accordingly, in the semiconductor device  50 , the gate electrodes  3  of the cell transistors  51  in the pair of cell lines (e.g.,  2 L 2n+1 ,  2 L 2n+2 ) are integrated to constitute each of the word lines  3 A and  3 B. 
         [0030]    As shown in  FIGS. 2B to 2D , a thickness of the gate insulating film  2  between the pair of cell lines and the pair of cell lines (e.g., between  2 L 2n+1  and  2 L 2n+2 ) is larger than that within the pair of cell lines. That is, an area where the distance between the silicon posts  1  is large is thicker than an area where the distance is small. 
         [0031]    Next, a method of producing the semiconductor device according to the embodiment will be described. 
         [0032]    First, a silicon post  1  is formed. As shown in  FIG. 3A , the silicon post  1  is formed by forming an oxide film  6  and a nitride film  7  on a semiconductor substrate  5 . The nitride film  7  is patterned to have a layout of the silicon post  1  as shown in  FIG. 2A . Subsequently, the silicon post  1  is formed by the patterned nitride film  7  as a mask. 
         [0033]    Then, a thick oxide film is formed on the surface of the semiconductor substrate  5  at the lower part of the silicon post  1 . First, an oxide film  8  and a nitride film are formed to cover the silicon post  1 , the oxide film  6 , and the nitride film  7  formed in  FIG. 3A . Next, as shown in  FIG. 3B , an etch-back process of the nitride film is performed until the oxide film  8  at the lower part of the silicon post  1  is exposed, and a side wall nitride film  9  is formed on the side wall of the silicon post  1 . 
         [0034]    Then, as shown in  FIG. 3C , silicon under the exposed oxide film  8  is selectively thermal-oxidized, thereby forming a thick oxide film  10 . 
         [0035]    At that time, from the difference of the thermal-oxidized area, in  FIGS. 2B to 2D , the thickness of the oxide film between the pair of cell lines and the pair of cell lines (e.g., between  2 L 2n+1  and  2 L 2n+2 ) becomes large as compared with that within the pair of cell lines. Accordingly, it is possible to increase an etch-back margin at the time of forming the gate electrode  3 . 
         [0036]    Next, as shown in  FIG. 3D , the oxide film  8  covering the side wall nitride film  9  and the silicon post  1  is removed. Then, as shown in  FIG. 3E , a gate insulating film  2  formed of an oxide film is formed on a side face of the silicon post  1 . 
         [0037]    Finally, a gate electrode  3  and a word line are formed. First, for example, poly silicon is formed on the whole side face of the silicon post  1  through the gate insulating film  2 . Then, as shown in  FIG. 3F , the gate electrode  3  is formed by the etch-back process. That is, at the same time of forming the gate electrode  3 , one word line (word lines  3 A and  3 B shown in  FIG. 2A ) is magnetically and conformably formed with respect to two lines (e.g. cell line L 4n+1  and cell line L 4n+2 , or cell line L 4n+3  and cell line L 4n+4  shown in  FIG. 2A ) of the silicon posts  1 . In other words, the gate electrodes  3  of the cell transistors  51  of one pair of cell lines are integrated to form the word lines  3 A and  3 B. As described above, the semiconductor device  50  according to the embodiment is formed. 
         [0038]    According to the semiconductor device  50  according to the embodiment, two adjacent cell lines (cell line L 4n+1  and cell line L 4n+2 , or cell line L 4n+3  and cell line L 4n+4 ) are connected by one word line  3 A or  3 B, and thus it is possible to widen the areas of the word lines  3 A and  3 B. Accordingly, it is possible to increase the distance between the word lines  3 A and  3 B. Therefore, it is possible to reduce resistance of the word lines and it is possible to reduce capacitance of the word lines. 
         [0039]    When the resistance is estimated by the schematic diagram of the known layout as shown in  FIG. 7  and the schematic diagram of the layout of the present invention as shown in  FIG. 1 , the area is doubled, resistance per unit length is reduced by ½, and the number of bits included in the unit length is doubled. Accordingly, resistance per 1 bit can be estimated as ¼. The distance from the adjacent word line is doubled, and thus it is possible to reduce the capacitance of the word line by ½. 
       SECOND EMBODIMENT 
       [0040]    Next, a second embodiment of the invention will be described. 
         [0041]    In the embodiment, for example, a case of applying the invention to a layout method of memory cells arranged on a silicon substrate will be described by way of example. 
         [0042]    As shown in  FIGS. 3G ,  4 A, and  4 B, in a semiconductor device according to the embodiment, schematically, capacitors are formed on the cell transistors  51  constituting the semiconductor device  50  according to the first embodiment, and bit lines connected onto the capacitors are formed so that distances from the surface of the semiconductor substrate are different (i.e., layers are different) from one another for each cell line. 
         [0043]    Specifically, as shown in  FIG. 3F , a part of the mask nitride film  7  is removed, and a cell contact  11   a  is formed. As shown in  FIGS. 3F and 4A , a capacitance contact pad  11  is formed on the cell contact  11   a.  In this case, the central position of the capacitance contact pad  11  of each cell line slightly deviates from the central position of the upper face of the silicon post  1  in the plan view. That is, as shown in  FIG. 4A , the silicon posts  1  are formed to deviate toward the opposite side from the silicon posts  1  of the adjacent cell, line in the same pair of cell lines. 
         [0044]    As shown in  FIG. 4B , a capacitor  12  including an upper electrode  12 A, a dielectric substance  12 B, and a lower electrode  12 C is formed on the capacitance contact pad  11 . In this case, an upper face  12   a  of each capacitor  12  is provided so that the capacitor  12  of any cell line is at the same height (i.e. the same layer) from the surface of the semiconductor substrate. 
         [0045]    Next, an interlayer insulating film  19  is formed to cover all the cell lines. As shown in  FIG. 5A , a part of the interlayer insulating film  19  on the adjacent cell lines (L 4n+2  and L 4n+3 ) between the adjacent pairs (e.g.,  2 L 2n+1  and  2 L 2n+2 ) of cell lines is opened to form a first contact hole  13  for the upper face  12   a  of the capacitor  12 . Then, as shown in  FIG. 5B , a first bit contact  14  and a first bit line  15  are formed. 
         [0046]    Next, as shown in  FIG. 5B , an interlayer insulating film  20  is formed so as to cover the first bit line  15 . In this case, as shown in  FIG. 6A , the cell line L 4n+1  and the cell line L 4n+4  are adjacent to a cell line L 4(n−1)+4  and a cell line L 4(n+1)+1  (not shown), respectively. Accordingly, in the same manner as the first contact hole  13 , part of the interlayer insulating film  20  on the adjacent cell lines (e.g., L 4(n−1)+4  and L 4n+1 ) between the adjacent pairs (e.g.,  2 L 2(n−1)+2  and  2 L 2n+1 ) of cell lines is opened to form a second contact hole  16  for the upper face  12   a  of the capacitor  12 , Then, as shown in  FIG. 6B , a second bit contact  17  and a second bit line  18  are formed. 
         [0047]    Accordingly, as shown in  FIG. 6B , the semiconductor device is formed so that the second bit line  18  of one cell line (e.g., L 4n+1 ) of the pair of cell lines and the first bit line  15  of the other cell line (e.g., L 4n+2 ) are provided at layers having different heights from the capacitor  12  of the pair of cell lines. 
         [0048]    According to the semiconductor device according to the second embodiment, in the first embodiment, as shown in  FIG. 2A , the adjacent cell lines (e.g., L 4(n−1)+4  and L 4n+1 ) between the adjacent pairs (e.g.,  2 L 2(n−1)+2  and  2 L 2n+1 ) of cell lines are shifted by the same width F, and thus commonality of contact for the adjacent cell lines (e.g., L 4   (n−1)+4  and L 4n+1 ) between the pairs (e.g.,  2 L 2(n−1)+2  and  2 L 2n+1 ) of cell lines with respect to the capacitance upper electrode  12  becomes possible. 
         [0049]    In the first embodiment and the second embodiment, the adjacent bit lines are formed of layers. 
         [0050]    According to the semiconductor device of the present invention, two adjacent cell lines are connected by one word line. Accordingly, it is possible to widen the area of the word line, and to increase the distance between the word lines. Therefore, it is possible to reduce the resistance of the word lines and to reduce the capacitance between the word lines. 
         [0051]    It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.