Abstract:
A regulator circuit for providing a regulated voltage, comprises a driver for generating a drive signal, and a charge pump having a first voltage input coupled to a first voltage source, being responsive to the drive signal, to generate a pump voltage from the first voltage source. An amplifier having a reference input is coupled to a reference voltage, a sense input is coupled to a sense signal representative of the pump voltage, and an output is operable in response to a difference between the reference voltage and the sense signal, to control the driver. A switch is coupled from the amplifier output to an output of the charge pump such that the pump voltage is controllably boosted by the amplifier output through the switch.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to charge pump circuits, and in particular to charge pump circuits that provide a regulated output voltage. 
     2. Discussion of the Related Art 
     A charge pump circuit is generally used for boosting a power supply voltage to a higher voltage level to be used for powering ancillary circuits. Closed loop control is sometimes used with charge pumps to provide a regulated output voltage. However, charge pumps that include closed loop control typically have extremely slow response times due to the relatively small amount of energy that can be transferred during each clock cycle. 
     SUMMARY OF THE INVENTION 
     The present invention provides a circuit and method having a fast response time for generating a regulated voltage from a first voltage of a first voltage source. The circuit includes a driver for generating a drive signal. The driver includes a clock input for receiving a clock signal. A charge pump that has a first voltage input coupled to the first voltage source. In response to the drive signal, the charge pump provides a pump voltage that is boosted from the first voltage. An amplifier has a reference input coupled to a reference voltage, a sense input coupled to a sense signal representative of the pump voltage, and an output. The amplifier is operable in response to a difference between the reference voltage and the sense signal, to control the driver. A switch is coupled from the amplifier output to an output of the charge pump such that the pump voltage is controllably boosted by the amplifier output through the switch. 
     For a more complete understanding of the invention, its objects and advantages, reference may be had to the following specification and to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a block diagram of a fast change charge pump regulator circuit in accordance with the teachings of the invention; and 
     FIG. 2A illustrates a timing diagram associated with a presently preferred embodiment of the invention; 
     FIG. 3 illustrates an expanded view of the timing diagram illustrated in FIG.  2 A: 
     FIG. 3A illustrates a prior art charge pump; 
     FIG. 3B illustrates another prior art charge pump; 
     FIG. 4 illustrates a block diagram of an embodiment of a voltage regulating circuit in accordance with the teachings of the invention; 
     FIG. 5 illustrates a timing diagram associated with another embodiment of the invention; and 
     FIG. 6 illustrates a block diagram of an alternative embodiment of a voltage regulating circuit in accordance with the teachings of the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 1, illustrated is a presently preferred embodiment of a fast change charge pump regulator circuit  10  constructed in accordance with the principles of the present invention. The regulator circuit  10  converts power from a voltage source to a regulated output. The present invention is particularly suitable when incorporated into a semiconductor device  11  for providing power to on-chip circuitry such as an output driver stage  13 . While the present invention is shown and described as being incorporated into a semiconductor device  11 , it will be appreciated that the circuit and method may be embodied in a variety of devices including a combination of discrete devices, an application specific integrated circuit, and a field programmable array. The regulator circuit  10  includes a charge pump circuit  12  for boosting voltage from a voltage source, V DD . High frequency components in the boosted voltage are attenuated by a filter  14 . The filtered voltage is used to drive a voltage buffer  16  that converts power from another voltage source, V S , to an output voltage, V O , that is proportional to the voltage level of the filtered voltage. A sense circuit  18  couples a voltage corresponding to the output voltage to the input of an amplifier  20 . The sense circuit  18  in the preferred embodiment is a direct connection to the output of the voltage buffer  16 . However, as those skilled in the art will readily recognize, the scope invention encompasses other sense circuits such as resistor divider networks. The amplifier  20  compares the sense voltage to a reference voltage that is coupled to another input of the amplifier  20 . An error signal is generated by the amplifier  20  based upon the comparison of the sense voltage and reference voltage. The output of the amplifier  20  is coupled to a driver  22  and a switch  24 . The driver  22  generates a pulsed drive signal to drive the charge pump  12 . The driver  22  in the presently preferred embodiment is an AND gate. However, any suitable device for driving the input of the charge pump circuit  12  is within the scope of the invention, such as devices having push-pull and totem-pole outputs. The switch  24  provides a controlled feedforward path during start-up and transient load/line conditions for quickly driving the input to the voltage buffer  16  up to a voltage level that is less than the steady-state boosted voltage. A switch controller  26  may additionally be included. The switch controller  26  controls the operation of the switch  24  based upon a predetermined switching criteria such as the voltage level of the output voltage, the operating mode of the regulator  10 , and the duration of operation. 
     The charge pump circuit  12  boosts power coupled from a voltage source, V DD , to a power input  28 , up to an unregulated output voltage ranging in value from V DD  to 2*V DD . The operation of the charge pump circuit  12  is controlled by the drive signal which is coupled to a drive input  30 . The drive signal is typically a pulsating waveform that alternately causes energy to be cycled into a series capacitor, and then out of the series capacitor into a storage capacitor. The output voltage of conventional charge pump circuits varies with the duty cycle and frequency of the drive input, the voltage level of V DD , the voltage level of the driver output, capacitor values, and load. The scope of the invention encompasses using all known unregulated charge pump circuits within the described system and method. Two such conventional charge pump circuits are illustrated in FIGS. 3A and 3B. 
     Referring to FIG. 3A, a single stage charge pump circuit  12   a  is illustrated. The charge pump circuit  12   a  includes a series capacitor  32 , storage capacitor  34 , and coupling diodes  36  and  38 . In operation, when the drive signal is in the low state, energy from V DD  is stored in the series capacitor  32  charging the capacitor  32  up to V DD . Then, when the drive signal transitions to the high state, the summation of the energy stored in the series capacitor  32  and energy provided by the drive signal is transferred through the coupling diode  38  charging up the storage capacitor  34 . The peak voltage level stored in the storage capacitor  34  is approximately the voltage amplitude of the drive signal plus the voltage of the series capacitor  32 . The scope of the invention also includes charge pump circuits that employ mode control circuitry for controlling the charge rate of the charge pump. Mode control circuitry typically consists of a transistor-capacitor series combination that is coupled across either the series capacitor  32  or the storage capacitor  34 . The series combination is switched into or out of the circuit to vary the charging rate of the circuit. 
     Referring to FIG. 3B, a multistage charge pump circuit  12   b  is illustrated. The charge pump circuit  12   b  uses two clock signals to permit multiple boost stages  40  to be series connected. A series capacitor  42  is included in each of the boost stages. A single storage capacitor  44  is coupled to the output of the charge pump circuit  12   b.    
     Again referring to FIG. 1, the filter  14  employed in the presently preferred embodiment is a low pass filter comprised of a resistor and capacitor. Although a discrete capacitor is used, it is within the scope of the invention to use the parasitic capacitance of the voltage buffer  16 , or to not include the filter  14 . The scope of the invention also includes using other low pass filters such as an inductor-capacitor filter. 
     In the presently preferred embodiment, the voltage buffer  16  is an NMOS transistor configured as a voltage follower. The scope of the invention additionally includes using other well known voltage buffer circuits such as bipolar transistors configured as voltage followers. 
     Although a single amplifier  20  is employed to drive both the driver  32  and the switch  24 , it is within the scope invention to provide a separate amplifier  21  to drive each device. The separate amplifier  21  may for example be a voltage buffer such as a voltage follower coupled between the output of the amplifier  20  and the switch  24  or the separate amplifier  21  may be coupled from the inputs of the amplifier  20  to the switch  24 . Employing a separate amplifier  21  provides design flexibility permitting different voltage levels to be supplied to the amplifier  20  and separate amplifier  21 . 
     The switch  24  in the presently preferred embodiment is an NMOS FET being employed as an active switch that is controlled by the switch controller  26 . The scope of the invention encompasses using other active switches such as bipolar transistors, CMOS FETs, and analog muxes. In addition, the scope of the invention includes using passive switches such as diodes. When a diode is used for example, the source voltage to the amplifier  20  is selected to be less than the normal output operating voltage of the charge pump circuit  12 , thereby providing a low impedance path for energy to charge the charge pump circuit output to a voltage level below the regulation point. 
     Referring to FIG. 2A, timing waveforms associated with the operation of the regulator circuit  10  are illustrated. At initial turn-on of the regulator  10 , the switch controller  26  drives the switch  24  to the closed state. Energy from the amplifier  20  is coupled through the switch  24 , directly to the output of the filter  14 . The filter output quickly ramps up to a voltage level slightly below the regulation point of the regulator circuit  10 . The switch controller  26  then drives the switch  24  to the open state, decoupling the direct connection of the amplifier  20  to the filter output. The output of the filter  14  is then charged up to the regulation point through the combination of the driver  22  and the charge pump circuit  12 . 
     Referring to FIG. 2B, an expanded view of the timing signals illustrated in FIG. 1 is shown. The transition of the output voltage, Vo, from initial start-up mode to steady-state mode operation is shown at point A. During steady-state operation, the driver  22  generates the drive signal in response to an error signal from the amplifier  20 , and the clock signal. When the sensed voltage corresponding to Vo is less than the reference voltage, Vref, the error signal is high, causing the driver  22  to enable the driver signal. The active driver signal causes the charge pump circuit  12  to transfer energy to the output, boosting the voltage level of Vo, until the sensed voltage exceeds Vref. When the sensed voltage exceeds Vref, the error signal transitions low, disabling the driver signal, thereby interrupting further boosting of the voltage level of Vo. 
     Referring to FIG. 4, a cascode circuit  40  is illustrated. The cascode circuit  40  includes two or more cascode connected regulator circuits  10 . In the presently preferred embodiment, three regulator circuits  10  are coupled in the cascode string. 
     The cascode circuit  40  provides an output voltage, VOUT N , in which the ripple amplitude is reduced. Preferably, the clock signals for the regulator circuits  10  are phase-shifted, so that the ripple voltage from all of the stages does not have a cumulative effect on the output. Phase-shifting the clock signals also increases the ripple frequency, improving the effectiveness of post-filtering that is applied to the output voltages. Also, the cascode circuit  40  may provide intermediate output voltages, VOUT n , from each of the regulator circuits. 
     A first regulator circuit  10   a  generates an output voltage, VOUT 1 , from a supply voltage, Vs. The first regulator circuit  10   a  is powered from V DD . The output voltage, VOUT 1 , is coupled to a second regulator circuit  10   b . The operation of the first regulator circuit  10   a  is similar to that described above with the addition that the output voltage is cascode connected to the second regulator circuit  10   b.    
     The second regulator circuit  10   b  uses VOUT 1  to supply power to the voltage buffer  16 . In a manner similar to the first regulator circuit  10   a , the second regulator circuit  10   b  is powered from V DD  and generates an output voltage, in this case VOUT 2 , from the voltage, VOUT 1 , supplied to the voltage buffer  16   b . In addition, VOUT 2  is coupled to a third regulator circuit  10   c  in the cascode string. 
     The third regulator circuit  10   c , in a manner similar to the operation of the first and second regulator circuits, is powered by V DD  and generates an output voltage, in this case, VOUT 3 , from the voltage supplied to the voltage buffer  16   c . The output voltage, VOUT 3 , is the final regulated voltage from the cascode circuit  40 . 
     Although, in the presently preferred embodiment of the invention each of the regulator circuits is powered from a combination of V DD  and Vs, it is within the scope of the invention to provide different interconnect schemes for the output voltages such as powering successive regulator circuits with the voltage generated in the preceding regulator circuit, as well as coupling the output voltage from a successive regulator circuit, back to a preceding regulator circuit. 
     A sequence control circuit  42  controls the switch  24  in each of the regulator circuits. The outputs from each of the regulator circuits  10 , as well as an enable signal  41  are coupled to the sequence control circuit  42 . The sequence control circuit  42  opens the switches  24  sequentially based on the voltage level of each output voltage. The scope of the invention also encompasses other criteria for controlling the switches such as the voltage level of a single output voltage, transferred energy, or a time based criteria including delaying a predetermined amount of time after enabling the corresponding switch. In addition, switch control can be executed independently within each regulator circuit. Also within the scope of the invention is using a passive switch such as a diode instead of an active switch. 
     Referring to FIG. 5, waveforms of signals associated with the cascode circuit  40  are illustrated. The first waveform is the ENABLE signal. The next three waveforms, VOUT 1 , VOUT 2 , and VOUT 3 , illustrate the output voltages of the regulator circuits during start-up of the cascode circuit  40 . With specific reference to the waveform of VOUT 3 , the voltage ramps up at a different rate during each of the four indicated operating states. At initial start-up, VOUT 3  ramps up at its fastest rate as each of the regulator circuits is in a fast charge mode. When the first regulator  10   a  transitions out of the fast charge mode, the rate of change of VOUT 3  decreases. Likewise, when the second regulator  10   b  and the third regulator  10   c  each transition out of the fast charge mode, the rate of change of VOUT 3  again decreases. 
     Waveforms S 1 , S 2 , and S 3  illustrate the operation of the switches within the regulator circuits. The sequence control circuit  42  opens each switch as the voltage level for the associated regulator circuit reaches a predetermined level. 
     Referring to FIG. 6, another embodiment in accordance with the principles of the invention is illustrated. This embodiment is similar to the cascode circuit  40  with the exception that the second and successive regulator circuits use the output voltage from preceding stages to power the charge pump  12 , and the output drive stages of the driver  22  and amplifier  20 , as well as the voltage buffer  16 . Using this configuration, the voltage level of VOUT N  is not limited by the voltage level of V DD . Instead, to obtain higher output voltages, additional regulator circuits  10  are added to the cascode string. 
     Thus it will be appreciated from the above that as a result of the present invention, a circuit and method for regulating a voltage is provided by which the principal objectives, among others, are completely fulfilled. It will be equally apparent and is contemplated that modification and/or changes may be made in the illustrated embodiment without departure from the invention. Accordingly, it is expressly intended that the foregoing description and accompanying drawings are illustrative of preferred embodiments only, not limiting, and that the true spirit and scope of the present invention will be determined by reference to the appended claims and their legal equivalent.