Abstract:
A hybrid digital pulse width modulator (DPWM) with digital delay-locked loops (DLLs) is provided. In this implementation, the digital pulse-width-modulator is synthesizable and includes a digital delay-locked loop around a delay-line to achieve constant frequency clocked operation. In this implementation, the resolution of the modulator is consistent over a wide range of process or temperature variations. The DPWM may implement trailing-edge, leading-edge, triangular, or phase-shift modulation. In an implementation suitable for DC-DC converters with synchronous rectifiers, for example, the DPWM may include two or more outputs for programmable dead-times. In another implementation, a digital pulse-width-modulator with a digital phase-locked loop is also provided.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. provisional application No. 60/944,483, filed 15 Jun. 2007, which is hereby incorporated by reference as though fully set forth herein. 
    
    
     BACKGROUND 
     a. Field 
     The instant invention relates to a digital pulse-width-modulator comprising a discretely adjustable delay line. 
     b. Background 
     Pulse-width-modulation (PWM) is a technique for controlling analog circuits with a digital output in which a duty cycle of a square wave is modulated to encode a specific input signal to a pulse-width modulator. PWM is employed in a wide variety of applications, ranging from measurement and communications to power control and conversion. 
     High resolution, high frequency digital pulse-width modulators (DPWM) can be used to control DC-DC converters and achieve features such as high bandwidth, precise regulation or elimination of limit cycling disturbances. In Syed, A et al., “Digital pulse-width modulator architectures,” IEEE PESC 2004, pp. 4689-95, Vol. 6 (2004), for example, different structures of DPWM topologies are discussed and compared. 
     The direct implementation of an analog pulse-width-modulator in the digital domain is a counter-based DPWM. An n-bit counter counts up by one step at each input clock period, t clk . When the counter counts to its period length, it resets itself and starts counting from the zero value at the next input clock period t clk . In such a counter-based DPWM, the required clock frequency is directly dependent on the number of bits of the counter, n, and the desired switching frequency, f sw =1/T s  as shown in the following formula.
 
f clk =2 n f sw   (1)
 
     The advantage of a counter-based DPWM is its simplicity and linearity. For a reasonable DPWM resolution, however, the number of bits of the counter, n, is large in value. Therefore, the required clock frequency f clk  can be unreasonably high. In a 10-bit DPWM implementation with a switching frequency f sw =1 MHz, for example, the required clock frequency, f clk  is approximately 1 GHz. This makes the implementation of a high-resolution, high-frequency counter-based DPWM a difficult task. 
     Another implementation of a DPWM is a delay-line DPWM. In a pure delay line DPWM, a delay line is used to resolve the output modulated signal. While a high resolution pure delay line DPWM requires a relatively larger area and more hardware resources than a counter-based DPWM, the pure delay line DPWM can be operated with a much lower clock frequency than a counter-based DPWM. 
     A hybrid DPWM is a compromise between a high clock frequency of a counter-based DPWM and a large area requirement of a pure delay line DPWM. A hybrid DPWM, for example, provides a high resolution, high frequency DPWM without a need for a relatively high input clock frequency, as in a counter-based DPWM, or a relatively large area, as in a pure delay-line based DPWM. 
     Different topologies of hybrid DPWM have been introduced, such as a ring-oscillator DPWM without any external clock and open-loop delay-line DPWM with an external clock. A hybrid DPWM with an open-loop delay-line is based on a combination of a counter and a delay-line. The counter, for example, may provide a most-significant-bit (msb) or a least-significant-bit (lsb) portion of the duty cycle of the modulator.  FIG. 1  shows an example of a hybrid DPWM  10 , with a counter  12  and an open-loop delay line  14 . The DPWM, in this example, is a 5-bit DPWM with a three-bit counter providing a three msb portion  16  of a duty cycle command and a two-bit delay line providing a two-bit lsb portion  18  of the duty cycle command. 
     As shown in  FIG. 1 , the counter  12  is an n-bit counter that counts at each clock period of the clock input signal, clk, to provide a counter output, cnt. The counter output cnt is compared to the three-bit msb portion  16  of the duty cycle command at a comparator  20 . An output of the comparator  20 , delclk, is provided to the open-loop delay-line  14 . The number of delay cells, L, required in the delay-line  14  depends upon the number of bits provided by the delay-line, l, in the hybrid DPWM. In this example, the delay-line provides l=2 bits of the duty cycle command, and the number of delay cells required L=2 1 =2 2 =4. Thus, the open-loop delay-line  14  includes four sequential delay cells del 0 , del 1 , del 2 , and del 3 . 
     An L:1 multiplexer  22  taps the nodes after each of the delay cells del 0 , del 1 , del 2 , and del 3  at inputs i 0 , i 1 , i 2 , and i 3 , respectively. The multiplexer  22  receives the two-bit lsb portion  18  of the duty cycle command and uses that portion to select one of the inputs connect the appropriate input i 0 , i 1 , i 2 , or i 3  to the output R. The output R of the multiplexer  22  is then provided to a flip-flop  24  that then provides an output, DPWM_out. 
     A counter stage comprises the counter  12  and the comparator  20 . The delay-line stage comprises the delay-line  14 , the multiplexer  22 , and the flip-flop  24 . 
       FIG. 2  shows a timing diagram for the hybrid DPWM  10  shown in  FIG. 1 . In this example, the clock input signal clk is shown at the top of the timing diagram. The counter output cnt is shown just below the clock input signal clk and provides a three-bit binary counter starting at 000 and resetting itself after eight clock cycles at 111. In the example shown in  FIG. 2 , the duty cycle command, duty, received by the hybrid DPWM  10  is duty=10110. Thus, the three-bit msb portion  16  is msb(duty)=101 and the two-bit lsb portion  18  is lsb(duty)=10. 
     As described above, the counter output cnt is compared to the three-bit msb portion  16  of the duty cycle command msb(duty) at the comparator  20  to provide the resulting delclk signal shown in the timing diagram of  FIG. 2 . The width of the delclk signal is equivalent to one clock period of the input clock signal clk. The signal delclk is then propagated through the delay-line  14 . The output of each delay cell is tapped out and connected to the L:1 multiplexer  22 . The propagated signals i 0 -i 3 , from the output of the delay cells del 0 -del 3  are also shown in the timing diagram of  FIG. 2 . In this example, the lsb portion of the duty cycle command lsb(duty)=10 (i.e., binary 2). Thus, the input i 2  of the multiplexer  22  is selected and connected to the output R of the multiplexer. The signal R resets the output DPWM_out of the flip-flop  24 . 
     The frequency of the output signal DPWM_out of the hybrid DPWM  10  is still determined by the formula (1) f clk =2 n f sw  given above, where n is the number of bits of the counter. Because a smaller n is used in a hybrid DPWM, the required input clock frequency is lower in value for a hybrid DPWM compared to a counter-based DPWM even though it provides the same DPWM resolution. In the example of  FIGS. 1 and 2 , for example, the required input clock frequency is four times smaller than an equivalent counter-based DPWM. 
     Digital Pulse-Width-Modulators with delay lines are used in many applications. In DC-DC power converters, for example, digital controllers include custom architectures and realizations of building blocks including high-resolution, high-frequency, digital pulse-width modulators (DPWM), simplified discrete-time compensator schemes, and analog-to-digital (A/D) converters. Digital controllers can also offer advantages of lower sensitivity to parameter variations, programmability, and reduction or elimination of passive components, often without compromising dynamic performance, simplicity, or cost. 
     BRIEF SUMMARY 
     Even for a very careful delay line design, delays of individual cells within the delay line vary with process, temperature, and input voltage variations. Such changes in the duration of delays introduced by the delay line, for example, can affect the operation of a pulse-width-modulator in which the delay line is used, such as by introducing non-linear and non-monotonic behavior. 
     One or more discretely adjustable delay cells can be used to adjust the delay through the delay line. In addition, an active control scheme can be used to control the delay through at least one individual delay cell of the delay-line. A delay of at least one delay cell in the delay line can be controlled in order to account for such variances, however. 
     In one implementation, a controllable delay line may be used to guarantee monotonic and near optimum behavior of a DPWM including a delay line (e.g., a hybrid or pure delay line DPWM). In this particular implementation, the total delay of the delay line can be controlled to be approximately equal to one clock period of the input clock. 
     In another particular implementation, a hybrid digital pulse width modulator (DPWM) with digital delay-locked loops (DLLs) is provided. In this implementation, the digital pulse-width-modulator is synthesizable and includes a digital delay-locked loop around a delay-line to achieve constant frequency clocked operation. In this implementation, the resolution of the modulator is consistent over a wide range of process or temperature variations. The DPWM may implement trailing-edge, leading-edge, triangular, or phase-shift modulation. In an implementation suitable for DC-DC converters with synchronous rectifiers, for example, the DPWM may include two or more outputs for programmable dead-times. The DPWM may further be implemented in FPGA or custom chip modules. 
     In another implementation, a digital pulse-width modulator is provided. The digital pulse-width modulator comprises a delay line, a multiplexer, and a controller. The delay line comprises an input for receiving an input signal and a plurality of delay cells connected in series. The plurality of delay cells comprises at least two discretely adjustable delay cells, and the delay line is configured to propagate the input signal through the plurality of delay cells. The multiplexer comprises a plurality of inputs and an output. Each of the plurality of inputs of the multiplexer is coupled to an output of one of the plurality of delay cells of the delay line. The output of the multiplexer is selected from the plurality of inputs of the multiplexer based upon at least a portion of a duty cycle command. The controller is coupled to outputs of at least two delay cells in the delay line. The controller samples the outputs at the end of a reference period to obtain a first sampled discrete value and a second sampled discrete value. The controller further compares the first discrete value to the second discrete value and determines a digital control code for discretely and independently adjusting a delay of the discretely adjustable delay cells based upon the comparison of the first discrete value to the second discrete value. 
     In yet another implementation, a hybrid digital pulse-width-modulator (DPWM) is provided. The hybrid DPWM comprises a counter stage, an adjustable delay line stage, a multiplexer, and a controller. The counter stage comprises a counter for providing a count signal, and a comparator coupled to the counter to receive the count signal. The comparator is configured to receive a first portion of a duty cycle command and to provide a counter stage output signal based on the count signal and the first portion of the duty cycle command. The adjustable delay line stage comprises a plurality of delay cells configured in series. At least two of the plurality of delay cells comprise a discretely adjustable delay cell with a digital adjustment input. A first delay cell of the plurality of delay cells is coupled to the counter stage to receive the counter output signal. The multiplexer comprises at least two data inputs coupled to the outputs of at least two of the plurality of delay cells and a selector input for receiving a second portion of the duty cycle command. The multiplexer outputs an input signal received at one of the data inputs based upon the second portion of the duty cycle command. The controller is coupled to an input of the plurality of delay cells to receive the counter stage output signal and to an output of at least one of the plurality of delay cells to receive a delayed signal. The controller is configured to generate a digital adjustment signal to discretely and independently control a delay of the discretely adjustable delay cells via the digital adjustment input of the discretely adjustable delay cells based upon a comparison of the counter stage output signal and the delayed signal. 
     In another implementation, a method for controlling a delay of a delay line of a digital pulse-width-modulator is provided. The method comprises: receiving a signal at a delay line of the digital pulse-width-modulator; propagating the signal through a plurality of delay cells of a delay line, at least two of the plurality of delay cells comprising a discretely adjustable delay cell; providing an output of at least two of the plurality of delay cells of the delay line to a multiplexer; selecting one of the outputs of the delay cells at the multiplexer based at least a portion of a duty cycle command; sampling the signal at the end of a reference period at an output of a first delay cell in the delay line and an output of a second delay cell in the delay line to obtain a first sampled discrete value and a second sampled discrete value; comparing the first discrete value to the second discrete value; determining a digital control code for discretely and independently adjusting a delay of the at least two discretely adjustable delay cells based upon the comparison of the first discrete value to the second discrete value; and applying the digital control code to the at least two discretely adjustable delay cell to adjust a delay of the discretely adjustable delay cell. 
     In yet another implementation, a digital pulse-width-modulator with a digital phase-locked loop is provided. The digital pulse-width-modulator comprises a ring oscillator, a phase/frequency detector, a controller, a multiplexer, and a comparator. The ring oscillator comprises a plurality of delay cells. At least two of the delay cells comprising a discretely adjustable delay cell. The phase/frequency detector is coupled to an output of the ring oscillator. The phase/frequency detector compares a phase and a frequency of the ring oscillator output to a phase and a frequency of a reference clock and generates a pair of digital error signals. The controller is coupled to the discretely adjustable delay cells of the ring oscillator to discretely and independently control a delay of the discretely adjustable delay cells via a digital control command. The digital controller generates the digital control command based on the pair of digital error signals. The multiplexer comprises a plurality of inputs coupled to the plurality of delay cells of the ring oscillator and an output for providing a multiplexer output signal corresponding to one of the plurality of inputs. The multiplexer output signal is selected from the plurality of inputs based upon a first portion of a duty cycle command. The comparator comprises a pair of inputs for receiving a counter signal and a second portion of the duty cycle command and an output. Course adjustment of an output pulse width of the digital pulse-width modulator is based on the output of the comparator. Fine adjustment of the output pulse width of the digital pulse-width modulator is based on the multiplexer output signal. 
     The foregoing and other aspects, features, details, utilities, and advantages of the present invention will be apparent from reading the following description and claims, and from reviewing the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows an example of a hybrid digital pulse-width-modulator with a counter and an open-loop delay line. 
         FIG. 2  shows a timing diagram for the hybrid DPWM  10  shown in  FIG. 1 . 
         FIGS. 3A through 3C  shows timing diagrams of an output from a four-bit hybrid digital pulse-width-modulator. 
         FIGS. 4A and 4B  show implementations of discretely adjustable delay cells. 
         FIG. 5  shows an implementation of a hybrid digital pulse-width-modulator configured to discretely adjust a delay of one or more delay cells in a delay line. 
         FIG. 6  shows one implementation of a shift register used to provide digital delay control signals for adjusting a delay of delay cells of a digital pulse-width-modulator. 
         FIG. 7  shows an implementation of a connection pattern for applying a digital control signal to a plurality of discretely adjustable delay cells. 
         FIG. 8  shows an example of a hybrid digital pulse-width-modulator module providing two outputs. 
         FIG. 9  shows one implementation of a hybrid digital pulse-width-modulator stage for producing the second output of the hybrid digital pulse-width-modulator shown in  FIG. 8 . 
         FIG. 10  shows a timing diagram for an example hybrid digital pulse-width-modulator. 
         FIG. 11  shows an implementation of a leading edge hybrid digital pulse-width-modulator. 
         FIG. 12  shows another implementation for generating a pair of outputs in a triangular hybrid digital pulse-width-modulator implementation. 
         FIG. 13  shows an experimental waveform of a hybrid digital pulse-width-modulator implementation. 
         FIG. 14  shows the change in the output of the output signal of a hybrid digital pulse-width-modulator for different values of a duty cycle command. 
         FIG. 15  shows two outputs of a hybrid digital pulse-width-modulator. 
         FIG. 16  shows a comparison of the output of a pair of digital pulse-width-modulators. 
         FIG. 17  shows a hybrid digital pulse-width-modulator with a digital phase-locked loop generating a pulse-width-modulated output based on trailing-edge modulation. 
     
    
    
     DETAILED DESCRIPTION 
     A digital pulse-width-modulator (DPWM) including a discretely adjustable delay line is provided. The discretely adjustable delay line of the DPWM may be used, for example, to compensate for delay variations introduced by process, temperature, and/or input voltage variations. The DPWM may comprise any type of DPWM that uses a delay line, such as a pure delay line DPWM, a hybrid DPWM, or a ring oscillator type hybrid DPWM. 
       FIG. 3A  shows an ideal timing diagram  30  of an output from a four-bit hybrid DPWM in which the most-significant bit (msb) portion of the duty cycle command is resolved by a counter-based portion of the hybrid DPWM and a least-significant-bit (lsb) portion of the duty cycle command is resolved by a delay line portion of the hybrid DPWM. In this example, the msb portion comprises two-bits of the four-bits of the overall hybrid DPWM, and the lsb portion comprises the remaining two-bits. The overall switching period from time 0 to time T s  is divided into four increments  32 ,  34 ,  36 , and  38  corresponding to the two-bit msb portion of the duty cycle command that is resolved by the counter-based portion of the hybrid DPWM. Specifically, the first increment  32  ranges from 0 to T s /4, the second increment  34  ranges from T s /4 to T s /2, the third increment  36  ranges from T s /2 to 3·T s /4, and the fourth increment ranges from 3·T s /4 to T s . 
     In the example shown in  FIG. 3A , the second increment  34  is expanded below the timing line to show the portion of the timing diagram corresponding the remaining two-bit lsb potion of the duty cycle command that is resolved via the delay line portion of the hybrid DPWM. Similar to the upper portion of the timing diagram corresponding to the msb portion of the duty cycle command, the lower portion of the timing diagram corresponding to the lsb portion of the duty cycle command is divided into four time slots  40 ,  42 ,  44 , and  46 . In the ideal hybrid DPWM, each of the time slots  40  to  46  corresponding to the delay line portion of the hybrid DPWM are equal to each other and result in a linear and monotonic modulated signal output from the hybrid DPWM. 
     In contrast to the ideal delays provided by the cells in the delay line shown in the timing diagram of  FIG. 3A , typical delay cells are strongly dependent on factors such as process and temperature variations.  FIGS. 3B and 3C , for example, shows timing diagrams from a four-bit hybrid DPWM in which the delay in cells of the delay line are able to vary, such as with process and/or temperature variations. In  FIG. 3B , for example, the delays of the individual cells of the delay line are shorter than the delays provided by the delay cells shown in  FIG. 3A . In  FIG. 3C , however, the delays of the individual cells of the delay line are longer than the delays provided by the delay cells shown in  FIG. 3A . 
     As described above with respect to  FIG. 3A ,  FIGS. 3B and 3C  both show time increments  32 ,  34 ,  36 , and  38  corresponding to the two-bit the most-significant bit (msb) portion of a duty cycle command that is resolved by a counter-based portion and time slots  40 ,  42 ,  44 , and  46  corresponding to the two-bit least-significant-bit (lsb) portion that is resolved by a delay line portion of the hybrid DPWM. Again, the msb portion comprises two-bits of the four-bit duty cycle command, and the lsb portion comprises the remaining two-bits. 
     In the example shown in  FIG. 3B , time slots shown in the expansion of the second increment  34  below the timing line show resolution of the remaining two-bit lsb potion of the duty cycle command via the delay line where the delays of the individual cells are each less than one-fourth of the total increment  34 . In this configuration, the shorter delays provided by the delay cells provide a non-linear output from the hybrid DPWM because the duration of each time slot within the increment  34  is not equal. The output of the hybrid DPWM is monotonic, however, because the delay through the delay line is not greater than the total time allocated to the increment  34 . 
     In  FIG. 3C , however, the time slots shown in the expansion of the second increment  34  below the timing line show resolution of the remaining two-bit lsb potion of the duty cycle command via the delay line where the delays of the individual cells are each greater than one-fourth of the total increment  34 . In this configuration, the longer delays provided by the delay cells provide a linear output if the delays of each cell in the delay line are the same. However, the output of the hybrid DPWM is non-monotonic because delay through the delay line is greater than the time allocated for the increment  34 . Thus, the output of the delay line extends into the third increment  36  of the counter portion of the hybrid DPWM and can lead to output signals that overlap. 
     Although  FIGS. 3A through 3C  shows timing diagrams for a hybrid DPWM, one skilled in the art would recognize that similar timing concerns would also apply in a pure delay line DPWM configuration. 
       FIG. 4A  shows an implementation of a discretely adjustable delay cell  50 A. The delay through the individual delay cell is discretely adjustable to control the delay of a delay line. Where each delay cell in the delay line is adjustable, for example, the delay of the entire delay line can be controlled. The delay line may also comprise a subset of one or more discretely adjustable delay cells that may be discretely controlled to compensate for variations of delays in the delay line. The discretely adjustable delay cell  50 A is the k th  cell of the delay line. The discretely adjustable delay cell  50 A can be adjusted with a ratio of 1:2. Within the delay cell  50 A, there are two parallel branches  52 A that connect an input i k−1  of the delay cell  50 A to the output i k  of the delay cell  50 A. If the first branch has a delay of Δt, the second branch of the delay cell has a delay of 2Δt. A control line a k−1  can be assigned a thermometer code to select the appropriate delay branch  52 A of the delay cell  50 A to provide a desired delay through the delay cell  50 A. The input control signals can be provided, for example by a delay control module that controls at least one of the delay cells within a delay line. 
       FIG. 4B  shows another implementation of a discretely adjustable delay cell  50 B. The delay through the individual delay cell  50 B is discretely adjustable to control the delay of a delay line. Where each delay cell in the delay line is discretely adjustable, for example, the delay of the entire delay line can be controlled. The delay line may also comprise a subset of one or more discretely adjustable delay cells that may be discretely controlled to compensate for variations of delays in the delay line. In  FIG. 4B , the discretely adjustable delay cell  50 B is the k th  cell of the delay line. In this implementation, the discretely adjustable delay cell  50 B can be adjusted with a ratio of 1:m. Within the delay cell  50 B, there are m parallel branches  52 B that connect the input i k−1  of the delay cell to the output i k  of the delay cell  50 B. If the first branch has a delay of Δt, the m th  branch of the delay cell has a delay of mΔt. The control lines a 1,k  to a m−1,k  can be assigned a thermometer code to select an appropriate delay branch  52 B of the cell  50 B to provide a desired delay through the delay cell  50 B. The input control signals can be provided, for example, by a delay control module that controls at least one of the delay cells within a delay line. 
       FIG. 5  shows an implementation of a hybrid DPWM  60  configured to discretely adjust a delay of one or more delay cells in the delay line. The overall structure of the hybrid DPWM  60  is similar to the hybrid DPWM  10  shown in  FIG. 1 , except one or more of the delay cells have a discretely adjustable delay controlled by the digital delay control signal(s) d_contp. The hybrid DPWM  60  receives a count signal cnt_out output from a counter and compares the count signal cnt_out with the modified duty cycle command msb(duty)−1 in a comparator  62 . The output of the comparator  62  is provided to a flip-flop  64  that secures the signal and prevents inconsistencies that might be introduced by combinatorial logic of the comparator  62 . To compensate for the delay introduced by the flip-flop  64 , the most-significant-bit portion msb(duty) of the duty cycle command is modified by subtracting one (corresponding to the delay of the flip-flop). The signal is then provided to a delay line  66 . In this particular implementation, for example, the delay line comprises  32  discretely adjustable delay cells corresponding to a five-bit resolution. 
     As described above with respect to  FIG. 1 , the outputs of each delay cell in the delay line  66  are tapped and provided to inputs of a multiplexer  68 . An input of the multiplexer is selected using the least-significant-bit portion duty LSB of the duty cycle command as described above with respect to  FIG. 1 . 
     The outputs of the flip-flop  64 , the second last delay cell del 30 , and the last delay cell del 31 , are tapped to provide the respective signals Dt, Dt 30 , and Dt 31 . These signals are provided to a delay locked loop (DLL) controller  70  to control the delay of one or more of the discretely adjustable delay cells of the delay line  66 . As shown above in  FIG. 3A , the ideal delay through the delay line should be equivalent to a width of the Dt signal received at the input of the delay line  66 . Thus, a falling edge of the input signal Dt should be aligned with the rising edge of the output signal Dt 31 . In the DLL controller  70 , a flip-flop may be used to detect a misalignment of edges of the input and output signals. If at a falling edge of the input signal Dt, a high value for the output signal Dt 31  is detected, the delay of the delay line may be increased, and if at the falling edge of the input signal Dt, a low value for the output signal Dt 31  is detected the delay of the delay line may be decreased. 
     In one particular implementation shown in  FIG. 6 , a shift register  80  is used to provide the digital delay control signals and adjust the delay of the delay cells. To increase the delay through the delay line a zero may be shifted to the left, and to decrease the delay through the delay line a one is shifted to the right. Other implementations are possible, however. In this implementation, the output of the shift register is then a thermometer coded signal that can be used to control the delay of one or more of the individual delay cells of the delay line. 
     In this particular implementation, to have a steady-state condition and prevent jittering on the output of the hybrid DPWM, the falling edge of the input signal Dt is compared with the rising edges of both tapped signals Dt 30  and Dt 31 . In this implementation, the change in the control value of the shift register is performed until the falling edge of the input signal Dt falls between the rising edges of the signals Dt 31  and Dt 31 . After the error=10 (see  FIG. 6 ), is achieved, no further change in the shift register need be performed, and a steady-state situation for the delay of the delay line may be achieved. 
     The total number of bits in the shift register depends on the number of discretely adjustable delay cells in the delay line and the delay cell adjustment ratio. If l is the number of discretely adjustable delay cells in the delay line and the individual discretely adjustable delay cells each have an adjustment ratio of 1:m, the total number of bits required to adjust each cell in the delay line is 2 l ·(m−1). In a five-bit delay line with a delay adjustment ratio of 1:4, for example, three sets of 32-bit shift registers may be used to digitally adjust a delay of each cell in the delay line. Two more bits, LOW lim  and UP lim , may be added at the beginning and the end of the shift register, respectively, to indicate if the delay line has reached its minimum or maximum achievable delay. Furthermore, it shows that the DLL cannot satisfy the requirement of having a falling edge of the input signal Dt to be aligned with the output signal Dt 31  (i.e., the error signal is always 11 or 00 in the implementation shown in  FIG. 6 ). 
     The digital control signals at the output of the shift register  80  can be connected to control inputs of the discretely adjustable delay cells in different ways. Although the connection of the control signal can be a direct connection (e.g., the bits of the thermometer code of the control signal can be connected linearly to the control inputs of the adjustable delay cells), the control signal can alternatively be connected in a connection pattern (e.g., a connection pattern that increases the linearity of the DPWM). The least linear output of the DPWM will occur when all the low or high delay modules are placed together (e.g., at the beginning or end of the delay line). 
     In an ideal design, half of the discretely adjustable delay cells are adjusted at a low delay value, and the other half of the discretely adjustable delay cells are adjusted at a high delay value. Therefore, the maximum linearity for this ideal case can be achieved by arranging the discretely adjustable delay cells consecutively in the delay line. For any number of the delay cells, a connection pattern can be derived that provides consecutive arrangements of delay. For a five-bit delay line with thirty-two discretely adjustable delay cells, for example, a connection pattern for the p th  of the m−1 sets of the shift register output is shown in  FIG. 7 . The output of the pattern module is then connected to the delay cell control input shown in  FIG. 4 . 
     A DPWM may provide one or more outputs. Examples of circuits that may need multiple outputs as control signals include a synchronous buck DC-DC converter or a converter that requires a phase shift.  FIG. 8  shows an example of a hybrid DPWM module  90  providing two outputs D 1  and D 2 . The dual output hybrid DPWM module  90  may be used, for example, in a DC-DC converter with a synchronous rectifier in which the outputs D 1  and D 2  are used to provide programmable dead-times for the synchronous rectifier. 
       FIG. 9  shows two delay lines  100  and  102  that together produce the second output of the hybrid DPWM  90  shown in  FIG. 8 , D 2 . The structure of each of the delay lines  100  and  102  is similar to the structure of the single delay line  60  shown in  FIG. 5 .  FIG. 10  shows a timing diagram for an example hybrid DPWM that has a combination of a two-bit counter and an l-bit delay line. In this example, a set point of the output signal D 1 , signal S 1 , is always fixed and happens at a time when a counter is zero. A reset point R 1 , on the other hand, may occur at any time between one clock period of an input signal clk. Therefore, a single delay line can be used to generate the signal D 1 , as shown in  FIG. 5 . 
     Input dead times are applied to the second output signal D 2 , as shown in the timing diagram of  FIG. 10 . As a result, the set and reset events of the output D 2  may happen at any time inside of one clock period of the input clock signal clk. To generate both the set signal S 2  and the reset signal R 2 , an approach with one or two delay lines may be used.  FIG. 10 , for example, shows a design with two delay lines. The second output signal D 2 , however, may be generated using a single delay line in which more sophisticated combinatorial logic is used to generate the most-significant-bit portion dutyMSB of the duty cycle command and the least-significant-bit portion dutyLSB of the duty cycle command. In  FIG. 12  discussed below, for example, a single delay line is shown for each output signal, D 1  and D 2 , in a triangular DPWM implementation in which neither the set nor the reset points of the DPWM output are fixed. 
     In  FIG. 9 , however, the most-significant-bit portions dutyMSBs of the duty cycle command and the least-significant-bit portions dutyMSBs of the duty cycle command are given as follows.
 
dutyMSB 2 =msb(duty+ t   d2 )
 
dutyLSB 2 =lsb(duty+ t   d2 )
 
dutyMSB 3 =lsb(1− t   d1 )
 
dutyMSB 2 =msb(1− t   d1 )
 
     The two delay lines for the output signal D 2  shown in  FIG. 9  are identical and matched with the delay line shown in  FIG. 5 . Therefore, the same digital control signals d_contp, generated from the DLL shown in  FIG. 6  can be used to control the delay of the discretely adjustable delay cells in the delay line shown in  FIG. 9 . It should also be noted that only one counter may be used to generate both output signals D 1  and D 2 . 
     Leading Edge and Triangular DPWM 
     Although  FIGS. 5 through 10  describe a trailing edge implementation in a hybrid DPWM, the design discussed above can also be extended to other modulation schemes, such as leading edge, triangular, and phase shift DPWM. In these modulation schemes, the structure of the hybrid DPWM, including the delay line, counter, and digital DLL is not changed. The combinatorial logics that provide the most-significant-bit portion dutyMSB or least-significant-bit portion dutyLSB of the duty cycle command can be modified for each scheme. In addition, the output latch of the hybrid DPWM can also be modified for each scheme. 
     In a leading edge hybrid DPWM, the reset signal can be fixed to occur when the counter has reached its maximum count (at the end of the switching period Ts), while the set point of the DPWM occurs at the time when the output of the counter equals the value of (1−duty).  FIG. 11 , for example, shows an example implementation of a leading edge hybrid DPWM. The second output signal D 2  can also be implemented with the same technique or with the dual delay line technique shown in  FIG. 9 . 
     In a triangular modulation scheme, the modulation scheme can be divided into two trailing edge and leading edge modulation steps. During one switching period, a hybrid DPWM can be switched to a leading edge operation and the value of (1−duty)/2 is considered to determine the most-significant bit portion dutyMSB and least-significant-bit portion dutyLSB values for the DPWM. In the following switching cycle, however, the hybrid DPWM can be switched to a trailing edge modulation scheme and the value duty/2 is provided to determine the most-significant-bit portion dutyMSB and the least-significant-bit portion dutyLSB values.  FIG. 12 , for example, shows an example implementation of a triangular modulation scheme using a hybrid DPWM with a digital DLL. The second DPWM output D 2 , can be constructed using the same technique with one delay line or as in  FIG. 9  with two delay lines. 
     EXAMPLE 
     A hybrid DPWM with a digital DLL was implemented on a field programmable gate array (FPGA) control board, which included a Xilinx Virtex II (XC2V100) chip. The hybrid DPWM had a ten-bit resolution, with a five-bit counter and a five-bit delay line (32 delay cells). An input clock frequency of f clk =25 MHz was provided to the hybrid DPWM. The hybrid DPWM provided a switching frequency of f sw =25 MHz/2 5 =781 KHz. The delay through the delay line should be equal to one clock period, del tot = 1/25 MHz=40 ns. For the 32 delay cells, the average and nominal delay of one delay cell was Δt=40 ns/32=1.25 ns. A delay cell, as show in  FIG. 4A , was chosen with an adjustment ratio of 1:2. Therefore, one set of a 32-bit shift register was used to provide 32 lines of delay control signals, d_contp. 
       FIG. 13  shows an experimental waveform of Dt, the input clock of the delay line, and Dt 31 , the propagated clock at the output of the delay line.  FIG. 13  shows that the falling edge of the signal Dt is aligned with the rising edge of the propagated clock signal Dt 31 . The delay control signals, d_contp, were monitored for this experimental setup and observed that 12 delay cells were adjusted to the low delay value and the remaining 20 delay cells were adjusted to the high delay value. 
       FIG. 14  shows the change in the output of the output signal D 1  for different values of the duty cycle command. Specifically, in this example, a ten-bit duty cycle command was changed by one step from the value of 3C5 Hex to 3C9 Hex. 
       FIG. 15  shows two outputs of a hybrid DPWM, D 1  and D 2 . Two dead-times t d1  and t d2  are applied to the output signal D 2 . In the experimental setup, a ten-bit hybrid DPWM is provided with a switching frequency f sw =781 KHz, while the input clock frequency is f clk =25 MHz. This clock frequency would have produced only a five-bit resolution using a simple counter-based DPWM with the same switching frequency. 
     A low-pass filter using a resistor and a capacitor is constructed and placed on the hybrid DPWM output D 1 . The duty cycle is then slowly increased from a zero value to a maximum value of d=0.985.  FIG. 16  shows a comparison of the output of the low-pass filter for two cases of (1) a five-bit, counter-based DPWM and (2) a 10-bit hybrid DPWM, where the remaining five-bits is provided by a delay line. In both cases, the switching frequency f sw =781 MHz and the clock frequency f clk =25 MHz. It is observed that the hybrid DPWM significantly increases the resolution over the counter-based DPWM, while maintaining its linearity. 
     Hybrid PWM Design 
     A hybrid DPWM is particularly useful if the resolution of a counter-based DPWM is insufficient for a desired application. Because of its simplicity, linearity, and limited area required for hardware resources, the counter stage of the hybrid DPWM can be used for the majority of the resolution of the DPWM. The delay line stage can then be used to provide additional resolution to supplement the counter stage of the hybrid DPWM. 
     In designing a hybrid DPWM, the input clock frequency, f clk , is typically considered first. The input clock frequency may be limited, for example, by hardware constraints, cost considerations, availability, or any other factor. The switching frequency, f sw , and/or the desirable resolution of the hybrid DPWM can be considered along with the input clock frequency. Having either of a desirable switching frequency f sw  or a maximum DPWM resolution can be used to determine the other value. In this example, it is assumed that the desired switching frequency, f sw , is known and the maximum achievable resolution of the DPWM is the result of the design. A designer could just as easily start with a desired resolution, however, instead of a switching frequency. 
     In this example, the maximum number of bits, n, of the counter can be determined from the following formula.
 
 n =Log 2 ( f   clk   /f   sw )  (7)
 
     To obtain an integer value for n, it is desirable that the clock frequency fclk and the switching frequency fsw have the following relationship described above.
 
f clk =2 n f sw  
 
     If the value of n is not an integer value, however, the value of n may be rounded to the next integer value. 
     The maximum length and achievable resolution of the delay line can be found from the process characteristics in which the DPWM is implemented. First, the delay element for the delay cells in the delay line may be selected. Typical examples include nor gates, inverters, or tri-state buffers. The delay cell may be constructed using the selected delay elements (e.g., two nor gates, two inverters, or one tri-state buffer). The maximum delay, Δt max , through the delay cell can be determined for the worst anticipated case of temperature, process, and voltage variations. As described above, the delay through the delay line is preferably equal to one clock period of T clk =1/f clk . The maximum number of bits, l, of the delay line can then be found by the following formula.
 
 l =Int[Log2( T   clk   /Δt   max )]
 
     The delay adjustment ratio, m, discussed above with respect to  FIG. 6 , can be found from the ratio of Δt max /Δt min . The value of Δt min  is the minimum delay of the simplest delay cell that is found for variations in temperature, process, or supply voltage. The delay adjustment ratio can thus be determined by the following formula.
 
 m=Δt   max   /Δt   min  
 
     The value of m is rounded to the next integer value. As shown in  FIG. 4B , each individual delay cell has m delay branches. It can be assumed that the delay branches are designed such that the ith branch has an equivalent delay of i·Δt, where Δt comprises the delay of the first branch (the delay branch with the shortest possible delay). Each delay cell has m−1 input control signals. 
     The delay locked loop has m−1 sets of 2 l -bit shift registers, which corresponds to 2 l ·(m−1) bits. As discussed above with respect to  FIG. 6 , two more bits (e.g., UP lim  and LOW lim ) can be added to the shift register. 
     The total number of bits of the hybrid DPWM is N=n+1. Without changing the design of the delay line, the number of bits of the counter, n, can be increased or decreased to provide different values of the switching frequency, f sw . For example, by having n=0 (no counter in the circuit), the switching frequency is increased to f sw =f clk . On the other hand, the switching frequency, f sw , can be decreased and the DPWM can obtain a higher resolution by increasing the number of bits, n, of the counter stage. 
     Phase-Locked-Loop 
       FIG. 17  shows a hybrid DPWM with a digital phase-locked loop (DPLL) generating a pulse-width-modulated output D 1  based on trailing-edge modulation. Other DPWM types can be easily constructed following the same principles. 
     In the hybrid DPWM shown in  FIG. 17 , delay cells with discretely adjustable delays form a ring oscillator. Although the embodiment shown in  FIG. 17  shows that each delay cell of the ring oscillator are discretely adjustable, only a subset of one or more delay cells of the ring oscillator may be discretely adjustable. 
     A phase/frequency detector compares the phase and frequency of the ring oscillator output to a reference clock clock and generates the digital error signals err 1  and err 2 . Digital control of the cell delays is accomplished based on the error signals err 1  and err 2  as shown in  FIG. 6 . In steady-state, the ring oscillator frequency and phase approximately match the reference clock frequency and phase. 
     Course adjustment of the output pulse width is based on a comparison of the MSB portion dutyMSB of the duty-cycle command with the counter output cnt_out. The LSB portion dutyLSB of the duty-cycle command selects a tap from the ring oscillator to finely adjust the output pulse width. 
     Although several embodiments of this invention have been described above with a certain degree of particularity, those skilled in the art could make numerous alterations to the disclosed embodiments without departing from the spirit or scope of this invention. For example, although a hybrid DPWM is primarily discussed, the concepts disclosed herein can also be simply extended to other topologies, such as a pure delay line or a ring oscillator type DPWM. In addition, various types of pulse-width-modulation can be performed, such as trailing edge, leading edge, triangular, or phase shift modulation. 
     All directional references (e.g., upper, lower, upward, downward, left, right, leftward, rightward, top, bottom, above, below, vertical, horizontal, clockwise, and counterclockwise) are only used for identification purposes to aid the reader&#39;s understanding of the present invention, and do not create limitations, particularly as to the position, orientation, or use of the invention. Joinder references (e.g., attached, coupled, connected, and the like) are to be construed broadly and may include intermediate members between a connection of elements and relative movement between elements. As such, joinder references do not necessarily infer that two elements are directly connected and in fixed relation to each other. It is intended that all matter contained in the above description or shown in the accompanying drawings shall be interpreted as illustrative only and not limiting. Changes in detail or structure may be made without departing from the spirit of the invention as defined in the appended claims.