Abstract:
An apparatus for driving a plasma display panel having a plurality of display cells, a first electrode and a second electrode. A load calculating circuit detects the number of display cells to be illuminated in a sustaining period. A pulse width calculating circuit obtains a pulse width of a reset pulse according to the number of display cells to be illuminated. A driving circuit applies the reset pulse between the first electrode and the second electrode.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates in general to a method and an apparatus for driving a plasma display. In particular, the present invention relates to a plasma display driving device and a driving method thereof.  
         [0003]     2. Description of the Related Art  
         [0004]     An AC memory type plasma display panel (referred to as PDP hereafter) has many advantages such as large screen size, high display ability, and high reliability. Thus, the PDP is applied in various wide screen electronic devices. Currently plasma display panels are driven through a plurality of sub-fields-display operations, which altogether constitute a full frame-display operation. For example, a picture frame in a plasma display panel with 256 gray levels may comprise eight sub-fields SF 0 ˜SF 7  as shown in  FIG. 1A . Each subframe-display operation comprises steps of resetting, scanning, and sustaining. Specifically, a plasma display panel is driven by a driving waveform that comprises a reset period, an address period, and a sustaining period. During the reset period, residual ions of each display cell of a PDP are erased. During the address period, scan pulses are applied to scan electrodes and data pulses are applied to data electrodes to produce proper amount of wall charges in corresponding cells in the address period. During the sustaining period, alternate sustain pulses are applied to sustaining electrodes and scan electrodes and sustain discharge occurs in the cells with wall charges.  
         [0005]      FIG. 1B  is a cross section of a conventional PDP structure, and  FIG. 1C  is a schematic top view of the data, sustaining and scan electrodes of the same PDP. As shown in  FIG. 1B , a PDP is constructed by joining a front glass substrate  1  with a rear glass substrate  2 , wherein data electrodes  3  are formed on the surface of the front glass substrate  1  opposing the rear glass substrate  1 . Furthermore, a plurality of ribs  4  is deposited on the surface of the front glass substrate  1  opposing the rear glass substrate  1  to form gas discharge space filled with inert gas, such as Ne, Xe, Ar or the mixture. A plurality of sustaining electrodes  7  and scan electrodes  8  in parallel direction, are also formed on the surface of the rear glass substrate  2  opposing the front glass substrate  1 , wherein the above-mentioned data electrodes  3  are formed perpendicular to both the sustaining electrodes  7  and the scan electrodes  8 . In addition, the surfaces of both the sustaining electrodes  7  and scan electrodes  8  are coated with a dielectric layer  6  (such as an MgO layer) for protection of the surfaces of the electrodes. In general, both dielectric layer and MgO layer exist in PDP. Usually the material of dielectric layer is ceramic material. MgO layer is deposited above dielectric layer for protection, too. Meanwhile, MgO layer will help to generate secondary electrons. Furthermore, a fluorescent material  5  (such as phosphorous) is deposited between ribs (where the display cells reside) for illumination as soon as gas discharge occurs. As shown in  FIG. 1C , a typical conventional plasma display panel comprises a plurality of row plasma display units (represented by L 1 ˜LN). Each row display unit comprising one of the plurality sustaining electrodes  7  (represented by a corresponding X 1 ˜X N ) and one of the plurality of parallel scan electrodes  8  (Y 1 ˜Y N ); for example, the first row display unit L 1  can comprise the first sustaining electrode X 1 , and the first scan electrode Y 1 . The plurality of display cells of the first row display unit L 1  is driven by the X 1 , Y 1  simultaneously during the sustaining period. The plurality of data electrodes  3  (D 1 ˜D M ) is disposed perpendicular to both the sustaining electrodes  7  (X 1 ˜X N ) and the scan electrodes  8  (Y 1 ˜Y N ). Each of the sustaining electrodes  7  (X 1 ˜X N ) is connected to the others, whereby the electrodes can be driven synchronously. In contrast, each of the scan electrodes  8  (Y 1 ˜Y N ) is connected separately from the other electrodes so as to supply scan pulse in the address period independently. Thus, data pulses synchronized with corresponding scan pulse are transmitted to each display cell of the plasma display panel via the data electrodes  3  (D 1 ˜D M ) in the address period.  
         [0006]      FIG. 2  is a driving waveform diagram of various electrodes of the plasma display panel shown in  FIGS. 1B, 1C , and  1 D, which are driven according to conventional method. Accordingly, a plasma display panel is driven by a driving waveform that comprises a reset period, an address period, and a sustaining period. During the reset period, a slow-rising priming pulse P P  with slope smaller than 20V/us and voltage V W  higher than the gas firing voltage is applied to the sustaining electrodes  7  X 1 ˜X N  to perform a priming process which produce space charges in the gas discharge space of each cell. The priming process will benefit reducing operation voltage and improving gas discharge uniformity of the panel. After priming pulse P P , a slow-rising reset pulse E P  with slope smaller than 20V/us and voltage V ER  higher than sustain voltage V S  of the sustain pulse but lower than the gas firing voltage is applied to scan electrodes Y 1 ˜Y N  to remove residual wall charges from the last sub-field and priming pulse. In some applications, because the priming effect can maintain for several milliseconds, the priming pulse only exists in one or two of the reset periods in a frame and other reset periods only comprise reset pulses. During the address period, a bias voltage V K  is applied to the sustaining electrodes  7  X 1 ˜X N  and scan pulses with voltage V Y  are applied to the scan electrodes  8  Y 1 ˜Y N  in proper order. At this the same time, data pulses with voltage V D  corresponding to the display data of cells are applied to the data electrodes  3  D 1 ˜D M  perform write operations. During the sustaining period, alternate sustain pulses with voltage V S  are applied to sustaining electrodes X 1 ˜X N  and scan electrodes Y 1 ˜Y N  and sustain discharge occurs in the cells in which wall charges was written in the address period.  
         [0007]     In the reset period, time required for the slow-rising priming and reset pulses to reach a predetermined voltage value V r  is dependent on the load, the number of cells discharging in the sustaining period of last sub-field, of the plasma display panel. As the load increases, the priming and erasing current will increase too. The slope of the slow-rising pulses drops and it cost more time to reach the predetermined voltage level. There are two types of slow-rising pulse, the RC-type and ramp-type, utilized to drive the PDP. The RC-type is obtained by charging the panel through a resistor and the ramp-type is obtained by charging the panel by a constant current source.  
         [0008]      FIGS. 3A and 3B  show the waveforms of the slow-rising pulse, such as priming pulse and reset pulse, of different types with different loads on the panel. In  FIG. 3A , the RC-type pulse  311  with light load reaches the predetermined voltage value V r  at time T 11 , and the RC-type pulse  312  with heavy load reaches the predetermined voltage value V r  at time T 12 , exceeding time T 11 . In  FIG. 3B , the ramp-type pulse  321  with light load reaches the predetermined voltage value V r  at time T 21 , and the ramp-type pulse  322  with heavy load reaches the predetermined voltage value V r  at time T 22 , exceeding time T 21 .  
         [0009]     To ensure that voltage level of the priming pulse and reset pulse is sufficient to perform priming operation and erasing operation, the conventional method implements a slow-reset pulse with a fixed pulse width in the reset period, capable of reaching the predetermined voltage level under full load.  
         [0010]     However, when the load on the plasma display panel is light, the long reset period limits the time of the sustaining period, decreasing peak luminance of the plasma display panel.  
       SUMMARY OF THE INVENTION  
       [0011]     The object of the present invention is thus to provide a method and apparatus to adjust the pulse width of the priming pulse and reset pulse according to the load on the plasma display panel. Since the width of the reset period is decreased, the sustaining period may be increased to improve peak luminance of the plasma display panel.  
         [0012]     To achieve the above-mentioned object, the present invention provides a method for driving a plasma display panel having a plurality of display cells, a first electrode and a second electrode, the method comprising the steps of counting the number of display cells to be illuminated in sustaining period of last sub-field, obtaining pulse width of the reset pulse, and applying the reset pulse between the first electrode and the second electrode.  
         [0013]     In addition, the present invention provides an apparatus for driving a plasma display panel having a plurality of display cells, a first electrode and a second electrode. A load calculating circuit counts the number of the display cells to be illuminated in a sustaining period of last sub-field. A pulse width calculating circuit obtains pulse widths of priming pulse and reset pulse accordingly. A driving circuit applies the priming pulse and reset pulse to the first electrode and the second electrode. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]     The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings, given by way of illustration only and thus not intended to be limitative of the present invention.  
         [0015]      FIG. 1A  shows the sub-fields included in a picture frame in a plasma display panel with 256 gray levels.  
         [0016]      FIG. 1B  is a cross section of a conventional PDP structure.  
         [0017]      FIG. 1C  is a schematic top view of the data, sustaining and scan electrodes arrangement of the same PDP.  
         [0018]      FIG. 2  is a driving waveform diagram of various electrodes of the plasma display panel.  
         [0019]      FIGS. 3A and 3B  show the waveforms of the slow-rising pulse in different types with different load on the panel.  
         [0020]      FIG. 4  is a block diagram of the driving device of a plasma display panel according to one embodiment of the present invention.  
         [0021]      FIG. 5  shows the waveform of the slow-rising pulse with adjustable pulse width. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0022]      FIG. 4  is a block diagram of the driving device of a plasma display panel according to one embodiment of the present invention. The driving device comprises a control circuit  40 , an address driver  46 , a sustaining driver  44  and a scan driver  42 . The control circuit  40  receives video signals, the transmission clock CLOCK, the vertical synchronous signal VSYNC and the horizontal synchronous signal HSYNC, and transmits the display data and control signals to the drivers. The address driver  46  drives the data electrodes D 1 ˜Dm during the address period to write the display data in the display cells  48  located at the intersection of corresponding data electrode, scan electrode and sustaining electrode. The scan driver  42  drives the scan electrodes Y 1 ˜Yn. The sustaining driver  44  drives the sustaining electrode X.  
         [0023]     As shown in  FIG. 2 , a slow-rising priming pulse Pp with slope smaller than 20V/us and voltage V W  higher than the gas firing voltage is applied to the sustaining electrodes  7  X 1 ˜X N  to perform a priming process which produce space charges in the gas discharge space of each cell. The priming process will benefit reducing operation voltage and improving gas discharge uniformity of the panel. After priming pulse P P , a slow-rising reset pulse Ep with slope smaller than 20V/us and voltage VER higher than sustain voltage V S  of the sustain pulse but lower than the gas firing voltage is applied to scan electrodes Y 1 ˜Y N  to remove residual wall charges from the last sub-field and priming pulse. In some applications, because the priming effect can maintain for several milliseconds, the priming pulse only exists in one or two of the reset periods in a frame and other reset periods only comprise reset pulses.  
         [0024]     In addition, the control circuit  40  comprises a load calculating circuit  41  and a pulse width calculating circuit  43 . The load calculating circuit  41  counts the load on the plasma display panel. Here, the load on the plasma display panel is determined according to the number of cells discharging in the sustaining period of last sub-field. After obtaining the load on the plasma display panel, the pulse width calculating circuit  43  generates the widths of priming pulse and reset pulse. Here, the pulse width of the reset pulse is determined according to the load on the plasma display panel.  
         [0025]     The pulse width T can be determined by the following expressions: 
 
 T=T   min   +x·Δt  
 
Δ t =( T   max   −T   min )/ T   max  
        where T min  denotes the pulse width with least load on the plasma display panel, such as full black image; T max  denotes the pulse width with largest load on the plasma display panel, such as full white image; and x denotes the percentage of the load, ranging from 0%, such as full black image, to 100%, such as full white image.        
 
         [0027]      FIG. 5  shows the waveform of the ramp-type slow-rising pulse with adjustable pulse width. The pulse width of the reset pulse according to one embodiment of the present invention is set between the pulse width T min  and T max  by correlating the pulse width with the load on the panel linearly.  
         [0028]     Alternately, the pulse width of the slow-rising pulse can also be determined by measuring the real time-requirement with different loads, so the pulse width distribution may be non-linear. For example, the pulse width of the slow-rising pulse corresponds to time required for the reset pulse to reach a predetermined voltage level, capable of performing the required operation, such as priming operation and erasing operation in the reset period.  
         [0029]     Moreover, the method according to the present invention is suitable for ramp-type slow-rising pulse or RC-type slow-rising pulse. In addition, in some application, slow-falling pulse is adopted to perform the priming operation or erasing operation, and the slope of the slow-falling pulse also changes with the load on the panel. The width of the slow-falling pulse also can be determined according to the invention. Furthermore, since the pulse width of the reset pulse is adjusted according to the load on the plasma display panel, the pulse widths of the sustaining pulse and the scan pulse are also adjusted with the change in the display load to obtain more stable display quality with reduced flicker.  
         [0030]     The driving method according to the present invention comprises the sequential steps of, in a reset period, counting the number of cells discharging in the sustaining period of last sub-field, obtaining pulse widths of slow-rising pulses according to the number of the display cells discharging in the sustaining period of last sub-field, applying the slow-rising pulses to the first electrode and the second electrode, correspondingly.  
         [0031]     Thus, the pulse width of the slow-rising pulse is decreased when the load on the plasma display panel is low. In addition, the sustain period is able to extend to obtain more sustain pulses and increase the peak luminance of the plasma display panel.  
         [0032]     The foregoing description of the preferred embodiments of this invention has been presented for purposes of illustration and description. Obvious modifications or variations are possible in light of the above teaching. The embodiments were chosen and described to provide the best illustration of the principles of this invention and its practical application to thereby enable those skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the present invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.