Abstract:
A noise canceler for use in a CATV converter includes a keying pulse processing circuit for removing a noise signal from a keying signal. The keying pulse processing circuit includes a canceling signal generator for generating a noise canceling pulse signal, a delaying circuit for delaying the keying signal to produce a delayed signal, and a logic circuit including an AND gate for producing a noise canceled signal which is obtained by taking a logical product of the canceling pulse signal and the delayed signal. Since the noise pulse has a sufficiently small width when compared with the pulse widths of the keying signal and noise removing signal, the noise pulse is removed to obtain a noise canceled signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a keying pulse processing circuit and, more particularly to, a keying pulse processing circuit for use in a noise canceler for a CATV converter. 
     2. Description of the Prior Art 
     The keying signal transmitted into the keying, pulse processing circuit is a group of pulse signals having information necessary to descramble a scrambled image signal. 
     A conventional keying pulse processing circuit will be described with reference to the block diagram shown in FIG. 3. A keying pulse signal S1 applied from an input terminal 1 is shaped into a rectangular waveform signal S2 by a wave shaping circuit 2, and further processed into various necessary pulse signals by a pulse processing circuit 3 for use in a video system 4 and CPU 5. 
     However, in the above conventional set-up of the keying pulse processing circuit, when a keying signal having a noise signal is input, there has been such a problem that the keying signal is processed without removing the noise signal from the keying signal, and the processed signal is input into the next stage as a normal keying signal. 
     SUMMARY OF THE INVENTION 
     The object of the present invention is therefore to provide an imaging device which solves these problems. 
     In order to achieve the aforementioned objective, a noise canceler for removing noise pulses from a keying signal defined by a plurality of keying pulses comprises a signal producing means for producing a noise canceling pulse signal having a canceling pulse in response to a leading edge of the keying pulse and the noise pulse in the keying signal. The canceling pulse had a predetermined pulse width. The noise canceler further comprises a delaying means for delaying the keying signal by a predetermined time to produce a delayed pulse signal, and a canceling means for receiving the canceling signal and the delayed signal and disabaling the generation of the delayed pulse during the presence of the canceling pulse. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and to other objects and features of the present invention will become clear from the following description taken in conjunction with the preferred embodiment thereof with reference to the accompanying drawings, in which: 
     FIG. 1a is a block diagram showing a noise canceler according to a preferred embodiment of the present invention; 
     FIG. 1b is a block diagram showing the details of the noise removal pulse generator of the noise canceler of FIG. 1; 
     FIG. 2 is a graph showing signals produced and/or processed by the noise canceler of FIG. 1; and 
     FIG. 3 is a block diagram showing a conventional keying pulse processing configuration. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A preferred embodiment of the present invention will be described hereinbelow with reference to the accompanying drawings. Components of the same constitution as those in the conventional configuration of FIG. 3 will be designated by the same reference number. 
     Referring to FIG. 1a, a block diagram of a noise canceler according to a preferred embodiment of the present invention is shown. A keying pulse processing circuit KC is provided between a wave shaping circuit 2 and a pulse processing circuit 3. The wave shaping circuit 2 shapes the keying signal S1 transmitted from a terminal 1 into a rectangular wave form signal S2 taking two alternative levels, &#34;1&#34; and &#34;0&#34;. The pulse processing circuit 3 processes a noise canceled signal 55 and produces various signals for the following stages of a video system 4 and a CPU 5. 
     The keying pulse processing circuit KC comprises a canceling pulse signal generator 6 for generating a noise removal pulse signal S3 based on the signal S2, a delaying circuit 7 including a delay circuit, such as a D flip-flop, for delaying the signal S2 by a predetermined time to produce a delay signal S4, and a logic circuit 8. The logic circuit 8 is an AND gate having an inverting input terminal and a non-inverting input terminal for receiving, respectively, the signals S3 and S4, and an output terminal. The logic circuit 8 operates to produce a logical product as a noise canceled signal S5 having alterative sleeve, &#34;0&#34; and &#34;1&#34;, in accordance with various combinations of &#34;0&#34; and &#34;1&#34; of the signals S3 and S4, as shown in Table 1, and transmits the produced signal S5 to the pulse processing circuit 3 through the output terminal. 
     
                       TABLE 1______________________________________(Truth Table of Logic Circuit 8)S3         S4    - S- 3       S4  S5______________________________________1          0     0            0   01          1     0            1   00          0     1            0   00          1     1            1   1______________________________________ 
    
     Referring to FIG. 1b, a detail of the canceling pulse signal generator 6 is shown. The canceling pulse signal generator 6 includes a leading edge detector 6a for detecting a leading edge of the signal S2 (a leading edge of signal S2 described herein is a rising edge), a digital timer 6b which times a predetermined time period τ 1  in response to the detection of the leading edge by the leading edge detector 6a and produces a clear command at the termination of the predetermined time period, and a latch 6 which latches the signal S2 in response to the receipt of level &#34;1&#34; signal thereof until the clear command is received from the digital timer 6b so as to produce a canceling pulse in the canceling pulse signal S3. 
     In operation, it is assumed that the keying signal S1 includes a noise pulse, and thus, the keying pulse signal S2 produced from the wave shaping circuit 2 has, as shown in FIG. 2, a keying pulse of a pulse width τ and a noise pulse of a pulse width τ N . It is to be noted that τ is greater than τ N  (τ&gt;τ N ). The canceling pulse signal generator 6 produces the canceling pulse signal S3 having a plurality of canceling pulses, each produced in response to each pulse in the signal S2 and having a predetermined width τ 1 . It is to be noted that τ 1  is smaller than τ but greater than τ N  (τ&gt;τ 1  &gt;τ N ). 
     The delaying circuit 7 delays the signal S2 by a predetermined time τ 2  and produces the delayed keying signal S4 so that a keying pulse of a width τ and a noise pulse of a width τ N  therein are delayed by a time τ 2  compared with the signal S2. It is to be noted that τ 2  is smaller than the difference between τ 1  -τ N  (τ 2  ≦τ 1  -τ N  or τ N  ≦τ 1  -τ 2 ). 
     The operation of the keying pulse processing circuit KC according to the present invention is further described in connection with FIG. 2. 
     Before time t 1   
     Because the signal S2 stays at &#34;0&#34;, the signals S3 and S4 are both set at &#34;0&#34;, according to the Table 1. 
     From time t 1  to t 2   
     At time t 1 , because the signal S2 changes to &#34;1&#34;, the signal S3 is set at &#34;1&#34; in response to the signal S2. However, the signal S4 stays at &#34;0&#34; for the period of τ 2 . Therefore, during this period, the signal S5 is set at &#34;0&#34;, according to Table 1. 
     From time t 2  to t 3   
     At time t 2 , i.e. after the time lapse of τ 2  from t 1 , the signal S4 changes to &#34;1&#34; while the signals S2 and S3 are still at &#34;0&#34;. Therefore, the signals S3 and S4 are both at &#34;1&#34;, and thus the signal S5 is set at &#34;0&#34;, according to Table 1. 
     From time t 3  to t 4   
     At time t 3 , i.e. after the time lapse of τ 1  from t 1 , the signal S3 returns to &#34;0&#34;, but the signals S2 and S4 stays at &#34;1&#34;. Thus the signal S5 is set at &#34;1&#34;, according to Table 1. 
     From time t 4  to t 5   
     At time t 4 , i.e. after the time lapse of τ from t 1 , the signals S2 returns to &#34;0&#34;, while the signals S3 and S4 remain at &#34;0&#34; and &#34;1&#34;, respectively. Therefore, the signal S5 is set at &#34;1&#34;, according to Table 1. 
     From time t 5  to t 6   
     At time t 5 , i.e. after the time lapse of τ from t 2 , the signals S2 and S3 are still at &#34;0&#34;, and the signal S4 is set at &#34;0&#34;. Therefore the signal S5 is set at &#34;0&#34;, according to Table 1. 
     From time t 6  to t 7   
     At time t 6 , because the signal S2 as produced from the wave shaping circuit 2 changes to &#34;1&#34;, the signal S3 is set at &#34;1&#34; in response to the signal S2. The signals S2 and S3 stay at &#34;1&#34; for a period of rx representing a noise pulse width and a period of τ 1 , respectively. Therefore, the signal S5 is set at &#34;0&#34;, according to Table 1. 
     From time t 7  to t 7   
     At time t 7 , i.e. after the time lapse of τ 2  from t 6 , the signals S2 and S3 are still at &#34;1&#34;, and the signal S 4  is set at &#34;1&#34;. Therefore, the signal S5 is set at &#34;0&#34;, according to Table 1. 
     From time t 8  to t 9   
     At time t 8 , i.e. after the time lapse of τ N  from t 6 , the signal S2 returns to &#34;0&#34;, but the signals S3 and S4 remain at &#34;1&#34;. Thus, the signal S5 is set at &#34;0&#34;, according to Table 1. 
     From time t 9  to t 10   
     At time t 9 , i.e. after the time lapse of τ N  from time t 7 , the signals S2 and S3 are still at &#34;0&#34; and &#34;1&#34;, respectively, but the signal S4 is set at &#34;0&#34;. Therefore, the signal S5 is set at &#34;0&#34;, according to Table 1. 
     From time t 10  to t 11   
     At time t 10 , i.e. after the time lapse of τ 1  from t6, the signals S2 and S4 are still at &#34;0&#34;, but S3 is set at &#34;0&#34;. Therefore, the signal S5 is at &#34;0&#34;. 
     After time t 11   
     At time t 10 , because the next keying pulse is produced, the pulses of signals S1, S2, S3, S4 and S5 become the same as that described previously. 
     As described above, when a noise pulse having a width τ N  less than the difference between τ 1  and τ 2  (τ N  ≦τ 1  -τ 2 ) is included in the keying signal S1, such a noise pulse is eliminated from the noise canceled keying signal S5 generated by the keying pulse processing circuit KC of the present invention. 
     According to the above embodiment, the noise canceled signal S5 is delayed by the delay time τ 2 , and the leading edge of the keying pulses therein is delayed by an amount of τ 1  when compared with the keying signal S4. In the case where such delays adversely affect the operation, the delay τ 2  can be counterbalanced with a suitable phase advancing device inserted in a transmission system and the problem of the delay τ 1  can be eliminated by using the trailing edge, instead of the leading edge, as a reference for processing the signal in the processing system. 
     As described hereinabove, it is possible to provide a keying pulse processing circuit KC which can remove the noise pulses having a pulse width less than a predetermined pulse width (τ 1  -τ 2 ) with a very simple construction without using a waveform memory or a feed-back system. Thus, it is possible to realize a circuit which can operate at a high speed and is suitable for an integrated circuit. 
     Although the present invention has been fully described in connection with the preferred embodiments thereof with reference to the accompanying drawings, it is to be noted that various changes and modifications are apparent to those skilled in the art. Such changes and modifications are to be understood as included within the scope of the present invention as defined by the appended claims unless they depart therefrom.