Abstract:
A semiconductor memory device includes: A method of manufacturing a semiconductor device, wherein a semiconductor chip is mounted on a lead frame including a plurality of lead lines, and terminals included in the semiconductor chip are connected to the lead lines, thereby to manufacture the semiconductor device, comprising the steps of:
       arranging distal end parts of the plurality of lead lines at equal intervals along a direction of a first axis, the distal end parts being connected with the terminals included in the semiconductor chip;   arranging terminal parts for inputting/outputting signals, at equal intervals along a direction of a second axis;   shaping intermediate parts for connecting the distal end parts and the terminal parts, so as to be bent between the distal end parts and the terminal parts;   forming a half number of the plurality of lead lines and the remaining half number of the plurality of lead lines so as to have a shape of line symmetry with respect to the second axis; and mounting the semiconductor chip on a front surface side of a package.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2007-42108, filed Feb. 22, 2007, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention has for its object to provide a method of manufacturing a semiconductor device which can cope with any assembly technique and whose size is reduced, and such a semiconductor device. 
         [0004]    2. Description of the Related Art 
         [0005]    Heretofore, in case of encapsulating a semiconductor chip within a package, a configuration has been employed wherein the semiconductor chip is mounted over (or under) a lead frame. The optimal array sequence of bonding pads in the semiconductor chip is determined by such conditions as the type of the package and the method of mounting, and it differs depending upon individual conditions. Accordingly, a semiconductor chip dedicated to each package is often prepared by, for example, changing the metal layer of the semiconductor chip in accordance with the type of the package, the method of mounting and other conditions. 
         [0006]    A TSOP (Thin Small Outline Package) is one of those packages of semiconductor chips which is used extensively. Therefore, many semiconductor manufactures adopt the TSOP. Besides, the semiconductor manufacturers often outsource the assembly process of the TSOP to assemblers in order to lower the cost of this process. 
         [0007]    In case of outsourcing the assembly process in this manner, the selection of the assembler becomes very important. The semiconductor manufacturer wants to suppress the assembling cost as much as possible. However, if the assembler offering a low assembling cost does not have a technique required by the semiconductor manufacturer, the semiconductor manufacturer cannot adopt the assembler. Besides, an assembler which uses a special technique (for example, a technique which mounts semiconductor chips on the top and bottom of a lead frame) which exceeds the requirements of the semiconductor manufacturer, frequently demands a high price. That is, a method of manufacturing a semiconductor device which can cope with any assembly technique needs to be provided in order that the semiconductor manufacturer may suppress the assembly process cost to a minimum. Besides, when the circuit of the semiconductor chip to be encapsulated within the TSOP is configured so as to be capable of coping with any assembly process, increase the size of the semiconductor chip. 
       BRIEF SUMMARY OF THE INVENTION 
       [0008]    A method of manufacturing a semiconductor device, wherein a semiconductor chip is mounted on a lead frame including a plurality of lead lines, and terminals included in the semiconductor chip are connected to the lead lines, thereby to manufacture the semiconductor device, comprising the steps of: 
         [0009]    arranging distal end parts of the plurality of lead lines at equal intervals along a direction of a first axis, the distal end parts being connected with the terminals included in the semiconductor chip; 
         [0010]    arranging terminal parts for inputting/outputting signals, at equal intervals along a direction of a second axis; 
         [0011]    shaping intermediate parts for connecting the distal end parts and the terminal parts, so as to be bent between the distal end parts and the terminal parts; 
         [0012]    forming a half number of the plurality of lead lines and the remaining half number of the plurality of lead lines so as to have a shape of line symmetry with respect to the second axis; and 
         [0013]    mounting the semiconductor chip on a front surface side of a package. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
         [0014]      FIG. 1  is a top view showing a semiconductor chip for use in an example of the manufacturing process of a semiconductor device; 
           [0015]      FIG. 2  is a top view showing a lead frame for use in an example of the manufacturing process of the semiconductor device; 
           [0016]      FIG. 3  is a side view showing the lead frame for use in the example of the manufacturing process of the semiconductor device; 
           [0017]      FIG. 4  is a top view showing a state where the semiconductor chip is mounted on the top of the lead frame in accordance with the example of the manufacturing process of the semiconductor device; 
           [0018]      FIG. 5  is a top view showing a state where the semiconductor chip is mounted on the bottom of the lead frame in accordance with the example of the manufacturing process of the semiconductor device; 
           [0019]      FIG. 6  is a schematic view of a method of manufacturing a semiconductor device according to an embodiment of the present invention; 
           [0020]      FIG. 7  is a top view showing a semiconductor chip for use in the manufacturing process of the semiconductor device according to the embodiment of the invention; 
           [0021]      FIG. 8  is a top view showing a first lead frame for use in the manufacturing process of the semiconductor device according to the embodiment of the invention; 
           [0022]      FIG. 9  is a top view showing a second lead frame for use in the manufacturing process of the semiconductor device according to the embodiment of the invention; 
           [0023]      FIG. 10  is a top view showing a state where the semiconductor chip has been mounted on the bottom of the first lead frame by the manufacturing process of the semiconductor device according to the embodiment of the invention; 
           [0024]      FIG. 11  is a side view showing the state where the semiconductor chip has been mounted on the bottom of the first lead frame by the manufacturing process of the semiconductor device according to the embodiment of the invention; 
           [0025]      FIG. 12  is a bottom view showing the state where the semiconductor chip has been mounted on the bottom of the first lead frame by the manufacturing process of the semiconductor device according to the embodiment of the invention; 
           [0026]      FIG. 13  is a top view showing a state where the semiconductor chip has been mounted on the top of the second lead frame by the manufacturing process of the semiconductor device according to the embodiment of the invention; 
           [0027]      FIG. 14  is a side view showing the state where the semiconductor chip has been mounted on the top of the second lead frame by the manufacturing process of the semiconductor device according to the embodiment of the invention; 
           [0028]      FIG. 15  is a bottom view showing the state where the semiconductor chip has been mounted on the top of the second lead frame by the manufacturing process of the semiconductor device according to the embodiment of the invention; 
           [0029]      FIG. 16  is a top view of a semiconductor device according to an embodiment of the invention; 
           [0030]      FIG. 17  is a side view of the semiconductor device according to the embodiment of the invention; and 
           [0031]      FIG. 18  is a bottom view of the semiconductor device according to the embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0032]    First, an example in the case where one semiconductor chip is accommodated in a TSOP package or where a plurality of semiconductor chips are stacked and accommodated in a single TSOP package will be described with reference to  FIGS. 1-5 . 
         [0033]      FIG. 1  is a top view of a semiconductor chip  31 ,  FIG. 2  is a top view of a lead frame  33 , and  FIG. 3  is a side view of the lead frame  33 . 
         [0034]    As shown in  FIG. 1 , the semiconductor chip  31  is in the shape of a rectangular plate, and twelve bonding pads  31 P 1 - 31 P 12  which are rectilinearly arrayed are formed in the vicinity of an end part of one surface of the semiconductor chip  31 . Besides, an input circuit  311 , a protection circuit  312  and an output circuit  313  are connected to each of the bonding pads  31 P 1 ,  31 P 6 ,  31 P 7  and  31 P 12  of the semiconductor chip  31 . That is, each of the bonding pads  31 P 1 ,  31 P 6 ,  31 P 7  and  31 P 12  includes all of the input circuit  311 , the protection circuit  312  and the output circuit  313 . 
         [0035]    As shown in  FIGS. 2 and 3 , an axis which extends in parallel with the lengthwise direction of the lead frame  33  is set as a first axis X, and an axis which passes through the center of the lead frame  33  and which intersects orthogonally to the first axis X is set as a second axis Y. Besides, an axis which intersects orthogonally to the first axis X and the second axis Y is set as a third axis Z. In  FIG. 2 , the package to be sealed is indicated by a broken line. 
         [0036]    The lead frame  33  consists of twelve lead lines  33 A 1 - 33 A 12 . The individual lead lines  33 A 1 - 33 A 12  have their distal end parts  331  arranged along the long edge of the package in parallel with the first axis X and at equal intervals, and they can be electrically connected to the bonding pads  31 P 1 - 31 P 12 , respectively. Besides, each of the lead lines  33 A 1 - 33 A 12  includes an intermediate part  332  and a terminal part  333  which are joined with the distal end part  331 . The intermediate part  332  is formed so as to connect the distal end part  331  and the terminal part  333 , within a plane which contains the first axis X and the second axis Y. That is, the intermediate part  332  is formed so as to extend in a direction parallel to the second axis Y, from the distal end part  331 , to be thereafter bent and to extend in the direction of the first axis X and reach the terminal part  333 . The terminal parts  333  are arranged along the short edge of the package in parallel with the second axis Y and at equal intervals. These terminal parts  333  are formed so as to be bent in the direction of the third axis Z, namely, in a direction perpendicular to the sheet of drawing in  FIG. 2 , and to protrude onto the bottom side of the package. 
         [0037]    Among the lead lines  33 A 1 - 33 A 12 , those  33 A 1 - 33 A 6  have their terminal parts  333  arranged along the left short edge of the package as seen in  FIG. 2 , whereas those  33 A 7 - 33 A 12  have their terminal parts  333  arranged along the right short edge of the package. Accordingly, the lead lines  33 A 1 - 33 A 6  and those  33 A 7 - 33 A 12  are endowed with the shape of mirror symmetry with respect to the second axis Y. 
         [0038]    Besides, the lead lines  33 A 1  and  33 A 6  function as control signal terminals to which the control signals of the semiconductor chip  31  are inputted from the terminal parts  333 , and the lead lines  33 A 7  and  33 A 12  function as I/O terminals which are used for exchanging data inputted from and outputted to the terminal parts  333 . 
         [0039]    Next, there will be described a state where the semiconductor chip  31  is arranged on the top or bottom of the lead frame  33 .  FIG. 4  is a top view of the package in the case of employing a top arrangement technique in which the semiconductor chip  31  is mounted on the top of the lead frame  33 , while  FIG. 5  is a top view of the package in the case of employing a bottom arrangement technique in which the semiconductor chip  31  is mounted on the bottom of the lead frame  33 . The pads  31 P 1 - 31 P 12 , and the plurality of lead lines  33 A 1 - 33 A 12  are respectively connected by bonding wires BW. Incidentally, the semiconductor chip  31  and the lead frame  33  are further covered with a sealing resin from the states shown in  FIGS. 4 and 5 , whereby the packaging of the semiconductor chip  31  is completed. 
         [0040]    Here, the notation  33 A 1 ( 31 P 1 ) means that the lead line  33 A 1  is connected to the bonding pad  31 P 1  of the semiconductor chip  31  in  FIG. 1 . Then, as shown in  FIG. 4 , connection relations in the case where the semiconductor chip  31  is connected to the lead frame  33  as shown in  FIG. 2 , by employing the top arrangement technique, become  33 A 1 ( 31 P 7 ), . . . ,  33 A 6 ( 31 P 12 ),  33 A 7 ( 31 P 6 ), . . . , and  33 A 12 ( 31 P 1 ). 
         [0041]    On the other hand, connection relations in the case where the semiconductor chip  31  in  FIG. 5  is connected to the lead frame  33  as shown in  FIG. 2 , by employing the bottom arrangement technique, become  33 A 1 ( 31 P 6 ), . . . ,  33 A 6 ( 31 P 1 ),  33 A 7 ( 31 P 7 ), . . . , and  33 A 12 ( 31 P 12 ). 
         [0042]    In this manner, in the above method for manufacturing a semiconductor device, the connection relations between the bonding pads  31 P 1 - 31 P 12  of the semiconductor chip and the lead lines  33 A 1 - 33 A 12  of the lead frame are mirrored along the second axis Y, depending upon whether the semiconductor chip is arranged on the top or bottom of the lead frame. As shown in  FIG. 1 , accordingly, the semiconductor chip  31  must have all of the input circuit  311 , the protection circuit  312  and the output circuit  313  connected to each of the bonding pads  31 P 1 ,  31 P 6 ,  31 P 7  and  31 P 12 , and the increase the size of the semiconductor chip  31  and the increase of a manufacturing cost. 
         [0043]    Besides, in order to avoid increasing of the size, there is considered a configuration in which only the input circuit  311  and the protection circuit  312  are connected to each of the bonding pads  31 P 1  and  31 P 6  of the semiconductor chip  31 , and in which the input circuit  311 , the protection circuit  312  and the output circuit  313  are connected to each of the bonding pads  31 P 7  and  31 P 12 , or a configuration in which the connections are opposite to the above. 
         [0044]    However, when the semiconductor chip  31  has such a configuration, physically the distances between the bonding pads and the distal end parts of the lead lines become long, and wiring lengths therefore increase to pose the problems that the parasitic resistance of the wiring lines increases and the operating speed is reduced. Further, since the wiring lengths increase, the wiring lines are prone to come into contact, and an increase of inductance, etc. will occur. 
         [0045]    Next, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be outlined with reference to  FIG. 6 .  FIG. 6  is a schematic view of the method of manufacturing the semiconductor device according to the first embodiment. 
         [0046]    As shown in  FIG. 6 , the method of manufacturing the semiconductor device according to the invention consists in manufacturing the semiconductor device by employing at least either of a first lead frame  13  and a second lead frame  15 , together with a semiconductor chip  11 . More specifically, in a case where the first lead frame  13  has been selected, the semiconductor chip  11  is mounted on the bottom of the first lead frame  13 , and in a case where the second lead frame  15  has been selected, the semiconductor chip  11  is mounted on the top of the second lead frame  15 . Now, the shapes of the semiconductor chip  11  and the first and second lead frames  13  and  15 , and the connection relations thereof for attaining such a configuration will be described in detail. 
         [0047]      FIG. 7  is a top view of the semiconductor chip  11 . Incidentally, as shown in  FIG. 7 , the semiconductor chip  11  is in the shape of a rectangular plate, and twelve bonding pads  11 p 1 - 11 P 12  which are arrayed rectilinearly are formed in the vicinity of an end part of one surface of the semiconductor chip  11 . Besides, an input circuit  111  and a protection circuit  112  are connected (an output circuit  113  is not connected) to each of the bonding pads  11 P 1  and  11 P 6  of the semiconductor chip  11 , whereas an input circuit  111 , a protection circuit  112  and an output circuit  113  are connected to each of the bonding pads  11 P 7  and  11 P 12 . 
         [0048]      FIG. 8  is a top view of the first lead frame  13 . Incidentally, a broken line in  FIG. 8  indicates a package to be sealed. As shown in  FIG. 8 , the first lead frame  13  is configured of twelve lead lines  13 A 1 - 13 A 12 . The first lead frame  13  has the same shape as that of the lead frame  33  shown in  FIG. 2 . More specifically, the individual lead lines  13 A 1 - 13 A 12  have their distal end parts  131  arranged along the long edge of the package in parallel with a first axis X and at equal intervals, and they can be electrically connected to the bonding pads  11 P 1 - 11 P 12 , respectively. 
         [0049]    Besides, each of the lead lines  13 A 1 - 13 A 12  includes an intermediate part  132  and the terminal part  133  which are joined with the distal end part  131 . The intermediate part  132  is formed so as to connect the distal end part  131  and the terminal part  133 , within a plane which contains the first axis X and a second axis Y. That is, the intermediate part  132  is formed so as to extend in a direction parallel to the second axis Y, from the distal end part  131 , to be thereafter bent and to extend in the direction of the first axis X and reach the terminal part  133 . 
         [0050]    The terminal parts  133  are arranged along the short edges of the package in parallel with the second axis Y and at equal intervals. These terminal parts  133  are formed so as to be bent in the direction of a third axis Z, namely, in a direction perpendicular to the sheet of drawing in  FIG. 7 , and to protrude onto the bottom side of the package. 
         [0051]    Among the lead lines  13 A 1 - 13 A 12 , those  13 A 1 - 13 A 6  have their terminal parts  133  arranged along the left short edge of a package substrate  12  as seen in  FIG. 8 , whereas those  13 A 7 - 13 A 12  have their terminal parts  133  arranged along the right short edge of the package substrate  12 . Accordingly, the lead lines  13 A 1 - 13 A 6  and those  13 A 7 - 13 A 12  are mirror symmetric with respect to the second axis Y. 
         [0052]    Besides, the lead lines  13 A 1  and  13 A 6  function as control signal terminals to which the control signals of the semiconductor chip  11  are inputted from the terminal parts  133 , and the lead lines  13 A 7  and  13 A 12  function as I/O terminals which are used for exchanging data inputted from and outputted to the terminal parts  133 . 
         [0053]      FIG. 9  is a top view of the second lead frame  15 . Incidentally, a broken line in  FIG. 9  indicates a package to be sealed. As shown in  FIG. 9 , the second lead frame  15  is configured of twelve lead lines  15 A 1 - 15 A 12 . Each of the lead lines  15 A 1 - 15 A 12  includes an intermediate part  152  in a shape in which the intermediate part  132  of the first lead frame  13  is inverted in symmetry with respect to the first axis X. Besides, likewise to the first lead frame  13 , the second lead frame  15  includes distal end parts  151  and terminal parts  153 . Unlike in the first lead frame  13 , the distal end parts  151  are disposed on a side opposite to the long edge of the package (namely, on the upper edge as seen in  FIG. 9 ). 
         [0054]    Next, a state where the semiconductor chip  11  has been arranged on the bottom of the first lead frame  13  by a bottom arrangement technique will be described with reference to  FIGS. 10-12 . Incidentally, broken lines in  FIGS. 10 and 12  indicate the package to be sealed.  FIG. 10  is a top view showing the state where the semiconductor chip  11  has been arranged on the bottom of the first lead frame  13 ,  FIG. 11  is a corresponding side view, and  FIG. 12  is a corresponding bottom view. Here, letting sign  13 A 1 ( 11 P 6 ) indicate that the lead line  13 A 1  is connected to the bonding pad  11 P 6 , connection relations shown in  FIGS. 10-12  become  13 A 1 ( 11 P 6 ), . . . ,  13 A 6 ( 11 P 1 ),  13 A 7 ( 11 P 7 ), . . . , and  13 A 12 ( 11 P 12 ). 
         [0055]    Next, a state where the semiconductor chip  11  has been arranged on the top of the second lead frame  15  by a top arrangement technique will be described with reference to  FIGS. 13-15 . Incidentally, broken lines in  FIGS. 13 and 15  indicate the package to be sealed.  FIG. 13  is a top view showing the state where the semiconductor chip  11  has been arranged on the top of the second lead frame  15 ,  FIG. 14  is a corresponding side view, and  FIG. 15  is a corresponding bottom view. Here, letting sign  15 A 1 ( 11 p 1 ) indicate that the lead line  15 A 1  is connected to the bonding pad  11 P 1 , connection relations shown in  FIGS. 13-15  become  15 A 1 ( 11 P 1 ), . . . ,  15 A 6 ( 11 P 6 ),  15 A 7 ( 11 P 7 ), . . . , and  15 A 12 ( 11 P 12 ). 
         [0056]    As thus far described, in this embodiment, either of the first lead frame  13  and the second lead frame  15  is selected and is attached to the semiconductor chip  11 , depending upon which of the bottom arrangement and the top arrangement the semiconductor chip  11  is mounted by. The first lead frame  13  and the second lead frame  15  have the shapes inverted vertically as stated above, and the connection relations between the lead lines and the corresponding bonding pads are not inverted across the second axis Y. As shown in  FIG. 7 , accordingly, only the input circuit  111  and the protection circuit  112  may be connected to each of the bonding pads  11 P 1  and  11 P 6  of the semiconductor chip  11 . As compared with the semiconductor chip stated before, therefore, the semiconductor chip of the embodiment can omit some of the circuits, and the size of the semiconductor chip is reduced. 
         [0057]    Incidentally, contrariwise to the above example, the semiconductor chip  11  may well be arranged on the top of the first lead frame  13  and on the bottom of the second lead frame  15 . 
         [0058]    Next, a semiconductor device according to an embodiment of the invention will be described with reference to  FIGS. 16-18 .  FIG. 16  is a top view of the semiconductor device according to the embodiment of the invention,  FIG. 17  is a corresponding side view, and  FIG. 18  is a corresponding bottom view. 
         [0059]    As shown in  FIGS. 16-18 , the semiconductor device includes a substrate  21 , semiconductor chips  22  and  22  which are disposed on both the surfaces of the substrate  21 , and a lead frame  23  which is disposed in the substrate  21  and which is configured of a plurality of leads that are electrically connected to the semiconductor chips  22  and  22 . 
         [0060]    Each of the semiconductor chips  22  and  22  is in the shape of a rectangular plate, and twelve bonding pads  22 P 1 - 22 P 12  which are arrayed rectilinearly are formed in the vicinity of an end part of one surface of each semiconductor chip. Besides, an input circuit and a protection circuit are connected to each of the bonding pads  22 P 1  and  22 P 6  of the semiconductor chip  22 , while an input circuit, a protection circuit and an output circuit are connected to each of the bonding pads  22 P 7  and  22 P 12  (omitted from illustration). 
         [0061]    Here, an axis which extends in parallel with the lengthwise direction of the substrate  21  in the vicinity of the end part thereof is set as a first axis X, and an axis which passes through the center of the substrate  21  and which extends in parallel with a widthwise direction intersecting orthogonally to the first axis X is set as a second axis Y. Besides, an axis which intersects orthogonally to the first axis X and the second axis Y is set as a third axis Z. 
         [0062]    The lead frame  23  consists of a first lead frame  24  and a second lead frame  25  each of which is configured of a plurality of lead lines. 
         [0063]    As shown in  FIGS. 16-18 , the first lead frame  24  is configured of twelve lead lines  24 A 1 - 24 A 12 . The individual lead lines  24 A 1 - 24 A 12  have their distal end parts  241  arranged on the first axis X in parallel and at equal intervals, and they are electrically connected to the bonding pads  22 . Besides, the first lead frame  24  extends in a first direction parallel to the second axis Y from the distal end parts  241 , within a plane containing the first axis X and the second axis Y, and it also extends in a second direction parallel to the first axis X and in a third direction opposite to the second direction, in symmetry with respect to the second axis Y, thereby to form terminal parts  242  at its terminal ends, respectively. The terminal parts  242  are formed so as to be exposed from the front surface of the substrate  21 . 
         [0064]    The second lead frame  25  is configured of twelve lead lines  25 A 1 - 25 A 12  which have such a shape that the lead lines of the first lead frame  24  are inverted with respect to the first axis X. Incidentally, likewise to the first lead frame  24 , the second lead frame  25  includes distal end parts  251  and terminal parts  252 . Besides, the distal end parts  251  of the respective lead lines  25 A 1 - 25 A 12  are connected to the bonding pads  22 P 1 - 22 P 12  of the semiconductor chip  22 . 
         [0065]    Besides, the respective lead lines  25 A 1 - 25 A 12  of the second lead frame  25  are connected to the corresponding lead lines  24 A 1 - 24 A 12  of the first lead frame  24 . 
         [0066]    As stated above, the second lead frame  25  is formed by inverting the first lead frame  24  with respect to the second axis Y, so that the connection relations between the lead frame and the semiconductor chips are not inverted astride (beyond) the second axis Y. It is accordingly permitted to provide the semiconductor device in which the semiconductor chips  22  and  22  of simplified circuit arrangement are arranged on both the surfaces of the substrate  21 . Moreover, the first and second lead frames  24  and  25  are formed having small occupation areas. It is therefore permitted to provide the semiconductor device of still smaller size. 
         [0067]    Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.