Abstract:
Embodiments of the present invention provide Method and apparatus for coding of an E-DCH Dedicated Physical Control Channel (E-DPCCH). The method includes encoding information bits of signalling on an E-DPCCH in a BLOCK coding manner. The apparatus includes a unit for encoding information bits of signalling on an E-DPCCH in a BLOCK coding manner. The embodiments of the present invention can solve the problem in which signalling overhead is high during signalling encoding, thus reduce transmission power of a terminal.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to wireless communications, and more particularly, to a method and an apparatus for coding of an E-DPCCH (E-DCH (Enhanced Dedicated Channel) Dedicated Physical Control Channel).  
       BACKGROUND OF THE INVENTION  
       [0002]     Wideband Code Division Multiple Access (WCDMA) of which the system is being perfected represents one of the three main 3 rd  Generation ( 3 G) standards. In Release  5 , WCDMA introduces a High Speed Downlink Packet Access (HSDPA) technique, which has been one of the most important characters of Release  5 . The HSDPA technique, which enables the throughput of the WCDMA downlink to be two to three times the throughput provided by the prior releases, can be an effective bearer of various packet services, satisfying the demand for such multimedia service information as data, video, image and the like apart from voice anywhere at any moment.  
         [0003]     Correspondingly, it is considered to introduce the standard of a High Speed Uplink Packet Access (HSUPA) technique into Release  6  of WCDMA. The core target of the HSUPA technique is to enable the throughput of a WCDMA uplink to increase by 50% to 70% than that provided by the prior releases to enhance the throughput of uplink packet data using several enhanced uplink techniques. HSUPA technique is an up-to-date technique, and the standard of HSUPA technique in Release  6  of a WCDMA system protocol is being shaped.  
         [0004]     At present, while which coding manner will be adopted for an E-DPCCH of HSUPA technique has not been specified, the main technical solution is to adopt a Convolutional Coding (CC) manner. The CC in WCDMA defines two coding rates of which one is ½ and the other is ⅓, and the constraint length is 9; tail bits having 8 bits of value 0 often need to be added to the coding block to be encoded so as to assist the CC. Although the CC is a mature coding technique, adding 8-bit tail bits to the coding block will bring a considerable signalling overhead for an E-DPCCH due to fewer effective bits of signalling on an E-DPCCH.  
       SUMMARY OF THE INVENTION  
       [0005]     Embodiments of the present invention provide a method and an apparatus for coding of an E-DCH Dedicated Physical Control Channel (E-DPCCH), encoding an E-DPCCH with lower signalling coding overhead.  
         [0006]     According to an embodiment, the method for coding of an E-DPCCH includes:  
         [0007]     encoding information bits of signalling on an E-DPCCH in a BLOCK coding manner.  
         [0008]     Said encoding the information bits of signalling includes:  
         [0009]     encoding information bits of signalling on an E-DPCCH in the BLOCK coding manner if the number of the information bits of signalling on an E-DPCCH is not more than a threshold.  
         [0010]     Said encoding information bits of signalling on an E-DPCCH in the BLOCK coding manner includes:  
         [0011]     dividing the information bits of signalling on an E-DPCCH into at least one data block;  
         [0012]     encoding the data block.  
         [0013]     Said encoding the data block includes:  
         [0014]     encoding the data block with a second-order Reed-Muller encoder.  
         [0015]     Said encoding the data block with the second-order Reed-Muller encoder includes:  
         [0016]     inputting the data block to be encoded into the second-order Reed-Muller encoder;  
         [0017]     calculating output codeword bits according to the following formula:  
           b   i     =       ∑     n   =   0       N   -   1       ⁢       (       a   n     ×     M     i   ,   n         )     ⁢   mod   ⁢           ⁢   2         ;       
 
         [0018]     wherein i is the sequence number of output codeword bits, N is the number of the data block to be encoded, n=0, 1, 2, 3 . . . N-1, a n  is the n-th bit of the data block to be encoded, M i, n  is the i-th value of the n-th basic sequence, and b i  is the i-th bit of the output codeword bits.  
         [0019]     Said encoding the data block with the second-order Reed-Muller encoder further includes:  
         [0020]     selecting a part of the output codeword bits as codeword of the information bits.  
         [0021]     According to another embodiment, the apparatus for coding of an E-DCH Dedicated Physical Control Channel (E-DPCCH) includes:  
         [0022]     a unit for encoding information bits of signalling on an E-DPCCH in a BLOCK coding manner.  
         [0023]     The unit includes:  
         [0024]     a module for dividing the information bits of signalling on an E-DPCCH into at least one data block;  
         [0025]     a module for encoding the data block in the BLOCK coding manner.  
         [0026]     The module is a BLOCK encoder.  
         [0027]     For example, the BLOCK encoder is a second-order Reed-Muller encoder.  
         [0028]     The module includes a plurality of BLOCK encoders, used for encoding different numbers of the information bits.  
         [0029]     For example, the BLOCK encoders are second-order Reed-Muller encoders.  
         [0030]     Through analyzing the overhead of the information bits of signalling on an E-DPCCH in the CC manner, an embodiment of the present invention provides a BLOCK coding manner for the signalling on an E-DPCCH, that is, the information bits to be transferred is divided into at least one data block for encoding, thereby reducing signalling overhead and saving transmission power of a terminal. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0031]      FIG. 1  is a simplified diagram illustrating a channel coding process of information bits of signalling in accordance with an embodiment of the present invention.  
         [0032]      FIG. 2  is a simplified schematic flowchart of a coding process in accordance with an embodiment of the present invention.  
         [0033]      FIG. 3  is a simplified schematic flowchart of a coding process in accordance with another embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0034]     The present invention is hereinafter further described in detail with reference to the accompanying drawings and preferred embodiments to further clarify the technical solutions and advantages of the present invention.  
         [0035]     Though almost all coding techniques conventionally used are maturely, a CC technique, as a coding technique with simple implementation and high encoding performance, is adopted widely in the art. However, tail bits having 8 bits of value 0 often need to be added to the coding block before being encoded so as to assist the CC during the coding procedure thereof adopted in a WCDMA system, which has little impact on the case that the information bits to be encoded are relatively more but brings obvious waste of power (about 2.6 dB) in the case that information bits are fewer, especially in the case of signalling coding. An embodiment of the present invention provides a BLOCK coding in view of the characteristic that information bits of signalling are fewer on an E-DPCCH.  
         [0036]     Descriptions are given hereinafter with an example of the coding process of an E-DPCCH in a WCDMA system.  
         [0037]     An embodiment of the present invention describes the coding process, for example in the case that the number of information bits of signalling is  10 . As shown in  FIG. 1 , a BLOCK coding is performed with a ( 32 ,  10 ) second-order Reed-Muller encoder which may generate 32-bit output codes after encoding if 10 bits are inputted. The encoder has, for example, the combinations of 10 basic sequences which are listed in Table 1. As shown in Table 2, for example, the basic sequences M i, 0 , M i, 1 , M i, 2 , M i, 3 , M i, 4 , M i, 5 , M i, 6 , M i, 7 , M i, 8  and M i, 9  (i=0, 1, 2, . . . , 31).  
                                                                                                     TABLE 1                       i   M i,0     M i,1     M i,2     M i,3     M i,4     M i,5     M i,6     M i,7     M i,8     M i,9                                  0   1   0   0   0   0   1   0   0   0   0       1   0   1   0   0   0   1   1   0   0   0       2   1   1   0   0   0   1   0   0   0   1       3   0   0   1   0   0   1   1   0   1   1       4   1   0   1   0   0   1   0   0   0   1       5   0   1   1   0   0   1   0   0   1   0       6   1   1   1   0   0   1   0   1   0   0       7   0   0   0   1   0   1   0   1   1   0       8   1   0   0   1   0   1   1   1   1   0       9   0   1   0   1   0   1   1   0   1   1       10   1   1   0   1   0   1   0   0   1   1       11   0   0   1   1   0   1   0   1   1   0       12   1   0   1   1   0   1   0   1   0   1       13   0   1   1   1   0   1   1   0   0   1       14   1   1   1   1   0   1   1   1   1   1       15   1   0   0   0   1   1   1   1   0   0       16   0   1   0   0   1   1   1   1   0   1       17   1   1   0   0   1   1   1   0   1   0       18   0   0   1   0   1   1   0   1   1   1       19   1   0   1   0   1   1   0   1   0   1       20   0   1   1   0   1   1   0   0   1   1       21   1   1   1   0   1   1   0   1   1   1       22   0   0   0   1   1   1   0   1   0   0       23   1   0   0   1   1   1   1   1   0   1       24   0   1   0   1   1   1   1   0   1   0       25   1   1   0   1   1   1   1   0   0   1       26   0   0   1   1   1   1   0   0   1   0       27   1   0   1   1   1   1   1   1   0   0       28   0   1   1   1   1   1   1   1   1   0       29   1   1   1   1   1   1   1   1   1   1       30   0   0   0   0   0   1   0   0   0   0       31   0   0   0   0   1   1   1   0   0   0                  
 
         [0038]     Referring to  FIG. 2 , a specific BLOCK coding process of the embodiment is as follows.  
         [0039]     Step  101 : information bits to be encoded are divided into at least one data block, each data block consists of 10 bits and is inputted into the (32, 10) encoder.  
         [0040]     10-bit information bits are, for example, considered as a data block, and the data block is inputted into the encoder in turn as a 0 , a 1 , a 2 , a 3 , a 4 , a 5 , a 6 , a 7 , a 8  and a 9  (corresponding to information bits index which is expressed in unsigned binary form), respectively.  
         [0041]     Step  102 : the encoder generates 32-bit codes from 10-bit codes.  
         [0042]     The output codeword bits corresponding to the information bits index are, for example, given by:  
           b   i     =       ∑     n   =   0     9     ⁢       (       a   n     ×     M     i   ,   n         )     ⁢   mod   ⁢           ⁢   2         ;       
 
         [0043]     where i is the sequence number of the output codeword bits, M i, n  is the i-th value of the n-th basic sequence shown in Table 1, and b i  (i=0, 1, 2, . . . , 31) denote the output codeword bits.  
         [0044]     Step  103 : b i  (i=0, 1, 2, . . . , 29) are selected as 30-bit codeword of the information bits.  
         [0045]     Step  104 : perform a spread-spectrum process of the 30-bit codeword.  
         [0046]     For example, three slots, namely 2 ms slots are obtained by using an S=256 spread-spectrum device, and sent on an E-DPCCH.  
         [0047]     The above is the coding process in the case that the number of the information bits of signalling is 10. For different numbers of information bits of signalling on an E-DPCCH, different coding processes can be implemented by selecting different encoders according to the number of the information bits. For example, in the case that the number of the information bits is 12, a (32, 12) second-order Reed-Muller encoder which may generate 32-bit output codes upon encoding if 12 bits are inputted is needed, that is, a new combination of basic sequences, namely 12 basic sequences shown as Table 2, needs to be constructed. As shown in Table 3, for example, the basic sequences consist of M i, 0 , M i, 1 , M i, 2 , M i, 3 , M i, 4 , M i, 5 , M i, 6 , M i, 7 , M i, 8 , M i, 9 , M i, 10  and M i, 11  (i=0, 1, 2, . . . , 31).  
                                                                                                                     TABLE 2                       i   M i,0     M i,1     M i,2     M i,3     M i,4     M i,5     M i,6     M i,7     M i,8     M i,9     M i,10     M i,11                                  0   1   1   1   1   1   1   0   0   0   0   0   0       1   1   1   1   1   1   0   0   0   0   1   0   0       2   1   1   1   1   0   1   0   0   1   0   0   1       3   1   1   1   1   0   0   0   0   1   1   0   1       4   1   1   1   0   1   1   0   1   0   0   1   0       5   1   1   1   0   1   0   0   1   0   1   1   0       6   1   1   1   0   0   1   0   1   1   0   1   1       7   1   1   1   0   0   0   0   1   1   1   1   1       8   1   1   0   1   1   1   1   0   0   0   1   1       9   1   1   0   1   1   0   1   0   0   1   1   1       10   1   1   0   1   0   1   1   0   1   0   1   0       11   1   1   0   1   0   0   1   0   1   1   1   0       12   1   1   0   0   1   1   1   1   0   0   0   1       13   1   1   0   0   1   0   1   1   0   1   0   1       14   1   1   0   0   0   1   1   1   1   0   0   0       15   1   1   0   0   0   0   1   1   1   1   0   0       16   1   0   1   1   1   1   1   1   1   1   0   0       17   1   0   1   1   1   0   1   1   1   0   0   0       18   1   0   1   1   0   1   1   1   0   1   0   1       19   1   0   1   1   0   0   1   1   0   0   0   1       20   1   0   1   0   1   1   1   0   1   1   1   0       21   1   0   1   0   1   0   1   0   1   0   1   0       22   1   0   1   0   0   1   1   0   0   1   1   1       23   1   0   1   0   0   0   1   0   0   0   1   1       24   1   0   0   1   1   1   0   1   1   1   1   1       25   1   0   0   1   1   0   0   1   1   0   1   1       26   1   0   0   1   0   1   0   1   0   1   1   0       27   1   0   0   1   0   0   0   1   0   0   1   0       28   1   0   0   0   1   1   0   0   1   1   0   1       29   1   0   0   0   1   0   0   0   1   0   0   1       30   1   0   0   0   0   1   0   0   0   1   0   0       31   1   0   0   0   0   0   0   0   0   0   0   0                  
 
         [0048]     Another embodiment of the present invention provides different coding process of encoding different numbers of information bits.  
         [0049]     Referring to  FIG. 3 , a specific BLOCK coding process of the embodiment is as follows.  
         [0050]     Step  201 : judge whether the number of the information bits of signalling is more than 12; if yes, execute the process of CC; otherwise, proceed to Step  202 .  
         [0051]     Step  202 : perform the corresponding process of BLOCK encoding according to the number of the information bits.  
         [0052]     For example, if the number of the information bits is equal to 12; proceed to Step  203 .  
         [0053]     For example, if the number of the information bits is less than 10, it is padded with zeros to 10 bits by setting the most significant bits to zero, and then execute the coding process of encoding 10-bit information bits.  
         [0054]     For example, if the number of information bits is 10, execute the coding process of encoding 10-bit information bits.  
         [0055]     Because the number of the information bits of signalling on an E-DPCCH is 10 or 12, herein take the coding process in the case that the numbers of the information bits are 10 and 12 as an example to describe an embodiment of the present invention, and the coding process of other numbers of information bits may be analogical.  
         [0056]     Step  203 : the information bits to be encoded are divided into at least one data block, each data block consists 12 bits and is inputted into a ( 32 ,  12 ) encoder.  
         [0057]     12-bit information bits are, for example, considered as a data block and the data block is inputted into the encoder in turn as a 0 , a 1 , a 2 , a 3 , a 4 , a 5 , a 6 , a 7 , a 8 , a 9 , a 10  and a 11  (corresponding to information bits index which is expressed in unsigned binary form), respectively.  
         [0058]     Step  204 : the encoder generates 32-bit codes from 12-bit codes.  
         [0059]     The output codeword bits corresponding to the information bits index are, for example, given by:  
           b   i     =       ∑     n   =   0     11     ⁢       (       a   n     ×     M     i   ,   n         )     ⁢   mod   ⁢           ⁢   2         ;       
 
         [0060]     where i is the sequence number of the output codeword bits, M i, n  is the i-th value of the n-th basic sequence shown in Table 2, and b i  (i=0, 1, 2, . . . , 31) denote the output codeword bits.  
         [0061]     Step  205 : b i  (i=0, 1, 2, . . . , 29) are selected as 30-bit codeword of the information bits.  
         [0062]     Step  206 : perform a spread-spectrum process of the 30-bit codeword.  
         [0063]     For example, three slots, namely 2 ms slots are, obtained by using an S=256 spread-spectrum device, and sent on an E-DPCCH.  
         [0064]     Other encoders which may implement BLOCK coding also may be adopted. The BLOCK coding disclosed by an embodiment of the present invention is suitable for the situation that the overhead of CC exceeds a threshold. If the overhead of the tail bits in CC, for example, occupies more than 30% of all overhead, the BLOCK coding manner according to an embodiment of the present invention may be adopted for encoding. For example, on an E-DPCCH, NodeB scheduling information consists of at most 10 effective bits and a Hybrid Automatic Repeat Request (HARQ) consists of at most 12 effective bits. As shown in Table 3, in the CC manner, the numbers of signalling overhead of the tail bits of the NodeB scheduling information and HARQ information are 44% and 40%, respectively. While, in the BLOCK manner, for example, if the number of the information bits is less than 10, it is padded with zeros to 10 bits by setting the most significant bits to zero; if the number of the information bits is 8, the numbers of signalling overhead is more than 20%; if the number of the information bits are not less than 10, the number of signalling overhead is zero. It can be seen that signalling overhead may be reduced to zero or avoided in accordance with an embodiment of the present invention.  
         [0065]     The foregoing description is only preferred embodiments of the present invention and is not for use in limiting the protection scope thereof. All the modifications, equivalent replacements or improvements in the scope of the present invention&#39;s spirit and principles shall be included in the protection scope of the present invention.  
                           TABLE 3                           Number of   Number of   Signalling       Signalling contents   information bits   tail bits   overhead                   NodeB scheduling   10   8   44%       information       HARQ information   12   8   40%