Abstract:
A semiconductor device includes: a semiconductor substrate whose contour is a pentagon; a front-stage amplifier formed relatively near a vertex of the pentagon of the semiconductor substrate; and a rear-stage amplifier formed relatively near a side opposed to the vertex of the semiconductor substrate and amplifying an output from the front-stage amplifier.

Description:
BACKGROUND OF THE INVENTION 
     Field 
       [0001]    The present invention relates to a semiconductor device including a front-stage amplifier and a rear-stage amplifier formed on a semiconductor substrate. 
       Background 
       [0002]    Conventional monolithic microwave integrated circuits (MMICs) are formed on rectangular semiconductor substrates (see, for example, Koh Kanaya et al., “A Ku-band 20 W GaN-MMIC Amplifier with Built-in Linearizer”, 2014 IEEE). 
         [0003]    An ordinary MMIC is constituted of amplifiers in a plurality of stages, and the number of FETs in a rear stage is larger than the number of FETs in a front stage. Empty spaces therefore exist on the periphery of the front stage and it is difficult to reduce the chip cost by reducing the chip area. 
       SUMMARY 
       [0004]    In view of the above-described problems, an object of the present invention is to provide a semiconductor device capable of reducing the chip area to reduce the chip cost. 
         [0005]    According to the present invention, a semiconductor device includes: a semiconductor substrate whose contour is a pentagon; a front-stage amplifier formed relatively near a vertex of the pentagon of the semiconductor substrate; and a rear-stage amplifier formed relatively near a side opposed to the vertex of the semiconductor substrate and amplifying an output from the front-stage amplifier. 
         [0006]    In the present invention, the semiconductor substrate having a pentagonal contour is used, the front-stage amplifier is formed relatively near one vertex, and the rear-stage amplifier is formed relatively near the side opposed to the vertex. Empty spaces on the front stage side can thereby be reduced in comparison with the case of the conventional rectangular semiconductor substrate. The chip area can thus be reduced to reduce the chip cost. 
         [0007]    Other and further objects, features and advantages of the invention will appear more fully from the following description. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0008]      FIG. 1  is a plan view of a semiconductor device according to a first embodiment of the present invention. 
           [0009]      FIG. 2  is a plan view showing a state where pentagonal semiconductor substrates are arranged on a wafer. 
           [0010]      FIG. 3  is a plan view showing a state where conventional rectangular semiconductor substrates are arranged on a wafer. 
           [0011]      FIG. 4  is a plan view showing a semiconductor device according to a second embodiment of the present invention. 
           [0012]      FIG. 5  is a plan view showing a state where semiconductor substrates in isosceles triangle form are arranged on a wafer. 
           [0013]      FIG. 6  is a plan view showing a semiconductor device according to a third embodiment of the present invention. 
           [0014]      FIG. 7  is a plan view showing a state where semiconductor substrates in isosceles trapezoid form are arranged on a wafer. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0015]    A semiconductor device according to the embodiments of the present invention will be described with reference to the drawings. The same components will be denoted by the same symbols, and the repeated description thereof may be omitted. 
       First Embodiment 
       [0016]      FIG. 1  is a plan view of a semiconductor device according to a first embodiment of the present invention. The contour of the semiconductor substrate  1  is a pentagon having five vertices  2   a  to  2   e  and five sides  3   a  to  3   e.  The side  3   a  is opposed to the vertex  2   a.  The vertex  2   a  is placed on a perpendicular to the side  3   a  passing through the middle point of the side  3   a.  The sides  3   b  and  3   e  are parallel to each other and equal in length to each other. The sides  3   c  and  3   d  are equal in length to each other. 
         [0017]    An MMIC of a three-stage configuration is formed on the semiconductor substrate  1 . An amplifier  5  in the second stage amplifies outputs from an amplifier  4  in the first stage, and an amplifier  6  in the final stage amplifies outputs from the amplifier  5  in the second stage. The amplifier  4  in the first stage has two FETs  7   a  and  7   b.  The amplifier  5  in the second stage has four FETs  7   c  to  7   f.  The amplifier  6  in the final stage has eight FETs  7   g  to  7   n.  Thus, the number of transistors included in the amplifier  6  in the final stage is larger than the number of transistors included in the amplifier  4  in the first stage. 
         [0018]    Because the FETs in the amplifiers  4  to  6  are connected in a tournament fashion, the circuit is denser at the second stage than at the first stage and denser at the final stage than at the second stage. A combining circuit for combining outputs from the plurality of FETs of the amplifier  6  in the final stage and a multiplicity of pads are also disposed at the output side of the final stage. In a case where an MMIC of a three-stage configuration is formed on a conventional rectangular semiconductor substrate, empty spaces are left on the periphery of the second stage and larger empty spaces are left on the periphery of the first stage, because the size of the semiconductor substrate is selected according to the width of the final stage. 
         [0019]    In the present embodiment, therefore, the semiconductor substrate  1  having a pentagonal contour is used, the amplifier  4  in the first stage is formed relatively near one vertex  2   a,  and the amplifier  6  in the final stage is formed relatively near the side  3   a  opposed to the vertex  2   a.  Empty spaces on the front stage side can thereby be reduced in comparison with the case of the conventional rectangular semiconductor substrate. The chip area can thus be reduced to reduce the chip cost. 
         [0020]      FIG. 2  is a plan view showing a state where pentagonal semiconductor substrates are arranged on a wafer. The semiconductor substrates  1  are alternately arranged as illustrated and can thus be laid on the wafer with no margin. It is necessary, for realization of this arrangement, that the pentagonal shape of each semiconductor substrate  1  be a combination of an isosceles triangle including the vertex  2   a  and a rectangle including the side  3   a.    
         [0021]      FIG. 3  is a plan view showing a state where conventional rectangular semiconductor substrates are arranged on a wafer. The number of chips per wafer is increased in the present embodiment in comparison with the case of the conventional rectangular semiconductor substrates, thus reducing the manufacturing cost per unit MMIC. 
       Second Embodiment 
       [0022]      FIG. 4  is a plan view showing a semiconductor device according to a second embodiment of the present invention. In the second embodiment, the contour of the semiconductor substrate  1  is an isosceles triangle having two first and second equal sides  8   a  and  8   b  equal in length to each other, and a bottom side  8   c.  The front-stage amplifier  4  is formed relatively near a vertex  9  shared by the first and second equal sides  8   a  and  8   b  of the semiconductor substrate  1 , while the rear-stage amplifier  5  is formed relatively near the bottom side  8   c  of the semiconductor substrate  1 . Empty spaces on the front stage side can thereby be reduced in comparison with the case of the conventional rectangular semiconductor substrate. The chip area can thus be reduced to reduce the chip cost. 
         [0023]      FIG. 5  is a plan view showing a state where semiconductor substrates in isosceles triangle form are arranged on a wafer. The semiconductor substrates  1  are alternately arranged as illustrated and can thus be laid on the wafer with no margin. The number of chips per wafer is increased in comparison with the case of the conventional rectangular semiconductor substrates, thus reducing the manufacturing cost per unit MMIC. 
       Third Embodiment 
       [0024]      FIG. 6  is a plan view showing a semiconductor device according to a third embodiment of the present invention. In the third embodiment, the contour of the semiconductor substrate  1  is an isosceles trapezoid having an upper base  10   a  and a lower base  10   b  parallel to the upper base  10   a  and longer than the upper base  10   a.  The front-stage amplifier  4  is formed relatively near the upper base  10   a  of the semiconductor substrate  1 , while the rear-stage amplifier  5  is formed relatively near the lower base  10   b  of the semiconductor substrate  1 . Empty spaces on the front stage side can thereby be reduced in comparison with the case of the conventional rectangular semiconductor substrate. The chip area can thus be reduced to reduce the chip cost. 
         [0025]      FIG. 7  is a plan view showing a state where semiconductor substrates in isosceles trapezoid form are arranged on a wafer. The semiconductor substrates  1  are alternately arranged as illustrated and can thus be laid on the wafer with no margin. The number of chips per wafer is increased in comparison with the case of the conventional rectangular semiconductor substrates, thus reducing the manufacturing cost per unit MMIC. 
         [0026]    Obviously many modifications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described. 
         [0027]    The entire disclosure of Japanese Patent Application No. 2016-077526, filed on Apr. 7, 2016 including specification, claims, drawings and summary, on which the Convention priority of the present application is based, is incorporated herein by reference in its entirety.