Abstract:
The present invention achieves the stated input receiver goals by merging many of the different functions required into a single unit instead of serializing them in the more traditional fashion. The present invention provides a receiver circuit having both a source-follower pair of MOS transistors, and a source-coupled pair of MOS transistors. The connecting node between these two pairs is coupled to a sense amplifier. The simultaneous use of the source-follower pair, the source-coupled pair and the sense-amplifier transistors allows for fast amplification of the low-swing input to full-rail CMOS, when triggered by a CMOS input clock.

Description:
This is a continuation of application Ser. No. 08/896,934, filed Jul. 18, 1997, Provisional Application No. 60/038,901, filed on Feb. 28, 1997. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to receiver circuits, and in particular to clocked receivers for amplifying low-swing signals to full-rail CMOS. 
     Faster VLSI devices put an ever increasing demand on bandwidth requirements for point-to-point and distributed busses. Frequently these busses experience large overshoots and undershoots if an attempt is made to drive them to the full range of the power supply. One effective technique used to make these interfaces run faster without such noise problems is to reduce the voltage swings below the full supply rails. This creates a new requirement for fast, low-swing data receivers and output drivers. 
     The requirement that a data receiver must be fast implies that it must have high bandwidth internally. Since signals inside CMOS VLSI devices are typically distributed as full-swing signals for noise-immunity and ease of use, the receiver should also have gain to amplify from low-swing to full-swing. 
     However, VLSI amplifiers in general experience a limited gain-bandwidth product. Thus, if it is desired to amplify low swings to full-rail CMOS (gain), some speed (bandwidth) is usually lost. In order to overcome speed and bandwidth limitations, two or more gain stages are often put in series. This unfortunately results in higher latency to valid output data. Achieving low latency is very important because it effects the actual time required to get the first data off of a bus and into the device. Another desirable quality for a low-swing receiver is a large input common-mode voltage range. Frequently, the actual input voltage levels are determined by many other factors in the environment, such as output driver characteristics, line impedance, available power supplies, etc. An input receiver with a large common mode range can avoid further constraining the voltage range. In summary, basic desirable qualities for a low-swing receiver include 1) good gain, 2) low latency, and 3) large common mode range. As with many VLSI circuits, additional favorable qualities include small physical area and low power consumption. 
     Receivers in the prior art, such as that of U.S. Pat. No. 5,319,755, entitled “High Speed Bus System”, by Horowitz &amp; Lee, as illustrated in FIG. 1 have several undesirable characteristics which are avoided in this invention. 
     First, in Horowitz/Lee, the input differential data BusData and Vref are sampled by a full-CMOS passgate, which means that the P+ diffusion of the PFETs of T1 and T2 are connected directly to device pins. This can lead to a latch-up condition if the power-up sequence is not tightly controlled, i.e., the pin is powered up before the well. 
     Second, the circuit is dependent on the distribution of a bias voltage, labelled VBIAS. U.S. Pat. No. 5,023,488 of Gunning has a similar bias requirement. In general, input receivers are usually distributed across the full width of a VLSI device. Voltage bias lines running large distances across a mixed-signal CMOS device are frequently disturbed by coupling capacitances to adjacent high-speed wires or by the substrate itself. It can in practice be very difficult to distribute quiet voltage-bias wires in a noisy environment. 
     Third, the circuit makes use of the signals CLK and nCLK, with each going into complementary devices. If the skew between the rising edge of CLK and the falling edge of nCLK is not very well controlled, it can lead to a condition where the data feeds through from the master to the slave latch a phase earlier than desired. Lastly, the latency of this design is quite high, requiring at least one full clock cycle plus the clock-to-Q delay of the final sense-amplifier. 
     SUMMARY OF THE INVENTION 
     The present invention achieves the stated input receiver goals by merging many of the different functions required into a single unit instead of serializing them in the more traditional fashion. The present invention provides a receiver circuit having both a source-follower pair of MOS transistors, and a source-coupled pair of MOS transistors. The connecting nodes between these two pairs are coupled to a sense amplifier. The simultaneous use of the source-follower pair, the source-coupled pair and the sense-amplifier transistors allows for fast amplification of the low-swing input to full-rail CMOS. 
     In a preferred embodiment, the nodes are connected to outputs through inverters. A power down transistor is coupled to the drains of the source-follower pair. Power saving transistors are connected to the drains of the source-coupled pair, with their gates coupled to the opposite connecting node. Pre-discharge transistors are connected to the common nodes between the source-follower and source-coupled transistors. All of the clock inputs to the circuit use the same phase of the clock, avoiding any possibility of skew-induced race conditions. 
     In a preferred embodiment, the present invention provides a data input receiver for boosting a low-swing data input signal to a full swing CMOS data output signal with low delay between the input and output. The data receiver receives a low-swing differential signal from a high speed bus, and combines boosting of the low-swing data to full-swing CMOS with latching for retention and use by subsequent circuits in order to achieve both functions in minimal time. The data receiver operates in less than one cycle of a single input clock, has a large common mode range, requires no bias inputs and has very small setup and hold requirements. Furthermore, the receiver may be powered down and returned to an active condition in less than one cycle of the input clock. 
     For a further understanding of the nature and advantages of the invention, reference should be made to the following description taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram of a prior art receiver. 
     FIG. 2 is a circuit diagram of a receiver according to one embodiment of the invention. 
     FIG. 3 is a circuit diagram of the receiver of FIG. 2 showing the details of the sense amplifier. 
     FIG. 4 is a timing diagram illustrating the clock signals and internal nodes of the circuit of FIG.  3 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The present invention functions as a single-unit, with several distinct portions of the receiver, the first being the input pairs. Referring to FIG. 2, nfets  100 ,  101 ,  102 , and  103  make up the input devices and are driven by the differential input signals. The use of both the source-follower nmos pair  100  &amp;  101  and the source-coupled nmos pair  102  &amp;  103  allows for large input common-mode input range. When the input common-mode is high, the source-follower pair provides the majority of the differential current into the differential sense-amp I/O nodes  200  and  201 . When the common-mode is low, the source-coupled nmos pair  102  &amp;  103  provide the majority of the differential current. At intermediate common-modes both pairs contribute to the differential current, allowing for operation beyond what either pair would be able to do alone. The receiver is also pre-discharged, and in its ready-state the source-follower pair provides substantial differential current. The simultaneous use of the source-follower pair, the source-coupled pair, and the sense-amp transistors allows for extremely fast amplification of the low-swing input to full-rail CMOS. This fast amplification has the secondary benefit of small setup and hold requirements. In addition, in power-down the majority of the circuit is in the same state as when it is pre-discharged. This, as well as the lack of bias inputs, allows for activation from power-down in less than  1  cycle. 
     FIG. 3 shows a detailed diagram of the invention. It is easiest to describe the operation by starting from the state when Clk  208  is high. When Clk  208  is high, nfets  104  &amp;  105  pull down nodes  200  &amp;  201  very close to Vss, pre-discharging them. At the same time, nfet  114  aids the pre-discharge by equalizing the two nodes  200  and  201 . When Clk  208  is high, pfet  109  is inactive, so there is no power supplied to the sense-amp  400 , and pfets  110  &amp;  111  are inactive. With both nodes  200  and  201  low, the source-coupled pair  102  and  103  in series with the power-savings devices  106  and  107  are also inactive. The source-follower nfets  100  &amp;  101 , however, are in the active saturation region and are providing differential current. Since pre-discharge transistors  104  &amp;  105  are active, however, this differential current does not yet become differential voltage. Note also that during pre-discharge both the Q  209  and QB  210  outputs are both high. 
     When the Clk  208  falls, several effects occur. Pre-discharge transistors  104  and  105  release nodes  200  &amp;  201 , and the source-follower pair begins to pull-up  200  &amp;  201 . At the same time, Clk  208  falling has had the action of powering up the sense-amp  400  through pfet  109 . As nodes  200  &amp;  201  begin to rise, the source-follower pair maintains differential current until the differential voltage on  200  &amp;  201  is equal to that on the differential inputs DB  206  &amp; D  207  or until the voltage level has risen to just below the input voltage—Vtn of the source-follower transistors. For this reason the preferred embodiment uses low-Vt devices for  100  &amp;  101 . In the preferred embodiment devices  100  &amp;  101  are the lowest-Vt devices available, frequently with Vt&#39;s of only 300 mV. Since it is always advantageous to keep the source-follower devices turned on, even 0-V Vt devices would be preferable, if available. 
     As  200  &amp;  201  rise a Vtn above Vss, the power-isolation devices  106  &amp;  107  turn on, enabling the source-coupled pair to apply differential current to  200  &amp;  201  as well. Once nodes  200  &amp;  201  are substantially above Vtn, the sense-amp transistors  110 - 113  take over and rapidly amplify the differential voltage present at  200  &amp;  201  to the full-supply rail. Whichever node of  200  &amp;  201  rises to Vdd produces a falling output from the corresponding inverter  300 ,  301 . In the preferred embodiment, the inverters are sized so their trip points are above the voltage-level where  200  &amp;  201  separate during sense-amplification. How far above this level is a trade-off of faster speed vs. better noise immunity. Inverters  300  &amp;  301  are sized in the preferred embodiment so that their trip point is just 200 mV above the separation point of nodes  200  &amp;  201  as determined by the Vt&#39;s of nfets  112  and  113  of the sense-amp  400 . A higher value than 200 mV unnecessarily delays the transition of the output. A lower value than 200 mV risks false tripping of an output inverter to the incorrect state before the sense-amp has resolved the value of the incoming data. 
     FIG. 4 illustrates the timing, with both nodes  200  and  201  initially rising on the falling edge of clock  208 . One of the nodes will go high with the other eventually returning to a low level after an initial small rise. in the example of FIG. 4, node  201  returns to a low level, while node  200  continues to climb to the high level as driven by the sense amplifier. 
     The latency of the receiver is less than one half of a clock period as it truly functions like an edge-triggered device; there are no phases dedicated solely to isolation or amplification. After Clk  208  has fallen, the output data remains valid until the rising edge of Clk  208 , when nodes  200  &amp;  201  are pre-discharged and equalized again, and the receiver is ready for the next falling edge of Clk  208 . 
     Power-saving devices  106  &amp;  107  eliminate part of the static current that would otherwise be present when Clk  208  was low. By turning on only when the complementary side is higher than vtn, they ensure no static power is consumed through nfets  102  &amp;  103 . However, source-follower devices  100  &amp;  101  are both on when Clk  208  is high and both  200  &amp;  201  are low, and one of them is on when Clk  208  is low and data has been evaluated. Thus, there is always some static power consumed if PwrDn  205  is not high. When PwrDn  205  is brought high, node  202  discharges to Vss and nodes  200  &amp;  201  discharge to Vss. Power consumed in this mode is negligible. As voltages present in this mode are extremely similar to those in the pre-discharged state, not much setup time is needed to transition from this power-down state to an active one. Less than 1 cycle is required to use pfet  108  to charge up node  202  and turn on the source-follower pair  100  &amp;  101 . In the preferred embodiment, pfet  108  is also given a large W/L to reduce resistance to Vdd for both sensing and recovery from power-down. Pfet  108 &#39;s W/L is preferably about 100 or more contrasted to normal ratios of 5-40 for other devices, wherein the L is set by the minimum feature size for the process. 
     As will be understood by those of skill in the art, the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. For example, other circuit configurations for the clocked sense amplifier  400  could be used. Accordingly, the foregoing description is intended to be illustrative, but not limiting, of the scope of the invention which is set forth in the following claims.