Abstract:
A two-stage ESD protection circuit coupled between an I/O pad and a power rail is provided in the present invention. The two-stage ESD protection circuit has a primary ESD protection circuit and a secondary ESD circuit. The trigger-on rate of the secondary ESD protection circuit is sped up by employing an ESD detection circuit coupled to the I/O pad. It can be further sped up by employing a native NMOS in the secondary ESD protection. According to the invention, the trigger-on speed of the secondary ESD protection circuit can be effectively improved to obtain better ESD protection for the thinner gate oxides of internal circuits in sub-quarter-micron CMOS process.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an electrostatic discharge (ESD) protection circuit. In particular, the present invention relates to speeding up the trigger-on rate of a secondary ESD protection circuit in a two-stage ESD protection system. 
     2. Description of the Related Art 
     As the semiconductor manufacturing process develops, ESD protection has become one of the most critical reliability issues for integrated circuits (IC). In particular, as semiconductor process advances into the deep sub-micron era, scaled-down devices, thinner gate oxides, lightly-doped drain regions (LDD), shallow trench isolation (STI) process and the metallic salicide process are more vulnerable in terms of ESD stress. Therefore, an efficient ESD protection circuit must be designed and placed on the I/O pad to clamp the overstress voltage across the gate oxide in the internal circuit. 
     FIG. 1A shows a conventional two-stage ESD protection circuit in an integrated circuit (IC). In FIG. 1A, the field oxide device NF, which utilizes a field oxide segment as a gate oxide and has a higher ESD robustness, acts as a primary ESD protection circuit. NF is positioned near the I/O pad  12  and directly coupled between the I/O pad  12  and VSS, serving to conduct most of the ESD current from the I/O pad  12  to VSS. Nevertheless, the trigger-on voltage of NF during an ESD event is still too high, and the internal circuit  10  of the IC may suffer damage from ESD current during an ESD event. Therefore, a secondary ESD protection circuit between the internal circuit  10  and VSS, incorporated with a buffering resistor RL, clamps voltage received by the internal circuit  10 , as shown in FIG.  1 A. The secondary ESD protection circuit conventionally consists of a gate-grounded NMOS, such as the NMOS N 2  in FIG.  1 A. When a positive ESD stress pulses at the I/O pad  12  and VSS is grounded, N 2  will initially be triggered on to clamp the voltage at node  14  due to its lower trigger-on voltage. NF, which has a higher trigger-on voltage, will trigger on later to drain most of the ESD charge out of the I/O pad  12  while the voltage at node  16  is higher to a certain level. N 2  responds by clamping voltage and draining out smaller ESD current, and, therefore, the silicon area for N 2  can be much smaller than that for NF. 
     As the semiconductor manufacturing process develops, STI process becomes dominant to replace LOCOS (local oxidation) process in CMOS (complementary metal oxide semiconductor) process flow. Unlike the field oxide device built by LOCOS process, the field oxide device built by STI process has a much lower trigger-on rate. If NF in FIG. 1A is formed by STI process, its response is so slow that risks the internal circuit  10  to ESD damage. Therefore, the NF in FIG. 1A becomes unsuitable as semiconductor process advances into the deep sub-micron era. 
     A known design for a two-stage ESD protection circuit is to apply NMOS with the same threshold voltage to construct the primary ESD protection circuit and the secondary ESD protection circuit, such as the gate-grounded NMOS N 1  and N 2  in FIG.  1 B. In order to achieve the object of the secondary ESD protection circuit triggering prior to the primary ESD protection circuit, the channel length of N 2  is designed to be shorter than that of N 1 . Nevertheless, the difference of trigger-on rate built by varying the channel length of an NMOS is very limited. In other words, although N 1  and N 2  have different channel lengths, during an ESD event, N 2  can&#39;t be distinctly triggered on prior to N 1 . Therefore, the efficiency of a two-stage ESD protection circuit is lost and the ESD protection circuit as shown in FIG. 1B may have a lower ESD robustness. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide an ESD design concept, which increases the trigger-on rate of a secondary ESD protection circuit and is especially suitable to ICs fabricated by STI process. 
     The two-stage electrostatic discharge (ESD) protection circuit of the present invention is suitable for an input/output (I/O) port and is coupled across a pad and a power rail. The two-stage ESD protection circuit comprises a primary ESD protection circuit, an ESD detection circuit, a resistor and a secondary ESD protection circuit. The primary ESD protection circuit is coupled between the pad and the power rail. The ESD detection circuit is also coupled between the pad and the power rail. The resistor is connected in series between the pad and an internal circuit. The secondary ESD protection circuit is coupled between the internal circuit and the power rail. At the beginning of an ESD event, the ESD detection circuit provides a trigger voltage to trigger on the secondary ESD protection circuit prior to the trigger-on of the primary ESD protection circuit, thereby clamping voltage received by the internal circuit. 
     Another two-stage ESD protection circuit suitable to an input/output (I/O) port according to the present invention is provided. The two-stage ESD protection circuit is coupled across a pad and a power rail, and comprises a primary ESD protection circuit, a resistor and a secondary ESD protection circuit. The primary ESD protection circuit is coupled between the pad and the power rail, comprising a general NMOS with a first threshold voltage. The resistor is connected in series between the pad and an internal circuit. The secondary ESD protection circuit is coupled between the internal circuit and the power rail, comprising a native NMOS with a second threshold voltage lower than the first threshold voltage. At the beginning of an ESD event, the native NMOS in the secondary ESD protection circuit is triggered on prior to the trigger-on of the general NMOS in the primary ESD protection circuit, thereby clamping voltage received by the internal circuit. 
     By utilizing the ESD detection circuit or the native NMOS, the difficulty of the prior art in separating the trigger-on times of the primary ESD protection circuit and the secondary ESD protection circuit can be overcome, and a two-stage ESD protection circuit with improved ESD robustness is obtained. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention can be more fully understood by reading the subsequent detailed description in conjunction with the examples and references made to the accompanying drawings, wherein: 
     FIG. 1A shows a conventional two-stage ESD protection circuit in an integrated circuit (IC); 
     FIG. 1B depicts another two-stage ESD protection circuit with NMOS of the same threshold voltage; 
     FIG. 2A depicts a concept of a two-stage ESD protection circuit according to the present invention; 
     FIG. 2B depicts an embodiment of the two-stage ESD protection circuit in FIG. 2A; 
     FIG. 3A depicts another embodiment of the two-stage ESD protection circuit according to the present invention; and 
     FIG. 3B depicts a two-stage ESD protection circuit with a combination of a native NMOS and an ESD detection circuit to increase the trigger-on rate. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 2A depicts a concept of a two-stage ESD protection circuit according to the present invention. The two-stage ESD protection circuit  13  according to the present invention is suitable to an I/O port and is coupled between an I/O pad  12  and an internal circuit  10 . The two-stage ESD protection circuit  13  has a primary ESD protection circuit  30  and a secondary ESD protection circuit  32 : the primary ESD protection circuit  30  is coupled between the I/O pad  12  and VSS; the secondary ESD protection circuit  32  is coupled between the internal circuit  10  and VSS. A buffering resistor RL is connected in series between the I/O pad  12  and the internal circuit  10 . Furthermore, the two-stage ESD protection circuit  13  has an ESD detection circuit  20  shunt with the primary ESD protection circuit  30 . When the ESD detection circuit  20  detects the occurrence of an ESD event on the I/O pad  12 , it sends out a trigger voltage to turn on the secondary ESD protection circuit  32  such that the voltage at node  14  is clamped to protect the internal circuit  10 . 
     FIG. 2B depicts an embodiment of the two-stage ESD protection circuit in FIG.  2 A. The primary ESD protection circuit  30  mainly consists of a gate-grounded NMOS N 1 , whose drain and source are coupled to node  16  and VSS respectively. The secondary ESD protection circuit  32  mainly consists of an NMOS N 2 , whose drain and source are coupled to node  14  and VSS respectively. An RC coupling circuit, having a capacitor C and a resistor R connected in series between the I/O pad  12  and VSS, constructs the ESD detection circuit  20 . To distinguish an ESD event from normal circuit operation, the R and C value of the ESD detection circuit should be correctly designed. 
     During normal operation, the coupling voltage to the gate of N 2  provided by the capacitor C can be designed smaller than the threshold voltage (Vth) of N 2  device, when an input voltage is applied to the I/O pad. Therefore, N 2 , which has a gate coupled to VSS via resistor R, is remained off. The gate-grounded NMOS N 1  is turned off, too. The I/O pad  12  can be coupled to the internal circuit  10  via the buffering resistor RL to transmit signals as an I/O port. 
     When a negative ESD stress pulses at the I/O pad  12  and VSS is grounded, the parasitic diode D 1  at the source of N 1  is forward biased to release the ESD stress and protect the internal circuit  10 . 
     When a positive ESD stress pulses at the I/O pad  12  and VSS is ground, due to the coupling effect of capacitor C in the ESD detection circuit  20 , the gate of N 2  will temporarily be raised to a relatively-high voltage higher than its threshold voltage. Experiments indicate that the NMOS with proper positive gate bias will enhance its ESD protection mechanism (or snapback) more quickly than the NMOS with zero gate bias. Therefore, N 2 , whose gate is positively biased, will be triggered on much earlier than N 1 , whose gate is grounded. By properly adjusting the separation between the trigger-on rates of N 1  and N 2 , the voltage at node  14  is clamped by N 2  and most of the ESD current is drained out by N 1 , thereby preventing ESD stress from damaging the internal circuit  10 . 
     N 1  and N 2  can have the same structure as the NMOS used in the internal circuit  10 . In other words, all the elements in FIG. 2B are compatible to conventional or advanced semiconductor process. No modification in semiconductor process is needed to implement the two-stage ESD protection circuit of the present invention. 
     Furthermore, advanced semiconductor process usually has a lithograph operation and a NMOS Vt (threshold voltage) implantation to adjust the threshold voltages of some NMOS in IC. Generally speaking, NMOS Vt implantation utilizes positive conductivity type (P-type) dopant to raise the Vt of some NMOS. Therefore, an IC might have two kinds of NMOS. These two kinds of NMOS have the same structure (or cross-sectional view) but different Vt. The NMOS not implanted during the NMOS Vt implantation has a lower Vt, which usually depends upon the dopant concentration of the P-well or P-substrate thereunder, and is referred as a native NMOS. The NMOS implanted during the NMOS Vt implantation and having a higher Vt is referred to as a general NMOS. The same concept can be also applied to PMOS. A native PMOS has the same structure (or cross-sectional view) as a general PMOS. Nevertheless, a native PMOS has a less negative threshold voltage than a general PMOS. 
     FIG. 3A depicts another embodiment of the two-stage ESD protection circuit according to the present invention. The two-stage ESD protection circuit  15  has a buffering resistor RL, a primary ESD protection circuit  30  and a secondary ESD circuit  32 . The primary ESD protection circuit  30  consists of a gate-grounded NMOS N 1 , a general NMOS, coupled between node  16  and VSS. The secondary ESD protection circuit  32  consists of a native NMOS N* 2  coupling between node  14  and VSS. In FIG. 3A, a native NMOS is symbolized by the same symbol as a general NMOS except having a bolder channel under the gate as that for N* 2 . Due to the Vt difference, N* 2 , a native NMOS, is triggered on much earlier than N 1 , a general NMOS. Utilizing native NMOS, the trigger-on rate of the secondary ESD protection circuit  32  is effectively increased, thus the ESD protection circuit  15  has a robust ESD tolerance level. 
     A combination of a native NMOS and an ESD detection circuit to increase the trigger-on rate is depicted in FIG.  3 B. In FIG. 3B, ESD detection circuit  20  consists of an RC coupling circuit with a resistor R and a capacitor C connected in series. As mentioned before, when the positive ESD stress pulses at the I/O pad  12  and VSS is grounded, the RC coupling circuit temporarily raises the voltage at the gate of the native NMOS N* 2  and further speeds up the trigger-on rate of N* 2 . 
     Employing the ESD protection circuit  20  or native NMOS, the trigger-on rate of the secondary ESD protection circuit can be increased, such that the overall ESD protection circuit has better ESD robustness. 
     The conventional ESD protection circuit in FIG. 1B has a disadvantage of difficulty in separating the trigger-on times of the primary ESD protection circuit and the secondary ESD protection circuit. By contrast, the trigger-on rate for the secondary ESD protection circuit is easily adjusted or increased by employing native NMOS and the ESD detection circuit. Therefore, the primary ESD protection circuit and the secondary ESD circuit can separately triggered on during an ESD event, thereby improving the ESD protection performance of a two-stage ESD protection circuit. 
     The embodiments described above utilize general NMOS and native NMOS. According to the same concept, general PMOS and native PMOS can also be utilized to improve the trigger-on rate of a secondary ESD protection circuit. The interchange skill between P-type and N-type as well as that between VDD and VSS is familiar to those in the art. Therefore, the embodiments with general PMOS and native PMOS will be familiar to those in the art after reading this specification and are, thus, not repeated here. 
     Finally, while the invention has been described by way of examples and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.