Abstract:
The present invention discloses a memory device with a leakage current reduction feature. The memory device includes at least one memory cell for storing a value, and at least one switch module coupled to the memory cell for generating an operating voltage at various levels depending on various operation modes of the memory cell. The operating voltage is at a first level when the memory cell is being accessed, and is at a second level lower than the first level when the memory cell is not being accessed, thereby reducing a leakage current for the memory cell.

Description:
BACKGROUND  
       [0001]     The present invention relates generally to integrated circuit designs, and more particularly to a static random access memory (SRAM) with reduced leakage current.  
         [0002]     SRAM, a volatile memory device, provides data storage capability as long as it is supplied with power. As opposed to dynamic random access memory (DRAM), SRAM provides faster and more reliable data storage, and does not need to be refreshed constantly. A standard six-transistor SRAM cell includes a pair of cross-connected inverters and two pass-gate transistors. The inverters are coupled between a power supply node and ground. The pass-gate transistors couple the inverters to a bit line and a complementary bit line, respectively. When the cell is being accessed, the pass-gate transistors are selected to allow the cross-connected inverters to be written into or read from.  
         [0003]     Many efforts have been made to reduce the leakage current of SRAM in order to improve its reliability.  FIG. 1  schematically illustrates a conventional SRAM cell  100  with the leakage current reduction feature (see, U.S. Pat. No. 6,560,139). The SRAM cell  100  includes PMOS transistors  102  and  104  serially coupled with NMOS transistors  106  and  108 , respectively, between power supply nodes having an operating voltage CVDD and an NMOS transistor  110 . When the cell  100  is being accessed, the NMOS transistor  110  is turned on to allow the transistors  102 ,  104 ,  106  and  108  to function properly. When the cell  100  is not being accessed, the NMOS transistor  110  is turned off for reducing the leakage current from the bit line or the power supply nodes (CVDD) to ground.  
         [0004]     One drawback of the conventional SRAM cell  100  is that the NMOS transistor  110  may adversely affect the operation of the NMOS transistors  106  and  108 . Conventionally, the NMOS transistors  106 ,  108  and  110  are constructed directly on the same P-type substrate. When a voltage is applied to the gate of the NMOS transistor  110 , the bias between the substrate and the sources of the NMOS transistors  106  and  108  can be adversely affected. Thus, the NMOS transistor  110  may cause a reliability issue to the cell  100 .  
         [0005]     As such, what is needed is a SRAM device with a leakage current reduction feature, without causing reliability issues.  
       SUMMARY  
       [0006]     The present invention discloses a memory device with a leakage current reduction feature. In one embodiment of the present invention, the memory device includes at least one memory cell for storing a value, and at least one switch module coupled to the memory cell for generating an operating voltage at various levels depending on various operation modes of the memory cell. The operating voltage is at a first level when the memory cell is being accessed, and is at a second level lower than the first level when the memory cell is not being accessed, thereby reducing a leakage current for the memory cell.  
         [0007]     The construction and method of operation of the invention, however, together with additional objectives and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]      FIG. 1  schematically illustrates a conventional SRAM cell with a leakage current reduction feature.  
         [0009]      FIG. 2  schematically illustrates a circuit system for reducing the leakage current for an SRAM cell in accordance with one embodiment of the present invention.  
         [0010]      FIG. 3  schematically illustrates a circuit system for reducing the leakage current for an SRAM cell in accordance with another embodiment of the present invention. 
     
    
     DESCRIPTION  
       [0011]      FIG. 2  schematically illustrates a circuit system  200  for reducing the leakage current for an SRAM cell, such as a 5T, 6T, 8T, 10T, 12T, 14T or content-address memory (CAM) cell, in accordance with one embodiment of the present invention. The SRAM cell  202  includes a PMOS transistor  206  having a source coupled to an internal power supply node  208 , which receives an operating voltage labeled by CVDD. An NMOS transistor  210  is serially coupled between the PMOS transistor  206  and ground or VSS. The drains of the PMOS and NMOS transistors  206  and  210  are coupled at a node  212 , while the gates of the same are connected at a node  214 . A PMOS transistor  216  and an NMOS transistor  218  are serially coupled between the internal power supply node  208  and ground or VSS. The drains of the PMOS transistor  216  and the NMOS transistor  218  are coupled at a node  220 , which is further connected to the node  214 , while the gates of the same are coupled at a node  222 , which is further connected to the node  212 . An NMOS transistor  224 , which functions as a pass-gate device, is coupled between the node  212  and a bit line BL. An NMOS transistor  226 , which also functions as a pass-gate device, is coupled between the node  220  and a complementary bit line BLB. The gates of the NMOS transistors  224  and  226  are coupled to a word line WL. When the SRAM cell  202  is being accessed, the NMOS transistors  224  and  226  are selected by the signal on the word line WL for allowing a data value to be written into or read from the nodes  212  and  220 .  
         [0012]     The switch module  204  is coupled between the internal power supply node  208  and an external power supply node  228  where the “internal” and “external” are named with reference to the cell  202 . The switch module  204  receives an external operating voltage XCVDD from the node  228  and generates an internal operating voltage CVDD to the node  208 . While the external operating voltage XCVDD can remain at a constant level, the internal operating voltage varies at a number of levels, depending on the operation mode of the cell  202 . For example, when the cell  202  is in an active mode as it is being accessed for a read or write operation, the switch module  204  may generate the internal operating voltage CVDD at a normal level. When the cell  202  is in a standby mode as it is not being accessed, the switch module  204  may generate the internal operating voltage CVDD at a reduced level that is lower than the normal level. This reduces the leakage current for the cell  202  when it is not being accessed.  
         [0013]     In this embodiment, the switch module  204  is a single PMOS transistor  230  having a source coupled to the node  228 , a drain coupled to the node  208 , and a gate controlled by a control signal with various voltage levels depending on the operation mode of the cell  202 . For example, the control signal can have high, medium and low levels. When the cell  202  is being accessed, the low level control signal can be applied to fully turn on the PMOS transistor  230  for maintaining the internal operating voltage  208  at a normal level. When the cell  202  is not being accessed, the medium level control signal can be applied to slightly turn on the PMOS transistor  230  for reducing the internal operating voltage  208  to a lower than normal level, thereby reducing the leakage current from the node  228  to ground or VSS. Alternatively, the high level control signal can be applied when the cell  202  is not being accessed. This can slightly turn off the PMOS transistor  230 , and therefore further reducing the leakage current.  
         [0014]     Besides reducing the leakage current, the PMOS transistor  230  has another advantage as it does not affect the operation of the cell  202 . The PMOS transistor  230  is constructed on a well that separates its source and drain from the substrate. Thus, the operation of the PMOS transistor  230  would not affect the NMOS transistors  210 ,  218 ,  224  and  226 , as it is not directly constructed on the substrate as they are.  
         [0015]      FIG. 3  schematically illustrates a circuit system  300  for reducing the leakage current for a SRAM cell in accordance with another embodiment of the present invention. The circuit system  300  includes an SRAM cell  302  and a switch module  304 . The cell  302  is similar to the cell  202  in  FIG. 2 , and therefore its construction is not detailed here. The switch module  304  is coupled between an internal power supply node  306  and an external power supply node  308 . The switch module  304  receives an external operating voltage XCVDD from the node  308  and generates an internal operating voltage CVDD to the node  306 . While the external operating voltage XCVDD can remain at a constant level, the internal operating voltage varies at a number of levels, depending on the operation mode of the cell  302 .  
         [0016]     In this embodiment, the switch module  304  includes two PMOS transistors  310  and  312  wherein the PMOS transistor  310  is larger than the PMOS  312  in size. When the cell  302  is being accessed, both the PMOS transistors  310  and  312  are turned on for maintaining the internal operating voltage CVDD at a normal level. When the cell  302  is not being accessed, the PMOS transistor  310  is turned on, while the PMOS transistor  312  is turned off, such that the internal operating voltage CVDD can be maintained at a reduced level lower than the normal level, thereby reducing the leakage current from the node  308  to the ground or VSS. Alternatively, the PMOS transistor  310  can be turned off and the PMOS transistor  312  can be turned on for further reducing the leakage current, when the cell  302  is not being accessed. The selection between the transistors  310  and  312  can be determined depending on design requirements. Note that while this embodiment shows only two PMOS transistors in the switch module, more can be used to provide the internal operating voltage CVDD with more levels for optimizing the power consumption of the cell  302 .  
         [0017]     Besides reducing the leakage current, the PMOS transistors  310  and  312  have another advantage as they do not affect the operation of the cell  302 . The PMOS transistors  310  and  312  are constructed on wells that separate their sources and drains from the substrate. Thus, the operation of the PMOS transistors  310  and  312  would not affect the NMOS transistors within the cell  302 .  
         [0018]     Note that while the switch modules in the above embodiments are shown to be connected with the SRAM cells directly, a global switch module can be implemented for a memory array that contains a plurality of cells. This reduces the area occupied by the switch module and simplifies the circuit design for SRAM.  
         [0019]     The above illustration provides many different embodiments or embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims.  
         [0020]     Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.