Abstract:
A switching mode voltage regulator circuit that operates at reduced quiescent current levels is provided. The voltage regulator preferably includes a control circuit and a switching element that connects and disconnects filter circuitry from the control circuit. An error amplifier in the control circuit is placed in a micropower operating state when the regulator is in standby mode to reduce quiescent current.

Description:
This application is a continuation of U.S. patent application Ser. No. 09/260,990, filed Mar. 1, 1999 now U.S. Pat. No. 6,127,815. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates to voltage regulators. More particularly, this invention relates to circuits and methods for reducing the quiescent current in switching voltage regulators. 
     The purpose of a voltage regulator is to provide a predetermined and substantially constant output voltage to a load from a poorly-specified and fluctuating voltage source. One type of voltage regulator commonly used to accomplish this task is a switching voltage regulator. Switching voltage regulators are typically arranged to have a switching element (e.g., a power transistor) and an inductor coupled between the voltage source and the load. The switching regulator regulates the voltage across the load by turning the switching element ON and OFF so that power is transmitted through the switching element and into the inductor in the form of discrete current pulses. The inductor and an output capacitor then convert these current pulses into a steady load current so that the load voltage is regulated. 
     To generate a stream of current pulses, switching regulators include control circuitry that commands the switching element ON and OFF. The duty cycle of the switching element (i.e., the amount of time the switching element is ON compared to the period of an ON/OFF cycle), which controls the flow of current into the load, can be varied by a variety of methods. For example, the duty cycle can be varied by fixing the pulse stream frequency and varying the ON or OFF time of each current pulse, or by fixing the ON or OFF time of each current pulse and varying the pulse stream frequency. 
     Because switching regulators can operate at high levels of efficiency, they are often used in battery operated systems such as notebook computers, cellular telephones, and hand-held instruments. In such systems, when the regulator is supplying close to its rated output current, the efficiency of the overall circuit is usually high. However, this efficiency is generally a function of output current and typically decreases when the switching regulator is providing small amounts of current. This reduction in efficiency is generally attributable to the losses associated with operating the switching regulator. These losses include, among others, quiescent current losses, losses in the control circuit of the switching regulator, switching element losses, switching element driver losses, and inductor/transformer winding and core losses. 
     The reduction in efficiency of switching regulators at low output currents is of concern to circuit designers. This is because it is common for battery operated devices to experience short periods of high power use (i.e., periods during which relatively large currents must be supplied to a load), followed by extended periods of low power use (i.e., “standby” time during which a very small load current flows, but a regulated output voltage must be maintained). If the standby periods far exceed the usage periods, the quiescent current (i.e., the input current that flows into the switching regulator when the output is unloaded but still in voltage regulation) will determine the effective life of the battery. Accordingly, it is desirable to reduce quiescent current consumption as much as possible to extend battery life. 
     In the past, numerous techniques have been employed to reduce quiescent current losses in switching regulators during standby periods. For example, a switching regulator such as the LT1070 from Linear Technology Corporation, Milpitas, Calif., uses a control circuit that includes a comparator circuit and an error amplifier for monitoring the regulated output signal. When the output of the error amplifier drops below a threshold voltage, the regulator shuts down some of its internal circuitry to reduce quiescent current levels. 
     Other switching regulators from Linear Technology Corporation, such as the LT1307, LT1500, and LTC1625 use a mode of operation called “Burst Mode™” to reduce quiescent current. This mode of operation recognizes that the efficiency of a typical switching regulator drops off as the load decreases, because a fixed amount of power is wasted in the switch drive circuitry that is independent of load size. These switching regulators reduce quiescent current by holding the switching transistor(s) OFF, and turns OFF unneeded internal circuits, when the load current drops below a certain value. 
     A typical prior art current-mode stepdown switching regulator  100  employing burst mode operation is shown in FIG.  1 . Voltage regulator  100  generally comprises an output circuit  110 , a control circuit  130 , and a filter circuit  125 . 
     The voltage regulator of FIG. 1 operates as follows. A switch timing circuit  101  (which may be, for example, a one-shot, an oscillator, or any other suitable circuit) within control circuit  130  supplies a control signal SW ON that sets a latch  104 . While latch  104  is set, a switch driver  106  provides a signal to output circuit  110  that causes a switch  108  in output circuit  110  to turn ON and provide current from an input voltage source VIN to an output node  117 . Latch  104  remains set until an output signal from a current comparator  102  causes latch  104  to reset. When reset, latch  104  turns switch  108  OFF so that current is no longer drawn from VIN. Current comparator  102  determines when to reset latch  104  by comparing a current signal (I L ) from output circuit  110  with a current threshold value (I TH ) generated by an error amplifier  122  in control circuit  130  (discussed in more detail below). 
     The primary purpose of output circuit  110  is to provide current pulses as directed by control circuit  130  and to convert those current pulses into a substantially constant output current. Output circuit  110  includes power switch  108  coupled to VIN and a node  109 , a catch diode  112  coupled from node  109  to ground, an inductor  114  coupled from node  109  to output node  117 , a capacitor  116  coupled from output node  117  to ground, and a voltage divider formed by resistors  118  and  120  coupled from node  117  to ground. Although switching element  108  is depicted as a field-effect transistor (FET) in FIGS. 1 and 2, any other suitable switching element may be used if desired. 
     The operation of output circuit  110  can be divided into two periods. The first is when power switch  108  is ON, and the second is when power switch  108  is OFF. During the ON period, current passes from VIN through switch  108  and flows through inductor  114  to output node  117 . During this period diode  112  is reverse-biased. However, after power switch  108  turns OFF, inductor  114  still has current flowing through it. The former current path from VIN through switch  108  is now open-circuited, causing the voltage at node  109  to drop such that catch diode  112  becomes forward-biased and starts to conduct. This maintains a closed current loop through a load (not shown). When power switch  108  turns ON again, the voltage at node  109  rises such that diode  112  becomes reverse-biased and turns OFF. 
     As shown in FIG. 1, error amplifier  122  in control circuit  130  senses the output voltage of regulator  100  via a feedback signal V FB  produced by resistors  118  and  120 . Error amplifier  122 , which is preferably a transconductance amplifier, compares V FB  with a reference voltage (V REF ) that is also connected to amplifier  122 . An output signal, I TH , is generated in response to this comparison. The I TH  signal is filtered by a filter circuit  125  comprised of resistor  124  and capacitor  126  and coupled to an input of current comparator  102 . The value of I TH  sets the point at which current comparator  102  trips. 
     An input of a burst comparator  128  in control circuit  130  is also coupled to the output of error amplifier  122  and receives the filtered I TH  signal. Burst comparator  128  monitors ITS as an indication of load current and compares the filtered I TH  signal with a voltage potential V 1  that is connected to another input burst comparator  128 . V 1  is typically set to a value that represents the minimum current value for which it is desirable to maintain regulator  100  in the normal operating mode. This is usually a fraction of the maximum rated output current for regulator  100 . When I TH  decreases to or below the value of V 1 , burst comparator  128  trips, sending a SLEEP signal to the shutdown enable inputs of current comparator  102  and switch timing circuit  101 . This shuts down current comparator  102  and switch timing circuit  101 , maintains switch  108  OFF, and thus places voltage regulator  100  in a standby mode so that quiescent current is reduced. While in standby mode, capacitor  116  supports the load and no switching losses are incurred. When the output voltage V OUT  has decayed slightly, causing the I TH  voltage to increase by the amount of the hysteresis in burst comparator  128 , the SLEEP output of comparator  128  is de-asserted and normal operation resumes. 
     When a large load step is applied to voltage regulator  100 , the current drawn from regulator  100  increases. This causes a slight reduction in the value of V FB  which, in turn, causes I TH  to increase. The increase in I TH  raises the threshold point at which current comparator  102  trips, resulting in an increase in the current supplied by the regulator to match the required load current. 
     However, when the demand for load current decreases, switching element  108  will continue to turn ON each cycle as directed by control circuit  130 , but the value of I TH  will decrease in order to turn switching element  108  OFF at lower currents. Switching element  108  therefore continues to switch at the same frequency, but it conducts less current as the load current decreases, causing switching losses to become a larger percentage of the output power. 
     As the load current decreases further, I TH  periodically drops below V 1  and voltage regulator  100  begins to experience standby periods. As the demand for load current drops even further, the standby periods become longer. Finally, voltage regulator  100  enters a prolonged standby state in which substantially no current is supplied to the load. When this occurs, the operating intervals become so infrequent that the input current to voltage regulator  100  is essentially defined by the quiescent current alone. 
     One significant limitation in the amount of quiescent current reduction possible in voltage regulator  100  is the need of error amplifier  122  to quickly slew filter circuit  125  when transitioning from standby mode to normal operating mode. Such a transition is necessary, for example, when a large load step is placed on voltage regulator  100  during a standby period. If the output current of error amplifier  122  cannot slew filter circuit  125  as fast as the load current is slewing output capacitor  116 , the recovery time from standby periods will be extended. This undesirably causes the output voltage (V OUT ) to undershoot. 
     In addition, because the value of capacitor  126  is typically large enough such that filter circuit  125  provides adequate filtering, slewing filter circuit  125  requires a relatively large output current capability from error amplifier  122 . Accordingly, amplifier  122  must constantly be able to supply this current so that regulator  100  can quickly respond to large load steps, even when it is in a standby state. As a result, amplifier  122  must undesirably draw substantial amounts of quiescent current even while regulator  100  is in a standby period. 
     Other prior art voltage regulators which operate at low quiescent currents are also presently available. For example, the LT1316 and LTC1474 from Linear Technology Corporation are able to operate at extremely low quiescent currents while in standby mode by replacing the above-described error amplifier with a micropower comparator that uses a voltage reference as a fixed comparator threshold. This type of regulator determines when to enter and exit standby periods by comparing the load voltage (which is indicative of load current) with the fixed voltage reference. Thus, during standby periods, only the fixed voltage reference and a micropower comparator circuit are active, which significantly reduces the quiescent current required by the regulator. However, because this type of regulator usually employs a fixed current threshold, it cannot adaptively increase the threshold value with increasing load current, which may limit the regulator&#39;s response to large current demands. 
     In view of the foregoing, it would be desirable to provide a circuit and method for operating switching mode voltage regulators at very low quiescent current levels during standby periods and yet provide large output current during periods of normal operation. 
     It would also be desirable to provide a circuit and method for allowing a fast transition in switching regulators from a low-output current, very low-power consumption state (standby or burst mode) to a high-current output state by optimizing the response time of control circuitry in the switching regulators during the transition period. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a circuit and method for operating a switching voltage regulator at a very low quiescent current during standby periods and yet provide large output current during periods of normal operation. 
     It is another object of the present invention to provide a circuit and method for allowing a fast transition in switching regulators from a low-output current, very low-power consumption (standby mode) to a high-current or normal output state by optimizing the response time of feedback circuitry in the voltage regulator during the transition period. 
     In accordance with these and other objects of the present invention, a switching voltage regulator capable of operating at reduced quiescent currents is described. The voltage regulator includes an error amplifier in a control circuit to monitor inductor current as an indication of output current (although voltage mode regulators are also possible). When the output current drops below a pre-determined value, the output of the error amplifier also drops to a threshold value where the voltage regulator enters a standby mode of operation during which the switching transistor is maintained OFF and unneeded circuitry is shut down to reduce quiescent current consumption. In addition, while in standby mode, the error amplifier is placed in a micropower operating state to further reduce current consumption and the filter circuitry coupled to the error amplifier is disconnected and coupled to a “parking” voltage. The disconnection reduces capacitive loading on the error amplifier while it is in the micropower operating state, allowing the amplifier upon exiting the standby mode to rapidly slew in response to rapidly changing output requirements. The parking voltage is preferably at a value such that when normal operation resumes, and the filter circuitry is reconnected to the error amplifier, the voltage regulator will not immediately transition back to standby mode. The voltage regulator thus will re-enter burst mode only when the output of the error amplifier, operating at its normal current, again slews below the standby mode threshold value. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects and advantages of the present invention will be apparent upon consideration of the following detailed description, taken in conjunction with accompanying drawings, in which like reference characters refer to like parts throughout, and in which: 
     FIG. 1 is a schematic diagram of a prior art switching voltage regulator circuit; and 
     FIG. 2 is a schematic diagram of an exemplary embodiment of a switching voltage regulator constructed in accordance with principles of the present invention. 
     FIG. 3 is a schematic diagram of an illustrative embodiment of a switching circuit in accordance with principles of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A current-mode switching regulator  200 , which is constructed in accordance with the principles of the present invention, is shown in FIG.  2 . As in FIG. 1, the regulator of FIG. 2 includes switch timing circuit  101 , current comparator  102 , latch  104 , switch driver  106 , output section  110 , and comparator  128 . 
     Regulator  200  has been improved as compared to the regulator of FIG. 1, however, by the addition of two-position switch  127  in filter circuit  225  and error amplifier  222  (which replaces error amplifier  122 ) that has a selectively enablable micropower mode. As FIG. 2 shows, switch  127  (which is preferably implemented using transmission gates (FIG.  3 ), although substantially any conventional switching circuitry may be used if desired), is coupled to selectively connect filter circuit  225  (i.e., switch  127 , resistor  124 , and capacitor  126 ) either to the output of error amplifier  222  (position A) or to a parking voltage V P  (position B). Switch  127  is controlled by a SLEEP signal that is generated by comparator  128 . The SLEEP signal is also coupled to a MICROPOWER ENABLE input  223  of error amplifier  222 , to selectively control whether the error amplifier is in a normal or micropower operating state. 
     As shown in FIG. 3, switch  127  may be implemented using parallel-coupled transmission gates  300  and  310 . Transmission gates  300  and  310  may include N-channel MOSFETs (NMOS)  330  and P-channel MOSFETs (PMOS)  320  that are connected to one another such that the drain of PMOS  320  is connected to the source of NMOS  330  and vice versa (although this may “switch” during operation). An inverter  350  is connected between the gates of the transistors within transmission gate  300  (i.e., PMOS  320  and NMOS  330 ) so that a signal applied to the gate of one transistor (e.g., PMOS  320 ) is inverted at the gate of the other transistor (e.g., NMOS  330 ). This allows both transistors of transmission gate  300  to be ON or OFF when control input  340  is low (de-asserted) or high (asserted), respectively. The opposite is true for transmission gate  310  (i.e., gate  310  is OFF when control input  340  is low and ON when control input  340  is high). 
     As FIG. 3 shows, input  311  of transmission gate  310  is connected to parking voltage V P  (position B) and input  301  of transmission gate  300  is connected to the I TH  signal (position A) at the output of error amplifier  222 . Control input  340  is connected to the SLEEP signal at the output of comparator  128  and to the gates of PMOS and NMOS transistors within transmission gates  300  and  310 . If the signal applied to control input  340  is de-asserted low, NMOS  330 ′ and PMOS  320 ′ in transmission gate  310  are OFF while NMOS  330  and PMOS  320  in transmission gate  300  are ON. This allows the I TH  signal from the output of error amplifier  222  to pass from input  301  of transmission gate  300  to output  302 . In this way, filter circuit  225  may be selectively connected to the output of error amplifier  222 . 
     However, if the signal applied to control input  340  is asserted high, NMOS  330 ′ and PMOS  320 ′ in transmission gate  310  are ON while NMOS  330  and PMOS  320  in transmission gate  300  are OFF. This allows parking voltage V P  to pass from input  311  of transmission gate  310  to output  312 . In this way, filter circuit  225  may be selectively connected to the parking voltage V P . Because the NMOS and PMOS transistors of only one transmission gate ( 300  or  310 ) can be ON at any given time, either the parking voltage V P  or the I TH  signal from the output of error amplifier  222  can be connected to filter  225 . 
     Although the circuit of FIG. 3 is shown using PMOS transistors  320  and  320 ′, one skilled in the art will appreciate that transmission gates  300  and  310  could be implemented using only NMOS transistors  330  and  330 ′ if the V P  and I TH  voltages are about one volt or more below the value of the asserted SLEEP signal. 
     During normal operation, when regulator  200  is providing medium to large load currents, the I TH  voltage is above threshold voltage V 1  and the SLEEP signal is de-asserted low, causing switch  127  to be in position A. In position A, the filter components of filter circuit  225  (i.e., resistor  124 , and capacitor  126 ) are connected to the output of error amplifier  222 , and operation is identical to regulator  100  shown in FIG.  1 . As in FIG. 1, a decrease in load current also causes I TH  to decrease until it reaches voltage potential V 1 . When this occurs, BURST comparator  128  trips and asserts the SLEEP signal to place regulator  200  in a standby state. In this state, as in the case of FIG. 1, switching transistor  108  is maintained OFF and switch timing circuit  101  and comparator  102  are also turned OFF. In addition, however, assertion of the SLEEP signal: (1) switches switch  127  from position A to position B, thereby de-coupling filter circuit  225  from I TH  and coupling the filter circuit  225  to parking voltage V P , and (2) causes error amplifier  222  to enter a micropower mode of operation (via assertion of SLEEP at micropower enable input  223 ). When error amplifier  222  is in the micropower mode, its operating current is reduced by a large factor (e.g., 10 or more), in order to reduce its quiescent current to that comparable to a micropower comparator. 
     At the instant that BURST comparator  128  trips to assert the SLEEP signal, the output of error amplifier  222  was sinking current, causing the voltage on capacitor  126  to discharge. When filter circuit  225  is disconnected from the output of error amplifier  222 , any excess sinking current pulls I TH  down further, ensuring that the standby interval is continued. Because the SLEEP signal also places the error amplifier in a micropower state, which starves the amplifier of operating current, its ability to slew current-drawing loads (e.g., capacitive loads) is severely compromised. However, because filter circuit  225  has been disconnected from the output of error amplifier  222 , the error amplifier no longer experiences a significant capacitive load from filter circuit  225 . Thus, switching switch  127  from position A to position B significantly reduces the capacitive loading on control circuit  130 . Accordingly, as VOUT decays during a standby period, the reduced output current of error amplifier  222  is still sufficient to rapidly slew the unloaded I TH  line. When I TH  subsequently increases above V 1  (plus the hysteresis in comparator  128 ), the SLEEP signal is again de-asserted and normal operation of regulator  200  resumes. 
     During a standby period, switch  127  couples filter  225  to parking voltage V P . This voltage is preferably made slightly larger than V 1 , so that when filter circuit  225  is reconnected to the output of error amplifier  222  upon exiting standby mode, the voltage on I TH  is above threshold voltage V 1 . This prevents an immediate retrip of comparator  128 , and a subsequent premature (and undesirable) re-entering of regulator  200  into standby mode. Regulator  200  will enter the standby mode again, by virtue of assertion of the SLEEP signal, only when the output of error amplifier  222 , operating in its normal state, again slews I TH  below V 1 . In this way, standby mode operation with very little V OUT  ripple can be obtained, since VOUT does not have to increase much for error amplifier  222  to slew I TH  from V P  to V 1  with filter circuit  225  connected, nor decrease much for the error amplifier to return I TH  back above V 1  with filter circuit  225  disconnected. 
     Thus, a switching voltage regulator capable of reducing quiescent current without sacrificing response time when large currents are needed has been disclosed. Although the invention has been illustrated in the context of a step-down (buck) switching regulator, it is equally applicable to any other regulator topology such as boost, buck-boost, or inverting. Similarly, the invention has been illustrated in the context of a current-mode regulator loop, but could also be used with a voltage-mode regulator loop. 
     It also will be understood that the terms “asserted” and “de-asserted” are used herein only for convenience, and that no fixed logic levels are intended or should be inferred by their use. For example, a signal may be asserted high or low (and de-asserted in opposite fashion) as desired, without substantially affecting the operation of the invention disclosed herein. 
     Persons skilled in the art will thus appreciate that the present invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and that the present invention is limited only by the claims which follow.