Abstract:
A sigma-delta modulator for generating a modulation signal that modulates a frequency division ratio of a comparator/frequency divider of a PLL circuit. Series-connected integrators accumulate an input signal and output overflow signals when their accumulated values exceed a predetermined value. Differentiators transfer the overflow signals of the integrators. An adder multiplies output signals output from the differentiators by a predetermined coefficient and adds the products. A control circuit for transferring the accumulated value in synchronization with a clock signal of each integrator is connected between the integrator of a final stage and the integrator of the preceding stage. The control circuit reduces the modulation width of the modulation signal without reducing the order number of the modulator.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of international patent application No. PCT/JP2003/015215, filed Nov. 28, 2003, the entire contents being incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to a PLL circuit, and more particularly, to a PLL circuit using a sigma-delta modulator. 
     In recent years, PLL circuits for use in mobile communication devices, such as cellular phones, are required not only to be further highly integrated and consume less power but must also improve their channel switching speed and C/N (carrier-to-noise ratio) characteristic. To satisfy these requirements, PLL circuits using sigma-delta modulators have been commercialized. The PLL circuits using sigma-delta modulators are required to further improve their channel switching speed and C/N characteristic. 
     The channel switching time and the C/N characteristic are loop characteristics that are important in PLL circuits. More specifically, a PLL circuit is required to shorten the time taken to switch from one lockup frequency to another lockup frequency, while reducing phase noise contained in the frequency of an output signal. 
     To satisfy these requirements, a fractional-N PLL frequency synthesizer (PLL circuits) has been commercialized in recent years. The fractional-N PLL frequency synthesizer uses a fractional frequency division ratio of a comparator/frequency divider that forms a PLL loop. Such a fractional frequency division type PLL circuit increases the frequency of a reference signal and is thus advantageous in improving the channel switching time and the C/N characteristic. 
     However, the fractional value for the fractional frequency division ratio is obtained in an equivalent and averaged manner by changing the integral frequency division value over time. More specifically, the fractional frequency division ratio is obtained in an equivalent manner by cyclically performing frequency division by N+1 while constantly performing frequency division by a fixed frequency division value N. For example, for a frequency division of 1/8, the eight frequency division operations are performed by repeating N frequency division seven times and N+1 frequency division once. In the frequency division of 3/8, eight frequency division operations are performed by repeating N frequency division five times and N+1 frequency division three times. 
     However, when using a phase comparator to compare the comparison signal obtained from the fractional frequency division operation with a reference signal, the N frequency division and N+1 frequency division are cyclically repeated. This results in a cyclic phase error. As a result, spurious noise is generated in the output signal of a voltage controlled oscillator. 
     As one method for preventing generation of such spurious noise resulting from fractional frequency division, a sigma-delta fractional-N PLL frequency synthesizer  100  including a multi-stage noise shaping (MASH) sigma-delta modulator, as shown in  FIG. 13 , has been proposed. The sigma-delta modulator provides one method for randomly changing the frequency division value that is used in fractional frequency division to prevent generation of spurious noise. 
     In  FIG. 13 , an oscillator  1  outputs a reference clock signal, which has an inherent frequency based on the oscillation of a crystal oscillator, to a reference frequency divider  2 . The reference frequency divider  2 , which is formed by a counter circuit, outputs a reference signal fr, which is generated by dividing the frequency of the reference clock signal based on a preset frequency division ratio, to a phase comparator  3 . 
     A comparison signal fp is input into the phase comparator  3  from a comparator/frequency divider  4 . The phase comparator  3  outputs a pulse signal, which is in accordance with the phase difference between the reference signal fr and the comparison signal fp, to a charge pump  5 . 
     The charge pump  5  outputs an output signal to a lowpass filter (LPF)  6  based on the pulse signal output from the phase comparator  3 . 
     This output signal is formed by a direct current element containing a pulse element. The direct current element changes as the frequency of the pulse signal changes. The pulse element changes based on the phase difference of the pulse signal. 
     The LPF  6  outputs, as a control voltage, an output signal, which is obtained by smoothing the output signal of the charge pump  5  and removing high frequency elements from the smoothed signal, to a voltage controlled oscillator (VCO)  7 . 
     The VCO  7  outputs an output signal fvco, which has frequency that is in accordance with the control voltage, to an external circuit and the comparator/frequency divider  4 . 
     The frequency division ratio of the comparator/frequency divider  4  is set in a manner that the ratio is freely changed by a sigma-delta modulator  8 . 
     The sigma-delta modulator  8  is formed as a third-order modulator including integrators (Σ)  9   a  to  9   c  having n bits, differentiators (Δ)  10   a  to  10   f  formed by flip-flop circuits, and an adder  11 . The integrators  9   a  to  9   c  and the differentiators  10   a  to  10   f  operate using the comparison signal fp input from the comparator/frequency divider  4  as a clock signal. 
     A numerator value F of the sigma-delta modulator  8  is input into the integrator  9   a  from an external device (not shown). The integrator  9   a  accumulates the input value F based on a clock signal. When the accumulated value exceeds a denominator value (modulo value) Q, the integrator  9   a  outputs an overflow signal OF 1 . After the overflow, the integrator  9   a  divides the accumulated value by the denominator value Q, and continues accumulating the input value F. 
     The denominator value (modulo value) Q is set at 2 n . The numerator value F is input as a digital signal having n−1 bits with respect to the power n of the denominator value Q. The denominator value Q, which is the same value for the integrators  9   a  to  9   c , is, for example, 1024, and the numerator value F is 30. 
     The overflow signal OF 1  of the integrator  9   a  is provided as an input signal a to the adder  11  via the differentiators  10   a  and  10   b . An accumulated value X 1  of the integrator  9   a  is provided to the integrator  9   b.    
     The integrator  9   b , which performs an accumulating operation of an input signal having the accumulated value X 1 , outputs an accumulated value X 2  resulting from the accumulation to the integrator  9   c . Further, an overflow signal OF 2  output from the integrator  9   b  is provided as an input signal b to the adder  11  via the integrator  10   c  and as an input signal c to the adder  11  via the differentiators  10   c  and  10   d.    
     The integrator  9   c , which performs an accumulating operation of an input signal having the accumulated value X 2 , outputs an overflow signal OF 3 . The overflow signal OF 3  is provided as an input signal d to the adder  11 , provided as an input signal e to the adder  11  via the integrator  10   e , and provided as an input signal f to the adder  11  via the differentiators  10   e  and  10   f.    
     The differentiators  10   a ,  10   b , and  10   d  are included to correct errors in the timings of the input signals a to f that may be caused by the operations of the differentiators  10   c ,  10   e , and  10   f  in accordance with the clock signal. 
     Based on the input signals a to f, the adder  11  performs the computation:
 
(+1)a+(+1)b+(−1)c+(+1)d+(−2)e+(+1)f.
 
     The coefficients by which the input signals a to f are multiplied are set based on Pascal&#39;s triangle. 
       FIG. 7  shows the computation result (excluding +N) of the computation operation performed by the adder  11  described above. As shown in the drawing, the adder  11  generates random numbers that change arbitrarily in a range of +4 to −2. 
     A fixed frequency division ratio N that is set in advance is input into the adder  11 . The adder  11  adds the above computation result to the fixed frequency division ratio N and outputs the result to the comparator/frequency divider  4 . 
     With this operation performed by the adder  11 , the frequency division ratio input into the comparator/frequency divider  4  changes randomly with respect to the fixed frequency division ratio N in a manner such as N, N+1, N, N−2, N+3, N−1, . . . , N+4, to N−1. 
     In the comparator/frequency divider  4 , a fractional frequency division operation is performed averagely based on the frequency division ratio output from the adder  11 . 
       FIG. 7  shows examples of the random numbers that are the computation values output from the adder  11  of the third-order sigma-delta modulator  8  shown in  FIG. 13 .  FIG. 10  shows examples of random numbers generated in a second-order sigma-delta modulator. As shown in the two drawings, the fluctuation width of the output signal of the sigma-delta modulator increases and the modulation width of the frequency division ratio of the comparator/frequency divider  4  increases as the order number of the sigma-delta modulator increases. 
       FIG. 15  shows the frequency spectrum of the output signal of the fractional-N PLL frequency synthesizer  100  using the third-order sigma-delta modulator described above.  FIG. 14  shows the frequency spectrum of the output signal of a fractional-N PLL frequency synthesizer using a second-order sigma-delta modulator, and  FIG. 16  shows the same frequency spectrum in the case of a fourth-order sigma-delta modulator. 
     As apparent when comparing  FIGS. 14 to 16 , the noise level in the lockup operation of the PLL increases and the C/N characteristic is deteriorated as the order number of the sigma-delta modulator becomes higher. 
     The C/N characteristic is improved as the order number of the sigma-delta modulator becomes lower. However, the sigma-delta modulation is unstable in this case. Such unstable sigma-delta modulation adversely affects the output signal of the sigma-delta modulator. 
     SUMMARY OF THE INVENTION 
     The present invention provides a sigma-delta modulator that decreases the modulation width of a comparator/frequency divider without reducing the order number of the modulator. 
     One aspect of the present invention is a sigma-delta modulator for generating a modulation signal for modulating a frequency division ratio for a comparator/frequency divider of a PLL circuit. The sigma-delta modulator includes a plurality of series-connected integrators, each accumulating an input signal based on a clock signal and outputting an overflow signal when an accumulated value exceeds a predetermined value. A plurality of differentiators are selectively connected to the plurality of integrators. Each of the differentiators transfers an overflow signal of a corresponding one of the integrators. An adder multiplies the overflow signals transferred from the plurality of differentiators by a predetermined coefficient and adds the products to generate the modulation signal. A control circuit, connected between a first integrator of a final stage and a second integrator of a stage preceding the final stage, provides an output signal of the second integrator to the first integrator in synchronization with a frequency-divided signal obtained by frequency-dividing the clock signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic block diagram of a PLL based frequency synthesizer having a third-order sigma-delta modulator according to a preferred embodiment of the present invention; 
         FIG. 2  is a block diagram of a control circuit of the third-order sigma-delta modulator shown in  FIG. 1 ; 
         FIG. 3  is a diagram showing a specific structure for a gate circuit shown in  FIG. 2 ; 
         FIG. 4  is a schematic block diagram of a frequency divider shown in  FIG. 2 ; 
         FIG. 5  is an explanatory diagram showing an output signal of a flip-flop circuit shown in  FIG. 4 ; 
         FIG. 6  is an explanatory diagram showing a frequency-divided signal output from a frequency divider; 
         FIG. 7  is an explanatory diagram exemplifying the modulation width of a modulation output of a third-order sigma-delta modulator according to a prior art example; 
         FIG. 8  is an explanatory diagram exemplifying the modulation width of a modulation output of the third-order sigma-delta modulator of the present invention; 
         FIG. 9  is an explanatory diagram exemplifying the modulation width of a modulation output of the third-order sigma-delta modulator of the present invention; 
         FIG. 10  is an explanatory diagram exemplifying the modulation width of a modulation output of a second-order sigma-delta modulator; 
         FIG. 11  is an explanatory diagram showing a simulation of an output signal of a PLL based frequency synthesizer having the third-order sigma-delta modulator in the prior art; 
         FIG. 12  is an explanatory diagram showing a simulation of an output signal of a PLL based frequency synthesizer having the third-order sigma-delta modulator of the present invention; 
         FIG. 13  is a schematic block diagram of a PLL based frequency synthesizer having the third-order sigma-delta modulator in the prior art; 
         FIG. 14  is an explanatory diagram showing the frequency spectrum of an output signal of a PLL based frequency synthesizer having a second-order sigma-delta modulator; 
         FIG. 15  is an explanatory diagram showing the frequency spectrum of an output signal of a PLL based frequency synthesizer having a third-order sigma-delta modulator; and 
         FIG. 16  is an explanatory diagram showing the frequency spectrum of an output signal of a PLL based frequency synthesizer having a fourth-order sigma-delta modulator. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       FIG. 1  shows a sigma-delta fractional-N PLL frequency synthesizer  200  according to a preferred embodiment of the present invention. The frequency synthesizer  200  of the preferred embodiment is formed by adding a control circuit  12  to the sigma-delta modulator  8  of the prior art example shown in  FIG. 13 . The other structure of the frequency synthesizer  200  is the same as in the prior art example described above. 
     The frequency synthesizer  200  includes an oscillator  1 , a reference frequency divider  2 , a phase comparator  3 , a comparator/frequency divider  4 , a charge pump  5 , an LPF (lowpass filter)  6 , a voltage controlled oscillator (VCO)  7 , and a third-order sigma-delta modulator  50 . 
     The third-order sigma-delta modulator  50  includes three integrators  9   a  to  9   c , six differentiators  10   a  to  10   f , an adder  11 , and the control circuit  12 . The integrators  9   a  to  9   c  and the differentiators  10   a  to  10   f  operate in the same manner as in the prior art example shown in  FIG. 13 . Further, input signals a to f are input into the adder  11 . 
     Based on the input signals a to f, the adder  11  performs the computation:
 
(+1)a+(+1)b+(−1)c+(+1)d+(−2)e+(+1)f.
 
     The coefficients by which the input signals a to f are multiplied are set based on Pascal&#39;s triangle in the same manner as in the prior art example. 
     The adder  11  is designed by a well-known automatic logical synthesizer that automatically performs logical synthesis based on, for example, the input of the computation expression described above. 
     The adder  11  adds a fixed frequency division ratio N, which is input from an external device (not shown), to the above computation result and outputs the computed value to the comparator/frequency divider  4 . More specifically, the adder  11  outputs random numbers that arbitrarily change in a range of N+4 to N−2. 
     The control circuit  12 , which is arranged between the integrators  9   b  and  9   c , operates using a comparison signal fp input from the comparator/frequency divider  4  as a clock signal. The control circuit  12  divides the frequency of the clock signal at a frequency division ratio that is set in advance and outputs an accumulated value X 2  output from the integrator  9   b  to the integrator  9   c  based on the resulting frequency-divided signal. 
     Next, the specific structure of the control circuit  12  will be described. As shown in  FIG. 2 , the control circuit  12  includes a gate circuit  13 , a shift register  14 , and a frequency divider  15 , which are arranged between the integrators  9   b  and  9   c.    
     The shift register  14  generates frequency division ratio setting signals Y 1  to Yn having a plurality of bits based on a clock signal CK, data DATA, and an enable signal LE, which are input from an external device, and outputs the frequency division ratio setting signals Y 1  to Yn to the frequency divider  15 . 
     The frequency divider  15  divides the frequency of the comparison signal fp input from the comparator/frequency divider  4 , based on the frequency division ratio setting signals Y 1  to Yn, and outputs the resulting frequency-divided signal Z to the gate circuit  13 . 
     The specific structure of the frequency divider  15  will now be described with reference to  FIG. 4 . The frequency divider  15  includes multiple stages of flip-flop circuits  16   a  to  16   d , which are connected in series, and a logic circuit unit  17  for generating the frequency-divided signal Z based on output signals FFL 1  to FFL 4  of the flip-flop circuits  16   a  to  16   d . The flip-flop circuits  16   a  to  16   d  form a normal binary counter. 
     The comparison signal fp is input into the flip-flop circuit  16   a  of the first stage. Output signals FF 1  to FF 3  of the flip-flop circuits  16   a  to  16   c  of the preceding stages are input into the flip-flop circuits  16   b  to  16   d  of the following stages, respectively. 
     As shown in  FIG. 5 , the flip-flop circuit  16   a  outputs the output signal FF 1  that is obtained by dividing the frequency of the comparison signal fp by one, the flip-flop circuit  16   b  outputs the output signal FF 2  that is obtained by dividing the frequency of the output signal FF 1  of the flip-flop circuit  16   a  by two, the flip-flop circuit  16   c  outputs the output signal FF 3  that is obtained by dividing the frequency of the output signal FF 2  of the flip-flop circuit  16   b  by two, and the flip-flop circuit  16   d  outputs an output signal FF 4  that is obtained by dividing the frequency of the output signal FF 3  of the flip-flop circuit  16   c  by two. 
     As a result, the flip-flop circuit  16   c  outputs the output signal FF 3  that is obtained by dividing the comparison signal fp by four, and the flip-flop circuit  16   d  outputs the output signal FF 4  that is obtained by dividing the comparison signal fp by eight. 
     The frequency division ratio setting signals Y 1  to Y 4  are input into the flip-flop circuits  16   a  to  16   d , respectively. When the frequency ratio setting signals Y 1  to Y 4  have high (H) levels, the output signals FFL 1  to FFL 4  are output to the logic circuit unit  17 . The output signals FF 1  to FF 4  have the same phases as the output signals FFL 1  to FFL 4 . 
     For example, when only the frequency division ratio setting signals Y 1  to Y 2  have H levels, only the output signals FFL 1  and FFL 2  are output to the logic circuit unit  17 . Further, the frequency division ratio setting signals Y 1  to Y 4  enable any combinations of the output signals FFL 1  to FFL 4  to be output to the logic circuit unit  17 . 
     The logic circuit unit  17  generates the frequency-divided signal Z that is obtained by dividing the frequency of the comparison signal fp by N based on the output signals FFL 1  to FFL 4  of the flip-flop circuits  16   a  to  16   d.    
     For example, when the output signal FFL 1  is output to the logic circuit unit  17  only from the flip-flop circuit  16   a , a frequency-divided signal Z 1  output from the logic circuit unit  17  is a signal obtained by dividing the frequency of the comparison signal fp by one, that is, a signal having the same phase as the comparison signal fp as shown in  FIG. 6 . When the output signals FFL 1  and FFL 2  are output to the logic circuit unit  17  only from the flip-flop circuits  16   a  and  16   b , a frequency-divided signal Z 3  is a signal obtained by dividing the frequency of the comparison signal fp by three. 
     This structure enables the frequency division ratio of the frequency-divided signal Z output from the frequency divider  15  having the structure shown in  FIG. 4  to be set freely in a range of 1 to 15 by appropriately setting the frequency division ratio setting signals Y 1  to Y 4 . Further, an increase in the number of stages of the flip-flop circuits enables the frequency division ratio to be set in a more versatile range. 
     The accumulated value X 2  output from the integrator  9   b  and the frequency-divided signal Z are input into the gate circuit  13 . The accumulated value X 2  may be signals K 1  to K 10  having, for example, ten bits. 
     In the gate circuit  13 , the signals K 1  to K 10  and the frequency-divided signal Z are input into AND circuits  18  as shown in  FIG. 3 . Thus, the accumulated value X 2  is output to the differentiator  9   c  via the gate circuit  13  only when the frequency-divided signal Z has an H level. 
     Next, the operation of the sigma-delta modulator  50  having the above-described structure will be described. The frequency division ratio setting signals Y 1  to Y 4  output from the shift register  14  cause the output signals FFL 1  and FFL 2  to be output to the logic circuit unit  17  only from the flip-flop circuits  16   a  and  16   b  of the frequency divider  15 . As a result, the frequency divider  15  outputs the frequency-divided signal Z 3 , which is obtained by dividing the frequency of the comparison signal fp by three, to the gate circuit  13 . 
     Then, the gate circuit  13  outputs the accumulated value X 2  output from the integrator  9   b  to the integrator  9   c  at a rate of once every three cycles of the comparison signal fp. Otherwise, the gate circuit  13  outputs all zeros. As a result, the accumulating operation is performed in the integrator  9   c  only once every three cycles of the comparison signal fp. This reduces the number of times the overflow signal OF 3  is output from the integrator  9   c.    
     Due to such an operation, in comparison with the random numbers generated in the normal third-order sigma-delta modulator shown in  FIG. 13 , as shown in  FIG. 8 , random numbers generated by the adder  11  do not become +4 and this reduces the fluctuation width of the random numbers. Further, random numbers generated by the adder  11  become +3 or −2 less frequently. 
       FIG. 9  shows random numbers generated in the adder  11  when the frequency division ratio of the frequency divider  15  is set at 9. In this case, the random numbers become +3 or −2 further less frequently. 
       FIG. 10  shows a case in which the frequency division ratio of the frequency divider  15  is further increased to substantially ∞. In this case, the random numbers become as close as possible to the random numbers generated in a second-order sigma-delta modulator. 
     Further, when the frequency division ratio of the frequency divider  15  is set at 1, the random numbers are those generated in the normal third-order sigma-delta modulator shown in  FIG. 7 . 
       FIG. 11  shows simulation of noise elements of an output signal of a fractional-N PLL frequency synthesizer using the third-order sigma-delta modulator of the prior art.  FIG. 11  corresponds to portion A of the frequency spectrum shown in  FIG. 15 . 
       FIG. 12  shows a simulation of noise elements of an output signal of a fractional-N PLL frequency synthesizer using the third-order sigma-delta modulator of the preferred embodiment shown in  FIG. 1 . 
     As apparent from the comparison between  FIGS. 11 and 12 , the preferred embodiment attenuates the noise elements entirely by about 5 dB in comparison with the prior art. 
     The sigma-delta modulator and the sigma-delta fractional-N PLL frequency synthesizer of the preferred embodiment have the advantages described below. 
     (1) The comparator/frequency divider  4  performs the fractional frequency division operation based on the output signal of the sigma-delta modulator  50 . This enables the reference signal fr to have a higher frequency. Thus, the channel switching speed, that is, the lockup speed of the output signal fvco of the PLL circuit is increased, and the C/N characteristic is improved. 
     (2) The fluctuation width of the random numbers, which are the computation values of the sigma-delta modulator  50 , is reduced while the order number of the sigma-delta modulator  50  is increased. As a result, the modulation width of the comparator/frequency divider  4  is reduced, the noise level of the output signal fvco of the PLL circuit is reduced, and the C/N characteristic is improved. 
     (3) The fluctuation width of the random numbers that are the computation values of the sigma-delta modulator  50  is reduced, while the order number of the sigma-delta modulator  50  is increased. This prevents the lockup speed from being lowered by an increase in the order number of the sigma-delta modulator  50 . 
     (4) The order number of the sigma-delta modulator  50  is increased, and the noise level of the output signal of the PLL circuit is stabilized. 
     (5) The fluctuation width of the random numbers that are the computation values of the sigma-delta modulator  50  is reduced simply by adding the control circuit  12  to the structure of the prior art. 
     (6) The fluctuation width of the random numbers that are the computation values of the sigma-delta modulator  50  is continuously changed by adjusting the frequency division ratio of the frequency divider  15  that forms the control circuit  12 . In the preferred embodiment, the fluctuation width of the random numbers can be continuously changed in a range of values obtained between the second-order and the third-order. 
     (7) The frequency division ratio of the frequency divider  15  is adjustable by changing the data DATA that is input into the shift register  14 . As a result, the noise level of the output signal fvco of the PLL circuit is easily adjustable by inputting the data DATA from an external device and adjusting the fluctuation width of the random numbers. 
     The application of the present invention should not be limited to the third-order sigma-delta modulator. The present invention may be applied to a fourth or higher order sigma-delta modulator. In this case, the control circuit is arranged between the integrator of the final stage and the integrator of the stage preceding the final stage. 
     The frequency divider included in the control circuit  12  may operate at a fixed frequency division ratio. 
     The sigma-delta fractional-N PLL frequency synthesizer of the present invention may be used either in a PLL circuit at a base station or in a PLL circuit at a mobile station.