Abstract:
An apparatus is disclosed for determining the impedance and dissipation factor of a capacitive and/or inductive device and to reduce measurement error by digital calculation and manipulation. A synchronous rectifying means, a phase shifter and a detecting means are employed to detect the in-phase and orthogonal components of the current through a device and to compare it to a reference voltage impressed across the device. An arithmetical calculation using the values of these components determines the impedance and the dissipation factor of the device.

Description:
BACKGROUND OF THE INVENTION 
     The present invention concerns an apparatus for measuring the impedance of an unknown device by phase comparison of the current through the device with the voltage across the device. 
     In prior art methods for measuring the impedance of an unknown device, to measure the phase difference of the current through the device and the voltage across the device, a phase detector, or a synchronous rectifier, has been employed. But the phase detector has the disadvantage of having a constant phase offset error. This phase error is an unavoidable measurement error, because the error is generated in part by the phase difference between the two signal input paths to the phase detector. This error is also generated in part by a residual phase error caused by the phase detector itself. 
     Another disadvantage to the prior art impedance meter is the difficulty of obtaining more accurate measurement and better resolution in the measurement of dissipation factors D, or tanδ in the case of a capacitive impedance. 
     An apparatus for measuring the vector voltage ratio using a synchronous phase detector circuit and an analog circuit is shown in Japanese patent application number SHOWA No. 54-09358, entitled &#34;An Apparatus for Measuring the Vector Voltage Ratio of Two A.C. Signals.&#34; The above cited application describes only the apparatus and method for measuring the vector ratio of two signals; it does not disclose a method for measuring impedance or dissipation factor D. 
     Accordingly, an object of the present invention is to provide an apparatus which can reduce measurement errors caused by phase detectors and which can increase accuracy and resolution in the measurement of the dissipation factor D of an unknown device. 
     SUMMARY OF THE INVENTION 
     An apparatus in accordance with the preferred embodiment of the present invention for measuring the impedance of an unknown device digitally removes measurement errors caused by the phase errors inherent in a synchronous phase detector circuit and by the signal paths to the synchronous phase detector circuit. This apparatus also digitally improves measurement accuracy and resolution of the dissipation factor D. 
     The apparatus in accordance with the preferred embodiment includes a conversion circuit that converts a current to a voltage. This current is a function of the impedance of the device and of the voltage impressed across the device. It also includes a switching circuit to selectively couple one of two a.c. input signals to an input terminal of a synchronous detector circuit. 
     A phase shifting circuit to shift the phase of one a.c. input signal is connected to another input terminal of the synchronous rectifying circuit. 
     A control circuit for selecting the input a.c. signal that the switching circuit is to couple and the amount of phase shift in the phase shifting circuit is also part of the apparatus. There is a voltage meter to measure the output voltage of the synchronous rectifying circuit. The output voltage of the synchronous rectifying circuit is then coupled to a calculating section to calculate the dissipation factor of the unknown device, thus forming an impedance measuring apparatus, or impedance meter. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a preferred embodiment of the apparatus for measuring impedance in accordance with the invention. 
     FIG. 2 is a vector diagram showing the phase relation between input signals E1 and E2 and reference signals X and Y. 
     FIG. 3 shows the relation of the input and output signals of the phase detector employed in the preferred embodiment of the apparatus shown in FIG. 1. 
     FIG. 4 is a detailed block diagram of the apparatus of FIG. 1 having a dual-slope analog-to-digital converter as the voltage meter. 
     FIG. 5 shows a time plot of the output voltage of the integrator employed by the apparatus shown in FIG. 4. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In FIG. 1, one terminal of a device 2 is connected to a reference oscillator 4 having an output voltage E and to an input terminal 6. The other end of device 2 is connected to the inverting input terminal of an operational amplifier 8. The inverting input terminal of operational amplifier 8 is also connected to a resistor 10; the other end of resistor 10 is connected to the output of operational amplifier 8. Operational amplifier 8 and resistor 10 together convert current that flows through device 2 to a corresponding voltage. In other words, operational amplifier 8 and resistor 10 together act as a current-to-voltage converter. 
     The output of operational amplifier 8, E 2 , is connected to an input terminal 12. A switch 7 selectively couples input signal E 1  and input signal E 2  to an input terminal 9 of a phase detector 14. Input signal E 1  is also coupled to another input terminal 11 of phase detector 14 through a phase shifter 16. 
     A phase shifter 16 produces a square wave corresponding to input signal E 1  with a phase shift from input signal E 1  of either 0, π/2, π, or 3π/2 radians. Phase shifters are known in the prior art. A control unit 19 selects the position of switch 7 and the amount of phase shift of phase shifter 16 as desired by a user. This phase shifter 16 can be embodied using the known technology. An output terminal 13 of phase detector 14 is coupled to a voltage meter 18, which measures the voltage of the output of phase detector 14. The values of the voltages are then calculated by a processor 21, such as a microprocessor or a calculator, to obtain the value of the impedance of device 2. 
     FIG. 2 is a vector diagram showing the phase relation between input signal E 1  and input signal E 2  of FIG. 1. In FIG. 2, vector E 1  corresponds to the voltage applied to input terminal 6, and vector E 2  corresponds to the voltage applied to input terminal 12. Here, vector E 2  corresponds to the magnitude and phase of the current that flows through device 2. 
     Due to the residual phase shift of the actual circuit, there is a residual phase difference θ 1  between output voltage E 1  and the output voltage of phase shifter 16. This is evident when phase shifter 16 is set for a phase shift of 0 or θ radians. This phase difference θ 1  can be attributed to the presence of phase shifter 16 in the signal path, if phase detector 14 is considered ideal and any contribution thereby to the phase difference θ 1  is ignored. 
     Thus there is an inherent phase error θ 1  in the phase difference between a reference vector X through phase shifter 16 and input signal E 1 . Similarly, in the phase difference between reference vector X and input signal E 2 , there is an inherent phase error θ 2 . 
     A vector E Y  is made orthogonal to vector E 1 . If device 2 is a test condenser with a certain loss, vector E 2  then corresponds to the flow of current through this test condenser. If the condenser is an ideal condenser, i.e., one with zero loss, the phase difference θ 4  between vector E 2  and vector E Y  will be zero, since the current through the condenser is leading its voltage E 1  by 90°. If there is any dielectric loss, phase difference θ 4  then corresponds to the dielectric loss of the test condenser. This dielectric loss is generally designated tanδ. When device 2 is an inductor, the phase difference θ 4  then corresponds to a dissipation factor D of an inductor. 
     If device 2 is capacitive and it is expressed in parallel equivalent circuit terminology, viz., C p  as parallel equivalent capacitance and R p  as parallel equivalent resistance, the dissipation factor D (or tanδ) can be expressed by the following relationship: ##EQU1## where ω=2πf, and f is the frequency of interest to input signal E 1 . 
     If device 2 is inductive and it is expressed in series equivalent circuit terminology, viz., L s  as series equivalent inductance and R s  as series equivalent resistance, the dissipation factor D (or tanδ) can be expressed by the following relationship: ##EQU2## where ω and f are defined as above. 
     FIG. 3 illustrates the operation of phase shifter 16 and phase detector 14 shown in FIG. 1. 
     FIG. 3(a) shows input signal E 1  and FIG. 3(b) shows the output of phase shifter 16 when the amount of phase shift is zero. θ 1  is the phase difference between the signals shown in FIGS. 3(a) and 3(b). When switch 7 of FIG. 1 is connected to input terminal 6 and the output of phase shifter 16 shown in FIG. 3(b) is coupled to phase detector 14, phase detector 14 generates a detected signal shown in FIG. 3(c) which represents the component of input signal E 1  in phase with the output signal of FIG. 3(b). In terms of the vector diagram in FIG. 2, the output of phase shifter 16 shown in FIG. 3(b) and the detected signal shown in FIG. 3(c) correspond, respectively, to vector X and to magnitude &#34;a&#34; on reference vector X. FIG. 3(d) shows an output signal of phase shifter 16 when the amount of phase shift is π/2, and FIG. 3(e) shows the detected signal of phase detector 14 when input signal E 1  is coupled. In terms of the vector diagram illustrated in FIG. 2, the output of phase shifter 16 shown in FIG. 3(d) and the detected signal shown in FIG. 3(e) correspond, respectively, to a reference vector Y made orthogonal to vector X and to magnitude &#34;b&#34; on reference vector Y. 
     It is possible to analyze similarly the input signal E 2  illustrated in FIG. 2. Magnitude &#34;c&#34; with respect to reference vector X is detected by connecting switch 7 to input terminal 12 and setting phase shifter 16 for a phase shift of zero. 
     Magnitude &#34;d&#34; of E 2  with respect to orthogonal reference vector Y is detected by connecting switch 7 to input terminal 12 and setting phase shifter 16 for a phase shift of π/2. 
     The operation of the impedance meter in accordance with the preferred embodiment of the present invention can be better understood with a discussion of the theory underlying the method of measuring impedance in accordance with the invention. Such a discussion follows. 
     THEORY TO THE IMPEDANCE MEASUREMENT 
     Dissipation factor D is 
     
         D=(1+α·β)/(β-α), 
    
     and reactance is ##EQU3## where α=b/a, β=d/c, γ=d/a, and a, b, c, and d are as defined by the vector diagram in FIG. 2. This can be shown as follows: 
     It is evident from FIG. 2 that dissipation factor D of the device is ##EQU4## But ##EQU5## so dissipation factor D becomes 
     
         D=(1+α·β)/(β-α).            (2) 
    
     Similarly from FIG. 2, the reactance of the device is ##EQU6## where: ##EQU7## Therefore, ##EQU8## From the identities ##EQU9## it follows that ##EQU10## Combining equations (1), (3), (4), and (5) results in the following relationship: ##EQU11## If the device is inductive, then 
     
         X=jωL, 
    
     where ω=2πf and L is the inductance. 
     If the device is capacitive, then ##EQU12## where ω=2πf and C is the capacitance. 
     The impedance of device 2 can be determined from equations (2) and (6). A microprocessor (not shown) is usually used to manipulate the parameters and to make the calculations called for by these equations. 
     FIG. 4 illustrates a detailed block diagram of an impedance meter in accordance with the preferred embodiment of the invention, and FIG. 5 illustrates a sequential timing diagram to explain the operation of FIG. 4. In this embodiment, a dual-slope voltage ratio meter 30 is used instead of a voltmeter 18 shown in FIG. 1. The output signal of phase detector 14 is transmitted to a smoothing filter 48 to produce a d.c. output signal which is coupled through a switch 41 to an input terminal 43 of an integrator 40. As illustrated in FIG. 4, integrator 40 includes an operational amplifier 45 and a feedback capacitor 47. The output of integrator 40 is coupled to a zero-crossing detector and counter 50. 
     In FIG. 5 the output voltage of integrator 40 is shown. Each of the steps in attaining this voltage is now discussed. 
     Step I 
     This is a step to measure a reference phase shift and to calculate α. 
     (1) Switch 7 is connected to input terminal 6. 
     (2) Phase shifter 16 is set for a phase shift of π/2. 
     (3) Switch 41 is next applied and the signal coupled thereby is allowed to be integrated for a predetermined period of TC seconds. This step corresponds to &#34;b,&#34; the orthogonal component of input signal E 1 , being integrated for Tc seconds. 
     (4) Phase shifter 16 is next set for a phase shift of π. It should be noted that switch 7 remains connected to input terminal 6 during this integration of &#34;-a&#34; volts. 
     (5) Finally, when the output voltage of integrater 40 falls to a predetermined level, switch 41 is switched off. 
     This interval is denoted as T 1 . By calculating T 1  /Tc, and from the relationship b/a=T 1  /Tc, b/a=α can be determined. 
     Step II 
     This step measures tanδ and calculates β. 
     (1) Switch 7 is connected to input terminal 12. 
     (2) Phase shifter 16 is set for a phase shift of π/2. 
     (3) Switch 41 is next applied and the signal coupled thereby is allowed to be integrated for a predetermined period of Tc seconds. This step corresponds to &#34;d,&#34; the orthogonal component of input signal E 2 , being integrated for Tc seconds. 
     (4) Phase shifter 16 is next set for a phase shift of π. It should be noted that switch 7 remains connected to input terminal 12 during this integration of &#34;-c&#34; volts. 
     (5) Finally, when the output voltage of integrator 40 falls to a predetermined level, switch 2 is then switched off. 
     This interval is denoted as T 2 . By calculating T 2  /T c  and from the relationship d/c=T 2  /Tc, d/c=β can be determined. 
     Step III 
     This step measures capacitance or inductance and calculates γ. 
     (1) Switch 7 is connected to input terminal 12. 
     (2) Phase shifter 16 is set for a phase shift of π/2. 
     (3) Switch 41 and is then applied and the signal coupled thereby is allowed to be integrated for a fixed time of Tc seconds. This step corresponds to &#34;d,&#34; the orthogonal component of input signal E 2 , being integrated for Tc seconds. 
     (4) Phase shifter 16 is next set for a phase shift of π, and switch 7 is simultaneously connected to input terminal 6. It should be noted that the integration of &#34;-a&#34; volts is accomplished during this period. 
     (5) Finally, when the output voltage of integrator 40 falls to a predetermined level, switch 41 is switched off. 
     This interval is denoted as T 3 . By calculating T 3  /Tc, and from the relationship d/a=T 3  /Tc, d/a=γ can be determined. 
     After α, β and γ are determined by steps (I), (II) and (III), respectively, the dissipation factor D is calculated from equation (2) and the reactance, either capacitance or inductance, is calculated from equation (6) by a calculator, such as a microprocessor. 
     As the above discussion illustrates, the apparatus in accordance with the preferred embodiment of the invention provides precise measurements of dissipation factors D and reactance, both capacitive and inductive. It does so by essentially removing the effects of phase errors inherent in synchronous phase detectors.