Abstract:
A thin film transistor (TFT) structure is provided herein, which comprises a substrate, a light-shielding resin, a polysilicon, a gate electrode insulator, a gate electrode, an interlayer dielectric layer, a source electrode, and a drain electrode. The light-shielding resin has functions of light-shielding and insulation. With doping through two through holes at two sides, the manufacturing process is simplified, the exposure process is simplified, the production time is shortened, the usage of masks is decreased, and the production cost is lowered.

Description:
BACKGROUND OF THE INVENTION 
     Field of Invention 
       [0001]    The present invention relates to a thin film transistor (TFT) structure and a manufacturing method of the same, and more particularly to a field of low temperature poly silicon (LTPS) TFT. 
       Description of Prior Art 
       [0002]    In the conventional art, the manufacturing process of the low temperature poly silicon (LTPS) thin film transistor (TFT) is: disposing a substrate, a light-shield (LS), a triple-layers structure (SiNx, SiOx, polysilicon), a channel doping, an N doping, a gate electrode insulator, a gate electrode, a P doping, an interlayer dielectric (ILD), a bottom indium tin oxide (BITO), a passivation layer (PV), and a top indium tin oxide (TITO). The LS is removed after being used, which increases the manufacturing process, the quantity of masks, the production time, and the production cost. 
         [0003]    In the conventional art, the two dopings applied to the polysilicon are performed by masks, hence, decreasing the usage of masks is a technical issue needing to be solved. 
         [0004]    Please refer to publication No. CN 200710122171 of State intellectual property office of the P.R.C., which proposes a LS disposed on the TFT structure of a substrate. Since the LS is made by metal, an insulation layer is needed to be inserted between the LS and the TFT structure, which still increases the manufacturing process, the quantity of masks, the production time, and the production cost. 
         [0005]    Hence, it is necessary to provide a TFT structure and a manufacturing method of the same to solve the technical issue. 
       SUMMARY OF THE INVENTION 
       [0006]    An objective of the present invention is to provide a thin film transistor (TFT) structure, which comprises a substrate, a light-shielding resin, a polysilicon, a gate electrode insulator, a gate electrode, an interlayer dielectric layer, a source electrode, and a drain electrode. 
         [0007]    The light-shielding resin is disposed on the substrate. The polysilicon is disposed on the light-shielding resin. The gate electrode insulator is disposed on the substrate and the polysilicon. The gate electrode is disposed close to the gate electrode insulator. An interlayer dielectric layer is disposed on the gate electrode insulator and the gate electrode. A source electrode and a drain electrode are disposed on the interlayer dielectric layer. The source electrode and the drain electrode are respectively connected with the polysilicon by two through holes. 
         [0008]    In one preferred embodiment, the through holes penetrate the interlayer dielectric layer and a portion of the gate electrode insulator. 
         [0009]    In one preferred embodiment, the light-shielding resin comprises an epoxy resin or polyurethane. 
         [0010]    In one preferred embodiment, the TFT structure further comprises a planar and a transparent conduction layer, the planar is disposed on a portion of the source electrode and the drain electrode, and overlaps the interlayer dielectric layer; the transparent conduction layer is disposed on the planar and another portion of the source electrode and the drain electrode. 
         [0011]    In one preferred embodiment, the polysilicon comprises a channel-doping region and two through-hole-doping regions, the through-hole-doping regions and the two through holes connect with each other and complete doping by the two through holes, the source electrode and the drain electrode are connected with the through-hole-doping regions on two sides of the channel-doping region by the two through holes. 
         [0012]    An objective of the present invention is to provide a TFT structure manufacturing method, which comprises: first, a substrate is deposited; then, a resin layer is deposited on the substrate, and a first mask is used to form a light-shielding resin; then, a polysilicon layer is deposited, and a second mask is used to form a polysilicon on the light-shielding resin; then, a first doping is performed on the polysilicon; a gate electrode insulator is deposited on the substrate and the polysilicon; then, a first metal layer is deposited, and a third mask is used to form a gate electrode on the gate electrode insulator; then, an interlayer dielectric layer is deposited on the gate electrode insulator and the gate electrode; then, a fourth mask is used to form two through holes in the interlayer dielectric layer and a portion of the gate electrode insulator; then, a second metal layer is deposited, and a fifth mask is used to form a source electrode and a drain electrode on the interlayer dielectric layer. The source electrode and the drain electrode are respectively connected with the polysilicon by two through holes. 
         [0013]    In one preferred embodiment, a doping to the polysilicon comprises the first doping and a second doping. The first doping is performed on the polysilicon after forming the polysilicon and before depositing the gate electrode insulator. The second doping is performed on the polysilicon through the two through holes after forming the two through holes. 
         [0014]    In one preferred embodiment, the polysilicon is completely doped in the first doping. 
         [0015]    In one preferred embodiment, a channel-doping region of the polysilicon is doped and through-hole-doping regions on two sides of the channel-doping region are not doped under the protection of the mask in the first doping. 
         [0016]    In one preferred embodiment, the through-hole-doping regions and the two through holes connect with each other and complete the second doping through the two through holes, to dope the through-hole-doping regions through the through holes by the second doping, to make the polysilicon form the channel-doping region and the through-hole-doping regions on two sides of the channel-doping region. 
         [0017]    In one preferred embodiment, the through-hole-doping regions and the two through holes connect with each other and complete the second doping through the two through holes, to dope the through-hole-doping regions through the through holes by the second doping, to make the polysilicon form the channel-doping region and the through-hole-doping regions on two sides of the channel-doping region. 
         [0018]    With the technical proposal of the present invention, the beneficial effect is: with the light-shielding resin which has functions of light-shield and insulation, an insulation layer is no longer disposed; besides, channel doping is performed on the polysilicon to make the polysilicon channel (where the region of the polysilicon corresponds with the gate electrode) to be N type or P type, in other words, with doping through the through holes on two ends to simplify the manufacturing process, simplify the exposure process, shorten the production time, decrease the usage of masks, and lower the production cost. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]      FIGS. 1-5, 6-1, 6-2, and 7-18  are side view drawings of each manufacturing process of the thin film transistor (TFT) of the present invention; 
           [0020]      FIG. 19  is a flowchart of a method of manufacturing the TFT structure according to the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0021]    The following description of each embodiment, with reference to the accompanying drawings, is used to exemplify specific embodiments which may be carried out in the present invention. Directional terms mentioned in the present invention, such as “top”, “bottom”, “front”, “back”, “left”, “right”, “inside”, “outside”, “side”, etc., are only used with reference to the orientation of the accompanying drawings. Therefore, the used directional terms are intended to illustrate, but not to limit, the present invention. 
         [0022]    Please refer to  FIG. 18 , which is a side view drawing of the thin film transistor (TFT) structure  100  of the present invention. The TFT structure  100  comprises a substrate  110 , a light-shielding resin  120 , a polysilicon  130 , a gate electrode insulator  140 , a gate electrode  150 , an interlayer dielectric layer  160 , a source electrode  172 , a drain electrode  171 , a planar  180 , and a transparent conduction layer  190 . 
         [0023]    The light-shielding resin  120  is disposed on the substrate  110 . In detail, the light-shielding resin  120  comprises an epoxy resin or polyurethane. The light-shielding resin  120  can not only shielding light but also serve as an insulation layer. 
         [0024]    The polysilicon  130  is disposed on the light-shielding resin  120 . The polysilicon  130  is used to provide electrons and holes for conduction. In detail, an area of the polysilicon  130  and an area of the light-shielding resin  120  are the same (perpendicular with the light&#39;s direction). The polysilicon  130  comprises a channel-doping region  133  and two through-hole-doping regions ( 131 ,  132 ), the through-hole-doping regions ( 131 ,  132 ) and the two through holes  170  connect with each other and complete doping by the two through holes  170 , the source electrode  172  and the drain electrode  171  are connected with the through-hole-doping regions ( 131 ,  132 ) on two sides of the channel-doping region  133  by the two through holes  170 . 
         [0025]    The gate electrode insulator  140  is disposed on the substrate  110  and the polysilicon  130 . In detail, the light-shielding resin  120  is disposed on a region where the polysilicon  130  and the gate electrode  150  are disposed, to avoid making the polysilicon generate a light leakage current. In other words, an area of the light-shielding resin  120  is larger than or equal to an area of the polysilicon  130  (perpendicular with the light&#39;s direction). The first metal layer  155  used to form the gate electrode  150  can be molybdenum. Referring to  FIGS. 8-9 , the gate electrode  150  are formed by using a third mask on the first metal layer  155 . The gate electrode insulator has high dielectric constant. 
         [0026]    The interlayer dielectric layer  160  is disposed on the gate electrode insulator  140  and the gate electrode  150 . In detail, the interlayer dielectric layer  160  completely covers the gate electrode  150  and other regions. The interlayer dielectric layer  160  is used to lower the capacitance value between the multi-layer wires. Generally, laminated layers of oxidized silicon-silicon nitride-oxidized silicon or laminated layers of oxidized silicon-silicon nitride are used to be flash memory of the interlayer dielectric layer  160 . 
         [0027]    The through holes  170  penetrate the interlayer dielectric layer  160  and a portion of the gate electrode insulator  140 . In detail, two through holes  170  penetrate the gate electrode insulator  140  and the interlayer dielectric layer  160 . For the two through holes  170  are deposited with the same material, the source electrode  172  and the drain electrode  171  respectively connect with two sides of the polysilicon  130 . 
         [0028]    In the preferred embodiment, the drain electrode  171  and the source electrode  172  are disposed on the interlayer dielectric layer  160 . However, in different preferred embodiments, the drain electrode  171  and the source electrode  172  can change position. A second metal layer used to form the drain electrode  171  and the source electrode  172  can be molybdenum/aluminum/molybdenum. 
         [0029]    The planar  180  is disposed on a portion of the drain electrode  171  and the source electrode  172 , and overlapping the interlayer dielectric layer  160 . In the preferred embodiment, the planar  180  completely overlaps the source electrode  172 , however, only partially overlaps the drain electrode  171 . 
         [0030]    The transparent conduction layer  190  is disposed on the planar  180  and another portion of the drain electrode  171  and the source electrode  172 . In the preferred embodiment, the transparent conduction layer  190  directly overlaps the drain electrode  171  which is not be overlapped by the planar  180 . The transparent conduction layer  190  can be indium tin oxide. 
         [0031]    A doping to the polysilicon  130  comprises the first doping and a second doping. The first doping is performed on the polysilicon  130  after forming the polysilicon  130  and before depositing the gate electrode insulator  140 . The second doping is performed on the two through-hole-doping regions ( 131 , 132 ) of the polysilicon  130  through the two through holes  170  after forming the two through holes  170 . 
         [0032]    Please refer to  FIGS. 1-19 ,  FIGS. 1-18  are side view drawings of each manufacturing process of the TFT of the present invention.  FIG. 19  is a flowchart of a method of manufacturing the TFT structure  100  according to the present invention. The method comprises: 
         [0033]    Step S 01 : as shows in  FIG. 1 , a substrate  110  is disposed. The substrate  110  can be a glass substrate or a transparent plastic baseplate. 
         [0034]    Step S 02 : as shows in  FIG. 2 , a resin layer  125  is deposited on the substrate  110 . As  FIG. 3  shows, the resin layer  125  is exposed and developed to form a light-shielding resin  120  by using a first mask  201 . 
         [0035]    Step S 03 : as shows in  FIG. 4 , a polysilicon layer  135  is deposited. As  FIG. 5  shows, the polysilicon layer  135  is exposed and developed to form a polysilicon  130  on the light-shielding resin  120  by using a second mask  202 . 
         [0036]    Step S 04 : as shows in  FIG. 6-1 , a first doping is performed on the polysilicon  130  by using a first doping mask  208 . In the preferred embodiment, the polysilicon  130  is whole and evenly doped. 
         [0037]    In another preferred embodiment, as  FIG. 6-2  shows, a first doping is performed on the polysilicon  130  by using a second doping mask  209 . In the preferred embodiment, channel-doping region  133  of the polysilicon  130  is doped; through-hole-doping regions ( 131 , 132 ) on two sides of the channel-doping region are protected from doping during the mask process. 
         [0038]    Step S 05 : as shows in  FIG. 7 , a gate electrode insulator  140  is deposited on the substrate  110  and the polysilicon  130 . The gate electrode insulator  140  can be SiOx, SiNx, or a combination of both. 
         [0039]    Step S 06 : as shows in  FIG. 8 , a first metal layer  155  is deposited by a chemical vapor deposition (CVD) or a vacuum evaporation (VE). As shows in  FIG. 9 , a third mask  203  is used to expose and develop the first metal layer  155 , to form a gate electrode  150  on the gate electrode insulator  140 . Generally, the first metal layer  155  can be molybdenum (Mo), aluminum (Al), aluminum alloy, titanium (Ti), copper (Cu), or wolfram (W). 
         [0040]    Step S 07 : as shown in  FIG. 10 , an interlayer dielectric layer  160  is deposited on the gate electrode insulator  140  and the gate electrode  150 . 
         [0041]    Step S 08 : as shown in  FIG. 11 , a fourth mask  204  is used to expose and develop the interlayer dielectric layer  160  and the gate electrode insulator  140 , to form two through holes  170  in the interlayer dielectric layer  160  and a portion of the gate electrode insulator  140 . 
         [0042]    Step S 09 : a second doping is performed on the polysilicon  130  through the two through holes  170 . The through-hole-doping regions ( 131 , 132 ) are connected with the two through holes  170  and complete the second doping by the two through holes. With the second doping to the through-hole-doping regions ( 131 , 132 ), the polysilicon  130  forms the channel-doping region and the through-hole-doping regions ( 131 , 132 ) on two sides of the channel-doping region  133 . 
         [0043]    Step S 10 : as shown in  FIG. 13 , a second metal layer  175  is deposited by a chemical vapor deposition (CVD) or a vacuum evaporation (VE). As  FIG. 14  shows, a fifth mask  205  is used to expose and develop the second metal layer  175 , to form a drain electrode  171  and a source electrode  172  on the interlayer dielectric layer  160 . For the second metal layer  175  fills the two through holes  170 , the drain electrode  171  and the source electrode  172  are respectively connected with the polysilicon  130  by two through holes  170 . 
         [0044]    Step S 11 : as shown in  FIG. 15 , a planar  180  is deposited. As shows in  FIG. 16 , a sixth mask  206  is used to expose and develop the planar  180 , to form the planar  180  only on a portion of the drain electrode  171  and the source electrode  172 , and overlap the interlayer dielectric layer  160 . 
         [0045]    Step S 12 : as shown in  FIG. 17 , a transparent conduction layer  190  is deposited on the planar  180  and another portion of the drain electrode  171  and the source electrode  172 . 
         [0046]    Step S 13 : as shown in  FIG. 18 , a seventh mask  207  is used to expose and develop the transparent conduction layer  190 , to form a notch on the drain electrode  171 . 
         [0047]    Although the present invention has been disclosed as preferred embodiments, the foregoing preferred embodiments are not intended to limit the present invention. Those of ordinary skill in the art, without departing from the spirit and scope of the present invention, can make various kinds of modifications and variations to the present invention. Therefore, the scope of the claims of the present invention must be defined.