Abstract:
A semiconductor memory device includes a masking unit for masking the generation of an undesired column access signal by using a write data masking signal, wherein the masking unit includes an address receiver for receiving control signals including a write data masking signal, a bank address column signal and a read/write strobe signal and a column address decoder for outputting a column access signal.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device capable of masking an undesired column access signal.  
         DESCRIPTION OF THE PRIOR ART  
         [0002]    [0002]FIG. 1A is a schematic circuit diagram showing a path to write data into a memory cell  150  and FIG. 1B is a timing chart for the circuit diagram of a prior art shown in FIG. 1A.  
           [0003]    Conventionally, when a data masking signal reaches an active level, global input/output data lines GIO/GIOZ, which are inputted into a write driver  110 , are masked. Namely, data, which are in global input/output data lines GIO/GIOZ, are not transmitted into local input/output data lines so that the data are not written in the memory cell  150 . However, a column access signal Yi, which is a control signal selecting column lines, is not masked.  
           [0004]    The column access signal Yi increases the voltage level of the bit line bar BLZ by transmitting the voltage of sub input/output lines SIO/SIOZ charged to an internal voltage level of Vintc bit lines BL/BLZ (NOT SHOWN). When the column access signal Yi disappears, the increased voltage level of the bit line bar BLZ returns to the original voltage level by the operation of a bit line sense amplifier  140 . However, if a precharge command is applied before the increased voltage level of the bit line bar BLZ returns to the original voltage level, the third NMOS transistor NM 3  is turned off because the voltage level of the word line WL becomes a low voltage level in the memory cell  150 . At this time, since the capacitor in the memory cell  150  is still charged with the increased voltage level, an original data, ‘0’, representing the discharged state of the capacitor, is lost. The bank write enable signal bwen inputted into the write driver  110  is a flag signal to enable the write of a bank. A block selection signal bs is a gate control signal to control the first NMOS transistor NM 1  in the block selection unit  120 .  
           [0005]    A write signal and data are inputted into the write driver  110  through the global I/O lines with a bank write enable signal bwen. Then the data inputted through the global input/output data lines GIO/GIOZ are transmitted to local input/output data lines LIO/LIOZ. When the block selection signal bs is applied to the block selection unit  120 , data is transmitted to the sub input/output lines SIO/SIOZ. When the column access signal Yi is applied to the column selection unit  130 , data is transmitted through the bitline sense amplifier  140  and to the memory cell  150  selected by a wordline and a bitline. If the data is masked at this time, data is not written in the memory cell  150 .  
           [0006]    When the write data masking signal wdm is inputted into the write driver  110  to mask the data, in the global input/output lines GIO/GIOZ, data is not transmitted to the local input/output lines LIO/LIOZ. However, a dummy column access signal is generated because control signals, except data, are not masked. When the undesired column access signal is applied to a second NMOS transistor NM 2  in the column selection unit  130 , voltage of the sub input/output lines SIO/SIOZ, which is precharged to Vintc, is applied to the bitline bar blz so that the voltage level of the bitline bar blz increases. If a precharge command is applied and the word line transistor NM 3  is turned off before the voltage level of the bitline bar blz returns to the original voltage level, the increased voltage is written in the memory cell  150  so that the data stored in the memory cell  150  is lost. Therefore, normal operation of the semiconductor memory device cannot be expected.  
         SUMMARY OF THE INVENTION  
         [0007]    It is, therefore, an object of the present invention to provide a semiconductor memory device capable of masking a dummy column access signal by using a write data masking signal.  
           [0008]    In accordance with an aspect of the present invention, there is provided a semiconductor memory device, comprising: a masking means for masking the generation of a column access signal by using a write data masking signal, wherein the masking means includes: a control signal generating means for receiving control signals including a write data masking signal, a column address signal and a read/write strobe signal and outputting a control signal to prevent the enabling of an undesired column access signal and a column address decoding means for outputting a column access signal in response to the control signal from the control signal generating means. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:  
         [0010]    [0010]FIG. 1A is a schematic circuit diagram showing a path to write data in a memory cell according to the prior art;  
         [0011]    [0011]FIG. 1B is a timing chart for the circuit diagram of the prior art shown in FIG. 1A;  
         [0012]    [0012]FIG. 2 is a schematic block diagram showing the generation of a column access signal according to the present invention;  
         [0013]    [0013]FIG. 3 is a circuit diagram showing the lay 12 _all block shown in FIG. 2 according to the present invention; and  
         [0014]    [0014]FIG. 4 is a circuit diagram showing the lay 12  block of FIG. 3 according to the present invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0015]    Hereinafter, a semiconductor memory device for masking inputted data that is to be written in a memory cell by using a data masking signal will be described in detail with reference to the accompanying drawings.  
         [0016]    [0016]FIG. 2 is a schematic block diagram showing the generation of a column access signal Yi through a lay 12 _all block  210 , which is a predecoder, and a Y decoder  220  according to the present invention.  
         [0017]    The lay 12 _all block  210  is a circuit to transform a bay 12  signal, which is a pre-decoded column address level signal, into a lay 12  signal, which is a pulse signal having a level of a desired range for controlling the Y decoder  220 . The bay 12  signal, a read/write strobe rdwtstbzp signal and a write data masking signal wdm are inputted into the lay 12 _all block  210 . The write data masking signal wdm masks the lay 12  signal, wherein the lay 12  signal is composed of the bay 12  signal and the read/write strobe signal rdwtstbzp, so that a generation of an undesired column access signal from the column address decoder  220  is prevented. A decoding process is carried out in the column address decoder  220  when the lay 12  signal has a logic value of ‘high’.  
         [0018]    Now, the lay 12 _all block  210  will be described in detail.  
         [0019]    [0019]FIG. 3 is a detailed circuit diagram showing the lay 12 _all block.  
         [0020]    Referring to FIG. 3, a write read bar signal wtrzt, which has a logic value of ‘high’ in the case of data write and a logic value of ‘low’ in the case of data read, is inputted into the lay 12 _all block  210  together with other signals.  
         [0021]    When data is written in a memory cell, the read write bar signal wtrzt is transited into logic value ‘high’. Accordingly, the first NMOS transistor NM 1  is turned on and the third PMOS transistor PM 2  is turned off. At this time, the read write strobe signal rdwtstbzp has a logic value of ‘low’ and the write data masking signal wdm has a logic value of ‘high’ so that the data masking bar signal dmz_lay 12  becomes a logic value of ‘low’. The data masking bar signal dmz_lay 12 , which has a logic value of ‘low’, is inputted into the lower lay 12  blocks  211 ,  213 ,  215  and  217  of the lay 12 _all block  210 . The lower lay 12  blocks  211 ,  213 ,  215  and  217  generate Y decoder decoding signals lay 12 &lt; 0 : 3 &gt;.  
         [0022]    [0022]FIG. 4 is a detailed circuit diagram showing the lower lay 12  blocks  211 ,  213 ,  215  and  217 .  
         [0023]    Referring to FIG. 4, the data masking bar signal dmz_lay 12  and the bay 12  signal are inputted into the first NAND gate NAND 1  wherein the output signal of the first NAND gate NAND 1  is inverted in an inverter I 1 . The output signal of the inverter I 1  is the Y decoder decoding signal lay 12 &lt; 0 : 3 &gt;, which is the output signal of the lay 12 _all block  210 .  
         [0024]    When the data masking bar signal dmz_lay 12  is transited into a logic value of ‘low’, the output signal of the first NAND gate NAND 1  becomes a logic value of ‘high’, independent of the logic value of the bay 12  signal. The bay 12  signal is a predecoding signal of the column address signal. The output of the first NAND gate NAND 1  is inverted into a signal with a logic value of ‘low’ in the inverter I 1 .  
         [0025]    In FIG. 2, a decoding process is carried out in the Y decoder when the Y decoder decoding signals lay 12 &lt; 0 : 3 &gt;have a logic value of ‘high’. This is to prevent the generation of an undesired column access signal.  
         [0026]    Accordingly, when the data masking signal is used to input the precharge command after inputting the write command, the loss of data stored in the memory cell can be prevented. Thus, a normal operation of the semiconductor memory device is expected.  
         [0027]    While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.