Abstract:
A method is described that induced dielectric breakdown within a capacitor&#39;s dielectric material while driving a current through the capacitor. The current is specific to data that is being written into the capacitor. The method also involves reading the data by interpreting behavior of the capacitor that is determined by the capacitor&#39;s resistance, where, the capacitor&#39;s resistance is a consequence of the inducing and the driving.

Description:
FIELD OF INVENTION 
   The field of invention relates generally to the electronic arts; and, more specifically, to non volatile data storage through dielectric breakdown. 
   BACKGROUND  
   Field Effect Transistors (FETs) have traditionally been built with a gate node, a source node and a drain node. Metal Oxide Semiconductor FETs (MOSFETs) are presently the most commonly manufactured type of transistor.  FIG. 1  shows a gate node  101  for a MOSFET. The gate node  101  is comprised of a metal and/or (more commonly) a heavily doped polycrystalline silicon layer which behaves like a metal. The gate node  101  is separated from an underlying conductive semiconductor region  103  by an oxide layer  102 . The gate node  101 , oxide  102  and conductive semiconductor region  103  essentially form a capacitor structure. 
   The electric field strength within the oxide layer  102  is proportional to the voltage between the gate node  101  and the underlying semiconductor wafer; and, the electronic field strength within the gate oxide layer is inversely proportional to the thickness of the oxide  102 . Thus, the higher the gate node  101  voltage and the thinner the oxide layer  102 , the greater the electric field strength. If “too strong” an electric field is established within the oxide layer  102 , the oxide layer  102  will suffer “dielectric breakdown”. 
   Dielectric breakdown is a form of oxide layer  102  damage. An oxide layer  102 , being a dielectric layer  102 , is an electrical insulator rather than an electrical conductor. As such, only an infinitesimal DC current I OX  (e.g., a few nanoamps (nA) or picoamps (pA)) will flow through oxide layer  102  if a voltage below a critical voltage at which dielectric breakdown occurs is applied to the gate node  101  and the oxide layer  102  has not already suffered dielectric breakdown. Because of the infinitesimal current, the DC resistance R OX  of the oxide layer  102  is said to be “near-infinite” (e.g., tens or hundreds of Megohms (MΩ)). 
   If the oxide layer  102  experiences dielectric breakdown, however, the behavior of the oxide layer  102  thereafter changes from that of an insulator to that of a semiconductor. Essentially, the DC resistance R OX  of the oxide layer  102  drops from its pre-breakdown value to a smaller value so as to allow a more substantial current such as tenths of microamps (μA) or higher. 
   Traditionally, the largest voltage that could reasonably be applied to a semiconductor chip&#39;s transistors has been well beneath the critical voltage at or above which dielectric breakdown could occur. With the continued miniaturization of transistor sizes and corresponding reduction in oxide thickness, however, it is presently more feasible to apply a gate voltage above a critical threshold value at or above which dielectric breakdown will occur. 

   
     FIGURES  
     The present invention is illustrated by way of example, and not limitation, in the figures of the accompanying drawings in which like references indicate similar elements and in which: 
       FIG. 1  shows a transistor gate structure; 
       FIG. 2   a  shows oxide current vs. applied gate voltage for oxides that have undergone different dielectric breakdown conditions; 
       FIG. 2   b  shows a circuit model for writing data into a gate dielectric; 
       FIG. 2   c  shows a circuit model for reading data from the gate dielectric; 
       FIG. 3  shows storage cell that is capable of storing data with a gate dielectric that has experienced dielectric breakdown; 
       FIG. 4  shows a method for writing to and reading from a storage cell formed with a gate dielectric that has experienced dielectric breakdown; 
       FIG. 5   a  shows a high voltage protection circuit constructed with an NVDMOS transistor; 
       FIG. 5   b  shows a high voltage protection circuit constructed with cascaded transistors; 
       FIG. 6  shows a memory array that stores information with gate dielectrics that have experienced dielectric breakdown; 
       FIG. 7  shows a computing system 
   

   DETAILED DESCRIPTION  
   It has been realized that information can be stored in dielectric material that has been subjected to dielectric breakdown. In particular, it has been realized that post breakdown DC resistance is a function of the conditions of the dielectric breakdown itself; and that, as a consequence, different data can be effectively stored in a dielectric layer by controlling the breakdown conditions it is subjected to. 
     FIGS. 2   a  through  2   c  explore the technique in more detail.  FIG. 2   a  shows oxide current vs. applied “post breakdown” gate voltage for gate oxides with identical material and structural composition that have undergone different dielectric breakdown conditions.  FIG. 2   b  shows an equivalent circuit for the dielectric breakdown condition. According to  FIG. 2   b , a voltage sufficiently high to cause dielectric breakdown (V PROG ) is applied to the gate node while a DC current (I PROG ) is forcibly driven through the dielectric. 
   Curve  201  of  FIG. 2   a  shows a DC resistance curve for a gate oxide that was subjected to an I PROG  of 1 mA during dielectric breakdown. Referring briefly to  FIG. 2   c , which shows an equivalent circuit for reading stored information from a dielectric after it has been subjected to breakdown, a DC resistance curve is simply a plot of the DC current (I OX ) through the dielectric, after it has been subjected to dielectric breakdown, that results when a DC voltage (V READ ) is applied across the dielectric. The read voltage V READ  should be sufficiently less than V PROG  so that the stored data is not changed through additional accidental breakdown caused by the application of the read voltage. 
   Curve  202  of  FIG. 2   a  shows a DC resistance curve for a gate oxide that was subjected to an I PROG  of 100 μA during dielectric breakdown. Curve  203  of  FIG. 2   a  shows a DC resistance curve for a gate oxide that was twice subjected to an I PROG  of 10 μA during dielectric breakdown for approximately 100 ms. Curve  204  of  FIG. 2   a  shows a DC resistance curve for a gate oxide that was subjected to an I PROG  of 10 μA only once during dielectric breakdown. 
   The same structure was used for each of the four gates structure (one distinct gate structure for each curve) used to generate the data of  FIG. 2   a . Each structure had a gate dielectric thickness of 20 Å and a gate length of 80 nm. The applied gate voltage V PROG  for inducing breakdown was 3.0 V for each of the four gates as well. 
   Because of the different breakdown conditions (i.e., the different applications of I PROG  during breakdown), the DC resistance curves  201 ,  202 ,  203 ,  204  of  FIG. 2   a  are different as well. In general, higher or more extensive I PROG  during breakdown results in lower observed DC resistance after breakdown. In a sense, stronger I PROG  during breakdown results in more damage to the dielectric; which, after breakdown, corresponds to less resistance/more current when the read voltage V READ  is applied across the dielectric. 
   As such, the structure submitted to the more extensive I PROG  during breakdown exhibits the lowest DC resistance (highest DC current)  201 . The structure submitted to the second most extensive I PROG  during breakdown exhibits the second lowest DC resistance (second highest DC current)  202 . The structure submitted to the third most extensive I PROG  during breakdown exhibits the third lowest DC resistance (third highest DC current)  203 . The structure submitted to the fourth most extensive I PROG  during breakdown exhibits the highest DC resistance (lowest DC current)  204 . 
   These properties can be used as a basis for storing data. For example, note that an applied read voltage V READ  of 1.0 v after breakdown results in an observed DC current I OX  of approximately 1 mA for curve  201 ; 10 μA for curve  202 ; 1 μA for curve  203 ; and 10 nA for curve  204 . Here, different I OX  currents can be made to correspond to different data. For example, referring to  FIG. 2   c , the observed current sense circuitry  205  could be designed to interpret, for an applied read voltage V READ  of 1.0 v: 1) “00” for a sensed I OX  of approximately 1 ma (curve  201 ); 2) “01” for a sensed I OX  of approximately 10 μA (curve  202 ); 3) “10” for a sensed I OX  of approximately 1 μA (curve  203 ); 4) “11” for a sensed I OX  of approximately 10 nA (curve  204 ). Of course, if more than four distinctly different breakdown conditions were imposed, more than four different data combinations could be stored by the dielectric (e.g., 8, 16, etc.). 
   In order to have initially written the data that the current sense circuitry  205  interprets, all that would need to be have been done is to apply the appropriate breakdown condition. That is: 1) I PROG =1 ma for “00”; 2) I PROG =100 μA for “01”; 3) I PROG =2×10 μA for “10”; and, 4) I PROG =1×10 μA for “11”. Because dielectric breakdown is a form of “permanent damage” a non volatile, “write once read many times” memory cell technology can therefore be implemented. 
     FIG. 3  shows an embodiment of a circuit designed to implement a non volatile, “write once read many times” memory cell through dielectric breakdown. Circuitry  303  is a current source that pulls the appropriate I PROG  current through a capacitor structure  301  having a dielectric that is subjected to a “write” programming voltage V PROG  sufficient to cause breakdown of the dielectric. Here, the capacitor structure can be formed with an FET transistor (such as a MOSFET) that has its drain and source tied together. 
   In an embodiment where NMOS type FETs are used, the capacitor structure is as shown in  FIG. 3  where the applied voltages are applied directly to the gate node. In an another embodiment where PMOS type FETs are used, the capacitor structure is still formed by tying the source and drain nodes together, however, unlike  FIG. 3 , the gate node is coupled to the protection circuitry and the voltages that are applied to the capacitor structure are applied directly to the source/drain node. 
   The “appropriate” I PROG  current is a current that sets a particular data value (e.g., as discussed above, 1 mA to implement curve  201  of  FIG. 2   a  for a data value of “00”). The current source circuit  303  can receive a first input command (SET I PROG ) that identifies the appropriate I PROG  current during a write; and, another input command to indicate if the capacitor  301  is deemed in write mode or read mode (R/W). If the capacitor  301  is deemed in write mode, a voltage V PROG  sufficient to cause breakdown may be applied to an electrode of the capacitor and the current sense circuit  304  is put into a high impedance state. 
   Because the V PROG  voltage is sufficient to damage other transistors in the integrated circuit that the capacitor structure  301  is integrated within, a high voltage protection circuit  302  is used to prevent the breakdown voltage V PROG  from damaging these other transistors. Here, the transistors from which the current source  303  and a current sense circuit  304  (for reading the data from the capacitor  301  after breakdown) are comprised are among those that are protected by the high voltage protection circuitry  302 . Thus, at least when the capacitor structure  301  is deemed to be in write mode, the high voltage protection circuitry  302  prevents the damaging high voltage V PROG  that is applied to the capacitor  301  during breakdown from reaching current source  303  and current sense circuit  304 ; while, permitting current source  303  to draw the appropriate I PROG  current during an actual write. 
   During a read, a non damaging read voltage V READ  can be applied to the capacitor structure. As such, any protection offered by protection circuit  302  may be immaterial. The current source  303  used to write data during read mode is effectively turned off, placed into a high impedance state or is otherwise made to not interfere with the current sensing activity of current sense circuit  304 . When V READ  is applied to the capacitor structure  301 , the current sensing circuit  304  receives current from the capacitor structure and interprets the amount of current received to particular read data value. The read data is provided at output node  306 . 
     FIG. 4  shows a methodology suitable for writing and reading data from a capacitor structure through dielectric breakdown. The methodology of  FIG. 4  is written with the view that the capacitor structure is a gate for an N type MOSFET transistor having its drain and source tied together. Those of ordinary skill will recognize that the methodology can be easily drawn P type MOSFET transistors and, more generally, to any type of capacitor structure. 
   According to the methodology of  FIG. 4 , a write includes setting the I PROG  current and enabling the protection of the high voltage protection circuitry  401 . Then, a voltage high enough to induce dielectric breakdown V PROG  is applied to the gate node  402 . For a read, a read voltage V READ  is applied to the gate node  403 . Then, the current that flows through the gate as a consequence of the applied read voltage is interpreted into specific read data  404 . 
     FIGS. 5   a  and  5   b  show two different embodiments for the high voltage protection circuitry.  FIG. 5   a  shows that a vertical double diffused MOS (vertical DMOS) transistor  502   a  can be used to implement the high voltage protection circuitry. A vertical DMOS transistor can be suitably tailored to not only receive the full V PROG  voltage without itself being damaged, but also can sustain a large voltage drop across its drain and source regions so as to protect the downstream circuitry. 
     FIG. 5   b  shows a cascoded arrangement of transistors  502   b , where the conductive channel of each transistor is part of the same conductive channel. Each transistor absorbs a different piece of the total voltage drop across the end-to-end conductive channel of the protection circuit  502   b . The voltage drop piece that any transistor is designed to support is less than or equal to the maximum voltage drop across the drain and source region that the transistor can handle. As such, none of the transistors are damaged by the application of the V PROG  voltage to the capacitive structure. 
   A voltage divider circuit  503  is used to divide a voltage V M  into discrete voltages that are appropriate gate voltages for each of the transistors in the cascode arrangement. Here, the appropriate gate voltage for each transistor helps in the formation of V GS  and V GD  voltages for the transistor that supports the range of current flow that could flow through the cascode arrangement and is within the maximum allowed V GS  and V GD  values specified for the transistor. 
   V M  can be any voltage sufficient to set-up the gate voltages as described just above. It is expected that, at least for writes, the V M  voltage will be larger than the standard supply voltage typically used for transistors of the type the cascode structure is constructed from (e.g., as found elsewhere in the integrated circuit such as the current sense circuit). In one embodiment V M =V PROG . In another embodiment V M =V PROG  for writes but V M  is something less than V PROG  for reads (e.g., the supply voltage used for the current sense circuit). Various circuitry approaches may be used to implement the voltage divider circuit  503  such as a network of passive elements (e.g., a resistor network, a resistor-diode network, etc.). 
   The protection circuits  302 ,  502  of  FIGS. 3 and 5  show an “enable” signal input that is used to establish a conductive channel between the capacitor structure and the circuitry being protected. When the enable signal is not asserted, the conductive channel is not present (e.g., by turning off the transistor(s) from which the conductive channel is comprised). In one embodiment, the enable signal itself has two states: write and read (or, the protection circuitry may be placed in either of the read or writes states when the enable signal is asserted). In the write state, the protection circuitry is configured to protect against a large voltage that is applied to the capacitive structure. In the read state the protection circuitry is not concerned with protection (e.g., by being configured to handle a small voltage drop compared to the write state) but still provides for a conductive channel. 
     FIG. 6  shows a memory array built with cells  601  where each cell stores data using a dielectric breakdown technique. According to the design of  FIG. 6 , cells are arranged into Y rows and X columns. Each column has its own dedicated current source for writing information into a cell (e.g., current source  603   1  for column x=1) and current sense circuit for reading data from a cell (e.g., current sense circuit  604   1  for column x=1). 
   The row select input  610  causes each cell along a particular row to receive an enable signal  602  at its protection circuitry. In an embodiment, assertion of the enable signal not only acts as an access voltage to all the cells in the particular row but also causes the protection circuitry to protect downstream circuitry in the case of a write and at least permit the DC current of the cell&#39;s capacitor structure to flow toward its corresponding column&#39;s current sense circuitry in the case of a read. 
   For example, in the case if the first cell from the first row  601   11  is to be selected, the value of the row select input  610  causes an enable signal to flow through the “first” channel of row select multiplexer  613  so as to be received by the protection circuitry for each of the cells along the first row  601   11 ,  601   21 , . . .  601   X1 . 
   In the case of a write, the cells of the first row each receive a voltage sufficient to cause their protection circuits to enter a state that protects their downstream circuitry. Moreover, again in the case if the first cell from the first row  601   11  is selected, cell  601   11  is given a voltage V PROG  that is sufficiently high to cause dielectric breakdown of the capacitor structure within cell  601   11 ; and, current source  603   1 , is set to pull the appropriate current I PROG  that sets the data value stored in the cell&#39;s capacitor structure. 
   In the case of a read, the cells of the first row each receive a voltage sufficient to cause their protection circuits to enter a state that at least permits the DC current of their corresponding capacitor structure to flow toward their corresponding column&#39;s current sense circuitry. Moreover, again in the case if the first cell from the first row  601   11  is selected, cell  601   11  is given a read voltage V READ  that causes an amount of DC current that corresponds to the data stored with cell  601   11  to flow out of the capacitor structure of cell  601   11 ; which, in turn, is sensed by current sense circuit  604   1 . For a read, the column select input  611  is used to present the interpreted data from sense circuit  604   1  at array output  614 . 
   Of course in an alternative embodiment, current source and sense circuitry could be allocated to each row rather than each column; and, the protection circuitry of each cell in a column could be enabled rather than each cell in a row. 
   Generally, the V PROG  and V READ  can be applied by circuitry configured to handle at least their respective voltages. In one embodiment, the respective voltages (or at least V PROG ) is supplied by way of a DC-DC converter. In a further embodiment the DC-DC converter is an on-chip DC-DC converter. Also, in other or related embodiments the capacitor structure used for storing information may be formed with the “triple gate” structure of a “triple gate” transistor. 
     FIG. 7  shows a computing system  700  adapted to use a non volatile memory  705  that achieves non volatile storage characteristics by way of dielectric breakdown of its constituent capacitors. The computing system includes a processor or controller  701 , “system memory”  702 , a display  703  (e.g., liquid crystal display (LCD), thin-film-transistor display (TFT), cathode ray tube (CRT)) and a keypad or keyboard  704 . Other components of the computing, such as its I/O, are not drawn for illustrative ease. 
   The computing system embodiment of  FIG. 7  may use the non volatile memory  705  to store various information such as the computing system&#39;s BIOS firmware. The computing system of  FIG. 7  should be adaptable to many different forms of computing systems such as personal computers, servers and handheld devices (e.g., PDAs, cellphones, etc.). 
   In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.