Abstract:
A method of manufacturing a semiconductor device that may include steps of forming a pad oxide layer and an insulating layer on a semiconductor substrate; and then performing a first etching process on the semiconductor device to form an insulating layer pattern exposing a portion of the pad oxide layer in a trench area; and then performing a second etching process with respect to the pad oxide layer by using the insulating layer pattern as a mask; and then performing a blanket ion implantation process with respect to the insulating layer pattern and the exposed portion of the pad oxide layer to form an ion layer in the semiconductor substrate; and then performing a third etching process with respect to the semiconductor substrate to simultaneously form a pad oxide layer pattern and a trench in the semiconductor substrate; and then forming an insulating layer on the semiconductor substrate including the trench; and then performing a planarization process with respect to the semiconductor substrate including the insulating material and removing the pad oxide layer pattern and the insulating layer pattern, thereby forming an isolation layer in the trench.

Description:
The present application claims priority under 35 U.S.C. 119 and 35 U.S.C. 365 to Korean Patent Application No. 10-2007-0061466 (filed on Jun. 22, 2007), which is hereby incorporated by reference in its entirety. 
   BACKGROUND 
   As semiconductor devices have become highly integrated, the size of a memory cell has been scaled down. Therefore, it is necessary to minimize the size of an isolation area. However, since the size of the isolation area is restricted due to a process of forming the isolation area and the arrangement of structures in a memory array, there are limitations in the reduction of the size of the isolation area. Accordingly, the isolation layer has been formed through a shallow trench isolation (STI) process providing a superior isolation characteristic with a narrow width instead of a local oxidation of silicon (LOCOS) process having a problem such as birds beak. In the STI process, a chemical mechanical polishing (CMP) may be performed after forming a trench in a semiconductor substrate and filling the trench with an oxide layer. However, when the isolation layer is formed through the STI process, an electric field may be concentrated on the edge of the isolation layer, so that an undesirable transistor is formed to exert an influence on the characteristic of a device. 
   SUMMARY 
   Embodiments relate to a method of manufacturing a semiconductor device that may include at least one of the following steps: forming a pad oxide layer and an insulating layer on and/or over a semiconductor substrate; and then forming an insulating layer pattern which exposes a portion of the pad oxide layer in a trench area through a first etching process on the semiconductor device; and then performing a second etching process with respect to the pad oxide layer using the insulating layer pattern as a mask; and then forming an ion layer on and/or over the semiconductor substrate by performing a blanket ion implantation with respect to the insulating layer pattern and the pad oxide layer; and then forming a pad oxide layer pattern and a trench by performing a third etching process with respect to the semiconductor substrate; and then providing an insulating material on and/or over the semiconductor substrate including the trench; and then performing a planarization process with respect to the semiconductor substrate including the insulating material; and then removing the pad oxide layer pattern and the insulating layer pattern, thereby forming an isolation layer. 
   Embodiments relate to a method that may include at least one of the following steps: sequentially forming a first oxide layer, a nitride layer and a second oxide layer on a semiconductor substrate; and then performing a first etching process to expose a portion of the semiconductor substrate to thereby form a first oxide layer pattern, a nitride layer pattern and a second oxide layer pattern on the semiconductor substrate; and then forming a third oxide layer on the semiconductor substrate including the first oxide layer pattern, the nitride layer pattern and the third oxide layer pattern; and then performing a second etching process to expose a portion of the semiconductor substrate to thereby form a spacer on sidewalls of the first oxide layer pattern, the nitride layer pattern and the third oxide layer pattern; and then performing an ion implantation process using the second oxide layer pattern and the spacer as masks to thereby form an ion layer in the semiconductor substrate; and then performing a third etching process to thereby form a trench in the semiconductor substrate, wherein the depth of trench is adjusted using the ion layer; and then forming a fourth oxide layer on the semiconductor substrate and in the trench and also on sidewalls of the first oxide layer pattern, the nitride layer pattern and the second oxide layer pattern; and then performing as fourth etching process to thereby remove the first oxide layer pattern, the nitride layer pattern and the second oxide layer pattern; and then performing a cleaning process with respect to the semiconductor substrate. 
   Embodiments relate to a method that may include at least one of the following steps: sequentially forming a first oxide layer, a nitride layer and a second oxide layer on a semiconductor substrate; and then performing a first etching process to expose a portion of the first oxide layer and thereby form a nitride layer pattern and a second oxide layer pattern on the semiconductor substrate; and then performing an ion implantation process to form an ion layer at a predetermined depth in the semiconductor substrate; and then performing a second etching process using ions from the ion layer as an etching gas to thereby form a trench in the semiconductor substrate and a first oxide layer pattern; and then removing the second oxide layer pattern; and then forming a third oxide layer on the semiconductor substrate and in the trench and also on sidewalls of the first oxide layer pattern and the nitride layer pattern; and then performing as third etching process to thereby remove the first oxide layer pattern and the nitride layer pattern; and then performing a cleaning process with respect to the semiconductor substrate. 

   
     DRAWINGS 
     Example  FIGS. 1 to 15  illustrate a method of manufacturing a semiconductor device, in accordance with embodiments. 
   

   DESCRIPTION 
   In the description of an embodiment, when a layer is referred to as being “on/over” another layer, it can be directly “on/over” the other layer, or intervening layers may also be present. The thickness and size of each layer shown in the drawings can be simplified or exaggerated for the purpose of convenience or clarity. In addition, the size of each element may be reduced or magnified from the real size thereof. 
   Any reference in this specification to “one embodiment,” “an embodiment,” “example embodiment,” etc., means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is submitted that it is within the purview of one skilled in the art to affect such feature, structure, or characteristic in connection with other ones of the embodiments. 
   As illustrated in example  FIG. 1 , a method of manufacturing a semiconductor device in accordance with embodiments may include sequentially forming pad oxide layer  20 , nitride layer  30  and first oxide layer  40  on and/or over semiconductor substrate  10 . Pad oxide layer  20  may have a thickness in the range of between 30 to 500 Å, nitride layer  30  may have a thickness in the range of between 500 to 3000 Å and first oxide layer  40  may have a thickness in the range of between 300 to 2000 Å. Pad oxide layer  20  may serve to protect elements formed on and/or over semiconductor device  10 . Nitride layer  30  may be composed of at least one of an SiN layer and an oxynitride layer. 
   As illustrated in example  FIG. 2 , after forming a photoresist pattern on and/or over semiconductor substrate  10  including pad oxide layer  20 , nitride layer  30  and first oxide layer  40 , an etching process is performed with respect to the resultant structure, thereby forming first oxide layer pattern  42 , nitride pattern  32  and pad oxide layer pattern  22 . The etching process may be performed by injecting a mixture gas including C x H y F z  gas as a main etching gas and at least one of SF 6 , Cl 2 , N 2 , O 2 , HBr, Ar and He as an additive gas. 
   As illustrated in example  FIG. 3 , second oxide layer  50  may then be formed on and/or over semiconductor substrate  10  including first oxide layer pattern  42 , nitride pattern  32 , and pad oxide layer pattern  22 . Second oxide layer  50  may be composed of the same material as that of first oxide layer pattern  42  and pad oxide layer pattern  22 . 
   As illustrated in example  FIG. 4 , an etching process may then be performed with respect to second oxide layer  50 , thereby forming spacer  52  on and/or over sidewalls of first oxide layer pattern  42 , nitride pattern  32 , and pad oxide layer pattern  22 . Spacer  52  may have a thickness in the range of between 50 to 1000 Å. 
   As illustrated in example  FIG. 5 , an ion implantation process may then be performed using first oxide layer pattern  42  and spacer  52  as masks, thereby forming ion layer  60  in semiconductor substrate  10 . The ion implantation process may be performed using at least one of one of F + , Cl + , Br +  and I +  as a source with a dosage amount of in the range of between 1×10 10  [atoms/cm 2 ] to 1×10 18  [atoms/cm 2 ] at energy in the range of between 10 Kev to 120 KeV. Ion layer  60  may be formed at a depth in the range of between 1000 to 4000 Å from the uppermost surface of semiconductor substrate  10 . Ion layer  60  may be formed to adjust the depth of a trench to be formed in a subsequent step. 
   As illustrated in example  FIG. 6 , semiconductor substrate  10  may then be etched, thereby forming first trench  70  therein. The etching process to form first trench  70  may be performed by injecting a mixture of a combination of Cl 2 , BCl 3 , and SF 6  as a main etch gas and at least one of Ar, O 2 , N 2  and He as an additive gas. When ions are implanted in order to form ion layer  60 , defects may occur in the lattice of semiconductor substrate  10 , and an etch rate increases in the etching process to form first trench  70 . In addition, if an etching process is performed at a point of ion layer  60 , ions implanted into ion layer  60  may serve as etch gas, so that an etch rate is rapidly increased. In this case, an etch end point can be obtained by measuring the etch rate through optical emission spectroscopy. By obtaining the etch end point as described above, the depth of first trench  70  can be adjusted. Accordingly, a predetermined trench etching depth can be obtained, so that the characteristic of a device can be improved. Spacer  52  may be removed during the etching process. 
   As illustrated in example  FIG. 7 , an oxidation process may then be performed with respect to semiconductor substrate  10 , thereby forming second trench  72  that is obtained by rounding an upper edge of first trench  70 . The oxidation process may be performed by using a furnace. Through the oxidation process, thermal oxidation layer  75  may be formed in an exposed portion of first trench  70 . The edge of first trench  70 , on which energy is concentrated, may become rounded. Since second trench  72  having a rounded edge may be formed through the oxidation process, a hump phenomenon, which causes degradation of a characteristic of a transistor due to an electric field concentrated on an edge of a trench, can be prevented. Accordingly, the insulating characteristics between devices can be improved. 
   As illustrated in example  FIG. 8 , an insulating material may then be provided on and/or over semiconductor substrate  10  including thermal oxidation layer  75  in second trench  72 , and also on and/or over sidewalls of first oxide layer pattern  42 , nitride pattern  32 , and pad oxide layer pattern  22 . A CMP process may then be performed with respect to the resultant structure, thereby forming insulating layer  80 . Insulating layer  80  may be formed through the CMP process using nitride layer pattern  32  as an etch stop layer after the insulating material is provided on and/or over semiconductor substrate  10 . Insulating layer  80  may be composed of at least one of tetra ethyl ortho silicate (TEOS), undoped silicate glass (USG) and high density plasma (HDP) oxide layers. 
   As illustrated in example  FIG. 9 , first oxide layer pattern  42 , nitride layer pattern  32  and pad oxide layer pattern  22  may then be removed through an etching process. A cleaning process may then be performed to remove foreign matter and debris generated in the etching process, thereby forming isolation layer  85  formed on and/or over thermal oxidation layer  75  in second trench  72 . In the etching and cleaning processes, an exposed portion of insulating layer  80  may be partially removed, thereby forming isolation layer  85 . Isolation layer  80  may include a portion which protrudes from second trench  72  and above the uppermost surface of semiconductor substrate  10 . 
   As illustrated in example  FIG. 10 , a method of manufacturing a semiconductor device in accordance with embodiments may include sequentially forming pad oxide layer  120 , nitride layer  130  and oxide layer  140  on and/or over semiconductor substrate  110 . Pad oxide layer  120  may have a thickness in the range between 30 to 500 Å, nitride layer  130  may have a thickness in the range between 500 to 3000 Å and first oxide layer  140  may have a thickness in the range between 300 to 2000 Å. Pad oxide layer  120  may serve to protect elements formed on and/or over semiconductor substrate  110 . Nitride layer  130  may be composed of at least one of an SiN layer and an oxynitride layer. 
   As illustrated in example  FIG. 11 , after forming photoresist pattern  145  on and/or over oxide layer  140 , an etching process may be performed with respect to the resultant structure, thereby forming nitride layer pattern  132  and oxide layer pattern  142  on and/or over pad oxide layer  120 . A portion of pad oxide layer  120  may then be etched to reduce the thickness of pad oxide layer  120  in the range between 10 to 30 Å. The etching process may be performed by injecting a mixture including C x H y F z  gas as a main etch gas and at least one of SF 6 , Cl 2 , N 2 , O 2 , HBr, Ar and He as an additive gas. 
   As illustrated in example  FIG. 12 , a blanket ion implantation process may then be performed with respect to oxide layer pattern  142  and pad oxide layer  120  on and/or over semiconductor substrate  110 , thereby forming ion layer  160  in semiconductor substrate  110 . The ion implantation process may be performed using at least one of a halogen element such as F + , Cl + , Br +  and I +  as a source with a dosage amount of dose in the range between 1×10 10  [atoms/cm 2 ] to 1×10 18  [atoms/cm 2 ] at energy in the range between 10 Kev to 120 KeV. In addition, ion layer  160  may be formed at a depth in the range between 1000 to 4000 Å from the uppermost surface of semiconductor substrate  10 . Ion layer  160  may be formed in order to adjust the depth of a trench to be formed in a subsequent process. Subsequently, photoresist pattern  145  may then be removed through an ashing process. 
   As illustrated in example  FIG. 13 , pad oxide layer  120  and semiconductor substrate  110  may then be etched, thereby forming trench  170  and pad oxide layer pattern  120 . The etching process for forming trench  170  may be performed by injecting a mixture including a combination of Cl 2 , BCl 3  and SF 6  as a main etch gas and at least one of Ar, O 2 , N 2  and He as an additive gas. When ions are implanted in order to form ion layer  160 , defects may occur in the lattice of semiconductor substrate  110 , and an etch rate may increase in the etching process to form trench  170 . In addition, if an etching process is performed at a point of ion layer  60 , ions implanted into ion layer  60  may serve as an etch gas, so that an etch rate is rapidly increased. In this case, an etch end point can be obtained by measuring the etch rate through optical emission spectroscopy. The etch end point may be obtained as described above, so that the depth of trench  170  can be adjusted. Accordingly, a predetermined trench etching depth can be ensured, so that the characteristic of a device can be improved. Subsequently, oxide layer pattern  142  may then be removed through an ashing process. 
   As illustrated in example  FIG. 14 , an insulating material may be formed on and/or over semiconductor substrate  110  including trench  170 . A CMP process may then be performed, thereby forming insulating layer  180  in trench  170  and on and/or over sidewalls of nitride layer pattern  132  and pad oxide layer pattern  120 . Insulating layer  180  may be formed through the CMP process using nitride layer pattern  132  as an etch stop layer after the insulating material is provided on and/or over semiconductor substrate  110 . Insulating layer  180  may be composed of at least one of TEOS, USG and HDP oxide layers. 
   As illustrated in example  FIG. 15 , nitride layer pattern  132  and pad oxide layer pattern  120  may then be removed through an etching process. A cleaning process may then be performed to remove foreign matter and debris generated during the etching process, so that isolation layer  185  can be formed. In the etching and cleaning processes, an exposed portion of insulating layer  180  may be partially removed, thereby forming isolation layer  185 . Isolation layer  180  may include a portion which protrudes from trench  170  and above the uppermost surface of semiconductor substrate  110 . 
   Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.