Abstract:
An integrated circuit module comprising integrated coupling transmission structures protruding from the main body of the integrated circuit with extra substrate material removed around and/or under the coupling transmission structures.

Description:
STATEMENT OF GOVERNMENT INTEREST  
       [0001]     This invention was made with government support under Contract No. F336 15-99-C-1512 funded by the Air Force Research Laboratories and DARPA-MTO. 
     
    
     FIELD OF THE INVENTION  
       [0002]     This invention relates to Integrated Circuits with coupling transmission structures that are being used as onboard probes or onboard antennas, which eliminate ribbon/wire bonding as well as the higher order modes in the waveguide.  
       BACKGROUND AND PRIOR ART  
       [0003]     Monolithic Microwave Integrated Circuits (MMIC) are implemented with conventional microstrip or grounded coplanar waveguide (GCPW) circuit elements on thin semiconductor substrates. The thickness of the substrate depends on the frequency of operation. Although at mm-wave frequencies wafer measurements of MMICs have shown satisfactory performance, MMICs actually suffer significantly in performance once removed from the wafer and packaged using either a ribbon bond approach or a flip-chip approach. The ribbon bond and flip-chip packaging approaches have a severe and detrimental effect on the performance of the MMICs at mm-wave frequencies.  
         [0004]     At higher-mm-wave and sub-mm-wave frequencies, most of the measurement equipment and MMIC modules have waveguide Inputs/Outputs (I/Os). Researchers have demonstrated MMIC modules by coupling MMIC I/Os to waveguide using, either waveguide transitions or antennas. These transitions can be placed on a semiconductor substrate and ribbon bonded to the MMIC, as shown in  FIGS. 1 and 2 . However, transitions that have been placed on the MMIC semiconductor substrate degrade the MMIC module performance by introducing higher order parasitic modes because MMICs are developed on semiconductor materials like InP, SiGe, GaAs.  
         [0005]     The transitions that have been designed on high performance substrates are ribbon bonded to the MMIC. Unfortunately, the assembly approach is complicated, MMIC module designs with ribbon-bonding suffer from impedance mismatch and produce lower power than expected, and at sub-millimeter frequencies, planar coupling transmission structures need to have narrow width for desired circuit impedances.  
         [0006]     Transitions have also been integrated into the MMIC module. See Weinreb, S., Faier, T., Lai, R., Barsky, M., Leong, Y. C., and Samoska, L., “High-Gain 150-215-Ghz MMIC Amplifier with Integral Waveguide Transitions”, IEEE Microwave and Guided Wave Letters, Vol. 9, No. 7, pp 282-284, July 1999 (Weinreb). However; this approach still presents problems by introducing higher order modes. See  FIG. 3 .  
         [0007]     The presently disclosed technology addresses the issues of higher order modes, parasitic modes, impedance mismatches by utilizing an integrated waveguide MMIC module quite unlike Weinreb. The presently disclosed technology eliminates or reduces the higher order modes in the waveguide by etching away extra high resistivity substrate around and/or underneath the coupling transmission structures. This allows the development of high-performance MMIC modules and subsystems at sub-millimeter and higher-millimeter wave frequencies. 
     
    
     BRIEF DESCRIPTION OF THE FIGURES AND THE DRAWINGS  
       [0008]      FIGS. 1 and 2  depict transition probes, on a semiconductor substrate, ribbon bonded to the MMIC for waveguide coupling, “Prior Art”;  
         [0009]      FIG. 3  depicts a schematic of transition probes on the MMIC semiconductor substrate, “Prior Art”;  
         [0010]      FIG. 4A  depicts a thinned wafer with streets to define MMIC chip areas;  
         [0011]      FIG. 4B-4D  depict individual Integrated circuits located within MMIC chip areas;  
         [0012]      FIGS. 4E, 4F  and  4 G depict some of possible shapes and positions of the coupling transmission structures;  
         [0013]      FIG. 5A  depicts the integrated circuit with the substrate material removed around the coupling transmission structures;  
         [0014]      FIG. 5B  depicts the integrated circuit with the substrate material removed around the coupling transmission structures placed in the waveguide;  
         [0015]      FIGS. 6   a - j  depict the process of removing the substrate material from around the coupling transmission structures that are extending from the integrated circuit;  
         [0016]      FIG. 7  depicts the integrated circuit with the substrate material removed from around and under the transition probes;  
         [0017]      FIGS. 8   a - l  depict the process of removing the substrate material from around and under the coupling transmission structures that are extending from the integrated circuit;  
         [0018]      FIG. 9  depicts the integrated circuit including an etch stop layer wherein the substrate material removed from around and under the transition probes;  
         [0019]      FIGS. 10   a - l  depict the process of removing the substrate material from around and under the coupling transmission structures that are extending from the integrated circuit by using an etch stop layer.  
     
    
     DETAILED DESCRIPTION  
       [0020]     The present disclosure addresses the issues of higher order modes, parasitic modes, and impedance mismatches in the waveguide by disclosing an integrated waveguide MMIC. Based on the presently disclosed technology, monolithic modular components can be developed to eliminate the need for wirebonding planar coupling transmission structure-to-waveguide transition probes. The transition probe or antenna, depending on the desired function, is an integral part of the MMIC chip. The higher order modes in the waveguide can be eliminated or reduced by etching away extra high resistivity substrate around the coupling transmission structure (coupling probe or antenna). The reduction of higher order modes allows MMICs to operate at sub-millimeter and higher-millimeter wave frequencies.  
         [0021]      FIG. 4A  shows a wafer  10  with streets  11  defining MMIC chip areas  12  before the chips are released from the wafer. MMIC chips  13 ,  14  and  15 , as shown in  FIGS. 4B, 4C  and  4 D, respectively, depict individual Integrated Circuits (ICs) located with in MMIC chip areas  12  of the wafer  10 .  
         [0022]     Integrated Circuits  18  are developed on the substrate material  19  of a wafer  10  with coupling transmission structures  20  extending from the Integrated Circuits  18 , as shown by  FIGS. 4B, 4C  and  4 D.  
         [0023]     This disclosure is not limited to shape and positions of the coupling transmission structures  20  as depicted in  FIGS. 4B  to  4 D. Coupling transmission structures  20  can vary in shape and can extend at different locations from the Integrated Circuit  18 , for example, see  FIGS. 4E, 4F  and  4 G.  
         [0024]     In one embodiment, the presently disclosed technology improves the performance and reduces higher order modes of the Integrated Circuit module by removing excess semiconductor substrate material  19  around the coupling transmission structures  20 , as shown by  FIG. 5A . In this embodiment, the peripheral edge of the semiconductor substrate material  19  closely follows the peripheral edges of the Integrated Circuit  18  and coupling transmission structures  20 . The distance between the peripheral edges of the semiconductor substrate material  19  and the peripheral edges of the Integrated Circuit  18  and coupling transmission structures  20  in  FIG. 5A  is exaggerated for illustration purposes.  
         [0025]      FIG. 5B  shows the placement of the Integrated Circuit  18  module as depicted in  FIG. 5A  inside the waveguide block  21 . The removal of the extra substrate material decreases higher order modes.  
         [0026]     The extra parasitic substrate material can be removed using a backside processing shown and described with reference to  FIGS. 6   a - j.    FIGS. 6   a - j  represent the cross section of a wafer, containing multiple ICs, for each of the backside process steps.  
         [0027]     In  FIG. 6   a,  a wafer comprises a substrate  30  and a circuitry layer  25 . The wafer is mounted with the circuitry layer  25  down on to a support substrate  40  and held in place with a wax or other suitable material  35 . The substrate  30  can be a semi-insulating semiconductor InP wafer, for example. The circuitry layer  25  contains multiple ICs.  
         [0028]     In  FIG. 6   b,  a thinning process is performed on the substrate  30 . The thinning process can be performed, for example, either by lapping the substrate  30 ; by etching the substrate  30  (wet or dry); grinding the substrate  30 ; or a combination of any of these processes can be used to obtain a desired thickness depending on design requirements.  
         [0029]     In  FIGS. 6   c - h,  a via process is performed on the substrate  30 . The via process can be performed by: applying and imaging a via mask  45  to the substrate  30 , as shown by  FIG. 6   c;  creating a via pattern  50  in the via mask  45 , as shown by  FIG. 6   d;  etching via holes  55  through the substrate  30  and removing the via mask  45 , as shown by  FIG. 6   e;  depositing a metallization layer  65  to the backside of the substrate  30  thereby covering via holes  55  with metal, as shown by  FIG. 6   f;  applying and imaging a metal mask  70  as shown by  FIG. 6   g;  etching the metallization layer  65 ; and removing the metal mask  70 , as shown by  FIG. 6   h.    
         [0030]     The via mask  45  and metal mask  70  can be but are not limited to a photoresist material. The metallization layer  65  can consist of but is not limited to first depositing Ti followed by Au metals. The metallization layer  65  can be developed by either evaporating or sputtering metal onto substrate  30  and then plating metal to desired thickness. Etching of the metallization layer  65  can be done through wet etch technique. Wet etching can consist of applying potassium iodide, to etch Au followed by hydrofluoric acid to etch Ti.  
         [0031]     In  FIGS. 6   i  and  6   j,  a disjoin process is performed on the substrate  30  and circuitry layer  25 . Upon completion of the disjoin process the individual ICs on the wafer will be disjoined from each other. The disjoin process can be performed by: applying and imaging an integrated circuit mask  80  to the substrate  30  exposing only the portions of the substrate  30  that are between the individual ICs, as shown by  FIG. 6   i;  etching through the substrate  30  and circuitry layer  25 ; and removing the integrated circuit mask  80 , as shown by  FIG. 6   j.    
         [0032]     Alternatively, the process of disjoining the individual ICs from the wafer can be accomplished by a laser die cutting process instead of masking and etching. The laser cutter is guided where the cutting is to be performed. Upon completion of the laser die cutting process, the individual ICs will be disjoined from each other, as shown by  FIG. 6   j.    
         [0033]     Finally, removing the wax or other suitable material  35  enables removal of the individual ICs from the support substrate  40 , as shown by  FIG. 6   j.  The wax  35  can be removed with Tetra-chloro-ethylene (TCE).  
         [0034]     In another embodiment, the presently disclosed technology improves the performance and reduces higher order modes of the IC by removing excess semiconductor substrate material  5  around and under the coupling transmission structures  20 , as shown by FIG.  7 . In this embodiment, the peripheral edge of the semiconductor substrate material  19  closely follows the peripheral edges of the Integrated Circuit  18  and coupling transmission structures  20 . The distance between the peripheral edges of the semiconductor substrate material  19  and the peripheral edges of the Integrated Circuit  18  and coupling transmission structures  20  in the  FIG. 7  is exaggerated for illustration purposes.  
         [0035]     The extra parasitic substrate material can be removed using a backside processing shown and described with reference to  FIGS. 8   a - l.    FIGS. 8   a - l  represent the cross section of a wafer, containing multiple ICs, for each of the backside process steps.  
         [0036]     In  FIG. 8   a,  a wafer comprises a substrate  130  and a circuitry layer  125 . The wafer is mounted with the circuitry layer  125  down on to a support substrate  140  and held in place with a wax or other suitable material  135 . The substrate  130  can be a semi-insulating InP wafer. The circuitry layer  125  contains multiple ICs.  
         [0037]     In  FIG. 8   b,  a thinning process is performed on the substrate  130 . The thinning process can be performed, for example, either by lapping the substrate  130 ; by etching the substrate  130  (wet or dry); grinding the substrate  130 ; or a combination of any of these processes can be used to obtain a desired thickness depending on design requirements.  
         [0038]     In  FIGS. 8   c - h,  a via process is performed on the substrate  130 . The via process can be performed by: applying and imaging a via mask  145  to the substrate  130 , as shown by  FIG. 8   c;  creating a via pattern  150  in the via mask  145 , as shown by  FIG. 8   d;  etching via holes  155  through the substrate  130  and removing the via mask  145 , as shown by  FIG. 8   e;  depositing a metallization layer  165  to the backside of the substrate  130  thereby covering via holes  155  with metal, as shown by  FIG. 8   f;  applying and imaging a metal mask  170  as shown by  FIG. 8   g;  etching the metallization layer  165 ; and removing the metal mask  170 , as shown by  FIG. 8   h.    
         [0039]     The via mask  145  and metal mask  170  can be, but are not limited to, a photoresist material. The metallization layer  165  can consist of but is not limited to first depositing Ti followed by Au metals. The metallization layer  165  can be developed by either evaporating or sputtering metal onto substrate  130  and then plating metal to desired thickness. Etching of the metallization layer  165  can be done through wet etch technique. Wet etching can consist of applying potassium iodide, to etch Au followed by hydrofluoric acid to etch Ti.  
         [0040]     In  FIGS. 8   i  and  8   j,  a coupling transmission structure thinning process is performed on the substrate  130 . Upon completion of the coupling transmission structure thinning process there is less substrate  130  material covering the coupling transmission structures extending from the individual ICs than there is substrate  130  material covering the circuitry of individual ICs. The coupling transmission structure thinning process can be performed by applying and imaging a coupling transmission structure mask  175  to the substrate  130 , which mask exposes only the portions of the substrate  130  that cover the coupling transmission structures extending from the individual ICs, as shown in  FIG. 8   i,  followed by etching the substrate  130  to remove a portion of the substrate  130  material covering the coupling transmission structures and removing the coupling transmission structure mask  175  covering the substrate  130 , as shown by  FIG. 8   j.    
         [0041]     Alternatively, the coupling transmission structure thinning process can be accomplished with a laser ablation process instead of masking and etching. The laser cutter is guided to where the thinning is to be performed. Upon completion of the laser ablation process a portion of the substrate  130  will be removed, as shown by  FIG. 8   j.    
         [0042]     In  FIGS. 8   k  and  8   l,  a disjoin process is performed on the substrate  130  and circuitry layer  125 . Upon completion of the disjoin process, the individual ICs on the wafer will be disjoined from each other. The disjoin process can be performed by: applying and imaging an integrated circuit mask  180  to the substrate  130  exposing only the portions of the substrate  130  that are between the individual ICs, as shown by  FIG. 8   k;  and etching through the substrate  130  and circuitry layer  125  and removing the integrated circuit mask  180 , as shown by  FIG. 8   l.    
         [0043]     Alternatively, the process of disjoining the individual ICs from the wafer can be accomplished by a laser die cutting process instead of masking and etching. The laser cutter is guided to where the cutting is to be performed. Upon completion of the laser die cutting process the individual ICs will be disjoined from each other, as shown by  FIG. 8   l.    
         [0044]     Finally, removing the wax or other suitable material  135  enables removal of the individual ICs from the support substrate  140 , as shown by  FIG. 8   l.  The wax  135  can be removed with Tetra-chloro-ethylene (TCE).  
         [0045]     In another embodiment, the presently disclosed technology improves the performance and reduces higher order modes of the IC by including an etch stop layer  204  under the circuitry layer  201  and removing all the excess semiconductor substrate material  203  that is under the portion of the etch stop layer that is under the coupling transmission structures  202 , as shown by  FIG. 9 . The presently disclosed technology is not limited to the etch stop layer being disposed between the circuitry layer  201  and the substrate material  203 . In this embodiment, the peripheral edges of the semiconductor substrate material  203  and etch stop layer  204  closely follow the peripheral edges of the circuitry layer  201  and coupling transmission structures  202 . The distances between the peripheral edges of the semiconductor substrate material  203  and etch stop layer  204  and the peripheral edges of the circuitry layer  201  and coupling transmission structures  202  in the  FIG. 9  are exaggerated for illustration purposes.  
         [0046]     The extra parasitic substrate material can be removed using a backside processing shown in  FIGS. 10   a - l.    FIGS. 10   a - l  represent the cross section of a wafer, containing multiple ICs, for each of the backside process steps.  
         [0047]     In  FIG. 10   a,  a wafer comprises a substrate  230 , an etch stop layer  210  and a circuitry layer  225 . The wafer is mounted with the circuitry layer  225  down on to a support substrate  240  and held in place with a wax or other suitable material  235 . The substrate  230  can be a semi-insulating InP wafer. The circuitry layer  225  contains multiple ICs.  
         [0048]     In  FIG. 10   b,  a thinning process is performed on the substrate  230 . The thinning process can be performed, for example, either by lapping the substrate  230 ; by etching the substrate  230  (wet or dry); grinding the substrate  230 ; or a combination of any of these processes can be used to obtain a desired thickness depending on design requirements.  
         [0049]     In  FIGS. 10   c - h,  a via process is performed on the substrate  230 . The via process can be performed by: applying and imaging a via mask  245  to the substrate  230 , as shown by  FIG. 10   c;  creating a via pattern  250  in the via mask  245 , as shown by  FIG. 10   d;  etching via holes  255  through the substrate  230  and the etch stop layer  210  and removing the via mask  245 , as shown by  FIG. 10   e;  depositing a metallization layer  265  to the backside of the substrate  230  thereby covering via holes  255  with metal, as shown by  FIG. 10   f;  applying and imaging a metal mask  270  as shown by  FIG. 10   g;  etching the metallization layer  265 ; and removing the metal mask  270 , as shown by  FIG. 10   h.    
         [0050]     The via mask  245  and metal mask  270  can be, but are not limited to, a photoresist material. The metallization layer  265  can be formed by, but is not limited to, first depositing Ti followed by Au metals. The metallization layer  265  can be developed by either evaporating or sputtering metal onto substrate  230  and then plating metal to a desired thickness. Etching of the metallization layer  265  can be done through wet etch technique. Wet etching can consist of applying potassium iodide to etch Au followed by hydrofluoric acid to etch Ti.  
         [0051]     In  FIGS. 10   i - j,  a coupling transmission structure thinning process is performed on the substrate  230 . Upon completion of the coupling transmission structure thinning process there is less substrate  230  material covering a portion of the etch stop layer  210  that is covering the coupling transmission structures extending from the individual ICs than there is substrate  230  material covering the rest of the etch stop layer  210 . The coupling transmission structure thinning process can be performed by applying and imaging a coupling transmission structure mask  275  to the substrate  230  exposing only the portions of the substrate  230  that cover the portion of the etch stop layer  210  that is covering the coupling transmission structures extending from the individual ICs, as shown in  FIG. 10   i,  followed by etching the substrate  230  to remove all the substrate  230  material that is covering the portion of the etch stop layer  210  covering the coupling transmission structures and removing the coupling transmission structure mask  275  covering the substrate  230 , as shown by  FIG. 10   j.    
         [0052]     In  FIGS. 10   k  and  10   l,  a disjoin process is performed on the substrate  230 , the etch stop layer  210  and circuitry layer  225 . Upon completion of the disjoin process the individual ICs on the wafer will be disjoined from each other. The disjoin process can be performed by: applying and imaging an integrated circuit mask  280  to the substrate  230  exposing only the portions of the substrate  230  that are between the individual ICs, as shown by  FIG. 10   k;  etching through the substrate  230 , the etch stop layer  210  and circuitry layer  225 ; and removing the integrated circuit mask  280 , as shown by  FIG. 10   l.    
         [0053]     Alternatively, the process of disjoining the individual ICs from the wafer can be accomplished by a laser die cutting process instead of masking and etching. The laser cutter is guided to where the cutting is to be performed. Upon completion of the laser die cutting process the individual ICs will be disjoined from each other, as shown by  FIG. 10   l.    
         [0054]     Finally, removing the wax or other suitable material  235  enables removal of the individual ICs from the support substrate  240 , as shown by  FIG. 10   l.  The wax  235  can be removed with Tetra-chloro-ethylene (TCE).  
         [0055]     The embodiments described in detail for exemplary purposes are, of course, subject to many different variations in structure, design and application. Since many varying and different embodiments may be made within the scope of the inventive concepts herein taught, and since many modifications may be made in the embodiment herein detailed in accordance with the descriptive requirements of the law, it is to be understood that the detailed embodiments provided above are to be interpreted as illustrative and not in a limiting sense.