Abstract:
A method of optimally generating a power failure warning (PFW) signal has been disclosed here in such a manner that adjusts timing of PFW signal generation according to load conditions in case of input AC voltage loss. A PFW voltage threshold value can be set at a lower value under light load conditions and at a higher value under heavy load conditions. PFW signal generation can also be triggered by a timing mechanism that is set when a bus voltage drops to a voltage threshold value. A countdown time of the timing mechanism is set according to a determined bus voltage drop rate. In this manner, issuance of the PFW signal is delayed for lighter load conditions and the power supply unit is capable of extending normal operation under lighter load conditions before the PFW signal is issued.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention is generally directed to the field of power supplies. More specifically, the present invention is directed to generating a power failure warning signal by an AC-to-DC power supply. 
       BACKGROUND OF THE INVENTION 
       [0002]    A power supply unit converts main AC voltage to one or more regulated DC voltages supplied to one or more loads, such as the internal components of a computer, server, or other electrical device. 
         [0003]      FIG. 1  illustrates a conventional power supply unit under digital control for supplying power to a server. The power supply unit includes a primary side for power factor correction (PFC) and AC-to-DC voltage conversion, and a secondary side for DC-to-DC voltage conversion. The primary side receives an AC input voltage, such as the main line AC voltage, and outputs a DC bus voltage, such as 400V. The secondary side converts the DC bus voltage output from the primary side to a desired DC voltage level that is used by a coupled load, such as 15V, 5V, or 3.3V. The PFC stage on the primary side is digitally controlled by a first digital signal controller (DSC). The DC-to-DC stage on the secondary side is digitally controlled by a second DSC or an analog control chip with a microcontroller (MCU) for management. There is bi-directional or unidirectional communication signals sent between the primary side and the secondary side. One such communication signal is a Power Failure Warning (PFW) signal sent from the primary side to the secondary side. The PFW signal is used for notifying the secondary side of the power supply, and even systems coupled to the secondary side, that action needs to be taken due to the near term power supply shutoff, which is typically a few milliseconds after input AC voltage loss. This warning gives the secondary side and/or system an opportunity to take proper measures such as unloading so as to avoid any damage or failure or even operating data loss due to AC voltage loss. The PFW signal is triggered when the DC bus voltage output from the PFC stage has decreased to a threshold level, typically resulting from the loss of the input AC voltage. In an exemplary implementation, the PFC stage includes a bulk capacitor coupled to store energy and also smooth the ripple on the bus voltage. It is the bulk capacitor that provides the stored energy to the secondary side for continuous operation during the intervals between input AC voltage loss and device shutoff. In normal operation, the normal bus voltage is a function of the AC voltage. However, when there is a power failure, the AC voltage is lost, and the bus voltage output from the PFC stage goes down due to the discharging of the bulk capacitor. Because the dropping voltage may impact safe operation of the secondary side, in practice the DC bus voltage level needs to be monitored. If the monitored DC bus voltage drops to a PFW voltage threshold, then the PFW signal is sent from the primary side to the secondary side. If the DC bus voltage level subsequently drops further to a shutoff voltage threshold, then the power supply unit is shutoff, thereby shutting off power supplied to a coupled load. 
         [0004]      FIG. 2  illustrates an exemplary timing diagram for implementation of the PFW signal relative to the bus voltage output from the PFC stage of  FIG. 1 . As shown in  FIG. 2 , the normal bus voltage is mainly a DC voltage plus secondary harmonics which depend on the characteristics of the specific power supply unit. At time t0, the input AC voltage is lost, at which point the DC bus voltage is no longer a function of the input AC voltage but instead is a result of the discharging energy stored in the bulk capacitor. The rate at which the bulk capacitor discharges, and therefore the rate at which the DC bus voltage decreases upon AC voltage loss is a function of the load coupled to the output of the DC-to-DC stage. The heavier the load, the greater the rate of DC bus voltage decrease. The rate at which the bus voltage decreases is barely changed if DC load has no change before and after AC voltage loss. When the DC bus voltage value decreases to a PFW voltage threshold, at time t1, the PFW signal is sent from the primary side to the secondary side. When the DC bus voltage value decreases to a shutoff voltage threshold, at time t2, the power supply unit is powered off. The time interval to is the time between issuing the PFW signal and power shutoff. The time interval tH is the hold-up time and is the time between input AC voltage loss and power shutoff. The hold-up time tH is the time delay before device shutoff provided by the bulk capacitor. 
         [0005]    Conventionally, the PFW voltage threshold and the shutoff voltage threshold are fixed values. Generation of the PFW signal only relies on the set value for the PFW voltage threshold regardless of load condition.  FIG. 3  illustrates exemplary timing diagrams corresponding to light load, intermediate load and heavy load conditions coupled to the power supply unit of  FIG. 1 . The timing diagram A corresponds to a heavy load condition. The timing diagram B corresponds to intermediate load conditions. The timing diagram C corresponds to light load conditions. As previously described and shown in  FIG. 3 , the rate of DC bus voltage decrease is greatest for heavy load conditions and least for light load conditions. Heavy loads draw more current which leads to faster drain of the energy stored in the bulk capacitor. Accordingly, the hold-up time tHA for heavy load conditions is shorter than the hold-up time tHB for intermediate load conditions, and the hold-up time tHB for intermediate load conditions is shorter than the hold-up time tHC for light load conditions. Similarly, the interval time between issuing the PFW signal and power shutoff is shortest for heavy load conditions, interval tA, longer for intermediate load conditions, interval tB, and longest for light load conditions, interval tC. 
         [0006]    The PFW voltage threshold and the shutoff voltage threshold are set such that the time interval between issuance of the PFW signal and power shutoff is set for worst case load conditions so as to ensure proper shutoff in the case of power loss. As heavy load conditions result in the greatest rate of DC bus voltage decrease, the PFW voltage threshold value and therefore the time interval between the issuance of the PFW signal and power shutoff is set according to the minimum time needed for shutdown, which corresponds to the heavy load condition and interval tA. For light and intermediate load conditions, the rate of DC bus voltage decrease is not as great, but the PFW voltage threshold is set according to the heavy load condition. This results in premature issuance of the PFW signal for intermediate and light load conditions, which unnecessarily constrains the run time of the power supply unit. For example, the time interval between issuance of the PFW signal and power shutoff for intermediate load conditions, interval tB, is greater than the necessary amount of time, which is interval tA. This difference between interval tB and interval tA is time that the device could be running, but is not. Similarly, the time interval tC for light load conditions is also greater than the necessary interval tA, and again results in unnecessary device down time. 
       SUMMARY OF THE INVENTION 
       [0007]    Embodiments are directed to a method of optimally generating a PFW signal in such a manner that adjusts timing of PFW signal generation according to load conditions. In some embodiments, the PFW voltage threshold value is set at a lower value under light load conditions and at a higher value under heavy load conditions. In other embodiments, PFW signal generation is triggered by a timing mechanism that is set when a bus voltage drops to a voltage threshold value. A countdown time of the time mechanism is set according to a determined bus voltage drop rate. In this manner, issuance of the PFW signal is delayed for lighter load conditions and the power supply unit is capable of extending normal operation under lighter load conditions before the PFW signal is issued. 
         [0008]    In an aspect, a method of generating a power failure warning signal is disclosed. The method includes monitoring a bus voltage of a power supply unit, adjusting a power failure warning voltage threshold value according to a varying load condition of a load coupled to an output of the power supply unit, and generating the power failure warning signal when the bus voltage drops to the power failure warning voltage threshold value. In some embodiments, adjusting the power failure warning threshold value includes determining a bus voltage drop rate and setting the power failure warning voltage threshold value according to the bus voltage drop rate to allow a minimum time period between generating the power failure warning signal and powering off the power supply unit to prepare for power shutoff. In some embodiments, adjusting the power failure warning threshold value includes determining the load condition and determining the power failure warning voltage threshold value according to the determined load condition so as to allow a minimum time period between generating the power failure warning signal and powering off the power supply unit to prepare for power shutoff. 
         [0009]    In another aspect, another method of generating a power failure warning signal is disclosed. The method includes setting a power shutoff voltage threshold value and setting a minimum time period to prepare for power shutoff. The method also includes measuring a bus voltage within a power supply unit and determining a bus voltage drop rate. The method also includes determining when a power failure warning signal is to be generated according to the power shutoff voltage threshold value, the minimum time period to prepare for power shutoff and the bus voltage drop rate. The method also includes generating the power failure warning signal. In some embodiments, the method also includes adjusting when the power failure warning signal is to be generated according to a load condition of a load coupled to an output of the power supply unit. In some embodiments, the bus voltage drop rate is greater for heavy load conditions than for light load conditions. In some embodiments, determining when the power failure warning signal is to be generated includes setting a power failure warning voltage threshold value by calculating a voltage equal to the bus voltage drop rate multiplied by the minimum time period to prepare for power shutoff and adding the calculated voltage to the power shutoff voltage threshold value, and comparing bus voltage to the set power failure warning voltage value. In this case, the power failure warning signal is generated when the bus voltage drops to the set power failure warning voltage value. In some embodiments, determining the bus voltage drop rate includes setting a first voltage threshold value and a second voltage threshold value, wherein the first voltage threshold value is greater than the second voltage threshold value and the second voltage threshold value is greater than the power shutoff voltage threshold value, comparing the bus voltage to the first voltage threshold value and the second voltage threshold value, counting a time for the bus voltage to drop from the first voltage threshold value to the second voltage threshold value, and calculating the bus voltage drop rate by dividing a voltage difference between the first voltage threshold value and the second voltage threshold value by the counted time. In this case, determining when the power failure warning signal is to be generated and generating the power failure warning signal can include calculating a first time period for the bus voltage to drop from the second voltage threshold value to the power shutoff voltage threshold value according to the calculated bus voltage drop rate, subtracting the minimum time period to prepare for power shutoff from the first time period to equal a second time period, setting a timer to count the second time period, and generating the power failure warning signal when the second time period is counted. In some embodiments, the bus voltage drop rate varies with varying load conditions of a load coupled to an output of the power supply unit. 
         [0010]    In yet another aspect, yet another method of generating a power failure warning signal is disclosed. The method includes setting a power shutoff voltage threshold value and setting a minimum time period to prepare for power shutoff. The method also includes receiving a load condition corresponding to a load coupled to an output of a power supply unit, determining when a power failure warning signal is to be generated according to the power shutoff voltage threshold value, the minimum time period to prepare for power shutoff and the received load condition, and generating the power failure warning signal. In some embodiments, the method can also include adjusting when the power failure warning signal is to be generated according to a varying load condition. 
         [0011]    In still yet another aspect, a device for generating a power failure warning signal is disclosed. The device includes means for monitoring a bus voltage of a power supply unit, means for adjusting a power failure warning voltage threshold value according to a varying load condition of a load coupled to an output of the power supply unit, and means for generating the power failure warning signal when the bus voltage drops to the power failure warning voltage threshold value. In some embodiments, the means for adjusting the power failure warning threshold value includes means for determining a bus voltage drop rate and means for setting the power failure warning voltage threshold value according to the bus voltage drop rate to allow a minimum time period between generating the power failure warning signal and powering off the power supply unit to prepare for power shutoff. In some embodiments, the means for adjusting the power failure warning threshold value includes means for determining the load condition and means for determining the power failure warning voltage threshold value according to the determined load condition so as to allow a minimum time period between generating the power failure warning signal and powering off the power supply unit to prepare for power shutoff. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    Several example embodiments are described with reference to the drawings, wherein like components are provided with like reference numerals. The example embodiments are intended to illustrate, but not to limit, the invention. The drawings include the following figures: 
           [0013]      FIG. 1  illustrates a conventional power supply unit under digital control for supplying power to a server. 
           [0014]      FIG. 2  illustrates an exemplary timing diagram for implementation of the PFW signal relative to the bus voltage output from the PFC stage of  FIG. 1 . 
           [0015]      FIG. 3  illustrates exemplary timing diagrams corresponding to light load, intermediate load and heavy load conditions coupled to the power supply unit of  FIG. 1 . 
           [0016]      FIG. 4  illustrates a conceptual implementation of a variable PFW voltage threshold for different load conditions according to an embodiment. 
           [0017]      FIG. 5  illustrates an exemplary method for determining a variable PFW voltage threshold value. 
           [0018]      FIG. 6  illustrates a conceptual implementation of the method of  FIG. 5  for a given load condition. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0019]    Embodiments of the present application are directed to a method of generating a power failure warning signal. Those of ordinary skill in the art will realize that the following detailed description of the method is illustrative only and is not intended to be in any way limiting. Other embodiments of the method will readily suggest themselves to such skilled persons having the benefit of this disclosure. 
         [0020]    Reference will now be made in detail to implementations of the method as illustrated in the accompanying drawings. The same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or like parts. In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. It will, of course, be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions must be made in order to achieve the developer&#39;s specific goals, such as compliance with application and business related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure. 
         [0021]      FIG. 4  illustrates a conceptual implementation of a variable PFW voltage threshold for different load conditions according to an embodiment. Three exemplary timing diagrams are shown in  FIG. 4 , each timing diagram corresponding to a different load condition. The timing diagram A corresponds to a heavy load condition. The timing diagram B corresponds to an intermediate load condition. The timing diagram C corresponds to a light load condition. At time t0, AC input voltage is lost, and the DC bus voltage is supplied by the energy stored in the bulk capacitor. Heavy loads draw more current which leads to faster drain of the bulk capacitor. The rate of DC bus voltage decrease is greatest for heavy load conditions and least for light load conditions. Accordingly, the slope of timing diagram A, which corresponds to the heavy load condition, is greater than the slope of timing diagram B, which corresponds to the intermediate load condition, and in turn the slop of the timing diagram B is greater than the slope of the timing diagram C, which corresponds to the light load condition. The slope of each timing diagram is a function of the decreasing DC bus voltage versus time. 
         [0022]    The power supply unit requires a set amount of time to prepare for power shutdown. This minimum time is application specific. The PFW voltage threshold value is set so as to provide the required time to prepare for power shutdown. For the heavy load condition, the PFW voltage threshold value is set at PFW voltage threshold value A. Value A is great enough that at the rate of bus voltage decrease corresponding to timing diagram A, the time to for the bus voltage to decrease from the PFW voltage threshold value A to the shutoff voltage threshold is equal to the required time to prepare for power shutdown. However, at lighter load conditions, such as the intermediate load condition corresponding to timing diagram B, the rate of bus voltage decrease is not as great and therefore the PFW voltage threshold value for the intermediate load condition does not need to be as great as the PFW voltage threshold value A corresponding to the heavy load condition. Since the rate of bus voltage decrease is lower for the intermediate load condition than for the heavy load condition, shown in  FIG. 4  as the timing diagram B having a smaller slope than the timing diagram A, the PFW voltage threshold value for the intermediate load condition is set at PFW voltage threshold value B. As shown in  FIG. 4 , the PFW voltage threshold value B is set at a lower voltage level than the PFW voltage threshold value A. Due to the lower rate of bus voltage decrease for the intermediate load condition, the lower PFW voltage threshold value B still provides the required time, time tA, to prepare for power shutdown. For illustrative purposes,  FIG. 4  shows the amount of time tB that would have been provided to prepare for power shutdown if the same PFW voltage threshold value A had also been used for the intermediate load condition. By instead using the lowered PFW voltage threshold value B for the intermediate load condition the device extends its normal operating time. The amount of extended normal operating time is equal to the difference between time tB and tA (tB-tA). In other words, the power supply unit, and the intermediate load coupled to the power supply unit, is capable of extending normal operation before the PFW signal is issued. 
         [0023]    Similarly, the rate of bus voltage decrease continues to decrease for still lighter load conditions, such as the light load condition corresponding to timing diagram C. The rate of bus voltage decrease is not as great for the light load condition as for the intermediate load condition and therefore the PFW voltage threshold value for the light load condition does not need to be as great as the PFW voltage threshold value B corresponding to the intermediate load condition. Since the rate of bus voltage decrease is lower for the light load condition than for the intermediate load condition, shown in  FIG. 4  as the timing diagram C having a smaller slope than the timing diagram B, the PFW voltage threshold value for the light load condition is set at PFW voltage threshold value C. As shown in  FIG. 4 , the PFW voltage threshold value C is set at a lower voltage level than the PFW voltage threshold value B. Due to the lower rate of bus voltage decrease for the light load condition, the lower PFW voltage threshold value C still provides the required time, time tA, to prepare for power shutdown. For illustrative purposes,  FIG. 4  shows the amount of time tC that would have been provided to prepare for power shutdown if the same PFW voltage threshold value A had also been used for the light load condition. By instead using the lowered PFW voltage threshold value C for the light load condition the device further extends its normal operating time. The amount of extended normal operating time under the light load condition is equal to the difference between time tC and tA (tB−tA). As compared to a fixed PFW voltage threshold value, a variable PFW voltage threshold value, such as the PFW voltage threshold B for the intermediate load condition and the PFW voltage threshold value C for the light load condition, enables extended normal operating time for the power supply unit under lighter load conditions. 
         [0024]    In some embodiments, the method of determining the variable PFW voltage threshold value utilizes a calculation algorithm implemented in firmware. In some embodiments, the method determines a rate of bus voltage decrease after AC voltage lost and using this determined rate to calculate the PFW voltage threshold value relative to a predetermined shutoff voltage threshold value.  FIG. 5  illustrates an exemplary method for determining a variable PFW voltage threshold value.  FIG. 6  illustrates a conceptual implementation of the method of  FIG. 5  for a given load condition. The exemplary implementation shown in  FIG. 6  corresponds to the heavy load condition of  FIG. 4 . It is understood that the method of  FIG. 5  can be applied to other load conditions. The method is implemented by a processing unit included within a power supply unit or alternatively by a processing unit externally coupled to the power supply unit. In some embodiments, the processing unit is a DSC included within the power supply unit. Memory sufficient for implementing the method can be included within the processing unit, separate from the processing unit and within the power supply unit, or externally coupled to the power supply unit. 
         [0025]    At the step  10 , a shutoff voltage threshold value for the power supply unit is set. When the bus voltage value reaches the shutoff voltage threshold value, the power supply unit is shutoff. As shown in  FIG. 6 , the set shutoff voltage threshold value corresponds to shutoff voltage threshold value V2. The shutoff voltage threshold value is a fixed, predetermined value based on design specifications of the power supply unit including the DC output voltage(s). 
         [0026]    At the step  20 , a first voltage threshold value is set. As shown in  FIG. 6 , the set first voltage threshold value corresponds to the first voltage threshold value Va1. 
         [0027]    At the step  30 , a second voltage threshold value is set. As shown in  FIG. 6 , the set second voltage threshold value corresponds to the second voltage threshold value Va2. The first voltage threshold value Va1 is greater than the second voltage threshold value Va2. The second voltage threshold value Va2 is greater than the shutoff voltage threshold value V2. Both the first voltage threshold value Va1 and the second voltage threshold value Va2 will be greater than a subsequently determined PFW voltage threshold value. In an exemplary application, the normal bus voltage when AC input voltage is present is approximately 400V, the first voltage threshold value Va1 is approximately 340V, the second voltage threshold value Va2 is approximately 330V, and the shutoff voltage threshold value V2 is approximately 316V. 
         [0028]    At the step  40 , the bus voltage is sampled and the sampled bus voltage value is compared to the first voltage threshold value Va1. If it is determined that the sampled bus voltage is greater than the first voltage threshold value Va1, then the step  40  is repeated for the next sampled bus voltage. If it is determined that the sampled bus voltage is less than or equal to the first voltage threshold value Va1, then as long as the bus voltage remains less than or equal to the first threshold voltage value Va1 the method moves to the step  50 . The bus voltage is sampled according to a determined sampling rate. In some embodiments, sampling is performed by the primary side DSC in the power supply unit. In other embodiments, a sampling circuit separate from the primary side DSC is used to sample the bus voltage. 
         [0029]    At the step  50 , a timer is started from a zeroed value. 
         [0030]    At the step  60 , the bus voltage is sampled and the sampled bus voltage is compared to the second voltage threshold value Va2. If it is determined that the sampled bus voltage is greater than the second voltage threshold value Va2, then the step  60  is repeated for the next sampled bus voltage. The sampled bus voltage is also compared to the first voltage threshold value Va1 to determine if the sampled bus voltage is still less than or equal to the first threshold voltage value Va1. If the sampled bus voltage remains less than or equal to the first threshold voltage value Va1, then the timer continues running and step  60  is repeated. If it is determined that the sampled bus voltage is less than or equal to the second voltage threshold value Va2, then the method moves to the step  70 . 
         [0031]    At the step  70 , the timer value is read, the value of which corresponds to the amount of time for the bus voltage to decrease from the first voltage threshold value Va1 to the second voltage threshold Va2. 
         [0032]    At the step  80 , the bus voltage drop rate is calculated. The bus voltage drop rate corresponds to the rate at which the bus voltage is decreasing. The bus voltage drop rate is calculated based on the known voltage drop between the first threshold voltage value Va1 and the second threshold voltage value Va2 and the time read out from the timer at the step  70 . Specifically, if the timer value is the difference between the time ta1 at which the sampled bus voltage equals the first voltage threshold value Va1 and the time ta2 at which the sampled bus voltage equals the second voltage threshold value Va2, then the timer value is ta2−ta1 and the bus voltage drop rate is equal to (Va1−Va2)/(ta2−ta1). 
         [0033]    At the step  90 , the bus voltage drop rate calculated in step  80  and the known voltage difference between the second voltage threshold value Va2 and the shutoff voltage threshold value V2 are used to calculate the time difference, t2−ta2, between the second voltage threshold value Va2 and the shutoff voltage threshold value V2. The time difference t2−ta2 is calculated by: 
         [0000]        t 2− ta 2=(( ta 2− ta 1)/( Va 2− Va 1))*( V 2− Va 2)  (1)
 
         [0000]    where (ta2−ta1)/(Va2−Va1) is the inverse of the voltage drop rate. 
         [0034]    At the step  100 , the predetermined time to required to prepare for power shutdown, which corresponds to the time difference between generating the PFW signal and power shutoff, is subtracted from the time difference between the second voltage threshold value Va2 and the shutoff voltage threshold value V2 calculated in the step  90 . The result of the calculation at the step  100  provides the amount of time for the bus voltage to drop from the second voltage threshold value Va2 to a minimum voltage where there remains time to issue a PFW signal, based on a voltage drop rate for current load conditions. The time difference t1−ta2 is calculated by: 
         [0000]        t 1− ta 2=( t 2− ta 2)− tA   (2)
 
         [0035]    At the step  110 , the time difference calculated at the step  100  is placed in a countdown timer. When the countdown timer reaches zero, a PFW signal is generated. 
         [0036]    The steps  80 ,  90 , and  100  are performed within a few processing cycles of the time ta2 when the timer value is read at the step  70 . As such, placing the calculated time difference from the step  100  into a countdown timer at the step  110  substantially corresponds to time ta2. As such, the countdown timer reaches zero at substantially time t1, and the PFW signal is appropriately generated, thereby leaving time tA before the power supply unit is shutoff. 
         [0037]    It is understood that the calculated voltage drop rate can be alternatively used to appropriately generate the PFW signal. For example, the bus voltage drop rate can be used along with the known shutoff voltage threshold value V2 and the known time tA required to prepare for power shutdown to calculate the PFW voltage threshold value. Once the bus voltage decreases to the calculated PFW voltage threshold value, the PFW signal is generated. 
         [0038]    In an alternative embodiment, the load condition is determined, such as by the secondary side DSC/MCU or some external controller coupled to the power supply unit, and the determined load condition is communicated to the primary side DSC. In an exemplary embodiment, the load condition is determined by measuring an amount of current drawn by the load from the power supply unit. The primary side DSC uses the received load condition to set a corresponding PFW voltage threshold value, such as by using a look-up table. 
         [0039]    The present application has been described in terms of specific embodiments incorporating details to facilitate the understanding of the principles of construction and operation of the method. Many of the components shown and described in the various figures can be interchanged to achieve the results necessary, and this description should be read to encompass such interchange as well. As such, references herein to specific embodiments and details thereof are not intended to limit the scope of the claims appended hereto. It will be apparent to those skilled in the art that modifications can be made to the embodiments chosen for illustration without departing from the spirit and scope of the application.