Abstract:
A circuit for dividing a reference current is composed of a number n of transistors connected in cascade, in a Darlington configuration, between current generator and a fractionary current output node and by N+k (where k is an integer different from zero) directly biased diodes in series, connected between the generator and the fractionary current output node. The circuit does not employ current mirrors, so all transistors may have the minimum size, which also minimizes the effects of leakage currents. Additionally, compensation elements may be used for compensating the leakage currents from the base regions of the transistors. The circuit is useful as a capacitance multiplier, or as a slow ramp generator in a large number of design situations. Independence from intrinsic parameters of the transistors used and/or from temperature of operation may be provided by employing a specifically designed reference current generator. Several embodiments are described.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority from EP 94830149.4, filed Mar. 29, 1994, which is hereby incorporated by reference. However, the content of the present application is not necessarily identical to that of the priority application. 
    
    
     CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority from EP 94830149.4, filed Mar. 29, 1994, which is hereby incorporated by reference. However, the content of the present application is not necessarily identical to that of the priority application. 
     BACKGROUND AND SUMMARY OF THE INVENTION 
     The present invention relates to an integrated capacitance multiplier circuit, and specifically to a ramp generator with a relatively long time constant that may be entirely integrated in a monolithic form. The circuit is able to provide a time constant in the order of several hundreds milliseconds, without requiring large capacitances that would be difficult to integrate and is useful in a large number of applications. 
     An ever increasing number of functions that are implemented in an integrated circuit (with the consequent limitation of the number of pins available)has led to the development of circuits that require a minimum number of externally connected components. 
     Notably parameters or functions that may be entirely integrated with increasing difficulty are relatively large time constants, for example on the order of several hundreds of milliseconds, which normally entail the use of large capacitances that are hardly integratable. 
     So-called capacitance multiplier circuits that can be fully integrated have been known for a long time. They commonly employ an operational amplifier, capable of controlling the charge current, necessarily of an extremely small value, of an integrated capacitor. A capacitance multiplier circuit, having improved characteristics of precision and thermal drift, is described in the European patent application No. 92830419.5, filed on Jul. 28, 1992, by the instant Applicant. 
     Capacitance multiplier circuits based on an operational amplifier are relatively complex and require a non-negligible area of integration. 
     A similar function may also be implemented by employing a simple constant current generator and a circuit capable of dividing the current by a factor in the order of thousands. Such circuits may be implemented by employing a plurality of cascaded current dividers, realized by current mirrors employing transistors of different size. A circuit of this kind, capable of achieving a ramp slope of about 100 V/sec with an integrated capacitance (C) of 10 pF, employing an easily integratable current generator capable of delivering a current of about 10 μA, is shown in FIG. 1. 
     In the reported example, it is necessary to divide the current Ir by a factor equal to 10,000. As shown in FIG. 1, the circuit may employ four cascaded current mirrors (current dividers), each dividing the current by 10. 
     A circuit of this type, is less burdensome than a capacitance multiplier based on the use of an operational amplifier, but still requires a non-negligible area of integration and the leakage currents of the tubs (corresponding to the base region of a transistor) within which the large size transistors are found and the substrate of the integrated circuit may assume a value that is comparable with the current I 2  (of about 1 nA) that must be delivered to the integrated capacitance C. At high temperature, the capacitance C may not charge at all. 
     Also an equivalent circuit of that depicted in FIG. 1, but implemented with NPN transistors instead than with PNP transistors would not provide any significant improvement. 
     The main aim of the present invention is to provide a ramp generator or a capacitance multiplier that can be fully integrated in a monolithic form while employing a reduced number of transistors that may have the minimum process size. 
     It is a further object of invention to provide as low ramp generator or capacitance multiplier having reduced area requirements and provided with means for compensating the leakage current of the tubs wherein the transistors that compose the circuit are formed, in order to ensure reliability of the circuit also at a high temperature of operation. 
     Basically, the circuit of the invention rests on the principle of employing the voltage drop across a number N of directly biased junctions for biasing a number N+k of junctions, where k an integer different from 0, and employing the current flowing through said N+k junctions for charging an integrated capacitance. The N, directly biased junctions are realized by an N number of transistors connected in cascade in a Darlington configuration, functionally connected between a reference current generator and a capacitor to be charged through a series of N+k diodes (junctions). The diodes are directly biased and functionally connected between the same reference current generator and the capacitor, schematically in a parallel arrangement with the cascaded Darlington configured transistors. 
     All transistors and diodes (or diode configured transistors) may have the minimum size that is allowed by the fabrication process of the integrated circuit. 
     It may be shown that the charge current of the integrated capacitance, which flows through the series of diodes, is inversely proportional by a factor given by the current transfer ratio (h FE ) of the N transistors used, in a common-emitter configuration, elevated at a power given by the ratio N/N+k (h FE   N/N+k ). 
     Using an integrated capacitance of about 10 pF, ramp slopes of about 100 V/sec may be easily achieved with only three, Darlington configured cascaded transistors and four diodes (diode-configured transistors). The charge current of the integrated capacitance that flows through the four diodes is given, in first approximation, by the product of the current generated by the current generator, elevated at a power 3/4, with the saturation current (Is) of the transistors used at a power of 1/4, divided by h FE   3/4 , that is: ##EQU1## 
     The circuit of the invention may also be implemented in different ways, for example in a way suitable to untie the value of the charge current from the h FE  parameter of the transistors used and/or compensate for non-negligible leakage currents, at a high temperature of operation. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The disclosed inventions will be described with reference to the accompanying drawings, which show important sample embodiments of the invention and which are incorporated in the specification hereof by reference, wherein: 
     FIG. 1 shows an integrated capacitance multiplier that may be employed as a ramp generator with a relatively large time constant, according to a known practice, as described above; 
     FIG. 2 shows a circuit according to the present invention which is functionally equivalent to the circuit of FIG. 1; 
     FIG. 3 shows the circuit of FIG. 2 provided with means for compensating leakage currents; 
     FIG. 4 shows a circuit made according to an alternative embodiment of the invention; 
     FIG. 5 shows an embodiment of a reference current generator employed in the circuit of FIG. 4. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The numerous innovative teachings of the present application will be described with particular reference to the presently preferred embodiment (by way of example, and not of limitation), in which: 
     FIG. 2 shows an integrated capacitance multiplier circuit that can be used as a ramp generator with a relatively large time constant, made according to the present invention. 
     According to this first embodiment, the circuit employs three bipolar PNP transistors (Q1, Q2 and Q3), connected in cascade, in a Darlington configuration (common emitter). 
     The base of Q3 is connected to the integrated capacitor C, the emitter of Q1 is connected to a reference current generator Ir, while the collectors of the transistors are connected in common to a common ground potential. 
     Four diodes (PN junctions), D1, D2, D3 and D4, are directly biased and are connected in series between the reference current generator Ir and the integrated capacitance C. 
     Consistently with the general requirements of minimizing the integration area, all the transistors used: Q1, Q2 and Q3, as well as the four diode configured transistors: D1, D2, D3 and D4, may advantageously have the same minimum dimensions that are permitted by the fabrication process of the integrated circuit. 
     The voltage drop across the three directly biased PN junctions (emitter-base junctions) of the transistors Q1, Q2, Q3, that is V1-V2, determines the biasing of the four PN junctions, that is of the diodes D1, D2, D3 and D4, thus controlling the current I 2  that flows through the diode chain D1 . . . D4, and which charges the integrated capacitance C (neglecting the contribution of the base current of the transistor Q3). 
     By analyzing the circuit one may write: ##EQU2## where V t  represents the so-called &#34;thermal voltage&#34; (equivalent to KT/q), I s  represents the saturation current of the transistors, β 1  and β 2  the current gains of Q1 and Q2, respectively (in a common emitter configuration). 
     From the equation (1) one obtains: ##EQU3## 
     Therefore, it is possible to derive the current I 2  that flows through the four diodes in series: ##EQU4## 
     Bringing the term 1/4 to exponent, neglecting unity and simplifying, the equation (3) may be simplified as follows: ##EQU5## that is: 
     In practicing the invention with a common fabrication process, ##EQU6## the decoupling transistor Q1 may be a PNP transistor of minimum area, as allowed by the process, for example of about 4300 μm2 for a high voltage application. If the base current of Q1 may be neglected and I r  =I 1 , by assuming: I1=30 μA, Is=-16 A, β1=β2=100, the current I 2  that is delivered by circuit will be equal to 1.28 nA, which is over 20,000 times less than I r . 
     By assuming I r  =I 1  and considering negligible the base current of Q1, the expression (5) may be rewritten as: ##EQU7## 
     Substantially, starting from a reference current I r , it is possible to derive a fractionary current I 2 , in a ratio that may be of four orders of magnitude, while employing a limited number of transistors, all of minimum size, with a marked saving of integration area. 
     The fractionary current I 2 , controlled by the voltage difference V1-V2, produced by the circuit of the invention, may be usefully employed for charging an integrated capacitance C, in order to produce on an output mode of the circuit (V out  =V 1 ), a voltage ramp. 
     The expression of the slope of the generated ramp may be obtained by dividing the expression (6) by the capacitance C, having assumed: I r  =I 1  and dV 1  /dt=dV 2  /dt. This derivation is justified by the fact that the voltage V 1  -V 2  is constant because a constant current flows through the transistors Q1, Q2 and Q3. Therefore the slope of the ramp will be given by: ##EQU8## 
     For a capacitance value of 10 pF and a reference current I r  of about 10 μA, ramps with a slope of about 100 V/sec may be obtained. 
     It is evident that the circuit of the invention lends itself to implement a capacitance multiplier circuit, that is a ramp generator circuit having a relatively large time constant, which is useful in a large number of design situations. 
     The embodiment depicted in FIG. 2 essentially employs bipolar PNP transistors. Of course the circuit may also be implemented with bipolar NPN transistors. 
     In an embodiment as the one depicted in FIG. 2, employing PNP transistors, the leakage currents of the tubs wherein the transistors are formed and the substrate of the integrated circuit could introduce errors and jeopardize the correct functioning at high temperature. 
     This occurrence may be prevented by implementing the circuit as shown in FIG. 3. The leakage of current of each tub may be effectively &#34;recovered&#34; (or compensated for) by employing an auxiliary PNP transistor, having a collector split in two parts. A first portion of the collector is short-circuited to the base to implement a diode configuration of the transistor, while the other portion of the collector injects in the tub of the transistor (that is in the base region thereof) a current that compensates the leakage current towards the substrate. 
     Of course, also these auxiliary transistors that maybe employed for compensating for the leakage current, may be transistors of minimum size, similar to the size of the other transistors that form the functional circuit. 
     According to an alternative embodiment of the invention, in order to satisfy particular design requirements of the circuit, for example in order to ensure a ramp slope independent from the h FE  parameters of the transistors used, the circuit may be implemented in an alternative form, as shown in FIG. 4. 
     The value of the charge current I.sub. 2 that is delivered to the integrated capacitance C may be untied from a direct dependency from the current transfer ratio (h FE ) of the transistors in a common emitter configuration, by employing as a reference current I r  a current that is purposely made dependent from the same parameters of the transistors h FE . This is obtained by generating the reference current I r  by means of a transistor Q4, driven through its space by a current generator I r , which is independent of the current gain of the transistors. In this way it is possible to nullify the dependency of the slope of the generated voltage ramp from said intrinsic parameter of the transistors used. 
     With reference to the circuit of FIG. 4, it is possible to demonstrate that the slope of the ramp is given by: ##EQU9## 
     A particularly preferred embodiment of a generator of a current I r&#39; , independent of the gain of transistors used, may be based on the use of a current generator that depends from the reverse junction current of the transistors used (substantially equivalent to the saturation current I s  of the transistors). Moreover, the generator may also be designed in such a way as to compensate, in terms of temperature drift, the ramp generating circuit. A current generator that satisfies both these requirements is depicted in FIG. 5. 
     The reference current generator I r , of FIG. 5 is dependent on the reverse junction current (which is substantially equivalent to the saturation current Is), of the transistor Q A  according to the following relationship: 
     
         I.sub.r&#39; =KI.sub.s.sup.-1/3 where K is a constant. 
    
     Moreover, the current generator of FIG. 5 is made temperature dependent according to an exponential law. It may be shown that the exponential factor of dependency from temperature may be pre-established by fixing the ratio between the resistances R1 and R2. 
     In the embodiment shown in FIG. 4, an effective temperature compensation of the entire circuit is achieved by verifying the following condition: ##EQU10## 
     Some other considerations which may be relevant in the circuits shown are as follows: 
     In the operation of the circuit of FIG. 2, with e.g. VCC=5 volts, the forward-biased junctions of transistors Q1, Q2, Q3 would quickly charge V2 and not turn on until Vout comes to 3 V be  &#39;s above ground, and from that point up Q1 would turn on and the slow ramping would proceed as described. The slow ramping would stop when V2 comes up to within three V be  &#39;s below VCC, plus whatever additional drop is introduced by the current source IR. 
     For practical timing circuits, a reset transistor would be used to initially discharge the capacitor until a timing cycle is desired. 
     With regard to the general formulation of the invention, that a number N of transistors is used together with a number N+K of diodes, the charging current would be even smaller if K is greater than 1. Having K=N would generally be undesirable, as tending to reduce head-room, but would reduce the base current of the last transistor (Q3 or equivalent) in the Darlington configuration. 
     Modifications and Variations 
     As will be recognized by those skilled in the art, the innovative concepts described in the present application can be modified and varied over a tremendous range of applications, and accordingly the scope of patented subject matter is not limited by any of the specific exemplary teachings given. For example, as will be obvious to those of ordinary skill in the art, other circuit elements can be added to, or substituted into, the specific circuit topologies shown. 
     In addition to timing circuits and ramp generators, the ability to provide an extremely small scaled-down copy of a reference current could be useful in oscillators. 
     Simple circuit modifications can be made to reduce the effect of the base current of transistor Q3 if necessary, but would not generally be necessary 
     In another embodiment, the circuits shown could be readily adapted to the dual NPN implementation. 
     As an alternative embodiment, the leakage-compensation auxiliary transistors added in FIG. 3 could be used on some but not all of the diode-connected transistors. 
     As another alternative embodiment, at least the diode-connected chain might be replaced by MOS transistors if desired. 
     As another alternative embodiment, it is possible that the complete circuit could be adapted to a MOS implementation, e.g. using subthreshold conduction in a chain of MOS diodes to supply the charging current.