Abstract:
A time multiplexing technique and corresponding circuitry which provides controlled access to one processor at a time of two or more access requesting processors, to a system resource shared by the two or more processors. Each of the access requesting processors is connected to an input of a plurality of multiplexers. Each of the multiplexers has a select input which determines which of the multiplexer&#39;s inputs becomes its output which is in turn, connected to an appropriate input of the system resource. By connecting together the select inputs of the multiplexers, access to the shared system resource is alternated between the two or more processors by alternating the value of the select input in response to the system clock.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates in general to techniques and circuitry for providing controlled access by one processor at a time of two or more processors, to a system resource shared by the two or more processors and in particular, to a time multiplexing technique and corresponding circuitry to provide such access. 
     Conventionally, arbiter circuitry is interposed between a system resource and two or more processors sharing access to that resource. If two or more processors request access to the resource at the same time, the arbiter circuitry determines which of the two or more processors is to be allowed access by a first-in-time and/or priority scheme. This prevents two or more processors from simultaneously accessing and/or modifying the contents of the shared resource and as a consequence, one processor contaminating the contents of the resource for the other processors. 
     Inclusion of arbiter circuitry in an integrated circuit chip, however, increases the size and complexity of the chip and as a result, can increase its cost and reduce its performance. Further, additional protocol handling requirements on the access requesting processors is required in order to interface with the arbiter circuitry and as a result, can interfere with the execution of other important activities being conducted by these processors. 
     OBJECTS AND SUMMARY OF THE INVENTION 
     Accordingly, one object of the present invention is to develop a technique and related circuitry for providing controlled access by one processor at a time of two or more processors, to a system resource shared by the two or more processors, without the aforementioned disadvantages of arbiter circuitry. 
     These and additional objects are accomplished by the various aspects of the present invention. One aspect of the invention accomplishes one or more of these objects by a method for sharing access to an electronic device between a plurality of access requesting devices, comprising the steps of: (a) establishing a sequential order in which the access requesting devices will be allowed access to the electronic device; (b) receiving a clock signal; and (c) providing access to a different one of the plurality of access requesting devices in a circular fashion using the established sequential order upon each new cycle of the clock signal. 
     Another aspect of the present invention is a method for sharing access to an electronic device between a plurality of access requesting devices, comprising the steps of: (a) receiving a clock signal and generating a select signal in response thereof; (b) receiving a control signal from each of the access requesting devices; and (c) selecting a control signal of one of the access requesting devices to act as a control input to the electronic device, wherein the selection of the one control input is determined by the generated select signal. 
     Still another aspect of the present invention is a circuit for providing shared access for a plurality of access requesting devices to an electronic device having a control input. The circuit includes means for receiving a clock signal and generating a select signal in response thereof, and means for receiving the select signal as well as a control signal from each of the access requesting devices, and selecting one of the received control signals to be an output of the receiving and selecting means, wherein the selected control signal is determined by the select signal and the resulting output is connected to the control input of the electronic device. 
     For example, in a preferred embodiment of the invention, the means for receiving the clock signal and generating a select signal in response thereof, comprises a frequency divider circuit which divides the received clock frequency by an integer value equal to the number of access requesting devices to generate the select signal; and the means for receiving the select signal and a control signal from each of the requesting devices, comprises a multiplexer having the select signal connected to its select input and each of the control signals from each of the requesting devices connected to an input of the multiplexer. 
     Additional objects, features and advantages of the various aspects of the present invention will become apparent from the following description of its preferred embodiment, which description should be taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates, as an example, a block diagram of a computer system utilizing aspects of the present invention; 
     FIG. 2 illustrates, as an example, a block diagram of an address multiplexing circuit utilizing aspects of the present invention; 
     FIG. 3 illustrates timing diagrams, utilizing aspects of the present invention, for selected signals in the example of FIG. 1, wherein two processors share access to a common system resource; and 
     FIG. 4 illustrates timing diagrams, utilizing aspects of the present invention, for selected signals in an example wherein three processors share access to a common system resource. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 illustrates, as an example, a block diagram of a computer system wherein two microprocessors (&#34;μP&#34;), 10 and 20, share access to a random-access-memory (&#34;RAM&#34;) 80. Access to the RAM 80 is controlled through multiplexers (&#34;MUX&#34;) 30, 40, 50 and 60, and data being read from the RAM 80 is controlled through a demultiplexer (&#34;DMUX&#34;) 90. 
     The RAM 80 receives address information from the MUX 40 over a system address bus 48, a read/write (&#34;R/W&#34;) signal from the MUX 50 over control line 54, and a chip select (&#34;CS&#34;) signal from the MUX 60 over control line 52. If the R/W signal indicates a write request, the RAM 80 receives data from the MUX 30 over a system data bus 38 and stores the received data at the address provided by MUX 40. On the other hand, if the R/W signal indicates a read request, the RAM 80 retrieves data stored at the address provided by MUX 40 and transmits the stored data to the DMUX 90 over the system data bus 38. 
     Each MUX, 30, 40, 50 and 60, has a select input (&#34;sel&#34;) and two selectable inputs (&#34;0&#34; and &#34;1&#34;). The select input determines which of the two selectable inputs is to be the output of the MUX. For example, if the select input equals a logical 0, then the input to the &#34;0&#34; input becomes the output of the MUX, and when the select input equals a logical 1, the input to the &#34;1&#34; input becomes the output for that MUX. The DMUX 90 also has a select input (&#34;sel&#34;), but instead of two selectable inputs, it has two selectable outputs (&#34;0&#34; and &#34;1&#34;). 
     Each of the access requesting μPs, 10 and 20, have control signals, address lines, and data lines connected to one of the inputs of each of the MUXs, 30, 40, 50 and 60, and the DMUX 90. For example, μP 10 has its CS signal connected to the &#34;0&#34; input of MUX 60 via control line 12, its R/W signal connected to the &#34;0&#34; input of MUX 50 via control line 14, address lines 16 connected to the &#34;0&#34; input of MUX 40, and data lines 18 connected to the &#34;0&#34; input of MUX 30 for writing data to the RAM 80 and to output &#34;0&#34; of DMUX 90 for reading data from the RAM 80. Likewise, μP 20 has its CS signal connected to the &#34;1&#34; input of MUX 60 via control line 22, its R/W signal connected to the &#34;1&#34; input of MUX 50 via control line 24, address lines 26 connected to the &#34;1&#34; input of MUX 40, and data lines 28 connected to the &#34;1&#34; input of MUX 30 for writing data to the RAM 80 and to output &#34;1&#34; of DMUX 90 for reading data from the RAM 80. 
     In order to simplify the description of the system, only single MUXs are shown connected to the address and data lines of μPs 10 and 20. In actual practice, however, each bit of the address and data lines preferably has a MUX associated with it so that parallel transfer of address information and data can be performed. 
     FIG. 2 illustrates an example where both μPs 10 and 20 have eight address lines. The first address line 161 of μP 10 is shown to be connected to a &#34;0&#34; input of a MUX 401, the second address line 162 of μP 10 to a &#34;0&#34; input of a MUX 402, and so on down to the eighth address line 168 of μP 10 which is connected to a &#34;0&#34; input of a MUX 408. Likewise, the first address line 261 of μP 20 is connected to a &#34;1&#34; input of the MUX 401, the second address line 262 of μP 20 to a &#34;1&#34; input of the MUX 402, and so on down to the eighth address line 268 of μP 20 which is connected to a &#34;1&#34; input of the MUX 408. The output of MUX 401 is then connected to the first address line A 0  of the system address bus 48, the output of MUX 402 connected to the second address line A 1  of the system address bus 48, and so on down to the output of MUX 408 which is connected to the eighth address line A 7  of the system address bus 48. 
     Each of the MUXs 401, 402, and so on down to MUX 408, has a select input (&#34;sel&#34;). Parallel transfer of address information from μP 10 to the system address bus 48 is accomplished by concurrently setting each of the select inputs to MUXs 401, 402, and so on down to MUX 408, to a &#34;0&#34;, and from μP 20 to the system address bus 48 by concurrently setting each of the select inputs to MUXs 401, 402, and so on down to MUX 408, to a &#34;1&#34;. Concurrent setting of the select inputs to MUXs 401, 402, and so on down to MUX 408, is accomplished by connecting together each of the select inputs for the MUXs 401, 402, and so on down to MUX 408. 
     A similar technique and structure could be described for parallel transfer of data to and from μPs 10 and 20 from and to the system data bus 38. For data transfer, however, in addition to a plurality of MUXs for transmitting data from the μPs 10 and 20 along their respective data lines 18 and 28, to the system data bus 38, a plurality of DMUXs for receiving data by the μPs 10 and 20 along their respective data lines 18 and 28, from the system data bus 38 is required. 
     Referring back now to FIG. 1, each of the MUXs 30, 40, 50 and 60, has a select input (&#34;sel&#34;) which determines which of its inputs, &#34;0&#34; or &#34;1&#34;, will become its output, and the DMUX 90 has a select input (&#34;sel&#34;) which determines which of its outputs, &#34;0&#34; or &#34;1&#34;, will be activated to pass through its input. When the select inputs of MUXs 30, 40, 50 and 60, and DMUX 90 are each a &#34;0&#34;, μP 10 has exclusive access to the RAM 80 for transmitting or receiving data to or from the RAM 80. Likewise, when the select inputs of MUXs 30, 40, 50 and 60, and DMUX 90 are each a &#34;1&#34;, μP 20 has exclusive access to the RAM 80 for transmitting or receiving data to or from the RAM 80. 
     Access to the RAM 80 is alternated between μPs 10 and 20 on a time basis, by connecting together the select inputs to MUXs 30, 40, 50 and 60, and DMUX 90 and then alternating the connected together select inputs between a &#34;0&#34; and a &#34;1&#34;. For example, as shown in FIG. 1, the connected together select inputs can be connected to a frequency divider (&#34;FD&#34;) 70 being driven by a system clock (&#34;CLK&#34;). By selecting a divide-by-2 circuit for the frequency divider 70, access to the RAM 80 can be alternated between μPs 10 and 20 on each cycle of the system clock CLK. A timing diagram illustrating this example is shown in FIG. 3. 
     Although the various aspects of the present invention have been described with respect to a preferred embodiment, it will be understood that the invention is entitled to full protection within the full scope of the appended claims. For example, the described method and circuit for controlling shared access to a RAM by two μPs, can be extended to more than two μPs and to other types of shared system resources (e.g., commonly shared registers). 
     To accomodate more than two μPs (or other access requesting devices), each of the MUXs 30, 40, 50 and 60, would preferably have the same number of inputs as the number of requesting devices, and the DMUX 90 would preferably have the same number of outputs as the number of requesting devices. For example, if there were three requesting devices, then each of the MUXs 30, 40, 50 and 60, would preferably have three inputs (e.g., &#34;0&#34;, &#34;1&#34;, and &#34;2&#34;), and the DMUX 90 would preferably have three outputs (e.g., &#34;0&#34;, &#34;1&#34;, and &#34;2&#34;). 
     Access between the three requesting devices can then be alternated on a time basis by connecting the first requesting device (e.g., μP10) to each of the &#34;0&#34; inputs of MUXs 30, 40, 50 and 60, and the &#34;0&#34; output of DMUX 90, the second requesting device (e.g., μP20) to each of the &#34;1&#34; inputs of MUXs 30, 40, 50 and 60, and the &#34;1&#34; output of DMUX 90, the third requesting device (e.g., μP30) to each of the &#34;2&#34; inputs of MUXs 30, 40, 50 and 60, and the &#34;2&#34; output of DMUX 90, and then alternating the connected together select inputs to MUXs 30, 40, 50 and 60, and the DMUX 90 between &#34;0&#34;, &#34;1&#34; and &#34;2&#34;. For example, the connected together select inputs to MUXs 30, 40, 50 and 60, and the DMUX 90 may be alternated between &#34;0&#34;, &#34;1&#34; and &#34;2&#34; by replacing the frequency divider 70 with a resettable counter (not shown) which increments its count on each clock cycle and resets its count after counting from &#34;0&#34; to &#34;2&#34;. A timing diagram illustrating this example is shown in FIG. 4.