Abstract:
A shift register circuit is provided that is adaptive for reducing a swing width of a clock voltage. In the shift register, a plurality of stages, one for each scanning line, generate first driving signals in response to first and second clock signals. A level shifter is connected between each the stages and its respective scanning line to receive the first driving signal, to thereby apply a second driving signal having a larger swing width than the first driving signal to the scanning line.

Description:
[0001]    This application claims the benefit of Korean Patent Application No. P2000-50907, filed on Aug. 30, 2000, which is hereby incorporated by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    This invention relates to driving circuitry for a liquid crystal display, and more particularly, to a shift register of a liquid crystal display driving circuit.  
           [0004]    2. Description of the Related Art  
           [0005]    Generally, a liquid crystal display (LCD) displays pictures by varying light transmissivity in the liquid crystal with selective application of electric field to the liquid crystal panel. In a matrix type LCD, pixel cells are arranged at intersections between data lines and scanning lines (e.g., gate lines). The data lines receive picture data from a data driver while the scanning lines receive scanning pulses from a scanning driver. The scanning driver includes a plurality of shift registers that sequentially apply the scanning pulses to the scanning lines.  
           [0006]    [0006]FIG. 1 is a block circuit diagram showing a configuration of a related art shift register. Referring to FIG. 1, the related art shift register includes n stages  2   1  to  2   n  in cascade configuration and connected to respective n row lines ROW 1  to ROWn via output lines  4   1  to  4   n . A start pulse SP is input to the first stage  2   1 , and each of the second to n-th stages  2   2  to  2   n , receives an output signal from its respective previous stage. Each of stages  2   1  to  2   n  is coupled to a row line ROWi connected to a pixel train and is selected using two of four clock signals C 1  to C 4 .  
           [0007]    [0007]FIG. 2 is a detailed circuit diagram showing the i-th stage and (i+1)-th stage of the related art shift register. Referring to FIG. 2, the i-th stage  2   i  includes second and fourth NMOS transistors T 2  and T 4  connected to a ground voltage VSS, a third NMOS transistor T 3  connected to a supply voltage VCC, fifth and sixth NMOS transistors T 5  and T 6  connected to the output line  4   i , and a first NMOS transistor T 1  supplied with an output signal g i−1  at the previous stage.  
           [0008]    The output signal g i−1  present at the previous stage is applied to gate terminals of the first and fourth NMOS transistors T 1  and T 4 . Drain terminals of the second NMOS transistor T 2 , the fourth NMOS transistor T 4  and the sixth NMOS transistor T 6  are connected to a ground voltage VSS. Gate terminals of the second and sixth NMOS transistors T 2  and T 6  are connected to a source terminal of the fourth NMOS transistor T 4  and a drain terminal of the third NMOS transistor T 3 . The first and third clock signals C 1  and C 3  are applied to the i-th stage  2   i , as shown in FIG. 2.  
           [0009]    An operation process of the i-th stage  2   i  will be explained with reference to FIG. 3 below. First, the third clock signal C 3  is applied to the gate terminal of the third NMOS transistor T 3 . If the third clock signal C 3  is applied, then the third NMOS transistor T 3  is turned on. When the third NMOS transistor T 3  is turned on, a supply voltage VCC is applied to a second node P 2  to turn on the second and sixth NMOS transistors T 2  and T 6 . At this time, a first node P 1  and the output line  4   i  are initialized at the ground voltage VSS.  
           [0010]    Subsequently, the output signal g i−1  at the previous stage is applied as a start pulse. If the output signal g i−1  from the previous stage is applied, then the first and fourth NMOS transistors T 1  and T 4  are turned on. When the fourth NMOS transistors T 4  is turned on, a second node P 2  is connected to the ground voltage VSS to turn off the second and sixth NMOS transistors T 2  and T 6 . On the other hand, when the first NMOS transistor T 1  is turned on, the output signal g i−1  from the previous stage is applied to the first node P 1 . At this time, the fifth NMOS transistor T 5  connected to the first node P 1  is turned on.  
           [0011]    After turning on the fifth NMOS transistor T 5 , the first clock signal C 1  is applied to the source terminal of the fifth NMOS transistor T 5 . The first clock signal C 1  applied upon turn-on of the fifth NMOS transistor T 5  is applied to the output line  4   i . In other words, the i-th output line  4   i  is selected. After the clock voltage signal C 1  is applied to the output line  4   i , the first clock signal C 1  is inverted into a low logic and thus the output line  4   1  also is supplied with a logic low voltage (i.e., a ground voltage).  
           [0012]    Typically, a gate line swing voltage of the related art LCD is approximately 20 to 25V. In order to fulfill this swing voltage, swing voltages of the clock signals C 1  to C 4  input to the shift register should be set to more than 20V.  
           [0013]    When the shift register is configured with NMOS transistors as shown in FIG. 2, clock signals C 1  to C 4  of 0 to 20V should be inputted for an application of a swing voltage of 20V to the gate line. On the other hand, when the shift register is configured with PMOS transistors, clock signals C 1  to C 4  of −8 to −12V should be inputted for an application of a swing voltage of 20V to the gate line. In other words, in the related art shift register, clock signals C 1  to C 4  having a large swing width are inputted from an external circuit (not shown) to the stages  2   1  to  2   n .  
           [0014]    The external circuit for supplying the clock signals C 1  to C 4  is configured within a single integrated circuit (IC) chip. The single IC chip generates clock signals C 1  to C 4  having a large swing width and applies them to the stages  2   1  to  2   n .  
           [0015]    However, while the external circuit of the related art (configured within the single IC chip) easily creates pulse signals having a low voltage (e.g., 0 to 10V), it has difficulty creating a voltage signal more than this low voltage or voltage signals at negative values. In other words, it is difficult to maintain reliable device characteristics according to the related art single IC chip because the external circuit has difficulty creating high voltages (e.g., more than 10V) and negative voltages. Thus, a high voltage or a negative voltage created by means of a single IC chip can cause erroneous operation resulting in adversely affected device characteristics.  
         SUMMARY OF THE INVENTION  
         [0016]    Accordingly, the present invention is directed to a shift register circuit that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.  
           [0017]    In one aspect of the present invention, a shift register provides a reduced swing width of a clock voltage.  
           [0018]    Additional features and advantages of the invention will be set forth in the description that follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.  
           [0019]    To achieve these and other advantages in accordance with the present invention, as embodied and broadly described, the shift register circuit according to the present invention includes a plurality of stages, each of the plurality of stages associated with a respective one of a plurality of scanning lines for generating a first driving signal in response to first and second clock signals, and a plurality of level shifters, each of the level shifters being connected between one of the plurality of stages and its associated scanning line for applying a second driving signal to the scanning line in response to the first driving signal, wherein the second driving signal has a larger swing width than the first driving signal.  
           [0020]    In another aspect of the present invention, a shift register circuit of the present invention includes a plurality of stages, each of the plurality of stages associated with a respective one of a plurality of scanning lines for generating a first driving signal in response to first and second clock signals, and a plurality of level shifters, each of the level shifters being connected between one of the plurality of stages and its associated scanning line for applying a second driving signal to the scanning line in response to the first driving signal, wherein the second driving signal has a larger swing width than the first driving signal, wherein the stages and the level shifters are configured within a single chip.  
           [0021]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]    The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:  
         [0023]    [0023]FIG. 1 provides a schematic block circuit diagram illustrative of a related art shift register.  
         [0024]    [0024]FIG. 2 is a detailed circuit diagram of two stages of the shift register shown in FIG. 1;  
         [0025]    [0025]FIG. 3 is a waveform diagram illustrative of driving signals applied to the stages shown in FIG. 2;  
         [0026]    [0026]FIG. 4 is a schematic block circuit diagram showing a configuration of an exemplary shift register according to a first embodiment of the present invention;  
         [0027]    [0027]FIG. 5 illustrates a circuit diagram of two stages and related level shifters of the exemplary shift register shown in FIG. 4;  
         [0028]    [0028]FIG. 6 is an exemplary waveform diagram of driving signals applied to the stages and the level shifters shown in FIG. 5;  
         [0029]    [0029]FIG. 7 illustrates a detailed circuit diagram of an exemplary stage and a level shifter in a shift register according to a second embodiment of the present invention; and  
         [0030]    [0030]FIGS. 8A and 8B are graphs illustrating simulation output waveforms of the shift register circuit shown in FIG. 7. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0031]    Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings.  
         [0032]    Referring to FIG. 4, there is shown a shift register circuit according to a first exemplary embodiment of the present invention. As shown in FIG. 4, the shift register circuit includes n stages  12   1  to  12   n  in cascade configuration. Each stage  12   1  is connected to a respective one of n row lines ROW 1  to ROWn via output lines  14   1  to  14   n , and n level shifters  13   1  to  13   n  are provided between the output lines  14   1  to  14   n  and the stages  12   1  to  12   n . Register stages  12   1  to  12   n  and level shifters  13   1  to  13   n  may be configured within a single chip.  
         [0033]    Generally, the shift register of the present invention operates by inputting a start pulse SP to the first stage while output signals present at the previous stages are applied to respective second to nth stages  12   2  to  12   n . Each of these stages  12   1  to  12   n  selects a row line ROWi connected to a pixel train according to two of four clock signals C 1  to C 4 , and each of the level shifters  13   1  to  13   n  is supplied with another one of the four clock signals C 1  to C 4 . For example, the first and third clock signals C 1  and C 3  are input to the first stage  12   1  while the second clock signal C 2  is input to the first level shifter  13   1 . However, it is to be understood that the clock signal input to the first level shifter  13   1  may be selected by any one of the clock signals having not been inputted to the first stage  12   1 . The level shifters  13   1  to  13   n  shift the levels of output signals from stages  12   1  to  12   n  and apply the level-shifted signals to the output lines  14   1  to  14   n .  
         [0034]    [0034]FIG. 5 is a detailed circuit diagram of a stage and a level shifter according to a first exemplary embodiment of the present invention. In FIG. 5, the i-th stage  12   i  includes second and fourth NMOS transistors T 2  and T 4  connected to a ground voltage VSS, a third NMOS transistor T 3  connected to a supply voltage VCC, fifth and sixth NMOS transistors T 5  and T 6  connected to the level shifter  13   i , and a first NMOS transistor T 1  supplied with an output signal g i−1  present at the previous stage.  
         [0035]    As shown in FIG. 5, the output signal g i−1  present at a stage previous to the i-th stage  12   i  is applied to gate terminals of the first and fourth NMOS transistors T 1  and T 4 . Drain terminals of the second NMOS transistor T 2 , the fourth NMOS transistor T 4  and the sixth NMOS transistor T 6  are connected to a ground voltage VSS. Gate terminals of the second and sixth NMOS transistors T 2  and T 6  are connected to a source terminal of the fourth NMOS transistor T 4  and a drain terminal of the third NMOS transistor T 3 . A first capacitor CP 1  is provided between the gate terminal of the fifth NMOS transistor T 5  and the ground voltage VSS.  
         [0036]    The i-th level shifter  13   i  includes seventh and eighth NMOS transistors T 7  and T 8  connected to the i-th stage  12   i  and ninth and tenth NMOS transistors T 9  and T 10  connected to the output line  14   i .  
         [0037]    A second clock signal C 2 , for example, is input to gate terminals of the seventh and tenth NMOS transistors T 7  and T 10 . The gate terminal of the eighth NMOS transistor T 8  and the source terminal of the seventh NMOS transistor T 7  are connected to the output of the stage  12   i . A high voltage V high  is applied to the source terminals of the eighth and ninth NMOS transistors T 8  and T 9 . The source terminal of the tenth NMOS transistor T 10  and the drain terminal of the ninth NMOS terminal are connected to the output line  14   i . The drain terminal of the tenth NMOS transistor T 10  is connected to the ground voltage VSS. A second capacitor CP 2  is connected between the output line and the drain terminal of the seventh NMOS transistor T 7 .  
         [0038]    An operation process of the shift register circuit will be described below in detail with reference to FIG. 6.  
         [0039]    First, the third clock signal C 3  is applied to the gate terminal of the third NMOS transistor T 3 . If the third clock signal C 3  is high, then the third NMOS transistor T 3  is turned on. When the third NMOS transistor T 3  is turned on, a voltage VCC is applied to a second node P 2  to turn on the second and sixth NMOS transistors T 2  and T 6 . At this time, a first node P 1  and the output line  14   i  are initialized to the ground voltage VSS.  
         [0040]    Subsequently, the output signal g i−1  at the previous stage is applied as a start pulse. If the output signal g i−1  at the previous stage is high, then the first and fourth NMOS transistors T 1  and T 4  are turned on. When the fourth NMOS transistors T 4  is turned on, a second node P 2  is connected to the ground voltage VSS to turn off the second and sixth NMOS transistors T 2  and T 6 . On the other hand, when the first NMOS transistor T 1  is turned on, the output signal g i−1  at the previous stage is applied to the first node P 1  and to the third node P 3 . Accordingly, a voltage corresponding to signal g i−1  is charged in the first capacitor CP 1  connected to the third node P 3 , and the fifth NMOS transistor T 5  turns on (by the voltage charged in the first capacitor CP 1 ). Thus, the first and second NMOS transistors T 1  and T 2  and the third and fourth NMOS transistors T 3  and T 4  act as controllers for controlling an output part of the shift register that includes the fifth and sixth NMOS transistors T 5  and T 6 .  
         [0041]    After the fifth NMOS transistor T 5  turns on, the first clock signal C 1  goes high and the signal C 1  is applied to a fourth node P 4   i . Consequently, a desired voltage generated at the fourth node P 4 i is supplied to the level shifter  13   i . After supplying the desired voltage to the level shifter  13   i , the first clock signal C 1  is inverted into a logic low level. Thus, the first and second NMOS transistors T 1  and T 2  and the third and fourth NMOS transistors T 3  and T 4  act as controllers for controlling an output part of the shift register that includes the fifth and sixth NMOS transistors T 5  and T 6 .  
         [0042]    Meanwhile, the desired voltage supplied to the fourth node P 4   i  is applied to a fifth node P 5 , and the eighth NMOS transistor T 8  is caused to turn on. When the eighth NMOS transistor T 8  is turned on, a high voltage V high  is applied to the second capacitor CP 2 . The second capacitor CP 2  charges the high voltage V high  and discharges the charged voltage.  
         [0043]    A voltage discharged from the second capacitor CP 2  turns on the ninth NMOS transistor T 9 . When the ninth NMOS transistor T 9  is turned on, a high voltage V high  is applied to the output line  14   i . In other words, a desired output voltage emerges at the output line  14   i . When the second capacitor CP 2  is completely discharged, the ninth NMOS transistor T 9  turns off.  
         [0044]    Thereafter, the second clock signal C 2  is applied to the gate terminal of the seventh NMOS transistor T 7  to turn on the seventh and tenth NMOS transistors T 7  and T 10 . When the tenth NMOS transistor T 10  turns on, the output line  14   i  is connected to the ground voltage VSS. Thus, the ninth and tenth NMOS transistors T 9  and T 10  act as output circuitry that applies either the ground voltage VSS or the high voltage V high  to the output line  14   i .  
         [0045]    On the other hand, when the seventh NMOS transistor T 7  is turned on, the output line  14   i  is connected to the fifth node P 5  at which no voltage is applied. Consequently, the second capacitor CP 2  maintains a low voltage and the ninth NMOS transistor T 9  turns off. Thus, the seventh and eighth NMOS transistors T 7  and T 8  act as control circuitry controlling the output circuitry.  
         [0046]    In the first exemplary embodiment, the clock signals C 1  to C 4  have a swing width of about 0 to 10V. In this case, the high voltage V high  is set to have a value of about 15 to 25V. In other words, in the first embodiment, a low voltage of less than 10V can be applied to the stages  12   1  to  12   n .  
         [0047]    Alternatively, the transistors in the first embodiment may be replaced by other switching element types that include an input terminal, an output terminal, and a control terminal, such as a PMOS transistor. In the case of a PMOS transistor, clock signals C 1  to C 4  may have a swing width of about 0 to 10V. For example, the high voltage V high  may be set to about −8V while the ground voltage VSS is set to about 10V.  
         [0048]    [0048]FIG. 7 is a detailed circuit diagram of a stage and a level shifter according to a second embodiment of the present invention. In FIG. 7, the i-th stage  12   i  includes second and fourth NMOS transistors T 2  and T 4  connected to a ground voltage VSS, a third NMOS transistor T 3  connected to a supply voltage VCC, fifth and sixth NMOS transistors T 5  and T 6  connected to the level shifter  13   i , and a first NMOS transistor T 1  supplied with an output signal g i−1  of the previous stage.  
         [0049]    The output signal g i−1  of the previous stage is applied to gate terminals of the first and fourth NMOS transistors T 1  and T 4 . Drain terminals of the second NMOS transistor T 2 , the fourth NMOS transistor T 4  and the sixth NMOS transistor T 6  are connected to a ground voltage VSS. Gate terminals of the second and sixth NMOS transistors T 2  and T 6  are connected to a source terminal of the fourth NMOS transistor T 4  and a drain terminal of the third NMOS transistor T 3 . A first capacitor CP 1  is provided between the gate terminal of the fifth NMOS transistor T 5  and the ground voltage VSS.  
         [0050]    The i-th level shifter  13   i  includes seventh and eighth NMOS transistors T 7  and T 8  connected to the output of the i-th stage  12   i , and ninth and tenth NMOS transistors T 9  and T 10  connected to the output line  14   i .  
         [0051]    A second clock signal C 2  is inputted to gate terminals of the seventh and tenth NMOS transistors T 7  and T 10 . The gate terminal of the eighth NMOS transistor T 8  and the source terminal of the seventh NMOS transistor T 7  are connected to the output of the stage  12   i . A high voltage V high  is applied to the source terminals of the eighth and ninth NMOS transistors T 8  and T 9 . The source terminal of the tenth NMOS transistor T 10  and the drain terminal of the ninth NMOS terminal are connected to the output line  14   i . The drain terminal of the tenth NMOS transistor T 10  is connected to the ground voltage VSS. A second capacitor CP 2  is connected between the output line  14   i  and the drain terminal of the seventh NMOS transistor T 7 .  
         [0052]    In operation, the third clock signal C 3  is first applied to the gate terminal of the third NMOS transistor T 3 . If the third clock signal C 3  is high, then the third NMOS transistor T 3  is turned on. When the third NMOS transistor T 3  turns on, a supply voltage VCC is applied to a second node P 2  to turn on the second and sixth NMOS transistors T 2  and T 6 . At this time, a first node P 1  and the output line  14   i  are initialized at the ground voltage VSS.  
         [0053]    Subsequently, the output signal g i−1  of the previous stage is applied as a start pulse. If the output signal g i−1  present at the previous stage is high, then the first and fourth NMOS transistors T 1  and T 4  are turned on. When the fourth NMOS transistors T 4  is turned on, a second node P 2  is connected to the ground voltage VSS and turns off the second and sixth NMOS transistors T 2  and T 6 .  
         [0054]    On the other hand, when the first NMOS transistor T 1  is turned on, the output signal g i−1  present at the previous stage is applied to the first node P 1 . A voltage corresponding to the output signal g i−1  at the previous stage that is applied to the first node P 1  also is applied to the third node P 3 . Accordingly, the corresponding voltage is charged in the first capacitor CP 1  connected to the third node P 3 , and the fifth NMOS transistor T 5  turns on by the voltage charged in the first capacitor CP 1 .  
         [0055]    After the fifth NMOS transistor T 5  turns on, the first clock signal C 1  goes high and is applied to a fourth node P 4   i . Consequently, a desired voltage is generated at the fourth node P 4   i  and is supplied to the level shifter  13   i . After supplying the desired voltage to the level shifter  13   i , the first clock signal C 1  is inverted into a logic low level. Similar to the first exemplary embodiment, the first and second NMOS transistors T 1  and T 2  and the third and fourth NMOS transistors T 3  and T 4  act as controllers for controlling an output part of the shift register that includes the fifth and sixth NMOS transistors T 5  and T 6 .  
         [0056]    Meanwhile, the desired voltage generated at the fourth node P 4   i  is applied to a fifth node P 5 , and the eighth NMOS transistor T 8  turns on. When the eighth NMOS transistor T 8  turns on, a high voltage V high  is applied to the second capacitor CP 2 . The second capacitor CP 2  charges the high voltage V high  and discharges the charged voltage.  
         [0057]    A voltage discharged from the second capacitor CP 2  turns on the ninth NMOS transistor T 9 . When the ninth NMOS transistor T 9  is turned on, a high voltage V high  is applied to the output line  14   i . In other words, in response to a voltage signal corresponding to clock signal C 1 , a desired output voltage corresponding to the high voltage V high  emerges at the output line  14   i . When the second capacitor CP 2  is completely discharged, the ninth NMOS transistor T 9  turns off.  
         [0058]    Thereafter, the second clock signal C 2  is applied to the gate terminals of the seventh and tenth NMOS transistors T 7  and T 10  to turns on the seventh and tenth NMOS transistors T 7  and T 10 . When the tenth NMOS transistor T 10  turns on, the output line l 4   i  is connected to the ground voltage VSS. Thus, the ninth and tenth NMOS transistors T 9  and T 10  act as output circuitry that applies either the ground voltage VSS or the high voltage V high  to the output line  14   i .  
         [0059]    On the other hand, when the seventh NMOS transistor T 7  is turned on, the output line  14   i  is connected to the fifth node P 5  at which no voltage is applied. Consequently, the second capacitor CP 2  maintains a low voltage and the ninth NMOS transistor T 9  turns off. Thus, the seventh and eighth NMOS transistors T 7  and T 8  act as control circuitry controlling the output circuitry.  
         [0060]    Meanwhile, the second capacitor CP 2  is connected to the fifth node P 5  rather than to the ground voltage VSS. Accordingly, the gate (control) terminal of the ninth NMOS transistor T 9  (i.e., the second capacitor CP 2 ) goes into a floated state. This state may output an undesired voltage to the output line  14   i .  
         [0061]    In order to prevent this phenomenon, the shift register of the second exemplary embodiment further includes stabilization circuitry to connect the second capacitor to the low-level voltage. As shown in FIG. 7, the source and drain of an eleventh NMOS transistor T 11  may be provided across capacitor CP 2 , and its gate terminal connected to the gate terminal of transistor T 6 . In addition, the source and the drain of a twelfth NMOS transistor T 12  may be connected between node  14   i  and the ground voltage VSS, and its gate terminal connected to the gate terminal of the eleventh NMOS transistor T 11 .  
         [0062]    The eleventh and twelfth transistors T 11  and T 12  turn on in response to receiving a voltage from the second node P 2 . When the eleventh NMOS transistor T 11  turns on, the second capacitor CP 2  is connected to the output line  14   i . When the twelfth NMOS transistor T 12  turns on, the output line  14   i  is connected to the ground voltage VSS. In other words, the second capacitor CP 2  is initialized at the ground voltage.  
         [0063]    In the second embodiment, the clock signals C 1  to C 4  have a swing width of about 0 to 10V. In this case, the high voltage V high  is set to have a value of about 15 to 25V. In other words, in the second embodiment, a low clock voltage of less than 10V can be applied to the stages  12   1  to  12   n .  
         [0064]    Alternatively, the transistors in the first embodiment may be replaced by other switching element types that include an input terminal, an output terminal, and a control terminal, such as a PMOS transistor. In the case of a PMOS transistor, then the clock signals C 1  to C 4  have a swing width of about 0 to about 10V. In this case, the high voltage V high  is set to about −8V and the ground voltage VSS is set to about 10V.  
         [0065]    As can be seen from FIGS. 8A and 8B, a maximum voltage of an output signal OUT 1  is higher than that of the second capacitor CP 2 . This is a result of a bootstrap phenomenon occurring due to an internal capacitor of the ninth transistor T 9  and the second capacitor CP 2 .  
         [0066]    As described above, according to the present invention, level shifters are included in the shift register circuit, thereby reducing swing widths of the clock signals applied to the shift register circuit. Accordingly, erroneous operation of the single IC chip that creates the clock signals is substantially prevented.  
         [0067]    Although the present invention has been explained by the embodiments shown in the drawings described above, it should be understood to the ordinary skilled person in the art that the invention is not limited to the embodiments, but rather that various changes or modifications thereof are possible without departing from the spirit of the invention. Accordingly, the scope of the invention shall be determined only by the appended claims and their equivalents.