Abstract:
An integrated-circuit including two NMOS depletion mode transistors having parameters selected so that when the transistors are connected in accordance with the invention (see FIG. 1), the circuit in response to a variable input DC voltage produces a stable DC output voltage.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to integratedcircuits which in response to a variable DC input voltage produce a stable output DC voltage. 
     2. Description of the Prior Art 
     There are a variety of applications where stable DC reference voltages are needed. For example, charge-coupled (CCD) devices often require five or six stable DC voltages. In CCD devices, these voltages operate gate electrodes and a reset gate which resets the floating diffusion of an output diode. Often these voltages are provided by off-chip circuitry. For purpose of this disclosure, when an electrical circuit is fabricated on or within a substrate, it will be referred to as an integrated-circuit. A chip includes a substrate and all the electrical circuits fabricated on it. Off-chip circuits generally add to the overall system cost and complexity while reducing system reliability. There are a number of advantages for providing an integrated-circuit for producing a stable DC voltage. Unfortunately, such circuits can include a number of active elements and consume a relatively large amount of chip area. 
     The object of this invention is to provide an integrated-circuit for producing a stable DC voltage and which can be used on-chip and which uses very little chip area and consumes a relatively small amount of power. 
     SUMMARY OF THE INVENTION 
     This object is achieved by an integrated-circuit which in response to a variable DC input voltage produces a stable DC voltage. The circuit includes first and second NMOS depletion mode transistors. Each transistor has gate drain and source electrodes. These electrodes are electrically connected as follows: the source and drain electrodes of the first and second transistors respectively, are connected. The first transistor&#39;s gate electrode and the second transistor&#39;s source and gate electrodes are connected to a reference potential. The drain electrode of the first transistor is connected to the variable input voltage. A stable DC output voltage is produced at the electrical junction of the connected source and drain electrodes. 
     Among the features of this integrated-circuit are that it has low power dissipation, requires very little surface area and is quite versatile. 
     This circuit reduces needed external components and also increases reliability, noise immunity and simplicity of overall system design. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of an on-chip integrated-circuit having two NMOS depletion mode transistors connected in accordance with the present invention; and 
     FIG. 2 is a perspective, not to scale, of a NMOS depletion mode transistor which can be used in the integrated-circuit shown in FIG. 1. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     As shown in FIG. 1, an integrated-circuit 10 is provided on a silicon chip 12. The chip 12 includes other active elements which may comprise, for example, a CCD image sensor (not shown). Two pins 14 and 16 provide a connection to an external power supply shown as V IN . It should be noted that pin 16 is at a reference potential (ground). The circuit 10 includes only two active elements; NMOS depletion mode transistors Q 1  and Q 2 . Each of these transistors includes a gate (G), a source (S) and a drain (D) electrode. The silicon substrate bulk electrode (B) under each of these transistors is connected to ground. 
     The source electrode S 1  of transistor Q 1  is connected to the drain D 2  of transistor Q 2  The gate electrodes G 1  and G 2  and the source electrode S 2  are also connected to ground. V IN  (relative to ground) is applied to electrode D 1 . The output voltage V OUT  is produced at the electrical junction of the source electrode S 1  and the drain electrode D 2 . 
     Turning now to FIG. 2, an NMOS depletion mode transistor which can be used as Q 1  or Q 2  in circuit 10 of FIG. 1, is shown to be constructed on a silicon semi-conductor substrate 34 of the chip 12. A silicon dioxide (SiO 2 ) insulating layer 36 overlies the substrate 34. Silicon dioxide has the property of preventing the diffusion of impurities through it and is an excellent insulator. Aluminum conductive electrodes provide the gate (G), drain (D) and source (S) electrodes and are deposited on top of the layer 36 as shown. Masking and etching processes are used to remove the undesired aluminum in the process of forming these electrodes. A polysilicon conductive layer can also be used for the gate electrode (G). 
     The bulk of the substrate 34 has been doped to be a p-type substrate. A suitable p-type dopant is boron. An n-type layer 34a has been diffused into the bulk substrate to define an actual channel. Suitable n-type materials are arsenic and phosphorus. The length of the diffusion layer 34a or channel is L and the width of the diffusion layer 34a or channel is W. The channel width is perpendicular to the channel length L. As will be discussed later, the parameters W and L of each transistor are important in providing the output voltage. 
     The threshold voltage V T  is that minimum voltage applied to the gate electrode which causes the transistor drain current to flow. Depletion mode transistors are fabricated with a net negative threshhold voltage. This V T  voltage can be easily adjusted during the manufacturing process by ion-implementation to alter the doping levels. 
     For the two transistors, there are three parameters that can be selected in accordance with the invention; V T , W and L, to obtain a desired V OUT . The threshhold voltages of the transistors Q 1  and Q 2 , after being selected by a designer, usually should not need to be changed. This is because the W/L ratios are more easily adjusted to change the desired value of the output voltage (V OUT ). 
     One of the requirements of the circuit shown in FIG. 1 is that V OUT  be less than -V T1 . This requirement is met by making the transistors Q 1  and Q 2  NMOS depletion mode transistors. 
     We will now show analytically why the only parameters that need to be selected are W, L and V T  for each transistor to adjust the output voltage V OUT . To produce a stable DC voltage, the circuit 10 must operate as follows. Q 1  must always be saturated but Q 2  can either operate in a saturated or a linear mode. First, let&#39;s assume both transistors are operating in saturated modes. In such a situation V OUT  &gt;V T2  and V IN  ≧-V T1 . Q 2  forms a constant-current source and the same current flowing through Q 1  must also flow through Q 2 . As a first order of approximation, we will assume that the current I DS2  flowing through Q 2  is given by the following well known relationship for a field effect transistor operating in saturation. ##EQU1## where K 1  is a constant which depends upon doping and oxide thickness, 
     L 2  and W 2  are as shown in FIG. 2. Since V GS2  =0 ##EQU2## As mentioned previously, I DS1  =I DS2 . Also by inspection of FIG. 1, V GS1  =-V OUT . I DS1  is given by eqn. (1) with the subscripts changed. It follows that: ##EQU3## It is thus seen from eqn. (4), the only parameters that need be adjusted are V T , L and W for each transistor. 
     In a similar fashion, if V OUT  &lt;-V T2 , then the transistor Q 2  operates in the linear region. The current flowing through transistor Q 2  is given by the following well-known relationship: ##EQU4## It can now be shown since I DS1  =I DS2  that ##EQU5## where K2/K1=W 2  L 1  /L 2  W 1 . 
     Although eqns. (4) and (6) are based on a simple square-low model for the NMOS transistors, they allow a qualitative understanding of circuit 10. Thus, it is clear that the output voltage is determined solely by the width-to-length ratios and the threshhold voltages of the transistors Q 1  and Q 2 . By using circuit 10, there is a minimum amount of power dissipation and a very small chip area need be used since only two transistors are needed. The circuit 10 is especially suitable for use on-chip with a burried channel CCD imager. 
     A circuit was constructed where Q 1  and Q 2  were depletion transistors with W/L ratio parameters of 40 μm/20 μm and 10.5 μm/30 μm, respectively. The measured voltage threshhold parameters for these transistors were: V T1  =-12.2 V, and V T2  =-4.74 V. The input voltage used was a variable 15 V DC. Using eqn. (4), since both Q 1  and Q 2  are in saturation, the calculated value for V OUT  is 10.22 V whereas the measured value was a stable 10.38 V. 
     The invention has been described in detail with particular reference to a certain preferred embodiment thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention.