Abstract:
The present invention enables a pin on an integrated circuit to provide multiple duties. The internal circuit coupled to the selected pin is placed into a high impedance or sampling state based on a recurring signal so that the terminal pin can be sampled. The sampled signal is used to control the operation of the circuit, such as turning off the internal clock to place the circuit in shutdown mode. In that specific example, the integrated circuit exits shutdown mode when the sampled signal changes.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to implementing control features on an integrated circuit (IC). In particular, this invention relates to implementing a control feature on an IC without adding a dedicated pin to implement that feature. 
     The invention is described below as it applies to a charge pump circuit; however, persons skilled in the art will appreciate that the principles of the present invention can be applied to other integrated circuits as well. By enabling additional control features to be added to an IC without adding extra pins, the invention preserves valuable space on the circuit board. 
     Direct current to direct current (DC—DC) conversion circuits can be implemented using an inductor based topology or a capacitor based topology (e.g., a charge pump). Each type of converter topology has its own advantages and disadvantages. The inductor based topology requires fewer power switches and can be implemented in fewer pins than the capacitor based topology. For example, a conversion circuit that boosts voltage four times (a quadruplet) can be implemented with an inductor based topology using three pins, while a capacitor based topology requires a minimum of eight pins. 
     The inductor based topology, however, also has several disadvantages. These circuits are more complex to design than capacitor based topologies because they require numerous external components in addition to many internal IC controls. Moreover, they require magnetic energy storage, which often is difficult to stabilize and radiates EMI waves. 
     Capacitor based topology requires a minimum of eight power switches and eight pins to operate. Adding a control feature will normally increase the pin count to at least nine pins. To avoid increasing pin count and consuming additional space on the circuit board, the present invention enables the designer to add a control feature to the IC without requiring additional pins be added to the IC. 
     SUMMARY OF THE INVENTION 
     Accordingly, one of the objects of the invention is to enable additional control features to be added to an IC without adding additional dedicated pins. 
     The present invention provides an additional control feature to the IC by assigning multiple duties to one of the pins. In a preferred embodiment, a shutdown control feature is added to a quadrupler charge pump IC. Persons skilled in the art, however, will appreciate that the present invention can be utilized in various circuits, such as, for example, a doubler, a sextupler, an octupler, etc. charge pump IC or in any other IC where it is desirable to preserve a low pin count. 
     In accordance with the invention, a charge pump circuit that normally has two terminal pins attached thereto is provided with an operating and a sampling state. A timing circuit is used to provide a recurring signal, such as once every sixteen clock cycles, that places the charge pump into the sampling state for the duration of the recurring signal (normally one clock pulse). A sampler circuit then samples one of the doubler circuit&#39;s pins while the doubler circuit is in the sampling state. The control feature (e.g., shutdown) is implemented based on the sampled signal. For instance, the internal circuit clock can be disabled when there is an external pull-down signal on the sampled pin so that the IC is effectively shut down. The control feature also could be implemented with a external pull-up signal or any number of known control signals. Thus, a shutdown control feature is added to a charge pump IC without adding an additional dedicated pin. The sampled signal could be used to implement any number of different control features, such as modifying the regulator voltage, modifying the internal clock frequency or enabling an auxiliary function of the IC. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects and advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference numerals refer to like parts throughout. 
     FIG. 1 is a block diagram of a quadrupler charge pump according to the present invention. 
     FIG. 2 is a circuit diagram of doubler circuits used to implement the charge pump circuit of FIG.  1 . 
     FIGS. 3A and 3B are circuit diagrams of the series of logic gates in the charge pump circuits of FIG. 1 used to generate control signals for each doubler circuit of FIG.  2 . 
     FIGS. 4A-C are circuit diagrams of the sampling circuit of FIG. 1 and a block diagram of the timing circuit of FIG. 1 according to the invention. 
     FIG. 5 is a diagram of a circuit that provides an external pull-down signal to the circuit of FIG.  1 . 
     FIG. 6 is a block diagram of a clock generation circuit that can be used to provide clock signals to the circuits of FIGS. 3A,  3 B and  4 A. 
     FIG. 7 is a block diagram of a flip-flop circuit used to generate the recurring signals (R and RB) of FIGS.  1 - 6 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows a capacitor based quadrupler charge pump circuit  10  having terminal pins  1 - 8  coupled to input voltage V in , output voltage V out , external capacitors C 1 , C 2 , C 3 , C in  and C out , and ground GND. 
     Quadrupler charge pump IC  10  comprises first charge pump circuit  20 , second charge pump circuit  30 , comparator circuit  40 , timing circuit  50 , sample circuit  70 , and bias control circuit  80 . One of skill in the art would appreciate that the low voltage start-up feature described in U.S. Patent Application 09/240,102; entitled “IC With Enhanced Low Voltage Start Up”, filed concurrently with the present application, can be added to this circuit; that application is herein incorporated by reference in its entirety. 
     Voltage V in  is input to first charge pump circuit  20 , which outputs a voltage approximately two times V in  and stores that voltage on capacitor C 2  as voltage V C2 . Voltage V C2  is then input to second charge pump circuit  30  which outputs a voltage approximately two times voltage V C2  as voltage V out . Thus, output voltage V out  is approximately four times input voltage V in . 
     Compartor  40  regulates output voltage V out  by comparing it to reference voltage V ref . Comparator  40 , shown in FIG. 1, disables timing circuit  50  via signal S 2  when the divided down voltage V out  is larger than reference voltage V ref . Timing circuit  50  is disabled by turning the oscillator circuit, shown in FIG. 6, OFF when the output voltage is too high e.g., above the regulated range. Thus, output voltage V out  is maintained within a predetermined range during operation of circuit  10 . 
     Divider resisters R 1 , R 2  are coupled to comparator  40  and V out  and are chosen based on the voltage to which the circuit designer wants V out  to be regulated. The values of resistors R 1  and R 2  also depend on the value chosen for reference voltage V ref . For example if V ref =1.2 volts and the desired V out =3.3 volts, then the ratio of divider resistors R 1 :R 2  should be 1.75:1. Any combination of resistors in that ratio will work, such as R 1 =2.1 Megohms and R 2 =1.2 Megohms. 
     Sample circuit  70 , samples terminal pin  2  based on recurring signals R and RB generated in timing circuit  50 . Sample circuit  70  then enables the control feature based on the signal input to terminal pin  2  during the sample interval. Timing circuit  50  also generates clock signals CLK 1  and CLK 2 . These two circuits and their operation will be described below in more detail. 
     First and second charge pump circuits  20  and  30  operate as follows. 
     First charge pump circuit  20  is coupled to internal bias voltage V ib , signal RB, two non-overlapping clock signals (signal CLK 1  and signal CLK 2 ), input voltage V in  and external capacitor C 1 . Internal bias voltage V ib  is generated in bias control circuit  80 . Bias control circuit  80  selects the highest voltage from input voltage V in , output voltage V out  and voltage V C2  to operate as V ib . Clock signals CLK 1  and CLK 2  and signal RB are generated in timing circuit  50 . These signals are used to control the first and second doublers, shown in FIG. 2 via the logic gates in FIGS. 3A and 3B, respectively. External capacitor C 1  is coupled to first charge pump circuit  20  via terminal pins  2  and  3 . 
     Clock signals CLK 1  and CLK 2  control the transfer of charges to the capacitors by turning the power switches in the doubler circuits, shown in FIG. 2, ON and OFF at the appropriate time to effectively double the voltage input to each doubler. Input voltage V in  is stored on capacitor C 1  as voltage V C1  when signal CLK 1  pulses HIGH and signal RB is HIGH. Then, voltage V C1  is summed with input voltage V in  when signal CLK 2  pulses HIGH and signal RB is HIGH. Thus, the voltage output from first charge pump circuit  20  is approximately two times the voltage input. The doubled voltage is stored on capacitor C 2  as voltage V C2  and then input to second charge pump circuit  30 . Second charge pump circuit  30  works in essentially the same manner as first charge pump circuit  20 , except capacitor C 3  is used to store the interim voltage that is summed with voltage V C2  during the second clock signal CLK 2 . 
     A circuit diagram of first and second charge pump circuits  20  and  30  are shown in FIGS. 2,  3 A and  3 B. First charge pump circuit  20  includes first doubler circuit  22 , shown in FIG. 2, and logic gates  201 - 218 , shown in FIG.  3 A. Second charge pump circuit  30  includes second doubler circuit  32 , shown in FIG. 2, and logic gates  301 - 317 , shown in FIG.  3 B. 
     As shown in FIG. 2, first doubler circuit  22  includes transistors N 1 , N 2 , N 3 , N 4 , P 3 , P 4  and bias control circuit  25 . Bias control circuit  25 , which consists of transistors P 5 , P 6  and Shottky diodes D 1 , D 2 , operates as a bias control for transistor P 4 . Signal A is coupled to transistors P 3  and P 4 , signal B is coupled to transistors N 3  and N 4 , and signal C is coupled to transistors N 1  and N 2 . Throughout this application, transistors designated with a “N” prefix are preferably implemented as n-channel transistors, while those designated with a “P” prefix are preferably p-channel transistors. 
     Second doubler circuit  32  includes transistors N 5 , N 6 , N 7 , P 7 , P 8  and bias control circuit  35 . Bias control  35 , which consists of Shottky diodes D 3 , D 4  and transistors P 9 , P 10 , provides bias control to transistor P 8 . Signal D is coupled to transistors P 7  and P 8 , signal E is coupled to transistor N 7 , and signal F is coupled to transistor N 5  and N 6 . 
     The transistors in both doublers are preferably MOSFETs that operate as power switches. The particular details of the transistors, such as size and type are an engineering design choice. The transistors in the first and second doublers of FIG. 2 are controlled by signals A, B and C and signals D, E, and F supplied by the logic gates shown in FIGS. 3A and 3B, respectively. 
     As illustrated in FIG. 2, signal C turns transistors N 1  and N 2  ON when it is HIGH. Signal A turns transistors P 3  and P 4  ON when it is LOW and signal B turns transistors N 3  and N 4  ON when it is HIGH. Signal F turns transistors N 5  and N 6  ON when it is HIGH. Signal E turns transistor N 7  ON when it is HIGH and signal D turns transistors P 7  and P 8  ON when it is LOW. The generation of these control signals A-F are described in more detail below. 
     As shown in FIG. 3A, control signals A, B, and C are generated from a series of logic gates  201 - 218  based on clock signals CLK 1  and CLK 2  and recurring signal RB, which operates as an override signal. Signals A, B, and C are used to turn ON and OFF the power switches in first doubler circuit  22 , as described above. When signal RB is LOW it acts as an override signal to turn transistors N 1 -N 4 , P 3 -P 4  OFF at the same time and, thus, place first doubler circuit  22  (and first charge pump circuit  20 ) in a high impedance state for sampling. 
     When signal RB is HIGH, signal CLK 1  generates control signal C through invertor chains  202 - 206  and CLK 2  generates signal B and A through invertor chains  212 - 216  and  212 - 213 ,  217 - 218 , respectively. NAND gates  201 ,  211  help provide the correct polarity for the control signals and enable signal RB or CLK 1 /CLK 2  to control the polarity of control signals A, B, and C. Thus, signal C is HIGH when CLK 1  is HIGH, signal B is HIGH when CLK 2  is HIGH and signal A is LOW when signal CLK 2  is HIGH. 
     The polarity of control signals A, B, and C alternate because clock signals CLK 1 , CLK 2  are non-overlapping, which enables first doubler circuit  22  to function properly without generating high throughput currents. This sequence causes V in  to be stored on capacitor C 1  during CLK 1  and then V in  to be combined with voltage V C1  during CLK 2  to effectively double the voltage. 
     The power switches in second doubler circuit  32  of FIG. 2 are controlled by the signals output from the logic gates shown in FIG. 3B, which work in a similar fashion to those described above for FIG. 3A, except that no override signal (RB) is provided to second charge pump circuit  30  in the described embodiment. 
     Control signals D, E, and F are generated by the series of logic gates shown in FIG. 3B from clock signals CLK 1  and CLK 2 . Transistor N 5  and N 6  are turned ON by control signal F when signal CLK 1  pulses HIGH, so that voltage V C2  is stored on capacitor C 3  as voltage V c3 . Transistor N 7  is turned ON by signal E and transistors P 7  and P 8  are turned ON by signal D when CLK 2  pulses HIGH, so that voltage V C2  is summed with voltage V C3 . Thus, voltage V out  is approximately four times voltage V in . 
     As shown in FIG. 3B, invertor chains  301 - 306 ,  311 - 315 , and  311 - 314 ,  317 - 318  work in the essentially the same fashion as described above with respect to the logic gates of FIG. 3A, except that no override signal RB is provided. Instead, the NAND gates from FIG. 3A are replaced with invertors ( 301 ,  311 ) to ensure that the correct polarities of signals D, E, and F are maintained. NAND gates are not required because there is no override signal for second charge pump circuit  30 . 
     If the low voltage start-up feature described in U.S. Patent Application 09/240,102 (incorporated by reference above) is added to circuit  10 , then invertors  301  and  311  are preferable replaced by NAND gates. 
     The invertors, shown in FIGS. 3A and 3B, may be progressively larger as the signal passes through each gate to provide better drive capability for the MOSFET transistors of the first and second doubler circuits shown in FIG.  2 . The length of the invertor chains is a design choice as long as the polarity of the control signals is correct. Thus, the exact number and size of the invertors depends on various factors, such as die area and switching speed. 
     Sample circuit  70  and its connections to timing circuit  50  are shown in FIGS. 4A to  4 C. As shown in FIG. 4A, timing circuit  50  supplies recurring signal R to sample circuit  70  and sample circuit  70  provides signal S 1  to timing circuit  50 . When signal R is HIGH, it triggers sample circuit  70  so that the signal on pin  2  is sampled and signal S 1  is output based on signal D which is determined by the sampled signal. When signal S 1  is forced LOW, it disables clock generator circuit  54  and thus timing circuit  50  via signal SO. When signal R is LOW, the output of NAND gate  72  (signal S 1 ) is always HIGH, so timing circuit  50  is not disabled by that signal. 
     Sample circuit  70  comprises NAND gate  75 , resistor R p , transistors Q 1  (n-channel) and P 1 , One-Shot A (FIG. 4B) and One-Shot B (FIG.  4 C). One-Shot A is coupled in parallel to resistor R p  to provide boost current to the pull-up current generated across resistor R p . One-Shot B is coupled in parallel to transistor P 1  to provide a boost to the pull-up current generated at node D. 
     As shown in FIG. 4B, One-Shot A comprises transistors N 12 , N 13  and P 12 , resistor R A , capacitor C A , and logic gates  71 - 72 . As shown in FIG. 4C, One-Shot B comprises transistors N 14 , P 13  and P 14 , resistors R B  and R D , capacitor C B , and NAND gate  78 . 
     As discussed above, signal RB forces first charge pump circuit  20  into a high impedance state when signal RB is LOW to allow the voltage on pin  2  to be sampled by sample circuit  70 . If there is no external pull-down present on pin  2  during the sampling interval, then One-Shot A pulls pin  2  to V in  via R p . Thus, transistor Q 1  remains ON and signal D remains LOW, so that the output of NAND gate  75  (signal S 1 ) is HIGH and clock generator circuit  54  in timing circuit  50  stays enabled. One-Shot B is activated after One-Shot A via signal B, which is output from NAND gate  71 , shown in FIG.  4 B. One-Shot B tries to force transistor Q 1  into its OFF state, but transistor Q 1  overpowers One-Shot B when there is no external pull-down present and thus stays ON so that signal S 1  remains HIGH. 
     If there is an external pull-down present on pin  2  when it is sampled, then One-Shot A cannot pull pin  2  high because the external pull-down overpowers One-Shot A and keeps pin  2  LOW (i.e., pulled to ground). Therefore, transistor Q 1  will be turned OFF. After One-Shot B is activated by signal B, it drives transistor P 1  which forces signal D HIGH since transistor Q 1  is turned OFF. Since signal D is HIGH and signal R is HIGH, signal S 1  from NAND gate  75  is LOW and clock generator circuit  54  in timing circuit  50  is disabled. 
     When clock generator circuit  54  in timing circuit  50  is disabled, signals CLK 1  and CLK 2  are not generated and the first and second charge pumps are functionally shut down. Timing circuit  50  stays disabled until the external pull-down is removed from pin  2 . When the external pull-down is removed, resistor R p  provides a weak pull-up current which turns transistor Q 1  back ON. The pull-up current provided across resistor R p  cannot turn transistor Q 1  ON when the external pull-down is present because resistor R E  used in the external pull-down circuit, shown in FIG. 5, is much smaller than resistor R p . Therefore, any current generated across resistor R p  flows to ground via the external pull-down circuit when it is activated. 
     When signal R is HIGH, One-shot A, shown in FIG. 4B, provides additional current boost to the pull-up current across resistor R p , since the current generated by resistor R p  is too weak to slew internal capacitances by itself during the sampling interval. One-Shot A is an n-channel one shot which enables a faster and harder switching than a p-channel one shot, such as One-Shot B. One-Shot B is designed so that it cannot overpower transistor Q 1  during the sampling interval without the help of the external pull-down signal. These one shots are not required to implement the invention because the pull-up currents could be made larger; however, that would increase the quiescent current of the device which is not preferable. 
     As shown in FIG. 4B, signal R activates One-Shot A when it is HIGH. If signal R is HIGH, then transistor P 12  is turned OFF and transistor N 12  is turned ON, so that capacitor C A  discharges through resistor R A  to force the output of NOR gate  71  (signal B) LOW for the duration of the discharge. The duration of the discharge is defined by the ratio of R A  to C A  (e.g., 300 nsec), which can be adjusted as needed. Thus, transistor N 13  is turned ON when signal B is LOW and pin  2  is pulled to V in  to keep transistor Q 1  ON during the sampling period, unless there is an external pull-down present. If there is an external pull-down present, then One-Shot A cannot overcome the external signal and pull pin  2  to V in , so transistor Q 1  is turned OFF, as described above. 
     When signal R is LOW, transistor N 12  is OFF and transistor P 12  is ON, thus the output of NAND gate  71  is forced HIGH and the output of invertor  72  is LOW so that transistor N 13  is OFF and pin  2  is not pulled to V in  via transistor N 13 . During this period of time, pin  2  is used by first charge pump  20  to double V in , as described above. 
     As shown in FIG. 4C, One-Shot B provides additional current boost to the pull-up current at node D when it is activated. One-Shot B is rising-edge triggered and is activated by signal B from One-Shot A. When signal R is HIGH, signal B transitions from LOW to HIGH as capacitor C A  is discharged across resistor R A . One-Shot B is activated based on this transition as signal B becomes HIGH. One-Shot B is designed as a p-channel one shot to attempt to pull voltage D to voltage V ib  when One-Shot B is activated. 
     When signal B is HIGH, transistor N 14  is ON and transistor P 13  is OFF, so that capacitor C B  discharges across resistor R B . The output of NAND gate  78  remains LOW for the duration of this discharge which turns transistor P 14  ON and attempts to pull voltage D to voltage V ib . Resistor R D  is provided to weaken the pull-up current at node D. Signal D will remain LOW as long as transistor Q 1  is ON, since transistor Q 1  can sink all of the current generated by One-Shot B. Of course, if transistor Q 1  is turned OFF, then voltage D is pull-up to voltage V ib  and the circuit operates as described above. 
     One-Shot B is only activated on a rising edge of signal B, so no pull up current is generated across resistor R D  when signal B is LOW or when signal B has been high longer than the time defined by the ratio of capacitor C B  to resistor R B . 
     One goal of using these one shots is to keep the pull-up currents low during sampling so that current is not wasted by being drained to ground across the external pull-down circuit, shown in FIG.  5 . The weak internal pull-up currents combined with the one shot current boosts during critical times enable the circuit to have a low quiescent current while in the shutdown state. 
     As shown in FIG. 5, the external pull-down signal is supplied by MOSFET transistor E 1  (n-channel) and pull-down resistor R E . If transistor E 1  is turned ON by signal T, then resistor R E  causes pin  2  to be pulled LOW (i.e., to ground) across transistor E 1 , which causes signal S 1  to become HIGH and thus disables clock generator circuit  54  so that signals CLK 1  and CLK 2  are not produced. When pin  2  is pulled LOW during the sampling interval, the internal clock of circuit  10  is disabled and circuit  10 , including first charge pump circuit  20  and second charge pump circuit  30  are shut down until the external pull-down is removed. 
     Timing circuit  50 , shown in FIG. 4A, comprises invertors  151 - 156 , NOR gate  160 , capacitor C S , clock generator circuit  54  (shown in FIG. 6) and divider circuit  52  (shown in FIG.  7 ). Logic gates  151 - 156 ,  160  and capacitor C S  serve as a delay circuit and produce signals SO and RESET. Signal RESET clears the counters in divider  52 . Signal SO is delayed by two invertors and C S  (compared to signal RESET) to ensure that the divider  52  is reset before clock generator circuit  54  begins creating pulses. Therefore, all of the pulses are counted by divider circuit  52  and the generation of recurring signals R and RB can be accurately controlled. 
     Timing circuit  50  can be turned OFF (i.e., disabled) by signal S 1  from sample circuit  70  or by signal S 2  from comparator  40 , as described above. NOR gate  160  allows timing circuit  50  to be controlled by either signal S 1  or S 2 . 
     The block diagram in FIG. 6 illustrates one possible configuration of clock generator circuit  54 . In FIG. 6, clock generator circuit  54  is comprised of two phase clock generator circuit  56  and oscillator circuit  9 . Any circuit capable of generating an oscillating wave (signal C) can be used as oscillator circuit  58 . Oscillator circuit  58  also generates clock bar signal CB via invertor  55 . Signals C and CB are used as timing signals for the generation of signals R, RB, as shown in FIG.  7 . Toggle flip-flops  161 - 65 , shown in FIG. 7, cannot tolerate significant non-overlap in signals C and CB or they will generate false pulses and the count provided by the flip-flops will be wrong. 
     Signal C is also input to two phase clock generator circuit  56 , which creates non-overlapping clock signals CLK 1  and CLK 2  from oscillating signal C. Clock signals CLK 1  and CLK 2  must be non-overlapping to avoid the generation of large flow through currents in the doublers. Several ways of creating these two non-overlapping clock signals are known in the art and any of them can be used in the implementation of the invention. 
     As shown in FIG. 7, divider circuit  52  is comprised of four toggle flip-flops  161 - 64  and logic gates  165 - 169 . Four toggle flip-flops  161 - 164  are used to generate recurring signals R and RB once every 16 clock pulses. Each toggle flip-flop acts to cut the frequency of the clock signals in half, thus using four flip-flops causes recurring signals R and RB to be generated once every  16  pulses (2 4 =16). NAND gate  165  provides a low pulse every 16 cycles when its four inputs are all HIGH at the same time. Thus, signal R becomes HIGH and signal RB becomes LOW based on the output of invertors  166 - 169 . 
     Since recurring signal RB places first charge pump circuit  20  into an OFF state when it is LOW, as described above, it is preferably not generated too often. However, pin  2  must be checked with some frequency, so recurring signals R and RB must be generated regularly. Therefore, an engineering compromise is reached and the sampling in charge pump  10  is preferably conducted every 16 cycles. Though recurring signals R and RB could also be generated every 8, 32 or some other number of clock cycles based on design choices. 
     The operation and design of toggle flip-flops are known in the art. Other known methods of dividing a clock signal can be used in the invention to generate a signal periodically. 
     The preferred embodiment is described above with respect to a charge pump circuit; however, the present invention can be used on any circuit with an internal clock to limit the number of pins necessary to implement extra control features in the circuit. Further, the sampled control signal could be implemented as a pull-up or any other designated signal and is not limited to an external pull-down. Persons skilled in the art will appreciate that the present invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims which follow.