Abstract:
An apparatus and a method for analysis of processing of a semiconductor wafer is disclosed which comprises gathering a plurality of items of processing data, applying at least one process model to the at least some of the plurality of items of processing data to derive at least one set of process results, comparing at least some of the derived sets of process results or at least some of the plurality of items of processing data with a process window, and outputting a set of comparison results based on the comparison of the derived sets of process results or the plurality of items of processing data with the process window.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    None 
       BACKGROUND OF THE INVENTION 
       [0002]    Field of the Invention 
         [0003]    This field of the present application relates in general to a method for analysis of processing of a semiconductor wafer and an apparatus for the processing of a semiconductor wafer. 
         [0004]    Brief Description of the Related Art 
         [0005]    It will be appreciated that the term “semiconductor wafer” as used in this disclosure is intended to imply wafers used in the manufacture of all types of semiconductor devices, including, but not limited to, memory devices, ASICS, logic circuits such as controllers or microprocessors, etc., liquid crystal panels, and photovoltaic devices. 
         [0006]    Current trends in the processing of the semiconductor wafers mean that overlay and critical dimension budgets shrink with shrinking ground rules and manufacturing processes are becoming more aggressive. Non-limiting examples of such aggressive manufacturing processes include, but are not limited to, multiple patterning, high aspect ratio etching or deposition of exotic materials on a surface of the semiconductor wafer. The non-uniformity of some manufacturing processes over the semiconductor wafer surface and a plurality of manufacturing process steps may result in non-uniform stress being applied to the semiconductor wafer. When the semiconductor wafer deforms from one manufacturing process step to a subsequent manufacturing process step, e.g. from one lower layer to a subsequent layer on top of the lower layer, patterns in the upper layer may become misaligned to patterns in the lower layer. For the error free functioning of a semiconductor device the relative position of patterns on the different layers to each other is relevant. These relative positional errors are termed “overlay errors”. 
         [0007]    A further issue that arises using the aggressive manufacturing processes are the so-called critical dimensions (CDs). This term is used to indicate the dimensions of critical patterns on the surface of the semiconductor wafer. These features are measured after processing, such as the patterning of the lithographic layer, or etching, etc., in order to verify the quality of the exposure and development process. 
         [0008]    In practice, there are multiple measurement parameters, which need to be considered when deciding whether microelectronic devices manufactured on the semiconductor wafer are likely to perform according to specifications. The use of the overlay measurements and CD measurements is merely used as an illustration. 
         [0009]      FIG. 6A  shows an example of the process window used in the manufacture of microelectronic devices on the semiconductor wafers. The process window is shown as an idealised three-dimensional cube in which all (or a majority of) measurements of the processing data for the semiconductor wafers should fall. It should be noted that in practice the measurements are made only in a selection of different fields or areas of the semiconductor wafer and the conclusion is drawn that the semiconductor wafer as a whole is good if the measurements all (or at least a majority) fall within the volume of the box. Measured processing data falling outside of the process window may lead to the semiconductor wafer being considered to be “defective” and the semiconductor wafer may therefore be rejected by a quality controller. 
         [0010]    In practice, the boundaries of the process window are likely to be more “fuzzy” and not so clear as the theory and practice has been applied to date. This can be illustrated with respect to the simple feature shown in  FIGS. 5A and 5B , which illustrate a non-limiting example of the use of the overlay measurements and critical dimension measurements to determine whether the overlay measurements and the critical dimension measurements are within tolerance limits.  FIGS. 5A and 5B  show the overlap of a contact L 2  with a metallisation line L 1 . It will be seen that, in  FIG. 5A , there is an overlay error of the contact L 2  with respect to the metallisation line L 1  and a CD error of the contact L 2  (i.e. too small). The area of overlap between the contact L 2  and the metallisation line L 1  is therefore too small to give an adequate electrical connection. On the other hand, in  FIG. 5B , the width of the metallisation line L 1  is nominally too wide, i.e. the metallisation line L 1  has a CD error, and the overlay error for the contact L 2  with respect to the metallisation line L 1  is identical with that of  FIG. 5A , as L 2  has in this example no CD error. However, in the example of  FIG. 5B , the area of overlap of the contact L 2  and the metallisation line L 1  is sufficient for a good electrical connection. 
         [0011]      FIG. 5B  illustrates therefore that there would be no need to reject this particular semiconductor wafer as being defective, even if the overlay measurements and the CD measurements indicate that the manufactured microelectronic device formed on the semiconductor layer is (theoretically) likely to fall outside of the process window. It will be noted that, in this particular simplified example, we have considered only two of the plurality of factors, such as other features and/or parameters, that will affect the performance of the manufacture microelectronic device. The idealised cube of  FIG. 6A  is, in other words, more like the polyhedron of  FIG. 6B  in which the various measurements influence each other. It will also be noted that in  FIGS. 6A and 6B  the process window is shown as a three-dimensional feature for illustrative purposes only and that the process window has, in fact, many more dimensions, i.e. n-dimensions, many of which influence each other. 
         [0012]    Gupta et al disclose in the paper “Full chip two-layer DN and overlay process window analysis”, Proc. of SPIE, vol. 9427, 94270H-1 to 94270H-6 an investigation of a two-layer model based analysis of CD and overlay errors. This paper discloses the concept of using measurement data from a first layer to dictate how to process the second layer in order to improve the yield of a semiconductor wafer. 
         [0013]    A method for designing a semiconductor chip is known from U.S. Pat. No. 7,941,780 B2 (IBM), which teaches use of a design automation tool to determine an intersect area (or overlap) between a first projected physical area of a first design shape and a second projected physical area of a second design shape. The &#39;780 patent also teaches modifying the first design shape and the second design shape if the determined intersect area is less than a predetermined value. 
         [0014]    U.S. Pat. No. 6,892,365 B2 (IBM) teaches a method of predicting overlay failure of circuit configurations on adjacent, lithographically produced layers of a semiconductor wafer by providing design configurations for circuit portions to be lithographically produced on one or more adjacent layer of a semiconductor wafer and predicting shape and alignment for each circuit portions on each adjacent layer using one or more predetermined values for process fluctuation or misalignment error. 
         [0015]    These prior art documents all teach the concept of simulating the manufacture of layers on the semiconductor wafer and then making adjustments to the process parameters to try and improve the yield of the semiconductor wafers. 
       SUMMARY OF THE INVENTION 
       [0016]    This disclosure teaches a general method for analysis of processing of a semiconductor wafer which is more wide-ranging than that known in the prior art. The method comprises initially gathering a plurality of items of processing data (not just overlay or CD measurements) and then applying at least one process model to the at least some of the plurality of items of processing data to derive at least one set of process results. The method then compares at least some of the derived sets of process results or at least some of the plurality of items of processing data with a process window and outputs at least one comparison result based on the comparison of the derived sets of process results or the plurality of items of processing data with the process window. 
         [0017]    The items of processing data are selected from the set of processing data which includes, but is not limited to, overlay errors, critical dimensions, levelling measurements, deposition thickness, etching times, etching depths, line edge roughness (LER), line width roughness (LWR), side wall angle, other geometry data of patterns, wafer shape and/or deformation, temperature of hot plates, defect measurements, exposure dose, focus/exposure dose measurement, electrical measurements. 
         [0018]    Based on this comparison result, it is possible to adapt the process window or to amend one or more of the process parameters to improve the yield of the semiconductor wafer. 
         [0019]    The method can be used for the processing of a further layer on a semiconductor wafer after deposition of at least one photoresist layer on a surface of a lower layer and exposing to radiation the at least one photoresist layer. At least part of the exposed photoresist layer can then be processed to leave a pattern. A plurality of items of processing data is measured during this process and at least one process model is applied to the at least some of the plurality of items of processing data to derive a set of process results. At least one of the derived set of process results or at least one of the plurality of items of processing data are compared with a process window. The comparison can indicate whether to accept or rework the further layer. 
         [0020]    The disclosure also teaches an apparatus for the processing of layers on a semiconductor wafer, which comprises measuring equipment for collecting a plurality of items of processing data, a memory store for storing a plurality of models and a process window. The apparatus further includes a processor for processing data to derive a set of process results from the plurality of items of processing data and the stored plurality of process models. The processor is configured/adapted, using a computer program product loaded into a memory, to execute program instructions to compare at least one of the derived set of process results or at least one of the plurality of items of processing data with the stored process window, and output a comparison result based on the comparison of the derived set of process results or at least one of the plurality of items of processing data with the process window. 
         [0021]    The method and apparatus of this disclosure therefore enable n-dimensions of items of processing data to be taken into account when analysing the manufacturing process of the semiconductor wafers. 
         [0022]    It will be appreciated that the semiconductor wafer can be a wafer for microelectronic devices, such as memory devices, logic circuits such as controllers or microprocessors, etc., or ASICS, liquid crystal panels as well as photovoltaic devices. 
         [0023]    Still other aspects, features, and advantages of the present invention are readily apparent from the following detailed description, simply by illustrating a preferable embodiments and implementations. The present invention is also capable of other and different embodiments and its several details can be modified in various obvious respects, all without departing from the spirit and scope of the present invention. Accordingly, the drawings and descriptions are to be regarded as illustrative in nature, and not as restrictive. Additional objects and advantages of the invention will be set forth in part in the description which follows and in part will be obvious from the description, or may be learned by practice of the invention. 
     
    
     
       DESCRIPTION OF THE FIGURES 
         [0024]    For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description and the accompanying drawings, in which: 
           [0025]      FIG. 1  shows a first aspect of the present disclosure. 
           [0026]      FIG. 2  shows wafer with exposure fields. 
           [0027]      FIG. 3  shows a further layer of wafer with exposure fields. 
           [0028]      FIG. 4A  shows a line without CD and contact with an overlay error and CD error. 
           [0029]      FIG. 4B  shows a line with a CD error and contact with both an overlay error but no CD error. 
           [0030]      FIG. 5A  shows an idealised process window. 
           [0031]      FIG. 5B  shows a more realistic implementation of a process window. 
           [0032]      FIG. 6A  shows an example of the process window used in the manufacture of microelectronic devices on the semiconductor wafers. 
           [0033]      FIG. 6B  shows an acceptable range for a process window used in the manufacture of microelectronic devices on the semiconductor wafers. 
           [0034]      FIG. 7  illustrates a method in accordance with the present invention for analysing the processing of a semiconductor wafer using a technique known as self-aligned double patterning (SADP). 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0035]    The invention will now be described on the basis of the drawings. It will be understood that the embodiments and aspects of the invention described herein are only examples and do not limit the protective scope of the claims in any way. The invention is defined by the claims and their equivalents. It will be understood that features of one aspect or embodiment of the invention can be combined with a feature of a different aspect or aspects and/or embodiments of the invention. 
         [0036]      FIG. 1  shows in a schematic view a fabrication unit  1  for patterning a surface of a semiconductor wafer  10  and performing the method for the analysis of the processing of the semiconductor wafer  10 . The fabrication unit  1  forms part of a semiconductor manufacturing system. The fabrication unit  1  comprises an exposure tool  20  for aligning and exposing portions of the surface of the semiconductor wafers  10  to produce exposed semiconductor wafers  11 , an exposure controller  30 , a developing unit  40  for developing the exposed semiconductor wafers  11  to produce developed and exposed semiconductor wafers  12 , and a measurement tool  50  to measure the developed and exposed semiconductor wafers  12 , resulting in measured semiconductor wafers  13 . The fabrication unit  1  also includes a processor  60 , shown here as a stand-alone computer, but which could be running as a software module on a server, in a cloud computer or on a local computer. The processor  60  includes a storage memory  65  for storage of data. Such fabrication units  1  are known in the art. 
         [0037]    A plurality of semiconductor wafers  10  is loaded into the exposure tool  20 . The semiconductor wafers  10  loaded into the exposure tool  20  have been coated in one non-limiting aspect of the method with a photoresist film in a preceding process step. The exposure tool  20  includes a load port  21  for loading the semiconductor wafers  10  and an unload port  29  for unloading exposed ones of the semiconductor wafers  11 . The load port  21  and the unload port  29  could be identical in the exposure tools  20 . Within the exposure tool  20 , the semiconductor wafers  10  are placed on a substrate holder  22 . 
         [0038]    A typical one of the semiconductor wafers  10  comprises a plurality of exposure fields  70  arranged on the semiconductor wafer  10  in a grid-like pattern, as schematically shown in  FIGS. 2 and 3 . The plurality of exposure fields  70  are usually exposed one exposure field  70  after another exposure field  70 . The substrate holder  22  is positioned by actuators (not shown) within the exposure device  20  at least in two dimensions to move the semiconductor wafer  10 . Thus each one of the exposure fields  70  on the semiconductor wafer  10  is positioned in turn using a projection system  25 . The projection system  25  comprises a light source  24  and projection optics  26 , which function with a photo mask  28 . The semiconductor wafer  10  includes, for example, alignment marks that are used by the exposure tool  20  to align the surface of the semiconductor wafer  10  with the light source  24  and the projection optics  26  to ensure that the correct exposure field  70  with the correct settings is illuminated. Items of processing data  23  from the alignment of the semiconductor wafer  10  as well as other processing data are generated by the exposure device  20  and this processing data  23  is transferred to the processor  60 . The exposure device  20  includes a plurality of measurement sensors  27  to measure further items of the processing data, including the measurement data  23  and can be further pre-processed, as described later. 
         [0039]    Each time the semiconductor wafer  10 , the photo mask  28  and the projection system  24 ,  26  have been aligned, the photo mask  28  is illuminated with the light source  24  and the pattern from the photo mask  28  is projected on an individual exposure field  70 . The pattern on the photo mask  28  is used to generate one or more patterns on the surface of the semiconductor wafer  10  as well as the overlay marks  71 . 
         [0040]    The overlay marks  71  are used in a feedback loop to determine overlay correction parameters to be used by the exposure tool  20  to project the photo mask  28  onto the correct portion of the surface of the semiconductor wafer  10  with the correct settings for the exposure field  70  for further semiconductor wafers The overlay correction parameter uses other overlay marks  72  generated in a lower layer during a previous process step by a different exposure pattern in a previous photoresist layer during the exposure of the structure for this previous semiconductor layer (i.e. for a lower semiconductor layer). These lower overlay marks  72  are, for example, hard patterned and are identifiable through later (upper) photoresist layers. These lower overlay marks  72  will be termed “reference marks”. 
         [0041]      FIGS. 2 and 3  show as one aspect of the present disclosure overlay marks  71  and lower or other overlay marks  72  that are used on the exposed and developed semiconductor wafer  12 .  FIG. 2  shows a surface view of four individual overlay marks  71  in each one of the exposure fields  70 . 
         [0042]    The overlay measurements on the exposure fields  70  of the semiconductor wafers  10  are done for several reasons. The first reason is to determine the disposition of the photoresist pattern with respect to the lower layers, e.g. determine whether there is a good value of the overlay or whether the overlay error is large. In case the disposition of the photoresist pattern is so large that, for example, a deposition layer created in the next process step would not match with the layers underneath and would cause a failure of a microelectronic device on the manufactured semiconductor chip, the photoresist film with the photoresist pattern can be removed from the upper surface of the exposed and developed semiconductor wafer  12 . In this case, the semiconductor wafer  10  can be reworked by removal of the photoresist film and coating with a new photoresist film. The new photoresist film can be exposed again in the exposure tool  20  to create a new photoresist pattern. 
         [0043]    The second reason for the overlay measurements is to calculate, if necessary, process correction parameters, which are then used to compensate for process errors (as noted briefly above). A third reason would be to amend the process window for further processing steps for this semiconductor wafer. 
         [0044]    It is shown in  FIGS. 2 and 3  that several overlay marks  71  are created which form a test structure for each exposure field  70  for each single overlay measurement. A common approach is to arrange an overlay mark  71  at each corner of the exposure field  70  and one overlay mark  71  in the middle of each exposure field  70 . Other patterns of the test structure are conceivable. 
         [0045]    It will be appreciated that the measurement of overlay and CD are only non-limiting examples of the analysis of processing data. Other items of measurement data can be obtained from a variety of sources, for example, in the exposure tool  20  and the measurement tool  50 . These items include, but are not limited to, overlay errors, critical dimensions, levelling measurements, deposition thickness, etching times, etching depths, line edge roughness (LER), line width roughness (LWR), side wall angle, other geometry data of patterns, wafer shape and/or deformation, temperature of hot plates, defect measurements, exposure dose, focus/exposure dose measurements, or electrical measurements. 
         [0046]    In an ideal world, a large number of measurements would be made of the processing data. This is, however, time-consuming and, in most cases, not necessary as many values of the items of the processing data remain substantially unchanged over time or there is one or more process models  67  to identify the changes of the processing data over time or over space. An example of the process model is a shift in the overlay of patterns from one layer to another layer. The overlay shifts can be measured at isolated data points and the process models  67  can be used based on measuring the isolated data points to be able to model the overlay error over the whole of the exposed and developed semiconductor wafer  12 . 
         [0047]    Similarly, it is not necessary to measure the processing data for every single one of the semiconductor wafers  10 . Measured items of processing data for a subset of the exposed and developed semiconductor wafers  12  can be used to estimate data using the so-called process models  67  stored in the memory store  65  for other ones of the exposed and developed semiconductor wafers  12  of the lot that has not been selected for the overlay measurement. A subset for a lot of twenty-five exposed and developed semiconductor wafers  12 , for example, could comprise three of the semiconductor wafers  12 . The number of exposed and developed semiconductor wafers  12  picked for measurement in the measurement tool  50  is user configurable and depends on a selection strategy decided by quality control engineers. Obviously, the more samples of the exposed and developed semiconductor wafers  12  that are chosen the more accurate the estimated data will be. If the statistical variations of the semiconductor manufacturing process are relatively low, a smaller number of samples of the exposed and developed semiconductor wafers  12  will suffice to obtain sufficiently accurate estimations by using the process models  67 . If the statistical variations increase, the number of selected ones of the exposed and developed semiconductor wafers  12  should be increased accordingly. 
         [0048]    The method for analysis of processing of the semiconductor wafer  10  is shown in outline in  FIG. 4 . The method starts in step  400 . In a first step  410 , items of processing data  23  are gathered during the processing steps, such as but not limited to, exposure of the photoresist layer on the semiconductor wafer  10  from, for example, the exposure tool  20  and the measurement tool  50 . Further items of the processing data can be obtained from other equipment and tools used during and after the manufacturing process and not illustrated in  FIG. 1 . These items are not just limited to measuring processing data from the lithographic process, but from other processes such as etching, deposition, etc. 
         [0049]    As noted above, this processing data includes, but is not limited to, overlay errors, critical dimensions, levelling measurements, deposition thickness, etching times, etching depths, line edge roughness (LER), line width roughness (LWR), side wall angle, other geometry data of patterns, wafer shape and/or deformation, temperature of hot plates, defect measurements, exposure dose, focus/exposure dose measurements, electrical measurements. Some of the items of processing data are obtained directly, whereas other items of processing data need to be pre-processed or calculated from other items of processing data. For example, the layout displacement is determined by pre-processing measurement of the wafer deformation. The processing data are passed to the processor  60  in step  420  and can be stored in the storage memory  65  in step  430 . 
         [0050]    The storage memory  65  also includes the one or more process models  67 , which can be applied in step  440  to one or more of the items of processing data to derive a set of process results. The process results enable, as explained above, the manufacturing process to be more completely understood by, for example, interpolating the process results from measured items of the processing data. These derived process results are stored in step  450  in the storage memory  65 . 
         [0051]    In step  460 , a comparison is made between some of the derived set of process results and/or some of the plurality of items of process data with the process window for the manufacturing process, as shown in  FIG. 6B . This comparison step  460  will indicate whether the exposure of the photoresist layer on the semiconductor wafer  10  is likely to lead to useable microelectronic devices formed on the semiconductor wafer  10 . The results of the comparison could be that the processed semiconductor wafer  13  is within acceptable process range and, for example, a (non-reversible) etching process can be carried out on the surface of the exposed and developed semiconductor wafer  12  using the pattern mask. Alternatively, the comparison step  460  may indicate that it is likely that any isolation layer or metallisation layer formed using the exposed pattern is likely to be out of specification and therefore it would be advisable to re-work the exposed and developed semiconductor layer  12 . Alternatively, it is possible that no decision can be made at that stage and that further measurements need to be made on one or more of the exposure fields  70  of the exposed and developed semiconductor wafer  12 . 
         [0052]    The comparison in step  460  is a multi-dimensional comparison and can be understood with reference to  FIGS. 5A, 5B, 6A and 6B . As noted in the introduction,  FIG. 5B  would lead to a usable microelectronic device formed on the semiconductor wafer  10 . This comparison step  460  would indicate that the individual items of processing data, in this case the critical dimensions and overlay error, are outside of the specification as given for example in  FIG. 6A , but nevertheless the result still lies within an acceptable range of the process window, as illustrated  FIG. 6B . 
         [0053]    The comparison result from step  460  may also be used to estimate yield. For example, it is possible that the comparison step  460  indicates that many of the exposure fields  70  on the semiconductor wafer  10  will lead to acceptable (within specification) microelectronic devices on the semiconductor wafer  10 , but one or more of the exposure fields or one or more of the microelectronic devices formed within the exposure field  70  ( FIGS. 2 and 3 ) may be out of specification, where most of the other semiconductor circuits or microelectronic devices formed in other ones of the exposure fields  70  are likely to be within the specification. In this latter case, there may be no reason for re-working the complete photoresist layer, but rather it would be more efficient to continue processing the rest of the layers on the measured semiconductor wafer  13  and to disregard potentially those microelectronic devices formed in the exposure fields  70  of the measured semiconductor wafer  13 , which may be out of specification. 
         [0054]    It should be appreciated that the comparison result generated in the comparison step  460  may not be necessarily be a binary decision. It is more likely that the comparison result is part of a continuum and that the comparison result indicates, for example, that there is a high probability that the microelectronic device may not be within specification and therefore the operator can make a decision. In one non-limiting example of these methods, a threshold value is inserted for one or more of the dimensions of the process window. Should the comparison result indicate in step  480  that the measured semiconductor wafer  13  falls on one side of the threshold value in one (or more) dimensions, then appropriate actions, such as re-working or scrapping of the exposed and processed semiconductor wafer  12  in step  485  can be initiated. Should the comparison step  460  indicate that the measured semiconductor wafer  13  is on the other side of the specified threshold value, then processing of the exposed and developed semiconductor wafer  12  can continue in step  480 . Some of the dimensions of the process results or the processing data are likely to be more critical than other ones of the process results or the processing data and this is also taken into account in this comparison step  460 . It will be also appreciated that some of the dimensions of the process results are related to other dimensions of the process results and that there can be a “trade off” between different ones of the process results, such as that shown in  FIG. 5B  in which there is a CD error in the line L 1  and an overlay error in L 2 , but the microelectronic circuit nonetheless is expected to work. 
         [0055]    The process window might be thought of in some cases as a multi-dimensional layered object, like an onion. At the centre of the layered object, there is a very high probability that, if all of the measurement parameters have values in this centre, the yield of the measured semiconductor wafer  13  will be high, as most if not all of the microelectronic devices should work. Towards the outer layers, there are areas of low probability variations. In other words, there is a lower probability that the microelectronic devices will work if one or more of the measurement parameters fall within these areas. However, there may be no need to completely re-work the exposed and developed semiconductor wafer  12  as it will be expected that at least most of the microelectronic devices will work and thus the yield will be sufficiently high. It is possible to change also the threshold values for rejecting an exposed and developed semiconductor wafer  12  over the volume of the process window to take into account mutual interactions of the process parameters. 
         [0056]    The comparison result can also be used to adapt the process window if appropriate and this is shown in steps  490  and  495 . The result of the tests can be used to adapt in step  495  the stored process window  67  to indicate that in fact some of the dimensions of the processing data are not as sensitive as originally stored in the process window, or that certain parameter combinations lead (or do not lead) to failure/malfunction of the microelectronic devices. This is termed “feedback”. 
         [0057]    Another result could indicate that some of the process parameters in the exposure tool  20  can be amended to improve the performance of the process and this is also done in step  495 . 
         [0058]    The comparison step  460  might also indicate that extra measurements need to be carried out on the layer of the measured semiconductor wafer  13  to indicate whether the specifications have been met. 
         [0059]    One non-limiting example use of the method of this description is in analysing the processing of the semiconductor wafer using a technique known as self-aligned double patterning (SADP). This technique is known in the art and comprises a so-called spacer which is a film layer, formed on the sidewall of a previously pre-patterned feature. The method is shown in  FIG. 7 , which starts at step  700  and in step  710  a photoresist layer is deposited on the surface of the semiconductor wafer  10 . The photoresist layer is patterned and exposed in the exposure tool  20  in step  720  to leave a pattern on the surface of the semiconductor wafer  10 . 
         [0060]    In a next step, a spacer is formed in step  730  by deposition of further material or reaction of the photoresist layer, followed by etching in step  740  to remove all of the material on a horizontal surface except the spacer material, thereby leaving only the spacer material on the sidewalls. The originally patterned feature can be removed in step  750  and leaves only the spacer left. As noted above, the spacers were formed on the side wall of the previously pre-patterned feature and there are now effectively two spacers for every line. 
         [0061]    The analysis method of this description can therefore be used to analyse whether the layers formed using SADP are likely to be within specification or not. This has been difficult with previous methods of the difficulty or the multiple variations of process parameters involved in the SADP method. 
         [0062]    The present disclosure further relates to a computer program product embedded on a computer readable medium for carrying out the analysis. The computer program product comprises executable instructions for the measurements on the semiconductor wafers and the manufacture of wafers, as well as the simulation. 
         [0063]    While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example, and not limitation. It will be apparent to persons skilled in the relevant arts that various changes in form and detail can be made therein without departing from the scope of the invention. For example, in the present disclosure, the semiconductor wafer has been exposed to a light source, such as an ultra-violet light source. However, it is well known to use other sources of illumination, such as electron beams, x-rays or similar sources of electromagnetic energy with wavelengths much shorter than light. Thus, the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. The entirety of each of the aforementioned documents is incorporated by reference herein. 
       REFERENCE NUMERALS 
       [0000]    
       
           1  Fabrication unit 
           10  Semiconductor wafer 
           11  Exposed semiconductor wafer 
           12  Exposed and developed semiconductor wafer 
           13  Measured semiconductor wafer 
           20  Exposure tool 
           21  Load port 
           22  Substrate holder 
           23  Processing data 
           24  Light source 
           25  Projection system 
           26  Projection optics 
           27  Measurement sensor 
           28  Photo mask 
           29  Unload port 
           30  Exposure controller 
           40  Developing unit 
           50  Measurement tool 
           60  Processor 
           65  Storage Memory 
           67  Process models 
           70  Exposure field 
           71  Overlay marks 
           72  Further overlay marks