Abstract:
A speech-synthesizer timepiece disclosed herein is adapted to provide audible sounds indicative of time and/or calender information. The audible sounds are followed by an adjective phrase which represents such a unit of the preceding time and/or calender information as month, day, day of the week, hours, and minutes. The adjective phrase consists of one or more audible sounds like that indicative of the body of the time and/or calender information.

Description:
BACKGROUND AND SUMMARY OF THE INVENTION 
     The present invention relates to a speech-synthesizer timepiece which provides audible sounds indicative of time and calendar information. 
     A speech-synthesizer timepiece is well known, for example, U.S. Pat. No. 3,998,045 TALKING SOLID STATE TIMEPIECE by R. W. Lester. A prior art timepiece was adapted to provide audible sounds indicative of time information in the form of a series of digits only. In other words, there was nothing in the audible sounds which modified the audible time information, for example, units of the preceding digital time information such as hours, minutes and seconds. It was, therefore, difficult to recognize the audible sounds indicative of time information accurately. 
     Accordingly, it is an object of the present invention to provide an improved speech-synthesizer timepiece which can provide audible sounds indicative of not only digit information but also unit information concerning updated time information. 
     It is another object of the present invention to provide an improved speech-synthesizer timepiece which can provide audible sounds indicative of not only digit information but also unit information concerning updated calender information. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects and many of the attendant advantages of the present invention will be readily appreciated as the same becomes better understood by reference to the following detailed description which should be considered in conjunction with the accompanying drawings, and wherein: 
     FIG. 1 is a perspective view of a speech-synthesizer timepiece in one preferred embodiment of the present invention; 
     FIG. 2 is a circuit block diagram of the speech-synthesizer timepiece of FIG. 1; 
     FIGS. 3 through 9 are flow charts showing control steps in the embodiment of the speech-synthesizer timepiece, wherein FIG. 3 shows a main routine MAIN, FIG. 4 shows a month announcing routine VOMNT, FIG. 5 shows a date announcing routine VOD, FIG. 6 shows a hour announcing routine VOH, FIG. 7 shows a minute announcing routine VOM, FIG. 8 shows a day of the week announcing routine VOW, and FIG. 9 shows a sound delivering routine VO; 
     FIG. 10 is a perspective view of another preferred embodiment of the speech-synthesizer; 
     FIG. 11 is a time chart showing control steps in a main routine MAIN&#39; in the second embodiment; 
     FIG. 12 is a block diagram of the timepiece having time correction facilities; and 
     FIG. 13 shows control steps in the timepiece of FIG. 12. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to FIG. 1, there is illustrated in a perspective view one preferred form of the present invention, which includes recall keys such as &#34;month&#34;, &#34;day&#34;, etc., and a loud speaker SP, thereby providing audible sounds in accordance with actuations of the recall keys. For example, an audible sound &#34;--gatsu (month in English)&#34; is provided upon actuation of the &#34;month&#34; recall key, an audible sound &#34;--nichi(day in English)&#34; is provided upon actuation of the &#34;day&#34; recall key, and an audible sound of full calender and time length &#34;--gatsu--nichi--yohbi (day of the week in English) --ji (hour in English)--fun or pun (minute in English)&#34; is provided upon actuation of the &#34;all&#34; recall key. 
     In FIG. 2 showing a block diagram of the speech-synthesizer timepiece embodying the present invention, an oscillator CG generates a time standard signal and a divider DV divides the time standard signal into a 60 KHz signal. A counter series CO provides a &#34;month&#34; signal, a &#34;day&#34; signal, a &#34;day of the week&#34; signal, a &#34;hour&#34; signal, and a &#34;minute&#34; signal for introduction to the corresponding regions of a timekeeping register R. The contents of the timekeeping register R are transferred into a second register B in response to the development of a command  13 . Upon the development of commands  14 - 22,  information in respective regions of the register B is transferred into a buffer register D. The register B consists of nine regions: Two regions MO 2  and MO 1  storing &#34;month&#34; information in the order of tens of months and months, two regions DA 2  and DA 1  storing &#34;day&#34; information in the order of tens of days and days, a region W storing &#34;day of the week&#34; information, two regions H 2  and H 1  storing &#34;hour&#34; information in the order of tens of hours and hours, and two regions M 2  and M 1  storing &#34;minute&#34; information in the order of tens of minutes and minutes. 
     A read only memory RM stores sound quantizing digital codes per voice word element. Table 1 sets forth the relationship between the type and the voice initial address of the respective voice elements. 
     
                       TABLE 1______________________________________NA      ichi    NO       jyu     NAC    futsuNB      itsu    NP       ji      NAD    miNC      ni      NQ       pun     NAE    itsuND      san     NR       fun     NAF    muiNE      yo      NS       rei     NAG    nanoNF      yon     NT       gatsu   NAH    yohNG      go      NU       tsuitachi                            NAI    kokonoNH      roku    NV       ka      NAJ    getsuNI      rotsu   NW       toh     NAK    kaNJ      nana    NX       hatsu   NAL    suiNK      hachi   NY       nichi   NAM    mokuNL      ku      NZ       yohbi   NAN    kinNM      kyu     NAA      shi     NAO    doNN      jyuh    NAB      yo      NAP    nichi______________________________________ 
    
     In the foregoing table 1, NA, NB, NC, . . . NAP denote the initial addresses of the respective word elements which are terminated with END codes led out during the final steps. The output R 0  of the read only memory RM is provided in the form of digital codes and then converted via a digital-to-analog converter DA and a low pass filter LPF into analog waveform signals suitable to the generation of audible sounds. The audible sounds are released from a loud speaker SP via a driver DR. 
     A first voice initial address circuit CC decides the voice initial address in accordance with the contents of the buffer register D in providing a desired audible sound. Address data is loaded into an address counter AC. A second voice initial address circuit CB decides a desired voice initial address pursuant to a command to be described later, the initial address thus decided being loaded into the same address counter AC. An adder FA effects additions of &#34;1&#34; to the contents of the address counter AC, incrementing the address specified by the second voice initial address circuit CB. A reset circuit CAC resets the address counter AC and, when the address counter AC is in the reset condition, none of the addresses in the read only memory RM may be designated. In this way, the address counter AC establishes the voice initial address and increments the address for selection of the respective word elements from the read only memory RM via an address decoder ADC. 
     A decision logic circuit JD is connected to the buffer register D to decide if the contents of the buffer register D are &#34;0&#34; or &#34;1, 4&#34; or &#34;1, 3, 4, 6&#34;, whereas a decision logic circuit JE detects the END codes led out from the read only memory RM. RS type flip flops FA, F1-F5 provide various controls, with the set outputs thereof being sensed by decision logic circuits JFA and JF1-JF5. Key switches MOK-AK are actuated for announcing calender and time information in the form of audible sounds. The actuated and non-actuated conditions are sensed by decision logic circuits. A sequential control circuit PC is responsive to the conditions of the respective keys and the outputs of the various decision circuits JD, JE, JFA, JF1-JF5, JMO-JA and JK to develop commands  1 ,  2 , . . .  Z . The month recall key is labeled MOK, the date recall key is labeled DAK, the day of the week recall key is labeled WK, the hour recall key is labeled HK, the minute recall key is labeled MK and the date/day of the week/time recall key is labeled AK. 
     FIG. 3 shows a main routine of the sequential control circuit PC, whereby the operative conditions of the respective keys are monitored to select the announcing subroutines which are described in detail below. 
     FIG. 4 shows the &#34;month&#34; announcing routine, FIG. 5 shows the &#34;day&#34; announcing routine, FIG. 6 shows the &#34;hour&#34; announcing routine, FIG. 7 shows the &#34;minute&#34; routine, and FIG. 8 shows the &#34;day of the week&#34; routine. These routines are described to give a better understanding of structure and operation of the device of FIG. 2. 
     [main routine MAIN: FIG. 3] 
     As stated briefly, the main routine is executed to monitor the operative conditions of the respective recall keys and select one of the announcing routines according to the results of such monitor. 
     During the step n 1  (abbreviated &#34;n 1  &#34; hereinafter, likewise the step n 2  and so on) it is decided whether any of the recall keys has been actuated. If the affirmative answer is provided, n 1  →n 2  so that a command  13  is developed to shift all the contents of the timekeeping register R into the register B, followed by n 3  whereby all the flip flops storing the various conditions are placed into the reset condition. The circuit configuration is, therefore, initiated prior to the beginning of the announcing modes. 
     The decision circuits JA, JMO, JDA, JW, JH monitor the operational conditions of the date/day of the week/time recall key AK, the month recall key MOK, the day recall key WK, the day of the week key WK, and the hour recall key HK, respectively, during n 4  to n 14 , with the results of the monitoring operation being stored within the flip flops FA, F 1  -F 5  in the set condition. Actuation of the minute recall key MK allows the procedure to to advance from n 11  to n 13 , placing the flip flop F 5  into the set condition without monitoring the condition of the key MK. It is obvious from FIG. 3 that during n 14  the flip flop FA is set upon actuation of the AK key, all the flip flops are held in the reset condition upon actuation of the MOK key, the flip flop F 1  is set upon actuation of the DAK key, the flip flop F 3  is set upon actuation of the WK key, the flip flop F 4  is set upon actuation of the HK key, and the flip flops are monitored until n 22  for subsequent selection of the announcing subroutines. 
     The flip flop F 5  in the set condition permits n 14  →n 15  and renders the subroutine VOM operable. The flip flop F 4  in the set condition permits n 16  →n 17  and renders the subroutine VOH operable. The flip flop F 3  in the set condition enables the subroutine VOM via n 19  →n 20 . 
     The flip flop F 1  in the set condition effects n 22  →n 23  leading to the subroutine VOD. In the event that any of the flip flops F 5 , F 4 , F 3  and F 1  is not in the set condition, n 22  →n 25  thereby starting the subroutine VOMT to provide desired audible sounds. If the flip flop FA is set, then the subroutine VOMT is enabled during n 25  and the flip flop F 1  is set upon n 25  →n 26  with the resulting sequences of n 26  →n 27  →n 14  and n 14  →n 16  →n 19  →n 22 . Under the existing circumstance it is decided whether the flip flops are in the set condition and n 22  →n 23  results in selecting the subroutine VOD since the flip flop F 1  has been already set during n 22 . Subsequent to this, n 20  is reached for providing an audible sound indicative of &#34;day of the week&#34; information. After completion of such announcing mode n 17  is effected for the hour announcing mode. Lastly, n 1  is restored after the minute announcing mode is completed during n 15 . In conclusion, audible sounds are provided in the sequence of &#34;month&#34;→&#34;date&#34;→&#34;day of the week&#34;→&#34;hour&#34;→&#34;minute&#34; upon actuation of the AK key. The respective announcing modes are carried through in the following manner. 
     [subroutine VOMNT: FIG. 4] 
     The subroutine VOMNT is constructed for providing audible sounds indicative of &#34;month&#34; and stemmed from n 25  within the main routine. 
     During n 28  the command  14  is developed so that the &#34;month&#34; information in the order of tens of months is transferred from the region MO 2  of the register B to the buffer register D. The next succeeding n 29  is effected to decide if such information is &#34;0&#34;. If D=O, n 32  is activated and, if D≠O, n 30  is activated. In the latter case D≠O any of jyugatsu (October) through Jyunigatsu (December) should be announced in audible sounds, implying that &#34;jyu&#34; should be first announced unconditionally. To this end n 30  and n 31  are effected to provide audible sound &#34;jyu&#34;. In other words, the command  n  is developed during n 30  so that the second voice initial address circuit CB specifies the voice initial address NN concerning the word element &#34;jyu&#34; for the address counter AC. The voice announcing subroutine V 0  is next selected to provide audible sounds &#34;jyu&#34;. Details of this routine will be described later. 
     After the production of the audible sounds &#34;jyu&#34; or after D=O is concluded during n 32 , the command  15  is developed in n 32  such that &#34;month&#34; information in the order of months is transferred from the region MO 1  of the register B to the buffer D. n 33  is executed to sense if the contents of the buffer D are D=&#34;4&#34; or D≠&#34;4&#34;. In the former, n 38  is effected so that the voice initial address NAA concerning the word element &#34;shi&#34; is specified in the address counter AC by the second voice initial address circuit CB. Conversely, in the latter, the command 23  is developed so that the contents of circuit element CC 1  of the first voice initial address CC is loaded into the address counter AC with the voice initial address of the word element corresponding to the contents of the buffer D. 
     It will be noted from FIG. 2 that the first voice initial address decision circuit CC consists of four circuit elements CC 1 , CC 2 , CC 3  and CC w  each deciding the voice initial address of the respective word elements. Table 2 lists such relationship between the word elements and the addresses. 
     
                                           TABLE 2__________________________________________________________________________CC.sub.1   CC.sub.2 CC.sub.3 CC.sub.4  word     word     word     wordD element  address      element           address               element                    address                        element                             address__________________________________________________________________________1 ichi NA  i    NB           getsu                             NAJ2 ni   NC  ni   NC  fu   NAC ka   NAK3 san  ND  san  ND  mitsu                    NAD sui  NAL4 yo   NE  yon  NF           moku NAM5 go   NG  go   NG  itsu NAE kin  NAN6 roku NH  ro   NI  mni  NAF do   NAO7 nana NJ  nana NJ  nana NAG nichi                             NAP8 hachi  NK  hachi           NK  yoh  NAH9 ku   NL  kyu  NM  kokono                    NAI__________________________________________________________________________ 
    
     Since the first voice initial address decision circuit CC 1  is selected during n 34 , the voice initial address specified by the address counter AC is any of NA, NC, ND, NG, NH, NJ, NK and NL. If D=&#34;0&#34;, the address counter AC still remains in the previous condition or the reset condition. When the address counter AC specifies a particular address during n 34  or n 38 , n 35  or the voice subroutine V 0  is reached to provide an appropriate word element. This is followed by n 36  where the command  t  is developed and the second voice initial address circuit CB specifies the voice initial address NT concerning the word element &#34;gatsu&#34; for the address counter AC. The audible sounds &#34;gatsu&#34; are provided through the subroutine VO in n 37 . The relationship between the month information stored within the regions MO 2  and MO 1  of the register B and the audible sounds are viewed as follows: 
     
         ______________________________________January  &#34;ichigatsu&#34; July      &#34;nanagatsu&#34;February &#34;nigatsu&#34;   August    &#34;hachigatsu&#34;March    &#34;sangatsu&#34;  September &#34;kugatsu&#34;April    &#34;shigatsu&#34;  October   &#34;jyuhgatsu&#34;May      &#34;gogatsu&#34;   November  &#34;jyuhichigatsu&#34;June     &#34;rokugatsu&#34; December  &#34;jyunigatsu&#34;______________________________________ 
    
     [subroutine VOD: FIG. 5] 
     The subroutine VOD starting with n 23  during the main routine is effected to provide audible sounds indicative of &#34;day&#34;. 
     The command  17  is developed during n 38 , shifting the &#34;day&#34; information in the order of days from the region DA 1  of the register B to the buffer D. Whether D=&#34;O&#34; is determined during n 39 , and when D=&#34;0&#34; n 40  is executed to set the flip flop F 2 . Subsequent execution of n 41  develops the command  16 , transferring the &#34;day&#34; information in the order of tens of days from the region DA 2  of the register B to the buffer D. n 42  is effected to check if the contents of the buffer B are &#34;0&#34;. If they are not &#34;0&#34;, n 53  is effected to check again if they are &#34;1&#34;. If not, n 67  is effected to check if they are &#34;2&#34;. This is because the same digits should sometimes be pronounced in different sounds. In the case where D=&#34;0&#34; during n 42 , the following procedure will be carried out. In this case n 42  →n 43  where the contents of the region DA 1  of the register B are loaded into the buffer D. When D=&#34;1&#34; during n 44 , the command  u  is developed via n 51  and n 52  to specify the voice initial address N u  concerning &#34;tsuitachi&#34; for the address counter AC. The sounds &#34;tsuitachi&#34; are provided during n 52 . If D≠&#34; 1&#34; during n 44 , the next step n 45  is effected to check if the contents of the buffer D are &#34;4&#34;. If D=&#34;4&#34;, the command  ab  is developed to specify the voice initial address NAB concerning the word element &#34;yo&#34; for the introduction to the address counter AC during n 47  in order to provide the word element &#34;yo&#34;. Such word element &#34;yo&#34; is provided during n 48 . Thereafter, the voice initial address NAK concerning the word element &#34;ka&#34; is specified by the address counter AC, followed by the audible sound &#34;Ka&#34; provided during n 30 . 
     If D≠4 during n 45 , n 46  is performed to specify the voice initial address concerning the word element corresponding to the contents of the buffer D through the address circuit CC 3  and load the same into the address counter AC. The word element is pronounced during n 48 , n 49  →n 50 . The &#34;day&#34; information stored within the register region DA1 and the audible sounds released from n 44  to n 50  are correlated as follows: 
     
         ______________________________________1st day   &#34;tsuitachi&#34;  6th day &#34;muika&#34;2nd day   &#34;futsuka&#34;    7th day &#34;nanoka&#34;3rd day   &#34;mikka&#34;      8th day &#34;yohka&#34;4th day   &#34;yokka&#34;      9th day &#34;kokonoka&#34;5th day   &#34;itsuka&#34;______________________________________ 
    
     When D≠0 during n 42 , n 42  →n 53  to decide if D=1. Since the &#34;day&#34; information should be pronounced starting with the tens of days unit in any case, there is established a distinction between ten&#39;s days, twenty&#39;s days and thirty&#39;s days. In order to provide peculier sounds, there should be further established between ten&#39;s and twenty&#39;s. In other words, n 53  is effected to make a distinction between ten&#39;s and twenty&#39;s and thirty&#39;s and n 67  between twenty&#39;s and thirty&#39;s. 
     During n 54  &#34;tenth day&#34; is distincted from other ten&#39;s days and during n 68  &#34;twentieth day&#34; is sensed different from other twenty&#39;s days. n 39  and n 40  are carried out to check if the flip flop F 2  is in the set condition. In the case of n 53  →n 54  →n 77 , the contents of the regions DA 2  and DA 1  of the register B designate &#34;tenth day&#34; and during n 77  the command  W  is developed to load the voice initial address NW concerning the word element &#34;toh&#34; into the address counter AC through the action of the second voice initial address circuit CB. This is followed by n 74  where the voice subroutine VO is selected to provide an audible sound &#34;toh&#34;. The development of the command  V  during n 75  permits the voice initial address NV concerning the word element &#34;ka&#34; to be loaded into the address counter AC, thereby providing an audible sound &#34;ka&#34;. Therefore, audible sounds &#34;tohka&#34; are provided in succession. 
     Upon the advance of n 53  →n 67  →n 68  →n 73 , the contents of the regions DA 2  and DA 1  of the register B specify &#34;twentieth day&#34; and the command  X  is developed during n 73 , loading the voice initial address NX for the word element &#34;hatsu&#34; into the address counter AC through the second voice initial address circuit CB. The subroutine VO is selected during n 74  to provide the word element &#34;hatsu&#34; and provide the word element &#34;ka&#34; during n 75 . In this case, &#34;hatsuka&#34; is pronounced in succession. &#34;Tenth day&#34; and &#34;twentieth day&#34; require the peculier pronunciations as above. Audible sounds indicative of tenth&#39;s days, twenth&#39;s days and thirty&#39;s days excluding the above described &#34;tenth day&#34; and &#34;twentieth day&#34; are provided in the following manner. 
     The first concern is the audible sounds indicative of tenth&#39;s days. Since in this case D=1 during n 53 , n 54  is made operable where the flip flop F 2  remains in the reset condition. Then, during n 55  the command  n  is developed to load the voice initial address NN concerning the word element &#34;jyuh&#34; into the address counter AC. The voice subroutine VO is selected to provide an audible sound &#34;jyuh&#34; during n 56 . The contents of the region DA 1  of the register B containing the &#34;day&#34; information in the order of days are transferred into the buffer D in response to the command  17 . The contents of the register D are indicated in the form of audible sounds in the following manner. If D=4 provision of audible sounds &#34;yokka&#34; requires sequential execution of n 58  →n 65 . In other words, the command  ab  is developed during n 65  to load the voice initial address NAB for the word element &#34;yo&#34; into the address counter AC through the second voice initial address circuit CB. Thereafter, the subroutine VO is selected to provide the word element &#34;yo&#34;. The audible sound &#34;ka&#34; is provided through n 75  and n 76 . If D≠4 during n 58 , the procedure is effected in the sequence of n 59  →n 60  to develop the command  23  and load into the address counter AC the voice initial address for the particular word element corresponding to the contents of the buffer D through the first voice initial address circuit CC 1 . n 60  →n 61  are sequentially executed to provide audible sounds corresponding to desired word elements. In the case of tenth&#39;s days, n 59  is not followed directly by n 62 . This is because n 54  →n 77  when the flip flop F 2  is in the set condition. 
     Immediately after the &#34;day&#34; information is announced in the form of audible sounds during n 61 , the unit information &#34;nichi(day in English)&#34; is to be provided. During n 62  the voice initial address NY concerning the word element &#34;nichi&#34; is established in the address counter AC and during n 63  the voice subroutine VO is selected and executed to provide audible sounds &#34;nichi&#34;. 
     Audible sounds indicative of twenty&#39;s days are provided during the sequence of n 53  →n 67  →n 68 . Audible sounds &#34;hatsuka&#34; are provided during n 68  →n 73 . Since twenty&#39;s days other than twentieth day are all provided in audible sounds &#34;nijyu . . . &#34;, it is necessary to provide first audible sounds &#34;nijyuh&#34; when n 68  →n 69 . This is accomplished in the sequence of n 69  →n 70  →n 55  →n 56 . More fully discussed, the command  C  is developed during n 69  to load the voice initial address NC concerning the word element &#34;ni&#34; into the address counter AC through the second voice initial address circuit CB. The voice subroutine VO is selected to produce an audible sound &#34;ni&#34; during n 70 , followed by n 55  wherein the command  N  during n 55  loads the address counter AC with the voice initial address NN concerning the word element &#34;jyuh&#34;, enabling n 66  to make that audible sounds. Accordingly, the audible sounds &#34;nijyuh&#34; are provided during the sequence of n 69  →n 70  →n 55  →n 56 . Upon the termination of the audible sounds indicative of the &#34;day&#34; information in the order to tens of days, n 57  is reached so that the audible sounds of the &#34;day&#34; information in the order of days are provided in the same way as above. In this case the flip flop F 2  is not likewise in the set condition during n 59 . As long as the flip flop F 2  is in the set condition, the day to be announced at this moment is &#34;twentieth day&#34;, permitting n 68  →n 73 . 
     Audible sounds indicative of thirty&#39;s days are provided in the following way. Since D=3 during n 41 , the events occur in the sequence of n 42  →n 53  →n 67  →n 71 . The command d  is developed during n 71 , setting the address counter AC with the voice initial address ND concerning the word element &#34;san&#34;, which in turn is announced during n 72 . The audible sounds &#34;jyuh&#34; are provided in the same way as in the tenth&#39;s days and twenty&#39;s days via n 55  →n 56  . . . , followed by generation of audible sounds indicative of the &#34;day&#34; information in the order of days. In the case of thirty&#39;s days, it is possible that n 59  may be followed directly by n 62 . This is due to the fact that the flip flop F 2  is in the set condition during n 40 . In this case audible sounds &#34;sanjyuhnichi&#34; are provided until n 63  is reached. Since there is no possibility that D= 4 during n 58 , n 58  is necessarily followed by n 59 . The following sets forth the relationship between the contents of DA 2  and DA 1  of the register B indicative of the &#34;day&#34; information and the corresponding audible sounds from n 53  to n 63 . 
     
         ______________________________________10th day  &#34;tohka&#34;11th day  &#34;jyuhichinichi&#34;                 21st day &#34;nijyuhichinichi&#34;12th day  &#34;jyuhninichi&#34;  22nd day &#34;nijyuhninichi&#34;13th day  &#34;jyuhsannichi&#34; 23rd day &#34;nijyuhsannichi&#34;14th day  &#34;jyuhyokka&#34;    24th day &#34;nijyuhyokka&#34;15th day  &#34;jyuhgonichi&#34;  25th day &#34;nijyuhgonichi&#34;16th day  &#34;jyuhrokunichi&#34;                 26th day &#34;nijyuhrokunichi&#34;17th day  &#34;jyuhnananichi&#34;                 27th day &#34;nijuuhnananichi&#34;18th day  &#34;jyuhhachinichi&#34;                 28th day &#34;nijyuhhachinichi&#34;19th day  &#34;jyuhkunichi&#34;  29th day &#34;nijyuhkunichi&#34;20th day  &#34;hatsuka&#34;      30th day ... &#34;sunjyuhnichi&#34;                 31st day &#34;sanjyuhichinichi&#34;______________________________________ 
    
     [Subroutine VOH: FIG. 6] 
     The subroutine VOH starting with n 17  of the main routine MAIN is executed to provide audible sounds indicative of &#34;hour&#34; information. 
     The flip flop F 3  is reset during n 81  and the command  19  is developed to transfer the &#34;hour&#34; information in the order to tens of hours from the region H 2  of the register B to the buffer D during n 79 . Then, n 80  is effected to enable the decision circuit JD to check if the contents thus transferred are &#34;0&#34;. If D=0, n 86  is enabled to set the flip flop F 3 . Contrarily, if D≠0, n 80  →n 81  is effected to determine D=1 or D≠1, selecting either n 84  or n 82 . In the former the voice initial address NN concerning the word element &#34;jyuh&#34; is loaded into the address counter AC through the second voice initial address circuit CB. Then, the voice routine VO is selected to provide audible sounds &#34;jyuh&#34; during n 85 . 
     If D≠1, n 81  →n 82  with the development of the command  C  which permits the voice initial address NC concerning the word element &#34;ni&#34; to be loaded via the second voice initial address circuit CB into the address counter AC. During n 83  the voice subroutine VO is performed to provide the sound &#34;ni&#34;, followed by provision of the audible sounds &#34;jyuh&#34; in n 84  →n 85 . In conclusion, the audible sounds &#34;nijyuh&#34; are released during the sequence of n 81  →n 82  →n 83  →n 84  →n 85 . 
     The above described procedure completes the provision of the audible sounds derived from the region H 1 . The succeeding routines are effected successively to provide audible sounds indicative of the contents of the region H 1  and the hour information. When D=0 during n 80 , n 87  is reached directly via n 86  so that an audible sound is not provided when the contents of the region H 2  are &#34;0&#34;. It is necessary to provide audible sounds &#34;reiji&#34; only when the contents of the region H 2  are &#34;0&#34; and that of the region H 1  are &#34;0&#34;. The reason why the flip flop F 3  is set during n 86  is because there is a requirement for determining the condition of the flip flop F 3  during n 89 . 
     Upon arrival at n 87 , since audible sounds indicative of the hour information in the order of hours are to be derived from the region H 1 , the contents of the region H of the register B are transferred into the buffer D in response to the command  20 . N 88  is carried out to check if the contents are &#34;0&#34; and when D=0 it is determined if the flip flop F 3  is in the set condition. If it is set, n 89  →n 90  is effected to provide audible sounds &#34;rei&#34; so that the command  S  is developed to specify the voice initial address NS concerning the word element &#34;rei&#34; for the address counter AC through the second voice initial address circuit CB. Then, the voice subroutine VO is selected to provide the audible sounds &#34;rei&#34; during n 92 . Contrarily, if the flip flop F 3  is in the reset condition during n 89 , there is no necessity for providing the audible sounds &#34;rei&#34; even when D= 0 during n 88  because D≠0 during n 80 . The next step is for the provision of an audible sound &#34;ji&#34; indicative of the unit of hours. 
     When D≠0 during n 88  and thus when the contents of the region H 1  storing the hour information in the order of hours are &#34;0&#34;, the command  23  is developed during n 91 , loading the address counter AC with the voice initial address of the word element as determined by the contents of the buffer D via the first voice initial address circuit CC 1  of CC in response to the command  23 . During the next succeeding step n 92  the voice subroutine VO is selected for the purposes of providing desired word elements. 
     The contents of the regions H 2  and H 1  are indicated in audible sounds until n 92  and the hour unit information &#34;ji&#34; is provided in audible sounds, thereby terminating the subtoutine VOH. The command  p  is developed during n 93  to thereby establish the voice initial address NP concerning the word elements &#34;ji&#34; within the address counter AC through the second voice initial circuit CB. The voice subroutine VO is enabled to provide the audible sound &#34;ji&#34; during n 94 . 
     From n 78  to n 95  the hour information stored within the regions H 2  and H 1  of the register B and the corresponding audible sounds are correlated as follows: 
     
         ______________________________________0 hour   &#34;reiji&#34;      10 hour  &#34;jyuhji&#34;1 hour   &#34;ichiji&#34;     11 hour  &#34;jyuhichiji&#34;2 hour   &#34;niji&#34;       12 hour  &#34;jyuhniji&#34;3 hour   &#34;sanji&#34;       .                  .                  .4 hour   &#34;yoji&#34;       15 hour  &#34;jyuhgoji&#34;5 hour   &#34;goji&#34;        .                  .                  .                  .6 hour   &#34;rokuji&#34;      .                  .7 hour   &#34;nanaji&#34;     20 hour  &#34;nijyuji&#34;                  .8 hour   &#34;hachiji&#34;     .                  .9 hour   &#34;kuji&#34;       24 hour  &#34;nijyuhyoji&#34;______________________________________ 
    
     [Subroutine VOM: FIG. 7] 
     The subroutine VOM diverged from N 15  in the main routine MAIN is executed to provide audible sounds indicative of the &#34;minute&#34; information. In the case that the AK key is depressed, this is the final subroutine subsequent to the execution of the above detailed subroutines VOMNT, VOD, VOW, and VOH. 
     During n 96  the command  22  is developed to shift the minute information in the order of minutes from the register B to the buffer D. Thereafter, if D=0 during n 97 , the flip flop F 3  is placed into the set condition at the transition of n 97  →n 98 . To the contrary, if D≠0 the step in operation is skipped from n 97  to n 99  without executing n 98 . The flip flop F 3  stores previously these conditions since subsequent pronunciations are different between D=0 and D≠0. n 99  is effected to shift the minute information in the order of tens of minute from the region M 2  of the register B to the buffer D. If D=0, n 100  →n 119  to decide if the flip flop F 3  is in the set condition. Otherwise, n 100  →n 101  to check if the contents of the buffer D are D=1 or D&gt;1. Since D≠0 means that the contents of the register B are time information longer than 10 minutes, the voice routine is carried through for the &#34;minute&#34; information in the order of tens of minutes since n 101 . If D=0, the contents of the register B are &#34;0&#34; or shorter than 10 minutes so that the flip flop F 3  is sensed with respect to the operational condition, leading to the voice routine for 0 minutes or less than 10 minutes. Since whether the flip flop F 3  is in the set condition has already decided during n 97  and n 108 , the voice enabling subroutine for zero minutes is effected through n 119  →n 120 , whereas the voice subroutine for the less than 10 minutes is effected through n 119  →n 108 . 
     If D≠0 during n 100 , n 101  is reached to decide whether D=1 or D&gt;1. Assume now that D≠1 or D&gt;1. n 101  →n 102  so that the voice initial address with respect to the word element corresponding to the contents of the buffer D more than &#34;1&#34; is established in the address counter AC via the first voice initial address circuit CC 2  upon the development of the command  24 . Thereafter, the voice subroutine VO is enabled to provide an audible sound representative of a desired word element during n 103 . n 104  is effected to sense the results with respect to the set condition of the flip flop F 3  determined during n 97  and n 98 . n 105  is advanced in the case of the reset condition. The command  0  is developed during n 105 , loading the address counter AC via the second initial address circuit CB with the voice initial address for the word element &#34;jyu&#34;. On the other hand, the command  n  is developed during n 196  so that the voice initial address for the word element &#34;jyuh&#34; is placed into the address counter AC via the second voice initial address circuit CB. This is due to the fact that &#34;jyu&#34; should be pronounced when the minute information in the order of minutes is &#34;0&#34; and &#34;jyuh&#34; be pronounced when it is not &#34;0&#34;. Provided that the address counter AC is loaded with the voice initial address for a desired word element, the voice subroutine VO is selected during n 197  to provide audible sounds &#34;jyu&#34; or &#34;jyuh&#34;. 
     In the case where D=1 during n 101  or in the case where the contents of the region M 2  of the register B are &#34;1&#34;, audible sounds &#34;jyu&#34; or &#34;jyuh&#34; may be provided and which of the audible sounds is determined according to the condition of the flip flop F 3  through n 101  →n 104 . 
     After completion of the audible sounds indicative of the contents of the region M 2  in the order of tens of minutes from n 101  to n 107 , the audible sound delivering subroutine is selected for the region M 1  storing the &#34;minute&#34; information in the order of minutes for the period starting with n 108 . The command  6  is developed during n 108 , placing the flip flop F 2  into the reset condition. The command  21  is next developed during n 109  to shift the contents of the region M 1  of the register B indicative of the &#34;minute&#34; information in the order of minutes into the buffer D. During n 110  it is decided whether D=1, 3, 4, 6 or D≠1, 3, 4, 6. n 110  →n 112  for the former and n 110  →n 111  for the latter. This is because of the necessity that there be a distinction between audible sounds &#34;fun&#34; and &#34;pun&#34; according to the contents of the &#34;minute&#34;  information in the order of minutes, as best seen from Table 3. 
     
                       TABLE 3______________________________________1 minute    ippun     6 minutes   roppun2 minute    nifun     7 minutes   nanafun3 minute    sanpun    8 minutes   hachifun4 minute    yonpun    9 minutes   kyufun5 minute    gofun     0 minutes   reifun______________________________________ 
    
     As is obvious from Table 3, the audible sounds &#34;pun&#34; are to be provided when D=1, 3, 4, 6 (the decision circuit JD=1, 3, 4, 6). If D≠1, 3, 4, 6, the flip flop F 2  is set via n 110  →n 111  and whether the flip flop F 3  is set is sensed via n 112 . 
     As already discussed with respect to n 97  and n 98 , the flip flop F 3  in the set condition means that the contents of the region M 1  in the order of minutes are &#34;0&#34;. In this case n 116  is effected and then followed by the subroutine VOM for an audible indication of the minute information with the audible sound &#34;pun&#34;. The command  Q  is developed during n 116  to introduce the voice initial address NQ regarding the word element &#34;pun&#34; into the address counter AC through the use of the second voice initial address circuit CB. Subsequently, the sounding subroutine VO is selected to release the sounds &#34;pun&#34; for n 118 . Unless the flip flop F 3  has been set during n 112 , the following step n 113  is carried out where the command  24  is developed to introduce into the address counter AC the voice initial address with respect to the word element corresponding to the contents of the buffer D via the first voice initial address circuit CC 2 . The sounding subroutine VO is selected during n 114  for provision of an audible indication. Since n 115  the flip flop F 2  is checked with respect to the operational condition to make a distinction between the audible sounds &#34;pun&#34; and &#34;fun&#34;. If the flip flop F 2  is in the set condition, n 115  →n 117  →n 118  are sequentially executed to provide &#34;fun&#34;. When in the reset condition, n 115  →n 116  →n 118  with the audible sounds &#34;pun&#34;. In summary, in the case where D≠1, 3, 4, 6 during n 110  the flip flop F 2  is set to provide &#34;fun&#34; since n 115 . If D=1, 3, 4, 6, the audible sound &#34;pun&#34; is provided. 
     Futhermore, when the flip flop F 3  is reset during n 119 , the register B assumes &#34;0&#34; with the results in the audible sounds &#34;reifun&#34; through n 120  →n 121  →n 171  →n 118 . The command  S  is developed during n 120 , locating the voice initial address NS with respect to the word element &#34;rei&#34; into the address counter AC through the second initial address circuit CB. For n 121  the voice subroutine VO is selected to provide &#34;rei&#34;, followed by &#34;fun&#34; during n 117  and n 118 . 
     The following is a listing of the audible sounds derived during the subroutine VOM. 
     
         ______________________________________  ten minutes             jyuppun  eleven minutes             jyuhippun      .      .      .      .      .      .      .  fifteen minutes             jyuhgofun  sixteen minutes             jyuhroppun      .      .      .      .      .      .  twenty minutes             nijyuppun      .      .      .  fifty minutes             goiyuppun      .      .      .      .  fifty nine minutes             . gojyuhkyuhfun______________________________________ 
    
     [Subroutine VOW: FIG. 8] 
     This subroutine VOW is constructed to provide audible sounds indicative of &#34;day of the week&#34;, starting with n 20  in the main routine MAIN. 
     As long as &#34;day of the week&#34; is determined an audible sound is determinative without any second condition. This routine does not require any decision step for sensing the condition of the flip flop. What day of the week is audibly announced during n 122  -n 124 , followed by an audible sound &#34;bi&#34; during the sequence of n 125  -n 126 . 
     During n 122  the command  18  is developed, indicating the contents of the region W of the register B storing the day of the week information to be shifted into the buffer D. Subsequent to this, the command  27  is developed during n 123  so that the voice initial address with respect to the word element corresponding to the contents of the register D is introduced into the address counter AC via the first voice initial address circuit CCW. n 124  is then effected to enable the voice subroutine VO for providing the word element indicative of &#34;day of week&#34;. During n 125  the command  Z  is provided, loading the voice initial address concerning word element &#34;bi&#34; into the address counter the AC with the aid of the voice initial address circuit CB. An audible indication of &#34;bi&#34; (n 126 ) follows. The relationship between the first voice initial address circuit CC W  and the buffer D is suggested in Table 2. 
     Through these procedures the day of the week information is audibly indicated in the following relationship. 
     
         ______________________________________Monday             &#34;getsuyohbi&#34;Tuesday           &#34;kayohbi&#34;Wednesday         &#34;suiyohbi&#34;Thursday          &#34;mokuyohbi&#34;Friday            &#34;kinyohbi&#34;Saturday          &#34;doyohbi&#34;Sunday            &#34;nichiyohbi&#34;______________________________________ 
    
     [Subroutin VO: FIG. 9] 
     The subroutine VO is one that is executed at the lowest level. The voice initial address concerning a desired word element within the address counter AC is increasingly incremented to derive sound quantizing data in succession from the output R o  of the read only memory RM. This subroutine permits all the audible sounds to be released outside. 
     n 127  is effected to decide if the quantizing data at the voice initial address in the address counter AC is the END code. Otherwise, the address counter AC is incremented by one via n 128 . n 128  is reached when the END code are to be sensed subsequent to return to n 127 . While passing a closed loop of n 127  →n 128  →n 127  →. . . , the address counter AC is incremented increasingly for eventual detection of the END code at n 127 . The quantizing data keeps being derived in succession from the output R o  until the development of the END code at n 127 . The END code sensed permits the address counter AC through n 127  →n 129 . In FIG. 10, there is illustrated another embodiment of the present invention with the number of keys reduced and manipulation simplified. FIG. 11 shows a modified main routine MAIN&#39;. Circuit construction is similar to that in FIG. 2 except that a family of the recall keys consists of a date recall key in terms of month, day and day of the week, a time key in terms of hours and minutes, and the ALL key and the decision circuit consists of only three circuits ID, JT and JA. 
     The modified main routine MAIN&#39; decides during n 1  whether any of the keys has been actuated. Upon detection of any actuated key the contents of the timekeeping register R are transferred to the register B during n 2  as in FIG. 3 and all the flip flops are reset during n 3 . Subsequently, n 4  and n 14  are effected to decide which of the date key (DK), the time key (TK) and the ALL key (AK) has been actuated. n 6  will follow upon the date key DK actuated and n 15  and n 6  will follow upon the time key TK actuated wherein the flip flop F 5  is set. When the ALL key AK has been actuated, the flip flop FA is set during n 5 , followed by n 6 . These flip flops make distinction between the date announcing mode and the time announcing mode and selects the modes both or either. Whether the flip flop F 5  is set is decided during n 6 . If the flip flop F 5  is set, n 12  →n 13  to execute the subroutines VOH and VOM for the time announcing mode. Otherwise, the subroutine VOMNT, VOD, and VOW are sequentially executed n 7  →n 8  →n 9  for the date announcing mode. In the case where the flip flip FA is set, n 6  →n 7  →n 8  →n 9  are sequentially effected for the date announcing mode and the flip flop F 5  is set during n 10 . Whether the flip flop F A  is in the set condition is determined during n 11 , followed by n 6 . Since the flip flop F 5  is in the set condition during n 10 , n 6  →n 12  →n 13  are effected for the time announcing mode. Those subroutines are identical to that as shown in FIGS. 4 and 5. 
     In FIG. 12, the timkeeping register (FIG. 2) is additionally provided with a region AP storing AM and PM information, which is connected to a time correction circuit Cu and a decision logic circuit JH determining whether the contents of the storage regions AP, H 2 , and H 1  are &#34;0&#34;. When it is desired to correct time and when the contents of the regions are &#34;0&#34;, i.e. when it is twelve o&#39;clock midnight, only the date information is audibly provided. A buffer CA is provided for keeping output pulses from the divider DV at a fixed interval. 
     Referring to FIG. 13, n 130  is effected to decide whether CA is in the set condition. If one pulse comes from the divider DA, CA is set. After CA is set, the decision circuit JH during n 131  decides whether the contents of the regions AP, H 2  and H 1  assume a specific condition, namely, &#34;0&#34; (the contents &#34;0&#34; of AP imply AM and the contents other than &#34;0&#34; imply PM). When they are &#34;0&#34;, n 131  →n 132  are sequentially effected and when they are not &#34;0&#34;, n 135  →n 136  are effected. 
     n 13  →n 132  are effected at 12 o&#39;clock midnight and when the date is to change, followed by n 132  →n 133  →n 134  for the month/day/day of the week announcing modes. Otherwise, n 131  →n 135  are effected. Each time the divider DV provides a pulse n 135  →n 136  are effected to provide audible sounds indicative of time. When AP, H 2  and H 1  reach &#34;0&#34; with incrementing the counting operation, the date information is audibly indicated through the sequence of n 131  →n 132  →N 133 . This sequence is repeated as long as the time correction circuit Cu is connected across terminals 1 and 3. The terminal 1 is connected to the region H 1  storing the time information, the terminal 2 is connected to an OFF terminal of the time correction circuit Cu, and a terminal 3 is connected to the region M 1  storing the minute information. The counting operation is incremented from the H 1  region to the more significant region by connecting the terminal 1 to the divider DV and from the M 1  region to the upper significant region by connecting the terminal 3 to the divider DV. 
     As stated above, calender information or time information is selected and audibly indicated at any desired point in time so that date or time is recognizable readily without being disturbed by the surrounding brightness. Sound converting means and other circuit constructions may be implemented with LSI technology without replying upon magnetic recording, thereby reducing a space requirement to a minimum. 
     The invention being thus described, it will be obvious that the same may be varied in many ways. Such modifications are not to be regarded as the departure from the spirit and scope of the invention, and all such modifications are intended to be included within the scope of the following claims.