Abstract:
A control circuit of a flyback power converter utilizes at least one of the information of an input voltage and an output voltage of the flyback power converter for adaptively adjusting the minimum on-time of the flyback power converter, to prevent the flyback power converter during light load operation from generating an over output voltage or getting out of control if feedback control is failed.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the priority benefit of Taiwan Patent Application No. 104107445, filed Mar. 9, 2015, the contents of which in its entirety are herein incorporated by reference. 
       FIELD OF THE INVENTION 
       [0002]    The present invention is related generally to a control circuit and method of a flyback power converter and, more particularly, to a circuit and method for adaptively adjusting the minimum on-time of a flyback power converter. 
       BACKGROUND OF THE INVENTION 
       [0003]      FIG. 1  shows a simplified circuitry of a conventional primary-side regulation (PSR) flyback power converter. The flyback power converter converts an alternating-current (AC) power source V AC  into a direct-current (DC) output voltage V OUT .  FIG. 2  is a waveform diagram of the flyback power converter shown in  FIG. 1  during heavy load operation, in which the waveform  20  represents the voltage V WP =V SW −V IN  on a primary-side winding W P , the waveform  22  represents a clamping current I CLAMP , the waveform  24  represents a first voltage V AUX  on an auxiliary winding WA, the waveform  26  represent a second voltage V DET  on a pin DET of a control circuit  10 , the waveform  28  represents the current I SW  that flows through the primary-side winding W P , the waveform  30  represents the current I DO  on a secondary-side winding W S , the waveform  32  represents the current I DAUX  that flows through a diode D AUX , and the waveform  34  represents a switching signal V DRV . Referring to  FIGS. 1 and 2 , a bridge rectifier  12  rectifies the AC power source V AC  to generate the input voltage V IN . (A drain terminal of) A power switch Q 1  is coupled to the primary-side winding W P  of a transformer TX 1  in a serial connection. The control circuit  10  provides the switching signal V DRV  to switch the power switch Q 1 , so that the input voltage VIN can be converted into the output voltage V OUT . Referring to waveforms  20 ,  22 ,  26 ,  28 , and  34  in  FIG. 2 , when the switching signal V DRV  becomes a high level to turn on the power switch Q 1 , the voltage V SW  of the drain terminal of the power switch Q 1  is almost 0. Thus, the voltage V WP  on the primary-side winding W P  of the transformer TX 1  is similar to −V IN . At this time, the current I SW  rises for storing energy. Moreover, in order to prevent the second voltage V DET  on the pin DET of the control circuit  10  from a negative voltage, an internal part of the control circuit  10  will provide the clamping current I CLAMP  to make the voltage V DET  to be held near a level of 0V. Referring to waveforms  20 ,  30 , and  34  in  FIG. 2 , when the switching signal V DRV  becomes a low level to turn off the power switch Q 1 , the current I DO  will be generated on the secondary-side winding W S  to release the energy to a capacitor C O  via an output diode D O  to generate the output voltage V OUT . Whereby, the power switch Q 1  is switched periodically, and the electric energy can be converted into the output voltage V OUT  from the input voltage V IN , so that the function of voltage conversion is achieved. Such PSR flyback power converter utilizes the transformer TX 1  to detect the output voltage V OUT  when the power switch Q 1  is turned off to achieve a feedback control of a constant output voltage. In the feedback control, at a “knee point” as shown by waveform  26  in  FIG. 2 , the pin DET of the control circuit  10  acquires a feedback voltage related to the output voltage V OUT . At the “knee point”, A relationship between the first voltage V AUX  of the auxiliary winding W A  and the voltage V WS  of the secondary-side winding W S  is equal to a turn ratio. Namely, V AUX =V WS ×(N A /N S ). Wherein, N A  is the turn of the auxiliary winding W A , and N S  is the turn of the secondary-side winding W S . Accordingly, the first voltage V AUX  related to the output voltage V OUT  can be acquired via the auxiliary winding WA as shown by waveform  24  in  FIG. 2 . Thence, a voltage divider formed by resistors R 1  and R 2  divides the first voltage V AUX  to generate the second voltage V DET  to the pin DET of the control circuit  10 . The control circuit  10  further samples-and-holds the second voltage V DET  at the “knee point” as the feedback voltage. At the “knee point”, the current I DO  of the secondary-side winding W S  is near 0 A as shown by time t 3  of waveform  30  in  FIG. 2  and a forward voltage V DO  of the output diode D O  is the lowest, so the accuracy of the feedback voltage can be enhanced. In the feedback control of the constant voltage, the control circuit  10  keeps detecting the output voltage V OUT  to adjust a peak current I SWPK  (as shown by waveform  28  in  FIG. 2 ) of the power switch Q 1  (and adjust a switching frequency of the power switch Q 1 ) to hold the output voltage V OUT  quite near a setting value. 
         [0004]      FIG. 3  is a waveform diagram of the flyback power converter shown in  FIG. 1  during light load operation, in which the waveform  40  represents the voltage V WP , the waveform  42  represent the clamping current I CLAMP , the waveform  44  represents the first voltage V AUX , the waveform  46  represents the second voltage V DET , the waveform  48  represents the current I SW , the waveform  50  represents the current I DO , the waveform  52  represents the current I DAUX , and the waveform  54  represents the switching signal V DRV . During light load operation, the peak current I SWPK  or the on-time of the power switch Q 1  is low or short, which easily resulted in a detection error on the feedback voltage. As a result, the feedback control of the output voltage will be failed, and the output voltage will be too high or out of control. Reasons might be as follows:
   (1) Before the secondary-side winding of the transformer TX 1  generates the current I DO  that flows through the output diode D O , the current I SW  of the primary-side winding has to charge a parasitic capacitor C PSW  of the power switch Q 1  and a capacitor C SN  of a buffer  14  to increase the voltages V SW  and V WS  to turn on the diode D O .   (2) When the control circuit  10  is operated, a capacitor C VDD  has to provide a current I DD , so a voltage of the capacitor C VDD  decreases. Thus, before the output diode D O  is turned on, the diode D AUX  will be turned on to generate the current I DAUX  for charging the capacitor C VDD , as shown by waveform  32  in  FIG. 2  and waveform  52  in  FIG. 3 . Aforementioned circumstance is more obvious during light load operation than that during heavy load operation.   (3) There is a parasitic capacitor C PDET  between the pin DET and a ground. The parasitic capacitor C PDET  includes the parasitic capacitor in the control circuit  10  and the parasitic capacitor on a printed circuit board (PCB). The parasitic capacitor C PDET  and the resistors R 1  and R 2  form an RC filter, which causes the waveform of the second voltage V DET  to be distorted and lag behind the first voltage V AUX , as shown by waveforms  44  and  46  in  FIG. 3 .   
 
         [0008]    As described above, during light load operation, the parasitic capacitor C PSW , the capacitor C SN , and the capacitor C VDD  need to be charged. Therefore, a peak current I DOPK  of the output diode D O  will be slightly lower than an ideal value n PS ×I SWPK . Wherein, n PS =N P /N S , and N S  is a turn of the primary-side winding W P . Consequently, the conduction time of the diode D O  is shorter. Moreover, an RC delay effect on the pin DET also makes the second voltage V DET  at the “knee point” to be lower than a correspondent value of the practical output voltage V OUT , which will result in the output voltage V OUT  too high or out of control. Thus, in order to detect the feedback voltage correctly and satisfy the need of input power during light load operation, keeping a minimum conduction time t ON   _   DO   _   MIN  of the output diode that can detect the output voltage V OUT  is a necessary design. In other words, setting a minimum of the conduction time of the power switch Q 1  (i.e. a minimum of the on-time t ON  of the switching signal V DRV ) can keep a proper minimum conduction time t ON   _   DO   _   MIN  of the output diode. The existing method for controlling the minimum conduction time t ON   _   DO   _   MIN  of the output diode is limiting a minimum of the peak of the current I SW  on the primary-side winding L P  of the transformer TX 1 . 
         [0009]      FIG. 4  shows a conventional control circuit  10  for controlling a minimum conduction time t ON   _   DO   _   MIN  of an output diode in the PSR flyback power converter. A switch circuit  60  in the control circuit  10  provides the switching signal V DRV  to control the power switch Q 1 . In the switch circuit  60 , a driver  66  generates the switching signal V DRV  according to a pulse width modulation signal PWM on an output terminal Q of an SR flip-flop  64 . When an oscillator  62  provides a clock CLK to a setting terminal S of the SR flip-flop  64 , the pulse width modulation signal PWM will be triggered as shown by the time t 1  of the waveform  34  in  FIG. 2 . Consequently, the switching signal V DRV  is converted into the high level for turning on the power switch Q 1 . When a resetting terminal of the SR flip-flop  64  receives a resetting signal S RESET , the SR flip-flop  64  ends the pulse width modulation signal PWM as shown by the time t 2  of the waveform  34  in  FIG. 2 . Consequently, the switching signal V DRV  is converted into the low level to turn off the power switch Q 1 . The control circuit in  FIG. 4  further includes a feedback voltage sample-and-hold circuit  74  for receiving the second voltage V DET . As shown by waveforms  26  and  30  in  FIG. 2 , when the power switch Q 1  is turned off and the current I DO  decreases to zero or almost zero, the feedback voltage sample-and-hold circuit  74  will sample-and-hold the second voltage V DET  to generate a feedback voltage V SH   _   DET  related to the output voltage V OUT . An error amplifier and feedback compensation network  76  amplifies a difference between the feedback voltage V SH   _   DET  and a reference voltage V REF  to generate a current threshold V TH   _   CS . A minimum voltage clamping circuit  78  is utilized to limit a minimum V TH   _   CS   _   MIN  of the current threshold V TH   _   CS . Namely, the minimum of the peak of the current I SW  on the primary-side winding W P  is limited. A current peak comparator  72  compares the current threshold V TH   _   CS  with a sensing signal V CS  related to the current I SW  that flows through the primary-side winding W P . When the sensing signal V CS  is higher than the current threshold V TH   _   CS , the current peak comparator  72  sends a comparison signal OC for ending the on-time t ON  of the switching signal V DRV . In order to prevent the pulse width modulation signal PWM from being reset incorrectly in view of an initial voltage spike of the sensing signal V CS  at the moment that the power switch Q 1  is changing from off to on, a leading edge blanking unit  68  will generate a leading edge blanking signal LEB at the moment that the power switch Q 1  is changing from off to on. An AND gate  70  will mask the comparison signal OC by the leading edge blanking signal LEB for a while, thereby generating the resetting signal S RESET . 
         [0010]    From the controlling method as shown in  FIG. 4 , the minimum conduction time 
         [0000]    
       
         
           
             
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         [0000]    of the output diode D O  can be deduced. Wherein, L P  represents an equivalent magnetizing inductance at two terminals of the primary-side winding W P . From the equation, the following questions might be discovered:
   (1) Power converters with different output watts usually need different sensing resistors R CS  serially connected to the power switch Q 1 . However, the minimum V TH   _   CS   _   MIN  of the current threshold V TH   _   CS  is fixed, so the minimum conduction time t ON   _   DO   _   MIN  of the output diodes D O  will be different.   (2) In the same power converter, when the output voltage V OUT  changes, the minimum conduction time t ON   _   DO   _   MIN  will also change; it will not be a fixed value.   (3) The minimum conduction time t ON   _   DO   _   MIN  of the output diode D O  is related to the selected equivalent magnetizing inductance L P  at the two terminals of the primary-side winding W P . The minimum conduction time t ON   _   DO   _   MIN  of the output diode D O  is also related to a variation of the equivalent magnetizing inductance L P  when the power converter is operating or a distribution of the equivalent magnetizing inductance L P  in the time of mass production.
 
Accordingly, in order to cover the variation range of the equivalent magnetizing inductance L P , the output voltage V OUT , and the sensing resistors R CS , the minimum V TH   _   CS   _   MIN  of the current threshold V TH   _   CS  should be higher enough, so that the output voltage V OUT  can be detected successfully during the minimum conduction time t ON   _   DO   _   MIN  of the output diode D O . However, such design might result in the control circuit  10  unfit difficult to adapt to different systems and cause the defects such as the input power during no load operation increasing, the lower loadless switching frequency, or the poorer dynamic load response.
   
 
       SUMMARY OF THE INVENTION 
       [0014]    An objective of the present invention is to provide a control circuit of a flyback power converter for preferably adjusting a minimum on-time of the power switch and a control method thereof. 
         [0015]    Another objective of the present invention is to provide a control circuit and a control method for adaptively adjusting the minimum on-time of the power switch according to at least one of the input voltage and the output voltage. 
         [0016]    According to the present invention, a control circuit of a flyback power converter comprises a switch circuit and a detection circuit. The switch circuit generates a switching signal for controlling the switching of a power switch to make the flyback power converter to convert an input voltage into an output voltage. The detection circuit adjusts a minimum of an on-time of the switching signal according to a second voltage that is in a proportional relationship to a first voltage on an auxiliary winding of a transformer. The detection circuit includes a feedback voltage sample-and-hold circuit configured to operably sample-and-hold the second voltage to generate a feedback voltage related to the output voltage when the power switch is turned off and a current of a secondary-side winding of the transformer decreases to zero or almost zero. The detection circuit further includes a minimum on-time generator configured to operably provide a pulse signal and generate a clamping current related to the input voltage to hold the second voltage at a zero voltage, a voltage closed to zero or a certain constant voltage when the power switch is turned on, wherein a pulse width of the pulse signal is determined by the feedback voltage and the clamping current and the pulse width of the pulse signal decides the minimum. The detection circuit further includes an error amplifier and feedback compensating circuit configured to operably amplify a difference between the feedback voltage and a reference voltage to generate a current threshold. The detection circuit further includes a current peak comparator configured to operably compare the current threshold with a sensing signal related to a current that flows through the primary-side winding to generate a comparison signal to end the on-time of the switching signal when the sensing signal is higher than the current threshold. The detection circuit further includes a signal mask logic circuit configured to operably mask the comparison signal according to the pulse signal to make the on-time of the switching signal to be not lower than the minimum. 
         [0017]    According to the present invention, a control circuit of a flyback power converter comprises a switch circuit and a detection circuit. The switch circuit generates a switching signal for controlling the switching of a power switch to make the flyback power converter to convert an input voltage into an output voltage. The detection circuit adjusts a minimum of an on-time of the switching signal according to a second voltage that is in a proportional relationship to a first voltage on an auxiliary winding of a transformer. The detection circuit includes a feedback voltage sample-and-hold circuit configured to operably sample-and-hold the second voltage to generate a feedback voltage related to the output voltage when the power switch is turned off and the current on the secondary-side winding of the transformer decreases to zero or almost zero. The detection circuit further includes a minimum on-time generator configured to operably provide a pulse signal and determine a pulse width of the pulse signal according to the feedback voltage, wherein the pulse width of the pulse signal decides the minimum. The detection circuit further includes an error amplifier and feedback compensating circuit configured to operably amplify a difference between the feedback voltage and a reference voltage to generate a current threshold. The detection circuit further includes a current peak comparator configured to operably compare the current threshold with a sensing signal related to a current that flows through the primary-side winding of the transformer to generate a comparison signal to end the on-time of the switching signal when the sensing signal is higher than the current threshold. The detection circuit further includes a signal mask logic circuit coupled to the minimum on-time generator and the current peak comparator, configured to operably mask the comparison signal according to the pulse signal to make the on-time of the switching signal to be not lower than the minimum. 
         [0018]    According to the present invention, a control circuit of a flyback power converter comprises a switch circuit and a detection circuit. The switch circuit generates a switching signal for controlling the switching of a power switch to make the flyback power converter to convert an input voltage into an output voltage. The detection circuit adjusts a minimum of an on-time of the switching signal according to a second voltage that is in a proportional relationship to a first voltage on an auxiliary winding of a transformer. The detection circuit includes a minimum on-time generator configured to operably provide a pulse signal and generate a clamping current related to the input voltage when the power switch is turned on to hold the second voltage at a zero voltage, a voltage closed to zero or a certain constant voltage, wherein a pulse width of the pulse signal is determined by the clamping current and the pulse width of the pulse signal decides the minimum. The detection circuit further includes a feedback voltage sample-and-hold circuit configured to operably sample-and-hold the second voltage to generate a feedback voltage related to the output voltage when the power switch is turned off and the current on the secondary-side winding of the transformer decreases to zero or almost zero. The detection circuit further includes an error amplifier and feedback compensating circuit configured to operably amplify a difference between the feedback voltage and a reference voltage to generate a current threshold. The detection circuit further includes a current peak comparator configured to operably comparing the current threshold with a sensing signal related to a current that flows through the primary-side winding to generate a comparison signal to end the on-time of the switching signal when the sensing signal is higher than the current threshold. The detection circuit further includes a signal mask logic circuit configured to operably mask the comparison signal according to the pulse signal to make the on-time of the switching signal to be not lower than the minimum. 
         [0019]    According to the present invention, a controlling method for a flyback power converter comprises the steps of: generating a switching signal for controlling a switching of a power switch to make the flyback power converter to convert an input voltage into an output voltage, wherein during an on-time of the switching signal, the power switch will be turned on, and during an off-time of the switching signal, the power switch will be turned off; and adjusting a minimum of the on-time of the switching signal according to a second voltage that is in a proportional relationship to a first voltage on an auxiliary winding of a transformer. The step of adjusting the minimum according to the second voltage includes the steps of: sampling-and-holding the second voltage to generate a feedback voltage related to the output voltage when the power switch is turned off and the current on the secondary-side winding of the transformer decreases to zero or almost zero; generating a clamping current related to the input voltage to hold the second voltage at a zero voltage, a voltage closed to zero or a certain constant voltage when the power switch is turned on; providing a pulse signal, wherein a pulse width of the pulse signal is determined by the feedback voltage and the clamping current and the pulse width of the pulse signal determines the minimum; amplifying a difference between the feedback voltage and a reference voltage to generate a current threshold; comparing the current threshold with a sensing signal related to a current that flows through the primary-side winding to generate a comparison signal to end the on-time of the switching signal when the sensing signal is higher than the current threshold; and masking the comparison signal by the pulse signal to make the on-time of the switching signal to be not lower than the minimum. 
         [0020]    According to the present invention, a controlling method for a flyback power converter comprises the steps of: generating a switching signal for controlling a switching of a power switch to make the flyback power converter to convert an input voltage into an output voltage, wherein during an on-time of the switching signal, the power switch will be turned on, and during an off-time of the switching signal, the power switch will be turned off; and adjusting a minimum of an on-time of the switching signal according to a second voltage that is in a proportional relationship to a first voltage on an auxiliary winding of a transformer. The step of adjusting the minimum according to the second voltage includes the steps of: sampling-and-holding the second voltage to generate a feedback voltage related to the output voltage when the power switch is turned off and the current on the secondary-side winding of the transformer decreases to zero or almost zero; providing a pulse signal, wherein a pulse width of the pulse signal is determined by the feedback voltage and the pulse width of the pulse signal determines the minimum; amplifying a difference between the feedback voltage and a reference voltage to generate a current threshold; comparing the current threshold with a sensing signal related to a current that flows through the primary-side winding of the transformer to generate a comparison signal to end the on-time of the switching signal when the sensing signal is higher than the current threshold; and masking the comparison signal by the pulse signal to make the on-time of the switching signal to be not lower than the minimum. 
         [0021]    According to the present invention, a controlling method for a flyback power converter comprises the steps of: generating a switching signal for controlling a switching of a power switch to make the flyback power converter to convert an input voltage into an output voltage, wherein during an on-time of the switching signal, the power switch will be turned on, and during an off-time of the switching signal, the power switch will be turned off; and adjusting a minimum of an on-time of the switching signal according to a second voltage that is in a proportional relationship to a first voltage on an auxiliary winding of a transformer. The step of adjusting the minimum according to the second voltage includes the steps of: generating a clamping current related to the input voltage to hold the second voltage at a zero voltage, a voltage closed to zero or a certain constant voltage when the power switch is turned on; providing a pulse signal, wherein a pulse width of the pulse signal is determined by the clamping current and the pulse width of the pulse signal determines the minimum; sampling-and-holding the second voltage when the power switch is turned off and the current on the secondary-side winding of the transformer decreases to zero or almost zero to generate a feedback voltage related to the output voltage; amplifying a difference between the feedback voltage and a reference voltage to generate a current threshold; comparing the current threshold with a sensing signal related to a current that flows through the primary-side winding of the transformer to generating a comparison signal to end the on-time of the switching signal when the sensing signal is higher than the current threshold; and masking the comparison signal by the pulse signal to make the on-time of the switching signal to be not lower than the minimum. 
     
    
     
       BRIE DESCRIPTION OF THE DRAWINGS 
         [0022]    These and other objectives, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments according to the present invention taken in conjunction with the accompanying drawings, in which: 
           [0023]      FIG. 1  shows a simplified circuitry of a primary-side regulation flyback power converter; 
           [0024]      FIG. 2  is a waveform diagram of the flyback power converter shown in  FIG. 1  during heavy load operation; 
           [0025]      FIG. 3  is a waveform diagram of the flyback power converter shown in  FIG. 1  during light load operation; 
           [0026]      FIG. 4  is a conventional control circuit for controlling the minimum conduction time of the output diode of the flyback power converter shown in  FIG. 1 ; 
           [0027]      FIG. 5  shows a first embodiment of a control circuit according to the present invention; 
           [0028]      FIG. 6  shows an embodiment of the minimum on-time generator shown in  FIG. 5 ; 
           [0029]      FIG. 7  shows another embodiment of the minimum on-time generator shown in  FIG. 5 ; 
           [0030]      FIG. 8  shows a second embodiment of a control circuit according to the present invention; 
           [0031]      FIG. 9  shows an embodiment of the minimum on-time generator shown in  FIG. 8 ; 
           [0032]      FIG. 10  shows another embodiment of the minimum on-time generator shown in  FIG. 8 ; 
           [0033]      FIG. 11  shows a third embodiment of a control circuit according to the present invention; and 
           [0034]      FIG. 12  shows an embodiment of the minimum on-time generator shown in  FIG. 11 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0035]      FIG. 5  shows a first embodiment of a control circuit  10  according to the present invention. In this embodiment, a switch circuit  60  provides a switching signal V DRV  to control the switching of a power switch Q 1 . A detection circuit  80  acquires information of an input voltage and information of an output voltage from a second voltage V DET  to adaptively adjust a minimum t ON   _   MIN  of an on-time t ON  of the switching signal V DRV . Accordingly, the minimum t ON   _   MIN  will increase when the output voltage V OUT  increases, and decrease when the input voltage V IN  increases. Referring to  FIGS. 1 and 5 , an auxiliary winding W A  of a transformer TX 1  generates a first voltage V AUX  in response to the switching of the power switch Q 1 . A voltage divider formed by resistors R 1  and R 2  divides the first voltage V AUX  to generate the second voltage V DET . The switch circuit  60  includes an oscillator  62 , an SR flip-flop  64  and a driver  66 . The oscillator  62  provides a clock CLK to a setting terminal S of the SR flip-flop  64  for triggering a pulse width modulation signal PWM. When a resetting terminal R of the SR flip-flop  64  receives a resetting signal S RESET , the SR flip-flop  64  will end the pulse width modulation signal PWM. The driver  66  generates the switching signal V DRV  according to the pulse width modulation signal PWM on an output terminal Q of the SR flip-flop  64 . 
         [0036]    The detection circuit  80  in  FIG. 5  includes a current peak comparator  72 , a feedback voltage sample-and-hold circuit  74 , an error amplifier and feedback compensating circuit  76 , a minimum on-time generator  82 , and a signal mask logic circuit  84 . After the power switch Q 1  is turned off over a preset time, the feedback voltage sample-and-hold circuit  74  samples-and-holds the second voltage V DET  to generate the feedback voltage V SH   _   DET  related to the output voltage V OUT . Wherein, the preset time is lower than or equal to a conduction time t ON   _   DO  of a diode D O . Preferably, when a current I DO  on a secondary-side winding W S  of the transformer TX 1  decreases to zero or almost zero as shown by time t 3  in  FIG. 2 , the second voltage V DET  will be sampled-and-held to generate the feedback voltage V SH   _   DET  related to the output voltage V OUT . The error amplifier and feedback compensating circuit  76  amplifies a difference between the feedback voltage V SH   _   DET  and a reference V REF  to generate a current threshold V TH   _   CS  for determining a peak I SWPK  of a current I SW  on a primary-side winding W P  of the transformer TX 1 . The current peak comparator  72  compares the current threshold V TH   _   CS  with a sensing signal V CS  related to the current I SW . When the sensing signal V CS  is higher than the current threshold V TH   _   CS , the current peak comparator  72  will generate a comparison signal OC of a high level to end the on-time t ON  of the switching signal V DRV . The minimum on-time generator  82  receives the feedback voltage V SH   _   DET  from the feedback voltage sample-and-hold circuit  74  and the pulse width modulation signal PWM from the switch circuit  60  and provides a pulse signal MINTON. When the power switch Q 1  is turned on, the minimum on-time generator  82  generates a clamping current I CLAMP  related to the input voltage V IN  to make the second voltage V DET  to be held at a zero voltage, a voltage closed to zero or a certain constant voltage. Wherein a pulse width of the pulse signal MINTON is determined by the feedback voltage V SH   _   DET  and the clamping current I CLAMP , and the pulse width of the pulse signal MINTON determines the minimum t ON   _   MIN  of the on-time of the switching signal V DRV . The signal mask logic circuit  84  includes a flip-flop  86  and an AND gate  88 . The signal mask logic circuit  84  masks the comparison signal OC according to the pulse signal MINTON to make the on-time t ON  of the switching signal V DRV  to be not lower than the minimum t ON   _   MIN . In this embodiment, when the pulse width modulation signal PWM is converted into the high level, the pulse signal MINTON is also converted to the high level and held for a time t ON   _   MIN . When the pulse signal MINTON is at the high level, the AND gate  88  will not send the resetting signal S RESET  even if the comparison signal OC becomes the high level. The AND gate  88  will not send the resetting signal S RESET  until the pulse signal MINTON is ended. Therefore, the on-time t ON  of the switching signal V DRV  has a minimum t ON   _   MIN . 
         [0037]      FIG. 6  shows an embodiment of the minimum on-time generator  82 , which includes a minimum voltage clamping circuit  90 , a current mirror  94 , a pulse generator  96 , and a threshold generator  98 . When the power switch Q 1  is turned on, the first voltage V AUX  on the auxiliary winding W A  is a negative voltage, as shown by waveform  24  in  FIG. 2 . When the minimum voltage clamping circuit  90  detects the second voltage V DET  that is slightly lower than 0V, an operation amplifier  92  in the minimum voltage clamping circuit  90  will control a transistor M 1  to adaptively generate a clamping current I CLAMP  to hold the second voltage V DET  at the zero voltage. Wherein, the clamping current I CLAMP  equals to (n AP ×V IN )/R 2 , n AP  represents a turn ratio of primary-side winding W P  and the auxiliary winding WA. Herein, the turn ratio n AP  and the resistor R 2  are both fixed values. Thus, the clamping current I CLAMP  is direct proportional to the input voltage V IN . In other embodiments, the minimum voltage clamping circuit  90  can also hold the second voltage V DET  at a preset voltage that is not zero. The current mirror  94  mirrors the clamping current I CLAMP  to generate a mirror current I VIN =k 1 ×I CLAMP  which is direct proportional to the input voltage V IN , wherein k 1  is a constant. The threshold generator  98  includes an attenuator or amplifier  106  and an adder  108 . The attenuator or amplifier receives the feedback voltage V SH   _   DET  and attenuates or amplifies the feedback voltage with a preset proportion k 2  to generate a third voltage V_k 2 . If the preset proportion k 2  is 1, the attenuator or amplifier  106  will be omitted. The adder  108  will add up the third voltage V_k 2  and a reference voltage V 1  to generate the minimum on-time threshold V TH   _   MINTON  related to the output voltage V OUT . If the reference voltage V 1  is 0, the adder  108  can be omitted. The pulse generator  96  includes a capacitor Cr coupled to the current mirror  94 , a charge and discharge switch Q 2  coupled to the capacitor Cr in a parallel connection, an inverter  100  for inverting the pulse width modulation signal PWM to generate a signal to control the charge and discharge switch Q 2 , a minimum on-time comparator  102 , and an AND gate  104 . Before the on-time of the switching signal V DRV  starts (or during the off-time), the pulse width modulation signal PWM is at the low level. Thus, the charge and discharge switch Q 2  will be turned on to make the capacitor Cr to be discharged. At this time, a voltage V RAMP  of the capacitor Cr will be reset. During the on-time of the switching signal V DRV , the pulse width modulation signal PWM is at the high level. Thus, the charge and discharge switch Q 2  will be turned off, so that the mirror current I VIN  charges the capacitor Cr to increase the voltage V RAMP  of the capacitor Cr. At this time, the voltage V RAMP  of the capacitor Cr is lower than the minimum on-time threshold V TH   _   MINTON , so the minimum on-time comparator  102  outputs a signal of the high level. Simultaneously, the pulse width modulation signal PWM is also at the high level, so the AND gate  104  will output the pulse signal MINTON of the high level to the signal mask logic circuit  84  to mask the comparison signal OC. When the voltage VAMP of the capacitor Cr equals to or higher than the minimum on-time threshold V TH   _   MINTON , the output of the minimum on-time comparator  102  becomes the low level to end the pulse signal MINTON. At this time, the comparison signal OC will decide whether to trigger the resetting signal S RESET  for resetting the pulse width modulation signal PWM. 
         [0038]    In  FIGS. 5 and 6 , the pulse width of the pulse signal MINTON determines the minimum t ON   _   MIN  of the on-time t ON  of the switching signal V DRV , i.e. the minimum on-time of the power switch Q 1 . The pulse width (t ON   _   MIN ) of the pulse signal MINTON is determined by the mirror current I VIN  and the minimum on-time threshold V TH   _   MINTON . Thus, the following equation can be obtained: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       t 
                       ON_MIN 
                     
                     = 
                     
                       
                         
                           Cr 
                           · 
                           
                             V 
                             TH_MINTON 
                           
                         
                         
                           
                             k 
                              
                             
                                 
                             
                              
                             
                               1 
                               · 
                               
                                 n 
                                 AP 
                               
                               · 
                               
                                 V 
                                 IN 
                               
                             
                           
                           
                             R 
                              
                             
                                 
                             
                              
                             2 
                           
                         
                       
                       = 
                       
                         
                           
                             Cr 
                             
                               k 
                                
                               
                                   
                               
                                
                               1 
                             
                           
                           · 
                           
                             
                               
                                 
                                   
                                     ( 
                                     
                                       
                                         V 
                                         OUT 
                                       
                                       + 
                                       
                                         V 
                                         DO 
                                       
                                     
                                     ) 
                                   
                                   · 
                                   k 
                                 
                                  
                                 
                                     
                                 
                                  
                                 2 
                               
                               + 
                               
                                 V 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                             
                               V 
                               IN 
                             
                           
                           · 
                           
                             n 
                             PS 
                           
                           · 
                           R 
                         
                          
                         
                             
                         
                          
                         
                           2 
                           · 
                           
                             
                               R 
                                
                               
                                   
                               
                                
                               1 
                             
                             
                               
                                 R 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                               + 
                               
                                 R 
                                  
                                 
                                     
                                 
                                  
                                 2 
                               
                             
                           
                         
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   
                     EQ 
                      
                     
                       - 
                     
                      
                     1 
                   
                   ) 
                 
               
             
           
         
       
     
         [0000]    which shows that the minimum t ON   _   MIN  of the on-time tot is modulated by the sum V OUT +V DO . Accordingly, the minimum t ON   _   MIN  will increase when the output voltage V OUT  increases. When the reference voltage V 1  is 0V, the minimum t ON   _   MIN  is direct proportional to the sum V OUT +V DO . Obviously, when related parameters are set properly, the minimum conduction time t ON   _   DO   _   MIN  that is appropriate and almost constant or changing within a small range can be obtained. The equation is as follows: 
         [0000]    
       
         
           
             
               
                 t 
                 ON_MIN 
               
               = 
               
                 
                   
                     
                       n 
                       PS 
                     
                     · 
                     
                       ( 
                       
                         
                           V 
                           OUT 
                         
                         + 
                         
                           V 
                           DO 
                         
                       
                       ) 
                     
                   
                   
                     V 
                     IN 
                   
                 
                 · 
                 
                   t 
                   
                     ON_DO 
                      
                     _MIN 
                   
                 
               
             
             , 
           
         
       
     
         [0000]    which shows that the minimum t ON   _   MIN  will increase when the value V OUT +V DO  increases, and decreases when V IN  increases. Thus, if the system adjusts the minimum t ON   _   MIN  and the ratio 
         [0000]    
       
         
           
             
               ( 
               
                 
                   V 
                   OUT 
                 
                 + 
                 
                   V 
                   DO 
                 
               
               ) 
             
             
               V 
               IN 
             
           
         
       
     
         [0000]    as being direct proportional to each other, then the minimum conduction time t ON   _   DO   _   MIN  of the output diode will be held in a constant value or changed within a small range. Accordingly, the minimum conduction time t ON   _   DO   _   MIN  of the diode D O  of the flyback power converter which is using the control circuit  10  of the present invention can be held at a constant value or changed within a small range when the output voltage V OUT  and the input voltage V IN  are changed. Thus, the feedback voltage V SH   _   DET  related to the output voltage V OUT  can be detected correctly. Moreover, when the output watt of the power converter is changed to make the sensing resistor R CS  to be changed, the minimum conduction time t ON   _   DO   _   MIN  of the output diode D O  can be held the same and does not need to redesign. Further, the minimum conduction time t ON   _   DO   _   MIN  of the output diode D O  is independent of an equivalent magnetizing inductance L P  at two terminals of the primary-side winding W P . The minimum conduction time t ON   _   DO   _   MIN  of the output diode D O  is also independent of the variation of the equivalent magnetizing inductance L P  when the power converter is operating or the distribution of the equivalent magnetizing inductance L P  in the time of mass production. 
         [0039]      FIG. 7  shows another embodiment of the minimum on-time generator  82  in  FIG. 7 . This embodiment includes the same minimum voltage clamping circuit  90 , current mirror  94 , and pulse generator  96 . Differently, the minimum on-time generator  82  in  FIG. 7  omits the threshold generator  98 . In this embodiment, the feedback voltage V SH   _   DET  is directly provided to the minimum on-time comparator  102  in the pulse generator  96 . When the voltage V RAMP  of the capacitor Cr is lower than the feedback voltage V SH   _   DET , the minimum on-time comparator  102  will output a signal of the high level. 
         [0040]    The embodiments in  FIGS. 5, 6, and 7  are applied to the situation that both the input voltage VIN and the output voltage V OUT  will change. In some applications, there is also a situation that the input voltage VIN or the output voltage V OUT  is a fixed value. Herein, the control circuit  10  of the present invention can be adjusted properly. 
         [0041]      FIG. 8  shows a second embodiment of the control circuit  10  according to the present invention. This embodiment is applied to the situation that the input voltage V IN  is fixed. The control circuit  10  in  FIG. 8  is the same as that in  FIG. 5 . The control circuit  10  in  FIG. 8  includes the switch circuit  60  for providing a switching signal V DRV  to control the switching of the power switch Q 1 . However, the detection circuit  80  of the control circuit  10  in  FIG. 8  merely acquires information of the output voltage from the second voltage V DET  to adaptively adjust the minimum t ON   _   MIN  of the on-time t ON  of the switching signal V DRV . Thus, the minimum t ON   _   MIN  will increases when the output voltage V OUT  increases. The detection circuit  80  of  FIG. 8  is the same as that of  FIG. 5 , which includes the current peak comparator  72 , the feedback voltage sample-and-hold circuit  74 , the error amplifier and feedback compensating circuit  76 , the minimum on-time generator  82  and the signal mask logic circuit  84 . The operation of the circuits in this embodiment are the same as those in the embodiment of  FIG. 5  except for the minimum on-time generator  82  which determines the pulse width of the pulse signal MINTON according to the feedback voltage V SH   _   DET .  FIG. 9  shows an embodiment of the minimum on-time generator  82  in  FIG. 8 . The minimum on-time generator  82  in  FIG. 9  includes a pulse generator  96 , a threshold generator  98 , and a constant current source  110 . In  FIG. 9 , the operation of pulse generator  96  and the threshold generator  98  are the same as that in  FIG. 6 . However, the circuit in  FIG. 9  utilizes the constant current source  110  to provide a constant current I CON  for charging the capacitor Cr. Namely, a rising speed of the voltage V RAMP  of the capacitor Cr is fixed. Therefore, the pulse width of the pulse signal MINTON is only controlled by the minimum on-time threshold V TH   _   MINTON . In other words, the pulse width of the pulse signal MINTON is only related to the feedback voltage V SH   _   DET . Referring to the equation EQ-2, the minimum t ON   _   MIN  of the on-time t ON  of the switching signal V DRV  will increase when the value V OUT +V DO  increases, so the minimum conduction time t ON   _   DO   _   MIN  of the output diode can be held in a constant value or changed within a small range. Consequently, the feedback voltage V SH   _   DET  related to the output voltage V OUT  can be detected correctly. Moreover, when the output watt of the power converter is changing to make the sensing resistor R CS  to be changed, the minimum conduction time t ON   _   DO   _   MIN  of the output diode D O  can be held the same and does not need to redesign. Further, the minimum conduction time t ON   _   DO   _   MIN  of the output diode D O  is independent of an equivalent magnetizing inductance L P  at two terminals of the primary-side winding W P . The minimum conduction time t ON   _   DO   _   MIN  of the output diode D O  is also independent of the variation of the equivalent magnetizing inductance L P  or the distribution of the equivalent magnetizing inductance L P  in the time of mass production. 
         [0042]      FIG. 10  shows another embodiment of the minimum on-time generator  82  in  FIG. 8 , which includes the pulse generator  96  and the constant current source  110 . The minimum on-time generator  82  in  FIG. 10  omits the threshold generator  98 . In this embodiment, the feedback voltage V SH   _   DET  is directly provided to the minimum on-time comparator  102  in the pulse generator  96 . When the voltage V RAMP  of the capacitor Cr is lower than the feedback voltage V SH   _   DET , the minimum on-time comparator  102  will output a signal of the high level. 
         [0043]      FIG. 11  shows a third embodiment of the control circuit  10  according to the present invention. This embodiment is applied to the situation that the output voltage V OUT  is fixed. The control circuit  10  depicted in  FIG. 11  includes the same switch circuit  60  as that depicted in  FIG. 6  for providing a switching signal V DRV  to control the switching of the power switch Q 1 . However, the detection circuit  80  of the control circuit  10  depicted in  FIG. 11  adjusts the minimum t ON   _   MIN  of the on-time t ON  of the switching signal V DRV  according to the information of the input voltage V IN . Accordingly, the minimum t ON   _   MIN  will decrease when the input voltage V IN  increases. The detection circuit  80  depicted in  FIG. 11  includes the same circuitry as that depicted in  FIG. 5 . The detection circuit  80  depicted in  FIG. 11  includes the current peak comparator  72 , the feedback voltage sample-and-hold circuit  74 , the error amplifier and feedback compensating circuit  76 , the minimum on-time generator  82 , and the signal mask logic circuit  84 . The operation of the circuits in this embodiment are the same as those in  FIG. 5  except for the minimum on-time generator  82  which does not receive the feedback voltage V SH   _   DET  to determine the pulse width of the pulse signal MINTON.  FIG. 12  shows an embodiment of the minimum on-time generator  82  depicted in  FIG. 11 , which includes the minimum voltage clamping circuit  90 , the current mirror  94 , the pulse generator  96 , and the constant voltage source  112 . The operations of the minimum voltage clamping circuit  90 , the current mirror  94 , and the pulse generator  96  are the same as those depicted in  FIG. 6 . Differently, the embodiment shown in  FIG. 12  utilizes the constant voltage source  112  to provide a fixed threshold V TH   _   CON  as the minimum on-time threshold. Thus, the pulse width of the pulse signal MINTON is only controlled by the mirror current I VIN . Namely, the pulse width of the pulse signal MINTON is only related to the input voltage V IN . Referring to the equation EQ-2, the minimum t ON   _   MIN  of the on-time t ON  of the switching signal V DRV  will decrease when V IN  increases, so the minimum conduction time t ON   _   DO   _   MIN  of the output diode can be held in a constant value or changed within a small range. Consequently, the feedback voltage V SH   _   DET  related to the output voltage V OUT  can be detected correctly. Moreover, when the output watt of the power converter is changing to make the sensing resistor R CS  to be changed, the minimum conduction time t ON   _   DO   _   MIN  of the output diode D O  can be held the same and does not need to redesign. Further, the minimum conduction time to t ON   _   DO   _   MIN  of the output diode D O  is independent of an equivalent magnetizing inductance L P  at two terminals of the primary-side winding W P . The minimum conduction time t ON   _   DO   _   MIN  of the output diode D O  is also independent of the variation of the equivalent magnetizing inductance L P  or the distribution of the equivalent magnetizing inductance L P  in the time of mass production. 
         [0044]    While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.