Abstract:
An input signal is pre-distorted to reduce distortion resulting from subsequent signal amplification. Frequency-dependent pre-distortion is preferably implemented in combination with frequency-independent pre-distortion, where the frequency-dependent pre-distortion is generated by expanding the derivative of a product of a pre-distortion function and the input signal and then relaxing constraints on the pre-distortion function and/or on frequency-dependent filtering associated with the frequency-dependent pre-distortion. In one implementation, four different frequency-dependent pre-distortion signals are generated for the expansion using up to four different pre-distortion functions and up to four different frequency-dependent filters.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of the filing date of U.S. provisional application No. 61/485,143, filed on May 12, 2011, the teachings of which are incorporated herein by reference in their entirety. 
     The subject matter of this application is related to the subject matter of U.S. Pat. No. 7,251,293, the teachings of which are incorporated herein by reference in their entirety. 
    
    
     BACKGROUND 
     1. Field of the Invention 
     The present invention relates to signal processing and, more specifically but not exclusively, to linearizing non-linear systems, such as non-linear amplifiers, using digital pre-distortion. 
     2. Description of the Related Art 
     Introduction 
     This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art. 
       FIG. 1  shows a schematic block diagram of signal-processing system  100 , which implements a conventional linearization scheme that employs digital pre-distortion to linearize an analog sub-system  130  having a non-linear amplifier  134 . Signal-processing system  100  receives a digital input signal x[n] and generates a linearized, amplified, analog output signal y amp (t). 
     In particular, the digital (e.g., baseband or IF (intermediate frequency)) input signal x[n] is processed by digital pre-distortion (DPD) module  114  to yield a pre-distorted digital signal x pd [n], which is converted into an analog pre-distorted signal x pd (t) using a digital-to-analog converter (DAC)  120 . The output of the DAC is frequency converted to a desired frequency (e.g., RF (radio frequency)) using upconverter  132  to yield an RF analog pre-distorted signal x pd     —     rf (t)=Re{x pd (t)e jw     c     t }. The RF signal x pd     —     rf (t) is amplified by non-linear amplifier  134  to yield the output signal y amp (t). 
     Purpose of Digital Pre-Distortion 
     The purpose of the digital pre-distortion in signal-processing system  100  is to ensure that the output signal y amp (t) is close to a linear scaled version of the (theoretical) analog version x(t) of the digital input signal x[n]. That is, y amp (t)≅Gx(t), where G is a constant. Note that, in the above notation, the digital signal x[n] is a sampled version of the analog signal x(t). 
     Computation of the Digital Pre-Distortion Function 
     In a typical implementation, a small portion of the amplifier output signal y amp (t) is removed at tap  140  and mixed down to a suitable intermediate frequency (IF) (or, alternatively, to baseband) using a downconverter  150 . The resulting downconverted feedback signal y fb (t) is digitized using an analog-to-digital (ADC) converter  160  to yield digital feedback signal y fb [n]. 
     The digital pre-distortion function implemented by module  114  is initially computed and subsequently adaptively updated by comparing the input signal x[n] with the feedback signal y fb [n] using a controller (not shown in  FIG. 1 ) that may be implemented as part of or separate from DPD module  114 . The computation can be performed in one of (at least) the following two ways: 
     1) In a non-real-time implementation, a block of samples of the input signal x[n] and a block of samples of the feedback signal y fb [n] are captured and processed by the controller offline to estimate the pre-distortion function. Such estimation is typically performed in a DSP (digital signal processor) or microcontroller. 
     2) In a real-time implementation, the pre-distortion function is updated by the controller on a sample-by-sample basis using an adaptive non-linear filter structure. 
     Pre-Processing 
     In both cases, one or both of the signals x[n] and y fb [n] are pre-processed before the controller estimates the pre-distortion function. The pre-processing aligns the delays, gains, and phases of the two signals. Mathematically, this can be described as follows: 
     Estimate the delay τ and the complex gain α that minimizes the cost function:
 
E{(x[n−τ]−αy fb [n]) 2 },
 
where E{·} denotes the expectation value operator (or average). In the non-real-time implementation, minimizing the cost function reduces to estimating values for the delay τ and the complex gain α that minimize the cost function in the least-squares sense. Note that the delay τ and the complex gain α can be estimated successively and/or jointly. Also, note that the delay τ can be a fractional delay. Techniques for least-squares estimation are well-known. See, for example, W. H. Press, B. P. Flannery, S. A. Teukolsky, and W. T. Vetterling,  Numerical Recipes: The Art of Scientific Computing  (New York: Cambridge University Press, 1986), the teachings of which are incorporated herein by reference.
 
     Digital Pre-Distortion Function 
     After the pre-processing, the digital pre-distortion can be described as estimating the arbitrary non-linear function ƒ pd (·) that minimizes the cost function:
 
E{(ƒ pd (x[n−τ],x[n−τ−1],x[n−τ+1], . . . )−αy fb [n]) 2 }.  (1)
 
     Limitations of Prior Art 
       FIG. 2 , which corresponds to FIG. 5 of U.S. Pat. No. 7,251,293, shows a block diagram of a digital pre-distortion architecture corresponding to the following Equation (2): 
                         x   pd     ⁡     [     n   ′     ]       =           f   0     ⁡     (     a   ⁡     [   n   ]       )       ·     x   ⁡     [     n   -     d   0       ]         +       (         f   1     ⁡     (     a   ⁡     [   n   ]       )       ·     x   ⁡     [     n   -     d   0       ]         )     *       h   d     ⁡     [   n   ]       *       h   P     ⁡     [   n   ]             ,       +     (         f   2     ⁡     (     a   ⁡     [   n   ]       )       ·     x   ⁡     [     n   -     d   0       ]         )       *       h   d     ⁡     [   n   ]       *       h   N     ⁡     [   n   ]                 (   2   )               
where:
 
     Complex input signal x[n]=I+jQ; 
     Complex pre-distorted signal x pd [n′]=I′+jQ′ is the n′-th output sample corresponding to n-th input sample; 
     Input signal power a[n]=∥x[n]∥ 2 =I 2 +Q 2  generated by power detector  502  of  FIG. 2 , 
     Delay d 0  is a synchronization delay applied by Delay — 0 block  504  of  FIG. 2  to compensate for the processing delay of power detector  502 ; 
     x[n−d 0 ] is the delayed input signal generated by Delay — 0 block  504 ; 
     Delay d 1  is a synchronization delay applied by Delay — 1 block  510  of  FIG. 2  to compensate for the processing delays of filters  518 ,  520 ,  526 , and  528 . Note that the use of sample index n′ in the output sample x pd [n′] represents the effect of delays d 0  and d 1 ; 
     ƒ 0 (·), ƒ 1 (·), ƒ 2 (·) are (possibly non-linear) polynomial functions of the input signal power a[n] and are represented by Lookup Table #0  506 , Lookup Table #1  514 , and Lookup Table #2  522  of  FIG. 2 , respectively; 
     h d [·] is the impulse response of each differentiator filter  518  and  526  of  FIG. 2 ; 
     h P [·],h N [·] are the impulse responses of positive and negative Hilbert filters  520  and  528  of  FIG. 2  for selecting the positive and negative frequencies, respectively; 
     “·” represents the complex multiplication operator of complex multipliers  508 ,  516 , and  524  of  FIG. 2 ; 
     “*” is the convolution operator, with x[n]*h[n] representing the output of filter h corresponding to the nth input sample x[n]; and 
     Summation block  512  of  FIG. 2  represents the addition operations in Equation (2). 
     Pre-distortion architectures such as those shown in  FIG. 2  do not provide adequate linearization for certain amplifier designs under some specific signaling conditions. An example is pre-distortion with extremely wideband signals and Doherty amplifiers. 
     SUMMARY 
     In one embodiment, the present invention is a method for reducing distortion in an output signal by applying pre-distortion to an input signal to generate a pre-distorted signal, such that, when the pre-distorted signal is applied to a non-linear system to generate the output signal, the pre-distortion reduces the distortion in the output signal. The pre-distorted signal is generated by (a) generating a first frequency-dependent pre-distortion signal corresponding to a product of (i) a derivative of a first pre-distortion function and (ii) the input signal; (b) generating a second frequency-dependent pre-distortion signal corresponding to a product of (i) a derivative of a second pre-distortion function and (ii) the input signal; (c) generating a third frequency-dependent pre-distortion signal corresponding to a product of (i) a third pre-distortion function and (ii) a derivative of the input signal; (d) generating a fourth frequency-dependent pre-distortion signal corresponding to a product of (i) a fourth pre-distortion function and (ii) a derivative of the input signal; and (e) generating the pre-distorted signal based on the first, second, third, and fourth frequency-dependent pre-distortion signals. 
     In another embodiment, the present invention is an apparatus for reducing distortion in an output signal by applying pre-distortion to an input signal to generate a pre-distorted signal, such that, when the pre-distorted signal is applied to a non-linear system to generate the output signal, the pre-distortion reduces the distortion in the output signal. The apparatus comprises first, second, third, and fourth signal paths and a summer. The first signal path is configured to generate a first frequency-dependent pre-distortion signal corresponding to a product of (i) a derivative of a first pre-distortion function and (ii) the input signal. The second signal path is configured to generate a second frequency-dependent pre-distortion signal corresponding to a product of (i) a derivative of a second pre-distortion function and (ii) the input signal. The third signal path is configured to generate a third frequency-dependent pre-distortion signal corresponding to a product of (i) a third pre-distortion function and (ii) a derivative of the input signal. The fourth signal path is configured to generate a fourth frequency-dependent pre-distortion signal corresponding to a product of (i) a fourth pre-distortion function and (ii) a derivative of the input signal. The summer is configured to generate the pre-distorted signal based on the first, second, third, and fourth frequency-dependent pre-distortion signals. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Other aspects, features, and advantages of the present invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements. 
         FIG. 1  shows a schematic block diagram of a signal-processing system that implements a conventional linearization scheme that employs digital pre-distortion to linearize a non-linear sub-system having a non-linear amplifier; 
         FIG. 2  shows a block diagram of a prior-art digital pre-distortion architecture; and 
         FIG. 3  shows a block diagram of a digital pre-distortion architecture according to one embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 3  shows a block diagram of a digital pre-distortion architecture  300  according to one embodiment of the present invention. As in the digital pre-distortion architecture of  FIG. 2 , digital pre-distortion architecture  300  receives a complex input signal x[n] represented by in-phase (I) and quadrature-phase (Q) components and generates a complex pre-distorted signal x pd [n′] that can be converted into an analog signal by a DAC analogous to DAC  120  of  FIG. 1  for application to a non-linear analog sub-system analogous to sub-system  130  of  FIG. 1 . Note that, although upconverter  132  of  FIG. 1  can contribute to the non-linearity of sub-system  130 , since most of the non-linearity is generated by amplifier  134 , for convenience, the rest of this description refers simply to the amplifier, although the teachings technically apply to the entire non-linear sub-system. 
     Like the architecture of  FIG. 2 , the digital pre-distortion architecture of  FIG. 3  represents the inverse of a model of the non-linear amplifier to which the pre-distorted signals are subsequently applied. Compared to the architecture of  FIG. 2 , however, the digital pre-distortion architecture of  FIG. 3  is based on a more-accurate model of that amplifier in order for the pre-distorter to sufficiently linearize more-complex amplifiers that exhibit significant nonlinear effects. As such, the architecture of  FIG. 3  can provide better linearization for certain amplifier designs under some specific signaling conditions, such as Doherty amplifiers with extremely wideband signals (e.g., signals having a bandwidth greater than about 40 MHz). 
     The digital pre-distortion architecture of  FIG. 3  can be represented mathematically according to Equation (3) as follows: 
                       x   pd     ⁡     [     n   ′     ]       =           f   0     ⁡     (     a   ⁡     [   n   ]       )       ·     x   ⁡     [     n   -     d   0       ]         +       {       x   ⁡     [     n   -     d   0       ]       ·     (         f   11     ⁡     (     a   ⁡     [   n   ]       )       *       h   d     ⁡     [   n   ]         )       }     *       h     B   ⁢           ⁢   1       ⁡     [   n   ]         +       {       x   ⁡     [     n   -     d   0       ]       ·     (         f   21     ⁡     (     a   ⁡     [   n   ]       )       *       h   d     ⁡     [   n   ]         )       }     *       h     B   ⁢           ⁢   2       ⁡     [   n   ]         +       {         f   12     ⁡     (     a   ⁡     [   n   ]       )       ·     (       x   ⁡     [     n   -     d   0       ]       *       h   d     ⁡     [   n   ]         )       }     *       h     B   ⁢           ⁢   3       ⁡     [   n   ]         +       {         f   22     ⁡     (     a   ⁡     [   n   ]       )       ·     (       x   ⁡     [     n   -     d   0       ]       *       h   d     ⁡     [   n   ]         )       }     *       h     B   ⁢           ⁢   4       ⁡     [   n   ]                   (   3   )               
where:
 
     Complex input signal x[n]=I+jQ; 
     Complex pre-distorted signal x pd [n′]=I′+jQ′ is the n′-th output sample corresponding to the n-th input sample; 
     Input signal power a[n]=∥x[n]∥ 2 =I 2 +Q 2  generated by power detector  302  of  FIG. 3 ; 
     Delay d 0  is a synchronization delay applied by Delay 0 block  304  of  FIG. 3  to compensate for the processing delay of power detector  302 ; 
     x[n−d 0 ] is the delayed input signal generated by Delay 0 block  304 ; 
     Delay d 1  is a synchronization delay applied by each of Delay 1 blocks  314 ,  324 ,  336 , and  346  of  FIG. 3  to compensate for the processing delays of blocks  316 ,  326 ,  334 , and  344 ; 
     Delay d 2  is a synchronization delay applied by Delay 2 block  310  of  FIG. 3  to compensate for differences between the processing delays of blocks  306  and  308  and the processing delays of blocks  314 - 352 . Note that the use of sample index n′ in the output sample x pd [n′] represents the effect of delays d 0 , d 1 , and d 2 ; 
     ƒ 0 (·), ƒ 11 (·), ƒ 12 (·), ƒ 21 (·), ƒ 22 (·) are (typically, but not necessarily, non-linear) polynomial pre-distortion functions of a[n] and are represented by Lookup Table ƒ 0    306 , Lookup Table ƒ 11    316 , Lookup Table ƒ 21    326 , Lookup Table ƒ 12    338 , and Lookup Table ƒ 22    348  of  FIG. 3 , respectively. Although shown as being implemented using lookup tables, the pre-distortion functions can alternatively be implemented algebraically; 
     h d [·] is the impulse response of each differentiator filter  318 ,  328 ,  334 , and  344  of  FIG. 3 ; 
     h B1 [·], h B2 [·], h B3 [·], h B4 [·] are the impulse responses of (e.g., linear) Hilbert filters  322 ,  332 ,  342 , and  352  of  FIG. 3  possibly for selecting the different frequencies; 
     “·” represents the complex multiplication operator of complex multipliers  308 ,  320 ,  330 ,  340 , and  350  of  FIG. 3 ; 
     “*” is the convolution operator; and 
     summation block  312  of  FIG. 3  represents the addition operations in Equation (3). 
     The non-linear distortion generated when a signal is amplified by an amplifier can comprise both a frequency-independent portion and a frequency-dependent portion. When pre-distorting the signal prior to its being applied to such an amplifier to pre-compensate for the amplifier&#39;s non-linear distortion, the pre-distortion can also comprise both a frequency-independent portion and a frequency-dependent portion. In Equation (2), the first term on the right-hand side (RHS) represents the frequency-independent portion of the pre-distortion operation, while the second and third terms represent the frequency-dependent portion of the pre-distortion operation. 
     In a situation where ƒ 1 =ƒ 2 =ƒ, the second and third terms would be equivalent to the time derivative of the product of two functions: the distortion function ƒ and the signal “function” x, where h d  represents the derivative function, since h P  and h N  represent linear filters that select the positive and negative frequencies, respectively. As such, Equation (2) is equivalent to the derivative of the product of two functions ƒ and x, with the further relaxation (i.e., additional degree of freedom) that the distortion function ƒ is allowed to be two different functions: ƒ 1  for positive frequencies selected by the filter function h P  and ƒ 2  for negative frequencies selected by the filter function h N . 
     Based on the well-known mathematical expansion, the derivative of the product of first and second two functions is equal to (1) the product of (i) the first function and (ii) the derivative of the second function plus (2) the product of (i) the second function and (ii) the derivative of the first function. 
     As in Equation (2), the first term on the RHS of Equation (3) represents the frequency-independent portion of the pre-distortion operation. The second through fifth terms on the RHS of Equation (3) represent the frequency-dependent portion of the pre-distortion operation. In particular, the second and fourth terms on the RHS of Equation (3) correspond to the mathematical expansion of the second term on the RHS of Equation (2), with the further potential relaxations (corresponding to two additional degrees of freedom) that (i) the function ƒ 1  of Equation (2) can be (but does not have to be) two different functions ƒ 11  and ƒ 12  and (ii) the positive-frequency filter function h P  of Equation (2) can be (but does not have to be) two different frequency-dependent filter functions h B1  and h B3 . Similarly, the third and fifth terms on the RHS of Equation (3) correspond to the mathematical expansion of the third term on the RHS of Equation (2), with the further potential relaxations (corresponding to two additional degrees of freedom) that (i) the function ƒ 2  of Equation (2) can be (but does not have to be) two different functions ƒ 21  and ƒ 22  and (ii) the negative-frequency filter function h N  of Equation (2) can be (but does not have to be) two different frequency-dependent filter functions h B2  and h B4 . 
     Note that, when ƒ 11 =ƒ 12  and ƒ 21 =ƒ 22  and h B1 =h B3 =h P  and h B2 =h B4 =h N , then Equation (3) is equivalent to Equation (2). On the other hand, when any one or more of those four equalities is not true, including implementations in which all four equalities are not true, then Equation (3) will be different from Equation (2). Allowing one or more of those four equalities to be false allows Equation (3) to provide greater flexibility than Equation (2) in modeling the pre-distortion operation to better compensate for the amplifier&#39;s non-linear distortion, thereby providing improved pre-distortion performance. 
     The (non-linear) polynomial functions ƒ 0 (·), ƒ 11 (·), ƒ 12 (·), ƒ 21 (·), ƒ 22 (·) and the (linear) filter functions h B1 [·], h B2 [·], h B3 [·], h B4 [·] can be generated by an algorithm which minimizes the difference between the input signal x[n] and the feedback signal y fb [n] (see  FIG. 1 ). Such an algorithm could consist of an adaptive filter algorithm such as LMS as described in, for example, S. Haykin,  Adaptive Filter Theory  (Prentice Hall), or an optimization algorithm as described in, for example, W. H. Press, B. P. Flannery, S. A. Teukolsky, and W. T. Vetterling,  Numerical Recipes: The Art of Scientific Computing  (New York: Cambridge University Press, 1986). 
     Note that one or more of the filter functions h B1 [·], h B2 [·], h B3 [·], h B4 [·] may be delays. 
     Broadening 
     Although the present invention has been described in the context of linearizing an analog sub-system having a non-linear amplifier, the invention can also be implemented in other contexts. For example, the invention can be implemented to linearize an analog sub-system having one or more of the following elements: baseband amplification, IF (intermediate frequency) amplification, RF amplification, frequency upconversion, frequency downconversion, vector modulation. Furthermore, depending on the frequency requirements of the particular application and the frequency capabilities of the physical components used to implement the various elements, upconverter  132  and/or downconverter  150  of  FIG. 1  may be omitted. Note that, in certain implementations, upconversion and/or downconversion may be partially or even completely implemented in the digital domain. In addition, pre-distorter  114  might not be adaptive, in which case the entire feedback path of tap  140 , downconverter  150 , and ADC  160  may be omitted. 
     The present invention may be implemented as (analog, digital, or a hybrid of both analog and digital) circuit-based processes, including possible implementation as a single integrated circuit (such as an ASIC or an FPGA), a multi-chip module, a single card, or a multi-card circuit pack. As would be apparent to one skilled in the art, various functions of circuit elements may also be implemented as processing blocks in a software program. Such software may be employed in, for example, a digital signal processor, micro-controller, general-purpose computer, or other processor. 
     The present invention can be embodied in the form of methods and apparatuses for practicing those methods. The present invention can also be embodied in the form of program code embodied in tangible media, such as magnetic recording media, optical recording media, solid state memory, floppy diskettes, CD-ROMs, hard drives, or any other non-transitory machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention. The present invention can also be embodied in the form of program code, for example, stored in a non-transitory machine-readable storage medium including being loaded into and/or executed by a machine, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention. When implemented on a general-purpose processor, the program code segments combine with the processor to provide a unique device that operates analogously to specific logic circuits. 
     It should be appreciated by those of ordinary skill in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the invention. Similarly, it will be appreciated that any flow charts, flow diagrams, state transition diagrams, pseudo code, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown. 
     Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value of the value or range. 
     It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this invention may be made by those skilled in the art without departing from the scope of the invention as expressed in the following claims. 
     The use of figure numbers and/or figure reference labels in the claims is intended to identify one or more possible embodiments of the claimed subject matter in order to facilitate the interpretation of the claims. Such use is not to be construed as necessarily limiting the scope of those claims to the embodiments shown in the corresponding figures. 
     It should be understood that the steps of the exemplary methods set forth herein are not necessarily required to be performed in the order described, and the order of the steps of such methods should be understood to be merely exemplary. Likewise, additional steps may be included in such methods, and certain steps may be omitted or combined, in methods consistent with various embodiments of the present invention. 
     Although the elements in the following method claims, if any, are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence. 
     Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term “implementation.” 
     The embodiments covered by the claims in this application are limited to embodiments that (1) are enabled by this specification and (2) correspond to statutory subject matter. Non-enabled embodiments and embodiments that correspond to non-statutory subject matter are explicitly disclaimed even if they fall within the scope of the claims.