Abstract:
A differential input comparator circuit comprises an input stage comprising dual polarity input voltages and an output stage adapted to output a differential voltage based on the input voltages, wherein the differential voltage is adapted to be transmitted to a comparator and wherein the circuit has high input impedance and works with high input voltage swings.

Description:
FIELD OF THE INVENTION 
   The present invention relates to differential input comparators and, more particularly, to a differential input comparator using MOS input transistors, for dual polarity, high voltage swing applications. 
   BACKGROUND OF THE INVENTION 
   A comparator circuit typically receives two input signals and generates an output signal based on the comparison of the two input signals. The comparison is generally based on the amplitude or magnitude of the input voltages. 
   Various problems are associated with comparator circuits, in particular with the input stage of the comparator. For example, input voltage limitations exist. Such limitations are imposed by the voltage breakdown of PN junctions and gate oxides in an ordinary complementary MOS (CMOS) or bipolar CMOS (BiCMOS) fabrication process. Further, certain solutions to these problems associated with comparator circuits employ external components to the chip or make use of circuit configurations that lower the input impedance of the comparator. 
   It is the purpose of the present invention to overcome the problems described above and to provide means of comparing signals of high voltage amplitude and both voltage polarities while keeping the comparator high input impedance presented by the MOS input transistors. 
   SUMMARY OF THE INVENTION 
   The present invention achieves technical advantages as a differential input comparator using MOS input transistors, for dual polarity high input voltage swing applications and high input impedance. 
   In one embodiment, a differential input comparator circuit comprises an input stage comprising dual polarity input voltages and an output stage adapted to output a differential voltage based on the input voltages, wherein the differential voltage is adapted to be transmitted to a comparator and wherein the circuit has high input impedance and works with high input voltage swings. 
   In another embodiment, a method for comparing signals comprises receiving dual polarity input voltages, maintaining a high input impedance, converting the dual polarity input voltages to a single polarity output voltage and outputting the single polarity output voltage, based on the input voltages, to a comparator. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1   a  illustrates a circuit in accordance with an exemplary embodiment of the present invention; 
       FIG. 1   b  illustrates a more detailed circuit of  FIG. 1   a  in accordance with an exemplary embodiment of the present invention; 
       FIG. 2  illustrates a graph depicting the input signals VP, VN when they are very close to each other (low overdrive voltage at the input) and the comparator output voltage, in accordance with an exemplary embodiment of the present invention; 
       FIG. 3  illustrates a graph depicting input signals VP, VN when they are very close with each other, and the output voltages of the input stage VNS, VPS, which are always positive in accordance with an exemplary embodiment of the present invention; 
       FIG. 4  illustrates a graph depicting the gate-to-source voltage VGS of the four PMOS transistors of the input stage not exceeding its maximum of 13.2 volts in accordance with an exemplary embodiment of the present invention; 
       FIG. 5  illustrates a graph depicting the drain-to-source voltage VDS of the four PMOS transistors of the input stage not exceeding its maximum of 30 volts in accordance with an exemplary embodiment of the present invention; 
       FIG. 6  illustrates a graph depicting the drain-to-backgate voltage VDB of the four PMOS transistors of the input stage not exceeding its maximum of 30 volts in accordance with an exemplary embodiment of the present invention; 
       FIG. 7  illustrates a graph depicting input signals VP, VN at high swing voltages (high overdrive voltage at the input) and the comparator output voltage, in accordance with an exemplary embodiment of the present invention; 
       FIG. 8  illustrates a graph depicting input signals VP, VN and positive output signals of the input stage VPS, VNS in accordance with an exemplary embodiment of the present invention; 
       FIG. 9  illustrates a graph depicting the gate-to-source voltage VGS of the four PMOS transistors of the input stage not exceeding its maximum of 13.2 volts in accordance with an exemplary embodiment of the present invention; 
       FIG. 10  illustrates a graph depicting the electrical current through transistor MP 8  and the gate-to-source voltage VGS and gate-to-backgate voltage VGB of transistor MP 8  when MP 8  is on and off in accordance with an exemplary embodiment of the present invention; 
       FIG. 11  illustrates a graph depicting the electrical current through transistor MP 4  and the gate-to-source voltage VGS and gate-to-backgate voltage VGB of transistor MP 4  when MP 4  is on and off in accordance with an exemplary embodiment of the present invention; 
       FIG. 12  illustrates a graph depicting the drain-to-source voltage VDS of the four PMOS transistors of the input stage not exceeding its maximum of 30 volts in accordance with an exemplary embodiment of the present invention; and 
       FIG. 13  illustrates a graph depicting the drain-to-backgate voltage VDB of the four PMOS transistors of the input stage not exceeding its maximum of 30 volts in accordance with an exemplary embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Circuit Description 
   Referring now to  FIG. 1   a , a differential input comparator circuit  10  of the present invention includes an input stage that comprises positive Channel MOS (PMOS) transistors MP 4 , MP 8 , MP 24 , and MP 26 , resistors R 2 , R 3 , R 4 , R 5 , R 10 , and R 11 , diodes D 0  and D 1 , current sources I 1  and I 2  voltage supplies VDDP 25  and VSSN 25 , and a circuit ground node gnd. The output of this first stage is the differential voltage VPS-VNS which is applied to an ordinary comparator  12 . Comparator  12  works only with single positive polarity signals so the first stage converts the dual polarity signals applied to VP and VN to positive voltages at VPS and VNS. 
   Resistor R 2  is connected between supply voltage VDDP 25  and the common node VPS of R 2 , R 3 , D 0 , D 1 , the N-well of transistor MP 4 , and the positive input of comparator  12 . Resistor R 3  is connected between the common node VPS and the source of PMOS transistor MP 4 . The gate of transistor MP 4  is connected to differential input signal voltage VP. The well of transistor MP 4  is connected to the common node VPS. The drain of transistor MP 4  is connected to the source of PMOS transistor MP 24 . The drain of transistor MP 24  is connected to supply voltage VSSN 25 . The well of transistor MP 24  is connected to circuit ground gnd. The gate of transistor MP 24  is connected to the common node A of resistor R 10  and current source I 1 . Resistor R 10  is connected between common node A and supply voltage VSSN 25 . Current source I 1  is connected between supply voltage VDDP 25  and the common node A. 
   Resistor R 5  is connected between supply voltage VDDP 25  and the common node VNS of R 5 , R 4 , D 0 , D 1 , the backgate (N-well) of transistor MP 8 , and the negative input of comparator  12 . Resistor R 4  is connected between the common node VNS and the source of PMOS transistor MP 8 . The gate of transistor MP 8  is connected to differential input signal voltage VN. The N-well of transistor MP 8  is connected to the common node VNS. The drain of transistor MP 8  is connected to the source of PMOS transistor MP 26 . The drain of transistor MP 26  is connected to supply voltage VSSN 25 . The substrate of transistor MP 26  is connected to circuit ground gnd. The gate of transistor MP 26  is connected to the common node B of resistor R 11  and current source I 2 . Resistor R 11  is connected between common node B and supply voltage VSSN 25 . Current source I 2  is connected between supply voltage VDDP 25  and the common node B. Transistors MP 4  and MP 8 , and transistors MP 24  and MP 26  are drain extended symmetrical devices. 
   The anode of diode D 0  is connected to common node VPS and the cathode of diode D 0  is connected to the common node VNS. The anode of diode D 1  is connected to common node VNS and the cathode of diode D 1  is connected to the common node VPS. The comparator  12  has its positive input connected to the common node VPS and its negative input connected to the common node VNS. 
   By example only, the resistors R 10  and R 11  each have a resistance value of 110 k ohms and the resistors R 2 , R 3 , R 4 , and R 5  each have a resistance value of 200 k ohms. The voltage source VDDP 25  has a voltage of +25 volts referenced to circuit ground gnd and voltage supply VSSN 25  has a voltage of −25 volts referenced to circuit ground gnd. Other values may also be used for the components of the circuit  10 . 
   Circuit Operation 
   The differential input comparator circuit  10  of the present invention uses PMOS transistors as the differential input pair and has high input impedance, works in dual polarity input voltages (VP and/or VN can be positive or negative relative to ground gnd), and works with high input voltage swings. The circuit  10  also comprises various circuits that adjust the bias voltage of those PMOS devices according to the input voltages. Such adjustment keeps the devices within a safe area of voltage operation. The circuit  10  also does not use external components to adjust the bias voltage. 
   The two input voltages to be compared are applied to VP and VN and can be of any value. For the present embodiment, the minimum voltage that may occur is −25 volts, and the maximum voltage that may occur is +25 volts. In other embodiments, the minimum and maximum voltages may differ. So, both voltages applied to VP and VN can be zero volts, they can be both positive voltages, both negative voltages or one positive and other negative. Two distinct situations might occur. In the first one, the voltages on VP and VN are very close to each other (low overdrive voltage at the input) and in the second one VP and VN can assume voltage levels that are far apart. 
   The situation where VP and VN are very close to each other is shown on  FIGS. 2–6 .  FIG. 2  depicts the input signal VP toggling above and below input signal VN (which is a ramp) in close proximity to VN. The signal VOUT is the digital output of the comparator  12 . VOUT is high (for example 5V) whenever VP is higher than VN and VOUT is low whenever VP is lower than VN. For applications where these input signals are very close to each other, they can certainly be compared. 
   The input voltage signal VP is applied to the gate of transistor MP 4 . MP 4 , R 2  and R 3  form a source follower circuit such that the voltage at the source of transistor MP 4  will be a VGS voltage (approximately 1 to 3 volts) above VP and will follow (track) the voltage VP applied to the gate of MP 4  and vary from +25 volts when VP is close to +25V to approximately −22V volts when VP is at −25V. The source of transistor MP 4  is connected to the resistor R 3  at node E. The resistors R 2  and R 3  are identical and are connected in series to act as a voltage divider. Since the voltages applied to VP and VN are close to each other, the output voltages of the first stage VPS and VNS will also be close to each other and no electrical current will flow through diodes D 0  or D 1 . That way, the resistor divider formed by R 2  and R 3  will make the voltage on VPS to be half way between supply VDDP 25  and the voltage on node E. The maximum voltage that may appear at node VPS is +25 volts when VP is +25 volts and the minimum voltage that may appear at node VPS is approximately +1.5 volts when VP is at −25 volts. The resistor divider is used to provide a positive voltage at VPS independent of the polarity of the input voltage VP.  FIG. 3  depicts the dual polarity input voltages VP and VN and output signals VNS and VPS which are always positive. The nodes VNS and VPS are the output of the first stage which converts dual polarity inputs to a single polarity output which is fed to the second stage or comparator  12 . The node VPS maximum voltage of +25 volts occurs when the transistor MP 4  is rendered nonconductive. In this case, there will be no current flow through transistor MP 4  and thus no current will flow through resistors R 2  and R 3 . As such, the voltage at node VPS will be equal to the supply voltage VDDP 25 . For this embodiment, the supply voltage VDDP 25  is +25 volts. The minimum node VPS voltage of approximately +1.5 volts occurs when the transistor MP 4  is rendered fully conductive. This will cause sufficient current to flow through transistor MP 4  such that the voltage across resistor R 2  will be equal to approximately 23.5 volts. Thus, a voltage of approximately +1.5 volts will be established at node VPS. 
   The circuit composed of transistor MP 24 , resistor R 10 , and current source I 1  is used to provide a source of voltage bias to the drain of transistor MP 4  so that transistor MP 4  is protected from experiencing excessive drain-to-source voltage or drain-to-backgate voltage that would exceed the break down voltages specific to the transistor. The current through current source I 1  is controlled so that it is linearly related to the input signal voltage VP such that if the voltage at VP increases, the current I 1  will also be increased, and if the voltage at VP decreases, the current I 1  will be decreased. The circuitry to establish this relationship between current I 1  and voltage VP is not shown in  FIG. 1   a . By increasing the current I 1 , the voltage at node A will be increased. This increase in voltage at node A is applied to the gate of transistor MP 24 , causing the transistor to become less conductive. This will in turn cause the voltage at node C (drain of MP 4 ) to be increased. When VP goes high, the voltage on VPS (backgate of MP 4 ) and the voltage on node E (source of MP 4 ) will also go high, but at the same time I 1  will increase and force node C (drain of MP 4 ) to go high. That way the voltage VDS across drain-to-source of MP 4  and the voltage from drain-to-backgate VDB of MP 4  will be limited and will not exceed the maximum allowable voltage. For this embodiment, the maximum allowable drain-to-source and drain-to-backgate voltage is 30 volts. Thus the circuit composed of transistor MP 24 , resistor R 10  and current source I 1  acts to protect transistor MP 4  from experiencing voltage breakdown. 
   The input voltage signal VN is applied to the gate of transistor MP 8 . MP 8 , R 5  and R 4  form a source follower circuit such that the voltage at the source of transistor MP 8  will be a VGS voltage (approximately 1 to 3 volts) above VN and will follow (track) the voltage VN applied to the gate of MP 8  and vary from +25 volts when VN is close to +25V to approximately −22V volts when VN is at −25V. The source of transistor MP 8  is connected to the resistor R 4  at node F. The resistors R 4  and R 5  are identical and are connected in series to act as a voltage divider. Since the voltages applied to VP and VN are close to each other the output voltages of the first stage VPS and VNS will also be close to each other and no electrical current will flow through diodes D 0  or D 1 . That way, the resistor divider formed by R 4  and R 5  will make the voltage on VNS to be half way between supply VDDP 25  and the voltage on node F. The maximum voltage that may appear at node VNS is +25 volts when VN is +25 volts and the minimum voltage that may appear at node VNS is approximately +1.5 volts when VN is at −25 volts. The resistor divider is used to provide a positive voltage at VNS independent of the polarity of the input voltage VN.  FIG. 3  depicts the dual polarity input voltages VP and VN and output signals VNS and VPS which are always positive. The nodes VNS and VPS are the output of the first stage which converts dual polarity inputs to a single polarity output which is fed to the second stage or comparator  12 . The node VNS maximum voltage of +25 volts occurs when the transistor MP 8  is rendered nonconductive. In this case, there will be no current flow through transistor MP 8  and thus no current will flow through resistors R 5  and R 4 . As such, the voltage at node VNS will be equal to the supply voltage VDDP 25 . For this embodiment, the supply voltage VDDP 25  is +25 volts. The minimum node VNS voltage of approximately +1.5 volts occurs when the transistor MP 8  is rendered fully conductive. This will cause sufficient current to flow through transistor MP 8  such that the voltage across resistor R 5  will be equal to approximately 23.5 volts. Thus, a voltage of approximately +1.5 volts will be established at node VNS. 
   The circuit composed of transistor MP 26 , resistor R 11 , and current source I 2  is used to provide a source of voltage bias to the drain of transistor MP 8  so that transistor MP 8  is protected from experiencing excessive drain-to-source voltage or drain-to-backgate voltage that would exceed the break down voltages specific to the transistor. The current through current source I 2  is controlled so that it is linearly related to the input signal voltage VN such that if the voltage at VN increases, the current I 2  will also be increased, and if the voltage at VN decreases, the current I 2  will be decreased. The circuitry to establish this relationship between current I 2  and voltage VN is not shown in  FIG. 1   a . By increasing the current I 2 , the voltage at node B will be increased. This increase in voltage at node B is applied to the gate of transistor MP 26 , causing the transistor to become less conductive. This will in turn cause the voltage at node D (drain of MP 8 ) to be increased. When VN goes high, the voltage on VNS (backgate of MP 8 ) and the voltage on node F (source of MP 8 ) will also go high, but at the same time I 2  will increase and force node D (drain of MP 8 ) to go high. That way the voltage VDS across drain-to-source of MP 8  and the voltage from drain-to-backgate VDB of MP 8  will be limited and will not exceed the maximum allowable voltage. For this embodiment, the maximum allowable drain-to-source and drain-to-backgate voltage is 30 volts. Thus the circuit composed of transistor MP 26 , resistor R 11  and current source I 2  acts to protect transistor MP 8  from experiencing voltage breakdown. 
   When the input voltages VP and VN are both too high, close to the supply VDDP 25 , there will be no current flowing through R 2 , R 3 , R 4 , R 5  and VPS and VNS will be at a voltage equal to the supply VDDP 25 . Since both VPS and VNS are at the same potential, the comparator  12  might make the wrong decision about the comparison of the two voltages. Therefore when both VP and VN are close to the rail VDDP 25  the comparator is not guaranteed to operate correctly. This can be noted on  FIG. 2  at around time zero. However, even is this scenario there is no risk for any breakdown to occur. 
     FIG. 1   b  shows an example of the implementation of current sources I 1  and I 2 , as well as an example of the implementation of comparator  12 . Transistor MN 1 , MP 19  and resistor R 13  form the current source I 1 . MN 1  is a symmetric drain extended NMOS and MP 19  is an asymmetric drain extended PMOS. When the voltage on VP goes high, the voltage on VPS goes high as well. The transistor MN 1  and resistor R 13  form a source follower configuration and when the gate voltage (VPS) goes high the source node  1  of MN 1  goes high as well. The transistor MP 19  has its gate connected to gnd, so the source node  2  of MP 19  will be at an almost constant voltage potential of 1 to 1.5 volts (VGS of MP 19 ). Since the voltage on node  1  moves up or down in a linear function of VP and the node  2  almost does not move, then the voltage and current across resistor R 13  increases when VP goes high and decreases when VP goes low. Due to the connection of R 13 , MP 19  and R 10 , the current that goes through R 13  is the same as the current through R 10 , which represents I 1  in  FIG. 1   a . Similarly, transistor MN 2 , MP 30  and resistor R 15  form the current source I 2 . MN 2  is a symmetric drain extended NMOS and MP 30  is an asymmetric drain extended PMOS. When the voltage on VN goes high, the voltage on VNS goes high as well. The transistor MN 2  and resistor R 15  form a source follower configuration and when the gate voltage (VNS) goes high the source node  3  of MN 2  goes high as well. The transistor MP 30  has its gate connected to gnd, so the source node  4  of MP 30  will be at an almost constant voltage potential of 1 to 1.5 volts (VGS of MP 30 ). Since the voltage on node  3  moves up or down in a linear function of VN and the node  4  almost does not move, then the voltage and current across resistor R 15  increase when VN goes high and decrease when VN goes low. Due to the connection of R 15 , MP 30  and R 11 , the current that goes through R 15  is the same as the current through R 11 , which represents I 2  in  FIG. 1   a.    
     FIG. 1   b  also shows an example of an implementation of the comparator  12 . Transistors MP 9 , MP 10 , MN 13 , and MN 14  are connected in a differential amplifier configuration. If VPS becomes less than voltage VNS, the voltage at the drain of MN 14  will decrease, eventually reaching the ground potential. Transistor MN 11  goes off forcing the voltage on node OUTS to go high. If VPS becomes greater than VNS, the voltage at the drain of MN 14  will increase, forcing MN 11  to be more conductive and bringing node OUTS to a low voltage potential. Transistors MN 13  and MN 14  form a current mirror so that the total current through MP 9  and MP 10  is constant. The bias current to the differential amplifier is provided by the current source composed of transistors MP 11 , MP 6 , MP 12 , and MP 13 . Transistors MN 0 , MN 11 , MP 14  and MP 15  form the output stage of comparator  12 . MN 0  limits the voltage level on node OUTS to be compatible with input of inverter IV 120 , which in turn translates the voltage level on OUTS to a 5 volts digital signal at the output OUT. 
     FIGS. 4–6  show the voltages across the PMOS transistors MP 4 , MP 8 , MP 24  and MP 26  of the circuit shown in  FIG. 1   b  when the input signals VP and VN are according to the waveform depicted in  FIG. 2 . As shown, they do not exceed the breakdown voltages of the devices. In  FIG. 4 , the VGS (gate to source) of the transistors MP 4 , MP 8 , MP 24 , and MP 26  is depicted not exceeding its maximum of 13.2 volts and is actually shown to be far below such a breakdown voltage. In  FIG. 5 , signal VDS (drain to source) of the transistors MP 4 , MP 8 , MP 24 , and MP 26  is depicted not exceeding its maximum of 30 volts and in  FIG. 6 , signal VDB (drain to backgate) of the transistors MP 4  and MP 8  is depicted not exceeding its maximum of 30 volts. Further, the drain to backgate voltage of MP 24  and MP 26  is at a fixed 25 volts. 
   When high swing voltages are applied to VP and VN, such that a high differential voltage exists across VP-VN, a high voltage will appear across the output voltages of input stage VPS and VNS. This will cause D 0  or D 1  to conduct current and clamp the voltage across VPS-VNS to less than 1 volt. Transistors MP 4  or MP 8  might become nonconductive (go OFF). For example, if the voltage on VP is much higher than on VN, the current that flows through R 2  will go to D 0  and then to VNS and no current will go through R 3  and MP 4  (MP 4  would go OFF). The diodes D 0  and D 1  are used to protect the input transistors (MP 9  and MP 10  of  FIG. 1   b ) of the comparator block  12  from experiencing voltages greater than the comparator input transistors can tolerate. The comparator positive and negative inputs are connected to the gate of MOS transistors which have gate-to-source and gate-to-drain breakdown voltages of 13.2 volts. The diodes D 0  and D 1  placed across the positive and negative inputs of comparator  12  limits the voltage of these inputs such that they cannot become greater than +13.2 volts or less than −13.2 volts. In other embodiments, the minimum and maximum breakdown voltages may differ. 
   The situation where high swing voltages are applied to VP and VN inputs of circuit shown in  FIG. 1   b  is depicted on  FIGS. 7–13 .  FIG. 7  shows the input signal VP and VN swinging from 0V, +20V and −20V according to the indicated waveform. From 0 s to 100 us VP and VN are close to 0V with VP just a few millivolts below VN. The signal VOUT is the digital output of the comparator  12 . VOUT is high (for example 5V) whenever VP is higher than VN and VOUT is low whenever VP is lower than VN. 
   Referring now to  FIG. 8 , input signals VP and VN are similarly depicted as in  FIG. 7  and the output signals VPS and VNS of the first stage are shown to be positive for receipt by the comparator  12 . It can be noticed that the voltage across VPS-VNS never exceeds 1V due to the voltage clamp function performed by D 0  and D 1 . 
   Referring now to  FIG. 9 , signal VGS of transistors MP 4  and MP 8  as well as signal VGS of transistors MP 24  and MP 26  are depicted as not exceeding its maximum of 13.2 volts even when the transistors are on and/or off. 
   Referring now to  FIG. 10 , various graphs are depicted. The top graph shows the current through transistor MP 8  and the intervals where that current goes to 0 indicating MP 8  is OFF. In both occurrences when MP 8  is OFF, the gate-to-backgate voltage of MP 8  does not exceed the breakdown voltage of the gate oxide which is 13.2V. That means that even though there is no channel formed since MP 8  is OFF, the voltage across the gate oxide will be no greater than the gate-to-backgate voltage and will not exceed the 13.2V. However, as can be seen in the middle graph, there is an occurrence between 100 us to 200 us when MP 8  is ON and the gate-to-backgate voltage VGB of MP 8  is higher than 13.2 volts. This is not a concern because at that time MP 8  is ON, the MOS channel is formed and the voltage across the gate oxide will be dictated by the gate-to-source voltage VGS of the transistor. As can be seen in the bottom graph, the VGS of MP 8  at that time is lower than the gate oxide breakdown voltage of 13.2 volts. Since the VGS is lower than 13.2 volts, and since the VGB is less than 13.2 volts when MP 8  is off, this is not a problematic situation. 
   Referring now to  FIG. 11 , the waveforms show the similar situation for transistor MP 4  as described in  FIG. 10  for transistor MP 8 . When transistor MP 4  is ON and the VGB of MP 4  is higher than 13.2 volts, at the same time, the VGS of MP 4  is lower than 13.2 volts preventing the voltage across the gate oxide of the transistor to be exceeded. 
   Referring now to  FIG. 12 , the drain-to-source signal VDS of transistors MP 4 , MP 8 , MP 24 , and MP 26  is depicted not exceeding its maximum of 30 volts. 
   Referring now to  FIG. 13 , the drain-to-backgate signal VDB of transistors MP 4  and MP 8  is depicted not exceeding its maximum of 30 volts. Further, the drain to backgate voltage of MP 24  and MP 26  is at a fixed 25 volts. 
   Although an exemplary embodiment of the present invention has been illustrated in the accompanied drawings and described in the foregoing detailed description, it will be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications, and substitutions without departing from the spirit of the invention as set forth and defined by the following claims.