Abstract:
A method and system for measuring displacement of a structure is disclosed. The method and system comprise providing a first capacitance and providing a second capacitance. The first and second capacitances share a common terminal. The method and system further include determining a difference of the inverses of the value of the first and second capacitances when the structure is displaced. The first capacitance varies in inverse relation to the displacement of the structure.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims benefit under 35 USC 119(e) of U.S. Provisional Patent Application No. 61/780,437, filed on Mar. 13, 2013, entitled “LINEAR CAPACITIVE DISPLACEMENT SENSOR,” which is incorporated herein by reference in its entirety. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates generally to displacement measurement by a sensor and more particularly to capacitive displacement sensing. 
       BACKGROUND 
       [0003]    Displacement sensors are utilized in a variety of environments. For example, they are utilized in automotive applications, motion sensing applications, aeronautical applications and the like. It is desirable to provide accurate and low cost displacement sensors for many of these applications. The present invention addresses such a need. 
       SUMMARY 
       [0004]    A method and system for measuring displacement of a structure is disclosed. The method and system comprise providing a first capacitance and providing a second capacitance. The first and second capacitances share a common terminal. The method and system further include determining a difference of the inverses of the value of the first and second capacitances when the structure is displaced. The first capacitance varies in inverse relation to the displacement of the structure. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]      FIG. 1   a  shows a diagram of capacitive sensor sharing one diaphragm. 
           [0006]      FIG. 1   b  shows a diagram of capacitive sensor sharing one fixed electrode. 
           [0007]      FIG. 2   a  shows a configuration to measure C s  at a first phase, where an operational amplifier is employed to regulate the voltage at sense electrode and the common terminal of C s  and C g  is driven by a step drive voltage V D . 
           [0008]      FIG. 2   b  shows a configuration to measure C g  at a second phase, where an operational amplifier is employed to regulate the voltage at gap electrode and the common terminal of C s  and C g  is driven by a step drive voltage −V D . 
           [0009]      FIG. 2   c  shows a configuration to linearize the output with respect to C g  at a third phase, where both C Ls  and C Lg  which sampled the outputs of the first two phases respectively are connected to the negative input of the operational amplifier. 
           [0010]      FIG. 2   d  shows a configuration to linearize the output with respect to C s  at the fourth phase, where the third phase outputs sampled at C Lx  is connected to an input of an operational amplifier. 
           [0011]      FIG. 2   e  shows an alternative configuration to measure a difference of C s  and C g  at the first phase by sensing at the common terminal, where an operational amplifier is employed to regulate the common terminal voltage. 
           [0012]      FIG. 3   a  shows a configuration to measure C s  with a common mode charge cancellation capacitor C r  at the first phase, where both the sense capacitor C s  and a fixed capacitance reference capacitor C r  are connected to a negative input of an operational amplifier. 
           [0013]      FIG. 3   b  shows a configuration to measure C g  with a common mode charge cancellation capacitor C r  at the second phase, where both sense the capacitor C g  and a fixed reference capacitor C r  are connected to the negative input of an operational amplifier. 
           [0014]      FIG. 4   a  shows a configuration to measure the difference of C s  and C g  at a first phase, where a differential operational amplifier is employed to regulate the voltage at the sense electrode and a gap electrode. 
           [0015]      FIG. 4   b  shows a configuration to linearize the output with respect to C g  at a second phase, where both C Lsp  and C Lsn  which sampled the first phase outputs are connected to the negative input of the differential operational amplifier. 
           [0016]      FIG. 4   c  shows a configuration to linearize the output with respect to C s  at a third phase, where both C Lgp  and C Lgn  which sampled the second phase outputs are connected to the inputs of the differential operational amplifier. 
           [0017]      FIG. 5   a  shows a configuration to measure the difference of C s  and C g  at a first phase, where the second stage of amplifier is employed to attenuate the common mode disturbance. 
           [0018]      FIG. 5   b  shows a configuration to linearize the output with respect to C g  at a second phase, where C Lsn  which sampled the first phase output is connected to a negative input of the differential operational amplifier. 
           [0019]      FIG. 5   c  shows a configuration to linearize the output with respect to C s  at the third phase, where C Lgn  which sampled the second phase output is connected to the inputs of the differential operational amplifier. 
           [0020]      FIG. 6  shows a flow chart of method of linearization of capacitive displacement sensor in accordance with an embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    The present invention relates generally to displacement measurement by a sensor and more particularly to capacitive displacement sensing. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein. 
         [0022]    As shown in  FIG. 1   a , physical structures of capacitive sensor  100  comprise one (or more) diaphragm  101  and a set of fixed electrodes  102  and  103 . Force F applied to one (or both) side(s) of the diaphragm will cause it to deflect until the elastic force balances the force. One sense electrode  102  is located underneath the diaphragm and where the diaphragm  101  deforms at  104  and one gap electrode  103  is located where diaphragm  101  is rigidly clamped at  106 . The overlap of diaphragm  101  and fixed electrodes  102  and  103  forms two capacitances: a sense capacitance C s    110  and gap capacitance C g    111 . 
         [0023]    In a second embodiment as shown in  FIG. 1   b , physical structures of capacitive sensor  100 ′ could also comprise one (or more) moving electrode  122  and a set of fixed electrodes  120  and  124 . Force F applied to the moving electrode  122  will change the displacement with respect to the fixed electrode  124 . Moving electrode  122  and fixed electrode  124  form a sense capacitance C s    126 . The fixed electrode  120  and the fixed electrode  124  form a gap capacitance C g    128 . 
         [0024]    The force F can be related to various mechanical or physical properties. Pressure and acceleration are two examples of known capacitive sensor applications. 
         [0025]    The displacements of sensors  100  and  100 ′ shown in  FIG. 1   a  and  FIG. 1   b  can be described by the equation: 
         [0000]        x=g   0   −f ( F )  (1)
 
         [0026]    where g o  is initial displacement, F is applied force and the separation of the electrode is a linear or affine function of applied force f(F) and x is the effective displacement with the appearance of force F. 
         [0027]    Assume the parallel plate model can be employed and ignoring fringing field, the sense capacitance C s  and gap capacitance C g  are given by the following equation: 
         [0000]    
       
         
           
             
               
                 
                   
                     C 
                     s 
                   
                   = 
                   
                     
                       
                         ɛ 
                         0 
                       
                        
                       
                         ɛ 
                         r 
                       
                        
                       A 
                     
                     x 
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
             
               
                 
                   
                     C 
                     g 
                   
                   = 
                   
                     
                       
                         ɛ 
                         0 
                       
                        
                       
                         ɛ 
                         r 
                       
                        
                       A 
                     
                     
                       g 
                       0 
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0028]    Where ε 0  the permittivity of free space is, ε r  is the relative permittivity of the material between electrodes or between electrodes and diaphragm, A is the area of overlap between electrodes or area of overlap between electrode and diaphragm and x is the displacement. From the above equations it is seen that the capacitance varies in a non-linear manner with respect to the displacement x. 
         [0029]    The first order linearization versus force can be achieved by inversion of the capacitance: 
         [0000]    
       
         
           
             
               
                 
                   
                     1 
                     
                       C 
                       s 
                     
                   
                   = 
                   
                     
                       
                         g 
                         0 
                       
                       - 
                       
                         f 
                          
                         
                           ( 
                           F 
                           ) 
                         
                       
                     
                     
                       
                         ɛ 
                         0 
                       
                        
                       
                         ɛ 
                         r 
                       
                        
                       A 
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
         [0030]    A common problem for the capacitance sensing is that the initial gap g 0  is susceptible to temperature and stress. To cancel the g 0  variation, the difference between the inversion of the gap capacitance and the inversion of the sense capacitance is given by equation (5) below: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       1 
                       
                         C 
                         g 
                       
                     
                     - 
                     
                       1 
                       
                         C 
                         s 
                       
                     
                   
                   = 
                   
                     
                       f 
                        
                       
                         ( 
                         F 
                         ) 
                       
                     
                     
                       
                         ɛ 
                         0 
                       
                        
                       
                         ɛ 
                         r 
                       
                        
                       A 
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0031]    Since C s  and C g  share same terminal, the measurement can be done by multiple phases. As shown in  FIG. 2   a  to  FIG. 2   d , a single-ended readout circuit with multiple phase operation can generate a output which is proportional to Equation (5) 
         [0032]      FIG. 2   a  shows a configuration to measure C s    202  at the first phase, where an operational amplifier  220  is employed to regulate the voltage at the sense electrode. A common terminal of C s    202  and C g    201  is driven by a positive step voltage V D    231 . Since C g    201  is disconnected from the input of the operational amplifier  220  during this phase, only net charge across C s    202  transfers to a feedback capacitance C f    203 . The output voltage V OUT    230  which is sampled by load capacitance C Ls    204  at the end of the first phase operation is given by the equation: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       OUT_ph 
                        
                       
                           
                       
                        
                       1 
                     
                   
                   = 
                   
                     
                       
                         - 
                         
                           V 
                           D 
                         
                       
                        
                       
                         C 
                         s 
                       
                     
                     
                       C 
                       f 
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
         [0033]      FIG. 2   b  shows a configuration to measure C g    201  at the second phase, where the common terminal of C s    202  and C g    201  is driven by a negative step voltage −V D    232 . Since C s    202  is disconnected from an input of the operational amplifier  220 , only the net charge across C g    201  transfers to a feedback capacitance C f    203 . The output voltage V OUT    230  which is sampled by load capacitance C Lg    205  at the end of the second phase operation is given by the equation: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       OUT_ph 
                        
                       
                           
                       
                        
                       2 
                     
                   
                   = 
                   
                     
                       
                         V 
                         D 
                       
                        
                       
                         C 
                         g 
                       
                     
                     
                       C 
                       f 
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
         [0034]      FIG. 2   c  shows a configuration to linearize the output with respect to C g    201  at the third phase, where both C Ls    204  and C Lg    205  which sampled first two phases outputs respectively are connected to the negative input of the operational amplifier  220 . The charge stored at C Ls    204  and C Lg    205  transfers to the feedback capacitance C g    201 . The output voltage V OUT    230  which is sampled by load capacitance C Lx    206  at the end of the third phase operation is given by the equation: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       OUT_ph 
                        
                       3 
                     
                   
                   = 
                   
                     
                       
                         V 
                         D 
                       
                        
                       
                         ( 
                         
                           
                             
                               C 
                               Lg 
                             
                              
                             
                               C 
                               g 
                             
                           
                           - 
                           
                             
                               C 
                               Ls 
                             
                              
                             
                               C 
                               s 
                             
                           
                         
                         ) 
                       
                     
                     
                       
                         C 
                         f 
                       
                        
                       
                         C 
                         g 
                       
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
         [0035]      FIG. 2   d  shows a configuration to linearize the output with respect to C s    202  at the fourth phase, where the third phase outputs sampled at C Lx    206  are connected to the input of operational amplifier  220 . The charge stored at C Lx    206  transfers to a feedback capacitance C s    202 . The output voltage V OUT    230  which is sampled by the load capacitance C L    207  at the end of the fourth phase operation is given by the equation: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       OUT_ph 
                        
                       4 
                     
                   
                   = 
                   
                     
                       
                         V 
                         D 
                       
                        
                       
                         
                           C 
                           Lx 
                         
                          
                         
                           ( 
                           
                             
                               
                                 C 
                                 Lg 
                               
                                
                               
                                 C 
                                 g 
                               
                             
                             - 
                             
                               
                                 C 
                                 Ls 
                               
                                
                               
                                 C 
                                 s 
                               
                             
                           
                           ) 
                         
                       
                     
                     
                       
                         C 
                         f 
                       
                        
                       
                         C 
                         g 
                       
                        
                       
                         C 
                         s 
                       
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
         [0036]    By setting C Ls    204  equal to C Lg    205 , the Equation (9) can be reduced by: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       OUT_ph 
                        
                       4 
                     
                   
                   = 
                   
                     
                       ( 
                       
                         
                           1 
                           
                             C 
                             g 
                           
                         
                         - 
                         
                           1 
                           
                             C 
                             s 
                           
                         
                       
                       ) 
                     
                      
                     
                       
                         
                           V 
                           D 
                         
                          
                         
                           C 
                           Lx 
                         
                          
                         
                           C 
                           Lg 
                         
                       
                       
                         C 
                         f 
                       
                     
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
         [0037]    From Equation (10), the output of the readout circuitry can deliver the linear function with respect to the displacement and the transducer gain of the readout circuitry is adjusted by setting V D , C Lx , C Lg  and C f  base on the sensitivity of C s . 
         [0038]      FIG. 2   e  shows an alternative configuration to measure difference of C s    202  and C g    201  at the first phase by sensing at a common terminal  212 , where an operational amplifier  220  is employed to regulate the voltage at the common terminal  212 . The electrode  211  of C s    202  and the electrode  210  of C g    201  are driven by a step drive voltage with the amplitude of V D    231  and −V D    232  respectively. The net charge across C s    202  and C g    201  transfers to a feedback capacitance C f    203 . The output voltage V OUT    230  which is sampled by the load capacitance C Ls    204  at the end of the first phase operation is given by the equation: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       OUT_ph 
                        
                       
                           
                       
                        
                       1 
                     
                   
                   = 
                   
                     
                       
                         V 
                         D 
                       
                        
                       
                         ( 
                         
                           
                             C 
                             g 
                           
                           - 
                           
                             C 
                             s 
                           
                         
                         ) 
                       
                     
                     
                       C 
                       f 
                     
                   
                 
               
               
                 
                   ( 
                   11 
                   ) 
                 
               
             
           
         
       
     
         [0039]    According to Equation (11), the four phases measurement described in  FIG. 2   a  to  FIG. 2   d  can be reduced into three phases:  FIG. 2   e  for first phase&#39;s configuration,  FIG. 2   c  and  FIG. 2   d  for subsequent two phases&#39; configuration respectively. But there are limitations of sensing from the common terminal: in applications where the common terminal  212  is exposed to external environment, it is susceptible to the Electromagnetic Interference (EMI), dust and humidity, etc. The readout accuracy and noise performance will be degraded because of the extra shielding and leakage. 
         [0040]    To decrease any chance for a potential charge disturbance at the input during the first two phases which could cause the operational amplifier  220  slewing and limits the speed of the operation, a fixed capacitance which can deliver opposite charges at the first two phases can be added. This feature is described in detail hereinafter with respect to  FIG. 3   a  and  FIG. 3   b.    
         [0041]      FIG. 3   a  shows a configuration to measure C s    302  a common mode charge cancellation capacitor C r    303  at a first phase, where both sense capacitor C s    302  and a fixed capacitance reference capacitor C r    303  are connected to the negative input of operational amplifier  320 . The common terminal of C s    302  and C g    301  is driven by a positive step voltage V D    331 , while the C r    303  is driven by a negative step voltage −V D    332 . Because that C s    302  and C r    303  are driven by opposite potential, only net charge across C s    302  and C r    303  transfers to a feedback capacitance C f    304 . The output voltage V OUT    330  which is sampled by the load capacitance C Ls    305  at the end of the first phase operation is given by the equation: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       OUT_ph 
                        
                       
                           
                       
                        
                       1 
                     
                   
                   = 
                   
                     
                       - 
                       
                         
                           V 
                           D 
                         
                          
                         
                           ( 
                           
                             
                               C 
                               s 
                             
                             - 
                             
                               C 
                               r 
                             
                           
                           ) 
                         
                       
                     
                     
                       C 
                       f 
                     
                   
                 
               
               
                 
                   ( 
                   12 
                   ) 
                 
               
             
           
         
       
     
         [0042]      FIG. 3   b  shows a configuration to measure C g    301  at a second phase, where both the sense capacitor C g    301  and C r    303  are connected to the negative input of operational amplifier  320 . The common terminal of C s    302  and C g    301  is driven by a negative step voltage −V D    331 , while C r    303  is driven by a positive step voltage with amplitude of V D    332 . Because C g    301  and C r    303  are driven by opposite potential, only the net charge across C g    301  and C r    303  transfers to the feedback capacitance C f    304 . The output voltage V OUT    330  which is sampled by the load capacitance C Lg    306  at the end of the first phase operation is given by the equation: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       OUT_ph 
                        
                       2 
                     
                   
                   = 
                   
                     
                       
                         V 
                         D 
                       
                        
                       
                         ( 
                         
                           
                             C 
                             g 
                           
                           - 
                           
                             C 
                             r 
                           
                         
                         ) 
                       
                     
                     
                       C 
                       f 
                     
                   
                 
               
               
                 
                   ( 
                   13 
                   ) 
                 
               
             
           
         
       
     
         [0043]    There is one extra term of 
         [0000]    
       
         
           
             
               
                 V 
                 D 
               
                
               
                 C 
                 r 
               
             
             
               C 
               f 
             
           
         
       
     
         [0000]    in Equation (12) compared to Equation (6) and one extra term of 
         [0000]    
       
         
           
             
               
                 - 
                 
                   V 
                   D 
                 
               
                
               
                 C 
                 r 
               
             
             
               C 
               f 
             
           
         
       
     
         [0000]    in equation (13) compared to Equation (7). These two terms have same absolute value with opposite sign. At the following phase as described in paragraph [0034], the two terms will be cancelled out and the transfer function is reduced to the one described in Equation (8). 
         [0044]      FIG. 4   a  to  FIG. 4   c  show the multiple phase operations to linearize the displacement measurement using fully differential structure. This configuration has the advantage of suppression of common mode charge injection, disturbance from supply and disturbance from common mode reference. 
         [0045]      FIG. 4   a  shows a configuration to measure the difference of C s    402  and C g    401  at a first phase, where a differential operational amplifier  420  is employed to regulate the voltage at sense electrode  411  and gap electrode  410 . A full bridge can be built by employing a pair of reference capacitors C refg    441  and C refs    440 . The common terminal  412  of C s    402  and C g    401  which is driven by a negative step voltage V D    432 . A positive step voltage V D    433  drives the shared terminal of reference capacitors C refg    441  and C refs    440 . Input common mode feedback is employed to regulate the inputs of differential operational amplifier  420  to common mode reference voltage V CM    434 , so that the input nodes of the differential operational amplifier  420  behave as virtual ground. Thus, the net charge delivered from input capacitances C g    401  and C refg    441  can be transferred through feedback capacitance C f    443  at a positive path. The net charge delivered from the input capacitances C s    402  and C refs    440  can be transferred through the feedback capacitance C f    444  at a negative path. The positive output voltage V OUTP    430  which is sampled by the load capacitance C Lsp    445  at the end of the first phase operation is given by the equation: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       OUTP_ph 
                        
                       
                           
                       
                        
                       1 
                     
                   
                   = 
                   
                     
                       
                         V 
                         D 
                       
                        
                       
                         ( 
                         
                           
                             C 
                             g 
                           
                           - 
                           
                             C 
                             refg 
                           
                         
                         ) 
                       
                     
                     
                       C 
                       f 
                     
                   
                 
               
               
                 
                   ( 
                   14 
                   ) 
                 
               
             
           
         
       
     
         [0000]    The negative voltage V OUTN    431  which is sampled by the load capacitance C Lsn    446  at the end of the first phase operation is given by the equation: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       OUTN_ph 
                        
                       
                           
                       
                        
                       1 
                     
                   
                   = 
                   
                     
                       
                         V 
                         D 
                       
                        
                       
                         ( 
                         
                           
                             C 
                             s 
                           
                           - 
                           
                             C 
                             refs 
                           
                         
                         ) 
                       
                     
                     
                       C 
                       f 
                     
                   
                 
               
               
                 
                   ( 
                   15 
                   ) 
                 
               
             
           
         
       
     
         [0046]      FIG. 4   b  shows a configuration to linearize the output with respect to C g    401  at a second phase, where both C Lsp    445  and C Lsn    446  which sampled the first phase outputs are connected to the negative input of the differential operational amplifier  420 . The positive charge stored at C Lsp    445  and negative charge stored at C Lsn    446  transfers to the feedback capacitance C g    401 . The positive output voltage V OUTP    430  which is sampled by the load capacitance C Lgp    449  at the end of the second phase operation is given by the equation: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       OUTP_ph 
                        
                       
                           
                       
                        
                       2 
                     
                   
                   = 
                   
                     
                       
                         V 
                         D 
                       
                        
                       
                         ( 
                         
                           
                             
                               C 
                               Lsp 
                             
                              
                             
                               C 
                               g 
                             
                           
                           - 
                           
                             
                               C 
                               Lsn 
                             
                              
                             
                               C 
                               s 
                             
                           
                         
                         ) 
                       
                     
                     
                       
                         C 
                         f 
                       
                        
                       
                         C 
                         g 
                       
                     
                   
                 
               
               
                 
                   ( 
                   16 
                   ) 
                 
               
             
           
         
       
     
         [0000]    C Ls    447 , C Ls    448  and C refg    451  form a pseudo negative path to sample the common mode disturbance, common mode noise and charge injections to suppress the circuit introduced non-idealities. 
         [0047]      FIG. 4   c  shows a configuration to linearize the output with respect to C s    402  at a third phase, where the second phase outputs sampled at C Lgp    449  and C Lgn    450  are connected to the inputs of the differential operational amplifier  420 . The charge stored at C Lgp    449  and C Lgn    450  transfers to a feedback capacitance C s    402 . The output voltage V OUTP    430  which is sampled by the load capacitance C Lp    453  at the end of the third phase operation is given by the equation: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       OUTP_ph 
                        
                       
                           
                       
                        
                       3 
                     
                   
                   = 
                   
                     
                       
                         V 
                         D 
                       
                        
                       
                         
                           C 
                           Lgp 
                         
                          
                         
                           ( 
                           
                             
                               
                                 C 
                                 Lsp 
                               
                                
                               
                                 C 
                                 g 
                               
                             
                             - 
                             
                               
                                 C 
                                 Lsn 
                               
                                
                               
                                 C 
                                 s 
                               
                             
                           
                           ) 
                         
                       
                     
                     
                       
                         C 
                         f 
                       
                        
                       
                         C 
                         g 
                       
                        
                       
                         C 
                         s 
                       
                     
                   
                 
               
               
                 
                   ( 
                   17 
                   ) 
                 
               
             
           
         
       
     
         [0000]    C Lg    452  and C refs    455  form a pseudo negative path to sample the common mode disturbance, common mode noise and charge injections to cancel the circuit introduced non-idealities. 
         [0048]    By setting both C Lsp    445  and C Lsn    446  equal to C Ls  the Equation (18) can be reduced to: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       OUTP_ph 
                        
                       
                           
                       
                        
                       3 
                     
                   
                   = 
                   
                     
                       
                         
                           V 
                           D 
                         
                          
                         
                           C 
                           Lgp 
                         
                          
                         
                           C 
                           Ls 
                         
                       
                       
                         C 
                         f 
                       
                     
                      
                     
                       ( 
                       
                         
                           1 
                           
                             C 
                             g 
                           
                         
                         - 
                         
                           1 
                           
                             C 
                             s 
                           
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   18 
                   ) 
                 
               
             
           
         
       
     
         [0049]    To suppress the common mode disturbance for the intermediate phases and compute the differential outputs of the operational amplifier  420 , a fully differential operational amplifier with output common mode feedback can be employed as described in  FIG. 5   a  to  FIG. 5   c.    
         [0050]      FIG. 5   a  shows a configuration to measure the difference of C s    502  and C g    501  at the first phase, where a differential operational amplifier  520  is employed to regulate the voltage at sense electrode  511  and gap electrode  510 . The common terminal  512  of C s    502  and C g    501  which is driven by a negative step voltage V D    532 . A positive step voltage V D    433  drives the shared terminal of reference capacitors C refg    541  and C refs    540 . Input common mode feedback is employed to regulate the inputs of differential operational amplifier  520  to common mode reference voltage V CM    534 , so that the input nodes of the differential operational amplifier  520  behave as virtual ground. 
         [0051]    Thus, the net charge delivered from input capacitances C g    501  and C refg    541  can be transferred through a feedback capacitance C f    543  at positive path and sampled by capacitor C a    560 . The net charge delivered from input capacitances C s    502  and C refs    540  can be transferred through the feedback capacitance C f    544  at negative path and sampled by capacitor C a    561 . A fully differential operational amplifier  521  with two feedback capacitors C af    562  and  563  computes the voltage difference sampled at capacitors C a    560  and  561 . To attenuate the common mode disturbance at outputs of the differential operational amplifier  520 , an output common mode feedback is employed at the differential operational amplifier  521  so that the common mode of V OUTP  and V OUTN  is regulated to common mode voltage V CM    534 . The positive output voltage V OUTP    530  which is sampled by the load capacitance C Lsp    545  at the end of the first phase operation is given by the equation: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       OUTP_ph 
                        
                       
                           
                       
                        
                       1 
                     
                   
                   = 
                   
                     
                       V 
                       CM 
                     
                     + 
                     
                       
                         
                           V 
                           D 
                         
                          
                         
                           
                             C 
                             a 
                           
                            
                           
                             ( 
                             
                               
                                 C 
                                 g 
                               
                               - 
                               
                                 C 
                                 s 
                               
                             
                             ) 
                           
                         
                       
                       
                         2 
                          
                         
                             
                         
                          
                         
                           C 
                           af 
                         
                          
                         
                           C 
                           f 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   19 
                   ) 
                 
               
             
           
         
       
     
         [0000]    The negative voltage V OUTN    531  which is sampled by the load capacitance C Lsn  at the end of the first phase operation is given by the equation: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       OUTN_ph 
                        
                       
                           
                       
                        
                       1 
                     
                   
                   = 
                   
                     
                       V 
                       CM 
                     
                     - 
                     
                       
                         
                           V 
                           D 
                         
                          
                         
                           
                             C 
                             a 
                           
                            
                           
                             ( 
                             
                               
                                 C 
                                 g 
                               
                               - 
                               
                                 C 
                                 s 
                               
                             
                             ) 
                           
                         
                       
                       
                         2 
                          
                         
                             
                         
                          
                         
                           C 
                           af 
                         
                          
                         
                           C 
                           f 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   20 
                   ) 
                 
               
             
           
         
       
     
         [0052]      FIG. 5   b  shows a configuration to linearize the output with respect to C g    501  at a second phase, where C Lsn    546  which sampled the first phase output is connected to the negative input of the differential operational amplifier  520 . The charge stored at C Lsn    546  transfers to the feedback capacitances C g    501 . C Ls    547  and C refg    551  to form a pseudo negative path to sample the common mode disturbance, common mode noise and charge injections to cancel the circuit introduced non-idealities. C a    560  and  561  sample the outputs of differential operational amplifier  520 . The positive output voltage V OUTP    530  which is sampled by the load capacitance C Lgp    549  at the end of the second phase operation is given by the equation: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       OUTP_ph 
                        
                       
                           
                       
                        
                       2 
                     
                   
                   = 
                   
                     
                       V 
                       CM 
                     
                     + 
                     
                       
                         
                           V 
                           D 
                         
                          
                         
                           C 
                           Lsn 
                         
                          
                         
                           C 
                           a 
                         
                          
                         
                           
                             C 
                             a 
                           
                            
                           
                             ( 
                             
                               
                                 C 
                                 g 
                               
                               - 
                               
                                 C 
                                 s 
                               
                             
                             ) 
                           
                         
                       
                       
                         4 
                          
                         
                             
                         
                          
                         
                           C 
                           af 
                         
                          
                         
                           C 
                           af 
                         
                          
                         
                           C 
                           f 
                         
                          
                         
                           C 
                           g 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   21 
                   ) 
                 
               
             
           
         
       
     
         [0000]    The negative voltage V OUTN    531  which is sampled by the load capacitance C Lgn    550  at the end of the second phase operation is given by the equation: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       OUTN_ph 
                        
                       
                           
                       
                        
                       2 
                     
                   
                   = 
                   
                     
                       V 
                       CM 
                     
                     - 
                     
                       
                         
                           V 
                           D 
                         
                          
                         
                           C 
                           Lsn 
                         
                          
                         
                           C 
                           a 
                         
                          
                         
                           
                             C 
                             a 
                           
                            
                           
                             ( 
                             
                               
                                 C 
                                 g 
                               
                               - 
                               
                                 C 
                                 s 
                               
                             
                             ) 
                           
                         
                       
                       
                         4 
                          
                         
                             
                         
                          
                         
                           C 
                           af 
                         
                          
                         
                           C 
                           af 
                         
                          
                         
                           C 
                           f 
                         
                          
                         
                           C 
                           g 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   22 
                   ) 
                 
               
             
           
         
       
     
         [0053]      FIG. 5   c  shows a configuration to linearize the output with respect to C s    502  at the third phase, where the second phase output sampled at C Lgn    550  is connected to the inputs of the differential operational amplifier  520 . The charge stored at C Lgn    550  transfers to a feedback capacitance C s    502 . C Lg    551  and C refs    540  form a pseudo negative path to sample the common mode disturbance, common mode noise and charge injections to cancel the circuit introduced non-idealities The output voltage V OUTP    530  which is sampled by the load capacitance C Lp    553  at the end of the third phase operation is given by: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       OUTP_ph 
                        
                       
                           
                       
                        
                       3 
                     
                   
                   = 
                   
                     
                       V 
                       CM 
                     
                     + 
                     
                       
                         
                           V 
                           D 
                         
                          
                         
                           C 
                           Lsn 
                         
                          
                         
                           C 
                           Lgn 
                         
                          
                         
                           C 
                           a 
                         
                          
                         
                           C 
                           a 
                         
                          
                         
                           
                             C 
                             a 
                           
                            
                           
                             ( 
                             
                               
                                 C 
                                 g 
                               
                               - 
                               
                                 C 
                                 s 
                               
                             
                             ) 
                           
                         
                       
                       
                         8 
                          
                         
                             
                         
                          
                         
                           C 
                           af 
                         
                          
                         
                           C 
                           af 
                         
                          
                         
                           C 
                           af 
                         
                          
                         
                           C 
                           f 
                         
                          
                         
                           C 
                           g 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   23 
                   ) 
                 
               
             
           
         
       
     
         [0000]    The negative voltage V OUTN    531  which is sampled by the load capacitance C Ln    554  at the end of the third phase operation is given by: 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     
                       OUTN_ph 
                        
                       
                           
                       
                        
                       3 
                     
                   
                   = 
                   
                     
                       V 
                       CM 
                     
                     - 
                     
                       
                         
                           V 
                           D 
                         
                          
                         
                           C 
                           Lsn 
                         
                          
                         
                           C 
                           Lgn 
                         
                          
                         
                           C 
                           a 
                         
                          
                         
                           C 
                           a 
                         
                          
                         
                           
                             C 
                             a 
                           
                            
                           
                             ( 
                             
                               
                                 C 
                                 g 
                               
                               - 
                               
                                 C 
                                 s 
                               
                             
                             ) 
                           
                         
                       
                       
                         8 
                          
                         
                             
                         
                          
                         
                           C 
                           af 
                         
                          
                         
                           C 
                           af 
                         
                          
                         
                           C 
                           af 
                         
                          
                         
                           C 
                           f 
                         
                          
                         
                           C 
                           g 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   24 
                   ) 
                 
               
             
           
         
       
     
         [0054]    The differential output is difference between V OUTP     —     ph3  and V OUTN     —     ph3 . 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     OUTP_diff 
                   
                   = 
                   
                     
                       
                         V 
                         D 
                       
                        
                       
                         C 
                         Lsn 
                       
                        
                       
                         C 
                         Lgn 
                       
                        
                       
                         C 
                         a 
                       
                        
                       
                         C 
                         a 
                       
                        
                       
                         
                           C 
                           a 
                         
                          
                         
                           ( 
                           
                             
                               C 
                               g 
                             
                             - 
                             
                               C 
                               s 
                             
                           
                           ) 
                         
                       
                     
                     
                       4 
                        
                       
                         C 
                         af 
                       
                        
                       
                         C 
                         af 
                       
                        
                       
                         C 
                         af 
                       
                        
                       
                         C 
                         f 
                       
                        
                       
                         C 
                         g 
                       
                     
                   
                 
               
               
                 
                   ( 
                   25 
                   ) 
                 
               
             
           
         
       
     
         [0055]    By setting both C Lsp    445  and C Lsn    446  equal to C Ls , C a    560  and  561  are equal to two times of the feedback capacitor C af    562  and  563 , therefore Equation 25 is reduced to 
         [0000]    
       
         
           
             
               
                 
                   
                     V 
                     OUTP_diff 
                   
                   = 
                   
                     
                       
                         2 
                          
                         
                             
                         
                          
                         
                           V 
                           D 
                         
                          
                         
                           C 
                           Lgp 
                         
                          
                         
                           C 
                           Ls 
                         
                       
                       
                         C 
                         f 
                       
                     
                      
                     
                       ( 
                       
                         
                           1 
                           
                             C 
                             g 
                           
                         
                         - 
                         
                           1 
                           
                             C 
                             s 
                           
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   26 
                   ) 
                 
               
             
           
         
       
     
         [0056]    The method of the measuring displacement of a sensor structure which provides two capacitors is summarized in  FIG. 6 . The two capacitors in the structure share a common terminal and the displacement of one of or both of the capacitors is changing accordingly with applied force. The first step  601  is to provide the first capacitance. The second step  602  is to provide the second capacitance. The difference of the inverse of the result generated in  601  and the inverse of the result generated in  602  can be determined in the third step  603 . The output of the step  603  is proportional to the difference of displacements of the two capacitors. 
         [0057]    Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the present invention.