Abstract:
By using special frequency response manipulation in the difference channel of a stereo signal, the stereo image appears to extend beyond the actual placement of the loudspeakers. This is accomplished by shaping the difference channel response to simulate the response one would be subjected to if the sources were physically moved to the virtual position, and by additionally cancelling the crosstalk effect in each channel.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field Of The Invention  
           [0002]    The subject invention relates to a signal processing circuit for enhancing a stereo image that corresponds to a stereo audio signal.  
           [0003]    2. Description Of The Related Art  
           [0004]    In conventional stereo systems, the amplifying circuits amplify the left and right channel signals and pass these amplified signals to left and right channel loudspeakers. This is done in an attempt to simulate the experience of a live performance in which the reproduced sounds emanate from different locations. Since the advent of stereo systems, there has been continual development of systems which more closely simulate this experience of a live performance. For example, in the early to mid 1970&#39;s, four-channel stereo systems were developed which included two front left and right channel loudspeakers and two rear left and right channel loudspeakers. These systems attempted to recapture the information contained in signals reflected from the back of a room in which a live performance was being held. More recently, surround sound systems are currently on the market which, in effect, seek to accomplish the same effect.  
           [0005]    A drawback of these systems is that there are four or more channels of signals being generated and a person must first purchase the additional loudspeakers and then solve the problem of locating the multiple loudspeakers for the system.  
           [0006]    U.S. Pat. No. 5,761,313 discloses a circuit for improving the stereo image separation of a stereo signal in which spatial frequency response manipulation in the different channels of a stereo system is used to cause the stereo image to appear to extend beyond the actual placement of the loudspeakers. This is accomplished by shaping the difference channel response to simulate the response one would be subjected to if the sources were physically moved to the virtual positions.  
           [0007]    U.S. Pat. No. 4,349,698 discloses that a stereo widening effect may be achieved by examining the head related transfer functions at different source positions and incorporating the response characteristics that are obtained in the (L−R) part of the stereo signal.  
         SUMMARY OF THE INVENTION  
         [0008]    It is an object of the present invention to further enhance the stereo image of an input stereo signal to achieve a greater stereo spread than that exhibited in the prior art.  
           [0009]    The above object is achieved in a circuit arrangement for improving the stereo image separation in a stereo signal comprising a first and a second input for receiving, respectively, a left and a right channel signal of an input stereo signal; a summing and equalizing circuit having a first and a second input coupled, respectively, to said first and second inputs of said circuit arrangement, for receiving said left and right channel signals, means for summing the left and right channel signals thereby forming a sum signal, and a first and a second output for supplying the sum signal; a difference and equalizing circuit having a first and a second input coupled, respectively, to said first and second inputs of said circuit arrangement, for receiving said left and right channel signals, means for subtracting the right channel signal from the left channel signal forming a difference signal, means for performing and equalization on said difference signal, said equalization having characteristics of an ear of a human being, means for processing said difference signal in order to effectively cancel crosstalk effects of the left channel signal reaching the right channel output and the right channel signal reaching the left channel output, and first and second outputs for providing, respectively, the equalized difference signal; first means for combining the first output of said summing and frequency equalizing circuit with the first output of said difference and frequency equalizing circuit to form a modified left channel output signal; second means for combining the second output of said summing and frequency equalizing circuit with the second output of said difference and frequency equalizing circuit to form a modified right channel output signal; and first and second outputs for providing said modified left and right channel output signals, respectively.  
           [0010]    Applicant has found that by cancelling the effects of crosstalk in the left or right signals reaching the ear of a listener, in addition to creating a frequency response that simulates the response correction that is necessary when the sound source is moved from a position directly in front of the listener to a position 90 degrees to the side of the listener, a signal is then presented to each ear of a listener that not only has the correct frequency response correction based on source positioning, but also isolates the source to the proper ear.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    With the above and additional objects and advantages in mind as will hereinafter appear, the invention will be described with reference to the accompanying drawings, in which:  
         [0012]    [0012]FIG. 1 is a block diagram of the circuit of the invention;  
         [0013]    [0013]FIG. 2 is a schematic block diagram of a first embodiment of the circuit of the invention;  
         [0014]    [0014]FIGS. 3 and 4 show response curves for the embodiment of FIG. 2;  
         [0015]    [0015]FIG. 5 is a schematic block diagram of a second embodiment of the circuit of the invention;  
         [0016]    FIGS.  6 - 8  show response curves for the embodiment of FIG. 5;  
         [0017]    [0017]FIG. 9 is a schematic block diagram of a third embodiment of the circuit of the invention; and  
         [0018]    [0018]FIGS. 10 and 11 show response curves for the embodiment of FIG. 9. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0019]    [0019]FIG. 1 shows a basic schematic block diagram of the subject invention. A first and a second input  10  and  12  receive the left and right channel signals from a stereo signal source. The left channel signal is applied both to a first input of a summing and frequency equalizing circuit  14  and to a first input of a difference and frequency equalizing circuit  16 . The right channel signal is similarly both to a second input of the summing and frequency equalizing circuit  14  and to a second input of the difference and frequency equalizing circuit  16 . The summing and frequency equalizing circuit  14  adds the signals applied to its first and second inputs and then optionally performs a high frequency equalization on the combined signal (L+R). This combined signal is then supplied to a first and a second output of the summing and frequency equalizing circuit  14 .  
         [0020]    The difference and frequency equalizing circuit  16  forms a first and a second difference signal (L−R and R−L), from the left and right channel signals applied to the first and second inputs. The difference and frequency equalizing circuit  16  then performs a frequency equalization, with respect to the response of the ear of a person on the difference signal to shape the response to simulate that which would be perceived by the person if the sound sources (loudspeakers) were actually placed at virtual positions, i.e., wider and directly opposite the persons ears. In addition, the difference and frequency equalizing circuit  16  further cancels the crosstalk effect of the left or right channel signal reaching the respective opposite ear. As such, the difference and frequency equalizing circuit  16  not only performs a frequency response correction based on source positioning, but also isolates the source to the proper ear.  
         [0021]    The processed difference signal (L−R) is applied to a first output of the difference and frequency equalizing circuit  16  while the processed difference signal (R−L) is applied to a second output of the difference and frequency equalizing circuit  16 . The first output of the difference and frequency equalizing circuit  16  is combined with one of the outputs of the summing and frequency equalizing circuit  14  to form the left channel output signal  18 , and the second output of the difference and frequency equalizing circuit  16  is combined with the other output of the summing and frequency equalizing circuit  14  to form the right channel output signal  20 .  
         [0022]    [0022]FIG. 2 shows a schematic diagram of a first embodiment of the circuit arrangement of FIG. 1. The left channel input  10  is applied to a capacitor C 10  and then through a resistor R 10  to the non-inverting input of a first operation amplifier (OP-AMP) A 1 . The inverting input of OP-AMP A 1  is connected to the output through a resistor R 11  and to ground via a resistor R 12  and via the series combination of a resistor R 13  and a capacitor C 11 .  
         [0023]    The right channel input  12  is applied to a capacitor C 12  and then through a resistor R 14 , shunted by a capacitor C 13 , and a resistor R 15  to the non-inverting input of OP-AMP A 2 , which is further connected to ground via a resistor R 16 . The right channel input  12  is also connected, via the capacitor C 12 , to a resistor R 17  connected to the non-inverting input of OP-AMP A 1 . In addition, the left channel input  10  is also connected, via the capacitor C 10 , through a resistor R 18 , shunted by a capacitor C 14 , and a resistor R 19 , to the inverting input of OP-AMP A 2 .  
         [0024]    A resistor R 20  connects the inverting input of OP-AMP A 2  to its output, which is in turn connected through resistor R 21  to the non-inverting input of OP-AMP A 3 , which is connected to ground via a resistor R 22 . The output of OP-AMP A 2  is further connected to the inverting input of OP-AMP A 3  through the series arrangement of a resistor R 23  and a capacitor C 15 . The inverting input of OP-AMP A 3  is connected to its output via a resistor R 24 , while the junction between resistor R 23  and capacitor C 15  is connected to the output of OP-AMP A 3  via a capacitor C 16 .  
         [0025]    The output of OP-AMP A 3  is connected, on the one hand, to the inverting input of OP-AMP A 4  via the combination of a resistor R 25  and a capacitor C 17 , and, on the other hand, to the non-inverting input of OP-AMP A 4  via a resistor R 26 , which is connected to ground through a resistor R 27 . A resistor R 28  connects the inventing input of OP-AMP A 4  to its output, while a capacitor C 18  connects the junction between resistor R 25  and capacitor C 17  to the output of OP-AMP A 4 .  
         [0026]    The serial arrangement of resistors R 29 , R 30  and R 31  connects the output of OP-AMP A 4  to the non-inverting input of OP-AMP A 5 , which is further connected to ground via a capacitor C 19 . A resistor R 32  connects the output of OP-AMP A 2  to the junction between resistors R 29  and R 30 . The inverting input of OP-AMP AS is connected directly to the output thereof, while a capacitor C 20  connects the junction between resistors R 30  and R 31  to the output.  
         [0027]    The output of OP-AMP A 5  is connected to the right channel output  20  of the circuit arrangement via a resistor R 33 , and is further connected to the inverting input of OP-AMP A 6  via a resistor R 34 , the non-inverting input being connected to ground. A resistor R 35  connects the inverting input of OP-AMP A 6  to its output which is then connected to the left channel output  18  via a resistor R 36 . A pair of resistors R 37  and R 38  interconnect the left and right channel outputs  18  and  20 , while the output from OP-AMP A 1  is connected to the junction between the resistors R 37  and R 38 .  
         [0028]    In FIG. 2, OP-AMP A 1  acts as the summing portion of circuit  14  in FIG. 1 for summing the left and right channel signals, and also performs a high frequency equalization on this sum signal (L+R). OP-AMP A 2  forms the difference between the right and left channel signals (R−L), while OP-AMP&#39;s A 3  and A 4  together form a mid- and high-range human ear equalizer (part of circuit  16  in FIG. 1). By processing this equalized version of the difference signal (R−L) from OP-AMP A 5  as well as its inverse (L−R) formed in OP-AMP A 6 , along with the equalized sum signal (L+R) in the resistance bridge formed by resistors R 37  and R 38 , any crosstalk is removed from the left and right channel output signals.  
         [0029]    [0029]FIGS. 3 and 4 show response curves for the first embodiment of FIG. 2, where FIG. 3 shows the response curve of a driven channel (left or right) as compared to the crosstalk channel, and FIG. 4 shows the response curve of either the left or right channel as compared to the monaural channel (at the output of OP-AMP A 1 ).  
         [0030]    [0030]FIG. 5 is a schematic diagram of a second embodiment of the circuit arrangement of the subject invention. The left channel input  10  is applied to a capacitor C 40  and then through resistors R 40  and R 41  to the non-inverting input of OP-AMP A 11 . The right channel input  12  is applied to a capacitor C 41  and then through a resistor R 42  to the junction of resistors R 40  and R 41 . A resistor R 43  connects the inverting input of OP-AMP A 11  to its output which is then connected through the series arrangement of a resistor R 44  and a capacitor C 42  to the left channel output  18 , which is connected to ground through a resistor R 45 .  
         [0031]    The left channel input  10  is also connected, through the capacitor C 40  and a resistor R 46 , to the inverting input of OP-AMP A 12 , while the right channel input  12  is connected, through the capacitor C 41  and a resistor R 47 , to the non-inverting input of OP-AMP A 12 . A resistor R 48  connects the inverting input of OP-AMP A 12  to its output which is connected through the parallel combination of capacitor C 44  and resistor R 49 , in series with capacitor C 45 , to the inverting input of OP-AMP A 13 , the junction between resistor R 49  and capacitor C 45  being connected to ground through resistor R 50 , and to the output of OP-AMP A 13  through a capacitor C 46 . The inverting input of OP-AMP A 13  is connected to its output through resistor R 51 . The inverting input of OP-AMP A 12  is connected to the non-inverting input of OP-AMP A 13  through a resistor R 52 .  
         [0032]    The output of OP-AMP A 12  is further connected through a resistor R 53 , resistor R 54  and a parallel combination of a resistor R 55  and a capacitor C 47  to the inverting input of OP-AMP A 14 . The resistor R 54  is shunted by the series arrangement of capacitors C 48  and C 49 , in which the junction between these capacitors is connected to ground through a resistor R 56 . A series arrangement of resistors R 57  and R 58  connect the inverting input of OP-AMP A 14  to its output, while a series arrangement of a capacitor C 50  and a resistor R 59  connect the junction between the resistors R 57  and R 58  to ground, a capacitor C 51  connecting the output of OP-AMP A 14  to the junction between the capacitor C 50  and the resistor R 59 . A resistor R 60  connects the non-inverting input of OP-AMP A 12  to the non-inverting input of OP-AMP A 14 .  
         [0033]    A series arrangement of resistors R 61  and R 62  connect the output of OP-AMP A 14  to the non-inverting input of OP-AMP A 15 , a capacitor C 52  connecting the non-inverting input to ground. The inverting input of OP-AMP A 15  is connected to its output. A resistor R 63  connects the output from OP-AMP A 13  to the junction between the resistors R 61  and R 62 , which is connected to the output of OP-AMP A 15  through a capacitor C 53 . A resistor R 64  connects the junction between the resistor R 44  and capacitor C 42  (at the output of OP-AMP A 11 ) to the output of OP-AMP A 15 .  
         [0034]    The output of OP-AMP A 15  is connect to the inverting input of OP-AMP A 16  through a resistor R 65 , while a resistor R 66  connects the non-inverting inputs of OP-AMP&#39;s A 13  and A 14  to the non-inverting input of OP-AMP A 16 , which is further connected to the output of OP-AMP A 11  through a resistor R 67 . The connection between the non-inverting input of OP-AMP A 14  and the resistor R 66  is connected to ground through the parallel arrangement if a capacitor C 54  and a resistor R 68 . A resistor R 69  connects the inverting input of OP-AMP A 16  to its output, which is connected, through capacitor C 55 , to the right channel output  20 , this output being connected to ground through a resistor R 70 .  
         [0035]    In FIG. 5, the sum signal (R+L) is formed at the non-inverting input of OP-AMP A 11 , while OP-AMP A 12  forms the difference signal (R−L). OP-AMP A 13  receives a first equalized version of the difference signal (R−L) and produces a first equalized “(L−R)” signal. OP-AMP A 14  also receives a second equalized version of the difference signal (R−L) and produces a second equalized “(L−R)” signal. These two “(L−R)” signals are combined at the input of OP-AMP A 15  which applies the resulting “(L−R)” signal to the inverting input of OP-AMP A 16 . The OP-AMP A 16  receives at its non-inverting input the sum signal, and as such, produces the right channel output signal. The OP-AMP A 11  supplies the sum signal “(L+R)” at its output. When the “(L+R)” signal at the output of OP-AMP A 11  is combined with the “(L−R)” signal from the output of OP-AMP A 15  at the junction of resistor R 44  and capacitor C 42 , the left channel output signal is formed.  
         [0036]    FIGS.  6 - 8  show response curves for the second embodiment of FIG. 5, where FIG. 6 shows the response curve of one driven channel as compared with the monaural (L+R) response, FIG. 7 shows the response curve of one driven channel as compared with the crosstalk channel, as well as the phase of the driven channel, and FIG. 8 shows the response curve of the difference (L−R) channel (at the output of OP-AMP A 15 ).  
         [0037]    [0037]FIG. 9 is a schematic diagram of a third embodiment of the circuit arrangement of the subject invention. The left channel input, coupled to ground via a resistor R 80 , is connected through the series arrangement of a capacitor C 80 , and a pair of resistors R 81  and R 82 , to the non-inverting input of OP-AMP A 21 , which is connected to ground via a capacitor C 81 . The right channel input, coupled to ground via a resistor R 83 , is connected through a capacitor C 82  and a resistor R 84  to the junction between resistors R 81  and R 82 , this junction being connected to the output of OP-AMP A 21  via a capacitor C 83 . A resistor R 85  connects the inverting input of OP-AMP A 21  to its output, which is connected via a resistor R 86  and a capacitor C 84  to the left channel output  18 , which is connected to ground via a resistor R 87 .  
         [0038]    The junction between capacitor C 80  and resistor R 81  is connected, via a resistor R 88 , to the inverting input of OP-AMP A 22 , this inverting input being connected to the output via a resistor R 89 . A pair of resistors R 90  and R 91  connect a voltage source Vcc to ground, the junction between these resistors being connected to ground via a capacitor C 84  and to the non-inverting input of OP-AMP A 22 .  
         [0039]    The junction between capacitor C 82  and resistor R 84  is connected, on the one hand, through the series arrangement of a capacitor C 86  and a resistor R 92 , and, on the other hand, through a resistor R 93 , to the inverting input of OP-AMP A 23 . The output of OP-AMP A 22  is connected, on the one hand, through a resistor R 94 , and, on the other hand, through the series arrangement of a capacitor C 87  and a resistor R 95 , also to the inverting input of OP-AMP A 23 . The non-inverting input of OP-AMP A 23  is connected to the non-inverting input of OP-AMP A 22 . The inverting input of OP-AMP A 23  is connected to its output via the series arrangement of resistors R 96  and R 97 , in which the junction between these resistors is connected to ground via the series arrangement of a capacitor C 88  and a resistor R 98 , while a capacitor C 89  connects the output of OP-AMP A 23  to the junction between capacitor C 88  and resistor R 98 .  
         [0040]    The junction between capacitor C 82  and resistor R 84  is further connected, via a resistor R 99  and a capacitor C 90  to the inverting input of OP-AMP A 24 , while output of OP-AMP A 22  is connected through a resistor R 100  to the junction between resistor R 99  and capacitor C 90 . The non-inverting input of OP-AMP A 23  is connected to the non-inverting input of OP-AMP A 24 , which is connected to the junction between resistor R 99  and capacitor C 90  by a resistor R 101 . A resistor R 102  connects the inverting input of OP-AMP A 24  to its output while a capacitor C 91  connects the junction between resistor R 99  and capacitor C 90  to the output.  
         [0041]    The output of OP-AMP A 23  is connected through resistors R 103  and R 104  to the non-inverting input of OP-AMP A 25 , which is connected to ground via a capacitor C 92 , and the output of OP-AMP A 24  is connected to the junction of resistors R 103  and R 104  through a resistor R 105 , which is, in turn, connected to the output of OP-AMP A 25  through a capacitor C 93 . The non-inverting input of OP-AMP A 24  is connected, through a resistor R 106 , to the inverting input of OP-AMP A 25 , which is connected, through a resistor R 107 , to its output.  
         [0042]    The output of OP-AMP A 25  is connected, on the one hand, to the junction between resistor R 86  and capacitor C 84  through a resistor R 108 , and, on the other hand, to the inverting input of OP-AMP A 26  through a resistor R 109 . Resistors R 110  and R 111  connect the inverting input of OP-AMP A 21  to the non-inverting input of OP-AMP A 26 , while the junction between resistors R 110  and R 111  is connected to the non-inverting input of OP-AMP A 24 . A resistor R 113  connects the inverting input of OP-AMP A 26  to its output which is connected, through a capacitor C 94 , to the right channel output  20 , which is connected to ground via a resistor R 114 .  
         [0043]    [0043]FIGS. 10 and 11 show response curves for the third embodiment of FIG. 9, where FIG. 10 shows the response curve of a driven channel as compared to the crosstalk channel, and FIG. 11 shows the response curve of either the left or right channel as compared to the monaural (L+R) channel (at the output of OP-AMP A 21 ).  
         [0044]    The values of the circuit components used in FIGS. 2, 5 and  9  are as follows:  
                                                                                                                      RESISTORS   VALUE (in ohms)                       R10, R17    22K           R11, R28    39K           R12, R13, R15, R19, R25    10K           R14, R18    33K           R16, R20    68K           R21, R22, R26, R27    47K           R23   8.2K           R24    30K           R29   1.5K           R30    13K           R31    15K           R32   5.1K           R33, R34, R35, R36     1K           R37, R38   3.9K                            CAPACITORS   VALUE                            C10, C12   5   μF           C11   1.5   NF           C13, C14   68   NF           C15, C16   2.7   NF           C17, C18, C20   4.7   NF           C19   330   PF                      
 
         [0045]    [0045]                                                                                                                      RESISTORS   VALUE (in ohms)                       R40, R42, R48, R60   22K           R41, R43, R52, R62   15K           R44, R64, R68    1K           R45, R70   100K            R46, R47, R66, R69   10K           R49   27K           R50, R56, R59   1.1K            R51   220K            R53   4.7K            R54   6.8K            R55, R63   33K           R57   5.6K            R58   68K           R61   30K           R65, R67   20K                            CAPACITORS   VALUE                            C40, C41, C42, C55   5   μF           C43   1   NF           C44   680   PF           C45, C46   3.3   NF           C47   6.8   NF           C48, C49, C50, C51, C53   33   NF           C52   47   PF           C54   100   μF                        
         [0046]    [0046]                                                                                                              RESISTORS   VALUE (in ohms)               R80, R83, R87, R114   100K        R81, R84, R85, R106, R107, R110, R111, R113   10K       R82   15K       R86, R90, R91, R108    1K       R88, R89   22K       R92, R94   3.9K        R93, R95, R99, R100, R103, R105   33K       R96   5.6K        R97   47K       R98   1.8K        R101   1.1K        R102   220K        R104, R109, R112   20K                        CAPACITORS   VALUE                            C80, C82, C84, C94   5   μF           C81   1   NF           C83   2.2   NF           C85   100   μF           C86, C87   2.7   NF           C88, C89   33   NF           C90, C91   3.3   NF           C92   750   PF           C93   1.5   NF                        
         [0047]    Numerous alterations and modifications of the structure herein disclosed will present themselves to those skilled in the art. However, it is to be understood that the above described embodiment is for purposes of illustration only and not to be construed as a limitation of the invention. All such modifications which do not depart from the spirit of the invention are intended to be included within the scope of the appended claims.