Abstract:
Techniques are provided for applying modulation constraints to data streams using a short block encoder. A short block encoder encodes a subset of the bits in a data stream. Then, the even and odd interleaves in a data stream are separated into two data paths. A first modulation encoder encodes the even interleave according to a first modulation constraint. A second modulation encoder encodes the odd interleave according to a second modulation constraint, which in general coincides with the modulation constraint for even interleave.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to techniques for imposing modulation constraints on data using short block encoders, and more particularly, to techniques for imposing modulation constraints on a subset of bits in each data block using a short block encoder prior to imposing modulation constraints on the even and odd interleaves. 
     A disk drive can write data bits onto a data storage disk such as a magnetic hard disk. The disk drive can also read data bits that have been stored on a data disk. Certain sequences of data bits are difficult to write onto a disk and often cause errors during read-back of the data. 
     Binary sequences are routinely transformed from one representation to another using precoders and inverse precoders, according to well known techniques. In describing this invention all binary sequences are represented as PR4 sequences that can be transformed into an NRZI representation by a precoder that convolves with 1/1+D or into an NRZ representation by a precoder which convolves with 1/(1+D 2 ). 
     Long sequences of consecutive zeros (e.g., 40 consecutive zeros) are examples of data bit patterns that are prone to errors. A long sequence of zeros in alternating positions (e.g., 0a0b0c0d0 . . . , where a, b, c, d may be 0 or 1) is another example of an error prone data bit pattern. 
     Therefore, it is desirable to eliminate error prone bit sequences in user input data. Eliminating error prone bit sequences ensures reliable operation of the detector and timing loops in a disk drive system. One way to eliminate error prone bit sequences is to substitute the error prone bit sequences with non-error prone bit patterns that are stored in memory in lookup tables. Lookup tables, however, are undesirable for performing substitutions of very long bit sequences, because they require a large amount of memory. 
     Many disk drives have a modulation encoder. A modulation encoder uses modulation codes to eliminate sequences of bits that are prone to errors. Fibonacci codes are one example of modulation codes that are used by modulation encoders. Fibonacci codes provide an efficient way to impose modulation code constraints on recorded data to eliminate error prone bit sequences. 
     A Fibonacci encoder maps an input number to an equivalent number representation in a Fibonacci base. A Fibonacci encoder maps an input vector with K bits to an output vector with N bits. A Fibonacci encoder uses a base with N vectors, which is stored as an N×K binary matrix. Successive application of Euclid&#39;s algorithm to the input vector with respect to the stored base gives an encoded vector of length N. 
     Fibonacci codes are naturally constructed to eliminate long runs of consecutive one digits. This is expressed in the literature as the j constraint, where the parameter j enumerates the longest permitted run of ones. A trivial modification of the Fibonacci code is formed by inverting the encoded sequence. This inverted Fibonacci code eliminates long runs of consecutive zero digits. This constraint is expressed in the literature variously as the k constraint or G constraint, where the parameter k (or G) enumerates the longest permitted run of zeros. 
     Maximum transition run (MTR) codes are one specific type of modulation codes that are used in conjunction with 1/(1+D) precoders. With respect to MTR codes, a j constraint refers to the maximum number of consecutive ones, a k constraint refers to the maximum number of consecutive zeros, and a t constraint refers to the maximum number of consecutive pairs of the same bits (e.g., aabbccddee . . . ). 
     Error prone sequences of the form 0a0b0c0d0 as described above are eliminated by the I constraint where the parameter I enumerates the longest run of consecutive zeros in even or odd subsequences. It therefore be desirable to provide modulation encoders extend the Fibonacci codes construction to encompass combined G and I constraints. 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention provides techniques for applying modulation constraints to data streams using a short block encoder. A short block encoder applies a modulation constraint to a subset of the bits in each data block. Then, the even and odd interleaves in a data block are separated into two data paths. A first modulation encoder encodes the even bits according to a modulation constraint for even bits. A second modulation encoder encodes the odd bits according to a modulation constraint for odd bits, which in general coincides with the modulation constraint for even bits. The constrained even and odd interleaves are then interleaved to form one serial data stream. 
     According to an embodiment of the present invention, a short block encoder of the present invention improves the rate of the resulting interleaved code by allowing the even bit and the odd bit modulation encoders to map M-bit input vectors to M-bit output vectors. The overall code transforms (2M−1)-bit vectors into 2M-bit vectors. 
     Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a modulation encoding scheme that includes a short block encoder and that applies modulation constraints to even and odd interleaves separately, according to an embodiment of the present invention. 
         FIG. 2  illustrates an example of a modulation encoding scheme that uses a 3/4 short block encoder, according to an embodiment of the present invention. 
         FIG. 3  illustrates an example of a modulation encoding scheme that uses a 9/10 short block encoder, according to an embodiment of the present invention. 
         FIG. 4  illustrates an example of a modulation encoding scheme that uses a 13/14 short block encoder, according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 1  illustrates a generalized embodiment of a modulation encoding scheme of the present invention. The embodiment of  FIG. 1  has a short block encoder that applies modulation constraints to a subset of each data block. A demultiplexer separates the even and odd interleaves in the data block including the bits generated by the short block encoder. Two modulation encoders then apply constraints to the even and odd interleaves separately. 
     The embodiment of  FIG. 1  has two Fibonacci encoders that map N bit input numbers to N bit output numbers. The modulation encoding scheme of  FIG. 1  is able to perform N-bit to N-bit mappings on interleaved data by adding a short block encoder  101  to the data before the data is modulation encoded. The short block encoder applies a constraint to the data that reduces the number of possible values of the data. This technique allows the modulation encoders to map a reduced set of N-bit input numbers to N-bit output numbers on an N-bit to N-bit basis, even though the N-bit output numbers are constrained to having less than 2 N  possible values. 
     In the embodiment of  FIG. 1 , a portion P of 2N−X bits are fed into a short block encoder  101 . Short block encoder  101  substitutes the first P bits in the block of data with a set of P+X short block bits. Short block encoder  101  can, for example, be a lookup table that maps each possible set of P bits in the user data to a set of P+X short block bits. The P+X short block bits are selected from the table and substituted for the P bits. Short block encoder  101  performs a simple mapping of P bits into P+X bits to enforce a particular set of constraints in order to reduce the number of possible values of each block of the input data. 
     Demultiplexer  102  receives the P+X output bits of encoder  101  and the remaining 2N−X−P bits of the data block. Demultiplexer  102  divides the resulting 2N data bits into its even and odd interleaves. 
     Fibonacci encoder  103  converts the N even interleaves into N output bits that are constrained according to a global even bit constraint Ge using a Fibonacci base. Fibonacci encoder  104  converts the N odd interleaves into N output bits that are constrained according to a global odd bit constraint Go using a Fibonacci base. Fibonacci encoders  103  and  104  both convert reduced N bit input numbers into N bit output numbers, thus performing N-bit to N-bit mappings. According to further embodiments of the present invention, encoders  103  and  104  can also be other types modulation encoders other than Fibonacci encoders. 
     Multiplexer  105  interleaves the constrained even and odd bits to generate the interleaved data output vectors. For each block of 2N−X data bits input into the system of  FIG. 1 , 2N bits are generated at the output of multiplexer  105 . The extra X bits are added by short block encoder  101 . 
     The output vectors of multiplexer  105  have a global constraint of G and an interleaved constraint of I. The global constraint of the output data is determined by G=1+2×min (Ge, Go), if Ge≠Go; and by G=2×Ge, if Ge=Go. The interleaved constraint of the output data is determined by I=max (Ge, Go). 
       FIG. 2  illustrates a specific example of a modulation encoding scheme that includes a 3/4 short block encoder. Short block encoder  201  maps the first 3 bits (x 1 , x 2 , x 3 ) of the input data to 4 bits (y 0 , y 1 , y 2 , y 3 ) selected from a lookup table. Short block encoder  201  performs a 3-to-4 mapping to enforce the constraints (y 0 , y 2 )≠(1, 1) and (y 1 , y 3 )≠(1, 1). Table 1 illustrates mappings that are performed by short block encoder  201  according to this example. 
     
       
         
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 Input bits (x 1 , x 2 , x 3 ) 
                 Output bits (y 0 , y 2 ) 
                 Output bits (y 1 , y 3 ) 
               
               
                   
               
             
             
               
                 0 0 0 
                 0 0 
                 0 0 
               
               
                 0 0 1 
                 0 0 
                 0 1 
               
               
                 0 1 0 
                 0 0 
                 1 0 
               
               
                 0 1 1 
                 0 1 
                 0 0 
               
               
                 1 0 0 
                 0 1 
                 0 1 
               
               
                 1 0 1 
                 0 1 
                 1 0 
               
               
                 1 1 0 
                 1 0 
                 0 0 
               
               
                 1 1 1 
                 1 0 
                 0 1 
               
               
                   
               
             
          
         
       
     
     Thus, short block encoder  201  receives 3-bit input vector (x 1 , x 2 , x 3 ) and generates a 4-bit output vector (y 0 , y 1 , y 2 , y 3 ) for each 199-bit data block. Demultiplexer  202  receives the 4-bit output (y 0 , y 1 , y 2 , y 3 ) of short block encoder  201  and the remaining 196-bit vector (y 4 , y 5 , . . . , y 198 , y 199 ). Demultiplexer  202  separates the even and odd interleaves to generate a stream of 100 even bits y 0 , y 2 , y 4 , . . . , y 198  and a stream of 100 odd bits y 1 , y 3 , y 5 , . . . , y 199 . 
     Fibonacci encoder  203  maps the 100-bit even interleaves to a 100-bit Fibonacci code, and Fibonacci encoder  204  maps the 100-bits odd interleaves to a 100-bit Fibonacci code. Multiplexer  205  interleaves the two Fibonacci codes to generate a combined data stream that has 200 bits. 
     Short block encoder  201  reduces the number of values that can be sent as input to Fibonacci encoders  203  and  204  by (25%). By preventing the first two even bits in the user data from being 11, only three of the four possible values for bits y 0  and y 2  are allowed (00, 01, and 10). The number of possible integer values for the 100-bit even interleaves is reduced by 25%, because one quarter of the possible 100-bit integer values that begin with 11 are not allowed. As a result, Fibonacci encoder  203  only has to map at the most 75% of the 2 100  possible values for a 100-bit even interleave. Fibonacci encoder  203  can perform 100-bit to 100-bit (N-bit to N-bit) mappings, as long as no more than 25% of the 2 100  possible values are forbidden by the global even bit constraint Ge, i.e., as long as the corresponding Fibonacci code has at least 3×2 98  code sequences. 
     The same principle holds for the odd interleaves. By preventing the first two odd bits (y 1  and y 3 ) in a data block from being 11, only three of the four possible values for bits y, and y 3  are allowed (00, 01, and 10). The number of possible integer values for a 100-bit odd interleave is reduced by 25%, because one quarter of the possible 100-bit integer values that begin with 11 are not allowed. As a result, Fibonacci encoder  204  only has to map at the most 75% of the 2 100  possible values for a 100-bit odd interleave. Fibonacci encoder  204  can perform 100-bit to 100-bit (N-bit to N-bit) mappings, as long as no more than 25% of the 2 100  possible values are forbidden by the global odd constraint Go, i.e., as long as the corresponding Fibonacci code has at least 3×2 98  code sequences. 
     The short block mapping of 3-to-4 bits allows Fibonacci encoders  203  and  204  to map reduced 100 bit input numbers to 100 bit Fibonacci output numbers (100-bit to 100-bit mappings) for the following reasons. A Fibonacci encoder can map a 199 bit block of data to a 200 bit constrained block of data on a 1-to-1 basis using the Fibonacci encoding technique for rate (N−1)/N. To reduce the size of a 199/200 Fibonacci encoder by half to reduce the storage space requirements, requires that an input number be 99.5 bits and the output number be 100 bits. 
     A theoretical 99.5 bit block would have 2 99.5  possible values, i.e. √2×2 99  or about (1.41421)×2 99 . This means that a 99.5 bit block has about X=(1.41421)×2 99  possible values. A 100 bit block has Y=2×2 99  possible values. A rate 99.5/100 modulation encoder needs to have at least X code sequences for mapping all of the possible input values to distinct output code sequences. 
     Therefore, from the possible 2 100  unconstrained 100-bit sequences only about X=(1.41421)×2 99  code sequences are required, which is about 70.7% of the total number of possible 100-bit sequences. The remaining 29.3% of the values of the 100 bit block can be forbidden by a modulation constraint G. 
     Because short block encoder  201  constrains blocks of the user data bits to having only ¾ of their possible values, Fibonacci encoders  203  and  204  only need to map at the most 75% of the 2 100  possible values of the 100 bit input numbers in the range from 0 to 3×2 98 −1. Short block encoder  201  can be replaced with another short block encoder of higher rate, thereby reducing the range of the 100-bit input numbers. In the limiting case, where the rate of the short block encoder is 199/200, the number of required code sequences can be reduced to about X, as long as X/Y is at least √2/2 (about 70.7%). 
     The modulation encoding schemes of  FIGS. 1–2  substantially reduce the complexity and storage requirements of an interleaved modulation encoder by replacing a subset of the user bits with a set of constrained bits. A short block encoder of the present invention can replace any desired number of the user bits with constrained bits. Short block encoder  201  is described merely as an example of the present invention and is not intended to limit the scope of the present invention to 3-to-4 bit mappings. One of skill in the art will understand that the present invention includes many different types of short block encoders. 
     Further embodiments of the present invention will now be described. A short block constrained coding of rate (2K−1)/2K transforms an input bit-sequence x 1 , x 2 , . . . , x 2K-1  into an output bit-sequence y 0 , y 1 , . . . , y 2K-1 , where both the even and the odd interleaves of the output sequence satisfy the same constraint, which is defined as follows. Let z 1 2 K−1 +z 2 2 K−2 + . . . +z K-1 2+z K  be the binary representation of ┌2 (2K−1)/2 ┐, i.e., of the smallest integer larger or equal to the square root of 2 (2K−1) . 
     The constraint applied by the short block encoder is given by the requirement that the even and odd interleave y 0 , y 2 , . . . , y 2k-2  and y 1 , y 3 , . . . , y 2K-1 , respectively, are smaller than the K-bit sequence z 1 , z 2 , . . . , z K  with respect to lexicographic ordering with the most significant bit being at the left most position. For instance, a rate—9/10 short block encoder ensures that in each interleave the bit stream will start with a five bit sequence, which is less than 10111. For example, the sequence 11000 is not allowed, but 10110 is a valid 5-bit string. Because both interleaves satisfy the same constraint, the resulting modulation code is balanced with respect to even and odd interleaves. 
     An embodiment of a short block encoder having rate—9/10 constrained codes is shown in  FIG. 3 . The embodiment of  FIG. 3  includes a short block encoder  301 , a demultiplexer  302 , Fibonacci encoders  303 – 304 , and a parallel-to-serial converter (or multiplexer)  305 . Short block encoder  301  imposes constraints on the first 9 bits of each data block received. Short block encoder  301  maps the first 9 bits in each data block to 10 output bits to provide a 9/10 rate code. 
     Demultiplexer  302  separates the even and odd interleaves from the remaining 190-bit vector (y 10 , y 11 , . . . , y 199 ) of the original data block and the 10-bit output vector of encoder  301 . Fibonacci encoder  303  imposes a modulation constraint on the even interleave to generate a constrained even interleave, and Fibonacci encoder  304  imposes a modulation constraint on the odd interleave to generate a constrained odd interleave, as described above. Parallel-to-serial converter  305  combines the constrained even and constrained odd bits into one serial data stream. 
     The constraints on the 10-bit output sequence y 0 , y 1 , . . . , y 9  of the rate—9/10 short block encoder  301  are given by:
 
(y 0 , y 2 )≠(1,1)
 
(y 0 , y 2 , y 4 , y 6 , y 8 )≠(1,0,1,1,1)
 
(y 1 , y 3 , y 5 , y 7 , y 9 )≠(1,0,1,1,1)
 
     These constraints ensure that the largest even/odd output sequence has a 5-bit prefix, that does not exceed 10110. In terms of Boolean equations, these constraints are characterized by:
 
 y   0   y   2 =0
 
 y   1   y   3 =0
 
 y   0   ˜y   2   y   4   y   6   Y   8 =0
 
 y   1   ˜y   3   y   5   y   7   y   9 =0
 
     The symbol ˜ stands for negation, multiplication stands for AND, and addition stands for OR. Among these three operations, negation has the highest precedence, and OR has the lowest precedence. An efficient implementation of the rate—9/10 encoder  301  is obtained using the technique of gated partitions. Four partitions m 1 –m 4  are specified by the following Boolean variables, where x 1 –x 9  represent the 9-bit inputs to encoder  301 :
 
m 1 =˜x 1  
 
 m   2   =x   1   x   2 ˜( x   4   x   6   x   8 )
 
 m   3   =x   1   ˜x   2 ˜( x   5   x   7   x   9 )
 
 m   4 =˜( m   1   +m   2   +m   3 )
 
     The input/output map of encoder  301  is specified by:
 
 y   0   =m   2   +m   4  
 
 y   1   =m   3   +m   4  
 
 y   2   =m   1   x   2   +m   3   x   3  
 
 y   3   =m   1   x   3   +m   2   x   3  
 
 y   4   =˜m   4   x   4   +m   4   x   3  
 
 y   5   =˜m   4   x   5   +m   4 ( x   2   x   5   +˜x   2   x   4 )
 
 y   6   =˜m   4   x   6   +m   4 ( x   2   x   7   +x   2   x   6   ˜x   8 )
 
 y   7   =˜m   4   x   7   +m   4 ( x   2   x   9   +˜x   2   x   6   x   8 )
 
 y   8   =˜m   4   x   8   +m   4   ˜x   2   x   8  
 
 y   9   =˜m   4   x   9   +m   4   ˜x   2   ˜x   8  
 
     The present invention also includes short block decoders that convert data block vectors that have been encoded by a short block encoder back to the original data pattern. The short block decoder that corresponds to encoder  301  converts sets of 10-bit vectors back to 9-bit vectors by reversing the short block mappings described above. An embodiment of such a short block decoder uses five auxiliary variables q 1 –q 5  and computes the inverse mapping via the Boolean expressions given below:
 
 q   1 =˜( y   0   +y   1 )
 
 q   2   =y   0   ˜y   1  
 
 q   3   =˜y   0   y   1  
 
 q   4   =y   0   y   1  
 
 q   5   =y   8   +y   9  
 
 x   1   =q   2   +q   3   +q   4  
 
 x   2   =q   1   y   2   +q   2   +q   4   ˜q   5  
 
 x   3 =( q   1   +q   2 ) y   3   +q   3   y   2   +q   4   y   4  
 
 x   4   =˜q   4   y   4   +q   4 (˜ q   5 +y 5 )
 
 x   5   =˜q   4   y   5   +q   4 ( q   5   +y   5 )
 
 x   6   =˜q   4   y   6   +q   4 (˜ q   5   +y   6   +y   7 )
 
 x   7   =˜q   4   y   7   +q   4 ( q   5   +y   6 )
 
 x   8   =˜q   4   y   7   +q   4 (˜ q   5   +y   8 )
 
 x   9   =˜q   4   y   9   +q   4 ( q   5   +y   7 )
 
     The rate—9/10 short block encoder  301  has 47 two-input gates, and the corresponding short block decoder has 42 two-input gates. This gate count gives a total complexity for the encoder/decoder pair of 89 two-input gates. 
     An embodiment of a short block encoder having rate—13/14 constrained codes is shown in  FIG. 4 . The embodiment of  FIG. 4  includes a short block encoder  401 , a demultiplexer  402 , Fibonacci encoders  403 – 404 , and parallel-to-serial converter (or multiplexer)  405 . Short block encoder  401  imposes constraints on the first  13  bits of each data block received. Short block encoder  401  maps a 13-bit vector in each data block to a 14-bit output vector to provide a 13/14-rate code. 
     Demultiplexer  402  separates the even and odd interleaves from the remaining 186-bit vector (y 13 , y 14 , . . . , y 199 ) of the original data block and the 14-bit output vector of encoder  401 . Fibonacci encoder  403  imposes a modulation constraint on the even interleave to generate a constrained even interleave. Fibonacci encoder  404  imposes a modulation constraint on the odd interleave to generate a constrained odd interleave. Parallel-to-serial converter  405  combines the constrained even and constrained odd interleaves into one serial data stream. 
     The constraints on the 14-bit output sequence y 0 , y 1 , . . . , y 3  of the rate—9/10 short block encoder  401  are given by:
 
(y 0 , y 2 )≠(1,1)
 
(y 1 , y 3 )≠(1,1)
 
(y 0 , y 2 , y 4 , y 6 , y 8 )≠(1,0,1,1,1)
 
(y 1 , y 3 , y 5 , y 7 , y 9 )≠(1,0,1,1,1)
 
(y 0 , y 2 , y 4 , y 6 , y 8 , y 10 , y 12 )≠(1,0,1,101,1)
 
(y 1 , y 3 , y 5 , y 7 , y 9 , y 11 , y 13 )≠(1,0,1,1,0,1,1)
 
     These constraints guarantee that the largest even/odd interleaved output sequence has a 7-bit prefix that does not exceed 1011010. The corresponding Boolean equations are given by:
 
 y   0   y   2 =0
 
 y   1   y   3 =0
 
 y   0   ˜y   2   y   4   y   6   y   8 =0
 
 y   1   ˜y   3   y   5   y   9 =0
 
 y   0   ˜y   2   y   4   y   6   ˜y   8   y   10   y   12 =0
 
 y   1   ˜y   3   y   5   y   7   ˜y   9   y   11   y   13 =0
 
     An example of a Boolean logic implementation of the rate—13/14 encoder  401  maps input bit sequence x 1 , x 2 , x 3 , . . . , x 13  to output sequence y 0 , y 1 , y 2 , . . . , y 13  using the auxiliary variables r 1 –r 12  as shown by the following logic functions:
 
 r   1   =x   4   x   6  
 
 r   2   =x   3   r   1  
 
 r   3   =x   8   r   1  
 
 r   4   =x   8   r   1  
 
 r   5   =x   5   x   7  
 
 r   6   =x   3   r   5  
 
 r   7   =x   9   r   5  
 
 r   8   =x   9   r   5  
 
 r   9   =x   1   ˜x   2  
 
 r   10   =x   1   ˜x   2  
 
 r   11   =x   10   x   12   r   4  
 
 r   12   =x   11   x   13   r   8.  
 
     The example Boolean logic implementation of the encoder also uses seven partitions m 1 , m 2 , m 3 , m 5 , m 6 , m 7 , m 8  where:
 
m 1 =˜x 1  
 
 m   2   =r   9   ˜r   3   ˜r   11  
 
 m   3   =r   10   ˜r   7   ˜r   12  
 
 m   4 =˜( m   1   +m   2   +m   3 )
 
 m   5   =r   9   r   3  
 
 m   6   =r   9   r   11  
 
 m   7   =r   10   r   7  
 
 m   8   =r   10   r   12  
 
     The input/output map of the Boolean logic implementation of the 13/14 short block encoder  401  is specified by:
 
 y   0   =m   2   +m   4  
 
 y   1   =m   3   +m   4  
 
 y   2   =m   1   x   2   +m   3   x   3  
 
 y   3   =m   1   x   3   +m   2   x   3  
 
 y   4   =˜m   4   x   4   +m   5   ˜r   5   x   3   +m   6   +m   7   ˜r   1   x   3   +m   8   ˜r   1   x   3  
 
 y   5   =˜m   4   x   5   +m   5   ˜r   5   x   5   +m   6   ˜r   5   x   3   +m   7   ˜r   1   x   4   +m   8  
 
 y   6   =˜m   4   x   6   +m   5   ˜r   5   ˜x   3   +m   6   +m   7   ˜r   1   ˜x   3   +m   8   ˜r   1   ˜x   3  
 
 y   7   =˜m   4   x   7   +m   5 (˜ r   5   x   7   +r   6 )+ m   6   ˜r   5   ˜x   3   +m   7 (˜ r   1   x   6   +r   2 )+m 8  
 
 y   8   =˜m   4   x   8   +m   7   +m   8   x   8  
 
 y   9   =˜m   4   x   9   +m   5   x   9   +m   6   x   9   +m   7   x   8  
 
 y   10   =˜m   4   x   10   +m   5   x   10   +m   6   ˜r   5   x   5   +m   7   x   10   +m   8   x   10  
 
 y   11   =˜m   4   x   11   +m   5   x   11   +m   6   x   11   +m   7   x   11   +m   8   ˜r   1   x   4  
 
 y   12   =˜m   4   x   12   +m   5   x   12   +m   6 (˜ r   5   x   7   +r   6 )+ m   7   x   12   +m   8   x   12  
 
 y   13   =˜m   4   x   13   +m   5   x   13   +m   6   x   13   +m   7   x   13   +m   8 (˜ r   1   x   6   +r   2 )
 
     A short block decoder that corresponds to encoder  401  converts 14-bit vectors back to 13-bit vectors by reversing the short block mappings described above. The Boolean logic implementation of the decoder for the rate—13/14 short block encoder uses the auxiliary variables s 1 –s 6  given below:
 
 s   1   =y   4   y   6  
 
 s   2   =y   8   s   1  
 
 s   3   =y   5   y   7  
 
 s   4   =y   9   s   3  
 
 s   5   =y   4   +y   6  
 
 s   6   =y   5   +y   7  
 
     The Boolean logic implementation of the decoder uses seven partitions q 1 , q 2 , q 3 , q 5 , q 6 , q 7 , q 8  where:
 
 q   1 =˜( y   0   +y   1 )
 
 q   3   =˜y   0   ˜s   4 ˜( s   3   ˜y   9   y   11   y   13 )
 
 q   4   =y   0   y   1  
 
 q   5   =q   4   ˜s   1   ˜s   3   ˜y   8  
 
 q   6   =q   4   s   1   ˜s   3  
 
 q   7   =q   4   ˜s   1   ˜s   3   y   8  
 
 q   8   =q   4   ˜s   1   s   3  
 
     The input/output map for the decoder is specified by the following mappings:
 
 x   1   =q   2   +q   3   +q   4  
 
 x   2   =q   1   y   2   +q   2 +( q   5   +q   6 )
 
 x   3 =( q   1   +q   2 ) y   3   +q   3   y   2   +q   5 ( y   4   +˜s   5   y   7 )+ q   6 ( y   5   +˜s   6   y   12 )+ q   7 ( y   4   +˜s   5   y   7 )+ q   8 ( y   4   +˜s   5   y   13 )
 
 x   4   =˜q   4   y   4   +q   5   +q   6   +q   7 ( y   5   +˜s   5 )+ q   8 ( y   11   +˜s   5 )
 
 x   5   =˜q   4   y   5   +q   5 ( y   5   +˜s   5 )+ q   6 ( y   10   +˜s   6 )+q 7   +q   8  
 
x 6   =˜q   4   y   6   +q   5   +q   6   +q   7 ( s   5   y   7   +˜s   5 )+ q   8 ( s   5   y   13   +˜s   5 )
 
 x   7   =˜q   4   y   7   +q   5 ( s   5   y   7   +˜s   5 )+ q   6 ( s   6   y   12   +˜s   6 )+ q   7   +q   8  
 
 x   8   =˜q   4   y   8   +q   5   +q   7   y   9   +q   8   y   8  
 
 x   9   =˜q   4   y   9   +q   5   y   9   +q   6   y   9   +q   7  
 
 x   10   =˜q   4   y   10   +q   5   y   10   +q   6   +q   7   y   10   +q   8   y   10  
 
 x   11   =˜q   4   y   11   +q   5   y   11   +q   6   y   11   +q   7   y   11   +q   8  
 
 x   12   =˜q   4   y   12   +q   5   y   12   +q   6   +q   7   y   12   +q   8   y   12  
 
 x   13   =˜q   4   y   13   +q   5   y   13   +q   6   y   13   +q   7   y   13   +q   8  
 
     The rate—13/14 encoder  401  has 93 two-input gates, and the corresponding decoder has 102 two-input gates. This gate count gives a total complexity for the encoder/decoder pair of 195 two-input gates. 
     While the present invention has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes, and substitutions are intended in the present invention. In some instances, features of the invention can be employed without a corresponding use of other features, without departing from the scope of the invention as set forth. Therefore, many modifications may be made to adapt a particular configuration or method disclosed, without departing from the essential scope and spirit of the present invention. It is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments and equivalents falling within the scope of the claims.