Abstract:
A method for forming a semiconductor device includes providing a substrate region having a first material and a second material overlying the first material, wherein the first material has a different lattice constant from a lattice constant of the second material. The method further includes etching a first opening on a first side of a gate and etching a second opening on a second side of the gate. The method further includes creating a first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the first in-situ doped epitaxial region is created using the second material. The method further includes creating a second in-situ n-type doped expitaxial region overlying the first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the second in-situ n-type doped epitaxial region is created using the second material.

Description:
FIELD OF THE INVENTION  
       [0001]     This invention relates to semiconductor devices and more particularly to semiconductor devices with stressors.  
       BACKGROUND OF THE INVENTION  
       [0002]     P and N channel transistors have been found to have improved performance by use of strained semiconductor material in the channel. N channel transistors benefit from more tensile stress, whereas P channel transistors benefit from compressive stress. A number of techniques have been proposed to achieve one or both of these stresses. One of the difficulties is enhancing the stress for both the N and P channel transistors. Another issue is achieving an enhancing stress while not introducing detrimental defects. Another issue is providing the optimum direction for the stress. For example, P channel transistors benefit more from an increase in compressive in the channel length direction than from an increase in compressive stress in both the channel length and channel width direction. Another issue is proper material choices for the P and N channel devices. N channel devices are generally better if they have a silicon channel rather than a germanium or silicon germanium (SiGe) channel because SiGe has lower electron mobility than silicon.  
         [0003]     Thus, there is an need for a device that has the desired benefits that can be made in a process that improves on one or more of these issues. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0004]     The foregoing and further and more specific objects and advantages of the invention will become readily apparent to those skilled in the art from the following detailed description of a preferred embodiment thereof taken in conjunction with the following drawings:  
         [0005]      FIG. 1  is a cross section of a semiconductor device at a stage in a process that is according to an embodiment of the invention;  
         [0006]      FIG. 2  is a cross section of the semiconductor device at a stage in the process subsequent to that shown in  FIG. 1 ;  
         [0007]      FIG. 3  is a cross section of the semiconductor device at a stage in the process subsequent to that shown in  FIG. 2 ;  
         [0008]      FIG. 4  is a cross section of the semiconductor device at a stage in the process subsequent to that shown in  FIG. 3 ;  
         [0009]      FIG. 5  is a cross section of the semiconductor device at a stage in the process subsequent to that shown in  FIG. 4 ;  
         [0010]      FIG. 6  is a cross section of the semiconductor device at a stage in the process subsequent to that shown in  FIG. 5 ; and  
         [0011]      FIG. 7  is a cross section of the semiconductor device at a stage in the process subsequent to that shown in  FIG. 6 .  
         [0012]      FIG. 8  is a cross section of the semiconductor device at a stage in the process subsequent to that shown in  FIG. 7 .  
         [0013]      FIG. 9  is a cross section of the semiconductor device at a stage in the process subsequent to that shown in  FIG. 8 .  
         [0014]      FIG. 10  is a cross section of the semiconductor device at a stage in the process subsequent to that shown in  FIG. 9 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0015]     In one aspect a device structure has an N channel transistor with a silicon channel and stressors as the source/drains that result in tensile stress in the channel and a P channel transistor with a silicon channel and stressors as the source/drains that result in compressive stress in the channel. The stressors, silicon for the N channel transistor and SiGe with increased germanium concentration for the P channel transistor, are epitaxially grown from a SiGe layer. This is better understood by reference to the drawings and the following description.  
         [0016]     Shown in  FIG. 1  is a semiconductor device structure  10  having a SiGe layer  12  and a silicon layer  14  on SiGe layer  12 . SiGe layer  12  is relaxed and has a concentration of about 20% germanium. Silicon layer  14  is also relaxed and is preferably pure silicon. Under SiGe layer  12  is further structural support and in this case would preferably be an oxide layer and a relatively thick silicon layer. An alternative to this is to have a virtual silicon germanium substrate in which SiGe layer  12  is grown from an underlying silicon layer with a gradient in a manner that results in SiGe layer  12  having relaxed strain. The structure shown in  FIG. 1  is believed to be unique in combining relaxed silicon and relaxed SiGe as two layers bonded together, but it can be made using known techniques. A wafer having a relaxed SiGe layer on its top face and another wafer having a relaxed silicon layer on its top face can be bonded together face to face so that the SiGe and silicon layers are bonded together. A subsequent cleaving of the silicon layer will result in device structure  10  of  FIG. 1 . A hydrogen implant along the line of cleaving is one way to assist in providing the cleaving to leave the desired thickness of the silicon layer. Another technique that could be used to provide a similar structure is to that of  FIG. 1  is to provide an underlying relaxed SiGe layer, epitaxially growing a graded layer that ends in pure silicon, and then continuing to grow a pure silicon layer that would be relaxed. Epitaxially growing a relaxed a silicon layer on a SiGe layer is known to be achievable by reducing the concentration of germanium during the growth. The substrate material shown in  FIG. 1  is based on a semiconductor wafer having a first semiconductor layer, SiGe layer  12 , substantially consisting of silicon and germanium, wherein the first semiconductor layer has relaxed strain, and a second semiconductor layer on the first semiconductor layer substantially consisting of silicon, silicon layer  14 , wherein the second semiconductor layer has relaxed strain.  
         [0017]     Shown in  FIG. 2  is semiconductor device structure  10  after forming an isolation region  16  in silicon layer  14  and SiGe layer  12 . Processes for forming isolation regions such as isolation region  16  are well known. Any such process should be satisfactory.  
         [0018]     Shown in  FIG. 3  is semiconductor device structure  10  after forming an N channel transistor  18  on one side of isolation region  16  and a P channel transistor  20  on the other side of isolation region  16 . Prior to transistors  18  and  20  being formed, the side with transistor  18  is implanted with p-type dopants, preferably boron, to provide background doping, and the side with transistor  20  is implanted with n-type dopants, preferably phosphorus and/or arsenic, to provide background doping. Transistor  18  comprises a gate  22  over silicon layer  14 , a gate dielectric  24  on silicon layer  14  and under gate  22 , a source/drain extension  26  in silicon layer  14  on one side of gate  22 , a source/drain extension  28  in silicon layer  14  on the other side of gate  22 , and a sidewall spacer  30  around gate  22 . Transistor  20  comprises a gate  32  over silicon layer  14 , a gate dielectric  34  on silicon layer  14  and under gate  22 , a source/drain extension  26  in silicon layer  14  on one side of gate  22  and a source/drain  30  extension  28  in silicon layer  14  on the other side of gate  22 . Source/drain extensions  26 ,  28 ,  36 , and  38  are preferably relatively shallow, about 500 Angstroms, but could be another depth. The doping concentrations for the background and the source/drain extensions are typical for those purposes.  
         [0019]     Shown in  FIG. 4  is semiconductor device structure  10  after masking the side with transistor  20  with a hard mask  42  of oxide and etching openings  44  and  46  through silicon layer  14  and into SiGe layer  12  about 500 Angstroms. This etch uses gate  22  and sidewall spacer  30  as a mask so that openings  44  and  46  are on opposite sides of gate  22 . The etch exposes SiGe layer  12  in openings  44  and  46 . This leaves source/drain extensions  26  and  28  under sidewall spacer  30  and silicon layer  14  under gate  22  and sidewall spacer  30 .  
         [0020]     Shown in  FIG. 5  is semiconductor device structure  10  after growing silicon layers of  48  and  50  epitaxially and in situ doped with p-type dopants, preferably boron, in openings  44  and  46 , respectively. P-doped silicon layers  48  and  50  grow on the exposed surface of SiGe layer  12  and exposed sides of silicon layer  14 . P-doped silicon layers follow the lattice from which they grow so that along silicon layer  14  it is relatively relaxed but along SiGe layer  12  it is tensile.  
         [0021]     Shown in  FIG. 6  is semiconductor device structure  10  after growing silicon layers of  52  and  54  epitaxially and in situ doped with n-type dopants, preferably arsenic and/or phosphorus, in openings  44  and  46 , respectively. In this case the dopant concentration increases as the growth continues so that it is much more lightly doped at the interface with p-doped silicon layers  48  and  50  than at the top surface. The lattice structure of silicon layers  48 ,  50 ,  52 , and  54  is tensile at a level that is between what it would be if it had the SiGe lattice structure of SiGe layer  12  and the relaxed condition of semiconductor layer  14 . Silicon layers  48  and  52  function as one stressor for transistor  18 , and layers  50  and  54  function as another stressor.  
         [0022]     Shown in  FIG. 7  is semiconductor device structure  10  after masking the side with transistor  18  with a hard mask  56  of oxide and etching openings  58  and  60  through silicon layer  14  and into SiGe layer  12  about 500 Angstroms. This etch uses gate  32  and sidewall spacer  40  as a mask so that openings  58  and  60  are on opposite sides of gate  32 . The etch exposes SiGe layer  12  in openings  58  and  60 . This leaves source/drain extensions  36  and  38  under sidewall spacer  40  and silicon layer  14  under gate  32  and sidewall spacer  40 .  
         [0023]     Shown in  FIG. 8  is semiconductor device structure  10  after growing SiGe layers of  62  and  64  epitaxially and in situ doped with n-type dopants, preferably arsenic and/or phosphorus, in openings  58  and  60 , respectively. Further, the germanium concentration of SiGe layers  62  and  64  is increased relative to the germanium concentration of SiGe layer  12 . N-doped SiGe layers  62  and  64  grow on the exposed surface of SiGe layer  12  and exposed sides of silicon layer  14  and follow the lattice from which they grow. Thus, the portions along SiGe layer  12  are tensile laterally in the direction of current flow of transistor  20  (channel length direction), which is the primary direction of interest. The SiGe growth on the sides of semiconductor layer  14  is also compressive but minimally so in the channel length direction.  
         [0024]     Shown in  FIG. 9  is semiconductor device structure  10  after growing SiGe layers of  52  and  54  epitaxially and in situ doped with p-type dopants, preferably boron, in openings  58  and  60 , respectively. In this case the dopant concentration increases as the growth continues so that it is much more lightly doped at the interface with n-doped SiGe layers  62  and  64  than at the top surface. In this example, SiGe  12  layer preferably has a germanium concentration of about 20 percent and the concentration of the grown SiGe layers  62 ,  64 ,  66 , and  68  are about 40 percent germanium. The lattice structure of SiGe layers  62 ,  64 ,  66 , and  68  is compressive. SiGe layers  62  and  66  function as one stressor for transistor  20 , and layers  64  and  68  function as another stressor.  
         [0025]     Shown in  FIG. 10  is semiconductor device structure  10  after performing an anneal that causes the dopants to move somewhat resulting in a P doped region  70  substantially in areas where silicon layer  14  and silicon layers  48  and  50  were present. The anneal also results in an N-doped regions  72  and  74  substantially where silicon regions  52  and  54  and source/drain extensions  26  and  28  were. The doping concentration is higher away from the channel than adjacent to the channel, the region between N-doped regions  72  and  74  immediately under gate dielectric  24 . The anneal further results in an N doped region  76  substantially in areas where silicon layer  14  and silicon layers  62  and  64  were present. In addition the anneal results in an P-doped regions  78  and  80  substantially where SiGe layers  62  and  64  and source/drain extensions  36  and  38  were. The doping concentration is higher away from the channel than adjacent to the channel, the region between P-doped regions  78  and  80  immediately under gate dielectric  34 .  
         [0026]     P channel region  70  ensures the presence of a PN junction between the source/drain regions, N doped regions  72  and  74 , and the interface between silicon layer  14  and SiGe layer  12 . This interface, both on the side having transistor  18  and the side having transistor  20 , has many defects including at the corners of the interface. It is beneficial that these defects, including the ones in the corners, not interfere with source/drain operation which is achieved by virtue of the growth of N-doped layers  62  and  64  and P-doped layers  48  and  50 . In addition to resulting in the beneficial compressive stress on the channel of the P channel transistor and the beneficial tensile stress on the channel of the N channel transistor, this approach also results in a silicon channel for the N channel transistor, which is the preferred material for N channel transistors.  
         [0027]     Various other changes and modifications to the embodiments herein chosen for purposes of illustration will readily occur to those skilled in the art. For example, the isolation regions were described as using an existing process, but the isolation regions could be made using a process that is subsequently developed. In come cases particular thicknesses were described but other thicknesses may be beneficial. To the extent that such modifications and variations do not depart from the spirit of the invention, they are intended to be included within the scope thereof which is assessed only by a fair interpretation of the following claims.