Abstract:
A method of filtering a differential signal. The method includes receiving the differential signal. Transitions of the differential signal are accelerated after the differential signal has passed through a cross-over point to create an accelerated differential signal. A delayed differential signal is created that is a delayed version of the accelerated differential signal delayed by a predetermined amount of time with respect to the accelerated differential signal. The accelerated differential signal is amplified to create an amplified accelerated differential signal. The delayed differential signal is amplified to create an amplified delayed differential signal. The amplified delayed differential signal and the amplified accelerated differential signal are combined to create an output signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims priority to U.S. Provisional Application No. 60/550,548, filed Mar. 5, 2004, titled An Amplification Circuit For Driving A Laser Signal which is hereby incorporated by reference in its entirety. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. The Field of the Invention  
         [0003]     The present invention relates to the field of high-speed data communications. In particular, the present invention relates to a circuit and method for amplifying a laser signal.  
         [0004]     2. Description of the Related Art  
         [0005]     In high speed optical communication systems, laser signals may be used to transmit information. For example, a laser signal, transmitted by a remote device, may be detected by a photo detector, amplified by a trans-impedance amplifier circuit, and filtered by a filter circuit. After the laser signal is filtered, it is then amplified by an amplification circuit and converted to a digital format for further processing or storage.  
         [0006]     Traditionally, the amplification circuit may be implemented with differential amplifiers consisting of pairs of transistors. One of the design goals of the amplification circuit is to decrease the settling time of the laser signal during a signal transition. This design goal may be accomplished by using a differential amplifier having a higher amplification gain to drive the laser signal in order to ensure a fast signal transition. Another design goal of the amplification circuit is to minimize the electromagnetic interference created by the higher order harmonics of the laser signal during signal transitions. This design goal may be accomplished by using a differential amplifier having a lower amplification gain to drive the laser signal. As a result, a design tradeoff has to be made to choose between having a higher or lower amplification gain. The design is comprised because it has either the adverse effect of electromagnetic interference or lower design margins for signal settling time during signal transitions. The adverse effect of electromagnetic interference may lead to additional system costs employed to reduce the interference problem. The adverse effect of lower design margins for signal settling time may lead to lower signal quality and may also lead to transmission errors.  
         [0007]     Therefore, there is a need for a laser amplification circuit which can increase the settling time margin during signal transitions and at the same time minimize the electromagnetic interference generated from such signal transitions.  
       BRIEF SUMMARY OF THE INVENTION  
       [0008]     One embodiment includes an amplification circuit for amplifying a differential pair of input signals. The amplification circuit includes a receiver circuit, a first differential amplifier circuit, a second differential amplifier circuit, a pair of output terminals, and a transition accelerating circuit. The receiver circuit receives the differential pair of input signals. The first differential amplifier circuit is coupled to a pair of output ports of the receiver circuit and generates first and second amplified signals. The second differential amplifier circuit is coupled to the pair of output ports of the receiver circuit through a transition smoothing circuit and generates third and fourth amplified signals. The pair of output terminals includes a first output terminal and a second output terminal. The first output terminal is configured to combine second amplified signal and the fourth amplified signal. The transition accelerating circuit is coupled to the pair of output ports of the receiver circuit, and speeds up the rate of signal change at the pair of output terminals during the predetermined period of signal transition.  
         [0009]     Another embodiment includes a method of filtering a differential signal. The method includes receiving the differential signal. Transitions of the differential signal are accelerated after the differential signal has passed through a cross-over point to create an accelerated differential signal. A delayed differential signal is created that is a delayed version of the accelerated differential signal delayed by a predetermined amount of time with respect to the accelerated differential signal. The accelerated differential signal is amplified to create an amplified accelerated differential signal. The delayed differential signal is amplified to create an amplified delayed differential signal. The amplified delayed differential signal and the amplified accelerated differential signal are combined to create an output signal.  
         [0010]     These and other features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.  
     
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS  
       [0011]     In order that the manner in which the above-recited and other advantages and features of the invention are obtained, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments of the invention and are not therefore to be considered limiting of its scope, the invention will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:  
         [0012]      FIG. 1  illustrates a sub-system for processing a received optical laser signal.  
         [0013]      FIG. 2  illustrates an implementation of the amplification circuit  108  of  FIG. 1 .  
         [0014]      FIG. 3A  illustrates a block diagram of the multiplexing amplifier circuit of  FIG. 2 .  
         [0015]      FIG. 3B  illustrates an implementation of one of the differential amplifiers of the multiplexing amplifier circuit.  
         [0016]      FIG. 4  illustrates an implementation of the polarity switching amplifier circuit  FIG. 2 .  
         [0017]      FIG. 5A  illustrates a block diagram of the accelerating amplifier circuit of  FIG. 2 .  
         [0018]      FIG. 5B  illustrates an implementation of the accelerating amplifier circuit of  FIG. 5A .  
         [0019]      FIG. 6A  illustrates output waveforms of the first and second differential amplifiers of  FIG. 5A .  
         [0020]      FIG. 6B  compares combined output waveforms of the first and second differential amplifiers of  FIG. 6A  with and without the transition smoothing circuit.  
         [0021]      FIG. 7A  illustrates an output signal transition of the accelerating amplifier circuit without the transition accelerating circuit  512 .  
         [0022]      FIG. 7B  compares output signals of the accelerating amplifier circuit with and without the transition accelerating circuit. 
     
    
       [0023]     Like reference numbers are used to identify like components throughout the Figures.  
       DETAILED DESCRIPTION OF THE INVENTION  
       [0024]      FIG. 1  illustrates a sub-system for processing a received optical laser signal. Information carried in the received optical laser signal is first detected by a photo detector  102  and converted into an electronic signal format as a pair of differential signals. The differential signals are then processed and transmitted by a trans-impedance amplifier  104  to a filter circuit  106 . The purpose of the filter circuit  106  is to filter out noise as well as to filter out higher order harmonics in the input laser signal. The noise and higher order harmonics may degrade the laser signal quality and generate undesirable electromagnetic interference in the system. The filter circuit  106  may be designed to filter or not filter the input signal from the trans-impedance amplifier  104 , hence it may send a filtered laser signal and a unfiltered laser signal to an amplification circuit  108  in the next stage. The output of the filter circuit  106  is sometimes herein called the input laser signal, as distinguished from the optical laser signal received by the photo detector  102 . The amplifcation circuit  108  may select either the filtered or unfiltered input laser signal, switch the polarity of the input laser signal, and amplify the input laser signal to a desired signal level for further processing or storage.  
         [0025]      FIG. 2  illustrates an implementation of the amplification circuit  108  of  FIG. 1 . The inputs to the amplification circuit  108  receive a filtered input laser signal  202  and a unfiltered input laser signal  203 . The amplification circuit includes a multiplexing amplifier circuit  204 , a polarity switching amplifier circuit  206 , an accelerating amplifier circuit  208 , and an output laser signal  210 . The multiplexing amplifier circuit  204  receives the filtered and unfiltered input laser signals  202 ,  203 . It then selects either the filtered  202  or unfiltered  203  input laser signals in accordance with a predetermined set of multiplexor control signals. The polarity switching amplifier circuit  206  receives the output of the multiplexing amplifier circuit  204 . It generates either an inverting or a non-inverting version of the received signal in accordance with a predetermined set of polarity control signals. The accelerating amplifier circuit  208  receives the output of the polarity switching amplifier circuit  206 . It amplifies the received input signal and generates the output laser signal  210 .  
         [0026]      FIG. 3A  illustrates a block diagram of the multiplexing amplifier circuit  204  of  FIG. 2 . The circuit includes a first differential amplifier  302  which receives a differential pair of filtered input laser signals  202 , and a second differential amplifier  304  which receives a differential pair of unfiltered input laser signals  203 . Both the first and second differential amplifiers  302 ,  304  are controlled by a multiplexor control source  306  which generates a set of multiplexor control signals  307 . The multiplexor control signals  307  either turn on the first differential amplifier  302  and turn off the second differential amplifier  304 , or alternatively turn off the first differential amplifier  302  and turn on the second differential amplifiers  304 . The outputs of the first and second differential amplifiers  302 ,  304  are combined at a first output port  308  (Output n) and a second output port  310  (Output P) to form a multiplexing amplifier circuit output  311 . Since only one of the differential amplifiers  302  or  304  is turned on at a time, either the filtered input laser signal  202  or the unfiltered input laser signal  203  is selected, amplified and transmitted to the output ports  308 ,  310  of the multiplexing amplifier circuit  204 .  
         [0027]      FIG. 3B  illustrates an implementation of one of the differential amplifiers  302 ,  304  of  FIG. 3A . The differential amplifier includes a first transistor  312  having a base terminal coupled to a first input port (Input p), which may be, for example, filtered input p of the filtered input laser signal  202 , a collector terminal coupled to the first output port  308  (Output n) and an emitter terminal coupled to a current source  314 . The differential amplifier further includes a second transistor  316  having a base terminal coupled to a second input port (Input n), which may be, for example, filtered input n of the filtered input laser signal  202 , a collector terminal coupled to the second output port  310  (Output p) and an emitter terminal coupled to the current source  314 . Both the first and second differential amplifiers  302 ,  304  have similar circuit structures, except the multiplexing control signals  307  which drive the switchable bias voltage signals for the differential amplifiers are non-overlapping signals. For example, when the switchable bias voltage signal for the first differential amplifier  302  is asserted, the corresponding switchable bias voltage signal for the second differential amplifier  304  is deasserted. These non-overlapping switchable bias voltage signals ensure the first and second differential amplifiers  302 ,  304  do not turn on at the same time. As a result, only one of the input signals  202 ,  203  is selected and transmitted to the output ports  308  and  310  of the multiplexing amplifier circuit  204 .  
         [0028]      FIG. 4  illustrates an implementation of the polarity switching amplifier circuit  206  of  FIG. 2 . The polarity switching amplifier circuit  206  includes a buffer circuit  401  that receives the multiplexing amplifier circuit output signals  311  from the output ports  308 ,  310  of the multiplexing amplifier circuit  204  ( FIG. 3A ). The buffer circuit  401  includes a first transistor Q 44 , a first bias current source  404 , a second transistor Q 46  and a second bias current source  408 . The first transistor Q 44  has a base terminal coupled to a first input  403  (Input p) of the buffer circuit  401 , a collector terminal coupled to a power supply Vdd, and an emitter terminal coupled to the first bias current source  404 . The second transistor Q 46  has a base terminal coupled to a second input  405  (Input n) of the buffer circuit  401 , a collector terminal coupled to the power supply Vdd, and an emitter terminal coupled to the second bias current source  408 .  
         [0029]     The polarity switching amplifier circuit  206  also includes a first differential amplifier circuit  410  formed with transistors Q 40  and Q 41 , a third switchable bias current source  414 , and a pair of output terminals  418  and  420 . The first differential amplifier  410  receives its input signals from the buffer circuit  401  at nodes  407  and  409  and generates a first amplified signal Output n at output terminal  418  and a second amplified Output p signal at output terminal  420  in response to the input signals received. The transistor Q 40  has a base terminal coupled to a first output port (node  407 ) of the buffer circuit  401 , a collector terminal coupled to the first output terminal  418  (Output n), and an emitter terminal coupled to the third switchable bias current source  414 . The transistor Q 41  has a base terminal coupled to the second output port (node  409 ) of the buffer circuit  401 , a collector terminal coupled to the second output terminal  420  (Output p), and an emitter terminal coupled to the emitter terminal of the transistor Q 40  and to the third switchable bias current source  414  that is enabled by a bias signal Va.  
         [0030]     The polarity switching amplifier circuit  206  further includes a second differential amplifier circuit  412  formed with transistors Q 42  and Q 43 , and a fourth switchable bias current source  416  that is enabled by a bias signal Vb. The second differential amplifier circuit  412  receives its input signals from the buffer circuit  401  at nodes  407  and  409  and generates a third amplified signal and a fourth amplified signal in response to the input signals received. The transistor Q 42  has a base terminal coupled to the first output port (node  407 ) of the buffer circuit  401 , a collector terminal coupled to the second output terminal  420  (Output p), and an emitter terminal coupled to the fourth switchable bias current source  416 . The transistor Q 43  has a base terminal coupled to a second output port (node  409 ) of the buffer circuit  401 , a collector terminal coupled to the first output terminal  418  (Output n), and an emitter terminal coupled to the emitter terminal of the transistor Q 42  and to the fourth switchable bias current source  416 . Similar to the multiplexing control signals  307  of the multiplexing amplifier circuit  204  ( FIG. 3A ), the polarity switching control signals which drive the switchable bias voltage signals Va and Vb are non-overlapping signals. These non-overlapping signals ensure the first and second differential amplifiers  410  and  412  do not turn on at the same time and therefore either an inverting or a non-inverting output signal is selected and transmitted to the output terminals  418  and  420  of the polarity switching amplifier circuit.  
         [0031]     The pair of output terminals  418 ,  420  includes the first output terminal  418  and the second output terminal  420 . The first output terminal  418  is configured to combine the first and fourth amplified signals, and the second output terminal  420  is configured to combine the second and third amplified signals. Note that the output of the first differential amplifier  410  is non-inverting, and the output of the second differential amplifier  412  is inverting. By selectively enabling either the first or the second differential amplifier  410 ,  412 , the polarity switching amplifier circuit  206  generates either an inverting or a non-inverting output signal.  
         [0032]      FIG. 5A  illustrates a block diagram of the accelerating amplifier circuit  208  of  FIG. 2 . The accelerating amplifier circuit  208  includes a pair of input terminals  502  and  503 , a receiver circuit  504 , a first differential amplifier circuit  506 , a second differential amplifier circuit  508 , a transition smoothing circuit  510 , a transition accelerating circuit  512  and a pair of output terminals  513  and  514 . The receiver circuit  504  receives a pair of input signals from the input terminals  502  and  503 . The first differential amplifier circuit  506  is coupled to the receiver circuit  504  and generates a first amplified signal and a second amplified signal. The second differential amplifier circuit  508  is coupled to the receiver circuit  504  through the transition smoothing circuit  510 , and it generates a third amplified signal and a fourth amplified signal. The pair of output terminals  513 ,  514  drive a first output signal output p and a second output signal output n. The output terminal  513  is configured to combine the first amplified signal and the third amplified signal, and the second output terminal  514  is configured to combine the second amplified signal and the fourth amplified signal. The transition accelerating circuit  512  is coupled to the input ports of the first differential amplifier  506  and to the input ports of the transition smoothing circuit  510 . The transition accelerating circuit  512  is configured to speed up signal transitions of the pair of differential output signals from the receiver circuit  504 .  
         [0033]      FIG. 5B  illustrates an implementation of the accelerating amplifier circuit  512  of  FIG. 5A . The receiver circuit  504  includes a negative signals path and a positive signal path. The negative signal path is formed with transistors Q 52 , Q 53 , Q 54 , a first bias current source formed with transistor Q 55  and resistor R 510 , and a second bias current source formed with transistor Q 56  and resistor R 511 . The transistor Q 52  has a base terminal couple to a first input terminal  502  of the receiver circuit  504 , a collector terminal coupled to a power supply Vdd, and an emitter terminal coupled to the first bias current source formed with transistor Q 55  and resistor  510 . The transistor Q 53  has a base terminal coupled to the emitter terminal of the transistor Q 52 , a collector terminal coupled to the collector of the transistor Q 52 , and an emitter terminal coupled to the second bias current source formed wth transistor Q 56  and R 511 . The transistor Q 54  has a collector terminal coupled to a first output port (b 1 ) of the receiver circuit  504 , a base terminal coupled to the collector terminal of transistor Q 54 , and an emitter terminal coupled to the emitter terminal of the transistor Q 53 .  
         [0034]     Similarly, the positive signal path is formed with transistor Q 512 , Q 513 , and Q 514 , a third bias current source formed with transistor Q 515  and resistor R 516 , and a fourth bias current source formed with transistor Q 516  and resistor R 515 . The transistor Q 512  has a base terminal coupled to a second input terminal (Ip) of the receiver circuit, a collector terminal coupled to the power supply, and an emitter terminal coupled to the third bias current source. The transistor Q 513  has a base terminal coupled to the emitter terminal of the transistor Q 512 , a collector terminal coupled to the collector of the transistor Q 512 , and a base terminal coupled to the fourth bias current source. The transistor Q 514  has a collector terminal coupled to a second output port (b 2 ) of the receiver circuit, a base terminal coupled to the collector terminal of transistor Q 514 , and an emitter terminal coupled to the emitter terminal of the transistor Q 513  and to the fourth bias current source including transistor Q 516  and resistor R 515 .  
         [0035]     Amplifier circuit  512  accelerates signal transitions at nodes b 1  and b 2 , but only after the signals at these nodes have passed through a transistion or cross-over point. As a result, the switching of the signals on nodes b 1  and b 2  starts out “slow” (thereby creating very little electromagnetic noise), and then speeds up to complete the transition before a next bit time. As a result, the processing of the differential input signal (Ip and In) is completed at high speed, within a low timeframe, but without generating large amounts of electromagnetic noise.  
         [0036]     The first differential amplifier  506  of  FIGS. 5A and 5B  includes transistors Q 50  and Q 51 , a resistor network R 54 , a first bias current source formed with transistor Q 57  and resistor R 512 , and a second bias current source formed with transistor Q 58  and resistor R 512 . The transistor Q 50  has a base terminal coupled to a first output port of the receiver circuit  504  and to a first output port (b 1 ) of the transition accelerating circuit  512 , a collector terminal coupled to a power supply Vdd through a resistor network R 50  and to a first output port  513  of the accelerating amplifier circuit, and an emitter terminal coupled to the first bias current source including transistor Q 57  and resistor R 512 . The transistor Q 51  has a base terminal coupled to a second output port of the receiver circuit and to a second output port (b 2 ) of the transition accelerating circuit  512 , a collector terminal coupled to the power supply Vdd through a resistor network R 51  and to a second output port  514  of the accelerating amplifier circuit, and an emitter terminal coupled to the emitter terminal of the transistor Q 50  through the resistor network R 54  and to the second bias current source including transistor Q 58  and resistor R 512 . The resistor networks R 50 , R 51 , and R 54  include one or more resistors connected in series or in parallel.  
         [0037]     The transition smoothing circuit  510  of  FIGS. 5A and 5B  includes a resistor network R 52  and a resistor network R 53 . Both resistor networks R 52  and R 53  include one or more resistors connected in series or in parallel. The resistor network R 52  is coupled between the first output port of the receiver circuit  504 , which is also the first output port (b 1 ) of the transition accelerating circuit  512  and the first input port  516  of the second differential amplifier circuit  508 . The resistor network R 52  produces a predetermined time shift at the first input port  516  of the second differential amplifier circuit  508 . Similarly, the resistor network R 53  is coupled between the second output port and the receiver circuit  504 , which is also the second output port (b 2 ) of the transition accelerating circuit  512 , and the second input port  520  of the second differential amplifier circuit  508 . The resistor network R 3  produces a predetermined time shift at the second input port  520  of the second differential amplifier circuit  508 .  
         [0038]     The second differential amplifier  508  of  FIGS. 5A and 5B  includes transistors Q 510  and Q 511 , a resistor network R 55 , a third bias current source formed with transistor Q 517  and resistor R 514 , and a fourth bias current source formed with transistor Q 518  and resistor R 514 . The transistor Q 510  has a base terminal coupled to a first output port of the transition smoothing circuit  510 , a collector terminal coupled to the power supply dd through the resistor network R 50  and to the first output port  513  of the transition accelerating amplifier circuit  512  and an emitter terminal coupled to the third bias current source including transistor Q 517  and resistor R 514 . The transistor Q 511  has a base terminal coupled to a second output port of the transition smoothing circuit  510 , a collector terminal coupled to the power supply through Vdd the resistor network R 51  and to the second output port  514  of the second differential amplifier  508 , and an emitter terminal coupled to the emitter terminal of the transistor Q 510  through the resistor network R 55  and to the fourth bias current source (Q 518 , R 514 ). The resistor network R 55  includes one or more resistors connected in series or in parallel.  
         [0039]     The transition accelerating circuit  512  of  FIGS. 5A and 5B  includes transistors Q 520  and Q 521 , a resistor network R 57 , a resistor network R 58 , a resistor network R 59 , a first bias current souice formed with transistor Q 522  and resistor R 513 , and a second bias current source formed with transistor Q 522  and resistor R 513 . The transistor Q 520  has a collector terminal coupled to a second output port (b 2 ) of the transition accelerating circuit  512 , a base terminal coupled to a first output port (b 1 ) of the transition accelerating circuit  512  through the resistor network R 57 , and an emitter terminal coupled to the first bias current source (Q 522 , R 513 ). The transistor Q 521  has a collector terminal coupled to the first output port (b 1 ) of the transition accelerating circuit  512  a base terminal coupled to the second output port (b 2 ) of the transition accelerating circuit  512  through the resistor network R 58 , and an emitter terminal coupled to the second bias current source (Q 23 , R 13 ) and to the emitter terminal of the transistor Q 520  through the resistor network R 59 . The resistor networks R 57 , R 58 , and R 59  each include one or more resistors connected in series or in parallel.  
         [0040]     The transition acceleration circuit  512  speeds up signal transitions at the output ports  513 ,  514  of the accelerating amplifier  208 . In one embodiment, when the input signal at the base terminal of transistor Q 50  switches from low to high and the input signal at the base terminal of transistor Q 51  switches from high to low, the transistor Q 50  is caused to turn on and the transistor Q 51  is caused to turn off. As a result, the output signal at the first output port  513  (Op) of the accelerating amplifier circuit transitions form high to low as this node is pulled low through the first bias current source (Q 57 , Q 512 ). The second output port  514  (On) of the accelerating amplifier circuit transitions from low to high as this node is pulled high through the resistor network R 51 . For the transition accelerating circuit  512 , when the input signal at the base terminal of transistor Q 520  switches from high to low, the transistors Q 20  and Q 521  behave in a similar fashion as the transistors Q 50  and Q 51 , respectively, expect that the output signals of the transition accelerating circuit  512  are delayed by the resistor networks R 57  and R 58 . When transistor Q 520  turns on, current is drawn from the base terminal of the transistor Q 51 , which enhances the switching of the input signal at the base terminal of transistor Q 51  from high to low, which in turn turns off the transistor Q 51  faster and therefore pulls up the second output port  514  (On) faster. Similarly, when Q 521  turns off, less current is drawn from the base terminal of transistor Q 50 , which enhances the switching of the input signal at the base terminal of transistor Q 50  from low to high faster, which in turn turns on the transistor Q 50  faster and therefore pulls down the first output port  513  faster. Note that the transition accelerating circuit  512  functions in a similar manner when the input signals at the base terminal of transistor Q 50  switches from high to low and the input signal at the base terminal of transistor Q 51  switches from low to high. Also note that the transition accelerating circuit  512  has a similar effect on the second differential amplifier  508  as on the first differential amplifier circuit  506 , except that such effects are delayed by the transition smoothing circuit  510 .  
         [0041]      FIG. 6A  illustrates output waveforms of the first and second differential amplifiers of  FIGS. 5A and 5B . Curve  602  represents an output of the first differential amplifier circuit  506 . Curve  604 , which is a dotted line, represents a corresponding output of the second differential amplifier circuit  508  if the accelerating amplifier circuit  208  does not include the transition smoothing circuit  510 . Curve  606  represents a corresponding output of the second differential amplifier circuit  508  if the accelerating amplifier circuit includes the transition smoothing circuit  510 . Note that the output signal represented by curve  606  is delayed by a predetermined amount of time with respect to the signal represented by curve  604 . The time difference between curve  604  and  606  is represented by Delta T  608 , which is due to the delay to the input signals of the second differential amplifier circuit  508  generated by the transition smoothing circuit  510 .  
         [0042]      FIG. 6B  compares combined output waveforms of the first and second differential amplifiers of  FIGS. 5A and 5B  with and without the transition smoothing differential amplifiers of  FIGS. 5A and 5B  with and without the transition smoothing circuit. Curve  610 , which is a dotted line, represents one of the output signals of the accelerating amplifier circuit  208  when operating without the transition smoothing circuit  510 . The curve  610  represents a sum of the output signals  602  and  604  generated by the first and second differential amplifier circuit  506  and  508 , respectively. Although the combined output signal represented by curve  610  is produced by a high amplification gain, this combined signal includes undesired higher order harmonics at the beginning and end of the signal transition due to the simultaneous switching of both the first and second differential amplifiers.  
         [0043]     Curve  612  represents one of the output signals of the accelerating amplifier circuit  208  when operating with the transition smoothing circuit  510 . In one embodiment, at the beginning of a signal transition when the first differential amplifier circuit  506  is on and the second differential amplifier circuit  508  is not yet on due to the delay of the transition smoothing circuit  510 , the output signal switches at a rate of the output signal of the first differential amplifier circuit  510  alone. Similarly, at the end of a signal transition when the first differential amplifier circuit  506  is off and the second differential amplifier circuit  508  alone. During the period when both the first and second differential amplifier circuits are on, the output signal switches at a combined rate of the outputs of the first and second differential amplifier circuits  506 ,  508 . As a result the combined output signal (represented by curve  612 ) has fewer undesirable higher order harmonics at the beginning and the end of a signal transition, and therefore the electromagnetic interference generated by the simultaneous switching of the first and second differential amplifiers  506 ,  508  ( FIGS. 5A and 5B ) is reduced.  
         [0044]      FIG. 7A  and  FIG. 7B  together illustrate the benefit of the transition accelerating circuit  512  ( FIGS. 5A and 5B ). In particular, curve  702  in  FIG. 7A  represents an output signal transition of the accelerating amplifier circuit  208  without the transition accelerating circuit  512 . This output signal is a combination of the output signals generated by the first and second differential amplifiers  506  and  508 .  
         [0045]      FIG. 7B  compares output signals of the accelerating amplifier circuit  208  with and without the transition accelerating circuit  512 . Curve  704  represents one of the output signals of the accelerating amplifier circuit  208  operating with the transition accelerating circuit  512 . Curve  706 , which is a dotted line and is the same as curve  702  in  FIG. 7A , represents the output signal of the accelerating amplifier circuit  208  operating without the transition accelerating circuit  512 . Note that curve  704  accelerates its rate of transition during the period of a signal transition and therefore it finishes the signal transition faster than the curve  706 . Hence, a benefit of the transition accelerating circuit  512  is that it allows the laser signal more settling time for a signal transition. In other words, it ensures a better “eye quality” of the output laser signal and oz provides more margin for sampling the output laser signal at the next stage.  
         [0046]     One skilled in the relevant art will recognize that there are many possible modifications of the disclosed embodiments that could be used, while still employing the same basic underlying mechanisms and methodologies. For example, different types of transistors, such as FET or MOS transistors, may be used to implement the amplification circuit. One or more pairs of differential amplifiers may be used and combined to drive the output laser signal.  
         [0047]     The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated.