Abstract:
An improved interconnection switch using NMOS passgates is presented which allows the gate voltage of the NMOS passgate to be bootstrapped to a higher voltage than the initial voltage applied thereon so as to allow a higher logic HIGH signal to be passed. The stimulus for this bootstrapping is the transition of the logic signal at the input terminal of the NMOS passgate, which obviates the need for a separate external stimulus. Because the bootstrapping occurs as a result of the dynamic coupling between the gate terminal and the channel of the NMOS passgate, the voltage across the gate oxide does not exceed the magnitude of the logic HIGH signal, thereby rendering the use of thick-oxide devices unnecessary.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This claims the benefit of U.S. Provisional Patent Application No. 60/225,585, filed Aug. 16, 2000. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates to integrated circuit devices, and more particularly to the interconnection switches that may be used in such devices. 
     One of the most commonly-used type of interconnection switch is the single-transistor NMOS passgate. A typical NMOS passgate acts as a switch by selectively “passing” a signal between its source and drain terminals, depending on whether the potential difference between its gate terminal, V GATE , and its source terminal, V SOURCE , exceeds the threshold voltage, V t . (As is well-known in the art, there is no physical difference between the “source” and “drain” terminals of an MOS device; the source terminal of an NMOS transistor is the terminal having the lower voltage.) When V GATE −V SOURCE  is less than V t , the NMOS passgate is in the “cutoff” state, thereby acting as an “open” switch; when V GATE −V SOURCE  is greater than V t , the NMOS passgate is in the conduction state, thereby acting as a “closed” switch. Accordingly, a ceiling is imposed on the output of an NMOS passgate in that it cannot exceed V GATE −V t  (since the NMOS passgate starts to enter the “cutoff” mode when V GATE −V SOURCE  approaches V t ). For example, when V GATE  and a logic HIGH signal to be passed by an NMOS passgate both correspond to the positive supply level, V DD , the signal that may be passed is limited to V DD −V t . (As is well-known in the art, V t  is not a discrete value for an MOS transistor; it may be considered a range of values that is influenced by a variety of second-order effects, such as substrate bias and subthreshold conduction. However, in order to simplify the illustration of the principles of the present invention, V t  will be discussed herein as if it is a discrete value rather than a range of values.) 
     This limit on the logic HIGH level that may be passed by an NMOS passgate renders it problematic for use in integrated circuit devices where the operating voltages (e.g., supply voltages, bias voltages, etc.) may be low enough such that V GATE −V t  may correspond to a voltage that would not be recognized as a logic HIGH signal. With the current trend in using ever-lower operating voltages, which are nearing levels comparable to V t , the ability of single-transistor NMOS passgate structures to reliably pass logic HIGH levels becomes more difficult in view of the influence V t  exerts on the logic levels that may be propagated. 
     SUMMARY OF THE INVENTION 
     The present invention relates to an improved design for interconnection switches that use NMOS passgates. An improved interconnection switch that may be constructed in accordance with the principles of the present invention includes bootstrapping circuitry that allows the gate voltage of an NMOS passgate to be boosted to a higher voltage so as to increase the effective V GATE , thereby raising the V GATE −V t  limit imposed on the logic HIGH signals that may be passed. The stimulus for this bootstrapping is the transition of the logic signal at the input terminal of the NMOS passgate, thereby obviating the need for a separate external stimulus. Because the bootstrapping occurs as a result of the dynamic coupling between the gate terminal and the channel of the NMOS passgate, the voltage across the gate oxide does not exceed the magnitude of the logic HIGH signal, thereby rendering the use of thick-oxide devices unnecessary. 
     Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is an improved interconnection switch that may be constructed in accordance with the principles of the present invention. 
     FIG. 2 is an alternative embodiment of the improved interconnection switch shown in FIG.  1 . 
     FIG. 3 is an alternative embodiment of the improved interconnection switch shown in FIG.  2 . 
     FIG. 4 is a simplified block diagram of a programmable logic device. 
     FIG. 5 illustrates how an aspect of the programmable logic device of FIG. 4 may be improved by employing any of the improved interconnection switches shown in FIGS. 1-3. 
     FIG. 6 is a simplified block diagram of an illustrative system that includes an integrated circuit device employing any of the improved interconnection switches shown in FIGS.  1 - 3 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 shows one embodiment of an improved interconnection switch  10  which may be constructed in accordance with the principles of the present invention. Interconnection switch  10 , which may be turned “on” or “off” depending on a single control signal, V CTRL , includes an NMOS pass transistor  100  coupled to a “native” n-channel transistor  150 , which, as will be described below, may be used to assist in bootstrapping the voltage on gate  103  of NMOS pass transistor  100  to a voltage higher than V CTRL . (“Native”-channel devices, which are available in most semiconductor fabrication processes, are transistors with positive threshold voltages that are close to zero volts). 
     For the purposes of the present invention, V CTRL  may be provided by any of a variety of sources such as a programmable RAM bit, a bias voltage (which may be generated internally or supplied externally, and which may or may not correspond to the supply voltage), or an internally-generated logic signal (which may be static or dynamic). For the purpose of simplifying the discussion of the principles of the present invention, the logic HIGH and LOW signals referred to herein will correspond to the positive and negative supply voltages, V DD  and V SS , respectively. However, it will be appreciated by one skilled in the art that the principles of the present invention are fully applicable to embodiments in which the logic HIGH and LOW values do not correspond to the supply voltages, or here a variety of different biasing and supply voltages are used. 
     As illustrated in FIG. 1, NMOS pass transistor  100  and “native” n-channel transistor  150  are connected such that V CTRL  is provided to the gate  103  of NMOS pass transistor  100  through “native” n-channel transistor  150 , whose gate  153  may be tied to V DD  for this purpose. When V CTRL  is set to V SS , “native” n-channel transistor  150  passes V SS  onto node  110 , such that NMOS pass transistor  100  is in the “cutoff” state. When V CTRL  is set to V DD , the voltage applied on node  110  is approximately V DD  and NMOS pass transistor  100  is in the “on” state in which it acts as a closed switch. (The voltage on node  110  is approximately V DD  because the “native” n-channel transistor  150  has a positive threshold voltage that is close to zero volts, such that the V GATE −V t  limit on signal levels passed by the “native” n-channel transistor  150  is approximately V DD .) 
     While in the “on” state and when V IN  on its input terminal  101  is logic LOW, NMOS pass transistor  100  passes the logic LOW value to its output terminal  102  as V OUT . When V IN  on input terminal  101  changes from logic LOW to logic HIGH, the resulting gate-channel coupling boosts the voltage on gate terminal  103 , which had been set to approximately V DD  by node  110 , to a voltage higher than V DD . While the voltage on gate  103  of NMOS pass transistor  100  is thus bootstrapped above V DD , “native” n-channel transistor  150  serves to isolate V CTRL  on lead  151 , which is at V DD , from node  110 , which is now at the higher bootstrapped voltage level that exceeds V DD . 
     As a result of this bootstrapping, the effective V GATE  of NMOS pass transistor  100  is increased, thereby raising the V GATE −V t  limit on the signal levels that may appear on its output terminal  102 . Over time, node  110  may leak charge and return to V DD ; however, it is not necessary for the bootstrapped voltage to be maintained on gate  103  for an extended period of time: the bootstrapped voltage should be available long enough for the logic HIGH signal to be propagated through NMOS pass transistor  100  and be recognized, and preferably latched, as a logic HIGH signal by the receiving logic (e.g., an inverter, driver, buffer, etc.). 
     When V IN  subsequently transitions from logic HIGH back to logic LOW, the gate-channel coupling brings node  110  below V DD . However, this is temporary since the “native” n-channel transistor  150  drives node  110  back up to approximately V DD  (if V CTRL  is set to V DD ), so as to allow the next rising edge to boost V GATE  via the above-described bootstrapping mechanism. 
     Although the bootstrapped V GATE  may exceed V DD , it is not necessary for NMOS pass transistor  100  to be a thick-oxide device because the bootstrapping occurs as a result of the dynamic coupling between the gate terminal and the channel, such that the voltage across the gate oxide is never greater than V DD . 
     If “native” devices, such as “native” n-channel transistor  150 , are not available or cannot be used, FIG. 2 shows one possible embodiment of an alternative interconnection switch  20  which may be constructed in accordance with the principles of the present invention. Interconnection switch  20  is an alternative embodiment of the interconnection switch  10  shown in FIG. 1 that does not use a “native” n-channel transistor  150  for bootstrapping the voltage on gate  103  of NMOS pass transistor  100  and isolating it from V CTRL . Instead, a pair of standard MOS transistors, PMOS transistor  240  and NMOS transistor  250 , are used for this purpose. Because the general operation of interconnection switch  20  is similar to that of interconnection switch  10 , the ensuing discussion of interconnection switch  20  will focus on their differences. 
     In a manner similar to “native” n-channel transistor  150  of interconnection switch  10 , NMOS transistor  250  of interconnection switch  20  serves to isolate node  210  from V CTRL  on lead  251  when node  210  is bootstrapped to a voltage that exceeds V CTRL . However, unlike “native” n-channel transistor  150 , the threshold voltage of standard NMOS transistor  250  is not close to zero. As a result, when V CTRL  is set to V DD , NMOS transistor  250  applies V DD −V t  on node  210 , which, if used as the gate voltage (without bootstrapping) to turn on NMOS pass transistor  100 , the V GATE −V t  ceiling on signals passed by NMOS pass transistor  100  would be (V DD −V t )−V t =V DD −2V t . Accordingly, in the embodiment shown in FIG. 2, PMOS transistor  240  has been added to pull up node  210  to V DD . 
     For interconnection switch  20 , the process of bootstrapping the voltage on gate  103  of NMOS pass transistor  100  to a voltage higher than V DD  may be illustrated as follows: when V IN  on the input terminal  101  of NMOS pass transistor  100  is logic LOW, the voltage on node  210  is pulled up from V DD −V t  to V DD  by PMOS transistor  240 ; when V IN  changes from logic LOW to logic HIGH, PMOS transistor  240  turns off and node  210 , which had been pulled up to V DD  by PMOS transistor  240 , is then bootstrapped to a voltage above V DD  via gate-channel coupling, thereby allowing NMOS pass transistor  100  to pass a logic HIGH voltage that may be higher than V DD −V t . 
     In order to allow more bootstrapping, PMOS transistor  240  should be turned off as quickly as possible when the voltage on input terminal  101  of NMOS pass transistor  100  transitions from logic LOW to logic HIGH. One example of such an arrangement is illustrated in FIG. 3, which shows an alternative embodiment of interconnection switch  20 . In the interconnection switch  30  shown in FIG. 3, an earlier signal on node  305  is used to turn off PMOS transistor  240  before the voltage on input terminal  101  of NMOS pass transistor  100  transitions from logic LOW to logic HIGH. Although FIG. 3 shows a pair of inverters  301   a/b  being used to introduce a signal delay between node  305  and the input terminal  101  of NMOS pass transistor  100 , any suitable delaying circuit or logic may be used. 
     Although the foregoing discussion illustrates how the principles of the present invention may be used to improve interconnection switch designs that use NMOS passgates, similar improvements may be made to interconnection switches that use PMOS passgates in order to improve the propagation of logic LOW signals. 
     The above-described interconnection switches  10 / 20 / 30  that have been constructed in accordance with the principles of the present invention are especially useful in integrated circuit devices, such as programmable logic devices, in which interconnection switches are used extensively to allow programmable routing and switching. FIG. 4 is a simplified block diagram of an illustrative programmable logic device  40  in which interconnection switches that have been constructed in accordance with the principles of the present invention may be readily used. Programmable logic device  40  includes a plurality of regions of programmable logic  410  operatively disposed in a two-dimensional array of rows and columns, and a programmable network of horizontal  430  and vertical  435  interconnection conductors for conveying signals amongst the logic regions  410  and various I/O structures  480 . In the network of interconnection conductors  430 / 435 , signals may be programmably routed via interconnection switches  400 . In some embodiments, programmable logic device  40  may also include any of a variety of functional blocks  450 , such as memory structures, multiplier/accumulator blocks, arithmetic logic units, microprocessors, etc. Functional blocks  450  may be dedicated structures that are configured to implement a specific function, or, alternatively, they may be user-programmable/reconfigurable structures. 
     FIG. 5 illustrates in greater detail how interconnection switches  400  may be used in the network of interconnection conductors  430 / 435  to route signals within programmable logic device  40 . For the purpose of illustrating the principles of the present invention, a signal source/destination within programmable logic device  40  may be any of the logic regions  410 , functional blocks  450 , I/O structures  480 , or other circuitry within programmable logic device  40 . As shown in FIG. 5, a signal may be routed from any given source to any given destination by using interconnection switches  400  to “switch” signals provided on the output leads  425  of signal source  410 / 450 / 480 /etc. onto the network of interconnection conductors  430 / 435  (within which interconnection switches  400  may also be used to programmably connect one interconnection conductor to another), from which the signal may be eventually “switched onto” the input lead  420  of signal destination  410 / 450 / 480 /etc. As shown in FIG. 5, the electrical characteristics of the network of interconnection conductors  430 / 435  may be represented as a chain of resistors  520  and capacitors  521   a/b  in a “black-box” abstraction. 
     Also shown in FIG. 5 is one embodiment of an interconnection switch  400  that may be constructed in accordance with the principles of the present invention. As illustrated in FIG. 5, interconnection switch  400  may include any of the interconnection switches  10 / 20 / 30  as the switching mechanism. In some embodiments, a pair of inverters  501   a  and  501   b , along with a “half-latch” PMOS transistor  502 , may also be included to provide buffering of the input and output signals. 
     FIG. 6 shows how an integrated circuit device  60  (e.g., a programmable logic device) employing any of the improved interconnection switch structures that have been described in the foregoing may be used in a system  600 . System  600  may include one or more of the following components: various peripheral devices  602 , I/O circuitry  603 , a processor  604 , and a memory  605 . These components may be coupled together by a system bus  601  and may be populated on a circuit board  606  which is contained in an end-user system  607 . 
     System  600  can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application where the advantage of using programmable or reprogrammable logic is desirable. Integrated circuit device  60 , employing interconnection switch structures that have been constructed in accordance with the principles of the present invention, may be used to perform a variety of different logic functions. For example, integrated circuit device  60  can be configured as a processor or controller that works in cooperation with processor  604 . Integrated circuit device  60  may also be used as an arbiter for arbitrating access to a shared resource in system  600 . In yet another example, integrated circuit device  60  may be configured as an interface between processor  604  and one of the other components in system  600 . 
     Various technologies may be used to implement the integrated circuit device  60  employing interconnection switch structures that have been constructed in accordance with the principles of the present invention. Moreover, this invention is applicable to both one-time-only programmable and reprogrammable devices. 
     Thus, it is seen that improved interconnection switch structures for an integrated circuit device have been presented. One skilled in the art will appreciate that the present invention may be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims which follow.