Abstract:
A power supply boosting circuit provides increased pumping efficiency by driving the gate of a transistor in a first precharge circuit with the pumped output voltage from a second precharge circuit, thereby eliminating a threshold voltage drop from the output voltage of the first precharge circuit. The pumped output voltage from the first precharge circuit is then used to precharge a pumping node in a pumping circuit, which in turn, eliminates a threshold voltage drop from the output voltage of the pumping circuit. A transistor in the second precharge circuit can likewise be driven by the pumped output voltage from the first precharge circuit, further increasing the pumping efficiency.

Description:
BACKGROUND OF THE INVENTION 
     This application claims priority from Korean patent application No. 98-21235 filed Jun. 9, 1998 in the name of Samsung Electronics Co., Ltd., which is incorporated by reference. 
     1. Field of the Invention 
     The present invention relates generally to voltage boosting circuits, and more particularly, to power supply voltage boosting circuits having cross-coupled precharge circuits. 
     2. Description of the Related Art 
     Signals in dynamic random access memories (DRAMs) constructed using CMOS transistor technology experience a voltage drop of somewhat more than the threshold voltage of a MOS transistor while being transmitted through the channel region of the MOS transistor. Such voltage drops can cause information loss and interfere with data read and write operations. 
     Continuous increases in the density and capacity of semiconductor memory devices have caused a commensurate increase of power consumption. Therefore, semiconductor memory devices use internal power supply voltages to reduce power consumption and enhance reliability. 
     To correctly read and write data from or to a memory cell composed of a MOS transistor and a capacitor, a voltage sufficient to overcome the threshold voltage of the MOS transistor must be provided. For example, the internal power supply voltage is typically boosted by 1.5V to drive word lines that are connected to the gates of the MOS transistors. 
     FIG. 1 is a block diagram of a conventional power supply voltage boosting circuit, and FIG. 2 is a circuit diagram showing more details of the circuit of FIG.  1 . 
     Referring to FIG. 1, the power supply voltage boosting circuit shown generally at  1  generates a boosted voltage Vpp which is higher than a power supply voltage (for example the internal power supply voltage Vcc) and includes a detector  12 , oscillator  14 , first and second drivers  16  and  22 , first and second pumping circuits  18  and  24  (also referred to as main pumping circuits), and first and second precharge circuits  20  and  26 . 
     Detector  12 , which detects whether the voltage Vpp is higher than a predetermined target voltage level, is coupled to a power line  10  which transfers the voltage Vpp to other circuits. Detector  12  generates a signal DET which goes low to disable the oscillator  14  when Vpp is higher than the target level. When Vpp is lower than the target level, detector  12  drives the signal DET to a logic high level to enable the oscillator. As shown in FIG. 2, detector  12  includes to resistors R 1  and R 2  coupled in series between the power line  10  and a power supply ground terminal. An inverter INV 11  has in input terminal connected to the node between R 1  and R 2  and an output terminal for generating the signal DET. 
     Referring again to FIG. 1, oscillator  14  generates an oscillation signal OSC which is enabled or disabled in response to the detection signal DET. When DET is high, the oscillator  14  outputs the oscillation signal OSC which oscillates with a predetermined period. When DET is low, the oscillation signal OSC is disabled and remains, for example, at a logic high level. As shown in FIG. 2, oscillator  14  includes a 2-input NAND gate G 1  and two series connected inverters INV 2  and INV 3 . Refening again to FIG. 1, the first driver  16 , the first pumping circuit  18  and the first precharge circuit  20  form a first boosted voltage generating section which performs a pumping operation to raise the potential of power line  10  during a first half period of the oscillation signal OSC. As shown in FIG. 2, the first driver  16  includes  3  series connected inverters INV 6 , INV 7  and INV 8 , which receive the oscillating signal OSC and output a first signal φ1. 
     The first pumping circuit  18  includes a pumping capacitor C 2  and two NMOS transistors M 3  and M 4 . Transistor M 3  is diode-connected between Vcc and a pumping node N 2 , and M 4  is diode-connected between node N 2  and the power line  10 . Capacitor C 2  is connected between the output of the first driver  16  and the gate of M 4  at node N 2 . The first precharge circuit  20  includes two inverters INV 4  and INV 5 , a pumping capacitor C 1 , and two NMOS transistors M 1  and M 2 . Inverters INV 4  and INV 5  are connected in series to generate a second signal φ2 in response to OSC. Transistor M 1  is diode-connected between Vcc and a pumping node N 1 , while M 2  is diode-connected between nodes N 1  and N 2 . Capacitor C 1  is connected between the gate of M 2  at node N 1  and the output of INV 5  to receive the signal φ2. 
     Referring back to FIG. 1, the second driver  22 , the second pumping circuit  24 , and the second precharge circuit  26  form a second boosted voltage generating section which performs a pumping operation to raise the potential of power line  10  during a second half period of the oscillation signal OSC. As shown in FIG. 2, the constituent components of the second boosted voltage generating section are essentially identical to those of the first section, with pumping nodes N 3  and N 4  corresponding to pumping nodes N 1  and N 2 , respectively, and signals φ2B and φ1B corresponding to signals φ1 and φ2, respectively. However, the second precharge circuit  26  and the second driver  22  are driven by a second oscillating signal OSCB which is complement of OSC and is obtained through inverter INV 9 . Because the two sections operate during alternate half cycles of the oscillation signal OSC, two pumping operations are performed during each cycle of OSC. 
     The operation of the power supply voltage boosting circuit  1  will now be described more thoroughly with reference to FIGS. 1 and 2. 
     When the oscillation signal OSC switches from a high to a logic low level, capacitor C 1  in the first precharge circuit  20  performs a negative pumping operation so that node N 1  is charged to a voltage of VCC-Vtn via the transistor M 1  (where Vtn represents a threshold voltage of an N-type MOS transistor). Since the output signal φ1 from the first driver  16  switches to a logic high level, node N 2  in the first pumping circuit  18  is boosted to 2VCC-Vtn via capacitor C 2 . 
     At the same time, since the output signal φ1B from the second driver  22  switches to a logic low level, capacitor C 4  in the second pumping circuit  24  performs a negative pumping operation so that node N 4  is charged to a voltage of VCC-Vtn via the NMOS transistor M 7 . Node N 3  in the second precharge circuit  26  is boosted to 2VCC-Vtn by the capacitor C 3 , so that node N 4  is then precharged to a voltage of 2VCC-2Vtn. Hereinafter, the above described operation is referred to as “a precharge pumping operation”. 
     When the oscillation signal OSC switches from a low to a logic high level, the power line  10  is boosted to 3VCC-3Vtn by the second pumping circuit  24 , and node N 2  is precharged to a voltage of 2VCC-2Vtn through the first precharge circuit  20 . 
     More specifically, at the low-to-high transition of OSC, the signal φ1B from the second driver  22  goes high, so node N 4  is boosted to 3VCC-2Vth via capacitor C 4 . Therefore, the power line  10  is boosted to 3VCC-3Vtn through NMOS transistor M 8  (hereinafter, the above described operation is referred to as “a main pumping operation”). Capacitor C 3  performs a negative pumping operation, so node N 3  is charged to a voltage of VCC-Vtn. At the same time, capacitor C 2  in the first pumping circuit  18  performs a negative pumping operation because the signal φ1 from the first driver  16  switches to a logic low level. Capacitor C 1  pumps node N 1  in the first precharge circuit  20  to a voltage of 2VCC-Vtn in response to the signal φ2 from the invertor INV 5  so that node N 4  is precharged to a voltage of 2VCC-2Vtn. That is, the precharge pumping operation is performed. 
     As described above, at the low-to-high transition of the oscillation signal OSC, the precharge pumping operation for node N 2  is performed while the second pumping circuit  24  performs the main pumping operation. On the other hand, at the high-to-low transition of the oscillation signal OSC, the precharge pumping operation for node N 4  is performed while the first pumping circuit  18  performs the main pumping operation. Therefore, according to the above described boosting circuit structure, it is possible to speed up the pumping operation because the two pumping operations are performed during alternate half-cycles of the oscillation signal OSC. 
     However, the threshold voltage drops of the NMOS transistors M 1  and M 5  in the first and second precharge circuits  20  and  26  reduce the pumping efficiency. That is, since node N 1  is charged to a voltage of VCC-Vtn before the precharge pumping operation, node N 2  has a voltage of 2VCC-2Vtn after the precharge pumping operation. Therefore, when the main pumping operation is performed, the voltage Vpp on the power line  10  is only pumped to 3VCC-3Vtn. If the power supply voltage VCC is about 2 volts and the threshold voltage Vtn is about 1 volt, the voltage Vpp on the power line  10  is only pumped to about 3 volts (3×2volts−3×1 volt) which is inadequate to sufficiently turn on a memory cell transistor when it is applied to the gate of the transistor. As a result, the circuit  1  illustrated in FIG. 2 has a low pumping efficiency. Furthermore, if the power supply voltage VCC is reduced, the pumping efficiency of the circuit of FIG. 2 becomes even lower due to the threshold voltage drops of the transistors M 1  and M 5 . 
     SUMMARY OF THE INVENTION 
     In a power supply voltage boosting circuit according to the present invention, the gate of a transistor in a first precharge circuit is driven by a pumped precharge voltage generated in a second precharge circuit, thereby eliminating a threshold voltage drop from a pumping node in the first precharge circuit. This allows the first precharge circuit to pump a node in a pumping circuit to a higher precharge voltage level, which in turn, eliminates a threshold voltage drop from the output voltage of the pumping circuit, thereby increasing the pumping efficiency of the power supply boosting circuit. 
     A transistor in the second precharge circuit can likewise be driven by the pumped precharge voltage from the first precharge circuit, further increasing the pumping efficiency. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be described by way of exemplary embodiments, but not limitations, illustrated in the accompanying drawings in which like references denote similar elements, and in which: 
     FIG. 1 is a block diagram showing a conventional power supply voltage boosting circuit; 
     FIG. 2 is a circuit diagram showing more details of the conventional power supply voltage boosting circuit illustrated in FIG. 1; 
     FIG. 3 is a first embodiment of a power supply voltage boosting circuit according to the present invention; 
     FIG. 4 is a diagram showing voltage levels at various nodes of the power supply voltage boosting circuit illustrated in FIG. 3; 
     FIG. 5 is a second embodiment of a power supply voltage boosting circuit according to the present invention; and 
     FIG. 6 is a third embodiment of a power supply voltage boosting circuit according to the present invention. 
    
    
     DETAILED DESCRIPTION 
     FIG. 3 is a first embodiment of a power supply voltage boosting circuit according to the present invention, and FIG. 4 is a diagram showing voltage levels at various nodes of the power supply voltage boosting circuit  100  illustrated in FIG.  3 . 
     The power supply voltage boosting circuit  100  shown in FIG. 3 differs from the conventional boosting circuit  1  shown in FIG. 2 in that NMOS transistor M 9  in the first precharge circuit  150  is not arranged in a diode-connected configuration, but instead, the gate of M 9  is connected to node N 3  in the second precharge circuit  180 . As a result of this configuration, the voltage applied to the gate of M 9  is sufficient to overcome the threshold voltage of transistor M 9 . Therefore, node N 1  in the first precharge circuit  150  is charged to a voltage of VCC instead of VCC-Vtn. 
     The operation of the power supply voltage boosting circuit  100  according to the first embodiment of the present invention will be more fully described with reference to FIGS. 3 and 4. 
     When the oscillation signal OSC switches from a logic high level to a logic low level, capacitor C 11  in the first precharge circuit  150  performs a negative pumping operation so that node N 1  is charged via NMOS transistor M 9  whose gate is coupled to node N 3 . Since the signal φ1 from the first driver  130  switches to a logic high level, the capacitor C 12  pumps node N 2  in the first pumping circuit  140  to a voltage of 2VCC-Vtn. 
     At the same time, the capacitor C 14  in the second pumping circuit  170  performs a negative pumping operation because the signal φ1B from the second driver  160  switches to a logic low level, thus node N 4  is charged to a voltage of VCC-Vtn. The capacitor C 13  in the second precharge circuit  180  pumps node N 3  to 2VCC-Vtn. Node N 4  is precharged to a voltage of 2VCC-2Vtn via the NMOS transistor M 14 . That is, the precharge pumping operation has been performed. 
     It can be seen that the gate voltage of the transistor M 9  is raised to 2VCC-Vtn during the precharge pumping operation for node N 4  (that is, at the high-to-low transition of the oscillation signal OSC). Therefore, node N 1  in the precharge circuit  150  is charged to the power supply voltage VCC instead of VCC-Vtn. 
     As the oscillation signal OSC repeatedly transitions from a logic low level to a logic high level, the main pumping operation associated with the second pumping circuit  170  is performed repeatedly. More specifically, when the signal φ1B from the second driver  160  transitions to a logic high level, node N 4  is boosted to 3VCC-2Vth via capacitor C 14 . Therefore, a voltage of 3VCC-3Vtn is delivered to the power line  10  through NMOS transistor M 16  (that is, the main pumping operation has been performed). At this time, the capacitor C 3  performs a negative pumping operation, thus node N 3  is charged to a voltage of VCC-Vtn. 
     The precharge operation for node N 2  is performed at the low-to-high transition of the oscillation signal OSC. More specifically, capacitor C 12  in the first pumping circuit  140  performs a negative pumping operation because the signal φ1 from the first driver  130  switches to a logic low level. Capacitor C 11  pumps node N 1  in the first precharge circuit  150  to 2VCC because node N 1  is charged to VCC at the previous high-to-low transition of the oscillation signal OSC. Therefore, node N 2  is precharged to a voltage of 2VCC-Vtn instead of 2VCC-2Vtn (that is, the precharge pumping operation has been performed). 
     When the oscillation signal OSC transitions from a logic high level to a logic low level, capacitor C 12  pumps node N 2  in response to the logic high level of signal φ1 from the first driver, so that node N 2  is boosted to a voltage of 3VCC-Vtn. Therefore, the potential on the power line  10  is raised further. 
     In the above-described power supply voltage boosting circuit  100 , the gate of transistor M 9  is supplied with a voltage sufficient to overcome its threshold voltage drop (for example, a voltage higher than VCC+Vtn). This enables node N 1  to be charged to the power supply voltage VCC, resulting in an increase in the pumping efficiency of the power supply voltage boosting circuit  100 . 
     FIG. 5 is a second embodiment of a power supply voltage boosting circuit  100  according to the present invention. In FIG. 5, the constituent elements that are identical to those in FIG. 3 are labeled with the same or like reference numerals. 
     The power supply voltage boosting circuit  100  according to the second embodiment of the present invention differs from the conventional boosting circuit  1  shown in FIG. 2 in that the gate of NMOS transistor M 13  in the second precharge circuit  180  is connected to node N 1  in the first precharge circuit  150 . Due to this configuration, a voltage sufficient to overcome the threshold voltage of NMOS transistor M 13  is supplied to the gate of transistor M 13 . 
     The operation of the second embodiment of the power supply voltage boosting circuit  100  according to the present invention will be more fully described with reference to FIG.  5 . 
     When the oscillation signal OSC transitions from a logic high level to a logic low level, capacitor C 11  in the first precharge circuit  150  performs a negative pumping operation, so that node N 1  is charged to a voltage of VCC-Vtn. Since the signal φ1 from the first driver  130  switches to a logic high level, capacitor C 12  pumps node N 2  in the first pumping circuit  140  to a voltage of 2VCC-Vtn. 
     At the same time, capacitor C 14  in the second pumping circuit  170  performs a negative pumping operation because the signal φ1B from the second driver  160  switches to a logic low level, and then node N 4  is charged to a voltage of VCC-Vtn. At this time, capacitor C 13  pumps node N 3  in response to the logic high level on signal φ2B so node N 3  is charged to a voltage less than 2VCC-Vtn because the gate of NMOS transistor M 13  is connected to node N 1 . As a result, node N 4  is precharged to a voltage less than 2VCC-2Vtn via NMOS transistor M 14 . 
     When the oscillation signal OSC transitions from a logic low level to a logic high level, a main pumping operation is performed by the second pumping circuit  170 . That is, capacitor C 14  pumps node N 4  in response to the signal φ1B from the second driver  160  transitioning to a logic high level. The boosted voltage on node N 4  is then transferred to the power line  10  through NMOS transistor M 16 . 
     The precharge operation for node N 2  is also performed at the low-to-high-transition of the oscillation signal OSC. In particular, capacitor C 12  performs a negative pumping operation in response to the signal φ1 being at a logic low level, and capacitor C 11  pumps node N 1  in the first precharge circuit  150  in response to the logic high level of signal φ2 from the invertor INV 15  to charge N 1  to a voltage of 2VCC-Vtn. As a result, node N 2  is precharged to a voltage of 2VCC-2Vtn. 
     At this time, it can be seen that a voltage sufficient to overcome the threshold voltage drop of the transistor M 13  is supplied to the gate of the transistor M 13  from node N 1  so that node N 3  is charged to VCC. Then, at the high-to-low transition of the oscillation signal OSC, node N 4  is precharged to a voltage of 2VCC-Vtn as set forth above. When the oscillation signal OSC transitions from a logic low level to a logic high level, capacitor C 14  pumps node N 4  to a voltage of 3VCC-Vtn. Therefore, the power line  10  is raised to a voltage of 3VCC-2Vtn during the main pumping operation. 
     In the above described power supply voltage boosting circuit  100  of FIG. 5, the gate of transistor M 13  is supplied with a voltagc (for example, a voltage higher than VCC+Vtn) sufficient to overcome its threshold voltage drop. This enables node N 3  to be charged to VCC, thereby increasing the pumping efficiency of the circuit  100 . 
     FIG. 6 shows a third embodiment of a power supply voltage boosting circuit  100  according to the present invention. In FIG. 6, the constituent elements that are identical to those in FIGS. 3 and 5 are labeled with the same or like reference numerals. 
     As shown in FIG. 6, the third embodiment of the power supply voltage boosting circuit  100  differs from the conventional boosting circuit  1  as follows. As with the first embodiment of the present invention, the gate of transistor M 9  in the first precharge circuit  150  is coupled to node N 3  in the second precharge circuit  180 . And, as with the second embodiment of the present invention, the gate of transistor M 13  in the second precharge circuit  180  is coupled to node N 1  in the first precharge circuit  150 . 
     As a result of the above described circuit configuration, it can be seen that nodes N 1  and N 3  are charged up to the power supply voltage VCC because a voltage sufficient to overcome the threshold voltage drop is supplied to the gates of transistors M 9  and M 13 . Nodes N 2  and N 4  are precharged to 2VCC-Vtn instead of 2VCC-2Vtn during their respective precharge pumping operation, and then during the respective main pumping operations, the power line  10  is boosted to 3VCC-2Vtn through the pumping circuits  140  and  170 . Accordingly, the power supply voltage boosting circuit  100  according to the third embodiment has an even higher pumping efficiency than that of the first and second embodiments. 
     Having described and illustrated the principles of the invention in a preferred embodiment thereof, it should be apparent that the invention can be modified in arrangement and detail without departing from such principles. We claim all modifications and variations coming within the spirit and scope of the following claims.