Abstract:
The present invention is a method and system to reduce defects in conductive surfaces during electrochemical processes. The system includes a first power supply and a second power supply. The first powers supply is configured to supply a first power between a conductive surface of a workpiece and an electrode of the system. The second power supply is configured to supply a second power between the conductive surface and the electrode when a switching unit switches from the first power from the first power supply to the second power from the second power supply in response to the conductive surface contacting the process solution.

Description:
FIELD  
       [0001]     The present invention relates to manufacture of semiconductor integrated circuits and, more particularly to a method for electrochemical deposition of conductive layers.  
       BACKGROUND  
       [0002]     Conventional semiconductor devices such as integrated circuits generally include a semiconductor substrate, such as a silicon substrate, and a plurality of sequentially formed dielectric interlayers and conductive paths or interconnects made of conductive materials. Copper and copper-alloys have recently received considerable attention as interconnect materials because of their superior electro-migration and low resistivity characteristics. Interconnects are usually formed by filling copper by a metallization process, into features or cavities etched into the dielectric layers. The preferred method of copper metallization is electrodeposition or electroplating. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in sequential layers can be electrically connected using vias.  
         [0003]     In a typical process, first an insulating layer is formed on the semiconductor substrate. Patterning and etching processes are performed to form features or cavities such as trenches and vias in the insulating layer. Then, a barrier/glue layer and a seed layer are deposited over the patterned surface and a conductor such as copper is electroplated to fill all the features.  FIG. 1  exemplifies a surface portion of a semiconductor substrate  10  or a wafer having features such as cavities  12 ,  13  and  14 . The cavities are formed in a dielectric layer  16 , which is deposited on the substrate  10 . Before the electroplating step, cavities  12 - 14  and the top surface of the dielectric layer  16  are coated with a barrier layer  18  and a seed layer  20 . During the copper electrodeposition process, specially formulated plating solutions or electrolytes are used to plate copper onto the seed layer. An exemplary electrolyte contains water, acid (such as sulfuric acid), ionic species of copper, chloride ions and certain additives, which affect the properties and the plating behavior of the deposited material.  FIG. 2  shows a simplified schematic of a typical electrodeposition system  50  for processing the wafer  10  in an electroplating solution  52  contained in a chamber  53 . The wafer  10  is held by a carrier head  54  so that the front surface  56 , which is lined with the seed layer  20  ( FIG. 1 ), is exposed to the electroplating solution  52 . During the process, a potential difference is applied between the front surface  56  and an anode  58  by a power supply  60  and material deposition onto the front surface  56  from the solution  52  is achieved.  
         [0004]     It is a known fact that process solutions may chemically interact with seed layers at the beginning of an electrochemical process. Thin copper seed layers, for example, are chemically attacked and may be damaged by the process solutions when the work piece is first introduced into the process solution. This is especially a serious problem for wafers with narrow and deep features. In such substrates, the seed layer thickness may be extremely thin especially deep in the narrow features. For example, for 0.15 micrometer wide, 1.0 micrometer deep, the seed layer thickness may be only 20-50 A on the lower portion of the sidewalls of the via, whereas the seed layer thickness at the top surface of the dielectric may be 800 A or more. Thickness of the seed layers and their profiles within the features of the wafers are strong functions of the seed layer deposition equipment and process.  
         [0005]     It should be appreciated that electrodeposition solutions, especially those with acidic pH has certain degree of etching rate for the material to be deposited. For example, depending upon the exact formulation, sulfuric acid based copper deposition electrolytes may have a copper etch rate of 5-200 A/min. Therefore, thin seed layers within the features on a wafer may get chemically attacked within a very short period once the wafer surface is wetted by the solution. This period, in some cases, maybe in the order of milliseconds, especially if the seed layer is very thin and it contains oxides which easily dissolve in the solutions used. Etching rate of copper oxide is much higher than etching rate of pure copper in acidic electrolytes.  
         [0006]     Hot entry is one way of avoiding this unwanted interaction between the process solution and the seed layer, when wafers with thin or weak seed layers are immersed into the process solutions for electroplating. During hot-entry, a voltage is applied to the seed layer before it is wetted by the process solution. This cathodic voltage protects the seed layer against chemical dissolution and material deposition starts immediately onto the seed layer. However, hot entry has some drawbacks, such as formation of hot spots, which are high current density spots and therefore high deposition locations on the wafer where the solution makes the initial physical contact with the seed layer.  
         [0007]      FIGS. 3A-3B  exemplify various stages of formation of the hot spots on the seed layer  20  and the effects of hot spots on the plated layer.  FIG. 3A  illustrates an instant of initial contact between the process solution  52  and the seed layer  20  on the wafer  10  while a plating voltage is applied to the seed layer  20  through the power supply  60 . As the wafer  10  is lowered onto the solution, seed layer  20  first may contact ripples  62  on surface of the process solution  52 . These ripples may be due to various sources. Vibrations of the various system components or simply movement of the process solution during the process may generate such ripples or small waves. It should be noted that ripples represent specific locations where the solution first makes physical contact with the wafer surface. These locations may not necessarily be due to waves or ripples. For example, in tool designs where the wafer enters the solution at an angle, only one small portion of the substrate surface first touches the solution. The hot-spot problem that we are about to describe takes place at that location in that case.  
         [0008]     Referring back to  FIG. 3A , as the tips of the ripples touch the seed layer, since a voltage has already been applied between the seed layer and an anode (not shown), current flows from the anode, through the process solution  52  and to the seed layer  20  only through the contact spots  64 , depositing copper in the process, preferentially and instantaneously onto the seed layer locations defined by the contact spots  64 . Contact spots  64  represent a very small area fraction compared to the total area of the wafer surface. Therefore, during this initial plating the current density at the contact spots  64  is high and as shown in  FIG. 3B , it causes almost instantaneous formation of individual copper growths  66  at the location of contact spots  64 . These copper growths  66  are also called hot spots. From this point on, if the plating process is continued, a copper layer  68  with a non-uniform thickness is formed on the seed layer, as shown in  FIG. 3C . Due to the growths  66 , thickness of the layer  68  on the hot spots  64  is thicker than the rest of the layer, which is an unwanted situation in manufacture of interconnects. It should be noted that the sketches of  FIGS. 3A through 3C  are not drawn to scale. The depth of the features may actually be smaller than the height of the ripples. Therefore, hot spots may form not only on the top surface of the dielectric but also within the features causing defects in the features. Furthermore, the size of the hot spots may change from sub-micron to several millimeters.  
         [0009]     To address the problem described above, some prior art methods use cold entry, i.e. entry of the substrate into the solution with no applied voltage and then apply the plating voltage. However, as discussed previously, upon cold entry, thin, oxidized or weak seed layers may get chemically attacked by the process solution within a time period of one second or less unless there is an applied cathodic voltage to protect them.  
         [0010]     To this end there is a need for plating methods that provide uniform deposition layers without defects even on substrates with weak seed layers.  
       SUMMARY OF THE INVENTION  
       [0011]     The present invention is a method and apparatus to reduce defects in conductive layers during electrochemical material deposition or electrochemical material removal.  
         [0012]     The process of the present invention uses multiple power supplies and multiple process voltages or currents to avoid formation of defects on seed layers and at the same time allow defect-free deposition of a conductor, such as copper, on wafers. In one embodiment, a first power from a first power supply is provided to the seed layer prior to contacting the seed layer to the surface of the electroplating solution. Upon contacting the solution, switching from the first power from the first power supply to a second power from a second power supply automatically takes place.  
         [0013]     According to an aspect of the present invention, a system for electroprocessing a conductive surface on a workpiece using a process solution and an electrode while holding the workpiece with a workpiece carrier is disclosed. The system comprises a first power supply configured to supply a first power between the conductive surface and the electrode, a second power supply configured to supply a second power between the conductive surface and the electrode, and a switching unit for switching the first power to the second power in response to the conductive layer contacting the process solution.  
         [0014]     According to another aspect of the present invention, method of electroprocessing a conductive surface on a workpiece is provided. The electroprocessing uses a process solution and an electrode wetted by the process solution. The method includes the steps of applying a first power between the conductive surface and the electrode using a first power supply, contacting the conductive surface to the process solution, and applying a second power between the surface and the electrode using a second power supply. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]      FIG. 1  is a schematic cross sectional view of a portion of a semiconductor substrate including features and surface of the substrate coated with a conductive layer;  
         [0016]      FIG. 2  is a schematic side view of a conventional electrochemical deposition system;  
         [0017]      FIGS. 3A-3C  are schematic cross-sectional views showing various stages of the formation of the hot spot defects on the conductive layer of the substrate shown in Figure land the effects of the defects on the electroplated layer;  
         [0018]      FIG. 4  is a schematic view of the system of the present invention including at least two power supplies; and  
         [0019]      FIGS. 5A-5D  are schematic cross sectional views showing various stages of a process of an embodiment of the present invention on a semiconductor substrate. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0020]     The process of the present invention uses multiple power supplies and multiple process voltages or currents to avoid formation of hot spots on the seed layer and at the same time allow defect-free deposition of a conductor, such as copper, on wafers lined with thin seed layers, such as seed layers that are thinner than 30 nm. In one embodiment, a first power such as a contact voltage or current from a first power supply is provided to the seed layer prior to contacting the seed layer to the surface of the electroplating solution. Upon contacting the solution, switching from the contact voltage or current from the first power supply to a second power such as an electroplating voltage or current from a second power supply is automatically performed and is applied to the seed layer. As will be explained more fully below, the contact current is significantly lower than the electroplating current. As a result, as the physical contact is established between the certain spots of the surface and the waves or ripples of the solution, current density at these spots is not high enough to form high-rate deposition or hot spots. In this embodiment, action of switching from the contact current to the electroplating current begins as soon as the seed layer touches the surface of the electroplating solution. Electroplating begins when a full contact between the wafer surface and the solution is established. The invention has the capability to switch from one power supply to the other within 200 milliseconds (ms) or earlier, avoiding formation of hot spots and at the same time preventing chemical dissolution of weak seed layers.  
         [0021]      FIG. 4  shows an exemplary system  100  to perform the process of the present invention. The system  100  includes process chamber  102  to contain the process solution  104 . Wafer  106  is held by a wafer carrier  108  and rotated. Wafer may additionally be moved vertically and laterally. Front surface  110  of the wafer  106  includes a seed layer, which will be described below. In this embodiment, the surface  110  and anode  111  of the system  100  are configured to be connected to two power supplies, namely a first power supply (FPS)  112  and a second power supply (SPS)  113 . The power supplies  112 ,  113  may preferably be connected to the anode and the surface through a switching unit  114 , which allows sequential use of the power supplies. The switching unit may include power switches S 1 , S 2 , S 3  and S 4 . Switch S 1  connects the negative terminal of the first power supply  112  to the surface  110  of the wafer  106  when the switch S 1  is in closed position. Switch S 2  connects the positive terminal of the first power supply  112  to the anode  111  when the switch S 2  is in closed position.  FIG. 4  shows switches S 1  and S 2  in closed position (and switches S 3  and S 4  are in open position) so that surface  110  and the anode  111  are connected to and energized by the first power supply  112 .  
         [0022]     Switch S 3  connects the negative terminal of the second power supply  113  to the surface  110  of the wafer  106  when the switch S 3  is in closed position. Similarly, switch S 4  connects the positive terminal of the second power supply  113  to the anode  111  when the switch S 4  is in closed position. When switches S 3  and S 4  are in closed position and the switches S 1  and S 2  are in open position, plating current is connected to and energizes the surface  110  of the wafer and the anode. Power switches S 1 -S 4  may be made of solid-state relays and associated circuitry. The system of the present invention may include multiple power supplies and corresponding multiple switch pairs to perform the present invention using multiple powers.  
         [0023]     The first power supply  112  includes a monitoring terminal  115  to monitor activity of the first power supply  112 . When power supply provides current for the system, the monitoring terminal, in response, generates a signal output. In one embodiment, the signal output of the monitoring terminal  115  is received by a detector  116 , preferably an analog detector. A control signal from the analog detector  116  to the switching unit  114  controls the switches S 1 -S 4 .  
         [0024]     In a sequential use of the power supplies, at a first stage of the process, the first power supply  112  is set to provide a first current. At this time, the switches S 1  and S 2  are in closed position and the switches S 3  and S 4  are in open position, and there is no current passing between the surface of the wafer and the anode until a physical contact between the surface and the solution is established. As soon as the physical contact is established between the surface and the solution, the initial small current dictated by FPS  112  flows from the solution to the seed layer. Current flow or sensing the current flow causes an output signal (contact signal) from the monitoring terminal to the analog detector  116 . The analog detector sends a control signal (command signal) to the switches S 1 -S 2  of the switching unit  114 . Upon receipt of the control signal, the switches S 1  and S 2  are brought into open position while the switches S 3  and S 4  are brought into closed position and, thereby allowing a second current from the second power supply  113  to be applied between the front surface of the wafer and the anode. It is understood that, power supplies used in the invention may be on and ready to be switched to the connecting process circuitry. Power is supplied from one or the other by using the switching unit.  
         [0025]     In this embodiment, the first current is denoted as contact current and the second current is denoted as electroplating current. It is understood that, in this embodiment, the contact current is significantly lower than the electroplating current and therefore, prevents formation of the hot spots when the wafer surface first touches the solution at certain locations. The contact current may vary depending on the chemistry and the acidity of the process solution. For example, for a low acid chemistry from Enthone, the contact current for a 300 mm diameter wafer may be in the range of 0.1-1.0 A. The electroplating current on the other hand may be 5 A or higher.  
         [0026]      FIGS. 5A-5D  exemplify stages of the process of the present invention using an exemplary portion of the surface  110  of the wafer  106 . The surface  110  of the wafer may include various features, such as vias  120  and trenches  121  formed in a dielectric layer  122 . Features and surface of the dielectric layer is coated with a barrier layer  124  and a copper seed layer  126 . An electrical contact  128  connects the seed layer  126  to the switches S 1  and S 3 , which are in turn connected to the negative terminals of the first and second power supplies.  
         [0027]     As shown in  FIG. 5B , as the wafer  106  is lowered onto surface  130  of the process solution  104 , the seed layer is connected to the first power supply  112  through switch S 1 , and the FPS is programmed to apply the contact current. Height of ripples  132  on the surface  130  of the solution  104  may be less than 2 mm. The ripple height may be defined as the distance between surface level of the solution  104  and tip  134  of the ripples  132 .  
         [0028]     As shown in  FIG. 5B , as the wafer  106  is lowered onto the solution with z motion of the carrier head  108 , and at one instant, the tips  134  of the ripples  132  touch the seed layer at contact locations  136 . This causes low contact current to flow to the contact locations  136  from the process solution  104 . As described above, this action generates a signal output from the monitoring terminal for analog detector  116 . As described above, upon receipt of the signal, the analog detector  116  controlling the series of switches, switches the connection to the first power supply  112  off and switches the connection to the second power supply  113  on, thus initiating electroplating of the copper onto the seed layer at the plating current density provided by the second power supply. For best results, the time of switching needs to be at least in the range of the travel time of the wafer surface for the ripple height, i.e., the time spent between the initial contact of the tip of the ripples with the seed layer and the time when surface is fully wetted by the solution. The critical importance of the switching time is that the high plating current should not be switched on before the ripples totally disappear from the wafer surface. In other words, contact between the solution and the seed layer should be full rather than local when the high current is switched on. In the present invention, using two power supplies and the z-motion of the carrier head, allows switching from low current to high current conditions in a very short time such as less than 200 milliseconds, preferably less than 100 ms, while preventing problems on the seed layer.  
         [0029]     As shown in  FIG. 5C , as the wafer is fully submerged into the solution  104 , the second power supply  113  is connected between its surface and an anode. As shown in  FIG. 5D , as the plating current is applied from the second power supply  113 , a copper layer is uniformly plated on the seed layer  126 .  
         [0030]     In one exemplary process sequence for a 200 mm diameter wafer, the first power supply is set to a small current value of between 0.05 to 0.2 amps. Using the carrier head, the wafer is brought down onto the solution with a speed of 20-40 mm/sec. As soon as the wafer touches the process solution, monitoring terminal output is received by an analog detector having a sampling rate of 1 ms. The analog detector sends a signal to a circuit of solid state relays to switch the anode and wafer connections from the first power supply (contact current) to the second power supply (electroplating current). As solid state relays are very fast, this switching action occurs very fast in a time period of 5-100 ms.  
         [0031]     Although various preferred embodiments and the best mode have been described in detail above, those skilled in the art will readily appreciate that many modifications of the exemplary embodiment are possible without materially departing from the novel teachings and advantages of this invention.