Abstract:
An apparatus comprising a first one or more threshold devices, a second one or more threshold devices and a logic device. The first one or more threshold devices may be configured to control an output. The second one or more threshold devices may be configured to receive the output. The logic device may be (i) coupled to the second one or more threshold devices and (ii) configured to provide a feedback to the first one or more threshold devices. The feedback may be configured to force a reset condition if a metastable event occurs.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     The present application may relate to co-pending application Ser. No. 09/877,659, filed Jun. 7, 2001, Ser. No. 09/877,660, filed Jun. 7, 2001, and Ser. No. 09/877,659, filed Jun. 7, 2001, which are each hereby incorporated by reference in their entirety. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a method and/or architecture for implementing a discriminator circuit generally and, more particularly, to a metastable insensitive circuit configured to arbitrate between requests based on pulse discriminators. 
     BACKGROUND OF THE INVENTION 
     Hardware devices are employed within computer systems to assist in determining the availability of computer resources (i.e., a memory chip, a hard disk drive, etc.) which can only be controlled and accessed by one requesting device at a time. However, metastable conditions can exist when contention between requests from different devices occurs. Arbitrators (or arbiters) have been designed to reduce bus contention through flags (or other such means). However, arbitrators can enter metastable states during simultaneous requests. Conventional arbitrators can therefore enter an undecided state and remain for an indefinite period of time, causing undesirable results (i.e., a system crash or hang, etc.). 
     Referring to FIG. 1, a circuit  10  is shown illustrating a conventional arbitration circuit. The circuit  10  comprises a NAND gate  12 , a NAND gate  14  and an interlock circuit  16 . The NAND gate  12  receives the signal A and an output from the NAND gate  14 . The NAND gate  14  receives a signal B and an output from the NAND gate  12 . The interlock circuit  16  presents a signal OUTA and a signal OUTB in response to the signal from the NAND gates  12  and  14 . The NAND gates  12  and  14  are implemented in a cross-coupled configuration. Therefore, the NAND gates  12  and  14  can enter a metastable condition. 
     Referring to FIG. 2, a timing diagram of the circuit  10  is shown. The input A and the input B are shown crossing between a time T 1  and a time T 2 . The period between the time T 1  and T 2  illustrates the metastable event which can cause a push out. The circuit  10  is subject to metastability when the inputs A and B change states simultaneously. 
     The interlock circuit  16  attempts to resolve metastable states, but does not prevent metastable events. The arbitration circuit  10  implements cross coupled NAND arbiters ( 12  and  14 ) which cause delays due to metastable events. The resolution (or recovery) time of the cross coupled arbiters  12  and  14  is not predictable. While the interlock circuit  16  can try to prevent metastable states from occurring on the outputs, the interlock circuit  16  does not resolve the occurrence of the metastable events. Conventional arbitrators attempt to reduce the probability of metastable occurrences rather than eliminate such occurrences. 
     It is desirable to provide a method and/or architecture that eliminates metastable conditions due to simultaneous requests. 
     SUMMARY OF THE INVENTION 
     One aspect of the present invention concerns an apparatus comprising a margin logic circuit, one or more discriminator circuits and a sense circuit. The margin logic circuit may be configured to receive a plurality of requests and present one or more control signals. The one or more discriminators may be configured to (i) present one or more leading access signals and (ii) receive the one or more control signals and the plurality of requests. The sense circuit may be configured to receive the one or more leading access signals and the plurality of requests and present grant access signal. The sense circuit may be configured to reduce the effects of metastable conditions. 
     Another aspect of the present invention concerns an apparatus comprising a first one or more threshold devices, a second one or more threshold devices and a logic device. The first one or more threshold devices may be configured to control an output. The second one or more threshold devices may be configured to receive the output. The logic device may be (i) coupled to the second one or more threshold devices and (ii) configured to provide a feedback to the first one or more threshold devices. The feedback may be configured to force a reset condition if a metastable event occurs. 
     The objects, features and advantages of the present invention include providing an arbitration circuit based on pulse discriminators that may (i) reduce the effects of metastable conditions, (ii) effect arbitration between two (or more) asynchronous requests, (iii) reduce delays associated with metastable events, and/or (iv) force a reset of a metastable condition. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
     FIG. 1 is a block diagram of a conventional metastable recovery circuit; 
     FIG. 2 is a timing diagram of the conventional circuit of FIG. 1; 
     FIG. 3 is a block diagram of a preferred embodiment of the present invention; 
     FIG. 4 is a detailed block diagram of the circuit of FIG. 3; 
     FIG. 5 is a more detailed block diagram of the circuit of FIGS. 3 and 4; 
     FIG. 6 is a more detailed block diagram of the circuit of FIGS. 3,  4  and  5 ; 
     FIG. 7 is a diagram of an alternate embodiment of the present invention; 
     FIG. 8 is a diagram of another alternate embodiment of the present invention; and 
     FIG. 9 is a block diagram of a discriminator of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 3, a block diagram of a circuit  100  is shown in accordance with a preferred embodiment of the present invention. The circuit  100  may be implemented as an arbitration circuit based on pulse discriminators. The circuit  100  may be implemented, for example, in applications where requests for data cannot be delayed. However, the circuit  100  may be implemented in other applications as well. The circuit  100  may be particularly useful in applications where an almost instantaneous decision may be required between two asynchronous requests. Since only one request is generally serviced at a time, one request is generally serviced and the other request may be required to wait. Additionally, the system  100  may be configured to service both requests or tasks within a predetermined time, such that the requests may be serviced in either order. 
     In a particular example, simultaneous requests in dual port memory applications may be received requiring access to the same memory space. The pair of accesses (or requests) should be serviced within a particular time (e.g., one clock cycle) before another pair of accesses are requested. Simultaneous requests may cause metastable states (e.g., a state with uncertain (or circumstantial stability) to occur). The circuit  100  may eliminate such occurrences (or potential danger) of metastable states. While metastability cannot be fully eliminated, knowledge of potential metastable occurrences may allow for an improved (e.g., metastable insensitive) design as provided by the circuit  100 . 
     The circuit  100  will be described in the particular context of a dual port implementation. The circuit  100  may be implemented with any number of ports in order to meet the criteria of a particular implementation. The circuit  100  may have an input  102  that may receive a signal (e.g., REQX), an input  104  that may receive a signal (e.g., REQY), an output  106  that may present a signal (e.g., GRANTY) and an output  108  that may present a signal (e.g., GRANTX). In one example, the signals REQX and REQY may be implemented as request signals and the signals GRANTX and GRANTY may be implemented as bus grant signals. 
     Referring to FIG. 4, a more detailed diagram of the circuit  100  is shown. The circuit  100  generally comprises a block (or circuit)  110 , a block (or circuit)  112 , a block (or circuit)  114  and a block (or circuit)  116 . The circuit  110  may be implemented as a margin logic circuit. The circuit  112  may be implemented as a discriminator circuit. The circuit  114  may be implemented as a discriminator circuit. The circuit  116  may be implemented as a sense logic circuit. 
     The margin logic circuit  110  may receive the signal REQX and the signal REQY. The margin logic circuit  110  may have an output  124  that may present a signal (e.g., A) and an output  126  that may present a signal (e.g., B). The discriminator  112  may have an input  128  that may receive the signal REQY and an input  130  that may receive the signal A. The discriminator circuit  112  may generate the signal GRANTY. The discriminator  112  may present the signal GRANTY in response to the signal REQY and the signal A. The discriminator  114  may have an input  134  that may receive the signal B, an input  136  that may receive the signal REQX and an output  138  that may present a signal (e.g., X). 
     The sense logic circuit  116  may have an input  140  that may receive the signal GRANTY and an input  142  that may receive the signal X. The sense logic circuit  116  may also have an input  144  that may receive the signal REQX and an input  146  that may receive the signal REQY. The sense logic circuit  116  may generate the signal GRANTX. The sense logic circuit  116  may present the signal GRANTX in response to the signals GRANTY, X, REQX and/or REQY. 
     Referring to FIG. 5, a more detailed diagram of the circuit  100  is shown. The margin logic circuit  110  is shown in more detail as a block (or circuit)  150  and a block (or circuit)  152 . The circuit  150  may be implemented as a leading margin circuit. The circuit  152  may also be implemented as a leading margin circuit. The circuits  150  and  152  may each receive the signals REQX and REQY and present the signal A and the signal B, respectively. The select logic circuit  116  generally comprises a block (or circuit)  160  and a block (or circuit)  162 . The circuit  160  may be implemented as a delay circuit. The circuit  162  may be implemented as a sense circuit. The delay circuit  160  may receive the signals REQX and REQY and present a signal (e.g., X=Y). The sense circuit  162  may receive the signals GRANTY, X and X=Y and present the signal GRANTX. The sense circuit  162  may be configured to determine when (i) the signal REQX leads REQY, (ii) the signal REQY leads REQX, and/or (iii) when the signal REQX is in close proximity to the signal REQY. 
     Referring to FIG. 6, a more detailed diagram of the circuit  100  is shown. The circuit  150  is shown implemented as an inverter  170 , a gate  172 , a circuit  174  and a gate  176 . The gates  172  and  176  may be implemented as AND gates. However, other gates may be implemented accordingly to meet the design criteria of a particular implementation. The circuit  152  may be implemented as an inverter  180 , a gate  182 , a circuit  184  and a gate  186 . The gates  182  and  186  may be implemented as AND gates. However, other gates may be implemented accordingly to meet the design criteria of a particular implementation. The circuit  174  may be a delay circuit. The circuit  184  may be a delay circuit. In one example, the delay circuits  174  and  184  may be implemented as leading margin delay circuits. The leading margin delay circuits  174  and  184  may have a predetermined delay, in one example, of 50-150 ps, more preferably 75-125 ps, most preferably 100 ps. Optional delay devices (not shown) may be implemented within the device paths of the circuit  150  and/or  152 . Moreover, the delay devices may be programmable. 
     The circuit  160  may be implemented as a gate  190  and the circuit  192 . The circuit  192  may be implemented as a delay circuit. In one example, the circuit  142  may be implemented as a matching delay circuit. The delay circuit  192  may have a predetermined delay. The circuit  162  may be implemented as an inverter  194 , an inverter  196 , a gate  198  and a gate  200 . The gate  198  may be implemented as an AND gate. The gate  200  may be implemented as an OR gate. An optional control signal (not shown) may be presented to the gate  198 . The optional control signal may allow a user to select between forcing the request REQX and the request REQY. The particular type of the gates  198  and  200  may be varied accordingly to meet the design criteria of a particular implementation. For example, the inverters  194  and  196  may be implemented as inverter inputs to the gate  198 . 
     The inverter  194  may receive the signal GRANTY. The signal GRANTY may indicate when the signal REQY leads the signal REQX by a leading margin. The inverter  196  and the gate  200  may receive the signal X. The signal X may indicate when the signal REQX leads the signal REQY by a leading margin. The gate  198  may receive an output of the inverter  194 , an output of the inverter  196  and the signal X=Y. The signal X=Y may indicate when the signal REQX and the signal REQY are in close proximity. An output of the gate  198  may be presented to the gate  200 . The gate  200  may present the signal GRANTX. The sense circuit  116  may force the signal GRANTX if the signal X=Y is active. 
     Referring to FIG. 7, an alternate embodiment  100 ′ of the circuit  100  is shown. The circuit  100 ′ may be similar to the circuit  100 . However, the sense circuit  162 ′ may also be configured to present a signal (e.g., CLOSE_PROX). The signal CLOSE_PROX may indicate a close proximity of the requests REQX and REQY. Additionally, the sense circuit  162 ′ may have a reduced complexity (e.g., the gate  200  is removed from the alternate embodiment). 
     Referring to FIG. 8, another alternate embodiment  100 ″ of the circuit  100  is shown. The circuit  100 ″ may be similar to the circuit  100 . The circuit  100 ″ may be implemented in a simple form. 
     The signal REQY may be presented to the inverter  170 ″. The inverter  170 ″ may present an output to the gate  172 ″ and the settling circuit  174 ″. In one example, the gate  172 ″ may be implemented as a NOR gate. However, other appropriate type gates may be implemented to meet particular design criteria. The signal REQX may be presented to the gate  172 ″ and the matching delay  192 ″. The gate  172 ″ may present a signal to an input of the discriminator  112 ″ and the settling delay  174 ″ may present a signal to a reset of the discriminator  112 ″. The discriminator  112 ″ may present a signal (e.g., Y) in response to the gate  172 ″ and the settling delay  174 ″. The signal Y may be presented to the sense circuit  116 ″. The matching delay  192 ″ may also present the signal X to the sense circuit  116 ″. 
     The sense circuit  116 ″ may present the signals GRANTX_B and GRANTY_B in response to the signals X and Y. The signal Y may be presented to the inverter  194 ″. The inverter  194 ″ may present the signal GRANTY_B. The signal X may be presented to a first input of the gate  198 ″ and the signal GRANTY_B may be presented to a second input of the gate  198 ″. The gate  198 ″ may be implemented as a NAND gate. However, other appropriate type gates may be implemented to meet a particular criteria. The gate  198 ″ may present the signal GRANTX_B. 
     Referring to FIG. 9, a more detailed diagram of the discriminator circuit  112  is shown. Although a particular implementation of the discriminator  112  is shown, other appropriate architectures may be implemented. However, the discriminator  112  may be used to sense and conceal metastable events. The discriminator circuit  114  may be similar to the discriminator  112 . The discriminator  112  generally comprises a transistor  210 , a transistor  212 , a transistor  214 , an inverter  216 , an inverter  218 , an inverter  220 , an inverter  222  and a gate  224 . The gate  224  may be implemented as an NOR gate. The inverters  216  and  218  may be implemented as inverters with high thresholds. The inverters  220  and  222  my be implemented as inverters with low thresholds. The low threshold inverters  220  and  222  may be implemented to sense and conceal metastable events. Alternatively, the inverters  220  and  222  may be implemented as inverter inputs to the gate  224 . The transistors  210 ,  212  and  214  may be implemented as CMOS transistors. However, other appropriate type transistors may be implemented to meet a particular criteria. 
     Alternatively, the circuits  100 ,  100 ′ or  100 ″ may implement delay devices on the request paths REQX and REQY. The delay devices may be optionally programmable. Optionally, a control signal may be presented to the sense logic circuit  116  to allow a user to select between forcing a first request (REQX) and a second request (REQY). In such a case, the sense logic circuit  116  may require additional components. 
     The circuit  100  may provide an arbitration circuit based on pulse discriminators ( 112  and  114 ) that may (i) reduce the effects of metastable conditions, (ii) effect arbitration between two (or more) asynchronous requests, (iii) reduce delays associated with metastable events, and/or (iv) force a reset of a metastable condition. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.