Abstract:
A phase-frequency detector (PFD) with increased phase error gain during acquisition of phase lock when used in a phase-locked loop (PLL). The reference and feedback signals are time-multiplexed into N pairs of input signals. Each pair of input signals is detected by one of N phase-frequency detectors, which produce N pairs of detection signals indicative of phase differences between the reference and feedback signals. These N pairs of detection signals are combined in separate logical-OR operations to produce a frequency increase control signal and a frequency decrease control signal indicative of when the feedback signal frequency is lower and higher, respectively, than the reference signal frequency. These control signals have respective substantially nonzero signal values that vary in respective relations to the difference between the reference and feedback signal phases when such phase difference is less than 2π radians, and repeat with patterns having phase difference intervals of 2Nπ radians when such phase difference is greater than 2π radians.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to digital phase-locked loops (PLLs), and in particular, to phase-frequency detectors (PFDs) used in such digital PLLs. 
     2. Description of the Related Art 
     Referring to FIG. 1, a conventional PFD that has been used in many digital PLL designs includes two D-type flip-flops  12   u ,  12   d  and a logic AND gate  14 . The flip-flops  12   u ,  12   d  are separately clocked by the reference signal REF and feedback signal FB. With each rising edge of these input signals REF, FB, a logic one (VDD applied at the D-input) is clocked through to the output Q of each flip-flop  12   u ,  12   d . The data output signals Q of the flip-flops  12   u ,  12   d  form the “pump up”. UP and “pump down” DN signals used for controlling a charge pump circuit  20 . Whenever the reference signal REF leads the feedback signal FB in phase, the pump up signal UP is asserted. Conversely, when the feedback signal FB leads the reference signal REF in phase, the pump down signal DN is asserted. When the pump up signal UP is asserted (and inverted by the inverter  18  within the charge pump  20 ), the output pull-up transistor P 1  is turned on, thereby causing electrical charge to be pumped to the output terminal  21 . Conversely, when the pump down signal DN is asserted, the output pull-down transistor N 1  is turned on, thereby causing electrical charge to be sunk from the output terminal  21 . 
     The logic AND gate  14  ensures that the data output signals Q of the flip-flops  12   u ,  12   d  are cleared in the event that both the pump up signal UP and pump down signal DN become asserted simultaneously. 
     A logic OR gate  16  can be included, as shown, so as to enable the user to place the PFD  10  in a high impedance state. By asserting the control signal HiZ, the output  17  of the logic OR gate  16  is also asserted, thereby clearing both output signals Q of the flip-flops  12   u ,  12   d . With both of these signals UP, DN in their cleared, or unasserted, states, both output transistors P 1 , N 1  of the charge pump are turned off, thereby leaving the output terminal  21  of the charge pump  20  in a high impedance state. 
     This type of PFD  10  is widely used due to the advantages afforded by its transfer function. As is well known, this type of PFD  10  has a transfer function such that the output signal  23  of the charge pump  20 , due to the control signals UP, DN provided by the PFD  10 , depends upon the phase difference between the two input signals REF, FB when the host PLL is in its phase-locked state, and depends upon the frequency difference between the input signals REF, FB when the host PLL is in its unlocked state. Accordingly, a digital PLL in which this PFD  10  is used will lock under any condition, in terms of the input signals REF, FB, regardless of the type of loop filter in use. 
     Referring to FIG. 2, by way of example, the timing diagrams are shown for the input REF, FB and output UP, DN signals when the host PLL (not shown) is not phase-locked, in this case with the feedback signal FB being slightly lower in frequency than the reference signal REF. Since the feedback signal FB lags the reference signal REF, the net output of the PFD  10  is “up,” i.e., the pump up signal UP is asserted, thereby seeking to increase the output frequency of the host PLL and, therefore, increase the frequency of the feedback signal FB. Accordingly, the duty cycle of this PFD output UP gradually increases until the point in time when the feedback signal FB lags the reference signal REF by approximately 360°, or 2π radians, in phase (at approximately the 300 nanosecond point in time for this example). At this point in time, the duty cycle of the PFD output UP changes from being nearly 100% to 0%. 
     Referring to FIG. 3, most loop filters  22  have low pass frequency characteristics and typically consist of a serially-connected resistor R and capacitor C 1  connected in shunt with another capacitor C 2 , as shown. When the duty cycle of the PFD output signal UP is high, and particularly as it is increasing, the voltage  23  across the loop filter  22  rises. Hence, this loop filter voltage  23  is higher at the end of each successive charge pump update. However, when the duty cycle is low, and particularly as it is decreasing, this loop filter voltage  23  decreases even though the net charge being delivered to the loop filter  22  by the positive pulses of the PFD signal UP continues to be positive. This is due to the fact that most loop filters  22  use second order loop filters, such as that shown here, where the series capacitors C 1  has a larger capacitance value than the shunt capacitor C 2 . As a result, before the loop filter  22  achieves its final state of equilibrium, the voltage on the smaller capacitor C 2  is higher than the voltage across the larger capacitor C 1 . Hence, if the duty cycle of the PFD output signal UP (or DN) is not high enough, the net change of the loop filter output voltage  23  can be negative. 
     SUMMARY OF THE INVENTION 
     A phase-frequency detector (PFD) in accordance with the presently claimed invention has increased phase error gain during acquisition of phase lock when used in a phase-locked loop (PLL). The reference and feedback signals are time-multiplexed into N pairs of input signals. Each pair of input signals is detected by one of N phase-frequency detectors, which produce N pairs of detection signals indicative of phase differences between the reference and feedback signals. These N pairs of detection signals are combined to produce frequency increase and decrease control signals indicative of when the feedback signal frequency is lower and higher, respectively, than the reference signal frequency. These control signals have respective substantially nonzero signal values that vary in respective relations to the difference between the reference and feedback signal phases when such phase difference is less than 2π radians, and repeat with patterns having phase difference intervals of 2Nπ radians when such phase difference is greater than 2π radians. 
     In accordance with one embodiment of the presently claimed invention, a PFD having increased phase error gain during acquisition of phase lock when used in a PLL includes routing circuitry, phase-frequency detection circuitry and combining circuitry. The routing circuitry receives and selectively routes reference and feedback signals having respective signal frequencies and phases to provide respective pluralities of reference and feedback signals. The phase-frequency detection circuitry, coupled to the routing circuitry, receives and detects the pluralities of reference and feedback signals to provide a plurality of detection signals having respective substantially nonzero signal values that vary in respective relations to: a difference between the reference and feedback signal phases when the signal phase difference is less than 2π radians; and a difference between the reference and feedback signal frequencies when the signal phase difference is greater than 2π radians. The combining circuitry, coupled to the phase-frequency detection circuitry, combines the plurality of detection signals to provide: a frequency increase control signal indicative of when the feedback signal frequency is lower than the reference signal frequency; and a frequency decrease control signal indicative of when the feedback signal frequency is higher than the reference signal frequency. 
     In accordance with another embodiment of the presently claimed invention, a PFD having increased phase error gain during acquisition of phase lock when used in a PLL includes input circuitry, output circuitry and a plurality N of phase-frequency detection circuits. The input circuitry receives reference and feedback signals having respective signal frequencies and phases and in response thereto provides a plurality of input signals. The output circuitry receives a plurality of output signals and in response thereto provides first and second control signals indicative of when the feedback signal frequency is lower and higher, respectively, than the reference signal frequency. The plurality N of phase-frequency detection circuits, coupled between the input and output circuitry, processes the plurality of input signals to provide the plurality of output signals. The first and second control signals have respective substantially nonzero signal values that: vary in respective relations to a difference between the reference and feedback signal phases when the signal phase difference is less than 2π radians; and repeat with patterns having phase difference intervals of 2Nπ radians when the signal phase difference is greater than 2π radians. 
     In accordance with still another embodiment of the presently claimed invention, a PFD having increased phase error gain during acquisition of phase lock when used in a PLL includes router means, phase-frequency detector means and combiner means. The router means is for receiving and selectively routing reference and feedback signals having respective signal frequencies and phases and providing respective pluralities of reference and feedback signals. The phase-frequency detector means is for receiving and detecting the pluralities of reference and feedback signals and providing a plurality of detection signals having respective substantially nonzero signal values that vary in respective relations to: a difference between the reference and feedback signal phases when the signal phase difference is less than 2π radians; and a difference between the reference and feedback signal frequencies when the signal phase difference is greater than 2π radians. The combiner means is for combining the plurality of detection signals and providing: a frequency increase control signal indicative of when the feedback signal frequency is lower than the reference signal frequency; and a frequency decrease control signal indicative of when the feedback signal frequency is higher than the reference signal frequency. 
     In accordance with yet another embodiment of the presently claimed invention, a PFD having increased phase error gain during acquisition of phase lock when used in a PLL includes input means, output means and phase-frequency detector means. The input means is for receiving reference and feedback signals having respective signal frequencies and phases and in response thereto providing a plurality 2N of input signals. The output means is for receiving a plurality 2N of output signals and in response thereto providing first and second control signals indicative of when the feedback signal frequency is lower and higher, respectively, than the reference signal frequency. The phase-frequency detector means is for processing the plurality 2N of input signals and providing the plurality 2N of output signals. The first and second control signals have respective substantially nonzero signal values that: vary in respective relations to a difference between the reference and feedback signal phases when the signal phase difference is less than 2π radians; and repeat with patterns having phase difference intervals of 2Nπ radians when the signal phase difference is greater than 2π radians. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a conventional PFD circuit and associated charge pump circuit. 
     FIG. 2 is a signal-timing diagram for the signals of the circuit of FIG.  1 . 
     FIG. 3 is a functional block and schematic diagram of a conventional charge pump circuit, loop filter circuit and voltage-controlled oscillator used in a PLL. 
     FIG. 4 is a schematic diagram of a PFD circuit in accordance with one embodiment of the presently claimed invention. 
     FIG. 5 is a signal-timing diagram for the signals of the circuit of FIG.  4 . 
     FIG. 6A is a graph of the transfer function for the circuit of FIG.  1 . 
     FIG. 6B is a graph of the transfer function for the circuit of FIG.  4 . 
     FIG. 7 is a graph comparing the loop filter output voltages over time for the circuits of FIGS. 1 and 4 when used in a PLL. 
     FIG. 8 is a graph comparing the average duty cycles for the output signals of the circuits of FIGS. 1 and 4. 
     FIG. 9 is a schematic diagram of a PFD circuit in accordance with another embodiment of the presently claimed invention. 
     FIG. 10 is a schematic diagram of a PFD circuit in accordance with still another embodiment of the presently claimed invention. 
     FIG. 11 is a graph of the generalized transfer function for the circuits of FIG. 4,  9  and  10 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 4, a PFD circuit  100  in accordance with one embodiment of the presently claimed invention has an input stage  112 , a PFD stage  114  and an output stage  116 . The PFD stage  114  uses conventional PFD circuits  10  (FIG.  1 ). The output signals UP 1 , DN 1 , UP 2 , DN 2  of the respective PFD circuits  10  are combined in the logic OR gates  116   u ,  116   d  to produce the overall, or composite, output control signals UP, DN. 
     At the input, the reference REF and feedback FB signals are time-multiplexed to provide the respective reference REF 1 , REF 2  and feedback FB 1 , FB 2  signals to the PFD circuits  10 . In this particular embodiment, where two PFD circuits  10  are used, this multiplexing function can be performed using two D-type flip-flops  112   u ,  112   d , connected as shown. Each flip-flop  112   u ,  112   d  is connected in the well known toggle configuration in which the inverted output QZ is fed back to the D-input. 
     The PFD circuits  10  are conventional in design and process their respective input signals REF 1 , FB 1 , REF 2 , FB 2  to provide their respective output signals UP 1 , DN 1 , UP 2 , DN 2  in accordance with the discussion above concerning the circuit  10  of FIG.  1 . 
     Referring to FIG. 5, by way of an example, the operation of this circuit  100  when the frequency of the feedback signal FB is lower than the frequency of the reference signal REF is as follows. As is shown, as the signal waveforms progress over time, the lower frequency feedback signal FB increasingly lags in phase relative to the higher frequency reference signal REF. As can be seen by the resulting output signals UP 1 , DN 1 , UP 2 , DN 2  from the respective PFD circuits  10 , the duty cycles of the asserted internal control signals UP 1 , UP 2  do not wrap, or revert to their unasserted states, when the phase difference reaches 2π radians. Instead, the duty cycles remain close to 100% for the interval of time that the phase error is between 2π and 4π radians. Accordingly, these control signals UP 1 , UP 2  have higher average duty cycles (over multiples of 2π radians of phase) as compared to the corresponding output signal UP (FIG. 2) of the conventional PFD circuit  10  (FIG.  1 ). 
     By combining these signals UP 1 , UP 2 , with their higher duty cycles, in the output stage  116 , an overall, or composite, output control signal UP is obtained in which the duty cycle is, in fact, 100% during this time interval. (As should be understood, when the frequency of the feedback signal FB is, conversely, higher than the frequency of the reference signal REF, the foregoing discussion remains true, but with the pump up UP and pump down DN signals interchanged.) 
     Referring to FIGS. 6A and 6B together, a difference in the performance of the PFD circuit of FIG. 4 as compared to that of the PFD circuit of FIG. 1 can be visualized by plotting the average PFD output signal/PFD_output/verses the input phase error θerr, i.e., the phase difference between the input signals REF, FB. As shown in FIG. 6A for the circuit of FIG. 1, the average PFD output signal value/PFD_output/, e.g., the signal  23   a  across the loop filter  22 .(FIG.  3 ), is proportional to the phase error θerr when such phase error θerr is less than 2π radians, i.e., between −2π (lag) and +2π (lead) radians. When the phase error θerr becomes greater than 2π radians, the output signal/PFD_output/begins to wrap and becomes proportional to the phase error θerr in a pattern that repeats every 2π radians. (It will be appreciated that this same characteristic is demonstrated by the average of the actual pump up UP and pump down DN control signals generated by the PFD circuit.) 
     Referring to FIG. 6B, the characteristic plot for the average PFD output signal/PFD_output/versus phase error θerr for the circuit of FIG. 4 demonstrates the same transfer function when the phase error θerr is less than 2π radians, i.e., that of proportionality. Hence, the PFD circuit of FIG. 4 performs as a conventional PFD circuit (FIG. 1) when the host PLL is in the last stages of phase lock or is already phase-locked (−2π&lt;θerr&lt;+2π). However, when the phase error θerr becomes greater than 2π radians, but is less than 4π radians, the average PFD output signal/PFD_output/remains at its maximum value, and remains at this maximum value until the phase error θerr reaches 4π radians. At that point, the transfer function begins to wrap, and begins to repeat in a pattern extending over 4π radians of phase error θerr. 
     Referring to FIG. 7, the effect of this difference in transfer functions can also be visualized by plotting the filtered PFD output signal 23 v/123 v across the loop filter  22  (FIG. 3) which serves as the control voltage for the voltage-controlled oscillator (VCO)  24  used by the host PLL. For the conventional circuit  10  of FIG. 1, this control voltage 23 v transcends many minimum and maximum peak values prior to reaching its steady state value  223  following acquisition of phase lock. In contrast, the control voltage 123 v produced by filtering the improved output signals from the PFD circuit  100  of FIG. 4 experiences far fewer interim signal peaks and achieves the steady state value 223 sooner since the host PLL achieves phase lock more rapidly. 
     Referring to FIG. 8, this difference in transfer functions can be visualized in yet another way by plotting the average duty cycle of the PFD output signals UP, DN versus the input frequency ratio Ffb/Fref, i.e., the ratio of the feedback signal frequency Ffb to the reference signal frequency Fref. As for the examples discussed above for the circuits of FIGS. 1 and 4, when the feedback signal frequency Ffb is lower than the reference signal frequency Fref, this ration is less than unity, and the pump up control signal UP has a high duty cycle. As shown by plot  11  for the circuit of FIG.  1  and plot  111  for the circuit of FIG. 4, the corresponding duty cycle for the output control signal for the circuit of FIG. 4 remains significantly higher for a longer interval than the control signal for the circuit of FIG. 1, thereby demonstrating a significantly higher phase error gain. Due to this higher average duty cycle for a given input frequency difference, the PFD circuit  100  of FIG. 4 can charge the loop filter faster, and thereby produce a faster PLL frequency lock time. 
     Referring to FIG. 9, in accordance with the present invention, the PFD circuit  100  of FIG. 4 can be expanded to a PFD circuit  200  in which the PFD stage  214  uses 4 conventional PFD circuits  10 . The input stage  212  performs the multiplexing of the input reference REF and feedback FB signals, while the output stage  216  continues to provide the logical OR operations for combining the respective pump up UP 1 , UP 2 , UP 3 , UP 4  and pump down DN 1 , DN 2 , DN 3 , DN 4  signals. 
     The input signals REF, FB are multiplexed using counters  220  and multiplexor circuits  222 . The inverters  218  are used so as to cause the counters  220  to increment on the falling, or trailing, edges of the incoming clock signals REF, FB. (This prevents timing problems cause by not allowing for sufficient setup time for the input signals REF, FB presented to the inputs of the multiplexors  222   u ,  222   d .) The output signals  221  of the counters  220  serve as the control signals for the multiplexors for selecting the appropriate output signal REF 1 , REF 2 , REF 3 , REF 4 , FB 1 , FB 2 , FB 3 , FB 4  to be active and provided to the corresponding PFD circuit  10 . Upon reaching their terminal counts, these counters  220  reset to zero and begin incrementing once again. 
     Referring to FIG. 10, the PFD circuits  100 ,  200  of FIGS. 4 and 9 can be further expanded to a PFD circuit  200 N in which N conventional PFD circuits  10  are used. The operation of this circuit  200 N is the same as the circuit  200  of FIG. 9 when N equals four. When N is greater than four: the counters  220  count to the higher number N−1 (0, 1, . . . , N−1); there are more (log 2 N) counter output signals  221 ; there are N multiplexed reference signals REF 1 , REF 2 , . . . , REFN; there are N feedback signals FB 1 , FB 2 , . . . , FBN; there are N PFD pump up output signals UP 1 , UP 2 , UPN; and there are N PFD pump down output signals DN 1 , DN 2 , . . . , DNN. 
     Referring to FIG. 11, and with reference to FIGS. 6A and 6B, the transfer function for the circuits of FIGS. 4,  9  and  10  can be generalized as shown. During the interval in which the phase error θerr is less than 2π radians, the average PFD output signal/PFD_output/is proportional to such phase error θerr. So long as the phase error θerr is greater than 2π radians, and less than 2Nπ radians, the average PFD output signal/PFD_output/remains at its maximum. This signal reverts to zero at a phase error θerr of 2Nπ radians, following which it again becomes proportional to the phase error θerr for the next 2π radians of phase error θerr. This pattern then repeats for successive phase difference intervals of 2Nπ radians. 
     Various other modifications and alterations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.