Abstract:
A super I/O module for controlling at least one I/O port of a computer system is provided. The super I/O module includes a controller, a signal detector and a selector. The controller supports functions corresponding to the I/O port. The signal detector receives an input signal from the I/O port, and detects whether the input signal has an identification code. When detecting that the input signal has the identification code, the signal detector generates a selection signal according to the identification code. The selector receives the selection signal and selectively provides the input signal to the controller or a function circuit of the computer system according to the selection signal.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This Application claims priority of Taiwan Patent Application No. 99116107, filed on May 20, 2010, the entirety of which is incorporated by reference herein. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The invention relates to a super input/output (I/O) module of a computer system, and more particularly to a method for controlling the devices of a computer system by using a super I/O module. 
         [0004]    2. Description of the Related Art 
         [0005]    At present, data for performing a power-on process is stored in a serial peripheral interface (SPI) flash memory of computer systems. Therefore, when the updating procedure of a flash memory on a main board of a computer system fails, a maintenance engineer must open a housing of the computer system, and then de-solder the flash memory. Next, the maintenance engineer uses a recorder to update the data stored in the de-soldered flash memory. Next, the maintenance engineer solders the flash memory that has been completely updated back to the main board, and then puts back the housing of the computer system. Therefore, traditionally, the maintenance engineer must perform complicated procedures to update the flash memory. In addition, if the de-soldering or soldering of the flash memory fails, the computer system can not normally work. 
         [0006]    Therefore, a control method is desired to control, debug or update the internal circuits of a computer system without removing a housing/case of the computer system. 
       BRIEF SUMMARY OF THE INVENTION 
       [0007]    A super I/O module, a computer system and a control method thereof are provided. An embodiment of a super I/O module for controlling at least one I/O port of a computer system is provided. The super I/O module includes a controller, a signal detector and a selector. The controller supports functions corresponding to the I/O port. The signal detector receives an input signal from the I/O port and detects whether the input signal has an identification code. The signal detector generates a select signal according to the identification code when detecting that the input signal has the identification code. The selector receives the select signal and selectively provides the input signal to the controller or a function circuit of the computer system according to the select signal. 
         [0008]    Furthermore, an embodiment of a computer system is provided. The computer system comprises at least one I/O port for receiving an input signal, a super I/O module and a function circuit. The super I/O module comprises: a controller for supporting functions corresponding to the I/O port; a signal detector for detecting whether the input signal has an identification code, and generating a select signal according to the identification code when detecting that the input signal has the identification code; and a selector. The selector selectively provides the input signal to the controller or the function circuit according to the select signal. 
         [0009]    Moreover, an embodiment of a control method for a computer system with a super I/O chip is provided. A first input signal is received via an I/O port of the computer system, wherein the I/O port is coupled to the super I/O chip. An identification code of the first input signal is detected. The first input signal is selectively provided to the controller or the function circuit according to the detected identification code of the first input signal. The controller is implemented in the super I/O chip and supports functions corresponding to the I/O port. 
         [0010]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0011]    The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0012]      FIG. 1  shows a computer system according to an embodiment of the invention; 
           [0013]      FIG. 2  shows an identification code table illustrating the identification codes corresponding to various circuits of a computer system according to an embodiment of the invention; and 
           [0014]      FIG. 3  shows a control method for a computer system with a super I/O chip according to an embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0015]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0016]    In a computer system, such as desktop computer, notebook computer, etc., a super Input/Output (I/O) module comprises various I/O controllers which control a PS/2 port, serial port, parallel port, and game port of the computer system to communicate with the peripheral devices of the computer system. The I/O controller, for example, can be a PS/2 port controller, a serial port controller, a parallel port controller or a game port controller. The PS/2 port controller can be used to control a keyboard and a mouse both coupled to the PS/2 port, and the parallel port controller can be used to control a printer coupled to the parallel port. 
         [0017]      FIG. 1  shows a computer system  100  according to an embodiment of the invention. The computer system  100  includes an I/O port  110 , a super I/O module  120 , a serial peripheral interface (SPI) flash memory  130 , a joint test action group (JTAG) circuit/bus  140  and a universal asynchronous receiver/transmitter (UART)  150 . The super I/O module  120  can be implemented in a super I/O chip, wherein the super I/O module  120  includes a signal detector  122 , a selector  124  and a controller  126  corresponding to the I/O port  110 . For example, the I/O port  110  can be a PS/2 port coupled to a keyboard  180  and a mouse  160 , and the controller  126  can be a PS/2 port controller for receiving the signals (e.g. the data signal DATA and the clock signal CLK) from the keyboard  180  and the mouse  160  and performing subsequent processes. In the embodiment, the PS/2 port is used as an example for description, and does not limit the invention. In another embodiment, the I/O port  110  can be another type of I/O port, such as the serial port, parallel port, or game port, and the controller  126  can be another type of I/O port controllers, such as the serial port controller, parallel port controller, or game port controller according to the type of the I/O port  110 . The central processing unit (CPU), north bridge chip, south bridge chip, and power module of the computer system  100  is not be described in detail herein in order to simplify descriptions. 
         [0018]    In  FIG. 1 , the signal detector  122  determines whether an input signal Sin has a specific identification code when receiving the input signal Sin via the I/O port  110 . For example, if a simulator  170  is connecting to the I/O port  110 , the simulator  170  may provide a signal with a specific identification code to the computer system  100  via the I/O port  110 , so as to control, debug, record or update the circuits within the computer system  100 . In the embodiment, the simulator  170  may control the SPI flash memory  130 , the JTAG circuit  140  and the UART  150  via the I/O port  110 . If the mouse  160  and/or the keyboard  180  is connected to the I/O port  110 , the signal received via the I/O port  110  does not have the specific identification code. Thus, the signal detector  122  may not provide a select signal Sel to the selector  124 . In such a case, the selector  124  may keep the last function option of control, debug, record or update without performing any switching of the function option. 
         [0019]    Referring to  FIG. 2 ,  FIG. 2  shows an identification code table illustrating the identification codes corresponding to various circuits of a computer system according to an embodiment of the invention. 
         [0020]    Referring to  FIG. 1  and  FIG. 2  together, when the simulator  170  wants to update the SPI flash memory  130  via the I/O port  110 , the simulator  170  can provide the input signal Sin with an identification code ID 1  to the super I/O module  120 . Next, the signal detector  122  determines whether the input signal Sin has a specific identification code, and then identifies that the identification code of the input signal Sin is ID 1 . Subsequently, the signal detector  122  generates the signal Sel according to the identification code ID 1  to control the selector  124 , so as to provide the input signal Sin to the SPI flash memory  130  but not provide the input signal Sin to the other circuits (e.g. the controller  126  etc.). In one embodiment, the selector  124  can be a de-multiplexer. Therefore, before a next identification code is identified by the signal detector  122 , the selector  124  may sequentially transmit the signals from the simulator  170  to the SPI flash memory  130 . Thus, a user can update the data (e.g. Basic Input Output System (BIOS)) of the SPI flash memory without removing a housing of the computer system  100 . Similarly, the simulator  170  may also provide the input signal Sin with an identification code ID 2  to the super I/O module  120 . Next, the signal detector  122  may identify that the identification code is ID 2 , and then may control the selector  124  to provide the signals from the I/O port  110  to the JTAG circuit  140 , so as to debug a portion of circuits of the computer system  100  via the JTAG circuit  140 . Moreover, the simulator  170  may also provide the input signal Sin with an identification code ID 3  to the super I/O module  120 . Next, the signal detector  122  may identify that the identification code is ID 3 , and then may control the selector  124  to provide the signals from the I/O port  110  to the UART  150  for communication. The JTAG circuit  140  may also be implemented in the super I/O module  120  for debugging a microcontroller (not shown) of the super I/O module  120 . Similarly, the UART  150  can also be implemented in the super I/O module  120 . 
         [0021]    In one embodiment, the simulator  170  may provide a specific check code) to the super I/O module  120  prior to the specific identification code. The specific check code, for example, can be a cyclic redundancy check (CRC) code for speeding up the determination of the specific identification code for the signal detector  122 , wherein a length of the specific check code is determined according to actual applications. For example, if the specific check code is a 64 k bits CRC16 code, the signal detector  122  may receive the CRC16 code first, and then may further detect the input signal Sin, so as to identify the identification code of the input signal Sin. Therefore, the identification code of the input signal Sin does not have to be detected by the signal detector  122  when the CRC16 code has not been received. In  FIG. 1 , the super I/O module  120 , the SPI flash memory  130 , the JTAG circuit  140  and the UART  150  can be implemented in different chips. However, in one embodiment, the circuits going to be controlled by simulator  170  and the super I/O module  120  can be implemented in the same chip. 
         [0022]    It is to be noted, after completing the control, debug, record or update process of the other circuits, the simulator  170  may provide the input signal Sin with an identification code ID 0  to the super I/O module  120  before that the simulator  170  is disconnected from the computer system  100  (or before communication between simulator  170  and computer system  100  is interrupt). Thus, the selector  124  is controlled to transmit the subsequent input signals from the I/O port  110  to the controller  126 , such that the mouse  160  and/or the keyboard  180  may operate normally after connecting to the computer system  100  again. 
         [0023]      FIG. 3  shows a control method for a computer system with a super I/O chip according to an embodiment of the invention. First, in step S 302 , an input signal Sin is received via an I/O port of the computer system (e.g.  110  of  FIG. 1 ). Next, in step S 304 , the input signal Sin is detected by a signal detector (e.g.  122  of  FIG. 1 ) within the super I/O chip, so as to determine whether the input signal Sin has a specific check code. If no, a selector (e.g.  124  of  FIG. 1 ) of the super I/O chip may directly transmit the input signal Sin to a pre-selected function circuit for subsequent processing (step S 306 ). On the contrary, if the input signal Sin has the specific check code, the signal detector of the super I/O chip may further identify an identification code of the input signal Sin (step S 308 ). Next, in the super I/O chip, the signal detector may control/switch the selector according to the identification code, such that the selector may transmit the input signal Sin to a function circuit corresponding to the identification code for subsequent processing (step S 310 ). 
         [0024]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.