Abstract:
Charge current in a charge pump of a phase locked loop is equalized by controlling one of the direct current sources with a feedback signal derived from the common mode voltage of a fully differential phase locked loop filter.

Description:
FIELD OF INVENTION  
       [0001]     This invention relates to the field of phase locked loops (PLLs), and in particular to a method of equalizing charge current in a charge pump of a phase locked loop including a pair of direct current sources.  
       BACKGROUND OF THE INVENTION  
       [0002]     A PLL typically employs a phase detector, loop filter, voltage controlled oscillator (VC)) and feedback loop to generate an output signal from a reference signal. When PLLs are integrated on CMOS integrated circuits with either an on-chip or off-chip loop filter, a fully differential control voltage of the voltage controlled oscillator VCO must be used to avoid noise injection. Otherwise unwanted spurs or degraded phase noise can occur.  
         [0003]     Generally, for simplicity, when an off-chip loop filter is used, use is made of a single ended control voltage. While a single-ended control voltage does not degrade performance when an off-chip loop filter is used, when an on chip loop filter is used or when minimized charge pump currents are required this approach cannot be employed.  
         [0004]     One possibility is to use a fully differential control voltage approach, as shown in  FIG. 1 , but this approach is not commonly used since the source and sink current sources used in the charge pump cannot be equal unless an automatic regulation system of common mode voltage control is used because the two current sources in a semiconductor device are never equal due to process variation and other inequalities.  
         [0005]     To avoid process variation, switched current sources are commonly used, as shown in  FIG. 2 . To ensure that the current sources always are saturated, i.e. turned on, two additional switches short the high impedance current sources to a low impedance voltage source that in the single output variant tracks the voltage at the output.  
       SUMMARY OF THE INVENTION  
       [0006]     According to the present invention there is provided a method of equalizing charge current in a charge pump of a phase locked loop including a pair of direct current source comprising providing a fully differential phase locked loop filter; and controlling one of said direct current sources with a feedback signal derived from a common mode voltage of said fully differential phase locked loop filter.  
         [0007]     The invention solves a problem related to the fact that two current sources in a semiconductor device are never equal due to process variation and other inequalities. The problem of unequal current sources prevents the use of a fully differential charge pump and loop filter since any difference in the sourcing and sinking current will force the fully differential loop filter, which floats with respect to a ground reference, towards either positive or negative supply, resulting in a degraded performance and higher noise sensitivity.  
         [0008]     In a preferred embodiment the invention consists of a phase/frequency detector with non overlapping control signal controlling a fully differential charge pump with active common mode control only connected across loop filter while charging is performed otherwise not. The arrangement does not degrade phase nose and spur performance of the VCO output as other charge pump and common mode control methods do.  
         [0009]     The invention relates especially to the control of error free charge injection into the loop filter and the control of common mode voltage of a fully differential, and with respect to ground or reference voltage, floating loop filter. The invention preferably uses a phase noise non degrading common mode control and switch control eliminating erroneous loop filter charge injection.  
         [0010]     In another aspect the present invention provides a phase locked loop comprising a phase detector; a fully differential loop filter; a charge pump with a pair of direct current sources for injecting charge into said fully differential filter; and a feedback loop for controlling one of said current sources with a feedback signal derived from a common mode voltage of said fully differential loop filter. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]     The invention will now be described in more detail, by way of example only, with reference to the accompanying drawings, in which:— 
         [0012]      FIG. 1  shows a prior art phase/frequency detector and fully differential output charge pump with switched current sources;  
         [0013]      FIG. 2  shows a prior art phase/frequency detector and single output charge pump with switched current sources;  
         [0014]      FIG. 3  shows a preferred embodiment of the invention including phase/frequency detector and fully differential output charge pump with non overlap switching current sources, and active, capacitive load only, common mode control.  
         [0015]      FIG. 4  shows a preferred embodiment of the invention including only the common mode voltage detector filter with buffered inputs and RC network filtered output; and  
         [0016]      FIG. 5  shows a preferred embodiment of the invention including only the current regulation loop. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0017]     In the drawings like parts are referenced with like reference numerals.  
         [0018]     Referring now to  FIG. 3 , a preferred embodiment of the inventive method to equalize the positive and the negative charge current sources of a PLL charge pump is shown.  
         [0019]     The embodiment comprises a phase detector  10  including a pair of up down counters  11 ,  17 , and a NAND gate  13 . A non-overlapping switch controller  19  controls switches  28 ,  29 ,  30 ,  31 ,  32 ,  33 . The purpose of the non-overlapping scheme is to prevent the fully differential loop filter  34  from being shorted during switching, which can cause erroneous charge injection. The loop filter  34  typically controls a voltage controlled oscillator (not shown).  
         [0020]     The PLL has a positive current source  20 , which is unregulated and constant. A negative current source  21  is placed in a sampled regulation loop  100  formed by a common mode voltage detector-filter  22 , a voltage subtractor  24 , an amplifier  25 , and a limiter  26 .  
         [0021]     The regulation loop  100  forces the value of the negative current source  21  such that the common mode voltage of the nodes vcp and vcn equals the common mode reference voltage vcm_ref generated by a voltage source  23 .  
         [0022]     The set of switches  28 - 33  performs the operation of switching the current sources either to one of vcp or vcn nodes or to a common node forced to a voltage equal to the common mode reference voltage by a buffer  27  depending on the output of the phase/frequency detector  10 .  
         [0023]     The purpose of the buffer  27  is to ensure that the current sources  20  and  21  always turn on to eliminate time dependent charging of the fully differential loop filter  34 .  
         [0024]     The switching operation forces the loop to be a sampled loop. This requires the current regulation loop bandwidth to be much lower than the sampling frequency defined by the frequency of the reference frequency signal. In practice this is not a significant limitation.  
         [0025]      FIG. 4  shows in more detail a preferred embodiment of the common mode voltage detector-filter  22 . Four high impedance input buffers  35 - 38 , with the gain of 1, isolate the nodes vcp and vcn from an RC filter network consisting of resistors  39 ,  40 ,  41 ,  42 ,  45 , and  46 , and capacitors  43 ,  44  that performs two tasks, namely: 
    a) Detecting the common mode voltage  
       vcm   =       (     vcp   +   vcn     )     2         
    b) low pass filtering the common mode voltage to remove any differential signal frequency content.      
         [0028]     In  FIG. 5  shows a detailed preferred embodiment of the current regulation loop. Here the reference voltage generator  23  is formed by a resistive divider  48  and  49  which feeds the reference voltage vcm_ref to an operational amplifier, in the following called opamp, configured as a voltage follower  75  and a transconductance operational amplifier  50 , hereafter referred to as OTA.  
         [0029]     The current regulation loop consists of the common mode voltage detector-filter  22 , comprising the preferred embodiment shown in  FIG. 4 , the OTA, a current limiter circuit  27  comprising four current sources  51 ,  52 ,  57  and  58  and four MOS devices  53 - 56 .  
         [0030]     Also included in the regulation loop are a current summation point  74  at which the nominal reference current of the negative current source I CPn     —     ref0  generated by PMOS device  61  and the regulation current I reg  are summed resulting in the regulated reference current I CPn     —     ref . The loop also includes MOS devices  60 , 62 ,  63 ,  64 ,  65   68 ,  69 ,  70 ,  71 , current source  66 , and voltage sources  59 ,  67 .  
         [0031]     The regulation loop is closed by the fact that ICPp and ICPn charge the fully differential loop filter  34  where the common mode voltage is detected and filtered by the above named common mode voltage detector-filter  22  from which the output is fed to the opposite input of the above named OTA.  
         [0032]     As noted above, in order to eliminate erroneous charging of the loop filter, the switch control signals controlling the current source switches are generated from the phase/frequency detector outputs, up and dwn by a non overlap scheme  19 .