Abstract:
A circuit to detect and record the occurrence of a surge in the supply voltage applied to an integrated circuit includes a detection circuit for providing a control signal if a voltage surge is detected. The circuit also includes a high voltage circuit, which produces a high programming voltage from the supply voltage if a voltage surge is detected, and a memory cell. The detection circuit may include a capacitor divider bridge, a voltage source, and a comparator. The circuit is particularly advantageous for use with electrically programmable memories.

Description:
FIELD OF THE INVENTION 
     The present invention relates to digital memory devices, and, more particularly, to electrically programmable non-volatile memories. 
     BACKGROUND OF THE INVENTION 
     In electrically programmable non-volatile memories, high voltages of about 10 to 20V are typically used to program or erase the memories. During programming or erasing, charge is stored or removed, respectively, from the floating gate of a floating gate transistor, which is the basic element of non-volatile memories. 
     External power supply circuits seldom provide such a high voltage. In particular, for embedded applications where the non-volatile memories are used in integrated circuits (e.g., smart cards), such a high voltage must necessarily be produced inside the memory. In most cases, this high voltage is provided by a low voltage supply using a voltage booster circuit of the charge pump type, for example. A charge pump typically includes capacitors, transistors and/or diodes. The charge pump is a fragile element in non-volatile memories. Indeed, the capacitors in such memories cannot withstand excessively high or long voltage surges in the power supply. 
     A non-volatile memory may undergo a voltage surge during use. That is, the low voltage supply of the memory may reach a value that is higher than a maximum value that the memory can withstand. A surge in the power supply voltage can damage or even destroy the charge pump of a memory and thus make it unusable. To limit the risks of destruction of the charge pump by excessively high power supply voltages, voltage limiter devices may be used. Voltage limiter devices limit the value of the supply voltage provided at the output of the charge pump. 
     Voltage limiters are not always sufficient to protect the memory because they may not limit the voltage at all points of the charge pump. A voltage surge may thus appear at a node of the charge pump without being visible at the output of the charge pump, and thus without being taken into account by the voltage limiter device. Moreover, the response time of voltage limiter devices is sometimes too long to avoid a surge in the supply voltage. 
     Accordingly, even with a voltage limiter device, a memory may still be subject to a voltage surge. As a result, manufacturers sometimes find that components coming off a production line are systematically rejected during a test procedure. To determine why the components have been rejected and to find a way to remedy this problem, it is often necessary to perform a complete analysis of the production line and, potentially, of the design of the product. This analysis may be very cumbersome if the cause of the problem is unknown. Similarly, users sometimes find that certain components wear out prematurely, and they are not able to easily ascertain the cause or a way to remedy it. 
     SUMMARY OF THE INVENTION 
     One object of the present invention is to provide a circuit to detect and record a voltage surge, particularly in electrically programmable non-volatile memories. 
     Another object of the present invention is to provide such a circuit that mitigates the above diagnostic difficulties. 
     These and other objects, features, and advantages are provided by a circuit for detecting and recording a voltage surge. The circuit includes a detection circuit to detect a voltage surge having a value higher than a maximum permissible value of a supply voltage provided by a power supply. The detection circuit provides a control signal if the voltage surge is detected. A high voltage circuit is also included to produce a high programming voltage from the power supply voltage, the high voltage circuit receiving the power supply voltage at a power supply input terminal and the control signal at an enabling input terminal. The circuit further includes a memory cell comprising an enabling input terminal to receive the control signal, a high voltage input terminal to receive the high voltage, and a low voltage input terminal to receive the power supply voltage. 
     The circuit may therefore be used to detect the occurrence of the voltage surge and then record this event in the memory cell, which is reserved for this purpose. The contents of the memory cell may also be read and used as an indicator, if necessary. The invention is well suited for non-volatile memories because suitable memory cells for use in the circuit are already available in such memories, making its implementation simple and inexpensive. Even so, the invention may also be used for other types of integrated circuits. 
     The detection circuit may include a capacitor divider bridge to provide a voltage that is proportional to the power supply voltage, a voltage source to provide a reference voltage, and a comparator receiving the voltage from the capacitor divider bridge at a first input terminal and the reference voltage at a second input terminal. The capacitor divider bridge may include two series-connected capacitors. Very little power is consumed in such an embodiment, making it particularly advantageous in applications such as integrated circuits for smart cards. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be understood more clearly, and further characteristics and advantages will be understood, from the following description made with reference to the appended figures. 
     FIG. 1 is a schematic diagram of a circuit for detecting and recording a voltage surge according to the invention. 
     FIG. 2 is a schematic diagram of an alternative embodiment of one element of the circuit of FIG.  1 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Turning now to FIG. 1, a circuit for detecting and recording a voltage surge is now described. The circuit includes a detection circuit  13 , a high voltage circuit  11 , and a memory cell  12 . The detection circuit  13  includes a capacitor divider bridge  10 , a voltage source  14 , and a comparator Comp. The capacitor divider bridge  10  has an input terminal  20  connected to a power supply source providing a power supply voltage V cc , and an output terminal  21  connected to an input terminal  22  (illustratively a positive (+) terminal) of the comparator Comp. 
     The capacitor divider bridge  10  may include two series-connected capacitors C 1 , C 2 . One of the terminals of the capacitor C 1  is connected to the input terminal  20 , and one of the terminals of the capacitor C 2  is connected to ground. A common point of the capacitors C 1 , C 2  is connected to the output terminal  21 . The potential at output terminal  21  is a value V 2 , where V 2 =V cc *C 1 /(C 1 +C 2 ), and the voltage V 2  is proportional to the power supply voltage V cc . 
     The voltage source  14  provides a reference voltage V ref  that is applied to an input terminal  23  (illustratively a negative (−) terminal) of the comparator Comp. The voltage source  14  may be obtained, for example, by using one or more Zener diodes, or by using one or more bipolar transistors. The latter structure is known as a “Bandgap Voltage Reference.” A reference voltage source of this kind should be temperature stable. 
     An output terminal  24  of the comparator Comp is connected to the output of the detection circuit  13 . The output of the comparator Comp is a steady state signal when the voltage V 2  is higher than the reference voltage V ref . A high voltage circuit  11  includes a power supply input terminal E connected to the power supply source, an enabling input terminal Val connected to the output terminal  24  of the detection circuit  13 , and an output terminal S that provides a high voltage HT to the memory cell  12 . 
     The memory cell  12  includes an enabling input terminal e 1  connected to the output terminal  24  of the detection circuit  13 , a high voltage input terminal e 2  connected to the output terminal S of the high voltage circuit  11 , and a low voltage input terminal e 3  connected to the power supply source. The enabling input terminal e 1  is connected to the gate of a selection transistor T 1  having a drain connected to the low voltage input terminal e 3 . A source of the selection transistor T 1  is connected to a drain of a floating gate storage transistor T 2  by a transistor T 3 , whose drain is connected to its gate to form a diode. A gate of the storage transistor T 2  is connected to the high voltage input terminal e 2  and its source is connected to ground. 
     The above circuit for detecting and recording a voltage surge works as follows. To avoid damaging the detection and recording circuit, the supply voltage V cc  should not exceed an acceptable maximum value V ccmax . For example, for a circuit whose normal supply voltage V cc  is about 5V, an acceptable maximum value V ccmax  is about 8V. A voltage source  14  made with band gap voltage reference bipolar transistors gives a reference voltage V ref  of about 1.2V. The two capacitors C 1 , C 2  are adjusted so that the supply voltage V ccmax  has a corresponding voltage V 2max , where V 2max =V ccmax *C 1 /(C 1 +C 2 )=V ref . 
     In normal operation, the supply voltage V cc  is lower than its acceptable maximum value V ccmax . The voltage V 2  is thus lower than the reference voltage V ref , and the comparator Comp provides zero voltage at the output  24  of the detection circuit  13 . Since the enabling input terminal Val of the high voltage circuit  11  receives a zero voltage, the high voltage circuit  11  is inactive and provides zero voltage at its output terminal S. 
     Because the memory cell  12  receives zero voltage at its enabling input terminal e 1  and zero voltage at its high voltage input terminal e 2 , the three transistors T 1 , T 2 , T 3  that form the memory cell are off and no information is recorded in the memory cell  12 . If during operation the supply voltage V cc  takes a value higher than its acceptable maximum value V ccmax , the voltage V 2  becomes greater than the reference voltage V ref . Then, at the output terminal  24  of the detection circuit  13 , the comparator Comp provides a positive voltage (for example, V cc ). 
     Since the enabling input terminal Val of the high voltage circuit  11  receives a positive voltage, the high voltage circuit  11  is activated and provides a high voltage HT of sufficient amplitude (i.e., approximately 10 to 20V) to program the memory cell  12  at its output terminal S. The memory cell  12  receives a positive voltage at its enabling input terminal e 1 , a high voltage HT at its high voltage input terminal e 2 , and a supply voltage V cc  at its low voltage input terminal e 3 , resulting in the three transistors T 1 , T 2 , T 3  being saturated and information being recorded in the memory cell  12 . 
     Numerous alternative embodiments of the circuit of FIG. 1 for detecting and recording a voltage surge may be used without departing from the scope of the present invention. For example, the transistor T 3  may be replaced by a diode. Further, the transistor T 3  may be eliminated, as it is needed only to limit the voltage applied to the drain of the storage transistor T 2 , especially for read operations. Indeed, in FLASH EEPROM type memories, for example, a voltage of 2 to 3V applied to the drain of the storage transistor T 2  is enough for its contents to be read. If the supply voltage V cc  is repeatedly applied to the drain of the storage transistor T 2 , there is a long term risk of damaging the transistor by causing a shift in its threshold voltage. 
     Other detection circuits  13  may also be used. Referring to FIG. 2, a second possible embodiment of the detection circuit  13  is shown which comprises n transistors Tr 1  to Tr n , a voltage source  14 , a transistor T 4 , and two inverters I 1 , I 2 . The gate and the drain of each transistor Tr 1  to Tr n  are connected together to make diodes. The drain of the transistor Tr 1  is connected to the power supply source, which provides the supply voltage V cc . The drain of each transistor Tr 2  to Tr n  is connected to the source of the transistors Tr 1  to Tr n−1 , respectively. The source of the transistor Tr n  is connected to the drain of the transistor T 4 , and the source of the transistor T 4  is connected to ground. 
     The voltage source  14  provides a reference voltage V ref  that is applied to the gate of the transistor T 4 . The two inverters I 1 , I 2 , each including an input terminal and an output terminal, are series-connected. An input terminal  25  of the inverter I 1  is connected to the drain of the transistor T 4  and is at the potential V 2 =V cc −n*V T , where V T  is the threshold voltage of the n transistors. The output terminal of the inverter I 2  is connected to the output terminal  24  of the detection circuit  13 . At its output terminal, the inverter I 2  provides a steady state signal equal to logic “1” when the voltage V 2  is higher than the reference voltage V ref . One potential disadvantage of the detection circuit of FIG. 2 is that it consumes more energy than the detection circuit of FIG.  1 . 
     According to another embodiment, the configuration of FIG. 1 may be modified to include a register  26  and a capacitor  27 , both of which are illustrated with dotted lines. The register  26  is connected between the output of the detection circuit  13  and the memory cell  12 . The register  26  has an input terminal connected to the output terminal  24  of the detection circuit  13  and an output terminal connected to the enabling input terminal e 1  of the memory cell  12 . The register  26  records the occurrence of a short-duration surge in the supply voltage V cc , which is done for a period of time long enough for the memory cell  12  to be completely programmed. 
     The capacitor  27  is connected between the power supply voltage V cc  and ground. In normal operation, the capacitor  27  stores power. In the event the power supply voltage V cc  drops after the occurrence of a surge in the supply voltage V cc , the capacitor  27  provides a power reserve to program the memory cell  12 . This is a valuable improvement but requires the use of a capacitor having a high capacitance, for example, of about 300 pF. 
     The voltage surge detection and recording circuit according to the invention may be used to detect a surge in the supply voltage of a non-volatile memory, such as an EPROM, EEPROM, or Flash EEPROM, for example.