Abstract:
A semiconductor memory device of the SRAM type includes a memory cell including a pair of inverters each having a resistor and a driving transistor connected in series forming a storage node at the junction point thereof. Switching transistors in the memory cell are respectively connected between the storage nodes and bit lines. A film thickness of a gate oxide film of each of the switching transistors (transfer MOS transistors) is larger than a film thickness of a gate oxide film of each of the driving transistors (driver MOS transistors).

Description:
BACKGROUND OF THE INVENTION 
     1. Field on the Invention 
     The present invention relates to a semiconductor memory device, and in particular, to a semiconductor memory device including a SRAM (static random access memory). 
     2. Description of the Prior Art 
     Semiconductor memory devices include volatile memories which can retain information only when power is being turned on, and nonvolatile memories which can retain information even when power is turned off. The volatile memories include a SRAM (static random access memory) and a DRAM (dynamic RAM), and the nonvolatile memories include a mask ROM (mask read only memory), a PROM (programmable ROM), an EPROM (erasable programmable ROM), and an EEPROM (electrically erasable and programmable ROM), and the like. 
     Among the volatile memories, the SRAM is frequently used in super computers and central portions of many computers, and in office automation equipment, and the like, because the timing of memory operation of the SRAM is easily achieved, no complicated refresh control is required thereby to facilitate the usage, and also the high speed operation is easily attained. 
     This SRAM has a structure, for example, as shown in FIG. 11, including switching transistors Q 1  and Q 4 , driving transistors Q 2  and Q 3 , and resistors R 1  and R 2 . An inverter is formed by the driving transistor Q 2  and the resistor R 1 , and another inverter is formed by the driving transistor Q 3  and the resistor R 2 , and in these two inverters, the output of one inverter is an input of the other inverter, and vice versa. A storage node N 1  at the junction point between the driving transistor Q 2  and the resistor R 1 , and a storage node N 2  at the junction point between the driving transistor Q 3  and the resistor R 2  are respectively connected to bit lines 200 through respective switching transistors Q 1  and Q 4 . The gates of the switching transistors Q 1  and Q 4  are connected to a word line 100. Furthermore, the switching transistors Q 1  and the driving transistor Q 2  form another inverter (hereinafter referred to as a Q 1  -Q 2  inverter), and the driving transistor Q 3  and the switching transistors Q 4  form still another inverter (hereinafter referred to as a Q 3  -Q 4  inverter). 
     In this SRAM, a high potential of the storage nodes N 1  and N 2  corresponds to a logic &#34;1&#34;, and a low potential of the storage nodes N 1  and N 2  corresponds to a logic &#34;0&#34;. Specifically, when the storage nodes N 1  is applied with a high potential, the driving transistor Q 3  is turned on to make the storage node N 2  to assume a low potential, and the driving transistor Q 2  is turned off to hold the storage modes N 1  at the high potential. Conversely, when the storage modes N 1  is applied with a low potential, the storage node N 2  is maintained at a high potential in a similar manner. This state is maintained as far as the power supply voltage is supplied, and as far as the potentials of the storage nodes N 1  and N 2  are not changed externally. 
     In the SRAM shown in FIG. 11, supposing that a certain memory cell (i-th row and j-th column) is designated. Here, when the word line 100 and a column selection line 300 are applied with a high voltage, since the switching transistors Q 1 , Q 4 , Q 5 , and Q 6  are turned on, potentials of the storage nodes N 1  and N 2  are read out, or data is written into the storage nodes N 1  and N 2  through a common bit line 400. In FIG. 11, although the resistors R 1  and R 2  are intended to represent load members, these resistors may be replaced by load transistors. 
     In the above-mentioned SRAM, it is important to design the memory cell so that it operates stably against non-uniformity of pattern shapes of elements and noise margin. 
     FIG. 12 shows an input/output characteristic of the Q 1  -Q 2  inverter and an input/output characteristic of the Q 3  -Q 4  inverter with respect to potentials of the storage nodes N 1  and N 2  just after rewriting of the memory cell (at the time when the switching transistors are in a turned-on state). As shown in FIG. 12, an output potential of the Q 3  -Q 4  inverter with respect to an input signal potential V 1  which is larger than a potential V T  is represented by V 2 , and when this potential V 2  is inputted to the Q 1  -Q 2  inverter, its output potential is represented by V 3 . From this, it will be seen that the output potential of the Q 1  -Q 2  inverter approaches a point A. Conversely, when a potential smaller than the potential V T  is inputted to the Q 3  -Q 4  inverter, the output potential of the Q 1  -Q 2  inverter will approach a point D. As shown here, the potential V T  is a boundary of logics &#34;0&#34; and &#34;1&#34;  for the output of the storage node N 1 , and represents a threshold value voltage. In this respect, points A to D represent the following states. 
     Point A: writing when the storage node N 1  is logic &#34;1&#34;. 
     Point B: reading out when the storage node N 1  is logic &#34;1&#34;. 
     Point C: reading out when the storage node N 1  is logic &#34;0&#34;. 
     Point D: writing when the storage node N 1  is logic &#34;0&#34;. 
     It has been known that the memory cell can be operated more stably when the area of a hatched portion formed by the input/output characteristic curve of the Q 1  -Q 2  inverter and the input/output characteristic curve of the Q 3  -Q 4  inverter becomes larger. In order to increase the area of the hatched portion, it is necessary to increase a β ratio of the switching transistors Q 1  and Q 4  to the driving transistors Q 2  and Q 3  as far as possible. In this respect, β and the β ratio is obtained from the following equations. ##EQU1## 
     Where, μ N  is the carrier mobility, C ox  is the gate capacitance, W eff  is the effective channel width, L eff  is the effective channel length, β S  is of the switching transistor, and β D  is β of the driving transistor. 
     Normally, it is known that a value of the β ratio is suitably about 2.5 to 5. From the equation (1), it is seen that in order to increase the β ratio as far as possible, β D  may be increased as far as possible as compared with β S . In order to increase β D , it is required to increase the effective channel width of the driving transistor. As a result, the size of the driving transistor is made necessarily large. Accordingly, it becomes impossible to manufacture the driving transistor with a minimum size, and thus there is a problem in that the high integration of a semiconductor memory device is disturbed. 
     Furthermore, Japanese Patent Laid-Open Publication No. 62-230058 discloses a non-volatile semiconductor memory device including a SRAM and an EEPROM connected to each other. In this semiconductor memory device, the miniaturization and the high integration of the driving transistor are achieved by reducing a film thickness of a gate insulation film of the SRAM to the same thickness as the tunnel insulation film of EEPROM and reducing a resistance value thereby to reduce the area of the driving transistor. However, this prior art example relates to a semiconductor memory device having both the SRAM and the EEPROM, and it is not related to the SRAMs and logic LSI including SRAMs. 
     SUMMARY OF THE INVENTION 
     The present invention is aimed to solve the problems mentioned above, and it is an object of the invention to provide a semiconductor memory device improved in the stability in a writing and reading operation without disturbing the high integration, and irrespective of nonuniformity of pattern shapes of elements and irrespective of noise margin or the like. 
     In order to achieve the object in the present invention, a semiconductor memory device comprises a memory cell. The memory cell includes a pair of inverters each having a load member and a driving transistor, an output of one inverter being connected to an input of the other inverter, an output of the other inverter being connected to an input of one inverter, and switching transistors respectively connecting storage nodes of the pair of inverters to bit lines, gates of the switching transistors being connected to a word line. The improvement in the semiconductor memory device resides in that a film thickness of an insulating film such as a gate oxide film of each of the switching transistors is thicker than a film thickness of a gate oxide film of each of the driving transistors of the inverters. 
     It is another object of the invention to provide a semiconductor memory device in which the film thickness of the gate oxide film of each of the driving transistors is equal to a film thickness of a gate oxide film of all transistors having a metal-oxide-semiconductor (hereinafter, referred to as &#34;MOS&#34;) structure in a peripheral circuit. 
     It is still another object of the invention to provide a semiconductor memory device in which the film thickness of the gate oxide film of each of the switching transistors is equal to a film thickness of a gate oxide film of all transistors having the MOS structure in the peripheral circuit. 
     It is still another object of the invention to provide a semiconductor memory device in which the film thickness of the gate oxide film of each of the switching transistors is equal to a film thickness of a gate oxide film of a part of the transistors having the MOS structure in the peripheral circuit, and the film thickness of the gate oxide film of each of the driving transistors is equal to a film thickness of a gate oxide film of the rest of the transistors having the MOS structure in the peripheral circuit. 
     It is still another object of the invention to provide a semiconductor memory device in which a relationship between the film thickness of the gate oxide film of the switching transistor and the film thickness of the gate oxide film of the driving transistor is such that the film thickness of the gate oxide film of the driving transistor:the film thickness of the gate oxide film of the switching transistor=10:11 to 10:20. 
     It is still another object of the invention to provide a semiconductor memory device in which a relationship between the film thickness of the gate oxide film of the switching transistor and the film thickness of the gate oxide film of the driving transistor is such that, preferably the film thickness of the gate oxide film of the driving transistor:the film thickness of the gate oxide film of the switching transistor=10:12 to 10:15. 
     It is still another object of the invention to provide a semiconductor memory device comprising a memory cell including a pair of inverters each having a load member and a driving transistor, an output of one inverter being connected to an input of the other inverter, an output of the other inverter being connected to an input of one inverter, and switching transistors respectively connecting storage nodes of the pair of inverters to bit lines, gates of the switching transistors being connected to a word line. The improvement in semiconductor memory device resides in that a dielectric constant of a gate oxide film of each of the driving transistors is larger than a dielectric constant of a gate oxide film of each of the switching transistors of the inverters. 
     In one aspect of the present invention, from the above-mentioned equation (1), in order to make the β ratio larger as far as possible, it is required to make β S  (β of the switching transistor) smaller than β D  (β of the driving transistor). To attain this, there is a method of extending the gate length of the switching transistor (which serves also as a word line), or reducing the gate capacitance C ox . 
     When the gate length is extended, a memory area is increased by an amount corresponding to a widened word line width. On the other hand, in the method of reducing the gate capacitance C ox , it is possible to reduce β S  without increasing the gate length. In addition, since the word line capacitance can also be reduced, it is effective and suitable in a high speed operation. 
     In this respect, the gate capacitance Cox is expressed by the following equation (2). ##EQU2## where, T ox  is the oxide film thickness, ε ox  is the relative permittivity of the oxide film, and ε o  is the permittivity (8.9×10 -12  F/m) in a free space. 
     From the equation (2), it will be seen that when T ox  is reduced, that is, when the film thickness of the gate oxide film of the driving transistor is reduced, the gate capacitance C ox  will be increased. 
     Accordingly, when the film thickness of the gate oxide film of the switching transistor is made thicker than the film thickness of the gate oxide film of the driving transistor, it is possible to increase the β ratio. 
     In another aspect of the present invention, since the film thickness of the gate oxide film of the driving transistor is made equal to the film thickness of the gate oxide film of all the MOS transistors in the peripheral circuit, it is possible, in addition to the above-mentioned technical effect, to increase the driving capability of the MOS transistors in the peripheral circuit. Accordingly, the high speed operation of the overall SRAM device can be attained. 
     In still another aspect of the present invention, since the film thickness of the gate oxide film of the switching transistor is made equal to the film thickness of the gate oxide film of all the MOS transistors in the peripheral circuit, it is possible, as a result of this, to reduce the thickness of only the gate oxide film of the driving transistors of the SRAM. Accordingly, it is possible to increase the β ratio of the memory cell without reducing the hot carrier resistive property of the peripheral circuit. Therefore, it is possible to obtain the SRAM which is improved in the reliability and stability. 
     In still another aspect of the present invention, since the film thickness of the gate oxide film of each of the switching transistors is equal to a film thickness of a gate oxide film of a part of the transistors having the MOS structure in the peripheral circuit, and the film thickness of the gate oxide film of each of the driving transistors is equal to a film thickness of a gate oxide film of the rest of the transistors having the MOS structure in the peripheral circuit, it is possible to obtain, in addition to the above-mentioned technical effect, the SRAM which is improved in the reliability and stability. Specifically, the gate oxide film of a circuit (for example, transfer gate, sense amplifier gate, and like) of which hot carrier deterioration appears to be relatively large in the peripheral circuit is made thick, and the gate oxide film of the other portion is made thin, thereby to obtain the SRAM which is improved in the reliability and the stability. 
     In still another aspect of the present invention, since it is arranged such that the film thickness of the gate oxide film of the driving transistor:the film thickness of the gate oxide film of the switching transistor=10:11 to 10:20, it is possible to obtain the SRAM which is improved in the reliability and the stability. 
     In still another aspect of the present invention, since it is arranged such that the film thickness of the gate oxide film of the driving transistor:the film thickness of the gate oxide film of the switching transistor=10:12 to 10:15, it is possible to obtain the SRAM which is improved in the reliability and the stability. 
     In still another aspect of the present invention, since the dielectric constant of a gate oxide film of each of the driving transistors is larger than the dielectric constant of a gate oxide film of each of the switching transistors of the inverters, in accordance with the equations (1) and (2), it is possible to increase the gate capacitance C ox , and thereby to increase the β ratio. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a partial sectional view of a semiconductor memory device illustrating a manufacturing process thereof in an embodiment of the present invention. 
     FIG. 2 is a partial sectional view of a semiconductor memory device illustrating a manufacturing process thereof in the embodiment of the present invention. 
     FIG. 3 is a partial sectional view of a semiconductor memory device illustrating a manufacturing process thereof in the embodiment of the present invention. 
     FIG. 4 is a partial sectional view of a semiconductor memory device illustrating a manufacturing process thereof in the embodiment of the present invention. 
     FIG. 5 is a partial sectional view of a semiconductor memory device illustrating a manufacturing process thereof in the embodiment of the present invention. 
     FIG. 6 is a partial sectional view of a semiconductor memory device illustrating a manufacturing process thereof in the embodiment of the present invention. 
     FIG. 7 is a partial sectional view of a semiconductor memory device illustrating a manufacturing process thereof in the embodiment of the present invention. 
     FIG. 8 is a partial sectional view of a semiconductor memory device illustrating a manufacturing process thereof in the embodiment of the present invention. 
     FIG. 9 is a partial sectional view of a semiconductor memory device illustrating a manufacturing process thereof in the embodiment of the present invention. 
     FIG. 10 is a partial sectional view of a semiconductor memory device illustrating a manufacturing process thereof in the embodiment of the present invention. 
     FIG. 11 shows a circuit diagram of an SRAM. 
     FIG. 12 is a diagram showing an input/output characteristic of a Q 1  -Q 2  inverter and an input/output characteristic of a Q 3  -Q 4  inverter with respect to potentials of storage nodes N 1  and N 2  just after rewriting of the circuit shown in FIG. 11. 
     FIG. 13 is a layout diagram of a SRAM in another embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Embodiments of the present invention will be described with reference to the drawings. 
     FIGS. 1 to 10 are partial sectional views illustrating manufacturing processes of a semiconductor memory device of the present invention. The semiconductor memory device includes on the same substrate, driver MOS transistors (corresponding to driving transistors) and transfer MOS transistors (corresponding to switching transistors) and MOS transistors in the peripheral circuit. In this respect, FIGS. 1 to 10 show a memory cell and a part of a peripheral circuit of the semiconductor memory device. 
     In a process shown in FIG. 1, after forming a P well 20 and an N well (not show) in an N-type silicon substrate 1 by a well-known technique, a thin oxide film is formed on the N-type silicon substrate 1, and a nitride film is further formed on the thin oxide film. Thereafter, the nitride film in an active region (to-be-formed transistor region) is selectively left, and the nitride film of the other portion is removed. Subsequently, channel stopper ions are ion implanted selectively in a non-active region of the N-type silicon substrate 1 to form a channel stopper 3. Then, an oxide film 2 having a thickness of 600 nm is formed in the non-active region by thermal oxidation thereby to separate elements from each other. Subsequently, the oxide film in the active region is removed, a gate oxide film 4 having a thickness of 15 nm is formed anew in the active region, and boron (B) for adjusting a threshold value is ion implanted in a channel region. Thereafter, a part (a portion in which the gate of the driver MOS transistor 5 contacts with the substrate 1 in a later process) of the gate oxide film 4 in a transfer MOS transistor region is selectively removed, and the N-type silicon substrate 1 in this part is exposed. 
     Subsequently, in a process shown in FIG. 2, a polysilicon film 5 having a thickness of 200 nm is formed by a CVD (chemical vapor deposition) technique in an atmosphere of 620° C. over the whole surface of the N-type silicon substrate 1 obtained in the process shown in FIG. 1, and then, phosphorous (P) is doped in the polysilicon film 5 by using POCL 3 , thereby to decrease a resistance of the polysilicon film 5. At this time, in the portion from which the gate oxide film 4 is removed in the process shown in FIG. phosphorous 21 is diffused. Next, a silicon oxide film 6 of 250 nm in thickness is formed over the whole surface of the N-type silicon substrate 1 by the CVD technique in an atmosphere of 430° C. 
     In a process shown in FIG. 3, the silicon oxide film 6 is selectively removed by anisotropy dry etching excepting a portion which is to be a gate region of a driver MOS transistor, and the remaining portion of the silicon oxide film 6 is used as a mask to remove the polysilicon film 5 and the gate oxide film 4 by dry etching. In the process, the gate oxide film (thickness of 15 nm) of the driver MOS transistor has been formed. Thereafter, a silicon oxide film 200 nm in thickness is formed over the whole surface of the N-type silicon substrate 1 by the CVD technique in an atmosphere of 430° C., and this film is etched back to form a spacer 7 on a side surface of a gate of the driver MOS transistor thereby to complete the gate of the driver MOS transistor. 
     In a process shown in FIG. 4, phosphorous having a relatively high concentration is ion implanted selectively in the to-be-formed drain 22, 23 regions in the N-type silicon substrate 1 obtained in the process shown in FIG. 3, and subsequently, arsenic having a high concentration is ion implanted to form the drains 22, 23. Thereafter, a gate oxide film 8 having a thickness of 18 nm is formed on the exposed portion of the N-type silicon substrate 1. In this process, the gate oxide film 8 (18 nm in thickness) of the transfer MOS transistor has been formed. In this respect, the film thickness of the gate oxide film 8 is made thicker than the film thickness of the gate oxide film 4 of the drive MOS transistor which is formed in the previous process. 
     In a process shown in FIG. 5, a polysilicon film 9 having a thickness of 100 nm is formed by the CVD technique in an atmosphere of 620° C. over the whole surface of the N-type silicon substrate 1, and subsequently, phosphorous is doped in the polysilicon film 9 by using POCL 3 , thereby to decrease the resistance of the polysilicon film 9. Next, after forming a tungsten silicide film 10 having a thickness of 120 nm by the CVD technique, a silicon film 11 having a thickness of 100 nm is formed by the CVD technique in an atmosphere of 430° C. 
     In a process shown in FIG. 6, the silicon film 11 is selectively removed by the anisotropical dry etching with the exception of the to-be-formed gate region of the transfer MOS transistor and the to-be-formed gate region of the peripheral circuit, and the remaining silicon film 11 is used as a mask to remove the tungsten silicide film 10, polysilicon film 9 and the gate oxide film 8 by dry etching. At this time, the gate of the driver MOS transistor is protected by the silicon oxide film 6. 
     In a process shown in FIG. 7, phosphorous having a relatively low concentration is ion implanted in the whole surface of the N-type silicon substrate 1 obtained in the process shown in FIG. 6. At this time, each gate formed in the previous process serves as a mask. Thereafter, a silicon oxide film 300 nm in thickness is formed by the CVD technique in an atmosphere of 430° C. over the whole surface of the N-type silicon substrate 1, and spacers 12 are formed on side surfaces of all the gates by etching back. Thereafter, an oxide film having a thickness of 5 nm is formed on exposed portions of the N-type silicon substrate 1 by thermal oxidation, and then arsenic is ion implanted in this portions to form a source and a drain. 
     In a process shown in FIG. 8, after forming a silicon oxide film 13 having a thickness of 100 nm by the CVD technique in an atmosphere of 430° C. over the whole surface of the N-type silicon substrate 1 obtained in the process shown in FIG. 7, the silicon oxide film 13 is selectively etched to open a contact hole to the driver MOS transistor. Next, a polysilicon film 14 having a thickness of 100 nm is formed by the CVD technique in an atmosphere of 580° C. over the whole surface of the N-type silicon substrate 1. Thereafter, a wiring and high resistor pattern is formed selectively on the polysilicon film 14, and the polysilicon film 14 is removed leaving the wiring and high resistor portion. Then, arsenic is ion implanted selectively into the polysilicon film 14 of the wiring portion. 
     In a process shown in FIG. 9, after forming a silicon oxide film 15 having a thickness of 100 nm by the CVD technique in an atmosphere of 430° C. over the whole surface of the N-type silicon substrate obtained in the process shown in FIG. 8, a BPSG (boron-phoso-silicate glass) film 300 nm in thickness is formed by the CVD technique in an atmosphere of 430° C. 
     In a process shown in FIG. 10, after smoothing by a heat treatment the surface of the N-type silicon substrate 1 obtained in the process shown in FIG. 9, a contact hole for connecting a metal wiring 17 which is formed later the the N-type silicon substrate 1, and a contact hole for connecting the metal wiring 17 to the gate are opened. Subsequently, a metal wiring layer of an aluminum alloy is formed by sputtering over the whole surface of the N-type silicon substrate 1, and the desired metal wiring 17 is formed by patterning the metal wiring layer. Thereafter, an oxide film 18 is deposited by a plasma CVD technique, and a resist is coated on the oxide film 18. Then, the oxide film 18 is smoothed by etching back with a gas ratio having the same etching rate as the resist and the oxide film 18. 
     Thereafter, if desired, a contact hole is opened, and other wirings are formed, thereby to form a multilayer wiring, and to complete the semiconductor memory device. 
     In this manner, the semiconductor memory device having a structure in which the film thickness of the gate oxide film 8 of the transfer MOS transistor is thicker than the film thickness of the gate oxide film 4 of the driver MOS transistor is obtained. 
     In this embodiment, although the thickness of the gate oxide film 4 of the driver MOS transistor is made 15 nm, and the thickness of the gate oxide film 8 of the transfer MOS transistor is made 18 nm, the present invention is not limited to this, and it is preferable to satisfy the following relationship in which the thickness of the gate oxide film 4 of the driver MOS transistor:the thickness of the gate oxide film 8 of the transfer MOS transistor=10:11 to 10:20, or preferably 10:12 to 10:15. 
     Furthermore, in the embodiment, although the thickness of the gate oxide film 4 of the driver MOS transistor is made thinner than the thickness of other gate oxide films, the present invention is not limited to this, and only the thickness of the gate oxide film 8 of the transfer MOS transistor may be made thicker than other gate oxide films. And by doing so, it is possible to increase the driving capability of the MOS transistors in the peripheral circuit, and to achieve high speed operation of the overall semiconductor memory device. 
     Furthermore, the thickness of the gate oxide film of the transfer MOS transistor may be made equal to the thickness of the gate oxide film of a part of the MOS transistors in the peripheral circuit, and the thickness of the gate oxide film of the driver MOS transistor may be made equal to the thickness of the gate oxide film of the rest of the driver MOS transistors in the peripheral circuit. And by doing so, in the peripheral circuit, the gate oxide film of a circuit (for example, transfer gate, sense amplifier gate, and the like) of which hot carrier deterioration appears to be large is made thick and the gate oxide film of the other part is made thin, thereby to provide the semiconductor memory device in which the reliability and the stability are improved. 
     Next, another embodiment of the present invention will be described. 
     FIG. 13 is a layout diagram of a semiconductor memory device (SRAM) processes by processes similar to that described in the foregoing. In FIG. 13, black portions represent gates of transfer MOS transistors and gates of driver MOS transistors. 
     The cell size of a SRAM which uses 0.5 μm design rule is 5.45×3.5=19.075 (μm 2 ), the β  ratio=2.5. Furthermore, in a driver MOS transistor of this SRAM, a gate width (W eff )=1.25 μm. 
     In this SRAM, only the film thickness of the gate oxide film of the transfer MOS transistor is made 15 nm, and the film thickness of the gate oxide film of the transfer MOS transistor is formed thicker than the film thickness of the gate oxide film of 11 nm of the driver MOS transistor. When this condition is introduced into the equations (1) and (2), the following numerical values are obtained in which in the transfer MOS transistor, the gate width (W eff )=0.917 μm, the cell size=5.15×3.5=18.025 (μm 2 ), and the cell size can be reduced by about 5%. From this, by making the film thickness of the gate oxide film of the transfer MOS transistor thicker than the film thickness of the gate oxide film of the driver MOS transistor, it is confirmed that the miniaturization and the high integration of the driver MOS transistor can be achieved. 
     Furthermore, as regards the hot carrier characteristics, in the SRAM, the transfer MOS transistor is weaker than the driver MOS transistor. Accordingly, by making the film thickness of the gate oxide film of the transfer MOS transistor thicker than the film thickness of the gate oxide film of the driver MOS transistor, it is possible to relatively improve the hot carrier resistive property. 
     In the embodiment, the β ratio is increased in view of the relationship between the film thickness of the gate oxide film of the transfer MOS transistor and the film thickness of the gate oxide film of the driver MOS transistor. However, the present invention is not limited to this, and the β ratio may be increased, for example, by forming the gate oxide film of the driver MOS transistor with an oxide film having a high dielectric constant such as tantalum oxide or the like so that the dielectric constant of the gate oxide film of the driver MOS transistor is made larger than the dielectric constant of the gate oxide film of the transfer MOS transistor, thereby to increase the gate capacitance C ox  of the driver MOS transistor. 
     Furthermore, in the embodiment, although an example of the manufacturing processes of the semiconductor memory device is described, the manufacturing method is not limited to this, and other manufacturing methods may be employed as far as it is possible to obtain a semiconductor memory device having a structure in which a film thickness of the gate oxide film of the switching transistor (transfer MOS transistor) is thicker than a film thickness of the gate oxide film of the driving transistor (driver MOS transistor). 
     It is apparent that the present invention is applicable to various types of SRAMs including an E/D type (a combination of a transistor (E type) applied with an input voltage and a transistor (D type) connected in series), a high resistance load type, a CMOS (complementary MOS), etc., to obtain similar technical effects. 
     As described in the foregoing, in the present invention, the following advantages are provided. 
     In one aspect of the invention, since the film thickness of the gate oxide film of the switching transistor is made thicker than the film thickness of the gate oxide film of the driving transistor of the memory cell, the gate capacitance of the switching transistor can be made smaller than the gate capacitance of the driving transistor. Accordingly, since β of the driving transistor can be made larger than β of the switching transistor without increasing the size of the semiconductor memory device, it is possible to increase the β ratio. As a result, the stability of a writing and reading operation of the semiconductor memory device is improved without disturbing the high integration, and irrespective of the non-uniformity of the pattern shapes of elements, and noise margin, or the like. 
     In another aspect of the invention, since the film thickness of the gate oxide film of the driving transistor is made equal to the film thickness of the gate oxide film of all the MOS transistors in the peripheral circuit, in addition to the above-mentioned advantage, the driving capability of the MOS transistor in the peripheral circuit can be increased. As a result, it is possible to achieve high speed operation of the overall semiconductor memory device. 
     In still another aspect of the invention, since the film thickness of the gate oxide film of the switching transistor is made equal to the film thickness of the gate oxide film of all the MOS transistors in the peripheral circuit, the β ratio of the memory cell can be increased without degrading the hot carrier resistive property of the peripheral circuit. As a result, in addition to the above-mentioned advantage, the reliability and the stability of the semiconductor memory device can be improved. 
     In still another aspect of the invention, since the film thickness of the gate oxide film of the switching transistor is made equal to the film thickness of the gate oxide film of a part of the MOS transistors in the peripheral circuit, and the film thickness of the gate oxide film of the driving transistor is made equal to the film thickness of the gate oxide film of the rest of the MOS transistors in the peripheral circuit, in addition to the above-mentioned advantage, the reliability and the stability of the semiconductor memory device can be improved. 
     In still another aspect of the invention, since the following relationship between the film thicknesses is adopted such that the film thickness of the gate oxide film of the driving transistor:the film thickness of the gate oxide film of the switching transistor=10:11 to 10:20, in addition to the above-mentioned advantage, the reliability and the stability of the semiconductor memory device can be improved. 
     In still another aspect of the invention, since the following relationship between the film thicknesses is adopted such that the film thickness of the gate oxide film of the driving transistor:the film thickness of the gate oxide film of the switching transistor=10:12 to 10:15, in addition to the above-mentioned advantage, the reliability and the stability of the semiconductor memory device can be improved. 
     In still another aspect of the invention, since the dielectric constant of the gate oxide film of the driving transistor is made larger than the dielectric constant of the gate oxide film of the switching transistor, the gate capacitance C ox  of the driving transistor can be increased, and thus the β ratio can be increased.