Abstract:
Disclosed is a semiconductor device having ferroelectric capacitors above a principal surface of a substrate and a process for producing the same wherein an oriented polycrystal silicon film or an amorphous silicon film  52  is disposed on the whole area beneath a conductive diffusion barrier,  61  or  73 , under a lower electrode,  62  or  74 , of each ferroelectric capacitor formed in the device. As a result, the conductive diffusion barrier, the lower electrode and the capacitor ferroelectric film become oriented films; therefore, it is possible to reduce the signal variation in capacitors even in minute semiconductor devices, and obtain a highly reliable semiconductor device.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]    This application is a continuation of U.S. application Ser. No. 09/705,692, filed Nov. 6, 2000, which, in turn, is a continuation of U.S. application Ser. No. 09/142,011, now U.S. Pat. No. 6,144,052, filed Aug. 31, 1998, which is a Section 371 of International Application PCT/JP96/00579, filed Mar. 8, 1996, and the entire disclosures of which are hereby incorporated by reference. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    The present invention relates to a large-scale integrated circuit (LSI) using minute capacitors, and a process for producing the same.  
           [0003]    In order to obtain a given capacitance in a small planar area in a large-scale integrated circuit including a dynamic random access memory (DRAM), the structure has become more complicated with the increase in the degree of integration. A silicon oxide film or silicon nitride film used as a dielectric film for capacitors has a low dielectric constant; therefore, ferroelectric materials, having a very large dielectric constant in the range of from several hundreds to several thousands, have been investigated for use as a capacitor dielectric film, as disclosed in Japanese Patent Application Laid-Open No. 63-201998.  
           [0004]    Ferroelectric materials have spontaneous polarization, and the direction thereof can be reversed by an applied electric field. Therefore, by using this property, the formation of nonvolatile memories has been attempted.  
           [0005]    As the aforementioned ferroelectric materials, an oxide ferroelectric material, such as lead zirconate titanate or bismuth layer ferroelectric material, is commonly known. A memory using a ferroelectric material employs the phenomenon that the spontaneous polarization of the ferroelectric material is reversed by a high electric field value and the direction of spontaneous polarization corresponds to the information “1” and “0” in the memory. In order to read the information stored in the memory, an electric field is applied to the ferroelectric film to detect electric charges flowing out at that time. The spontaneous polarization is directed to a specific direction in the crystal, but in a thin film ordinarily composed of polycrystal, its average value corresponds to the effective amount of information.  
           [0006]    As disclosed in, for example, Japanese Patent Application Laid-Open No. 3-256358, the structure of a memory generally includes a semiconductor substrate having a formed MOS transistor which is coated with a dielectric material  81  (FIG. 13) and on which a ferroelectric capacitor is formed, wherein one electrode of the ferroelectric capacitor is connected to the source or the drain of the MOS transistor by means of a conductive material  82  embedded inside a contact hole formed in the dielectric material. In this structure, a capacitor is formed to extend over a plug  82  in which polysilicon is embedded in an amorphous interlayer dielectric layer  81 . The capacitor is formed of an upper electrode  86 , a ferroelectric film  85  and a lower electrode  84 . The temperature for making the ferroelectric film  85  is 500° C. or more. Thus, the lower electrode  84  commonly is made of platinum. However, a conductive diffusion barrier  83 , such as Ti, Ta, TiN or TiSi 2 , is disposed between the platinum electrode  84  and the polycrystal silicon layer  82 , so as to prevent deterioration of the ferroelectric capacitor characteristics by the phenomenon that platinum reacts with silicon to form a silicide, or Si is diffused in the platinum to form a Si oxide film on the surface of the platinum. This conductive diffusion barrier  83  is a polycrystal because it is formed on the polycrystal silicon layer  82  and the amorphous interlayer dielectric  81 . For this reason, the ferroelectric film  85  formed thereon also becomes a polycrystal. On the other hand, there is also a known structure wherein a conductive diffusion barrier is formed on the polycrystal silicon, as described in Japanese Patent Application Laid-Open 6-5810, although the polycrystal silicon is not formed as an underlayer to improve the crystallinity of films formed thereon.  
           [0007]    As memories are highly integrated, however, the area of a capacitor becomes smaller so that its size will become as small as the size of a crystallite of a ferroelectric material. In this state, spontaneous polarization is directed in a direction perpendicular to the substrate in a crystallite of a certain capacitor while spontaneous polarization is directed in parallel to the substrate for a crystallite of the other capacitor. In nonvolatile memories, therefore, spontaneous polarization values for their capacitors are largely varied so that the memories will incorrectly operate. Similarly, in DRAMs their signals are varied from cell to cell. Thus, it is necessary that a finite number of crystallites constituting respective capacitors are oriented in a specific direction. However, control of crystal orientation of the electrode on the capacitor cannot be expected in the case, as in the prior art memories, wherein the capacitor is formed to extend over the polycrystal silicon layer  82  and the amorphous interlayer dielectric  81 , or wherein the capacitor is formed on the polycrystal silicon layer, but includes a very thin portion, and crystallographic properties or surface roughness are not taken into account.  
           [0008]    An object of the present invention is to provide a semiconductor device having capacitors whose spontaneous polarization does not vary from capacitor to capacitor, and are highly reliable and suitable for high integration; and a process for producing the semiconductor.  
         SUMMARY OF THE INVENTION  
         [0009]    This object can be attained by disposing an oriented poly film as it is, or an amorphous film as it is, under the whole area of diffusion barrier under a platinum lower electrode for a capacitor using a ferroelectric material.  
           [0010]    It is preferred to arrange a conductive layer as a diffusion barrier ( 61 ) comprising TiN for preventing silicon from reacting with platinum between the aforementioned oriented semiconductor, such as a polycrystal silicon film, or the amorphous semiconductor film, such as an amorphous silicon film (FIG. 10, reference number  52 ) and the platinum lower electrode ( 62 ). The platinum lower electrode ( 62 ) is electrically connected to a desired area of the semiconductor element, for example, the source or the drain area (FIG. 8, reference number  25  and  26 ) of a MOS transistor through the conductive diffusion barrier ( 61 ).  
           [0011]    In the case of disposing a TiN film as the conductive diffusion barrier, the [111] orientation of the TiN film is preferred to prompt the [111] orientation of the platinum lower electrode. In order to obtain a platinum film having an intense [111] orientation, the FWHM (full width at half maximum) value of the rocking curve of the TiN [111] diffraction peak is preferably 12 degrees or less.  
           [0012]    To form such a TiN film having an intense [111] orientation, Ti is reactively sputtered under the condition of a shortage of nitrogen-supply. The sputtering gas is inert gas, such as argon, which preferably contains from 20 to 60% by mole of nitrogen. When the nitrogen-supply is insufficient, the formed TiN film contains excessive Ti and is liable to have a [111] orientation.  
           [0013]    More preferably, the TiN film is annealed in an ammonia atmosphere after the formation of a thin layer containing, as the main component, platinum thereon, in order to improve the crystallinity and orientation of the TiN film formed under the aforementioned condition and further to approximate its composition to achieve stoichiometry for improvement in resistance to oxidization.  
           [0014]    TiN has a crystal structure of the sodium chloride type. Thus, when its [111] direction grows perpendicular to the substrate, the arrangement of atoms is similar to the [111] surface of platinum so that the platinum electrode film has a higher [111] orientation. Furthermore, on the [111]-oriented platinum electrode, a ferroelectric material of a perovskite type, for example, lead zirconate titanate, easily grows with a [111] orientation. In the semiconductor device according to the present invention, the polycrystal silicon film is formed under the whole area of the TiN film. For this reason, the platinum electrode grows with a [111] orientation; therefore, the perovskite type ferroelectric material grows with a [111]- orientation. In this oriented film, the spontaneous polarization directions are the same so that polarization can be easily reversed and any memory cells can exhibit the same polarization values.  
           [0015]    In the structure of TiN, which is used as an adhesion and diffusion barrier layer, a platinum electrode, PZT, and the effects of the substrates on the [111] orientation of the lead zirconate titanate were investigated.  
           [0016]    At first, a TiN film of 100 nm was formed on a silicon substrate by a reactive sputtering process. The sputtering condition for the TiN film formation was as follows: the inputted power was 200 W, the sputtering gas was argon containing from 20 to 60% of nitrogen gas, and its gas pressure was 20 mTorr, and the substrate was not heated. After that, a 20-nm-thick platinum film was formed by a sputtering process. The sputtering condition for the platinum film formation was as follows: the inputted power was 400 W, the sputtering gas was argon gas (100%), its gas pressure was 5 mTorr, and the substrate was heated to 300° C.  
           [0017]    The results of X-ray diffraction demonstrated that TiN films formed on different substrate material or under different sputtering gas compositions had different orientations, such as a [111] or [100] orientation. The [111] orientation of the platinum films formed on these TiN films were also varied by influence of the TiN underlayer. The FWHM value of the Pt[111] rocking curve was changed within the range from 2 to 15 degrees. Furthermore, a 100-nm thick lead zirconate titanate film was formed by sol-gel process. The sol was obtained by reacting lead acetate, titanium isoproxide, and zirconium isoproxide in methoxy ethanol. The film was subjected to rapid thermal annealing at 650° C. for 2 minutes in an oxygen atmosphere for crystallization. The films were evaluated by X-ray diffraction.  
           [0018]    [0018]FIG. 1 shows the relationship between the FWHM value of the Pt[111] rocking curve and the [111] degree of orientation for the lead zirconate titanate (PZT) thin film. As understood from this figure, the [111] degree of orientation of the lead zirconate titanate thin film decreased with the FWHM value of the Pt[111] rocking curve. When the FWHM value of the Pt[111] rocking curve is 5 degrees or less, the lead zirconate titanate film is perfectly [111]-oriented.  
           [0019]    [0019]FIG. 2 shows the relationship between the FWHM value of the TiN[111] rocking curve and the FWHM value of the Pt[111] rocking curve. As the FWHM value of the TiN[111] rocking curve decreased, the FWHM value of the Pt[111] rocking curve is also decreased. In order to form a Pt film whose FWHM value of the [111] rocking curve is 5 degrees or less, it is necessary that the platinum film should be grown on a TiN film whose FWHM value of the [111] rocking curve is 12 degrees or less.  
           [0020]    Next, FIG. 3 shows X-ray diffraction patterns of TiN films formed on an amorphous oxidized silicon film formed by the CVD process, on a polycrystal silicon film formed on a Si substrate heated up to a crystallization temperature and not exhibiting any specific orientation (hereafter called an in-situ polycrystal silicon), on a polycrystal crystallized by post-annealing and having a [111] orientation, and on an amorphous silicon film. The TiN films on the polycrystal silicon film having a [111] orientation and on the amorphous silicon film clearly have a higher [111] orientation. The TiN films on the amorphous oxidized silicon film and on the polycrystal silicon film not exhibiting any orientation have a bad crystallinity and do not show a strong orientation. The FWHM value of the [111] rocking curve was  9  degrees for the TiN film on the polycrystal silicon film having a [111] orientation, while that for the TiN film on the amorphous oxidized silicon film was 15 degrees or more. The orientation of the TiN film on the polycrystal silicon film not exhibiting any orientation was somewhat better than that of the TiN film on the amorphous oxidized silicon film. This is because silicon has a larger surface energy and, consequently, it has a smaller contact angle to the substrate than amorphous oxidized silicon, and the in-situ polycrystal silicon film does not exhibit any specific crystal orientation and has also a large surface roughness. Accordingly, it has been found that for forming a highly [111]-oriented TiN film, it is necessary to choose an underlying material which has a large surface energy, and also to take into account the crystal orientation and roughness of the underlayer. The aforementioned silicon films are generally phosphorus-doped silicon films, but the crystal property of TiN films does not depend on the dopant concentration of phosphorus. This is because there is no big difference in Si growth rate in the temperature range of the memory-cell process (&lt;900° C.) although the crystallization temperature is lowered with the dopant level.  
           [0021]    An upper gold electrode was formed using a metal mask, on 100-nm-thick lead zirconate titanate thin films derived by sol-gel process and their dielectric properties were examined. It was found that the lead zirconate titanate thin films formed on the polycrystal silicon film having a [111] orientation, or on the amorphous silicon film, had a small coercive field and showed a square hysteresis curve, while the lead zirconate titanate thin films on the amorphous oxidized silicon film and on the in-situ polycrystal silicon film had a large coercive field and a small remnant polarization. This is because the TiN films on the polycrystal silicon film have a [111] orientation and on the amorphous silicon film have a higher [111] orientation, so that platinum will have a higher [111] orientation and, further, the lead zirconate titanate thin film will have a higher orientation. However, as the amorphous silicon has a somewhat high resistivity, it is preferably annealed after TiN deposition to be crystallized.  
           [0022]    These results show that post annealed polycrystal silicon is needed as an underlayer of TiN.  
           [0023]    As described above, a lead zirconate titanate thin film having good characteristics is formed on a TiN film with an intense [111] orientation. Thus, the condition for forming such a TiN film was examined. FIG. 4 shows the relationship between the flow ratio of argon and nitrogen in a reactive sputtering process and the FWHM value of the TiN [111] rocking curve. When the percentage of nitrogen flow was from 20 to 60%, a TiN film was formed whose FWHM value of the TiN [111] rocking curve was less than 10 degrees. This may be attributed to the preferred orientation of titanium when a TiN film is formed under the condition of supplying excessive titanium.  
           [0024]    Furthermore, the TiN film was annealed in ammonia gas to improve the [111] orientation. FIG. 5 shows the annealing temperature dependence of the molar ratio of N to Ti in the TiN film and the FWHM value of the TiN [111] rocking curve. When the TiN film is annealed at a temperature greater than 650° C., the FWHM value of the TiN [111] rocking curve was drastically decreased and the molar ratio of N to Ti was increased. When the annealing treatment was conducted at a temperature of 750° C. or higher, this effect was especially remarkable. It has been found that use of TiN film annealed in ammonia in such a manner affects the lead zirconate titanate thin film to have a higher [111]-orientation, and also improves the degree of nitrization, thereby improving the resistance to oxidization.  
           [0025]    According to the present invention, therefore, spontaneous polarization is not varied from capacitor to capacitor, wherein the crystal orientation of the ferroelectric material is controlled, and, consequently, it is possible to obtain a highly reliable semiconductor device. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0026]    [0026]FIG. 1 is a graph which shows the relationship between the FWHM value of a Pt [111] rocking curve and the ratio of PZT [111] diffraction peak intensity.  
         [0027]    [0027]FIG. 2 is a graph which shows the relationship between the FWHM value of a TiN [111] rocking curve and the FWHM value of a Pt [111] rocking curve.  
         [0028]    [0028]FIG. 3 is a graph which shows X-ray diffraction patterns of TiN films formed on amorphous silicon, [111] oriented polycrystal silicon, polycrystal silicon and amorphous silicon.  
         [0029]    [0029]FIG. 4 is a graph which shows the dependence of the FWHM value of a TiN [111] rocking curve on the percentage of nitrogen flow.  
         [0030]    [0030]FIG. 5 is a graph which shows annealing temperature dependence of the FWHM value of a TiN [ 111 ] rocking curve, and the atomic ratio N/Ti in the TiN film.  
         [0031]    FIGS.  6 - 10  are cross sections showing steps of a process for producing a memory cell according to the present invention.  
         [0032]    [0032]FIG. 11 is a top view illustrating a memory cell according to the invention.  
         [0033]    [0033]FIG. 12 is a cross section of a memory cell according to the invention.  
         [0034]    [0034]FIG. 13 is a cross section of a memory cell in the prior art.  
         [0035]    [0035]FIG. 14 is a diagram which shows the amount of electric charges when the spontaneous polarization in a ferroelectric material is reversed and non-reversed. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
     EXAMPLE 1  
       [0036]    FIGS.  6 - 10  illustrate the steps for producing an Example of memory cells using the present invention, and FIG. 11 shows a top view of such memory cells. The cross sections illustrated in FIGS.  6 - 10  are taken along the line A-A′ in FIG. 11. In accordance with the present invention, a capacitor-over-bitline-type stacked structure, as described in Japanese Patent Application Laid-Open No. 3-256356, was used, and the storage capacitor had a flat structure. This cell structure works as a nonvolatile memory when it is operated so as to read the amount of switching charges Qsw or non-switching charges Qd depending on the polarization state, while it functions as DRAM when it is operated to read the non-reversal charges Qd, as shown in FIG. 14.  
         [0037]    Referring to FIG. 6, a switching transistor is firstly formed by a conventional MIS type FET producing process. Herein,  21  represents a p-type semiconductor substrate,  22  represents an isolation dielectric film,  23  represents a gate oxide film,  24  represents a word line which will be a gate electrode,  25  and  26  represent n-type dopant layers (phosphorus), and  27  represents an interlayer dielectric. A known CVD process is used to form a 50-nm-thick SiO 2  film  28  and a 600-nm-thick Si 3 N 4  film  29 , respectively, on the whole surface, and then the Si 3 N 4  film is etched off, in the thickness direction thereof, to embed the dielectric film between the word lines. The SiO 2  film  28  is an undercoat when bit lines are processed in the next step, and functions to prevent exposure of the surface of the substrate and etch-off of the isolation dielectric film.  
         [0038]    Subsequently, as shown in FIG. 7, portions  25  where the bit lines will contact the n-type diffusion layers at the surface of the substrate and portions  26  where the electrodes will contact the n-type dopant layers at the surface of the substrate are bored by known photolithographic and dry etching processes. A 600-nm-thick polycrystal silicon film containing an n-type dopant is deposited using a CVD process, and then etching is carried out in its thickness direction, so that polycrystal silicon films  31  and  32  are filled into the contact holes formed by the aforementioned etching.  
         [0039]    Next, as shown in FIG. 8, a known CVD process is used to deposit a dielectric film  41  on the whole surface, and then portions of the dielectric film  41  on the polycrystal silicon film  31  are removed by known. photolithographic and dry etching processes in order that the bits lines can be electrically connected to the diffusion layer  25  in the substrate. Subsequently, the bit lines  42  are formed. As a material for the bit lines; a stacked film of metal silicide and polycrystal silicon was used. Thereon, a 200-nm-thick SiO 2  film  43  is deposited. The SiO 2  film  43  and the bit lines  42  are processed by known photolithographic and dry etching processes. Furthermore, a 150-nm-thick Si 3 N 4  film is deposited by a CVD, and etched by a dry etching process to form side wall spacers of Si 3 N 4  on the side walls of the bit lines, thereby insulating the bit lines. The dielectric film  41  on the polycrystal silicon film  32  was removed by using known photolithographic and dry etching processes.  
         [0040]    Subsequently, as shown in FIG. 9, a silicon oxide film  51 , such as BPSG, was deposited to planarize the substrate surface. It is necessary for this dielectric film  51  to have a thickness sufficient to planarize the substrate surface. In the present example, the thickness of the dielectric film  51  was 500 nm. Another possible process is depositing a SiO 2  film on the substrate by a CVD process and etching back the surface. Then, known photolithographic and dry etching processes are used to make contact holes in the interlayer dielectric film  51 . A phosphorus-doped amorphous silicon film 250 nm-thick  52  for embedding is then deposited by a CVD process, and, subsequently, an etching back is carried out by a dry etching process to fill up the contact holes. At this time, the phosphorus-doped amorphous silicon film  52  which is 50-nm-thick remains on the silicon oxide film  51 , without being etched. It is necessary that the phosphorus-doped amorphous silicon film has a thickness of 10 nm or more for maintaining good crystal property after annealing treatment. If the thickness is too large, the height of the capacitor stack increases. It is difficult for a thin silicon film of from 10 to 30 nm to remain unetched. In this case, therefore, etching back is carried out until the interlayer dielectric is etched away from the phosphorus-doped amorphous silicon film for embedding, and then a new phosphorus-doped amorphous silicon film is again formed. This process is well controlled.  
         [0041]    Next, as shown in FIG. 10, a 100-nm-thick TiN film  61  is formed as a diffusion barrier and a 100-nm-thick platinum electrode  62  is formed. In accordance with the present invention, the TiN film  61  was formed by a DC sputtering process using 50% nitrogen and 50% argon. Then, a lead zirconate titanate thin layer  63  was formed by a sol-gel process, and then approximately a 50 nm platinum upper electrode  64  was formed using a sputtering process. The five layers on the phosphorus-doped amorphous silicon film  52  are etched at one time as follows. A 250-nm-thick tungsten film is first formed as a hard mask, and a photoresist pattern is transcribed on the tungsten film by sputter etching in argon gas using a photoresist as a mask. Using this tungsten film as a mask, the Pt film  64 , the lead zirconate titanate thin layer  63 , the platinum lower electrode  62  and the TiN film  61  are successively patterned. Then, it is coated with an interlayer dielectric, followed by metalization to connect the upper platinum electrode, so as to complete a capacitor in the memory cells. In FIG. 10, however, interlayer dielectric and metalization are not shown to avoid complication in the figure. In the case wherein the angle of the side wall to the bottom face of the aforementioned five layers is less than 75 degrees, a short-circuit between the upper and lower electrodes caused by deposition on the side walls can be prevented even if the capacitor is etched at one time.  
         [0042]    The dielectric property of this capacitor was measured. For the capacitors of 0.2 to 100 μm 2 , square hysteresis curves were obtained in all cases, and the size-dependency of spontaneous polarization was not found. This is because the underlayer of the TiN film was wholly composed of phosphorus-doped amorphous silicon films, consequently, the TiN film had a [111] orientation and the lead zirconate titanate thin layer also had a [111] orientation.  
         [0043]    Similar properties were obtained when the lead zirconate titanate (Pb(Zr 0.5  Ti 0.5 )0 3 ) thin layer was formed by using a high frequency magnetron sputtering process. The sputtering conditions were as follows: the high frequency power was 200 W. argon gas containing  10  % of oxygen was used as sputtering gas, and its gas pressure was 10 Pa. The temperature of the substrate was 650° C. Thus, a crystallized PZT film was directly formed. If the lower electrode and the diffusion barrier are formed in this manner according to the process of the present invention, the diffusion barrier is not oxidized in the crystallization process of an amorphous ferroelectric material by post annealing or in the process wherein a crystallized film is directly formed. Accordingly, reactive vapor deposition or a CVD process may be used.  
         [0044]    In the aforementioned example, lead zirconate titanate (Pb(Ti x Zr 1−x )0 3 ), wherein X=0.5, was given as an example of the ferroelectric material. However, even if lead zirconate titanate having different compositions, such as barium lead zirconate titanate, or a bismuth layered ferroelectric material, is used, a memory cell can be formed similarly.  
       EXAMPLE 2  
       [0045]    In example 1, the phosphorus-doped amorphous silicon film for embedding was left and it functioned as an underlayer for the TiN film. However, as shown in FIG. 12, interlayer dielectric and contact holes may be formed in a two-step process, and the contact holes in the second layer can be made larger. In this case, phosphorus-doped amorphous silicon layers for embedding are formed, by the thickness of the respective interlayer dielectrics, and the phosphorus-doped amorphous silicon layer is subjected to etch-back just to be embedded. The process for producing the capacitor is the same as in example 1. The height of the capacitor can be made smaller by embedding the portion connected to the substrate into the interlayer dielectrics in the manner as mentioned above.  
         [0046]    As described above, the present invention is applicable to all volatile and nonvolatile semiconductor devices using a capacitor.