Abstract:
First and second integer transform matrices can be used to approximate the discrete cosine transform. An input matrix of data is multiplied by a first transform matrix of integers to produce an intermediate matrix of data. The intermediate matrix is multiplied by a second transform matrix of integers to produce a transform result matrix of data. The multiplications by the first and second transform matrices can be pipelined to increase throughput. A plurality of transform data paths can also be provided in parallel to increase throughput.

Description:
PRIORITY CLAIM 
   This application claims the priority under 35 U.S.C. §119(e) of co-pending U.S. Provisional Application No. 60/531,489, filed on Dec. 19, 2003 and incorporated herein by reference. 

   TECHNICAL FIELD 
   This disclosure is generally directed to data processing and more specifically to video compression processing. 
   BACKGROUND 
   The documents listed below are incorporated herein by reference.
     [1]. T. Weigand, G. S. Sullivan, G. Bjontegaard, and A. Luthra, “Overview of the H.264/AVC Video Coding Standard,”  IEEE Transaction on Circuits and Systems for Video Technology , Vol. 13, No. 7, pp. 560-576, July 2003,   [2] Draft ITU-U Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. H.264|ISO/IEC 14496-10 AVC), Geneva, Switzerland, May 2003.   [3]. N. Ahmed, T. Natarajan, and K. B. Rao, “Discrete Cosine Transform,”  IEEE Transaction on Computers , Vol. C-23, pp. 90-93, January 1974.   [4] H. S. Malvar “Low Complexity Length-4 Transform and Quantization with 16-bit Arithmetic” ITU-T SC 16, September 2001, Docs. VCEG-N43   [5] H. S. Malvar, A. Hallapuro, M. Karczewicz, and I., Kerofsky “Low Complexity Transform and Quantization in H.264/AVC”  IEEE Transaction on Circuits and Systems for Video Technology , Vol. 13, No. 7, pp. 598-603, July 2003.   [6] H. Malvar, “Fast Computation of the Discrete Cosine Transform and the Discrete Hartley Transform,”  IEEE Trans. on Acoustics, Speech and Signal Processing , Vol. ASSP-35, No. 10, pp 1484-1485, October 1987.   [7] Y. Arai, T. Agui, and Nakajima, “A Fast DCT-SQ Scheme for Images,”  Trans. of the IEICEE , Vol. E71, No. 9, pp 1095-1097, November 1988.   [8] W. B. Pennebaker, J. L. Mitchel,  JPEG Still Image Compression Standard , Van Nostrand Reinhold, New York (1992).   [9] T. D. Tran, “The BinDCT: Fast Multiplierless Approximation of the DCT,”  IEEE Signal Processing Letter , vol. 7, pp. 141-145, June 2000.   [10] J. Liang and T. D. Tran, “Fast Multiplierless Approximations Of The DCT With The Lifting Scheme,”  IEEE Trans. on Signal Processing , vol. 49, pp. 3032-3044, December 2001.   [11] Steve Furber, “ARM System-on-chip Architecture”, Addison Wesley 2000.   [12] ARM Limited, ARM946-E-S Technical Reference Manual, 2001.   

   H.264/AVC is the latest video compression standard. It was developed by the Joint Video Team (JVT), which includes experts from the Video Coding Experts Group (VCEG) of the International Telecommunications Union (ITU-T) and the Moving Picture Experts Group (MPEG) from the International Organization for Standardisation (ISO) and the International Electrotechnical Commission (IEC). In ITU-T&#39;s documents, the formal name of the new video compression standard is ITU-T Recommendation H.264. The ISO/IEC called it the ISO/IEC 14496-10 Advanced Video Coding. For short reference, this new video compression standard is commonly referred as the H.264/AVC. 
   H.264/AVC has many applications, including: video broadcasting over cable, satellite and DSL; video-on-demand or multimedia streaming services; conversational services over ISDN, Ethernet, LAN, wireless and mobile networks; and interactive or serial storage on optical devices such as DVD. 
   The H.264/AVC was designed for higher coding efficiency. In order to obtain better compression, H.264/AVC standard adopted many advanced video coding techniques. For intra coding, H.264/AVC uses a directional spatial prediction scheme to find more redundancies among pixels within a video frame. For inter coding, H.264/AVC implements multiple frames reference, weighted prediction, de-blocking filter, variable block size and quarter sample accurate motion compensations. For transformation, H.264/AVC uses a small, block-based, integer, and hierarchical transform. For entropy coding, H.264/AVC adopts two different coding techniques. The context adaptive based arithmetic coding (CABAC) is selected for the main profile whereas the context adaptive variable length coding (CAVLC) is used for baseline, main and extended profiles. Three profiles of H.264/AVC support 15 levels. These levels specify sets of algorithms and parameters for a wide range of video applications. 
   Note that the integer transform of H.264/AVC has lower complexity than that of the Discrete Cosine Transform (DCT) in previous video compression standards. Fifteen levels of H.264/AVC, however, cover a wide range of video formats from SQCIF (128×96) to 16:9 (4096×2304). For real time video processing, the number of macroblocks that must be processed per second is very high and is not efficient for software implementation. For instance, to process 30 frames of CIF (352×288) video format in real time, an embedded processor must process 11,880 macroblocks, which requires 36,495,360 shift and add instructions. Without load, store and transposition operations, this complexity already costs more than 36 million instructions per second (MIPS). This computational complexity is high for most embedded applications. The 16:9 format has an even far greater computational complexity than CIF. 
   The Discrete Cosine Transform (DCT) is one of the most important transformations in image and video processing. It has been used in many compression standards which include JPEG, H.261, H.263, MPEG-1, MPEG-2, and MPEG-4. The DCT was first proposed by Ahmed, Natarajan, and Rao in 1974 (see document [3] above). Their landmark paper presents an N-point DCT that can be computed with a 2N-point FFT and some additional post-processing. The one-dimensional DCT can map a vector x of length N into a new vector z of transform coefficients by a linear transformation z=Hx, where H is an N×N matrix such as shown in  FIG. 1 , and where C 1   √{square root over (½)}  cos (π/8), C 2   =√{square root over (½)}  cos (2π/8), and C 3   =√{square root over (½)}  cos (3π/8). Let X be a 4×4 input matrix, Y be a 4×4 output matrix, and H t  be the transpose matrix of H. The two-dimensional (2-D) 4×4 forward DCT is then defined as Y=HXH t . 
   A basic disadvantage of the 4×4 DCT is that the entries in H ( FIG. 1 ) are irrational numbers. Hence, both the forward 4×4 DCT and the inverse 4×4 DCT require floating-point execution units. The floating-point implementation increases the hardware complexity of the coding system. 
   To resolve this problem, Malvar (see document [4] above) suggested a method that scales entries of the 4×4 DCT matrices to obtain integer operations. The output results are rescaled to obtain an approximation of 4×4 DCT. Malvar used the scaling factor α=2.5 (see documents [4] and [5] above). The resulting scaled matrix K is shown at  21  in  FIG. 2 .  FIG. 3  illustrates the use of the integer transform matrix  21  to perform a 4-point one-dimensional integer transform on a vector x. 
   The approximation of a two-dimensional 4×4 DCT is Z=(KXK t ){circle around (x)}S where Z is a 4×4 matrix, and S is a 4×4 resealing matrix. The matrix S is typically incorporated into the quantization stage, which is usually implemented by lookup tables. Therefore, the approximation of a two-dimensional 4×4 DCT can be implemented completely by integer operations. With the matrix S incorporated into the quantization stage, the two-dimensional 4×4 integer transform is W=KXK t . 
   In view of the computational complexities associated even with integer transform processing of the various video formats supported by H.264/AVC, it is desirable to provide for integer transform processing with reduced computational complexity. 
   SUMMARY 
   Exemplary embodiments of the invention utilize first and second integer transform matrices to approximate the discrete cosine transform. An input matrix of data is multiplied by a first transform matrix of integers to produce an intermediate matrix of data. The intermediate matrix is multiplied by a second transform matrix of integers to produce a transform result matrix of data. The multiplications by the first and second transform matrices can be pipelined to increase throughput. A plurality of transform data paths can also be provided in parallel to increase throughput. 
   The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art will appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form. 
   Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words or phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, whether such a device is implemented in hardware, firmware, software or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, and those of ordinary skill in the art will understand that such definitions apply in many, if not most, instances to prior uses, as well as to future uses, of such defined words and phrases. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, wherein like numbers designate like objects, and in which: 
       FIG. 1  illustrates a matrix for performing a 4×4 discrete cosine transform according to the prior art; 
       FIG. 2  illustrates a scaled and round-off version of the matrix of  FIG. 1  for performing an integer approximation to the discrete cosine transform of  FIG. 1  according to the prior art; 
       FIG. 3  illustrates the use of the matrix of  FIG. 2  according to the prior art; 
       FIG. 4  illustrates factoring of the matrix of  FIGS. 2 and 3  according to exemplary embodiments of the invention; 
       FIG. 5  illustrates an exemplary implementation of the  FIG. 4  factoring according to the invention; 
       FIG. 6  illustrates a first stage matrix multiplication operation of the  FIG. 5  implementation according to exemplary embodiments of the invention; 
       FIG. 7  illustrates a second stage matrix multiplication operation of the  FIG. 5  implementation according to exemplary embodiments of the invention; 
       FIG. 8  diagrammatically illustrates exemplary embodiments of a data processing apparatus which can perform the first and second stage matrix multiplication operations of  FIGS. 6 and 7  according to the invention; 
       FIG. 9  illustrates in tabular format the timing of exemplary operations which can be performed by the data processing apparatus of  FIG. 8 ; 
       FIG. 10  diagrammatically illustrates exemplary embodiments of a data processing apparatus which can perform two-dimensional transform operations according to the invention; 
       FIG. 11  illustrates in tabular format the timing of exemplary operations which can be performed by the data processing apparatus of  FIG. 10 ; 
       FIG. 12  diagrammatically illustrates exemplary embodiments of a data processing apparatus which can perform a plurality of two-dimensional transforms in parallel according to the invention; and 
       FIG. 13  diagrammatically illustrates a data processing system according to exemplary embodiments of the invention. 
   

   DETAILED DESCRIPTION 
     FIGS. 1 through 13 , discussed below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented relative to any suitable data processing application. 
     FIG. 4  illustrates factoring of the integer transform matrix  21  of  FIGS. 2 and 3  according to exemplary embodiments of the invention. In  FIG. 4 , the integer transform matrix  21  is factored into constituent transform matrices  41  and  42  which, when multiplied together, produce the matrix  21 . Considering again the 4-point one dimensional integer transform illustrated in  FIG. 3 , that transform requires twelve addition operations and four multiplication (typically data shift) operations. This means that a 4×4 one dimensional integer transform using the matrix  21  of  FIG. 3  would require 48 addition operations and 16 shift operations, and a 4×4 two dimensional integer transform using the matrix  21  of  FIG. 3  would require 96 addition operations and 32 shift operations. 
   However, if the integer transform operation is performed using the constituent factor transform matrices  41  and  42  of FIG.  4 , then a 4 point one dimensional integer transform operation of the type illustrated in  FIG. 3  can be performed with only 8 addition operations and 2 multiplication (shift) operations. This means that a 4×4 one dimensional integer transform operation can be performed with 32 addition operations and 8 shift operations, and a 4×4 two dimensional integer transform operation can be performed with 64 addition operations and 16 shift operations. 
     FIG. 5  illustrates an exemplary implementation of the constituent factor transform matrices  41  and  42  of  FIG. 4  according to the invention. In  FIG. 5 , the transform matrices  41  and  42  are used to perform a 4×4 one dimensional integer transform on a matrix  51  of input data, in order to produce a 4×4 transform result matrix  52 . The data components of input matrix  51  are designated by x rj  in  FIG. 5  where r and j are the respective row and column indices of the matrix  51 , and where r and j can each take the values 0, 1, 2 and 3. The data components of the transform result matrix  52  are designated as b rj  in  FIG. 5 , where r and j are the same respective row and column indices as described above with respect to matrix  51 . 
     FIG. 6  illustrates a first stage (stage  1 ) integer transform operation associated with the implementation of  FIG. 5 . In the example of  FIG. 6 , the transform matrix  41  is used as a first stage transform matrix and is multiplied by the input data matrix  51  to produce an intermediate data matrix  61  whose components are designated as a rj , where r and j are the same respective row and column indices as described above with respect to matrices  51  and  52 . 
     FIG. 7  illustrates a second stage (stage  2 ) integer transform operation associated with the implementation of  FIG. 5 . In  FIG. 7 , the matrix  42  is used as a second stage transform matrix and is multiplied by the intermediate matrix  61  in order to produce the transform result matrix  52  (see also  FIG. 5 ). 
     FIG. 8  diagrammatically illustrates exemplary embodiments of a data processing apparatus which can perform the first and second stage operations described above with respect to  FIGS. 6 and 7 . The apparatus of  FIG. 8  includes a matrix multiplication apparatus having a matrix multiplier  81  which performs the first stage matrix multiplication operation illustrated in  FIG. 6 , and having a matrix multiplier  82  which performs the second stage matrix multiplication operation illustrated in  FIG. 7 . As shown in  FIG. 8 , the first stage matrix multiplier  81  receives the data from the input data matrix  51  and performs the arithmetic operations necessary to produce the intermediate data matrix  61  (see also  FIG. 6 ). In particular, the matrix multiplier  81  includes four adders connected appropriately, and with necessary inversions, to perform the four addition operations required to implement the matrix multiplication equation of  FIG. 6 . The matrix multiplier  82  receives the data from the intermediate matrix  61  and performs the arithmetic operations necessary to produce the transform result matrix  52  (see also  FIG. 7 ). The matrix multiplier  82  includes four adders connected appropriately, and with necessary inversions and shifters, to perform the four addition operations and two shift operations required to implement the matrix multiplication equation of  FIG. 7 . Data shifters  83  and  84  each perform a single left shift (multiply by 2) operation in order to implement the two multiplication operations required by the equation of  FIG. 7 . 
     FIG. 9  illustrates in tabular format the timing of exemplary operations which can be performed by the data processing apparatus of  FIG. 8 . In particular, and referring also to  FIGS. 6 and 7 ,  FIG. 9  shows that the data processing apparatus of  FIG. 8  can produce each column of the matrix  61  of  FIG. 6  in a single clock cycle, and can also produce each column of the matrix  52  of  FIG. 7  in a single clock cycle. That is, the adders of the matrix multiplier  81  can effectuate a multiplication of all four rows of the transform matrix  41  by any given column of the input matrix  51  in a single clock cycle, and the adders of the matrix multiplier  82 , together with shifters  83  and  84 , can effectuate multiplication of all four rows of matrix  42  by any given column of matrix  61  in a single clock cycle. Therefore, during clock cycle  2 , after the first stage matrix multiplier  81  has already produced the first column of intermediate matrix  61  during clock cycle  1 , the second stage matrix multiplier  82  can use the first column of the intermediate matrix  61  to produce the first column of the transform result matrix  52 . Thus, during clock cycle  1  of  FIG. 9 , the matrix multiplier  81  produces the first column (column  0 ) of the intermediate matrix  61 . Thereafter, during clock cycle  2  of  FIG. 9 , while the matrix multiplier  81  is producing the second column (column  1 ) of the intermediate matrix  61 , the second stage matrix multiplier  82  is simultaneously using the already-produced first column of intermediate matrix  61  to produce the first column of the transform result matrix  52 . 
   Thus, the operations of the matrix multipliers  81  and  82  can be pipelined as shown in  FIG. 9  in order to produce the complete transform result matrix  52  of  FIG. 7  in five clock cycles. So the data processing apparatus of  FIG. 8  can perform a 4×4 one dimensional integer transform in five clock cycles. As indicated by  FIG. 9 , during clock cycle  5 , while the second stage matrix multiplier  82  is producing the fourth column (column  3 ) of the transform result matrix  52  of  FIG. 7 , the first stage matrix multiplier  81  can be simultaneously operating on a subsequent input data matrix  51  to produce the first column of a subsequent intermediate data matrix  61  (see also  FIG. 6 ). 
     FIG. 10  diagrammatically illustrates exemplary embodiments of a data processing apparatus which can perform a 4×4 two dimensional integer transform according to the invention. In the example of  FIG. 10 , the architecture of  FIG. 8  is used to perform a horizontal transform HT and is also used to perform a vertical transform VT. In the matrix multiplication apparatus illustrated in  FIG. 10 , the horizontal transform portion HT performs the operations illustrated in  FIG. 8  to produce the transform result matrix  52 . This transform result matrix  52  is then stored in one of two buffers  105  and  106 , as selected by a selector  103  under control of a control signal  107 . A further selector  104  under control of a control signal  108  provides the content of one of buffers  105  and  106  to the vertical transform portion VT. In some embodiments, the buffers  105  and  106  can be read such that the data from the buffered transform result matrix  52  is provided to the vertical transform portion VT on a row-by-row basis, so the vertical transform portion VT operates on the transpose of the buffered transform result matrix  52 . This effective transposing of the buffered transform result matrix  52  is illustrated in  FIG. 10  by the use of the reference character  52   t . Transposition of the result matrix produced by horizontal transform portion HT permits the vertical transform portion VT to perform the transform in the second dimension. 
     FIG. 11  illustrates in tabular format the timing of exemplary operations which can be performed by the data processing apparatus of  FIG. 10 . In clock cycle  5 , the horizontal transform portion HT completes its operation on the first 4×4 input data matrix  51  (also designated as B 1 ), and stage  1  of the HT portion has also already begun operation on the second 4×4 input data matrix  51  (also designated as B 2 ). Because the horizontal transform portion finishes producing the first transform result matrix  52  during clock cycle  5 , this means the vertical transform portion VT can begin operations on the transpose  52   t  of the first transform result matrix  52  during clock cycle  6 . The correspondence of the transposed transform result matrices  52   t  to the input data matrices  51  is illustrated in  FIG. 11  by maintaining corresponding subscript numbers on the designators B. 
   In  FIG. 10 , the selectors  103  and  104  are controlled by logically complementary control signals  107  and  108  such that the vertical transform portion VT is never accessing the buffer to which the horizontal transform portion HT is writing. As shown in  FIG. 11 , while the vertical transform portion VT is processing the transposed transform result matrix  52   t /B 1  associated with the first input matrix  51 /B 1 , the horizontal transform portion HT is simultaneously processing data from the second input data matrix  51 /B 2  in the sequence of input data matrices. The horizontal transform portion HT can complete its operation on a sequence of six 4×4 input matrices in 25 clock cycles and, by virtue of the pipelining illustrated in  FIG. 11 , the complete two dimensional transform of a sequence of six 4×4 input data matrices is completed in thirty clock cycles. 
   The output of the vertical transform portion VT in  FIG. 10  can be provided to a conventional quantization stage for conventional rescaling and quantizing. 
     FIG. 12  diagrammatically illustrates exemplary embodiments of a data processing apparatus which can perform a plurality of 4×4 two-dimensional integer transforms in parallel according to the invention. The example of  FIG. 12  generally uses four instances of the architecture of  FIG. 10 , arranged in parallel. Therefore, the apparatus of  FIG. 12  can perform two dimensional transform processing on 24 4×4 input matrices in thirty clock cycles (see also  FIG. 11 ). The twenty four 4×4 input data blocks illustrated in the example of  FIG. 12  are the well-known constituent blocks of a conventional H.264/AVC macroblock. Each of the four 32-bit input registers can hold four 8-bit input pixels. 
     FIG. 13  diagrammatically illustrates exemplary embodiments of a data processing system according to the invention. The system of  FIG. 13 , for example a high definition television system or a digital cinema system, includes a main processor  131 , a memory portion  132 , a user interface (I/O)  133  and an accelerator coprocessor  134 . These components are interconnected by a bus system  135 . In various embodiments, the accelerator coprocessor  134  can implement the various exemplary integer transform architectures described above with respect to  FIGS. 8-12 . In some exemplary embodiments, the main processor  131  and the coprocessor  134  implement respective pipelines. The coprocessor  134  receives instructions from the main processor  131 , and uses a pipeline follower to determine what instruction it must execute. To avoid congestion in the critical path, in some embodiments the coprocessor pipeline operates one clock cycle behind the main processor pipeline. After receiving a given instruction, the coprocessor loads data from the memory and performs the necessary transform operations. 
   In some exemplary embodiments, the main processor  131  is an ARM946E-S processor, the system memory portion  132  includes 512 kilobytes of SRAM and 4 megabytes of SDRAM, and the bus system  135  is a conventional high speed AMBA bus system for increased data throughput between the main processor  131 , the coprocessor  134  and the system memory  132 . 
   Referring again to the exemplary architecture of  FIG. 12 , the hardware cost of the illustrated architecture is low. It requires four 32-bit registers, four 64-bit registers, 16 multiplexers, 32 adders and 256 bytes of buffer memory. The small buffer memory is implemented with D flip-flops in some embodiments. In one example using 0.18 μm CMOS technology, the footprint of the  FIG. 12  architecture is only 0.0838 mm 2 . Even with this small footprint, the architecture still provides sufficient computing power for real time video processing. At a 10 MHz clock rate, for example, the architecture can compute integer transforms for 2K×1K (2048×1024) format at 30 frames per second. For high definition video applications using 16:9 format (4096×2034) running at 60 frames per second, the architecture requires 66,355,200 clock cycles, which is equivalent to 67 MHz. The design of the architecture can be scaled to meet this real time constraint. 
   Note that the average power consumption of a CMOS gate due to the switching current is given by P=αC L V dd   2 f, where f is the system clock frequency, V dd  is the supply voltage, C L  is the load capacitance, and α is the switching activity. In one example of the architecture of  FIG. 12 , the clock rate is 10 MHz, the global voltage is 1.55 V, and the load capacitance is 1 pf. The switching power reported by a hardware simulation for this example is 529 μW. 
   Besides the compact area and low power consumption, exemplary embodiments of the invention require only a small data range. From  FIGS. 5-7 , the data range at the output of each stage can be easily determined. In the worst case, and assuming 8-bit pixel inputs, the outputs of the first dimensional transform (e.g. HT in  FIGS. 10 and 12 ) are 11 bits and the outputs of the second dimensional transform (e.g. VT in  FIGS. 10 and 12 ) are 14 bits. Hence, a 4×4 two-dimensional integer transform can be implemented with a 14-bit wide data path. 
   As demonstrated above, exemplary embodiments of the invention introduce a method and an apparatus to reduce computational complexity and increase the throughput of the integer transform in H.264 video compression standard. The method factors the integer transform matrix into two integer matrices with less computations. In addition, this approach also allows the integer transform be calculated in two steps, which is well suited for pipeline architecture. 
   While this disclosure has described certain embodiments and generally associated methods, alterations and permutations of these embodiments and methods will be apparent to those skilled in the art. Accordingly, the above description of example embodiments does not define or constrain this disclosure. Other changes, substitutions, and alterations are also possible without departing from the spirit and scope of this disclosure, as defined by the following claims.