Abstract:
The invention relates to a power semiconductor module including a module underside, a module housing, and at least two substrates spaced from each other. Each substrate has a topside facing an interior of the module housing and an underside facing away from the interior of the module housing. The underside of each substrate includes at least one portion simultaneously forming a portion of the module underside. At least one mounting means disposed between two adjacent substrates enables the power semiconductor module to be secured to a heatsink.

Description:
PRIORITY CLAIM 
       [0001]    This application claims priority to German Patent Application No. 102009002993.1-33 filed on 11 May 2009, the content of which is incorporated herein by reference in its entirety. 
       FIELD OF TECHNOLOGY 
       [0002]    The invention relates to power semiconductor modules. 
       BACKGROUND 
       [0003]    Power semiconductor modules comprise one or more power semiconductor chips. To dissipate the heat materializing in operation of the module the power semiconductor module is usually bonded to a heatsink. This mostly involves employing a complicated system of multiple bonds so that the pressure is evenly distributed. 
         [0004]    In addition, the module is often electrically and mechanically bonded to a user-specific gating circuit, this again necessitating a complicated system of multiple bonds for the necessary electrical connections. 
         [0005]    The power semiconductor chips of the module are usually mounted on one or more ceramic substrates because of their coefficient of thermal expansion, for one thing, being hardly different to the coefficient of thermal expansion of the semiconductor chips used, and, for another, because they achieve good dissipation of the heat materializing from operation of the power semiconductor chips. 
         [0006]    One known possibility of incorporating one or more ceramic substrates componented with power semiconductor chips in a power semiconductor module is to mount all ceramic substrates used on a common solid metal baseplate, the underside of which simultaneously forms the underside of the module and to apply the power semiconductor module by its underside to a heatsink. But, the baseplate hampers good thermal contact between the substrates and the heatsink. 
         [0007]    An alternative configuration eliminates the need of a solid metal baseplate. To attain an even distribution of the contact pressure between the substrates and the heatsink the individual substrates are pressed either along their circumferential side edges by the module housing to the heatsink which is bonded to the heatsink by a system of multiple bonds, or each of the substrates features fastener holes so that, for example by means of a screw, a contact pressure can be generated in the interior portion of the substrate in the direction of the heatsink. However, such power semiconductor modules having no common baseplate have either the disadvantage of a complicated system of multiple bonds between the power semiconductor module and the heatsink or mounting holes need to be fabricated in the ceramic substrates, again adding to the complications, taking up valuable space on the substrate, detrimenting dissipating the heat to the heatsink and, to make matters worse, risking a ceramic fracture in the region of each hole. 
         [0008]    Furthermore, the more the number of power semiconductor chips incorporated in a power semiconductor module the larger the substrates needed, the greater the footprint thereof, making it all the more difficult to attain a uniform contact pressure of the substrates against the heatsink. In addition to this an expansive substrate componented with a plurality of power semiconductor chips has to be singled out from use or repaired, which is complicated, when even just one of the power semiconductor chips develops a fault. 
         [0009]    There is a need for a power semiconductor module comprising no common metal baseplate mounting the substrates of the module and which can be simply mounted on a heatsink with a few bonds whilst in addition permitting bonding to a user-specific gating circuit. 
       SUMMARY 
       [0010]    According to an embodiment, a power semiconductor module comprises a module underside, a module housing and at least two substrates spaced from each other. Each substrate includes a topside facing an interior of the module housing and an underside facing away from the interior of the module housing. The underside of each substrate comprises at least one portion simultaneously forming a portion of the module underside. Via this portion, the waste heat materializing in the power semiconductor module can be dissipated to a heatsink. Furthermore, the module comprises at least one mounting means, e.g., a mounting hole disposed between two adjacent substrates permitting the power semiconductor module to be secured to a heatsink. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The invention can be better understood with reference to the following drawings and description. The components in the figures are not necessarily to scale, instead emphasis being placed upon illustrating the principles of the invention. Moreover, in the figures, like reference numerals designate corresponding parts. In the drawings: 
           [0012]      FIG. 1  is a view in perspective of a power semiconductor module including two substrates spaced from each other; 
           [0013]      FIG. 2  is a view in perspective of the power semiconductor module as shown in  FIG. 1  mounting a printed circuit board including a user-specific gating circuit; 
           [0014]      FIG. 3  is an exploded view of the assembly as shown in  FIG. 2 ; 
           [0015]      FIG. 4  is a view in perspective of a portion of a power semiconductor module including three substrates spaced from each other, a flange of the module housing being disposed between adjacent substrates; 
           [0016]      FIG. 5  is a view in perspective of a power semiconductor module including two substrates spaced from each other between which a flange is disposed to which a printed circuit board is secured; 
           [0017]      FIG. 6  is a vertical section through an assembly as shown in  FIGS. 2 and 3  wherein the power semiconductor module comprises a plurality of electrical contacts brought out from the topside of the module housing and configured as press-in contacts; 
           [0018]      FIG. 7  is a vertical section through an assembly as shown in  FIGS. 2 and 3  wherein the power semiconductor module comprises a plurality of electrical contacts brought out from the topside of the module housing and configured as pressure contacts; 
           [0019]      FIG. 8  is a circuit diagram of a power semiconductor module including two discrete power semiconductor switches arranged on separate substrates; 
           [0020]      FIG. 9  is a circuit diagram of a power semiconductor module including three half-bridges, each of which is arranged on a separate substrate; 
           [0021]      FIG. 10  is a circuit diagram of a power semiconductor module including three half-bridges, each of which comprises a high-side switch and a low-side switch, wherein the high-side switches are arranged in common on a first substrate and the low-side switches on a second substrate; 
           [0022]      FIG. 11  is a circuit diagram of a power semiconductor module including three half-bridges, of which a first is arranged on a first substrate and a second on a second substrate wherein the third half-bridge comprises a high-side power semiconductor switch arranged on the first substrate as well as a low-side power semiconductor switch arranged on the second substrate; 
           [0023]      FIG. 12  is a circuit diagram of a power semiconductor module including three half-bridges, at least one of which comprises a controllable low-side power semiconductor switch and a controllable high-side power semiconductor switch, wherein both the low-side and the high-side power semiconductor switches each comprise a first single switch as well as a second single switch arranged on the second substrate; 
           [0024]      FIG. 13  is a circuit diagram of a power semiconductor module comprising two componented substrates as shown in  FIG. 10 , as well as a further substrate on which a bridge rectifier switch as well as a brake chopper circuit are arranged; 
           [0025]      FIG. 14  is a circuit diagram of a power semiconductor module including a first substrate on which three half-bridge branches are arranged, as well as a second substrate on which a bridge rectifier circuit and a brake chopper circuit are arranged. 
           [0026]      FIG. 15  is a top-down view of two power semiconductor module substrates including a single mounting hole. 
           [0027]      FIG. 16  is a top-down view of three power semiconductor module substrates including two mounting holes. 
       
    
    
       [0028]    In the Figures—unless stated otherwise—like or corresponding elements having a like or corresponding function are identified by like reference numerals. 
       DETAILED DESCRIPTION 
       [0029]    In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top”, “bottom”, “front”, “back” “leading”, “trailing”, etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. 
         [0030]    Referring now to  FIG. 1  there is illustrated a view in perspective of a power semiconductor module  100  including a module housing  104  as well as two substrates T 1  and T 2  spaced from each other showing their topsides  51  facing the interior of the module housing. Disposed between the adjacent substrates T 1  and T 2  is a flange  54  represented as a component of the module housing  104  and wherein a mounting hole  53  is provided by means of which the power semiconductor module  100  can be screwed to a heatsink. 
         [0031]    The mounting hole  53  is fully disposed between the two adjacent substrates T 1  and T 2 . In this arrangement, the two adjacent substrates T 1  and T 2  may comprise two outer edges  71  and  72  facing each other between which the mounting hole  53  is arranged in the middle. 
         [0032]    Arranged circuited on the substrates T 1  and T 2  are power semiconductor chips  120  which may be, for example, IGBTs, backwards conducting IGBTs, MOSFETs, J-FETS, thyristors, diodes or any other kind of a power semiconductor component. More particularly the power semiconductor chips  120  may also be configured as controllable power semiconductor switches. 
         [0033]    Each of the substrates T 1 , T 2  features at least on its topside  51  a metallization  55  which may be patterned for circuiting the power semiconductor chips  120 . Inserted in the sidewall of the module housing  104  are electrical terminals  110  bonded in the interior module housing  104  to the power semiconductor chips  120  and brought out from the module housing  104  at the topside thereof so that the power semiconductor module  100  can be bonded to a user-specific gating electronics. 
         [0034]    To improve the dielectric strength the interior of the module housing  104  may be optionally potted, for example by a silicone gel. 
         [0035]    Referring now to  FIG. 2  there is illustrated a view in perspective of an assembly including the power semiconductor module  100  as shown in  FIG. 1  mounting a printed circuit board  200  including user-specific gating electronics. Provided at the side of the printed circuit board  200  facing away from the power semiconductor module  100  is an optional pressure plate  300  ensuring even distribution of the pressure on the printed circuit board  200  and power semiconductor module  100  when the composite of power semiconductor module  100 , printed circuit board  200  and pressure plate  300  is screwed to a heatsink (not shown) for which the pressure plate  300  comprises a mounting hole  353  aligned with the mounting hole  53  of the power semiconductor module  100 . 
         [0036]    Referring now to  FIG. 3  there is illustrated an exploded view of the assembly as shown in  FIG. 2 , evident being how the module housing  104  of the power semiconductor module  100  comprises a housing frame  105  as well as a flange  54  optionally integrated with the housing frame  105 . Formed by the housing frame  105  and flange  54  are two recesses  106  at the underside of the housing frame  105 , into each of which one of the substrates T 1  and T 2  is inserted. 
         [0037]    As shown, the module housing  104  may comprise an optional housing cover  103  covering at least the power semiconductor chips  120 . One such optional housing cover  103  is configured so that the electrical terminals  110  are accessible from the outer side of the power semiconductor module  100  after the housing cover  103  is located on the housing frame  105 . For this purpose, the terminals  110  can be routed to side-step the edge of the housing cover  103  or brought out through holes in the housing cover  103 . 
         [0038]    The printed circuit board  200  may comprise an electrical gating circuit (not shown in  FIG. 3 ) serving to gate the power semiconductor module  100 . The electrical components that may be used for this purpose can be arranged on the underside facing the power semiconductor module  100  and/or topside of the printed circuit board  200  facing away from the power semiconductor module  100 . In addition, the printed circuit board  200  comprises a fastener hole  253  configured, for example—relative to the underside  102  of the power semiconductor module  100 —as a central fastener hole aligned with the mounting hole  53  of the power semiconductor module  100  and the mounting hole  353  of the pressure plate  300  when correctly mounted. 
         [0039]    The printed circuit board  200  and terminals  110  are adapted to each other so that the gating circuit realized on the printed circuit board  200  is properly circuited with the terminals  110  when the printed circuit board  200  is mounted on the power semiconductor module  100 . 
         [0040]    As is also evident from  FIG. 3  the pressure plate  300  may comprise not just one, but several components  301 ,  302 . 
         [0041]    Referring now to  FIG. 4  there is illustrated a portion of a power semiconductor module  100  including three substrates spaced from each other T 1 , T 2 , T 3  connected in series featuring parallel side edges  71 ,  72 ,  73 ,  74 . Disposed between two each adjacent substrates T 1 /T 2  or T 2 /T 3  of the substrates T 1 , T 2 , T 3  is a flange  54  optionally integrated including a housing frame (not shown). These flanges  54 —like the housing frame—may be engineered in plastics, for example. In an alternative aspect the underside of the housing frame may also be formed by a printed circuit board incorporating the recesses  106  (see  FIG. 3 ). In this configuration, the flange  54  may also be configured as a portion of one such printed circuit board. 
         [0042]    Each flange  54  features a mounting hole  53  by means of which the power semiconductor module  100  can be screwed to a heatsink. Topping each mounting hole  53  and arranged on each corresponding flange  54  is a cylindrical ring which may be configured integral with the corresponding flange  54  in serving to prevent weeping of a potting compound through the corresponding mounting hole  53  when the module  100  is potted. 
         [0043]    To electrically conductively connect the circuits realized on the substrates T 1 , T 2  and T 3  as needed, electrical bonds may be provided so that adjacent substrates T 1 /T 2  or T 2 /T 3  are electrically bonded over the interposed flange  54 . One such bonding element may be configured, for example, as a metallic clip  58  soldered or welded to the topside metallization  55  of the corresponding substrates T 1  and T 2  or as a bond wire  59  bonded at the topside metallization  55  of the adjacent substrates T 2  and T 3  to be electrically conductively connected. 
         [0044]    Referring now to  FIG. 5  there is illustrated a view in perspective of a portion of a power semiconductor module  100  including two substrates spaced from each other T 1  and T 2  between which a flange  54  is disposed as described above mounting an optional printed circuit board  60  which in one embodiment may serve as a support module for bonding adjacent substrates T 1  and T 2  componented where required with electrical components  61  interconnected via the printed circuit board  60 . The printed circuit board  60  may be electrically bonded, for example, —as shown—by means of bond wires  62  to the substrates T 1  and T 2  bordering the flange  54 . 
         [0045]    As an alternative or in addition thereto it is possible that the printed circuit board  60  is electrically bonded to one or more of the terminals  110  in bonding the printed circuit board  60  by means of bond wires or other electrical bonding means to one or more of the terminals  110 . 
         [0046]    Referring now to  FIG. 6  there is illustrated a vertical section through an assembly basically the same as shown in  FIGS. 2 and 3  comprising in sequence a heatsink  400 , a power semiconductor module  100 , a printed circuit board  200  and a pressure plate  300 . These components are aligned so that a mounting hole  353  of the pressure plate  300  is in line with fastener hole  253  of the printed circuit board  200  and mounting hole  53  of the power semiconductor module  100  as well as including a tapped hole  453  of the heatsink  400  so that the individual components can be joined together in the sequence as shown by means of a fastener  500  configured, for example, as a screw. To optimize the thermal contact between the underside  102  of the power semiconductor module  100  and the topside  401  of the heatsink  400  a thermal transfer medium  140 , for example a thermal compound, may be applied to the underside  102  of the power semiconductor module  100  and/or topside  401  of the heatsink  400 . 
         [0047]    The terminals  110  used in the power semiconductor module  100  as shown are, for example, press-in contacts, the ends of which protruding from the module housing  104  are pressed into corresponding holes  210  of the printed circuit board  200  to electrically bond the printed circuit board  200  and via the patterning of the tracks to the gating circuit. Not shown in  FIG. 6  is how the printed circuit board  200  is componented. 
         [0048]    The substrates T 1  and T 2  each comprise at their topsides  51  a metallization  55  which may be patterned, as well as at their undersides  52  an optional underside metallization  57 . Each of the substrates T 1  and T 2  features the metallization  55  as well as the optionally underside metallization  57  applied to an insulator  56 , for example, a ceramic platelet made, for example, of aluminum oxide, silicon nitride or aluminum nitride ceramic whilst the substrates T 1  and T 2  may be configured as direct copper bonding (DCB), direct aluminum bonding (DAB) or active metal brazing (AMB) substrates. 
         [0049]    Referring now to  FIG. 7  there is illustrated how the assembly as shown therein differs from the assembly as shown in  FIG. 6  in that the power semiconductor module  100  comprises terminals  110  configured as spring contacts for pressure-contacting the power semiconductor module  100  to the corresponding contact pad  211  of the printed circuit board  200 . 
         [0050]    Referring now to  FIG. 8  there is illustrated a circuit diagram of a power semiconductor module  100  featuring two controllable power semiconductor switches S 1 H and S 1 L whose load circuits are connected in series to a half-bridge  1  comprising for feeding a positive power supply voltage +U B  and a negative power supply voltage −U B  a top terminal and bottom terminal respectively. 
         [0051]    In keeping with the present application as regards two controllable power semiconductor switches S 1 H and S 1 L intercircuited into a half-bridge, the controllable power semiconductor switch S 1 H nearest to the contact for the supply of the positive power supply voltage +U B  is termed a high-side switch and the controllable power semiconductor switch S 1 L nearest to the contact for the supply of the negative power supply voltage −U B  is termed a low-side switch. 
         [0052]    Optionally a free-wheeling diode D 1 H and D 1 L can be connected in antiparallel to each controllable power semiconductor switch S 1 H and S 1 L respectively. The designation of the controllable power semiconductor switches and free-wheeling diodes as used in the present application is in accordance with the following systematics: 
         [0053]    The first term “S” designates a controllable power semiconductor switch, and “D” a diode. The number following as the second term (in the present example the “1”) corresponds to the number of the half-bridge. An “H” as the third term means that the component involved is a “high-side component”, i.e., a component arranged at the side of the half-bridge contact provided to supply the positive power supply voltage +U B  whilst an “L” as the third term means a low-side component, i.e., arranged at the side of the contact provided to supply the negative power supply voltage −U B.    
         [0054]    A controllable power semiconductor switch S 1 H, S 1 L in the sense of the present application is understood as a logic unit realized either by means of exactly just one power semiconductor chip or, however, by means of two or more power semiconductor chips connected in parallel. One such power switch realized by means of exactly just one power semiconductor chip is termed a single switch in the following. 
         [0055]    Referring again to  FIG. 8  there is illustrated an assembly in which each of the controllable power semiconductor switches S 1 H and S 1 L is arranged on its own substrate T 1  and T 2  respectively located spaced from each other in the power semiconductor module  100 . In  FIG. 8 , the same as in the subsequent Figures, the various substrates spaced from each other T 1 , T 2  and where necessary T 3  of a power semiconductor module are depicted by broken lines, i.e., all components S 1 H, D 1 H or S 1 L, D 1 L depicted boxed by a broken line are sited on the substrates T 1  and T 2  respectively corresponding to the broken line. This does not apply, however, to the conductor tracks and circuit nodes likewise represented. 
         [0056]    Referring now to  FIG. 9  there is illustrated a circuit diagram of another power semiconductor module  100  comprising three substrates spaced from each other T 1 , T 2  and T 3  on each of which a half-bridge  1 ,  2  and  3  respectively is arranged. Each of these half-bridges  1 ,  2  and  3  comprises a controllable high-side power semiconductor switch S 1 H, S 2 H and S 3 H and a controllable low-side power semiconductor switch S 1 L, S 2 L and S 3 L respectively. In each of the half-bridges  1 ,  2  and  3  the load circuit of the corresponding controllable high-side power semiconductor switch is connected in series to the load circuit of the corresponding controllable low-side power semiconductor switch. Optionally a free-wheeling diode D 1 H, D 2 H, D 3 H, D 1 L, D 2 L and D 3 L respectively can be circuited antiparallel to the load circuit of each controllable power semiconductor switch S 1 H, S 2 H, S 3 H, S 1 L, S 2 L and S 3 L respectively. Each of these free-wheeling diodes is arranged on the same substrate T 1 , T 2  and T 3  as the corresponding controllable power semiconductor switch whose load circuit features the corresponding free-wheeling diode circuited in antiparallel. 
         [0057]    The half-bridges  1 ,  2 ,  3  can be optionally connected in parallel to permit a common supply of a positive power supply voltage +U B  and a negative power supply voltage −U B.    
         [0058]    Referring now to  FIG. 10  there is illustrated a circuit diagram of a power semiconductor module  100  comprising three half-bridges  1 ,  2 ,  3  which may be circuited just the same as the three half-bridges  1 ,  2 ,  3  as shown in  FIG. 9 . The power semiconductor module  100  as shown in  FIG. 10  differs from that as shown in  FIG. 9  by a different assembly of the controllable power semiconductor switches and the corresponding optional free-wheeling diodes. In the power semiconductor module  100  as shown in  FIG. 10  the controllable high-side power semiconductor switches S 1 H, S 2 H, S 3 H of all half-bridges  1 ,  2 ,  3  are arranged on a substrate T 1  and all controllable low-side power semiconductor switches S 1 L, S 2 L and S 3 L of the half-bridges  1 ,  2 ,  3  on another substrate T 2  separate from the substrate T 1 . 
         [0059]    Optionally a free-wheeling diode D 1 H, D 2 H, D 3 H, D 1 L, D 2 L and D 3 L respectively may be circuited in antiparallel to the load circuit of each controllable power semiconductor switches S 1 H, S 2 H, S 3 H, S 1 L, S 2 L and S 3 L and arranged on the same substrates T 1  and T 2  respectively the same as the controllable power semiconductor switches S 1 H, S 2 H, S 3 H, S 1 L, S 2 L and S 3 L belonging to the corresponding free-wheeling diode D 1 H, D 2 H, D 3 H, D 1 L, D 2 L and D 3 L. 
         [0060]    Referring now to  FIG. 11  there is illustrated a circuit diagram of a power semiconductor module  100  including a half-bridge  2  the controllable low-side power semiconductor switch S 2 L of which is arranged on a first substrate T 1  and the controllable high-side power semiconductor switch S 2 H of which is arranged on a second substrate T 2  spaced from the first substrate T 1 . 
         [0061]    Furthermore, the second half-bridge  2  comprises an optional high-side diode DH connected in series to the load circuit of the controllable low-side power semiconductor switch S 2 L and which is arranged on the first substrate T 1 . Correspondingly the half-bridge  2  comprises a low-side diode DL connected in series to the load circuit of the controllable high-side power semiconductor switch S 2 H and which is arranged on the second substrate T 2 . The high-side diode DH is arranged on the first substrate T 1  and the low-side diode DL on the second substrate T 2 . 
         [0062]    Furthermore, arranged on the first substrate T 1  is an optional further half-bridge  1  including controllable power semiconductor switches S 1 H and S 1 L as well as free-wheeling diodes D 1 H and D 1 L and correspondingly an optional half-bridge  3  including controllable power semiconductor switches S 3 H and S 3 L as well as free-wheeling diodes D 3 H and D 3 L is arranged on the second substrate T 2 . 
         [0063]    Referring now to  FIG. 12  there is illustrated a circuit diagram of a power semiconductor module  100  including a half-bridge  1  the controllable power semiconductor switch S 1 H of which comprises two controllable single power semiconductor switches S 1 H 1  and S 1 H 2  connected in parallel and the controllable low-side power semiconductor switch S 1 L of which comprises two controllable single power semiconductor switches S 1 L 1  and S 1 L 2  connected in parallel. The controllable single power semiconductor switches S 1 H 1  and S 1 L 1  are realized as power semiconductor chips and arranged on a first substrate T 1 . Correspondingly, the controllable single switches S 1 H 2  and S 1 L 2  are also realized as power semiconductor chips but arranged on a second substrate T 2  spaced from the second substrate T 1 . 
         [0064]    As shown, every controllable high-side power semiconductor switch S 2 H, S 3 H of the second half-bridge  2  and third half-bridge  3  and every controllable low-side power semiconductor switch S 2 L, S 3 L of the second half-bridge  2  and third half-bridge  3  can be formed by a parallel circuit of two or more controllable power semiconductor switches S 2 H 1  in parallel with S 2 H 2 , S 3 H 1  in parallel with S 3 H 2 , S 2 L 1  in parallel with S 2 L 2  or S 3 L 1  in parallel with S 2 L 2 . 
         [0065]    Referring now to  FIG. 13  there is illustrated a circuit diagram of a power semiconductor module  100  comprising three half-bridges  1 ,  2 ,  3  intercircuited the same as described with reference to  FIG. 10  and which may be arranged separate on two substrates T 1  and T 2 , in addition to which a third substrate T 3  is provided spaced from the substrates T 1  and T 2 . Arranged on the third substrate T 3  is a bridge rectifier circuit  4  realized, for example, by means of diodes D. The bridge rectifier circuit  4  serves to rectify an at least two-phase alternating current. The bridge rectifier circuit  4  comprises for each phase a series circuit of R 1 , R 2  and R 3  each including a series circuit of two diodes D. These series circuits R 1 , R 2  and R 3  are connected in parallel to thus provide an intermediate circuit voltage between two outputs  41  and  42  of the bridge rectifier circuit  4 . 
         [0066]    Arranged on the third substrate T 3  is in addition a brake chopper circuit  5  comprising a controllable power semiconductor switch SW featuring connected in series to its load circuit a diode DW. 
         [0067]    Referring now to  FIG. 14  there is illustrated a circuit diagram of a power semiconductor module  100  different from that as shown in  FIG. 13  in that the half-bridges  1 ,  2 ,  3  are now arranged on a common substrate T. 
         [0068]    Referring now to  FIGS. 15 and 16  it will now be explained how one or more mounting holes  53  of a power semiconductor module  100  may be arranged in relation to two or more substrates T 1 , T 2  and T 3  respectively of the module  100  with reference to examples shown diagrammatically. 
         [0069]    The assembly as shown in  FIG. 15  shows two substrates spaced from each other T 1  and T 2 . The module  100  comprises a single mounting hole  53  arranged in the middle between the substrates T 1  and T 2 . 
         [0070]    Correspondingly, the assembly as shown in  FIG. 16  shows three substrates spaced from each other T 1 , T 2  and T 3 , the power semiconductor module  100  here comprising two mounting holes  53  each arranged in the middle between a pair of adjacent substrates T 1  and T 2  respectively T 2  and T 3 . 
         [0071]    It is understood that in any power semiconductor module  100  having a number N 1  of substrates T 1 , T 2 , T 3  and a number N 2  of mounting hole  53  the ratio N 2 :N 1  may be generally selected, for example, smaller than 1 or smaller than ⅔. 
         [0072]    Although various examples to realize the invention have been disclosed, it will be apparent to those skilled in the art that various changes and modifications can be made which will achieve some of the advantages of the invention without departing from the spirit and scope of the invention. It will be obvious to those reasonably skilled in the art that other components performing the same functions may be suitably substituted. Such modifications to the inventive concept are intended to be covered by the appended claims. Unless the features of the appended claims do not exclude each other, these features may be combined in an arbitrary manner.