Abstract:
A method and apparatus configures the data bits of partially defective memory devices in order to construct usable memory chip or module packages that meet the specification of a fully or partially functional package.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to semiconductor memory devices, memory chips, memory modules, and the handling of defective memory components. 
     Due to the yield limitation of semiconductor fabrication process, a semiconductor memory wafer usually contains defective memory devices. These defective memory devices are declared as unusable because the defects within the device are beyond the repairing capability of the device fabrication process. 
     We may categorize the types of defective memory devices by the defective data bit positions. For a memory device with eight data bits, there are 255 types of defective memory devices. The large number of defective memory types further complicates the issue regarding to the handling, sorting, and packaging of these memory devices. 
     BRIEF SUMMARY OF THE INVENTION 
     This invention proposes a method and apparatus to utilize partially defective memory devices to construct usable memory chip or module packages that meet the specification of a functional package. 
     This invention provides a method that maximizes the usage of non-defective memory data bits in the partially defective memory devices. 
     The present invention provides a method that reduces the complexity in the chip and module packaging, sorting, and handling. 
     This invention further provides a method to reduce the large number of defective memory device types. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram of a prior art memory chip. 
     FIG. 2 shows a preferred embodiment of the present invention for a memory chip package. 
     FIG. 3 shows another preferred embodiment of the present invention for a memory chip package. 
     FIG. 4 shows a third preferred embodiment of the present invention for a memory chip package. 
     FIG. 5 shows a preferred embodiment of the present invention for a memory chip package with two memory devices. 
     FIG. 6 shows another preferred embodiment of the present invention for a memory chip package with two memory devices. 
     FIG. 7 is a diagram of a prior art memory module. 
     FIG. 8 shows a preferred embodiment of the present invention for a memory module package. 
     FIG. 9 shows a preferred embodiment for a portion of the memory module package in FIG.  8 . 
     FIG. 10 shows another preferred embodiment of a portion for the memory module package in FIG.  8 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention will be illustrated with some preferred embodiments. 
     FIG. 1 is a diagram of a prior art memory chip. The memory device  101  contains device data bit points  102 , a memory address control unit  103 , and a memory cell array  104 . The device data bit points  102  are connected to the corresponding chip data bit points  105 . 
     FIG. 2 shows a preferred embodiment of the present invention for a memory chip package. In memory device  201 , the memory cell array  202  contains defective memory cells within memory blocks  203 ,  204 ,  205 , and  206 . 
     The memory data bits corresponding to device data bit points  211 ,  213 ,  214 ,  216  and  217  are marked as functional because they do not contain any defective memory blocks. These data bit points are mapped onto chip data bit points  220 ,  221 ,  222 ,  223 , and  224 , each with a connecting mechanism. In this preferred embodiment, the connecting mechanisms are metal wires during a wire bonding process. 
     The memory data bits corresponding to device data bit points  210 ,  212 , and  215  are marked as defective because they contain at least one defective memory blocks. These data bit points are mapped onto chip data bit points  225 ,  226 , and  227 , each with a disconnecting mechanism. In this preferred embodiment, the disconnecting mechanisms are open circuit conditions without any wire connections. 
     FIG. 3 shows another preferred embodiment of the present invention for a memory chip package. In memory device  301 , the memory cell array  302  contains defective memory cells within memory blocks  303 ,  304 ,  305 ,  306 , and  307 . 
     The memory data bits corresponding to device data bit points  310 ,  312 , and  315  are marked as functional because they do not contain any defective memory blocks. These data bit points are mapped onto chip data bit points  325 ,  326 , and  327 , each with a connecting mechanism. In this preferred embodiment, the connecting mechanisms are metal wires during a wire bonding process. 
     The memory data bits corresponding to device data bit points  311 ,  313 ,  314 ,  316  and  317  are marked as defective because they contain at least one defective memory blocks. These data bit points are mapped onto chip data bit points  320 ,  321 ,  322 ,  323 , and  324 , each with a disconnecting mechanism. In this preferred embodiment, the disconnecting mechanisms are open circuit conditions without any wire connections. 
     FIG. 4 shows a third preferred embodiment of the present invention for a memory chip package. In memory device  401 , the memory cell array  402  contains defective memory cells within memory blocks  403 ,  404 ,  405 , and  406 . 
     The memory data bits corresponding to device data bit points  411 ,  413 ,  414 ,  416  and  417  are marked as functional because they do not contain any defective memory blocks. These data bit points are mapped onto chip data bit points  421 ,  423 ,  424 ,  426 , and  427 , each with a connecting mechanism. In this preferred embodiment, the connecting mechanisms are metal wires during a wire bonding process. 
     The memory data bits corresponding to device data bit points  410 ,  412 , and  415  are marked as defective because they contain at least one defective memory blocks. These data bit points are mapped onto chip data bit points  420 ,  422 , and  425 , each with a disconnecting mechanism. In this preferred embodiment, the disconnecting mechanisms are open circuit conditions without any wire connections. 
     FIG. 5 shows a preferred embodiment of the present invention for a memory chip package with two memory devices. The data bit mapping element  501  maps the device data bit points  502  of the memory device  503  to selected package data bit points  504  using a mapping structure similar to FIG.  2 . It also maps the device data bit points  505  of the memory device  506  to remaining package data bit points using a mapping structure similar to FIG.  3 . 
     FIG. 6 shows a preferred embodiment of the present invention for a memory chip package with two memory devices. The data bit mapping element  601  maps the device data bit points  602  of the memory device  603  to selected package data bit points  604  using a mapping structure similar to FIG.  4 . It also maps the device data bit points  605  of the memory device  606  to remaining package data bit points using a similar mapping structure. 
     FIG. 7 is a diagram of a prior art memory module. The memory module data bit points  701  are connected to the corresponding chip data bit points of the memory device  702 . This combination constitutes a memory unit  703 . This memory module contains a total of eight memory units. The module is built on a printed circuit board  704  with an edge connection  705  to interface with other system components. 
     FIG. 8 shows a preferred embodiment of the present invention for a memory module package. The data bit mapping element  804  maps the chip data bit points of the first memory chip  802  and second memory chip  803  to the memory module data bit points  801 . This combination constitutes a memory unit  805 . This memory module contains a total of eight memory units. The module is built on a printed circuit board  806  with an edge connection  807  to interface with other system components. 
     FIG. 9 shows a preferred embodiment for a memory unit of the memory module package in FIG.  8 . The data bit mapping element  904  maps the chip data bit points of the first memory chip  902  and second memory chip  903  to the memory module data bit points  901 . 
     For the first memory chip  902 , the memory chip data bit points  920 ,  921 ,  922 ,  923 ,  924 ,  925 ,  926 , and  927  are mapped onto module data bit points  940 ,  941 ,  942 ,  943 ,  944 ,  945 ,  946 , and  947 , each with a connecting mechanism. In this preferred embodiment, the connecting mechanisms are low value resistors. However, only the memory chip data bit points  920 ,  921 ,  922 ,  923 , and  924  are mapped onto by device data bit points within the first memory chip  902  as illustrated in FIG.  2 . 
     For the second memory chip  903 , the memory chip data bit points  930 ,  931 ,  932 ,  933 ,  934 ,  935 ,  936 , and  937  are also mapped onto module data bit points  940 ,  941 ,  942 ,  943 ,  944 ,  945 ,  946 , and  947 , each with a connecting mechanism. In this preferred embodiment, the connecting mechanisms are low value resistors. However, only the memory chip data bit points  935 ,  936 , and  937  are mapped onto by device data bit points within the first memory chip  903  as illustrated in FIG.  3 . 
     FIG. 10 shows another preferred embodiment for a memory unit of the memory module package in FIG.  8 . The data bit mapping element  954  maps the chip data bit points of the first memory chip  952  and second memory chip  953  to the memory module data bit points  951 . 
     For the first memory chip  952 , the memory chip data bit points  971 ,  973 ,  974 ,  976  and  977  are mapped onto module data bit points  991 ,  993 ,  994 ,  996  and  997 , each with a connecting mechanism. In this preferred embodiment, the connecting mechanisms are low value resistors. The memory chip data bit points  970 ,  972 , and  975  are mapped onto module data bit points  990 ,  992 , and  995 , each with a disconnecting mechanism. In this preferred embodiment, the disconnecting mechanisms are open circuits without any connections. 
     For the second memory chip  953 , the memory chip data bit points  980 ,  982 , and  985  are mapped onto module data bit points  990 ,  992 , and  995 , each with a connecting mechanism. In this preferred embodiment, the connecting mechanisms are low value resistors. The memory chip data bit points  981 ,  983 ,  984 ,  986  and  987  are mapped onto module data bit points  991 ,  993 ,  994 ,  996  and  997 , each with a disconnecting mechanism. In this preferred embodiment, the disconnecting mechanisms are open circuits without any connections.