Abstract:
A universal logic module of a programmable semiconductor device is constructed by first, second, third, fourth and fifth terminals, a first transfer gate connected between the first and fourth terminals, a second transfer gate connected between the second and fourth terminals, and an inverter connected between the third and fifth terminals. The first and second transfer gates are controlled by voltages at the third and fifth terminals, so that one of the first and second transfer gates is turned ON and the other of the first and second transfer gates is turned OFF.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a programmable semiconductor device including universal logic modules.  
           [0003]    2. Description of the Related Art  
           [0004]    In a programmable semiconductor device such as a field programmable gate array (FPGA) device, a logic cell formed by a plurality of kinds of universal logic modules is provided. Then, the user performs a connection operation upon the logic cell to realize a desired user logic circuit.  
           [0005]    In a prior art programmable semiconductor device (see: JP-A-2002-198801), a logic cell is constructed by first universal logic modules serving as two-input, one-output multiplexers, second universal logic modules serving as inverters and a third universal logic module serving as a two-input, one-output multiplexer. Note that the third universal logic module has the same configuration as the universal logic modules except that an inverter having a large current driving ability is provided. Also, various kinds of user logic circuits can be made by the user using the first universal logic modules. This will be explained later in detail.  
           [0006]    In order to cope with as many user inverters as possible in the logic cell of the above-described prior art programmable semiconductor device, the number of second universal logic modules may be increased. In this case, however, if the ratio of the first universal logic modules, the second universal logic modules and the third universal logic modules is inappropriate due to the increased number of the second universal logic modules, the number of unused logic modules may be increased, which would increase a wasted area of the logic cell.  
           [0007]    Further, in the logic cell of the above-described prior art programmable semiconductor device, a user delay circuit can be realized by connecting a plurality of the second universal logic modules in series. In this case, however, long connections are required between the series of the second universal logic modules, so that a delay time of the user delay circuit is increased.  
           [0008]    Still further, since all the second universal logic modules are of the same type, a realized user inverter has the same driving power and the same delay time. As a result, various kinds of user inverters cannot be realized.  
         SUMMARY OF THE INVENTION  
         [0009]    It is an object of the present invention to provide a semiconductor device including a logic cell formed by universal logic modules capable of coping with as many user inverters as possible, providing a user delay circuit having a smaller delay time and providing a user inverter having various kinds of current driving abilities and various kinds of delay times.  
           [0010]    According to the present invention, a logic module of a programmable semiconductor device is constructed by first, second, third, fourth and fifth terminals, a first transfer gate connected between the first and fourth terminals, a second transfer gate connected between the second and fourth terminals, and an inverter connected between the third and fifth terminals. The first and second transfer gates are controlled by voltages at the third and fifth terminals, so that one of the first and second transfer gates is turned ON and the other of the first and second transfer gates is turned OFF. Thus, a user inverter using the above-mentioned inverter can be realized without the first and second transfer gates.  
           [0011]    Also, a logic module of a programmable semiconductor device is constructed by: first, second, third, fourth, fifth, sixth and seventh terminals; first and second connection/non-connection nodes capable of being either in a connection state or in a non-connection state; a first inverter connected between the first terminal and the first connection/non-connection terminal; a second inverter connected between the third terminal and the second connection/non-connection terminal; a third inverter connected between the fifth and seventh terminals; a first transfer gate connected between the first connection/non-connection node and the sixth terminal; and a second transfer gate connected between the second connection/non-connection node and the sixth terminal. The first and second transfer gates are controlled by voltages at the fifth and seventh terminals so that one of the first and second transfer gates is turned ON and the other of the first and second transfer gates is turned OFF. Thus, a user inverter using one of the first, second and third inverters can be realized without the first and second transfer gates. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]    The present invention will be more clearly understood from the description set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein:  
         [0013]    [0013]FIG. 1 is a circuit diagram illustrating a prior art programmable semiconductor device;  
         [0014]    [0014]FIGS. 2A, 2B,  2 C and  2 D are circuit diagrams illustrating user logic circuits realized by the universal logic module of FIG. 1;  
         [0015]    [0015]FIG. 3 is a circuit diagram illustrating a user inverter realized by the universal logic module of FIG. 1;  
         [0016]    [0016]FIG. 4 is a circuit diagram illustrating an embodiment of the programmable semiconductor device according to the present invention;  
         [0017]    [0017]FIGS. 5A and 5B are cross-sectional views of the connection/non-connection node of FIG. 4;  
         [0018]    [0018]FIGS. 6A, 6B,  6 C,  7 A,  7 B,  7 C,  8 ,  9 ,  10 A,  10 B,  10 C,  11 A,  11 B and  11 C are circuit diagrams illustrating user logic circuits realized by the universal logic module of FIG. 4; and  
         [0019]    [0019]FIGS. 12A, 12B,  12 C and  12 D are circuit diagrams illustrating modifications of the universal logic module of FIG. 4. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0020]    Before the description of the preferred embodiment, a prior art programmable semiconductor device will be explained with reference to FIG. 1 (see: JP-A-2002-198801).  
         [0021]    In FIG. 1, a logic cell is constructed by universal logic modules X 1  and X 2  serving as two-input, one-output multiplexers, universal logic modules Y 1  and Y 2  serving as inverters and a universal logic module Z serving as a two-input, one-output multiplexer. Note that the universal logic module Z has the same configuration as the universal logic modules X 1  and X 2  except that an inverter having a large current driving ability is provided.  
         [0022]    The logic cell of FIG. 1 has twenty terminals T 1  through T 20 . Therefore, the user performs a connection operation upon all or some of the terminals T 1  through T 20 , thus completing a desired user logic circuit.  
         [0023]    In more detail, the universal logic module X 1  is constructed by three CMOS inverters  1 ,  2  and  3  and two transfer gates  4  and  5  each formed by a P-channel MOS transistor and an N-channel MOS transistor. The transfer gates  4  and  5  are controlled by a voltage at the terminal T 5  and the output voltage of the inverter  3 , so that one of the transfer gates  4  and  5  is turned ON and the other is turned OFF.  
         [0024]    Various kinds of user logic circuits can be made by the user using the universal logic module X 1  as illustrated in FIGS. 2A, 2B,  2 C and  2 D.  
         [0025]    In FIG. 2A, the terminal T 1  is fixed at “0” (low level), and the terminals T 2  and T 4  are open. Also, input signals A and B are supplied to the terminals T 3  and T 5 , respectively, and an output signal Q is obtained from the terminal T 6 . Thus, a NAND circuit is realized.  
         [0026]    In FIG. 2B, the terminal T 3  is fixed at “1” (high level), and the terminal T 2  and T 4  are open. Also, input signals A and B are supplied to the terminals T 1  and T 5 , respectively, and an output signal Q is obtained from the terminal T 6 . Thus, a NOR circuit is realized.  
         [0027]    In FIG. 2C, the terminals T 2  and T 3  are short-circuited, and the terminal T 4  is open. Also, input signals A and B are supplied to the terminals T 1  and T 5 , respectively, and an output signal Q is obtained from the terminal T 6 . Thus, an exclusive OR circuit is realized.  
         [0028]    In FIG. 2D, the terminals T 1  and T 4  are short-circuited, and the terminal T 2  is open. Also, input signals A and B are supplied to the terminals T 3  and T 5 , respectively, and an output signal Q is obtained from the terminal T 6 . Thus, an exclusive NOR circuit is realized.  
         [0029]    On the other hand, a user inverter may be realized by the user using the universal logic module X 1  or X 2 . For example, in the universal logic module X 1 , as illustrated in FIG. 3, the terminal T 5  is fixed at “0” (low level), and the terminals T 2 , T 3  and T 4  are open. Also, an input signal A is supplied to the terminal T 1 , and an output signal Q is obtained from the terminal T 6 . In this case, however, a large delay time is generated due to the presence of the transfer gate  4 . Therefore, the universal logic modules Y 1  and Y 2  are provided in the logic cell of FIG. 1 specialized for forming user inverters.  
         [0030]    Also, in order to cope with as many user inverters as possible in the logic cell of FIG. 1, the number of the universal logic modules such as Y 1  and Y 2  may be increased. In this case, however, if the ratio of universal logic modules such as X 1  and X 2 , universal logic modules such as Y 1  and Y 2  and universal logic modules such Z is inappropriate due to the increased number of the universal logic modules such as Y 1  and Y 2 , the number of unused logic modules may be increased, which world increase a wasted area of the logic cell.  
         [0031]    Further, in the logic cell of FIG. 1, a user delay circuit can be realized by connecting a plurality of the universal logic modules such as Y 1  and Y 2  in series. In this case, however, long connections are required between the series of the universal logic modules such as Y 1  and Y 2 , so that a delay time of the user delay circuit is increased.  
         [0032]    Still further, since all the universal logic modules such as Y 1  and Y 2  for inverters are of the same type, a realized user inverter has the same driving power and the same delay time. As a result, various kinds of user inverters cannot be realized.  
         [0033]    In FIG. 4, which illustrates an embodiment of the programmable semiconductor device according to the present invention, the universal logic modules X 1  and X 2  of FIG. 1 are replaced by universal logic modules X 1 ′ and X 2 ′, respectively.  
         [0034]    In the universal logic module X 1 ′ (X 2 ′), a terminal T 21  (T 22 ) and connection/non-connection nodes N 1  and N 2  (N 3  and N 4 ) are added to the elements of the universal logic module X 1  (X 2 ) of FIG. 1.  
         [0035]    The connection/non-connection node N 1  will be explained next with reference to FIGS. 5A and 5B, which are partial cross-sectional views of the programmable semiconductor device of FIG. 4.  
         [0036]    In FIG. 5A, conductive layers  51   a  and  51   b  are connected to the inverter  1  (the terminal T 2 ) and the transfer gate  4 , respectively. Also, an insulating layer  52  is formed on the conductive layers  51   a  and  51   b , and via structures  53   a  and  53   b  are formed through the insulating layer  52  on the conductive layers  51   a  and  51   b , respectively. Further, a conductive layer  54  is formed on the via structures  53   a  and  53   b , so that the conductive layer  51   a  is electrically connected to the conductive layer  51   b , i.e., the node N 1  is in a connection state.  
         [0037]    On the other hand, if an etching operation or a trimming operation is performed on the conductive layer  54 , the entirety of the conductive layer  54  is removed as illustrated in FIG. 5B, so that the conductive layer  51   a  is electrically disconnected from the conductive layer  51   b , i.e., the node N 1  is in a non-connection state. In this case, note that a part of the conductive layer  54  can be removed.  
         [0038]    Thus, the node N 1  (N 2 , N 3  and N 4 ) can be either in a connection state or in a non-connection state.  
         [0039]    The user logic circuits as illustrated in FIGS. 2A, 2B,  2 C and  2 D can be realized by the user using the universal logic module X 1 ′ under the condition that the nodes N 1  and N 2  are in a connection state and the terminal T 21  is open, in the same way as in the universal logic module X 1 .  
         [0040]    Also, various kinds of inverters and delay circuits can be made by the user using the universal logic module X 1 ′ as illustrated in FIGS. 6A, 6B,  6 C,  7 A,  7 B,  7 C,  8 ,  9 ,  10 A,  10 B,  10 C,  11 A,  11 B and  11 C.  
         [0041]    One inverter is realized by the universal logic module X 1 ′ as illustrated in FIGS. 6A, 6B and  6 C.  
         [0042]    In FIG. 6A, the terminal T 3  is fixed at “0” (low level) or “1” (high level), and the terminals T 4 , T 5 , T 6  and T 21  are open. Also, an input signal A is supplied to the terminal T 1 , and an output signal Q 1  is obtained from the terminal T 2 . Further, the node N 1  is in a non-connection state, while the node N 2  is in a connection state. Thus, one inverter using the inverter  1  is realized. In this case, since no transfer gate is present between the terminals T 1  and T 2 , the realized inverter has a higher current driving ability and a smaller delay time as compared with an inverter realized by the universal logic module X 1  of FIG. 1.  
         [0043]    In FIG. 6B, the terminal T 1  is fixed at “0” (low level) or “1” (high level), and the terminals T 2 , T 5 , T 6  and T 21  are open. Also, an input signal B is supplied to the terminal T 3 , and an output signal Q 2  is obtained from the terminal T 4 . Further, the node N 1  is in a connection state, while the node N 2  is in a non-connection state. Thus, one inverter using the inverter  2  is realized. In this case, since no transfer gate is present between the terminals T 3  and T 4 , the realized inverter has a higher current driving ability and a smaller delay time as compared with an inverter realized by the universal logic module X 1  of FIG. 1.  
         [0044]    In FIG. 6C, the terminals T 1  and T 3  are fixed at “0” (low level) or “1” (high level), and the terminals T 2 , T 4 , and T 6  are open. Also, an input signal C is supplied to the terminal T 5 , and an output signal Q 3  is obtained from the terminal T 21 . Further, the nodes N 1  and N 2  are in a non-connection state. Thus, one inverter using the inverter  3  is realized. In this case, since no transfer gate is present between the terminals T 5  and T 21 , the realized inverter has a higher current driving ability and a smaller delay time as compared with an inverter realized by the universal logic module X 1  of FIG. 1.  
         [0045]    Two inverters are realized by the universal logic module X 1 ′ as illustrated in FIGS. 7A, 7B and  7 C.  
         [0046]    In FIG. 7A, the terminals T 5 , T 6  and T 21  are open. Also, input signals A and B are supplied to the terminals T 1  and T 3 , respectively, and output signals Q 1  and Q 2  are obtained from the terminals T 2  and T 4 , respectively. Further, the nodes N 1  and N 2  are in a non-connection state. Thus, two inverters using the inverters  1  and  2  are realized. In this case, since no transfer gate is present between the terminals T 1  and T 2  and between the terminals T 3  and T 4 , each of the realized inverters has a higher current driving ability and a smaller delay time as compared with an inverter realized by the universal logic module X 1  of FIG. 1.  
         [0047]    In FIG. 7B, the terminal T 3  is fixed at “0” (low level) or “1” (high level), and the terminals T 4  and T 6  are open. Also, input signals A and C are supplied to the terminals T 1  and T 5 , respectively, and output signals Q 1  and Q 3  are obtained from the terminals T 2  and T 21 , respectively. Further, the node N 1  is in a non-connection state, while the node N 2  is in a connection state. Thus, two inverters using the inverters  1  and  3  are realized. In this case, since no transfer gate is present between the terminals T 1  and T 2  and between the terminals T 5  and T 21 , each of the realized inverters has a higher current driving ability and a smaller delay time as compared with an inverter realized by the universal logic module X 1  of FIG. 1.  
         [0048]    In FIG. 7C, the terminal T 1  is fixed at “0” (low level) or “1” (high level), and the terminals T 2  and T 6  are open. Also, input signals B and C are supplied to the terminals T 3  and T 5 , respectively, and output signals Q 2  and Q 3  are obtained from the terminals T 4  and T 21 , respectively. Further, the node N 1  is in a connection state, while the node N 2  is in a non-connection state. Thus, two inverters using the inverters  2  and  3  are realized. In this case, since no transfer gate is present between the terminals T 3  and T 4  and between the terminals T 5  and T 21 , each of the realized inverters has a higher current driving ability and a smaller delay time as compared with an inverter realized by the universal logic module X 1  of FIG. 1.  
         [0049]    In FIGS. 7A, 7B and  7 C, since two inverters are provided in the universal logic module X 1 ′, the integration can be enhanced.  
         [0050]    Three inverters are realized by the universal logic module X 1 ′ as illustrated in FIG. 8.  
         [0051]    In FIG. 8, the terminal T 6  is open. Also, input signals A, B and C are supplied to the terminals T 1 , T 3  and T 5 , respectively, and output signals Q 1 , Q 2  and Q 3  are obtained from the terminals T 2 , T 4  and T 21 , respectively. Further, the nodes N 1  and N 2  are in a non-connection state. Thus, three inverters using the inverters  1 ,  2  and  3  are realized. In this case, since no transfer gate is present between the terminals T 1  and T 2 , between the terminals T 3  and T 4  and between the terminals T 5  and T 21 , each of the realized inverters has a higher current driving ability and a smaller delay time as compared with an inverter realized by the universal logic module X 1  of FIG. 1.  
         [0052]    In FIG. 8, since three inverters are provided in the universal logic module X 1 ′, the integration can be enhanced.  
         [0053]    One inverter formed by three inverter elements is realized by the universal logic module X 1 ′ as illustrated in FIG. 9.  
         [0054]    In FIG. 9, the terminal T 2  is connected to the terminal T 3 , and the terminal T 4  is connected to the terminal T 5 . Also, the terminal T 6  is open. Also, an input signal A is supplied to the terminal T 1 , and an output signal Q 3  is obtained from the terminal T 21 . Further, the nodes N 1  and N 2  are in a non-connection state. Thus, one inverter using the series of the inverters  1 ,  2  and  3  is realized. In this case, since no transfer gate is present between the terminals T 1  and T 21 , the realized inverter has a higher current driving ability and a smaller delay time as compared with an inverter realized by the universal logic module X 1  of FIG. 1.  
         [0055]    A delay circuit (buffer circuit) is realized by the universal logic module X 1 ′ as illustrated in FIGS. 10A, 10B and  10 C.  
         [0056]    In FIG. 10A, the terminal T 2  is connected to the terminal T 3 , and the terminals T 5 , T 6  and T 21  are open. Also, an input signal A is supplied to the terminal T 1 , and an output signal Q 2  is obtained from the terminal T 4 . Further, the nodes N 1  and N 2  are in a non-connection state. Thus, a delay circuit using the inverters  1  and  2  is realized. In this case, since no transfer gate is present between the terminals T 1  and T 4 , the realized delay circuit has a high current driving ability.  
         [0057]    In FIG. 10B, the terminal T 2  is connected to the terminal T 5 . Also, the terminal T 3  is fixed at “0” (low level) or “1” (high level), and the terminals T 4  and T 6  are open. Also, an input signal A is supplied to the terminal T 1 , and an output signal Q 3  is obtained from the terminal T 21 . Further, the node N 1  is in a non-connection state, while the node N 2  is in a connection state. Thus, a delay circuit using the inverters  1  and  3  is realized. In this case, since no transfer gate is present between the terminals T 1  and T 3 , the realized delay circuit has a high current driving ability.  
         [0058]    In FIG. 10C, the terminal T 4  is connected to the terminal T 5 . The terminal T 1  is fixed at “0” (low level) or “1” (high level), and the terminals T 2  and T 6  are open. Also, an input signal B is supplied to the terminal T 3 , and an output signal Q 3  is obtained from the terminal T 21 . Further, the node N 1  is in a connection state, while the node N 2  is in a non-connection state. Thus, a delay circuit using the inverters  2  and  3  is realized. In this case, since no transfer gate is present between the terminals T 3  and T 21 , the realized delay circuit has a high current driving ability.  
         [0059]    A delay circuit (buffer circuit) as well as an inverter are realized by the universal logic module X 1 ′ as illustrated in FIGS. 10A, 10B and  10 C.  
         [0060]    In FIG. 11A, the terminal T 2  is connected to the terminal T 3 , and the terminals T 6  and T 21  are open. Also, input signals A and C are supplied to the terminals T 1  and T 5 , respectively, and output signals Q 2  and Q 3  are obtained from the terminals T 4  and T 21 , respectively. Further, the nodes N 1  and N 2  are in a non-connection state. Thus, a delay circuit using the inverters  1  and  2  and an inverter using the inverter  3  are realized. In this case, since no transfer gate is present between the terminals T 1  and T 4  and between the terminals T 5  and T 21 , each of the realized delay circuit and inverter has a high current driving ability.  
         [0061]    In FIG. 11B, the terminal T 2  is connected to the terminal T 5 . Also, the terminal T 6  is open. Also, input signals A and B are supplied to the terminals T 1  and T 3 , respectively, and output signals Q 2  and Q 3  are obtained from the terminals T 4  and T 21 , respectively. Further, the node N 1  is in a non-connection state, while the node N 2  is in a connection state. Thus, a delay circuit using the inverters  1  and  3  and an inverter using the inverter  2  are realized. In this case, since no transfer gate is present between the terminals T 1  and T 2  and between the terminals T 3  and T 4 , each of the realized delay circuit and inverter has a high current driving ability.  
         [0062]    In FIG. 11C, the terminal T 4  is connected to the terminal T 5 . The terminal T 6  is open. Also, input signals A and B are supplied to the terminals T 1  and T 3 , respectively, and output signals Q 1  and Q 3  are obtained from the terminals T 2  and T 21 , respectively. Further, the node N 1  is in a connection state, while the node N 2  is in a non-connection state. Thus, a delay circuit using the inverters  2  and  3  and an inverter using the inverter  1  are realized. In this case, since no transfer gate is present between the terminals T 3  and T 21  and between the terminal T 1  and T 2 , each of the realized delay circuit and inverter has a high current driving ability.  
         [0063]    In the above-described embodiment, if the inverters  1 ,  2  and  3  have different current driving abilities and different delay times from each other, a realized user inverter can have various current driving abilities and delay times.  
         [0064]    The present invention can be applied to a universal logic module as illustrated in FIGS. 12A, 12B,  12 C and  12 D. In FIG. 12A, the inverters  1  and  2 , the terminals T 1  and T 2  and the nodes N 1  and N 2  are removed from the universal logic module X 1 ′ of FIG. 4. In FIG. 12B, the terminals T 1  and T 2  and the nodes N 1  and N 2  are removed from the universal logic module X 1 ′ of FIG. 4. In FIG. 12C, the inverter  2 , the terminals T 1  and T 2  and the node N 1  and N 2  are removed from the universal logic module X 1 ′ of FIG. 4. In FIG. 12D, the inverter  1 , the terminals T 1  and T 2  and the nodes N 1  and N 2  are removed from the universal logic module X 1 ′ of FIG. 4. That is, in FIGS. 12A, 12B,  12 C and  12 D, at least one user inverter using the inverter  3  can be realized.  
         [0065]    As explained hereinabove, according to the present invention, many user inverters and delay circuits having different current driving abilities and delay times can be provided.