Abstract:
The present invention discloses a half-bridge LLC resonant converter with self-driven synchronous rectifiers, which utilizes a primary IC controller and a gate driver to drive the secondary synchronous rectifiers. In correspondence with the gate drive output voltages of the primary IC controller to the primary switch transistors, the gate driver for the secondary synchronous rectifiers comprises a differential transformer if the primary IC controller outputs two ground-referenced gate drive voltages, which cannot directly drive the primary switch transistors but can be imposed on the differential transformer; or comprises a DC shifter, a DC restorer and a differential transformer if the primary IC controller outputs two gate-source voltages, which can directly drive the primary switch transistors but cannot be imposed on the differential transformer. The drive voltages of the primary switch transistors are unipolar; however the drive voltage of the secondary synchronous rectifiers can be bipolar or unipolar. Under the valid operation mode, this converter can decrease the rectifier conduction losses to increase the power converter efficiency.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of Invention 
   The present invention relates to a half-bridge LLC resonant converter with self-driven synchronous rectifiers. 
   2. Related Art 
     FIG. 1  shows a circuit diagram of a prior art. An ideal transformer T 0  includes a primary winding N p  and two secondary windings N s . A primary circuit is connected to the N p  and a secondary circuit to the two N s . 
   The primary circuit includes a first switch transistor M 1 , a second switch transistor M 2  and an LLC resonant tank, which includes a magnetizing inductor L m , a resonant inductor L r  and a resonant capacitor C r . M 1  and M 2  are connected between an input voltage source V in  and a primary ground terminal in a half-bridge configuration, where the point at which M 1 , M 2  and the LLC resonant tank intersect is called a first node P, and the LLC resonant tank is connected between the first node P and the primary ground terminal. 
   It is emphatically noted that a practical transformer T 1  is equivalent to the integration of the ideal transformer T 0  including the N p  and the two N s , L m  and a leakage inductor, where L m  is in parallel with the N p , and the leakage inductor is in series with the parallel circuit of L m  and N p . L m  can be measured from the primary side with the two N s  open-circuited, and the leakage inductance can be measured from the primary side with the two N s  short-circuited. If the N p  and the two N s  of T 1  are wound with a sandwich structure, then an external L r  is necessary, but if the N p  and the two N s  of T 1  are wound on a slotted bobbin, then the L r  can be provided by the leakage inductance of T 1 . A transformer with a slotted bobbin is used in this example. 
   The secondary circuit includes a first rectifier diode D 1 , a second rectifier diode D 2  and an output capacitor C o . D 1  and D 2  are connected in a center-tapped common-cathode rectifier configuration between the two N s  and C o , where the two N s  are connected in a center-tapped configuration at the secondary ground terminal, and D 1  and D 2  are connected in a common-cathode rectifier configuration at the output voltage terminal with an output voltage V o . 
   For the convenience of illustration, the circuit parameters are defined as follows: f s  is the switching frequency of M 1  and M 2 , 
             f   r     =     1     2   ⁢   π   ⁢         L   r     ⁢     C   r                   
is the resonant frequency of L r  and C r ,
 
           n   =       N   p       N   s             
is the primary-to-secondary turns ratio of T 0 , V o  is the output voltage, and V or =nV o  is the reflected output voltage. Regarding the circuit variables, the reference polarities of the gate-source voltages v GS   M1 (t) and v GS   M2 (t) of M 1  and M 2 , the resonant capacitor voltage v C     r   (t), the primary voltage v p (t) and the secondary voltage v s (t) as well as the reference directions of the resonant inductor current i L     r   (t), the magnetizing inductor current i L     m   (t), the primary current i p (t) and the secondary current i s (t) are also shown in  FIG. 1 .
 
   According to the conditions of f s &lt;f r , f s =f r  and f s &gt;f r , the waveforms of v GS   M1 (t), v GS   M2 (t), i L     r   (t), i L     m   (t) and i s (t) are shown in  FIGS. 2   a ,  2   b  and  2   c  respectively. As shown in the figures, the waveforms of the first half period and the second half period are symmetrical, so only equivalent circuits and critical waveforms of the first half period are described and those of the second half period can be analogized using the symmetry. 
   Firstly, the physical meanings of t=t 0 , t=t 1 , t=t r  and t=t s  are interpreted as follows: t=t 0  is the time when a resonant period resumes, t=t 1  is the time when i L     r   (t) crosses 0, t=t r  is the time when i s (t) descends to 0 and t=t s  is the time when v GS   M1 (t) switches to 0. 
   Regardless of f s ≦f r  or f s &gt;f r , during the interval of t 0 ≦t≦t 1 , v GS   M1 (t)=0, v GS   M2 (t)=0, i L     r   (t)&lt;0 and i L     r   &gt;i L     m   (t). M 1  and M 2  are turned off, i L     r   (t) flows through the body diode of M 1 , i p (t)=i L     r   (t)−i L     m   (t)&gt;0 flows into the dotted terminal of N p , i s (t)=ni p &gt;0 flows out of the dotted terminal of N s , D 1  is turned on and D 2  is turned off. L m  does not participate in the resonance of L r  and C r  due to the clamp of V or , i L     r   (t) and i s (t) are quasi-sinusoidal waves and the rising slope of i L     m   (t) is equal to 
               V   or       L   m       .         
D 1  switches to on state at t=t 0  under zero-current-switching (ZCS), and M 1  switches to on state during t 0 ≦t≦t 1  under zero-voltage-switching (ZVS) and, more particularly, at t=t 1  under ZVS and ZCS, so the switching losses are reduced.
 
   Under the condition of f s ≦f r  (i.e. t r ≦t s ), i s (t) descends to 0 before M 1  turns off. The interval of t 1 ≦t≦t s  is divided into two subintervals t 1 ≦t≦t r  and t r ≦t≦t s . During the subinterval of t 1 ≦t≦t r , v GS   M1 (t)=V cc , V GS   M2 (t)=0, i L     r   (t)&gt;0 and i L     r   &gt;i L     m   (t). M 1  is turned on, M 2  is turned off, i L     r   (t) flows through the channel of M 1 , i p (t)&gt;0 flows into the dotted terminal of N p , i s (t)&gt;0 flows out of the dotted terminal of N s , D 1  is turned on and D 2  is turned off. L m  does not participate in the resonance of L r  and C r  due to the clamp of V or , i L     r   (t) and i s (t) are quasi-sinusoidal waves and the rising slope of i L     m   (t) is equal to 
               V   or       L   m       .         
D 1  switches to off state at t=t r  under ZCS. During the subinterval of t r ≦t≦t s , v GS   M1 (t)=V cc , v GS   M2 (t)=0, i L     r   (t)&gt;0 and i L     r   =i L     m   (t). M 1  is turned on, M 2  is turned off, i L     r   (t) flows through the channel of M 1 , i p (t)=0, i s (t)=0, both D 1  and D 2  are turned off. L m  participates the resonance of L r  and C r , and the rising slope of i L     r   (t) and i L     m   (t) is smaller than
 
               V   or       L   m       .         
Especially,
 
                     ⅆ       i     L   m       ⁡     (   t   )           ⅆ   t       &lt;       V   or       L   m         ⇒       v   s     ⁡     (   t   )         =           L   m     n     ⁢       ⅆ       i     L   m       ⁡     (   t   )           ⅆ   t         &lt;     V   o         ,         
D 1  is reverse-biased by the voltage difference between V o  and v s (t) to turn off, and D 2  switches to on state at t=t s  under ZCS.
 
   Under the condition of f s &gt;f r  (i.e. t r &gt;t s ), i s (t) descends to 0 after M 1  turns off. The interval t 1 ≦t≦t r  is divided into t 1 ≦t≦t s  and t s ≦t≦t r . During t 1 ≦t≦t s , v GS   M1 (t)=V cc , v GS   M2 (t)=0, i L     r   (t)&gt;0 and i L     r   (t)&gt;i L     m   (t). M 1  is turned on, M 2  is turned off, i L     r   (t) flows through the channel of M 1 , i p (t) flows into the dotted terminal of N p , i s (t) flows out of the dotted terminal of N s , D 1  is turned on and D 2  is turned off. L m  does not participate in the resonance of L r  and C r  due to the clamp of V or , i L     r   (t) and i s (t) are quasi-sinusoidal waves and the rising slope of i L     m   (t) is equal to 
               V   or       L   m       .         
During t s ≦t≦t r , v GS   M1 (t)=0, v GS   M2 (t)=0, i L     r   (t)&gt;0 and i L     r   &gt;i L     m   (t). Both M 1  and M 2  are turned off, i L     r   (t) flows through the body diode of M 2 , i p (t) flows into the dotted terminal of N p , i s (t) flows out of the dotted terminal of N s , D 1  is truned on and D 2  is turned off. L m  does not participate in the resonance of L r  and C r  due to the clamp of V or , i L     r   (t) and i s (t) are quasi-sinusoidal waves and the rising slope of i L     m   (t) is equal to V or /L m . Especially,
 
                 ⅆ       i     L   m       ⁡     (   t   )           ⅆ   t       =           V   or       L   m       ⇒       v   s     ⁡     (   t   )         =           L   m     n     ⁢       ⅆ       i     L   m       ⁡     (   t   )           ⅆ   t         =     V   o           ,         
D 1  remains on. i s (t=t r ) commutates from D 1  to D 2  at t=t r  under ZCS.
 
   This conventional converter benefits from lower switching losses due to ZVS and ZCS but suffers from higher conduction losses due to the diode rectifiers. To reduce the conduction losses, self-driven synchronous rectifiers (SRs) are proposed. The primary switch transistors and the secondary SRs are driven by an IC controller and a gate driver simultaneously. Conceptually, the IC controller can be a primary IC controller or a secondary IC controller. Practically, a primary IC controller has three advantages over a secondary IC controller: (1) easier to buy from the market, (2) easier to cooperate with a primary power factor corrector and (3) easier to realize the protection functions of the converter. Based on a primary IC controller, a cost-effective half-bridge LLC resonant converter with self-driven synchronous rectifiers is proposed. 
   SUMMARY OF THE INVENTION 
   According to an aspect of the present invention, a half-bridge LLC resonant converter with self-driven synchronous rectifiers uses a primary IC controller and a gate driver to drive the primary switch transistors and the secondary synchronous rectifiers. 
   In correspondence with the gate drive output voltages of the primary IC controller to the primary switch transistors, the gate driver of the secondary synchronous rectifiers comprises a differential transformer if the primary IC controller outputs two ground-referenced gate drive voltages, which should be followed by a drive module for driving the primary switch transistors; or further comprises a DC shifter and a DC restorer if the primary IC controller outputs two drive voltages referred to the sources of two primary switch transistors and these two voltages can directly drive the primary switch transistors. 
   The drive voltage of the primary switch transistors is unipolar, and the drive voltage of the secondary synchronous rectifiers can be bipolar or unipolar. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows a circuit diagram of a half-bridge LLC resonant converter according to a prior art. 
       FIGS. 2   a ,  2   b  and  2   c  show voltage and current waveforms for the conditions of f s &lt;f r , f s =f r  and f s &gt;f r  respectively. 
       FIGS. 3   a  and  3   b  show a circuit diagram and drive voltage waveforms of the first embodiment according to the present invention. 
       FIGS. 4   a  and  4   c  show a circuit diagram and drive voltage waveforms of the second embodiment according to the present invention. 
       FIGS. 4   b  and  4   c  show a circuit diagram and drive voltage waveforms of the third embodiment according to the present invention. 
       FIGS. 5   a  and  5   b  show a circuit diagram and drive voltage waveforms of the fourth embodiment according to the present invention. 
       FIGS. 6   a  and  6   c  show a circuit diagram and drive voltage waveforms of the fifth embodiment according to the present invention. 
       FIGS. 6   b  and  6   c  show a circuit diagram and drive voltage waveforms of the sixth embodiment according to the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Firstly, the effect of the relationship between the switching frequency and the resonant frequency on the converter operation is illustrated with the analyses of  FIG. 2   a  through  2   c.  Six exemplary circuit topologies according to the present invention are shown in  FIG. 3   a,    FIG. 4   a ,  FIG. 4   b ,  FIG. 5   a ,  FIG. 6   a  and  FIG. 6   b.    
   Under the condition of f s &lt;f r , during the interval of t r ≦t≦t s , the first switch transistor M 1  is turned on and the second switch transistor M 2  is turned off, so the first synchronous rectifier SR 1  is turned on and the second synchronous rectifier SR 2  is turned off. A reverse voltage resulting from the voltage difference between the output voltage V o  and the secondary voltage v s (t) is imposed on SR 1 . The reverse voltage imposed on the conducting SR 1  will cause a huge shoot-through current 
               i   st     ⁡     (   t   )       =         V   o     -       v   s     ⁡     (   t   )           R   on             
to burn down SR 1 , where R on  is the very small on-resistance of M 1 .
 
   Under the condition of f s &gt;f r , during the interval of t s ≦t≦t r , both M 1  and M 2  are turned off, so SR 1  and SR 2  are turned off. Even if the channel of SR 1  is cut off, i s (t)&gt;0 still can flow through the body diode of SR 1 , the converter still can operate safely. Therefore, all the embodiments according to the present invention are merely applicable to the condition of f s &gt;f r . 
   The voltage waveforms shown in  FIG. 3   b ,  FIG. 4   c ,  FIG. 5   b  and  FIG. 6   c  correspond to the six embodiments shown in  FIGS. 3   a ,  4   a ,  4   b ,  5   a ,  6   a  and  6   b . It is emphatically noted that M 1 , M 2 , SR 1  and SR 2  according to the present invention can be implemented with a p-channel metal oxide semiconductor field effect transistor (PMOS), an n-channel metal oxide semiconductor field effect transistor (NMOS), a p-type junction field effect transistor (p-JFET) or an n-type junction field effect transistor (n-JFET). For the convenience of illustration, it is assumed in this text that M 1 , M 2 , SR 1  and SR 2  are all implemented with NMOS. 
   Three exemplary embodiments are shown in  FIG. 3   a ,  FIG. 4   a  and  FIG. 4   b  when the primary IC controller U 1  outputs two ground-referenced drive voltages v B (t) and v A (t). The circuit diagram and drive voltage waveforms of the first embodiment according to the present invention are shown in  FIGS. 3   a  and  3   b , respectively. The ideal transformer T 0  comprises a primary winding N p  and two secondary windings N s . A primary circuit is connected to the N p  and a secondary circuit to the two N s . 
   The primary circuit includes a first switch transistor M 1 , a second switch transistor M 2  and an LLC resonant tank, which includes a magnetizing inductor L m , a resonant inductor L r  and a resonant capacitor C r . M 1  and M 2  are connected between an input voltage source V in  and a primary ground terminal in a half-bridge configuration, where the point at which M 1 , M 2  and LLC resonant tank intersect is called a first node P with a voltage V P , and the LLC resonant tank is connected between the first node P and the primary ground terminal. 
   It is emphatically noted that a practical transformer T 1  is equivalent to the integration of the ideal transformer T 0  including the N p  and the two N s , L m  and a leakage inductor, where L m  is in parallel with the N p , and the leakage inductor is in series with the parallel circuit of L m  and N p . L m  can be measured from the primary side with the two N s  open-circuited, and the leakage inductance can be measured from the primary side with the two N s  short-circuited. If the N p  and the two N s  of T 1  are wound with a sandwich structure, then an external L r  is necessary, but if the N p  and the two N s  of T 1  are wound on a slotted bobbin, then the L r  can be provided by the leakage inductance of T 1 . A transformer with a slotted bobbin is used in this example hereafter but it can be replaced by an ordinary transformer having a sandwich winding structure in series with an external L r . 
   When M 1  is turned on but M 2  is turned off, V P  is equal to V in , but when M 1  is turned off but M 2  is turned on, V P  is equal to 0. This means that the potential V P  is fluctuating. The output voltages v B (t) and v A (t) of U 1  are referred to the primary ground, so they cannot be directly used as the gate-source voltages v GS   M     1   (t) and v GS   M     2   (t) for M 1  and M 2 , especially for M 1 . In this case, an IC-based or a transformer-based driver module U 2  is needed to convert v B (t) and v A (t) referred to the primary ground into v GS   M     1   (t) and v GS   M     2   (t) referred to the sources to M 1  and M 2 . 
   The secondary circuit includes a first synchronous rectifier SR 1 , a second synchronous rectifier SR 2  and an output capacitor C o . SR 1  and SR 2  are connected in a center-tapped common-source rectifier configuration between the two N s  and the secondary ground terminal, where the two N s  are connected at the output voltage terminal and the common source of SR 1  and SR 2  is connected at the secondary ground terminal G. 
   SR 1  and SR 2  are driven by a differential transformer T 3 , which has a primary winding and two secondary windings as well as a 1:1:1 primary-to-secondary turns ratio, so a primary bipolar differential voltage v T     3   (t)=v B (t)−v A (t) of T 3  generates two secondary bipolar gate-source voltages v GS   SR     1   (t) and v GS   SR     2   (t) of SR 1  and SR 2 . v T     3   (t), v GS   SR     1   (t) and v GS   SR     2   (t) are listed in Table 1: 
   
     
       
             
             
             
           
         
             
               TABLE 1 
             
             
                 
             
             
               V T     3   (t) 
               V GS   SR     1   (t) 
               V GS   SR     2   (t) 
             
             
                 
             
           
           
             
               V cc   
               V cc   
               −V cc   
             
             
               0 
               0 
               0 
             
             
               −V cc   
               −V cc   
               V cc   
             
             
                 
             
           
        
       
     
   
   The corresponding voltage waveforms of v A (t), v B (t), v GS   M     1   (t), v GS   M     2   (t), v GS   SR     1   (t) and v GS   SR     2   (t) are shown in  FIG. 3   b.    
   A circuit diagram of the second embodiment according to the present invention is shown in  FIG. 4   a , where two half-wave rectifiers and two fast turn-off circuits are connected between the secondary windings of T 3  and the gates of SR 1  and SR 2 , respectively. One of the two half-wave rectifiers comprises a diode D 52  and a resistor R 5  for SR 1 , and the other a diode D 62  and a resistor R 6  for SR 2 . One of the two fast turn-off circuits comprises a diode D 51  and a PNP bipolar transistor Q 5  for SR 1 , and the other a diode D 61  and a PNP bipolar transistor Q 6  for SR 2 . 
   v GS   SR     1   (t) and v GS   SR     2   (t) are provided by two voltages, which are first induced by the two secondary windings of T 3  and then processed by the half-wave rectifiers as well as the fast turn-off circuits. When V T     3   (t)=V cc , D 52 , D 51  and Q 6  are turned on but Q 5 , D 62  and D 61 , are turned off, so SR 1  is turned on but SR 2  is turned off. When V T     3   (t)=0, D 52 , D 51 , D 62  and D 61  are turned off but Q 5  and Q 6  are turned on, so both SR 1  and SR 2  are turned off. When V T     3   (t)=−V cc , D 62 , D 61  and Q 5  are turned on but Q 6 , D 52  and D 5 , are turned off, so SR 2  is turned on but SR 1  is turned off. V T     3   (t), v GS   SR     1   (t) and v GS   SR     2   (t) are listed in Table 2: 
   
     
       
             
             
             
           
         
             
               TABLE 2 
             
             
                 
             
             
               V T     3   (t) 
               V GS   SR     1   (t) 
               V GS   SR     2   (t) 
             
             
                 
             
           
           
             
               V cc   
               V cc   
               0 
             
             
               0 
               0 
               0 
             
             
               −V cc   
               0 
               V cc   
             
             
                 
             
           
        
       
     
   
   A circuit diagram of the third embodiment according to the present invention is shown in  FIG. 4   b . v GS   SR     1   (t) and v GS   SR     2   (t) are provided by a differential transformer T 5  and a signal distributor, which comprises a diode D 7  and a diode D 8 . T 5  has a primary winding and a secondary winding as well as a 1:1 primary-to-secondary turns ratio, so a primary bipolar differential voltage v T     s   (t)=v B (t)−v A (t) or T 5  generates an identical secondary bipolar differential voltage. D 7  and D 8  are connected in a common-anode configuration between the secondary winding of T 5  and the gates of SR 1  and SR 2 . The signal distributor is used for converting the secondary bipolar differential voltage into two unipolar drive voltages as well as distributing these two voltages to SR 1  and SR 2  respectively. 
   When v T     5   (t)=V cc , D 8  is turned on but D 7  is turned off, so SR 1  is turned on but SR 2  is turned off. When V T     5   (t)=0, both D 7  and D 8  are turned off, so both SR 1  and SR 2  are turned off. When V T     5   (t)=−V cc , D 7  is turned on but D 8  is turned off, so SR 2  is turned on but SR 1  is turned off. v T     5   (t), v GS   SR     1   (t) and v GS   SR     2   (t) are listed in Table 3, and the corresponding voltage waveforms of v A (t), v B (t), v GS   M     1   (t), v GS   M     2   (t), v GS   SR     1   (t) and v GS   SR     2   (t) of the second and the third embodiments are shown in  FIG. 4   c.    
   
     
       
             
             
             
           
         
             
               TABLE 3 
             
             
                 
             
             
               V T     5   (t) 
               V GS   SR     1   (t) 
               V GS   SR     2   (t) 
             
             
                 
             
           
           
             
               V cc   
               V cc   
               0 
             
             
               0 
               0 
               0 
             
             
               −V cc   
               0 
               V cc   
             
             
                 
             
           
        
       
     
   
   Three exemplary embodiments are shown in  FIG. 5   a ,  FIG. 6   a  and  FIG. 6   b , when the primary IC controller U 1  outputs two drive voltages referred to the sources of M 1  and M 2  for directly driving M 1  and M 2 . However, the output drive voltage of U 1  for M 1  is referred to the source of M 1  but not the primary ground instead, so it cannot be directly used as v B (t) on T 3 , but the output drive voltage of U 1  for M 2  is referred to the primary ground, so it can be used as v A (t) on T 3 . In view of this, the combined circuit of a DC shifter and a DC restorer is used to convert the output drive voltage of U 1  for M 1  referred to the source of M 1  into v B  (t) referred to the primary ground. The DC shifter comprises a capacitor C 4  and a pulse transformer T 4  that has a primary winding and a secondary winding as well as a 1:1 primary-to-secondary turns ratio. The DC restorer comprises a capacitor C 3  and a diode D 3 . T 3  is connected between the DC restorer and the gates of SR 1  and SR 2  to convert a primary bipolar voltage v T     3   (t)=v B (t)−v A (t) into two secondary bipolar voltages v GS   SR     1   (t) and v GS   SR     2   (t). 
   The DC shifter converts the output drive voltage of U 1  for M 1  to an AC voltage, and then the DC restorer converts the AC voltage back to a DC voltage referred to the primary ground. The voltage across C 4  can be derived from the volt-seconds product equilibrium equation:
 
( V   cc   −V   C4 ) D=V   C4 (1− D )             V   C4   =DV   cc  
 
where D is the duty ratio of M 1  and D≈0.5         V C4 =DV cc ≈0.5V cc , so V C     4    can be viewed as a constant voltage source during a switching period. The voltage across the secondary winding of T 4  can be expressed as:

               v   w     ⁡     (   t   )       =     {               V   cc     -     V     C   4         ,             M   1     ⁢           ⁢   on   ⁢           ⁢   and   ⁢           ⁢     D   3     ⁢           ⁢   off                 -     V     C   4         ,             M   1     ⁢           ⁢   off   ⁢           ⁢   and   ⁢           ⁢     D   3     ⁢           ⁢   on                   
When D 3  is turned on, C 3  is recharged to V C     4   . Therefore, the voltage across C 3 , V C     3   =V C     4   ≈0.5V cc , can be also viewed as a constant voltage source during a switching period.
 
   The voltage difference between the node B and the primary ground terminal can be expressed as: 
                     v   B     ⁡     (   t   )       =       V     C   3       +       v   w     ⁡     (   t   )                     =       V     C   4       +     {               V   cc     -     V     C   4         ,             M   1     ⁢           ⁢   on   ⁢           ⁢   and   ⁢           ⁢     D   3     ⁢           ⁢   off                 -     V     C   4         ,             M   1     ⁢           ⁢   off   ⁢           ⁢   and   ⁢           ⁢     D   3     ⁢           ⁢   on                           =     {             V   cc     ,             M   1     ⁢           ⁢   on   ⁢           ⁢   and   ⁢           ⁢     D   3     ⁢           ⁢   off               0   ,             M   1     ⁢           ⁢   off   ⁢           ⁢   and   ⁢           ⁢     D   3     ⁢           ⁢   on                         
The voltage of the node B is denoted as v B (t) referred to the primary ground, so the differential voltage v T     3   (t)=v B (t)−v A (t) can be imposed on T 3  to generate v GS   SR     1   (t) and v GS   SR     2   (t).
 
   The secondary circuit of the fourth embodiment shown in  FIG. 5   a  is the same as that of the first embodiment shown in  FIG. 3   a , so they have similar voltage waveforms shown in  FIGS. 3   b  and  5   b . The fifth and sixth embodiments shown in  FIG. 6   a  and  FIG. 6   b  respectively have the same primary circuit as the fourth embodiment shown in  FIG. 5   a  as well as the same secondary circuit as the second and third embodiments shown in  FIG. 4   a  and  FIG. 4   b,  so they have similar voltage waveforms shown in  FIGS. 4   c  and  6   c . The operational principles of the fifth and the sixth embodiments can be inferred from the aforementioned embodiments, and will not be restated here. 
   While the invention has been described in terms of what are presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.