Abstract:
An array substrate of an N-line inversion type includes data lines, scan lines and pixels. A number of the data lines is ‘m’, and the data lines are extended in a first direction. A number of the scan lines is ‘n’, and the scan lines are extended in a second direction that is substantially perpendicular to the first direction. Each of the scan lines has a contact terminal that makes contact with corresponding ones of output terminals of a scan driving part that generates scan signals. A K(N+1)-th output terminal is disconnected from the scan lines. The number of the pixels is ‘m times n’. The pixels are formed in regions defined by the data and scan lines. m, n, K and N are each natural numbers. Therefore, a charging rate of each of inverted horizontal lines increases.

Description:
[0001]     This application claims priority to Korean Patent Application No. 2004-58850, filed on Jul. 27, 2004, and all the benefits accruing therefrom under 35 U.S.C §119, and the contents of which in its entirety are herein incorporated by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to an array substrate, a display device having the array substrate, a driving unit for driving the display device and a method of driving the display device. More particularly, the present invention relates to an array substrate capable of improving a charging rate, a display device having the array substrate, a driving unit for driving the display device and a method of driving the display device.  
         [0004]     2. Description of the Related Art  
         [0005]     A conventional liquid crystal display (LCD) device includes an LCD panel and a driving part that drives the LCD panel. The LCD panel includes an array substrate, an upper substrate and a liquid crystal layer disposed between the array substrate and the upper substrate.  
         [0006]     The array substrate includes data lines, scan lines and pixels. The data lines cross the scan lines. Each of the pixels is defined by the data and scan lines adjacent to each other.  
         [0007]     A switching element, a liquid crystal capacitor and a storage capacitor are included in each of the pixels. A gate electrode of the switching element is electrically connected to a corresponding one of the scan lines. A source electrode of the switching element is electrically connected to a corresponding one of the data lines. A drain electrode of the switching element is electrically connected to a pixel electrode that is a first electrode of the liquid crystal capacitor. The storage capacitor is formed by the gate electrode and the pixel electrode.  
         [0008]     The upper substrate includes a color filter corresponding to each of the pixels and a common electrode that is a second electrode of the liquid crystal capacitor. When a voltage having a predetermined polarity is continuously applied to the first and second electrodes adjacent to a liquid crystal of the liquid crystal layer, the liquid crystal is deteriorated. Deterioration of the liquid crystal is prevented through an inversion method. In the inversion method, polarity of voltage applied to the first and second electrodes adjacent to the liquid crystal is inverted at a predetermined interval.  
         [0009]     The inversion method is classified into a frame inversion type, a line inversion type, a dot inversion type, etc. In the frame inversion type, the polarity of the voltage applied to the first and second electrodes adjacent to the liquid crystal over all of the pixels is inverted in every frame. In the line inversion type, the polarity of the voltage applied to the first and second electrodes adjacent to the liquid crystal over pixels corresponding to each of the gate or data lines is inverted in every frame, and the polarity of voltages of the gate or data lines are different from one another. In the dot inversion type, the polarity of the voltage applied to the first and second electrodes adjacent to the liquid crystal over each of the pixels is inverted in every frame, and the polarity of the first and second electrodes are different from one another.  
         [0010]     When the voltage applied to the first and second electrodes adjacent to the liquid crystal is inverted from a first polarity to a second polarity, a level of the voltage is dropped so that a charging rate of each of inverted horizontal lines is smaller than a charging rate of non-inverted horizontal lines.  
         [0011]     When the charging rate of the inverted horizontal lines is decreased, a horizontal stripe is formed on a screen of the LCD device. For example, a bright horizontal stripe and a dark horizontal stripe are formed in a normally white mode and a normally black mode, respectively. In addition, when the LCD device has a high resolution and displays a moving image, an image display quality of the LCD device is decreased.  
       SUMMARY OF THE INVENTION  
       [0012]     The present invention provides an array substrate capable of improving a charging rate. The present invention further provides a display device having the above-mentioned array substrate. The present invention still further provides a driving unit for driving the above-mentioned display device. The present invention still further provides a method of driving the above-mentioned display device.  
         [0013]     An array substrate of an N-line inversion type in accordance with an aspect of the present invention includes data lines, scan lines and pixels. A number of the data lines is ‘m’, and the data lines are extended in a first direction. A number of the scan lines is ‘n’, and the scan lines are extended in a second direction that is substantially perpendicular to the first direction. Each of the scan lines has a contact terminal that makes contact with corresponding ones of output terminals of a scan driving part that generates scan signals. A K(N+1)-th output terminal is disconnected from the scan lines. The number of the pixels is ‘m×n’ (m times n). The pixels are formed in regions defined by the data and scan lines. m, n, K and N are each natural numbers.  
         [0014]     A display device in accordance with an aspect of the present invention includes a display part, a driving part, a scan driving part and a controlling part. The display part has data lines, scan lines and pixels. Each of the pixels is electrically connected to corresponding ones of the data lines and corresponding ones of the scan lines. The driving part outputs valid data signals that charge the pixels and an invalid data signal to the data lines. The scan driving part generates scan signals corresponding to the valid data signals and the invalid scan signal corresponding to the invalid data signal to output the scan signals to the scan lines. The scan signals activate the scan lines corresponding to the valid data signals. The controlling part controls the data driving part so that the data driving part outputs N valid data signals having a first polarity, an invalid data signal having a second polarity and N valid data signals having the second polarity to the data lines, in sequence. The second polarity is opposite to the first polarity with respect to a reference voltage.  
         [0015]     A driving unit for driving a display device in accordance with an aspect of the present invention includes a driving part, a scan driving part and a controlling part. The display device includes a display part having data lines, scan lines and pixels electrically connected to the data and scan lines. The driving part outputs valid data signals that charge the pixels and invalid data signal to the data lines. The scan driving part generates scan signals corresponding to the valid data signals and an invalid scan signal corresponding to the invalid data signal to output the scan signals to the scan lines. The scan signals activate the scan lines corresponding to the valid data signals. The controlling part controls the data driving part so that the data driving part outputs N valid data signals having a first polarity, an invalid data signal having a second polarity and N valid data signals having the second polarity to the data lines, in sequence or in a first-in first out manner. The second polarity is opposite to the first polarity with respect to a reference voltage.  
         [0016]     A method of driving a display in accordance with an aspect of the present invention is provided as follows. The display device includes a display part having data lines, scan lines and pixels electrically connected to the data and scan lines. N valid data signals to the data lines is applied, and scan signals are applied to the scan lines corresponding to the N valid data signals to activate the scan lines corresponding to the N valid data signals using an N-line inversion method. The N valid data signals have a first polarity. An invalid data signal is applied to one of the data lines after the N valid data signals, and an invalid scan signal is applied to one of the scan lines corresponding to the invalid data signal to deactivate the one of the scan lines corresponding to the invalid data signal. The invalid data signal has a second polarity that is opposite to the first polarity with respect to a reference voltage.  
         [0017]     Therefore, the charging rate of each of inverted horizontal lines increases. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]     The above and other advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:  
         [0019]      FIG. 1  is a plan view showing an N-line-dot inversion method in accordance with an exemplary embodiment of the present invention;  
         [0020]      FIG. 2  is a timing diagram showing a charging rate of an inverted pixel that is inverted through the N-line inversion method of  FIG. 1 ;  
         [0021]      FIG. 3  is a block diagram showing a liquid crystal display (LCD) device in accordance with an exemplary embodiment of the present invention;  
         [0022]      FIG. 4  is a block diagram showing an exemplary driving unit of the LCD device of  FIG. 3 ;  
         [0023]      FIG. 5  is a timing diagram showing a method of driving the driving unit of  FIG. 4 ;  
         [0024]      FIG. 6  is a timing diagram showing a method of driving a driving unit in accordance with another exemplary embodiment of the present invention;  
         [0025]      FIG. 7  is a block diagram showing a driving unit of an LCD device in accordance with another exemplary embodiment of the present invention;  
         [0026]      FIG. 8  is a timing diagram showing a method of driving a driving unit in accordance with another exemplary embodiment of the present invention;  
         [0027]      FIG. 9  is a timing diagram showing a method of driving a driving unit in accordance with another exemplary embodiment of the present invention;  
         [0028]      FIG. 10  is a plan view showing an exemplary scan driving part of  FIG. 3 ;  
         [0029]      FIG. 11  is a plan view showing another exemplary scan driving part of  FIG. 3 ;  
         [0030]      FIG. 12  is a plan view showing another exemplary scan driving part of  FIG. 3 ; and  
         [0031]      FIG. 13  is a plan view showing another exemplary scan driving part of  FIG. 3 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0032]     It should be understood that the exemplary embodiments of the present invention described below may be modified in many different ways without departing from the inventive principles disclosed herein, and the scope of the present invention is therefore not limited to these particular following embodiments. Rather, these embodiments are provided so that this disclosure will be through and complete, and will fully convey the concept of the invention to those skilled in the art by way of example and not of limitation.  
         [0033]     Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.  
         [0034]      FIG. 1  is a plan view showing an N-line-dot inversion method in accordance with an exemplary embodiment of the present invention.  
         [0035]     Referring to  FIG. 1 , a polarity of a voltage applied to pixels in every N-th line is inverted. In this exemplary embodiment, the polarity of the voltage applied to the pixels in every 4-th line is inverted.  
         [0036]      FIG. 2  is a timing diagram showing a charging rate of an inverted pixel that is inverted through the N-line-dot inversion method of  FIG. 1 .  
         [0037]     Referring to  FIG. 2 , pixels in a first column COLUMN_ 1  are charged by data signals from a first date line.  
         [0038]     A data signal having a first polarity that is a positive polarity is applied to first to N-th horizontal lines. In addition, a data signal having a second polarity that is a negative polarity is applied to (N+1)-th to 2N-th horizontal lines. Furthermore, a data signal having the first polarity that is the positive polarity is applied to the ( 2 N+1)-th to 3N-th horizontal lines. In other words, a polarity of the data signal is inverted in every N-th horizontal lines. As shown in oval portion I of  FIG. 2 , a charging delay exists as polarity applied to the horizontal lines switches from positive to negative polarity or from negative to positive polarity.  
         [0039]      FIG. 3  is a block diagram showing a liquid crystal display (LCD) device in accordance with an exemplary embodiment of the present invention.  
         [0040]     Referring to  FIG. 3 , the LCD device includes a timing controlling part  110 , a data driving part  130 , a scan driving part  150 , a driving voltage generating part  170  and an LCD panel  190 .  
         [0041]     The timing controlling part  110  processes data signals DATA from an external graphic unit (not shown) to output processed data signals DATA′ to the data driving part  130 .  
         [0042]     When a number of scan lines is ‘n’, the timing controlling part  110  further outputs dummy data signals DUMMY to the data driving part  130  so as to decrease a difference between charging rates of the pixels. In this exemplary embodiment, the dummy data signals DUMMY are a predetermined data signal. Alternatively, the dummy data signals DUMMY may be a previous data signal. When n is a multiple of N, a number of the dummy data signals DUMMY is n/N−1. When n is not a multiple of N, the number of the dummy data signals DUMMY is a truncated integer of n/N without decimals. Alternatively, the number of the dummy data signals DUMMY may be n/N although n is a multiple of N.  
         [0043]     For example, the timing controlling part  110  outputs a data signal having the first polarity, one of the dummy data signals DUMMY having the second polarity and a data signal having the second polarity, in sequence, so that the charging rate is controlled by the dummy data signal DUMMY. For example, when the number of the scan lines is 800, and the polarity of the data signals is inverted in every 128th horizontal lines, the timing controlling part  110  outputs six dummy data signals DUMMY after the data signals corresponding to 128th scan line, (128×2+1)-th scan line, (128×3+2)-th scan line, (128×4+3)-th scan line, (128×5+4)-th scan line and (128×6+5)-th scan line are outputted from the timing controlling part  110 , respectively. The six dummy data signals DUMMY may be applied to the scan lines. In this exemplary embodiment, the six dummy data signals DUMMY are applied to the data signals corresponding to (128+1)-th scan line, (128×2+2)-th scan line, (128×3+3)-th scan line, (128×4+4)-th scan line, (128×5+5)-th scan line and (128×6+6)-th scan line, respectively. Alternatively, the six dummy data signals DUMMY may not be applied to the scan lines. A truncated integer of 800/128 without decimals is 6. Each of the dummy data signals DUMMY is inverted from each of the data signals corresponding to (128+1)-th scan line, (128×2+2)-th scan line, (128×3+3)-th scan line, (128×4+4)-th scan line, (128×5+5)-th scan line and (128×6+6)-th scan line, respectively.  
         [0044]     The dummy data signals DUMMY are inserted between the data signals so that a portion of the data signals are delayed by the dummy data signals DUMMY. The delayed data signals are outputted during a vertical blanking period.  
         [0045]     The timing controlling part  110  outputs second to fourth control signals based on a first control signal that is provided by the external graphic unit. The first control signal includes a main clock signal MCLK, a horizontal synchronization signal HSYNC, a vertical synchronization signal VSYNC and a data enable signal DE. The second control signal includes a horizontal start signal STH, an inversion signal RVS and a load signal TP. The second control signal controls the data driving part  130 . The third control signal includes a main clock signal, an inversion signal, etc. The third control signal controls the driving voltage generating part  170 . The fourth control signal includes a scan start signal STV, a clock signal CK, an output enable signal OE, etc. The fourth control signal controls the scan driving part  150 .  
         [0046]     The data driving part  130  converts the data signals into analog data signals D 1 , D 2 , . . . Dm responsive to the second control signal to output the analog data signals D 1 , D 2 , . . . Dm to data lines DL 1 , DL 2 , . . . DLm. The data driving part  130  outputs n valid data signals that correspond to the n scan lines and the dummy data signals DUMMY that are invalid data signals through an N-line inversion method.  
         [0047]     The scan driving part  150  generates scan signals responsive to the fourth control signal to output the scan signals to the scan lines. The scan signals include n scan signals that correspond to the n scan lines and dummy scan signals that correspond to the dummy data signals DUMMY. When n is a multiple of N, the number of the dummy scan signals is n/N−1. When n is not a multiple of N, the number of the dummy scan signals is a truncated integer of n/N without decimals. Alternatively, the number of the dummy signals DUMMY may be n/N although n is a multiple of N.  
         [0048]     For example, one of the dummy scan signals SD is inserted between N-th scan signal SN and (N+1)-th scan signal SN+1. When the N-th data signal having the first polarity is applied to the Nth data line, the N-th scan signal SN is applied to the N-th scan line SLn so that the N-th scan line SLn is activated.  
         [0049]     The dummy scan signals SD are not applied to the scan lines, although the dummy data signals DUMMY are applied to the data lines. The dummy data signals DUMMY are not stored in the pixels of the LCD panel  190 . Therefore, the charging rate is not deteriorated although the polarity of the signals is inverted.  
         [0050]     The driving voltage generating part  170  generates a first voltage VOFF, a second voltage VON and a common voltage VCOM. The first and second voltages VOFF and VON are applied to the scan driving part  150 . The common voltage VCOM is applied to a liquid crystal capacitor CLC and a storage capacitor CS of the LCD panel  190 .  
         [0051]     The LCD panel  190  includes an array substrate, an upper substrate and a liquid crystal layer interposed between the array substrate and the upper substrate.  
         [0052]     The array substrate includes the data lines DL 1 , DL 2 , . . . DLm, the scan lines SL 1 , SL 2 , . . . SLn and pixels. Each of the pixels is defined by the data and scan lines adjacent to each other. A number of the pixels is m×n (m times n).  
         [0053]     A switching element that includes a thin film transistor TFT, the liquid crystal capacitor CLC and the storage capacitor CS is included in each of the pixels. A gate electrode of the switching element is electrically connected to a corresponding one of the scan lines SL 1 , SL 2 , . . . SLn. A source electrode of the switching element is electrically connected to a corresponding one of the data lines DL 1 , DL 2 , . . . DLm. A drain electrode of the switching electrode is electrically connected to a pixel electrode that is a first electrode of the liquid crystal capacitor CLC. The storage capacitor CS is defined by the gate electrode of the switching element and the pixel electrode.  
         [0054]     The upper substrate includes a color filter and a common electrode that is a second electrode of the liquid crystal capacitor CLC. The color filter corresponds to each of the pixels. The common voltage VCOM from the driving voltage generating part  170  is applied to the common electrode and the storage capacitor CS and the liquid crystal capacitor CLC.  
         [0055]      FIG. 4  is a block diagram showing an exemplary driving unit of the LCD device of  FIG. 3 .  
         [0056]     Referring to  FIG. 4 , the driving unit includes a timing controlling part  210 , a data driving part  230 , a scan driving part  250  and a driving voltage generating part  270 .  
         [0057]     The timing controlling part  210  includes a signal processing part  213 , a data processing part  215 , a memory  217  and a controlling part  219 .  
         [0058]     The signal processing part  213  generates control signals responsive to signals from exterior to the driving unit. The control signals generated by the signal processing part  213  are applied to the data driving part  230 , the scan driving part  250  and the driving voltage generating part  270 , respectively.  
         [0059]     For example, the signal processing part  213  outputs the control signals to the data driving part  230 , the scan driving part  250  and the driving voltage generating part  270  responsive to the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the data enable signal DE and the main clock signal MCLK, which are provided by an external graphic controller (not shown). Frames of the driving unit are controlled responsive to the vertical synchronization signal VSYNC. Horizontal lines of the driving unit are controlled responsive to the horizontal synchronization signal HSYNC. The data enable signal DE enables the signal processing part  213  to generate a signal having a high level while processing data signals. For example, the signal processing part  213  generates the horizontal start signal STH, the load signal TP, the scan clock CK, the vertical start signal STV that is a scan start signal, the inversion signal RVS, a scan output enable signal OE that is a gate output enable signal, etc.  
         [0060]     The data processing part  215  processes data signals DATA from the external graphic controller (not shown) through the controlling part  219 , and processed data signals  215   a  are applied to the data driving part  230 . The data processing part  215  may control timing of the data signals DATA.  
         [0061]     A portion of the data signals DATA are delayed by a dummy data signal. The delayed portion of the data signals DATA are temporarily stored as stored data signals in the memory  217 .  
         [0062]     The controlling part  219  controls an operation of the driving unit. In addition, the controlling part  219  stores the delayed portion of the data signals DATA in the memory  217 , and reads the stored data signals. The controlling part  219  outputs the stored data signals to the data driving part  230  during the vertical blanking period, in sequence. The vertical blanking period may be a latter portion of a frame.  
         [0063]     The data driving part  230  outputs analog signals to the data lines DL 1 , DL 2 , . . . DLm responsive to the data signals DATA and the dummy data signals. The data signals DATA and the dummy data signals are outputted from the timing controlling part  210  responsive to the horizontal start signal STH, the load signal TP, the inversion signal RVS, etc.  
         [0064]     The scan driving part  250  generates scan signals and the dummy data signals responsive to control signals such as the scan start signal STV, the output enable signal OE, the scan clock signal CK, etc., and the first and second voltages VOFF and VON from the driving voltage generating part  270 . The scan driving part  250  outputs the scan signals to the scan lines SL 1 , SL 2 , . . . SLn, and does not output the dummy scan signals to the scan lines SL 1 , SL 2 , . . . SLn.  
         [0065]     The driving voltage generating part  270  outputs the first and second voltages VOFF and VON to the scan driving part  250 , and outputs the common voltage VCOM to the liquid crystal capacitor CLC of the LCD panel  190  and the common electrode of the storage capacitor CS.  
         [0066]      FIG. 5  is a timing diagram showing a method of driving the driving unit of FIG.  4 . As shown in  FIG. 5 , a number of the scan lines SL 1 , SL 2 , . . . SLn of the driving unit is twelve, and thus timing diagrams for corresponding scan signals S 1  to S 12  are shown. A unit frame is 16H, and each frame has a vertical blanking period of 4H. The driving unit is operated through a 3-line inversion method.  
         [0067]     Referring to  FIGS. 3, 4  and  5 , first to twelfth line data signals  1 L_DA to  12 L_DA, shown by data signals DATA_IN, are applied to the first to twelfth data lines DL 1  to DL 12  of the driving unit responsive to the data enable signal DE during the unit frame, in sequence.  
         [0068]     The first line data signal  1 L_DA is processed by the data processing part  215  and the data driving part  230  so that the first line data signal  1 L_DA has a first polarity with respect to a reference voltage level. Following processing, the first line data signal  1 L_DA is synchronized with a second data enable pulse DE_ 2 . The synchronized first line data signal  1 L_DA is applied to the first data line DL 1  as a portion of the data signals DATA_OUT.  
         [0069]     Second and third line data signals  2 L_DA and  3 L_DA are synchronized with third and fourth data enable pulses DE_ 3  and DE_ 4 , respectively, so that the synchronized second and third line data signals  2 L_DA and  3 L_DA are applied to the second and third data lines DL 2  and DL 3 , in sequence.  
         [0070]     When the first, second and third line data signals  1 L_DA,  2 L_DA and  3 L_DA are applied to the first, second and third data lines DL 1 , DL 2  and DL 3 , the scan driving part  250  outputs the first, second and third scan signals S 1 , S 2  and S 3  to the first, second and third scan lines SL 1 , SL 2  and SL 3 , in sequence.  
         [0071]     The controlling part  219  outputs the first dummy data signal DM_ 1  to the data driving part  230  after the third line data signal  3 L_DA using the 3-line inversion method. The first dummy data signal DM_ 1  may be data stored in the memory  217  or a previous line data signal such as the third line data signal  3 L_DA.  
         [0072]     The controlling part  219  stores a fourth line data signal  4 L_DA in the memory  217  while the controlling part  219  outputs the first dummy data signal DM_ 1 . The data driving part  230  processes the first dummy data signal DM_ 1  so that the first dummy data signal DM_ 1  has a second polarity with respect to the reference voltage level. The second polarity is opposite to the first polarity. The first dummy data signal DM_ 1  having the second polarity may be applied to one of the data lines DL 1  to DL 12 . Alternatively, the first dummy data signal DM_ 1  having the second polarity may not be applied to one of the data lines DL 1  to DL 12 . Here, the scan driving part  250  generates a first dummy scan signal SD_ 1 . However, the first dummy scan signal SD_ 1  is not applied to the scan lines SL 1  to SL 12  so that the first dummy data signal DM_ 1  does not charge a pixel of the LCD panel  190  although the first dummy data signal DM_ 1  is applied to one of the data lines DL 1  to DL 12 . The controlling part  219  reads the stored fourth line data signal  4 L_DA to output the fourth line data signal  4 L_DA to the data driving part  230 . The controlling part  219  stores a fourth line data signal  5 L_DA in the memory  217  while the controlling part  219  reads the stored fourth line data signal.  4 L_DA.  
         [0073]     The fourth, fifth and sixth line data signals  4 L_DA,  5 L_DA and  6 L_DA that have the second polarity are applied to the fourth, fifth and sixth data lines DL 4 , DL 5  and DL 6 , and the fourth, fifth and sixth scan signals S 4 , S 5  and S 6  are applied to the fourth, fifth and sixth scan lines SL 4 , SL 5  and SL 6 , respectively.  
         [0074]     The seventh, eighth and ninth line data signals  7 L_DA,  8 L_DA and  9 L_DA that have the first polarity are applied to the seventh, eighth and ninth data lines DL 7 , DL 8  and DL 9 , and the seventh, eighth and ninth scan signals S 7 , S 8  and S 9  are applied to the seventh, eighth and ninth scan lines SL 7 , SL 8  and SL 9 , respectively.  
         [0075]     The controlling part  219  outputs the second dummy data signal DM_ 2  to the driving part  230  during the ninth data enable pulse DE_ 9 . The seventh, eighth and ninth line data signals  7 L_DA,  8 L_DA and  9 L_DA are synchronized with the second dummy data signal DM_ 2 , and the synchronized seventh, eighth and ninth line data signals  7 L_DA,  8 L_DA and  9 L_DA are applied to the driving part  230 , in sequence or in a first-in first-out manner.  
         [0076]     The scan driving part  250  outputs the second dummy scan signal SD_ 2  and seventh, eighth and ninth scan signals S 7 , S 8  and S 9  while the second dummy data signal DM_ 2  and the seventh, eighth and ninth line data signals  7 L_DA,  8 L_DA and  9 L_DA are outputted to the seventh, eighth and ninth data lines DL 7 , DL 8  and DL 9 .  
         [0077]     The tenth, eleventh and twelfth line data signals  10 L_DA,  11 L_DA and  12 L_DA that are delayed by the first, second and third dummy data signals DM_ 1 , DM_ 2  and DM_ 3  are stored in the memory  217 . The stored tenth, eleventh and twelfth line data signals  10 L_DA,  11 L_DA and  12 L_DA are applied to the tenth, eleventh and twelfth data lines DL 10 , DL 11  and DL 12  during the vertical blanking period, respectively.  
         [0078]     The controlling part  219  outputs the third dummy data signal DM_ 3  to the driving part  230  during the thirteenth data enable pulse DE_ 13 . The tenth, eleventh and twelfth line data signals  10 L_DA,  11 L_DA and  12 L_DA are synchronized with the third dummy data signal DM_ 3 , and the synchronized tenth, eleventh and twelfth line data signals  10 L_DA,  11 L_DA and  12 L_DA are applied to the driving part  230 , in sequence.  
         [0079]     Therefore, the third dummy data signal DM_ 3  and the tenth, eleventh and twelfth line data signals  10 L_DA,  11 L_DA and  12 L_DA are applied to the data lines during the vertical blanking period, in sequence.  
         [0080]     The scan driving part  250  outputs the third dummy scan signal SD_ 3  and tenth, eleventh and twelfth scan signals S 10 , S 11  and S 12  while the third dummy data signal DM_ 3  and the tenth, eleventh and twelfth line data signals  10 L_DA,  11 L_DA and  12 L_DA are outputted to the tenth, eleventh and twelfth data lines DL 10 , DL 11  and DL 12 .  
         [0081]     According to this exemplary embodiment, a predetermined line ‘T’ representing a decreased charging rate is removed using dummy data signals and dummy scan signals in the N-line inversion method.  
         [0082]      FIG. 6  is a timing diagram showing a method of driving a driving unit in accordance with another exemplary embodiment of the present invention. A driving unit of  FIG. 6  is same as in FIGS.  1  to  5  except for a pulse width. Thus, the same reference numerals will be used to refer to the same or like parts as those described in FIGS.  1  to  5  and any further explanation will be omitted.  
         [0083]     Referring to  FIGS. 3, 4  and  6 , a delayed data signal that is delayed by the dummy data signal is temporarily stored in a memory, and is operated during a blanking period. A pulse width of each scan signal is 2H, which corresponds to a time period for activating two scan lines adjacent to each other.  
         [0084]     When the data driving part  230  outputs the second line data signal  2 L_DA, the scan driving part  250  outputs the second scan signal S 2  that is partially overlapped with the first scan signal S 1  by 1H. The second scan signal S 2  has a pulse width of 2H.  
         [0085]     When pixels of a first horizontal line are charged by the first line data signal  1 L_DA, pixels of a second horizontal line are pre-charged by the second scan signal S 2  and the first line data signal  1 L_DA. The second line data signal  2 L_DA is then applied to the second scan line SL 2  so that pixels of the second scan line SL 2  are charged. Therefore, a charging rate of the pixels receiving data signals having a same polarity is increased by overlapping scan signals.  
         [0086]     When the data driving part  230  outputs the first dummy data signal DM_ 1 , the scan driving part  250  outputs the first dummy scan signal SD_ 1  that is partially overlapped with the third scan signal S 3  by 1H. The first dummy scan signal SD_ 1  is not applied to one of the scan lines so that the first dummy data signal DM_ 1  is not charged in the pixels. Therefore, the charging rate of the pixels receiving inverted signals is increased by the first dummy scan signal SD_ 1 .  
         [0087]     When the data driving part  230  outputs the fourth line data signal  4 L_DA, the scan driving part  250  outputs the fourth scan signal S 4  that is partially overlapped with the first dummy data signal DM_ 1  by 1H.  
         [0088]     According to this exemplary embodiment, a time delay is not formed between the third and fourth scan signals S 3  and S 4 . In other words, the fourth scan signal S 4  is not delayed with respect to the third scan signal S 3  although the first dummy scan signal SD_ 1  is not applied to one of the scan lines.  
         [0089]      FIG. 7  is a block diagram showing a driving unit of an LCD device in accordance with another exemplary embodiment of the present invention.  
         [0090]     Referring to  FIG. 7 , the driving unit includes a timing controlling part  410 , a data driving part  430 , a scan driving part  450  and a driving voltage generating part  470 .  
         [0091]     The timing controlling part  410  includes a first signal processing part  411 , a second signal processing part  413 , a data processing part  415 , a memory  417  and a controlling part  419 .  
         [0092]     An external graphic controller (not shown) outputs first control signals to the first signal processing part  411 . The controlling part  419  controls the first signal processing part  411  so that the first signal processing part  411  generates a second control signal for controlling dummy signals. The dummy signals are used in an N-line inversion method.  
         [0093]     The first signal processing part  411  of an N-line inversion type driving unit modifies a data enable signal DE so that a number of clocks of a modified data enable signal DE′ corresponds to valid data signals and the dummy data signals. In this exemplary embodiment, the first signal processing part  411  includes a phase locked loop circuit to modify the data enable signal DE.  
         [0094]     For example, when a number of scan lines and a number of line inversions are 800 and 32, respectively, a number of the dummy data signals is 800/32=25 so that a number of pulses of the data enable signal DE is changed from 800 into 825. Therefore, a portion of pulses of the modified data enable signal DE′ corresponding to each of the line inversions corresponds to 32 data signals and one dummy data signal. Thus, the portion of the pulses of the modified data enable signal DE′ corresponding to each of the line inversions is changed from 32 to 33.  
         [0095]     The first signal processing part  411  also sends a modified horizontal synchronization signal HSYNC′ and a modified vertical synchronization signal VSYNC′ responsive to the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC, respectively, to the second signal processing part  413 .  
         [0096]     In this exemplary embodiment, when the number of the scan lines and the number of line inversions are n and N, respectively, and n is a multiple of N, the number of the clocks is changed from n to n+(n/N−1). However, when n is not a multiple of N, the number of the clocks is changed from n into a truncated integer of n+(n/N) without decimals.  
         [0097]     The second signal processing part  413  generates control signals that are applied to the data driving part  430 , the scan driving part  450  and the driving voltage generating part  470 , respectively, responsive to the modified data enable signal DE′ from the first signal processing part  411 .  
         [0098]     For example, the second signal processing part  413  generates a horizontal synchronization signal STH, a load signal TP, a scan clock signal CK, a vertical start signal STV that is a scan start signal, an inversion signal RVS, a scan output enable signal OE that is a gate output enable signal, etc.  
         [0099]     The data processing part  415  processes data signals from the exterior graphic controller (not shown) to modify a timing and data of the data signals so that modified data signals  415   a  are applied to the data driving part  430 .  
         [0100]     The memory  417  temporarily stores the data signals. The controlling part  419  controls an operation of the memory  417  so that the memory  417  temporarily stores the data signals and the controlling part  419  reads stored data signals.  
         [0101]     The data driving part  430  outputs the scan signals S 1 , S 2 , . . . Sn and the dummy scan signals to an LCD panel  190  of  FIG. 3  responsive to the control signals such as the scan start signal STV, the scan output enable signal OE, the scan clock signal CK, etc., and the first and second voltages VOFF and VON from the driving voltage generating part  470 .  
         [0102]     The driving voltage generating part  470  generates the first and second voltages VOFF and VON and the common voltage VCOM. The first and second voltages VOFF and VON are applied to the scan driving part  450 . The common voltage VCOM is applied to the liquid crystal capacitor CLC and the storage capacitor CS of the LCD panel  190  of  FIG. 3 .  
         [0103]      FIG. 8  is a timing diagram showing a method of driving a driving unit in accordance with another exemplary embodiment of the present invention. In this exemplary embodiment, a number of scan lines that are electrically connected to the driving unit is 12. A scanning period of a unit frame is 12H. The driving unit is operated through a 3-line inversion method.  
         [0104]     Referring to  FIGS. 3, 7  and  8 , the first signal processing part  411  processes the data enable signal DE into the modified data enable signal DE′ for processing the dummy signals through the 3-line inversion method. Four pulses of the modified data enable signal DE′ correspond to three pulses of the data enable signal DE.  
         [0105]     The controlling part  419  temporarily stores a first line data signal  1 L_DA in the memory  417  during a first data enable pulse DE_ 1  being applied to the controlling part  419 . The controlling part  419  reads the stored first line data signal  1 L_DA and temporarily stores a second line data signal  2 L_DA during a second data enable pulse DE_ 2  being applied to the controlling part  419 . The controlling part  419  temporarily reads and stores the data enable pulses of the data enable signal DE, in sequence.  
         [0106]     For example, an input line data signal DATA_IN is stored in the memory  417  responsive to the data enable signal DE, and an output line data signal DATA_OUT is outputted from the memory  417  responsive to the modified data enable signal DE′.  
         [0107]     The controlling part  419  sequentially reads the first, second and third line data signals  1 L_DA,  2 L_DA and  3 L_DA from the memory  417  responsive to the modified data enable signal DE′.  
         [0108]     The data driving part  430  receives the first, second and third line data signals  1 L_DA,  2 L_DA and  3 L_DA to output data signals having a first polarity with respect to a reference voltage responsive to the modified data enable signal DE′ to the first, second and third data lines DL 1 , DL 2  and DL 3 , in sequence.  
         [0109]     The scan driving part  450  outputs first, second and third scan signals S 1 , S 2  and S 3  that are synchronized with the first, second and third line data signals  1 L_DA,  2 L_DA and  3 L_DA to the first, second and third scan lines.  
         [0110]     When the third line data signal  3 L_DA having the first polarity is applied to the third data line DL 3 , the controlling part  417  applies the first dummy data signal DM_ 1  to the data driving part  430 . The data driving part  430  outputs a data signal having a second polarity responsive to the first dummy data signal DM_ 1  to one of the data lines DL 1 , DL 2 , . . . DL 12 . The second polarity is different from the first polarity with respect to the reference voltage. The scan driving part  450  generates a first dummy scan signal SD_ 1  that corresponds to the first dummy data signal DM_ 1 . The first dummy scan signal SD_ 1  is not applied to the scan lines so that the first dummy data signal DM_ 1  does not operate the LCD panel  190  of  FIG. 3 .  
         [0111]     The data driving part  430  then outputs fourth, fifth and sixth line data signals  4 L_DA,  5 L_DA and  6 L_DA to fourth, fifth and sixth data lines DL 4 , DL 5  and DL 6 , in sequence. The scan driving part  450  outputs fourth, fifth and sixth scan signals S 4 , S 5  and S 6  that are synchronized with the fourth, fifth and sixth line data signals  4 L_DA,  5 L_DA and  6 L_DA to the fourth, fifth and sixth scan lines SL 4 , SL 5  and SL 6 .  
         [0112]     The data driving part  430  outputs the twelve line data signals  1 L_DA,  2 L_DA, . . .  12 L_DA and three dummy data signals DM_ 1 , DM_ 2  and DM_ 3  to the data lines DL 1 , DL 2 , . . . DL 12  responsive to the modified data enable signal DE′. In addition, the scan driving part  450  generates the twelve scan signals S 1 , S 2 , . . . S 12  and the three dummy scan signals, and applies the twelve scan signals S 1 , S 2 , . . . S 12  to the scan lines SL 1 , SL 2 , . . . SL 12 .  
         [0113]     According to this exemplary embodiment, a portion ‘T’ at which a charging rate is decreased is eliminated using the dummy data signal and the dummy scan signals so that a charging rate of the driving unit is uniformized.  
         [0114]      FIG. 9  is a timing diagram showing a method of driving a driving unit in accordance with another exemplary embodiment of the present invention. A driving unit of  FIG. 9  is same as in  FIG. 7 . Thus, the same reference numerals will be used to refer to the same or like parts as those described in  FIG. 7  and any further explanation will be omitted.  
         [0115]     An operation of the driving unit of  FIG. 9  is same as in  FIG. 8  except a pulse width. Thus, the same reference numerals will be used to refer to the same or like parts as those described in  FIG. 8  and any further explanation will be omitted. A pulse width of each of scan signals is 2H.  
         [0116]     When the data driving part  430  outputs the second line data signal  2 L_DA, the scan driving part  450  outputs the second scan signal S 2  that is partially overlapped with the first scan signal S 1  by 1H. The second scan signal S 2  has a pulse width of 2H.  
         [0117]     When pixels of a first horizontal line are charged by the first line data signal  1 L_DA, pixels of a second horizontal line are pre-charged by the second scan signal S 2  and the first line data signal  1 L_DA. The second line data signal  2 L_DA is then applied to the second scan line SL 2  so that the pixels of the second scan line SL 2  are charged. Therefore, the charging rate of the pixels receiving data signals having a same polarity is increased by overlapping the scan signals.  
         [0118]     When the data driving part  450  outputs the first dummy data signal DM_ 1 , the scan driving part  450  outputs the first dummy scan signal SD_ 1  that is partially overlapped with the third scan signal S 3  by 1H. The first dummy scan signal SD_ 1  is not applied to one of the scan lines so that the first dummy data signal DM_ 1  is not charged in the pixels. Therefore, the charging rate of the pixels receiving inverted signals is increased by the first dummy scan signal SD_ 1 .  
         [0119]     When the data driving part  430  outputs a fourth line data signal  4 L_DA, the scan driving part  450  outputs a fourth scan signal S 4  that is partially overlapped with the first dummy data signal DM_ 1  by 1H.  
         [0120]     According to this exemplary embodiment, a time delay is not formed between the third and fourth scan signals S 3  and S 4  that are adjacent to the first dummy scan signal SD_ 1 . In other words, the fourth scan signal S 4  is not delayed with respect to the third scan signal S 3  although the first dummy scan signal SD_ 1  is not applied to one of the scan lines.  
         [0121]      FIG. 10  is a plan view showing an exemplary scan driving part of  FIG. 3 . The scan driving part includes a scan driving integrated circuit (IC). The scan driving part is on an array substrate of the LCD panel  190 .  
         [0122]     Referring to  FIG. 10 , an IC pad  151  is formed adjacent to a side of the array substrate that has scan lines. The scan driving IC is mounted on the IC pad  151 . The IC pad  151  includes a plurality of contact terminals CNT_ 1 , CNT_ 2 , . . . CNT_n+K that make contact with respective output terminals of the scan driving IC.  
         [0123]     Selected ones of the contact terminals CNT_ 1 , CNT_ 2 , . . . CNT_n+K are electrically connected to corresponding ones of the scan lines SL 1 , SL 2 , . . . SLn. A number of the contact terminals is n+K in an N-line inversion method. The number of the dummy scan signals is K.  
         [0124]     Nth contact terminal CNT_N is electrically connected to Nth scan line SL_N. (N+1)-th contact terminal CNT_N+1 is not electrically connected to one of the scan lines SL 1 , SL 2 , . . . SLn. In addition, ( 2 N+2)-th contact terminal CNT_ 2 N+2, ( 3 N+3)-th contact terminal C NT_ 3 N+3, . . . are not electrically connected to one of the scan lines SL 1 , SL 2 , . . . SLn.  
         [0125]     The (N+1)-th contact terminal CNT_N+1, ( 2 N+2)-th contact terminal CNT_ 2 N+2, ( 3 N+3)-th contact terminal CNT_ 3 N+3, . . . of the IC pad  151  are electrically connected to the (N+1)-th output terminal, the ( 2 N+2)-th output terminal, the ( 3 N+3)-th output terminal, . . . of the scan driving IC, respectively. Therefore, (N+1)-th scan signal, ( 2 N+2)-th scan signal, ( 3 N+3)-th scan signal, . . . which are dummy signals are not applied to the LCD panel  190 .  
         [0126]      FIG. 11  is a plan view showing another exemplary scan driving part of  FIG. 3 .  
         [0127]     Referring to  FIG. 11 , a scan driving IC  152  is formed adjacent to a side of the array substrate that has the scan lines. The scan driving IC  152  includes a plurality of output terminals OUT_ 1 , OUT_ 2 , . . . OUT_n that correspond to the scan lines SL 1 , SL 2 , . . . SLn, respectively. In this exemplary embodiment, a number of the output terminals OUT_ 1 , OUT_ 2 , . . . OUT_n is equal to a number of the scan lines SL 1 , SL 2 ,  
         [0128]     The scan driving IC  152  generates the scan signals S 1 , S 2 , . . . Sn and the dummy scan signals. The number of the dummy scan signals is K. The scan driving IC  152  outputs the scan signals S 1 , S 2 , . . . Sn to the scan lines SL 1 , SL 2 , . . . SLn. The scan driving IC  152  does not output the dummy scan signals.  
         [0129]     For example, the scan driving IC  152  outputs N-th scan signal SN through N-th output terminal OUTN. The scan driving IC  152  does not output (N+1)-th scan signal SN+1. The scan driving IC  152  then outputs (N+2)-th scan signal SN+2 through (N+1)-th output terminal OUTN+1.  
         [0130]     According to this exemplary embodiment, the scan driving IC  152  does not have output terminals for (N+1)-th scan signal, ( 2 N+2)-th scan signal, ( 3 N+3)-th scan signal, . . . which are dummy signals so that (N+1)-th scan signal, ( 2 N+2)-th scan signal, ( 3 N+3)-th scan signal, . . . are not outputted from the scan driving IC  152 .  
         [0131]      FIG. 12  is a plan view showing another exemplary scan driving part of  FIG. 3 . The scan driving part  150  is integrated on a portion of an array substrate. A switching element that is formed on the array substrate includes an amorphous-silicon thin film transistor (a-Si TFT). The a-Si TFT has a channel layer defined by an amorphous-silicon (a-Si) layer and an N+a-Si layer that is on the a-Si layer.  
         [0132]     Referring to  FIG. 12 , the scan driving part  150  has a shift register including a plurality of stages SRC 1 , SRC 2 , . . . SRCn. The stages SRC 1 , SRC 2 , . . . SRCn are electrically connected in parallel with one another. An output terminal of each of the stages SRC 1 , SRC 2 , . . . SRCn is electrically connected to an input terminal of a next stage so that the stages SRC 1 , SRC 2 , . . . SRCn provide a parallel output shift register. Each of the stages SRC 1 , SRC 2 , . . . SRCn has a plurality of a-Si TFT.  
         [0133]     A portion of the stages SRC 1 , SRC 2 , . . . SRCn+K correspond to the scan lines SL 1 , SL 2 , . . . SLn. A number of the stages SRC 1 , SRC 2 , . . . SRCn corresponding to the scan lines SL 1 , SL 2 , . . . SLn is n. A remaining portion of the stages SRC 1 , SRC 2 , . . . SRCn+K generate dummy scan signals. A number of the dummy stages SRC 1 , SRC 2 , . . . SRCK is K. The shift register further includes a control stage SRCn+K+1 that applies a control signal to the (n+K)-th stage that is a last stage of the stages SRC 1 , SRC 2 , . . . SRCn+K.  
         [0134]     Each of the stages SRC 1 , SRC 2 , . . . SRCn+K includes the input terminal IN, the output terminal OUT, a control terminal CT, a clock input terminal CLK, a first voltage terminal VOFF and a second voltage terminal VON.  
         [0135]     A scan start signal STV is applied to the input terminal IN of the first stage SRC 1  as an operation start signal. An output signal of one of remaining stages SRC 2 , SRC 3 , . . . SRCn+K, which is a present stage, is applied to the input terminal IN of a next stage as the operation start signal. Alternatively, each of the stages SRC 1 , SRC 2 , . . . SRCn+K may further include a carry signal generating part that receives the output signal of the next stage as a carry signal so that the carry signal may be applied to the input terminal IN of a previous stage.  
         [0136]     The scan lines SL 1 , SL 2 , . . . SLn are electrically connected to the output terminals OUT 1 , OUT 2 , . . . OUTn+K except (N+1)-th output terminal OUTN+1, ( 2 N+2)-th output terminal OUT 2 N+2, . . . which are dummy output terminals. An odd stage clock signal CKA is applied to odd numbered stages SRC 1 , SRC 3 , . . . SRCn+K−1. An even stage clock signal CKB is applied to even numbered stages SRC 2 , SRC 4 , . . . SRCn+K. The odd and even stage clock signals CKA and CKB may have opposite phases to each other.  
         [0137]     The output signal OUT of a next stage is applied to a control terminal CT of a present stage as a control signal. For example, a level of the output signal OUT of the present stage is changed into a low level by the control signal so that the present stage is reset.  
         [0138]     In the N-line inversion method, output signals of (N+1)-th stage SRCN+1, ( 2 N+2)-th stage SRC 2 N+2, . . . which are dummy stages are not applied to the scan lines SL 1 , SL 2 , . . . SLn. Each of the output signals of the dummy stages is only applied to the previous stage and the next stage as the control signal and the input signal IN, respectively. In other words, the output signals of the dummy stages are dummy signals.  
         [0139]     According to this exemplary embodiment, the scan driving part  150  has the dummy stages so that a portion of the output signals of the stages SRC 1 , SRC 2 , . . . SRCn+K except the dummy stages SRCN+1, SRC 2 N+2, . . . are applied to the scan lines SL 1 , SL 2 , . . . SLn as the scan signals S 1 , S 2 , . . . Sn.  
         [0140]      FIG. 13  is a plan view showing another exemplary scan driving part of  FIG. 3 .  
         [0141]     Referring to  FIG. 13 , a scan driving part  150 ′ includes a first scan driving portion  155  and a second scan driving portion  156 . The first scan driving portion  155  applies scan signals to odd numbered scan lines SL 1 , SL 3 , . . . SLn−1. The second scan driving portion  156  applies scan signals to even numbered scan lines SL 2 , SL 4 , . . . SLn. The first and second scan driving portions  155  and  156  are adjacent to sides of the LCD panel  190 . In this exemplary embodiment, the first and second scan driving portions  155  and  156  are disposed adjacent to each other.  
         [0142]     The first scan driving portion  155  has a shift register having first stages SRC 1 , SRC 3 , . . . SRC 2   n+ 2K+1. The first stages SRC 1 , SRC 3 , . . . SRC 2   n+ 2K−1 are electrically connected to one another, and in parallel with one another to provide a parallel output shift register. Output terminals of the first stages SRC 1 ,  3  . . . SRC 2   n+ 2K−1 are electrically connected to odd numbered scan lines SL 1 , SL 3 , SLn−1, respectively.  
         [0143]     The second scan driving portion  156  has a shift register having second stages SRC 2 , SRC 4 , . . . SRC 2   n+ 2K. The second stages SRC 2 , SRC 4 , . . . SRC 2   n+ 2K are electrically connected to one another, and in parallel with one another to provide a parallel output shift register. Output terminals of the second stages SRC 2 , SRC 4 , . . . SRC 2   n+ 2K are electrically connected to even numbered scan lines SL 2 , SL 4 , . . . SLn, respectively.  
         [0144]     The first scan driving portion  155  includes a first control stage SCR 2   n+ 2K+1 that applies a control signal to a last stage SRC 2   n+ 2K−1 of the first scan driving portion  155 . The second scan driving portion  156  includes a second control stage SCR 2   n+ 2K+2 that applies a control signal to a last stage SRC 2   n+ 2K of the second scan driving portion  156 .  
         [0145]     The first and second scan driving portions  155  and  156  are independently operated from each other. The first and second scan driving portions  155  and  156  are operated responsive to a modified scan start signal STV′ and first and second clock signals CK 1  and CK 2 .  
         [0146]     In this exemplary embodiment, the second clock signal CK 2  that is applied to the second scan driving portion  156  is delayed by ½H with respect to the first clock signal CK 1  that is applied to the first scan driving portion  155 . The first and second scan driving portions  155  and  156  alternately output odd numbered scan signals and even numbered scan signals to the odd numbered scan lines SL 1 , SL 3 , . . . SL 2   n− 1 and the even numbered scan lines SL 2 , SL 4 , . . . SL 2   n , respectively.  
         [0147]     The first scan driving portion  155  further includes first dummy stages SRC 2 N+1, SRC 4 N+3, . . . SRC 2 KN+2K−1 that generate first dummy scan signals. A number of the first dummy stages SRC 2 N+1, SRC 4 N+3, . . . SRC 2 KN+2K−1 is K. The second scan driving portion  156  further includes second dummy stages SRC 2 N+2, SRC 4 N+4, . . . SRC 2 KN+2K that generate second dummy scan signals. A number of the second dummy stages SRC 2 N+2, SRC 4 N+4, . . . SRC 2 KN+2K is K.  
         [0148]     Output terminals of the first and second dummy stages SRC 2 N+1, SRC 2 N+2, . . . SRC 2 KN+2K−1 and SRC 2 KN+2K are electrically disconnected from the scan lines so that output signals outputted from the first and second dummy stages SRC 2 N+1, SRC 2 N+2, . . . SRC 2 KN+2K−1 and SRC 2 KN+2K are dummy signals.  
         [0149]     Each of the output signals outputted from the first dummy stages SRC 2 N+1, SRC 4 N+3, . . . SRC 2 KN+2K−1 is applied to a previous stage of the first scan driving portion  155  as a control signal and to a next stage of the first scan driving portion  155  as an input signal. Each of the output signals outputted from the second dummy stages SRC 2 N+2, SRC 4 N+4, . . . SRC 2 KN+2K is applied to a previous stage of the second scan driving portion  156  as a control signal and to a next stage of the second scan driving portion  156  as an input signal.  
         [0150]     According to the present invention, the charging rate of each of inverted horizontal lines is uniformized in spite of a voltage drop in the N-line inversion method.  
         [0151]     Therefore, although the display device displays high resolution and high frequency, an image display quality of the display device is improved. In addition, the display device displays a moving image.  
         [0152]     This invention has been described with reference to the exemplary embodiments. It is evident, however, that many alternative modifications and variations will be apparent to those having skill in the art in light of the foregoing description. Accordingly, the present invention embraces all such alternative modifications and variations as fall within the spirit and scope of the appended claims.