Abstract:
An alignment method for successively aligning a plurality of alignment areas of a plurality of successively supplied substrates with predetermined reference positions, includes four processes. The first process measures the positions of the alignment areas of at least a leading one of the substrates with respect to preassigned positions of the alignment areas comprising a preassigned arrangement of the alignment areas to obtain the actual arrangement of the alignment areas. The second process determines conversion parameters, such that when the relationship between the actual arrangement of alignment areas and the preassigned arrangement of alignment areas obtained in the first process is represented by a conversion formula including the conversion parameters and a correction remainder representing the error in the actual arrangement as compared to the preassigned arrangement, the error becomes a minimum. The third process stores error data representing the amount of the error in the measured position of each of the alignment areas measured in the first process with respect to the preassigned positions of the alignment areas using the determined conversion parameters. The fourth process corrects the error data stored in the third process during the alignment of successive substrates by the conversion parameters obtained for the substrates.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an alignment method for precisely aligning a plurality of areas on substrates to be aligned with predetermined reference positions in a device requiring precise alignment, such as a contraction projection type exposure apparatus in which an electronic circuit pattern is projected onto a semiconductor substrate for exposure. 
     2. Description of Related Art 
     The development of highly integrated semiconductors, in recent years, has caused the dimensions of the semiconductor device pattern to be of the order of a submicron, so that technical developments have been carried out extensively for more precise alignment of the mask and the wafer in a semiconductor exposure apparatus. 
     As a semiconductor exposure device, a so-called stepper of the contraction projection type is widely used. FIG. 5a schematically illustrates an example of a contraction projection type semiconductor exposure device. 
     Referring to the figure, a light beam from an exposure illuminating system (not illustrated) illuminates an electronic circuit pattern formed on a reticle R. The illuminated pattern is projected onto a wafer W for exposure through a projection optical system 1. Wafer W is placed on a stage 11 movable two-dimensionally along the X and Y planes. S denotes an alignment optical system, which detects a position along the x dimension in the figure. A similar alignment optical system (not illustrated) is also provided, which detects a position along the y dimension. A CPU 9 (central processing unit) controls the operation of the entire exposure apparatus. 
     The alignment of the wafer W relative to the reticle R is carried out before exposure by the following process. When wafer W is placed onto XY stage 11 by a wafer transporting device (not illustrated), CPU 9 generates a command to a stage driver 10 such that, as illustrated in FIG. 6, alignment marks M1x and M1y of shot area S1 are positioned within the field of view of alignment optical system S, thereby causing XY stage 11 to be driven. An alignment illuminating device 2 irradiates wafer W with a light beam which does not cause exposure nor photosensitization of a resist (photosensitization agent) coated on the wafer W, and the light beam illuminates an alignment mark M1x (hereinafter referred to as wafer mark) through a beam splitter 3, reticle R and projection optical system 1. 
     FIG. 5b illustrates this wafer mark M1x in detail, wherein a plurality of marks having the same rectangular shape are disposed at a constant pitch of λp. A light beam reflected from wafer mark M1x reaches the beam splitter 3 by passing through, once again, projection optical system 1 and reticle R, where it is reflected, and the reflected light passes through an image-forming optical system 4 to form a wafer mark M1x image WM on an imaging surface of an image pick-up device 5. In the image pick-up device 5, the mark M1x image is subjected to photoelectric conversion, and the resultant image is converted into two-dimensional digital signal rows by an A/D (analog-to-digital) converter 6. 
     In FIG. 5a, reference numeral 7 denotes an integrating device, for setting, as illustrated in FIG. 5b, a processing window Wp with respect to wafer mark image WM, converted into a digital signal by A/D converter 6, and performing a movement averaging operation along the Y dimension in FIG. 5b in the aforementioned window to convert the two-dimensional image signal to a one-dimensional digital signal row S(x). 
     In the same figure, reference numeral 8 denotes a position detector in which pattern matching is performed using a previously stored template pattern with respect to the one-dimensional signal row S(x) output from the integrating device 7. The template pattern which matches most closely with the S(x) address position is output to the CPU 9. Since the output signal represents a mark position with reference to an image pick-up plane of the image pick-up device 5, CPU 9 computes position a x1  which is the position of wafer mark M1x along the x dimension with respect to a portion of the reticle R from the relative position of the image pick-up device 5 and reticle R previously obtained from a method which is not illustrated. This completes the measurement for the first measurement shot area along the x dimension. Then, CPU 9 measures the position ay1 along the y dimension of the wafer mark M1y with respect to reticle R using the same process employed to measure the displacement along the x dimension. 
     The CPU 9 causes stage 11 to move to the position of a second measurement shot area S2 to measure the position of wafer marks M 2x  and M 2y  in the x and y dimensions as it has been done for the first measurement shot area S1. The same measurements are performed for the remaining predetermined number of measurement shot areas, n, (n=4 in the example of FIG. 6), and the measured positions for each of the shot areas are stored as a xi , a yi  (where i=1, 2 . . . , n). 
     Then, based on the obtained position of each measurement shot area, the CPU 9 aligns the wafer W relative to the reticle R in the following way. First, a preassigned mark position d i  of the ith measurement shot area is found by the formula 
     
         d.sub.i =[d.sub.xi, d.sub.yi ].sup.T, 
    
     where d xi  represents the preassigned position of the ith shot area along the x dimension, d yi  represents the preassigned position of the ith shot area along the y dimension, and T indicates that the matrix [d xi , d yi  ] is transposed. The preassigned position d i  is superimposed by correction and conversion onto the actual mark position a i  of the ith measurement short area found by the formula 
     
         a.sub.i =[a.sub.xi, a.sub.yi ].sup.T 
    
     which is obtained by wafer mark measurements. As a result, the relationship between a correction position g i  of the ith short area, including a correction remainder e i  of the ith shot area (e i  =[e xi , e yi  ] T ), obtained by the formula 
     
         g.sub.i =[g.sub.xi, g.sub.yi ].sup.T =[a.sub.xi +e.sub.xi, a.sub.yi +e.sub.yi ].sup.T, 
    
     and d i  is expressed by formula (1), 
     
         g.sub.i =Ad.sub.i +S                                       (1) 
    
     so as to allow computation of the conversion parameters A, S such that the sum of the squares of the correction remainder e i  is a minimum, where e i  is the correction of ith shot area in the x and y dimensions, e i  is the correction remainder of the ith shot area along the x dimension, e yi  is the correction remainder of the ith shot area along the y dimension, T indicates that the matrices [a xi , a yi  ] and [e xi , e yi  ] are transposed, g xi  is the correction position of the ith shot area along the x dimension, g yi  is the correction position of the ith shot area along the y dimension, and T also indicates that the matrix [a xi  +e xi , a yi  +e yi  ] is transposed. Based on the conversion parameters A, S, the CPU 9 computes the correction position g i  in accordance with formula (1) to allow the XY stage 11 to be driven in accordance with the correction position g i . This allows step-and-repeat operations to be performed which minimizes the difference between the measured mark position and designed mark position, so that exposure of all shot areas formed on wafer W is performed. 
     Here, A and S are defined as in formula (2): ##EQU1## 
     where αx and αy denote, respectively, the expansion or contraction of each wafer in the x and y dimensions; θ x  and θ y  denote respectively the rotation component of the x and y coordinate axes of the shot arrangement from the preassigned x and y coordinate axes of the shot arrangement as shown by θ and θ+ω in FIG. 8 of U.S. Pat. No. 5,153,678, which is hereby incorporated by reference thereto; s denotes the displacement of the entire wafer from the preassigned position to the measured position, where S x  denotes the displacement of the entire wafer along the x dimension from the preassigned position to the measured position, and S y  denotes the displacement of the entire wafer along the y dimension from the preassigned position to the measured position. 
     According to this method, aligning is performed using a limited number of sample shots, and not by measuring the displacement of all the exposure shots, so that throughput of the device is increased. However, although the relationship expressed by formula (1) is a linear expression representing error components of parallel (translational) movement, rotation, and expansion and contraction of the wafer W, there are some wafers to be processed in the actual semiconductor production process which are partly deformed, so that precise alignment of the entire wafer cannot be obtained by a linear expression. 
     SUMMARY OF THE INVENTION 
     In view of the above-described problem, it is an object of the present invention to provide an alignment method in which high precision alignment can be performed for a substrate for which one linear predetermined conversion formula cannot express the relationship between the measured position of the alignment areas and the preassigned position of the alignment areas. 
     It is still another object of the present invention to provide an alignment apparatus and method for performing alignment of a plurality of substrates, even when deviations occur in each of the substrates from a predetermined conversion formula. 
     According to one aspect, the present invention which achieves at least one of these objectives relates to an alignment method for successively aligning a plurality of alignment areas of a plurality of successively supplied substrates with predetermined reference positions. The plurality of alignment areas of each substrate are formed in accordance with a predetermined arrangement. The method comprises the step of performing a first process of measuring the positions of the alignment areas of at least a leading one of the substrates with respect to the preassigned positions of the alignment areas comprising a preassigned arrangement of the alignment areas to obtain the actual arrangement of the alignment areas. The method also comprises the step of performing a second process of determining conversion parameters such that when the relationship between the actual arrangement of alignment areas and the preassigned arrangement of alignment areas obtained in the first process is represented by a conversion formula including the conversion parameters and a correction remainder representing the error in the actual arrangement as compared to the preassigned arrangement, the error becomes a minimum. The method also comprises a third process of storing error data representing the amount of the error in the measured position of each of the alignment areas measured in the first process with respect to the preassigned positions of the alignment areas using the determined conversion parameters. The method also comprises a fourth process of correcting the error data stored in the third process performing step during alignment of successive substrates by the conversion parameters obtained for the substrates. 
     The fourth process can comprise the steps of determining a weighted function based on an error in the actual arrangement of alignment areas obtained for successive substrates and performing weighting of the error data stored in the third process by the weighted function. In addition, the method can further comprise the step of determining the weighted function by the distance between the position of an alignment area and a grid point used when the conversion parameters are obtained for the leading one of the substrates. In addition, the method can further comprise the step of determining the weighted function by computing the ratio of the error data stored in the third process and the error data obtained for successive substrates. 
     The error, obtained from a predetermined conversion formula, by measuring as many alignment areas as possible in the first and second processes, can be regarded as a correction value obtained by the conversion formula during alignment of substrates of the same lot. Error correction is carried out based on the deviation from the conversion formula of each of the substrates. Therefore, high precision alignment can be insured regardless of the variations of each substrate. 
     In addition, according to one aspect of the invention, the displacement of each of the areas on a substrate can be calculated from a plurality of sample positions and the deviation from a predetermined conversion formula is previously obtained using as many samples as possible for one substrate. This calculated displacement can then be stored for use in correcting the alignment of subsequent substrates. The amount of deviation from the conversion formula is reflected as a weighted value during correction. Therefore, high precision alignment can be obtained even when there is a change in the deviation trend of the alignment areas of each of the substrates from the conversion formula. 
     Other features and advantages of the present invention will become apparent upon reviewing the drawings in conjunction with the detailed description of preferred embodiments provided below. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic view of an exposure apparatus for producing semiconductors to which is applied the present invention. 
     FIGS. 2(a) and 2(b) illustrate sample shot positions on a wafer. 
     FIG. 3 is a schematic representation of the relationship between FIGS. 3A and 3B; FIGS. 3A and 3B are flowcharts illustrating a first embodiment of an alignment method of the present invention. 
     FIG. 4 is a schematic representation of the relationship between FIGS. 4A and 4B; FIGS. 4A and 4B are flowcharts illustrating a second embodiment of an alignment method of the present invention. 
     FIG. 5(a) is a schematic view of a conventional semiconductor exposure apparatus. 
     FIG. 5(b) is a schematic view of a wafer mark image and a processing window. 
     FIG. 6 illustrates sample shot positions of a conventional semiconductor exposure apparatus. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A detailed description will hereunder be given of the present invention with reference to the embodiments illustrated in the drawings. FIG. 1 is a schematic view of an alignment device of a first embodiment of the present invention. Reference numerals and letters that are the same as those used in FIG. 5(a) denote the same or similar elements. 
     Referring to the figure, the functions of alignment optical system S, A/D (analog-to-digital) converter 6, integrating device 7, and position detector 8, are the same as those of the corresponding components in the conventional apparatus shown in FIG. 5(a), so that their details will be omitted here. In the embodiment, a storage device 12 is added to the arrangement of the conventional apparatus. 
     A description will hereunder be given of the alignment method of the embodiment based on the flowcharts illustrated in FIGS. 3A and 3B. If not particularly specified, the determination and control operations are assumed as being executed by a CPU (central processing unit) 9. 
     In Step S101, CPU 9 sends a command to a wafer transporting device (not illustrated) to allow placement of the first wafer W1 of the lot to be processed (e.g. there are about 25 or 50 wafers in one lot to be subjected to the same processing) onto XY stage 11. 
     In Step S102, a determination is made as to whether or not the wafer W1 placed on XY stage 11 is the first wafer of the lot. If it is the first wafer, the process proceeds to Step 103. 
     In Step S103, CPU 9 sends out a command to stage driver 10 to drive the xy stage 11 so that alignment marks M1x and M1y formed at the first measurement shot area S1 of the wafer W1 illustrated in FIG. 2a are positioned within the field of view of alignment optical system S. 
     In Step S104, the light beam generated by the alignment illuminating device 2, which does not cause exposure, passes through the beam splitter 3, the reticle R, and the projection optical system 1 and illuminates alignment marks M1x and M1y. The alignment marks M1x and M1y comprise grids as shown in FIG. 5b. By means of A/D converter 6, integrating device 7, and position detector 8 the displacement of marks M1x and M1y relative to the reticle R is determined by the same method as described in the conventional apparatus. The position a 1   1  is found by: 
     
         a.sup.1.sub.1 =[a.sup.1.sub.x1, a.sup.1.sub.y1 ].sup.T 
    
     where a 1   1  denotes the position, in the x and y directions, of the first shot area S1 of the wafer W1, the number in superscript to the right of &#34;a&#34; representing the number of the wafer, while the number in the subscript represents the number of the shot area. More generally, the reference letters used in the mathematical expressions below denote the same parameters as the corresponding letters discussed above in connection with the FIGS. 5(a) and 6 embodiment, except that the number in superscript represents the number of the wafer. 
     In Step S105, CPU 9 determines whether or not sample measurement is completed. If not, Steps S103 and S104 are repeated for each shot area until sample measurement for wafer W1 is completed. Upon completion, displacement measurement in the x and y dimensions of each of exposure shot areas, S1, S2, S3, . . . , S24 on wafer W1 is completed. The position of each of the shot areas on wafer W1 is illustrated in FIG. 2a. If sample measurement is complete, the process proceeds to Step S106. 
     In Step S106, when preassigned mark position d i , at each measurement shot area (sample), found by the expression 
     
         d.sub.i =[d.sub.xi, d.sub.yi ].sup.T, 
    
     is superimposed onto the actual mark position by correction and conversion of the actual mark displacement a 1   i , obtained by wafer mark measurement and found by the expression, 
     
         a.sup.1.sub.i =[a.sup.1.sub.xi, a.sup.1.sub.yi ].sup.T, 
    
     and when the relationship of correction position g 1   i  obtained by the formula (3) g 1   i  =[g 1   xi , g 1   yi  ] T  =[a 1   xi  +e 1   xi , a 1   yi  +e 1   yi  ] T  (3) and d i  is expressed as g 1   i  =B 1  θ 1  d i  +S 1 , CPU 9 computes conversion parameters B 1 , θ 1 , and S 1 , by which the sum of the squares of correction remainder e i   1  of the ith shot of wafer W1 is a minimum, based on the condition that V becomes a minimum when it is expressed by formula (4) ##EQU2## where B 1 , θ 1 , and S 1  are defined respectively by formula (5) ##EQU3## where β1 x  and β1 y  denote respectively the expansion or contraction of each wafer in the x and y dimensions, and θ 1   x  and θ 1   y  denote respectively rotation components of the x and y coordinate axes of the shot arrangement of wafer W1 from a preassigned x and y coordinate axes of the shot arrangement of wafer W1. S 1  represents the displacement of the entire wafer W1 in the xy plane from a preassigned position to a measured position, S x  denotes the displacement of the entire wafer along the x dimension from the preassigned position to the measured position, and S y  denotes the displacement of the entire wafer along the y dimension from the preassigned position to the measured position. These conversion patterns represent a multiplying factor component, a rotation component, and a displacement-from-parallel position component as important factors causing displacement error of the pattern formed on the wafer W1 from the ideal position. 
     In Step S107, CPU 9 stores in storage device 12 error amount or remainder E 1 , the difference between the correction position g 1   i  obtained by formula (3) with the use of the conversion parameters B 1 , θ 1 , and S 1  and the actual position displacement a 1   i , the remainder E 1  given by formula E 1  =(e 1   1 , e 1   2 , . . . , e 1   24 ). 
     In Step S108, in accordance with the grids obtained by conversion of the preassigned shot arrangement grids (mark position di) converted by the conversion parameters B 1 , θ 1 , and S 1 , CPU 9 instructs stage driver 10 to drive the XY stage 11 to perform step-and-repeat operations, whereby each of the shots on wafer W1 are successively exposed. 
     In Step S109, upon completion of exposure of wafer W1 shots, CPU 9 causes wafer W1 to be stored in a wafer storage carrier (not illustrated) by so instructing a wafer transporting device. Then, CPU 9 causes the process to return to Step S101 and instructs the wafer transporting device to place the wafer W2 to be processed next onto XY stage 11. When the wafer is not the first wafer of the lot, the process proceeds to Step S110. 
     In Step 110, CPU 9 sends a command to stage driver 10 to drive xy stage 11 so that alignment marks M2x and M2y formed at shot area S2 illustrated in FIG. 2b are positioned within the field of view of the alignment optical system 2. 
     In Step S111, CPU 9 measures the position a 2   2  of the marks M2x and M2y relative to the reticle R by the same method described in Step S104, which is found by the formula 
     
         a.sup.2.sub.2 =[a.sup.2.sub.x2, a.sup.2.sub.y2 ].sup.T 
    
     In Step 112, as in the first case, with wafer W1 CPU 9 causes Steps S110 and S111 to be repeated, in which alignment marks for shot areas 2, 4, 12, 13, 21, and 23 on wafer W2 are successively measured, until sample measurement is completed. Then, the position A 2  of each of the shot areas is measured by formula (6): 
     
         A.sup.2 ={k | a.sup.2.sub.k, where k=2, 4, 12, 13, 21, 23}, where k identifies the shots that are measured.                 (6) 
    
     In Step 113, based on the position A 2  at each of the measurement shot areas obtained from Steps S110 to S112, CPU 9 determines conversion parameters B 2 , θ 2 , and S 2  by the same method as that performed in Step 106. 
     In Step S114, when CPU 9 corrects the grid position based on formula (3) using the obtained conversion parameters B 2 , θ 2 , and S 2 , the non-linear error amount E 2  is obtained from the corrected grid positions at each of the measurement shot positions using formula (7) 
     
         E.sup.2 ={k | e.sup.2.sub.k, where k=2, 4, 12, 13, 21, 23}(7) 
    
     Then, from this and the non-linear error amount E 1 , previously stored in storage device 12, formula (8) is used to calculate a weighted coefficient W: ##EQU4## where e 1   k  is the correction remainder of the kth shot area of wafer W1 and e 2   k  is the correction remainder of the kth shot area of wafer W2. 
     The coefficient W is the ratio of the nonlinear component correction remainder of the shot arrangement on wafer W2 and the nonlinear component of the correction remainder of the shot arrangement on wafer W1. 
     In Step S115, based on the conversion parameters obtained in Steps S113 and S114, CPU 9 instructs the stage driver 10 to drive the xy stage 11 to perform step-and-repeat operations so that all of the shot areas are subjected to exposure in accordance with the shot arrangement on wafer W2 as the grid marks obtained by correction of the preassigned arrangement grids are corrected by the following formula (9), where i=(1, 2, . . . , 26): 
     
         g.sup.2.sub.i =B.sup.2 θ.sup.2 d.sub.i +S.sup.2 +We.sup.1.sub.i(9) 
    
     In Step S116, CPU 9 sends a command to the wafer transporting device to allow storage of wafer W2 in a wafer storage place. 
     In Step S117, the third and subsequent wafers are subjected to measurement by the same process as that performed on W2 until all of the wafers in the same lot have been processed to perform step-and-repeat exposure thereof. 
     CPU 9 allows previous storage of the number of wafers in a lot. When the lot of the wafers changes, the nonlinear component error of the first wafer is measured and stored as has been done for that of wafer W1, and this process is repeated for the remaining wafers of the same lot as has been done for wafer W2. 
     Although in the first embodiment, coefficient W with respect to the nonlinear component is obtained from the average of each of the nonlinear components, i.e., the correction remainder, and this obtained value is used as a constant value for each of the individual wafers, a coefficient in accordance with each shot position during exposure may also be obtained. With reference to the flowchart of FIG. 4, a description will be hereunder given of such an alignment method of a second embodiment of the application. It is to be noted that Steps S100 to S113 are the same as those of the first embodiment, so that detailed descriptions of these steps will not be repeated. 
     In Step S118, based on an error amount E 2  given by formula (10) 
     
         E.sup.2 ={k | e.sup.2.sub.k, where k=2, 4, 12, 13, 21, 23}(10) 
    
     and obtained from the corrected grid marks at each measurement shot position as a result of grid mark correction carried out using the conversion parameters B 2 , θ 2 , and S 2  obtained in Step S113, and error amount E 1  obtained in Step S107, where k=2, 4, 12, 13, 21, 23, a spline function f 2  which satisfies the formula (11) ##EQU5## is obtained. This calculated value is stored in an internal memory of the CPU 9 or storage device 12 as a weighted function related to wafer W2. It is to be noted that (x k , y k ) are coordinate values of the kth preassigned shot. 
     In Step S119, from the conversion parameters and weighted function f 2  obtained respectively in Steps 113 and 118, CPU 9 defines the wafer W2 shot arrangement as a correction grid position g 2   i  of the ith shot of the wafer W2 in which the preassigned arrangement grid point position has been corrected by the following formula (12), where i=(1, 2, . . . , 24). According to this position, all of the shot areas are exposed while XY 11 stage performs step-and-repeat operations. 
     
         g.sub.2.sup.i =B.sup.2 θ.sup.2 d.sub.i +S.sup.2 +f.sup.2 (x.sub.i, y.sub.i)e.sup.1.sub.i                                     (12) 
    
     In this case, since each of the shot grid points is weighted based on weighted function f 2  representing the distribution of the ratio of the amount of error obtained for wafer W2 and that obtained for wafer W1, changes in the nonlinear component of wafer W2 with respect to wafer W1 are also taken into consideration, so that high precision alignment can be performed. 
     Subsequently, Step S116 and onwards are repeated as has been performed in the first embodiment until all of the wafers of the same lot have been measured and subjected to step-and-repeat exposure.