Abstract:
The receiver comprises a 90° hybrid and analog-to-digital convertersetween the RF section and digital processing; which makes it possible to eliminate a phase correlator, four diode detectors and two differential amplifiers used in previous IFM receivers to obtain the sine and cosine signal samples at an initial time and at a delayed time.

Description:
RIGHTS OF THE GOVERNMENT 
     The invention described herein may be manufactured and used by or for the Government of the United States for all governmental purposes without the payment of any royalty. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates generally to the field of instantaneous frequency measurement (IFM) receivers with digital processing. 
     The conventional IFM receiver is a radio frequency receiver used primarily in electronic warfare. Its basic function is to measure the frequency of pulsed signals radiated from hostile radar. Generally, it may be said that IFM receivers measure the frequencies of incoming RF signals utilizing interferometric techniques by detecting the phase shift magnitudes produced in multiple, calibrated delay lines. For instance, the received RF signal is divided and simultaneously introduced into a non-delayed path and a delay line of known length. Since the phase differences between the delayed and non-delayed receiver paths are functions of the input signal frequency, conversion of the phase difference signals to video signals provides signals whose amplitudes are related to phase delay. These video signals typically take the form sin ωτ or cos ωτ, where ω is the angular frequency of the processed input signal. The sin ωτ and cos ωτ signals are delivered to an encoding network which makes amplitude comparisons of the signals, determines the numerical value of ω, and generates the digital frequency descriptive word. 
     An IFM receiver has many attractive features necessary for electronic warfare applications, such as small size, light weight, wide instantaneous bandwidth, and fine frequency resolution. 
     Typical IFM receivers are shown in U.S. Pat. Nos. 3,939,411 to James, and 4,336,541 and 4,426,648 to Tsui and Shaw. Other U.S. patents of interest are U.S. Pat. Nos. 4,021,804 to Dounce et al; 4,268,279 to Hines; 3,431,405 to Dawson; and 4,364,048 to Waters et al. 
     SUMMARY OF THE INVENTION 
     An object of the invention is to simplify the design of IFM receivers. 
     An IFM receiver according to the invention comprises a 90° hybrid and analog-to-digital converters between the RF section and digital processing; which makes it possible to eliminate a phase correlator, four diode detectors and two differential amplifiers used in previous IFM receivers. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram of a prior art IFM receiver; and 
     FIGS. 2 and 3 are diagrams of IFM receivers with A/D converters. 
    
    
     DETAILED DESCRIPTION 
     Referring to FIG. 1, a typical conventional prior art IFM receiver consists of an RF section comprising an amplifier-limiter combination 12 with input from an antenna 10, a power splitter 14, an RF delay line 16, a phase correlator or phase discriminator 18, diode detectors D1-D4, differential amplifier comparators 20,22 and logic circuits 24. The frequency in digital format is supplied from the logic circuits 24 to utilization circuits 26. An input signal passing through the RF section is separated into two parts: one proceeds directly to the phase discriminator 18, the other passes through the delay line 16 before proceeding to the phase discriminator 18. At the outputs of the discriminator there are four diode detectors followed by comparators 20,22 and logic circuits 24 (which may include a memory). 
     The phase correlator 18 is used to provide the necessary phase shift to the input signals and combine the signals to certain desired forms at its four outputs, and each of them is followed by a diode detector. The diode detectors D1-D4 convert the RF signals into video signals and at the same time perform mathematical squaring to the input signals. The outputs of the detectors D1-D4 are connected to the inputs of two differential amplifiers 20 and 22. Each differential amplifier amplifies the difference of its two input signals. The outputs of the differential amplifiers are sin ωτ and cos ωτ, where ω is the input angular frequency and τ is the delay time of the delay line 16. The logic circuits 24 following the differential amplifiers digitize the outputs and further process the data to generate the frequency information. 
     An IFM receiver according to the invention simplifies the design by eliminating the phase correlator, four diode detectors and two differential amplifiers of FIG. 1, and substitutes analog-to-digital converters followed by digital processing to perform the functions. 
     As shown in FIGS. 2 and 3, the IFM receiver has the same amplifier-limiter combination 12 as in FIG. 1, and has the output in the same digital format for supply to the utilization circuits 26. The circuit now includes a 90° hybrid, and analog-to-digital (A/D) converters. The input signal from the amplifier-limiter combination 12 passes through the 90° hybrid 34. The outputs are sin ωτ and cos ωτ. FIG. 2 shows two A/D converters 36 and 38 to digitize these outputs at time t 1 , and then at time (t 1  +τ). If the A/D converters are too slow to sample at time τ apart, then four A/D converters 56-59 can be used as shown in FIG. 3. In that case, two of the A/D converters 56 and 58 will sample at time t 1 , and the other two 57 and 59 will sample at time (t 1  +τ). In both of FIGS. 2 and 3, there are four A/D converter outputs listed as: 
     
         A=sin ωt.sub.1                                       (1) 
    
     
         B=cos ωt.sub.1                                       (2) 
    
     
         C=sin (ωt.sub.1 -ωτ)                       (3) 
    
     
         D=cos (ωt.sub.1 -ωτ)                       (4) 
    
     The above four equations are combined as follows: ##EQU1## The mathematical operations for equations (5) to (8) can be performed by properly programmed read only memories (ROMs) in the logic unit 44. The frequency from the memory appears at the output of the logic unit 44 in digital format. 
     It is understood that certain modifications to the invention as described may be made, as might occur to one with skill in the field of this invention, within the scope of the appended claims. Therefore, all embodiments contemplated hereunder which achieve the objects of the present invention have not been shown in complete detail. Other embodiments may be developed without departing from the spirit of the invention or from the scope of the appended claims.