Abstract:
A method and apparatus to improve modulation efficiency. A symbol is created in which the relative position of a second pulse is a symbol period encode at least one bit. The symbol is transmitted across a communication channel. The one or more bits modulated by the position of the second pulse are recovered such that high bit rate communication may occur without channel compensation.

Description:
BACKGROUND  
         [0001]    1. Field  
           [0002]    Embodiments of the invention relate to modulation. More specifically, embodiments of the invention relate to an improved encoding density modulation scheme.  
           [0003]    2. Description of the Related Art  
           [0004]    Various forms of modulation have long been used to encode data with greater efficiency so that more data can be transmitted during a particular time period over a transmission medium. Combinations of various modulation techniques such as, pulse width modulation, amplitude modulation and rise time modulation have been employed to improve the encoding density of modulation schemes. See for example, copending application entitled “Symbol-Based Signaling For An Electromagnetically-Coupled Bus System,” Ser. No. 09/714,244. However, such schemes often require per-emphasis and channel equalization which increases the cost and complexity of the system. Moreover, in any event it remains desirable to improve coding density to allow for even higher bit rates. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]    [0005]FIG. 1 is a diagram showing a generalized format of a symbol of one embodiment of the invention.  
         [0006]    [0006]FIG. 2 is a diagram showing the modulation elements of symbol of one embodiment of the invention that encodes eight databits.  
         [0007]    [0007]FIG. 3 a - 3   e  are diagrams of possible symbols to encode eight bits per symbol.  
         [0008]    [0008]FIG. 4 is a block diagram of a modulator of one embodiment of the invention.  
         [0009]    [0009]FIG. 5 is a block diagram of the demodulator of one embodiment of the invention.  
         [0010]    [0010]FIG. 6 is a block diagram of the system incorporating one embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0011]    [0011]FIG. 1 is a diagram showing a generalized format of a symbol of one embodiment of the invention. The symbol  100  occurs within a symbol period (T p )  106 . The symbol includes a first pulse  102  alternatively referred to as a basic pulse  102  and N additional pulses  104 . In FIG. 1 N is equal to one, however, N could be any positive integer. Additional pulses are alternatively referred to herein as IDP pulses  104 .  
         [0012]    The basic pulse  102  includes i leading slots  112 , where i is a positive integer, a base pulse  114  and j lagging slots  116 , where j is also a positive integer. The IDP pulse  104  includes a base pulse  118  and m lagging slots where m is a positive integer. Notably, i, j and m are not necessarily equal. In FIG. 1, T fx  is the width of a leading slot  112 , T bx  is a width of the lagging slot  116  (alternatively referred to as front end slots and back end slots respectively) of the basic pulse  102  and T IDP  is a width of the lagging slot  120  of the IDP pulse  104 . The slot width between leading slots and lagging slots and between the pulses may not be equal.  
         [0013]    T SB  is the width of the base pulse  114  of the basic pulse  102 . T IDP  is the width of the base pulse  118  of the IDP pulse. T SB  and T SIDP  are selected in one embodiment to be the minimum pulse that can be properly propegated along the communication channel without the necessity of channel compensation such as equalization. The basic pulse  102  is separated from the IDP pulse  104  by a gap with T g1 .  
         [0014]    If additional IDP pulses are present within the symbol period, they will each be separated from their predecessor by a gap. It is not necessary that all additional pulse have a same format. As used herein, format refers to the base pulse and lagging slots. Thus, a same format has an equal number and equal size of slots and a same width base pulse. Thus, where m x ≠m y  a different format exists, where x &amp; y refer to distinct additional pulses. A final gap occurs after the last IDP pulse  104 , in this case, having a gap width T g2 . Amplitude modulation (AM) can be used separately on each pulse. This provides two bits of modulation (one per pulse) if return to zero (RZ) AM is used or four bits of modulation (two per pulse) if non return to zero (NRZ) AM is used.  
         [0015]    [0015]FIG. 2 is a diagram showing the modulation elements of a symbol of one embodiment of the invention that encodes eight data bits. P 1  is the possible starting position of the front edge of the basic pulse. A 1  is the possible polarization of the basic pulse. P 2  is the possible back edge position of the basic pulse. PP 2  is a possible starting position of the base pulse of the IDP pulse. A 2  is the possible polarization of the IDP pulse. P 3  is the possible position of the back edge of the IDP pulse. In this case, referring back to the nomenclature of FIG. 1, i equals 1, j equals 3 and m equals 4.  
         [0016]    [0016]FIGS. 3 a - 3   e  are diagrams of possible symbols to encode eight bits per symbol in accordance with modulation elements discussed in connection with FIG. 2. As can be seen, the relative position of the base pulse of the IDP pulse varies within the symbol period. This variance of the position of the base pulse of the IDP pulse encodes at least one bit, and in this example, two bits of data. Stated slightly differently, the relationship between the pulses improves modulation efficiency. The position the IDP pulse may assume depends on the duration of the basic pulse. The IDP pulse is thus moveable within the symbol period T p . Conversely, in one embodiment, the location of the base pulse of the basic pulse is fixed within T p .  
         [0017]    In this 8-bit modulation example, two bits are associated with the amplitude modulation (one for basic pulse the other for IDP pulse). This assumes RZ AM. One bit is modulated by the front edge of basic pulse. Five bits are modulated by the combinations of the basic pulse and the IDP pulse. In FIG. 3 a , two bits are modulated by the back edge of basic pulse and one bit is modulated by back edge of IDP pulse, which yields eight possible states. In FIG. 3 b , the combination of basic pulse&#39;s back edges (three edge positions) and the IDP pulse&#39;s back edges (three edge positions) results in total of nine states. FIG. 3 c  yields eight states, similar to FIG. 3 a . FIG. 3 d, e  provide an additional eight possible states. The total combinations for FIGS. 3 a - e , provide more than 32 states for five bits of modulation. These states are addressed further below in connection with Tables 6-10.  
         [0018]    Tables 1 through 5 show one possible mapping of the data to the symbols shown in FIGS. 3 a - 3   e  respectively.  
                           TABLE 1                                       D 0     A1 (1 = HIGH, 0 = LOW)           D 1     P1 (0 = edge_0, 1 = edge_1)           D2 = 0   PP2           D3 = 0   PP2           D4   P2           D5   P2           D6   A2 (1 = HIGH, 0 = LOW)           D7   P3                      
 
         [0019]    [0019]                           TABLE 2                                       D0   A1 (1 = HIGH, 0 = LOW)           D1   P1 (0 = edge_0, 1 = edge_1)           D2 = 1   PP2           D3 = 0   PP2           D4   P2 &amp; P3           D5   P2 &amp; P3           D6   P2 &amp; P3           D7   A2 (1 = HIGH, 0 = LOW)                        
         [0020]    [0020]                           TABLE 3                                       D0   A1 (1 = HIGH, 0 = LOW)           D1   P1           D2 = 0   PP2           D3 = 1   PP2           D4   P2           D5   A2 (1 = HIGH, 0 = LOW)           D6   P2           D7   P3                        
         [0021]    [0021]                           TABLE 4                                       D0   A1 (1 = HIGH, 0 = LOW)           D1   P1           D2 = 1   PP2           D3 = 1   PP2           D4 = 0   P2           D5   A2 (1 = HIGH, 0 = LOW)           D6   P3           D7   P3                        
         [0022]    [0022]                           TABLE 5                                       D0   A1 (1 = HIGH, 0 = LOW)           D1   P1           D2 = 1   PP2           D3 = 1   PP2           D4 = 1   P3           D5   P2           D6   P2           D7   A2 (1 = HIGH, 0 = LOW)                        
         [0023]    One of ordinary skill will recognize that various other mappings are possible and are within the scope and contemplation of embodiments of the invention.  
         [0024]    Referring again to FIGS. 3 a - e , in one embodiment, the symbol period, TP is 2000 ps. T LEAD  (width of the leading slot) is 240 ps, T s  is 320 ps T LAG  (width of the lagging slot for both pulses) is 160 ps, and the gap width T gap  is 240 ps. In such an embodiment, data rates of 4 Gbps can be achieved on a 30″ channel with two ball grid array (BGA) packages and two connectors. A wide leading slot is used because the leading edge of the first pulse is most effected by what occurred on the channel previously. Thus, by making the slot wider, it is less likely that channel noise will cause a misinterpretation of the location of the front edge.  
         [0025]    In an alternative embodiment, TP is 1250 ps with T LEAD  is 130 ps, T s  is 200 ps, T LAG  is 110 and T gap  is 140. This permits data rates of 6.4 Gbps on a 5″ channel.  
         [0026]    In an alternative embodiment, TP is 1000 ps. T LEAD  is 110 ps, T s  is 135 ps, T LAG  is 100 ps and T gap  is 110 Ps. This embodiment permits data rates of 8 Gbps on a 5″ channel.  
         [0027]    [0027]FIG. 4 is a block diagram of a modulator of one embodiment of the invention. A three width bits wb 0  through wb 2  and the two IDP front edge bits IDPFE 0  and IDPFE 1  provide the inputs to the state control unit  402 . Based on these inputs, the state control unit enables or disables various signal paths through the modulator and therefore frequency controls the pulses created by the electric pulse generation units to form the symbol. The various signal paths are driven through a plurality of delays to effect the creation of the symbols of the forms previously described. Tables 6-10 show the response of the state control unit  400  based on the inputs. In these tables “0” means pass and “1” means stop.  
                                                                                                                 TABLE 6                       IDPFEO   IDPFE1   Wb0   Wb1   Wb2   SB0   SB1   SB2   SB3   SI0   SI1   SI2   SI3                   19.   0   0   0       0   1   1   1                            (Enable)   0   1       1   0   0   1                           1   0       1   1   0   1           1   1       1   1   1   0                   0                   0   1   1   1                   1                   1   0   1   1                  
 
         [0028]    [0028]                                                                                                                 TABLE 7                       IDPFEO   IDPFE1   Wb0   Wb1   Wb2   SB0   SB1   SB2   SB3   SI0   SI1   SI2   SI3                   1.   1   0   0   0   0   1   1   1   0   1   1   1            (Enable)   0   0   0   0   1   1   1   1   1   1   1           0   1   0   0   1   1   1   1   1   0   1           0   1   1   1   0   1   1   0   1   1   1           1   0   0   1   0   1   1   1   0   1   1           1   0   1   1   0   1   1   1   1   0   1           1   1   0   1   1   0   1   0   1   1   1           1   0   1   1   1   0   1   1   0   1   1                    
         [0029]    [0029]                                                                                                                 TABLE 8                       IDPFEO   IDPFE1   Wb0   Wb1   Wb2   SB0   SB1   SB2   SB3   SI0   SI1   SI2   SI3                   20.   0   0   0                       0   1   1   1            (Enable)   0   0                       0   1   1   1           1   0                       1   1   0   1           1   1                       1   1   1   0                   0   0   1   1   1                   1   1   0   1   1                    
         [0030]    [0030]                                                                                                                 TABLE 9                       IDPFEO   IDPFE1   Wb0   Wb1   Wb2   SB0   SB1   SB2   SB3   SI0   SI1   SI2   SI3                   21.   1   0   0   0   0   1   1   1   0   1   1   1            (Enable)       0   0   0   1   1   1   0   1   1   1               1   0   1   1   0   1   0   1   1   1               1   1   1   1   1   0   0   1   1   1           1   0   0   0   1   1   1   0   1   1   1               0   1   0   1   1   1   1   0   1   1               1   0   0   1   1   1   1   1   0   1               1   1   0   1   1   1   1   1   1   0                    
         [0031]    [0031]                                           TABLE 10                       IDPFEO   IDPFE1   Wb0   SIFE0   SIFE1   SIFE2   SIFE3   SIFE4                   0   0       1   1   1   0   1       0   1       1   1   0   1   1       1   0       1   0   1   1   1       1   1   0   0   1   1   1   1       1   1   1   1   1   1   1   0                    
         [0032]    Tables 6-9 define the back edge modulation for the basic pulse (SBO-SB 3 ) and the IDP pulse SIO-SI 3 . Table 10 defines the IDP pulse front edge delay states. In the aggregate, the states provide for modulation consistent with the mappings of Tables 1-5, and are implemented by state control  402  in one embodiment. Matching logic  410  insures that the forwarded clock is time consistent with the symbol generated.  
         [0033]    [0033]FIG. 5 is a block diagram of the demodulator of one embodiment of the invention. The data is received in input  518  while the forwarded clock is received at clock recovery circuit  520 . The clock is recovered in the clock recovery circuit  520  and passed into the demodulator as shown. The data is similarly forwarded into the demodulator as shown. Comparison of delayed data with the AM threshold and the clock yield the two AM bits and the front edge bit of the basic pulse via a bit mapping unit  526 . Comparison of the data with various levels of delay of the clock yields the two IDP front edge bits via bit mapping unit  524 . Delays of the clock compared with the data signal also fed into state mapping units  528  and  530  which then provides their state information to bit mapping unit  532  which in turn yields the width bits wb 0  through wb 2 . The state control unit  522  insures that the bit mapping unit  532  outputs the right bits base on the state and the group defined by the position of the IDP pulse.  
         [0034]    [0034]FIG. 6 is a block diagram of the system incorporating one embodiment of the invention. The processor  600  includes a modulator  400  and demodulator  500 . The processor is coupled to a chip set  602  which is coupled to a memory bus  612  and an I/O bus  610 . The chip set includes a memory controller  614  which also includes a modulator  400  and a demodulator  500 . The memory controller interacts with the memory  604  over memory bus  612 . In such an embodiment, the memory interface may may or may not include a modulation  400  and demodulator  500 , as a benefit is achieved even where only the communication between the processor  600  and the memory controller  600  occurs at the high speeds provided by the described modulation scheme. An I/O device  606  which also contains a modulator  400  and a demodulator  500  is coupled to I/O bus  610  and may receive symbols modulated as previously described such that a position of an additional pulse within the symbol period encodes at least one bit. The I/O device may include, for example, a disk controller.  
         [0035]    In another embodiment, the memory controller is embedded in the processor. Such an embodiment may or may not have a chip set, but in any event, the memory interface would need to have the corresponding modulator/demodulator to gain a benefit of the described modulation technique during memory accesses. Also, in such an embodiment (assuming a chip set is present) the chip set need not have the modulator and demodulator for a benefit to be realized.  
         [0036]    In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes can be made thereto without departing from the broader spirit and scope of embodiments of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.