Abstract:
A processor, a multiprocessor, and a debugging method for solving the conventional problems, one of which is very difficult to switch among debug programs and start the selected program within a certain time. The above convention problem can be solved by a processor that includes a debug unit block, a multimode debug interrupt control block, and an execution block. The debug unit block monitors the execution of the debug target user program and issues a debug interrupt when a predetermined debug condition is satisfied. The control block, upon receiving such a debug interrupt, specifies a debug mode that selects a predetermined debug program. When the debug unit block issues such a debug interrupt, the execution block selects and executes a debug program according to the debug mode specified by the control block.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to a processor, a multiprocessor, and a debugging method. 
       BACKGROUND OF THE INVENTION 
       [0002]    In recent years, along with the appearance of highly enhanced and high performance vehicle control units and mobile phones, the software of the microcomputers built in those units and devices have been expanded in scale and become complex in function. And in order to debug the software programs of those built-in microcomputers, task debuggers have been developed so as to efficiently cope with debugging of tasks on their operating systems (OS) respectively. A task debugger sets break points in the debug target task, thereby stopping the task and check the memory contents, etc. at each of those set break points. 
         [0003]    There is a well-known invention that provides such a task debug function, as well as a system debug function that stops the while target system. JP-A-2006-079261 discloses such an invention “Program Debugging Method”. According to the invention, a debugger sends a debug command to a target system that includes two debug programs. When the target system receives the debug command, a monitor management program of the system switches between those two debug monitoring programs. This method can realize both of task debugging that stops only the target task and system debugging that stops the whole system in the same debugging environment. 
       SUMMARY 
       [0004]    Control object systems of such built-in type microcomputers are very complicated. A debugging method referred to as bypass emulation is usually employed for debugging in order to develop such control object systems efficiently; part of the object algorithm is executed by an externally provided alternative high performance general computer in this case. 
         [0005]      FIG. 1  shows a diagram for describing such bypass emulation. As shown in  FIG. 1 , the bypass emulation uses an external computer to bypass some processings. If a break is detected in the bypass emulation, control is passed to an alternative program (debug program) from the user program. The microcomputer then executes the alternative program and outputs the input values of the bypass processings to the external computer (STEP  00 ). The external computer then executes [processing  1 ], [processing  2 ], and [processing  3 ] respectively and returns the results of those processings to the microcomputer. The microcomputer then executes the alternative program and fetches the operation results output from the external computer (STEP  99 ). Here, the alternative program returns control to the user program. 
         [0006]    Under such circumstances, there has been a demand for constructing a debugging environment so as to realize a debug function that executes such bypass emulation, as well as other debug functions. According to the technique disclosed in the JP-A-2006-079261, however, it has been confronted with a problem that it is very difficult to execute such bypass emulation within a fixed time. In case of the technique disclosed in the JP-A-2006-079261, for example, when switching is made from system debugging to task debugging, the user is required to operate the debugger to send the object debug command. Furthermore, in the target system, the monitoring management program is required to switch between the two debug programs. Therefore, the bypass emulation cannot be started before the switching by the monitoring management program is ended. As a result, the response is delayed so much, thereby it becomes very difficult to keep normal operations in the control object system. 
         [0007]    Furthermore, in case of the technique disclosed in the JP-A-2006-079261, when one debug program is switched to the other, the user is required to operate the debugger to send the debug command. Consequently, the user is further required to operate the debugger properly to determine which specific part of the object user program should be related to its corresponding specific debug program. And this is why it has been impossible to relate a specific operation in the user program to bypass emulation. This has been a problem. 
         [0008]    Furthermore, in case of the multiprocessor type microcomputer, one processor executes one user program while the other processor executes the other user program. 
         [0009]    Consequently, if the technique of the JP-A-2006-079261 is applied to such a multiprocessor type microcomputer, it is very difficult to assure matching between the debug mode of one processor and the debug mode of the other processor. This is why the technique cannot cope with the simultaneous breaking (also referred to as a synchronous breaking) to be executed in such a multiprocessor type microcomputer so easily. 
         [0010]    Hereunder, there will be described “means for solving the problem” with reference to the numbers/reference numerals used in “best mode for carrying out the invention”. Those numbers/reference numerals are put in parentheses to clarify the correspondence between the description of “what is claimed is” and the description of “the best mode for carrying the invention”. Those numbers/reference numerals cannot be used to describe the technical field of the invention described in “what is claimed is”. 
         [0011]    The processor in the first aspect of the present invention includes a debug unit block (B 2 ), a multimode debug interrupt control block (B 6 ), and an execution block (B 7 ). The debug unit block (B 2 ) monitors the execution of a user program to be debugged and issues a debug interrupt to the user program when a predetermined debug condition is satisfied. The multimode debug interrupt control block B 6 , upon receiving the debug interrupt, specifies a debug mode used to select a predetermined debug program. The execution block B 7  then selects and executes a debug program according to the debug mode specified by the multimode debug interrupt control block B 6  when the debug unit block B 2  issues a debug interrupt to the user program. 
         [0012]    The processor in the second aspect of the present invention includes one processor (B 100 - 1 ) having the above first aspect property and another processor (B 100 - 2 ). 
         [0013]    The multimode debug interrupt control block (B 106 - 1 ) of the processor (B 100 - 1 ), if a debug interrupt is generated in the processor (B 100 - 1 ), specifies the same debug mode as that of the processor (B 100 - 1 ) for the multimode debug interrupt control block (B 106 - 2 ) in the processor (B 100 - 2 ) and sends a simultaneous break interrupt that executes a simultaneous debug interrupt to the control block (B 106 - 2 ). The multimode debug interrupt control block (B 106 - 2 ) of the processor (B 100 - 2 ), when receiving the specified debug mode and a simultaneous break interrupt from the multimode debug interrupt control block (B 106 - 1 ) in the processor (B 100 - 1 ), executes the debug interrupt in another processor (B 100 - 2 ) and specifies the same debug mode as that in one processor (B 100 - 1 ) for the execution block (B 7 - 2 ) in another processor (B 100 - 2 ). 
         [0014]    The debug method in the third aspect of the present invention includes: applying a debug interrupt; specifying a debug mode, and executing the debug mode. In the applying of a debug interrupt, in the processor (B 0 ), the execution of the user program to be debugged is monitored and a debug interrupt is issued to the user program when a predetermined debug condition is satisfied. In the specifying of a debug mode, in the processor (B 0 ), a debug mode used to select a predetermined debug program is specified in response to the received debug interrupt. In the executing of a predetermined debug program, in the processor (B 1 ), a predetermined debug program is selected and executed in the debug mode specified in response to the received debug interrupt. 
         [0015]    According to the present invention, it is therefore possible to prepare plural debug modes and quickly switch to a predetermined debug program. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]      FIG. 1  is a block diagram for describing bypass emulation; 
           [0017]      FIG. 2  is a block diagram for describing a configuration of a processor in an embodiment; 
           [0018]      FIG. 3  is a block diagram for describing a configuration of the processor B 0  in the first embodiment; 
           [0019]      FIG. 4  is a block diagram for describing a detailed configuration of a multimode debug interrupt control block; 
           [0020]      FIG. 5  is a block diagram for describing a detailed configuration of an execution block; 
           [0021]      FIG. 6  is a block diagram for describing a configuration of a multiprocessor in the second embodiment; and 
           [0022]      FIG. 7  is a block diagram for describing a configuration of a multimode debug interrupt control block corresponding to the multiprocessor in the second embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0023]    Hereunder, there will be described a preferred embodiment of the present invention with reference to the accompanying drawings.  FIG. 2  is a block diagram for describing a configuration of a processor in one of the embodiments of the present invention. In  FIG. 2 , one or plural debug conditions (hereunder, also to be referred to as break points/break conditions) can be set in the user program. In  FIG. 2 , five break points are set. Each break point can be related to a predetermined debug program. A processor  10  corresponds to plural debug modes and can access any of memory areas that store plural types of debug programs W, X, Y, and Z, respectively. 
         [0024]    As shown in  FIG. 2 , the processor  10  in this embodiment includes a debug unit block  11 , a multimode debug interrupt control block  12 , and an execution block  13 . The debug unit block  11  monitors the execution of the user program. The debug unit block  11 , when detecting a set break point, issues a debug interrupt corresponding to the break point. In  FIG. 2 , three types of debug interrupts α, β, and γ are defined. The multimode debug interrupt control block  12 , when accepting a debug interrupt from the debug unit block  11 , specifies the debug mode corresponding to the debug interrupt type. The execution block  13  then selects and executes a debug program according to the specified debug mode. 
         [0025]    For example, if the user program developer operates an operation for setting a break α in the 1000th step in the user program as shown in  FIG. 2 , the debug unit block  11  stores the set content and issues the debug interrupt α when the 1000th step is executed. The multimode debug interrupt control block  12  stores the data denoting the correspondence of each debug program to the debug interrupt “α” beforehand. Therefore, when accepting the debug interrupt α, the control block  12  specifies the debug mode of the debug program W according to the specified data. The execution block  13  then selects and executes the debug program W in the specified debug mode. 
       First Embodiment 
       [0026]    Hereunder, there will be described the embodiments of the present invention in detail.  FIG. 3  is a block diagram of a processor B 0  with respect to its configuration employed in the first embodiment. As shown in  FIG. 3 , the processor B 0  includes a multimode debug interrupt control block B 6 , an execution block B 7 , and a debug unit block B 2 . In  FIG. 3 , ICE (In-Circuit Emulator (registered trademark)) B 1  denotes an external unit to be operated by the user. 
         [0027]    In  FIG. 3 , the debug unit block B 2  controls the resources provided in the processor B 0  according to the instruction, etc. received from the ICE B 1  to realize the object debug function. The debug unit block B 2  communicates with the ICE B 1  and uses an ICE interface input signal S 11  and an ICE interface output signal S 12  to set a debug condition for the user program. In the debug unit block B 2  in this first embodiment are set two types of debug conditions (one debug condition x for generating the first type break interrupt α and the other debug condition y for generating the second type break interrupt  1 ). The debug unit block B 2  monitors the user program executed by the execution block B 7  and issues a break interrupt a to the program if the debug condition x is satisfied and issues a break interrupt β to the program if the debug condition y is satisfied. 
         [0028]    The execution block B 7  has functions for selecting and executing any one of the debug object user program, the runtime debug program for bypass emulation, and the normal debug program. The execution block B 7 , upon receiving a break interrupt request signal S 3 , selects the address of the runtime debug program storage area B 4  or the normal debug program storage area B 5  according to the break interrupt factor information S 5 . Then, branching to the selected address, the execution block B 7  fetches and executes the object debug program instruction. 
         [0029]    The multimode debug interrupt control block B 6  can accept plural types of break interrupts. In this first embodiment, there are prepared two types of break interrupts; α and β. The multimode debug interrupt control block B 6 , when accepting the first type break interrupt α, controls so as to execute one of the two debug programs. When accepting the second type break interrupt β, the multimode debug interrupt control block B 6  controls so as to execute one of the two debug programs. The control block B 6  uses the outputted break interrupt factor information S 5  for those controls. And according to this break interrupt factor information S 5 , the control block B 6  specifies a debug mode for selecting the object debug program. 
         [0030]    In  FIG. 3 , the debug object user program is created by the user himself/herself and stored in the user program storage area B 3 . The runtime debug program is used to execute debug processings that require quick responses, such as bypass emulation, etc. The runtime debug program is stored in a runtime debug program storage area B 4 . The normal debug program is a program that is not required to be started within a certain time limitation, for example, like the execution of bypass emulation. The program is usually stored in a normal debug program storage area B 5 . The processor B 0  in this first embodiment selects one of the addresses of the three program storage areas B 3 , B 4 , and B 5  and fetches the instruction from the selected address and executes the instruction. 
       &lt;&lt;Operations&gt;&gt; 
     [Initialization by ICE] 
       [0031]    When debugging a program in the processor B 0  in this first embodiment, the user operates the ICE B 1  before executing the debug target user program to set various necessary items in the processor B 0 . At first, the user activates the debug unit block B 2  with use of an ICE interface input signal S 11 . When the debug unit block is activated in such a way, the debug unit enable signal S 7  is activated. 
         [0032]    Next, the user sets the data denoting the correspondence between the type of the break interrupt and the debug program for the multimode debug interrupt control block B 6 . Then, the user transfers the program used to set the correspondence data from the ICE B 1  to the normal debug program data storage area B 5  through the lines of the ICE interface input signal S 11  and the access bus signal S 10 . After this transfer completes, the debug unit block B 2  sends the execution block control signal S 8  denoting the completion of the transfer and the start of the execution to the execution block B 7 . When the execution block B 7  starts up the program for setting with use of the system bus signal S 6 , the correspondence data is set in the multimode debug interrupt control block B 6 . In this first embodiment, the break interrupt α is related to the runtime debug program while the break interrupt  13  is related to the normal debug program. 
         [0033]    The debug unit block B 2  accepts and sets each break condition according to the ICE interface input signal S 11 . Plural break conditions can be set and either the first type break interrupt α or the second type break interrupt β can be set for each of those break conditions. In this first embodiment, two break conditions x and y are set for the user program. When the break condition x is satisfied, the break interrupt α is executed and when the break condition y is satisfied, the break condition β is executed. 
       [Starting Up the User Program] 
       [0034]    When the user completes the initialization with use of the ICE B 1 , the debug unit block B 2  sends an execution block control signal S 8  to the execution block B 7 . The signal S 8  denotes the start of the user program execution. The execution block B 7  then selects the address of the user program storage area B 3  and starts the execution of the user program. While the execution block B 7  is executing the user program, the debug unit block B 2  keeps monitoring the execution block sate signal S 9  sent from the execution block B 7 . Detecting that the subject break condition is satisfied, the debug unit block B 2  issues a predetermined break interrupt according to the setting. 
       [Operations to be Executed in Response to the Condition of a Detected Runtime Break Interrupt] 
       [0035]    If the debug unit block B 2  detects that the break condition x is satisfied, a break interrupt α is issued. Then, the multimode debug interrupt control block B 6  receives a break interrupt a input signal S 1  from the debug unit block B 2 . Receiving the signal S 1 , the multimode debug interrupt control block B 6  outputs a break interrupt request signal S 3  to the execution block B 7 . At the same time, the control unit B 6  refers to the set correspondence data and outputs the break interrupt factor information S 5  that specifies the debug mode corresponding to the runtime debug program to the execution block B 7 . 
         [0036]    The execution block B 7  thus receives the break interrupt request signal S 3  and the break interrupt factor information S 5  from the multimode debug interrupt control block B 6 . Accepting the break interrupt, the execution block B 7  returns a break interrupt acceptance complete signal S 4  to the control unit B 6 . The control unit B 6 , upon receiving the break interrupt acceptance complete signal S 4 , turns off the break interrupt request signal S 3 . 
         [0037]    Then, the execution block B 7  fetches the instruction from the address of the runtime debug program storage area B 4  according to the break interrupt factor information S 5  and executes the runtime debug program. The execution block B 7  switches from the user program to the runtime debug program quickly; here, none of the ICE B 1  and the debug unit block B 2  are required for the switching. 
       [Operations to be Executed in Response to the Condition of a Detected Normal Break Interrupt] 
       [0038]    If the debug unit block B 2  detects that the break condition y is satisfied, a break interrupt β is issued. At this time, the multimode debug interrupt control block B 6  receives a break interrupt β input signal S 2  from the debug unit block B 2 . Receiving this break interrupt β input signal S 2 , the control unit B 6  outputs a break interrupt request signal S 3  to the execution block B 7 . At the same time, the control unit B 6  refers to the set correspondence data and outputs the break interrupt factor information S 5  that specifies the debug mode corresponding to the normal debug program to the execution block B 7 . 
         [0039]    The execution block B 7 , upon receiving the break interrupt request signal S 3  and the break interrupt factor information S 5 , fetches the instruction from the address of the normal debug program storage area B 5  and makes an attempt for executing the normal debug program. At this time, if the execution block control signal S 8  enables the access to the normal debug program storage area B 5 , the execution block B 7  fetches the instruction from the address of the normal debug program storage area B 5  and executes the normal debug program right away. 
         [0040]    On the other hand, if the execution block control signal S 8  disables the access to the normal debug program storage area B 5 , the execution block B 7  suspends the execution of the program. The user then operates the ICE B 1  to load the normal debug program that includes the function to the normal debug program storage area B 5  and resets the access disabled by the execution block control signal S 8 . The execution block B 7  then fetches the instruction from the address of the normal debug program storage area B 5  and executes the loaded normal debug program. When executing the normal debug program for the second time or later, the normal debug program that is already loaded into the normal debug program storage area B 5  may be used or another normal debug program is overwritten in the normal debug program storage area B 5  so as to use the normal debug program that comes to have different functions. 
         [0041]    As described above, in this first embodiment, the runtime break interrupt or the normal break interrupt is selected and executed automatically in accordance with the execution of the user program. Furthermore, the runtime debug program or the normal debug program is selected and executed automatically in accordance with the execution of the user program. Here, no user operation is required for any of those selections and executions. 
       &lt;&lt;Detailed Configuration of the Multimode Debug Interrupt Control Block&gt;&gt; 
       [0042]      FIG. 4  is a block diagram for describing the detailed configuration of the multimode debug interrupt control unit. As shown in  FIG. 4 , the multimode debug interrupt control block B 6  in the first embodiment includes a break interrupt request generation block b 61 , a break interrupt factor information generation block b 62 , a setting register block b 66 , and a bus interface block b 63 . The setting register block b 66  includes a runtime break selection bit α holding block b 64  corresponding to the break interrupt α and a runtime break selection bit  3  holding block b 65  corresponding to the break interrupt β. 
         [0043]    The runtime break selection bit α and the runtime break selection bit  3  are set at the initialization time respectively. The setting program is started up first, and then corresponding data is written in the setting register unit b 66  according to the system bus signal S 6 , the bus interface unit b 63 , and the internal access bus signal S 17 . In this first embodiment, the runtime debug program is related to the break interrupt α and the normal debug program is related to the break interrupt β. Therefore, “1” is written in the runtime break selection bit a holding block b 64  and “0” is written in the runtime break selection bit β holding block b 65 . In other words, when “1” is set in the runtime break selection bit, the debugging is executed in the runtime debug mode. And when “0” is set in the runtime break selection bit, no debugging is executed in the runtime debug mode. 
       [Operations to be Executed in Response to the Condition of a Detected Runtime Break Interrupt] 
       [0044]    In the multimode debug interrupt control block B 6 , the break interrupt request generation block b 61  receives the break interrupt alpha input signal S 1 . The break interrupt request generation block b 61  then generates a break interrupt request signal S 3  and outputs the signal S 3  to the execution block B 7 . At this time, the block b 61  generates a break interrupt type signal S 14  and outputs the signal S 14  to the break interrupt factor information generation block b 62 . The break interrupt factor information generation block b 62  then generates the break interrupt factor information S 5  according to the break interrupt type signal S 14  and the runtime break selection bit α output signal S 15  that notifies the content of the runtime break selection bit α holding block b 64 . Because “1” is set in the runtime break selection bit α here, the break interrupt factor information S 5  output to the execution block B 7  specifies the runtime debug mode. After this, when receiving the break interrupt acceptance complete signal S 4  from the execution block B 7 , the break interrupt request generation block b 61  turns off the break interrupt request signal S 3 . 
       [Operations to be Executed in Response to the Condition of a Detected Normal Break Interrupt] 
       [0045]    In the multimode debug interrupt control block B 6 , the break interrupt request generation block b 61  receives the break interrupt β input signal S 2 . The break interrupt request generation block b 61  then generates a break interrupt request signal S 3  and outputs the signal S 3  to the execution block B 7 . At this time, the block b 61  also generates a break interrupt type signal S 14  and outputs the signal S 14  to the break interrupt factor information generation block b 62 . The break interrupt factor information generation block b 62  generates the break interrupt factor information S 5  according to the break interrupt type signal S 14  and the runtime break selection bit β output signal S 16  that notifies the content of the runtime break selection bit β holding block b 65  and outputs the information S 5  to the execution block B 7 . Because “0” is set in the runtime break selection bit β at this time, the break interrupt factor information S 5  output to the execution block  87  specifies the normal debug mode. After this, receiving the break interrupt acceptance complete signal S 4  from the execution block B 7 , the break interrupt request generation block b 61  turns off the break interrupt request signal S 3 . 
       &lt;&lt;Detailed Configuration of the Execution Block&gt;&gt; 
       [0046]      FIG. 5  is a block diagram for describing the configuration of the execution block. As shown in  FIG. 5 , the execution block B 7  includes a user program access address generation block b 71 , a runtime debug program access address generation block b 72 , a normal debug program access address generation block b 73 , an address selection block b 74 , a break interrupt acceptance block b 75 , an instruction execution block b 76 , and a bus interface block b 77 . 
         [0047]    The break interrupt acceptance block b 75 , upon receiving a debug unit enable signal S 7  from the debug unit block B 2 , is activated to accept a break interrupt request signal S 3 . If accepting the break interrupt request signal S 3  in this status, the break interrupt acceptance block b 75  refers to the instruction execution block status signal S 29 . If the instruction execution block status signal S 29  denotes that the debug program is being executed (break status), the break interrupt acceptance block b 75  suspends the acceptance of the break interrupt. 
         [0048]    On the other hand, if the instruction execution block status signal S 29  denotes that the user program is being executed (user status), the break interrupt acceptance block b 75  accepts the break interrupt and outputs a break interrupt acceptance signal S 25  to the instruction execution block b 76 . After this, if the instruction execution block b 76  changes the status of the instruction execution block status signal S 29  to denote the break status, the break interrupt acceptance block b 75  outputs a break interrupt acceptance complete signal S 4  to the multimode debug interrupt control block B 6 . 
         [0049]    The instruction execution block b 76  outputs an instruction request signal S 28  and inputs an instruction fetch bus signal S 26  to fetch the object instruction. The instruction request signal S 28  includes the information denoting whether the instruction execution block b 76  is in the user status or in the break status. As a result of the execution of the fetched instruction, if a data access is generated, the instruction execution block b 76  fetches the object data through the data access bus signal S 27  line, the bus interface block b 77 , and the system bus signal S 6  line. 
         [0050]    Upon receiving the execution block control signal S 8 , the instruction execution block b 76  is enabled to receive commands to start and stop instruction executions from the debug unit block B 2 . Furthermore, the instruction execution block b 76  sends an execution block sate signal S 9  to notify the debug unit block B 2  of the progress of the program execution. And the instruction execution block b 76 , upon receiving the break interrupt acceptance signal S 25  from the break interrupt acceptance block b 75 , shifts the status from user status to break status and changes the content of the instruction execution block status signal S 29  from user status information to break status information. 
         [0051]    The user program access address generation block b 71  generates an address to access the user program according to the instruction request signal S 28  and outputs the first address information S 21  denoting the address of the user program storage area B 3 . The runtime debug program access address generation block b 72  generates an address for accessing the runtime debug program according to the instruction request signal S 28  and outputs the second address information S 22  denoting the address of the runtime debug program storage area B 4 . The normal debug program access address generation block b 73  generates an address for accessing the normal debug program according to the instruction request signal S 28  and outputs the third address information S 23  that denotes the address of the normal debug program storage area B 5 . 
         [0052]    The address selection block b 74  selects one of the first address information S 21 , the second address information S 22 , and the third address information S 23  according to the instruction execution block status signal S 29  and the break interrupt factor information S 5 . The address selection block b 74  then outputs the selected address information S 24  to the bus interface block b 77 . If the instruction execution block status signal S 29  denotes the user status, the address selection block b 74  selects the first address information S 21 . If the instruction execution block status signal S 29  denotes the break status and if the break interrupt factor information S 5  denotes the runtime debug mode respectively, the address selection block b 74  selects the second address information S 22 . If the instruction execution block status signal S 29  denotes the break status and if the break interrupt factor information S 5  denotes the normal debug mode respectively, the address selection block b 74  selects the third address information S 23 . 
       &lt;&lt;Operations in the Detailed Configuration&gt;&gt; 
     [Initialization] 
       [0053]    If the instruction execution block b 76  fetches and executes an instruction for writing to the runtime break selection bit α holding block b 64  or an instruction for writing to the runtime break selection bit β holding block b 65  in the multimode debug interrupt control block B 6 , the write access is enabled through the data access bus signal S 27  line, the bus interface block b 77 , and the system bus signal S 6  line. The write data to appear in the line of the system bus signal S 6  is fetched into the bus interface block b 63  in the multimode debug interrupt control block B 6 . Then, the writing to the setting register unit b 66  is done through the line of the internal bus signal S 17 . 
       [Operations in the User Status] 
       [0054]    While the user status is set, the execution block B 7  is active and the multimode debug interrupt control block B 6  is inactive. In this case, the following operations will be executed in order: 
         [0055]    1. The instruction execution block b 76  adds the user status information to the instruction request signal S 28  and outputs the signal S 28 . Here, the instruction execution block b 76  also outputs an instruction execution block status signal S 29  that denotes the user status. 
         [0056]    2. The user program access address generation block b 71  outputs the first address information S 21  according to the instruction request signal S 28 . The runtime debug program access address generation block b 72  and the normal debug program access address generation block b 73  are both inactive, since the user status denoting information is added to the instruction request signal S 28 . 
         [0057]    3. The address selection block b 74  selects the first address information S 21  from among the first address information S 21 , the second address information S 22 , and the third address information S 23  according to the received instruction execution block status signal S 29  and outputs the selected address information S 24 . 
         [0058]    4. The bus interface block b 77  generates an instruction fetch request access according to the selected address information S 24  and outputs the access signal to the line of the system bus signal S 6 . In addition, receiving an instruction of the user program through the line of the system bus signal S 6 , the bus interface block b 77  outputs the instruction to the line of the instruction fetch bus signal S 26 . 
         [0059]    5. The instruction execution block b 76  executes the instruction fetched through the line of the instruction fetch bus signal S 26 . Then, the instruction execution block b 76  outputs the progress status of the instruction execution to the line of the execution block status signal S 9 . 
       [Operations to be Executed in Response a Runtime Break Interrupt Generated in the User Status] 
       [0060]    While the execution block B 7  is executing the user program, if the multimode debug interrupt control block B 6  receives a break interrupt a input signal S 1  from the debug unit block B 2 , the following operations are to be executed: 
         [0061]    1. The break interrupt request generation block b 61  outputs a break interrupt request signal S 3  to the execution block B 7 . The break interrupt request generation block b 61  also outputs a break interrupt type signal S 14  to the break interrupt factor information generation block b 62 . The signal S 14  denotes that the interrupt input signal is a break interrupt a input signal S 1 . 
         [0062]    2. The break interrupt factor information generation block b 62  outputs the break interrupt factor information S 5  that specifies the runtime debug mode to the address selection block b 74  according to the break interrupt type signal S 14  and the runtime break selection bit alpha output signal S 15 . Because “1” is set for the runtime break selection bit α at this time, the runtime break selection bit α output signal S 15  specifies the runtime debug mode. 
         [0063]    3. The break interrupt acceptance block b 75 , upon accepting the break interrupt request signal S 3 , outputs a break interrupt acceptance signal S 25  to the instruction execution block b 76 . 
         [0064]    4. The instruction execution block b 76 , upon receiving the break interrupt acceptance signal S 25 , changes the internal status from user status to break status. Then, the instruction execution block b 76  outputs an instruction execution block status signal S 29  to the break interrupt acceptance block b 75  and the address selection block b 74  respectively. Furthermore, the instruction execution block b 76  also outputs an instruction request signal S 28  having added status information of “now in the break status” to those blocks. 
         [0065]    5. The break interrupt acceptance block b 75 , when confirming that the status of the instruction execution block status signal S 29  has been changed from user status to break status, initializes the internal status and outputs a break interrupt acceptance complete signal S 4  to the break interrupt request generation block b 61 . 
         [0066]    6. The runtime debug program access address generation block b 72  and the normal debug program access address generation block b 73 , upon receiving an instruction request signal S 28  having added status information of “now in the break status”, generate the second address information S 22  and the third address information S 23  and output them to the address selection block b 74  respectively. The user program access address generation block b 71  makes no operation at this time, since the instruction request signal S 28  denotes “now in the break status”. 
         [0067]    7. The address selection block b 74  selects the second address information S 22  from among the first, second, and third address information items S 21  to S 23  according to the instruction execution block status signal S 29  denoting the break status and the break interrupt factor information S 5  that specifies the runtime debug mode. Then, the address selection block b 74  outputs the second address information S 22  to the bus interface block b 77  as the selected address information S 24 . 
         [0068]    8. The bus interface block b 77  generates an instruction fetch request access signal with use of the selected address information S 24  and outputs the access signal to the destination as a system bus signal S 6 . After this, the subject instruction is read from the runtime debug program storage area B 4  and output to the line of the system bus signal S 6 . The bus interface block b 77  reads this instruction. 
         [0069]    9. The read instruction is passed to the instruction execution block b 76  through the line of the instruction fetch bus signal S 26 . Thus the runtime debug program instruction is executed. 
       [Operations to be Executed in Response to a Normal Break Interrupt Issued in the User Status] 
       [0070]    While the execution block B 7  is executing the user program, if multimode debug interrupt control block B 6  receives a break interrupt β input signal S 2  from the debug unit block B 2 , the interrupt will be processed as follows: 
         [0071]    1. The break interrupt request generation block b 61  outputs a break interrupt request signal S 3  to the execution block B 7 . Furthermore, the break interrupt request generation block b 61  outputs a break interrupt type signal S 14  to the break interrupt factor information generation block b 62 . The signal S 14  denotes that the interrupt input signal is a break interrupt beta input signal S 2 . 
         [0072]    2. The break interrupt factor information generation block b 62  outputs the break interrupt factor information S 5  that specifies the normal debug mode to the address selection block b 74  according to the break interrupt type signal S 14  and the runtime break selection bit output signal S 16 . Because “0” is set for the runtime break selection bit β at this time, the runtime break selection bit β output signal S 16  specifies the normal debug mode. 
         [0073]    3. The break interrupt acceptance block b 75 , upon accepting the break interrupt request signal S 3 , outputs a break interrupt acceptance signal S 25  to the instruction execution block b 76 . 
         [0074]    4-1. The instruction execution block b 76 , upon receiving the signal S 25 , changes the internal status from user status to break status. The instruction execution block b 76  then outputs the instruction execution block status signal S 29  to the break interrupt acceptance block b 75  and the address selection block b 74  respectively. Furthermore, the instruction execution block b 76  outputs the instruction request signal S 28  having added status information of “now in the break status” to those blocks b 75  and b 74 . 
         [0075]    4-2. When the status of the instruction execution block b 76  is changed to the break status, if the execution block control signal S 8  disables the access to the normal debug program storage area B 5 , the instruction execution block b 76  waits for the instruction request signal S 28  having added status information of “now in the break statue” for a certain time, then outputs the signal S 28 . Meanwhile, the user operates the ICE B 1  to load the normal debug program having a desired function into the normal debug program storage area B 5  and resets the access having been disabled by the execution block control signal S 8 . 
         [0076]    5. The break interrupt acceptance block b 75 , upon confirming that the status of the instruction execution block status signal S 29  is changed from user status to break status, initializes the internal status and outputs a break interrupt acceptance complete signal S 4  to the break interrupt request generation block b 61 . 
         [0077]    6. The runtime debug program access address generation block b 72  and the normal debug program access address generation block b 73 , upon receiving an instruction request signal S 28  having added status information of “now in the break status”, generate the second address information S 22  and the third address information S 23  and output those information items to the address selection block b 74  respectively. The user program access address generation block b 71  makes no operation at this time, since the instruction request signal S 28  denotes “now in the break status”. 
         [0078]    7. The address selection block b 74  selects the third address information S 23  from among the first, second, and third address information items S 21  to S 23  according to the instruction execution block status signal S 29  denoting the break status and the break interrupt factor information S 5  that specifies the normal break mode. Then, the address selection block b 74  outputs the third address information S 22  to the bus interface block b 77  as the selected address information S 24 . 
         [0079]    8. The bus interface block b 77  generates an instruction fetch request access signal with use of the selected address information S 24  and outputs the access signal to the destination as a system bus signal S 6 . After this, the signal S 6  is read from the normal debug program storage area B 5  and output to the line of the system bus signal S 6 . The bus interface block b 77  reads this instruction. 
         [0080]    9. The read instruction is passed to the instruction execution block b 76  according to the instruction fetch bus signal S 26 . Thus the normal debug program instruction is executed. 
       Effects of the First Embodiment 
       [0081]    As described above, in this first embodiment, whether a break interrupt is issued when a predetermined debug condition is satisfied is determined automatically and quickly so as to be used as a quickly responsible runtime break interrupt or as a normal break that does not require a quick response but can realize an enhanced debug function. This can thus quicken start of the execution of the debug program. Furthermore, because the address of the debug program storage area can be selected as described above, branching to the object debug program can be made instantaneously. 
       Second Embodiment 
       [0082]      FIG. 6  is a block diagram for describing a configuration of a multiprocessor in this second embodiment. As shown in  FIG. 6 , the multiprocessor in this second embodiment includes two processors B 100 - 1  and B 100 - 2  that are the same in configuration as that of the processor B 0  in the first embodiment. In  FIG. 6 , the debug unit block B 2 - 1  of the processor B 100 - 1  and the debug unit block B 2 - 2  of the processor B 100 - 2  are the same in function and in configuration as that of the debug unit block B 2  of the processor B 0  in the first embodiment. The execution block B 7 - 1  of the processor B 100 - 1  and the execution block B 7 - 2  of the processor B 100 - 2  are the same in function and in configuration as that of the execution block B 7  of the processor B 0  in the first embodiment. 
         [0083]    The ICE B 1  shown in  FIG. 6  is the same as the ICE B 1  shown in  FIG. 3  and the ICE interface input signal S 11  and the ICE interface output signal S 12  can be used to set the two debug unit blocks B 2 - 1  and B 2 - 2 . When setting the debug unit block B 2 - 1 , the inter-unit bock signal S 102  is passed through the debug unit block B 2 - 2  and changed to an ICE interface output signal S 12 . When setting the debug unit block B 2 - 2 , the ICE interface input signal S 11  is passed through the debug unit block B 2 - 1  and changed to an inter-unit block signal S 102  to be inputted to the debug unit block B 2 - 2 . 
         [0084]    The break interrupt a input signals S 1 - 1  and S 1 - 2 , the break interrupt β input signals S 2 - 1  and S 2 - 2 , the break interrupt request signals S 3 - 1  and S 3 - 2 , the break interrupt acceptance complete signals S 4 - 1  and S 4 - 2 , the break interrupt factor information items S 5 - 1  and S 5 - 2 , the system bus signals S 6 - 1  and S 6 - 2 , the debug unit enable signals S 7 - 1  and S 7 - 2 , the execution block control signals S 8 - 1  and S 8 - 2 , the execution block status signals S 9 - 1  and S 9 - 2 , and the access bus signals S 10 - 1  and S 10 - 2  are also the same in function as the break interrupt a input signal S 1 , the break interrupt  3  input signal S 2 , the break interrupt request signal S 3 , the break interrupt acceptance complete signal S 4 , the break interrupt factor information item S 5 , the system bus signal S 6 , the debug unit enable signal S 7 , and the execution block control signal S 8 , the execution block status signal S 9 , and the access bus signal S 10  in the first embodiment respectively. 
         [0085]    The user program storage areas B 3 - 1  and B 3 - 2 , the runtime debug program storage areas B 4 - 1  and B 4 - 2 , and the normal debug program storage areas B 5 - 1  and B 5 - 2  are also the same in function as the user program storage area B 3 , the runtime debug program storage area B 4 , and the normal debug program storage area B 5  in the first embodiment, respectively. 
         [0086]    Each of the multimode debug interrupt control block (B 106 - 1 ) and multimode debug interrupt control block (B 106 - 2 ) in this second embodiment is provided with some functions in addition to those of the multimode debug interrupt control block (B 106 ) in the first embodiment so as to correspond to a multiprocessor.  FIG. 7  is a block diagram for describing the configuration of the multimode debug interrupt control block (B 106 ) corresponding to a multiprocessor in this second embodiment. The multimode debug interrupt control blocks (B 106 - 1 ) and (B 106 - 2 ) corresponding to a multiprocessor respectively shown in  FIG. 6  are the same in configuration and in function as the multimode debug interrupt control block (B 106 ) shown in  FIG. 7 . 
         [0087]    In  FIG. 7 , the break interrupt factor information generation block b 62 , the bus interface block b 63 , the runtime break selection bit α holding block b 64  corresponding to the break interrupt α and the runtime break selection bit β holding block b 65  corresponding to the break interrupt β are the same in function as those shown in  FIG. 4 . 
         [0088]    The setting register block b 66 ′ of the multimode debug interrupt control block (B 106 ) corresponding to a multiprocessor includes a simultaneous break acceptance enable bit holding block b 67  added newly thereto. The bit holding block b 67  holds the simultaneous break acceptance enable bit written at the initialization time. This simultaneous break acceptance enable bit comes to have “1” in response to the acceptance of a simultaneous break interrupt and have “0” in response to the rejection of the interrupt. 
         [0089]    The masking block b 69  executes an AND operation of a simultaneous break interrupt input signal S 101 -( k ) received from the processor in the preceding stage and a simultaneous break acceptance enable bit, then outputs a break interrupt input signal S 18  when the AND condition is satisfied. When receiving a simultaneous break interrupt signal S 101 -( k ) while the simultaneous break acceptance enable bit is “1”, the masking block b 69  enables the simultaneous break interrupt and outputs a break interrupt input signal S 18 . If receiving a simultaneous break interrupt signal S 101 -( k ) while the simultaneous break acceptance enable bit is “0”, the masking block b 69  disables the simultaneous break interrupt and does not output the break interrupt signal S 18 . 
         [0090]    In  FIG. 7 , the break interrupt request generation block b 61 ′ has the function for accepting the break interrupt input signal S 18  from the masking block b 69  in addition to the function of the break interrupt request generation block b 61 . The break interrupt request generation block b 61 ′, upon accepting a break interrupt input signal S 18  from the masking block b 69 , outputs a break interrupt request signal S 3  and a break interrupt type signal S 14  that denotes the same debug mode as that specified by the simultaneous break interrupt input signal S 101 -( k ). The break factor storage bit holding block b 68  outputs a simultaneous break interrupt input signal S 101 -( k+ 1) to the processor in the next stage after confirming that the multimode debug interrupt control block (B 106 ) accepts a break interrupt and the execution block goes into the break status. This simultaneous break interrupt input signal  5101 -( k+ 1) is generated according to the break interrupt factor information S 5  and includes the information that specifies a debug mode. 
       &lt;&lt;Multiprocessor Operations&gt;&gt; 
       [0091]    [Operations Executed when a Simultaneous Break Interrupt is Set and a Break Interrupt is Generated in the Processor B 100 - 1 ] 
         [0092]    1-1. It is premised here that the multimode debug interrupt control block (B 106 - 1 ) in the processor  100 - 1  receives a break interrupt β input signal S 2 . 
         [0093]    1-2. The break interrupt request generation block b 61 ′ outputs a break interrupt request signal S 3 . Furthermore, the break interrupt request generation block b 61 ′ outputs a break interrupt type signal S 14  to the break interrupt factor information generation block b 62 . The signal S 14  denotes that the break interrupt is generated by a break interrupt β input signal S 2 . 
         [0094]    1-3. The break interrupt factor information generation block b 62  outputs the break interrupt factor information S 5  that specifies the normal debug mode according to the break interrupt type signal S 14  and the runtime break selection bit β output signal S 16 . It is also premised here that “0” is set in the runtime break selection bit β just like in the first embodiment. 
         [0095]    1-4. After this, if the execution block goes into the break status, the break interrupt request generation block b 61 ′ receives a break interrupt acceptance complete signal S 4 . 
         [0096]    1-5. The break factor storage bit holding block b 68  generates information that specifies the normal debug mode according to the break interrupt factor information S 5  and outputs a simultaneous break interrupt input signal S 101 - 2  to the processor B 100 - 2  synchronously with the break interrupt acceptance complete signal S 4 . 
         [0097]    2-1. Then, the masking block b 69  in the processor B 100 - 2  receives a simultaneous break interrupt input signal S 101 - 2 . The masking block b 69  thus executes an AND operation of the simultaneous break interrupt input signal S 101 - 2  output from the processor B 100 - 1  and the simultaneous break acceptance enable bit. If “0” is set in the simultaneous break acceptance enable bit, the masking block b 69  masks the simultaneous break interrupt signal S 101 - 2  and does not output the break interrupt input signal S 18 . On the other hand, if “1” is set for the simultaneous break acceptance enable bit, the masking block b 69  enables the simultaneous break interrupt and outputs a break interrupt input signal S 18 . 
         [0098]    2-2. Upon receiving the break interrupt input signal S 18  from the masking block b 69 , the break interrupt request generation block b 61 ′ outputs a break interrupt request signal S 3 . Furthermore, the break interrupt request generation block b 61 ′ outputs a break interrupt type signal S 14  to the break interrupt factor information generation block b 62 . The signal S 14  denotes the same normal debug mode as that generated at the side of the processor B 100 - 1 . 
         [0099]    2-3. The break interrupt factor information generation block b 62  outputs the break interrupt factor information S 5  that specifies the normal debug mode according to the break interrupt type signal S 14  and the runtime break selection bit β output signal S 16 . It is premised here that “0” is set in the runtime break selection bit β just like in the processor B 100 - 1 . 
         [0100]    2-4. After this, when the execution block goes into the break status, the break interrupt request generation block b 61 ′ receives a break interrupt acceptance complete signal S 4 . 
         [0101]    2-5. The break factor storage bit holding block b 68  generates information that specifies the normal debug mode according to the break interrupt factor information S 5 , then outputs a simultaneous break interrupt input signal S 101 - 1  to the processor B 100 - 1  synchronously with the break interrupt acceptance complete signal S 4 . 
         [0102]    3. Then, each of the processors B 100 - 1  and B 100 - 2  goes into the normal debug mode to process the simultaneous break interrupt. 
       Effects of the Second Embodiment 
       [0103]    In this second embodiment, the normal debug mode can be divided into some sub-modes so as to realize a simultaneous break debug mode that is indispensable in multiprocessor type computers.