Abstract:
In a bus driver circuit having a floating gate circuit for controlling voltage on the gate of the output driver and a floating well circuit for controlling voltage on the body of the output driver, the improvement comprising a well pull up circuit coupled to the output driver for applying supply voltage to the body during transmission and for applying the output of the floating gate circuit to the body during quiescence.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates generally to an apparatus and method for operating an integrated circuit. In particular, it relates to a MOS output driver that is powered by a 3.3v power supply and may be occasionally connected to a higher supply, such as 5v. 
     Complementary metal oxide semiconductors (CMOS) are ubiquitous in integrated circuits and systems. CMOS technology continues to shrink and as it shrinks the power supplies that operate the CMOS devices shrink accordingly. At present, many CMOS devices operate with a 3.3v power supply. However, these devices are often connected to peripheral devices in a system or even on the same chip that may operate or otherwise carry a higher voltage, such as 5v. If an output driver on a circuit is connected to a power supply that is greater than the output driver&#39;s normal power supply, the greater power supply may inadvertently turn on the driver when the system requires that the driver be off or otherwise in a quiescent state. 
     As explained later, others have provided solutions to this problem by controlling the voltage on the gate of the driving transistor, as well as controlling the voltage on the well of the driving transistor. If either of those voltages are not properly controlled, then one or more of the two body diodes in the drive transistor may turn on or the mosfet may itself turn on. See, in particular, U.S. Pat. No. 5,160,855 which shows a well voltage control circuit for controlling the voltage on the well of the drive transistor. The well voltage control circuit includes at least four transistors. However, I have found that the well control circuit does not adequately control the output transistor body when the output voltage is close to the value of the supply voltage during transmission. 
     SUMMARY OF THE INVENTION 
     The invention provides a bus driver that is less complex than the prior art and solves the problem of a floating well voltage where output voltage is close to the value of the supply voltage during mission. The invention provides a first output driver MOS transistor that has a source, an insulated gate, a body and a drain. This structure includes two inherent diodes. The drain and the body form one diode and the body and the source form the other. A low voltage supply terminal is connected to the source of the MOS transistor and the drain provides the output terminal. The gate terminal receives a gate voltage signal that turns the bus driver MOS transistor on or off. A floating gate control circuit is coupled to the gate and allows the gate to rise with the output voltage on the drain when the output voltage on the drain exceeds the primary supply voltage. This ensures that the normal mosfet conduction does not occur. A well pull up circuit is connected to the floating gate control circuit, the body of the MOS transistor and to the primary supply terminal. The well pull up circuit lets the well float and thereby prevents its inadvertent operation of tuning on one of the body diodes of the MOS transistor. An enable control circuit controls the well pull up circuit. The enable control circuit is high during operation of the bus output driver and low when the bus is quiescent. 
    
    
     DRAWINGS 
     FIG. 1 a  is a schematic of a single bus driver transistor. 
     FIG. 1 b  is a schematic corresponding to  1   a  and shows the two inherent body diodes. 
     FIG. 2 is a schematic of a prior art bus driver circuit. 
     FIG. 3 is a further schematic of the floating gate circuit of FIG.  2 . 
     FIG. 4 is a schematic diagram of the invention having a well pull up circuit. 
     FIG. 5 is a more detailed schematic of the well pull up circuit. 
     FIG. 6 is a schematic of a CMOS output driver that applies the invention to the NMOS and PMOS transistors. 
    
    
     DETAILED DESCRIPTION 
     FIGS. 1 a ,  1   b ,  2  and  3  show the problem faced by bus drivers and how the problem is addressed by the circuit disclosed in U.S. Pat. No. 5,160,855. FIG. 1 a is a simplified version of a bus driver. The driving transistor Q BUS  receives an input signal V IN . Q BUS  is connected between a power supply V DD  and an output terminal V OUT . The transistor Q BUS  is shown as a PMOS transistor. A PMOS transistor includes P-type diffusions in the surface of a substrate that substantially comprises N-type doping. As a result, the transistor Q BUS  has or can be viewed as a structure with two internal diodes such as shown in FIG. 1 b . Since the source is coupled to the body, one diode is, in effect, shorted to the drain. The other diode is controlled by V OUT . It is important that these diodes that are formed by the respective P-type diffusions and the body of the Q BUS  be kept from triggering on. If V OUT  exceeds V DD , the body diode D 2  will be turned on. This is undesirable since, in effect, Q BUS  could be turned on at a time when V IN  was high. In the ideal bus driver, Q BUS  never turns on until V IN  is low. Those skilled in the art will appreciate that, in a CMOS device, the output circuit of FIG. 1 a  will have a corresponding NMOS output transistor. 
     The circuits shown in U.S. Pat. 5,160,855 and FIG. 2 include a floating gate voltage circuit (VFG) and a floating well voltage circuit (VFW). The VFG circuit is connected between the input V IN  and the gate of the output transistorQ BUS . The VFW circuit is connected between the output V OUT  and the body tie of Q BUS . During quiesence the input to VFG is tied to the supply voltage V DD . As long as V OUT  is less than V DD  the gate voltage is tied to V DD . The VFG monitors the output voltage and adjusts the gate voltage to follow the output voltage V OUT  when V OUT  is greater than V DD . During transmission, the input of the floating gate circuit may vary between ground and the supply voltage to turn the drive transistor on and off, respectively. In this way, the gate and the drain of the transistor Q BUS  are maintained at the same potential when V OUT  rises above V DD . Accordingly, the transistor Q BUS  is prevented from turning on. Of course, the problem of a floating output voltage V OUT  also affects the well of the output transistor Q BUS . In the prior art solution as shown in FIG. 3, the VFW circuit attempts to adjust the voltages applied to the well of Q OUT  in order to prevent unwanted operation. The prior art circuit functions acceptably for conditions when V OUT  is significantly less than V DD  and when V OUT  is significantly greater than V DD . However, it experiences problems when V OUT is approximately the same value as V DD . 
     When V OUT  is less than V DD , transistor Q 4  is on and VFW is effectively connected to V DD . Accordingly, the diode in the body tie is reverse biased and does not conduct current. That is the condition for normal transmission. When the bus is off and there is no transmission, V OUT  may rise to a voltage greater than V DD . For example, V DD  for a bus is normally 3.3v but elements and devices driven by the bus may be at 5v. Accordingly, V OUT  may be much greater than V DD . In that case, Q 4  is off and Q 1  and Q 2  are on and VFW follows V OUT . The same voltage of V OUT  is applied across the body tie diode D 2 . Since the same voltage is across both terminals of the body tie diode, the diode remains off. 
     However, the circuit shown in FIG. 3 does not control VFW when V OUT  is close to V DD . When V OUT  is nearly the same as V DD , all of the transistors Q 1 -Q 4  are off. At that time, there is no control on VFW. Consequently the body becomes a high impedance node and is susceptible to charge injection through the drain to body capacitance during transmission. The injected charge changes the voltage on the body which then changes the threshold voltage on Q BUS  Modulating the threshold voltage in such a way causes signal distortion. 
     Turning to FIGS. 4 and 5, the invention remedies this deficiency of prior art by adding a well pull up (WPU) circuit to the circuit of FIG.  3  and removing the VFW circuit. The WPU circuit (WPU) is connected to the body of Q BUS , the output of the VFG circuit, and to V DD . It receives an input enable signal that is derived from one or more of the enable signals that turn on the bus. In operation, the well pull up circuit ensures that the body of the output transistor Q BUS  is tied to V DD  when the bus is enabled. At all other times, the well pull up circuit allows the body of Q BUS  to float electrically so that the drain diode of Q BUS  can not conduct current. 
     With reference to FIG. 5, when the enable signal is high, Q 5  is on which turns on Q 6 . Accordingly, V DD  is connected to VFW through Q 6  and V DD  is applied to the body of Q BUS . During transmission the supply voltage V DD  is connected to one end of diode D 2  and, since V OUT  is less than V DD  during transmission the diode is reverse biased and does not conduct. When enable is low and the bus is quiescent, Q 5  and Q 6  are off while Q 7  is turned on. Q 7  connects the VFG node to the gate of Q 6 . This is necessary to keep Q 6  off when V OUT  is backwards driven above V DD . Thus, when the circuit is not enabled, the body of Q BUS  is allowed to float and can not carry current. 
     In summary, during operation, when ENABLE is high, Q 5  and Q 6  are on and so VFW is coupled to V DD . This prevents the body diode from floating during transmission and precludes signal distortion due to charge injection into the body. ENABLE is high when the output stage is driving a load. In order to disable the output stage and create a high impedance state, V IN  is set high, i.e., to V DD  and ENABLE is set low, i.e., to zero volts. This turns off Q 5  and turns on Q 7 . The voltage VFG is used to turn off Q 6 . VFG, by design, will be greater than or equal to V IN . With Q 6  off, the body of the output PMOS Q BUS  device is allowed to float so that it cannot conduct current. 
     With reference to FIG. 6, a CMOS output driver is shown. The embodiment includes two output transistors, Q PBUS  and Q NBUS . The transistors are connected in series with Q PBUS  connected to V DD  and Q NBUS  connected to ground. The output voltage V OUT  is taken from the series connection of the transistors Q PBUS  and Q NBUS . The voltage on the gate of Q PBUS  is monitored and controlled by a floating gate circuit, VFG/P. A corresponding floating gate circuit, VFG/N controls the voltage on the gate of Q NBUS . The voltage on the well of Q PBUS  is controlled by the well pull up circuit WPU/P. In a similar manner, the voltage on the well of Q NBUS  is controlled by another well pull up circuit, WPU/N. An enable control circuit  60  is coupled to WPU/P and to WPU/N. The enable control circuit  60  applies the enable signal to WPU/P and applies the signal enable bar to WPU/N. The operation of WPU/P and WPU/N of FIG. 6 substantially corresponds to the operation of the WPU circuit shown in FIGS. 4 and 5. Those skilled in the art understand that the NMOS transistor may be connected to ground or to a negative power supply. Function and operation of CMOS output drivers is otherwise generally well-known those skilled in the art.