Abstract:
A memory system includes a memory module including a plurality of memories and a memory controller suitable for controlling an operation timing of each of the memories, wherein the memories enter a refresh operation mode simultaneously in response to a refresh operation command of the memory controller and individually perform a refresh operation according to the operation timing.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application claims priority of Korean Patent Application No. 10-2014-0019556, filed on Feb. 20, 2014, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Field 
         [0003]    Exemplary embodiments of the present invention relate to a semiconductor memory device, and more particularly, to a memory system including a semiconductor memory device and a refresh operation method thereof. 
         [0004]    2. Description of the Related Art 
         [0005]    A semiconductor device including a semiconductor memory device such as a Dynamic Random Access Memory (DRAM), is widely used in diverse electronic systems. Especially the semiconductor memory device is for storing data used in the electronic systems. Taking DRAM as an example, each unit cell of a semiconductor memory device is formed of one transistor and one capacitor, and data is stored by way of a charge accumulated in the capacitor. However, a problem arises as the charge leaks over time because it is difficult to cut off the capacitor from the peripheral region over the semiconductor substrate. As a result, the data stored in the unit cell may be damaged or lost. To sustain the charge stored in the capacitor, the semiconductor memory device performs what is known as a refresh operation. 
         [0006]    A semiconductor memory device performs a refresh operation by sequentially varying its internal address based on an external command. When a refresh operation mode begins based on an external command, word lines of a memory cell are sequentially selected as a row address is sequentially increased at a predetermined cycle. The charges stored in a capacitor corresponding to the selected word line are amplified by a sense amplifier and then stored back into the capacitor. Through a series of refresh operations, the stored data is retained without being damaged. While in refresh operation mode, more word lines are simultaneously enabled, and more charges stored in the corresponding capacitors are sense-amplified compared to a general operation mode. This means that peak current is raised while in refresh operation mode resulting in power noise. 
         [0007]    A semiconductor memory device is packaged in conformity to the system where the semiconductor memory device is mounted in an environment where the capacity and operation rates required by systems are always increasing. For example, several semiconductor memory devices mounted on a personal computer (PC) are packaged in the form of a module that is integrated on a Printed Circuit Board (PCB), and the module is inserted into a slot of the PC. A typical form of module among the modules packaged in conformity to a system is a Dual In-line Memory Module (DIMM). A plurality of memory devices mounted on the DIMM may be grouped and operated on the basis of rank. 
         [0008]      FIG. 1  is a timing diagram describing a refresh operation of a typical DIMM. 
         [0009]    Referring to  FIG. 1 , the typical DIMM includes eight memory devices DRAM 0  to DRAM 7  in one rank RANK 0 , and the timing diagrams of the refresh operations of the memory devices DRAM 0  to DRAM 7  are shown in the drawing. 
         [0010]    As described above, since the memory devices mounted on the memory module are grouped and operated together, the refresh operations are performed simultaneously as shown in  FIG. 1 . As the simultaneous refresh operations raise the peak current, noise may be produced in the power source voltage VDD or the ground voltage VSS (see  FIG. 1 ). 
       SUMMARY 
       [0011]    The present invention is directed at a refresh operation method of a memory module, which can be represented in multiple embodiments in various semiconductor memory devices and memory systems. 
         [0012]    In accordance with an embodiment of the present invention, a memory system includes a memory module including a plurality of memories, and a memory controller suitable for controlling an operation timing of each of the memories, wherein the memories enter a refresh operation mode simultaneously in response to a refresh operation command of the memory controller and individually perform a refresh operation according to the operation timing. 
         [0013]    In accordance with another embodiment of the present invention, a method for performing a refresh operation in a memory system including a plurality of memories includes setting an operation timing of each of the memories, inputting a refresh operation command to the memories to enter a refresh operation mode simultaneously, and individually performing the refresh operation in each of the memories at a set operation timing in the refresh operation mode. 
         [0014]    In accordance with yet another embodiment of the present invention, a semiconductor memory device includes a Mode Register Set (MRS) unit suitable for outputting a delay control signal corresponding to an input data in response to a mode register set control signal, and a delay control unit suitable for controlling a delay amount of an input path of a refresh operation control signal in response to the delay control signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  is a timing diagram illustrating a refresh operation of a typical Dual In-line Memory Module (DIMM). 
           [0016]      FIG. 2  is a block view illustrating a memory system in accordance with an embodiment of the present invention. 
           [0017]      FIG. 3  is a block view illustrating a semiconductor memory device in accordance with an embodiment of the present invention. 
           [0018]      FIG. 4  is a flowchart describing an operation of the memory system shown in  FIG. 2 . 
           [0019]      FIG. 5  is a timing diagram illustrating the timings of the refresh operations of memories shown in  FIG. 2 . 
       
    
    
     DETAILED DESCRIPTION 
       [0020]    Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts in the various figures and embodiments of the present invention. 
         [0021]      FIG. 2  is a block view illustrating a memory system in accordance with an embodiment of the present invention. 
         [0022]    Referring to  FIG. 2 , the memory system  200 , in accordance with an embodiment of the present invention, may include a memory controller  210  and a memory module  220 . The memory module  220  may include a plurality of memories M. 
         [0023]    The memories M are divided into a plurality of groups R and operate on the basis of a group R in response to a command CMD and an address ADDR that are transmitted from the memory controller  210 . The memories M of a group perform a corresponding operation at predetermined timings respectively. The timings may be set differently under the control of the memory controller  210 . A method for setting an operation timing of each memory will be described in detail below. 
         [0024]    Taking a brief look at the method, memories M 0  to M 7  of a first group R 0  enter a refresh operation mode together. The memories M 0  to M 7  perform a refresh operation according to a timing that is pre-set internally. The memory controller  210  may set the operation timing of each of the memories M 0  to M 7  differently. 
         [0025]    The process of setting the operation timing and performing the refresh operation in each memory will be described in detail. 
         [0026]      FIG. 3  is a block view illustrating a semiconductor memory device in accordance with an embodiment of the present invention. 
         [0027]    The semiconductor memory device  300 , in accordance with an embodiment of the present invention, may form the memory M of  FIG. 2 . Referring to  FIG. 3 , the semiconductor memory device  300  may include a decoding unit  310 , a Mode Register Set (MRS) unit  320 , and a delay control unit  330 . 
         [0028]    The decoding unit  310  decodes a command inputted from an external device, e.g., the memory controller  210  of  FIG. 2 , and generates a corresponding control signal. When the logic level combination of an external command corresponds to a mode register set operation, the decoding unit  310  generates a mode register set control signal MRS. When the combination of an external command corresponds to a refresh operation, the decoding unit  310  generates a refresh operation control signal REF. 
         [0029]    The mode register set unit  320  outputs a delay control signal DLY[0:N] of bits corresponding to an input data DQ in response to the mode register set control signal MRS that is outputted from the decoding unit  310 . For example, the data DQ may include an address ADDR or a data DATA inputted from the memory controller  210 , which is shown in  FIG. 2 . In short, the bit value of the delay control signal DLY[0:N] outputted from the mode register set unit  320  may be set by the memory controller  210 . 
         [0030]    The delay control unit  330  may decide an internal delay amount in response to the delay control signal DLY[0:N], delay the refresh operation control signal REF generated in the decoding unit  310  by the decided delay amount, and output a delayed refresh operation control signal REFD. The internal delay amount of the delay control′ unit  330  may be decided based on the bit value of the delay control signal DLY[0:N]. The delay control unit  330  may include a synchronous or asynchronous delay circuit. Since a delay circuit that delays a signal by a delay amount decided in response to a bit signal is a known technology, a detailed description on the delay circuit is not provided. 
         [0031]    In short, the semiconductor memory device, in accordance with an embodiment of the present invention, may set the delay of a refresh operation command input path by using the control signals during a mode register set operation. In this way, the timing for a refresh operation of the semiconductor memory device may be decided. 
         [0032]    The semiconductor memory device  300 , in accordance with an embodiment of the present invention, may further include a refresh operation control unit  340 . The refresh operation control unit  340  may control the refresh operation of the semiconductor memory device  300  in response to the delayed refresh operation control signal REFD, which is outputted from the delay control unit  330 . 
         [0033]    The operations of the memory system  200  and the semiconductor memory device  300  having the above-described structures are described with reference to  FIG. 4 . 
         [0034]      FIG. 4  is a flowchart describing an operation of the memory system  200 . 
         [0035]    First, in step S 410 , operation timing for each of the memories M 0  to M 7  is set based on a control signal inputted from the memory controller  210 . This may be performed through a mode register set operation. The memory controller  210  may generate control signals for a mode register set operation, input the generated control signals into the memories M 0  to M 7 , and set the operation timing for each of the memories M 0  to M 7  differently. 
         [0036]    Subsequently, in step S 420 , all the memories M 0  to M 7  enter a refresh operation mode in response to a refresh operation command of the memory controller  210 . 
         [0037]    After entering the refresh operation mode, in step S 430 , each of the memories M 0  to M 7  performs a refresh operation according to the timing that is set in the step S 410 . 
         [0038]      FIG. 5  is a timing diagram illustrating the timing of the refresh operations of the memories M 0  to M 7  that operate as described above. 
         [0039]    Referring to  FIG. 5 , the memories M 0  to M 7  enter the refresh operation mode in response to the refresh operation command generated in the memory controller  210 . To be more accurate, the memories M 0  to M 7  perform the refresh operations, respectively, in synchronization with the delayed refresh operation control signals REFD (see  FIG. 3 ) that are obtained internally. The delay amount, which is the timing for the refresh operation, may be set differently by the memory controller  210 . As shown in  FIG. 5 , the delay amount may be set in such a manner that the refresh operations of the memories M 0  to M 7  may be performed sequentially, and this may prevent noise from occurring in the power source voltage. 
         [0040]    In the memory system, in accordance with embodiments of the present invention described above, it is possible to prevent a peak in current by staggering the operation timing of each memory, although the memories perform their refresh operation synchronously. 
         [0041]    According to an embodiment of the present invention, power noise may be prevented in a memory module including a plurality of memory devices by controlling the timings for the refresh operations of the semiconductor memory devices. 
         [0042]    While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.