Abstract:
An architecture for a smart liquid crystal display (LCD) panel interface is described. The architecture enables a circuit to transfer only updated display data to the interface. When there are no display data updates to transfer, the circuit is placed in the lowest power state to reduce power consumption while the interface displays information locally stored.

Description:
FIELD OF THE INVENTION 
   The present invention pertains to the field of integrated circuit design. More particularly, the present invention relates to a graphics architecture for reducing power and optimizing bandwidth. 
   BACKGROUND OF THE INVENTION 
     FIG. 1A  depicts an Unified Memory Architecture (UMA) for processing graphics to display on a liquid crystal display (LCD) panel  130 . A central processing unit (CPU)  110  is coupled to a chipset  120 . The chipset  120  comprises a main memory  122  and a memory controller hub (MCH)  124 . The MCH  124  is the central hub for processing data. The MCH is also coupled to a graphics engine  126  and a display controller  128 . The CPU  110  determines what data is to be displayed. Data that is to be displayed is accessed from main memory  122  by the MCH  124 . 
   Data is stored in main memory  122  in packet format. The packet comprises a header portion and a payload portion. The header provides the position and dimension of the image to be displayed. The payload contains the data of the image to be displayed. Thus, the packet graphics files must be rasterized or reconstructed out of those components before they can be presented as an actual image on the panel  130 . The graphics engine  126  computes and creates a bitmap of the data accessed by the MCH  124 . The bitmapped file contains pixel image data. Each dot on the LCD panel  130  is represented by data in the bitmapped file. The display controller  128  sends the data stream of pixels to a panel  130  to be displayed. 
     FIG. 1B  depicts a Discrete Graphics Architecture (DGA) for processing graphics to display on a LCD  170 . For this system, a CPU  140  is coupled to a chipset  150 . The chipset  150  comprises a main memory  152  and a MCH  154 . The MCH  154  is the central hub for processing data. In contrast to the system of  FIG. 1A , graphics engine  162  and display controller  164  are located on a discrete graphics chip  160  rather than on the chipset  150 . In addition, the discrete graphics chip  160  comprises a local frame buffer  166  for graphics engine  162 . The data that is to be displayed on LCD  170  is obtained from the frame buffer  166  rather than main memory  152 . 
   When the system is idle in the UMA, the CPU  110  and the MCH  124  may not quiesce to the lowest power state because the circuits have to maintain the data display stream to the LCD panel  130 . A computer system may be in an idle state when no data is being entered into the computer and when no programs are running. An user input such as a mouse-click or a key stroke brings the CPU  110  out of idle. The DGA of  FIG. 1B  may be more efficient than the UMA because the UMA drives data from a large main memory  152  to the LCD  170  while the DGA drives a smaller, dedicated, and less shallow memory subsystem to the LCD  170 . The CPU  140  and the MCH  124  of the DGA, however, also do not quiesce when the system is idle. In both the UMA and the DGA, an image frame is periodically transferred to the LCD panels  130  and  170 , regardless if the new frame is different from the previous frame. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The embodiments of the present invention are illustrated by way of example and not in the figures of the accompanying drawings, in which like references indicate similar elements and in which: 
       FIG. 1A  is a prior art Unified Memory Architecture that delivers data to a LCD panel; 
       FIG. 1B  is a prior art Discrete Graphics Architecture that delivers data to a LCD panel; 
       FIG. 2  is an embodiment of an Unified Memory Architecture for delivering data to a LCD panel that reduces idle power consumption and optimizes bandwidth; and 
       FIG. 3  is an embodiment of a Discrete Graphics Architecture for delivering data to a LCD panel that reduces idle power consumption and optimizes bandwidth. 
   

   DETAILED DESCRIPTION 
   In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention. 
     FIG. 2  depicts an embodiment of an UMA for optimizing bandwidth and reducing idle power consumption in a computer system. For this embodiment of the invention, CPU  210  is coupled to chipset  220 . Chipset  220  comprises a MCH  224  that is coupled to a main memory  222 , a graphics engine  226 , and a delta engine  228 . The chipset  220  is coupled to a panel  230 . The panel  230  comprises a receiver  232 . The receiver  232  is coupled to a timing controller  234 . The timing controller  234  is coupled to a display buffer  235 , a row driver  236 , and a column driver  237 . The row driver  236  and the column driver  237  are coupled to a liquid crystal display (LCD)  238 . 
   The power consumption of the UMA of  FIG. 2  is reduced because the CPU  210  and the chipset  220  may be quiesced or placed in the lowest power state if there is no updated data to display on panel  230 . In other words, the CPU  210  and the chipset  220  do not maintain a periodic stream of data to the panel  230  when the system is idle. A new image frame is sent to the panel  230  only if the new image frame is different from the previous image frame. The CPU of a mobile platform may be in idle approximately 70% of the time. Therefore, allowing idle circuits such as the CPU  210  and the chipset  220  to quiesce to the lowest power state helps to save battery life in a mobile platform. Power savings, however, may also be achieved in other systems such as a desktop platform. 
   If CPU  210  determines that a display update is required, the CPU  210  sends instructions to the chipset  220  to transmit the new image to the panel  230 . When the CPU  210  requests an image update, the MCH  224  accesses the requested data from the main memory  222 . The graphics engine  226  creates a bitmap of the data obtained from main memory  222 . The delta engine  228  then transmits the bitmap of the updated data to the panel  230 . The delta engine  228  only transmits data to the panel  230  if the new image frame is different from the previous image frame. 
   For one embodiment of the invention, each bitmapped pixel of the LCD  238  may be comprised of  18  bits of colors. For example, the colors may comprise six bits of red, six bits of green, and six bits of blue. For another embodiment of the invention, each pixel may be described using 24 colors. In addition to color, each pixel may comprise a display enable bit, a clock bit, and a plurality of raster bits. The raster bits may comprise a line pulse (LP) and a first line marker (FLM). The LP signal is a line synchronization pulse that latches a line of display data into the column driver  237 . The LP signal becomes active when a line of pixel data is clocked into the panel  230  and stays asserted for a duration approximately equal to the number of pixel clock periods. The FLM signal may indicate the start of a new display frame. The FLM signal activates each subsequent pixel row of the LCD  238  through the row driver  236 . The FLM signal is asserted after a first LP signal of the frame until a second LP signal is detected. The FLM signal then remains deasserted until the next frame. The data updates are transferred to the panel  230  when LP is asserted. 
   The data may be transmitted to panel  230  using high speed serial bus. Alternatively, the data may be transmitted via a low voltage differential swing signal. Thus, the receiver  232  may comprise a low voltage differential swing input/output buffer. When no update is received from chipset  220 , the timing controller  234  transmits a bitmapped image to be displayed from display buffer  235 . By providing a localized storage area to obtain data, the display buffer  235  helps to minimize the need to fetch data from main memory  222 . The main memory  222  may be used to store many different types of data. As a result, the main memory  222  may be accessed by circuits of a computer system for many reasons other than fetching display data. Contention in accessing data from main memory  222  may potentially decrease the efficiency of the system. Therefore, the display buffer  235  helps to optimize the bandwidth of main memory  222  and to increase the efficiency of the system. 
   When an update is received, however, the timing controller  234  transmits the bitmapped image as received by receiver  232  to the row driver  236  and the column driver  237 . The updated image may also be stored in the display buffer  235 . The row driver  236  and column driver  237  may display the image on the LCD  238  by sweeping across each line of the image, working their way down the LCD  238  from line to line. 
     FIG. 3  depicts an embodiment of a DGA for optimizing bandwidth and reducing idle power consumption in a computer system. For this embodiment of the invention, CPU  340  is coupled to chipset  350 . The chipset  350  comprises a main memory  352  coupled to a MCH  354 . The chipset  350  is coupled to a discrete graphics chip  360 . The discrete graphics chip  360  comprises a delta engine  364  that is coupled to a graphics engine  362  and a frame buffer  366 . The discrete graphics chip  360  is coupled to a panel  230 . The panel comprises a receiver  232  coupled to a timing controller  234 . The timing controller  234  is coupled to a display buffer  235 , a row driver  236 , and a column driver  237 . The row driver  236  and the column driver  237  are coupled to a liquid crystal display  238 . The storage capacity of the frame buffer  366  is a function of the resolution and pixel depth of the liquid crystal display  238 . 
   The power consumption of the DGA of  FIG. 3  may be reduced by placing the CPU  340 , the chipset  350 , and the discrete graphics chip  360  in the lowest power state if there is no updated data to display on panel  230 . CPU  340 , chipset  350 , and discrete graphics chip  360  do not maintain a stream of data to the panel  230  when the system is idle. However, if CPU  340  detects a display update, CPU  340  sends instructions to chipset  350  and discrete graphics chips  360  to transmit the new image to the panel  230 . 
   After the MCH  354  receives the CPU  340  instructions, the MCH accesses the main memory  352  for command instructions and passes the information to the discrete graphics chip  360 . The graphics engine  362  of the discrete graphics chip  360  then obtains the updated display from the frame buffer  366 . The graphics engine  362  creates a bitmap of the data file obtained from the frame buffer  366 . The delta engine  364  then transmits the updated data to the panel  230 . The processing of the graphics may be performed out of phase with respect to any other CPU  340  processes to further reduce power consumption. 
   The panel  230  of the DGA operates in the same manner as described above for the UMA. For one embodiment of the invention, the panel  230  may be used with a notebook, mobile or laptop system. For another embodiment of the invention, the panel  230  may be used with a desktop system. 
   In the foregoing specification the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modification and changes may be made thereto without departure from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense.