Abstract:
Disclosed is a Dual-Modulus Prescaler (DMP) dividing an input signal into an output signal, comprising: a synchronous counter, including a D-Flip-Flop (DFF), a first NOR-Flip-Flop and a second NOR-Flip-Flop, receiving the input signal, the division ratio thereof being based on an intermediate signal; a control logic, controlling the division ratio of the synchronous counter and selecting the output frequency based on first and second control signals, and outputting the intermediate signal to the synchronous counter; and an asynchronous counter, coupled to the control logic and the synchronous counter, having a chain of five DFFs.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of Invention  
         [0002]     The present invention relates to a prescaler. More particularly, the present invention relates to a dual-modulus prescaler (DMP) with dynamic circuit technique.  
         [0003]     2. Description of Related Art  
         [0004]     Frequency synthesizers are widely used in communication systems and microprocessors. A frequency synthesizer at least includes a frequency divider and a voltage-controlled oscillator (VCO). The operating frequency of the frequency synthesizer is limited by the frequency divider and the voltage-controlled oscillator (VCO).  
         [0005]     A dual-modulus prescaler (DMP) is a leading example in the frequency divider. A prescaler at least includes two parts, i.e., a synchronous counter and an asynchronous counter. The synchronous counter is the most crucial block in the whole DMP. The synchronous counter works at maximum frequency and consumes most power. The speed of the synchronous counter limits the maximum operating frequency of the prescaler. A merge structure of NAND gates and D-Flip-Flops (DFFs) is popular. When the synchronous counter is implemented in P-precharge dynamic circuit techniques, there are two serial NMOS transistors in the discharge path, which results a large delay and lowers the operating frequency.  
         [0006]     With a structure optimization of the synchronous counter, the operating frequency of the prescaler is increased and the power consumption thereof is lowered. Besides, there is a demand on an optimized structure of the DMP, which may reduce the propagation delay and have higher operating speed.  
         [0007]     Therefore, there is a need for developing a DMP meeting the requirements.  
       SUMMARY OF THE INVENTION  
       [0008]     One of the objects of the invention is to provide a dual-modulus prescaler (DMP) with higher operating frequency, lower power consumption, reduced propagation delay reduced and higher operation speed.  
         [0009]     To at least achieve the above and other objects, the invention provides a Dual-Modulus Prescaler (DMP) dividing an input signal into an output signal, comprising: a synchronous counter, including a D-Flip-Flop (DFF), a first NOR-Flip-Flop and a second NOR-Flip-Flop, receiving the input signal, the division ratio thereof being based on an intermediate signal; a control logic, controlling the division ratio of the synchronous counter and selecting the output frequency based on first and second control signals, and outputting the intermediate signal to the synchronous counter; and an asynchronous counter, coupled to the control logic and the synchronous counter.  
         [0010]     It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.  
         [0012]      FIG. 1  is a block diagram of a dual-modulus prescaler (DMP) according to one preferred embodiment of the present invention.  
         [0013]      FIG. 2  is a block diagram of a D-Flip-Flop (DFF) in the DMP of  FIG. 1 .  
         [0014]      FIG. 3  is a block diagram of an NOR-Flip-Flop (NOR-FF) in the DMP of  FIG. 1 .  
         [0015]     FIGS.  4 ( a ) and  4 ( b ) are output waveforms of the DMP, in divided-by-65 and-64 operations, respectively. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0016]     Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.  
         [0017]     In this invention, a Dual-Modulus (divide-by-128/129 or 64/65) Prescaler (DMP) based on dynamic circuit technique implemented in 0.25 μm CMOS digital technology is disclosed.  
         [0018]     The block diagram of the disclosed DMP is shown in  FIG. 1 . The DMP  10  includes a synchronous counter  20 , a control logic  30 , and an asynchronous counter  40 .  
         [0019]     The synchronous counter  20  is, for example but not limited to, a divide-by-4/5 counter. When the control signal MD outputting from the control logic  30  is logic high (MD=1), the division ratio of the synchronous counter  20  is four. When the control signal MD is logic low (MD=0), the division ratio of the synchronous counter  20  is five.  
         [0020]     In this invention, the synchronous counter  20  is made up of one D-Flip-Flop (DFF) DFF 1  and two NOR-Flip-Flops (NOR-FF) NOR-FF 1  and NOR-FF 2 . The NOR-FF is a flip-flop with NOR logic function. In the merge structure of NOR-FFs and DFF, the sizes of logic blocks are small, and fast storage elements share the same delays. So the propagation delay is reduced and the speed of the synchronous counter  20  is improved. These flip-flops are based on glitch-free configuration, but many modifications may be made to adapt the speed requirement of high frequency circuits. The input signal Fin is fed into the CLK terminals of the DFF 1  and the NOR-FF 1  and NOR-FF 2 .  
         [0021]      FIG. 2  shows the DFF 1  in the synchronous counter  20 . The DFF  1  includes PMOS transistors MP 1 ˜MP 5  and NMOS transistor MN 1 ˜MN 7 . The source electrodes of MP 1 ˜MP 5  are connected to VDD and the sources electrodes of MN 1 , MN 3 , and MN 5 ˜MN 7  are connected to GND. The signal CLK (the input signal Fin in  FIG. 1 ) is connected to the gate electrodes of MP 1 , MP 2 , MN 3  and MN 5 . The input terminal D is connected to the gate electrode of MN 1 . An internal node n 1  is connected to the drain electrodes of MP 1  and MN 1 , and the gate electrodes of MP 4 , MN 2 , and MN 6 . An internal node n 2  is connected to the drain electrodes of MP 4  and MN 6 , and the gate electrode of MN 4 . An internal node n 3  is connected to the drain electrodes of MP 2  and MN 2 , and the gate electrode of MP 3 . The source electrode of MN 2  is connected to the drain electrode of MN 3 . The source electrode of MN 4  is connected to the drain electrode of MN 5 . An output Q− is connected to the drain electrodes of MP 3  and MN 4 , and the gate electrodes of MP 5  and MN 7 . An output Q+ is connected to the drain electrodes of MP 5  and MN 7 .  
         [0022]     When CLK=0, the DFF 1  is in hold state and the internal nodes are pre-charged through the PMOS transistors (MP 1  and MP 2 ) controlled by the CLK signal. At rising edges of CLK, DFF 1  changes state based on the input signal D.  
         [0023]     Compared with prior art, the DFF 1  decreases the number of transistors, reduces the capacitive load, shortens the charge and discharge time by the reduction of transistors in the charge and discharge path and lowers dynamic power consumption. These improve the operating speed, reduce dynamic power consumption and make the circuit suitable for GHz frequency range. Although the static power consumption of the DFF 1  is slightly increased, in power consumption of high frequency applications, the dynamic power consumption due to continuous switch at high frequency dominates and the static power consumption is not significant.  
         [0024]      FIG. 3  shows the NOR-FF 1  (or NOR-FF 2 ) in the synchronous counter  20 . As shown, the NOR-FF 1  (or NOR-FF 2 ) includes PMOS transistors MP 6 ˜MP 10  and NMOS transistors MN 8 ˜MN 15 . The source electrodes of MP 6 ˜MP 10  are connected to VDD and the sources electrodes of MN 8 , MN 9 , MN 11 , and MN 13 ˜ 15  are connected to GND. The input signal CLK is fed into the gate electrodes of MP 6 , MP 7 , MN 11  and MN 13 . The input signal D 1  is fed into the gate electrode of MN 8 , and another input signal D 2  is fed into the gate electrode of MN 9 . An internal node n 4  is connected to the drain electrodes of MP 6 , MN 8  and MN 9 , and the gate electrodes of MP 9 , MN 10  and MN 14 . An internal node n 5  is connected to the drain electrodes of MP 9  and MN 14 , and the gate electrode of MN 12 . An internal node n 6  is connected to the drain electrodes of MP 7  and MN 10 , and the gate electrode of MP 8 . The source electrode of MN 10  is connected to the drain electrode of MN 11 . The source electrode of MN 12  is connected to the drain electrode of MN 13 . An output Q+ is connected to the drain electrodes of MP 8  and MN 12 , and the gate electrodes of MP  10  and MN 15 . An output Q− is connected to the drain electrodes of MP 10  and MN  15 . Based on  FIG. 3 , it is known that Q+=(D 1 +D 2 )′ and Q−=(D 1 +D 2 ). [Para  25 ]As shown in  FIG. 3 , there are two parallel NMOS transistors MN 8  and MN 9  in the discharge path. Compared to two serial NMOS transistors in the discharge path in prior art, the discharge time is reduced and the speed is improved.  
         [0025]     The control logic  30  includes an inverter INV 1 , two NOR gates NOR 1 ˜NOR 2  and four NAND gates NAND 1 ˜NAND 4 . The inverter INV 1  inverts the control signal SW and outputs to the NAND gate NAND 1 . The NAND gate NAND 1 , a two-input NAND gate, inputs the output of the inverter INV 1  and the output signal Q+ from the DFF 6  of the asynchronous counter  40 . The NAND gate NAND 3 , a two-input NAND gate, inputs the control signal SW and the output signal Q+ from the DFF 5  of the asynchronous counter  40 . The NAND gate NAND 4 , a three-input NAND gate, inputs the output from the NOR gate NOR 2 , the output signal Q− from the DFF 3 , and the output signal Q− from the DFF 2  of the asynchronous counter  40 . The NAND gate NAND 4  outputs the signal MD to the D 2  terminal of the NOR-FF 2  in the synchronous counter  20 . The NOR gate NOR 1 , a two-input NOR gate, inputs the control signal SW and the output signal Q− from the DFF 6  of the asynchronous counter  40 . The NOR gate NOR 2 , a four-input NOR gate, inputs the control signal MODE, the output from the NOR gate NOR 1 , the output signal Q+ from the DFF 5  of the asynchronous counter  40 , and the output signal Q+ from the DFF 4  of the asynchronous counter  40 . The NAND gate NAND  2  receives the outputs from the NAND gates NAND 1  and NAND 3 , and outputs the signal Fout.  
         [0026]     The control logic  30  controls the division ratio of the first stage and selects the output frequency. The control signal SW is used to select the dual-modulus division ratio as 128/129 or 64/65, while the fractional division ratio is selected according the control signal MODE. According to levels of the control signals SW and MODE, the output frequency of the DMP  10  is shown in following Table.  
                               TABLE                                   SW   MODE   Fout                           Low   High   Fin/128           Low   Low   Fin/129           High   High   Fin/64           High   Low   Fin/65                      
 
         [0027]     Fout is the frequency of the output signal OUT, and Fin is the frequency of the input signal IN. As shown in the above Table, when the signal SW is Logic Low and the signal MODE is Logic High, Fout is Fin/128, which means the DMP  10  executes a divide-by-128 operation. When the signal SW is Logic Low and the signal MODE is Logic Low, the frequency of Fout is Fin/129, which means the DMP  10  executes a divide-by-129 operation. When the signal SW is Logic High and the signal MODE is Logic High, the frequency of Fout is Fin/64, which means the DMP  10  executes a divide-by-64 operation. When the signal SW is Logic High and the signal MODE is Logic Low, the frequency of Fout is Fin/65, which means the DMP  10  executes a divide-by-65 operation.  
         [0028]     The asynchronous counter  40  is a chain of five DFFs, i.e., DFF 2 ˜DFF 6 . The operating frequency thereof is one-fourth or one-fifth of the input frequency, so the speed requirement is decreased. However, it requires the DFF is low power consumption, glitch-free and no limit of the minimum operating frequency to maintain the good performance of the whole circuit. A fast DFF configuration is suitable.  
         [0029]     To verify the performance of the DMP in the invention, the DMP is implemented in 0.25 μm single-poly five-metal N-well salicide 2.5V CMOS digital process. FIGS.  4 ( a ) and  4 ( b ) show the output waveforms of the DMP in divide-by-65 operation mode (Fout=Fin/65) and divide-by-64 operation mode (Fout=Fin/64), respectively. In FIGS.  4 ( a ) and  4 ( b ), the input signal is a sine waveform with an amplitude of 0.8V and a frequency of 2.5 GHz and the power supply (VDD) is 2.5V. The horizontal scale is 5 ns/div and the vertical scale is 0.5V/div. Under the conditions, the measured power supply current is 14 mA. So the whole power consumption is 35 mW. Because the prescaler works well at 3 GHz, the maximum input frequency of the prescaler is higher than 3 GHz. The measure result proves the prescaler has excellent performance and may be applied to many RF systems.  
         [0030]     As above discussion, a divide-by-128/129 or 64/65 Dual-Modulus prescaler is disclosed. It uses NOR-FF structure instead of NAND-FF structure, and uses dynamic circuit technique to optimize the DFF in the synchronous counter. These make the DMP work at high frequency and keep low power consumption. In this invention, the propagation delay of the DMP is reduces and the operating speed thereof is higher. The experiment results show that the DMP works well in gigahertz (GHz) frequency range.  
         [0031]     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing descriptions, it is intended that the present invention covers modifications and variations of this invention if they fall within the scope of the following claims and their equivalents.