Abstract:
A wafer process for molded chip scale package (MCSP) comprises: depositing metal bumps on bonding pads of chips on a wafer; forming a first packaging layer at a front surface of the wafer to cover the metal bumps; forming an un-covered ring at an edge of the wafer to expose two ends of each scribe line of a plurality of scribe lines; thinning the first packaging layer to expose metal bumps; forming cutting grooves; grinding a back surface of the wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal seed layer at a bottom surface of the wafer in the recessed space; cutting off an edge portion of the wafer; flipping and mounting the wafer on a substrate; depositing a metal layer covering the metal seed layer; removing the substrate from the wafer; and separating individual chips from the wafer by cutting through the first packaging layer, the wafer, the metal seed layers and the metal layers along the scribe lines.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This patent application is a Continuation in Part (CIP) Application of a pending application Ser. No. 14/317,152 filed on Jun. 27, 2014 by having a common inventor. The Disclosure made in the patent application Ser. No. 14/317,152 is hereby incorporated by reference. 
     The application Ser. No. 14/317,152 is a Continuation in Part (CIP) Application of an application Ser. No. 13/602,144 filed on Sep. 1, 2012 and issued as a U.S. Pat. No. 8,853,003 on Oct. 17, 2014 by having a common inventor. The Disclosure made in the U.S. Pat. No. 8,853,003 is hereby incorporated by reference. 
     The application Ser. No. 14/317,152 is a Continuation in Part (CIP) Application of an application Ser. No. 13/931,854 filed on Jun. 29, 2013 and issued as a U.S. Pat. No. 8,778,735 on Jul. 15, 2014 by having a common inventor. The Disclosure made in the U.S. Pat. No. 8,778,735 is hereby incorporated by reference. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to a packaging method of semiconductor devices. Particularly, this invention aims at providing an improved wafer process for MCSP for obtaining thin chip packages with thick backside metal and molding compound on front side and/or backside of the devices. 
     DESCRIPTION OF THE RELATED ART 
     In a wafer level chip scale package (WLCSP) technology, the semiconductor chip is packaged directly on the wafer level after the semiconductor chips are finished completely on the wafer following by the separation of individual chip packages from the wafer. As a result, the size of the chip package is same as the size of the original semiconductor chip. Conventionally, the WLCSP technology is widely used for the semiconductor devices. As well known in the art, vertical power device, such as a common drain MOSFETs, has larger Rdson. Therefore, the wafer is thinned to reduce the substrate resistance, thus Rdson is reduced. However, as the wafer is thinner, it is difficult to treat and handle the thin wafer due to lack of the mechanical protection. In addition, to reduce the Rdson in vertical power device, a thick backside metal is required to reduce spreading resistance. Conventional processes usually use a thick lead frame and the semiconductor chips are then attached on the thick lead frame. However, this approach cannot achieve 100% chip scale package. 
     In addition, in the conventional chip scale packaging technology, the wafer is directly cut along the scribe line at the front surface of the wafer to separate individual chip packages from the wafer. However, the front surface of the wafer is usually packaged with a molding compound before the wafer is thinned to enhance the mechanical support for the wafer to prevent the thinned wafer from cracking. As a result, the scribe line is covered by the molding compound. Therefore, it is difficult to cut the wafer along the scribe line at the front surface of the wafer. 
     Given the above description of related prior arts, therefore, there is a need to manufacture ultra thin chips with thick backside metal and molding compound on front side and/or backside of the devices by WLCSP. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       As shown in attached drawings, the embodiment of the invention is more sufficiently described. However, the attached drawing is only used for explaining and illustrating rather than limiting the range of the invention. 
         FIG. 1A  is a top view of the front surface of a semiconductor wafer having semiconductor chips formed thereon. 
         FIG. 1B  is a cross-sectional schematic diagram of the semiconductor wafer having metal bump formed on the semiconductor chip&#39;s metal bonding pad. 
         FIGS. 2A-2B  are schematic diagrams illustrating the step of depositing a first packaging layer to cover the front surface of the wafer. 
         FIGS. 3A-3B  are schematic diagrams illustrating steps of grinding to thin the first packaging layer and forming cutting grooves on the first packaging layer. 
         FIG. 4  is a cross-sectional schematic diagram illustrating the step of grinding to thin the wafer from its back surface. 
         FIG. 5  is a cross-sectional schematic diagram illustrating the step of depositing a thin metal layer at the bottom surface of the thinned wafer. 
         FIG. 6  is a cross-sectional schematic diagram illustrating the step of cutting the edge portion of the wafer. 
         FIG. 7  is a cross-sectional schematic diagram illustrating the step of flipping and mounting the wafer of  FIG. 6  on a substrate. 
         FIG. 8  is a cross-sectional schematic diagram illustrating the step of depositing a thick metal layer on the thin metal layer at the bottom of the thinned wafer. 
         FIG. 9  is cross-sectional schematic diagram illustrating a step of removing the substrate from the wafer formed in the step shown in  FIG. 8 . 
         FIG. 10  is a cross-sectional schematic diagram illustrating the step of separating individual packaging structures with backside metal exposed by cutting through the first packaging layer, the wafer and the metal layer. 
         FIG. 11  is cross-sectional schematic diagrams illustrating a step of forming a second packaging layer on the thick metal layer of the device structure in  FIG. 8  before removing the substrate and separating the individual packaging structures. 
         FIG. 12  is cross-sectional schematic diagram illustrating a step of removing the substrate from the wafer formed in the step shown in  FIG. 11 . 
         FIG. 13  is cross-sectional schematic diagram illustrating a step of separating individual packaging structures of the wafer formed in the step shown in  FIG. 12  with molding compound on top and bottom sides of the packaging structure by cutting through the first packaging layer, the wafer, the metal layer and the second packaging layer. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       FIG. 1A  is a top view of a wafer  100  including a plurality of semiconductor chips  101  formed on the front surface of the wafer with each scribe line  102  located between two adjacent chips  101 . It is well known in the art that individual chip  101  is separated from the wafer  100  by cutting along the scribe line  102 . Generally, a plurality of metal bonding pads (not shown) are formed on the front surface of each chip  101  forming the electrodes of the chip, which connect to the power supply, the ground or a terminal for signal transmission with an external circuit. 
     As shown in  FIG. 1B , conductive bumps  110 , for example metal pumps, are formed on each metal bonding pad at the front surface of each chip  101 . The metal bump  110  can be made of a conductive material, such as copper, gold, silver, aluminum and the like or their alloy. The metal bump  110  can have a shape of sphere, ellipse, cube, cylinder, or wedge and the like. 
     As shown in  FIG. 2A , a packaging material, such as epoxy resin and the like, is deposited to form a first packaging layer  120  with a certain thickness covering the front surface of the wafer  100  and all metal bumps  110 . As shown in  FIGS. 2A and 2B , the radius of the first packaging layer  120  is slightly smaller than the radius of the wafer  100 , as such the first packaging layer  120  does not cover the whole front surface of the wafer  100 , for example, an un-covered ring  103  close to the edge of the wafer is not covered by the first packaging layer  120 . 
     As shown in  FIG. 3A , the first packaging layer  120  is ground to expose the metal bumps  110 . In one embodiment, the thickness of the first packaging layer  120  after grinding is about 50 microns to 100 microns. The metal bump  110  is preferably made of a harder metal, for example copper, to eliminate the unexpected contamination at the grinding surface of the first packaging layer  120  when the dust from the metal bump is adhered on the grinding wheel while grinding the first packaging layer. In  FIG. 3A , a plurality of cutting grooves  121  are then formed on the front surface of the thinned first packaging layer  120 . As shown in  FIG. 2B , the radius of the first plastic packaging layer  120  is smaller than the radius of the wafer  100  to ensure that the two ends of each scribe line  102  in the un-covered ring  103  is not covered by the first plastic packaging layer  120 . The cutting groove  121  can be formed by cutting a shallow line on the front surface of the first packaging layer  120 , which is aligned with a scribe line  102  extending from its two ends exposed in the un-covered ring  103 . Particularly, each shallow line or cutting groove  121  is overlapped with the corresponding scribe line  102  as shown in  FIG. 3B . The depth of the cutting groove  121  can be adjusted. In one embodiment, the cutting groove  121 A (as shown in dashed lines in  FIG. 3A ) can penetrate through the first packaging layer  120  to the front surface of the wafer. 
     As shown in  FIG. 4 , the wafer  100 , with an original thickness of 760 microns, is ground at its back surface to a predetermined thickness, which is about 50 microns to 100 microns. In a preferred embodiment, the ground first plastic package layer is thicker than the ground wafer for a mechanical support. In addition, to provide a mechanical support for the thinned wafer, a support ring at the edge of the wafer is not ground. As shown in  FIG. 4 , a recessed space  130  is formed by grinding the back surface of the wafer  100  with a grinding wheel having a radius smaller than the radius of the wafer  100 . The radius of the recessed space  130  is as large as possible to maximize the yield of chips formed close to the edge of the wafer. In this step, a support ring  104  at the edge of the wafer  100  is formed and the width of the support ring  104  is the difference between the radius of the wafer  100  and the radius of the recessed space  130 . In this step, the designed thickness of the thin wafer  100  can be adjusted by the depth of the recessed space  130 . The support ring  104  and the thinned packaging layer  120  provide a mechanical support for the thinned wafer  100 , thus the thinned wafer is not easy to crack. In one embodiment, the radius of the recessed space  130  is smaller than the radius of the first packaging layer  120  in order to further maintain the mechanical strength of the thinned wafer  100 , so that a portion of the first packaging layer  120  can be partially overlapped with a portion of the support ring  104 . In examples of the present disclosure, an optional metal layer  140 A is deposited at the bottom surface of the wafer  100  in the recessed space  130  for an Ohmic contact and used as a barrier for the metal seed layer  140  ( FIG. 5 ) to diffuse into the semiconductor wafer  100 . 
     As shown in  FIG. 5 , optionally, dopants are heavily doped at the bottom surface of the wafer  100  exposed inside the recessed space  130  followed by the annealing for dopants to diffuse. Then, a thin metal layer  140 , such as TiNiAg, TiNi, TiNiAl and the likes, is deposited at the bottom surface of the wafer  100 , for example by evaporation or sputtering. The thin metal layer  140  may be used as a seed layer  140  for the deposition of a thick metal layer in a next step. 
     As shown in  FIG. 6 , the edge portion  105  of the thinned wafer  100  and the support ring  104  are cut off. The overlapped part  122  of the first packaging layer  120  is also cut off. The width of the cut edge portion  105  of the wafer is equal to or slightly greater than the width of the support ring  104 . 
     As shown in  FIG. 7 , the whole wafer structure of  FIG. 6  is flipped and mounted on a substrate  142 . The substrate  142  can be a dummy wafer, a metal plate or a resin plate. The whole wafer structure of  FIG. 6  can be mounted on the substrate  142  using a double side tape, a thermal release material, or glue. 
     As shown in  FIG. 8 , a thick bottom metal layer  124  is deposited atop the thin metal layer  140  by electroplating and/or electroless plating. The metal layer  124  can be Al, Ag, Cu, Ni, Au and the likes. The thickness of the bottom metal layer  124  is about 10 microns to 100 microns depending on the size of the semiconductor chips formed on the wafer. In general bottom metal layer  124  should be at least 1/10 of the wafer thickness for wafer grounded to 100 microns or less. For wafer grounded to 50 microns, the bottom metal layer should be at least ⅕ of the wafer thickness, preferably more than ½ of the wafer thickness. In one embodiment, with a thickness of the ground wafer (in  FIG. 4 ) of about 50 microns, a bottom metal layer with a thickness larger than 50 microns is deposited. For wafer grounded less than 50 micron, bottom metal layer  124  should be more than ½ of the wafer thickness. As the metal layer  124  is formed by deposition, no adhesive material such as solder or epoxy between the wafer bottom surface and the surfaces of the bottom metal layer. Thick metal layer not only provides the benefit of resistance reduction and better heat dissipation, but also provides the mechanical support for the integrity of the wafer and semiconductor chip during the fabrication process especially after the thickness of the wafer is reduced less than 100 micron. The substrate  142  is then removed from the wafer structure as shown in  FIG. 9 . 
     As shown in  FIG. 10 , the first packaging layer  120 , the wafer  100 , the seed layer  140  and the thick bottom metal layer  124  can be cut through by a cutter  180  along the cutting groove  121  to separate individual chips  101  from the wafer  100 . As a result, the first packaging layer  120  can be cut into a plurality of top packaging layers  1200 , the seed layer  140  can be cut into a plurality of seed layers  1400 , and the thick bottom metal layer  124  can be cut into a plurality of thick bottom metal layer  1240 , thus a plurality of wafer-level packaging structures  200 A are obtained. Each packaging structure  200 A includes a top packaging layer  1200  covering the front surface of each chip  101 , a seed layer  1400  covering the back surface of the chip  101  and a thick bottom metal layer covering the seed layer  1400  with the metal bump  110  exposed out from the top packaging layer  1200  functioning as contact terminals of the packaging structure  200 A to electrically connect the external circuit and the thick bottom metal layer  1240  exposed at the bottom of the packaging structures  200 A functioning as a contact terminal of the packaging structure  200 A and also for heat dissipation. 
     In one embodiment, the chip  101  is a vertical MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), in which the current flows from the front surface to the back surface of the chip or vice versa. As such, the plurality of metal bonding pads formed at the front surface of the chip includes a bonding pad forming a source electrode and a bonding pad forming a gate electrode, and the bottom metal layer  1240  forms the drain electrode of the chip. With the thick bottom metal layer  1240 , the resistance of the packaging structures  200 A can be greatly reduced. 
     In another embodiment, a packaging structure  200 B with a bottom packaging layer  1320  can be formed as shown in  FIGS. 11-13 . After the thick bottom metal layer  124  is deposited atop the thin metal layer  140  as shown in  FIG. 8 , a second packaging layer  132  is formed to cover the thick bottom metal layer  124  as shown in  FIG. 11 . Then the substrate  142  is removed from the wafer structure as shown in  FIG. 12 . 
     As shown in  FIG. 13 , the first packaging layer  120 , the wafer  100 , the seed layer  140 , the thick bottom metal layer  124  and the second packaging layer  132  are cut to separate individual chips  101  from the wafer  100 . As a result, the first packaging layer  120  is cut into a plurality of top packaging layers  1200 , the seed layer  140  is cut into a plurality of seed layers  1400 , the thick bottom metal layer  124  is cut into a plurality of thick bottom metal layers  1240  and the second packaging layer  132  is cut into a plurality of bottom packaging layer  1320 , thus a plurality of packaging structures  200 B are obtained. Each packaging structure  200 B includes a top packaging layer  1200  covering the front surface of the chip  101 , a seed layer  1400  covering the back surface of the chip  101 , a thick bottom metal layer  1240  covering the seed layer  1400 , and a bottom packaging layer  1320  covering the thick bottom metal layer  1240  with the metal bump  110  exposed out of the top packaging layer  1200  functioning as a contact terminal of the packaging structure  200 B for electrically connecting with the external circuit. In this embodiment, since the thick bottom metal layer  1240  is covered by the bottom packaging layer  1320 , the bottom metal layer  1240  cannot be used as the contact terminal for connecting with the external circuit. As such, when the chip  101  is a vertical MOSFET, the plurality of metal bonding pads formed at the front surface of the chip include a bonding pad forming a source electrode, a bonding pad forming a gate electrode, and bonding pads electrically connecting to the bottom metal layer  1240  forming the drain electrode through a metal interconnecting structure (not shown) formed in the chip. 
     The above detailed descriptions are provided to illustrate specific embodiments of the present invention and are not intended to be limiting. Numerous modifications and variations within the scope of the present invention are possible. The present invention is defined by the appended claims.