Abstract:
An integrated circuit comprising logic circuits and at least one push-pull stage. In order to reduce the magnitude of induction voltages on power supply lines of the circuit, caused by the current variations in the push-pull stage comprising a push transistor and a pull transistor, a first current through one transistor is kept substantially constant until after a most significant rise of a second current through the other transistor when the push-pull stage is switched. A push-pull stage produces lower induction voltages during switching can thus be realized without adversely affecting the switching speed.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to an integrated circuit, comprising logic circuits and at least one push-pull stage which comprises, connected in a first path between a first power supply line which carries a high supply voltage and a stage output, a current channel of a push transistor and, connected in a second path between the stage output and a second power supply line which carries a low supply voltage, a current channel of a pull transistor. Control means are provided which are connected to control electrodes of the push transistor and the pull transistor in order to generate, when a logic state of the stage changes, time-dependent control voltages in order to reduce voltage noise on the power supply lines which is caused by current variations at the stage output. 
     Such an IC comprising a push-pull stage is known from Netherlands Patent Application No. 8601558, which corresponds to U.S. Pat. No. 4,783,601 (11/8/88), and which is hereby incorporated by reference. The known push-pull stage comprises control means for generating time-dependent control voltages on the control electrodes of the push transistor and the pull transistor in order to reduce voltage noise on the internal power supply lines of the circuit. Due to variations of the load current which the push-pull stage supplies to an output load, induction voltages are generated across inductances present in the power supply lines. The control means control the currents through the push transistor and the pull transistor so that the currents are varied by a constant amount per unit of time during switching i.e. the currents vary linearly with time during switching. Consequently, the said load current, being the difference between these currents, is also varied by a constant amount per unit of time. When the load current is made to vary linearly in time, the maximum value of the interfering voltages induced thereby is limited and is constant. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to improve the known push-pull stage by reducing the induction voltages occurring on the power supply lines even further. To achieve this, an integrated circuit in accordance with the invention is characterized in that during the switching of the push-pull stage the control means keep a first current through one transistor of the stage substantially constant until a greatest rise has occurred in a second current through the other transistor of the stage. In the known push-pull stage the currents through the push transistor and the pull transistor change substantially simultaneously, one current increasing linearly in time by an amount which equals the amount by which the other current decreases. Because the load current is the difference between these two currents, the variation of the load current is cumulative. By keeping one current substantially constant until the other current variation has taken place substantially completely, the maximum value of the induction voltage generated is reduced without deterioration of the switching speed. 
     An embodiment of an integrated circuit in accordance with the invention, in which the control means comprise controllable charge paths and dicharge paths which are connected to the control electrodes of the push transistor and the pull transistor, is characterized in that in its conductive state the discharge path between the control electrode of the pull transistor and the second power supply line conducts a substantially smaller maximum current than the charge path between the first power supply line and the control electrode of the push transistor in the conductive state of said charge path. The push transistor is then fully conductive before a current through the pull transistor can vary substantially. This is due on the one hand to the rise of the drive voltage across the pull transistor and on the other hand to the decrease of the control voltage of the pull transistor. 
     A further embodiment of an integrated circuit in accordance with the invention is characterized in that the discharge path for the control electrode of the push transistor comprises a current channel of a discharge transistor, which current channel connects a node between the current channels of the push transistor and the pull transistor to the control electrode of the push transistor. Just before the push transistor turns off, a current through this transistor is substantially independent of a voltage across its current channel, which is referred to herein as the driving voltage. By thus connecting the control electrode of the push transistor, when this transistor is going to be cut-off, to a node between the current channels of the push transistor and the pull transistor via the discharge transistor, during which operation the pull transistor is made conductive, the push transistor initially continues to supply a substantially constant current. This situation changes only when the voltage at said node has dropped so far below the voltage on the control electrode of the discharge transistor that the latter transistor starts to discharge the input of the push transistor. 
     Another embodiment of a push-pull stage in accordance with the invention is characterized in that the control means comprise a control circuit which includes a switching transistor, a current channel of which is connected to the control electrode of the push transistor in series with the relevant charge path, which switching transistor forms an inverter circuit in conjunction with the discharge transistor. The control means comprise a second control circuit which includes a second inverter circuit which has an output connected to the control electrode of the pull transistor and which is formed by a second switching transistor, having a current channel connected between the control electrode of the pull transistor and the relevant charge path, and by a second discharge transistor having a current channel connected between the control electrode of the pull transistor and the second power supply line. The charge paths of the first and the second control circuit each comprise, connected to the first power supply line, a current channel of a respective cascode transistor, a control electrode of which is connected to the output of the respective inverter circuit, and also comprise, connected parallel to the current channel of the respective cascode transistor, a current channel of a respective further cascode transistor. An input of the first and the second inverter circuit, are connected, via a first and a second delay element, respectively, to a control electrode of the respective further cascode transistor. The further cascode transistor is made conductive after a delay. Initially, this cascode transistor does not influence the voltages in the inverter circuit which generates, as described in the prior art, a suitable control voltage which ensures a linear variation in time of the currents switched by the transistors of the push-pull stage. The further cascode transistor raises the output voltage of the inverter circuit to the voltage level of the first power supply line only after expiration of a given period of time. In comparison with the prior art, this is a better way of keeping the current variation in time substantially linear. According to the prior art, the further cascode transistor is rendered conductive without delay so that the said variation of the current in time in the push transistor, or the pull transistor, is influenced from the very beginning. 
     Another embodiment of a push-pull stage in accordance with the invention is characterized in that the discharge path between the control electrode of the pull transistor and the second power supply line comprises at least first and second parallel paths. The first parallel path can be switched off in response to on a control signal to be applied to the control means while the second parallel path can be switched off in response to a voltage at a gate first and second output of a logic gate, gate inputs of which are connected to the control electrode of the pull transistor and to the push-pull stage output, respectively. For example, in the case of an extremely large capacitive load on the stage output the pull transistor could be cut-off prematurely, thus causing large current variations and hence high induction voltages. By switching off a part of the discharge path in these circumstances, a more gradual current variation through the pull transistor is achieved. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The invention will be described in detail hereinafter with reference to the accompanying drawing; in which: 
     FIG. 1 shows a circuit diagram of a push-pull stage, 
     FIGS. 2A and 2B illustrate a current variation in a push-pull stage according to the state of the art, 
     FIGS. 3A and 3B show a current variation in a push-pull stage in an integrated circuit in accordance with the invention, 
     FIG. 4 shows a preferred embodiment of a push-pull stage in an integrated circuit in accordance with the invention, and 
     FIG. 5 shows a detail of the push-pull stage in the integrated circuit shown in FIG. 4. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows a circuit diagram of a push-pull stage. The stage comprises a cascode connection of a push transistor T 1  and a pull transistor T 2  between power supply lines carrying the supply voltages V DD  and V SS . The output K of the stage is loaded by, for example, a TTL circuit which is represented in the Figure by resistances R 1  and R 2 , connected in series between the power supply lines, and a capacitance C 0  which is connected parallel to the resistance R 2 . The stage also comprises a control circuit CC, inputs of which receive logic signals D and D. The transistors T 1  and T 2  are controlled by means of mutually logically complementary control signals. The load current I 0  at all times equals the difference between the current I 1  conducted by the transistor T 1  and the current I 2  conducted by the transistor T 2 . For example, when the push transistor T 1  is made conductive and the pull transistor T 2  is blocked substantially simultaneously, the variation of the current I 1  per unit of time amounts to: dI 1  /dt, positive, and the variation of the current I 2  per unit of time is: dI 2  /dt, negative. The variation of the load current I 0  per unit of time (dI 0  /dt) equals the sum of the absolute values of the variations in I 1  and I 2  : 
     
         dI.sub. 0 /dt= |dI.sub.1 /dt| +|dI.sub.2 /dt|. 
    
     On the internal power supply lines, which inevitably include parasitic inductances L 1  and L 2  coupled via a parasitic capacitance C p , this current variation dI 0  /dt causes a high induction voltage giving rise to interference, for example, in the logic state of other parts of an integrated circuit in which the push-pull stage is included. 
     FIGS. 2A and 2B illustrate the variation in time of the currents I 1  and I 2  and the load current I 0 , and their time derivatives, for a circuit according to the present state of the art. When the most significant variations in the currents I 1  and I 2  coincide substantially in time, the variation dI 0  /dt generates a maximum induction voltage equal to the sum of the absolute extreme values of dI 1  /dt and dI 2  /dt. 
     FIGS. 3A and 3B illustrate the variation in time of the currents I 1  and I 2  and the load current I 0 , and their time derivatives, for a circuit in accordance with the invention. Because the extreme values of dI 1  /dt and dI 2  /dt have been shifted in time with respect to one another, the maximum induction voltage dI 0  /dt is substantially a factor 2 times smaller than in the case illustrated with reference to FIGS. 2A and 2B. 
     FIG. 4 shows a preferred embodiment of a push-pull stage in accordance with the invention. A TTL load, represented by resistances R 1 , R 2  and a capacitance C 0 , is connected to output terminal K of the stage which comprises a push transistor T 1  and a pull transistor T 2 . The push transistor T 1  receives a control signal V 1  from a first control circuit INV1 and the pull transistor T 2  receives a control signal V 2  from a second control circuit INV2. Each of the control circuits INV1 and INV2 comprise a controllable discharge path which is formed by a transistor T 3  and a transistor T 8 , respectively. The function of the transistor T 3 , which is connected between the control electrode of the push transistor T 1  and the output terminal K, will be described with reference to FIG. 5. The charge paths of the control circuits INV1 and INV2 comprise transistors T 4  to T 7  and T 9  to T 12 , respectively. Because the charge paths have the same construction, only that of the control circuit INV1 will be described hereinafter. A similar explanation applies to the charge path in the control circuit INV2. Therefore, when reference is made to a component of the control circuit INV1, a reference to a corresponding component of the control circuit INV2 is stated between parentheses. The transistor T 4   (T 9 ) serves as a switch for the transistor T 5  (T 10 ) which is connected as a current source and which has a control electrode connected to the control electrode of the push transistor T 1  (pull transistor T 2 ). Using this set-up, a time-dependent control signal V 1  (V 2 ) is formed such that, when the push transistor T 1  (pull transistor T 2 ) is activated, the current therethrough increases approximately linearly in time. This linear time dependency limits the maximum value of the interference voltages induced by the current variations in the push-pull stage. Because T 5  (T 10 ) is cut off further as the control voltage V 1  (V 2 ) increases, there is provided a parallel transistor T 6  (T 11 ) which raises the control voltage V 1  (V 2 ) to the supply voltage V DD  after a retardation via the delay element DL1 (DL2). Due to the delayed switching-on of the parallel transistor, it initially has no effect on the control voltage variation realized by the transistor T 5  (T 10 ). In order to improve the control voltage variation of V 1  (V 2 ) for a current which varies linearly in time in the push transistor T 1  (pull transistor T 2 ) when the control voltage V 1  (V 2 ) approaches the supply voltage V DD , there is provided a non-linear capacitance which is realized by means of the transistor T 7  (T 12 ). Because this capacitance decreases strongly as the control voltage V 1  (V 2 ) increases beyond a voltage equal to V DD  minus a threshold, an excessively low charge current via the transistors T 5  and T 6  (T 10  and T 11 ) to the control electrode of the push transistor T 1  (pull transistor T 2 ) is compensated for in said control voltage interval. In order to enable the current through the pull transistor T 2  to be kept substantially constant when the push transistor T 1  is turned on, the discharge path for the control electrode of the pull transistor T 2 , comprising the transistors T 8 , T 13  and T 14 , is proportioned with respect to the charge path for the control electrode of the push transistor T 1 , comprising the transistors T 4 , T 5  and T 6 , in such a way that the maximum discharge current through the aforesaid discharge path is a factor from 1.5 to 10 times smaller than the maximum charge current through the charge path. For a W/L ratio of 535/1.3 for the push transistor T 1  and of 531/1.3 for the pull transistor T 2 , it has been found that the following W/L ratios suffice: 
     
         --T.sub.4 :80/1.3--T.sub.5 :30/1.3--T.sub.6 :40/1.3 
    
     
         --T.sub.8 :2/1.3--T.sub.10 :14/1.3--T.sub.14 :14/1.3. 
    
     It is thus achieved that the push transistor T 1  is already fully conductive before a current through the pull transistor T 2  changes substantially. The pull transistor T 2  then operates in the linear range. The decrease of the control voltage on the control electrode of T 2  and the increase of the driving voltage across the current channel of T 2  oppose one another in as far as the current variation is concerned. The discharge path in INV2 comprises a first path consisting of transistor T 8  and a second path consisting of transistors T 13  and T 14 . The transistors T 8  and T 14  receive the same control signal, the transistor T 13  receiving a signal from a logic NAND gate P 1 . The gate P 1  is fed on the one hand by the control signal for the pull transistor T 2  (V 2 ) and on the other hand by the output voltage V 0  at the terminal K. For example, if the load capacitance C 0  or the load resistance R 1  were very high, the switching off of the pull transistor T 2  would be too fast when the discharge path is fully conductive, thus causing an excessively large current variation and hence an excessively high induction voltage. This can be avoided by temporairly switching off a part of the discharge path. When the control signal V 2  is high and the output voltage V 0  still has a level above a predetermined value, the transistor T 13  is blocked via the NAND-gate P 1 . The instant of switching on or off of the transistor T 13  depends inter alia on the transition point of the gate P 1 , the dimensions of the transistors forming the gate, and on a delay element DL3, if any, between the gate output of the gate P 1  and the control electrode of the transistor T 13 . The capacitance T 15  serves to achieve gradual switching of the transistor T 13 . 
     FIG. 5 shows a detail of the push-pull stage shown in FIG. 4. The push transistor T 1  and the pull transistor T 2  are shown, and also the TTL load which is represented by the resistances R 1 , R 2  and the capacitance C 0 , which load is connected to the output terminal K. Terminals A and B are connected to further parts of the control circuit (not shown). Between the control electrode of the push transistor T 1  and the output terminal K there is formed a discharge path which includes a discharge transistor T 3 . Just before the instant of switching off, the push transistor T 1  operates in the saturated state. The current conducted is thus independent of a driving voltage across the current channel. The output voltage V 0  on the output terminal K is then high. The switching off of the push transistor T 1  is preceded by the switching on of the pull transistor T 2 , the uncoupling of the terminal A from the remainder of the control circuit, and the activation of the further transistor T 3  by means of a high voltage. Via the terminal E the further transistor T 3  is driven to full output when the push transistor T 1  is switched off. Because the output voltage V 0  is still high at that instant, the further transistor T 3  will operate beyond or near its threshold voltage, which implies that the control electrode of the push transistor T 1  is not discharged or only partly so. During the decrease of the output voltage V 0 , the push transistor T 1  remains saturated and delivers a constant current. It is only when the output voltage V 0  has decreased sufficiently far that the further transistor T 3  starts to conduct that the control electrode of the push transistor T 1  is discharged further.