Abstract:
Apparatus and method for generating internal voltages within an integrated circuit. Current drivers are configured to pass current from external sources to internal power lines in response to circuit power needs and operating mode (e.g., active, stand-by, deep power down, and so forth). The current drivers preferably have switching thresholds at or outside of the voltage range of the internal voltage supply lines. Single current drivers can be modulated on one or more internal supply lines, preferably in response to comparing the internal voltage supply line with a reference voltage. Additional embodiments describe parallel current drivers, preferably configured with differing current carrying capacity, switched singly or in combinations to control internal voltage supply line power in response to the operating mode of the integrated circuit. The invention is directed toward decreasing noise susceptibility, and reducing both power dissipation and current leakage, especially under stand-by and power-down operating modes.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims priority from U.S. provisional application Ser. No. 60/571,063 filed on May 14, 2004, incorporated herein by reference in its entirety. 
     
    
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT  
       [0002]     Not Applicable  
       INCORPORATION-BY-REFERENCE OF MATERIAL SUBMITTED ON A COMPACT DISC  
       [0003]     Not Applicable  
       NOTICE OF MATERIAL SUBJECT TO COPYRIGHT PROTECTION  
       [0004]     A portion of the material in this patent document is subject to copyright protection under the copyright laws of the United States and of other countries. The owner of the copyright rights has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the United States Patent and Trademark Office publicly available file or records, but otherwise reserves all copyright rights whatsoever. The copyright owner does not hereby waive any of its rights to have this patent document maintained in secrecy, including without limitation its rights pursuant to 37 C.F.R. § 1.14.  
       BACKGROUND OF THE INVENTION  
       [0005]     1. Field of the Invention  
         [0006]     This invention pertains generally to integrated circuits, and more particularly to internal voltage converters within integrated circuits. 2. Description of Related Art  
         [0007]     The internal voltage converter (IVC) is widely used in VLSI design to control the operating voltage of the chip for reliability and power reduction. The operating voltage is controlled on an internal voltage supply line within the integrated circuit from an external supply voltage.  
         [0008]     It will be recognized that smaller integrated circuit device geometries provide increased circuit density and reduced power consumption. However, these device can be constrained to operate at lower voltages, or are at least preferably operated at reduced voltage levels to reduce power dissipation. For example consider the case when the external system voltage is 3.3V with an integrated circuit fabricated with 0.13 μm technology whose maximum voltage (to guarantee device reliability) is less than 3.3V. In this case the operating voltage for the chip should be lowered below 3.3V, while it still must interface with devices operating at the external system voltage. It should be appreciated that lowering the voltage for the chip allows reducing the power consumption accordingly. By way of example, dropping the internal operating voltage from 3.3V to 1.3V can result in lowering power consumption by approximately 60%.  
         [0009]     In these cases an internal voltage converter (IVC) provides a mechanism for generating the required internal voltage, such as depicted by the conventional IVC scheme of  FIG. 1 . The conventional IVC scheme is composed of the driver (mpdrv 1 ), the error detector (AMP 1 ) and a reference voltage (V ref1 ) to control the level of the internal voltage (IV CC ).  
         [0010]     External voltage (EV CC ) provides the power for the IVC and is typically a higher voltage than the internal voltage (IV CC ) generated by the IVC, and couples to the source of the IVC. The generated voltage IV CC  couples to the source of logic circuits within the logic block in  FIG. 1  to supply the current for circuit operation. The IVC level is determined by a reference voltage (V ref1 ). As the IV CC  level starts exceeding V ref1 , the voltage of node N 1  rapidly increases toward turning off driver mpdrv 1  to reduce the current flowing from the external source (EV CC ) to the internal source (IV CC ). After some cycles of circuit operations, when IV CC  level decreases and is lower than V ref1 , the voltage of node N 1  decreases to turn on the driver to recover the lowered level. Having the driver in the feedback loop therefore maintains internal voltage (IV CC ) in relation to the reference voltage V ref1 .  
         [0011]     However, the conventional IVC scheme shown in  FIG. 1  suffers from a number of shortcomings. The first shortcoming is a susceptibility to a power noise when electrical noise exists at EV CC . Since EV CC  is a source of the PMOS driver mpdrv 1 , the noise at the power source is transferred directly to IV CC  wherein the voltage IV CC  is output in response to the variation of EV CC . A second shortcoming is the leakage current that exists in the deep power-down modes. Even though PMOS driver mpdrv 1  is off, the leakage current flowing through it is not negligible and represents a large portion of the total leakage current when the device is in deep power-down mode.  
         [0012]     Accordingly, a need exists for an internal voltage converter which can efficiently support a different internal voltage for the device without being subject to the noise and leakage problems of conventional IVC implementations.  
       BRIEF SUMMARY OF THE INVENTION  
       [0013]     Internal voltage converters (IVCs) are described which can be implemented within a variety of integrated circuits to provide a stable internal voltage with improved noise immunity and reduced power-down leakage, in particular at stand-by, or in power-down operating modes. The IVCs are implemented using current drivers comprising FET transistors, such as depletion and/or enhancement mode MOSFETs, and is well suited for use with NMOS pass transistors. It should be appreciated that the apparatus and method amenable to embodiment with a wide variety of transistors, and are not limited to use with specific types of transistors.  
         [0014]     Internal voltage converters are described in general while a number of specific IVC embodiments are also taught. By way of example and not limitation, IVCs are taught which use analog control of switching, such as with an operational amplifier (or less preferably a form of comparator or discriminator) as well as IVCs which singly or in combination switch parallel pass transistors according to the operating mode. Two general types of IVC are also described, a standby IVC (SIVC) and an active IVC (AIVC). Standby IVCs (SIVCs) switch on after chip power is on and the chip is in the standby mode in order to maintain the IV CC  level. By contrast active IVCs (AIVCs) are activated during chip operation to maintain IV CC .  
         [0015]     The IVC devices generally comprise at least one pass element which is controlled in response to detected power needs, such as detected on one or more internal voltage supply lines, or in response to operating mode. In one set of embodiments the power needs are detected by a voltage error detector. Another set of embodiments determines the power needs based on the operating mode of the integrated circuit device, wherein it activates current drivers singly or in combination. Within the present invention the structure and configuration of the means for detecting the power needs and the current drivers are unique and provide a number of benefits in relation to conventional IVC devices.  
         [0016]     The invention is amenable to being embodied in a number of ways, including but not limited to the following. One embodiment of the invention can be generally described as an apparatus for generating an internal voltage supply line within an integrated circuit from an external supply voltage, comprising: (a) a current driver passing a desired level of current between an external power supply input and at least one internal power supply line for an integrated circuit; (b) wherein the current driver is configured with a switching threshold at or more preferably outside of the range of voltages available on the internal voltage supply line; and (c) means for modulating the gate voltage of the current driver to control the switching state in response to power needs detected on the internal voltage supply line for the operating mode of the integrated circuit (e.g., active, stand-by, power-down, deep power-down).  
         [0017]     The current driver, or drivers, may comprise any FET transistor, or transistor circuit. NMOS depletion or enhancement mode transistors are used according to one preferred embodiment to reduce leakage currents and increase noise immunity, in part due to their smaller footprint. It should also be noted that by driving the transistors with voltages at, or more preferably outside of the range of the internal voltage supply lines that both noise and leakage are reduced.  
         [0018]     In one embodiment the means for modulating the gate voltage comprises an error detector circuit configured for detecting voltage errors on the internal voltage supply line in relation to a reference voltage. The error detector circuit preferably comprises an operational amplifier, or similar. In another embodiment multiple parallel current paths are provided and their activation and deactivation controlled singly or in combination according to the operating mode of the integrated circuit. In this embodiment the current driver(s) comprise at least two parallel transistor circuits (i.e., capable of switching different levels of current), and the means for modulating gate voltage comprises logic for activating singly, or in combination, the parallel transistor circuits for supplying the internal voltage supply. It should also be appreciated that the above two approaches can be combined in one circuit, wherein parallel current drivers are controlled singly or in combination with an analog feedback signal. Overall, it should be appreciated that that aspects of the described embodiments can be implemented singly, or in combination with one another, and/or in combination with what is known to one of ordinary skill in the art without departing from the teachings of the present invention.  
         [0019]     It is preferred in these embodiments that the external supply voltage exceeds the internal supply voltage by an amount equal to or exceeding the threshold voltage of the current driver circuit (i.e., single MOSFET transistor such as NMOS or PMOS transistor). The current drivers are driven by a voltage range equal to or exceeding the internal voltage source range, or more preferably to a voltage range that is at or exceeding the external supply voltage range. Embodiments describe controlling a single internal voltage supply line, opposing positive and negative supply lines, multiple internal voltage supply lines (positive and/or negative), wherein a wide range of integrated circuit applications can be supported.  
         [0020]     An additional power control circuit can be coupled to control the activity of the current drivers in response to the operating mode of the integrated circuit, such as when entering standby or power-down modes.  
         [0021]     An embodiment of the invention can also be described as an apparatus for generating an internal supply voltage within an integrated circuit from an external supply voltage, comprising: (a) a current driver coupled between an external power supply and an internal supply line of an integrated circuit; (b) wherein the current driver is configured with a switching threshold at or outside of the range of voltages available on the internal supply line; and (c) an error detector configured for modulating the gate voltage of the current driver in response to voltage errors detected between the internal voltage supply line and a reference voltage. It should be appreciated that the internal voltage is preferably compared directly with the reference voltage, although it may be compared to a scaled and/or offset version of the reference voltage. Consequently, the present invention does not limit how the comparisons are made against the reference voltage for providing switching feedback.  
         [0022]     The error detector (i.e., operational amplifier) is configured with an output voltage swing sufficiently outside of the range of voltages available on the internal supply line to control the switching of the current driver. Additional circuits can be incorporated to modulate the gate voltage of the current driver(s) in response to the operating mode of the integrated circuit. These circuits can alter, or switch, the level of current through the current driver(s) and provide for shutting down (deactivating) unnecessary circuits in response to stand-by, deep power-down modes, and so forth.  
         [0023]     An embodiment of the invention can also be described as an apparatus for controlling internal voltage supplies within an integrated circuit configured for operating in different power modes, comprising: (a) multiple parallel switching devices supplying current to one or more internal voltage supply lines for the integrated circuit; (b) wherein the parallel switching devices are configured to have different current drive capabilities; and (c) a switching device driver coupled to each of the switching devices and configured to control the activation of each switching device in response to power modes within the integrated circuit.  
         [0024]     At least a portion of the parallel switching devices in this embodiment are configured with a switching threshold at or outside of the range of the internal voltage supply lines. The multiple parallel switching devices comprise parallel transistors coupled for providing current to each of multiple positive, multiple negative, positive and negative, or multiple positive and negative internal voltage supply lines. The switching device driver is configured for activating selected parallel switching devices to supply current on one or more of the internal voltage supply lines in response to the operating modes (e.g., active, stand-by, and deep power down) of the integrated circuit.  
         [0025]     An embodiment of the invention can also be described as a method of generating internal voltages for an integrated circuit, comprising: (a) coupling at least one current pass transistor having a threshold voltage at or outside of the range of voltage being supplied on an internal voltage supply line to a circuit device; (b) detecting power needs on the internal voltage supply line for the present operating mode of the integrated circuit; (c) driving the switching state of the current drive (pass) transistor in response to the detected power needs on the internal voltage supply line; and (d) wherein the current drive transistor is either activated or switched off by driving its gate with a voltage outside of the range of the internal voltage supply lines.  
         [0026]     The detecting of power needs, according to one embodiment, comprises detecting voltage error on the internal voltage supply line in comparison with a reference voltage. The switching states are then driven by this feedback to maintain a desired voltage level on the internal voltage supply line. In another embodiment detecting of power needs comprises activating select current pass transistors in response to the operating mode of the integrated circuit. In either embodiment the switching threshold of the current drivers is preferably at or more preferably outside of the voltage range of the internal voltage supply lines, wherein the control circuits must generate control voltage outside of the internal supply voltage range. In these embodiments the switching state of the current drivers can be changed in response to power mode selections within the integrated circuit.  
         [0027]     An embodiment of the invention can also be described as a method of generating voltage on internal voltage lines within an integrated circuit, comprising: (a) coupling multiple parallel current pass switches, configured for passing different levels of current, between external supply voltages and internal voltage supply lines within the integrated circuit; and (b) deactivating selected the pass switches in response to stand-by and power down modes within the integrated circuit.  
         [0028]     The embodiment can further comprise supplying current through the current pass switches for both positive and negative internal voltage supply lines, while multiple positive internal voltage supply lines, multiple negative internal voltage supply lines, or multiple positive and negative internal voltage supply lines are also readily supported.  
         [0029]     Described within the application are a number of beneficial inventive aspects, including but not necessarily limited to the following.  
         [0030]     An aspect of the invention is an internal voltage converter (IVC) using an NMOS transistor driven by an error detector circuit.  
         [0031]     Another aspect of the invention is an IVC that supports active and/or stand-by voltage conversion.  
         [0032]     Another aspect of the invention is an IVC using either an enhancement or depletion mode NMOS transistor, or transistors.  
         [0033]     Another aspect of the invention is an IVC using an NMOS transistor, or transistors, with an external voltage, or boosted voltage, which compensates for the drop across the pass element of the IVC, such as an NMOS transistor.  
         [0034]     Another aspect of the invention is an IVC configured for having its error detector shut down in response to circuit operating mode, such as in response to entering a standby or shut-down state.  
         [0035]     Another aspect of the invention is an IVC configured with a pass element that is controlled by an error detector within a first set of circuit modes, and controlled by circuit signals other than from the error detector in a second set of circuit modes.  
         [0036]     Another aspect of the invention is an IVC having an NMOS driver, current passing device, configured with a gate whose voltage is boosted to provide an internal voltage level without a voltage threshold drop problem in active mode and subject to being self-reverse biased in another mode.  
         [0037]     Another aspect of the invention is a power control apparatus which utilizes power pass elements having different characteristics according to the operating mode of the device.  
         [0038]     A still further aspect of the invention is a method of controlling voltages generated within a device in response to operating mode.  
         [0039]     Further aspects of the invention will be brought out in the following portions of the specification, wherein the detailed description is for the purpose of fully disclosing preferred embodiments of the invention without placing limitations thereon. 
     
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)  
       [0040]     The invention will be more fully understood by reference to the following drawings which are for illustrative purposes only:  
         [0041]      FIG. 1  is a schematic of a conventional internal V CC  converter (IVC) shown with the voltage converter section powering a logic block.  
         [0042]      FIG. 2  is a schematic of an IVC generator according to an embodiment of the present invention shown for actively converting the voltage in response to control logic inputs.  
         [0043]      FIG. 3  is a schematic of a standby IVC (SIVC) generator (Type 1) according to an embodiment of the present invention.  
         [0044]      FIG. 4  is a schematic of another standby IVC (SIVC) generator (Type 2) according to an embodiment of the present invention.  
         [0045]      FIG. 5  is a schematic of a first type of power management according to an embodiment of the present invention.  
         [0046]      FIG. 6  is a schematic of a second type power management according to an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0047]     Referring more specifically to the drawings, for illustrative purposes the present invention is embodied in the apparatus generally shown in  FIG. 2  through  FIG. 6 . It will be appreciated that the apparatus may vary as to configuration and as to details of the parts, and that the method may vary as to the specific steps and sequence, without departing from the basic concepts as disclosed herein.  
         [0048]     1. Active IVC Generator.  
         [0049]      FIG. 2  illustrates by way of example, an IVC generator according to the invention having a current pass element which comprises an NMOS driver (mndrv 21 ) instead of the conventional PMOS driver. This novel arrangement is somewhat counterintuitive and has not been adopted by the industry. However, this novel IVC generator circuit provides an ability to suppress noise effects at the power line as well as reducing leaking currents. The NMOS transistor in this embodiment can comprise a depletion or enhancement mode transistor, or transistors, depending on device process technology. Although a preferred configuration describes the use of a single NMOS driver transistor, it should be appreciated that multiple elements may be utilized. A device (mnctrl 22 ) is configured for controlling the NMOS driver, such as coupled to the gate input of the NMOS driver. The error detector AMP 2  is coupled to the driver and controlled according to the operating modes and applications for the device. It should be noted that the error detector is configured in this embodiment with a reverse sense in relation to the conventional PMOS driver.  
         [0050]     In a normal mode, the new IVC operates in a similar manner as the conventional scheme shown in  FIG. 1 . When the internal (IV CC ) voltage level is higher than v ref2  the voltage of node N 2  decreases toward turning off the driver to reduce the current from the external power to the internal power. When the IV CC  level is lower than a v ref2 , the voltage of node N 2  increases toward turning on the driver thereby increasing the current flow from external power to internal power.  
         [0051]     According to circuit applications, the IVC can be generally classified into at least two modes. One is referred to herein as standby IVC (SIVC) generation and the other as active IVC (AIVC) generation. SIVC is turned on after the chip power is on and the chip is in standby mode and configured for maintaining the IV CC  level within this substantially static mode of operation. AIVC is turned on when necessary during the active operation of the chip to maintain IV CC  level despite heavier current requirements which are typically more dynamic in nature. Therefore, both the static and active voltage conversions in the SIVC and AIVC have to be properly controlled in response to the given operating mode of the device. Therefore, AIVC shown in  FIG. 2  needs to be turned off in both standby and deep power down mode while SIVC is only turned off when in deep power-down mode.  
         [0052]     AIVC is preferably controlled by operating mode signals, such as exemplified by stand-by (ST) and deep power-down (DPD) as depicted in the figure. In a preferred embodiment, the error detector controlling the NMOS driver is configured to supply a voltage sufficiently higher than the internal voltage (IV CC ) to overcome the V t  drop due to use of the NMOS transistor. For example, when EV CC  is 1.5V, a target IV CC  level is 1.2V and V t  of the NMOS transistor is 0.7V the gate voltage of mndrv 21 , i.e., the voltage of node N 2  should be 1.9V (=1.2+0.7) to allow supplying 1.2V to the IV CC  node. If voltage EV CC  is significantly higher than voltage IV CC , for example EV CC  at 3.3V, IV CC  at 1.2V and V t  being 0.7V, then EV CC  can be used for the source voltage of AMP 2 . If the voltage EV CC  is not sufficient, then another boosted voltage should be generated internally or provided from an external source.  
         [0053]     In standby or deep power-down mode the NMOS driver can be turned off by another device, such as mnctrl 22 . In standby or deep power-down mode, the node C 2  goes to high to turn on mnctrl 22 , the N 2  node goes to V SS  and turn off the NMOS driver. In addition signal C 2  is preferably utilized for turning off AMP 2  to eliminate any power consumption. By pulling down the node N 2  to V SS , the V gs  of mndrv 21  is −V DD  (0−V DD =−V DD ), assuming that internal voltage level IV CC  is V DD  in the active mode, and the V gs  of a PMOS logic transistor is zero (e.g., considering the first PMOS transistor shown in the logic block in  FIG. 1 ).  
         [0054]     Since mndrv 21  receives a significantly stronger reverse-bias than the logic PMOS transistor, shown in the conventional IVC of  FIG. 1 , the leakage current through mndrv 21  is consequently far smaller than the leakage current of the PMOS logic transistor, wherein the IV CC  level decreases a bit. Therefore, the logic PMOS transistor also becomes reverse-biased. Thus, all transistors, including mndrv 21  and PMOS logic transistor become reverse-biased and the leakage current flowing through the NMOS driver, mndrv 21 , can be suppressed significantly compared to that of the conventional scheme. So, in the new IVC scheme using the NMOS driver leads to improving the power noise immunity while the use of a voltage higher than IV CC  can be achieved without any voltage drop issue in active mode and since both the NMOS driver and PMOS logic transistors are reverse-biased in standby and deep power-down modes the leakage current is suppressed significantly.  
         [0055]     2. Standby IVC Generator (Type 1).  
         [0056]      FIG. 3  is an embodiment of a first type (Type 1) standby IVC generator (SIVC). It should be appreciated that the standby (SIVC) differs from the active (AIVC) circuit shown in  FIG. 2 . The SIVC generator should be turned on when the chip is in standby mode, wherein SIVC is controlled in response to a device power-down (DPD) control signal as shown in  FIG. 3 . It should be recognized that the SIVC may be alternatively controlled with similar signals, or a group of signals, relating to standby operation. In the embodiment of  FIG. 3 , when the chip is in standby mode AMP 3  is turned-on to detect any voltage drop at the IVCC node and to recover its dropped level to a target level. However, the circuit is configured so that the NMOS driver as well as AMP 3  are turned-off when the device is subject to a deep power-down mode.  
         [0057]     3. Standby IVC Generator (Type 2).  
         [0058]     One issue with the new SIVC scheme illustrated in  FIG. 3  is the power consumption of error detector AMP 3  during standby mode. Since the voltage drop at the IV CC  level is detected and compared with V ref3  during the standby mode, AMP 3  should is turned on and consuming power.  
         [0059]      FIG. 4  illustrates a second type (Type 2) of SIVC which operates at reduced standby current levels. It can be seen in the figure that additional control circuits are shown coupled to the SIVC for controlling driver and AMP 4  operation in both standby and deep power-down modes. It can be seen that in the deep power-down mode, the error detector AMP 4  and the driver mndrv 41  are turned off as in the other IVC schemes in  FIG. 2  and  FIG. 3 .  
         [0060]     However, in  FIG. 4  the configuration is different because AMP 4  is turned off in standby mode and another switch means, such as mpctrl 43 , is activated to control the activity of the driver mndrv 41 . It should be appreciated that although transistor mpctrl 43  is depicted as a PMOS transistor, it can be replaced with an NMOS transistor. By turning on mpctrl 43  the IV CC  level can be made equal to EV cc -V tn , where V tn  is a threshold voltage of mndrv 41 . As a result, in this new SIVC circuit the power consumption of the error detector can be eliminated when in standby mode.  
         [0061]     It should be recognized that these embodiments represent a new method of generating internal circuit device voltages from externally available voltages. A simple embodiment of this method could be described as an internal voltage generation method comprising: (a) coupling at least one current pass transistor having a threshold voltage at or outside of the range of voltage being supplied on an internal supply voltage line to a circuit device; (b) detecting voltage fluctuations on the internal supply voltage line; and (c) driving the gate of the current driver (pass transistor) in response to the voltage fluctuations (i.e., voltage error in relation with a reference voltage); wherein the gate drive can be at or outside of the range of voltage supplied to the circuit device.  
         [0062]     In one embodiment an NMOS transistor replaces the PMOS transistor typically coupled from external V CC  (EV CC ) to internal V CC  (IV CC ) and is driven by a detector circuit having reversed sensing and at least one supply rail driven outside of the range provided by the internal supply voltage. In addition, at least one additional transistor can be coupled to the gate of the current pass transistor to modulate drive levels in response to the operating mode of the circuit device, such as stand-by and power-down modes. Furthermore, signals controlling the mode of the circuit device can select whether or not the error detector is activated. Still further, one or more additional transistors can be coupled to the driver, such as between the external power supply line and gate of the driver transistor, thereby controlling driver activity in response to an integrated circuit mode (i.e., stand-by or power-down) with the error detector shut down. It should be recognized that the apparatus and method is amenable to various modifications and can be practiced in a number of different ways which would be obvious to one of ordinary skill in the art and not limited to the embodiments exemplified in  FIG. 2  through  FIG. 4 .  
         [0063]     4. Power Management Types 1 and 2.  
         [0064]      FIG. 5  and  FIG. 6  represent power management mechanisms within integrated circuits which provide device power in a manner according to the specific operating mode of the device. In  FIG. 5 , transistors MN 1 , MN 2 , MN 3  and MN 4  control power received from the V DD  power source to two separate internal voltage supplies, while transistors MP 1 , MP 2 , MP 3  and MP 4  control V SS  power, respectively, from another two internal voltage supplies. It is preferable in this embodiment that transistors MN 1 , MP 1 , MN 2  and MP 2  are configured with higher current driving capacity than MN 3 , MP 3 , MN 4  and MP 4 . In addition, only source transistors MN 2  and MP 2  are connected to IV CC2  and IV SS2 , respectively with their gate voltages controlled to deliver V DD  and V SS  power levels without degradation. The logic states in standby mode for the logic block are also shown in  FIG. 5 .  
         [0065]     In active mode, all transistors, in this case MN 1 , MN 2 , MN 3 , MN 4 , MP 1 , MP 2 , MP 3  and MP 4  are active to allow the logic block to execute at its maximum speed. In standby mode transistors MN 5 , MP 6 , MN 7  and MP 8  are turned on to maintain logic states shown in  FIG. 5 . Therefore, transistors MN 1 , MN 4 , MP 1  and MP 4  are turned off. It should be appreciated that since only the state of the logic circuits needs to be maintained in standby mode, that transistors MN 2  and MP 2  can be turned off and only transistors MN 3  and MP 3  are kept active. In active standby-mode, the logic states depicted in  FIG. 5  are reversed, wherein high becomes low and vice versa. Therefore, in active standby-mode transistors MP 5 , MN 6 , MP 7  and MN 8  are turned on. In this case, MN 1  and MP 1  are turned off and small transistors, such as MN 4  and MP 4  can be turned on to suppress leakage current. The operation of these transistors can be controlled by a number of control signals depicted as C 1 , C 1 B, C 11 , C 11 B, C 21 , C 21 B, C 22  and C 22 B. It will be readily recognized that all source transistors can be turned off when the device enters deep power-down mode. The transistor characteristics and operation states for the embodiment of  FIG. 5  are summarized in Table 1.  
         [0066]     It should be appreciated that a number of alternatives to this power management mechanism and method can be implemented. For example different numbers and levels and types of transistors may be utilized without departing from the teachings of the present invention.  
         [0067]      FIG. 6  illustrates an example embodiment of a logic circuit whose power is managed according to the invention in a similar manner as shown in  FIG. 5 , however each transistors device is shown replaced by its complement, specifically PMOS transistors are used for V DD  control with NMOS transistors utilized for V SS  control. The transistor characteristics and operation states for  FIG. 6  are summarized in Table 2.  
         [0068]     It should be recognized that these power management embodiments can be considered a new method of controlling internal circuit device voltages from externally available voltages. A simple embodiment of this method could be described as a circuit device power management method, comprising: (a) coupling multiple parallel current pass switches between external supply voltages and supply voltages internal to a circuit device; and (b) activating selected pass switches in response to the desired power modes of the circuit device. The multiple current pass switches are preferably fabricated in different sizes, structures or geometries for providing different current driving capability. According to one mode of the method the current pass switches are coupled between both positive and negative outputs of the external supply voltages and the internal supply voltages. This novel power management method is particularly well suited for use with integrated circuits configured for operating under different supply voltage conditions in response to their operating modes. One of ordinary skill in the art should recognize that the novel aspects of the apparatus and methods taught herein can be practiced in a wide variety of ways without departing from the invention. By way of example, the device circuit can operate in modes including standby and power-down modes and any desired variations thereof with internal circuitry responsive to power being supplied by any desired number of internal supply lines.  
         [0069]     It should be understood that the extended operating power modes (i.e., beyond On and Off) of a device circuit, which have been exemplified as stand-by and power-down or deep power-down have been provided by way of example. The apparatus and method of the present invention can be practiced with a variety of power related modes regardless of what they are specifically referred to or to what extents they regulate the power dissipation and activity within the integrated circuit device.  
         [0070]     Although the description above contains many details, these should not be construed as limiting the scope of the invention but as merely providing illustrations of some of the presently preferred embodiments of this invention. Therefore, it will be appreciated that the scope of the present invention fully encompasses other embodiments which may become obvious to those skilled in the art, and that the scope of the present invention is accordingly to be limited by nothing other than the appended claims, in which reference to an element in the singular is not intended to mean “one and only one” unless explicitly so stated, but rather “one or more.” All structural and functional equivalents to the elements of the above-described preferred embodiment that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. Moreover, it is not necessary for a device or method to address each and every problem sought to be solved by the present invention, for it to be encompassed by the present claims. Furthermore, no element, component, or method step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or method step is explicitly recited in the claims. No claim element herein is to be construed under the provisions of 35 U.S.C. 112, sixth paragraph, unless the element is expressly recited using the phrase “means for.” 
                                                                   TABLE 1                           Transistor Characteristics and Operation States (type 1)                            Active-   Deep           Size   Active   Standby   Standby   Power-down                        MN1   Large   On   Off   Off   Off       MN2   Large   On   Off   Off   Off       MN3   Small   On   On   On/Off   Off       MN4   Small   On   Off   On/Off   Off       MP1   Large   On   Off   Off   Off       MP2   Large   On   Off   Off   Off       MP3   Small   On   On   On/Off   Off       MP4   Small   On   Off   On/Off   Off                  
 
         [0071]    
       
         
               
             
               
               
               
               
               
               
             
               
               
               
               
               
               
             
           
               
                 TABLE 2 
               
             
             
               
                   
               
               
                   
               
               
                 Transistor Characteristics and Operation States (type 2) 
               
             
          
           
               
                   
                   
                   
                   
                 Active- 
                 Deep 
               
               
                   
                 Size 
                 Active 
                 Standby 
                 Standby 
                 Power-down 
               
               
                   
                   
               
             
          
           
               
                 MP1 
                 Large 
                 On 
                 Off 
                 Off 
                 Off 
               
               
                 MP2 
                 Large 
                 On 
                 Off 
                 Off 
                 Off 
               
               
                 MP3 
                 Small 
                 On 
                 On 
                 On/Off 
                 Off 
               
               
                 MP4 
                 Small 
                 On 
                 Off 
                 On/Off 
                 Off 
               
               
                 MN1 
                 Large 
                 On 
                 Off 
                 Off 
                 Off 
               
               
                 MN2 
                 Large 
                 On 
                 Off 
                 Off 
                 Off 
               
               
                 MN3 
                 Small 
                 On 
                 On 
                 On/Off 
                 Off 
               
               
                 MN4 
                 Small 
                 On 
                 Off 
                 On/Off 
                 Off