Abstract:
Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells including a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.

Description:
BACKGROUND 
     1. Technical Field 
     The present invention relates to sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, useful in low-supply-voltage technologies. 
     Specifically, the invention relates to sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, said sensing circuitry comprising a sense amplifier having a first sensing-circuit portion connected to a cell to be read and a second reference-load-circuit portion connected to a reference generator. 
     The invention relates, particularly but not exclusively, to circuitry for sensing the state of memory cells in embedded applications with low supply voltages, this description making reference to that field of application for convenience of illustration only. 
     2. Prior Art 
     As is well known, semiconductor memories are organized in cell arrays set up as rows or wordlines and columns or bitlines. 
     Each cell has essentially a floating-gate transistor, which also has drain and source terminals. The floating gate is formed on top of a semiconductor substrate and separated from the substrate by a thin layer of gate oxide. A control gate is coupled capacitively to the floating gate through a dielectric layer, and metal electrodes are provided to contact the drain, source, and control gate so that predetermined voltage values can be applied the memory cell. 
     The cells in one wordline share an electric line driving their respective control gates (directly in flash memories, and indirectly through a pass transistor in EEPROMs), while the cells in one bitline have the drain terminal in common. 
     The state of the cell is sensed, i.e. the information stored in it is “read”, by means of sensing circuitry. 
     The reading is effected by sensing a current value that flows through a cell to be read, at a preset bias through an amplifying circuit, in particular a sense amplifier. 
     The sense amplifier is used to bias the cell drain terminal, as well as to read the cell state. The drain terminal is accessed through the bitline, which is, as mentioned before, a metal line interconnecting (directly in flash memories, and indirectly through a select transistor in EEPROMs) the drain terminals of all the cells in one column of the array. Thus, the bitline has an amount of capacitance that is proportionate to the vertical dimension of the array and must be precharged at the voltage level to which the drain terminal of a cell being read is to be biased. The precharging is also performed through the sense amplifier. 
     Recent generations of memories are designed to provide shorter access times along with larger storage capacities (i.e., number of cells) with supply voltages that are specified at ever lower levels. 
     Accordingly, faster sense amplifiers at low supply voltages are in demand. 
     A first prior approach to satisfy this demand is illustrated by a conventional sense amplifier SA1 for use in smart card applications, as shown in FIG.  1 . 
     In particular, the sense amplifier SA1 has a first circuit portion or sensing portion  1  connected between a voltage supply Vdd and ground GND. 
     The sensing portion  1  has a first leg, comprising a cascade of a PMOS transistor Mmir 10  and an NMOS transistor M 10 . The sensing portion  1  also has a second leg  3  comprising a native transistor NAT 1 , which is a low-threshold transistor connected between the voltage supply Vdd and a first node A. 
     The control terminal of the native transistor NAT 1  is connected to an interconnection node MAT, itself connecting the transistors Mmir 10  and M 10  together. The control terminal of transistor M 10  is connected to the node A. A resistor R is connected between the node A and a node BUS 1 . 
     This node BUS 1  is connected, through a decode circuit N 1 , to the drain terminal of a cell  4  whose state is to be sensed. 
     At steady state, the current flowing through the cell  4  also flows through the transistor NAT 1 . Since the voltage level at node A is dependent on the size of transistor M 10  and the bias current to transistor NAT 1 , the node MAT is brought to a level such that a voltage VGS (VMAT-VA) at transistor NAT 1  will cause a current I flowing through the transistor M 10  to equal the current ICELL 1  flowing through the cell  4 . Therefore, transistor NAT 1  effects a current-to-voltage conversion. 
     The sense amplifier SA 1  further comprises a second circuit portion, or reference portion  5 , connected between the voltage supply and ground GND. The reference portion  5  has a first leg  7  comprising a cascade of a PMOS transistor Mmir 20  and an NMOS transistor M 2 . The reference portion  5  also has a second leg  6  comprising a native transistor NAT 2  connected between the voltage supply Vdd and a node B. 
     The control terminal of the native transistor NAT 2  is connected to a node REF 2 , itself connecting the transistors Mmir 20  and M 2  together. The control terminal of transistor M 2  is connected to the node B, which also has a reference cell  8  connected to it. 
     This reference portion  5  performs dynamically like the first sensing portion  1 . The transistor NAT 2  effects then a current-to-voltage conversion, with the voltage level at node REF 2  being set by a given reference current IREF 2 . 
     If more current flows through the cell  4  to be read than through the reference cell  8 , then node MAT is at a higher voltage level than node REF 2 , whereas if the current through the cell  4  to be read is smaller than the current through the reference cell  8 , then node MAT is brought at steady state down to a lower voltage level than node REF 2 . 
     By comparing these two nodes, MAT and REF 2 , in a voltage comparator (not shown because conventional) the state of the cell  4  can be determined, the state of the reference cell  8  being known beforehand. 
     While being advantageous in several aspects, this first approach has shortcomings. The voltage difference between the voltage supply Vdd and ground GND is equal to the sum of the voltage Vds at PMOS Mmir 10 , voltage Vgs at the native (low-threshold) transistor NAT 1 , and voltage Vgs at the inverter M 10 , namely: 
     
       
           Vdd=VdsMmir   10 + VgsNAT   1 + VgsM   10   (1) 
       
     
     Equation (1) above becomes a fairly critical one with low supply voltages. 
     Another shortcoming comes from the bound placed on the size of transistors M 10  and NAT 1 . Transistor M 10 , in fact, cannot be highly conductive because the bitline bias is dependent on its voltage Vgs. 
     As best seen with reference to FIG. 2, however, the I-V characteristics of MOS transistors diverge from each other as temperature varies, except around a specific value of the voltage Vgs. This value of Vgs is the value at which temperature compensation is achieved between the effects of diminishing threshold as temperature increases (that depresses Vgs) and diminishing current gain (that increases the voltage Vgs for a given bias current I). 
     Nor can transistor M 10  deviate substantially from that value of the voltage Vgs. For example, it may be about 740 mV, to prevent the bitline bias from changing substantially with temperature. 
     Transistor NAT 1  cannot be highly conductive because the sensitivity S of the sense amplifier is dependent on it, as follows: 
     
       
           S=|dVMAT/dICELL   1 |=1 /gmNAT   1   (2) 
       
     
     where, 
     VMAT is the voltage at node MAT; 
     ICELL 1  is the current through the cell  4  to be read; and 
     gmBAT 1  is the transconductance of the native transistor NAT 1 . 
     For instance, assuming the circuit of FIG. 1 to have been dimensioned for sensitivity S≧25 mV/uA and the voltage difference at node BUS 1  (ΔVbus 1 )≦60 mV at varying temperatures between −40° and 125° C., a current ICELL 1 =3 uA is sufficient to bring the node MAT to about 1.1V, as shown in FIG. 3, and at Vdd=1.2V, the PMOS transistor Mmir 10  has Vds=100 mV and its mirrored current I goes to 7.3 uA, from 8 uA, as shown in FIG.  4 . 
     The sensing circuit SA1 is also used to precharge the bitline. Nodes MAT and REF are preset at the supply voltage Vdd and the ground voltage GND, respectively. At power-on of the sensing circuit SA1, node BUS 1  is discharged, i.e. is same as GND, and the voltage Vgs at the native transistor NAT 1  is initially same as Vdd. At this stage, transistor NAT 1  allows the bitline to be precharged with much overdrive and, therefore, a large current ICELL 1 . BUS 1 , while under charge, will tend toward the bias voltage set by transistor M 10  functioning as an inverter, and by its bias current I. Node MAT is then brought to a sufficient level for the current needed by the cell  4  to be read to flow through transistor NAT 1 . 
     Therefore, a need has arisen for a sensing circuit that can be operated on low supply voltages and that overcomes problems that besets prior-art sensing circuits. 
     SUMMARY OF THE INVENTION 
     In one aspect of the invention, sensing circuitry includes two current/voltage conversion blocks respectively connected to a memory cell to be read and to a reference cell, said blocks being connected to a single bias and precharge block such that the bias block is not in the conductive path between the voltage supply Vdd and ground GND of the individual conversion blocks. 
     Features and advantages of the sensing circuit according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings: 
     FIG. 1 is a diagram of a sense-amplifier read circuit according to the prior art; 
     FIG. 2 is a plot of the current vs. voltage characteristics of MOS transistors at different temperatures; 
     FIG. 3 is a plot of the voltages at two nodes of the sense-amplifier read circuit of FIG. 1; 
     FIG. 4 is a plot of a bias current of the sense-amplifier read circuit of FIG. 1; 
     FIG. 5 is a block diagram of sensing circuitry according to an embodiment of the invention; and 
     FIG. 6 is a schematic diagram of the sensing circuitry of FIG.  5 . 
    
    
     DETAILED DESCRIPTION 
     With reference to the drawings, in particular to FIG. 5 thereof, sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, adapted for use in low supply voltage technologies, is shown generally at  10  according to an embodiment of the invention. 
     The sensing circuitry  10  comprises a sense amplifier  11  of the differential type, employed to compare a current ICELL that flows through a cell  12  in a memory array with a reference current generated by a reference generator IREF. The reference current from the reference generator IREF is the current that flows through a reference cell  13 , e.g. a virgin cell, or is generated by a dedicated current-generating circuit. 
     The sense amplifier  11  uses two current-to-voltage (I/V) conversion blocks S 1  and S 2  to convert read analog data, i.e. the current values being read, to digital data. 
     More particularly, the circuitry  10  comprises first and second I/V conversion blocks S 1  and S 2  that are connected between a first voltage reference, e.g. the voltage supply Vdd, and a second voltage reference, e.g. ground GND. The blocks, S 1  and S 2 , generate first and second voltages VBUS and VOUT 1  for comparison in a comparator  14 . 
     According to an embodiment of the invention, a single bias and precharge block  15  supplies a bias current IPOL and a precharge current IPRECH to both blocks S 1  and S 2 . 
     An embodiment of the sensing circuitry  10  according to the invention will now be described in greater detail with reference to FIG.  6 . 
     Block S 1  comprises a first transistor Mmir 2 , which has its conduction terminals connected between the voltage supply Vdd and a first node BUS. A second transistor M 1  has its conduction terminals connected between this node BUS and ground GND. 
     In a preferred embodiment, the second transistor M 1  comprises two transistors M 1   a  and M 1   b  connected in parallel in a diode configuration. The cell  12  to be read is also connected to the node BUS. 
     The second block S 2  comprises a first transistor Mmir 3  having its conduction terminals connected between the voltage supply Vdd and a first node OUT. A second transistor M 2 , which may be an NMOS transistor, has its conduction terminals connected between the node OUT and ground GND. 
     In a preferred embodiment, the second transistor M 2  in the block S 2  may advantageously comprise two transistors M 2   a  and M 2   b  connected in parallel, with transistor M 2   a  provided in a diode configuration. The control terminal of transistor M 2   b  is then connected to node BUS. 
     The control terminals of transistor Mmir 2  and transistor Mmir 3  are connected together and to the bias and precharge block  15 . 
     Advantageously, these transistors Mmir 2  and Mmir 3  are PMOS transistors, whereas transistors M 1  and M 2  are NMOS transistors. 
     It should be noted that the blocks S 1  and S 2  of this invention use no bias transistor comparable to the transistors NAT 1  and NAT 2  of prior circuits. In this way, their path GATE-SOURCE, and hence the voltage VGS, can be removed from the path between the voltage supply Vdd and ground GND. 
     The bias and precharge block  15  includes a circuit that delivers the reference voltage VPOL to the P-channel transistors Mmir 2  and Mmir 3 , in order to they deliver the precharge current to node BUS. 
     In particular, the bias and precharge block  15  is connected between the voltage supply Vdd and ground GND, and has a first leg  16 , which comprises a cascade of a transistor Mmir 1  in diode configuration and a transistor M 6 . Transistor Mmir 1  forms a current mirror configuration with the transistors Mmir 2  and Mmir 3  of blocks S 1  and S 2 . 
     The bias and precharge block  15  has, moreover, a second leg  17 , which comprises a cascade of a transistor Mmir 0  and transistors M 4  and M 5 . The control terminals of transistors M 4  and M 5  are connected together. The control terminal of transistor Mmir 0  is driven by a reference voltage VIPSENSE. 
     Transistor M 6  has its control terminal connected via a common node A to transistors Mmir 0  and M 5 . 
     Advantageously, transistors Mmir 0  and Mmir 1  also form a current mirror. 
     The bias and precharge block  15  further comprises a transistor M 3  connected between the shared node by transistors M 4 , M 5  and ground GND. The control terminal of transistor M 3  is then connected, via a node FEEDBACK, to the control terminal of the transistor M 1  in the first block S 1 . 
     Advantageously, transistors Mmir 0  and Mmir 1  are PMOS transistors, whereas transistors M 3 , M 4 , M 5  and M 6  are NMOS transistors. 
     Advantageously in this embodiment of the invention, the two blocks S 1  and S 2  are such that nodes BUS and OUT will be at the same voltage level when the currents ICELL and IREF, respectively, that flows through the cell  12  to be read and the reference cell  13 , are the same. 
     Since at steady state, transistor M 3  shorts out the voltage Vds of transistor M 4 , transistors Mmir 1  and Mmir 2  will be mirroring a current IPOL, given as: 
     
       
           IPOL=I* ( W/L ) M6 /( W/L ) M5   (3) 
       
     
     where, 
     I is the current input to node A; 
     (W/L) M6  is the channel aspect ratio e of transistor M 6 ; and 
     (W/L) M5  is the channel aspect ratio e of transistor M 5 . 
     A current IM 1  flowing through transistor M 1 , comprised of transistors M 1   a  and M 1   b  in parallel, for example, is: 
     
       
           IM   1 = IPOL−ICELL   (4) 
       
     
     where, 
     IPOL is the bias current of blocks S 1  and S 2 ; and 
     ICELL is the current flowing through the cell  12  to be read. 
     The voltage VBUS at node BUS is proportional, except for the threshold voltage of transistor M 1 , to the current IM 1 . Thus, the larger current ICELL, the lower will be the voltage level VBUS at node BUS, according to Relation (4) above, and the higher the voltage level VOUT at node OUT. 
     By having the voltages at nodes BUS and OUT compared in the voltage comparator  14 , the state of the cell  12  to be read can be determined. 
     Advantageously, the comparator  14 , shown in FIG. 6, used for the comparison does not degrade the performance of the low-voltage sensing circuit  10 , since comparator  14  is a similar construction to the I/V conversion blocks S 1  and S 2 . 
     In particular, the comparator  14  is connected between the voltage supply Vdd and ground GND, and comprises: a current mirror formed of transistors Mmir 7  and Mmir 8 , with transistor Mmir 7  in a diode configuration. Each one of the transistors Mmir 7  and Mmir 8  in the mirror has a transistor M 10  and M 11  respectively connected in series therewith. 
     The control terminal of transistor M 10  is then connected to node OUT, while the control terminal of transistor M 11  is connected to node BUS. 
     Advantageously, transistors Mmir 7  and Mmir 8  are PMOS transistors, and transistors M 10  and M 11  are NMOS transistors. 
     To have a minimum of sensing errors caused by comparator  14 , a good match of blocks S 1  and S 2  must be achieved. This is done by having the transistors M 10 , M 11 , M 1  and M 2  all of the same size. 
     This also provides good control of power usage, because the current forced on blocks S 1  and S 2  of the sense amplifier  11  is at most passed through the transistors Mmir 7  and Mmir 8  of comparator  14 . 
     How the signals evolve dynamically will now be described. 
     Nodes BUS and OUT are preset at the supply voltage Vdd and the ground voltage GND, respectively. At power-on of the sense amplifier  11 , these nodes BUS and OUT are released, transistor M 3  is turned off, and the mirrored current by transistor Mmir 1  becomes: 
     
       
           IPRECH+IPOL=I ( W/L ) M6 (1/( W/L )) M4 +1/( W/L  ) M5 )  (5) 
       
     
     
       
         with, 
       
     
     
       
           IPRECH=I ( W/L ) M6 /( W/L ) M4   (6) 
       
     
     where, 
     I is the input current to node A; 
     (W/L) M6  is the channel aspect ratio of transistor M 6 ; 
     (W/L) M4  is the channel aspect ratio of transistor M 4 ; and 
     IPOL is as given by Relation (3). 
     The capacitance associated with the bitline that is connected to the drain of the cell  12  to be read is precharged quite rapidly by means of the current IPRECH added. 
     Upon the bitline reaching a level at which transistor M 3  is turned on, transistor M 3  shorts out transistor M 4 , and the mirrored current in transistor Mmir 1  is again IPOL, according to Relation (3) above. 
     The more resistive the transistor M 4 , the larger the current IPRECH and the faster is the bitline charged. 
     On the other hand, if transistor M 4  is made too resistive, the voltage level at node A could reach a value such that transistor Mmir 0  will move into the linear range and no longer mirror the input current I to node A correctly. 
     Advantageously in a modification of the sensing circuitry  10  according to an embodiment of the invention, the sense amplifier  11  further comprises an auxiliary precharge block  18 . 
     The auxiliary precharge block  18  delivers a precharge boost current IAUX. 
     In particular, the auxiliary precharging circuit  18  is connected between the voltage supply Vdd and ground GND, and comprises a current mirror formed of the PMOS transistors Mmir 5  and Mmir 6 , of which transistor Mmir 5  is a diode configuration, and a transistor M 9  connected in series with transistor Mmir 5 . 
     The auxiliary precharging circuit  18  has also a leg comprising a transistor Mmir 4  in cascade with a diode-configured transistor M 8 . The auxiliary precharging circuit  18  additionally comprises a transistor M 7  connected in parallel with transistor M 8 . 
     The control terminal of transistor M 7  and the conduction terminal of transistor Mmir 6  are connected to each other and to node FEEDBACK. 
     Advantageously, transistors Mmir 4 , Mmir 5  and Mmir 6  are PMOS transistors, and transistors M 7 , M 8  and M 9  are NMOS transistors. 
     The auxiliary precharging circuit  18  is dimensioned, for example, to deliver a current only during the precharging step. The more conductive transistor M 7 , the sooner is the auxiliary precharging step completed. The precharge current IAUX is set in particular by the ratios of the current mirrors formed of the PMOS transistors Mmir 5  and Mmir 6 . 
     Note should be taken of that this auxiliary precharging step is completed ahead of the sensing step, to avoid overshooting at the node BUS. 
     The sensing circuitry  10  is suitable to form, for example, a sense amplifier  11  capable of discriminating between the states of cells in an embedded EEPROM macrocell for applications SMARTCARD with a bitline capacitance of about 1 pF, supply voltages of down to 1.2 V or less, and a sensing time of less than 20 ns. Within this time range, the bitline would be precharged and the state of the cells with a supply voltage of 1.2 to 1.9 V determined. 
     To summarize, the sensing circuitry provides a circuit structure that is fully compatible with standard processes and enables discriminating between small current differences, e.g. differences of about 1 μA.