Abstract:
For detecting whether an input signal is above or below a reference level in such a way that brief signal interruptions and negative spurious pulses are not interpreted as decreases below the reference level, the detector includes an input comparator, a first delay circuit, a second delay circuit and an output circuit. The first delay circuit comprises a first integrator comprising a first transistor and a first capacitor, a first current source and a second comparator. The second delay circuit comprises a second integrator with a second transistor and a second capacitor, a second current source and a third comparator. The first delay circuit and the second delay circuit have equal delay times. In order to ensure that during detection of a decrease below the reference level a positive spurious pulse is not interpreted as an increase above the reference level a third Transistor connects a third current source in parallel with the first current source of the first delay circuit when the input signal lies below the reference level, so that the delay time of the first delay circuit becomes smaller than that of the second delay circuit.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a signal level detector for a compact disc player and, more particularly, to a level detector furnishing an output for controlling the position of the beam relative to the track. 
     2. Description of the Prior Art 
     Such a level detector may be employed in, for example, a Compact Disc Audio player. At the time of filing of the present Application such a player is commercially available under the type designation Philips CD 303. In such a player the digital audio information in the form of a spiral tracks of pits and lands is read by means of a laser beam and converted into a signal current. This signal current constitutes a sequence of sinusoidal pulses of variable width. The signal is amplified and applied to inter alia a plurality of level detectors, in which the signal level of the rectified signal is compared with a plurality of reference levels in order to supply control signals for the various control devices employed in a compact-disc player if these reference levels are not reached. The player has, for example, a tracking system in order to keep the laser beam on the track. The maximum signal level is obtained if the laser beam follows the center of the track. If the beam is offset from this center, the signal level decreases. If a level corresponding to approximately 60% of the nominal level is not reached, a level detector generates a control signal by means of which the laser beam is returned to the center of the track. In addition, the player has level detectors which, if a level corresponding to approximately 50% and 20% of the nominal level is not reached generate a control signal for respectively disabling a phase-locked loop in the speed-control system, which system becomes unreliable for low signal levels, and for detecting the absence of the signal as a result of flaws in and on the disc, so called drop-outs. For these control systems it is important that the level detectors accurately detect whether the levels are reached and in such a way that brief interruptions in the signal level between two consecutive pulses and spurious pulses cannot actuate these control systems. 
     In the known compact-disc player the level detectors are constructed as a discrete circuits with non-integrable capacitors. However, it may be desirable to integrate these detectors on the same substrate as the other control circuits. A level detector which, in prinicple, is suitable for this purpose is known from U.S. Pat. No. 4,338,530. 
     In this detector the input signal is applied to a comparator which compares the input signal level with a reference level. The output signal of this comparator is applied to a first delay circuit which ensures that if the input signal briefly decreases below the reference level of the comparator such a decrease does not produce an output signal on the output of the level detector. The level detector only produces an output signal on its output when the input signal has remained below the reference level of the comparator for a specific time interval. A second delay circuit ensures that when the input signal again exceeds the reference level of the comparator the output signal of the level detector is sustained until the input signal has remained above the reference level for a specific second time interval. 
     A drawback of this detector is that if the first time interval and the second time interval are equal to each other, which is desirable for the above-mentioned uses, a positive spurious pulse during a detected decrease below the reference level will be interpreted as an increase above the reference level. This leads to an undesired actuation of further circuits. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to improve the known level detector in such a way that the above problem is eliminated. According to the invention a level detector of the type defined in the opening paragraph is therefore characterized in that the first time interval and the second time interval are substantially equal to each other, in that a switchable third current source is arranged in parallel with the first current source, and in that the level detector is provided with switching means for switching on the third current source if the output of the third comparator of the second delay circuit is currentless. 
     At the instant at which a decrease below the reference level is detected, the third current source causes the first time interval of the first delay circuit to become smaller than the second time interval of the second delay circuit. This ensures that during a detected decrease below the reference level a positive spurious pulse is not detected as an increase above the reference level. 
     In one embodiment of the invention the second comparator comprises a first transistor of a first conductivity type having an emitter, a base and a collector, the emitter constituting the first input, the base constituting the second input and the collector constituting the output, and the third comparator comprises a second transistor of the first conductivity type having an emitter, a base and a first and second collector the emitter constituting the first input, the base constituting the second input and the first collector constituting the output, and in that the switching means comprise a third transistor of a second conductivity type opposite to the first conductivity type, having a base, an emitter and a collector, the base being connected to the second collector of the second transistor and the collector being connected to the third current source and, via a diode, to the output of the second comparator. 
     A further embodiment of the invention is characterized in that the first integrator comprises a fourth transistor (first integrator transistor) of the second conductivity type having a base, an emitter and a collector, the base being connected to the output of the input comparator, the emitter being connected to a point carrying a reference potential, and the collector being connected to the first current source, in that the second integrator comprises a fifth transistor (second integrator transistor) of the second conductivity type having a base, an emitter and a collector, the base being connected to the output of the second comparator, the emitter being connected to the point carrying a reference potential, and the collector being connected to the second current source, and in that the first current source, the second current source and the third current source each supply an output current which is proportional to the current-gain factor of a transistor of the second conductivity type. 
     Embodiments of the invention will now be described in more detail, by way of example, with reference to the accompanying drawings, in which: 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a known level detector, 
     FIG. 2 shows waveforms to explain the operation of the arrangement shown in FIG. 1, 
     FIG. 3 shows a level detector in accordance with the invention, and 
     FIG. 4 shows some waveforms to explain the operation of the arrangement shown in FIG. 3. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 shows a known level detector. The level detector comprises an input comparator 1 having an input 2 to which the input signal, in the present case an input current I i , is applied. The output of a current source 4 carrying a reference current I ref  is applied to the input 2. Further, the input 2 is connected to the emitter of a PNP transistor T 1  whose base is at a constant voltage V R  and whose collector is connected to the output 3 of the input comparator 1. This output 3 is connected to the input 6 of a first delay circuit 5. This circuit comprises an integrator comprising an NPN transistor T 2  whose base is connected to the input 6 and whose emitter is connected to the negative power-supply terminal, in the present case earth. 
     Between the collector and the base of a transistor T 2  a capacitor 8 is arranged, which may for example be constituted by the collector-base capacitance of the transistor itself. The collector of the transistor T 2  is connected to the positive power-supply terminal by a current source 7. This current source 7 carries a current βI 1 , i.e. a current which depends on the current gain factor β of a transistor. Such a current source can be realised, for example, by applying a constant current I 1  to the base of a transistor and using the collector current as the output current. The collector of the transistor T 2  is further connected to the emitter of a PNP transistor T 3  whose base is at a constant voltage V R  and whose collector is connected to the output 9 of the first delay circuit 5. The transistor T 3  forms the comparator of the first delay circuit 5. A second delay circuit 10 comprising transistors T 4  and T 5 , a capacitor 13 and a current source 13 is constructed in the same way as the first delay circuit 5. The input 11 of this second delay circuit is connected to the output 9 of the first delay circuit. The output 14 is connected to the base of an NPN transistor T 6  whose collector is connected to the positive power-supply terminal by a current source 20. The collector of the transistor T 6  is connected to the output 21 of the level detector. The transistor T 6  with the current source 20 amplifies and inverts the output current of the second delay circuit 10. 
     The operation of the arrangement will now be described in more detail with reference to FIG. 2. FIG. 2, line a shows the waveform of the input signal applied to the input 2 of the level detector. In the present example the input signal is the amplified and rectified signal current obtained by reading a compact disc. The input current I i  comprises a sequence of sinewave pulses of variable width. This input current I i  is compared with a reference current I ref  to generate a control signal if the maximum signal current I i  is a smaller than the reference current I ref , in such a way that if the reference level I ref  is not reached for a short time between two consecutive sinewave pulses this should not be detected. It is assumed that at the instant t=0 the current I i  is larger than the reference current I ref . The voltage on the emitter of the transistor T 1  is consequently higher than the voltage V R  on its base, so that this transistor conducts and the difference between the input current I i  and the reference current I ref  is applied to the input 6 of the first delay circuit 5. The transistor T 2  is then turned on and is almost fully saturated. As a result of this, capacitor 8 is then discharged almost completely and the voltage V A  on the collector of the transistor T 2 , whose waveform is shown in line b, is substantially zero volts. Consequently, the transistor T 3  is cut off, so that the entire current βI 1 , from the current source 7 flows through the transistor T 2 . Then no current is applied to the input 11 of the second delay circuit 10, so that the transistor T 4  does not conduct. The capacitor 13 is then charged, in which case the voltage V B  on the collector of the transistor T 4 , whose waveform is shown in line c, is equal to V B  =V R  +V BET5 , where V BET5  is the base-emitter voltage of the transistor T 5 . The current βI 2  from the current source 12 is then applied to the base of the transistor T 6  via the transistor T 5 , so that this transistor T 6  conducts and receives the current from the current source 20. The output 21 is then currentless, as is illustrated in FIG. 2d. 
     If at the instant t=t 1  the current I i  is smaller than the current I ref , the transistor T 1  and consequently the transistor T 2  are cut off. The capacitor 8 is then charged by the current βI 1  from the current source 7, so that the voltage V A  increases. As the instant t=t 2  the current I i  becomes larger than the current I ref . The transistor T 2  is turned on again via the transistor T 1 . The capacitor C 8  is then almost wholly discharged immediately, so that the voltage V A  becomes again substantially zero volts. The capacitor 8 has a comparatively low capacitance C. However, as a result of the Miller effect this capacitor, as seen from the collector of the transistor T 2 , has a capacitance which is (β+1) times as high. As a result of this, the voltage V A  on the collector of the transistor T 2  increases only slowly in the interval t 1  =t 2  and does not reach the level at which the transistor T 3  is turned on. In this way it is achieved that if the current I 1  briefly decreases below the reference level I ref  this has no effect on the output 21. In a similar way the interruptions between the instants t 3  -t 4  ; t 5  -t 6  and t 7  -t 8  have no effect on the output 21. At the instant t=t 9  current I i  again becomes smaller than the current I ref  and now remains below this level for a considerable time due to the absence of a signal, for example as a result of a dropout. The transistor T 2  is then turned off. The capacitor C 8  is now charged to such an extent that after a time τ 1  at the instant t=t 10  the voltage on the collector of the transistor T 2  becomes equal to V A  =V R  +V BET3 , where V BET3  is the base-emitter voltage of the transistor T 3 . The current βI 1  from the current source 7 then flows to the base of the transistor T 4  via the transistor T 3 , so that this transistor T 4  is turned on. The capacitor 13 is now almost wholly discharged immediately so that the voltage V B  becomes zero volts. As a result of this, the transistor T 5  is turned off, so that the transistor T 6  also becomes currentless. The current from the current source 20 now flows to the output 21 of the level detector. If the current I i  becomes smaller than the current I ref , this is only detected at the output of the level detector if the current I 1  has remained smaller than the current I ref  for at least a time interval τ  1 . 
     The delay time τ 1  is given by: ##EQU1## where (β+1) C is the total Miller-multiplied capacitance, V R  is the voltage across the capacitor 8 in the charged condition, and βI 1  is the current of the current source 7. The β-dependence of the current from the current source 7 ensures that the delay time τ 1  is independent of β and variations thereof. 
     The delay time τ 1  can be adjusted by means of the current βI 1 , the voltage V R  on the base of the transistor T 2  and the capacitance C of the capacitor C 8 . The delay time τ 1  should be adjusted in such a way that this time is longer than the maximum period of the input signal or, in the case of a rectified signal such as the signal shown in FIG. 2a, the maximum half-cycle of the signal. For the signal shown in FIG. 2a this maximum half-cycle is approximately 1 μs. The delay time τ 1  may then be selected to be for example τ 1  ≈10 μs. Such a time can be obtained, for example, by means of a collector-base capacitance of the transistor T 2  of C≈1 pF, a current I 1  ≈0.3 μA and a voltage V R  ≈3 V. 
     At the instant t=t 11  the current I i  again becomes larger than the current I ref . Via the T 1  the transistor T 2  is turned on, so that the capacitor C 8  is discharged and the voltage V A  becomes zero volts again. The transistor T 3  and the transistor T 4  are consequently cut off. As a result of this, the capacitor 13 is charged. If the reference level I ref  is not reached briefly as between the instants t 12  and t 13 , this has no influence on the charging of the capacitor 13. After a time τ 2  at the instant t 14  the voltage on the collector of the transistor T 4  becomes V B  =V R  +V BET5 . The current βI 2  from the current source 12 then turns on the transistor T 6  via the transistor T 5 , so that the output 21 becomes currentless again. The current I i  should therefore be above the reference level I ref  for a period τ 2  before this is detected on then output of the level detector. Brief interruptions of the signal during the time τ 2  are not regarded as excursions below the level. The delay time τ 2  may be selected to be equal or unequal to the delay time τ 1  the time τ 2  being adjustable in the same way as the time τ 1 . 
     As a result of the appearance of a negative spurious pulse or spike at the instant t=t 15  during a signal pulse the current I i  becomes smaller than the current I ref  very briefly. This spurious pulse is suppressed in the same way as brief signal interruptions between two consecutive signal pulses. 
     A drawback of the arrangement shown in FIG. 1 is that if a positive spurious pulse occurs between the instants t 10  and t 11 , this is detected as an increase above the reference level and results in a corresponding signal on the output 21. When the spurious pulse exceeds the reference level the capacitor 8 is discharged rapidly and at the same time charging of the capacitor 13 is started. If, briefly after this, the level decreases below the reference level, charging of the capacitor 8 begins. As the charging of the capacitor 13 has started earlier, the voltage V B  on the collector of the transistor T 4  reaches the level at which the transistor T 5  is turned on before the voltage V A  on the collector of the transistor T 2  has reached the level at which the transistor T 3  is turned on and discharges said capacitor 13. The spurious pulse is transferred to the output 21 of the detector because the transistor T 5  is turned on. 
     A level detector in accordance with the invention is shown in FIG. 3 in which identical parts bear the same reference numerals as in FIG. 1. In this embodiment the transistor T 5  in the delay circuit 10 is provided with a second collector. This second collector is connected to the base of a NPN transistor T 7 , whose emitter is connected to the negative power-supply terminal and whose collector is connected to the positive power-supply terminal by the current source 30 carrying a current βI 3  and to the collector of the transistor T 2  by a diode D 1 . The transistor T 7  operates as a switch by means of which the current source 30 can be connected in parallel with the current source 7. In the present embodiment the currents βI 1  and βI 2  from the current sources 7 and 12 are substantially equal to one another, so that in the case of equal capacitors 8 and 13 and equal voltages on the bases of the transistors T 3  and T 5  equal delays τ 1  and τ 2  are obtained, which is desirable for some purposes. In the present example the current βI 3  from the current source 30 is selected to be equal to βI 1 , but this need not be necessarily so. The operation of the arrangement will be explained with reference to FIG. 4. FIG. 4 line a again represents the input signal I i , lines b and c represent the voltage V A  and the voltage V B  on the collectors of the respective transistors T 2  and T 4 , and line d represents the output current I o . It is assumed that at the instant t=0 the input current I i  is larger than the reference current I ref . In this situation the voltage V B  on the collector of the transistor T 4  is high and the transistor T 5  conducts, so that the transistor T 7  is driven into conduction. This transistor T 7  consequently receives the full current βI 3  from the current source 30. The diode D 1  is then cut off and prevents a part of the current βI 1  from flowing from the current source to the transistor T 7 . 
     If the input current decreases below the reference level I ref  between two consecutive sinewave pulses, such as between the instants t=t 1  and t=t 2  and if negative spurious pulses appear during a sinewave pulse, this does not affect the output of the level detector, in the same way as in the circuit arrangement shown in FIG. 1. At the instant t=t 3  the current I i  again becomes smaller than the current I ref . After a time τ 1  at the instant t=t 4 , the voltage V A  reaches the level at which the transistor T 3  is turned on. As a result of this, the voltage V B  decreases and a current flows to the output 21. Since the transistor T 5  is cut off the transistor T 7  is also cut off, so that the current source 30 is connected in parallel with the current source 7. If at the instant t=t 5  as a result of a positive spurious pulse the current I i  becomes larger than the current I ref  the capacitor 8 is discharged rapidly and charging of the capacitor 30 begins. Very briefly after this at the instant t=t 7  the current I i  again becomes smaller than the current I ref , so that the charging of the capacitor 8 begins. Since the current source 30 is connected in parallel with the current source 7, the capacitor 8 is charged more rapidly than the capacitor 13, i.e. 2× as fast in the present embodiment. The voltage V A  on the collector of the transistor T 2  then reaches the level at which the transistor T 3  is turned on in a time τ i  which is smaller than the time τ 2  in which the voltage V B  on the collector of the transistor T 4  has reached the level at which the transistor T 5  is turned on. Since the transistor T 3  is turned on the capacitor 13 is discharged rapidly. As a result of this, the transistor T 5  remains in the non-conductive state, so that the positive spurious pulse is not transferred to the output. It is to be noted that in the arrangement of FIG. 1 positive spurious pulses are also suppressed if the delay time τ 2  is selected to be longer than the delay time τ 1 , which is easy to demonstrate. 
     The invention is not limited to the present embodiments. For example, the input comparator 1 may be constructed in different ways. Instead of a current the input signal may be a voltage which is compared with a reference voltage by means of a voltage comparator having a current output. In principle, the output transistor T 6  with the current source 20 may be dispensed with. However, alternatively, these elements may be replaced by another output circuit. The integrators and comparators of the delay circuits may also be constructed in a manner other than shown. In the arangement shown in FIG. 2 the current source 30 may also be arranged in parallel with the current source 7 in any other way. Finally, it is to be noted that the transistor may, of course, be replaced by transistors of opposite conductivity types.