Abstract:
A phase control circuit includes: a variable delay circuit for delaying a clock signal; a first flip-flop circuit having a clock input terminal to which the delayed clock signal is input and a data input terminal to which a data signal is input; a second flip-flop circuit having a clock input terminal to which the data signal is input and a data input terminal to which the delayed clock signal is input; and an integration circuit for controlling a delay amount of the variable delay circuit based on an output signal of the second flip-flop circuit.

Description:
[0001]     This application claims foreign priority based on Japanese Patent application No. 2006-026667, filed Feb. 3, 2006, the content of which is incorporated herein by reference in its entirety.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a phase control circuit, and more particularly, to a phase control circuit which enables adjustment of an optimal timing regardless of changes over time or changes in temperature.  
         [0004]     2. Description of the Related Art  
         [0005]     Related arts of the phase control circuit are JP-A-2-202115, JP-A-5-199088 and JP-A-2001-111393, for example.  
         [0006]      FIG. 6  is a block diagram showing an example of such a related-art phase control circuit. In  FIG. 6 , reference numeral  1  designates a delay circuit; and reference numeral  2  designates a flip-flop circuit. Reference numeral  100  designates a data signal; reference numeral  101  designates a clock signal; reference numeral  101   a  designates a clock signal delayed by the delay circuit  1 ; reference numeral  102  designates a noninverted output signal; and reference numeral  103  designates an inverted output signal.  
         [0007]     The data signal  100  is transmitted to a data input terminal of the flip-flop circuit  2 . The clock signal  101  is transmitted to an input terminal of the delay circuit  1 , and an output terminal of the delay circuit  1  is connected to a clock input terminal of the flip-flop circuit  2 . The noninverted output signal  102  is output from a noninverted output terminal of the flip-flop circuit  2 , and the inverted output signal  103  is output from an inverted output terminal of the flip-flop circuit  2 .  
         [0008]     Operation of the example of the related-art flip-flop circuit  2  shown in  FIG. 6  will now be described. The data signal  100  is an NRZ (Non Return to Zero) signal, and the flip-flop circuit  2  operates at a rising edge of a clock input signal.  
         [0009]     It is assumed that the delay circuit  1  is eliminated from  FIG. 6  and that the clock signal  101  is transmitted directly to the clock input terminal of the flip-flop circuit  2 . In this case, for instance, in the flip-flop circuit  2 , when a timing when the data signal  100  that is input to the data input terminal changes coincides with a timing of the rising edge of the clock signal  101  that is input to the clock input terminal, an output becomes uncertain.  
         [0010]     Specifically, when a setup time or a hold time of the data signal  100  is not satisfied with respect to the rising edge of the clock signal  101 , an output from the flip-flop circuit  2  becomes uncertain. For this reason, even when the data signal  100  is synchronized with the clock signal  101 , adjustment of the timings is required.  
         [0011]     As long as the delay circuit is used for either the data signal  100  or the clock signal  101 , timings can be adjusted. However, since the band of the data signal is broader than the band of a clock signal in most cases, a delay circuit is usually used for the clock signal.  FIG. 6  shows a case where the delay circuit  1  is used for the clock signal  101 .  
         [0012]     As a result, by providing the delay circuit  1  for the clock signal  101  that is input to the clock input terminal of the flip-flop circuit  2 , the timing of a change in the data signal  100  that is input to the data input terminal of the flip-flop circuit  2  and the timing of the rising edge of the clock signal  101   a  that is input to the clock input terminal are optimized, and hence a stable output signal can be output.  
         [0013]      FIG. 7  is a block diagram showing another example of such a related-art phase control circuit. In  FIG. 7 , reference numeral  3  designates a phase detector; reference numeral  4  designates a loop filter; reference numeral  5  designates an oscillator; reference numeral  104  designates a reference signal; and reference numeral  105  designates an output signal.  
         [0014]     A reference signal is input to one input terminal of the phase detector  3 , and an output terminal of the phase detector  3  is connected to an input terminal of the loop filter  4 . An output terminal of the loop filter  4  is connected to an input terminal of the oscillator  5 . The output signal  105  is output from an output terminal of the oscillator  5 , and the output terminal is connected to the other input terminal of the phase detector  3 .  
         [0015]     Operation of the related-art phase control circuit shown in  FIG. 7  will now be described. The circuit shown in  FIG. 7  is generally called a PLL (Phase-Locked Loop) and outputs, as the output signal  105 , a signal having a frequency accurately synchronized with the reference signal  104 .  
         [0016]     Specifically, the phase detector  3  detects a phase difference between the reference signal  104  that is input from the external and the output signal  105  which is the output of the oscillator  5 . The loop filter  4  converts a result of detection into a control voltage for the oscillator  5  to thus perform automatic control so that the phase difference becomes constant.  
         [0017]     Consequently, the phase detector  3  detects a phase difference between the reference signal  104  and the output signal  105  of the oscillator  5 , and the loop filter  4  converts a result of detection into a control voltage for the oscillator  5  to thus perform automatic control so that the phase difference becomes constant. As a result, a signal whose frequency is accurately synchronized with the reference signal  104  can be output as the output signal  105 .  
         [0018]     However, in the related-art example shown in  FIG. 6 , even if the timing of the data signal  100  and the timing of the clock signal  101  can be adjusted under conditions of a surrounding environment at a specific point in time such as at a time of manufacturing and shipment, there arises a problem that the timing becomes gradually unadjusted, because of a difference between a path of the data signal  100  and a path of the clock signal  101  or characteristics of the delay circuit  1  itself, in accordance with a change in service temperature environment or changes over time.  
         [0019]     In the related-art example shown in  FIG. 7 , control can be performed in such a way that the phase difference between the reference signal  104  and the output signal  105  from the oscillator  5  becomes constant. However, there has been no circuit of a simple configuration that can match the timing of the data signal with the timing of the clock signal in the flip-flop circuit by utilizing this PLL technique.  
       SUMMARY OF THE INVENTION  
       [0020]     The present invention has been made in view of the above circumstances, and provides a phase control circuit which enables adjustment of optimal timings at all times, regardless to changes over time or temperature changes.  
         [0021]     In some implementations, a phase control circuit of the invention, comprising:  
         [0022]     a variable delay circuit for delaying a clock signal;  
         [0023]     a first flip-flop circuit having a clock input terminal to which the delayed clock signal is input and a data input terminal to which a data signal is input;  
         [0024]     a second flip-flop circuit having a clock input terminal to which the data signal is input and a data input terminal to which the delayed clock signal is input; and  
         [0025]     an integration circuit for controlling a delay amount of the variable delay circuit based on an output signal of the second flip-flop circuit.  
         [0026]     Accordingly, the adjustment to obtain the optimal timing is available at all times regardless to changes over time or temperature changes.  
         [0027]     In the phase control circuit, the variable delay circuit changes the delay amount in accordance with a magnitude of the output signal of the integration circuit. Accordingly, the adjustment to obtain the optimal timing is available at all times regardless to changes over time or temperature changes.  
         [0028]     In the phase control circuit, the integration circuit includes:  
         [0029]     a first resistor of which one end is connected to a noninverted output terminal of the second flip-flop circuit;  
         [0030]     a first capacitor of which one end is connected to the other end of the first resistor;  
         [0031]     a second resistor of which one end is connected to an inverted output terminal of the second flip-flop circuit;  
         [0032]     a second capacitor of which one end is connected to the other end of the second resistor and of which other end is connected to ground; and  
         [0033]     an amplifier having an inverted input terminal connected to the other end of the first resistor and the one end of the first capacitor, a noninverted input terminal connected to the other end of the second resistor and the one end of the second capacitor, and an output terminal connected to the other end of the first capacitor and a control terminal of the variable delay circuit.  
         [0034]     Accordingly, the adjustment to obtain the optimal timing is available at all times regardless to changes over time or temperature changes.  
         [0035]     According to the phase control circuit, the integration circuit integrates outputs from the second flip-flop circuit having the clock input terminal to which the data signal is input and the data input terminal to which the clock signal is input. Then, the variable delay circuit is controlled based on the output resulting from integration. Thus, the timing of the clock signal is optimized. Accordingly, realization of a phase control circuit capable of adjustment to obtain the optimum timing at all times regardless to changes over time or temperature changes becomes feasible.  
         [0036]     In some implementations, a phase control circuit of the invention, comprising:  
         [0037]     a variable delay circuit for delaying a clock signal;  
         [0038]     a first flip-flop circuit having a clock input terminal to which the delayed clock signal is input and a data input terminal to which a data signal is input;  
         [0039]     a second flip-flop circuit having a clock input terminal to which the data signal is input and a data input terminal to which the delayed clock signal is input; and  
         [0040]     an integration circuit for controlling a delay amount of the variable delay circuit by a mechanical driving force based on an output signal of the second flip-flop circuit.  
         [0041]     Accordingly, the adjustment to obtain the optimal timing is available at all times regardless to changes over time or temperature changes.  
         [0042]     In the phase control circuit, the variable delay circuit changes the delay amount in accordance with the mechanical driving force from the integration circuit. Accordingly, the adjustment to obtain the optimal timing is available at all times regardless to changes over time or temperature changes.  
         [0043]     In the phase control circuit, the integration circuit includes:  
         [0044]     a motor; and  
         [0045]     a motor driving circuit for driving the motor by controlling a rotating direction of the motor in accordance with a logical level of the output signal of the second flip-flop circuit.  
         [0046]     Accordingly, the adjustment to obtain the optimal timing is available at all times regardless to changes over time or temperature changes.  
         [0047]     According to the phase control circuit, the integration circuit converts, into the mechanical driving force, the outputs from the second flip-flop circuit having the clock input terminal to which the data signal is input and the data input terminal to which the clock signal is input. Then, the variable delay circuit is controlled based on the driving force, whereby the timing of the clock signal is optimized. Accordingly, realization of a phase control circuit capable of adjustment to obtain the optimal timing at all times regardless to changes over time or temperature changes becomes feasible. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0048]      FIG. 1  is a configuration block diagram showing an embodiment of a phase control circuit of the present invention;  
         [0049]      FIG. 2  is a timing chart showing an operation timing of a flip-flop circuit;  
         [0050]      FIG. 3  is a timing chart showing operation timings of flip-flop circuits;  
         [0051]      FIG. 4  is a timing chart showing operation timings of flip-flop circuits;  
         [0052]      FIG. 5  is a configuration block diagram showing another embodiment of a phase control circuit of the present invention;  
         [0053]      FIG. 6  is a configuration block diagram showing an example of a related-art phase control circuit; and  
         [0054]      FIG. 7  is a configuration block diagram showing another example of the related-art phase control circuit. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0055]     The present invention will be described in detail herein below by reference to the drawings.  FIG. 1  is a configuration block diagram showing an embodiment of a phase control circuit according to the present invention. In  FIG. 1 , reference numerals  2 ,  100 ,  101 ,  101   a ,  102 , and  103  are the same as those shown in  FIG. 6 . Reference numeral  6  designates a variable delay circuit; reference numeral  7  designates a flip-flop circuit; reference numerals  8  and  9  designate resistors; reference numerals  10  and  11  designate capacitors; and reference numeral  12  designates an amplifier.  
         [0056]     An integration circuit  50  includes the resistors  8  and  9 , the capacitors  10  and  11 , and the amplifier  12 .  
         [0057]     The data signal  100  is transmitted to a data input terminal of the flip-flop circuit  2  and a clock input terminal of the flip-flop circuit  7 . The clock signal  101  is transmitted to an input terminal of the variable delay circuit  6 , and an output terminal of the variable-delay circuit  6  is connected to a clock input terminal of the flip-flop circuit  2  and a data input terminal of the flip-flop circuit  7 .  
         [0058]     A noninverted output terminal of the flip-flop circuit  7  is connected to one end of the resistor  8 , and the other end of the resistor  8  is connected to one end of the capacitor  10  and an inverted input terminal of the amplifier  12 . An inverted output terminal of the flip-flop circuit  7  is connected to one end of the resistor  9 , and the other end of the resistor  9  is connected to one end of the capacitor  11  and a noninverted input terminal of the amplifier  12 .  
         [0059]     The other end of the capacitor  11  is connected to ground, and an output terminal of the amplifier  12  is connected to a control terminal of the variable delay circuit  6  and the other end of the capacitor  10 . The noninverted output signal  102  is output from the noninverted output terminal of the flip-flop circuit  2 , and the inverted output signal  103  is output from an inverted output terminal of the flip-flop circuit  2 .  
         [0060]     Operation of the phase control circuit of the present embodiment shown in  FIG. 1  will be described by reference to  FIGS. 2, 3 , and  4 .  FIG. 2  is a timing chart showing an operation timing of the flip-flop circuit  2 , and  FIGS. 3 and 4  are timing charts showing the operation timing of the flip-flop circuit  2  and that of the flip-flop circuit  7 .  
         [0061]      FIG. 2  shows a timing chart achieved when the timing of data input and the timing of a clock signal input to the flip-flop circuit  2  are optimal. Specifically, the timing of a rising edge of the clock signal  101   a  does not coincide with the timing of change in the data signal  100  but the timing comes when the data signal is stable.  
         [0062]      FIG. 3  shows a timing chart achieved when the timing of data input to the flip-flop circuit  2  is ahead of the optimal timing. As shown in  FIG. 3 , the noninverted output signal of the flip-flop circuit  7  becomes constantly at a low level except an initial unstable period, whereas the inverted output signal becomes constantly at a high level except the initial unstable period.  
         [0063]     When the noninverted output signal and the inverted output signal from the flip-flop circuit  7  are input to the integration circuit  50 , the output signal from the integration circuit  50  gradually becomes large.  
         [0064]     It is assumed that as a characteristic of the variable delay circuit  6 , the delay amount changes in accordance with the magnitude of a control signal that is input to a control terminal of the variable delay circuit. Specifically, when the control signal is large, the delay amount becomes larger. In contrast, when the control signal is small, the delay amount becomes smaller.  
         [0065]     When the output signal from the integration circuit  50  gradually becomes larger, the delay amount of the variable delay circuit  6  gradually becomes larger correspondingly. Then, the clock signal  101   a  having been input ahead of the optimal timing approaches the optimal timing.  
         [0066]      FIG. 4  shows a timing chart achieved when the timing of data input to the flip-flop circuit  2  is behind the optimal timing. As shown in  FIG. 4 , the noninverted output signal from the flip-flop circuit  7  becomes constantly at a high level except the initial unstable period, and the inverted output signal becomes constantly at a low level except the initial unstable period.  
         [0067]     When the noninverted output signal and the inverted output signal from the flip-flop circuit  7  are input to the integration circuit  50 , the signal output from the integration circuit  50  gradually becomes small.  
         [0068]     When the signal output from the integration circuit  50  gradually becomes smaller, the delay amount of the variable delay circuit  6  gradually becomes smaller correspondingly. Then, the clock signal  101   a  having been input behind the optimal timing approaches the optimal timing.  
         [0069]     Consequently, the integration circuit  50  integrates outputs from the flip-flop circuit  7  having the clock input terminal to which the data signal  100  is input and the data input terminal to which the clock signal  101   a  is input. Then, the variable delay circuit  6  is controlled based on the integrated output, whereby the timing of the clock signal  101  is optimized. Accordingly, the adjustment to obtain the optimal timing is available at all times regardless to changes over time or temperature changes.  
         [0070]     In the embodiment shown in  FIG. 1 , the integration circuit  50  is provided with a differential input configuration. However, providing the integration circuit with a differential input configuration is not always needed, and the integration circuit may also be provided with a single input configuration.  
         [0071]     In the embodiment shown in  FIG. 1 , the integration circuit  50  is formed with electrical components. However, forming the integration circuit with the electrical components is not always necessary, and integration may also be performed by use of a mechanical component such as a motor.  
         [0072]     Operation of the phase control circuit performed in this case will be described by reference to  FIG. 5 .  FIG. 5  is a configuration block diagram showing another embodiment of the phase control circuit of the present invention. In  FIG. 5 , reference numerals  2 ,  7 ,  100 ,  101 ,  101   a ,  102 , and  103  are the same as those shown in  FIG. 1 . Reference numeral  6   a  designates a variable delay circuit; reference numeral  13  designates a motor driving circuit; and reference numeral  14  designates a motor. An integration circuit  51  includes the motor driving circuit  13  and the motor  14 .  
         [0073]     A noninverted output terminal of the flip-flop circuit  7  is connected to one input terminal of the motor driving circuit  13 , and an inverted output terminal of the flip-flop circuit  7  is connected to the other input terminal of the motor driving circuit  13 . One output terminal of the motor driving circuit  13  is connected to one input terminal of the motor  14 , and the other output terminal of the motor driving circuit  13  is connected to the other input terminal of the motor  14 .  
         [0074]     A rotary portion of the motor  14  is connected to a delay control rotary switch of the variable delay circuit  6   a . The other connections are the same as those shown in  FIG. 1 , and hence their explanations are omitted.  
         [0075]     The basic operation of the phase control circuit is essentially identical with that of the phase control circuit according to the embodiment shown in  FIG. 1 . A difference between the basic operations of the phase control circuits lies in that the integration circuit  51  is formed with the motor driving circuit  13  and the motor  14 , and that the variable delay circuit  6   a  is controlled by mechanical driving force.  
         [0076]     As in the case of the embodiment shown in  FIG. 1 , when the timing of data input to the flip-flop circuit  2  is ahead of the optimal timing, the noninverted output signal of the flip-flop circuit  7  remains at a low level at all times except the initial unstable period, whereas the inverted output signal remains at a high level at all times except the initial unstable period.  
         [0077]     During a period in which the noninverted output of the flip-flop circuit  7  remains at a low level and the inverted output of the flip-flop circuit remains at a high level, the motor driving circuit  13  rotates the motor  14  at a given speed in one direction. As a result, the delay control rotary switch of the variable delay circuit  6   a  is rotated, and the delay amount gradually becomes large. The clock signal  101   a  having been input ahead of the optimal timing approaches the optimal timing.  
         [0078]     Likewise, when the timing of the data input to the flip-flop circuit  2  is behind the optimal timing, the noninverted output signal of the flip-flop circuit  7  remains at a high level at all times except the initial unstable period, whereas the inverted output signal of the same remains at a low level at all times except the initial unstable period.  
         [0079]     During a period in which the noninverted output of the flip-flop circuit  7  is at a high level and the inverted output of the same is at a low level, the motor driving circuit  13  rotates the motor  14  at a given speed in reverse direction. As a result, the delay control rotary switch of the variable delay circuit  6   a  is rotated, and the delay amount gradually becomes small. The clock signal  101   a  having been input behind the optimal timing approaches the optimal timing.  
         [0080]     Consequently, the data signal  100  is input to the clock input terminal, the integration circuit  51  converts, into mechanical rotation, outputs from the flip-flop circuit  7  having the data input terminal to which the clock signal  101   a  is input. Then, the variable delay circuit  6   a  is controlled based on the mechanical rotation. Thus, the timing of the clock signal  101  is optimized. Accordingly, the adjustment to obtain the optimal timing is available at all times regardless to changes over time or temperature changes.  
         [0081]     In the embodiment shown in  FIG. 5 , the variable delay circuit  6   a  is controlled by the rotation generated by the integration circuit  51 . However, rotation is not always needed, and the variable delay circuit  6   a  may be controlled by any mechanical driving force.  
         [0082]     For instance, the rotation generated by the integration circuit  51  may be converted into horizontal sliding motion, and the delay amount of the variable delay circuit  6   a  may also be switched by a slide switch.  
         [0083]     It will be apparent to those skilled in the art that various modifications and variations can be made to the described preferred embodiments of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover all modifications and variations of this invention consistent with the scope of the appended claims and their equivalents.