Abstract:
According to one embodiment of the invention, an apparatus comprises a high speed memory unit, a memory controller and an external bus interface (EBIF) unit coupled to the memory controller. The EBIF unit, based on a memory request issued by a host device to read a block of data from an external memory device, (i) initiates a burst or page mode read cycle independent of whether the memory request is associated with consecutive memory accesses to the external memory device, (ii) stores the block of data read in the high speed memory unit in response to the burse or page mode read cycle, and (iii) retrieves requested data from the high speed memory unit in response to a subsequent, non-consecutive memory request issued by the host device for data already stored within the high speed memory unit.

Description:
FIELD 
   An embodiment of the invention relates to the field of processor, memory, and data transfer technologies including memory operations and memory interface, and more specifically, relates to a method, apparatus, and system for improving memory access speed in computer systems. 
   BACKGROUND 
   In recent years, computer systems&#39; performance and capabilities have continued to advance rapidly in light of various technological advances and improvements with respect to processor architecture and performance. In particular, central processing unit (CPU) speed has continued to improve significantly in the past several years. However, memory access speed has not improved as much compared with the CPU speed. Consequently, CPU operations and performance can be limited by memory access speed. To improve this situation, some CPUs employ high access speed memory (e.g., cache memory) to store some part of main memory (also called system memory) in order to improve memory access efficiency. Typically a CPU may need a cache memory having a size larger than 4 kbytes (KB) with high access speed to be located near the CPU. Such a cache memory is typically expensive and tends to require complicated design cache or memory controller circuit. Consequently, the use of such cache memory may negatively impact the CPU design itself and the overall cost of the CPU. Accordingly, there exists a need to improve CPU memory access efficiency without large size of high speed memory (cache) or complicated memory controller design. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention may best be understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention. In the drawings: 
       FIG. 1  shows a block diagram of a system configuration with external memory; 
       FIG. 2  illustrates an exemplary timing diagram of a memory data read (e.g., with respect to a Flash ROM); 
       FIG. 3  illustrates an exemplary timing diagram of a memory data read in a burst or page mode (e.g., with respect to a Flash ROM having a burst or page access mode); 
       FIG. 4  shows a block diagram of a system according to one embodiment of the invention; 
       FIG. 5  illustrates a block diagram of an External Bus Interface (EBIF) circuit in accordance with one embodiment of the invention; 
       FIG. 6  shows an example of bus read access timing of CPU for a typical CPU system; 
       FIG. 7  shows an example of improved bus read access timing of CPU according to one embodiment of the invention; and 
       FIG. 8  shows a flow diagram of a method according to one embodiment of the invention. 
   

   DETAILED DESCRIPTION 
   In the following detailed description numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. 
   As mentioned above, in order to improve memory access efficiency, some CPUs have employed high access speed memory (e.g., cache memory) which is located near the CPU to store some part of main memory (also called system memory). However, such a cache memory is typically expensive and requires complicated design cache or memory controller circuit. Thus, the use of such cache memory may negatively impact the CPU design itself and the overall cost of the CPU. 
   According to one embodiment of the invention, the CPU memory access efficiency can be improved without using large size and high cost cache memory and/or complicated memory controller circuit. In one embodiment, the CPU memory access efficiency is achieved by implementing a high speed and small-size temporary memory unit to store data received from an external memory device which has slower memory access speed compared to the temporary memory unit. The high speed temporary memory unit is accessed via a memory controller which is coupled to an external bus interface (EBIF) unit. The EBIF is configured to control and facilitate memory accesses between a host device (e.g., a CPU) and the high speed temporary memory unit to reduce memory access time (also called memory access latency) for the host device. The structure and operations of these components are described in greater detail below. 
     FIG. 1  shows a block diagram of a computer system configuration  100  which includes a CPU  110 , one or peripheral devices  120 , external bus interface (EBIF)  130 , one or more Flash ROM devices  140  and system memory (e.g., SRAMs)  150 . The CPU  110  and other modules such as peripheral devices  120  may be stand-alone units or be parts of integrated circuit (IC) chip. As shown in  FIG. 1 , the CPU  110 , the peripheral devices  120 , and the EBIF are typically connected via an internal bus  160 . The memory devices such as the Flash ROM  140  and the SRAM  150  are coupled to the EBIF  130  via an external bus  170 . In general, the CPU  110  accesses the memory devices (e.g., Flash ROM  140  and SRAM  150 ) via the EBIF  130 . For example, a program may be stored on the Flash ROM  140  and the CPU  110  can read the program from the Flash ROM  140  and execute it. As mentioned above, the speed of a memory device such as the Flash ROM  140  is much slower compared to that of the CPU  110 . As a result, the CPU&#39;s performance can be significantly limited by the slow speed of the Flash ROM  140  when it needs data from the Flash ROM  140  to perform its corresponding functions. 
     FIG. 2  illustrates an exemplary timing diagram of a memory data read with respect to a Flash ROM (e.g., Flash ROM  140 ). In this example, the CPU clock rate is three times faster than the Flash ROM access speed. Therefore the CPU needs to wait two more cycles to get data from the Flash ROM because the CPU needs to wait for valid data to come. As a result, a total of three cycles is needed for the CPU to access the Flash memory in this example. If the CPU needs two consecutive Flash ROM accesses, it would take six CPU clock cycles to get the data needed. As shown in  FIG. 2 , the output enable (OE) signal is generated by the EBIF and provided to the external memory (e.g., Flash ROM  140 ). The OE signal allows the external memory device such as the Flash ROM to output its data to an external data bus (e.g., external data bus  170  in  FIG. 1 ). 
     FIG. 3  illustrates an exemplary timing diagram of a memory data read in a burst or page mode (e.g., from a Flash ROM having a burst or page access mode). When a memory device such as the Flash ROM  140  has a burst or page mode access, the number of memory access cycles for consecutive data read can be reduced. Certain types of Flash ROM devices are configured to have the burst or page mode access capability. The burst or page mode has the same access speed as the conventional Flash ROM device for the first memory access. However, if the CPU needs consecutive memory accesses, the speed of subsequent accesses are much faster compared to the first access. In the example illustrated in  FIG. 3 , it takes 3 CPU cycles for the first memory access but it only takes 1 cycle for the second memory access in the burst or page mode. As a result, the burst or page access mode is very efficient for consecutive memory accesses. However, if the CPU does not access the Flash ROM consecutively, the CPU cannot utilize these modes. As described herein, in one embodiment, the present invention provides a mechanism and a method which enable a host device such as a CPU to effectively utilize the burst or page access mode. 
     FIG. 4  shows a block diagram of a system  400  according to one embodiment of the invention. As shown in  FIG. 4 , the system  400  includes a CPU  410 , one or more peripheral devices  420 , external bus interface (EBIF) unit  430  that are coupled to each other via an internal bus  460 . The system  400  further includes one or more Flash ROM devices  440  that are configured to have page or burst access mode and one or more SRAM devices  450 . The Flash ROM  440  and SRAM  450  are coupled to the EBIF  430  via external bus  470 . As shown in  FIG. 4 , the system  400  further includes a high speed and small-size temporary memory unit  480  and memory controller  490  which is coupled to the EBIF  430 . In one embodiment, the temporary memory unit  480  is a high speed memory which can be accessed by a host device such as CPU  410  with no wait cycles or less wait cycles compared with an external memory device such as the Flash ROM  440 . In one embodiment, the size of the temporary memory unit  480  is configured to correspond to the number of consecutive data read size in page or burst access mode (e.g., 4 words to 16 words). The EBIF  430  is described in greater detail below. 
     FIG. 5  illustrates a block diagram of an External Bus Interface (EBIF) circuit (e.g., EBIF  440  shown in  FIG. 4 ) in accordance with one embodiment of the invention. As shown in  FIG. 5 , the EBIF  440  includes a data controller  510 , an address controller  520 , and an external bus access timing generator  530 . The data controller  510  is coupled to the Flash ROM  440  via external data bus (bi-directional)  572  and the address controller  520  is coupled to the Flash ROM  440  via external address bus  574 . External data bus  572  and external address bus  574  are shown together as external bus  470  in  FIG. 4 . Timing generator  530  is coupled to the memory controller  490  and data selector  540 . In one embodiment, the timing generator  530  is configured to manage and generate external bus access timing signals. Data controller  510  and address controller  520  convert the interface access timing signals between the internal bus  460  and external bus  470 . As shown in  FIG. 5 , the internal bus  460  includes internal write data bus  562 , internal read data bus  564 , and internal address bus  566 . Data selector  540  is coupled to select data from either external data bus  572  via data controller  510  or from temporary memory unit  480  and provide the selected data to internal read data bus  564 . The internal write data bus  562  is coupled to data controller  510 . Internal address bus  566  is coupled to timing generator  530  and address controller  520 . 
     FIG. 6  shows an example of bus read access timing of CPU for a typical CPU system (e.g., system  100 ) without implementing the teachings of the present invention. In this example, as shown in  FIG. 6 , address range m+i corresponds to the IC internal peripheral address and n+i corresponds external device address (e.g., external memory device address). In this example, it is assumed that the CPU can access internal peripherals without wait cycles. In this example, it can be seen that the CPU accesses external memory and internal peripherals alternately, as illustrated in  FIG. 6 . Accordingly, the CPU access address is n, m, n+1, m+1, n+2, m+2, and so on. To access addresses n to m+2 in this example, it would take 12 CPU cycles to complete the access operations, assuming 1 cycle for internal peripheral access and 3 cycles for external memory access (3×3=9 cycles for external memory accesses and 1×3=3 cycles for internal peripheral accesses). 
     FIG. 7  shows an example of improved bus read access timing of CPU according to one embodiment of the invention as described above with respect to  FIGS. 4 and 5 . In this example, as illustrated in  FIG. 7 , the CPU (e.g., CPU  410 ) also accesses external memory and internal peripherals alternately. However, since the external Flash memory access speed is improved by the present invention, it takes only 8 CPU cycles to access addresses n to m+2. This is because the data from external memory addresses n, n+1, n+2, and n+3 are read consecutively in one Flash ROM data read cycle by page mode (without data wait cycles incurred with respect to n+1, n+2, and n+3 memory addresses). The data read from external memory addresses n+1, n+2, and n+3 are then stored in the high speed temporary memory unit and sent to the CPU when they are needed. Accordingly, for example, when the CPU issues a memory read request to access data from external memory address n+2, the requested data will be retrieved from the high speed temporary memory unit instead of being fetched from the external Flash ROM device. The external bus access timing generator as shown in  FIG. 5  controls the data path between the CPU and the memory units (e.g., the temporary memory unit and the external Flash ROM) and the timing of the EBIF unit depends on the access addresses generated by the CPU. In this embodiment, when the CPU issues a memory read request for external memory address n, the EBIF initiates a Flash ROM data read cycle by page mode which reads data consecutively from external memory addresses n, n+1, n+2, and n+3. The requested data from address n is sent to the CPU at this point. Data from external memory addresses n+1, n+2, and n+3 are stored in the high speed temporary memory unit since they are not needed by the CPU at this point. Subsequently, when the CPU issues memory read requests for external memory addresses n+1, n+2, and n+3, the requested data are retrieved from the high speed temporary memory unit for the CPU instead of being fetched from the external Flash ROM. As such, the memory access efficiency is significantly improved because the data stored in the high speed temporary memory unit can be accessed much faster by the CPU compared to the Flash ROM access time. In this configuration according to one embodiment of the invention, the fast access speed in burst or page mode can be efficiently and effectively utilized even when the CPU does not access the Flash ROM consecutively. 
     FIG. 8  shows a flow diagram of a method according to one embodiment of the invention. At block  810 , a first memory request is received from a host device (e.g., CPU  410 ) to fetch data from an nth address in an external memory device (e.g., Flash ROM  440 ). At block  820 , a memory block request (e.g., memory read in page or burst mode) is generated to fetch a block of consecutive data from the external memory device starting at the nth address (nth, n+1th, n+2th, n+3th, etc.). At block  830 , the block of consecutive data fetched from the external memory device is stored in a high speed memory unit which has faster access time compared to that of the external memory device. At block  840 , in response to a subsequent memory request from the host device to fetch data whose address matches the address of the data stored in the high speed memory unit, the requested data is retrieved from the high speed memory unit for the host device instead of being fetched from the external memory device. 
   While the invention has been described in terms of several embodiments, those of ordinary skill in the art will recognize that the invention is not limited to the embodiments described herein. It is evident that numerous alternatives, modifications, variations and uses will be apparent to those of ordinary skill in the art in light of the foregoing description.