Abstract:
A stable and flexible synchronization system and method are disclosed. The method includes selecting to receive an external clock signal, detecting a difference between an internal clock signal and the selected external clock signal and generating a control signal representing the difference; determining if the control signal has a first value that is within a predetermined range; calculating a second value representing an absolute value of a difference between a current value of the control signal and a previous value of the control signal; determining if the value is less than a third value; resetting the output signal upon receipt of an edge of said selected external clock signal; determining if a timing difference between the output signal and the selected clock signal is substantially zero; and issuing a signal indicative of synchronization.

Description:
The present invention is a continuation-in-part application of U.S. patent application Ser. No. 08/992,641, filed Dec. 17, 1997 issued as U.S. Pat. No. 6,104,222, which is assigned to the assignee of the present invention. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates in general to phase locked loop circuits and more particularly, to a method and apparatus for providing a flexible phase locked loop system that is compatible with a variety of standards. 
     2. Description of the Related Art 
     In the filming industry, it is desirable to synchronize each film frame or video frame to the corresponding audio samples, so that the appropriate speech, music and/or sound effects may be matched with the corresponding action during playback. 
     To accomplish this, the frames are counted and provided to a master circuit which runs the projector and the audio systems at the same speed. As shown in FIG. 1A, the film is typically run at 24 frames per second. The audio signals are typically sampled at 48 kHz. For this example, each of the frames have 2,000 corresponding audio samples. The master circuit typically employs a phase locked loop (PLL) system  10  (FIG. 1B) comprising a phase-frequency detector (PFD)  12 , a voltage-controlled oscillator (VCO)  14 , a divide-by-A circuit  16  and a divide-by-B circuit  18 . The frequency divider circuits  16  and  18  are used in the feedback loops of the PLL so that frequencies higher than that of the input clock signal can be generated. The output of the VCO  14  is provided as a first output signal for internal operations of the master circuit. The output of the VCO  14  is also provided to the divide-by-A circuit  16 , which subsequently generates a second output signal that is typically used to synchronize the video information with audio information (which typically operates at 48 kHz). The value of A is determined by the ratio of the master clock frequency to the audio frequency to be synchronized to. For example, if the audio frequency is 48 kHz, and the master clock frequency is 12.288 MHz, A=256. 
     The second output signal is also provided to the divide-by-B circuit  18 . The divide-by-B circuit  18  generates a feedback signal that is provided to the PFD  12 . The value of B is determined by a ratio of the audio frequency to be synchronized to and the frame clock frequency. For example, if the audio frequency is 48 kHz and the frame clock frequency is 24 Hz, the value of B will be 2,000. The PFD  12  receives input signals from a frame clock and compares the phase/frequency of the input signals with the phase/frequency of the feedback signal. The PFD  12  produces a control voltage which is a function of the difference (error) between the input signal and the feedback signal. The PFD  12  presents the control voltage to a loop filter  14 , which filters the output voltage of the PFD  12  and subsequently provides the filtered output voltage to the VCO  16  to adjust the frequency of the output signal. After some time as determined by the frequency response of the loop, the PLL system  10  locks onto the input clock signal and presents an output having a stable frequency and phase. 
     However, such an approach requires a substantially lengthy period for the PLL system  10  to lock onto the input clock signal, because the input clock signal operates at a low frequency, typically 24 Hz. In addition, the PLL system  10  is susceptible to noise conditions such as power supply fluctuations, etc. To avoid the slow response time and instability of such a PLL system, a higher input clock frequency is used. A typical frequency is the horizontal frequency as established by the National Television Systems Committee (NTSC). Although such an approach overcomes the slow response time and instability problems of the previous technique, it cannot provide the flexibility of accommodating a variety of video formats like the Phase Alternating Line (PAL), Sequential Couleur avec Memoire (SECAM) and NTSC. 
     Accordingly, there is a need in the technology for providing a stable PLL system that provides a fast response time, while providing flexibility and compatibility with a variety of video standards. 
     BRIEF SUMMARY OF THE INVENTION 
     A stable and flexible synchronization system and method are disclosed. The method comprises (a) selecting to receive one of a plurality of external clock signals; (b) detecting a difference between an internal clock signal and the selected one of a plurality of external clock signal and generating a first control signal representing the difference; (c) determining if the first control signal has a first value that is within a predetermined range; (d) if so, calculating a second value representing an absolute value of a difference between a current value of the first control signal and a previous value of the first control signal, otherwise repeating (c); (e) determining if the second value is less than a third value; (f) if so, resetting the output signal upon receipt of an edge of said selected one of the plurality of external clock signals, otherwise repeating (c); (g) determining if a timing difference between the output signal and the selected one of the plurality of external clock signals is substantially zero; (h) if so, issuing a signal indicative of synchronization, otherwise repeating (c). 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A illustrates a conventional technique for synchronizing video and audio information. 
     FIG. 1B illustrates a conventional phase locked loop circuit. 
     FIG. 2 illustrates one embodiment of the phase locked loop system  100  in accordance with the teachings of the present invention. 
     FIG. 3 is a chart illustrating a variety of frequency values that VCO  130  of FIG. 2 may be configured to provide, so as to enable the PLL system  100  to accommodate a corresponding variety of input signals. 
     FIGS. 4A and 4B are charts illustrating a variety of values P, D, N and M for the respective divide counters  110 ,  140 ,  156  and  160  of FIG. 2, corresponding to a variety of video formats. 
     FIG. 5 is a chart illustrating a variety of values of the divide counters P, D, N and M for the respective divide counters  110 ,  140 , 156  and  160  of FIG. 2, when the phase lock loop system  100  is configured to adjust the corresponding frequencies provided by a variety of systems. 
     FIG. 6A illustrates one example of unsynchronized input and output sync signals. 
     FIG. 6B illustrates one example of synchronized input and output sync signals. 
     FIG. 6C illustrates one example of synchronized input and output sync signals in which a video vertical sync signal is used as the sync source. 
     FIG. 7 illustrates one embodiment of the synchronization system  200  provided in accordance with the teachings of the present invention. 
     FIG. 8 is a graph illustrating the difference between the input and output sync signals. 
     FIG. 9 illustrates one embodiment of the software code used to implement the synchronization process of the invention. 
     FIGS. 10A and 10B are flow charts illustrating one embodiment of the synchronization process of the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention is an apparatus and method for providing a stable phase locked loop system that provides a fast response time, while providing compatibility with a variety of video standards. 
     FIG. 2 illustrates one embodiment of the phase locked loop system  100  in accordance with the teachings of the present invention. In the following discussion, the phase locked loop (PLL) system  100  is described with reference to a horizontal synchronization (HSYNC) signal that is derived from a video signal. Although the PLL system  100  of the present invention may be particularly suited for synchronizing video information to audio information, it is apparent to one of ordinary skill in the technology that the PLL system  100  may be readily applied to any other system in which frequency or phase synchronization is required. 
     The phase locked loop (PLL) system  100  comprises a divide-by-P circuit  110 , a phase frequency detector (PFD)  120 , a loop filter  125 , a voltage-controlled oscillator (VCO)  130 , a divide-by-D circuit  140 , a phase lock loop circuit  150  and a divide by M circuit  160 . In one embodiment, the voltage-controlled oscillator  130  is a voltage-controlled crystal oscillator. In one embodiment, the PFD  120  and VCO  130  may be implemented using the High Performance Phase Frequency Locked Loop as marketed by Texas Instruments of Dallas, Tex., under the part designation TLC29321. In one embodiment, the loop filter  125  may be implemented using a low pass filter. Examples of such a low pass filter includes a lag filter, a lag-lead filter and an active filter. The PLL system  100  receives the HSYNC-signal r 1 , and provides the HSYNC signal to a divide-by-P circuit  110  which divides the frequency f 1  of r 1  by an integer, P. This is accomplished so as to enable the user to configure the PLL system  100  to operate at any desired lower frequency. The resulting signal r 2  has a frequency f 2 =f 1 /P, which is provided as one input to phase frequency detector (PFD)  120 . 
     The PFD  120  compares the input signal r 2  with a feedback signal f b  and provides a control voltage to a loop filter  125 . The loop filter  125  is provided to ensure stable loop operation and low jitter. The filtered control voltage is then provided to the VCO  130  which generates a frequency f v . The output of the VCO  130  is provided as a first output clock signal r OUT1 , which is used to drive the internal operations of the master circuit (not shown) which implements the PLL system  100 . It is apparent to one of ordinary skill in the technology that the first output clock signal r OUT1  may be used to drive any desired circuit. The output of the VCO  130  is also provided to a divide-by-X circuit  170 , which subsequently generates a second output clock signal r OUT2  that is used to drive a second circuit (not shown). For example, r OUT2  may be used as a master clock to analog-to-digital (A/D) or digital-to-analog (D/A) converters operating at the audio sample rate. It is apparent to one of ordinary skill in the technology that the PLL system  100  may be used to synchronize r 1  with r OUT1  and/or r OUT2 . In one embodiment, the value of X is determined by a ratio of the master clock frequency for the audio converters to the audio sample frequency. For example, if the audio information operates at 48 kHz and the master clock frequency (i.e., r OUT1 ) is 12.288 MHz etc., then the value of X is 256. 
     The first output signal r OUT1  is also provided to the divide-by-D circuit  140 , which divides the frequency of r OUT1  by an integer D. The divide-by-D circuit  140  is implemented to facilitate use of a phase locked loop (PLL) circuit  150  that operates at a desired frequency. The resulting signal, r 3  (which has a frequency of f 3 ) is provided to the PLL circuit  150 , which in turn generates a signal r 4  having a frequency of f 4 . The value of D is determined by a ratio of the frequency of r OUT1 , i.e., f OUT1 , to the quantity (M*f 1 /N). The PLL circuit  150  is used to assist in locking the signal r 4  to the frequency of the signal r 3 , i.e., to f 3 . In one embodiment, the PLL circuit  150  comprises a PFD  152 , a loop filter  154 , a VCO  155  and a divide-by-N circuit  156 . In one embodiment, the PFD  152  and VCO  155  may be implemented using the High Performance Phase-Frequency Locked Loop as marketed by Texas Instruments of Dallas, Tex., under the part designation TLC29321. In one embodiment, the loop filter  154  may be implemented using a low pass filter. Examples of such a low pass filter includes a lag filter, a lag-lead filter and an active filter. 
     The PFD  152  receives r 3  and compares the phase/frequency of r 3  (i.e., f 3 ) with the phase/frequency of a feedback signal f bb . The PFD  152  produces a control voltage which is a function of the difference (error) between the input signal r 3  and the feedback signal. This difference is a frequency difference between the input signal r 3  and the feedback signal f bb , when the PLL circuit  150  has not yet locked onto the input signal r 3 . Upon locking onto the input signal r 3 , the PFD  152  detects the phase difference between the input signal r 3  and the feedback signal fbb. The PFD  152  presents the control voltage to loop filter  154 , which filters the control voltage and subsequently provides the filtered control voltage to the VCO  155  to adjust the frequency of its output signal r p . The output of VCO  155  is provided as a feedback signal to the divide-by-N circuit  156 , which divides the frequency of the output of VCO  155  by N. The resulting signal is provided as a feedback signal fbb to PFD  152 . After some response time, as determined by the frequency response of the loop filter  154 , the PLL circuit  150  locks onto the signal r 3  and presents an output signal r 4 . 
     The signal r 4  is next provided to a divide-by-M circuit  160 , which subsequently divides the f 4  by an integer M. The value of M is determined by f 4 /f 1 . The divide-by-M circuit  160  generates a feedback signal f b  that is provided to the PFD  120 . As discussed earlier, the PFD  120  receives HSYNC signals from a frame clock and compares the phase/frequency of the input signals with the phase/frequency of the feedback signal f b . The PFD  120  produces a control voltage which is a function of the difference (error) between the input signal (i.e., HSYNC or r 1 ) and the feedback signal f b . This difference is a frequency difference between the input signal (HSYNC or r 1 ) and the feedback signal f b , when the PLL circuit  100  has not yet locked onto the input signal (HSYNC or r,). Upon locking onto the input signal (HSYNC or r 1 ), the PFD  120  detects the phase difference between the input signal (HSYNC or r 1 ) and the feedback signal f b . The PFD  120  presents a control voltage to the VCO  130  to adjust the frequency of the output signal. After some time as determined by the frequency response of the loop filter  125 , the PLL system  100  locks onto the-input clock signal r 1  and presents output signals r OUT1  and r OUT2 , each having a stable frequency and phase. 
     The relationship between the values P, D, N and M of the respective divider circuits  110 ,  140 ,  156  and  160 , with that of the input signal, HSYNC (or r 1  having a frequency of f 1 ) and the frequency f v  generated by the VCO  130  may be expressed as follows: 
     
       
         
           f 
           1 
           P=[f 
           v 
           *N]/[D*M] 
         
       
     
     Using numerical techniques, the smallest value of P, N, D and M may be obtained. It is apparent to one of ordinary skill in the technology that divider circuit(s) providing any other multiple of the smallest value of P, N, D and M may be implemented, according to need and availability. 
     A further aspect of the present invention is the use of a reset signal RESET (see FIG. 2) for synchronizing the reset of all the divider circuits  110 ,  140 ,  156 ,  160  and  170 . As is apparent to one of ordinary skill in the art, any combination of the divider circuits  110 ,  140 ,  156 ,  160  and  170  may be synchronously or simultaneously reset using the reset signal. In this manner, all or a combination of the divider circuits  110 ,  140 ,  156 ,  160  and  170  may be reset with a single input, and timing considerations associated with individual reset of the divider circuits  110 ,  140 ,  156 ,  160  and  170  may be dispensed with. In one embodiment, the reset signal is applied coincident with the frame edge of the incoming video source so that the audio sample clock edge is exactly coincident with the video frame edge. 
     FIG. 3 is a chart illustrating a variety of frequency values that the crystal oscillator of FIG. 2 may be configured to provide, so as to accommodate a corresponding variety of frame rates. As shown, for a sample rate of 48 kHz, the VCO  130  provides a frequency (f v ) of 12288000 Hz. 
     FIGS. 4A and 4B are charts illustrating a variety of values P, D, N and M for the respective divide counters  110 ,  140 ,  156  and  160  of FIG. 2, corresponding to a variety of video formats, based on a sample rate of 48 kHz (i.e., where r OUT2 is 48 kHz) and where f v , the frequency generated by the VCO  130  is 12.288 MHz. As shown in FIG. 4A, when interfacing with an NTSC Color format, the input signal r 1  has a frequency f 1  of 15.73426573 kHz. The corresponding value of P for divide-by-P circuit  110  is 15, so as to provide a signal r 2  of frequency 1.048951049 kHz. The corresponding value of D in the divide-by-D circuit  140  is 32, and the output frequency f 3  of the divide-by-D circuit  140  is 384.000 kHz. The corresponding value of N in the divide-by-N circuit  156  is 50, while the frequency of the VCO  155  is 19.2 MHz. The corresponding value of M in the divide-by-M circuit  160  is 18304, while the output frequency of the divide-by-M circuit  160  is 1.048951049 kHz. 
     When interfacing with an NTSC Black and White format, the input signal r 1  has a frequency f 1  of 15.750 kHz. The corresponding value of P for divide-by-P circuit  110  is 10, so as to provide a signal r 2  of frequency 1.575 kHz. The corresponding value of D in the divide-by-D circuit  140  is 32, and the output frequency f 3  of the divide-by-D circuit  140  is 384.000 kHz. The corresponding value of N in the divide-by-N circuit  156  is 42, while the frequency of the VCO  155  is 16.128 MHz. The corresponding value of M in the divide-by-M circuit  160  is 10240, while the output frequency of the divide-by-M circuit  160  is 1.575 kHz. 
     When interfacing with the PAL format, the input signal r 1  has a frequency f 1  of 15.625 kHz. The corresponding value of P for divide-by-P circuit  110  is 10, so as to provide a signal r 2  of frequency 1.5625 kHz. The corresponding value of D in the divide-by-D circuit  140  is 32, and the output frequency f 3  of the divide-by-D circuit  140  is 384.000 kHz. The corresponding value of N in the divide-by-N circuit  156  is 50, while the frequency of the VCO  155  is 19.2 MHz. The corresponding value of M in the divide-by-M circuit  160  is 12288, while the output frequency of the divide-by-M circuit  160  is 1.5625 kHz. 
     FIG. 5 is a chart illustrating a variety of values P, D, N and M for the respective divide counters  110 ,  140 ,  156  and  160  of FIG. 2, when the phase lock loop system  100  is configured to adjust the corresponding frequencies provided by a variety of systems. As shown, the “off” speeds differ from the sample rate of 48 kHz or 44.1 kHz by ±0.1%. In the case of the sample rate of 48 kHz, the “off” speeds include an “up” speed of 48.048 kHz (difference of ±0.1% from 48 kHz), and a “down” speed of 47.95205 kHz (difference of −0.1% from 48 kHz). In such a case, the various values, such as P, D, N, f v  and M must be reconfigured. 
     For example, when interfacing with the NTSC format, and used for adjusting from a sample rate of 48 kHz to an “up” speed of 48.048 kHz, the input-signal r 1  has a frequency f 1  of 15.73426573 kHz. The corresponding value of P for divide-by-P circuit  110  is 15, so as to provide a signal r 2  of frequency 1.048951049 kHz. The corresponding value of D in the divide-by-D circuit  140  is 32, and the output frequency f 3  of the divide-by-D circuit  140  is 384 kHz. The corresponding value of N in the divide-by-N-circuit  156  is 50, while the frequency of the VCO  155  is 19.2MHz. The corresponding value of M in the divide-by-M circuit  160  is 18304, while the output frequency of the divide-by-M circuit  160  is 1.048951049 kHz. Other examples are illustrated in FIG.  5 . 
     The present invention thus provides a stable and flexible PLL system-that provides a fast response time, while providing compatibility with a variety of video standards. 
     In typical audio and video systems, the time difference between the incoming synchronization (“sync”) signal and the outgoing audio signal (which is based on the output sync signal) is generally random, as shown in FIG. 6A, and thus unsynchronized, resulting in the loss of sound quality due to phase differences between different audio sources. Attempts at synchronization to provide input and output sync signals as shown in FIG. 6B are achieved with equal input and output audio sampling rates. FIG. 6C illustrates one example in which the video vertical sync signal (or frame sync) is used as the sync source. In this case, the video sync signal rising edge is coincident with a rising edge of the output sync signal every video frame. 
     FIG. 7 illustrates one embodiment of the synchronization system  200  provided in accordance with the teachings of the present invention. As shown, the synchronization system  200  comprises the divide-by-P circuit  110 , a phase lock loop PLL  115 , a divide-by-X circuit  170 , an analog-to-digital converter  220 , a processor  230  such as a digital signal processor (DSP), a divide-by-Z circuit  240  and a digital audio transmitter  250 . In one embodiment, the processor  230  includes any one of the x86, Pentium™, Pentium II™, and Pentium Pro™ microprocessors as marketed by Intel™ Corporation, the K-6 microprocessor as marketed by AMD™, or the 6x86MX microprocessor as marketed by Cyrix™ Corp. Further examples include the Alpha processor as marketed by Digital Equipment Corporation™, the 680X0 processor as marketed by Motorola™; or the Power PC processor as marketed by IBM™. In addition, any of a variety of other processors, including those from Sun, MIPS, IBM, Motorola, NEC, Cyrix, AMD, Nexgen and others may be used for implementing processor  230 . The processor  230  is not limited to microprocessor but may take other forms such as a microcontroller, digital signal processor, reduced instruction set computer, application specific integrated circuit, and the like. Although shown with one processor, synchronization system  200  may alternatively include multiple processing units. 
     The PLL  115  comprises a PFD  120 , loop filter  125 , VCO  130 , divide-by-D circuit  140 , the phase lock loop circuit  150 , the divide-by-M circuit. The PFD  120 , loop filter  125 , VCO  130 , divide-by-D circuit  140 , the phase lock loop circuit  150 , the divide-by-M circuit  160  and the divide-by-X circuit  170  are the same as that shown in FIG.  2 . However, in the synchronization system  200 , the divide-by-D circuit  140 , the divide-by-N circuit  156 , the divide-by-M circuit  160  and the divide-by-X circuit  170  are not reset through the RESET signal of FIG. 2, but by a Reset signal  232  that is issued by a processor  230 , as discussed in detail in the following sections. The synchronization system  200  further comprises a sync multiplexer (MUX)  210  that receives inputs from a variety of sources. Such sources include, but are not limited to, a Word Clock circuit (not shown) that provides a Word Clock signal, a digital audio receiver  212 , that provides a digital audio frame sync signal, and a video sync circuit, that provides a horizontal sync (HSYNC) signal to the sync mux  210  and a vertical sync (VSYNC) signal to the processor  230 . One example of the digital audio receiver  212  is the Audio Engineering Society/European Broadcaster&#39;s Union (“AES/EBU”) receiver, such as that marketed by Cirrus Logic, Inc., under the part designation CS8412 or CS8414. 
     The processor  230  also receives the digital audio frame signal from the digital audio receiver  212 , and the VSYNC signal generated by the video sync circuit  214 . The processor  230  further receives digital signals from an analog-to-digital converter (ADC)  220 , which generates digital values that are proportional to the analog output of the PFD  120 . In one embodiment, the ADC  220  is an 8-bit converter, which provides digital values in the range of 0 to 255. The processor  230  generates a Select signal that is provided to the sync mux  210  to select one of the plurality of input signals received by the sync mux  210 . The processor  230  further generates a RESET signal  232  that is provided to the divide-by-X circuit  170  and a digital audio transmitter  250 . One example of the digital audio transmitter  250  is the AES/EBU transmitter, such as that marketed by Cirrus Logic Inc., under the part designation 8402A or 8404A. 
     As shown in FIG. 7, the output f v  of the VCO  130  is provided to the divide-by D circuit  140 , the divide-by-X circuit  170  and a divide-by-Z circuit  240 . The output of the divide-by-Z circuit  240  is provided to the digital audio transmitter  250 , which generates an output sync (Fsync) signal and a digital audio reference output signal based on the output f v  of the VCO  130 . The output sync signal Fsync is fed back to the processor  230 , which issues the reset signal  232  based on one of the input sync signals, in accordance with the principles of the invention, which is discussed in detail in the following sections. The digital audio reference output signal (AES reference signal) may be used as a reference signal to provide digital audio synchronization between digital audio devices. The output r OUT2  of the divide-by-X circuit  170  is fed back to the processor  230  as an output sync signal at the audio rate. This square wave signal is often referred to as a “word clock.” In particular, the output signal r OUT2  is provided as an output of the synchronization system  200  to connect to the input of a second synchronization system  200  (or other digital audio device) where the sync mux of that second system selects a word clock signal. In addition, the output digital audio reference is provided as the output of the synchronization system  200  to connect to the input of a second system  200  where the sync mux of the second system  200  selects the frame signal from the digital audio receiver  212  which receives the AES reference signal. In this manner, the system  200  may provide synchronization between two digital audio systems. In addition, the input signal of the system  200  may be selected from a variety of input sources, including but not limited to a word clock circuit, an AES reference signal source or a video source. 
     In accordance with the practices of persons skilled in the art of computer programming, the present invention is described below with reference to symbolic representations of operations that are performed by synchronization system  200 , unless indicated otherwise. Such operations are sometimes referred to as being computer-executed. It will be appreciated that the operations which are symbolically represented include the manipulation by processor  230  of electrical signals representing data bits and the maintenance of data bits at memory locations in memory (not shown), as well as other processing of signals. The memory locations where data bits are maintained are physical locations that have particular electrical, magnetic, optical, or organic properties corresponding to the data bits. 
     When implemented in software, the elements of the present invention are essentially the code segments to perform the necessary tasks. The program or code segments can be stored in a processor readable medium or transmitted by a computer data signal embodied in a carrier wave over a transmission medium or communication link. The “processor readable medium” may include any medium that can store or transfer information. Examples of the processor readable medium include an electronic circuit, a semiconductor memory device, a ROM, a flash memory, an erasable ROM (EROM), a floppy diskette, a CD-ROM, an optical disk, a hard disk, a fiber optic medium, a radio frequency (RF) link, etc. The computer data signal may include any signal that can propagate over a transmission medium such as electronic network channels, optical fibers, air, electromagnetic, RF links, etc. The code segments may be downloaded via computer networks such as the Internet, Intranet, etc. 
     FIG. 8 is a graph illustrating the ADC  220  output level, which represents the voltage at the input of VCO  130 . Any timing difference between the input and output sync signals f i  and f o  will cause the phase lock loop to lose lock. For present discussion purposes, reference to a timing difference refers to the timing difference in the leading or trailing edges of the input and output sync signals f i  and f o . When the timing difference is zero, the leading or trailing edges (depending on the edge selected as a reference) are coincident, i.e., the signals are synchronized, as shown in FIG.  6 B. As shown in FIG. 7, upon receiving an input signal f i  the synchronization system  200  generates an output sync signal f o . The output sync signal f o  may be that generated by the digital audio transmitter  250  (i.e., Fsync)or the divide-by X-circuit  170  (i.e., r OUT2 ), depending on the corresponding input signal. In particular, if the input signal is a word clock signal, then the output sync signal is r OUT2 ; if the input signal is a digital audio frame sync signal, then the output sync signal is Fsync. In either case, the timing difference between the output sync signal f o  and the input sync signal f i  is initially large and rapidly changing. The processor  230  is configured to monitor the VCO  130  input and issue a signal indicating that the two signals are synchronized when the timing difference is substantially zero. 
     In one embodiment, such a process is provided in software that is executed by the processor  230 . A C language version of this software embodiment is shown in FIG. 9 and a flow chart of the software is shown in FIGS. 10A and 10B. The software may be stored in memory (not shown) coupled to the DSP  230 . The synchronization is monitored in three stages. The first, referred to as LOCKSTATUS=1 is established when the output [hereinafter referred to as “ADC value”] of the ADC  220 , which represents the output-of the Loop Filter  125 , is X 1 &lt;ADC value&lt;X 2 , where X 1  and X 2  are predetermined integers. In one embodiment, where the ADC  220  is an 8-bit converter, X 1  is 24 and X 2  is 232. When LOCKSTATUS=1, it indicates that the ADC value is within a range that is acceptable for further synchronization monitoring. Next, the DSP  230  determines if the ADC value difference is less than Y, where Y is a predetermined integer. In this case, the ADC value difference DIFF ADC  is calculated as follows: 
     
       
           DIFF   ADC =|(current  ADC  value)−(previous  ADC  value)|  equation (1). 
       
     
     In one embodiment, Y is in a range between 3 and 20. In a second embodiment, Y is 5. When the relationship DIFF ADC &lt;Y is established, LOCKSTATUS=2. The next stage, LOCKSTATUS=3, is achieved when the timing difference between f i  and f o  is substantially equal to zero after the phase reset circuit is activated (see discussion below). When this occurs, the processor  230  will indicate that the required synchronization is accomplished. 
     FIGS. 10A and 10B are flow charts illustrating one embodiment of the synchronization process of the invention. Beginning from a start state, the process  300  proceeds to decision block  310 , where it determines if a predetermined time interval has elapsed. This interval is selected for running the process  300  at a predetermined time, for example, every second. If so, the process  300  reads the PLL  115 &#39;s ADC  220  value, as shown in process block  312 . The process  300  then determines if the ADC value is between X 1  and X 2 , i.e., if X 1 &lt;ADC value&lt;X 2 , where X 1  and X 2  are predetermined integers. As discussed earlier, if the ADC  220  is an 8-bit converter, having values in the range of 0 and 255, then X 1  may be selected to be 24 and X 2  may be selected to be 232. If the ADC value is not within this range, then LOCKSTATUS is set to zero, as shown in process block  316  and the process  300  returns to decision block  310 . Otherwise, the process  300  proceeds to process block  318 . At process block  318 , the process  300  calculates the difference DIFF ADC , between the current ADC value and the previous ADC value, in accordance with equation (1). The process  300  then advances to decision block  320  and determines if DIFF ADC  is less than a predetermined value Y, where Y is an integer. In one embodiment, Y is in a range between 3 and 20 depending on the frequency variation in the incoming clock signal. In a second embodiment, Y is fixed at 7. If DIFF ADC &gt;Y, then the LOCKSTATUS is set to 0 (process block  322 ) and the process  300  returns to process block  310 . When the relationship DIFF ADC &lt;Y is established, the process  300  proceeds to decision block  324  to determine if LOCKSTATUS=0, if so, the Phase Reset Bit is set to TRUE (process block  326 ) and LOCKSTATUS is set to 1 (process block  328 ). When the Phase Reset Bit is set, it indicates to the reset circuit that the required phase lock or synchronization has not yet been achieved. Later when the phase reset bit is released, the RESET signal will be pulsed near the: time of the next edge of the input sync source. Next, the process  300  returns to process block  310 . 
     If, at decision block  324 , the LOCKSTATUS≠0, the process  300  advances to decision block  330 , where it queries if LOCKSTATUS is equal to 1. If not, the process  300  advances to decision block  332 , where it checks if LOCKSTATUS is equal to 2. If not, it proceeds back to process block  310 . If LOCKSTATUS=1, it proceeds to decision block  334 , where it determines if the input sync signal edge has been detected. If not, the process  300  remains at block  334 , where it continues to monitor for the input sync signal edge. Otherwise, it proceeds to process block  336 , where the processor  230  waits N DELAY  (typically  42  in one embodiment) audio samples and then issues the RESET signal by releasing the phase reset bit in process block  338 . The process  300  then proceeds to block  340 , where it sets LOCKSTATUS=2 and returns to process block  310 . 
     If, at decision block  332  LOCKSTATUS=2, the process  300  waits until both the input and output sync edges have been detected (done by process blocks  342  and  344 ). The process  300  then proceeds to process block  346 , where it checks the time difference between the leading or trailing edges of the input and output sync signals. The process  300  then determines if the time difference is substantially equal to zero, as shown in decision block  348 . If not, the process  300  sets LOCKSTATUS to 0 (process block  350 ) and returns to decision block  310 . Otherwise, it proceeds to process block  352 , where it sets LOCKSTATUS=3, indicating that the required synchronization is achieved. The process  300  then continues to monitor the LOCKSTATUS by proceeding to decision block  310 . 
     The present invention thus provides an apparatus and method for providing synchronization between two signals, one of which may be selected from a plurality of sources, including a video source, an audio source and a word clock circuit. For example, the synchronization system may synchronize an audio signal with another audio signal, an audio signal with a video signal and/or a word clock signal to another word clock signal. Such synchronization may be accomplished with increased precision and flexibility over that provided by existing systems. 
     The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.