Abstract:
The present invention discloses a short circuit protection circuit comprising: a first input terminal; a second input terminal; an output terminal; at least two transistors including a first and a second transistors connected in series with each other and electrically connected between the first input terminal and the output terminal; and a voltage source circuit electrically connected with the first input terminal, the second input terminal, the output terminal, and the gates of the first and second transistors.

Description:
FIELD OF INVENTION 
     The present invention relates to a circuit and a method for short circuit protection, and in particular to a short circuit protection circuit to be electrically connected to an output terminal of a boost converter circuit, which is made of relatively low voltage devices but capable of sustaining relatively high voltage, and a corresponding short circuit protection method. 
     BACKGROUND OF THE INVENTION 
     A boost converter circuit converts a relatively low input voltage to a relatively high output voltage and supplies it to a load.  FIG. 1  shows a conventional boost converter circuit  10 , which converts a relatively low input voltage Vin to a relatively high output voltage and supplies it to an output terminal Vout. In the circuit shown in  FIG. 1 , if the output terminal of the boost converter circuit  10  is shorted to ground, although the switch SW can be turned OFF by the control circuit  12 , the path from the input terminal Vin to the output terminal Vout is still conductive; therefore, the inductor L still keeps storing energy, and there may be other damages caused by current continuously flowing on the path. Hence as shown in  FIG. 2 , preferably, a short circuit protection circuit is provided between the output VBO of the boost converter circuit  10  and the output terminal Vout, for cutting off the conduction between the node VBO and the output terminal Vout when the output terminal of the boost converter circuit  10  is shorted to ground. 
       FIGS. 3-7  show several conventional short circuit protection circuits  14 . Referring to  FIG. 3 , in normal operation, the output voltage VBO is higher than the input voltage Vin, the gate to source voltage Vgs of the PMOS transistor Q being negative, so the PMOS transistor Q is completely ON, and the voltage at the output terminal Vout is substantially equal to the output voltage VBO of the boost converter circuit  10 . When the output terminal Vout is shorted to ground, the boost converter circuit  10  does not operate, and the output voltage VBO of the boost converter circuit  10  drops. When the output voltage VBO is equal to the input voltage Vin, the gate to source voltage Vgs of the PMOS transistor Q becomes zero, and therefore the PMOS transistor Q turns OFF, cutting off the conduction between the node VBO and the output terminal Vout, to thereby provide the short circuit protection effect. 
     The operation of the circuits shown in  FIGS. 4-6  is similar to that of  FIG. 3 . As to the circuit of  FIG. 7 , in normal operation, the switch S is ON; when the output terminal Vout is shorted to ground, a control signal is generated (for example from the comparator shown in  FIGS. 1 and 2 ) to turn OFF the switch S, so that the gate to source voltage Vgs of the PMOS transistor Q becomes zero. In this manner, it also achieves the short circuit protection effect as above. 
     The conventional short circuit protection circuits shown in  FIGS. 3-7  do provide the short circuit protection effect as required, but they have the following disadvantages. Because the circuit  10  is a boost converter, the output voltage VBO is a high voltage, and thus at the initial instant period when the output terminal Vout is shorted to ground, the source to drain voltage difference of the transistor Q is very large. For this reason, the transistor Q has to be made of a costly high voltage device capable of sustaining relatively high voltage, and it also increases the complexity of the corresponding wafer manufacturing process. 
     Therefore, a short circuit protection circuit made of relatively low voltage devices but capable of sustaining relatively high voltage is desired. 
     SUMMARY 
     In view of the foregoing, it is an objective of the present invention to provide a short circuit protection circuit, to meet the aforementioned desire. 
     Another objective of the present invention to provide a short circuit protection method. 
     In accordance with the foregoing and other objectives of the present invention, and from one aspect of the present invention, a short circuit protection circuit comprises: a first input terminal; a second input terminal; an output terminal; at least two transistors including a first and a second transistors connected in series with each other and electrically connected between the first input terminal and the output terminal; and a voltage source circuit electrically connected with the first input terminal, the second input terminal, the output terminal, and the gates of the first and second transistors. 
     Preferably, when the output terminal is shorted to ground, the voltage source circuit controls the gates of the first and second transistors such that the first and second transistors share the voltage difference between the first input terminal and the output terminal. In addition, when the first input terminal is below a predetermined voltage, the voltage source circuit controls the gates of the first and second transistors to cut off the conduction between the first input terminal and the output terminal. 
     Preferably, the voltage source circuit includes three voltage sources: a first voltage source electrically connected between the first input terminal and the gate of the first transistor, a second voltage source electrically connected between the gate of the first transistor and the gate of the second transistor, and a third voltage source electrically connected between the gate of the second transistor and the second input terminal. More preferably, the second voltage source is a variable voltage source. 
     From another aspect of the present invention, a short circuit protection method, comprising the steps of: providing at least two transistors including a first and a second transistors connected in series with each other and electrically connected between an input terminal and an output terminal; when the output terminal is operating normally, controlling the voltages at the gates of the first and second transistors to be substantially equal with each other; and when the output terminal is shorted to ground, controlling the first and second transistors such that the first and second transistors share the voltage difference between the input terminal and the output terminal. 
     It is to be understood that both the foregoing general description and the following detailed description are provided as examples, for illustration rather than limiting the scope of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings. 
         FIG. 1  is a schematic diagram showing a conventional boost converter circuit. 
         FIG. 2  is a schematic diagram showing how a short circuit protection circuit is provided to the output terminal of a conventional boost converter circuit. 
         FIGS. 3-7  are schematic diagrams showing conventional short circuit protection circuits. 
         FIG. 8  is a schematic diagram showing a short circuit protection circuit according to an embodiment of the present invention. 
         FIGS. 9 and 10  are schematic diagrams showing two short circuit protection circuits according to two embodiments of the present invention. 
         FIG. 11  is a schematic diagram showing a more specific hardware structure of the embodiment of  FIG. 9 . 
         FIG. 12  is a schematic diagram showing a more specific hardware structure of the embodiment of  FIG. 10 . 
         FIG. 13  is a schematic diagram showing another hardware structure of the embodiment of  FIG. 10 . 
         FIG. 14  is a schematic diagram showing an alternative of the embodiment of  FIG. 13 . 
         FIGS. 15A and 15B  show alternatives to the zener diode. 
         FIGS. 16A-16D  show alternatives to the current source. 
         FIG. 17  is a schematic diagram showing another embodiment of the present invention. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       FIG. 8  is a schematic circuit diagram illustrating a first embodiment of the present invention. As shown in the figure, according to the present embodiment, two transistors Q 1  and Q 2  are provided. At the initial instant period when the output terminal Vout is shorted to ground, the voltage VBO is still much higher than the input voltage Vin, so the resistors R 1 , R 2  and R form a voltage divider circuit, and the gate to source voltages Vgs 1  and Vgs 2  of the transistors Q 1  and Q 2  correspond to the voltages across the resistors R 1  and R 2 , respectively. Assuming R 1 =R 2  for simplicity (not necessarily required), and that the transistors Q 1  and Q 2  have matching characteristics, the transistors Q 1  and Q 2  evenly share the voltage VBO. In comparison with the conventional circuits shown in  FIGS. 3-7 , because the transistors Q 1  and Q 2  evenly share the voltage VBO, they can be made of devices having a lower voltage specification than that of the transistor Q. In general, the cost of two transistors with a lower voltage specification is still lower than the cost of one transistor with a higher voltage specification, and furthermore the process integration for low voltage devices is easier. The resistors R 1 , R 2  and R in this embodiment may be replaced by other voltage sources or devices providing similar effects, such as zener diode, current source, and the like, as referring to  FIGS. 3-7 . 
     The embodiment of  FIG. 8  can be further improved with respect to its power transmission efficiency. More specifically, assuming R 1 =R 2  for simplicity, if both transistors Q 1  and Q 2  are completely turned ON, it means VBO=Va=Vout. However, because of the voltages across the resistors R 1  and R 2 , the gate to source voltage Vgs 2  of the transistor Q 2  is twice the gate to source voltage Vgs 1  of the transistor Q 1 ; thus, unless the transistors Q 1  and Q 2  have different device characteristics, they can not both be completely turned ON. In practice, the two transistors are devices with the same characteristics, and therefore the transistor Q 1  can only be turned half-ON, forming a relatively higher internal resistance. As a result, Vout&lt;VBO, that is, the voltage VBO can not be fully transmitted to the output terminal Vout, and the power transmission efficiency is not optimum. 
     The embodiment of  FIG. 8  can be further improved according to the present invention. Referring to  FIG. 9  which shows a more preferred embodiment, in which a variable voltage source Vs 2  is provided between the gates of the transistors Q 1  and Q 2 . The variable voltage source Vs 2  has a voltage value which is controlled by a control signal CS. The control signal CS for example may be the output from the comparator shown in  FIGS. 1 and 2 , or other signals (to be explained later). 
     The circuit of  FIG. 9  operates as follows. In normal operation, the voltage value of the variable voltage source Vs 2  is zero, so that there is no voltage difference between the gates of the transistors Q 1  and Q 2 . When the voltage across the voltage source Vs 1  completely turns ON the transistor Q 2 , the transistor Q 1  is also completely turned ON, so that there is no voltage difference among the voltages VBO, Va and Vout. As a result, the voltage VBO is fully transmitted to the output terminal Vout. 
     When the output terminal Vout is shorted to ground, the voltage value of the variable voltage source Vs 2  is controlled to be higher than zero, so that the transistors Q 1  and Q 2  share the voltage VBO (which is very high at the instant period when the output terminal Vout is just shorted to ground). In one embodiment, the voltage value of the variable voltage source Vs 2  is substantially equal to the voltage value of the voltage source Vs 1 , thus, according to the principle explained in the above with reference to  FIG. 8 , the transistors Q 1  and Q 2  evenly share the voltage VBO. Thereafter, the voltage VBO gradually decreases to the level of the voltage Vin, and at this moment the gate to source voltage Vgs 1  of the transistor Q 1  becomes zero, so that the transistor Q 1  is turned OFF, to cut off the conduction between the voltage node VBO and the output terminal Vout. 
       FIG. 10  shows another preferred embodiment of the present invention. In fact, the normal (life-time) voltage sustaining capability of, a transistor device is different from the short-term (instant) voltage sustaining capability of the same transistor device; the latter can be as high as twice the former. In this embodiment, the voltage source Vs 1  is replaced by a variable voltage source Vs 4 , which is also subject to the control by the control signal CS (or by other means). In normal operation, the voltage value of the variable voltage source Vs 4  is about equal to that of the voltage source Vs 1 ; when the output terminal Vout is shorted to ground, the voltage value of the variable voltage source Vs 4  can be increased to, e.g., twice that of the voltage source Vs 1 , and the variable voltage source Vs 2  is also adjusted to about the same value. Thus, the gate to source voltages Vgs 1  and Vgs 2  of the transistors Q 1  and Q 2  become twice that of the transistors Q 1  and Q 2  in  FIG. 9 ; in other words, the transistors Q 1  and Q 2  can be made of devices having lower specification of sustained voltage. For example, the specification of sustained voltage of the transistors Q 1  and Q 2  in  FIG. 10  can be half of that of the transistors Q 1  and Q 2  in  FIG. 9 . 
     As a more detailed embodiment of the circuit shown in  FIG. 9 , please refer to  FIG. 11 . In this embodiment, the voltage source Vs 1  is a zener diode Z 1 ; the variable voltage source Vs 2  is a parallel circuit including a zener diode Z 2  and a path having a switch thereon. The switch S 12  is subject to the control by the control signal CS such that the switch S 12  is ON in normal operation, but is turned OFF when the output terminal Vout is shorted to ground. 
       FIG. 12  is a more detailed embodiment of the circuit shown in  FIG. 10 , in which the variable voltage source Vs 4  includes two zener diodes Z 11  and Z 12 , and a switch S 14  connected in parallel; the variable voltage source Vs 2  includes two zener diodes Z 21  and Z 22 , and a switch S 12  connected in parallel. In normal operation, both switches S 12  and S 14  are turned ON by the control signal CS; when the output terminal Vout is shorted to ground, both switches S 12  and S 14  are turned OFF by the control signal CS. In this manner, by means of the instant voltage sustaining capability of the transistors Q 1  and Q 2 , the gate to source voltages of the two transistors are further expanded when the output terminal Vout is shorted to ground, which means that the transistors Q 1  and Q 2  can be made of devices having even lower specification of sustained voltage than that in the circuit of  FIG. 9 . 
     The control signal CS can be generated from the comparator shown in  FIGS. 1 and 2 , or by other means for example as follows. Referring to  FIG. 13 , four current sources I 1 -I 4  are provided in this embodiment, wherein the current amounts of the current sources are in this order: I 1 &lt;I 2 &lt;I 3 &lt;I 4 . In normal operation, because the voltage at the node VBO is about equal to the voltage at the output terminal Vout, I 4  is not conductive; and because I 1 &lt;I 2 &lt;I 3 , the nodes N, G 1  and G 2  are shorted together, bypassing the zener diodes Z 12 , Z 21  and Z 22 . The gate to source voltages of the transistors Q 1  and Q 2  are both equal to the breakdown voltage of the zener diode Z 11 , and are both turned ON. 
     On the other hand, at the initial instant period when the output terminal Vout is shorted to ground, the voltage at the node VBO is far greater than the voltage at the output terminal Vout, and thus I 4  is conductive; and because I 2 &lt;I 3 &lt;I 4 , the voltage at the node G 2  will be pulled down to a level where all zener diodes Z 11 , Z 12 , Z 21  and Z 22  breakdown, to create a current path from the node VBO through zener diodes Z 11 -Z 12 -Z 21 -Z 22  to the node G 2  to supply more current in addition to the current sources I 2  and I 3 . Thus, the gate to source voltage Vgs 1  of the transistor Q 1  is about equal to the total voltage across the zener diodes Z 11  and Z 12 , and the gate to source voltage Vgs 2  of the transistor Q 2  is about equal to the total voltage across the zener diodes Z 21  and Z 22 , so that the transistors Q 1  and Q 2  share the voltage at the node VBO. Moreover, because the input voltage Vin is higher than the voltage at the output terminal Vout, there is a current path from the input terminal Vin to the output terminal Vout through diode D 1 —node G 2 —current source I 4 —diode D 4 , and the voltage at the node G 2  is about equal to the input voltage Vin minus the voltage drop of a diode (i.e., Vin-0.7V). As the voltage at the node VBO decreases, when the voltage at the node Va is about equal to the voltage at the node G 2 , the transistor Q 2  automatically turns OFF to cut off the primary current path from the node VBO to the output terminal Vout; as the voltage at the node VBO further decreases, the zener diode Z 11  also shuts down, so that no current will flow from the node VBO to the output terminal Vout. 
       FIG. 14  is a variation of  FIG. 13 , in which the current source I 1  is connected to ground instead of Vin, and a switch SW replaces for the diode D 4  so that when the output terminal Vout is shorted to ground, after the short circuit protection is achieved, the switch SW may be turned OFF when the voltage at the node VBO is even lower than a threshold, to cut off the current path from Vin to Vout through I 4 . 
     The devices employed in the embodiments of  FIGS. 13 and 14  can be replaced in a way similar to those shown in  FIGS. 3-7 . For example, the current source I 4  may be replaced by a resistor. As another example, the zener diode ( FIG. 15A ) may be replaced by the circuit shown in  FIG. 15B . As a further example, the current source ( FIG. 16A ) may be replaced by the circuits shown in  FIGS. 16B-16D  (wherein DQ is a depletion mode MOS field effect transistor, and DJ is a depletion mode junction field effect transistor). 
     The number of the transistors to share the voltage difference between the voltage at the node VBO and the voltage at the terminal Vout is not limited to two. More number of transistors can be used, as shown in  FIG. 17 . 
     The present invention has been described in considerable detail with reference to certain preferred embodiments thereof. However, these embodiments are for illustrative purpose and not for limiting the scope of the present invention. Other variations and modifications are possible. For example, the boost converter where the present invention is applied to is not limited to the switching converter as shown in  FIGS. 1 and 2 . Moreover, although a boost converter does require a short circuit protection circuit, the short circuit protection circuit and method according to the present invention can be used in circuits other than the boost converter. The present invention can be applied to protect any abnormal condition that results in a sudden increase of voltage difference between two nodes of a circuit, not necessarily limited to short-circuiting of one of the nodes. In the embodiments above, the VOUT short circuit condition results in a sudden increase of voltage difference between VBO and VOUT. In other cases of different applications, the VBO node may be coupled to an abnormal energy source (such as being hot plugged) and the voltage at the node VBO suddenly increases to an overrated level, and similarly, it results in a sudden increase of voltage difference between VBO and VOUT. This is recognized as the “over voltage” condition, and it can also be protected by this invention. 
     In view of the foregoing, it is intended that the present invention cover all such modifications and variations, which should be interpreted to fall within the scope of the following claims and their equivalents.