Abstract:
The present invention discloses a chip package carrier and a fabrication method, which have the advantages of high reliability, thickness reduction and the scale reduction. The carrier and the method uses blind holes., which penetrates the substrate but external traces and external bonding pads, which cover the external traces. A chip can be installed and encapsulated directly on a first surface.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a chip package carrier, which, in particular uses blind hole to connect the circuits of chips and external devices. 
         [0003]    2. Description of the Related Art 
         [0004]    In chip packaging, a chip is protected by encapsulating the chip in a carrier, which uses internal traces and external traces on a substrate to communicate with external circuits. The internal traces and external traces communicate with each other via through-holes. Then, internal bonding pads and external bonding pads disposed on the internal traces and external traces to connect the chip circuits and external circuits, respectively. The internal traces, external traces and through-holes can be protected by covering a solder mask, and the chip is connected to the internal bonding pads by conductive components. At last, the chip and related components are encapsulated with a molding compound. 
         [0005]    However, it is easy to crash the electric conduction of external traces, internal traces and through-holes to degrade the reliability of a package structure due to the humidity permeation, which permeates through the space between the solder mask and traces. Besides, it is hard to decrease the thickness of the package structure to reach the demand of thinization, especially, for a mult-layer carrier. Further, it is hard to reduce the carrier size to satisfy the demand of miniaturation due to the seperated arragement of the through-holes, the internal traces, the external traces and the bonding pads. 
         [0006]    Therefore, it is very important to redesign the through-holes to reach the demands of high reliability, thickness reduction and scale reduction. 
       SUMMARY OF THE INVENTION 
       [0007]    One objective of the present invention is to provide a chip package carrier, which has the advantages of high reliability, thickness reduction and scale reduction. The carrier uses blind holes to connect internal traces with external traces. The internal bonding pads and external bonding pads cover the internal traces and the external traces, respectively. The the internal traces and external tracescan be conducted by disposing a conductive material in the blind holes. 
         [0008]    Another objective of the present invention is to provide a method of fabricating a chip package carrier having the blind holes, which has the advantage of simplifying the fabrication process. The method comprises steps of forming a metal layer on a second surface of a substrate, forming blind holes in the substrate, wherein the blind holes penetrates the substrate but the metal layer, forming external traces by processing the metal layer, wherein the external traces cover the blind holes, and covering the external traces with external bonding pads to complete a carrier. 
         [0009]    It is a method to connect the chip and the external traces via the blind hols when the chip is installed on a first surface of the substrate, and to encapsulate the chip and the related components by a molding compound. Another method is to form internal traces on the first surface and to form internal bonding pads cover the internal traces first, and then to connect the chip to the internal bonding pads, and finally to encapsulate the chip and the related components by a molding compound. 
         [0010]    Alternatively, the chip can be installed on the second surface of the carrier and connects to the external bonding pads by conductive components, and then to encapsulate the chip and related components by a molding compound. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIGS. 1   a - 1   c  are diagrams schematically showing the package structures, which are installed on the chip package carriers according to embodiments of the present invention; 
           [0012]      FIGS. 2   a - 2   c  are diagrams schematically showing the package structures, which are installed on the chip package carriers according to other embodiments of the present invention; 
           [0013]      FIGS. 3   a - 3   d  are sectional views schematically showing the process of the fabrication method of a chip package carrier according to one embodiment of the present invention; and 
           [0014]      FIGS. 4   a - 4   e  are sectional views schematically showing the process of the the fabrication method of a chip package carrier according to another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0015]    Accompanying with drawings, the description of this invention is followed to convince the spirit of this invention. 
         [0016]      FIGS. 1   a - 1   c  show the package structures of utilizing the chip package carriers according to embodiments of this invention. 
         [0017]      FIG. 1   a  shows an embodiment. Internal traces  110   u  connect with external traces  110   d  via a conductive material set inside blind holes  410 . From a first surface of the substrate  100 , the blind hole  410  penetrates the substrate  100  and the internal trace  110   u  on but the external trace  110   d  on a second surface of the substrate  100 , so called blind hole. External bonding pads  320   d  cover the external traces  110   d,  and internal bonding pads  320   u  are formed on the internal traces  110   u.  A chip  200  is installed on the first surface and between two internal traces  110   u  and connected to the internal bonding pads  320   u  via conductive components, such as metallic bonding wires. A molding compound  500  encapsulates the chip  200 , conductive components  310 , internal bonding pads  320   u  and internal traces  110   u  to complete a package structure. 
         [0018]    The embodiment in  FIG. 1   b  is a variant of the embodiment in  FIG. 1   a,  where the difference is a chip base  210  interposed between the chip  200  and the substrate  100 , and another variant, shown in  FIG. 1   c,  where the difference is the conductive balls  311  instead of the metallic bonding wires in  FIG. 1   a.    
         [0019]    The embodiments in  FIGS. 2   a - 2   c  show the package structures on a package carrier without the internal trace, and the internal bonding pads  320   u  are directly formed inside the blind holes  410  on the external traces  110   d.  The chip  200 , shown in  FIG. 2   a,  connects to internal bonding pads  320   u  via the metallic bonding wires  310 . For a variant as  FIG. 2   b,  the chip base  210  is interposed between the chip  200  and the substrate  100 , and another variant as  FIG. 2   c,  the metallic bonding wires is replaced by conductive balls  311  to reduce the thickness of the package structure further thereby. 
         [0020]    Alternatively, the chip can be installed on the second surface and connect the external bonding pads via the conductive components directly. 
         [0021]    It is not necessary to assign the material of the substrate. The substrate can be made by a copper clad laminate, an insulation substrate, a glass fiber substrate, a glass fiber prepreg, or a polymeric substrate. The conductive material inside the blind hole can be formed by electroplating a metal layer, filling metallic material or filling conductive glue, wherein the metal is copper usually. The internal and external traces are made of a conductive material, such as a metallic material or copper. The internal and external bonding pads should be made of the material having the features of high conductivity and anti-corrosiveness, such as gold, nickel, palladium, tin, lead, silver or an alloy thereof. The solder mask covering the external traces can be omitted. The conductive component, which connects the chip with the bonding pad, can be a metallic bonding wire or a conductive ball. 
         [0022]    Accompanying with  FIGS. 3   a - 3   d,  the process of making the carrier used in  FIGS. 2   a - 2   c  decribed as following. 
         [0023]    As  FIG. 3   a,  a metal layer  120   d  is formed on a second surface of a substrate  100 . Next, as  FIG. 3   b,  blind holes  400  are formed. The blind hole  400  penetrates the substrate  100  from a first surface but the metal layer  120   d.  Refer to  FIG. 3   c.  Continuously, as  FIG. 3   c,  the metal layer  120   d  is processed to form external traces  110   d,  and every external trace  110   d  covers one blind hole  400 . Finally, as  FIG. 3   d,  internal bonding pads  320   u  are formed in blind holes  400  on the external traces  110   d,  and external bonding pads  320   d  are formed on and cover the external traces  110   d.    
         [0024]    Accompanying with  FIGS. 4   a - 4   e,  the process of making the carrier used in  FIGS. 1   a - 1   c  decribed as following. 
         [0025]    As  FIG. 4   a,  a first metal layer  120   u  and a second metal layer  120   d  are formed on a first surface and a second surface of a substrate  100 , respectively. Next, as  FIG. 4   b,  blind holes  400  are formed. Every blind hole  400  penetrates the substrate  100  from the first metal layer  120   u  but the second metal layer  120   d.  Next, as  FIG. 4   c,  a conductive material  410  is filled into the blind holes  400 . Next, as  FIG. 4   d,  the first metal layer  120   u  and the second metal layer  120   d  are respectively processed to form internal traces  110   u  and external traces  110   d.  Then, as  FIG. 4   e,  internal bonding pads  320   u  are formed on the internal traces  110   u  and external bonding pads  320   d  are formed on the external traces  110   d,  respectively. 
         [0026]    The conductive material in the blind hole can be formed by an electroplating method, a sputtering method, a vapor deposition method or an electrodeless plating method. The blind hole can be formed by a plasma method, a depth-control method, an image-transfer method or a laser-drilling method. 
         [0027]    The embodiments described above are to exemplify the present invention to enable the persons skilled in the art to understand, make and use the present invention. However, it is not intended to limit the scope of the present invention. Therefore, any equivalent modification or variation according to the spirit of the present invention is to be also included within the scope of the present invention.