Abstract:
There is provided a processing system capable of preventing third parties from improper operation. Referring to FIG.  4 , a storage device generates a pseudo random number (key data k), calculates a value g (k) of a function g, rearranges each bit of the key data k and value g (k) in accordance with a predetermined method, transmits them to a terminal device, and calculates a value f (k) of a function f. The terminal device receives data and calculates a value g (k). The terminal device compares the value g (k) received from the storage device and the value g (k) calculated by the terminal device. If the values do not match, access to the storage device is stopped. If the values match, the terminal device calculates and transmits value f (k) to the storage device. The storage device compares the value f (k) calculated by the storage device and the value f (k) received from the terminal device and responds to a result of the comparison by determining whether to permit access from the terminal device.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to processing systems comprised of a data processing device and a data access device, and data processing and data access devices used in processing systems. The present invention relates particularly to processing systems comprised of data processing and data access devices capable of preventing improper access, and data processing and data access devices used in processing systems capable of preventing improper access. 
     2. Description of the Background Art 
     A hard disk device and a PC card ATA (Personal Computer Card Advance Technology Attachment) which are used in a terminal device such as a notebook-type personal computer can readily be removed from the terminal device and thus often used for carrying data. However, the data stored therein can be improperly stolen or changed by a third party and they are thus not suitable for storing classified information. Thus it is essential for such storage devices to have a mechanism which protects the security of data. It is also important for IC (Integrated Circuit) cards to have a data security protection mechanism. 
     Japanese Patent Laying-Open No. 61-43376 discloses a method of virtual authentication between an IC card and a device that can prevent a third party, e.g., from improperly stealing or changing the data stored therein. Referring to FIG. 11, an IC card  62  and a device  60 , which communicate data mutually, each have system-specific functions F 1  and F 2 . Device  60  and IC card  62  generate random numbers a 1  and a 2 , respectively, and transmit their respective random numbers to each other. Device  60  and IC card  62  each use random numbers a 1  and a 2  as arguments to calculate values F 1  (a 1 , a 2 ) and F 2  (a 1 , a 2 ) of the respective functions F 1  and F 2 . Device  60  transmits value F 2  (a 1 , a 2 ) to IC card  62 . IC card  62  compares the received value F 2  (a 1 , a 2 ) with a value F 2  (a 1 , a 2 ) calculated by IC card  62  and, if the values are equal, regards device  60  as a regular device. When IC card  62  recognizes device  60  as a regular device, IC card  62  transmits value F 1  (a 1 , a 2 ) to device  60 . Device  60  compares the received value F 1  (a 1 , a 2 ) with a value F 1  (a 1 , a 2 ) calculated by device  60  and, if the values are equal, regards IC card  62  as a regular card and issues to IC card  62  a command for access. Once the command for access has been issued, device  60  and IC card  62  mutually communicate data, as desired. Device  60  and IC card  62  having common functions and comparing values of the functions thus allow device  60  to determine whether card  62  is a regular card and card  62  to determine whether device  60  is a regular device. 
     However, if a third party could improperly steal data communicated between regular device  60  and regular IC card  62 , the third party can obtain random numbers a 1  and a 2  and values F 1  (a 1 , a 2 ) and F 2  (a 1 , a 2 ) of functions F 1  and F 2 . Thus the third party can construct a false device  60  to improperly steal data of IC card  62 . 
     It should also be noted that if possible values of random numbers a 1  and a 2  can widely range and such a round-robin system as mentioned above cannot be carried out in a reasonable time, a portion of data can be used to conjecture function F 2 . Thus a third party can construct a false device  60  which outputs value F 2  (a 1 , a 2 ) of function F 2  so that IC card  62  regards false device  60  as a regular device. Thus the third party can improperly steal data stored in IC card  62 . 
     SUMMARY OF THE INVENTION 
     The present invention has been made to overcome the above disadvantages. 
     One object of the present invention is to provide a processing system capable of preventing third parties from carrying out improper processings. 
     Another object of the present invention is to provide a processing system capable of preventing third parties from carrying out improper processings if the third parties could improperly steal data communicated between devices. 
     Still another object of the present invention is to provide a data processing device used in a processing system that can prevent third parties from carrying out improper processings. 
     Still another object of the present invention is to provide a data processing device used in a processing system that can prevent third parties from carrying out improper processings if the third parties could improperly steal data communicated between devices. 
     Still another object of the present invention is to provide a data access device used in a processing system that can prevent third parties from carrying out improper processings. 
     Still another object of the present invention is to provide a data access device used in a processing system that can prevent third parties from carrying out improper processings if the third parties could improperly steal data communicated between devices. 
     In one aspect of the present invention, a processing system includes a data processing device and a data access device which are mutually connected to implement a predetermined function. The data processing device includes a data select unit disposed to select data, a first conversion unit connected to the data select unit to convert selected data according to a predetermined method, a first transmission unit connected to the first conversion unit to transmit converted data to the data access device, a first reception unit receiving data from the data access device, a second conversion unit connected to the data select unit to convert the selected data according to a predetermined method, and a first operation determining unit connected to the first reception unit and the second conversion unit to compare outputs from the first reception unit and the second conversion unit and respond to a result of the comparison between the outputs from the first reception unit and the second conversion unit by determining an operation of the data processing device. The data access device includes a second reception unit connected to the first transmission unit to receive an output from the first transmission unit, a third conversion unit connected to the second reception unit to convert an output from the second reception unit in accordance with a predetermined method, a first comparator unit connected to the second reception unit and the third conversion unit to compare an output from the third conversion unit and data defined by the output from the second reception unit, a fourth conversion unit connected to the second reception unit to convert the output from the second reception unit in accordance with a predetermined method, and a second operation determining unit connected to the first comparator unit and the fourth conversion unit and respond to a result of the comparison by determining an operation of the data access device and transmitting an output from the fourth conversion unit to the data processing device. 
     A third party who has obtained a relationship between selected data and the output from the fourth conversion unit that is transmitted from the second operation determining unit may improperly construct a false data access device which can transmit to the data processing device the data identical to the output from the fourth conversion unit associated with the selected data once the false device has received the selected data. Thus the third party may improperly combine the false data access device with the regular data processing device to implement a predetermined function. For example, if the data processing device is a storage device the third party may improperly steal data stored in the storage device. In effect, however, the selected data is previously converted by the first conversion unit before it is transmitted to the data access device. Thus, if the third party could improperly steal communication between the data processing device and the data access device, the party could hardly extract only the selected data. Thus the third party cannot engage the processing system of interest in implementing the predetermined function. 
     Furthermore, a third party who has obtained a relationship between the data converted by the first conversion unit and the output from the fourth conversion unit may improperly construct a false data access device which can transmit to the data processing device the data identical to the output from the fourth conversion unit associated with the converted data from the first conversion unit once the false device has received the converted data from the first conversion unit. Thus the third party may improperly combine the false data access device with the regular data processing device to implement a predetermined function. In effect, however, a bit length of the data converted by the first conversion unit is an item classified between the data processing device and the data access device. Thus the third party cannot obtain the bit length of the data converted by the first conversion unit, so that the party cannot obtain the possible number taken by the converted data. Thus the third party could not find how many combinations of the converted data from the first conversion unit and the output from the fourth conversion unit should be extracted and will thus continue to take data endlessly. Thus the third party can hardly obtain such combinations properly, so that the party cannot engage the processing system of interest in implementing the predetermined function. 
     Thus the third party cannot exploit the processing system to carry out improper processings. 
     Preferably, the first conversion unit includes a fifth conversion unit connected to the data select unit to convert selected data in accordance with a first predetermined method and a sixth conversion unit connected to the data select unit and the fifth conversion unit to convert outputs from the data select unit and the fifth conversion unit in accordance with a predetermined conversion method, the third conversion unit includes a seventh conversion unit connected to the second reception unit to extract selected data from the output of the second reception unit and convert the selected data in accordance with the first method, and the first comparator unit includes a second compactor unit connected to the second reception unit and the seventh conversion unit to extract from the output of the second reception unit the data converted according to the first method and compare the extracted data with an output from the seventh conversion unit. 
     Still preferably, the sixth conversion unit includes a conversion rearrangement unit connected to the data select unit and the fifth conversion unit to rearrange each bit of the outputs from the data select unit and the fifth conversion unit in accordance with a predetermined rearrangement method. 
     In another aspect of the present invention, a data processing device is used in a processing system including a data processing device and a data access device which are interconnected to implement a predetermined function. The data processing device includes a data select unit disposed to select data, a first conversion unit connected to the data select unit to convert selected data in accordance with a predetermined method, a first transmission unit connected to the first conversion unit to transmit converted data to the data access device, a first reception unit receiving data from the data access device, a second conversion unit connected to the data select unit to convert the selected data in accordance with a predetermined method, and a first operation determining unit connected to the first reception unit and the second conversion unit to compare outputs from the first reception unit and the second conversion unit and respond to a result of the comparison by determining an operation of the data processing device. 
     A third party who has obtained a relationship between selected data and data transmitted from the data access device may improperly construct a false data access device which can transmit to the data processing device the data identical to the data transmitted from the data access device associated with the selected data once the false device has received the selected data. Thus the third party may improperly combine the false data access device with the regular data processing device to implement a predetermined function. For example, if the data processing device is a storage device the third party may improperly steal data stored in the storage device. In effect, however, the selected data is previously converted by the first conversion unit before it is transmitted to the data access device. Thus, if the third party could improperly steal communication between the data processing device and the data access device, the party could hardly extract only the selected data. Thus the third party cannot engage the processing system of interest in implementing the predetermined function. 
     Furthermore, a third party who has obtained a relationship between the data converted by the first conversion unit and data transmitted from the data access device may improperly construct a false data access device which can transmit to the data processing device the data identical to the data transmitted from the data access device associated with the converted data from the first conversion unit once the false device has received the converted data from the first conversion unit. Thus the third party may improperly combine the false data access device with the regular data processing device to implement a predetermined function. In effect, however, a bit length of the data converted by the first conversion unit is an item classified between the data processing device and the data access device. Thus the third party cannot obtain the bit length of the converted data from the first conversion unit, so that the party cannot obtain the possible number taken by the converted data. Thus the third party could not find how many combinations of the converted data from the first conversion unit and the data transmitted from the data access device should be extracted and will thus continue to take data endlessly. Thus the third party can hardly obtain such combinations properly, so that the party cannot engage the processing system of interest in implementing the predetermined function. 
     The data transmitted from the data access device to the data processing device is comprised of selected data and data converted based on the selected data, with each bit rearranged. Thus the third party could hardly extract the selected data from the rearranged data. Thus the third party could hardly construct a false data access device nor exploit the system of interest to implement improper processings. 
     Still preferably, the sixth conversion unit includes an enciphering unit connected to the data select unit and the fifth conversion unit to encipher the outputs from the data select unit and the fifth conversion unit and the second reception unit includes a reception and deciphering unit connected to the first transmission unit to receive and decipher the output from the first transmission unit. 
     Data transmitted from the data access device to the data processing device is comprised of the selected data and data converted based on the selected data that are enciphered. Thus third parties could hardly extract the selected data from the enciphered data. Thus the third parties could hardly construct a false data access device nor exploit the processing system of interest to implement improper processings. 
     In still another aspect of the present invention, a data access device is used in a processing system comprised of: a data processing device including a data select unit disposed to select data, a first conversion unit connected to the data select unit to convert selected data in accordance with a predetermined method, a first transmission unit connected to the first conversion unit to transmit converted data to a data access device, a first reception unit receiving data from the data access device, a second conversion unit connected to the data select unit to convert selected data in accordance with a predetermined method, and a first operation determining unit connected to the first reception unit and the second conversion unit to compare outputs from the first reception unit and the second conversion unit and respond to a result of the comparison by determining an operation of the data processing device; and a data access device interconnected to the data processing device to implement a predetermined function. The data access device includes a second reception unit connected to the first transmission unit to receive an output from the first transmission unit, a third conversion unit connected to the second reception unit to convert an output from the second reception unit in accordance with a predetermined method, a first comparator unit connected to the second reception unit and the third conversion unit to compare an output from the third conversion unit and data defined by the output from the second reception unit, a fourth conversion unit connected to the second reception unit to convert the output from the second reception unit in accordance with a predetermined method, and a second operation determining unit connected to the first comparator unit and the fourth conversion unit and responding to a result of the comparison by determining an operation of the data access device to transmit an output from the fourth conversion unit to the data processing device. 
     A third party who has obtained a relationship between selected data and the output from the fourth conversion unit that is transmitted from the second operation determining unit may improperly construct a false data access device which can transmit to the data processing device the data identical to the output from the fourth conversion unit associated with the selected data once the false device has received the selected data. Thus the third party may improperly combine the false data access device with the regular data processing device to implement a predetermined function. For example, if the data processing device is a storage device the third party may improperly steal data stored in the storage device. In effect, however, the selected data is previously converted by the first conversion unit before it is transmitted to the data access device. Thus, if the third party could improperly steal communication between the data processing device and the data access device, the third party could hardly extract only the selected data. Thus the third party cannot engage the processing system of interest in implementing the predetermined function. 
     Furthermore, a third party who has obtained a relationship between the data converted by the first conversion unit and the output from the fourth conversion unit may improperly construct a false data access device which can transmit to the data processing device the data identical to the output from the fourth conversion unit associated with the converted data from the first conversion unit once the false device has received the converted data from the first conversion unit. Thus the third party may improperly combine the false data access device with the regular data processing device to implement a predetermined function. In effect, however, a bit length of the data converted by the first conversion unit is an item classified between the data processing device and the data access device. Thus the third party cannot obtain the bit length of the data converted by the first conversion unit, so that the party cannot obtain the possible number taken by the converted data. Thus the third party could not find how many combinations of the converted data from the first conversion unit and the output from the fourth conversion unit should be extracted and will thus continue to take data endlessly. Thus the third party could hardly obtain such combinations properly, so that the party cannot engage the processing system of interest in implementing the predetermined function. 
     Thus the third party cannot exploit the processing system to carry out improper processings. 
     The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 schematically shows a card-type storage system  8  according to a first embodiment of the present invention. 
     FIG. 2 is a block diagram representing a configuration of a card-type data storage device  10  according to the first embodiment. 
     FIG. 3 is a block diagram representing a configuration of a terminal device  40  according to the first embodiment. 
     FIG. 4 is a flow chart of a processing performed to establish a connection between card-type data storage device  10  and terminal device  40  according to the first embodiment. 
     FIG. 5 schematically shows a card-type storage system  72  according to a second embodiment of the present invention. 
     FIG. 6 is a flow chart of a processing performed to establish a connection between a card-type data storage device  74  and a terminal device  76  in accordance with the second embodiment. 
     FIG. 7 schematically shows a card-type storage system  82  according to a third embodiment of the present invention. 
     FIG. 8 is a flow chart of a processing performed to establish a connection between a card-type data storage device  84  and a terminal device  86  in accordance with the third embodiment. 
     FIG. 9 schematically shows a card-type storage system  92  according to a fourth embodiment of the present invention. 
     FIG. 10 is a flow chart of a processing performed to establish a connection between a card-type data storage device  94  and a terminal device  96  in accordance with the fourth embodiment. 
     FIG. 11 illustrates a conventional method of virtual authentication between IC card  62  and device  60 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First Embodiment 
     Referring to FIG. 1, a card-type storage system  8  according to the first embodiment includes a terminal device  40  for writing and reading data to and from a card-type data storage device  10  described herein after and vice versa, and card-type data storage device  10  mounted internal to terminal device  40  for data storage. 
     Referring to FIG. 2, card-type data storage device  10  includes a memory block  18  for data storage, an address decoder  20  receiving an address data transmitted from terminal device  40  as an input, a command register  24  connected to terminal device  40  and address decoder  20  to receive a command issued from terminal device  40 , a command control block  22  outputting an interruption signal when the command is written in command register  24 , a variable register  26  connected to terminal device  40  and address decoder  20  to receive a value of a variable output from terminal device  40 , a data register  30  connected to terminal device  40  and memory block  18  for holding data to be written to memory block  18  and data read from memory block  18 , a data transfer control block  28  connected to memory block  18  to transmit a memory control signal to memory block  18  to control writing and reading data to and from memory block  18 , a central processing unit (CPU) block  14  connected to command control block  22 , command register  24 , variable register  26 , data transfer control block  28  and a power-on reset circuit  12  (described later) to operate in response to data held in command register  24  and data held in variable register  26 , the interruption signal output from command control block  22  and a reset signal output from power-on reset circuit  12  to control data transfer control block  28 , a random access memory (RAM)  16  and a read only memory (ROM)  17  each storing a program executed by CPU block  14  and various data, power-on reset circuit  12  outputting the reset signal when various components of card-type data storage device  10  are powered on, and a CPU bus interconnecting CPU block  14 , RAM  16 , RAM  17 , command register  24 , variable register  26  and data transfer control block  28 . 
     Referring to FIG. 3, terminal device  40  includes an input/output (I/O) interface  42  disposed to communicate data with card-type data storage device  10 , a CPU  44  performing data communication process, a ROM  46  and a RAM  48  each storing a program executed by CPU  44  and various data, and a bus interconnecting I/O interface  42 , CPU  44 , ROM  46  and RAM  48 . 
     Between card-type data storage device  10  and terminal device  40 , data are transmitted and received as desired after a connection for data transfer has been established therebetween. 
     Reference will now be made to FIG. 4 to illustrate a process performed to establish the connection between card-type data storage device  10  and terminal device  40 . 
     When card-type data storage device  10  is mounted to terminal device  40 , terminal device  40  supplies power to card-type data storage device  10  and power-on reset circuit  12  outputs the reset signal (S 2 ). In response to the reset signal output from power-on reset circuit  12 , CPU block  14  generates a pseudo random number (S 4 ), which is herein adopted as key data k. CPU block  14  uses key data k as an argument to calculate a value g (k) of a predetermined function g (S 6 ). CPU block  14  rearranges each bit of the key data k and value g (k) in accordance with a predetermined rearrangement method and writes it into variable register  26  (S 8 ). CPU block  14  also sets in a status register (not shown) a flag indicating that data has been written in variable register  26 . When the flag is set in the status register, a ready signal is output on a signal line (not shown). It should be noted that the respective bit lengths of key data k and value g (k) written into variable register  26  and the method of rearranging each bit thereof are items classified between card-type data storage device  10  and terminal device  40  and are not explicitly disclosed for third parties. CPU block  14  uses key data k as an argument to calculate a value f (k) of a predetermined function f (S 10 ). 
     CPU  44  of terminal device  40  receives the ready signal via I/O interface  42  and is thus notified that data has written in variable register  26  at the S 8  step. Terminal device  40  CPU  44  reads the data written in variable register  26  via I/O interface  42  (S 22 ). CPU  44  extracts key data and value g (k) from the read data and uses key data k as an argument to calculate value g (k) of function g which is identical to that used in the S 6  step (S 24 ). CPU  44  compares value g (k) read from variable register  26  with value g (k) calculated by CPU  44  (S 26 ). If the values do not match (NO at S 28 ), CPU  44  stops access to card-type data storage device  10  (S 36 ). If the values match (YES at S 28 ), CPU  44  uses key data k as an argument to calculate value f (k) of function f which is identical to that used in the S 10  step (S 30 ). CPU  44  writes value f (k) into variable register  26  (S 32 ) and writes an unlocking command into command register  24  (S 34 ). 
     When the unlocking command is written into command register  24 , command control block  22  generates an interruption signal. In response to the interruption signal, CPU block  14  compares value f (k) calculated by CPU block  14  with value f (k) written into variable register  26  (S 12 ). If the values match, (YES at S 14 ), CPU block  14  permits access from terminal device  40  in the subsequent process (S 16 ). If the values do not match (NO at S 14 ), CPU block  14  prohibits access from terminal device  40  in the subsequent process and locks data storage device  10  (S 18 ). In other words, any access from terminal device  40  is ignored. 
     Once access from terminal device  40  has been permitted at the S 16  step, the process described below is followed to provide data communication between card-type data storage device  10  and terminal device  40 , as desired. More specifically, when from terminal device  40  a parameter is set in variable register  26  and a command is written into command register  24 , command control block  22  issues an interruption signal to CPU block  14 . In response to the interruption signal, CPU block  14  starts processing. 
     For example, when the command written in command register  24  is a command associated with data transfer, CPU block  14  controls data transfer control block  28  to transfers data. Data transfer control block  28  applies a memory control signal to memory block  18  to allow memory block  18  and data register  30  to write and read data to and from each other. Terminal device  40  writes and reads data to and from memory block  18  and vice versa via data register  30 . 
     The functions f and g described above are each an arithmetic function or a combination of arithmetic functions. Functions f and g may each also be a bit operation for key data k. For example, when key data k is (N+1)-bit data with an i-th bit thereof having a value of ki and value f(k) of function f is (M+1)-bit data with an i-th bit thereof having a value of yi, value f(k) may be calculated in accordance with the following expression (l):                f        (   k   )       =         (         G00       ⋯       G0N           ⋮       ⋰       ⋮             G                 M0         ⋯         G                 M                 N           )                     (         k0           ⋮             k                 N           )       =     (         y0           ⋮             y                 M           )               (   1   )                                
     It should be noted that Gmn is a predetermined value, wherein m=0 to M and n=0 to N. 
     As described above, In card-type storage system  8  the data transmitted from a regular card-type data storage device  10  to a regular terminal device  40  is comprised of key data k and value g (k) with each bit rearranged. Furthermore, neither the respective bit lengths of key data k and value g (k) nor the method of rearranging each bit thereof are disclosed. Thus if a third party could improperly steal communication between data storage device  10  and terminal device  40 , the third party cannot obtain key data k nor obtain a relationship between key data k and value f (k) of function f. Thus the third party cannot construct a false terminal device  40  which transmits value f (k) of function f corresponding to key data k when key data k is received, nor improperly steal data stored in memory block  18  of card-type data storage device  10 . 
     Furthermore, even if a third party attempts to obtain a relationship between the data comprised of key data k and value g (k) with each bit rearranged and value f (k), the third party cannot obtain the bit length of the rearranged data and the third party can thus not find out the number of possible values of the rearranged data. Thus the third party cannot tell how many combinations of the rearranged data and value f (k) should be extracted and the third party will continue to take data endlessly. Thus the third party cannot obtain function f. 
     It is also difficult for third parties to estimate function f from a multiple of the rearrange data and values f (k); for the rearrange data of L,l bits and key data k of M bits, for example, wherein L&gt;M, the rearranged data can have 2 L  values but in effect 2 M  values. Thus the rearranged data has more values that are in effect not taken (or more singularity). Thus function f can hardly be estimated. 
     Thus, card-type storage system  8  of the present embodiment can prevent third parties from readily, improperly stealing data stored in card-type data storage device  10 , resulting in enhancement of data security. 
     Second Embodiment 
     Referring to FIG. 5, a card-type storage system  72  of the second embodiment is comprised of a terminal device  76  writing and reading data to and from a card-type data storage device  74  (described later) and vice versa, and card-type data storage device  74  mounted internal to terminal device  76  to store data. 
     Card-type data storage device  74  and terminal device  76  are similar in hardware configuration to the FIGS. 2 and 3 card-type data storage device  10  and terminal device  40 , respectively, and will thus not be described in that term. 
     Reference will now be made to FIG. 6 to describe a process performed to establish connection between card-type data storage device  74  and terminal device  76 . 
     Card-type data storage device  74  performs the S 2 -S 6  steps. These steps will thus not be described since they are similar to those described with reference to FIG.  4 . After the S 6  step, CPU block  14  of card-type data storage device  74  applies an enciphering function Fs using a key s to encipher a plain text P comprised of key data k and value g (k) to obtain a cipher text C (S 7 ). CPU block  14  writes cipher text C into variable register  26  (S 9 ). After the S 9  step, card-type data storage device  74  performs the S 10 - 16  steps. These steps will not be described since they are similar to those described with reference to FIG.  4 . 
     Cipher text C written into variable register  76  at the S 9  step is read by terminal device  76  CPU  44  via I/O interface  42  (S 21 ). CPU  44  uses a deciphering function Gs using the identical key s used in the S 7  steps to decipher the read cipher text C to obtain plain text P comprised of key data k and value g (k) (S 23 ). It should be noted that deciphering function Gs is an inverse function of enciphering function Fs. Thereafter, terminal device  76  performs the S 24 -S 36  steps, which will not be described since they are similar to those described with reference to FIG.  4 . 
     In card-type storage system  72  described above, if a third party could improperly steal communication between regular card-type data storage device  74  and regular terminal device  76 , the enciphered key data k and value g (k) written in variable register  26  of data storage device  74  can prevent the third party from improperly obtaining the data k and hence a relationship between key data k and value f (k) of function f. Thus the third party cannot construct a false terminal device  76  nor improperly steal data stored in memory block  18  of data storage device  74 . 
     Furthermore, the key data k, value g (k) and enciphered data that have their respective bit lengths undisclosed can prevent a third party improperly attempting to obtain a relationship between the enciphered data and value f (k) from obtaining the number of possible values of the enciphered data, since the third party cannot obtain the bit length of the enciphered data. Thus the third party cannot tell how many combinations of the enciphered data and value f (k) should be extracted and the third party will take data endlessly. Thus the third party cannot obtain function f. 
     Thus, card-type storage system  72  of the present embodiment can prevent third parties from readily, improperly stealing data stored in card-type data storage device  74 , resulting in enhancement of data security. 
     Third Embodiment 
     Referring to FIG. 7, a card-type storage system  82  of the third embodiment includes a terminal device  86  writing and reading data to and from a card-type data storage device  84  (described later) and vice versa, and card-type data storage device  84  mounted internal to terminal device  86  for data storage. 
     Card-type data storage device  84  and terminal device  86  are similar in hardware configuration to card-type data storage device  10  and terminal device  40  described with reference to FIGS. 2 and 3, respectively, and will thus not be described in that term. 
     Reference will now be made to FIG. 8 to describe a process performed to establish connection between card-type data storage device  84  and terminal device  86 . 
     When card-type data storage device  84  is mounted to terminal device  86 , terminal device  86  supplies power to data storage device  84  and power-on reset circuit  12  outputs a reset signal (S 2 ). In response to the reset signal output from power-on reset circuit  12 , CPU block  14  sets a counter i to 0 (S 42 ). It should be noted that counter i is adapted to be provided in RAM  16 . CPU block  14  generates a pseudo random number (S 44 ). It should be noted that an i-th generated pseudo random number is adopted as key data ki. CPU block  14  uses key data ki as an argument to calculate a value gi (ki) of a predetermined function gi (S 46 ). It should be noted that function gi is provided for each value of counter i. CPU block  14  rearranges each bit of the key data ki and value gi (ki) in accordance with a predetermined rearrangement method and writes it into variable register  26  (S 48 ). CPU  14  also sets in a status register (not shown) a flag indicating that data has been written in variable register  26 . When the flag is set in the status register, a ready signal is output on a signal line (not shown). It should be noted that the respective bit lengths of key data ki and value gi (ki) written in variable register  26  and the method of rearranging each bit thereof are items classified between card-type data storage device  84  and terminal device  86  and are not explicitly disclosed for third parties. CPU block  14  uses key data ki as an argument to calculate a value fi (ki) of a predetermined function fi (S 50 ). Function fi is provided for each value of counter i. 
     CPU  44  of terminal device  86  receives the ready signal and is thus notified that key data ki and value gi (ki) have written in variable register  26  at the S 48  step. The data written into variable register  26  is thus read by terminal device  86  CPU  44  via I/O interface  42  (S 62 ). CPU  44  uses read key data ki and an argument to calculate value gi (k) of the identical function gi to that used in the S 46  step (S 64 ). It should be noted that RAM  48  in terminal device  86  is provided with counter i, as in card-type data storage device  84 . Counter i provided for RAM  48  is incremented by one when CPU  44  reads data via I/O interface  42 . Counter i is also adapted to be reset to zero when data storage device  84  is mounted to terminal device  86 . CPU  44  compares value gi (ki) read from variable register  26  with value gi (ki) calculated by CPU  44  (S 66 ). If the values do not match (NO at S 68 ), CPU  44  stops access to card-type data storage device  84  (S 36 ). If the values match (YES at S 68 ), CPU  44  uses key data ki as an argument to calculate value fi (ki) of the identical function fi to that used in the S 50  step (S 70 ). CPU  44  writes value fi (ki) into variable register  26  (S 72 ) and writes an unlocking command into command register  24  (S 34 ). 
     When the unlocking command is written in command register  24 , command control block  22  generates an interruption signal. In response to the interruption signal, CPU block  14  compares value fi (ki) calculated by CPU block  14  with value fi (ki) written in variable register  26  (S 52 ). If the values do not match (NO at S 54 ), CPU block  14  prohibits access from terminal device  86  in the subsequent process and locks data storage device  84  (S 18 ). In other words, any access from terminal device  86  is ignored in the subsequent process. If the values match (YES at S 54 ), CPU block  14  increments counter i by one (S 56 ). CPU block  14  determines whether counter i has reached a predetermined value imax (S 58 ). If counter i has not yet reached value imax (NO at S 58 ), the process from S 44  onwards is repeatedly applied for incremented counter i. If counter i has reached value imax, i.e., if values gi (ki) and fi (ki) compared imax times between data storage device  84  and terminal device  86  match all of the imax times, then card-type data storage device  84  permits access from terminal device  84  in the subsequent process (S 16 ). 
     In accordance with card-type storage system  82  described above, in addition to the function and effect of card-type storage system  8  of the first embodiment, value gi (ki) and value fi (ki) are compared multiple times and key code ki and functions gi and fi are also varied each time. It is thus extremely difficult for third parties to construct a false terminal device  86  and improperly steal data stored in card-type data storage device  84 . 
     Thus, card-type storage system  82  of the present embodiment can prevent third parties from readily, improperly stealing data stored in card-type data storage device  84 , resulting in enhancement of data security. 
     Fourth Embodiment 
     Referring to FIG. 9, a card-type storage system  92  of the fourth embodiment includes a terminal device  96  writing and reading data to and from a card-type data storage device  94  described later and vice versa, and card-type data storage device  94  mounted internal to terminal device  96  for data storage. 
     Card-type data storage device  94  and terminal device  96  are similar in hardware configuration to card-type data storage device  10  and terminal device  40  described with reference to FIGS. 2 and 3, respectively, and will thus not be described in that term. 
     Reference will now be made to FIG. 10 to describe a process performed to establish connection between card-type data storage device  94  and terminal device  96 . 
     Card-type data storage device  94  provides the S 2  and S 42 -S 46  steps, which will not be described since they are similar to those described with reference to FIG.  8 . After the S 46  step, CPU block  14  of data storage device  94  applies enciphering function Fs using key s to encipher a plain text Pi comprised of key data ki and value gi (ki) to obtain a cipher text Ci (S 47 ). CPU block  14  writes cipher text Ci into variable register  26  (S 49 ). After the S 49  step, data storage device  94  provides the S 50 -S 58  steps and the S 16 -S 18  steps, which will not be described since they are similar to those described with reference to FIG.  8 . 
     Cipher text Ci written in variable register  26  at the S 49  step is thus read by terminal device  96  CPU  44  via I/O interface  42  (S 61 ). CPU  44  uses deciphering function Gs using the identical key s to that used in the S 47  step to decipher read cipher text Ci to obtain plain text P comprised of key data ki and value gi (ki) (S 63 ). It should be noted that deciphering function Gs is an inverse function of enciphering function Fs. Thereafter, terminal device  96  provides the S 64 -S 72  steps and the S 34 -S 36  steps, which will not described since they are similar to those described with reference to FIG.  8 . 
     According to card-type storage system  92  described above, in addition to the functional and effect of card-type storage system  72  of the second embodiment, values gi (ki) and fi (ki) are compared multiple times and key code ki and functions gi and fi are varied each time. It is thus extremely difficult for third parties to construct a false terminal device  96  and thereby improperly steal data stored in card-type data storage device  94 . 
     Thus, card-type data storage system  92  of the present embodiment can prevent third parties from readily, improperly stealing data stored in card-type data storage device  94 , resulting in enhancement of data security. 
     Although the above embodiments have been described with respect to card-type storage systems comprised of a card-type data storage device and a terminal device, the above configurations are merely illustrative and any systems are applicable that are comprised of a plurality of processing devices interconnected to implement a predetermined function. 
     Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.