Abstract:
A processor-based automatic alignment device and method for data movement. Data stored in a memory at a first position is partitioned by word boundaries into a first part, a second part and a third part and written to the memory at a second position. The device includes: an internal register, a load combine register, a shifter, a rotator, a store combine register and a mask selector. Data is loaded in and aligned by the device for storing in internal register of a processor. Next, data stored in the internal register is automatically aligned and then written in the memory at an unaligned position.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to the technical field of data processing and, more particularly, to a processor-based structure and method for loading unaligned data. 
   2. Description of Related Art 
   While a processor performs data processing, data alignment may affect the performances of many key operations, such as the operations of string, array and the like. As shown in  FIG. 1 , data to be processed, such as ‘ABCDEFGHIJKL’, normally exceeds the store boundary. As such, before a processor performs any string or array operation on the data, the data must be restored to the aligned format by executing many additional operations firstly. 
   Upon this problem, a typical scheme is that after the data is loaded to the processor, various instructions in the processor are applied for obtaining required data. As shown in  FIG. 2 , partial data ‘ZABC’ at address  100   h  is loaded to register R 16  to shift left by eight bits and remove the letter ‘Z’, then partial data ‘DEFG’ at address  104   h  is loaded to register R 17  to shift right by 24 bits and remove letters ‘EFG’, and finally an OR operation is applied to registers R 16  and R 17  to obtain a result to be stored in register R 16 . At this point, the content of register R 16  is a required data ‘ABCD’. Accordingly, as the cited steps are repeated, partial data ‘EFGH’ and ‘IJKL’ are loaded to registers R 17  and R 18 . 
   As cited, if a required length of unaligned data to be loaded is n words (each having 32 bits), the typical scheme requires 5n instructions to describe load operations and at least 5n instruction cycles to complete the load operations, which needs large memory space for storing required program codes and also increase processor load so as to cause poor performance. 
   Upon this problem, U.S. Pat. No. 4,814,976 granted to Hansen, et al. for a “RISC computer with unaligned reference handling and method for the same” performs the alignment as loading unaligned data and reads a data exceeding the boundary completely by two times. As shown in  FIG. 3 , data ‘ABC’ at addresses  101   h  to  103   h  is loaded to bytes  0 ,  1  and  2  of register r 16 . In this case, byte  3  of register  16  is X (don&#39;t care). Next, data ‘D’ at address  104   h  is loaded to byte  3  of register R 16 . At this point, data ‘ABCD’ to be processed is in register R 16 . Accordingly, as the cited steps are repeated, data ‘EFGH’ and ‘IJKL’ are loaded to registers R 17  and R 18 . 
   As cited, if a required length of unaligned data to be loaded is n words, it needs 2n instructions to describe load operation and at least 2n instruction cycles to complete the load operation. Since read and write are repeated at a same memory position and a same register, the processor pipeline stall can be increased and the bus bandwidth is wasted. Especially to some systems without cache, delay can be obvious. 
   Therefore, it is desirable to provide an improved structure and method for loading unaligned data to mitigate and/or obviate the aforementioned problems. 
   SUMMARY OF THE INVENTION 
   The object of the present invention is to provide a processor-based structure and method for loading unaligned data, which can avoid the prior problem and reduce required instructions for describing load operation and instruction cycles for completing load operation, thereby increasing the performance. 
   In accordance with one aspect of the present invention, there is provided a processor-based method for loading unaligned data. The unaligned data is stored in a memory having a plurality of m-bit words partitioned by word boundaries. The unaligned data is divided by word boundaries into a first part, a second part and a third part. The method includes: a first fetching step, a second fetching step, a first shifting step, a third fetching step, and a seconding shifting step. The first fetching step executes a first instruction to fetch a first word from the memory having the first part. The second fetching step executes a second instruction to fetch a second word from the memory having the second part. The first shifting step combines the first word and the second word to form a first combination and shifts the first combination to a first position. The third fetching step executes a third instruction to fetch a third word from the memory having the third part. The second shifting step combines the second word and the third word to form a second combination and shifts the second combination to the first position. 
   In accordance with another aspect of the present invention, there is provided a processor-based method for loading unaligned data. The unaligned data is stored in a memory having a plurality of m-bit words partitioned by word boundaries. The unaligned data is divided by word boundaries into a first part and a second part. The method includes: a start fetching step, an end fetching step and a first shifting step. The fetch start step executes a first instruction to fetch a first word from the memory having the first part. The fetch end step executes a second instruction to fetch a second word from the memory having the second part. The first shifting step combines the first word and the second word to form a first combination and shifts the first combination to a first position. 
   In accordance with a further feature of the present invention, there is provided a processor-based structure for loading unaligned data. The unaligned data divided by word boundaries into a first part, a second part and a third part is stored in a memory having a plurality of m-bit words partitioned by word boundaries. The structure includes: a load combine register, a shifter, and a controller. The internal register temporarily stores data. The load combine register is coupled to the memory for temporarily storing data read out of the memory. The shifter is coupled to the load combine register and the memory for shifting in accordance with stored address of the unaligned data. The controller firstly fetches a first word from the memory having the first part for storing in the load combine register temporarily, then fetches a second word from the memory having the second part such that the shifter combines the first word and the second word to form a first combination and shifts the first combination to a first position, and finally fetches a third word from the memory having the third part such that the shifter combines the second word and the third word to form a second combination and shifts the second combination to the first position. 
   Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows a schematic view of typical memory arrangement of an unaligned data; 
       FIG. 2  shows a schematic view of program codes for loading an unaligned data in accordance with a prior art; 
       FIG. 3  shows a graph of program codes for loading an unaligned data to a register in accordance with another prior art; 
       FIG. 4  is a block diagram of a processor-based structure for loading unaligned data in accordance with the invention; 
       FIG. 5  is a table of instruction formats in accordance with the invention; 
       FIG. 6  schematically illustrates LCB instruction in accordance with the invention; 
       FIG. 7  schematically illustrates LCW instruction in accordance with the invention; 
       FIG. 8  schematically illustrates LCE instruction in accordance with the invention; 
       FIG. 9  is a table of executing LCB, LCW and LCE instructions in accordance with the invention; 
       FIG. 10  shows an example of the invention; and 
       FIG. 11  shows another example of the invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 4  is a block diagram of a processor-based structure for loading unaligned data in accordance with the invention. As shown, the structure includes a memory  100 , a load combine register (LDCR)  200 , a shifter  300  and a controller  400 . The memory  100  has a plurality of m-bit words partitioned by word boundaries. In this embodiment, m is preferred to be 32, i.e., the memory  100  consists of a plurality of 32-bit words. The unaligned data (ABCDEFGHIJKL) is stored in the memory  100  and divided by word boundaries into a first part  110 , a second part  120  and a third part  130 . 
   The LDCR  200  is coupled to the memory  100  for temporarily storing data read out of the memory  100 . The shifter  300  is coupled to the LDCR  200  and the memory  100  for shifting in accordance with the stored address of the data. The shifting can be a form of shift or rotation. 
   The controller  400  firstly fetches a first word from the memory  100  having the first part  110  for storing in the LDCR  200  temporarily, then fetches a second word from the memory  100  having the second part  120  such that the shifter  300  combines the first word and the second word to form a first combination and shifts the first combination to a first position, and finally fetches a third word from the memory  100  having the third part  130  such that the shifter  300  combines the second word and the third word to form a second combination and shifts the second combination to the first position. 
   Three load instructions, Load Combine Begin (LCB), Load Combine Word (LCW) and Load Combine End (LCE), are defined by the inventive structure so that the controller  400  can generate corresponding control signals. Instruction formats are shown in  FIG. 5 . 
   Instruction LCB [Addr] loads memory content at the stored address Addr to the LDCR  200 . As shown in  FIG. 6 , LCB [ 101   h ] loads the content (ABC) of address  101   h  to the LDCR  200 . 
   As shown in  FIG. 7 , instruction LCW rD, [Addr] firstly combines memory content at the stored address Addr and the content of the LDCR  200 , then shifts the combined content left in accordance with the address Addr, and finally writes the shifted content to register rD. At this point, the memory content at the address Addr is loaded to the LDCR  200 , wherein when Addr=4N (positive integer), no shift is performed; when Addr=4N+1, shifting left by eight bits is performed; when Addr=4N+2, shifting left by 16 bits is performed; and when Addr=4N+3, shifting left by 24 bits is performed. 
   As shown in  FIG. 8 , for instruction LCE rD, [Addr], when Addr=4N, the content of the LDCR  200  is written into register rD directly but memory content at the stored address Addr is not loaded into the LDCR  200 . When Addr is not equal to 4N, the memory content at the stored address Addr and the content of the LDCR  200  are combined to further write to the register rD after shifting left in accordance with the address Addr. At this point, the memory content at the address Addr is loaded to the LDCR  200 , wherein when Addr=4N+1 (N is positive integer), shifting left by eight bits is performed; when Addr=4N+2, shifting left by 16 bits is performed; and when Addr=4N+3, shifting left by 24 bits is performed. 
     FIG. 9  shows a summary table of executing the instructions LCB [Addr], LCW rD, [Addr] and LCE rD, [Addr] under data arrangement of little endian and big endian. As shown in  FIG. 9 , for data ‘abcd’ in the LDCR  200  and data ‘ABCD’ in the memory, s=0 represents Addr=4N, s=1 represents Addr=4N+1, s=2 represents Addr=4N+2, and s=3 represents Addr=4N+3. In this case, 4N=100 is given as an example. 
     FIG. 10  is an example of the invention. As shown, when an unaligned data ‘ABCDEFGHIJKL’ is to load to registers R 16 , R 17  and R 18 , an instruction LCB [ 101   h ] is executed firstly to load content ‘ZABC’ at the stored address  101   h  in the memory  100  to the LDCR  200 . The LDCR  200  has a content ‘ZABC’ ([LDCR]=ZABC) after the instruction LCB [ 101   h ] is executed completely. Next, an instruction LCW R 16 , [ 105   h ] is executed to combine the content ‘ZABC’ of the LDCR  200  and a content ‘DEFG’ of the memory containing the address  105   h  to obtain ‘ZABCDEFG’. Next, the content ‘ZABCDEFG’ is shifted left by eight bits in accordance with the address  105   h  in order to write the content ‘ABCD’ of high 32 bits of the shifted content to register R 16 . Also, memory content containing the address  105   h  is loaded to the LDCR  200  such that after the instruction LCW R 16 , [ 105   h ] is executed completely, the register R 16  has a content ‘ABCD’ and the LDCR  200  has a content ‘DEFG’ ([LDCR]=DEFG). 
   Next, an LCW R 17 , [ 109   h ] is executed to combine the content ‘DEFG’ of the address  105   h  and a content ‘HIJK’ of the memory containing the address  109   h  to obtain ‘DEFGHIJK’. Next, the content ‘DEFGHIJK’ is shifted left by eight bits in accordance with the address  109   h  in order to write the content ‘EFGH’ of high 32 bits of the shifted content to register R 17 . Also, memory content containing the address  109   h  is loaded to the LDCR  200  such that after the instruction LCW R 17 , [ 109   h ] is executed completely, the register R 17  has a content ‘EFGH’ and the LDCR  200  has a content ‘HIJK’ ([LDCR]=HIJK). 
   Finally, an instruction LCE R 18 , [10Dh] is executed to combine the content ‘HIJK’ of the LDCR  200  and a content ‘LZZZ’ of the memory containing the address  10 Dh to obtain ‘HIJKLZZZ’. Next, the content ‘HIJKLZZZ’ is shifted left by eight bits in accordance with the address  10 Dh in order to write the content ‘IJKL’ of high 32 bits of the shifted content to register R 18 . Also, memory content containing the address  10 Dh is loaded to the LDCR  200  such that after the instruction LCE R 18 , [ 10 Dh] is executed completely, the register R 18  has a content ‘IJKL’ and the ‘LDCR’  200  has a content ‘LZZZ’ ([LDCR]=LZZZ). 
     FIG. 11  is another example of the invention. As shown, when an unaligned data ‘ABCD’ is to load to registers R 16 , an instruction LCB [ 101   h ] is executed firstly to load content ‘ZABC’ at stored address  101   h  in the memory  100  to the LDCR  200 . The LDCR  200  has a content ZABC ([LDCR]=ZABC) after the instruction LCB [ 101   h ] is executed completely. 
   Next, an instruction LCE R 16 , [ 105   h ] is executed to combine the content ‘ZABC’ of the LDCR  200  and a content ‘D’ of the memory containing the address  105   h  to obtain ‘ZABCDZZZ’. Next, the content ‘ZABCDZZZ’ is shifted left by eight bits in accordance with the address  105   h  in order to load the content ‘ABCD’ of high 32 bits of the shifted content to the register R 16 . Also, memory content containing the address  105   h  is loaded to the LDCR  200  such that after the instruction LCE R 16 , [ 105   h ] is executed completely, the register R 16  has a content ‘ABCD’ and the LDCR  200  has a content ‘DZZZ’ ([LDCR]=DZZZ). 
   In view of the foregoing, it is known that, if a required length of unaligned data to be loaded is n words, the invention can describe load operations only by (n+1) instructions, which requires only (n+1) instruction cycles to complete the load operations, thereby reducing codes and relatively increasing performance. In addition, repeated read/write does not occur on a same memory or register position, and thus the stall probability of a processor pipeline is reduced. Further, a same memory position is loaded only one time at a pinch, and thus bus bandwidth is saved to reach the best utilization. 
   Although the present invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed.