Abstract:
Improved AC/DC conversion in power supplies having an isolation transformer located between rectified-AC input and DC output leads. The transformer is given a primary winding having one or more taps, and a positive input lead is connected thereto by a corresponding number of intermediate leads, each containing selected components. The improvement not only enables power factor correction (PFC) but also desired adjustment of or control over other operational variables, such as bulk capacitor voltage stress, output regulation, and overall efficiency, often at a reduction in circuit complexity and cost.

Description:
TECHNICAL FIELD 
     This invention relates to AC/DC converters improved with at least one so-called PFC (power factor correction) lead to at least one primary winding tap of an isolation transformer located between circuitry for rectifying input AC and circuitry for outputting DC. 
     BACKGROUND OF THE INVENTION 
     Conventional methods of adequate power factor correction (PFC), especially for consolidated (single-stage) AC/DC converters, include contributions described in U.S. patents and/or in technical reports. 
     Notable patented examples include the following: &#34;Single Conversion Power Factor Correction Using SEPIC Converter&#34; by Fraidlin, Slack and Wadlington in U.S. Pat. No. 5,115,185 (1992)--good power factor but low-frequency ripple in output voltage and slow transient response; also &#34;High Power Factor AC/DC Converter&#34; by Teramoto, Sekine, and Saito in U.S. Pat. No. 5,301,095 (1994)--a PFC corrective design with a sole high-frequency capacitor, but the primary diode undergoes hard switching unsuited to high-frequency operation, while input and load ranges are narrow in the absence of extensive frequency modulation; and, more recently, &#34;Input Harmonic Current Corrected AC-to-DC Converter with Multiple-Coupled Primary Windings&#34; by Ho and Lee in U.S. Pat. No. 5,600,546 (1997)--a single-stage PFC AC/DC converter with one power switch and one magnetic component, its energy-storage capacitor so highly voltage-stressed as to limit power factor to about 0.8, and pulsating input with high switching AC ripple requiring optimal EMI filtration, and with the switching diode undergoing hard switching. 
     Notable examples of contributions to the technical literature include &#34;Integrated High Quality Rectifier-Regulators&#34; by Madigan, Erickson, and Ismail in their 1992 PESC Record article describing so-called BIFRED (and BIBRED)--designs of very good power factor and regulation, but not so good efficiency, and also nearly as bulky as earlier designs; also &#34;A New Family of Single-Stage Power-Factor Correctors with Fast Regulation of the Output Voltage&#34; by Redl, Balogh, and Sokal in their 1994 PESC Record article--teaching PFC correction with a sole diode, but imposing high switching stresses because of deep discontinuous conduction and requiring a large EMI filter, very bulky; and also, more recently, &#34;Single-Stage Single-Switch Isolated Power Supply Technique with Input-Current Shaping and Fast Output-Voltage Regulation for Universal Input-Voltage-Range Operations&#34; by Huber and Jovanovic in their 1997 APEC Proceedings IEEE article--describing a converter reasonably capable of 0.9 power factor and 400 V capacitors but requiring a complicated power transformer, with at least three primary windings, heavily dependent upon transformer leakage inductance, very resistant to adequate control. 
     My present invention relies heavily upon reduction in number of components via intermediate tapping of transformer primary windings. 
     SUMMARY OF THE INVENTION 
     A primary object of this present invention is to simplify PFC (power factor correction) in single-stage AC/DC converter circuitry. 
     Another object of this invention is to enhance the topologies of PFC AC/DC soft-switching converters, as used in power supplies. 
     A further object of the invention is to improve operation of various single-stage AC/DC converters via transformer primary taps. 
     Yet another object is to enable suitable optimization of AC/DC converter circuitry to meet varied goals of power factor correction, output regulation, overall efficiency, and related indexes of merit. 
     A still further object is to economize in both number and cost of circuit elements or components used according to this invention. 
     In general, the objects of this invention are accomplished, in an AC/DC power supply, by connecting at least one PFC lead from a junction with a rectified-AC positive lead to a primary winding of an isolation transformer located between the AC-rectification input circuitry and DC-conversion output circuitry. Such a PFC lead from such positive lead preferably contains a diode in series with a high-frequency inductor. At least one such lead connects to a tap intermediate the ends of the winding. Varying tap location on the winding enables adjustment or optimization of operational variables. 
     The transformer primary winding itself is also connected to a power switch controlled to function as a high-frequency AC voltage source. The series-connected switch and primary winding are bridged together as a unit by a smoothing (bulk or energy-storage) capacitor connected from a negative (or neutral) rectified-AC input line to the top (high end) of the same primary winding. 
     A secondary winding of the transformer connects to DC-conversion output circuitry, which may be of substantially any known conventional type, such as boost, buck, buck-boost, Cuk, flyback, forward, SEPIC, or Zeta, for example. 
     Other objects of this invention, together with methods and means for attaining the various objects, will become apparent from the following description and the accompanying diagrams of at least one embodiment, presented by way of example rather than limitation. 
     SUMMARY OF THE DRAWINGS 
     FIG. 1 is a schematic circuit diagram of a single-stage AC/DC converter of this invention represented in generalized form; 
     FIG. 2 is a specific flyback embodiment of the FIG. 2 circuit; 
     FIG. 3 is a time graph of typical line voltage and average line current waveforms of the FIG. 2 embodiment; 
     FIG. 4 is a time graph of various internal operating voltages and currents in the same embodiment under FIG. 3 DCM conditions; 
     FIG. 5A is a time graph of the current waveform in inductor L1 for a specific embodiment according to FIG. 3A at full load; and 
     FIG. 5B is a time graph of the current waveform in inductor L1 for the FIG. 5A specific embodiment operating at only half load. 
     FIG. 6A is a conventional forward converter variant of the FIG. 3A embodiment with a multiple-input-winding transformer; 
     FIG. 6B is a variant of the FIG. 6A forward converter embodiment, wherein the secondary (output) winding is center-tapped; 
     FIG. 7A is a multiple-tap input winding variant of the general FIG. 1 embodiment; and 
     FIG. 7B is a time graph of typical line voltage and average line current waveforms of the FIG. 7A embodiment. 
     FIG. 8A is a dual PFC lead embodiment with filter inductor (Lf) and generalized lower PFC impedance and transformer connection; 
     FIG. 8B is a specific flyback converter version of the FIG. 8A embodiment, with the PFC lead particularized as to impedance and transformer connection; 
     FIG. 9A is a multiple-tap version of such flyback converter; 
     FIG. 9B is a forward converter version otherwise like FIG. 9A; 
     FIG. 10A is a variant of the multiple-tap flyback embodiment of FIG. 9A, including a controllable saturable (non-linear) inductor; 
     FIG. 10B is a variant of the multiple tap forward embodiment of FIG. 9B, including a controllable saturable (non-linear) inductor. 
    
    
     DESCRIPTION OF THE INVENTION 
     FIG. 1 shows, in schematic circuitry diagram form, generalized single-stage AC/DC converter of my design, wherein the intermediate (or PFC) lead is connected to a primary winding tap of an isolation transformer Tr. Such showing includes DR rectifier circuitry at the left, with its positive and negative (or neutral) output lead pair proceeding rightward. The positive lead contains inductor L1, then diode D1, then connects to the designated tap on a tapped primary winding of transformer Tr, the winding having N P1  turns in its upper part and N P2  turns in its lower part. Energy-storage (bulk or smoothing) capacitor Cb connects between the high end of the primary winding and the negative lead, whereas high-frequency power switch S connects between the negative lead and the low end of the primary winding. At the far right, output resistor Ro represents an external electrical load for the power supply, whereas other parts of the DC/DC conversion circuitry are omitted to simplify the illustration. Although elimination of diode D1 would aid overall efficiency by reducing conduction loss, in practice D1 often is essential to preclude a severe reverse-recovery problem where the rectifying diodes in bridge DR are slow and/or where capacitors are used after the bridge to reduce EMI (electromagnetic interference). For this embodiment the bridge preferably has two fast-rectifying diodes. Any EMI capacitors should be inserted ahead of the bridge. 
     FIG. 2 is a more detailed example of the first embodiment of this invention in flyback converter form. If capacitor C b  is large enough so that its voltage V Cb  is equivalent to a constant-voltage source having a value exceeding the peak line voltage, L1 functions in discontinuous conduction mode (DCM). 
     When in DCM, the converter has two operating modes depending upon instantaneous line voltage V In . Mode I occurs when V In  is less than (N P2  /N P )V Cb  (noting that N P  =N P1  +N P2 ), whereas Mode II occurs whenever V In  is greater than (N P2  /N P )V Cb . 
     During Mode I, the actual voltage at point A always exceeds line voltage, so D1 is reverse-biased, and no current flows through L1--much as in a conventional flyback converter; but in Mode II the converter draws current from the rectified AC source so the operation differs a bit. 
     FIG. 3 shows graphically the resulting operation. Mode I gives way to Mode II when the line voltage exceeds the tapped voltage and resumes only when the line voltage subsequently falls below the tapped voltage. The line current (I In ) is apparent in Mode II. 
     FIG. 4 shows graphically the three topological states occurring in each switching cycle, designated by times t0, t1, t2; t0&#39; (etc.). 
     [t0-t1] Power switch S is ON during this interval, as noted and as indicated by the V gs  increase to a given higher value (S ON). V A , the voltage at point A equals (N P2  /N P )V Cb  --whereupon the L1 current increases at a rate equal to [V in  -(N P2  /N P )V Cb )]/L1. The flyback transformer is charged by both the Cb voltage and the input line voltage. 
     [t1-t2] Power switch S turns off at time t1, and diode DR1 in series with secondary winding N S  conducts. The voltage at A is clamped to [V Cb  +(N P1  /N S )V o  ]--whereupon the L1 current decreases at a rate equal to [V Cb  +(N P1  /N S )V o  -V In  ]/L1. During this interval Cb is charged by the L1 current. If the flyback transformer operates in CCM, the voltage at point A remains unchanged during OFF time. 
     [t2-t0&#39;] When t2 is reached, D1 current (marked I L1 ) becomes zero and D1 becomes reverse-biased. The rectifier is thus shown to operate with zero-current switching. The transformer continues to deliver energy to the output load (Ro--shown previously). At time t0&#39;, switch S turns on again, and a new cycle occurs likewise. 
     The foregoing analysis assumes that smoothing capacitor Cb is large enough to be considered an ideal DC voltage source without line frequency ripple, but a real capacitor will have significant ripple, and its voltage will equal the rectified line voltage at about the line peak level. Consequently, the converter has another operating mode during which L1 operates in CCM during part of a line cycle. 
     FIGS. 5A and 5B show representative wave-forms experimentally obtained for a particular 65 W (19 V, 3.4 A) converter according to FIG. 3A operating at full load and at half load, respectively. 
     The main circuit elements of such converter have the following values: S, IRF740; L1, 170uH; Cb, 150uF/200 V; N P1  :N P  =1:2; N P  :N S  =5:1; D1, UES306; and DR1, 16CTQ100. 
     From these diagrams (FIGS. 5A and 5B) it is apparent that L1 operates in CCM at full load when the line voltage is near its peak. As the load current decreases, the Cb voltage increases, and L1 operates in DCM whenever current is being drawn from the input. 
     Using simple fixed-frequency control (fs=100 kHz), the converter tightly regulates the output voltage from no load to full load over the entire input range. Over the line and load range, the maximum voltage on Cb, occurring at high line and about half load, is 192 V. At full load and 115 VAC out, measured efficiency is 90%, and power factor is 0.87--fine for single-stage PFC converters. 
     Another like converter was tested with a 90-264 VAC (universal) input range, and these values: S, IRFPC40; L1, 183uH; Cb, 150uF/400 V; N P1  :N P  =28:55; N P  :N S  =55:9; D1, UES306; and DR1, 16CTQ100. At full load, measured power factors at 115 and 230 VAC, respectively, were 87.5% and 88.5%. The maximum voltage stress on Cb (which occurs at 264 VAC input and 0.5% load) is only about 382 V. 
     For a given N P1  /N P  ratio, when the L1 value increases, the efficiency increases, the bulk capacitor voltage and input switching current ripple decrease, while the power factor decreases, For a given L1 value, a larger N P1  /N P  ratio leads to higher power factor but lower efficiency and higher Cb voltage stress. For most practical purposes the overall performance of the converter is deemed optimum when the N P1  /N P  ratio is between about 1/4 and about 3/4, not to exceed four-fifths. When the corresponding winding ratio is 1/2, the converter of the FIGS. 5A and 5B waveforms can provide a power factor of about 0.9 and very good efficiency, while keeping Cb voltage well below 400 V for universal input. 
     FIGS. 6A and 6B show schematically, in circuit diagram form, two single-stage forward AC/DC converters embodying this invention likewise but having a transformer with a second primary winding reverse-wound (with N P3  turns) for resetting the transformer--without requiring or utilizing another high-frequency switch. 
     FIG. 6A shows such an embodiment of the present invention with an intermediate tap (optionally a centertap) connection to the primary winding, utilizing customary forward converter circuitry also including a conventional secondary winding with N S  turns. 
     FIG. 6B shows a similar embodiment with centertapped secondary winding having N S1  turns and N S2  turns in its respective halves. 
     FIG. 7A shows schematically, in like circuit diagram form but generalized by omission of the output circuitry components, a variant of the embodiment of FIG. 2 extended to a double-tapped winding on its transformer. A pair of parallel PFC leads connect respectively to the two (interior) taps. The first such lead includes inductor L1 and diode D1 in series from the positive lead to the first tap (junction of N P1  and N P2 ), whereas the second such lead includes inductor L2 and diode D2 in series from the positive lead to the second tap (junction of N P2  and N P3 ). 
     As was noted previously, the selection of a primary windings ratio involves a trade-off between power factor and voltage stress of Cb. However, addition of the second intermediate (or PFC) lead provides a designer with greater flexibility, by enabling L2 to be selected significantly larger than L1 and thereby to achieve close to a power factor of 0.95 while still keeping V Cb  below 400 V for universal input applications. 
     FIG. 7B shows graphically the resulting operation of the power supply of FIG. 7A (much as FIG. 3 did for the apparatus of FIG. 2). For this example, two taps are put at respective junctions of three equal parts of the primary winding of the FIG. 7A embodiment. 
     FIG. 8A shows schematically, in circuit diagram form, a dual PFC lead embodiment differing from previous embodiments in having a high-frequency or filter inductor (Lf) present. This showing simply generalizes the impedance of the intermediate (or lower) PFC lead and its transformer connection, as well as the conversion circuitry. Thus, Zn stands for any of various impedance components, such as a capacitor or a diode, either alone or in series with an inductor. It will be understood that node A on that lead (corresponding to node B on the upper PFC lead) is to be extended to the right (arrow) for connection to a node acting as a high-frequency AC source, as at an end (or within) its transformer&#39;s primary winding, to which the high-frequency switch is connected. 
     FIG. 8B is a flyback converter example of the more generalized embodiment of FIG. 7B, distinguished by having only diode D1 in the PFC lead to node A--and on to a connection with the junction of high-frequency power switch S and low end of the primary winding. This embodiment exhibits higher efficiency than a predecessor AC/DC converter wherein the other (or higher) PFC lead connects to the high end of the first (or upper) winding of the transformer--instead of tapping thereinto as shown in FIG. 8A and here. 
     FIGS. 9A and 9B show schematically, in circuit diagram form, specific embodiments of generalized embodiment 8A of this invention, each with the transformer primary winding having two taps. FIG. 9A illustrates a flyback converter, and FIG. 9B a forward converter. With smoothing inductor Lf present, the upper PFC lead includes diode D on the way to node B--and on to the upper of the two taps, at the junction of winding portions N P1  and N P2 , whereas the lower PFC lead includes both inductor L1 and diode D1 in going to node A. The latter lead goes onward to the other (lower) of the two taps, at the junction of respective winding portions N P2  and N P3 . 
     As with the converters described above, selection of the L1 and Lf values and the tap locations involves trade-offs, such a between power factor and bulk capacitor voltage stress. For instance, as the L1 inductance decreases, or the tap node A moves lower, power factor increases, but the capacitor stress also increases. In order to improve power factor without overstressing the capacitor voltage, the present invention implements L1 as a non-linear inductor (with varying inductance values, as compared with the unvarying inductance values of a linear inductor. Then at nominal input voltage, L1 preferably has a relatively low inductance commensurate with a good power factor. At high line and light load, where maximum bulk capacitor voltage stress occurs, L1 should have a relatively larger inductance value in order to suppress such capacitor voltage stress. Although the power factor may degrade significantly when the value of L1 inductance increases at high line and light load, PFC is not a prime requisite for most power supplies under such circumstances. 
     A simple way of controlling L1 inductance range is to use a series connection of a linear inductor (a minimum inductance value) and a controllable saturable inductor, but FIGS. 10A and 10B illustrate respective flyback and forward converter embodiments using a somewhat simpler implementation: a non-linear inductor, specifically a saturable reactor (magnetic amplifier). 
     FIGS. 10A and 10B show saturable reactor L1 having a control winding to control its reset current. Vc is the control voltage source, Q1 is a transistor to control the reset current of L1, and Dz is a zener diode that sets the threshold voltage to turn on Q1. 
     When input voltage is low or load current is heavy, transistor Q1 is off (non-conductive) because the bulk capacitor voltage is too low to turn Q1 on. Once Q1 is turned on, the control winding of L1 starts to provide reset to L1 during the power switch S OFF time. Then L1 becomes unsaturated (with very high inductance value) and can block a certain amount of volt-seconds when S is turned ON again in the next switching cycle. This increases the equivalent inductance of L1 and, thus, can effectively suppress the bulk capacitor voltage stress. Proper selection of Q1 gain and R1, R2 resistor values, can limit the maximum bulk capacitor voltage to a value only slightly higher than the threshold voltage of Dz. 
     The present invention has been illustrated and described here in embodiments including single-tapped and multi-tapped primary windings of the customary isolation transformer, and with corresponding single and multiple intermediate (conveniently designated here as PFC) leads from the positive rectified AC input. 
     The invention is adapted to functioning with these converters: boost, buck, buck-boost, Cuk, flyback, forward, SEPIC, and Zeta. Such an adaptation for several of them has been shown and described. 
     This invention greatly enhances the ability of a power supply designer to optimize a mix of pertinent characteristics, such as number and size of circuit components, power factor, soft-switching, output regulation, overall efficiency (power out/power in), bulk capacitor voltage stress, etc. 
     The various advantages and benefits of the present invention will become even more apparent to designers undertaking to practice it, and to the purchasers and users of power supplies so designed. 
     Preferred embodiments and variants have been suggested for this invention. Other modifications may be made, as by adding, combining, deleting, or subdividing components or steps, while retaining all or at least some of the advantages and benefits of the present invention--which itself is defined in the following claims.