Abstract:
Method and circuitry for efficiently boosting voltage for low power supply applications. In one embodiment a phase boosting circuit that boosts a clock signal to substantially twice the power supply voltage level in a single half-cycle is implemented. The circuit eliminates the need for depletion transistors and can thus be implemented using conventional complementary metal-oxide-semiconductor (CMOS) fabrication processes. A novel voltage summing circuit allows the phase doubler to achieve greater boosting capability for applications with ultra low power supply voltages.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates in general to integrated circuits, and in particular to a voltage boost circuit that provides efficient voltage boosting for circuits operating at lower power supply voltages. 
     Certain integrated circuit applications require internally generating a secondary voltage source that is often larger in magnitude than the primary externally supplied power source. For example, some non-volatile memory circuits, such as electrically erasable programmable read only memories (EEPROMs), that may use a single power supply voltage of, for example, 3.5 volts, also require a programming or erase voltage that is much larger in magnitude (e.g., 12 volts). Voltage multiplying or charge pump techniques have been developed to internally generate the higher voltage from the primary supply voltage. Charge pump circuits take advantage of charge storing capability of capacitors to, for example, double the level of a primary supply voltage by bootstrapping. A typical charge pump circuit may include transistors that transfer charge to one or more capacitors in response to an oscillating (or clock) signal. In some implementations, the charge pump circuit requires non-overlapping clock signals whose voltage levels are themselves boosted to higher than power supply level. The higher the boosted level of the clock signal, the faster the charge pump can give rise to the target output voltage level. 
     One known circuit implementation for generating boosted clock signals for charge pumps is shown in FIG.  1 . The signal at the output node, OUT, is discharged to ground by n-channel transistor Q 1  when VDIS is high. When VDIS goes low, transistor Q 1  turns off and p-channel transistor Q 3  turns on. A depletion mode (negative Vt) transistor Q 2  operates to isolate OUT from transistor Q 3 . During the first half of the clock cycle, signal VPCH turns on transistor Q 2  allowing OUT to get precharged up to the power supply voltage Vcc. During the second half of the clock cycle a boost signal VBT is applied to one terminal of pump capacitor Cp raising the voltage level at OUT from Vcc up toward twice Vcc. The negative threshold voltage of depletion transistor Q 2  allows output voltage OUT to swing above the precharge voltage. The operation of this circuit is illustrated by the timing diagram of FIG.  2 . 
     There are a number of drawbacks with this type of boosting circuit. First, the process must provide for a depletion mode transistor, which is not readily available in conventional CMOS fabrication processes. Second, the efficiency of the circuit is reduced by the fact that pumping occurs only during a portion of the clock half-cycle, as opposed to the entire half-cycle. Current leakage through the depletion transistor further reduces the circuit efficiency, where the output voltage can get close to but not quite double the power supply voltage. This effect is further exacerbated at lower power supply voltages where it becomes increasingly difficult to fully turn off the depletion transistor. At lower power supply voltages, therefore, this circuit becomes ineffective and ultimately non-functional. 
     There is a need for a voltage boosting circuit that operates efficiently at lower power supply voltages. 
     SUMMARY OF THE INVENTION 
     The present invention provides method and circuitry for efficiently boosting voltage for low power supply applications. In a specific embodiment, the present invention provides a phase boosting circuit that boosts a clock signal to substantially twice the power supply voltage level in a single half-cycle. The circuit eliminates the need for a depletion transistor and can thus be implemented using conventional complementary metal-oxide-semiconductor (CMOS) fabrication processes. A novel voltage summing circuit allows the phase doubler of the present invention to achieve greater boosting capability for applications with ultra low power supply voltages. 
     Accordingly, in one embodiment, the present invention provides a voltage boosting circuit having an input that receives an input signal and an output that generates a boosted output signal, the circuit including a pull-down transistor coupled between the output of the circuit and a low potential and having an input coupled to the input of the circuit; a charge transfer transistor coupled between a precharge node and the output of the circuit and having an input coupled to the input of the circuit; a precharge transistor coupled between a power supply and the precharge node and having an input coupled to the output of the circuit; a capacitive element having a first terminal coupled to the precharge node; and an inverter having an input coupled to the input of the circuit and an output coupled to a second terminal of the capacitive element. 
     In another embodiment, the present invention provides a low power voltage boosting circuit the includes two voltage boosting circuits as described in the preceding paragraph, whose outputs are capacitively summed by a third boost circuit, wherein the third boost circuit includes a pull-down transistor, a charge transfer transistor and a precharge transistor coupled as described above. 
     A better understanding of the nature and advantages of the voltage boosting circuit according to the present invention will be gained with reference to the detailed description below and the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit schematic of a prior art phase boost circuit; 
     FIG. 2 is a timing diagram illustrating the operation of the phase boost circuit of FIG. 1; 
     FIG. 3 is an exemplary circuit implementation for a voltage boosting circuit according to a specific embodiment of the present invention; 
     FIG. 4 is a timing diagram illustrating the operation of the voltage boost circuit of FIG. 3; and 
     FIG. 5 is an exemplary circuit implementation for a voltage boosting circuit according to another specific embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 3, there is shown an exemplary circuit implementation for a voltage boost circuit  300  according to the present invention. In this embodiment, the voltage boosting technique is employed as a phase doubler for charge pump circuits such as those used in EEPROM devices. It is to be understood, however, that the technique of the present invention may be employed in other types of circuits requiring voltage boosting. Broadly, voltage boost circuit  300  includes a pump capacitor Cp, one terminal of which, at node N 1 , is precharged to the power supply voltage Vcc during one phase (e.g., low half-cycle) of the input clock signal. During the other phase (e.g., high half-cycle) of the clock, the voltage at node N 1  is boosted by an amount equal to Vcc to achieve a doubling of the clock level. The boosted signal is transferred to the output by a charge transfer transistor M 4 . To accomplish this efficiently, circuit  300  includes an n-channel pull-down (or discharge) transistor M 3  that connects between the output node OUT and ground, with its gate terminal driven by the input clock signal IN. A p-channel precharge transistor M 5  connects between node N 1  and the power supply Vcc. The gate terminal of precharge transistor M 5  is driven by the output signal fed back from output node OUT. The charge transfer transistor M 4  connects between node N 1  and output node OUT, and has its gate driven by the input clock signal IN. Charge pump capacitor Cp connects between node N 1  and node N 2 , where node N 2  is the output of a CMOS inverter  302 . CMOS inverter  302  is made up of a p-channel pull-up transistor M 2  and an n-channel pull-down transistor M 1 . The input of inverter  302  is also driven by the input clock signal IN. 
     The operation of voltage boost circuit  300  will be described below in connection with the timing diagram shown in FIG.  4 . When the input clock signal IN is high, both n-channel transistors M 1  and M 3  are turned on pulling OUT and node N 2  down to ground, respectively. With OUT at ground, precharge transistor M 5  turns on pulling node N 1  up to Vcc. Capacitor Cp is thus charged to Vcc. When the clock signal IN transitions low, n-channel transistors M 1  and M 3  turn off, and p-channel transistors M 2  and M 4  turn on. The conductive channel of transistor M 4  transfers the charge from node N 1  to output node OUT pulling it up to Vcc. As OUT rises to Vcc, p-channel precharge transistor M 5  turns off isolating node N 1  from Vcc. At about the same time, the conductive channel of p-channel transistor M 2  pulls node N 2  up toward Vcc. The Vcc jump at node N 2  is capacitively coupled to node N 1 , raising the potential at node N 1  to about 2Vcc. The 2Vcc level is transferred to output node OUT via p-channel transistor M 4 . In this fashion, the voltage level at OUT is doubled within one half cycle of the input clock signal. 
     There are a number of features of the present invention that enables voltage boosting circuit  300  to double the clock phase efficiently. The exemplary circuit implementation shown in FIG. 3 assumes an n-well CMOS process where the P-channel transistors are formed inside an n-type well region. Thus, the body (or well) terminal of the p-channel transistors can be separately biased. Normally, the body terminals (n-well) of the p-channel transistors are tied to the power supply Vcc, as is the case for p-channel transistor M 2  in inverter  302 . Body terminals  304  and  306  of p-channel transistors M 5  and M 4 , however, are tied to node N 1  instead of Vcc. This ensures that when the voltage at node N 1  rises above Vcc, the inherent p-n junctions, which are formed between the source (p+)/drain (p+) and body (n-well) of transistors M 4  and M 5 , do not become forward biased. Otherwise, the voltage level at node N 1  would be limited to one diode drop (Vd) above Vcc. 
     Care is also taken to make sure that when node N 1  is charged to 2Vcc, p-channel transistor M 4  transfers the charge to output node OUT as quickly as possible so that the gate voltage of p-channel transistor M 5  does not at any point drop below the potential at node N 1 . That is, for transistor M 5  to perform its isolating function properly, the rise in voltage at its gate terminal must not lag that of node N 1 . Proper layout techniques can ensure that the delays through the interconnect lines provide the correct timing. 
     For circuit applications with ultra low power supply voltage, the present invention offers and alternative embodiment wherein boosted outputs of multiple boost circuits of the type shown in FIG. 3 are summed together to achieve an even higher boosted voltage. One exemplary circuit implementation for this embodiment is shown in FIG.  5 . In this embodiment, two boost circuits  300 - 1  and  300 - 2  of the type shown in FIG. 3 each generate 2Vcc at their respective outputs OUT 1  and OUT 2 . Outputs OUT 1  and OUT 2  are then capacitively coupled, via capacitors C 1  and C 2 , to a third boost circuit  500 . Boost circuit  500  is a modified version of boost circuit  300  and includes the second (or output) stage of boost circuit  300 . Boost circuit  500  operates essentially the same as circuits  300  except that it includes two pump capacitors C 1  and C 2  each of which receives an already boosted signal at its first (or input) terminal. The two capacitors C 1  and C 2  form a summing network and in combination with circuit  500  operate to further boost the already boosted and summed signals. In other embodiments, more than two boost circuits  300  can be combined in a similar fashion to provide for additional boosting of the output voltage. It is also possible to achieve further boosting of a signal by combining multiple circuits of the type shown in FIG.  5 . 
     In conclusion, the present invention provides circuit techniques for efficiently boosting voltages for circuits operating with low power supply voltages. The circuit of the present invention can be implemented using conventional CMOS processes. While the above provides a complete description of specific embodiments of the present invention, it is possible to use various alternatives, modifications and equivalents. For example, one may use a p-well CMOS process with the polarity of the transistors changed from n-channel to p-channel and vice versa. Also, similar circuit techniques may be used to generate a high negative voltage. The pump capacitors may be made of any type of capacitive element including poly capacitors or gate capacitance of MOS transistors. Therefore, the scope of the present invention should be determined not with reference to the above description alone but should, instead, be determined with reference to the appended claims along with their full scope of equivalents.