Abstract:
A method is described for checking masks used for the ion implantation steps in the manufacture of semiconductor integrated circuit element wafers before these masks are used for wafer processing. The masks being checked are segmented and the tone, clear or dark, is described by a numerical or logical value assigned to each segment. Mathematical operations on the data representing each mask are carried out and the results are compared with values expected from masks which are error free. Results From the mathematical operations on data representing masks which do not agree with the expected results indicate a high probability of error in those masks. The masks are then checked carefully and errors corrected before using the masks in wafer processing.

Description:
BACKGROUND OF THE INVENTION 
     (1) Field of the Invention 
     The invention relates to a method of checking mask patterns to prevent mask tone errors from causing wafer defects and more particularly to using digital mask data to prevent mask tone errors. 
     (2) Description of the Related Art 
     This invention uses digital data describing the clear and dark areas of the masks used in semiconductor wafer manufacturing to check for mask errors before the masks are used in wafer processing. The digital data of different masks is combined in a predetermined manner and the results are checked against expected values. Unexpected results indicate a high probability of mask error. 
     In U.S. Pat. No. 5,436,097 to Norishima et al. describes a method of mask checking that uses resistance measurements of a conductive film deposited in a test pattern. The test pattern is formed using different rotational orientations and the resistance measurements for the different orientations are compared. This method checks the aligning equipment and the optical system used and is quite different from the method described in this invention. 
     SUMMARY OF THE INVENTION 
     The manufacture of integrated circuit elements require a large number of process steps using masks. For integrated circuit elements having devices such as complimentary metal oxide semiconductor field effect transistors, CMOS devices, or the like these process steps often include ion implantation for N -   wells, P -   wells, N +   source/drain regions, P +   source/drain regions and the like. Mask errors, such as in masks used for ion implantation, can form defects in semiconductor wafers which will not be detected until substantial process time and capability have been expended on the defective wafers. Identification of mask errors before the defective masks have been used to process wafers will result in considerable savings in process time., process capability, and cost. 
     It is a principal objective of this invention to provide a method for checking masks for defects prior to using the masks for wafer processing. 
     This objective is achieved by performing logical comparisons of the tone, clear or dark, of the various masks used for the ion implantation steps of the wafer processing. The digital data required for these comparisons are available from the mask design data. The logical comparisons are compared with expected results. If the logical comparisons produce the expected results there is a high probability that the masks are correct and the wafer processing is continued. If the logical comparisons do not produce the expected results there is a high probability that the masks are defective and the masks are subjected to a thorough technical analysis before being used to process wafers. Errors discovered by the technical evaluation are corrected and the logical comparisons are performed again. If the logical comparisons now produce expected results the wafer processing is continued. If the logical comparisons again fail to produce expected results the thorough technical analysis, mask error correction, and logical comparison is repeated until the expected results are achieved. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a top view of a mask used for ion implantation. 
     FIG. 2 shows a cross section view of a mask used for ion implantation. 
     FIG. 3 shows a top view of a mask used for ion implantation showing division of the mask into segments. 
     FIG. 4 shows a cross section view of a CMOS device using both a P -  well and an N -   well. 
     FIG. 5 shows a cross section view of a CMOS device using an N -   well. 
     FIG. 6 shows a cross section view of a CMOS device using a P -   well. 
     FIG. 7 shows a flow diagram of the mask checking method of this invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Refer now to FIGS. 1-7, there is shown an embodiment of the mask checking method of this invention. FIG. 1 shows a top view of a typical mask used for ion implantation steps in integrated circuit element fabrication. The mask has transparent regions 12 and opaque regions 10. The opaque regions are indicated by diagonal shading in FIG. 1. The mask regions are described according to the mask tone wherein the tone of the transparent regions is clear and the tone of the opaque regions is dark. FIG. 2 shows a cross section of the mask shown in FIG. 1 along the section line 2-2&#39; showing the regions of clear tone 12 and dark tone 10. The mask is formed on a transparent substrate 14. This discussion of the mask will use the tone descriptions clear and dark to describe and analyze the mask. Polarity is also used to describe the masks wherein polarity is the inverse of tone. 
     FIG. 3 shows the top view of a mask laid out on X-Y co-ordinates. The mask has transparent regions 12 and opaque regions 10. The opaque regions 10 are indicated by diagonal shading in FIG. 3. In the X direction the mask is divided into I divisions where I is a positive integer. In the Y direction the mask is divided into J divisions, where J is a positive integer. The mask then has M segments, where M=I×J, and each segment is either clear or dark. The mask shown in FIG. 3 has clear regions 12 and dark regions 10 so that the segment at the ij co-ordinate 18 is clear and the segment at the IJ coordinate 20 is dark. In this example I is 6780 and J is 6600 so that the mask is divided into 44,648,000 segments. A logical one is assigned to clear segments 18 and a logical zero is assigned to dark segments 20. In this manner the mask is described digitally. If greater resolution is required the number of segments can be increased. If the segments are numbered from 1 to M the segment having a particular number in one mask will have the same relative position as the segment having the same number in another mask. This digital data is already available from the mask design data. 
     Refer now to FIG. 4, there is shown a cross section of two complimentary metal oxide semiconductor devices using a P -   well 32, an N -  well 30, and a P channel stop or field region 40 located under a part of the field oxide isolation region 38. N +  source/drain regions 34 are formed in the P -   well 32 and P +   source/drain regions 36 are formed in the N -   well 30. The P -   well 32, N -   well 30, P field region 40, N +   source/drain regions 34, and P +  source/drain regions 36 are formed using masks and ion implantation. As can be seen from FIG. 4 there should be very little overlap of the clear regions or the dark regions of the P +   source/drain mask and of the N +   source/drain mask, of the N -   well mask and the P field mask, of the N -   well mask and the P -   well mask, or of the N +   source/drain mask and the N -   well mask. Also as seen in FIG. 4, there should be a large overlap of the clear regions and the dark regions of the P +  source/drain mask and the N -  well mask. 
     A set of M index numbers A 1 , A 2 , A 3 , . . . , A M  are defined, one index number for each of the M segments of the P -  well mask where the index number corresponding to a clear region has a value of 1 and the index number corresponding to a dark region has a value of 0. A similar set of M index numbers B 1 , B 2 , B 3 , . . . , B M  are defined, one index number for each of the M segments of the N -  well mask. Index numbers C 1 , C 2 , C 3 , . . . , C M  are defined for each of the M segments of the P field mask; index numbers D 1 , D 2 , D 3 , . . . , D M  are defined for each of the M segments of the P +  source/drain mask; and index numbers E 1 , E 2 , E 3 , . . . , E M  are defined for each of the M segments of the N +   source/drain mask. In each case the index number for a dark region is 0 and the index number for a clear region is 1. 
     Next a first index ratio, R 1 , second index ratio, R 2 , third index ratio, R 3 , fourth index ratio, R 4 , and fifth index ratio R 5  are defined according to the following equations: 
     
         R.sub.1 =(D.sub.1 ×E.sub.1 +D.sub.2 ×E.sub.2 +D.sub.3 ×E.sub.3 +. . . +D.sub.M ×E.sub.M)/M, 
    
     
         R.sub.2 =(B.sub.1 ×C.sub.1 +B.sub.2 ×C.sub.2 +B.sub.3 ×C.sub.3 +. . . +B.sub.M ×C.sub.M)/M, 
    
     
         R.sub.3 =(B.sub.1 ×A.sub.1 +B.sub.2 ×A.sub.2 +B.sub.3 ×A.sub.3 +. . . +B.sub.M ×A.sub.M)/M, 
    
     
         R.sub.4 =(E.sub.1 ×B.sub.1 +E.sub.2 ×B.sub.2 +E.sub.3 ×B.sub.3 +. . . +E.sub.M ×B.sub.M)/M, and 
    
     
         R.sub.5 =(D.sub.1 -B.sub.1 +D.sub.2 -B.sub.2 +D.sub.3 -B.sub.3 +. . . +D.sub.M -B.sub.M)/M. 
    
     In accordance with the clear and dark region overlap expected described above it is then expected that R 1 , R 2 , R 3 , R 4 , and R 5  will be small compared to 1. If R 1 , R 2 , R 3 , R 4 , and R 5  meet this expectation there is a good probability that the masks are correct. If R 1 , R 2 , R 3 , R 4 , and R 5  are different than expected there is an almost certainty that there is a mask error and the masks must be thoroughly analyzed before processing any semiconductor wafers. For this embodiment R 1 , R 2 , and R 3  must be less than 0.05; and R 4  and R 5  must be less than 0.10. 
     Refer now to FIG. 7, there is shown the flow diagram of the method of checking mask quality of this invention. A circuit design 60 and a technical analysis 62 results is mask design data 64 which provides the index numbers described above. A mask data check 82 comprises forming the first, second, third, fourth, and fifth index ratios, R 1 , R 2 , R 3 , R 4 , and R 5  ; which are compared with the expected values of the index numbers of less than 0.05 for R 1 , R 2 , and R 3  ; and less than 0.10 for R 4  and R 5 . If the index numbers are not within the expected range the technical analysis 62 is repeated and the masks are corrected. If the index numbers are as expected the mask fabrication 66 is completed and the masks are used in wafer processing 68. 
     At the step of wafer probe testing 70 if the evaluation of the wafers 72 indicates the wafers are good the wafer processing continues 74. If the wafers do not test good the wafers are scrapped 76 and the technical analysis 62 is repeated. This process flow allows mask errors to be discovered and corrected early in the process before processing of actual wafers. 
     Refer now to FIG. 5, there is shown a cross section of a slightly different CMOS device structure. This structure formed on a P -   substrate 44 has an N -   well 30, and a P channel stop or field region 40 located under a part of the field oxide isolation region 38. N +   source/drain regions 34 are formed in the P -   substrate 44 and P +  source/drain regions 36 are formed in the N -   well 30. 
     As in the preceding embodiment index numbers B 1 , B 2 , B 3 , . . . , B M  are defined for the M segments of the N -  well mask; index numbers C 1 , C 2 , C 3 , . . . , C M  are defined for the M segments of the P field mask; index numbers D 1 , D 2 , D 3 , . . . , D M  are defined for the M segments of the P +  source/drain mask; and index numbers E 3 , E 2 , E 3 , . . . , E M  are defined for the M segments of the N +  source/drain mask. In each case the index number for a dark region is 0 and the index number for a clear region is 1. 
     As in the preceding embodiment a first index ratio, R 4 , a second index ratio, R 2 , a third index ratio, R 3 , and a fourth index ratio, R 4  are defined according to the following equations: 
     
         R.sub.1 =(D.sub.1 ×E.sub.1 +D.sub.2 ×E.sub.1 +D.sub.3 ×E.sub.3 +. . . +D.sub.M ×E.sub.M)M, 
    
     
         R.sub.2 =(B.sub.1 ×C.sub.1 +B.sub.2 ×C.sub.2 +B.sub.3 ×C.sub.3 +. . . +B.sub.M ×C.sub.M)M, 
    
     
         R.sub.3 =(E.sub.1 ×B.sub.1 +E.sub.2 ×B.sub.3 +E.sub.3 ×B.sub.3 +. . . +E.sub.M ×B.sub.M)/M, and 
    
     
         R.sub.4 =(D.sub.1 -B.sub.1 +D.sub.2 -B.sub.2 +D.sub.3 -B.sub.3 +. . . +D.sub.M -B.sub.M)/M. 
    
     In this embodiment it is expected that R 1 , R 2 , R 3 , and R 4  will be small compared to 1. For this embodiment R 1  and R 2  must be less than 0.05, and R 3  and R 4  must be less than 0.10. The mask quality is then evaluated as described in the preceding embodiment and as shown in the flow diagram of FIG. 7. 
     Refer now to FIG. 6, there is shown a cross section of a slightly different CMOS device structure. This structure formed on an N -   substrate 46 has a P -   well 32, and a P channel stop or field region 40 located under a part of the field oxide isolation region 38. N +   source/drain regions 34 are formed in the P -   well 32 and P +   source/drain regions 36 are formed in the N -  substrate 46. 
     As in the preceding embodiment index numbers A 1 , A 2 , A 3 , . . . , A M  are defined for the M segments of the P -  well mask; index numbers D 1 , D 2 , D 3 , . . . , D M  are defined for the M segments of the P +   source/drain mask; and index numbers E 1 , E 2 , E 3 , . . . , E M  are defined for the M segments of the N +   source/drain mask. In each case the index number for a dark region is 0 and the index number for a clear region is 1. 
     As in the preceding embodiment a first index ratio, R 1 , a second index ratio, R 2 , and a third index ratio, R 3 , are defined according to the following equations: 
     
         R.sub.1 =(D.sub.1 ×E.sub.1 +D.sub.2 ×E.sub.2 +D.sub.3 ×E.sub.3 +. . . +D.sub.M ×E.sub.M)/M, 
    
     
         R.sub.2 =(D.sub.1 ×A.sub.1 +D.sub.1 ×A.sub.2 +D.sub.3 ×A.sub.3 +. . . +D.sub.M ×A.sub.M)/M, and 
    
     
         R.sub.3 =(E.sub.1 -A.sub.1 +E.sub.1 -A.sub.2 +E.sub.3 ×A.sub.3 +. . . +E.sub.M -A.sub.M)/M. 
    
     In this embodiment it is expected that R 4 , R 2 , and R 3  will be small compared to 1. For this embodiment R 1  and R 2  must be less than 0.05 and R 3  must be less than 0.10. The mask quality is then evaluated as described in the preceding embodiment and as shown in the flow diagram of FIG. 7. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.