Abstract:
A method of fabrication of copper interconnect by means of copper electroplating is disclosed. In the conventional method of fabricating copper interconnect for integrated circuits, critical steps such as deposition of copper seed layer and chemical mechanical polishing (CMP) are required. However in this invention, both the seed layer deposition and CMP are not required.

Description:
BACKGROUND  
         [0001]    In the manufacture of devices on a semiconductor wafer, it is now the practice to fabricate multiple levels of conductive (typically metal) layers above a substrate. The multiple metallization layers are employed in order to accommodate higher densities as device dimensions shrink well below one micron design rules. Thus, semiconductor “chips” having three and four levels of metallization are becoming more prevalent as device geometries shrink to sub-micron levels.  
           [0002]    One common metal used for forming metal lines (also referred to as wiring) on a wafer is aluminum. Aluminum is used because it is relatively inexpensive compared to other conductive materials, it has low resistivity and is also relatively easy to etch. Aluminum is also used as a material for forming interconnections in vias to connect the different metal layers. However, as the size of via/contact holes is scaled down to a sub-micron region, the step coverage problem appears, which has led to reliability problems when using aluminum to form the interconnection between different wiring layers. The poor step coverage in the sub-micron via/contact holes result in high current density and enhance the electromigration.  
           [0003]    One material which has received considerable attention as a replacement material for VLSI interconnect metallizations is copper. Since copper has higher resistance electromigration property and lower resistivity than aluminum, it is a more preferred material for interconnect (plugs and wiring) formation than aluminum. However, one serious disadvantage of using copper metallization is that it is difficult to etch. Thus, where it was relatively easier to etch aluminum after deposition to form wiring lines or plugs (both wiring and plugs are referred to as interconnects), substantial additional cost and time are now required to etch copper.  
           [0004]    One typical practice in the art is to fabricate copper plugs and wiring by inlaid (Damascene) structures by employing CMP. Dual Damascene processing eliminates not only the need for metal etch (which is increasingly challenging in aluminum interconnects and nearly impossible with copper), but also the need for dielectric gap fill (another challenging process). This technique involves the creation of interconnect lines by first etching a trench or canal in a planar dielectric layer, and then filling that trench with metal, such as aluminum or copper. In dual damascene processing, a second level is involved where a series of holes (i.e., contacts or vias) are etched and filled in addition to the trench. A diffusion barrier such as tantalum is deposited by PVD first to prevent copper diffusion. A variety of techniques have been developed to deposit copper, including chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, electroplating, and electroless plating. If electroplating is employed, a copper seed layer is required to deposit on top of the diffusion barrier as a prerequisite for the subsequent electroplating operation. After copper deposition, a chemical mechanical polishing (CMP) process is required to remove excess copper and barrier layer and planarize the dielectric surface.  
         SUMMARY  
         [0005]    A method of fabrication of copper interconnect by means of copper electroplating is disclosed. In the conventional method of fabricating copper interconnect for integrated circuits, critical steps such as deposition of copper seed layer and chemical mechanical polishing (CMP) are required. However in this invention, both the seed layer deposition and CMP are not required.  
           [0006]    These together with other objects of the invention, along with the various features of novelty which characterize the invention, are pointed out with particularity in the claims annexed to and forming a part of this disclosure. For a better understanding of the invention, its operating advantages and the specific objects obtained by its uses, reference should be made to the accompanying drawings and descriptive matter in which there are illustrated preferred embodiments of the invention. 
       
    
    
     DESCRIPTION OF THE DRAWING  
       [0007]    [0007]FIG. 1A is a schematic illustration of a side elevation of a silicon wafer having trenches coated with Ta/TaN barrier layer and a copper seed layer before electroplating;  
         [0008]    [0008]FIG. 1B is a schematic illustration of a side elevation of the silicon wafer of FIG. 1 being electroplated with copper to fill trenches;  
         [0009]    [0009]FIG. 2 is a schematic illustration of a side elevation of the silicon wafer after copper plating utilizing CMP (Chemical Mechanical Polishing) to remove excess copper/barrier layer and planarize copper/silicon oxide surface;  
         [0010]    [0010]FIG. 3 is a schematic illustration of a side elevation of the structure of a silicon wafer to be copper plate in accordance with the invention:  
         [0011]    [0011]FIG. 4 illustrates the copper plating of the silicon wafer of FIG. 3; and  
         [0012]    [0012]FIGS. 5 through 9 illustrates various integrated circuit technologies suitable for this invention. 
     
    
     DETAILED DESCRIPTION  
       [0013]    This invention describes a fabrication method of copper interconnects using copper electroplating. In the case of electrodeposition (electroplating) of copper onto a silicon wafer, the wafer is typically coated with a thin conductive layer of copper (seed layer) and immersed in a solution containing cupric ions. Electrical contact is made to the seed layer, and current is passed such the reaction Cu 2+ + 2 e − →Cu occurs at the wafer surface. The wafer, electrically connected so that metal ions (cupric ions) are reduced to metal (copper) atoms, is referred to as the cathode.  
         [0014]    Another electrically active surface, known as the anode (copper metal), is present in the conductive solution to complete the electrical circuit. At the anode, an oxiation reaction occurs that balances the current flow at the cathode, thus maintaining electrical neutrality in the solution. In the case of copper plating, all cupric ions removed from solution at the wafer surface are replaced by dissolution from a solid copper anode. FIG. 1A is a schematic illustration of a side elevation of a silicon wafer  18  having trenches  10  coated with Ta/TaN barrier layer  14  and a copper seed layer  12  before electroplating. FIG. 1B is a schematic illustration of a side elevation of the silicon wafer of FIG. 1 being electroplated with copper  20 . The copper  20  fill trenches  10  coated with Ta/TaN barrier layer  14  on a wafer formed from silicon  18  and silicon dioxide  16  layers by a copper  22  strip connected to an anode in a solution  28  containing cupric ions.  
         [0015]    CMP (chemical mechanical polishing) is required after copper electroplating to remove excess copper and diffusion barrier layer and to planarize the metal-dielectric. FIG. 2 is a schematic illustration of a side elevation of the silicon wafer formed from silicon  18  and silicon dioxide  16  after copper plating utilizing CMP to remove excess copper/barrier layer and planarize copper/silicon oxide surface  10  with the Ta/TaN barrier layer  14 . Copper CMP is more complex because of the need to remove the tantalum or tantalum nitride barrier layers and copper uniformly without overpolishing any features. This is difficult because current copper deposition processes are not as uniform as the oxide deposition process. Copper also has the properties that add to the polish difficulties. It is a soft metal and subject to scratching and embedded particles during polishing. Also because copper is highly electrochemically active and does not form a natural protecive oxide, it corrodes easily. Therefore protecting the copper surface during polishing, clean and subsequent processing will be essential.  
         [0016]    In accordance with the invention, the electrical contact for the copper eletroplating is not made to the seed layer, as depicted from FIG. 1B as for the conventional method. Therefore no seed layer is required in this unique plating method. Referring to FIG. 3, which shows a cross-sectional view of a transistor structure with source  48 , drain  38 , gate electrode  42  and gate oxide  44 , a metal layer  40  and N-type substrate  46  are connected to the p-type implanted regions  38 . The negative terminal (cathode) of the power supply (battery) is made to contact to the back side of the wafer which is a n-type silicon wafer  46 . Before copper electroplating, a diffusion barrier layer (plug) such as tantalum  50  is deposited in a conventinal way, but this barrier layer is patterned to the defined areas such as in the trenches and vias. As shown in FIG. 3, the trenches  10  and vias  50  are formed by depositing field oxide  36 , nitride  34 , and oxide  32  layers with a barrier layer of tantalum  30 .  
         [0017]    The wafer is then subject to a solution  52  containing cupric ions for copper electroplating  20  and the trenches and vias are filled up as illustrated in FIG. 4 (only showing filling of trenches). Tantalum plugs near the gate region are deposited by conventional method). The copper deposit fills up the trenches to the top and the power to the plating bath is then terminated. In this unique way of copper electroplating no seed layer is required to initiate plating and no CMP is needed to remove excess copper and barrier layer from the surface of the dielectric layer to planarize the copper/dielectric surface. The critical processing steps required by the conventional plating method are totally eliminated.  
         [0018]    This unique electroplating method can be applied to various MOS (metal oxide semiconductor) field-effect transistors (FET) technologies such as PMOS (p-channel) and CMOS (complementary metal oxide semiconductor) IC technollogies. FIGS. 5 through 9 illustrates these different configurations. Referring to FIG. 5A, a PMOS device having gate electrode  42  on a gate oxide  44  (with field oxide  36  and dielectric layer  58 ), with P+ source  70  and P+ drain  72  on a n-type substrate  56  is connected to a cathode to the power supply  22  for electroplating as a transistor configuration in accordance with one embodiment of the invention invention.  
         [0019]    Similarly, as shown in FIG. 5B, a CMOS device (P-well) having gate electrode  42  on a gate oxide  44  (with field oxide  36  and dielectric layer  58 ), with P+ source  70 , P+ drain  72 , with N+ source  74 , N+ drain  76 , all on a n-type substrate  56  is connected to a cathode and the anode to a P− well  80  to the power supply  22  for electroplating as a transistor configuration in accordance with another embodiment of the invention.  
         [0020]    In another embodiment shown in FIG. 6, a CMOS device (P-well) having gate electrode  42  on a gate oxide  44  (with field oxide  36  and dielectric layer  58 ), with P+ source  70 , P+ drain  72 , with N+ source  74 , N+ drain  76 , all on a n-type substrate  56  is connected to the power supply  22  for electroplating as a transistor configuration. A bias is alos provided cathode and the anode to a P− well  80  and the n-type substrate  56 .  
         [0021]    In yet anothert embodiment shown in FIG. 7, a CMOS device (twin-well) having gate electrode  42  on a gate oxide  44  (with field oxide  36  and dielectric layer  58 ), with P+ source  70 , P+ drain  72 , with N+ source  74 , N+ drain  76 , all on a n-type substrate  56  with a n-epitaxy layer  84  is connected to a cathode and the anode to a P− well  80  to the power supply  22  for electroplating as a transistor configuration in accordance with another embodiment of the invention.  
         [0022]    In still yet another embodiment shown in FIG. 7, a CMOS device (twin-well) having gate electrode  42  on a gate oxide  44  (with field oxide  36  and dielectric layer  58 ), with P+ source  70 , P+ drain  72 , with N+ source  74 , N+ drain  76 , all on a n-type substrate  56  with a n-epitaxy layer  84  is connected to a cathode and the anode to a P− well  80  to the power supply  22  for electroplating as a transistor configuration in accordance with another embodiment of the invention. A bias is alos provided cathode and the anode to a P− well  80  and the n-type substrate  56 .  
         [0023]    Referring to FIG. 9, there is shown a diode device having oxide layers  32  in association with a P− well  80  on layered on a n-type substrate  56  for connection to an anode of a power supply  22  for plating in accordance with the invention.  
         [0024]    It should further be noted that numerous changes in details of construction and the combination and arrangement of elements may be resorted to without departing from the true spirit and scope of the invention as hereinafter claimed.