Abstract:
Methodology, and associated circuitry, for encoding and decoding signals utilize bistate orthogonal code techniques that effect autonomy of communications and simplified signal processing, thereby improving reliability. 
     Encoder (121) processes an incoming data stream by associating a bistate orthogonal code with each binary one in the input stream and then by transmitting a series of rate-increased pulses over a path during intervals determined by the code for each of the binary ones. 
     Decoder (131), in synchronism with encoder (121), is generally arranged as a correlation detector in that the decoder only responds to the particular bistate orthogonal code for which it is configured. Sensors in energy transfer relation to the path are positioned at detection points on the path in correspondence to an assigned code. The outputs of the sensors are processed to produce a rate-decreased detected signal at the rate of the input stream whenever a rate-increased stream corresponding to the decoder configuration is propagating along the path.

Description:
CROSS-REFERENCE TO A RELATED APPLICATION 
     The following U.S. application, which is assigned to the same assignee as the instant application and which is filed concurrently therewith, contains related subject matter: 
     &#34;Encoding and Decoding for Code Division Multiple Access Communication Systems&#34;, U.S. Ser. No. 423,332 of F. R. K. Chung--M. Kerner--M. G. O&#39;Connor J. A. Salehi--V. K. Wei. 
     FIELD OF THE INVENTION 
     This invention relates generally to digital communication systems and, more particularly, to a methodology and associated circuitry for encoding and decoding signals to effect information interchange among a plurality of stations interconnected via a common wideband channel. 
     BACKGROUND OF THE INVENTION 
     Present day communication networks must generally serve end-users requiring a broad range of integrated (data/voice/video) services. For example, a large business with hundreds of employees and numerous host machines and communication needs for facsimile, high resolution graphics and video may require up to 1 gigabit/sec. transmission capability. Other networks might operate at transmission rates in excess of 10 megabit/sec to interconnect terminals, intelligent workstations and personal computers to a large host or to interconnect small numbers of large hosts. 
     To achieve this capability, network operations previously performed electronically can now be implemented with optical processing, and the networks are configured with optical devices such as laser transmitters, photodiode receivers and fiber optic cables. 
     In many conventional electronic systems, the signals propagating over the channel facility may be expressed in terms of voltage and current waveforms. In the voltage-current domain, it is possible to generate and detect both positive and negative voltages and currents. For instance, channel signals could include, on a normalized basis, the ±1 signals as well as the 0 state, and detection of these signals takes advantage of the ability to sum voltages or currents to zero. With one technique, a so-called orthogonal code is utilized for encoding incoming signals and a receiver is configured as a so-called correlation detector. Because of the availability of two polarities, the overlap or projection of one pattern from the orthogonal code onto a different pattern from the code over a given time interval (basically a correlation operation) may be reduced essentially to zero. This allows for an effective detection process by the receiver since a high correlation implies that signal on the channel matches the receiver configuration whereas a low correlation indicates the signal is not destined for the particular receiver. 
     In an optical system, signals on a channel are propagated by the presence or absence of light energy or photons, that is, information interchange is conveyed by the ON/OFF signal states; this is in contrast to the plus, minus and zero states of electronic systems. In optics, there is no equivalent to negative values. Optical detection is equivalent to power measurement and, since power is inherently non-negative, detected signals cannot be optically manipulated to add to zero with other incident power. Thus, conventional electronic processing techniques cannot be exploited in the optical domain (or, for that matter, in any domain having a zero state and only one non-zero state), so two-state systems have required the consideration of new signal coding schemes satisfying new sets of constraints. 
     In a multiple user environment having only two propagation states, the considerations become even more complex. Signal separation and, ultimately, signal detection are generally achieved by time or frequency division, that is, a time or frequency slot is dedicated to each user. This is oftentimes inefficient. An alternative approach for a multiple user environment is code division. This method of transmission exploits codes in such a way that a user is able to extract the message intended for the user from the superposition of many messages on the transmission facility. Two exemplary versions of this technique are discussed in the article entitled &#34;Coding and Decoding for Code Division Multiple User Communication Systems&#34;, published in the IEEE Transactions on Communications, Vol. COM-33, No. 4, April, 1985. Decoding in conventional code division systems is generally quite complex and a substantial portion of processing time is dedicated to decoding time, thereby reducing throughput. 
     SUMMARY OF THE INVENTION 
     The limitations and shortcomings of conventional techniques for encoding, transmitting and decoding information in a system supporting only two signal propagation states are obviated, in accordance with the present invention, by methodology and corresponding circuitry for encoding and decoding the information with code patterns that engender the two-state equivalent of electronic orthogonal coding in a code division multiple access environment. These special code patterns are referred to as bistate orthogonal codes. 
     Broadly, in contrast to offsetting positive states of a coded signal over a given time interval to mitigate correlation of different patterns from the code, bistate orthogonal coding utilizes delay to minimize the projection of one code pattern onto another code pattern from the code. To introduce the delay dimension into the overall processing, each non-zero state emanating from a source controls a rate-increased stream of two-state signals called a signature pattern or signature template. Each source is assigned a particular signature. The channel signal comprises a composite of the signatures from the various active sources propagating over the channel. The sources are synchronized to the rate of the rate-increased stream. 
     Each receiver is also assigned a preselected signature and is configured accordingly. In one illustrative embodiment, signal taps are positioned along the channel in correspondence to the preselected signature. Whenever the sources and receivers are synchronized, and the preselected signature embedded in the composite channel signal is aligned with the taps, a threshold level in the receiver is exceeded, thereby indicating detection of the associated signature. The receiver also effects a rate-decreasing operation to restore the original information rate. 
     The code patterns selected are based on the manner in which the receivers are configured. If each receiver is enabled once at the rate corresponding to the original signal rate for a time period related to the rate of the rate-increased stream, one class of bistate orthogonal codes is admissible. If each receiver is enabled each time period, a second class of bistate orthogonal codes is admissible. 
     The organization and operation of this invention will be better understood from a consideration of the detailed description of the illustrative embodiments thereof, which follow, when taken in conjunction with the accompanying drawing. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 depicts, in block diagram form, the electro-optical communication system under consideration in accordance with the present invention; 
     FIG. 2 depicts the relationship between the incoming electrical signal and the rate-increased optical signal propagated by any of the encoders of FIG. 1; 
     FIG. 3 illustrates the operation of transmitting superimposed code patterns; 
     FIG. 4 illustrates the operation of shifting one code pattern relative to a second, fixed code pattern; 
     FIG. 5 illustrates the effect of superposition of code patterns on continuous processing; 
     FIG. 6 is a block diagram depicting an encoder illustrative of the present invention; and 
     FIG. 7 is a block diagram depicting a decoder illustrative of the present invention. 
    
    
     DETAILED DESCRIPTION 
     Overview 
     The general communication system 100 under consideration is depicted in block diagram form in FIG. 1. In system 100, M sources 101,102, . . . ,103 are arranged to communicate with N receivers 111,112, . . . ,113 over interposed optical channel 141. Sources 101-103 are coupled to channel 141 via electro-optical encoders 121-123, respectively, which comprise transmitter 120. In addition, electro-optical decoders 131-133 serve to couple the channel signals to receivers 111-113, respectively. Each encoder 121, 122 or 123, besides performing an encoding function, also converts electrical input signals to optical output signals. Similarly, each decoder 131, 132 or 133, besides effecting a decoding function, is also arranged to convert optical input signals to electrical output signals. The optical portion of system 100 is shown generally as between the dashed lines that intersect, respectively, the encoder blocks and the decoder blocks. 
     Although FIG. 1 shows M sources and N receivers, the encoding and decoding techniques in accordance with the present invention are applicable as well to the special cases where M or N equals 1, i.e., the cases where a single transmitter transmits to multiple receivers, or multiple transmitters transmit to a single receiver. 
     The channel under consideration, as exemplified by optical channel 141, is of the type that propagates only two-level or two-state digital signals, such as a logic zero (a &#34;space&#34;) and a logic one (a &#34;mark&#34;). To match this channel characteristic, signals emanating from encoders 121, . . . , 123 on leads 151, . . . , 153, designated by signature signals S i ,i=1, . . . , M, respectively, provide a stream of two-level or mark and space signals. Each S i  stream corresponds to a similar stream produced by each source 101, . . . , 103, respectively, as discussed shortly. Since channel 141 only supports two-level signals, if one or more encoders 121-123 propagate logic one signals over channel 141 during the same time duration, the channel. level remains a logic one. The channel level is logic zero if all the S i  outputs, i=1, . . . , M, are zero during the same time duration. In a logical sense, channel 141 behaves as an &#34;inclusive OR&#34; channel. 
     The composite signal on channel 141 due to all S i  &#39;s is the superposition of all S i  &#39;s and is represented by ##EQU1## where the summation is treated in the inclusive OR sense. Each lead 161, . . . , 163 emanating from channel 141 in FIG. 1 serves as an input to and provides composite signal S o  to decoders 131, . . . , 133, respectively. It follows from this description that all signatures S i ,i=1, . . . , M share substantially the same frequency band on channel 141. 
     Each signature signal S i ,i=1, . . . , M is constrained in time such that sources 101, . . . , 103 must initiate a transmission or information interchange in synchronism. One approach to achieving this synchronism is shown in FIG. 1. Clock 104 generates the timing signal, via lead 1041, which controls framing and synchronization among sources 101-103 and encoders 121-123. The encoding and decoding techniques in accordance with the present invention also allow the use of a special synchronization code, satisfying the same constraints as other assigned codes, which, when continually transmitted, would provide for network synchronization. 
     Decoders 131, . . . , 133 are in synchronism with encoders 121-123. Encoders &#34;train&#34; the decoders using any of the well-known training techniques to provide the requisite synchronization. In addition, receivers 111-113 are arranged to be in synchronism with decoders 131-133. 
     The primary function of each encoder 121, . . . , 123 is that of converting each logic one received from each corresponding source 101, . . . , 103 to a predetermined rate-increased stream of logic ones and logic zeros, as depicted generically in FIG. 2. Line (i) in FIG. 2 depicts three contiguous data bits, namely, a &#34;mark-space-mark&#34; sequence appearing in the output stream of, say, source 101 or the input stream to encoder 121. The time interval of either a mark or space is designated as a bit duration. 
     Line (ii) in FIG. 2 represents an output pulse stream, say S 1  from encoder 121, corresponding to the line (i) input stream. As shown, a rate-increased stream of logic one and logic zero pulses, which is replicated for all other marks produced by source 101, is generated by encoder 121. Since channel 141 is, illustratively, an optical medium, the logic one levels in output stream S 1  correspond physically to light or photon pulses. 
     In the rate-increased or optical portion of system 100, a frame corresponds to a bit duration, and the time interval of a logic one light pulse or a logic zero (no light pulse) is designated the chip duration. Thus, each frame is composed of a fixed number of so-called &#34;chips&#34;; three logic one chips occur during each mark frame in FIG. 2. The envelope of the mark frames is shown by the dashed rectangles on line (ii) of FIG. 2. 
     In order to communicate effectively within system 100, each signature S i ,i=1, . . . , M, as produced by its assigned encoder in response to an input mark, may not be selected arbitrarily, but must be carefully chosen to achieve efficient, error-free communication. This means basically that each S i  must be selected in view of all the other S i  &#39;s based on such considerations as number of sources M and the bandwidth of channel 141. These considerations, in turn, depend on the communication or system requirements or transmission characteristics. Sets of signatures S i ,i=1, . . . , M which effect efficient information interchange for a given number of chips and sources are discussed below. 
     The essential function of each decoder 131, . . . , 133 is that of discriminating within the composite signal S o  the preassigned signature associated with each decoder 131, . . . , 133. In one illustrative embodiment, each decoder 131, . . . , 133 is implemented by optical tapped delay lines arranged along channel 141. The optical separation among taps for each decoder corresponds to the distribution of logic one chips in the signature preassigned to the decoder. Thus, whenever a mark is transmitted, each tap in a given decoder extracts a high-peak signal whenever the logic one chips in the preassigned signature propagating as part of S o  are aligned with the taps. In this way, a so-called peak correlation manifests the arrival of the preassigned signature and, in turn, the propagation of a mark by the source having the same preassigned signature. A decoder illustrative of these principles is presented shortly. 
     The above overview description with reference to FIGS. 1 and 2 provides a basic framework for the principles of the present invention. The following sections elaborate on the details of illustrative embodiments, particularly those representative of encoders 121-123 and decoders 131-133. 
     Bistate Orthogonal Codes 
     For clarity of exposition, it is helpful first to consider particular examples of bistate orthogonal code sets in accordance with the present invention. The reason is three-fold, namely: it affords the opportunity to introduce terminology and notation; it provides a heuristic basis for the general encoding-decoding principles to be elucidated; and it highlights the differences in processing corresponding to different system assumptions. 
     1. Heuristic Basis 
     In the examples discussed in this section, two cases of synchronous transmission systems referred to earlier are distinguished. The first, Case I, is one in which processing is carried out frame-by-frame. The second, Case II, is one in which processing is carried out continuously. As shall be discussed below, these two cases generate different constraints on acceptable codes and require different algorithms. 
     Given a pulse pattern in K chips, c 1 ,c 2 . . . , c K , then the the delay between chips c i  and c j  is defined as |(i-j)|. The vector representation of a code of K chips in which M are marked to indicate pulses is as follows: The vector has form &lt;d 1 ,d 2 ,d 3 , . . . , d M  &gt;, where d i , for 1≦i≦M-1, equals the delay between the i th  and (i+1) st  marked chip, and d M  equals ##EQU2## With reference to FIG. 3, a code is shown comprising tour pulses in the 1st, 8th, 11th and 14th slots of a 15-chip frame. The notation for this code is &lt;7,3,3,2&gt;. In the next frame are the pulses for a &lt;3,2,6,4&gt; code, with pulses in the 1st, 4th, 6th and 12th chips. In the next frame, both codes are superimposed, so that pulses appear in the 1st, 4th, 6th, 8th, 11th, 12th and 14th chips. The notation for the pulses in this frame is &lt;3,2,2,3,1,2,2&gt;. 
     It is now envisioned that a template representation of a &lt;7,3,3,2&gt; code is being compared with the transmitted signal, frame-by-frame. In the first frame, all four transmitted pulses overlap. In the second frame only one pulse overlaps. In the third frame, all four pulses again overlap. The detector will recognize that a &#34;1&#34; as transmitted in the first frame, a &#34;0&#34; was transmitted in the second frame, and another &#34;1&#34; was transmitted in the third frame. 
     It is important to notice that when codes are superimposed on a frame, gaps between pulses may be generated which do not appear in the individual codes. For example, when the two codes were superimposed in the previous example, a gap of &#34;1&#34; appeared, representing the gap between the 3rd pulse of the 1st code and the 4th pulse of the 2nd code. No gap of &#34;1&#34; appears in the individual codes. Since the simultaneous transmission of codes within a single frame may generate new gaps, care must be taken in the generation of codes to guarantee that when a receiver&#39;s code aligns with M pulses in a frame, it is the result of the receiver&#39;s code intentionally being transmitted, and not the result of gaps being detected that are the result of simultaneous transmission of signals. It is also important to note that the synchronous nature of the transmission is important to the ability to identify the gaps that can possibly appear when all codes are transmitted. 
     Case I CDMA codes are defined to be codes with the property that when arbitrary combinations of the codes are superimposed on a single frame and the frames are processed discreetly, any detector will match with precisely 0, 1, or M pulses, and M pulses will be matched only when the receiver&#39;s assigned code has been transmitted. An algorithm for generation of these codes is described in Section 3. 
     Case II is now considered, where comparisons between a receiver&#39;s code with the transmitted signals is not made frame-by-frame, as described above, but continuously. 
     With reference to FIG. 4, a code pattern depicted on line (i) has representation &lt;4,10,11&gt; in a 25-chip frame. 
     Line (ii) of FIG. 4 depicts the same code pattern shifted one unit to the right and, therefore, is designated as pattern A(1). Lines (iii) and (iv) depict, respectively, a left-shift of one unit (A(-1)), and a right-shift of four units (A(4)). 
     Comparison of line (i) with line (iv) of FIG. 4 indicates that the code patterns &#34;overlap&#34;, that is, have a common chip. Thus, A(4) is said to overlap A(0) in one position and this is tabulated on line (iv) as OVERLAP=1. For lines (ii) and (iii), the overlaps are 0. Hence, A(4) overlaps A(0) in one position whereas A(1) relative to A(0) as well as A(-1) relative to A(0) have no overlaps. 
     The detection process in the continuous case can be thought of as a detector matching its pulse pattern against a continually shifting sequence of K chips. To use the terminology just introduced, in the case of frame-by-frame processing, only A(-25),A(0),A(25), etc., would be compared with the code pattern of the detector. In the case of continuous processing, all intermediate intervals, i.e., 
     A(-25),A(-24), . . . , A(0),A(1), . . . , A(24),A(25), are examined as well. 
     In an environment with multiple users, arbitrary combinations of codes may be combined in a single frame, corresponding to the simultaneous transmissions of &#34;1&#34; to multiple users. As described above, the superposition of multiple codes in a single frame generates gaps between pulses not necessarily found in individual codes. Continuous processing generates yet another source of new gaps, as now described. 
     In FIG. 5, a &lt;4,10,11&gt; code and a &lt;5,7,13&gt; code are shown superimposed on two consecutive 25 chip frames. Within each frame, new gaps appear that do not appear in either of the two individual codes. For example, a gap of 8 occurs between the marked 5th chip and the marked 13th chip and a gap of 2 exists between the marked 13th chip and the marked 15th chip. However, by matching a receiver&#39;s assigned pulse pattern with pulse patterns formed by concatenating pulse patterns in one frame with pulse patterns in another frame, continuous processing introduces many additional gaps. Suppose, for example, that a detector is processing the 25 chips starting with the 11th chip of the first frame and ending at the 10th chip of the second frame. The gap between the pulse in chip 13 in the first frame and chip 1 in the second, the gap between chip 13 in the first frame and chip 5 in the second, as well as many others, now appear. In general, many new gaps are formed by an initial pulse in one frame and a terminal pulse in the following frame, all within K chips. For the example in FIG. 5, the set of all possible gaps that can occur on the transmission line within K chips is: 
     
         {1,2,4,5,7,8,9,10,11,12,13,14,15,16,17,18,20,21,23,24} 
    
     Case II CDMA codes are defined to be codes with the property that even when arbitrary combinations of the codes are superimposed on successive frames, and the frames processed continuously, as described above, any detector will match with precisely 0, 1 or M pulses, and M pulses will be matched only when the receiver&#39;s corresponding code has been transmitted. This property can be described in terms of the delays detected during continuous processing. These delays must satisfy two properties. 
     1. Delays detected by different receivers must be distinct. 
     2. A delay which can be detected by some receivers will occur at most once in K transmitted chips. 
     An algorithm for generating codes saisfying these conditions is described in Section 3. Note that any codes satisfying these conditions automatically satisfy the conditions described earlier in Case I CDMA codes. 
     2. Illustrative Embodiments 
     In order to propagate the types of code patterns exemplified by FIGS. 3-5 over channel 141 of FIG. 1, one implementation for any encoder 121, 122 or 123, say encoder 121, depicted in block diagram form in FIG. 6 may be utilized. Chip clock 1211, which operates under control of clock 104 via lead 1041, outputs a pulse stream at the chip rate 1/T (T being the chip duration). Clock 1211 drives shift register 1212 and causes register 1212 to recirculate its stored bits. The bits shown as illustrative of the contents of register 1212 represent a typical eight-chip signal, designated generally as code G(0). The circulating bits serve as one input to AND gate 1213. The second input to gate 1213 is provided by lead 1011 emanating from source 101 of FIG. 1. Only a logic one or mark on lead 1011 causes gate 1213 to replicate the bits stored in register 1213 at the output of gate 1213, thereby providing the ON/OFF control of light source 1214. Lead 151 couples light source 1214 to channel 141. As depicted in FIG. 6, light pulses will be produced in the time periods between (0,T), (T,2T) and (4T,5T), corresponding to the G(0) code pattern stored in register 1212. 
     To detect the types of code patterns propagating on channel 141 of FIG. 1, one implementation for any decoder 131,132 or 133, say decoder 131, as depicted in block diagram form in FIG. 7 may be utilized. The description that follows assumes that the decoder is already in system synchronism. Again, this may be accomplished via the well-known technique of providing a &#34;training&#34; session prior to the transmission of any actual data. 
     Taps 201-203 on channel 141 are positioned according to the time distribution of the preassigned code pattern. For instance, if decoder 121 is arranged to detect the G(0) pattern {1,1,0,0,1,0,0,0}, taps 202 and 203 are spaced apart 2T and 3T seconds in time, respectively, from tap 201, or in terms of optical length, the distance traveled by a pulse in 2T and 3T seconds. The positioning of the taps relative to an G(0) frame during one instant of the detection process is illustrated by the FRAME time diagram above channel 141 in FIG. 7. 
     Taps 201-203 feed corresponding optical photo-detectors 211-213 and the individual outputs of these photo-detectors serve as inputs to integrators 221-223, respectively. 
     A channel signal S o  on channel 141 having an embedded code pattern corresponding to the tap positions generates a detectable signal at the output of each photo-detector for the chip duration. Each corresponding integrator sums the output of the photo-detector for a prescribed time interval, typically the chip duration. The outputs of integrators 221-223 are combined via summer 1312. This accumulated signal is then provided to threshold comparator 1313 for comparison to a predetermined threshold. In terms of the previous discussion, if detector 131 is arranged to detect G(0) patterns, then the appearance of an G(0) frame in S o  simultaneously provides a normalized signal of one unit at the end of the integration period from each integrator 221-223, respectively. Accordingly, summer 1312 registers a three unit output, and if the threshold is set to a normalized value of 2.5 units, the detection of this mark frame in comparator 1313 is indicated by enabling decoder 1315. Decoder 1315 performs a rate-decreasing operation to restore the original data rate. Each time decoder 1315 is enabled, lead 1311 registers a logic one at the original data rate. 
     If, however, the channel signal S o  is composed of only the pattern {1,0,1,0,0,0,1,0} and summer 1312 is enabled for a single chip duration once per frame by circuit 1314, then only integrator 223 senses an overlap and summer 1312 never exceeds one unit. Thus, comparator 1313 provides a logic zero to lead 1311. 
     For instance, it is supposed that channel 141 is propagating a signal corresponding to the G(0) chip pattern and this signal is to be detected in the present frame; moreover, it is supposed that continuous processing occurs. Then, the precursor to G(0) is the sequence G(-7), G(-6), . . . , G(-1), so that G(0) sweeps into view on a chip-by-chip basis at the input to detector 131. The post-cursor to G(0) is the sequence G(1), G(2), . . . , G(7) as the propagating signal sweeps out of view of detector 131. Basically, detector 131 detects the overlap of G(k) relative to G(0) for k=-7,-6, . . . , -1,1,2, . . . 7. The effects of the signal occur over the present as well as the succeeding frame. For the present frame, the maximum peak detected is 3 units (G(0) relative to G(0)). For the next frame, the value detected is one unit, and this peak is due solely to the tail of the propagating signal. Detector 131 outputs a logic one for the present frame and logic zero for the next frame for a threshold of 2.5 units. 
     In the design of codes, it is necessary to select chip locations with sufficient separation so that tail and head ends of the composite channel signal do not overlap and thereby cause a peak detection even though a pattern corresponding to the detector signature is not present. 
     The special codes derived for the situation of enabling gate 1312 for only one chip duration per frame are called Case I codes. For this situation, processing is carried out discretely frame-by-frame, that is, no processing occurs between frame enablement periods. 
     It is possible to consider another situation in which processing is carried out continuously, that is, on a chip-by-chip basis within each frame. The codes for this situation, designated above as Case II codes, are derived from more restrictive circumstances than the Case I codes. Any set of codes derived for a Case II system are applicable to a Case I system. For Case II, the channel signal being processed by a particular decoder results from the tail end of a preceding frame and the head end of the succeeding frame overlapping portions of the frame under consideration. The overlapping of tail and head ends may be understood in terms of the discussion presented above. 
     It is apparent that integrators 221-223 and summer 1312 should be reset at the beginning of each chip duration for either Case I or Case II arrangements. This reset operation is controlled by sync/reset circuit 1314, via lead 1316, in the usual manner for electronic correlation-type detectors. Furthermore, circuit 1314 maintains encoder-decoder synchronism via an initial training session. Frame synchronization is supplied to decoder 1315, also via lead 1316 from circuit 1314. 
     3. General Code Properties 
     In the preceding sections, certain generalized properties were introduced during the discussion of the correlation evaluations. Codes to satisfy these properties are now derived. 
     Case I Codes 
     The following procedure yields Case I codes for a (k,w,s)-system where k, w and s are positive integers such that 1≦w≦k and ##EQU3## with being the largest integer ≦y. In this notation, k is the total number of chips per frame, w is the number of logic one chips per frame, and s is the number of distinct codes in the (k,w,s)-system. In the patterns depicted by FIG. 5, k=25, w=3, s=2 and the patterns are Code 1 and Code 2. The procedure is: 
     (1) Create a w by s matrix by 
     (i) randomly selecting, without replacement, s×(w-1) integers from [1,k-1]; 
     (ii) filling up the first w-1 rows of the matrix with these values; and 
     (iii) assigning the value k to each entry in the wth row. 
     (2) Obtain the jth code, denoted as 
     
         D.sub.j =&lt;d.sub.1,d.sub.2, . . . d.sub.w &gt;, 
    
      by: 
     (i) taking the elements from the jth column of the matrix created in step (1) and putting them in ascending order in a vector, i.e., forming the vector 
     
         B.sub.j =&gt;b.sub.1,b.sub.2,b.sub.3, . . . , b.sub.w &gt; 
    
      such that b 1  &lt;b 2  &lt;b 3  &lt; . . . &lt;b w  =k; and 
     (ii) multiplying B j  by a matrix P of w rows and w columns which has a unit diagonal, -1&#39;s beneath each diagonal element, and 0&#39;s elsewhere, thereby obtaining 
     
         P×B.sub.j =D.sub.j 
    
     (3) Obtain the pulse pattern corresponding to D j  over a frame duration by 
     (i) marking the first chip, c 1 , to signify a pulse; and 
     (ii) continuing to mark the frame so that delay between the ith and (i+1)st marked chips is d i . 
     As an example, this procedure is considered for a (8,3,2)-system to demonstrate how codes may be derived. It is first noted that the constraints 1&lt;w≦k and ##EQU4## are satisfied since 1&lt;3≦8 and 1≦2≦ 7/2 =3. Step (1) (i): four integers 1,2,4,6 are randomly selected since s×(w-1)=4; 
     Step (1) (ii)-(iii): form ##EQU5##  a 3×2 matrix from the selected elements; Step (2) (i): B 1  =&lt;1,4,8&gt;; B 2  =&lt;2,6,8&gt;; 
     Step (2) (ii) for B 1  : ##EQU6## Step (2) (iii) for B 2  : ##EQU7##  Thus, D 1  =&lt;1,3,4&gt;; D 2  =&lt;2,4,2&gt; Step (3) (i)-(ii) for D 1  : the first chip c 1  is marked with a logic one pulse; the next chip to have a logic one pulse is chip c 2  since the offset or delay between chips c 1  and c 2  is d 1 , which equals 1; the next chip with a logic one pulse is chip c 5  since the delay between c 5  and c 2  is d 2  =3; finally, d 3  =4 to guarantee 
     that the sum of the D i  is k=8. 
     The derived code patterns for the Case I (8,3,2)-system are D 1  and D 2 . 
     Case II Codes 
     The following procedure yields Case II codes for a (k,w,s)-system: 
     (1) Construct design matrix P 1  of Q(Q-1) rows and Q columns, where Q=(w×s)-s+1, and whose elements form the following design: ##STR1## (2) Construct design matrix P 2  of ##EQU8##  rows and s(w-1) columns of the form: ##EQU9##  where [O] and [T] are each matrices of ##EQU10##  rows and (w-1) columns and such that [O] contains all zeros and [T] is a matrix whose elements form the following design: ##STR2## (3) Determine a vector 
     
         C=&lt;c.sub.1, c.sub.2, . . . , c.sub.Q &gt; 
    
      of length Q by 
     (i) randomly selecting Q-1 integers from [1,k-1] whose sum is less than k; 
     (ii) letting the first Q-1 elements of C be these integers, set the last element to ##EQU11## (4) Convert the C-vector to chip locations having logic one representations in a frame of length k chips. 
     (5) Assign pulse c 1  and w-1 other pulses to each of s vectors. 
     (6) Assign a i ,j to the ith element in the jth vector from the set of s vectors. 
     (7) Form the vector A as follows: 
     
         A=&lt;a.sub.1,1, . . . , a.sub.w-1,1,a.sub.1,2, . . . , a.sub.w-1,2, . . . , a.sub.l,s, . . . ,a.sub.w-1,s &gt;. 
    
     (8) Obtain vector R 2  by performing the matrix multiplication 
     
         P.sub.2 ×A=R.sub.2 
    
     (9) Obtain vector R 1  by performing the matrix multiplication of 
     
         P.sub.1 ×C=R.sub. 
    
     (10) If the elements of R 2  are distinct and appear only once in R 1 , then the s vectors ##EQU12##  are Case II codes. 
     As an example, this procedure is considered for a (156,4,3)-system. 
     Steps (1) and (2): with 4 pulses per code and 3 codes desired, Q=10. Thus, P 1  has 90 rows and 10 columns; also, P 2  has 18 rows and 9 columns where ##EQU13## Step (3): 
     
         C=&lt;6,25,27,11,26,13,7,25,4,12&gt; 
    
     Steps (4) and (5): the three vectors formed from C are 
     
         s.sub.1 =&lt;6,89,49,12&gt; 
    
     
         s.sub.2 =&lt;58,50,32,16&gt; 
    
     
         s.sub.3 =&lt;31,38,46,41&gt; 
    
      by assigning the 2nd, 6th and 10th marked chips to s 1 , the 4th, 7th and 9th marked chips to s 2 , and the 3rd, 5th and 8th chips to s 3 . 
     Steps (6) and (7): 
     
         A=&lt;6,89,49,58,50,32,31,38,46&gt; 
    
     Step (8): 
     
         R.sub.2 =&lt;6,89,49,95,138,144,58,50,32, 108,82,140,31,38,46,69,84,115&gt;. 
    
     Step (9): ##STR3## Step (10): 
     It can readily be verified that the elements in R 2  are distinct and appear only once in R 1 . Accordingly, s 1 , s 2  and s 3  provide appropriate codes for a Case II (156,4,3)-system.