Abstract:
A system on chip (SOC) contains a core circuit and an input/output (I/O) circuit embedded with an array of single-poly erasable programmable read only memory cells, each of which comprises a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P-type substrate. The first PMOS transistor includes a single-poly floating gate, a first P +  doped drain region and a first P +  doped source region, the second PMOS transistor includes a single-poly select gate and a second P +  doped source region, and the first P +  doped source region of the first PMOS transistor serves as a drain of the second PMOS transistor.

Description:
BACKGROUND OF INVENTION 
   1. Field of the Invention 
   The present invention relates to an integrated circuit embedded with single-poly non-volatile memory (NVM) fabricated using an application specific integrated circuit (ASIC) or conventional logic process. 
   2. Description of the Prior Art 
   In previous designs, an electronic system would be based on a board populated with a microprocessor or micro-controller, memory, discrete peripherals, and a bus controller. Today, such a system can fit on a single chip, hence the term System On Chip (SOC). SOC is an IC consisting of a processor, embedded memory, various peripherals, and an external bus interface. Embedded memory can be either volatile (SRAM, DRAM) or non-volatile (ROM, Flash). Peripherals vary from the general purpose (Counter/Timers, UART, Parallel I/O, Interrupt controller, etc) to the specialized (LCD Controller, Graphics Controller, Network Controllers, etc). The external bus interface allows the SOC to interface with external memory devices and peripherals with little or no glue logic. Almost every semiconductor company that has a processor, or access to one, is developing SOC products. This advancement in technology allows system designers to reduce system testing and size, improve reliability, and shorten the time to market for their products. 
   It is desirable, when embedding memory cells into a standard logic process, to do so without changing the single-poly process typically used in the fabrication of the logic circuitry. This desire has led to the development of a single-poly ROM cell having N +  source and N +  drain regions formed in a P −  substrate and a polysilicon gate overlying a channel region extending between the source and the drain. An N diffusion region formed in the P −  substrate serves as the control gate and is capacitively coupled to the floating gate via a thin oxide layer. The oxide layer has a tunnel window opened in a portion thereof near the N +  drain to facilitate electron tunneling. The control gate and floating gate of this single-poly ROM cell form a capacitor in a manner similar to that of the more traditional stacked-gate, or double-poly, EEPROM cells. However, the above-described N-channel single-poly ROM cell is disadvantageous since it requires programming and erasing voltages of 20 V. These high programming and erase voltages limit the extent to which the size of such cells may be reduced. 
   Sung and Wu, in U.S. Pat. No. 6,044,018, disclose a single-poly memory device that can be fabricated with a conventional CMOS process sequence. A complimentary cell couples the floating gate of an NMOS device to the floating gate of a PMOS device. Each gate at least partially overlaps a source region and a drain region. A channel-stop region adjacent to the source of the PMOS device inhibits formation of a channel between the source and drain, and hence essentially eliminates current flow from the drain to the source in the PMOS device, even when a voltage is present between the source and drain and the floating gate has sufficient potential to otherwise initiate a channel. 
   Nevertheless, the single-poly memory device disclosed in U.S. Pat. No. 6,044,018 suffers from several drawbacks. First, the prior art memory device consumes a lot of chip area since it is composed of a PMOS device and an NMOS device, and hence an extra field oxide layer is needed for isolating the PMOS form the NMOS. Second, the prior art EEPROM cell needs an extra channel stop region and the formation of a conductor for connecting two gates, this, in turns, means extra process steps and thus raised cost. 
   SUMMARY OF INVENTION 
   Accordingly, it is a primary object of the claimed invention to provide a single-poly non-volatile memory (NVM) cell that is operated at a lower programming voltage and can be fabricated with a conventional logic process, thereby incorporating into a system on a chip fabrication process. The single-poly NVM device according to this invention can be operated at relatively low voltages and is thus a low power consumption NVM memory. 
   It is another object of the claimed invention to provide a SOC embedded with high-density single-poly NVM device that is logic process compatible and consumes small per unit chip area and is power saving. 
   It is still another object of the claimed invention to provide a unique embedded high-density single-poly NVM device and related operation methods. 
   According to one embodiment of the claimed invention, an integrated circuit (IC) comprises a core circuit and an input/output (I/O) circuit embedded with an array of single-poly non-volatile memory cells, each of which comprises a first transistor serially connected to a secondtransistor. The first and second transistors are both formed on a well of a semiconductor substrate. The first transistor includes a single-poly floating gate, a first drain region and a first source region, the second PMOS transistor includes a single-poly select gate and a second source region, and the first source region of the first transistor serves as a drain of the second transistor. 
   In a programming mode, a well voltage is applied to the well, and a drain of the first transistor is biased to a first voltage, thereby coupling a second voltage on the single-poly floating gate to turn on a channel under the single-poly floating gate. It is advantageous to use the present invention because the embedded single-poly non-volatile memory cells have a same transistor or device structure as the transistor structure of the I/O circuit device (i.e., the embedded single-poly non-volatile memory cells are made from some of the I/O circuit devices, or fabricated with substantially the same design rule), and thus they can sustain relatively higher voltages than the core circuit device does. The core circuit devices are operated at lower voltages and higher speeds. 
   In different process technologies, the I/O devices with the same operating voltage range will behave the same electrical performances. Meanwhile, due to process technique improvement, the shrinkage in the device size is still observed. Another object of the claimed invention to provide a embedded single-poly nonvolatile memory (NVM) cells formed by the devices which are the same as those in I/O circuits can be easily ported to different process technologies which provide the same I/O devices. Thus, the embedded NVM cells can be also shrunk to a smaller cell size due to process improvement. 
   Other objects, advantages and novel features of the invention will become more clearly and readily apparent from the following detailed description when taken in conjunction with the accompanying drawings. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings: 
       FIG. 1  is a block diagram schematically showing an integrated circuit (IC) embedded with a single-poly NVM therein according to the present invention. 
       FIG. 2  demonstrates a P-type NVM cell according to the present invention. 
       FIG. 3  is an enlarged top view showing the layout of the NVM cell of FIG.  2 . 
       FIG. 4  to  FIG. 7  are cross-sectional views of this invention. 
       FIG. 8  depicts the relation between the drain current I d  and the floating gate voltage. 
       FIG. 9  plots the gate currents versus gate voltages of the floating gate regarding a selected PMOS transistor (Channel Hot Electron (CHE) operation) at different drain to N-well biases (V d =V BL −V NW ). 
       FIG. 10  is an array of the single-poly NVM according to the present invention. 
       FIG. 11  demonstrates an N-type NVM cell according to the present invention. 
       FIG. 12  is an enlarged top view showing the layout of the NVM cell of FIG.  11 . 
       FIG. 13  to  FIG. 16  are cross-sectional views of this invention. 
       FIG. 17  plots the gate currents versus gate voltages of the floating gate (for N-channel). 
       FIG. 18  is an array of the single-poly NVM according to another preferred embodiment of the present invention. 
   

   DETAILED DESCRIPTION 
   The preferred embodiment in accordance with the present invention will be discussed in detail with reference to  FIG. 1  to FIG.  18 . It is understood that the type of semiconductor regions, device layout, and polarity of voltages are chosen solely for illustration, and person having ordinary skill in the art would recognize other alternatives, variations, and modifications. 
   Please refer to FIG.  1 .  FIG. 1  is a block diagram schematically showing an integrated circuit (IC) embedded with a single-poly non-volatile memory (NVM) therein according to the present invention. As shown in  FIG. 1 , the IC  10  comprises a core circuit  12  and an input/output (I/O) circuit  14 . The core circuit  12  comprises a plurality of core circuit devices (either PMOS or NMOS, not shown in this figure), which are operated at relatively low voltages and high speed and are fabricated using advanced logic process such as 0.25-micron technology. That is, the core circuit devices have a critical dimension of about 0.25 microns, thinner gate oxide thickness, and therefore smaller device dimension and faster speed. It is understood that, heretofore, some chip manufacturers have advanced to 0.18-micron, 0.13-micron, even beyond 100-nanometer technology, and the present invention is not limited thereto. 
   The I/O circuit  14  comprises I/O circuit devices, which can sustain relatively higher voltages such as 3.3V. A portion of the 3.3V I/O circuit devices are used to constitute an array of non-volatile memory (embedded NVM)  141  and a memory control circuit  142  thereof. The communication (bus) between the embedded NVM  141  and the memory control circuit  142  and between the core circuit  12  and the memory control circuit  142  employs technologies known in the art and the details are therefore omitted. 
   Please refer to FIG.  2  through FIG.  10 . It is also an object of the claimed invention to provide a unique embedded high-density single-poly NVM device and related operation methods. Referring first to FIG.  2  and  FIG. 3 ,  FIG. 2  is a circuit of a NVM cell according to the present invention.  FIG. 3  is an enlarged top view showing the layout of the NVM cell according to the present invention. As shown in FIG.  2  and  FIG. 3 , the NVM device  20  comprises two serially connected PMOS transistors  201  and  202 . The PMOS transistor  201  acts as a select transistor or switch transistor and the select gate of the PMOS transistor  201  is electrically connected to a word line. In operation, a select gate voltage (V SG ) is applied to the select gate of the PMOS transistor  201  via the specific word line. The PMOS select transistor  201  further comprises a source terminal  301  biased to a source line voltage (V SL ) and a drain terminal  302  coupled to the PMOS transistor  202 . That is, the drain terminal  302  of the PMOS transistor  201  simultaneously serves as a source terminal of the PMOS transistor  202 . The PMOS transistor  202  further comprises a single-poly floating gate  306  and a drain terminal  303  that is biased to a bit line voltage (V BL ). The drain terminal  302  of the PMOS transistor  201  (also the source of the PMOS transistor  202 ) and the drain terminal  303  define a P-channel under the floating gate  306 . 
   
     
       
             
             
             
             
             
             
             
           
         
             
               TABLE 1 
             
             
                 
             
             
                 
                 
               Un- 
                 
                 
                 
                 
             
             
                 
               Selected 
               selected 
               Selected 
               Unselected 
               Source 
                 
             
             
               Operation 
               WL 
               WL 
               BL 
               BL 
               Line 
               N-well 
             
             
                 
             
           
           
             
               Write “1” 
               0 V 
                 5 V 
                 0 V 
                 5 V 
                 6 V 
                 6 V 
             
             
               Write “0” 
               0 V 
                 5 V 
                 5 V 
                 5 V 
                 5 V 
                 5 V 
             
             
               Read 
               0 V 
               3.3 V 
               2.3 V 
               3.3 V 
               3.3 V 
               3.3 V 
             
             
                 
             
           
        
       
     
   
   Referring to Table 1 and FIG.  4  through  FIG. 7 , a best mode for low-voltage memory operations is listed in Table 1, and the programming/reading modes regarding the single-poly EPROM device of the present invention are illustrated in cross sectional views. As shown in  FIG. 4 , in a programming mode for writing “digital one”, the selected word line is grounded. The unselected word lines are applied with a positive voltage of about 3V-8V, preferably 5V. The selected bit line is grounded and the unselected bit lines are applied with a positive voltage of about 3V-8V, preferably 5V. A source line voltage V SL  of about 5V is applied on the source terminal of the select transistor  201 . A well voltage of about 5V is applied to the N-well (NW). Under these conditions, the P-channel of the select transistor  201  and the P-channel under the floating gate of the PMOS transistor  202  turn on and hot channel electrons inject into the floating gate of the single-poly PMOS transistor  202 . 
   As shown in  FIG. 5 , in a programming mode for writing “digital zero”, the selected word line is grounded. The unselected word lines are applied with a positive voltage of about 3V-8V, preferably 5V. The selected bit line is applied with a positive voltage of about 3V-8V, preferably 5V. A source line voltage V SL  of about 5V is applied on the source terminal of the select transistor  201 . A well voltage of about 5V is applied to the N-well. Under these conditions, the P-channel under the floating gate of the PMOS transistor  202  is in an “OFF” state. 
   As shown in  FIG. 6 , in a data reading operation, the selected word line is grounded. The unselected word lines are biased to a voltage of about 2.5V-5V. The selected bit line is biased to a voltage of about 0V-2.5V. The unselected bit lines are biased to a bit line voltage of about 3.3V. The source line voltage is about 2.5V-5V. The N-well voltage is about 2.5V-5V. When reading a programmed cell, the floating gate of the programmed cell is charged, then V FG −V S &lt;V THP (V THP : threshold voltage of PMOS transistor  202 ), the memory cell maintains at a status of “ON”. The floating gates of those un-programmed memory cells have no charge injected therein, then V  FG −V S &gt;V THP , these memory cells are in a status “OFF”. 
     FIG. 8  depicts the relation between the drain current I d  and the floating gate voltage.  FIG. 9  plots the gate currents I G  versus gate voltages of the floating gate regarding a selected PMOS transistor (Channel Hot Electron (CHE) operation) at different drain to N-well biases (V d =V BL −V NW ). As shown in FIG.  8  and  FIG. 9 , according to a best mode of the present invention, the drain to N-well bias (V d ) is about −5V to −6V. A maximum gate current of about 1.0×10 −9  to 5×10 −11  μA/μm is observed at a floating gate voltage of about −1V to −1.5V. More specifically, at a drain bias V d =−5V, for example, the floating gate acquires a relatively low-level coupling voltage of about −1˜−2V. At the same time, the P channel thereof is just turned on and reaches a gate current approaching a maximum value of about 5×10 −11  μA/μm. In other words, a better performance during the writing operation can be achieved according to the present invention, since the gate current to drain current ratio (I G /I d ) is improved. 
     FIG. 10  is a top view illustrating a portion of the memory array of the single-poly NVM according to the present invention. As shown in  FIG. 10 , for programming (writing “digital one”) the cell I (as specifically indicated with dash line cycle), a bit line voltage V BL  of about 5V to 6V is applied to the drain terminal of the floating gate PMOS transistor of the memory cell I. The select gate of the memory cell I is grounded. Along the same bit line, the other un-programmed memory cells (cell II, cell III, and cell IV) will not suffer from the drain disturbance that typically occurs during programming for a conventional stacked gate memory device. 
   Referring to FIG.  11  and  FIG. 12 ,  FIG. 11  is a circuit of a NVM cell according to another preferred embodiment of the present invention.  FIG. 12  is an enlarged top view showing the layout of the NVM cell of FIG.  11 . As shown in FIG.  11  and  FIG. 12 , the NVM device  20  comprises two serially connected NMOS transistors  401  and  402 . The NMOS transistor  401  acts as a select transistor or switch transistor and the select gate of the NMOS transistor  401  is electrically connected to a word line. In operation, a select gate voltage (V SG ) is applied to the select gate of the NMOS transistor  401  via the specific word line. The NMOS select transistor  401  further comprises a source terminal  601  biased to a source line voltage (V SL ) and a drain terminal  602  coupled to the NMOS transistor  402 . That is, the drain terminal  602  of the NMOS transistor  401  simultaneously serves as a source terminal of the NMOS transistor  402 . The NMOS transistor  402  further comprises a single-poly floating gate  606  and a drain terminal  603  that is biased to a bit line voltage (V BL ). The drain terminal  602  of the NMOS transistor  401  (also the source of the NMOS transistor  402 ) and the drain terminal  603  define an N-channel under the floating gate  606 . 
   Referring to FIG.  13  through  FIG. 16 , a best mode for programming/reading the single-poly N-type NVM device of the present invention is illustrated in cross-sectional views. As shown in  FIG. 13 , in a programming mode for writing “digital one”, the selected word line is applied with a positive voltage of about 3V-8V, preferably 6V. The selected bit line is applied with a positive voltage of about 3V-8V, preferably 6V. A source line voltage V SL =0V is applied on the source terminal of the select transistor  401 . A well voltage of 0V is applied to the P-well (PW). Under these conditions, the N-channel of the select transistor  401  is turned on and hot holes inject into the floating gate of the single-poly NMOS transistor  402 . 
   As shown in  FIG. 14 , in a programming mode for writing “digital zero”, the selected word line is applied with a positive voltage of about 3V-8V, preferably 6V. The selected bit line is applied with a voltage of 0V. A source line voltage V SL =0V is applied on the source terminal of the select transistor  401 . A well voltage of 0V is applied to the P-well (PW). Under these conditions, the N-channel under the floating gate of the PMOS transistor  402  is in an “OFF” state. 
   As shown in  FIG. 15 , in a data reading operation, a select gate voltage V SG =3.3V is applied on the selected word line. The selected bit line is biased to a voltage of about 0V-2.5V, preferably 1V. As shown in  FIG. 16 , the unselected word lines are biased to a voltage of 0V. The unselected bit lines are biased to a bit line voltage of about 0V-2.5V, preferably 1V. The source line voltage is 0V. The N-well voltage is 0V. The operations of the memory cell as set forth through  FIG. 13  to  FIG. 16  are based on the relation plotted in FIG.  17 . 
   To sum up, the present invention provides an IC embedded with unique NVMs such as EPROM or OTP cells, which is suited for different-generation (such as 0.25-micron, 0.18-micron, or 0.13-micron) advanced logic processes. No matter what generation logic process the core circuit of the IC uses, a portion of the 3.3V I/O devices can be utilized to create an array of NVM and memory control circuit thereof. No additional mask is required for the NVM. The development cycle for the embedded logic NVM memory can thus be shortened for each generation logic process. Further, the high voltage used to program the NVM cells is decoupled in I/O devices such that the high field is not observed between the gate oxide of the I/O devices and the junction-to-well of the I/O devices, thus guarantee the reliability of the device. 
   Those skilled in the art will readily observe that numerous modification and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.