Abstract:
A single, programmable, multifunctional input circuit scheme for integrated circuit chips is disclosed. An input pin is provided with selectable input logic circuit blocks, each capable of providing an input signal to another circuit in the integrated circuit system architecture. The user of the chip is provided with means for programming said pin to select one of said logic circuit blocks, whereby each said pin has multifunction capability.

Description:
BACKGROUND OF THE lNVENTlON 
     1. Field of the Invention 
     The present invention generally relates to integrated circuit devices and, more particularly, to a single, multifunctional, integrated circuit input scheme which is user-programmable. 
     2. Description of the Related Art 
     Integrated circuit (IC) miniaturization has progressed to the stage where, in very large scale integration (VLSI) technologies, there are in excess of a million devices on an integrated chip which is typically 0.3 to 0.5 square inch in surface area. 
     While functional density and capability at the IC level has increased dramatically, one limitation on the flexibility of IC use has remained the number of input and output pins available on the chip carrier package. The circuit designer is limited as to the functions which the device can perform by the number of input control signals and output signals that will be available based on the design of the carrier package. Examples of typical dual-inline package input/output requirements for several programmable read only memory (PROM) ICs are shown in FIG. 1. 
     One solution is to use packages with more pins. Pin grid array packages, such as shown in FIG. 2, provide a higher input/output capability. However, this solution is at the expense of miniaturization and problems such as chip-to-chip interconnect distances and pin-to-socket alignment difficulties. While suitable for chips such as programmable logic arrays (PLA) used, for example, as simple state-machines, such packaging would be unacceptable for higher logic devices such as memory chips used in compact, powerful, high-speed computers. 
     Another solution has been to provide the user with the option to implement a variety of input functionalities through fabrication process modification. Typically, separate metallization masks are used to alter the interconnect pattern of the completed integrated circuit. This, of course, is a customization during fabrication which cannot be altered thereafter. 
     A simple &#34;programmability&#34; solution has been to provide the user with an &#34;either/or&#34; choice for a particular pin. For example, the devices of FIG. 1, manufactured by the current assignee, Advanced Micro Device, Inc., Sunnyvale, Calif., can have a programmable output enable pin and/or a programmable register initialize pin. The unprogrammed state of these pins is asynchronous operation. Should the system in which they are used require, either function may be changed to a synchronous mode of operation by programming an architecture word. For example, the initialize function uses a programmable word which is loaded into the output data registers to change the device to synchronous operation. This is a very limited, narrow application solution to the problem at hand. 
     Hence, there is a need for increasing the flexibility of the available pins of an IC package. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a scheme for programming a single input of an integrated circuit to a variety of functions. 
     It is another object of the present invention to provide user-programmable circuitry for an integrated circuit input pin. 
     It is yet another object of the present invention to increase the flexibility of integrated circuit devices having a fixed number of input terminals by providing a programmability scheme for each input terminal. 
     In a broad aspect, the present invention comprises a programmable input circuit having a plurality of input circuits for providing a variety of output signals, and means for selecting one of said plurality of input circuits. 
     Other objects, features and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the FIGURES. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 (prior art) is a depiction of typical pin arrangements for dual-in-line type IC carrier packages; 
     FIG. 2 (prior art) is a depiction of a typical pin arrangement for a grid array type IC carrier package; 
     FIG. 3 is a schematic drawing of the general logic block diagram of the system architecture of the preferred embodiment of the present invention; 
     FIG. 4 is a schematic circuit logic diagram of an exemplary implementation of the present invention as shown in FIG. 3; 
     FIG. 5 is a truth table for operational modes of the embodiment of FIG. 4; and 
     FIG. 6 is an alternative embodiment of the exemplary implementation of FIG. 4 with gate minimization. 
    
    
     The drawings referred to in this description should be understood as not being drawn to scale except if specifically noted. Moreover, the drawings are intended to illustrate only one portion of an integrated circuit fabricated in accordance with the present invention. 
     DETAILED DESCRIPTION OF THE INVENTION 
     Reference is made now, in detail, to a specific embodiment of the present invention which illustrates the best mode presently contemplated by the inventors for practicing the invention. Alternative embodiments are also briefly described as applicable. 
     Referring now to FIG. 3, the present invention is shown in generalized logic block diagram form. A chip input pin 4 is coupled via interconnect line 6 to one input terminal of each of a plurality of functional logic circuitry blocks #1-#N. Each block #1-#N (also marked 16, 18 . . . N On FIG. 3) is a circuit which generates an output signal at an output terminal. The output signal is transmitted via respective output interconnect lines #1&#39;-#N&#39; to another circuit (not shown) on the same integrated circuit chip. 
     In other words, a particular signal from one of said blocks 16, 18 . . . N is transmitted to the main functional sections of the chip, such as programmable read only memory (PROM) or programmable logic array (PLA) circuits. 
     A signal supplied on input pin 4 would be a form of user-supplied &#34;enable-type&#34; signal to initiate the operation of the blocks #1-#N to generate said output signal to said chip circuit via interconnect lines #1&#39;-#N&#39;. 
     In order to determine which of the logic blocks #1-#N is operational, each block has a second input terminal for receiving a signal level which will effectively &#34;select&#34; that block #1-#N over any other block. 
     In this embodiment, the input pin is &#34;programmed&#34; such that only one of the blocks #1-#N output signals is actually generated on output line #1&#39;-#N&#39;, respectively, when the enabling-type signal is applied to input pin 4 and, hence, to the block #1-#N first input terminals. 
     In order to perform said programming of each input pin 4 which is coupled to such selectable logic block #1-#N, on-chip circuitry 8 is provided for programming the means for selecting which block #1-#N receives said selecting signal. 
     In the embodiment shown in FIGS. 3 and 4, the programming circuitry 8 is used to sever on-chip fuses Fl-Fn, the state of which will determine which block #1-#N receives the selecting signal level. This programming circuitry 8 can be on or off the IC. (Note: the same programming circuitry 8 can also serve to program other programmable sections of the chip, such as the PROM or PLA. Such circuitry and commercial devices for performing such programming are well known in the art and, therefore, no detailed description is presented here.) As will be recognized by a person skilled in the art, the fuses can also be selectively severed by other means, such as a laser adapted for this purpose. 
     In the present embodiment, each fuse Fl-Fn is a coupling between a reference potential level, such as circuit ground, and discrete input terminals DIl - DIN of a decoder circuit 10 via interconnect lines 12-l through 12-n. The decoder 10 is the hardware implementation of a truth table which effectively reads the state of the fuses Fl-Fn based upon the signal level at the decoder inputs DIl-DIN. 
     Each decoder output terminal DOl-DON is discretely coupled via interconnect lines 14-1 through 14-N to said second input terminals of said blocks #1-#N, respectively. Hence, once programmed, e.g., once the appropriate fuses Fl-Fn are severed in order to couple one respective decoder input to the reference potential, the respective block FX coupled to said reference potential through the decoder 10 will have an active input signal on said second input and be in a &#34;selected&#34; state. In the example, &#34;selected&#34; block--and only the selected block--will be ready to generate its output signal whenever enabled by the appropriate input signal on pin 4. 
     In this manner, i.e., by blowing the appropriate fuses, the user programs the input pin 4 such that the desired available blocks #1-#N generate an output signal to the chip. 
     Note, particularly, that to provide a higher order of programmability the fuses can be replaced by programmable logic elements, such as logic-controllable pass-gates. In other words, it is contemplated that a reprogrammable or variably programmable embodiment can be constructed which can be digitally controlled during operation, such as by a central processing unit (CPU). The structure and operation of such elements are well known in the art; therefore, a detailed description is not necessary to an understanding of the invention. 
     A detailed logic gate circuit schematic of the present invention is shown in FIG. 4. For the purpose of describing the invention, an exemplary embodiment with a programmability of four possible states, requiring two fuses, is described. For more complicated input requirements, the number of fuses would be 2 n , where n=number of possible states. 
     As an example of types of input signals which are common to registered memory-type integrated circuits, this embodiment is described with respect to using two architecture fuses to program an input pin for the ENABLE and INITIALIZE signals in synchronous or asynchronous input functionality, viz., four possible states. An ENABLE signal may be desirable to provide a word depth expansion function; an INITIALIZE signal may be desirable during a power up or reset operation. A truth table describing the two-bit architecture programming is shown in FIG. 5. 
     The circuit implementation of the present invention, as shown in FIG. 4, comprises common logic gates and flip-flop registers. As will be obvious to a person skilled in the art, therefore, the invention can be implemented in any semiconductor technology, e.g., bipolar, MOS, BiMOS, GaAs, etc. 
     Referring now to FIG. 4, programming circuitry 8 is used to preprogram the input pin 4 by setting the condition of architecture fuses F1&#39; and F2&#39;. Thereafter, decoder 10 will provide only one enabling signal on one of the decoder outputs DIl-DI4. In other words, the decoder acts as the truth table implementation, selecting which of the logic blocks 16, 18, 20, 22 is to be enabled, based upon the condition of the fuses F1&#39;, F2&#39;. Fuse F3&#39; is a data fuse for controlling the initialization state of the data register. 
     For example, based on the logic of FIG. 4 and as shown in the truth table of FIG. 5, with the two architecture fuses F1, F2 intact, both the ENABLE and INITIALIZE functions will operate ASYNCHRONOUSLY because only one AND gate, G3, of the decoder 10 is active. Thus, only decoder output line D13 has an active signal to provide an input to one of the four logic blocks 16, 18, 20, 22--in this example, the selected logic block being the ASYNCHRONOUS ENABLE LOGIC block 20 which gets its other input directly from the input pin 4 (as would each of the logic blocks 16, 18, 20, 22, if so selected). Logic blocks for generating a digital signal level based upon input conditions are common logic gate implementation and well known in the art, and no detailed description is provided herein. 
     Thus, by severing selected fuses only, the user can program the input pin 4 to select only one of the input logic circuits, /INIT 16, /INITs 18, /ENABLE 20, /ENABLEs 22, when a LOW, or &#34;0&#34; is put on pin 4. In effect, the decoder outputs tell which of the logic blocks 16, 18, 20, 22 is activated. 
     As will be recognized by a person skilled in the art, without such programmability, to provide the possibility of having all such signals available, four inputs would be required. 
     Furthermore, using gate minimization design, the embodiment as shown in FIG. 4 can be reduced in size as shown in FIG. 6. 
     The foregoing description of the preferred embodiment of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. It is possible that the invention may be practiced in other technologies, such as with other MOS or even bipolar processes. The scope of the invention can be defined by the claims appended hereto and their equivalents.