Abstract:
A RESURF LDMOS transistor ( 32 ) has a drain region including a first region ( 24 ) and a deep drain buffer region ( 34 ) surrounding the first region. The first region is more heavily doped than the deep drain buffer region. The deep drain buffer region improves the robustness of the transistor.

Description:
FIELD OF THE INVENTION 
     This invention relates to semiconductor devices and, more particularly, to a RESURF (REduced SURf ace Field) LDMOS (lateral double-diffused “metal” N-oxide-semiconductor) device having a deep buffer implant in the drain region and method of fabrication thereof. 
     BACKGROUND OF THE INVENTION 
     LDMOS devices are the devices of choice in the 20-60V range. LDMOS devices are very easy to integrate into a CMOS or BiCMOS process thereby facilitating the fabrication of control, logic, and power switches on a single chip. In the 20-60V range, optimized LDMOS devices are also much more efficient in terms of on-state voltage and switching losses than power bipolar junction transistors or other hybrid MOSbipolar devices. 
     Optimized LDMOS design seeks to provide power switches with very low specific on-state resistance (Rsp) while maintaining high switching speed. A low Rsp helps reduce power losses as well as the size of the die. RESURF LDMOS or RLDMOS devices are very attractive in this respect as they offer very good trade-off between Rsp and breakdown voltage (BV) capability compared to non-RLDMOS devices. RLDMOS devices use the Reduced Surface electric field phenomenon to increase the drift region doping for a given breakdown voltage. The increased drift region doping causes reduction in the drift region resistance leading to an overall lower Rsp for the device. 
     As device size shrinks, the desire to maintain as wide a Safe Operating Area (SOA) as possible remains, since the applications these devices are used in remain the same. However, shrinking RESURF LDMOS device size has a negative impact on the robustness of the device. Accordingly, a need exists for a RESURF LDMOS device having improved robustness. 
     SUMMARY OF THE INVENTION 
     Applicants have discovered that factors contributing to the failure of conventional RLDMOS devices during reverse breakdown include the presence of a high electric field at the location where the RESURF region overlaps the n+drain region and a correspondingly high impact ionization rate near the drain region and low snap back current. 
     Generally, and in one form of the invention, a transistor includes: 
     a semiconductor layer of a first conductivity type; 
     a RESURF region of a second conductivity type formed in the semiconductor layer; 
     a LOCOS field oxide region formed at a face of the RESURF region, the RESURF region being self-aligned to the LOCOS field oxide region; 
     a well of the first conductivity type formed in the semiconductor layer; 
     a source region of the second conductivity type formed in the well, a channel region defined in the well between a first edge of the source region and a first edge of the RESURF region; 
     a drain region of the second conductivity type formed in the semiconductor layer adjacent a second edge of the RESURF region, the drain region including a first region extending from the face of the semiconductor layer to a first distance below the face of the semiconductor layer and a second region surrounding the first region and extending a second distance below the face of the semiconductor layer, the first distance being less than the second distance and the first region being more heavily doped than the second region; and 
     a conductive gate formed over and insulated from the channel region. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings: 
     FIG. 1 is a cross-sectional elevation view of a RESURF LDMOS transistor according to the prior art; 
     FIG. 2 shows the measured BV (breakdown voltage) curve at room temperature for a device according to FIG. 1; 
     FIG. 3 shows a simulated BV curves at room temperature for the device of FIG.  1  and the device of FIG. 10; 
     FIGS. 4-5 show plots of doping concentration, carrier concentration and electric field profiles in the device of FIG. 1 near the surface under different current conditions; 
     FIG. 6, shows hole and electron current during breakdown for the devices of FIG.  1  and FIG. 10; 
     FIG. 7 shows the impact ionization rate for the device of FIG. 1 for Ids= 10 A, the snap back current of the device; 
     FIG. 8 shows a plot of doping concentration, carrier concentration and electric field profiles in the device of FIG. 1 near the surface for Ids= 10 A; 
     FIG. 9 is a plot showing the destructive UIS behavior of the device of FIG. 1; 
     FIG. 10 shows an RLDMOS device in accordance with the present invention 
     FIGS. 11-16 are cross-sectional elevation views showing the RLDMOS transistor of FIG. 10 at successive stages during fabrication; 
     FIG. 17 shows a plot of doping concentration, carrier concentration and electric field profiles in the device of FIG. 10 at Ids= 0 A; 
     FIG. 18 shows the impact ionization rate for the device of FIG. 10 for Ids= 10 A; 
     FIGS. 19 and 20 show the destructive UIS behavior of the device of FIG.  10 . 
    
    
     Corresponding numerals and symbols in the different figures refer to corresponding parts unless otherwise indicated. 
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows an RLDMOS transistor  10  according to the prior art. Transistor  10  is fabricated in a p− epitaxial layer  14  formed over p+substrate  12 . Transistor  10  includes a p well  16  in epitaxial layer  14 . An n+source region  22  and p+ backgate contact region  20  are formed in p well  16 . Transistor  10  also includes n+ drain region  24  and an n type RESURF region  18  formed in epitaxial layer  14 . RESURF region  18  is self-aligned to LOCOS field oxide region  28 . A gate oxide layer  26  is formed at the face of epitaxial layer  14 . Polysilicon gate  30  extends over gate oxide layer  26  and a portion of LOCOS field oxide region  28 . 
     FIG. 2 shows the measured BV (breakdown voltage) curve at room temperature for a device according to FIG. 1 having a distance L=3.3 microns, distance M=2.0 microns, and device area=8e−3 cm 2  with p- epi doping and n- type resurf implant dose chosen to obtain about 45V BVdss (drain-source breakdown voltage with gate shorted to source). 
     FIG. 3 shows a simulated BV curve  1  at room temperature for the device of FIG.  1 . As seen in FIG. 3, the device of FIG. 1 snaps back at about 10 amps around 70-75 volts. The primary reason for UIS (unclamped inductive switching) failure is non-uniform snap back in the device leading to current hogging and excessive heating. 
     FIG. 4 shows a plot of doping concentration, carrier concentration and electric field profiles in the device of FIG. 1 near the surface under low current conditions (point a in FIG.  3 ). As can be seen in FIG. 4, there are no electrons and holes in the “depletion” region, where “depletion” region is defined as the region with the device where the bulk of the applied voltage drops. As such the electric field in the depletion region is determined solely by the doping concentrations. Due to the curvature near the bird&#39;s beak, the electric field is very high near the bird&#39;s beak. As a result there is a very high impact ionization generation rate near the bird&#39;s beak leading to the breakdown of the device. 
     FIG. 5 shows a plot of doping concentration, carrier concentration and electric field profiles in the device of If FIG. 1 near the surface under high current conditions (point b in FIG.  3 ). As can be seen in FIG. 5, there is a significant concentration of electrons and holes in the depletion region. As such, the electric field distribution in the drift region is now determined by the sum total of charge present in the depletion region. The net charge at any given place in the drift region is given as: 
     
       
         N + =N D +P−n 
       
     
     Where N D  is the donor density, p is the hole concentration, and n is the electron concentration. The field near the bird&#39;s beak (point c) remains essentially the same due to presence of a comparable number of holes and electron carriers. The field inside the resurf region depends on the two dimensional distribution of carriers within the drift region. This field increases (point d) due to an increase in net positive charge. This electric filed inside the drift region is less than that under the bird&#39;s beak but applicants have discovered that it leads to an increase in breakdown voltage at high current. 
     FIG. 6, shows hole and electron current during breakdown. As can be seen from FIG.  6  and FIG. 3, the parasitic NPN transistor formed by n+ drain  24 , p type regions  14  and  16 , and n+ source region  22  turns on at lower current than the snap back current value. 
     In addition to the BV of the parasitic NPN operating in the active region and the resurf region charge modulation, the snap back current also depends upon the impact ionization generation rate throughout the resurf region. FIG. 7 shows the impact ionization rate for the device of FIG. 1 for Ids= 10 A, the snap back current of the device. In addition to impact ionization near the bird&#39;s beak, the device of FIG. 1 shows a high impact ionization generation rate near the drain side. 
     FIG. 8 shows a plot of doping concentration, carrier concentration and electric field profiles in the device of FIG. 1 near the surface for Ids= 10 A. The high impact ionization generation rate near the drain side in the device of FIG. 1 (seen in FIG. 6) causes an increase in hole concentration in the resurf region as seen in FIG.  7 . In addition, the field near the bird&#39;s beak (point c) also increases dramatically. 
     FIG. 9 is a plot showing the destructive UIS behavior of the device of FIG.  1 . As seen in FIG. 9, the device of FIG. 1 fails at 8-8.2A 
     FIG. 10 shows an RLDMOS device  32  in accordance with the present invention. Device  32  is identical to device  10  of FIG. 1 with the exception that the drain region includes, in addition to n+ region  24 , a deep drain n buffer implant region  34 . Region  34  surrounds region  24 . 
     FIGS. 11-16 are cross-sectional elevation views showing transistor  32  of FIG. 10 at successive stages during fabrication. As seen in FIG. 10, fabrication of LDMOS transistor  32  begins with the formation of p− epitaxial layer  14  on p+ substrate  12 . A pad oxide layer  36  is then formed over p− epitaxial layer  14 . A layer of photoresist  38  is deposited over oxide layer  36  and patterned and etched to expose a D well region. Implants of p and n type dopants, with the n type having substantially less diffusivity than the p type, such as arsenic and boron, are sequentially performed to form p− region  16  and n− region  40 . Photoresist layer  38  is then removed. 
     As seen in FIG. 12, nitride layer  42  and photoresist layer  44  are formed over oxide layer  36  and patterned and etched to expose a resurf region. An n type implant, using arsenic, for example, is performed to form resurf region  18 . 
     As seen in FIG. 13, field oxide region  28  is then hermally grown in the exposed region over resurf region  18 . Resurf region  18  is thus self-aligned to field oxide region  28 . Oxide and nitride layers  36  and  38  are then removed and a thin gate oxide layer  26  is formed over the face of epitaxial layer  14 . A polysilicon layer is then deposited over gate oxide layer  26  and field oxide region  28  and patterned and etched to form gate  30 . 
     As seen in FIG. 14, a layer of photoresist  46  is formed over the device and patterned and etched to expose the drain region. An n type implant, using phosphorous, for example, is performed to form the deep drain n buffer region  34 . 
     Photoresist layer  46  is then removed and a layer of photoresist  48  is then formed over the device and patterned and etched to expose the backgate contact region as shown in FIG. 15. A p type implant, using boron, for example, is then performed to form p+ backgate contact region  20 . 
     Photoresist layer  48  is then removed and a layer of photoresist  50  is then formed over the device and patterned and etched to expose the source and drain regions as shown in FIG.  16 . An n type implant, using arsenic, phosphorous, or both, for example, is then performed to form n+ source region  22  and n+ drain region  24 . 
     FIG. 17 shows a plot of doping concentration, carrier concentration and electric field profiles in the device of FIG. 10 at Ids= 0 A and having L=3.3 microns, M=2.3 microns, and area=8e−3cm 2 . As seen in FIG. 17, the electric field crowding near the bird&#39;s beak of the drain side present in FIG. 8 (point c) has been reduced as has hole concentration in the resurf region. 
     FIG. 18 shows the impact ionization rate for the device of FIG. 10 for Ids= 10 A. As can be seen, the device of FIG. 10 has not snapped back. In addition to impact ionization near the bird&#39;s beak, is much lower than that of the device  10  of FIG.  1 . This is due to the fact that the deeper drain side buffer implant region helps the depletion region to spread out reducing the electric field crowding near the bird&#39;s beak of the drain side. 
     The device of FIG. 10, when fabricated with the dimensions given above, has a snap back current of  15 A and simulated breakdown curve shown at  3  in FIG.  3 . The device of FIG. 10 can be fabricated with the same dimensions as the device of FIG. 1 (i.e. L=3.3 microns, M=2.0 microns, and area=8e−3cm 2 ) and improvements in snap back current still result. In this case, snap back current is 11.3A and a simulated breakdown curve is shown at  2  in FIG.  3 . With either set of dimensions, a significant improvement over the snap back current of  10 A for the device of FIG. 1 results. The use of a longer drift region M produces a higher snap back current because the longer drift region helps produce a lower electric field and therefore a lower impact ionization rate near the drain side as the depletion region can spread out more. 
     FIG. 19 shows the destructive UIS behavior of the device of FIG. 10, with L=3.3 microns, M=2.0 microns, and area=8e−3cm 2 . As seen in FIG. 19, the device fails at 99.5A. FIG. 20 shows the destructive UIS behavior of the device of FIG. 10, with L=3.3 microns, M=2.3 microns, and area=8e−3cm 2 . As seen in FIG. 20, the device fails at 12.5-13A 
     A preferred embodiment has been described in detail hereinabove. It is to be understood that the scope of the invention also comprehends embodiments different from that described, yet within the scope of the claims. For example, a RESURF LDMOS transistor  32  that is a PMOS transistor could be formed by changing regions of N type conductivity to P type and regions of P type to N type. In addition, instead of forming the RESURF LDMOS transistor directly in the epitaxial layer, it could be formed in a deep well in an epitaxial layer, the deep well being of the same conductivity type as the DWELL. The use of deep wells of opposite conductivity types would thus permit both PMOS and NMOS transistors to be formed on a single chip. 
     While this invention has been described with reference to an illustrative embodiment, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiment, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.