Abstract:
There is provided a technology that can reduce the number of signal lines by encoding a PWM signal used in a display driver IC. The display driver circuit for displaying a gradation on a display screen based on a PWM signal includes a PWM signal generator for generating a PWM signal, a PWM encoder for encoding the PWM signal generated from the PWM signal generator, a PWM decoder for decoding the encoded PWM signal into the PWM signal, a switching unit for selectively outputting the PWM signal generated from the PWM decoder, a data storage unit for storing a display data used to switch the switching unit, and an SRAM decoder for outputting an on/off signal to the switching unit according to the display data outputted from the data storage unit.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to a driver circuit for driving a display screen in a liquid crystal display (LCD) or the like; and, more particularly, to a technology that can reduce the number of signal lines by encoding a pulse width modulation (PWM) signal used to implement a gradation display function in a display driver integrated circuit (IC).  
       DESCRIPTION OF RELATED ART  
       [0002]     In driving a liquid crystal display (LCD) or the like, an active addressing technology is recently used to display an image having a plurality of gradation levels. A representative method is a Frame Rate Control (FRC) method, a Pulse Width Modulation (PWM) method, and an Amplitude Modulation (AM) method.  
         [0003]      FIG. 1  illustrates a structure of a circuit used to display a PWM-based gradation in a conventional 256-color LCD driver integrated circuit (IC) having a PWM gradation display function.  
         [0004]     Referring to  FIG. 1 , PWM signals generated from a PWM generator  1  are transmitted to an entire system along 24 (=3×8=3×2 3 ) signal lines  2 .  
         [0005]     In order to represent 256 colors, an SRAM  3  stores 8-bit display data. 3 bits of the 8-bit data represent a red (R) gray scale, and 3 bits represent a green (G) gray scale. The remaining 2 bits and an external 1 bit represent a blue (B) gray scale.  
         [0006]     The gray scales of R, G and B colors are determined by the respective 3-bit data and thus eight PWM signals are required. A total of 24 PWM signals are used to represent the entire R, G and B colors.  
         [0007]     The SRAM  3  outputs data of X addresses 0 to n at the same time so as to display one line of an LCD panel. The respective 3-bit data turn on one of eight switches through a 3×8 SRAM decoder  4  and one selected PWM signal is outputted.  
         [0008]     At this point, the PWM signals are designed to pass through the upper portion of the SRAM within the LCD driver IC and they occupy a wide area. Also, signal interference often occurs between the signal lines. Therefore, if the circuit is badly designed, it may have a bad influence on the operation of the circuit.  
         [0009]     Further, in recent years, there is a demand for 4,096 colors or 65K colors in the display. In this case, if the display driver IC is designed using the conventional method, 48 PWM signal lines are required for 4,096 colors and 128 PWM signal lines are required for 65K colors. Accordingly, the signal lines occupy a wide area in the entire IC and it is difficult to scale down the circuit.  
       SUMMARY OF THE INVENTION  
       [0010]     It is, therefore, an object of the present invention to provide a technology that can reduce the number of signal lines by encoding a PWM signal used to implements a gradation display function in a display driver IC, thereby reducing an area occupied by the signal lines and reducing an interference between the signal lines.  
         [0011]     In accordance with an aspect of the present invention, there is provided a display driving method for displaying a gradation on a display screen based on a PWM signal. The display driving method includes the steps of: encoding a PWM signal; decoding the encoded PWM signal into the PWM signal; and displaying a gradation on a display screen based on the decoded PWM signal.  
         [0012]     In accordance with another aspect of the present invention, there is provided a display driver circuit for displaying a gradation on a display screen based on a PWM signal, the display driver circuit including: a PWM signal generator for generating a PWM signal; a PWM encoder for encoding the PWM signal generated from the PWM signal generator; a PWM decoder for decoding the encoded PWM signal into the PWM signal; a switching means for selectively outputting the PWM signal generated from the PWM decoder; a data storage means for storing a display data used to switch the switching means; and an SRAM decoder for outputting an on/off signal to the switching means according to the display data outputted from the data storage means.  
         [0013]     In accordance with a further another aspect of the present invention, there is provided a display driver circuit for displaying a gradation on a display screen on a PWM signal, the display driver circuit including: a PWM signal generator for generating an encoded PWM signal; a PWM decoder for decoding the encoded PWM signal into the PWM signal; a switching means for selectively outputting the PWM signal generated from the PWM decoder; a data storage means for storing a display data used to switch the switching means; and an SRAM decoder for outputting an on/off signal to the switching means according to the display data outputted from the data storage means.  
         [0014]     If 2 n  PWM signals are used, the PWM signal generator generates (n+1) signals by using n signals and a PWM signal having a longest pulse width.  
         [0015]     In the case of a 256-color display, the PWM signal generator generates 4 signals, based on 8 PWM signals (PW 0 , PW 1 , PW 2 , PW 3 , PW 4 , PW 5 , PW 6  and PW 7 , whose pulse widths become longer from PW 0  to PW 7  in this order), the 4 signals being given by a Boolean algebra expression below. 
 
 E   0 ={overscore ( PW   0 )}· PW   1 +{overscore ( PW   2 )}+ PW   3 +{overscore ( PW   4 )}+ PW   5 +{overscore ( PW   6 )}· PW   7  
 
 E   1 ={overscore ( PW   1 )}· PW   3 +{overscore ( PW   5 )}· PW   7  
 
 E   2 ={overscore ( PW   3 )}· PW   7  
 
PW 7  
 
         [0016]     The PWM decoder generates an intermediate signal by using a Boolean algebra expression below 
 
 D   0 = PW   7 ·{overscore ( E   2 )}·{overscore ( E   1 )}·{overscore ( E   0 )}
 
 D   1 = PW   7 ·{overscore ( E   2 )}·{overscore ( E   1 )}· E   0  
 
 D   2 = PW   7 ·{overscore ( E   2 )}· E   1 ·{overscore ( E   0 )}
 
 D   3 = PW   7 ·{overscore ( E   2 )}· E   1 · E   0  
 
 D   4 = PW   7 · E   2 ·{overscore ( E )}· E   0  
 
 D   5 = PW   7 · E   2 ·{overscore ( E   1 )}· E   0  
 
 D   6 = PW   7 · E   2 · E   1 ·{overscore ( E   0 )}
 
D 7 =PW 7  
        and decodes the intermediate signal into a final PWM signal by using a Boolean algebra expression below 
 
PW 0 =D 0  
 
 PW   1 = PW   0 + D   1  
 
 PW   2 = PW   1 + D   2  
 
 PW   3 = PW   2 + D   3  
 
 PW   4 = PW   3 + D   4  
 
 PW   5 = PW   4 + D   5  
 
 PW   6 = PW   5 + D   6  
 
PW 7 =D 7  
       
 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]     The above and other objects and features of the instant invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:  
         [0019]      FIG. 1  illustrates a structure of a conventional display driver IC having a PWM gradation display function;  
         [0020]      FIG. 2  illustrates a structure of a display driver IC in accordance with a preferred embodiment of the present invention;  
         [0021]      FIG. 3  is a timing chart of an encoded PWM signal generated from a PWM encoder shown in  FIG. 2 ;  
         [0022]      FIG. 4  is a timing chart illustrating a process of decoding the encoded PWM signal at a PWM decoder shown in  FIG. 2 ;  
         [0023]      FIG. 5  is a circuit diagram of a PWM decoder, a PWM encoder and an SRAM decoder shown in  FIG. 2 ;  
         [0024]      FIG. 6  is a logic circuit diagram of a PWM encoder shown in  FIG. 5 ;  
         [0025]      FIG. 7  is a logic circuit diagram of a PWM decoder shown in  FIG. 5 ;  
         [0026]      FIG. 8  is a logic circuit diagram of an SRAM encoder and a switching block; and  
         [0027]     FIGS.  9  to  12  are timing charts of signals shown in FIGS.  5  to  8 .  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0028]     Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.  
         [0029]      FIG. 2  is a circuit diagram of a display driver IC in accordance with a preferred embodiment of the present invention.  
         [0030]     A basic structure of the circuit shown in  FIG. 2  is similar to that of the conventional circuit shown in  FIG. 1 . That is, PWM signals are generated from a PWM signal generator  11  so as to represent the gradation and are transmitted to an entire system along PWM signal lines  12 . Switches  17  are turned on/off by an SRAM decoder  14 , based on display data stored in an SRAM. In this manner, the transmission of the PWM signals is controlled.  
         [0031]     However, the display driver IC further includes a PWM encoder  15  and a PWM decoder  16  on a signal path directed from the PWM signal generator  11  and thus the number of the PWM signal lines  12  is reduced.  
         [0032]     In  FIG. 2 , the number of the PWM signal lines is 12 (=3×4). Compared with the 24 (=3×8) signal lines shown in  FIG. 1 , the number of the PWM signal lines is reduced by half.  
         [0033]     The PWM signals generated from the PWM signal generator  11  of  FIG. 2  are identical to those of  FIG. 1 . As shown in  FIG. 3 , the PWM signals are classified into PW 0 , PW 1 , PW 2 , PW 3 , PW 4 , PW 5 , PW 6  and PW 7 . At this point, it is assumed that the pulse widths of the PWM signals are lengthened from PW 0  to PW 7  by one unit.  
         [0034]     The PWM signals from the PWM signal generator  11  are encoded by a PWM encoder  15  and transmitted to an entire system. The signals transmitted to the respective blocks are decoded later into the original PWM signals by a PWM decoder  16 , thereby outputting the desired PWM waveforms.  
         [0035]      FIG. 3  is a timing chart illustrating a process of encoding the PWM signals at the PWM encoder  15 .  
         [0036]     Referring to  FIG. 3 , the PWM signals are generated as many as 2 n  signals. Since the 2 n  signals have a different pulse width, they are divided into 2 n  if portions where the pulse width is changed are divided by a timing interval.  
         [0037]      FIG. 3  illustrates an embodiment when 8 (=23) PWM signals are used to display 256 colors. In this embodiment, each of R, G and B has 2-bit data and 8 PWM signals corresponding to 3-bit data. Also, if portions where 8 PWM signals are changed are divided based on the pulse width, the signals can be divided into 8 PWM signals having a different pulse width. Here, it is assumed that the PWM signals PW 0 , PW 1 , PW 2 , PW 3 , PW 4 , PW 5  PW 6  and PW 7  have the increasing pulse width in this order.  
         [0038]     In  FIG. 3 , in case where the 2 n  PWM signals (8 PWM signals in  FIG. 3 ) are used, the encoding process using the PWM signals generates (n+1) encoded PWM signals. The (n+1) encoded PWM signals include n encoded PWM signals (3 signals in  FIG. 3 , i.e., E 0  to E 2 ) and one PWM signal (PW 7  in  FIG. 7 ). Here, the n encoded PWM signals are processed by a predefined method and the PWM signal PW 7  has the longest pulse width and is used to distinguish a portion where there is the signal from a portion where there is no signal.  
         [0039]     The encoded PWM signals can be generated based on the PWM signals by a following method.  
         [0040]     For example, in case where 8 PWM signals of the 256-color display shown in  FIG. 3  are used, the divided 8 PWM signals can be represented by 3 encoded signals and a PWM signal (PW 7 ) having the longest pulse width.  
         [0041]     4 output signals of the PWM encoder, which are generated from the 8 PWM signals, are E 0  ( 20 ), E 1  ( 21 ), E 2  ( 22 ) and PW 7 .  
         [0042]     Here, the E 0  signal is a signal having 20 digits and a Boolean algebra can be expressed as 
 
 E   0 ={overscore ( PW   0 )}· PW   1 +{overscore ( PW   2 )}· PW   3 +{overscore ( PW   4 )}· PW   5 +{overscore ( PW   6 )}· PW   7  
 
 AS can be seen, the encoded signals are generated by combining two adjacent PWM signals. 
 
         [0043]     The E 1  signal is a signal having 21 digits and is generated by combining second, fourth, sixth and eighth PWM signals, which can be expressed as 
 
 E   1 ={overscore ( PW   1 )}· PW   3 +{overscore ( PW   5 )}· PW   7  
 
         [0044]     The E 2  signal is a signal having 22 digits and is generated by combining the fourth and eight PWM signals, which can be expressed as 
 
 E   2 ={overscore ( PW   3 )}· PW   7  
 
         [0045]     Although the PWM signals required for 256 colors are shown in  FIG. 3 , the PWM signals for 4,096 colors or 65K colors or higher can also be encoded by the above-described method.  
         [0046]     For example, the number of the PWM signal lines for 4,096 colors is 15 (5×3 (R, G, B)), and the number of the PWM signal lines for 65K colors is 21 (=7×3 (R, G, B)).  
         [0047]     The encoded signals are transmitted to the respective processing blocks and are converted into the original PWM signals (in the case of the 256 colors, 8 PWM signals) by the PWM decoder  16 .  
         [0048]      FIG. 4  is a timing diagram illustrating a process of decoding the encoded PWM signals into the original PWM signals.  
         [0049]     The decoding process can be carried out by two steps.  
         [0050]     The first step is to generate waveforms D 0 , D 1 , D 2 , D 3 , D 4 , D 5 , D 6  and D 7  shown in  FIG. 4 .  
         [0051]     The waveforms are generated using the following Boolean algebra expression. 
 
 D   0 = PW   7 ·{overscore ( E   2 )}·{overscore ( E   1 )}·{overscore ( E   0 )}
 
 D   1 = PW   7 ·{overscore ( E   2 )}·{overscore ( E   1 )}· E   0  
 
 D   2 = PW   7 ·{overscore ( E   2 )}· E   1 ·{overscore ( E   0 )}
 
 D   3 = PW   7 ·{overscore ( E   2 )}· E   1 · E   0  
 
 D   4 = PW   7 · E   2 ·{overscore ( E   1 )}·{overscore ( E   0 )}
 
 D   5 = PW   7 · E   2 ·{overscore ( E   1 )}· E   0  
 
 D   6 = PW   7 · E   2 · E   1 ·{overscore ( E   0 )}
 
D 7 =PW 7  
 
         [0052]     Next, the PWM signals are decoded in the second step of  FIG. 2 . The finally decoded signals PW 0 , PW 1 , PW 2 , PW 3 , PW 4 , PW 5 , PW 6  and PW 7  are generated by carrying out an OR logic operation based on the following Boolean algebra expression. 
 
PW 0 =D 0  
 
 PW   1 = PW   0 + D   1  
 
 PW   2 = PW   1 + D   2  
 
 PW   3 = PW   2 + D   3  
 
 PW   4 = PW   3 + D   4  
 
 PW   5 = PW   4 + D   5  
 
 PW   6 = PW   5 + D   6  
 
PW 7 =D 7  
 
         [0053]     Meanwhile, the above encoding and decoding methods can be applied to the case where the number of the PWM signals is increased.  
         [0054]     The SRAM  13  stores the 8-bit display data so as to represent the 256 colors. 3 bits of the 8-bit data represent a red (R) gray scale, and 3 bits represent a green (G) gray scale. The remaining 2 bits and an external 1 bit represent a blue (B) gray scale.  
         [0055]     The SRAM  3  outputs data of X addresses 0 to n at the same time so as to display one line of an LCD panel. The respective 3-bit data turn on one of  8  switches through a 3×8 SRAM decoder  14  and one selected PWM signal is outputted.  
         [0056]      FIG. 5  is a circuit diagram illustrating the connection of the PWM decoder, the PWM encoder, the SRAM decoder and the PWM signal generator (not shown) shown in  FIG. 2 .  
         [0057]     In  FIG. 5 , the PWM encoder and the PWM decoder are configured with independent ICs. The signal lines between the PWM encoder and the PWM decoder include 4 signal lines. That is, the 4 signal lines include 3 signal lines (E 0 , E 1  and E 2 ) for the encoded PWM signals and the PW 7  signal line for the uppermost PWM signal. This display driver IC supports the 256 colors.  
         [0058]     However, the present invention is not limited to it.  
         [0059]     For example, the PWM decoder  16  can be integrated in a single chip together with the SRAM decoder  14  and can include the switches  17 .  
         [0060]     In addition, the PWM  15  can be integrated in a single chip together with the PWM signal generator  11 . In case of the integrated single chip, the PWM signal generator  11  and the PWM encoder  15  can be integrated physically and functionally. That is, the PWM signal generator  11  can be designed to directly generate the encoded PWM signals E 0 , E 1 , E 2  and PW 7 , instead of the PWM signals PW 0 , PW 1 , PW 2 , PW 3 , PW 4 , PW 5  and PW 6 .  
         [0061]      FIG. 6  is a logic circuit diagram of the PWM encoder  15  configured based on the Boolean algebra expression described in the above example. The PWM encoder  15  receives the input signals PW 0 , PW 1 , PW 2 , PW 3 , PW 4 , PW 5 , PW 6  and PW 7  from the PWM signal generator  11  and outputs the output signals E 0 , E 1  and E 2 , as shown in  FIG. 3 .  
         [0062]      FIG. 7  is a logic circuit diagram of the PWM decoder  16  based on the Boolean algebra expression described in the above example.  
         [0063]     The PWM decoder  16  outputs the PWM signals PW 0 , PW 1 , PW 2 , PW 3 , PW 4 , PW 5 , PW 6  and PW 7  by using the encoded PWM signals E 0 , E 1  and E 2  and the longest PWM signal PW 7 , which are generated from the PWM encoder  15  and transmitted along the signal lines  12 .  
         [0064]      FIG. 8  is a schematic circuit diagram of the 3×8 SRAM decoder  14  and the switch circuit. One of the 8 PWM signals PW 0 , PW 1 , PW 2 , PW 3 , PW 4 , PW 5 , PW 6  and PW 7  is selected based on the display data DD outputted from the SRAM encoder  14 .  
         [0065]      FIG. 9  is a timing diagram of the signals when the PWM signals are encoded by the PWM encoder  15 .  
         [0066]     Also,  FIG. 10  is a timing diagram of the signals PW 0 , D 1 , D 2 , D 3 , D 4 , D 5 , D 6  and D 7  in the first step when the encoded signals are decoded by the PWM decoder  16  of  FIG. 7 .  FIG. 11  is a timing diagram of the signals after the PWM signals are decoded using the output signal of the first step.  
         [0067]      FIG. 12  is a timing diagram illustrating the final waveform of the output stage through which the SRAM signals corresponding to the PWM signals are outputted according to the display data of the SRAM by using the output signals of the second step shown in  FIG. 11 .  
         [0068]     As can be seen from FIGS.  9  to  12 , the elements of  FIG. 5  correctly carry out their functions.  
         [0069]     The present invention can be applied to the case of 4,096 colors or the case of 65K colors, in addition to the case of 256 colors.  
         [0070]     The LCD display driver IC having the PWM-based gradation display function is designed to perform the encoding operation on the PWM signal transmission path. Accordingly, it is possible to reduce the number of the PWM signal lines and the entire area of the IC. In addition, the noise between the signal lines can be reduced. Further, it is possible to minimize the increase of the chip size, which is caused by the increase in the number of colors.  
         [0071]     The present application contains subject matter related to Korean patent application No. 2004-27515, filed in the Korean Patent Office on Apr. 21, 2004, the entire contents of which being incorporated herein by reference.  
         [0072]     While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.