Abstract:
An apparatus for supplying an internal voltage is provided the apparatus for supplying an internal voltage comprises: a comparison unit for comparing a reference voltage with an internal reference voltage to output a driving signal based on the comparison result; an internal voltage providing unit for providing the internal voltage according to the current value of the driving signal; a first biasing unit for providing a first bias current to the comparison unit according to the reference voltage; and a second biasing unit for providing a second bias current to the comparison unit according to a standby operation mode.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to an apparatus for supplying an internal voltage for use in a semiconductor memory device.  
       DESCRIPTION OF RELATED ARTS  
       [0002]     Generally, in accordance with the demands for high speed, high density and low power in a memory device, a memory device converts an external power into an internal voltage having a lower level than an external power and use for a core voltage, a peripheral voltage, a voltage for delay locked loop (DLL), a bit line pre-charge voltage, and a cell plate voltage.  
         [0003]     The memory device generates the internal voltage by converting the external power or pumping charge using the external power.  
         [0004]     A method for generating the internal voltage by converting the external power uses a unit gain amplifier with a current mirror and a buffer.  
         [0005]     The operation of the memory device should be stably maintained regardless of variations of the external power. The power consumption for operating the memory device is reduced by providing the current needed during a standby mode and an active mode of the memory device using the internal voltage above.  
         [0006]     That is, it is advantageous to use the internal voltage to maintain a predetermined certain level instead of using the external power directly for operation of the memory device as it is, in regard to reliability and power consumption.  
         [0007]     Furthermore, the internal voltage may be provided to prepare drivers in regard to an operation mode of the memory device, i.e., standby mode or active mode, to reduce power consumption.  
         [0008]      FIG. 1  is a schematic diagram illustrating a conventional apparatus for supplying an internal voltage for use in a memory device.  
         [0009]     The conventional apparatus for supplying an internal voltage of the memory device includes: a comparison unit  1 ; a biasing unit  2 ; a current control unit  3 ; a load unit  4 ; and a capacitor unit  5 .  
         [0010]     The comparison unit  1  includes an inverter IV 1 , PMOS transistors P 1  to P 4  wherein PMOS transistors P 2  and P 3  form a current mirror, and NMOS transistors N 1  and N 2 . The comparison unit  1  compares a reference voltage VREF with an internal reference voltage Vint_REF to output a driving signal DRV.  
         [0011]     The biasing unit  2  connected between the comparison unit  1  and a ground voltage VSS includes an NMOS transistor N 3 , wherein the reference VREF is inputted at the gate of the NMOS transistor N 3 . The NMOS transistor N 3  is turned on while the reference VREF provides a stable reference voltage in order to control a bias state of the comparison unit  1 .  
         [0012]     The current control unit  3  includes PMOS transistors P 5  to P 7  connected in parallel between a supply terminal of an external voltage VDD and an output terminal of an internal voltage Vint, wherein the driving signal DRV is inputted at each gate of the PMOS transistors P 5  to P 7 .  
         [0013]     The load unit  4  connected between the output terminal of the internal voltage Vint and a supply terminal of the ground voltage VSS includes PMOS transistors P 8  and P 9 , wherein each gate of PMOS transistors P 8  and P 9  is connected to each drain of the same for performing an operation as a diode.  
         [0014]     Also, the capacitor unit  5  connected between the output terminal of the internal voltage Vint and a supply terminal of the ground voltage VSS includes a first capacitor CP 1  made using a PMOS transistor and a second capacitor CN 1  made using an NMOS transistor for maintaining the voltage levels of the internal voltage and the internal reference voltage Vint_REF.  
         [0015]     A size of the NMOS transistor N 3  in a biasing unit  2  with the above described configuration is closely related to an enable characteristic and standby current consumption of the comparison unit  1 .  
         [0016]     Because the internal voltage is used periodically in the semiconductor memory device, there is a periodic current consumption by the apparatus used to supply the internal voltage. Therefore, the voltage level of internal voltage being outputted to the output node (A) fluctuates.  
         [0017]     It is important to recover the voltage level of internal voltage back to the original level as fast as possible. If the voltage level of the internal voltage is not quickly recovered, the semiconductor memory device using the internal voltage may not operate stably.  
         [0018]     Thus, to supply the stable voltage level of the internal voltage, the size of the NMOS transistor N 3  in a biasing unit  2  must be increased sufficiently.  
         [0019]     However, as the size of the NMOS transistor N 3  in a biasing unit  2  become larger, an amount of the current flowing in the NMOS transistor N 3  is increased to thereby increase standby current of the apparatus for supplying an internal voltage.  
         [0020]     Therefore, there is a limitation that the conventional apparatus unnecessarily consumes a large amount of current when the amount of current required for stably generating the internal voltage is very small, e.g., during a self refresh mode.  
       SUMMARY OF THE INVENTION  
       [0021]     It is, therefore, an object of the present invention to provide an apparatus for supplying an internal voltage with the characteristic of optimizing current consumption based on an operation mode of semiconductor memory device.  
         [0022]     In accordance with an aspect of the present invention, there is provided an apparatus for supplying an internal voltage, comprising: a comparison unit for comparing a reference voltage with an internal reference voltage to output a driving signal based on the comparison result; an internal voltage providing unit for providing the internal voltage according to the current value of the driving signal; a first biasing unit for providing a first bias current to the comparison unit according to the reference voltage; and a second biasing unit for providing a second bias current to the comparison unit according to a standby operation mode. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0023]     The above and other objects and features of the present invention will become better understood with respect to the following description of the specific embodiments given in conjunction with the accompanying drawings, in which:  
         [0024]      FIG. 1  is a schematic diagram illustrating a conventional apparatus for supplying an internal voltage for use in memory device; and  
         [0025]      FIG. 2  is a schematic diagram illustrating an apparatus for supplying an internal voltage in accordance with a specific embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0026]     An apparatus for supplying an internal voltage in accordance with specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.  
         [0027]      FIG. 2  is a schematic diagram illustrating an apparatus for supplying an internal voltage in accordance with a specific embodiment of the present invention.  
         [0028]     The specific embodiment of the present invention includes: a comparison unit  10 ; an internal voltage providing unit  20 ; a first biasing unit  30 ; and a second biasing unit  40 .  
         [0029]     The comparison unit  10  includes an inverter IV 2 , PMOS transistors P 10  to P 13  wherein PMOS transistors P 11  and P 12  forms a current mirror, and NMOS transistors N 4  and N 5 . The comparison unit  10  compares a reference voltage VREF with an internal reference voltage Vint_REF to output a driving signal DRV.  
         [0030]     Herein, a reference circuit using band gap type or widlar type, although not illustrated, is used to generate a uniform level of the reference voltage VREF, regardless of a variation of an external power, temperature and process.  
         [0031]     The reference voltage VREF maintaining uniform level regardless of a variation of an external power, temperature and process is inputted into a gate of the NMOS transistor N 4 .  
         [0032]     The internal voltage providing unit  20  includes a current control unit  21 ; a load unit  22  and a capacitor unit  23 .  
         [0033]     The current control unit  21  includes PMOS transistors P 14  to P 16  connected in parallel between a supply terminal of an external voltage VDD and an output terminal of an internal voltage Vint, wherein the driving signal DRV is inputted at each gate of the PMOS transistors P 14  to P 16 .  
         [0034]     The load unit  22  connected between the output terminal of the internal voltage Vint and a supply terminal of the ground voltage VSS includes PMOS transistors P 17  and P 18 , wherein each gate of PMOS transistors P 17  and P 189  is connected to each drain of the same for performing an operation as a diode.  
         [0035]     Also, the capacitor unit  23  connected between the output terminal of the internal voltage Vint and a supply terminal of the ground voltage VSS includes a first capacitor CP 2  made using a PMOS transistor and a second capacitor CN 2  made using an NMOS transistor for maintaining the voltage levels of the internal voltage and the internal reference voltage Vint_REF.  
         [0036]     The first biasing unit  30  connected between the comparison unit  10  and a ground voltage VSS includes an NMOS transistor N 6 , wherein the reference VREF is inputted at the gate of the NMOS transistor N 6 . The NMOS transistor N 6  is turned on while the reference VREF provides a stable reference voltage in order to control a bias state of the comparison unit  10 .  
         [0037]     The second biasing unit  40  connected in parallel with the first biasing unit  30  between the comparison unit  10  and a terminal of a ground voltage VSS includes NMOS transistors N 7  and an inverter IV 3 . The inverter IV 3  inverts a self refresh signal SREF and outputs into a gate of the NMOS transistor N 7 .  
         [0038]     The NMOS transistor N 7  is turned on when the self refresh signal SREF is inactivated, and provides a bias point to the comparison unit  10 . On the other hand, the NMOS transistor N 7  is turned off when the self refresh signal SREF is activated, and prevents unnecessary current from the comparison unit  10  to the supply terminal of the ground voltage VSS through the second biasing unit  40 .  
         [0039]     The NMOS transistors N 6  and N 7  of the present invention are each formed to be half the size of NMOS transistor N 3  of the conventional apparatus. During the self refresh mode, only one of the NMOS transistors N 6  and N 7  are turned on, resulting in reduced standby current consumption and a rapidly controllable response characteristic of the comparison unit  10 . Herein, a size of the NMOS transistors N 6  and N 7  is considered adequate for an operation environment of a memory device.  
         [0040]     An operation process of the specific embodiment of the present invention with the above configuration is described below.  
         [0041]     A test signal TEST is low and disabled during a normal operation mode. Accordingly, a current mirror operates normally during the normal operation mode, and generates an internal voltage double the amount of the reference voltage VREF to drive current. Herein, the reference voltage VREF for generating the internal voltage is generally required to be set up before reaching a power up level.  
         [0042]     On the other hand, if the test signal TEST is high and enabled, the PMOS transistors P 10  to P 13  are turned on, and a node (L) and a node (R) reach a supply voltage VDD level, and thus the current mirror operation is disabled.  
         [0043]     The operation process of the specific embodiment of the present invention is described below in more detail.  
         [0044]     When a power up signal which acknowledges circuit initialization is enabled and the supply voltage reaches a level capable of performing normal operations, a uniform current is supplied through the PMOS transistor P 10  and P 11 .  
         [0045]     Herein, when the reference voltage VREF is supplied into a gate terminal of the NMOS transistor N 5  and the transistor is enabled, then the comparison unit  10  operates.  
         [0046]     Afterwards, the comparison unit  10  compares the reference voltage VREF and the internal reference voltage Vint_REF. If the internal reference voltage Vint_REF is lower than the reference voltage VREF, current in the node (L) is decreased. Accordingly, an electric potential of the driving signal DRV is decreased, and thus the PMOS transistor P 14  to P 16  are turned on, resulting in a larger amount of current being supplied into the output node (B).  
         [0047]     Such operations continue until the reference voltage VREF and an electric potential of the internal reference voltage Vint_REF become identical by a sensing operation of the current mirror. Accordingly, the electric potential of the internal voltage Vint becomes two times higher than the internal reference voltage Vint REF due to a distribution effect of the PMOS transistors P 17  and P 18 . Also, because a small amount of current flows due to the PMOS transistors P 17  and P 18  operating as diodes, the internal voltage Vint is prevented from diffusion.  
         [0048]     At this time, when there is a periodic current consumption in the output node (B), the internal voltage Vint is generally required to recover back to the original level as fast as possible. Thus, in an active mode, the NMOS transistors N 6  and N 7  are all turned on and supply normal current to the comparison unit  10 .  
         [0049]     On the other hand, the self refresh signal SREF is activated during a self refresh operation mode when there is any current consumption in the output node (B). Accordingly, current supplied to the comparison unit  10  can be decreased by turning the NMOS transistor N 7  off.  
         [0050]     Although the specific embodiment of the present invention described utilizing one activated transistor N 7 , the specific embodiment of the present invention may be applied with two or more enable transistors. By turning on and off the transistors, the response characteristic and the amount of standby current can be controlled.  
         [0051]     In accordance with the specific embodiment of the present invention, an internal voltage driving circuit, which converts an external supply power into a low electric potential, capable of reducing the amount of standby current consumed in a current mirror during a self refresh mode is provided.  
         [0052]     The present application contains subject matter related to the Korean patent application No. KR 2005-0048378, filed in the Korean Patent Office on Jun. 7, 2005, the entire contents of which being incorporated herein by reference.  
         [0053]     While the present invention has been described with respect to certain specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.