Abstract:
A process for fabricating a combined micro electromechanical/gallium nitride structure. The micro electromechanical structure comprises a piezoelectric device, such as a piezoelectric switch or a bulk acoustic wave device. According to the process, high Q compact bulk acoustic wave resonators can be built. The process is applicable to technologies such as tunable planar filter technology, amplifier technology and high speed analog-to-digital converters.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
   This application claims the benefit of U.S. Provisional Application No. 60/563,598 for “Piezoelectric MEMS Integration with GaN Technology” by Sarabjit Mehta, David E. Grider and Wah S. Wong, filed on Apr. 19, 2004, which is incorporated herein by reference in its entirety. 

   BACKGROUND 
   1. Field 
   The present disclosure relates to micro-electromechanical systems (MEMS) and, in particular, to a method for integrating piezoelectric MEMS, such as PZT multimorph switches or bulk acoustic wave (BAW) resonators, with gallium nitride (GaN) technology and an apparatus integrating piezoelectric MEMS with GaN technology. 
   2. Related Art 
   The related art deals with the integration of PZT films with GaAs substrates, and the fabrication of PZT BAW devices on these substrates, as shown in “Lead Zirconate Titanate Thin Films for Microwave Device Applications”, S. Arscott, R. E. Miles, and S. J. Milne, Sol-Gel Materials for Device Applications, IEEE proc.-Circuits Devices Syst., Vol. 145, no. 5, October 1998. 
   A BAW device comprises a piezoelectric layer placed between two electrodes. When a radio frequency (RF) signal is applied across the device, a mechanical wave is produced in the piezoelectric layer. The thickness of the piezoelectric layer determines the resonant frequency, and the fundamental resonance occurs when the wavelength of the mechanical wave is about twice the thickness of the piezoelectric layer. As the thickness of the piezoelectric layer is reduced, the resonance frequency is increased. 
   The prior art does not explicitly address integration issues of PZT and GaAs MMIC technology. 
   The present disclosure presents a significant advantage over the related art because it considers PZT/GaN MMIC process integration, as GaN is the material of choice for high power applications. 
   SUMMARY 
   According to a first aspect, a process for fabricating a combined micro electromechanical/gallium nitride (GaN) structure is provided, the process comprising: providing a substrate; depositing a GaN layer on the substrate; obtaining a GaN transistor structure; depositing and patterning a first metal layer on the GaN layer; depositing a non-metal separation layer on the GaN layer in correspondence of the GaN transistor structure; patterning the non-metal separation layer to form a protective region to protect the GaN transistor structure; depositing a sacrificial layer on the protective region, the patterned first metal layer and at least a portion of the GaN layer so as to leave a further portion of the GaN layer between the protective region and the patterned first metal layer exposed; depositing and patterning a second metal layer on the sacrificial layer; depositing a support layer on the sacrificial layer, the second metal layer and the exposed GaN layer; providing a piezoelectric structure on the support layer; patterning the support layer in proximity of the GaN transistor structure to provide access holes; removing the non-metal separation layer and the sacrificial layer from the proximity of the GaN transistor structure through the access holes; providing a metal overlay above the GaN transistor structure, the metal overlay forming a gate of the GaN transistor structure; providing a gate passivation layer above the gate of the GaN transistor structure; providing a further metal layer above the gate passivation layer; and removing the sacrificial layer between the first patterned metal layer and the second patterned metal layer. 
   According to a second aspect, an integrated gallium nitride (GaN) field emitter transistor (FET)/micro electromechanical switch device is provided. 
   According to a third aspect, an integrated gallium nitride (GaN) field emitter transistor (FET)/bulk acoustic wave (BAW) device is provided. 
   According to a fourth aspect, a process for fabricating a combined micro electromechanical/gallium nitride (GaN) structure is provided, the process comprising: depositing a GaN layer; obtaining a GaN transistor structure on the GaN layer; forming a first metal contact pad on the GaN layer; forming a protective region around the GaN transistor structure; depositing a sacrificial layer on the protective region and the first metal contact pad; forming a second metal contact pad on the sacrificial layer; depositing a support layer on the sacrificial layer and the second metal contact pad; providing a piezoelectric structure on the support layer; removing the sacrificial layer from the proximity of the GaN transistor structure; patterning the piezoelectric structure in correspondence of the first metal contact pad and the second metal contact pad; forming a gate of the GaN transistor structure; providing a gate passivation layer above the gate of the GaN transistor structure; providing a further metal layer above the gate passivation layer; and removing the sacrificial layer between the first metal contact pad and the second metal contact pad. 
   According to a fifth aspect, a process for fabricating a combined gallium nitride (GaN)/piezoelectric structure is provided, comprising: obtaining a GaN structure on a GaN layer; forming a first contact pad on the GaN layer separated from the GaN structure; forming a protective region around the GaN structure; depositing a sacrificial layer on the protective region and the first metal contact pad; forming a second metal contact pad on the sacrificial layer; depositing a support layer on the sacrificial layer and the second metal contact pad; providing a piezoelectric switch structure on the support layer; removing the sacrificial layer from the proximity of the GaN structure; and patterning the piezoelectric switch structure in correspondence of the first metal contact pad and the second metal contact pad. 
   According to a sixth aspect, a process for fabricating a combined gallium nitride (GaN)/piezoelectric structure is provided, comprising: obtaining a GaN structure on a GaN layer; forming a first contact pad on the GaN layer separated from the GaN structure; forming a protective region around the GaN structure; depositing a sacrificial layer on the protective region and the first metal contact pad; forming a second metal contact pad on the sacrificial layer; depositing a support layer on the sacrificial layer and the second metal contact pad; providing a piezoelectric bulk acoustic wave resonator structure on the support layer; removing the sacrificial layer from the proximity of the GaN structure; and patterning the piezoelectric switch structure in correspondence of the first metal contact pad and the second metal contact pad. 
   According to a seventh aspect, a process for fabricating a combined gallium nitride (GaN)/piezoelectric structure is provided, the process comprising: providing a substrate; depositing a GaN layer on the substrate; obtaining a GaN transistor structure; depositing a non-metal separation layer on the GaN layer in correspondence of the GaN transistor structure; patterning the non-metal separation layer to form a protective region around the GaN transistor structure; depositing a sacrificial layer on at least a portion of the GaN layer and on the protective region; creating at least a cavity in the sacrificial layer; depositing a support layer on the sacrificial layer and the cavity; providing a piezoelectric structure on the support layer; patterning the support layer in proximity of the GaN transistor structure to provide access holes; removing the non-metal separation layer and the sacrificial layer from the proximity of the GaN transistor structure through the access holes; patterning the piezoelectric structure in correspondence of the patterned first metal layer and patterned second metal layer; providing a metal overlay above the GaN transistor structure, the metal overlay forming a gate of the GaN transistor structure; providing a gate passivation layer above the gate of the GaN transistor structure; providing a further metal layer above the gate passivation layer; and removing the sacrificial layer between the GaN layer and the support layer. 
   The combination between PZT devices and GaN devices offers enhanced functionality of RF components. For example, PZT MEMS switches can be incorporated into tunable matching networks surrounding active GaN HEMT processing or environmental conditions. According to the present disclosure, tunable matching networks are integrated directly onto the GaN monolithic microwave integrated circuit (MMIC), thus providing on-chip reconfigurability. The PZT devices such as PZT switches and BAW devices are extremely small (e.g. 50×100 μm) so that minimal MMIC space is required. 
   According to the present disclosure, high Q, compact BAW resonators can be built, that can be in on-chip filters or tuning networks. Integrated BAW resonators are not only useful in microwave circuits (e.g. amplifiers, active Q enhanced filters, oscillators) but also high speed A/D converter front ends. This latter application takes advantage of the high Q of the PZT resonator to produce high spur free dynamic range of Delta-Sigma A/D converters, while the high breakdown voltage characteristics of GaN HEMT technology greatly extends the bandwidth, dynamic range and power dissipation of the A/D converter. 
   Possible applications of present disclosure relate to technologies such as active tunable planar filter and amplifier technology, and high speed A/D converters. For example, the teachings of the present disclosure can be applied to X-band front and selectable filter banks, advanced multifunction RF systems, UHF communication, satellite communications terminals, and wireless base stations. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be understood and appreciated more fully from the following detailed description taken in conjunction with the drawings in which: 
       FIGS. 1-14  show steps of a process to fabricate a GaN-MEMS structure according to the present disclosure; 
       FIG. 15  shows a structure comprising a GaN FET and a BAW device, fabricated with the process in accordance with the present disclosure; 
       FIG. 16  shows a top view of a BAW portion of  FIG. 15 ; and 
       FIGS. 17-28  show steps of a process to fabricate a GaN-BAW structure according to the present disclosure. 
   

   DETAILED DESCRIPTION 
   The processing steps for both PZT MEMs structures and the GaN devices involve high temperature treatments at different steps. In order to successfully integrate the two technologies, the present disclosure will establish a proper combination of fabrication steps. Due to the nature of GaN materials, processing of a GaN high electron mobility transistor (HEMT) device is inherently not as trivial as for GaAs HEMT device, which makes process integration more complicated and difficult. 
     FIGS. 1-14  illustrate a preferred embodiment of the process according to the present disclosure. The process is performed using generally known microfabrication techniques, such as masking, etching, deposition and lift-off. While  FIGS. 1-14  depict multiple fabrication steps, alternative fabrication processes may allow separate steps to be combined into fewer steps. Additionally, alternative fabrication processes may use a different sequence of steps. 
     FIG. 1  shows a first step of the process, where a substrate  10  is provided and a GaN layer  20  is deposited on the substrate  10 . The substrate used in the preferred embodiment may be a sapphire substrate or a SiC substrate, although other materials may be used. The GaN layer  20  is usually deposited by means of epitaxial deposition. 
     FIG. 2  shows a second step of the process, where a CaN transistor structure  30  is obtained, for example a GaN field emission transistor (FET), comprising a buffer layer, an active layer, and source, drain, and gate contacts. The structure  30  is only schematically represented in  FIG. 2 , because it is well known to the person skilled in the art. The GaN FET processing also comprises ohmic contact and device isolation steps. The ohmic contact step comprises a rapid thermal annealing process (RTA) at about 900° C. for about 30 seconds. 
     FIG. 3  shows a third step of the process, where a metal layer is deposited on the GaN layer  20  and patterned to form a bottom contact pad  40 . The metal layer is, for example, a Ti/Pt layer about 0.1 μm thick. The metal layer is patterned using, for example, electron beam evaporation and liftoff. The FET structure  30  is protected during the metal layer deposition and patterning process. 
     FIG. 4  shows a fourth step of the process, where a non-metal separation layer is deposited above the GaN layer  20  and patterned to form a protective region  50  protecting the FET structure  30 . The non-metal separation layer is usually a 500 Å thick layer made of Si 3 N 4 , which is deposited using PECVD (Plasma Enhanced Chemical Vapor Deposition). 
     FIG. 5  shows a fifth step of the process, where a sacrificial layer  60  is deposited on the GaN layer  20 , the protective region  50 , and the contact pad  40 . A sacrificial layer is a layer which is first deposited in a step of a process and then removed in a further step of the process. The thickness of the layer  60  will determine a distance between the contacts pads of the switch, i.e. the air gap of the switch, as later explained. Additionally, the layer  60  will also serve as a lift off layer to eventually remove any processing residue from the FET structure. The sacrificial layer  60  is, for example, an about 1 μm thick layer made of silicon dioxide (SiO 2 ) which may be deposited using PECVD. 
     FIG. 6  shows a sixth and seventh step of the process. In the sixth step, a second metal layer is deposited on the sacrificial layer  60  and patterned to form a top contact pad  70  using, for example, electron beam evaporation and liftoff. The second metal layer is, for example, a 0.1 μm thick Ti/Pt layer. In the seventh step, the sacrificial layer  60  is etched (for example dry or wet etching). The etching step creates a hole or cavity  80  in the structure. 
     FIG. 7  shows an eighth step of the process, where a layer  90  is deposited above the sacrificial layer  60 , the top contact pad  70 , and the hole  80 . The layer  90  is, for example, an about 0.1 to about 0.5 μm thick layer made of Si 3 N 4 , which is deposited using PECVD. The use of the layer  90  is preferred, because it provides support and mechanical strength to the final released structure of the switch. The thickness of the layer  90  may be adjusted to compensate for any stress related bending. 
   The layer  90  can be patterned at the present stage or later, depending on the etch method used for the piezoelectric layer  140  in  FIG. 8  below. Should the piezoelectric layer  140  of  FIG. 8  be etched through a dry etch process, the layer  90  can be patterned at the present stage. Should the piezoelectric layer  140  of  FIG. 8  be etched through a wet etch process, the layer  90  is preferably patterned at a later stage, because it serves to protect the underlying sacrificial layer  60  from the etching chemicals, some of which may attack the sacrificial layer  60 . The layer  90  also serves to better protect the FET region while processing for the piezoelectric layer is carried out. 
     FIG. 8  shows further steps of the process, where deposition of metallic layers is alternated with deposition of piezoelectric layers. In particular, a first electrode  100 , a second electrode  110 , a third electrode  120 , and a fourth electrode  130  are alternated with piezoelectric layers  140  and  150 . The electrodes are patterned from metal layers. The metal layers are, for example, 0.1 μm thick Ti/Pt layers deposited using a liftoff technique. The piezoelectric layers are, for example, 0.5 μm thick lead zirconate titanate (PZT) or lead lanthanum zirconate titanate (PLZT) layers deposited using, for example, a sol-gel deposition technique. The process of depositing the layers  140 ,  150  preferably involves an annealing step at about 500-700° C. The annealing can either be a 1-15 seconds RTA or a 15 minutes furnace process. The layers  140 ,  150  can be patterned using a variety of dry or wet etch techniques. 
     FIG. 9  shows a further step of the process, where the layer  90  is patterned to provide access holes  160 ,  170 ,  180  for the SiO 2  removal in the FET region only. 
     FIG. 10  shows a further step of the process, where the protective region  50  and the sacrificial layer  60  are removed from the FET region, for example by successive immersions in buffered oxide etchant (BOE) solution and/or by dry etching. The PZT regions  140 ,  150  are protected during this step. 
     FIG. 11  shows a further step of the process, where the sacrificial layer  60  and layer  90  are patterned in correspondence of the bottom and top contact pads  40 ,  70 . In particular, the layers  60 ,  90  are dry etched to define the switch outline and also to expose the outer parts of the contact pads. The FET region is protected during this step. 
     FIG. 12  shows a further step of the process, where the GaN FET process is started by defining the FET gate region, i.e. by providing a metal overlay  190  for the FET. The switch region is protected during this step. The metal overlay  190  can also be used to complete part or all of the switch circuitry, for example to form the electrode  130 . The metal overlay step is followed by a gate passivation step by means, for example, of a Si 3 N 4  layer  200 . The PZT region is protected during this step. 
     FIG. 13  shows a further step of the process, where a further metal layer  210  for the FET to build up gold thickness on the source, drain and gate pads for heat dissipation. 
     FIG. 14  shows a final step of the process, where the sacrificial layer  60  is removed, for example by means of a BOE process. This process is followed by a liquid CO 2  cleaning process to release the switch. This prevents any damage to the structure due to the trapped liquid. The FET region is protected during this step. 
   In a similar way, a GaN FET can be obtained together with a BAW device, as shown in the following  FIGS. 15 and 16 . 
     FIG. 15  shows a combined GaN FET/BAW structure. The BAW structure comprises a top electrode  1100 , a bottom electrode  1000 , a piezoelectric active layer  1400 , and a Si 3 N 4  substrate  900 , together with a GaN FET structure  255 . The BAW resonator shown in  FIG. 15  is released from the substrate to increase the Q-factor. 
     FIG. 16  shows a top view taken along section  16 - 16  of  FIG. 15  where also the supported areas  260 ,  270  of the BAW device are shown. 
     FIGS. 17-28  illustrate a further embodiment of the process according to the present disclosure for obtaining the device of  FIGS. 15 and 16 . The process is performed using generally known microfabrication techniques, such as masking, etching, deposition and lift-off. While  FIGS. 17-28  depict multiple fabrication steps, alternative fabrication processes may allow separate steps to be combined into fewer steps. Additionally, alternative fabrication processes may use a different sequence of steps. 
     FIG. 17  shows a first step of the exemplary process, where a substrate  11  is provided and a GaN layer  200  is deposited on the substrate  11 . The substrate used in the exemplary embodiment may be a sapphire substrate or a SiC substrate, although other materials may be used. The GaN layer  200  is usually deposited by means of epitaxial deposition. 
     FIG. 18  shows a second step of the process, where a GaN transistor structure  300  is obtained, for example a GaN field emission transistor (FET), comprising a buffer layer, an active layer, and source, drain, and gate contacts. The structure  300  is only schematically represented in  FIG. 18 , because well known to the person skilled in the art. The GaN FET processing also comprises ohmic contact and device isolation steps. The ohmic contact step comprises a rapid thermal annealing process (RTA) at about 900° C. for about 30 seconds. 
     FIG. 19  shows a third step of the process, where a non-metal separation layer is deposited above the GaN layer  200  and patterned to form a protective region  500  protecting the FET structure  300 . The non-metal separation layer is usually a 500 Å thick layer made of Si 3 N 4 , which is deposited using PECVD (Plasma Enhanced Chemical Vapor Deposition). 
     FIG. 20  shows a fourth step of the process, where a sacrificial layer  600  is deposited on the GaN layer  200  and the protective region  500 . A sacrificial layer is a layer which is first deposited in a step of a process and then removed in a further step of the process. The thickness of the layer  600  will determine a distance between the contacts pads of the switch, i.e. the air gap of the switch, as later explained. Additionally, the layer  600  will also serve as a lift off layer to eventually remove any processing residue from the FET structure. The sacrificial layer  600  is, for example, an about 1 μm thick layer made of silicon dioxide (SiO 2 ) which may be deposited using PECVD. 
     FIG. 21  shows a fifth of the process, where the sacrificial layer  600  is etched (for example dry or wet etching). The etching step creates holes or cavities  800  in the structure. 
     FIG. 22  shows a sixth step of the process, where a layer  900  is deposited above the sacrificial layer  600  and the holes  800 . The layer  900  is, for example, an about 0.1 to about 0.5 μm thick layer made of Si 3 N 4 , which is deposited using PECVD. 
   The layer  900  can be patterned at the present stage or later, depending on the etch method used for the piezoelectric layer  1400  in  FIG. 23  below. Should the piezoelectric layer  1400  of  FIG. 23  be etched through a dry etch process, the layer  900  can be patterned at the present stage. Should the piezoelectric layer  1400  of  FIG. 23  be etched through a wet etch process, the layer  900  is preferably patterned at a later stage, because it serves to protect the underlying sacrificial layer  600  from the etching chemicals, some of which may attack the sacrificial layer  600 . The layer  900  also serves to better protect the FET region while processing for the piezoelectric layer is carried out. 
     FIG. 23  shows further steps of the process, where deposition of metallic layers is alternated with deposition of piezoelectric layer. In particular, a first electrode  1000  and a second electrode  1100  are alternated with piezoelectric layer  1400 . The electrodes  1000 ,  1100  are patterned from metal layers. The metal layers are, for example, 0.1 μm thick Ti/Pt layers deposited using a liftoff technique. The piezoelectric layer  1400  is, for example, 0.5 μm thick lead zirconate titanate (PZT) or lead lanthanum zirconate titanate (PLZT) layers deposited using, for example, a sol-gel deposition technique. The process of depositing the layer  1400  preferably involves an annealing step at about 500-700° C. The annealing can either be a 1-15 seconds RTA or a 15 minutes furnace process. The layer  1400  can be patterned using a variety of dry or wet etch techniques. 
     FIG. 24  shows a further step of the process, where the layer  900  is patterned to provide access holes  1600 ,  1700 ,  1800  for the SiO 2  removal in the FET region only. 
     FIG. 25  shows a further step of the process, where the protective region  500  and the sacrificial layer  600  are removed from the FET region, for example by successive immersions in buffered oxide etchant (BOE) solution and/or by dry etching. The PZT region  1400  are protected during this step. 
     FIG. 26  shows a further step of the process, where the GaN FET process is started by defining the FET gate region, i.e. by providing a metal overlay  1900  for the FET. The BAW region is protected during this step. The metal overlay step is followed by a gate passivation step by means, for example, of a Si 3 N 4  layer  2000 . The PZT region is protected during this step. 
     FIG. 27  shows a further step of the process, where a further metal layer  2100  may be deposited for the FET to build up gold thickness on the source, drain and gate pads for heat dissipation. 
     FIG. 28  shows a final step of the process for obtaining the device of  FIGS. 15 and 16 , where the sacrificial layer  600  is removed, for example by means of a BOE process. The FET region is protected during this step. 
   While several illustrative embodiments of the invention have been shown and described, numerous variations and alternative embodiments will occur to those skilled in the art. Such variations and alternative embodiments are contemplated, and can be made without departing from the scope of the invention as defined in the appended claims. 
   The foregoing detailed description of exemplary and preferred embodiments is presented for purposes of illustration and disclosure in accordance with the requirements of the law. It is not intended to be exhaustive nor to limit the invention to the precise form(s) described, but only to enable others skilled in the art to understand how the invention may be suited for a particular use or implementation. The possibility of modifications and variations will be apparent to practitioners skilled in the art. No limitation is intended by the description of exemplary embodiments which may have included tolerances, feature dimensions, specific operating conditions, engineering specifications, or the like, and which may vary between implementations or with changes to the state of the art, and no limitation should be implied therefrom. Applicant has made this disclosure with respect to the current state of the art, but also contemplates advancements and that adaptations in the future may take into consideration of those advancements, namely in accordance with the then current state of the art. It is intended that the scope of the invention be defined by the Claims as written and equivalents as applicable. Reference to a claim element in the singular is not intended to mean “one and only one” unless explicitly so stated. Moreover, no element, component, nor method or process step in this disclosure is intended to be dedicated to the public regardless of whether the element, component, or step is explicitly recited in the claims. No claim element herein is to be construed under the provisions of 35 U.S.C. Sec. 112, sixth paragraph, unless the element is expressly recited using the phrase “means for . . . ” and no method or process step herein is to be construed under those provisions unless the step, or steps, are expressly recited using the phrase “step(s) for . . . .”