Abstract:
A method and system is disclosed for controlling power supply to a memory device. After determining at least one word line being selected, supply voltage lines are controlled so that a predetermined active mode voltage is provided to one or more predetermined memory cells associated with the selected word line, and a standby voltage lower than the active mode voltage is provided to all other unselected portions of the memory device.

Description:
BACKGROUND  
       [0001]     The present disclosure relates generally to electronic memory circuits, and more particularly to complementary metal oxide semiconductor (CMOS) static random access memories (SRAM). Still more particularly, the present disclosure relates to methods of placing these memories in, and of recovering these circuits from, a standby mode.  
         [0002]     Electronic memory circuits have been known for many years. Such memory circuits have employed a wide variety of types of circuits and circuit elements in order to store information in some way, such as by storage of charge in a capacitive element or the use of a bistable circuit or element. Such a bistable element can take the form, for example, of the well-known flip-flop circuit, where a pair of transistors are cross-coupled in such a way that when one transistor is turned on, the other will be forced off, or a magnetizable core or other element or domain which can be selectively magnetized into one of at least two distinct states.  
         [0003]     Each of these memory types, categorized by the type of memory cell employed, has distinct advantages and disadvantages with respect to the other types of memory and each type will typically be applied where the advantages can be best utilized.  
         [0004]     With widespread use of electronic devices for operating portable appliances such as portable telephones, personal digital assistants (PDA), portable information terminals, AV devices and others on batteries, it is becoming more important to decrease both power consumption during operation and power consumption during device standby mode.  
         [0005]     In recent years, there has been an interest in increasing the memory capacity of all types of memory devices, including static memory devices. Some particular problems are encountered in doing so in SRAMs because the size of each memory cell on the chip is much larger than in dynamic RAMs due to the use of a greater number of circuit elements in each memory cell. SRAMs have the advantage over dynamic RAMs by demonstrating significantly higher switching speeds and have the ability to be put in a standby mode, which significantly reduces total memory current.  
         [0006]     SRAMs are comprised of gate-insulated field-effect transistors, or MOS transistors. These transistors require an operating voltage that decreases as the transistor size decreases, because the breakdown voltage of the transistor decreases with the smaller size. As well, the threshold voltage (VT) of the MOS transistor must be lowered in accordance with the drop of operating voltage so as to retain high-speed operation, because the operating speed is dominated by the effective gate voltage of the MOS transistor (i.e., the operating voltage minus VT), and increases as the difference increases.  
         [0007]     Generally speaking, however, if the VT is lower than about 0.4 V, a direct sub-threshold current, which exponentially increases with the drop in VT, will flow through the MOS transistor, which should intrinsically be cut off. As a result, the direct current greatly increases in a semiconductor integrated circuit composed of a number of MOS transistors, even if the circuit is a CMOS circuit. This sub-threshold current is significant when multiplied by the large number of memory cells in current memory arrays and produces undesirable standby power consumption during standby.  
         [0008]     The most popular and simplest method of reducing power involves reducing the applied operating voltage to the entire memory during the standby mode. This approach requires a longer charge time to retrieve the first information from the memory upon recovery from the standby mode. It also requires a high current charging current during the switching from the standby to operating condition. For large bit density SRAMs, lower power consumption is important for device thermal stability, power bus design and product specification. Thus a standby circuit model is widely used in SRAM circuit design.  
         [0009]     Desirable in the art of semiconductor memory design are method and circuit designs for operating devices under their standby mode.  
       SUMMARY  
       [0010]     In view of the foregoing, this disclosure provides a system and method for reducing power for static random access memories.  
         [0011]     A method and system are disclosed for controlling power supply to a memory device. After determining at least one word line being selected, supply voltage lines are controlled so that a predetermined active mode voltage is provided to one or more predetermined memory cells associated with the selected word line, and a standby voltage lower than the active mode voltage is provided to all other unselected portions of the memory device.  
         [0012]     Various aspects and advantages will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating the principles of the disclosure by way of examples.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]      FIG. 1  illustrates a first embodiment of a control circuit in accordance with the first example of the present disclosure.  
         [0014]      FIG. 2  illustrates a second embodiment of a control circuit in accordance with the first example of the present disclosure.  
         [0015]      FIG. 3  illustrates a third embodiment of a control circuit in accordance with the first example of the present disclosure.  
         [0016]      FIG. 4  illustrates a typical memory cell.  
         [0017]      FIG. 5  illustrates a memory design in accordance with the first example of the present disclosure. 
     
    
     DESCRIPTION  
       [0018]     The present disclosure provides an improved system and method for reducing power for static random access memories. A new standby mode operation is proposed in order to eliminate the first bit read or write delay time issue, to minimize the charge current, and to reduce the standby power consumption. For illustration purposes, SRAM is used as an example, although it is understood that similar memory devices can also be used.  
         [0019]     The present disclosure provides control circuits to manage memory power supply (or Vcc) lines. Only selected word lines of an SRAM is powered up to a full operating voltage level (e.g., Vdd), which may be referred to as an active mode voltage, while other unselected word lines are supplied with a lower voltage level, which may be referred to as a standby voltage. Unlike the conventional designs, only a small portion of the SRAM suffers from higher standby leakage problem due to the fact that not all memory cells are supplied with the active mode voltage.  
         [0020]      FIG. 1  illustrates a control circuit  100 , which includes a first control module  102  and a second control module  104 . The first control module  102  includes an NMOS transistor NM 1 , whose gate is connected to its drain and whose source is connected to an output node  106 . The second control module  104  includes a PMOS transistor PM 1  and inverters  108  and  110 . Inverter  108  includes a PMOS transistor PM 2  and an NMOS transistor NM 2 , while inverter  110  includes a PMOS transistor PM 3  and an NMOS transistor NM 3 . The output of the inverter  110  is connected, via a node  112 , to the input of the inverter  108 . Node  112  also connects to the gate of transistor PM 1 . The input of the inverter  110  is driven, via a node  114 , by a word line select signal. The output of inverter  108  connects to a node  116 , which also connects to the source of PM 1 , whose drain connects to the output node  106 . The output node  106  is then connected to a power supply line or a Vcc line for a word line of the SRAM array to supply power thereto.  
         [0021]     If the word line is supposed to be in an active mode, it is assumed that the word line select signal switches to high (logic  1 ), node  114  is high and node  112  is low (logic  0 ). Since node  112  is connected to the gate of PM 2 , PM 2  is turned on, thereby passing a full operating voltage Vdd (or the active mode voltage) to node  116 . Also, since node  112  is connected to the gate of PM 1 , PM 1  is turned on, thereby allowing Vdd at node  116  to pass to node  106 . As such, the control circuit  100  acts as a switched power supply to the connected individual word line. That is, when an individual word line is selected, node  114  is high and Vdd is eventually passed to the output node  106  for supplying the selected word line with a predetermined high voltage.  
         [0022]     If the word line is supposed to be in a standby mode, in this example, the word line select signal switches to low, node  114  is low and Vdd is not passed to node  106 . Instead, a regulated voltage or the standby voltage, which is lower than Vdd, is generated by the first control module  102  and passed to the output node  106 . This regulated voltage is calculated as the difference between Vdd and the threshold voltage of NM 1 , or VT NM1 . When word line select signal switches to high, the regulated voltage is supplanted by the full operating voltage that is supplied by the second control module  104 . As such, for each word line of the SRAM array, it is only supplied by the full operating voltage Vdd when the word line is specifically selected. Otherwise, a voltage at a lower level is supplied. This reduces the current leakage problem during the standby mode since only a relatively small localized area of the SRAM array is powered up to the full operating voltage.  
         [0023]      FIG. 2  illustrates a control circuit  200 , which includes the first control module  102  and a second control module  202 . The second control module  202  is similar to the control module  104  of  FIG. 1  except that the inverter  108  is eliminated. In other words, the second control module  202  includes the transistor PM 1  and the inverter  110 . The node  116 , instead of connecting to the output of the inverter  110 , it is now connected to Vdd. Like the control circuit  100 , the drain of the transistor PM 1  is connected to the output node  106 . Similarly, node  112  is connected to the gate of transistor PM 1 . In other words, the output of the inverter  110  is applied directly to the gate of PM 1 .  
         [0024]     As in  FIG. 1 , when an individual word line is selected, node  114  is high and node  112  is low. Since node  112  is connected to the gate of PM 1 , PM 1  is turned on, thereby passing Vdd to node  106 . In this embodiment, control circuit  200  functions in the same manner as the control circuit  100 , except that control circuit  200  passes current through only one PMOS transistor, and as a result exhibits turn-on timing difference. Also circuit layout area is reduced due to the absence of the inverter  108 .  
         [0025]      FIG. 3  illustrates a control circuit  300 , which includes a first control module  302  and a second control module  304 . In this example, the first control module  302  includes only a PMOS transistor PM 4 , whose source is connected to Vdd and whose gate is connected to its drain. The drain of PM 4  is also connected to the output node  106 . During the standby mode with the word line deselected, node  114  is low and the node  112  is high, thereby turning off PM 1 . A regulated voltage, which is the difference between Vdd and the threshold voltage of PM 4 , or V PM4 , is supplied to the output node  106 . As such, the deselected word lines are supplied with a reduced voltage supply in the standby mode to reduce standby power and leakage current. When the word line is selected, node  114  is high and node  112  is low, thereby turning on PM 1 . Vdd is then passed to the output node  106 , which supplants the regulated voltage generated by the first control module  302 .  
         [0026]     As illustrated above in various examples, the designs for the first control module and the second control module are relatively independent. For example, the first control module can use the NMOS design as well as the PMOS design, and the second control module can use any appropriate one to operate with the first control module. Further, the separation of the first and second control modules are artificial for illustration purposes as they are all parts of an integrated control circuit.  
         [0027]      FIG. 4  shows a typical CMOS single memory cell  400 , which includes PMOS transistors  402  and  404 , and NMOS transistors  406 ,  408 ,  410  and  412 . The operating power of this cell is supplied via node  106 , which is the output node from the control circuit as described above. When a word line WL is selected, the logic states stored in nodes  414  and  416  will be passed, respectively, to bitlines BLb and BL. As explained above, when the operating power of this cell is reduced during the standby mode, current leakage problem is minimized. It is understood that any memory cell design can work with the above described control circuit as long as it receives a controlled supply voltage that is lowered during the standby mode. For example, in another typical memory cell design, PMOS transistors  402  and  404  are each replaced with a high valued poly silicon resistor. Because the resistor may be constructed on top of the rest of the transistors, significant space may be saved.  
         [0028]      FIG. 5  shows a memory  500  in accordance with one example of the present disclosure. A memory array  502  includes an array of memory cells  400  with n rows and m columns, interconnecting with each other through word lines WL 0  to WLn and bitlines BLb 0 /BL 0  to BLbm/BLm. A plurality of power supply circuits  504  is used to provide power to the memory array  502 . Any one of the control circuits  100 ,  200  or  300  may be implemented as the power supply circuit  504  to achieve the same function. The control circuits  100 ,  200  and  300  provide the same effective result with slight differences in timing. Each power supply circuit is connected, via its output node, to the memory array  502 .  
         [0029]     One of the word lines WL 0  to WLn is first selected by a word line multiplex circuit  506 , after which voltage is generated by the corresponding power supply circuit  504  and passed, via the output node, to the memory array  502 . The bitlines are further selected by a bitline multiplex circuit  508 . Therefore, the word line by the word line multiplex circuit  506  is supplied with a full operating voltage, or Vdd. Other word lines in standby mode receive a regulated voltage, which is smaller than Vdd, from the power supply circuit  504 .  
         [0030]     The above disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components, and processes are described to help clarify the disclosure. These are, of course, merely examples and are not intended to limit the disclosure from that described in the claims.  
         [0031]     Although illustrative embodiments of the disclosure have been shown and described, other modifications, changes, and substitutions are intended in the foregoing disclosure. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the disclosure, as set forth in the following claims.