Abstract:
The present invention discloses an improved inductance-voltage clamping full-bridge soft-switch circuit, comprising a full-bridge converter, a transformer, an output rectifying unit, an inductor, a clamping resistor, a capacitor, a first clamping diode and a second clamping diode. The inductor includes a first winding used as an auxiliary inductor and a second winding used for clamping. The present invention greatly reduces the transient current stress on the clamping resistor by connecting a capacitor in parallel with the clamping resistor connected in series, thereby effectively enhancing the reliability of the clamping resistor and improving the reliability of the overall circuit.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to a full-bridge soft-switch circuit, and in particular, to a full-bridge soft-switch circuit having inductance-voltage clamp. 
       BACKGROUND OF ART 
       [0002]    In the conventional full-bridge soft-switch circuit, because of the advantages of simple circuit and control, soft switch being achieved easily by switch tube, high circuit efficiency, low EMI, etc., it was widely used in the area of converters. However, because of adding an auxiliary inductor therein, a diode may bring relatively large voltage spike and oscillation during the reverse recovery of a diode at secondary side, thereby increasing the loss of a diode switch tube such that EMI of circuit becomes worse. If boosting the withstand voltage of diode, the reverse recovery time of diode will be longer which makes circuit performances even worse. 
         [0003]    In order to eliminate the influence caused in the recovery of a backward diode so as to enhance the circuit reliability, Patent Application No 03114296.6, titled “Soft Switch Full-bridge Phase-shift Circuit with Resonant Inductance Voltage Clamp”, (inventors: Zhang Huajian, Lv Minghai, Wang Guoyong, Huang Boning, Publication Date: Nov. 12, 2003) discloses a novel resonant inductance voltage clamping soft switch full-bridge phase-shift circuit. It uses the champing winding of a resonant inductor to resolve the problems caused during the reverse recovery of an output diode such that the circuit, at the same time of maintaining the inherent soft switch characteristics of full bridge circuit, greatly reduces oscillations caused by the reverse recovery of the output diode. In one of typical embodiments of the patent application, as shown in  FIG. 1 , a resonant inductance branch connects a resistor Rc in series. The purpose thereof is to ensure that the circuit, during each switch cycle, consumes extra energy of the resonant inductor and eliminates the influence caused by the recovery of a backward diode, and ensure that the clamping diodes D 5  and D 6  are zero current switches. In this way, it can enhance the reliability of the clamping circuit considerably. However, the current stress di/dt or voltage stress dv/dt on the added resistor Rc is relatively large, and peak is relatively high, such that there are certain effects against the reliability of resistor Rc. For the clamping resistor, the average energy needed to be consumed in whole procedure is substantially definite, and is determined by the characteristics of the entire circuit. The average loss of the resistor can meet requirements under general choices, but instantaneous power is different. In particular, in the instant of current occurring barely, the instantaneous power is very large, while when the current is zero, the resistor has no loss. Resistor instantaneous stress is an important factor for both of choice and lifetime of resistors. If the instantaneous power of resistors is excessively large it will reduce the lifetime of resistors, even damage resistors. Therefore, in the situation of maintaining total loss unchanged, it is desired that the instantaneous power is as lower as possible. 
       SUMMARY OF THE INVENTION 
       [0004]    A major object of the present invention is to provide an improved inductance-voltage clamping full-bridge soft-switch circuit to resolve the technical problems in the prior art, and to reduce the instantaneous current or instantaneous power of the clamping resistor and enhance the reliability of the resistor. 
         [0005]    The present inventor provides an improved inductance-voltage clamping full-bridge soft-switch circuit, comprising a full-bridge converter, a transformer, an output rectifying unit, an inductor, a resistor, a first clamping diode and a second clamping diode. Leading bridge arms and lagging bridge arms of the full-bridge converter are connected to positive and negative input buses respectively. The inductor includes a first winding used as an auxiliary inductor and a second winding used for clamping. The primary side of the transformer is connected to the first winding in series and then to the middle point of the leading bridge arms and lagging bridge arms of the full-bridge converter. The two ends of the secondary side of the transformer are connected to the output rectifying units respectively. The first end of the second winding connects the first winding at one side close to the middle point of the leading bridge arms of the full-bridge converter, and the second end of the second winding connects the resistor in series, and then clamps on the positive and negative input buses via the first clamping diode and the second clamping diode respectively. The circuit further comprises a capacitor connected to the two ends of the resistor in parallel. 
         [0006]    The present invention has the further improvement of limiting the capacitor and the resistor connected thereto in parallel to meet the following formula: Rc×Cs&lt;T/6, wherein T is the switch cycle of the circuit. 
         [0007]    The represent invention has the advantage of improving the current stress di/dt or voltage stress dv/dt on the clamping resistor because of having a capacitor. Depending on shunt of a capacitor, the embodiment of the present invention makes the pulse current of the clamping resistor greatly smooth and instantaneous strike power greatly reduced without adversely affecting the other performances of the circuit so as to enhance the reliability of the resistor, and thereby increasing the reliability of the entire circuit. 
         [0008]    The characteristics and advantages of the present invention are more appreciated in connection with the following detailed description taken in conjunction with the accompanying drawings. 
     
    
     
       DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  is a inductance-voltage clamping full-bridge phase-shift soft-switch circuit of the prior art; 
           [0010]      FIG. 2  is a circuit diagram of the inductance-voltage clamping full-bridge phase-shift soft-switch circuit according to an embodiment of the present invention; 
           [0011]      FIG. 3  is waveforms of diode D 5 , output diode DR 2  and resonant inductor Lr during the reverse recovery of the output diode in the inductance-voltage clamping full-bridge phase-shift soft-switch circuit; 
           [0012]      FIG. 4  is a reverse recovery characteristic diagram of a diode; 
           [0013]      FIG. 5  is a waveform of the voltage on the clamping resistor before and after adding a capacitor; 
           [0014]      FIG. 6  is an expanded waveform of the voltage on the clamping resistor before and after adding the capacitor; 
           [0015]      FIG. 7  is a circuit diagram of the inductance-voltage clamping full-bridge soft-switch circuit according to another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0016]      FIG. 2  shows a phase-shift full-bridge clamping soft-switch circuit having inductance-voltage clamp added on a conventional phase-shift full-bridge soft-switch circuit. Leading bridge arms Q 1 , Q 2  and lagging bridge arms Q 3 , Q 4  of full-bridge converter are connected to positive and negative input buses respectively. Inductor Lr comprises a first winding used as an auxiliary inductor and a second winding used for clamping. The primary side of a transformer T 1  is connected to the first winding in series, and then to the middle point of the leading bridge arms Q 1 , Q 2  and lagging bridge arms Q 3 , Q 4  of the full-bridge converter. Two ends of the secondary side of the transformer T 1  are straightly connected to an output rectifying unit respectively. The output rectifying unite generally is a diode rectifying circuit, and in the present embodiment, the output rectifying unit is output diodes DR 1 , DR 2 . The anodes of the output diodes DR 1 , DR 2  are connected to the two ends of the secondary side of the transformer T 1  respectively, and the cathodes and the middle tap of the secondary side of the transformer T 1  are connected to a filter unit and then to a load. One end of the second winding connects the first winding at one side close to the middle point of the leading bridge arms Q 1 , Q 2  of the full-bridge converter, and another end of the second winding connects the resistor Rc in series, and then straightly connects the first clamping diode D 5  and reversely connects the second clamping diode D 6  respectively, and then clamps on the positive and negative input buses. A capacitor Cs is connected to the two ends of the resistor Rc in parallel. The resistor Rc is called as a clamping resistor Rc because it clamps. 
         [0017]    The following is the further analysis regarding the capacitor Cs improving the reliability of the resistor Rc by reference to  FIGS. 3-5 . 
         [0018]      FIG. 3  shows main voltage current waveforms of the clamping circuit thereof. When the current Ilr on the first winding reaches a peak, the output voltage VDR 2  of the output diode DR 2  also has a peak. Accordingly, on the first clamping diode D 5 , the current ID 5  thereof has a pulse at first and then decays to zero gradually. This current inevitably flows through the clamping resistor Rc such that the clamping resistor Rc also has a pulse current thereon. The peak of the pulse current is: 
         [0000]    
       
         
           
             
               I 
               
                 d 
                  
                 
                     
                 
                  
                 5. 
                  
                 p 
                  
                 
                     
                 
                  
                 k 
               
             
             = 
             
               
                 
                   I 
                   rp 
                   2 
                 
                 + 
                 
                   
                     ( 
                     
                       
                         V 
                         
                           i 
                            
                           
                               
                           
                            
                           n 
                         
                       
                       
                         Z 
                         rr 
                       
                     
                     ) 
                   
                   2 
                 
               
             
           
         
       
     
         [0019]    Wherein: 
         [0000]    
       
         
           
             
               
                 I 
                 rp 
               
               = 
               
                 
                   
                     I 
                     0 
                   
                   n 
                 
                 + 
                 
                   
                     
                       V 
                       
                         i 
                          
                         
                             
                         
                          
                         n 
                       
                     
                     * 
                     
                       t 
                       rr 
                     
                   
                   
                     Lr 
                     ′ 
                   
                 
               
             
             ; 
           
         
       
     
         [0000]    Io is a load current, n is transformation ratio of the primary and secondary sides, Lr′ is the resonant inductance quantity of the first winding, trr is the reverse recovery time of the output diodes DR 1 , DR 2 , Vin is the input voltage of the bus. 
         [0000]    
       
         
           
             
               
                 Z 
                 rr 
               
               = 
               
                 
                   
                     Lr 
                     ′ 
                   
                   
                     Cs 
                     ′ 
                   
                 
               
             
             ; 
           
         
       
     
         [0000]    Cs′ is circuit equivalent parasitic capacitance and absorbing capacitance converted for the primary side of the transformer T 1 . 
         [0020]    When the reverse recovery of the output diodes DR 1 , DR 2  ends, this current transfers to the clamping circuit quickly. The current rising of the clamping circuit depends on the reverse recovery characteristics of the output diodes DR 1 , DR 2 . The extra current of the output diodes DR 1 , DR 2  starts to transfer to the clamping circuit during the reduction of the reverse recovery current. A normal diode has a relatively precipitous curve in the period of current reduction during the reverse recovery. As shown in  FIG. 4 , the reverse current in the reverse recovery characteristics of the normal diode drops quickly, such as, trr 2  less 0.4 trr generally. For the quick recovery diode, the reverse current of the diode drops even quickly, such as the quick recovery diode (FRED) in  FIG. 4  which has a smaller trr 1  time. Thus, the current is transferred to the clamping circuit more quickly, and the initial current pulse on the clamping resistor Rc will be more precipitous and higher. After the current on the resistor Rc reaches the largest value, the clamping current decays to zero gradually as the resistor energy losses. 
         [0021]    Since there is a capacitor Cs connecting to the two ends of the resistor Rc in parallel, the most of the pulse current is shunted from the capacitor Cs at the time of beginning because of having a high frequency capacitor such that the current on the resistor Rc is reduced greatly at the time of turning on. Because of the voltage is boosted after the capacitor Cs is charged, the current is transferred to the resistor Rc gradually. Thus, the instantaneous current on the resistor Rc will be greatly smoothed, and instantaneous inrushing power is reduced greatly. 
         [0022]      FIG. 5  shows the voltage waveform on the resistor Rc before and after adding a capacitor in real applications. Curve 1  is the voltage waveform of the resistor Rc without adding the capacitor Cs; Curve 2  is the voltage waveform of the resistor Rc after the capacitor Cs is added. It can be seen from the figure, the peak voltage has dropped from 95.5V to 53.5V; and in this way, the instantaneous maximum power is reduced to around 30%. The expanded voltage waveform of the clamping resistor of  FIG. 6  can be obtained by expanding the waveforms of  FIG. 5 . It can be seen that, after the capacitor is added, the voltage of the clamping resistor becomes smoother, and the current peak is reduced greatly. This indicates fully that it is able to greatly reduce voltage current stress of the clamping resistor after adding the capacitor. Thus, it verifies the availability and feasibility of adding the absorbing capacitor Cs in both theory and practice. 
         [0023]    However, not any capacitor can achieve the purpose of the present invention. After the capacitor Cs is connected to the two ends of the resistor Rc in parallel, if the capacitance value is excessively large, the first clamping diode D 5  and the second clamping diode D 6  will come into continuous status, that is, diodes will not turn off within the ½ switch period, resulting in that dc/dc straight-through phenomenon occurs. For example, for the first clamping diode D 5 , if the switch tube Q 2  of the Leading bridge arm already turns on when the first clamping diode D 5  has not turned off yet, the first clamping diode D 5  and the switch tube Q 2  form straight-through phenomenon, resulting in the damage of the first clamping diode D 5  and the switch tube Q 2 . Thus, the capacitance cannot be too large. Also, the resistance value of the resistor Rc cannot be too small. If the resistor Rc has a too small resistance value, it will cause the first clamping diode D 5  and the second clamping diode D 6  to come into the continuous status. Thus, it is necessary for the capacitor Cs and the resistor Rc to meet RcCs&lt;T/6, wherein T is the switch period of the circuit, that is, the product of the capacitance value of the capacitor Cs and the resistance value of the resistor Rc is less than ⅙ switch period. 
         [0024]      FIG. 7  shows is an implementation of the inductance-voltage clamping full-bridge phase-shift soft-switch circuit of the present invention used in a three-level circuit. Lagging bridge arms V 32 , V 33 , V 34 , V 35  and leading bridge arms V 30 , V 31 , V 36 , V 37  of a full-bridge converter are connected to positive and negative input buses H 1 , H 3 , respectively. An inductor Lr comprises a first winding used as an auxiliary inductor and a second winding used for clamping. The primary side of a transformer T 1  is connected to the first winding in series, and then to the middle point of the lagging bridge arms V 32 , V 33 , V 34 , V 35  and the leading bridge arms V 30 , V 31 , V 36 , V 37  of the full-bridge converter. Two ends of the secondary side of the transformer T 1  are straightly connected to output rectifying units D 316 , D 317  respectively. The anodes of the output rectifying unites D 316 , D 317  are connected to the two ends of the secondary side of the transformer T 1  respectively, and the cathodes and the middle tap of the secondary side of the transformer T 1  are connected to a filter unit and then to a load. The first end of the second winding is connected to a end of the first winding connected on the middle point of the lagging bridge arms V 32 , V 33 , V 34 , V 35  of the full-bridge converter, and the second end of the second winding connects the resistor Rc in series, and then straightly connects to the first clamping diode D 5  and reversely connects to the second clamping diode D 6  respectively, and then clamps on the positive and negative input buses H 1 , H 3 . A capacitor Cs is connected to the two ends of the resistor Rc in parallel. 
         [0025]    In summary, the present invention can greatly reduce the instantaneous current stress on the clamping resistor by connecting a capacitor in parallel to the clamping resistor connected in series so as to enhance the reliability of the clamping resistor and improve the reliability of the entire of the circuit. Thus, it can be referred to as an improved inductance-voltage clamping full-bridge soft-switch circuit, and the capacitor is also called as an absorbing capacitor because of its absorption of the pulse current on the resistor.