Abstract:
A semiconductor memory device includes a plurality of first wirings extending in a first direction, a plurality of memory elements connected with the first wirings, a plurality of second wirings extending in a second direction different from the first direction, the second wirings being disposed opposite to the first wirings with the memory elements interposed between the first and second wirings, the second wirings being spaced from the memory elements, and first transistors or diodes connected between two adjacent of the second wirings.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
         [0001]    This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-399223, filed Dec. 27, 2000; and No. 2001-373071, filed Dec. 6, 2001, the entire contents of both of which are incorporated herein by reference  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to a semiconductor memory device and more specifically to write wirings of a magnetic random access memory (MRAM) which uses tunneling magneto resistive (TMR) elements as memory elements.  
           [0004]    2. Description of the Related Art  
           [0005]    In recent years, MRAM cells have been proposed which utilize the tunneling magneto resistive (hereinafter abbreviated as TMR) effect.  
           [0006]    [0006]FIG. 17 shows an equivalent circuit diagram of a prior-art semiconductor device. FIG. 18 is a schematic sectional view of a TMR element.  
           [0007]    As shown in FIG. 18, a bit line  21  and a pair of word lines  19  and  20  are arranged so that they intersect with each other. At the intersection of the bit line  21  and the write word line  19  is placed a TMR element  20 , which has one end connected to the bit line  21  and one other end connected to a transistor  13 . The gate electrode of the transistor  13  forms the read word line  26 .  
           [0008]    The TMR element  20  is formed into a three-layer structure consisting of two magnetic layers and a non-magnetic layer sandwiched between the magnetic layers. That is, as shown in FIG. 18, the TMR element  20  is formed from a magnetization fixing layer  41  connected with a lower electrode  17 , a magnetic recording layer  43  connected with the bit line  21  by an upper electrode (not shown), and a thin tunnel junction layer  42  sandwiched between the upper and lower layers.  
           [0009]    The magnetization fixing layer  41 , formed from an antiferromagnetic layer and ferromagnetic layer, is referred to as the pin layer because the magnetization is fixed in one direction. On the other hand, the magnetic recording layer  43 , consisting of a ferromagnetic layer, is referred to as the memory layer because the direction of magnetization can be changed freely and hence data can be stored. The direction of magnetization in the magnetic recording layer  43  can be changed by a composite magnetic field resulting from a current in the bit line  21  and a current in the write word line  19 .  
           [0010]    [0010]FIG. 19 illustrates, in sectional view, a prior-art semiconductor memory device. As shown in this diagram, a semiconductor substrate (or a well)  11  of, for example, p-type conductivity is selectively formed with device isolation regions  12  of shallow trench isolation (STI) structure and MOSFETs  13  having n-type source/drain regions  14 . The gate electrode of each MOSFET  13  forms a read word line  26 . First contacts  16   a  are formed in an insulating layer  15  formed over the semiconductor substrate  11  so that they connect to the source/drain regions  14 . First wirings  17   a  are formed on the first contacts  16   a . Likewise, second, third and fourth contacts  16   b ,  16   c  and  16   d  and second, third and fourth wirings  17   b ,  17   c  and  17   d  are formed in the insulating layer  15 . Part of the first wirings  17   a  form ground (GND) lines  18 . Part of the third wirings  17   c  form write word lines  19   a ,  19   b  and  19   c . To each of the fourth wirings  17   d  is connected a TMR element  20  which is connected at the other end to a bit line  21 .  
           [0011]    Next, the read/write operation of the semiconductor memory device will be described briefly.  
           [0012]    To write a 1 or 0 into the TMR element  20 , the corresponding word line  19  and bit line  21  are selected and driven, so that currents flow in the selected word and bit lines to produce magnetic fields. Thereby, the selected cell (TMR element), placed at the intersection of the selected word and bit lines, is subjected to a composite magnetic field which is of such intensity as to allow the reversal of magnetization to occur in the TMR element  20 . As a result, data is written into the selected TMR element.  
           [0013]    When the magnetization fixing layer  41  and the magnetic recording layer  43  are magnetized in the same direction, the resistance of the tunneling junction layer  42  is minimized. This state can be used to store a 1. On the other hand, when the magnetization fixing layer  41  and the magnetic recording layer  43  are magnetized in opposite directions, the resistance of the tunneling junction layer  42  is maximized. This state can be used to store a 0. That is, in the MRAM, the difference in the tunnel resistance is used to store binary digits of one and zero.  
           [0014]    To read information written into the TMR element  20 , on the other hand, the corresponding read word line  26  and bit line  21  are selected, whereupon current flows from the bit line  21  through the corresponding MOSFET  13  to the corresponding ground line  18 . The peripheral circuit can discriminate between stored information 1 and 0 by sensing (the magnitude of the current which depends on) the tunnel resistance.  
         BRIEF SUMMARY OF THE INVENTION  
         [0015]    According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: a plurality of first wirings extending in a first direction; a plurality of memory elements connected with the first wirings; a plurality of second wirings extending in a second direction different from the first direction, the second wirings being disposed opposite to the first wirings with the memory elements interposed between the first and second wirings, the second wirings being spaced from the memory elements; and first transistors or diodes connected between two adjacent of the second wirings.  
           [0016]    According to a second aspect of the present invention, there is provided a semiconductor memory device comprising: a plurality of first wirings extending in a first direction; a plurality of memory elements connected with the first wirings; a plurality of second wirings extending in a second direction different from the first direction, the second wirings being disposed opposite to the first wirings with the memory elements interposed between the first and second wirings, the second wirings being spaced from the memory elements; and second transistors or diodes connected between two adjacent of the second wirings. 
       
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF DRAWING  
       [0017]    [0017]FIG. 1 is a circuit diagram of a semiconductor memory device according to a first embodiment of the present invention;  
         [0018]    [0018]FIG. 2 is a sectional view of the A region of the semiconductor memory device of FIG. 1;  
         [0019]    [0019]FIG. 3 is a sectional view of the B region of the semiconductor memory device of FIG. 1;  
         [0020]    [0020]FIGS. 4A and 4B are sectional views of a single tunneling junction structure used in the embodiments of the present invention;  
         [0021]    [0021]FIGS. 5A and 5B are sectional views of a double tunneling junction structure used in the embodiments of the present invention;  
         [0022]    [0022]FIG. 6 shows current magnetic field versus spacing between adjacent write word lines for different values of current density;  
         [0023]    [0023]FIG. 7 shows the asteroid curve of a TMR element;  
         [0024]    [0024]FIG. 8 is a circuit diagram of another semiconductor memory device according to the first embodiment of the present invention;  
         [0025]    [0025]FIG. 9 is a circuit diagram of a semiconductor memory device according to a second embodiment of the present invention;  
         [0026]    [0026]FIG. 10 is a sectional view of the C region of the semiconductor memory device of FIG. 9;  
         [0027]    [0027]FIG. 11 is a circuit diagram of another semiconductor memory device according to the second embodiment of the present invention;  
         [0028]    [0028]FIG. 12 is a circuit diagram of a semiconductor memory device according to a third embodiment of the present invention;  
         [0029]    [0029]FIG. 13 is a sectional view of the D region of the semiconductor memory device of FIG. 12;  
         [0030]    [0030]FIG. 14 is a circuit diagram of another semiconductor memory device according to the third embodiment of the present invention;  
         [0031]    [0031]FIG. 15 is a circuit diagram of a semiconductor memory device according to a fourth embodiment of the present invention;  
         [0032]    [0032]FIG. 16 is a circuit diagram of another semiconductor memory device according to the fourth embodiment of the present invention;  
         [0033]    [0033]FIG. 17 is a circuit diagram of a conventional semiconductor memory device;  
         [0034]    [0034]FIG. 18 is a sectional view of the conventional semiconductor memory device of FIG. 17; and  
         [0035]    [0035]FIG. 19 is a sectional view of the conventional semiconductor memory device. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0036]    With conventional semiconductor memory devices, the cell-to-cell spacing has been reduced with advances in fine pattern technology; that is, the spacing between adjacent write word lines, indicated at X in FIG. 19, has fallen below 1 μm. Therefore, at the time of writing data, a magnetic field produced by a current that flows in, for example, the write word line  19   b  would reach the next adjacent write word lines  19   a  and  19   b , resulting in a problem of crosstalk to adjacent cells.  
         [0037]    The present invention is directed to a semiconductor memory device in the form of a magnetic random access memory (MRAM) using tunneling magneto resistive (TMR) elements. This MRAM is a memory cell array structure in which a large number of memory cells having TMR elements are arranged in a matrix. The MRAM has address decoders and sense circuits formed on the outside of the cell array to allow an individual memory cell to be accessed for reading or writing.  
         [0038]    Hereinafter, the embodiments of the present invention will be described with reference to the accompanying drawings, wherein like reference numerals designate like or corresponding parts throughout several views.  
         [0039]    [First Embodiment] 
         [0040]    The first embodiment is configured such that a transistor is connected between each write word line and the next adjacent write word line so that, at the time of writing into a memory cell, a current will flow in the opposite direction in the write word lines adjacent to the write word line associated with that memory cell.  
         [0041]    [0041]FIG. 1 is a circuit diagram of a semiconductor memory device according to the first embodiment of the present invention. FIG. 2 is a sectional view of a region A shown in FIG. 1. FIG. 3 is a sectional view of a B region shown in FIG. 1.  
         [0042]    As shown in FIG. 1, bit lines  21  and word lines  19  ( 26 ) are arranged in rows and columns, respectively. The word lines comprise write word lines  19  and read word lines  26 . TMR elements  20  are located at the intersections of the bit lines  21  and the write word lines  19  to form a memory cell array. Outside the memory cell array area, each write word line  19  is connected at one end to a current driver circuit  33  and at the other end to transistors (e.g., MOSFETs)  23 .  
         [0043]    An A region shown in FIG. 1 will be described next. The A region shows the standard MRAM structure. That is, as shown in FIG. 2, a semiconductor substrate (or a well)  11  of, for example, p-type conductivity is selectively formed with device isolation regions  12  of shallow trench isolation (STI) structure and MOSFETs  13  having n-type source/drain regions  14 . The MOSFETs are read switching elements and their gate electrodes form the read word lines  26 . First contacts  16   a  are formed in an insulating layer  15  formed over the semiconductor substrate  11  so that they connect to the source/drain regions  14 . First wirings  17   a  are formed on the first contacts  16   a . Likewise, second, third and fourth contacts  16   b ,  16   c  and  16   d  and second, third and fourth wirings  17   b ,  17   c  and  17   d  are formed in the insulating layer  15 . Part of the first wirings  17   a  form ground (GND) lines  18 . Part of the third wirings  17   c  form write word lines  19   a ,  19   b  and  19   c . To each of the fourth wirings  17   d  is connected a TMR element  20  which is connected at the other end to a bit line  21 .  
         [0044]    The B region shown in FIG. 1 will be described next. This region is characteristic of the first embodiment of the present invention. That is, as shown in FIG. 3, a third contact  16   c , a second wiring  17   b , a second contact  16   b , a first wiring  17   a  and a first contact  16   a  are connected in this order to each of the write word lines  19   a ,  19   b , and  19   c.    
         [0045]    Each of the first contacts  16   a  is connected to a corresponding one of the source/drain regions  24  of transistors  23   a  and  23   b  formed in the semiconductor substrate  11 . Namely, the transistor  23   a  is introduced between the adjacent write word lines  19   a  and  19   b , and the transistor  23   b  is introduced between the adjacent write word lines  19   b  and  19   c.    
         [0046]    Next, the structure of the TMR elements  20  will be described. The TMR element  20  is composed, as shown in FIG. 2, of a magnetization fixing layer (magnetic layer)  41 , a tunnel junction layer (nonmagnetic layer)  42 , and a magnetic recording layer (magnetic layer)  43 . This element may be of either the single tunnel junction structure or the double tunnel junction structure, which will be described below.  
         [0047]    [0047]FIGS. 4A and 4B are sectional views of TMR elements of the single tunnel junction structure.  
         [0048]    The TMR element  20  shown in FIG. 4A comprises a magnetization fixing layer  41 , a tunnel junction layer  42 , and a magnetic recording layer  43 , which are stacked in this order. The magnetization fixing layer  41  consists of a template layer  101 , an initial ferromagnetic layer  102 , an antiferromagnetic layer  103 , and a reference ferromagnetic layer  104  stacked in this order. The magnetic recording layer  43  consists of a free ferromagnetic layer  105  and a contact layer  106 .  
         [0049]    The TMR element  20  shown in FIG. 4B likewise comprises the magnetization fixing layer  41 , the tunnel junction layer  42 , and the magnetic recording layer  43 ., The magnetization fixing layer  41  is formed from a template layer  101 , an initial ferromagnetic layer  102 , an antiferromagnetic layer  103 , a ferromagnetic layer  104 ′, a nonmagnetic layer  107 , and a ferromagnetic layer  104 ″, which are stacked in the order mentioned. The magnetic recording layer  43  is formed from a ferromagnetic layer  105 ′, a nonmagnetic layer  107 , a ferromagnetic layer  105 ″ and a contact layer  106 , which are stacked in the order mentioned.  
         [0050]    In the TMR element shown in FIG. 4B, a three-layer structure of ferromagnetic layer  104 ′, nonmagnetic layer  107 , and ferromagnetic layer  104 ″ is introduced in the magnetization fixing layer  41 . Moreover, a three-layer structure of ferromagnetic layer  105 ′, nonmagnetic layer  107  and ferromagnetic layer  105 ″ is introduced in the magnetic recording layer  43 . This configuration makes the formation of magnetic poles in the ferromagnetic material more difficult than in the TMR element shown in FIG. 4A and is therefore more suitable for scaling down the dimensions of cells.  
         [0051]    The double tunnel junction structures of TMR elements are illustrated in FIGS. 5A and 5B.  
         [0052]    The TMR element of FIG. 5A comprises a first magnetization fixing layer  51 , a first tunnel junction layer  52 , a magnetic recording layer  43 , a second tunnel junction layer  53 , and a second magnetization fixing layer  54 , which are stacked in the order mentioned. The first magnetization fixing layer  51  consists of a template layer  101 , an initial ferromagnetic layer  102 , an antiferromagnetic layer  103 , and a reference ferromagnetic layer  104  which are stacked in the order mentioned. The second magnetization fixing layer  54  consists of a reference ferromagnetic layer  104 , an antiferromagnetic layer  103 , an initial ferromagnetic layer  102 , and a contact layer  106 , which are stacked in the order mentioned.  
         [0053]    The TMR element of FIG. 5B likewise comprises a first magnetization fixing layer  51 , a first tunnel junction layer  52 , a magnetic recording layer  43 , a second tunnel junction layer  53 , and a second magnetization fixing layer  54 , which are stacked in the order mentioned. The first magnetization fixing layer  51  consists of a template layer  101 , an initial ferromagnetic layer  102 , an antiferromagnetic layer  103 , and a reference ferromagnetic layer  104 , which are stacked in the order mentioned. The magnetic recording layer  43  consists of a ferromagnetic layer  43 ′, a nonmagnetic layer  107 , and a ferromagnetic layer  43 ′, which are stacked in the order mentioned. The second magnetization fixing layer  54  consists of a ferromagnetic layer  104 ′, a nonmagnetic layer  107 , a ferromagnetic layer  104 ″ an antiferromagnetic layer  103 , an initial ferromagnetic layer  102 , and a contact layer  106 , which are stacked in the order mentioned.  
         [0054]    The TMR element of FIG. 5B is configured such that a three-layer structure is introduced in each of the second magnetization fixing layer  54  and the magnetic recording layer  43 . This configuration makes the formation of magnetic poles in the ferromagnetic material more difficult than in the TMR element shown in FIG. 5A and is therefore more suitable for scaling down the dimensions of cells.  
         [0055]    In comparison with the TMR element of the single tunnel junction structure, the TMR element of the double tunnel junction structure has a higher magneto resistance (MR) ratio (the ratio in resistance of the “1” state to the “0” state) when the same external bias is applied and can therefore be operated from higher biases. This is advantageous in reading data from cells to the outside.  
         [0056]    The TMR elements described above are formed using the following materials:  
         [0057]    For the magnetization fixing layers  41 ,  51  and  54  and the magnetic recording layer  43 , it is desirable to use (1) Fe, Co, Ni, or their alloys, (2) magnetites large in spin polarizability, (3) oxides, such as CrO 2 , RXMnO 3-y , etc., and (4) Heusler&#39;s alloys, such as NiMnSb, PtMnSb, etc. Nonmagnetic elements, such as Ag, Cu, Au, Al, Mg, Si, Bi, Ta, B, C, O, N, Pd, Pt, Zr, Ir, W, Mo, Nb, etc., may be contained in some quantity in the above magnetic materials as long as their ferromagnetic property is retained.  
         [0058]    For the antiferromagnetic layer  103  forming part of the magnetization fixing layer  41 , it is desirable to use Fe—Mn, Pt—Mn, Pt—Cr—Mn, Ni—Mn, Ir—Mn, NiO, or Fe 2 O 3 .  
         [0059]    For the tunnel junction layers  42 ,  52  and  53 , a dielectric material, such as Al 2 O 3 , SiO 2 , MgO, AlN, Bi 2 O 3 , MgF 2 , CaF 2 , SrTiO 2 , or AlLaO 3 , can be used. Oxygen, nitrogen or fluorine deficiency is allowed to be present in these dielectric materials.  
         [0060]    Next, the operation of writing data into the semiconductor memory device of the first embodiment will be described.  
         [0061]    [0061]FIG. 6 shows magnetic field intensity versus spacing between every two adjacent write word lines. Here, the sectional area of the write wirings (the write word lines  19  and the bit lines  21 ) is assumed to be (0.1×0.1) μm 2 .  
         [0062]    As can be seen from FIG. 6, the intensity of the magnetic field generated varies with the spacing X between each write word line and the current density in the write word lines. That is, the intensity of the magnetic field increases as the spacing X between each write word line decreases. Also, the intensity of the magnetic field increases as the current density increases.  
         [0063]    [0063]FIG. 7 shows the asteroid curve of the TMR element. In this diagram, the horizontal axis represents the intensity of the magnetic field in the direction of the fixed axis and the vertical axis represents the intensity of the magnetic field in the direction of the easy axis.  
         [0064]    Hereinafter, the writing of information “1” and “0” will be described using the asteroid curve. In the description which follows, the spacing X between each write word line is assumed to be 0.1 μm. The wirings in the direction of the fixed axis are assumed to be the write word lines  19  and the wirings in the direction of the easy axis are assumed to be the bit lines  21 .  
         [0065]    To write “1”, it is required to produce a composite magnetic field the intensity of which lies within the P region. That is, assuming that the write word line  19  is driven to produce a magnetic field having an intensity of, say, 10 Oe, it is required to drive the bit line to produce a magnetic field of the order of 20 to 25 Oe. To this end, the write word line is simply driven with a current the density of which is 5 MA/cm 2  and the bit line with a current the density of which is 10 MA/cm 2  (see FIG. 6). By producing a composite magnetic field the intensity of which lies within the P region in this manner, the direction of magnetization can be changed to write “1”.  
         [0066]    To write 0, on the other hand, it is required to generate a composite magnetic field the intensity of which lies within the Q region. That is, assuming that the write word line  19  is driven to produce a magnetic field having an intensity of, say, 10 Oe, it is required to drive the bit line to produce a magnetic field of the order of 20 to 30 Oe. To this end, the write word line is simply driven with a current the density of which is 5 MA/cm 2  and the bit line with a current the density of which is 10 MA/cm 2  (see FIG. 6). By producing a composite magnetic field the intensity of which lies within the Q region in this manner, the direction of magnetization can be changed to write “0”.  
         [0067]    Next, a description is given of the operation of writing data into a cell with a transistor connected between each write word line.  
         [0068]    First, in the arrangement of FIG. 1, to write data into a certain cell  30 , the bit line  21   b  and the write word line  19   b  are selected and then current driven so that a composite magnetic field is produced which has an intensity that lies within the P region or the Q region shown in FIG. 7. When a transistor  31  of the current driver  33  is turned on in order to cause a current  25  to flow in a first direction in the write word line  19   b , transistors  23   a  and  23   b  are also turned on. As a result, the current  25  in the write word line  19   b  passes through the transistors  23   a  and  23   b  and flows as currents  25   a  and  25   b  in the respective write word lines  19   a  and  19   c  each adjacent to the write word line  19   b . The currents  25   a  and  25   b  are in the opposite direction (a second direction) to the current  25 .  
         [0069]    Thus, magnetic fields  32   a  and  32   b  resulting from the currents  25   a  and  25   b  in the write word lines  19   a  and  19   b  are each opposite in direction to a magnetic field  32  produced by the current  25  in the word line  19   b . For this reason, even if the magnetic field  32  produced by the write word line  19   b  reaches the write word lines  19   a  and  19   b , it will be canceled by the magnetic fields  32   a  and  32   b  produced by the lines  19   a  and  19   b.    
         [0070]    The data written into the TMR element in the aforementioned manner can be read through the standard method. That is, as shown in FIG. 2, the MOSFET  13  connected to the TMR element  20  in which data is stored is simply turned on so that a current path is formed which extends from the bit line  21  through the TMR element, the contacts  16   a ,  16   b ,  16   c  and  16   d , the wirings  17   a ,  17   b ,  17   c  and  17   d , and the source/drain regions  14  to ground. The resistance of the TMR element can be read to discriminate between “1” and “0”.  
         [0071]    According to the first embodiment, the connection of transistors between each write word line allows, when writing data into a TMR element, currents to flow in write word lines  19   a  and  19   c , adjacent to the write word line  19   b  associated with that TMR element, in the reverse direction to that in the line  19   b . Therefore, the magnetic field resulting from the write current  25  is canceled by magnetic fields  32   a  and  32   b  resulting from the reverse currents  25   a  and  25   b . As a result, it becomes possible to prevent adjacent cells from being written into in error, allowing the crosstalk problem to be resolved.  
         [0072]    In the first embodiment, transistors  23  may be connected between each bit line  21  as shown in FIG. 8. Furthermore, the arrangements of FIGS. 1 and 8 may be used in combination. These arrangements will also provide the same advantages as described in the first embodiment.  
         [0073]    [Second Embodiment] 
         [0074]    The second embodiment is arranged such that diodes are connected between each write word line in place of the transistors in the first embodiment.  
         [0075]    [0075]FIG. 9 is a circuit diagram of a semiconductor memory device according to the second embodiment of the present invention. FIG. 10 is a sectional view of a region C shown in FIG. 9. The sectional view of the A region shown in FIG. 9 remains unchanged from FIG. 2 and hence description thereof is omitted.  
         [0076]    As shown in FIG. 9, bit lines  21  and word lines  19  ( 26 ) are arranged in rows and columns, respectively. The word lines comprise write word lines  19  and read word lines  26 . TMR elements  20  are located at the intersections of the bit lines  21  and the write word lines  19  to form a memory cell array. Outside the memory cell array area, each write word line  19  is connected at its one end to a current driver circuit  33  and at its other end to diodes  61 .  
         [0077]    The C region shown in FIG. 9 will be described next. This region is characteristic of the second embodiment of the present invention. That is, as shown in FIG. 10, a third contact  16   c , a second wiring  17   b , a second contact  16   b , a first wiring  17   a  and a first contact  16   a  are connected in this order to each of the write word lines  19   a  and  19   b.    
         [0078]    Each of the first contacts  16   a  is connected to a PN junction diode  61  formed in the semiconductor substrate  11 . Namely, the diode  61  is introduced between the adjacent write word lines  19   a  and  19   b.    
         [0079]    The write operation of the second embodiment will be described hereinafter.  
         [0080]    First, in the arrangement of FIG. 9, to write data into the TMR element  20  in a certain cell  30 , the bit line  21   b  and the write word line  19   b  are selected and then current driven so that a composite magnetic field is generated which has an intensity that lines within the P region or the Q region shown in FIG. 7. When a forward bias voltage is applied to a transistor  31  of the current driver  33  in order to cause a current  25  to flow in a first direction in the write word line  19   b , the current  25  flows through the diodes  61   a  and  61   b  as well. As a result, currents  25   a  and  25   b  respectively flow in the write word lines  19   a  and  19   c  in the opposite direction (a second direction) to the current  25 .  
         [0081]    Thus, magnetic fields  32   a  and  32   b  resulting from the currents  25   a  and  25   b  in the write word lines  19   a  and  19   b  are each opposite in direction to a magnetic field  32  produced by the current  25  in the word line  19   b . For this reason, even if the magnetic field  32  produced by the write word line  19   b  reaches the write word lines  19   a  and  19   b , it will be canceled by the magnetic fields  32   a  and  32   b  produced by the lines  19   a  and  19   b.    
         [0082]    The information written into the TMR element  20  can be read in the same manner as in the first embodiment; thus, description of the read operation is omitted.  
         [0083]    The second embodiment can provide the same advantages as the first embodiment.  
         [0084]    In the second embodiment, diodes  61  may be connected between each bit line  21  as shown in FIG. 11. Furthermore, the arrangements of FIGS. 9 and 11 may be used in combination. These arrangements will also provide the same advantages as described in the second embodiment.  
         [0085]    [Third Embodiment] 
         [0086]    The third embodiment is a modification of the first embodiment in which the transistors as read switching elements are replaced by diodes.  
         [0087]    [0087]FIG. 12 is a circuit diagram of a semiconductor memory device according to the third embodiment of the present invention. FIG. 13 is a sectional view of a region D shown in FIG. 12.  
         [0088]    As shown in FIG. 12, in the B region, as in the first embodiment, the transistor  23   a  is introduced between adjacent write word lines  19   a  and  19   b  and the transistor  23   b  is introduced between adjacent write word lines  19   b  and  19   c.    
         [0089]    As shown in FIG. 13, in the D region, each of the TMR elements  20  located at the intersections of the bit line  21  and the write word lines  19   a ,  19   b  and  19   c  is connected in series with a diode  71 .  
         [0090]    The write operation of the third embodiment remains unchanged from that of the first embodiment; thus, description thereof is omitted. The read operation of the third embodiment is performed in the following manner. That is, bias voltage is adjusted so that a current will flow in the diode connected with a TMR element into which data has been written and then the resistance of that TMR element is read out. A change in the resistance of the TMR element allows discrimination between “1” and “0”.  
         [0091]    The third embodiment will also provide the same advantage as the first embodiment.  
         [0092]    The third embodiment that uses diodes as switching elements requires less area for the memory cell array than the first and second embodiment that use transistors.  
         [0093]    As shown in FIG. 14, transistors  23  may be introduced between each bit line  21 . Furthermore, the arrangements of FIGS. 12 and 14 may be used in combination. These arrangements will also provide the same advantages as described in the third embodiment.  
         [0094]    [Fourth Embodiment] 
         [0095]    The fourth embodiment is a modification of the second embodiment in which the transistors as read switching elements are replaced by diodes.  
         [0096]    [0096]FIG. 15 is a circuit diagram of a semiconductor memory device according to the fourth embodiment of the present invention. As shown in FIG. 15, in the C region, as in the second embodiment, the diode  61   a  is introduced between adjacent write word lines  19   a  and  19   b  and the diode  61   b  is introduced between adjacent write word lines  19   b  and  19   c . In the D region, as in the third embodiment, each of the TMR elements  20  located at the intersections of the bit line  21  and the write word lines  19   a ,  19   b  and  19   c  is connected in series with a PN junction diode  71 .  
         [0097]    The write operation of the fourth embodiment remains unchanged from that of the second embodiment; thus, description thereof is omitted. The read operation of the fourth embodiment is the same as in the third embodiment; thus, description thereof is omitted.  
         [0098]    The fourth embodiment will also provide the same advantage as the second embodiment.  
         [0099]    The fourth embodiment that uses diodes as switching elements requires less area for the memory cell array than the first and second embodiments that use transistors.  
         [0100]    As shown in FIG. 16, diodes  61  may be introduced between each bit line  21 . Furthermore, the arrangements of FIGS. 15 and 16 may be used in combination. These arrangements will also provide the same advantages as described in the fourth embodiment.  
         [0101]    In the embodiments described so far, the TMR elements may be replaced by GMR (Giant Magneto Resistive) elements each of which comprises two magnetic layers and a conductive layer sandwiched between the magnetic layers. In addition, the memory cell array structure may be modified in various ways as needed.  
         [0102]    Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.