Abstract:
A power consumption reduction circuit for reducing power consumed by a clock tree network including a transmission control circuit. The power consumption reduction circuit includes a transmission control circuit for controlling transmission of the clock signal to the buffer circuit group so as to selectively provide and interrupt the clock signal. A switch circuit disconnects the buffer circuit group from a power supply when the transmission control circuit interrupts the clock signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2005-103941, filed on Mar. 31, 2005, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     The present invention relates to a clock network for transmitting a clock signal, and more particularly, to a clock tree network provided with a power consumption reduction function.  
         [0003]     In a semiconductor integrated circuit device, synchronization circuits including flip-flop circuits may be provided with a clock signal from a clock tree network configured by buffer circuits. The higher integration of recent semiconductor integrated circuit devices has increased the number of buffer circuits in a clock tree network. Due to the demand for lower power consumption of semiconductor integrated circuit devices, the power consumed by a clock network tree must be reduced.  
         [0004]      FIG. 1   a  is a schematic circuit diagram showing a first prior art example of a clock network  100   a . The clock network  100   a  provides a clock signal CLK in parallel to a plurality of flip-flop circuits FF 1  to FF 4 . The clock signal CLK is provided to the flip-flop circuits FF 1  to FF 4  via a buffer circuit group  1   a.    
         [0005]      FIG. 1   b  is a schematic circuit diagram showing a second prior art example of a clock tree network  100   b  including a gated clock buffer (GCB), which functions as a transmission control circuit. Flip-flop circuits FF 1  and FF 2  are provided with a clock signal CLK via a buffer circuit group  1   a . Flip-flop circuits FF 3  and FF 4  are provided with the clock signal CLK via the GCB and a buffer circuit group  1   b.    
         [0006]     When there is no need to provide the flip-flop circuits FF 3  and FF 4  with the clock signal CLK, the GCB interrupts the clock signal CLK provided to the buffer circuit group  1   b . This reduces the power consumption of the buffer circuit group  1   b.    
         [0007]     Less buffer circuits and a shorter network are effective for reducing the power consumed by the above-described clock tree network. The use of a transistor having a relatively low threshold in each buffer circuit to increase the load driving capacity is also effective. However, a transistor having a relatively low threshold would increase leakage current during inactivation.  
         [0008]      FIG. 2  is a schematic circuit diagram showing a third prior art example of a clock network  200  for decreasing leakage current in buffer circuits, which configure the clock network  200 . The clock network  200  includes a switch circuit  2 , which is connected between a buffer circuit group  1   c  and a power supply VDD, and a switch circuit  3 , which is connected between the buffer circuit group  1   c  and a power supply VSS. In a standby state, the switch circuit  2  and the switch circuit  3  are disconnected from the power supplies VDD and VSS, respectively. This stops the flow of leakage current from the power supply VDD to the power supply VSS in the standby state.  
         [0009]      FIG. 3  is a schematic circuit diagram showing a fourth prior art example of a clock network  300 . In the clock network  300 , the switch circuit  2  and switch circuit  3  of the clock network  200  are respectively embodied by a P-channel MOS transistor Tr 1  and an N-channel MOS transistor Tr 2 . In the clock network  300 , when a buffer circuit group  1   c  is in a standby state (power save mode), the transistors Tr 1  and Tr 2  are inactivated to stop the flow of leakage current from the power supply VDD to the power supply VSS.  
         [0010]     Due to the miniaturization of semiconductor integrated circuit devices in recent years, when the gate of a transistor is narrowed, the leakage current during inactivation tends to relatively increase. By using the transistors Tr 1  and Tr 2  having a relatively high threshold, leakage current would be decreased during inactivation. Further, in the buffer circuit group  1   c , the use of a transistor having a relatively low threshold would increases the load drive capacity. This would reduce the number of buffer circuits and shorten the network length.  
         [0011]     Japanese Laid-Open Patent Publication No. 2000-82286 describes a CMOS circuit connected to a power supply switch including a transistor, which is inactivated during a standby state. Due to the power supply switch, the leakage current produced when the CMOS circuit is in the standby state is only the leakage current produced by a power supply switch including a transistor.  
       SUMMARY OF THE INVENTION  
       [0012]     In the clock tree network including the GCB and shown in  FIG. 1   b , the power consumption of the buffer circuit group  1   b  is reduced when the GCB interrupts the clock signal CLK and suspends the operation of the buffer circuit group  1   b . However, leakage current does not stop current flow in the buffer circuit group  1   b . Thus, the leakage current hinders reduction of power consumption. Particularly, when using transistors having a relatively low threshold to ensure the load driving capacity, leakage current increases in the buffer circuit group  1   b.    
         [0013]     In Japanese Laid-Open Patent Publication No. 2000-82286 or in the buffer circuit group  1   c  including switch circuits for reducing leakage current and shown in  FIG. 3 , when a chip is entirely set in the power save mode, in response to the control signal, the buffer circuit group  1   c  is disconnected from the power supply VDD and the power supply VSS. This prevents the generation of leakage current. However, when the GCB interrupts the clock signal CLK provided to the buffer circuit group, which is part of the clock tree network, the switch circuits of the buffer circuit group are not inactivated. As a result, leakage current is not sufficiently suppressed.  
         [0014]     The present invention provides a power consumption reduction circuit for reducing the power consumed by a clock tree network including a transmission control circuit.  
         [0015]     One aspect of the present invention is a power consumption reduction circuit for use in a clock network including a power supply and a buffer circuit group for transmitting a clock signal. The power consumption reduction circuit includes a transmission control circuit for controlling transmission of the clock signal to the buffer circuit group so as to selectively provide and interrupt the clock signal. A switch circuit, connected between the buffer circuit group and the power supply, disconnects the buffer circuit group and the power supply when the transmission control circuit interrupts the clock signal.  
         [0016]     Another aspect of the present invention includes a clock network for use with a power supply. The clock network includes a buffer circuit group for transmitting a clock signal. A transmission control circuit controls transmission of the clock signal to the buffer circuit group so as to selectively provide and interrupt the clock signal. A switch circuit, connected between the buffer circuit group and the power supply, disconnects the buffer circuit group and the power supply when the transmission control circuit interrupts the clock signal.  
         [0017]     Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]     The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which:  
         [0019]      FIG. 1   a  is a schematic circuit diagram showing a first prior art example of a clock network;  
         [0020]      FIG. 1   b  is a schematic circuit diagram showing a second prior art example of a clock network including a GCB, which functions as a transmission control circuit;  
         [0021]      FIG. 2  is a schematic circuit diagram showing a third prior art example of a clock network;  
         [0022]      FIG. 3  is a schematic circuit diagram showing a fourth prior art example of a clock network;  
         [0023]      FIG. 4  is a schematic circuit diagram showing a clock tree network provided with a power consumption reduction function according to a first embodiment of the present invention;  
         [0024]      FIG. 5  is a schematic circuit diagram showing a clock tree network provided with a power consumption reduction function according to a second embodiment of the present invention;  
         [0025]      FIG. 6  is a schematic circuit diagram showing a clock tree network provided with a power consumption reduction function according to a third embodiment of the present invention;  
         [0026]      FIG. 7  is a schematic circuit diagram showing a clock tree network provided with a power consumption reduction function according to a fourth embodiment of the present invention;  
         [0027]      FIG. 8  is a schematic circuit diagram showing a clock tree network provided with a power consumption reduction function according to a fifth embodiment of the present invention;  
         [0028]      FIG. 9  is a schematic circuit diagram showing a clock tree network provided with a power consumption reduction function according to a sixth embodiment of the present invention;  
         [0029]      FIG. 10  is a timing and waveform diagram showing the operation of the sixth embodiment of the present invention;  
         [0030]      FIG. 11  is a schematic circuit diagram showing a clock tree network provided with a power consumption reduction function according to a seventh embodiment of the present invention; and  
         [0031]      FIG. 12  is a schematic circuit diagram showing a clock tree network provided with a power consumption reduction function according to an eighth embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0032]     In the drawings, like numerals are used for like elements throughout.  
         [0033]      FIG. 4  is a schematic circuit diagram showing a clock tree network  400  provided with a power consumption reduction function according to a first embodiment of the present invention. The clock tree network  400  includes a buffer circuit group  11   a , which receives a clock signal CLK via a GCB functioning as a transmission control circuit. The buffer circuit group  11   a  includes an even number of series connected inverter circuits (buffer circuits).  
         [0034]     The GCB is provided with the clock signal CLK and a control signal A. The GCB provides the buffer circuit group  11   a  with the clock signal CLK as an output signal X when the control signal A is set at a low (L) level. The GCB fixes the output signal X at the L level when the control signal A is set at a high (H) level.  
         [0035]     A plurality of flip-flop circuits FF are connected in parallel to the output terminal of the buffer circuit group  11   a . The buffer circuit group  11   a  is connected to a high potential power supply VDD via a P-channel MOS transistor Tr 3 , which functions as a switch circuit, and a lower power supply VSS via an N-channel MOS transistor Tr 4 , which also functions as a switch circuit. The transistors Tr 3  and Tr 4  have relatively high thresholds. The buffer circuit group  11   a  is configured by transistors having relatively low thresholds.  
         [0036]     The gate of the transistor Tr 3  is provided with the control signal A. An inverter circuit  12  inverts the control signal A and generates an inverted control signal, which is provided to the gate of the transistor Tr 4 . Accordingly, when the control signal A is set at an L level, that is, when the clock signal CLK is provided from the GCB to the buffer circuit group  11   a , the transistors Tr 3  and Tr 4  are activated. This activates the buffer circuit group  11   a  and provides the clock signal CLK to each of the flip-flop circuits FF.  
         [0037]     When the control signal A is set at an H level, that is, when the output signal of the GCB is fixed at an L level, the transistors Tr 3  and Tr 4  are inactivated. This disconnects the buffer circuit group  11   a  from the power supplies VDD and VSS. Accordingly, the buffer circuit group  11   a  is inactivated, and an indefinite output signal is generated at an output node of the buffer circuit group  11   a.    
         [0038]     The clock tree network  400  of the first embodiment has the advantages described below.  
         [0039]     (1) When the GCB is activated in accordance with the control signal A, the buffer circuit group  11   a  is activated and the clock signal CLK is provided in parallel to the flip-flop circuits FF.  
         [0040]     (2) In synchronism with when the GCB is inactivated in accordance with the control signal A, the buffer circuit group  11   a  is disconnected from the power supplies VDD and VSS. This inactivates the buffer circuit group  11   a.    
         [0041]     (3) The transistors Tr 3  and Tr 4  have relatively high thresholds. This reduces leakage current from the power supply VDD to the power supply VSS when the buffer circuit group  11   a  is inactivated.  
         [0042]     (4) In synchronism with the inactivation of the GCB, the transistors Tr 3  and Tr 4  are inactivated. Accordingly, when the buffer circuit group  11   a  is inactivated, the transistors Tr 3  and Tr 4  are inactivated to reduce leakage current.  
         [0043]      FIG. 5  is a schematic circuit diagram showing a clock tree network  500  provided with a power consumption reduction function according to a second embodiment of the present invention. The clock tree network  500  suppresses differences in wiring resistances between the power supply VDD and inverter circuits of a buffer circuit group  11   a  and between the power supply VSS and the inverter circuits.  
         [0044]     When the buffer circuit group  11   a  is configured by a large number of buffer circuits, or a large number of inverter circuits, concentration of switch circuits for connecting the inverter circuits to the power supply VDD and the power supply VSS increases differences in the resistances between the inverter circuits and the power supply VDD and between the inverter circuits and the power supply VSS.  
         [0045]     Thus, to decrease the differences in the resistances between the inverter circuits and the power supply VDD and between the inverter circuits and the power supply VSS, transistors Tr 3   a  to Tr 3   c  are distributed between the power supply VDD and a high potential power supply line (power supply node) L 1  of the inverter circuits. In the same manner, transistors Tr 4   a  to Tr 4   c  are distributed between the power supply VSS and a low potential power supply line (power supply node) L 2  of the inverter circuits.  
         [0046]     In addition to the advantages of the clock tree network  400  of the first embodiment that controls the clock signal CLK provided to the buffer circuit group  11   a  with the GCB, the clock tree network  500  of the second embodiment has an advantage in that differences in the characteristics of the buffer circuits are decreased.  
         [0047]      FIG. 6  is a schematic circuit diagram showing a clock tree network  600  provided with a power consumption reduction function according to a third embodiment of the present invention. The clock tree network  600  is configured by adding to the clock tree network  500  of the second embodiment, a capacitor C 1 , which is connected between the high potential power supply line L 1  and the power supply VSS, and a capacitor C 2 , which is connected between the low potential power supply line L 2  and the power supply VDD.  
         [0048]     With the configuration of the clock tree network  600 , when the transistors Tr 3   a  to Tr 3   c  perform switching operations, the capacitor C 1  absorbs noise produced at the high potential power supply line L 1  due to gate coupling that occurs between the high potential power supply line L 1  and the gates of the transistors Tr 3   a  to Tr 3   c.    
         [0049]     Further, the capacitor C 2  absorbs noise produced at the low potential power supply line L 2  due to gate coupling that occurs between the low potential power supply line L 2  and the gates of the transistors Tr 4   a  to Tr 4   c.    
         [0050]     In addition to the advantages of the clock tree network  500  of the second embodiment, the clock tree network  600  has an advantage in that the absorption of noise with the capacitors C 1  and C 2  stabilizes the operation of each inverter circuit.  
         [0051]      FIG. 7  is a schematic circuit diagram showing a clock tree network  700  provided with a power consumption reduction function according to a fourth embodiment of the present invention. To configure the clock tree network  700 , each inverter circuit of the clock tree network  600  in the third embodiment is additionally provided with the switch circuit connected to the power supply VDD, the switch circuit connected to the power supply VSS, and capacitors connected to each power supply node.  
         [0052]     More specifically, transistors Tr 3   a  to Tr 3   d  are respectively connected between the inverter circuits and the power supply VDD. Further, transistors Tr 4   a  to Tr 4   d  are respectively connected between the inverter circuits and the power supply VSS.  
         [0053]     Further, capacitors C 1   a  to C 1   d  are respectively connected between the power supply VSS and a node between the inverter circuits and corresponding transistors Tr 3   a  to Tr 3   d . Capacitors C 2   a  to C 2   d  are respectively connected between the power supply VDD and a node between the inverter circuits and corresponding transistors Tr 4   a  to Tr 4   d.    
         [0054]     In the clock tree network  700  of the fourth embodiment, the resistance between each inverter circuit and the power supply VDD and the resistance between each inverter circuit and the power supply VSS are uniformed. Further, a capacitor is connected to the power supply node of each inverter circuit. Thus, the noise produced at the power supply node of each inverter circuit is suppressed and uniformed.  
         [0055]     Accordingly, in comparison with the clock tree network  600  of the third embodiment, in the fourth embodiment, the operations of the inverter circuits configuring the buffer circuit group  11   a  are further stabilized.  
         [0056]      FIG. 8  is a schematic circuit diagram showing a clock tree network  800  provided with a power consumption reduction function according to a fifth embodiment of the present invention. The clock tree network  800  is configured by adding a clamp circuit for clamping an output node of the buffer circuit group  11   a  at the level of the power supply VSS when the buffer circuit group  11   a  is inactivated.  
         [0057]     More specifically, the output node of the buffer circuit group  11   a  is connected to the power supply VSS via an N-channel MOS transistor Tr 5 . The gate of the transistor Tr 5  is provided with an inverted signal generated by an inverter circuit  13  inverting the signal provided to the gates of the transistors Tr 4   a  to Tr 4   d . Accordingly, the phase of the gate signal of the transistor Tr 5  is the same as the control signal A provided to the GCB.  
         [0058]     In the clock tree network  800  of the fifth embodiment, when the control signal A is set at an H level, that is, when the transistors Tr 3   a  to Tr 3   d  and Tr 4   a  to Tr 4   d  are inactivated and the buffer circuit group  11   a  is inactivated, the transistor Tr 5  is activated to clamp the output node of the buffer circuit group  11   a  at the level of the power supply VSS.  
         [0059]     When the buffer circuit group  11   a  is inactivated and the potential at the output node is indefinite, there is a tendency for the operation of the buffer circuit group  11   a  to be affected by crosstalk noise from proximal wires. However, such influence from noise is eliminated by clamping the output node at the level of the power supply VSS.  
         [0060]     Accordingly, in addition to the advantages of the clock tree network  700  of the fourth embodiment, the clock tree network  800  of the fifth embodiment has an advantage in that the operation of the buffer circuit group  11   a  in an inactivated state is stabilized.  
         [0061]      FIG. 9  is a schematic circuit diagram showing a clock tree network  900  provided with a power consumption reduction function according to a sixth embodiment of the present invention. The clock tree network  900  is an improvement of the clock tree network  800  of the fifth embodiment. In the clock tree network  900  of the sixth embodiment, when the buffer circuit group  11   a  shifts from an inactivated state to an activated state, all of the transistors Tr 3   a  to Tr 3   d  and Tr 4   a  to Tr 4   d  are activated, and each of the inverter circuits configuring the buffer circuit group  11   a  are activated. Then, the clock signal CLK is provided from the GCB to the buffer circuit group  11   a.    
         [0062]     More specifically, the control signal A is provided to an OR circuit  14 . Further, the control signal A is provided to the gates of the transistors Tr 3   a  to Tr 3   d  and then provided as control signal A 1  to the OR circuit  14 . The control signal A is also provided to the gates of the transistors Tr 4   a  to Tr 4   d  and then provided as control signal A 2  to the OR circuit  14 . The control signals A 1  and A 2  are provided to the OR circuit  14  slightly delayed from the control signal A. The OR circuit  14  provides an output signal B to the GCB as a control signal.  
         [0063]     Referring to  FIG. 10 , in the clock tree network  900  of the sixth embodiment, when the control signal A rises from an L level to an H level, the output signal B of the OR circuit  14  immediately rises in response to the rising of the control signal A. This inactivates the GCB and stops the output of the clock signal CLK. If the control signal A falls from the H level to the L level, the output signal B of the OR circuit  14  falls to an L level when the output signal B and the control signals A, A 1 , and A 2  have all fallen to an L level. Accordingly, the transistors Tr 3   a  to Tr 3   d  and Tr 4   a  to Tr 4   d  are all activated, and the buffer circuit group  11   a  is activated. Then, the GCB provides the clock signal CLK to the buffer circuit group  11   a.    
         [0064]     The clock tree network  900  functions to stabilize the clock signal CLK provided from the buffer circuit group  11   a  to the flip-flop circuits FF. If the clock signal CLK is provided before the buffer circuit group  11   a  is completely activated, the propagation time of the clock signal CLK in the buffer circuit group  11   a  would become unstable. In such a case, the clock tree network  900  would become out of synchronization with other clock tree networks. The clock tree network  900  of the sixth embodiment is configured to eliminate such a deficiency.  
         [0065]      FIG. 11  is a schematic circuit diagram showing a clock tree network  1000  provided with a power consumption reduction function according to a seventh embodiment of the present invention. The clock tree network  1000  includes a buffer circuit group  11   b , which has a configuration similar to that of the clock tree network  900  in the sixth embodiment, and buffer circuit groups  11   c  to  11   e , which receive the clock signal CLK from the same GCB as the buffer circuit group  11   b.    
         [0066]     For each of the buffer circuit groups  11   b  to  11   e  provided with the clock signal CLK from the same GCB, the control signal A of the GCB is provided through a single line L 3  to the gate of the transistor functioning as the switch circuit for supplying high potential power. The terminal end of the line L 3  is connected to a first input terminal of an OR circuit  14 .  
         [0067]     Further, the gate of the transistor functioning as the switch circuit for supplying low potential power in each of the buffer circuit groups  11   b  to  11   e  is provided with the inverted signal of the control signal A through a line (not shown). The terminal end of the line is connected to a second input terminal of the OR circuit  14 .  
         [0068]     Accordingly, with regard to the buffer circuit groups  11   b  to  11   e  in the clock tree network provided with the clock signal CLK from the same GCB, the clock tree network  1000  of the seventh embodiment has the same advantages as the clock tree network  900  of the sixth embodiment.  
         [0069]      FIG. 12  is a schematic circuit diagram showing a clock tree network  1100  provided with a power consumption reduction function according to an eighth embodiment of the present invention. The clock tree network  1100  is configured by adding to the clock tree network  1000  of the seventh embodiment a branch line for each of the buffer circuit groups  11   b  to  11   e  to provide the control signal A.  
         [0070]     More specifically, the gates of the transistors (switch circuits), connected between the high potential power supply and the buffer circuit groups  11   b  to  11   e  receiving the clock signal CLK from the same GCB, receive the control signal A of the GCB through a corresponding one of branch lines L 4  to L 7 . The terminal ends of the branch lines L 4  to L 7  are connected to input terminals of an OR circuit  15 . The OR circuit  15  provides an output signal to the OR circuit  14  as a control signal A 1 .  
         [0071]     Further, the gates of the transistors (switch circuits) supplying the buffer circuit groups  11   b  to  11   e  with low potential power receive the inverted signal of the control signal A through a corresponding clock tree branch line (not shown). The terminal ends of each of the branch lines are connected to input terminals of an OR circuit (not shown). This OR circuit provides an output signal to the OR circuit  14  as a control signal A 2 .  
         [0072]     Accordingly, with regard to the buffer circuit groups  11   b  to  11   e  in the clock tree network provided with the clock signal CLK from the same GCB, the clock tree network  1100  of the eighth embodiment has the same advantages as the clock tree network  900  of the sixth embodiment.  
         [0073]     Further, the OR circuit  15 , which is provided with the control signal A from the branch lines L 4  to L 7  of the clock tree, determines the voltage level of each of the branch lines L 4  to L 7  and provides the control signal A 1  to the OR circuit  14 . This shortens the length of the wire for providing the buffer circuit groups  11   b  to  11   e  with a control signal. Further, the OR circuit  15  functions as a buffer for the control signal A 1 .  
         [0074]     Accordingly, in comparison with the clock tree network  1000  of the seventh embodiment, the propagation speeds of the control signals A 1  and A 2  are increased. Further, the time from when the control signal A falls to when the GCB is activated is shortened.  
         [0075]     It should be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention. Particularly, it should be understood that the present invention may be embodied in the following forms.  
         [0076]     The transmission control circuit may be a circuit other than a GCB.  
         [0077]     The present examples and embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalence of the appended claims.