Abstract:
An improved voltage reference circuit relies on electrically adjustable analog devices fabricated on a common substrate. The circuit has two electrically adjustable matched transistor pairs. A first matched transistor pair includes an adjusting transistor and a differential pair transistor. A second matched transistor pair also includes an adjusting transistor and a differential pair transistor. Each of the matched transistor pairs share an insulated gate or electrically connected insulated gates. Geometrical and electrical matching occurs as between the two adjusting transistors and between the two differential pair transistors. The two differential pair transistors are electrically connected at the source terminals to form a differential circuit. A feedback loop, which includes an amplifier, a fixed resistor and a current source complete the circuit.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to semiconductor integrated circuit devices. More specifically, this invention relates to an integrated voltage reference circuit. 
     2. Description of the Related Art 
     Many analog circuit applications require the presence of a voltage reference function. One prior art approach to fulfill the voltage reference function is the employment of zener diodes, typically buried zener diodes. Other prior art voltage reference techniques, such as bandgap voltage reference circuits rely on bipolar transistor device. The disadvantages of these prior art solutions is that the process requirements for fabrication are typically inconsistent with integrated circuits that are fabricated using CMOS technology. 
     Therefore, a need exists to provide an integrated voltage reference circuit using conventional CMOS fabrication processes. Performance and flexibility would be enhanced by having the CMOS reference voltage circuit electrically adjustable to suit the requirements of various applications. 
     BRIEF SUMMARY 
     It is an object of this invention to provide an integrated voltage reference circuit using conventional CMOS technology and fabrication methods. 
     It is another object of this invention to provide an integrated voltage reference circuit that is electrically adjustable. 
     An improved voltage reference circuit is comprised of electrically adjustable analog devices fabricated on a common substrate. The circuit comprises two electrically adjustable matched transistor pairs. A first matched transistor pair comprises an adjusting transistor and a differential pair transistor. A second matched transistor pair also comprises an adjusting transistor and a differential pair transistor. Each of the matched transistor pairs share an insulated gate or electrically connected insulated gates. Geometrical and electrical matching occurs as between the two adjusting transistors and the two differential pair transistors. The two differential pair transistors are electrically connected at the source terminals to form a differential circuit. A feedback loop is comprised of an amplifier, a fixed resistor and a current source or load. 
    
    
     The foregoing and other objects, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiments of the invention, as illustrated in the accompanying drawing. 
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
     The FIGURE is a schematic diagram of one embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     Referring to the FIGURE, one embodiment of the present invention is illustrated. The electrically adjustable integrated voltage reference circuit (circuit)  100  is comprised of a differential pair transistors, i.e. differential pair transistor  110  and differential pair transistor  111 . These differential pair transistors are typically Metal Oxide Semiconductor (MOS) or Complementary Metal Oxide Semiconductor (CMOS) devices which share a common substrate. The geometries of differential pair transistor  110  and differential pair transistor  111  are purposefully matched by design, i.e. length and width, such that they share common electrical characteristics in response to external parameters such as temperature variation. 
     The drain terminal of differential pair transistor  110  is electrically connected to an independent current load  120 , which produces drain current I D1  through differential pair transistor  110 . The drain terminal of differential pair transistor  111  is electrically connected to a second independent current load  121 , which produces drain current I D2  through differential pair transistor  111 . The loads  120  and  121 , which are matched in geometry and electrical characteristics, are connected to a supply voltage V + . 
     The source terminal of differential pair transistor  110  is electrically connected to the source terminal of differential pair transistor  111  and to a current source  115 . Thus, the combined electrical current through the current source  115  is I D1 +I D2 . 
     The circuit  100  is further comprised of adjusting transistor  130  and adjusting transistor  131 . These adjusting transistors  130  and  131  are typically MOS or CMOS devices which share a common substrate with the differential pair transistors  110  and  111 . The geometries of adjusting transistor  130  and transistor  131  are purposefully matched by design, i.e. length and width, such that they share common electrical characteristics in response to external parameters such as temperature variation. 
     In one embodiment, the electrical characteristics of the adjusting transistors  130  and  131  are not matched to the electrical characteristics of the differential pair transistors  110  and  111 . However, in alternate embodiments, when the electrical characteristics of the adjusting transistors  130  and  131  are matched to the electrical characteristics of the differential pair transistors  110  and  111 , respectively, the adjusting transistors  130  and  131  no longer serve an independent function and the circuit may be reduced, from a transistor perspective, to the differential pair transistors  110  and  111 . 
     The gate terminal of adjusting transistor  130  is electrically connected to the gate terminal of the differential pair transistor  110 . Differential pair transistor  110  shares a common floating or insulated gate with adjusting transistor  130 . The drain terminal of adjusting transistor  130  is connected to charge injection input P 1  and the source terminal is connected to ground potential. 
     The gate terminal of adjusting transistor  131  is electrically connected to the gate terminal of the differential pair transistor  111 . Differential pair transistor  111  shares a common floating or insulated gate with adjusting transistor  131 . The drain terminal of adjusting transistor  131  is connected to charge injection input P 2  and the source terminal is connected to ground potential. 
     A feedback loop connects the drain terminals of the differential pair transistors  110  and  111  with the gate terminals of the differential pair transistors  110  and  111  and the gate terminals of the adjusting transistors  130  and  131 . The drain terminal of differential pair transistor  110  is electrically connected to an input terminal of amplifier  140 . The drain terminal of differential pair transistor  111  is electrically connected to another input terminal of amplifier  140 . 
     The output of amplifier  140  is electrically connected to the gate terminal of differential pair transistor  111 , to the gate terminal of adjusting transistor  131  and to one terminal of resistor  150 . The other terminal of resistor  150  is connected to the gate terminal of differential pair transistor  110  and to the gate terminal of adjusting transistor  130 . The resistor  150  is also connected to a bias current source or load  160 , which is connected to ground potential. The output of the circuit  100 , V REF , is the differential as between V 2  and V 1 , as indicated by the output nodes, or V REF =V 2 −V 1 . 
     The amplifier  140 , sensing the drain currents I D1  and I D2 , amplifies any difference as between the drain voltages of differential pair transistors  110  and  111 . In the equilibrium state, the I D1  is equal to I D2  and the output of the amplifier is different from I D2 , the amplifier produces a bias current I R . Bias current I R  propagates through the resistor  150  and through the bias current source  160 . The voltage drop across resistor  150 , resulting from the bias current I R , produces the differential as between V 2  and V 1 . 
     When the differential pair transistors  110  and  111  and the adjusting transistors  130  and  131  are initially powered up, the two differential pair transistors  110  and  111 , each having equal electrical characteristics, will develop a gate voltage requirement to maintain drain currents such that I D1  is equal to I D2 . Thus, the gate voltages V 1  and V 2  are equal to each other, and V REF  is equal to zero. 
     To create a non-zero V REF , a different amount of charge is injected on to one or both of the insulated gates of adjusting transistors  130  and  131 . Charge injection is accomplished for adjusting transistor  130  via charge injection input P 1 , through the drain terminal and on to the insulated gate. Similarly, charge injection is accomplished for adjusting transistor  131  via charge injection input P 2 , through the drain terminal of adjusting transistor  131  and on to the insulated gate. 
     Since the insulated gate of adjusting transistor  130  is electrically connected to the insulated gate of differential pair transistor  110  and the insulated gate of adjusting transistor  131  is electrically connected to the insulated gate of differential pair transistor  111 , the insulated gate voltage potential of each of the adjusting transistors is equal to the insulated gate potential of the associated differential pair transistor following charge injection. Alternatively, the adjusting transistor and the associated differential pair transistor may be seen as sharing a common insulated gate as opposed to separate gate structures which are electrically connected. Once the respective charges are injected into the circuit  100 , the drains of the adjusting transistors  130  and  131  are open and the adjusting transistors  130  and  131  are no longer active. 
     In the case where different amounts of charge are injected into the adjusting transistors  130  and  131 , the differential pair transistors  110  and  111  will each develop a different gate voltage requirement in order to maintain their initial drain currents, respectively. The new gate voltage requirement is dependent upon the amount of charge injected on to the insulated gates of each of the devices. The voltage differences on the insulated gates of differential pair transistors  110  and  111  result in a current differential as between I D1  and I 1D . 
     This current differential and the resulting drain voltage differential is now inputted into amplifier  140  which produces bias current I R . When bias current I R  propagates through the fixed resistor  150 , there results in a voltage potential as between V 2  and V 1 . The circuit  100  shall maintain a gate overdrive voltage V V  on differential pair transistor  110  and a separate gate overdrive voltage V 2  on differential pair transistor  111  until such time as I D1  is equal to I D2 . When I D1  once again equal I D2 , the bias current I R  reaches a level to maintain a voltage equilibrium potential as between V 2  and V 1 , through the fixed resistor  150 . 
     V REF  is a function of the difference in the amount of charge stored on the insulated gates of the respective device matched pairs, i.e. matched pair  1 : adjusting transistor  130  and differential pair transistor  110 , and matched pair  2 : adjusting transistor  131  and differential pair transistor  111 . 
     The amount of charge stored within each of the two matched pairs is independent of temperature. The resultant overdrive voltages V 1  and V 2  depend on the electrical and geometric characteristics of differential pair transistors  110  and  111 . In the preferred embodiment, because the differential pair transistors  110  and  111  are matched, i.e. having nearly identical geometric and electrical characteristics, the effect of temperature variation on the performance of each of the differential pair transistors  110  and  111  are similarly matched. That is, the effect of temperature variation on differential pair transistor  110  cancels the effect of temperature variation on differential pair transistor  111 . Thus, the differential effect of temperature variation is zero. 
     In alternate embodiments, the differential pair transistors  110  and  111  and the adjusting transistors  130  and  131  may be proportional to each other, as opposed to match pairs. This will yield an equilibrium state where I D1  is proportional, rather than equal, to I D2 . The proportionality as between I D1  and I D2  may be compensated for in the amplifier  140  to produce a equilibrium state where V REF  is equal to zero. 
     Although the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the spirit and scope of the invention.