Abstract:
A hot carrier lifetime of a MOS transistor is estimated, depending on model formulas: 1/τ=1/τ 0+1/τ   b ; τ b   ∝1   sub   −mb ·I d   mb−2 ·exp(a/|V bs |), where τ denotes a lifetime, I sub  denotes a substrate current, I d  denotes a drain current, V bs  denotes a substrate voltage, τ 0  denotes a lifetime at the time the substrate voltage V bs =0, τ b  denotes a quantity representing deterioration of a lifetime at the time the substrate voltage |V bs &gt;0, and mb and ‘a’ are model parameters. Furthermore, a parameter Age representing a cumulative stress quantity is calculated depending on model formulas: Age=Age 0 +Age b ; Age b =∫1/H b [I sub   mb ·I d   2−m ]·exp(−a/|V bs |)dt, where t denotes time, H b  is a model parameter, Age 0  denotes a parameter representing a cumulative stress quantity at the time the substrate voltage V bs =0, and Age bs  denotes a quantity representing an increase of the cumulative stress quantity at the time the substrate voltage at |V bs |&gt;0. Thereby, a lifetime in actual use is determined with accuracy even when a substrate voltage is applied, and circuit characteristic degradation is simulated with high accuracy.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a method of estimating a lifetime concerning hot carrier degradation of a MOS transistor. More specifically, it relates to improvement of accuracy in lifetime estimation in a case of applying a substrate voltage. The present invention also relates to a method of simulating circuit characteristic degradation caused by hot carrier degradation of a MOS transistor. More specifically, it relates to improvement of simulation in a case of applying a substrate voltage.  
         BACKGROUND OF THE INVENTION  
         [0002]    The size of MOS transistors has been reduced considerably with a trend toward high density, high integration and miniaturization of semiconductor integrated circuit devices. With the miniaturization trend, especially due to the decreasing channel length, hot carrier degradation has been a critical problem, since the degradation will affect the reliability of a MOS transistor. Hot carrier degradation refers to a phenomenon in which highly energized electrons and positive holes (hereinafter ‘hot carrier’) are generated by a high electric field at a drain end of a MOS transistor, which will degrade the characteristics of a gate oxide film. This hot carrier degradation includes plural degradation modes. In degradation under a condition to cause a maximum substrate current or degradation under a condition that the gate voltage V gs  is a half the drain voltage V ds , a drain current is decreased over time for both N-type and P-type MOS transistors. As a result, the delay time of the circuit is increased over time. When the delay reaches a certain degree, a timing error occurs at a time of input/output of signals within the semiconductor integral circuit or between the circuit and outside, and this causes a malfunction of an entire system in which the semiconductor integrated circuit is assembled.  
           [0003]    Regarding the hot carrier degradation, hot carrier reliability has been evaluated by a stress acceleration experiment under a DC (direct current) condition with respect to the MOS transistor. Product reliability has been provided by optimizing a production process to satisfy the hot carrier evaluation standard.  
           [0004]    A hot carrier lifetime model used in such a hot carrier reliability evaluation is as follows. Hot carrier degradation of a MOS transistor is evaluated by, for example, ΔI d /I d , and this is a ratio of a drain current variation ΔI d  to an initial drain current I d . Under a static hot carrier stress condition by a DC, the hot carrier degradation rate ΔI d /I d  is represented by the following formula (1).  
             ΔI   d   /I   d   =A·t   n    (1)  
           [0005]    Here, ‘t’ denotes a hot carrier stress time, while characters ‘A’ and ‘n’ are regarded as coefficients depending on a transistor manufacturing process and a stress condition.  
           [0006]    If a transistor lifetime τ is defined as a stress time required for a variation rate of drain current to reach (ΔI d /I d ) f , a formula (2) is obtained from the formula (1). For example, time t when (ΔI d /I d ) f =10% is defined as a lifetime τ.  
           ( ΔI   d   /I   d ) f   =A·τ   n    (2)  
           [0007]    In a typical stress acceleration experiment for a MOS transistor, DC stress is applied to a transistor so that the transistor lifetime reaches a variation rate (ΔI d /I d ) f  defined by the formula (2) within a measureable time period, that is, from 1 second to about 100,000 seconds. Then, a drain current of the transistor is measured to calculate a transistor lifetime from ΔI d /I d  in a linear region or a saturation region.  
           [0008]    The following stress voltage application method is used in a stress acceleration experiment during a hot carrier reliability evaluation. Every gate voltage V g  is determined under a condition where the hot carrier degradation rate is maximized with respect to each of plural drain voltages V d  used for the acceleration experiment. In other words, each of the gate voltages V g  causes a maximum substrate current I sub  under a respective drain current. At this time, one gate voltage is set for each drain voltage. In this way, a transistor lifetime is calculated under a condition in which the degradation rate is maximized with respect to an arbitrary drain voltage.  
           [0009]    A method of evaluating hot carrier reliability of a MOS transistor is described in IEEE Electron Device Lett., vol. 4, pp. 111-113, April 1983 by E. Tanaka et al. According to the description, the lifetime τ of a MOS transistor is calculated by using an empirical model represented by the following formula (3).  
           τ∝exp(−C/V ds )   (3)  
           [0010]    In this formula, V ds  denotes a voltage between a drain and a source, and C denotes a fitting parameter.  
           [0011]    Furthermore, a method of evaluating hot carrier reliability of a MOS transistor for a case in which a substrate voltage V bs  is applied is described, for example, in Proc. IEEE VLSI Tchnol. Symp., pp. 119-120, 2001 by E. Murakami et al. According to the description, the lifetime τ of a MOS transistor is determined by using an empirical model represented by the following formula (4).  
           τ∝exp(−C(1/V ds +1/V db ))   (4)  
           [0012]    [0012]FIG. 5 shows a method of estimating a lifetime based on this empirical model. In FIG. 5, each of the elements  21  denotes a measured value of the lifetime under a condition to cause a maximum substrate current or under a condition that a gate voltage V gs =V ds /2, and a line  22  denotes a regression line of lifetime estimation. Numeral  23  denotes a value of 1/V ds +1/V db  in actual use, and  24  denotes an estimated lifetime in actual use. For a lifetime estimation, 1/V ds +1/V db  is used to enter a horizontal axis of a graph, and a logarithm of τ is used to enter the vertical axis so that the measured values  21  for a lifetime are plotted. Next, the regression line  22  is fitted to the measured values  21  by using a least squares method. The regression line  22  is used to obtain a lifetime corresponding to the 1/V ds +V db  in actual use, and this is determined as an estimated lifetime  24  in actual use. Hot carrier reliability evaluation is executed by observing whether the lifetime  24  satisfies a hot carrier evaluation standard, e.g., whether the lifetime  24  satisfies a standard of at least 10 years.  
           [0013]    Recently however, such a conventional hot carrier evaluation standard has been difficult to satisfy in the hot carrier reliability evaluation under the DC condition. For solving this problem, a recently developed technique provides product reliability by a simulation of hot carrier degradation for a semiconductor integrated circuit (hereinafter “circuit reliability simulation”). Acircuit reliability simulator simulates a circuit operation subsequent to hot carrier degradation by using a hot carrier lifetime model and a SPICE parameter after degradation, and the simulation is based on calculated values of voltage and current at every terminal of every transistor, which are calculated by a circuit simulator SPICE. Typical simulators are BERT developed at the University of California, Berkeley (R. H. Tu et al., “Berkeley reliability tools-BERT,” IEEE Trans. Compt.-Aided Des. Integrated Circuits &amp; Syst., vol. 12, no. 10, pp. 1524-1534, October 1993), and BTABERT (a commercial version of BERT). This circuit reliability simulation technique is used for estimating degraded or malfunctioning parts in a semiconductor integrated circuit and measures against the degradation or malfunction are taken during designing, so that reliability assurance or reliability design is possible.  
           [0014]    An example of simulation methods concerning hot carrier degradation of a MOS transistor is described in IEEE Trans. Electron Devices, vol. 35, pp. 1004-1011, July 1988 by Kuo et al. A hot carrier lifetime model applied to this circuit reliability simulator is as follows. According to Kuo et al., a lifetime τ of a MOS transistor is represented by an empirical formula (5) using a hot carrier lifetime model.  
           τ=((Δ I   d   /I   d ) f ) 1/n   ·H·W·I   sub   −m   ·I   d   m−1    (5)  
           [0015]    In the formula, W denotes a gate width, H denotes a coefficient depending on a condition for manufacturing a transistor, I sub  denotes a substrate current, and m denotes an index relating to an impact ionization and interface level formation.  
           [0016]    A coefficient A in a hot carrier lifetime model is represented by a formula (6) that is derived from the formulas (2) and (5).  
             A= (( W·H ) 31 1   ·I   sub   m   ·I   d   1−m ) n    (6)  
           [0017]    Therefore, a formula (7) is derived from the formulas (1) and (6).  
           Δ I   d   /I   d =(( W·H ) −1   ·I   sub   m   ·I   d   1−m   ·t ) n    (7)  
           [0018]    When Age is defined for convenience as in the following formula (8), the formula (7) can be rewritten into a formula (9).  
           Age=( W·H ) −1   I   sub   m   ·I   d   1−m   ·t    (8)  
           Δ I   d   /I   d =(Age) n    (9)  
           [0019]    In the formula (8), ‘Age’ represents a stress quantity from a start of hot carrier stress to a time t in a hot carrier lifetime model. From a physical point of view, it represents a total quantity of hot carrier having an energy of at least a critical energy to generate damage in a MOS transistor.  
           [0020]    The parameters n, H and m used in the formulas (4)-(9) are regarded as hot carrier lifetime parameters. These hot carrier lifetime parameters are functions of vertical electric field strength at a drain end where the hot carrier is generated. Therefore, these parameters are represented as functions of a gate-drain voltage V gd .  
           [0021]    [0021]FIG. 7 shows a method of simulating characteristics after degradation by using a ΔI d  model. A simulation method using a ΔI d  model is described in IEEE Trans. Electron Devices, vol. 40, pp. 2245-2254, December 1993 by Quader et al.  
           [0022]    FIGS.  6 (A) and  6 (B) are equivalent circuit diagrams showing a method of simulating hot carrier degradation of a MOS transistor. In FIGS.  6 (A) and  6 (B),  25   a  denotes a fresh MOS transistor before stress application,  25   b  denotes a MOS transistor after stress application, and  26  denotes a variable current source. FIG. 6(A) shows a drain current I d  flowing in a fresh MOS transistor  25   a  before stress application. FIG. 6(B) shows a drain current I d ′ flowing in a MOS transistor  25   b  after hot carrier degradation. It is shown that the drain current flowing in the transistor changes from the initial drain current I d  by ΔI d  due to the hot carrier degradation.  
           [0023]    As shown in the following formula (10), a drain current I d ′ after degradation is simulated by adding degradation ΔI d  of a drain current to a fresh drain current I d  before stress application.  
             I   d   ′=I   d ( V   d   , V   g )+Δ I   d (Age,  V   d   , V   g )   (10)  
           [0024]    ΔI d  is a function of Age as stress quantity from the start of hot carrier stress to a time t, as well as a function of a drain voltage V d  and a gate voltage V g . For calculating Age under a dynamic stress condition by AC (alternating current) in a circuit, the formula (8) is rewritten into the following formula (11) as an integral form over time for calculation.  
           Age=∫[( W·H ) −1   I   sub   m   ·I   d   1−m   ]dt    (11)  
           [0025]    In this simulation, ΔI d  is represented by an equivalent circuit prepared by adding a variable current source  26  shown in FIG. 6(B) to a source-drain of an initial MOS transistor. At this time, a transistor parameter to calculate the initial drain current is not changed.  
           [0026]    [0026]FIG. 7 is a flow chart to show a process to simulate hot carrier degradation of a MOS transistor according to a conventional technique. In this flow chart, a step S 01  includes sub-steps S 01   a -S 01   g  to extract an unknown parameter in the formulas (10) and (11) with respect to a hot carrier lifetime model by a preliminary measuring experiment.  
           [0027]    In the sub-step S 01   a,  a model formula I sub =g(V g , V d ) is determined to fit to measurement data of plural substrate currents I sub  in a preliminary measuring experiment, so that the substrate current I sub  in the formula (11) is determined. Here, V g  denotes a gate voltage, and V d  denotes a drain voltage. An example of a method for determining a substrate current I sub  is described in IEEE Electron Device Lett., vol. EDL-5, pp. 505-507, December 1984 by Chan et al.  
           [0028]    The sub-steps S 01   b -S 01   d  are for extracting hot carrier lifetime parameters in a preliminary measuring experiment. In the sub-step S 01   b,  a stress voltage is applied to a MOS transistor, and a hot carrier lifetime defined by the formula (2) is measured. For applying the stress voltage, a gate voltage V g  is set so that a gate-drain voltage V gd =V g −V d  is constant with respect to plural drain voltages V d . In this method, typically plural numbers of V gd  are set, and also gate voltages V g =V d +V gd  corresponding to the plural V gd  are set with respect to every drain voltage V d . In the following sub-step S 01   c,  coefficient n is extracted as a function of V gd  by a comparison between the empirical formula (1) and data concerning measurement points in a DC stress experiment for the sub-step S 01   b.  Similarly in the sub-step S 01   d,  an index m and a coefficient H are extracted as functions of V gd  by a comparison between the empirical formula (5) and data concerning measuring points in a DC stress experiment for the sub-step S 01   b.    
           [0029]    Sub-steps S 01   e -S 01   g  are for determining a fresh drain current I d  before stress application and degradation ΔI d  of the drain current in the formula (10) for a ΔI d  model. In the sub-step S 01   e,  transistor parameters such as carrier mobility and a flat-band voltage are extracted. Such parameters are used for determining fresh drain current I d (V d , V g ) before stress application. BSIM (Berkeley Short-Channel IGFET Model) is used for a model to determine such a fresh drain current I d (V d , V g ). The BSIM is described in detail in IEEE J. Solid-State Circuits, vol. SC-22, pp. 558-566, August 1987 by Sheu et al. Subsequently in the sub-step S 01   f,  DC stress is applied to the transistor. In the sub-step S 01   g,  ΔI d  model parameters are extracted before and after the DC stress application. The drain current degradation ΔI d (Age, V d , V g ) is determined by the ΔI d  model parameters. The ΔI d  model is described by Quader et al. in relation to NMOS. PMOS is described in JP-A-08-64814 by Shimizu et al.  
           [0030]    The transistor parameters should be extracted before DC stress application so that actual transistor characteristics before the stress application coincide with simulated transistor characteristics. The ΔI d  model parameters should be extracted before and after the DC stress application so that the actual drain current degradation ΔI d  before and after the stress application coincides with the simulated drain current degradation ΔI d .  
           [0031]    The step S 02  includes sub-steps S 02   a -S 02   d  so that a reliability simulator simulates hot carrier degradation of a transistor in accordance with parameters extracted in the step S 01  and also with the formulas (10) and (11).  
           [0032]    In the sub-step S 02   a,  a drain current is simulated by transistor parameters before stress application, where the parameters have been extracted in the prior sub-step S 01   e.  In the sub-step S 02   b,  a substrate current is simulated on the basis of a substrate current model formula I sub =g(V g , V d ) determined by the S 01   a . In the sub-step S 02   c,  Age, which represents degradation of each transistor based on the formula (11), is calculated by time-integrating functions of a drain current I d  and a substrate current I sub  in a circuit. At this time, the drain current I d  simulated in the sub-step S 02   a,  the substrate current I sub  simulated in the sub-step S 02   b,  and hot carrier lifetime parameters H and m calculated in the sub-step S 01   d,  are used. In the sub-step S 02   d,  hot carrier degradation of the transistor is simulated by using the formula (10) on the basis of the Age.  
           [0033]    The following is a detailed explanation of a method of extracting hot carrier lifetime parameters H and m for a hot carrier lifetime model. FIG. 8 is an explanatory view of a method of extracting hot carrier lifetime parameters H and m. FIG. 8 relates to a plot for calculating hot carrier lifetime parameters H and m included in the empirical formula (5) using a hot carrier lifetime model. In FIG. 8, the vertical axis is a logarithmic scale of a value τ·I d /W calculated from a lifetime τ in a DC stress experiment, a drain current I d  during a stress and a gate width W of a MOS transistor. The horizontal axis is a logarithmic scale of a ratio I sub /I d  when I sub  is a substrate current during a stress and I d  is a drain current. Numeral  27  denotes data concerning a plurality of measurement points in a DC stress experiment, and  28  denotes a line fitted with respect to data concerning the measurement points. The MOS transistor lifetime τ is measured under plural gate-drain voltage V gd  conditions, e.g., under three conditions of V gd =0.0, −1.0, and −2.0 V, so that data  27  for plural measurement points are obtained. A line  28 , fitted by a least squares method with respect to data  27  concerning the measurement points, is obtained. Hot carrier parameters H and m are obtained respectively from an intercept and a gradient of the line  28 . By executing this method for plural V gd , the hot carrier lifetime parameters H and m in a hot carrier lifetime model can be calculated as functions of V gd .  
           [0034]    The above description is about a conventional method of estimating a lifetime of hot carrier degradation of a MOS transistor, and a conventional method of simulating degradation in circuit characteristics caused by the hot carrier degradation. However, these methods can cause the following problems.  
           [0035]    First, in the method of estimating a lifetime of hot carrier degradation of a MOS transistor, the model formula (4) adopting an effect of a substrate voltage lacks explicit physical grounds, and the repeatability will not be assured. Secondly, since a lifetime is represented as a function of a drain voltage and a substrate voltage, the lifetime cannot be predicted accurately with respect to an arbitrary gate voltage.  
           [0036]    A third problem is that a lifetime under a condition in which a hot carrier degradation rate is maximized will be estimated as longer than its actual lifetime. Therefore, depending on use conditions, the lifetime in actual use of the MOS transistor may be shorter than the lifetime estimated corresponding to this model. That is, the quality of the product cannot be assured appropriately.  
           [0037]    Regarding the method of simulating circuit characteristic degradation caused by the hot carrier degradation, the effect of the substrate voltage with respect to the hot carrier degradation is not included in the conventional hot carrier lifetime model represented by the formula (5). According to the formula (4), the lifetime will be shortened in comparison with the conventional hot carrier lifetime model formula (5) when a substrate voltage is applied. Therefore, in a case of applying a substrate voltage, the lifetime in actual use will be shorter than the simulation result obtained by using the conventional model formula (5). However, as described above, the model formula (4) cannot be used for the simulation of the circuit characteristic degradation, due to a lack of repeatability based on physical grounds and gate voltage dependency.  
           [0038]    The conventional model formula (5) is based on a hypothesis that hot carrier degradation occurs due to one kind of hot carrier, that is electrons or holes, having an energy of not lower than the critical energy required for causing damage on the MOS transistor, and that the hot carrier lifetime is inversely proportional to the yield of this one kind of hot carrier. According to this model, it is difficult to provide a hot carrier lifetime model adopting a physical effect with respect to the hot carrier degradation in the substrate voltage.  
         SUMMARY OF THE INVENTION  
         [0039]    In order to solve the above-identified problems, the present invention provides a method of estimating a lifetime of hot carrier degradation of a MOS transistor, so that the lifetime is determined with accuracy by adopting an effect of a substrate voltage based on physical grounds with respect to a hot carrier lifetime and also by providing a hot carrier lifetime model for representing a gate voltage dependency with accuracy, and thus providing assurance for a product.  
           [0040]    In the method of simulating circuit characteristic degradation caused by the hot carrier degradation, the present invention provides a model formula, based on physical grounds, including an effect of a substrate voltage with respect to hot carrier degradation, realizing a highly accurate simulation even for a case of applying a substrate voltage in order to provide product reliability at a time of designing and to provide high transistor performance.  
           [0041]    For achieving the above-described objects, in a method of estimating a hot carrier lifetime of a MOS transistor according to the present invention, estimation is conducted, based on a hot carrier lifetime model expressed by the following formulas.  
           1/τ=1/τ 0 +1/τ b    
           τ b ∝1 sub   −mb   I   d   mb−2   ·exp ( a/|V   bs |)  
           [0042]    In the formulas, τ denotes a lifetime, I sub  denotes a substrate current, I d  denotes a drain current, V bs  denotes a substrate voltage, τ 0  denotes a lifetime at the time V bs =0, τ b  denotes a deterioration of lifetime at the time the substrate voltage |V bs |&gt;0, and both mb and ‘a’ are model parameters.  
           [0043]    This hot carrier lifetime model is based on a theory that hot carrier degradation occurs due to re-bonding of two kinds of hot carriers, i.e., electrons and holes having an energy not lower than the critical energy required for causing damage on the MOS transistor, and that the hot carrier lifetime is inversely proportional to a yield of the two kinds of hot carriers. For this model, model formulas representing the hot carrier lifetime τ can be shown as the following formulas (12), (13), and (14) replacing the conventional formula (4) or (5), where the model parameters are m0, H 0 , mb and H b .  
           1/τ=1/τ 0 +1/τ b    (12)  
           τ 0 =((Δ I   d   /I   d ) f ) 1/n   ·H   0   W·I   sub   −m0     19  I   d   m0−2    (13)  
           τ b =((Δ I   d   /I   d ) f ) 1/n   ·H   d   ·W   2   ·I   sub   −mb   ·I   d   mb−2   ·exp ( a/|V   bs |)   (14)  
             mb= ((Φ h /λ h )/(Φ ei /λ e )+2  
           [0044]    Here, τ 0  denotes a lifetime at the time the substrate voltage V bs =0, and τ b  denotes a quantity representing deterioration of the lifetime at the time the substrate voltage |V bs |&gt;0, which represents degradation caused by re-bonding among the primary hot carriers. Φ h  denotes a critical energy of holes to generate damage, Φ ei  denotes an impact ionization energy of electrons, and λ h  and λ e  denote respectively mean free paths of holes and electrons.  
           [0045]    The model formula (13) is distinguished from the conventional model formula (5) in that the formula (13) adopts a functional form of (exponent of I d )=−(exponent of I sub )−2, while the conventional formula adopts (exponent of I d )=−(exponent of I sub )−1. The difference is caused by the fact that a hot carrier lifetime is inversely proportional to a yield of one kind of hot carrier in a conventional technique, while the same lifetime is inversely proportional to a yield of two kinds of hot carriers in the present invention.  
           [0046]    It was confirmed by a comparison with measured values of N-type and P-type MOS transistors that a model of the present invention corresponds well to a measured value, and V gd  dependence of the hot carrier lifetime parameters H 0  and m0 is decreased considerably.  
           [0047]    The model formula (14) represents the deterioration of the lifetime at the time the substrate voltage |V bs |&gt;0. This formula represents hot carrier degradation caused by re-bonding between a secondary hot carrier occurring due to application of the substrate voltage and the primary hot carrier.  
           [0048]    Though the model parameters H 0  and H b  correspond to measured values well even if they are regarded as constants, the parameters actually have a weak dependency on V gd , since the depth of a current path at the edges in a MOS transistor varies depending on V gd . The depth of the current path has a weak dependency on V gd .  
           [0049]    According to a lucky electron model (C. Hu et al., IEEE Trans. Electron Devices, vol. 23, pp. 375-385, February 1985), the quantity of the hot carrier is decreased exponentially with respect to the distance. Therefore, the effects have an exponential dependency on the V gd . As a result, H 0  and H b  are represented by the following formulas (15) and (16).  
           H 0 ∝exp(H 0 ·|V bd |)   (15)  
           H b ∝exp(H b ·|V bd |)   (16)  
           [0050]    In general, sufficient accuracy can be realized for H 0  and H b  even when they are regarded as constants.  
           [0051]    For estimating a lifetime of hot carrier degradation according to the present invention, hot carrier lifetime parameters n, H 0 , m0, Hb, mb and ‘a’ in the formulas (12), (13) and (14) are determined as constants on the basis of values measured in a stress acceleration experiment. From these parameters and the formulas (12) and (13), a hot carrier lifetime in actual use is determined on the basis of measured values of the substrate current I sub  and the drain current I s  in actual use, which is determined as an estimated lifetime in actual use.  
           [0052]    In the simulation of hot carrier degradation of the MOS transistor according to the present invention, a parameter Age representing cumulative stress quantity with respect to the MOS transistor is calculated by a model formula expressed below.  
           Age=Age 0 Age+Age b    
           Age b =∫1/ H   b   [I   sub   mb   ·I   d   2−m   ]·exp (− a/|V   bs |) dt    
           [0053]    Here, t denotes time, I sub  denotes a substrate current, I d  denotes a drain current, V bs  denotes a substrate voltage, H b , mb and a are model parameters, Age 0  denotes a parameter representing a cumulative stress quantity with respect to a MOS transistor at the time the substrate voltage V bs =0, Age bs  denotes a quantity representing an increase in a cumulative stress quantity with respect to the MOS transistor at the time the substrate voltage |V bs &gt;0.  
           [0054]    For example, in a method of simulating circuit characteristic degradation caused by hot carrier degradation of a MOS transistor, the formula (11) is replaced by the following formula (17) as an integral over time.  
           Age=Age 0 +Age  b    (17)  
           Age 0 =∫1/ H   0 ·( I   d   /W)   2 ( I   sub   /I   d ) m0 ·dt   (18)  
           Age b =∫ 1 / H   b ·( I   d   /W)   2 ( I   sub   /I   d ) mb   ·exp (− a/|V   bs |) 
           [0055]    dt   (19)  
           [0056]    Furthermore, in extraction of hot carrier lifetime parameters, the hot carrier lifetime parameters H 0 , m0, H b , and mb are determined as constants on the basis of values measured in a stress acceleration experiment. The model formula (18) is distinguished from the conventional model formula (11) in that the formula (18) adopts a functional form of (exponent of I d )=2−(exponent of I sub ), while the conventional formula adopts (exponent of I d )=1−(exponent of I sub ). The difference is caused by the fact that a hot carrier lifetime is inversely proportional to a yield of one kind of hot carrier in a conventional technique, while the same lifetime is inversely proportional to a yield of two kinds of hot carriers in the present invention. The hot carrier lifetime parameters H 0 , m0, H ,  mb included in the model formulas (17), (18), and (19) are identical to those in the model formulas (12), (13) and (14) according to the present invention. The V gd  dependency is small remarkably, and sufficient simulation accuracy can be obtained even when the parameters are regarded as constants.  
           [0057]    In the model formulas (12), (13) and (14), the dependency of the hot carrier lifetime on the substrate voltage and the gate voltage can be estimated accurately with respect to a wide range of voltage. Therefore, in the method of estimating a lifetime of hot carrier degradation of a MOS transistor of the present invention, a lifetime in actual use can be estimated with accuracy on the basis of a small number of measured values under a stress voltage condition and both the drain current I d  and substrate current I sub  in actual use. Thus, the present invention can provide assurance for the product properly.  
           [0058]    In a method of simulating a circuit characteristic degradation due to hot carrier degradation of a MOS transistor according to the present invention, a highly accurate simulation corresponding well to measured values in product degradation can be realized with repeatability even under a condition that a substrate voltage is applied. Therefore, there is no need for applying a process reliability evaluation standard having an excessive reliability margin for quality assurance. As a result, the reliability evaluation standard is satisfied and the transistor performance can be improved further. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0059]    [0059]FIG. 1 is an explanatory view to show a method of estimating a lifetime on the basis of a hot carrier lifetime model in an embodiment of the present invention.  
         [0060]    [0060]FIG. 2 is an explanatory view to show a method of extracting a hot carrier lifetime parameter as a constant in an embodiment of the present invention.  
         [0061]    [0061]FIG. 3 is an explanatory view to show a method of extracting a hot carrier lifetime parameter as a constant in an embodiment of the present invention.  
         [0062]    [0062]FIG. 4 is a flow chart to show a method of simulating circuit characteristic degradation in an embodiment of the present invention.  
         [0063]    [0063]FIG. 5 is an explanatory view to show a conventional method of estimating a lifetime.  
         [0064]    [0064]FIGS. 6A and 6B are equivalent circuit diagrams to show a conventional method of simulating hot carrier degradation of a MOS transistor.  
         [0065]    [0065]FIG. 7 is a flow chart to show a conventional method of simulating hot carrier degradation of a MOS transistor.  
         [0066]    [0066]FIG. 8 is an explanatory view to show a conventional method of extracting a hot carrier lifetime parameter. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0067]    Embodiments according to the present invention are further explained below by referring to the drawings.  
         [0068]    [0068]FIG. 1 shows a method of estimating a lifetime based on hot carrier lifetime model formulas (12), (13) and (14) according to the present invention. In FIG. 1, the vertical axis is a logarithmic scale of a value τ·(I d /W) 2  calculated from a lifetime τ in a DC stress experiment, a drain current I d  during a stress, and a gate width W of a MOS transistor. The horizontal axis is a logarithmic scale of a ratio I sub /I d , where I sub  is a substrate current during a stress and I d  is a drain current. Data indicated with respective marks of ∘, x, □, ⋄, Δ are values measured under varied conditions. Here, V gs @I submax  denotes a gate-source voltage V gs  at the time that the substrate current I sub  becomes maximum. The plural curves denote fitting curves based on the hot carrier model formulas (12), (13) and (14) corresponding to the respective substrate voltages. A point 1 on the horizontal axis denotes a maximum value of I sub /I d  in actual use, and a point 2 on the vertical axis denotes a value of τ·(I d /W) 2  on the fitting curves at the maximum value of the substrate voltage and I sub /I d  in actual use.  
         [0069]    As shown in FIG. 1, the hot carrier lifetime deteriorates with application of substrate voltage. According to this model, based on physical grounds, deterioration of this hot carrier lifetime caused by application of substrate voltage can be written accurately with respect to wide ranges of drain and gate voltages. An estimated lifetime at the maximum values of the substrate voltage and I sub /I d  in actual use can be calculated on the basis of a value τ·(I d /W) 2  determined at the point 2 on the τ·(I d /W) 2  axis.  
         [0070]    [0070]FIG. 2 is an explanatory view to show a method of extracting model parameters H 0  and m0. In FIG. 2, the vertical axis is a logarithmic scale of a value τ 0 ·(I d /W) 2  calculated from τ 0  lifetime o in a DC stress experiment at the substrate voltage V bs =0, a drain current I d  during a stress and a gate width W of a MOS transistor. The horizontal axis is a logarithmic scale of a ratio I sub /I d , where I sub  is a substrate current during a stress and I d  is a drain current. Data indicated with respective marks of ∘, □, ⋄, Δ, x are measured values.  
         [0071]    First, a method for determining a parameter H 0  as a constant will be explained blow. The following method is used for applying stress voltage used in a stress acceleration experiment in evaluation of the hot carrier reliability. That is, a gate voltage V g  with a maximum substrate current I sub  is used with respect to plural drain voltages V d  used for the acceleration experiment. This voltage is indicated as V g {fourth root}I submax  in FIG. 2. At this time, one gate voltage is set for every drain voltage. In this manner, a line, fitted by a least squares method with respect to data concerning the measurement points, is obtained. In FIG. 2, the fitted straight lines are shown as solid lines. Hot carrier parameters H 0  and m0 are obtained respectively from an intercept and a gradient of the line.  
         [0072]    For determining a parameter h 0  of the model formula (15) by using the parameter H 0  as a function of V gd , the following method is used for applying stress voltage used in a stress acceleration experiment in evaluation of hot carrier reliability. That is, plural gate-drain voltages V gd  are set, to which plural drain voltages V d  used for the acceleration experiment are applied respectively. In this manner, a plurality of parallel straight lines, fitted with a common gradient for every gate-drain voltage V gd  by a least squares method with respect to data concerning the measurement points, are obtained. In FIG. 2, the fitted parallel straight lines are shown as broken lines. From the gradient of the parallel straight lines, a hot carrier lifetime parameter m0 is obtained as a constant. H 0  is determined as a function of V gd  from the plural intercepts of the parallel straight lines, and thereby a parameter h 0  is determined. FIG. 2 demonstrates that sufficient accuracy is obtained even when regarding H 0  as a constant.  
         [0073]    [0073]FIG. 3 is an explanatory view to show a method of extracting model parameters a, H b , and mb. In FIG. 3, τ b  denotes a quantity representing deterioration of lifetime at the substrate voltage |V bs |&gt;0 which is calculated on the basis of the model formulas (12) and (13) from a measured value τ of the lifetime in a DC stress experiment at the substrate voltage |V bs |&gt;0, and the model parameters H 0  and m0 determined previously as constants. The vertical axis is a logarithmic scale of a value τ b ·(I d /W) 2  calculated from τ b , a drain current I d  during a stress, and a gate width W of a MOS transistor. Data indicated with marks of x, □, ⋄, Δ are values respectively measured from measured values. The solid lines are parallel straight lines fitted for the respective substrate voltages V bs . A parameter mb is determined from a gradient of the parallel straight lines. Parameters ‘a’ and H b  are determined by fitting the respective intercepts of the parallel straight lines and the intervals thereof.  
         [0074]    For obtaining a parameter h 0  of the model formula (16) by using the parameter H b  as a function of V gd , the following method is used for applying stress voltage used in a stress acceleration experiment in evaluation of hot carrier reliability. That is, in a case of applying a substrate voltage, a plurality of gate-drain voltages V gd  are set, to which plural drain voltages V d  used for the acceleration experiment are applied respectively. In this manner, similar to the case for determining the parameter h 0 , a plurality of parallel straight lines, fitted with a common gradient for every gate-drain voltage V gd  by a least squares method with respect to data concerning the measurement points, are obtained. From the gradient of the parallel straight lines, a hot carrier lifetime parameter mb is obtained as a constant. H b  is determined as a function of V gd  from the plural intercepts of the parallel straight lines, and thereby a parameter h b  is determined. FIG. 3 demonstrates that sufficient accuracy is obtained even when regarding H b  as a constant.  
         [0075]    [0075]FIG. 4 is a flow chart showing a method of simulating circuit characteristic degradation according to the present invention. In the flow chart, a step S 1  includes sub-steps S 1   a -S 1   g  to extract unknown parameters in the formulas (10), (17), (18) and (19) by using a preliminary measuring experiment.  
         [0076]    In the sub-step S 1   a,  in order to determine a substrate current I sub  in the formulas (17), (18) and (19), a model formula I sub =g(V g , V d ) is determined to fit with a plurality of substrate current I sub  measurement data in the preliminary measuring experiment. Here, V g  represents a gate voltage, and V d  represents a drain voltage. A method of determining a substrate current I sub  is described in IEEE Electron Device Lett., vol. EDL-5, pp. 505-507, December 1984 by Chan et al.  
         [0077]    The sub-steps S 1   b -S 1   d  serve to extract hot carrier lifetime parameters by a preliminary measuring experiment. In the sub-step S 1   b,  stress voltage is applied to a MOS transistor in order to measure a hot carrier lifetime defined in the formula (2). For applying the stress voltage, a gate voltage V g  causing a maximum substrate current I sub  is used with respect to plural drain voltages V d . At this time, one gate voltage is set for every drain voltage. In the subsequent sub-step S 1   c,  a coefficient n is extracted as a constant by a comparison between the empirical formula (1) and data concerning plural measurement points in a DC stress experiment in the sub-step S 1   b.  Similarly in the sub-step S 1   d,  model parameters ‘a’, H 0 , H b , m0 and mb are extracted as constants by a comparison between the empirical formulas (12), (13), and (14) and data concerning plural measurement points in a DC stress experiment of the sub-step S 1   b.    
         [0078]    The sub-steps S 1   e -S 1   g  serve to determine a fresh drain current I d  before applying stress and drain current degradation ΔI d  in the formula (10) for a ΔI d  model. In the sub-step S 1   e,  transistor parameters, such as a flat band voltage and carrier mobility to determine fresh drain current I d (V d , V g ) before stress application, are extracted. BSIM (Berkeley Short-Channel IGFET Model) can be used for a model to determine such a fresh drain current I d (V d , V g ). Details of the BSIM method are described in IEEE J. Solid-State Circuits, vol. SC-22, pp. 558-566, August 1987 by Sheu et al. In the subsequent sub-step S 1   f,  a DC stress is applied to the transistor. In the sub-step S 1   g,  ΔI d  model parameters before and after DC stress application are extracted. The drain current degradation ΔI d (Age, V d , V g ) is determined from this ΔI d  model parameter. The ΔI d  model concerning NMOS is described by the above-mentioned Quader et al. PMOS is described in JP-A-08-64814 by Shimizu et al.  
         [0079]    Transistor parameters should be extracted before the DC stress application in order to bring actual transistor characteristics before the stress application to coincide with the simulated transistor characteristics. Similarly, the ΔI d  model parameters should be extracted before and after the DC stress application in order to bring actual drain current degradation ΔI d  after the stress application to coincide with the simulated drain current degradation ΔI d .  
         [0080]    A step S 2  includes sub-steps S 2   a -S 2   d  in which a reliability simulator simulates hot carrier degradation of a transistor in accordance with the parameters extracted in the step S 1  and the formulas (10), (17), (18) and (19).  
         [0081]    In the sub-step S 2   a,  a drain current is simulated by the transistor parameters before stress application, and the parameters have been extracted in the sub-step S 1   e.  In the sub-step S 2   b,  a substrate current is simulated by the substrate current model formula I sub =g(V g , V d ) determined by the S 1   a.  In the sub-step S 2   c,  Age, which represents degradation of every transistor on the basis of the formulas (17), (18) and (19), is calculated by time integration of a function of a drain current I d  and substrate current I sub  in a circuit. At this time, a drain current I d  simulated in the sub-step S 2   a,  a substrate current I sub  simulated in the sub-step S 2   b,  and model parameters a, H 0 , H b , m0, and mb calculated in the sub-step S 1   d,  are used. In the sub-step S 2   d,  hot carrier degradation of the transistor is simulated based on the Age, by using the formula (10).  
         [0082]    In a MOS transistor, a plurality of degradation modes may exist depending on the stress voltage or the stress temperature. In such a case, the degraded drain current I d ′ represented by the model formula (10) of the present invention can be replaced by a degraded drain current I d ′ for a simulation in accordance with the following formula (20) including one or plural Age′ corresponding to other degradation modes.  
           I   d   ′=I   d ( V   d   , V   g )+Δ I   d (Age, Age′,  V   d   , V   g )   (20)  
         [0083]    A method of estimating a lifetime according to the present invention or a method of simulating circuit characteristic degradation according to the present invention may be programmed wholly or partly, and executed automatically by a computer. When the method of the present invention cannot be executed automatically, it can be executed manually.  
         [0084]    The literature and patent publications discussed above are incorporated herein by reference. The invention may be embodied in other forms without departing from the spirit or essential characteristics thereof. The embodiments disclosed in this application are to be considered in all respects as illustrative and not limiting. The scope of the invention is indicated by the appended claims rather than by the foregoing description, all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein.