Abstract:
A method of preparing a signal for measurement includes receiving the signal and selecting a first edge and a second edge within the signal. The method also includes delivering the first edge to a time interval measurement system after expiration of a first delay period and delivering the second edge to a time interval measurement system after expiration of a second delay period.

Description:
TECHNICAL FIELD 
       [0001]    This document relates generally to a time interval measurement system and method for use in connection with signals, such as data, communication, and/or clock signals, and more particularly to a system and method for removal of frequency-based distortion of such time interval measurements. 
       BACKGROUND 
       [0002]    In the context of circuit design, it is commonplace to evaluate the data communication pathways interconnecting various circuits within a system. Oftentimes, in performing such tests, it is necessary to measure the span of time between two logic level transitions within a signal (or between two transitions in different signals) that has propagated through a communication pathway to be evaluated. For example, in performing such an evaluation, one may wish to measure the span of time between the second rising edge and fourth rising edge in a data signal that has propagated through a communication pathway under test. 
         [0003]      FIG. 1  depicts an exemplary system for performing such a measurement. As can be seen from  FIG. 1 , the exemplary system includes a limiting amplifier  100  that receives a signal  102  that has propagated through a pathway (not depicted in  FIG. 1 ) to be evaluated. The limiting amplifier  100  generates at its output  104  an amplified, isolated output signal that includes the same data transitions as those exhibited by the input signal  102 . Of course, the limiting amplifier  100  exhibits a small delay period, c, meaning that a logic level transition occurring at time to at the input of the limiting amplifier  100  is witnessed at time t 0 +c at the output  104  thereof. 
         [0004]    The output of the limiting amplifier  100  is delivered to a first edge selection system  106 , a second edge selection system  108 , and an arming circuit  110 . The first edge selection system  106  includes an amplifier  112 , which functions in the same manner as the aforementioned limiting amplifier  100 . Thus, the output of the amplifier  112  is essentially an isolated and slightly delayed replica of the input signal  102 . The output of the amplifier  112  is delivered to an edge selection circuit  114 . The edge selection circuit  114  is composed of flip flops, counters, and other combinatorial logic arrangements. The edge selection circuit  114  is configured to select a particular logic level transition (also referred to herein as an “edge” or as a “transition”) from the output data signal  102 , and to deliver the selected edge to a time interval measurement system  116 . Thus, for example, the edge selection circuit  114  may select the second rising edge from the signal  102 . Per such a scenario, the arming circuit  110  instructs the edge selection circuit  114  when to begin counting rising edges within the data signal  102 , and upon observation of the second rising edge, the edge selection circuitry  114  delivers that edge to the time interval measurement system  116 . The second edge selection system  108  (comprised of amplifier  117  and edge selection circuitry  118 ) works in an identical manner, with the notable exception that it may select a different edge than is selected by the first edge selection system  106  (it may select the same edge, as well). The time interval measurement system  116  measures the interval of time between the two edges selected by the first and second edge selection systems  106  and  108 . 
         [0005]      FIGS. 2A-2C  depict the behavior of the system of  FIG. 1 , assuming that the second and fourth rising edges have been selected for measurement.  FIG. 2A  depicts the incoming data signal  102  of  FIG. 1 . The second rising edge in the incoming data signal  102  is identified by reference numeral  200 , and the fourth rising edge is identified by reference numeral  202 . As can be seen, an ideal measurement of the interval of time between these two edges yields a quantity of I. 
         [0006]    It should be noted that for the purpose of discussion of the subject matter herein, the logic level transitions are depicted and described as vertical “edges,” such that a transition from a logic level low to a logic level high, or vice versa, is described as occurring instantly. Of course, a logic level transition occurring in an actual system occurs over a span of time. The edges depicted herein can be thought of as occurring at the instant in time at which the signal crosses a threshold (e.g., voltage threshold) that defines the distinction between a logical “0” from a logical “1.” 
         [0007]      FIG. 2B  depicts the behavior exhibited at the output of the first edge selection circuit  114 . The depiction is presented as a Cartesian plane, with time on the x-axis and voltage on the y-axis. Notably, time=K at the origin of the Cartesian plane. The term K is equal to the propagation delay of the signal  102  through the amplifiers  100  and  112 . Thus, assuming that the first edge selection circuit  114  exhibited no propagation delay, the rising edge  200 ′ (depicted in  FIG. 2B ) at the output thereof would appear vertically aligned with the rising edge  200  of the data signal (depicted in  FIG. 2A ). However, as can be seen from  FIG. 2B , the first edge selection circuit  114  signal exhibits a propagation delay D 1 . As can be seen from  FIG. 2C , the second edge selection circuit  118  exhibits a propagation delay D 2 . Thus, the interval between the second leading edge  200  and fourth leading edge  202 , as measured by the interval measurement system  116 , is (I−D 1 +D 2 ), instead of I. 
         [0008]    As shown in  FIG. 3 , the propagation delay exhibited by an edge selection circuit  114  and/or  118  is a function of, amongst other variables, the frequency content of the signal propagating through the selection circuit. Thus, the propagation delays D 1  and D 2  constantly change, and simple addition/subtraction of a constant cannot achieve the end goal of correcting the measurement generated by the interval measurement system  116 . 
         [0009]    From the foregoing, it is evident that there exists a need by which distortions, such as frequency-dependent distortion (and other mechanisms, e.g., thermal), of interval measurements may be reduced. 
       SUMMARY  
       [0010]    Against this backdrop, the present invention was developed. According to one aspect of the invention, a method of preparing a signal for measurement includes receiving the signal and selecting a first edge and a second edge within the signal. The method also includes delivering the first edge to a time interval measurement system after expiration of a first delay period and delivering the second edge to a time interval measurement system after expiration of a second delay period. 
         [0011]    According to another aspect on the invention, a system for measurement of a time interval includes a first edge selection circuit configured to receive a signal, to select a first transition within the signal, said selection occurring over a first span of time, and to deliver the first selected transition to a first state device upon elapsing of the first span of time. The system also includes a second edge selection circuit configured to receive the signal, to select a second transition within the signal, said selection occurring over a second span of time, and to deliver the second selected transition to a second state device upon elapsing of the first span of time. The system further includes a first delay element configured to deliver a pulse to the first state device at a point in time following the elapsing of the first span of time, so that the first state device assumes a state determined by the first selected transition, and a second delay element configured to deliver a pulse to the second state device at a point in time following the elapsing of the second span of time, so that the second device assumes a state determined by the second selected transition. 
         [0012]    According to yet another aspect of the invention, there is provided a method of preparing a signal for measurement. The method comprising receiving the signal, selecting a first edge within the signal, selecting a second edge within the signal, delivering the first edge to a time interval measurement system after expiration of a first delay period, and delivering the second edge to a time interval measurement system after expiration of the first delay period. 
         [0013]    While the invention will be described with respect to preferred embodiment configurations, and with respect to preferred devices and example edge transitions, it will be understood that the invention is not to be construed as limited in any manner by either such configuration, preferred devices or example edge transitions described herein. Instead, the principles of this invention extend to any environment in which a first edge is delivered to a time interval measurement system after expiration of a first delay period and a second edge is delivered to a time interval measurement system after expiration of a second delay period. These and other variations of the invention will become apparent to those skilled in the art upon a more detailed description of the invention. 
         [0014]    The advantages and features which characterize the invention are pointed out with particularity in the claims annexed hereto and forming a part hereof. For a better understanding of the invention, however, reference should be had to the drawings which form a part hereof and to the accompanying descriptive matter, in which there is illustrated and described a preferred embodiment of the invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    In the drawings in which like elements are identified with the same designation numeral: 
           [0016]      FIG. 1  depicts an exemplary embodiment of a system for measuring a time interval between logic level transitions. 
           [0017]      FIG. 2A  depicts an exemplary incoming data signal to the system  FIG. 1 . 
           [0018]      FIG. 2B  depicts the behavior exhibited at the output of the first edge selection circuit. 
           [0019]      FIG. 2C  depicts the behavior exhibited at the output of the second edge selection circuit. 
           [0020]      FIG. 3  depicts an exemplary relationship between a delay exhibited by an edge selection circuit of  FIG. 1 , and the frequency content of the incoming signal. 
           [0021]      FIG. 4  depicts an exemplary embodiment of an improved system for measuring a time interval between logic level transitions. 
           [0022]      FIG. 5A  depicts an exemplary incoming data signal to the system of  FIG. 4 . 
           [0023]      FIG. 5B  depicts the behavior exhibited at the output of the first edge selection circuit of the system of  FIG. 4 . 
           [0024]      FIG. 5C  depicts the behavior exhibited at the output of the first delay element of the system of  FIG. 4 . 
           [0025]      FIG. 5D  depicts the behavior exhibited at the output of the first D flip flop of the system of  FIG. 4 . 
           [0026]      FIG. 5E  depicts the behavior exhibited at the output of the second edge selection circuit of the system of  FIG. 4 . 
           [0027]      FIG. 5F  depicts the behavior exhibited at the output of the second delay element of the system of  FIG. 4 . 
           [0028]      FIG. 5G  depicts the behavior exhibited at the output of the second D flip flop of the system of  FIG. 4 . 
           [0029]      FIG. 6  depicts an embodiment of the system of  FIG. 4 , in which a time interval may be measured between edges of different signals. 
           [0030]      FIG. 7  depicts an embodiment of the system of  FIG. 4 , in which a time interval may be measured between rising and falling edges. 
       
    
    
     DETAILED DESCRIPTION  
       [0031]    Various embodiments of the present invention will be described in detail with reference to the drawings, wherein like reference numerals represent like parts and assemblies throughout the several views. Reference to various embodiments does not limit the scope of the invention, which is limited only by the scope of the claims attached hereto. Additionally, any examples set forth in this specification are not intended to be limiting and merely set forth some of the many possible embodiments for the claimed invention. 
         [0032]    Turning first to  FIG. 4 , a measurement system according to the present invention that minimizes the aforementioned frequency dependent distortion of time interval measurements is disclosed. The system of  FIG. 4  may be identical to the system of  FIG. 1 , with the exception that four additional elements have been added thereto: (1) a first fixed delay element  400 ; (2) a second fixed delay element  402 ; (3) a first D-type flip flop  404 ; and (4) a second D-type flip flop  406 . 
         [0033]    As can be seen from  FIG. 4 , the signal propagating to the input of the first edge selection circuit  114  is split, and a portion thereof is delivered to a fixed delay element  400 . The fixed delay element  400  is a device that conducts a signal from its input to its output, and exhibits a substantially fixed propagation delay in so doing. For example, according to one embodiment, the fixed delay element  400  is a coaxial cable, the length of which determines the propagation delay. Per such an embodiment, the propagation delay exhibited by the fixed delay element  400  is substantially independent of the frequency content or any other time related distortion of the signal propagating through the element  400 , and is also substantially independent of other sources of distortion. Of course, it is understood that other elements achieve the similar effect of delivering a signal from an input to an output with a substantially fixed delay, and other such elements may be used in connection with the measurement schemes described herein. 
         [0034]    The output of the fixed delay element  400  is coupled to the clock input of a D-type flip flop  404 . The D-type flip-flop  404  operates so that the logic level exhibited at its D input at the time of a rising edge on its clock input is held on its output (Q), until the occurrence of the next rising edge at the clock input (at which time whatever logic level is exhibited at the D input is again held on the output, and so on). 
         [0035]    By virtue of the structure of the system of  FIG. 4 , the data signal to be measured is split and travels along two paths toward the D-type flip flop  404 : (1) a first path through the edge selection circuit  114 ; and (2) a second path through the fixed delay element  400 . Such a state of affairs is useful in selecting a rising edge in the data signal (an exemplary embodiment of a system for detecting rising and falling edges is discussed below). If the delay exhibited by the delay element  400  is slightly longer than the delay exhibited by the edge selection circuit  114 , then the flip flop  404  will transfer a selected rising edge (from edge selection circuit  114 ) to its output when it receives the slightly-more delayed rising edge (from the fixed delay element  400 ) at its clock pin. 
         [0036]    It should be noted that the D-type flip flop  404  exhibits a delay, δ. Thus, if a rising edge is observed at the clock input of the flip flop  404  at time to, the logical “1” observed at the D input at time to is observed at the output of the flip flop at time t 0 +δ. 
         [0037]    The delay, δ, exhibited by the D-type flip flop  404  is substantially constant if the logic level provided to the D input of the flip flop  404  arrives in advance of the rising clock edge by a set-up time of C. For example, for some types of flip flops, C may be approximately 50 picoseconds, but it is to be understood that this value can vary substantially from one type of device to another. Accordingly the delay exhibited by the fixed delay element  400  should be chosen so as to be substantially equal to (or slightly greater than) the sum of the maximum delay exhibited through the edge selection circuit  114  and the aforementioned set-up time, C. 
         [0038]    The second distortion-reduced edge selection system  403  works in an identical fashion as that just described with reference to the first distortion-reduced edge selection system  401 . Thus, the system of  FIG. 4  behaves as shown in  FIGS. 5A-5G . 
         [0039]      FIG. 5A  depicts an incoming data signal  500 . For the sake of illustration, it is assumed that the interval of time between the second and fourth rising edges  502  and  504  is to be measured. Thus, as can be seen from  FIG. 5A , if measured ideally, the span of time between the second and fourth rising edges is equal to I. 
         [0040]      FIG. 5B  depicts the signal exhibited at the output of the first edge selection circuit  114 . As can be seen, the first rising edge  502 ′ exhibits a delay, D 1  as it propagates through the first edge selection circuit  114 . Thus, the second rising edge  502  propagates through the first edge selection circuit  114  and arrives at the D input of the first flip flop  404  at a point in time D 1  seconds later than it was received by the first edge selection circuit  114 . 
         [0041]      FIG. 5C  depicts the second rising edge  502 ″, as it exits the first fixed delay element  400 . As can be seen, the second rising edge  502 ″ exhibits a fixed delay of FD 1  as it exits the first fixed delay element  400 . As mentioned previously, the delay of an edge propagating through an edge selection circuit is not knowable in advance. However, the delay is known to fall within a distribution. Such a distribution is depicted by bell curve  506 . (It is understood that the distribution of possible delays is not necessarily Gaussian. Bell curve  506  is presented for the sake of illustration only.) As can be seen, from  FIG. 5B , the first edge selection circuit  400  exhibits a maximum delay, which is identified by reference numeral  508 . FD 1  is chosen to be equal to (or slightly greater than) the sum of the maximum delay  508  exhibited by the first edge selection circuit  114  and the aforementioned set-up time, C 1 , required by the first flip flop  404 . Thus, the second rising edge  502  propagates through the fixed delay element  400  and arrives at the clock input of the first flip flop  404  at a point in time FD 1  seconds later than it was received by the first edge selection circuit  114 . Accordingly, the first flip flop  404  presents the second rising edge  502  at its output at a point in time FD 1 +E 1  seconds later than it was received by the first edge selection circuit  114 , where El represents the aforementioned substantially constant delay exhibited by the first flip flop  404  (this is depicted in  FIG. 5D ). 
         [0042]      FIG. 5E  depicts the signal exhibited at the output of the second edge selection circuit  118 . As can be seen, the fourth rising edge  504 ′ exhibits a delay, D 2  as it propagates through the second edge selection circuit  118 . Thus, the fourth rising edge  504  propagates through the second edge selection circuit  118  and arrives at the D input of the second flip flop  406  at a point in time D 2  seconds later than it was received by the second edge selection circuit  118 . 
         [0043]      FIG. 5F  depicts the fourth rising edge  504 ″, as it exits the second fixed delay element  402 . As can be seen, the fourth rising edge  504 ″ exhibits a fixed delay of FD 2  as it exits the second fixed delay element  402 . Once again, the delay of an edge propagating through an edge selection circuit is not knowable in advance. However, the delay is known to fall within a distribution. Such a distribution is depicted by bell curve  510 . (It is understood that the distribution of possible delays is not necessarily Gaussian. Like bell curve  506 , bell curve  510  is presented for the sake of illustration only.) As can be seen, from  FIG. 5E , the second edge selection circuit  402  exhibits a maximum delay, which is identified by reference numeral  512 . FD 2  is chosen to be equal to (or slightly greater than) the sum of the maximum delay  512  exhibited by the second edge selection circuit  118  and the aforementioned set-up time, C 2 , required by the second flip flop  406 . Thus, the fourth rising edge  504  propagates through the second fixed delay element  402  and arrives at the clock input of the second flip flop  406  at a point in time FD 2  seconds later than it was received by the second edge selection circuit  118 . Accordingly, the second flip flop  406  presents the fourth rising edge  504  at its output at a point in time FD 2 +E 2  seconds later than it was received by the second edge selection circuit  118 , where E 2  represents the aforementioned substantially constant delay exhibited by the second flip flop  406  (this is depicted in  FIG. 5G ). 
         [0044]    The aforementioned description assumes that the first and second flip flops  404  and  406  are the same brand and part number, and therefore exhibit the substantially similar delay, i.e., that E 1 ≈E 2 . The import of the foregoing is that the interval, I, between the second and fourth rising edges  502  and  504  may be found by the time interval measurement circuitry  116  by subtracting the difference between FD 1  and FD 2  from the measured interval, as shown in  FIG. 5G , i.e., I=Measured Interval−(FD 1 −FD 2 ). Notably, assuming that FD 1 =FD 2 , and further assuming that E 1 =E 2 , then the measured interval is equal to interval, I, between the second and fourth rising edges  502  and  504 , and no correction is needed. Of course, assuming the general case in which FD 1 ≠FD 2  and E 1 ≠E 2 , then I=Measured Interval−(FD 1 +E 1 −FD 2 −E 2 ), because the difference between FD 1  and FD 2 , and the difference between E 1  and E 2  are constant, meaning that such correction may be made by the time interval measurement circuitry  116 . 
         [0045]    As mentioned previously, the foregoing scheme generally assumes that the delay imposed by the fixed delay elements  400  and  402  is equal to, or slightly larger than, the maximum delay exhibited by their respective edge selection circuits  114  and  118  plus the needed set-up time (C 1  or C 2 ) for the respective D flip flops  404  and  406 . For the sake of manufacturability, it may be desirable to arrange the edge selection circuitry  114  and  118  to impose a selectable variable delay at their respective output stages, so that their respective delays are equal to D 1 +ε 1  and D 2 +ε 2 , where ε 1  and ε 2  represent the aforementioned chosen variable delay. For example, the output stage of each edge selection circuit  114  and  116  may include a comparator biased with a reference voltage that is chosen to impose a delay on the selected edge. Assuming a comparator is used to generate the delay, and assuming that a rising edge is selected, then the greater the reference voltage, the longer the delay, and the lower the reference voltage, the shorter the delay (the selected variable delay, □ 1  or ε 2 , can be as short as 0 seconds or as long as the rise time of a logic level transition). Such flexibility is useful, when, for instance, the fixed delay elements  400  and  402  are embodied as coaxial cables of a predetermined length. In order to satisfy the aforementioned condition that the delay imposed by the fixed delay elements  400  and  402  is equal to, or slightly larger than, the maximum delay exhibited by their respective edge selection circuits  114  and  118  plus the needed set-up time (C 1  or C 2 ) for the respective D flip flops  404  and  406 , the delay of the edge selection circuits  114  and  118  may be altered by changing the bias of the reference voltage on the aforementioned comparators, in order to bring about the aforementioned condition. 
         [0046]      FIG. 6  depicts an embodiment of the measurement system in which rising edges from two different signals may be selected for time interval measurement. As can be seen from  FIG. 6 , the front end of the measurement system includes first and second amplifiers  600  and  602  that receive first and second signals  604  and  606 . The first amplifier  600  delivers an amplified and isolated replica of the first signal  604  to a first distortion-reduced edge selection system  608 , and to an arming circuit  612 . Similarly, the second amplifier  602  delivers an amplified and isolated replica of the second signal  606  to a second distortion-reduced edge selection system  610 , and to the arming circuit  612 . The edge selection systems  608  and  610  are constructed and operate as described with reference to distortion-reduced edge selection systems  401  and  403  in  FIG. 4 . Like the arming circuit of  FIG. 4 , the arming circuit  612  of  FIG. 6  operates so as to instruct the edge selection circuits within each edge selection system  608  and  610  when to start counting edges or to otherwise being the edge selection process. The outputs of each edge selection system  608  and  610  are coupled to a time interval measurement system  614 , which measures the time interval between the edges selected by the aforementioned selection systems  608  and  610 , and corrects the measured interval according to the correction process described with reference to  FIG. 5 . Thus, by virtue of the foregoing arrangement, the system of  FIG. 6  may operate so as to determine a span of time separating logic level transitions in two different signals (e.g., to find the span of time separating the second rising edge in the first data signal  604  from the fourth rising edge in the second data signal  606 ). 
         [0047]      FIG. 7  depicts an embodiment of the measurement system having four edge selection systems: (1) a first edge selection system including front-end amplifier  700 , fixed delay element  702 , edge selection circuitry  704 , and D flip flop  706 ; (2) a second edge selection system including front-end amplifier  700 , fixed delay element  702 , edge selection circuitry  708 , and D flip flop  710 ; (3) a third edge selection system including front-end amplifier  700 , fixed delay element  702 , edge selection circuitry  712 , and D flip flop  714 ; and (4) a fourth edge selection system including front-end amplifier  700 , fixed delay element  702 , edge selection circuitry  716 , and D flip flop  718 . The four aforementioned edge selection systems operate as described with reference to  FIGS. 4 and 5 , and are coupled to a time interval measurement system  720  that measures the time interval separating a selected pair of edges supplied thereto, as described previously herein. 
         [0048]    The system of  FIG. 7  includes two D flip flops  706  and  714  that have inverted clock inputs. Therefore, these flip flops  706  and  714  may be used for selection of falling edges (the previous examples herein have assumed selection of rising edges). Accordingly, the system of  FIG. 7  may measure the span of time between two rising edges (using the edges from flip flops  710  and  718 ), between two falling edges (using the edges from  706  and  714 ), between a rising edge and a subsequent falling edge (using the edges from flip flops  710  and  714 , and between a falling edge and a subsequent rising edge (using the edges from flip flops  710  and  718 ). 
         [0049]    Additionally, it should be noted that the front-end amplifier  700  and fixed delay element  702  are shared by all four of the aforementioned edge selection systems, thereby reducing the number of components needed, and the associated cost with each component. 
         [0050]    It is to be noted that the embodiments of  FIGS. 6 and 7  may be combined, so that time intervals between rising and falling edges on different signals may be measured. 
         [0051]    The various embodiments described above are provided by way of illustration only and should not be construed to limit the invention. Those skilled in the art will readily recognize various modifications and changes that may be made to the present invention without following the example embodiments and applications illustrated and described herein, and without departing from the true spirit and scope of the present invention, which is set forth in the following claims.