Abstract:
A DC voltage control circuit comprising DC superposing means for superposing a control signal an input signal; discriminating means for discriminating an output of the superposing means with a plurality of discriminating levels including a center level and for providing a regenerated output digital signal and an error digital signal; control signal generating means for providing control signal in response to the error digital signal; and limiter means for limiting the output of said discriminating means to be within a predetermined range which is less than a spacing between said discriminating level and the center level.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a DC voltage control circuit, and more particularly a DC voltage control circuit utilized in a demodulation apparatus as a circuit for discriminating a demodulated signal produced by phase detecting a quadrature amplitude modulated wave, and for compensating for the DC drift or the like of the demodulated signal. 
     In recent years, a multi-level quadrature amplitude modulation (QAM) system for carrying a digital signal with a microwave carrier wave has been developed as a high efficiency modulation system capable of efficiently utilizing a frequency band. In order to realize such a high efficiency modulation system, it is necessary to avoid, as far as possible, undesirable phenomenon occurring at various parts of the circuit, a typical one of such phenomena being a DC drift contained in the input to the discriminating circuit of the demodulation apparatus. 
     In a DC voltage control circuit for compensating for the DC drift component, a DC superposing circuit such as a subtractor superposes a DC voltage upon the demodulated multi-level signal. A discriminating circuit such as an A/D (analog-to-digital) converter discriminates the output of the superposing circuit with respect to a plurality of discriminating levels and provides a plurality of digital signals. The control signal generator filters one of the digital signals and produces the DC voltage. This circuit operates satisfactory when used continuously. But, as will be described later, when the input signal is once interrupted and then recovered, there is a fear that an abnormal pull-in occurs depending upon the initial state. Therefore, the circuit provides erroneous DC voltage, thereby failing to resume a normal operation. 
     SUMMARY OF THE INVENTION 
     An object of this invention is to provide an improved DC voltage control circuit capable of avoiding an abnormal pull-in phenomenon in any initial state. 
     According to this invention, there is provided a DC voltage control circuit comprising DC superposing means for superposing a control signal upon an input signal; discriminating means for discriminating an output of the superposing means with a plurality of discriminating levels including a center level and providing a regenerated output digital signal and an error digital signal; control signal generating means for providing the control signal in response to the error digital signal, and limiter means limiting the output of the discriminating means to be within a predetermined range which is less than a spacing between the discriminating level and the center level. 
     According to a modified embodiment of this invention, there is provided a DC voltage control circuit comprising DC superposing means for superposing a control signal on an input signal; discriminating means for discriminating an output of said superposing means with a plurality of signal discriminating levels including a center discriminating level and with a plurality of error discriminating levels and for providing a plurality of digital signals, said signal discriminating levels dividing said input signal into a plurality of signal regions, said error discriminating levels dividing said signal regions into two, respectively; and control signal generator means for generating said control signal in response to some of said digital signals, which comprise error information obtained from said error regions except at least the error regions on positive or negative side adjoining said center discriminating level. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the accompanying drawings: 
     FIG. 1 is a block diagram showing a prior art demodulation apparatus; 
     FIG. 2 shows discrimination regions of an A/D converter; 
     FIG. 3 is a block diagram showing a first embodiment of a DC voltage control circuit according to this invention; 
     FIG. 4 is a block diagram showing a second embodiment of the DC voltage control circuit according.to this invention; 
     FIG. 5 is a block diagram showing a third embodiment of the DC voltage control circuit according to this invention; 
     FIG. 6 is a block diagram showing a fourth embodiment of the DC voltage control circuit according to this invention; 
     FIG. 7 is a block diagram showing a fifth embodiment of the DC voltage control circuit according to this invention; 
     FIG. 8 is a block diagram showing a first embodiment of demodulation apparatus according to this invention which is adapted for demodulation of 4 PSK (4-phase phase shift keying) waves; and 
     FIG. 9 is a block diagram showing a second embodiment of demodulation apparatus according to this invention which is adapted for demodulation of 64 QAM (64-level quadrature amplitude modulation) waves. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     To have better understanding of this invention, the demodulator apparatus will firstly be described with reference to FIG. 1. This demodulation apparatus is adapted for 16 QAM waves and comprises an intermediate frequency amplifier 1 having an automatic gain control performance, a demodulation circuit 300 for demodulating a 16-level QAM wave outputted from the amplifier 1 to provide two series of 4-level digital signals P and Q, and a DC voltage control circuit 200. This circuit 200 includes subtractors 3 and 3a for superposing DC voltages on respective outpus P and Q, discrimination circuits A/D converters 4 and 4a for discriminating the outputs 102 of the substractors 3 and 3a in terms of 8 levels to produce 2-bit regenerated output signals X 1  or X 2 , and Y 1  or Y 2  and an one-bit error signal X 3  or Y 3 , and low-pass filters 5 and 5a which repectively suppress high frequency noise components contained in the error signals X 3  and Y 3 , for producing a control DC voltage 101 fed back to subtractors 3 and 3a. 
     The demodulation circuit 300 comprisies a carrier synchronizing circuit 19 responsive to the output data signals of the DC voltage control circuit 200 to produce a reference carrier frequency, and a demodulator 2 including a phase detector 24 and another phase detector 24a which respectively respond to the reference carrier frequency directly and via a 90 degree phase shifter 25 so as to demodulate a 16 QAM wave applied to the phase detectors 24 and 24a. 
     The carrier synchronizing circuit 19 comprises a section including an exclusive OR gate 23a with its inputs connected via terminals C 1  and C 2  to a data signal Y 3  from the A/D converter 4a and a data signal X 1  from the A/D converter 4, an exclusive OR gate 23 with its inputs connected via terminals C 3  and C 4  to a data signal X 3  from the A/D converter 4 and a data signal Y 1  from the A/D converter 4a, and a subtractor 22 applied with outputs of the exclusive OR gates 23 and 23a. This section is responsive to the outputs of the A/D converters 4 and 4a to generate an error signal for detecting the rotational direction of the respective waveform response signals of the 16 QAM wave. In addition to this error signal generating section, the carrier synchronizing circuit 19 has a low-pass filter 21 responsive to the output of the subtractor 22, and a voltage controlled oscillator 20 controlled by the output of the low-pass filter to produce the reference carrier frequency supplied to the phase detector 24 and 90 degree phase shifter 25 via a terminal C 5 . 
     The carrier synchronizing circuit 19 operates as follows. Data signals Y 1  and X 3  are exclusive ORed at the exclusive OR gate 23 so that this gate 23 produces an output &#34;0&#34; when the respective waveform response signals of the 16 QAM wave rotate counterclockwise. Data signals X 1  and Y 3  are exclusive ORed at the exclusive OR gate 23a which, in turn, produces an output &#34;1&#34; when the respective waveform response signals rotate counterclockwise. Thus, by subtracting the output signals of the two exclusive OR gates 23 and 23a at the subtractor 22, a &#34;0&#34; signal of doubled level can be obtained. This doubled &#34;0&#34; level output is passed through the low-pass filter 21 for suppression of noises and supplied to the voltage controlled oscillator 20 which then produces a carrier signal in synchronism with the input 16 QAM wave. 
     In this demodulation apparatus, the DC voltage control circuit comprised of subtractors 3 and 3a, A/D converters 4 and 4a and low-pass filters 5 and 5a controls the DC component contained in the demodulated signals such that the A/D converters can discriminate the signal at an optimum operating condition. 
     FIG. 2 is a chart showing the discrimination regions of each A/D converter useful to explain the operation of the DC voltage control circuit. More particularly, the input voltage to each A/D converter 4 or 4a is divided into four signal regions I to IV in accordance with three signal discriminating levels V 0  =0 volt, V 2  =+2d volt, and V -2  =-2d volt, and then respective signal regions are divided into two error regions I +  and I - , II +  and II - , III +  and III - , and IV +  and IV -  in accordance with error discriminating levels V 1  =+d volt, V -1  =-d volt, V 3  =+3d volt and V -3  =-3d volt. Each A/D converter 4 or 4a is constructed to send out binary signals X 1 , X 2  and X 3  shown in FIG. 2 or Y 1 , Y 2  and Y 3  (not shown) depending upon whether the input signal 102 is contained in which one of the regions shown in FIG. 2. Since either A/D converter 4 or 4a operates in the same manner, only one channel (P signal channel) including the A/D converter 4 will be described hereafter. When the A/D converter 4 shown in FIG. 1 is in the optimum operating state, the four signal levels of the input signal 102 coincide with centers of respective signal regions, that is, error discriminating levels A 1  to A 4 . When the input signal level deviates from these values in the positive direction by Δv to become A 1 , to A 4  &#39; due to a DC drift, the error signals X 3  become all &#34;1&#34; with respect to any signal levels, thereby increasing the DC output 101 of the low-pass filter 5. Consequently the DC component in the output 102 of the subtractor 3 whose input P has been superposed with a DC voltage will change in the negative direction so that A 1  &#39; to A 4  &#39; are shifted in a direction of arrow α to return to the optimum operating state. Conversely, when the input signal level shifts in the negative direction as shown by dotted lines due to the DC drift, the error signals X 3  become all &#34;0&#34; to decrease the DC output of the control signal generator 5 so that the DC components contained in the output signal 102 of the substractor 3 will be controlled in the positive direction. Thus, even when the DC component of the input signal D inputted to the subtractor is caused to vary due to the DC drift caused by the demodulator and a baseband amplifier, the input signal 102 to the A/D converter will always be controlled to the optimum operating states A 1  to A 4 . 
     With this prior art DC voltage control circuit, however, when the input signal is once interrupted and then applied again, the DC component deviation ΔV&#39; at the initial state is large so that ΔV&#39; becomes larger than the discriminating level spacing d as shown by B 1  to B 4  in FIG. 2. Then, the arrow signal X 3  regarding B 1  become &#34;1&#34; but error signals X 3  regarding B 2  to B 4  become all &#34;0&#34;, thus increasing outputs &#34;0&#34;. Consequently, the DC componet of the output 102 of subtractor 3 will be controlled in the negative direction. Consequently, except for B 2  subject to control in the normal direction as shown by arrow γ, B 2  to B 4  will be shifted in direction β opposite to the normal control direction, thus resulting in abnormal pull-in phenomenon wherein B 2  shifts to A 1 , B 3  to A 2 , and B 4  to A 3 . On the other hand, when the DC component deviation change, greatly in the negative direction beyond -d to assume B 1  &#39; to B 4  &#39;, the number of &#34;1&#34; outputs of the error signals X 3  increases, whereby except for B 1  &#39; subject to control in the normal direction as shown by arrow γ, B 1  &#39; to B 4  &#39; are controlled in direction β&#39; opposite to the normal direction to cause abnormal pull-in phenomenon. Consequently, the input signal will never be correctly regenerated, thus causing errors. 
     A first method effective to prevent the abnormal pull-in phenomenon involves the step of not using error information from error regions I - , II + , II - , III + , III -  and IV +  that might generate control information in erroneous directions shown by arrows β and β&#39; in FIG. 2 and causing the control signals based on only the outputs from error regions I +  and IV -  that output control information in correct directions shown by γ; and γ&#39; in FIG. 2. 
     FIG. 3 is a block diagram showing a first embodiment of a DC voltage control circuit, generally designated by 201, according to this invention based on this method. Similar to FIG. 1, either signal channel of this embodiment (exemplified as P signal channel herein) is constituted by a subtractor 3, an A/D convertor 4 and a control signal generator 9. The control signal generator 9 comprises an AND gate circuit 6 that determines a logic product of the outputs X 1 , X 2  and X 3  of the A/D converter 4, a NOR gate circuit 7 that determines a NOR logic sum of the outputs X 1 , X 2  and X 3 , a flip-flop circuit 8 with its set input terminal connected to receive the output signal S 1  of the AND gate circuit 6 and its reset terminal connected to receive the output signal R 1  of the NOR gate circuit 7, and a low-pass filter 5 having the same construction as that shown in FIG. 1. The following Table I shows how the output signals S 1  and R 1  of the AND gate circuit 6 and the NOR gate circut 7 are related to various error regions shown in FIG. 2. 
     
                       TABLE______________________________________I.sup.+ I.sup.-          II.sup.+                 II.sup.-                       III.sup.+                            III.sup.-                                  IV.sup.+                                        IV.sup.-______________________________________S.sub.11      0      0    0     0    0     0     0R.sub.10      0      0    0     0    0     0     1______________________________________ 
    
     By using the output S 1  =&#34;1&#34; from region I +  and the output R 1  =&#34;1&#34; from region IV -  the flip-flop circuit 8 is caused to produce a binary signal R 1  of &#34;1&#34; and &#34;0&#34; and the signal R 1  is processed by the low-pass filter 5 in the same manner as has been described in connection with FIG. 1 for producing a DC output 103. With the construction shown in FIG. 3, even in the case of B 1  to B 4  and B 1  &#39; to B 4  &#39; shown in FIG. 2, correct controls shown by γ and γ&#39; can be ensured, thus eliminating abnormal pull-in operation. 
     FIG. 4 is a block diagram showing a second embodiment of DC voltage control circuit 202 according to this invention which is constituted by a subtractor 3, an A/D converter 4 and a control signal generator 9a. In this embodiment, the control signal generator 9a is constituted by an OR gate circuit 10, AND gate circuits 11 and 12, a NAND gate circuts 13, a NOT circuit 14, a flip-flop circuit 8, and a low-pass filter 5. The circuit of this second embodiment is constructed so as not to use the error information from the error regions II -  and III +  among various error regions shown in FIG. 2 but to produce a control signal in accordance with only the error information from remaining six error regions. The set input S 2  and the reset input R 2  of the flip-flop circuit 8 are related to various error regions as shown in the following Table II. 
     
                       TABLE II______________________________________I.sup.+ I.sup.-          II.sup.+                 II.sup.-                       III.sup.+                            III.sup.-                                  IV.sup.+                                        IV.sup.-______________________________________S.sub.21      1      1    0     0    0     0     0R.sub.20      0      0    0     0    1     1     1______________________________________ 
    
     Thus, the control signal is generated by using the output S 2  of &#34;1&#34; and the output R 2  of &#34;1&#34;. Since, even when the input signal 102 to the A/D converter 4 shifts to A 1  &#39; to A 4  &#39; or B 1  to B 4  from the optimum state, the probability of generating the four signal levels is equal and since their order of generation can be considered random, the ratio of probabilities at which S 2  becomes &#34;1&#34; and R 2  becomes &#34;1&#34; becomes 2:1. For this reason, the interval in which the ouptput Q 2  of the flip-flop circuit 8 becomes &#34;1&#34; will become longer than the interval in which the output Q 2  becomes &#34;0&#34; so that the input signal 102 will be controlled in the directions α and γ. Conversely, when the input signal 102 shifts to B 1  &#39; to B 4  &#39;, the input signal will be controlled in the normal direction shown by arrow γ&#39;, thus always converging to the optimum state without causing any abnormal pull-in phenomenon. 
     FIG. 5 is a block diagram showing a third embodiment of DC voltage control circuit 203 according to this invention. The circuit 203 comprises a subtractor 3, an A/D converter 4 and a control signal generator 9b. The control signal generator 9b is constituted by an AND gate circuit 15, a NAND gate circut 16, a flip-flop circuit 8 and a low-pass filter 5. In this embodiment, a control signal is generated by using error information from the error regions I + , II + , III -  and IV - . The set input S 3  and the reset input R 3  of the flip-flop circuit 8 are related to various error regions as shown in the following Table III. 
     
                       TABLE III______________________________________I.sup.+ I.sup.-          II.sup.+                 II.sup.-                       III.sup.+                            III.sup.-                                  IV.sup.+                                        IV.sup.-______________________________________S.sub.31      0      1    0     0    0     0     0R.sub.30      0      0    0     0    1     0     1______________________________________ 
    
     Thus, the control signal is provided by using outputs S 3  of &#34;1&#34; from regions I +  and II + , and outputs R 3  of &#34;1&#34; from regions III -  and IV - . In this circuit, when the input signal 102 are B 1  to B 4  and b 1  &#39; and B 4  &#39; shown in FIG. 3 the probability in which S 3  is &#34;1&#34; becomes equal to that in which R 3  is &#34;1&#34; so that a valid control signal can not be produced. In other cases, control signals approaching toward the optimum operation state can be produced so that the control signal can be converged on the optimum operation state free from abnormal pull-in phenomenon although time for the convergence is prolonged slightly. 
     FIG. 6 is a block diagram showing a fourth embodiment of DC voltage control circuit 204 according to this invention. The circuit 204 comprises a subtractor 3, an A/D converter 4 and a control signal generator 9c. The control signal generator 9C is provided with a switching circuit 17 which feeds to a low-pass filter 5 an error signal X 3  (same as that of the prior art shown in FIG. 1) or the flip-flop output Ql (identical to that of the third embodiment shown in FIG. 3). A switching control circuit 18 compares a positive output Q 1  and an inverted output Q 1 . When Q 1  is in sequence of &#34;1&#34; or &#34;0&#34;, the switching circuit 17 selects Q 1  as the input whereas when Q 1  alternately becomes &#34;1&#34; and &#34;0&#34;, the transfer circuit 17 select signal X 3  as the input to the low-pass filter 5. Accordingly, when the input signal 102 greatly deviates from the optimum level, the circuit operates in the same manner as in FIG. 3, thus controlling the control signal substantially near the optimum level. Thereafter, a highly precise control is performed by utilizing error information from all error regions in the same manner as in FIG. 1 utilizing X 3 . 
     Although the embodiments shown in FIGS. 3 and 4 are constructed to form set and reset inputs to the flip-flop circuit 8 by subjecting outputs X 1 , X 2  and X 3  of the A/D converter 4 to logical processings, the set and reset inputs can be derived out directly from the outputs of respective discriminators comprising the A/D converter 4. Furthermore, the embodiments shown in FIGS. 3 to 5 are constructed to produce the control voltage 101 by converting &#34;1&#34; information to the set input terminal and &#34;1&#34; information to the reset input terminal into binary signals with the flip-flop circuit, it is also possible to make the set and reset inputs correspond to positive and negative voltages and then to integrate the positive and negative voltages to produce the control signal, without utilizing the flip-flop circuit. 
     The embodiment shown in FIG. 6 is constructed to use the circuit shown in FIG. 1 and the circuit shown in FIG. 3 by switching them but the circuit shown in FIG. 3 may be substituted by the circuit shown in FIG. 4 or 5. Further, it should be understood that the circuits shown in FIGS. 3 and 4 may be combined. 
     Although, in the foregoing embodiments, a case was described in which the input signal level is a four-level signal of ±d and ±3d, which have positive and negative symmetricity, the signal may not always be symmetrical in positive and negative directions, multilevel signals other than the four level signal can also be processed in the same manner. Although a subtractor was used for the purpose of superposing DC voltage upon the input signal, an adder can be used instead of the subtractor. In other words, any other circuit can be used so long as it can control the DC component with a control signal. 
     In still another embodiment of DC voltage control circuit 205 according to this invention as shown in FIG. 7, there are provided a subtractor 3, an A/D converter 4 a low-pass filter 5 and a limiter 26 which limits the output voltage of the low-pass filter 5 so that the DC voltage 103 to be superposed on the input signal P by subtractor 3 is limited in a predetermined range of ±L less than ±d. Accordingly, even when the input P to subtractor 3 decreases to zero volt upon interruption of the input P, the input 102 to the A/D converter 4 becomes +L or -L. Where a predicted maximum drift including the DC component variation of a 4-value input signal is assumed to be +D, no initial condition that forms an abnormal pull-in phenomenon will occur if the level of L is selected to satisfy a relation d ≧(D+L). The limiter 6 may have any well known construction and by limiting the output range thereof to satisfy the condition described above in which the output range is less than the discriminating level spacing d, a DC voltage control circuit freed from abnormal pull-in phenomenon can readily be obtained. Since, under the normal operation state, the DC drift component ±D must be compensated for by the DC voltage 103 to be superposed, the relation L≧D. Accordingly, D≦d/2 is of course required and the permissible range of the DC drift should be 1/2 of the discriminating level spacing d in both positive and negative directions. Accordingly, the discriminating level spacing of the A/D converter should be selected to satisfy the condition described above from a predictable drift level. 
     As described above, according to a DC voltage control circuit embodying the invention, it is possible to resume the normal operation irrespective of the initial condition without resulting in any abnormal pull-in phenomenon even when the input signal is interrupted. Thus preventing regeneration error caused by the abnormal pull-in phenomenon. 
     Practically, the DC voltage control circuit of the present invention described previously are preferably incorporated in demodulation apparatus for obtaining data signals from 4-PSK wave, or 64 QAM wave. 
     FIG. 8 shows an embodiment of demodulation apparatus of the invention adapted for demodulation of 4 PSK waves. A DC voltage control circuit 200a is constituted by control signal generators 9&#39; and 9a&#39; and A/D converters 4&#39; and 4a&#39; and subtractors 3 and 3a respectively associated the generators 9&#39; and 9a&#39;. Each of the control signal generators 9&#39; and 9a&#39; has a similar construction to the generator 9 in FIG. 3 except that the number of inputs to an AND gate circuit 6&#39; and a NOR gate circuit 7&#39; is two. Thus, Data signals X 1  standing for data 1 and X 2  from the A/D converter 4&#39; are applied to AND gate circuit 6&#39; via terminals H 1  and H 2  and to the NOR gate circuit 7&#39; via terminals L 1  and L 2  in the control signal generator 9&#39;. Data signals Y 1  standing for data 2 and Y 2  from the A/D converter 4a&#39; are applied to the control signal generator 9a&#39; having the same construction as the generator 9&#39;. The same demodulation circuit 300 as that of FIG. 1 is used, whereby the carrier synchronizing circuit 19 of the demodulation circuit 300 is responsive to data signals X 1 , X 2  Y 1  and Y 2  from the DC voltage control circuit 200a via terminals C 1  to C 4  to produce the reference carrier signal applied via terminal C 5  to the demodulator 2. 
     FIG. 9 shows an embodiment of demodulation apparatus of the invention adapted for demodulation of 64 QAM waves, comprising a DC voltage control circuit 200b and the demodulation circuit 300. A control signal generators 9&#34; and 9a&#34; have an increased number of input terminals corresponding to an increased number of data signals from A/D converters 4&#34; and 4a&#34;, which convert the outputs of the subtractors 3 and 3a into the four digital signals, respectively.