Abstract:
A delay circuit and a plurality of accepting circuits are comprised. The input signal supplied from exterior is delayed for a predetermined length of time by the delay circuit, and then it is distributed and output to the plurality of the receiver circuits. The delay time of the delay circuit is adjusted to optimize an accepting timing to an input signal by a clock signal in each of the accepting circuit. The each accepting circuit reliably accepts the delayed input signal respectively in synchronization with a clock signal. Therefore, it is unnecessary to respectively provide a delay circuit in the plurality of the accepting circuits. As a result, the plurality of accepting circuits can reliably accept input signals without enlarging a circuit scale. A plurality of delay circuits, a plurality of accepting circuits, and an operating circuit are comprised. The delay circuit receives a plurality of input signals, and outputs each of the delayed input signals respectively to the plurality of accepting circuits. The accepting circuit accepts the delayed input signals in synchronization with a clock signal. More than one of the delayed input signals are supplied to the operating circuit to perform a logic operation. The delay time of the each delay circuit, for example, is in accordance with the supplying timing to the input signal supplied to the operating circuit. As a result, the operating circuit performs the logic operation with a sufficient timing margin.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to semiconductor integrated circuits, and more particularly to a semiconductor integrated circuit which operates so as to accept input signals in synchronization with a clock signal.  
           [0003]    2. Description of the Related Art  
           [0004]    In general, semiconductor integrated circuits are broadly classified into logic LSIs, such as a microcomputer, and memory LSIs, such as a DRAM. The microcomputer has been widely known as a semiconductor integrated circuit which operates in synchronization with a clock. On the other hand, in the memory LSIs, an SDRAM (Synchronous DRAM) or the like operating in synchronization with a clock has been developed.  
           [0005]    In the SDRAM, an interfacing circuit is operated at high speed in synchronization with a clock signal supplied from exterior, so that writing or reading data at high speed is made possible while timing margins are kept.  
           [0006]    [0006]FIG. 1 shows the block diagram of an input interfacing circuit  1  in the semiconductor integrated circuit of this kind. The input interfacing circuit  1  includes a clock buffer  2 , a plurality of input buffers  3   a,    3   b,    3   c,  and a plurality of input signal accepting circuits  4   a,  6     4   b,    4   c.  Each of the input signal accepting circuits  4   a,    4   b,    4   c includes a latch  5 . The clock buffer  2  is supplied with a clock signal CLK from exterior of a chip. This clock buffer  2  decides the signal level of the clock signal CLK, converts the clock signal CLK into an internal clock signal CLKIN of high level or low level, and outputs the internal clock signal CLKIN to the respective input signal accepting circuits  4   a,    4   b,    4   c.  The input buffers  3   a,    3   b,    3   c  are respectively supplied with input signals S 1 , S 2 , S 3  from exterior of the chip. These input buffers  3   a,    3   b,    3   c  decide the signal levels of the input signals S 1 , S 2 , S 3 , convert the input signals S 1 , S 2 , S 3  into internal signals SIN 1 , SIN 2 , SIN 3  of high level or low level, and output the internal signals SIN 1 , SIN 2 , SIN 3  to the input signal accepting circuits  4   a,    4   b,    4   c,  respectively. The latches  5  accept the internal signals SIN 1 , SIN 2 , SIN 3  in synchronization with the edge of the internal clock signal CLKIN, and output accepted signals SIN 1 A, SIN 2 A, SIN 3 A to a controlling circuit  6 , or the like. within the chip, respectively. In the figure, lines indicated by arrows denote wiring patterns, and the directions of the arrows denote the directions in which the signals are transmitted.  
           [0007]    In the input interfacing circuit  1  described above, ordinarily the input buffers  3   a,    3   b,    3   c  are arranged near pads for receiving the signals from exterior and are dispersed on the chip. In contrast, the input signal accepting circuits  4   a,    4   b,    4   c  are arranged at the predetermined position on the chip. Therefore, the wiring patterns which are respectively laid to transmit the internal signals SIN 1 , SIN 2 , SIN 3  between the input buffers  3   a,    3   b,    3   c  and the input signal accepting circuits  4   a,    4   b,    4   c  can not have the same lengths. By way of example, the wiring pattern for transmitting the internal signal SIN 1  is the shortest, and the wiring pattern for transmitting the internal signal SIN 3  is the longest. Since the propagation delay time of each signal is proportional to the length of the wiring pattern, the internal signals SIN 1 , SIN 2 , SIN 3  are respectively supplied to the input signal accepting circuits  4   a,    4   b,    4   c  at timings different from one another.  
           [0008]    As a result, the timings of the respective latches  5  for accepting the internal signals SIN 1 , SIN 2 , SIN 3  shift as shown in FIG. 2. In the example of FIG. 2, the signal in which a timing margin for a set-up time tS is the smallest is the internal signal SIN 3 , and the signal in which a timing margin for a hold time tH is the smallest is the internal signal SIN 1 . Here, the “set-up time tS” is the specification of the minimum time in which the input signal needs to be settled before the rise of the clock signal CLK, and the “hold time tH” is the specification of the minimum time in which the input signal needs to be held after the rise of the clock signal CLK. Besides, in general, the ratings of external input terminals for the set-up time tS and the hold time tH are specified by the worst value of all input signals. For this reason, when the accepting timings of the internal signals SIN 1 , SIN 2 , SIN 3  fluctuates, the timing margins of the external input terminals for the set-up time tS and the hold time tH become short.  
           [0009]    The specifications of the set-up time tS and the hold time tH need to be strictened more as the frequency of the clock signal CLK becomes higher. In the SDRAM of high speed operation, therefore, the input signal accepting circuits  4   a,    4   b,    4   c  are respectively furnished with delay circuits  7   a,    7   b,    7   c  on the input sides of the latches  5  as shown in FIG. 3, thereby to lower the fluctuation of the timings of the internal signals SIN 1 , SIN 2 , SIN 3 . In the figure, the sizes of the delay circuits  7   a,    7   b,    7   c  express the lengths of delay times. The delay circuits  7   a,    7   b,    7   c  are respectively adjusted in accordance with the delays of the internal signals SIN 1 , SIN 2 , SIN 3  attributed to the unequal lengths of the wiring patterns, and the timings at which the internal signals SIN 1 , SIN 2 , SIN 3  are respectively transmitted to the latches  5  are set same. In consequence, the set-up times tS and hold times tH of all the internal signals SIN 1 , SIN 2 , SIN 3  are equalized.  
           [0010]    Meanwhile, in an SDRAM or the like, the combinations of the signal levels of a plurality of input signals received in synchronization with a clock signal CLK are decided as a plurality of controlling commands, by which an internal circuit is controlled.  
           [0011]    As shown in FIG. 4, the input interfacing unit  1  of the SDRAM of this type is formed with a decoder  8  which receives accepted signals SIN 1 A, SIN 2 A, SIN 3 A output from respective latches  5 , and which outputs a command signal CMD.  
           [0012]    With the circuit shown in FIG. 4, the output of the command signal CMD delays because the internal signals SIN 1 A, SIN 2 A, SIN 3 A accepted by the corresponding latches  5  are decoded by the decoder  8 . As a result, the operation of a controlling circuit  6  delays, and an access time, or the like. cannot be enhanced. In order to quicken the output of the command signal CMD, internal signals SIN 1 , SIN 2 , SIN 3  before being accepted by the latches  5  should be decoded.  
           [0013]    Each of FIGS. 5 and 6 shows the construction of the principal parts of an input interfacing unit  1  which serves to decode the internal signals SIN 1 , SIN 2 , SIN 3  before being accepted by the latches  5 , and which has been thought out by the inventor of the present invention.  
           [0014]    The input interfacing unit  1  shown in FIG. 5 is formed with a command accepting unit  9  which includes a decoder  10 , a delay circuit  7   d  and a latch circuit  5 . The decoder  10  receives the internal signals SIN 1 , SIN 2 , SIN 3 , and outputs a command signal CMD to the delay circuit  7   d.  The delay circuit  7   d  outputs the delayed command signal to the latch circuit  5 . The latch circuit  5  accepts the delayed command signal CMD in synchronization with an internal clock signal CLKIN, and outputs the accepted signal to the controlling circuit  6  as a command signal CMD 1 . Here, the delay circuit  7   d  is a circuit for adjusting the timings of the command signal CMD and the internal clock signal CLKIN which are supplied to the latch circuit  5 .  
           [0015]    The input interfacing unit  1  shown in FIG. 6 is formed with a command accepting unit  11  which includes delay circuits  7   e,    7   f,    7   g,  a decoder  10  and a latch circuit  5 . The decoder  10  receives the internal signals SIN 1 , SIN 2 , SIN 3  through the delay circuits  7   e,    7   f,    7   g,  respectively, and outputs a command signal CMD to the latch circuit  5 . The latch circuit  5  accepts the command signal CMD in synchronization with an internal clock signal CLKIN, and outputs the accepted signal to the controlling circuit  6  as a command signal CMD 1 .  
           [0016]    It is added that the input interfacing units  1  shown in FIGS. 5 and 6 are not known yet.  
           [0017]    With the input interfacing unit  1  shown in FIG. 5, the command signal CMD has its width W narrowed by the decoder  10  as shown in FIG. 7. This incurs the problem that the timing margins of the command signal CMD for the set-up time tS and the hold time tH become small in the latch circuit  5 .  
           [0018]    On the other hand, with the circuit construction shown in FIG. 6, the command latch  11  is formed with the plurality of delay circuits  7   e,    7   f,    7   g.  The input interfacing unit  1  requires delay circuits for adjusting the timings of the respective latches for the input signals, besides the delay circuits  7   e,    7   f,    7   g.  This results in the problem that the number of the delay circuits increases to enlarge the circuit scale. The enlargement of the circuit scale leads to that of a chip size. Since the enlargement of the chip size directly affects production costs, it exerts serious influence especially on the memory LSI such as DRAM.  
         SUMMARY OF THE INVENTION  
         [0019]    An object of the present invention is to provide a semiconductor integrated circuit which can reliably receive input signals without enlarging the circuit scale.  
           [0020]    Another object of the present invention is to provide a semiconductor integrated circuit where an internal circuit can be quickly and reliably operated.  
           [0021]    Still another object of the present invention is to set an optimal delay time of an input signal.  
           [0022]    According to one of the aspects of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit comprises a delay circuit and a plurality of receiver circuits. The input signal supplied from exterior is delayed for a predetermined length of time by the delay circuit, and then it is distributed and output to the plurality of the receiver circuits. The delay time of the delay circuit is set so that a receiving timing of an input signal received in synchronization with a clock signal is optimized in each of the receiver circuits. Each receiver circuit reliably receives the delayed input signal respectively in synchronization with a clock signal.  
           [0023]    Therefore, it is unnecessary to provide a delay circuit in each of the plurality of receiver circuits. As a result, the plurality of receiver circuits can reliably receive the input signals without enlarging the circuit scale. When there is a need to adjust the delay time of the input signals, only one of the delay circuits needs to be changed.  
           [0024]    Generally, in the semiconductor integrated circuit, the delay circuit is constructed by combining a resistor and a capacitor whose sizes are designed according to the lengths and the sizes of wirings, diffusion layers and insulators. This often results in the enlargement of the layout size of a delay circuit as compared to other circuits. The present invention makes it possible to reduce the number of the delay circuits so that the size of each delay circuit can be also be reduced as well as the size of the chip.  
           [0025]    According to another aspect of the semiconductor integrated circuit in the present invention, switching the ON/OFF state of a switch provided in the delay circuit enables the transmission path of the input signal to change and its delay time to be adjusted. Therefore, when it is necessary to adjust the delay time of the input signal, only the switch needs to be changed.  
           [0026]    According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit comprises a plurality of delay circuits, a plurality of receiver circuits, and an operating circuit. The delay circuit receives a plurality of input signals, and respectively outputs each of the delayed input signals to the plurality of receiver circuits. The receiver circuit receives the delayed input signals in synchronization with a clock signal. More than one of the delayed input signals are supplied to the operating circuit to perform a logic operation. The delay time of each delay circuit, for example, is set in accordance with the supplying timing to the input signal supplied to the operating circuit. As a result, the operating circuit performs the logic operation with a sufficient timing margin, and the timing margin between the input signals supplied to the operating circuit does not fluctuate, even when the delay time of each delay circuit is relatively shifted. By relatively shifting the delay time of each delay circuit, each receiver circuit becomes capable of reliably receiving the delayed input signal respectively in synchronization with a clock signal. Consequently, the delay circuit is able to supply input signals to both the operating circuit and the receiver circuit at an optimal timing.  
           [0027]    According to another aspect of the semiconductor integrated circuit in the present invention, the logical operating circuit is constructed as a command decoder and it comprises a command signal receiver circuit, which receives a command signal output from the command decoder in synchronization with a clock signal.  
           [0028]    The command decoder directly receives the input signals delayed by the delay circuits and outputs a command signal controlling the operations of internal circuits. The command signal receiver circuit reliably receives a wide command signal output from the command decoder in synchronization with a clock signal. Since the command signal receiver circuit receives the command signal decoded by the command decoder, an early start can be made in the operations of the internal circuits. Besides, there can be a plurality of command decoders and there can be a common delay circuit between the command decoders, so that the number of the delay circuits is further reduced to also reduce the size of each delay circuit as well as the size of the chip.  
           [0029]    According to another aspect of the semiconductor integrated circuit in the present invention, switching the ON/OFF state of the switch enables the transmission path of the input signal to change and its delay time to be adjusted. Therefore, the optimal delay time of the each delay circuit can be set. When it is necessary to adjust the delay time of the input signal, only the switch needs to be changed. The layout data of the elements of the delay circuit other than the switch is made common between each other, so that the layout designing time may be shortened.  
           [0030]    The delay time of the each delay circuit is adjusted so that the supply timings to the command decoder are equal between each input signal. This prevents the pulse width of the command decoder from becoming narrower so that the internal circuits can be reliably operated. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0031]    The nature, principle, and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by identical reference numbers, in which:  
         [0032]    [0032]FIG. 1 is a block diagram showing the construction of an input interfacing unit in the prior art semiconductor integrated circuit;  
         [0033]    [0033]FIG. 2 is a timing chart showing the timings at which internal signals are accepted in the prior art;  
         [0034]    [0034]FIG. 3 is a block diagram showing the construction of another input interfacing unit in the prior art semiconductor integrated circuit;  
         [0035]    [0035]FIG. 4 is a block diagram showing the construction of an input interfacing unit in the prior art semiconductor integrated circuit including a command decoder;  
         [0036]    [0036]FIG. 5 is a block diagram showing the construction of the principal parts of an input interfacing unit thought out by the inventor of the present invention;  
         [0037]    [0037]FIG. 6 is a block diagram showing the construction of the principal parts of another input interfacing unit thought out by the inventor;  
         [0038]    [0038]FIG. 7 is a timing chart showing the timing at which a decoded signal is accepted in the input interfacing unit shown in FIG. 5;  
         [0039]    [0039]FIG. 8 is a block diagram showing the basic principles of the first embodiment of a semiconductor integrated circuit according to the present invention;  
         [0040]    [0040]FIG. 9 is a block diagram showing the first embodiment of a semiconductor integrated circuit according to the present invention;  
         [0041]    [0041]FIG. 10 is a block diagram showing the construction of the principal parts of an input interfacing unit in FIG. 9;  
         [0042]    [0042]FIG. 11 is a circuit diagram showing the details of a clock buffer in FIG. 10;  
         [0043]    [0043]FIG. 12 is a circuit diagram showing the details of each of input buffers in FIG. 10;  
         [0044]    [0044]FIG. 13 is a circuit diagram showing the details of delay circuits in FIG. 10;  
         [0045]    [0045]FIG. 14 is a circuit diagram showing the details of each of latches and a command latch in FIG. 10;  
         [0046]    [0046]FIG. 15 is a circuit diagram showing the details of a command decoder in FIG. 10;  
         [0047]    [0047]FIG. 16 is a timing chart showing the decoding timings of internal signals and the accepting timing of a decoded signal; and  
         [0048]    [0048]FIG. 17 is a block diagram showing the second embodiment of the semiconductor integrated circuit according to the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0049]    Now, the embodiments of the present invention will be described with reference to the drawings.  
         [0050]    [0050]FIG. 8 is a block diagram showing the basic principles of the first embodiment of a semiconductor integrated circuit according to the present invention.  
         [0051]    The semiconductor integrated circuit includes a plurality of delay circuits  39  each having switches S, and a plurality of receiver circuits  41 ,  43 . A plurality of input signals IN 1 , IN 2  supplied from exterior are delayed predetermined time periods by each delay circuit  39 , and the delayed signals are distributed and output toward the plurality of accepting circuits  41 ,  43 . The transmission path of each of the input signals IN 1 , IN 2  is altered by changing the ON/OFF states of the switches S included in each delay circuit  39 , whereby the delay time is adjusted.  
         [0052]    Besides, the receiver circuit  43  includes a logic operating circuit  45  and a command signal receiver circuit  46 . The delayed input signals IN 1 , IN 2  (in general, numbering two or more) are supplied to the logical operating circuit  45  so as to perform a logic operation. In this example, the logical operating circuit  45  is constructed as a command decoder. The command decoder  45  directly receives the input signals IN 1 , IN 2  delayed by the delay circuits  39 , and outputs a command signal CMD for controlling the operations of internal circuits  23 ,  25 . The command signal receiver circuit  46  receives the command signal CMD output from the command decoder  45 , in synchronization with a clock signal CLK.  
         [0053]    [0053]FIG. 9 shows the first embodiment of the semiconductor integrated circuit according to the present invention.  
         [0054]    The semiconductor integrated circuit of this embodiment is formed on a silicon substrate as an SDRAM by using CMOS process technology.  
         [0055]    The SDRAM includes an input interfacing unit  21 , a controlling unit  23  and two memory core units  25 . The input interfacing unit  21  is configured of input units  27  arranged as two divided portions, and an accepting unit  29  arranged substantially in the center of a chip. The controlling unit  23  and the memory core units  25  correspond to the internal circuits ( 23 ,  25  in FIG. 8). Each of the input units  27  includes a plurality of pads  31  (which correspond to pads  31   a,    31   b,    31   c,    31   d  to be mentioned below), and a plurality of input circuits  33  (which correspond to input circuits  33   a,    33   b,    33   c,    33   d  to be mentioned below). In FIG. 9, lines indicated by arrows denote wiring patterns, and the senses of the arrows denote the directions in which signals are transmitted.  
         [0056]    [0056]FIG. 10 is a block diagram showing the construction of the principal parts of the input interfacing unit  21 . In the figure, only three major input signals are illustrated.  
         [0057]    Each of the input units  27  is formed with the pads  31   a,    31   b,    31   c  and  31   d  which receive a clock signal CLK, a chip select signal ICS, a row address strobe signal/RAS and a column address strobe signal /CAS from exterior, respectively. The pads  31   a,    31   b,    31   c,    31   d  are respectively connected to the corresponding input circuits  33   a,    33   b,    33   c,    33   d.  The input circuit  33   a  includes a clock buffer  35 . The clock buffer  35  decides the signal level of the clock signal CLK supplied through the pad  31   a,  converts the clock signal CLK into an internal clock signal CLKIN of high level or low level, and outputs the internal clock signal CLKIN to the accepting unit  29 .  
         [0058]    The input circuit  33   b  includes an input buffer  37  and a delay circuit  39   a.  Likewise, the input circuit  33   c  includes an input buffer  37  and a delay circuit  39   b.  Also, the input circuit  33   d  includes an input buffer  37  and a delay circuit  39   c.    
         [0059]    The input buffer  37  of the input circuit  33   b  decides the signal level of the chip select signal /CS supplied through the pad  31   b,  converts the chip select signal /CS into an internal signal CSX of high level or low level, and outputs the internal signal CSX to the delay circuit  39   a.  Further, the input buffer  37  of the input circuit  33   c  decides the signal level of the row address strobe signal /RAS supplied through the pad  31   c,  converts the row address strobe signal /RAS into an internal signal RASX of high level or low level, and outputs the internal signal RASX to the delay circuit  39   b.  Still further, the input buffer  37  of the input circuit  33   d  decides the signal level of the column address strobe signal /CAS supplied through the pad  31   d,  converts the column address strobe signal /CAS into an internal signal CASX of high level or low level, and outputs the internal signal CASX to the delay circuit  39   c.    
         [0060]    The delay circuits  39   a,    39   b,    39   c  delay the internal signals CSX, RASX, CASX for predetermined time periods and output the delayed signals to the accepting circuits ( 41  in FIG. 8) as delay signals CS 1 X, RAS 1 X, CAS 1 X, respectively. In the figure, the sizes of the delay circuits  39   a,    39   b,    39   c  express the delay times. The delay times are determined in accordance with the lengths of wiring patterns by which the respective delay signals CS 1 X, RAS 1 X, CAS 1 X are transmitted to a command decoder  45  to be explained later. Specifically, the delay times of each delay circuits  39   a,    39   b,    39   c  are set so as to equalize all of the totals as follows; (1) the total delay time of the delay signal CS 1 X, due to the wiring pattern, and of the delay circuit  39   a,  (2) the total delay time of the delay signal RAS 1 X, due to the wiring pattern, and of the delay circuit  39   b,  and (3) the total delay time of the delay signal CAS 1 X, due to the wiring pattern, and of the delay circuit  39   c.  Simultaneously, the delay times of each delay circuits  39   a,    39   b,    39   c  are set so that the set-up times tS and the hold times tH of the signals which are accepted by latches to be explained later can be satisfactorily ensured. In this embodiment, the length of the wiring pattern laid to the command decoder  45  is the longest for the delay signal CS 1 X and the shortest for the delay signal CAS 1 X.  
         [0061]    The accepting unit  29  includes the latches  41   a,    41   b,    41   c  which receive the delay signals CS 1 X, RAS 1 X, CAS 1 X, respectively, and a command accepting circuit  43  which receives all of these delay signals CS 1 X, RAS 1 X, CAS 1 X. The latches  41   a,    41   b,    41   c  and the command accepting circuit  43  correspond to the receiver circuits ( 41 ,  43  in FIG. 8).  
         [0062]    The latch  41   a  receives the internal clock signal CLKIN and the delay signal CS 1 X, and outputs internal signals CS 2 Z, CS 2 X to the controlling unit  23 . Further, the latch  41   b  receives the internal clock signal CLKIN and the delay signal RAS 1 X, and it outputs internal signals RAS 2 Z, RAS 2 X to the controlling unit  23 . Still further, the latch  41   c  receives the internal clock signal CLKIN and the delay signal CAS 1 X, and it outputs internal signals CAS 2 Z, CAS 2 X to the controlling unit  23 . Incidentally, the signals whose symbols end in “Z” are ones of positive logic, and the signals whose symbols end in “X” are ones of negative logic.  
         [0063]    The command accepting circuit  43  includes the command decoder  45  and a command latch  46 . The command latch  46  is the same circuit as each of the latches  41   a,    41   b,    41   c.  This command latch  46  corresponds to the command signal accepting circuit ( 46  in FIG. 8).  
         [0064]    The command decoder  45  receives the delay signals CS 1 X, RAS 1 X, CAS 1 X, and outputs a command signal CMD. The command latch  46  receives the internal clock signal CLKIN and the command signal CMD, and outputs command signals CMDZ, CMDX to the controlling unit  23 . By the way, the latches  41   a,    41   b,    41   c  and the command accepting circuit  43  are arranged at near positions within the accepting unit  29 .  
         [0065]    [0065]FIG. 11 shows the details of the clock buffer  35 . The clock buffer  35  is so constructed that two CMOS inverters  47 ,  49 , and an inverter row  51  consisting of two inverters are connected in cascade.  
         [0066]    The source of a pMOS (p-channel MOSFET)  47   b  in the CMOS inverter  47  is connected to a power supply VCC through a pMOS  47   a.  The gate of the pMOS  47   a  is connected to the ground VSS. In addition, the source of an nMOS (n-channel MOSFET)  47   c  in the CMOS inverter  47  is connected to the ground VSS through an nMOS  47   d.  The gate of the nMOS  47   d  is connected to the power supply VCC.  
         [0067]    The drain of an nMOS  49   c  in the CMOS inverter  49  is connected to the output node of this inverter through an nMOS  49   b.  The gate of the nMOS  49   b  is connected to the power supply VCC. The output node of the CMOS inverter  49  is connected to the inverter row  51 , which outputs the internal clock signal CLKIN.  
         [0068]    [0068]FIG. 12 shows the details of each input buffer  37 . The input buffer  37  is configured of two CMOS inverters  53 ,  55  connected in cascade, an inverter row  57  consisting of two inverters, and a controlling circuit  59  for inactivating this input buffer  37 . The input buffer  37  receives the one of the chip select signal ICS, row address strobe signal /RAS and column address strobe signal /CAS by means of the CMOS inverter  53 , and it outputs one of the internal signals CSX, RASX, CASX from the CMOS inverter  55 .  
         [0069]    The CMOS inverter  53  is the same as the CMOS inverter  47  of the clock buffer  35  shown in FIG. 11, except that the output node of the inverter row  57  is connected to the gate of an nMOS  53   a  located on the side of the ground VSS. The CMOS inverter  55  is the same as the CMOS inverter  49  of the clock buffer  35 . The input node of the inverter row  57  is supplied with an input activation signal ENZ. The input activation signal ENZ is a signal which becomes a high level during the normal operation of the SDRAM, and which becomes a low level in the low power consumption mode thereof.  
         [0070]    The controlling circuit  59  is configured of three pMOSs  59   a,    59   b,    59   c,  two nMOSs  59   d,    59   e,  and an inverter  59   f.  The drain of the pMOS  59   a  is connected to the output node of the CMOS inverter  53 , and the source thereof to the power supply VCC. In addition, the gate of the pMOS  59   a  is connected to the gate of the PMOS  59   b  and the drain of the PMOS  59   c.  The sources of the pMOSs  59   b,    59   c  are connected to the power supply VCC. Besides, the gate of the PMOS  59   c  is connected to the drain of the pMOS  59   b.  Further, the drains of the pMOSs  59   b,    59   c  are respectively connected to the drains of the nMOSs  59   d,    59   e.  The sources of the nMOSs  59   d,    59   e  are connected to the ground VSS. The output node of the inverter row  57  is connected to the gate of the nMOS  59   d.  Also, the output node of the inverter row  57  is connected to the gate of the nMOS  59   e  through the inverter  59   f.  The controlling circuit  59  has the function of applying the high level to the input of the CMOS inverter  55  through the pMOS  59   a  when the input activation signal ENZ is at the low level.  
         [0071]    [0071]FIG. 13 shows the details of the delay circuits  39   a,    39   b,    39   c.    
         [0072]    Each of the delay circuits  39   a,    39   b,    39   c  is a circuit in which a plurality of inverters  61   a,    61   b,    61   c,    61   d,    61   e  are connected in cascade through resistors R 1 , R 2  and switches S 1 -S 10 . The resistors R 1 , R 2  are formed of diffusion resistances, wire resistances of polysilicon, or the likes.  
         [0073]    In the delay circuit  39   a,  the output node of the inverter  61   a  is connected to the input node of the inverter  61   b  through the resistor R 1 . Next, the output node of the inverter  61   b  is connected to the input node of the inverter  61   c  through the switch S 1 . Subsequently, the output node of the inverter  61   c  is connected to the input node of the inverter  61   d  through the resistor R 2 . Finally, the output node of the inverter  61   d  is connected through the switch S 2  to the input node of the inverter row  61   e  in which two inverters are connected in cascade. The inverter row  61   e  outputs the delay signal CS 1 X. The output node of the inverter  61   b  is also connected to the input node of the inverter row  61   e  through the switch S 3 . Further, the input node of the inverter  61   c  is connected to the ground VSS through the switch S 4 . Still further, a capacitor part  62   a  is connected to the input node of the inverter  61   b  through the switch S 5 . Likewise, a capacitor part  62   b  is connected to the input node of the inverter  61   d  through the switch S 6 . Herein, the capacitor part  62   a  is configured of MOS capacitors C 1 , C 2 , in each of which the source and drain of an nMOS are connected to the ground VSS, and the switches S 7 , S 8 . On the other hand, the capacitor part  62   b  is configured of MOS capacitors C 3 , C 4  and the switches S 9 , S 10 . The gate of the MOS capacitor C 1  is connected to the ground VSS through the switch S 7 . Moreover, the gates of the MOS capacitors C 1 , C 2  are interconnected through the switch S 8 . Likewise, the gate of the MOS capacitor C 3  is connected to the ground VSS through the switch S 9 . Moreover, the gates of the MOS capacitors C 3 , C 4  are interconnected through the switch S 10 .  
         [0074]    Modifying the wiring pattern of a wiring mask for the uppermost layer makes it possible to turn ON or OFF each of the switches S 1 -S 10 . Each of the delay circuits  39   b,    39   c  is the same circuit as the delay circuit  39   a  except the ON and OFF states of the switches S 1 -S 10 . In this embodiment, in the delay circuit  39   a,  the switches S 1 , S 2 , S 5 , S 6  are turned OFF, and the switches S 3 , S 4 , S 7 , S 8 , S 9 , S 10  are turned ON. Also, in the delay circuit  39   b,  the switches S 1 , S 2 , S 6 , S 7  are turned OFF, and the switches S 3 , S 4 , S 5 , S 8 , S 9 , S 10  are turned ON. Besides, in the delay circuit  39   c,  the switches S 3 , S 4 , S 7 , S 9  are turned OFF, and the switches S 1 , S 2 , S 5 , S 6 , S 8 , S 10  are turned ON.  
         [0075]    That is, in the delay circuit  39   a,  neither of the capacitor parts  62   a,    62   b  is connected to the transmission path of the internal signal CSX. In the delay circuit  39   b,  only the capacitor part  62   a  is connected to the transmission path of the internal signal RASX. In the delay circuit  39   c,  both the capacitor parts  62   a,    62   b  are connected to the transmission path of the internal signal CASX. As a result, the delay times are in the relationship of (delay circuit  39   a )&lt;(delay circuit  39   b )&lt;(delay circuit  39   c ).  
         [0076]    Incidentally, the delay circuits  39   a,    39   b,    39   c  can set, at most,  18  sorts of delay times in accordance with the ON and OFF states of the switches S 1 -S 10 .  
         [0077]    [0077]FIG. 14 shows the details of each of the latches  41   a,    41   b,    41   c  and command latch  46 .  
         [0078]    Each of the latches  41   a,    41   b,    41   c  and command latch  46  is configured of a signal accepting unit  63  and a signal outputting unit  65 .  
         [0079]    In the signal accepting unit  63 , there are symmetrically arranged a latching unit  67  in which a pMOS  67   a  and nMOSs  67   b,    67   c  are connected in series, and a latching unit  69  in which a PMOS  69   a  and nMOSs  69   b,    69   c  are connected in series. An accepted signal INZ is output from the drains of the pMOS  67   a  and nMOS  67   b.  An accepted signal INX is supplied to the gates of the PMOS  67   a  and nMOS  67   b.  Likewise, the accepted signal INX is output from the drains of the PMOS  69   a  and nMOS  69   b.  The accepted signal INZ is supplied to the gates of the pMOS  69   a  and nMOS  69   b.  The sources of the pMOSs  67   a,    69   a  are connected to the power supply VCC. Further, the drains of pMOSs  63   a,    63   b,  the sources of which are connected to those of the pMOSs  67   a,    69   a,  are connected to the drains of the pMOSs  67   a,    69   a,  respectively. Still further, the output nodes of the inverters  65   a,    65   b  of the signal outputting unit  65  to be explained later are connected to the gates of the nMOSs  67   c,    69   c,  respectively.  
         [0080]    The internal clock signal CLKIN is supplied to the gates of the pMOSs  63   a,    63   b  and an nMOS  63   f.  The drains of nMOSs  63   c,    63   d,  the sources of which are connected to the ground VSS through the nMOS  63   f,  are connected to the drains of the nMOSs  67   c,    69   c,  respectively. Any of the delay signals CS 1 X, RAS 1 X, CAS and command signal CMD is supplied to the gate of the nMOS  63   c.  Also, any of the delay signals CS 1 X, RAS 1 X, CAS 1 X and command signal CMD as inverted by an inverter  63   e  is supplied to the gate of the nMOS  63   d.  The sources of the nMOSs  67   c,    69   c  are connected to the ground VSS through the nMOS  63   f.    
         [0081]    The signal accepting unit  63  has the functions of receiving the rising edge of the internal clock signal CLKIN and activating the latching units  67 ,  69 , accepting any of the delay signals CS 1 X, RAS 1 X, CAS 1 X and command signal CMD to output the accepted signals INX, INZ to the signal outputting unit  65 .  
         [0082]    The signal outputting unit  65  is configured of an outputting circuit  71  which consists of a pMOS  71   a  and an nMOS  71   b,  an outputting circuit  73  which consists of a PMOS  73   a  and an nMOS  73   b,  the inverters  65   a  and  65   b,  inverters  65   c  and  65   d  whose input nodes and output nodes are connected to each other, and inverters  65   e  and  65   f.  The gates of the pMOSs  71   a,    73   a  are supplied with the accepted signals INZ, INX, respectively. The sources of the pMOSs  71   a,    73   a  are connected to the power supply VCC. In addition, the output nodes of the inverters  65   b,    65   a  are connected to the gates of the nMOSs  71   b,    73   b,  respectively. Besides, the sources of the nMOSs  71   b,    73   b  are connected to the ground VSS. The output node of the outputting circuit  71  is connected to the input nodes of the inverters  65   c,    65   e.  On the other hand, the output node of the outputting circuit  73  is connected to the input nodes of the inverters  65   d,    65   f.  Thus, any of the internal signals CS 2 Z, RAS 2 Z, CAS 2 Z and the command signal CMDZ is output from the inverter  65   e.  Also, any of the internal signals CS 2 X, RAS 2 X, CAS 2 X and the command signal CMDX is output from the inverter  65   f.    
         [0083]    The signal outputting unit  65  has the functions of receiving the accepted signals INX, INZ in the outputting circuits  71 ,  73  and latching them in the inverters  65   c,    65   d,  and then outputting any of the internal signals CS 2 Z, RAS 2 Z, CAS 2 Z corresponding to the above accepted signals and the command signal CMDZ and any of the internal signals CS 2 X, RAS 2 X, CAS 2 X corresponding to the above accepted signals and the command signal CMDX.  
         [0084]    [0084]FIG. 15 shows the details of the command decoder  45 . The command decoder  45  is configured of inverters  45   a,    45   b  and a 3-input AND circuit  45   c.  The inverter  45   a  is supplied with the delay signal CS 1 X. The inverter  45   b  is supplied with the delay signal RAS 1 X. The input nodes of the AND circuit  45   c  are supplied with the outputs of the inverters  45   a,    45   b  and the delay signal CAS 1 X. The AND circuit  45   c  outputs the command signal CMD. In this embodiment, the command decoder  45  brings the command signal CMD to the high level when the chip select signal /CS, row address strobe signal /RAS and column address strobe signal /CAS supplied to the input interfacing unit ( 21  in FIG. 9) have the low level, low level and high level, respectively. Thus, the command latch  46  shown in FIG. 14 operates to latch the command signal CMD and to output the command signals CMDZ, CMDX to the controlling unit  23  (refer also to FIG. 10). Then, the controlling unit  23  executes a predetermined command input process.  
         [0085]    In the SDRAM described above, the input interfacing unit  21  accepts the signals supplied from exterior and outputs the accepted signals to the controlling unit  23  as will be explained below.  
         [0086]    The chip select signal /CS, row address strobe signal /RAS and column address strobe signal /CAS supplied from exterior are converted into the internal signals CSX, RASX and CASX by the input buffers  37  of the input circuits  33   b,    33   c  and  33   d  shown in FIG. 10, respectively. The internal signals CSX, RASX and CASX are respectively supplied to the delay circuits  39   a,    39   b  and  39   c.  Subsequently, the delay signals CS 1 X, RAS 1 X and CAS 1 X obtained by delaying the internal signals CSX, RASX and CASX the predetermined time periods are output from the delay circuits  39   a,    39   b  and  39   c.  As shown in FIG. 13, the delay times of the respective delay circuits  39   a,    39   b  and  39   c  can be finely adjusted by the switches S 1 -S 10 , and they are adjusted so that the timings of each delay signals CS 1 X, RAS 1 X and CAS 1 X arriving at the command decoder  45  may coincide. Consequently, the delay signals CS 1 X, RAS 1 X and CAS 1 X at the input node of the command decoder  45  have the same timings as shown in FIG. 16. Moreover, the set-up time tS and the hold time tH of the command signal CMD output from the command decoder  45  shown in FIG. 10, with respect to the internal clock signal CLKIN, are equalized. That is, the timing margins for the set-up time tS and the hold time tH are maximized. Thereafter, the command latch  46  outputs the accepted command signal CMD to the controlling unit  23  as the command signals CMDZ, CMDX. Since the command signal CMD is generated without the intervention of any of the latches  41   a,    41   b  and  41   c,  the output timing thereof is advanced. It is therefore possible to advance the control timing of the controlling unit  23 .  
         [0087]    Besides, the delay signals CS 1 X, RAS 1 X and CAS 1 X are supplied to the latches  41   a,    41   b  and  41   c  and accepted thereinto at the rise of the internal clock signal CLKIN, respectively. The latches  41   a,    41   b  and  41   c  are arranged at positions near the command decoder  45 . Therefore, the timing margins of each of the latches  41   a,    41   b  and  41   c  for the set-up time tS and the hold time tH with respect to the internal clock signal CLKIN are substantially equalized to the timing margins of the command latch  46 . To be exact, the timing of each of the delay signals CS 1 X, RAS 1 X and CAS 1 X shifts in correspondence with the number of gates (three stages) of the command decoder  45 , but the shifting magnitude lies within an allowable range. The accepted delay signals CS 1 X, RAS 1 X and CAS 1 X are respectively output to the controlling unit  23  as the internal signals CS 2 Z as well as CS 2 X, RAS 2 Z as well as RAS 2 X, and CAS 2 Z as well as CAS 2 X. Accordingly, the timing margins of the set-up times tS and the hold times tH to the latches  41   a,    41   b  and  41   c  and the internal clock signal CLKIN of the command latch  46  for are sufficiently given by the delay circuits  39   a,    39   b  and  39   c  respectively formed in the input circuits  33   b,    33   c  and  33   d.    
         [0088]    In the semiconductor integrated circuit constructed as described above, the internal signals CS 1 X, RAS 1 X and CAS 1 X delayed the predetermined time periods by the respective delay circuits  39   a,    39   b  and  39   c  are output to the command decoder  45 . Therefore, the timings at which the internal signals CS 1 X, RAS 1 X and CAS 1 X arrive at the command decoder  45  can be caused to coincide. As a result, the command decoder  45  can output the command signal CMD of large pulse width. Accordingly, the command latch  46  can accept the command signal CMD while the set-up time tS and the hold time tH with respect to the internal clock signal CLKIN are ensured sufficiently.  
         [0089]    The command signal CMD is generated in such a way that the internal signals CS 1 X, RAS 1 X and CAS 1 X output from the respective delay circuits  39   a,    39   b  and  39   c  are directly received by the command decoder  45 . Therefore, the output timing of the command signal CMD can be advanced to start the operation of the controlling unit  23  earlier.  
         [0090]    The latches  41   a,    41   b  and  41   c  and the command accepting circuit  43  are arranged at the near positions within the accepting unit  29 . Therefore, the timings at which the internal signals CS 1 X, RAS 1 X and CAS 1 X arrive at the respective latches  41   a,    41   b  and  41   c  and the command latch  46  of the command accepting circuit  43  become substantially coincident. In the respective latches  41   a,    41   b  and  41   c,  accordingly, the timing margins of the internal signals CS 1 X, RAS 1 X and CAS 1 X for the set-up times tS and the hold times tH with respect to the internal clock signal CLKIN can be substantially equalized to the timing margins of the command signal CMD in the command latch  46 . That is, the acceptance timings of both the latches  41   a,    41   b  and  41   c  and the command latch  46  can be ensured by only the delay circuits  39   a,    39   b  and  39   c  respectively formed in the input circuits  33   b,    33   c  and  33   d.    
         [0091]    The input signals (/CS, /RAS and /CAS) received from exterior are transmitted through the respective delay circuits  39   a,    39   b  and  39   c,  and the resulting signals are thereafter distributed to the respective latch circuits  41   a,    41   b  and  41   c  and the command accepting circuit  43  as the internal signals CS 1 X, RAS 1 X and CAS 1 X. Therefore, the number of the delay circuits  39   a,    39   b  and  39   c  can be minimized. In consequence, the size of the chip can be made smaller.  
         [0092]    The delay time of each of the delay circuits  39   a,    39   b  and  39   c  can be modified by changing the transmission path of the signal in accordance with the ON/OFF states of the switches S 1 -S 10 . Therefore, the optimum delay time can be set for each of the delay circuits  39   a,    39   b  and  39   c.  Even in a case where the adjustment of the delay time has become necessary, the delay time can be modified merely by changing the ON/OFF states of the switches S 1 -S 10 . Moreover, in case of making the layout designs of each delay circuits  39   a,    39   b  and  39   c,  the layout data of the elements other than the switches S 1 -S 10  can be made common, so that the layout designing time can be shorten.  
         [0093]    [0093]FIG. 17 shows the second embodiment of the semiconductor integrated circuit according to the present invention.  
         [0094]    In this embodiment, delay circuits  39   a,    39   b,    39   c  are respectively arranged within an accepting unit  29 . The remaining construction of this embodiment is the same as in the first embodiment described before.  
         [0095]    With this embodiment, effects similar to those of the first embodiment described before can be attained. Furthermore, since the delay circuits  39   a,    39   b,    39   c  are arranged within the accepting unit  29  in this embodiment, they can be located at near positions. As a result, the connections of the switches S 1 -S 10  can be easily confirmed on a wiring mask by way of example.  
         [0096]    Incidentally, the foregoing embodiments have been exemplified as adjusting the delay times in the way that the switches S 1 -S 10  of the delay circuits  39   a,    39   b,    39   c  are turned ON or OFF by changing the wiring patterns of the wiring masks at the uppermost layer. The present invention, however, is not restricted to such an aspect of performance. For example, the delay times may well be adjusted in the way that the switches S 1 -S 10  are formed of transmission gates made of MOS transistors, and that the transmission gates are controlled to turn ON or OFF. Alternatively, the delay times may well be adjusted in the way that the switches S 1 -S 10  are formed of fuses made of polysilicon or the like, and that some of the fuses are blown as are necessary. In the case where the switches S 1 -S 10  are formed of the fuses, the blowing of the fuses can be efficiently carried out by arranging the delay circuits  39   a,    39   b,    39   c  at the near positions as shown in the second embodiment.  
         [0097]    The foregoing embodiments have been exemplified as forming the delay circuits  39   a,    39   b,    39   c  by the use of the resistors R 1 , R 2  and the MOS capacitors C 1 , C 2 , C 3 , C 4 . The present invention, however, is not restricted to such an aspect of performance. For example, each delay circuit may well be formed by meandering a wiring pattern which has the same width as that of the wiring pattern of the internal clock signal CLKIN. In this case, the total of the lengths of the wiring pattern of each delay circuit and the wiring pattern of, for example, the delay signal CS 1 X laid to the latch  41   a  is equalized to the length of the wiring pattern of the internal clock signal CLKIN laid to the latch  41   a.  It is consequently possible to maximize the timing margins of the delay signal CS 1 X for the set-up time tS and the hold time tH with respect to the internal clock signal CLKIN.  
         [0098]    The invention is not limited to the above embodiments and various modifications may be made without departing from the spirit and the scope of the invention. Any improvement may be made in part or all of the components.