Abstract:
A nearly instantaneous companding processor uses variable precision block quantization for reducing the digital transmission rate of speech signals while at the same time maintaining a high quality signal in a digital communication system. The variable number of bits which are used to encode each sample is controlled as a function of the maximum sample magnitude in a block of N samples. This technique takes advantage of the amplitude probability density function of a speech signal to thereby reduce the quantizing noise without increasing the transmission rate.

Description:
BACKGROUND OF THE INVENTION 
     The present invention is related to a technique for reducing the digital transmission rate of speech signals while at the same time maintaining a high quality signal in a digital communications system. More particularly, the present invention is related to a &#34;nearly instantaneous companding&#34; (NIC) source coding technique which uses a rescaling protocol on a block of samples to reduce the transmission bit rate. Examples of such coding techniques may be found in &#34;Near Instantaneous Companding for Non-Uniformly Quantized PCM&#34;, by D. L. Duttweiler and D. G. Messerschmitt in IEEE Transactions on Communications, Vol. COM-24, No. 8, August 1976, at pages 843-864; and in &#34;Nearly Instantaneous Companding and Time Diversity as Applied to Mobile Radio Transmission&#34;, in International Conference on Communications, June 1975, San Francisco, at pages 40(12)-40(15). 
     With reference to a prior art compander shown in FIG. 1, digital amplitude samples from a speech signal are applied to an A-law or μ-law compander 10, where the digital amplitude samples are compressed according to the well known A-law or μ-law data compression schemes. The digitally companded samples are applied on the one hand to an N Sample Memory 15, while on the other hand applied to Maximum Sample Finder 20. The Maximum Sample Finder 20 determines the maximum value of the N digitally companded speech samples stored in memory 15, and delivers the maximum value on the one hand to quantizer 25 and on the other hand to Encoder 30. 
     Generally, the purpose of the NIC processor is to reduce the transmission bit rate of the digitally companded signal x(nT), where n is equal to 0, 1, 2 . . . , and T is equal to 125 μsec, for example. For convenience, the signal x(nT) will hereinafter be denoted x n . The reduction in transmission bit rate is accomplished by collecting the block of N samples in memory 15, determining the largest sample magnitude, S max , among the N samples to thereby select the quantizing range and uniformly quantizing the N samples in quantizer 25. 
     The quantizing step size Δ i  used in the quantizer 25 is given by 
     
         Δ.sub.i =S.sub.max /2.sup.p-1,                       (1) 
    
     where p represents the number of bits/sample used in the transmission of the sampled information. The samples quantized in accordance with the quantizing step Δ i  are then encoded in encoder 30. 
     In addition to the encoded digital speech samples, m bits are needed to transmit the protocol information, namely the value S max  or Δ i , to the receiver in order to decode that particular block of N samples. Thus, if S max  is transmitted, the protocol information bit rate for A-law companded signals having seven bits of precision (plus one sign bit) would be 7 S/N bits per second, where S is the sampling rate. The total transmission rate is defined as the sum of the nominal rate and the protocol rate. 
     Thus, the overall transmission bit rate can be reduced without an overall degradation in speech quality since the quantizing or signal measuring process automatically accommodates wide variations in the value of signal amplitudes. However, this method does not take advantage of the probability of occurrences in speech signal amplitudes, since it uses the same number of quantizer levels (2 p-1 ), wherein the number of quantizer levels per sample block will hereinafter be referred to as the ∓byte length&#34; regardless of the value of S max . Furthermore, the higher the value of S max , the larger the value of Δ i . Thus, the value of Δ i  affects the quantizing noise which increases with an increasing Δ i . Again, the value of p in equation (1) cannot be varied in accordance with the above mentioned technique. 
     SUMMARY OF THE PRESENT INVENTION 
     The present invention overcomes the shortcomings associated with the prior art device by taking advantage of the amplitude probability density function of the speech signal by varying the value of p as a function of S max . 
     By properly controlling the number of bits per sample, p, as a function of S max , it is possible to reduce the quantizing noise without increasing the transmission rate. Further, the present invention uses the same number of bits, m, as in the prior device for the protocol information. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a prior art NIC encoder; 
     FIG. 2 is a block diagram of the NIC processor having variable precision block quantization in accordance with the present invention; 
     FIG. 3 is a block diagram of the details of the NIC processor in accordance with the present invention; 
     FIG. 4 is a block diagram of the details of the M Value Detector 135 of FIG. 3; 
     FIG. 5 is a block diagram of the details of the encoder 140 of FIG. 3; 
     FIG. 6 is a block diagram of the details of the receiving circuitry in accordance with the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     With reference to FIG. 2, the speech amplitude samples are applied to the A-law or μ-law compander 10, which in turn provides digitally companded samples to N Sample Memory 35, on the one hand, and to S max  Finder 40, on the other hand. Variable Bit Number (or Byte Length) Quantizer 45 receives a first input from memory 35 and a second input from S max  Finder 40, and provides an output to a first input of Encoder 50, while S max  Finder 40 provides a second input to Encoder 50. The encoded signals from Encoder 50 are applied to buffer 55, which in turn provides the transmitter with a signal having a constant bit rate of R bits/S. 
     On the receive end, a buffer 60 receives the constant bit rate signal and provides samples to Decoder 65 as required. Decoder 65 decodes the signal to provide a digitally companded signal to the input of an A-law or μ-law compander 70. Compander 70 expands the samples to provide the reconstructed digital speech signal. 
     The NIC processor in accordance with the present invention will be described in more detail with reference to FIG. 3. Assuming A-law compression, the input to the processor is a digitally companded speech signal having 8 bit precision, 7 bits of magnitude plus one sign bit. In telephone speech transmission, these samples may typically arrive at an 8 kHz sampling rate. A &#34;block&#34; of N of the samples is stored in memory 35 and the maximum magnitude S max  of the samples is determined in S max  Finder 40. As shown in FIG. 3, the magnitude S j  of each speech sample is applied to a first latch 110 and to the first input of comparator 120. The value S m  stored in latch 110 will remain therein as long as its value is greater than the value of S j . When such is not the case, the comparator 120 provides an enable input to latch 110 to thereby substitute the S j  value for the S m  value, and the process recursively continues. Latch 115 accepts the final value in latch 110 when memory 35 is filled to thereby provide the value S max . 
     The value S max  is delivered to ROM 125, divider 130 and error correction encoder 142, the latter of which provides an error correction encoded value of S max  to encoder 140. The ROM 125 and divider 130 determine the quantizing step size Δ&#39; i  in accordance with the equation 
     
         Δ&#39;.sub.i =S.sub.max /2.sup.n i.sup.-1,               (2) 
    
     where n i  is the number of bits used to encode each sample in the ith block, the value of n i  varying from one block to another depending on the value of S max . By properly choosing the value of n i  as a function S max , the overall signal-to-quantizing noise ratio (SNR) can be considerably improved. 
     Table 1, below, has been found to provide a substantial improvement in the overall signal-to-quantizing noise ratio for speech signals transmitted over a telephone transmission system. With reference to FIG. 3 and Table 1, it is assumed that the A-law compander provides digitally companded signals having seven magnitude bits, A1-A7, and one sign bit A8. The three most significant magnitude bits, A5-A7, are applied to read only memory 125, the number of bits applied to ROM 125 depending upon the number of bits required to indicate all of the segments in the particular data compression scheme. For A-law companding, 8 segments are utilized, requiring a total of 3 bits to determine a segment. Thus, three bits corresponding to the segment number of the digital sample, namely bits A5 through A7, are applied to the ROM. 
     
                       TABLE 1______________________________________                        A-LawS.sub.max  A7       A6    A5     Segment No.                                 n.sub.i - 1______________________________________0           0     0        0        20           0     1        1        20           1     0        2        20           1     1        3        21           0     0        4        41           0     1        5        41           1     0        6        61           1     1        7        6______________________________________ 
    
     Read only memory 125 provides a lookup table in accordance with Table 1. Thus, for a bit pattern input for bits A7, A6 and A5 of &#34;000&#34;, ROM 125 provides a value of n i  -1=2, and so on. 
     The value of n i  -1 is applied to divider 130, along with S max  bits A1-A7, where the quantizing step level Δ&#39; i  is determined in accordance with the equation 2. Since the quantizing level Δ&#39; i  is equal to S max  divided by a power of 2 (2 2 , 2 4  or 2 6 ), the divider 130 may easily be implemented by a shift register, since a division by 2 can be achieved by a single shift of bits A1-A7. Thus, divider 130 need only accept the bit pattern A1 through A7 and shift the bit pattern a number of times equal to the value of n i  -1 to provide the quantizing step size. 
     The quantizing step size Δ&#39; i  is applied to M Value Detector 135 along with the magnitude of the companded amplitude sample S j , comprising bits A1 through A7, bit A8 being applied directly from memory 35 to encoder 140. The M Value Detector 135 is illustrated in more detail in FIG. 4, and operates to determine the minimum integer M such that M·Δ&#39; i  is greater than or equal to the magnitude of S j . With reference to FIG. 4, the magnitude of S j  is applied to one input of comparator 150, the other input receiving the output of multiplier 160. Multiplier 160, on the other hand, receives and multiplies the quantizing step size Δ&#39; i  and the integer M, initialized to a value of &#34;1&#34;. The comparator provides a signal on line 155 when the value S j  is greater than the value MΔ&#39; i  to thereby increment the M Counter 170. The M Value Detector 135 thereby iterates the comparison cycle until the value MΔ&#39; i  is greater than or equal to the magnitude of S j , at which point comparator 150 provides an output on line 165 to enable M counter 170 to output the value M to encoder 140. 
     From an inspection of equation 2, it can be seen that at a maximum, M can only attain a value equal to 2 n  i -1 , the maximum M being attained when the value S max  is applied to the M value detector. Thus, in the case where n i  -1 is equal to 4, the maximum value of M is 2 4  =16, the quantizing step size Δ&#39; i  providing 16 quantizing levels. Since the M counter 170 may contain a maximum count of 16, Encoder 140 encodes the value of M-1 (having values 0-15) to ensure that the transmitted value can be expressed in n i  -1 bits. 
     FIG. 5 is a block diagram of the details of encoder 140. The value M is delivered from M Value Detector 135 and applied to a subtractor 175 which acts to subtract the value &#34;1&#34; from M. The output of subtractor 175, having a value M-1, is applied to a first input of multiplexer 180, the sign bit A8 is concatenated thereto. The sequential values of M-1, each of the values having n i  bits including the associated sign bits, are applied to buffer 55 via multiplexer 180. Under the control of a control signal applied to the multiplexer 180, indicative of the start of a new block of N samples, the protocol information, including the error correction encoded value of S max  is applied to the buffer 55 as the first word in each block of N samples. The N Sample Memory 35 provides the control signal to the multiplexer 180 as soon as memory 35 is filled with N samples. After a predetermined period of time associated with the generation of the protocol information, as determined by Protocol Counter 182, control is returned to the other input of multiplexer 180 to provide the values M-1 to buffer 55, in a well known manner. Thereafter, the values S j  are clocked out of memory 35 and applied to M Value Detector 135. 
     The encoded sample value can be represented as 
     
         M-1=[(S.sub.j 2.sup.n i.sup.-1)-1]/S.sub.max,              (3) 
    
     where S j  is the companded digital sample value. Since n i  represents the number of bits used to encode the quantizer output, the average transmission rate R is given by ##EQU1## where s=sampling rate, m=number of bits used for protocol information, P i  =the probability that S max  falls in the ith segment of the companding law, and c=the number of segments (positive or negative) in the A-law or μ-law companding scheme. 
     Since the value of n i  can vary from one block to another, buffer 55 is required to provide the constant output bit rate for the transmitter, as illustrated in FIG. 2. 
     With reference to FIG. 6, the received data are applied to buffer 60 and unique word detector 205. Buffer 60 is of the first-in-first-out type and provides an output signal to shift register 210 and serial to parallel converter 215. Serial to parallel converter 215 provides a parallel input to ROM 220 via latch 225 and forward error correction circuitry 230, connected in series. FEC circuit 230 also provides an input to decoder 275. The output of ROM 220 provides an input to latch 235 and multiplier 240, the latter of which provides one input to comparator 245. The other input to comparator 245 is received from counter 250, which receives a clock signal and a clear pulse from the comparator. The output of the comparator provides an enable pulse to the serial parallel converter 215 via OR gate 225, which receives a second input from unique word detector 25 via counter 207. 
     The output of latch 235 is applied to a second comparator 260, the second input of which receives a signal from counter 265 controlled by the data clock. The output of comparator 260 provides a CLEAR pulse to shift register 210 and a LOAD pulse to latch 270. Latch 270 provides the signal M-1 to decoder 275, which in turn provides an eight bit input to A-law or μ-law compander 70, FIG. 2. 
     In operation, the received signal is applied to first-in-first-out buffer 60. Since the length of each block of N samples varies in accordance with the value of n i , special circuitry is required for extracting the protocol information from the data stream. Assuming that initialization has not yet occurred, such as when initially receiving a burst of information, synchronization is provided in a unique word detector 205, which operates in a well known manner to extract synchronization information from an incoming data burst. After a predetermined period of time as determined in counter 207, the decoding circuitry of FIG. 6 knows a priori that protocol information is about to be received from the first block of N samples. The counter 207 thus provides an enable signal to serial to parallel converter 215 via OR gate 255. The buffered data, corresponding to the protocol information is applied to serial to parallel converter 215 and loaded into latch 225. Since the protocol information includes the bit length information for each block of N samples, special care must be taken to ensure the proper reception of the protocol information. Thus, the value of S max , especially the three most significant bits thereof, are applied to error correction encoder 142, FIG. 3, and are accordingly decoded in forward error correction circuitry 230 to provide the value S max  to read only memory 220. 
     Read only memory receives the value S max  and produces the output n i  in accordance with Table 2 below. 
     
                       TABLE 2______________________________________S.sub.max  A7    A6           A5  n.sub.i______________________________________    0   0            0     3    0   0            1     3    0   1            0     3    0   1            1     3    1   0            0     5    1   0            1     5    1   1            0     7    1   1            1     7______________________________________ 
    
     ROM 220 thus provides a value of n i  equal to 3, 5 or 7 to latch 235 and multiplexer 240. The value of n i  applied to latch 235 is compared to the present count of counter 265 in comparator 260. Shift register 210 receives the serial output of buffer 60 and shifts the bits in accordance with the local bit rate clock to provide a parallel output to latch 270. After 3, 5 or 7 shifts in register 210, in accordance with the present value of n i , comparator 260 provides a LOAD pulse to latch 270 and a CLEAR pulse to shift register 210 and counter 265 in order to provide an n i  bit value of M-1 at the output of latch 270. Decoder 275 receives this value and decodes the value according to 
     
         S.sub.j =[2(M-1)+1]S.sub.max /2.sup.n i                    (5) 
    
     Thus, decoder can comprise any number of well known calculating devices. 
     The sign bit from the latch 270 is concatenated to the output of the decoder to provide 8 bit words representing samples S j  to the compander 70, FIG. 2. 
     After the block of N samples have been delivered from buffer 60, the protocol information heading the next block of N samples must be extracted in a likewise manner. The end of the present block of N samples is detected in comparator 245. The value N×n i  is produced in multiplier 240, which receives the value n i  from ROM 220, and multiplies the value by N to provide comparator 245 with the number of bits included in the N sample block. The number of bits in the block are applied to counter 250, and upon attaining a count equal to the value provided by multiplier 240, comparator 245 provides an ENABLE pulse to serial to parallel converter 215 via OR gate 255, such that the protocol information for the next block of N samples is loaded into converter 215. The ENABLE output from comparator 245 clears counter 250. 
     The operation of the NIC variable precision block quantizer in accordance with the present invention will be further described in the following example. Assume that S max  finder 40, FIG. 3, determines that the maximum sample, S max , in a block of N samples, has the bit pattern &#34;1010111&#34;, the left most bit corresponding to A7, the most significant magnitude bit, the right most bit, A1, corresponding to the least significant bit. The three bits &#34;101&#34;, corresponding to bits A7, A6, A5, are applied to ROM 125 where they are decoded according to Table 1. ROM 125 therefore provides the value &#34;4&#34; to divider 130, which operates to shift the input bit pattern A1-A7 four places to effect a division by 2 4  or 16. Thus, shifter 130 provides the value &#34;101.0111&#34; to M Value Detector 135 as the value of Δ&#39; i . Since N i  -1 is equal to 4, M can attain values of from 1 to 16 (2 4 ). The 4 bit value of M-1 for each speech sample S j  has sign bit A8 added thereto for delivery from encoder 140 to buffer 55 for transmission. 
     Now assume that a particular speech sample S j  has a value falling somewhere between 8/16 and 9/16(S max ). Counter 170, FIG. 4, will output a value of M=9 since this is the minimum value which will enable the output of counter 170. Encoder 140 receives the value 9, subtracts 1, encodes the signal 8 (1000), and concatenates the sign bit thereto for transmission. 
     At the receive end, the decoded signal is produced in accordance with equation 5. In accordance with equation 5 in the present example, the encoded value &#34;8&#34; (M-1) is multiplied by 2, and 1 is added to the result to yield 17. The value 17 is scaled by the value of S max  and divided by the value 2 n  i, the value of which is 32. Thus, the decoded value for the above example is 17/32 or 8.5/16(S max ), which places the decoded value approximately at the original value which was slightly higher than 1/2 the value of S max . 
     It can readily be seen that the NIC variable precision block quantizer in accordance with the present invention can readily be modified to accommodate a variety of operational characteristics. The choice of the value n i  -1 as a function of S max  can be chosen for any number of input signals and transmission media characteristics. Further, the number of bits employed to determine the value n i  -1 can vary according to the particular companding scheme employed. For A-law companded digital speech transmission at a transmission rate of 32 kbit/second, the processor in accordance with the present invention provides a 5 to 7 db improvement in signal-to-quantizing noise ratio compared to the existing NIC technique illustrated in FIG. 1. 
     The present invention thus produces a reduced rate of transmission without sacrificing speech quality and can be used in a single channel or digital speech interpolation environment. Further, the present invention is designed to directly receive a companded PCM input, and can be fully implemented using standard digital elements. The digital elements can be discrete, or a number of the elements in accordance with the present invention may be embodied in a single microprocessor. 
     Various changes, additions, and omissions of elements may be made within the scope and spirit of this invention. It is to be understood that the invention is not limited to specific details, examples and preferred embodiments shown and described herein.