Abstract:
An on-chip clock generation system used the Serial Interface in an on-chip JTAG facility to write bit patterns in a shift register. The bit patterns are applied to control inputs of a clock generation circuit whose clock outputs are varied in accordance with changes to the bit patterns. By using the same facility to provide JTAG and clock functions the output clocks provided by clock generation circuit on the chip can be varied without using additional pins or the output clocks themselves.

Description:
RELATED APPLICATIONS 
     The present invention, is related to the subject matter of the following commonly assigned U.S. Pat. No. 6,668,332 issued Dec. 23, 2003, entitled “FUNCTIONAL CLOCK OBSERVATION CONTROLLED BY JTAG EXTENSIONS”, which was filed concurrently with the present application, on the same day. 
     The content of the above-referenced copending patent application Ser. No. 09/504,367, is thus incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     The present invention relates to the problem area of clock generation circuitry, present inside a VLSI module (Chip). This clock generation circuitry needs to have control inputs that are capable of being varied in value, such that the effect that those varying values have on the clocks being generated, may be observed at the chip outputs. 
     BACKGROUND OF THE INVENTION AND PRIOR ART 
     The need and application for clock generation is ubiquitous. An exemplary, but not exclusive application can be found in a computing system wherein a processor utilizes a so-called system clock to communicate with external system devices such as DRAM, and synthesizes one or more internal clocks from the system clock to clock so-called functional units within the processor. It should be understood that a computing system is but one of many applications known to one skilled in the art. 
     By the way of further background, clock generation can be broadly categorized into either phase-locked loop (PLL) circuitry or delay line loop (DLL) circuitry. Pll circuitry generally takes reference signals, such as the system clock, compares it to the feedback signal, and generates an error signal in response thereto. The error signal drives a voltage controlled oscillator which produces an output signal. The output signal is also scaled to generate the feedback signal for comparison with the reference signal. The divisor setting of the divider sets the frequency ratio between the reference and output clock signals. 
     Although a review of the prior art related to test boundary scans was noted in the prior art, however no specific reference to the use of JTAG extensions, controlled and varied using JTAG design specific registers, was not found in any prior art reference. 
     SUMMARY OF INVENTION 
     The present invention relates to the problem area of clock generation circuitry, present inside a VLSI module (Chip). This clock generation circuitry needs to have control inputs that are capable of being varied in value, such that the effect that those varying values have on the clocks being generated, may be observed at the chip outputs. This invention solves the problem defined above by adding circuitry to part of the chip which implements IEEE Standard 1149.1 (IEEE Test Access Port and Boundary Scan Architecture, A.K.A. JTAG). Since JTAG circuitry uses clocking that is required to be independent of any other clocking domains on the chip, the requirement detailed above is met. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 This represents a description of the problem showing an ASIC (Chip). 
     FIG. 2 shows a JTAG (IEEE 1149.1) Overview within an ASIC (Chip) 
     FIG. 3 shows a representation of the solution of the problem as outlined in the Summary and defined in the Description of the Invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Before going into the detail description of the invention, it would be beneficial to define some of the acronyms employed throughout the Specifications. 
     ASIC This is the acronym for Application Specific Integrated Circuit. 
     JTAG defined as Joint Test Action Group. It is an alias for IEEE 1149.1, which is also known as IEEE Standard Test Access Port and boundary-Scan Architecture. 
     Pll is an acronym for Phase-Locked Loop. 
     VLSI is an acronym for Very Large Scale Integration. 
     DSR is an acronym for Design-Specific Register. 
     Multiplexer is a hardware circuit for selecting a single output from multiple inputs. It is a device for funneling several different streams od data over a common communications line. 
     Regarding the present invention, it relates to the problem area of clock generation circuitry, present inside a VLSI module (Chip). This clock generation circuitry needs to have control inputs that are capable of being varied in value, such that the effect that those varying values have on the clocks being generated, may be observed at the chip outputs. 
     This mechanism allows the optimum values for the clock generation control inputs to be determined by trying different input values, and observing the resulting generated clock signals in an iterative fashion. 
     The optimum values are the ones which cause the clock generation circuitry to produce the best quality clocks. An example of a quality measurement would be clock jitter. An example of clock generation logic that has such a requirement is a on-chip PLL circuit which has inputs which control aspects of the feedback loop in the PLL. 
     If the chip has spare input pins that would otherwise be unused, then providing the clock generation control inputs is a simple matter of connecting the control input to the input pins. Since this frequently is not the case it is necessary to multiplex functional chip signals with the clock signals. This allows a common set of chip output or input pins to be used for both normal functional signals, as well as the control input signals. 
     However, since clock signals being generated may not be operating correctly, as the control inputs are varied, it is necessary that the circuitry which provides the control inputs, be completely independent of the generated clock signals themselves. 
     In addition to the advantages outlined in the summary of the invention, by adding the clock control circuitry to part of the chip which implements IEEE Standard 1149.1 (IEEE Test Access Port and Boundary Scan Architecture, A.K.A. JTAG), the already existing chip input and output pins, which are used to provide the required JTAG signals, may also be used to access the clock generation control circuitry. This solves the problem without requiring any additional chip pins to be used for the clock generation control inputs. 
     The problem as noted in FIG. 3, is resolved by employing a JTAG design-specific data register (DSR). FIG.  3 . at location  304 , is added to the JTAG design. The outputs of this register form the set of signals used to control the clock generation circuitry. When the chip&#39;s reset input signal is asserted, DSR is reset to a set of nominal values that are the initial targeted values to cause the clock generation logic to produce good clocks. 
     To apply a new value to the clock inputs, a write is performed (via the JTAG interface) to the DSR with the targeted values. Any write to DSR causes the clock generation logic to perform an initialization sequence. At the end of the sequence, the clock generation logic will begin generating clocks, which may then be observed at chip outputs. Each candidate value for the clock control inputs is iterated through in the manner described above. Once the optimum setting (the one that produces the best quality clock value) is determined, the nominal value that the DSR takes on during chip functional reset is changed to be the optimum setting. 
     The invention will now be illustrated by several FIGS.,  1 ,  2  and  3 . Starting with_FIG. 1, which represents a problem description ASIC (Chip). The output clocks are noted at location  100 , the clock generation at  101 , the input clocks at location  103 , the reset at  104  and the control inputs at location  102 . 
     As noted earlier, control inputs affect quality of the output clocks, and control of the inputs  102 , must not be generated as a function of the output clocks at location  100 . Control inputs must be capable of being varied in an iterative fashion in order to allow affect on the output clock quality to be observed. This process may be used to empirically determine the control inputs at  102  settings which produce the most ideal output clocks. The input clock is located at  103 , the reset at  104 , and clock generation at  101 . 
     FIG. 2 Located at  200  represents a JTAG (EEE 1149.1) Overview of an ASIC CHIP. It shows the input into the chip at  201  and the output at  202 . The chip shows the scan instruction register at  203 , the parallel instruction register at  204 . The JTAG clock, the JATG mode select and the JTAG Reset are seen at  205  respectively. The JTAG instruction decode is seen at  206 , the scan data register select controls seen at  207 . The multiplexor is noted at location  208 . 
     FIG. 3 The figure represents the solution to the problem outline earlier in the Specifications. The solution is achieved without requiring any dedicated chip I/O signals. The process is performed as follows. Apply a value to the clock generator ( 301 ) control inputs by using the JTAG interface signals to write the desired pattern to the DSR at  304 . Any write to the DSR causes the latch to be set at location  300 . This causes the clock generation ( 301 ) logic to perform an initialization sequence at  303 . Following the initialization sequence, the clock generation logic will begin to generate functional clocks. Each candidate value for the clock control inputs is iterated through using the sequence described above. 
     The functional chip input Reset at location  301 , causes latch at  300  to reset, and chip outputs at  302 , to carry clock outputs. Any write to the DSR at  305 , causes the latch to be set, and the chip outputs to carry the output clocks  302 . The Design Specific Register is located at  304 . 
     While the invention has described with respect to a specific embodiment, it will be obvious to those skilled in this art that changes in both form and/or detail may be made without a departure from the scope and/or spirit of the invention.