Abstract:
A method of manufacturing a semiconductor device comprises the steps of: preparing a semiconductor substrate, the semiconductor substrate having first and second predetermined regions; forming a first field region surrounding the first predetermined region; forming a second field region surrounding the second predetermined region while a separating region exists between adjacent first and second field regions; forming a first insulation film on the semiconductor substrate; forming a resist pattern on the first insulation film, the resist pattern covering the first predetermined region and a part of the separating region; exposing the second predetermined region by etching the first insulation film using the resist pattern as a mask; forming a second insulation film on the second predetermined region; and forming gate electrodes on the first and second insulation films.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a method of manufacturing a semiconductor device, which in particular may have a high withstand voltage element and a low withstand voltage element mounted together on the same semiconductor substrate.  
         [0003]     2. Background Information  
         [0004]     In recent years, liquid crystal displays have prevailed in the fields of personal computers and televisions, and their rapid growth in these fields is remarkable. Moreover, as liquid crystal displays have come to be used in cellular phones, digital cameras etc, it is expected that there will be even more demands for them in the future.  
         [0005]     A conventional liquid crystal panel requires high voltage in order to be operated. Therefore, a driver LSI for driving the liquid crystal panel needs high withstand voltage MOS (metal-oxide semiconductor) transistors. On the other hand, a logic circuit for digital processing needs an advanced logic process in order to obtain processing speed.  
         [0006]     Generally, in the logic processor, low withstand voltage MOS transistors are used. As opposed to this, in the driver LSI, elements having both high withstand voltage MOS transistors and low withstand voltage MOS transistors mounted on the same semiconductor substrate are used.  
         [0007]     Examples of general types of semiconductor devices having high withstand voltage MOS transistors and low withstand voltage MOS transistors mounted together on the same semiconductor substrate are exhibited in Japanese Laid-Open Patent Application No. 2000-150665 (hereinafter to be referred to as Patent Reference 1) and Japanese Laid-Open Patent Application No. 2000-200836 (hereinafter to be referred to as Patent Reference 2).  FIG. 1A  and  FIG. 1B  are diagrams showing structures of a general type of conventional semiconductor device  900 .  
         [0008]      FIG. 1A  is a sectional view of the conventional semiconductor device  900  taken along a line I-I′, and  FIG. 1B  is an overhead diagram of the semiconductor device  900 . The I-I′ section of  FIG. 1A  is a section of the line I-I′ shown in  FIG. 1B . Here, the same reference numbers are used for the same structural elements.  
         [0009]     As shown in  FIG. 1A  and  FIG. 1B , the semiconductor device  900  has a high withstand voltage MOS transistor region  900 A and a low withstand voltage MOS transistor region  900 B. A MOS transistor formed in the high withstand voltage MOS transistor region  900 A (hereinafter to be referred to as high withstand voltage MOS transistor) has a gate oxide film  913   a  and a gate electrode  914  formed on a silicon substrate  911 , sidewall spacers  916  formed on two sides of the gate electrode  914 , and a pair of source/drain regions  915  sandwiching a region underneath the gate electrode  914  in the silicon substrate  911 . On the other hand, like the high withstand voltage MOS transistor, a MOS transistor formed in the low withstand voltage MOS transistor region  900 B (hereinafter to be referred to as low withstand voltage MOS transistor) has a gate oxide film  913   b  and a gate electrode  914  formed on the silicon substrate  911 , sidewall spacers  916  formed on two sides of the gate electrode  914 , and a pair of source/drain regions  915  sandwiching a region underneath the gate electrode  914  in the silicon substrate  911 .  
         [0010]     The high withstand voltage MOS transistor and the low withstand voltage MOS transistor are electrically separated from each other by a field oxide (a field oxide is also called an element isolating insulation film)  912  formed in the silicon substrate  911 .  
         [0011]     In the above structure, a boundary  900   a  between the high withstand voltage MOS transistor region  900 A and the low withstand voltage MOS transistor region  900 B is positioned on the field oxide  912 .  
         [0012]     Now, with reference to  FIG. 2A  to  FIG. 3B , a method of manufacturing the semiconductor device  900  according to prior art will be explained.  FIG. 2A  to  FIG. 3B  show manufacturing processes focusing attention on the section of the line I-I′ shown in  FIG. 1B .  
         [0013]     First, as shown in  FIG. 2A , field oxides  912  are formed in the p-type silicon substrate  911  using a well known STI (Shallow Trench Isolation) method for instance. By this arrangement, active regions and field regions are defined in the surface of the silicon substrate  911 .  
         [0014]     Next, by conducting a thermal oxidation treatment on the surface of the silicon substrate  911 , a gate oxide film  913  for the high withstand voltage MOS transistor is formed on the entire surface of the silicon substrate  911  as shown in  FIG. 2B . Here, the gate oxide film  913  is normally formed to a thickness which is sufficient to not be damaged by an operating voltage. Generally, the gate oxide film  913  is formed to the thickness of around 30 to 50 nm (nanometer) for instance.  
         [0015]     Next, by conducting a known photolithographic process, a resist pattern R 901  is formed only in the high withstand voltage MOS transistor region  900 A. Then, the gate oxide film  913  in the low withstand voltage MOS transistor region  900 B is removed by a known etching method while using the resist pattern R 901  as a mask. By this process, the gate oxide film  913 A which is a part of the gate oxide film  913  remains only in the high withstand MOS transistor region  900 A as shown in  FIG. 2C . The resist pattern R 901  remained on the gate oxide film  913 A is removed after the etching process is over.  
         [0016]     Next, by conducting a thermal oxidation treatment on the entire surface of the silicon substrate  911 , a gate oxide film  913 B for the low withstand voltage MOS transistor is formed in the low withstand voltage MOS transistor region  900 B as shown in  FIG. 2D . Here, the gate oxide film  913 B is normally formed to a thickness which is decided depending on the operating voltage and performance expected from the low withstand voltage MOS transistor. Generally, the gate oxide film  913 B is formed to a thickness of around 2 to 7 nm for instance.  
         [0017]     Next, polysilicon is deposited on the entire surface of the silicon substrate  911  on which the gate oxide films  913 A and  913 B are formed, and processed by a known photolithographic method and an etching method to form the gate electrode  914  on the gate oxide film  913 A in the high withstand voltage MOS transistor region  900 A and the gate electrode  914  on the gate oxide film  913 B in the low withstand voltage MOS transistor region  900 B. Then, while using the gate electrodes  914  as masks, an etch back process is done on the entire surface of the silicon substrate  911  to remove the gate oxide films  913 A and  913 B except for the parts underneath the gate electrodes  914 . By these processes, a structure shown in  FIG. 3A  can be obtained.  
         [0018]     Next, an insulation film such as a silicon oxide film or a silicon nitride film is formed on the entire surface of the silicon substrate  911  using a known CVD (Chemical Vapor Deposition) method, after which an etch back process according to a known etching technique is performed on the insulation film to form the sidewall spacers  916  on the sides ofthe gate electrodes  914  respectively, as shown in  FIG. 3B .  
         [0019]     Next, arsenic (As) ions are implanted into the silicon substrate  911  while using the field oxides  912 , gate electrodes  914  and the sidewall spacers  916  as masks, a pair of source/drain regions  915  are formed in the active region of each of the high withstand voltage MOS transistor region  900 A and the low withstand voltage MOS transistor region  900 B in a self-aligning manner, the pair of source/drain regions  915  being formed in a way sandwiching a region underneath the gate electrode  914  and the sidewall spacers  916 .  
         [0020]     Taking the processes described above, a semiconductor device having a low withstand voltage transistor and a high withstand voltage transistor formed on the same semiconductor substrate can be produced.  
         [0021]     However, in the above-described conventional manufacturing method, it has been noted as a problem that a step is produced in the upper part of the field oxide in the boundary between the high withstand voltage MOS transistor region and the low withstand voltage MOS transistor region. This is because in the etching process of  FIG. 2C , over etching to the extent of about several dozen percent of the thickness of the gate oxide film  913  is done for the purpose of preventing variations in thickness to be made in the gate oxide film  913 B after etching process. Due to such over etching, the upper part of the field oxide  912  which is not covered by the resist pattern R 901  is also etched as shown in  FIG. 2C . As a result, a step is formed in the upper part of the field oxide  912  in the boundary between the high withstand voltage MOS transistor region  900 A and the low withstand voltage MOS transistor region  900 B as can be seen in  FIG. 2C . Normally, this step is about 50 to 100 nm high, although it depends on the thickness of the gate oxide film  913 .  
         [0022]     Such a step can be a cause of defective printing in the photolithographic process in forming the gate electrode  914  in the later process, and can be a cause of etching residuals of the polysilicon film. In addition to that, since the field oxide  912  becomes thinner, leakages, for instance, between transistors and wirings may be caused (hereinafter to be referred to as inter-field leakage).  
         [0023]     In the above described way, when there is a step in the upper part of the field oxide, problems such as open, short, leakage, etc. can occur, which leads to a problem in which normal operation of the semiconductor device becomes difficult.  
         [0024]     In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved method of manufacturing a semiconductor device. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.  
       SUMMARY OF THE INVENTION  
       [0025]     It is therefore an object of the present invention to resolve the above-described problems and to provide a method of manufacturing a semiconductor device, which has a high withstand voltage element and a low withstand voltage element formed on the same semiconductor substrate and which does not form any step in a field oxide.  
         [0026]     In accordance with a first aspect of the present invention, a method of manufacturing a semiconductor device comprises the steps of: preparing a semiconductor substrate, the semiconductor substrate having first and second predetermined regions; forming a first field region surrounding the first predetermined region; forming a second field region surrounding the second predetermined region while a separating region exists between adjacent first and second field regions; forming a first insulation film on the semiconductor substrate; forming a resist pattern on the first insulation film, the resist pattern covering the first predetermined region and a part of the separating region; exposing the second predetermined region by etching the first insulation film using the resist pattern as a mask; forming a second insulation film on the second predetermined region; and forming gate electrodes on the first and second insulation films.  
         [0027]     In accordance with a second aspect of the present invention, a method of manufacturing a semiconductor device comprises the steps of: preparing a semiconductor substrate having first and second predetermined regions; forming a first element isolating insulation film encircling the first predetermined region; forming a second element isolating insulation film encircling the second predetermined region while a separating region exists between the first and second element isolating insulation films, the first and second element isolating insulation films being separated physically by the separating region; forming a first insulation film on the semiconductor substrate having the first and second element isolating insulation films; forming a protective film on the first insulation film; forming a resist pattern on the protective film, the resist pattern covering the protective film over the second predetermined region, and a part of the edge of the resist pattern being located over the separating region; exposing the first predetermined region and the first element isolating insulation film by etching the protective film and the first insulation film using the resist pattern as a mask; forming a second insulation film on the first predetermined region; exposing the second predetermined region and the second element isolating insulation film by etching the remaining protective film and the remaining first insulation film; forming a third insulation film on the second predetermined region; and forming gate electrodes on the second and third insulation films, respectively.  
         [0028]     In accordance with a third aspect of the present invention, a semiconductor device has a semiconductor substrate having first and second active regions, a first field region encircling the first active region, a second field region encircling the second active region, a separating region physically separating the first and second regions, gate insulation films formed on the first and second regions, and gate electrodes formed on the gate insulation films.  
         [0029]     These and other objects, features, aspects, and advantages of the present invention will become apparent to those skilled in the art from the following detailed description, which, taken in conjunction with the annexed drawings, discloses preferred embodiments of the present invention. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0030]     Referring now to the attached drawings which form a part of this original disclosure:  
         [0031]      FIG. 1A  and  FIG. 1B  are diagrams showing a structure of a semiconductor device  900  according to prior art;  
         [0032]      FIG. 2A  to  FIG. 2D  are diagrams showing processes of forming the semiconductor device  900  according to a prior art manufacturing method;  
         [0033]      FIG. 3A  and  FIG. 3B  are diagrams showing processes of forming the semiconductor device  900  according to the prior art manufacturing method;  
         [0034]      FIG. 4A  and  FIG. 4B  are diagrams showing a structure of a semiconductor device  1  according to a first embodiment of the present invention;  
         [0035]      FIG. 5A  to  FIG. 5C  are diagrams showing processes of forming the semiconductor device  1  according to a manufacturing method of the first embodiment of the present invention;  
         [0036]      FIG. 6A  to  FIG. 6C  are diagrams showing processes of forming the semiconductor device  1  according to the manufacturing method of the first embodiment of the present invention;  
         [0037]      FIG. 7A  and  FIG. 7B  are diagrams showing a structure of a semiconductor device  2  according to a second embodiment of the present invention;  
         [0038]      FIG. 8A  to  FIG. 8C  are diagrams showing processes of forming the semiconductor device  2  according to a manufacturing method of the second embodiment of the present invention;  
         [0039]      FIG. 9A  to  FIG. 9C  are diagrams showing processes of forming the semiconductor device  2  according to the manufacturing method of the second embodiment of the present invention; and  
         [0040]      FIG. 10A  and  FIG. 10B  are diagrams showing processes of forming the semiconductor device  2  according to the manufacturing method of the second embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0041]     Selected embodiments of the present invention will now be explained with reference to the drawings. It will be apparent to those skilled in the art from this disclosure that the following descriptions of the embodiments of the present invention are provided for illustration only and not for the purpose of limiting the invention as defined by the appended claims and their equivalents.  
       First Embodiment  
       [0042]     A first embodiment of the present invention will be described in detail with reference to the drawings.  
         [0043]     Structure  
         [0044]      FIG. 4A  is a sectional view of a semiconductor device  1  according to the first embodiment of the present invention taken along a line II-II′, and  FIG. 4B  is an overhead diagram showing the semiconductor device  1 . The II-II′ section of  FIG. 4A  is a section of the line II-II′ shown in  FIG. 4B . Here, the same reference numbers are used for the same structural elements.  
         [0045]     As shown in  FIG. 4A  and  FIG. 4B , the semiconductor device  1  has a high withstand voltage MOS transistor region  1 A and a low withstand voltage MOS transistor region  1 B which are both semiconductor elements. An active region AR in the high withstand voltage MOS transistor region  1 A is defined by being electrically separated from the other regions by field oxides  12 A which are field regions FR. Likewise, an active region AR in the low withstand voltage MOS transistor region  1 B is defined by being electrically separated from the other regions by field oxides  12   b  which are field regions FR.  
         [0046]     A high withstand voltage MOS transistor formed in the high withstand voltage MOS transistor region  1 A has a gate insulation film  13   a  and a gate electrode  14  formed on a silicon substrate  11 , sidewall spacers  16  formed on two sides of the gate electrode  14 , and a pair of source/drain regions  15  sandwiching a region underneath the gate electrode  14  in the silicon substrate  11 . On the other hand, like the high withstand voltage MOS transistor, a low withstand voltage MOS transistor formed in the low withstand voltage MOS transistor region  1 B has a gate insulation film  13   b  and a gate electrode  14  formed on the silicon substrate  11 , sidewall spacers  16  formed on two sides of the gate electrode  14 , and a pair of source/drain regions  15  sandwiching a region underneath the gate electrode  14  in the silicon substrate  11 .  
         [0047]     In the above structure, a p-type silicon substrate can be applied as the semiconductor substrate  11  for example. Furthermore, the field oxides  12 A and  12   b  can be formed using an STI method for instance. However, the method of forming the field oxides  12 A and  12   b  is not limited to the STI method, and can also be formed using a LOCOS (local oxidation of silicon) method for instance.  
         [0048]     The gate insulation film  13   a  in the high withstand MOS transistor region  1 A can be an insulation film such as a silicon oxide film for instance. The gate insulation film  13   a  should be formed to a thickness which is sufficient to not be damaged by an operating voltage, and such thickness may be around 30 to 50 nm for instance.  
         [0049]     On the other hand, the gate insulation film  13   b  in the low withstand MOS transistor region  1 B can be an insulation film such as a silicon oxide film for instance, as with the gate insulation film  13   a . A thickness of the gate insulation film  13   b  can be decided depending on the operating voltage and performance expected from the low withstand voltage MOS transistor, and it may be set to around 2 to 7 nm for instance. The gate insulation film  13   b  is usually thinner than the gate insulation film  13   a.    
         [0050]     The gate electrodes  14  in the high withstand voltage MOS transistor region  1 A and the low withstand voltage MOS transistor region  1 B can be a polysilicon film including predetermined impurities, and they may be 200 to 300 nm thick for instance.  
         [0051]     The sidewall spacers  16  formed on the sides of each gate electrode  14  can be insulation films such as silicon nitride films for instance. However, it is preferable that the sidewall spacers  16  are made of a material which can be etched selectively under predetermined conditions with respect to the gate insulation films  13   a  and  13   b , field oxides  12 A and  12   b , and the semiconductor substrate  11 . By choosing such material for the sidewall spacers  16 , it is possible to form the sidewall spacers  16  without having to form any resist patterns or the like for protecting the semiconductor substrate  11 , the sidewall spacers  16 , the field oxides  12 A and  12   b , the gate electrode  15  and so forth. For example, the sidewall spacers  16  can be formed without requiring any resist patterns or the like, under the conditions that the semiconductor substrate  11  is a silicon substrate, the field oxides  12 A and  12   b  are silicon oxide films, the gate insulation films  13   a  and  13   b  are silicon oxide films, the sidewall spacers  16  are silicon nitride films, and a mixed gas of CHF 3 , Ar and O 2  with a mixture ratio of about 50:100:1 is used as an etching gas for processing the silicon nitride film formed on the semiconductor substrate  11 .  
         [0052]     In the active region AR of each of the high withstand voltage MOS transistor region  1 A and the low withstand voltage MOS transistor region  1 B, a pair of source/drain regions  15  are formed in the regions except the region underneath the gate electrode  14  and the sidewall spacers  16 , and the source/drain regions  15  are formed in a way which sandwich this region underneath the gate electrode  14  and the sidewall spacers  16 . In case of manufacturing a MOS transistor in which an n-type channel is formed, the source/drain regions  15  can be formed by implanting impurities having an n-type conductivity to the extent that the dose amount becomes around 2.0 to 5.0×10 12 /cm 2 . Here, arsenic (As) ions, for instance, can be used as the n-type impurities. On the other hand, in case of manufacturing a MOS transistor in which a p-type channel is formed, the source/drain regions  15  can be formed by implanting impurities having a p-type conductivity to the extent that the dose amount becomes around 2.0 to 5.0×10 12 /cm 2 . Here, boron (B) ions, for instance, can be used as the p-type impurities.  
         [0053]     In the above-described structure, as shown in  FIG. 4A  and  FIG. 4B , the semiconductor device  1  has a semiconductor layer  1   b  between the field oxide  12 A which defines the active region AR for the high withstand voltage MOS transistor region  1 A and the field oxide  12   b  which defines the active region AR for the low withstand voltage MOS transistor region  1 B. This semiconductor layer  1   b  is a region where the semiconductor substrate  11  is exposed, and it serves as a separating region which physically separates the field oxide  12 A and the field oxide  12   b . In this embodiment, a boundary  1   a  between the high withstand voltage MOS transistor region  1 A and the low withstand voltage MOS transistor region  1 B is positioned on the semiconductor layer  1   b . Therefore, in this embodiment, in an exposure process in the manufacturing process of the semiconductor device  1  (which will be described later on) for instance, a photo mask with a layout enabling the boundary between the high withstand voltage MOS transistor region  1 A and the low withstand voltage MOS transistor region  1 B to be located on the semiconductor layer  1   b , and suitable exposure conditions for such purpose, are used. Here, the boundary to be located onto the semiconductor layer  1   b  corresponds to the boundary  1   a.    
         [0054]     In this way, this embodiment realizes the structure in which the boundary  1   a  between the high withstand voltage MOS transistor region  1 A and the low withstand voltage MOS transistor region  1 B can be located on the semiconductor layer  1   b , which is the exposed semiconductor substrate  11 , but not on the field oxide, i.e. the silicon oxide film. Therefore, in this embodiment, for instance, in a gate insulation film patterning process (q.v.  FIG. 5C ) to be described later on, a boundary (which corresponds to  1   a ) between a region to be etched and a region not to be etched will not be disposed on the field oxide. As a result, it is possible to prevent any step from being formed in the upper part of the field oxide.  
         [0055]     Furthermore, as it will be mentioned later on, the semiconductor layer  1   b  is a region where predetermined impurities are doped as with the active regions AR in the semiconductor substrate  11 . Therefore, by applying a predetermined electric potential to the semiconductor layer  1   b , possible inter-field leakage can be prevented.  
         [0056]     Accordingly, by having the structure according to this embodiment, it is possible to realize the semiconductor device  1  which is capable of preventing wire disconnection which can be caused by defective printing in the photolithographic process, or in other words, the semiconductor device  1  which is capable of preventing problems such as occurrences of open, short, leakage, etc.  
         [0057]     Manufacturing Method  
         [0058]     Now, a method of manufacturing the semiconductor device  1  according to the first embodiment of the present invention will be described in detail with reference to the drawings.  FIG. 5A  to  FIG. 6C  are diagrams showing processes of manufacturing the semiconductor device  1  according to the first embodiment of the present invention. With respect to  FIG. 5A  to  FIG. 6C , each process will be described in terms of a section taken along the line II-II′ shown in  FIG. 4B .  
         [0059]     First, as shown in  FIG. 5A , field oxides  12 A and  12 B are formed in the upper parts of the semiconductor substrate  11  using a known STI method for instance. Thereby, the active region AR in the high withstand voltage MOS transistor region  1 A and the active region AR in the low withstand voltage MOS transistor region  1 B are defined, and the semiconductor layer  1   b  which is an exposed semiconductor substrate  11  between the field oxides  12 A and  12 B (i.e. two field regions FR) is also defined. However, the method of forming the field oxides  12 A and  12 B is not limited to the STI method, but can also be a LOCOS method for instance.  
         [0060]     Next, by conducting a thermal oxidation treatment on the semiconductor substrate  11 , as shown in  FIG. 5B , a gate insulation film  13  which has the same thickness as the gate insulation film  13   a  for the high withstand voltage MOS transistor (e.g. around 30 to 50 nm) is formed on the whole upper surface of the semiconductor substrate  11 . Here, as for the conditions of the thermal oxidation treatment, for instance, the temperature is set at 850° C. and the heating time is set to around 30 to 40 minutes.  
         [0061]     Next, by conducting a known photolithographic process, a resist pattern R 1  is formed only in the high withstand voltage MOS transistor region  1 A. In this process, due to using a photo mask which enables the boundary  1   a  shown in  FIG. 4B  to be focused onto the semiconductor layer  1   b , as shown in  FIG. 5C , the side edge of the resist pattern R 1  is located on the semiconductor layer  1   b.    
         [0062]     Next, by using a known etching method, the gate insulation film  13  in the low withstand voltage MOS transistor region  1 B is removed. By this process, as shown in  FIG. 5C , a gate insulation film  13 A which is a part of the gate insulation film  13  remains only in the high withstand voltage MOS transistor region  1 A. Here, in order to prevent the semiconductor substrate  11  from being damaged, it is preferable to use a wet etching method. In this wet etching process, for instance, the semiconductor substrate  11  having the gate insulation film  13  which is a silicon oxide film is soused in a hydrofluoric acid liquid of approximate 5% concentration for about 1 to 2 minutes. Moreover, in order to prevent etching residuals of the gate insulation film  13  from staying in the low withstand voltage MOS transistor region  1 B, it is preferable to conduct over etching to the extent of about several dozen percent of the thickness of the gate insulation film  13 . Here, an upper part of a field oxide in a region which is not covered by the resist pattern R 1 , i.e. the upper part of the field oxide  12 B in the low withstand voltage MOS transistor region  1 B, is also removed by this over etching. By this process, as shown in  FIG. 5C , the field oxide  12   b  of which upper parts is etched is formed. In addition, in the wet etching process using a hydrofluoric acid liquid as an etchant, it is possible to selectively etch the silicon oxide film (i.e. the gate insulation film  13 ) with respect to the silicon substrate (i.e. the semiconductor substrate  11 ). In this process, however, the surface of the semiconductor substrate  11  is etched slightly in over etching. Accordingly, a minute step  1   c  is formed at the surface of the semiconductor substrate  11  as shown in  FIG. 5C . After such etching process, the resist pattern R 1  on the remained gate insulation film  13 A is removed.  
         [0063]     Next, by conducting a thermal oxidation treatment on the semiconductor substrate  11 , a gate insulation film  13 B for the low withstand voltage MOS transistor is formed in the low withstand voltage MOS transistor region  1 B as shown in  FIG. 6A . Here, the gate insulation film  13 B is formed to a thickness which is decided depending on an operating voltage and performance expected from the low withstand voltage MOS transistor. For instance, the gate insulation film  13 B is formed to the thickness of around 2 to 7 nm. As for the conditions of the thermal oxidation treatment, for instance, the temperature is set at 850° C. and the heating time is set to around 10 minutes.  
         [0064]     Next, by depositing polysilicon over the entire surface of the semiconductor substrate  11  on which the gate insulation films  13 A and  13 B are formed, a polysilicon film having a thickness of about 200 to 300 nm, for instance, is formed over the semiconductor substrate  11 . Then, by processing the polysilicon film using a known photolithographic method and a known etching method, gate electrodes  14  are formed on the gate insulation film  13 A in the high withstand voltage MOS transistor region  1 A and on the gate insulation film  13 B in the low withstand voltage MOS transistor region  1 B, respectively. Then, while using the gate electrodes  14  as masks, an etch back process is done on the entire surface of the silicon substrate  11  to remove the gate insulation films  13 A and  13 B except for the parts underneath the gate electrodes  14 . By these processes, a structure shown in  FIG. 6B  can be obtained.  
         [0065]     Next, an insulation film such as a silicon oxide film or a silicon nitride film is formed on the entire surface of the semiconductor substrate  11  using a known CVD method, after which an etch back process according to a known etching technique is performed on the insulation film to form sidewall spacers  16  on the sides of the gate electrode  14  respectively, as shown in  FIG. 6C .  
         [0066]     Next, arsenic (As) ions are implanted into the semiconductor substrate  11  while using the field oxides  12 A and  12   b , the gate electrodes  14  and the sidewall spacers  16  as masks, by which a pair of source/drain regions  15  are formed in the active region of each of the high withstand voltage MOS transistor region  1 A and low withstand voltage MOS transistor region  1 B in a self-aligning manner, the pair of source/drain regions  15  being formed in a way which sandwich a region undernearth the gate electrode  14  and the sidewall spacers  16 , as shown in  FIG. 4A . On the other hand, in order to form an electrode for controlling a substrate potential (which is also called a well potential), p-type impurities (e.g. boron (B) ions) are implanted into the semiconductor layer  1   b . By this arrangement, the electrical conductivity of the semiconductor layer  1   b  can be improved.  
         [0067]     Taking the processes described above, a semiconductor device  1  having the low withstand voltage MOS transistor and the high withstand voltage MOS transistor formed on the same semiconductor substrate  11  can be produced.  
         [0068]     In the above-described way, according to this embodiment, the field oxide  12 A is formed in a way encircling the active region AR in the high withstand voltage MOS transistor region  1 A, the field oxide  12   b  is formed in a way encircling the active region AR in the low withstand voltage MOS transistor region  1 B, and the semiconductor layer  1   b  being the equivalent of the active region is formed between adjacent high withstand MOS transistor region  1 A and low withstand MOS transistor region  1 B. In this structure, since the boundary  1   a  between the adjacent high withstand MOS transistor region  1 A and low withstand MOS transistor region  1 B is set on the semiconductor layer  1   b , it is possible to prevent any step from being formed in the field oxides  12 A and  12   b  which electrically separate the high withstand MOS transistor region  1 A and the low withstand MOS transistor region  1 B. By such structure, in the photolithographic process and the like which form the gate electrodes  14  made of polysilicon for instance, it is possible to prevent problems such as defective printing, etching residual of the polysilicon film, etc.  
         [0069]     Moreover, since the semiconductor layer  1   b  being the equivalent of the active region AR is laid out in a way encircling the high withstand voltage MOS transistor region  1 A (or the low withstand voltage MOS transistor region  1 B), by applying an arbitrary potential to this semiconductor layer  1   b , the possible occurrence of inter-field leakage can be prevented.  
         [0070]     Due to such effects, problems such as occurrences of open, short, leakage, etc. can be prevented in a semiconductor device in which a high withstand voltage MOS transistor and a low withstand voltage MOS transistor are formed in a single semiconductor substrate.  
       Second Embodiment  
       [0071]     A second embodiment of the present invention will be described in detail with reference to the drawings. In the following, for the structures that are the same as the first embodiment, the same reference numbers will be used, and redundant explanations of those structure elements will be omitted.  
         [0072]     Structure  
         [0073]      FIG. 7A  is a sectional view of a semiconductor device  2  according to the second embodiment of the present invention taken along a line III-III′, and  FIG. 7B  is an overhead diagram showing the semiconductor device  2 . The III-III′ section of  FIG. 7A  is a section of the line III-III′ shown in  FIG. 7B . Here, the same reference numbers are used for the same structural elements.  
         [0074]     As shown in  FIG. 7A  and  FIG. 7B , the semiconductor device  2  has a high withstand voltage MOS transistor region  2 A and a low withstand voltage MOS transistor region  2 B which are both semiconductor elements. An active region AR in the high withstand voltage MOS transistor region  2 A is defined by being electrically separated from the other regions by field oxides  22   a  which are field regions FR. Likewise, an active region AR in the low withstand voltage MOS transistor region  2 B is defined by being electrically separated from the other regions by field oxides  22   b  which are field regions FR.  
         [0075]     A high withstand voltage MOS transistor formed in the high withstand voltage MOS transistor region  2 A has the same structure as the high withstand voltage MOS transistor formed in the high withstand voltage MOS transistor region  1 A in the first embodiment, and in the high withstand voltage MOS transistor in the second embodiment, the gate insulation film  13   a  is replaced with a gate insulation film  23   a . On the other hand, like the high withstand voltage MOS transistor, a low withstand voltage MOS transistor formed in the low withstand voltage MOS transistor region  2 B has the same structure as the low withstand voltage MOS transistor formed in the low withstand voltage MOS transistor region  1 B in the first embodiment, and in the low withstand voltage MOS transistor in the second embodiment, the gate insulation film  13   b  is replaced with a gate insulation film  23   b.    
         [0076]     The gate insulation film  23   a  is substantially the same as the gate insulation film  13   a  in the first embodiment, but the formation process thereof differs from the formation process of the gate insulation film  13   a . Likewise, the gate insulation film  23   b  is substantially the same as the gate insulation film  13   b  in the first embodiment, but the formation process thereof differs from the formation process of the gate insulation film  13   b . These formation processes will be described later on in describing a manufacturing method, and therefore, detailed descriptions of those processes will be omitted in this past of the description.  
         [0077]     Furthermore, in the semiconductor device  2  of the second embodiment, the field oxide  12 A formed in the high withstand voltage MOS transistor region  1 A in the semiconductor device  1  of the first embodiment is replaced with the field oxide  22   a , and the field oxide  12   b  formed in the low withstand voltage MOS transistor region  1 B in the semiconductor device  1  of the first embodiment is replaced with the field oxide  22   b.    
         [0078]     As can be seen from comparing  FIG. 4A  and  FIG. 7A , unlike the field oxide  12 A, an upper part of the field oxide  22   a  is removed and the amount removed in the field oxide  22   a  is less than that in the field oxide  12   b . On the other hand, as can be seen from comparing  FIG. 4A  and  FIG. 7A , the amount removed in the field oxide  22   b  is less than that in the field oxide  12   b . These differences are provided by differences in the formation processes between the field oxides  12 A and  12   b  and the field oxides  22   a  and  22   b , respectively. These formation processes will be described later on as with the processes of the field oxides  22   a  and  22   b.    
         [0079]     As described above, in the second embodiment, it is possible to reduce the removing amounts in the field oxide  22   a  and  22   b . Furthermore, in this embodiment, the field oxides  22   a  and  22   b  are formed by etching field oxides  22 A and  22 B, which will be described later on, subject to the thickness of the silicon oxide film  27 , which will be described later on. Therefore, it is possible to conform the height of the upper face of the field oxide  22   a  in the high withstand voltage MOS transistor region  2 A and the height of the upper face of the field oxide  22   b  in the low withstand voltage MOS transistor region  2 B. Accordingly, in etching to remove a polysilicon film deposited over the field oxides  22   a  and  22   b  using a photolithographic method within the process of forming the gate electrode  14 , which will be described later on, it is possible to spread a margin to cope with displacements and defocuses (this margin is also called an exposure margin).  
         [0080]     Moreover, because the heights of the field oxides  22   a  and  22   b  are made even, it is possible to uniform the depths of contact holes formed over the gate electrodes  14  on the field oxides  22   a  and  22   b . Accordingly, it is possible to spread a margin for etching conditions in forming the contact holes (this margin is also called an etching margin).  
         [0081]     Since the rest of the structure is the same as the first embodiment, a detailed description thereof will be omitted here.  
         [0082]     Manufacturing Method  
         [0083]     Now, a method of manufacturing the semiconductor device  2  according to the second embodiment of the present invention will be described in detail with reference to the drawings.  FIG. 8A  to  FIG. 10B  are diagrams showing processes of manufacturing the semiconductor device  2  according to the second embodiment of the present invention. With respect to  FIG. 8A  to  10 B, each process will be described in terms of a section taken along the line III-III′ shown in  FIG. 7B .  
         [0084]     First, as shown in  FIG. 8A , field oxides  12 A and  12 B are formed in upper parts of the semiconductor substrate  11  using a known STI method for instance. Thereby, the active region AR in the high withstand voltage MOS transistor region  2 A and the active region AR in the low withstand voltage MOS transistor region  2 B are defined, and the semiconductor layer  1   b  which is an exposed semiconductor substrate  11  between the field oxides  12 A and  12 B (i.e. two field regions FR) is also defined. However, the method of forming the field oxides  12 A and  12 B is not limited to the STI method, and can also be a LOCOS method for instance.  
         [0085]     Next, by conducting a thermal oxidation treatment on the semiconductor substrate  11 , a silicon oxide film  27  which is thinner than the gate insulation film  13   a  for the high withstand voltage MOS transistor (e.g. around 10 to 20 nm) is formed on the whole upper surface of the semiconductor substrate  11 . Here, as for the conditions of the thermal oxidation treatment, for instance, the temperature is set at 850° C. and the heating time is set to around 20 minutes. Then, by depositing silicon nitride over the silicon oxide film  27  using a known CVD method for instance, a silicon nitride film  28  having a thickness of about 100 to 200 nm, for instance, is formed on the silicon oxide film  27 . By these processes, a structure shown in  FIG. 8B  can be obtained. The silicon nitride film  28  is a protective film with respect to a thermal oxidation treatment which will be described later on reference to with  FIG. 9A . Therefore, any thickness of the silicon nitride film  28  is applicable as long it is a sufficient thickness with which the silicon oxide film  28  can protect the semiconductor substrate  11  from the thermal oxidation treatment.  
         [0086]     Next, by conducting a known photolithographic process, a resist pattern R 2  is formed only in the low withstand voltage MOS transistor region  2 B. In this process, as with the first embodiment, due to using a photo mask which enables the boundary  1   a  shown in  FIG. 7B  to be focused onto the semiconductor layer  1   b , as shown in  FIG. 8C , the side edge of the resist pattern R 2  is located on the semiconductor layer  1   b.    
         [0087]     Next, by using a known etching method, the silicon nitride film  28  and the silicon oxide film  27  in the high withstand voltage MOS transistor region  2 A is removed. By this process, as shown in  FIG. 8C , a silicon nitride film  28 B which is a part of the silicon nitride film  28  and a silicon oxide film  27 B which is a part of the silicon oxide film  27  remain only in the low withstand voltage MOS transistor region  2 B. Here, in order to prevent the semiconductor substrate  11  from being damaged, it is preferable to use a wet etching method. In this wet etching process, for instance, the silicon nitride film  28  is etched by sousing the semiconductor substrate  11  having the silicon nitride film  28  in a thermal phosphoric acid liquid at a temperature of around 160° C. for about 30 to 40 minutes. The silicon oxide film  27  is etched by sousing the semiconductor substrate  11  having the silicon oxide film  27  in a hydrofluoric acid liquid of approximate around 5% concentration for about 1 to 2 minutes. Moreover, in order to prevent etching residuals of the silicon oxide film  27  from staying in the high withstand voltage MOS transistor region  2 A, it is preferable to conduct over etching to the extent of about several dozen percent of the thickness of the silicon oxide film  27 . Here, an upper part of a field oxide in a region which is not covered by the resist pattern R 2 , i.e. the upper part of the field oxide  12 A in the high withstand voltage MOS transistor region  2 A, is also removed by this over etching. By this process, as shown in  FIG. 8C , the field oxide  22   a  of which the upper part is etched is formed. However, since the thickness of the silicon oxide film  27  is thinner than the thickness of the gate insulation film  13  in the first embodiment (e.g. around 30 to 50 nm), and it may be around 10 to 20 nm for instance, the amount of the removed upper part of the field oxide  12 A is larger than the amount of the removed upper part of the field oxide  12 B which is removed in the etching process of the gate insulation film  13  in the first embodiment. That is, according to this embodiment, the amount of removed upper parts of field oxides can be reduced. In addition, in the wet etching using a thermal phosphoric acid liquid as an etchant, it is possible to selectively etch the silicon nitride film  28  with respect to the silicon oxide film  27 . Therefore, in this wet etching process, it is possible to ignore the thinning of the silicon nitride film  28 . Furthermore, in the wet etching process using a hydrofluoric acid liquid as an etchant, as with the first embodiment, it is possible to selectively etch the silicon oxide film  27  with respect to the silicon substrate (i.e. the semiconductor substrate  11 ). In this process, however, the surface of the semiconductor substrate  11  is etched slightly due to the over etching. Accordingly, a minute step  1   c  is formed at the surface of the semiconductor substrate  11  as shown in  FIG. 8C . After such etching processes, the resist pattern R 2  on the remained silicon oxide film  28  is removed.  
         [0088]     Next, by conducting a thermal oxidation treatment on the semiconductor substrate  11 , a gate insulation film  23 A for the high withstand voltage MOS transistor is formed in the high withstand voltage MOS transistor region  2 A as shown in  FIG. 9A . Here, considering that the gate insulation film  23 A is to be thinned in the following process of etching the silicon oxide film  27 B, the gate insulation film  23 A should preferably be formed to a thickness that is thicker than a thickness that is sufficient to not be damaged by an operating voltage, by a portion of the gate insulation film  23 A to be thinned in the etching process of the silicon oxide film  27 B. The thickness sufficient to not be damaged by an operating voltage is around 30 to 50 nm for instance, and the portion of the gate insulation film  23 A to be thinned in the etching process of the silicon oxide film  27 B, in thickness, is around 11 to 22 nm for instance. Therefore, in this process, the gate insulation film  23 A should preferably be formed to a thickness of around 41 to 52 nm for instance. In addition, in this process, the silicon nitride film  28 B formed in the low withstand voltage MOS transistor region  2 B functions as a protective film with respect to a thermal oxidation treatment. Therefore, the gate insulation film  23 A should not be formed in the low withstand voltage MOS transistor region  2 B and the silicon oxide film  27 B should not be thickened. As for the conditions of the thermal oxidation treatment, for instance, the temperature is set at 850° C. and the heating time is set to around 30 to 40 minutes.  
         [0089]     Next, the silicon nitride film  28 B and silicon oxide film  27 B remaining in the low withstand voltage MOS transistor region  2 B are removed using the same wet etching method as in the process explained referring to  FIG. 8C . Thereby, the semiconductor substrate  11  in the low withstand voltage MOS transistor region  2 B is exposed as shown in  FIG. 9B . In this process, the gate insulation film  23 A is also etched. Thereby, a gate insulation film  23 C having a desired thickness (e.g. around 30 to 50 nm) is formed in the high withstand voltage MOS transistor region  2 A as shown in  FIG. 9B . Furthermore, in this process, an upper part of the field oxide  12 B is removed by the over etching described above. Thereby, the field oxide  22   b  in which the upper part is etched is formed. However, as described above, since the thickness of the silicon oxide film  27  is thinner than the thickness of the gate insulation film  13  in the first embodiment (e.g. around 30 to 50 nm), and it may be around 10 to 20 nm for instance, the amount of the removed upper part of the field oxide  12 B is larger than the amount of the removed upper part of the field oxide  12 B which is removed in the etching process of the gate insulation film  13  in the first embodiment. That is, according to this embodiment, the amount of the removed upper parts of the field oxides can be reduced. Moreover, according to this embodiment, it is possible to conform the removing thicknesses between the field oxides  12 A and  12 B. That is, it is possible to conform the height of the upper face of the field oxide  22   a  in the high withstand voltage MOS transistor region  2 A and the height of the upper face of the field oxide  22   b  in the low withstand voltage MOS transistor region  2 B.  
         [0090]     Next, by conducting a thermal oxidation treatment on the semiconductor substrate  11 , a gate insulation film  23 B for the low withstand voltage MOS transistor is formed in the low withstand voltage MOS transistor region  2 B as shown in  FIG. 9A . Here, as with the first embodiment, the gate insulation film  23 B is formed to a thickness which is decided depending on the operating voltage and performance expected from the low withstand voltage MOS transistor. For instance, the gate insulation film  13 B is formed to a thickness of around 2 to 7 nm. As for the conditions of the thermal oxidation treatment, for instance, the temperature is set at 850° C. and the heating time is set to around 10 minutes.  
         [0091]     Next, by depositing polysilicon over the entire surface of the semiconductor substrate  11  on which the gate insulation films  23 C and  23 B are formed, a polysilicon film having a thickness of about 200 to 300 nm, for instance, is formed over the semiconductor substrate  11 . Then, by processing the polysilicon film using a known photolithographic method and a known etching method, gate electrodes  14  are formed on the gate insulation film  23 C in the high withstand voltage MOS transistor region  2 A and on the gate insulation film  23 B in the low withstand voltage MOS transistor region  2 B, respectively. Then, while using the gate electrodes  14  as masks, an etch back process is done on the entire surface of the silicon substrate  11  to remove the gate insulation films  23 C and  23 B except for the parts underneath the gate electrodes  14 . By these processes, a structure shown in  FIG. 10A  can be obtained.  
         [0092]     Next, an insulation film such as a silicon oxide film or a silicon nitride film is formed on the entire surface of the semiconductor substrate  11  using a known CVD method, after which an etch back process according to a known etching technique is performed on the insulation film to form sidewall spacers  16  on the sides of the gate electrode  14  respectively, as shown in  FIG. 10B .  
         [0093]     Next, arsenic (As) ions are implanted into the semiconductor substrate  11  while using the field oxides  22   a  and  22   b , the gate electrodes  14  and the sidewall spacers  16  as masks, by which a pair of source/drain regions  15  are formed in the active region of each of the high withstand voltage MOS transistor region  2 A and low withstand voltage MOS transistor region  2 B in a self-aligning manner, the pair of source/drain regions  15  being formed in a way which sandwich a region undernearth the gate electrode  14  and the sidewall spacers  16 , as shown in  FIG. 7A . On the other hand, in order to form an electrode for controlling a substrate potential (which is also called a well potential), p-type impurities (e.g. boron (B) ions) are implanted into the semiconductor layer  1   b . By this arrangement, the electrical conductivity of the semiconductor layer  1   b  can be improved.  
         [0094]     Taking the processes described above, a semiconductor device  2  having the low withstand voltage MOS transistor and the high withstand voltage MOS transistor formed on the same semiconductor substrate  11  can be produced.  
         [0095]     In the above-described way, according to this embodiment, the field oxide  22   a  is formed in a way encircling the active region AR in the high withstand voltage MOS transistor region  2 A, the field oxide  22   b  is formed in a way encircling the active region AR in the low withstand voltage MOS transistor region  2 B, and the semiconductor layer  1   b  that is the equivalent of the active region is formed between adjacent high withstand MOS transistor region  2 A and low withstand MOS transistor region  2 B. In this structure, since the boundary  1   a  between the adjacent high withstand MOS transistor region  2 A and low withstand MOS transistor region  2 B is set on the semiconductor layer  1   b , it is possible to prevent any step from being formed in the field oxides  22   a  and  22   b  which electrically separate the high withstand MOS transistor region  2 A and the low withstand MOS transistor region  2 B. By such structure, in the photolithographic process and the like in forming the gate electrodes  14  made of polysilicon for instance, it is possible to prevent problems such as defective printing, etching residual of the polysilicon film, etc.  
         [0096]     Moreover, since the semiconductor layer  1   b  that is the equivalent of the active region AR is laid out in a way encircling the high withstand voltage MOS transistor region  2 A (or the low withstand voltage MOS transistor region  2 B), by applying an arbitrary potential to this semiconductor layer  1   b , the possible occurrence of inter-field leakage can be prevented.  
         [0097]     Due to such effects, problems such as the occurrence of open, short, leakage, etc. can be prevented in a semiconductor device in which a high withstand voltage MOS transistor and a low withstand voltage MOS transistor are formed in a single semiconductor substrate.  
         [0098]     Moreover, according to this embodiment, it is possible to reduce the removing amounts in the field oxide  22   a  and  22   b . Furthermore, in this embodiment, the field oxides  22   a  and  22   b  are formed by etching field oxides  22 A and  22 B subject to the thickness of the silicon oxide film  27 . Therefore, it is possible to conform the height of the upper face of the field oxide  22   a  in the high withstand voltage MOS transistor region  2 A and the height of the upper face of the field oxide  22   b  in the low withstand voltage MOS transistor region  2 B. Accordingly, in etching to remove a polysilicon film deposited over the field oxides  22   a  and  22   b  using a photolithographic method within the process of forming the gate electrode  14 , it is possible to spread an exposure margin to cope with displacements and defocuses.  
         [0099]     Moreover, because the heights of the field oxides  22   a  and  22   b  are made even, it is possible to uniform the depths of contact holes formed over the gate electrodes  14  on the field oxides  22   a  and  22   b . Accordingly, it is possible to spread an etching margin for etching conditions in forming the contact holes.  
         [0100]     Although the cases where an n-type high withstand voltage MOS transistor and an n-type low withstand voltage MOS transistor are mounted together on the same semiconductor substrate have been referred to in the above descriptions of the first and second embodiments, the present invention is not limited to this factor. For instance, by changing the impurities (ions) to be used, the present invention can be applied to a case where a p-type high withstand voltage MOS transistor and a p-type low withstand voltage MOS transistor are mounted together on the same semiconductor substrate, and a case where n-type and p-type high withstand voltage MOS transistors and n-type and p-type low withstand voltage MOS transistors are mounted together on the same semiconductor substrate.  
         [0101]     Although the case where two kinds of MOS transistors (i.e. a high withstand voltage MOS transistor and a low withstand voltage MOS transistor) are mounted together on the same semiconductor substrate has been referred to in the above descriptions of the first and second embodiments, i.e. the case where two kinds of gate insulation films with different thicknesses are formed on the same semiconductor substrate, the present invention is not limited to this factor. For instance, the present invention can be applied to a case where more than three kinds of gate insulation films with different thicknesses are formed on the same semiconductor substrate.  
         [0102]     Although the thermal oxidation treatment method is used for forming the gate insulation films ( 13 ,  13 B,  23 A and  23 B) and silicon oxide film ( 27 ) in the above descriptions of the first and second embodiments, the present invention is not limited to this factor, and any method for forming a high resistance film having a desired thickness on the semiconductor substrate  11  can be applied as long as the formed film conforms to the spirit or the scope of the present invention.  
         [0103]     While the preferred embodiments of the invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or the scope of the following claims.  
         [0104]     This application claims priority to Japanese Patent Application No. 2005-69719. The entire disclosures of Japanese Patent Application No. 2005-69719 is hereby incorporated herein by reference.  
         [0105]     While only selected embodiments have been chosen to illustrate the present invention, it will be apparent to those skilled in the art from this disclosure that various changes and modifications can be made herein without departing from the scope of the invention as defined in the appended claims. Furthermore, the foregoing descriptions of the embodiments according to the present invention are provided for illustration only, and not for the purpose of limiting the invention as defined by the appended claims and their equivalents. Thus, the scope of the invention is not limited to the disclosed embodiments.  
         [0106]     The term “configured” as used herein to describe a component, section or portion of a device includes hardware and/or software that is constructed and/or programmed to carry out the desired function.  
         [0107]     Moreover, terms that are expressed as “means-plus function” in the claims should include any structure that can be utilized to carry out the function of that portion of the present invention.  
         [0108]     The terms of degree such as “substantially,” “about,” and “approximately” as used herein mean a reasonable amount of deviation of the modified term such that the end result is not significantly changed. For example, these terms can be construed as including a deviation of at least ±5% of the modified term if this deviation would not negate the meaning of the word it modifies.