Abstract:
An on-die calibration system includes an external reference component, a first and a second on-die adjustable components, and a calibration module coupled to the reference component, the first and second components, wherein the calibration module calibrates the first component according to the reference component and calibrates the second component according to the calibrated first component.

Description:
BACKGROUND 
   The present invention relates generally to integrated circuit designs, and, more particularly, to on-die calibration circuit designs. 
   Electrical signals are reflected back when they reach the end of a transmission path, or at points where impedance differs. Signal reflection causes noise, which lowers signal quality. In a high-speed data transfer system, high quality signals are required and even a slight amount of noise can be a major problem. On-die-termination (ODT) reduces signal reflection by attaching a resistor with a suitable resistance value, to an I/O pin of a chip. The termination resistance ‘swallows’ the signaling voltage, which, therefore cannot be reflected. 
   When termination resistors are built on a die, the resistance of the resistors may fluctuate due to PVT (process, voltage, temperature) variations. Then an on-die PVT compensation circuit becomes desirable in a chip design. An on-die PVT compensation circuit automatically calibrates all the ODT resistors through internal calibration loops. 
   What is needed is an improved method and system for calibrating on-die components. 
   SUMMARY 
   This invention discloses a method and system for on-die component calibration. The system, according to one embodiment of the present invention, may comprise an external reference component, a first and a second on-die adjustable component, and a calibration module coupled to the reference component, the first and second components, wherein the calibration module calibrates the first component according to the reference component and calibrates the second component according to the calibrated first component. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram of a conventional resistor calibration system illustrating a mechanism of calibrating a digital-code-controlled resistor; 
       FIG. 2  is a schematic diagram of a digital-code-controlled (DCC) resistor; 
       FIG. 3  is a block diagram of a resistor calibration system according to one embodiment the present invention; and 
       FIG. 4  is a block diagram of a chip with an on-die resistor calibration system. 
   

   DESCRIPTION 
     FIG. 1  is a block diagram of a conventional resistor calibration system  100  illustrating a mechanism of calibrating a digital-code-controlled (DCC) resistor  110 . Resistor  120  is a reference resistor, serially connected with the DCC resistor  110 . Then the resistors are connected between a system of high voltage (Vcc) and a system of low voltage (Vss). A connection node C between the two resistors  110  and  120  serves as one of two inputs of a comparator  130 . The other input of the comparator  130  is connected to a reference voltage (Vref). An output of the comparator  130  is coupled to a latch  140  input. Then latched data from the comparator  130  is fed into an up/down counter  150 . In one design, the counter  150  counts up when node C voltage is higher than Vref, and counts down when Vref is higher than node C voltage. Yet in another design, the counter  150  can work the opposite way, i.e., counts up when Vref is higher than node C voltage, and counts down when node C voltage is higher than Vref. Either way, when the difference between node C voltage and Vref falls into a predetermined range, the counter  150  stops counting and outputs a counting result number to a code register  160 . The counting result number is then used to determine a resistor value of the DCC resistor  110 . 
     FIG. 2  is a schematic diagram of the DCC resistor  110  as shown in  FIG. 1 . Referring to  FIG. 2 , resistors R[ 1 :n] are connected in parallel with a resistor R[ 0 ] through their respective switches K[ 1 :n]. The switches K[ 1 :n] are controlled by the code register  160  as shown in  FIG. 1 . The more switches are closed, e.g., more resistors are connected, the lower the total resistance between nodes A and B. 
     FIG. 3  is a block diagram of a resistor calibration system  300  according to one embodiment of the present invention. The calibration system  300  expends the calibration system  100 , as shown in  FIG. 1 , to calibrate multiple DCC resistors R[ 1 :n]. When a switch K[ 0 ] is closed, a switch K[ 1 ] is switched to Vdd, and all other switches are open, a reference resistor R[ 0 ] is used to calibrate a first DCC resistor R[ 1 ]. After the first DCC resistor R[ 1 ] is calibrated, it is used to calibrate other DCC resistors R[ 2 :n], one by one. During these calibrations, the switch K[ 0 ] is open, K[ 1 ] is switched to Vss. Switches K[ 2 ] and Ka[ 2 ] are closed when a DDC resistor R[ 2 ] is under calibration, or switches K[ 3 ] and Ka[ 3 ] are closed when a DDC resistor R[ 3 ] is under calibration, or similarly, switches K[n] and Ka[n] are closed when a DDC resistor R[n] is under calibration. The calibration mechanism used by the system  300  is the same as described in the system  100  as shown in  FIG. 1 . Here a comparator  330 , a latch  340  and an up/down counter  350  are also employed. In order to synchronize the open-and-close of the switches, K[ 0 :n], a code-register-controller  360  is used in place of the simple code register  160  as shown in  FIG. 1 . The code-register-controller has pre-programmed sequence and control logic to automatically implement the aforementioned switching activities, so that all the DCC resistors R[ 1 :n] get calibrated one by one. 
     FIG. 4  is a block diagram of chip  400  with an on-die resistor calibration system, which is adapted from the calibration system  300  as shown in  FIG. 3 . DDC resistors R[ 1 : 12 ], which are connected to pad[ 1 : 12 ], respectively, are on-die-termination (ODT) resistors. A resistor R[ 0 ], connected to a pad[ 0 ], is an external reference resistor, used to calibrate the first ODT resistor R[ 1 ]. Then the calibrated first ODT resistor R[ 1 ] is used to calibrate the rest of the ODT resistors R[ 2 : 12 ] one by one through switching arrangement. For instance, when the R[ 1 ] is used to calibrate R[ 2 ], switches K[ 1 : 2 ] and Ka[ 2 ] are closed, Ka[ 1 ] is open, and Kb[ 1 ] is switched to Vss. A node C voltage is compared with a reference voltage Vref at a comparator  430 . A comparator output is latched by latch  440  and used to control an up/down counter  450 . A code-register-controller  460  takes the counter  450  output and uses it to control the DCC resistor R[ 2 ]. Changing resistor R[ 2 ] value will alter node C voltage, which in turn will further modify resistor R[ 2 ] value to reduce the voltage difference between node C and Vref. Such negative feed back loop keeps running until the voltage difference between the node C and Vref falls into a predetermined range, then the loop stops, and the second ODT resistor R[ 2 ] is calibrated. Here, the code-register-controller  460  not only registers codes to adjust DCC resistors R[ 1 : 12 ], but also controls all the switches to open and close, so that all the ODT resistors can be calibrated one at a time using a calibrated ODT resistor. 
   The above illustration provides many different embodiments or embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims. 
   Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.