Abstract:
The present invention provides an apparatus for enhancing Q factor of an inductor. The apparatus includes a negative resistance generator coupled to the inductor for providing a negative resistance, and a bias circuit coupled to the negative resistance generator for biasing the negative resistance generator.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a circuit, especially to a circuit capable of enhancing the Q factor of an inductor.  
         [0003]     2. Description of the Prior Art  
         [0004]     A typical inductor in an analog circuit is usually a planar inductor having a Q factor of approximately 3˜8. This low Q factor often limits the application of an inductor. For example, when an inductor is utilized as a load of an amplifier, the gain of the amplifier is proportional to the square of the inductor&#39;s Q factor. Therefore, a low Q factor implies a low gain. Moreover, in some narrow-band communication systems, an inductor with high Q factor is utilized for making a narrow-band resonant chamber capable of filtering out interfering signals. The 3 dB bandwidth of the resonant chamber is inversely proportional to the Q factor of the inductor. Therefore, an inductor with a higher Q factor leads to a narrower-band resonant chamber.  
         [0005]     Some methods for enhancing the Q factor of an inductor are proposed, such as removing the substrate underneath the inductor to reduce power consumption of the substrate, inserting an isolation metal layer between the inductor and the substrate to reduce power consumption due to a vortex current, and substituting aluminum with high conductance metal (e.g., silver). However, these methods have a significant common drawback of being incompatible with the standard CMOS manufacturing methods. In addition to the methods mentioned above, an inductor can also be implemented by active circuit. However, the noise and linearity of an active circuit limits its application while being utilized in high-frequency and low-noise circuits.  
       SUMMARY OF THE INVENTION  
       [0006]     Therefore, it is one of objectives of the claimed invention to provide an apparatus for enhancing the Q factor of an inductor to solve the above-mentioned problems.  
         [0007]     It is one of objectives of the claimed invention to provide an apparatus for enhancing the Q factor of an inductor. The apparatus is coupled to the inductor to eliminate power consumption of the inductor such that the Q factor of the inductor can be enhanced.  
         [0008]     It is one of objectives of the claimed invention to provide an apparatus for enhancing the Q factor of an inductor. The apparatus is compatible with the standard manufacturing process of COMS.  
         [0009]     It is one of objectives of the claimed invention to provide an apparatus for enhancing the Q factor of an inductor. The apparatus does not affect the linearity and low noise performance of the inductor.  
         [0010]     It is one of objectives of the claimed invention to provide an apparatus for enhancing the Q factor of an inductor. The Q factor of the inductor, which is enhanced by the apparatus, will not change in accordance with voltage, temperature, or manufacturing parameters.  
         [0011]     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]      FIG. 1  is the circuit configuration of the present invention illustrating a negative resistance generator compensating for the parasitical resistors of the inductor.  
         [0013]      FIG. 2  is an equivalent circuit of the circuit shown in  FIG. 1 .  
         [0014]      FIG. 3  is an equivalent circuit of the circuit shown in  FIG. 2 .  
         [0015]      FIG. 4  shows the constant transconductance bias circuit according to an embodiment of the present invention.  
         [0016]      FIG. 5  shows a circuitry which implements the load unit shown in  FIG. 4  based on the switched capacitor technique.  
         [0017]      FIG. 6  shows a circuit according to an embodiment of the present invention where a constant transconductance bias circuit, which adopts the switched capacitor technique, is utilized to bias the negative resistance generator. 
     
    
     DETAILED DESCRIPTION  
       [0018]     One method to enhance the Q factor of a chip inductor is reducing the power consumption of the chip inductor due to its parasitical resistor. The present invention adopts a negative resistance generator, which provides negative resistance, to compensate for the parasitical resistor of the chip inductor. Please refer to  FIG. 1 .  FIG. 1  is the circuit configuration of the present invention illustrating a negative resistance generator  120  compensating for the parasitical resistors of inductors  112  and  114 . The inductors  112  and  114  together with an operation circuit  116  construct an application circuit  110 . The negative resistance generator  120  is coupled to the application circuit  110  to compensate for the parasitical resistors of the inductors  112  and  114 . The negative resistance generator  120  comprises a pair of transistors  122  and  124 , which couple to each other. In this embodiment, P-MOSFET&#39;s sever as exemplary devices for the transistors  122  and  124  for the sake of illustrating the configuration, but are not meant to be a limitation of the present invention. The gates of the transistors  122  and  124  are coupled to each other, and then further coupled to the drain of the transistor  122  through a capacitor  126  and to the drain of the transistor  124  through a capacitor  128 . The capacitors  126  and  128  are AC coupled capacitors, utilized for separating DC components and AC components. Moreover, a voltage level Vc is coupled to the gates of the transistors  122  and  124  to bias the negative resistance generator  120 . Under the ways of configuration and biasing described above, the negative resistance generator  120  can be regarded effectively as two resistors coupled in series. Thus,  FIG. 1  is simplified to an equivalent circuit shown in  FIG. 2 . If the manufacturing parameters are the same for both transistors  122  and  124 , then in this embodiment, the resistances of the equivalent resistors  212  and  214  shown in  FIG. 2  are approximately −1/gm, where gm is the transconductance of the transistors  122  and  124 .  
         [0019]     The connection among resistors  212 ,  214 , and inductors  112 ,  114  can be further simplified to an equivalent circuit shown in  FIG. 3 . The resistor  310  is equivalent to the serial-coupled resistors  212  and  214 , and the resistance R_ of the resistor  310  is −2/gm. The inductor  320  is equivalent to the serial-coupled inductors  112  and  114 , and is illustrated in  FIG. 3  by a parasitical resistor  324  coupled in parallel with a real inductor  322 . The resistance of the parasitical resistor  324  is RL, and the inductance of the inductor  322  is L. As shown in  FIG. 3 , it is well known to those skilled in the art that the Q factor of the inductor  320  is approximately equal to R p /ωL, where, R p  is a resistance of the parallel-coupled resistors R_ and R L , and ω is an angular frequency of inductors  112  and  114 . Therefore, by properly biasing the negative resistance generator  120  and determining the resistance R_ of the resistor  310 , the parasitical resistor  324  of the inductor  320  can be compensated and therefore the Q factor of the inductor is enhanced.  
         [0020]     In the above-mentioned embodiment, the voltage level Vc, which is utilized to bias the negative resistance generator  120 , is provided by a bias circuit. Please refer to  FIG. 4 .  FIG. 4  shows the bias circuit  400  according to an embodiment of the present invention. The bias circuit  400  is a constant transconductance bias circuit. The bias circuit  400  comprises four transistors  410 ,  420 ,  430 ,  440  and a load unit  450 . In this embodiment, two P-MOSFET&#39;s and two N-MOSFET&#39;s sever as exemplary devices for the transistors  410 ,  420 ,  430 , and  440  for the sake of illustrating the configuration, but are not meant to be a limitation of the present invention. In  FIG. 4 , assuming that the sizes of the transistors  410 ,  420 ,  430 ,  440  are respectively (W/L) N , (W/L) N , K(W/L) P , (W/L) P  (K is the ratio of the size of the transistor  430  to the size of the transistor  440 ), and the load unit  450  is a resistor with resistance Rs, then the output current I OUT of the bias circuit  400  is represented as  
               I   OUT     =       2       μ   p     ⁢         C   ox     ⁡     (     W   /   L     )       p         ⁢     1     R   s   2       ⁢       (     1   -     1     K         )     2               Eq   .           ⁢     (   1   )               
 
         [0021]     Since the transistors  122  and  124  are biased by the bias circuit  400 , the transconductance gm of the transistors  122  and  124  is  
             gm   =         2   ⁢     μ   p     ⁢         C   ox     ⁡     (     W   /   L     )       p     ⁢     I   OUT         =       2     R   s       ⁢     (     1   -     1     K         )                 Eq   .           ⁢     (   2   )               
 
         [0022]     Thus, the resistance R_ of the resistor  310  shown in  FIG. 3  is
 
  
             R_   =       -     2   gm       =       -     R   s         (     1   -     1     K         )                 Eq   .           ⁢     (   3   )               
 
         [0023]     Because the resistor R s  is subject to the manufacturing process, the resistance R_ of the resistor  310  is relatively unstable. In another preferred embodiment, the load unit  450  shown in  FIG. 4 , which has a resistance of R s , is implemented by an equivalent resistor generated based on a switched capacitor technique. Therefore, a negative resistance, which is more stable and finely adjustable, can be obtained. Please refer  FIG. 5 .  FIG. 5  shows a circuitry which implements the load unit  450  shown in  FIG. 4  according to the switched capacitor technique. The switches  520  and  530  are controlled respectively by two different clocks CK,  CK , which have the same frequency but opposite phases. When one of the switches  520  and  530  is conducted, the other is not conducted, i.e., the switches  520  and  530  are controlled respectively by the clocks CK,  CK  and therefore continuously change their states. Assuming that the capacitance of the capacitor  510  is C s , and the period of the clocks CK,  CK  is T, then the equivalent resistance R eq  of the load unit  450  shown in  FIG. 5 
 
is  R   eq   =T/C   s    Eq. (4)
 
         [0024]     Substituting R s  in Eq. (3) with R eq  of Eq. (4), the resistance R_ becomes  
             R_   =       -   T         C   s     ⁡     (     1   -     1     K         )                 Eq   .           ⁢     (   5   )               
 
         [0025]     As a result, the resistance R_ of the resistor  310  is determined by the precise timing period T, the ratio K, and the capacitance C s . Therefore, a negative resistance that is more precise and easily adjustable can be obtained.  
         [0026]     Please refer to  FIG. 1  and  FIG. 6  together.  FIG. 6  shows a circuit according to an embodiment of the present invention where a constant transconductance bias circuit, which adopts the switched capacitor technique, is utilized to bias the negative resistance generator. As shown in this embodiment, the original inductors are coupled to the circuit of the present invention such that the power consumption of the inductors is reduced and therefore the Q factor is enhanced. In addition, this circuit is compatible with the standard CMOS manufacturing methods, and this circuit will not affect the linearity and low noise performance of the inductor. The Q factor of the inductor will not change in accordance with voltage, temperature, or manufacturing parameters.  
         [0027]     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.