Abstract:
In one embodiment, a test circuit is coupled to receive a first signal from a signal generator such as a test equipment. The test circuit allows access to one or more terminals of a first integrated circuit, a second integrated circuit, or both based at least on the signal. The test circuit may be in the first integrated circuit. The first integrated circuit and the second integrated circuit may be in a single package. In one embodiment, the test circuit routes signals to and from the second integrated circuit, thus allowing the second integrated circuit to be tested as if it was stand-alone. In one embodiment, the test circuit allows access to otherwise inaccessible terminals of the first integrated circuit, the second integrated circuit, or both.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to integrated circuits, and more particularly to methods and apparatus for testing integrated circuits. 
     2. Description of the Background Art 
     Some applications call for the placement of multiple integrated circuits in one package. For example, several dies of integrated circuits may be mounted on a single substrate, which is then encapsulated using plastic or ceramic packaging technology. Putting multiple integrated circuits in one package advantageously minimizes printed circuit board space requirements, and facilitates manufacture of custom devices by combining several off-the-shelf integrated circuits. A single package having multiple integrated circuits is also referred to as a multi-chip module. 
     Multi-chip modules present unique testing problems because embedded integrated circuits may no longer be directly accessible after the packaging process. After packaging, some pads of a die may no longer be able to receive signals from outside the multi-chip module because those pads are connected exclusively to another embedded die. Those pads may also be test pads that are not routed to an external pin of the multi-chip module in order to minimize pin count. 
     Because of difficulties in testing multi-chip modules, some vendors individually test integrated circuits before packaging them together. Once packaged, the integrated circuits are assumed to be good and not extensively tested. This approach ignores the fact that an integrated circuit may fail during the packaging process (and anytime before it leaves the factory). 
     Assembled printed circuit boards and multi-chip modules can be tested using the IEEE 1149.1 standard. The IEEE 1149.1 includes guidelines for boundary scan testing, which is useful in verifying the structural integrity of pin-to-pin connections between integrated circuits mounted on a printed circuit board or multi-chip module. However, the serial nature of IEEE 1149.1 results in relatively long test time and cost. The IEEE 1149.1 also does not take advantage of the testability of individual integrated circuits before they were packaged together in a multi-chip module. 
     SUMMARY 
     The present invention relates to methods and apparatus for testing multiple integrated circuits in a single package. 
     In one embodiment, a test circuit is coupled to receive a signal from a signal generator such as a test equipment. The test circuit allows access to one or more terminals of a first integrated circuit, a second integrated circuit, or both based at least on the signal. The test circuit may be in the first integrated circuit. The first integrated circuit and the second integrated circuit may be in a single package. 
     In one embodiment, the test circuit routes signals to and from the second integrated circuit, thus allowing the second integrated circuit to be tested as if it was stand-alone. 
     In one embodiment, the test circuit allows access to otherwise inaccessible terminals of the first integrated circuit, the second integrated circuit, or both. 
     These and other features and advantages of the present invention will be readily apparent to persons of ordinary skill in the art upon reading the entirety of this disclosure, which includes the accompanying drawings and claims. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a schematic diagram of a system for testing multiple integrated circuits in a single package in accordance with an embodiment of the present invention. 
     FIG. 2 shows a schematic diagram of a device under test in accordance with an embodiment of the present invention. 
     FIG. 3 shows a schematic diagram of a master test circuit in accordance with an embodiment of the present invention. 
     FIG. 4 shows a schematic diagram of a slave test circuit in accordance with an embodiment of the present invention. 
     FIG. 5 illustrates an example inter-connection between a master integrated circuit and a slave integrated circuit in accordance with an embodiment of the present invention. 
    
    
     The use of the same reference label in different drawings indicates the same or like components. 
     DETAILED DESCRIPTION 
     In the present disclosure, numerous specific details are provided, such as examples of apparatus, circuits, components, and methods to provide a thorough understanding of embodiments of the invention. Persons of ordinary skill in the art will recognize, however, that the invention can be practiced without one or more of the specific details. In other instances, well-known details are not shown or described to avoid obscuring aspects of the invention. 
     Referring now to FIG. 1, there is shown a schematic diagram of a system  100  for testing multiple integrated circuits in a single package according to an embodiment of the present invention. System  100  includes a test equipment  101  and a device under test (DUT)  110 . Test equipment  101  may be an automated test equipment (ATE), a system of bench-type signal generators and monitors, or any type of device or instrumentation capable of generating and receiving signals. The type of test equipment used does not detract from the merits of the present invention. 
     In one embodiment, DUT  110  is a multi-chip module having two or more integrated circuits  120  (i.e.,  120 A,  120 B, . . . ,  120   n ) in a single package. Each integrated circuit  120  is embodied in a die; however, each integrated circuit  120  may also be embodied in other forms. During testing, test equipment  101  sends stimulus signals  102  to DUT  110 . Stimulus signals  102  may include any type of test pattern or sequence designed to test the functionality of DUT  110 . Response signals  103  are generated by DUT  110  in response to stimulus signals  102 . As depicted in FIG. 1, stimulus signals  102  and response signals  103  are on two sets of unidirectional lines. It should be understood, however, that stimulus signals  102  and response signals  103  (and all other signals in the present disclosure) may also be on bi-directional lines. 
     FIG. 2 shows a schematic diagram further illustrating the components of a DUT  110  in accordance with an embodiment of the present invention. DUT  110  includes a bus  205  coupled to a package interface  210 . In the present disclosure, the word “bus” broadly refers to any set of lines for carrying signals. Because integrated circuits  120  are in die form in this embodiment, signals are coupled to an integrated circuit  120  via die pads. Specifically, bus  205  is coupled to the die pads of integrated circuits  120 A. 
     Package interface  210  couples DUT  110  to the outside world. For example, a test equipment  101  may be coupled to DUT  110  via package interface  210 . Package interface  210  may include pins, balls, bumps, etc. 
     DUT  110  may also include one or more inner-busses, which in the example of FIG. 2 are denoted as inner-bus  215  and inner-bus  216 . Inner-bus  215  couples integrated circuit  120 A to integrated circuit  120 B, whereas inner-bus  216  couples integrated circuit  120 B to integrated circuit  120   n . It is to be noted that the signal line connections and integrated circuits arrangement shown in FIG. 2 are provided for illustration purposes only. As can be appreciated, embodiments of the present invention may be adapted to test other configurations of multi-chip modules. 
     Ordinarily, because of their location deep in DUT  110  and because DUT  110  may be covered by packaging material, inner-busses  215  and  216  would be difficult to control and observe from package interface  210 . Thus, without the use of embodiments of the present invention, comprehensive testing of DUT  110  would be very difficult to perform. However, in embodiments of the present invention, DUT  110  includes a test circuit in integrated circuits  120  for controlling and observing one or more inner-buses. This facilitates direct access of inner-busses  215  and  16 , thereby facilitating comprehensive testing of embedded integrated circuits such as integrated circuit  120 B. 
     In the example of FIG. 2, integrated circuit  120 A is designated as a master integrated circuit (“master IC”) and accordingly includes a master test circuit  201 . The remaining integrated circuits  120  are each designated as a slave integrated circuit (“slave IC”) and each includes a slave test circuit  231 . That is, integrated circuit  120 A is designated as the master IC, while integrated circuits  120 B, . . . ,  120   n  are designated as slave ICs. Generally speaking, any integrated circuit  120  may be designated as the master IC. However, the master IC is advantageously the integrated circuit  120  with the most direct lines to package interface  210 . For example, in a multi-chip module having a microprocessor and several supporting integrated circuits, the microprocessor is advantageously designated as the master IC if it has a lot of lines that directly lead to the module pins. Each master test circuit  201  and slave test circuit  231  may be incorporated within an integrated circuit  120  as shown in FIG. 2, or implemented within DUT  110  but outside an integrated circuit  120 . Advantageously, a test circuit is fabricated in an unused section of an integrated circuit to save space. 
     Still referring to FIG. 2, master test circuit  201  enables direct access of signal lines on the slave ICs. Master test circuit  201  may be controlled by an apparatus external to DUT  110  (e.g., test equipment  101 ) using test interface lines  221 . Test interface lines  221  may be used to place DUT  110  in test mode, to select a particular test mode (e.g., a test sequence), or to place certain input/output (I/O) lines of integrated circuit  120 A in a certain state. Test interface lines  221  typically go through package interface  210 , but are separately depicted in FIG. 2 for illustration purposes. 
     Master test circuit  201  also includes test control lines  220  for sending command signals to each slave test circuit  231 . Master test circuit  201  may select a slave test circuit  231  and place it in a particular test mode. Master test circuit  201  may also command one or more slave test circuits  231  to feed-through particular signal lines to package interface  210 . That is, master test circuit  201  and slave test circuits  231  may include switching logics (e.g., multiplexers) for routing signals. For example, package interface  210  may be coupled to inner-bus  216  by routing the lines of inner-bus  216  through master test circuit  201  and slave test circuit  231  of integrated circuit  120 B. Thereafter, integrated circuit  120   n  may be comprehensively tested because most of its die pads will then be accessible from package interface  210 . Additionally, integrated circuit  120   n  may then be coupled to a test equipment  101  and tested as a stand-alone integrated circuit. Thus, test programs developed for testing integrated circuit  120   n  by itself may be used to test integrated circuit  120   n  in a multi-chip DUT  110 . 
     Master test circuit  201  may also command a slave test circuit  231  to initiate an internal test mode of a slave IC, or to place the slave IC&#39;s I/O control lines in a certain state. 
     FIG. 3 shows a schematic diagram of a master test circuit  201  in accordance with an embodiment of the present invention. Master test circuit  201  includes a master test decode logic  301 , routing logic  310 , and routing logic  320 . In one embodiment, master test decode logic  301  includes combinational logic for receiving command signals over package interface  210 , for selecting and controlling slave test circuits  231 , for controlling routing logics  310  and  320 , and for placing the I/O control pads of the master IC in a certain state. 
     In the example of FIG. 3, master test decode logic  301  receives test mode lines  302  and test mode enable line  303 . Test mode lines  302  and test mode enable line  303  may be part of test interface lines  221 , and received through package interface  210  (see FIG.  2 ). DUT  110  is placed in normal function mode when test mode enable line  303  is unasserted. When in normal function mode, signals within DUT  110  are routed as if there were no test circuits in DUT  110 . That is, integrated circuits  120  are coupled and configured for normal operation when DUT  110  is in normal function mode. 
     Asserting test mode enable line  303  places DUT  110  in test mode. When DUT  110  is in test mode, slave ICs may be controlled by the master IC for testing purposes. Also when in test mode, master test decode logic  301  decodes the signals on test mode lines  302  to interpret and execute command signals received from a test equipment  101 . For example, test mode lines  302  may include several lines, with each combination of signals on the lines representing a particular command. 
     I/O control lines  306  may be coupled to the I/O control pads of the master IC. Each line of I/O control lines  306  may be controlled by sending command signals on test mode lines  302 . For example, the 110 control pads of the master IC may not be accessible from package interface  210  by design. To place the I/O control pads of the master IC in a certain state, a test equipment  101  may assert test mode enable line  303  to place DUT  110  in test mode, and then send command signals on test mode lines  302  to manipulate (e.g., by setting or resetting) each line of I/O control lines  306 . Signals on I/O control lines  306  may initiate an internal test of the master IC, place the master IC in a known state prior to sending stimulus signals to the master IC, or control an otherwise inaccessible pad of the master IC, for example. 
     Slave test mode lines  307  and slave select lines  308  may be part of test control lines  220  (see FIG. 2) and go to each slave test circuit  231 . Signals on slave select lines  308  select a particular slave test circuit  231 , while signals on slave test mode lines  307  specify a test mode for the selected slave test circuit  231 . Each line of slave test mode lines  307  and slave select lines  308  are controllable by sending appropriate command signals on test mode lines  302 . For example, command signals may be sent on test mode lines  302  to select a particular slave test circuit  231  using slave select lines  308 . Command signals may also be sent on test mode lines  302  to select a particular test mode for the selected slave test circuit  231  using slave test mode lines  307 . 
     In one embodiment, a slave IC may be tested by first selecting it&#39;s slave test circuit  231  and then performing the test. Thereafter, the next slave IC may be selected and tested, and soon. 
     Command signals may be sent on test mode lines  302  to control routing logics  310  and  320  using control lines  304  and  305 , respectively. Routing logics  310  and  320  may be multiplexers, for example. Routing logic  310  includes input nodes  311  for receiving signals from package interface  210 . Routing logic  310  also includes input nodes  312  for receiving signals ordinarily routed to a designated slave IC during normal operation. That is, signals that go to a slave IC during normal operation are coupled to input nodes  312 . Routing logic  310  also includes output nodes  313  leading to a slave IC. Using control lines  304 , either the signals on input nodes  311  or the signals on input nodes  312  may be routed to output nodes  313 . 
     During normal operation, the signals on input nodes  312  may be routed to output nodes  313 . During testing, the signals on input nodes  311  may be routed to output nodes  313 . This advantageously allows an external apparatus such as a test equipment  101  to directly send stimulus signals  102  (see FIG. 1) to an embedded slave IC during testing. 
     Routing logic  320  includes input nodes  321  for receiving signals from a slave IC. Routing logic  320  also includes input nodes  322  for receiving signals ordinarily routed to package interface  210  during normal operation. For example, signals going from a master IC to package interface  210  during normal operation may be coupled to input nodes  322 . Routing logic  320  also includes output nodes  323  leading to package interface  210 . Using control lines  305 , either the signals on input nodes  321  or the signals on input nodes  322  may be routed to output nodes  323 . 
     During normal operation, the signals on input nodes  322  may be routed to output nodes  323 . During testing, the signals on input nodes  321  may be routed to output nodes  323 . This advantageously allows an external apparatus such as a test equipment  101  to directly receive response signals  103  (see FIG. 1) from an embedded slave IC during testing. 
     Referring now to FIG. 4, there is shown a slave test circuit  231  in accordance with an embodiment of the present invention. Slave test circuit  231  includes a slave test decode logic  401 , routing logic  410 , and routing logic  420 . In one embodiment, slave test decode logic  401  includes combinational logic for receiving command signals from a master test circuit  201 , for controlling routing logics  410  and  420 , and for placing the I/O control pad of the slave IC in a certain state. 
     In the example of FIG. 4, slave test decode logic  401  receives slave test mode lines  402  and slave test mode enable line  403 . Slave test mode lines  402  may be part of test control lines  220  (see FIG.  2 ), and may be coupled to slave test mode lines  307  of a master test circuit  201  (see FIG.  3 ). Slave test mode enable line  403  may be derived by decoding slave select lines  308  of a master test circuit  201 . 
     Slave test circuit  231  may be placed in test mode by asserting slave test mode enable line  403 . When in test mode, slave test decode logic  401  decodes command signals on slave test mode lines  402 . For example, slave test mode lines  402  may include several lines, with each combination of signals on the lines representing a particular command from a master test circuit  201 . 
     I/O control lines  406  may be coupled to the I/O control pads of the slave IC. Each line of I/O control lines  406  may be controlled by sending command signals on test slave mode lines  402 . For example, the I/O control pads of the slave IC may not be accessible from package interface  210  by design. To place the I/O control pads of the slave IC in a certain state, a command to do so may be sent to master test circuit  201 . In response, master test circuit  201  may then send the appropriate command signals on slave test mode lines  402  to manipulate each line of I/O control lines  406 . Signals on I/O control lines  406  may initiate an internal test of the slave IC, place the slave IC in a known state prior to sending stimulus signals to the slave IC, or control an otherwise inaccessible pad of the slave IC, for example. 
     Command signals may be sent on slave test mode lines  402  to manipulate lines  407 , which may be coupled to internal nodes of the slave IC. For example, lines  407  may be manipulated to initiate an internal test of the slave IC or to place the slave IC in a particular mode. As can be appreciated, lines  407  may be coupled to nodes that may otherwise be inaccessible for testing or other purposes. 
     Command signals may be sent on slave test mode lines  402  to control routing logics  410  and  420  using control lines  404  and  405 , respectively. Routing logics  410  and  420  may be multiplexers, for example. Routing logic  410  includes input nodes  411  for receiving signals to be routed to another slave IC, a master IC, or package interface  210 . For example, lines of the slave IC that may otherwise be inaccessible may be coupled to input nodes  411 . As another example, lines originating from another slave IC may be coupled to input nodes  411 . This allows signals from one slave IC to be transmitted through another slave IC for routing to the master IC or package interface  210 . 
     Routing logic  410  includes input nodes  412  for receiving signals ordinarily routed to another slave IC, a master IC, or package interface  210  during normal operation. For example, signals that go from the slave IC to the master IC during normal operation may be coupled to input nodes  412 . Routing logic  410  also includes output nodes  413  leading to another slave IC, a master IC, or package interface  210 . Using control lines  404 , either the signals on input nodes  411  or the signals on input nodes  412  may be routed to output nodes  413 . 
     During normal operation, the signals on input nodes  412  may be routed to output nodes  413 . During testing and depending on the test, either the signals on input nodes  411  or the signals on input nodes  412  may be routed to output nodes  413 . This advantageously allows an external apparatus such as a test equipment  101  to directly receive response signals  102  (see FIG. 1) from an embedded slave IC during testing. 
     Routing logic  420  includes input nodes  421  for receiving signals ordinarily routed to another slave IC, a master IC, or package interface  210  during normal operation. During normal operation, routing logic  420  may be used to route signals to one destination (e.g., integrated circuit  120   n ) while routing logic  410  may be used to route signals to another destination (e.g., integrated circuit  120 A). 
     Routing logic  420  includes input nodes  422  for receiving signals to be routed to another slave IC, a master IC, or package interface  210 . For example, lines of the slave IC that may otherwise be inaccessible may be coupled to input nodes  422  for routing to package interface  210 . As another example, input nodes  422  may be used to feed-through lines originating from another slave IC. 
     Routing logic  420  also includes output nodes  423 , which lead to another slave IC, a master IC, or package interface  210 . Using control lines  405 , either the signals on input nodes  421  or the signals on input nodes  422  may be routed to output nodes  423 . 
     During normal operation, the signals on input nodes  421  may be routed to output nodes  423 . During testing and depending on the test, either the signals on input nodes  422  or the signals on input nodes  421  may be routed to output nodes  423 . 
     An example inter-connection between a master IC and a slave IC is now described with reference to the schematic diagram of FIG.  5 . In the example of FIG. 5, integrated circuit  120 A is designated as the master IC and accordingly includes a master test circuit  201 ; integrated circuit  120 B is designated as a slave IC and accordingly includes a slave test circuit  231 . Only the routing logics of the test circuits are shown in FIG. 5 for clarity. Additionally, the inter-connection shown in FIG. 5 may be extended to accommodate additional slave ICs. 
     In the example of FIG. 5, lines from package interface  210  are coupled to input nodes  311  via die pads  501 . Lines from integrated circuit  120 A that go to integrated circuit  120 B during normal operation are coupled to input nodes  312 . Thus, during normal operation, signals on input nodes  312  are coupled to integrated circuit  120 B via routing logic  310 , output nodes  313 , die pads  502 , and die pads  503 . During testing, signals on input nodes  311  are coupled to integrated circuit  120 B via routing logic  310 , output nodes  313 , die pads  502 , and die pads  503 . For example, a test equipment  101  may directly send stimulus signals to integrated circuit  120 B via package interface  210 , pads  501 , input nodes  311 , routing logic  310 , output nodes  313 , die pads  502 , and die pads  503 . 
     Signals that go from integrated circuit  120 A to package interface  210  during normal operation are transmitted over input nodes  322 , routing logic  320 , output nodes  323 , and die pads  501 . 
     In the example of FIG. 5, lines that go from integrated circuit  120 B to integrated circuit  120 A during normal operation are coupled to input nodes  412 . During normal operation, signals on input nodes  412  are coupled to integrated circuit  120 A via routing logic  410 , output nodes  413 , die pads  503 , and die pads  502 ; from die pads  502 , the signals may then go to other nodes of integrated circuit  120 A. 
     During testing, signals on input nodes  411  or input nodes  412  may be coupled to package interface  210  via routing logic  410 , output nodes  413 , die pads  503 , die pads  502 , input nodes  321 , routing logic  320 , output nodes  323 , and die pads  501 . This allows signals that may otherwise be inaccessible to be routed to package interface  210 . For example, signals on input nodes  412  may be received by a test equipment  101  coupled to package interface  210 . Similarly, signals on input nodes  411  (which may be originating from other slave ICs or otherwise inaccessible lines of integrated circuit  120 B) may also be received by a test equipment  101  coupled to package interface  210 . 
     In the example of FIG. 5, routing logic  420  includes output nodes  423  coupled to die pads  504 . Die pads  504 , in turn, may be coupled to integrated circuit  120 A, another slave IC, or to package interface  210 . During normal operation, the signals on input nodes  421  are routed to output nodes  423 . During testing and depending on the test, either the signals on input nodes  421  or input nodes  422  may be routed to output nodes  423  and onto die pads  504 . 
     Still referring to the example of FIG. 5, integrated circuit  120 B may be tested stand-alone by sending stimulus signals to integrated circuit  120 B via package interface  210 , die pads  501 , input nodes  311 , routing logic  310 , output nodes  313 , die pads  502 , and die pads  503 . The stimulus signals may be developed using Automatic Test Pattern Generation (ATPG) software and generated by a test equipment  101  coupled to package interface  210 , for example. Response signals from integrated circuit  120 B may be routed via input nodes  411  or  412 , routing logic  410 , output nodes  413 , die pads  503 , die pads  502 , input nodes  321 , routing logic  320 , output nodes  323 , die pads  501 , and package interface  210 . 
     As can be appreciated, embodiments of the present invention allow for comprehensive testing of multi-chip modules. By routing otherwise inaccessible signals to and from the package interface, the integrated circuits in the multi-chip module may be comprehensively tested. Additionally, the integrated circuits may be tested using test programs designed for testing individual integrated circuits. Among other advantages, this simplifies testing of multi-chip modules, reduces test development time, and also facilitates debugging of failed modules. Embodiments of the present invention also allow for comprehensive testing of multi-chip modules by providing a way to control otherwise inaccessible lines (e.g., I/O control pads, internal nodes) of an integrated circuit. Thus, embodiments of the present invention help increase test coverage, which in turn results in lower multi-chip module failures in the field. 
     Improved techniques for testing multiple integrated circuits in a single package have been disclosed. While specific embodiments have been provided, it is to be understood that these embodiments are for illustration purposes and not limiting. Many additional embodiments will be apparent to persons of ordinary skill in the art reading this disclosure. Thus, the present invention is limited only by the following claims.