Abstract:
A system circuit board and a computer are presented. The system circuit board includes a processor and a hard disk (HD) indicator circuit. The HD indicator circuit includes a first switch, a first light-emitting diode, a second switch, a second light-emitting diode, an inverting circuit, and a third light-emitting diode. The first switch is electrically connected between a first pin of the processor and the first light-emitting diode. The second switch is electrically connected between a second pin of the processor and the second light-emitting diode. The inverting circuit is connected between the second pin and the third light-emitting diode. Therefore, the second light-emitting diode and the third light-emitting diode share the second pin, so that the processor can execute more functions, and the number of resistors required by the HD indicator circuit is reduced.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This non-provisional application claims priority under 35 U.S.C. § 119(a) on Patent Application No(s). 201210414860.0 filed in China on Oct. 25, 2012, the entire contents of which are hereby incorporated by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Technical Field of the Invention 
         [0003]    The disclosure relates to a system circuit board used for presenting an operational status of an electronic device, and more particularly to a system circuit board including a hard disk (HD) indicator circuit, and a computer. 
         [0004]    2. Description of the Related Art 
         [0005]    With the vigorous development of networks, the management of a network storage device becomes more important, and a network storage server may manage and control a Hard Disk (HD) in the following methods. In one method, a processor in a main system is directly used to manage and control an HD. In another method, a processor dedicated to management and control of an HD is added to a Serial Advanced Technology Attachment (SATA) backplane connected to the HD. In still another method, a monitoring device which is installed on a SATA backplane and is independent of a main system, is used to monitor multiple HDs connected to the SATA backplane. During the management and control of an HD, the status of the HD is displayed in a visualized manner by multiple light-emitting diodes connected to the processor. 
         [0006]    A circuit for displaying an operational status of an HD generally uses three separated circuits to respectively control the on/off of light-emitting diodes with three different colors, and each of the circuits occupies a pin of a processor. For a 2.5-inch HD backplane, when the number of HDs is 24, all the pins of the processor is occupied. In this case, if a designer intends to add a control function to the processor (for example, add a function of determining the status of a Serial Attached SCSI (SAS) HD and the status of a SATA HD), the implementation fails because the pins of the processor are all occupied. 
       SUMMARY OF THE INVENTION 
       [0007]    A system circuit board disclosed by the disclosure comprises a processor and an HD indicator circuit. The HD indicator circuit comprises a first switch, a first light-emitting diode, a second switch, a second light-emitting diode, an inverting circuit, and a third light-emitting diode. 
         [0008]    The first switch is electrically connected to a first pin of the processor, and is switched on or off according to a first control signal provided by the first pin. The first light-emitting diode is connected to the first switch, and used for emitting light when the first switch is switched on. The second switch is electrically connected to a second pin of the processor, and is switched on or off according to a second control signal provided by the second pin. The second light-emitting diode is connected to the second switch, and is used for emitting light when the second switch is switched on. The inverting circuit is connected to the second pin, and is used for inverting the second control signal. The third light-emitting diode is connected to the inverting circuit, and is used for determining whether to emit light or not, according to the inverted second control signal. 
         [0009]    A computer disclosed by the disclosure comprises a system circuit board. The system circuit board comprises a processor and an HD indicator circuit. The HD indicator circuit comprises a first switch, a first light-emitting diode, a second switch, a second light-emitting diode, an inverting circuit, and a third light-emitting diode. 
         [0010]    The first switch is electrically connected to a first pin of the processor, and is switched on or off according to a first control signal provided by the first pin. The first light-emitting diode is connected to the first switch, and is used for emitting light when the first switch is switched on. The second switch is electrically connected to a second pin of the processor, and is switched on or off according to a second control signal provided by the second pin. The second light-emitting diode is connected to the second switch, and is used for emitting light when the second switch is switched on. The inverting circuit is connected to the second pin, and is used for inverting the second control signal. The third light-emitting diode is connected to the inverting circuit, and is used for determining whether to emit light or not, according to the inverted second control signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The disclosure will become more fully understood from the detailed description given herein below for illustration only, and thus does not limit the disclosure, wherein: 
           [0012]      FIG. 1  is a schematic structural view of an HD indicator circuit according to an embodiment of the disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0013]    In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing. 
         [0014]    In this embodiment, a circuit used for presenting an operational status of an electronic device is disposed in a system circuit board. The system circuit board is disposed in a system device, and used for controlling and monitoring the operation of the electronic device in the system device. 
         [0015]    In this embodiment and some other embodiments, the system device is a computer, the system circuit board is a motherboard, and the electronic device is a HD, but the disclosure is not limited thereby. The system circuit board presents an operational status of the HD in real time through an HD indicator circuit provided by the disclosure. 
         [0016]      FIG. 1  is a schematic structural diagram of a HD indicator circuit according to an embodiment of the disclosure. The HD indicator circuit is disposed on a system circuit board, and connected to a processor on the system circuit board. The HD indicator circuit comprises resistors R 1  and R 2 , a first switch Q 1 , a first light-emitting diode PR, a second switch Q 2 , a second light-emitting diode PG, an inverting circuit, a third light-emitting diode PY, and a common resistor R 4 . 
         [0017]    In this embodiment and some other embodiments, the light emitted by the first light-emitting diode PR is red, the light emitted by the second light-emitting diode PG is green, and the light emitted by the third light-emitting diode PY is orange, but the disclosure is not limited thereby. In this embodiment and some other embodiments, the first switch Q 1  and the second switch Q 2  are, for example, transistors. 
         [0018]    The gate of the first switch Q 1  is connected to a first pin P 1  of the processor through the resistor R 1 . The source of the first switch Q 1  is grounded and connected to the anode of a diode D 1 . The drain of the first switch Q 1  is connected to the cathode of the diode D 1  and to the cathode of the first light-emitting diode PR. The anode of the first light-emitting diode PR is connected to one end of the common resistor R 4 . The another end of the common resistor R 4  is connected to a second power supply terminal V 2 . The first switch Q 1  is switched on according to the status of a first control signal provided by the first pin P 1 . 
         [0019]    The gate of the second switch Q 2  is connected to a second pin P 2  of the processor through the resistor R 2 . The source of the second switch Q 2  is grounded and connected to the anode of a diode D 2 . The drain of the second switch Q 2  is connected to the cathode of the diode D 2  and to the cathode of the second light-emitting diode PG. The anode of the second light-emitting diode PG is connected to the common resistor R 4 . The second switch Q 2  is switched on according to the status of a second control signal provided by the second pin P 2 . 
         [0020]    The inverting circuit comprises a resistor R 3 , diodes D 3  and D 4 , a third switch Q 3 , and a fourth switch Q 4 , and is used for inverting the second control signal provided by the second pin P 2 . In this embodiment and some other embodiments, the third switch Q 3  and the fourth switch Q 4  are, for example, transistors. In this embodiment and some other embodiments, the diodes D 3  and D 4  are, for example, Zener diodes. 
         [0021]    The gate of the third switch Q 3  is connected to the second pin P 2 . The base of the third switch Q 3  is grounded. The source of the third switch Q 3  is connected to the anode of the Zener diode D 3 . The drain of the third switch Q 3  is connected to the cathode of the Zener diode D 3 , to one end of the resistor R 3 , and to the gate of the fourth switch Q 4 . The other end of the resistor R 3  is connected to a first power supply terminal V 1 . The base of the fourth switch Q 4  is grounded. The source of the fourth switch Q 4  is connected to the anode of the Zener diode D 4 . The drain of the fourth switch Q 4  is connected to the cathode of the Zener diode D 4  and to the cathode of the third light-emitting diode PY. The anode of the third light-emitting diode PY is connected to the common resistor R 4 . 
         [0022]    When the status of the first control signal provided by the first pin P 1  is at a high level, the first switch Q 1  is switched on, and a current flows from the second power supply terminal V 2  to the first light-emitting diode PR through the first light-emitting diode PR to drive the first light-emitting diode PR to emit light. When the status of the first control signal provided by the first pin P 1  is at a low level, the first switch Q 1  is switched off, and no current flows from the second power supply terminal V 2  to the first light-emitting diode PR through the first light-emitting diode PR. Herein, the first light-emitting diode PR does not emit light. 
         [0023]    When the status of the second control signal provided by the second pin P 2  is at a high level, the second switch Q 2  is switched on, and a current flows from the second power supply terminal V 2  to the second light-emitting diode PG through the second light-emitting diode PG to drive the second light-emitting diode PG to emit light. Herein, the third switch Q 3  and the fourth switch Q 4  are switched off, so that the third light-emitting diode PY does not emit any light. 
         [0024]    When the status of the second control signal provided by the second pin P 2  is at a low level, the second switch Q 2  is switched off Herein, no current flows from the second power supply terminal V 2  to the second light-emitting diode PG through the second light-emitting diode PG, so that the second light-emitting diode PG does not emit light. In this case, the third switch Q 3  and the fourth switch Q 4  are switched on, and a current flows from the second power supply terminal V 2  to the third light-emitting diode PY through the third light-emitting diode PY to drive the third light-emitting diode PY. 
         [0025]    Through the foregoing operations, the computer can use the three light-emitting diodes to notify users the operation status of the HD. The detailed notification manner is described as follows. 
         [0026]    When detecting no HD, the processor turns off the first light-emitting diode PR, the second light-emitting diode PG, and the third light-emitting diode PY. 
         [0027]    When detecting that an HD exits, the processor switches the second light-emitting diode PG on, and turns off the third light-emitting diode PY. Simultaneously, the first light-emitting diode PR operates according to the status of the first pin P 1 . 
         [0028]    When detecting that the HD operates inappropriately or is interrupted during rebuilding, the processor turns off the second light-emitting diode PG, and switches the third light-emitting diode PY on. Simultaneously, the first light-emitting diode PR operates according to the status of the first pin P 1 . 
         [0029]    When detecting that the HD is being rebuilt, the processor switches the first light-emitting diode PR and the second light-emitting diode PG on alternately. For example, the second light-emitting diode PG is switched on for 400 micro-seconds (ms) while the third light-emitting diode PY is turned off for 400 micro-seconds. The first light-emitting diode PR operates according to the status of the first pin P 1 . Afterward, the second light-emitting diode PG is turned off for 100 ms, while the third light-emitting diode PY is switched on for 100 micro-seconds. The first light-emitting diode PR operates according to the status of the first pin P 1 . 
         [0030]    When detecting that the HD is successfully installed, the processor alternately switches on the second light-emitting diode PG and the third light-emitting diode PY in a way different from that in the rebuilding of the HD. For example, the second light-emitting diode PG is switched on for 250 ms while the third light-emitting diode PY is turned off for 250 ms. Afterward, the processor turns off the second light-emitting diode PG for 250 ms while switches the third light-emitting diode PY on for 250 ms. The first light-emitting diode PR operates according to the status of the first pin P 1 . 
         [0031]    The status of the first pin P 1  changes according to the operational status of the HD. The above embodiments are not intended to limit the disclosure. 
         [0032]    In this example, a voltage value of the first power supply terminal V 1  is smaller than a voltage value of the second power supply terminal V 2 . 
         [0033]    Through the inverting circuit, the second light-emitting diode PG and the third light-emitting diode PY are capable of sharing one pin of the processor. Therefore, the processor can spare one pin for performing other control functions, and the number of resistors required in the circuit used for presenting an operational status of an electronic device is reduced as compared with the case that the light-emitting diodes are connected one-to-one to the pins of the processor. 
         [0034]    Further, through the common resistor R 4 , the number of resistors required when the light-emitting diodes are connected to the first power supply terminal, is reduced in the circuit for presenting an operational status of an electronic device. 
         [0035]    The disclosure may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the disclosure is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.