Abstract:
A booster circuit includes a first transistor performing a first on-off operation based on a first control signal and a second transistor performing a second on-off operation based on the first control signal. The first on-off operation and the second on-off operation are reversed. A third transistor performs the first on-off operation based on a second control signal. The second control signal has a phase opposite the first control signal. A fourth transistor is included in a metal oxide semiconductor capacitor.

Description:
BACKGROUND 
   1. Technical Field 
   The present invention relates to a semiconductor device and a booster circuit, and is particularly preferable to apply to a switched-capacitor DC-DC converter. 
   2. Related Art 
   In recent years, accompanying the developments of semiconductor manufacturing processes, semiconductor integrated devices have been integrated in highly density and become multifunctional. As a result, a power supply voltage inside a semiconductor integrated device circuit tends to be lowered. In addition, various power supply sources including high voltage power supply sources have been incorporated as the semiconductor integrated circuits become multifunctional. For example, a high voltage of 10 V or more is required in nonvolatile memories such as flash memories, and EEPROMs, and driver ICs for display elements such as liquid crystal displays. Thus, a charge pump method, which is easily incorporated into the semiconductor integrated devices, is employed as a booster circuit to generate such high voltage instead of a switching regulator method using coils and so on. As the charge pump method, Dickson charge pump circuit is typically used. 
   In order to achieve higher conversion efficiency than the charge pump circuit, a method using a DC-DC converter that employs a switched-capacitor method, i.e. switched-capacitor DC-DC converter, as a booster circuit is disclosed in JP-A-2004-172631. In the switched-capacitor method, a plurality of kick capacitors to which power supply voltage is applied parallel, is switched to be connected in series by a switching element, thereby a boosted output voltage can be output. 
   However, in a case where a kick capacitor used for the switched-capacitor method is structured by a MOS capacitor, a problem arises in that boosted voltage is lowered since a depletion layer capacitance formed along a bonded surface of a well and a substrate acts as a parasitic capacitance. 
   In contrast, in a case where the kick capacitor is structured by a SiO 2 /Si 3 N/SiO 2  (ONO) capacitor having a polysilicon layer as its upper and lower electrodes, a problem arises in that an element area increases. 
   SUMMARY 
   An advantage of the invention is to provide a semiconductor device and a booster circuit that can reduce the parasitic capacitance of a kick capacitor while increasing of the element area is depressed. 
   A semiconductor device according to a first aspect of the invention includes: a semiconductor substrate; a buried oxide (BOX) layer formed on the semiconductor substrate; a semiconductor layer formed on the BOX layer; a plurality of metal oxide semiconductor (MOS) capacitors formed on the semiconductor layer; and a switching element formed on the semiconductor substrate. The switching element switches a first condition in which the plurality of MOS capacitors are connected parallel so that a direct current voltage is applied in common to the plurality of MOS capacitors, and a second condition in which the plurality of MOS capacitors connected parallel is connected in series. 
   According to the first aspect of the invention, a BOX layer capacitance can be capacitively coupled in series with a depletion layer capacitance formed in the semiconductor substrate, thereby a parasitic capacitance that acts to the MOS capacitor can be reduced. As a result, a kick capacitor used in a switched capacitor method can be structured by a MOS capacitor while the parasitic capacitance is lowered, thereby a boosted voltage can be increased while increasing of an element area is depressed. 
   In the semiconductor device according to the first aspect of the invention, the switching element may be formed in a bulk region of the semiconductor substrate. 
   This makes it possible to prevent a breakdown voltage of the switching element from being deteriorated even in a case where the MOS capacitor includes a silicon on insulator (SOI) structure. As a result, a boosted voltage can be increased. 
   A booster circuit according to a second aspect of the invention includes: a first electric field effect transistor performing a first on-off operation based on a first control signal; a second electric field effect transistor performing a second on-off operation based on the first control signal, the first on-off operation and the second on-off operation being reversed; a third electric field effect transistor performing the first on-off operation based on a second control signal having a phase opposite the first control signal; and a fourth electric field effect transistor included in a MOS capacitor. Sources of the first electric field effect transistor and the second electric field effect transistor are coupled to a gate of the fourth electric field effect transistor, a drain of the first electric field effect transistor is coupled to a source of the third electric field effect transistor, a drain of the third electric field effect transistor is coupled to a source and a drain of the fourth electric field effect transistor, and the fourth electric field effect transistor includes a silicon on insulator (SOI) structure. 
   According to the second aspect of the invention, a BOX layer capacitance can be capacitively coupled in series with a depletion layer capacitance formed under the channel of the fourth electric field effect transistor, thereby a parasitic capacitance that acts to the MOS capacitor can be reduced even in a case where the MOS capacitor is structured by the fourth electric field effect transistor. As a result, a kick capacitors used in a switched capacitor method can be structured by a MOS capacitor while the parasitic capacitance is lowered, thereby a boosted voltage can be increased while increasing of an element area is depressed. 
   In the booster circuit, the thickness of a buried oxide film of the SOI structure is preferably 10 nm or more, more preferably 57 nm or more. 
   In the booster circuit according to the second aspect of the invention, the first through third electric field effect transistors may be formed on a bulk substrate. 
   This makes it possible to prevent a breakdown voltage of the first through third electric field effect transistors from being deteriorated even in a case where the MOS capacitor includes an SOI structure. As a result, a boosted voltage can be increased. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be described with reference to the accompanying drawings, wherein like numbers reference like elements. 
       FIG. 1  is a circuit diagram illustrating the schematic structure of a booster circuit according to one embodiment of the present invention. 
       FIGS. 2A and 2B  are circuit diagrams illustrating the operation of the booster circuit in  FIG. 1 . 
       FIG. 3  shows a relation between the boosted voltage and the parasitic capacitance of the booster circuit in  FIG. 1 . 
       FIGS. 4A and 4B  are cross-sectional views and equivalent circuit diagrams illustrating the structure of the kick capacitor of the booster circuit in  FIG. 1  compared to an example of related art. 
       FIG. 5  shows a circuit structure of one stage of the booster circuit in  FIG. 1 . 
       FIG. 6  shows a layout pattern of one stage of the booster circuit in  FIG. 1 . 
   

   DESCRIPTION OF EXEMPLARY EMBODIMENTS 
   A booster circuit device according to an embodiment of the present invention will be described below with reference to accompanying drawings. 
     FIG. 1  is a circuit diagram illustrating the schematic structure of a booster circuit according to the embodiment of the present invention. 
   In  FIG. 1 , the booster circuit includes 6 stages of kick capacitors, i.e. 6 kick capacitors C 1  to C 6 , storing an electric charge according to a voltage of a direct current power supply source VDD. The booster circuit also includes switches SW 0  to SW 5 , and SW 11  to SW  16 , which connect the kick capacitors C 1  to C 6  in parallel to the direct current power supply source VDD, and switches SW 6  to SW 10  and SW 17 , which connect the kick capacitors C 1  to C 6  connected in parallel to the direct current power supply source VDD in series. Further, the booster circuit includes a switch SW 18  that outputs a boosted voltage boosted by the kicked capacitors C 1  to C 6 , and a capacitor CL that separates the switch SW 18  from the direct current power supply source VDD. 
   Here, the kick capacitors C 1  to C 6  can be structured by a MOS capacitor having an SOI structure. In the kick capacitors C 1  to C 6  structured by the MOS capacitor having the SOI structure, a parasitic capacitance Csub 1  of the kick capacitors C 1  to C 6  is produced. The parasitic capacitance Csub 1  is composed of depletion layer capacitances Cd 1  to Cd 6  formed in a semiconductor substrate, and BOX layer capacitances CB 1  to CB 6 . Each of the depletion layer capacitances Cd 1  to Cd 6  is capacitively coupled in series with respective BOX layer capacitances CB 1  to CB 6 . 
     FIGS. 2A and 2B  are circuit diagrams illustrating the operation of the booster circuit in  FIG. 1 . 
   In  FIG. 2A  illustrating a charge operation, the kick capacitors C 1  to C 6  are connected in parallel to the direct current power supply source VDD by turning on the switches SW 0  to SW 5 , and SW 11  to SW 16 , while turning off the switches SW 6  to SW 10 , SW 17 , and SW 18 . As a result, a voltage supplied from the direct power supply source VDD is applied to each of the kick capacitors C 1  to C 6 , thereby an electric charge according to the voltage supplied from the direct power supply source VDD is charged in each of the kick capacitors C 1  to C 6 . 
   In  FIG. 2B  illustrating a pump-up operation, the kick capacitors C 1  to C 6  are connected in series with the direct current power supply source VDD by turning off the switches SW 0  to SW 5 , and SW 11  to SW 16 , while turning on the switches SW 6  to SW 10 , SW 17 , and SW 18 . As a result, each voltage applied to each of the kick capacitors C 1  to C 6  by the direct current power supply source VDD, and the voltage supplied from the direct current power supply source VDD are added and output, thereby a boosted voltage according to the number of connecting stages of the kick capacitors C 1  to C 6  can be obtained. 
   In this regard, if the parasitic capacitance Csub 1  is present in the kick capacitors C 1  to C 6 , the boosted voltage obtained by the pump-up operation is lowered. 
     FIG. 3  shows a relation, which is obtained by a calculation, between the boosted voltage of the booster circuit in  FIG. 1  and the parasitic capacitance. 
   As is clear from  FIG. 3 , the more the parasitic capacitance Csub of kick capacitor increases, the more the boosted voltage HVOUT obtained by the pump-up operation decreases. 
   Accordingly, the kick capacitors C 1  to C 6  in  FIG. 1  that are structured by the MOS capacitor having the SOI structure allow each of the BOX layer capacitances CB 1  to CB 6  to be capacitively coupled in series with each of the depletion layer capacitances Cd 1  to Cd 6  formed in a semiconductor substrate. As a result, the parasitic capacitance Csub 1  that acts to the kick capacitors C 1  to C 6  can be reduced. Thus, the kick capacitors C 1  to C 6  used in a switched capacitor method can be structured by a MOS capacitor while the parasitic capacitance Csub 1  is lowered, thereby a boosted voltage can be increased while increasing of an element area is depressed. 
     FIGS. 4A and 4B  are cross-sectional views and equivalent circuit diagrams illustrating the structure of the kick capacitor of the booster circuit in  FIG. 1  compared to an example of an bulk transistor of related art.  FIG. 4A  shows a case where a MOS capacitor is fabricated on a bulk substrate.  FIG. 4B  shows a case where a MOS capacitor is fabricated on an SOI substrate. 
   In  FIG. 4A , a well  12  is formed in a semiconductor substrate  11 . A depletion layer  13  having a depth of d 1  is formed along the bonded surface of the semiconductor substrate  11  and the well  12 . On the semiconductor substrate  11 , a gate electrode  15  is formed with a gate insulation film  14  therebetween. To the sidewall of the gate electrode  15 , a sidewall  16  is formed. A source layer  17   a  is formed in the well  12  adjacent to one side of the gate electrode  15 , while a drain layer  17   b  is formed in the well  12  adjacent to the other side of the gate electrode  15 . Around the well  12 , highly doped impurity diffusion regions  18   a  and  18   b  are formed to contact a back gate. The gate electrode  15  is connected to the source layer  17   a , the drain layer  17   b , and the highly doped impurity diffusion regions  18   a  and  18   b  through a direct current power supply source Va 1 . 
   In a case where a MOS capacitor is formed on a bulk substrate, a parasitic capacitance Csub 11  including a depletion layer capacitance Cd 11  is added in parallel with a MOS capacitance Cg 11  of the MOS capacitor. The depletion layer capacitance Cd 11  varies by an impurity concentration Nsub of the semiconductor substrate  11 , an impurity concentration N D  of the well  12 , and a voltage E 1  of the direct current power supply source Va 1 . 
   The depletion layer capacitance Cd 11  is expressed by the following formula (1). 
                   Cd   ⁢           ⁢   11     =         q   ⁢           ⁢     ɛ   si     ⁢   Nsub       2   ⁢     (     Vbi   +     E   ⁢           ⁢   1       )                   formula   ⁢           ⁢     (   1   )                 
where q is the elementary electric charge (=1.60218×10 −19  coulomb), ε si  is the dielectric constant of silicon (=1.053×10 −10  F/m) and Vbi is the built-in potential, which varies by N D .
 
   Here, Nsub is 1E21 cm 3  in a case where a typically used p-type silicon wafer is used. N D  is Nsub or more due to the characteristic of a CMOS process, in order to maintain PN diode characteristics. If N D =Nsub, Vbi=0.6 V. The larger is N D , the larger is Vbi. Accordingly, the maximum of Cd 11  is obtained to be Cd 11 =120 μFm by formula (1), when E 1 =0V. 
   In contrast, in  FIG. 4B , an insulation layer  22  is formed on a semiconductor substrate  21 . On the insulation layer  22 , a semiconductor layer  24  is formed. In the semiconductor substrate  21 , a depletion layer  23  having a depth of d 2  is formed along the bonded surface of the semiconductor substrate  21  and the insulation layer  22 . As the material for the semiconductor substrate  21  and the semiconductor layer  24 , for example, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, and the like can be used. As the insulation layer  22 , for example, SiO 2 , SiON, and an insulation layer or buried insulation layer of SiON or Si 3 N 4  can be used. As the semiconductor substrate  21  in which the semiconductor layer  24  is formed on the insulation layer  22 , for example, an SOI substrate can be used. A separation by implanted oxygen (SIMOX) substrate, a bonded substrate, a laser annealed substrate, and the like can be used as the SOI substrate. Instead of using the semiconductor substrate  21 , an insulation substrate such as sapphire, glass, and ceramic may be used. 
   On the semiconductor layer  24 , a gate electrode  26  is formed with a gate insulation film  25  therebetween. To the sidewall of the gate electrode  26 , a sidewall  27  is formed. A source layer  28   a  is formed in the semiconductor layer  24  adjacent to one side of the gate electrode  26 , while a drain layer  28   b  is formed in the semiconductor layer  24  adjacent to the other side of the gate electrode  26 . The gate electrode  26  is connected to the source layer  28   a , and the drain layer  28   b  through a direct current power supply source Va 2 . 
   In a case where a MOS capacitor is formed on a SOI substrate, a parasitic capacitance Csub 21  including a depletion layer capacitance Cd 21  capacitively coupled in series with a BOX layer capacitance CB 21  is added in parallel with a MOS capacitance Cg 21  of the MOS capacitor. 
   As a result, the parasitic capacitance Csub 21  in  FIG. 4B  is smaller than the parasitic capacitance Csub 11  in  FIG. 4A . Namely, a parasitic capacitance added to a MOS capacitor can be reduced by forming the MOS capacitor on an SOI substrate compared to a case where the MOS capacitor is formed on a bulk substrate. For example, the parasitic capacitance Csub 21  can be reduced by approximately 70% as Csub 21  is calculated to be 0.012 pF with the following conditions: the film thickness of the insulation layer  22  is 2000 nm; and the depletion layer capacitance Cd 21  in  FIG. 4B  is equal to the depletion layer capacitance Cd 11  in  FIG. 4A . 
   CB 21  and Csub 21  are respectively expressed by the following formulas (2) and (3). 
                   CB   ⁢           ⁢   21     =       ɛ   sio       d   BOX               formula   ⁢           ⁢     (   2   )                   Csub   ⁢           ⁢   21     =         CB   21     ×     Cd   21           CB   21     +     Cd   21                 formula   ⁢           ⁢     (   3   )                 
where ε si  is the dielectric constant of silicon dioxide, and d BOX  is the thickness of the buried oxide film. The maximum of the depletion layer capacitance is 120 μFm. In order to make Csub 21  30 μFm or less, preferably, 10 μFm, the thickness of the buried oxide film is preferably 19 nm or more, more preferably, 57 nm or more. This makes it possible to further reduce the parasitic capacitance.
 
     FIG. 5  shows a circuit structure of one stage of the booster circuit in  FIG. 1 . 
   In  FIG. 5 , for example, the switches and kick capacitor in  FIG. 1  can be structured as follows: the switch SW 8  is structured by an P channel electric field effect transistor T 1 , the switch SW 13  is structured by a N channel electric field effect transistor T 2 , the switch SW 3  is structured by an P channel electric field effect transistor T 3 , and the kick capacitor C 3  is structured by an P channel electric field effect transistor T 4 . Here, the P channel electric field effect transistor T 4  can be structured by a MOS capacitor having an SOI structure. 
   In the structure, the sources of the P channel electric field effect transistor T 1  and the N channel electric field effect transistor T 2  are connected to the gate of the P channel electric field effect transistor T 4 . The drain of the P channel electric field effect transistor T 1  is connected to the source of the P channel electric field effect transistor T 3 . The drain of the P channel electric field effect transistor T 3  is connected to the source and drain of the P channel electric field effect transistor T 4 . 
   In addition, a first control signal XSC 1 , which turns on or off the P channel electric field effect transistor T 1  and the N cannel electric field effect transistor T 2 , is input to the gates of the P channel electric field effect transistor T 1  and the N channel electric field effect transistor T 2 . A second control signal XSC 2 , which turns on or off the P channel electric field effect transistor T 3 , is input to the gate of the P channel electric field effect transistor T 3 . The first control signal XSC 1  and the second control signal XSC 2  can use pulse signals each having a phase opposite to each other. 
   In the charging operation, the first control signal XSC 1  is set to be a low level, while the second control signal XSC 2  is set to be a high level. After the setting, the P channel electric field effect transistor T 1  is turned off, and the N channel electric field effect transistor T 2  and the P channel electric field effect transistor T 3  are turned on. As a result, the voltage of the direct current power supply source VDD is applied to the P channel electric field effect transistor T 4 , thereby electric charges are stored in the P channel electric field effect transistor T 4 . 
   In the pump-up operation, the first control signal XSC 1  is set to be the high level, while the second control signal XSC 2  is set to be the low level. After the setting, the P channel electric field effect transistor T 1  is turned on, and the N channel electric field effect transistor T 2  and the P channel electric field effect transistor T 3  are turned off. As a result, the output voltage from the Kick capacitor C 2  serving as the previous stage is applied to the gate of the P channel electric field effect transistor T 4 , thereby the output voltage from the source and drain of the P channel electric field effect transistor T 4  is applied to the kick capacitor C 4  serving as the subsequent stage. 
     FIG. 6  is a plan view illustrating a layout pattern of one stage of the booster circuit in  FIG. 1 . 
   In  FIG. 6 , a bulk region R 1  and an SOI forming region R 2  are provided in a semiconductor chip  31 . In the bulk region R 1 , N wells N 1  and N 2 , and a P well P 1  are formed. In the SOI forming region R 2 , an N well N 3  is formed. The P channel electric field effect transistors T 1 , T 3 , and T 4  in  FIG. 5  are respectively formed to the N wells N 1 , N 2 , and N 3 , while the N channel electric field effect transistor T 2  in  FIG. 5  is formed to the P well P 1 . 
   On the P well P 1 , a gate electrode G 3  is formed. In the P well P 1 , N type impurity diffusion layers DN 3   a  and DN 3   b  are formed so as to sandwich the gate electrode G 3 . Around the P well P 1 , a P type impurity diffusion region DP 3  is formed to contact a back gate. 
   On the N well N 1 , a gate electrode G 1  is formed. In the N well N 1 , P type impurity diffusion layers DP 1   a  and DP 1   b  are formed so as to sandwich the gate electrode G 1 . Around the N well N 1 , an N type impurity diffusion region DN 1  is formed to contact a back gate. 
   On the N well N 2 , a gate electrode G 2  is formed. In the N well N 2 , P type impurity diffusion layers DP 2   a  and DP 2   b  are formed so as to sandwich the gate electrode G 2 . Around the N well N 2 , an N type impurity diffusion region DN 2  is formed to contact a back gate. 
   On the N well N 3 , a gate electrode G 4  is formed. In the N well N 3 , a P type impurity diffusion layers DP 4  is formed so as to sandwich the gate electrode G 4 . 
   The N type impurity diffusion region DN 1 , and the P type impurity diffusion layers DP 1   a  and DP 2   b  are connected through a lower wiring layer H 11 . The gate electrode G 4 , the P type impurity diffusion layer DP 1   a , and the N type impurity diffusion layer DN 3   a  are connected through a lower wiring layer H 12 . The gate electrodes G 1  and G 3  are connected through a lower wiring layer H 13 . The N type impurity diffusion layer DN 3   b , and the P type impurity diffusion region DP 3  are connected through a lower wiring layer H 14 . The P type impurity diffusion layers DP 2   a , DP 4 , and the N type impurity diffusion region DN 2  are connected through a lower wiring layer H 15 . The lower wiring layer H 13  is connected to an upper wiring layer H 21 , to which the control signal XSC 1  is input. The lower wiring layer H 16  is connected to an upper wiring layer H 22 , to which the control signal XSC 2  is input. 
   Accordingly, a parasitic capacitance that acts to a MOS capacitor can be reduced, even in a case where the MOS capacitor is structured by the P channel electric field effect transistor T 4 , since the P channel electric field effect transistor T 4  is formed in the SOI forming region R 2 . Thus, a kick capacitors used in a switched capacitor method can be structured by a MOS capacitor while the parasitic capacitance is lowered, thereby a boosted voltage can be increased while increasing of an element area is depressed. 
   Further, breakdown voltage of a switching element used in a switched capacitor method can be prevented from being deteriorated even though a case where a MOS capacitor includes an SOI structure, since the P channel electric field effect transistors T 1 , T 3 , and the N channel electric field effect transistor T 2  are formed in the bulk region R 1 . As a result, a boosted voltage can be increased.