Abstract:
An I/O circuit is disclosed for tolerating a high voltage input without incurring a leakage current. An ESD current bypass module is coupled between a power supply node and a circuit pad. A high voltage tolerant charge module is used for disabling the ESD current bypass module when the circuit pad receives a high voltage input that is higher than a voltage at the power supply node. In addition, a high voltage tolerant discharge module may be included for alleviating the ESD current bypass module from a voltage overstress when the circuit pad receives a low voltage input that is lower than the voltage at the power supply node.

Description:
BACKGROUND  
       [0001]     The present invention generally relates to an input/output (I/O) circuit, and more particularly to an ElectroStatic Discharge (ESD) current bypass module in an I/O circuit that tolerates a high voltage input.  
         [0002]      FIG. 1  illustrates a conventional ESD current bypass circuit  10 . A pad  11  is electrically connected to an internal circuit  12  via a node  16 . A first diode  14  is connected between the node  16  and an I/O power supply  13  having a reference voltage Vdd. A second diode  15  is connected between ground and the node  16 . The first diode  14  and second diode  15  clamp the voltage level between the pad  11  and the internal circuit  12  to a certain range. In a normal operation mode, an input signal that falls in this voltage range travels directly from the pad  11  to the internal circuit  12 . In an ESD event, an ESD current input from the pad  11  would have a voltage level exceeding the clamped voltage range, and dissipate via the first diode  14  to the I/O power supply  13  or via the second diode  15  to ground. Thus, the internal circuit  12  is protected from such high voltage input due to the ESD event.  
         [0003]     One problem of the conventional ESD current bypass circuit  10  is that it cannot operate normally when an operational signal input from the pad  11  has a voltage level Vpad higher than Vdd. If Vpad is higher than Vdd, the first diode  14  will be forward biased and a leakage current will occur between the node  16  and the I/O power supply  13 . This would cause Vpad dropping to a lower voltage level, and therefore distort the input signal. As it happens often that high voltage devices and low voltage devices are used in the same integrated circuit, the low voltage devices may be exposed to high voltage signals. The low voltage device may not accommodate the high voltage signals. As such, the problems of leakage current and signal distortion become increasingly troublesome.  
         [0004]      FIG. 2  illustrates another conventional ESD current bypass circuit  20 . A pad  21  is connected to an internal circuit  24  via a node  30 . A PMOS transistor  22  is connected between the node  30  and an I/O power supply  29  having a voltage Vdd. A PMOS transistor  25  is connected between the I/O power supply  29  and the gate of the PMOS transistor  22 . A PMOS transistor  26  that is used as a capacitor is connected between the I/O power supply  29  and ground via a resistor RP. An NMOS transistor  23  is connected between the node  30  and ground. An NMOS transistor  27  is connected between ground and the gate of the transistor  23 . An NMOs transistor  28  that is used as a capacitor is connected between ground and Vdd via a resistor RN.  
         [0005]     The conventional ESD current bypass circuit  20  also has the problems of leakage current and signal distortion, when an operational signal input from the pad  21  has a voltage level Vpad higher than Vdd. For example, assuming Vpad is 5.0 V and Vdd is 3.3 V, the voltage level on wire pp 1  is 0.0 V as it is connected to ground. Thus, the PMOS transistor  25  conducts, and wire pp 2  has a voltage level of 3.3V, the same as Vdd. For the PMOS transistor  22 , the voltage difference between its gate and source is −1.7 V (3.3 V−5.0 V) and the voltage difference between the gate and drain is 0.0 V. The PMOS transistor  22  cannot be completely turned off and there would be leakage current between the node  30  and I/O power supply  29 . This would distort the 5.0 V signal input from the pad  21 .  
         [0006]     In addition, the ESD current bypass circuit  20  has the problem of voltage overstress on the gate oxide of the NMOS transistor  23 . Since the voltage level of the gate of transistor  23  constantly remains at 0 V, no matter whether the signal input from the pad  21  is a high voltage or low voltage signal. Due to the voltage overstress, the gate oxide may fail over a period of time. This causes potential reliability issues.  
         [0007]     What is needed is an ESD bypass I/O circuit that tolerates high voltage signals and is less susceptible to voltage overstress issues.  
       SUMMARY  
       [0008]     An I/O circuit is disclosed for tolerating a high voltage input without incurring a leakage current. An ESD current bypass module is coupled between a power supply node and a circuit pad. A high voltage tolerant charge module is used to prevent the ESD current bypass module from voltage overstress when the circuit pad receives a high voltage input that is higher than a voltage at the power supply node. In addition, a high voltage tolerant discharge module may be included to prevent the ESD current bypass module from leakage when the circuit pad receives a low voltage input that is lower than the voltage at the power supply node.  
         [0009]     The disclosed I/O circuit includes the ESD current bypass module to avoid leakage current between the circuit pad and the power supply node. Accordingly, the disclosed I/O circuit provides a robust pin-to-power ESD protection. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]      FIG. 1  schematically illustrates an conventional ESD bypass circuit.  
         [0011]      FIG. 2  schematically illustrates another conventional ESD bypass circuit.  
         [0012]      FIG. 3  schematically illustrates a high voltage tolerant I/O circuit, according to an embodiment of the present invention.  
     
    
     DESCRIPTION  
       [0013]     The invention discloses an I/O circuit that is able to bypass ESD current, while preventing a leakage current and getting rid of voltage overstress issues. The I/O circuit employs an ESD current bypass module for pin-to-power ESD protection. A charge module is used to charge the ESD current bypass module to ensure that no voltage overstress would occur, when a high voltage I/O signal is input from a pad into the I/O circuit. When a low voltage I/O signal is input from the pad into the I/O circuit, a discharge module is used to disable the ESD current bypass module to prevent the ESD current bypass module from conduction. The invention is described in detail in the following embodiments.  
         [0014]      FIG. 3  illustrates an I/O circuit  31  according to an embodiment of the present invention. A pad  32  is connected to an internal circuit node  34 . NMOS transistors  40  and  38  are connected in series between a node  66  and ground, wherein the gate of NMOS transistor  40  is connected to Vdd. An NMOS transistor  42  is connected between the gate of the transistor  38  and ground. The gate of NMOS transistor  42  is connected to Vdd via a resistor RN. An NMOS transistor  44  that is used as a capacitor is connected to ground with its gate connected to Vdd via the resistor RN.  
         [0015]     An ESD current bypass module  46  is connected between the node  66  and an I/O power supply  64  having a reference voltage Vdd. In this embodiment, the ESD current bypass module  46  is an NMOS transistor having its gate connected to a high voltage tolerant discharge module  68  and a high voltage tolerant charge module  62 . (It is a normal NMOS) The gate of the ESD current bypass module  46  is floating when the pad  32  is experiencing an ESD event. As such, the gate of the ESD current bypass module  46  would achieve an early breakdown to dissipate an ESD current from the node  66  to the I/O power supply  64 .  
         [0016]     The discharge module  68  includes NMOS transistors  48 ,  54  and  50 , and PMOS transistors  56  and  58 . The NMOS transistor  48  is connected between the gate of the ESD current bypass module  46  and the NMOS transistor  54 . The gate of the NMOS transistor  48  is connected to the drain of the NMOS transistor  50  and the PMOS transistor  56 . The NMOS transistor  54  is connected between the NMOS transistor  48  and a node  70 , with its gate connected to Vdd. The PMOS transistors  58 ,  56  and NMOS transistor  50  are serially connected between Vdd and ground. The gate of the PMOS transistor  58  is connected to a node  72 . The gate of the PMOS transistor  56  is connected to the source of the NMOS transistor  54 . The gate of the NMOS transistor  50  is connected to the gate of the ESD current bypass module  46  via nodes  74  and  76 .  
         [0017]     The high voltage tolerant charge module  62  includes an NMOS transistor  52  and PMOS transistor  60 . The NMOS transistor  52  is connected between the gate of the ESD current bypass module  46  and the PMOS transistor  60  that is further connected to a node  78 . The gates of the NMOS transistor  52  and the PMOS transistor  60  are connected to Vdd.  
         [0018]     The I/O circuit  31  ensures that no high voltage would stress the gate of ESD current bypass module  46  when an operational voltage Vpad input from the pad  32  is higher than Vdd. In such case, the charge module  62  charges the gate of the ESD current bypass module  46  to a sufficient voltage level. In this embodiment, when Vpad is greater than Vdd, the PMOS transistor  60  is turned on because the voltage difference between its gate and source is lower than 0.0 V. The voltage level on wire pp 1  is Vpad. The NMOS transistor  52  is always turned on because its gate is connected to Vdd. The voltage level on wire pp 2  is Vdd−Vt, where Vt is the threshold voltage of the NMOS transistor  52 . Therefore, the voltage difference between the gate and source of the ESD bypass device  46  is −Vt, and the voltage difference between the gate and the drain of the ESD bypass device  46  is Vpad−(Vdd−Vt). As such, the ESD bypass device  46  is completely turned off to prevent a leakage current between the node  66  and the I/O power supply Vdd, and there is no voltage overstress on the gate of the ESD bypass device  46  as long as Vpad&lt;2*Vdd−Vt.  
         [0019]     How the charge module  62  disables the ESD current bypass module  46  to prevent a leakage current and get rid of voltage overstress is better understood by the following example. Assuming Vdd is 3.3 V and Vpad is 5.0 V, the electrical potentials on wires PP 1 , PP 2 , PP 3 , PP 4 , PP 5 , NN 1 , NN 2  and NN 3  are listed in table 1 as the following:  
                                                                                                   TABLE 1                                       Wire                PP1   PP2   PP3   PP4   PP5   NN1   NN2   NN3                        Vol-   5   3.3-Vt   0.0   3.3-Vt   floating   3.3   0.0   3.3-Vt       tage                  
 
         [0020]     The discharge module  68  pulls down a gate voltage of the ESD current bypass module  46 , when the voltage level of Vpad is lower than Vdd. Because the gate voltage of ESD current bypass device is 0 V, normally there would not be any leakage current from the I/O power supply Vdd to the node  66 .  
         [0021]     For example, assuming Vpad is 0.0 V and Vdd remains 3.3 V, the NMOS transistor  54  is turned on and the voltage level on wire pp 4  becomes 0.0 V. Because the gate voltage of the PMOS transistor  58  equals to Vpad, which is 0.0 V, it would be turned on and the voltage level on wire pp 5  would be Vdd, which is 3.3 V. As the voltage on wire pp 4  is 0.0 V, the PMOS transistor  56  is turned on, and the voltage level on wire pp 3  equals to that on wire pp 5 , which is 3.3 V. This turns on the NMOS transistors  48 . Because the NMOS transistor  54  is always on, the voltage on wire pp 2  becomes Vpad, which is 0.0 V. The voltage levels on wires PP 1 , PP 2 , PP 3 , PP 4 , PP 5 , NN 1 , NN 2  and NN 3  can be found in table 2 as the following:  
                                                                                                   TABLE 2                                       Wire                PP1   PP2   PP3   PP4   PP5   NN1   NN2   NN3                        Voltage   0.0   0.0   3.3   0.0   3.3   3.3   0.0   0.0                  
 
         [0022]     The invention has an advantage of achieving a high voltage tolerant I/O circuit with a single NMOS transistor. When combined with cascade dynamic-floating-gate arrangements, the disclosed I/O circuit can be used as an I/O buffer in an open-drain configuration. The disclosed I/O circuit can also be used simply as a high voltage power supply. In such case, the discharge module  68  would not be necessary and may be optionally removed.  
         [0023]     The above invention provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components, and processes are described to help clarify the invention. These are, of course, merely examples and are not intended to limit the invention from that described in the claims.  
         [0024]     Although illustrative embodiments of the invention have been shown and described, other modifications, changes, and substitutions are intended in the foregoing invention. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.