Abstract:
An internal supply-voltage generator of a semiconductor memory device, which can be used both in a high-voltage test mode and in a normal operation mode, maintains a constant response speed in the normal operation mode and includes; a comparator comparing a reference voltage with an internal supply voltage and outputting the result of the comparison through an output terminal; and a driver receiving an external supply voltage and outputting the internal supply voltage in response to the result of the comparisons wherein the internal supply voltage is directly fed back to the comparator, and the output terminal of the comparator is electrically disconnected from an operating voltage source of the comparator when the semiconductor memory device is in a high-voltage test mode.

Description:
CROSS-REFERENCE TO RELATED PATENT APPLICATION 
       [0001]    This application claims the benefit of Korean Patent Application No. 10-2007-0003077, filed on Jan. 10, 2007, in the Korean lntellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Technical Field 
         [0003]    The present disclosure relates to a semiconductor memory device and, more particularly, to an internal supply voltage generator of a semiconductor memory device. 
         [0004]    2. Discussion of Related Art 
         [0005]    In a semiconductor memory device, specifically, in a Dynamic Random Access Memory (DRAM), as the degree of integration increases, the thicknesses of the gate oxide films become thinner and thinner. Accordingly, the resisting pressure of the gate oxide film of a transistor is lowered, which deteriorates the reliability of the semiconductor memory device. For this reason, in order to ensure the reliability of such a semiconductor memory device and to reduce power consumption, a low external supply voltage is used. From a semiconductor memory users&#39; viewpoint, however, that is, from the system makers&#39; viewpoint, lowering an external supply voltage is not preferable because it increases manufacturing costs, and the like. 
         [0006]    Accordingly, in an attempt to solve this problem, an internal supply voltage generating method has been developed. In the internal supply voltage generating method, when an external supply voltage from the outside is supplied to a chip, an internal supply-voltage generator clamps the external supply voltage and generates an internal supply voltage lower than the external supply voltage and supplies the internal supply voltage inside the chip. A conventional internal supply-voltage generating circuit is disclosed in U.S. Pat. No. 5,808,953. 
         [0007]      FIG. 1  is a circuit diagram of a conventional internal supply-voltage generator. 
         [0008]    Referring to  FIG. 1  the conventional internal supply-voltage generator includes a comparator  11  for comparing a reference voltage VREF with an internal supply voltage IVC and outputting the result CO of the comparison through an output terminal, and a driver  13  for receiving an external supply voltage EVC and outputting the internal supply voltage IVC in response to the result CO of the comparison. 
         [0009]    Generally, semiconductor makers perform a high-voltage test for operating a semiconductor memory device at a supply voltage higher than a voltage at which the semiconductor memory device operates in a normal state, in order to test the reliability of the semiconductor memory device. For example in a high-voltage test mode, in order to raise an internal supply voltage IVC to an external supply voltage EVC, a method of raising a reference voltage VREF to the external supply voltage EVC without varying the operation of the comparator  11  can be used. 
         [0010]    In this case, however, due to the voltage drop of the driver  13 , it is difficult to make the internal supply voltage IVC be substantially equal to the external supply voltage EVC. Also, due to an increase in operation current of the comparator  11 , when the operating current exceeds a current rating of the tester, the high-voltage test cannot be performed. 
         [0011]    Accordingly, an internal supply-voltage generator that can be used both when a semiconductor memory device operates in a normal operation mode and when the semiconductor memory device operates in a high-voltage test mode, is employed.  FIG. 2  is a circuit diagram of a conventional internal supply-voltage generator that can be used both in a normal operation mode and in a high-voltage test mode. 
         [0012]    Referring to  FIG. 2 , the conventional internal supply-voltage generator includes a comparator  21 , a driver MP 20 , and control transistors MP 21  and MN 23  and logic gates NR 21 , I 21 , and OR 21  for controlling a high-voltage test. The comparator  21  includes PMOS transistors MP 22  through MP 25 , and NMOS transistors MN 20  through MN 22 . The transistors are connected between an external supply voltage EVC and a ground voltage VSS. 
         [0013]    When a semiconductor memory device operates in the high-voltage test mode, a high-voltage test control signal HVCC_TEST is logic “high”, and an internal supply-voltage generator enable signal ENABLE is logic “low”. Accordingly. the control transistor MP 21 , which is a PMOS transistor, is turned off, and the control transistor MN 23 , which is a NMOS transistor, is turned on. Accordingly, in the high-voltage test mode, the internal supply voltage IVC is not fed back to the comparator  21 , and the NMOS transistor MN 21  of the comparator  21  is turned off. 
         [0014]    When the semiconductor memory device operates in the normal operation mode, the high-voltage test signal HVCC_TEST is logic “low”, and the internal supply-voltage generator enable signal ENABLE is logic “high”. Accordingly, the PMOS control transistor MP 21  is turned on, and the NMOS control transistor MN 23  is turned off. Accordingly, the internal supply voltage IVC is fed back to the comparator  21  through the PMOS control transistor MP 21 , and the comparator  21  operates normally. 
         [0015]    The internal supply-voltage generator illustrated in  FIG. 2  has a disadvantage that a response speed is slow, because the internal supply voltage IVC is fed back to the comparator  21  through the PMOS control transistor MP 21  in the normal operation mode. 
       SUMMARY OF THE INVENTION 
       [0016]    Exemplary embodiments of the present invention provide an internal supply-voltage generator that can be used both in a high-voltage test mode and in a normal operation mode, and maintain a constant response speed in the normal operation mode. 
         [0017]    According to an exemplary embodiment of the present invention, there is provided an internal supply-voltage generator of a semiconductor memory device including: a comparator comparing a reference voltage with an internal supply voltage and outputting the result of the comparison through an output terminal; and a driver receiving an external supply voltage and outputting the internal supply voltage in response to the result of the comparison, wherein the internal supply voltage is directly fed back to the comparator, and the output terminal of the comparator is electrically disconnected from an operating voltage source of the comparator when the semiconductor memory device is in a high-voltage test mode. 
         [0018]    The comparator includes: a first input transistor having one end connected to the output terminal, and a gate to which the reference voltage is applied; a second input transistor having one end connected to a complementary output terminal of the output terminal, and a gate to which the internal supply voltage is applied; and a control transistor connected between the other end of the first input transistor and the other end of the second input transistor, wherein, when the semiconductor memory device is in a normal operation mode, the control transistor is turned on so that the comparator operates normally, and, when the semiconductor memory device is in the high-voltage test mode, the control transistor is turned off so that the output terminal is electrically disconnected from the operating voltage source of the comparator. 
         [0019]    The comparator includes: a first input transistor having one end connected to the output terminal, and the other end connected to a common node; and a second input transistor having one end connected to the complementary output terminal of the output terminal, a gate to which the internal supply voltage is applied, and the other end connected to the common node, wherein, when the semiconductor memory device is in the normal operation mode, the reference voltage is applied to the gate of the first input transistor so that the comparator operates normally, and, when the semiconductor memory device is in the high voltage test mode, the first input transistor is turned off so that the output terminal is electrically disconnected from the operating voltage source of the comparator. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]    Exemplary embodiments of the present invention will be understood in more detail from the following descriptions taken in conjunction with the attached drawings, in which: 
           [0021]      FIG. 1  is a circuit diagram of a conventional internal supply-voltage generator; 
           [0022]      FIG. 2  is a circuit diagram of a conventional internal supply-voltage generator that can be used both in a normal operation mode and in a high-voltage test mode; 
           [0023]      FIG. 3  is a circuit diagram of an internal supply-voltage generator according to an exemplary embodiment of the present invention; 
           [0024]      FIG. 4  is a circuit diagram of an internal supply-voltage generator according to an exemplary embodiment of the present invention; and 
           [0025]      FIG. 5  is a circuit diagram of an internal supply-voltage generator according to an exemplary embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
       [0026]    The attached drawings illustrating exemplary embodiments of the present invention are referred to in order to gain a sufficient understanding of the present invention, the merits thereof, and the objectives accomplished by the implementation of the present invention. 
         [0027]    Hereinafter, the present invention will be described in detail by explaining exemplary embodiments of the invention with reference to the attached drawings. Like reference numerals in the drawings denote like elements. 
         [0028]      FIG. 3  is a circuit diagram of an internal supply-voltage generator according to an exemplary embodiment of the present invention. 
         [0029]    Referring to  FIG. 3 , the internal supply-voltage generator includes a comparator  31 , a driver MP 30 , and a NOR gate NR 31 , an inverter I 31 , an OR gate OR 31 , and an AND gate AD 31  for controlling a high-voltage test. 
         [0030]    More specifically, an internal supply voltage IVC is directly fed back to the comparator  31  and is not fed back via any transistor. The comparator  31  compares the internal supply voltage IVC that is directly fed back, with a reference voltage VREF, and outputs the result of the comparison through an output terminal CO. The driver MP 30  receives an external supply voltage EVC, and outputs an internal supply voltage IVC in response to the result of the comparison received from the output terminal CO of the comparator  31 . 
         [0031]    More specifically, the comparator  31  includes a first PMOS load transistor MP 32 , a second PMOS load transistor MP 33 , a first NMOS input transistor MN 30 , a second NMOS input transistor MN 31 , a first PMOS control transistor MP 34 , a second NMOS control transistor MN 34 , a first NMOS pull-down transistor MN 32 , a second NMOS pull-down transistor MN 33 , and a pull-up transistor MP 31 . 
         [0032]    The first PMOS load transistor MP 32  has a source to which the external supply voltage EVC is applied, a drain connected to the output terminal CO, and a gate connected to a complementary output terminal COB. The second PMOS transistor MP 33  has a source to which the external supply voltage EVC is applied, and a drain and a gate connected to the complementary output terminal COB. 
         [0033]    The first NMOS input transistor MN 30  has a drain connected to the output terminal CO, and a gate to which the reference voltage VREF is applied. The second NMOS input transistor MN 31  has a drain connected to the complementary output terminal COB, and a gate to which the internal supply voltage IVC is directly fed back. 
         [0034]    The first PMOS control transistor MP 34  is connected between the output terminal CO and the complementary output terminal COB, and has a gate to which the output of the OR gate OR 31  is applied. The OR gate OR 31  receives a high-voltage test control signal HVCC_TEST and an internal supply-voltage generator enable signal ENABLE. The high-voltage test control signal HVCC_TEST goes logic “high” when the corresponding semiconductor memory device is in a high-voltage test mode, and the enable signal ENABLE goes logic “high” when the internal supply-voltage generator is enabled. 
         [0035]    The second NMOS control transistor MN 34  is connected between the source of the first NMOS input transistor MN 30  and the source of the second NMOS input transistor MN 31 , and has a gate to which an inverted signal HVCC_TESTB of the high-voltage test control signal HVCC_TEST is applied. 
         [0036]    The first NMOS pull-down transistor MN 32  has a drain connected to the source of the first NMOS input transistor MN 30 , a gate to which the output of the OR gate OR 31  is applied, and a source to which a ground voltage VSS is applied. The second NMOS pull-down transistor MN 33  has a drain connected to the source of the second NMOS input transistor MN 31 , a gate to which the output of the NAND gate AD 31  is applied, and a source to which the ground voltage VSS is applied. The NAND gate AD 31  receives the inverted signal HVCC_TESTB of the high-voltage test control signal HVCC_TEST, and the internal supply-voltage generator enable signal ENABLE. 
         [0037]    The pull-up transistor MP 31  has a source to which the external supply voltage EVC is applied, a gate to which the output of the NOR gate NR 31  is applied, and a drain connected to the complementary output terminal COB. The NOR gate NR 31  receives the high-voltage test control signal HVCC_TEST and the output signal of the inverter I 31 . The inverter I 31  inverts the enable signal ENABLE. 
         [0038]    Hereinafter, the operation of the internal supply-voltage generator according to the exemplary embodiment, as illustrated in  FIG. 3 , witl be described in detail. When the semiconductor memory device is in a normal operation mode, the high-voltage test control signal HVCC_TEST goes logic “low” and the inverted signal HVCC_TESTB of the high-voltage test control signal HVCC_TEST goes logic “high”, so that the internal supply-voltage generator enable signal ENABLE goes logic “high”. 
         [0039]    Accordingly, the pull-up transistor MP 31  is turned off, the first PMOS control transistor MP 34  is turned off, the second NMOS control transistor MN 34  is turned on, and the first and second NMOS pull-down transistors MN 32  and MN 33  are turned on. 
         [0040]    Accordingly, when the semiconductor memory device is in the normal operation mode, the comparator  31  operates normally by the first PMOS load transistor MP 32 , the second PMOS load transistor MP 33 , the first NMOS input transistor MN 30 , and the second NMOS input transistor MN 31 . 
         [0041]    Meanwhile, when the semiconductor memory device is in the high-voltage test mode, the high-voltage test control signal HVCC_TEST goes logic “high”, and the inverted signal HVCC_TESTB of the high-voltage test control signal HVCC_TEST goes logic “low”, so that the internal supply-voltage generator enable signal ENABLE goes logic “low”. 
         [0042]    Accordingly, the pull-up transistor MP 31  is turned on, the first PMOS control transistor MP 34  is turned off, the second NMOS control transistor MN 34  is turned off, the first NMOS pull-down transistor MN 32  is turned on, and the second NMOS pull-down transistor MN 33  is turned off. Accordingly, the voltage of the complementary output terminal COB is fixed at the external supply voltage EVC and, as a result, the first PMOS load transistor MP 32  and the second PMOS load transistor MP 33  are turned off. 
         [0043]    Accordingly, when the semiconductor memory device is in the high-voltage test mode, the output terminal CO is electrically disconnected from the operating supply voltage, that is, the external supply voltage EVC, of the comparator  31 , and the voltage of the output terminal CO substantially becomes the ground voltage VSS through the first NMOS input transistor MN 30  and the first NMOS pull-down transistor MN 32 . Therefore, the PMOS driver MP 30  is fully turned on, so that the internal supply voltage IVC substantially becomes the external supply voltage EVC. 
         [0044]    As described above, the internal supply-voltage generator according to this exemplary embodiment outputs an internal supply voltage IVC having the same level as the external supply voltage EVC, when the semiconductor memory device is in the high-voltage test mode. Also, when the semiconductor memory device is in the normal operation mode, because the internal supply voltage IVC is directy fed back to the comparator  31  not via any transistor, a constant response speed is maintained. 
         [0045]      FIG. 4  is a circuit diagram of an internal supply voltage generator according to an exemplary embodiment of the present invention. 
         [0046]    Referring to  FIG. 4 , the internal supply-voltage generator according to the exemplary embodiment includes a comparator  41 , a driver MP 40 , a NOR gate NR 41 , an inverter I 41 . an OR gate OR 41 , a NOR gate NR 42 , and an inverter I 42  for controlling a high-voltage test. 
         [0047]    More specifically, an internal supply voltage IVC is directly fed back to the comparator  41 , and not via any transistor. The construction of the internal supply-voltage generator according to this exemplary embodiment is similar to the construction of the internal supply voltage generator according to the exemplary embodiment shown in  FIG. 3 , except for the construction of the comparator  41 . 
         [0048]    The comparator  41  includes a first PMOS load transistor MP 42 , a second PMOS load transistor MP 43 , a first NMOS input transistor MN 40 , a second NMOS input transistor MN 41 , a first PMOS control transistor MP 44 , a second PMOS control transistor MP 45 , a third NMOS control transistor MN 43 , a fourth NMOS control transistor MN 44 , a NMOS pull-down transistor MN 42 , and a pull-up transistor MP 41 . 
         [0049]    The first PMOS load transistor MP 42  has a source to which an external supply voltage EVC is applied, a drain connected to an output terminal CO, and a gate connected to a complementary output terminal COB. The second PMOS load transistor MP 43  has a source to which the external supply voltage EVC is applied, and a drain and a gate connected to the complementary output terminal COB, 
         [0050]    The first NMOS input transistor MN 40  has a drain connected to the output terminal CO, a source connected to a common node CN, and a gate connected to the drain of the second PMOS control transistor MP 45  and the drain of the fourth NMOS control transistor MN 44 . A reference voltage VREF is applied to the source of the second PMOS control transistor MP 45  and a high-voltage test control signal HVCC_TEST is applied to the gate of the second PMOS control transistor MP 45 . A ground voltage VSS is applied to the source of the fourth NMOS control transistor MN 44 , and a high-voltage test control signal HVCC_TEST is applied to the gate of the fourth NMOS control transistor MN 44 . 
         [0051]    The first PMOS control transistor MP 44  is connected between the output terminal CO and the complementary output terminal COB, and the output of the OR gate OR 41  is applied to the gate of the first PMOS control transistor MP 44 . The OR gate OR 41  receives the high voltage test control signal HVCC_TEST and an internal supply voltage generator enable signal ENABLE. The third NMOS control transistor MN 43  has a drain connected to the output terminal CO, a gate to which the high voltage test control signal HVCC_TEST is applied, and a source to which the ground voltage VSS is applied. 
         [0052]    The second NMOS input transistor MN 41  has a drain connected to the complementary output terminal COB, a gate to which an internal supply voltage IVC is directly fed, and a source connected to the common node CN. The NMOS pull-down transistor MN 42  has a drain connected to the common node CN, a gate to which the output of the NOR gate NR 42  is applied, and a source to which the ground voltage VSS is applied. The NOR gate NR 42  receives the high-voltage test control signal HVCC_TEST and the output signal of the inverter I 42 . The inverter I 42  inverts the enable signal ENABLE. 
         [0053]    The pull-up transistor MP 41  has a source to which the external supply voltage EVC is applied, a gate to which the output of the NOR gate NR 41  is applied, and a drain connected to the complementary output terminal COB. The NOR gate NR 41  receives the high-voltage test control signal HVCC_TEST and the output signal of the inverter I 41 . The inverter I 41  inverts the enable signal ENABLE. 
         [0054]    Hereinafter, the operation of the internal supply-voltage generator according to this exemplary embodiment will be described in detail. First, when the semiconductor memory device is in the normal operation mode, the high-voltage test control signal HVCC_TEST goes logic “low”, and the internal supply-voltage generator enable signal ENABLE goes logic “high”. 
         [0055]    Accordingly, the pull-up transistor MP 41  is turned off, the first PMOS control transistor MP 44  is turned off, the third NMOS control transistor MN 43  is turned off, and the NMOS pull-down transistor MN 42  is turned on. Also, the second PMOS control transistor MP 45  is turned on and the fourth NMOS control transistor MN 44  is turned off, so that a reference voltage VREF is applied to the gate of the first NMOS input transistor MN 40 . 
         [0056]    Therefore, when the semiconductor memory device is in the normal operation mode, the comparator  41  operates normally by the first PMOS load transistor MP 42 , the second PMOS load transistor MP 43 , the first NMOS input transistor MN 4 O, and the second NMOS input transistor MN 41 . 
         [0057]    On the other hand, if the semiconductor memory device is in the high-voltage test mode, the high-voltage test control signal HVCC_TEST goes logic “high”, and the internal supply-voltage generator enable signal ENABLE goes logic “low”. 
         [0058]    Accordingly, the pull-up transistor MP 41  is turned on, the first PMOS control transistor MP 44  is turned off, the third NMOS control transistor MN 43  is turned on, and the NMOS pull-down transistor MN 42  is turned off. Also, the second PMOS control transistor MP 45  is turned off. and the fourth NMOS control transistor MN 44  is turned on, so that the ground voltage VSS is applied to the gate of the first NMOS input transistor MN 40  and the first NMOS input transistor MN 40  is turned off. Thus, the voltage of the complementary output terminal COB is fixed at the external supply voltage EVC, and as a result the first PMOS load transistor MP 42  and the second PMOS load transistor MP 43  are turned off. 
         [0059]    Therefore, when the semiconductor memory device is in the high-voltage test mode, the voltage of the output terminal CO is electrically disconnected from the operating supply voltage, that is, the external supply voltage EVC, of the comparator  41 , and becomes substantially the ground voltage VSS by action of the third NMOS control transistor MN 43 , which is turned on. Accordingly, the PMOS driver MP 40  is fully turned on, and the internal supply voltage IVC becomes substantially the same as the external supply voltage EVC. 
         [0060]    As described above, in the internal supply-voltage generator according to the exemplary embodiment shown in  FIG. 4 , like the internal supply-voltage generator according to the exemplary embodiment shown in  FIG. 3 , an internal supply voltage IVC having the same level as an external supply voltage EVC is output in the high-voltage test mode, and the internal supply voltage IVC is directly fed back to the comparator  41  and is not fed back via any transistor in the normal operation mode, so that a constant response speed is maintained. 
         [0061]      FIG. 5  is a circuit diagram of an internal supply-voltage generator according to an exemplary embodiment of the present invention. 
         [0062]    Referring to  FIG. 5 , the internal supply-voltage generator according to this exemplary embodiment has a construction similar to the internal supply-voltage generator according to the exemplary embodiment as illustrated in  FIG. 4 , except that the drain of an NMOS transistor MN 54  is connected to the gate of a first NMOS input transistor MN 40  and one end of a transmission gate T 51 . 
         [0063]    A high-voltage test control signal HVCC_TEST is applied to the gate of the NMOS control transistor MN 54 , and a ground voltage VSS is applied to the source of the NMOS control transistor MN 54 . A reference voltage VREF is applied to the other end of the transmission gate T 51 , and the transmission gate T 51  is turned on when the high-voltage test control signal HVCC_TEST goes logic “low”. 
         [0064]    The operation of the internal supply-voltage generator according to this exemplary embodiment is similar to the operation of the internal supply-voltage generator according to the exemplary embodiment as illustrated in  FIG. 4  and, accordingly, a detailed description thereof will be omitted. 
         [0065]    As described above, in an internal supply-voltage generator according to exemplary embodiments of the present invention, an internal supply voltage having the same level as an external supply voltage is output in a high-voltage test mode, and the internal supply voltage is directly fed back to a comparator and is not fed back via any transistor in a normal operation mode, so that a constant response speed is maintained. 
         [0066]    While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it witl be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention, as defined by the following claims.