Abstract:
An acoustic resonator comprising a substantially horizontal membrane of piezoelectric material with upper and lower metal electrodes on its upper and lower faces, said membrane being attached around its perimeter to the inner side walls of a rectangular interconnect frame by an attaching polymer, the side walls of the package frame being substantially perpendicular to the membrane and comprising conducting vias within a dielectric matrix, the conducting vias running substantially vertically within the side walls, the metal electrodes being conductively coupled to the metal vias by a feature layer over the upper surface of the membrane and top and bottom lids coupled to top and bottom ends of the interconnect frame to seal the acoustic resonator from its surroundings.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application is a Continuation in Part application of U.S. Ser. No. 14/590,621 to Hurwitz and Huang, filed on Jan. 6, 2015, and titled “Film Bulk Acoustic Resonator Filter.” The disclosure of U.S. Ser. No. 14/590,621 is hereby incorporated by reference herein in its entirety. 
     
    
     BACKGROUND 
       [0002]    1. Field of the Disclosure 
         [0003]    The present invention relates to RF filters for use in mobile phones and the like. 
         [0004]    2. Description of the Related Art 
         [0005]    Mobile phones are getting smarter. In the transition from so called 3rd generation smart phones to 4th and 5th generation smart phones there has been an explosive growth in radio frequencies and bands. To be able to operate correctly, it is necessary to filter out signals from nearby bands. 
         [0006]    RF and microwave applications benefit greatly from the use of tunable devices and circuits. With components that can be tuned over a broad range, filters can be made to tune over multiple frequency bands of operation, impedance matching networks can be adjusted for amplifier power level or antenna impedance. 
         [0007]    To meet the demand of ever more sophisticated smart phones and RF devices in automobiles and the like, it is necessary to use different frequency bands for different communication channels, and for different RF frequency devices such as smart phones to co-exist in the presence of frequencies that would otherwise interfere with normal operation. One way to do this is to use FBAR technology as filters. 
         [0008]    FBAR (Film Bulk Acoustic Resonator) filters are a form of bulk acoustic wave filter that have superior performance with steeper rejection curves compared to surface acoustic wave filters. They have low signal loss and consequently enable longer battery life and more talk time in mobile telecommunication technology. 
         [0009]    When most applications were third generation (3G), only four or five different bands benefited from using FBAR (Film Bulk Acoustic Resonator) filtering. Now, as worldwide carriers move to 4G (fourth generation), filter specifications are much more stringent. 
         [0010]    Barium strontium titanate (BST) is a mixed titanate that exists as a centrosymmetric piezoelectric material having a perovskite structure at room temperature. BST has a high dielectric constant, low dielectric loss and low leakage current density and has been used as the dielectric of capacitors. 
         [0011]    BST generally has a high dielectric constant so that large capacitances can be realized in a relatively small area. Furthermore, BST has a permittivity that depends on the applied electric field. Consequently, thin-film BST has the remarkable property that the dielectric constant can be changed appreciably by an applied DC-field, allowing for very simple voltage-variable capacitors whose capacitance can be tuned by changing a bias voltage across the capacitor. In addition, the bias voltage typically can be applied in either direction across a BST capacitor since the film permittivity is generally symmetric about zero bias. That is, BST typically does not exhibit a preferred direction for the electric field. These characteristics enable BST to be used a dielectric within alternating current circuits, such that at a characteristic voltage that depends on the dimensions, the dielectric material resonates and can thus serve as a filter by absorbing electrical energy and changing it into acoustic energy. 
         [0012]    U.S. Pat. No. 7,675,388 B2 to Humirang and Armstrong describes a switchable tunable acoustic resonator using BST material. The Acoustic resonator comprises a pair of electrodes with a barium strontium titanate (BST) dielectric layer disposed therebetween. The device is switched on as a resonator with a resonant frequency if a DC (direct current) bias voltage is applied across the BST dielectric layer. The acoustic resonator is also switched off if no DC bias voltage is applied across the BST dielectric layer. Furthermore, the resonant frequency of the acoustic resonator can be tuned based on a level of the DC bias voltage, with the resonant frequency increasing as the level of the DC bias voltage increases. 
         [0013]    In one design described therein, U.S. Pat. No. 7,675,388 B2 describes such acoustic resonators formed on sapphire substrates. In another design described therein, such acoustic resonators are formed over an air gap disposed between the second electrode and a substrate. Also described are acoustic resonators formed over an acoustic reflector disposed between the second electrode and a substrate, where the acoustic reflector is comprised of a plurality of alternating layers of platinum (Pt) and silicon dioxide (SiO 2 ) which reduces the damping of the resonance of the acoustic resonator caused by the substrate. 
         [0014]    The BST based acoustic resonator functions can be switched on or off by applying a DC bias voltage and its resonant frequency can be tuned by varying the DC bias voltage. Thus BST based acoustic resonators have many versatile uses in electronic circuits, such as switchable, tunable filters and duplexers for transmitting and receiving a radio frequency signal over an antenna. 
       BRIEF SUMMARY OF THE DISCLOSURE 
       [0015]    A first aspect of the present invention is directed to a method of fabricating a thin film bulk resonator filter comprising:
       (a) Obtaining dice comprising a sacrificial substrate with a piezoelectric material grown thereon between electrode layers;   (b) Obtaining a dielectric grid of frameworks defining an array of cavities such that each cavity is surrounded by a framework, the dielectric grid further comprising conductive vias running through the frameworks;   (c) Adhering a tacky detachable tape to the undersurface of the grid of frameworks;   (d) Positioning a die in each cavity holding the die in place by tackiness of the detachable tape;   (e) Removing the sacrificial substrate, laminating an attaching polymer over and around the membrane and removing the detachable tape;   (f) Drilling through the attaching polymer to at least a first and a second via around each membrane; and through the piezoelectric material to the electrode layer thereunder;   (g) Fabricating on a top surface, a first connection between an upper end of the first via and the electrode over the piezoelectric layer, and a second connection between an upper end of a second via and the electrode layer under the piezoelectric layer and an upper connecting ring enclosing the upper end of the first via, the upper end of the second via and the first and second connections;   (h) Fabricating on a lower surface, lower pads on lower ends of the first via and the second via and a lower connecting ring enclosing the lower ends of the first via and the second via;   (i) Fabricating legs for surface mounting extending from lower pads to below the lower connection ring;   (j) Removing the attaching polymer under the lower electrode;   (k) Attaching an upper lid to the upper ring and a lower lid to the lower ring, and   (l) Singulating the individual packaged thin film bulk resonator filters from the grid.       
 
         [0028]    Optionally, the sacrificial substrate is a single crystal of c-plane sapphire. 
         [0029]    Optionally, the piezoelectric material is a mixed Barium Strontium Titanate (B x S (1-x) TiO 3 ). 
         [0030]    Optionally, the piezoelectric material is fabricated by a process selected from the group consisting of molecular beam epitaxy, pulsed laser deposition, RF sputtering and atomic layer deposition. 
         [0031]    Preferably, the the piezoelectric material is epitaxially grown. 
         [0032]    Optionally, the piezoelectric material is single crystal. 
         [0033]    Optionally, the electrode layers, comprise platinum or tantalum. 
         [0034]    Optionally, an interface layer is deposited between the sacrificial substrate and the first electrode layer. 
         [0035]    Optionally, (e) comprises radiating the interface layer through the sacrificial substrate. 
         [0036]    Optionally, the interface layer comprises a AlN, TiN, GaN or InN. 
         [0037]    Optionally, step (a) comprises: obtaining a wafer of sacrificial substrate; fabricating an interface layer on a surface of the sacrificial substrate; fabricating a lower electrode on the interface layer; fabricating an epitaxial layer of piezoelectric material on the lower electrode; fabricating an upper electrode on the piezoelectric layer, and singulating the electrode into dice. 
         [0038]    Optionally, the dielectric grid of frameworks comprises a ceramic matrix cofired with metallic vias. 
         [0039]    Alternatively, the dielectric grid of frameworks comprises a polymer matrix and copper vias. 
         [0040]    Optionally, the polymer matrix further comprises glass fibers and ceramic fillers. 
         [0041]    Optionally, the copper vias are fabricated by electroplating as upstanding pillars in a patterned photoresist, stripping away the photoresist and laminating the polymer matrix thereover. 
         [0042]    Optionally, the the polymer matrix is a liquid crystal polymer. 
         [0043]    Optionally, step (d) of positioning a die in each cavity, comprises positioning the die with the sacrificial substrate in contact with the removable tape and the piezoelectric layer and electrodes facing upwards. 
         [0044]    Optionally, step (e) of removing the sacrificial substrate, laminating an attaching polymer over and around the membrane and removing the detachable tape comprises the steps of: 
         [0045]    Laminating a polymer coating over the die and framework; 
         [0046]    Applying a carrier over the attaching polymer; 
         [0047]    Removing the removable tape; 
         [0048]    Plasma Etching or laser Skiving through attaching polymer to carrier, whilst protecting the grid of frameworks with a hard mask; 
         [0049]    Irradiating the interface layer through the sacrificial substrate to melt the interface layer, 
         [0050]    Removing the sacrificial substrate, and 
         [0051]    Applying an attaching polymer and 
         [0052]    Removing the carrier. 
         [0053]    Optionally, the carrier is a metal carrier and removing the carrier comprises etching the carrier away. 
         [0054]    Optionally, the sacrificial substrate comprises sapphire and the interface layer comprises AlN, TiN, GaN or InN, wherein the step of irradiating the interface layer through the sacrificial substrate comprises irradiating with an argon fluoride (ArF) laser or a Krypton fluoride (KrF) laser to reduce the nitride to metal and to melt the metal, detaching the sacrifical substrate from the electroded piezoelectric layer. 
         [0055]    Optionally, step (d) of positioning a die in each cavity, comprises positioning each die with the outer electrode in contact with the removable tape and the sacrificial substrate upwards. 
         [0056]    Optionally, claim  20 , wherein step (e) comprises:
       i. irradiating the interface layer to melt the interface;   ii. removing the sacrificial substrate;   iii. applying an attaching polymer, and   iv. removing the attaching tape.       
 
         [0061]    Optionally, the sacrificial substrate comprises sapphire and the interface layer comprises AlN, TiN, GaN or InN, wherein the step of irradiating the interface layer through the sacrificial substrate comprises irradiating with an argon fluoride (ArF) laser or a Krypton fluoride (KrF) laser to reduce the nitride to metal and to melt the metal, detaching the sacrifical substrate from the electroded piezoelectric layer. 
         [0062]    Optionally, applying an attaching polymer comprises applying a liquid crystal polymer film under and around the membrane and frame. 
         [0063]    Optionally, step (f) of drilling through attaching polymer to at least a first and a second via around each membrane; and through the piezoelectric material to the electrode thereunder comprises at least one of laser drilling and plasma etching. 
         [0064]    Optionally, step (g) comprises depositing a seed-layer over the outer surfaces and the holes; laying photoresist over the top surface; patterning the photoresist with first and second connections and upper connecting ring; electroplating copper into the pattern; stripping off the photoresist and removing the seed layer. 
         [0065]    Optionally, the method further comprises: applying Ni, Au, or Ni/Au contacts to the upper connection ring prior to stripping away the photoresist and seed layer. 
         [0066]    Optionally, step (h) comprises: depositing a seed-layer over the lower surfaces and the holes; laying photoresist over the lower surface; patterning the photoresist with lower pads and lower connecting ring; electroplating copper into the pattern; stripping off the photoresist, and removing the seed layer. 
         [0067]    Optionally, the seed layer is applied to upper and lower surfaces simultaneously. 
         [0068]    Optionally, the first and second connections, the upper and lower sealing rings and the lower pads are electroplated simultaneously. 
         [0069]    Optionally, step (i) comprises applying a layer of photoresist of appropriate thickness to the lower surface, patterning the photoresist with legs for surface mounting onto the lower pads, electroplating the legs into the pattern, and removing the photoresist, to below the lower connection ring and removing the seed layer. 
         [0070]    Optionally, the method further comprises applying Ni, Au, or Ni/Au contacts to the lower connection ring and legs prior to stripping away the photoresist and seed layer. 
         [0071]    Optionally, step (j) of removing a central region of the attaching polymer under the lower electrode comprises plasma etching away the attaching polymer whilst protecting the framework and a perimeter region of the attaching polymer with a hard mask. 
         [0072]    Optionally, the method further comprises removing remnants of the interface exposed by the removing of the central region. 
         [0073]    Optionally, the method further comprises thinning any attaching polymer from over the upper electrode. 
         [0074]    In some embodiments, the method further comprises removing part of the upper electrode to ensure isolation of the upper electrode from connection to the lower electrode. 
         [0075]    Optionally, the upper lid and the lower lid comprise materials selected from the group comprising: ceramics, metals and polymers. 
         [0076]    Optionally, step (k) of attaching an upper lid to the upper ring and a lower lid to the lower ring comprises reflowing a contact metal. 
         [0077]    Optionally, step (l) of attaching an upper lid to the upper ring and a lower lid to the lower ring comprises reflowing a contact metal. 
         [0078]    Optionally, step (n) of singulating the individual packaged thin film bulk resonator filters from the grid comprises cutting. 
         [0079]    Optionally, the dielectric grid of frameworks further comprises a copper dividing grid embedded within the dielectric material and step (n) of singulating the individual packaged thin film bulk resonator filters from the grid comprises selectively dissolving the copper dividing grid. 
     
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         [0080]    For a better understanding of the invention and to show how it may be carried into effect, reference will now be made, purely by way of example, to the accompanying drawings. 
           [0081]    With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of the preferred embodiments of the present invention only, and are presented in the cause of providing what is believed to be the most useful and readily understood description of the principles and conceptual aspects of the invention. In this regard, no attempt is made to show structural details of the invention in more detail than is necessary for a fundamental understanding of the invention; the description taken with the drawings making apparent to those skilled in the art how the several forms of the invention may be embodied in practice. In the accompanying drawings: 
           [0082]      FIG. 1  is a flowchart showing the steps of a manufacturing method for fabricating a sacrificial substrate with a parelectrical material grown thereon between electrode layers; 
           [0083]      FIGS. 1 a    to  1   ei  and  1   eii  are schematic sectional illustrations of the build up of an electroded piezoelectric layer deposited on a sapphire substrate; 
           [0084]      FIGS. 1   fi  and  1   fii  are schematic sectional illustrations of a plurality of individual dice, each consisting of an electroded piezoelectric film on a sacrificial substrate for use as FBAR core according to a first embodiment; 
           [0085]      FIG. 2  is a flowchart showing how an acoustic resonator of one embodiment may be fabricated; 
           [0086]      FIG. 3  is a schematic sectional illustration of a fiber reinforced polymer interconnect framework of cavities, with the dice of  FIG. 1   fi  positioned in the cavities; 
           [0087]      FIG. 4  is a schematic sectional illustration of a ceramic interconnect framework of cavities, with the dice of  FIG. 1   fi  positioned in the cavities; 
           [0088]      FIG. 5  is a schematic sectional illustration of the fiber reinforced polymer interconnect framework of cavities of  FIG. 3 , with the dice of  FIG. 1   fi  positioned in the cavities, and subsequently laminated with an attaching polymer film; 
           [0089]      FIG. 6  is a schematic sectional illustration of the structure of  FIG. 5 , with a carrier attached; 
           [0090]      FIG. 7  is a schematic sectional illustration of the interconnect framework of  FIG. 6  with the sacrificial substrate removed; 
           [0091]      FIG. 8  is a schematic sectional illustration of the structure of  FIG. 7  with holes the polymer film around the die removed through to the carrier; 
           [0092]      FIG. 9  is a schematic sectional illustration of the structure of  FIG. 8  with sacrificial substrate detached; 
           [0093]      FIG. 10  is a schematic sectional illustration of the structure of  FIG. 9  laminated with attaching polymer, filling the spaces around the membrane, the cavity left by the removal of the sacrificial substrate and covering the frame by a further 50 microns or so; 
           [0094]      FIG. 11  is a schematic sectional illustration of the structure of  FIG. 10  with the carrier removed; 
           [0095]      FIG. 12  is a schematic sectional illustration of the structure of  FIG. 11  with holes drilled through to the vias, and holes drilled through the attaching polymer to the upper electrode, and through the attaching polymer and the membrane to the lower electrode; 
           [0096]      FIG. 13  is a schematic illustration of the structure of  FIG. 12  with a seed layer covering the surface, including the surfaces of the drill holes; 
           [0097]      FIG. 14  is a schematic illustration of the structure of  FIG. 13  with drill holes filled and contact pads connecting the filled drill holes to the vias and electrodes, lower pads connected to the lower ends of the vias, and forming upper and lower sealing rings; 
           [0098]      FIG. 15  is a schematic illustration of the structure of  FIG. 14  with via posts grown from the lower pads to well below the lower sealing ring for surface mounting, such as for coupling to a land grid array LGA; 
           [0099]      FIG. 16  is a schematic sectional illustration of the structure of  FIG. 15  with contact pads and ring seals coated with nickel, gold or nickel gold terminations; 
           [0100]      FIG. 17  is a schematic sectional illustration of the structure of  FIG. 16  with the seed layer etched away; 
           [0101]      FIG. 18  is a schematic sectional illustration of structure of  FIG. 17  with the attaching polymer under on both sides of the membrane substantially thinned away and the interface layer removed; 
           [0102]      FIG. 19  is a schematic sectional illustration of structure of  FIG. 18  with lids applied above and below the membrane, the lids being sealed to the interconnecting frame by ring seals, providing hermetic sealing; 
           [0103]      FIG. 20  is a schematic sectional illustration of structure of  FIG. 18  after singulation from the grid of frameworks; 
           [0104]      FIG. 21  is a schematic sectional illustration of structure of  FIG. 20  from above, and 
           [0105]      FIG. 22  is a schematic sectional illustration of structure of  FIG. 21  from below; 
           [0106]      FIG. 23  is a flow chart showing a manufacturing route of a variant structure; 
           [0107]      FIG. 24  is a schematic sectional illustration of a single cavity and surrounding frame that is part of a grid of a fiber reinforced polymer interconnect framework of cavities, with a die of  FIG. 1   fii  positioned in the cavity, resting face downwards, with the sacrificial substrate face upwards on a removable tape; 
           [0108]      FIG. 25  is a schematic sectional illustration of the single cavity, surrounding frame and die of  FIG. 1   fii  face downwards, showing the sacrificial substrate being lifted off and away; 
           [0109]      FIG. 26  is a schematic sectional illustration of the structure of  FIG. 25  laminated with an attaching polymer that fills the space between the membrane and the frame, covers any remaining material from the interface layer, and fills the frame, overfilling by about 50 microns; 
           [0110]      FIG. 27  is a schematic sectional illustration of the structure of  FIG. 26  with the removable tape removed, exposing ends of the framework and the vias; 
           [0111]      FIG. 28  is a schematic sectional illustration of the structure of  FIG. 27  with holes through the polymer film down to the opposite ends of the vias, and hole drilled through the outer electrode and piezoelectric membrane to the inner electrode (as illustrated, the holes are through the polymer to the upper ends of the vias, and through the lower electrode and membrane to the upper electrode, but the structure is about to be turned over . . . ); 
           [0112]      FIG. 29  is a schematic sectional illustration of the structure of  FIG. 28  with metallic seed layers covering both upper and lower surfaces of the array, and coating the walls of the drill holes; 
           [0113]      FIG. 30  is a schematic sectional illustration of the structure of  FIG. 29  with the drill holes filled and contact pads and ring seals fabricated on each side; 
           [0114]      FIG. 31  is a schematic sectional illustration of the structure of  FIG. 30  with via posts grown from the pads on opposite side of the structure to the membrane to well beyond the sealing ring for surface mounting, such as for coupling to a land grid array LGA; 
           [0115]      FIG. 32  is a schematic sectional illustration of the structure of  FIG. 31  with the contact pads and the ring seals coated with nickel, gold or nickel gold; 
           [0116]      FIG. 33  is a schematic sectional illustration of the structure of  FIG. 32  with the seed layer etched away; 
           [0117]      FIG. 34  is a schematic sectional illustration of the structure of  FIG. 33  rotated through 180°, with the exposed (now) upper electrode etched away; 
           [0118]      FIG. 35  is a schematic sectional illustration of structure of  FIG. 34  with the attaching polymer substantially removed, and remnants of the interface layer removed from where exposed; 
           [0119]      FIG. 36  is a schematic sectional illustration of structure of  FIG. 35  with top and bottom lids attached to the lop and bottom ring seals; 
           [0120]      FIG. 37  is a schematic sectional illustration of structure of  FIG. 36  after sectioning through the grid of frameworks to singulate the packaged acoustic resonator from the grid. 
       
    
    
     DETAILED DESCRIPTION 
       [0121]    The present invention is directed to an acoustic resonator with a piezoelectric membrane that resonates when an alternating current having an appropriate voltage and frequency is applied. This enables it to convert electrical signals into mechanical energy, and filters RF frequencies that cause noise in RF devices such as mobile phones and the like. The component is thus a switchable tunable acoustic-resonator-filter. 
         [0122]    One high performance piezoelectric material the mixed Barium—Strontium Titanate B x S (1-x) TiO 3 . 
         [0123]    When a signal of around 0.8 MV/cm (19.2V for 2400 A of thick BST membrane) is applied to a BST membrane, it resonates. By converting electrical energy into mechanical energy in this manner, BST films may be used as filters that absorb radio frequency electronic signals. Such thin film bulk acoustic resonator FBAR filters with good Q values (&gt;1000) are known. 
         [0124]    To achieve high efficiency and reliability, the piezoelectric material is preferably epitaxially grown and may be single crystal or polycrystalline. 
         [0125]    BST may be epitaxially grown on a substrate with appropriate lattice spacing. One such substrate is a C-plane &lt;0001&gt; sapphire wafer. These are currently commercially available in diameters of 2″, 4″ 6″ and 8″, and in thicknesses of from 75 microns to 500 microns. 
         [0126]    The membrane requires inert electrodes on each side and is packaged for protection. To protect from the atmosphere and particularly from moisture, it is preferably hermetically or at least semi-hermetically sealed. 
         [0127]    Embodiments of the present invention are directed to packaged paraelectic membranes and to methods of fabrication of such packaged piezoelectric membranes. The packaging is a box consisting of a frame and top and bottom lids. Contacts for surface mounting are provided on the bottom surface of the frame. The frame has vias running through the frame. The bottom lid is attached to the inner perimeter of the bottom surface of the frame and protects the membrane. The vias are coupled to bottom contacts that extend beyond the frame, allowing surface mounting of the packaged components. 
         [0128]    An upper end of a first via is coupled to the lower electrode by a connecting pad and an upper end of a second via is coupled to the upper electrode by a second connecting pad. The top lid extends over the membrane, the connecting pads and the upper ends of the first and second vias. In this manner, none the connecting pads do not need to run out from under the edge of either lid. Consequently the lids can be securely and tightly attached to the frame providing a high quality seal. 
         [0129]    The lids themselves may be ceramic, silicon, glass or metal. Such lids are commercially available. Where hermetic sealing of the component is not required, such as where the component is used in a device that is itself hermetically sealed, the lids may be fabricated from other materials such as polymers. Preferably such polymers are, nevertheless, characterized by ultra low moisture absorption. Liquid crystal polymers LCP) are suitable candidates. 
         [0130]    It is a feature of embodiments of the invention that the BST membrane is attached to the surrounding frame by a polymer that surrounds the edges of the membrane and supports the outer perimeter of the lower face. Optionally, the polymer also supports an outer perimeter of the top face. As with the lid, to enhance protection from moisture, preferably the polymer is a liquid crystal polymer LCP. 
         [0131]    To obtain high acoustic resonance, the piezoelectric membrane such as BST is preferably epitaxially grown. A good sacrificial substrate for growing BST membranes is the C plane of a single crystal sapphire wafer. 
         [0132]    There are a number of variant manufacturing processes which result in slightly different structures. 
         [0133]    Common to two manufacturing routes described hereunder, an interface layer that may be AlN, TiN, GaN or InN is first deposited onto the sacrificial substrate. The interface layer may have a thickness of one or two microns (1000 Angstroms to 2000 Angstroms). Remnants of this interface layer under the lower electrode, at least around the perimeter protected by polymer is a good indication that the structure was processed by the fabrication route described hereunder. 
         [0134]    A lower electrode that is typically platinum but may be tantalum is deposited over the interface layer. The piezoelectric material (such as BST) is deposited thereover, and a second electrode is deposited over the piezoelectric material. The second electrode may only cover part of the surface of the piezoelectric material and may be deposited into a pattern or panel plated thereonto and partially stripped away. The sapphire wafer is then singulated into individual dice. Each die with the electrodes and piezoelectric membrane is positioned within a cavity of a dielectric gridwork of frames defining cavities with vias running vertically through the frame, typically onto a removable tape, which may be a tacky film forming the bottom of the cavities. In one variant process described hereunder, the die is placed into the cavity with the piezoelectric material and electrodes upwards, and in another variant process described hereunder, the die is placed into the cavity with the piezoelectric material and electrodes downwards. The two variant methods result in slightly different structures also detailed below. 
         [0135]    In common to both structures and processes, the sacrificial substrate is removed. This may be achieved by irradiating it through the sacrificial substrate to melt the interface layer. An appropriate laser may be used to irradiate the sapphire sacrificial substrate to metallize and then melt the nitride interface layer. An appropriate laser may have a power of 200˜400 mJ/cm 2  and may, for example, be an argon fluoride (ArF) excimer laser (laser) with a wavelength of 193 nm or a Krypton fluoride (KrF) excimer laser with a 248 nm wave-length. Sapphire is transparent to these lasers, but the interface layer of AlN, TiN, GaN or InN absorbs the energy and heats up, is converted into the metal and then melts, releasing the sapphire substrate. 
         [0136]    In the final structure, the membrane is physically attached to the frame by an attaching polymer that is typically a liquid crystal polymer. The upper and lower electrodes are coupled to the upper ends of vias in the upper end of the frame by copper pads, and a top lid covers the membrane and the upper ends of the vias. A bottom lid covers the cavity below the membrane and is attached to the lower surface of the bottom frame. The cavities above and below the membrane allow it to vibrate, but optionally, to provide mechanical support, the upper surface is coated with a thin layer of polymer, which may be up to about 5 microns thick. 
         [0137]    The bottom lid covers the lower aperture beneath the membrane, and is fixed to the frame by a seal around its inner perimeter, such that the lower contacts for surface mounting are attached to the lower end of vias around and beyond the lower lid. 
         [0138]    With reference to  FIG. 1  and to the build ups shown schematically in corresponding  FIGS. 1 a  to 1 f   , a method of fabricating the piezoelectric membrane on a sacrificial substrate is now detailed. 
         [0139]    Firstly a sacrificial substrate is obtained—step  1 ( a ). This may be a c-cut sapphire (Al 2 O 3 ) wafer, for example. The wafer  10  is typically in the range of 100 microns to 250 microns thick. Sapphire wafers are commercially available in a range of diameters, from about 2″ to about 8″. An interface layer  12  is grown on the surface of the sacrificial substrate  10 —step( 1   b ). The interface layer  12  may be a nitride such as AlN, TiN, GaN or InN, for example. The interface layer  12  typically has a thickness of one or two microns, ibut may be from 500 Angstroms to 4000 Angstroms thick. 
         [0140]    A lower electrode  14  is then deposited onto the interface layer  12  (step  1   c ). 
         [0141]    Typically the lower electrode  14  comprises an inert metal, such as platinum or tantalum. The thickness of the lower electrode  14  is typically between about 1 and 2.5 microns, and has a structure allowing the epitaxial growth of BST thereupon. The interface layer  12  and the lower electrode  14  may be grown by Molecular Beam Epitaxy MBE. 
         [0142]    A layer of piezoelectric material  16 , that is typically an epitaxial layer of barium-strontium-titanate BST is grown on the lower electrode (step  1   d ). In one embodiment, the piezoelectric material  16  is grown by Molecular Beam Epitaxy MBE. Molecular beam epitaxy takes place in high vacuum or ultra-high vacuum 
         [0000]    (10 −8  Pa). The low deposition rate of MBE which is typically less than 3000 nm per hour, allows films to grow epitaxially on substrates with appropriate lattice spacing. These deposition rates require a proportionally better vacuum to achieve the same impurity levels as other deposition techniques. The absence of carrier gases as well as the ultra high vacuum environment result in the highest achievable purity of the grown films 
         [0143]    Alternatively however, other technologies such as pulsed laser deposition, RF sputtering or atomic layer deposition may be used to prepare the thin films of the interface layer  12  (AlN, TiN, GaN or InN, for example), the lower electrode  14  (Pt or Ta for example), and the piezoelectric material  16 , BST for example. 
         [0144]    Epitaxial growth of the BST  16  is required for good reproducibility and optimum performance. The thin-film of piezoelectric material  16  may be single crystal or polycrystalline. The thickness of the piezoelectric material  16  is typically in the range of from about 1 to about 5 microns, and may be around 2500 Angstrom, for example. 
         [0145]    The ratio of barium to strontium in BST thin films may be accurately controlled. For different applications, the selected B/S ranges may be varied from about 25/75 to about 75/25 but preferably is in the range of from about 30/70 to about 70/30. The appropriate ratio is governed by film thickness, the maximum resonating field (V/um), and the relative proportions of the ions in the mixed structure may be used to optimize the Q factor. 
         [0146]    Upper electrodes are now fabricated on the piezoelectric material  16  (step  1   e ). In one variant (shown as  FIG. 1   ei ), an array of discontinuous upper electrodes  18   i  is fabricated on the piezoelectric layer  16 . The discontinuous upper electrodes  18   i  may be sputtered and then selectively etched using a photoresist mask, or may selectively sputtered into a photoresist mask. 
         [0147]    Alternatively, in the variant shown in  FIG. 1   eii , a continuous upper electrode  18   ii  is fabricated on the piezoelectric layer  16 . 
         [0148]    The upper electrodes  18   i,    18   ii  typically have thicknesses of around 1 micron. 
         [0149]    Typically, the upper electrode  18   i,    18   ii  will comprise a double layer, having a first layer of aluminum, platinum or tantalum in contact with the BST and a second layer of copper deposited thereover. As illustrated by  FIGS. 1 a    to  1   ei ,  1   eii , these steps are generally accomplished in a large array of components on a sapphire wafer. 
         [0150]    At this stage, the sacrificial substrate  10  (e.g. wafer of sapphire) may be diced into individual components or dice  20   i  ( 20   ii ). Such individual dice are shown in  FIGS. 1   fi  and  1   fii.    
         [0151]    The dice  20   i  ( 20   ii ) may be positioned within the cavities defined by a grid of interconnect frames on a sacrificial substrate. There are two main processing routes. In the first processing route described with reference to  FIG. 2 , and to schematic illustrations  3  to  22  the dice  20   i  may be positioned with the piezoelectric layer  16  and electrodes  14 ,  18   i  uppermost, or, in a second processing route described with reference to  FIG. 23 , and to schematic illustrations  24  to  36 , the dice  20   ii  may be positioned with the piezoelectric layer  16  and electrodes  14 ,  18   ii  uppermost. 
         [0152]    With reference to the flowchart of  FIG. 2 , a first processing route for fabricating packaged thin film bulk acoustic resonators FBAR filter with good Q values is presented. 
         [0153]    The individual dice  20   i  of  FIG. 1   fi  obtained via the process shown in  FIG. 1  may be positioned piezoelectric layer  16  and electrodes  14 ,  18   ii  uppermost onto a ring tape in readiness for pick &amp; place. 
         [0154]    In this first processing route the individual dice  20   i  are placed sacrificial substrate  10  downwards (i.e. electrode  18   i  upwards) in the cavities  25  defined by a grid of interconnect frames on a removable tape  26 —step ( 2   b ). 
         [0155]    The grid of interconnect frames may be a polymer grid of interconnect frames  22  with embedded copper vias  24  as shown in  FIG. 3 , or a ceramic grid of interconnect frames  28  with embedded copper vias  24  as shown in  FIG. 4 . The removable tape  26  may be a tacky polymer membrane, for example. In general, ceramic grids of interconnect frames  28  with conducting vias  24  running vertically there through may be fabricated by LTCC or HTCC. Such ceramic grids are commercially available. Ceramic interconnect frames have better hermetic sealing. Polymer frames may, however provide adequate sealing for some applications and will generally be cheaper to manufacture and process. 
         [0156]    With reference to  FIG. 3 , if a polymer matrix grid of interconnect frames  22  is used, a high Tg polymer with a glass transition temperature above 280° C. and preferably above 300° C. should be used. It is essential that the polymer  22  has a low take-up of water. Liquid crystal polymers are ideal. Where the grids of interconnect frames has a polymer matrix, it is preferable that the matrix and/or the polymer used for attaching the piezoelectric membrane is liquid crystal polymer (LCP). 
         [0157]    With reference to  FIG. 4 , where the grid of interconnect frames  28  is ceramic, it may be a monolithic ceramic support structure that is cofired with in-built conductive vias  24  of gold, copper or tungsten, for example. The co-fired ceramics technology is established in multi-layer packaging for the electronics industry, such as military electronics, MEMS, microprocessor and RF applications. One manufacturer is Murata. Both high and low temperature cofired ceramics, HTCC and LTCC are known. Such structures are available in arrays of up to 8″×8″, and, whilst not allowing the same throughput as the polymer grid of interconnect frame technology developed by Zhuhai Access, is, nevertheless, an alternative that allows true hermetic sealing. 
         [0158]    Whichever type of grid of frames  22 ,  28  is used, the depth of the grid of interconnect frames is about 50 microns thicker than that of the dice  20  and is typically in the range of 150 microns to 300 microns. Due to the additional thickness of the frame  22  ( 28 ), mechanical pressure on the piezoelectric membrane  16  is avoided. This is important since piezoelectric structures such as BST convert mechanical stress to voltage differences there-across, and convert electrical signals there-across to mechanical deformations. 
         [0159]    The grid of interconnect frames  22  ( 28 ) is positioned on a removable tape  26  which may be a tacky membrane, for example. A pick &amp; place robot may be used to position the dice  20   i  with the sacrificial substrate  10  face down, and the piezoelectric layer  16  and upper electrode  18   i  face up within each socket of the grid of interconnect frames  22  ( 28 )—step ( 2   b ). 
         [0160]    Since the subsequent processing is the same for both ceramic and polymer grids of interconnect frames, the process is now explained using figures that illustrate a grid of polymer interconnect frames. This proprietary technology has been developed by Zhuhai-Access and enables fabrication in very large arrays on framework panels that are currently up to 21″×25″. However, as stated hereinabove, ceramic grids of interconnect frames of up to about 200 mm×200 mm are commercially available and may be used instead. 
         [0161]    The dice  20   i  and framework  22  ( 28 ) are laminated with an attaching polymer  30 —step ( 2   c ). A schematic illustration of dice  20   i  within the cavities  25  of a polymer interconnect framework  22  with attaching polymer  30  is shown in  FIG. 5 . There are a number of commercially available candidate materials for the attaching polymer  30 . By way of non-limiting illustration only, these include: Ajinomoto ABF-T31, Taiyo Zaristo-125, Sumitomo LAZ-7751 and Sekisui NX04H. 
         [0162]    Preferably, however, the attaching polymer  30  is a liquid crystal polymer. Liquid crystal polymer films may be processed at temperatures in the range of 240° C. to 315° C. Such materials have very low permeability to water and help protect and seal the piezoelectric membrane. 
         [0163]    The thickness of the attaching polymer  30  is generally about 50 microns more than the depth of the frame  22 . 
         [0164]    A carrier  27  is applied over the attaching polymer  30  (step  2   d ). The carrier may be a metal carrier, such as a copper carrier, for example. The resulting structure is schematically shown in  FIG. 6 . 
         [0165]    The removable tape  26  is now removed, exposing the sacrificial substrate  10  and the bottom ends of the frame  22 , including the vias  24  (step  2   e ). The resulting structure is schematically shown in  FIG. 7 . 
         [0166]    Referring to  FIG. 8  which is an enlarged schematic focusing on one component, but noting that the processing typically occurs in an array, the attaching polymer  30  around the die  20   i  is removed down to the carrier  27  (step  2   f ). Plasma etching or laser skive-away may be used. A hard mask  29 , such as a stainless steel mask may be used to protect the frame  22  ( 28 ). 
         [0167]    The sacrificial substrate  10  is then removed (step  2   g ). One way of achieving this is by laser irradiation through the sacrificial substrate  10 , heating and melting the interface  12 . Where the interface is a nitride layer, this may be reduced to the metal and then melted. The laser irradiation may use a pattered laser with a power of 200˜400 mJ/cm 2 . An argon fluoride (ArF) excimer laser (laser) with a wavelength of 193 nm or a Krypton fluoride (KrF) excimer laser with a 248 nm wave-length may be used. Sapphire substrates are transparent to these lasers, but the nitride layer absorbs them and heats up, is converted into the metal and then melts, releasing the sapphire substrate which is lifted away leaving the structure of  FIG. 9 . 
         [0168]    Referring to  FIG. 10 , the attaching polymer  30  is applied (step  2   h ), filling the space around the perimeter of the nitride  12 , electrodes  14 ,  18   i  and piezoelectric membrane  16 , attaching them to the frame  22 ,  28  and filling the cavity left by the removal of the sacrificial substrate  10 . The attaching polymer  30  also extends below the frame  22 ,  28  a further 50-150 microns. In one embodiment, 
         [0169]    The carrier  27  is now removed. Where carrier  27  metal, such as copper, for example, it may be etched away (step  2   i ) giving the structure shown schematically in  FIG. 11 . 
         [0170]    With reference to  FIG. 12 , showing one membrane  16  encapsulated in the attaching polymer  30  within a cavity of a polymer grid of interconnect frames  22  with conductive vias  24  therethrough, the upper electrode  18   i  may be accessed by drilling a hole  32  through the attaching polymer  30 , and the lower electrode  12  may be accessed by drilling a second hole  34  through the attaching polymer  30  and the piezoelectric membrane  16 , stopping once the lower electrode layer  14  is reached. Holes  36  may also be drilled through to the copper vias  24  from both sides (step  2   j ). In one embodiment, laser drilling is used. In another embodiment, plasma etching is used whilst protecting the surrounding attaching polymer  30  with an appropriate mask, such as a stainless steel (e.g. 304 SS and 316 SS) hard mask ( 29  see  FIG. 9 ), for example. Optionally, a combination of laser drilling and plasma etching may be used. 
         [0171]    The drill holes  32 ,  34 ,  36  are now filled with copper, and coupled to the vias  24  through the interconnect framework  22  step ( 2   k ). At the same time, sealing rings are fabricated. 
         [0172]    With reference to  FIG. 13 , this step may be achieved by first sputtering a seed layer such as titanium Ti, a mixture of titanium and tantalum Ti/Ta or titanium and tungsten Ti/W. over the drill holes  32 ,  34 ,  36  and the surface of the polymer  30  and then sputtering a layer of copper  38  thereover. 
         [0173]    Copper is then pattern plated into the drill holes, the filled drill holes are coupled to the vias by upper pads  40  and lower pads  42  are created that allow surface mounting and provide access to the vias  24 . Sealing upper and lower sealing rings  44 ,  46  are fabricated on both sides of the framework giving the structure shown in  FIG. 14 . This may be achieved by applying a photoresist, patterning, electroplating and removing the photoresist. Pads  42  connect the electrodes to the vias in the frame. Upper and lower sealing rings  44 ,  46  are deposited. The resulting structure is shown in  FIG. 14 . 
         [0174]    With reference to  FIG. 15 , lower Cu pillars  48  are deposited by applying a photoresist, patterning, electroplating and removing the photoresist. The lower copper pillars  48  form a land grid array LGA or a ball grid array BGA pad and must be at least a 100 microns thick. The lower sealing ring  46  excludes the lower copper pillars  50 . The upper sealing ring  44  surrounds the membrane  16  and pads  40  to allow hermetic sealing of a lid over and around the pads. Typically it is fabricated on what will become the outer perimeter of the top surface of the interconnect frame, once the interconnect framework is sectioned into individual components. 
         [0175]    Referring to  FIG. 16 , to facilitate adhesion, the sealing rings  44 ,  46  and pillars  48  may be coated with Ni, Au or Ni/Au  50  (step  2   m ). 
         [0176]    Referring to  FIG. 17 , the seed layers  32  are then removed (step  2   n ). 
         [0177]    Next, the attaching polymer  30  covering the piezoelectric membrane  14  may be thinned down from each side (step  2   o ) using a controlled plasma to erode between the electrodes producing the structures of  FIG. 18 . The purpose of thinning away the film of attaching polymer is to allow the piezoelectric membrane  16  to resonate. Optionally, a thin layer (up to 5 microns) of polymer is nevertheless retained over the piezoelectric membrane  16  to provide mechanical support. The thickness of the attaching polymer film  30  above the top electrode  18   i  may be tailored to any desired thickness depending on the desired Q of the BST FBAR. 
         [0178]    Optionally, as shown in  FIG. 19 , the attaching polymer film  30  may be removed right down to the piezoelectric membrane  16 . 
         [0179]    Referring to  FIG. 20 , top and bottom lids  52 ,  54  are positioned under and over the piezoelectric membrane  16 , coupling to the Ni/Au sealing rings on the interconnect framework (step  2   p ). Using As/Sn sealing ring contacts on the lids  52 ,  54  that correspond to the Ni, Au or Ni/Au coated  50  sealing rings  44 ,  46  on the frame of the package enables reflow at the As/Sn eutectic which occurs at temperatures of about 320°-340° C. and seals the lids  52 ,  54  in position on the top and bottom of the package frame thereby hermetically encasing the piezoelectric membrane  16 . 
         [0180]    Any commercially available lids  52 ,  54  may be used. The lids  52 ,  54  may be LCP, ceramic, silicon, glass or metal. Such packaging solutions are used in MEMS packages. Lids that are plated with nickel and gold and provided with a gold tin eutectic frame for sealing are commercially available and conform to military standards. Also available are ceramic lids with glass sealants. 
         [0181]    The lids  52 ,  54  may be positioned and bonded in place onto the sealing rings  44 ,  46  of the frame within an inert gas environment, such as a nitrogen environment, for example, protecting the BST membrane from oxygen and moisture. 
         [0182]    Preferably the top lid  52  covers the pads  40  that connect the membrane to the vias in the frame, whereas the bottom lid  54  does not extend out to the lower copper pillars  48  for surface bonding the package  60  to a substrate. Consequently, it becomes unnecessary to run conductors under either lid which would deteriorate their sealing performance. 
         [0183]    The lower copper pillars  44  for surface mounting of the component extend below the bottom lid  54 . 
         [0184]    At this stage, the grid of interconnect frames may be singulated (step  2   q ) into separate components  60  each encased between top and bottom lids  52 ,  54 , and a surrounding interconnect frame  22 . See  FIG. 20 . Alternatively, the singulation may have occurred previously or may occur after additional steps. 
         [0185]    Top and bottom views are shown in  FIGS. 21 and 22 . 
         [0186]    It will be noted that there are also typically traces of the interface layer  12  under the bottom electrode  14 , between the bottom electrode  14  and the supporting polymer  30 . The interface layer may be AlN, TiN, GaN or InN, or Al, Ti, GA or In. This interface layer is a good indication that the structure was processed by one of the fabrication routes described herein, or by a variant thereof. 
         [0187]    With reference to  FIG. 23 , a variant process is shown. Essentially the main difference between the first fabrication route shown in  FIG. 2  and the second fabrication route shown in  FIG. 23  is that in the process shown in  FIG. 23  the die  20   ii  is positioned face down in the cavity  25  of a framework of cavities. Once again the framework may be a polymer framework  22  or a ceramic framework  28  and will include metallic vias  24  therethrough. Firstly, dies with the piezoelectric membrane are obtained—step  23 ( i ). The process shown in  FIG. 1  may be used. 
         [0188]    The dice are placed electrode downwards, sacrificial substrate upwards in a cavity of a framework of cavities on a removable tape—step  23 ( ii ). 
         [0189]    A framework  22  with dies  20   ii  positioned electrode  18   ii  downwards (sacrificial substrate  10  upwards) on a removable tape  26  is schematically shown in  FIG. 24 . 
         [0190]    In this variant process, the interface layer  12  is now irradiated through the sacrificial substrate using a laser to melt the interface layer and the sacrificial substrate is lifted away—step  23 ( iii ) giving the structure shown in  FIG. 25 . 
         [0191]    The polymer framework  22  or ceramic framework  28  with metallic vias  24  therethrough, and having the electroded piezoelectric thin film  70  in the cavities thereof  25 , on the removable tape  26  is then coated with an attaching polymer  30  that attaches the electroded piezoelectric thin film  70  to the framework  22  ( 28 ) and extends 50-150 microns beyond the framework  22 ,  28 —step  23 ( iv ) giving the structure shown in  FIG. 26 . The attaching polymer  30  may be applied as a film, for example. Preferably, a liquid crystal polymer is used to minimize moisture absorption. 
         [0192]    The removable tape  26  is now removed—step  23 ( v ), giving the structure shown in  FIG. 27 . 
         [0193]    Holes  134  may be drilled through the polymer down to the vias  24  in the frame, and a further hole  136  may be drilled through the piezoelectric layer  16  to access the inner electrode  14  through giving the structure shown in  FIG. 28 —step  23 ( vi ). The holes  136 ,  138  may be fabricated by laser drilling and/or by selective plasma etching through a mask. 
         [0194]    Seed layers  138  are applied to both sides, coating the surfaces of the drill holes  136 ,  138  giving the structure shown in  FIG. 29 —step  23 ( vii ). 
         [0195]    Connection pads  140 ,  142  and sealing rings  144 ,  146  are now fabricated—step  23 ( viii ). One fabrication route is by applying and patterning layers of photoresist on the two surfaces, and electroplating copper into the patterns on each side filling the holes  136 ,  138  giving the structure shown in  FIG. 30 . 
         [0196]    Referring to  FIG. 31 , via posts  148  are grown from the lower pads ( 140 —shown here at the top of the figure) to well beyond the lower sealing ring  144  for surface mounting, such as for coupling to a land grid array LGA—step  23 ( ix ). 
         [0197]    The sealing rings  144 ,  146  and via posts  148  are now electroplated with Nickel Ni and Gold Au or Ni/Au connections  50 —step  23 ( x ), giving the structure shown in  FIG. 32 . The photoresist is stripped away. 
         [0198]    The seed layers  138  are etched away—step ( 23   xi ) giving the structure shown in  FIG. 33 , which is also rotated through 180°. 
         [0199]    The upper electrode  18   ii  is partially etched away using an appropriate wet or dry etch, giving the structure shown in  FIG. 34 —step  23 ( xii ). 
         [0200]    The polymer  30  under the piezoelectric film  16  may be etched away using a hard mask hard mask  29  (shown in  FIG. 9 ), such as a stainless steel mask to protect the surrounding polymer and the terminations—step  23 ( xiii ). A schematic representation of the resultant structure is shown in  FIG. 35 . 
         [0201]    As described hereinabove with reference to the first embodiment, lids  152 ,  154  with corresponding gold-tin contact rings may be applied—step  23 ( xiv ) and bonded to the sealing rings of the structure by heating to the cause reflow of the Au/Sn eutectic. The resultant structure us shown in  FIG. 36 . 
         [0202]    Solder seal lids, sometimes marketed as Combo Lids™ are standard components used for high reliability packaging in the semiconductor industry. They provide corrosion and moisture resistance and reliable packaging. They also conform to the military specification MIL-M-38510. 
         [0203]    In alternative packages, ceramic lids may be used with a glass sealant, or, where hermetic sealing of the component is not required, such as where the whole device is subsequently hermetically sealed, an epoxy of other sealant may be used. Where appropriate, such as where hermetic sealing is not required, plastic lids such as liquid crystal polymer lids may be used with sealing rings of a low temp LCP on the package. 
         [0204]    As noted previously, fabrication typically occurs in arrays. The grid of frames may now be singulated into the individual components—step  23 ( xv ). It will be appreciated however, that the singulation could alternatively occur prior to the plasma thinning, enabling tuning individual components separately. The resultant structure is shown in  FIG. 37 . It will be appreciated that singulation may occur at a previous instance. 
         [0205]    It will be appreciated that the process route and structures shown lend themselves to much variation. A double lidded frame may include other components in addition to the piezoelectric membrane  16 , and may include two or more such membranes tuned to different frequencies, such as by having different thicknesses for example. 
         [0206]    Persons skilled in the art will therefore appreciate that the present invention is not limited to what has been particularly shown and described hereinabove. Rather the scope of the present invention is defined by the appended claims and includes both combinations and sub combinations of the various features described hereinabove as well as variations and modifications thereof, which would occur to persons skilled in the art upon reading the foregoing description. 
         [0207]    In the claims, the word “comprise”, and variations thereof such as “comprises”, “comprising” and the like indicate that the components listed are included, but not generally to the exclusion of other components.