Abstract:
This invention discloses a clock generator capable of automatically adjusting output clock when process, voltage, or temperature variation occurred. The clock generator comprises: a current generator, for generating a first current and a second current according to a bias signal; an oscillator, coupled to the current generator, for generating a clock signal according to the first current; a frequency detector, coupled to the oscillator, for generating a control signal according to the clock signal and a reference signal; and a bias voltage adjuster, coupled to the current generator and the frequency detector, for adjusting the bias signal according to the control signal; wherein, when the signal frequency of the clock signal changes, the bias signal corresponds to the bias voltage adjuster, to adjust the first current and the second current.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    (a) Field of the Invention 
         [0002]    The present invention relates to a clock generator, and more particularly, to a clock generator that is substantially immune from the influence of manufacturing process, supply voltage, and temperature. 
         [0003]    (b) Description of the Related Art 
         [0004]    The compensation correction circuits of manufacturing process, voltage, and temperature are used to stabilize variables and control oscillator. The oscillator in a different environment can output accurate frequency, immune from the influence of environment and manufacturing process. 
         [0005]    The general of compensation practice is to use another oscillator to detect changes in the environment, then the detection of the result is transmitted to compensate the circuit. This method requires a total of two oscillators which increase consumption of area and power. If these two oscillators mismatch, it is easy detected the results inaccurately and makes the output frequency different from the design. In addition, the compensation circuit controlls the current source to adjust the output frequency of the oscillator, but the current leakage of the transistor in the advanced manufacturing process would be a problem in this practice. To control the current extremely small, it is required a higher resolution and the more difficult to achieve. 
         [0006]    Another compensation practice is to use differences of the temperature coefficient to compensate. In order to generate appropriate temperature coefficient, the hybrid concentration of electronic and electric hole should be adjusted during the production process. In the actual production of on the need more than one procedure will increase production costs. During the production process, if the process on the drift can not be produced the correct temperature coefficient, it will lack repression to process variations. Therefore, the oscillator is made from the charge and discharge of resistors and capacitors, each resistor will need a positive temperature coefficient of the resistor and a negative temperature coefficient of the resistor, to connect in series to couple to offset the impact of temperature on the oscillation frequency. However, if the production in the process drifts, then the resistor will still be affected by temperature, so the precision of output frequency will be reduced. If the oscillator couples more groups such resistors, the repression to process variations will be worse. At low frequency, the output frequency precision is more easily influenced by temperature becouse of the requirement of the larger resistor. 
         [0007]    However, there uses the bandgap reference voltage regulator to have stable voltage to suppress the impact of voltage variability, and reduces effects from temperature and process variation with internal use of the temperature/process circuit. For high precision of the output frequency, the two circuits need more power consumption of several mA. If it is used for low power applications, it can not achieve high precision output. 
       BRIEF SUMMARY OF THE INVENTION 
       [0008]    One object of the present invention is to provide a clock generator with economizing on ping and the generated clock signal that is substantially immune from the influence of manufacturing process, voltage drift, and temperature. 
         [0009]    One object of the present invention is to provide a clock generator with cost saving. 
         [0010]    One object of the present invention is to provide a clock generator with improving the precision of the output frequency. 
         [0011]    One object of the present invention is to provide a clock generator with reducing consumption of power. 
         [0012]    One embodiment of the invention discloses a clock generator. The clock generator comprises: a current generator, for generating a first current and a second current according by a bias signal; an oscillator, coupled to the current generator, for generating a clock signal according to the first current; a frequency detector, coupled to the oscillator, for generating a control signal according to the clock signal and a reference signal; and a bias voltage adjuster, coupled to the current generator and the frequency detector, for adjusting the bias signal according to the control signal; wherein, when the signal frequency of the clock signal changes, the bias signal corresponds to the bias voltage adjuster, to adjust the first current and the second current. 
         [0013]    The present invention adjusts the passive components and controls the input of the oscillator, that can be obtained with high precision output frequency under variations of different temperature, manufacturing process and voltage. This method in the circuit produced without the additional concentration of electron and hole which can reduce cost. And it can control high resolution to achieve high precision output frequency with low power consumption according to adjust the passive components to control the output. It is suitable for low-power product applications. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]      FIG. 1  shows a schematic diagram illustrating a clock generator according to one embodiment of the invention; 
           [0015]      FIG. 2  shows a schematic diagram illustrating a clock generator according to one embodiment of the invention; 
           [0016]      FIG. 3  shows a schematic diagram illustrating a clock generator according to one embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0017]    First of all, please refer to  FIG. 1 , which shows a schematic diagram illustrating the clock generator according to a first embodiment of the invention. As shown in this figure, the clock generator  100  includes a current generator  101 , an oscillator  102 , a frequency detector  103 , a bias voltage adjuster  104 , a frequency to voltage converter  105 , and a comparator  106 . 
         [0018]    The current generator  101  couples to the oscillator  102 , the bias voltage adjuster  104 , and the comparator  106 . The current generator  101  generates the current I 1  and I 2  according to one of the output of the bias signal BS. Among them, the oscillator  102  generates a clock signal S by the current I 1  after the oscillator  102  receives the current I 1 . The frequency to voltage converter  105  couples to the current generator  101  to receive the current I 2  and the clock signal S. The current I 2  and the clock signal S convert by the frequency to voltage converter  105  and output a converted voltage CV to the comparator  106 . The comparator  106  couples to the voltage frequency converter  105  and the current generator  101 . The comparator  106  is used to compare the bias signal BS of the node N with the converted voltage CV, to generate the feedback signal FS to the current generator  101 . 
         [0019]    Following the operation of this embodiment will make a more detailed explanation of the principle. When the clock generator  100  is in the initial state, the current generator  101  according to the bias signal BS outputted by the bias voltage adjuster  104  generates the current I 1  and I 2 . Then, the oscillator  102  generates the clock signals S by the current I 1 , and the frequency to voltage converter  105  converts the clock signal S to a converted voltage CV by the current I 2 . Finally, the comparator  106  compares the converted voltage CV and the bias signal BS to adjust the current generator  101 . Furthermore, when the comparator  106  compares the converted voltage CV is different from the bias signal BS, the feedback signal FS adjusts the current generator  101  to make the current I 1  and I 2  be adjusted, and changes the converted voltage CV, until the converted voltage CV and the bias signal BS are the same. In other words, when the converted voltage CV and the bias signal BS are the same, it shows that the oscillator  102  outputs the clock signal S can be stabilized at the designed frequency range. 
         [0020]    In addition, in one embodiment, the clock generator  100  can add the frequency detector  103  to increase the frequency precision of the clock signal S. As shown in  FIG. 1 , the frequency detector  103  couples to the output end of the oscillator  102 , and determines whether the frequency detector  103  detects the frequency of the clock signal S or not according to the enable signal ES. When the oscillator  102  generates that the frequency of the clock signal S is different from the reference clock signal RS, the frequency detector  103  detects the frequency difference and outputs the control signals CS to the bias voltage adjuster  104  to adjust the bias signal BS of the output of the bias voltage adjuster  104 , to change the value of the current I 1  and I 2  until the output of the oscillator  102 , the clock signal S, has the frequency the same as the reference clock signal RS. Thus, the clock generator  100  increases more frequency precision. In other words, the frequency detector  103  can be used to calibrate the frequency of the clock signal S. Wherein, in order to achieve more power saving purposes, after the frequency detector  103  calibrates frequency of the clock signal S, that is to say, when the clock signal S is oscillated to the target frequency, the clock generator  100  can disable the frequency detector  103  by the enable signal ES to save unnecessary power consumption. 
         [0021]    We can understand from the above description, the first loop made by the current generator  101 , the oscillator  102 , the frequency to voltage converter  105 , and the comparator  106  in the clock generator  100 . The first loop can make the oscillator  102  for outputting the frequency of the clock signal S which oscillates in the designed frequency range. Furthermore, a second loop made by the current generator  101 , frequency detector  103  and the bias voltage adjuster  104  can make the oscillator  102  for outputting the frequency of the clock signal S which oscillates on the target frequency. 
         [0022]    Please refer to  FIG. 2 , which shows a schematic diagram illustrating the clock generator according to an embodiment of the invention. The current generator  101  of the clock generator  200  includes a transistor  101   a  and a current mirror circuit  101   b.    
         [0023]    The transistor  101   a  couples to the comparator  106  and the bias voltage adjuster  104  to output a control current Ic according to the feedback signal FS. The current mirror circuit  101   b  couples to the transistor  101   a  to the current I 1  and I 2  by the control current Ic. Wherein, current mirror circuit  101   b  includes transistors Mr, M 1  and M 2 . 
         [0024]    The control current Ic flows to the current mirror circuit  101   b , which the transistor M 1  generates the current I 1 , the transistor M 2  generates the current I 2 . When the aspect ratio of the transistor M 1  is designed to be “b” times more than the aspect ratio of the transistor Mr, the first current I 1  is substantially equal to “b” times more than the control current Ic. Similarly, when the aspect ratio of the transistor M 2  is designed to be “a” times more than the aspect ration of the transistor Mr, the second current I 2  is substantially equal to “a” times more than the control current Ic. 
         [0025]    As shown in  FIG. 2 , the drain of the transistor M 1  is coupled to the oscillator  102 , wherein the oscillator  102  generates the clock signal S by the current I 1  outputted from the transistor M 1 . The frequency to voltage converter  105  receives the current I 2  and the clock signal S, converts the current I 2  and the clock signal S to a converted voltage CV, and then the frequency to voltage converter  105  outputs the converted voltage CV to the comparator  106 . The comparator  106  compares the converted voltage CV and the bias signal BS, outputs the feedback signal FS to the transistor  101   a  to form a loop system. Moreover, according to one embodiment, the bias voltage adjuster  104  can be implemented by a variable resistor, but not be limited to the present invention. 
         [0026]    Please refer to  FIG. 3 , which shows a schematic diagram illustrating the clock generator according to an embodiment of the invention. As shown in  FIG. 3 , the clock generator includes a current generator  301 , an oscillator  302 , a frequency detector  303 , and a bias voltage adjuster  304 . 
         [0027]    The oscillator  302  couples the frequency detector  303  and generates a clock signal S by the current I outputted from the current generator  301 . The frequency detector  303  receives the clock signal S and the reference clock signal RS, and the frequency detector  303  determines whether the frequency detector  303  detects the frequency or not according to the enable signal ES. When the frequency detector  303  is enabled to detect the frequency difference between the clock signal S and the reference clock signal RS, outputs the control signal CS 1  and CS 2  to the bias voltage adjuster  304  and the current generator  301  according to the relationship between the clock signal S and the reference clock signal RS. 
         [0028]    The bias voltage adjuster  304  couples to the frequency detector  303  to adjust the bias signal BS by the control signals CS 1 , to make the current generator  301  for generating the chance of the current I to correct the frequency of the oscillator  302 . In other words, when the frequency of the clock signal S changes or the oscillator  302  outputs the oscillation frequency different from the reference clock signal RS, the bias voltage adjuster  304  corresponds to adjust the bias signal BS according to the changes of the frequency, to change the current I. 
         [0029]    In one embodiment of the present invention, the current generator  301  also includes a current mirror circuit  301   a  and at least one switch SW. The current mirror circuit  301   a  comprises a reference transistor Mr and at least one output transistor Mn. In this embodiment, the output transistors with n M 1 ˜Mn, and n is the positive integer greater than 1. Among them, the reference transistor Mr is used to control the output current of the output transistors M 1 ˜Mn by the control current Ic. 
         [0030]    The switch SW couples the gate of the output transistors M 1 ˜Mn and the gate of the reference transistor Mr. The switch SW is controlled to enable or disable by the control signal CS 2 . And the current generator  301  adjusts the current value according to the number of enabled switch SW. 
         [0031]    To note that, the value of the current I is equal to the sum of the current of the drain of the output transistors M 1 ˜Mn that stands on the enabled state of the switch SW. In other words, if the enabled number of the switch SW is 3 by the control signal CS 2 , then the value of the current I is the sum of the current of the drain of the transistors M 1 ˜Mn. By changing the value of the current I to adjust the frequency of the clock signal S generated from the oscillator  302 . 
         [0032]    In one embodiment of the present invention, the bias voltage adjuster  304  can be satisfied by a variable resistor. In another embodiment, the bias voltage adjuster  304  also can be satisfied by the thermal compensation resistor to reduce the impact of temperature from oscillator  302 . 
         [0033]    Therefore, the current generator  301  generates the current I transmitted to the oscillator  302 , and the oscillator  302  generates the clock signal S to the frequency detector  303 . The frequency detector  303  outputs the control signal CS 1  and CS 2  to the bias voltage adjuster  304  and the current generator  301  respectively by the clock signal S and the reference clock signal RS, to adjust the resistance value of the bias voltage adjuster  304  and the number of the switch SW to change the value of the output current I transmitted from the current generator  301 . To adjust the clock signal S generated by the oscillator  302 , and thus achieve the effect of the frequency correction of the oscillator  302 . 
         [0034]    In conclusion, by means of the three feedback control mechanisms of the current generator, the oscillator, and the voltage adjuster, the value of the current generated by the current generator will be adjusted, to change the frequency generated by the oscillator. Furthermore, the clock signal outputted by the oscillator of the clock generator will not be substantially influenced by the manufacturing process, the supply voltage, and the temperature. The frequency generated by the oscillator is stable in the design frequency.