Abstract:
A method for making a semiconductor device may include forming a dummy gate above a semiconductor layer on an insulating layer, forming sidewall spacers above the semiconductor layer and on opposing sides of the dummy gate, forming source and drain regions on opposing sides of the sidewall spacers, and removing the dummy gate and underlying portions of the semiconductor layer between the sidewall spacers to provide a thinned channel region having a thickness less than a remainder of the semiconductor layer outside the thinned channel region. The method may further include forming a replacement gate stack over the thinned channel region and between the sidewall spacers and having a lower portion extending below a level of adjacent bottom portions of the sidewall spacers.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to the field of electronic devices and, more particularly, to semiconductor devices and related methods. 
       BACKGROUND 
       [0002]    Some semiconductor devices utilize semiconductor-on-insulator (SOI) technology, in which a thin layer of a semiconductor (typically having a thickness of a few nanometers), such as silicon, is separated from a semiconductor substrate by a relatively thick electrically insulating layer (typically featuring a thickness of a few tens of nanometers). Integrated circuits using SOI technology offer certain advantages compared to traditional “bulk” technology for Complementary Metal Oxide Semiconductor (CMOS) integrated circuits. For example, SOI integrated circuits typically provide a lower power consumption for a same performance level. 
         [0003]    SOI circuits may also feature a reduced stray capacitance, allowing an increase of commutation speeds. Furthermore, the latch-up phenomena encountered in bulk technology may be mitigated. Such circuits are commonly used in System on Chip (SoC) and Micro electro-mechanical systems (MEMS) applications. SOI circuits may also be less sensitive to ionizing radiations, making them more reliable than bulk-technology circuits in applications where radiation may induce operating problems (e.g., aerospace applications). SOI integrated circuits may include memory components such as Static Random Access Memory (SRAM), as well as logic gates. 
         [0004]    One particular type of SOI technology that is helping to allow for continued CMOS scaling is fully depleted SOI (FDSOI). As opposed to a partially depleted SOI (PDSOI) device, in an FDSOI device a relatively thin semiconductor channel film is provided over the buried oxide (BOX) layer, such that the depletion region of the device covers the whole film. FDSOI devices may provide advantages such as higher switching speeds and a reduction in threshold voltage roll off, as compared to PDSOI devices, for example. 
         [0005]    One example FDSOI configuration is set forth in U.S. Pat. Pub. No. 2013/0193514 to Loubet et al. This reference discloses a method for making an FDSOI device in which an SOI substrate has a first region isolated from a second region. An SiGe layer is deposited on top of the SOI substrate in the second region. The substrate is subjected to a thermal oxidation process which drives in Ge from the SiGe layer to form an SiGeOI structure in the second region and an overlying oxide layer. If the SOI substrate is exposed in the first region, the thermal oxidation process further produces an oxide layer overlying the first region. The oxide layer(s) is(are) removed to expose an Si channel layer in the first region and an SiGe channel layer in the second region. Transistor gate stacks are formed over each of the Si channel layer and SiGe channel layer. Raised source and drain regions are formed from the Si channel layer and SiGe channel layer adjacent the transistor gate stacks. 
         [0006]    Despite the existence of such configurations, further enhancements in SOI devices may be desirable in some applications. 
       SUMMARY 
       [0007]    A method for making a semiconductor device may include forming a dummy gate above a semiconductor layer on an insulating layer, forming sidewall spacers above the semiconductor layer and on opposing sides of the dummy gate, forming source and drain regions on opposing sides of the sidewall spacers, and removing the dummy gate and underlying portions of the semiconductor layer between the sidewall spacers to provide a thinned channel region having a thickness less than a remainder of the semiconductor layer outside the thinned channel region. The method may further include forming a replacement gate stack over the thinned channel region and between the sidewall spacers and having a lower portion extending below a level of adjacent bottom portions of the sidewall spacers. 
         [0008]    More particularly, the thinned channel region may have a thickness in a range of 50 to 75% of the thickness of the remainder of the channel layer. By way of example, the thinned channel region may have a thickness in a range of 5 nm to 6 nm, and the remainder of the channel layer may have a thickness in a range of 8 nm to 9 nm. 
         [0009]    Forming the source and drain regions may include forming raised source and drain regions above the semiconductor layer on opposing sides of the sidewall spacers. Furthermore, the insulating layer may comprise a buried oxide (BOX) layer defining a fully-depleted semiconductor-on-insulator (FDSOI) configuration with the semiconductor layer. Forming the replacement gate stack may include forming a replacement metal gate stack, and forming the sidewall spacers may include forming nitride spacers. By way of example, the semiconductor layer may comprise at least one of silicon and germanium. 
         [0010]    A related semiconductor device may include a substrate, an insulating layer on the substrate, a semiconductor layer on the insulating layer and having a thinned channel region therein with a thickness less than a remainder of the semiconductor layer outside the thinned channel region, and a gate stack over the thinned channel region. The semiconductor device may further include sidewall spacers above the semiconductor layer and on opposing sides of the gate stack gate, with the gate stack having a lower portion extending below a level of adjacent bottom portions of the sidewall spacers. Source and drain regions may be on opposing sides of the sidewall spacers. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is cross-sectional diagram of a semiconductor device in accordance with an example embodiment. 
           [0012]      FIGS. 2-7  are series of cross-sectional diagrams illustrating method aspects associated with making the semiconductor device of  FIG. 1  in accordance with an example embodiment. 
           [0013]      FIG. 8  is a graph of extension resistance vs. silicon layer thickness in accordance with example embodiments. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0014]    The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout. 
         [0015]    By way of background, as CMOS development continues in its scaling trend, fully depleted devices (e.g., FINFET/Trigate and ultra-thin body BOX (UTBB)) have been the focal point for the better short channel control. In fully depleted devices, to have desired electrostatics (i.e., short channel control), the channel thickness generally needs to be relatively thin, with a rule of thumb being that the thickness is approximately one quarter of the gate length. However, with such a thin channel, the extension resistance (i.e., the resistance under the spacer close to the channel) may become problematic. Furthermore, the process margin may be relatively low for such channel thicknesses, as the gate reactive ion etch (RIE)/spacer RIE may further thin down the FIN/SOI, and may accordingly result in cutting off the channel region from the source/drain region, as will be appreciated by those skilled in the art. 
         [0016]    Generally speaking, an approach is provided herein which allows for a relatively thick semiconductor layer to be used to form the device structure, yet while still achieving a relatively thin channel area and the associated advantages thereof. In accordance with an example approach, after source/drain formation, during the replacement gate formation process when the dummy gate is removed, the semiconductor layer in the channel region is etched or thinned down to the desired thickness prior to formation of the final replacement gate stack. This provides a relatively thin channel but with thicker extension regions (i.e., below the gate sidewall spacers) to provide lower extension resistance. In the meantime, the dummy gate RIE and spacer RIE margin are both improved due to the thicker silicon layer. 
         [0017]    Turning now to  FIG. 1 , this approach and an associated semiconductor device  30  produced thereby are first described. The method begins with a OTBB FDSOI wafer including a semiconductor (e.g., silicon) substrate  31 , a BOX layer  32  on the substrate, and a semiconductor (e.g., monocrystalline silicon) layer  33  on the BOX layer. In the illustrated example, shallow trench isolation (STI) regions  34  are also included for separating adjacent electrical devices (e.g., transistors) from one another. While the examples set forth herein are silicon devices, it will be appreciated that the techniques presented may be used with other semiconductor configurations, including silicon germanium, III-V materials, etc. 
         [0018]    As noted above, for the present approach, a relatively thick semiconductor layer  33  is used compared to the normal thickness for a given process node. For the present example a 14 nm process node is assumed, for which an approximate 8 nm to 9 nm thickness may be used for the semiconductor layer  33 , although other thicknesses and process nodes (e.g., 10 nm, 28 nm, etc.) may be used in different embodiments. 
         [0019]    As seen in  FIGS. 2 and 3 , a dummy gate (e.g., polysilicon)  35  is formed on the semiconductor layer  33  over the location of the channel, and associated sidewall spacers  36  (e.g., silicon nitride, SiN) are also formed on sidewalls of the dummy gate. In the present example, raised source and drain regions  37 ,  38  are formed (e.g., via epitaxial silicon growth) on the semiconductor layer  33  on opposite sides of the dummy gate  35  and sidewall spacers  36 , as shown in  FIG. 4 . Secondary sidewall spacers  39  (e.g., SiN, SiBCN, SiOCN) are also formed laterally adjacent the sidewall spacers  36  and partially overlying the source and drain regions  37 ,  38 . However, it should be noted that different configurations may be used in some embodiments. For example, raised source and drain regions need not be used in all configurations, and the source and drain regions may instead be formed directly in the semiconductor layer  33 , for example, by initially forming the semiconductor layer to a desired thickness and implanting an appropriate dopant in the regions where the source and drain are to be located, as will be appreciated by those skilled in the art. 
         [0020]    An oxide  40  (e.g., SiO 2 ) may be filled over the source and drain regions  37 , the spacers  36 ,  39 , and the dummy gate  35  and patterned (e.g., via chemical-mechanical polishing, CMP) to stop on the gate nitride hard mask, and the gate mask and dummy gate may be removed, as seen in  FIG. 5 . As such, this allows the channel region  41  which was beneath the dummy gate  35  to be thinned down to the desired thickness, such as by wet (e.g., SC1) or dry (e.g., HCl) etching as seen in  FIG. 6 . By way of example, for the 14 nm process node mentioned above, the semiconductor layer  33  may be about 8 nm to 9 nm thick, and the channel region  41  may be thinned to about 5 nm to 6 nm, although other dimensions may be used in different embodiments. Considered alternatively, the thinned channel region  41  may have a thickness in a range of about 50 to 75% of the thickness of the remainder of the channel layer, for example. 
         [0021]    Thus, the extension regions  42  directly adjacent the ends of the thinned channel area or region  41  remain of the original thickness (e.g., 8 nm), while the channel region is thinner (e.g., 5 nm to 6 nm). As shown in the graph  80  of  FIG. 8 , for example, the use of an 8 nm thickness for the extension regions instead of a 6 nm extension region results in approximately a 25% reduction in extension resistance. 
         [0022]    After thinning of the channel region  41 , a standard gate replacement process may be used to form the final gate stack  43  overlying the channel region  41  and between the spacers  36 , as seen in  FIG. 7 . For example, the gate stack  43  may be a replacement metal gate stack, although other gate configurations may be used in different embodiments. The oxide layer  40  may be removed and subsequent conventional processing steps may be performed as appropriate to provide the completed semiconductor device  30  shown in  FIG. 1 , as will be appreciated by those skilled in the art. 
         [0023]    It should be noted that while the semiconductor device  30  and method for making the same have been described herein with respect to UTBB and FDSOI, other SOI configurations (e.g., conventional SOI, PDSOI, etc.) may also be used in different embodiments. Moreover, in some embodiments the semiconductor device  30  may be configured with a “back” gate, in which the body of the device is biased on the backside of the substrate  31 , as will be appreciated by those skilled in the art. In addition to the lower extension resistance noted above, another advantage of the above-described approach is that this may provide for a reduction in wafer costs. More particularly, because the entire silicon layer  33  need not be formed or thinned to the relatively thin channel thickness, this may lead to a relatively easier, and less costly, wafer fabrication process. 
         [0024]    Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is understood that the invention is not to be limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included within the scope of the appended claims.