Abstract:
A current steering semi-digital reconstruction filter for a digital-to-analog conversion circuit, which includes a shift register having a 1-bit digital input stream and a plurality of output taps, where each output tap provides a 1-bit signal which has a value of a logic 1 or a logic 0, and a plurality of resistive paths, where each resistive path includes a resistive element which is connected to a common current source and to a first terminal of an active high switch and a first terminal of an active low switch. A single output tap is used to control the active high switch and the active low switch for a single resistive path. A second terminal of each active high switch of each of the plurality of resistive paths is connected to a non-inverted current path, and a second terminal of each active low switch for each of the plurality of resistive paths is connected to an inverted current path.

Description:
SPECIFICATION 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a digital-to-analog filter. More specifically, the present invention relates to a digital-to-analog filter which uses current steering techniques. 
     2. Brief Description of the Related Technology 
     Previous methods for digital-to-analog (D/A) conversion and reconstruction filtering involve several methods. The actual D/A conversion process has been accomplished using methods such as a single current source and sink, or by dumping charge from a switched capacitor that has been charged to either a positive or negative reference voltage. Reconstruction filtering has been accomplished by using a combination of active and/or passive classical filtering techniques, such as continuous time active filters with resistors and capacitors, continuous time passive filters utilizing resistors, capacitors, and inductors, or switched capacitor filter techniques. A method of filtering which combines a D/A converter with a reconstruction filter has recently become known in the art. 
     Oversampled D/A converters generally include the following signal processing blocks: (1) an interpolator filter, or series of filters, which raises the sample rate of the incoming digital signal to a higher sample rate, (2) a digital sigma-delta processor (or noise shaper) which lowers the number of bits representing the signal by shaping the quantization noise in a way that places most of it at higher frequencies, (3) a D/A converter which converts the output of the noise shaper into an analog signal, and (4) an analog low pass filter which removes, or substantially lowers, the noise that was placed at higher frequencies by the noise shaper. 
     As illustrated in FIG. 1, a semi-digital reconstruction filter typically uses a tapped delay line, or shift register, to control a plurality of devices each of which has an associated gain factor. The outputs of the plurality of devices are then summed together to form a single output of the filter. In some cases, individual current sources are employed as the plurality of devices. The amount of current in each current source is designed such that a desired FIR filter response is achieved. The output of each current source is then provided, or steered, to a current summing node (IOUT) or to an alternative current summing node (IOUT*), depending on the logic state of the control bit (B N ) at the delay line tap associated with each current source. The currents at one or both of the current summing nodes are then converted to a voltage using standard current to voltage conversion techniques. Additional filtering may then be employed to remove extremely high frequency noise. 
     In other cases, the plurality of devices in the semi-digital filter FIR coefficients are represented as charge stored on a plurality of capacitors. The charge on each capacitor can then be summed by employing a switched capacitor summing amplifier. Once again, additional filtering may be employed to remove any extremely high frequency noise. 
     In another semi-digital filter scheme, the FIR coefficients are represented as a current value through a plurality of resistors. Each resistor is selectively connected to a voltage reference depending on the state of the individual control bit from the delay line tap associated with each individual resistor. The current is then summed and converted to a voltage by means of resistive feedback around an operational amplifier (op amp). As in the previous methods discussed, additional filtering may be employed to remove any high frequency noise. 
     In all sigma-delta D/A converters, there exists a need to filter the high frequency noise inherent to this method of conversion. It is common for a digital noise shaper (digital sigma-delta modulator) to have as its output a single bit. The single bit digital output signal is then converted to an analog signal using switched capacitor techniques or switched current source techniques. Once this conversion is made, filtering of the high frequency noise is then accomplished through a variety of means. 
     SUMMARY OF THE INVENTION 
     The method and apparatus described herein is one which uses a single current reference and a current divider network which includes a plurality of parallel resistive paths. The amount of current through each resistive path is dependent on the effective resistance in each resistive path. The current through each resistive path is steered to a current summing node, or an alternative current summing node, depending on the logic level of a control bit at a delay line tap associated with each resistive path. A shift register which shifts the single bit, output signal from a digital sigma-delta modulator, forms a delay line. The shift register includes a series of flip-flops. 
     The output of each flip flop provides the input of the next flip flop in the series. All flip-flops are clocked at the same rate. The output of each flip flop also provides the control bit associated with each resistive path. That is, for an individual resistive path, if the control bit is a logic 1, the current through the resistive path is steered to the current summing node. If the control bit is a logic 0, the current is steered to the alternative current summing node. Since a tapped delay line and a summed output(s) consisting of weighted values (with weight determined by resistance value of each resistive path) of the intermediate points in the tapped delay line are provided, a Finite Impulse Response (FIR) filter exists. Such a filter may be designed using techniques available to those smiled in the art. Any type of filter such as bandpass, bandreject, high pass, and low pass may be built using this technique. The present invention is directed to, a low pass filter which is desirable to remove high frequency noise generated by the sigma-delta process. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 schematically illustrates a prior art embodiment of a semi-digital FIR filter utilizing a plurality of current sources; 
     FIG. 2 schematically illustrates a semi-digital FIR filter which uses a single current source and current steering techniques of present invention; 
     FIG. 3 schematically illustrates an embodiment of the present invention which removes an effective DC offset using a current source; 
     FIG. 4 schematically illustrates an embodiment of the present invention which utilizes differential currents and differential voltages; and 
     FIGS. 5a-c schematically illustrate various embodiments to implement the resistive paths or R0 and R1 associated with the switches of FIGS. 2 and 3. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The present invention utilizes a single reference current, IREF, a resistive current division network, a method for steering the output of each individual resistor in the current steering network, a current summing node, an alternative current summing node, and a method to convert the current in the current summing node to a voltage. 
     FIG. 1 illustrates a prior art implementation of a semi-digital FIR filter 50 using a plurality of current sources 52 and 53. The 1-bit output from a sigma-delta modulator 16 is input to shift register 14 as input signal 12. The current flows through the non-inverted current switches (B0, B1) to non-inverted current summing node 62 and through inverter current switches (B0*, B1*) to inverted current summing node 58. Switches B0 and B0* are controlled by the logic level of output tap B0 of shift register 14. Switches B1 and B1* are controlled by the logic level of output tap B1. If output tap B0 is a logic 0, inverted current switch B0* is closed and non-inverted switch B0 is open, causing current to flow from current source 52 to inverted current summing node 58. If output tap B0 is a logic 1, non-inverted current switch B0 is closed and inverted current switch B0* is open, causing current to flow from current source 52 to non-inverted current summing node 62. Non-inverted current switch B1 and inverted current switch B1* would function in a similar manner, causing current to flow from current source 53 to non-inverted current summing node 62 or inverted current summing node 58, depending on the logic value of shift register output tap B1. 
     FIG. 2 illustrates a semi-digital FIR filter current steering circuit 10 of the present invention. FIG. 2 depicts a current steering circuit 10 which includes two control bits (B0 and B1) and their logical inverses (B0* and B1*) which are output from shift register 14 as output tap B0 and B1, respectively. These control bits are used to control whether the current in an individual resistive path 21, 23 is steered to non-inverted current summing node 62 (IOUT), or to the alternative current summing node, inverted current summing node 58 (IOUT*). In order for the individual currents through the resistive paths 21, 23 to remain constant, the current summing nodes 62, 58 (IOUT and IOUT*) must be held at identical voltages. For the example shown in FIG. 2, it will be assumed that summing nodes 62 and 58 (IOUT and IOUT*) are at zero volts. Thus, the current through resistive path 21, represented by resistive element R0, is represented by the following equation: 
     
         I0=IREF[R1/(R0+R1)] 
    
     Likewise, the current through resistive path 23; represented by resistive element R1, is given by the following equation: 
     
         I1=IREF[R0/(R0+R1)] 
    
     Therefore, the current in non-inverted current summing node 62 (IOUT) can be represented by the following equation: 
     
         IOUT(k)=I0[x(k)]+I1×[x(k-1)] 
    
     where x(k) is the digital input signal 12, illustrated in FIG. 1, where input signal 12 (x(k)) is output from sigma-delta modulator 16, and where IOUT(k) represents the output current in the non-inverted current summing node 62, and I0 and I1 are the currents through the two resistive paths 21, 23, for R0 and R1, respectively. 
     The standard equation for an FIR filter is given by: 
     
         y(k)=a.sub.0 [x(k)]+a.sub.1 [x(k-1)]+. . . a.sub.n [x(k-n)] 
    
     Since the equation for non-inverted current IOUT(k) is of the same form as for y(k), the structure illustrated in FIG. 1 is an FIR filter. The equation for non-inverted current IOUT(k) can also be written in the following way by substituting I0 and I1 as their equivalent functions of current source IREF, resistive elements R0 and R1, as given in the above equations by: 
     
         IOUT(k)=[IREF[R1/(R0+R1)]]x(k)+[IREF[R0/(R0+R1)]]x(k-1) 
    
     Table 1 provides the summed currents IOUT and IOUT* for all possibilities of switches B0 and B1 in FIG. 2. 
     
                       TABLE 1______________________________________B0     B1          IOUT      IOUT*______________________________________0      0           0         IREF0      1               ##STR1##                         ##STR2##1      0               ##STR3##                         ##STR4##1      1           IREF      0______________________________________ 
    
     Since, in FIG. 1, input signal 12 (x(k)) can take on only a value of logic 0 or logic 1, current summing nodes IOUT and IOUT* can only be equal to zero or positive values. In fact, both current summing nodes IOUT and IOUT* may take on values from zero to the value of current source IREF (FIG. 2). Thus, the structure illustrated in FIG. 2 adds an effective DC offset with a value of IREF/2. This can easily be removed by subtracting a fixed amount of current, IREF/2, from current summing nodes IOUT and IOUT*, as shown in FIG. 3. Table 2 illustrates that both current summing nodes, IOUT and IOUT*, may take on values from -IREF/2 to IREF/2. 
     
                       TABLE 2______________________________________B0   B1      IOUT           IOUT*______________________________________0    0         ##STR5##                        ##STR6##0    1         ##STR7##                        ##STR8##1    0         ##STR9##                        ##STR10##1    1         ##STR11##                        ##STR12##______________________________________ 
    
     In fact for each combination of switches B0 and B1, the value of inverted current summing node 58, IOUT*, is equal to negative the value of non-inverted current summing node 62, -[IOUT]. Th.us, the inverted and non-inverted currents are differential in nature. This differential current embodiment is used to remove any even-ordered distortion which may occur. 
     FIG. 4 illustrates a method of converting current summing nodes IOUT and IOUT* from differential currents to differential voltages via operational amplifier circuits 20 and 22. Each op amp circuit, 20 and 22, includes an op amp 25 and a feedback resistor 30. If desired, the differential voltages in this embodiment may be converted to a single-ended voltage 37 using series input resistor R A , voltage divider resistor network R C  and R D  and feedback resistor R B  together with op amp 27, as shown in FIG. 4. As stated previously, additional filtering of extremely high frequency noise can then be accomplished by connecting a capacitor C F  in parallel to feedback resistor 30 in FIG. 4. 
     Several techniques may be used to implement the resistive paths 21 and 23, via resistive elements R0 and R1 and associated switches B0, B0*, B1, and B1* of FIGS. 2 and 3. Resistive elements R0 and R1 may be resistors, as shown in FIGS. 2 and 3. As shown in FIG. 5a, an explicit resistor R i  and a pair of switches B i  and B i  * are utilized to implement resistive paths 25 and 27. The resistor R i  may be realized as a poly resistor, a diffused resistor, a thin film resistor, or by any of the standard methods of realizing resistors. The switches B i  and B i  * may be realized by employing CMOS transmission gates T 1  and T 2 , or single MOSFETS, to act as switches. In the technique of FIG. 5a, the resistance of an individual resistive path 25 or 27 would be the sum of the explicit resistor, R i , plus the effective &#34;on&#34; resistance of the switch B i  or B i  *. Care must be taken to make the &#34;on&#34; resistance of T 1  and T 2  negligible with respect to R i , or, alternatively, the &#34;on&#34; resistance of the switch B i  or B i  * may also be ratioed by the same ratio which is used to calculate R i . However, like the prior art techniques shown in FIG. 1, discussed above, any error in effective static switch &#34;on&#34; resistance will only change the effective FIR coefficient for the filter and will not affect the linearity of the filter. 
     Another technique that may be used to implement resistive paths 25 and 27 is shown in FIG. 5b, is to realize R0 or R1 in FIGS. 2 and 3 as the effective &#34;on&#34; resistance of a CMOS transmission gate T 1 , or single MOSFET transistor. In FIG. 5b, T 1  represents the effective resistance for R0 or R1. The switches B i  and B i  * are likewise realized as CMOS transmission gates T 2  and T 3 , or as single MOSFET transistors. The switches B i  and B i  * are designed such that the effective &#34;on&#34; resistance of gate T 2  is identical to the effective &#34;on&#34; resistance of gate T 3 . Thus, the effective resistance of the resistive paths 25 or 27 is the sum of the &#34;on&#34; resistance of gate T 1  plus the &#34;on&#34; resistance of gate T 2  or T 3 . Like the technique described above for FIG. 5a, the &#34;on&#34; resistance of gate T 2  and T 3  must either be made negligible with respect to the &#34;on&#34; resistance of gate T 1 , or they must be ratioed by the same ratio which is used to calculate the on resistance of gate T 1 . Once again, any error in effective static switch &#34;on&#34; resistance will only change the effective FIR filter coefficient and will not affect the linearity of the analog signal at current summing nodes 62 and 58, IOUT and IOUT*. 
     An alternative technique that may be used to implement resistive paths 25 and 27, shown in FIG. 5c. Resistive elements R0 and R1 and switches B0, B0*, B1, and Bi* are implemented as individual CMOS transmission gates T A  and T B , or as single MOSFET transistors. In this case, the &#34;on&#34; resistance of gate T A  is designed to be equivalent to the &#34;on&#34; resistance of gate T B . Thus, the effective resistance of the resistive paths 25 or 27 is the &#34;on&#34; resistance of gates T A  or T B . Like the above methods shown in FIGS. 5a or 5b, any error in effective static &#34;on&#34; resistance will only change the effective FIR filter coefficient (and therefore the frequency response of the filter) and not the linearity of the analog signal which results from using this technique. 
     The prime reason the current steering structure of the present invention is linear is because the effective current through each resistive path 25 or 27 is not dependent on the current through any of the other resistive path. Thus, ideally, the current through a resistive path 25 or 27 should not depend on the 1-bit digital input signal 12, x(k). This is true for the ideal cases of the three techniques described above and illustrated in FIGS. 5a-c. In practice, however, this may not be completely true. 
     If, in FIG. 5c, due to random manufacturing resistance mismatches, the &#34;on&#34; resistance of gate T A  is not equivalent to the &#34;on&#34; resistance of gate T B , then current I A  passing through switch T A  when shift register output tap B i  is a logic 1 would not be equivalent to current I i  through gate T B  when output tap B i  is a logic 0. This means current I i  through a resistive path 25 or 27, rather than being constant, is dependent on the input signal 12, x(k). This concept also applies to the embodiments illustrated in FIGS. 5a and 5b. Since the FIR filter structure as a whole is built as a current divider, if the current in one resistive path 25 or 27 changes, the amount of current through all paths 25 and 27 must change in order for the total current to remain equal to reference current IREF. Thus, there is potential for harmonic distortion to result. One of the first assumptions is that the value of current summing nodes IOUT and IOUT* must be held at the same potential. In practice, this may not be possible due to random op amp offset voltages. Fortunately, to the extent the harmonic clistortion is even-ordered, using differential non-inverted and inverted currents, IOUT and IOUT*, and converting them to differential voltages as shown in FIG. 4, will reduce the total harmonic distortion. 
     The present invention, therefore, is well adapted to carry out the objects and attain the ends and advantages mentioned herein as well as other ends and advantages made apparent from the disclosure. While preferred embodiments of the invention have been described for the purpose of disclosure, numerous changes and modifications to those embodiments described herein will be readily apparent to those skilled in the art and are encompassed within the spirit of the invention and the scope of the following claims.