Abstract:
A method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. An amorphous silicon layer is formed on the RSD in the PFET portion. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The amorphous layer in the PFET portion prevents epitaxial growth in the PFET portion during formation of the RSD in the NFET portion. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.

Description:
RELATED APPLICATION 
     This application is related to U.S. patent application Ser. No. 13/551,100, entitled “SEMICONDUCTOR STRUCTURE HAVING NFET EXTENSION LAST IMPLANTS” and filed even date herewith, the disclosure of which is incorporated by reference herein. 
     BACKGROUND 
     The present invention relates to semiconductor structures and, more particularly, to semiconductor structures having NFET extension last implants. 
     ETSOI (extremely thin silicon-on-insulator) is a leading candidate for continued scaling of planar silicon technology. Successful introduction of ETSOI into manufacturing requires integration of n-type metal oxide semiconductor (nMOS) and p-type metal oxide semiconductor (pMOS) devices with high performance and low leakage. ETSOI devices naturally have low leakage currents due to the extremely thin SOI layer (typically less than 10 nm). However, this extremely thin SOI layer often leads to high series resistance that lowers drive current and degrades performance. A key feature to reduce series resistance in ETSOI and therefore, improve performance is the use of raised source/drain (RSD) epitaxy. Ideal junction design for ETSOI devices with RSD epitaxy involves (i) low source/drain resistance (ii) low extension resistance and (iii) good link-up between source/drain and extension. 
     BRIEF SUMMARY 
     The various advantages and purposes of the exemplary embodiments as described above and hereafter are achieved by providing, according to a first aspect of the exemplary embodiments, a method of forming a semiconductor structure which includes: obtaining an extremely thin semiconductor-on-insulator (ETSOI) wafer having a PFET portion where a p-type field effect transistor (PFET) will be formed and an NFET portion where an n-type field effect transistor (NFET) will be formed; forming at least one gate structure in the PFET portion and at least one gate structure in the NFET portion; depositing a high quality nitride over the PFET portion and the NFET portion, the high quality nitride being unetchable in dilute hydrofluoric acid (HF); depositing a low quality nitride over the high quality nitride, the low quality nitride being etchable in dilute HF; etching the PFET portion to remove the high quality nitride and low quality nitride except for high quality nitride and low quality nitride adjacent to the at least one gate structure in the PFET portion; etching the PFET portion and the NFET portion to remove the low quality nitride; forming a doped faceted epitaxial silicon/germanium (SiGe) on the ETSOI adjacent to the high quality nitride and the at least one gate structure in the PFET portion to form a faceted raised source/drain (RSD) in the PFET portion and an amorphous portion on the high quality nitride; depositing a low quality nitride over the PFET portion and the NFET portion; etching the PFET portion to remove the low quality nitride while maintaining the low quality nitride adjacent to the high quality nitride and at least one gate structure to form disposable spacers from the low quality nitride adjacent to the high quality nitride and etching the NFET portion to remove the low quality nitride and high quality nitride except for high quality nitride and low quality nitride adjacent to the at least one gate structure in the NFET portion, the low quality nitride adjacent to the at least one gate structure in the NFET portion forming disposable spacers; ion implanting into the RSD in the PFET portion to render amorphous a top portion of the RSD in the PFET portion; etching the disposable spacers adjacent the at least one gate structure in the NFET portion and the PFET portion to leave at least the high quality nitride adjacent to the at least one gate structure in the PFET portion and at least the high quality nitride adjacent to the at least one gate structure in the NFET portion; forming a faceted epitaxial silicon RSD on the ETSOI adjacent to the at least one structure in the NFET portion; performing a rapid thermal anneal; ion implanting extensions into the ETSOI underneath the at least one gate structure in the NFET portion; and performing a short time scale anneal to activate the NFET extension implants but not diffuse them. 
     According to a second aspect of the exemplary embodiments, there is provided a method of forming a semiconductor structure which includes: providing a semiconductor structure comprising an extremely thin semiconductor on insulator (ETSOI) wafer having a PFET portion where a p-type field effect transistor (PFET) will be formed and an NFET portion where an n-type field effect transistor (NFET) will be formed, at least one gate structure in the PFET portion and at least one gate structure in the NFET portion, a high quality nitride spacer adjacent to the at least one gate structure in the PFET portion and a high quality nitride spacer adjacent to the at least one gate structure in the NFET portion, the high quality nitride being unetchable in dilute hydrofluoric acid (HF), and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion; forming an amorphous silicon layer on the RSD in the PFET portion; forming a faceted epitaxial silicon RSD on the ETSOI adjacent to the high quality nitride in the NFET portion; performing a rapid thermal anneal; ion implanting extensions into the ETSOI underneath the at least one gate structure in the NFET portion; and performing a short time scale anneal to activate the NFET extension implants but not diffuse them. 
    
    
     
       BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS 
       The features of the exemplary embodiments believed to be novel and the elements characteristic of the exemplary embodiments are set forth with particularity in the appended claims. The figures are for illustration purposes only and are not drawn to scale. The exemplary embodiments, both as to organization and method of operation, may best be understood by reference to the detailed description which follows taken in conjunction with the accompanying drawings in which: 
         FIGS. 1 to 20  illustrate the processing to form a semiconductor structure according to the exemplary embodiments in which: 
         FIG. 1  illustrates the formation of gate structures on an ETSOI semiconductor substrate having PFET and NFET portions; 
         FIG. 2  illustrates the deposition of a high quality nitride on the ETSOI substrate and gate structures; 
         FIG. 3  illustrates the deposition of a low quality nitride on the high quality nitride; 
         FIG. 4  illustrates the masking of the NFET portion while etching the low quality nitride and high quality nitride in the PFET portion; 
         FIG. 5  illustrates the stripping of the mask from the NFET portion; 
         FIG. 6  illustrates the etching of the low quality nitride; 
         FIG. 7  illustrates the formation of a doped epitaxial raised source/drain (RSD) on the PFET portion; 
         FIG. 8  illustrates the deposition of a low quality nitride on the semiconductor structure; 
         FIG. 9  illustrates the etching of the low quality nitride in the PFET and NFET portions and the etching of the high quality nitride in the NFET portion; 
         FIG. 10  illustrates the masking of the NFET portion and the formation of an amorphous layer on the RSD in the PFET portion; 
         FIG. 11  illustrates the stripping of the mask from the NFET portion; 
         FIG. 12  illustrates the etching of the remaining low quality nitride from the PFET and NFET portions and the forming of the RSD in the NFET portion; 
         FIGS. 13 to 16  illustrate the doping of the RSD in the NFET portion if it was not doped when formed; 
         FIG. 17  illustrates the masking of the PFET portion and the ion implanting of extensions in the NFET portion; 
         FIG. 18  illustrates the removal of the mask from the PFET portion and the short time scale anneal of the NFET portion to activate the extensions; 
         FIG. 19  illustrates the formation of nitride spacers in the PFET and NFET portions; and 
         FIG. 20  illustrates the formation of a silicide layer in the PFET and NFET portions. 
     
    
    
     DETAILED DESCRIPTION 
     In the exemplary embodiments, an extension last complementary metal oxide semiconductor (CMOS) integration scheme is demonstrated with the following key elements for 20 nm node and beyond: (i) in-situ boron doped (ISBD) silicon germanium to reduce PFET series resistance, (ii) extension last NFET and (iii) metal-gate/high-k gate structure. 
     Referring to the Figures in more detail, and particularly referring to  FIG. 1 , there is shown a semiconductor structure  100  having a p-type field effect transistor (PFET) portion  102  and an n-type field effect transistor (NFET) portion  104 . The PFET portion  102  is fabricated using pMOS technology while the NFET portion  104  is fabricated using nMOS technology. 
     The semiconductor structure  100  is fabricated using an ETSOI wafer  106  which includes a semiconductor substrate  108 , usually silicon, a buried oxide layer  110  (also referred to as a BOX layer) and an ETSOI layer  112 . The semiconductor substrate  108  may be made from semiconductor materials other than silicon. The ETSOI layer  112  may have a thickness of about 2 to 10 nanometers which is substantially thinner than a typical SOI layer. The semiconductor structure  100  may also include shallow trench isolation (STI)  114  to separate the PFET portion  102  from the NFET portion  104 . The ETSOI wafer  106  having STI  114  may be fabricated by conventional processing. 
     Semiconductor structure  100  may further include at least one gate structure  116  on PFET portion  102  and at least one gate structure  118  on the NFET portion. Each of the gate structures  116 ,  118  includes a gate dielectric  120 , a gate conductor  122  and a nitride cap  124 . Preferably, the gate dielectric  120  is a high-k gate dielectric and the gate conductor  122  is a metal gate conductor. The gate structures  116 ,  118  may be fabricated by depositing layers of gate dielectric, gate conductor and gate nitride followed by gate definition including photolithography, reactive ion etching (RIE) and resist strip. While there is only one PFET portion  102  and one NFET portion  102  shown in the Figures, it should be understood that the semiconductor structure  100  will typically have many such PFET portions  102  and NFET portions  104 , each having at least one gate structure. 
     Referring now to  FIG. 2 , about 2 to 5 nanometers of a high quality nitride  128  is deposited everywhere. A high quality nitride is a nitride that has an etch rate in dilute hydrofluoric (HF) acid of less than about 1 nanometer per minute. Dilute HF may be defined as typically HF:H 2 O (water)=1:50 but may also range from 1:10 to 1:100. Some examples of high quality nitrides are nitrides deposited by low-pressure chemical vapor deposition (LPCVD) and rapid-thermal chemical vapor deposition (RTCVD). 
     Thereafter, as shown in  FIG. 3 , 2 to 5 nanometers of a low quality nitride  130  is deposited over the high quality nitride  128 . A low quality nitride is a nitride that has an etch rate in dilute HF of more than about 10 nanometers per minute. Therefore, the low quality nitride etches at least 10 times faster than the high quality nitride in dilute HF. Some examples of low quality nitrides are nitrides deposited by plasma-enhanced chemical vapor deposition (PECVD). 
     Referring now to  FIG. 4 , a photoresist mask  132  is defined to cover the NFET portion  104  of the semiconductor structure  100 . Thereafter, by a two-step RIE process, the low quality nitride  130  and the high quality nitride  128  are etched in the PFET portion  102 . The nitride RIE is performed using inductively coupled plasma (ICP) with hydrogen (H 2 ) and fluorine-based chemistry. The fluorine-based gases may be hexa-fluoro-ethane (C 2 F 6 ), octa-fluoro-cyclobutane (C 4 F 8 ), and sulphur hexafluoride (SF 6 ). The gas ratios and ICP power may be adjusted to obtain anisotropic etch and selectivity to silicon and SiO 2 . The ICP power also determines the nitride etch rate with higher power leading to higher etch rates (that is, the nitride etch is more aggressive). In the two-step RIE process, the ICP power may be first kept low during the etch of the low quality nitride  130  and then increased during the etch of the high quality nitride  128 . 
     What remains are L-shaped spacers  134  of the high quality oxide  128  and disposable spacers  136  of the low quality nitride  130 . The L-shaped spacers  134  and disposable spacers  136  are adjacent to gate structure  116 . 
     The photoresist mask  132  is then stripped to result in the structure shown in  FIG. 5 . 
     Thereafter, the disposable spacers  136  may be removed from the PFET portion  102  and the low quality nitride  130  is removed from the NFET portion  104  by a dilute HF etch as shown in  FIG. 6 . 
     Referring now to  FIG. 7 , in-situ boron doped (ISBD) silicon germanium (SiGe) may be epitaxially grown on the PFET portion to form the raised source/drain (RSD)  138 . The high quality nitride  128  serves as a mask to prevent deposition of SiGe on the NFET portion  104 . 
     The SiGe epitaxy may be performed using chemical vapor deposition (CVD). Typical epitaxy temperature is in the 600-850° C. range and pressure in the 1-100 torr range. The exact process temperature and pressure are chosen based on (i) the requirement that the SiGe epitaxy must be selective to oxide and nitride, that is, crystalline SiGe is deposited only on exposed crystalline Si, and crystalline SiGe is not deposited on exposed oxide (STI regions) and exposed nitride (PFET cap and spacers  134 , and NFET high quality nitride  128 ), (ii) the desired Ge concentration in SiGe, and (iii) the gas sources of Si and Ge used in the process. Typical gases used may be (i) silane (SiH 4 ), dicholorosilane (SiH 2 Cl 2 ), or silicon tetrachloride (SiCl 4 ) as source of Si, and (ii) germane (GeH 4 ), germanium tetrachloride (GeCl 4 ), or isobutyl germane (C 4 H 12 Ge═(CH 3 ) 2 CHCH 2 GeH 3 ) as source of Ge. 
     The RSD  138  will be faceted due to the growth conditions of the ISBD SiGe. However, the portion  140  of the ISBD SiGe that grows on the L-shaped spacers  134  will be amorphous due to the L-shaped spacers  134  being noncrystalline (being formed of high quality nitride). No amorphous SiGe may grow on nitride  128  since it is noncrystalline and there is no crystalline seed to start growth of even amorphous SiGe. 
     Then, as shown in  FIG. 8 , another low quality nitride layer  142  may be deposited on the semiconductor structure  142 . The low quality nitride layer  142  has a thickness of about 2 to 5 nanometers. 
     The semiconductor structure  100  shown in  FIG. 8  then undergoes another two-step RIE process to remove horizontal portions of the low quality nitride layer  142  in both the PFET portion  102  and the NFET portion  104  and then remove the high quality nitride  128  from portions of the NFET portion  104  that are not protected by the low quality nitride. The operating parameters of the two-step RIE process may be similar to the two-step RIE process employed earlier. The resulting structure is shown in  FIG. 9  where the PFET portion  102  contains disposable spacers  144  adjacent to the L-shaped spacers  134  and the NFET portion  104  contains L-shaped spacers  146  and disposable spacers  148 . The L-shaped spacers  146  and disposable spacers  148  are adjacent to the gate structure  118 . 
     Referring now to  FIG. 10 , a photoresist mask  150  is defined over the NFET portion  104 . Then, the PFET portion  102  undergoes ion implanting  152  to form implanted layer  154 . The ion implanting causes the crystalline RSD  138  to become amorphous within layer  154 . The implanted layer  154  over the buffer portion  140  should also be amorphous since buffer portion  140  is amorphous. The implant species may be B or BF 2  or neutral species such as Si, Ge, Xe, Ar or N 2 . 
     The photoresist mask  150  is conventionally stripped as shown in  FIG. 11 . 
     As now shown in  FIG. 12 , the semiconductor structure is etched in dilute HF to remove the disposable spacers  144  from the PFET portion  102  and disposable spacers  148  from the NFET portion  104 . The dilute HF does not affect the spacers  134 ,  146  in the PFET portion  102  and the NFET portion  104 , respectively. Then, the semiconductor structure  100  undergoes a cyclic epitaxial process to grow cyclic epitaxial silicon on the NFET portion  104 . 
     Cyclic epitaxial deposition involves deposition and etch cycles. During the deposition cycle, crystalline epitaxial silicon is grown off exposed silicon from the ETSOI layer  112  because the silicon in the ETSOI layer  112  is crystalline. Amorphous silicon is deposited on non-crystalline surfaces such as the amorphous silicon in layer  154  and the nitride in spacers  134 ,  146  in the PFET portion  102  and the NFET portion  104 , respectively. During the etch cycle, the process is tuned to etch away the amorphous silicon. Since the layer  154  on top of the SiGe RSD  138  was rendered amorphous by the prior implantation that formed layer  154 , amorphous silicon is deposited on the PFET portion  102  and this amorphous silicon will get etched in the subsequent etch cycle. By controlling the etch cycles, it is possible to grow crystalline RSD  156  on the crystalline silicon in the ETSOI layer  112  in the NFET portion  104  without growing crystalline silicon on the PFET portion  102 . Masking the PFET portion  102  during the cyclic epitaxial silicon process thus become unnecessary. 
     The crystalline RSD  156  may be in-situ phosphorus doped (ISPD) silicon, ISPD silicon carbide (SiC) or undoped silicon. The semiconductor structure  100  would then undergo a rapid thermal anneal to drive in boron from the ISBD SiGe RSD  138  into PFET extension regions  158  and NFET RSD  156  into ETSOI region  160  for better/lower link-up resistance as shown in  FIG. 17 . 
     If the crystalline RSD  156  is undoped silicon, further processing is necessary to dope the RSD  156 . This further processing is illustrated in  FIGS. 13 to 16 . Referring first to  FIG. 13 , an oxide is deposited and then reactive ion etched to form spacers  162  in PFET portion  102  and spacers  164  in NFET portion  104 . Then, as shown in  FIG. 14 , a photolithographic mask  166  is patterned over the PFET portion  102  to protect the PFET portion  102  while exposing the NFET portion  104 . The RSD  156  may then be exposed to conventional ion implanting  168  to dope the RSD  156  with, for example, phosphorus or arsenic or antimony. The photolithographic mask  166  is then stripped as shown in  FIG. 15 . The semiconductor structure  100  would then undergo a rapid thermal anneal to drive in boron from the ISBD SiGe RSD  138  into PFET extension regions  158  and NFET RSD  156  into ETSOI region  160  for better/lower link-up resistance as shown in  FIG. 16 . The dopants in NFET RSD  156  essentially do not diffuse into the NFET extension regions because of the low diffusion constant of the phosphorus/arsenic/antimony dopants in NFET RSD  156 . The oxide spacers  162 ,  164  may be removed by a dilute HF etch. 
     Referring again to  FIG. 17 , a photolithographic mask  170  is patterned over the PFET portion  102  to protect the PFET portion  102  while exposing the NFET portion  104 . The NFET portion  104  may then be exposed to conventional ion implanting to ion implant  172  to form extensions  174  in NFET portion  104 . The implanted species may be phosphorus, arsenic or antimony but arsenic or antimony are preferred because they are heavier than phosphorus and may lead to much sharper doping profiles. 
     The photolithographic mask  170  is conventionally stripped as shown in  FIG. 18 . Then, a short time anneal such as a laser anneal or a flash anneal is performed on semiconductor structure  100  to activate the NFET extension implants  174  but not to diffuse them. A conventional rapid thermal anneal is greater than one second in duration. However, a laser anneal is about 1 millisecond and a flash anneal is about 10 milliseconds which are too short in time to lead to any significant diffusion of the dopants. 
     Referring now to  FIG. 19 , nitride spacers  176 ,  178  are formed by depositing nitride and then reactive ion etching to form nitride spacers  176  on PFET portion  102  and nitride spacers  178  on NFET portion  104 . 
     Conventional silicide processing then may be performed to form silicide  180  in PFET region  102  and silicide  182  in NFET region  104  as illustrated in  FIG. 20 . 
     Further conventional front end of the line, middle of the line and back end of the line processing may be performed to form finished semiconductor devices from semiconductor structure  100 . 
     It will be apparent to those skilled in the art having regard to this disclosure that other modifications of the exemplary embodiments beyond those embodiments specifically described here may be made without departing from the spirit of the invention. Accordingly, such modifications are considered within the scope of the invention as limited solely by the appended claims.