Abstract:
A method and apparatus of interfacing data between a microprocessor and a memory, in which the microprocessor accesses data temporarily stored in the memory. The microprocessor controls a read timing according to an interrupt signal so as to generate a transmission request signal, the data being read according to the transmission request signal, and the interrupt signal being generated when a predetermined amount of data is stored in the memory.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to data transmission and, more particularly, to a method and apparatus of alternate interfacing for read/write of data of one data sector according to a microprocessor and two memories. 
     2. Description of the Related Art 
     A digital video disk, a digital moving picture disk medium, is a next-generation high-quality multimedia memory device storing a digital picture of moving picture experts group 2 (MPEG2) over two hours. In order to demodulate the data to an original signal in a decoder for reproducing the data stored in the digital video disk, the data is read and temporarily stored in a memory. Here, a microprocessor for controlling the decoder reads data required for access of the memory. When the microprocessor reads all data stored in the memory, its read timing should be adjusted according to various circumstances. Furthermore, the memory must alternately read and write data without loss. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a method and apparatus of interfacing data between a microprocessor and a memory, in which a write-mode memory is converted to a read-mode memory when a predetermined amount of data is written in the write-mode memory, and two memories alternately perform write and read modes, to thereby output data to the microprocessor. 
     Another object of the present invention is to provide a method of interfacing data between a microprocessor and a memory, in which the microprocessor controls the read timing by an interrupt when a predetermined amount of data is written in the memory. 
     To accomplish the objects of the present invention, there is provided a method of interfacing data between a microprocessor and memory, in which the microprocessor accesses data temporarily stored in the memory, the microprocessor controlling a read timing according to an interrupt signal so as to generate a transmission request signal, the data being read according to the transmission request signal, the interrupt signal being generated when a predetermined amount of data is stored in the memory. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A more complete appreciation of this invention, and many of the attendant advantages thereof, will be readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings, in which like reference symbols indicate the same or similar components, wherein: 
     FIG. 1 is a system block diagram of a microprocessor and a memory according to a preferred embodiment of the present invention; and 
     FIG. 2 is a timing diagram for data interface between a microprocessor and memory according to the preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Reference will now be made in detail to the preferred embodiment of the present invention, examples of which are illustrated in the accompanying drawings. For clarity, component reference numbers are consistent between all the drawings. 
     FIG. 1 is a system block diagram of a microprocessor and a memory according to the preferred embodiment of the present invention. Referring to FIG. 1, a data bus 115 is connected to several devices for reproducing data such as a demodulator, an error correction portion and a descrambler. A data transmission controller 113 connected to the data bus 115 selects an address for the purpose of accessing data in the data bus 115 to a memory 110, and generates various control signals so as to substantially read/write data from/to the memory 110. By doing so, the memory 110 temporarily stores the data of the data bus 115 for processing data reproduced from a digital video disk under the control of the data transmission controller 113. Here, the memory 110 includes write-mode and read-mode memories which are set to a current memory selection circumstance. That is, when a first memory 111 is in the write mode, a second memory 112 is in the read mode. A microprocessor 114 accesses data to be read from the first and second memories 111 and 112 through the data transmission controller 113. 
     The data transmission controller 113 checks the amount of data when the data of the data bus 115 is stored in the write-mode memory. Here, if the amount of data becomes 2048 bytes of one data sector, the data transmission controller 113 outputs an interrupt signal to the microprocessor 114. The microprocessor 114 recognizes if it can read the data according to the interrupt signal, and outputs an activated transmission request signal to the data transmission controller 113. The data transmission controller 113 outputs write and read signals to the first and second memories 111 and 112, respectively, in order to convert the write-mode memory to the read-mode memory, or the read-mode memory to the write-mode memory according to the transmission request signal. Then, the write-mode memory is converted to the read-mode memory according to the read signal so as to output data of one data sector to the data transmission controller 113, and the read-mode memory is converted to the write-mode memory by the write signal so as to store the data of the data bus 115. 
     FIG. 2 is a timing diagram for data interface between a microprocessor and a memory according to the preferred embodiment of the present invention. Referring to FIGS. 1 and 2, the transmission request signal is output from the microprocessor 114 to the data transmission controller 113 at point P1. Then, a memory selection signal becomes a &#34;high&#34; level according to the data transmission controller 113, and the data transmission controller 113 outputs a first read signal and a second write signal to the first memory 111 and the second memory 112, respectively. By doing so, the data transmission controller 113 accesses one data sector of data stored in the first memory 111 and outputs it to the microprocessor 114 during period dl. Here, the address of the data transmitted to the microprocessor 114 is output from the microprocessor 114. 
     Furthermore, the data transmission controller 113 writes the data of the data bus 115 in the second memory 112 during the period W1. Here, the address of a region where the data is stored is output from the data transmission controller 113. The period of the signal for writing the data of data bus 115 in the second memory 112 is shorter than that of the read signal of the microprocessor 114. Thus, the writing operation is completed before the microprocessor 114 reads all of the data from the first memory 111. 
     The data transmission controller 113 confirms if the amount of data written in the second memory 112 corresponds to one data sector, and generates the interrupt signal to the microprocessor 114 when it does. The interrupt signal becomes an inactivated &#34;high&#34; level according to the rising edge where the transmission request signal is inactivated. The read signal and address are not generated during the period T1 before the transmission request signal from the microprocessor 114 is activated. This is to protect the stored data and transmit the data by 2049 bytes. During the period T1, the microprocessor 114 performs the operation required. 
     The transmission request signal becomes an activated &#34;low&#34; level by the microprocessor 114 at point P2. Then, the &#34;high&#34; level of a memory selection signal becomes a &#34;low&#34; level. By doing so, the data transmission controller 113 outputs a first write signal in order to convert the read mode of the first memory 111 to the write mode, and outputs a second read signal in order to convert the write mode of the second memory 112 to the read mode. During the period d2, the second memory 112 in the read mode outputs one data sector of data which was stored during the period d1 to the microprocessor 114 through the data transmission controller 113 under the control of the data transmission controller 113. The first memory 111 in the write mode stores the data of the data bus 115 under the control of data transmission controller 113 during the period W2. 
     When the amount of data stored in the first memory 111 corresponds to one data sector, data transmission controller 113 generates a &#34;low&#34; level of the interrupt signal, and the transmission request signal of the microprocessor 114 becomes an inactivated &#34;high&#34; level state. The microprocessor 114 controls the read timing of data during period T2, and outputs a &#34;low&#34; level of the transmission request signal at point P3. 
     An address generating portion which is applied to the first memory 111 and the second memory 112 is varied according to a state of the memory selection signal between the microprocessor 114 and the data transmission controller 113. 
     First, in the case that the memory selection signal is a &#34;high&#34; level, the data transmission controller 113 applies an address generated from the microprocessor 114 to the first memory 111. At this time, the address to the second memory 112 is generated from the data transmission controller 113 and is applied to the second memory 112. That is, a read address generated from the microprocessor 114 is applied to the first memory 111 through the data transmission controller 113, and the write address generated from the data transmission controller 113 is applied to the second memory 112. Accordingly, in this case, the microprocessor 114 corresponds to a first memory address generating portion, and the data transmission controller 113 corresponds to a second memory address generating portion. 
     Secondly, in the case that the memory selection signal is a &#34;low&#34; level, the data transmission controller 113 applies the address generated from the microprocessor 114 to the second memory 112. At this time, the address to the first memory 111 is generated from the data transmission controller 113 and is applied to the second memory 112. That is, the read address generated from the microprocessor 114 is applied to the second memory 112 through the data transmission controller 113, and the write address generated from the data transmission controller 113 is applied to the first memory 111. Accordingly, in this case, the data transmission controller 113 corresponds to the first memory address generating portion, and the microprocessor corresponds to the second memory address generating portion. 
     The relation of the memory selection signal, memory address generator and operation mode will be shown in the following table. 
     
         ______________________________________address generating        &#34;high&#34; level of memory                       &#34;low&#34; level ofportion      selection signal                       memory selectionand operation mode          signalfirst memory address        microprocessor data transmissiongenerating portion          controllerfirst memory operation        read           writemodesecond memory address        data transmission                       microprocessorgenerating portion        controllersecond memory        write          readoperation mode______________________________________ 
    
     When the transmission request signal of an inactivated &#34;high&#34; level is generated, the microprocessor 114 carries out the operation required. On the other hand, the microprocessor 114 performs only the data reading operation when the transmission request signal becomes a &#34;low&#34; level. As described above, when the amount of data stored in the write-mode memory corresponds to one data sector, the interrupt is applied to the microprocessor 114, and the microprocessor 114 controls the read timing according to the interrupt. By doing so, the data amount of one data sector can be read. Moreover, since the first and second memories 111 and 112 are alternately operated in the write mode and the read mode, the data can be stored without loss, resulting in a decrease of error. In the aforementioned embodiment of the present invention, a digital video disk is illustrated. However, the present invention can be applied to the interface for reading data of a microprocessor and a memory of another type of device. 
     Therefore, it should be understood that the present invention is not limited to the particular embodiment disclosed herein as the best mode contemplated for carrying out the present invention, but rather that the present invention is not limited to the specific embodiments described in this specification except as defined in the appended claims.