Abstract:
A procedure for establishing a scalable spanning tree over a network composed of nodes and links in which the resources for each node is independent of the size of the network. The procedure involves the selection of a set of states, a set of messages, state transition rules as well as a completion rule to thereby detect the the setting up of the spanning tree. One established, data may be distributed over the spanning tree so that coordination of data is maintained over all the nodes in the network.

Description:
FIELD OF THE INVENTION 
     This invention relates generally to implementing distributed programs and services in a network of autonomous computers and, more specifically, to a methodology for democratically synchronizing and distributing state changes as well as concomitant data from the autonomous computers. 
     COPYRIGHT NOTICE 
     A portion of the disclosure of the patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. 
     BACKGROUND OF THE INVENTION 
     A distributed program is one in which elements of the program execute simultaneously on multiple processors. Examples of distributed programs include network services such as: simple two-party telephone calls, or conference telephone calls; shared network file systems; and Local Area Network operating systems. 
     Inherent in a distributed program is the problem of providing data distribution and synchronization among processors. The current approach to distributing data in a network is via messages. These messages are packetized by the application processes and distributed using complex protocol stacks such as TCP/IP or OSI. These protocols provide reliable distribution of packets and network session management. Elements of distributed programs communicate with another program via multiple point-to-point sessions which are established through the network. 
     The difficult problem of coordinating the asynchronous processes which comprise the distributed program is left to the application. Typically, this coordination involves a set of processors in a &#34;wait&#34; state because the processors have reached an &#34;abstraction barrier&#34;, that is, a point at which certain processors cannot continue until other processors in the system reach a comparable point--at which point (in time) the processors share some data. At this point, the processors must all agree by exchanging messages that the processors all have the same values for the same set of data. The processors can proceed independently until another abstraction barrier is reached, whereupon the message interchange must again be effected. Implementing this coordination is a complex and error-prone task. For example, each processor must keep track of which other processors in the network must agree before any given abstraction barrier can be passed. This is exceedingly difficult in practice since where each process actually executes is dynamically allocated based on available total system resources. System recovery in the event of a failure of one or more elements in the network is particularly difficult. Recovery is usually triggered by timeouts which occur asynchronously in different parts of the network. In order for the system to function reliably, these timeouts must be sensitive to propagation delays in the network. 
     In a network of processors where multiple distributed applications are executing simultaneously, isolating problems resulting from inadvertent interference between applications comprises the most difficult and time consuming part of system testing and debugging. In single processor environments, this problem has been solved by memory protection schemes. With such schemes, virtual memory space is partitioned by the operating system and assigned to processes running within the system. If a process makes an illegal memory reference (i.e. to an address outside its assigned space), the event is detected by the hardware and trapped. A process of a distributed application, however, must reference objects outside its own memory space since its must be able to communicate with other parts of the system. Because there is no protection for this type of shared space, inadvertent accesses outside its own memory space go undetected, resulting in eventual unpredictable behavior of the system. 
     The underlying network itself is responsible for the actual delivery of the data packets. At its simplest level, the network may be a single wire such as an Ethernet, on which all messages are broadcast to each computer in the network. As demand grows, however, a single wire can no longer carry all the traffic, and the network becomes a set of local area networks interconnected by switching elements which direct franc between the local networks as necessary. When this happens, the operation and management of the network increases in complexity. In very large networks such as the public switched telephone network, hundreds or even thousands of these switching elements are required. In these switch networks, message routing and provision of adequate reliability in the event of hardware or software failures is an extremely complex problem. Oftentimes, such a network is described as one that does not scale gracefully. Scalability means that information required for processing is finite at each processor and is independent of the size of the network. 
     SUMMARY OF THE INVENTION 
     These deficiencies as well as other shortcomings and limitations are obviated, in accordance with the present invention, by a methodology and concomitant system arrangement so as to: (i) greatly reduce the effort required to design, program, test, and deploy distributed applications; and (ii) allow the creation of networks which can economically grow from small to very large size without appreciable increase in the complexity of routing and management. 
     Broadly, in accordance with one method aspect of the present invention, a scalable spanning tree is established for an arbitrary subset of nodes and links in a network in which the total resources at each node is independent of the size of the network. In determining this scalable spanning tree, first a set of states is selected for each node and each link in the network, the set of states being independent of the topology of the network, of the size of the network, and of the node itself. Next, a set of messages is selected to be exchanged between neighboring nodes over the links, the set of messages also being independent of the topology of the network, of the size of the network, and of the node itself. Then, state transition rules are determined for the state of each node and of each link to coordinate the sending and receiving of the messages to the neighboring nodes for setting up the spanning tree, the state transition rules also being independent of the topology of the network, of the size of the network, and of the node itself. Finally, a completion rule is determined in order that at least one node detects the formation of the spanning tree, the rule also being independent of the topology of the network, of the size of the network, and of the node itself. 
     In the network of processors operating in accordance with the methodology of the present invention, distribution, coordination, and protection are interlocked so that all data transfers are synchronized to some discrete instant of time and are protected from inadvertent reading and updating by the system. The methodology utilizes the logical construct of a &#34;harmonic clock&#34;. (A harmonic clock may also be referred to as an interface cycle. The details of an interface cycle have been disclosed in a U.S. patent application Ser. No. 08/021,096 filed Feb. 23, 1993, and having the same inventors as the present invention; this identified patent application is incorporated by reference herein). Each harmonic clock is a counter which can be used to represent an abstraction barrier. Participating processes, that is, those processes which are relevant to a particular abstraction barrier and which have the appropriate authorization key, can read the value of the harmonic clock associated with the abstraction barrier. In addition to reading the value of the harmonic clock, each processor can perform other operations on the harmonic clock; exemplary operations are &#34;inhibit&#34;, &#34;trigger&#34;, and &#34;release&#34;. When a processor inhibits a harmonic clock, it is, in effect, freezing the value of the harmonic clock. When a processor releases a harmonic clock, it is removing any inhibits which the processor had previously placed on the harmonic clock. When a processor triggers a harmonic clock, it is indicating to the network of processors that the harmonic clock should be advanced as soon as there are no other inhibits registered against the harmonic clock. In addition, when a processor triggers a harmonic clock, the processor can pass along with the trigger some arbitrary data to the network, that is, to participating processors. 
     The methodology embedded in the network of processors keeps track of the status of each harmonic clock. When any harmonic clock has had at least one trigger, the network methodology will advance the clock as soon as there are no inhibits against the harmonic clock. When this occurs, (a) the clock is incremented (advanced), and (b) the network allows each participating processor to advance in lock-step with the given harmonic clock. This advance includes the new value of the counter, that is, the harmonic clock, and all the data that any participating processors had included with their triggers. To the participating processors, this event signifies that an abstraction barrier has been passed. 
     The methodology changes the paradigm for programming distributed systems. Processors no longer need to keep track of a dynamically changing set of participating processors at any abstraction barrier. The processors simply participate in the harmonic clock for each abstraction barrier of relevance. Because all data distribution is synchronized to the advance of a harmonic clock, all processors know that all other processors have identical values of data distributed with respect to a particular harmonic clock along with the same value of the harmonic clock. This synchronization permits distributed programs to proceed as a set of logical steps on multiple processors, only proceeding to the next step after agreement by those processors having a need to coordinate. In the event of failures, recovery is initiated with respect to the value of the harmonic clock, rather than with respect to the conventional technique of referencing physical timers, thereby insuring that all participating processors are working with identical data and state information. Because data is never discarded by the network, conventional protocol software is not required. Data is simply transferred as logical variables, with read and update authorizations of those variables being enforced by the methodology. At the applications interface, the entire network appears as memory, and coordinated data transfers become nothing more than simple memory reads and writes. 
     The methodology specifies a network implementation of harmonic clocks which guarantees that the value of the counter associated with each harmonic clock does not vary by more than one increment at all places in the network at any instant of time. In addition, the methodology ensures an efficient, fully distributed procedure for multicasting harmonic clock status and data through the network. 
     One important feature of this methodology is a unique flow control mechanism based on harmonic clocks which manages data flow through the network having the following properties: (1) flow control is applied on a virtual circuit basis; and (2) data is never discarded by the network because the links of the network, that is, the interconnection paths between processors geographically dispersed in the network, are used as buffers in which data is circulating until the data can be delivered. 
     Another significant feature is that the network of harmonic clocks can scale--increase in size--very gracefully because it has the following properties: 
     (a) the number of messages per virtual circuit per node does not increase as the number of nodes in the network grows; 
     (b) the amount of buffer space needed at any node is independent of both the number of virtual circuits and the number of nodes, that is, the number of processors in the network; 
     (c) multiple links between the same nodes are supported, with no change to the network control mechanism; 
     (d) each node is aware of its neighbors (those nodes with which a node shares a link). There is no single place (or set of places) where the entire network topology must be known to route connections or otherwise manage the network; and 
     (e) the entire network is self timed implying that the logical consistency of any distributed application is totally independent of it performance. 
    
    
     The organization and operation of this invention will be understood from a consideration of the detailed description of the illustrative embodiment, which follows, when taken in conjunction with the accompanying drawing. 
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 illustrates a three-node, three-link network arranged in accordance with the present invention; 
     FIG. 2 illustrates a two-node, one-link network with associated entities arranged in accordance with the present invention; 
     FIG. 3 depicts the node, link, message, and clock states for a complete synchronized agreement cycle for the first node in a two-node, one-link network; 
     FIG. 4 depicts the node, link, message, and clock states for a complete synchronized agreement cycle for the second node in a two-node, one-link network; 
     FIG. 5 depicts, in flow diagram form, the methodology for handling messages; 
     FIGS. 6-8 depict (self messages); 
     FIGS. 9-10 depict (clock messages); 
     FIGS. 11-16 depict (system messages); 
     FIGS. 17-27 depict the state of the nodes and the link for the two-node, one-link example at various stages due to self messages, clock messages, and system messages; 
     FIGS. 28-48 depict the state of the nodes and the links for the three-node, fully-connected example at various stages due to self messages, clock messages, and system messages; and 
     FIG. 49 shows the distribution of backward propagating data and forward propagating data relative to the occurrences of the system messages. 
    
    
     DETAILED DESCRIPTION 
     To place in perspective the detailed description of the present invention, it is instructive to first gain a basic understanding of the network-of-computers environment in which the present invention operates. This approach has the advantage of introducing notation and terminology which will aid in elucidating the various detailed aspects of the present invention. Thus, the first part of the description focuses on a high-level discussion of the network environment pertinent to the inventive subject matter. After this, the second part of the description focuses on illustrative examples which further elucidate aspects of this invention which will aid in understanding the broadest aspects of the present invention. Next, the third part of the description covers the most general exposition of the present invention by way of presentation of pseudo-code for the network transition messages. Finally, the fourth part of the description provides programming code in standard VHDL language for implementing the general exposition. 
     I. Overview 
     With reference to FIG. 1, there is shown network 100 in accordance with the present invention. Network 100 is generally composed of N &#34;nodes&#34;; for illustrative purposes, and without loss of generality, the case of N=3 is shown in FIG. 1, that is, network 100 comprises nodes 101, 102, 103. Node identifiers such as &#34;101&#34; are designated as physical descriptors since such descriptors identify the nodes in a topology that remains fixed. Nodes may also be referred to by logical descriptors. For instance, node 101 has logical descriptor &#34;Node 1&#34; shown internal to node 101, node 102 has descriptor Node 2, and so forth, and the numerical part of the logical descriptor (e.g., &#34;1&#34; in Node 1) refers to the &#34;rank&#34; of the node--with the largest numerical value identitying the highest rank. The rank of a node can change dynamically, as will be described below, whereas the physical identifier of a node (e.g., node 101) is fixed. Initially, the rank of each node corresponds to its physical descriptor in the network hierarchy. When reference is made to Node J or NJ, J is the physical descriptor. 
     The nodes of network 100 are interconnected with &#34;links&#34;, such as link 111 connecting nodes 101 and 102, link 112 coupling nodes 101 and 103, and link 113 joining nodes 102 and 103. Links are bidirectional. Also, more than one link may join node pairs; for instance, link 114, shown as dashed, would also interconnect nodes 101 and 102. Network 100 is assumed to be &#34;connected&#34;, that is, there is a path comprising one or more links from any given node to any other node. Links route the &#34;messages&#34; generated by the nodes; messages are discussed in more detail shortly. The &#34;neighborhood&#34; of a node I is the set of other nodes J for which links exist. For example, the neighborhood of node 101 is the set composed of nodes 102 and 103. Either node 102 or node 103 is referred to as a &#34;neighbor&#34; of node 101. 
     Each node is always in one of four states, namely: CHARGED, FORCED, SNAPPED, DISCHARGED. The meaning of these terms will be elucidated as the description proceeds. 
     Each end of each link may have associated with it a two-part link identifier; the first part of the link identifier is called the &#34;role&#34;; the role is one of the following: captain, guard, friend. The second part of the link identifier is called the &#34;mode&#34;; the mode is one of the following: charge, force, snap, discharge, resign. A link identifier has the form role.mode; examples of link identifiers include charge.guard; captain.snap; and guard.force. Not all combinations are possible, as will be evidenced as the discussion unfolds. Also, the meaning of the link identifier in the role.mode form will be elucidated as the description proceeds. 
     Messages are propagated over links. Each message is composed of a &#34;field&#34; and &#34;rank&#34;. Messages are either transmitted by a node or received by a node. Since links are bilateral, messages can be simultaneously transmitted and received by a given node over each link. For either a transmitted or received message, the field identifiers are the same as the mode identifiers, namely, the field is one of the following: charge, force, snap, discharge, resign. For a message being assembled for transmission, the rank is the logical rank of the node at the instant the message is assembled. On the other hand, for a received message, the rank is already embedded in the message for identification. 
     A harmonic clock C provides a way to coordinate programs executing within the nodes, processors, or other entities associated with the nodes of network 100 (programs, processors, or entities are hereinafter referred to as &#34;entities&#34; as a shorthand notation) using a logical version of a synchronized agreement &#34;cycle&#34;. A cycle is broadly defined at this point as the progression from a initial stage to one or more intermediate stages with eventual return to the initial stage; refinements to this definition will be effected as the discussion proceeds. A harmonic clock allows these entities to agree on the definition of the cycle in a distributed manner. When the entities are under control of the operating principles to be elucidated shortly, it is guaranteed that any cycle will not be completed until all entities have agreed to allow the cycle to complete. There may be many harmonic clocks simultaneously and independently active. Each clock has a count designated P. The upper limit on P is typically finite, so the count of any clock C is interpreted modulo Q, where Q is the upper limit. 
     At the initiation of each clock C, it is assumed that a network, such as exemplified by network 100, has been configured to distribute the given clock C to a set of nodes, such as nodes 101-103. This network is denoted by C --  Net. The set of nodes of C --  Net is denoted by C --  N. The set of links in C --  Net that impinge on node I is denoted by C --  Nd(I). A clock C has associated with it a three-part identifier of the form &#34;clock --  state1,clock --  state2,count&#34;, wherein clock --  state1 is either relaxed or triggered, clock --  state2 is either inhibited or released, and the count is the actual numerical value (P modulo Q) registered by clock C. 
     
         __________________________________________________________________________Additional Terminology and Notation__________________________________________________________________________1.)  C.*      Messages &#34;received&#34; by a node regarding a clock C are      denoted by prefixing the message with C.; for example,      &lt;C.rank&gt; means the rank associated with the clock C      embedded in a message received by a given node.2).  L        The link over which a node receives a message.3).  CONTINUE The starting point in the message handling process.4).  message=[force,      &lt;C.rank&gt;] Means &#34;message.#[force.&lt;C.rank&gt;&#34;__________________________________________________________________________ 
    
     Data Structures 
     Data structures are described as nested sets. An enumerated set is described by the list of its elements; for example: {a,b,c} is the set consisting of a, b, and c. A data structure x represented by x.{a,b,c} can have values a, b, or c. When a data structure has several components, a comma is used to separate elements; for example: [x,y] has two components. A nested structure is denoted using the nesting of [] and {}; for example: [x.{a,b,c},y.{d,e}] consists of two components x and y where x can take on the values a, b, or c and y can have values d or e. The modification of data structures by events are described by indicating the components that change. All other components are assumed to have the previous value. For example: set x.[3,4]=a only changes the values of x.3 and x.4 to a. Substitution of a label with the value of another is indicated by &lt;&gt;; for example: x.&lt;y&gt; denotes x.z if y=z. An * at a place in a data structure denotes all possible substitutions; for example: x.*.a denotes all elements of the array x that have the value a. Specific instances of a data structure that may take on several values are represented by denoting the values of components using =, or by showing values in place. For example, the data structure x.[y.{a,b,c},z.{d,e}] can have value x.[y=a,z=d] or, equivalently, x.[#a,#d] or x.#[a,d]. 
     In terms of the data structure definitions, the form of a self message may be summarized as: 
     
         self.[{forced?,snapped?,discharged?}] 
    
     In terms of the data structure definitions, the form of a system message may be summarized as: 
     
         message.[{force,snap,resign,discharge,charge}, &lt;rank&gt;]. 
    
     In the data structure notation defined above, the clock message for each node may be summarized as follows: 
     
         clock.[{relaxed,triggered},{inhibited,released}, &lt;P mod Q&gt;]. 
    
     II. Illustrative Examples 
     A. Two Node, one Link case 
     With reference to FIG. 2, two nodes 201 and 202 (also designated nodes N1 and N2, respectively) are shown interconnected by single, bidirectional link 203. For purposes of discussing the illustrative example, nodes 201 and 202 both have the same status upon initialization, namely, each node state is CHARGED, and the rank of each node is its physical node identifier; for example, node 201 has rank=1, and node 202 has rank=2. The initial role and mode of link 203 are the same for both ends, namely, the role=guard and the mode=charge. Each node has a computing entity associated with the node, and in FIG. 2, entity 205 is shown as associated with node 201 wherein entity 206 is associated with node 202. Each entity may be, for example, an external computer system operating in cooperation with its associated node; as another example, each entity may be a microprocessor embedded in the associated node. In any case, each entity is presumed to operate under control of an autonomous clock, such as clock 207 associated with entity 205, or clock 208 associated with entity 206. Each clock is assumed to have initial &#34;clock --  state1&#34; and &#34;clock --  state2&#34; states of relaxed and inhibited, respectively. In addition, the initial &#34;count&#34; is assumed to be 0, that is, P=0. 
     By way of summarizing this information, the table of FIG. 3 depicts a time sequence in the vertical dimension of the unfolding of: (a) the states and rank of node 201 (&#34;Node 1&#34; in the top line of the table; which is subdivided into &#34;State&#34; and &#34;R&#34;); (b) the role.mode of the end of link 203 terminating on node 201 (&#34;Link&#34; in the top line of the table, which is subdivided into &#34;Role&#34; and &#34;Mode&#34;); and (c) the states and the phase of clock 207 (&#34;Clock&#34; in the top line of the table, which is subdivided into &#34;CS1&#34;, &#34;CS2&#34;, and &#34;P&#34;). The top line of the table of FIG. 3 also includes: (i) a column designated &#34;Time&#34;, which, on a normalized basis, is incremented in single units; (ii) a column designated &#34;MSG-O&#34; for &#34;message-out&#34;, which is subdivided into &#34;FO&#34; and &#34;R&#34;, meaning &#34;field-out&#34; and &#34;rank&#34;; and (iii) &#34;Local Msg&#34; for &#34;local message&#34;, which is the message (trigger or release) originated by the local entity 205. The row corresponding to &#34;Time&#34;=0 summarizes the initialization information as presented above. Moreover, as a data point to continue the discussion, it is presumed that a trigger message has been generated by local entity 205 at &#34;Time&#34;=0. 
     In the same manner just described for node 201, there is a corresponding table which summarizes information about node 202, link 203 terminating on node 202, entity 206, and clock 208, and this table is shown in FIG. 4 with the same layout as the table of FIG. 3 
     In order to clearly and concisely discuss the node states, role.mode of the link at each end, clock states, and so forth for a complete synchronized agreement cycle between nodes 201 and 202, it is most expeditious to introduce a set of flow diagrams, namely the diagrams shown in FIGS. 5-17, which elucidate the transitions occurring during the synchronized agreement cycle. Reference to the relevant flow diagram will be made when required. Each flow diagram in the set FIGS. 6-17 has a similar layout in that the first block represents a &#34;STATUS&#34; which must be conformed to in order to invoke the processing depicted by the remainder of the flow diagram. For example, FIG. 11 shows that the STATUS of the (a)node, (b)link, and (c) incoming message must be, respectively, CHARGED, guard.charge, and #[force, &lt;C.rank&gt;]. FIG. 5 is special in that it depicts the message handling technique for self messages, clock messages, and system messages, as discussed in detail below. As depicted in FIG. 5, self messages are messages directed to the node giving rise to the message, and self messages as handled as illustrated in FIGS. 6, 7, and 8. Clock messages are the messages produced by each clock to establish a synchronized cycle, and clock messages are handled as illustrated in FIGS. 9 and 10. System messages are transmitted over links from originating nodes, and system messages are handled as illustrated in FIGS. 11-16. 
     The objective of selecting: these states for the nodes and links; selecting the self, clock, and system messages (so-called set-up messages); and rules for transitioning among the states, is to establish a scalable spanning tree in such a way that at least one node detects the formation of the spanning tree as the states, messages, and rules unfold. In this disclosure, the establishment of a spanning tree can be broadly stated to mean the dynamic determination of a subset of the topology of the network that is loop-free (a tree) and yet has sufficient connectivity so that, where possible, there is a path between every pair of nodes (the tree then becomes a spanning tree). 
     The state of the nodes and link at the commencement of processing is as summarized in FIG. 17. The left-hand node (node 201) has rank 1 (&#34;1&#34; in upper part of the left-hand circle representing the node), the node is CHARGED (C in the left-hand circle representing the node), and the link (link 203) is in the guard.charge (g.c above the line representing the link) role.mode at node 201. (In the following FIGS. 18-27, the reference numerals for nodes 201 and 202 as well as link 203 are not shown on the figures for the sake of clarity.) Also, the clock associated with node 201 is relaxed,inhibited (RX,IN under CL in the left-most portion of FIG. 17). Similarly, the right-had node (node 202) has rank 2, is CHARGED (C), and the link is in the role.mode of guard.charge at node 202. Also, the clock of node 202 is relaxed,inhibited. Finally, it is presumed that link 203 has a delay of 5 units (as shown by the &#34;5&#34; in parenthesis under the line representing link 203). 
     For node 201, the first flow diagram of interest is shown by FIG. 9, which pertains to a local message of trigger (recall a trigger occurs at &#34;Time&#34;=0 from the table of FIG. 3) whenever the STATUS of the clock is both relaxed and inhibited. As depicted by block 902, the clock is first set so that clock has clock --  state1 and clock --  state2 of triggered and inhibited, respectively. Then decision block 903 is entered to see if node 201 is CHARGED, and since it is for the example (refer to the TIME=0 line of FIG. 3), the processing of block 905 is next invoked. An outgoing message of having a &#34;field-out&#34; (FO) of force, and a &#34;rank&#34; (R) of 1 (f,1) is sent onto single link 203 at TIME=1, that is, the next processing interval. Then, all links associated with node 201 are set to role.mode of guard.force (g.f) by block 906. Next, as per block 907, node 201 is set to FORCED (F), and the rank is maintained as &#34;1&#34; by block 908. In addition, a snapped? self message is sent to node 201. The state after a trigger by the clock associated with node 201 is summarized in FIG. 18. 
     It is assumed that at TIME=1, the clock associated with node 202 also sends a trigger signal. The flow diagram of FIG. 9 also describes the actions taken at node 202 as the result of the change in node 202&#39;s clock. The actions are summarized by the depiction of FIG. 19. The message shown as emanating from the left-hand node (dotted f,1) is the message emitted by node 201 which is still propagating over the link, since the link is presumed to have a delay of 5 units. 
     The next activity that occurs results from the arrival of the f,1 message from node 201 at node 202, as depicted by the flow diagram of FIG. 12. The status of node 202 is summarized by block 1201, that is, node 202 is FORCED, the link is in guard.force, and the message arriving is f,1. Decision block 1202 is entered to see if the local rank (rank) is less than the incoming rank (C.rank). In this case the local rank (2) is greater than the incoming rank (1), so decision block 1207 is entered next, followed immediately by processing block 1208 which returns a force message with the local rank of &#34;2&#34; (f,2) back onto the link. 
     Next, the original f,2 message sent by node 202 arrives at node 201; the flow diagram of FIG. 12 also controls this processing event. Now, since the incoming rank (C.rank=2) is greater than the local rank (rank=1), processing by decision block 1202 results in the invoking of processing block 1203 which, in this case, is a null event since there is no link yet designated a captain link. If there was a captain link, then as per block 1204, this link would be set to guard.force. Next, as indicated by processing block 1205, the incoming link is set to captain.force. Finally, the rank of node 201 is set to the incoming rank. The results of this sequence of events at both nodes 201 and 202 is depicted by the status diagram of FIG. 20. In addition, FIG. 21 summarizes the node and link states after all messages have completed their traversal of the links, and a quiescent state is achieved to await the next activity. 
     Moreover, the timing diagram of FIG. 3 summarizes the occurrence of these events at node 201. In particular, at TIME=7, it is seen that the incoming f,2 message arrives from node 202, which results in a change in the role.mode to captain.force and the rank to &#34;2&#34;. TIME=12 shows the arrival of the second incoming f,2 message from node 202 (which was actually originated by node 201), but this has a null effect due to the prior arrival of the same message. (Formally, this effect may be expressed as a CONTINUE operation, which means that, as per the CONTINUE block 510 of FIG. 5, messages are processed in top-down fashion by blocks 520-521 if there is a self message, or by blocks 530-531 is there is a clock message, or by blocks 540-541 is there is a system message. Moreover, if there is no flow diagram in the set of FIGS. 6-17 that covers a particular STATUS, this is to be interpreted as invoking a CONTINUE operation.) In addition, the timing diagram of FIG. 4 summarizes the occurrence of these events at node 202. In particular, at TIME=6, the f,1 message arrives from node 201, and in the next time interval, the message is converted to a f,2 message and is returned to node 201. 
     The next processing event occurs at TIME=14 whereupon the clock of node 201 effects a release, that is, the clock changes to the trigger,release (Trg,Rel) state, which is reflected at the next unit of time, namely, TIME=15 in FIG. 3. The flow diagram which summarizes the initial activity resulting from the release of the clock is shown in FIG. 10. With reference to FIG. 10, blocks 1001 and 1002 show the original status and the changed status as a result of the release. Decision block 1003 is entered next: since node 201 is FORCED, and the node has no guard links (therefore there are no links that must equal the mode of snap), there is a branch to block 1004. Processing by block 1004 results in setting node 201 to SNAPPED, and then decision block 1005 is entered--with the question to be resolved is the role of link 203 a captain,? Since link 203 is a captain, then processing block 1008 is invoked, which results in a message of snap,2 being sent onto link 203. As blocks 1009 and 1010 depict, the following actions also occur: the link is set to mode of snap, and a CONTINUE operation is invoked. The state of the nodes and link after the release of the clock associated with node 201 is shown in FIG. 22. 
     The next event that occurs in marked by the clock associated with node 202 also causing a release, that is, a clock condition of trigger,release occurring at TIME=16. To determine the unfolding of events, reference is first made to FIG. 10. Processing by blocks 1001 and 1002 leads to decision block 1003. Since node 202 is FORCED, but the link is not in the role.mode of guard.snap, a CONTINUE operation is completed via block 1011. The state of the nodes and link at this point in time is shown in FIG. 23. The dotted s,2 indicates that the snap message emitted at TIME=15 from node 201 is still propagating over the link. 
     The next event occurs when the s,2 message arrives at node 202 at TIME=21. Since node 202 is FORCED, the link is guard.force, and the incoming message is snap,2, then the flow diagram of FIG. 14 is invoked. With reference to FIG. 14, the first processing block entered is block 1402, whereupon the link is set to guard.snap (g.s). Since all guards are have the snap role, processing by decision block 1403 leads to decision block 1405. Since the clock associated with node 202 has released, processing block 1407 sets node 202 to SNAPPED. Then, decision block 1408 is entered to determine if the node has a captain. Since node 202 does not have a captain, as per blocks 1412 and 1413, a self message of snapped? is sent to node 202 and a CONTINUE operation is effected. The state of the nodes and the link just after the self message are summarized in FIG. 24. 
     As a result of the snapped self message, processing by the flow diagram of FIG. 7 is invoked next. With reference to FIG. 7, as per block 702, a discharge,2 (d,2) message is emitted on the link by node 202. Also, the next four processing blocks (703-706) lead to: the guard links are set to a mode of discharged; the node is set to DISCHARGED; a self message of discharged? is sent; and a CONTINUE operation is completed. The state of the nodes and the link just after this last self message are summarized in FIG. 25. 
     As a result of the discharged? self message, processing by the flow diagram of FIG. 8 is invoked next. With reference to FIG. 8, processing by block 802 leads to the CONTINUE operation of block 803 since node 202 has a guard link. 
     The next processing event occurs at TIME=27 when the d,2 link message arrives at node 201. The flow diagram of FIG. 15 is then invoked. With reference to FIG. 15, since the status of node 201 is SNAPPED, the link is captain.snap (c.s), and the message is discharge,2, processing by the remaining blocks 1502-1506 leads to: setting the link to captain.discharge (note block 1502 is a null operation since there are no guard links); setting node 201 to DISCHARGED; and sending a discharged? self message to node 201. The state of the nodes and link at this point is shown in FIG. 26. 
     As a result of the discharged? self message, processing by the flow diagram of FIG. 8 is invoked next. With reference again to FIG. 8, processing by block 802 leads to the sequence of processing blocks 804-808 since node 201 does not have any guards. As per block 804, a charge,2 (c,2) message is sent over the link, followed by changing the link to guard.charge (block 805), setting the node to CHARGED (block 806) and the rank back to &#34;1&#34;, and incrementing the phase of the clock by one (P becomes P+1) (whereupon processing by node 201 may commence--including a step of re-setting the clock to released,inhibited). The state of the nodes and the link after processing by the flow of FIG. 8 is shown in FIG. 27. 
     Finally, at TIME=35, the c,2 message arrives at node 202. The flow diagram of FIG. 16 is then invoked. With reference to FIG. 16, decision block 1602 leads to processing by blocks 1604-1608 (since there is only one link in guard.discharge, that is, &#34;all links=guard.charge except the incoming link&#34;). As a result of processing by blocks 1604-1608, node 202 is returned to CHARGED, the rank remains rank=2, link 203 is set to guard.charge, and the clock is advanced (P to P+1). It is presumed that the processing by node 202 leads to re-setting of the clock to relaxed,inhibited, followed by a CONTINUE operation. After all processing is complete, the state of the nodes and link is, once again, as depicted in FIG. 17. 
     The timing diagrams of FIGS. 3 and 4 summarize the states of the nodes and link as effected by processing of self messages, clock messages, and system messages. 
     B. Fully-Connected Three Node Case 
     With reference to FIG. 28, an exemplary fully-connected network having three nodes 101-103 and three interconnecting links 111-113 is depicted (FIG. 28 is commensurate with FIG. 1 and is labeled accordingly; for FIGS. 28-48, the reference numerals for the nodes and links are omitted for the sake of clarity). For purposes of this illustrative example, nodes 101-103 each have the same status upon initialization, namely, each node state is CHARGED, and the rank of each node is its physical node identifier; thus, node 101 has rank=1, node 102 has rank=2, and node 103 has rank=3. The initial role and mode of links 111-113 are guard.charge, respectively. As in the previous two-node example, each node has a computing entity associated with the node (in this case the entities are not shown since their relation to each node and their operation are completely analogous to the entities 205 and 206). Accordingly, each entity is presumed to have a clock (not shown), and each clock is assumed to have an initial state described by relaxed.inhibited. In addition, the initial count of each clock is P. 
     In order to clarify and concisely discuss the node states, link states, and clock states, it is again most expeditious to present a series of state diagrams which are obtained by tracing the state transitions with the guidance of the flow diagrams in FIGS. 5-17. The state of the nodes, links, and clocks at the commencement of processing is as summarized in FIG. 28. It is to be noted that the delays of links 111, 112, and 113 are, respectively, 1 unit, 10 units, and 100 units (shown in parenthesis next to each link). These delays are selected so that signals propagating on the different links are essentially non-overlapping, which helps clarify the discussion. 
     At TIME=0, with reference to FIG. 29, it is presumed for this example that each clock initiates a trigger message. The first flow diagram of interest is shown in FIG. 9, which pertains to a local clock message of trigger. As depicted by block 902, each clock is then set to the triggered,inhibited state. Then decision block 903 is entered to see if the associated node is CHARGED, and since each node is in the CHARGED state, then processing of block 905 is invoked. An outgoing message of force.rank is emitted for each node; accordingly, node 101 emits a f,1 message over both links 111 and 112; node 102 emits a f,2 message over both links 111 and 113; and node 103 emits a f,3 message over both links 112 and 113. Then, each end of each link is set to guard.force, and each node is set to FORCED and each node maintains its original rank, as per blocks 906-908. In addition, a forced? self message is circulated to each node--which ultimately effects a CONTINUE operation. The state after the trigger events at TIME=0 at each node is summarized in FIG. 29. 
     The next state of interest is shown in FIG. 30, wherein the f,2 message has arrived at node 101 and the f,1 message has arrived concurrently at node 102. The flow diagram of FIG. 12 depicts the activity that occurs in each node. First, for node 101, the incoming rank (2) is greater than the local rank (1), so processing by blocks 1203-1206 and 1214 is entered via decision block 1202. Blocks 1203-1204 result in essentially null activities since there are no captain links as yet. Block 1205 leads to setting the incoming link 111 to captain.force, and the local rank is set so that rank=2 via block 1206. Second, for node 102, the incoming rank (1) is less than the local rank (2), so processing by blocks 1208 and 1215 is effected after pass-through by decision blocks 1202 and 1207. Block 1208 leads to returning a f,2 message back along link 111 from node 102. The state of the network at this point in time is shown in FIG. 30. The dotted messages (f,1, f,2, and f,3) indicate messages still propagating in the network as a result of the trigger by each clock at TIME=0. 
     The next state of interest occurs when the second f,2 message reaches node 101. Now, since the role.mode of link 111 at node 101 is captain.force, and there is no corresponding flow diagram in the set of FIGS. 6-17, by definition the only activity is one of CONTINUE. The state of the network at this point in time, namely, TIME=4, is shown in FIG. 31. Now, there are no messages traversing link 111, but the earlier messages from node 101 to node 103, and vice versa, are still traversing link 112, and similarly for link 113 between nodes 102 and 103. 
     The next state of interest occurs when the f,3 message reaches node 101 and the f,1 message simultaneously reaches node 103 at TIME=11. First, the f,3 message causes the flow depicted by FIG. 12 to be invoked. Since the incoming rank (3) is greater than the local rank (2), processing by blocks 1203-1206 and 1214 leads to: sending a f,3 message along the captain link 111; changing the captain link 111 to guard.force; setting link 112 to captain.force, and setting the local rank to rank=3. Second, the arrival of the f,1 message at node 103 having an incoming rank=1 results in, as per blocks 1202, 1207, 1208, and 1215, a returning of a f,3 message to node 101 on link 111. The state of the network after the aforementioned activities is shown in FIG. 32. 
     The next state of interest occurs at TIME=13, when the f,3 message traveling from node 101 to node 102 arrives at node 102. Since the rank of the incoming message (3) is greater than the local rank (2), processing by blocks 1203-1206 and 1214 is completed, which leads to changing link 111 to captain.force at node 102, and changing the rank of node 102 to rank=3. The state of the network after these activities is shown in FIG. 33. 
     The next state of interest occurs at at TIME=22, when the f,3 message traveling from node 103 to node 101 arrives at node 101. The status of node 101 results in a CONTINUE operation. The state of the network after these activities is shown in FIG. 34. Now, both links 111 and 112 are quiescent in the sense that no messages are propagating over these links; the only messages still propagating in the network are along link 113. 
     The next state of interest occurs at TIME=101, when the f,2 message arrives at node 103 and the f,3 message arrives concurrently at node 102. First, since the rank of node 102 has been modified by an earlier arriving message to attain rank=3, and node 102 is FORCED and link 113 at node 102 is guard.force, the flow depicted by FIG. 12 is effected. The result of processing by decision blocks 1202 and 1207 ultimately leads to decision block 1209, whereupon there is a branch to the sequence of blocks 1210-1211-1213. Block 1210 causes a resign,3 (r,3) message to be sent back along link 113, and block 1211 causes the link to be set to friend.resign (f.r) (this role.mode is an indication for link 113 to, in effect, be temporarily removed for the remainder of the synchronization cycle). Second, for message f,2 arriving at node 103, since the local rank (3) is greater than the incoming rank (2), the flow of FIG. 12 indicates that a f,3 message is returned over link 113 (as per processing blocks 1202, 1207, 1208, and 1215). The state of the network after the processing at nodes 102 and 103 is as shown in FIG. 35. 
     The next state of interest occurs at TIME=202, when the r,3 message arrives at node 103 and the f,3 messages arrives at node 102. First, the f,3 message at node 102 is merely a repeat of the same message that arrived at TIME=101, so a CONTINUE operation occurs. Second, the r,3 message arriving at node 103 is controlled by the flow diagram of FIG. 13. With reference to FIG. 13, it is seen that link 113 is set to friend.resign by processing block 1302, followed by a CONTINUE operation. The state of the network after the processing at nodes 102 and 103 is as shown in FIG. 36. Now, all messages initiated at TIME=0 have traversed the network and a rooted tree has been formed. In particular, node 103 is the root of the tree (the so-called &#34;supercaptain&#34;), that is, node 103 is not connected to another node through a captain link. On the other hand, node 101 has captain link 111 which points to or connects to its captain node 103. In turn, node 102 has a captain ink 112 which points to or connects to its captain node 101. As alluded to above, operation of link 113 is considered as temporarily suspended for the remainder of the synchronization cycle. 
     Now, with reference to FIG. 37, it is presumed that the clock associated with node 101 causes a release signal at TIME=500. To see the effect of this clock signal, reference is now made to FIG. 10. First, processing by block 1002 causes this clock to enter the triggered,released state, and the processing by decision block 1003 leads to a CONTINUE operation since node 101&#39;s only link is not in the mode of snap. 
     Next, it is presumed that the clock associated with node 102 initiates a release signal at TIME=515. Again the flow set forth in FIG. 10 is traced. Now, since node 102 does not have any guard links (only a captain link), and node 102 is FORCED, then the result decision block 1003 leads to setting node 102 to SNAPPED. Moreover, since node 102 has a captain, the decision by block 1005 leads to processing by the sequence of blocks 1008-1010. First, a snapped,3 message is sent over link 111, the captain link, as per block 1008. Then, this captain link is set to captain.snap (c.s), and a CONTINUE operation is effected. The state of the network at this point is time is summarized by FIG. 38. 
     The next state of interest occurs when the s,3 message arrives at node 101 at TIME=517. Since node 101 is FORCED and its link is guard.force, the flow diagram of FIG. 14 is followed. Initially, the link is set to guard.snap (g.s) by processing block 1402. Then decision block 1403 yields a Yes (Y) response since the (only) link is guard.snap. Accordingly, decision block 1404 is entered, and since the clock associated with node 101 has already released, processing by block 1407 is invoked next, whereupon node 101 is set to SNAPPED. Next, as a result of decision block 1408 yielding a Y (Yes), processing blocks 1409-1411 are completed: first, a snap,3 (s,3) message is sent over link 112, then the captain link is set to captain.snap (c.s), and a CONTINUE operation is completed. The state of the network after the above activities is shown in FIG. 39. 
     The next state of interest (TIME=528) occurs when the s,3 message arrives at node 103. Because of the existing status of node 103 when this message arrives, the flow diagram of FIG. 14 is carried out. Thus, link 112 is set to guard.snap (block 1402), and decision block 1405 is entered via decision block 1404 since the only link has a role of snap. However, since the clock associated with node 103 is presumed not to have initiated a release as yet, only the CONTINUE operation of processing block 1406 is effected. The state of the network after these actions is shown in FIG. 40. 
     The next state of interest occurs at TIME=575 when the clock associated with node 102 emits a release. Processing by the flow diagram of FIG. 10 is then completed. The clock is set to *,released by block 1002, and decision block 1003 is entered to determined the next step. Since node 103 is FORCED, and the only guard link is set to snap, processing by block 1004 is then invoked, whereupon node 103 is set to SNAPPED. Since node 103 has no captain, a snapped self message is sent (block 1006) and then a CONTINUE operation is called. The state of the network after these actions is shown in FIG. 41. 
     The snapped? self message at node 103 causes the flow diagram of FIG. 7 to be followed. The processing by blocks 701-706 leads to: a discharge,3 (d,3) message being sent over guard link 112, link 112 is then set to guard.discharge (g.d), node 103 is set to DISCHARGED, and a self message of discharged? is returned to node 103. The state of the network after these actions is shown in FIG. 42. 
     As a result of the discharged? self message at node 103, FIG. 8 is now referenced. Since node 103 has a guard link, processing by block 802 leads to a CONTINUE operation, as per block 803. 
     The next state of interest occurs when the d,3 message reaches node 101. Because of the status of node 101, the processing blocks 1502-1506 of FIG. 15 are then invoked. The incoming d,3 message leads to sending the same d,3 message over link 111 (block 1502), to setting link 112 to captain.discharge (c.d) (block 1503), to setting node 101 to DISCHARGED (block 1504), and to sending a self message of discharged? to node 101 (block 1505). The state the network after the occurrence of these activities is shown in FIG. 43. 
     Because of the self message of discharged at node 101, it is again necessary to trace the flow through FIG. 8. Since node 101 has a guard, processing by block 802 leads to block 803, wherein a CONTINUE operation is invoked. 
     The next state of interest occurs when the d,3 message arrives at node 102. The flow of FIG. 15 is now pertinent. Again, processing by blocks 1502-1506 leads to the following sequence of activities: since there are no guard links, block 1502 is a null event; link 111 is set to captain.discharge; node 102 is set to DISCHARGED; and a self message of discharged? is circulated to node 102. The state of the network after processing by the blocks of FIG. 15 is shown in FIG. 44. 
     Because of the self message of discharged? returned to node 102, the flow of FIG. 8 must be followed. Now, since node 102 does not have a captain, blocks 804-808 are traversed. Accordingly, a charge,3 (c,3) message is sent over link 111; all links are set to guard.charge, including link 113 which has remained in friend.resign since it was placed in that role.mode; node 102 is set to CHARGED and the rank of node 102 is reset to its physical descriptor; and processing by node 102 is now allowed whereupon the active phase is incremented by one (P goes to P+1). The state of the network after this processing is shown in FIG. 45. 
     The next state of interest occurs when the c,3 message arrives at node 101. Because of the status of node 101, the flow diagram of FIG. 16 is invoked. The results of decision block 1602 leads to processing by blocks 1604-1608 since the only existing link is the incoming link (L), so all links except L are in guard.charge (block 1602). The c,3 message is forwarded along link 112, node 101 is set to CHARGED and the original rank=1 of node 101 is restored. In addition, all links associated with node 101 are set to guard.charge. Node 101 may commence active processing, and the phase P in node 101 is advanced by one (P goes to P+1). Finally, the CONTINUE operation is invoked. The state of the network after these events is shown in FIG. 46. 
     The next state of interest occurs when the c,3 message arrives at node 103. A traversal of the processing shown in FIG. 16 leads to: setting node 103 to CHARGED (the rank is already the physical descriptor); setting link 112 to guard.charge; and allowing node 103 to process data with an active phase of P+1. The state of the network after this processing is shown in FIG. 47. Also shown in FIG. 47 are possible states of each clock associated with each node at this point in time. Recall, that all clocks associated with the nodes have initiated a release. 
     Finally, FIG. 48 shows the state of the network after all messages have been processed, the nodes have initiated internal processing, and the clocks have advanced. It is noted that this network state is essentially that shown in FIG. 28, except that the clock phase is now incremented by one. ##SPC1## 
     By way of reiteration, TABLE I below shows the allowable combinations of node and link states. All nodes start as CHARGED, and then cycle through the FORCED, SNAPPED, and DISCHARGED states. The nodes may cycle synchronously or asynchronously; however, the nodes are never out of lock-step. The link state may be misaligned with the node state because the link state may lag or lead the node state. 
     
                       TABLE I______________________________________nodes/links  captain     guard    friend______________________________________CHARGED                  chargeFORCED       force       force    resign                    snapSNAPPED      snap        snap     resignDISCHARGED   discharge   discharge                             resign                    charge______________________________________ 
    
     In addition, TABLE II shows the possible states and state transitions of a clock in one clock cycle. The transition marked x* is possible only when no data is interlocked between trigger and release; equivalently, no data is transferred. It is further noted that the clock can be in any one of the possible states at the start of a clock cycle. 
     
                       TABLE II______________________________________  relaxed         inhibited  relaxed         released  triggered         inhibited  triggered         released______________________________________--         r,i   r,r         t,i t,r______________________________________r,i        x     x           xr,r              x                x*t,i              x               xt,r                              x______________________________________ 
    
     Distribution of Data After Establishment of the Spanning Tree 
     Data may be distributed as part of the synchronized cycles described above. Between the trigger and release of any clock, data may be written. Also, with reference to FIG. 48, data may be received along each guard link (reference numeral 4802) whose mode is force, as per reference numeral 4810. All data messages are propagated backward (reference numeral 4820) toward the root of the spanning tree via each node&#39;s captain link. Thus, data moves toward the root (or supercaptain (4801)--i.e., the node with no captain link). Once a node becomes SNAPPED, which is equivalent to each link associated with this node having a mode of snap (reference numeral 4830), no further data messages can originate upward from this node or from any links which this node guards, since the clock in this node and all clocks in nodes accessible via guard links are already released. All data messages are accumulated with the supercaptain by the time it becomes SNAPPED. All accumulated data is distributed forward (reference numeral 4840) in the spanning tree toward leaf nodes with the discharge message (reference numeral 4850). Each node receiving a discharge message holds a copy of the data for local read access, and forwards data along each guard link with the discharge message. Nodes ultimately respond with the charge message (reference numeral 4860) to begin a new synchronization cycle. Thus, the network cycles through write-read phases, including a stage wherein reconfiguration of the network occurs in each cycle to determine another spanning tree (possibly a new one or maybe even the last spanning tree). 
     IV. VHDL Code 
     The VHDL code commensurate with the flow diagrams set forth in FIGS. 5-16 is set forth in the Appendix. 
     It is to be understood that the above-described embodiments are simply illustrative of the application of the principles in accordance with the present invention. Other embodiments may be readily devised by those skilled in the art which may embody the principles in spirit and scope. Thus, it is to be further understood that the methodology described herein is not limited to the specific forms shown by way of illustration, but may assume other embodiments limited only by the scope of the appended claims. ##SPC2##