Abstract:
Disclosed herein is a nonvolatile semiconductor memory device which comprises a memory cell array, page buffers and Y-pass gate circuit. Each page buffer according to the present invention contains its latch which has a first current driving capacity during a sensing period of a read operation and a second current driving capacity during a data output period of the read operation. Similar adjustable current drive capacity is provided during a program operation of the memory device. Preferably, such additional current drive capacity is provided via dual parallel pull-up transistors provided within a data latch circuit corresponding with each bit line of the memory device. Provision of the second parallel transistor and associated gating eliminates the need for one of the prior art circuit inverters in the latch, thereby reducing layout space over-all within the page buffer circuit region of the device.

Description:
FIELD OF THE INVENTION 
     The present invention relates to memories and more particularly to memories employing electrically erasable and programmable read-only-memory cells (EEPROM cells). 
     BACKGROUND OF THE INVENTION 
     There is an increasing demand for semiconductor memories that can be electrically erased and programmed without the need for refreshing data stored in the memory. Also, there is a trend toward enhancing the storage capacity and the density of integration in memory devices. NAND-type flash memory is one example of a nonvolatile semiconductor memory that provides high capacity and integration density without the need for refreshing stored data. 
     FIG. 1 contains a block diagram of an array of memory cells and conventional page buffers assigned to the array in a NAND-type flash memory. The memory includes a memory cell array  10 , a page buffer circuit  20  and a Y-pass gate circuit  30  (or referred to as “a switch circuit”). The memory cell array  10  is formed of a plurality of strings  12  (a “string” is a cell unit corresponding to one bit of data) arranged in columns. Each string  12  includes a string selection transistor SSTi (i=0, 1, . . . , m), the gate of which is coupled to a string selection line SSL. Each string  12  also includes a ground selection transistor GSTi (i=0, 1, . . . , m), the gate of which is coupled to a ground selection line GSL. Memory cells MCj (j=0, 1, . . . , n) are connected in series between each string selection transistor SSTi and its associated ground selection transistor GSTi. Control gates of the memory cells are coupled to word lines WLj (j=0, 1, . . . , n). The drain of each string selection transistor SSTi is connected to its corresponding bit line Bli (i=0, 1, . . . , m), and the source of each ground selection transistor GSTi is connected to a common source line CSL. 
     The page buffer circuit  20  includes page buffers  20 _i (i=0, 1, . . . , m) corresponding to the bit lines BLi, respectively. During a read operation, a page buffer senses data from a selected memory cell and then transfers the data to a data bus DB through the Y-pass gate circuit  30 . Hereinafter, even page buffer  20 _ 0 , corresponding to bit line BL 0 , is referred to in describing its constructions. Other page buffers  20 _ 1  to  20 _m, corresponding to other bit lines BL 1  to BLm, have the same constructions and functions as those of the page buffer  20 _ 0 . 
     The page buffer  20 _ 0  includes PMOS transistor M 2 , six NMOS transistors M 1  and M 3  to M 7 , a latch  40  formed of a pair of inverters INV 1  and INV 2 , and tri-state inverter INV 3 . The NMOS transistor M 1 , whose gate is coupled to signal BLSHF, is connected between a sensing node N 1  and a corresponding bit line BL 0  to adjust a voltage level of the bit line BL 0  which is developed while being activated and to prevent the page buffer  20 _ 0  from being influenced by a high voltage when the high voltage is applied to BL 0 . The gate and source of the PMOS transistor M 2 , the drain of which is connected to the sensing node N 1  (at the drain of M 1 ), are connected to a signal CURMIR and a power supply voltage Vcc, respectively. The PMOS transistor M 2  supplies current to the bit line BL 0  in response to the signal CURMIR. 
     As seen from FIG. 2, the inverter INV 1  of the latch  40  is formed of two PMOS transistors M 12  and M 13  and one NMOS transistor M 14  connected as illustrated in FIG. 2, and the inverter INV 2  of the latch  40  is formed of CMOS inverter well known in the art. The PMOS transistor M 12  is controlled by a signal PBset, which from FIG. 1 will be understood to be inactivated only when the NMOS transistor M 3  is turned on (i.e. only during a discharge period of the read operation when DCB is active (high)). This is to prevent power noise from being generated when the page buffers are reset and the bit lines are discharged. 
     Referring again to FIG. 1, the NMOS transistor M 3  has its source and gate connected to a ground voltage Vss and a signal DCB, respectively, and is connected between the sensing node N 1  and the ground voltage Vss. The transistor M 3  discharges a voltage of the bit line BL 0  and resets the page buffer  20 _ 0  output to a ground level. The NMOS transistor M 4 , the gate of which is coupled to a signal SBL, is connected between a node N 2  of latch  40  and the sensing node N 1 . The drain of the transistor M 4  is connected to the Y-pass gate circuit  30  through tri-state inverter INV 3 , the state of which is controlled by signals Osac and nOsac (the complement of Osac). Data in the latch  40  is transferred to the data bus DB through the tri-state inverter INV 3  and the Y-pass gate circuit  30 . Data to be programmed is transferred to the node N 2  of the latch  40  through the NMOS transistor M 7 , the gate of which is coupled to a signal SPB. Node N 3  (a complementary node of N 2 ) of latch  40  is connected to Vss through the NMOS transistor M 5 , whose gate is coupled to the sensing node N 1 , and the NMOS transistor M 6 , whose gate is coupled to a signal Olatch. The NMOS transistors M 5  and M 6  thus set the state of data stored in the latch in response to a voltage level on the bit line BL 0 . 
     According to the conventional page buffer as described above, when data held in the latch  40  is transferred to the data bus DB during read and program operation, the tri-state inverter INV 3  not only drives the data bus DB in response to a voltage level of the node N 2 , but also prevents charges on the node N 2  from being discharged to the data bus DB. However, the data path of the conventional page buffer is divided into an input path formed of the NMOS transistor M 7  and an output path formed of the tri-state inverter INV 3 . And, the tri-state inverter INV 3  is formed by use of multiple MOS transistors and power lines as well known to ones skilled in the art. For this reason, the conventional page buffer has a high component count that renders it difficult to lay out the tri-state inverters in the page buffers  20 _i within a page buffer region of the flash memory device in which higher capacity and integration density are required. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a nonvolatile semiconduct or memory device having improved page buffers. 
     In order to attain the above objects, according to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device which contains memory cells arranged in rows and columns, page buffers and Y-pass gate circuit. The page buffers are arranged so as to correspond to the columns, with each page buffer holding a datum. The Y-pass gate circuit selects one or more of the bit lines to transfer data held in latches corresponding to the selected bit lines to a data bus. Each latch has adjustable current driving capacity: a first current driving capacity when data is sensed and latched by corresponding page buffers during a read operation, and a second current driving capacity when data is transferred from the corresponding page buffers to the data bus via the switch circuit during the read operation. 
     In accordance with one embodiment, the latch of each page buffer comprises an inverter having an input terminal coupled to a corresponding sensing node via the first transfer transistor and an output terminal coupled to a latch controller; a first pull-up transistor having a source coupled to a power supply voltage, a gate coupled to a first control signal, and a drain; a second pull-up transistor having a source coupled to the power supply voltage, a gate coupled to a second control signal, and a drain coupled to the drain of the first pull-up transistor; a third pull-up transistor having a source coupled to a common drain of the first and second pull-up transistors, a gate coupled to the input terminal of the inverter, and a drain coupled to the output terminal of the inverter; and a pull-down transistor having a drain coupled to the input terminal of the inverter, a gate coupled to the output terminal of the inverter, and a source grounded. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be described by way of exemplary embodiments, but not limitations, illustrated in the accompanying drawings in which like references denote similar elements, and in which: 
     FIG. 1 is a block diagram of a memory cell array and page buffers in a conventional NAND-type flash memory device; 
     FIG. 2 is a detailed circuit diagram of a conventional latch illustrated in FIG. 1; 
     FIG. 3 is a block diagram of a memory cell array and page buffers in a NAND-type flash memory device according to the present invention; 
     FIG. 4 shows a preferred embodiment of a latch illustrated in FIG. 3; 
     FIG. 5 is a timing diagram for describing a read operation according to the present invention; and 
     FIG. 6 is a timing diagram for describing a program operation according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The preferred embodiment according to the present invention will be more fully described below with reference to the accompanying drawings. 
     FIG. 3 contains a block diagram of an array of memory cells and page buffers assigned to the array in a NAND-type flash memory according to the present invention. The memory includes a memory cell array  10 , a page buffer circuit  100  and a Y-pass gate circuit  30  (referred to also as “a switch circuit”). The memory cell array  10  is formed of a plurality of strings  12  (a “string” is a cell unit corresponding to one bit of data) arranged in columns. Each string  12  includes a string selection transistor SSTi (i=0, 1, . . . , m), the gate of which is coupled to a string selection line SSL. Each string  12  also includes a ground selection transistor GSTi (I=0, 1, . . . , m), the gate of which is coupled to a ground selection line GSL. Memory cells MCj (j=0, 1, . . . , n) are connected in series between each string selection transistor SSTi and its associated ground selection transistor GSTi. Control gates of the memory cells MCj are coupled to corresponding word lines WLj (j=0, 1, . . . , n). The drain of each string selection transistor SSTi is connected to its corresponding bit line Bli (i=0, 1, . . . ,m), and the source of each ground selection transistor GSTi is connected to a common source line CSL. The word lines WLj, the string selection line SSL and the ground selection line GSL are coupled to a row decoder (not shown). 
     The page buffer circuit  100  according to the present invention includes a plurality of page buffers  100 _i assigned to the bit lines BLi in the memory cell array  10 . One page buffer  100 _ 0 , corresponding to a bit line BL 0 , is referred to in describing its construction. Other page buffers  100 _ 1  to  100 _m, corresponding to other bit lines BL 1  to BLm, have the same constructions and functions as those of the page buffer  100 _ 0 . The page buffer  100 _ 0  includes PMOS transistor M 22 , six NMOS transistors M 21  and M 23  to M 27  and a latch  120  formed of a pair of inverters INV 21  and INV 22 . In this embodiment, the page buffer  100 _ 0  according to the present invention differs from that of FIG. 1 in that the tri-state inverter INV 3  of FIG. 1 is removed and one inverter INV 1  of FIG. 1 is substituted by an inverter INV 21  which performs the function similar to the removed tri-state inverter INV 3 , as will be more fully described below. 
     Referring to FIG. 3, the NMOS transistor M 21  (referred to as “a bit line shut-off transistor”), whose gate is coupled to a signal BLSHF, is connected between a sensing node N 1  and a corresponding bit line BL 0  to adjust a voltage level of the bit line BL 0  which is developed while being activated and to prevent the page buffer  100 _ 0  from being influenced by a high voltage when the high voltage is applied to the bit line BL 0 . The gate and source of the PMOS transistor M 22 , the drain of which is connected to the sensing node N 4  (and to the drain of M 21 ), are connected to a signal CURMIR and a power supply voltage Vcc, respectively. The PMOS transistor M 22  supplies current to the bit line BL 0  in response to the signal CURMIR. 
     Continuously, the NMOS transistor M 23  (referred to as “a discharge transistor”) has its source and gate connected to a ground voltage Vss and a signal DCB, respectively, and its drain is connected to the sensing node N 4 . The NMOS transistor M 23  discharges a voltage of the bit line BL 0  and resets the latch  120  to a ground voltage Vss level (i.e. it sets a node N 5  to the ground voltage level). The NMOS transistor M 24  (referred to as “a first transfer transistor”), the gate of which is coupled to a signal SBL, is connected between the nodes N 4  and N 5 . The drain of the transistor M 24  is connected to the Y-pass gate circuit  30  via the NMOS transistor M 27  (referred to as “a second transfer transistor”), the gate of which is coupled to a signal SPB. Data to be programmed is transferred to the node N 5  of the latch  120  through the NMOS transistor M 27 . Furthermore, data held in the latch  120  is transferred to the Y-pass gate circuit  30  via the NMOS transistor M 27 . A node N 6  (a complementary node of N 5 ) of the latch  120  is connected to Vss through the NMOS transistor M 25 , whose gate is coupled to the sensing node N 4 , and the NMOS transistor M 26 , whose gate is coupled to a signal Olatch. The NMOS transistors M 25  and M 26  change a state of data stored in the latch in response to a voltage level on the bit line BL 0 , and constitute “a latch controller”. 
     As illustrated in FIG. 3, the NAND-type flash memory device further comprises precharge means formed of PMOS transistor M 28 . The precharge means is connected to the data bus DB, and is to charge the data bus DB at a power supply voltage Vcc before a selected memory cell starts to be programmed, as will be more fully described below. 
     Referring to FIG. 4, a preferred embodiment of the latch  120  of FIG. 3 is illustrated. One inverter INV 21  of the latch  120  is formed of three PMOS transistors M 12 , M 13  and M 29  used as pull-up transistors, and an NMOS transistor M 14  used as a pull-down transistor. (The other inverter INV 22  is a well-known CMOS inverter.) The PMOS transistor M 12  has its source connected to the power supply voltage Vcc and its gate coupled to a signal PBset. The PMOS transistor M 13 , whose source is connected to the drain of the transistor M 12 , has its gate coupled to the node N 6  and its drain coupled to the node N 5 . The PMOS transistor M 29 , the gate of which is connected to a signal nDouten, has its source coupled to the power supply voltage Vcc and its drain coupled in common to the drain of the transistor M 12  and the source of the transistor M 13 . The NMOS transistor M 14  has its gate coupled to the node N 6 , its drain coupled in common to the node N 5  and to the drain of the transistor M 13 , and its source coupled to the ground voltage Vss. 
     When the low-active signal nDouten is high (inactivated), the current driving capacity of the latch  120  is determined only by the PMOS transistor M 12  (hereinafter, it is referred to as “a first current driving capacity”). On the other hand, when the signal nDouten is activated low, the current driving capacity of the latch  120  is determined by the PMOS transistors M 12  and M 29  (hereinafter, it is referred to as “a second current driving capacity”). Thus, according to the improved page buffer of the present invention, the latch  120  has adjustable current driving capacity. 
     In this embodiment, the PMOS transistor M 12  is controlled by the signal PBset, which is inactivated any time the NMOS transistor M 23  is turned on, i.e. only during a discharge period of the read operation. This is to prevent power noise from being generated when the page buffers  100 _i are reset and the bit lines are discharged. Furthermore, the signal nDouten is activated when data in the latch  120  is transferred to the data bus DB via the Y-pass gate circuit  30 . This is to prevent charges on the node N 5  from being discharged to the data bus DB. Furthermore, the signal nDouten is activated when data in the latch  120  is transferred to the corresponding bit line BL 0  during a program operation (or the bit line BL 0  is charged by the latch  120 , depending on its latch state during the program operation). This is to charge the bit line BL 0  at Vcc a shorter period of time during a bit line charge period of the program operation. 
     FIG. 5 is a timing diagram for describing a read operation of NAND-type flash memory device using the page buffer according to the present invention. The read operation according to the present invention will be described more fully described below with reference to FIGS. 3 to  5 . The page buffer  100 _ 0 , corresponding to the bit line BL 0 , is referred to in describing the read operation. Other page buffers  100 _ 1  to  100 _m, corresponding to other bit lines BL 1  to BLm, have the same functions as those of the page buffer  100 _ 0 . 
     If the read operation is started, the signals BLSHF, CURMIR, DCB and SBL all are set to Vcc. This forces the transistors M 21 , M 23  and M 24  to be turned on and the transistor M 22  to be turned off, thereby discharging the bit line BL 0  to a ground voltage Vss level and the node N 5  of the latch  120  to the ground voltage Vss level (that is, the latch  120  is reset). Since the signals PBset and nDouten are set to Vcc, the PMOS transistors M 12  and M 29  of FIG. 4 are turned off. This is to prevent power noise from being generated when the latch  120  is reset and the bit line BL 0  is discharged. The above-described operation is referred to as “a discharge period of the read operation”. 
     In this embodiment, as the signal nCharge_en is maintained at Vcc, the PMOS transistor M 29  used as precharge means is turned off during the read operation. Therefore, the data bus DB may be charged at Vss during the read operation. 
     And then, in a sensing period of the read operation, data stored in a selected memory cell (e.g. a datum stored at WL 0  and BL 0 ) is sensed by the page buffer  100 _ 0 . In particular, the string selection line SSL, the ground selection line GSL and unselected word lines (e.g. WL 1  to WLn) are set to Vcc or higher than Vcc while a selected word line (e.g. WL 0 ) and common source line CSL are held to Vss. At this time, the voltage of the signal BLSHF goes to a predetermined voltage level, for example, about 1.5 to 1.6V, and the signals SBL and DCB transitions from a logic high level (e.g. Vcc) to a logic low level (e.g. Vss). The signal CURMIR drops down to a predetermined voltage level. With the biasing condition of the control signals, the bit line BL 0  either is pulled up to about 1.5V when the selected memory cell MC 0  is a programmed memory cell (referred to as an “off-cell”), or it is pulled down to 0V when the selected memory cell MC 0  is an erased memory cell (referred to as an “on-cell”). 
     In the case of the former, the sensing node N 4  of the page buffer  100 _ 0  becomes the power supply voltage Vcc level, so that when the signal Olatch goes high, the node N 5  of the latch  120  is changed to Vcc from Vss by the NMOS transistors M 25  and M 26 . In the case of the latter, the sensing node N 4  thereof becomes the ground voltage Vss level, so that although the signal Olatch transitions from a logic low level to a logic high level, the node N 5  of the latch  120  is held to Vss (since the transistor M 25  is turned off). 
     During sensing data from the selected memory cell, the signal nDouten is set to Vcc and the signal PBset is set to Vss. Therefore, the latch  120  has the first current driving capacity which is determined only by the PMOS transistor M 12 . 
     Thereafter, in a data output period of the read operation, data held in the latch  120  is transferred to the data bus DB (i.e. its corresponding data line) from the page buffer  120  via the Y-pass gate circuit  30 . During the data output period, the signal nDouten is set to the ground voltage Vss level, so that the PMOS transistor M 29  of the latch  120  is turned on. This means that the current driving capacity of the latch  120  is increased by the current driving capacity of the transistor M 29 . Thus, the latch  120  has the second current driving capacity. Under this condition, when the Y-pass gate circuit  30  is activated, data in the latch  120  is transferred to the data bus DB which has been discharged at the voltage level of Vss. If the node N 5  is held to Vcc, the data bus DB is charged up to the power supply voltage Vcc level by the PMOS transistors M 12  and M 29  of the latch  120 . Since the transistors M 12  and M 29  supply the data bus DB with an amount of current sufficient to charge the data bus DB, the node N 5  of the latch  120  continues to be maintained at the power supply voltage Vcc level without being discharged. 
     As seen from the above description, although the tri-state inverter INV 3  is removed, the page buffer of the present invention performs the same read functions as those of FIG.  1 . As a result, since only one transistor M 29  and a signal line nDouten are added to the page buffer, while tri-state inverter INV 3  is removed altogether, the chip region occupied by the page buffer of the invention is decreased to an important extent, compared with the conventional page buffer. 
     FIG. 6 is a timing diagram for describing a program operation of the NAND-type flash memory device using the page buffer according to the present invention. The program operation will be more fully described below with reference to FIGS. 3,  4  and  6 . The page buffer  100 _ 0 , corresponding to the bit line BL 0 , is referred to in describing the program operation. Other page buffers  100 _ 1  to  100 _m, corresponding to other bit lines BL 1  to BLm, have the same functions as those of the page buffer  100 _ 0 . 
     In a discharge period of the program operation, the signals CURMIR, BLSHF and SBL are set to Vss, and the signal Olatch is set to Vcc. This forces the NMOS transistors M 21  and M 24  to be turned off and the PMOS transistors M 22  and M 28  and the NMOS transistor M 26  to be turned on. Under this condition, as the sensing node N 4  is pulled up to Vcc level by the transistor M 22 , the NMOS transistor M 25  is turned on. Thus, the node N 6  of the latch  120  is grounded via the transistors M 25  and M 26 , so that the node N 5  thereof is set to Vcc via the inverter INV 21 . At the same time, the signal nCharge_en is set to Vss level so as to charge the data bus DB at Vcc level. During the discharge period, the signal nDouten is set to Vcc level and the signal PBset is set to Vss level. That is, the current driving capacity of the latch  120  is determined only by the PMOS transistor M 12  in FIG.  4 . 
     In a bit line charge period of the program operation, the node N 5  of the latch  120  is reset to Vcc, and data to be programmed is loaded in the page buffer  100 _ 0  via the Y-pass gate circuit  30 . The signals BLSHF and SBL are set to Vpp higher than Vcc, and the signal nDouten is set to Vss. This forces the NMOS transistors M 21  and M 24  to be turned on, thereby charging the bit line BL 0  either at Vcc (in this case, the selected memory cell is program inhibited) or at Vss (in this case, the selected memory cell is programmed) depending on a logic level of data to be programmed. Since the signal nDouten is set to Vss, the PMOS transistor M 29  of the latch  120  is turned on, so that the current driving capacity of the latch  120  is determined by the PMOS transistors M 12  and M 29  (the latch  120  has the second current driving capacity). Thus, the bit line BL 0  is charged more quickly in time via the NMOS transistors M 21  and M 24  as compared with the conventional page buffer which contains a latch having the current driving capacity determined only by one PMOS transistor M 12  (refer to FIG.  2 ). 
     Continuously, after the bit line BL 0  is charged either at Vcc or at Vss, a high voltage is applied to a selected word line (for example, WL 0 ), so that a selected memory cell starts to be programmed for a predetermined time. At the same time with programming, Y-scanning operation is performed which is to check the programmed level of the memory cell so as to prevent the memory cell to be programmed from being over-programmed. As the NMOS transistor M 8  of the Y-pass gate circuit  30  corresponding to the page buffer  100 _ 0  is switched on, a latch state of the node N 5  is transferred to the data bus DB via the Y-pass gate circuit  30 . As illustrated in FIG. 6, since the signal nDouten is maintained at Vss during the programming and Y-scanning period, the current driving capacity of the latch  120  is determined by the sum of the current driving capacities of the PMOS transistors Ml 12  and M 29 . 
     In the case where the data bus DB is discharged at Vss and the node N 5  has Vcc (when the cell is program inhibited), charge sharing between the node N 5  and the data bus DB occurs during the Y-scanning operation, so that the potential of the node N 5  is increasingly lowered. This means that the memory cell to be inhibited is programmed. That is, the program disturb well known in the art can be induced. Therefore, in this embodiment, in order to prevent this disadvantage, the data bus DB is charged at Vcc by the PMOS transistor M 28  before programming and Y-scanning. And then, a verify operation is performed. The verify operation is identical to data sensing of the above-described read operation, and description thereof is thus omitted. 
     As above described, the page buffer of the present invention performs the same program function as that of FIG.  1 . As a result, since only one transistor M 29  and a signal line nDouten are added to the page buffer, while the tri-state inverter is removed entirely, the region occupied by the page buffer of the invention can be decreased as compared with the conventional page buffer. Furthermore, during the bit line charge period of the program operation, the bit lines are charged more quickly in time via the NMOS transistors M 21  and M 24  of corresponding page buffers as compared with the conventional page buffer which contains a latch having the current driving capacity determined only by one PMOS transistor M 12  of FIG.  2 . 
     The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.