Abstract:
A display device includes a display panel having an adjustable refresh frequency, a data driver for receiving display data, generating driving voltages based on the display data, and driving the display panel to display images using the driving voltages, and a timing controller providing a timing control signal to the data driver. The timing control signal is generated according to the refresh frequency of the display panel. The data driver dynamically adjusts a setup time and a hold time of the data driver according to the timing control signal.

Description:
BACKGROUND 
     1. Technical Field 
     The present disclosure relates to display technology, and more particularly, to a display device having a data driver capable of dynamically adjusting a setup time and a hold time of the data driver. 
     2. Description of Related Art 
     Liquid crystal displays (LCD) provide advantages of portability, low power consumption, and low radiation, and thus have been widely used in various portable information products. 
     A typical LCD includes a liquid crystal panel having a plurality of pixel units, a gate driver (namely, a gate IC) providing scanning signals to the pixel units, and a data driver (namely, a source IC) providing gray scale voltages to the scanned pixel units. The data driver receives display data from a timing controller, converts the display data to corresponding gray scale voltages, and outputs the gray scale voltages to the scanned pixel units, driving the pixel units to display corresponding images. 
     Generally, the display data is provided to the data driver in a reduced swing differential signaling (RSDS) form. To enable the data driver to successfully receive and identify the RSDS data, a setup time and a hold time are preset in the data driver. 
     Specifically, the setup time is defined as a time period from when an RSDS data arrives at the data driver to a significant RSDS clock signal beginning, that is a prepare time period for fetching the RSDS data. The hold time is defined as a time period from the beginning of the RSDS clock signal to the arriving of a next RSDS data, that is a time period for the data driver to fetch the RSDS data. 
     Normally, the setup time and the hold time are both preset as fixed values. Nevertheless, a display timing of the LCD may be changed during operation, for example, a refresh frequency of the liquid crystal panel may be adjusted by a user to satisfy a current displaying requirement. In this circumstance, the data driver may be unable to identify the received RSDS display data. This may disable the LCD to function. 
     What is needed, therefore, is an LCD that can overcome the above-described limitation. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of at least one embodiment. In the drawings, like reference numerals designate corresponding parts throughout the various views. 
         FIG. 1  is a block diagram of a display device according to a first embodiment of the present disclosure, the display device including a timing controller having a timing signal generator. 
         FIG. 2  is a block diagram of the timing signal generator of the timing controller of the display device of  FIG. 1 . 
         FIG. 3  illustrates a timing signal generator and a data driver of a display device according to a second embodiment of the present disclosure. 
         FIG. 4  illustrates a timing signal generator and multiple data drivers of a display device according to a third embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Reference will now be made to the drawings to describe specific exemplary embodiments of the present disclosure in detail. 
     Referring to  FIG. 1 , a display device  100  according to a first embodiment of the present disclosure is shown. The display device  100  may be an LCD in one embodiment. The display device  100  includes a liquid crystal panel  101 , a gate driver  102 , a data driver  103 , and a timing controller  104 . 
     The liquid crystal panel  101  include a plurality of pixel units arranged as a matrix. Each pixel unit may include an active element which is configured to activate the pixel unit in response to a scanning signal provided by the gate driver  102 . The active element may be a thin film transistor (TFT), which includes a gate electrode electrically coupled to the gate driver  102 , a source electrode electrically coupled to the data driver  103 , and a drain electrode electrically coupled the a pixel electrode of the pixel unit. Under the control of the timing controller  104 , the gate driver  102  may output scanning signals to the pixel units in a determined time interval, so as to activate the pixel units row by row. When the pixel unit is activated, a corresponding data signal (e.g., a gray scale voltage signal) outputted from the data driver  103  is transmitted to the pixel electrode via the active element, such that the pixel unit is driven to display a related image. 
     The data driver  103  is configured to receive display data from the timing controller  104 , convert the display data into corresponding gray scale voltage signals, and output the gray scale voltage signals to the pixel units of the liquid crystal panel  101 . In one embodiment, the display data may be in an RSDS form. Moreover, the data driver  103  can also receive a timing control signal from the timing controller  104 . The timing control signal may be a 2-bit binary code, which may control the data driver  103  to dynamically configure a setup time and a hold time of the data driver  103  so as to enable the data driver  103  to successfully receive and identify the RSDS display data. For example, the data driver  103  may include a look-up table pre-stored in the data driver  103 . The table includes a plurality of entries each corresponding to a respective 2-bit binary code. The entries are configured to indicate mapping relations between the 2-bit binary codes and the corresponding setup time values and hold time values. 
     In one exemplary embodiment, the pre-stored table may be illustrated as follow, where T represents an RSDS clock cycle of the RSDS display date. 
     
       
         
               
               
               
               
             
               
               
               
               
               
             
           
               
                   
                   
               
               
                   
                 timing control signal 
                 setup time 
                 hold time 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 0 
                 0 
                  T/16-T/2 
                  T/16 
               
               
                   
                 0 
                 1 
                 2T/16-T/2 
                 2T/16 
               
               
                   
                 1 
                 0 
                 3T/16-T/2 
                 3T/16 
               
               
                   
                 1 
                 1 
                 4T/16-T/2 
                 4T/16 
               
               
                   
                   
               
             
          
         
       
     
     Upon receiving the timing control signal, the data driver  103  may select a corresponding entry in the table based on the timing control signal, obtain a setup time value and a hold time value from the selected entry, and then configure the setup time and the hold time the data driver  103  correspondingly. 
     By use of the table, the data driver  103  can automatically and dynamically adjust the setup time and the hold time the data driver  103 , and thereby satisfying different display timing requirements. As such, even if a refresh frequency of the liquid crystal panel  101  is adjusted during an operation of the display device  100 , the data driver  103  can identify the received RSDS display data efficiently, and thus generate corresponding gray scale voltage signals all the same. 
     Reference will now be made to the  FIGS. 2-4  to describe the how the timing control signal is provided to the data driver  103 . 
     The timing controller  104  is configured to receive original display data from an interface circuit (not shown), convert the original display data into the RSDS form, and then provide the RSDS display data to the data driver  103 . In particular, the original display data may be in a low voltage differential signaling (LVDS) form. Moreover, the timing controller  104  can also generate the 2-bit timing control signal according to the display timing of the display device  100 , and output the timing control signal to the data driver  103 . In particular, the timing controller  104  may employ a timing signal generator  105  to generate the timing control signal. 
     Referring to  FIG. 2 , in one embodiment, the timing signal generator  105  includes a memory  12 , a control unit  10 , a detector  15 , and a digital code converter  16 . The memory  12  may be an electrically erasable programmable read-only memory (EEPROM), which is used to store a plurality of timing codes each corresponding to a refresh frequency. Each timing code is a 4-bit digital code, and can be selected and outputted by the control unit  10  to the digital code converter  16  as to generate a corresponding timing control signal. For example, a 4-bit digital code (1, 1, 0, 0) may correspond to a refresh frequency of 60 Hz, while a 4-bit digital code (1, 0, 0, 1) may correspond to a refresh frequency of 75 Hz. In particular, the timing codes can be obtained through experiments on the display device  100  during the manufacturing processor, and pre-stored in the memory  12 . 
     The detector  15  may detect a frequency of the original display data received by the timing controller  104 , and provide a frequency indication signal to the control unit  10  in accordance with the detected frequency. By analyzing the frequency of original display data, the detector  15  can obtain a current refresh frequency of the liquid crystal panel  101 . When the refresh frequency is adjusted by a user, the detector  15  can update the frequency indication signal, so as to inform the control unit  10  with the adjusted refresh frequency. 
     The control unit  10  may analyze the frequency indication signal outputted by the detector  15 , and thereby obtaining the current refresh frequency of the liquid crystal panel  101 . Based on the refresh frequency, the control unit  10  may further select a corresponding one of the timing codes from the memory  12 , and then parallel output the timing code to the digital code converter  16 . 
     Upon receiving the timing code, the digital code converter  16  may convert the timing code into a 2-bit timing control signal, and output the timing control signal to the data driver  103 , so as to enable the data driver  103  to adjust a setup time and a hold time thereof. 
     The digital code converter  16  may include a first transistor Q 1 , a second transistor Q 2 , a third transistor Q 3 , and a fourth transistor Q 4 . The first to fourth transistors Q 1 -Q 4  may be metal oxide semiconductor filed effect transistors (MOSFETs). Gate electrodes of the transistor Q 1 -Q 4  serve as four input terminals of the digital code converter  16 , and are configured to receive the 4-bit timing code in parallel. Drain electrodes of the transistors Q 1  and Q 3  are both electrically coupled to a digital power voltage DVDD, and source electrodes of the transistors Q 2  and Q 4  are both grounded. Two resistors R 1  and R 2  are electrically coupled in series between a source electrode of the first transistor Q 1  and a drain electrode of the second transistor Q 2 , and a node between these two resistors R 1  and R 2  serves as a first output terminal of the digital code converter  16 . Two resistors R 3  and R 4  are electrically coupled in series between a source electrode of the third transistor Q 3  and a drain electrode of the fourth transistor Q 4 , and a node between these two resistors R 3  and R 4  serves as a second output terminal of the digital code converter  16 . The first and second output terminals may cooperative parallel output the 2-bit timing control signal to the data driver  103 . 
     For example, when the detector  15  detects a current refresh frequency of the liquid crystal panel  101  is 60 Hz, the control unit  10  select a corresponding 4-bit timing code (1, 1, 0, 0) from the memory  12 , and output the timing code (1, 1, 0, 0) to the digital code converter  16 . The timing code (1, 1, 0, 0) causes the first and third transistors Q 1  and Q 3  to be turned on, while the second and fourth transistor Q 2  and Q 4  to be turned off. Thus, a 2-bit timing control signal (1, 1) is generated and outputted to the data driver  103  by the digital code converter  16 . Based on the timing control signal (1, 1), the data driver  103  obtains a desired setup time value in a range from 4T/16 to T/2 and a hold time value of 4T/16 from the table pre-stored therein, and then configures the setup time and the hold time thereof according to the obtained values. As such, the data driver  103  is ensured to identify the received RSDS display data efficiently and provide corresponding gray scale voltage signals to the liquid crystal panel  101 . 
     In an alternative embodiment, the timing controller  104  can employ another timing signal generator  205  as illustrated in  FIG. 3  to generate the timing control signal. Referring to  FIG. 3 , the timing signal generator  205  is similar to be above-described timing signal generator  105  in  FIG. 2 , but differs in that the timing signal generator  205  need no digital code convert as illustrated in  FIG. 2 , instead, the timing control signals corresponding to different refresh frequencies are directly stored in a memory  22  thereof. Specifically, the timing signal generator  205  includes the memory  22 , a control unit  20 , and a detector  25 . In operation, the control unit  20  may select a corresponding 2-bit timing control signal from the memory  22  based on the current refresh frequency detected by the detector  25 , and directly output the timing control signal to the data driver  103 . 
     Furthermore, when the liquid crystal panel has a relative large size, pixel units of the liquid crystal panel can be divided into a plurality pixel regions. Each pixel region can be driven by a respective data driver. That is, multiple data drivers may be adopted in the display device to drive different regions of pixel units. Referring to  FIG. 4 , in such kind of display device, the control unit  30  of the timing signal generator  305  may simultaneously output the timing control signals to multiple data drivers  36 , such that multiple data drivers  36  can configure the setup time and the hold time properly. 
     It is to be further understood that even though numerous characteristics and advantages of a preferred embodiment have been set out in the foregoing description, together with details of the structures and functions of the embodiments, the disclosure is illustrative only; and that changes may be made in detail, especially in matters of shape, size and arrangement of parts within the principles of present disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.