Abstract:
A semiconductor memory device invention having a data latch circuit disclosed in the present invention, comprising a plurality of bit lines to which a reprogramable memory cell is connected, a data bus on which data is transferred, a latch circuit having latching the data transferred on the data bus, a read our circuit connected to the data bus and a data transfer circuit group having an ability to directly transfer the data latched in the latch circuit, to the read our circuit without transferred to the memory cell.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
         [0001]    This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-066954, filed Mar. 10, 2000, the entire contents of which are incorporated herein by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    This present invention relates to a semiconductor memory device which is reprogramable, and particularly relates to a reprogramable semiconductor memory device having a page latch.  
           [0004]    2. Description of the Related Art  
           [0005]    In some of a nonvolatile semiconductor memory device (EEPROM) which is reprogramable by one byte to by a few tens bytes (for one page), one latch circuit (page latch circuit) for retaining one page data is provided for every bit line. In this specification, the nonvolatile semiconductor memory device is called a semiconductor memory device having a page latch.  
           [0006]    An operation of a conventional nonvolatile semiconductor memory device having a page latch will be explained. FIGS. 18 a  to  18   c  indicate data flow diagrams at a data loading operation, at a programming operation and at a read operation in a conventional semiconductor memory device having a page latch, respectively. First of all, as shown in FIG. 18 a , one-page program data are loaded to a page latch. When one-page program data are stored in the page latch, typically one page data stored in memory cells are erased.  
           [0007]    As shown in FIG. 18 b , the one-page program data in the page latch are simultaneously written to the one-page memory cells, whose previous data have been erased. Also, when a data in the memory cell is read out, as shown in FIG. 18 c , a selected memory cell is connected to a read out circuit and the data is read from the selected memory cell.  
           [0008]    However, once a data loading operation is started, the operation continues to a data erasing operation and a data programming operation automatically in the conventional nonvolatile semiconductor memory device with a page lath. Also, in the data reading out operation, the conventional nonvolatile semiconductor memory device only has a mode in which the operation reads out data programmed to the memory cell.  
           [0009]    In such conventional nonvolatile memory devices with page latches, when a data is programmed to a memory cell and the programmed data is read out from the memory cell, and assuming that the data which is read out includes an error, it is very hard to determine whether the data which is programmed to the memory cell has included the error or the data which is read out from the memory cell was broken at the read out circuit.  
           [0010]    Also, when you test the page latch and the read out circuit in the conventional nonvolatile semiconductor memory device, you need a very long time to test because a data is programmed to a memory cell automatically.  
         SUMMARY OF INVENTION  
         [0011]    An object of this invention is to provide a semiconductor memory device capable of making it easy to determine a cause of an error if there is an error in reprogrammed data and carrying out a test of the page latches and the read out circuits in a short time.  
           [0012]    In order to accomplish the above object of this invention, a semiconductor memory device related to this invention comprises a bit line to which a reprogramable memory cell is connected, a data bus on which data is transferred, a latch circuit having latching the data transferred on the data bus, a read our circuit connected to the data bus and a data transfer circuit group has an ability to directly transfer the data latched in the latch circuit, to the read our circuit without via the memory cell.  
           [0013]    The data transfer circuit may have a first operation mode to transfer a data loaded to the latch circuit, to the memory cell connected to the bit line, a second operation mode to a data read out from the memory cell to the read circuit and a third operation mode to directly transfer the data latched in the latch circuit, to the read circuit.  
           [0014]    The third operation mode may be performed during a test of the semiconductor memory device.  
           [0015]    The first and the second operation mode may be performed during a normal operation and the third operation mode is performed during a test of the semiconductor memory device.  
           [0016]    The data transfer circuit group may have a first transfer gate, an one end of which electrically connected to the bit line, a second transfer gate, an one end of which electrically connected to an other end of the first transfer gate, a third transfer gate, an one end of which electrically connected to the one end of the first transfer gate and an other end of which electrically connected to the latch circuit and a fourth transfer gate, an one end of which electrically connected to an other end of the second transfer gate and an other end of which electrically connected to the read out circuit.  
           [0017]    It is desirable that when a data loaded to the latch circuit is transferred to the memory cell, the first transfer gate is set to ON state, the second transfer gate is set to OFF state, the third transfer gate is set to ON state, the fourth transfer gate is set to ON state, when a data read out from the memory cell is transferred to the read out circuit, the first transfer gate is set to ON state, the second transfer gate is set to ON state, the third transfer gate is set to OFF state, the fourth transfer gate is set to ON state, when a data loaded to the latch circuit is directly transferred to the read out circuit without via the memory cell, the first transfer gate is set to OFF state, the second transfer gate is set to ON state, the third transfer gate is set to ON state, the fourth transfer gate is set to ON state.  
           [0018]    A voltage of a gate electrode of the third transfer gate may be gradually raised to set to ON state.  
           [0019]    It may be desirable that when a data loaded to the latch circuit is transferred to the memory cell, the first transfer gate is set to ON state, the second transfer gate is set to OFF state, the third transfer gate is set to ON state, the fourth transfer gate is set to OFF state, when a data read out from the memory cell is transferred to the read out circuit, the first transfer gate is set to ON state, the second transfer gate is set to ON state, the third transfer gate is set to OFF state, the fourth transfer gate is set to ON state, when a data loaded to the latch circuit is transferred to the read out circuit, the first to the fourth transfer gate are set to ON state, the memory cell is set to non-selected state.  
           [0020]    A voltage of a gate electrode of the third transfer gate may be gradually raised to set to ON state.  
           [0021]    The semiconductor memory device having a data latch circuit further comprises a control circuit controlling the transfer gate group so as to achieve a first and second operation modes, the first operation mode programming a data loaded to the latch circuit, to the memory cell, the second operation mode stopping an operation after a data is loaded to the latch circuit.  
           [0022]    The first operation mode may be performed at a normal operation, the second operation mode is performed at a testing operation.  
           [0023]    The semiconductor memory device having a data latch circuit further comprises an error correction circuit is electrically connected to the read out circuit.  
           [0024]    A semiconductor memory device having a data latch circuit comprise, a bit line to which a reprogramable memory cell is connected, a data bus on which data is transferred, a latch circuit having latching the data transferred on the data bus, a read our circuit connected to the data bus and a data transfer circuit group, wherein the data transfer circuit group is controlled so as to transfer the data latched in the latch circuit, to the read our circuit without via the memory cell.  
           [0025]    The data transfer circuit may have a first operation mode to transfer a data loaded to the latch circuit, to the memory cell connected to the bit line, a second operation mode to a data read out from the memory cell to the read circuit and a third operation mode to directly transfer the data latched in the latch circuit, to the read circuit.  
           [0026]    The third operation mode may be performed during a test of the semiconductor memory device.  
           [0027]    The first and the second operation mode may be performed during a normal operation and the third operation mode may be performed during a test of the semiconductor memory device.  
           [0028]    It is desirable that the data transfer circuit group has a first transfer gate, an one end of which electrically connected to the bit line, a second transfer gate, an one end of which electrically connected to an other end of the first transfer gate, a third transfer gate, an one end of which electrically connected to the one end of the first transfer gate and an other end of which electrically connected to the latch circuit and a fourth transfer gate, an one end of which electrically connected to an other end of the second transfer gate and an other end of which electrically connected to the read out circuit.  
           [0029]    It is desirable that when a data loaded to the latch circuit is transferred to the memory cell, the first transfer gate is set to ON state, the second transfer gate is set to OFF state, the third transfer gate is set to ON state, the fourth transfer gate is set to ON state, when a data read out from the memory cell is transferred to the read out circuit, the first transfer gate is set to ON state, the second transfer gate is set to ON state, the third transfer gate is set to OFF state, the fourth transfer gate is set to ON state, when a data loaded to the latch circuit is directly transferred to the read out circuit without via the memory cell, the first transfer gate is set to OFF state, the second transfer gate is set to ON state, the third transfer gate is set to ON state, the fourth transfer gate is set to ON state.  
           [0030]    A voltage of a gate electrode of the third transfer gate may be gradually raised to set to ON state.  
           [0031]    It may be desirable that when a data loaded to the latch circuit is transferred to the memory cell, the first transfer gate is set to ON state, the second transfer gate is set to OFF state, the third transfer gate is set to ON state, the fourth transfer gate is set to OFF state, when a data read out from the memory cell is transferred to the read out circuit, the first transfer gate is set to ON state, the second transfer gate is set to ON state, the third transfer gate is set to OFF state, the fourth transfer gate is set to ON state, when a data loaded to the latch circuit is transferred to the read out circuit, the first to the fourth transfer gate are set to ON state, the memory cell is set to non-selected state.  
           [0032]    A voltage of a gate electrode of the third transfer gate may be gradually raised to set to ON state.  
           [0033]    The semiconductor memory device having a data latch circuit further comprises a control circuit controlling the transfer gate group so as to achieve a first and second operation modes, the first operation mode programming a data loaded to the latch circuit, to the memory cell, the second operation mode stopping an operation after a data is loaded to the latch circuit.  
           [0034]    The first operation mode may be performed at a normal operation, the second operation mode is performed at a testing operation.  
           [0035]    The semiconductor memory device having a data latch circuit further comprises an error correction circuit is electrically connected to the read out circuit.  
           [0036]    A test method of a semiconductor memory device comprises steps of; latching data at a page latch via a data bus on which the data are transferred, transferring the data latched in the page latch to a cell matrix for stored the data at a first mode and to a read out circuit at a second mode for testing whether or not an error occurs at a data transfer circuit group including the data bus, the page latch and read out circuit. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0037]    [0037]FIG. 1 a  and FIG. 1 b  show data flows respectively in a case that a semiconductor memory device of a first embodiment of this invention is set for a data loading operation and a page latch reading out operation.  
         [0038]    [0038]FIG. 2 shows a circuit example of a page latch which is provided in the semiconductor memory device of the first embodiment of this invention.  
         [0039]    [0039]FIG. 3 shows a waveform diagram which indicates a data loading operation of the page latch in FIG. 2.  
         [0040]    [0040]FIG. 4 shows a waveform diagram which indicates a programming operation of the page latch in FIG. 2.  
         [0041]    [0041]FIG. 5 shows a waveform diagram which indicates a reading out operation of the page latch in FIG. 2.  
         [0042]    [0042]FIG. 6 shows a waveform diagram which indicates a page latch reading out operation of the page latch in FIG. 2.  
         [0043]    [0043]FIG. 7 a  shows a state of the page latch at a data loading operation.  
         [0044]    [0044]FIG. 7 b  shows a state of the page latch at a programming operation.  
         [0045]    [0045]FIG. 7 c  shows a state of the page latch at reading out operation.  
         [0046]    [0046]FIG. 7 d  shows a state of the page latch at a page latch reading out operation.  
         [0047]    [0047]FIG. 8 a  and FIG. 8 b  show a circuit diagram of a control circuit to control a transfer signal N 2 .  
         [0048]    [0048]FIG. 9 shows a waveform diagram which indicates another page latch reading out operation of a page latch in FIG. 2.  
         [0049]    [0049]FIG. 10 a  shows a circuit diagram of a NOR type nonvolatile semiconductor memory device.  
         [0050]    [0050]FIG. 10 b  shows a circuit diagram of a three-transistor type nonvolatile semiconductor memory device.  
         [0051]    [0051]FIG. 11 shows a block diagram of one example of the control circuit.  
         [0052]    [0052]FIG. 12 shows a waveform diagram, which indicates a normal operation of the control circuit in FIG. 11.  
         [0053]    [0053]FIG. 13 shows a waveform diagram which indicates a normal operation of the control circuit in FIG. 11.  
         [0054]    [0054]FIG. 14 shows a waveform diagram which indicates a testing operation of the control circuit in FIG. 11.  
         [0055]    [0055]FIG. 15 shows a flow chart which indicates a control sequence of the control circuit.  
         [0056]    [0056]FIG. 16 a  and FIG. 16 b  show data flows respectively in a case that a semiconductor memory device of a second embodiment of this invention is set for a data loading operation and a page latch reading out operation.  
         [0057]    [0057]FIG. 17 a  to FIG. 17 c  show data flows at the data loading operation and the page latch reading out operation of the second embodiment of this invention respectively.  
         [0058]    [0058]FIG. 18 a  to FIG. 18 c  show data flows at the data loading operation, the data programming operation and the data reading out operation of the conventional semiconductor memory device respectively.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0059]    We will explain embodiments of this invention with reference to figures. We will attach same numbers to same parts through all of the figures.  
       A First Embodiment  
       [0060]    [0060]FIGS. 1 a  and  1   b  show data flows at a data loading operation and at a data reading out operation from a page latch (page latch read) of a nonvolatile semiconductor memory device of a first embodiment, respectively. As shown in FIG. 1 a , one page data are loaded to a page latch  11  via a data bus  1  at the data loading operation. Then, the conventional nonvolatile semiconductor memory device, erasing of data programmed in a memory cell and programming of the loaded data follow the loading operation continuously and automatically when program data of one page are set to the page latch  11 .  
         [0061]    On the other hand, in the nonvolatile semiconductor memory device of the first embodiment of this invention, the loading operation is once stopped when program data of one page are set to the page latch  11 .  
         [0062]    After the stop of the operation, as shown in FIG. 1 b , the page latch  11  is electrically separated from a cell matrix  2  and, furthermore, is electrically connected to a read out circuit  27 . Thereby, the data loaded to the page latch  11  can be transferred to the read out circuit  27  directly and read out form the page latch  11  without transferring the data to the cell matrix  2 .  
         [0063]    The reading out operation, which reads out the data from the page latch  11 , for instance, is carried out at a testing operation. The reading out operation can be used for an examination for separating non-defect productions from defect productions and for a defect analysis of nonvolatile semiconductor memory device, or the like.  
         [0064]    The nonvolatile semiconductor memory device of the first embodiment in this present invention can carry out operations shown in FIG. 18 a  to FIG. 18 c  at a normal operation. In other words, the nonvolatile semiconductor memory device of the first embodiment in this present invention can be used, similarly to the conventional nonvolatile semiconductor memory device at the normal mode.  
         [0065]    Next, we will explain about one circuit example of the page latch  11 . FIG. 2 shows an exemplary circuit diagram of the page latch  11  contained in the nonvolatile semiconductor memory device of the first embodiment.  
         [0066]    As shown in FIG. 2, the page latch  11  has first transfer gates  13 - 1  to  13 -N, second transfer gates  15 - 1  to  15 -N, third transfer gates  17 - 1  to  17 -N and latch circuits  19 - 1  to  19 -N, respectively. The first to third transfer gates comprise, for instance, MOS transistors.  
         [0067]    Each one end of current paths of the fist transfer gates  13 - 1  to  13 -N is connected to corresponding bit lines BL 1  to BLN respectively. A transfer signal N 3  is commonly supplied to control nodes of the first transfer gate  13 - 1  to  13 -N.  
         [0068]    Each one end of current paths of the second transfer gates  15 - 1  to  15 -N is connected to corresponding the other ends of the current paths of the first transfer gates  13 - 1  to  13 -N respectively, which are connected to a data line  21 . The data line  21  is one line of the data bus  1  shown in FIGS. 1 a  and  1   b . The data line  21  is connected to the read out circuit  27  via a fourth transfer gate  25 . A transfer signal N 4  is supplied to a control node of the fourth transfer gate  25 . Select transfer signals N 1 [ 1 ] to N 1 [N] are supplied to the control nodes of the second transfer gates  15 - 1  to  15 -N respectively. The select transfer signals N 1 [ 1 ] to N 1 [N] are column select signals and outputted from a decoder  3  (a column decoder) shown in FIG. 1 a  and FIG. 1 b.    
         [0069]    Each one end of current paths of the third transfer gates  17 - 1  to  17 -N is connected to corresponding nodes  23 - 1  to  23 -N respectively. Each of the nodes  23 - 1  to  23 -N is the corresponding connection-node between the first transfer gates  13 - 1  to  13 -N and the second transfer gates  15 - 1  to  15 -N respectively. Each another end of current paths of the third transfer gates  17 - 1  to  17 -N is connected to corresponding latch circuits  19 - 1  to  19 -N respectively. A transfer signal N 2  is supplied to the control nodes of the third transfer gates  17 - 1  to  17 -N commonly.  
         [0070]    In the above-stated circuit, each gate of the first transfer gates  13 - 1  to  13 -N, the second transfer gates  15 - 1  to  15 -N, the third transfer gates  17 - 1  to  17 -N and the fourth transfer gates  25  functions as a data transfer circuit for transferring data. The data transfer circuit transfers data inputted on the data line  21  to the memory cell via the latch circuits  19 - 1  to  19 -N and the bit lines BL 1  to BLN, or transfers data via the data line  21  to the read out circuit  27 .  
         [0071]    It is noted that in the page latch  11  shown in FIG. 2 the N latch circuits  19 - 1  to  19 -N are electrically connected to one data line  21 . Therefore, at the data loading, data are loaded to the page latch  11  N times. When a total of N data are latched to the latch circuits  19 - 1  to  19 -N, respectively, one page data are set to the page latch  19 . After that, as shown in FIG. 1 b , the page latch reading out operation or the data erasing and the data programming operations are carried out.  
         [0072]    The number of the latch circuits  19 - 1  to  19 -N provided in the page latch  11  shown in FIG. 2 may be M (an integral number) in an actual device. In this case, parallel data M×N (M parallel data, N times) are loaded to the M page latches  11  via the M data lines  21 . When a total of M×N data are latched to the corresponding M×N latch circuits respectively, one page data is set in the page latches  11 . After that, as shown in FIG. 1 b , the page latch reading out operation, or the data erasing and the data programming operations are carried out. Next, we will explain about an operation example of the page latch  11  shown in FIG. 2.  
       DATA LOADING OPERATION  
       [0073]    [0073]FIG. 3 shows waveform diagram s at the data loading operation of the data latch  11  shown in FIG. 2. Also, FIG. 7 a  shows states of the page latch  11  at the data loading operation.  
         [0074]    As shown in FIG. 3, at a time t 1 , a chip enable signal /CE and a write enable signal /WE are set from High level to Low level respectively. When each of the chip enable signal /CE and the write enable signal /WE is set to Low level, the transfer signals N 3  and N 4  are set from High level to Low level respectively.  
         [0075]    As a result, the first transfer gates  13 - 1  to  13 -N and the fourth transfer gate  25  are set to OFF respectively, the page latch  11  is electrically separated from the cell matrix  2  and the read out circuit  27 . When the chip enable signal /CE and the write enable signal /WE are set to Low level, an address signal ADD is inputted to the chip. As a result, typically one of the N select transfer signals N 1 [ 1 ] to N 1 [N] is selected in accordance with the inputted address signal ADD, and the selected signal (for example, the select transfer gate signal N 1 [ 1 ]) is set from Low level to High level. This causes the second transfer gate  15 - 1  to turn ON, and the data DATA is transferred from the data line  21  to the connection node  23 - 1 .  
         [0076]    Next, at a time t 2 , a transfer signal N 2  is set to High level, thereby forcing the third transfer gates  17 - 1  to  17 -N to turn ON respectively. As a result, as shown in FIG. 7 a , the data DATA is transferred to the latch circuit  19 - 1  from the data line  21  via the connection node  23 - 1 , and latched by the latch circuit  19 - 1 .  
         [0077]    Same operations are repeated from times t 3  to t 8 . Thereby, the data DATA are transferred to all of the latch circuits  19 - 1  to  19 -N and the N data are latched to the corresponding latch circuits  19 - 1  to  19 -N respectively. And at a time t 9 , a DATA LOAD END signal is set to High level contemporarily, thereby finishing the data loading operation.  
       PROGRAMMING OPERATION  
       [0078]    The programming operation is carried out after the erasing operation. FIG. 4 shows waveform diagrams of the programming operation of the page latch  11  illustrated in FIG. 2. FIG. 7 a  shows a diagram illustrating a state of the page latch  11  at the programming operation. As shown in FIG. 4, first of all, at a time t 1 , a signal ERASE END indicated to an end of the erasing operation is set to High level to Low level. Thereby, all of the select transfer signals N 1 [ 1 ] to N 1 [N] are set to Low level. And the transfer signal N 3  remains at High level.  
         [0079]    As a result, the page latch  11  is electrically connected to the cell matrix  2  and separated from the data line  21 . Also, the transfer signal  2  slowly changes from at Low level to High level in order to prevent the data from destruction by a charge sharing. This, as shown in FIG. 7 b , allows each of the data DATA latched in the latch circuits  19 - 1  to  19 -N to be slowly transferred to the bit lines BL 1  to BLN and to be programmed to the memory cells (not shown in FIG. 7 a ) connected to bit lines BL 1  to BLN respectively. Next, at a time t 2 , the transfer signal N 2  is set from High level to Low level. The PROGRAM END signal is set to High level contemporarily and the programming operation is finished.  
         [0080]    [0080]FIG. 8 a  and FIG. 8 b  show circuit examples of the control circuits to control the transfer signal N 2  (hereafter, which are called N 2  control circuits). As shown in FIGS. 8 a  and  8   b , transfer signals N 2  SLOW and N 2  QUICK are inputted to the N 2  control circuit  100 . At the data loading operation, the transfer signal N 2  QUICK is set to Low level. Thereby, a output node  102  is sharply charged from a voltage supply VCC via a transistor PMOS  101 . On the other hand, at the programming operation or the after-stated page latch reading out operation, the transfer signal N 2  SLOW is set to Low level. Thereby, the output node  102  is slowly charged from the voltage supply VCC via a depletion type NMOS  104  and a PMOS resistor  103  or resistance  105 . These allow the transfer signal N 2  to be slowly changed from Low level to High level.  
         [0081]    It is noted that in order to prevent the data from destruction by the charge sharing, an inverter circuit can be located between the latch circuits  19 - 1  to  19 -N and the third transfer gates  17 - 1  to  17 -N, other than the transfer signal N 2  being made to change slowly from Low level to High level. But in view of high integration, it is more preferable that the transfer signal N 2  is made to change slowly from Low level to High level than that the inverter circuit is located between the latch circuits  19 - 1  to  19 -N and the third transfer gates  17 - 1  to  17 -N.  
       READING OUT OPEARATION  
       [0082]    As shown in FIG. 5, first of all, at a time t 1 , each of the chip enable signal /CE and the output enable signal /OE are set from High level to Low level, thereby allowing the signal N 4  to be set from Low level to High level. Also, the signal N 3  remains at High level and the signal N 2  remains at Low level.  
         [0083]    As a result, the page latch  11  is electrically connected to the cell matrix  2  and the data line  21  is electrically connected to the read out circuit  27  (see FIG. 2). This allows data DATA stored in the memory cell to be transferred to the connection nodes  23 - 1  to  23 -N via the bit lines BL 1  to BLN. After that, when the chip enable signal /CE and the output enable signal /OE are set to Low level respectively, the address signal ADD is inputted to the chip. As a result, by the address signal ADD, one of the N select transfer signals N 1 [ 1 ] to N 1 [N] is selected typically, and the selected one of the select transfer signals is set from Low level to High level. Thereby, as shown in FIG. 7 c , a selected one of the bit lines BL 1  to BLN (for example, BL 1  in FIG. 7 c ) is connected to the data line  21  via the connection node  23 - 1 , and the data DATA stored in the memory cell is transferred to the read out circuit  27 , and the data DATA which is transferred to the read out circuit  27  is outputted from the read out circuit  27  as a read out data.  
         [0084]    Next, at a time t 2 , the chip enable signal /CE and the output enable signal /OE are set from Low level to High level respectively. Thereby the transfer signal N 4  is set from High level to Low level, and the reading out operation is over.  
       PAGE LATCH READING OPERATION  
       [0085]    [0085]FIG. 6 shows a waveform diagram which indicates a page latch reading out operation illustrated in FIG. 2. And FIG. 7 d  shows a state diagram of the page latch  11  at the page latch reading out operation.  
         [0086]    As shown in FIG. 6, first of all, at a time t 1 , similar to the reading out operation, the chip enables signal /CE and the output enable signal /OE are set from High level to Low level respectively. Thereby, at the page latch reading out operation, the signal N 4  is set from Low level to High level, and the signal N 3  is set from High level to Low level.  
         [0087]    As a result, the first transfer gates  13 - 1  to  13 -N turn OFF, the page latch  11  is electrically separated from the cell matrix  2 . Also, the fourth transfer gate  25  turns ON. The data line  21  is electrically connected to the read out circuit  27 . Furthermore, the signal N 2  slowly changes from at Low level to High level. This allows data latched in the latch circuit  19 - 1  to  19 -N to be slowly transferred to the connection nodes  23 - 1  to  23 -N. After that, similar to the reading out operation, when the chip enable signal /CE and the output enable signal /OE are set to Low level respectively, the address signal ADD is inputted into the chip. Thereby, by the address signal ADD, one of the N select transfer signals N 1 [ 1 ] to N 1 [N] is selected typically, and the selected one of the select transfer signals is set from Low level to High level. As a result, as shown in FIG. 7 d , a selected one of the latch circuits  19 - 1  to  19 -N (for example, a latch circuit  19 - 1  in FIG. 7 c ) is connected to the data line  21  via the connection node  23 - 1 , and the data DATA latched in the memory cell is transferred to the read out circuit  27 , and the data DATA which transferred to the read out circuit  27  is outputted from the read out circuit  27  as a read out data.  
         [0088]    Next, at a time t 2 , the chip enable signal /CE and the output enable signal /OE are set from Low level to High level respectively. Thereby the transfer signal N 3  is set from Low level to High level, and the signal N 2  and N 4  are set from High level to Low level respectively, then the page latch reading out operation is over.  
         [0089]    We will explain about another type of the page latch reading out operation. The page latch reading out operation which is explained with reference to FIG. 6 and FIG. 7 is carried out at the state where the first transfer gates  13 - 1  to  13 -N are set to be OFF and the page latch  11  is electrically separated from the cell matrix  2 . However, the page latch reading out operation also may be carried out at a state where the page latch  11  is electrically connected to the cell matrix  2 . Hereinafter, we will explain such a page latch reading out operation as another type of the page latch reading out operation.  
         [0090]    [0090]FIG. 9 shows a waveform diagram of another page latch reading out operation of the page latch  11  illustrated in FIG. 2. Also, FIG. 10 a  shows a state diagram of the page latch  11  at this another type of the page reading out operation. As shown in FIG. 9 and FIG. 10, this another type of the page latch reading out operation differs from the page latch reading out operation which is explained with reference to FIG. 6 and FIG. 7 d , in the viewpoint that the memory cell is set to be non-selected state, while in the latter type of the latch reading out operation the signal N 3  remains at High level and the first transfer gates  13 - 1  to  13 -N are ON.  
         [0091]    With the memory cell MC being at non-selected state, even if the first transfer gates  13 - 1  to  13 -N are at ON state, the data stored in the memory cell is not transferred to the bit lines BL 1  to BLN. Therefore, the data latched in the latch circuits  19 - 1  to  19 -N can be transferred to the connection nodes  23 - 1  to  23 -N. As described above, in this another type of the page latch reading out operation, the data DATA latched in the latch circuits  19 - 1  to  19 -N can be transferred to the read out circuit  27 .  
         [0092]    In order to set the memory cell to be non-selected state, there are some ways in accordance with a type of nonvolatile memory cell, which are grouped into two types whether the nonvolatile memory has a select transistor or not.  
         [0093]    [0093]FIG. 10 a  shows a general NOR type nonvolatile memory cell. The NOR type nonvolatile memory cell does not have a select transistor. In this type of a nonvolatile memory cell, in order to set the memory cell MC to be non-selected, it is necessary to set all of the word lines WL in the cell matrix  2  to be at a non-select voltage which is typically 0 V. Also, FIG. 10 b  shows a three-transistor type nonvolatile memory. The three-transistor type nonvolatile memory cell has a select transistor STD connected to a bit line and a select transistor STS connected to a source line. In this type of a nonvolatile memory cell, in order to set the memory cell MC to be non-selected, it is necessary to set all the select transistors STD connected to the bit line or all the select transistors STS connected to the source line in the cell matrix  2 , to be non-select voltage which is typically 0V.  
         [0094]    With the memory cell MC being at non-selected state, even if the first transfer gates  13 - 1  to  13 -N are ON state, the data stored in the memory cell MC is not transferred to the bit lines BL 1  to BLN.  
         [0095]    Next, we will explain about one example of a control circuit to control the nonvolatile semiconductor memory device of the first embodiment with operations thereof. FIG. 11 shows a block diagram illustrating one example of the control circuit. It is noted that FIG. 11 specifically shows a block diagram of a control circuit to control from the data loading operation to the data programming operation.  
       NORMAL OPERATION  
       [0096]    [0096]FIG. 12 and FIG. 13 show waveform diagrams at normal operation of the control circuit illustrated in FIG. 11 respectively. It is noted that FIG. 2 and FIG. 3 are originally one waveform diagram, which is divided into two waveform diagrams. Therefore, times t 1 , t 2 , , , , , illustrated in FIG. 12 correspond with times t 1 , t 2 , , , , , illustrated in FIG. 13, respectively.  
         [0097]    As shown in FIG. 11, the control circuit  31  includes a data load control logic  33 , a finish logic after data load  35 , an erase control logic  37 , a program control logic  39 , a verify control logic  41 , a verify result judgment logic  43  and a recovery control logic  45 .  
         [0098]    The data load control logic  33  receives the chip enable signal /CE and the write enable signal /WE. When both of the chip enable signal /CE and the write enable signal /WE are set to Low level, a READY//BUSY signal is set from High level to Low level (at time t 1  in FIG. 12). The READY//BUSY signal is a signal that indicates whether the nonvolatile semiconductor memory device is a ready state or a busy state. When the READY//BUSY signal is at High level, the READY//BUSY signal indicates the ready state. When the READY//BUSY signal is at Low level, the READY//BUSY signal indicates the busy state.  
         [0099]    The data load control logic  33  outputs DATA LOAD  1  to DATA LOAD N signals when both of the chip enable signal /CE and the write enable signal /WE are set to Low level. Each of the DATA LOAD  1  to DATA LOAD N signals is a signal to control timings of N times of data loading. The DATA LOAD 1  to DATA LOADN signals are typically set from Low level to High level in numerical order (during the time period between t 1  and t 2  in FIG. 12 (DATA LOAD)). When all of the DATA LOAD 1  to DATA LOADN are set from High level to Low level, the data load logic  33  outputs a DATA LOAD END signal which is a signal that indicates an end of the data loading operation and is inputted to the finish logic after data load  35 .  
         [0100]    The finish logic after data load  35  outputs the ERASE START signal which is at High level when the a DATA LOAD END signal is set to High level and the TEST signal is set to Low level. It is noted that the TEST signal is set to Low level at the normal operation. The ERASE START signal is inputted to the erase control logic  37 .  
         [0101]    The erase control logic  37  outputs an ERASE  1  to ERASE N′ signals when the ERASE START signal is set to High level. Each of the ERASE  1  to ERASE N′ signals is a signal to control timings of the N′ times of data erasing. The ERASE  1  to ERASE N′ are typically set from Low level to High level in numerical order (during the time period between t 3  and t 4  in FIG. 12 (ERASE)). When all of the ERASE  1  to ERASE N′ signals are set from High level to Low level, the erase control logic  37  outputs a ERASE END signal which is a signal that indicates an end of the erasing operation and is inputted to an OR logic gate  38 .  
         [0102]    The OR logic gate  38  outputs a PROGRAM START signal which is High level when one of an ERASE END signal and a REPROGRAM START signal is set to High level. The PROGRAM START signal is a signal which indicates a start of the programming operation and is inputted to the program control logic  39 .  
         [0103]    The program control logic  39  outputs PROGRAM  1  to PROGRAM N″ signals when the PROGRAMS START signal is set to High level. Each of the PROGRAM  1  to PROGRAM N″ signals indicates a signal to control timings of N″ times of data programming. The PROGRAM  1  to PROGRAM N″ signals are typically set from Low level to High level in numerical order (during the time period between t 5  and t 6  in FIG. 12 (PROGRAM)). When all of the PROGRAM  1  to PROGRAM N″ signals are set from High level to Low level, the program control logic  39  outputs a PROGRAM END signal which is a signal that indicates an end of the programming operation and is inputted to a verify control logic  41 .  
         [0104]    When the PROGRAM END signal is set to Low level, the verify control logic  41  outputs VERIFY  1  to VERIFY N″′ signals. Each of the VERIFY  1  to VERIFY N″′ signals indicates a signal to control timings of N″′ times of verifying. The VERIFY  1  to VERIFY N″′ signals are typically set from Low level to High level in numerical order (during the time period between t 7  and t 8  in FIG. 13 (VERIFY)). When all of the VERIFY  1  to VERIFY N″′ signals are set from High level to Low level, the verify control logic  41  outputs a VERIFY END (I) signal which is a signal that indicates an end of the verifying operation and is inputted to a verify result judgment logic  43 .  
         [0105]    When both of the VERIFY END (I) signal and a VERIFY PASS signal are set to High level, the verify result judgment logic  43  outputs the VERIFY END (I) of High level. When the VERIFY PASS signal is set to Low level, the verify result judgment logic  43  outputs the PROGRAM START signal of Low level. The PROGRAM START signal indicates a start of a reprogramming operation and is inputted to the OR logic gate  38 . When a REPROGRAM START signal is set to High level, the reprogramming operation, which is shown as REPROGRAM in FIG. 12, is carried out. Also, the VERIFY END (Π) signal is a signal which indicates an end of the verifying operation at an normal operation and is inputted to the OR logic gate  44 .  
         [0106]    The OR logic gate  44  outputs a RECOVERY START (I) signal of High level, when one of the VERIFY END (Π) signal and the RECOVERY START (Π) signal is set to High level. The RECOVERY START (I) signal is a signal which indicates a start of a recovery operation and is inputted to a recovery control logic  45 .  
         [0107]    When the RECOVERY START (I) signal is set to High level, the recovery control logic  45  outputs RECOVRY  1  to RECOVRY N″″ signals. Each of the RECOVRY  1  to RECOVRY N″″ signals indicates a signal to control timings of N″″ times of recovery. The RECOVRY  1  to RECOVRY N″″ signals are typically set from Low level to High level in numerical order (during the time period between t 9  and t 10  in FIG. 13 (RECOVEY). When all of the RECOVRY  1  to RECOVRY N″″ signals are set from High level to Low level, the recovery control logic  45  outputs a RECOVERY END signal which is a signal that indicates an end of the recovery operation. When the RECOVERY END signal is set from High level to Low level, a READY//BUSY signal is set from Low level to High level. As a result, the semiconductor memory device becomes in a halted condition (at a time t 11  in FIG. 13).  
         [0108]    As stated above, the control circuit  31  makes the semiconductor memory device to carry out the data loading operation, the data erasing operation, the data programming operation and the verifying operation automatically at the normal operation. And after the verifying operation, the semiconductor memory device carries out the recovery operation, then is halted. It is noted that the verifying operation can be omitted. In this case, after automatically carrying out the data loading operation, the data erasing operation and the data programming operation, the semiconductor memory device carries out the recovery operation and then, becomes in a halted condition.  
       TESTING OPERATION  
       [0109]    [0109]FIG. 14 shows waveform diagram, which indicates a testing operation of the control circuit  31 , illustrated in FIG. 11. A time period between a time t 1  and a time t 2  in FIG. 14 indicates a period of a data loading operation. Similar to the normal operation, after the data loading operation, the DATA END signal is set to High level. The logic after data load  35  outputs the RECOVERY START (Π) of High level, when the DATA LOAD END signal and a TEST signal are set to High level. It is noted that the TEST signal is set to High level during the testing operation. The RECOVRY START (Π) signal is inputted to the OR logic gate  44 . Also, the ERASE START signal remains at Low level.  
         [0110]    The OR logic gate  44  outputs a RECOVERY START (I) signal of High level, when one of the VERIFY END (Π) signal and the RECOVERY START (Π) signal is set to High level. The RECOVERY START (I) signal is inputted to a recovery control logic  45 . A recovery period between a time t 3  and a time t 4  in FIG. 14 is a time period while the recovery operation carried out similar to the normal operation. After the recovery operation is ended, the RECOVERY END signal is set to High level then is set to Low level (RECOVERY END). The READY//BUSY signal is set from Low level to High level, and the semiconductor memory device becomes in a halted condition (at a time t 5  in FIG. 14).  
         [0111]    As stated above, at the testing operation, the control circuit  31  carries out the recovery operation after the data loading operation is ended, and makes the semiconductor memory device become in a halted condition.  
         [0112]    It is noted that a specific circuit schematic of the control circuit  31  is not limited to a circuit schematic illustrated in FIG. 11, and any other circuit configurations including a sequence as to be illustrated in FIG. 15 may be used thereto.  
       A Second Embodiment  
       [0113]    [0113]FIG. 16 a  and FIG. 16 b  show data flow diagrams at the data loading operation and the page latch reading out operation of a semiconductor memory device of the second embodiment respectively. The semiconductor memory device of the second embodiment differs from the semiconductor memory device of the first embodiment in that an error correction system is provided.  
         [0114]    First of all, the error correction system produces an inspection bits from an original data. The inspection bits are produced by an inspection bit generating circuit  51 . The inspection bits and the original data are programmed to the corresponding memory cells at the same time. Also, at the reading out operation, the original data and the inspection bits are read out from the memory cells at the same time to judge whether there is an error or not. Data that was judged as an error is corrected and outputted. The judgment of whether there is an error or not, and the error correction if any are carried out at the error correction circuit  53 .  
         [0115]    When a test and an inspection of the error correction system are carried out, it is necessary that many suspected error correction patterns are inputted to confirm that the error patterns are corrected regularly. Conventionally, it has taken a long time to test and inspect data by the error correction system because the data are programmed to memory calls after data loading. Nevertheless, in the second embodiment of the present invention, as shown in FIG. 16 a  and FIG. 16 b , at a testing operation, after the data loading operation is carried out, an operation of the semiconductor memory device is once stopped. After that, the page latch operation is carried out. This sequence is the same as the operations of the first embodiment.  
         [0116]    As a result, the data programming operation to the memory cells can be omitted at the test and inspection operation by the error correction system where it is necessary that many suspected error patterns are inputted. Therefore, in the second embodiment, a time for estimating and testing by the inspection bits generating circuit  51  and the error correction circuit  53  can be shorter than the conventional semiconductor memory device.  
         [0117]    [0117]FIG. 17 a  to FIG. 17 c  show data flows of the second embodiment of the nonvolatile semiconductor memory device at the normal operation. As shown in FIG. 17 a  to FIG. 17 c , the semiconductor memory device in the second embodiment operates similar to the conventional semiconductor memory device at the normal operation.  
         [0118]    As explained above, with the present invention, it is possible to provide a semiconductor memory device that is capable of being easy to specify a cause of an error for the case where a reprogrammed data is an error and operating tests of a page latch and a read out circuit at short time.  
         [0119]    Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended and their equivalents.