Abstract:
A galvanically isolating circuit for converting input voltage which is in a first potential to an output variable which is in a second potential. The circuit is characterized by a first input terminal and a second input terminal for receiving the input voltage in the first potential, and a first output terminal and a second output terminal in the second potential for generating the output variable. The circuit is further characterized by a serial capacitance section for providing galvanic isolation between the input terminals and the output terminals, first polarity switching means, which are arranged to operationally connect the input terminals to the serial capacitance section by periodically reversing the polarity, and second polarity switching means, which ate arranged to operationally connect the serial capacitance section to output terminals by periodically reversing the polarity, in synchronism with the first polarity switching means.

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to the transfer of an analog signal and particularly to a method and equipment for providing galvanic isolation. The invention further relates to a galvanically isolated electronic switch. 
     Analog signals need to be transferred from one device into another for example in industrial automation systems. Since the control devices are often in a different potential than the devices to be controlled, or because currents flowing in the neutral conductors of the devices may cause errors, a specific technique is needed for transferring the measurement or control signals of the devices to be controlled: if the difference in potential between the controlling device and the device to be controlled is small, then an ordinary differential amplifier is sufficient. When greater differences in potential are concerned, galvanic isolation is used. 
     The prior art teaches that galvanic isolation can be carried out for example with a converter, capacitor or opto-isolator. The analog signal to be measured is then first converted into a frequency, pulse ratio, light intensity or a digital form, and after the galvanic isolation the analog signal conforming to the original variable is restored. The present prior art galvanic isolators are, however, expensive. 
     In U.S. Pat. No. 5,361,037 Isolation Amplifier with Capacitive Coupling, the signals of the device to be controlled are isolated from those of the controlling device by means of a linear isolation amplifier circuit. The circuit in question performs the isolation using Switched Capacitor (SC) switching. The circuit is composed of a voltage-to-charge converter and a differential amplifier functioning as a charge indicator. The disadvantages of the circuit in question are, however, the sensitivity of the switching to stray capacitance, the large capacitors needed in the circuit because of the stray capacitance, and high load caused on the input side. 
     BRIEF DESCRIPTION OF THE INVENTION 
     It is an object of the invention to provide a method and an apparatus implementing the method to allow the above mentioned problems to be solved or at least minimized. The object of the invention is achieved with an method and an arrangement characterized by what is stated in the independent claim. The preferred embodiments of the invention are disclosed in the dependent claims. 
     The circuit of the invention comprises: 
     a first input terminal and a second input terminal for receiving input voltage; 
     a first output terminal and a second output terminal for generating output current; 
     a serial capacitance section for providing galvanic isolation between the input terminals and the output terminals; 
     first polarity switching means arranged to operationally connect the input terminals to the serial capacitance section by periodically reversing the polarity; and 
     second polarity switching means arranged to operationally connect the serial capacitance section to the output terminals by periodically reversing the polarity, in synchronism with the first polarity switching means. 
     The switches of a circuit according to a preferred embodiment of the invention may be provided with small capacitors, which provides such advantage as good tolerance for disturbances, low loading of the measurement point and low power consumption at high frequencies. The circuit of the preferred embodiment of the invention loads the input side only a little, and the circuit of the invention is not sensitive to stray capacitance. In addition, a circuit comprising smaller capacitors requires less silicon space and is therefore more economical than a circuit comprising large capacitors. Moreover, the circuit is simple. 
     According to another preferred embodiment of the invention, the output current which is in the circuit output terminals and which is proportional to the voltage to be measured, is converted to an output voltage in a second capacitance section. This provides the advantage that no power source is needed for the circuit and it is not necessary to examine in connection with installation whether the analog input, for example, should be isolated or not, because the couplings between the inputs, outputs and the controls of the circuit are galvanically isolated from one another. 
     According to an alternative embodiment of the invention, the second polarity switching means are followed by active means requiring a power source for generating output voltage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the following the invention will be described in greater detail in connection with preferred embodiments and with reference to the accompanying drawings, in which 
     FIG. 1 shows a differential voltage-to-current converter; 
     FIG. 2 shows two galvanically isolated analog switches; 
     FIG. 3 shows an embodiment of the invention for generating output voltage proportional to the voltage to be measured; 
     FIG. 4 shows switching according to a preferred embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 shows a differential voltage-to-current converter. The circuit comprises input terminals P 1  and N 1 , the first polarity switching means PS 1 , a serial capacitance section CS, i.e. a capacitor, polarity switching means PS 2 , and output terminals P 2  and N 2 . Output terminals A 1  and B 1  of the first polarity switching means serve at the same time as input terminals of the capacitance section CS, and output terminals A 2  and B 2  of the capacitance section CS serve at the same time as input terminals of the second polarity switching means. A voltage to be measured Uin is connected to the circuit&#39;s first and second input terminals P 1  and N 1 . The first polarity switching means PS 1  is arranged to connect terminal P 1  to terminal A 1  and teal N 1  to terminal B 1  and vice versa. Correspondingly, the second polarity switching means PS 2  are arranged to connect terminal A 2  to terminal P 2  and terminal B 1  to terminal N 2  or vice versa. The first and second polarity switching means are controlled periodically and in synchronism, i.e. they periodically reverse the direction of the current flowing through the capacitance section CS, while maintaining, at the same time, the original direction of the circuit&#39;s output current lout. To avoid transient short circuits, the switched SW 1 -SW 4  must be of the break-before-make type. 
     The voltage-to-current converter of FIG. 1 directs the voltage to be measured Uin entering the converter through the first polarity switching means PS 1  to the capacitance section CS and from there onward through the second polarity switching means PS 2  to a current loop IS. In the capacitance section CS the current changes its flow direction, whereas in the current loop portion IS the direction of the current lout remains unchanged. All the switches SW 11 , SW 21 , SW 12 , SW 22  function co-phasally, i.e. they are simultaneously connected first to A terminals, then to NC terminals and finally to B terminals. After this, the switches are again connected to NC terminals and then back to A terminals. The NC terminals in FIG. 1 show how a switch which is to be connected to terminal N, for example, is first detached from terminal P, and vice versa. In other words, the switches are of the break-before-make type. 
     In the fist step the switches SW 11  and SW 21  connect capacitor CA between terminals P 1  and P 2 . This charges the capacitor with a charge where Q=CA*Uin. Since the switches SW 12  and SW 22  connect capacitor CB between terminals N 1  and N 2 , which charges capacitor CB with a charge where Q 2 =CB*Uin, the circuit is closed. Consequently, the current lout=f*(CA+CB)*Uin, where f represents the switching frequency of the switches, in the current loop IS current flows from terminal P 2  to terminal N 2 . If capacitors CA and CB are of an equal magnitude (CA=CB=C), the current flowing from terminal P 2  to terminal N 2  is Iout=*f*C*Uin. This provides for a low penetration of disturbing signals, since the penetration is proportional to the difference between capacitors CA and CB. 
     In the second step, the switches SW 1   1  and SW 21  connect capacitor CA between terminals N 1  and N 2 , and the switches SW 12  and SW 22  connect capacitor CB between terminals P 1  and P 2 . Since the capacitors are of an equal magnitude, the current lout=2*f*C*Uin in the current loop flows from terminal P 2  to terminal N 2 , i.e. into the same direction and at an equal magnitude as in the first step. In other words, the differential voltage-to-current converter of FIG. 1 converts the measured direct current difference Uin to direct current lout. 
     Capacitors CA and CB in FIG. 1 are charged to and discharged by voltage Uin when the switches are in positions P and N, respectively. During a cycle, the charge Q=C*Uin causes two pulse-like direct current outputs lout=2*f*C*Uin, always to the same direction. 
     According to a preferred embodiment of the invention, the current loop IS of FIG. 1 can be switched off, and capacitor Cx can be placed to switch off point X, FIG.  4 . After several switching cycles, a voltage Uc=k*Uin where coefficient k&lt;1, the coefficient depending on stray capacitors, is generated over capacitor Cx. If the stray capacitors are considerably smaller than capacitors CA and CB, the switching can be used in a galvanically isolated voltage-to-voltage transfer. 
     The switching shown in FIG. 1 is independent of stray capacitors, because the stray capacitors of input terminals P 1  and N 1  only load the input, and the voltages over the output stray capacitors are constant and therefore no current is connected to the output. 
     FIG. 2 shows two galvanically isolated analog switches of an embodiment of the invention. The measures and values appearing in parentheses after the reference numerals of the components are given by way of example. 
     The first switch SW 11  comprises a PMOS transistor M 1  (W=40 μm, L=4 μm) and an NMOS transistor M 2  (W=20 μm, L=8 μm). Source S 1  and bulk B 1  of the PMOS transistor M 1  are connected to terminal P of the circuit formed by the two switches SW 11  and SW 12 , gate G 1  is connected to terminal W 1  of the switch SW 11  and drain D 1  to terminal W 3  of the switch SW 11 . Source S 2  and bulk B 2  of the NMOS transistor M 2  are connected to terminal N of the circuit formed by the two switches SW 11  and SW 12 , gate G 2  is connected to terminal W 2  of the switch SW 11 , and drain D 2  to terminal W 3  mentioned above. Between terminals W 1  and P are connected, in parallel, capacitor CP 1  (0.25 pF) and gate-to-source resistor R 3  (1 Mohm). Between terminal W 2  and terminal P is connected capacitor CP 2  (0.25 pF). Between terminal W 2  and terminal N is connected gate-to-source resistor R 5  (1 Mohm). Between input terminal AToN and terminal W 1  is connected capacitor C 1  (0.25 pF) and between input terminal AToN and terminal W 2  is connected capacitor C 2  (0.25 pF). 
     The second switch SW 12  shown in FIG. 2 comprises a PMOS transistor M 3  (W=40 μm, L=4 μm) and an NMOS transistor M 4  (W=20 μm, L=8 μm). Source S 3  and bulk  3  of the PMOS transistor M 3  are connected to terminal P mentioned above, gate G 3  is connected to terminal W 4  of the switch SW 12  and drain D 3  to terminal W 6  of the switch SW 12 . Source S 4  and bulk B 4  of the NMOS transistor M 4  are connected to the above mentioned terminal N, gate G 4  is connected to terminal W 5  of the switch SW 12  and drain D 4  to terminal W 6  of the switch SW 12 . Between terminals W 4  and P are connected, in parallel, capacitor CP 3  (0.25 pF) and gate-to-source resistor R 6  (1 Mohm). Between terminal W 5  and terminal P is connected capacitor CP 4  (0.25 pF). Between terminal W 5  and terminal N is connected gate-to-source resistor R 9  (1 Mohm). Between output terminal BToN and terminal W 4  is connected capacitor C 3  (0.25 pF). Between output terminal BToN and terminal W 5  is connected capacitor C 4  (0.25 pF). 
     Control inputs AtoN and BtoN shown in FIG. 2 can be galvanically isolated from the rest of the circuit by using capacitors C 1 , C 2 , C 3  and C 4  which may be formed quite simply, for example, of the contact&#39;s first netal layer, and isolating layer (such as silicon dioxide) and the second metal layer underneath. Because of the resistors R 3 , R 5 , RS and R 9 , the average values of the gate-to source voltages of the transistors M 1 -M 4  are about 0 volts. Consequently, in a polarity switch situation the conduction transistor (e.g. M 1 ) stops conducting until the other transistor (M 2 ) belonging to tie same switch (SW 11 ) is connected. 
     Capacitors CP 1 , CP 2 , CP 3  and CP 4  in FIG. 2 reduce the nonlinearity of the gate-to-source capacitors. Capacitors CP 1 , CP 2 , CP 3  and CP 4  are formed of the second metal layer, the isolation underneath it and a silicon base connected to a contact. FIG. 2 further shows electrostatic shields, i.e. resistor R 1  (&lt;1 kohm), diode D 1  and diode D 5 , and resistor R 2  (&lt;1 kohm), diode D 6  and diode D 7 , connected to output contacts A and B, respectively. When the circuit of FIG. 2 is to be implemented as a microcircuit, capacitors CP 1 , CP 2 , CP 3  and CP 4  are automatically formed of parasitic components included in the connection. 
     The galvanically isolated analog switch of FIG. 2 operates as follows. A square wave voltage (where U=15V, F=500 kHz, for example) which is differential (with regard to the P and N terminals, for example) is connected between terminals AtoN and BtoN to control the operation of the transistors. Control voltages and AtoN and BtoN of the switches SW 11  and SW 12  are connected through a thick capacitive isolator (C 1 , C 2 , C 3  and C 4 ), such as silicon dioxide which is able to withstand over 400 volts even in normal processes. When the voltage V (AtoN-BtoN) between terminals AtoN and BtoN becomes positive, transistors M 2  and M 3  become conductive. Output terminal A is then connected to terminal N and output terminal B to terminal P. 
     The time transistors N and M 3  stay in the conductive state depends on the time constant of the gate (e.g. (C 1 +CP 1 +Cg 1 )*R 3  where Cg 1  represents the gate-to-source capacitance of transistor M 1 ), on control voltage V(AtoN-BtoN) to be connected between terminals AtoN and BtoN, and on the threshold voltage of the transistors. When voltage V(AtoN-BtoN) becomes negative, transistors M 1  and M 4  become conductive. Terminal A then connects to terminal P and terminal B to terminal N. 
     Terminals P and N, i.e. measurement input, in FIG. 2 are correspondingly set as operating voltage and ground terminals for the microcircuit. According to the invention, these terminals are not used for power input, as in prior art microcircuits. The transistors and other parts of the microcircuit can thus be made small, which allows for small power losses and low input loads. 
     The microcircuit of FIG. 2 can be implemented using CMOS processes. If a plural number of switches of the invention are to be integrated into one and the same silicon chip, SOI technique (Silicon-On-Insulator), for example, can be used. Instead of controls AtoN and BtoN, optical switching can also be used, a hither voltage endurance being thereby obtained. 
     In FIG. 2 the switches are implemented using MOS transistors. Another alternative to implement the switches of FIG. 2 is to use bipolar technique. In that case, a saw-tooth voltage is connected between terminals AtoN and BtoN to control the bipolar transistors. 
     The output voltage of terminals A and B in FIG. 2 is a differential square wave voltage, the peak-to-peak value of the voltage being the voltage between terminals P and N. If external capacitors are used for connecting terminals A and B to a third potential, the output generated is a differential alternating current I=fC*V(P−N) where f represents the switching frequency of the switches, C represents the value of the external capacitor and V(P−N) the voltage between terminals P and N. This alternating current can be rectified using another microcircuit of FIG. 2, for example. FIG. 3 illustrates this alternative embodiment of the invention, where the voltage Uin in the first potential between terminals P 1  and N 1  is converted to output voltage Uout of the second potential. 
     In FIG. 3, the voltage to be measured Uin is supplied to terminals P ad N of a first microcircuit X 1 . The control signal for terminals AtoN and BtoN of microcircuits X 1 , X 2  and X 3  is obtained from clocks CL 1  and CL 2 , the second terminal of which are connected to circuit potential  3 . VDD represents the operating voltage of the circuit. 
     The output currents of terminals A and B of microcircuits X 1 , X 2  and X 3  are converted to voltage in sC resistors C 41 , C 42 , C 43  and C 44 . The conductance (g) values of the resistors are defined as the product of the switching frequency (f) of the switches and the values of the capacitors concerned (g=C*f). There is no direct current flowing through the resistors. 
     The function of resistors R 34  and R 35  and capacitors C 34  and C 36  is to stabilize the operation of microcircuit X 4 . 
     The output voltage of the circuit can be supplied to a load depicted in FIG. 3 by capacitor C 35  and resistor R 36 . 
     In FIG. 3, power is supplied to microcircuit X 4  through capacitors C 31  and C 32 . Diodes D 41 -D 43  rectify the currents flowing through capacitors C 31  and C 32 . C 33  acts as a filter capacitor for the operating voltage. 
     The voltage amplification in FIG. 3 is Uout Uin=(C 41 +C 42 )/(C 43 +C 44 ). If the amplification is defined as one, the input voltage to be measured Uin is obtained directly as the value of output voltage Uout. 
     It is apparent to a person skilled in the art that as technology advances, the basic idea of the invention can be implemented in various ways. The invention and its embodiments are therefore not restricted to the above described examples but they may vary within the scope of the claims.