Abstract:
The invention relates to a three-dimensionally controlled liquid crystal matrix display having a low number of connections and transistors to its control process. The display comprises a first insulating wall covered with electrode rows, each formed from n aligned row strips, a second insulating wall covered with electrode columns, each formed by r aligned column strips, and a liquid crystal layer inserted between the electrode columns and the electrode rows. The row strips and the column strips are respectively grouped into p first and second packets of s parallel row strips, and of t parallel column strips, with p=n×r, s=m×n/p and t=q×r/p. Each row strip and each column strip is associated respectively with a transistor serving to interconnect the row strips and interconnect the column strips to form s row connections, t column connections, and p packet connections.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a three-dimensionally controlled liquid crystal matrix display and to the control process for the same. 
     The invention more particularly applies to the field of optoelectronics and especially to the control of liquid crystal matrix displays, e.g. used as converters of electrical information into optical information, for the real time processing of optical images and for analogue display purposes. 
     FIG. 1a shows a cross-bar liquid crystal matrix display according to the prior art and FIG. 1b is an exploded view thereof. FIG. 1a shows two facing insulating walls 1, 3, which are kept spaced by a sealing joint 2 arranged on the peripheries thereof and between which is introduced a liquid crystal layer 4. 
     Over the inner face of wall 1 is distributed a first group of m parallel electrode rows, designated L i , with i being an integer such that 1≦i≦m, constituted by continuous conductive strips, whilst on the inner face of the other wall 3 is distributed a second group of q parallel electrode columns, designated C j , with j being an integer such that 1≦j≦q, whilst also being formed by conductive strips, the m and q columns of electrodes crossing one another. These m electrode rows and q electrode columns carry electrical signals, respectively row signal and column signals suitable for the excitation of the liquid crystal. The signals are produced in per se known manner by a power supply 6. 
     FIG. 1b shows an exploded view of the display with a first group of m electrode rows, designated L i  and a second group of q electrode columns, designated C j , which are respectively distributed over walls 1 and 3. As the q electrode columns and m electrode lines cross one another, a liquid crystal zone I ij  is defined by the overlap region of row L 1  and the column C j . Each zone I ij  defines and elementary image point of the display means, so that the latter comprises mxq image points distributed in matrix-like manner. 
     In general terms, to the m rows and q columns of electrodes are applied alternating electric signals in phase or in phase opposition, the amplitude of the row signals slightly exceeding that of the column signals. 
     When the signal of row L i  and the signal of column C j  are in phase, the resulting signal is equal to the difference of the amplitudes in absolute value of the row signal and the column signal. The resulting signal is then below the threshold voltage V s  of the liquid crystal, corresponding to the minimum voltage necessary for exciting the liquid crystal. In addition, in the overlap zone I ij , as the liquid crystal is not excited, a black point is displayed. Conversely when the signal of row L i  and the signal of column C j  are in phase opposition, the resulting signal has an amplitude equal to the sum of the amplitudes in absolute value of the row signal and the column signal. The resulting signal produces an electric field in the overlap zone I ij , which generally brings about a collective orientation of molecules in said zone and consequently a white display. 
     By utilizing the selective orientation of the molecules and the punctiform excitation of the liquid crystal, an image is made to appear on the complete cell. 
     According to another type of known matrix display (called active matrix display), a counter electrode is provided in one wall and the electrode walls and columns are provided on the other wall. 
     With the intersection of each row and each column is e.g. associated a switch, such as a thin film transistor connected to a point electrode and, which transmits to the corresponding zone I ij  defined by the overlapping of the point electrode and the counter-electrode, the signal resulting form the row signal applied to row L i  and the column signal applied to column C j . Thus, there are the same number of transistors as there are image points. 
     In the aforementioned matrix display, in order to display mxq points, use is consequently made of a large number of transistors mxq, as well as a large number of connections m+q, said connections corresponding to all the inputs of electrical signals on the m rows and the q columns of electrodes. 
     SUMMARY OF THE INVENTION 
     The object of the invention is to obviate these disadvantages by providing a display having a number of connections and transistors below those of the prior art means, without it being necessary to reduce the number of elementary image points. 
     More specifically the present invention relates to a liquid crystal matrix display comprising two facing insulating walls, respectively covered by a first group of m electrode rows and a second group of q electrode columns, said rows and columns crossing on another, a liquid crystal layer placed between the first and second groups, and means for applying electrical signals to the electrodes permitting the excitation of the liquid crystal, wherein each electrode of the first group is constituted by n small row strips, wherein each electrode of the second group is constituted by r small column strips, the small rows and the small columns being respectively grouped into p row packets and p column packets with p=n·reach row packet grouping s small parallel rows and each column packet grouping t small parallel columns with s=m·n/p and t=q·r/p, an image point I ijk  being defined by the region corresponding to the superimposing of a small row l i  of a row packet P k  and a small column c j  of the corresponding packet T k , i, j, and k being integers such that 1≦i≦s, 1≦j≦t and 1≦k≦p, wherein each small row is associated with a switch serving on the one hand to interconnect the n small rows of an electrode row and interconnect the electrode rows in order to form s row connections and on the other hand to interconnect the s small rows of each row packet P k  in order to form p first packet connections and wherein each small column is associated with a switch serving on the one hand to interconnect the r small columns of an electrode column and interconnect the electrode columns in order to form t column connections and on the other hand interconnect the t small columns of each column packet T k  in order to form p second packet connections, the row packet P k  and the column packet T k  being interconnected by the first and second corresponding packet connections. 
     According to an embodiment of the display, the electrode rows (L a ), (L 2s+1-a ), (L 2s+a ), (L 4s+1-a ) and so on are interconnected to form s row connections and the electrode columns (C b ), (C 2t+1-b ), (C 2t+b ), (C 4t+1-b ) and so on are interconnected to form t column connections, a and b being integers such that 1≦a≦m and 1≦b≦q. 
     According to another embodiment of the display, the electrode rows (L a ), (L a+s ), (L a+2s ), (L a+3s ) and so on are interconnected to form s row connections and the electrode column (C b ), (C b+t ), (C b+2t ), (C b+3t ) and so on are interconnected to form t column connections, a and b being integers such that 1≦a≦m and 1≦b≦q. 
     According to a preferred embodiment of the display, the switches are thin film transistors. 
     The invention also relates to a process for the control of a display according to the invention, wherein there is a continuous application to the t column connections of cyclic electric signals of cycle T with polarity reversal for each half-cycle T/2, said column signals being alternately positive and then negative on each half-cycle T/2, applying to the s row connections cyclic pulse-type electric signals of cycle T with polarity reversal for each half-cycle T/2, each row signal being non-zero during a row time T L  =T/(2·s), all the row times being distributed over a half-cycle T/2, and applying to p packet connections cyclic pulse-type electric signals of cycle T L , each packet signal being non-zero during a time T C  =T L  /p, all the times T C  being distributed over a time T L , T C  corresponding to the charging time of a switch. 
     According to a preferred embodiment of this process, the row signals and the column signals are either in phase or in phase opposition. 
     According to another preferred embodiment of the process, with the switch being a transistor, the packet signals either select the conductive state, or the non-conductive state of said transistors associated with the packet connections. 
     According to another embodiment of the process, the electrical signals applied are square-wave signals. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention is described in greater detail hereinafter relative to non-limitative embodiments and the attached drawings, wherein show: 
     FIGS. 1a and 1b, already described, in section and in exploded view a cross-bar matrix display according to the prior art. 
     FIG. 2 diagrammatically and in an exploded view an embodiment of a matrix display according to the invention. 
     FIG. 3 the timing diagram of the different signals applied to the different connections of the display of FIG. 2, as well as examples of the resulting signals at the corresponding image points. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 2 shows an embodiment of a matrix display according to the invention. The present display, like those of the prior art (FIG. 1), has two facing walls 1, 3, respectively covered by a first group of m electrode rows, designated L a  and a second group of q electrode columns designated C b , a and b being integers such that 1≦a≦m and 1≦b≦q. A liquid crystal layer 4 is placed between the two groups of electrodes. 
     According to the invention, the first group of m electrode rows is constituted by discontinuous conductive strips, each formed by n small row strips 5, 7, 9. In the same way the second group of q electrode columns is constituted by discontinuous conductive strips, each formed by r small column strips 11, 13. In this way m·n small rows and q·r small columns are obtained. All the small rows and small columns are respectively grouped into p row packets and p column packets with p=n·r arranged in matrix-like manner. 
     In the example of FIG. 2, m=10, n=3, q=18, and r=2, so that there are 30 small rows and 36 small columns grouped into p=6 packets. 
     Each row packet, designated P k  is therefore constituted by s small rows, designated l i , whilst each column packet, designated T k , is constituted by t small columns, designated c j , with s=m·n/p and t=q·r/p i, j and k being integers such that 1≦i≦s, 1≦j≦t and 1≦k≦p. In the example of FIG. 2, we therefore obtain s=5 and t=6. 
     With such a display, an image point I ijk  is defined by the overlap region between a small row l i  of a row packet P k  and a small column c j  of the corresponding column packet T k . 
     In order to control said display means with each small row l i  and with each small column c j  is respectively associated a switch 15, 17, such as a thin film transistor, connected to each small row l i  and to each small column c j  by the drain (or source) thereof. The transistors 15 associated with the small rows, designated l i , thus permit via their source (or their drain) to interconnect the n small rows constituting an electrode row and to interconnect the rows (L a ), (L a+s ), (L a+2s ) etc or the rows (L a ), (L 2s+1-a ), (L 4s+1-a ), etc, as in the example of the drawing, in order to form s row connections, designated X i . Thus, in the example of FIG. 2, row L i  is connected to row L 10 , row L 2  to row L 9  and so on, thus forming 5 row connections. 
     By means of their gate, transistors 15 also make it possible to interconnect the s small rows of each row packet P k  to form p first packet connections, designated Z k , p being equal to 6 in the case of the drawing. 
     The transistors 17 associated with the small columns, designated c j , make it possible via their source (or their drain), to interconnect the r small columns forming an electrode column and to interconnect the columns (C b ), (C b+t ), (C b+2t ); etc or the columns (C b ), (C 2t+1-b ), (C 2t+b ), (C 4t+1-b ), etc, as in the example of the drawing, to form t column connections, designated Y j . 
     Thus, FIG. 2 shows column C 1  connected to column C 12 , itself connected to column C 13 , column C 2  connected to column C 11 , itself connected to column C 14  and so in this way t=6 column connections Y j  are obtained. 
     By means of their gate, transistor 17 also make it possible to interconnect the t small columns of each column packet T k  to form p second packet connections, designated Z k . 
     The row packet P k  and the column packet T k  are interconnected by first and second corresponding packet connections to form p packet connections, designated Z k . 
     In the above description, two connecting modes of the electrode rows and electrode columns have been given for forming respectively s row connections and t column connections, but any other connecting mode making it possible to obtain s row connections and t column connections can be envisaged without passing beyond the scope of the invention. Thus, there are s row connections, designated X i , t column connections, designated Y j  and p packet connections, designated Z k , i, j and k being integers such that 1≦i≦s, 1≦j≦t and 1≦k≦p, with s=5, t=6 and p=6 in the present example. 
     Each overlap zone between the small row strip, l i  of a packet P k  and the small column strip C j  of the corresponding packet T k  defines an point I ijk . The signal which is seen by this image point consequently results from the superimposing of a signal applied to the corresponding row connection X i , called the row signal F i , a signal applied to the corresponding column connection Y j , called column signal G j  and a signal applied to the corresponding packet connection Z k , called packet signal H k . The signal resulting at image point I ijk  will be designated R ijk . 
     The control of such a display means consequently takes place by superimposing three types of different signals F i , G j , H k , said control type consequently being called three-dimensional control. 
     Row signal F i  is received by all the transistors 15 interconnected by their source (or their drain) and associated with the small row strips l i  corresponding thereto. The column signal G j  is received by all the transistors 17 interconnected by their source (or their drain) and associated with the corresponding small column strip c j . 
     Conversely, the packet signal H k  permits the passage or not of row signal F i  and column signal G j  on row l i  and column c j  respectively of packet P k , T k , which makes it possible to differentiate the different small row strips l i  of the p row packets P k  and the different small column strips c j  of the p column packets T k . Thus, transistors 15, 17 of the corresponding packets P k , T k  are selected at the same time and according to the signal applied are in the passing or conductive state, which is the case when they permit the passage of row signal F i  and column signal G j  respectively on row l i  of packet P k  and column c j  of the corresponding packet T k , or in the high impedance state and in this case they permit no signal to pass. 
     Thus, by means of a display according to the invention, on the basis of m rows, q columns and p packets respectively of s small rows and t small columns, we obtain m·q=s·t·p image points using only (s+t)·p transistors and s+t+p connections. 
     In the embodiment shown in FIG. 2, there are 10 rows (m), 18 columns (q) and 6 packets (p) of 5 small row (s) and 6 small columns (t) in each case. Thus, with such a display, it is possible to display 180 points using 66 transistors and 17 connections, whereas with a prior art display with 10 rows (m) and 18 columns (q), it is possible to display 180 points using 180 transistors (m·q) and 28 connections (m+q). 
     The transistors used here are preferably thin film transistors. 
     FIG. 3 shows the timing chart of the different control signals of the display of FIG. 2. It is possible to see two examples of column signals G 1  and G 2  applied to the column connections Y 1 , Y 2 , the row signals F 1 , F 2  . . . F 5  applied to the different row connections X 1 , X 2  . . . X 5 , the packet signals H 1 , H 2  . . . H 6  applied to the different packet connections Z 1 , Z 2  . . . Z 6 , as well as two examples of the resulting signals R 111  and R 121  at the corresponding image points I 111  and I 121 . 
     The row signals F 1 , F 2  . . . F 5  and column signals G 1 , G 2  . . . G 6  of the display are in particular square-wave signals of cycle T. The polarity of these signals is reversed for each half-cycle T/2 to protect the liquid crystal from direct currents and therefore extend its life. Thus, the mean value of these signals is 0 in each cycle. 
     Time T/2 corresponds to the periodic or cyclic refreshening of the information in the liquid crystal and consequently to maintaining the points excited. Time T/2 is generally approximately 20 ms. 
     The row signals F 1 , F 2  . . . F 5  are of the pulse type and are non-zero during a row time T L  equal to T/(2·s), s representing the number of row connections of the display means. The s row times are thus distributed over each half-cycle T/2, whereby a single non-zero pulse of a row signal corresponds to each time t L . Time T L  is the time necessary for storing the signal. In the described case s=5, the duration of the different signals F 1 , F 2  . . . F 5  being respectively T/10, i.e. approximately ms. 
     The column signal G j  is applied continuously and is either in phase with the row signal F i  in question and in this case the corresponding image point is black, or in phase opposition therewith and in this case the image point is white, with i and j in the display described being integers such that 1≦i≦5 and 1≦j≦6. In the example of FIG. 3, the signals G 1  and G 2  relative to the column connections Y 1  and Y 2  are identical, but of opposite polarity. As a function of the desired display, either the column signal G 1  or the column signal G 2  is delivered to the column connections Y 1  or Y 2 . 
     Packet signals H 1 , H 2  . . . H 6  control both the state of the transistors associated with the small row strips, designated l i , of a row packet P k  and those associated with the small column strip c j  of the corresponding column packet T k , with k being an integer such that 1≦k≦6. The packet signals are pulse-type square-wave signals. The duration of these signals, designated T C , is equal to T L  /p, p representing the number of packet connections Z k  and T L  the row time, so that T C  is equal to T/(2·s·p). Thus, time T C  corresponds to the charging time of a transistor. The p times T C  are distributed over each time T L , whereby to the latter corresponds a single non-zero pulse of a packet signal. In the case of the example described s=5 and p=6, so that T C  has a duration of approximately 0.66 ms. 
     During this time T C , a packet connection Z k  receives the pulse signal H k , the transistors 15 associated with the small row strips of packet P k  and the transistors 17 associated with the small column strips of packet T k  are in the passing state. Outside a pulse over the remainder of a row time T L , the packet signal H k  is zero, the transistors 15, 17 of the corresponding packets P k  and T k  are in the high impedance state, i.e. non-conductive. 
     When the transistors associated with a packet connection Z k  are in the passing or conductive state, they then allow the passage of row signals F i  on the corresponding rows l i  of packet P k  and column signals G j  on the corresponding column c j  of packet T j . The superimposing of these signals brings about the display or extinction of the corresponding image points, respectively when the signals F i  and G j  are in phase or in phase opposition. 
     When these transistors are non-conductive, no signal passes on the rows and columns of packets P k  and T k , the amplitude of the signal seen by the corresponding image points decreases slowly, following the elapsing of the storage time corresponding to the row time T L . 
     Thus, in the embodiment of FIG. 3, the signal R 111  corresponding to the superimposing of a row signal F 1  applied to the connection X 1 , of a column signal G 1  applied to connection Y 1  and a packet signal H 1  applied to connection Z 1  is zero at the start of a half-cycle T/2 during a row time T L , due to signals F 1  and G 1  being in phase during the passing state of the transistors associated with L 1  and column c 1  selected by the packet signal Z 1 . This zero signal then persists throughout the duration of the time T L  corresponding to the storage time. This results in the display of a black image point I 111 . 
     At the end of this first row time T L , as the row signal F 1  is zero for the remainder of time T/2, signal R 111  will be that of the column signal G 1  at the time when packet signal H 1  selects the passing state of the transistor corresponding to said small column strip c 1 . As the amplitude of the column signal is below the threshold voltage value of the liquid crystal, the black display at point I 111  will persist over the remainder of time T/2. This applies to each time T/2. 
     For the image point I 121  corresponding to the superimposing of a row signal F 1  applied to connection X 1 , of a column signal G 2  applied to connection Y 2  and a packet signal H 1  applied to connection Z 1 , at the start of a half-cycle T/2 for time T L , the resulting signal R 121  has an amplitude equal to the sum of the amplitudes in absolute value of the row signal F 1  and the column signal G 2 , due to the fact that these signals are in phase opposition during the passing state of the transistors, associated with row l 1  and column c 2  selected by the packet signal H 1 , so that there is a white point I 121 . As for point I 111 , as signal F 1  is zero for the remainder of the time T/2, signal R 121  is dependent on the column signal G 2  applied to connection Y 2  when the transistor of column c 2  is selected by packet signal H.sub. 1. The white display at point I 121  consequently persists over the remainder of time T/2 and this applies to each half-cycle T/2. 
     The three-dimensionally controlled display described hereinbefore, i.e. which uses three types of signals applied to three types of connections, makes it possible to have ratios between the number of displayed points (s·t·p) and the number of connection (s+t+p) and between the number of displayed points (s·t·p) and the number of transistors (s+t)·p used, which are superior to those of the known display means.