Abstract:
An operational amplifier circuit, including first and second differential amplifier circuits, at least one of which operates in response to an input signal within a voltage range between a high potential power supply and a low potential power supply,
       a level shifter unit outputting a level shifted signal generated by level shifting of output signals of the first and second differential amplifier circuits, and an output circuit including complementary output transistors series being coupled between the high potential power supply and the low potential power supply and inputting the level shifted signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of Japanese Patent Application No. 2006-318637 filed on Nov. 27, 2006, the entire contents of which are incorporated herein by reference. 
       BACKGROUND 
       [0002]    1. Field 
         [0003]    The embodiments discussed herein are each directed to an operational amplifier circuit. In recent years, in the field of semiconductor integrated circuit (IC) devices, technological development has rapidly progressed to achieve further reduction in power consumption and power supply voltage. For an operational amplifier circuit onto a semiconductor IC device, it is necessary that an allowable range of an input signal voltage is expanded to a power supply voltage range, and stabilized operation is secured. 
         [0004]    2. Description of the Related Art 
         [0005]      FIG. 1  illustrates a conventional operational amplifier circuit. The operational amplifier circuit has a configuration including first and second differential amplifier circuits,  1   a  and  1   b , which respectively receive input signals IN 1  and IN 2 , a level shifter unit  2 , which receives output signals of the respective differential amplifier circuits  1   a  and  1   b , and an output circuit  3  to be driven by the level shifter unit  2 . 
         [0006]    The first and second differential amplifier circuits  1   a  and  1   b  are provided in order to output an output signal OUT at a full amplitude from the output circuit  3  even in the event the respective input signals IN 1  and IN 2  approach either the level of a high electrical potential power supply Vcc or low electrical potential power supply Vss (the “electrical potential” hereinbelow will be simply referred to as “potential”). 
         [0007]    More specifically, when the input signals IN 1  and IN 2  approach the level of the power supply Vcc, the second differential amplifier circuit  1   b  does not substantially operate while the first differential amplifier circuit  1   a  operates and outputs an output signal of its own to the level shifter unit  2 . 
         [0008]    Alternatively, when the input signals IN 1  and IN 2  approach the level of the power supply Vss, the first differential amplifier circuit  1   a  does not substantially operate while the second differential amplifier circuit  1   b  operates and outputs an output signal of its own to the level shifter unit  2 . 
         [0009]    Still alternatively, when the input signals IN 1  and IN 2  are each at an intermediate level between the power supplies Vcc and Vss, the first and second differential amplifier circuits  1   a  and  1   b  both operate. 
         [0010]    In the level shifter unit  2 , nodes N 1  and N 22 , having level shifted the output signals of the first and second differential amplifier circuits  1   a  and  1   b , are connected to gates of a pull-up transistor T 1  and a pull-down transistor T 2  of the output circuit  3 . The level shifter unit  2  generates a certain level shifted voltage ΔV between the nodes N 1  and N 2 . 
         [0011]    The level shifted voltage ΔV preferably satisfies expression (1) below: 
         [0000]      Δ V=Vcc −( Vgsp 1 +Vgsn 2)  (1) 
         [0000]    Where Vgsp 1  is a gate-source voltage of the transistor T 1  of the level shifter unit  22 , when the output current of the output circuit  3  is an ideal value  12 ; and Vgsp 2  is a gate-source voltage of the transistor T 2  of the level shifter unit  22 , when the output current of the output circuit  3  is an ideal value  12 . 
         [0012]    More specifically, a current I 1  is represented by expression (2) below: 
         [0000]        I 1=( Vcc−Vgsn 3)/ R 1  (2) 
         [0000]    where Vgsn is a gate-source voltage of a transistor T 3  of the level shifter unit  2 . 
         [0013]    The level shifted voltage ΔV is represented as expression (3) below: 
         [0000]        ΔV=R 2 /R 1×( Vcc−Vgsn 3)  (3) 
         [0014]    Accordingly, it is preferable that expression (4) below is satisfied: 
         [0000]        Vcc −( Vgsp 1 +Vgsn 2)= R 2 /R 1×( Vcc−Vgsn 3)  (4) 
         [0000]    where R 1  and R 2  are resistors of the level shifter unit  2 . 
         [0015]    For example, a relational expression of the above takes the form of expression (5) shown below when, for example, Vcc=3V, Vgsp 1 =0.5V; and Vgsn 2 , Vgsn 3 =0.5V. 
         [0000]        Vcc −( Vgsp 1 +Vgsn 2)= R 2 /R 1×( Vcc−Vgsn 3) 
         [0000]      3.0V−(0.5V+0.5V)= R 2 /R 1×(3.0V−0.5V) 
         [0000]        R 2 /R 1=4/5  (5) 
         [0016]    The above is indicative that an ideal operation can be achieved when the design is carried out so that the ratio between the resistance values of resistors R 1  and R 2  of the level shifter unit  2  is 5:4. 
         [0017]    In addition, supposing that, given the ratio 5:4 between the resistance values of the resistors R 1  and R 2 , the state is changed in accordance with transistor threshold values changed due to process variations, such as: Vgsp 1 =0.8V; and Vgsn 2 , Vgsn 3 =0.8V. In this case, the relational expression takes the form of expression (6) given below. 
         [0000]        Vcc −( Vgsp 1 +Vgsn 2)=3.0V−(0.8V+0.8V)=1.4 V 
         [0000]        R 2 /R 1×( Vcc−Vgsn 3)=4/5×(3.0V−0.8V)=1.76V 
         [0000]        Vcc −( Vgsp 1 +Vgsn 2)≠ R 2 /R 1×( Vcc−Vgsn 3)  (6) 
         [0018]    Consequently, the level shifted voltage ΔV is offset from the ideal value due to an offset in the transistor threshold value, thereby leading to, for example, an increase in offset voltage error and/or an offset in the ideal value  12 . 
         [0019]    Thus, according to the operational amplifier circuit of  FIG. 1 , the level shifted voltage ΔV can be preliminarily set to the ideal value by setting the resistance values of the resistors R 1  and R 2 . When the transistor threshold value is offset due to process variations, however, the level shifted voltage ΔV is offset from the set value. 
         [0020]    Thus, one drawback of operational amplifier circuit is that, in the state where the power supply voltage is low, the offset in the level shifted voltage ΔV associated with the offset in the transistor threshold value, poses the problem of significantly reducing the accuracy of the output signal of the operational amplifier circuit. 
         [0021]    Japanese Laid-Open Publication No. 2002-43871 discloses an operational amplifier circuit, in which the sum of current values of bias currents for supply to first and second input differential pair is controlled to be constant, thereby suppressing fluctuations in characteristics due to process variations. 
         [0022]    Japanese Laid-Open Publication No. 2001-60832 discloses a configuration for reducing power consumption in the preceding circuit for driving respective transistors of a complementarily connected output circuit. 
         [0023]    Japanese Laid-Open Publication No. 06-85570 discloses an operational amplifier circuit apparatus including a P-top operational amplifier circuit and an N-top operational amplifier circuit, in which any one of the operational amplifier circuits is operated in accordance with the voltage level of an input signal. 
         [0024]    Other objects, features, and advantages will be apparent to persons of ordinary skill in the art from the following description of the invention and the accompanying drawings. 
       SUMMARY 
       [0025]    It is an aspect of the embodiments discussed herein to provide an operational amplifier circuit, including first and second differential amplifier circuits, at least one of which operates in response to an input signal within a voltage range between a high potential power supply and a low potential power supply, a level shifter unit outputting a level shifted signal generated by level shifting of output signals of the first and second differential amplifier circuits and an output circuit including complementary output transistors series being coupled between the high potential power supply and the low potential power supply and inputting the level shifted signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0026]      FIG. 1  illustrates a circuit diagram of a conventional example; 
           [0027]      FIG. 2  illustrates an embodiment of an operational amplifier circuit; 
           [0028]      FIG. 3  illustrates another embodiment of an operational amplifier circuit. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0029]      FIG. 2  illustrates an embodiment of an operational amplifier circuit. 
         [0030]    The operational amplifier circuit includes first and second differential amplifier circuits  1   a  and  1   b , a level shifter unit  11 , and an output circuit  3 . In the first differential amplifier circuit  1   a , input signals IN 1  and IN 22 , are respectively, are input to gates of N-channel MOS transistors T 11  and T 12 . The sources of transistors T 11  and T 12  are coupled to a drain of an N-channel MOS transistor T 13 . A source of the transistor T 13  is coupled to a low potential power supply Vss. 
         [0031]    A drain of the transistor T 11  is coupled to a drain of a P-channel MOS transistor T 14 . A drain of the transistor T 12  is coupled to a drain of a P-channel MOS transistor T 15 . The sources of transistors T 14  and T 15  are each coupled to a high potential power supply Vcc. The gates of transistors T 14  and T 15  are coupled to each other, and are further coupled to the drain of the transistor T 15 , whereby a current mirror circuit is configured. 
         [0032]    In the second differential amplifier circuit  1   b , the input signals IN 1  and IN 2  are input to the respective gates of P-channel MOS transistors T 16  and T 17 . The sources of transistors T 16  and T 17  are coupled to a drain of a P-channel MOS transistor T 18 . A source of the transistor T 18  is coupled to the high potential power supply Vcc. 
         [0033]    A drain of the transistor T 16  is coupled to a drain of an N-channel MOS transistor T 19 . A drain of the transistor T 17  is coupled to a drain of an N-channel MOS transistor T 20 . The sources of transistors T 19  and T 20  are coupled to the power supply Vss. The gates of transistors T 19  and T 20  are coupled to each other, and are further coupled to the drain of the transistor T 20 , whereby a current mirror circuit is configured. 
         [0034]    In the level shifter unit  11 , the sources of P-channel MOS transistors T 21  and T 22  are coupled to the power supply Vcc. The gates of transistors T 21  and T 22  are coupled to each other, and further coupled to a drain of the transistor T 21 , whereby a current mirror circuit is configured. 
         [0035]    The sources of N-channel MOS transistors T 23  and T 24  are coupled to the power supply Vss. The gates of the transistors T 23  and T 24  are coupled to each other and are further coupled to a drain of the transistor T 23 , whereby a current mirror circuit is configured. 
         [0036]    The drains of transistors T 21  and T 23  are coupled together via a resistor R 3 . The drains of transistors T 22  and T 24  are coupled together via a resistor R 4 . A high potential terminal of the resistor R 3  is coupled to a gate of the transistor T 13 , and a low potential terminal of the resistor R 3  is coupled to a gate of the transistor T 18 . A resistance value of the resistor R 3  and a resistance value of the resistor R 4  are set to the same value. 
         [0037]    The drains of transistors T 11  and T 14 , which are output terminals of the first differential amplifier circuit  1   a , are coupled to a drain (node N 1 ) of the transistor T 22  of the level shifter unit  11 , and are further coupled to a gate of a pull-up transistor T 1  (output transistor) of the output circuit  3 . 
         [0038]    The drains of transistors T 16  and T 19 , which drains are output terminals of the second differential amplifier circuit  1   b , are coupled to a drain (node N 2 ) of the transistor T 24  of the level shifter unit  11 , and are further coupled to a gate of a pull-down transistor T 2  (output transistor) of the output circuit  3 . 
         [0039]    In the level shifter unit  11 , the transistors T 21  and T 22  and the transistors T 23  and T 24  perform current mirror operations, and the same current I 3  flows to the resistors R 3  and R 4 . 
         [0040]    As such, a level shifted voltage ΔV, which is a voltage between two terminals of the resistor R 4 , i.e., a voltage between the nodes N 1  and N 2 , is represented by expression (7) below: 
         [0000]      Δ V=Vcc −( Vgsp 21 +Vgsn 23)  (7) 
         [0000]    where Vgsp 21  is a gate-source voltage of the transistor T 21 ; and Vgsp 23  is a gate-source voltage of the transistor T 23 . 
         [0041]    Accordingly, the gate-source voltage of each of the transistors T 21  and T 23  operates as a voltage regulating unit. 
         [0042]    In order to attain an ideal operation of the operational amplifier circuit, the level shifted voltage ΔV is set to satisfy expression (8) below. 
         [0000]        Vcc −( Vgsp 1 +Vgsn 2)= Vcc −( Vgsp 21+ Vgsn 23)  (8) 
         [0043]    The sizes of the respective output transistors T 1  and T 2  and the transistors T 21  to T 24  of the level shifter unit  11  are determined to satisfy expression (9) below, regardless of process variations. 
         [0000]      Vgsp1=Vgsp21, Vgsn2=Vgsn23  (9) 
         [0044]    Operation of the operational amplifier circuit thus configured will now be described herebelow. 
         [0045]    The first and second differential amplifier circuits  1   a  and  1   b  operate in accordance with the respective input signals IN 1  and IN 2 . The potentials of the respective nodes N 1  and N 2  vary, and an output signal OUT is output in accordance with the variations in the potentials. 
         [0046]    For example, when the potential of the input signal IN 1  rises relative to the input signal IN 2 , the potential of the node N 1  is reduced in accordance with the operation of the first differential amplifier circuit  1   a . The potential of the node N 2  is reduced in accordance with the operation of the second differential amplifier circuit  1   b . Then, the drain current of the output transistor T 1  is increased, and the drain current of the output transistor T 2  is reduced, whereby the voltage of the output signal OUT is increased. 
         [0047]    Alternatively, when the potential of the input signal IN 1  falls relative to the input signal IN 2 , the potential of the node N 1  is increased in accordance with the operation of the second differential amplifier circuit  1   b . Then, the potential of the node N 2  is increased in accordance with the operation of the second differential amplifier circuit  1   b . Consequently, the drain current of the output transistor T 1  is reduced, and the drain current of the output transistor T 2  is increased, whereby the voltage of the output signal OUT is reduced. 
         [0048]    Under such an operation, the level shifted voltage ΔV is maintained constant, regardless of variations in the potentials of the respective nodes N 1  and N 2 . 
         [0049]    When a potential difference between the input signal IN 1 , IN 2  and the level of the power supply Vcc becomes lower than or equal to a threshold value of the P-channel MOS transistor, the second differential amplifier circuit  1   b  becomes inoperable. In this case, the potentials of the nodes N 1  and N 2  are set in accordance with the output signal of the first differential amplifier circuit  1   a  in accordance with the potential difference between the nodes N 1  and N 2  and the operation of the level shifter unit  11 , so that the output signal OUT is output in accordance with the potential difference between the input signals IN 1  and IN 2 . In this event, the level shifted voltage ΔV is maintained toat the value indicated in expression (6). 
         [0050]    Alternatively, when a potential difference between the input signal IN 1 , IN 2  and the level of the high voltage power supply Vss becomes lower than or equal to a threshold value of the N-channel MOS transistor, the first differential amplifier circuit  1   a  becomes inoperable. In this case, the potentials of the nodes N 1  and N 2  are set in accordance with the output signal of the second differential amplifier circuit  1   b  in accordance with the potential difference between the input signals IN 1  and IN 2  and the operation of the level shifter unit  11 , so that the output signal OUT is output in accordance with the potentials of the nodes N 1  and N 2   
         [0051]    According to the operational amplifier circuit configured as described above, effects and advantages described below can be obtained. They are: 
         [0052]    (1) The output signal OUT can be normally output in response to the input signals IN 1  and IN 22 , respectively, in the ranges of the high potential power supply Vcc and the high voltage power supply Vss. 
         [0053]    (2) Even when the threshold values of the output transistors T 1  and T 2  and the threshold values of the transistors T 21  to T 24  of the level shifter unit  11  are fluctuated due to process variations, the operational amplifier circuit can beoperate at all times under the condition satisfying expression (8). 
         [0054]    (3) Regardless of process variations, the level shifted voltage ΔV between the nodes N 1  and N 2  can be maintained the ideal value, so that accuracy of the output signal OUT can be secured. 
         [0055]      FIG. 3  illustrates an operational amplifier circuit of another embodiment. The embodiment is configured in a manner that the MOS transistors of the above-described first embodiment are replaced with bipolar transistors. More specifically, the P-channel MOS transistors, respectively constituting the first and second differential amplifier circuits  1   a  and  1   b , level shifter unit  11 , and output circuit  3 , are replaced with PNP transistors, and the N-channel MOS transistors are respectively replaced with NPN transistors. 
         [0056]    According to the operational amplifier circuit thus configured, similar effects and advantages as those of the first embodiment can be obtained. Further, compared to the operational amplifier circuit configured with the MOS transistors, threshold value fluctuations due to process variations can be suppressed, and operation speeds can be improved even more. 
         [0057]    The embodiments described above can be effectuated with the following arrangements: 
         [0058]    The resistors R 3  and R 4  do not have to necessarily be set to the same resistance value; and 
         [0059]    The transistors T 1  and T 21  or the transistor T 2  and T 23  do not have to have the same size, inasmuch as the threshold value fluctuations due to process variations are identical to each other. 
         [0060]    While the present invention has been described in connection with preferred embodiments, it will be understood by those skilled in the art that variations and modifications of the preferred embodiments described above may be made without departing from the scope of the invention. Other embodiments will be apparent to those skilled in the art from a consideration of the specification or from a practice of the invention disclosed herein.