Abstract:
A circuit for generating a signal comprising a first transistor having a drain, a gate and a source. A second transistor having a drain, a source and a gate coupled to the gate of the first transistor to form a current mirror. A current source coupled to the source of the first transistor. A diode-connected transistor having a drain coupled to the source of the second transistor, a source and a gate that forms an output. A variable resistor having a first terminal coupled to the source of diode-connected transistor and a second terminal. A capacitor coupled to the second terminal of the variable resistor.

Description:
RELATED CASES 
       [0001]    The present application claims priority to U.S. Provisional application Ser. No. 61/578,214, “LOW-POWER PROGRAMMABLE OSCILLATOR &amp; RAMP GENERATOR,” filed Dec. 20, 2011, and which is hereby incorporated by reference for all purposes. 
     
    
     TECHNICAL FIELD 
       [0002]    The present disclosure relates to a programmable oscillator and ramp generator, and more specifically to a combined low-power programmable oscillator and ramp generator circuit. 
       BACKGROUND OF THE INVENTION 
       [0003]    Circuits for generating a ramp signal are known, as are circuits for generating a clock signal. These circuits are generally separate and discrete, and must be synchronous with each other to avoid misoperation associated systems and components. Synchronizing these two separate circuits requires complex and expensive circuitry. 
       SUMMARY OF THE INVENTION 
       [0004]    A circuit for generating a signal provided. The circuit includes a first transistor having a drain, a gate and a source, and a second transistor having a drain, a source and a gate coupled to the gate of the first transistor to form current mirror. A current source coupled to the source of the first transistor generates the current that is mirrored by the second transistor. A diode-connected transistor having a drain coupled to the source of the second transistor, a source and a gate that forms an output is coupled at its source to a first terminal of a variable resistor. A second terminal of the variable resistor is coupled to a capacitor, and a switch is used to short the capacitor when the voltage across the capacitor equals a reference voltage, so as to form a relaxation oscillator. 
         [0005]    Other systems, methods, features, and advantages of the present disclosure will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present disclosure, and be protected by the accompanying claims. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0006]    Aspect of the disclosure can be better understood with reference the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views, and in which: 
           [0007]      FIG. 1  is a diagram of a circuit for providing combined ramp generator and oscillator in accordance with an exemplary embodiment of the present disclosure; 
           [0008]      FIG. 2  is a switch control block diagram in accordance with an exemplary embodiment of the present disclosure; 
           [0009]      FIG. 3  is a diagram of exemplary waveforms of the circuits in  FIGS. 1 and 2  of the present disclosure; and 
           [0010]      FIG. 4  is a diagram of control circuitry in accordance with an exemplary embodiment of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0011]    In the description that follows, like parts are marked throughout the specification and drawings with the same reference numerals. The drawing figures might not be to scale and certain components can be shown in generalized or schematic form and identified by commercial designations in the interest of clarity and conciseness. 
         [0012]    Many pulse width modulation (PWM) based systems require both clock signals and sawtooth voltage waveform signals to function, such as those used in DC-DC converters and Class-D amplifiers. For optimum performance, the sawtooth waveform signals should be synchronous to the clock source signals without unnecessary jumps in the waveform. Also, because DC-DC converters and Class-D amplifiers are typically used in applications where power efficiency is of high importance, the clock source and sawtooth waveform generator should ideally consume very little current. Finally, these systems can further benefit from programmability on the sawtooth waveform offset, amplitude and frequency. 
         [0013]    Typically, the clock source and sawtooth waveform generator are separate circuits. The clock source can be taken from a suitable crystal oscillator, ring oscillator, phase locked loop, or her suitable circuit, and the clock source is also used as and input to synchronize a sawtooth waveform generator. Without calibration, the natural time constant of the sawtooth waveform generator will likely be different from that of the clock source, which can lead to discrepancies in the waveform that can adversely impact the performance of the system. 
         [0014]    The present disclosure combines relaxation oscillator circuit and sawtooth waveform generator circuit into a single circuit. The relaxation oscillator can be implemented in the above-mentioned manners, and a constant current source (either poly-resistor based or discrete-resistor based, depending on the frequency accuracy requirements) can be used to charge a capacitor linearly. A comparator can be used to measure the capacitor voltage and compare that voltage to a reference voltage. When the comparator output toggles, the capacitor is discharged (such as by using a constant current in the opposite direction, by using a low-resistance switch to discharge rapidly, depending on the desired shape, or in other suitable manners). 
         [0015]    The disclosed ramp generation output is linear and does not suffer from the body effect, which can be accomplished as follows. A reference voltage is generated by inserting a diode in series with the capacitor, and this circuit is used to drive an open-loop buffer in the form of a source follower. The output buffer can thus drive a voltage that matches that of the relaxation oscillator: a sawtooth waveform with little distortion. This buffer is capable of driving the voltage into a resistor to convert the voltage to a current, and the current offset and gain can be readily adjusted without affecting the oscillator. The resulting current can be driven into another resistor if a voltage sawtooth waveform is needed, or added to other currents, such as a sensing current if suitable. 
         [0016]    As used herein, “hardware” can include a combination of discrete component an integrated circuit, an application-specific integrated circuit, a field programmable gate array, or other suitable hardware. As used herein, “software” can include one or more objects, agents, threads, lines of code, subroutines, separate software applications, two or more lines code or other suitable software structures operating in two or more software applications or on two or more processors, or other suitable software structures. In one exemplary embodiment, software can include one or more lines of code or other suitable software structures operating in a general purpose software application, such as an operating system, and one or more lines of code or other suitable software structures operating in a specific purpose software application. 
         [0017]      FIG. 1  is a diagram of a circuit  100  for providing combined ramp generator and oscillator in accordance with an exemplary embodiment of the present disclosure. Circuit  100  provides a clock signal that is synchronized to a ramp signal in a single circuit. 
         [0018]    The first branch of circuit  100  includes power switch  104 , variable PFET  102 , PFET controller  154  and current source  106 . Power switch  104  disables operation of circuit  100 , and variable PFET  102  can be controlled to vary the amount of current flowing through current source  106 . In one exemplary embodiment, variable PFET  102  can include a plurality of transistors connected in parallel, where PFET controller  154  receives a control signal or control data input and converts the input to a series of bits that are used to turn predetermined combinations of the parallel transistors on or off. The number of transistors and associated current can be used to control the frequency of oscillation, as described herein. 
         [0019]    The second branch of circuit  100  provides a relaxation oscillator that includes PFET  108 , which is an array of transistors that forms a current mirror with variable PFET  102 , NFET  110 , programmable resistor  114 , capacitor  118  and switch  120 . Programmable resistor  114  forms a series resistor-capacitor circuit in conjunction with capacitor  118 , and can be varied by resistor controller  144  to select the effective clock frequency. In one exemplary embodiment, the programmable resistor can have resistance values that are coordinated with the value of capacitor  118 , where resistor controller  144  is configured to receive a three bat code that is used to set the clock frequency in the following increments: 
         [0000]                                                000   400 KHz           001   533 KHz           010   800 KHz           011   1600 KHz            100   200 KHz           101   229 KHz           110   267 KHz           111   320 KHz                        
In one exemplary embodiment, the three bit code can be used to control switches to reconfigure an array of resistors to be connected in series and parallel as needed to provide a total resistance value that results in the desired frequency, such as by determining the voltage rise time from the equation:
 
         [0000]        Vc ( t )−( AVDD−AVSS )(1 −e   −t/RC )
 
       Where 
       [0000]    
       
         
           
             Vc(t)=voltage across the capacitor as a function of time. 
             AVDD=high supply voltage 
             AVSS=low supply voltage 
             R=resistance in ohms 
             C=capacitance in farads
 
Other suitable frequency increments can also or alternatively be used. Resistor controller  144  can be implemented in hardware or a suitable combination of hardware and software, and can receive a control signal such as a data value or input signal level and can translate the control signal into a corresponding three bit code. Likewise, the frequency can be controlled using PFET controller  154 , where an increase in the amount of current for given resistance setting will result in a faster rise time for the voltage drop cross capacitor  118 .
 
           
         
       
     
         [0025]    Switch  120  is used to reset capacitor  11   e  when the voltage across it is equal to a reference voltage, and can be controlled by a signal generated by a comparator in switch controller  146  that compares the capacitor voltage to the reference voltage and which generates a signal to open switch  120 , or in other suitable manners. Switch  124  is normally closed, such that the gate voltage that is generated at NFET  110  is also generated at the gate of NFET  130 , but can be opened in order to disable the ramp output where suitable. Current sources  122  and  126  can be selected to provide currents of equal magnitude, so as to improve the operation speed of NFET  130  by biasing NFET  130  at a minimum level of operation to avoid time delays due to turning NFET  130  on. Adjustable resistor  128  is used to control the current magnitude through PFET  132  and NFET  130 , and is controlled by current controller  128 . In one exemplary embodiment, adjustable resistor  128  can be a plurality of resistors connected by switches that allow the resistors to be selectively configured in series or parallel combinations, where the switch settings are controlled with a suitable number of bits output by current controller  128 , and where current controller  128  receives a signal or data and converts the signal or data into a suitable binary output, or in other suitable manners. 
         [0026]    Variable PFET  134  is controlled by current gain adjust  150  to provide an adjustable current gain to the output at V RAMPOUT . In one exemplary embodiment, current gain adjust can control the number of parallel translators of variable PFET  134 , as to increase or decrease the current gain provided by variable PFET  134 . Variable PFET  136  is controlled by offset adjust  152  to adjust the voltage offset of V RAMPOUT . V RAMPOUT  is the ramp voltage output that is synchronized with the clock signa generated by the comparator in conjunction with the relaxation oscillator. ISENSE is used to detect an overcurrent condition in order to shut down circuit  100 , and switch  140  and load  142  are used to provide a test load, such that switch  140  is open during normal operation. 
         [0027]    In operation, resistor  14  of circuit  100  is adjusted to control the speed at which capacitor  118  charges. When the voltage across capacitor  118  reaches a predetermined reference voltage, switch  120  is opened to discharge capacitor  118 , which operates as a relaxation oscillator to generate a clock signal having a selectable frequency. In addition, the voltage across the series RC circuit is used to control an output driver that generates a ramp signal, such as for use in a DC to DC converter, a class D amplifier, or for other suitable purposes. The ramp signal of circuit  100  is synchronized to the clock signal, which prevents system misoperation. 
         [0028]      FIG. 2  is a switch control block diagram  200  in accordance with an exemplary embodiment of the present disclosure. Switch control block diagram  200  includes comparator  202 , which receives the ramp capacitor voltage and the reference voltage and generates an output when the ramp capacitor voltage equals the reference voltage. The output filtered by low pass filter  204  and is provided to latch  206 , which controls the minimum pulse width the output clock signal. In addition, the output of comparator  202  can be used to control switch  120  of circuit  100 , so as to open switch  120  to discharge capacitor  118 . 
         [0029]      FIG. 3  is a diagram of exemplary waveforms of the circuits in  FIGS. 1 and 2  of the present disclosure. SW_RESET is a signal that is used to drive switch  120  of  FIG. 1 , and it can be seen that VRAMP_CAP peaks at the magnitude of the reference voltage when SW_RESET transitions from low to high. As discussed above with respect to switch control block diagram  200 , SW_RESET can be used to control switch  120  or circuit  100 , which causes the voltage stored in capacitor  120  to discharge. The length of time that the SW_RESET signal stays high is function of the response time to open switch  120  and for the value of V RAMP     —     CAP  to change at the input to comparator  202 . The slope of the increase in VRAMP_CAP (and hence the frequency of the relaxation oscillator) is determined by the value of variable resistor  114 . The waveforms shown for COMPOUT, DGLITCH_OUT and DGLITCH 1 _OUT are related to the signals generated by the control circuitry as shown in  FIG. 4 . 
         [0030]      FIG. 4  is a diagram of control circuitry  400  in accordance with an exemplary embodiment of the present disclosure. Control circuitry  400  includes comparator  402 , which receives the voltage drop across the capacitor of the relaxation oscillator, such as capacitor  118  of  FIG. 1 , and which compares the voltage a reference voltage. The output is provided to dc-glitch low pass filter  404 , and both comparator  402  and low pas filter  404  can be deactivated by PDB_COMPDG 1  when an external clock signal is being provided. Multiplexer  412  is used to select between the external clock signal and the internal clock signal as a function of a clock select signal CLKSEL. The output from multiplexer  412  is provided to dc-glitch low pass filter  414  and latch  416 , which are connected to AND gates  418 ,  429  and  424  and multiplexer  422  as shown to generate a switch reset output SW_RESET and a clock output CLKOUT. 
         [0031]    In operation, control circuitry  400  allows an internal or external clock to be selected, and provides additional low pass filtering of the internal clock signal to prevent misoperation due to high frequency transients. 
         [0032]    It should be emphasized that the above-described embodiments are merely examples of possible implementations. Many variations and modifications may be made to the above-described embodiments without departing from the principles of the present disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the following claims.