Abstract:
An apparatus and method is provided for correcting data words resulting from a package fail within a memory array in which coded data is divided into a plurality of multi-bit packages of b bits each. The coded data comprises n-bit words with r error correcting code bits and n-r data bits. The invention is capable of correcting one package which has suffered at least one hard failure. The invention correcting exploits single error correcting (SEC)-and double error detecting (DED) codes, requiring no additional check bits, which give a syndrome when the data word has suffered an error coming from at least one error in a package.

Description:
TECHNICAL FIELD 
     This invention relates generally to error correction. In particular, it relates to the correction of a number of hard errors beyond the unextended capability of the error correction code being used. 
     BACKGROUND OF THE INVENTION 
     Error correcting codes (ECC) have been routinely used for fault tolerance in computer memory subsystems. The most commonly used codes are the single error correcting (SEC)-double error detecting (DED) codes capable of correcting all single errors and detecting all double errors in a code word. These SEC-DED codes are most effective in protecting memory data when the memory array chips are configured in one-bit-per-chip with respect to the ECC words. 
     As the size of computer memories has increased while the individual memory cells have become further miniaturized, there has resulted an unacceptable occurrence of bit errors in data stored in a memory. No longer can an occasional error be allowed to cause a program to stop operating or require replacement of a memory chip. These bit errors are of two general types, soft errors and hard errors. A soft error is a seemingly random inversion of stored data. This inversion is caused by occasional bursts of electrical noise and, in some cases, by atomic particles, the so-called alpha particle upset. The soft errors problem has increased as the individual cell sizes have been reduced so that noise levels represent relatively low amounts of power. 
     A hard error, in contrast, represents a permanent electrical failure of the memory chip, often restricted to particular memory locations but also sometimes associated with peripheral circuitry of the memory chip so that the entire chip can be affected. Naturally, designers of memory chips have strived to reduce the occurrence of both hard and soft errors in their chips. However, both types of errors have not been completely eliminated and, indeed, it is not believed that they can be eliminated. Reliability beyond a certain point can be bought only at the expense of reduced performance or increased cost. 
     An alternative to the above solution for both hard and soft errors has been the implementation of ECC in large computer memories. The fundamentals of error detecting and correcting are described by R. W. Hamming in a technical article titled “Error detecting and error correcting codes” appearing in the Bell System Technical Journal, Volume 26, No. 2, 1950 at pages 147-160. In one of the most popular Hamming codes, an 8 bit data word is encoded to a 13-bit word according to a selected Hamming code. The described code is classified as SEC-DED. However, since a SEC-DED Hamming code can correct only a single random error (either soft or hard) occurring in any byte, more elaborate error correcting codes have been developed and implemented. 
     In particular, a better procedure has been developed for dealing with hard errors in multi-bit packages. These errors are referred to as package errors and the error correction codes designed specifically for package errors will be called package codes. The codes rely upon the fact that multiple hard errors do not randomly occur across the entire field of the data word. Instead, multiple hard errors are confined to a sub-field of the data word, affecting up to all the bits associated with the memory package and defined by the outputs of the package. In the context of a 4M×4 memory chip, consisting of a 16 megabit memory chip adapted to have 4 data ports simultaneously accessible, such a code cannot correct any four errors occurring in 32 bits. However, the code can correct four-bit errors that occur in any one of eight 4-bit sub-fields. 
     Nonetheless, even such codes are not completely satisfactory. If the code is a SPC-DPD (single package correct/double package detect) code, then the code can correct any errors that occur in only one package and can detect, but not correct, errors occurring in two packages. Thus if one package has suffered a hard failure, the occurrence of any additional errors, either soft or hard, in the remaining packages means that the error condition can be detected but the errors cannot be corrected. The existence of one hard failure is the effective limit of correction provided by a SPC-DPD code. 
     U.S. Pat. No. 4,661,955 (&#39;955) discloses an extended error correcting device and method for SPC-DPD codes that is capable of correcting both a single soft error in one package and hard errors in another package. In the disclosed device and method, if the initial pass of the data through the error correction code indicates an uncorrected error, the data is complemented and restored in the memory and then reread. The reread data is recomplemented and again passed through the error correction code. The complementing, storing, retrieving, recomplementing, and ECC of the data is known as a “complement/recomplement” (comp/recomp) or an “invert and retry” procedure. If an uncorrected error persists after the comp/recomp, then a bit-by-bit comparison is performed between the originally read data and the retrieved complemented data to isolate the hard failure in the memory. The bits in the sub-field associated with the hard failure are sequentially changed and the changed data word is passed through the error correction code. A wrong combination is detected by the error correction code. The sub-field associated with the hard failure matches the originally stored data, in which case the error correction code can correct the remaining errors in the remaining sub-fields. However, the successive changes of the bits in the sub-field associated with the hard failure involve a long process of iterations. Moreover, this system has the disadvantage of involving a long process of bit by bit comparisons between the originally read data and the retrieved complemented ones, numerous compare circuits and latches, and a non-fixed length correcting sequence since the originally stored data in a sub-field associated with the hard fail can be any of the 16 different combinations. 
     U.S. Pat. No. 4,961,193 (&#39;193), like the aforementioned &#39;955, describes an extended error correcting device and method for SPC-DPD codes that is capable of correcting both a single soft error in one package and hard errors in another package. However, unlike the aforementioned &#39;955, the device and method described in &#39;193 does not use a bit-by-bit method. In the &#39;193 device and method, if the initial pass of the data through the error correction code indicates an uncorrected error, the syndrome of the data is stored and a complement/recomplement procedure is performed. If an uncorrected error persists after the comp/recomp procedure, the syndrome of the data is added to the syndrome of the complemented data. This sum is checked to see if it is a double package error (DPE) and, therefore, uncorrectable. If this sum is not a DPE, it is then matched to values in a table. Given the sum, the table provides the package to correct and the bits in error within the package. Using this data, the hard errors can be corrected. While this method avoids the use of a bit-by-bit process, it requires the use of a comp/recomp procedure and cannot be used with other processes known in the art, such as the read/write pattern test or the reference of data collected from past history. 
     SUMMARY OF THE INVENTION 
     In an embodiment of the present invention, a digital n-bit error correction-coded word includes a plurality of b-bit packages. The n-bit word is received from a data source having a faulty element, and an error correction code is performed on the n-bit word to correct a number of errors in the word. In addition to correcting the number of errors, the error correction code generates a syndrome for the word, and detects a number of errors in excess of the errors that it can correct. The position of the package in which the detected but uncorrected errors are located is then determined. Using the position of the package and the syndrome, an error pattern is determined. The errors in the n-bit word are then corrected using this pattern. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Referring now to the drawings wherein like elements are numbered alike in the several FIGURES: 
     FIG. 1 is a pictorial representation of memory array partitions; 
     FIG. 2 is a flow diagram illustrating the extended error correction of the present invention; 
     FIG. 3 is a parity check matrix of a (72, 64) code having 8 check bits and 64 data bits; and 
     FIGS. 4 (A and B) is a package error correction table for determining a package error pattern from a syndrome and package position. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 is a pictorial representation of a memory array  110  partitioned into N elements  112  as may be found in a computer memory. Each of the N elements  112  include an array of memory locations  114  with b-bits being simultaneously accessible. For example, each element  112  may comprise a 4M×4 memory chip, consisting of a 16 megabit memory chip adapted to have 4 data ports  116  simultaneously accessible for the read/write of four bits. The b-bits of each element  112  are a package (sub-field). The N sub fields combine to create a data word of n-bits. 
     A package error correction procedure of the present invention, generally referred to as  210 , is shown in FIG.  2 . In procedure  210 , a data word is fetched from an original memory location (data source). The fetched data are operated on by an error correcting code (ECC) in a block  212 . The ECC is capable of correcting all single errors and detecting all double errors. It is also capable of detecting all single package errors. The operation of an ECC is known to those familiar with the art. The result of the operation of the ECC is inspected in a block  216  to see if there is no error or an uncorrected error (UE). If there is no error or the ECC can correct the error, the corrected data is delivered at  218 . In the alternative, if an uncorrected error is found in block  216  it may be further operated on by subjecting the results to a comp/recomp procedure at a block  222 . FIG. 3 shows a typical parity check matrix of a (72, 64) SEC-DED code capable of detecting all single 4-bit package errors having 8 check bits and 64 data bits as may be used for an ECC in block  212 . 
     Referring again to FIG. 2, in the comp/recomp procedure of block  222  the fetched data are stored in an alternate memory location while a complement of the fetched data is stored back in the original memory location. The complemented data are retrieved from the original memory location, and recomplemented. The recomplemented data are then subjected to the ECC at a block  230 . If the cause of the original error was due to a soft error, the double inversion and the ECC will likely produce the correct data. If there is no indication of an uncorrected error after the ECC processing, then the corrected value is delivered at a block  228 . If, however, the ECC processing of the recomplemented data still produces an uncorrected error, then procedure  210  continues at a block  234 . In block  234 , the recomplemented data are compared to the originally fetched data stored in the alternate memory location. The recomplemented data should equal the originally fetched data because of the two intervening inversions. However, if the memory has suffered a hard failure such that one or more of the b-bit output values in the retrieved data are stuck either high or low, then the two data words will not be equal. If there is a hard error, the package error position, j, is identified at a block  234  from the comparison of the data. 
     While the described embodiment employs the comp/recomp method to detect which of the N memory partitions (elements) has failed due to a hard error, it will be understood by one skilled in the art that any similar procedure can be used. For example, this may include an actual read/write pattern test, or data collected from past history. 
     If the data are reported as UE in block  226 , then S, the error syndrome, from the original data at block  212  and j, the package error position from block  234 , are used in a block  240  as look up values in the package error correction (PEC) table shown in FIGS. 4A and 4B. As is shown in FIGS. 4A and 4B, the PEC table includes a plurality of unique package position and syndrome combinations. Each unique combination has a corresponding error pattern. For example in FIG. 4A, the combination of a syndrome 11100110 and a package position  7  results in an error pattern of 0001 indicating a failure of bit position  4 . 
     Referring again to FIG. 2, if the unique package position is found in the PEC table at block  240 , the errors in the original fetched data are corrected by flipping the data bits at the package position j according to the error pattern found. The corrected data are subjected to the ECC at a block  242 . If there is no indication of an uncorrected error after the ECC processing in block  242 , then the corrected value is delivered at block  248 . If the S and j jointly are not an entry in the PEC table then the errors are reported as unrecoverable data at a block  244 . 
     All single package errors are correctable using this scheme. The scheme will not improperly correct any double package errors in package j and another package, i. The errors will be detected as UE. 
     The disclosed scheme relies on a procedure to determine which of the N memory partitions has failed. This is either a comp/recomp procedure, an actual read/write pattern test, or data collected from past history. Determination of the failed memory partition is separated from determination of the failed bit pattern so one may use any conceivable approach to determine which of the N memory partitions has failed. 
     The present invention can be embodied in the form of computer-implemented processes and apparatuses for practicing those processes. The present invention can also be embodied in the form of computer program code containing instructions embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, or any other computer-readable storage medium, wherein, when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing the invention. The present invention can also be embodied in the form of computer program code, for example, whether stored in a storage medium, loaded into and/or executed by a computer, or transmitted over some transmission medium, such as over electrical wiring or cabling, through fiber optics, or via electromagnetic radiation, wherein, when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing the invention. When implemented on a general-purpose microprocessor, the computer program code segments configure the microprocessor to create specific logic circuits. 
     While a preferred embodiment has been shown and described, various modifications and substitutions may be made thereto without departing from the spirit and scope of the invention. Accordingly, it is to be understood that the present invention has been described by way of illustration and not limitation.