Abstract:
A video display apparatus for pictures from broadcast sources having standard or high definition, which may also display computer generated images. To display this range of sources a horizontal frequency signal generator is selectably operable at a plurality of frequencies. The generator comprises an oscillator controlled for synchronized oscillation at a plurality of horizontal frequencies. A source of synchronizing pulses is coupled to an input of a phase detector which has another input coupled to the oscillator. The phase detector generates an output signal representative of a phase difference between the inputs. A processor is coupled to the phase detector for processing the output signal and generating a control signal for controlling the oscillator. The processor gain is controlled responsive to selected ones of the plurality of frequencies.

Description:
This invention relates generally to the field of horizontal scanning systems for video display apparatus and in particular to the synchronization and generation of horizontal rate signals in systems operable at multiple horizontal scanning frequencies. 
     BACKGROUND 
     In a video display apparatus, scanning circuits are synchronized to a synchronizing component or sync derived from the input video signal. Hence, a video display apparatus which is operable at multiple horizontal scanning frequencies must be capable of synchronizing to a standard definition NTSC signal horizontal scanning frequency of nominally 15.734 kHz or to a high definition, Advanced Television Standards Committee, ATSC, signal having horizontal scanning frequency of nominally 33,670 kHz with 1080 active lines and interlaced scanning (1080I ). In addition to synchronizing to broadcast video signals, the apparatus may be required to display computer generated non-broadcast video signals, such as, for example, a super video graphics adapter signal or SVGA, having a horizontal frequency of 37,880 kHz. 
     Horizontal frequency oscillators employing phase locked loop control are widely known and used in video display apparatus. Dual and triple phase locked loops are also known and used to provide functional separation between potentially conflicting requirements of synchronization and scanning waveform generation. In a dual loop configuration, a first loop may be a conventional phase locked loop in which a voltage controlled oscillator output, or an output divided therefrom is compared with horizontal synchronizing pulses derived from the video signal to be displayed. The second phase locked loop, which for example, operates at the same frequency, compares the oscillator output from the first loop with a horizontal rate pulse, for example, a retrace pulse voltage derived from or representative of defection current flow. The error voltage from the second phase comparison is used to generate a width modulated pulse signal which determines the initiation of the deflection output device turn off, and subsequently, retrace initiation, or the phase of each line within the period of a vertical scan. 
     The response of the first phase locked loop may be optimized for fringe area reception of broadcast video signals suffering poor signal to noise ratios. Such signals suggest that the response of the first phase locked loop is relatively slow. Accordingly, the first loop may have a narrow bandwidth to optimize phase jitter reduction. However, since a video display apparatus is required to be operable with signals from a variety sources and with differing horizontal frequencies. The response of the first phase locked loop represents a compromise between a narrow bandwidth for minimized phase jitter and a wide bandwidth, fast loop response capable of rapid phase recovery. For example, a narrow bandwidth loop is suited to synchronization by low noise, non-broadcast computer generated signals, whereas and wide bandwidth, fast loop response, capable of rapid phase recovery is required for synchronization of video cassette recorder (VCR) replay signals where abrupt changes in horizontal sync. pulse phase, by as much as 10 microseconds may occurring between the beginning and end of the vertical banking interval. Hence tradeoffs in respective loop responses may be made to provide adequate weak signal performance without significant overall degradation of receiver performance. The second phase locked loop generally has a faster loop response. Accordingly, the second phase locked loop may have a wider bandwidth allowing it to track variations in the defection current due to horizontal output transistor storage time variations, or high voltage transformer tuning effects. Such tight tracking yields a straight, non-bending raster largely independent of beam current loading. 
     The use of voltage controlled oscillators for horizontal frequency signal generation is well known. It is known to employ an oscillator operating at a multiple of the input horizontal sync. frequency and to achieve synchronization by means of a down counter with a selectable divide by two stage. However, when input signals have non-integer horizontal scanning frequencies, simple halving or doubling of an oscillator count down ratio cannot readily provide synchronization. In addition, input signals that are subject to widely differing distortions necessitate differing processing characteristics to provide optimized display performance. 
     SUMMARY OF THE INVENTION 
     The conflicting requirements of horizontal oscillator synchronization with multiple frequencies and sync signals from differing sources are advantageously resolved by an inventive arrangement. A horizontal frequency signal generator is selectably operable at a plurality of frequencies. The generator comprises an oscillator controlled for synchronized oscillation at a plurality of horizontal frequencies. A source of synchronizing pulses is coupled to an input of a phase detector which has another input coupled to the oscillator. The phase detector generates an output signal representative of a phase difference between the inputs. A processor is coupled to the phase detector for processing the output signal and generating a control signal for controlling the oscillator. The processor gain is controlled responsive to selected ones of the plurality of frequencies. In a further inventive arrangement a synchronizing circuit comprises a voltage controlled oscillator generating a horizontal frequency signal at a plurality of frequencies. A synchronizing means synchronizes the voltage controlled oscillator to a source of horizontal synchronizing pulses. An active low pass filter is coupled to the synchronizing means for filtering a voltage from the synchronizing means for coupling to synchronize the voltage controlled oscillator. The active filter bandwidth is changed responsive to operation at one of the plurality of frequencies. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of an exemplary horizontal frequency oscillator employing three phase locked loops with various inventive arrangements. 
     FIG. 2 is a schematic diagram of part of FIG.  1  and shows an inventive switched active filter. 
     FIG. 3 shows a voltage controlled oscillator including inventive features which form part of FIG.  1 . 
     FIG. 4 is a schematic diagram of the inventive switching interlock which forms of part of FIG.  1 . 
     FIG. 5A is a plot illustrating the gain versus frequency characteristic of the inventive switched active filter of FIG.  2 . 
     FIG. 5B is a plot illustrating the phase versus frequency characteristic of the inventive switched active filter of FIG.  2 . 
    
    
     DETAILED DESCRIPTION 
     A horizontal frequency oscillator and deflection amplifier employing three phase locked loops and operable at a plurality of frequencies is shown in FIG.  1 . In a first phase locked loop  10 , an input video display signal, for example a standard definition NTSC signal is coupled to a sync separator, SS, where a horizontal synchronizing signal component is separated. A voltage controlled oscillator has a frequency of 32 times an NTSC horizontal frequency, 1Fh, and is divided by 32 in a counter, depicted as, ÷32. The divided oscillator signal is coupled as one input to a phase detector PD, with the second input coupled to the separated sync component. The resulting phase error between the divided oscillator signal and the separated syncs is coupled from phase detector, PD, to synchronize the 32Fh voltage controlled oscillator. The functional elements of PLL  10 , form part of a bus controlled integrated circuit, for example type TA 1276 . The standard definition horizontal sync component from PLL 10  is coupled to a sync source selector switch SW 15  which provides selection between a plurality of synchronizing signals coupled as input sources to synchronize second and third controlled horizontal oscillator loops,  100  and  410  respectively. Selector switch SW 15  is depicted with three exemplary sync sources, namely a standard definition NTSC sync signal, a high definition sync signal, for example ATSC 1080I, and a computer generated SVGA sync signal, however, sync selection for horizontal oscillator synchronization signal is not limited to these examples. Sync switch SW 15  is controlled by switching signal  15   a  which is generated by microcontroller  800  in response to a user control command, for example, as generated by a remote control transmitter RC, which communicates by wireless means IR to receiver IRR,  801  which inputs the remote control data to microcontroller  800 . Remote control RC allows display signal source selection, for example, changing broadcast TV channels between HD and SD broadcasts or viewing a computer program with selectable display resolution. 
     The three phase locked oscillators depicted in FIG. 1 are advantageously controlled to provide optimized performance, not only with input signals of differing frequencies but also with signals subject to timing perturbations. During the display of NTSC signals, loops  10 ,  100  and  410  are utilized. However NTSC signals may originate from a broadcast source or a VCR. The latter source may be subject to sync phase perturbations, thus such signal disturbances are advantageous accommodated within PLL  100  by means of controlled selection of low pass filter characteristic. Selection of high definition signal inputs, for example ATSC or SVGA cause PLL 10  to be bypassed reducing the sync system to two controlled loops, for example PLL 100  and PLL 410 . Thus microcontroller  800  is required to control input video display selection responsive to user commands, to control sync source selection responsive to the display selection, control the oscillator frequency, the oscillator divider and phase locked oscillator low pass filter characteristics. 
     The selected synchronizing signal  5 , from switch  15 , is coupled to an input of phase detector  50  to facilitate synchronization of the second phase locked loop  100 . A second input to phase detector  50  is supplied with signal  401 , derived by division of voltage controlled oscillator signal  301 . The resulting phase error signal  11  is low pass filtered and applied to control VCO  300  thus achieving synchronism with the input video display signal horizontal sync. The third phase locked loop  410  compares a signal from voltage controlled oscillator VCO  300  with a scanning related signal Hrt, for example a horizontal scan derived pulse resulting from a scanning current generated by a scanning amplifier  500 . 
     The center frequency of horizontal oscillator  300  is determined by means of control bus  420 , for example an I 2 C bus, which advantageously transmits data words which independently change the oscillator frequency and the low pass filter characteristics. In addition an advantageous protection circuit  600  prevents circuitry damage resulting from accidental, erroneous and undesired switching of divide by two counter  415 A by means of an electronic interlock. 
     Operation of the second and third horizontal oscillator loops and scanning amplifier of FIG. 1 is as follows. A horizontal sync signal  5 , depicted as an exemplary positive pulse, is selected by switch  15  from either PLL 10  or sync signals derived from a plurality of input display signals. Synchronizing signal  5  is applied to a phase detector  50  where it is compared with a horizontal rate signal  401  produced by division of line locked clock signal LLC,  301  from voltage controlled oscillator, VCO  300 . Block  400  represents an exemplary deflection processing integrated circuit IC  400 , for example type TDA9151. Integrated circuit  400  is bus controlled, for example by I 2 C bus  420 , and also includes a phase detector PLL 3 , and dividers  415  and  415 A. Divider  415 A is controlled by signal  402 , to provide division ratios of  432  and  864  respectively and thereby produce horizontal rate signals in two bands of frequencies, nominally 1Fh and 2Fh. Control signal  402  is coupled to switch  412  which inserts or bypasses divider  415 A, to provide two division ratios. Thus voltage controlled oscillator, VCO  300  operates only in a band of frequencies about 13.6 MHz, but is synchronized to horizontal frequencies differing by more than 2:1. 
     Examples of such non-integer related horizontal frequencies are NTSC signals where the horizontal frequency, represented by 1Fh, is 15.734 kHz and an ATSC 1080I signal with a horizontal frequency, represented relative to the NTSC signal as 2.14Fh, or 33.670 kHz. During the display of NTSC derived images, switch  412  selects divider  415 A which provides a division ratio of 864:1 yielding a frequency nominally that of the NTSC horizontal frequency 1Fh. Similarly for the display of images with horizontal frequencies of 2Fh or greater, for example an ATSC 1080I signal, switch  412  bypasses divider  415 A resulting in a division ratio of 432 which produces a horizontal frequency 2Fh, of 31.468 kHz, twice that of the NTSC standard. However, the ATSC 1080I horizontal frequency is not an integer multiple of the NTSC signal 1Fh and is actually 2.14 times the NTSC frequency. Thus to achieve synchronism with a 1080I input signal, or any non 2Fh sync rate, requires that the VCO frequency is changed to a frequency which when divided by 432 yields a frequency which may be synchronized with that of ATSC 1080I , or the selected input signal horizontal rate. 
     Divided line locked clock signal  401  is also coupled to synchronize the third loop  410  by means of phase detector PLL 3 , which compares clock signal  401  with a scan current derived pulse Hrt,  501 . An output signal  403  from PLL 3  is coupled via a driver stage  450  to a horizontal scanning stage  500  which generates a scan related current, for example, in a display device or an electron beam deflection coil. In addition to coupling to PLL 3 , scanning pulse Hrt is also coupled to protection circuit  600  and X-ray protection circuit  690 . 
     A protection circuit  600 , is shown in FIG. 4, which provides various protective functions related to the presence or absence of scanning current as indicated by detection of pulse Hrt,  501 . Circuit block  610 , detects the presence or absence of pulse  501  and generates an active low interrupt, {overscore (SCAN-LOSS INTR.)}  615 , which is coupled to a microcontroller, μ CONT.  800 . 
     A second protective function provided by circuit  600  is to inhibit horizontal frequency selection during the presence of pulse  501 , i.e. during scanning. Horizontal frequency selection data is coupled from microcontroller  800  by bus  420 . Data from the bus is demultiplexed and frequency selection data is digital to analog converted by DAC  700  to form switching signal  1 H_SW for coupling to circuit block  650 . The circuitry of block  650  allows the logical state of signal  1 H_SW to be coupled for frequency selection only if scan amplifier  500  is not generating pulses Hrt. Thus any change of horizontal frequency is inhibited or interlocked until the cessation of scan related pulses. 
     In block  610  of FIG. 4, scan derived pulses Hrt are rectified by diode D 1  and charge capacitor C 1  positively via a resistor R 2  towards the positive supply. The junction of resistor R 2  and capacitor C 1  are joined to the base of a PNP transistor Q 1  with the result that the positive charge developed across capacitor C 1  turns the transistor off when deflection related pulses are present. The emitter of transistor Q 1  is coupled to a positive voltage supply via a diode D 2  which prevents base emitter zenner breakdown and ensures that transistor Q 1  turns off when the pulse derived charge across capacitor C 1  is approximately 1.4 volts or less. The collector of transistor Q 1  is coupled to ground via series connected resistors R 3  and R 4 . The junction of the resistors is coupled to the base of an NPN transistor Q 2  which has the emitter grounded and the collector coupled via a resistor R 7  to form an open collector output signal. Thus when pulses Hrt are present transistor Q 1  is turned off, which in turn turns off transistor Q 2  rendering output signal  615 , scan loss interrupt, an open circuit. When scan related pulses are absent, for example as a consequence of a bus derived control function, circuit failure or X-ray protection, the positive charge developed across capacitor C 1  is dissipated via the series combination of resistors R 1  and R 2  thus allowing capacitor C 1  to charge towards ground potential. When the potential across capacitor C 1  is nominally 1.4 volts transistor Q 1  turns on with the collector terminal assuming the nominal potential at the cathode of diode D 2 . Thus this positive potential of about 7 volts at transistor Q 1  collector is applied via the potential divider formed by resistors R 3  and R 4  to the base of transistor Q 2 , which turns on taking the collector and output signal  615  to nominal ground potential. Signal  615  is an interrupt signal which, when low, signals microcontroller  800  that scanning current is absent in the exemplary display or coil. 
     The collector of transistor Q 1  of FIG. 4, is also coupled to circuit block  650  which advantageously allows or inhibits changes of horizontal frequency originated by the microcontroller and communicated via bus  420  to a digital to analog converter DAC  700 . The digital to analog converter  700  generates an analog control signal  1 H_SW which has two voltage values. When control signal  1 H_SW is nominally at zero volts (Vcesat), divide by two stage of processor  400  is bypassed and divider  415  divides the VCO output signal LLC,  301 , by  432  to produce a frequency in a higher band of horizontal frequencies equal to or greater than 2Fh. When control signal  1 H_SW is approximately 9.6 volts, divide by two stage  415 A is selected which produces a combined division of 864. Thus the VCO generated line locked clock LLC  301  is divided by 864 to produce a nominal frequency of 1Fh. The collector of transistor Q 1  is coupled via series connected resistors R 5  and R 6  which form a potential divider to ground. The junction of resistors R 5  and R 6  is coupled to the base of an NPN transistor Q 3  which has a grounded emitter. The collector of transistor Q 3  is connected to the positive supply via a load resistor R 8  and is also coupled to the base of an NPN transistor Q 4  via a resistor R 10 . The emitter of transistor Q 4  is coupled to the junction of a potential divider formed between the positive supply and ground where resistor R 9  is connected to the supply and resistor R 11  is connected to ground. Thus, the emitter of transistor Q 4  is biased at about 4 volts. Hence transistor Q 4  is turned on when the base voltage exceeds about 4.7 volts causing the collector to assume the nominal emitter potential. The collector of transistor Q 4  is connected directly to the junction of control signal  1 H_SW, and both the trigger input TR and threshold the threshold input of input TH of integrated circuit U 1 , for example I.C. type LMC  555 . Thus with both the trigger and threshold inputs clamped to 4 volts, changes in control signal  1 H_SW resulting from bus generated commands or erroneous signal pickup are prevented from changing the output state of I.C. U 1 . The threshold input of integrated circuit U 1  responds when voltage value of control signal  1 H_SW exceeds about 5.3 volts and results in the selection of a 1Fh scanning frequency. The trigger input of I.C. U 1  responds to a negative transition of control signal  1 H_SW and when the voltage value is less than approximately 2.6 volts results in the selection of a 2Fh scanning frequency. 
     Operation of circuit  650  is as follows. The presence of Hrt pulses coupled to circuit  610  turns off transistor Q 1  with the collector assuming a nominally ground potential via the parallel combination of series connected resistors R 3  and R 4 , and series connected resistors R 5  and R 6 . Thus, transistor Q 3  is also turned off with the collector assuming the nominal supply voltage via resistor R 8 . This positive potential is applied to the base of transistor Q 4  which turns on connecting the junction of control signal  1 H_SW and integrated circuit U 1  to a potential of about +4 volts. With +4 volts applied to both the trigger and threshold inputs of IC U 1 , U 1  is prevented from responding to changes of control signal  1 H_SW. Thus the current status of select horizontal frequency control signal  202 / 402  is maintained and cannot be changed whilst scanning pulses Hrt are present. Hence any change of horizontal frequency is prevented and failure of horizontal scanning stage  500  is prevented. 
     In the absence of scanning pulses transistor Q 1  turns on and the collector assumes the nominal supply potential. This positive potential is coupled via series resistors R 5  and R 6  and turns on transistor Q 3  which in turn, turns off transistor Q 4 . With transistor Q 4  off, the inhibit is removed from integrated circuit U 1 , thus for 1Fh operation signal  1 H_SW assumes a high voltage value, and IC U 1  output SEL. H. FREQ., assumes a low voltage value. Similarly when 2Fh operation is selected control signal  1 H_SW assumes a low voltage with U 1  output SEL. H. FREQ., assuming a high voltage value. T 
     The advantageous control of integrated circuit U 1  by means of pulse Hrt presence or absence is also utilized in circuit block  655  of FIGS. 1 and 4. In FIG. 4, a power supply switching command  2 H_VCC, from DAC  700 , is coupled to series connected resistors R 13  and R 14  which form a potential divider to ground. The junction of the resistors is connected to the base of a transistor Q 5  which has the emitter grounded and the collector connected as an open collector output to generate power supply control signal SEL.  1 H_VCC,  656 . The base of a transistor Q 5  is also connected to a discharge output of I.C. U 1 . The operation of circuit block  655  is as follows. A power supply switching command is generated by microcontroller  800  and transmitted by bus  420  to DAC  700  for demultiplexing and generation of control signal  2 H_VCC,  702 . When control signal  702  is high, for example, approximately +9.6 volts, transistor Q 5  is turned on and the collector, and output control signal SEL.  1 H_VCC,  656  assume a potential of nominally zero volts, (Vcesat) of transistor Q 5 . However, operation of transistor Q 5  is controlled by the discharge output circuitry of IC U 1  which prevents transistor Q 5  from inverting power supply control signal  2 H_VCC by clamping the base to nominal ground potential, Vcesat, of the discharge transistor of IC U 1 . Thus power supply switching is prevented and signal SEL.  1 H_VCC,  656  remains high, sustaining a 1Fh power supply condition, for example a lower operating voltage. The discharge circuitry of I.C. U 1  becomes inactive when the output circuitry of U 1  changes state, i.e. output signal SEL H. Freq. goes low in response to the selection of a 2Fh operating mode. Thus power supply selection for 2Fh and higher horizontal frequencies requires that a 2Fh scanning frequency is initially selected whilst scanning is inactive. 
     As has been described, the operating frequency of the second and third phase locked loops may be changed in the ratio of 2:1 by means of switching divider  415   a . However, to achieve synchronization of the VCO at other than harmonically related frequencies, for example with an ATSC 1080I frequency of 2.14Fh, or an SVGA signal with an 2.4Fh horizontal frequency, requires that the VCO of second phase locked loop is controlled to achieve a nominal horizontal frequency of between 2.14 and 2.4 times that of an NTSC horizontal frequency. In voltage controlled oscillator  300  an advantageous frequency setting DC potential, FREQ. SET,  302  determines an oscillator frequency which when divided generates a nominal horizontal frequency. The frequency setting DC potential is generated by a digital to analog converter and is applied to a voltage variable capacitor or varicap diode which forms part of the oscillator frequency determining network. The oscillator is synchronized to the input sync signal by means of a phase detector error signal, which is filtered and applied to an inductor which is part of the frequency determining network of VCO  300 . In simple terms, a frequency setting DC is applied to the varicap diode end of the series tuned network, with the phase error signal applied at the inductor end. Thus frequency and phase control signals are applied across the frequency determining tuned circuit. 
     Voltage controlled oscillator  300  is depicted in FIG.  1  and is shown in schematic form in FIG.  3 . Operation of the advantageously controlled oscillator  300  is as follows. Microcontroller  800  and a memory, (not shown), access and output frequency setting data via data bus  420 , for example an I 2 C bus, as illustrated in FIG.  1 . The I 2 C bus is connected to a digital sync processor  400 , to provide various control functions, and to a digital to analog converter  700  which separates and converts data into analog voltages. Digital to analog converter  700  generates frequency switching control signal  1 H_SW,  701 , and VCO frequency setting voltage FREQ. SET  302 . In FIG. 3, the frequency setting voltage FREQ. SET  302  is coupled via a resistor R 1  to the junction of resistors R 3 , R 4  and a capacitor C 3 , which in conjunction with resistor R 1  forms a low pass filter to ground. Resistors R 1  and R 3  form a potential divider for the frequency setting voltage with resistor R 3  connected to DAC  700  reference voltage (VRef). Thus analog voltage  302  is nominally halved and referenced to the DAC reference voltage (Vref) to apply a nominal voltage of about +3.8 volts of biasing potential to varicap diode D 1 . The junction of resistors R 1 , R 3  and capacitor C 3  are coupled to the cathode of varicap diode D 1  via a resistor R 4 . Thus the nominal DC voltage value, derived from voltage (Vref), plus a data determined frequency setting voltage  302 , from ADC  700 , are applied to the varicap diode DI of the oscillator frequency determining network. The frequency setting voltage  302 , is nominally zero volts in 1Fh and 2Fh modes and rises to about +7 volts when operation at 2.4Fh, for example SVGA, is selected. 
     The oscillator of VCO  300  is formed by PNP transistor Q 3  which has the emitter connected to a positive supply via a resistor R 7  and the collector connected to ground via a parallel combination of a resistor R 8  and a capacitor C 4 . The base of transistor Q 3  is connected to the positive supply via a resistor R 6 , and is coupled to ground via a capacitor C 5 . The oscillator frequency is determined largely by a series resonant network formed by an adjustable inductor L 1  and a parallel combination of varicap diode D 1  and capacitor C 4 . The junction of resistor R 4 , diode D 1  cathode and capacitor C 4  are coupled to the base of transistor Q 3  via capacitor C 6 . The collector of transistor Q 3  is connected via capacitor C 8  to the junction of inductor L 1  and a resistor, depicted in FIG. 2 as R 6 , which supplies the processed phase error signal  201  for oscillator synchronization. Thus, the frequency control and the phase synchronization signals are applied across the series resonant network formed by elements D 1 , C 4 , L 1 . Initial tuning of the oscillator may be achieved by setting the DAC voltage  302  to nominally zero volts, and with a 1Fh, NTSC horizontal sync signal coupled to the phase detector  50 , inductor L 1  is adjusted to center the phase detector error signal within its operating range. In an alternative oscillator setting method a non-adjustable inductor L 1  is employed. A horizontal frequency sync signal of 1Fh is applied to phase detector  50  and DAC voltage  302  is varied, by the microcontroller via the bus, until the phase detector error signal is centered. The data value corresponding to this centering value of voltage  302  is then stored. To determine the frequency set voltage for operation at an exemplary 2.4Fh rate, the immediately preceding method is repeated with the data value which centered the loop being stored. 
     The oscillator output signal is extracted from the emitter of transistor Q 3  at resistor R 7  and coupled to the emitter of PNP transistor Q 4  via a coupling capacitor C 6 . Transistor Q 4  is configured as a grounded base amplifier with the base decoupled to ground by a capacitor C 7  and connected to a positive supply via a resistor R 11 . The collector of transistor Q 4  is connected to ground via resistor R 10 . Thus the oscillator output signal is developed across resistor R 10  and coupled to the sync processing IC  400  as a line locked clock, LLC  301 . 
     Selection between the plurality of horizontal frequencies is initiated via a control command coupled from the microcontroller  800  via bus  420  and addressed to sync processing IC  400 . The control command, LFSS, starts or stops horizontal and frame generation within IC  400 , thus horizontal drive output signal,  403 , may be terminated as depicted by output switch  412   a . Hence, in the absence of horizontal drive signal  403 , horizontal scan amplifier  500  ceases to generate current flow and consequently pulse Hrt is no longer produced. Following the horizontal off command, LFSS, the microcontroller transmits control words addressed to the digital to analog converter DAC  700 . A first control word addressed to DAC  700  may represent a horizontal frequency switch command which is output from DAC  700  as analog control signal  1 H_SW,  701 , and is coupled as has been described, to switching interlock  650 . The DAC may also receive a second control word, which as has been described, generates an analog frequency setting potential FREQ. SET  302 . 
     Having turned off horizontal drive  403 , and thereby terminated generation of pulse Hrt, control signal  1 H_SW is permitted to change the state of integrated circuit U 1 . With the inhibit removed from I.C. U 1  the output signal SEL. H. FREQ.  402 , is able to change state thereby selecting a different divider ratio and hence a different horizontal frequency for the phase locked loops. Hence signal  402  is applied to sync processor  400  causing divider  415 A to be inserted or bypassed from the divider chain, without causing damage to the horizontal driver  450  or horizontal scan amplifier  500 . The microcontroller transmits the horizontal off command prior to transmitting horizontal frequency switch command in order to ensure that horizontal scanning amplifier  500  is quiescent and thereby avoid circuitry damage. However, protection circuitry  600  provides a further level of protection by ensuring that horizontal frequency selection by signal  402  can only occur in the absence of horizontal scan pulses Hrt. Thus sync processor  400  and scanning amplifier  500  are protected against VCO divider changes resulting from spurious signals generated, for example by, ADC  700 , or resulting from errant circuit functions, power supply loading or CRT arcing. 
     The output signal from IC U 1 , SEL. H. FREQ.,  202  is also coupled to inventive low pass active filter  200 , which is shown in FIG.  2  and functions follows. A phase error signal Φ ERROR,  11 , which results from the phase comparison between signal  401 , divided VCO, and input signal sync  5 , is coupled to input resistor R 1 . Input resistor R 1  is connected in series with resistor R 2  to a inverting input of an integrated circuit amplifier  210 . The junction of resistors R 1  and R 2  is connected to a fixed contact 1Fh of switch S 1 . The moving contact of switch S 1  is connected to the junction of a parallel combination of resistor R 3 , and capacitor C 3  and a parallel combination of resistor R 4 , and capacitor C 4 . Negative feedback is applied from the output of amplifier  210  to the inverting input via a frequency dependent network formed by capacitor C 2  and series connected combination of parallel networks of resistor R 4  and capacitor C 4  and resistor R 3  and capacitor C 3 . Parallel network R 3 , C 3  is connected between switch S 1  wiper and the inverting input of amplifier  210 . When switch S 1  selects position 1Fh, resistor R 2  is connected in parallel with the parallel combination of resistor R 3  and capacitor C 3  with the result that the newly formed parallel network, R 2 , R 3 , C 3  has little effect in the determination of the amplifier gain or frequency response. Thus when synchronized at 1Fh, with switch position 1Fh selected the amplifier gain is set by input resistor R 1 , with the frequency response determined by capacitor C 2  and parallel network R 3 , C 3 . When the display is operating at a horizontal frequency greater than 1Fh switch S 1  selects position 2Fh and resistor R 2  becomes the predominant gain determining component, with the frequency response controlled by the series combination of capacitor C 2  and parallel networks R 3 , C 3  and R 4 , C 4 . The non-inverting input of amplifier  210  is biased to a positive potential of about 2.5 volts. 
     The output from amplifier  210  is coupled via series connected resistors R 5  and R 6  to form a processed phase error signal, PROC. Φ ERROR,  201 , for coupling to synchronize VCO  300 . The junction of resistors R 5  and R 6  is decoupled to ground by a capacitor C 1  which forms a low pass filter to prevent high frequency noise generated, for example by switched mode power supply operation from producing spurious VCO phase modulation. The junction of resistors R 5  and R 6  is connected to a peak to peak limiter or clipper formed by the emitters of PNP transistor Q 1  and NPN transistor Q 2 . The collector of transistor Q 1  is connected to ground with collector of transistor Q 2  connected to a positive supply via a resistor R 9 . The base of transistor Q 2  is connected to the junction of series connected resistors R 10  and R 7 . Resistor R 10  is connected to ground and resistor R 7  is series connected to a further positive supply via a resistor R 8 . The junction resistors R 7  and R 8  is connected to the base of transistor Q 1 . Thus, resistors R 7 , R 8  and R 10  form a potential divider which determines the peak to peak clipping values of approximately +0.3 v and +2.2 volts at which processed error signal  201  is limited. 
     In a phase locked loop, the selection of phase detector output filtering is, as has been described, a compromise between static or locked phase stability and dynamic, or lock-in performance. For example, synchronization to a computer generated SVGA signal may require, or may benefit from, a narrow bandwidth VCO control signal, which will provide a highly phase stable oscillator and horizontal frequency. However, as described previously, VCR replay sync signals may include abrupt horizontal sync phase changes in the vicinity of the vertical sync and vertical blanking intervals. To prevent, or mitigate, the effect of this phase change requires that the loop have a wider bandwidth than required for either computer generated SVGA signals or broadcast signals which are not subject to abrupt phase disturbances. Advantageous amplifier  210  is arranged as an active low pass filter where output signal components are feedback to the inverting input via frequency dependent series connected network C 2 , C 3 , C 4 , and R 3 , R 4 . In accordance with an inventive aspect switch S 1  is controlled responsive to a selected horizontal oscillator frequency such that in switch position 1Fh, resistor R 2  is connected in parallel with parallel combination R 3 , C 3  to form an impedance in series with the inverting input. This parallel combination of resistors R 2 , R 3  and C 3  produces little effect on filter gain or frequency response. In switch position 1Fh the filter gain is determined by the impedance of network C 2 , C 1  and R 4  divided by the value of input resistor R 1 . Clearly as the loop operating frequency approaches DC the impedance of capacitor C 2  becomes large and the loop gain approaches an upper limit condition as depicted in FIG.  5 A. When operating at other than 1Fh horizontal frequency switch S 1  is controlled to select position 2Fh. In switch position 2Fh filter gain is determined by the impedance of feedback network R 3 , C 2 , C 1  and R 4 , divided by the series combination of resistors R 1  and R 2 . Since resistor R 2  is significantly larger than resistor R 3  the gain in the 2Fh switch position is reduced relative to that of the 1Fh position. Thus the active filter gain and bandwidth are controlled to be different in response to a selection of horizontal operating frequency. 
     During operation at a horizontal frequency of 2Fh or higher, switch S 1  selects the 2Fh position with the result that the gain at frequencies close to DC is approximately 10 dB, as is illustrated by the broken line in the amplitude versus frequency plot of FIG.  5 A. The gain then falls to zero at about 10 Hz and continues to fall reaching −20 dB at about 100 Hz. Thus when operating in a 2Fh mode with switch S 1  in the 2Fh position the zero gain bandwidth is approximately 10 Hz. FIG. 5B shows phase versus frequency plots for the two horizontal frequencies with the 2Fh mode indicated by a broken line. When operating at an NTSC frequency of 1Fh, switch S 1  is controlled to select the 1Fh position which increases the filter gain and provides a zero gain bandwidth in excess of 10 kHz. Reference to FIG. 5A illustrates that greater low frequency filter gain is employed during operation at 1Fh than that used during operation at higher horizontal frequencies. In addition the filter produces a significantly wider phase error signal bandwidth than that obtained in the 2Fh mode. Active filter gain and frequency response switching is advantageously achieved with a single switch contact which provides savings in printed circuit board area which consequently reduces susceptibility stray field pickup and spurious phase instability. The inventive switching of gain and bandwidth in an active low pass filter of a phase locked loop facilitates the rapid response to abrupt horizontal phase changes at one horizontal frequency while providing enhanced phase stability and freedom from jitter at a second horizontal frequency.