Abstract:
A method of manufacturing a solar cell on a flexible film by providing a substrate; depositing on the substrate a sequence of layers of semiconductor material forming a solar cell; mounting the semiconductor substrate on a flexible film; and thinning the semiconductor substrate to a predetermined thickness. The sequence of layers forms an inverted metamorphic solar cell structure.

Description:
REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is related to co-pending U.S. patent application Ser. No. 11/109,016 filed Apr. 19, 2005. 
         [0002]    This application is also related to co-pending U.S. patent application Ser. No. 11/445,793 filed Jun. 2, 2006. 
         [0003]    This application is also related to co-pending U.S. patent application Ser. No. 11/500,053 filed Aug. 7, 2006. 
     
    
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
       [0004]    The U.S. Government has a paid-up license in the invention and the right in limited circumstances to require the patent owner to license others on reasonable terms as provided for by the term of AFRL Agreement FA9453-04-2-0041 awarded by the Air Force Research Laboratory. 
     
    
     BACKGROUND OF THE INVENTION 
       [0005]    1. Field of the Invention 
         [0006]    The present invention relates to the field of solar cell semiconductor devices, and particularly to integrated semiconductor structures mounted on a flexible film including a multijunction solar cell and a via that allows both anode and cathode terminals to be accessed from the front side of the cell. 
         [0007]    2. Description of the Related Art 
         [0008]    Photovoltaic cells, also called solar cells, are one of the most important new energy sources that have become available in the past several years. Considerable effort has gone into solar cell development. As a result, solar cells are currently being used in a number of commercial and consumer-oriented applications. While significant progress has been made in this area, the requirement for solar cells to meet the needs of more sophisticated applications has not kept pace with demand. Applications such as satellites used in data communications have dramatically increased the demand for solar cells with improved power and energy conversion characteristics. 
         [0009]    In satellite and other space related applications, the size, mass and cost of a satellite power system are dependent on the power and energy conversion efficiency of the solar cells used. Putting it another way, the size of the payload and the availability of on-board services are proportional to the amount of power provided. Thus, as the payloads become more sophisticated, the design efficiency of solar cells, which act as the power conversion devices for the on-board power systems, become increasingly more important. 
         [0010]    Solar cells are often fabricated in vertical, multijunction structures, and disposed in horizontal arrays, with the individual solar cell connected together in a series. The shape and structure of an array, as well as the number of cells it contains, are determined in part by the desired output voltage and current. 
         [0011]    Inverted metamorphic solar cell structures such as described in U.S. Pat. No. 6,951,819, M. W. Wanless et al., Lattic Mismatched Approaches for High Performance, III-V Photovoltaic Energy Converters (Conference Proceedings of the 3 st  IEEE Photovoltaic Specialists Conference, Jan. 3-7, 2005, IEEE Press, 2005) and copending U.S. patent application Ser. No. 11/445,793 filed Jun. 2, 2006, of the present assignee, present an important starting point for the development of future commercial products with high energy conversion efficiency. 
         [0012]    Prior to the present invention, the materials and fabrication steps disclosed in the prior art have not been described for producing an energy efficient solar cell based on an inverted metamorphic structure mounted on a flexible film. 
       SUMMARY OF THE INVENTION 
     1. Objects of the Invention 
       [0013]    It is an object of the present invention to provide an improved solar cell mounted on a flexible film. 
         [0014]    It is an object of the invention to provide an improved inverted metamorphic solar cell. 
         [0015]    It is still another object of the invention to provide a method of manufacturing an inverted metamorphic solar cell using a thin, flexible film as a support. 
         [0016]    Additional objects, advantages, and novel features of the present invention will become apparent to those skilled in the art from this disclosure, including the following detailed description as well as by practice of the invention. While the invention is described below with reference to preferred embodiments, it should be understood that the invention is not limited thereto. Those of ordinary skill in the art having access to the teachings herein will recognize additional applications, modifications and embodiments in other fields, which are within the scope of the invention as disclosed and claimed herein and with respect to which the invention could be of utility. 
       2. Features of the Invention 
       [0017]    Briefly, and in good general terms, the present invention provides a method of manufacturing a solar cell by providing a substrate; depositing on the substrate a sequence of layers of semiconductor material forming a solar cell; mounting the substrate on a flexible film; and thinning the substrate to a predetermined thickness. 
         [0018]    In another aspect briefly, and the general terms, the present invention provides a method of manufacturing a solar cell by adhering a first substrate to a flexible film support after depositing on the substrate a sequence of layers of semiconductor material to form at least one cell of a multijunction solar cell; and subsequently removing at least a portion of the first substrate. 
         [0019]    The present invention further provides a solar cell mounted on a flexible film including a semiconductor body having a sequence of layers including a first solar subcell having a first band gap; a second solar subcell disposed over the first subcell and having a second band gap smaller than the first band gap; a grading interlayer disposed over the second subcell having a third band gap larger than the second band gap, and a third subcell disposed over the interlayer such that the third solar subcell is lattice mis-matched with respect to the second subcell and has a fourth band gap smaller than the third band gap. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0020]    These and other features and advantages of this invention will be better and more fully appreciated by reference to the following detailed description when considered in conjunction with the accompanying drawings, wherein: 
           [0021]      FIG. 1  is an enlarged cross-sectional view of the solar cell according to the present invention at the end of the process steps forming the layers of the solar cell on a first substrate; 
           [0022]      FIG. 2  is a cross-sectional view of the solar cell of  FIG. 1  after the next process step according to the present invention including adhering the structure to the top of a flexible film; 
           [0023]      FIG. 3  is a cross-sectional view of the structure of  FIG. 2  after the next process step of adhering a surrogate substrate to the flexible film; 
           [0024]      FIG. 4  is a cross-sectional view of the solar cell structure of  FIG. 3  after the next process step according to the present invention depicted including removing the original substrate below the solar cell layers to leave a semiconductor structure; 
           [0025]      FIG. 5  is a cross-sectional view of the solar cell of  FIG. 4  after the next process step according to the present invention of removing a layer from the top of the semiconductor surface; 
           [0026]      FIG. 6  is a cross-sectional view of the solar cell of  FIG. 5  after the next process step according to the present invention in which another layer of the semiconductor surface is removed; 
           [0027]      FIG. 7  is a cross-sectional view of the solar cell of  FIG. 6  after the next process step according to the present invention in which a metal layer is deposited over the surface of the semiconductor surface; 
           [0028]      FIG. 8  is a cross-sectional view of the solar cell of  FIG. 7  after the next process step according to the present invention in which the metal layer is patterned into grid lines; 
           [0029]      FIG. 9  is a cross-sectional view of the solar cell of  FIG. 9  after the next process step according to the present invention in which the top layer of the semiconductor surface between the grid lines is removed; 
           [0030]      FIG. 10  is a cross-sectional view of the solar cell of  FIG. 9  after the next process step according to the present invention in which an ARC layer is deposited over the surface; 
           [0031]      FIG. 11  is a cross-sectional view of the solar cell of  FIG. 10  after the next process step according to the present invention in which bond pads are opened in the ARC layer; 
           [0032]      FIG. 12  is a cross-sectional view of the solar cell of  FIG. 11  after the next process step according to the present invention in which the surrogate substrate is removed. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0033]    Details of the present invention will now be described including exemplary aspects and embodiments thereof. Referring to the drawings and the following description, like reference numbers are used to identify like or functionally similar elements, and are intended to illustrate major features of exemplary embodiments in a highly simplified diagrammatic manner. Moreover, the drawings are not intended to depict every feature of the actual embodiment nor the relative dimensions of the depicted elements, and are not drawn to scale. 
         [0034]      FIG. 1  depicts the multifunction solar cell according to the present invention after formation of the three subcells A, B and C on a substrate. More particularly, there is shown a first substrate  100 , which may be either gallium arsenide (GaAs), germanium (Ge), or other suitable material. In the case of a Ge substrate, a nucleation layer such as InGaP 2  is deposited on the substrate. In the case of a Ge substrate, a nucleation layer such as InGaP 2  is deposited on the substrate. On the substrate, or over the nucleation layer in the case of a Ge substrate, a buffer layer  103  of GaAs, and an etch stop layer  104  of GaInP 2  are further deposited. A cap or contact layer  105  of N++ GaAs is then deposited on layer  104 , and a window layer  106  of n+AlInP 2  is deposited on the cap or contact layer  105 . The subcell A, consisting of an n+ emitter layer  107  of GaInP 2  and a p type base layer  108  of GaInP 2  , is then deposited on the window layer  106 . 
         [0035]    Although the preferred embodiment utilizes the III-V semiconductor materials described above, the embodiment is only illustrative, and it should be noted that the multijunction solar cell structure could be formed by any suitable combination of group III to V elements listed in the periodic table subject to lattice constant and band gap requirements, wherein the group III includes boron (B), aluminum (Al), gallium (Ga). Indium (In), and thallium (T). The group IV includes carbon (C), silicon (Si), germanium (Ge), and tin (Sn). The group V includes nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb), and bismuth (Bi). 
         [0036]    In the preferred embodiment, the substrate  100  is gallium arsenide, the emitter layer  107  is composed of InGa(Al)P, and the base layer is composed of InGa(Al)P. The Al term in parenthesis means that Al is an optional constituent, and in this instant may be used in an amount ranging from 0% to 30%. 
         [0037]    On top of the base layer  108  is deposited a p+ type back surface field (“BSF”) layer  109  of AlGaInP which is used to reduce recombination loss. 
         [0038]    The BSF layer  109  drives minority carriers from the region near the base/BSF interface to minimize the effect of recombination loss. In other words, a BSF layer  109  reduces recombination loss at the backside of the solar subcell A and thereby reduces the recombination in the base. 
         [0039]    On top of the BSF layer  109  is deposited a sequence of heavily doped p-type (such as AlGaAs) and n-type layers  110  (such as InGaP 2 ) which forms a tunnel diode, which is used as a circuit element to electrically connect cell A to cell B. 
         [0040]    On top of the tunnel diode layers  110  a window layer  111  of n+InAlP 2  is deposited. The window layer  111  used in the subcell B also operates to reduce the recombination loss. The window layer  111  improves the passivation of the cell surface of the underlying junctions. It should be apparent to one skilled in the art, that additional layer(s) may be added or deleted in the cell structure without departing from the scope of the present invention. 
         [0041]    On top of the window layer  111  the layers of cell B are deposited: the n+ emitter layer  112 , and the p-type base layer  113 . These layers are preferably composed of n+ GaAs and p type GaAs respectively, although any other suitable materials consistent with lattice constant and band gap requirements may be used as well (e.g., an InGaP emitter region and an In 0.015 GaAs base region). 
         [0042]    On top of the cell B is deposited a BSF layer  114  of p+type AlGaAs which performs the same function as the BSF layer  109 . A n++/p++ tunnel diode  115  is then deposited over the BSF layer  114  similar to the tunnel diode of layers  110 , again forming a circuit element to electrically connect cell B to cell C. The tunnel diode is preferably a layer of GaAs over a layer of AlGaAs. A metamorphic buffer layer  117  is then deposited over the tunnel diode  116 . The layer  117  is preferably a compositionally step-graded composition of InGaAlAs deposited as a series of layers with monotically changing lattice constant that provides a transition in lattice constant from cell B to subcell C. The bandgap of layer  117  is 1.5 eV constant with a value slightly greater than the bandgap of the middle cell B. 
         [0043]    In one embodiment, as suggested in the Wanless et al. paper, the step grade contains nine compositionally graded steps with each step layer having a thickness of 0.25 micron. In the preferred embodiment, the interlayer is composed of InGaAlAs, with monotonically changing lattice constant. 
         [0044]    On the top of the metamorphic buffer layer  117  another n+ window layer  118  of GaInP 2  is deposited. The window layer  117  improves the passivation of the cell surface of the underlying junctions. Additional layers may be provided without departing from the scope of the present invention. 
         [0045]    On top of the window layer  118  the layers of subcell C are deposited: the n+ type emitter layer  119  and the p type layer  120 . In the preferred embodiment, the emitter layer is composed of GaInAs and the base layer is composed of GaInAs with about a 1.0 eV bandgap, although any other semiconductor materials with suitable lattice constant and band gap requirements may be used as well. 
         [0046]    On top of the base layer  120  of subcell C a back surface filed (BSF) layer  121 , preferably of p++ type GaInAs. 
         [0047]    On top of the p+ contact layer  122  is deposited a metal layer  123 , preferably a Ti/Au/Ag/Au sequence of layers. 
         [0048]    The semiconductor structure shown in  FIG. 1  is then bonded to the surface of a flexible film  151  (such as Kapton) by an adhesive  150 , as shown in  FIG. 2 . The flexible film typically has a thickness around 75 microns, while the semiconductor structure including substrate is around 660 microns. More particularly, the structure is bonded face down, i.e. with metal contact layer  123  being adjacent to the film  151 . 
         [0049]      FIG. 3  is a cross-sectional view of the structure of  FIG. 2  after the next process step of adhering a surrogate substrate  175  such as sapphire to the bottom of the flexible film  151 . In the preferred embodiment, the surrogate substrate is about 1000 microns in thickness, and is perforated with holes about 1 mm in diameter, spaced 4 mm apart, to aid in subsequent removal of the substrate. The details of the adhering process including a discussion of the choice of materials, will be subsequently discussed. 
         [0050]      FIG. 4  is a cross-sectional view of the solar cell structure of  FIG. 3  after the next process step according to the present invention depicted including removing the original substrate  100  below the solar cell layers  123  through  103  to leave a semiconductor structure consisting of layers  123  through  103  about 12 microns in thickness. 
         [0051]      FIG. 5  is a cross-sectional view of the solar cell of  FIG. 4  after the next process step according to the present invention of removing layer  103  from the top of the exposed semiconductor surface by known wet or dry chemical etching. Since  104  is an etch stop layer the etching removes layer  103  entirely. 
         [0052]      FIG. 6  is a cross-sectional view of the solar cell of  FIG. 5  after the next process step according to the present invention in which the layer  104  of the semiconductor surface is removed, typically by a HCl/H 2 O solution. 
         [0053]      FIG. 7  is a cross-sectional view of the solar cell of  FIG. 6  after the next process step according to the present invention. Lithography is first done to deposit photoresist to define regions where there will be no metal. A metal layer is evaporated over the photoresist. A metal layer  125  is typically composed of Pd/Ge/Ti/Pd/Ag/Au layers. 
         [0054]      FIG. 8  is a cross-sectional view of the solar cell of  FIG. 7  after the next process step according to the present invention in which the metal layer is patterned into grid lines by known lithographic techniques, in which portions of the metal layer  125  are lifted off so that the remaining metal forms parallel lines  126  which forms the grid on the front surface of the solar cell. 
         [0055]      FIG. 9  is a cross-sectional view of the solar cell of  FIG. 8  after the next process step according to the present invention in which the grid lines are used as a mask, and the cap layer  105  of the semiconductor structure between the grid lines is removed by known wet or dry chemical etching processes, thereby exposing the window layer  106  between the grid lines and over the reset of the exposed semiconductor surface. 
         [0056]      FIG. 10  is a cross-sectional view of the solar cell of  FIG. 9  after the next process step according to the present invention in which an ARC layer is deposited to a thickness of about 2000 Angstroms over the top surface of the grid lines  126 . A lithographic process is then used so that the ARC is removed from regions where bond pads are to be located. 
         [0057]      FIG. 11  is a cross-sectional view of the solar cell of  FIG. 10  after the next process step according to the present invention in which the peripheral edges of the structure are etched down to the metal layer  123 , thereby forming a mesa semiconductor structure on the surface of the wafer. Another lithographic process is then used to wet etch a back metal via from the top of the cell to the back metal. This allows contact to be made to the back metal or anode of the solar cell. 
         [0058]      FIG. 12  is a cross-sectional view of the solar cell of  FIG. 11  after the next process step according to the present invention in which the surrogate substrate is removed. 
         [0059]    Although the present invention has been described above in a specific preferred embodiment as a process for making a certain type of solar cell, more generally the invention is simply a method of bonding a wafer (with or without device structure or layers) face down on a relatively thing flexible film (such ad Kapton from Du Pont), using an appropriate adhesive (such as Teflon (FFP/PFA), or polyimide from Du Pont), then thinning the wafer (grinding/lapping and etching) till the desired thickness is reached or the desired layers are reached, and then further processing the thin wafer further to make electronic, optical, or mechanical devices (for example, thin photovoltaic cells). 
         [0060]    The invention also more generally includes using a rigid carrier (such as sapphire) to support the thin semiconductor structure of wafer on flexible thin film, through all the semiconductor device definition and processing, then the film can be demounted from the rigid substrate, and then applied to the final surface (for example, a solar panel). The film can be attached to the carrier using a temporary adhesive (such as I-4010 from Dow Corning). 
         [0061]    Thinning the substrate means that some other means of support has to be given to the device layers, during the processing, and in use. Kapton is a good material, since it is heat and chemically resistant, and also it is flexible. It can be obtained in different thicknesses, and can be obtained with adhesives on one or both sides. Adhesives such as Teflon are available on Kapton, which is suitable for this purpose, since Teflon is very chemically resistant, and also is heat resistant to a certain degree. Alternatively, adhesive can be applied (by lamination, or spinning on, for example). Teflon sheets can be laminated onto Kapton. Polyimide can be spun on to the wafer and the wafer can be attached to Kapton using the polyimide as an adhesive. Adhesives can also be applied to Kapton, at the end of the process, to attach it to curved or flat surfaces temporarily or permanently. 
         [0062]    As described above, one embodiment of the present invention comprises attaching wafers face down on to a film such as Kapton, using adhesives such as Teflon or polyimide, attaching a rigid carrier if needed, thinning the wafers, processing the devices, demounting from the rigid carrier (if used), and then applying the devices on Kapton to the final surface, with or without another adhesive. 
         [0063]    FEP and PFA are Du Pont varieties of Teflon and are thermoplastics that can also be used as adhesives. PFA (300-310 C) is higher melting than FEP (250-280 C). PFA can be subject to 260 C continuous use, and FEP can be subject to 205 C continuous use. Both of these are available in films of various thicknesses. 
         [0064]    Kapton is a polyimide from Du Pont, available in various thicknesses, and with FEP or PFA already laminated to it. Alternatively, FEP and/or PFA can be applied to Kapton films by laminating in a hot platen press. 
         [0065]    There are two ways, depending on whether the Kapton has FEP/PFA on one or both sides. If the polymer is only on one side, another adhesive, such as Dow Corning I-4010, can be used on the other side, if the wafer/Kapton combination has to be attached to a rigid carrier, for support while processing, for example during lithography. 
         [0066]    In the embodiment using double sided FEP/Kapton or PFA/Kapton, the starting point would be the wafer with any needed device layers. For the specific case of making thin inverted photovoltaics, the wafer can then be metallized on the device side, an annealed, if needed. 
         [0067]    If a rigid carrier is needed during processing, mate the wafer (device side down) and the carrier (for example, a sapphire disc/Si wafer) on either side of the Kapton, in a hot platen press. The press applies a combination of heat and pressure. The FEP/PFA is melted under pressure, to make a continuous bond. Upon cooling and removal of pressure, after a prescribed time, the wafer (device side down), the Kapton, and the carrier (sapphire/Si), will be attached to each other. 
         [0068]    Thin (grinding, lapping and/or etching) the bulk of the wafer, to reach an etch stop, and/or the device layers (if any), and further process the wafer (standard device fab processes). For the specific case of thin inverted photovoltaic, these processes might include, and not be restricted to, lithography, metallizations, depositions, etching, etc. The cell(s) on the wafer can be tested at this stage, by contacting the back metal from the front side through suitably etched contact windows and also front contact pads. 
         [0069]    Detach the Kapton from the carrier by heating up to the melting point of the thermoplastic. This can be done on a hot plate, for example. When the polymer between the carrier and the Kapton melts, the Kapton with the thinned wafer on it can be pulled off. There might be some melting of the polymer between the Kapton and the wafer, but this will re-solidify when the Kapton is taken off the carrier. There shouldn&#39;t be any detachment of the 1 MM wafer/cells from the Kapton. Ideally, Kapton with PFA on the wafer side, and FEP on the carrier side, should be used, in which case, heating up to the FEP melting temperature would release the Kapton/wafer from the carrier, leaving the PFA bond between the Kapton and the wafer intact, as PFA melts higher than FEP. 
         [0070]    The devices are now on Kapton, ready for further connection. Cutting the Kapton mechanically, through etched streets on the wafer, if needed, can separate them. A cover glass can be attached. For the specific case of photovoltaics, the mesa streets can be used to cut through the Kapton, if the cells need to be separated, and the cells can be interconnected. The Kapton can be attached to a final flat or curved surface, with or without adhesive (for example, a solar panel), as the devices with be thin enough (microns) to be flexible. 
         [0071]    In the embodiment using single sided FEP/Kapton or PFA/Kapton, in which a rigid carrier could be used during processing, another adhesive, for example Dow Corning I-4010, can be used to attach the Kapton to the rigid carrier, which may be for example a sapphire substrate with holes as previously noted. This is done in commercially available wafer equipment that applies a combination of vacuum, pressure and heat to cure the adhesive. This can be done after the Kapton/FEP or the Kapton/PFA is attached to the wafer in the hot platen press. I-4010 is a silicone adhesive that is inert to many solvents, acids, bases and other chemicals used in wafer fab. It is also heat resistant. 
         [0072]    After processing, as before, the carrier used has to be debonded by a solvent. The holes in the sapphire help to speed up the debonding, by increasing access of the solvent to the adhesive. The FEP/PFA bond is inert to this solvent, and therefore the Kapton/wafer bond will remain intact after demounting from the sapphire. Just as before, the wafer bonded to Kapton can be cut mechanically to separate the devices, for further processing. 
         [0073]     Other adhesives: Instead of FEP/PFA, we can also use any other adhesive that is resistant to the temperatures, chemicals, and other environment that&#39;s involved in the processing and final application of the devices. One chemically and thermally resistant material that can be used is polyimide, of which a variety is available, with different cure temperatures and environmental resistance. This can be applied by, for example, spin coating, to the wafer backside, the Kapton can be attached, and the stack cured to make the bond. After which the procedure is the same as above. 
         [0074]    It will be understood that each of the elements described above, or two or more together, also may find a useful application in other types of constructions differing from the types of constructions differing from the types described above. 
         [0075]    While the invention has been illustrated and described as embodied in a multifunction inverted metamorphic solar cell mounted on a flexible film, it is not intended to be limited to the details shown, since various modifications and structural changes may be made without departing in any way from the spirit of the present invention. 
         [0076]    Without further analysis, the foregoing will so fully reveal the gist of the present invention that others can, by applying current knowledge, readily adapt it for various applications without omitting features that, from the standpoint of prior art, fairly constitute essential characteristics of the generic or specific aspects of this invention and, therefore, such adaptations should and are intended to be comprehended within the meaning and range of equivalence of the following claims.