Abstract:
A sensor includes a gain stage with a differential amplifier with an adjustable gain. The differential amplifier may change its gain in response to the magnitude of a signal readout from the pixel array. The differential amplifier includes an input transistor with an adjustable transconductance. A transconductance controller can change the bias currents supplied to one or more sets of parallel transistors in the input transistor and consequently change the transconductance, and power consumption, of the input transistor. The transconductance controller can select a transconductance setting that is associated with a selected gain setting in order to more efficiently match the power consumption of the amplifier to its gain.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority to U.S. Provisional Application Ser. No. 60/285,431 filed on Apr. 19, 2001. 
    
    
     BACKGROUND 
     Active pixel sensor (APS) imaging devices are described in U.S. Pat. No. 5,471,515. These imaging devices include an array of pixel cells, arranged in rows and columns, that convert light energy into electric signals. Each pixel includes a photodetector and one or more active transistors. The transistors typically provide amplification, readout control and reset control, in addition to producing the electric signal output from the cell. 
     The pixels generate analog signals, which are converted into digital signals by analog-to-digital converters (ADCs) for further processing. The analog signal read-out chain may include a gain stage to amplify the analog signals into a range suitable for the ADCs. The magnitude of the gain may range from unity to about eight. 
     During readout, the amplifier provides adjustable signal gain with a given amplifier accuracy. The amplifier accuracy determines the required amplifier settling time, i.e., the interval between the application of the input voltage step and the point at which the output signal reaches and stays within a given error band. 
     In many sensors, the unity gain frequency of the amplifier is selected to satisfy the settling time requirement for the worst-case condition, i.e., the maximum signal gain. While this design approach ensures that the amplifier is complying with the settling time requirement at any signal gain selection, it only optimizes the amplifier power consumption in the unique case of the worst-case (maximum) gain setting. For any gain setting lower than the maximum gain setting, the amplifier draws more power than is necessary for the required settling time. 
     SUMMARY 
     A sensor includes a pixel array, a read-out stage, and a gain stage that includes a differential amplifier with an adjustable gain. The differential amplifier may change its gain in response to the magnitude of a signal readout from the pixel array. The differential amplifier includes an input transistor with an adjustable transconductance. The transconductance of the input transistor is proportional to the power consumption of the input transistor. The input transistor includes two or more sets or parallel transistors, each set connected to a different bias current supply. A transconductance controller can change the bias currents supplied to one or more sets of parallel transistors and consequently change the transconductance, and power consumption, of the input transistor. The transconductance controller can select a transconductance setting that is associated with a selected gain setting in order to more efficiently match the power consumption of the amplifier to its gain. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a sensor according to an embodiment. 
         FIG. 2  is a schematic diagram of a differential amplifier with variable gain according to an embodiment. 
         FIG. 3  is a schematic diagram of the differential amplifier of  FIG. 2  in greater detail. 
         FIG. 4  is a block diagram of a bias current selection and generation circuit according to an embodiment. 
         FIG. 5  is a schematic diagram of a current multiplexer according to an embodiment. 
         FIG. 6  is a flowchart describing an operation for matching a current bias to a selected gain value according to an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     A sensor  100  according to an embodiment includes a pixel array  102 . The sensor  100  may be an active pixel sensor (APS), in which the pixel array includes a grid of individually addressable pixels  104  arranged in rows and columns. Each pixel  104  includes a photodetector, such as a photogate, photodiode, or pinned photodiode. The photodetector converts light energy received in the form of photons into an electric charge. This electric charge corresponds to an amount of light that the pixel  104  receives during an exposure to an image. The amount of light received by each pixel in the array during exposure to the image is used by the sensor  100  to produce a signal indicating a corresponding digital image. 
     After the exposure and a subsequent integration period, the pixel array  102  is read out row-by-row for processing. The electric charge held in the pixel in each column in the selected row is output to a sample-and-hold (S/H) unit  110  in a S/H block  112 . The S/H unit  110  may include a sampling switch and a holding capacitor to store the sampled analog signal. 
     The sampled analog signals are passed from the S/H block  112  to a gain stage  120  before being sent to analog-to-digital converters (ADCs) in an ADC block  130  for conversion to digital signals. The ADCs may have a range of analog signals they can convert into discrete digital values. The analog signals generated by pixels exposed to very low levels of light may fall below the lower limit of this range. The gain stage  120  selects an appropriate gain setting to amplify such small analog signals to values that are within a suitable range for the ADCs. The gain stage  120  may have, for example, a minimum gain setting of 1 and a maximum gain setting of 8. 
     The gain stage  120  may include a class A differential amplifier  200  with variable gain, as shown in  FIG. 2 . The differential amplifier  200  has two input nodes  202 ,  204 . The input voltages Vin n  and Vin p  applied to these nodes are equal in amplitude and 180° out of phase. The differential amplifier also has two output nodes  206 ,  208 . The output voltages Vout n  and Vout p  are equal in amplitude and 180° out of phase. 
     The gain provided by the differential amplifier  200  may be adjusted by selecting an input capacitance and a feedback capacitance. The input capacitance may be set by selectively opening and closing switches sw 0 –sw 5 , and the feedback capacitance may be set by selectively opening and closing switches sw 6 –sw 7 . Each switch sw 0 –sw 7  is coupled to an associated capacitor C 0 –C 7 . Exemplary values for C 0  –C 7  are 12.5 fF, 25 fF, 50 fF, 100 fF, 200 Ff, 400 fF, 100 fF, and 100 fF, respectively. The ratio of the input capacitance to the output capacitance determines the gain setting. 
     The power consumed by the amplifier increases with its gain bandwidth (GBW). The GBW of the amplifier is proportional to the transconductance (g m ) of the input transistors in the amplifier, and is given by 
         gm     2   ⁢   π   ⁢           ⁢   C       ,       
 
where C is the load capacitance. Since the transconductance is proportional to the bias current of the input transistor, the GBW may be varied by changing the bias current of the input transistor.
 
       FIG. 3  illustrates a differential amplifier  300  with variable gain and a variable GBW, which may be selected in response to the selected gain in order to increase the efficiency of the amplifier. Rather than having two input transistors for Vin n  and Vin p , respectively, the input transistors are segmented into two sets of input transistors  302 ,  304  and  312 ,  314 . Each set of transistors is connected in parallel. The bias current through the set of parallel transistors  302 ,  304  is controlled by bias transistor  320  with input terminal tail 1 . The bias current through the set of parallel transistors  312 ,  314  is controlled by bias transistor  322  with input terminal tail 2 . 
     The total bias current input to the differential amplifier  300  is 2Ib 1 +2Ib 2 . The bias transistors  320 ,  322  form current mirrors. Each bias transistor controls the bias current through the two parallel transistors to which it is connected. The tail 1  bias transistor  320  sets the portion of the bias current flowing through each of the parallel transistors  302 ,  304  to Ib 1 , and the tail 2  bias transistor  322  sets the portion of the bias current flowing through each of the parallel transistors  312 ,  314  to Ib 2 . 
     The input transconductance, g m , and hence the GBW and power consumption, of the amplifier may be varied by varying the bias current through one or both sets of parallel transistors (Ib 1  and/or Ib 2 ). In an embodiment, the bias current applied to terminal tail 2  is reduced for lower gain settings. When the bias current Ib 2  gets close to the operating threshold for the parallel transistors  312 ,  314 , i.e., the current at which the transistors begin to turn off, the bias current applied to terminal tail 1  may then be reduced to further lower the transconductance at the input of the differential amplifier  300 . 
     As shown in  FIG. 4 , a gain decoder  402  selects a bias current setting in response to the gain setting. The gain decoder  402  controls two current multiplexers  410 ,  420 . Each current multiplexer may include an array of ten 1 μA current sources  500 – 509 , as shown in  FIG. 5 . Each current source  500 – 509  may be selected by closing a corresponding control switch s&lt; 0 &gt;–s&lt; 9 &gt;. The total current output by a current multiplexer depends on the number of control switches selected by the gain decoder  402 . 
     The currents  415 ,  425  output from the current multiplexers  410 ,  420  are input to a bias generator  430 . The bias generator  430  uses these currents to generate bias voltages in response to the selected gain setting and applies the bias voltages to terminals  350 – 355  (for bias 1 , bias 2 , bias 3 , bias 4 , tail 1 , and tail 2 , respectively).  FIG. 6  is a schematic diagram of a bias generator circuit  600  according to an embodiment. 
     In an embodiment, the differential amplifier  300  may have three bias current settings; HIGH, MED, and LOW. The gain decoder  402  may decode these three settings from the states of switches sw 3 –sw 6 . A HIGH setting corresponds to a gain between 6 and 8, a MED setting corresponds to a gain between 3 and 6, and a LOW setting corresponds to a gain between 1 and 3. For the HIGH setting, all switches for both current multiplexers  410 ,  420  are closed, providing 100% of the available bias current. For the MED setting, all switches in the current multiplexer  410  are closed, and switches s&lt; 0 &gt; and s&lt; 1 &gt; are closed in the current multiplexer  420 , providing 60% of the available bias current. For the LOW setting, switches s&lt; 0 &gt; to s&lt; 3 &gt; are closed in the current multiplexer  410 , and all switches are open in the current multiplexer  420 , providing 20% of the available bias current. 
       FIG. 6  illustrates a flowchart describing a bias selection and generation operation  600  according to an embodiment. The flow of the operation  600  is exemplary, and blocks in the flowchart may be skipped or performed in different order according to alternate embodiments. 
     A gain setting is selected (block  602 ) in response to the amplitude of the analog signal output from a pixel in a selected row. The switches sw 0 –sw 7  are selectively opened and closed to produce the selected the gain setting (block  604 ). For example, in the present embodiment, a gain of 1 is produced when all switches but switch sw 7  are open, a gain of about 4 is produced when all switches are closed, and a gain of about 8 is produces when all switches but sw 6  are closed. 
     The gain decoder determines the bias current setting (HIGH, MED, or LOW) from the state of switches sw 3 –sw 6  (block  606 ). The gain decoder controls the current multiplexers  410 ,  420  to generate the current appropriate for the gain setting and input the currents to the bias generator (block  608 ). The bias generator generates the appropriate bias voltages for terminals  350 – 355  (bias 1 , bias 2 , bias 3 , bias 4 , tail 1 , and tail 2 ) (block  610 ) and sets the bias current in the bias transistors  320 ,  322  appropriate for the gain setting (block  612 ). 
     In alternate embodiments, the input transistors may be split into more than two sets of parallel input transistors, each with an associated bias transistor. This may provide more precise tuning of the bias current to the various gain settings. Each gain setting may be associated with a distinct bias current setting to optimize power consumption in the amplifier for that gain setting. 
     With more sets of parallel input transistors, the bias current may be reduced in one set until the input transistors in that set begin to turn off, at which point the bias current in another set may be reduced. The use of multiple sets of parallel input transistors may enable greater tuning of the bias current settings to the various gain settings. 
     It may be desirable to provide a minimum amount of bias current through all input transistors to prevent the input transistors from turning completely OFF, which may produce unpredictable behavior in the amplifier. 
     An advantage of matching the GBW to a selected signal gain may be reduced power consumption of the amplifier. Another advantage may be reduced root mean square (RMS) voltage noise at the output of the amplifier. The total RMS voltage noise at the output of the amplifier may be proportional to the root square of the amplifier&#39;s GBW. For a selected signal gain, matching the GBW to the signal gain selects the lowest GBW value for a given settling time requirement. This may produce less noise at the amplifier output compared to an amplifier that is designed for the worst-case gain setting (i.e., with no GBW matching to the selected signal gain). 
     A number of embodiments have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims.