Abstract:
Disclosed here is an apparatus that comprises a sensor including a plurality of sense nodes, a plurality of first latch circuits including a plurality of first input nodes and a plurality of first output nodes, respectively, the plurality of first input nodes coupled to the plurality of sense nodes, respectively, a plurality of second latch circuits including a plurality of second input nodes and a plurality of second output nodes, respectively, the plurality of second input nodes coupled to the plurality of first output nodes, respectively, and a selector including a plurality of third input nodes coupled respectively to the plurality of first output nodes, a plurality of fourth input nodes coupled respectively to the plurality of second output nodes and a plurality of third output nodes.

Description:
[0001]    This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2014-100510 filed on May 14, 2014, the disclosure of which are incorporated herein in its entirely by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor device and particularly to a semiconductor device including a physical quantity sensor that measures physical quantities, such as temperatures. 
         [0004]    2. Description of Related Art 
         [0005]    A semiconductor device, such as DRAM (Dynamic Random Access Memory), may include a temperature sensor that measures a chip temperature. Temperature information obtained by the temperature sensor is used for operations of various circuits, such as a refresh control unit, (Japanese Patent Application Laid Open No. 2002-343079) 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    The above features and advantages of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which: 
           [0007]      FIG. 1  is a block diagram of a semiconductor device according to one embodiment of the present invention; 
           [0008]      FIG. 2  is a waveform chart showing shift timing of control signals; 
           [0009]      FIG. 3  is a block diagram of a configuration of a detection signal generator; 
           [0010]      FIG. 4  is a timing chart for explaining an operation of a temperature sensor; 
           [0011]      FIG. 5  is a first timing chart for explaining an operation of the detection signal generator; 
           [0012]      FIG. 6  is a second timing chart for explaining an operation of the detection signal generator; 
           [0013]      FIG. 7  is a third timing chart for explaining an operation of the detection signal generator; and 
           [0014]      FIG. 8  is a fourth timing chart for explaining an operation of the detection signal generator. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0015]    The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be realized using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes. 
         [0016]      FIG. 1  is a block diagram of a semiconductor device  10  according to one embodiment of the present invention. 
         [0017]    The semiconductor device  10  according to this embodiment is a DRAM. However, the semiconductor device according to this embodiment is not limited to the DRAM. The present invention may be applied also to other semiconductor memory devices, such as a SRAM, ReRAM, and flash memory, and also to logic-processing semiconductor memory devices, such as a CPU and DSP. 
         [0018]    Referring now to  FIG. 1 , the semiconductor device  10  according to a first embodiment of the present invention includes a clock terminal group  11 , a command terminal group  12 , an address terminal group  13 , a data input/output terminal group  14 , and a power terminal group  15 , which work as external terminals. These external terminals, i.e., the clock terminal group  11 , the command terminal group  12 , the address terminal group  13 , the data input/output terminal group  14 , and the power terminal group  15  are connected to a clock input circuit  21 , a command input circuit  22 , an address input circuit  23 , a data input/output circuit  24 , and an internal voltage generator  25 , respectively. The semiconductor device  10  also includes a power terminal group  16  serving as dedicated terminals for the data input/output circuit  24 . The data input/output circuit  24  includes data output buffers. 
         [0019]    The semiconductor device  10  further includes a timing generator  30 , an internal clock generator  31 , a command decoder  32 , an address control circuit  33 , a mode register  34 , a memory cell array  35 , a row decoder  36 , a column decoder  37 , a main amplifier  38 , a logic circuit  39 , and a detection signal generator  40 . 
         [0020]    The clock terminal group  11  receives external clock signals CK and /ck. 
         [0021]    The dock input circuit  21  receives the incoming external dock signals CK and /CK from the dock terminal group  11  and generates internal dock signals ICLK synchronized with the external dock signals CK and /CK. The dock input circuit  21  then outputs the internal dock signal ICLK to the timing generator  30  and to the internal dock generator  31 . 
         [0022]    Based on the internal dock signal ICLK, the timing generator  30  generates various internal docks that are timing-adjusted. Various internal docks generated by the timing generator  30  are supplied to circuit blocks included in the semiconductor device  10 . 
         [0023]    The internal clock generator  31  is, for example, a DLL circuit. The internal dock generator  31  adjusts the phase of the internal dock signal ICLK, and thereby generates an input/output dock signal LCLK. The internal dock generator  31  carries out a phase adjusting operation to set a phase difference between the external dock signal CK or /CK and the input/output dock signal LCLK to a given phase difference value. The internal dock generator  31  supplies the input/output dock signal LCLK to the data input/output circuit  24 . 
         [0024]    The command terminal group  12  receives a command signal COM. The command signal COM includes, for example, a row address strobe signal /RAS, a column address strobe signal /CAS, a chip select signal /CS, a dock enable signal CKE., etc. 
         [0025]    The command input circuit  22  receives the incoming command signal COM from the command terminal group  12  and outputs the command signal COM to the command decoder  32 . The clock enable signal CKE of the command signal COM is output to the internal clock generator  31 . 
         [0026]    The command decoder  32  receives the command signal COM. The command decoder  32  saves, decodes, and counts command signals, and thereby generates internal command signals. The command decoder  32  generates these internal command signals to include an active command IACT, read command IRD, write command IWR, mode register setting command MRS, and mode register read command MMRR. 
         [0027]    The address terminal group  13  receives an address signal ADD. 
         [0028]    The address input circuit  23  receives the incoming address signal ADD from the address terminal group  13  and outputs the address signal ADD to the address control circuit  33 . 
         [0029]    The address control circuit  33  receives the incoming address signal ADD from the address input circuit  23 . When the mode register setting command MRS is activated, the address control circuit  33  outputs a mode signal MADD including the address signal ADD to the mode register  34 . The address control circuit  33  outputs an address signal ADD representing a row address XADD to the row decoder  36 , and outputs an address signal ADD representing a column address YADD to the column decoder  37 . 
         [0030]    The mode register  34  is the register with which operational parameters of the semiconductor device  10  (e.g., burst length or CAS latency) are registered. The mode register  34  receives the mode register setting command MRS from the command decoder  32  and the mode signal MADD from the address control circuit  33 , and registers an operational parameter that is specified based on the mode register setting command MRS and the mode signal MADD. 
         [0031]    The memory cell array  35  includes multiple word lines WL, multiple bit lines BL and /BL, and multiple memory cells MC. Each memory cell MC is specified by a word line WL and a bit line BL or /BL. 
         [0032]    The row decoder  36  receives the incoming row address XADD from the address control circuit  33  and an incoming active command IACT from the command decoder  32 . Upon receiving the active command ACT, the row decoder  36  selects the word line WL corresponding to the row address from the multiple word lines WL in the memory cell array  35 . 
         [0033]    In the memory cell array  35 , the word lines WL intersect with the bit lines BL and /BL, and the memory cells MC are arranged at their intersections. For simpler description,  FIG. 1  depicts one word line WL, a pair of bit lines BL and /BL, and one memory cell MC. The bit lines BL and /BL are connected to a corresponding sense amplifier RAMP. 
         [0034]    The column decoder  37  receives the incoming column address YADD from the address control circuit  33  and further receives an incoming read command IRD and a write command IWR from the command decoder  32 . Upon receiving the column address YADD and the read command IRD or write command IWR, the column decoder  37  activates a column selection signal YS corresponding to the column address YADD. 
         [0035]    When the column selection signal YS is activated, the sense amplifier SAMP corresponding to the column selection signal YS is connected to a pair of local I/O lines LIOT and LIOB, which are connected to a pair of main I/O lines MIOT and MIOB via a connection circuit TG. The pair of main I/O lines MIOT and MIOB are connected to the main amplifier  38 . 
         [0036]    When a read operation is carried out (when the read command TRD is issued), data stored in memory cells MC selected by word lines WL are amplified by the sense amplifiers SAMP corresponding to the memory cells MC. From that data, a piece of data amplified by a sense amplifier SAMP selected by the column decoder  37  is transferred to the main amplifier  38  via the pair of local I/O lines LIOT and LIOB and the pair of main I/O lines MIOT and MIOB. The main amplifier  38  further amplifies the data transferred thereto. Data DQ output from the main amplifier  38  is transferred through the data input/output circuit  24  to the data input/output terminal group  14  and is output therefrom to the outside. 
         [0037]    When a write operation is carried out (when the write command MR is issued), data DQ received by the data input/output terminal  14  is transferred to the data input/output circuit  24 , the main amplifier  38 , the pair of main I/O lines MIOT and MIOB, and the pair of local I/O lines LIOT and LIOB in order. The transferred data DQ is then written to a memory cell MC corresponding to a sense amplifier SAMP selected by the column decoder  37 , via the SAMP. 
         [0038]    The data input/output circuit  24  receives the incoming input/output clock signal LCLK from the internal clock generator  31 . When the read operation is carried out, the data input/output circuit  24  outputs the data DQ to the data input/output terminal group  14  in synchronization with the input/output clock signal LCLK. 
         [0039]    The power terminal group  15  receives a higher source voltage VDD and a lower source voltage VSS. 
         [0040]    The internal voltage generator  25  receives the incoming source voltages VDD and VSS from the power terminal group  15  and generates internal voltages, such as a voltage VPP, voltage VOD, voltage VARY, and voltage VPERI. 
         [0041]    The voltage VPP is used mainly by the row decoder  36 . The voltages VOD and VARY are used mainly by the sense amplifier SAMP, The voltage VPERI is used as an operating voltage for other peripheral circuits. 
         [0042]    The power terminal group  16  receives a higher source voltage VDDQ and a lower source voltage VSSQ. The voltages VDDQ and VSSQ are used as operating voltages for the data input/output circuit  24 . 
         [0043]    In this specification, a signal name with “/” appended at the beginning represents a complementary signal to an original signal defined by the signal name, or means a low-active signal. The external clock signal CK and the external clock signal /CK are, therefore, complementary to each other. 
         [0044]    The logic circuit  39  receives a mode register read command MMRR. When receiving the mode register read command MMRR, the logic circuit  39  activates a control signal MMIRR 1  and a control signal MMRR 4  in order. The control signals MMRR 1  and MMRR 4  are input to the detection signal generator  40 . 
         [0045]    In synchronization with the control signals MMRR 1  and MMRR 4 , the detection signal generator  40  supplies a detection signal COP to the data input/output circuit  24 , which then outputs the detection signal COP to the outside of the semiconductor device  10  through the data input/output terminal group  14 , 
         [0046]      FIG. 2  is a waveform chart showing shift timing of the control signals MMRR 1  and MMRR 4 . 
         [0047]    As shown in  FIG. 4 , the mode register read command MMRR is specified as a three-clock-cycle command. 
         [0048]    At time t 1  at which a chip select signal CS is at a high voltage level, the control signals MMRR 1  and MMRR 4  are at a low voltage level. At time t 2  at which the chip select signal CS is at the low voltage level, the control signal MMRR 1  shifts to the high voltage level. At time t 3  at which the chip select signal CS is at the high voltage level, the control signal MMRRI is at the high voltage level while the control signal MMRR 4  is at the low voltage level. At time t 4  at which the chip select signal CS is at the low voltage level, the control signal MMRR 4  shifts to the high voltage level. 
         [0049]    In this manner, when the mode register read command MMRR is issued, the control signal MMRR 1  shifts to the high voltage level first and after the passage of 2 clock cycles, the control signal MMRR 4  then shifts to the high voltage level. 
         [0050]      FIG. 3  is a block diagram of a configuration of the detection signal generator  40  according to this embodiment, 
         [0051]    As shown in  FIG. 3 , the detection signal generator  40  has an oscillator  51  and a temperature sensor  52 . 
         [0052]    The oscillator  51  automatically generates a cyclic oscillation signal TSEN, which does not synchronize with the external clock signals CK and /CK. 
         [0053]    The temperature sensor  52  performs temperature measurement in synchronization with the oscillation signal TSEN, and outputs a measured chip temperature as a 3-bit sense signal TEMPOP. During a temperature measurement period, the temperature sensor  52  activates a monitoring signal TSREADY at a monitoring node. When the temperature measurement is over and the value of the sense signal TEMPOP is defined, a control signal TRAN is activated. 
         [0054]    The detection signal generator  40  also has latch circuits  61  to  63 , a selector  53 , and an SR latch circuit  54 . 
         [0055]    The first latch circuit  61  latches the sense signal TEMPOP in synchronization with a rising edge of the control signal TRAN. A 3-bit detection signal T 1  output from the first latch circuit  61  is supplied to a first input node of the selector  53 . 
         [0056]    The second latch circuit  62  latches a detection signal T 1 ′ in synchronization with a rising edge of the control signal MMRR 1 . The detection signal T 1 ′ is a signal created by delaying the detection signal T 1 , which is output from the first latch circuit  61 , through a delay circuit  55 . A 3-bit detection signal T 2  output from the second latch circuit  62  is supplied to a second input node of the selector  53 . 
         [0057]    The third latch circuit  63  latches a detection signal T 3  in synchronization with a rising edge of the control signal MMRR 4 . The detection signal T 3  is output from the selector  53 . A 3-bit detection signal COP output from the third latch circuit  63  is supplied to the data input/output circuit  24 . 
         [0058]    The selector  53  selects either the detection signal T 1  or detection signal T 2 , based on a control signal MMRRFAST, and outputs the selected detection signal as the detection signal T 3 , The selector  53  includes two transfer gates G 1  and G 2  switching on independently of each other. The gate electrodes of transistors respectively making up the transfer gates G 1  and G 2  are supplied with the incoming control signal MMRRFAST or the reverse signal thereto. 
         [0059]    When the control signal MMRRFAST is at low voltage level, the transfer gate G 1  is switched on, which connects the first latch circuit  61  to the third latch circuit  63 . In this case, the detection signal T 3  is identical with the detection signal T 1 . When the control signal MMRRFAST is at the high voltage level, in contrast, the transfer gate G 2  is switched on, which connects the second latch circuit  62  to the third latch circuit  63 . In this case, the detection signal T 3  is identical with the detection signal T 2 . 
         [0060]    The control signal MMRRFAST is Generated by the SR latch circuit  54 , which is a selection signal generator. A set node of the SR latch circuit (a selector control circuit)  54  receives the control signal MMRR 1 , while a reset node of the SR latch circuit  54  receives the monitoring signal TSREADY. In such a configuration, when the control signal MMRR 1  shifts to the high voltage level in a period during which the monitoring signal TSREADY stays at the low voltage level, the control signal MMRRFAST shifts to the high voltage level. Afterward, when the control signal MMRR 1  shifts to the low voltage level, the control signal MMRRFAST shifts back to the low voltage level. 
         [0061]      FIG. 4  is a timing chart for explaining an operation of the temperature sensor  52 . 
         [0062]    The temperature sensor  52  operates in synchronization with the cyclically activated oscillation signal TSEN. In the example of  FIG. 4 , the cycle of the oscillation signal TSEN is 16 msec. 
         [0063]    When the oscillation signal TSEN rises, an active signal TSACTIVE, which is an internal signal of the temperature sensor  52 , is temporarily activated to the high voltage level. A period during which the active signal TSACTIVE stays at the high voltage level is equivalent to the operation period of the temperature sensor  52 . 
         [0064]    When the active signal TSACTIVE is activated to the high voltage level, the temperature sensor  52  measures a chip temperature, and updates the value of the sense signal TEMPOP based on the measured chip temperature. During a period of updating the value of the sense signal TEMPOP, the value of the sense signal TEMPOP is temporarily left undefined. In  FIG. 4 , hatched periods each represent a period during which the value of the sense signal TEMPOP is left undefined. During this period, the temperature sensor  52  keeps the monitoring signal TSREADY indicating that the value of the sense signal TEMPOP is undefined, at the low voltage level. 
         [0065]    At the same point of time at which the monitoring signal TSREADY shifts back to the high voltage level, the control signal TRAN shifts to the high voltage level. As described above, when the control signal TRAN shifts to the high voltage level, the sense signal TEMPOP is latched by the first latch circuit  61 . As a result, the value of the detection signal T 1  output from the first latch circuit  61  is updated. 
         [0066]    Afterward, when the oscillation signal TSEN rises, the sense signal TEMPOP is latched inside the temperature sensor  52  and its value is fixed. Because temperature measurement by the temperature sensor  52  has been completed at this point of time, the value of the sense signal TEMPOP output from the temperature sensor  52  is not changed at this point of time. 
         [0067]      FIGS. 7 to 10  are timing charts for explaining operations of the detection signal generator  40 . 
         [0068]    In the example of  FIG. 5 , a period during which the monitoring signal TSREADY stays at low voltage level does not overlap a period during which the control signal MMRR 1  stays at a high voltage level. 
         [0069]    Specifically, the monitoring signal TSREADY shifts to the low voltage level at time t 1  and shifts back to the high voltage level at time t 12 . Afterward, the control signal MMRR 1  shifts to the high voltage level at time t 13  and shifts back to the low voltage level at time t 15 . 
         [0070]    In this case, the SR latch circuit  54  shown in  FIG. 3  is kept in its reset state, in which case the control signal MMRRFAST is kept at the low voltage level. As a result, the selector  53  constantly selects the detection signal T 1 . In other words, the value of the detection signal T 3  constantly matches the value of the detection signal T 1 . 
         [0071]    When the control signal MMRR 4  shifts to the high voltage level at time t 14 , the detection signal T 3  is latched by the third latch circuit  63  and therefore the value of the detection signal COP is updated. 
         [0072]    In this manner, in the example of  FIG. 5 , the detection signal T 1  (2nd data) is constantly used as the detection signal T 3 . This allows the latest temperature information to be transferred to the data input/output circuit  24 . In addition, under the condition of  FIG. 5 , almost simultaneous activation of the control signal TRAN and the control signal MMRR 4  does not occur. For this reason, the detection signal T 3  with its value undefined is not latched by the third latch circuit  63 . 
         [0073]    At time t 13 , because the control signal MMRR 1  shifts to the high voltage level at this point, the second latch circuit  62  latches the delayed detection signal T 1 ′. As a result, the value of the detection signal T 2  output from the second latch circuit  62  is updated at time t 13 . However, because the control signal MMRRFAST is kept at the low voltage level under the condition of  FIG. 5 , the detection signal T 2  output from the second latch circuit  62  is not used under this condition. 
         [0074]    In the example of  FIG. 6 , a period during which the monitoring signal TSREADY stays at the low voltage level overlaps a period during which the control signal MMRR 1  stays at the high voltage level. 
         [0075]    Specifically, after the monitoring signal TSREADY shifts to the low voltage level at time t 21 , the control signal MMRR 1  shifts to the high voltage level at time t 22  before the monitoring signal TSREADY shifts back to the high voltage level at time t 23 . Afterward, the control signal MMRR 4  shifts to the high voltage level at time t 24  and then the control signals MMRR 1  and MMRR 4  shift back to the low voltage level at time t 25 . 
         [0076]    In this case, the SR latch circuit  54  shifts to set state at time t 22  and remains in this state until time t 25 . During the period between time t 22  and time t 25 , therefore, the control signal MMRRFAST stays at the high voltage level. In other words, during the period between time t 22  and time t 25 , the selector  53  selects the detection signal T 2  and outputs it as the detection signal T 3 . 
         [0077]    Meanwhile, when the control signal MMRR 1  shifts to the high voltage level at time t 22 , the second latch circuit  62  latches the delayed detection signal T 1 ′. As a result, the value of the detection signal T 2  output from the second latch circuit  62  is updated at time t 22 . 
         [0078]    When the control signal MMRR 4  shifts to the high voltage level at time t 24 , the third latch circuit  63  latches the detection signal T 3 . As a result, the value of the detection signal COP is updated. 
         [0079]    In this manner, in the example of  FIG. 6 , the detection signal T 2  (1st data) is used as the detection signal T 3 . Even under a condition that provides a possibility of almost simultaneous activation of the control signal TRAN and the control signal MMRR 4 , therefore, the detection signal T 3  with its value undefined is not latched by the third latch circuit  63  because the detection signal T 1  is not used. 
         [0080]    In the example of  FIG. 7 , a period during which the monitoring signal TSREADY stays at the low voltage level overlaps a period during which the control signal MMRR 1  stays at the high voltage level, as in the example of  FIG. 6 . 
         [0081]    Specifically, after the control signal MMRR 1  shifts to the high voltage level at time t 31 , the monitoring signal TSREADY shifts to the low voltage level at time t 32  before the control signal MMRR 1  shifts back to the low voltage level at time t 35 . Afterward, the monitoring signal TSREADY shifts back to the high voltage level at time t 33  and the control signal MMRR 4  shifts to the high voltage level at time t 34 . 
         [0082]    In this case, the SR latch circuit  54  shifts to set state at time t 32  and remains in this state until time t 35 . During the period between time t 32  and time t 35 , therefore, the control signal MMRRFAST stays at the high voltage level. In other words, during the period between time t 32  and time t 35 , the selector  53  selects the detection signal T 2  and outputs it as the detection signal T 3 . 
         [0083]    Meanwhile, when the control signal MMRR 1  shifts to the high voltage level at time t 31 , the second latch circuit  62  latches the delayed detection signal T 1 ′. As a result, the value of the detection signal T 2  output from the second latch circuit  62  is updated at time t 31 . 
         [0084]    When the control signal MMRR 4  shifts to the high voltage level at time t 34 , the third latch circuit  63  latches the detection signal T 3 . As a result, the value of the detection signal COP is updated. 
         [0085]    In this manner, in the example of  FIG. 7 , the detection signal T 2  (1st data) is used as the detection signal T 3 , as in the example of  FIG. 6 . Even under a condition that provides a possibility of almost simultaneous activation of the control signal TRAN and the control signal MMRR 4 , therefore, the detection signal T 3  with its value undefined is not latched by the third latch circuit  63  because the detection signal T 1  is not used. 
         [0086]    In the example of  FIG. 8 , a period during which the monitoring signal TSREADY stays at the low voltage level overlaps a period during which the control signal MMRR 1  stays at the high voltage level, as in the example of  FIG. 6 . 
         [0087]    Specifically, after the control signal MMRR 1  shifts to the high voltage level at time t 41 , the monitoring signal TSREADY shifts to the low voltage level at time t 43  before the control signal MMRR 1  shifts back to the low voltage level at time t 44 . Afterward, the monitoring signal TSREADY shifts back to the high voltage level at time t 45 . The control signal MMRR 4  shifts to the high voltage level at time t 42 . 
         [0088]    In this case, the SR latch circuit  54  shifts to set state at time t 44  and remains in this state until time t 45 . During the period between time t 44  and time t 45 , therefore, the control signal MMRRFAST stays at the high voltage level. In other words, during the period between time t 44  and time t 45 , the selector  53  selects the detection signal T 2 . 
         [0089]    At this point of time, time t 42  at which the MMRR 4  shifts to the high voltage level belongs to the past. The third latch circuit  63 , therefore, latches the detection signal T 3  having passed through the first latch circuit  61 . In other words, the detection signal T 2  output from the second latch circuit  62  is not used. 
         [0090]    In this manner, in the example of  FIG. 8 , the detection signal T 1  (1st data) is used as the detection signal T 3 . This allows the latest temperature information to be transferred to the data input/output circuit  24 . In addition, under the condition of  FIG. 8 , almost simultaneous activation of the control signal TRAN and the control signal MMRR 4  does not occur. For this reason, the detection signal T 3  with its value undefined is not latched by the third latch circuit  63 . 
         [0091]    As described above, according to the detection signal generator  40  of this embodiment, when the first latch circuit  61  and the third latch circuit  63  may possibly perform their latching actions almost simultaneously, the detection signal T 2  from the second latch circuit  62  is selected. This prevents a case where the detection signal T 3  with its value undefined is latched by the third latch circuit  63  as a result of overlapping latching actions. 
         [0092]    A possibility that the first latch circuit  61  and the third latch circuit  63  perform their latching actions almost simultaneously can be detected by watching the monitoring signal TSREADY and the control signal MMRR 1 . Specifically, given the fact that the monitoring signal TSREADY stays at the low voltage level during a given period (e.g., period between time t 11  and time t 12 ) before a point of time of activation of the control signal TRAN, knowing the monitoring signal TSREADY is at the low voltage level leads to a conclusion that activation of the control signal TRAN is near. Likewise, given the fact that the control signal MMRR 1  stays at the high voltage level during a given period (e.g., period between time t 13  and time t 14 ) before a point of time of activation of the control signal MMRR 4 , knowing the control signal MMRR 1  is at the high voltage level leads to a conclusion that activation of the control signal MMRR 4  is near. 
         [0093]    Based on the above features, according to this embodiment, when the control signal MMRR 1  shifts to the high voltage level in a period during which the monitoring signal TSREADY stays at the low voltage level, the selector  53  switches transfer gate connection and selects the detection signal T 2 . As a result, when the first latch circuit  61  and the third latch circuit  63  may possibly perform their latching actions almost simultaneously, the detection signal T 3  with its value undefined is not latched by the third latch circuit  63 . 
         [0094]    The semiconductor device including the temperature sensor has been described in the above embodiments. The present invention may be applied not only to such a semiconductor device but also to a wide variety of semiconductor devices having physical quantity sensors. 
         [0095]    It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.