Abstract:
A method of fabricating a semiconductor device according to one embodiment includes: forming a mask material on a semiconductor substrate comprising first and second regions; forming a pattern of a core on the mask material in the first region; forming a sidewall spacer mask on a side surfaces of the core pattern and subsequently removing the core pattern; transferring a pattern of the sidewall spacer mask to the mask material in the first region after removing the core; and thereafter, carrying out trimming of the pattern of the sidewall spacer mask which is transferred to the mask material in the first region, and formation of a predetermined pattern on the mask material in the second region, simultaneously.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2009-010653, filed on Jan. 21, 2009, the entire contents of which are incorporated herein by reference. 
     BACKGROUND 
     A conventional fabrication (patterning) technique is known in which a sidewall spacer is formed on a side surfaces of a dummy pattern which is called a core, and after removing the core, a microscopic pattern is formed on a semiconductor substrate using the sidewall spacer as an etching mask. Since a width of the mask composed of the sidewall spacer is determined by a deposited thickness of a material film of the mask before shaped into a sidewall shape or by etching time during the shaping, more accurate dimension control, including line width control, is possible than by conventional lithography. Thanks to this method, it is possible to reduce variation of mask dimension compared to a broadly used etching hard mask formation method using a combination of a resist coating and lithographic exposure. This technique, for example, is disclosed in a non-patent literary document of A. Kaneko et al., IEDM Tech. Dig. pp. 863-866, 2005. 
     However, since the sidewall spacer mask has a ring pattern surrounding a periphery of the core due to formation method thereof, it is necessary to trim the sidewall spacer mask to shape the ring pattern into a line-and-space pattern by applying additional lithography process and an etching process again using a mask called a pattern cut mask or a trimming mask in order to use the sidewall spacer mask as a mask for forming a linear pattern called line-and-space on the workpiece material. 
     Specifically, when a fin of an SRAM cell, or another type of memory cell such as DRAM, composed of FinFET is formed applying a line-and-space pattern, a mask having in a critical design level having a submicroscopic pattern must be used as a patterning photomask for core formation and a trimming photomask for a sidewall spacer mask. Therefore, the production cost of the entire chip including cost of the mask becomes high. In addition, for a photolithography process using these photomasks, it is necessary to use a lithography technique (e.g., immersion lithography, etc.) which is good at controllability of dimension or overlay accuracy but is highly difficult and at high cost. 
     BRIEF SUMMARY 
     A method of fabricating a semiconductor device according to one embodiment includes: forming a mask material on a semiconductor substrate comprising first and second regions; forming a pattern of a core on the mask material in the first region; forming a sidewall spacer mask on a side surfaces of the core pattern and subsequently removing the core pattern; transferring a pattern of the sidewall spacer mask to the mask material in the first region after removing the core; and thereafter, carrying out trimming of the pattern of the sidewall spacer mask which is transferred to the mask material in the first region, and formation of a predetermined pattern on the mask material in the second region, simultaneously. 
     A method of fabricating a semiconductor device according to another embodiment includes: forming a mask material on a semiconductor substrate; shaping the mask material, thereby forming a region with a ring pattern formed thereon and a region without ring pattern; and thereafter, carrying out trimming of the ring pattern of the mask material into a line-and-space pattern and formation of a predetermined pattern in the region of the mask material without ring pattern simultaneously by using a photolithography technique using a photomask having both a pattern for trimming a ring pattern of a workpiece material into a line-and-space pattern and a pattern for forming a predetermined pattern in a region of the workpiece material without ring pattern. 
     A photomask according to another embodiment includes: a first pattern for trimming a ring pattern of a workpiece material into a line-and-space pattern; and a second pattern for forming a pattern in a region of the workpiece material without ring pattern. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
         FIG. 1  is a plan view of a semiconductor device according to an embodiment; 
         FIGS. 2A to 2N  are cross sectional views, which are in a direction perpendicular to a length direction of a fin, showing processes for fabricating the semiconductor device according to the embodiment; 
         FIGS. 3A to 3F  are plan views showing processes for fabricating an SRAM region of the semiconductor device according to the embodiment; 
         FIGS. 4A and 4B  are a plan view and a cross sectional view of a photomask according to the embodiment; and 
         FIGS. 5A to 5G  are cross sectional views showing processes for fabricating a semiconductor device by a conventional general method as Comparative Example. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiment 
     Structure of Semiconductor Device 
       FIG. 1  is a plan view of a semiconductor device  1  according to an embodiment. On a semiconductor substrate  2 , the semiconductor device  1  has an SRAM region  3  in which an SRAM (Static Random Access Memory) cell is formed, and a peripheral circuitry region  4  in which peripheral circuits (not shown) such as a flip-flop or a sensor amplifier, etc., are formed in an active region  5 . 
     An SRAM cell is formed in the SRAM region  3 . In the present embodiment, six transistor type of SRAM cell composed of fin-type transistors will be explained as an example. The six transistor type SRAM cell has two each of n-type transfer transistor, n-type driver transistor and p-type load transistor in one unit cell  10 . 
     Three types of transistors, which are an n-type transfer transistor  3 T, an n-type driver transistor  3 D and a p-type load transistor  3 L, a fin  12   a  including source/drain regions (not shown) of the transfer transistor T and the driver transistor  3 D, a fin  12   b  including a source/drain region (not shown) of the load transistor  3 L, a gate electrode  13   a  used for the transfer transistor  3 T and a gate electrode  13   b  commonly used for the driver transistor  3 D and the load transistor  3 L are formed in the SRAM region  3 . 
     For the semiconductor substrate  2 , it is possible to use, for example, a Si substrate, a SiGe substrate, or a substrate combined thereof by a partial selective epitaxial growth method, etc. 
     The fins  12   a  and  12   b  are formed by, e.g., etching a surface of the semiconductor substrate  2 , and are made of single crystal Si or single crystal SiGe, etc. In addition, the fins  12   a  and  12   b  include source/drain regions on both sides of the gate electrodes  13   a  and  13   b.    
     An n-type impurity such as As or P, etc., is contained in the source/drain regions of the n-type transfer transistor T and the driver transistor D, and a p-type impurity such as B or BF 2 , etc., is contained in the source/drain region of the p-type load transistor L. 
     In addition, a fin contact region  14  to be connected to a source region or a drain region is formed at a predetermined position on upper surfaces of the fins  12   a  and  12   b . The fin contact region  14  electrically connects a source region or a drain region of each portion to upper wirings. 
     The gate electrode  13   a  contacts with both side surfaces of the fin  12   a  via a gate insulating film. Meanwhile, the gate electrode  13   b  contacts with both side surfaces of the fins  12   a  and  12   b  via a gate insulating film. Regions of the fins  12   a  and  12   b  in contact with the gate electrodes  13   a  and  13   b  via the gate insulating film function as a channel region. 
     The gate electrodes  13   a  and  13   b  are made of, e.g., polycrystalline silicon or polycrystalline germanium containing a conductivity type impurity. An n-type impurity such as As or P, etc., is contained in each region of the gate electrodes  13   a  and  13   b , which belongs to the n-type transfer transistor T and the driver transistor D, and a p-type impurity such as B or BF 2 , etc., is contained in each region of the gate electrodes  13   a  and  13   b , which belongs to the p-type load transistor L. 
     Note that, a silicide layer may be formed on a surface of each of the gate electrodes  13   a  and  13   b . Alternatively, the gate electrodes  13   a  and  13   b  may be a full silicide electrode which is a fully-silicided electrode. In addition, the gate electrodes  13   a  and  13   b  may be a metal gate electrode made of W, Ta, Ti, Hf, Zr, Ru, Pt, Ir, Mo, Al or Ni, etc., or a compound thereof. In addition, the gate electrodes  13   a  and  13   b  may have a laminated structure of a metal gate electrode portion and a polycrystalline Si electrode portion. In addition, a gate sidewall spacer made of an insulating material may be each formed on side surfaces of each of the gate electrodes  13   a  and  13   b.    
     In addition, a gate contact region  15  is formed at a predetermined position on the upper surfaces of the gate electrode  13   a . The gate contact region  15  electrically connects the gate electrode  13   a  to an upper wiring. Furthermore, a shared contact  16  which is a contact shared by the gate electrode  13   b  and the fin  12   b  is formed on upper surfaces thereof. The shared contact  16  electrically connects the gate electrode  13   b  and the fin  12   b  to upper wirings. 
     The fin  12   b  is divided on a boundary of the unit cell  10  on the shared contact  16  side. 
     (Fabrication of Semiconductor Device) 
       FIGS. 2A to 2N  are cross sectional views, which are in a direction perpendicular to a length direction of a fin, showing processes for fabricating the semiconductor device according to the embodiment. In addition,  FIGS. 3A to 3F  are plan views showing processes for fabricating an SRAM region  3  of the semiconductor device  1  according to the embodiment. Here,  FIGS. 3A ,  3 B,  3 C,  3 D and  3 E respectively correspond to  FIGS. 2C ,  2 E,  2 G,  2 J and  2 L. 
     Firstly, as shown in  FIG. 2A , after laminating a SiO 2  film  30 , a SiN film  31 , an amorphous Si film  32 , a resist film  33  and an antireflection coating  34  on the semiconductor substrate  2  in the SRAM region  3  and the peripheral circuitry region  4 , a pattern of a below-described core (may be called mandrel)  35  is formed on the resist film  33  and the antireflection coating  34 . 
     The SiO 2  film  30 , the SiN film  31 , the amorphous Si film  32 , the resist film  33  and the antireflection coating  34  are formed by a CVD (Chemical Vapor Deposition) method, etc. In addition, the resist film  33  and the antireflection coating  34  are patterned by, for example, a combination of a photolithography method such as an immersion lithography method and an etching method such as a RIE (Reactive Ion Etching) method. 
     The pattern of the core  35  is submicroscopic, and which is required to have the small edge roughness. Therefore, a photomask in a design level called critical design level having a pattern of 10 nm order (a critical pattern) is used for patterning the resist film  33  and the antireflection coating  34 . 
     In general, higher pattern accuracy is required in the production of a photomask in a critical design level than in that of a photomask in a design level not really submicroscopic, in which minimum pattern size is about 1.0 μm order or larger. Hereinafter, this design level is referred to as “noncritical design level”, where the pattern can be exposed by a apparatus not having a maximum level of resolution. In addition, the turnaround time required for manufacturing and testing of the photomask in a critical design level is usually longer than that of the photomask in a noncritical design level. Therefore, the production cost of the photomask in a critical design level is very high. 
     In addition, since the maximum level of pattern formation capability or pattern overlay accuracy is required in order to perform pattern exposure of the photomask in a critical design level, it is necessary to use a high-performance and expensive photolithography tool. Therefore, the required cost spent for the photolithography process using a photomask in a critical design level is also high. 
     Next, as shown in  FIG. 2B , the amorphous Si film  32  is etched using the resist film  33  and the antireflection coating  34  as a mask, which results in that the amorphous Si film  32  is shaped into the core  35 . 
     Next, as shown in  FIGS. 2C and 3A , the resist film  33  and the antireflection coating  34  are removed by etching. 
     Next, as shown in  FIG. 2D , a TEOS film  36  is formed by the CVD method, etc., so as to conformally cover an upper surface and side surfaces of the core  35 . 
     Next, as shown in  FIGS. 2E and 3B , the TEOS film  36  is removed by the RIE method, etc., while leaving a portion thereof located on the side surfaces of the core  35 , thereby forming a sidewall spacer mask  37 . At this stage, the sidewall spacer mask  37  has a ring pattern. 
     Next, as shown in  FIG. 2F , the core  35  is removed by wet etching, etc. 
     Next, as shown in  FIGS. 2G and 3C , a resist film  38  and an antireflection coating  39  are laminated on the SiN film  31  and are subsequently patterned so as to be selectively left in the peripheral circuitry region  4 . The pattern of the resist film  38  and the antireflection coating  39  are formed larger than the active region  5 , which is formed in a posterior process, by a photolithography method using a photomask in a noncritical design level and an etching method such as the RIE method, etc. 
     Next, as shown in  FIG. 2H , the SiO 2  film  30  and the SiN film  31  are etched using the sidewall spacer mask  37 , the resist film  38  and the antireflection coating  39  as a mask. 
     Here, portions of the SiO 2  film  30  and the SiN film  31  in the SRAM region  3  to which a ring pattern of the sidewall spacer mask  37  is transferred are respectively defined as a SiO 2  film  30   a  and a SiN film  31   a . Meanwhile, portions in the peripheral circuitry region  4 , to which the pattern of the resist film  38  and the antireflection coating  39  is transferred, are defined as a SiO 2  film  30   b  and a SiN film  31   b . The pattern formed by the resist film  38  and the antireflection coating  39  is larger than the eventually formed pattern of the active region  5 . In other words, any pattern does not exist in a region in the SiO 2  film  30   b  and the SiN film  31   b  including a region to be a mask of the active region  5 . 
     Next, as shown in  FIG. 2I , the sidewall spacer mask  37 , the resist film  38  and the antireflection coating  39  are removed by etching. 
     Next, as shown in  FIGS. 2J and 3D , a resist film  40  and an antireflection coating  41  are laminated on the whole surface of the semiconductor substrate  2 , and are subsequently patterned. 
     The resist film  40  and the antireflection coating  41  are patterned by a photolithography method such as an immersion lithography method using a photomask in a critical design level, thus, a pattern for trimming the ring pattern transferred to the SiN film  31   a  into a line-and-space pattern is formed in the SRAM region  3 , and a pattern of the active region  5  is formed in the peripheral circuitry region  4 . In detail, the trimming of the pattern transferred to the SiN film  31   a  means that end portions of the rectangular ring pattern of the SiN film  31   a  in a longitudinal direction are removed for splitting into the fins  12   a  and  12   b , and the pattern of the fin  12   b  is divided on a boundary of the unit cell  10  on the shared contact  16  side. 
       FIG. 4A  is a plan view of a photomask  6  used for the photolithography process. In addition,  FIG. 4B  is a cross sectional view of the photomask  6  on cross-section A-A shown in  FIG. 4A . 
     The photomask  6  has a transparent substrate  6   a  and a light shielding film  6   b  patterned on the transparent substrate  6   a . A pattern formed on the light shielding film  6   b  includes a trimming region  7   a  including an opening pattern for trimming the pattern of the fin  12   b , and a patterning region  7   b  including a pattern for forming the pattern of the active region  5 . Note that, the light shielding film  6   b  may be also made of a semi-transparent material which does not completely shield light. 
     Next, as shown in  FIG. 2K , the trimming of the pattern of the SiN film  31   a  and the transfer of the pattern of the active region  5  to the SiN film  31   b  are simultaneously carried out by etching the SiO 2  film  30   b  and the SiN film  31   b  using the resist film  40  and the antireflection coating  41  as a mask. 
     Next, as shown in  FIGS. 2L and 3E , the resist film  40  and the antireflection coating  41  are removed by etching. Alternatively, after removing the resist film  40  and the antireflection coating  41 , a process of thinning a width of the SiN film  31   a  having the patterns of the fins  12   a  and  12   b  may be carried out, if required. 
     Next, as shown in  FIG. 2M , the semiconductor substrate  2  is etched using the SiO 2  films  30   a ,  30   b , the SiN films  31   a  and  31   b  as a mask, which results in that the fins  12   a ,  12   b  and the active region  5  are formed. 
     Next, as shown in  FIG. 2N , the SiO 2  films  30   a ,  30   b , the SiN films  31   a  and  31   b  are removed by etching. 
     Next, as shown in  FIG. 3F , the gate electrodes  13   a ,  13   b , the fin contact  14 , the gate contact  15  and the shared contact  16  are formed. In addition, although it is not shown in the figure, peripheral circuits such as a flip-flop or a sensor amplifier, etc., are formed in the active region  5 . 
     COMPARATIVE EXAMPLE 
       FIGS. 5A to 5G  are cross sectional views showing processes for fabricating a semiconductor device by a conventional general method as Comparative Example. Comparative example is different from the embodiment in that formation of mask material pattern for forming a pattern of the active region  5  and formation of mask material pattern for trimming the pattern formed on the SiN film  31   a  are performed in a separate process. Note that, a semiconductor device formed in Comparative Example has the same structure as the semiconductor device  1  in the present embodiment. 
     Firstly, as shown in  FIG. 5A , the processes until the process, shown in  FIGS. 2A to 2F , for removing the core  35  are carried out in the same way as the embodiment. 
     Next, as shown in  FIG. 5B , a resist film  50  and an antireflection coating  51  are laminated on the SiN film  31  and are subsequently patterned so as to be selectively left the peripheral circuitry region  4 . Here, the pattern of the active region  5  is formed on the resist film  50  and the antireflection coating  51  by a photolithography method such as an immersion lithography method, using a photomask in a critical design level and an etching method such as the RIE method. 
     Next, as shown in  FIG. 5C , the SiO 2  film  30  and the SiN film  31  are etched using the sidewall spacer mask  37 , the resist film  50  and the antireflection coating  51  as a mask. 
     Here, portions of the SiO 2  film  30  and the SiN film  31  in the SRAM region  3  to which a pattern of the sidewall spacer mask  37  is transferred are respectively defined as a SiO 2  film  30   a  and a SiN film  31   a , and portions in the peripheral circuitry region  4 , to which the pattern of the resist film  50  and the antireflection coating  51  are transferred, are defined as a SiO 2  film  30   b  and a SiN film  31   b.    
     Next, as shown in  FIG. 5D , the resist film  50  and the antireflection coating  51  are removed by etching. 
     Next, as shown in  FIG. 5E , after laminating a resist film  52  and an antireflection coating  53  on the whole surface of the semiconductor substrate  2 , a pattern for trimming the pattern formed on the SiN film  31   a  is formed thereon. Here, the resist film  52  and the antireflection coating  53  are patterned by a photolithography method using a photomask in a critical design level and an etching method such as the RIE method. 
     Next, as shown in  FIG. 5F , the resist film  52  and the antireflection coating  53  are removed by etching. 
     Next, as shown in  FIG. 5G , the semiconductor substrate  2  is etched using the SiO 2  film  30   a ,  30   b , the SiN film  31   a  and  31   b  as a mask, which results in that the fins  12   a ,  12   b  and the active region  5  are formed. Note that, the subsequent processes are performed in the same way as the embodiment. 
     (Effect of the Embodiment) 
     In above-mentioned Comparative Example, unlike the embodiment, the patterns of the fins  12   a  and  12   b  and the patterns of the active region  5  are simultaneously patterned on the SiO 2  film  30  and the SiN film  31 . At this time, as shown in  FIG. 5C , the side surfaces of the SiN film  31   b  may not be vertically shaped and may become a taper shape. 
     This is because a dimension conversion difference (a dimensional difference between a pattern on the photomask and a pattern actually formed on a workpiece material) is different between the pattern of the fins  12   a  and  12   b  and the pattern of the active region  5  which have different dimensions. In this case, the dimension of the active region  5  differs from the dimension of the photomask pattern. Note that, when trying to vertically form the side surfaces of the SiN film  31 , the side surfaces of the SiN film  31   a  may not become vertical but may become a reverse taper shape. 
     On the other hand, in the present embodiment, since the patterns of the fins  12   a  and  12   b  and the pattern of the active region  5  are formed on the SiO 2  film  30  and the SiN film  31  in a separate process, it is possible to perform a correction for a etching condition appropriate for each processed shape at the time of etching based on the dimension conversion difference of each pattern. As a result, it is possible to vertically shape the side surfaces of the SiN films  31   a  and  31   b , thereby forming accurate patterns of the fins  12   a ,  12   b  and the active region  5 . 
     In addition, in Comparative Example, a photomask in a critical design level is used in three processes in total, which are a process for forming the pattern of the core  35 , a process for forming the pattern of the active region  5  on the resist film  50  and the antireflection coating  51  and a process for forming a pattern for trimming the pattern formed on the SiN film  31   a  on the resist film  52  and the antireflection coating  53 . 
     On the other hand, in the embodiment, a photomask in a critical design level is used only in two processes, which are a process for forming the pattern of the core  35  and a process for forming a pattern for trimming the pattern formed on the SiN film  31   a  and a pattern of the active region  5  on the resist film  40  and the antireflection coating  41 . 
     In other words, in the embodiment, since the frequency of using the photomask in a critical design level is less than Comparative Example, it is possible to reduce the production cost of the photomask or a cost for performing highly accurate lithography, thereby reducing the total production cost of the semiconductor device  1 . 
     [Other Embodiments] 
     It should be noted that the present invention is not intended to be limited to the above-mentioned embodiment, and the various kinds of changes thereof can be implemented by those skilled in the art without departing from the gist of the invention. For example, a combination of films made of different materials may be used instead of the SiO 2  film  30 , the SiN film  31 , the amorphous Si film  32  or the TEOS film  36 . 
     In addition, although a fin used for an SRAM cell and an active region in a peripheral circuitry region have been specifically described as an example of a member having a microscopic line-and-space pattern and a microscopic pattern of the periphery thereof in the above-mentioned embodiment, it is not limited thereto in practice, and it is possible to apply the method for fabricating the semiconductor device shown in the above-mentioned embodiment to a fabrication of a member having the similar pattern, for example another type of memory cell such as DRAM.