Abstract:
A reconfigurable P-way parallel N-tap feed forward equalizer includes an adaptive filter configured to generate a series of coefficients (taps) and an input register for storing input symbols. A variable cursor position defined by a parameter corresponding to a position in the input register selects a set of pre-cursor and post-cursor taps for dynamic ISI correction of a like set of pre-cursor and post-cursor symbols. Multiplier banks generate partial result symbols by applying the taps to the set of input symbols, and a set of combiners or adder banks generate equalized output symbols from the partial result symbols. Two multiplexers adjust input symbols and coefficients according to the parameter, and a controller allows selection of an optimal parameter, and thus an optimal variable cursor position. The coefficient corresponding to the parameter may additionally be preset to save storage space.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority under 35 U.S.C. §119(e) to provisional patent application No. 61/930,115, filed on Jan. 22, 2014. Said application is herein incorporated by reference in its entirety. 
    
    
     TECHNICAL FIELD 
     This invention relates generally to digital signal processing, and particularly receiver equalization in a serializer/deserializer (SerDes) device. 
     BACKGROUND 
     Serializer/deserializer (SerDes) receivers facilitate the transmission of parallel data through a serial link by converting parallel data to serial data, transmitting the serial data through a communications channel, then converting the serial data to parallel data. Signal distortion, loss, noise, or other dispersion effects introduced by the communications channel may require signal equalization in order to correct for inter-symbol interference (ISI) or other impairments. In a digital SerDes receiver, an analog to digital converter (ADC) for sampling and digitizing the received analog signal may be implemented as an analog/mixed signal circuit and all processing of the digitized signal may be accomplished in a digital domain data path. The digital data path may include a variety of filters and equalizers, e.g., a feed forward equalizer (FFE) or a decision feedback equalizer (DFE). 
     If the data path includes a decision feedback equalizer there will be a “cursor” or received bit currently being processed by the DFE. Similarly, “post-cursor” bits are consecutive bits already processed by the DFE and “pre-cursor” bits are not yet processed by the DFE. The decision feedback equalizer can only correct ISI caused by post-cursor bits; however, inter-symbol interference can also be caused by pre-cursor bits. For optimal SerDes receiver performance, a feed forward equalizer is often used to correct ISI generated by pre-cursor bits. A combination of a feed forward equalizer and decision feedback equalizer, therefore, can correct both pre-cursor and post-cursor ISI. A data path featuring a feed forward equalizer of fixed size followed by a decision feedback equalizer may be used to provide ISI correction via a fixed number of pre-cursor and post-cursor taps. 
     SUMMARY 
     Embodiments of the present invention concern a reconfigurable parallel feed forward equalizer with variable cursor position for selection of pre-cursor and post-cursor taps in order to correct a selectable number of pre-cursor and post-cursor symbols for inter-symbol interference (ISI). Dynamic ISI correction through a reconfigurable feed forward equalizer, utilizing a variable number of pre-cursor and post-cursor taps, allows selection of an optimal configuration for any given application or communication channel. 
     In embodiments, the feed forward equalizer is an N-coefficient parallel FFE with level of parallelism P (where N, P are positive integers) that can store a set of input symbols (digital symbols received from an analog to digital converter) in an input register, each symbol in a unique register position. Two sets of multiplexers at the input—one for adjusting FFE input data and one for adjusting coefficients (ex. —taps, weights)—can both be controlled by a single parameter D w  corresponding to the variable cursor position. The cursor may take any FFE tap position corresponding to a register position: leftmost, rightmost, or any point in between (pre-cursor taps are “left” of the cursor and post-cursor taps are “right” of the cursor). Similarly, in embodiments the parameter D w  can be set to any value in the continuous range of integers greater than or equal to zero and less than P. The set of multiplexers realigns both input data and coefficients to the internal taps (ex. —filters) in the FFE, a matrix of multipliers and combiners (ex. —adders). Furthermore, to save hardware embodiments of the feed forward equalizer may assign the cursor tap a constant value (via the adaptive filter) so as not to occupy a physical location in the FFE samples&#39; storage. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not necessarily restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and together with the general description, serve to explain the principles of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The advantages of the invention may be better understood by those skilled in the art by reference to the accompanying figures in which: 
         FIG. 1  is an illustration of a data path in a SerDes receiving device; 
         FIG. 2  is an illustration of a feed forward equalizer; 
         FIG. 3  is a block diagram of a feed forward equalizer according to an embodiment of the present invention; 
         FIG. 4A  is a diagram of a feed forward equalizer according to an embodiment of the present invention; and 
         FIG. 4B  is a diagram of a feed forward equalizer according to an embodiment of the present invention. 
         FIG. 5A  is a diagram of ISI correction according to an embodiment of the present invention. 
         FIG. 5B  is a diagram of ISI correction according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Features of the present invention in its various embodiments are exemplified by the following descriptions with reference to the accompanying drawings, which describe the present invention with further detail. These drawings depict only selected embodiments of the present invention, and should not be considered to limit its scope in any way. 
       FIG. 1  illustrates a SerDes data path  100  that receives data samples  110  from an analog to digital converter (ADC) and generates equalized output symbols  118 . An N w -way parallel FFE  120  (N w =8) performs ISI correction on pre-cursor bits; a P-way parallel feed forward equalizer (where P is a positive integer) fixes at (N w −1) the quantity of pre-cursor taps w 0 , w 1 , . . . w 7  for ISI correction. A two-way DFE  140  can correct two post-cursor bits via two taps h 1 , h 2 . Adaptive filter  160  defines both pre-cursor and post-cursor taps. 
       FIG. 2  illustrates an 8-way parallel feed forward equalizer  120 . A set  110  of eight input symbols is received by the feed forward equalizer and stored in positions  122 ( a ),  122 ( b ) . . .  122 ( h ) of input register  122 . Set  110  of input samples is then delayed in register positions  122 ( a ),  122 ( b ) . . .  122 ( h ) and loaded into register positions  122 ( i ),  122 ( j ) . . .  122 ( o ) respectively. Each of eight multiplier banks  124 ( a ),  124 ( b ), . . .  124 ( h ) receives eight input values and multiplies each input value by weighted taps (ex. —coefficients) c0, c1, . . . c7. For example, multiplier bank  124 ( a ) multiplies input samples in register positions  122 ( a ) through  122 ( h ) by c0, multiplier bank  124 ( b ) multiplies input samples in register positions  122 ( b ) through  122 ( i ) by c1, etc. Finally, adder bank  128  combines results for each input sample to generate a set  130  of eight ISI-corrected output symbols. Cursor position  126  corresponds to register position  122 ( a ) and the latest-in-time input sample stored therein. 
       FIG. 3  illustrates an embodiment of a SerDes data path  200  including an 8-way parallel reconfigurable feed forward equalizer  220  with a variable cursor position  226  of the present invention. In embodiments, feed forward equalizer  220  is instrumented with coordinated multiplexer sets  262  and  264 , for adjusting input data and weighted taps (ex. —coefficients) respectively, and controlled by parameter D w  corresponding to cursor position  226 . N w -tap, P-way parallel FFE cursor position  226  may align to any of N w  tap positions. In other words, parameter D w  may take any value between 0 and (N w −1). In embodiments, adaptive filter  160  of the data path generates FFE weighted taps (ex. —coefficients) w 0 , w1, . . . w 7  via least mean squares algorithm. 
       FIG. 4A  illustrates an embodiment of an 8-way parallel reconfigurable feed forward equalizer  220  of the present invention. In embodiments where parameter D w =0, cursor position  226  corresponds to the “newest” or latest received input symbol y 7  stored in “leftmost” register position  222 ( a ). Therefore, there will be no pre-cursor filtering and seven post-cursor filtering taps w 0 , w 1 , . . . w 7  (applied to input signals by multiplier banks  224 ( a ),  224 ( b ), . . .  224 ( h )) in feed forward equalizer  220 . Adder bank  228  can then combine filter results for each input sample y 7 , y 6 , . . . y 0  and generate the corresponding set  130  of output symbols y w (7), y w (6), . . . y w (0). 
     Embodiments of the N w -tap, P-way parallel feed forward equalizer  220  can operate on vectors of P values. For example, the vector Y(m) of ADC output samples y 7 , y 6 , . . . y −8  (where Y denotes a vector quantity and m a corresponding lower case value, e.g., a digital clock index) corresponds to the set  110  of feed forward equalizer input symbols and can be defined by the equation
 
 Y ( m )=[ y ( Pm ) y ( Pm+ 1) . . .  y ( Pm+P− 1)].  (1)
 
Therefore, embodiments of feed forward equalizer input multiplexer  262  can define the content of FFE input register  222  by the equation
 
 Y ( m )=[ y ( Pm+P− 1+ D   w ) y ( Pm+P− 2+ D   w ) . . .  y ( Pm+D   w ) y ( P ( m− 1)+ P− 1+ D   w ) . . .  y ( P ( m− 1)+1+ D   q )].  (2)
 
Embodiments of feed forward equalizer  220  can include N w  symbol-spaced taps where the sample from each tap can be multiplied by an element w(n) of coefficient (weight) vector W(m) (realigned by coefficient multiplexer  264 ), which can be defined by the equation
 
 W ( m )=[ w   −D     w   ( m ) w   −D     w+1   ( m ) . . .  w   N     w     −D     w     −1 ( m )]  (3)
 
where parameter D w  corresponds to cursor position  226 . Therefore the elements y w (n) of feed forward equalizer output vector Y w (m) (corresponding to set  130  of FFE output symbols) can be defined by the series
 
                       y   w     ⁡     (   n   )       =       ∑     i   =     -     D   w             N   w     -     D   w     -   1       ⁢           ⁢         w   i     ⁡     (   m   )       ⁢     y   ⁡     (     n   -   i     )                   (   4   )               
(note that the output of feed forward equalizer  220  is dependent on parameter D w  corresponding to cursor position  226 ). In embodiments of the feed forward equalizer  220  where N w =8, for example, the value of parameter D w  may vary between 0 and 7.
 
     Referring now to  FIG. 4B , in embodiments of the feed forward equalizer  220  when parameter D w =2, data can be aligned so that cursor position  226  corresponds to register position  222 ( c ) and input sample y 7  stored therein, two positions away from “leftmost” register position  222 ( a ). Input symbol storage in register  222  includes the range from input sample y 9  at register position  222 ( a ) through input sample y −5  at register position  222 ( p ). Feed forward equalizer  220  can thus filter two pre-cursor symbols y 9  and y 8  and five post-cursor symbols y 6 , y 5 , . . . y 2 . 
       FIGS. 5A and 5B  illustrate pre-cursor and post-cursor symbols as shown in  FIGS. 4A and 4B  as notated by embodiments of decision feedback equalizer (DFE)  240 . In embodiments of data path  200 , cursor position  226  (and thus data alignment) is always aligned to h 0 , the DFE cursor (and thus the DFE error signal); the alignment of h 0  is a reference defined by the bit currently being processed by the DFE. Referring to  FIG. 5A , in embodiments where parameter D w =0, two post-cursor symbols h 1  and h 2  are used for correcting inter-symbol interference by 8-way parallel DFE  240 . When D w =0, cursor position  226  is aligned with DFE cursor h 0  and there are seven post-cursor taps w 1 , w 2 , . . . w 7  in feed forward equalizer  220 , the first two (w 1  and w 2 ) being aligned to the two DFE taps present, h 1  and h 2 . Referring to  FIG. 5B , in embodiments where parameter D w =2, cursor position  226  is aligned with DFE cursor h 0  and the two pre-cursor taps h −2  and h −1  not utilized by the DFE are aligned with the two pre-cursor taps w −2 , w −1  of the FFE. Out of the five post-cursor taps w 1 , w 2 , . . . w 5  in feed forward equalizer  220 , the first two, w 1  and w 2 , are aligned to the two DFE taps present, h 1  and h 2 . 
     Those having skill in the art will appreciate that there are various vehicles by which processes and/or systems and/or other technologies described herein can be effected (e.g., hardware, software, and/or firmware), and that the preferred vehicle will vary with the context in which the processes and/or systems and/or other technologies are deployed. For example, if an implementer determines that speed and accuracy are paramount, the implementer may opt for a mainly hardware and/or firmware vehicle; alternatively, if flexibility is paramount, the implementer may opt for a mainly software implementation; or, yet again alternatively, the implementer may opt for some combination of hardware, software, and/or firmware. Hence, there are several possible vehicles by which the processes and/or devices and/or other technologies described herein may be effected, none of which is inherently superior to the other in that any vehicle to be utilized is a choice dependent upon the context in which the vehicle will be deployed and the specific concerns (e.g., speed, flexibility, or predictability) of the implementer, any of which may vary. Those skilled in the art will recognize that optical aspects of implementations will typically employ optically-oriented hardware, software, and or firmware. 
     The herein described subject matter sometimes illustrates different components contained within, or connected with, different other components. It is to be understood that such depicted architectures are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “connected”, or “coupled”, to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being “couplable”, to each other to achieve the desired functionality. Specific examples of couplable include but are not limited to physically mateable and/or physically interacting components and/or wirelessly interactable and/or wirelessly interacting components and/or logically interacting and/or logically interactable components. 
     While particular aspects of the present subject matter described herein have been shown and described, it will be apparent to those skilled in the art that, based upon the teachings herein, changes and modifications may be made without departing from the subject matter described herein and its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications as are within the true spirit and scope of the subject matter described herein.