Abstract:
A semiconductor integrated circuit device having internal circuits, and a test mode selecting circuit. The selecting circuit includes a first load device, a transistor having a first terminal receiving a signal via the first load device, a control terminal receiving a first voltage and a second terminal, and a second load device provided between the second terminal of the transistor and a reference voltage node. A test mode selecting signal is output via the second terminal of the transistor when a second voltage higher than the voltage of the signal applied to the first load device in a normal operation mode is applied thereto. The test mode selecting signal is applied to predetermined internal circuits among said internal circuits, so that the predetermined internal circuits are switched to states of a test mode from the normal operation mode.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to semiconductor integrated circuit devices and, more particularly, to a semiconductor integrated circuit device equipped with a test mode selecting circuit that detects a test mode voltage applied to a predetermined external-connection terminal and which test mode voltage is higher than a normal voltage applied thereto in a normal operation mode and sets internal circuits to a test mode. 
     2. Description of the Prior Art 
     An SRAM (Static Random Access Memory) device is known having a built-in test mode selecting circuit as described above. A conventional built-in test mode selecting circuit includes a plurality of MOS transistors. The operation of the test mode selecting circuit greatly depends on the characteristics of the MOS transistors, more particularly, the threshold voltages thereof. If there is a difference in the threshold voltages between SRAM devices, the respective test mode selecting circuits will operate in different manners. If the threshold voltages of the MOS transistors deviate from the designed threshold voltages, the selecting circuit formed by these MOS transistors will malfunction. A test mode voltage, higher than a normal voltage, applied to a predetermined terminal will fail to cause the test mode selecting circuit to set the internal circuits to the test mode. 
     SUMMARY OF THE INVENTION 
     It is a general object of the present invention to provide a semiconductor integrated circuit device having a test mode selecting circuit in which the above disadvantage is eliminated. 
     A more specific object of the present invention is to provide a semiconductor integrated circuit device having a test mode selecting circuit capable of stably performing the mode switching operation even if there are differences among the characteristics of transistors forming the selecting circuit. 
     The above objects of the present invention are achieved by a semiconductor integrated circuit device comprising internal circuits and a test mode selecting circuit, the test mode selecting circuit comprising a first load device, a transistor having a first terminal receiving a signal via the first load device, a second terminal, a control terminal receiving a first voltage and a second load device provided between the second terminal of the transistor and a reference voltage node, a test mode selecting signal being output via the second terminal of the transistor when a second voltage higher than the voltage of the signal applied to the first load device in a normal operation mode is applied thereto, the test mode selecting signal being applied to predetermined internal circuits among the internal circuits, so that the predetermined internal circuits are switched to states of a test mode from the normal operation mode. 
     The above objects of the present invention are also achieved by a semiconductor memory device comprising a memory cell array having memory cells connected to word lines and bit lines, driving circuits for driving the word lines and bit lines. 
     Address circuits for sending the driving circuits signals necessary for driving the word lines and bit lines, a test mode selecting circuit comprising a first load device, a transistor having a first terminal receiving a signal via the first load device, a second terminal, a control terminal receiving a first voltage, and a second load device provided between the second terminal of the transistor and a reference voltage node, a test mode selecting signal being output via the second terminal of the transistor when a second voltage higher than the voltage of the signal applied to the first load device in a normal operation mode is applied thereto, so that the driving circuits are switched to states of a test mode from the normal operation mode. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a block diagram of a SRAM device related to the present invention; 
     FIG. 2 is a circuit diagram of a test mode selecting circuit shown in FIG. 1; 
     FIG. 3 is a graph of the input/output characteristic of the test mode selecting circuit shown in FIG. 2; 
     FIG. 4 is a block diagram of the principle of the present invention; 
     FIG. 5 is a graph of the input/output circuit of a test mode selecting circuit shown in FIG. 4; 
     FIG. 6 is a block diagram of an SRAM device according to an embodiment of the present invention; 
     FIG. 7 is a cross-sectional view of a structure of transistors forming a test mode selecting circuit shown in FIG. 6; 
     FIG. 8 is a graph of the input/output characteristic of the test mode selecting circuit shown in FIG. 6; and 
     FIG. 9 is a cross-sectional view of another structure of transistors forming the test mode selecting circuit shown in FIG. 6. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows an SRAM device having a built-in test mode selecting circuit. The SRAM device shown in FIG. 1 includes a memory cell array 1 having memory cells arranged in rows and columns, and X address signal input terminals 2 0  through 2 n  (n is an integer). to which X address signals (row address signals) X 0  through X n  are applied. In the normal operation, each of the X address signals X 0  through X n  has either a low (L) level, between 0 and 0.8 [V], or a high (H) level between 2.0 and 5.5 [V]. When a test mode is selected, a high level voltage V HH , higher than the level of the X address signal X 0  and equal to, for example, 7 [V], is applied to the X address signal input terminal 2 0 . 
     The SRAM device includes an X address buffer 3, temporarily storing the X address signals X 0  -X n , and a word driver 4, decoding the X address signals X 0  -X n  stored in the X address buffer 3 and performing word line driving on the basis of the decoded address signals. The SRAM device includes column address signal input terminals 5 0  -5 m  (m is an integer), a Y address buffer 6, a column switch circuit 7. Y address signals (column address signals) Y 0  -Y m  are respectively applied to the column address signal input terminals 5 0  -5 m . The Y address buffer 6 temporarily stores the Y address signals Y 0  -Y m . The column switch circuit 7 decodes the Y address signals Y 0  -Y m  stored in the Y address buffer 6 and performs column selection on the basis of the decoded address signals. 
     The SRAM device includes a sense amplifier/write driver 8, an output buffer 9 and a data output terminal 10. The sense amplifier/write driver 8 includes a sense amplifier part which amplifies data read from the memory cell array 1 and a write driver part used when data is written into the memory cell array 1. The output buffer 9 latches output data D out  and outputs it to the outside (i.e., extremely) of the SRAM device via the data output terminal 10. 
     The SRAM device includes a write enable signal terminal 11, a write enable (WE) buffer 12, a chip select signal input terminal 13, and a chip select (CS) buffer 14. A write enable signal /WE (symbol &#39;/&#39; denotes an active-low signal and corresponds to the &#34;bar&#34; positioned above the letters &#34;WE&#34; as shown in FIG. 1) is applied to the write enable signal input terminal 11. The WE buffer 12 temporarily stores the write enable signal /WE. A chip select signal /CS is applied to the chip select signal input terminal 13. The CS buffer 14 temporarily stores the chip select signal /CS. 
     A test mode selecting circuit 15 is provided as shown in FIG. 1. When the test mode is selected, the test mode selecting circuit 15 detects the high voltage V HH  applied to the X address signal input terminal 2 0  which is and equal to, for example, 7 [V], and sets the word driver 4 and the column switch circuit 7 to a test mode. V TEST  denotes the output signal of the test mode selecting circuit 15. When the output signal V TEST  is switched to the low (L) level, the word driver 4 drives all word lines, and the column switch circuit 7 selects all columns. In this state, the test is performed. 
     FIG. 2 is a circuit diagram of the test mode selecting circuit 15, which is made up of n-channel field effect transistors such as MOS (Metal Oxide Semiconductor) transistors (hereinafter simply referred to as nMOS transistors) 16-21, resistors 22 and 23, and a power supply line V CC  via which a power supply voltage Vcc of, for example, 5 [V] is applied. Each of the nMOS transistors 16-21 has a threshold voltage V TH-N  of 1.0 [V]. 
     FIG. 3 is a graph of the input/output characteristic of the test mode selecting circuit 15. In FIG. 3, V IN  denotes the voltage applied to the X address signal input terminal 2 0 , and V 25  denotes the voltage of a node 25 shown in FIG. 2. A two-dot chained line 26 indicates a variation in the voltage V 25  of the node 25 with respect to a change of the voltage V IN  under the condition in which there is no deviation in the threshold voltages V TH-N  of the nMOS transistors 16-21 and the threshold voltages V TH-N  are equal to 1.0 [V]. A solid line 27 indicates a variation in the output voltage V TEST  of the selecting circuit 15 with respect to a change of the voltage V IN  under the condition in which there is no deviation in the threshold voltages V TH-N  of the nMOS transistors 16-21 and the threshold voltages V TH-N  are equal to 1.0 [V]. 
     A broken line 28 indicates a variation in the voltage V IN  under the condition in which the threshold voltages V TH-N  of the nMOS transistors 16-21 deviate by +0.2 [V] and are equal to 1.2 [V]. A broken line 29 indicates a variation in the output voltage V TEST  of the selecting circuit 15 with respect to a change of the voltage V IN  under the condition in which the threshold voltages V TH-N  of the nMOS transistors 16-21 deviate by +0.2 [V] and are equal to 1.2 [V]. 
     A broken line 30 indicates a variation in the voltage V IN  under the condition in which the threshold voltages V TH-N  of the nMOS transistors 16-21 deviate by -0.2 [V] and are equal to 0.8 [V]. A broken line 31 indicates a variation in the output voltage V TEST  of the selecting circuit 15 with respect to a change of the voltage V IN  under the condition in which the threshold voltages V TH-N  of the nMOS transistors 16-21 deviate by -0.2 [V] and are equal to 0.8 [V]. 
     In the test mode selecting circuit 15, when there is no deviation in the threshold voltages V TH-N  and V TH-N  =1.0 [v] and V IN  &lt;6×V TH-N  =6×1.0=6.0 [V], the nMOS transistors 16-21 are OFF, so that V 25  =0 [V] and V TEST  =5 [V]. When V IN  ≧6×V TH-N  =6×1.0=6.0 [V], the nMOS transistors 16-21 are ON, so that the voltage V 25  rises as the voltage V IN  rises, and the output voltage V TEST  becomes lower as the voltage V IN  becomes higher, due to the characteristic of an inverter made up of the nMOS transistor 21 and the resistor 23. 
     When the threshold voltage of the test mode selecting circuit 15 is denoted as V TH-TEST , this threshold voltage V TH-TEST  is approximately equal to 6.6 [V] when V TH-N  is equal to 1.0 [V]. When V IN  is between 0 and 5.5 [V], that is, when the X address signal X 0  is applied to the X address signal input terminal 2 0 , the output voltage V TEST  is switched to the high (H) level and the normal operation mode is hence selected. 
     When the voltage V IN  is equal to 7.0 [V], that is, when the high voltage V HH  for mode selection is applied to the X address signal input terminal 2 0 , the output voltage V TEST  is switched to the low (L) level and hence the test mode is selected. 
     However, there is a possibility that the threshold voltages of the nMOS transistors 16-21 may deviate from the designed threshold voltages due to a cause introduced in the production process. In this case, the value of the voltage V IN  at which the logic level of the output voltage V TEST  switches, that is, the threshold voltage V TH-TEST  of the test mode selecting circuit 15, will be greatly varied due to the deviations of the threshold voltages of the nMOS transistors 16-21. This leads to a malfunction of the test mode selecting circuit 15. 
     If there is a deviation of +0.2 [V] in the threshold voltages V TH-N , the resultant deviation of the threshold voltage V TH-TEST  is +1.2 [V] (=+0.2×6), and hence the threshold voltage V TH-TEST  becomes equal to 7.8 [V] (=6.6+1.2). As a result, in this case, even if the voltage V IN  is set to 7 [V] in order to switch to the test mode, the output voltage V TEST  is not switched to the low (L) level, and hence the test mode cannot be selected. In this case, if the high voltage V HH  is set equal to 8.0 [V], the output voltage V TEST  can be switched to the low level. However, the transistors forming the row address buffer 3 shown in FIG. 1 may be damaged. 
     If there is a deviation of -0.2 [V] in the threshold voltages V TH-N , the resultant deviation of the threshold voltage V TH-TEST  is -1.2 [V] (=-0.2×6), and hence the threshold voltage V TH-TEST  becomes equal to 5.4 [V] (=6.6-1.2). As a result, in this case, when the X address signal X 0  is switched to the high (H) level and becomes equal to 5.5 [V] in the normal operation mode, the nMOS transistors 16-21 are switched to ON and the output signal V TEST  is switched to the low level. Hence, the test mode is mistakenly set. 
     Since the high level of the address signals is required to fall in the range 2.0-5.5 [V] to satisfy the standard, it is necessary to design the circuit so that the X address signal X 0  having the high level between 2.0-5.5 [V] is input. 
     As described above, in the structure shown in FIGS. 1 and 2, the threshold voltage V TH-TEST  of the test mode selecting circuit 15 greatly depends on the threshold voltages V TH-N  of the nMOS transistors 16-21 thereof, and the test mode cannot be selected with high reliability if the threshold voltages V TH-N  deviate from the designed threshold voltage. 
     FIG. 4 shows the principle of the present invention. A semiconductor integrated circuit device 32 includes a test mode selecting circuit 34 and an external-connection terminal 33. A binary signal S A  is applied to an external-connection terminal 33 in the normal operation mode of the device 32 and a predetermined high voltage V B , higher than the level of the binary signal S A , is applied thereto in the test mode. The binary signal S A  is an address signal when the device 32 is a semiconductor memory device. 
     The test mode selecting circuit 34 includes a PNP transistor 35 and load devices 36 and 37. A voltage V R , necessary to operate the PNP transistor 35, is applied to the base of the PNP transistor 35. The test mode selecting circuit 34 outputs a test mode selecting signal S TEST  via the collector of the PNP transistor 35 when the predetermined high voltage V b , higher than the binary signal S A  , is applied to the external-connection terminal 33. 
     FIG. 5 is a graph of the input/output characteristic of the test mode selecting circuit 34. In other words, FIG. 5 shows a variation in the output signal S TEST  (the collector voltage of the PNP transistor 35) of the test mode selecting circuit 34 with respect to a change of the voltage V IN  applied to the external-connection terminal 33. In the test mode selecting circuit 34, when the voltage V IN  applied to the terminal 33 is lower than V R  +0.8 [V] (the value 0.8 [V] is the base-emitter voltage of the PNP transistor 35), the PNP transistor 35 is OFF and then V TEST  =0 [V]. 
     When the voltage V IN  is equal to or higher than V R  +0.8 [V], the PNP transistor 35 is ON and the output voltage V TEST  rises as V IN  rises. When the output voltage V TEST  becomes equal to V R  +0.8 [V], the PNP transistor 35 is saturated and the output voltage V TEST  becomes constant and independent of the rise of the voltage V IN . Hence, in the case where the output voltage V TEST  is between 0 [V] and V R  +0.8 [V], and is equal to a predetermined voltage V C , higher than the value of the voltage V TEST  obtained when the binary signal S A  is at the high level, and when the voltage V TEST  is used as the test mode selecting signal S TEST , the value of the voltage V IN  obtained when V TEST  =V C  can be the threshold voltage V TH-TEST  of the test mode selecting circuit 34. 
     In the above manner, the threshold voltage V TH-TEST  of the test mode selecting circuit 34 is determined so that the normal operation mode is selected when V IN  &lt;V TH-TEST  and the test mode is selected when V IN  &gt;V TH-TEST . 
     In the case where V IN ≧V R  +0.8 [V] and V TEST ≦V R  +0,8 [V], and when the resistance values of the load devices 36 and 37 are respectively denoted by R 36  and R 37  and I E  (the emitter current of the PNP transistor 35) is nearly equal to I C  (the collector current of the PNP transistor 35), the following equations are obtained: 
     
         (V.sub.IN -V.sub.R -0.8)/R.sub.36 =V.sub.TEST /R.sub.37 
    
     
         V.sub.TEST =(V.sub.IN =V.sub.R -0.8)×R.sub.37 /R.sub.36 
    
     Hence, V TH-TEST  =R 36  /R 37  ·V C  +V R  +0.8, and the threshold voltage V TH-TEST  is determined by the ratio R 36  /R 37 , the predetermined voltage V R  and the base-emitter voltage V BE  of the PNP transistor 35. It is possible to obtain a constant value of the ratio R 36  /R 37  by forming the load devices 36 and 37 of an identical material. In the test mode, the constant value of the predetermined voltage V R  can be supplied by an LSI tester. The base-emitter voltage of the PNP transistor 35 does not have (i.e. undergo) any deviation because it is determined by the p-n junction. 
     Hence, according to the present invention, the threshold voltages V TH-TEST  of the test mode selecting circuits 34 of the different devices do not have (i.e. undergo) any deviation even if the nMOS transistors of the devices have different threshold voltages. 
     FIG. 6 shows the structure of an SRAM device having a test mode selecting circuit 38 according to an embodiment of the present invention. The SRAM device shown in FIG. 6 differs from that shown in FIG. 1 in that a test mode selecting circuit 38 is substituted for the test mode selecting circuit 15 shown in FIG. 1, the circuit 38 having a circuit configuration different from that of the circuit 15. The other parts of the SRAM device shown in FIG. 6 are the same as those of the SRAM device shown in FIG. 1. 
     The test mode selecting circuit 38 includes a PNP transistor 39, resistors 40 and 41 made of polysilicon, and an inverter 42 formed by, for example, a CMOS inverter. A power supply voltage Vcc of, for example, 5 [V], is applied to the base of the PNP transistor 39. The circuit is configured so that I E  is nearly equal to I C  when the common-emitter static forward current transfer ratio h FE  of the PNP transistor 39 is equal to 10. The resistance R 40  of the resistor 40 is equal to 1 KΩ and the resistance R 41  of the resistor 41 is equal to 5 KΩ. 
     The PNP transistor 39 is formed by, for example, a lateral-type PNP transistor utilizing pMOS transistors. 
     FIG. 7 is a cross-sectional view of such a lateral-type PNP transistor. As shown in FIG. 7, the PNP transistor includes a P-type silicon substrate, an N-type well 44, field oxide films 45-48, P-type diffusion layers 49-51, insulating layers 52 and 53, polysilicon layers 54 and 55, and aluminum layers 56-62. A P-type MOS transistor (hereinafter referred to as a pMOS transistor) 63 is formed by the P-type diffusion layers 49 and 50 and the polysilicon layer 54. The diffusion layers 49 and 50 are respectively the drain and source regions of the pMOS transistor 63, and the polysilicon layer 54 is the gate thereof. A pMOS transistor 64 is formed by the P-type diffusion layers 50 and 51 and the polysilicon layer 55. The diffusion layers 50 and 51 are respectively the source and drain regions of the pMOS transistor 64, and the polysilicon layer 54 is the gate thereof. 
     The PNP transistor 39 has a base region formed by the N-type well 44, an emitter region formed by the P-type diffusion layer 50 serving as the source regions of the pMOS transistors 63 and 64, and a collector region formed by the P-type diffusion layers 49 and 51. Further, the P-type diffusion layer 50 is electrically connected to the polysilicon layers 54 and 55 serving as the gates of the pMOS transistors 63 and 64. 
     FIG. 8 is a graph of the input/output characteristic of the test mode selecting circuit 38. In FIG. 8, a broken line 65 indicates the collector voltage V 39  of the PNP transistor 39, and a solid line 66 indicates the output voltage V TEST  of the test mode selecting circuit 38 in FIG. 6. When the voltage V IN  applied to the X address signal input terminal 2 0  is lower than Vcc+0.8 [V] (0.8 [V] is the base-emitter voltage of the PNP transistor 39), the PNP transistor 39 is OFF and I E  =I C  =0. Hence, the output voltage V TEST  becomes 0 [V]. 
     When the voltage V IN  becomes equal to or higher than Vcc+0.8 [V], the PNP transistor 39 is turned ON. Then, the emitter current I E  flows. Since the emitter current I E  is nearly equal to the collector current I C , the following equations can be obtained: 
     
         (V.sub.IN -Vcc-0.8)/R.sub.40 =V.sub.39 /RV.sub.41 
    
     
         V.sub.39 =(V.sub.IN -Vcc-0.8)×R.sub.41 /R.sub.40. 
    
     However, when V 39  =Vcc+0.8, the PNP transistor 39 is saturated. Hence, the voltage V 39  is clamped at Vcc+0.8 [V] independently of an increase in the voltage V IN . 
     If the threshold voltage of the inverter 42 is equal to Vcc/2, the threshold voltage V TH-TEST  of the test mode selecting circuit 38 is written as follows: ##EQU1## 
     As described above, according to the present embodiment, the threshold voltage V TH-TEST  of the test mode selecting circuit 38 is determined by the ratio R 40  /R 41 , the power supply voltage Vcc and the base-emitter voltage V BE  of the PNP transistor 39. Since the resistors 40 and 41 are formed of polysilicon, the ratio R 40  /R 41  does not contain (i.e., is not subject to) any deviation. In the test mode, the power supply voltage Vcc is supplied by an LSI tester, and has little deviation. The base-emitter voltage V BE  of the PNP transistor 39 does not have any deviation because it is determined by the p-n junction. 
     Hence, according to the present invention, the threshold voltages V TH-TEST  (=6.3 [V] in the above-mentioned example) of the test mode selecting circuits 38 of the different devices do not have any deviation even if the nMOS transistors of the devices have different threshold voltages. When the voltages V IN  and V HH  are selected in the test mode so that V IN  =V HH  =7 [V], the output signal V TEST  can be switched to the low level and hence the test mode can be selected. 
     Even in the case where the X address signal X 0  is at the high level 5.5 [V], the voltage V TEST  is not switched to the low level but is maintained at the high level. Hence, the test mode is not selected in this case. 
     Even in the case where there are deviations in the characteristics of the circuit elements arising from a cause introduced in the production process, there is no possibility that the threshold voltage V TH-TEST  of the test mode selecting circuit 38 is varied. Hence, the test mode can be selected with high reliability. 
     Further, according to the present embodiment, since the PNP transistor 39 is formed of the lateral-type PNP transistor comprising the pMOS transistors 63 and 64, an additional production step is not needed when fabricating CMOS SRAM devices including the test mode selecting circuits 38. 
     FIG. 9 shows another possible cross-sectional structure of the PNP transistor 39. The PNP transistor 39 shown in FIG. 9 includes a P-type silicon substrate, an N-type well 68, field oxide films 69-74, P-type diffusion layers 75-77, and aluminum layers 78-82. In the structure shown in FIG. 9, the N-type well 68 serves as the base region of the PNP transistor 39, the P-type diffusion layer 76 serves as the emitter region thereof, and the P-type diffusion layers 75 and 77 serve as the collector region thereof. 
     According to the present invention, the output voltage of the test mode selecting circuit is determined by the ratio of the resistance of the load device (36) to that of the load device (37), the predetermined voltage (V R ) applied to the base of the PNP transistor (35), and the base-emitter voltage of the PNP transistor (35). Hence, the threshold voltage (V TH-TEST ) of the test mode selecting circuit is made constant even if there are deviations of the circuit parameters. Hence, switching between the normal operation mode and the test mode can be realized with high reliability. 
     The present invention is not limited to SRAM devices but is applicable to other semiconductor integrated circuit devices such as DRAMs. 
     The present invention is not limited to the specifically disclosed embodiments, and variations and modifications may be made without departing from the scope of the present invention.