Abstract:
The present invention relates to enhancing MOSFET performance with the corner stresses of STI. A method of manufacturing a MOS device comprises the steps of: providing a semiconductor substrate; forming trenches on the semiconductor substrate and at least a pMOS region and at least an nMOS region surrounded by the trenches; filling the trenches with a dielectric material having a stress; removing at least the dielectric material having a stress in the trenches which is adjacent to a position where a channel is to be formed on each of the pMOS and nMOS regions so as to form exposed regions; filling the exposed regions with a insulating material; and forming pMOS and nMOS devices on the pMOS region and the nMOS region, respectively, wherein each of the pMOS and nMOS devices comprises a channel, a gate formed above the channel, and a source and a drain formed at both sides of the channel; wherein in a channel length direction, the boundary of each exposed region is substantially aligned with the boundary of the position of the channel, or the boundary of each exposed region extends along the channel length direction to be aligned with the boundary of corresponding pMOS or nMOS region.

Description:
CROSS REFERENCE 
       [0001]    This application is a National Phase application of, and claims priority to, PCT Application PCT/CN2012/000403, filed on Mar. 29, 2012, entitled ‘enhancing MOSFET performance with corner stresses of STI’, which claimed priority to Chinese Application No. 201110417139.2, filed on Dec. 14, 2011. Both the PCT Application and Chinese Application are incorporated herein by reference in their entireties. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates to the technical field of semiconductor manufacturing and, more particularly, to a structure and a method for enhancing MOSFET performance with corner stresses of a Shallow Trench Isolation (STI). 
       BACKGROUND OF THE INVENTION 
       [0003]    It has been proved by both theoretical research and experience investigation that when a stress is applied to a channel of a transistor, the carrier mobility of the transistor will be increased or decreased. However, it is also known that electrons and holes have different responses to strains of the same type. For example, applying a compressive stress in the direction of current flow is favorable to the hole mobility but harmful to the electron mobility, while applying a tensile stress is favorable to the electron mobility but harmful to the hole mobility. To be specific, with respect to an nMOS device, applying a tensile stress along the direction of the channel will increase mobility of electrons in the channel; on the other hand, with respect to a pMOS device, applying a compressive stress along the direction of the channel will increase mobility of holes in the channel. With the continuous reduction in the feature size of the device, the strained channel engineering for the purpose of increasing mobility of carriers in the channel is playing a more and more important role. However, smaller device pitch will result in more difficulties in applying strong stresses to the MOSFET. 
         [0004]    Therefore, there is still need for a new structure and a method that can easily increase the stress in the channel. 
       SUMMARY OF THE INVENTION 
       [0005]    To solve the above problem, according to one aspect of the present invention, a method of manufacturing a MOS device is provided, which comprises the steps of: providing a semiconductor substrate; forming trenches and two MOS regions surrounded by the trenches on the semiconductor substrate; filling the trenches with a dielectric material having a stress; removing at least the dielectric material having a stress in the trenches which is adjacent to a position where a channel is to be formed on each MOS region so as to form exposed regions; filling the exposed regions with a dielectric material; and forming MOS devices on the MOS regions, wherein a channel is formed at the position where a channel is to be formed, a gate is formed above the channel, and a source and a drain are formed at the two sides of the channel; wherein in the direction of the length of the channel, the boundary of each exposed region is substantially aligned with the boundary of the position where a channel is to be formed, or the boundary of each exposed region extends along the direction of the length of the channel until it is aligned with the boundary of the corresponding MOS region. 
         [0006]    According to one aspect of the present invention, a MOS device is provided, comprising: a semiconductor substrate; trenches and two MOS regions surrounded by the trenches formed on the semiconductor substrate; a dielectric material having a stress, which fills the trenches; exposed regions, which are obtained by removing at least the dielectric material having a stress in the trenches which is adjacent to the position where a channel is to be formed on each MOS region; a dielectric material which fills the exposed regions; and a channel formed at the position where a channel is to be formed, a gate formed above the channel, and a source and a drain formed at the two sides of the channel; wherein in the direction of the length of the channel, the boundary of each exposed region is substantially aligned with the boundary of the position where a channel is to be formed, or the boundary of each exposed region extends along the direction of the length of the channel until it is aligned with the boundary of the corresponding MOS region. 
         [0007]    According to one aspect of the present invention, a method of manufacturing a MOS device is provided, which comprises the steps of: providing a semiconductor substrate; forming trenches and two MOS regions surrounded by the trenches on the semiconductor substrate; filling the trenches with a dielectric material having a stress; removing at least the dielectric material having a stress in the trenches at the outside of the ends of the two MOS regions that are away from each other, wherein the portions having the dielectric material having a stress removed respectively form exposed regions; filling the exposed regions with a dielectric material; and forming MOS devices on the MOS regions, wherein a channel is formed at the position where a channel is to be formed, a gate is formed above the channel, and a source and a drain are formed at the two sides of the channel; wherein in the direction of the length of the channel, the boundary of each exposed region is substantially aligned with the boundary of the corresponding MOS region, or the boundary of each exposed region extends toward the direction of the channel along the direction of the length of the channel until it reaches the boundary of the position where a channel is to be formed. 
         [0008]    According to one aspect of the present invention, a MOS device is also provided, comprising: a semiconductor substrate; trenches and two MOS regions surrounded by the trenches formed on the semiconductor substrate; a dielectric material having a stress, which fills the trenches; exposed regions, which are obtained by removing at least the dielectric material having a stress in the trenches at the outside of the ends of the two MOS regions that are away from each other; a dielectric material which fills the exposed regions; and a channel formed at the position where a channel is to be formed, a gate formed above the channel, and a source and a drain formed at the two sides of the channel; wherein in the direction of the length of the channel, the boundary of each exposed region is substantially aligned with the boundary of the corresponding MOS region, or the boundary of each exposed region extends toward the direction of the channel along the direction of the length of the channel until it reaches the boundary of the position where a channel is to be formed. 
         [0009]    The dielectric material having a stress and the semiconductor substrate thereunder in the present invention have the same stress. However, the substrate has a greater thickness, and therefore the unit stress produced thereby is far less than the unit stress at the position where the dielectric material having a stress is located. When removing the dielectric material having a stress, a larger force thereon acts on the boundary of the un-removed dielectric material having a stress, thus generating a “Corner Effect”. In the embodiments of the present invention, after removing the dielectric material having a stress, a larger force will be generated between the edge of the remaining dielectric material having a stress and the substrate contacting therewith, so that a larger stress will be generated in the channel of the MOSFET. As a result, it is easier to enhance the MOSFET performance. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The embodiments can be best understood with reference to the following descriptions and the drawings illustrating each of the embodiments. In the drawings: 
           [0011]      FIGS. 1   a - 1   b,    2 ,  3   a - 3   b,    4   a - 4   d,    5   a - 5   c,    6   a - 6   b,    7   a - 7   b,    8   a - 8   b,    9 ,  10   a - 10   b,    11   a - 11   b,    12   a - 12   b,    13 ,  14   a - 14   b,    15   a - 15   d,    16   a - 16   c,    17   a - 17   b,    18   a - 18   b  and  19   a - 19   b  show the sectional views of the device corresponding to each of the steps of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0012]    One or more aspects of the embodiment of the present invention will be described below with reference to the figures, wherein throughout the figures, the same elements are generally represented by the same reference signs. In the descriptions below, many specific details are elucidated for the purpose of explanation, so that a thorough understanding of one or more aspects of the embodiment of the present invention can be provided. However, it is obvious to those skilled in the art that one or more aspects of the embodiment of the present invention may be implemented by a fewer of the specific details. 
       First Embodiment 
       [0013]    First, a semiconductor substrate  100  is provided, and can be of any type known in the field of electronics, such as a bulk semiconductor, and Semiconductor On Insulator (SOI). The material of the substrate can be monocrystalline silicon, gallium arsenide, indium phosphide, etc. In one specific embodiment, the semiconductor substrate  100  is a silicon substrate with (100) crystal orientation or (110) crystal orientation. The selection of the crystal orientation depends on requirements for the performance of the finished device, and the substrate with (100) crystal orientation can help to increase mobility of electrons in the device, while the substrate with (110) crystal orientation can help to increase mobility of holes in the device, and the electron mobility is greater than the hole mobility due to their properties. Therefore, in a CMOS device, for example, if it is desired that the performance of the pMOS device therein is as close as possible to the performance of the nMOS device, then the substrate with (110) crystal orientation is preferable; and if a higher performance of the nMOS device is desired, then the substrate with (100) crystal orientation is preferable. In addition, the provided semiconductor substrate may be P-type, N-type or un-doped. 
         [0014]    Next, the step of forming trenches and MOS regions surrounded by the trenches on the semiconductor substrate is performed. 
         [0015]    To this end, a hard mask is first formed in an embodiment. In one specific embodiment, an oxide  105  is first formed on the semiconductor substrate  100 , and includes, but is not limited to, SiO 2 , and has a thickness within the range of about 5-20 nm, for example. The method of forming the oxide includes, but is not limited to, Chemical Vapor Deposition (CVD), Plasma Assisted CVD, Atomic Layer Deposition (ALD), vapor deposition, reactive sputtering, chemical solution deposition or other similar deposition techniques. As a substitute, the oxide may also be formed by a thermal oxidation technology or by a combination of thermal oxidation technology and deposition technology. For example, in the case where the substrate is formed of Si, thermal oxidation is performed on the silicon substrate to form a thin SiO 2 , then the rest SiO 2  is deposited to reach a predetermined height using a deposition technology. 
         [0016]    Next, a nitride  110  is formed on the oxide  105 . The nitride includes, but is not limited to, SiN and Si 3 N 4 , and the thickness thereof is, for example, within a range of about 50-150 nm. The method of forming the nitride includes, but is not limited to, Chemical Vapor Deposition (CVD), Plasma Assisted CVD, Atomic Layer Deposition (ALD), vapor deposition, reactive sputtering, chemical solution deposition or other similar deposition techniques. 
         [0017]    Then, the oxide and nitride are patterned to form a patterned hard mask, and parts of the substrate are removed by means of the patterned hard mask so as to form the trenches in the substrate, and the un-removed substrate corresponds to the MOS regions. In one specific embodiment, the nitride  110  and oxide  105  are patterned, and parts of the semiconductor substrate  100  are removed to form trenches  120  and MOS regions  115   a  and  115   b  surrounded by the trenches, wherein, there is also a trench between the MOS regions  115   a  and  115   b.    FIG. 1   a  is a top view of the resulting structure,  FIG. 1   b  is a planar view taken along line AA′ in  FIG. 1   a.  Two MOS regions are shown in the figure, but this is only an example and more than two MOS regions can be formed on the substrate. The methods for patterning and removing include, but are not limited to, dry etching and wet etching, and Reactive Ion Etching (RIE) is preferable. 
         [0018]    The method for forming trenches includes, but is not limited to, the above-mentioned method. In another embodiment, the trenches can be formed by directly cutting the substrate using a cutting technology. More generally, the trenches can be formed by any appropriate method in the art. 
         [0019]    Then, a step of filling the trenches with a dielectric material having a stress is performed, and the dielectric material having a stress may include, but not limited to, strained nitride. 
         [0020]    To this end, in one specific embodiment, a strained nitride  130  is formed in the trenches  120  to fill the trenches, as shown in  FIG. 3 .  FIG. 3   a  is a top view of the resulting structure, and  FIG. 3   b  is a planar view taken along line AA′ in  FIG. 3   a . It can be seen from  FIG. 3   a  that the MOS regions are completely surrounded by the strained nitride  130 . In the case where the MOS to be made is an nMOS, the nitride should have a tensile stress, while in the case where the MOS to be made is a pMOS, the nitride should have a compressive stress. Specifically, the structure can be formed by depositing the strained nitride  130  and by etching back or Chemical Mechanical Polishing (CMP) the nitride. 
         [0021]    In the specific embodiment where the trenches are formed by directly cutting the substrate, the structure can be formed by depositing the strained nitride  130  and by etching back or CMP the nitride to expose the substrate in the MOS regions. 
         [0022]    Preferably, before filling the strained nitride, a layer of oxide  125  is formed in the trenches. The method of forming the oxide includes, but is not limited to, Chemical Vapor Deposition (CVD), Plasma Assisted CVD, Atomic Layer Deposition (ALD), vapor deposition, reactive sputtering, chemical solution deposition or other similar deposition techniques. The oxide functions as a buffer layer between the strained nitride and the substrate. In the specific embodiment using the hard mark, the oxide  125  also exists on the MOS regions, as shown in  FIG. 2 . In the specific embodiment where the trenches are formed by directly cutting the substrate, the oxide  125  does not exist on the surface of the exposed substrate in the MOS regions. 
         [0023]    Next, a step of removing a part of the strained nitride in the trenches is performed. 
         [0024]    To this end, at least the strained nitride  130  in the trenches which is adjacent to the position (the area surrounded by dashed lines in  FIG. 4   a ) where a channel is to be formed on each of the MOS regions ( 115   a,    115   b ), is removed, and the portions where the strained nitride are removed respectively form exposed regions  1251 ,  1252 ,  1253  and  1254 . In the channel length direction, the boundary of each exposed region is substantially aligned with the boundary of the position where a channel is to be formed. The word “substantially” herein means that the boundary of the exposed region is aligned with the boundary of the position where a channel is to be formed within the range of process tolerance.  FIGS. 4   c  and  4   d  are sectional views taken along lines AA′ and BB′ in  FIG. 4   a . Positions C, S and D in the figures correspond to the channel to be formed, the source to be formed and the drain to be formed, respectively. In another embodiment, any one of the boundaries of exposed regions  1251 ,  1252 ,  1253  and  1254  can extend along the direction of the length of the channel to be formed (the direction indicated by the double-headed arrow line in  FIG. 4   b ) until it is aligned with the boundary of the corresponding MOS region. The method of removing the strained nitride includes, but is not limited to, RIE selective to the materials thereunder. 
         [0025]    In the case where the MOS device is an nMOS device, after removing the tensile strained nitride in the trenches corresponding to the position where a channel is to be formed in each of the MOS regions, owing to the corner effect, the tensile stress of the tensile strained nitride  130  at the periphery of each of the MOS regions is more concentrating in the channel, thereby generating a larger stress. In the case where the MOS device is a pMOS device, after removing the compressive strained nitride in the trenches corresponding to the position where a channel is to be formed in each of the MOS regions, owing to the corner effect, the compressive stress of the compressive strained nitride  130  at the periphery of each of the MOS regions is more concentrating in the channel, thereby generating a larger stress. As for detailed explanations of the “corner effect” mentioned herein, reference can be made to relevant technical documents that have been published, and it is known to those skilled in the art. 
         [0026]    The following describes the case shown in  FIG. 4   a.    
         [0027]    The exposed regions are filled with a dielectric material  135 , such as an oxide. In the specific embodiment where the hard mask is used, the step is realized through depositing the dielectric material  135  and planarizing it by etching back or a CMP technology until exposing the hard mask on the MOS regions, as shown in  FIG. 5 . Wherein,  FIG. 5   a  is a top view after the step, and  FIGS. 5   b  and  5   c  are sectional views taken along the lines AA′ and BB′ in  FIG. 5   a . In the specific embodiment where the trenches are formed by directly cutting the substrate, the structure can be formed through depositing the dielectric material  135  and etching back or CMP the dielectric material  135  to expose the substrate in the MOS regions. 
         [0028]    In the specific embodiment where the hard mask is used, there is a further step of removing the nitride  110 , as shown in  FIGS. 6   a  and  6   b . Wherein,  FIGS. 6   a  and  6   b  are sectional views taken along lines AA′ and BB′, respectively. The method of removing the nitride  110  includes but is not limited to RIE selective to the dielectric material  135 . In this step, the strained nitride  130  is covered by the dielectric material  135  and thus is not influenced. Subsequently, the oxide  105  on the MOS regions is removed to expose the substrate  100  thereon. Meanwhile, the dielectric material  135  of a certain thickness is also removed. 
         [0029]    Next, a MOS device is formed using a conventional MOS technology, wherein a channel is formed at a position (position C of  FIG. 4 ) where a channel is to be formed, a gate is formed above the channel, and a source and a drain are formed at both sides of the channel (positions S and D of  FIG. 4 ), as shown in  FIG. 7 .  FIG. 7   a  is a top view after the step, and  FIG. 7   b  is a sectional view taken along line AA′ in  FIG. 7   a.    
       Second Embodiment 
       [0030]    The second embodiment is substantively the same as the first embodiment, and descriptions below focus on the differences, while the parts that are the same as the first embodiment will not be elaborated any more. 
         [0031]    A similar substrate as that in the first embodiment is provided. 
         [0032]    MOS regions  215   a  and  215   b  and trenches  220  surrounding MOS regions  215   a  and  215   b  are formed, unlike in the first embodiment, the MOS regions  215   a  and  215   b  are directly adjacent to each other without any trench therebetween.  FIG. 8   a  is a top view of the resulting structure, and  FIG. 8   b  is a planar view taken along line AA′ in  FIG. 1   a.    
         [0033]    Then a step similar to that in the first embodiment is performed to form a dielectric material having a stress in the trenches  220  to fill the trenches, and the dielectric material includes, but not limited to, a strained nitride  230 , as shown in  FIG. 9 . 
         [0034]    At least the strained nitride  230  in the trenches, which is adjacent to the position (the area surrounded by dashed lines in  FIG. 10   a ) where a channel is to be formed on each of the MOS regions ( 215   a,    215   b ), is removed, and the portions having the strained nitride removed respectively form exposed regions  2251 ,  2252 ,  2253  and  2254 . In the channel length direction, the boundary of each exposed region is substantially aligned with the boundary of the position where a channel is to be formed. The word “substantially” herein means that the boundary of the exposed region is aligned with the boundary of the position where a channel is to be formed within the range of process tolerance. Positions C, S and D in the figures correspond to the channel to be formed, the source to be formed and the drain to be formed, respectively. In another embodiment, any one of the boundaries of exposed regions  2251 ,  2252 ,  2253  and  2254  can extend along the direction of the length of the channel to be formed (the direction indicated by the double-headed arrow line in  FIG. 10   b ) until it is aligned with the boundary of the corresponding MOS region. The method of removing the strained nitride includes, but is not limited to, RIE selective to the materials thereunder. 
         [0035]    In the case where the MOS device is an nMOS device, after removing the tensile strained nitride in the trenches corresponding to the position where a channel is to be formed in each of the MOS regions, owing to the corner effect, the tensile stress of the tensile strained nitride  230  at the periphery of each of the MOS regions is more concentrating in the channel, thereby generating a larger stress. In the case where the MOS device is a pMOS device, after removing the compressive strained nitride in the trenches corresponding to the position where a channel is to be formed in each of the MOS regions, owing to the corner effect, the compressive stress of the compressive strained nitride  230  at the periphery of each of the MOS regions is more concentrating in the channel, thereby generating a larger stress. 
         [0036]    Taking the case shown in  FIG. 10  as an example, a step similar to that of the first embodiment proceeds to form a MOS device, wherein a channel is formed at a position (position C in  FIG. 10 ) where a channel is to be formed, a gate is formed above the channel, and a source and a drain are formed at both sides of the channel (positions S and D in  FIG. 10 ), as shown in  FIG. 11 .  FIG. 11   a  is a top view after the step, and  FIG. 11   b  is a sectional view taken along line AA′ in  FIG. 11   a.    
       Third Embodiment 
       [0037]    First, a semiconductor substrate  300  is provided, and it can be of any type known in the field of electronics, such as a bulk semiconductor, and Semiconductor On Insulator (SOI). The material of the substrate can be monocrystalline silicon, gallium arsenide, indium phosphide, etc. In one specific embodiment, the semiconductor substrate  300  is a silicon substrate with (100) crystal orientation or (110) crystal orientation. The selection of the crystal orientation depends on requirements for the performance of the finished device, and the substrate with (100) crystal orientation can help to increase mobility of electrons in the device, while the substrate with (110) crystal orientation can help to increase mobility of holes in the device, and the electron mobility is greater than the hole mobility due to their properties. Therefore, in a CMOS device, for example, if it is desired that the performance of the pMOS device therein is as close as possible to the performance of the nMOS device, then the substrate with (110) crystal orientation is preferable; and if a higher performance of the nMOS device is desired, then the substrate with (100) crystal orientation is preferable. In addition, the provided semiconductor substrate may be P-type, N-type or un-doped. 
         [0038]    Next, the step of forming trenches and MOS regions surrounded by the trenches on the semiconductor substrate is performed. 
         [0039]    To this end, a hard mask is first formed in an embodiment. In one specific embodiment, an oxide  305  is first formed on the semiconductor substrate  300 , and it includes, but is not limited to, SiO 2 , and has a thickness within the range of about 5-20 nm, for example. The method of forming the oxide includes, but is not limited to, Chemical Vapor Deposition (CVD), Plasma Assisted CVD, Atomic Layer Deposition (ALD), vapor deposition, reactive sputtering, chemical solution deposition or other similar deposition techniques. As a substitute, the oxide may also be formed by a thermal oxidation technology or by a combination of thermal oxidation technology and deposition technology. For example, in the case where the substrate is formed of Si, thermal oxidation is performed on the silicon substrate to form a thin SiO 2 , and then the rest SiO 2  is deposited to reach a predetermined height using a deposition technology. 
         [0040]    Next, a nitride  310  is formed on the oxide  305 . The nitride includes, but is not limited to, SiN and Si 3 N 4 , and the thickness thereof is, for example, within a range of about 50-150 nm. The method of forming the nitride includes, but is not limited to, Chemical Vapor Deposition (CVD), Plasma Assisted CVD, Atomic Layer Deposition (ALD), vapor deposition, reactive sputtering, chemical solution deposition or other similar deposition techniques. 
         [0041]    Then, the oxide and nitride are patterned to form a patterned hard mask, and parts of the substrate are removed by means of the patterned hard mask so as to form trenches in the substrate, and the un-removed substrate corresponds to the MOS regions. In one specific embodiment, the nitride  310  and oxide  305  are patterned, and parts of the semiconductor substrate  300  are removed to form trenches  320  and MOS regions  315   a  and  315   b  surrounded by the trenches. There is also a trench between the MOS regions  315   a  and  315   b.    FIG. 12   a  is a top view of the resulting structure, and  FIG. 12   b  is a planar view taken along line AA′ in  FIG. 12   a . Two MOS regions are shown in the figure, but this is only an example and more than two MOS regions can be formed on the substrate. The methods for patterning and removing include, but are not limited to, dry etching and wet etching, and Reactive Ion Etching (RIE) is preferable. 
         [0042]    The method for forming trenches includes, but is not limited to, the above-mentioned method. In yet another embodiment, the trenches can be formed by directly cutting the substrate using a cutting technology. More generally, the trenches can be formed by any appropriate method in the art. 
         [0043]    Then, a step of filling the trenches with a dielectric material having a stress is performed, the dielectric material having a stress including, but not limited to, strained nitride. 
         [0044]    To this end, in one specific embodiment, a strained nitride  330  is formed in a trenches  320  to fill the trenches, as shown in  FIG. 14 .  FIG. 14   a  is a top view of the resulting structure, and  FIG. 14   b  is a planar view taken along line AA′ in  FIG. 14   a . It can be seen from  FIG. 14   a  that the MOS regions are completely surrounded by the strained nitride  330 . In the case where the MOS to be made is an nMOS, the nitride should have a compressive stress, while in the case where the MOS to be made is a pMOS, the nitride should have a tensile stress. Specifically, the structure can be formed by depositing the strained nitride  330  and by etching back or Chemical Mechanical Polishing (CMP) the nitride. In one specific embodiment, the structure can be formed by depositing the strained nitride  330  and by etching back or Chemical Mechanical Polishing (CMP) the nitride. 
         [0045]    In the specific embodiment where the trenches are formed by directly cutting the substrate, the structure can be formed by depositing the strained nitride  330  and by etching back or CMP the nitride to expose the substrate in the MOS regions. 
         [0046]    Preferably, before filling the strained nitride, a layer of oxide  325  is formed in the trenches. The method of forming the oxide includes, but is not limited to, Chemical Vapor Deposition (CVD), Plasma Assisted CVD, Atomic Layer Deposition (ALD), vapor deposition, reactive sputtering, chemical solution deposition or other similar deposition techniques. The oxide functions as a buffer layer between the strained nitride and the substrate. In the specific embodiment where the hard mark is used, the oxide  325  also exists on the MOS regions, as shown in  FIG. 13 . In the specific embodiment where the trenches are formed by directly cutting the substrate, the oxide  325  does not exist on the surface of the exposed substrate in the MOS regions. 
         [0047]    Next, a step of removing a part of the strained nitride in the trenches is performed. 
         [0048]    To this end, at least the strained nitride  330  in the trenches at outer sides of the ends of the two MOS regions ( 315   a,    315   b ) that are away from each other is removed, and the portions having the strained nitride removed respectively form exposed regions  3251  and  3252 . In the channel length direction, the boundary of each exposed region is substantially aligned with the boundary of the corresponding MOS region. The word “substantially” herein means that the boundary of the exposed region is aligned with the boundary of the corresponding MOS region within the range of process tolerance. In another embodiment, any one of the exposed regions  3251  and  3252  can extend toward the direction of the channel to be formed along the direction of the length of the channel (the direction indicated by the double-headed arrow line in  FIG. 15   b ) until reaching the boundary of the position where a channel is to be formed. Positions C, S and D in  FIG. 15   b  respectively correspond to the channel to be formed, the source to be formed and the drain to be formed.  FIGS. 15   c  and  15   d  are sectional views taken along lines AA′ and BB′ in  FIG. 15   b , respectively. The method of removing the strained nitride includes, but is not limited to, RIE selective to the materials thereunder. 
         [0049]    In the case where the MOS device is an nMOS device, after removing the compressive strained nitride in the periphery, owing to the corner effect, the compressive stress of the remaining compressive strained nitride  330  is more concentrating in the channel, thereby generating a larger stress. In the case where the MOS device is a pMOS device, after removing the tensile strained nitride in the periphery, owing to the corner effect, the tensile stress of the remaining tensile strained nitride  330  is more concentrating in the channel, thereby generating a larger stress. 
         [0050]    The following describes the case shown in  FIG. 15   b.    
         [0051]    The exposed regions are filled with a dielectric material  335 , such as an oxide. In the specific embodiment where the hard mask is used, the step is realized through depositing the dielectric material  335  and planarizing it by etching back or a CMP technology until exposing the hard mask on the MOS regions, as shown in  FIG. 16 . Wherein,  FIG. 16   a  is a top view after the step, and  FIGS. 16   b  and  16   c  are sectional views taken along lines AA′ and BB′ in  FIG. 16   a . In the specific embodiment where the trenches are formed by directly cutting the substrate, the structure can be formed through depositing the dielectric material  135  and etching back or CMP the dielectric material  335  to expose the substrate in the MOS regions. 
         [0052]    In the specific embodiment where the hard mask is used, there is a further step of removing the nitride  310 , as shown in  FIGS. 17   a  and  17   b . Wherein,  FIGS. 17   a  and  17   b  are sectional views taken along lines AA′ and BB′, respectively. The method of removing the nitride  310  includes but is not limited to RIE selective to the dielectric material  335 . In this step, the strained nitride  330  is covered by the dielectric material  335  and thus is not influenced. Subsequently, the oxide  305  on the MOS regions is removed to expose the substrate  300  thereon. Meanwhile, the dielectric material  335  of a certain thickness is also removed. 
         [0053]    Next, a MOS device is formed using a conventional MOS technology, wherein a channel is formed at a position (position C of  FIG. 15 ) where a channel is to be formed, a gate is formed above the channel, and a source and a drain are formed at both sides of the channel (positions S and D of  FIG. 15 ), as shown in  FIG. 18 .  FIG. 18   a  is a top view after the step and  FIG. 18   b  is a sectional view taken along line AA′ in  FIG. 18   a.    
       Fourth Embodiment 
       [0054]    The fourth embodiment is substantively the same as the third embodiment, so descriptions below focus on the differences, while the parts that are the same as the third embodiment will not be elaborated any more. 
         [0055]    A similar substrate as that in the third embodiment is provided. 
         [0056]    Two MOS regions and trenches surrounding the MOS regions are formed, unlike in the third embodiment, the two MOS regions are directly adjacent to each other without any trench therebetween, which is similar to the case shown in  FIG. 8 . 
         [0057]    Then a step similar to that in the first embodiment is performed to form a dielectric material having a stress in the trenches to fill the trenches, the dielectric material including, but not limited to, a strained nitride, which is similar to the case shown in  FIG. 9 . 
         [0058]    At least the strained nitride in the trenches at outer sides of the ends of the two MOS regions that are away from each other is removed, and the portions having the strained nitride removed respectively form exposed regions  4251  and  4252 . In the channel length direction, the boundary of each exposed region is substantially aligned with the boundary of the corresponding MOS region. The word “substantially” herein means that the boundary of the exposed region is aligned with the boundary of the corresponding MOS region within the range of process tolerance. In another embodiment, any one of the exposed regions  4251  and  4252  can extend toward the direction of the channel to be formed along the direction of the length of the channel (the direction indicated by the double-headed arrow line in  FIG. 19   b ) until reaching the boundary of the position where a channel is to be formed. Positions C, S and D in  FIG. 19   b  correspond to the channel to be formed, the source to be formed and the drain to be formed, respectively. The method of removing the strained nitride includes, but is not limited to, RIE selective to the materials thereunder. 
         [0059]    In the case where the MOS device is an nMOS device, after removing the compressive strained nitride in the periphery, owing to the corner effect, the compressive stress of the remaining compressive strained nitride  430  is more concentrating in the channel, thereby generating a larger stress. In the case where the MOS device is a pMOS device, after removing the tensile strained nitride in the periphery, owing to the corner effect, the tensile stress of the remaining tensile strained nitride  430  is more concentrating in the channel, thereby generating a larger stress. 
         [0060]    Then, a MOS device is formed, wherein a channel is formed at the position where a channel is to be formed, a gate is formed above the channel and a source and a drain are formed at both sides of the channel. 
         [0061]    The above described four embodiments are merely preferred embodiments of the present invention, and do not intend to limit the present invention. Therefore, various modifications and variations can be made to the present invention without departing from the principle of the technical method of the present invention and the protection scope of the attached claims.