Abstract:
A polyphase filter having metal-insulator-semiconductor (MIS) capacitors in which the whole body of the polyphase filter is fabricated as an IC. Resistors are individually combined with the capacitors to form serial connection circuits and every four signal connection circuits individually form bridge circuits that are connected in a cascade manner. When the MIS capacitors are fabricated into an IC, capacitors that are parasitic to the MIS capacitors are connected to the input sides of the resistors.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a polyphase filter and a receiver using thereof. 
     2. Description of the Related Art 
     With regard to digital audio broadcasting system, DAB (Digital Audio Broadcasting complies with Eureka 147 standard) system is adopted in Europe, and ISDB-T (Integrated Services Digital Broadcasting for Terrestrial) system is proposed in Japan. 
     ISDB-T system employs: 
     transmission band width of 432 kHz (for narrow-band ISDB-T system); 
     modulation system of OFDM (Orthogonal Frequency Division Multiplex); and 
     multiplexing system of MPEG2 (Moving Picture Experts Group 2); which enable simultaneous broadcasting of digital audio data and digital data in a plurality of channels. Broadcasting based on the narrow-band ISDB-T system is now planned to use the current VHF television broadcasting band. 
     One example of an ISDB-T receiver is typically composed as shown in FIG.  5 . The figure shows a narrow-band ISDB-T receiver employing a super heterodyne configuration. 
     Broadcasting wave based on the narrow-band ISDB-T system is received by an antenna  11 , the received signal is then fed to an antenna tuning circuit  12  based on the electronic tuning system, thereby a received signal S RX  having a target frequency is extracted. The extracted signal S RX  is then fed to mixer circuits  15 I,  15 Q via a variable gain amplifier  13  and an inter-stage tuning circuit  14  based on the electronic tuning system. 
     On the other hand, an oscillation signal having a predetermined frequency is generated by a PLL (Phase Locked Loop)  31 , the oscillation signal from the PLL  31  is then fed to a frequency dividing circuit  32 , where the oscillation signal is divided into two signals having a frequency higher, for example, by 500 kHz than a carrier frequency (center frequency) of the received signal S RX  and differ by 90° with each other in phase, the divided signals are then supplied to the mixer circuits  15 I,  15 Q as local oscillation signals. 
     Thus the received signal S RX  is frequency-converted at the mixer circuits  15 I,  15 Q to generate two intermediate frequency signals S IFI  and S IFQ  (having a center frequency of 500 kHz) differ by 90° with each other in phase, that is, an in-phase intermediate frequency signal S IFI  and a quadrature intermediate frequency signal S IFQ  orthogonal with each other. 
     In this process, a part of control voltage supplied from the PLL  31  to a variable capacity diode (not shown) of its VCO (Voltage Controlled Oscillator), is extracted, and the extracted control voltage is fed to the tuning circuit  12  as a tuning voltage, which allows tuning to the received signal S RX . 
     The intermediate frequency signals S IFI  and S IFQ  from the mixer circuits  15 I,  15 Q are then individually supplied to phase shifting circuits  17 I,  17 Q via the low pass filters  16 I,  16 Q, where the signals S IFI  and S IFQ  are phase-shifted by φ and φ+90°, respectively. The phase-shifted signals are then supplied to an adder circuit  18 , from which an intermediate frequency signal S IF  having only a desired signal component is extracted while image signal components being canceled. 
     The intermediate frequency signal S IF  is then supplied on a signal line comprising a bandpass filter  19  for filtering intermediate frequency component, a variable gain amplifier  21  for AGC (Automatic Gain Control) and a low pass filter  22  to a demodulation circuit  23 , where the signal is subjected to demodulation processing corresponded to the modulation processing at the time of the ISDB-T transmission, and audio signals L, R of a desired program selected from a plurality of programs (channels) are extracted from such demodulation circuit  23 . 
     Such receiver can be integrated into an one-chip integrated circuit (IC) except the tuning circuits  12 ,  14 , an oscillation circuit of VCO in the PLL  31  and the demodulation circuit  23 . 
     The phase shifting circuits  17 I,  17 Q and the adder circuit  18  now can be composed by a polyphase filter  17  as shown in FIG.  6 . 
     In this configuration, a serial connection circuit consisting of a resistor R 11  and a capacitor C 11  is inserted between input terminals  17 A and  17 B; a serial connection circuit consisting of a resistor R 21  and a capacitor C 21  is inserted between input terminals  17 B and  17 C; a serial connection circuit consisting of a resistor R 31  and a capacitor C 31  is inserted between input terminals  17 C and  17 D; and a serial connection circuit consisting of a resistor R 41  and a capacitor C 41  is inserted between input terminals  17 D and  17 A. 
     A serial circuit consisting of a resistor R 12  and a capacitor C 12  is inserted between the output side of the resistor R 11  (connection point of the resistor R 11  and the capacitor C 11 ) and the output side of the resistor R 21  (connection point of the resistor R 21  and the capacitor C 21 ); a serial circuit consisting of a resistor R 22  and a capacitor C 22  is inserted between the output sides of the resistor R 21  and the output side of the resistor R 31 ; a serial circuit consisting of a resistor R 32  and a capacitor C 32  is inserted between the output side of the resistor R 31  and the output side of the resistor R 41 ; and a serial circuit consisting of a resistor R 42  and a capacitor C 42  is inserted between the output side of the resistor R 41  and the output side of the resistor R 11 . 
     Similarly, serial connection circuits individually consisting of resistors R 13  to R 43  and capacitors C 13  to C 43  are connected to the respective output sides of the resistors R 12  to R 42 . The individual output sides of the resistors R 13  and R 23  are connected to an output terminal  17 E, and the individual output sides of the resistors R 33  and R 43  are connected to an output terminal  17 F. 
     The outputs from the low pass filters  16 I and  16 Q are balanced type, and the intermediate frequency signal S IFI  output from the low pass filter  16 I is supplied between the output terminals  17 A and  17 C, and the intermediate frequency signal S IFQ  output from the low pass filter  16 Q is supplied between the output terminals  17 B and  17 D. Thus an intermediate frequency signal having only a desired signal component is output in a balanced type between the output terminals  17 E and  17 F while image signal components being canceled. 
     Such polyphase filter  17  is advantageous in that it can be fabricated into an IC, and in that it is stable in the characteristic against non-uniformity in the fabrication of the IC devices and can ensure thorough elimination of the image signal component according to the foregoing method, since the resistors R 11  to R 43  and the capacitors C 11  to C 43  composing the polyphase filter  17  are in bridge connection. 
     In the polyphase filter  17 , a frequency f 17  receiving 90° phase shifting is now expressed as 
     
       
           f   17 =1/(2 πCR ) 
       
     
     where, CR is a product of values for the resistors and the capacitors in the individual stages. The number of the stages of the polyphase filter  17  is determined based on the amount of attenuation required for suppressing the image signal components and specific band. 
     When fabricating the polyphase filter  17  into an IC, the capacitors C 11  to C 43  can be constituted by a metal-insulator-semiconductor (MIS) capacitor as shown in FIG.  7 A. In this figure, on a p-type semiconductor substrate  71 , formed are an n-type epitaxial layer  72 , an n + -type buried region  73  and a p + -type isolation region  74 . 
     An n + -type semiconductor layer  75  is formed in a superficial area of the epitaxial layer  72 , and thereon an SiO 2  layer  76  and an extra thin insulating layer  77  are formed. Further thereon an electrode  78  is formed so as to contact the semiconductor layer  75 , and an electrode  79  is formed so as to be opposed to the n + -type semiconductor layer  75  while being interposed by the insulating layer  77 . The electrodes  78 ,  79  are generally made of aluminum. 
     The electrode  78 , the insulating layer  77  and the n + -type semiconductor layer  75  are thus combined to form a capacitor Cm as shown in FIG. 7B, where the electrodes  78  and  79  serves as outlet terminals of the capacitor Cm. The symbol “r” represents resistance component of the n + -type semiconductor layer  75 . In the polyphase filter  17  fabricated in an IC, the capacitors C 11  to C 43  can individually be materialized by such MIS-type capacitor Cm. 
     The MIS-type capacitor Cm is advantageous in that reducing the occupied area of the capacitors C 11  to C 43  in the polyphase filter  17  fabricated in an IC, since the capacitor of this type has a large capacitance per unit area. 
     In the MIS-type capacitor Cm, however, the semiconductor layer  75  is electrically connected to the buried region  73  via the epitaxial layer  72 , and the buried layer  73  and the substrate  71  together form a p-n junction. This is equivalent to that, as shown in FIG. 7C, a p-n junction Ds contributed by the buried layer  73  and the substrate  71  is connected on the electrode  79  side of the capacitor Cm. 
     The p-n junction Ds is reversely biased when the MIS-type capacitor Cm operates, so that, as shown in FIG. 7D, the p-n junction Ds will act as a parasitic capacitor Cs. The parasitic capacitor Cs accounts for 5 to 10% of the main capacitor Cm, and the influence thereof on the polyphase filter  17  is not negligible. 
     FIG. 8 shows an equivalent circuit of the polyphase filter  17  in which the capacitors C 11  to C 43  are materialized as the MIS capacitor Cm, where the parasitic capacitor Cs also inclusive. The parasitic capacitors Cs appear on the output side of every stage. The parasitic capacitors Cs, and the resistors R 11  to R 43  in the previous stage thereof individually form low pass filters, which will lower the levels of the intermediate frequency signals S IFI  and S IFQ  passing through the polyphase filter  17 . 
     It is thus necessary to compensate such lowering in the signal level, either by enhancing the drive ability of the output stage of the low pass filters  16 I,  16 Q in the former stage of the polyphase filter  17 , or by raising the gain as well as reducing noise of the band pass filter  19  in the latter stage. Both methods, however, can merely compensate the signal loss in the polyphase filter  17 , and cannot be an essential solution. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to solve the foregoing problem. 
     According to one aspect of the present invention, provided is a polyphase filter including a plurality of bridge circuits in a cascade connection, each bridge circuit being composed of four sets of serial connection circuit, and each serial connection circuit being composed of a resistor and a capacitor serially connected thereto, wherein the polyphase filter as a whole is fabricated into an integrated circuit; the capacitor is composed of a metal-insulator-semiconductor capacitor; and the metal-insulator-semiconductor capacitor is fabricated into the integrated circuit so that a parasitic capacitor accompanying said metal-insulator-semiconductor capacitor is connected to a connection point between the serial connection circuits. 
     According to another aspect of the present invention, provided is a polyphase filter including a plurality of bridge circuits, each bridge circuit being composed of four sets of serial connection circuit, and each serial connection circuit being composed of a resistor and a capacitor serially connected thereto, connection points between each adjacent ones of four serial connection circuits being provided as signal input terminals, connection points between the individual resistors and the individual capacitors in the individual serial connection circuits being provided as signal output terminals, a plurality of the bridge circuits being individually connected in a cascade manner via the signal input terminal and the signal output terminal, a first input signal being supplied to a first pair of the opposing signal input terminals of the bridge circuit in the first stage of a plurality of the bridge circuits in the cascade connection, a second input signal being supplied to a second pair of the opposing signal input terminals of the bridge circuit in the first stage, a first pair of the adjacent signal output terminals of the bridge circuits in the last stage of the bridge circuits in the cascade connection being connected with each other to provide a first signal output terminal, a second pair of the adjacent signal output terminals of the bridge circuits in the last stage being connected with each other to provide a second signal output terminal, so as to obtain output signals from the first and second signal output terminals; wherein the polyphase filter as a whole is fabricated into an integrated circuit; the capacitor is composed of a metal-insulator-semiconductor capacitor; and the metal-insulator-semiconductor capacitor is fabricated into the integrated circuit so that a parasitic capacitor accompanying said metal-insulator-semiconductor capacitor is connected to a connection point between the serial connection circuits composing the individual bridge circuits. 
     According to still another aspect of the present invention, provided is a receiver comprising: 
     a tuning circuit for extracting a signal to be received having a target frequency from received signals; 
     a first mixer circuit and a second mixer circuit to which the signal to be received extracted by the tuning circuit is supplied; 
     a circuit for supplying to the first and the second mixer circuits a first local oscillation signal and a second local oscillation signal being differed by 90° with each other in phase; 
     a polyphase filter to which a first intermediate frequency signal and a second intermediate frequency signal being differed by 90° with each other in phase output from the first and the second mixer circuits are supplied; and a demodulation circuit to which an output signal from the polyphase filter is supplied; wherein, the polyphase filter is as a whole fabricated into an integrated circuit; and includes a plurality of bridge circuits in a cascade connection, each bridge circuit being composed of four sets of serial connection circuit, and each serial connection circuit being composed of a resistor and a capacitor serially connected thereto; the capacitor being composed of a metal-insulator-semiconductor capacitor; and the metal-insulator-semiconductor capacitor being fabricated into the integrated circuit so that a parasitic capacitor accompanying said metal-insulator-semiconductor capacitor is connected to a connection point between the serial connection circuits composing the individual bridge circuits. 
     According to the present invention, effects of the parasitic capacitor which is likely to be produced when the capacitor of the polyphase filter is materialized by the MIS capacitor can be reduced, and thus a desired phase shifting characteristic can be obtained without correcting the transit characteristic of the polyphase filter. 
     It is also unnecessary to raise the gain in the former stage of the polyphase filter, nor to raise the gain and to reduce noise in the latter stage. This allows the receiver using such polyphase filter to improve its image signal characteristic. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a system diagram showing an embodiment of the present invention; 
     FIG. 2 is a connection diagram showing an embodiment of the present invention; 
     FIG. 3 is a connection diagram showing an embodiment of the present invention; 
     FIG. 4 is a characteristic diagram for explaining the present invention; 
     FIG. 5 is a system diagram showing an embodiment of the related art; 
     FIG. 6 is a connection diagram showing an embodiment of the polyphase filter; 
     FIG. 7A is a sectional view and FIGS. 7B to  7 D are connection diagrams for explaining the MIS capacitor; and 
     FIG. 8 is a connection diagram for explaining the related art. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Digital Audio Broadcasting Receiver 
     A digital audio broadcasting receiver is composed, for example, as shown in FIG.  1 . The figure shows a narrow-band ISDB-T receiver and is based on a super heterodyne configuration. In this figure, basically the same reference numerals are used as used in FIG. 5 for easy understanding of the present invention. 
     Broadcasted wave based on the narrow-band ISDB-T system is received by an antenna  11 , the received signal is then fed to an antenna tuning circuit  12  based on the electronic tuning system, thereby a received signal S RX  having a target frequency is extracted. The extracted signal S RX  is then fed to mixer circuits  15 I,  15 Q via a variable gain amplifier  13  and an inter-stage tuning circuit  14  based on the electronic tuning system. 
     On the other hand, an oscillation signal having a predetermined frequency is generated by a PLL  31 , the oscillation signal from the PLL  31  is fed to a frequency dividing circuit  32 , where the oscillation signal is divided into two signals having a frequency higher, for example, by 500 kHz than a carrier frequency (center frequency) of the received signal S RX  and differ by 90° with each other in phase, the divided signals are then supplied to the mixer circuits  15 I,  15 Q as local oscillation signals. 
     Thus the received signal S RX  is frequency-converted in the mixer circuits  15 I,  15 Q to generate two intermediate frequency signals S IFI  and S IFQ  (with a center frequency of 500 kHz) differ with each other in phase by 90°, that is, an in-phase intermediate frequency signal S IFI  and a quadrature intermediate frequency signal S IFQ  orthogonal with each other. 
     In this process, a part of control voltage supplied from the PLL  31  to a variable capacity diode (not shown) of its VCO (Voltage Controlled Oscillator), is extracted, and the extracted control voltage is fed to the tuning circuit  12  as a tuning voltage, which allows tuning to the received signal S RX . 
     The intermediate frequency signals S IFI  and S IFQ  from the mixer circuits  15 I,  15 Q are then supplied to a polyphase filter  17  having a constitution described later, and therefrom an intermediate frequency signal S IF  having only a desired signal component is extracted while image signal components being canceled. 
     The intermediate frequency signal S IF  is then supplied on a signal line comprising a band pass filter  19  for filtering intermediate frequency component, a variable gain amplifier  21  for AGC (Automatic Gain Control) and a low pass filter  22  to a demodulation circuit  23 . The demodulation circuit  23  is responsible for various demodulation processes corresponding the modulation processing at the time of the ISDB-T transmission, which include complex Fourier transformation, frequency de-interleaving, time de-interleaving, selection of digital audio data for a target channel from two or more channels, error correction and data expansion. 
     Audio signals L, R of a desired program selected from a plurality of programs (channels) are extracted from such demodulation circuit  23 . 
     On the other hand, the intermediate frequency signal S IF  from the low pass filter  22  is supplied to an AGC detection circuit  35  to generate an AGC voltage V 35 , which is supplied to the variable gain amplifier  21  as a gain control signal. 
     The intermediate frequency signals S IFI , S IFQ  from the low pass filters  16 I,  16 Q are supplied to the AGC detection circuit  33  to generate a delayed AGC voltage V 33 , which is supplied to an adder circuit  34 . Also the AGC voltage V 35  is supplied to the adder circuit  34 . From the adder circuit  34  obtained is an summed voltage V 34  of the delayed AGC voltage V 33  and the AGC voltage V 35 , and the summed voltage V 34  is then supplied to the variable gain amplifier  13  as a gain control signal. 
     Thus automatic gain control is effected using the AGC voltage V 34  on the received signal S RX  from the tuning circuit  12 , and is also effected using the AGC voltage V 35  on the intermediate frequency signal S IF  from the band pass filter  19 . 
     Such receiver can be integrated into an one-chip IC except the tuning circuits  12 ,  14 , an oscillation circuit of VCO in the PLL  31  and the demodulation circuit  23 . 
     The Polyphase Filter  17   
     It is generally known that loss in the polyphase filter can be suppressed by setting the impedance so as to increase from the bridge circuit in the input stage toward the bridge circuit in the output stage. Thus the value of the resistors in the bridge circuits are generally selected so as to increase towards the latter stage. 
     From this aspect, the present invention is to relieve the polyphase filter  17  from characteristic degradation due to parasitic capacitor Cs when the capacitors in the polyphase filter  17  are configured as MIS capacitors. 
     Thus the polyphase filter  17  is constituted, for example, as shown in FIG.  2 . The figure shows an exemplary case of the five-stage polyphase filter  17  having five bridge circuits  171  to  175 . 
     In this configuration, a serial connection circuit consisting of a resistor R 11  and a capacitor C 11  is inserted between input terminals  17 A and  17 B; a serial connection circuit consisting of a resistor R 21  and a capacitor C 21  is inserted between input terminals  17 B and  17 C; a serial connection circuit consisting of a resistor R 31  and a capacitor C 31  is inserted between input terminals  17 C and  17 D; and a serial connection circuit consisting of a resistor R 41  and a capacitor C 41  is inserted between input terminals  17 D and  17 A. A bridge circuit  171  in the first stage of the polyphase filter  17  is thus configured. 
     A serial circuit consisting of a resistor R 12  and a capacitor C 12  is inserted between the output side of the resistor R 11  and the output side of the resistor R 21 ; a serial circuit consisting of a resistor R 22  and a capacitor C 22  is inserted between the output sides of the resistor R 21  and the output side of the resistor R 31 ; a serial circuit consisting of a resistor R 32  and a capacitor C 32  is inserted between the output side of the resistor R 31  and the output side of the resistor R 41 ; and a serial circuit consisting of a resistor R 42  and a capacitor C 42  is inserted between the output side of the resistor R 41  and the output side of the resistor R 11 . A bridge circuit  172  in the second stage of the polyphase filter  17  is thus configured. 
     Similarly, resistors R 13  to R 43  and capacitors C 13  to C 43  are connected to the bridge circuit  172  to provide a bridge circuit  173  of the third stage of the polyphase filter  17 ; and also similarly, the resistors R 14  and R  44  are connected to an output terminal  17 E, and resistors R 14  to R 44  and capacitors C 14  to C 44  are connected to the bridge circuit  173  to provide a bridge circuit  174  of the fourth stage. Moreover, resistors R 15  to R 45  and capacitors C 15  to C 45  are similarly connected to the bridge circuit  174  to provide a bridge circuit  175  of the fifth stage. 
     The individual output sides of the resistors R 15  and R 25  are connected to an output terminal  17 E, and the individual output sides of the resistors R 35  and R  45  are connected to an output terminal  17 F. Load resistors R 71 , R 72  are respectively connected between the output terminals  17 E,  17 F and the ground. 
     The polyphase filter  17  intended for use in the receiver previously shown in FIG. 1 can be integrated into an IC together with the circuits of the receiver, where individual capacitors C 11  to C 45  are configured, for example, by the MIS capacitor Cm shown in FIG.  7 . 
     When the polyphase filter  17  is intended to be integrated into an IC, the MIS capacitor Cm is fabricated into the IC so that, as shown in FIG. 3 representatively illustrating the bridge circuit  171 , terminals (electrodes)  78 ,  78  of the capacitors C 11  to C 41  (capacitance Cm, Cm) are connected to the output side of the resistors R 11  to R 41 , and so that the terminals (electrodes)  79 ,  79  are connected to the input side of the resistors R 21  to R 41  and R 11 . The bridge circuits  172  to  175  are also integrated into the IC in a similar manner. 
     To suppress loss in the polyphase filter  17 , the values for the resistors R 11  to R 45  in the bridge circuits  171  to  175  are generally selected so as to increase toward the latter stage. 
     The number of the stages of the polyphase filter  17  is determined based on the amount of attenuation required for suppressing the image signal components and specific band. In the polyphase filter  17 , a frequency f 17  receiving 90° phase shifting is now expressed as 
     
       
           f   17 =1/(2 πCR ) 
       
     
     where, CR is a product of values for the resistors and the capacitors in the individual stages. Preferable setting relates to: 
     R 11 =R 21 =R 31 =R 41 ; 
     R 12 =R 22 =R 32 =R 42 ; 
     R 13 =R 23 =R 33 =R 43 ; 
     R 14 =R 24 =R 34 =R 44 ; 
     R 15 =R 25 =R 35 =R 45 ; and 
     R 11 :R 12 :R 13 :R 14 :R 15 =1:2:4:4:8 
     Preferable setting also relates to: 
     R 71 =R 72 ; and 
     R 11 :R 71 =1:10 
     It is preferable that the values for the load resistors R 71 , R 72  are larger than those for the resistors R 15 , R 25 , R 35 , R 45  and R 55  of the bridge circuit in the last stage so as to suppress loss in such loads resistors. 
     The outputs from the low pass filters  16 I and  16 Q are balanced type, and the intermediate frequency signal S IFI  output from the low pass filter  16 I is supplied between the output terminals  17 A and  17 C, and the intermediate frequency signal S IFQ  output from the low pass filter  16 Q is supplied between the output terminals  17 B and  17 D. Thus an intermediate frequency signal having only a desired signal component is output in a balanced type between the output terminals  17 E and  17 F while image signal components being canceled. 
     It is now apparent from comparison between the polyphase filters  17  shown in FIG.  2  and FIG. 8, assuming that the both having an equal number of stages of the bridge circuits, that the polyphase filter  17  shown in FIG. 2 will have the low pass filters contributed by the parasitic capacitor Cs and the resistors in the former stage thereof but will have no low pass filters in the bridge circuit  175  in the last stage, so that the total number of the stages of the low pass filters will be subtracted by one. 
     The polyphase filter  17  shown in FIG. 2 is also advantageous in that effects of the parasitic capacitors Cs, Cs of the bridge circuit  171  in the first stage can be reduced by lowering the output impedance of the low pass filters  16 I,  16 Q provided in the former stage thereof. 
     The polyphase filter  17  shown in FIG. 2 is still also advantageous in that no low pass filters are produced on the output sides of the resistors R 15  to R 45  of the bridge circuit  175  in the last stage having a largest impedance since no parasitic capacitors Cs, Cs are connected thereto. 
     From three these viewpoints, the polyphase filter  17  shown in FIG. 2 can be improved in its frequency characteristic, and can limit the signal attenuation even if the MIS capacitor Cm is accompanied by the parasitic capacitor Cs. 
     In FIG. 4, solid line “A” indicates an output level of the polyphase filter  17  shown in FIG. 2 supplied with an image signal, assuming an output level of the desired wave signal as a reference level (=0 dB). A target band extends from 200 kHz to 1 MHz. It is found from the characteristic curve “A” that the image signal is successfully reduced as much as 69 dB or more within the target band. 
     Broken line “B” in FIG. 4 indicates an output level of the desired wave signal of the polyphase filter  17  shown in FIG. 8 configured in five stages, also assuming an output level of the desired wave signal of the polyphase filter  17  shown in FIG. 2 as a reference level (=0 dB). 
     It is found from the characteristic curve “B” that the polyphase filter  17  shown in FIG. 8 with a five-stage configuration can only afford an output level of the desired wave signal lower by 4 dB as compared with that for the polyphase filter  17  shown in FIG.  2 . In other words, the polyphase filter  17  shown in FIG. 2 is improved in the output level of the desired wave signal by 4 dB at maximum as compared with that for the polyphase filter  17  shown in FIG. 8 with a five-stage configuration. 
     According to the polyphase filter  17  shown in FIG. 2, even if the capacitors C 11  to C 45  thereof are composed by the MIS capacitor Cm, effects of the capacitor Cs parasitic to the MIS capacitor Cm can be reduced, and thus the frequency characteristic of the polyphase filter  17  is prevented from being excessively lowered, which results in leveling of the overall transit characteristic. Connecting the load resistors R 71 , R 72  to the output terminals  17 E,  17 F also contributes further leveling of the transit characteristic. Thus a desired phase shifting characteristic can be obtained without correcting the transit characteristic of the polyphase filter  17 , and the image signal component can be removed, for example, by virtue of the characteristic curve “A” in FIG.  4 . 
     Relieving effects of the parasitic capacitor Cs also result in reduction in loss causative of such parasitic capacitor Cs. This eliminates necessity in enhancing the drive ability of the output stages of the low pass filters  16 I,  16 Q provided in the former stage of the polyphase filter  17 , reduces the power consumption thereof, and reduces the size of the transistors. It is also unnecessary to enhance the gain of the band pass filter  19  in the latter stage nor to reduce the noise thereof.