Abstract:
A semiconductor memory device controls the voltage level of an equalization signal to be a boost voltage VPP for a predetermined time period and then to be an external power supply voltage VDD, when the equalization signal is repeated by a repeater. In order to improve bit line precharging performance of the bit line precharge portion enabled by the equalization signal, a rising interval of the equalization signal is activated as the boost voltage. Precharging is then performed with the external supply voltage after a predetermined time period. Thus, a thin gate insulating membrane can be used in a transistor in the bit line precharge portion which receives the equalization signal can be formed.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to semiconductor design technology, and more particularly, to a method for repeating an equalization signal of a semiconductor memory device.  
       DESCRPITION OF RELATED ARTS  
       [0002]     Recent development trends in semiconductor memory devices provide large capacity and fast operating speed. In addition, it is known that low voltage or low memory power is need for reliable operation under a low supply voltage environment. Especially, a memory embedded in a portable system such as a mobile phone or a notebook computer for mobile communications, to office systems, tends to consume as little power as possible.  
         [0003]     One of these development results is a technology for minimizing the power consumption in a cell core area of a memory. The cell core area is composed of a memory cell, bit lines and word lines, and designed based on a finely itemized design rule. Therefore, the memory cell is of a very small size and thus can use the low power.  
         [0004]     A semiconductor device, DRAM, adopts a bit line precharge operation. The bit line precharge operation, which is followed by a data reading or data writing operation, precharges the bit lines to a predetermined voltage level before an access to data and then fits the levels of the bit lines to an input range of a sense amplifier that judges a logical state of data stored.  
         [0005]     In addition, the DRAM is provided with an equalizer that receives an equalization signal BLEQ for maintaining the bit lines and segment input/output lines, namely, data transmission lines, to be at a constant voltage level in the precharge state.  
         [0006]     When an active command is inputted, the equalization signal BLEQ causes the voltage levels of the bit lines and segment input/output lines that were under the precharge state to be in a floating state to thereby make the DRAM to be in a sensing state. Upon input of a precharge command, the equalization signal BLEQ serves to cause the bit lines and segment input/output lines to have a predetermined voltage level.  
         [0007]      FIG. 1  is a circuit diagram illustrating a cell core area of a conventional semiconductor memory device.  
         [0008]     Referring to  FIG. 1 , the cell core area comprises a cell array  108 , a pair of bit lines BL and /BL, a sense amplifier driver  107 , a sense amplifier  105 , an equalizer  101  for equalizing voltage levels of the pair of bit lines BL and /BL, and a bit line precharge portion  103  for precharging the pair of bit lines BL and /BL and a pull-up line RTO of the sense amplifier driver  107  to a precharge voltage VBLP.  
         [0009]     The equalizer  101  and the bit line precharge portion  103  are driven by the equalization signal BLEQ as set forth above.  
         [0010]     Although there are shown in  FIG. 1  the equalizer  101  and the bit line precharge portion  103  with respect to the single pair of bit lines BL and /BL, the cell array  107  proportional to the capacity of the memory exists in the cell core area and accordingly the equalizer  101  and the bit line precharge portion  103  are as many as the number proportional to the capacity of the memory.  
         [0011]     Therefore, since the equalization signal BLEQ should enable the equalizer  101  and the bit line precharge portion  103  that exist as many as the number proportional to the capacity of the memory, a repeater is arranged to maintain a voltage level of a signal by repeating the signal in order to prevent the voltage level of the signal from being lowered.  
         [0012]      FIG. 2  is circuit diagram illustrating an equalization signal generating circuit and repeater according to the prior art.  
         [0013]     Referring to  FIG. 2 , the equalization signal generating circuit and repeater comprises a signal generator  201  for receiving an upper block selection signal LAX9A and a lower block selection signal LAXBC, which has a logic high level when an active command is input and a logic low level when a precharge command is input and generating an equalization signal BLEQ, a buffer  203  for buffering the output signal of the signal generator  201 , and a repeater  205  for repeating the equalization signal BLEQ that is an output signal of the buffer  203 .  
         [0014]     This prior art equalization signal generating circuit and repeater generates and repeats the equalization signal having a voltage level of an external power supply voltage VDD. There is no defect of enabling the equalizer; but where it receives the equalization signal BLEQ and then enables the bit line pre-charge portion that precharges the bit line pair BL and /BL, it takes a long time to activate the equalization signal BLEQ of low voltage level to a logic high level. This causes the bit line precharge portion to operate slowly, thereby resulting in a slow precharging.  
         [0015]      FIG. 3  is a circuit diagram illustrating an equalization signal generating circuit and repeater according to another prior art embodiment.  
         [0016]     Referring to  FIG. 3 , the equalization signal generating circuit and repeater comprise a signal generating portion  301  for receiving an upper block selection signal LAX9A and a lower block selection signal LAXBC that have a logic high level when an active command is input and a logic low level when a precharge command is input and generating the equalization signal BLEQ, a level shifter  303  for shifting a voltage level of the output signal BLEQ from the signal generating portion  301  to a boost voltage VPP wherein the voltage level is an external power supply voltage VDD, and a repeater  305  for repeating the equalization signal BLEQ whose voltage level is the boost voltage.  
         [0017]     This prior art equalization signal generating circuit and repeater repeats the equalization signal BLEQ having the voltage level of the boost voltage. There is no defect of enabling the equalizer; but where it receives the equalization signal BLEQ and then enables the bit line precharge portion to precharge the bit line pair BL and /BL, a thick insulating membrane of a gate of a transistor forming the bit line precharge portion is required. This is because of the reliability of the gate insulating membrane, which makes a level of a threshold voltage Vt high, current conductivity decreased and precharging performance lowered. Furthermore, due to the level shifter  303 , an equalization bar signal BLEQb is also generated slowly, thereby delaying the generation of the equalization signal BLEQ.  
       SUMMARY OF THE INVENTION  
       [0018]     It is, therefore, an object of the present invention to provide a semiconductor memory device and its driving method which control a voltage level of an equalization signal to enhance a precharging performance for bit lines when the equalization signal is repeated to enable a bit line precharging portion.  
         [0019]     In accordance with an aspect of the present invention, there is provided a semiconductor memory device having a bit line sense amplifier shared by an upper cell block and a lower cell block including an equalization signal generator for generating an equalization signal in response to an upper cell block selection signal and a lower cell block selection signal; a repeater for repeating the equalization signal; and a pull-up controller for providing a first voltage as a pull-up voltage of the repeating means for a predetermined time period from a precharge time in response to the equalization signal and then providing a second voltage having a lower level than the first voltage as the pull-up voltage of the repeating means until a next activation time.  
         [0020]     In accordance with another aspect of the present invention, there is provided a method of driving a semiconductor memory device having a bit line sense amplifier shared by an upper cell block and a lower cell block, the method including generating an equalization signal in response to an upper cell block selection signal and a lower cell block selection signal; creating a driver control pulse being activated for a predetermined time period from a precharge time in response to the equalization signal; driving a pull-up voltage stage of a repeater that repeats the equalization signal using a first voltage for a predetermined time period from the precharge time in response to the driver control pulse; and driving the pull-up voltage stage of the repeater from an inactivation time of the driver control pulse to a next activation time with a second voltage having a lower level than the first voltage in response to the driver control pulse.  
         [0021]     More specifically, when the equalization signal is repeated by the repeater, the present invention controls a voltage level of the equalization signal to be a boost voltage VPP for a predetermined time period and then to be an external power supply voltage VDD. Namely, in order to improve the bit line precharging performance of the bit line precharge portion enabled by the equalization signal, a rising interval of the equalization signal is activated as the boost voltage. Precharging is then performed with the external supply voltage after a predetermined time period. Thus, a thin gate insulating membrane can be used in a transistor in the bit line precharge portion which receives the equalization signal.  
         [0022]     The other objectives and advantages of the invention will be understood by the following description and will also be appreciated by the embodiments of the invention more clearly. Further, the objectives and advantages of the invention will readily be seen that they can be realized by the means and its combination specified in the claims. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0023]     The above and other objects and features of the instant invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:  
         [0024]      FIG. 1  is a circuit diagram illustrating a cell core area of a conventional semiconductor memory device;  
         [0025]      FIG. 2  is a circuit diagram illustrating an equalization signal generating circuit and repeater according to the prior art;  
         [0026]      FIG. 3  is a circuit diagram illustrating an equalization signal generating circuit and repeater according to another prior art;  
         [0027]      FIG. 4  is a circuit diagram illustrating an equalization signal generating circuit and repeater in accordance with an embodiment of the present invention; and  
         [0028]      FIG. 5  is a timing diagram for describing the operation of the equalization signal generating and repeater shown in  FIG. 4 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0029]     Hereinafter, preferred embodiments of the present invention will be described in detail referring to the accompanying drawings so that the invention can be readily conceived by those in the art to which the invention pertains.  
         [0030]      FIG. 4  is a circuit diagram illustrating an equalization signal generating circuit and repeater in accordance with an embodiment of the present invention.  
         [0031]     Referring to  FIG. 4 , the invention equalization signal generating circuit and repeater comprise a signal generator  401  for receiving an upper block selection signal LAX9A and a lower block selection signal LAXBC that have a logic high level when an active command is inputted and a logic low level when a pre-charge command is inputted and generating an equalization signal BLEQ, a repeater pull-up voltage source  403  for controlling a voltage level of the equalization signal BLEQ to be at a boost voltage VPP at first and to be an external power supply voltage VDD after a predetermined time period, and a repeater  405  for taking the equalization signal BLEQ that is the output of the signal generator  401  and then repeating the equalization signal BLEQ corresponding to a voltage level of an output signal of the pull-up voltage source  403 .  
         [0032]     At this time, the signal generating portion  401  can be implemented with a NAND gate NAND 1  for receiving the upper block selection signal LAX9A and lower block selection signal LAXBC and outputting the equalization signal BLEQ, and a first inverter INV 1  for inverting an output signal of the NAND gate NAND1.  
         [0033]     The repeater pull-up voltage source  403  can be implemented with a pulse generator  407  for generating a driver control pulse A being activated for a predetermined time period from a precharge time in response to the output signal BLEQ of the signal generator  401 , an over-driver  409  for driving the pull-up voltage source  403  in the repeater with a boost voltage for the predetermined time period from the precharge time in response to the driver control pulse A, and a normal driver  411  for driving the pull-up voltage source  403  in the repeater with the supply voltage from an inactivation time of the driver control pulse A to a next activation time wherein the supply voltage is lower than the boost voltage.  
         [0034]     At this time, the pulse generator  407  can be implemented with a fifth inverter INV 5  for inverting the output signal of the signal generator  401 , a delay DELAY for delaying an output signal of the fifth inverter INV 5 , a fourth inverter INV 4  for inverting an output signal of the delay DELAY, and a second NAND gate NAND 2  for NAND-operating the output signal of the signal generator  401  and an output signal of the fourth inverter INV 4 .  
         [0035]     The over-driver  409  can be implemented with a first PMOS transistor P 1  connected to a boost voltage stage and having an output signal of the second NAND gate NAND 2  as its gate input.  
         [0036]     The normal driver  411  can be implemented with a PMOS transistor P 3  connected to a supply voltage stage and having the driver control pulse A inverted in a previous stage as its gate input.  
         [0037]     The repeater  405  can be implemented with a second inverter INV 2  and a third inverter INV 3  for buffering the output signal of the signal generator  401 , and a fourth PMOS transistor P 4  and a second NMOS transistor N 2  for receiving an equalization bar signal BLEQb that is an output signal of the third inverter INV 3  via its gate.  
         [0038]      FIG. 5  is a timing diagram for describing an operation of the equalization signal generating circuit and repeater of  FIG. 4 . The detailed description thereof that follows recites the reference characters of  FIG. 4 .  
         [0039]     Referring to  FIG. 5 , with the upper block selection signal LAX9A and lower block selection signal LAXBC, the equalization bar signal BLEQb that is the output signal of the signal generator  401  has the same logic level as the upper block selection signal LAX9A and lower block selection signal LAXBC.  
         [0040]     Thereafter, the driver control pulse A that is the output signal of the pulse generator  407  is generated by the equalization bar signal BLEQb delayed as much as delay information of the delay DELAY. The driver control pulse A is activated to a logic low level corresponding to a falling edge of the equalization bar signal BLEQb.  
         [0041]     In other words, the equalization signal BLEQ begins to rise, namely, to be repeated, by the equalization bar signal BLEQb that is the output signal of the signal generator  401 . The first PMOS transistor P 1  in the over-driver  409  is then turned on by the output signal A of the pulse generator  407 . Accordingly, the equalization signal BLEQ rises to the boost voltage VPP.  
         [0042]     Successively, the output signal A of the pulse generator  407  is inactivated as a logic high level and simultaneously a signal B input to the third PMOS transistor P 3  is activated as a logic low level. Correspondingly, a voltage level of the equalization signal BLEQ becomes the external supply voltage VDD.  
         [0043]     In other words, when enabling the bit line precharge portion by repeating the equalization signal BLEQ, an equalization signal input transistor in the bit line precharge portion is over-driven by the boost voltage VPP for a predetermined initial time period and then normally driven by the external supply voltage VDD. Here, the predetermined initial time period is determined by delay information of the delay DEALY in the pulse generator  407 .  
         [0044]     The above-described time period can be precisely known from the logic level of the equalization signal BLEQ. It can be also noted that a rising time of the equalization signal BLEQ to a logic high level differs deterministically from that of the conventional equalization signal BLEQ_OLD as shown in  FIG. 1 .  
         [0045]     As described above, there are two problems. One of them is that the turn-on time of the equalization signal input transistor in the bit line precharge portion becomes long due to a low voltage level of the equalization signal BLEQ, when the equalization signal BLEQ is repeated to drive the equalization signal input transistor by the conventional repeater. The other is the thick gate insulating membrane of the transistor due to a high voltage level of the equalization signal BLEQ. In order to overcome the two problems, the present invention comprises the equalization signal input transistor having a thin gate insulating membrane in the bit line pre-charge portion. In this arrangement, a voltage level of the equalization signal BLEQ repeated by the repeater of the present invention causes the transistor to over-drive, thereby improving the precharging speed. When the equalization signal BLEQ goes up to a logic high level, it has the level of the boost voltage VPP and thereafter the level of the external supply voltage VDD. Consequently, the rising time of the equalization signal BLEQ is decreased.  
         [0046]     The logic types and arrangements employed in the above-described embodiments are exemplified with respect to the input and output signals having only high activation signals. Therefore, when their activation polarities are changed, the logic implementation should be also changed accordingly. The present invention can be embodied in various ways and modifications of the embodiments can also be technically easily deduced by those skilled in the art. Thus, a detailed description of each case is omitted here.  
         [0047]     In addition, it is also only exemplified but not restrictive that the signal generator  401 , the repeater pull-up voltage source  403  and the repeater  405  are implemented with a plurality of logics.  
         [0048]     As mentioned above, the present invention allows the use of the thin gate insulating membrane in the equalization signal input transistor of the bit line precharge portion by controlling the voltage level of the equalization signal to be the boost voltage VPP for a predetermined time period and then to be the external supply voltage when the equalization signal is repeated by the repeater, and activates the rising interval of the equalization signal with the boost voltage. As a result, the present invention can improve precharging speed and accordingly precharge time tRP.  
         [0049]     The present application contains subject matter related to Korean patent application No. 2005-91675 and No. 2005-134012, filed with the Korean Intellectual Property Office on Sep. 29, 2005 and on Dec. 29, 2005, the entire contents of which are incorporated herein by reference.  
         [0050]     While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.