Abstract:
A selective low power clocking apparatus and method is used to reduce power consumption by an electronic system or integrated circuit that is coupled to an external system via a system bus which is configured to selectively transmit or receive signals from the electronic system or integrated circuit. The electronic system or integrated circuit includes a plurality of sub-circuits or functional blocks. Each sub-circuit or functional block is configured to operate under control of a clock signal and further includes an apparatus for holding or rejecting the clock signal. Once each sub-circuit within the electronic system or integrated circuit rejects the clock signal, the clock signal to that sub-circuit is disabled. The arbiter circuit continuously monitors the system bus. Upon detecting that the external system needs to transmit or receive signals from the electronic system or integrated circuit, the arbiter re-enables the clock signal to the sub-circuits which are required for the transmission or reception.

Description:
This is a Continuation of application Ser. No. 08/148,378 filed on Nov. 8, 1993 now abandoned. 
    
    
     FIELD OF THE INVENTION 
     This invention relates generally to electronic systems having selective application of a clock signal to multiple sub-circuits within that electronic system. More particularly, the invention preferably relates to an integrated circuit design which conserves power by gating the generation of the clock signal individually to its multiple sub-circuits when they do not require a clock signal. 
     BACKGROUND OF TEE INVENTION 
     Within each electronic system or integrated circuit are many sub-circuits or functional blocks which all work together to perform operations required by the CPU. Each synchronous sub-circuit within the electronic system or integrated circuit is supplied a clock signal from either the external system clock or a clock internal to the electronic system or integrated circuit. This clock signal is used to synchronize the operation of the integrated circuit and to toggle a response signal through the functional blocks, integrated circuit or electronic system. For all synchronous functional blocks the clock is used as the timing reference to ensure that each synchronous functional block will execute its operations in the sequence that they are to occur. 
     For certain types of circuits, including CMOS circuits, power consumption is increased as a result of the circuit being exercised, eg., by a clock signal. Typical digital systems employ multiple integrated circuit chips. As is well understood, each chip typically performs a limited number of functions for the system, for example, to control a semiconductor memory, to control a hard disk, to control a screen display and other related functions. Periodically, each of these circuits is not needed and is idle insofar as system functionality is concerned. Unfortunately, because these circuits continue to receive a clock signal, their respective internal circuits continue to be exercised and consume significant electric power, even while idle. 
     Lower power consumption is desirable for all electronic systems, but especially for portable computers which are supplied power from a battery with a finite lifetime. Conserving power in a portable computer will mean that the user can use their computer for a longer period of time before it is necessary to replace or recharge the battery, which supplies power to the portable computer. 
     One method used to reduce the time that the clock signal is supplied to an integrated circuit is used in PCMCIA Most Adapters, part Nos. C1-PD6710/PD672X, which are supplied by Cirrus Logic, Inc. This method teaches simultaneously dis-abling the clock signal to all of the functional blocks, after all of the functional blocks has signalled that they no longer require the clock signal. An arbiter circuit then monitors the system bus and will re-enable the clock signal to all of the functional blocks simultaneously, when an address within the range controlled by the arbiter and a corresponding command are present on the system bus. The disadvantage of this system is that the power savings can only be realized when the entire circuits of the C1-PD6710/PD672X become temporarily inactive. 
     What is needed is an apparatus and method which allows an electronic system or integrated circuit to selectively turn off the clock signal provided to its functional blocks during the time when the sub-circuits are not required for operation and allows the clock signal to be restored very rapidly when the functional blocks are necessary to the operation of the electronic system or integrated circuit. What is also needed is an apparatus and method which can turn off the clock signal to functional blocks within an electronic system or integrated circuit and keep the fact that the clock signal is turned off to those functional blocks transparent to both the system bus and the user. 
     SUMMARY OF THE INVENTION 
     A selective low power clocking apparatus and method is used to reduce power consumption by an electronic system or integrated circuit that is coupled to an external system via a system bus which is configured to selectively transmit or receive signals from the electronic system or integrated circuit. The electronic system or integrated circuit includes a plurality of sub-circuits or functional blocks. Each sub-circuit or functional block is configured to operate under control of a clock signal and further includes an apparatus for holding or rejecting the clock signal. Once each sub-circuit within the electronic system or integrated circuit rejects the clock signal, the clock signal to that sub-circuit is disabled. The arbiter circuit continuously monitors the system bus. Upon detecting that the external system needs to transmit or receive signals from the electronic system or integrated circuit, the arbiter re-enables the clock signal to the sub-circuits which are required for the transmission or reception. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a schematic diagram of the selective low power clocking apparatus of the present invention. 
     FIG. 2 illustrates a timing diagram of the outgoing clock signal in response to the incoming clock signal, the Kill --  Clock signal line and the Start --  Clock signal line for an individual functional block. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The selective low power clocking apparatus of the present invention is illustrated in FIG. 1. Each of the functional blocks 11-14 is provided a clock signal when the central arbiter 1 anticipates that the operation of the respective functional block will be necessary for completion of the operation. Once a functional block 11-14 is provided with a clock signal, the clock signal to that block will not be disabled until the functional block 11-14 has completed its required operations and no longer needs the clock signal. 
     Providing a clock signal to each of the functional blocks 11-14 is preferably accomplished in the same manner for all of the functional blocks 11-14. The central arbiter 1 and the comparison circuitry 2 monitorthe system bus 9 for addresses within the range controlled by the central arbiter 1 and for specific corresponding commands, whose completion will require the operation of this electronic system or integrated circuit. When an address within the controlled range and a specific corresponding command is detected, the central arbiter 1 then determines which functional blocks 11-14 will be necessary for completion of its task. Oncethe central arbiter 1 determines which functional blocks 11-14 will be required for operation, the central arbiter 1 pulls the respective Start --  Clock signal lines 15-18 to a logical low voltage level, causing the output of the respective NAND gates 44-47 to switch from a logical low voltage level to a logical high voltage level. The respective clock signals 40-43 are then provided to the functional blocks 11-14 whichare required for operation by the central arbiter 1 until they have completed their operations and no longer require a clock signal. 
     The clock signal to a particular functional block 11-14 is disabled when the particular functional block 11-14 raises its respective Kill --  Clock signal line output 19-22 to a logical high voltage level and the appropriate one of the Start --  Clock signal lines 15-18 for that functional block is also at a logical high voltage level, causing the output of the individual NAND gate 44-47 to switch from a logical high voltage level to a logical low voltage level. 
     The system bus 9 is coupled as an input to the central arbiter 1. The central arbiter 1 is coupled to the comparison circuitry 2 through the address lines 7 which provide the address from the system bus 9 to the comparison circuitry 2. The comparison circuitry 2 is also coupled to the central arbiter 1 through the control line 8 which informs the central arbiter 1 when the address on the address lines 7 is in the range of addresses controlled by the central arbiter 1. 
     The Start --  Clock signal line output 15 from the central arbiter 1 is coupled as an input to the NAND gate 44 for restoring the clock signal to the functional block 11. The Start --  Clock signal line output 16 fromthe central arbiter 1 is coupled as an input to the NAND gate 45 for restoring the clock signal to the functional block 12 when its operation is necessary. The Start --  Clock signal line output 17 from the central arbiter 1 is coupled as an input to the NAND gate 46 for restoringthe clock signal to the functional block 13 when its operation is necessary. The Start --  Clock signal line output 18 from the central arbiter 1 is coupled as an input to the NAND gate 47 for restoring the clock signal to the functional block 14 when its operation is necessary. 
     The Kill --  Clock signal line output 19 of the functional block 11 is coupled as the other input to the NAND gate 44 to signal when the functional block 11 no longer requires a clock signal. The Kill --  Clock signal line output 20 of the functional block 12 is coupled as the other input to the NAND gate 45 to signal when the functional block 12 no longer requires a clock signal. The Kill --  Clock signal line output 21 of the functional block 13 is coupled as the other input to the NAND gate 46 to signal when the functional block 13 no longer requires a clock signal. The Kill --  Clock signal line output 22 of the functional block 14 is coupled as the other input to the NAND gate 47 to signal when the functional block 14 no longer requires a clock signal. 
     The external clock signal 5 is provided as an input to the multiplexer 4 and to the frequency synthesizer 3. The output of the frequency synthesizer 3 is also provided as an input to the multiplexer 4. The clockselect signal line 6 is coupled as an input to the multiplexer 4 and can beused to select between the external clock signal 5 or the clock signal which is output from the frequency synthesizer 3. The frequency synthesizer 3 can be used to multiply or divide the external clock signal.In the preferred embodiment of the present invention, the frequency synthesizer 3 multiplies the external clock signal by the value of 7/4. The clock output signal 35 from the multiplexer 4 is coupled to the clock input of the central arbiter 1. 
     The output of the NAND gate 44 is coupled as the D input of the flip-flop 23. The Q output of the flip-flop 23 is coupled as an input to the NAND gate 27. The clock output signal 35 from the multiplexer 4 is provided as an input to the inverter 31 and as the other input of the NAND gate 27. The output signal from the inverter 31 is coupled to the clock input of the flip-flop 23. The output from the NAND gate 27 is coupled to the inputof the inverter 36 and the output signal 43 from the inverter 36 is coupledas the clock signal input to the functional block 11. 
     The output of the NAND gate 45 is coupled as the D input of the flip-flop 24. The Q output of the flip-flop 24 is coupled as an input to the NAND gate 28. The clock output signal 35 from the multiplexer 4 is provided as an input to the inverter 32 and as the other input of the NAND gate 28. The output signal from the inverter 32 is coupled to the clock input of the flip-flop 24. The output from the NAND gate 28 is coupled to the inputof the inverter 37 and the output signal 42 from the inverter 37 is coupledas the clock signal input to the functional block 12. 
     The output of the NAND gate 46 is coupled as the D input of the flip-flop 25. The Q output of the flip-flop 25 is coupled as an input to the NAND gate 29. The clock output signal 35 from the multiplexer 4 is provided as an input to the inverter 33 and as the other input of the NAND gate 29. The output signal from the inverter 33 is coupled to the clock input of the flip-flop 25. The output from the NAND gate 29 is coupled to the inputof the inverter 38 and the output signal 41 from the inverter 38 is coupledas the clock signal input to the functional block 13. 
     The output of the NAND gate 47 is coupled as the D input of the flip-flop 26. The Q output of the flip-flop 26 is coupled as an input to the NAND gate 30. The clock output signal 35 from the multiplexer 4 is provided as an input to the inverter 34 and as the other input of the NAND gate 30. The output signal from the inverter 34 is coupled to the clock input of the flip-flop 26. The output from the NAND gate 30 is coupled to the inputof the inverter 39 and the output signal 40 from the inverter 39 is coupledas the clock signal input to the functional block 14. 
     Only the operation of the functional block 11 and its accompanying circuitry will be described in detail because in the preferred embodiment each group of circuitry accompanying each functional block operates in thesame manner. The Kill --  Clock line 19 notifies the NAND gate 44 when the functional block 11 still requires the clock signal 43 for its operations. As long as any of the inputs to the NAND gate 44 are at a logical low voltage level then the output from the NAND gate 44 will be ata logical high voltage level and the clock signal 43 will be provided to the functional block 11. When the functional block 11 completes its operations and no longer requires the clock signal 43 it will raise its Kill --  Clock signal line 19 to a logical high voltage level. As soon as the Kill --  Clock signal line 19 and the Start --  Clock signal line 15 are at a logical high voltage level the output of the NAND gate 44switches from a logical high voltage level to a logical low voltage level and the clock signal 43 is then disabled or pulled to a constant logical low voltage level. 
     The clock signal 43 remains disabled until the central arbiter 1 and the comparison circuitry 2 determine that the functional block 11 will requirethe clock signal 43. The comparison circuitry 2 uses the address value on the system bus 9 and compares that address value to lookup tables or to hard-wired internal chip registers to determine if the address value on the system bus 9 is within the range of addresses controlled by the central arbiter 1. If the address value specified on the system bus 9 is within the range of addresses controlled by the central arbiter 1 then thecontrol line 8 is raised to a logical high voltage level and the central arbiter 1 is notified that an address is present on the system bus 9 whichis in its control. The central arbiter 1 then determines whether or not a corresponding command is also present on the system bus 9. If the central arbiter 1 determines that the functional block 11 will require a clock signal it will pull the Start --  Clock signal line 15 to a logical lowvoltage level causing the output of the NAND gate 44 to rise to a logical high voltage level. The clock signal 43 is then re-enabled, or coupled to match the output signal 35 from the multiplexer 4, and the functional block 11 is provided with the clock signal 43. In the preferred embodimentof the present invention, the central arbiter 1 specifically monitors the system bus 9 for commands involving any bus transactions to a register, including Input/Output Read or Write and Memory Read or Write commands, within the electronic system or integrated circuit or any transaction to circuitry controlled by the system. When an address within the range controlled by the central arbiter 1 and one of these specific commands is detected, then the central arbiter 1 determines which one or more of the functional blocks 11-14 should be provided with a clock signal. 
     Once the command on the system bus 9 is not one of the specific commands that the central arbiter 1 is configured to respond to and the address specified on the system bus 9 is no longer in the address range controlledby the central arbiter 1 or the operation of the functional block is no longer required, the central arbiter 1 will then raise the Start --  Clock signal line 15 to a logical high voltage level to signal that it no longer requires the clock signal for the functional block 11. The clock signal 43 will remain active however, until the functional block 11 has completed its tasks and has raised its Kill --  Clock signal line 19 toa logical high voltage level. The clock signal 43 is then disabled until the comparison circuitry 2 instructs the central arbiter 1 that the address specified on the system bus 9 is within the range of addresses which the central arbiter 1 is controlling and the central arbiter 1 detects one of the specific commands that it is configured to respond to and the operation of the functional block 11 is required for completion ofthe task. 
     The system bus used in the preferred embodiment of the present invention isan ISA bus which has a 16 bit wide data path and a 24 bit wide address bus.The ISA bus is asynchronous and operates with system clock rates of 6 MHz to 12 MHz. 
     FIG. 2 illustrates a timing diagram which shows the timing of the operationof a functional block of the selective low power clocking apparatus of the present invention. The output clock signal 35 from the multiplexer 4 is illustrated at the top of FIG. 2 by the Clk --  in waveform, the clock signal line 43 output from the inverter 36 is illustrated as the Clk --  out waveform, the D input to the flip-flop 23 is illustrated asthe D waveform, the Q output from the flip-flop 23 is illustrated as the Q waveform and the Start --  Clock signal line 15 from the central arbiter 1 is illustrated as the Start --  Clock waveform. While only the timing of the functional block 11 and its accompanying circuitry is illustrated and described in detail, it will be apparent to one of reasonable skill in the art that the timing and operation of the other functional blocks 12-14 and their accompanying circuitry is identical to the timing and operation of the functional block 11 and its accompanying circuitry. 
     Upon startup, the integrated circuit of the preferred embodiment is broughtup in its low power clock mode, with the clock signal 43 to the functional block 11 disabled. When operation of the functional block 11 is required for operation of the integrated circuit, the central arbiter 1 pulls the Start --  Clock signal line 15 to a logical low voltage level, causing the Clk --  out signal to be activated and the clock signal 43 to be provided to the functional block 11. The central arbiter 1 will then raisethe Start --  Clock signal line 15 to a logical high voltage level if the address specified on the system bus 9 is not within the range of addresses controlled by the central arbiter 1 and the command on the system bus 9 is not one of the specific commands that the central arbiter 1 is looking for, or if the central arbiter 1 determines that the functional block 11 is no longer needed to complete the required tasks. Then, once the functional block 11 has completed its required operations and no longer needs the clock signal 43, it will raise its Kill --  Clock signal line 19 to a logical high voltage level, causing the output of the NAND gate 44 and the D input of the flip-flop 23 to switch from a logical high voltage level to a logical low voltage level as is illustrated in FIG. 2 at the time 50. In response to the D input of the flip-flop 23 changing, the Q output of the flip-flop 23 then switches froma logical high voltage level to a logical low voltage level on the next negative clock edge of the Clk --  in signal, illustrated in FIG. 2 at the time 51. At this same clock edge, the Clk --  out signal is disabled so that the functional block 11 is not provided with a clock signal. Because the operation of the flip-flop 23 is controlled by the negative edge of the clock signal Clk --  in, the clock signal Clk --  out is disabled when it is already at a logical low voltage level, allowing disabling of the clock signal to occur without glitches, noise pulses or runt pulses. 
     When the Clk --  out signal is disabled, the central arbiter 1 and the comparison circuitry 2 monitor all of the addresses and commands on the system bus 9, until one of the addresses within the range controlled by the central arbiter 1 and one of the specific corresponding commands appears on the system bus 9. When one of the specific commands and addresses within the range of control appears on the system bus 9, the central arbiter 1 determines whether or not the functional block 11 is needed for completion of this operation. If the central arbiter 1 determines that the functional block 11 is needed for completion of this operation, then the central arbiter 1 pulls the Start --  Clock signal line 15 to a logical low voltage as illustrated at the time 52 and the Clk --  out signal is re-enabled. In response to the Start --  Clocksignal line 15 switching to a logical low voltage level, the output of the NAND gate 44 switches from a logical low voltage level to a logical high voltage level, causing the D input of the flip-flop 23 to do the same, as illustrated at the time 53 in FIG. 2. On the next negative clock edge of the Clk --  in signal, the Q output from the flip-flop 23 switches froma logical low voltage level to a logical high voltage level, as illustratedat the time 54 in FIG. 2. In response to the Q output of the flip-flop 23 changing, the Clk --  out signal will be re-enabled, beginning at the next positive clock edge as illustrated at the time 55. Because the clock signal Clk --  out is at a logical low voltage level when the clock signal is disabled, the present invention is designed so that the clock signal will always restart on the next positive edge of the clock signal Clk --  in. 
     The signal Clk --  out stays enabled until the central arbiter 1 raises the Start --  Clock signal line 15 to a logical high voltage level and the functional block 11 raises its Kill --  Clock signal line 19 to a logical high voltage level, signalling that it has completed its required operations and no longer requires the clock signal 43. When this happens, the output of the NAND gate 44 switches from a logical high voltage level to a logical low voltage level causing the D input of the flip-flop 23 to do the same. In response to the D input changing, on the next negative clock signal edge, the Q output is pulled to a logical low voltage level and the Clk --  out signal is disabled as illustrated in FIG. 2 at the time 56. The clock signal 43 then remains disabled until the central arbiter 1 pulls the Start --  Clock signal line 15 to a logical low voltage level. 
     After the clock signal 43 to the functional block 11 has been disabled, theclock signal 43 cannot be re-enabled and provided to those circuits until the central arbiter 1 pulls the Start --  Clock signal line 15 to a logical low voltage level. The functional blocks 11-14 can only signal that they no longer require a clock signal 40-43, but cannot signal that they need a clock signal 40-43, once it has been disabled. Once the clock signals 40-43 have been disabled, the central arbiter 1 must then continuously monitor the system bus 9 and the comparison circuitry 2 so that it knows when the functional blocks 11-14 are required for operation and will need their respective clock signals 40-43. 
     In order for the central arbiter 1 and the comparison circuitry to continuously monitor the system bus 9, they must either be provided a clock signal at all times or preferably be designed as an asynchronous circuit. In the preferred embodiment of the present invention, the output clock signal 35 from the multiplexer 4 is always provided to the inverters31-34, to the flip-flops 23-26 and to the NAND gates 27-30. The output clock signal 35 from the multiplexer 4 is also coupled to always be provided to the central arbiter 1 for the parts of the central arbiter 1 which are synchronous and require the clock signal in order to monitor thesystem bus and the comparison circuitry 2. The comparison circuitry 2 is designed to be asynchronous so that it does not require a clock signal to make its comparisons of the addresses on the system bus 9 and to notify the central arbiter 1 when the address on the system bus 9 is within the range of addresses controlled by the central arbiter 1. 
     The present invention has been described in terms of specific embodiments incorporating details to facilitate the understanding of the principles ofconstruction and operation of the invention. Such reference herein to specific embodiments and details thereof is not intended to limit the scope of the claims appended hereto. It will be apparent to those skilled in the art that modifications may be made in the embodiment chosen for illustration without departing from the spirit and scope of the invention.