Abstract:
A voltage comparator for use in a subranging A/D converter includes a coarse preceding comparison circuit 30, a fine preceding comparison circuit 31, and an amplification circuit 32 having an automatic zero compensation function. The coarse preceding comparison circuit 30 compares an analog input voltage Vin and a coarse reference voltage Vai. The fine preceding comparison circuit 31 compares the analog input voltage Vin and a fine reference voltage Vbi. The coarse and fine preceding comparison circuits 30, 31 sequentially outputs comparison results to the amplification circuits 32 so that the comparison results do not overlap each other. The amplification circuits 32 resets offset voltages before amplifying the comparison results applied. The number of elements necessary for a subranging A/D converter can be reduced, and a voltage comparator operating at a high speed and highly accurately can be provided.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a voltage comparator and a subranging A/D converter including such a voltage comparator. 
     2. Description of the Background Art 
     An A/D converter converts an analog signal to a digital signal. There are flash A/D converters, subranging A/D converters, etc. A subranging A/D converter A/D-converts an analog signal in two stages, i.e. stages of more significant bits and less significant bits. This subranging A/D converter has a smaller circuit scale and smaller power consumption as compared to a flash A/D converter. The subranging A/D converter is suited for installation in an LSI (Large Scale Integrated circuit) or a VLSI (Very Large Scale Integrated circuit) for this characteristic. This advantage of the series-parallel type has recently accelerated its development. An example of a subranging A/D converter as described above is presented in a document entitled &#34;A CMOS 40 MHz 86 105 mW Two-Step ADC&#34;, IEEE ISSCC Dig. of Teach. Papers. pp. 14-15, 1989. 
     FIG. 12 is a block diagram showing the conventional subranging A/D converter disclosed in the above-stated document. The subranging A/D converter shown in FIG. 12 conducts A/D conversion of a total of m+n bits formed of more significant m bits and less significant n bits. Referring to FIG. 12, the subranging A/D converter includes a reference voltage generation circuit 1, coarse voltage comparators A 0  -A k-1  (k=2 m  1), a coarse encoder 2 for encoding m bits, fine voltage comparators B 0  -B l-1  (l≧2 n  -1), a fine encoder 3 for encoding n bits, and an error correction circuit 4. The reference voltage generation circuit 1 has two input terminals 5 and 6 for applying reference voltages Vrt and Vrb, and an input terminal 7 for controlling a signal. The reference voltage generation circuit 1 has k coarse reference voltage output terminals a 0  -a k-1  and l fine reference voltage output terminals b 0  -b l-1  for outputting analog voltages based on these input voltages or input signals. The coarse voltage comparators A i   (i=0 to k-1) each has 2 input terminals, one of which is connected together to an analog voltage application terminal 8, the other is connected to the coarse reference voltage output terminal a i . The coarse encoder 2 has k input terminals connected to the outputs of k coarse voltage comparators a i , a 4 bit encoder result output terminal for outputting an encoder result, and an output terminal for control. The terminal to output an encoder result is connected to the input terminal of the error correction circuit 4, the output terminal for control signal is connected to the input terminal for control signal 7 of the reference voltage generation circuit 1. As is the case with the coarse voltage comparator A i , the fine comparators Bj (j=0 to l-1) each have 2 input terminals, one of which is connected together to the analog voltage application terminal 8, and the other is connected to the fine reference voltage output terminal b j . The fine encoder 3 has l input terminals connected to the outputs of the fine voltage comparators B j , an output terminal 9 for outputting an encode result of n bits, and an error detection signal output terminal 10 for outputting an error detection signal to the error correction circuit 4. The error correction circuit 4 has m input terminals connected to the output of coarse encoder 2, an input terminal connected to the error detection signal output terminal 10, and an output terminal 11 for outputting a final coarse encoder result of m bits which has been subjected to error correction. 
     An operation of the subranging A/D converter shown in FIG. 12 will be described. The subranging A/D converter operates in two stages, in other words in stages of coarse A/D conversion and fine A/D conversion. In the first stage, in other words in the coarse A/D conversion stage, each of the coarse voltage comparators A i  compares an analog signal voltage Vin and a coarse reference voltage Va i  output from the coarse reference voltage input terminal a i . The coarse reference voltage Va i  is usually obtained by dividing the two voltages Vrt and Vrb applied to the reference voltage application terminals 5 and 6 of the reference voltage generation circuit 1. Such reference voltage Va i  and the analog signal voltage Vin are compared at the voltage comparator, and a range of voltage in which the analog voltage Vin exists is detected, and then a conversion into a desired code is conducted at the encoder 2. At the same time, a detection signal of the above-stated voltage range is applied to the control signal input terminal 7 of the reference voltage generation circuit 1. 
     In the second stage, in other words in the fine A/D conversion stage, a fine reference voltage Vb j  to be output to the fine reference voltage application terminal B j  is generated by the reference voltage generation circuit 1 based on a control signal. For example, if the presence of the analog signal voltage Vin between the coarse reference voltages Va i  and Va i+1  in the course of a coarse A/D conversion, a voltage further divided including both voltages is generated. Thus generated fine reference voltages V bj  are each input into one input end of a corresponding voltage comparator B j . The analog signal voltage Vin is applied in common to the other input end of each of the voltage comparators B j , comparison and encoding are conducted as is the case with the coarse A/D conversion operation, and finally a fine A/D conversion result in a desired code is output from the terminal 9. At the same time, a determination is made whether or not the range in which the analog signal voltage Vin detected in the fine A/D conversion exists coincide with that of the coarse A/D conversion result, and if no coincidence is found, a control signal is transferred to the error correction circuit 4 through the error detection signal output terminal 10. The error correction circuit 4, based on the control signal, corrects the coarse encoder result, and finally outputs a coarse A/D conversion result to the terminal 11. 
     FIG. 13 is a circuit diagram showing an example of a conventional 2-input voltage comparator. Referring to FIG. 13, in the voltage comparator, a coarse voltage comparator A i  and a fine voltage comparator Bj are independently provided. The voltage comparator is controlled by clock signals φ 1  -φ 31  generated by a clock signal generation circuit 50 externally provided. 
     The coarse voltage comparator A i  is formed of a series-connection of an input circuit 12, amplification circuits 13a and 14a of first and second stages having an automatic zero compensation function, and an inversion amplifier 15a. The input circuit 12 includes a switch S1 connected to an analog signal application terminal 8, and a switch S2 connected to a coarse reference voltage application terminal a i . The switch S1 is turned on/off in response to the clock signal φ1. The switch S2 is turned on/off in response to the clock signal φ2. The output terminals of the switches S1 and S2 are connected together to the input end of the first stage amplification circuit 13. The first stage amplification circuit 13 includes a coupling capacitor Cc, an inversion amplifier 16, and a switch S3 connected between the input and output of the inversion amplifier 16. The coupling capacitor Cc has one end connected to the output of the input circuit 12 and the other end connected to the input of the inversion amplifier 16. The switch S3 is turned on/off in response to the clock signal φ1. When the switch S3 conducts, the output of the inversion amplifier 16 is fed back to the input of the amplifier 16. The second stage amplification circuit 14a has the same construction as that of the first amplification circuit 13. 
     As is the case with the coarse voltage comparator A i , a fine voltage comparator B j  is formed of a series-connection of an input circuit 17, first stage and second stage amplification circuits 13b and 14b, and an inversion amplifier 15b. An essential difference from the coarse voltage comparator A i  is that the input circuit 17 is connected to the fine reference voltage output terminal b j  (see FIG. 12), and the fine reference voltage output terminal b j  is connected to the input end of the first stage amplification circuit 13b through a switch S4. The switch S4 is turned on/off in response to the clock signal φ3. 
     FIG. 14 is a representation showing the signal waveforms of the circuits shown in FIG. 13. The waveforms of V 3 , V 4 , V 5  indicated by the solid lines in FIG. 14 are voltage waveforms in the coarse comparison, while the waveforms of V 3 , V 4 , V 5  depicted by the chain dotted lines are voltage waveforms in the fine comparison. Referring to FIG. 14, a description of an operation of the coarse voltage comparator A i  shown in FIG. 13 follows. In a period when the clock signal φ1 is in an &#34;H&#34; level (this period is referred to as an auto zero period), the switches S1 and S3 are turned on, while the switch S2 is turned off. With the switch S1 made conductive, the analog signal voltage Vin is applied to the first stage amplification circuit 13a. With the switch S3 made conductive, the outputs of the internal nodes N1 and N2 of first stage and second stage amplification circuits 13a and 14a are biased to the logic threshold voltage Vb of the inversion amplifier 16. Thus, charges are accumulated on the internal nodes N1 and N2 of the first stage and second stage amplification circuits 13a and 14a. Assuming that the accumulated charges are Q and Q 2 , respectively, and the parasitic capacitance of nodes N1 and N2 are Cs and Cs 2 , respectively, the following equations hold. 
     
         Q.sub.1 =PCc (Vb-V.sub.in)+C.sub.s1 Vb                     (1) 
    
     
         Q.sub.2 =PCc (Vv-V.sub.b)+C.sub.S2 Vb                      (2) 
    
     At the same time, the output of the inversion amplifier 15a is also biased to the threshold Vb. 
     In a period when the clock signal φ2 is in an &#34;H&#34; level (this period is referred to as coarse comparison period), the switch S2 is turned on, while the switches S1 and S3 are turned off. With the switch S3 conducting, the first stage and second stage amplification circuits 13a and 14a lose an inlet and outlet path for charges to and from the internal nodes N1 and N2, and the charges Q 1  and Q 2  accumulated in the auto zero period are held therein. Meanwhile, the coarse reference voltage Va i  rather than the analog signal voltage Vin is applied to the input terminal of the first stage amplification circuit 13a of the coarse voltage comparator A i  in this period. Thus, the voltages of the internal nodes N1 and N2 of the first stage and second stage amplification circuits 13a and 14a change its level from the threshold voltage Vb to certain voltages V 1  and V 2 . Accordingly, the amount of charge Q at the internal node N1 of the first stage amplification circuit 13 is given by the following equation using the voltage V 1 . 
     
         Q.sub.1 =Cc (V.sub.1 -Va.sub.i)+Cs.sub.1 V.sub.1           ( 3) 
    
     Therefore, from equations (1) and (3), the voltage V 1  is finally given by the following equation. 
     
         V.sub.1 =Vb+λ(Va.sub.i -V.sub.in)                   (4) 
    
     where, 
     
         λ=Cc/(Cc+Cs)                                        (5) 
    
     Equation (4) means that the voltage of the internal node N1 of the first stage amplification circuit 13a shifts from the threshold voltage Vb in response to a voltage change (this proportion amount is referred to as a voltage transmission rate) generated at the input. More specifically, the amount of voltage change created on the input side by the coupling capacitor Cc and the parasitic capacitor Cs is multiplied by λ, and the λ-multiplied voltage change is superimposed to the threshold voltage Vb. Now, assuming that the voltage change on the input side is ΔVin, the voltage on the output side before this voltage change is transferred is Vout 0 , the voltage on the output side after the transfer is Vout, Vout is generally given by the following equation 
     
         Vout=Vout.sub.0 +λΔVin                        (6) 
    
     Accordingly, the input of the first stage amplification circuit 13a is shifted from the threshold voltage Vb by λΔVic (where ΔVic=Va i  -Vin; coarse input differential voltage). Such shift amount is amplified by the inversion amplifier 16 of the first stage amplification circuit 13a. When the voltage amplification factor of the inversion amplifier 16 is -G and the output voltage is V 3 , the output voltage V 3  is given by the following equation: 
     
         V.sub.3 =Vb-λGΔVic                            (7) 
    
     In the second stage amplification circuit 14, the above-stated voltage V 3  is applied rather than the threshold voltage Vb in the auto zero period. The application of the output voltage V 3  changes the voltage of the internal node N2 from Vb. The amount of this voltage change can be produced based on the principle of conservation of charge in the input node N2, but herein, only the result is given based on equation (6). More specifically, the voltage change ΔV 3  on the input side of the second stage amplification circuit 14 is -λGΔVic from equation (7), and therefore the voltage change ΔV 2  generated at the node N2 is given by the following equation: 
     
         ΔV.sub.2 =λΔV.sub.3 =-λ.sup.2 GΔVic (8) 
    
     This voltage change ΔV 2  is further amplified by the inversion amplifier 16 of the second stage amplification circuit 14a. The voltage change Δ V4  in the output end of the inversion amplifier 16 is given by the following equation: 
     
         Δ.sub.V.sub.4 =-GΔV.sub.2 =λ.sup.2 G.sup.2 ΔVic (9) 
    
     This is further amplified by the inversion amplifier 15a, and, therefore, the output voltage V 5  of the amplifier 15a is given by the following equation: 
     
         V.sub.5 =Vb-GΔV.sub.4 =Vb-λ.sup.2 G.sup.3 ΔVic (10) 
    
     Equation (10) indicates that the coarse input differential voltage ΔVic is multiplied by λ 2  G 3  for output in the coarse voltage comparator A i . Accordingly, if, for example, λ=1, G=10, Vb=2.5 V, and an input differential voltage is equal to or larger than 1.7 mV, amplification can be made up to a logic level (&#34;H&#34; is more than 4.2 V, while &#34;L&#34; is less than 0.8 V with a power supply voltage of 5 V). At that time, the voltage comparator outputs an &#34;H&#34; level when Vin&gt;Va i , and an &#34;L&#34; level when Vin&lt;Va i . Based on this output result (comparison result) the reference voltage generation circuit 1 generates the fine reference voltage Vb j , and applies the generated voltage to the fine reference voltage application terminal b j . 
     The fine voltage comparator B j  operates based on the same principle as the coarse voltage comparator A i  with only the difference being that comparison is conducted when the clock signal φ3 is in an &#34;H&#34; level (this is called fine comparison period). Therefore, description will not be repeated here. 
     As described above, when the conventional 2-input voltage comparator is used in a subranging A/D converter, it is necessary to separately provide a voltage comparator for coarse A/D conversion and a voltage comparator for fine A/D conversion. As described above, the subranging A/D converter conducts series-parallel A/D conversion in two stages, and as is well known the converter needs at least 2 m  -1 voltage comparators for a parallel A/D conversion of, for example, m bits. Accordingly, with increase of resolution, the number of voltage comparators necessary increases as an exponential rate. In order to alleviate such disadvantage of the subranging A/D converter, use of a 3-input voltage comparator is proposed in an article entitled &#34;An 8-bit 20 MS/s CMOS A/D Converter with 50-mW Power Consumption&#34; IEEE Journal of Solid State Circuit 1990 Vol. 25, No. 1 pp. 167-172. 
     FIG. 15 is a circuit diagram showing the 3-input voltage comparator disclosed in the above-stated article, and FIG. 16 is a representation showing the signal waveforms of the circuits in FIG. 15. The voltage comparator shown in FIG. 15 is different from the voltage comparator shown in FIG. 13 in that a three-input input circuit 19 is used instead of two 2-input input circuits 12 and 17, and first stage and second stage amplification circuits 13 and 14, and the inversion amplifier 15 are provided one for each. The input circuit 19 includes three input terminals, an analog signal application terminal 8, a coarse reference voltage application terminal a i  and a fine reference voltage application terminal b j . The input terminals 8, a i  and b j  are connected together to the input end of the first stage amplification circuit 13 respectively through switches S1, S2 and S4. The switch S1 is turned on/off in response to the clock signal φ1. The switch S2 is turned on/off in response to the clock signal φ2. The switch S4 is turned on/off in response to the clock signal φ3. 
     A description of an operation follows. The voltage comparator is controlled by the clock signals shown in FIG. 16 (the same as those shown in FIG. 14), and operates in three stages. When the clock signal φ1 is in an &#34;H&#34; level (auto zero period), the switches S1 and S3 are turned on, while the switches S2 and S4 are turned off. With the switch S1 being turned on, the analog signal voltage Vin is applied to the input of the first stage amplification circuit 13. With the switch S3 being turned on, the internal nodes N1, N2 and outputs of the first stage and second stage amplification circuits 13 and 14 are biased to the logic threshold voltage Vb of the inversion amplifier 16. The output of the inversion amplifier 15 is biased to the voltage Bb accordingly. 
     In a period when the clock signal φ2 is of &#34;H&#34; level (coarse comparison period), only the switch S2 is turned on, and the other switches S1, S3, and S4 are turned off. The operation in this case is the same as the above-stated voltage comparator (FIG. 13), a description will not be repeated here. 
     In a period when the clock signal φ3 is of &#34;H&#34; level (fine comparison period), the switch S4 is turned on, and the other switches S1-S3 are turned off. Also in this period, with the switch S3 still being turned off, the internal nodes N1 and N2 of the first stage and second stage amplification circuits 13 and 14 attain a high impedance state. Therefore, in the auto zero period, charges accumulated at the internal nodes N1 and N2 are still conserved in this period, and equation (6) given above holds in this period. Meanwhile, with the switch S4 being turned on, the fine reference voltage Vbj instead of the coarse reference voltage Va i  is applied to the input of the first stage amplification circuit 13. The voltage obtained by multiplying this voltage change (Vb j  -Va i ) by λ is superimposed to the voltage V 1  produced by equation (4). Accordingly, the voltage V 11  of the node N3 of the amplification circuit 13 in the fine comparison period is given by the following equation: ##EQU1## 
     Equation (11) indicates that voltage change from Vin to the fine reference voltage Vb j  takes place at the input end of the first stage amplification circuit 13. The voltage shift from the logic threshold voltage Vb is transferred to succeeding stages as is the case with the voltage comparator shown in FIG. 13, and a fine comparison is conducted. When the voltage comparator is constructed as shown in FIG. 15, the coarse and fine voltage comparisons can be conducted in a single voltage comparator. Therefore, A/D conversion of a total of 2m bits formed of more significant m bits and less significant m bits is conducted, (2 m  -1) voltage comparators may be provided. This means that the number of voltage comparators necessary is reduced by half as compared to the 2-input voltage comparator (FIG. 13) which requires 2·(2 m  -1) voltage comparators. The voltage comparator of this construction however still suffers from the following disadvantage. 
     This disadvantage will be described in conjunction with the output transient responsive waveforms of the amplification stages of fine voltage comparator Bj and the transient responsive waveforms of the amplification stages of the 3-input voltage comparator shown in FIG. 16. In FIGS. 14 and 16, V3 represents the output voltage of the first stage amplification circuit 13, V4 the output voltage of the second stage amplification circuit 14, and V5 the output voltage of the inversion amplifier 15. As can be seen from FIG. 14, all the internal nodes N1-N4 are biased to the threshold voltage Vb immediately before fine comparison in the 2-input voltage comparator (this state is referred to as initial state), the internal nodes N1-N4 start responding for outputting a correct comparison result the moment the fine reference voltage Vb j  is supplied. In contrast, in the 3-input voltage comparator, the internal nodes have shifted from the logic threshold voltage Vb immediately before execution of the fine comparison depending upon the coarse comparison result. Accordingly, the 3-input voltage comparator requires an extra time period (this is referred to as recovery time) until the voltage at the end of the coarse comparison returns to the initial state. For example, in the first stage amplification circuit 13, time until the output voltage V3 crosses the logic threshold voltage Vb is the recovery time of the amplification circuit 13. The output voltage V4 of the second stage amplification circuit 14 begins to be inverted at the moment the output voltage of the first stage amplification circuit 13 crosses Vb. Therefore, the recovery time of the amplification circuit 14 is produced as the sum of the recovery time of the first stage amplification circuit 13 and its recovery time. Recovery time increases in succeeding stages, which results in degradation in the comparison speed for the entire voltage comparator. 
     Additionally, in the conventional 2-input and 3-input voltage comparators, comparison accuracy sometimes degrades due to a clock noise. A transmission gate as shown in FIG. 17 is generally used for the switches S1-S4 in the voltage comparators shown in FIGS. 13 and 15. The transmission gate includes a PMOS transistor 20, and an NMOS transistor 21 connected in parallel thereto. The PMOS and NMOS transistors 20 and 21 have their gate terminals 22 and 23 supplied with clock signals which are complementary to each other. The drain electrodes and source electrodes of the transistors 20 and 21 are connected together to terminals 24 and 25, respectively. Gate-drain capacitors 26 and 27 of capacitance values C 1  and C 2  exist in a parasitic manner between the gate electrodes 22, 23 and drain electrodes 24 of the transistors 20, 21. Similarly, gate-source capacitors 28 and 29 of capacitance values C 3  and C 4  exist in a parasitic manner between the gate electrodes and source electrodes of transistors 20 and 21. 
     Now, an operation of the transmission gate taking into account the parasitic capacitance will be described. When a signal applied to the gate electrode 22 changes its level from &#34;L&#34; to &#34;H&#34;, and a signal applied to the gate electrode 23 changes its level from &#34;H&#34; to &#34;L&#34;, the transmission gate is turned off. This gate voltage change is transferred to the terminals 24 and 25 through the parasitic capacitor. More specifically, charge is implanted into terminals 24 and 25 by the change of the gate voltage. When the terminals 24 and 25 are in the state of high impedance, a minor voltage change takes place by the implanted charge. When a signal of a large amplitude is dealt with as in the case of a digital circuit, such minor voltage change does not cause any problem, but results in a significant problem in an analog circuit. 
     Now, an operation of the 2-input coarse voltage comparator A i  taking into such implanted charge will be described. Consider, for example, the switch S3 of the first stage amplification circuit 13a shown in FIG. 13. When the switch S3 is formed of a transmission gate, it generates a voltage change caused by the change of the clock signal at the internal node N2 at the moment it is turned off. The voltage change ΔV 21  of the internal node N2 caused exclusively by this clock change is given by the following equation, wherein the gate terminal voltage of a P type transistor is ΔVclk, and the gate terminal voltage of an N type transistor is -ΔVclk: ##EQU2## 
     Therefore, the voltage V 1  of the internal node N1 in the first stage amplification circuit 13 in the coarse comparison period when such clock noise is taken into account is given by the following equations: 
     
         V.sub.1 =Vb+λΔVic+λCΔVclk        (13) 
    
     , where 
     
         λC→(C.sub.1 -C.sub.2)/(Cc+Cs.sub.1)          (14 
    
     From the above equations, when, for example, ΔVic=-1 mV, and ΔVclk=5 V, and the following expression holds: 
     
         C.sub.1 -C.sub.2 &gt;Cc/5000                                  (15) 
    
     This indicates that an erroneous operation is caused by the clock noise. When expression (15) is satisfied, V 1  -Vb&gt;0 is true despite that ΔVic&lt;0. In order to prevent such erroneous operation, if Cc=0.1 fF, the expression C 1  -C 2  &lt;0.02 fF or smaller must be satisfied. C 1  and C 2  are parasitic capacitors, and, therefore, it is difficult to control the capacitance values in the above-stated order. Upon occurrence of an erroneous operation in the first stage amplification circuit 13, this error is amplified and output as a comparison result. Such clock noise is also generated in the second stage amplification circuit 14, but the signal has already been amplified at the first stage amplification circuit 13, and therefore does not cause such a significant problem as compared to the first stage. 
     With the conventional 2-input voltage comparator constructed as in the above-described manner, the number of voltage comparators necessary when an A/D converter is formed using such voltage comparators increases as an exponential function with increase of the resolution of A/D converter. Also, the conventional 3-input voltage comparator alleviates the above-stated problem, but its comparison speed decreases. Furthermore, both 2-input and 3-input voltage comparators are prone to erroneous operations caused by clock noises, and both have problems in the comparison accuracies. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to simplify a construction of a subranging A/D converter. 
     Another object of the invention is to provide a high speed and highly accurate voltage comparator. 
     Simply stated, a voltage comparator in accordance with the invention is a voltage comparator to compare an analog input signal and at least 2 reference voltages, and includes at least two voltage signal generators, an amplifier, and a resetting device. 
     The at least two voltage signal generators are provided correspondingly to at least two reference voltages, each of which generates in a time-dividing manner a voltage signal corresponding to the difference between the analog input signal and a corresponding reference voltage. 
     The amplifier sequentially amplifies the reference voltage generated in a time dividing manner by the at least two voltage signal generators after a prescribed resetting period. 
     The resetting device resets the offset voltage of the amplifier in the prescribed resetting period. 
     In operation, the at least two voltage signal generators generate in a time dividing manner voltage signals corresponding to the difference between the analog input signal and a corresponding reference voltage. The generated respective voltage signals are sequentially applied to the amplifier. The amplifier is reset by the resetting device before amplifying the voltage signals. Thus, the offset voltage accumulated in amplifying the voltage signal is canceled, and the voltage signal applied thereafter is amplified. It is therefore not necessary to set recovery time for the amplifier, which reduces time required for the comparison. A clock noise from the resetting period to the next comparison period is canceled between the outputs of at least two voltage signal generators, thus suppressing erroneous operations caused by the clock noise. 
     According to the invention, since comparison between an analog input signal and at least two reference voltages is conducted in a single voltage comparator, the number of voltage comparators necessary can be reduced as compared to a conventional 2-input voltage comparator. Thus, the construction of a subranging A/D converter can be simplified. The amplifier is reset before amplifying each of the voltage signals output from at least two voltage signal generators, recovery time will not be necessary, and the clock noise can be canceled. As a result, a high speed and highly accurate voltage comparator can be provided. 
    
    
     The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing a voltage comparator in accordance with one embodiment of the present invention; 
     FIG. 2 is a representation showing the output signal waveforms of the circuits shown in FIG. 1; 
     FIG. 3 is a circuit diagram showing a second embodiment of the invention; 
     FIG. 4 is a circuit diagram showing a third embodiment of the invention; 
     FIG. 5 is a circuit diagram showing a fourth embodiment of the invention; 
     FIG. 6 is a circuit diagram showing a preceding comparison circuit 40 shown in FIG. 5; 
     FIG. 7 is a circuit diagram showing in detail an amplifier having a plural-input automatic zero compensation function shown in FIG. 5; 
     FIG. 8 is a timing chart for use in illustration of an operation of the voltage comparator shown in FIG. 5; 
     FIG. 9 is a circuit diagram showing a fifth embodiment of the invention; 
     FIG. 10 is a circuit diagram showing a variation of an amplification circuit having an automatic zero compensation function; 
     FIG. 11 is a block diagram showing an A/D converter in accordance with a sixth embodiment of the invention; 
     FIG. 12 is a block diagram showing a conventional subranging A/D converter; 
     FIG. 13 is a circuit diagram showing a conventional 2-input voltage comparator; 
     FIG. 14 is a representation showing the output waveforms of the circuits of the 2-input voltage comparator shown in FIG. 13; 
     FIG. 15 is a circuit diagram showing a conventional 3-input voltage comparator; 
     FIG. 16 is a representation showing the output waveforms of the circuits of the voltage comparator shown in FIG. 14; and 
     FIG. 17 is a circuit diagram showing examples of the switches S1-S4 shown in FIGS. 13 and 15. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is a circuit diagram showing an embodiment of a voltage comparator according to the invention. Referring to FIG. 1, the voltage comparator includes a coarse preceding comparison circuit 30, a fine preceding comparison circuit 31, a 2-input amplification circuit having an automatic zero compensation function 32, and an inversion amplifier 15. The voltage comparator is controlled by clock signals φ1, φ2, φ4 and φ5 generated by an externally provided clock signal generation circuit 100. 
     The 2-input amplification circuit 32 has 2 input ends, one of which is connected to the output of the coarse preceding comparison circuit 30, and the other input end is connected to the output of the fine preceding comparison circuit 31. The inversion amplifier 15 is connected to the output of the 2-input amplification circuit 32. The coarse preceding comparison circuit 30 is formed of a series connection of an input circuit 12 and an amplification circuit having an automatic zero compensation function 13. The fine preceding comparison circuit 31 is formed of a series connection of an input circuit 33 and an amplification circuit having an automatic zero compensation function 13b. The constructions of the input circuit 12 and amplification circuit 13 are identical to those in FIG. 13, and a description will not be repeated here. In the input circuit 33, the switch S4 of the input circuit 17 shown in FIG. 13 is replaced with a switch S5 controlled by the clock signal φ4. The 2-input amplification circuit 32 includes capacitors 34 and 35, a switch S6, and an inversion amplifier 37. The capacitor 34 has a capacitance value C 34  and one end connected to the output of the coarse comparator 30, while the capacitor 35 has a capacitance value C 35  and one end connected to the output of the fine preceding comparison circuit 41, with the other ends of the capacitors 34 and 35 being connected together to an internal node 34. The internal node 36 is connected to the input of an inversion amplifier 37. The output of the inversion amplifier 37 is connected to the input of the inversion amplifier 15 and fed back to the input through the switch S6. The switch S6 is turned on/off in response to the clock signal φ5. 
     FIG. 2 is a representation showing the output waveforms of the circuits shown in FIG. 1. Referring to the output waveforms shown in FIG. 2, a description of an operation of this embodiment follows. This voltage comparator operates in four stages altogether, i.e. auto zero period (1), coarse comparison period (2), reset (3), and fine comparison period (4). In the auto zero period (1), the clock signals φ1 and φ5 attain an H level, and the clock signals φ2 and φ4 attain an L level, which turns on the switches S1, S3, and S6, and turns off the switches S2 and S5. With the switch S1 being turned on, an analog signal voltage Vin is applied to the inputs of the preceding comparison circuits 30 and 31 and the amplification circuits 13a and 13b. Further, with the switches S3 and S6 being turned on, the input/output ends of the inversion amplifiers 15, 16, and 37 are biased to the threshold voltage Vb. 
     In the coarse comparison period (2), only the clock signal φ2 attains an &#34;H&#34; level, only the switch S2 is turned on, and all the other switches S1, S3, S5, and S6 are turned off. With the switches S3 and S6 being turned off, the internal nodes N1 and N3 of the amplification circuits 13a and 13b, and the internal node 36 of the amplification circuit 32 attain a high impedance state, and the charge stored in the auto zero period is conserved. Meanwhile, a coarse reference voltage Va i  is applied to the input end of the amplification circuit 13a instead of the analog input voltage Vin. On the other hand, no voltage is applied to the amplification circuit 13b of the fine preceding comparison circuit 31. Therefore, the output of the fine preceding comparison circuit 31 does not undergo any voltage change except for those caused by clock noises, and the coarse comparison is conducted based on the same principle as the conventional one by series-connected amplification circuit 13 and 32, and inversion amplifier 15. 
     In the reset period (3), since only the clock signal φ5 attains an H level, only the switch S6 is turned on, and all the other switches S1, S2, S3, and S5 are turned off. With the switch S6 being turned on, the input of the inversion amplifier 15, and the input end of the inversion amplifier 37 are once again biased to the threshold voltage Vb. On the other hand, in this period and the fine comparison period following this period, the output voltage of the coarse preceding comparison circuit 30 does not change. Therefore, in the period until the fine comparison is completed, only a flow of a signal in a circuit formed of the fine preceding comparison circuit 31, the 2-input amplification circuit 32, and the inversion amplifier 15 is considered. Now, the voltage of the internal node N3 of the fine preceding comparison circuit 31 in the reset period (3) is considered. Voltage at the input/output end of the inversion amplifier 16 should usually be the threshold voltage Vb in this period (3), but the voltage change ΔVclk caused by the clock noise exists as described in conjunction with the conventional example, an input voltage V 1  and an output voltage V 3  are given by the following equations, wherein the amplification factor of the inversion amplifier 16 is -G: 
     
         V.sub.1 =Vb+λcΔVclk                           (16) 
    
     
         V.sub.3 =Vb-λcGΔVclk                          (17) 
    
     In the fine comparison period (4), since only the clock signal φ4 attains an &#34;H&#34; level, only the switch S5 is turned on, while all the other switches S1, S2, S3, and S6 are turned off. With the switch S6 being turned off, the input/output end of the inversion amplifier 37 attains a high impedance state, and the charge stored at the internal node 36 in the reset period is conserved. Meanwhile, with the switch S5 being turned on, the fine reference voltage Vb j  rather than the analog signal voltage Vin is applied to the amplification circuit 13b of the fine preceding comparison circuit 31. This voltage change ΔVif=Vb j  -Vin is transferred to the node N3 of the fine preceding comparison circuit 31, and amplified by the inversion amplifier 16. The input voltage V 11  and output voltage V 13  of the inversion amplifier 16 at the time are given by the following equations: 
     
         V.sub.11 =Vb+λcΔVclk+λΔVif       (18) 
    
     
         V.sub.13 =Vb-λcGΔVclk-λGΔVif     (19) 
    
     Meanwhile the 2-input, amplification circuit 32 is reset in the reset period, and, therefore, only the voltage change since the reset period (3) to the fine comparison period (4) is transferred to the node 36 through the capacitors 34 and 35. Since there is not any voltage change at the input end of the capacitor 34, only the voltage change transferred through the capacitor 35 is superimposed to the threshold voltage Vb at the internal node 36. The voltage change ΔV from the reset period (3) to the fine comparison period (4) is given by the following equations (17) and (19): 
     
         ΔV=V.sub.13 -V.sub.3 =-λGΔVif           (20) 
    
     Therefore, the voltage V 36  of the node 36 is given as: 
     
         V.sub.36 =Vb-λGΔVif                           (21) 
    
     As can be clearly seen from equation (21), the voltage of the internal node 36 is shifted from Vb by the amount of the voltage in proportion to the fine input differential voltage Vif, and free of any effect by a clock noise. This amount of shift from the threshold voltage Vb is amplified by the inversion amplifiers 37 and 15, and a comparison result in size between Vif and Vb j  is output without an erroneous operation caused by the noise. 
     A voltage comparator constructed in the above-described manner reduces the number of voltage comparators required for forming an A/D converter by about 1/2 as compared to a conventional 2-input voltage comparator. Also, since coarse and fine comparisons are initiated from their initial states, recovery time is not necessary unlike a conventional 3-input voltage comparator. Comparison accuracy can also be improved with a clock noise canceling function. Although the above-stated noise canceling function is not effective in the coarse comparison, there will be no problem as far as the fine comparison is accurately conducted, because a coarse A/D conversion result is usually corrected based on a fine A/D conversion result in an A/D converter. 
     FIG. 3 is a circuit diagram showing a second embodiment of the invention. The voltage comparator shown in FIG. 3 is different from the voltage comparator shown in FIG. 1 in that a switch S7 controlled by a clock signal /φ2 is provided instead of the switch S3 of the coarse preceding comparison circuit 30, and a switch S8 controlled by a clock signal /φ4 is provided instead of the switch S3 of the fine preceding comparison circuit 31. 
     In operation, the switch S7 is turned off only in a coarse comparison period (2), while the switch S8 is turned off only in a fine comparison period. Thus, coarse comparison and fine comparison can be conducted in the same manner as the voltage comparator shown in FIG. 1 in terms of timings, and recovery time is not necessary as is the case with the 3-input voltage comparator. However, in a reset period (3), since both switches are turned on, a clock noise generated in a transition period from the reset period to the fine comparison period cannot be canceled. 
     In the above embodiment, the circuit configuration is simplified for the purpose of simplifying the description. A general embodiment of the invention is illustrated in FIG. 4. In a voltage comparator shown in FIG. 4, as is the case with FIG. 1, the outputs of a coarse preceding comparison circuit 38 and a fine preceding comparison circuit 39 are connected to the input of a 2-input amplification circuit 32. The output of the 2-input amplification circuit 32 is connected to the inputs of amplification circuits 13c of series-connected m stages having a function of automatic zero compensation. The final output of the amplification circuits 13c of the series-connected m stages is connected to the input of inversion amplifiers 15 of series-connected n stages (n≧0). The coarse preceding comparison circuit 38 includes an input circuit 12, amplification circuits 13a of series-connected l stages (l≧1). The fine preceding comparison circuit 39 includes an input circuit 33 and amplification circuits 13b of series-connected k stages (k≧1). Thus, by connecting the amplification circuits 13a, 13b, 13c and the inversion circuits of a plurality of stages in series, a comparison result can be brought about to an appropriate potential. The above-stated m, n, l, and k are different from the bit numbers shown in FIG. 11. 
     FIG. 5 is a circuit diagram showing a fourth embodiment of the invention. A voltage comparator shown in FIG. 5 is different from the voltage comparator shown in FIG. 4 in that h (h&gt;2) preceding comparators 40 0  -40 h-1  are provided instead of two preceding comparators, an amplification circuit 41 having an automatic zero compensation function of h input nodes is provided instead of the 2-input amplification circuit. The voltage comparator shown in FIG. 5 allows an analog voltage Vin to be sequentially compared to reference voltages of different h levels (h≧2). A clock signal generation circuit 101 generates clock signals φ 0  -φ n+1  for controlling the voltage comparator. 
     FIG. 6 is a block diagram showing the preceding comparison circuit 40 h-1  shown in FIG. 5. FIG. 7 is a block diagram showing a plural-input amplification circuit 41 having an automatic zero compensation function shown in FIG. 5. Referring to FIG. 6, the preceding comparison circuit 40 h-1  includes an input circuit 46 and an amplification circuit 13 of l stages. This preceding comparison circuit 40 h-1  further includes an analog voltage application terminal 8, a reference voltage application terminal 42, a terminal 43 for inputting the clock signal φ1 for analog signal, a terminal 44 for inputting the clock signal φ p  for reference voltage, and a terminal 45 for inputting the clock signal φ1. The input circuit 46 includes a switch S9 connected to the analog voltage application terminal 8 and turned on/off in response to the input clock signal φ1, and a switch S10 connected to the reference voltage application terminal 42 and turned on/off in response to the clock signal φp input to the terminal 43. The switch S3 of the amplification circuit 13 (FIG. 1) is controlled by the clock signal φ1 input to the terminal 45. 
     Referring to FIG. 7, the plural-input amplification circuit 41 includes h input terminals I 0  -I h-1 , each of which is connected in common to the inversion amplifier 37 through a capacitor Cc p  (p=0-h-1). The output end of the inversion amplifier 37 is connected to its input end through the switch S6 controlled by the clock signal Δ0 for resetting. 
     Referring back to FIG. 5, the analog signal application terminal 8 is supplied with an analog voltage Vin, while the reference voltage application terminal 42 is supplied with reference voltages Vp (p=0-h-1) of different h levels. The clock signals φ1 and φp (p=2-h+1) are applied to the clock signal application terminals 43 and 44, respectively. The clock signal φ1 is applied to the terminal 45 (FIG. 6). 
     FIG. 8 is a timing chart showing an operation of the voltage comparator shown in FIGS. 5 to 7. The operation of the voltage comparator will be described in conjunction with FIG. 8. The voltage comparator operates in 2h stages. In a first period p 1  (a period when the clock signal φ1 is in &#34;H&#34; level), the preceding comparison circuit 40 inputs the analog signal voltage Vin and is set to auto zero (automatically set to V b  level). At that time, the plural-input amplification circuit 41 and the amplification circuits 13c of m stages connected in series to this amplification circuit 41 are set to auto zero. In a second period p 2  (a period when the clock signal φ2 is in &#34;H&#34; level), the preceding comparison circuit 40 for inputting a first reference voltage Vp 0  attains a comparison mode, and applies the reference voltage Vp 0 . At that time, all the above-stated amplification circuits 41 and 13 attain the comparison mode, and a voltage comparison between the analog input voltage Vin and the reference voltage Vp 0  is conducted. In a third period p 3 , the plural-input amplification circuit 41 and the amplification circuits 13 of m stages connected in series thereto are once again set to auto zero, and the above-stated first comparison result is reset. Then, when the clock signal φ3 is in &#34;H&#34; level, in other words in a fourth period p 4 , the preceding comparison circuit 40 for inputting a second reference voltage Vp 1  attains a comparison mode, and inputs the reference voltage Vp 1 . At that time, the above-stated amplification circuits 41 and 13 again attain the comparison mode, and a voltage comparison between the analog input voltage Vin and the reference voltage Vp 1  is conducted. Thereafter, similarly repeating the voltage comparison, the reference voltages Vp 0  -Vp h-1  in the H level are subjected to comparison in time series. 
     FIG. 9 is a circuit diagram showing a fifth embodiment of the invention. A voltage comparator in FIG. 9 is different from the voltage comparator shown in FIG. 5 in that 2 or more plural-input amplification circuits are used. Referring to FIG. 9, the voltage comparator includes first, second, and third preceding comparison circuits 400, 401, and 403 provided correspondingly to reference voltages Vp 0  -Vp 2  of three levels, a first 2-input amplification circuit 47 connected to the outputs of the first and second preceding comparison circuits 400 and 401, a second 2-input amplification circuit 48 connected to the amplification circuit 47 and the third preceding comparison circuit 402, amplification circuits 13 of m stages (m≧0) connected in series to the amplification circuit 48, and inversion amplifiers 15 of n stages (n≧0) connected in series to the amplification circuits 13. 
     Now, an operation of the fifth embodiment will be described. The voltage comparator operates in six stages. In the first stage, the first to third preceding comparison circuits 400 and 401, the first and second 2-input amplification circuits 47 and 48, and the amplification circuit 18 are all set to auto zero (automatically set to V b  level). At that time, the first preceding comparison circuit 400 inputs an analog signal voltage Vin. In the second stage, the first preceding comparison circuit 400 attains a comparison mode, and inputs the reference voltage Vp 0 . At that time, the amplification circuits 47, 48, and 13 all attain the comparison mode, and a voltage comparison between Vin and Vp 0  is conducted. In the third stage, the amplification circuits 47, 48, and 13 are once again set to auto zero, thus resetting the first comparison result. In the fourth stage, the second preceding comparison circuit 401 for inputting the second reference voltage Vp 1  attains a comparison mode, and inputs the reference voltage Vp 1 . At that time, the amplification circuits 47, 48, and 13 once again attain the comparison mode, and a voltage comparison between Vin and Vp 1  is conducted. In the fifth stage, the amplification circuits 48 and 13 are once again set to auto zero, thus resetting the second comparison result. In the sixth stage, the third preceding comparison circuit 402 for inputting the third reference voltage Vp 2  attains a comparison mode, and inputs the reference voltage Vp 2 . At that time, the amplification circuits 48 and 13 also once again attain the comparison mode, and a voltage comparison between Vin and Vp 2  is conducted. Thus, comparison between the analog signal voltage and the reference voltages of three levels can be conducted. 
     Although in the first to fifth embodiments, the bias voltages (threshold voltages) for the amplification circuits having an automatic zero compensation function or the plural-input amplification circuit are set by switches for feed back, but the invention is by no means limited thereto. For example, such biasing can be implemented by a circuit as shown in FIG. 10. 
     Referring to FIG. 10, the amplification circuit having an automatic zero compensation function is connected to the inversion amplifier 16 through a 3-input coupling capacitor Cc. The input of the inversion amplifier 16 is also connected to the output of the bias generation circuit 49 through the switch controlled by the clock signal φ. The bias generation circuit 49 generates a voltage signal in an approximately identical level to a logic threshold voltage Vb. 
     In operation, the inversion amplifier 16 is reset by a bias voltage generated by the bias generation circuit 49. 
     FIG. 11 is a block diagram showing a subranging A/D converter in accordance with a sixth embodiment of the invention. The A/D converter shown in FIG. 11 is different from the A/D converter shown in FIG. 12 in that a voltage comparator including a coarse preceding comparator 30, a fine preceding comparator 31, an amplification circuit 32, and an inverter 15 shown in FIG. 11 is provided instead of the voltage comparator shown in FIG. 13. The other circuit elements are the same as those shown in FIG. 12. In FIG. 11, for the purpose of simple representation, the coarse and fine preceding comparators 30 and 31 of the same number are shown. 
     Operations of the circuits 30, 31, 32, and 15 are the same as those already described in conjunction with FIG. 1. 
     As shown in FIG. 11, since the amplification circuit 32 and the inverter 15 for resetting and amplifying a coarse comparison result and a fine comparison result can be shared between the coarse part and the fine part, this subranging A/D converter can be implemented with a reduced number of elements as compared to conventional ones. 
     The voltage comparator used in this A/D converter, as described above, can operate at a high speed with high accuracy, and, therefore, high speed and highly accurate A/D conversion operation can be achieved. 
     Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.