Abstract:
An image sensor array is provided with: a first CCD image sensor configured to output a plurality of first signal voltages from a first output terminal; a second CCD image sensor configured to output a plurality of second signal voltages from a second output terminal; a switch circuit selectively connecting one of the first and second output terminals to a signal voltage output terminal; and a timing generator circuit responsive to a basic clock for generating first and second control signals and switch control signals. The first and second control signals are used for controlling generation of the plurality of first and second signal voltages, respectively. The switch control signals are used for controlling the switch circuit. The timing generator circuit controls the first and second CCD image sensors so that the first and second CCD image sensors output the plurality of first signal voltages and the plurality of second signal voltages, alternately. The timing generator circuit controls the switch circuit so that switch circuit outputs from the signal voltage output terminal one of the plurality of first signal voltages and one of the plurality of second signal voltages, alternately.

Description:
INCORPORATION BY REFERENCE 
       [0001]    This application claims the benefit of priority based on Japanese Patent Application No. 2007-151278, filed on Jun. 7, 2007, the disclosure of which is incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a CCD (charge coupled device) image sensor, more particularly, to a CCD image sensor adapted to resolution switching. 
         [0004]    2. Description of the Related Art 
         [0005]    Multi-function printers (MFP), which are complex machines having functions of an image scanner, a facsimile, a printer and so on, have become popular due to the technical advancement in recent years. In multi-function printers, the following two types of sensors have been put into practical use: an CCD image sensor adapted to optical image reduction with an optical lens; and a contact image sensor (CIS) comprising a contact rod lens and a color cell guide having a built-in LED emitting device, which is more cost-effective. 
         [0006]    Various types of contact image sensors are known in the art. One example is a CMOS image senor array in which a plurality of CMOS image sensor chips are arranged and another example is a CCD image sensor array in which a plurality of CCD image sensors are arranged as disclosed in Japanese Laid-Open Patent Application No. JP-A Heisei 11-234473. 
         [0007]      FIG. 1  is a block diagram illustrating the configuration of a prototype image sensor array provided with a pair of CCD image sensors, which has been developed by the inventor. The image sensor array shown in  FIG. 1  is provided with first and second CCD image sensors  101  and  102 , a timing generator  103 , and a switch circuit  111 . 
         [0008]    The first and second CCD image sensors  101  and  102  are each provided with: a plurality of photodiodes for photoelectric conversion; memories temporarily holding electric charges received from the photodiodes; and a CCD shift register transferring the electric charges received from the memories to the output terminal. A first transfer gate is provided between the photodiodes and the memories, and a second transfer gate is provided between the memories and the CCD shift register. 
         [0009]    The timing generator  103  has a function of supplying control signals (which may be referred to as clock pulses, hereinafter) required for driving these CCD image sensors. The timing generator  103  is connected to the first and second CCD image sensors  101  and  102 , and supplies a first transfer gate signal ΦTG 100  to the first and second CCD image sensors  101  and  102 . The timing generator  103  also feeds control signals (referred to as the first CCD control signals  116 , hereinafter) to the first CCD image sensor  101 , including a first CCD second transfer gate signal ΦTG 101 , a first CCD non-inverted clock Φ 101 , a first CCD inverted clock Φ 101 B, a first CCD last gate pulse Φ 101 L, and a first CCD reset gate pulse Φ 101 R. In addition, the timing generator  103  feeds control signals (referred to as the second CCD control signals  117 , hereinafter) to the second CCD image sensor  102 , including a second CCD second transfer gate signal ΦTG 102 , a second CCD non-inverted clock Φ 102 , a second CCD inverted clock Φ 102 B, a second CCD last gate pulse Φ 102 L, and a second CCD reset gate pulse Φ 102 R. 
         [0010]    The first transfer gate signal ΦTG 100  is applied to the first transfer gates within the first and second CCD image sensors  101  and  102  to activate the first transfer gates at desired timings. The first CCD second transfer gate signal ΦTG 101  is applied to the second transfer gate of the first CCD image sensor  101 . The first CCD non-inverted clock Φ 101  and the first CCD inverted clock Φ 101 B are applied to the CCD shift register of the first CCD image sensor  101 . The first CCD last gate pulse Φ 101 L is applied to the final stage of the electric charge transfer channel of the first CCD image sensor  101 . The first CCD reset gate pulse Φ 101 R is applied to a reset gate of the electric charge transfer channel of the first CCD image sensor  101 . The second CCD second transfer gate signal ΦTG 102  is applied to a second transfer gate of the second CCD image sensor  102 . The second CCD non-inverted clock Φ 102  and the second CCD inverted clock Φ 102 B are applied to an electric charge transfer channel of the second CCD image sensor  102 . The second CCD last gate pulse Φ 102 L is applied to the final stage of the electric charge transfer channel of the second CCD image sensor  102 . The second CCD reset gate pulse Φ 102 R is applied to a reset gate of the electric charge transfer part of the second CCD image sensor  102 . 
         [0011]    The first and second CCD control signals  116  and  117  are generated by the timing generator  103  and supplied to the first and second CCD image sensors  101  and  102 , so that the output voltage signals of the first and second CCD image sensors  101  and  102  (which may be referred to as the first and second CCD output voltages V OUT101 , and V OUT102 , respectively) do not overlap each other in the time domain. 
         [0012]    The switch circuit  111  has a function of selecting the output voltage signals supplied from the first and second CCD image sensors  101  and  102 . The switch circuit  111  is connected to the first and second CCD image sensors  101  and  102 . The switch circuit  111  is responsive to first and second switch timing control signals SW 101  and SW 102  received from the timing generator  103  for selecting one of the output signals from the first and second CCD image sensors  101  and  102 . The selected output signal is outputted from the switch circuit  111  as a final output voltage  112 . 
         [0013]      FIG. 2  is a timing chart illustrating operation timings of the first and second CCD image sensors  101  and  102 . The first and second CCD image sensors  101  and  102  have the same configuration, and the operation of the first CCD image sensor  101  is same as the operation of the second CCD image sensor  102 . Therefore, a description is given in the following only of the first CCL image sensor  101 . 
         [0014]      FIG. 2  shows the waveforms of the first transfer gate signal ΦTG 100 , the first CCD second transfer gate signal ΦTG 101 , the first CCD non-inverted clock Φ 101 , the first CCD inverted clock Φ 101 B, the first CCD last gate pulse Φ 101 L, the first CCD reset gate pulse Φ 101 R, and the first CCD output voltage V OUT101 . 
         [0015]    When externally receiving a light signal, the first CCD image sensor  101  provides photoelectric conversion by using PN junctions within the photodiodes of the first CCD image sensor  101  to thereby generate electric charge signals. At the time t 01  when the accumulation of the electric charge signals is completed for one line, the first transfer gate signal ΦTG 100  is pulled up to the high level to turn on the first transfer gate within the first CCD image sensor  101 . At this time, electric charges are transferred from the photodiodes to the memory within the first CCD image sensor  101 . At the time t 02 , the first transfer gate signal ΦTG 100  is then pulled down to the low level to turn off the first transfer gate. 
         [0016]    This is followed by switching the first CCD second transfer gate signal ΦTG 101  from the low level to the high level at the time t 03 , allowing the electric charges accumulated in the respective memories of the first CCD image sensor  101  are transferred to the CCD shift register connected to the memories at the reading timings of the CCD image sensors. 
         [0017]    At the time t 04 , the first CCD second transfer gate signal ΦTG 101  is switched from the high level to the low level to complete the transfer of the electric charges from the memories to the CCD shift register. The CCD shift register is provided with electrodes which receives the first CCD non-inverted clock Φ 101  and the first CCD inverted clock Φ 101 B, respectively. The first CCD non-inverted clock Φ 101  and the first CCD inverted clock Φ 101 B are set to the high level and the low-level, respectively, and thereby the electric charges transferred to the CCD shift register are sequentially transferred to the last gate. 
         [0018]    The first CCD last gate pulse Φ 101 L is fed to the last gate. At the time t 05 , the first CCD last gate pulse Φ 101 L is switched from the high level to the low level to allow the electric charges to be injected into a CFJ (Capacitor Floating Junction) provided at the subsequent stage of the last gate. The CFJ has a function of converting an electric charge signal into a voltage signal with a capacitive element. The accumulated electric charges are converted into the first CCD output voltage V OUT101 , by the CFJ, and the first CCD output voltage V OUT101  is signal-amplified by an amplifier connected to the output of the CFJ. 
         [0019]    A reset gate transistor is connected to the CFJ for initialization of the electric charges accumulated across the CFJ. The first CCD reset gate pulse Φ 101 R is fed to the gate terminal of the reset gate transistor. When the first CCD reset gate pulse Φ 101 R is switched from the low level to the high level, a VRD voltage of a predetermined voltage level (for example, 10V) is applied to the gate terminal to clear off the electric charges across the CFJ. 
         [0020]    In the following, a description is given of the operation of the image sensor array, which incorporates the first and second CCD image sensors  101  and  102 .  FIG. 3  is a timing chart showing the operation of the image sensor array of  FIG. 1 . It should be noted that the first CCD control signals  116 , including the first CCD second transfer gate signal ΦTG 101 , the first CCD non-inverted clock Φ 101 , the first CCD inverted clock Φ 101 B, the first CCD last gate pulse Φ 101 L, and the first CCD reset gate pulse Φ 101 R, are fed to the first CCD image sensor  101 , while the second CCD control signals  117 , including the second CCD second transfer gate signal (ΦTG 102 , the second CCD non-inverted clock Φ 102 , the second CCD inverted clock Φ 102 B, the second CCD last gate pulse Φ 102 L, and the second CCD reset gate pulse Φ 102 R, are fed to the second CCD image sensor  102 . 
         [0021]    The basic operation of the first and second CCD image sensors  101  and  102  is as described above. After the first and second CCD image sensors  101  and  102  receive light for a certain period of time, electric charges are accumulated across the photodiodes integrated therein. At the time t 11 , the first transfer gate signal ΦTG 100  which is fed to both of the first and second CCD image sensors  101  and  102 , is pulled up to the high level to thereby turn on the first transfer gates within the first and second CCD image sensors  101  and  102 , simultaneously. As a result, the electric charges are transferred to the memories within each CCD image sensor in the period between the time t 11  and the time t 12 . 
         [0022]    This is followed by pulling up the first CCD second transfer gate signal ΦTG 101  to the high level at the time t 13 , in order to output the electric charges accumulated in the memories of the first CCD image sensor  101  in first. The pull-up of the first CCD second transfer gate signal ΦTG 101  allows the electric charges accumulated in the memories to be transferred to the CCD shift register in the first CCD image sensor  101 . 
         [0023]    At the time t 14 , the first switch timing control signal SW 101  is switched to the high level to allow the switch circuit  111  to select the output of the first CCD image sensor  101 , in order to output the pixel signal of the first CCD image sensor  101  in first. Thereafter, the first CCD control signals  116  are supplied to operate the first CCD image sensor  101 , so that pixel signals are sequentially supplied from the first CCD image sensor  101  to the switch circuit  111 . The switch circuit  111  outputs the final output voltage  112  in accordance with the pixel signals. 
         [0024]    Next, the second CCD second transfer gate signal ΦTG 102  is pulled up to the high level at time t 15 . The pull-up of the second CCD second transfer gate signal ΦTG 102  allows the electric charges accumulated in the memories of the second CCD image sensor  102  to be transferred to the CCD shift register of the second CCD image sensor  102 . At the time t 16 , the second switch timing control signal SW 102  is then pulled up to the high level to allow reading the pixel signal of the second CCD image sensor  102 , and the first switch timing control signal SW 101  is pulled down to the low level. This allows the switch circuit  111  to select the pixel signals received from the second CCD image sensor  102 . Thereafter, the second CCD control signals  117  are fed to operate the second CCD image sensor  102  so that the pixel signals are sequentially supplied from the second CCD image sensor  102  to the switch circuit  111 . The switch circuit  111  outputs the final output voltage  112  in accordance with the pixel signals from the second CCD image sensor  102 . 
         [0025]    The image sensor array shown in  FIG. 1  operates as thus described, outputting the pixel signals from the photodiodes integrated within the CCD image sensors. 
         [0026]    CCD image sensors are often adapted to resolution switching. Typically, such a CCD image sensor is designed to operate in a low resolution mode in addition to the normal operation mode. In the following, an exemplary operation of the CCD image sensor for the low resolution mode will be described. Specifically, a description is given of a case when pixel signals from two pixels are added together to generate a resultant output signal in a read operation. Such operation may be also referred to as the multiple-pixel addition mode or referred to as the two-pixel addition mode for indicating that the number of relevant pixels is two. The person skilled in the art would recognize that the operation of the two-pixel addition mode results in the reduction in the resolution of the image sensor array down to half of the original resolution. 
         [0027]      FIG. 4  is a timing chart showing operation timings of the first and second CCD image sensors  101  and  102  in the low resolution mode. As described above, the configuration and operation of the first and second CCD image sensors  101  and  102  are same. Therefore, the following description will be directed to the operation of the first CCD image sensor  101  in the low resolution mode. 
         [0028]      FIG. 4  shows waveforms of the first transfer gate signal ΦTG 100 , the first CCD second transfer gate signal ΦTG 101 , the first CCD non-inverted clock Φ 101 , the first CCD inverted clock Φ 101 B the first CCD last gate pulse Φ 101 L, the first CCD reset gate pulse Φ 101 R.  FIG. 4  also shows the amount of electric charges injected into the CFJ. 
         [0029]    From the time t 21  to t 24 , the operation in the two-pixel addition mode is same as the operation shown in  FIG. 2 . As shown in  FIG. 4 , cycle periods of the first CCD last gate pulse Φ 101 L and the first CCD reset gate pulse Φ 101 R are half of those of the first CCD non-inverted clock Φ 101  and the first CCD inverted clock Φ 101 B. In this operation, electric charges of the two adjacent pixels are added together at the last gate. When a series of four photodiodes are used as first to fourth pixels of the CCD image sensor  101 , for example, the electric charges of the first and second pixels, which are positioned adjacent to each other, are added together at the last gate, and the electric charges of the third and fourth pixels are added together at the last gate. 
         [0030]    At the time t 24 , the second transfer gate signal ΦTG  101  is switched from the high level to the low level. At the time t 25 , the first CCD non-inverted clock Φ 101  is switched from the high level to the low level, and this allows the electric charges generated within the first pixel to be transferred from the CCD shift register to the last gate. At the time t 25 , the electric charges of the first pixel are accumulated at the last gate without being transferred to the CFJ, since the first CCD last gate pulse Φ 101 L is set to the high level. The first CCD non-inverted clock Φ 101  is switched from the low level to the high level after the time t 25 , and then switched from the high level to the low level at the time t 26 . Similarly, the first CCD inverted clock Φ 101 B is switched from the high level to the low level after the time t 25 , and switched from the low level to the high level at the time t 26 . 
         [0031]    At the time t 26 , the electric charges generated within the second pixel are transferred from the CCD shift register and to the last gate. This allows the electric charges of the first and second pixels to be added together at the last gate. Moreover, at the time t 26 , the first CCD last gate pulse Φ 101 L is switched from the high level to the low level to transfer the electric charges of the first and second pixels accumulated at the last gate to the CFJ. The electric charges obtained by adding together the electric charges of the first and second pixels are converted into a signal voltage by the CFJ, and the resultant signal voltage is outputted from the CFJ. 
         [0032]    This is followed by pulling up the first CCD reset gate pulse Φ 101 R to the high level at the time t 27  to initialize the CFJ. The first CCD last gate pulse Φ 101 L is also pulled up to the high level at the time t 27 . 
         [0033]    Similar operation is then implemented for the third and fourth pixels. The first CCD last gate pulse Φ 101 L is kept at the high level from the time t 27  to t 29 . In the meantime, the first CCD non-inverted clock Φ 101  is switched from the low level to the high level and then to the low level. Similarly, the first CCD inverted clock Φ 101 B is switched from the high level to the low level and then to the high level. At the time t 28 , the electric charges generated within the third pixel are transferred to the last gate through the CCD shift register. Subsequently, the first CCD non-inverted clock Φ 101  is switched from the low level to the high level and then to the low level, while the first CCD inverted clock Φ 101 B is switched from the high level to the low level and then to the high level. At the time t 29 , the electric charges generated within the fourth pixel is transferred to the last gate. 
         [0034]    At the time t 29 , the first CCD non-inverted clock Φ 101  is switched from the high level to the low level, and the first CCD last gate pulse Φ 101 L is switched from the high level to the low level. This results in that the electric charges of the third and fourth pixels are added together at the last gate, and the electric charges accumulated at the last gate are transferred to the CFJ. This completes the output of the pixel signals associated with the electric charges from the photodiodes within the CCD image sensor. 
         [0035]    Hereinafter, a description is given of the overall operation of the image sensor array provided with the first and second CCD image sensors  101  and  102 , when the image sensor array is placed into the two-pixel addition mode, which results in the reduction of the resolution down to one half. 
         [0036]      FIG. 5  is a timing chart showing the operation of the image sensor array in the two-pixel addition mode. It should be noted that the first CCD control signals  116 , including the first CCD second transfer gate signal ΦT 101 , the first CCD non-inverted clock Φ 101 , the first CCD inverted clock Φ 101 B, the first CCD last gate pulse ΦT 101 L, and the first CCD reset gate pulse Φ 101 R, are fed to the first CCD image sensor  101 , while the second CCD control signals  117 , including the second CCD second transfer gate signal ΦTG 102 , the second CCD non-inverted clock Φ 102 , the second CCD inverted clock Φ 102 B, the second CCD last gate pulse Φ 102 L, and the second CCD reset gate pulse Φ 102 R, are fed to the second CCD image sensor  102 . The basic operation of the first and second CCD image sensors  101  and  102  is same as the operation described referring to  FIG. 4 . 
         [0037]    At the time t 31 , the first switch timing control signal SW 101  is switched to the high level to select the output of the first CCD image sensor  101 . This allows outputting the pixel signals of the first CCD image sensor  101  in first. In the meantime, electric charges generated within the photodiodes are transferred to the memories before the time t 32  within each of the CCD image sensors  101  and  102 . 
         [0038]    The electric charges accumulated in the memories are transferred to the CCD shift register within the first CCD image sensor  101  in response to the first CCD second transfer gate signal ΦTG 101 . The first CCD control signals  116  are fed to the first CCD image sensor  101  so as to operate the first CCD image sensor  101  in the two-pixel addition mode (in which the resolution is reduced to one half), and signal voltages are sequentially outputted from the first CCD image sensor  101  with the electric charges of two adjacent pixels added together. 
         [0039]    This is followed by pulling up the second switch timing control signal SW 102  to the high level to select the second CCD image sensor  102 , while the first switch timing control signal SW 101  is pulled down to the low level This allows outputting the pixel signals of the second CCD image sensor  102  from the switch circuit  111 . Before that, the second CCD second transfer gate signal ΦTG 102  is switched to the high level to transfer the electric charges from the memories to the CCD shift register within the second CCD image sensor  102 . 
         [0040]    Thereafter, the second CCD control signals  117  are fed to the second CCD image sensor  102  so that the second CCD image sensor  102  operates in the two-pixel addition mode (in which the resolution is reduced to one half), and signal voltages are sequentially outputted from the second CCD image sensor  102  with the electric charges of two adjacent pixels added together. 
         [0041]    One requirement of a CCD image sensor array is the reduction of the image reading time. The inventor has discovered that there is a room for reducing the image reading time in operating the image sensor array in the low resolution mode. In the above-described operation of the prototype CCD image sensor array, the image reading time in reading pixel signals with a normal resolution (or a high resolution) is same as that in reading pixel signals with a low resolution (or a multiple-pixel addition mode). The reading speed or charge transfer speed of a CCD image sensor is determined by the speed of transferring electric charges over the CCD shift register. Therefore, the CCD image sensor array suffers from a difficulty in enhancing the image reading speed over the maximum transfer speed of the CCD shift register, even when the image sensor array is operated in a multiple-pixel addition mode with a low resolution), This may result in that the user feels that the reading speed is slow when the image sensor array is placed into the multiple-pixel addition mode (with a low resolution). This is a problem to be avoided for both a customer who uses a scanner and a company which manufactures the scanner by using a contact image sensor device. 
         [0042]    One may consider that the image reading time is sufficiently short when an image scanner is operated in a preview mode or the like; however, the reduction of the image reading time in a preview mode is actually achieved by omission of reading pixel signals for some pixels. The omission of reading pixel signals for some pixels allows reducing the image data conversion time and the image data transfer time. Further, the read operation from the pixels in the sub-scanning direction is not done for all of the lines of the CCD image sensor; the read operation is only performed for every multiple lines. 
         [0043]    One potential approach to solve this problem may be to increase the charge transfer speed of the CCD shift register. For example, Japanese Laid-Open Patent Application No. JP-A Heisei 11-308409 discloses that the cycle period of the charge transfer clock is increased up to double of the normal operation mode, when the CCD image sensor chip is operated with a half resolution mode. However, the skilled person would appreciate the technical difficulty in increasing the charge transfer speed. The maximum charge transfer speed of the CCD shift register is determined by the voltage waveform of the non-inverted clock and the inverted clock supplied to the CCD shift register and by the dose amount of ions injected into the CCD shift register. Typically, signal levels of the non-inverted and inverted clocks fed to the CCD shift register are fixed to 5V or 3.3V. The signal levels of the non-inverted and inverted clocks determine the maximum operation speed and transferable electric charge amount of the CCD shift register. 
         [0044]    One potential approach for enhancing the operation speed of the CCD shift register is to shallow the potential of the CCD shift register by reducing the dose amount of ions injected into the CCD shift register. However, the reliable operation of the CCD shift register requires a certain amount of electric charges enough to develop a pixel signal with a voltage level of 1 to 2V or more. Therefore, it is not preferable to excessively reduce the dose amount of ions injected into the CCD shift register. Another potential approach may be to shallow the potential of the CCD shift register with the width thereof increased in order to increase the volume of electric charges stored in the CCD shift register. However, this approach undesirably increases the chip size, causing the cost increase of the CCD image sensors. 
       SUMMARY 
       [0045]    In an aspect of the present invention, an image sensor array is provided with: a first CCD image sensor configured to output a plurality of first signal voltages from a first output terminal; a second CCD image sensor configured to output a plurality of second signal voltages from a second output terminal; a switch circuit selectively connecting one of the first and second output terminals to a signal voltage output terminal; and a timing generator circuit responsive to a basic clock for generating first and second control signals and switch control signals. The first and second control signals are used for controlling generation of the plurality of first and second signal voltages, respectively. The switch control signals are used for controlling the switch circuit. The timing generator circuit controls the first and second CCD image sensors so that the first and second CCD image sensors output the plurality of first signal voltages and the plurality of second signal voltages, alternately. The timing generator circuit controls the switch circuit so that switch circuit outputs from the signal voltage output terminal the plurality of first signal voltages and the plurality of second signal voltages, alternately. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0046]    The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which: 
           [0047]      FIG. 1  is a block diagram showing a configuration of a prototype CCD image sensor array; 
           [0048]      FIG. 2  is a timing chart showing a basic operation of a CCD image sensor within the prototype CCD image sensor array shown in  FIG. 1 ; 
           [0049]      FIG. 3  is a timing chart showing the operation of the prototype CCD image sensor array shown in  FIG. 1 ; 
           [0050]      FIG. 4  is a timing chart showing the operation of the CCD image sensor when the CCD image sensor is operated so that the resolution thereof is reduced down to one half of the original resolution (the operation of two-pixel addition mode); 
           [0051]      FIG. 5  is a timing chart showing the overall operation of the image sensor array when the image sensor array is operated so that the resolution thereof is reduced down to one half of the original resolution (the operation of two-pixel addition mode); 
           [0052]      FIG. 6  is a block diagram illustrating a configuration of a contact image sensor of a first embodiment; 
           [0053]      FIG. 7  is a block diagram illustrating a configuration of a CCD image sensor array of the first embodiment; 
           [0054]      FIG. 8  is a block diagram illustrating a configuration of a CCD image sensor of the image sensor array of the first embodiment; 
           [0055]      FIG. 9  is a timing chart showing an operation of the CCD image sensor array of the first embodiment; 
           [0056]      FIG. 10  is a block diagram illustrating the configuration of a CCD image sensor array of a second embodiment; and 
           [0057]      FIG. 11  is a timing chart illustrating the operation of the CCD image sensor array of the second embodiment. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0058]    The invention will now be described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes. 
       First Embodiment  
       [0059]    Hereinafter, embodiments of the present invention will be described, referring to the accompanying drawings. In embodiments below, a description is given with an assumption that a CCD image sensor array of the present invention is incorporated within a contact image sensor device; however, this does not mean that the present invention is applied only to contact image sensors. 
         [0060]      FIG. 6  is a block diagram illustrating the configuration of a contact image sensor device  1  in a first embodiment of the present invention. Referring to  FIG. 6 , the contact image sensor device  1  is provided with an image sensor unit  10 , a color cell guide  4 , and a contact rod lens  5 . A glass plate  6  is provided on the top of the contact image sensor device  1 . A target document  7  is placed on the glass plate  6 . The contact image sensor device  1  is driven to travel in a vertical direction of the document  7  in order to read the image and/or text on the document  7 . 
         [0061]    The color cell guide  4  incorporates LED light sources which emit red, blue, and green lights. The lights emitted by the LED light sources travels across the color cell guide  4  to generate illumination light  8 . The generated illumination light  8  is evenly exposed to the document surface  7   a . The document surface  7   a  reflects the illumination light  8  to generate reflected light  9  which contains color information of the document  7 . The reflected light  9  enters the contact rod lens  5  through the glass plate  6 , and then enters the CCD image sensor array  2  located under the contact rod lens  5 . 
         [0062]    The light incident on the CCD image sensor array  2  is photoelectrically converted into electric signals (or color signals) by photodiodes within the CCD image sensor array  2 . The color signals generated by the contact image sensor device  1  are transmitted to an A/D (analog/digital) converter integrated within an image scanner or the like, and are converted into digital signals that can be handled by computers. 
         [0063]    Referring again to  FIG. 7 , the image sensor unit  10  includes a CCD image sensor array  2 , a timing generator circuit  3 , and a switch circuit  11 . The CCD image sensor array  2  includes first and second CCD image sensors CCD- 1  and CCD- 2 , which are both connected to the timing generator circuit  3 . 
         [0064]    The timing generator circuit  3  controls the operation timings of the CCD image sensors CCD- 1  and CCD- 2 . More specifically, the timing generator circuit  3  feeds a first transfer gate signal ΦTG 1  to both the first and second CCD image sensors CCD- 1  and CCD- 2 . Moreover, the timing generator circuit  3  feeds first control signals CTL 1  to the first CCD image sensor CCD- 1 , and feeds second control signals CTL 2  to the second CCD image sensor CCD- 2 . In this embodiment, the first control signals CTL 1  includes a first CCD second transfer gate signal ΦTG 2 - 1 , a first CCD non-inverted clock Φ 1 , a first CCD inverted clock Φ 1 B, a first CCD last gate pulse Φ 1 L, and a first CCD reset gate pulse Φ 101 R. Correspondingly, the second control signals CTL 2  includes a second CCD second transfer gate signal ΦTG 2 - 2 , a second CCD non-inverted clock Φ 2 , a second CCD inverted clock Φ 2 B, a second CCD last gate pulse Φ 2 L, and a second CCD reset gate pulse Φ 2 R. The first and second CCD last gate pulses Φ 1 L and Φ 2 L are low-active signals, while the first and second CCD reset gate pulses Φ 1 R and Φ 2 R are high-active signals, in this embodiment. 
         [0065]    The first CCD image sensor CCD- 1  has an output terminal  13  connected to the switch circuit  11 . Similarly, the second CCD image sensor CCD- 2  has an output terminal  14  connected to the switch circuit  11 . The switch circuit  11  receives signal voltages V OUT1  and V OUT2  respectively outputted from the first and second CCD image sensors CCD- 1  and CCD- 2 , and selects one of the signal voltages V OUT1 , and V OUT2 . The switch circuit  11  outputs the selected signal voltage from a resultant signal voltage output terminal  15 . The switch circuit  11  is responsive to first and second switch control signals SW- 1  and SW- 2  received from the timing generator circuit  3  for selecting the signal voltages V OUT1  and V OUT2  received from the CCD image sensors CCD- 1  and CCD- 2 . 
         [0066]    Hereinafter, a description is given of the configuration of the first and second CCD image sensors CCD- 1  and CCD- 2 . In the present embodiment, the configuration of the first CCD image sensors CCD- 1  is same as that of the second CCD image sensors CCD- 2 , except for that the second CCD image sensors CCD- 2  receives the control signals CTL 2  in place of the control signals CTL 1  Therefore, the description below mainly refers to the first CCD image sensors CCD- 1 . 
         [0067]      FIG. 8  is a block diagram illustrating the configuration of the first CCD image sensor CCD- 1  (and the second CCD image sensor CCD- 2 ). The first CCD image sensor CCD- 1  is provided with: a photodiode array  20 , a first transfer gate array  21 , a memory array  22 , a second transfer gate array  23 , a CCD shift register  24 , a last gate  25 , a reset gate transistor  26 , a CFJ (Capacitor Floating Junction)  27 , and an amplifier  28 . 
         [0068]    The photo diode array  20 A comprises a plurality of photodiodes arranged laterally. For simplicity, it is assumed that four photodiodes (first to fourth pixel photodiodes  20 A to  20 D) are provided within the first CCD image sensor CCD- 1  (and the second CCD image sensor CCD- 2 ) in this embodiment; however, the skilled person would appreciate that the number of the photodiodes within the CCD image sensors CCD- 1  and CCD- 2  is not limited to four. 
         [0069]    The first transfer gate array  21  comprises transfer gates  21 A to  21 D which transfer electric charges from the pixel photodiodes  20 A to  20 D to the memory array  22 , respectively. The transfer gates  21 A to  21 D are responsive to the first transfer gate signal ΦTG 1  for transferring the electric charges to the memory array  22 . 
         [0070]    The memory array  22  comprises a plurality of memories, referred to as first to fourth pixel memories  22 A to  22 D, which temporarily store electric charges received from the photodiodes  20 A to  20 D, respectively. 
         [0071]    The second transfer gate array  23  is comprises transfer gates  23 A to  23 D which transfer electric charges from the first to fourth pixel memories  22 A to  22 D to the CCD shift register  24 . The transfer gates  23 A to  23 D are responsive to the first CCD second transfer gate signal ΦTG 2 - 1  for transferring the electric charges to the memory array  22 . 
         [0072]    The CCD shift register  24  transfer electrical charges received from the first to fourth pixel memories  22 A to  22 D to the last gate  25 , which is connected to the output of the CCD shift register  24 . The CCD shift register  24  comprises serially-connected charge shift elements  24 A to  24 D which are connected with the pixel memories  22 A to  22 D, respectively. Each of the charge shift elements  24 A to  24 D of the CCD shift registers  24  is provided with a pair of electrodes receiving the first CCD non-inverted clock Φ 1  and the first CCD inverted clock Φ 1 B, respectively. 
         [0073]    The last gate  25  transfers the electric charges from the CCD shift register  24  to the CFJ  27  in response to the first CCD last gate pulse Φ 1 L. The CFJ  27  is a capacitive element which converts the electric charge signal received from the last gate  25  into a voltage signal. The reset gate transistor  26  is connected to the CFJ  27  to initialize the CEJ  27 . The reset gate transistor  26  receives the first CCD reset gate pulse Φ 1 R on the gate thereof and resets the CFJ  27  to a predetermined reset voltage in response to the first CCD reset gate pulse Φ 1 R. The CFJ  27  is also connected to the amplifier  28  which amplifies the voltage signal obtained by the CFJ  27 . 
         [0074]    The first CCD image sensor CCD- 1  operates as follows: When light enters the photodiode array  20 , the photodiode array  20  provides photoelectrical conversion by using PN junctions to accumulate electric charge signals across the photodiodes. When the accumulation of the electric charge signals completes for one line, the first transfer gate array  21  is turned on to transfer the electric charges to the respective memories  22 A,  22 B,  22 C, and  22 D connected to the four photodiodes  20 A,  20 B,  20 C, and  20 D. After the completion of the electric charge transfer, the first transfer gate array  21  is turned off. 
         [0075]    The electric charges accumulated in the respective memories  22 A,  22 B,  22 C, and  22 D are transferred to the corresponding charge transfer elements  24 A,  24 B,  24 C, and  24 D of the CCD shift register  35  at the read timing of the respective CCD image sensors. This is followed by alternately switching the first CCD non-inverted clock Φ 1  and the first CCD inverted clock Φ 1 B between the high level and the low level, and thereby transferring the electric charges over the CCD shift register  24  from the charge transfer element  24 D, to the charge transfer element  24 C, to the charge transfer element  24 B, to the charge transfer element  24 A, and then to the last gate  25 . 
         [0076]    When the first CCD last gate pulse OIL is switched from the high level to the low level, the electric charges are injected into the CFJ  27 . The CFJ  27  converts the electric charge signal received from the last gate  25  into a voltage signal, and the voltage signal is amplified by the amplifier  28 . This allows outputting the signal voltage V OUT1  from the first CCD image sensor CCD- 1 . When the first CCD reset pulse Φ 1 R is then switched from the low level to the high level, a VRD voltage of a predetermined voltage level (for example, 10V) is applied to the CFJ  27  so that the electric charges across the CFJ  27  are cleared. 
         [0077]    The second CCD image sensor CCD- 2  is structured and operated identically, except for receiving the second CCD second transfer gate signal ΦTG 2 - 2 , the second CCD non-inverted clock Φ 2  and the second CCD inverted clock Φ 2 B, the second CCD last gate pulse Φ 2 L, and the second CCD reset gate pulse Φ 2 R in place of the first CCD second transfer gate signal ΦTG 2 - 1 , the first CCD non-inverted clock Φ 1  and the first CCD inverted clock Φ 1 B, the first CCD last gate pulse Φ 1 L, and the first CCD reset gate pulse Φ 1 R. 
         [0078]    Next, a description is given of the overall operation of the image sensor array of the present embodiment for the case when the image sensor array is placed in the two-pixel addition mode, with reference to  FIG. 9 . It should be noted that the resolution of the image sensor array is reduced down to one half of the original resolution thereof, when the image sensor array is operated in the two-pixel addition mode. It should be also noted that the operation of the image sensor array of the present embodiment in the normal operation mode is identical to that shown in  FIG. 3 , wherein the image sensor array is operated with the original resolution thereof. 
         [0079]    When the photodiodes integrated within the first and second CCD image sensors CCD- 1  and CCD- 2  receive light for a certain period of time, the received light is photoelectrically converted by the PN junctions of the photodiodes, and accumulated as electric charges. 
         [0080]    After the completion of the accumulation of the electric charges, the first transfer gate signal ΦTG 1  supplied is switched to the high level at the time t 51  to turn on the first transfer gate arrays  21  within both of the first and second CCD image sensors CCD- 1  and CCD- 2 . In a period from the time t 51  to the time t 52 , the electric charges accumulated across the photodiodes are transferred to the memory array  22  connected to the photodiodes. At the time t 52 , the timing generator circuit  3  pulls down the first transfer gate signal ΦTG 1  to the low level and thereby turns off the first transfer gate array  21 , thereby ending the charge transfer. 
         [0081]    This is followed by pulling up the first CCD second transfer gate signal ΦTG 2 - 1  to the high level at the time t 53 , and thereby transferring the electric charges stored in the memories are transferred to the CCD shift register  24  within the first CCD image sensor CCD- 1 . The second transfer gate array  23  of the first CCD image sensor CCD- 1  is activated in response to the pull-up of the first CCD second transfer gate signal ΦTG 2 - 1 . The electric charges accumulated in the memory array  22  are transferred to the CCD shift register  24  through the second transfer gate array  23  within the first CCD image sensor CCD- 1 . 
         [0082]    At this moment, as shown in  FIG. 9 , the timing generator circuit  3  previously sets the first CCD non-inverted clock Φ 1  to the high level and sets the first CCD inverted clock Φ 1 B to the low level, so that the CCD shift register  24  of the first CCD image sensor CCD- 1  receives the transferred electric charges. Thereafter, at the time t 54 , the timing generator circuit  3  pulls down the first CCD second transfer gate signal ΦTG 2 - 1  to the low level to turn off the second transfer gate array  23  of the first CCD image sensor CCD- 1 . 
         [0083]    At the time t 55 , the second CCD second transfer gate signal ΦTG 2 - 2  is then pulled up to the high level to activate the second transfer gate set  23  of the second CCD image sensor CCD- 2 . In response to the pull-up of the second CCD second transfer gate signal ΦTG 2 - 2 , the second transfer gate array  23  transfers the electric charges stored in the memory array  22  to the CCD shift register  24  within the second CCD image sensor CCD- 2 . At this moment, the second CCD non-inverted clock Φ 2  is previously set to the high level and the second CCD inverted clock Φ 2 B is previously set at the low level so that the electric charges can be received by the CCD shift register  24  of the second CCD image sensor CCD- 2 . Thereafter, the timing generator circuit  3  pulls down the second CCD second transfer gate signal ΦTG 2 - 2  to the low level at the time t 57  to turn off the second transfer gate array  23  within the second CCD image sensor CCD- 2 . 
         [0084]    In the present embodiment, as shown in  FIG. 9 , the activation timing of the second CCD second transfer gate signal ΦTG 2 - 2  fed to the second CCD image sensor CCD- 2  is shifted from that of the first CCD second transfer gate signal ΦTG 2 - 1  fed to the first CCD image sensor CCD- 1  by one cycle period of the first and second CCD non-inverted clocks Φ 1  and Φ 2 . In an alternative embodiment, the activation timing of the first CCD second transfer gate signal ΦTG 2 - 1  fed to the first CCD image sensor CCD- 1  may be same as that of the second CCD second transfer gate signal ΦTG 2 - 2  fed to the second CCD image sensor CCD- 2 . 
         [0085]    After the electric charges are transferred to the respective charge transfer elements  24 A to  24 D of the CCD shift register  24 , the electric charges are transferred over the CCD shift register  24  with the electric charge signals of the first and second pixel photodiodes  20 A and  20 B added together at the last gate  25  within the first CCD image sensor CCD- 1 . Specifically, the first CCD last gate pulse Φ 1 L is previously set to the high level before the charge transfer to the CCD shift register  24 . The first CCD non-inverted clock Φ 1  is then switched from the high level, to the low level, again to the high level, and then to the low level, while the first CCD inverted clock Φ 1 B is switched from the low level, to the high level, again to the low level, and then to the high level. 
         [0086]    At the time t 56 , the first CCD non-inverted clock Φ 1  is switched from the high level to the low level to allow the electric charges of the first pixel photodiode  20 A to be forwarded to the last gate  25  within the first CCD image sensor CCD- 1 . 
         [0087]    At the time t 57 , the first CCD non-inverted clock Φ 1  is switched from the low level to the high level. In the meantime, the first switch control signal SW- 1  is pulled up to the high level so that the signal voltage V OUT1  received from the first CCD image sensor CCD- 1  is selected by the switch circuit  11 . This allows externally outputting the field through level voltage (reference level voltage) and pixel signals from the first CCD image sensor CCD- 1 . 
         [0088]    At the time t 58 , the first CCD non-inverted clock Φ 1  is then switched from the high level to the low level for the second time to transfer the electric charges of the second pixel photodiode  20 B to the last gate  25 . This results in that the electric charges of first and second pixel photodiodes  20 A and  20 B are added together at the last gate  25 . 
         [0089]    This is followed by switching the first CCD last gate pulse Φ 1 L from the high level to the low level when the first non-inverted clock Φ 1  is pulled down to the low level for the second time at the time  58 . This allows the electric charges of the two pixels stored at the last gate  25  to be collectively transferred to the CFJ  27  within the first CCD image sensor CCD- 1 . The CFJ  27  converts the electric charges into a signal voltage and supplies the voltage signal to the amplifier  28 . The amplifier  28  amplifies the supplied signal voltage to output the signal voltage V OUT1 . After the signal detection period of the first CCD image sensor CCD- 1 , the first CCD reset pulse Φ 1 R is pulled up to the high level at the time t 59  to initialize the CFJ  27  for the preparation for the next signal accumulation. 
         [0090]    This is followed by outputting the signal voltage V OUT2  from the second CCD image sensor CCD- 2  with the electric charge signals of the first and second pixel photodiodes  20 A and  20 B added together at the last gate  25  within the second CCD image sensor CCD- 2 . In order to avoid the signal voltage V OUT2  overlapping the signal voltage V OUT1  from the first CCD image sensor CCD- 1  the activation timings of the second CCD non-inverted clock Φ 2 , the second CCD inverted clock Φ 2 B, the second CCD last gate pulse Φ 2 L, and the second CCD reset pulse Φ 2 R are shifted from those of the first CCD non-inverted clock Φ 1 , the first CCD inverted clock Φ 1 B, the first CCD last gate pulse Φ 1 L, and the first CCD reset pulse Φ 1 R by one clock period of the first CCD non-inverted clock Φ 1 . More specifically, the second CCD last gate pulse Φ 2 L is previously set at the high level before the time t 58 . The second CCD non-inverted clock Φ 2  is then sequentially switched from the high level to the low level, again to the high level, and then to the low level, while the second CCD inverted clock Φ 2 B is switched from the low level to the high level, again to the low level, and further to the high level. 
         [0091]    At the time t 58 , as shown in  FIG. 9 , the second CCD non-inverted clock Φ 2  is switched from the high level to the low level to allow the electric charges of the first pixel photodiode  20 A to be transferred to the last gate  25  within the second CCD image sensor CCD- 2 . Thereafter, at the time t 60 , the second CCD non-inverted clock Φ 2  switched from the high level to the low level for the second time to transfer the electric charges of the second pixel photodiode  20 B to the last gate  25  within the second CCD image sensor CCD- 2 . This results in the electric charges of the first and second pixel photodiodes  20 A and  20 B are added together at the last gate  25  within the second CCD image sensor CCD- 2 . 
         [0092]    At the time t 59 , the second CCD non-inverted clock Φ 2  is switched from the low level to the high level for the first time. In the meantime, the first switch control signal SW- 2  is pulled up to the high level so that the signal voltage V OUT2  received from the second CCD image sensor CCD- 2  is selected by the switch circuit  11 . This allows externally outputting the field through level voltage (reference level voltage) and pixel signals from the second CCD image sensor CCD- 2 . 
         [0093]    At the time t 60 , the second CCD non-inverted clock Φ 2  is pulled down to the low level for the second time, and the second CCD last gate pulse Φ 2 L is pulled down to the low level at the same time. This allows the electric charges of two pixels stored at the last gate  25  to be collectively transferred to the CFJ  27  within the second CCD image sensor CCD- 2 . The CFJ  27  converts the transferred electric charges into a signal voltage and supplies the signal voltage to the amplifier  28 . The amplifier  28  amplifies the supplied signal voltage to output the signal voltage V OUT2 . 
         [0094]    After the signal detection period of the second CCD image sensor CCD- 2  is completed, the second CCD reset pulse Φ 2 R is pulled up to the high level to initialize the CFJ  27 , and then the second CCD reset pulse Φ 2 R is pulled down to the low level in preparation for the next signal accumulation. 
         [0095]    Similar operations are implemented again for outputting the pixel signals of the third and fourth pixel diodes  20 C and  20 D of the first and second CCD image sensors CCD- 1  and CCD- 2 . 
         [0096]    Specifically, the first CCD last gate pulse Φ 1 L is previously set at the high level before the time t 60 , and the first CCD non-inverted clock Φ 1  is sequentially switched from the high level to the low level, again to the high level, and then to the low level, while the first CCD inverted clock Φ 1 B is switched from the low level to the high level, again to the low level, and then to the high level. When the first CCD non-inverted clock Φ 1  is switched from the high level to the low level at the time t 60 , the electric charges of the third pixel photodiode  20 C is transferred to the last gate  25  within the first CCD image sensor CCD- 1 . When the first CCD non-inverted clock Φ 1  is then switched from the high level to the low level for the second time at the time t 62 , the electric charges of the fourth pixel photodiode  20 D are transferred to the last gate  25  within the first CCD image sensor CCD- 1 . This allows the electric charges of the third and fourth pixel photodiodes  20 C and  20 D to be added together at the last gate  25  within the first CCD image sensor CCD- 1 . 
         [0097]    In the meantime, the first switch control signal SW- 1  is pulled up to the high level at the time t 61 , at which the first CCD non-inverted clock Φ 1  is switched from the low level to the high level, so that the pixel signals of the first CCD image sensor CCD- 1  are selected by the switch circuit  11 . This allows outputting the field through level signal and pixel signals of the first CCD image sensor CCD- 1 . 
         [0098]    When the first CCD non-inverted clock Φ 1  is pulled down to the low level for the second time at the time t 62 , the first CCD last gate pulse Φ 1 L is switched to the low level to allow the electric charges of the third and fourth pixel photodiodes  20 C and  20 D stored in the last gate  25  to be collectively transferred to the CFJ  27  within the first CCD image sensor CCD- 1 . The CFJ  27  converts the electric charges received from the last gate  25  into a signal voltage, and the amplifier  28  amplify the signal voltage to output the signal voltage V OUT1 . 
         [0099]    After the completion of the signal detection period of the first CCD image sensor CCD- 1 , the first CCD reset pulse Φ 1 R is pulled up to the high level to initialize the CFJ  27 , and then the first CCD reset pulse Φ 1 R is pulled down to the low level in preparation for the next signal accumulation. 
         [0100]    This is followed by generating the signal voltage V OUT2  with the electric charges of the third and fourth pixel photodiodes  20 C and  20 D added together within the second CCD image sensor CCD- 2 . In order to avoid the signal voltage V OUT2  overlapping the signal voltage V OUT1  received from the first CCD image sensor CCD- 1 , the activation timings of the second CCD non-inverted clock Φ 2 , the second CCD inverted clock Φ 2 B, the second CCD last gate pulse Φ 2 L, and the second CCD reset pulse Φ 2 R are shifted from the first CCD non-inverted clock Φ 1 , the first CCD inverted clock Φ 1 B, the first CCD last gate pulse Φ 1 L, and the first CCD reset pulse Φ 1 R by one clock cycle of the first CCD non-inverted clock Φ 1 . 
         [0101]    Similar operations to those for the third and fourth pixel photodiodes  20 C and  20 D of the first CCD image sensor CCD- 1  are then implemented for the second CCD image sensor CCD- 2 , whereby the electric charges of the third and fourth pixel photodiodes  20 C and  20 D transferred to the CCD shift registers  24  are added together at the last gate  25 . In the second CCD image sensor CCD- 2 , the electric charges of third and fourth pixel photodiodes  20 C and  20 D stored at the last gate  25  are collectively transfers to the CFJ  27 . The CFJ  27  converts the electric charges transferred thereto into a voltage signal, and the amplifier  28  amplified the voltage signal to output the signal voltage V OUT2  After the completion of the signal detection period of the second CCD image sensor CCD- 2 , the CFJ  27  is initialized in preparation for the next signal accumulation. 
         [0102]    As a result of performing the operation described above, the signal voltage generated by the first CCD image sensor CCD- 1  corresponding to the electric charges of the first and second pixel photodiodes  20 A and  20 B added together is outputted first from the output of the switch circuit  11 , and then the signal voltage generated by the second CCD image sensor CCD- 2  corresponding to the electric charges of the first and second pixel photodiodes  20 A and  20 B added together is outputted. This is followed by outputting the signal voltage generated by the first CCD image sensor CCD- 1  corresponding to the electric charges of the third and fourth pixel photodiodes  20 C and  20 D added together, and then outputting the signal voltage generated by the second CCD image sensor CCD- 2  corresponding to the electric charges of the third and fourth pixel photodiodes  20 C and  20 D added together. The time period required for outputting the signal voltages is half of that conventionally required. Therefore, the time period required for reading the pixel signals from the image sensor array can be reduced by half by forming the image sensor unit  10  of the present embodiment and then performing the operation described above. 
       Second Embodiment  
       [0103]    Hereinafter, a description is then given of an image sensor array of a second embodiment of the present invention. In the second embodiment, an image sensor array is provided with four CCD image sensors and is designed to be adapted to four-pixel addition mode (which results in the reduction of the resolution down to one quarter of the original resolution). 
         [0104]      FIG. 10  is a block diagram showing an exemplary configuration of an image sensor unit  10  of the second embodiment. The image sensor unit  10  is provided with a CCD (Charge Couple Device) image sensor array  2 , a timing generator circuit  3 , and a switch circuit  11 . In the second embodiment, the CCD (Charge Couple Device) image sensor array  2  of the image sensor unit  10  includes first to fourth CCD image sensors CCD- 1 , CCD- 2 , CCD- 3 , and CCD- 4 . The first to fourth CCD image sensors CCD- 1 , CCD- 2 , CCD- 3  and CCD- 4  are structured similarly to that of the CCD image sensor shown in  FIG. 6 , except for that a different number of photodiodes, memories, and shift registers are integrated therein; the first to fourth CCD image sensors CCD- 1 , CCD- 2 , CCD- 3 , and CCD- 4  are each provided with eight photodiodes, eight memories, and eight charge transfer elements. 
         [0105]    The first to fourth CCD image sensors CCD- 1  to CCD- 4  are commonly connected to the timing generator circuit  3  and also commonly connected to the switch circuit  11 . The switch circuit  11  has a function of selecting signal voltages received from the first to fourth CCD image sensors CCD- 1  to CCD- 4  in response to first to fourth switch control signals SW- 1 , SW- 2 , SW- 3 , and SW- 4  supplied from the timing generator circuit  3 . 
         [0106]    The timing generator circuit  3  provides timing controls of the first to fourth CCD image sensors CCD- 1  to CCD- 4 . Specifically, a first transfer gate signal ΦTG 1  is commonly fed to the first to fourth CCD image sensors CCD- 1  to CCD- 4  from the timing generator circuit  3 . In addition, the timing generator circuit  3  feeds first control signals CTL 1  to the first CCD image sensor CCD- 1 , and second control signals CTL 2  to the second CCD image sensor CCD- 2 . Furthermore, the timing generator circuit  3  feeds third control signals CTL 3  to the third CCD image sensor CCD- 3 , and also feeds fourth control signals CTL 4  to fourth second CCD image sensor CCD- 4 . 
         [0107]    In the second embodiment, the first control signals CTL 1  includes a first CCD second transfer gate signal ΦTG 2 - 1 , a first CCD non-inverted clock Φ 1 , a first CCD inverted clock Φ 1 B, a first CCD last gate pulse Φ 1 L, and a first CCD reset pulse Φ 1 R, and the second control signals CTL 2  includes a second CCD second transfer gate signal ΦTG 2 - 2 , a second CCD non-inverted clock Φ 2 , a second CCD inverted clock Φ 2 B, a second CCD last gate pulse Φ 2 L, and a second CCD reset pulse Φ 2 R. Correspondingly, the third control signals CTL 3  includes a third CCD second transfer gate signal ΦTG 2 - 3 , a third CCD non-inverted clock Φ 3 , a third CCD inverted clock Φ 3 B, a third CCD last gate pulse Φ 3 L, and a third CCD reset pulse Φ 3 R. The fourth control signals CTL 4  includes a fourth CCD second transfer gate signal ΦTG 2 - 4 , a fourth CCD non-inverted clock Φ 4 , a fourth CCD inverted clock Φ 4 B, a fourth CCD last gate pulse Φ 4 L, and a fourth CCD reset pulse Φ 4 R. 
         [0108]    The operation of the image sensor array of the second embodiment is similar to that of the first embodiment. 
         [0109]      FIG. 11  is a timing chart illustrating the operation of the image sensor array in the second embodiment. In the second embodiment, electric charges of a series of four pixel photodiodes are added together in the first to fourth CCD image sensors CCD- 1  to CCD- 4 , respectively, and the signal voltages are generated from the electric charges added together in the first to fourth CCD image sensors CCD- 1  to CCD- 4 . In order to achieve this, cycle periods of the first CCD last gate pulse Φ 1 L, the second CCD last gate pulse Φ 2 L, the third CCD last gate pulse Φ 3 L, the fourth CCD last gate pulse Φ 4 L, the first CCD reset pulse Φ 1 R, the second CCD reset pulse Φ 2 R, the third CCD reset pulse Φ 3 R, and the fourth CCD reset pulse Φ 4 R are reduced down to one quarter of those for the normal operation mode. In order to sequentially output the signal voltages, the timing generator circuit  3  sequentially pulls up the first, second, third, and fourth switch control signals SW- 1 , SW- 2 , SW- 3 , and SW- 4 . 
         [0110]    More specifically, after the first to fourth CCD image sensors CCD- 1  to CCD- 4  are allowed to receive light for a certain period of time, the first transfer gate signal ΦTG 1  is pulled up to the high level, and the first transfer gate arrays  21  integrated within the first to fourth CCD image sensors CCD- 1  to CCD- 4  are activated in response to the pull-up of the first transfer gate signal ΦTG 1 . This allows the electric charges accumulated across the pixel photodiodes are transferred to memories integrated with in the first to fourth CCD image sensors CCD- 1  to CCD- 4  through the first transfer gate arrays  21 . After the completion of the charge transfer, the first transfer gate signal ΦTG 1  is pulled down to the low level to deactivate the first transfer gate arrays  21 . 
         [0111]    First, the electric charges stored in the memories are transferred to the CCD shift register  24  in the first CCD image sensor CCD- 1 . More specifically, the first CCD second transfer gate signal ΦTG 2 - 1  is pulled up to the high level to turn on the second transfer gate array  23  within the first CCD image sensor CCD- 1 . This allows transferring the electric charges from the memories to the CCD shift register  24  within the first CCD image sensor CCD- 1 . 
         [0112]    After the charge transfer to the CCD shift register is completed, the first CCD second transfer gate signal ΦTG 2 - 1  is pulled down to the low level to turn off the second transfer gate array  23 . 
         [0113]    This is followed by repeatedly switching the first CCD non-inverted clock Φ 1  and the first CCD inverted clock Φ 1 B from the high level to the low level three times with the first CCD last gate pulse Φ 1 L kept at the high level, to store the electric charges of the leading three pixel photodiodes of the first CCD image sensor CCD- 1  at the last gate  25  of the first CCD image sensor CCD- 1 . At the fourth switching of the first CCD non-inverted clock Φ 1  from the high level to the low level, electric charges of the fourth pixel photodiodes are transferred from the CCD shift register  24  to the last gate  25  within the first CCD image sensor CCD- 1 . Simultaneously, the first CCD last gate pulse Φ 1 L is switched from the high level to the low level. This allows transferring the electric charges of the four pixel photodiodes accumulated at the last gate  25  to the CFJ  27 . A signal voltage V OUT1  is then generated by the first CCD image sensor CCD- 1  so as to correspond the electric charges of the leading four pixel photodiodes added together. In the meantime, the first switch control signal SW- 1  is pulled up to the high level so that the signal voltage V OUT1  which is generated by the first CCD image sensor CCD- 1 , is outputted from the output terminal of the switch circuit  11 . 
         [0114]    Next, the electric charges stored in the memories are transferred to the CCD shift register  24  in the second CCD image sensor CCD- 2 . More specifically, the second CCD second transfer gate signal ΦTG 2 - 2  is pulled up to the high level to turn on the second transfer gate array  23  within the second CCD image sensor CCD- 2 . This allows transferring the electric charges from the memories to the CCD shift register  24  within the second CCD image sensor CCD- 2 . After the charge transfer to the CCD shift register is completed, the second CCD second transfer gate signal ΦTG 2 - 2  is pulled down to the low level to turn off the second transfer gate array  23 . 
         [0115]    This is followed by repeatedly switching the second CCD non-inverted clock Φ 2  and the second CCD inverted clock Φ 2 B from the high level to the low level three times with the second CCD last gate pulse Φ 2 L kept at the high level, to store the electric charges of the leading three pixel photodiodes of the second CCD image sensor CCD- 2  at the last gate  25  of the second CCD image sensor CCD- 2 . At the fourth switching of the first CCD non-inverted clock Φ 2  from the high level to the low level, electric charges of the fourth pixel photodiodes are transferred from the CCD shift register  24  to the last gate  25  within the second CCD image sensor CCD- 2 . Simultaneously, the second CCD last gate pulse Φ 2 L is switched from the high level to the low level. This allows transferring the electric charges of the four pixel photodiodes accumulated at the last gate  25  to the CFJ  27 . A signal voltage V OUT2  is then generated by the second CCD image sensor CCD- 2  so as to correspond the electric charges of the leading four pixel photodiodes added together. In the meantime, the second switch control signal SW- 2  is pulled up to the high level so that the signal voltage V OUT2 , which is generated by the second CCD image sensor CCD- 2 , is outputted from the output terminal of the switch circuit  11 . 
         [0116]    Next, the electric charges stored in the memories are transferred to the CCD shift register  24  in the third CCD image sensor CCD- 3 . More specifically, the third CCD second transfer gate signal ΦTG 2 - 3  is pulled up to the high level to turn on the second transfer gate array  23  within the third CCD image sensor CCD- 3 . This allows transferring the electric charges from the memories to the CCD shift register  24  within the third CCD image sensor CCD- 3 . After the charge transfer to the CCD shift register is completed, the third CCD second transfer gate signal ΦTG 2 - 3  is pulled down to the low level to turn off the second transfer gate array  23 . 
         [0117]    This is followed by repeatedly switching the third CCD non-inverted clock Φ 3  and the third CCD inverted clock Φ 3 B from the high level to the low level three times with the third CCD last gate pulse Φ 3 L kept at the high level, to store the electric charges of the leading three pixel photodiodes of the third CCD image sensor CCD- 3  at the last gate  25  of the third CCD image sensor CCD- 3 . At the fourth switching of the third CCD non-inverted clock Φ 3  from the high level to the low level, electric charges of the fourth pixel photodiodes are transferred from the CCD shift register  24  to the last gate  25  within the third CCD image sensor CCD- 3 . Simultaneously, the third CCD last gate pulse Φ 3 L is switched from the high level to the low level. This allows transferring the electric charges of the four pixel photodiodes accumulated at the last gate  25  to the CFJ  27 . A signal voltage V OUT3  is then generated by the third CCD image sensor CCD- 3  so as to correspond the electric charges of the leading four pixel photodiodes added together. In the meantime, the third switch control signal SW- 3  is pulled up to the high level so that the signal voltage V OUT3 , which is generated by the third CCD image sensor CCD- 3 , is outputted from the output terminal of the switch circuit  11 . 
         [0118]    Next, the electric charges stored in the memories are transferred to the CCD shift register  24  in the fourth CCD image sensor CCD- 4 . More specifically, the fourth CCD second transfer gate signal ΦTG 2 - 4  is pulled up to the high level to turn on the second transfer gate array  23  within the fourth CCD image sensor CCD- 4 . This allows transferring the electric charges from the memories to the CCD shift register  24  within the fourth CCD image sensor CCD- 4 . After the charge transfer to the CCD shift register is completed, the fourth CCD second transfer gate signal ΦTG 2 - 4  is pulled down to the low level to turn off the second transfer gate array  23 . 
         [0119]    This is followed by repeatedly switching the fourth CCD non-inverted clock Φ 4  and the fourth CCD inverted clock Φ 4 B from the high level to the low level three times with the fourth CCD last gate pulse Φ 4 L kept at the high level, to store the electric charges of the leading three pixel photodiodes of the fourth CCD image sensor CCD- 4  at the last gate  25  of the fourth CCD image sensor CCD- 4 . At the fourth switching of the fourth CCD non-inverted clock Φ 4  from the high level to the low level, electric charges of the fourth pixel photodiodes are transferred from the CCD shift register  24  to the last gate  25  within the fourth CCD image sensor CCD- 4 . Simultaneously, the fourth CCD last gate pulse Φ 4 L is switched from the high level to the low level. This allows transferring the electric charges of the four pixel photodiodes accumulated at the last gate  25  to the CFJ  27 . A signal voltage V OUT4  is then generated by the fourth CCD image sensor CCD- 4  so as to correspond the electric charges of the leading four pixel photodiodes added together. In the meantime, the fourth switch control signal SW- 4  is pulled up to the high level so that the signal voltage V OUT4 , which is generated by the fourth CCD image sensor CCD- 4 , is outputted from the output terminal of the switch circuit  11 . 
         [0120]    The above-described operation is repeated once again, since each CCD image sensor incorporates eight photodiodes. More specifically, the operation of generating the signal voltages V OUT1  to V OUT4  corresponding to the electric charges of four pixel photodiodes added together within the first to fourth CCD image sensors CCD- 1  to CCD- 4  is repeated twice, and the first to fourth CCD image sensors CCD- 1  to CCD- 4  are sequentially selected twice in response to the first to fourth switch control signal SW- 1 , SW- 2 , SW- 3 , and SW- 4 . 
         [0121]    The image sensor array in the second embodiment, which incorporates four CCD image sensors connected together, can be operated most efficiently with the speed reduced down to one fourth of that in the normal operation speed, when the signal voltage V OUT1  to V OUT4  are generated from electric charges of four pixel photodiodes added together, that is, when the resolution is reduced down to one quarter of the original resolution. 
         [0122]    Alternatively, the operation may be modified to provide the resolution reduction down to one half of the original resolution in this embodiment. In this case, the signal voltages V OUT1  and V OUT2  of the first and second CCD image sensors CCD- 1  and CCD- 2  are first outputted from the switch circuit  11 , and the signal voltages V OUT3  and V OUT4  of the third and fourth CCD image sensors CCD- 3  and CCD- 4  are then outputted from the switch circuit  11 . In other words, the same operations as that of the first embodiment are implemented twice for each of the set of the first and second CCD image sensors CCD- 1  and CCD- 2  and the set of the third and fourth CCD image sensors CCD- 3  and CCD- 4 . 
         [0123]    It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope of the invention. 
         [0124]    It should be especially noted that the number of CCD image sensors connected together is not limited to two or four as described above; the number of CCD image sensors may be three, six, eight, or other numbers. Moreover, when the number of pixels of the photodiodes is increased, it is preferable to increase the number of applied clock pulses accordingly. 
         [0125]    It should be also noted that the number of pixel photodiodes within each CCD image sensor is not limited to four or eight. Image sensor arrays currently commercially available usually incorporate approximately 10300 photodiodes for reading a sheet of A4 paper (with a short side sized approximately 21 cm) in total, when the resolution is 1200 DPI (dots per inch). This may be achieved by integrating 800 to 1600 photodiodes within each CCD image sensor with six to twelve CCD image sensors within an image sensor array.