Abstract:
A method, apparatus, and system for a custom electronic hardware for iris pattern matching in a mobile device. In one embodiment, a method of a custom hardware solution that includes a change in the CPU clock frequency dependency by using programmable logic and a highly parallel array of high capacity flash memory is shown.

Description:
FIELD OF TECHNOLOGY 
       [0001]    This disclosure relates generally to the field of mobile technology and in one embodiment to a method, apparatus, and system for a custom electronic hardware for iris pattern matching in a mobile device. 
       DISCLOSURE 
       [0002]    An iris recognition algorithm identifies the approximately concentric circular outer boundaries of the iris and the pupil in a photo of an eye from which the iris is rendered in pixel sets. These pixel set or sets are transformed into a bit pattern that may be a means of preserving the data that is essential for a statistically meaningful comparison between two iris images. 
         [0003]    By discarding amplitude information in an algorithm, it is ensured that a biometric template may remain largely unaffected by changes in illumination and virtually negligibly by iris color, which contributes significantly to the long-term stability of the template. Authentication via identification which may be provided by one-to-many template matching or verification which may be provided by one-to-one template matching shows how a template created by imaging the iris is compared to a stored value template in a database. 
         [0004]    Each Iris template is 2048 bits; IR matching speed is the primary factor which is considered especially for a large population, such as a million iris codes enrolled in the UAE central database. 
         [0005]    Iris recognition algorithm is designed to match a new template with one previous enrolled based on the predetermined factional Hamming distance. This continuous exhaustive comparison is conducted by sequentially central processing unit (CPU)-based system. Search speed scales linearly with CPU frequency, hence an Iris database searches may require faster CPUs. These databases are generally stored on hard drives or solid state drives. 
         [0006]    CPUs that have a higher frequency use a lot of power which creates heat in the device. To replicate the same search in a mobile device requires a large battery. The requirement for heat sinking and a large battery adds weight and increases the size of a mobile product. CPUs can only access standard storage devices which may not offer the ideal combination of storage capacity, speed and mechanical robustness. 
         [0007]    In the desk top type PC, the faster CPU requires a cooling fan, heat sink and heat pipe for heat dissipation. In portable, hand-held mobile identification application, some of approaches are not permitted in a rugged environment, such as a cooling fan. The demand for the higher performance may mainly be restricted by the heat dissipation and battery life. 
     
    
     
       BRIEF DESCRIPTION OF FIGURES 
         [0008]    Example embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which: 
           [0009]      FIG. 1  is a high level view of the invention being used in a mobile iris pattern matching application. 
           [0010]      FIG. 2  is a block view which illustrates a hardware block diagram of a pattern matching module (PMM)  100 , according to one embodiment. 
           [0011]      FIG. 3  is a block view which illustrates a pattern matching module  100  incorporated in a complete system, according to one embodiment. 
           [0012]      FIG. 4  is a block view which illustrates the pattern matching process flow. Data is read from a pattern database  201  stored in a NAND flash array, according to one embodiment. 
           [0013]      FIG. 5  is a block view which illustrates the Host system  210  write access to the pattern matching module, according to one embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]    A method, apparatus, and system for a custom electronic hardware for iris pattern matching in a mobile device. Although the present embodiments have been described with reference to specific example embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the various embodiments. In another embodiment the iris pattern matching algorithm may be replaced by another pattern matching algorithm, such as a finger print matching algorithm, or any other pattern matching algorithm. 
         [0015]    What is disclosed here is, a method, apparatus, and system for a custom electronic hardware for iris pattern matching in a mobile device.  FIG. 1  shows an example application  150  where a persons iris is scanned using a mobile device. The mobile device, incorporating a Pattern Matching Module (PMM), compares the scanned iris against an iris pattern database and determines if there is a match. 
         [0016]    (Refer to  FIG. 2 ), which shows a hardware block diagram of a Pattern Matching Module (PMM)  100 . This is the central component of the invention, and performs the pattern matching between a pattern database and a target pattern. The pattern database may be stored in a NAND Flash memory array  112 . The NAND Flash array comprises of two or more NAND flash memory devices arranged so that their data buses are coupled in parallel, via a parallel data bus  110 , to a Programmable Gate Array (PGA)  107 . The pattern database is loaded into the NAND flash memory via the USB interface  109 , USB Controller  102 , parallel data bus  108 , and PGA  107 . The target pattern may be stored in memory inside the PGA  107 , and the target pattern memory is also loaded via the USB  109  interface. NAND flash memory suffers from bit errors, and these must be detected and corrected. The PGA  107  device provides bad block mapping, Error Correcting Code (ECC) generation, ECC error detection and ECC error correction. A SD Flash card  103  may be used to store the NAND flash bad block table. The SD flash card may also be used to store the configuration files required to initialize the PGA  107 . The PGA  107  may access the SD flash  103  via a serial interface  104 . Power for the board may be supplied by the USB interface and may be regulated on board by the voltage regulators  111 . 
         [0017]      FIG. 3  illustrates a pattern matching module  100  incorporated in a complete system. One or more pattern matching modules  100  may be combined in parallel via one or more USB interfaces  403 . If the host system  210  has enough USB interfaces  401  to service all the pattern matching modules, then the host system may be coupled directly. Otherwise a USB hub  402  may be used to couple the pattern matching module to the host system  210 . When multiple PMMs are used in a system the pattern database may be split across PMMs. A search is then performed by loading the same target pattern onto every PMM and requesting each PMM to search its pattern database. 
         [0018]      FIG. 4  illustrates the pattern matching process flow. Data is read from a pattern database  201  stored in a NAND flash array. To avoid reading data from bad blocks in the NAND flash memory, a bad block mapper  202  remaps known bad blocks as identified by the bad block table  203 , which resides in SD Flash memory. Data from the pattern database undergoes ECC correction  204  before being presented to the pattern matching algorithm  205 , where it is compared with a target pattern  206 . A match selector  207  saves the index and score for the pattern in the database which best matches the target pattern. The final results of the search are copied to a register file  208  which may be accessed by the host system  210  via the USB interface  209 . 
         [0019]      FIG. 5  shows the Host system write access to the pattern matching module. The host system  210  may have write access to the pattern database  201 , PGA configuration file  211 , NAND flash bad block table  203 , and target pattern memory  206 . All these memory locations are accessed by the host system  210  via the USB Interface  209  and a FIFO memory  303 . Data written to the pattern database  201  must first have a ECC added to the data by the ECC generation module  305 , and then the data address must be remapped to avoid NAND flash bad blocks. Remapping is performed by the bad block mapping module  202 , which remaps the data according to information in the bad block table  203 .