Abstract:
The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of:
       providing a semiconductor substrate with a main surface; forming a wiring metal layer above said main surface; forming a doped getter layer on said wiring metal layer; and forming at least one additional wiring metal layer on said doped getter layer. The present invention also provides a corresponding integrated semiconductor structure and a semiconductor memory device.

Description:
BACKGROUND 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a manufacturing method for an integrated semiconductor structure and to a corresponding semiconductor structure. 
         [0003]    2. Description of the Related Art 
         [0004]    Although applicable to arbitrary integrated semiconductor structures, the following invention and the underlying problems will be explained with respect to integrated DRAM memory circuits in silicon technology. In particular, DRAM technology which is scaled down to below 100 nm generation provides big challenges. 
         [0005]    Phospho-silicate glass (PSG) is used to getter mobile ions (Li, Na, K) and metal contaminants in semiconductor structures, because these elements which are still present in today&#39;s semiconductor structures deteriorate the electrical functions thereof. 
         [0006]      FIG. 5  shows a schematic layout for illustrating a known manufacturing method for an integrated semiconductor structure according. 
         [0007]    In  FIG. 5  reference sign  1  denotes a semiconductor substrate having a (not shown) integrated circuitry, e.g. a DRAM-circuitry, and having a main surface OS with a non-planar topology. In this particular case, a plurality of gate lines G is arranged in parallel on the main surface OS, said gate lines G having a certain distance from each other and leaving spaces therebetween. Up to now a phospho-silicate glass layer PGL was deposited on such a semiconductor structure with non-planar topology as a getter layer and a planarizing layer. 
         [0008]    However, as indicated with reference sign L in  FIG. 5 , due to the poor gap fill of PSG, in particular in low thermal budget process flows, unwanted voids L are formed in the spaces between the gate lines G. This makes it necessary to look for alternative gap fill materials, such as spin-on dielectrics with exhibit much better gap flow. However, these spin-on dielectrics, e.g. polysilacane based spin-on dielectrica, are usually not phosphorous doped or cannot easily be doped with phosphorous. 
       SUMMARY 
       [0009]    According to one aspect of the invention as claimed in claim  1 , a manufacturing method for an integrated semiconductor structure comprises the steps of: providing a semiconductor substrate with a main surface; forming a wiring metal layer above said main surface; forming a doped getter layer on said wiring metal layer; and forming at least one additional wiring metal layer on said doped getter layer. 
         [0010]    According to another aspect of the present invention as claimed in claim  23 , an integrated semiconductor structure comprises: a semiconductor substrate with a main surface; wiring metal layer formed above said main surface; a doped getter layer formed on said wiring metal layer; and at least one additional wiring metal layer formed on said doped getter layer. 
         [0011]    According to another aspect of the present invention as claimed in claim  39 , a semiconductor memory device comprises: 
         [0012]    a semiconductor substrate having a main surface including a plurality of non-planar gate stacks; a planarization layer for planarizing said gate stacks; a wiring metal layer formed in or on said planarization layer; an interlevel insulating layer formed on said wiring metal layer; a doped getter layer formed on said interlevel insulating layer; and at least one additional wiring metal layer formed on said doped getter layer. 
         [0013]    One advantage of the proposed implementation is that any underlying layer may be chosen without paying attention to gettering effects thus e.g. avoiding planarizing deficites of gettering material layers. 
         [0014]    Preferred embodiments are listed in the respective dependent claims. 
     
    
     
       DESCRIPTION OF THE DRAWINGS 
         [0015]    In the Figures: 
           [0016]      FIG. 1   a )- d ) show schematic layouts for illustrating a manufacturing method for an integrated semiconductor structure according to a first embodiment of the present invention; 
           [0017]      FIG. 2  shows a schematic layout for illustrating a manufacturing method for an integrated semiconductor structure according to a second embodiment of the present invention; 
           [0018]      FIG. 3   a )- c ) show schematic layouts for illustrating a manufacturing method for an integrated semiconductor structure according to a third embodiment of the present invention; 
           [0019]      FIG. 4  shows a schematic layout for illustrating a manufacturing method for an integrated semiconductor structure according to a fourth embodiment of the present invention; and 
           [0020]      FIG. 5  shows a schematic layout for illustrating a known manufacturing method for an integrated semiconductor structure according. 
       
    
    
       [0021]    In the Figures, identical reference signs denote equivalent or functionally equivalent components. 
       DETAILED DESCRIPTION 
       [0022]      FIG. 1   a )- d ) show schematic layouts for illustrating a manufacturing method for an integrated semiconductor structure according to a first embodiment of the present invention. 
         [0023]    In  FIG. 1   a ) reference sign  1  denotes a semiconductor substrate having a (not shown) integrated circuitry, e.g. a DRAM-circuitry, and having a main surface OS with a non-planar topology. In this particular case, a plurality of gate lines G is arranged in parallel on the main surface OS, said gate lines G having a certain distance from each other and leaving spaces therebetween. 
         [0024]    In this first embodiment, a spin-on glass layer SOL is used as a planarization and gap fill layer which exhibits excellent property regarding gap fill and essentially exhibits no unwanted voids. However, this spin-on glass layer SOL does not contain any getter material such as phosphorous. 
         [0025]    On top of the spin-on glass layer SOL, a lowest level wiring metal layer MO is deposited and structured, e.g. a tungsten layer, by masking and etching process steps. 
         [0026]    In a next process step which is shown in  FIG. 1   b ) an LPCVD-oxide base layer BL is deposited on the lowest level wiring metal layer MO and the exposed parts of the spin-on glass layer SOL. Then, an interlevel insulating layer ILD 0  in form of a low-K dielectric layer is deposited on the LPCVD-oxide base layer BL. The interlevel insulating layer ILD 0  forms a planar surface, and after deposition of layer ILD 0 , a phospho-silicate glass getter layer GL is deposited over the entire structure in a gas-phase doping deposition step. 
         [0027]    In a subsequent process step which is shown in  FIG. 1   c ) a (not shown) hard mask, e.g. made of carbon, is formed on top of the structure of  FIG. 1   b ), said hard mask layer having openings at the position of electrical contacts K to be formed at this process state. Then, using the hard mask, contact holes KH are etched which extend through the getter layer GL and the interlevel insulating layer ILD 0  down to regions of the lowest level wiring metal layer MO to be contacted. Subsequently, tungsten is deposited over the entire structure and polished back to the upper surface of the getter layer GL in order to reach the process state shown in  FIG. 1   c ) showing said contacts K in said contact holes KH. 
         [0028]    Then, as shown in  FIG. 1   d ) a second level wiring metal layer M 1  made of TiN is deposited and structured by known processes. Finally, another interlevel insulating layer ILD 1  is deposited over the second level wiring metal layer M 1  which leads to the process state shown in  FIG. 1   d ). 
         [0029]    In the semiconductor structure shown in  FIG. 1   d ), the phospho-silicate glass getter layer GL is arranged above the lowest level wiring layer M 0  and has no longer any influence regarding the gap fill properties arising in connection with the non-planar topology of the underlying semiconductor structure  1 , G. 
         [0030]    Although described here as pure phospho-silicate glass layer, it is of course possible to have a mixed layer such as a boro-phospho-silicate glass layer, typically with a phosphorous content between 0.01%-10% by weight. Even though the mentioned phosphorous content may be advantageous it is only an example and other contents may be possible. 
         [0031]      FIG. 2  shows a schematic layout for illustrating a manufacturing method for an integrated semiconductor structure according to a second embodiment of the present invention. 
         [0032]    According to the second embodiment shown in  FIG. 2 , the process state of which essentially corresponds to the process state shown in  FIG. 1   d ), an adhesive layer AL is deposited on the getter layer GL after formation thereof and before formation of the contacts K. This adhesive layer AL is for example an undoped silane-oxinitride (SiON) layer which also acts as a diffusion barrier against unwanted external ions coming from above. This is beneficial, because the getter layer GL shows the tendency to be saturated after having received a certain amount of foreign ions to be gettered. 
         [0033]      FIG. 3   a )- c ) show schematic layouts for illustrating a manufacturing method for an integrated semiconductor structure according to a third embodiment of the present invention. 
         [0034]    The process state shown in  FIG. 3   a ) corresponds to the process state shown in  FIG. 1   b ), except for the following differences. 
         [0035]    Namely, in this third embodiment, the interlevel insulating layer ILD 0  is a high-density plasma-oxide layer which after deposition shows a non-planar surface. After deposition of this interlevel insulating layer ILD 0 , a getter layer GL′ made of phospho-silicate glass is deposited over the non-planar surface of the interlevel insulating layer ILD 0  and thereafter polished back in chemical-mechanical polishing step, so as to reach the process state shown in  FIG. 3   a ). 
         [0036]    The contact K formation step shown in  FIG. 3   b ) corresponds to the contact K formation step described in connection with  FIG. 1   c ). 
         [0037]    Also, the second level wiring metal layer M 1  formation step shown in  FIG. 3   c ) corresponds to the steps described already with reference to  FIG. 1   d ). 
         [0038]      FIG. 4  shows a schematic layout for illustrating a manufacturing method for an integrated semiconductor structure according to a fourth embodiment of the present invention. 
         [0039]    According to the fourth embodiment, the getter layer GL′ is deposited without any doping on the interlevel insulating layer ILD 0 , e.g. as pure silicate-glass. Thereafter and before formation of the contacts K an ion-implantation step for implanting phosphorous ions into the getter layer GL′ is performed. The parameters of this ion-implantation step are chosen such that a roughening of a surface area of the getter layer GL′ is effected which improves the adhesion to the second level wiring metal layer M 1  and allows omission of the adhesion layer described in connection with the second embodiment shown in  FIG. 2 . 
         [0040]    However, it is possible as well to additionally add said adhesion layer to the embodiment shown in  FIG. 4  which further improves the adhesion of the second level wiring metal layer M 1  and exhibits the aforementioned diffusion barrier function against foreign ions penetrating from above. 
         [0041]    Although the present invention has been described with reference to a preferred embodiment, it is not limited thereto, but can be modified in various manners which are obvious for a person skilled in the art. Thus, it is intended that the present invention is only limited by the scope of the claims attached herewith. 
         [0042]    Although not shown here, the lowest level metal wiring layer M 0  and corresponding interlevel insulating layer ILD 0  can be formed in damascene-level type, i.e. metal and interlevel dielectric extend to the same upper height. 
         [0043]    Such a damascene technique would be performed by forming a insulating layer on said main surface, etching trenches in said insulating layer, depositing said wiring metal layer above said trenched insulating layer, and planarizing said wiring metal layer such that it only remains in said trenches. 
         [0044]    Moreover, said metal layers can be any level metal layers. 
         [0045]    Moreover, if necessary, the getter layer can be annealed immediately after its formation, especially if the getter layer is implanted with phosphorous ions after its deposition. 
         [0046]    Moreover, said interlevel insulating layer ILD 0  could comprise a HDP oxide layer and a TEOS layer deposited thereon. If the underlying structure is non-planar said TEOS layer could be planarized in a planarizing step before the getter layer is deposited thereon.