Abstract:
A circuit, for use in a delay locked loop, provides a phase-shifted output relative to a first signal. The circuit includes plural current sources, current source switches that are selectable to transmit varying amounts of current from the plural current sources, and input switches that receive current via the current source switches and provide the phase-shifted output. The output switches include a first switch for receiving the first signal and a second switch for receiving a second signal phase-shifted from the first signal. The phase-shifted output relative to the first signal is based on an amount of current that passes through each input switch.

Description:
TECHNICAL FIELD 
     This invention relates to delivering a fine delay stage for a delay locked loop (DLL) that incrementally varies the phase shift of input and output voltages. 
     BACKGROUND 
     Double data rate synchronous dynamic random access memory (SDRAM) is available today in new memory integrated circuits that are designed with DLLs. Among their many applications, DLLs perform synchronization in a delay chain having the amount of fixed unit delays changed by a controller which evaluates a phase detector. DLLs have commonly been designed to have a coarse delay stage and fine delay stage where a coarse delay stage is larger than a fine delay stage. Since a coarse delay is process dependent, a coarse delay cannot be made very small to improve the resolution of the DLL, so a fine delay stage is used to improve the resolution. 
     SUMMARY 
     The invention relates to a circuit that produces a fine delay stage for a DLL and a corresponding method that incrementally varies the phase shift of input and output voltages to achieve the fine delay stage. 
     In general, in one aspect, the invention is directed to a fine delay unit circuit, for use in a DLL, that provides a phase-shifted output relative to a first signal. The circuit includes plural current sources, current source switches that are selectable to transmit varying amounts of current from the plural current sources, and input switches that receive current via the current source switches and provide the phase-shifted output. The output switches include a first switch for receiving the first signal and a second switch for receiving a second signal phase-shifted from the first signal. The phase-shifted output relative to the first signal is based on an amount of current that passes through each input switch. 
     This aspect may include one or more of the following features. Each current source may be a constant current source. The plural current sources may include a first current source and a second current source. The second current source may generate twice as much current as the first current source. Each additional current source may generate current 2 N  times greater than the first current source. 
     Each current source may include a first transistor. Each current source switch may include a first transistor and a second transistor. The second transistor may receive a fourth signal that is complementary to a third signal received by the second transistor. The first input switch may include a first transistor and a second transistor. The second input switch may include a third transistor and fourth transistor. The first transistor may receive the first signal and the second transistor may receive a third signal complementary to the first signal. The third transistor may receive the second signal and the fourth transistor may receive a fourth signal complementary to the second signal. 
     In general, in another aspect, the invention is directed to a method that provides a phase-shifted output relative to a first signal in a DLL. The method includes selecting varying amounts of current from plural current sources by enabling current source switches, and transmitting a first signal to a first input switch and a second signal, phase-shifted from the first signal, to a second input switch. Using this method, the phase-shifted output relative to the first signal is based on an amount of current that passes through the first input switch and the second input switch. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic of a circuit for generating fine delay stages in a DLL. 
     FIG. 2 is a schematic showing one embodiment of the circuit of FIG.  1 . 
     FIG. 3A is a graph of the relationship of input signals E and L (FIG. 2) to the circuit of FIG.  2 . 
     FIG. 3B is a graph of the relationship of input signals bE and bL (FIG. 2) to the circuit of FIG.  2 . 
     FIG. 4A is a graph of the phase relationship between input signal E and output signal OUT when signals S 0 -S 3  (FIG. 2) are low. 
     FIG. 4B is a graph of the phase relationship between the input signal E and the output signal OUT when signals S 0 -S 3  are high. 
     FIG. 5A is a graph of the relationship of I E  and I L  in FIG.  4 A. 
     FIG. 5B is a graph of the relationship of I E  and I L  in FIG.  4 B. 
     FIGS. 6 a  and  6   b  are graphs of the relationship of I E  and I L  with respect to the phase delay between E and OUT. 
     FIG. 7 is a graph showing the relationship of the current switches of FIG. 1 to the generation of fine delay steps. 
     FIG. 8A is a general block diagram of a typical DLL 
     FIG. 8B is a general block diagram showing the usage of the fine delay circuit of FIG.  1 . 
    
    
     DETAILED DESCRIPTION 
     Referring to FIG. 1, a fine delay circuit for a DLL is shown. Circuit  10  contains an adjustable current source  15  that provides two output currents, I E  and I L . Adjustable current source  15  contains constant current sources  9 ,  11 ,  13 , and  17 , which produce currents I 1 , I 2 , I 3 , and I 4 , respectively, and current source switches  20 ,  21 ,  22 ,  23 ,  24 ,  25 ,  26 , and  27 . Switches  20 ,  22 ,  24 , and  26  receive signals SO to S 3 . Switches  21 ,  23 ,  25 ,  27  receive signals bS 0 , bS 1 , bS 2 , and bS 3 , which are complementary to signals SO to S 3 . What is meant by complementary is that when one signal is high, its complementary signal is low, and vice versa. 
     Circuit  10  includes input switches  1 ,  2 ,  3 , and  4 . Input switch  1  receives a first input clock signal E, input switch  3  receives a signal bE that is complementary to signal E, input switch  2  receives a second input clock signal L that is phase-shifted from signal E, and input switch  4  receives a signal bL that complementary to signal L. The phase shift between signals E and L is equal to one coarse delay T. Fine delay circuit  10  produces an output voltage OUT that is phase-shifted from signal E. 
     Activating and deactivating current source switches  20 ,  21 ,  22 ,  23 ,  24 ,  25 ,  26 , and  27  changes the phase shift of signal OUT relative to signal E. Coarse delay T is defined as the difference of the minimum phase shift between signal E and signal OUT when current source signals to switches  20 ,  22 ,  24 ,  26  are low (the switches are open) and the current source signals to  21 ,  23 ,  25 , and  27  are high (the switches are closed) and the maximum phase shift between signals E and OUT when current source signal  20 ,  22 ,  24 ,  26  are high (the switches are closed) and current source signals to switches  21 ,  23 ,  25 , and  27  are low (the switches are open). 
     Referring to FIGS. 1 and 2, constant current sources  9 ,  11 ,  13 , and  17  include n-channel transistors  5 ,  6 ,  7 , and  8  respectively. The gate terminals of these transistors are connected to a constant voltage potential, VC. The constant current sources I 1 , I 2 , I 3 , and I 4  are binary weighted. That is, transistor  6  has twice the conductivity of transistor  5 , transistor  7  has twice the conductivity of transistor  6 , and transistor  8  has twice the conductivity of transistor  7 . In other words, if transistor  5  produces current I 1 , then transistor  6  produces a current  2 I 1 , transistor  7  produces a current  4 I 1  and transistor  8  produces a current,  8 I 1 . If additional transistors are added, the additional transistors would produce  2   N I 1  current, if desired. 
     Each constant current source is connected to a pair of current sources switches. Thus, current source I 1  connects to current source switches  20  and  21 , current source I 2  connects to current source switches  22  and  23 , current source I 3  connects to current source switches  24  and  25 , and current source I 4  connects to current source switches  26  and  27 . Each pair of switches is comprised of two transistors. The gates of transistors  31 ,  33 ,  35 , and  37  receive signals S 0 -S 3  and the gates of transistors  32 ,  34 ,  36 , and  38  receive the complementary signals bS 0 -bS 3 . 
     The drain terminals of the constant current source transistors  5 ,  6 ,  7 , and  8  connect to the current source switch at the source of the of n-channel transistors  31 ,  32 ,  33 ,  34 ,  35 ,  36 ,  37 , and  38 . That is, transistor  5  connects to transistor  31  and transistor  32 , transistor  6  connects to transistor  33  and transistor  34 , transistor  7  connects to transistor  35  and transistor  36 , and transistor  8  connects to transistor  37  and transistor  38 . FIGS. 3A and 3B show the relationship of signals E, L, bL, and bE in Circuit  10 . 
     Referring back to FIG. 1, constant current sources  9 ,  11 ,  13 , and  17  and current source switches  20 ,  21 ,  22 ,  23 ,  24 ,  25 ,  26 , and  27  draw two output currents, I E  and I L  (also shown in FIG.  2 ). I E  is the sum of the current that passes through the input switches  1  and  2 . Input switches  1  and  2  are comprised of two n-channel transistors  41  and  43  in FIG.  2 . The gate of transistor  41  receives the input signal E and the gate of transistor  43  receives the input signal bE, which is the complement of signal E. The source of transistors  41  and  43  are connected to the drain of the n-channel transistors  32 ,  34 ,  36 , and  38 . 
     I L  is the sum of the current that passes through input switches  3  and  4 . Input switches  3  and  4  are comprised of two n-channel transistors,  42  and  44  in FIG.  2 . The gate of transistor  42  receives the input signal L and the gate of transistor  44  receives the input signal bL, which is the complement of signal L. The sources of transistors  42  and  44  are connected to the drains of n-channel transistors  31 ,  33 ,  35 , and  37 . The drain terminals of transistor  41  and transistor  42  are connected to a load  61 . The drain terminals of transistor  43  and transistor  44  are connected to a load  62 . Load  61  and load  62  are of equal resistance in this embodiment. The current through each of the loads is equal to I LOAD . 
     Output signal OUT is measured at a node  19  between load  62  and transistors  43  and  44  (FIG.  2 ). Node  19  has a capacitor  52  connected to ground. A complement to output signal OUT, namely output signal OUTB, is measured at a node  18  between load  61  and transistors  41  and  42 . Node  18  has a capacitor  51  connected to ground. As described below, the charging and discharging of capacitor  51  and capacitor  52  is used by fine delay circuit  10  to create fine delay steps. The proper selection of capacitor  51  and capacitor  52  is made to allow for charging and discharging of the capacitors at high frequencies. Capacitor  51  and capacitor  52  may be hidden in the input load of the next gate stage connected to node  18  and node  19 , respectively. In this configuration, fine delay circuit  10  has current I LOAD =I E +I L =I 1 +I 2 +I 3 +I 4 =15I 1 . 
     Referring to FIGS. 4A-4B and  5 A- 5 B, the phase shift between signal E and OUT is adjusted in fine steps by current source switches  20 ,  21 ,  22 ,  23 ,  24 ,  25 ,  26 , and  27 . For example, referring to FIGS. 4A and 5A, when switch signals S 0 -S 3  are at a minimum voltage designated as “0000”, complementary signals bS 0 -bS 3  are at a maximum voltage designated as “1111”. This condition corresponds to current source switches  20 ,  22 ,  24 ,  26  switches being open and current source switches  21 ,  23 ,  25 , and  27  being closed. All of the current generated from constant current sources  9 ,  11 ,  13 , and  17  maximizes current I E  while current I L  is zero. Therefore, I E =I LOAD =15I 1 . This produces a minimum phase shift delay between signal OUT relative to signal E. 
     Referring to FIGS. 4B and 5B when signals S 0 -S 3  are at a maximum voltage (1111), complementary signals bS 0 -bS 3  are zero voltage (0000). All of the current generated from constant current sources I 1 , I 2 , I 3 , and I 4  maximizes the current I L  while current I E  is zero. Therefore, I L =I LOAD =15I 1 . This produces a maximum phase shift delay between OUT relative to E. The difference of the minimum phase delay and the maximum phase delay is equal to coarse delay T. Referring to FIG. 6A and 6B, as I E  moves from a minimum to a maximum value the delay between signals E and OUT decreases linearly. 
     Referring to FIG. 7, the creation of the fifteen fine delay steps can be generated by adjusting signals at S 0 -S 3  from voltages 0000 to 1111. FIG. 7 shows four stages of the sixteen stages. At Rise  1 , the edge is defined by switch settings being set at S 0 -S 3 =0000 and bS 0 -bS 3 =1111. Thus, the current becomes I E =15I 1 , and I L =0. When signal bE goes low at tRE, node  19  is pulled-up through the resistor load resulting in Rise  1  having the fastest edge of the sixteen stages. Even if the signal bL goes low after a delay of one course delay, it will not affect node  19  because current I L  is zero. At Fall  1 , when bE goes high at tFE, node  19  discharges. Since all the current is in I E  the discharge is the fastest of the sixteen stages. 
     At Rise  2  the switches are set as S 0 -S 3 =1010 and bS 0 -bS 3 =0101. The current becomes I E =10I 1  and I L =5I 1 . When signal bE goes low at tRE, the charging of node  19  starts but since signal bL is high for one course delay after bE goes low, the current I L  tries to pull node  19 . Thus, the rising of node  19  is slower until signal bL is high. Once bL goes low at tRL, the node  19  gets charged with the same slope as in the case of rise  1 . 
     At Fall  2 , when the signal bE goes high at tFE the node  19  starts discharging current I E  which is now less than in the case of Rise  1  so that the discharge is slower until signal bL goes high. Once signal bL goes high at tFL, current I L  is added on to the discharge current and the node  19  discharges faster. 
     At Rise  3 , the switches are set as S 0 -S 3 =0101 and bS 0 -bS 3 =1010. The current becomes I E =5I 1  and I L =10I 1 . The function is the same as Rise  2  except that the values of the currents I E  and I L  are different which slows the rate of charging. Likewise, Fall  3  functions the same as Fall  2  except that the change in current slows the rate of discharging. 
     At Rise  4 , the switches are set as S 0 -S 3 =1111 and bS 0 -bS 3 =0000. The current becomes I E =0 and I L =15I 1 . In this case signal bE has no effect because I E =0. The charging of node  19  begins only when signal bL goes low at tRL, which is the slowest rising edge of the sixteen stages. During Fall  4 , the node  19  discharges only when bL goes high at tFL, which is the slowest falling edge of the sixteen falling edges. 
     FIG. 7 also shows the signal OUT 2 , which is the output voltage of an inverter connected to node  19 . The signal OUT (signal at node  19 ) crosses the voltage level VINV at different points in time according to the switch settings. VINV is the input threshold voltage of the inverter when the output of the inverter switches. 
     FIG. 8A shows a block diagram of the typical DLL  40  in a circuit. FIG. 8B shows fine delay circuit  10  incorporated into a DLL block in which an input clock signal CLKIN produces a phase-shifted output clock signal CLKOUT. 
     Other embodiments include varying the amount of fine delay steps, where a fine step is equal to 2 N  and where N equals the number of binary weighted constant current sources. Also, p-channel transistors can be substituted for the n-channel transistors shown in the figures. 
     Other embodiments not described here are also within the scope of the following claims.