Abstract:
A semiconductor structure and a method for forming the same. The semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an electrically insulating region on top of the semiconductor substrate. The semiconductor structure further includes a first semiconductor region on top of and in direct physical contact with the semiconductor substrate. The semiconductor structure further includes a second semiconductor region on top of the insulating region. The semiconductor structure further includes a capacitor in the first semiconductor region and the semiconductor substrate. The semiconductor structure further includes a capacitor electrode contact in the second semiconductor region and the electrically insulating region.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Technical Field 
         [0002]    The present invention relates to semiconductor capacitors, and more specifically, to semiconductor capacitors formed in HOT substrates. 
         [0003]    2. Related Art 
         [0004]    A conventional process for forming a semiconductor capacitor comprises forming two trenches in the substrate: a first trench is for the capacitor itself and a second trench is for providing an electrical contact to the capacitor. Therefore, there is a need for a method for forming the capacitor and its electrical contact in the substrate which is simpler than the method in the prior art. 
       SUMMARY OF THE INVENTION 
       [0005]    The present invention provides a semiconductor structure, comprising (a) a semiconductor substrate; (b) an electrically insulating region on top of the semiconductor substrate; (c) a first semiconductor region on top of and in direct physical contact with the semiconductor substrate; (d) a second semiconductor region on top of the insulating region; (e) a capacitor in the first semiconductor region and the semiconductor substrate; and (f) a capacitor electrode contact in the second semiconductor region and the electrically insulating region. 
         [0006]    The present invention provides a semiconductor fabrication method, comprising providing a semiconductor structure which includes (a) a semiconductor substrate, (b) an electrically insulating region on top of the semiconductor substrate, (c) a first semiconductor region on top of and in direct physical contact with the semiconductor substrate, and (d) a second semiconductor region on top of the insulating region, wherein the first semiconductor region and the second semiconductor region are electrically insulated from each other; forming a first trench, wherein the first trench is formed in the first semiconductor region and the semiconductor substrate; and forming a second trench, wherein the second trench is formed in the second semiconductor region. 
         [0007]    The present invention provides a method for forming the capacitor and its electrical contact in the substrate, which is simpler than the method in the prior art. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]      FIGS. 1-12  illustrate the fabrication of a capacitor and its electrical contact, in accordance with embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0009]      FIGS. 1-12  show cross-section views of a semiconductor structure  100  going through different steps of a fabrication process, in accordance with embodiments of the present invention. With reference to  FIG. 1 , in one embodiment, more specifically, the fabrication process starts with a silicon-on-insulator (SOI) substrate  110 + 120 + 130  including (a) a first silicon layer  110 , (b) a buried insulating layer  120  on top of the first silicon layer  110 , and (c) a second silicon layer  130  on top of the insulating layer  120 . Illustratively, the top layer of the first silicon layer  110  comprises silicon having a lattice orientation of ( 110 ), the top layer of the second silicon layer  130  comprises silicon having a lattice orientation of ( 100 ), and the buried insulating layer  120  is a BOX (Buried Oxide) layer comprising silicon oxide. Note that any other semiconductor materials such as germanium, silicon germanium, silicon carbide, gallium arsenic, gallium nitride, indium phosphoride can be used as the top semiconductor layer  110  and the bottom semiconductor layer  130 . The top semiconductor layer  110  and the bottom semiconductor layer  130  can have the same or different semiconductor materials. 
         [0010]    Next, in one embodiment, a sacrificial pad layer  140  is formed on top of the second silicon layer  130 . Illustratively, the sacrificial pad layer  140  comprises silicon nitride. In one embodiment, the sacrificial pad layer  140  is formed by CVD (Chemical Vapor Deposition). 
         [0011]    Next, in one embodiment, the sacrificial pad layer  140 , the second silicon layer  130 , and the BOX layer  120  are in turn patterned resulting in the semiconductor structure  100  of  FIG. 2 . With reference to  FIG. 2 , after the patterning process, what remain of the sacrificial pad layer  140 , the second silicon layer  130 , and the BOX layer  120  are a sacrificial pad region  140 ′, a second silicon region  130 ′, and a BOX region  120 ′, respectively. Illustratively, the patterning process can involve lithography and then anisotropic etching. 
         [0012]    Next, with reference to  FIG. 3 , in one embodiment, a spacer layer  310  is formed on top of the semiconductor structure  100  of  FIG. 2 . Illustratively, the nitride spacer layer  310  comprises an oxide or nitride formed by (conformal) CVD. In one embodiment, the spacer layer  310  comprises silicon oxide. 
         [0013]    Next, in one embodiment, the nitride spacer layer  310  is anisotropically etched resulting in a nitride spacer  310 ′ of  FIG. 4 . In one embodiment, the anisotropic etching of the nitride spacer layer  310  can be RIE (Reactive Ion Etching). 
         [0014]    Next, with reference to  FIG. 5 , in one embodiment, an epi silicon region  510  is formed by the selective epitaxial growth of silicon on an exposed top surface  111  of the first silicon layer  110  using selective CVD. Because the first silicon layer  110  has the silicon lattice orientation of ( 110 ), the epi silicon region  510  also has silicon lattice orientation of ( 110 ). In one embodiment, a top surface  511  of the epi silicon region  510  is at a higher level than a top surface  141  of the sacrificial pad region  140 ′. 
         [0015]    Next, in one embodiment, the epi silicon region  510  is planarized and recessed resulting in the semiconductor structure  100  of  FIG. 5A . Illustratively, with reference to  FIG. 5A , the planarization processes such as CMP (chemical mechanical polishing) is first performed until the top surface  511  of the epi silicon region  510  is coplanar with a top surface  141  of the sacrificial pad region  140 ′. The recess process such as RIE (reactive ion etching) is then performed until the top surface  511  of the epi silicon region  510  is coplanar with the top surface  131  of the second silicon region  130 ′. 
         [0016]    Next, in one embodiment, the entire sacrificial pad region  140 ′ and a top portion of the spacer  310 ′ are removed resulting in the semiconductor structure  100  of  FIG. 6 . Illustratively, the entire sacrificial pad region  140 ′ and the top portion of the spacer  310 ′ are removed by wet etching. 
         [0017]    Next, with reference to  FIG. 7 , in one embodiment, a pad layer  710  is formed on top of the semiconductor structure  100  of  FIG. 6 . Illustratively, the pad layer  710  comprises silicon nitride. In one embodiment, the pad layer  710  can be formed by CVD. Optionally, an oxide layer (not shown) can be formed on top of the semiconductor structure  100  of  FIG. 6  before the pad layer  710  is formed. 
         [0018]    Next, in one embodiment, a hardmask layer  720  is formed on top of the pad layer  710 . Illustratively, the hardmask layer  720  comprises BSG (Boro-Silicate Glass). In one embodiment, the hardmask layer  720  can be formed by CVD. 
         [0019]    Next, with reference to  FIG. 8 , in one embodiment, first and second trenches  810 a and  810 b are simultaneously formed by photo-lithography (i.e., using a single lithographic mask) and then anisotropic etching process resulting in the semiconductor structure  100  of  FIG. 7 . The first trench  810   a  is deeper than the second trench  810   b  because the etching process for forming the second trench  810   b  is stopped by the BOX region  120 ′. In one embodiment, trenches  810   a  and  810   b  are formed by a RIE (reactive ion etching) process which etches silicon at a much greater rate than the hardmask layer  720  and the BOX layer  120 ′. 
         [0020]    Next, in one embodiment, the hardmask layer  720  is completely removed. Illustratively, the hardmask layer  720  can be removed by wet etching. 
         [0021]    Next, with reference to  FIG. 8A , in one embodiment, a dielectric layer  812  is formed on top of the structure  100  (including on the bottom and side walls of the trenches  810   a  and  810   b ). Illustratively, the dielectric layer  812  is formed by CVD or ALD (atomic layer deposition). In one embodiment, the dielectric layer  812  comprises silicon nitride, silicon oxide, silicon oxynitride, or other dielectric materials such as high-k (high dielectric) materials. 
         [0022]    Next, in one embodiment, the first and second trenches  810   a  and  810   b  are filled resulting in the semiconductor structure  100  of  FIG. 9 . Illustratively, the first and second trenches  810   a  and  810   b  are filled by n-type doped polysilicon regions  814   a  and  814   b,  respectively. Alternatively, any other suitable materials such as metals (tungsten, titanium, copper, etc.) and metallic compounds (tungsten nitride, titanium nitride, tungsten silicide, cobalt silicide, etc) can be used to fill trenches  810   a  and  810   b.  In one embodiment, the first and second trenches  810   a  and  810   b  are filled by CVD or ALD and planarized by CMP. The dielectric layer  812  on top of the pad layer  710  may be consumed during CMP process. Alternatively, the dielectric layer  812  on top of the pad layer  710  can be removed by dry or wet etching process. As can be seen in  FIG. 9 , what remain of the dielectric layer  812  ( FIG. 8A ) are referred to as dielectric layers  812   a  and  812   b.    
         [0023]    Next, in one embodiment, a top portion  814   a ′ of the n-type doped poly silicon region  814   a  and the entire n-type doped poly silicon region  814   b  are removed resulting in the semiconductor structure  100  of  FIG. 9A . Illustratively, the top portion  814   a ′ of the n-type doped poly silicon region  814   a  and the entire n-type doped poly silicon region  814   b  are removed by anisotropic etching. In one embodiment, the anisotropic etching of the top portion  814   a ′ of the n-type doped poly silicon region  814   a  and the entire n-type doped poly silicon region  814   b  is a RIE process. 
         [0024]    Next, with reference to  FIG. 9A , in one embodiment, exposed portions of the first dielectric layer  812   a  and the entire second dielectric layer  812   b  are removed resulting in the semiconductor structure  100  of  FIG. 10 . Illustratively, the exposed portions of the first dielectric layer  812   a  and the entire second dielectric layer  812   b  are removed by wet etching. 
         [0025]    It should be noted that, the removal of the top portion  814   a ′ of the n-type doped poly silicon region  814   a  ( FIG. 9 ), the entire n-type doped poly silicon region  814   b  ( FIG. 9 ), the exposed portions of the first dielectric layer  812   a  and the entire second dielectric layer  812   b  results in two trenches  810   a ′ and  810   b ′ ( FIG. 10 ). 
         [0026]    Next, with reference to  FIG. 11 , in one embodiment, a first collar  813   a  and a second collar  813   b  are formed on side walls of the trenches  810   a ′ and  810   b ′, respectively. Illustratively, the first collar  813   a  and the second collar  813   b  are formed by CVD on the semiconductor structure  100  of  FIG. 10  and followed by an anisotropic etching process such as RIE. In one embodiment, the first collar  813   a  and the second collar  813   b  comprise silicon oxide. In one embodiment, the anisotropic etching step is continued to etch through the BOX region  120 ′ until the top surface  111  of the first silicon layer  110  is exposed to the surrounding ambience via the trench  810   b′.    
         [0027]    Next, in one embodiment, the trenches  810   a ′ and  810   b ′ are filled with a second conducting regions  815   a  and  815   b,  respectively ( FIG. 12 ). In one embodiment, the conducting regions  815   a  and  815   b  comprise n-type doped polysilicon. Illustratively, the polysilicon regions  815   a  and  815   b  are formed in the trenches  810   a ′ and  810   b ′, respectively by (i) depositing polysilicon on top of the semiconductor structure  100  of  FIG. 11  (including inside the trenches  810   a ′ and  810   b ′) by CVD, and (ii) polishing the top surface of the semiconductor structure  100  of  FIG. 11  by CMP resulting in the semiconductor structure  100  of  FIG. 12 . 
         [0028]    As can be seen in  FIG. 12 , the semiconductor structure  100  comprises a capacitor that includes a first polysilicon electrode  814   a + 815   a,  a second electrode  110 , and a capacitor dielectric layer  812   a.  The n-type doped polysilicon region  815   b  provides electrical access to the capacitor electrode  110 . 
         [0029]    While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.