Abstract:
In a circuit having two input stages multiplexed to a common output stage having an output, one of the two input stages including transistor having a base, a collector and an emitter; a method of protecting the transistor from μ-degradation when the one of the two input stages is disabled comprises: clamping the base to a substantially fixed voltage for a first range of voltages applied to the one of the two input stages; and bootstrapping the base to a voltage that follows the output for a second range of voltages applied to the one of the two input stages. Alternatively, a method of protecting a transistor having a base connected through a finite impedance to an input voltage, a collector and an emitter, may comprise bootstrapping the base to a voltage that follows the input voltage with an offset when the input voltage is within a second range of voltages. A circuit having an input voltage connected thereto through a finite impedance may comprise: a transistor having a base, a collector and an emitter; a comparator having a comparator output and having an input connected between the base and the input voltage; a clamping circuit having an output connected to the base and an input connected through a series resistance to a clamping reference voltage; and a bootstrapping circuit responsive to the comparator output, the bootstrapping circuit having an output that injects a variable current into the series resistance, altering the behavior of the clamping circuit from a fixed voltage clamp to a follower.

Description:
BACKGROUND OF INVENTION 
   This application relates generally to circuits for protecting transistors from adverse applied voltages. In particular, the application relates to protection of bipolar transistors from excess reverse V be  voltages, including those resulting in μ-degradation over time. 
   The phenomenon of μ-degradation is a response of a bipolar transistor to a stress. A bipolar transistor is a three-terminal amplifying device, whose terminals are referred to as the base, the collector and the emitter. There are junctions between the materials of which the base and collector are formed and between the materials of which the base and emitter are formed. The amount of gain, i.e. how large is the amplifying factor of the device, is called μ, hence degradation of the gain in response to a stress is called μ-degradation. 
   The phenomenon of μ-degradation occurs when a bipolar transistor is stressed by a reverse V be  voltage in a range between zero volts and the reverse breakdown voltage of the base-emitter junction of the bipolar transistor. When reverse-biased with a voltage between zero and a voltage at which reverse breakdown, i.e., zener breakdown, occurs, a transistor junction will exhibit a small reverse leakage current. This reverse leakage current or reverse conduction causes hot carrier induced oxide damage to the oxide overlying the junction, resulting in μ-degradation and increased noise. Hot carrier induced oxide damage results in electron migration into the oxide, creating undesired additional current paths, reducing breakdown voltage and causing the increase in noise. The range of voltages for which μ-degradation occurs and the range of voltages for which operation is considered to be normal is dependent on the process used to manufacture the bipolar transistor. 
   Although many circuit designs do not produce voltages across the base-emitter junction, V be , that result in μ-degradation, there are other circuits for which this problem will occur during normal circuit operation. One example of such a circuit is the video multiplexer circuit shown in FIG.  1 A. Another example is shown in FIG.  1 B. Although aspects of embodiments of the invention will be described as they apply to the circuit of  FIG. 1A , and both  FIGS. 1A and 1B  are feedback connections, it will be seen that embodiments of aspects of the invention are not so limited. 
   The transconductance multiplexer of  FIG. 1A  includes a first transconductance input amplifier  101  and a second transconductance input amplifier  102  whose outputs are combined at summing junction  103  and converted to an output voltage vo by amplifier  104 . The output voltage vo is fed back to inputs VNA and VNB of input transconductance amplifiers  101  and  102 , respectively. 
   Each input transconductance amplifier  101  and  102  is a differential transistor amplifier. Conventionally, a differential transistor amplifier comprises a differential pair of bipolar transistors, tied at the emitters to a current source, the differential pair steering current through the collectors of the differential pair to one leg or the other of the circuit depending on the differential input voltage. A differential transistor amplifier could also be constructed using other transistor types, such as JFETs, MOSFETs, etc. At the point in time shown, input transconductance amplifier  101  is enabled by current source  105  while input transconductance amplifier  102  is disabled by current source  106 . At other points in time, input transconductance amplifier  101  could be disabled by current source  105  and input transconductance amplifier  102  could be enabled by current source  106 , or both input transconductance amplifiers  101  and  102  could be disabled by their respective current sources  105  and  106 . Because of the feedback connection, which renders the combination of amplifier  104  and enabled input transconductance amplifier  101  a voltage follower, a voltage substantially equal to input voltage va applied to terminal VPA of input transconductance amplifier  101  is produced as the output voltage vo. However, the input to the second input transconductance amplifier  102 , vb, applied to input terminal VPB of disabled input transconductance amplifier  102  is independent of, and may be substantially different from, output voltage vo. 
   A different feedback path is active in the circuit of  FIG. 1B , but the result that the inputs to at least one transconductance amplifier input stage are far apart remains the same. Indeed, in transconductance stages including a differential pair, regardless of what mechanism causes the inputs to be very different, the fact that they are different causes the problem discussed. 
     FIG. 2  is a schematic of one of the amplifiers  101  and  102 . It can be seen from this schematic that the large voltage between the input terminals VPB and VNB of input transconductance amplifier  102  may be large enough to substantially stress the transistors comprising the differential circuit of input transconductance amplifier  102 . For example, if the voltage at VN is brought to a high level, say +1.5 V for example, while the voltage at VP is brought to a low level, say −1.5 V for example, then the 3 V input is distributed across transistors Q 7  and Q 5  in parallel with transistors Q 8  and Q 6 , RD, and transistors Q 3  and Q 1  in parallel with transistors Q 4  and Q 2 , principally as a reverse V be  on transistors Q 7 , Q 6 , Q 3  and Q 2 . 
   SUMMARY OF INVENTION 
   In a circuit having two input stages multiplexed to a common output stage having an output, one of the two input stages including transistor having a base, a collector and an emitter; a method of protecting the transistor from μ-degradation when the one of the two input stages is disabled comprises: clamping the base to a substantially fixed voltage for a first range of voltages applied to the one of the two input stages; and bootstrapping the base to a voltage that follows the output for a second range of voltages applied to the one of the two input stages. The method may further comprise applying a reference voltage through a series resistance to a buffer amplifier having an output connected to the base. The method may yet further comprise injecting a current into the series resistance, the injected current proportional to the voltage applied to the one of the two input stages. The method may even yet further comprise providing the series resistance by simulating a large resistor using an operational transconductance amplifier. Alternatively, the method may further comprise defining the first range of voltages and the fixed voltage so a reverse Vbe of the transistor never exceeds a voltage at which μ-degradation is observable. 
   Alternatively, a method of protecting a transistor having a base connected through a finite impedance to an input voltage, a collector and an emitter, may comprise bootstrapping the base to a voltage that follows the input voltage with an offset when the input voltage is within a second range of voltages. This method may further comprise applying a reference voltage through a series resistance to a buffer amplifier having an output connected to the base. This method may yet further comprise injecting a current into the series resistance, the injected current proportional to the voltage applied to the one of the two input stages. This method may even yet further comprise providing the series resistance by simulating a large resistor using an operational transconductance amplifier. Alternatively, this method may further comprise defining the first range of voltages and the fixed voltage so a reverse V be  of the transistor never exceeds a voltage at which μ-degradation is observable. 
   A circuit having an input voltage connected thereto through a finite impedance may comprise: a transistor having a base, a collector and an emitter; a comparator having a comparator output and having an input connected between the base and the input voltage; a clamping circuit having an output connected to the base and an input connected through a series resistance to a clamping reference voltage; and a bootstrapping circuit responsive to the comparator output, the bootstrapping circuit having an output that injects a variable current into the series resistance, altering the behavior of the clamping circuit from a fixed voltage clamp to a follower. The circuit may further comprise an operational transconductance amplifier connected to provide the series resistance. The circuit may yet further comprise a transconductance amplifier that produces the variable current; and a current mirror operatively connected to mirror the variable current into the series resistance. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
     In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. In the drawings: 
       FIG. 1A  is a block diagram of a switched input transconductance multiplexer, which will be used to illustrate the problem of μ-degradation in a transistor and solutions thereto; 
       FIG. 1B  is a block diagram of another circuit with input transconductance amplifiers illustrating μ-degradation; 
       FIG. 2  is a simplified schematic of the disabled transconductance input stage of  FIG. 1 , in which the μ-degradation problem arises and is solved; 
       FIG. 3  is a functional block diagram of circuits added to the circuit of  FIG. 2  according to some aspects of the invention; 
       FIG. 4  is a functional block diagram of alternative circuits added to the circuit of  FIG. 2  according to some aspects of the invention; 
       FIG. 5  is a circuit block diagram of one embodiment of aspects of the invention; 
       FIG. 6  is a circuit block diagram of another embodiment of aspects of the invention; 
       FIG. 7  is a circuit block diagram of an improvement to the topology of  FIG. 6 ; 
       FIG. 8  is a circuit block diagram of a portion of the circuit of  FIG. 2  with circuits as shown in  FIG. 7  added; 
       FIG. 9  is a graph of generic transfer functions realizable using aspects of embodiments of the invention; 
       FIG. 10  is a circuit block diagram of an improvement to the circuit of  FIG. 8 ; 
       FIG. 11  is a detailed block diagram of the circuit of  FIG. 10 ; 
       FIG. 12  is a more detailed circuit schematic of the circuit of  FIG. 11 ; 
       FIG. 13  is a graph of transfer functions of the clamp/boot strap circuits of  FIGS. 11 and 12 , with break points aligned; and 
       FIG. 14  is a graph of alternative transfer functions of the clamp/boot strap circuits of  FIGS. 11 and 12 , with only one break point in each transfer function. 
   

   DETAILED DESCRIPTION 
   The present invention will be better understood upon reading the following detailed description of various embodiments of aspects thereof, taken in connection with the figures. The particular aspects and embodiments of the invention described relate to the two-input, transconductance multiplexer of  FIG. 1A  described in the background hereof. However, the invention is not limited to that application, as will be understood by those skilled in this art. Any transistor, for example those of the circuit of FIG.  1 B and others, for which μ-degradation may be a problem, used in a circuit for which the methods and circuits described are suitable can be protected by application of appropriate aspects of the invention. The circuits illustrated in  FIGS. 1A and 1B  are non-limiting examples, only. The number of parallel input blocks (e.g.,  FIG. 1A , input amplifiers  101  and  102 ) and the number of gain stages within each input block can be varied, including the use of two or more input blocks and two or more gain stages within each input block. 
   Briefly, with reference to  FIG. 1A , the transconductance multiplexer through which the principles of aspects of embodiments of the invention will be illustrated includes a first transconductance input amplifier  101  and a second transconductance input amplifier  102  whose outputs are combined at summing junction  103  and converted to an output voltage vo by amplifier  104 . The output voltage vo is fed back to inputs VNA and VNB of input transconductance amplifiers  101  and  102 , respectively. 
   Each input transconductance amplifier  101  and  102  is a differential transistor amplifier. Conventionally, a differential transistor amplifier comprises a differential pair of bipolar transistors, tied at the emitters to a current source, the differential pair steering current through the collectors of the differential pair to one leg or the other of the circuit depending on the differential input voltage. A differential transistor amplifier could also be constructed using other transistor types, such as JFETs, MOSFETs, etc. Amplifiers  101  and  102  and their differential pairs are described in further detail, below. At the point in time shown, input transconductance amplifier  101  is enabled by current source  105  while input transconductance amplifier  102  is disabled by current source  106 . At other points in time, input transconductance amplifier  101  could be disabled by current source  105  and input transconductance amplifier  102  could be enabled by current source  106 , or both input transconductance amplifiers  101  and  102  could be disabled by their respective current sources  105  and  106 . Because of the feedback connection, which renders the combination of amplifier  104  and enabled input transconductance amplifier  101  a voltage follower, a voltage substantially equal to input voltage va applied to terminal VPA of input transconductance amplifier  101  is produced as the output voltage vo. However, the input to the second input transconductance amplifier  102 , vb, applied to input terminal VPB of disabled input transconductance amplifier  102  is independent of, and may be substantially different from, output voltage vo. Therefore, the voltage between the input terminals VPB and VNB of input transconductance amplifier  102  may be large enough to substantially stress the transistors comprising the differential circuit of input transconductance amplifier  102 . This will be explained further in connection with FIG.  2 . 
   The input transconductance amplifier illustrated in FIG.  2  and used as a non-limiting example to illustrate aspects of embodiments of the invention may be understood as two differential amplifiers, stacked one on the other. The top differential pair is formed by transistors Q 3  and Q 5 . The bottom differential pair is formed by transistors Q 4  and Q 6 . In the stacked configuration shown, the current sources that ordinarily supply current to the emitters of each differential pair have been set equal to each other. Therefore, they mathematically cancel out, and no current sources are required, or appear, in this portion of the illustrated circuit. 
   Transistor Q 1 , having its collector tied to V EE  and biased by Q 103 , is a follower that level shifts the positive input voltage applied to terminal VP before it is applied to the base of Q 3 , so that the voltage at the emitter of Q 3  tracks the voltage at the positive input VP. Likewise, Q 2 , having its collector tied to V CC  and biased by Q 104 , is a follower that level shifts the voltage at the positive input VP that is applied to the base of Q 4  so that the voltage at the emitter of Q 4  is also made to track the voltage at the positive input terminal VP. Of course, the emitters of Q 3  and Q 4  are tied together at node VPI. A similar arrangement is constructed on the negative input side of the circuit, as follows. The input voltage applied to the negative input terminal VN is level shifted through follower transistors Q 7  and Q 8 , having their collectors tied to V EE  and V CC  and biased by transistors Q 105  and Q 106 , respectively. The resulting, level shifted input is then applied to the bases of transistors Q 5  and Q 6 , respectively. The emitters of Q 5  and Q 6  thus carry a voltage that tracks the voltage at the negative input terminal VN. The difference between the voltage at the positive input terminal VP and the voltage at the negative input terminal VN is thus copied across resistor RD, thereby producing a current through the resistor RD proportional to the differential input voltage. That current is carried to the next stage of the multiplexer through terminals IPU, IPD, IMU and IND, where it shows up as a difference in currents between those terminals. 
   As shown in  FIG. 1A , the voltage at input terminal VN is the output voltage vo, of the multiplexer. Thus, if the amplifier illustrated in  FIG. 2  has been enabled (e.g., it represents input transconductance amplifier  101 , FIG.  1 A), then the voltage applied to input terminal VN ( FIG. 1A , VNA) will closely track the voltage applied to input terminal VP ( FIG. 1A , VPA). Therefore, all of the transistors of the enabled amplifier will be operating in the forward active regime. 
   An input-transconductance stage is considered “disabled” when the input to output DC transfer function of the stage is reduced to essentially zero. Disabling an input stage such as that illustrated in  FIG. 2  may be effected by forcing all stage transistors into the cutoff regime for all allowable voltages at the stage&#39;s input(s). Disabling an input stage by forcing all transistors into the cutoff regime may reverse bias the base-emitter junction of one or more individual devices comprising the stage. Furthermore, individual devices may experience reverse V be  stress for some subset of allowable input voltages. The transconductance stage shown in  FIG. 2  may be disabled by reducing the voltage between the bases of Q 3  and Q 4  and the voltage between the bases of Q 5  and Q 6 , to substantially less than two forward V beS , respectively. Furthermore, the voltages at the bases of transistors Q 3  through Q 6  must be chosen so that transistors Q 3  through Q 6  remain in the cutoff regime. It is desirable to keep transistors Q 1 , Q 2 , Q 7  and Q 8  also operating in the cutoff regime. 
   If the amplifier illustrated in  FIG. 2  is disabled (e.g., it represents input transconductance amplifier  102 ,  FIG. 1A ) then the input voltage applied to terminal VN ( FIG. 1A , VNB) may be any valid input voltage for the circuit, while the input voltage applied to terminal VP ( FIG. 1A , VPB) may be any other valid input voltage for the circuit. The difference between the voltages at terminals VP and VN may be as large as the full range of allowable input voltages, resulting in a substantial reverse base-emitter voltage, referred to herein as a reverse V be , for at least some transistors in most practical circuits. The transistors that will be stressed in this manner may include one or more of transistors Q 1 , Q 2 , Q 3 , Q 4 , Q 5 , Q 6 , Q 7  and Q 8 . Which transistor will see the stressor reverse V be  depends upon the input voltages applied. 
   According to aspects of embodiments of the invention, it is desirable to modulate the voltage appearing on the emitter of one or more of the affected transistors as a function of the voltages applied to one or more of the input nodes. The function should be selected to minimize or eliminate operation in a voltage range causing μ-degradation. Functions that have been tried in the past include a simple clamp and a simple bootstrap. A simple clamp forces the emitter or another terminal of an affected transistor to a fixed voltage. By contrast, a simple bootstrap forces the emitter or another terminal of an affected transistor to track a signal, such as an input signal, to which the terminal is bootstrapped. A simple clamp does not permit a sufficiently wide range of input voltages for those same applications, but a simple bootstrap function permits an unacceptably high degree of cross talk for at least some applications. Thus, neither of these functions is acceptable. 
   The illustrative circuit of  FIG. 2  includes inner, differential pairs of transistors and outer, emitter follower transistors. The circuit could alternatively include chains of plural emitter follower transistors in each location where one outer emitter follower is presently shown. The function applied to one or more of the emitters of the transistors of such a circuit should be selected to distribute the stress of a reverse V be  sufficiently that no transistor of the claims, including the inner transistors suffers μ-degradation. 
   Therefore, as shown in  FIGS. 3 and 4 , according to various aspects of embodiments of the invention, circuits can be added to the transconductance amplifier stage illustrated in  FIG. 2 , to control the voltages at the emitter terminals of transistors Q 1 , Q 2 , Q 7  and Q 8 , corresponding respectively to the base terminals of transistors Q 3 , Q 4 , Q 5  and Q 6 . The functions of input voltage VP, f(VP) and g(VP), prevent significant signal transmission through the input transistors ( FIG. 2 ; Q 1 , Q 2 , Q 3  and Q 4 , for example), while also preventing any of the input transistors ( FIG. 2 ; Q 1 , Q 2 , Q 3 , Q 4 , Q 5 , Q 6 , Q 7 , Q 8 ) from entering an operating region in which μ-degradation or worse can occur. The functions f(VP) and g(VP) can be implemented directly, or can be decomposed into h(VP), f′(h(VP)) and g′(h(VP)), as shown in FIG.  4 . This partition is advantageous for simplifying embodiments of aspects of the invention. 
   We now discuss how the functions illustrated in  FIGS. 3 and 4  are achieved, referring to  FIGS. 5-9 . 
     FIG. 5  shows a circuit embodying aspect of the invention that produces a two-part transfer function, i.e. one having a single breakpoint. Switches S 1  and S 2  should be assumed to be ideal, wherein each switch closes when the gate signal is TRUE and opens when the gate signal is FALSE. 
   Another circuit embodying aspect of the invention, shown in  FIG. 6 , has two comparators  601 ,  602  and three switches S 61 , S 62 , S 63 , arranged in dual breakpoint generator  601  to produce a three-part transfer function, i.e. one having two breakpoints. Switch S 61  is controlled by output φ 1  of comparator  601 , while switch S 63  is controlled by output φ 2  of comparator  602 . Switch S 62  is controlled by a combination (φ 1 ∩φ 2 ). Thus, voltage V x  obeys the following equation: 
         V   x     =     {               V   C1     ⁢     ∀       v   p     ≤     v   b1           ,                   V   C2     ⁢     ∀       v   b1     ≤     v   p     ≤     v   b2           ,           ⁢   and                 V   C3     ⁢     ∀       v   b2     ≤       v   p     .                       
 
   An improvement to the circuit of  FIG. 6  is shown in FIG.  7 . This circuit  701  uses offset voltages v 0S1  and v 0S3  to make inputs V C1  and V C3  proportional to but offset is from v p . In order to reduce crosstalk, V C2  is held constant. V C1  and V C3  are controlled to be proportional to V P  in order to keep transistors Q 1 , Q 2 , Q 3  and Q 4  in a safe operating region. 
   Two copies  701   a ,  701   b  of the circuit  701  and concepts illustrated in  FIG. 7  are used, as shown in  FIG. 8 , one circuit  701   a  to protect the upper transistors ( FIG. 2 , Q 1  and Q 3 ) and one circuit  701   b  to protect the lower transistors ( FIG. 2 , Q 2  and Q 3 ). The resulting transfer functions, in a general form, are shown in FIG.  9 . 
   As shown by the circuit of  FIG. 10 , a simplification can be made wherein the four breakpoints of  FIG. 9  are overlapped into two breakpoints. Only one master function generator circuit  601  is then needed. 
   The topology illustrated in  FIG. 10  is shown in more detail, in connection with a more specific embodiment, in FIG.  11 .  FIG. 11  shows just the positive input half  1101  of the differential transconductance amplifier. As will be understood by the skilled artisan, analogous circuits and principles are applied to the negative input side of the differential transconductance amplifier, if desired and circumstances permit. When the transconductance amplifier is disabled, a protection circuit having two modes is engaged. The protection circuit may receive a voltage V ref  from a reference voltage source, and may include a large effective resistance R large , operational transconductance amplifiers (OTAs)  1102   a ,  1102   b , driven by input V P  through offset voltages V 0S1  and V 0S2 , and controlled by comparators  1103   a ,  1103   b . When engaged in clamping mode, the protection circuit forces the bases of Q 5  and Q 6  to a voltage equal to V ref . The output of the protection circuit can be varied, when in bootstrap mode, through OTAs  1102   a  and  1102   b  selected by enable signals φ 1  and φ 2 . When in clamping mode, signals φ 1  and φ 2  deselect both OTAs, producing a constant, preferably zero, output current. When in bootstrapping mode, OTAs  1102   a  and  1102   b  produce an output current that varies with the input voltage vp. 
   The exemplary protection circuit of  FIG. 11 , shown in detail in  FIG. 12 , is configured to produce a transfer function, as explained in connection with  FIG. 13 , that clamps the bases of Q 3  and Q 4  over a range of input voltages near the center of the potential input voltage range, but which bootstraps the bases of Q 3  and Q 4  outside the center range. Other transfer functions are also possible, as also explained below. The bootstrap function is accomplished by injecting currents into the node carrying the voltage V clamp  to cause it to track the input. As will be seen in the following more detailed description of  FIG. 11 , the functionality of comparators  1103   a  and  1103   b , OTAs  1102   a  and  1102   b  and resistance  1101  can be repartitioned as sense stacks  1201   a  and  1201   b  and merged OTA and large effective resistance (LER)  1202 . 
   During clamping mode, cross-talk is minimized because the clamp prevents the input of the disabled input transconductance amplifier from appearing across the inherent capacitance of transistors Q 3  and Q 4 , which should be in an “off” state. 
   During bootstrap mode, any cross-talk is limited to the excess of the input voltage over the clamping range. Bootstrapping mode extends the protection range to the full range of potential input voltages. 
   The range of input voltages over which clamping mode extends can be centered within the range of permissible input voltages, with bootstrapping mode entered for voltages above the clamping mode range and for voltages below the clamping mode range. Alternatively, the clamping mode range can be offset to one side or another of the range of permissive input voltages, leaving a range of voltages for which bootstrapping mode is entered only on one side of the clamping range. Implementation of the latter design may be simpler than the former. However, the former design allows clamping mode to extend over the largest and most useful portion of the potential input voltage range. 
   The detailed circuit schematic of  FIG. 12  is now described, while also referring back to  FIG. 11 , so that the circuit elements providing the functions of the block diagram of  FIG. 11  can be readily seen. 
   The basic input transconductance amplifier positive input branch  1101  is comprised of transistors Q 1 , Q 2 , Q 3  and Q 4 , as before. Transistors Q 1  and Q 2  are configured as followers. Transistor Q 3  is one-half of a differential pair which together with Q 5  (not shown) forms the top differential pair discussed above. Transistor Q 4  is one-half of a differential pair which together with Q 6  (not shown) forms the bottom differential pair discussed above. Differential pair Q 15  and Q 16  comprise merged OTA/LER  1202 . One input to OTA/LER  1202  is voltage V 2  derived from reference voltage V ref . Two current mirrors modify the output of OTA/LER  1202  depending upon mode, as discussed above. One current mirror is comprised of transistors Q 11  and Q 13 , the other of transistors Q 12  and Q 14 . The current mirror comprised of transistors Q 11  and Q 13  is arranged to increase the current output by OTA/LER  1202  by sourcing additional current into the output node, while the current mirror of transistors Q 12  and Q 14  is arranged to reduce the current output by OTA/LER  1202  by sinking excess current from the output node. The current mirrors are each controlled by a sense stack  1201   a  and  1201   b , respectively. The sense stack  1201   a  controlling current mirror  1203   a , comprised of transistors Q 11  and Q 13  includes input transistor Q 7  biased by transistors Q 9  and D 1 . Similarly, sense stack  1201   b  controlling current mirror  1203   b  is comprised of input transistor Q 8  biased by transistor Q 10  and D 2 . Any other suitable passive or active threshold circuit could be used in place of the sense stacks shown, provided it performs the desired threshold function. For example, under some circumstances, a diode may suffice to provide the threshold function, or a more complex circuit may provide advantageous characteristics. 
   By suitably setting the threshold point for each of the sense stacks, and by selecting the offset voltage suitably, the transfer function of  FIG. 13  can be achieved. Lines  1301  and  1302  indicate the acceptable operational limits of the voltages at V p  and the base of transistor Q 4 . Therefore, allowing an offset  1303  for transistor Q 4  V be , the break points  1304  and  1305  are selected to keep the voltage at the base of Q 4  within acceptable limits. Likewise, lines  1306  and  1307  define the acceptable limits for combinations of voltages V p  and the voltage at the base of transistor Q 3 . Although the range of voltage V p  between the limits may be different between transistors Q 3  and Q 4  because one is a PNP transistor and the other an NPN transistor, the V p  break points  1308  and  1309  of the clamping and bootstrapping transfer function is aligned with V p  for break points  1304  and  1305  so as to simplify the reference voltage and input structures of the two comparator circuits required. As a result, only one reference voltage V RX  is required, and the simple sense stack structure of Q 7 , Q 8 , Q 9 , Q 10 , D 1  and D 2  provide an efficient circuit for controlling the modes as described. 
   In an alternative design, as discussed above, a single break point may be used, as shown in FIG.  14 . The circuit topology to produce this single break point design is substantially the same as that which produces the two break point design discussed above. The transfer function selected may depend on the range of voltages over which protection is desired, the degree of cross-talk permitted, etc. One possible criteria is that clamping mode engage over the most common range of input voltages expected, while the transfer function overall is arranged to be achievable over the entire range of expected input voltages. It should be noted that a transfer function having two break points, such as illustrated in  FIG. 13  is theoretically achievable for one input gain stage over any arbitrary range of input voltages, whereas the transfer function of  FIG. 14  exceeds the acceptable reverse V be  limit for voltages falling in the range  1410 . Therefore, a transfer function as illustrated in  FIG. 14  is only acceptable if the range of input voltages V p  is constrained to be less than voltage  1411 . Even using the transfer function illustrated in  FIG. 13 , a large enough input voltage will cause some stage of the input to break down. Input stages and their protection circuits can be cascaded to widen the range of protected and useful input voltages to any extent required in order to accommodate an anticipated range of input voltages. 
   Having thus described several aspects of at least one embodiment of this invention, it is to be appreciated various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description and drawings are by way of example only.