Abstract:
A packaging substrate and a method for fabricating the same are proposed, including: providing a substrate body having a first surface and an opposing second surface, wherein the first surface has a plurality of flip-chip solder pads and wire bonding pads and the second surface has a plurality of solder ball pads; forming a first and a second solder mask layers on the first and second surfaces respectively and forming openings in the first and second solder mask layers to expose the flip-chip solder pads, the wire bonding pads and the solder ball pads; forming first bumps on the flip-chip solder pads; and forming an electroless Ni/Pd/Au layer on the first bumps and the wire bonding pads by electroless plating, wherein the electroless Ni/Pd/Au layer has a thickness tolerance capable of meeting evenness requirements for fine pitch applications.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates generally to packaging substrates and methods for fabricating the same, and more particularly, to a packaging substrate with a reinforced electrical connection structure and a method for fabricating the same. 
         [0003]    2. Description of Related Art 
         [0004]    Along with the rapid development of electronic industries, electronic products are becoming lighter, thinner, shorter and smaller. There is a trend towards high-performance, high-functionality, and high-speed electronic products. In a conventional semiconductor package structure, an inactive surface of a semiconductor chip is attached to a packaging substrate and an active surface of the semiconductor chip is electrically connected to the packaging substrate through bonding wires. Alternatively, the active surface of the semiconductor chip can be electrically connected to the packaging substrate by flip-chip technique. Further, a plurality of solder balls are mounted on the back side of the packaging substrate so as to electrically connect the semiconductor chip to a printed circuit board. 
         [0005]      FIG. 1  is a sectional view of a conventional packaging substrate, wherein both wire bonding and flip-chip techniques are used for electrically connecting semiconductor chips to the packaging substrate. As shown in  FIG. 1 , first, a substrate body  10  having a first surface  10   a  and an opposing second surface  10   b  is provided, wherein on the first surface  10   a  are a plurality of flip-chip solder pads  101  and wire bonding pads  102 , and the second surface  10   b  has a plurality of solder ball pads  103  thereon. A first solder mask layer  11   a  and a second solder mask layer  11   b  are formed on the first and second surfaces  10   a ,  10   b , respectively. A plurality of first openings  110   a , second openings  111   a  and third openings  110   b  are formed in the first and second solder mask layers  11   a ,  11   b  for exposing the flip-chip solder pads  101 , the wire bonding pads  102  and the solder ball pads  103 , respectively. A surface treatment layer  12  is formed on the wire bonding pads  102  and the solder ball pads  103 . Solder bumps  13  are formed on the flip-chip solder pads  101 . The surface treatment layer  12  is an electroplated or electroless Ni/Au layer, and the solder bumps are made of SnPb, SnAg, SnCu, or SnAgCu. Alternatively, only a surface treatment layer (not shown) made of organic solderability preservative (OSP) coatings, immersion tin (IT) or a solder material is formed on the flip-chip solder pads  101 . 
         [0006]    A first semiconductor chip  14   a  is mounted on the flip-chip solder pads  101  through the solder bumps  13 . The first semiconductor chip  14   a  has an active surface  141   a  and an inactive surface  142   a . A plurality of first electrode pads  143   a  are disposed on the active surface  141   a  and connected to the solder bumps  13  through a plurality of conductive bumps  144  such that the first semiconductor chip  14   a  is flip-chip electrically connected to the substrate body  10 . 
         [0007]    Further, a second semiconductor chip  14   b  is mounted on the first semiconductor chip  14   a  when the inactive surface  142   b  of the second semiconductor chip  14   b  is coupled to the inactive surface  142   a  of the first semiconductor chip  14   a  by a bonding material  15  provided therebetween. A plurality of second electrode pads  143   b  are disposed on an active surface  141   b  of the second semiconductor chip  14   b  and electrically connected to the wire bonding pads  102  by conductive wires  16  made of gold (Au). Further, a molding material  17  is formed to cover the first solder mask layer  11   a , the wire bonding pads  102 , the conductive wires  16 , and the first and second semiconductor chips  14   a ,  14   b  for protection. 
         [0008]    However, owing to the trend towards increasingly compact electronic devices, the pitches between the flip-chip solder pads  101 , the wire bonding pads  102  and the solder ball pads  103  are continuously decreasing. Also, the diameter of the first and third openings  110   a ,  110   b  decreases relatively, and the exposed area of the flip-chip solder pads  101  and the solder ball pads  103  also decreases, thereby resulting in reduced bonding area between the flip-chip solder pads  101  and the solder bumps  13  as well as the solder ball pads  103  and solder balls (not shown). Further, with the flip-chip solder pads  101 , the wire bonding pads  102  and the solder ball pads  103  being generally made of copper, the surface treatment layer  12  and the solder bumps  13  have to meet a lead-free soldering requirements, the surface treatment layer  12  and the solder bumps  13  face the following problems that may adversely affect the electrical connection reliability. 
         [0009]    Firstly, with the surface treatment layer  12  being made of a solder material (SnPb, SnAg, SnCu, SnAgCu), immersion tin or OSP, it is difficult to prevent copper migration that may otherwise cause a short circuit. Further, along with the continuous increase of the thickness of an IMC (intermetallic compound) layer formed at the Sn—Cu interface, the thickness of the flip-chip solder pads  101  and the solder ball pads  103  continuously decreases, thereby adversely affecting the joint reliability. 
         [0010]    Secondly, the surface treatment layer  12  which is an electroplated Ni/Au layer does not have fine-pitch applications for failure to meet evenness requirements for the fine-pitch applications. With the surface treatment layer  12  being formed on the flip-chip solder pads  101  or solder ball pads  103 , the solder bumps  13  or solder balls readily come off the surface treatment layer  12 . With the surface treatment layer  12  being formed on the wire bonding pads  102 , the conductive wires  16  readily come off the surface treatment layer  12 . 
         [0011]    Thirdly, with the surface treatment layer  12  made of electroless Ni/Au being formed on the flip-chip solder pads  101  or the solder ball pads  103 , the solder bumps  13  or solder balls readily come off the surface treatment layer because of the characteristics of Ni. Therefore, the surface treatment layer cannot be applied to hand-held products. If the surface treatment layer is formed on the wire bonding pads  102 , there will be poor attachment between the Au layer and the conductive wires  16  because the Au layer formed by electroless plating is quite thin and structurally weak. 
         [0012]    Fourthly, if the solder bumps  13  are formed by screen printing, a fine pitch cannot be achieved because the average size and height tolerance of the solder bumps  13  cannot be controlled well enough. If the solder bumps  13  are formed on the flip-chip solder pads  101  and the average size or height of the solder bumps  13  is small, an underfill process can be adversely affected. On the other hand, large average size or height of the solder bumps  13  is conducive to providing a solder bridge which is likely to cause a short circuit. In addition, given large height tolerance of the solder bumps  13 , chips can easily be damaged due to uneven joint stresses caused by poor coplanarity. 
         [0013]    Therefore, the semiconductor industry is in dire need of a solution to overcome the above drawbacks. 
       SUMMARY OF THE INVENTION 
       [0014]    To overcome the above drawbacks, an objective of the present invention is to provide a packaging substrate and a method for fabricating the same such that integrated wire bonding and flip-chip packages can meet requirements for fine-pitch applications. 
         [0015]    Another objective of the present invention is to provide a packaging substrate and a method for fabricating the same so as to improve the electrical connection reliability. 
         [0016]    In order to attain the above and other objectives, the present invention provides a packaging substrate, which comprises: a substrate body having a first surface and an opposing second surface, wherein a plurality of flip-chip solder pads and wire bonding pads are provided on the first surface and a plurality of solder ball pads are provided on the second surface, a first solder mask layer and a second solder mask layer are respectively disposed on the first surface and the second surface, the first solder mask layer has a plurality of first openings for exposing the flip-chip solder pads, further has a plurality of second openings for exposing the wire bonding pads and the first surface thereabout, and the second solder mask layer has a plurality of third openings for exposing the solder ball pads, respectively; a plurality of first bumps disposed on the flip-chip solder pads; and an electroless Ni/Pd/Au layer disposed on the first bumps and the wire bonding pads. 
         [0017]    In the above-described packaging substrate, the first bumps are made of copper, and the width of the first bumps is greater than or equal to the diameter of the first openings of the first solder mask layer. Each of the first bumps further has a recess portion. 
         [0018]    The packaging substrate further comprises a first conductive layer disposed between the flip-chip solder pads and the first bumps. The first conductive layer comprises a palladium material, but the first surface exposed from the second openings is free of the residual palladium material. 
         [0019]    In addition, the above-described packaging substrate further comprises a plurality of second bumps made of copper, disposed on the solder ball pads, and covered by the electroless Ni/Pd/Au layer. A second conductive layer is disposed between the second bumps and the solder ball pads, and each of the second bumps has a recess portion. 
         [0020]    The present invention further provides a method for fabricating a packaging substrate. The method comprises the steps of: providing a substrate body having a first surface and an opposing second surface, with a plurality of flip-chip solder pads and wire bonding pads disposed on the first surface, a plurality of solder ball pads disposed on the second surface, and a first solder mask layer and a second solder mask layer disposed on the first surface and the second surface, respectively; forming in the first solder mask layer a plurality of first openings for exposing the flip-chip solder pads and a plurality of second openings for exposing the wire bonding pads and the first surface thereabout, and forming in the second solder mask layer a plurality of third openings for exposing the solder ball pads, respectively; forming a first conductive layer on the first solder mask layer, the flip-chip solder pads, the wire bonding pads and the first surface of the substrate body; forming a first resist layer and a second resist layer on the first conductive layer and the second solder mask layer, respectively, and forming a plurality of first openings in the first resist layer to expose the first conductive layer on the flip-chip solder pads; forming a plurality of first bumps on the first conductive layer in the first openings of the first resist layer by electroplating; removing the second resist layer, the first resist layer, and the first conductive layer covered by the first resist layer; and forming an electroless Ni/Pd/Au layer on the first bumps and the wire bonding pads by electroless plating. 
         [0021]    In the above-described method, the first bumps can be made of copper, and the width of the first bumps is greater than or equal to the diameter of the first openings of the first solder mask layer. Each of the first bumps further has a recess portion. 
         [0022]    The first conductive layer formed comprises a palladium material which functions as a catalyst for metal deposition so as to facilitate the formation of the first conductive layer on the first solder mask layer, the flip-chip solder pads, the wire bonding pads and the first surface of the substrate body. The above-described method further comprises removing the first resist layer and the first conductive layer covered by the first resist layer, and performing a micro-etching process that uses an etching solution containing cyanide (CN) or thiourea ((NH 2 ) 2 CS)) so as to completely remove the palladium material, thereby ensuring the first surface exposed from the second openings of the first solder mask layer to be free of the residual palladium material. 
         [0023]    In addition, in the above-described method, the electroless Ni/Pd/Au layer can be formed on the solder ball pads by electroless plating. Alternatively, a plurality of second bumps made of copper are formed on the solder ball pads by electroplating, and the electroless Ni/Pd/Au layer is formed on the second bumps by electroless plating. Each of the second bumps has a recess portion. 
         [0024]    The fabrication method of the second bumps further comprises: forming a second conductive layer on the second solder mask layer and the solder ball pads; forming a second resist layer on the second conductive layer, and forming second openings in the second resist layer so as to expose the second conductive layer on the solder ball pads; forming the second bumps on the second conductive layer in the second openings of the second resist layer by electroplating; and removing the second resist layer and the second conductive layer covered by the second resist layer. 
         [0025]    Compared with the conventional electroplated Ni/Au layer, the electroless Ni/Pd/Au layer of the present invention is helpful to prevent copper migration so as to prevent a short circuit. Meanwhile, the electroless Ni/Pd/Au layer formed by electroless plating has a thickness tolerance capable of meeting evenness requirements for fine pitch applications. Further, the electroless Ni/Pd/Au layer applied to the flip-chip solder pads or solder ball pads and even the first and second bumps can prevent detachment of solder bumps or solder balls. In addition, the electroless Ni/Pd/Au layer formed on the wire bonding pads can facilitate the wire bonding process. 
         [0026]    Furthermore, instead of using the conventional screen printing, the present invention forms the first bumps by electroplating. Thus, the average size and height tolerance are easy to control so as to overcome the conventional problems of underfilling difficulty, joint bridge and uneven joint stresses caused by poor coplanarity of the bumps. The recess portions of the first bumps further alleviate stresses between the semiconductor chips and the packaging substrate. 
         [0027]    Therefore, the packaging substrate of the present invention improves the electrical connection reliability and makes integrated wire bonding and flip-chip packages capable of meeting requirements for fine pitch applications. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0028]      FIG. 1  is a sectional view of a conventional packaging substrate and semiconductor chips; 
           [0029]      FIGS. 2A to 2E  are sectional views showing a packaging substrate and a method for fabricating the same according to a first embodiment of the present invention, wherein FIG.  2 D′ is a partial enlarged view of  FIG. 2D , and FIG.  2 E″ and FIG.  2 E′ shows other embodiments of  FIG. 2E ; 
           [0030]      FIGS. 3A to 3D  are sectional views showing a packaging substrate and a method for fabricating the same according to a second embodiment of the present invention, wherein FIG.  3 D′ shows another embodiment of  FIG. 3D ; and 
           [0031]      FIG. 4  is a sectional view of a package structure with the packaging substrate and semiconductor chips of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0032]    The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those skilled in the art after reading the disclosure of this specification. 
       First Embodiment 
       [0033]      FIGS. 2A to 2E  are sectional views showing a packaging substrate and a method for fabricating the same according to a first embodiment of the present invention. 
         [0034]    As shown in  FIG. 2A , a substrate body  20  having a first surface  20   a  and an opposing second surface  20   b  is provided. A plurality of flip-chip solder pads  201  and wire bonding pads  202  are formed on the first surface  20   a . A plurality of solder ball pads  203  are formed on the second surface  20   b . A first solder mask layer  21   a  and a second solder mask layer  21   b  are formed on the first surface  20   a  and the second surface  20   b , respectively. A plurality of first openings  210   a  and second openings  211   a  are formed in the first solder mask layer  21   a  so as to allow the flip-chip solder pads  201  to be exposed from the first openings  210   a  and allow the wire bonding pads  202  as well as the first surface  20   a  around the wire bonding pads  202  to be exposed from the second openings  211   a . A plurality of third openings  210   b  are formed in the second solder mask layer  21   b  so as to expose the solder ball pads  203 . 
         [0035]    As shown in  FIG. 2B , a first conductive layer  22   a  is formed on the first solder mask layer  21   a , the flip-chip solder pads  201 , the wire bonding pads  202  and the first surface  20   a  of the substrate body  20 . The first conductive layer  22   a  comprises a palladium material which functions as a catalyst for metal deposition, thereby facilitating the formation of the first conductive layer  22   a  on the first solder mask layer  21   a , the flip-chip solder pads  201 , the wire bonding pads  202  and the first surface  20   a  of the substrate body  20 . 
         [0036]    Next, a first resist layer  23   a  is formed on the first conductive layer  22   a , and a second resist layer  23   b  is formed on the second solder mask layer  21   b . A plurality of first openings  230   a  are formed in the first resist layer  23   a  to expose the first conductive layer  22   a  on the flip-chip solder pads  201  and on the first solder mask layer  21   a  around the flip-chip solder pads  201 . 
         [0037]    As shown in  FIG. 2C , a plurality of first bumps  24   a  made of copper are formed on the first conductive layer  22   a  in the first openings  230   a  of the first resist layer  23   a  by electroplating. 
         [0038]    As shown in  FIG. 2D , the first resist layer  23   a  and the first conductive layer  22   a  covered by the first resist layer  23   a  are removed to expose the first solder mask layer  21   a , the first bumps  24   a , the wire bonding pads  202  and the first surface  20   a  around the wire bonding pads  202 . Meanwhile, the second resist layer  23   b  is removed to expose the second solder mask layer  21   b  and the solder ball pads  203 . 
         [0039]    Further referring to FIG.  2 D′, after the first conductive layer  22   a  covered by the first resist layer  23   a  is removed, the palladium material may be left on the first surface  20   a  around the wire bonding pads  202  in the second openings  211   a  of the first solder mask layer  21   a . Thus, when an electroless Ni/Pd/Au layer is formed on the wire bonding pads  202  in a subsequent process, the electroless Ni/Pd/Au layer is also formed on the first surface  20   a  due to the residual palladium material thereon, thereby resulting in bridging between the wire bonding pads  202  and a short circuit. To overcome the drawback, the residual palladium material on the first surface  20   a  around the wire bonding pads  202  in the second openings  211   a  is completely removed through a micro-etching process that uses an etching solution containing cyanide (CN) or thiourea ((NH 2 ) 2 CS). 
         [0040]    As shown in  FIG. 2E , an electroless Ni/Pd/Au layer  25  (with Au formed outermost) is formed on the first bumps  24   a , the wire bonding pads  202  and the solder ball pads  203  by electroless plating. The width of the first bumps  24   a  is greater than the diameter of the first openings  210   a  of the first solder mask layer  21   a.    
         [0041]    As shown in FIG.  2 E′, each of the first bumps  24   a  has a recess portion  240   a . Alternatively, as shown in FIG.  2 E″, the width of the first bumps  24   a ′ is equal to the diameter of the first openings  210   a  of the first solder mask layer  21   a . Further, an electroless Ni/Pd/Au layer  25  is formed on an exposed surface of the first bumps  24   a ,  24   a ′ of FIGS.  2 E′ and  2 E″. 
         [0042]    The present invention further provides a packaging substrate. As shown in  FIG. 2E , the packaging substrate comprises a substrate body  20  having a first surface  20   a  and an opposing second surface  20   b . A plurality of flip-chip solder pads  201  and wire bonding pads  202  are disposed on the first surface  20   a . A plurality of solder ball pads  203  are disposed on the second surface  20   b . A first solder mask layer  21   a  and a second solder mask layer  21   b  are disposed on the first surface  20   a  and the second surface  20   b , respectively. A plurality of first and second openings  210   a ,  211   a  are disposed in the first solder mask layer  21   a  for exposing the flip-chip solder pads  201  and the wire bonding pads  202 , respectively. A plurality of third openings  210   b  are disposed in the second solder mask layer  21   b  for exposing the solder ball pads  203 . A plurality of first bumps  24   a  are made of copper and disposed on the flip-chip solder pads  201 . An electroless Ni/Pd/Au layer  25  (with Au formed outermost) is disposed on the first bumps  24   a , the wire bonding pads  202  and the solder ball pads  203 . 
         [0043]    The packaging substrate further comprises a first conductive layer  22   a  disposed between the flip-chip solder pads  201  and the first bumps  24   a , wherein the first conductive layer  22   a  comprises a palladium material, but the first surface  20   a  exposed from the second openings  211   a  of the first solder mask layer  21   a  is free of the residual palladium material. 
         [0044]    In addition, the width of the first bumps  24   a  is greater than the diameter of the first openings  210   a  of the first solder mask layer  21   a  (as shown in  FIG. 2E ) or equal to the diameter of the first openings  210   a  (as shown in FIG.  2 E″), and each of the first bumps  24   a  has a recess portion  240   a  (as shown in FIG.  2 E′). 
       Second Embodiment 
       [0045]      FIGS. 3A to 3D  are cross-sectional views of a packaging substrate and a method for fabricating the same according to a second embodiment of the present invention. The second embodiment differs from the first embodiment in that, in the second embodiment, a plurality of second bumps are formed on the solder ball pads. 
         [0046]    As shown in  FIG. 3A , a structure as shown in  FIG. 2A  is provided. Then, a first conductive layer  22   a  is formed on the first solder mask layer  21   a , the flip-chip solder pads  201 , the wire bonding pads  202  and the first surface  20   a  of the substrate body  20 , wherein the first conductive layer  22   a  comprises a palladium material. A first resist layer  23   a  is formed on the first conductive layer  22   a . A plurality of first openings  230   a  are formed in the first resist layer  23   a  to expose the first conductive layer  22   a  on the flip-chip solder pads  201  and around the flip-chip solder pads  201 . A second conductive layer  22   b  is formed on the second solder mask layer  21   b  and the solder ball pads  203 . A second resist layer  23   b  is formed on the second conductive layer  22   b . A plurality of second openings  230   b  are formed in the second resist layer  23   b  to expose the second conductive layer  22   b  on the solder ball pads  203  and around the solder ball pads  203 . 
         [0047]    As shown in  FIG. 3B , a plurality of first bumps  24   a  made of copper are formed on the first conductive layer  22   a  in the first openings  230   a  of the first resist layer  23   a  by electroplating, and a plurality of second bumps  24   b  made of copper are formed on the second conductive layer  22   b  in the second openings  230   a  of the second resist layer  23   b  by electroplating. 
         [0048]    As shown in  FIG. 3C , the first resist layer  23   a  and the first conductive layer  22   a  covered by the first resist layer  23   a  are removed to expose the first solder mask layer  21   a , the first bumps  24   a , the wire bonding pads  202  and the first surface  20   a  around the wire bonding pads  202 . Meanwhile, the second resist layer  23   b  is removed to expose the second solder mask layer  21   b  and the second bumps  24   b . The residual palladium material on the first surface  20   a  around the wire bonding pads  202  in the second openings  211   a  of the first solder mask layer  21   a  is completely removed by a micro-etching process that involves using an etching solution containing cyanide (CN) or thiourea ((NH 2 )  2  CS). 
         [0049]    As shown in  FIG. 3D , an electroless Ni/Pd/Au layer  25  (with Au formed outermost) is formed on the first bumps  24   a , the wire bonding pads  202  and the second bumps  24   b  by electroless plating. As shown in FIG.  3 D′, each of the second bumps  24   b  has a recess portion  240   b.    
         [0050]    The present invention further provides a packaging substrate. As shown in  FIG. 3D , the packaging substrate comprises a substrate body  20  having a first surface  20   a  and an opposing second surface  20   b , wherein a plurality of flip-chip solder pads  201  and wire bonding pads  202  are disposed on the first surface  20   a , and a plurality of solder ball pads  203  are disposed on the second surface  20   b . A first solder mask layer  21   a  and a second solder mask layer  21   b  are disposed on the first surface  20   a  and the second surface  20   b , respectively. A plurality of first and second openings  210   a ,  211   a  are disposed in the first solder mask layer  21   a  for exposing the flip-chip solder pads  201  and the wire bonding pads  202 , respectively. A plurality of third openings  210   b  are disposed in the second solder mask layer  21   b  for exposing the solder ball pads  203 . A plurality of first bumps  24   a  are made of copper and disposed on the flip-chip solder pads  201 . A plurality of second bumps  24   b  are made of copper and disposed on the solder ball pads  203 . An electroless Ni/Pd/Au layer  25  (with Au formed outermost) is disposed on the first bumps  24   a , the wire bonding pads  202  and the second bumps  24   b.    
         [0051]    The packaging substrate further comprises a first conductive layer  22   a  disposed between the flip-chip solder pads  201  and the first bumps  24   a , wherein the first conductive layer  22   a  comprises a palladium material, but the first surface  20   a  exposed from the second openings  211   a  is free of the residual palladium material. The packaging substrate further comprises a second conductive layer  22   b  disposed between the second bumps  24   b  and the solder ball pads  203 . 
         [0052]    In addition, the width of the first bumps  24   a  is greater than the diameter of the first openings  210   a  of the first solder mask layer  21   a  (as shown in FIGS.  3 D and  3 D′) or equal to the diameter of the first openings  210   a  (not shown), and each of the first bumps  24   a  has a recess portion  240   a  (as shown in FIG.  3 D′). Also, the width of second bumps  24   b  is greater than the diameter of the third openings  210   b  (as shown in FIGS.  3 D and  3 D′) or equal to the diameter of the third openings  210   b  (not shown), and each of the second bumps  24   b  has a recess portion  240   b  (as shown in FIG.  3 D′). 
         [0053]    Referring to  FIG. 4 , a first semiconductor chip  25   a  is mounted on the first bumps  24   a  on the flip-chip solder pads  201 , wherein the first semiconductor chip  25   a  has an active surface  251   a  and an opposing inactive surface  252   a . A plurality of first electrode pads  253   a  are disposed on the active surface  251   a . Conductive bumps  254  are disposed on the electrode pads  253   a  such that the first electrode pads  253   a  are connected to the first bumps  24   a  through the conductive bumps  254 , thereby flip-chip electrically connecting the first semiconductor chip  25   a  to the substrate body  20 . 
         [0054]    In addition, a second semiconductor chip  25   b  with an active surface  251   b  and an inactive surface  252   b  is provided. The second semiconductor chip  25   b  is mounted on the first semiconductor chip  25   a  when the inactive surface  252   b  of the second semiconductor chip  25   b  is coupled to the inactive surface  252   a  of the first semiconductor chip  25   a  by a bonding material  26  provided therebetween. A plurality of second electrode pads  253   b  are disposed on the active surface  251   b  of the second semiconductor chip  25   b  and electrically connected to the wire bonding pads  202  through conductive wires  27  made of metal such as gold (Au). A molding material  28  is disposed to cover the first solder mask layer  21   a , the wire bonding pads  202 , the conductive wires  27 , and the first and second semiconductor chips  25   a ,  25   b  for protection. 
         [0055]    According to the present invention, the electroless Ni/Pd/Au layer  25  is helpful to prevent copper migration so as to prevent a short circuit. Further, with the electroless Ni/Pd/Au layer  25  being disposed between copper and tin, a high temperature reflow process produces a uniform IMC layer characterized advantageously by evenness and a low thickness-increasing speed, thereby ensuring a high electrical joint quality. 
         [0056]    Further, compared with the conventional electroplated Ni/Au layer, the electroless Ni/Pd/Au layer  25  formed by electroless plating has a thickness tolerance that meets evenness requirements for fine pitch applications. The electroless Ni/Pd/Au layer  25  applied to the flip-chip solder pads  201  or solder ball pads  203  and even the first bumps  24   a ,  24   a ′ and the second bumps  24   b  prevents detachment of the conductive bumps  254  or solder balls (not shown). In addition, the electroless Ni/Pd/Au layer  25  formed on the wire bonding pads  202  facilitates the wire bonding process. 
         [0057]    Furthermore, instead of using the conventional screen printing, the present invention forms the first bumps  24   a ,  24   a ′ and the second bumps  24   b  by electroplating. Thus, the average size and height tolerance are easy to control so as to overcome the conventional problems of the underfilling difficulty, joint bridge and uneven joint stresses caused by poor coplanarity of the bumps. The recess portions  240   a  of the first bumps  24   a  further alleviate stresses between the semiconductor chips and the packaging substrate. 
         [0058]    Therefore, according to the present invention, the design of the electroless Ni/Pd/Au layer and the first bumps not only improves the electrical connection reliability but also enables integrated wire bonding and flip-chip packages to meet requirements for fine pitch applications. 
         [0059]    The above-described descriptions of the detailed embodiments illustrate the preferred implementation according to the present invention but do not limit the scope of the present invention. Accordingly, all modifications and variations made by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.