Abstract:
A technique for minimizing the area occupied by traces on wireless fixture printed circuit boards of a printed circuit board tester on a per trace basis which ensures meeting maximum trace resistance and/or proper current delivery requirements for tests to be performed using the traces is presented. A printed circuit board implemented in accordance with the invention includes a plurality of conductive pads and a plurality of traces, each of which conductively connects at least two of said conductive pads. At least two of the traces may have differing respective cross-sectional areas predetermined to allow sufficient current to flow therethrough to drive devices connectable to said conductive pads. The cross-sectional area of each trace is calculated based on the minimum sufficient amount of current required to be delivered across the trace, the maximum allowed resistance of the trace, the trace length, and the characteristic resistance of the trace material.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention pertains generally to testing of printed circuit boards, and more particularly to a technique for minimizing the area occupied by traces on wireless fixture printed circuit boards on a per trace basis while also ensuring proper trace resistance requirements for tests to be performed using the traces.  
         BACKGROUND OF THE INVENTION  
         [0002]    Printed circuit assemblies (PCA&#39;s) must be tested after manufacture. Testing of the bare printed circuit board without components and devices attached is performed to test the continuity of the traces between pads on the board. Loaded-board testing is performed after some or all the electrical components and devices have been attached, and is performed to verify that all required electrical connections have been properly completed. Loaded-board testing is also performed to verify that the loaded components perform within specification.  
           [0003]    Printed circuit assemblies testing requires complex tester resources. The tester hardware must be capable of probing conductive pads, vias and traces on the board under test. Loaded-board testing includes analog and digital tests, such as tests for electrical connectivity, voltage, resistance, capacitance, inductance, circuit function, device function, polarity, vector testing, vectorless testing, and circuit functional testing.  
           [0004]    [0004]FIG. 1 illustrates a test system  1 . Test system  1  includes a tester  2 , a fixture  3 , and a device under test (DUT) mount  25 . Tester  2  includes a plurality of test interface pins  9  arranged in an array along the top side of the tester  2 . Tester  2  includes tester hardware  5  which operates under the control of a controller  6 . Controller  6  may be controlled by tester software  7 , which may execute within the tester  2  itself, or remotely via a standard communication interface. One function of the controller  6  is to configure the hardware  5  to make or not make electrical connections between measurement circuits within the tester and each of the test interface pins  9 . To this end, each test interface pin  9  is connectable to or isolated from the tester hardware by a relay  4 . Electrical contact may be made with a respective test interface pin  9  by closing the relay; conversely, the pin  9  may be isolated from the test hardware by opening the relay  4 .  
           [0005]    Mounted on top of the tester and over the tester interface pin  9  field is the test fixture  3 . Fixture  3  comprises a fixture printed circuit board (PCB) adapter  10  and a fixture frame  20 .  
           [0006]    The fixture PCB adapter  10  comprises an adapter top plate  11  and an adapter guide plate  13  which together are supported by sidewalls  12 . Adapter  10  includes a plurality of solid floating probes  14  that are inserted through precisely aligned holes in the guide/plate  13  and top plate  11 . Guide plate  13  ensures precise vertical alignment of solid floating probes  14 .  
           [0007]    In the embodiment shown, the adapter  10  also includes a probe field shrinking printed circuit board (PCB)  15  which is used to translate the relatively larger test interface pin  9  field of the tester  2  to a relatively smaller probe field of the printed circuit board under test. In particular, in this embodiment, the probe field shrinking PCB  15  comprises a plurality of pins  17  that connect on one end to the top tips of certain test interface pins  9  of the tester and on the other end to conductive traces on the probe field shrinking PCB  15  which route to conductive pads on the top side of the probe field shrinking PCB  15 . The adapter includes a plurality of single-ended spring probes  16  whose bottom tips electrically contact the conductive pads on the top side of the probe field shrinking PCB  15 . The single-ended spring probes  16  are also inserted through precisely aligned holes in the guide/plate  13  and top plate  11 .  
           [0008]    The fixture PCB adapter  10  is mounted over the test interface pin  9  field such that the bottom tips of the solid floating probes  14  and the bottom tips of the probe field shrinking PCB pins  17  align with and make electrical contact with the top tips of corresponding test interface pins  9  of the tester  2 , as shown.  
           [0009]    A fixture printed circuit board (PCB)  8  is mounted on the top plate  11  of the adapter  10  such that the top tips of the solid floating probes  14  and the top tips of the single-ended spring probes  16  align with and make electrical contact with conductive pads on the bottom side of the fixture PCB  8 . The conductive pads on the bottom side of the fixture PCB  8  electrically connect to conductive pads on the top side of the fixture PCB  8  by traces and vias, and possibly through several intervening conductive layers of the PCB  8 .  
           [0010]    The fixture frame  20  includes a top plate  21  and a guide plate  23  supported by sidewalls  22 , and an alignment plate  24 . Fixture  10  includes a plurality of double-ended spring probes  18  that are inserted through precisely aligned holes in the top plate  21 , guide/plate  23  and alignment plate  24 . Plastic standoffs  19   a  and/or retainer screws  19   b  respectively keep the adapter pins from pushing the fixture PCB  4  up and prevents the fixture PCB  4  from bowing when the assembly is vacuum compressed during test of a PBC under test  26 .  
           [0011]    Frame  20  is mounted over the fixture adapter  10 , precisely aligning the bottom tips of the double-ended spring probes  18  onto conductive pads on the top of the fixture PCB  8  to ensure electrical contact.  
           [0012]    The DUT mount  25  includes a support plate  28  mounted on the top side of the frame top plate  21  by foam or spring gaskets  29   b . Foam or spring gaskets  29   a  are also mounted on the top side of the support plate  28  to allow a DUT  26  such as a printed circuit board to be mounted thereon. The printed circuit board  26  may be loaded, including one or more electrical components  27  attached thereto, or may be a bare board.  
           [0013]    When a DUT  26  is to be tested, the tester interface pins  9  press on the fixture PCB  8  upward at its bottom conductive pads (indirectly through the fixture adapter  10 ). Simultaneously, the bottom tips of the double-ended probes  18  press against the fixture PCB  8  downward against its top conductive pads. The top tips of the double-ended probes  18  press against the bottom conductive pads of the DUT  26 . During test of the DUT  26 , the test software  7  directs the controller  6  to configure the tester hardware  5  to make connections between certain tester interface pins  9  of interest to measurement circuits within the tester hardware  5 . The tester hardware  5  may then make measurements of the device or pad under test according to software instruction.  
           [0014]    The present invention is concerned with the fixture printed circuit board (PCB)  8 . The quality of signals routed on the fixture PCB  8  is affected by probe and pin contact against the conductive pads on opposing sides of the board  8 , as well as by the characteristic resistance of the PCB traces.  
           [0015]    When making analog measurements, the concern with the traces is in fact the characteristic resistance of each of the traces used in the measurements of the analog components. The effect of the resistance of the trace on the error of the actual measured resistance value of an analog component under test depends on the proportional values of the trace resistance and expected resistance value of the component under test. If the trace resistance is relatively large in proportion to the expected resistance value of the component under test, the measurement error will be large. Conversely, if the trace resistance is relatively small in proportion to the expected resistance value of the component under test, the measurement error will be small. For example, if the trace resistance is 2 Ohms added on to each end of the component under test whose expected resistance value is 10 ohms, the measurement error will be very large in proportion to the actual measured value. If, however, the same trace resistance of 2 Ohms is added on to each end of a component under test whose expected value is 10 KOhms, the measurement error will be insignificant in proportion to the actual measured value.  
           [0016]    One solution to the problem of a trace having a high proportional resistance with respect to the expected measured resistance is to increase the cross-sectional area of the trace to ensure sufficient current delivery to the component under test.  
           [0017]    In contrast to testing analog components mounted on a printed circuit board under test, which generally are characterized by very low current delivery requirements, when the component under test is a power supply, the current delivery requirements are generally significantly higher (e.g., on the order of 1 to 10 Amps). In this case, the parameter of concern is not generally the trace resistance, but rather the amount of current capability of the trace versus the voltage drop between the measurement circuit and power supply under test. Again, one solution to ensuring sufficient current delivery requirements on the testing trace is to ensure sufficiently large cross-sectional area of the traces testing the power supply.  
           [0018]    When testing digital components, the series resistance is the parameter of concern. Generally, a minimum current (e.g., on the order of tenths of an Amp) with a maximum acceptable voltage loss between the measurement circuit and the digital component under test (e.g., on the order of tenths of a Volt) are required to perform the test. These parameters dictate the maximum resistance allowable for traces testing the digital component under test. With digital over-drive testing, the minimum current is much higher (e.g., on the order of 0.75 Amps), but the maximum acceptable voltage loss between the measurement circuit and the digital component under test remains the same. Again, a maximum allowable resistance requirement is thus placed on the testing trace.  
           [0019]    In each type of the above-mentioned testing, the trace resistance and/or current delivery requirements of the testing trace may be ensured by using traces of sufficient cross-sectional area. However, increasing the cross-sectional area of the fixture traces increases the area occupied by the traces on the fixture PCB. This in turn can lead to requirements for additional PCB layers, adding cost and complexity to the fixture PCB. Layer count may be reduced by minimizing the area occupied by the traces and their vias.  
           [0020]    Accordingly, a need exists for a technique for minimizing the area occupied by traces and vias of a fixture PCB without adversely affecting the quality of the signals thereon.  
         SUMMARY OF THE INVENTION  
         [0021]    The present invention is a method for automatically minimizing the area occupied by the traces of a test fixture printed circuit board on a per trace basis which ensures proper current delivery requirements for tests to be performed using the traces. A printed circuit board implemented in accordance with the invention includes a plurality of conductive pads and a plurality of traces. Each trace conductively connects at least two conductive pads of the test fixture printed circuit board. At least two of the traces have differing respective cross-sectional areas predetermined to have a maximum trace resistance and/or allow sufficient current to flow therethrough to test devices connectable to the conductive pads. The cross-sectional area of each trace is calculated based on the minimum sufficient amount of current required to be delivered through the trace, the maximum allowed resistance of the trace, the trace length, and the characteristic resistance of the trace material. In particular, in one embodiment, given a fixed trace thickness, the minimum sufficient width of each trace of the fixture PCB is calculated based on the trace resistivity requirements or current delivery requirements of the trace for tests to be performed using the trace. By adaptively applying the minimum sufficient width required for each trace on a per trace basis, tests are guaranteed sufficient current delivery for proper testing performance, while allowing the total trace area to be minimized in order to minimize the PCB layer count and cost. Note that the required width is often a function of trace length. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWING  
       [0022]    The invention will be better understood from a reading of the following detailed description taken in conjunction with the drawing in which like reference designators are used to designate like elements, and in which:  
         [0023]    [0023]FIG. 1 is a block diagram of a printed circuit board test system;  
         [0024]    [0024]FIG. 2A is a bottom view of a portion of a fixture printed circuit board implemented in accordance with the invention;  
         [0025]    [0025]FIG. 2B is a top view of the portion of the fixture printed circuit board of FIG. 2A;  
         [0026]    [0026]FIG. 2C is a transparent top view of the fixture printed circuit board of FIGS. 2A and 2B, illustrating the path of the traces on each conductive layer;  
         [0027]    [0027]FIG. 3 is a block diagram of a system for calculating the minimum sufficient trace widths for each net in a fixture PCB implemented according to the invention;  
         [0028]    [0028]FIG. 4 is an operational flowchart illustrating the method of the invention;  
         [0029]    [0029]FIG. 5A is a block diagram view of a printed circuit board test system implemented in accordance with the invention;  
         [0030]    [0030]FIG. 5B is a bottom view of a portion of the fixture printed circuit board shown in FIG. 5A implemented in accordance with the invention;  
         [0031]    [0031]FIG. 5C is a top view of the portion of the fixture printed circuit board of FIG. 5B;  
         [0032]    [0032]FIG. 5D is a transparent top view of the fixture printed circuit board of FIGS. 5B and 5C, illustrating the path of the traces on each conductive layer;  
         [0033]    [0033]FIG. 6A is a schematic block diagram of a simple analog test apparatus used to derive the equations for calculating the minimum sufficient trace cross-sectional area for a trace used to perform an analog test;  
         [0034]    [0034]FIG. 6B is a schematic block diagram of the analog test apparatus of FIG. 6A illustrating the problem of parallel parasitic impedance;  
         [0035]    [0035]FIG. 6C is a schematic block diagram of the analog test apparatus of FIG. 6A illustrating a guarding technique;  
         [0036]    [0036]FIG. 7 is a flowchart illustrating a method  120  for calculating the minimum sufficient trace width of a net used to perform an analog test;  
         [0037]    [0037]FIG. 8A is a portion of an example test specification file illustrating the format of the file;  
         [0038]    [0038]FIG. 8B is a portion of an example test specification file;  
         [0039]    [0039]FIG. 8C is a portion of an example output file generated by the minimizing trace calculator of the invention illustrating the format of the file; and  
         [0040]    [0040]FIG. 8D is a portion of an example output file generated by the minimizing trace calculator of the invention;  
         [0041]    [0041]FIG. 9A is a view of a portion of the first conductive layer of a printed circuit board implemented in accordance with a second embodiment of the invention;  
         [0042]    [0042]FIG. 9B is a view of a portion of the second conductive layer of the printed circuit board of FIG. 9A according to the second embodiment of the invention;  
         [0043]    [0043]FIG. 9C is a view of a portion of the third conductive layer of the printed circuit board of FIGS. 9A and 9B according to the second embodiment of the invention; and  
         [0044]    [0044]FIG. 9D is a transparent top view of the fixture printed circuit board of FIGS. 9A, 9B and  9 C, illustrating the path of the traces on each conductive layer  
     
    
     DETAILED DESCRIPTION  
       [0045]    A novel method for automatically minimizing the area occupied by the traces of the fixture PCB on a per trace basis is described in detail hereinafter. Although the invention is described in terms of specific illustrative embodiments, it is to be understood that the embodiments described herein are by way of example only and that the scope of the invention is not intended to be limited thereby.  
         [0046]    Turning now to the invention, FIGS. 2A, 2B, and  2 C illustrate a fixture PCB  30  implemented in accordance with the principles of the invention. As shown therein, the fixture PCB  30  includes a plurality of conductive traces  34   a - 34   d  connecting between conductive pads  32   a - 32   d  and vias  36   a - 36   d  on a first side  30   a  of the board  30 , which connect to conductive pads  38   a - 38   d  on the opposite side  30   b  of the fixture PCB  30 . As shown, the traces  34   a - 34   d  vary in width w a -w d  in order to allow the minimum sufficient width of the trace while meeting maximum trace resistance requirements and/or still ensuring sufficient current delivery to support accurate testing.  
         [0047]    In particular, FIG. 2A shows the bottom side view of the portion of the PCB  30 . In this example, the bottom side  30   a  of the PCB  30  comprises a conductive pad  32   a  conductively connected by a conductive trace  34   a  defined by a first width w a  to a via  36   a . The bottom side  30   a  of the PCB  30  comprises a conductive pad  32   b  conductively connected by a conductive trace  34   b  defined by a second different width w b  to a via  36   b , a conductive pad  32   c  conductively connected between a conductive trace  34   c  defined by a third different width w c  to a via  36   c , and a conductive pad  32   d  conductively connected by a conductive trace  34   d  defined by a fourth different width w d  to a via  36   d.    
         [0048]    [0048]FIG. 2B shows the top view of the portion of the PCB  30  of FIG. 2C. In this example, the vias  36   a - 36   d  each connect through an intervening dielectric layer of the board  30  to the top  30   b  of the PCB  30 . The top  30   b  of the PCB  30  therefore comprises conductive via  36   a  from the bottom  30   a  of the PCB  30  conductively connected to a conductive pad  38   a  by the continuation of the conductive trace  34   a  defined by first width w a . The top  30   b  of the PCB  30  also comprises conductive via  36   b  from the bottom  30   a  of the PCB  30  conductively connected to a conductive pad  38   b  by the continuation of the conductive trace  34   b  defined by width w b , conductive via  36   c  from the top side  30   a  of the PCB  30  conductively connected to a conductive pad  38   c  by the continuation of the conductive trace  34   c  defined by width w c , and conductive via  36   d  from the top side  30   a  of the PCB  30  conductively connected to a conductive pad  38   d  by the continuation of the conductive trace  34   d  defined by width w d.    
         [0049]    [0049]FIG. 2C is a transparent top view of the PCB  30  of FIGS. 2A and 2B, illustrating the path of the traces on each conductive layer  30   a ,  30   b.    
         [0050]    As illustrated, each of conductive traces  34   a ,  34   b ,  34   c ,  34   d  have different widths w a , w b , w c , w d , which are calculated according to the principles of the invention to have a substantially minimum sufficient width to meet maximum trace resistance requirements and/or deliver sufficient current to devices under test for proper performance of tests performed on the devices under test using each trace.  
         [0051]    For simplicity, the illustrative example of the fixture PCB  30  of FIGS. 2A, 2B, and  2 C assumes only two conductive routing layers (namely, the bottom exposed conductive layer  30   a  and the top exposed conductive layer  30   b . However, it will be appreciated by those skilled in the art that the fixture PCB may include any number of intervening conductive layers through which signals may be routed between the bottom and top exposed layers  30   a  and  30   b.    
         [0052]    [0052]FIG. 3 is a block diagram of a system  40  for determining the minimum sufficient trace width for each net of a fixture PCB on a per net basis. As shown, the system  40  includes test generator software  42  which receives a board description  41  of the physical locations, parameters, and characteristics of each of the devices pads, and nets on the board under test. Given the board description  41 , the test generator software  42  determines a set of tests to be executed and a set of nets on the wireless test fixture printed circuit board that will be used to perform the tests, and generates a set of test specifications  43 . Among other test setup parameters, the test specifications  43  include the current requirements for performing the test and/or the maximum resistance of each trace used in performing the tests. A trace minimizing calculator  44  calculates the cross-sectional area or width and/or thickness of each trace based on the maximum resistance and/or current delivery requirements of the trace so as to minimize the area that the trace occupies on the printed circuit board. In the illustrative embodiment, the length of the trace is predefined, and the thickness of the trace is fixed; accordingly, the trace minimizing calculator  44  calculates the substantially minimum trace width for each trace that still ensures sufficient current delivery across the trace to perform the tests associated with the net.  
         [0053]    In order to determine the minimum sufficient width for a given trace, all of the devices that are stimulated for test by the trace must be considered. These devices may require various types of tests, such as digital-only tests, analog-only tests, or both types of tests, which require different amounts of current. In addition, some digital tests of certain devices require “over-driving” of other devices in their proximity, and hence sufficient current must also be delivered to these other devices.  
         [0054]    [0054]FIG. 4 depicts a method for determining the minimum sufficient trace width for each net of a wireless fixture PCB on a per net basis in accordance with the invention. As shown, for each net on the fixture PCB, the minimum sufficient trace width of the net is calculated for each possible test that will be executed using the trace. The widest of the calculated minimum sufficient trace widths is selected as the trace width in order to ensure sufficient current for each test. In particular, method  100  begins by selecting a first net  101 / 102 . The method determines whether an analog test is to be performed  103 , and if so, calculates  104  a minimum trace width required to provide sufficient current on the selected net to perform the analog test. The method then optionally determines whether a digital test is to be performed  105 , and if so, calculates  106  a minimum trace width required to provide sufficient current on the selected net to perform the digital test. The method then optionally determines whether an overdrive test is to be performed  107 , and if so, calculates  108  a minimum trace width required to provide sufficient current on the selected net to perform the overdrive test. Once all minimum trace widths are calculated for each test to be performed using the trace, the widest of the calculated minimum trace widths for the selected net is selected  109  as the trace width for the selected net. Steps  101 - 109  are repeated for each remaining unprocessed net.  
         [0055]    [0055]FIG. 5A is a block diagram view of a test system  200  implemented in accordance with the invention. As shown, the test system  200  is set up to be connected to test a resistor  201  on a board under test  211 . The board under test  211  is mounted on a test fixture  214 , including a fixture printed circuit board  215 . The tester hardware includes a pin card  212  and measurement hardware  250  comprising stimulus sources  252 , a measuring operational amplifier (MOA) circuit  254 , and response detectors  256 . A controller  260  manages each in-circuit test by closing the proper testhead relays  213   a ,  213   b  to connect the device under test  201  to the MOA circuit  254 . The measurement hardware  250  includes a stimulus source  252 , which may be configured to connect a current source, voltage source, AC or DC source as the source input to the MOA circuit  254 . The measurement hardware  250  also includes a response detector circuit  256  which may be configured to detect analog or digital signals. As the stimulus source  252  is applied to the MOA circuit  254 , the response detector  256  measures the output of the MOA circuit  254  and sends the results to the controller  260  for evaluation. Depending on the results, the controller  260  sends either a pass or fail condition back to the test program.  
         [0056]    [0056]FIG. 6A is a schematic block diagram of a simple analog test apparatus  50  implementing the MOA circuit  254  of the measurement hardware  250 . The analog test apparatus  50  determines the resistance value R X  of the tested analog device  52  (e.g., resistor, capacitor, inductor, diode, transistor, fuse, potentiometer, etc.) by using a reference device  57  having a known resistance value R REF  and measured source and detector voltages V S    51  and V O    56 . As illustrated, the analog test apparatus  50  includes an operational amplifier  55  having a positive input  54  connected to a circuit ground, a negative input  53  connected between the output of the device under test  52  and one end of a known reference feedback resistance R REF    57 , and an output V O  taken on an output line  56  and connected to the second end of the known feedback resistance R REF    57 .  
         [0057]    Because the input impedance of an operational amplifier  55  is characteristically very high, most of the current flowing through the device under test will flow through the reference resistance R REF    57 . The resistance value R X  of the device under test may therefore be calculated as:  
           R   X   =R   REF   *V   S   /−V   O   (Formula 1)  
         [0058]    In practice, the device under test  52  may have one or more parallel paths around it depending on the board&#39;s circuit topology. In these situations, the impedance of these parallel parasitic paths can cause errors since they are not included in the above formula. FIG. 6B is a schematic block diagram of the simple analog test apparatus  50  illustrating the parasitic resistance problem. As shown, a parallel parasitic resistance path Z  58  is in parallel with the device under test  52 .  
         [0059]    The problem shown in FIG. 6B is circumvented using a technique called “guarding”. An analog test apparatus which illustrates the guarding technique is shown in FIG. 6C. In this apparatus, the parallel impedance path is broken by a guard bus G  61 . By connecting the G bus  61  as shown, the current that would otherwise flow through both Z sg  and Z ig  becomes negligible. When the non-inverting input  54  to the operational amplifier  55  is grounded as shown in FIG. 5C, the inverting input  53  becomes a virtual ground due to characteristics of the operational amplifier  55 . This also places the I bus connection  53  at virtual ground. With the G bus  61  also at ground potential, no difference of potential exists across Z ig,  and no current flows through the parallel path around R X  and through the feedback path R REF . The applied voltage V S  on line  51  does supply current to Z sg ; however, this current does not affect the measurement as long as the output impedance of the applied voltage V S  is very low compared to Z sg . Also, because there may be one or more parallel paths around the device under test  52 , there may be one or more G bus connections. Accordingly, as long as the above conditions are met, essentially the same current flows through R X  and R REF , allowing formula (1) to apply once again.  
         [0060]    In practice, the value R X  of the device under test  52  is allowed to deviate from a nominal value within a tolerance range. The board test software  262  (see FIG. 5A) returns a “PASS” status for the device under test  52  if the value R X  calculated using formula (1) is within these tolerances, and a “FAIL” status is returned otherwise. Accordingly, the current delivered to test the device must handle device values within the entire tolerance range, or must be high enough (greater than some minimum value) to handle the highest allowable impedance. In addition, since some of this current will be lost to flow through the parasitic path portion Z sg , the required stimulus current must be higher to account for this loss.  
         [0061]    In turn, the traces through which the required current is delivered must be thick enough to accommodate its required minimum value. Hence, given the maximum allowable impedance value R X =R MAX  of the device under test  52  and the impedance Z sg  of the parasitic path, the minimum required current i min  is given by:  
           i   min   =V   S   /R   MAX   +V   S   /Z   sg   (Formula 2).  
         [0062]    The resistance of the trace R TRACE  is based on:  
         [0063]    1. For an analog test, the allowable test error budget (as analyzed by the tester software, e.g., IPG  259  of FIG. 5A) as it relates to I MIN , involves (more or less) an allowable voltage drop in the circuit divided by R TRACE . The allowable error impedance calculated by the tester analysis software leads directly to a maximum value for R TRACE .  
         [0064]    2. For a digital/overdrive test R TRACE  comes from the allowable voltage drop for the device/family type and the device&#39;s normal operating voltage levels combined with the worst case expected current.  
         [0065]    3. For power traces R TRACE  can be calculated based on the actual expected power supply current for the DUT board, or the maximum current the system power supply can deliver. This current combined with the acceptable power supply voltage drop leads to a maximum value for R TRACE .  
         [0066]    The resistance of a conductor with length (L), cross-sectional area (A) and bulk resistivity (p) is given by:  
             R   =       ρ                 L     A             (     Formula                 3     )                               
 
         [0067]    which leads to:  
             A   =         ρ                 L     R     .             (     Formula                 4     )                               
 
         [0068]    Applying this to a specific printed circuit board construction we can work in terms of squares (trace segments with equal length and width) to simplify the calculations. For example the total resistance R TRACE  of a 1-oz copper trace having a per-square resistance of 0.49 mOhms/square is equivalent to the following number of squares:  
           n   squares   =R   TRACE /0.00049  (Formula 5)  
         [0069]    If this trace has length l, its corresponding width is:  
           w=l/n   squares   (Formula 6)  
         [0070]    [0070]FIG. 7 is a flowchart illustrating a method  120  for calculating the minimum sufficient trace width of a net used to perform an analog test. As illustrated therein, the method includes a first step  121  of obtaining the current requirements, trace length, trace resistivity, and allowable error budget of the trace. These parameters may be calculated based on other known parameters, or may be simply be known given values. The method  120  includes the second step  122  of determining the maximum resistance R MAX  of the trace. Again, the maximum resistance R MAX  may be calculated based on the current requirements, trace length, trace resistivity, and allowable error budget obtained in step  121 , or may be simply be a known given value. The method  120  includes the third step of calculating the minimum cross-sectional area of trace based upon trace length, trace resistivity, and maximum resistance of trace R MAX . If the thickness is a known fixed value, the calculation may be reduced to finding the minimum sufficient width of the trace.  
         [0071]    Digital tests typically necessitate a minimum current of 0.1A to be delivered through the trace. The acceptable voltage loss (drop) between the tester and DUT is usually on the order of 0.2 V. This means that the maximum resistance of the trace is:  
           R   TRACE =0.2/0.1=2  Ohms   (Formula 7)  
         [0072]    Using Formula 5 for a 1-oz copper trace having a per-square resistance of 0.49 mOhms/square:  
           n   squares =2/0.00049=4082  (Formula 8)  
         [0073]    If the trace has a length/=20″, formula 6 results in a width of:  
           w =20/4082=0.0049 inches  (Formula 9)  
         [0074]    These numbers are used for illustration only. Those skilled in the art will appreciate that the results will depend upon the actual values of the current requirements for the test(s), the applied voltage, the trace resistivity, and the trace length.  
         [0075]    For digital over-drive tests, over-driving requires a larger amount of current to be delivered than in regular digital tests, for example, a typical value may be 0.75 A. The acceptable voltage loss (drop) between the tester and DUT is usually on the order of 0.2 V. This means that the maximum resistance of the trace is:  
           R   TRACE =0.2/0.75=0.267  Ohms   (Formula 10)  
         [0076]    Using formula 5 for a 1-oz copper trace having a per-square resistance of 0.49 mOhms/square:  
           nsquares= 0 . 267 / 0 . 00049 = 545     (Formula 11)  
         [0077]    If the trace has a length l=20″, formula 6 results in a width of:  
           w= 20/545=0.0367 inches  (Formula 12)  
         [0078]    Again, these numbers are used for illustration only. Those skilled in the art will appreciate that the results will depend upon the actual values of the current requirements for the test(s), the applied voltage, the trace resistivity, and the trace length.  
         [0079]    Turning back to FIG. 5A, in the preferred embodiment, the tester  210  is an Agilent 3070 running tester software called Board Consultant  258  for setting up a board description of a board under test  201 , Integrated Program Generator (IPG)  259  for determining the appropriate tests to be run for each device and generating the tests, the trace minimizing calculator  261  of the invention, and various board tests  262  generated by IPG  259 . It will be appreciated that any of the software modules may be executed by a tester processor or alternatively on a remote computer system which communicates with the tester  210  as necessary using standard communication protocols.  
         [0080]    [0080]FIGS. 5B, 5C, and  5 D illustrate a portion of an example PCB  215  used for testing a board under test  211 . The portion shown is the portion of the PCB  215  implementing trace  221  for testing resistor R X    201  on the board under test  211  of FIG. 5A. As illustrated in FIGS. 5B, 5C, and  5 D, net  221  comprises the metal trace connecting conductive pad  222   a  to via  222   c  on the bottom side  215   a  of the PCB  215  and via  222   c  to conductive pad  223   a  on the top side  215   b  of the PCB  215 . The trace width to be determined is shown as w x .  
         [0081]    In the example of FIGS. 5B, 5C, and  5 D, the position of certain tester interface pins  218  correspond to the positions of the bottom conductive pad  222   a , trace corner  222   b , via  222   c , and top conductive pad  223   a . For convenience, labels P 1 , P 2 , P 3 , and P 4  identify the locations of the bottom conductive pad  222   a , the trace corner  222   b , via  222   c , and the top conductive pad  223   a  respectively. The x and y coordinates of the locations identified by labels P 1 , P 2 , P 3 , and P 4  are known by the tester software (e.g., IPG  259  of FIG. 5A). Accordingly, the location data of the points P 1 , P 2 , P 3 , P 4  may be used by the trace minimizing calculator  262  to calculate the length of the trace  221  under consideration. For example, the length of trace  221  is the distance between P 1  and P 2  plus the distance between P 2  and P 3  plus the distance between P 3  and P 4 .  
         [0082]    Referring again to FIG. 5A, during actual testing of the resistor R X    201 , only the pin  218   a  located at position P 1  at the far end of the trace  221  (See FIGS.  5 B- 5 D) is actually electrically connected to the conductive pad  222   a  on the bottom side  215   a  of the PCB  215 . This is accomplished by closing the relay  213   a  (FIG. 5A) associated with the tester pin  218   a  located at position P 1 . The far end of the trace  221  at position P 4  is electrically connected to the first end of the resistor R X    201   a . Accordingly, trace  221  forms the line  51  in the operational amplifier circuit of FIG. 6C.  
         [0083]    It will be appreciated that the second end of the resistor  201   b  is connected to the I bus input  53  of the operational amplifier  55  of FIG. 6C using a different trace (not shown).  
         [0084]    Prior to test, the integrated program generator IPG  259  (FIG. 5A) generates a test specification file  270  containing tests for each trace, including the maximum resistance for the trace. The parameters in this file may be used to calculate the minimum trace width or cross-sectional area for a given trace.  
         [0085]    [0085]FIG. 8A illustrates the format of a portion  300  of an example test specification file  270  generated by IPG  259 . As illustrated, to test a device, net or pad on the board under test  211 , IPG  259  generates a test statement containing a connection statement  310  and a measurement statement  320 . The connection statement  310  identifies the conductive pads on the bottom of the test fixture printed circuit board  215  that should be probed by the tester interface pins  218 , and causes the tester  210  to close/open the appropriate relays  213  (which make/do not make electrical connection between the tester interface pins  218  and the MOA  254  in the tester). The connection statement  310  also specifies the connections to make for each of the S bus  51 , I bus  53 , G bus  61 , and non-inverting input  54  of the operational amplifier  55  in the MOA circuit  50  (FIG. 6C) implementing the MOA circuit  254  of the tester  210 .  
         [0086]    The measurement statement  320  defines the device name, device type, expected measured value, tolerance, test limits, measurement options, and MOA circuit parameters such as the minimum and maximum admittance Y si , Y sg , and Y ig  of the device and parasitic parallel path impedances.  
         [0087]    [0087]FIG. 8B illustrates the portion  300  of an example test specification file  270  associated with testing the resistor R X    201  of FIG. 5A. As shown, in this example the connection statement  310  specifies connecting the S bus to a source voltage SOURCE, the I bus to node RX_IN defined to be at position P 1  on the fixture PCB  215 , and the G bus to ground.  
         [0088]    The measurement statement  320  specifies the nominal value of the resistor R X  to be 75 Ohms with a tolerance of +/−1%. For this example the test system analysis software has determined that the maximum acceptable trace resistance (R TRACE ) for the S bus connection is 0.12 Ohms. Assuming that the trace is a 1-oz copper trace having a per-square resistance of 0.49 mOhms/square, and that the trace minimizing calculator  262  determines the length/of the trace connecting P 1  to P 2 , P 2  to P 3 , and P 3  to P 4  to be 8.6 inches, formula (5) may be applied to determine the number of squares as:  
           n   squares   =R   TRACE /0.00049=0.12/0.00049=245  
         [0089]    In this example, since the trace length/is 8.6 inches, then applying formula (6), the width of the trace should be:  
           w=l/n   squares =8.6/245=0.035 inches.  
         [0090]    [0090]FIG. 8C illustrates the format of an example portion  330  of an output file generated  330  by the trace minimizing calculator  261 . As illustrated, the output file specifies a trace width &lt;trace_width&gt; to be associated with a trace &lt;trace_name&gt;. The trace route is defined by PCB positions &lt;first-trace_pin&gt;, &lt;next_trace_pin1&gt;, . . . &lt;next_trace_pinN&gt;, and &lt;last_trace_pin&gt;.  
         [0091]    [0091]FIG. 8D illustrates the example portion  300  of the output file generated by the trace minimizing calculator  261  based on the input file  300  of FIG. 8B. The portion of the output file shown is a section of the file associated with the trace RX_IN_TRACE connecting to the first end  201   a  of resistor RX  201  on the board under test  211 . As shown, in this example, the output file contains the trace definition “CUSTOMTRACE — 35 mils” assigned to the trace named “RX_IN_TRACE”. CUSTOMTRACE — 35 mils is determined by the software to be 0.035 inches (or 35 mils) wide. The PCB locations of the trace are indicated as P 1 , P 2 , P 3 , and P 4 .  
         [0092]    FIGS.  9 A- 9 D illustrate another embodiment of a fixture printed circuit board  400  implemented in accordance with the principles of the invention. In this embodiment, traces  430   a ,  430   d  of a first thickness are implemented on layers  401  and  403 , where traces  430   b ,  430   c  characterized by a second thickness greater than the first are implemented on layer  402 . Traces  430   b ,  430   c  which require a lower resistance are preferably implemented on layer  402 , while traces allowing higher resistance  430   a ,  430   d  are implemented on layers  401  and  403 .  
         [0093]    The above-described invention improves over the prior art in several ways. First, the cross-sectional area of each trace is determined on a per trace basis to ensure that current delivery requirements are met. Second, the cross-sectional area of each trace is preferably minimized to a substantially minimum cross-sectional area that still meets the current delivery requirements of each trace. By minimizing the cross-sectional area of each trace on a per trace basis, the size and number of layers of the fixture printed circuit board are reduced.  
         [0094]    While illustrative and presently preferred embodiments of the invention have been described in detail herein, it is to be understood that the inventive concepts may be otherwise variously embodied and employed and that the appended claims are intended to be construed to include such variations except insofar as limited by the prior art.