Abstract:
An interconnect structure which has improved stress migration reliability is disclosed. According to one exemplary embodiment, the interconnect structure comprises a top interconnect metal layer, at least one via and a bottom interconnect metal layer. The bottom interconnect metal layer comprises at least one finger. The at least one via electrically connects the top interconnect metal layer to the at least one finger. The finger width of the at least one finger is less than a bottom layer width of the bottom interconnect metal layer. In another embodiment, a method for fabricating the above interconnect structure is disclosed.

Description:
TECHNICAL FIELD  
         [0001]    The present invention relates generally to the field of semiconductor devices. More particularly, the present invention relates to interconnect structures in semiconductor devices.  
         BACKGROUND ART  
         [0002]    Modern semiconductor dies include densely packed circuits which use, among other things, interconnect metal layers and vias for electrical connectivity. For example, a top interconnect metal layer can be electrically connected to a bottom interconnect metal layer by a via or a number of vias.  
           [0003]    Disadvantageously, stress migration or stress-induced voiding (“SIV”), i.e. migration of voids in metals due to stress, can reduce or eliminate electrical contact between vias and interconnect metal (“ICM”) layers, which can cause device failure. Stress migration can be particularly troublesome in connections between a via and its associated underlying ICM layer when the width of the underlying ICM layer is much greater than the width of the via, i.e. a high ratio of ICM layer width to via width.  
           [0004]    Stress migration can cause small voids in an underlying interconnect metal layer to migrate to beneath a via. These small voids can collectively form into a large void beneath the via. Large voids reduce or eliminate electrical contact between the underlying metal layer and the via. Stress migration can be caused by thermal cycling and process variations such as improper annealing, chemical mechanical polish (“CMP”) processes, copper fillings, barrier/seed quality and dielectric interface quality. Thus, stress migration can cause reduced electrical contact between vias and underlying ICM layers, which causes increased resistivity and can lead to device failure. Accordingly, there exists a strong need in the art to overcome deficiencies of known interconnect structures such as those described above, and for an interconnect structure having improved stress migration reliability.  
         SUMMARY  
         [0005]    The present invention is directed to an interconnect structure having improved stress migration reliability. The invention addresses and resolves the need in the art for an interconnect structure which has improved stress migration reliability and reduced device failure rates.  
           [0006]    According to one exemplary embodiment, the interconnect structure comprises a top interconnect metal layer and at least one via and a bottom interconnect metal layer. The bottom interconnect metal layer includes at least one finger. The at least one via electrically connects the top interconnect metal layer to the at least one finger. The finger width of the at least one finger is less than the bottom interconnect metal layer width. The exemplary embodiment can also comprise an interlayer dielectric situated over the bottom interconnect metal layer and beneath the top interconnect metal layer, where the at least one via is formed within the interlayer dielectric. In another embodiment, the invention is a method for fabricating the above interconnect structure. Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]    [0007]FIG. 1A shows a top view of a conventional interconnect structure.  
         [0008]    [0008]FIG. 1B shows a cross-sectional view of the conventional interconnect structure of FIG. 1.  
         [0009]    [0009]FIG. 2 is a flowchart illustrating the steps taken to implement an embodiment of the invention.  
         [0010]    [0010]FIG. 3A shows a top view of an interconnect structure in intermediate stages of formation, according to one embodiment of the invention.  
         [0011]    [0011]FIG. 3B shows a top view of an interconnect structure in intermediate stages of formation, according to one embodiment of the invention.  
         [0012]    [0012]FIG. 3C shows a top view of an interconnect structure in intermediate stages of formation, according to one embodiment of the invention.  
         [0013]    [0013]FIG. 3D shows a top view of an interconnect structure according to one embodiment of the invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0014]    The present invention is directed to an interconnect structure having improved stress migration reliability. The following description contains specific information pertaining to the implementation of the present invention. One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order not to obscure the invention.  
         [0015]    The drawings in the present application and their accompanying detailed description are directed to merely exemplary embodiments of the invention. To maintain brevity, other embodiments of the present invention are not specifically described in the present application and are not specifically illustrated by the present drawings.  
         [0016]    [0016]FIG. 1A shows a top view of conventional interconnect structure  100  in a semiconductor die. As shown in FIG. 1A, interconnect structure  100  includes bottom interconnect metal (“ICM”) layer  112 , vias  130  and  140  and top ICM layer  120 . Bottom ICM layer  112  and top ICM layer  120  can comprise aluminum or copper and can be fabricated by a deposition and patterning process. Vias  130  and  140  can comprise aluminum or copper and are situated within an interlayer dielectric (not shown in FIG. 1A). Bottom ICM layer  112  is electrically connected to top ICM layer  120  by vias  130  and  140 . Width  160  of bottom ICM layer  112  is much greater than width  161  of via  130  and thus, as described above, stress migration can cause small voids to form into a large void beneath via  130 .  
         [0017]    [0017]FIG. 1B shows a cross-sectional view along line  1 B- 1 B of conventional interconnect structure  100  in FIG. 1A. As shown in FIG. 1B, interlayer dielectric (“ILD”)  150  and via  130  are situated over bottom ICM layer  112 . ILD layer  150  can comprise a low-k dielectric and can be fabricated by a deposition process. Top ICM layer  120  is situated over, and is in contact with, ILD layer  150  and via  130 . Void  154  is formed beneath via  130  due to stress migration, which can be caused by thermal cycling and process variations. Void  154  causes reduced electrical contact between via  130  and bottom ICM layer  112 , which causes increased resistivity and can lead to device failure.  
         [0018]    [0018]FIG. 2 shows a flowchart illustrating exemplary process steps taken to implement an embodiment of the invention. Certain details and features have been left out of flowchart  200  of FIG. 2 that are apparent to a person of ordinary skill in the art. For example, a step may consist of one or more sub-steps or may involve specialized equipment or materials, as known in the art. While steps  202  through  210  indicated in flowchart  200  are sufficient to describe one embodiment of the present invention, other embodiments of the invention may utilize steps different from those shown in flowchart  200 . It is noted that the processing steps shown in flowchart  200  are performed on a wafer which, prior to step  202 , includes a substrate.  
         [0019]    [0019]FIGS. 3A, 3B,  3 C and  3 D show top views of some of the features of an exemplary interconnect structure in intermediate stages of fabrication, formed in accordance with one embodiment of the invention. These intermediate stages of fabrication show some of the features of fabrication of an exemplary interconnect structure, formed in accordance with one exemplary embodiment of the present invention. These fabrication stages are described in greater detail further below in relation to flowchart  200  of FIG. 2.  
         [0020]    Referring to FIGS. 2 and 3A, at step  202  of flowchart  200 , and as shown in corresponding structure  302  in FIG. 3A, bottom interconnect metal layer  312  is deposited over a substrate (not shown in any of the Figures). Bottom ICM layer  312  can comprise, for example, aluminum or copper. Referring to FIGS. 2 and 3B, at step  204  of flowchart  200 , and as shown in corresponding structure  304  in FIG. 3B, bottom ICM layer  312  is patterned to form fingers  372 ,  374 ,  376 ,  382 ,  384  and  386 . The width of fingers  372 ,  374 ,  376 ,  382 ,  384  and  386  can be approximately equal to each other. In one embodiment, the width of fingers  372 ,  374 ,  376 ,  382 ,  384  and  386  are equal to a minimum design rule width. Those skilled in the art shall recognize that the finger widths can vary from each other and the number of fingers can vary without departing from the scope of the present invention.  
         [0021]    Referring to FIG. 2, at step  206  of flowchart  200 , an interlayer dielectric (not shown in FIGS. 3A through 3D) is deposited over bottom ICM layer  312 . The interlayer dielectric can comprise a low-k dielectric. Referring to FIGS. 2 and 3C, at step  208  of flowchart  200 , and as shown in corresponding structure  308  in FIG. 3C, vias  332 ,  334 ,  336 ,  342 ,  344  and  346  are formed within the interlayer dielectric (not shown) deposited at step  206 . Vias  332 ,  334 ,  336 ,  342 ,  344  and  346  are situated over, and electrically connected to, fingers  372 ,  374 ,  376 ,  382 ,  384  and  386 , respectively. Vias  332 ,  334 ,  336 ,  342 ,  344  and  346  can comprise, for example, tungsten or copper.  
         [0022]    Referring to FIGS. 2 and 3D, at step  210  of flowchart  200 , and as shown in corresponding structure  310  in FIG. 3D, top interconnect metal layer  320  is deposited and patterned over the interlayer dielectric (not shown) and vias  332 ,  334 ,  336 ,  342 ,  344  and  346 . Thus, top ICM layer  320  is situated over, and electrically connected to, vias  332 ,  334 ,  336 ,  342 ,  344  and  346 . Top ICM layer  320  can comprise, for example, aluminum or copper.  
         [0023]    [0023]FIG. 3D shows interconnect structure  310  formed in accordance with one embodiment of the present invention. As shown in FIG. 3D, structure  310  includes top ICM layer  320 , vias  332 ,  334 ,  336 ,  342 ,  344  and  346  and bottom ICM layer  312 , where bottom ICM layer  312  comprises fingers  372 ,  374 ,  376 ,  382 ,  384  and  386 . Bottom ICM layer  312  is electrically connected to top ICM layer  320  by vias  332 ,  334 ,  336 ,  342 ,  344  and  346 . Specifically, fingers  372 ,  374 ,  376 ,  382 ,  384  and  386  are connected to vias  332 ,  334 ,  336 ,  342 ,  344  and  346 , respectively.  
         [0024]    The present invention advantageously increases stress migration reliability by reducing the effective ratio of the width of the bottom ICM layer to via width, while substantially retaining the overall ICM layer width to preserve its low resistance and its high current conduction capability. Referring to FIG. 3D, bottom ICM layer  312  has bottom layer width  360 . Fingers  372 ,  374  and  376  have finger widths  362 ,  364  and  366 , respectively. Finger widths  362 ,  364  and  366  are each equal to slightly less than approximately one-third of bottom layer width  360 . Moreover, a substantial portion of bottom ICM layer  312  has preserved its initial configuration, i.e. a substantial portion of bottom ICM layer  312  is not divided into fingers. However, the effective width of bottom ICM layer  312  in relation to via  332  is approximately equal to finger width  362 . Moreover, the effective ratio of the width of bottom ICM layer  312 , e.g. finger width  362 , to via width, e.g. width of via  332 , is significantly reduced, while approximately retaining the overall bottom ICM layer width because the sum of finger widths  362 ,  364  and  366  is approximately equal to bottom layer width  360 . A similar analysis of the remaining fingers, i.e. fingers  382 ,  384  and  386 , and vias, i.e. vias  342 ,  344  and  346 , is not described herein because these elements are substantially similar to the aforementioned fingers and vias.  
         [0025]    In comparison to the conventional interconnect structure  100  of FIG. 1A, the embodiment of the present invention of FIG. 3D, reduces the effective ratio of the width of bottom ICM layer  312 , e.g. finger width  362 , to a via width, e.g. widths of vias  362 ,  364  and  366 , to approximately one-third of the ratio of bottom layer width  160  to via width  161 . This reduction in the effective ratio of bottom layer width to via width advantageously increases stress migration reliability, which reduces void migration underneath vias.  
         [0026]    In sum, forming interconnect structures in the manner described above advantageously results in an ICM layer comprising fingers, which reduces the effective ratio of bottom layer width to via width. Thus, stress migration within the interconnect structure is reduced. Moreover, in comparison to conventional interconnect structures, electrical contact between vias and underlying ICM layers is more reliable and resistivity is reduced.  
         [0027]    From the above description of exemplary embodiments of the invention it is manifest that various techniques can be used for implementing the concepts of the present invention without departing from its scope. Moreover, while the invention has been described with specific reference to certain embodiments, a person of ordinary skill in the art would recognize that changes could be made in form and detail without departing from the spirit and the scope of the invention. For example, the number of fingers or the finger widths referred to in the present application can be modified without departing from the scope of the present invention. The described exemplary embodiments are to be considered in all respects as illustrative and not restrictive. It should also be understood that the invention is not limited to the particular exemplary embodiments described herein, but is capable of many rearrangements, modifications, and substitutions without departing from the scope of the invention.  
         [0028]    Thus, an interconnect structure having improved stress migration reliability has been described.