Abstract:
A method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution controls the defined pitches of the target layer by use of polymer spacer, photo-insensitive polymer plug and polymer mask during the process, so as to achieve the minimum pitch of the target layer beyond photolithographic resolution. Applied to memory manufacture, this method is capable of simultaneously overcoming the process difficulty of significant difference between polysilicon pitches in memory array region and periphery region.

Description:
FIELD OF THE INVENTION 
   The present invention relates generally to the manufacture of an integrated circuit (IC) and more particularly, to a method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution. 
   BACKGROUND OF THE INVENTION 
   Generally, the growth of integrated circuit industry depends on the continuous advancement in photolithographic technologies in integrated circuit manufacture. Propelled by advancement of photolithographic technologies, integrated circuits have repeatedly achieving the targets of higher density and smaller size. Hence, critical dimension (CD), including both minimum line width and space, of integrated circuits also has become finer and finer, indicating that higher resolutions are required. However, photolithographic resolution is fundamentally restricted by the wavelength of light sources used. To overcome such restriction, numerous methods provided by prior arts are available. 
   Referring to U.S. Pat. No. 5,618,383 issued to John N. Randall disclosing a low-temperature process for forming narrow lateral dimensioned microelectronic structures, this art comprises the steps of depositing and patterning an uncured photoresist on a supporting layer, at a low temperature using an anisotropic manufacturing process, depositing a conformal layer on sidewalls and on surfaces of the uncured photoresist with the conformal layer having substantial etch selectivity with respect to the photoresist, low-temperature anisotropic etching to remove the conformal layer from the surfaces of the uncured photoresist without substantially etching the conformal layer from vertical sidewalls, selectively removing the uncured photoresist to leave the isolated conformal layer, spin-coating of photoresist onto the isolated conformal layer and etching back to stop at the conformal layer, selectively etching to remove the conformal layer for forming an opening having a width as that of the conformal layer, and depositing a conductor to the opening, removing excessive conductor and photoresist for producing a narrow lateral dimensioned structure. However, structures formed using this method are prone to drawbacks as having relatively insufficient adherence. 
   Referring to U.S. Pat. No. 5,328,810 issued to Tyler A. Lowrey disclosing a method for reducing, by a factor of 2 N , the minimum masking pitch of a photolithographic process, this art utilizes a conventional exposure and developing method for producing pattern of minimum line width F formable by photolithographic process onto a hard buffer layer, with the steps of reducing the line width of the hard buffer layer from F to F/2 by direct or indirect manner, depositing a second hard buffer layer having a relatively higher selective etch ratio to that of the hard buffer layer and underlayers, anisotropically etching to remove the second hard buffer layer on the top surfaces of the first hard buffer layer to leave the second hard buffer layer on the sidewalls of the first hard buffer layer, adopting the left sidewall second hard buffer layer as etch mask to reduce the pitch to ½ of the original pitch of mask pattern for that a width of the sidewall second hard buffer layer being F/4 at this point. The foregoing steps are repeated, and the minimum masking pitch of a photolithographic process is reduced by a factor of 2 N . To be more precise, this method reduces a pitch by repeated deposition of conformal layers and anisotropic etching of hard buffer layers. However, this art has a drawback as the hard buffer layer being not so easily deposited. 
   Therefore, it is desired an improved method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution. 
   SUMMARY OF THE INVENTION 
   One object of the present invention is to provide a method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution, so as to resolve difficulties as photolithographic resolution being restricted by the wavelength of light source used. 
   In an embodiment according to the present invention, a method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution comprises deposition of an insulating layer and a polysilicon onto a substrate already defined with a memory array region and a periphery region, formation of photoresist pattern on the polysilicon with the memory array region and periphery region to have different pitches, formation of polymer spacer to the photoresist pattern, etching the polysilicon to form trenches with the photoresist pattern and polymer spacer as mask, filling a photo-insensitive polymer into the trenches, removing the photoresist pattern over the memory array region, formation of polymer mask with which as mask to etch the polysilicon in the memory array region, and removing all the polymers, and as a result, it is obtained a final polysilicon pitch beyond photolithographic resolution. 
   In another embodiment according to the present invention, a method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution comprises the steps of deposition of an insulator, a polysilicon and a buffer layer onto a substrate already defined with a memory array region and a periphery region, formation of a photoresist pattern on the buffer layer with the memory array region and periphery region to have different pitches, formation of polymer spacers to the photoresist pattern, etching the buffer layer and polysilicon with the photoresist pattern and polymer spacers as mask to form trenches, filling the trenches with a photo-insensitive polymer, etching back to the buffer layer, removing the buffer layer, forming a polymer mask over the memory array region with which as mask to etch the polysilicon, and removing all the polymers, and as a result, it is obtained a final polysilicon pitch beyond photolithographic resolution. 
   Furthermore, in this method, the minimum polysilicon pitch in the memory array region on photomask is enlarged and the initial minimum polysilicon pitch in the periphery region on photomask can be reduced. It helps overcoming the difficulty of a significant difference in polysilicon pitch between the memory array region and periphery region in conventional approaches. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which: 
       FIGS. 1A to 1I  are schematic views showing a first embodiment according to the present invention; and 
       FIGS. 2A to 2I  are schematic views showing a second embodiment according to the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   First Embodiment 
     FIGS. 1A–1I  show a first embodiment according to the present invention. Referring to  FIG. 1A , an oxide  12  and a polysilicon  14  are deposited on a substrate  10  on which a memory array region  10   a  and a periphery region  10   b  are defined. The polysilicon  14  is the target layer that will be formed with pitches beyond photolithographic resolution in the following process. An anti-reflection coating (ARC)  16  and a photoresist  18  are applied on the polysilicon  14 , and a photoresist pattern  18  is defined to the photoresist  18  after exposure and development. The minimum pitch in the memory array region  10   a  is A and the minimum pitch in the periphery region  10   b  is B. Pitch is defined as the sum of a line width and a line space, and preferably, both the line width and the space in the memory array region are A/2, as shown in  FIG. 1B . 
   Referring to  FIG. 1C , polymer spacers  20  are formed on each sidewall of the photoresist pattern  18 . This polymer  20  is deposited only on the sidewalls of the photoresist pattern  18 . If the polymer  20  is also deposited on the top surface of the photoresist pattern  18 , an etching back is further performed to remove the top portion. Preferably, the space C between the polymer spacers  20  in the memory array region  10   a  is A/4. At the same time, the space in the periphery region  10   b  becomes D. Using the photoresist pattern  18  and the polymer spacers  20  as a mask to etch the polysilicon  14  and ARC  16 , trenches  22  having a width C are formed in the memory array region  10   a . As described above, C=A/4, and the trenches  24  formed at the periphery region  10   b  have a width of D, as shown in  FIG. 1D . A photo-insensitive polymer  26  is then filled in the trenches  22  and  24  and etched back, as shown in  FIG. 1E . Another photoresist  28  is coated. Exposure and development are performed to the memory array region  10   a , and only the photoresist  28  in the periphery region  10   b  remains, as shown in  FIG. 1F . 
   Using, for example, chemical vapor deposition (CVD), polymer masks  30  and  32  are formed in the periphery region  10   b  and memory array region  10   a , respectively. The polymer mask  32  in the memory array region  10   a  has a space of E, and preferably, E=C=A/4, as shown in  FIG. 1G . With the polymer mask  32 , the ARC  16  and polysilicon  14  in the memory array region  10   a  are etched to form trenches  34  having a width of E, as shown in  FIG. 1H . Referring to  FIG. 1I , the polymer masks  30  and  32 , photoresist  28  and  18 , polymer spacers  20  and photo-insensitive polymer  26  are removed. In the memory array region  10   a , the spaces  34  and  36  are E and C, respectively, and equal to A/4, with a final pitch F equal to A/2. In other words, the final pitch F is reduced to a half of the initial pitch A of the photoresist pattern  18  shown in  FIG. 1B . In the periphery region  10   b , the final pitch G is the same as the initial pitch B of the photoresist pattern  18  shown in  FIG. 1B . 
   Second Embodiment 
     FIGS. 2A–2I  show another embodiment according to the present invention. An oxide  52  and a polysilicon  54  are deposited onto a substrate  50 , on which a memory array region  50   a  and a periphery region  50   b  are to be defined, and the polysilicon  54  in the memory array region  50   a  is the target layer to have the pitch beyond photolithographic resolution. Referring to  FIG. 2B , a buffer layer  56 , for example, oxide or silicon nitride of sufficiently high etch selectivity with respect to polysilicon  54  is further deposited. An ARC  58  and a photoresist  60  are applied thereon, and a photoresist pattern  60  is defined by exposure and development processes. The minimum pitch in the memory array region  50   a  is referred to as A, and the minimum pitch in the periphery region  50   b  is referred to as B. Preferably, a line width and a line space of the pitch A are both A/2. 
   Referring to  FIG. 2C , polymer spacers  62  are formed on the sidewalls of the photoresist pattern  60 . Preferably, the width of polymer spacers  62  is A/8, such that each space C between the polymer spacers  62  in the memory array region  50   a  is A/4. Meanwhile, each space in the periphery region  10   b  is D. The ARC  58 , buffer layer  56  and polysilicon  54  are etched with the photoresist pattern  60  and polymer spacers  62  as etch mask, to form trenches  64 , each of which having a width of C, in the memory array region  50   a  and to form trenches  66 , having a width of D, in the periphery region  10   b , as shown in  FIG. 2D . 
   The polymer spacer  62  can be optionally removed. A photo-insensitive polymer  68  fills trenches  64  and  66 . It is then etched back thereto to stop at the buffer layer  56 , and in this etching back process, over etching is allowed to the buffer layer  56 , Referring to  FIG. 2E . Buffer layer  56  is then removed and a photoresist  70  is coated. Exposure and development are performed to the memory array region  50   a , and only the photoresist  70  in the periphery region  50   b  remains, as shown in  FIG. 2F . 
   Using for example CVD, polymer masks  72  and  74  are deposited in the memory array region  50   a  and periphery region  50   b , respectively. The polymer mask  74  in the memory array region  50   a  has spaces E, and preferably, E=C=A/4, as shown in  FIG. 2G . With the polymer mask  74 , polysilicon  54  in the memory array region  50   a  is etched to form trenches  76 , each of which having a width of E, as shown in  FIG. 2H . Referring to  FIG. 2I , polymer masks  72  and  74 , photoresist  70  and photo-insensitive polymer  68  are all removed. In the memory array region  50   a , spaces  76  and  78  are E=C=A/4, with a final pitch of F=A/2. That is, the final pitch F is reduced to a half of the initial pitch A of the photoresist pattern  60  shown in  FIG. 2B . On the other hand, in the periphery region  50   b , the final pitch G is the same as the initial pitch B of the photoresist pattern  60  shown in  FIG. 2B . 
   The ARC layers  16  and  58  may be organic before or after coating the photoresist. Organic ARC material if spun-on before coating the photoresist, has the advantage of being simultaneously removed with the photoresist. In addition, the purpose of polymer spacers  20  and  62  are used to reduce the spaces C in the photoresist pattern  18  and  60 . 
   Embodiments of the invention realize the final pitch F of the polysilicon in the memory array region being a half of the initial pitch A of the photoresist pattern. In the two embodiments, when the initial pitch A is less than 2 times of the photolithographic resolution, then the final pitch F, equal to A/2, will be less than photolithographic resolution. In addition, the initial polysilicon pitch in the memory array region in this invention is twice as much as it is in the conventional approach. As a result, the difference in polysilicon pitch in the memory array region and peripheral region is thus minimized. Therefore, this invention provides a method which overcomes the difficulty, encountered in the conventional approach, of a significant difference in the polysilicon pitch in the memory array region and periphery region. 
   While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.