Abstract:
A phase locked loop circuit and method that substantially decouples control of the phase/frequency and the amplitude of the oscillation output such that the frequency of the oscillation can be controlled independently of the amplitude. The phase locked loop circuit comprises a phase/frequency control loop and an amplitude control loop wherein both loops control an oscillator that oscillates at a certain frequency in response to a phase/frequency control signal generated by the phase/frequency control loop. In addition, the oscillation amplitude is determined by an amplitude control signal generated by the amplitude control loop. As with conventional circuits of this type, a parasitic gain is coupled from the amplitude control loop into the phase/frequency control loop, thereby causing interference between the loops that leads to stability problems. To counter the coupling of the parasitic gain, an inverted gain is inserted from the amplitude control loop into the phase/frequency control loop in opposite to the parasitic gain, so as to effectively cancel the interference. The circuit and method also provide for canceling the opposite parasitic gain that is coupled from the phase/frequency loop into the amplitude control loop.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally concerns the control of a phase locked loop (PLL), and in more particular concerns the simultaneous control of frequency and amplitude in a PLL. 
     2. Background Information 
     Amplitude control of an oscillator over process, temperature, and power supply variations is a challenging task in PLL design. Uncontrolled oscillation amplitude can be a source of additional jitter due to changing operating points and cyclostationary device noises. Another application that requires amplitude control in PLLs is the master-slave tuning in on-chip filters. Oscillation amplitude of the PLL should match with the signal amplitude processed in the filter to avoid distortion that causes frequency errors. However, active amplitude compensation incorporated into a PLL can be a major problem of stability. Consider a gm-C (transconductance-Cell) based relaxation type oscillator. The loop introduced to control amplitude interferes with the main phase/frequency locking loop. The mechanism that adjusts the amplitude, i.e., the current of the negative gm load of the oscillator where the negative gm load is used to compensate for resistive losses, initiates the oscillation cycle as well as sets the oscillation amplitude, thereby imposing an inverse force that causes the two loops that fight each other, wherein precise control of one of the loops has an adverse effect on the control of the other loop. The traditional solution to minimize the problem is to maximize the difference between time constants governing the amplitude and phase/frequency locking loops. Basically, the amplitude loop should be slowed down by using large component values, such as huge capacitors, which consumes more area and power than desired. Still, the system should be overdesigned to have enough margin to accommodate not only the environmental variables, but also component values especially for large time constants. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein: 
     FIG. 1 is a schematic block diagram of a conventional charge pump PLL with amplitude control; 
     FIG. 2 is a schematic block diagram of a gm-C based relaxation-type oscillator; 
     FIG. 3 is a schematic diagram of an exemplary circuit structure that may be used for a transconductance (gm) stage; 
     FIG. 4 is a schematic diagram of an exemplary circuit structure that may be used to provide a negative resistance; 
     FIG. 5 is a schematic diagram of an exemplary circuit structure that may be used for a gm stage loaded with C t  and net negative resistance; 
     FIG. 6 is a schematic block diagram for modeling the behavior of the conventional charge pump PLL of FIG. 1; 
     FIG. 7 is a schematic block diagram for modeling the behavior of a modified charge pump PLL circuit in accord with a first exemplary implementation of the present invention; and 
     FIG. 8 is a schematic block diagram for modeling the behavior of a modified charge pump PLL circuit in accord with a second exemplary implementation of the present invention. 
    
    
     DETAILED DESCRIPTION 
     A conventional charge pump based PLL system  10  that includes amplitude control is depicted in FIG.  1 . PLL system  10  comprises an amplitude control loop  12  and a phase/frequency control loop  14  that provide a pair of input signals to a current-controlled oscillator (ICO)  16  that is common to both control loops. As will be understood by those skilled in the art, although two separate lines corresponding to an amplitude output signal  17  (A out ) and a frequency output signal  18  (F out ) are shown in FIG. 1, A out  and F out  represent components of a single composite signal that is output by ICO  16 . Amplitude control loop  12  includes a peak detector/comparator  19 , an amplitude loop filter  20 , a voltage-to-current converter  22 , and current-controlled oscillator (ICO)  16 . Phase/frequency control loop  14  includes a phase detector  24 , a charge pump  26 , a frequency loop filter  28 , a voltage-to-current converter  30 , ICO  16 , and an optional frequency divider  32 . If frequency divider  32  is used, frequency output signal  18  becomes frequency output signal  18 ′ after its frequency is divided. 
     Amplitude control loop  12  works in the following manner. The loop receives an amplitude reference signal  34  that is compared to amplitude output signal  17  of the loop by peak detector/comparator  19 . Peak detector/comparator  19  produces a current output signal  38  based on a difference in the amplitude of amplitude reference single  34  and amplitude output signal  17 , which is then filtered by amplitude loop filter  20  through means of passive filter elements C 1  and R 1  to produce an amplitude control voltage  40 . Amplitude control voltage  40  is then fed into voltage-to-current converter  22 , which outputs an amplitude control current  42  that provides an input to ICO  16  to produce amplitude output signal  17 . 
     Phase/frequency control loop  14  works in a similar manner. The loop receives a frequency reference input signal  44  that is compared with frequency output signal  18 ′ in phase detector  24 . Phase detector  24  outputs a pair of control signals  48  and  50  that are fed into charge pump  26 , which pumps a current  52  that is proportional to the phase difference between signal  44  and  18 ′. Then current  52  is filtered by phase/frequency loop filter  28  through means of passive elements C 2 , C 3 , and R 2  to produce a frequency control voltage  54 . Frequency control voltage  54  is then fed into voltage-to-current converter  30 , which outputs a frequency control current signal  56  that drives ICO  16 . 
     Different architectures can be used to realize the amplitude and phase/frequency controls in PLLs. Depending on the variables that change frequency and amplitude of the oscillation, there might be less interaction, but nevertheless, it is very unlikely to eliminate the coupling entirely, especially for the jitter requirements of recent PLL systems. 
     With reference to FIG. 2, a gm (transconductance)-C based relaxation type oscillator  60  is depicted that might typically be used as a low-cost current controlled oscillator (ICO) in the circuitry shown in FIG.  1 . Gm-C oscillator  60  comprises two cascaded gm stages that provide a 180 degree phase shift, including a first gm stage  62  and a second gm stage  64 . The output of second gm stage  64  is then inverted, as depicted by an inverter block  66 , and fed back as the input of first gm stage  62 . Gm-C oscillator  60  further comprises a first stage frequency current source  68 , a first stage capacitor C t1 , a first stage negative resistance  70 , a first stage amplitude current source  72 , a second stage frequency current source  74 , a second stage capacitor C t2 , a second stage negative resistance  76 , and a second stage amplitude current source  78 . Negative resistances  70  and  76  are included at the output of each stage to compensate for the output conductance losses. Circuit structures associated with the gm stage and negative resistance are illustrated in FIGS. 3 and 4, respectively, further details of which are provided below. 
     In the ideal case, the output signal frequency F out  would be directly controlled by the frequency control current I freq , such that, 
     
       
           F   out =( I   freq )  (1) 
       
     
     and the output signal amplitude A out  would be directly controlled by the amplitude control current I amp , such that, 
     
       
           A   out =( I   amp )  (2). 
       
     
     However, as discussed above, the control of one parameter adversely affects the control of the other parameter, such that, 
     
       
           F   out =( I   freq )+( I   amp )  (3) 
       
     
     and 
     
       
           A   out =( I   amp )+( I   freq )  (4). 
       
     
     This occurs due to the following interactions. In the phase/frequency loop, the tail currents (I freq ) of the gm stages that drive the oscillation can be used to change the transconductance of the stages. As a first order relation, frequency of oscillation depends on gm/C t  where C t  is the total capacitance at the output of the gm stage. Negative resistance at the output of each gm stage can be realized by implementing a cross-coupled pair, such as shown in FIG.  4  and described in further detail below. Tail current (I amp ) of the cross-coupled pair adjusts (V gs −V t ) of the transistors, which makes the cross-coupled pair. This parameter (V gs −V t ) limits the oscillation amplitude. On the other hand, (V gs −V t ) affects the average transconductance of the gm stage within a single oscillation cycle because the gm stage exhibits a limited region of linearity. As the amplitude of oscillation reaches the linearity boundaries, the instantaneous gm decreases, vanishes, and then starts to increase with opposite polarity to pursue the other phase of the oscillation cycle. Accordingly, I amp  interferes into the phase/frequency loop. In general, an increase in amplitude decreases the frequency. Furthermore, I freq  contributes to amplitude changes through the dependency of output conductance of a MOS transistor on its channel current. As output conductance varies due to I freq , it adversely affects the amplitude loop. The relative strength of these interactions depends heavily on loop bandwidths, operating points, and basic transistor parameters such as gm, gds, and (V gs −V t ), all of which typically are changing dynamically. 
     This cross coupling between the loops can introduce right half plane poles into the PLL system given the dynamic nature of loop variables. In the present invention, I amp  is inserted into phase/frequency control loop  14  to cancel the coupling path coming from amplitude control loop  12 . The basic idea can be formulated as follows; 
     
       
           out =( I   freq )+( I   amp )  (5) 
       
     
     Instead, one can utilize; 
     
       
           out =( I   freq   +kI   amp )+ I   amp )≈( I   freq )  (6) 
       
     
     Even though the cancellation may not be complete, it gives the flexibility to accommodate a larger range of variations to the system to reduce the complexity of overdesign. 
     An exemplary circuit structure  80  that may be used for a typical gm stage is shown in FIG.  3 . Current for driving circuit structure  80  is provided by a “Vdd” supply  81 , which supplies current to the sources of a pair of PMOS transistors  82  and  84 , the drains of which are connected to the drains of respective NMOS transistors  86  and  88 . The sources of NMOS transistors  86  and  88  are commonly tied to the high side of a current source  89  (corresponding to first and second stage frequency current sources  68 ,  74 ), which is tied to a ground  90 . A “Pbias” signal  92  is provided to the gates of each of PMOS transistors  82  and  84  and is maintained at a voltage level such that both PMOS transistors  82  and  84  are saturated throughout the oscillations of the circuit. As a result, PMOS transistors behave as if they were pull-up resistors to Vdd, which may be substituted in place of the PMOS transistors in an optional configuration. If PMOS transistors are used, the circuit is referred to as a source-coupled pair with PMOS loads. In general, a source-coupled pair with resistive loads may also be used. 
     The behaviors of NMOS transistors  86  and  88  are controlled by a pair of complimented control signals, including an “in” signal  94  and an inb(bar) signal  96 , which are provided to the gates of NMOS transistors  86  and  88 , respectively. In addition, circuit structure  80  provides a pair of complimented output signals “out”  98  and “outb”  100  between the PMOS and NMOS transistors on opposing branches of the circuit. With respect to the circuit of FIG. 2, “in” signal  94  corresponds to input signals  102  and  104 , which are respectively received by first and second stages  62  and  64 , while “out” signal  98  corresponds the outputs of the respective stages, labeled  106  and  108 . Additionally, “outd”  101  represents the differential voltage across complimented output signals “out”  98  and “outb”  100 . 
     An exemplary circuit structure  110  comprising a cross-coupled pair with PMOS or resistive loads that may be used for negative resistances  70  and  76  is shown in FIG.  4 . This circuit structure is substantially similar to circuit structure  80  of FIG. 3, and includes a Vdd supply  112 , PMOS transistors  114  and  116 , each of which is provided with a “Pbias” signal  118  at their respective gates, and NMOS transistors  120  and  122 . The sources of NMOS transistors  120  and  122  are commonly tied to the high side of a current source  124  (e.g., amplitude control current sources  72  and  78  of FIG. 3) that is tied to a ground  126 . Furthermore, PMOS transistors  114  and  116  behave in a similar manner to the PMOS transistors of circuit structure  80 , wherein Pbias signal  118  is set at a voltage such that the PMOS transistors are continuously saturated and behave as resistors. Accordingly, as with the circuit structure  80 , pull-up resistors may be substituted in place of the PMOS transistors. 
     A primary difference between circuit structures  80  and  110  is how the NMOS transistors are controlled. As depicted in FIG. 4, the control signals for NMOS transistors  120  and  122  are respectively provided by complimented gm stage output signals “out”  121  and “outb”  126 , which cross across the opposing branches of the circuit structure, to form the cross coupled pair. Similar to circuit  80 , the differential voltage across complimented output signals “out”  121  and “outb”  126  corresponds to an “outd” signal  127 . 
     An exemplary circuit  130  that may be used in implementing the present invention that provides the gm stage loaded with C t  and net negative resistance through combining circuits that produce positive and negative gms is shown in FIG.  5 . Circuit  130  includes a gm stage  132 , preferably comprising circuitry in accord with circuit structure  80  of FIG.  3 . Gm stage  132  receives a pair of complimented input signals “in”  134  and “inb”  136 , and produces a pair of complimented output signals “out”  138  and “outb”  140 . A capacitor C t  is tied across the complimented output signals. The output signals are used to drive a source-coupled diode connected pair with PMOS loads circuit  142  and a cross-coupled pair with PMOS loads circuit  144 . 
     Circuit  142  comprises a pair of PMOS transistors  146  and  148 , and n pairs of NMOS transistors  150  and  152 . Similarly, circuit  144  comprises a pair of PMOS transistors  154  and  156  and m pairs of NMOS transistors  158  and  160 . The sources of each of the PMOS transistors is commonly tied to a Vdd supply  162 , while the sources of NMOS transistors  150  and  152  are connected to the high side of an amplitude control current source  164  and the sources of NMOS transistors  158  and  160  are tied to the high side of an amplitude control current source  166 . Each of current sources  164  and  166  provide substantially the same current are tied to a common ground  168 . In addition, a Pbias signal  170  is provided to the gates of each of PMOS transistors  146 ,  148 ,  154  and  156  such that each of these PMOS transistors is saturated and behaves as a resistor. As with the foregoing circuits, the PMOS transistors may be replaced with pull-up resistors. 
     Note the difference in how NMOS transistors  150 ,  152  of circuit  142  are connected when compared with NMOS transistors  158 ,  160  of circuit  144 . In circuit  142 , the NMOS transistors are diode connected, wherein the drain of each transistor is tied to the gate of the transistor. In contrast, the drains of NMOS transistors  158  and  160  are tied to gates of the opposite transistor on a pair-wise basis, such that the drain of transistor  158  is tied to the gate of transistor  160 , and the drain of transistor  160  is tied to the gate of transistor  158 . Accordingly, circuit  144  is a cross-coupled circuit comprising m pairs of cross-coupled NMOS transistors. 
     It is noted that there respectively are n and m sets of NMOS transistors for circuits  142  and  144 . The reason for this is to have a net negative gm depending on relative differences rather than absolute values, which makes variations less severe over process, temperature, and supply voltages. 
     Suppose that all of the NMOS transistors have substantially the same characteristics. Therefore, as depicted in FIG. 5, circuit  142  produces a positive gm that is a function of n, the number of pairs of transistors  150  and  152 , while circuit  144  produces a negative gm that is a function of m, the number of pairs of transistors  158  and  160 . The overall effect, identified as the NET gm, will be negative if the following condition is met: 
     
       
           NET gm=( n−m )gm&lt;0 for  m&gt;n   (7) 
       
     
     Accordingly, the scaling factor can be adjusted by varying the values for n and m. Optionally, the scaling factors can be adjusted by simply adjusting the length and/or width of the NMOS transistors. 
     Block diagrams that model the behavior of the foregoing circuitry are shown in FIGS. 6 and 7. The block diagram of FIG. 6 models the phase/frequency (the upper) and amplitude (the lower) control loops and the cross-coupling between the loops in accord with the conventional PLL circuitry of FIG.  1 . The phase/frequency control loop model includes a summing block  170 , a phase detector block  172 , a loop filter block  174 , a voltage-to-current converter gm block  176 , a current-to-frequency transfer function block  178 , a summing block  180 , and an integration block  182 . The phase/frequency control loop may optionally include a frequency divider, modeled by a divide-by-n block  184 . 
     The amplitude control loop model includes a summing block  186 , a loop filter block  188 , a voltage-to-current converter block  190 , a current-to-amplitude transfer function block  192 , and a summing block  194 . In addition to the respective blocks of each loop, the cross coupling between the loops is modeled using a parasitic amplitude-to-frequency gain (kv ap ) block  198  and a parasitic frequency-to-amplitude gain (kv pa ) block  200 . kv ap  and kv pa  are modeled as negative gains (i.e., the “−” marks near summing blocks  180  and  194 ) since an increase in either the frequency or the amplitude generally decreases the other. 
     The behavior of the conventional PLL circuit can be modeled using the following equations.                  Z   F1          (   s   )       =         s        (       R   1          C   1       )       +   1           s   2          (       R   1          C   1          C   2       )       +     s        (       C   1     +     C   2       )                   (   8   )                   Z   F2          (   s   )       =       K   const           s        (     c   gm     )       peak     +   1               (   9   )                 θ   0     =       1   s          [         kv   pp          I   c1       -       kv   ap          I   c2         ]               (   10   )                 A   0     =         kv   aa          I   c2       -       kv   pa          I   c1                 (   11   )                 I   c1     =       (         I   p       2                 π            gm   p            Z   F1          (   s   )         )          (       θ   i     -       θ   0     N       )               (   12   )                 I   c2     =       (       gm   a            Z   F2          (   x   )         )          (       A   1     -     A   0       )               (   13   )                                
     θ 0  can be determined by plugging equations (12) and (13) into equation (10). In rearranged form, the resulting equation is,                  θ   0          [           1   +         kv   pp          I   p          gm   p            Z   F1          (   s   )           2      π                 Ns                   (     F   00     )           ]       =                    +     [               kv   pp          I   p          gm   p            Z   F1          (   s   )           2                 π                 s                 (     F   01     )           ]            θ   i       -                                  [               kv   ap          gm   a            Z   F2          (   s   )         s               (     F   10     )           ]          A   i       +                                [               kv   ap          gm   a            Z   F2          (   s   )         s               (     -     F   11       )           ]          A   0                                    
     or, 
     
       
           F   00 θ 0   +F   11   A   0   =F   01 θ i   +F   10   A   i   (14) 
       
     
     A 0  can be determined by plugging equations (12) and (13) into equation (11). In rearranged form, the resulting equation is,                  A   0          [           1   +       kv   aa          gm   a            Z   F2          (   s   )                     (     H   00     )           ]       =                    +     [               kv   aa          gm   a            Z   F2          (   s   )                      s                 (     H   01     )           ]            A   i       -                                  [               kv   pa          I   p          gm   p            Z   F1          (   s   )           2      π                 (     H   10     )           ]          θ   i       +                                [               kv   pa          I   p          gm   p            Z   F1          (   s   )           2                 π                 N                 (     -     H   11       )           ]          θ   0                                    
     or, 
     
       
           H   00   A   o   +H   11 θ 0   =H   01   A   i   +H   10 θ i   (15) 
       
     
     Combining equations (14) and (15) in a linear algebraic matrix equation form yields,                    [           F   00           F   11               H   11           H   00           ]          [           θ   0               A   0           ]       =         [           F   01           F   10               H   10           H   01           ]          [           θ   i               A   i           ]                     or       ,           (   16   )                 [           θ   0               A   0           ]     =           1         F   00          H   00       -       F   11          H   11                [           H   00           -     F   11                 -     H   11             F   00           ]            [           F   01           F   10               H   10           H   01           ]            [           θ   i               A   i           ]                                                
     It is desired to minimize the coupling between the phase/frequency and amplitude control loops. As shown in FIG. 7, this can be accomplished by adding KI C2  to I C1 , as indicated by a K scale factor block  202 , a connection line  204 , and a summing block  206 . The overall effect is that the parasitic gain from the amplitude control loop to the phase/frequency control loop is substantially canceled out. The appropriate value for K can be determined from the following modified equations, wherein (I c1 +KI c2 ) has been substituted for I c1  in equations 10-11 and 14-16.               θ   0     =         1   s          [         kv   pp          (       I   c1     +     KI   c2       )       -       kv   ap          I   c2         ]       =       1   s          [         kv   pp          I   c1       +       (       Kkv   pp     -     kv   ap       )          I   c2         ]                 (     10   ′     )                 A   0     =           kv   aa          I   c2       -       kv   pa          (       I   c1     +     KI   c2       )         =         (       kv   aa     -     Kkv   pa       )          I   c2       +       kv   pa          I   c1                   (     11   ′     )                 I   c1     =       (         I   p       2                 π            gm   p            Z   F1          (   s   )         )          (       θ   i     -       θ   0     N       )                     (     REMAINS                 THE                 SAME     )               (   12   )                 I   c2     =       (       gm   a            Z   F2          (   s   )         )          (       A   1     -     A   0       )                     (     REMAINS                 THE                 SAME     )               (   13   )                                
     It turns out that kv pp  and kv ap  are of the same order. From equation 10′, it would be desirable to have (Kkv pp −kv ap =0) to eliminate the cross-coupling effect. However, testing has revealed that the effect of kv pa  is insignificant, i.e., kv pa &lt;&lt;kv aa . Alternatively, if it is desired not to ignore the effect of kv pa , the appropriate equation is (K′kv aa −kv pa =0). This can be modeled by adding a second “K”′ scale factor block  208  disposed along a connection  210  that connects I c1  to I c2  through a summing block  212 , as shown in FIG.  8 . In this instance, the foregoing equations 10-16 would be solved by replacing I c2  with I c2 +K′I c1 . 
     If the effects of kv pa  are ignored, the matrix equations become,                F   10   ′     =         F   10          (       kv   ap     -     Kkv   pp       )         kv   ap               (   17   )                 F   11   ′     =         F   11          (       kv   ap     -     Kkv   pp       )         kv   ap               (   18   )                 H   00   ′     =       [       (       H   00     -   1     )            (       kv   aa     -     Kkv   pa       )       kv   aa         ]     +   1             (   19   )                 H   01   ′     =         H   01          (       kv   aa     -     Kkv   pa       )         kv   aa               (   20   )                 [           θ   0               A   0           ]     =           1         F   00          H   00   ′       -       F   11   ′          H   11                [           H   00   ′           -     F   11   ′                 -     H   11             F   00           ]            [           F   01           F   10   ′               H   10           H   01   ′           ]            [           θ   i               A   i           ]               (     16   ′     )                                
     As discussed above, by adjusting the value of K relative to the values of kv aa  and kv pa  (i.e., such that Kkv pp −kV ap ≈0), the parasitic coupling effect of the amplitude loop onto the phase/frequency loop can be substantially eliminated. As a result, control of the amplitude and phase/frequency control loops are decoupled, enabling the frequency to be controlled independently of the amplitude. 
     The above description of illustrated embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. Accordingly, it is not intended that the scope of the invention in any way be limited by the above description, but instead be determined entirely by reference to the claims that follow.