Abstract:
A system and method for allowing a user to create instructions for building a packet processing integrated circuit. The system includes a user interface for allowing a user to define a desired packet processing algorithm ( 4 ) using a plurality of discrete packet processing blocks ( 22, 24, 28, 30 ), each of the blocks corresponding to a portion of the desired packet processing algorithm ( 4 ). The system allows the user to define connections ( 10 ) between the plurality of packet processing blocks ( 22, 24, 28, 30 ). The system processes a plurality of packet processing blocks ( 22, 24, 28, 30 ) and the connections to provide a list of instructions in a hardware description language for producing an integrated circuit capable of executing the desired packet processing algorithm ( 19 ). The list of instructions can be delivered to a customer ( 12 ), or the customer can receive an integrated circuit constructed using the list of instructions ( 19 ), or the customer can receive a NETLIST generated using said list of instructions ( 16 ). The plurality of packet processing blocks ( 22, 24, 28, 30 ) can include a Packet Processing Unit (PPU, PPUX)  22 , a Packet Modification Unit (PMU)  28 , and a Decision and Forwarding Unit (DFU)  30.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to digital component design and implementation systems and, more particularly, to a system and method for designing and implementing packet processing products. 
   2. Related Art 
   Computer-based communications are dominated by the transmission of packets of data. Typically, a packet contains a payload, i.e., a portion of an overall data message, surrounded by a number of header bits or bytes, that are used to insure that the payload is transmitted and received without error. The header bits or bytes can be divided into a number of fields designating commands, responses, packet characteristics, etc. The fields can take on one or more values depending on the particular protocol used. Some protocols are custom-designed, while others, such as asynchronous transfer mode (ATM) or Transmission Control Protocol/Internet Protocol (TCP/IP), are standardized. For any type of protocol, there is a need to extract and examine the header bits or bytes to make decisions as to how to classify a type of packet, where to route the packet, and whether to drop or temporarily store (queue) the packet for future processing. The header must be parsed, bits or bytes examined or processed, and then routing decisions must be made. 
   Various hardware and software products have, in the past, been developed for designing and implementing products for processing and classifying data packets. In one approach, parsing, decision, and routing functions are implemented in software modules executed by the host processor and memory of the receiving computer. Processing large amounts of data in real time is often slow, since doing so puts a strain on processor resources. A second approach is to use a specialized microprocessor and associated hardware, called a network processing unit (NPU). The NPU provides a programmable interface for programming nearly any type of protocol functionality. However, the ability to program nearly every aspect of a transmission packet protocol burdens an NPU with a large amount of functionality, rendering an NPU both expensive and slow (low data rates). Also, the time needed for a developer to program an NPU may take several hours to days, which can be cost prohibitive. Another approach is to design a customized application specific integrated circuit (ASIC). This approach often wastes large numbers of gates to achieve only limited functionality, and is thus not cost effective. As such, there is a lack of an adequate system or methodology for designing and implementing packet parsing and classification products, wherein such products can be designed and implemented. 
   Accordingly, what would be desirable, but has not yet been provided, is a system and method for designing and implementing packet processing products which addresses the foregoing limitations. 
   SUMMARY OF THE INVENTION 
   The present invention relates to a system and method for designing and implementing packet processing products, wherein a user can create instructions for building a packet processing integrated circuit. The system includes a user interface for allowing a user to define a desired packet processing algorithm by defining a plurality of discrete, packet processing blocks, each of the blocks corresponding to a portion of the desired packet processing algorithm, as well as connections between the plurality of packet processing blocks. The system processes the plurality of packet processing blocks and the connections to provide a list of instructions in a hardware description language for producing an integrated circuit capable of executing the desired packet processing algorithm. The list of instructions can be delivered to a customer, or the customer can be provided with an integrated circuit constructed using the list of instructions. The customer can also be provided with a NETLIST generated using said list of instructions. 
   The packet processing blocks of the present invention include a Packet Processing Unit (PPU), a Packet Modification Unit (PMU), and a Decision and Forwarding Unit (DFU). The PPU includes functionality for extracting a header of a packet; for pointing to a portion of the header of a predetermined width using a predetermined index of a bit location in the header; for comparing the data represented by the portion of the header with at least one predetermined value; and for declaring a match when the result of the comparison is true. A variation of a PPU, called a PPUX, includes functionality for accessing an external Content-Addressable Memory (CAM) or Random-Access Memory (RAM). The PMU includes functionality for extracting a packet; pointing to a portion of the packet of a predetermined width using a predetermined index of a bit location in the packet; and modifying the portion of the packet. A packet can be modified in one of three ways: deletion, insertion, or overwriting a portion of the packet. The DFU can perform one of drop, queue, and forwarding operations on packets coming from at least one PPU, PPUX, or PMU. The PPU, PPUX, PMU, and DFU can be programmed by an external microprocessor. 
   Further features and advantages of the invention will appear more clearly on a reading of the detailed description of an exemplary embodiment of the invention, which is given below by way of example only with reference to the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention, reference is made to the following detailed description of an exemplary embodiment considered in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a flowchart showing a process according to the present invention for designing a packet processing product; 
       FIG. 2A  is a screen shot of a window in a graphical user interface (GUI) according to the present invention for choosing a type of packet processing block to be configured; 
       FIG. 2B  is a screen shot of a window in a graphical user interface (GUI) for selecting configuration parameters for generating a Packet Processing Unit (PPU) of the present invention; 
       FIG. 2C  is a screen shot of a window in a graphical user interface (GUI) for selecting configuration parameters for generating a Packet Modification Unit (PMU) of the present invention; 
       FIG. 2D  is a screen shot of a window in a graphical user interface (GUI) according to the present invention for selecting configuration parameters for generating a Decision and Forwarding Unit (DFU) of the present invention; 
       FIG. 3  is a block diagram of a plurality of packet processing blocks according to the present invention for designing a packet processing product; 
       FIG. 4  is a block diagram showing, in greater detail, a Packet Parsing Unit (PPU) of the present invention; 
       FIG. 5  is a block diagram showing, in greater detail, a Packet Parsing Unit with an external interface to a CAM/RAM (PPUX) of the present invention; 
       FIG. 6  is a block diagram showing, in greater detail, a Packet Modification Unit (PMU) of the present invention; 
       FIG. 7  is a block diagram showing, in greater detail, the Decision and Forwarding Unit (DFU) of the present invention; and 
       FIG. 8  is a block diagram showing a sample packet processor design for determining the queuing precedence of a VLAN/non-VLAN frame. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Referring to  FIG. 1 , a process according to the present invention for designing packet processing products is shown. The present invention allows a user to design packet processing products using a high-level programming language which generates a NETLIST for generating a hardware design specification of a digital circuit. A NETLIST describes the connectivity of an electronic design. The design process begins at step  1 , wherein a set of user requirements and specifications are received, which may be in the form of a packet parsing architecture or a packet parsing and classification algorithm. Typically, these requirements are in the form of a text description of the system to be generated. At step  2 , the description is translated by the user or provider into a textual or graphical design using packet processing blocks which include Packet Parsing Units (PPU), Packet Parsing Units with an external interface to a CAM/RAM (PPUX), Packet Modification Units (PMU), and Decision and Forwarding Units (DFU), which will be described hereinbelow with reference to  FIGS. 3-7 . 
   As an example of step  2 , if the customer needs a firewall that accepts TCP packets and rejects UDP packets, then three PPUs and one DFU are required. One of the PPUs is devoted to determining a source IP address; a second PPU is devoted to extracting a destination IP address; and a third PPU is devoted to distinguishing between TCP and UDP packets. The three PPUs are connected in parallel (since the information can be extracted simultaneously from the same packet), and the “match” outputs of the PPUs (to be described with reference to  FIG. 4 ) and a source packet is forwarded to a DFU. Once the source and destination addresses are extracted from the packet and the type of packet is extracted, the DFU takes each match input and the packet and makes a decision: If the packet is a TCP packet and the source and destination addresses are allowed, then the packet is passed on, otherwise the packet is to be dropped. Thus, in step  2 , the user can select the required number and combination of packet processing blocks to be used in the design. 
   At step  3 , the packet processing block requirements, including their required inputs and outputs, are entered into a connection document, which can be a text based EXCEL™ spreadsheet or a VISIO™ block diagram. Typical inputs to the connection document include entries for each PPU and DFU block, which may include an index representing the point of entry into a packet to be processed, and whether a lookup in an internal table of data in a PPU is required. 
   Once the connection document has been completed, then, at step  4 , packet processing blocks, e.g., each PPU and DFU, can be configured. Configuring a packet processing block involves taking a “default” packet processing block file, such as a generic PPU or DFU file, and modifying portions of it and setting variables within each file. Code for the packet processing blocks to be described in  FIGS. 4-7  (written in pseudo-code) can be found in Appendices A-E and G-L attached hereto. In particular, the pseudo-code for the PPU calls code found in the following appendices: a file for describing a generic header extraction block called a Hardware Lookup Unit (HLU) (see Appendices D and K), and a file for describing a generic Match/Lookup Unit (MLU) (see Appendices E and L). Both the HLU and MLU will be described hereinbelow as part of the description of the PPU. The packet processing blocks are implemented in a hardware design language (HDL) which models digital circuits, with gates, flip flops, counters, and other logic in a C-like software language. In some implementations, the “pruning” process can be performed by manually copying and editing a maximally configured processing block file, or by applying a preprocessor in the form of shell scripts to cull code from and substitute variables within a maximally configured processing block files. Preprocessing shell scripts, as is known in the art, can include textual or graphically-based user prompts for answering questions about specific parameters desired by the user for a particular block. 
     FIGS. 2A-2D  show one possible example of graphical user interface (GUI) which can be used to enter parameters for packet processing blocks. A Main generation GUI window  13  is presented to the user, as shown in  FIG. 2A . One of a number of radio buttons  13  is selected by the user to indicate the type of processing block to be configured. Depending on the processing block chosen, a configuration window  15  is displayed, one for each type of processing block (i.e., PPU/PPUX (see  FIG. 2B ); PMU (see  FIG. 2C ); and DFU (see  FIG. 2D )). Each configuration window  15  contains a field  16  for naming the processing block. A series of configuration screen elements  17  are presented to the user for allowing parameters of each processing block to be specified by the user (including, e.g., data bus width, start of packet width, end of packet width, maximum header words, qualifier width, result width, result expression, external memory parameters, number of interfaces, etc.), and which may vary according each type of processing block. Finally, the user can click on either a “Generate” button  18  to cause the particular processing block code to be generated, or a “Cancel” button  19 . 
   The GUI code can pass the input parameters to a preprocessor, such as a preprocessor called “veriloop2.” The pseudo-code for veriloop 2  can be found in Appendix F. Veriloop 2  first performs substitutions into appropriate variables using the parameters passed from the GUI. Veriloop 2  then searches for constructs such as name-value pairs, conditional constructs, and loops having a particular syntax, and then culls the maximally configured packet processing block file to produce a preprocessed header-like library files, each containing a function or class representing a particular PPU, DFU, etc. Pseudo code for types of preprocessor constructs can be found in Appendix G. Pseudo code for sample pre-processed files of  FIG. 8  can be found in Appendices H-L. Note that there is only one PPU/MLU/HLU file for all three PPUs, which share the same number of inputs/outputs and share the same general structure. The number of PPUs that need to be generated depends upon the degree of parallelism needed for a particular design. If all the operations for a number of PPUs can be performed in series, then one PPU is needed, since all that changes between instances of PPUs is the input parameters (e.g. opcode, mask, etc.). There is one generated PPU for each parallel operation. There are separate DFU Appendices (i.e., Appendices B, H, and I because each DFU can have a different number of inputs/outputs). 
   The present invention distils the implementation of maximally configured processing blocks into common sub-blocks which have unique names (e.g., PPU_ 1 , DFU_ 2 ) or modules which have inputs and outputs that can be interconnected in such a way as to perform all of the functions necessary for implementing a desired packet processing product. The common blocks described herein are preferably instantiations of packet processing blocks written in VHDL, Verilog, or System C, but other suitable hardware description languages can be used. The software implementation of packet processing blocks is platform independent, and can be written in a platform independent language such as JAVA. As such, packet parser/classifier functionality of the present invention can run both in Windows and in different versions of the Unix operating system, as well as others. In a GUI, the programmer/designer can invoke instances of these common modules using a C-like application programming interface (API) surrounded by other C-like code for interconnecting the sub-blocks. 
   At step  5 , integration is performed. Integration involves declaring instantiations of each processing block by name, and making connections between instantiated packet parsing blocks in a top-level main program file (the top-level main program file is similar to the file containing the main( ) function call in C language). These connections are called “wires” or “signals” which are declared like variables, and associations are made between two processing block instances which have a common wire. For example, signal “x” in PPU 1  ties to signal “y” in the top level file. Signal “z” of DFU 1  also ties to signal “y” in the top level file. In this way, signal “x” of PPU 1  is tied to Signal “z” of DFU 1  which may also be tied to one or more other signals. Certain input parameters can also be “hard-coded” within the top-level file. 
   At this point, all source HDL code has been generated which together can constitute a fully designed product. At step  6 , if the customer desires only the design, then at step  7 , the generated packet processing block files and the top level file can be delivered to the customer. If the customer desires to have a NETLIST, then at step  8 , the generated files are run through a commercially-available synthesis tool, as is known in the art. Sample synthesis tools include Design Compiler from Synopsis, Precision Synthesis from Mentor Graphics, Sinplify from Synplicity, or XST from Xilinx. The synthesis tool behaves like an optimizing compiler which produces a NETLIST for producing an electrical schematic for a custom integrated circuit which is implemented with a minimum number of logic gates, flip-flops, counters, etc. The type of NETLIST generated depends on whether the customer desires to have a foundry-specific device, e.g. a Xilinx FPGA or a generic (“virtual”) NETLIST which is not specific to a particular vendor&#39;s product. Customers which are EDA (electronic design automation) vendors desire a non-specific NETLIST. The NETLIST could be a foundry-specific or “virtual” bitstream or binary file that is delivered to customer. 
   At step  9 , if the customer does not desire to have a digital integrated circuit delivered to them, then at step  10 , the NETLIST is delivered to the customer, otherwise, at step  11 , the NETLIST is run through a place and route program, which physically constructs the gates defined in the NETLIST on a silicon die and interconnects them. The choice of a place and route tool depends on whether the packet parser/classifier is to be implemented as an ASIC (fixed logic) or an FPGA (programmable logic). Sample place and route programs include Quartus II from Altera and ISE from Xilinx. At step  12 , the integrated circuit is delivered to the customer. 
   With reference to  FIG. 3 , a block diagram of a graphical design environment using packet processing blocks according to the present invention for designing a packet processing product, indicated generally at  20 , is depicted. The blocks  20  can be implemented in a text-based or graphical design environment. The environment  20  includes combinations of any number of Packet Parsing Units (PPUs)  22 , PPUXs  24  (which are PPUs that can access CAM/RAM memory  26 ), Packet Modification Units (PMUs)  28 , and Decision and Forwarding Units (DFUs)  30 . The PPUs  22 , PPUXs  24 , PMUs  28 , and DFUs  30  can be connected by a designer in a variety of ways to create parsing/classification logic for any desired packet processing algorithm. The PPUs  22  operate on packet headers  21 . The packet itself can be passed through the environment  20  intact. Alternatively, only the packet header  21  is passed through the environment, which requires the creation and passing of a pointer to the packet data to be output after the DFUs  30 . The packets are stored in memory upon arrival and retrieved from memory upon departure. A copy of the header  21  and a pointer to the packet location is passed to the development environment  20 . The length of the copied header  21  is variable. It starts at a programmable position in the header  21  and ends at the last field that must be processed. A PPU takes a header  21  and can seek, i.e., locate, any field of constant or variable length. Once the field is found in the header  21 , the PPU  22  can perform a check on that field, such as whether the field is equal to or greater than a given value, or matches a particular value, and then output that value depending on the operation performed. 
   PPUXs  24  are PPUs that can perform lookups or searches using external random-access memories (RAMs) or CAMs (a CAM is defined as a RAM-like memory which can determine whether an input value is present in the memory device). A PMU  28  is a PPU which allows fields in the header of a packet or the packet itself to be modified by means of insertions, deletions, or substitution of bytes. In contrast, the PPUs  22  and PPUXs  24  only allow the fields of a packet header to be examined. Any number of PPUs  22 , PPUXs  24 , and PMUs  28  can be chained together in series or in parallel to implement complex expressions. The DFUs  30  combine the output of one or more PPUs  22  and/or PPUXs  24  and/or PMUs  28  using a programmable condition, and then forward the header to one of a plurality of outputs. The outputs can represent Boolean True and False values, and decisions as to whether to drop, forward, or queue the packet. The DFUs  30  make decisions to forward, drop, or enqueue packets based on the results from the PPUs  22 . For example, the output of the last DFU in the chain, such as the DFU labeled “A”, can be a queue ID, i.e. of the queue implemented in an external traffic manager  31 . 
   The traffic manager  31  is a device which performs a set of actions and operations for a network to guarantee the operability of the network. Traffic Management (TM) is exercised in the form of traffic control and flow control. In the context of the present invention, the traffic manager  31  operates on a packet stream once the classification &amp; processing is done on a packet (i.e. once it passes from PPU/DFU blocks). For example, PPU/DFU blocks are used to figure out the priority number of a packet. The traffic manager is given that priority number and the packet to do a traffic control operation to guarantee that high priority packets pass before low priority packets. 
   With reference to  FIG. 4 , a block diagram of the PPU  22  is depicted. The PPU  22  performs basic parsing of the packet header  21  and may perform mathematical/logical operations on the parsed fields of packet header  21 . The PPU  22  includes a plurality of inputs and outputs  32 - 83 . The function of each input and output  32 - 83 , as well as the values that each input or output handle, are described with reference to Table 1 hereinbelow. 
   
     
       
             
             
             
             
           
         
             
               TABLE 1 
             
             
                 
             
             
                 
               Ref. # 
               Type 
                 
             
             
                 
               In 
               (In = Input; 
             
             
               Signal 
               FIG. 4 
               Out = Output) 
               Description 
             
             
                 
             
           
           
             
               Clk 
               32 
               In 
               Clock input 
             
             
               Rst 
               34 
               In 
               Asynchronous reset (Active high) 
             
             
               DataIn 
               36 
               In 
               Packet header data input 
             
             
               SOHIn 
               38 
               In 
               Start of header input (Active High) 
             
             
               EOHIn 
               40 
               In 
               End of header input (Active High) 
             
             
               InVal 
               42 
               In 
               Data In valid indication (Active High) 
             
             
               DataOut 
               44 
               Out 
               Packet header output 
             
             
               SOHOut 
               46 
               Out 
               Start of header output (Active High) 
             
             
               EOHOut 
               48 
               Out 
               End of header output (Active High) 
             
             
               OutVal 
               50 
               Out 
               Data Out valid output (Active High) 
             
             
               Qual/Enb 
               52 
               In 
               Qualifier/Enable input that is checked using the 
             
             
                 
                 
                 
               Qualifier Condition 54 below to enable the PPU 
             
             
                 
                 
                 
               22 on a packet by packet basis. The Qual/Enb 
             
             
                 
                 
                 
               52 can be the Result 70 from a previous PPU. 
             
             
               QualCond 
               54 
               In 
               Qualifier Condition: The PPU operation is 
             
             
                 
                 
                 
               enabled if the result of the check of the 
             
             
                 
                 
                 
               Qual/Enb input 52 using the Qualifier condition 
             
             
                 
                 
                 
               54 is true. The Qualifier Condition 54 can be: 
             
             
                 
                 
                 
               Always True, Equal, Less Than, Less Than or 
             
             
                 
                 
                 
               Equal, Greater Than, Greater Than or Equal, 
             
             
                 
                 
                 
               etc.) 
             
             
               Index 
               56 
               In 
               Index that points to a byte position in the header 
             
             
                 
                 
                 
               relative to the start of packet. The first byte in 
             
             
                 
                 
                 
               the header has an Index of 0. 
             
             
               Width 
               58 
               In 
               Width of the field to be operated on 
             
             
               Mask 
               60 
               In 
               The Mask value is ANDed with the data to be 
             
             
                 
                 
                 
               operated on. This allows checking of only 
             
             
                 
                 
                 
               certain bits in a data field 
             
             
               Opcode 
               62 
               In 
               The Opcode specified the operation to be 
             
             
                 
                 
                 
               performed. The opcodes are: 
             
             
                 
                 
                 
               EQ: Equal to Param1 64 
             
             
                 
                 
                 
               LT: Less Than Param1 64 
             
             
                 
                 
                 
               LE: Less Than or Equal to Param1 64 
             
             
                 
                 
                 
               GT: Greater Than Param1 64 
             
             
                 
                 
                 
               GE: Greater Than or Equal to Param1 64 
             
             
                 
                 
                 
               RNG: Check if within range &lt;Param1 64, 
             
             
                 
                 
                 
               Param2 66&gt; 
             
             
                 
                 
                 
               LUP: Look up 
             
             
                 
                 
                 
               SPCL: Special programmable expression 
             
             
                 
                 
                 
               which can use PARAM1 64, PARAM2 
             
             
                 
                 
                 
               66, four special purpose registers 
             
             
                 
                 
                 
               provisioned in PPU 12, Index 56, Width 
             
             
                 
                 
                 
               58, and Qualifier/Condition 54. 
             
             
               Param1 
               64 
               In 
               Most opcodes use the parameter Param1 
             
             
               Param2 
               66 
               In 
               The RNG opcode uses Param2 to indicate the 
             
             
                 
                 
                 
               end of the range 
             
             
               Match 
               68 
               Out 
               Match is asserted (high) if the result of the 
             
             
                 
                 
                 
               operation is true 
             
             
               Result 
               70 
               Out 
               The Result output is controlled by a logical or 
             
             
                 
                 
                 
               arithmetic expression on any of the inputs. For 
             
             
                 
                 
                 
               example, to output a Result that drives the 
             
             
                 
                 
                 
               Index input 56 of the next PPU so that it points 
             
             
                 
                 
                 
               to a data field that is 2 bytes ahead: 
             
             
                 
                 
                 
               Result = Index + 2 
             
             
               ResVal 
               72 
               Out 
               Indication that Result 70 is valid 
             
             
               SeqOut 
               74 
               Out 
               Sequence number used for synchronization 
             
             
                 
                 
                 
               between PPUs and a DFU. This value 
             
             
                 
                 
                 
               increments every packet 
             
             
               MapWrRd_n 
               76 
               In 
               Map write enable is used to program internal 
             
             
                 
                 
                 
               registers. Active high is writing, active low for 
             
             
                 
                 
                 
               reading 
             
             
               MapAddr 
               78 
               In 
               16 Address locations are provisioned for 
             
             
                 
                 
                 
               following usage 
             
             
                 
                 
                 
               0x0 = PPU ID 
             
             
                 
                 
                 
               0x1 = Qualifier enable condition value 
             
             
                 
                 
                 
               0x2 = Address to program internal Lookup table 
             
             
                 
                 
                 
               0x3 = Data to program internal Lookup table 
             
             
                 
                 
                 
               (Note: The address needs to be written first 
             
             
                 
                 
                 
               followed by data) 
             
             
                 
                 
                 
               0x4-0x7: Used for special purpose registers 
             
             
                 
                 
                 
               which can be used in any equation for the 
             
             
                 
                 
                 
               special Operation code 
             
             
                 
                 
                 
               0x8-0xF: For future use 
             
             
               MapWrData 
               80 
               In 
               Write data for the PPU map 
             
             
               MapRdData 
               81 
               Out 
               Read back data from the PPU map 
             
             
               SeqIn 
               82 
               In 
               An optional externally defined sequence 
             
             
                 
                 
                 
               number. This may be used in place of an 
             
             
                 
                 
                 
               internally generated sequence number for a 
             
             
                 
                 
                 
               PPU. 
             
             
               TAG 
               83 
               In 
               An optional user defined label to be associated 
             
             
                 
                 
                 
               with the packet header 
             
             
                 
             
           
        
       
     
   
   The terms in brackets in  FIG. 4  accompanying a specific input or output represents the bit width of the input or output, in standard HDL syntax. For example, if the input DataIn  36  is to be 32 bits wide, then the variable DW is set to 32 such that DataIn  36  is expressed in an HDL file as “DataIn[DW-1:0]=DataIn[32-1:0]=DataIn[31:0]”, where “31” represents the last bit and “0” represents the first bit. 
   The input Clk  32  is supplied from external hardware, such as the clock of a microprocessor. The Input Rst  34  is used to cause the PPU to go into a pre-defined state where most internal variables and outputs are set to an initial value. This condition is usually needed at power-up of the hardware in logic systems to stabilize the system before execution of a packet processing algorithm. The system is initially Reset. A predetermined amount of time later, when it is known that all circuits have stabilized, then the circuit is put into operation by toggling Rst  34 . 
   The PPU  22  includes a Hardware Lookup Unit (HLU)  84 , a Delay/FIFO module  86  containing an optional Delay Line  88  or a FIFO  90 , a Match and Lookup Unit (MLU)  92 , Result Generation (process)  94 , Sequence Generation (process)  96 , an Output Alignment (process)  98 , interconnected as shown. The sub-blocks  84 - 98  are implemented as modules or processes. A module is similar to a class or subclass in an object-oriented language like C++, while a process is similar to a function. The PPU also contains (not shown) a predetermined but limited number of internal general-purpose registers for storing and retrieving values for comparisons, lookups, etc. 
   A stream of data is continuously presented to the input DataIn  36  of the HLU  84 . No data of the input stream is stored in a memory. In such circumstances, it is the job of the HLU  84  to extract information from a packet and present that information to the other blocks of the PPU  22 . The HLU  84  takes a snapshot of the data stream according to the location in the data stream specified by the inputs Index  56  and Width  58 . The inputs SOHIn  38 , EOHIn  40 , and InVal  42  allow for fine tuning of locating data from the output of other PPUs, PPUXs, PMUs, or external hardware. SOHIn  38 , EOHIn  40 , and InVal  42  tell the PPU  22  how to delimit data a packet header. SOHIn  38  tells the hardware where packet starts and EOHIn  40  tells the hardware when a packet header ends. Once the packet starts, then at every clock cycle, the data presented at DataIn  36  is either valid or invalid, as indicated by the input InVal  42 . The extracted header bits are present as an output CompDat  100  and as an input to the MLU  92 . CompDat  100  stands for the data that needs to be compared in the MLU  92 . 
   The Delay/FIFO module  86  is used to synchronize the outputs of the PPU  22  to be presented to a subsequent block, such as a DFU. The Delay/FIFO module  86  is needed because the inputs to the PPU, such as DataIn  36 , along with the control input signals SOHIn  38 , EOHIn  40 , and InVal  42 , need to be aligned in time in the Output Alignment process  98  with intermediate outputs of other sub-blocks of the PPU  22 , such as the Match output  110  of the MLU  92 , which may be delayed relative to the inputs due to delays in processing within the MLU  92 . The MLU  92  performs its decision making (e.g., a comparison of a bit within DataIn  36  with a user specified parameter (Param 1 )) without full packet storage. Therefore, DataIn  36  along with the control input signals SOHIn  38 , EOHIn  40 , and InVal  42  are pipelined to the Result Generation process  94  and the Output Alignment process  98  by way of intermediate I/O Val_i  102 , SOH_i  104 , EOH_i  106 , and Data_i  108 . There are fixed delays (measured in clock cycles) associated with processing in the in Result Generation process  94  and the MLU  92 . There is a variable delay associated with the HLU  84  depending upon value of Index  56 . The inputs described above must be delayed in the Output Alignment process  98  by the sum of the aforementioned individual delays. For example, if Index  56  is  8 , then CompDat  100  is received at the MLU  92  eight clock cycles after DataIn  36  arrives at the PPU  22 . If the MLU  92  processes CompDat  100  in three clock cycles, then the PPU  22  inputs need to be delayed by 8+3 clock cycles in the Output Alignment process  98 . The choice of the optional Delay Line  88  or the FIFO  90  depends on the size of the delay needed. A FIFO always works but requires using scarce memory in the PPU  22 . Thus, if only a few clock cycles worth of delay up to about  16  clock cycles are needed, then the Delay Line  88  is used, otherwise the FIFO  90  is used. 
   The MLU  92  performs the bulk of the packet parsing and classification operation to be performed on one unit of a packet processing algorithm. The MLU  92  is programmable, i.e., it can compare the data/fields extracted in the HLU  84  with values stored in internal registers by means of the inputs Opcode  62 , Param 1   64 , Param 2   66 , and Mask  68  and declares a match or no match which appears on the internal output Match  110 , which, in turn, appears as an output of the Result Generation process  94 . The inputs QualEnb  52  and QualCond  54  enable or disable the MLU  92  depending on certain conditions. The operation to be performed in the MLU  92  are enabled if the result of the check of the QualEnb  52  using the QualCond  54  is true. QualEnb  52  is a value stored in a qualEnb register (not shown) which is user programmable through an address map. The Qualifier Condition  44  can be: Always True, Equal, Less Than, Less Than or Equal, Greater Than, Greater Than or Equal, etc. 
   For example, if the user desires only to allow IPV6 packets, then QualEnb  52  can be programmed through the qualEnb register (not shown) to be the value 6. QualCond  54  is set to Equal To (EQ). The packet type is retrieved from a mode register from an external CPU. If the packet type is 6 (IPV6), then the MLU  92  is enabled; if the packet type is 4 (IPV4), then the MLU  92  is disabled, and no comparison takes place. If it is desired to have all types of IP packets, then QualCond  54  is set to Less Than or Equal (LE) or Always True. 
   The match/no-match functionality of the MLU  92  is performed on the portion of the DataIn  36  packet header pointed to by Index  56  and Width  58 . Additional inputs Mask  60 , Opcode input  62 , Param 1   64 , and optionally Param 2   66  are needed to perform the comparison/match/no-match operation. The MLU  92  performs a seek and operation function. 
   The seek function finds a data field in a packet header (not shown) based on an offset from the start of the packet header indicated by the input Index  56 . If Index  56  is 0, then the first byte of the packet header is indicated. An Index  56  of six indicates the seventh byte from the beginning of the packet header. The interconnections that can be made to the Index input  56  include a fixed value (e.g. 4), a value stored in an internal user defined control register, or the result output  70  of another PPU, PMU, or DFU. If the Index input  56  is driven from another PPU, PMU, or DFU, the value placed on the Index input  56  is variable, depending on the condition(s) evaluated in the previous PPU, PMU, or DFU. 
   The operation function performs a check, an extraction, or a lookup on “Data_Field”, which is the contents of the packet header pointed to by the Index input  56  of width equal to the value in bits placed on the Width input  58 . The general expression of the operation is
 
Op(Data_Field AND Mask, Param1, Param2)
 
The Data_Field may be filtered (AND&#39;ed) with the Mask input  60 . “Op” is one of the opcodes placed on the Opcode input  62  given the Param 1  input  64 , and optionally the Param 2  input  66 . The types of operations are shown in Table 2 below:
 
   
     
       
             
             
             
           
         
             
               TABLE 2 
             
             
                 
             
             
               Mnemonic 
               Parameters 
               Description 
             
             
                 
             
           
           
             
               EQ 
               Param1 
               Equal: Check if the Data field is equal to 
             
             
                 
                 
               Param1. 
             
             
               LT 
               Param1 
               Less Than 
             
             
               LE 
               Param1 
               Less Than or Equal 
             
             
               GT 
               Param1 
               Greater Than 
             
             
               GE 
               Param1 
               Greater Than or Equal 
             
             
               RNG 
               Param1, 
               In Range between Param1 and Param2 
             
             
                 
               Param2 
             
             
               LUP 
               — 
               Look Up 
             
             
               SP 
               — 
               Search: or special operation for a PPU using 
             
             
                 
                 
               PARAM1, PARAM2, four Special purpose 
             
             
                 
                 
               registers provisioned in PPU, Index, Width &amp; 
             
             
                 
                 
               Qualifier. 
             
             
                 
             
           
        
       
     
   
   For example, a single MLU can be programmed to check if an IP address less than 224.XX.XX.XX, by specifying the following values:
         Opcode=LT   Param 1 =224   Index=Points to IP DA or SA and can be adjusted automatically for VLAN tagging using a PPU.       

   As another example, to point to the beginning of an Ethernet frame payload for both untagged and VLAN tagged frames:
         Index=14 (Type/Length)   Opcode: EQ   Param 1 : 0×8100   QualCond=True   Match (True): Index=20   Match (False): Index=16       

   The inputs MapWrRd_n  76 , MapAddr  78 , and MapWrData  80 , and the output MapRdData  81  are used as the interface between an external microprocessor and the internal registers of the PPU  22  to allow for reading of and writing to the registers. The PPU  22 , PPUX  24 , PMU  28 , and DFU  30  can contain a user defined number of internal registers for packet header manipulation either internally or via an external microprocessor. The opcodes LUP and SPCL can be used to directly manipulate data in internal registers. 
   The output Match  110  of the MLU  92  is fed to the input of the Result Generation process  94  to be described hereinbelow. The Match output  110  is True if the operation performed in the MLU  92  is True, or False otherwise. The Result Generation process  94  takes the Match output  110 , the outputs of the Delay/FIFO module  86 , and optionally a tag value present on TAG  83  and produces the result output iResult  112 , which is fed as an input to the Output Alignment process  98  and ultimately is the output Result  70  of the PPU  22 . The Result Generation process  94  also outputs iResVal  114 , which indicates when iResult  112  is valid. This is needed as a handshaking device, since result generation can take more than a single clock cycle. iMatch  116  is the value of Match  110  passed along from the MLU  92 . Assuming the MLU  92  was enabled, iResult  112  can take on two values corresponding to the True or False evaluation of the operation performed in the MLU  92 . The True/False result values can be fixed or an arithmetic or logical function of any of the PPU  22  inputs. The iResult output  112  is later passed through the Output Alignment process  98  to be described hereinbelow as Result  70 , which can be used to drive a DFU input or any input of another PPU or a PMU. Result  70  can also be a complex expression that the user may want to program. This allows the Index  56 , QualEnb  52 , Opcode  62 , or Param&lt; 1 , 2 &gt;  64 ,  66  inputs of a PPU to be driven with different values depending on the Result  70  output of other PPUs. 
   The PPU  22  generates or forwards a sequence number using the Sequence Generation process  96 . The sequence number can optionally come from an external process/hardware via the input SeqIn  82  and passed along to a DFU; otherwise sequence numbers are internally generated within a PPU  22  using the Sequence Generation process  96 . The sequence number, which appears as an internal output iSeq  118 , is passed through the Output Alignment process  98  to a DFU through the PPU output SeqOut  74 . Sequence numbers are incremented sequentially for each use of a PPU and are used for internal synchronization of all the inputs of a DFU. Sequence numbers are needed because different PPUs can present their output packet header data, match data, and results at different times. For example, one PPU may index at bit  0  of an incoming packet, in which case match output may appear at an input to a DFU after three clock cycles. If another PPU indexes on a VLAN type field, then index is set to block  5  or  6 , which gives its results to the same DFU after 6+3 clock cycles. The DFU takes the matches packet headers, and sequence number from each of the PPUs and arranges them in correct sequence to be described hereinafter. 
   The Output Alignment process  98  aligns all outputs to the start of packet (SOP) or the end of packet (EOP). This is done in order to provide proper delineation of the output signals of one PPU to the next PPU/PPUX/PMU/DFU. For example, if PPU 1  is connected to PPU 2 , and PPU 1  operates either on an 802.3 Ethernet frame or an Ethernet type 2 frame, then PPU 1  examines a byte field which is either 20 bytes or 40 bytes from the beginning of a packet header. Therefore, all outputs of PPU 1  need to be aligned on SOP as a requirement for input to PPU 2 . As another example, some protocols use trailer insertion, e.g., inserting a checksum at the end of a packet. Therefore, outputs are aligned at EOP. 
   With reference to  FIG. 5 , a block diagram of a PPUX  24  is depicted. A PPUX  24  has the same I/O signals and sub-blocks as the PPU  22  except for additional I/O needed to access an external CAM/RAM  220 . Elements illustrated in  FIG. 5  which correspond to the elements described above in connection with the PPU  22  of  FIG. 5  have been identified by corresponding reference numbers increased by one hundred. Unless otherwise indicated, both the PPU  22  and the PPUX  24  have the same construction and operation. 
   In a PPU, as mentioned earlier, there is a predetermined number of internal registers/memory which can be programmed by a user. A typical need for programmed memory is for performing a lookup of values by MLU  192 . For example, if there is a need to compare Param 1   164  to one hundred IP addresses, then internal memory is used. However, if the number of lookups and hence values to be stored in memory is on the order of thousands of bytes or more, then it may be necessary to store and retrieve these values to/from an external CAM/RAM  220 . 
   
     
       
             
             
             
             
           
         
             
               TABLE 3 
             
             
                 
             
             
                 
                 
               Type 
                 
             
             
                 
               Ref. # 
               (In = Input; 
             
             
               Signal 
               in FIG. 5 
               Out = Output) 
               Description 
             
             
                 
             
           
           
             
               XRdAddr 
               222 
               Out 
               Memory address output 
             
             
               XRdEnb 
               224 
               Out 
               Read signal (Active High) 
             
             
               XRdData 
               226 
               In 
               Read data from memory 
             
             
               XRdVal 
               228 
               In 
               Read data valid input 
             
             
                 
                 
                 
               (Active High) 
             
             
                 
             
           
        
       
     
   
   With reference to  FIG. 6 , a block diagram of a Packet Modification Units (PMU)  28  is depicted. A PMU allows for modification, i.e., insertion, deletion, or replacement, of bytes in a packet, including both the header and payload data. The PMU  28  includes a Delay/FIFO module  300  containing an optional Delay Line  302  or a FIFO  304 , a Modification Unit (MU)  306 , a Result Generation process  308 , a Sequence Generation process  310 , and an Output Alignment process  312 , interconnected as shown. These sub-blocks  300 - 312  are implemented as software modules or processes. 
   The inputs InVal  314 , SOHIn  316 , EOHIn  318 , DataIn  320 , TagIn  322 , Rst  324 , and Clk  326  have the same functionality as is found in the PPU  22  and the PPUX  24 . The delay/FIFO module  300  can be used to synchronize the inputs InVal  314 , SOHIn  316 , EOHIn  318 , DataIn  320 , and TagIn  322  with the outputs of the Result Generation Process  308  and the outputs of the Modification Unit (MU)  306  as is done in the PPU  22 , but it also provides a second function: to delay incoming packet data by an amount equal to the number of bytes that may be inserted into a packet in the Modification Unit  306 . This delay is not needed for removing or overwriting data in a packet. As with the PPU  22 , the choice of the optional Delay Line  302  or the FIFO  304  depends on the size of the delay needed. If only a few clock cycles worth of delay (a few words to be inserted) are needed, then the Delay Line  302  is used, otherwise the FIFO  304  is used. As with the PPU  22 , InVal  314 , SOHIn  316 , EOHIn  318 , and DataIn  320  are pipelined to the a Modification Unit (MU)  306  as the intermediate outputs Val_i  328 , SOH_i  330 , EOH_i  332 , and Data_i  334 . 
   Val_i  328  is also directed to the Result Generation Process  308 . The Result Generation Process  308  has a different purpose from the one found in a PPU  22 . The intermediate outputs iResVal (result valid)  358  and iResult (the result)  360  are not based on a field value, but reflect the number of bytes inserted. Like a PPU  22 , iResult  360  becomes the output Result  378  which can be used as an input to another PPU/PPUX/PMU/DFU. It can also be a complex expression that the user may want to program. The Sequence Generation Process  310  with the optional SeqIn input  362  has the same functionality as in the PPU  22 . 
   The Modification Unit (MU)  306  inserts/modifies/removes data as specified by a user. The MU  306  is specified at preprocessing time as one of an inserting type, modifying type, or removing type PMU. The type of operations performed by the input signals ByteOffset  336 , ByteValid  338 , and ByteData  340  are shown in Table 4 below: 
   
     
       
             
             
             
             
           
         
             
               TABLE 4 
             
             
                 
             
             
                 
               Ref. # 
               Type 
                 
             
             
                 
               in 
               (In = Input; 
             
             
               Signal 
               FIG. 6 
               Out = Output) 
               Description 
             
             
                 
             
           
           
             
               ByteOffset 
               336 
               In 
               Byte Offset for insertion/deletion/ 
             
             
                 
                 
                 
               modification starting at zero bytes 
             
             
                 
                 
                 
               from the beginning of the packet 
             
             
               ByteValid 
               338 
               In 
               Valid (Active High) for the number 
             
             
                 
                 
                 
               of clock cycles needed to insert 
             
             
                 
                 
                 
               N bytes 
             
             
               ByteData 
               340 
               In 
               The N bytes of data to be inserted 
             
             
                 
                 
                 
               or overwritten (not used for 
             
             
                 
                 
                 
               deletion) 
             
             
                 
             
           
        
       
     
   
   The inputs MapWrRd_n  342 , MapAddr  344 , and MapWrData  346 , and the output MapRdData  348  provide a future programming interface for an external microprocessor to allow for the reading and writing from/to internal registers of the PMU  28  to, for example, dynamically program an MU to either insert, delete, or modify a packet at run time. Val_i  350 , SOH_i  352 , and EOH_i  354  are passed after a delay intact from their corresponding inputs to the MU  306  to the Output Alignment process  312 . The modified packet, represented as the intermediate input/output Data_i  356  is also presented to the Output Alignment process  312 . The Output Alignment process  312  has the same purpose and functionality as found in the PPU or PPUX, i.e., aligning all intermediate outputs iSeq  362 , iResVal  358 , iResult  360 , Vali_i  350 , SOH_i  352 , EOH_i  354  and Data_i  356  on either the start of packet (SOP) or the end of packet (EOP) to become the aligned outputs SeqOut  366 , OutVal  368 , SOHOut  370 , EOHOut  372 , DataOut  374 , ResVal  376 , Result  378 , and TagOut  380 . 
   With reference to  FIG. 7 , a block diagram of a Decision and Forwarding Unit (DFU)  30  is depicted. The DFU  30  performs drop, queue, or forward operations based on input from 1 to N PPUs, PPUXs, PMUs, or other DFUs. The DFU  30  includes a plurality of inputs and outputs  400 - 444 . The function of each input and output  400 - 444 , as well as the values each input or output can take on, are described with reference to Table 5 hereinbelow. 
   
     
       
             
             
             
             
           
         
             
               TABLE 5 
             
             
                 
             
             
                 
               Ref. # 
               Type 
                 
             
             
                 
               in 
               (In = Input; 
             
             
               Signal 
               FIG. 7 
               Out = Output) 
               Description 
             
             
                 
             
           
           
             
               RIn 
               400a-400n 
               In 
               Result from PPUs 0 to N − 1 
             
             
               MIn 
               402a-402n 
               In 
               Match from PPUs 0 to N − 1 
             
             
               RInSeq 
               404a-404n 
               In 
               Sequence Number from PPUs 0 to N − 1. The 
             
             
                 
                 
                 
               DFU matches the sequence number among 
             
             
                 
                 
                 
               all its input ports to ensure that it is operating 
             
             
                 
                 
                 
               on results for the same packet 
             
             
               RInVal 
               406a-406n 
               In 
               Result valid from PPUs 0 to N − 1 (Active High) 
             
             
               ROutAVal 
               408 
               Out 
               Result output port A valid (Active High) 
             
             
               ROutBVal 
               410 
               Out 
               Result output port B valid (Active High) 
             
             
               ROutDVal 
               412 
               Out 
               Result output port D valid (Active High) 
             
             
               ROut 
               414 
               Out 
               Result output. The result is based on the 
             
             
                 
                 
                 
               evaluation of a logical expression of the match 
             
             
                 
                 
                 
               and result inputs 
             
             
               SeqOut 
               416 
               Out 
               Sequence number output. This sequence 
             
             
                 
                 
                 
               number is output with the results 
             
             
                 
                 
                 
               corresponding to the input sequence number 
             
             
               DValIn 
               418a-418n 
               In 
               Data valid from PPUs 0 to N − 1 
             
             
               SOHIn 
               420a-420n 
               In 
               SOH from PPUs 0 to N − 1 
             
             
               EOHIn 
               422a-422n 
               In 
               EOH from PPUs 0 to N − 1 
             
             
               DataIn 
               424a-424n 
               In 
               Data from PPUs 0 to N − 1 
             
             
               DValOut 
               426 
               Out 
               Data valid output 
             
             
               SOHOut 
               428 
               Out 
               SOH output 
             
             
               EOHOut 
               430 
               Out 
               EOH output 
             
             
               DOut 
               432 
               Out 
               data output 
             
             
               MapWrRd_n 
               434 
               In 
               Map read/write enable is used to program 
             
             
                 
                 
                 
               internal registers. Active high is writing, active 
             
             
                 
                 
                 
               low for reading. 
             
             
               MapAddr 
               436 
               In 
               16 Address locations are provisioned for 
             
             
                 
                 
                 
               following usage 
             
             
                 
                 
                 
               0X0 = DFU ID 
             
             
                 
                 
                 
               0x1-0xF: For future use 
             
             
               MapWrData 
               438 
               In 
               Write data for the DFU map 
             
             
               MapRdData 
               440 
               Out 
               Read back data from the DFU map 
             
             
               Clk 
               442 
               In 
               Clock input 
             
             
               Rst 
               444 
               In 
               Asynchronous reset (Active high) 
             
             
                 
             
           
        
       
     
   
   Referring again to  FIG. 7 , the DFU  30  includes sub-blocks Latch  445   a - 445   n , Data Selection MUX  446 , Result Generation process  448 , and Output Alignment process  450 . The triangles within  FIG. 7  are for blocking together intermediate outputs and do not themselves have inherent functionality. All sub-blocks are processes. Latch  445   a - 445   n  latches the incoming results, data, and other output signals coming from 0 to N-1 PPUs/PPUXs/PMUs to be processed at a later time inside the DFU  30 . The Latch  445   a - 445   n  are necessary since each PPU/PPUX/PMU may present packet data at different times. Four signals from each Latch  445   a - 545   n , namely iDValIn  452   a - 552   n , iSOH  454   a - 554   n , iEOH  456   a - 456   n , and iData  458   a - 458   n , corresponding to the latched inputs DValIn  418   a - 418   n , SOH  420   a - 420   n , EOH  422   a - 422   n , and Data  424   a - 424   n , respectively, and representing together data signals from each PPU/PPUX/PMU, belong to groups, which are fed together to the Data Selection MUX  446 . Likewise, four signals from each Latch  445   a - 445   n , namely iRInVal  459   a - 459   n , iMln  460   a - 460   n , iRIn  462   a - 462   n , and iRInSeq  464   a - 464   n  corresponding to the latched inputs RInVal  406   a - 406   n , MIn  402   a - 402   n , RIn  400   a - 400   n , and RInSeq  404   a - 404   n , respectively, and representing together control/result signals from each PPU/PPUX/PMU, belong to groups, which are fed together to the Result Generation process MUX  448 . The Data Selection MUX  446  selects one of the sets of N-1 data groups and forwards the data group to the output group which includes iDValOut  466 , iSOHOut  468 , iEOHOut  470 , and iDOut  472  as inputs to the Output Alignment Process  450 . The Result Generation Process  448  has a similar purpose to that found in the PPU/PPUX, namely, generating a result iRout  482  which depends on the evaluation of a programmable logical expression which may depend on the value of the inputs RIn[0−(N-1)]  400   a - 400   n  and/or Min [0−(N-1)]  402   a - 402   n . In addition, the evaluation of this complex logical expression can determine an output port to which the packet is to be routed, i.e., the pass along/queue outputs A and B, or the drop port D, represented as active high enabling intermediate outputs iROutAVal  476 , iROutBVal  478 , and iROutDVal  480 . These outputs are passed along to the Output Alignment Process  450 , which has the same purpose and function as the PPU  22 , PPUX  24 , and PMU  28 . The intermediate outputs  466 - 482  become the DFU outputs DValOut  426 , SOHOut  428 , EOHOut  430 , DOut  432 , SeqOut  416 , ROutAVal  408 , ROutBVal  410 , and ROutDVal  412 , and Rout  414 , respectively. 
   With the addition of a group of external AND gates and control outputs ROutAVal  408 , ROutBVal  410 , and ROutDVal  412 , the output DOut  432  is routed to one of three output ports: DOutA  484 , DOutB  486 , or DOutD  488 . Typically, DOutA  484  and DOutB  486  can be used for normal output and DOutD  478  can be used for dropping a packet (not shown). Alternatively, DOutD  488  can be used as a third routing output port. For the normal ports DOutA  484  and DOutB  486 , the packet is either forwarded to a destination, or another chain of PPUs/PPUXs/PMUs, or sent to a queue of a traffic manager. 
   As an example of the operation of the Data Selection MUX  446  and Result Generation process  448 , if the DFU  30  has two PPU inputs DIn[ 0 ] and DIn[ 1 ], and two match inputs Min[ 0 ] and Min[ 1 ], then the following conditions exist:
         Output packet to Port DOutA if MIn[ 0 ] is True and Min[ 1 ] is True;   Output packet to Port DOutB if MIn[ 0 ] is True and Min[ 1 ] is False; and   Output packet to Port DOutD if MIn[ 0 ] is False and Min[ 1 ] is False.       

   The design environment of the present invention can be connected to a set of internal PPU/PPUX/PMU/DFU registers and programmed through a microprocessor interface. The operations that the microprocessor would perform are reads and writes to/from the registers. Table 6 below shows a sample interface for a microprocessor manufactured by Freescale, Inc. (formerly Motorola): 
   
     
       
             
             
             
           
         
             
               TABLE 6 
             
             
                 
             
             
               Signal 
               Type 
               Description 
             
             
                 
             
           
           
             
               UP_CLK 
               In 
               Clock: This is the clock for the μP interface. 
             
             
               UP_CS 
               In 
               Chip Select: This active low signal enables the 
             
             
                 
                 
               core to respond to microprocessor cycles. 
             
             
               UP_RWn 
               In 
               Read/Write: Read (high)/Write (low) signal 
             
             
               UP_READY 
               Out 
               Ready: Active low signal asserted by the core 
             
             
                 
                 
               to indicate the successful transfer of read or 
             
             
                 
                 
               write data. 
             
             
               UP_A[15:0] 
               In 
               Address Bus: 16-bit address driven by the 
             
             
                 
                 
               microprocessor to address the core registers. 
             
             
               UP_D[15:0] 
               In/Out 
               Data Bus: Bi-directional 16-bit data 
             
             
               UP_IRQ 
               Out 
               Interrupt Request: Active low signal asserted 
             
             
                 
                 
               by the core to indicate that an event was 
             
             
                 
                 
               detected. 
             
             
                 
             
           
        
       
     
   
   The possible types of interconnections between DFUs and PPUs are numerous. Depending on the application, the control inputs of the PPUs or DFUs can be driven with fixed values (hardwired), from programmable registers, or from the outputs of other PPUs or DFUs. Table 7 shows the options for control signal connections, with some typical examples of standard packet processing: 
   
     
       
             
             
             
           
         
             
               TABLE 7 
             
             
                 
             
             
               PPU Control 
                 
                 
             
             
               Input 
               Connected To 
               Description/Functionality 
             
             
                 
             
           
           
             
               Qualifier 
               Fixed Value 
               PPU always enabled 
             
             
                 
               Register 
               Enable/disable under software control 
             
             
                 
               Other 
               Enable/disable conditionally depending on result from 
             
             
                 
               PPU/DFU 
               other PPU/DFU 
             
             
               Index 
               Fixed Value 
               Index is fixed. Example: MAC Destination or 
             
             
                 
                 
               Source Address 
             
             
                 
               Register 
               Index is software programmable 
             
             
                 
               Other 
               Index depends on result from other PPU/DFU. 
             
             
                 
               PPU/DFU 
               Example: IP Destination Address for untagged or VLAN 
             
             
                 
                 
               frames 
             
             
               Width 
               Fixed Value 
               Width is fixed. Example: MAC Destination or 
             
             
                 
                 
               Source Address 
             
             
                 
               Register 
               Width is software programmable 
             
             
                 
               Other 
               Width depends on result from other PPU/DFU. 
             
             
                 
               PPU/DFU 
               Example: IPv4 or IPv6 Address 
             
             
               Mask 
               Fixed Value 
               Mask value fixed or not used 
             
             
                 
               Register 
               Mask value is software programmable 
             
             
                 
               Other 
               Mask value depends on result from other 
             
             
                 
               PPU/DFU 
               PPU/DFU 
             
             
               Opcode 
               Fixed Value 
               Opcode is fixed. Example: Equal 
             
             
                 
               Register 
               Opcode is software programmable 
             
             
                 
               Other 
               Opcode changes depending on result from other 
             
             
                 
               PPU/DFU 
               PPU/DFU 
             
             
               Param&lt;1,2&gt; 
               Fixed Value 
               Parameter(s) value is fixed. Example: Check for fixed 
             
             
                 
                 
               MAC Address 
             
             
                 
               Register 
               Parameter(s) value is software programmable. 
             
             
                 
                 
               Example: Check for programmable MAC Address. 
             
             
                 
               Other 
               Parameter(s) value depends on result from other 
             
             
                 
               PPU/DFU 
               PPU/DFU. Example: Check TTL field in IP packet 
             
             
                 
             
           
        
       
     
   
   Each PPU/PPUX/PMU/DFU is configurable at synthesis time using the parameters shown in Table 8: 
   
     
       
             
             
             
           
         
             
               TABLE 8 
             
             
                 
             
             
               Parameter 
               Range 
               Description 
             
             
                 
             
           
           
             
               Data Width 
               8, 16, 
               Data bus width 
             
             
                 
               32, 64 
             
             
                 
               Bits 
             
             
               Qualifier Input 
               0-64 
               Qualifier input width See PPU 
             
             
               Width 
               Bits 
               interface description 
             
             
               Result Output 
               0-64 
               Result output width 
             
             
               Width 
               Bits 
             
             
               Max Header Size 
               1-1023 
               Maximum packet header size to be 
             
             
                 
               Bytes 
               processed 
             
             
               Max Internal 
               1-16K 
               Maximum length of internal lookup 
             
             
               Lookup Depth 
                 
               table (Note that very deep and wide 
             
             
                 
                 
               can consume a very large amount of 
             
             
                 
                 
               memory and may not be practical or 
             
             
                 
                 
               feasible) 
             
             
               Max Field Width 
               1-256 
               Maximum width field to be operated on 
             
             
               Max Internal 
               1-64 
               Sets the maximum lookup latency. 
             
             
               Lookup Latency 
                 
               The configuration tool uses this 
             
             
                 
                 
               parameter to determine the amount of 
             
             
                 
                 
               parallelism in the lookup. If a very 
             
             
                 
                 
               short latency is required, the search is 
             
             
                 
                 
               done more in parallel and consumes 
             
             
                 
                 
               more registers/flip-flops as opposed to 
             
             
                 
                 
               memory. 
             
             
               PPUX Address 
               1-32 
               PPUX external memory address width 
             
             
               Width 
             
             
               PPUX Data Width 
               1-64 
               PPUX external memory data width 
             
             
               Number of DFU 
               1-16 
               Each DFU can be fed by up to 16 
             
             
               Input Ports 
                 
               PPUs/PPUXs 
             
             
                 
             
           
        
       
     
   
   With reference to  FIG. 8 , a block diagram is depicted showing a sample packet processing algorithm design using the present invention. In this example, the packet processing algorithm relates to extracting the precedence field of an IP packet for a VLAN/Non-VLAN frame from a packet header  500  belonging to a packet  499 . Pseudo code which implements the two DFUs and the three PMUs of  FIG. 8  can be found in Appendix H-L. A top-level file for the example of  FIG. 8 , expressed in pseudo code, can be found in Appendix M. The precedence field is used as the QID of the queue into which the packet is to be stored in a traffic manager. The packet header  500  is fed to a DataIn input  502  of a PPU  504 . The PPU  504  determines first whether the inputted packet header  500  belongs to a virtual LAN (VLAN) frame or a non-VLAN frame by pointing to byte  12  of the header (Index=12) with a field width of 2 bytes. The operation to be performed is:
 
 EQ (Data_Field(byte 12, width 2) AND Mask=0 xFFFF , Param1=0 x 8100, Param2=0)
 
If packet header  500  points to a VLAN frame, then the Result output  506  of the PPU  504  is set to point to the location or offset in the packet header  500  of the IP address in a VLAN type frame, otherwise it points to the location in the packet header  500  of the IP address in a non-VLAN frame. This IP address is fed to the Index input  508 , along with the header  500  to a second PPU  510 . In the PPU  510 , the most significant byte is checked and must be less than  224 , signifying that the input IP address is valid. The operation to be performed is:
 
 GE (Data_Field(byte= MSB  of  IP  address, width=1) AND Mask=0 xFF , Param1=224, Param2=0)
 
   The packet header  500  is then passed to the Din[ 0 ] input  512  of a DFU  514 . If the DA field of the IP address is &gt;=224.0.0.0, then the packet is to be dropped by placing the header on the DOutD output  516  of an AND gate  518  connected to the DFU  514 . Otherwise, the packet  499  is forwarded to a third PPU  520  with the Index input  522  of the PPU  520  pointing to the “type of service” field (ToS) in the header  500  based on whether the packet  499  belongs to a VLAN or non-VLAN frame. The ToS tells the application how a datagram should be used, e.g. delay, precedence, reliability, minimum cost, throughput etc. Depending on the value of the ToS field, one can change a priority assigned to a packet which is then sent to a traffic manager which processes the packet based on the set priority. 
   In the PPU  520 , the IP precedence field is extracted from the header  500  with the following operation:
 
 EXTR (Data_Field(byte= ToS  field location, width=1) AND Mask=0 xFF , Param1=2 (start), Param2=3 (len))
 
   The IP precedence field is fed to the Din[ 0 ] input  524  of a second DFU  526 . The DFU  526  places the packet header on the DOutA output  528  of an AND gate  530  for queueing, and the precedence field is placed on the DOutB output  532  of an AND gate  534 . The precedence field functions as the Queue Identifier (QID) for the packet to be queued and both inputs  536 ,  538  are fed to a traffic manager  540 . The traffic manager  540  outputs the classified packet on output  542  and the QID on output  544 . 
   The present invention is subject to numerous variations and modifications. For example, the packet processing blocks having other types of functionality can be provided, such as:
         checksum or CRC generation and/or checking   packet content modification/editing   packet header removal   packet header or trailer addition (e.g., for downstream processing)   per flow rate control       

   As an alternative to a textual programming interface for implementing a given packet parser/classifier, the programmer/designer can use a graphical design program such as OrCAD or Microsoft Visio to draw and interconnect sub-blocks with input windows for entering interconnecting expressions and entering program inputs. 
   The present invention has several advantages over prior art packet processing products. The present invention can be used to produce an inexpensive piece of digital hardware, while the prior art products are limited to programs running on a microprocessor. The present invention is scalable to handle simple to complex classification tasks, and software modules can be connected and configured in a variety of ways. 
   It will be understood that the embodiment described herein is merely exemplary and that a person skilled in the art may make many variations and modifications without departing from the spirit and scope of the invention. All such variations and modifications are intended to be included within the scope of the present invention as defined in the appended claims.