Abstract:
A SerDes receiver device can receive binary signals via wireline channel such that information recovery is primarily or entirely performed via DSP algorithms in the digital domain includes an analog to digital converter, adaptation and calibration blocks, and a sequential n-way parallel equalization data path. The data path provides preliminary equalization of digital input symbols through a feed forward equalizer block followed by a decision feedback equalizer block, to which a k-slice decision feed forward equalizer block is appended for generating equalized hard decision outputs. The decision feed forward equalizer block may include a concatenation of cascading DFFE slices to improve the performance of the data path.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority under 35 U.S.C. §119(e) to provisional patent application U.S. Ser. No. 61/947,738 filed on Mar. 4, 2014. Said application is hereby incorporated by reference herein in its entirety. 
    
    
     TECHNICAL FIELD 
     This invention relates generally to data communications and particularly to method and apparatus for a high-speed, wire-line, digital serialization/deserialization (SerDes) receiver. 
     BACKGROUND 
     Architecture for serializer/deserializer (SerDes) receiver data path processing generally combines a front-end continuous-time linear equalizer (CTLE) and a decision feedback equalizer (DFE). These equalizing components are automatically adjusted using adaptive algorithms, e.g., least mean squares (LMS). For high-speed applications, data path equalization components are most often implemented as analog, transistor-level circuits while the adaptation is implemented via digital blocks. 
     An alternative method is to implement only an analog to digital converter (ADC) as an analog circuit, processing the received signal fully in the digital domain. A digital signal processing (DSP) data path of this nature offers technical potential for advanced DSP algorithms, expanding applications to extra long reach (XLR) channels or modulation schemes higher than non-return to zero (e.g., PAM-4). A digital receiver additionally has better reliability, testability and flexibility compared to its analog counterparts, and is easier to port across technology nodes. 
     There are at least two major technical challenges associated with building a DSP SerDes receiver: first, the technical feasibility of a high-speed, low-power ADC for digitizing a received analog signal, and second, lower clock speeds in the digital domain as opposed to analog alternatives. The former can be addressed by contemporary ADC architectures. The latter requires parallelization of hardware, which in turn creates its own set of challenges. It may be desirable to provide a primarily or fully digital SerDes receiver that provides high speed performance while minimizing the necessary area. 
     SUMMARY 
     Embodiments of the invention concern a proposed system for receiving binary signals via wireline channel such that information recovery is primarily or entirely performed via DSP algorithms in the digital domain, and a SerDes receiver implementing the proposed system architecture. Embodiments of the proposed receiver are designed to receive PAM-4 or NRZ/PAM-2 symbols at a data rate of 12.5 to 14 GS/s. In some embodiments, the system architecture includes an analog to digital converter (ADC) at the front end and a sequential 8-way parallel data path including a Feed Forward Equalizer (FFE) followed by a Decision Feedback Equalizer (DFE) followed by a Decision Feed Forward Equalizer (DFFE). The sequential combination of DFE and DFFE equalizers can provide high performance while minimizing the necessary area. Embodiments of the data path according to the invention can process eight digital samples of the signal per clock cycle at a frequency one-eighth times the transmitted symbol rate. In embodiments, the system architecture can further include a baud rate clock/data recovery (CDR) block with expanded gradient calculations (3-value sign+magnitude error signal) and an ADC calibration block. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the invention may be better understood by those skilled in the art by reference to the accompanying figures in which: 
         FIG. 1  is a block diagram of an embodiment of the invention; 
         FIG. 2  is a block diagram of an embodiment of a data path and its components according to the invention; 
         FIG. 3  is a block diagram of an embodiment of components of a data path including multiple DFFE slices according to the invention; and 
         FIG. 4  is a block diagram of a prior art feed forward equalizer. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  illustrates an embodiment of a FFE-DFE-DFFE data path  400  for a digital serializer/deserializer (SerDes) receiver device according to the invention. In embodiments of data path  400 , section  100  can include the essential minimum for a DSP SerDes receiver employing analog to digital converter (ADC)  110  and feed forward equalizer (FFE)  120 . Section  200  can append to section  100  a decision feedback equalizer (DFE) block  210 . For prior art combinations of a FFE-DFE data path to achieve a desired performance, a large number of FFE taps (e.g., 32) is required, which increases area proportionally and may adversely affect the filtered signal due to the large amount of fixed point arithmetic operations. The large size of a parallel DFE architecture restricts the DFE to at most 2 taps. 
     In embodiments of the invention, a DSP SerDes receiver can include a data path  400  that appends to a combination of FFE block  100  and DFE block  200  block  300 , including decision feed forward equalizer (DFFE  310 . In embodiments DFFE  310  can include a concatenation of a plurality of DFFE slices (ex.—cascading DFFE stages, elementary DFFE units). The performance of embodiments of DFFE  310  (ex.—probability of error) can then be adjusted through the concatenation of more or fewer DFFE slices or through DFFE analysis. In embodiments, a SerDes receiver device according to the invention can reduce the necessary number of taps used by FFE  120  to  8  or fewer due to the performance advantage realized by appending DFFE  310 . The total area required for embodiments of data path  400  can also be reduced as the added area required for appending DFFE  310  can be outweighed by the area saved in reducing the number of taps used by FFE  120 . 
     Embodiments of DSP SerDes equalization data path  400  can also include a high speed, low power analog to digital converter (ADC)  110  with phase interpolator and clock generator, adaptive filter (ex.—adaptation block)  140 , ADC calibration block  150 , and clock/data recovery (CDR) block  160 . In embodiments of data path  400 , the three n-way parallel filters are sequentially arranged: FFE  120  in block too, then DFE  210  in block  200 , then DFFE  310  in block  300 . Fully digital ADC calibration block  150  can measure parameters of the sampled analog signal and corrects offset or gain mismatches and clock errors inside ADC  110 . Adaptive filter  140  can automatically adjust coefficients for all three equalizing filters (e.g., c 0  . . . c n  for FFE  120 , h 1  . . . h k  for DFE  210 ) via least mean squares (LMS) or other adaptive algorithms. 
       FIG. 2  illustrates an embodiment of data path  400  in which decision feed forward equalizer (DFFE) block  300  includes a single DFFE slice. In embodiments, a DFFE slice can include combiner (ex.—subtractor)  318 , product block (ex.—multiplier)  314 , and decision devices (ex.—slicers, comparators)  312   a  and  312   b . In embodiments, DFFE slicer  312   a  can generate hard decision bits DFE; from input decision bits  212  generated by the DFE  210 . In embodiments, product block  314  can then multiply DFE; by a coefficient h i  generated by adaptive filter  140  of block too to approximate inter-symbol interference (ISI); this approximate ISI (DFE i ×h i ) can then be subtracted by combiner  318  from a latency-matched raw (ex.—non-filtered, non-equalized) digital input symbol  114  generated by ADC  110  to generate a final equalized output symbol and a hard decision DFFE i . In embodiments, latency matching block  316  can time-align input symbols  112  from ADC  110  to account for preliminary equalization (via FFE  120  and DFE  210 ) or hard decision generation (ex.—slicing), delivering latency-matched input symbols  114  from ADC  110  to combiner  318 . In embodiments, final output symbols generated by combiner  318  can then be received by decision device  312   b  for generation of hard decision bits DFFE 0  output by the DFFE slice of block  300 . 
       FIG. 3  illustrates an embodiment of data path  400  incorporating a k-slice cascading DFFE block  300  (where k is a positive integer). In embodiments, final hard decisions DFFE 0i  generated by decision device  312   b  and combiner  318   a  of slice n (o≦n&lt;k) can then be received as input by product block  314   b  of slice n+1, where DFFE 0i  is again multiplied by coefficient h i  to generate a subsequent product approximating ISI (DFFE 0i ×h i ). In embodiments, combiner  318   b  of slice n+1 can then subtract the subsequent product (DFFE 0i ×h i ) from a subsequent latency-matched input symbol  114   b  generated by ADC  110  (time-aligned for preliminary equalization as well as the components of previous DFFE slices 0, 1, . . . k−1. In embodiments, the resulting subsequent final output symbol can then be received by subsequent decision device  312   c  to generate hard decision bit DFFE 1i . In embodiments, subsequent decision bit DFFE 1i  can serve as data path output or as input for subsequent DFFE slices (as with previous hard decision bit DFFE 0i ). 
     In embodiments of the DSP receiver data path, DFE  210  can be an 8-way parallel, 2-tap, fully unrolled DFE and FFE  120  can be an 8-way parallel finite impulse response (FIR) filter with variable coefficients and as shown in  FIG. 4 . Timing closure constraints on maximum clock speeds at current technology nodes (28 nm through 16 nm) provide for parallelism of 8-way or higher. Embodiments of the invention, however, can accommodate any level of parallelism provided for by available technology or target system requirements. 
     Those having skill in the art will appreciate that there are various vehicles by which processes and/or systems and/or other technologies described herein can be effected (e.g., hardware, software, and/or firmware), and that the preferred vehicle will vary with the context in which the processes and/or systems and/or other technologies are deployed. For example, if an implementer determines that speed and accuracy are paramount, the implementer may opt for a mainly hardware and/or firmware vehicle; alternatively, if flexibility is paramount, the implementer may opt for a mainly software implementation; or, yet again alternatively, the implementer may opt for some combination of hardware, software, and/or firmware. Hence, there are several possible vehicles by which the processes and/or devices and/or other technologies described herein may be effected, none of which is inherently superior to the other in that any vehicle to be utilized is a choice dependent upon the context in which the vehicle will be deployed and the specific concerns (e.g., speed, flexibility, or predictability) of the implementer, any of which may vary. Those skilled in the art will recognize that optical aspects of implementations will typically employ optically-oriented hardware, software, and or firmware. 
     The herein described subject matter sometimes illustrates different components contained within, or connected with, different other components. It is to be understood that such depicted architectures are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “connected”, or “coupled”, to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being “couplable”, to each other to achieve the desired functionality. Specific examples of couplable include but are not limited to physically mateable and/or physically interacting components and/or wirelessly interactable and/or wirelessly interacting components and/or logically interacting and/or logically interactable components. 
     While particular aspects of the invention described herein have been shown and described, it will be apparent to those skilled in the art that, based upon the teachings herein, changes and modifications may be made without departing from the subject matter described herein and its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications as are within the true spirit and scope of the subject matter described herein.