Abstract:
A circuit structure is disclosed, wherein the circuit structure comprises: a substrate comprising a top surface, a bottom surface and lateral surfaces connecting the top surface and the bottom surface; a plurality of conductive layers disposed over the top surface of the substrate, wherein a dielectric layer is disposed between each two adjacent conductive layers, wherein at least one capacitor is formed by a first portion of the plurality of conductive layers with the dielectric layers therebetween, and wherein at least one first inductor is formed by a second portion of the plurality of conductive layers; and at least one conductive pattern layer disposed over at least one of the lateral surface to form at least one second inductor, wherein a third portion of the plurality of conductive layers electrically connects with said at least one capacitor, said at least one first inductor and said at least one second inductor.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
       [0001]    This application is a continuous application of U.S. application Ser. No. 13/251,183, filed on Oct. 2, 2011, which claims the priority benefit of China application serial No. 201010529025.2, filed on Oct. 25, 2010. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates to a filter, and in particular, to a filter circuit and a layout structure of the filter circuit fabricated by thin film technology. 
       BACKGROUND OF THE INVENTION 
       [0003]      FIG. 1  is a schematic circuit diagram of a conventional bandpass filter  100 . The conventional bandpass filter  100  comprises a capacitor C 1 , a capacitor C 2 , a capacitor C 3 , an inductor L 1  and an inductor L 2 . One terminal of the capacitor C 1 , the capacitor C 3  and the inductor L 1  are electrically connected to a first I/O (input/output) terminal TA of the filter  100 . One terminal of the capacitor C 2 , the other terminal of the capacitor C 3  and one terminal of the inductor L 2  are electrically connected to a I/O terminal TB of the filter  100 , wherein if the I/O terminal TA is an input terminal, the I/O terminal TB is an output terminal, or vice versa. The other terminal of the capacitor C 1 , C 2 , L 1  and L 2  are connected to a ground voltage GND. The conventional bandpass filter  100  is fabricated by LTCC (Low Temperature Co-Fired Ceramics). 
         [0004]      FIG. 2  is a frequency-response diagram of the circuit shown in  FIG. 1 . The filter  100  has a resonant frequency f 0  in the center of the passband, and there is a notch on the left-side band of f 0  (which means the range smaller than f 0 ) at the position about 1.9 GHz. The notch means that the filter  100  will cause larger attenuation at the frequency herein. It can be seen clearly from  FIG. 2  that the attenuation on the right-side band of f 0  (the range larger than f 0 ) is not as ideal as the attenuation on the left-side band of f 0 , but this frequency response is acceptable in some application conditions. However, due to some limitation of regulations, application environments or specification of products, the attenuation on the right-side band of the resonant frequency f 0  of the conventional bandpass filter  100  might not meet the requirement of them. For example, some regulations or specification of products require that the attenuation near a certain frequency (such as two times the resonant frequency, i.e. 2 f 0 ) on the right-side band of the resonant frequency f 0  should achieve a rated quantity (such as −35 dB), and it is thus very limited for the conventional bandpass filter  100  to apply. 
       SUMMARY OF THE INVENTION 
       [0005]    An object of this invention is to provide a filter and a layout structure of the filter to make a notch on the right-side band of the resonant frequency f 0  of the frequency response. 
         [0006]    One embodiment of the present invention provides a filter and a layout structure of the filter comprising a substrate, a first capacitor, a second capacitor, a third capacitor, a first inductor, a second inductor and a third inductor. The first, the second and the third capacitor and the first and the second inductor are disposed on the top surface of the substrate. A first electrode of the first capacitor and a first terminal of the first inductor are electrically connected to a first I/O terminal of the filter. A first electrode of the second capacitor and a first terminal of the second inductor are electrically connected to a second I/O terminal of the filter. The third capacitor is electrically connected between the first I/O terminal and the second I/O terminal of the filter. The third inductor is disposed on a first lateral surface of the substrate. A first terminal of the third inductor is electrically connected to second electrodes of the first and the second capacitors. 
         [0007]    One embodiment of the present invention provides a filter comprising a first capacitor, a second capacitor, a third capacitor, a first inductor, a second inductor and a third inductor. A first electrode of the first capacitor and a first terminal of the first inductor are electrically connected to a first I/O terminal of the filter. A first electrode of the second capacitor and a first terminal of the second inductor are electrically connected to a second I/O terminal of the filter. The third capacitor is electrically connected between the first and the second I/O terminals of the filter. A first terminal of the third inductor is electrically connected to second electrodes of the first and the second capacitors, and a second terminal of the third inductor is electrically connected to a reference voltage. 
         [0008]    Based on the above, thin film technology can be used to achieve the layout structure of the filter circuit according to the embodiment of the present invention so as to reduce costs. Moreover, the filter circuit provided according to the embodiment of the present invention has a notch on the right-side band of the resonant frequency f 0  of the frequency response. 
         [0009]    The detailed technology and above preferred embodiments implemented for the present invention are described in the following paragraphs accompanying the appended drawings for people skilled in this field to well appreciate the features of the claimed invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The foregoing aspects and many of the accompanying advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description when taken in conjunction with the accompanying drawings, wherein: 
           [0011]      FIG. 1  is a schematic circuit diagram of a conventional bandpass filter. 
           [0012]      FIG. 2  is a frequency response diagram of the circuit shown in  FIG. 1 . 
           [0013]      FIG. 3  is a schematic circuit diagram of a filter according to one embodiment of the present invention. 
           [0014]      FIG. 4  is a schematic circuit diagram of a filter according to another embodiment of the present invention. 
           [0015]      FIG. 5  is a frequency response diagram of the circuit shown in  FIG. 4 . 
           [0016]      FIG. 6  is a top view of a layout structure of the filter shown in  FIG. 4  according to the embodiment of the present invention. 
           [0017]      FIG. 7  is a perspective view of the layout structure shown in  FIG. 6 . 
           [0018]      FIG. 8  is an explosion diagram of the layout structure shown in  FIG. 7 . 
           [0019]      FIG. 9  is an equivalent circuit diagram of the layout structure shown in  FIG. 6 . 
           [0020]      FIG. 10  is a perspective view of parts of the layout structure of the filter shown in  FIG. 4  according to another embodiment of the present invention. 
           [0021]      FIG. 11  is a block diagram of a communication system according to one embodiment of the present invention. 
           [0022]      FIG. 12  is a frequency response diagram of the matching network shown in  FIG. 11 . 
           [0023]      FIG. 13  is a cross-sectional view of the filter shown in  FIG. 6  according to the embodiment of the present invention. 
           [0024]      FIG. 14  is a schematic circuit diagram of a filter according to yet another embodiment of the present invention. 
           [0025]      FIG. 15  is a perspective view of the layout structure of the filter shown in  FIG. 14  according to the embodiment of the present invention. 
           [0026]      FIG. 16  is an explosion diagram of the layout structure shown in  FIG. 15 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0027]    The detailed explanation of the present invention is described as following. The described preferred embodiments are presented for purposes of illustrations and descriptions, and they are not intended to limit the scope of the present invention. 
         [0028]      FIG. 3  is a schematic diagram of a filter  300  according to one embodiment of the present invention. The filter  300  comprising a capacitor C 1 , a capacitor C 2 , a capacitor C 3 , a inductor L 1 , a inductor L 2  and a inductor LG 1 . An electrode  301  of the capacitor C 1  is electrically connected to an I/O terminal T 1  of the filter  300 . An electrode  303  of the capacitor C 2  is electrically connected to a I/O terminal T 2  of the filter  300 , wherein if the I/O terminal T 1  is an input terminal, the I/O terminal T 2  is an output terminal, or vice versa. An electrode  305  of the capacitor C 3  is electrically connected to the I/O terminal T 1  of the filter  300  and an electrode  306  of the capacitor C 3  is electrically connected to the I/O terminal T 2  of the filter  300 . A first terminal of the inductor LG 1  is electrically connected to a second electrode  302  of the capacitor C 1  and a second electrode  304  of the capacitor C 2 , and a second terminal of the inductor LG 1  is electrically connected to a first reference voltage (such as a ground voltage GND or other fixed voltages). A first terminal of the inductor L 1  is electrically connected to the I/O terminal T 1  of the filter  300 . A first terminal of the inductor L 2  is electrically connected to the I/O terminal T 2  of the filter  300 . Mutual inductance can be generated by interactive coupled magnetic field between the inductor L 1  and the inductor L 2 . Second terminals of the inductor L 1  and the inductor L 2  are connected to a second reference voltage (such as a ground voltage GND or other fixed voltages), wherein at least either the first reference voltage is a ground voltage or the second reference voltage is a ground voltage. The filter  300  can make a notch on the right-side band of the resonant frequency f 0  of the frequency response (such as the notch  502  in  FIG. 5 ). The frequency of the notch  502  can be changed by modifying capacitance of the capacitors C 1 , C 2  and C 3  or modifying inductance of the inductor LG 1 . For example, inductance of the inductor LG 1  can be 0.01˜0.1 times inductance of the inductor L 1  or the inductor L 2 . 
         [0029]      FIG. 4  is a schematic diagram of a filter  400  according to another embodiment of the present invention. A difference between the filter  300  and the filter  400  is that the filter  400  further comprises an inductor LG 2 . A first terminal of the inductor LG 2  is electrically connected to second terminals of the inductor L 1  and the inductor L 2 , and a second terminal of the inductor LG 2  is electrically connected to a third reference voltage (such as a ground voltage GND or other fixed voltages), wherein at least either the first reference voltage is a ground voltage or the third reference voltage is a ground voltage. The position of the notch  502  can also be changed by modifying an inductance of the inductor LG 2 . For example, an inductance of the inductor LG 2  can be 0.01˜0.1 times an inductance of the inductor L 1  or the inductor L 2 . 
         [0030]      FIG. 5  is a characteristic-curve-of-frequency-response diagram of the filter  400  shown in  FIG. 4 . The filter  400  has a resonant frequency f 0  in the center of the passband, and there are a first notch  501  and a second notch  502  on the left-side band (the range smaller than f 0 ) and the right-side band (the range larger than f 0 ) of f 0  respectively. A notch is a frequency at which it has larger attenuation in the filter  400 . For example, the resonant frequency f 0  is about 2.5 GHz; the frequency of the first notch  501  is about 1.8 GHz, and the attenuation herein is about −36 dB; the frequency of the second notch  502  is about 5 GHz, and the attenuation herein is about −54 dB. 
         [0031]    Comparing to the conventional filter  100 , the filter  400  can make the second notch  502  on the right-side band of the resonant frequency f 0  of the frequency response. The frequency of the notch  502  can be changed by modifying capacitance of the capacitors C 1 , C 2  and C 3  or modifying the inductance of the inductors LG 1  and LG 2 . If the inductance of the inductor LG 1  or the inductor LG 2  is increased, the frequencies of the notch  501  and  502  will be close to (approach) the resonant frequency f 0 , and the attenuation at the notch  501  and  502  will decrease slightly (i.e. moving up along the Y axis in  FIG. 5 ). Otherwise, if the inductance of the inductor LG 1  or the inductor LG 2  is decreased, the frequencies of the notch  501  and  502  will be far from (leave) the resonant frequency f 0 , and the attenuation at the notch  501  and  502  will increase slightly (i.e. moving down along the Y axis in  FIG. 5 ). The frequency of the second notch  502  can be determined according to design requirements. For example, the filter  400  can make the frequency of the second notch  502  around a double resonant frequency (i.e. 2f 0 ) to meet the needs of the regulations or specification of products. 
         [0032]    Those skilled in the art will readily realize the filter  300  and the filter  400  by any manufacturing process and any layout structure in light of the teaching of the foregoing embodiment. For example,  FIG. 6  is a top view of the layout structure of the filter  400  shown in  FIG. 4 .  FIG. 7  is a perspective view of the layout structure shown in  FIG. 6 , and  FIG. 8  is an explosion diagram of the layout structure shown in  FIG. 7 . The layout of the filter  400  comprising a substrate SUB, a capacitor C 1 , a capacitor C 2 , a capacitor C 3 , a inductor L 1 , a inductor L 2 , a inductor LG 1 , a inductor LG 2  and a soldering pad  601 . The capacitors C 1 , C 2  and C 3  and the inductors L 1  and L 2  are disposed on the top surface of the substrate SUB. The capacitor C 1  and the capacitor C 2  are symmetrically disposed on both sides of a central line CL, and the inductor L 1  and the inductor L 2  are symmetrically disposed on both sides of the central line CL as well. In this embodiment, the geometrical shape of the inductor L 1  and the inductor L 2  are both long-straight wires as shown in  FIG. 6˜FIG .  8 , and inductance of the inductors L 1  and L 2  can be determined by changing the length and width of the wires. 
         [0033]      FIG. 9  is an equivalent circuit diagram of the layout structure of the filter  400  shown in  FIG. 6 . Please refer to  FIG. 6˜FIG .  9 , the capacitor C 3  of the filter  400  is performed by a capacitor C 31  and a capacitor C 32  in series due to layout consideration. An electrode  305  of the capacitor C 31  is electrically connected to an I/O terminal T 1  of the filter  400 . An electrode  609  of the capacitor C 32  is electrically connected to an electrode  608  of the capacitor C 31 , and an electrode  306  of the capacitor C 32  is electrically connected to an I/O terminal T 2  of the filter  400 . The capacitor C 31  and the capacitor C 32  are symmetrically disposed on both sides of the central line CL. 
         [0034]    A conducting wire  603  is disposed on a first edge of the top surface of the substrate SUB, wherein the first edge is adjacent to a first lateral surface of the substrate SUB, and the inductor LG 1  is disposed on the first lateral surface. In this embodiment, the geometrical shape of the inductor LG 1  is a vertical wire, and inductance of the inductor LG 1  can be determined by changing the width of the vertical wire. The central portion of the conducting wire  603  is connected to a terminal of the inductor LG 1 . Each end of the conducting wire  603  has an extending portion; and each extending portion is connected to an electrode  302  of the capacitor C 1  and an electrode  304  of the capacitor C 2  respectively. Therefore, the inductor LG 1  can be electrically connected to the electrode  302  of the capacitor C 1  and the electrode  304  of the capacitor C 2  through the conducting wire  603 . In a high-frequency application environment, the conducting wire  603  can be regarded as inductors LC 2  and LC 3 , and each of the extending portions of the conducting wire  603  can be regarded as inductors LC 1  and LC 4  respectively. 
         [0035]    A conducting wire  602  is disposed on a second edge of the top surface of the substrate SUB, wherein the second edge is adjacent to a second lateral surface of the substrate SUB, and the inductor LG 2  is disposed on the second lateral surface. In this embodiment, the geometrical shape of the inductor LG 2  is a vertical wire, and inductance of the inductor LG 2  can be determined by changing the width of the vertical wire. The central portion of the conducting wire  602  is connected to a first terminal of the inductor LG 2 . A first terminal and a second terminal of the conducting wire  602  are connected to a second terminal of the inductor L 1  and a second terminal of the inductor L 2  respectively. In a high-frequency application environment, the conducting wire  602  can be regarded as inductors LL 2  and LL 3 . 
         [0036]    A soldering pad  601 , a soldering pad  604  and a soldering pad  605  are disposed on the bottom surface of the substrate SUB. The soldering pad  604  is electrically connected to the I/O terminal T 1  of the filter  400 . The soldering pad  605  is electrically connected to the I/O terminal T 2  of the filter  400 . The soldering pad  601  is electrically connected to second terminals of the inductor LG 1  and the inductor LG 2 . The soldering pad  601  can be electrically connected to any reference voltage (such as a ground voltage GND or other fixed voltages) according to design requirements. 
         [0037]    The process of fabricating the filter  400  is described as the following. Please refer to  FIG. 8 , providing a substrate SUB first, which can be made of glass, ceramics, bakelite, plastics or other insulating materials, such as Aluminum oxide (Al 2 O 3 ). Then, form a first conducting layer M 1  on the substrate SUB and pattern it to form the electrode  301  of the capacitor C 1 , the electrode  305  of the capacitor C 31 , the electrode  306  of the capacitor C 32 , the electrode  303  of the capacitor C 2 , the conducting segment  603   a , the conducting segment  602   a , the I/O terminals T 1  and T 2  of the filter  400 . The material of the first conducting layer M 1  is mainly low-resistance material (e.g., Al, Cu, or Ag). The first conducting layer M 1  can be formed by conventional methods. 
         [0038]    Next, form a first insulating layer DE 1  on the first conducting layer M 1  and pattern it to optionally form dielectric windows. The first insulating layer DE 1  can be made of organic, inorganic or hybrid materials, such as SiO 2 , SiNx, SiON, polyimide-based or acrylic-based (acrylic). The first insulating layer DE 1  can be formed by conventional methods, such as CVD (chemical vapor deposition), sputtering, spin coating or coating. Next, form a second conducting layer M 2  on the first insulating layer DE 1  and pattern it to form the electrode  302  of the capacitor C 1 , the electrode  608  of the capacitor C 31 , the electrode  609  of the capacitor C 32 , the electrode  304  of the capacitor C 2 , the conducting segment  603   b , the conducting segment  602   b , the inductor L 1  and the inductor L 2 , and form dielectric window vias in the dielectric windows of the first insulating layer DE 1 . The terminals of the inductor L 1  and the inductor L 2  can be electrically connected to the I/O terminal T 1  and the I/O terminal T 2  of the filter  400  through the dielectric window vias respectively. The material, thickness and manufacturing process of the second conducting layer M 2  can be the same as that of the first conducting layer M 1 . 
         [0039]    Next, form a second insulating layer DE 2  on the second conducting layer M 2  and pattern it to optionally form dielectric windows. The material, thickness and manufacturing process of the second insulating layer DE 2  can be the same as that of the first insulating layer DE 1 . Then, form a third conducting layer M 3  on the second insulating layer DE 2  and pattern it to form the conducting segment  603   c , the conducting segment  602   c  and interconnects, and form dielectric window vias in the dielectric windows of the second insulating layer DE 2 . The material, thickness and manufacturing process of the third conducting layer M 3  can be the same as that of the first conducting layer M 1 . 
         [0040]    The conducting segments  603   a ,  603   b ,  603   c ,  602   a ,  602   b  and  602   c  of the conducting wire  603  and the conducting wire  602  on each conducting layer can be electrically connected through the dielectric window vias. The electrode  608  of the capacitor C 31  is electrically connected to the electrode  609  of the capacitor C 32  through the dielectric window vias and the interconnects. The conducting wire  603  is electrically connected to the electrode  302  of the capacitor C 1  and the electrode  304  of the capacitor C 2  through the dielectric window vias. 
         [0041]    Next, form the inductor LG 1  on the first lateral surface of the substrate SUB, and form the inductor LG 2  on the second lateral surface of the substrate SUB. In this embodiment, the inductor LG 1  and the inductor LG 2  are symmetrical with respect to the central line CL. Sometimes, process error may induce misalignment based on the central line CL of the inductor LG 1  and the inductor LG 2  (i.e. the values of parasitic inductance LL 2  and LL 3  are not equal). To improve the forgoing problem of process error, the positions of the inductor LG 1  and the inductor LG 2  can not be adjacent to the edges of the substrate SUB. The following takes the inductor LG 2  for an example, by which the inductor LG 1  can be referred. 
         [0042]    Those implementing this invention can moderately modify the layout structure shown in  FIG. 8  according to the teaching of the foregoing embodiment or design requirements. In one example, dispose the electrode  608  of the capacitor C 31  and the electrode  609  of the capacitor C 32  in the third conducting layer M 3 . In another example, dispose the electrode  608  in the second conducting layer M 2  and dispose the electrode  609  in the third conducting layer M 3 . In yet another example, dispose the electrode  608  in the third conducting layer M 3  and dispose the electrode  609  in the second conducting layer M 2 . 
         [0043]    In one example, dispose the electrode  302  of the capacitor C 1  and the electrode  304  of the capacitor C 2  in the third conducting layer M 3 . In another example, dispose the electrode  302  in the second conducting layer M 2  and dispose the electrode  304  in the third conducting layer M 3 . In yet another example, dispose the electrode  302  in the third conducting layer M 3  and dispose the electrode  304  in the second conducting layer M 2 . 
         [0044]    In one example, dispose the inductor L 1  and the inductor L 2  in the third conducting layer M 3 . In another example, dispose the inductor L 1  in the second conducting layer M 2  and dispose the inductor L 2  in the third conducting layer M 3 . In yet another example, dispose the inductor L 1  in the third conducting layer M 3  and dispose the inductor L 2  in the second conducting layer M 2 . No matter in which layer the inductor L 1  and the inductor L 2  are disposed, the terminals of the inductor L 1  and the inductor L 2  can both be electrically connected to the first I/O and the second I/O terminals of the filter  400  through its dielectric window vias respectively. 
         [0045]      FIG. 10  is a perspective view of portions of the layout structure of the filter  400  shown in  FIG. 4  according to another embodiment of the present invention. What isn&#39;t shown and described in this embodiment can be referred by the description in  FIG. 6˜FIG .  8 . The difference between this embodiment and the layout structure shown in  FIG. 6˜FIG .  8  is that the second conducting wire  602  shown in  FIG. 10  isn&#39;t adjacent to the edge of the substrate SUB. There is a small distance between the edge of the conducting wire  602  disposed on the top surface of the substrate SUB and the edge of the substrate SUB. A central portion of the conducting wire  602  has a central extending portion  1001 , which extends to the edge of the substrate SUB to connect to the inductor LG 2 . The inductor L 1  and the inductor L 2  are connected by the conducting wire  602 . Likewise, the first conducting wire  603  in this embodiment isn&#39;t adjacent to the edge of the substrate SUB, and there is a small distance between the edge of the conducting wire  603  and the edge of the substrate SUB. A central portion of the conducting wire  603  also has a central extending portion, which extends to a terminal of the inductor LG 1 . Each of the two ends of the conducting wire  603  has an extending portion to connect an electrode of the capacitor C 1  and an electrode of the capacitor C 2  respectively. Therefore, although there is misalignment with the central line CL of the inductor LG 2  (or the inductor LG 1 ) due to process error, the values of parasitic inductance LL 2  and LL 3  are still substantially equal, and the foregoing problem of process error can thus be effectively improved in this embodiment. 
         [0046]    In the abovementioned description, the inductance of the inductor LG 1  and the inductor LG 2  is determined by design requirements. In one example, in the foregoing embodiment, total inductance of the inductor LG 1  and the central extending portion of the conducting wire  603  is 0.01˜0.1 times the inductance of the first inductor L 1  or the inductor L 2 . In another example, total inductance of the inductor LG 2  and the central extending portion  1001  of the conducting wire  602  is 0.01˜0.1 times the inductance of the inductor L 1  or the inductor L 2 . 
         [0047]    Thin film technology can be used to perform the layout structure of the filter circuit described in the foregoing embodiments of this invention so that total manufacturing cost can be reduced. Furthermore, the filter circuit in the foregoing embodiments of this invention can make a notch on the right-side band of the resonant frequency f 0  of frequency response. 
         [0048]    The abovementioned filter  300  and filter  400  can be applied in any system, for example, a communication system.  FIG. 11  is a block diagram of a communication system  1100  according to one embodiment of the present invention. The communication system  1100  comprises an antenna  1110 , a matching network  1120 , a duplexer  1130  and a duplexer  1140 . The duplexer  1130  transmits signals to the antenna  1110 ; the duplexer  1140  receives the signals from the antenna  1110 . The matching network  1120  is also called impedance-matching circuit. The matching network  1120  can provide matching impedance, and improve the isolation of the foregoing transmitting and receiving of the signals. The foregoing filter circuit  300  and filter circuit  400  can be used as the matching network  1120  in the communication system  1100 . For example, connect the I/O terminal T 1  of the filter  400  to the antenna  1110 , and connect the I/O terminal T 2  of the filter  400  to the duplexer  1130  or the duplexer  1140 . 
         [0049]      FIG. 12  is a frequency-response diagram of the matching network  1120  shown in  FIG. 11 . The filter  400  is used in the matching network  1120  shown in  FIG. 11  herein. By increasing inductance of the inductors LG 1  and LG 2 , the impedance of the matching network  1120  will increase, and the impedance band can be made narrower, as shown in the curve  1201 . On the contrary, by decreasing inductance of the inductors LG 1  and LG 2 , the impedance of the matching network  1120  will decrease, and the impedance band can be made broader, as shown in the curve  1202 . 
         [0050]    In some application, the method or process of manufacturing the matching network  1120  may not be the same as that of the duplexers  1130  and  1140 . The matching network and the duplexers can be different package components, and a larger area of PCB (printed circuit board) may be occupied. The duplexers  1130  and  1140  can be stacked on the matching network  1120  (i.e. the filter  400 ), and the matching network and the duplexers can be in a single package component to save the area of PCB. 
         [0051]      FIG. 13  is a cross-sectional view of the filter  400  shown in  FIG. 6 . In some embodiment, those skilled in the art can further dispose a third insulating layer DE 3  on the third conducting layer M 3  according to design requirements and pattern it to form dielectric windows; and dispose a fourth conducting layer M 4  on the third insulating layer DE 3  and pattern it to form a die area, a soldering pad  606  and a soldering pad  607 . The soldering pad  606  is electrically connected to the I/O terminal T 1  of the filter  400  through the dielectric window vias; the soldering pad  607  is electrically connected to the I/O terminal T 2  of the filter  400  through the dielectric window vias. A die  1310 , such as a duplexer die, can be placed in the die area, and the duplexer  1130  or the duplexer  1140 , as shown in  FIG. 11 , can be included in the duplexer die  1310 . The soldering pad  606  and the soldering pad  607  are electrically connected to the duplexer die  1310  by wire bonding. Therefore, by stacking the duplexers  1130  and  1140  on the matching network  1120  (i.e. the filter  400 ), the matching network and the duplexers made by different method (or process) can be in a single package component to reduce costs and save the area of PCB. 
         [0052]      FIG. 14  is a schematic circuit diagram of a filter circuit  1400  according to yet another embodiment of the present invention. This embodiment illustrated in  FIG. 14  can be easier to understand by referring to  FIG. 4 . The difference between the filter  400  and the filter  1400  is that the filter  1400  further comprises a capacitor C 6 , an inductor L 3 , a capacitor C 4  and a capacitor C 5 . An electrode  1461  of the capacitor C 6  is electrically connected to a terminal of the inductor LG 1 . An electrode  1462  of the capacitor C 6  is electrically connected to a terminal  1431  of the inductor L 3 . A terminal  1432  of the inductor L 3  is electrically connected to a terminal of the inductor LG 2 . The electrode  301  of the capacitor C 1 , an electrode  1441  of the capacitor C 4  and a terminal  1411  of the inductor L 1  are electrically connected to an I/O terminal T 1  of the filter  1400 . The electrode  303  of the capacitor C 2 , a electrode  1451  of the capacitor C 5  and a terminal  1421  of the inductor L 2  are electrically connected to a I/O terminal T 2  of the filter  1400 , wherein if the I/O terminal T 1  is an input terminal, the I/O terminal T 2  is an output terminal, and vice versa. An electrode  1442  of the capacitor C 4  and an electrode  1452  of the capacitor C 5  are electrically connected to an electrode  1462  of the capacitor C 6  and a terminal  1431  of the inductor L 3 . 
         [0053]    Comparing to the filter  300 , the filter  1400 , as illustrated in  FIG. 14 , comprises not only the first capacitor-inductor pair (the capacitor C 1  and the inductor L 1 ) and the second capacitor-inductor pair (the capacitor C 2  and the inductor L 2 ) but also the third capacitor-inductor pair (the capacitor C 6  and the inductor L 3 ). Mutual inductance can be generated by interactive coupled magnetic field between the inductor L 1 , the inductor L 2  and the inductor L 3 . 
         [0054]    Capacitance of the C 6  can be equal to capacitance of C 1  or C 2 ; capacitance of the C 4  or C 5  can be equal to capacitance of C 3 ; inductance of the inductor L 3  can be equal to inductance of the inductors L 1  and L 2 . Because the third capacitor-inductor pair (the capacitor C 6  and the inductor L 3 ) is added, the attenuation at the resonant frequency can be increased. Taking  FIG. 5  for an example, the notch  501  and  502  can be pulled down. 
         [0055]    Those skilled in the art will readily realize the filter  1400  by any manufacturing process and any layout structure in light of the teaching of the foregoing embodiment. For example,  FIG. 15  is a perspective view of the layout structure of the filter  1400  shown in  FIG. 14 ,  FIG. 16  is an explosion diagram of the layout structure shown in  FIG. 15 . The layout of the filter  1400  can be easier to understand by referring to the description of the filter  300  and the filter  400 . The difference between the filter  1400  and the filter  400  is that the layout structure of the filter  1400  further comprises an inductor L 3 , a capacitor C 6 , a capacitor C 4  and a capacitor C 5 . The capacitors C 4 , C 5 , C 6  and L 3  are disposed on the top surface of the substrate SUB. The capacitor C 4  and the capacitor C 5  are symmetrically disposed on both sides of a central line CL, and the inductor L 3  is symmetrically disposed on the central line CL. In this embodiment, the geometrical shapes of the inductor L 1 , L 2  and L 3  are long-straight wires as shown in  FIG. 15˜FIG .  16 , and inductance of the inductors L 1 , L 2  and L 3  can be determined by changing the length and width of the wires. 
         [0056]    Please referring to  FIG. 14˜FIG .  16 , the electrode  1441  of the capacitor C 4  is electrically connected to the I/O terminal T 1  of the filter  1400 . The electrode  1442  of the capacitor C 4  is electrically connected to the electrode  1462  of the capacitor C 6 , the electrode  1452  of the capacitor C 5  and the terminal  1431  of the inductor L 3  through the interconnects and the dielectric window vias. 
         [0057]    Those implementing this invention can moderately modify the layout structure shown in  FIG. 15  and  FIG. 16  according to the teaching of the foregoing embodiments or design requirements. In one example, dispose the electrode  1442  of the capacitor C 4 , the electrode  1452  of the capacitor C 5  and the electrode  1462  of the capacitor C 6  in the second conducting layer M 2 . In another example, dispose the electrode  1442 , the electrode  1452  and the electrode  1462  in the third conducting layer M 3 . In yet another example, dispose the electrode  1442 , the electrode  1452  and the electrode  1462  in different layers, such as disposing the electrode  1442  and  1452  in the second conducting layer M 2  and disposing the electrode  1462  in the third conducting layer M 3 . 
         [0058]    In one example, dispose the inductor L 3  in the second conducting layer M 2 . In another example, dispose the inductor L 3  in the third conducting layer M 3 . No matter in which layer the inductor L 3  is disposed, the terminal  1431  of the inductor L 3  can be electrically connected to the electrode  1442 , the electrode  1452  and the electrode  1462  through the dielectric window vias and the interconnects. 
         [0059]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.