Abstract:
A memory cell sensing circuit to sense data from a memory cell includes a reference memory cell coupled to pass a reference current. A sense amplifier has a first input and a second input coupled to a bias circuit of the data memory cell. A first mirror mirrors the reference current to a voltage coupled to the first input of the sense amplifier. A second mirror mirrors the reference current to a voltage coupled to the bias circuit of the data memory cell. A third mirror mirrors the reference current to a voltage coupled to the second input of the sense amplifier through a pass gate.

Description:
PRIORITY CLAIM  
         [0001]    This application claims priority to Italian Application Serial Number 2002A000798, filed Sep. 13, 2002.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to sense-amplifier circuits. More particularly, the present invention relates to a fast dynamic mirror sense amplifier with separate comparison, equalization and evaluation paths.  
           [0004]    2. The State of the Art  
           [0005]    In order to correctly read the data item from a memory cell from a memory matrix, it is known to compare the data item read from the memory matrix cell with the data item read from a reference matrix cell, so as to detect the difference between a programmed cell and an erased cell. For this purpose, memory matrices are usually preset so that a reading of the data item from a memory cell is matched by a reading of an amount of current that flows across a reference matrix cell. The difference between the two readings determines the particular data item read.  
           [0006]    A first possible implementation is to use a local reference memory cell for each sense amplifier as illustrated in FIG. 1. Reference memory cell  10  is biased by n-channel MOS transistor  12  in cascode configuration using inverter  14  fed by diode-connected p-channel MOS transistor  16  used as a current source. The current drawn by p-channel MOS transistor  16  is mirrored to p-channel MOS transistor  20 , which sources current to matrix memory cell  18  through n-channel MOS transistor  22  in cascode configuration using inverter  24 . During an equalization period of timely length, pass gate  26  is enabled and is used to charge the MAT node  28  to the potential of the REF node  30 . At the end of the equalization period, pass gate  26  is turned off and the MAT node  28  is allowed to move toward either the power supply potential or ground potential depending on the difference between the reference cell current and the matrix cell current. The sense operation is performed by a comparator  32 , having the nodes REF and MAT as its inputs.  
           [0007]    The approach of FIG. 1 has the disadvantage of causing disturbs on the REF node, both during the equalization period and the subsequent sense period. At the beginning of the equalization period the MAT node  28  is grounded and, after the pass gate  26  has been enabled, it is directly connected to the REF node  30 , whose transient is in this way disturbed. Considering that the gate of the p-channel MOS transistor  20  at REF node  30  is an input of the comparator  32 , inevitably, during the evaluation period, the commutation of the output couples a disturb onto it and, consequently, disturbs the reference current.  
           [0008]    Moreover having many reference cells is disadvantageous both from the point of view of die area occupation and from the point of view of managing these reference cells during testing operations.  
           [0009]    A normal evolution of the system illustrated in FIG. 1 consists of locally repeating the reference cell current for each sense amplifier by using a local current mirror as shown in FIG. 2. The same reference-current-generating structure shown in FIG. 1 is used in the system of FIG. 2, employing reference cell  10 , n-channel MOS transistor  12  in cascode with inverter  14  and p-channel MOS transistor current source  16 . The current drawn by the reference memory cell  10  is mirrored from p-channel MOS transistor  16  to p-channel MOS mirror transistor  34 . Diode-connected n-channel MOS transistor  36  establishes the REF_N voltage.  
           [0010]    To eliminate the disturbs during the equalization and the evaluation periods, the circuit of FIG. 2 makes use of additional local current mirrors to generate two reproductions of the REF_P node (EQ_LEV and COMP_LEV) to be used for the equalization and as reference input of the comparator  32 . Local current mirror structures  38 ,  40 , and  42  each employ a p-channel MOS transistor (shown as  38 - 1 ,  40 - 1 , and  42 - 1 , respectively, in mirror structures  38 ,  40 , and  42 ) and an n-channel MOS transistor (shown as  38 - 2 ,  40 - 2 , and  42 - 2 , respectively, in mirror structures  38 ,  40 , and  42 ) to generate the signals REF_P, EQ_LEV, and COMP_LEV. P-channel MOS mirror transistor  20  and n-channel MOS transistor  22  cascoded with inverter  24  provide a mirrored current for matrix memory cell  18  as in the circuit of FIG. 1. The EQ_LEV voltage is supplied to the MAT node input to comparator  32  through pass gate  46 .  
           [0011]    In a system that uses the architectural approach of FIG. 2, the p-channel MOS mirror transistor  38 - 1  in local current mirror  38  must be set to precisely the reference cell current because, during the evaluation period, the voltage on the node MAT will increase or decrease depending on the difference between the matrix cell current and the current biasing the p-channel MOS mirror transistor  38 - 1 . The EQ_LEV and COMP_LEV signals are obtained in the same way, starting from the reference cell current, using local current mirrors  40  and  42  identical to local current mirror  38  used to generate REF-P signal.  
           [0012]    In systems like that shown in FIG. 2, the REF-N node supplies three different subcircuits, multiplied by the number of sense amplifiers, and thus has a very high capacitive load.  
         BRIEF DESCRIPTION OF THE INVENTION  
         [0013]    The present invention provides a fast dynamic mirror sense amplifier with separate comparison equalization and evaluation paths. A first memory cell sensing circuit comprises: a reference memory cell coupled to pass a reference current; a data memory cell having a bias circuit; a sense amplifier having a first input and a second input coupled to the bias circuit of the data memory cell; a pass gate; a reference-voltage source; a comparison current coupled between the reference-voltage source and the first input of the sense amplifier to a voltage coupled to the bias circuit of the data memory cell; an equalization circuit coupled between the reference-voltage source and the second input of the sense amplifier through the pass gate; and a mirror mirroring the reference current to a voltage coupled to the first input of the sense amplifier.  
           [0014]    Another memory cell sensing circuit to sense data from a memory cell includes a reference memory cell coupled to pass a reference current. A sense amplifier has a first input and a second input coupled to a bias circuit of the data memory cell. A first mirror mirrors the reference current to a voltage coupled to the first input of the sense amplifier. A second mirror mirrors the reference current to a voltage coupled to the bias circuit of the data memory cell. A third mirror mirrors the reference current to a voltage coupled to the second input of the sense amplifier through a pass gate. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWING FIGURES  
       [0015]    [0015]FIG. 1 is a schematic diagram of a first prior-art memory-sensing scheme using a local reference cell for each sense amplifier.  
         [0016]    [0016]FIG. 2 is a schematic diagram of another prior-art memory-sensing scheme that operates by locally repeating the reference cell current for each sense amplifier by using a local current mirror.  
         [0017]    [0017]FIG. 3 is a schematic diagram of an illustrative fast dynamic mirror sense amplifier with separate comparison equalization and evaluation paths according to the principles of the present invention.  
         [0018]    [0018]FIG. 4 is a schematic diagram of a generalization of a fast dynamic mirror sense amplifier with separate comparison equalization and evaluation paths according to the principles of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0019]    Persons of ordinary skill in the art will realize that the following description of the present invention is only illustrative and not in any way limiting. Other embodiments of this invention will be readily apparent to those skilled in the art having benefit of this disclosure.  
         [0020]    It is important that the REF-N node reaches its stable value as soon as possible and with the highest accuracy because the reference current is constant when the REF-N node reaches its stable value and it is thus possible to perform an accurate sense operation. For this reason it is important to make the capacitive load of the REF-N node as light as possible, limiting the number of gates connected to it to the lowest possible number.  
         [0021]    The present invention advantageously exploits the fact that it is necessary to put an accurate current information to precisely repeat the reference-cell current only on the p-channel MOS transistor from which the reference voltage is derived, while two voltage levels that are not as accurate may be used to generate the equalization and the evaluation potentials.  
         [0022]    In order to detect the movement of the voltage on the MAT node toward the power supply potential or ground potential it is sufficient to have a reference voltage for the comparator  32  that may be generated completely independently from the circuit that replicates the reference current in the matrix memory cell  18  for the comparison with the matrix cell current.  
         [0023]    The reference voltage for the REF input node of the comparator  32  is however related to the voltage value toward which the MAT node must be taken during the equalization period; the equalization voltage level must be inside the operating range that allows the sense amplifier to work properly.  
         [0024]    Referring now to FIG. 3, a schematic diagram illustrates a solution in accordance with the present invention that allows minimizing the number of gates connected to the REF-N node and hence its capacitance, making it relatively immune from disturbs due to capacitive coupling.  
         [0025]    The same reference-current-generating structure shown in FIG. 1 is used in the system of FIG. 3, employing reference cell  10 , n-channel MOS transistor  12  in cascode with inverter  14  and p-channel MOS transistor current source  16 .  
         [0026]    The current drawn by the reference memory cell  10  is mirrored from p-channel MOS transistor  16  to p-channel MOS mirror transistors  50 ,  52 , and  54 . Diode-connected n-channel MOS transistor  56  establishes the REF_N voltage. Diode-connected n-channel MOS transistors  58 , and  60 , respectively, establish the REF_EQ and REF_COMP voltages.  
         [0027]    The REF_N voltage is supplied to a first current mirror  62  at the gate of n-channel MOS transistor  64 . N-channel MOS transistor  64  is driven by a current-source diode-connected p-channel MOS transistor  66 . The current through diode-connected p-channel MOS transistor  66  is mirrored to the matrix memory cell  18 , configured as in the prior figures using p-channel MOS mirror transistor  20  and n-channel MOS transistor  22  cascoded with inverter  24  provide a mirrored current for matrix memory cell  18  as in the circuit of FIG. 1.  
         [0028]    In the circuit of FIG. 3, the voltage references for the comparator and the equalization circuit are locally generated in each sense amplifier by separate local dedicated mirrors. Each local mirror uses a dedicated reference signal derived from n-channel MOS transistor  16 . Thus the equalization voltage level is generated by local mirror  68  at the gate and source of diode-connected p-channel MOS transistor  70 , sourcing current to n-channel MOS transistor  72 . The gate of n-channel MOS transistor  72  is driven by the REF_EQ voltage at the gate and drain of the diode-connected n-channel MOS transistor  60 . The equalization potential is supplied to the MAT node input to comparator  32  through pass gate  46 . Similarly, the COMP_LEVEL comparison voltage level is generated by local mirror  74  at the gate and source of diode-connected p-channel MOS transistor  76 , sourcing current to n-channel MOS transistor  72 . The gate of n-channel MOS transistor  78  is driven by the REF_EQ voltage at the gate and drain of the diode-connected n-channel MOS transistor  58 .  
         [0029]    This arrangement significantly reduces the capacitive load on the reference current line. The accuracy (and dimensions) of these current mirrors may be lower than accuracy of the current mirror used for generation of the reference current.  
         [0030]    This solution provides a capacitive load lowered by a factor 2 or 3 and thus allows the reference current to reach its stable value faster in comparison with the solution shown in FIG. 2, without being disturbed during read phases.  
         [0031]    From the observation that at the input of the comparator the information to be processed is contained in the difference between two voltage levels, arises the idea of further freeing the circuit supplying the reference current from those used for equalization and evaluation.  
         [0032]    [0032]FIG. 4 shows a generalization of the architecture of FIG. 3. The circuit of FIG. 4 generally implements the need to have a very accurate current information related to the reference cell only for the evaluation path while for the equalization and comparator paths the information needed is voltage information that is not necessarily related to the reference current but necessary only to initially set the MAT, EQ_LEV and COMP_LEV nodes to a value within the correct range.  
         [0033]    The circuit of FIG. 4 employs reference cell  10 , n-channel MOS transistor  12  in cascode with inverter  14  and p-channel MOS transistor current source  16 . The current drawn by the reference memory cell  10  is mirrored from p-channel MOS transistor  16  to p-channel MOS mirror transistor  50  and n-channel MOS transistor  56 . The REF_N voltage from the gate and drain of n-channel MOS transistor  56  is supplied to a current mirror  62  at the gate of n-channel MOS transistor  64 . N-channel MOS transistor  64  is driven by a current-source diode-connected p-channel MOS transistor  66 . The current through diode-connected p-channel MOS transistor  66  is mirrored to the matrix memory cell  18 , configured as in the prior figures using p-channel MOS mirror transistor  20  and n-channel MOS transistor  22  cascoded with inverter  24  provide a mirrored current for matrix memory cell  18  as in the circuit of FIG. 1.  
         [0034]    The voltage references for the comparator and for the equalization circuit are locally supplied in each sense amplifier by mean of diode-connected p-channel MOS transistors  70  and  74 , respectively, biased by the current drawn by n-channel MOS transistors  72  and  78 , respectively, whose gates are both tied to a fixed potential V REF , independent from power supply and temperature variations, which may be supplied by, for example, a band-gap reference.  
         [0035]    The bias current for the comparator and for the equalization circuit obtained in this way is not independent from power supply and temperature variations, nor follows the reference cell current variations but, opportunely dimensioning the circuit components, it is possible to keep the voltage references for the comparator and for the equalization circuit inside the limits needed to guarantee the system functionality.  
         [0036]    There are several constraints to be observed so that the system works properly. First, the p-channel MOS transistors in the memory cell bias circuits must operate in saturation in order to operate as a current mirror. The cascode n-channel MOS transistors must also operate in saturation. Finally, the reference voltage for the comparator must properly bias the comparator input stage so that its input transistors operate in their saturation regions.  
         [0037]    While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.