Abstract:
A distributed and adjustable level-shifiting netwrok is intergrated with cascaded amplifiers, eliminating the need for a direct current (dc) blocking capacitor between the amplifiers. The level-shifting network can be adjucted to compensate for process variations and to balcane the crossover firequency response of the cascaded amplifiers.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]    This application claims the benefit of U.S. Provisional Application No. 60/351,976, filed Jan. 25, 2002, which application is incorporated by reference herein. 
     
    
     
       BACKGROUND  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates generally to the field of electronic components for optical and broadband communication systems, and more particularly to techniques implement in integrated circuit (IC) technology for cascading broadband amplifiers while preserving their broadband frequency response.  
           [0004]    2. Background  
           [0005]    Amplifiers used in optical and broadband communication systems typically need to amplify low frequency signals. This requirement makes cascading two or more broadband amplifiers difficult and expensive since a large capacitor is required to block the direct current (dc) bias of the output of one amplifier stage from the input of the subsequent amplifier stage. This blocking capacitor must be large enough (e.g., high capacitance) to pass the full frequency range of the cascaded amplifiers, which can extend down to dc.  
           [0006]    Unfortunately, a large capacitor presents various problems that make cascading broadband amplifiers difficult and expensive to implement in certain IC technologies, such as Monolithic Microwave Integrated Circuit (MMIC) technology. To address these problems, several conventional techniques for implementing cascaded broadband amplifiers using IC technology have been proposed.  
           [0007]    A first technique uses a large off-chip capacitor in between the amplifier stages. The large physical size of a capacitor capable of passing the required frequency range has significant parasitic effects that make it difficult to design properly.  
           [0008]    A second technique uses a small coupling capacitor between the high frequency amplifier stages to pass the high frequencies, and an off-chip parallel path low frequency amplifier to provide dc restoration. The use of a parallel path amplifier requires near perfect match of phase and amplitude through the crossover network, which is difficult to achieve in practice.  
           [0009]    A third technique uses a small coupling capacitor and an off-chip high gain feedback amplifier to raise the input impedance of the subsequent amplifier stage at low frequencies. With this technique it is difficult to achieve the high resistor-capacitor (RC) constant required for low frequencies (i.e., KHz range).  
           [0010]    Accordingly, a solution is needed for providing adjustable, dc level-shifting capability in a distributed amplifier without using a blocking capacitor and without sacrificing the broadband frequency response of the cascaded amplifiers.  
         SUMMARY OF THE INVENTION  
         [0011]    The present invention overcomes the deficiencies of conventional techniques by providing an integrated circuit comprising cascaded amplifiers integrated with an adjustable, distributed level-shifting network. The cascaded amplifiers are direct-coupled together without the use of a dc blocking capacitor. The distributed level-shifting network is coupled to one or more amplifiers in the cascade and provide the desired dc levels. The level-shifting network is adjustable through, for example, one or more variable resistors to balance the crossover frequency response of the cascaded amplifiers and/or to compensate for process variations.  
           [0012]    In one embodiment of the present invention, the distributed level-shifting network includes a resistor-capacitor (RC) network coupled in series with a variable resistor and offset voltage supply for balancing the crossover frequency response of the cascaded amplifiers. The variable resistor can be an active device (e.g., transistor) configured to function as a variable resistor. The variable resistor can be included in each amplifier or a single variable resistor can be shared by all of the amplifiers in the cascade.  
           [0013]    In another embodiment of the present invention, the distributed level-shifting network is coupled in shunt with the input of an amplifier and includes a level-shifting capacitor coupled in shunt with at least one diode in series with an optional coupling resistor. The level-shifting network can be coupled in series with a variable resistor and offset voltage supply for balancing the crossover frequency response of the amplifier. One or more diodes can also be added for temperature compensation. The variable resistor can be an active device (e.g., transistor) configured to function as a variable resistor. The variable resistor can be included in each amplifier or a single variable resistor can be shared by all of the amplifiers in the cascade. The variable resistor can be optionally coupled to a feedback circuit which uses sensed bias current to maintain a desired bias level over temperature.  
           [0014]    The present invention enables two or more broadband amplifiers to be cascaded and fabricated in a single integrated circuit chip, thereby saving the expense of assembling the cascaded amplifiers in a hybrid microcircuit using a coupling capacitor. The cascaded amplifiers have improved frequency response performance due to inclusion of a distributed and adjustable level-shifting network. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]    [0015]FIG. 1 is a circuit diagram of an integrated circuit, including cascaded amplifiers integrated with a distributed level-shifting network, in accordance with one embodiment of the present invention.  
         [0016]    [0016]FIG. 2 is a circuit model diagram of the “ith” stage of an amplifier integrated with an adjustable, level-shifting network, in accordance with one embodiment of the present invention.  
         [0017]    [0017]FIG. 3 is a circuit diagram of an adjustable, level-shifting network in accordance with one embodiment the present invention.  
         [0018]    [0018]FIG. 4 is a circuit diagram of an integrated circuit, including an amplifier integrated with an adjustable, distributed level-shifting network, in accordance with one embodiment of the present invention.  
         [0019]    [0019]FIG. 5 is a circuit diagram of an integrated circuit, including an amplifier integrated with an adjustable, distributed level-shifting network, in accordance with one embodiment of the present invention.  
         [0020]    [0020]FIG. 6 is a circuit diagram of an integrated circuit, including an amplifier integrated with an adjustable, distributed level-shifting network, in accordance with one embodiment of the present invention.  
         [0021]    [0021]FIG. 7 is a circuit diagram of an adjustable, level-shifting network, in accordance with one embodiment of the present invention.  
         [0022]    [0022]FIG. 8 is a circuit diagram of an adjustable, level-shifting network, in accordance with one embodiment of the present invention.  
         [0023]    [0023]FIG. 9 is a circuit diagram of a single IC cell including an adjustable, level shifting circuit, in accordance with one embodiment of the present invention.  
         [0024]    [0024]FIG. 10 is a circuit diagram of a feedback circuit, in accordance with one embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF EMBODIMENTS  
       [0025]    The present invention is described below using symbols and nomenclature known to those skilled in the art of integrated circuit technology. Like elements are collectively designated by a single numerical designation, and individual elements within the numerically designated set of elements are designated alphanumerically. For example, elements  100   a  and  100   b  may be referred to collectively as elements  100  or elements  100   a - b.    
         [0026]    The semiconductor devices described in the embodiments below can be any type of device, including without limitation, Bipolar Junction Transistors (BJTs), Field Effect Transistors (FETs), Pseudomorphic high electron mobility (pHEMPTs), Dual Gate Devices, and Cascode Pairs. These devices can be made of any material, including without limitation, Silicon (Si), Gallium Arsenide (GaAs), Indium Phosphate (InPh), and Gallium Nitride (GaN).  
         [0027]    [0027]FIG. 1 is a circuit diagram of an integrated circuit  100 , including cascaded amplifiers  101 , in accordance with one embodiment of the present invention. The cascaded amplifiers  101  include an input amplifier  102  coupled to an output amplifier  104  without using a dc blocking capacitor (i.e., direct-coupled). The cascaded amplifiers  101  are not limited to two amplifiers but rather can include any number of amplifiers depending upon the application. Also, each amplifier can include any number and type of gain devices (e.g., FETs, BJTs).  
         [0028]    In one embodiment of the present invention, the input amplifier  102  includes gain devices  106   a - b  and the output amplifier  104  includes gain devices  108   a - b.  The drain terminals d of the gain devices  106   a - b  are coupled to the output transmission line  103   a  via inductive elements L d  and the gate terminals g of the gain devices  106   a - b  are coupled to an adjustable, level shifting networks  122   a - b,  respectively. The drain terminals d of the gain devices  108   a - b  are coupled to the output transmission line  103   b  via inductive elements L d  and the gate terminals g of the gain devices  108   a - b  are coupled to level shifting networks  100   a - b,  respectively. Each gain device  106   a - b,    108   a - b,  is separated from its neighboring gain device by an inductive element L out  inserted in the output transmission lines  103   a - b,  and an inductive element L in  inserted in the input transmission lines  105   a - b.  The inductive elements L out , L d , L in  form an artificial line low-pass filter, which absorbs the parasitic capacitance of the gain devices  106   a - b  and  108   a - b  using known circuit techniques. In practice, these elemental inductances are implemented using a small length of high impedance transmission line. The R levAi  resistors are used as a dc level shift. There values are chosen as not to load the characteristic impedance Z o  of the input transmission line  105   a,  and are typically at least 10× the value of Zo. The R levBi  resistors complete the level shifting down to a negative supply.  
         [0029]    The level-shifting networks  122   a - b,  include level capacitors  124   a - b  (C levA1 , C levA2 ) coupled in parallel to a resistors  126   a - b  (R levA1 , R levA2 ), to form resistive-capacitive (RC) networks. The values of the resistors  126   a - b  are selected to provide a desired dc level shifting without loading the input transmission line  105   a  with excess attenuation. The level capacitors  124   a - b  are selected to maintain a flat frequency response down to near dc. The parallel combination of the capacitors  124   a - b  and the resistors  126   a - b  are coupled in shunt to a fixed or variable resistors  128   a - b  (R levB1 , R levB2 ), which are coupled in series to a variable resistor  130  (R var1 ). The variable resistor  130  is coupled to a voltage offset  132 .  
         [0030]    The level-shifting networks  110   a - b,  include level capacitors  112   a - b  (C levA3 , C leVA4 ) coupled in parallel to a resistors  114   a - b  (R levA3 , R levA4 ), to form RC networks. The values of the resistors  114   a - b  are selected to provide a desired a dc level shifting without loading the input transmission line  105   b  with excess attenuation. The level capacitors  112   a - b  are selected to maintain a flat frequency response down to near dc. The parallel combination of the capacitors  112   a - b  and the resistors  114   a - b  are coupled in shunt to variable resistors  116   a - b  (R levB3 , R levB4 ), which are coupled in series to a variable resistor  120  (R var2 ). The variable resistor  120  is coupled to a voltage offset  118 .  
         [0031]    The level-shifting networks  122   a - b  and  110   a - b  provide an adjustable, dc level to the input and output amplifiers  102 ,  104 , respectively, without using a dc blocking capacitor. The level-shifting networks  122   a - b  and  110   a - b  are adjustable via the variable resistors  116   a - b,    120 ,  130 , to compensate for IC process variations and to balance the crossover frequency response of the cascaded amplifiers  101 . The operation of the level-shifting networks  122   a - b  and  110   a - b  is discussed more fully below with respect to FIG. 2.  
         [0032]    In one embodiment, the output transmission line  103   b  is coupled to a sensing feedback circuit, which uses R termout  and/or an internal or external sense resistor to sense the bias current I bias . The sensed bias current is provided to a feedback circuit  1000  (FIG. 10) for holding the dc bias constant over temperature variations.  
         [0033]    [0033]FIG. 2 is a circuit model diagram of the “ith” stage  200  of an amplifier  201  integrated with an adjustable, level-shifting network  203 , in accordance with one embodiment of the present invention. The “ith” stage  200  of the amplifier  201  includes gain device  202  (e.g., a FET) having an input capacitance  204  (C fin ). The level-shifting network  203  includes a level capacitor  206  (C levA ), a resistor  208  (R levA ), and a variable resistor  210  (R levBi ). The level-shifting network  203  models the level-shifting networks  110  shown in FIG. 1.  
         [0034]    The resistor  208  is coupled in parallel with the level capacitor  206  to form an RC network. The parallel combination of the resistor  208  and level capacitor  206  is coupled in shunt with the variable resistor  210 , which is used to balance the crossover frequency response of the ith stage of the amplifier  201  as follows:  
         R levAi *C levAi =R levBi *C fin     1      (1)  
         [0035]    where “i” means the “ith” stage of the amplifier  201 .  
         [0036]    As can be seen from equation (1), the crossover frequency can be balanced by adjusting the variable resistor  210  (R levBi ) until the relationship described in equation (1) is achieved.  
         [0037]    Referring back to FIG. 1, the level-shifting networks  122   a - b  enable direct coupling between amplifiers  102  and  104  by driving the dc bias on the drain terminals d of gain devices  106   a - b  to about 0 volts. For example, if the amplifiers  102 ,  104 , each have a gain of 4 so that the gain devices  108   a - b  in amplifier  104  are scaled to be 4× larger than the gain devices  106   a - b  in amplifier  102 , and the drain terminal supply voltage in amplifier  102  is 8 Volts, and it is desired to level shift it down to about 0 Volts at the gate terminal g of each gain device  108   a - b,  then the R levA  resistors  126   a - b  can be about 4× larger than the R levB  resistors  128   a - b,  thus providing a −2 Volt bias across the R levB  resistors  128   a - b  to get 0 Volts at the gate terminal g of each gain device  108   a - b.  The values of level capacitors  124   a - b  in level-shifters  122   a - b  are preferably selected such that equation (1) is satisfied for about ¼ of the input capacitance (C fin ) of the gain devices  106   a - b.    
         [0038]    To minimize the attenuation along the input transmission line  105   a,  the parallel value of the R levA  resistors  126   a - b  is preferably large compared to the characteristic impedance Z o  of the input transmission line  105   a.  For an eight section distributed amplifier, this would make the R levA  resistors  126   a - b  each about 8×10××Z o  or about 4K Ohms, and the R levB  resistors  128   a - b  each about 1K Ohm.  
         [0039]    [0039]FIG. 3 is a circuit diagram of a level adjusting network  300  in accordance with one embodiment the present invention. The level adjusting network  300  includes a plurality of resistors  302   a - d  (R levB1 -R levB4 ) and a variable resistor  304  (R var ). While only four resistors are shown in FIG. 3, any number of resistors  302   a - d  can be used with the present invention. The level adjusting network  300  can be used in place of the variable resistor  210  shown in FIG. 2. The variable resistor  304  in the level adjusting network  300  provides a continuous range of tuning to compensate for process variations and parasitic effects, while also providing crossover frequency balance. The level adjusting network  300  in combination with a level-shifting network (e.g., level-shifting networks  122   a - b ) provides level shifting with a less negative voltage applied to subsequent broadband amplifiers added to a cascade.  
         [0040]    The crossover frequency balance is represented mathematically as follows:  
                   ∑     i   =   1     n            R     lev                   A   i         *     C     lev                   A   i             =       ∑     i   =   1     n            (       R     lev                   B   i         +     n   *     R   var         )     *     C     fin   i             ,           (   2   )                               
 
         [0041]    where “i” means the “ith” stage of the distributed amplifier and “n” is the total number of resistors R levBi , R levBi .  
         [0042]    As can be seen from equation (2), the crossover frequency can be balanced by adjusting the variable resistor  304  (R var ) until the relationship described in equation (2) is achieved.  
         [0043]    [0043]FIG. 4 is a circuit diagram of an integrated circuit  400 , including a broadband amplifier  402  integrated with a level adjusting network  404 , in accordance with one embodiment of the present invention. The level adjusting network  404  is similar to the level adjusting network  300  shown in FIG. 3 and includes parallel resistors  406   a - d  (R levb1 -R levB4 ) coupled in shunt with a variable resistor  410  (R var ). The variable resistor  410  is coupled to a voltage offset  412  (e.g., 1 Volt). The broadband amplifier  402  includes gain devices  424   a - d,  each having a drain terminal d coupled via inductive element L d  to output transmission line  420  and a gate terminal g coupled to the level adjusting network  404 .  
         [0044]    A diode-capacitor level shifting network  414 , including one or more series diodes  416  coupled in parallel with a level capacitor  418 , is coupled in shunt to the input of the broadband amplifier  402  to provide de level shifting in conjunction with the level adjusting network  404 . The number of diodes  416  used depends upon the required value of the series resistance contributed by the diodes  416  to achieve the desired crossover frequency response.  
         [0045]    In one embodiment, the output transmission line  420  is coupled to a sense resistor R biasFB  to sense the bias current I bias . The sensed current is provided to a feedback circuit  1000  (FIG. 10) for holding the dc bias constant over temperature variations.  
         [0046]    [0046]FIG. 5 is a circuit diagram of an integrated circuit  500 , including a broadband amplifier  502  integrated with a level adjusting network  504 , in accordance with one embodiment of the present invention. The level adjusting network  504  is similar to the level adjusting network  300  shown in FIG. 3 and includes parallel resistors  506   a - d  (R levB1 -R levB4 ) coupled in shunt with a variable resistor  510  (R var ). The variable resistor  510  is coupled to a voltage offset  512  (e.g., 1 Volt). The amplifier  502  includes gain devices  524   a - d,  each having a drain terminal d coupled via inductive element L d  to output transmission line  520  and a gate terminal g coupled to the level adjusting network  504 .  
         [0047]    A diode-capacitor network  514 , including one or more series diodes  516  coupled in parallel with a level capacitor  518 , is coupled in shunt to the output of the broadband amplifier  502  to provide dc level shifting in conjunction with the level adjusting network  504 . The number of diodes  516  used depends upon the required value of the series resistance contributed by the diodes  516  to achieve the desired crossover frequency response.  
         [0048]    In one embodiment, the output transmission line  520  is coupled to a sense resistor R biasFB  to sense the bias current I bias . The sensed current is provided to a feedback circuit  1000  (FIG. 10) for holding the dc bias constant over temperature variations.  
         [0049]    [0049]FIG. 6 is a circuit diagram of an integrated circuit  600 , including a broadband amplifier  602  integrated with a level adjusting network  604 , in accordance with one embodiment of the present invention. The level adjusting network  604  is similar to the level adjusting network  300  shown in FIG. 3 and includes parallel resistors  606   a - d  (R levB1 -R levB4 ) coupled in shunt with a variable resistor  610  (R var ). The variable resistor  610  is coupled to a voltage offset  612  (e.g., 1 Volt). The amplifier  602  includes gain devices  624   a - d,  each having a drain terminal d coupled via inductive element L d  to output transmission line  620  and a gate terminal g coupled to the level adjusting network  604 .  
         [0050]    A distributed, diode-capacitor level-shifting network  614 , including one or more series diodes  616   a - d  coupled in parallel with a level capacitors  618   a - d,  is coupled in shunt to the inputs of gain devices  624   a - c  to provide proper level shifting in conjunction with the level adjusting network  604 . The number of diodes  616  (“m diodes”) used by the level-shifting network  614  depends upon the required value of the series resistance contributed by the diodes  616  to achieve the desired crossover frequency response.  
         [0051]    In one embodiment, one or more diodes  605   a - d  (“n diodes”) are coupled in series with the resistors  606   a - d,  respectively, to provide temperature compensation.  
         [0052]    In the general case, where m diodes are used with level-shifting capacitance (C lev ) and n diodes are use for temperature compensation, the crossover balance is represented mathematically as follows:  
                 R   mdiodes     =       ∑     j   =   1     m          R     diode   j           ;           (   3   )                   R   ndiodes     =       ∑     j   =   1     n          R   diodej         ;   and           (   4   )                     (       R     lev                 Ai       +     R     lev                 Bi       +     R   mdiodes       )     ×     C     lev                 i         =       (       R   Ci     +     R   ndiodei     +     nR   D       )     *     C   Feti         ,           (   5   )                               
 
         [0053]    where “n” is the number of sections of a distributed amplifier.  
         [0054]    [0054]FIG. 7 is a circuit diagram of a diode-based level-shifting network  700 , in accordance with the present invention. The level-shifting network  700  comprises one or more sections  702   a - d  having one or more diodes  704   a - d  coupled in shunt with leveling capacitors  706   a - d , respectively. The number of diodes  704   a - d  used in the network  700  depends upon the required value of the series resistance contributed by the diodes  704   a - d  to achieve the desired crossover frequency response. Each section  702   a - d  is coupled in parallel to the other sections  702   a - d  and separated by inductive elements  708   b - g , as shown in FIG. 7.  
         [0055]    [0055]FIG. 8 is a circuit diagram of a transistor-based circuit  800  that can be used in place of diodes, in accordance with one embodiment of the present invention. The transistor-based circuit  800  comprises at least one transistor  802 , an output capacitor  804 , and bias resistors  804   a - b . The transistor  803  can be a FET, BJT, or some other known transistor device. The values of the bias resistors  804   a - b  are selected to bias the transistor  802  to function as a diode.  
         [0056]    [0056]FIG. 9 is a circuit diagram of a single IC cell  900  including an adjustable, level shifting circuit, in accordance with one embodiment of the present invention. The cell  900  includes gain devices  902   a - b , each having a drain terminal d coupled to an output transmission line  926  and a gate terminal g coupled to an input transmission line  928  via level capacitors  904  and  910 . The gate terminal g of the gain devices  902   a  is coupled in shunt with a series resistor  916  and one or more diodes  918 , which are used coupled in shunt with a series resistor  916  and one or more diodes  918 , which are used for temperature compensation, as previously discussed with respect to FIG. 6. Likewise, the gate terminal g of the gain device  90   b  is coupled in shunt with a series resistor  920  and one or more diodes  922 , which are used for temperature compensation. The diodes  918  and  922  are coupled to a variable resistor  924 . To provide the proper amount of level shifting, a resistor  906  coupled in series with one or more diodes  908  is coupled between the input transmission line  928  and bias resistors  912  and  914 .  
         [0057]    In the general case, where m diodes are used with level-shifting capacitance (C lev ) and n diodes are use for temperature compensation, the crossover balance is represented mathematically as follows:  
                 R   mdiodes     =       ∑     j   =   1     m          R     diode   j           ;           (   6   )                   R   ndiodes     =       ∑     j   =   1     n          R   diodej         ;   and           (   7   )                     (       2        R     lev                 Ai         +     R     lev                 Bi       +     2        R   mdiodes         )     ×     C   levi       =       (       R   Ci     +     R   ndiodei     +     nR   D       )     *     C   Feti         ,           (   8   )                               
 
         [0058]    where “n” is the number of sections of a distributed amplifier.  
         [0059]    [0059]FIG. 10 is a circuit diagram of a feedback circuit  1000 , in accordance with one embodiment of the present invention; The feedback circuit  1000  includes an amplifier  1004  having a first input coupled to a sense resistor R biasFB  (FIGS. 4 and 5) and a second input for receiving feedback from the output of the amplifier  1004 . The output is also coupled to a low pass filter  1002 . The feedback circuit  1000  maintains the bias current I bias  at a desired value by sensing the de value of I bias  and holding it constant over temperature. The feedback circuit  1000  can replace the voltage offsets  118 ,  412  and  512  shown in FIGS. 1, 4 and  5 , respectively.  
         [0060]    The above description is included to illustrate the operation of the preferred embodiments and is not meant to limit the scope of the invention. Rather, the scope of the invention is to be limited only by the claims. From the above discussion, many variations will be apparent to one skilled in the relevant art that would yet be encompassed by the spirit and scope of the invention.