Abstract:
An amplifier comprises a Low Noise Amplifier (LNA) that amplifies a Radio Frequency (RF) signal that includes a transconductance, a gain and an input stage that receives the RF signal. A bias assembly includes a bias circuit with a bias resistance and generates a bias current for the input stage of the LNA, which is related to the bias resistance. A shunt feedback stage amplifies an output of the input stage, generates an RF output and includes a shunt resistance. Changes in the bias resistance due to changes in conditions are substantially offset by changes in the shunt resistance due to the changes in conditions, which reduces variation of the gain of the LNA based on the changes in conditions.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation of U.S. patent application Ser. No. 10/301,349 filed on Nov. 20, 2002 now U.S. Pat. No. 6,784,738. The disclosure of the above application is incorporated herein by reference. 

   TECHNICAL FIELD 
   This invention relates to low noise amplifiers (LNA). 
   BACKGROUND 
   One of the key building blocks of a conventional RF transceiver is a Low Noise Amplifier (LNA).  FIG. 1  shows an implementation of a CMOS LNA high gain path  200  commonly adopted in conventional RF transceivers. The gain of this amplifier can be expressed as:
         A v =g m ·Q 2 ·R p  where gm is the transconductance of the input device, Q is the quality factor of the load inductor and R p  is the parasitic resistance associated with the inductor.       

   Referring to the equation above, the gain is a strong function of gm of the input transistor, as well as the Q of the inductor of the LNA. gm may vary +/−30-40%, and the Q 2 R p  term typically varies +/−10-20% due to process, temperature etc. variation. As a result, the gain of the LNA can easily vary by greater than 6 dB. This gain variation may affect receiver performance significantly in real life applications and hence, the implementation may not be desirable. 
   SUMMARY 
   An amplifier comprises a Low Noise Amplifier (LNA) that amplifies a Radio Frequency (RF) signal and that includes a transconductance, a gain and an input stage that receives the RF signal. A bias assembly includes a bias circuit with a bias resistance and generates a bias current for the input stage of the LNA, which is related to the bias resistance. A shunt feedback stage amplifies an output of the input stage, generates an RF output and includes a shunt resistance. Changes in the bias resistance due to changes in conditions are substantially offset by changes in the shunt resistance due to the changes in conditions, which reduces variation of the gain of the LNA based on the changes in conditions. 
   In other features, the bias resistance and the shunt resistance include the same type of resistors. The conditions include at least one of process, temperature, environmental, and/or power variations. The bias resistance and the shunt resistance include poly resistors. 
   In other features, an integrated circuit comprises the amplifier. The shunt resistance is arranged on the integrated circuit in close proximity to the bias resistance such that the conditions of the bias resistance substantially mirror the conditions of the shunt resistance. 
   In other features, the bias circuit further includes a first transistor having a gate, a source and a drain. A second transistor has a gate, a source, and a drain. The gate and drain of the second transistor and the gate of the first transistor communicate. A source of the first transistor communicates with a first end of the bias resistance. The bias circuit further includes a current mirror that communicates with the drains of the first and second transistors and that outputs the bias current. The bias circuit further includes a bias current buffer that communicates with the current mirror and that supplies a buffered current based on the bias current. The current mirror includes a third transistor that has a first size and that communicates with the drain of the first transistor. A fourth transistor has a second size and communicates with the drain of the second transistor. The first size is substantially equal to the second size. 
   The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims. 

   
     DESCRIPTION OF DRAWINGS 
       FIG. 1  is a block diagram of a conventional LNA. 
       FIG. 2  is a block diagram of an aspect of a transceiver. 
       FIG. 3  is a block diagram of an aspect of an amplifier for amplifying an RF signal. 
       FIG. 4  is a block diagram of an aspect of an LNA biasing scheme. 
       FIG. 5  is a detailed schematic diagram of an aspect of several bias impedance configurations. 
       FIG. 6  is a detailed schematic diagram of an aspect of a bias circuit for an LNA. 
       FIG. 7  is a flow diagram of an aspect of generating a bias current for an LNA. 
   

   Like reference symbols in the various drawings indicate like elements. 
   DETAILED DESCRIPTION 
     FIG. 2  shows an aspect of a wireless transceiver  210  for communicating information. The receive path of the wireless transceiver  210  may include an amplifier  212  for amplifying an input signal  214 . The amplifier  212  may include a bias assembly  218  and LNA  216  constructed in accordance with the principles of the invention. A mixer  222  may combine the amplified input signal with a Radio Frequency (RF) LO signal  224 . A filter  226  and adjustable amplifier  223  may filter and amplify the combined signal, and mix the generated signal with an Intermediate Frequency (IF) LO signal down to baseband for possibly further amplification and filtering. An analog-to-digital converter (ADC)  228  may convert the mixed signal to a digital signal for further processing. 
   In the transmit path, a digital-to-analog converter  227  may convert a digital signal to an analog signal for transmission by a transmitter  225 . 
     FIG. 3  shows an aspect of an amplifier  230  for generating an RF output. The amplifier  230  is configured to compensate for gain variations that may be caused by process and environmental variations. The amplifier  230  is suitable for assembly as an integrated circuit fabricated with CMOS techniques. The amplifier  230  includes a bias assembly  232  for supplying a bias current, lout, to an LNA  234 . A bias current buffer  236  may be connected between the bias assembly  232  and LNA  234  to level shift and amplify the bias current. 
   In one aspect, the LNA  234  may include an input stage  238  and a shunt feedback stage  240  to amplify an RF in  signal  242 . To compensate for gain changes related to resistive component variations in the shunt feedback stage  240 , the bias assembly  232  may be configured to have a resistive variation that is about inversely proportional to the shunt feedback stage resistive variation. The bias assembly  232  may, for example, include a bias circuit  244  to generate the bias current as a function of a bias resistor  246 , where environmental variations of the bias resistor resistance may partially or completely cancel resistance variations of the shunt feedback stage  240 . 
   In another aspect, the LNA  234  may include an input stage  238  to amplify the RF in  signal  242 , but not include a shunt feedback stage  240 . A bias assembly  232  may include a bias circuit  244  to generate the bias current as a function of a bias resistor  246 . The bias resistor  246  may be either an on-chip resistor or an external resistor. If an on-chip resistor is used, the bias assembly  232  may also include a calibration circuit  248  to partially or completely cancel resistance variations of the bias resistor  246 . 
     FIG. 4  shows an aspect of a bias assembly  10  for supplying a bias current, lout, to an LNA (not shown). The bias assembly  10  is suitable for assembly as an integrated circuit fabricated with CMOS techniques. The bias assembly  10  includes a bias circuit  12  and a calibration circuit  14 . The bias circuit  12  generates the bias current as a function of a bias impedance  16 . The bias impedance  16  may be controlled in response to a control signal  18  from the calibration circuit  14  to maintain a relatively constant value over variations in operating conditions such as process variations and environmental conditions variations. 
   Referring to  FIG. 5 , several configurations of the bias impedance are shown. A hybrid configuration  50  includes a series string of resistors  52  and control transistors  54  that are connected in shunt with one or more of the resistors  52 . A series configuration  60  includes a series string of resistors  62  with control transistors  64  that are connected in shunt with each resistor  62 . A shunt configuration  70  includes groupings of a resistor  72  connected in series with a control transistor  74  and the series combinations of resistor-transistor connected in shunt. The resistors in each of the configurations may be made from any suitable material including N+ poly and P+ poly. 
   Referring to  FIG. 4 , a bias voltage that may include temperature and process compensation is applied across the bias impedance  16  to generate the bias current. The bias current is supplied to a current mirror  20  that may reflect the bias current to a buffer  22 . The buffer  22  supplies the bias current to an LNA (not shown) and may be configured as either a P Metal Oxide Semiconductor (PMOS) or an NMOS current mirroring gain buffer. The device characteristics of the buffer  22  may be varied in relation to the current mirror  20  to change the amplitude of the bias current supplied by the buffer  22 . For example, the size of the buffer  22  may be varied relative to the current mirror to cause a corresponding change in the current supplied. 
   The calibration circuit  14  may determine the effect of process and environmental variations on a calibration impedance  24  such as a poly resistor. The calibration impedance  24  preferably is constructed from similar material, has a similar configuration, and is located in close proximity to the bias impedance  16  so that changes in the calibration impedance  24  may track changes in the bias impedance  16 . A reference current, Iref,  26  may be applied to the calibration impedance  24  to generate a calibration voltage that is compared to a reference voltage, Vref,  28 . The reference current  26  may be generated from a fixed voltage such as the reference voltage  28  and a fixed resistor that maintains a predictable value over process and environmental variations. A comparator  30  monitors changes in the calibration impedance  24  relative to the voltage reference  28 . A latch  32  may latch the output of the comparator  30  synchronous to a clock. A calibration control circuit  34  may delay the latch output to reduce the impact of noise generated at the clock edges. The calibration control circuit  34  may include control logic and a up/down counter  38 . A calibration signal, CAL, enables the calibration control circuit  34 . A clock signal, Clk 2 , provides a timing reference for the counter  38 . A decoder  40  interprets the signal from the calibration control circuit  34  and in response may control the resistance of the calibration impedance  24  by enabling or disabling control transistors. 
     FIG. 6  shows an aspect of a bias circuit  80  for generating an LNA bias current. The bias circuit  80  may include a PMOS current mirror pair, Q 3  and Q 4 , and a pair of NMOS transistors, Q 1  and Q 2 ,  82  and  84  for generating a controlled current, Is, through a resistor, R s ,  86 . A size ratio, K, of Q 1  and Q 2  is selected to provide a desired current amplitude of Is. The following equations show the relation between the transconductance of Q 1  and R s , if the currents flowing through Q 1  and Q 2  are equal, 
               2   ⁢     I   s         μ   ⁢           ⁢   C   ⁢     W   L           +     V   TH1       =           2   ⁢     I   s         μ   ⁢           ⁢       C   ⁡     (     W   L     )       ·   K           +     V   TH2     +       I   s     ·     R   s               
   Canceling V TH1  and V TH2 , and rearranging terms; 
               I   s     =         2     μ   ⁢           ⁢     C   ⁡     (     W   L     )           ·     1     R   s   2         ⁢       (     1   -     1     K         )     2               Equation   ⁢           ⁢   1             
 
   The pair of PMOS transistors, Q 3  and Q 4 ,  88  and  90  may be selected to have the same size so that the currents flowing through drains of Q l  and Q 2  are substantially equal. With equal currents in Q 1  and Q 2 , the relationship described by Equation 1 is maintained. A buffer  92  is preferably the same type of transistor as Q 3  and Q 4 ,  88  and  90 , and may be sized in relation to Q 3  to vary the amplitude of current, lout flowing from the buffer  92 . For example, if the buffer  92  is selected to be three times larger than Q 3 , then I out1  will be three times larger than Is. A current mirror  94  including transistors Q 6  and Q 7  may be connected to the buffer  92  to set a bias current, I out2 , of an LNA  95 . The ratio of the sizes of Q 6  and Q 7  may be varied to change the amplitude of I out2  with respect to I out1 . 
   If the size ratio of Q 5  and Q 3  is M and the ratio of Q 7  and Q 6  is N, then the bias current I out2  flowing into Q 7  will be: 
         g     m   ,   Q7       =         2   ⁢   μ   ⁢           ⁢       C   ⁡     (     W   L     )       ·     I   out2           =         2   ⁢     MN         R   s       ⁢     (     1   -     1     K         )             
 
   Solving for g m , Q 7 
         I   out2     =       MNI   s     =           2   ⁢   MN       μ   ⁢           ⁢     C   ⁡     (     W   L     )           ·     1     R   s   2         ⁢       (     1   -     1     K         )     2             
 
   It can be seen that the transconductance of the LNA input stage is predominately dependent on the resistor value R s . R s  may be implemented as an external resistor or an on chip resistor. If R s  is implemented as an on chip resistor, then the resistance value of R s  will vary with process and environmental variations. The variation of the LNA gain to process and environmental changes may be reduced by using any of several techniques including 1) a calibration scheme to reduce the variation of R s  with process and environmental changes, and 2) adding a shunt feedback stage to cancel out the resistor variation. 
   In one aspect, the LNA  95  may include an input stage  96  to amplify an RF input signal, RF in . Recall that the gain of the LNA is: 
         A   v     =         g   m     ·     Q   2     ·     R   p       ∝         Q   2     ⁢     R   p         R   s             
 
   Since R s  will be calibrated, the Q 2 Rp term becomes the dominant contributor of gain variation, varying by about 10%-20%. 
   In another aspect, the LNA  95  may also include a shunt feedback stage  97  connected to the input stage  96  to further amplify RF in . The gain of this LNA can be expressed as: 
           A   v     =         g   m     ·     R   f       ∝       R   f       R   s           ,       
 
where R f  is the shunt feed back resistor. If R f  is chosen to be the same type of resistor as R s , a good match can be achieved, leading to improved gain accuracy.
 
     FIG. 7  shows an operation for amplifying an RF signal. Starting at block  100 , a bias voltage may be generated by a two transistor circuit. The bias voltage may be equal to the difference between the V gs  voltages of the two transistors. At block  102 , the bias voltage is applied across a bias impedance to generate a bias current. The bias impedance may be controllable and may include one or more poly resistors in combination with switches. The magnitude of the bias current may be a function of the poly resistors and the physical characteristics of the two transistors including size ratio, width, length, and capacitance. At block  104 , the bias current is mirrored to generate an output current that is a function of the poly resistance. 
   In one aspect, at block  106 , a reference current is generated. At block  108 , the reference current is supplied to a controlled calibration impedance that may include several poly resistors in combination with switches. At block  110 , the voltage developed across the controlled calibration impedance may be compared to a reference voltage. At block  112 , the impedance of the controlled calibration impedance may be controlled as a function of the comparison to reduce the difference between the reference voltage and the voltage developed across the controlled calibration impedance. Different ones of the control switches are turned on or off to effect the desired control. At block  114 , a control signal may be generated to indicate the change in the controlled calibration impedance that cancels the difference between the reference voltage and the voltage developed across the controlled calibration impedance. The control signal may indicate the state of each of the control switches. At block  116 , the impedance of the controlled bias impedance may be controlled in response to the control signal so that changes in the poly resistance are compensated for by effecting the same changes to the controlled bias impedance that are effected for the controlled calibration impedance. Variations in the resistance of the poly resistors caused by process, environmental conditions, and operating conditions may be compensated for by controlling for the change in resistance of the controlled calibration impedance poly resistors and mirroring that control to the controlled bias impedance poly resistors. By compensating for changes in the resistance of the poly resistors, the transconductance of the LNA may be held constant over process variations and environmental conditions resulting in a relatively constant LNA gain, with the dominant variation resulting from the effective impedance from the inductor tank. 
   In another aspect, continuing from block  104  to block  118  an LNA is biased with the output current. The LNA may include an input stage to receive an RF input signal. At block  120 , a portion of the amplified RF input signal may be communicated to the input stage using a shunt resistor to provide feedback. Variations in the shunt resistor may be compensated for by variations in the bias impedance to cause the gain of the amplifier to be substantially independent of changes in conditions that affect the values of the resistors. 
   Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the current invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.