Abstract:
Discloses are a constant current control unit and a control method, apt to a switched mode power supply with primary side control. The switched mode power supply comprises a power switch and an inductive device. A reflective voltage of the inductive device is detected to generate a feedback voltage signal. By delaying the feedback voltage signal, a delayed signal is generated. According to the feedback voltage and the delayed signal determining, a discharge time of the inductive device is determined when the power switch is OFF. According to the discharge time and a current-sense signal, a maximum average output current of the switched mode power supply is stabilized. The current-sense signal represents a current flowing through the inductive device.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority to and the benefit of Taiwan Application Series Number 101123952 filed on Jul. 4, 2012, which is incorporated by reference in its entirety. 
       BACKGROUND 
       [0002]    The present disclosure relates generally to switched mode power supplies with primary side control. 
         [0003]    Power supplies, as needed for most electronic apparatuses, convert the electric power from power sources, such as batteries or power grids, into the electric power with specifications required by loadings. Among conventional power supplies, switched mode power supply, known to be compact in size and efficiency in power conversion, is globally popular, especially in consumer market. 
         [0004]    Two different control methodologies are employed for switched mode power supplies. One is primary side control (PSC), and the other secondary side control (SSC) . SSC utilizes a detection circuit directly sensing an output node powered by the secondary winding of a power supply, and the detection result is passed, via a photo coupler, to a power controller located in the primary side to regulate the power a primary winding converts. Different to SSC, PSC directly senses a reflective voltage across an auxiliary winding to indirectly know the output voltage over the secondary winding and the output voltage on the output node. For PSC, detection of output voltage and control of power conversion are both performed in the primary side. In comparison with SSC, PSC is cheaper in view of bill of material (BOM) cost, because it needs no bulky and costly photo coupler. Furthermore, PSC could naturally have higher conversion efficiency as it has no detection circuit located in the secondary side, which acts as an additional loading constantly consuming power. 
         [0005]      FIG. 1  is a switched mode power supply  10  known in the art, employing the control methodology of PSC. Bridge rectifier  20  performs full-wave rectification, converting the alternative-current (AC) power source from a power grid into a direct-current (DC) input power source V IN . The voltage of the input power source V IN  could have an M-shaped waveform or be substantially a constant. Via the driving node GATE, the power controller  26  periodically turns ON and OFF the power switch  34 . When the power switch  34  is ON, the primary winding PRM of the transformer energizes. When it is OFF, the transformer de-energizes via the secondary winding SEC and the auxiliary winding AUX to build up output power source V OUT  for loading  24  and operation power source V CC  for power controller  26 . 
         [0006]    The voltage divider consisting of resisters  28  and  30  detects voltage drop V AUX  over the auxiliary winding AUX, to provide the feedback node FB of the power controller  26  feedback voltage signal V FB . When the power switch  34  is OFF, the voltage drop V AUX  is a reflective voltage in proportion to the voltage drop over the secondary winding SEC. Based on the feedback voltage signal V FB , power controller  26  builds compensation voltage V COM  upon the compensation capacitor  32 , to control the duty cycle of the power switch  34  accordingly. Via current-sense node CS, power controller  26  detects current-sense voltage V CS , which represents the current I PRM  flowing through not only the current sense resistor  36 , but also the power switch  34  and the primary winding PRM. 
         [0007]      FIG. 2  shows gate voltage V GATE , feedback voltage signal V FB , and secondary output current I SEC  of  FIG. 1 , where the secondary output current I SEC  is the current flowing through the secondary winding SEC and powering the loading  24 . By knowing the peak value of secondary output current I SEC  and the real discharge time T DIS-R  when secondary winding SEC discharges, power controller  26  could conclude both the total amount of output charge from the secondary winding SEC and the average output current, to determine whether the average output current is out of specification. 
         [0008]    As known in the art, an estimated discharge time T DIS-E  used as the real discharge time T DIS-R , is determined by sensing the first time when feedback voltage signal V FB  drops across about 0V after gate signal V GATE  turns to 0V. Nevertheless, estimated discharge time T DIS-E  is very different to real discharge time T DIS-R , as shown in  FIG. 2 . After the completion of the discharge, it takes time for the feedback voltage signal V FB  to reach 0V, causing the difference between the real discharge time T DIS-R  and the estimated discharge time T DIS-E . This difference could cause both misjudgment of the average output current from the secondary side and failure of average output current regulation for switched mode power supply  10 . 
       SUMMARY 
       [0009]    Embodiments of the present invention disclose a constant current control unit apt to a switched mode power supply with primary side control. The switched mode power supply has a power switch and an inductive device. A voltage-waveform detector in the constant current control unit determines a discharge time of the inductive device when the power switch is OFF, based on a feedback voltage signal and a delayed signal. The feedback voltage signal is provided from a reflective voltage of the inductive device and the delayed signal is generated by delaying the feedback voltage signal. A constant current controller in the constant current control unit generates an integral result according to the discharge time and a current-sense signal. The current-sense signal is provided based on a current flowing through the inductive device. The integral result is used for controlling the power switch to stabilize a maximum average output current of the switched mode power supply. 
         [0010]    Embodiments of the present invention disclose a control method apt to a switched mode power supply with primary side control. The switched mode power supply comprises a power switch and an inductive device. A reflective voltage of the inductive device is detected to generate a feedback voltage signal. By delaying the feedback voltage signal, a delayed signal is generated. According to the feedback voltage and the delayed signal determining, a discharge time of the inductive device is determined when the power switch is OFF. According to the discharge time and a current-sense signal, a maximum average output current of the switched mode power supply is stabilized. The current-sense signal represents a current flowing through the inductive device. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The invention can be more fully understood by the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0012]      FIG. 1  is a switched mode power supply known in the art; 
           [0013]      FIG. 2  shows gate voltage V GATE , feedback voltage signal V FB , and a secondary output current I SEC  of  FIG. 1 ; 
           [0014]      FIG. 3  demonstrates a power controller according to embodiments of the invention; 
           [0015]      FIG. 4  demonstrates the constant current control unit in  FIG. 4 ; and 
           [0016]      FIG. 5  shows some waveforms of the signals in  FIG. 1  and  FIG. 4 . 
       
    
    
     DETAILED DESCRIPTION 
       [0017]      FIG. 3  demonstrates a power controller  27  according to embodiments of the invention. In one embodiment of the invention, power controller  27  replaces the power controller  26  in  FIG. 1 . The switched mode power supply  10  is not for limiting the scope of the invention, and the invention could be apt to other kinds of power supplies. 
         [0018]    Power controller  27  has a protection unit  38 , a constant current control unit  40 , a constant voltage control unit  42 , and a gate logic  44 . The gate logic  44  gathers the output results from the protection unit  38 , the constant current control unit  40 , and the constant voltage control unit  42  to generate gate signal V GATE  as a pulse-width-modulation signal for controlling the duty cycle of the power switch  34 . 
         [0019]    Even though they all are coupled to the feedback node FB and the current sense node CS, the protection unit  38 , the constant current control unit  40 , and the constant voltage control unit  42  function differently. The protection unit  38  is in charge of detection of the occurrence of abnormal events, such as over voltage, output short, over loading, to name a few, to provide appropriate protection mechanisms for the whole switched mode power supply. The purpose of the constant current control unit  40  is to limit the average output current powering the loading  24 , making the average output current not over a predetermined maximum value. In other words, the constant current control unit  40  stabilizes the average output current to the loading  24  to be the maximum value when the loading  24  is very heavy. During the time when the loading  24  is normal or light, the constant voltage control unit  42  stabilizes the voltage value of the output power source V OUT  to be a predetermined voltage. 
         [0020]      FIG. 4  demonstrates the constant current control unit  40  of  FIG. 3 , including a voltage-waveform detector  60  and a constant current controller  62 . The voltage-waveform detector  60  outputs discharge signal S DIS , which represents discharge time T DIS-E-NEW , based on which the constant current controller  62  performs maximum output current control to limit the average output current to the loading  24  in the secondary side. 
         [0021]    Inside the voltage-waveform detector  60  are a low-pass filter  64 , a comparator  66  and a logic control  68 . The low-pass filter  64 , consisting of a resistor  70  and a capacitor  72 , low passes the feedback voltage signal V FB  to generate delayed signal V DLY . Equivalently, the low-pass filter  64  delays the feedback voltage signal V FB  for a RC time constant to provide delayed signal V DLY , and this RC time constant is determined by the electric characteristics of the resistor  70  and the capacitor  72 . The comparator  66  compares the feedback voltage signal V FB  with delayed signal V DLY . When the feedback voltage signal V FB  decreases and becomes a certain amount less than the delayed signal V DLY , the detection result S DET  is asserted, meaning the feedback voltage signal V FB  seems to drop abruptly, an indication that the discharge of the secondary winding SEC completes. Based on the gate signal V GATE  and the detection result S DET , the logic control  68  provides the discharge signal S DIS  to estimate a discharge time T DIS-E-NEW  of the secondary winding SEC when the power switch  34  is OFF. 
         [0022]    The constant current controller  62  has an integrator  74 , a peak finder  78 , and a decision maker  76 . The peak finder  78  generates peak voltage V CS-PEAK  representing the peak voltage of the current-sense voltage V CS  when the power switch  34  is ON. The integrator  74  has a constant current source  82 , a switch  86 , a voltage-controllable current source  84  and a capacitor  80 . Controlled by discharge signal S DIS , the switch  86  acts as a short circuit only during the discharge time T DIS-E-NEW . The voltage-controllable current source  84  converts peak voltage V CS-PEAK  to sink current I DN , which drains or discharges capacitor  80  only during the discharge time T DIS-E- NEW . The capacitor  80  stores accordingly the integral result of the sink current I DN  with respect to the discharge time T DIS-E-NEW . The constant current source  82  provides constant current I UP  to charge the capacitor  80  constantly, which similarly stores the integral result of the constant current I UP  with respect to the whole cycle time of the power switch  34 . A cycle time is the summation of the ON time when the power switch  34  is ON and the OFF time when the power switch  34  is OFF. By checking the trend of the integral result voltage V RESULT  as the count of the switch cycles increases over time, it can be determined whether the average output current from the secondary winding SEC has exceeded a predetermined maximum value represented by the constant current I UP . If the integral result voltage V RESULT  goes beyond a certain range, the decision maker  76  can provide feedback control to pull it back, such that the average output current from the secondary winding SEC is stabilized at the predetermined maximum value. 
         [0023]      FIG. 5  shows some waveforms of the signals in  FIG. 1  and  FIG. 4 . In addition to the gate signal V GATE , the feedback voltage signal V FB , and the secondary output current I SEC  shown in  FIG. 2 ,  FIG. 5  further has the delayed signal V DLY  the discharge signal S DIS , and the integral result voltage V RESULT . Neighboring to the delayed signal V DLY  the feedback voltage signal V FB  is illustrated once again in a dashed waveform for comparison. The delayed signal V DLY  and the feedback voltage signal V FB  substantially share the same waveform, but the former is about delay time T DLY  later than the later. As shown in  FIG. 5 , the rising and falling edges of the delayed signal V DLY  all occur later than corresponding edges of the feedback voltage signal V FB  by about delay time T DLY , which is in proportion to the RC time constant defined by the low-pass filter  64 . At the moment when the gate signal V GATE  turns OFF the power switch  34 , OFF time T OFF  begins and the discharge signal S DIS  switches to be “1” in logic, indicating the beginning of the discharge time T DIS-E-NEW . As shown in  FIG. 5 , the feedback voltage signal V FB  drops abruptly after the completion of the discharge of the secondary winding SEC. Meanwhile, because of the delay time T DLY  provided by the low-pass filter  64 , the delayed signal V DLY  remains at a high voltage for a while. As the feedback voltage signal V FB  falls and the delayed signal V DLY  remains, the difference between them, if larger than a predetermined amount, can trigger the discharge signal S DIS  to be “0”, proclaiming the end of discharge time T DIS-E-NEW . 
         [0024]    During the discharge time T DIS-E-NEW , integral result voltage V RESULT  could decline because sink current I DN  is larger than the constant current I UP . Otherwise, the integral result voltage V RESULT  always ramps up because the constant current I UP  constantly charges the capacitor  80 . If the integral result voltage V RESULT  becomes less at the end of a cycle time T CYC  than it was at the beginning of the cycle time T CYC , it could be determined that the average output current from the secondary winding SEC exceeds a predetermined maximum value. If the average output current form the secondary winding SEC is determined to be too much, for example, decision maker  76  could lower compensation voltage V COM  to decrease the output power the switched mode power supply provides, such that the average output current is pulled back. 
         [0025]      FIG. 5  also illustrates the estimated discharge time T DIS-E  of  FIG. 2 , which is obtained by the judgment when the feedback voltage drops across 0V as known in the prior art. Shown in  FIG. 5 , the discharge time T DIS-E-NEW  is determined earlier than the estimated discharge time T DIS-E , and is closer to the real discharge time T DIS-R . Accordingly, the discharge time T DIS-E-NEW  could achieve maximum output current control more accurately than the estimated discharge time T DIS-E  does. 
         [0026]    While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.