Abstract:
A power converter uses a charge pump divider that includes a capacitive divider core and a phase clock generator. The capacitive divider core has an input for receiving an input voltage and an output for providing an output voltage. In a first phase the capacitive divider core is adapted to couple a flying capacitor in series with an output capacitor. In a second phase the capacitive divider core is adapted to couple the flying capacitor in parallel with the output capacitor. The phase clock generator activates a first phase clock indicating the first phase when a flying voltage across the flying capacitor is less than a predetermined portion of the input voltage minus a peak voltage, and subsequently activates a second phase clock indicating the second phase when the flying voltage exceeds the predetermined portion of the input voltage plus the peak voltage.

Description:
FIELD OF THE DISCLOSURE 
       [0001]    The present disclosure relates generally to power conversion circuits, and more particularly to power converters using charge pump converters. 
       BACKGROUND 
       [0002]    Modern portable electronic products use to a wide extent rechargeable batteries to power internal circuitry. Smaller devices such as compact cameras, cellular telephones and phablets can use battery packs that are based on single-cell batteries that provide a direct current (DC) voltage over a range of, for example, 2.5 to 4.5 volts (V). In these devices the battery pack voltage can be used to drive an integrated circuit chipset directly. However larger mobile devices such as high-end digital still cameras, tablets and laptop computers require the use of battery packs with multiple battery cells for high current requirements. These cells can be configured in parallel, in series or “stacked”, or as a combination of the two. The resulting battery packs generate a higher voltage in the range of, for example, 5V and 9V. The higher voltages are primarily used to power the larger displays, internal disk drivers, DVD drives, and the like. As a consequence however, in these larger devices, the chipset can no longer be powered directly from the battery pack and the higher battery voltage must to be reduced. Thus these devices typically use DC-DC buck converters to reduce the higher battery voltage to a level more suitable for powering integrated circuits. 
         [0003]    Moreover in order to preserve the limited battery life, these devices implement various screen-saving and power-saving modes. These different modes have caused the load conditions seen by the DC-DC converters (usually measured in terms of load current) to vary over a large range, possibly spanning up to three orders of magnitude or more. Because of the need to preserve battery life, the DC-DC converters need to be as efficient as possible under the widely varying load conditions. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]    The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings, in which: 
           [0005]      FIG. 1  illustrates a graph of the efficiency of a capacitive divider known in the prior art versus load current; 
           [0006]      FIG. 2  illustrates a graph of the efficiency of an inductive buck converter known in the prior art versus load current; 
           [0007]      FIG. 3  illustrates in partial block diagram and partial schematic form a charge pump divider according to an embodiment of the present invention; 
           [0008]      FIG. 4  illustrates in partial block diagram and partial schematic form a diagram showing the operation of the charge pump divider of  FIG. 3  during a first phase; 
           [0009]      FIG. 5  illustrates in partial block diagram and partial schematic form a diagram showing the operation of the charge pump divider of  FIG. 3  during a second phase; 
           [0010]      FIG. 6  illustrates a timing diagram of voltages relevant to the operation of the charge pump divider of  FIG. 3 ; 
           [0011]      FIG. 7  illustrates in block diagram form a frequency control circuit for use in the phase clock generator of  FIG. 3 ; 
           [0012]      FIG. 8  illustrates in partial block diagram and partial schematic form a power converter using an integrated circuit based on the charge pump divider of  FIG. 3 ; and 
           [0013]      FIG. 9  illustrates a graph of the relative efficiencies of the charge pump divider of  FIG. 1 , the inductive buck converter of  FIG. 2 , and the charge pump divider of  FIG. 3  versus load current; and 
           [0014]      FIG. 10  illustrates in block diagram form a frequency spreading circuit that can be added to the clock management block of  FIG. 8  to reduce EMI. 
       
    
    
       [0015]    The use of the same reference symbols in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well. 
       DETAILED DESCRIPTION 
       [0016]      FIG. 1  illustrates a graph  100  of the efficiency of a charge pump divider known in the prior art versus load current. In  FIG. 1  the horizontal axis represents load current in milli-Amperes (mA) using a logarithmic scale, and the vertical axis represents efficiency in percentage using a linear scale. A waveform  110  represents the efficiency of a typical charge pump converter using a divide-by-2 architecture versus load current. At higher load currents, such as 100 mA to over 1 A, efficiency is relatively high, peaking at about 98% at around 400-500 mA. However as current decreases from the peak, efficiency drops markedly, including about 91% at around 100 mA, about 85% at around 50 mA, and about 65% at around 20 mA. Thus the charge pump divider is inefficient in systems that require low power modes. While the charge pump divider has a very high peak efficiency of about 98%, efficiency at low loads is poor. 
         [0017]      FIG. 2  illustrates a graph  200  of the efficiency of an inductive buck converter known in the prior art versus load current. In  FIG. 2  the horizontal axis represents load current in mA using a logarithmic scale, and the vertical axis represents efficiency in percentage using a linear scale. A waveform  210  represents the efficiency of a typical low voltage inductive buck converter. Efficiency peaks at about 91% at around 1 A, but only decreases slightly as the load decreases, including about 88% at around 100 mA, about 87% at about 10 mA, and about 80% at around 1 mA. While the inductive buck converter has fairly constant efficiency over a wide load range, its peak efficiency is low. 
         [0018]      FIG. 3  illustrates in partial block diagram and partial schematic form a charge pump divider  300  according to an embodiment of the present invention. Charge pump divider  300  includes generally an input capacitor  310 , a capacitive divider core  320 , a flying capacitor  330 , an output capacitor  340 , and a phase clock generator  350 . Input capacitor  310  has a first terminal for receiving an input voltage labeled “V IN ”, and a second terminal connected to ground. Capacitive divider core  320  includes N-channel metal oxide semiconductor (MOS) transistors  322 ,  324 ,  326 , and  328 . Transistor  322  has a drain for receiving V IN , a gate for receiving a signal labeled “Φ 1 ”, and a source. Transistor  324  has a drain connected to the source of transistor  322 , a gate for receiving a signal labeled “Φ 2 ”, and a source for providing a voltage labeled “V OUT ”. Transistor  326  has a drain, a gate for receiving signal Φ 2 , and a source connected to ground. Transistor  328  has a drain connected to the source of transistor  324 , a gate for receiving signal Φ 1 , and a source connected to the drain of transistor  326 . Flying capacitor  330  has a first terminal connected to the source of transistor  322  and the drain of transistor  324 , and a second terminal connected to the drain of transistor  326  and the source of transistor  328 . Output capacitor  340  has a first terminal connected to the source of transistor  324  and to the drain of transistor  328 , and a second terminal connected to ground. Phase clock generator  350  has a first output terminal for providing signal Φ 1 , and a second output terminal for providing signal Φ 2 . 
         [0019]    As will now be explained, charge pump divider  300  is able to operate as a divide-by-two converter having both high peak efficiency and relatively constant efficiency over a wide load range by controlling the frequency of the generation of phase clock signals Φ 1  and Φ 2 . The basic operation of charge pump divider  300  will now be explained followed by a description of the operation of phase clock generator  350 . 
         [0020]      FIG. 4  illustrates in partial block diagram and partial schematic form a diagram showing the operation of the charge pump divider of  FIG. 3  during a first phase. The first phase corresponds signal Φ 1  being active at a logic high while signal Φ 2  is inactive at a logic low. During the first phase, transistors  322  and  328  are active and operate as closed switches, while transistors  324  and  326  are inactive and operate as open switches. The circuit path is shown by a dashed arrow  400 . Neglecting the parasitic resistances of transistors  322  and  328 , capacitors  330  and  340  are connected in series, and assuming they are equal-valued, V OUT  will be about one-half of V IN . 
         [0021]      FIG. 5  illustrates in partial block diagram and partial schematic form a diagram showing the operation of charge pump divider  300  of  FIG. 3  during a second phase. The second phase corresponds signal Φ 1  being inactive at a logic low while signal Φ 2  is active at a logic high. During the second phase, transistors  324  and  326  are active and operate as closed switches, while transistors  322  and  328  are inactive and operate as open switches. The circuit path is shown by a dashed arrow  500 . Neglecting the parasitic resistances of transistors  324  and  326 , capacitors  330  and  340  are connected in parallel between the node forming V OUT  and ground. 
         [0022]      FIG. 6  illustrates a timing diagram  600  of voltages relevant to the operation of charge pump divider  300  of  FIG. 3 . In  FIG. 6 , the horizontal axis represents time in microseconds (μsec), while the vertical axis represents the amplitude of relevant signals in volts. Timing diagram  600  shows waveforms of two signals of interest, including a waveform  610  that represents the voltage across flying capacitor  330 , and a waveform  620  that represents the voltage across output capacitor  340 . In timing diagram  600 , input voltage V IN  is assumed to be about 7.4 volts (V). In waveform  610 , the voltage across flying capacitor  330  has an average value of about 3.7 V but includes a ripple that causes it to vary between about 3.62 V and 3.78 V. The ripple across flying capacitor  330  is a triangular waveform at the switching frequency, and the average (DC) voltage is approximately equal to V IN /2. In waveform  620 , the ripple across output capacitor  340  is an asymmetric waveform at twice the switching frequency, and the average (DC) voltage depends on load current and in the illustrated example is about 3.6 V. 
         [0023]    Since the output ripple of a fixed frequency charge pump increases with the load, the inventor has discovered that the efficiency of charge pump  300  of  FIG. 3  can be improved by varying the switching frequency to obtain a constant peak-to-peak ripple. A circuit for use in phase clock generator  350  that varies the switching frequency to obtain a constant ripple will now be described. 
         [0024]      FIG. 7  illustrates in block diagram form a frequency control circuit  700  for use in phase clock generator  350  of  FIG. 3 . Frequency control circuit  700  includes a comparator  710 , a switch  720 , and an inverter  730 . Comparator  710  has a positive input for receiving a voltage labeled “V_Cfly”, a negative input, and an output for providing signal Φ 2 . Switch  720  has a first throw for receiving a first voltage labeled “V IN /2−V P ”, a second throw for receiving a second voltage labeled “V IN /2+V P ”, a common terminal connected to the negative input of comparator  710 , and a control input connected to the output of comparator  710  for receiving the Φ 2  signal. Inverter  730  has an input connected to the output of comparator  710 , and an output for providing the Φ 1  signal. 
         [0025]    Frequency control circuit  700  activates signal Φ 1  at a logic high and provides signal Φ 2  at a logic low when V_Cfly is less than V IN /2−V. When signal Φ 2  goes low, switch  720  switches the V IN /2+V P  reference voltage to the negative input of comparator  710 . During this phase flying capacitor  330  is connected in series with output capacitor  340  and the voltage across flying capacitor  330  increases. When V_Cfly exceeds V IN /2+V P , frequency control circuit  700  activates signal Φ 2  at a logic high and provides signal Φ 1  at a logic low. When signal Φ 2  goes high, switch  720  switches the V IN /2−V P  reference voltage to the negative input of comparator  710 . During this phase flying capacitor  330  is connected in parallel with output capacitor  340  and the voltage across flying capacitor  330  decreases. When V_Cfly is less than V IN /2−V P , frequency control circuit  700  again activates signal Φ 1  at a logic high and provides signal Φ 2  at a logic low, repeating the sequence. In this manner, the switching frequency of the phase clock generator will adapt to the size of the load. Accordingly, for a higher load (larger slope of the ripple on V OUT ), the switching frequency increases and for a smaller load (smaller slope of the ripple on V OUT ), the switching frequency decreases. 
         [0026]      FIG. 8  illustrates in partial block diagram and partial schematic form a power converter  800  using an integrated circuit  860  based on charge pump divider  300  of  FIG. 3 . Power converter  800  includes generally a two-cell battery  810 , an input capacitor  820 , a boost capacitor  830 , a flying capacitor  840 , and an output capacitor  850  all connected to an integrated circuit  860  in a manner that will be described as follows. Two-cell battery  810  has a positive output terminal connected to an integrated circuit terminal labeled “VIN”. Input capacitor  820  has a first terminal connected to the VIN terminal, and a second terminal connected to ground. Boost capacitor  830  has a first terminal connected to an integrated circuit terminal labeled “CB”, and a second terminal connected to an integrated circuit terminal labeled “CPP”. Flying capacitor  840  has a first terminal connected to the CPP terminal, and a second terminal connected to an integrated circuit terminal labeled “CPN”. Output capacitor  850  has a first terminal connected to an integrated circuit terminal labeled “GND” that is connected to ground, and a second terminal connected to an integrated circuit terminal labeled “VOUT” that provides the output voltage. Integrated circuit  860  also has an enable terminal labeled “EN” for receiving an externally supplied enable signal, and an analog ground terminal labeled “AGND” connected to an analog ground voltage terminal. 
         [0027]    Integrated circuit  860  includes generally a capacitive divider core  870 , a clock management block  880 , a mode control block  890 , and an output sense block  892 . Capacitive divider core  870  includes transistors  322 ,  324 ,  326 , and  328  labeled the same as corresponding elements in  FIG. 3  and connected as described with respect to  FIG. 3 . Capacitive divider core  860  has terminals connected to the VIN and GND terminals of integrated circuit  860 , terminals connected to the CPP and CPN terminals for connection to external flying capacitor  840 , a terminal connected to the CB terminal, input terminals for receiving the Φ 1  and Φ 2  clock signals, and an output terminal for providing an output voltage to the VOUT terminal. In addition to the transistors described in  FIG. 3 , capacitive divider core  870  includes a set of drivers  872  for buffering clock signals Φ 1  and Φ 2  and providing similarly labeled buffered drive signals to the gates of transistors  322  and  324 , respectively, and a set of drivers  874  for buffering clock signals Φ 1  and Φ 2  and providing similarly labeled buffered drive signals to the gates of transistors  328  and  326 , respectively. Drivers  872  and  874  are used to buffer signals Φ 1  and Φ 2  from phase clock generator  880  to drive the gates of transistors  322 ,  324 ,  326 , and  328 , which are relatively large integrated MOS transistors with high gate capacitances. 
         [0028]    Integrated circuit  860  also includes additional features useful for forming a practical integrated circuit charge pump divider that can be adapted for different environments. For example, in order to raise the gate voltage of transistor  322  to a high enough level, a voltage greater than VIN is generated by means of the bootstrap capacitor connected between terminals CPP and CB. Integrated circuit  860  also includes a mode control block  890  used to enable the operation of capacitive divider core  870  or to place it in a low power mode based on the state of the EN terminal, and an output sense block  892  used for shutdown control in the case of an output fault. In addition, integrated circuit  860  includes circuitry that provides the V_CFLY, V P , and V IN /2 voltages to clock management circuit  880  that is not shown in  FIG. 8 . 
         [0029]      FIG. 9  illustrates a graph of the relative efficiencies of the charge pump divider of  FIG. 1 , the inductive buck converter of  FIG. 2 , and the charge pump divider of  FIG. 3  versus load current. In  FIG. 9  the horizontal axis represents load current in mA using a logarithmic scale, and the vertical axis represents efficiency in percentage using a linear scale. A waveform  910  represents the efficiency of the known charge pump divider divider as previously shown in  FIG. 1 , a waveform  920  represents the efficiency of the known inductive buck converter as shown in  FIG. 2 , and a waveform  930  represents the efficiency of charge pump divider  300  of  FIG. 3 , all superimposed on common axes. As can be readily seen from  FIG. 9 , charge pump divider  300  of  FIG. 3  has about the same high peak efficiency as the capacitive divider of  FIG. 1 , but also maintains near-peak efficiency over a wide load range similar to the inductive buck converter of  FIG. 2 . Thus charge pump divider  300  avoids the disadvantages of both architectures and is suitable for use in such applications as dual-cell portable devices that operate over very wide load ranges. 
         [0030]    The power converter built on the architecture of charge pump divider  300  of  FIG. 3  is self-oscillating and the choice of a value for flying capacitor  330  will only affect the frequency and thus overall efficiency but not on the DC level and quality of VOUT. In some embodiments, it may be useful to limit the lower end of the self-oscillating frequency range to stay out of the audible frequency range, while degrading efficiency somewhat. In some embodiments, it is desirable to reduce electromagnetic interference (EMI) as well. 
         [0031]      FIG. 10  illustrates in block diagram form a frequency spreading circuit  1000  that can be added to clock management block  880  of  FIG. 8  to reduce EMI. Frequency spreading circuit  1000  includes a summing device  1010  and a noise source  1020 . Summing device  1010  has a first input for receiving an input peak voltage labeled “V P ′”, a second input, and an output for providing signal V P . Noise source  1020  is connected to ground and has an output connected to the second input of summing device  1010  for providing a noise signal thereto. Noise source  1020  injects random noise having an average value of 0 V into the peak ripple voltage signal V P ′ so that the output of summing device  1010  has an average value of V P ′ but varies randomly within a range. Noise source  1020  varies the reference level of comparator  710 , causing the actual switching frequency to vary. In this way, frequency spreading circuit  1000  introduces a jitter into the switching frequency of charge pump divider  300  to spread the emitted EMI over a frequency range proportional to the frequency range of the noise signal. The noise source may also be pseudo-random, produce shaped noise or a defined waveform shape. 
         [0032]    The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the true scope of the claims. For example in other embodiments, an integrated circuit charge pump divider can include different peripheral circuits to enable different operating modes, or remove certain features that are not needed for application-specific products. Moreover the generation of the Φ 1  and Φ 2  signals could be accomplished using two comparators each receiving a fixed threshold rather than by shared comparator  710  used in frequency control circuit  700  of  FIG. 2 . Also while capacitive divider core  320  was shown as being constructed using only N-channel MOS transistors, in other embodiments it could also be formed with only P-channel transistors or with a combination of P-channel transistors and N-channel transistors. The substitution of a P-channel transistor for N-channel transistor  322  avoids the need for bootstrap capacitor  830 , connected between terminals CB and CPP. Moreover input capacitor  820  can alternatively be connected between VIN and VOUT, which may improve the hot-plug robustness and may reduce output voltage ripple. 
         [0033]    Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.