Abstract:
Uninterruptible power supplies (UPSs), power conversion apparatus and power conversion methods are provided which may improve phase regulation of polyphase AC voltages in the presence of load imbalances. According to one embodiment, a UPS includes a DC voltage generating circuit that produces a DC voltage. A space vector domain controlled inverter couples the DC voltage generating circuit to an AC load, and produces a polyphase AC output voltage at the load by sensing a plurality of voltages at the load, transforming the plurality of sensed voltages according to a space vector (d-q) transformation to produce an output space vector, generating an error space vector from the output space vector and a reference space vector, and selectively coupling the DC voltage generating circuit to the load responsive to the error space vector. In this manner, a voltage control loop is closed in the d-q domain, which may improve per-phase regulation of the polyphase AC output. Preferably, compensation is applied to the error space vector to produce a control space vector that compensates for poles or other transfer characteristics of the forward path of the voltage control loop. In another embodiment, the reference space vector is generated by an outer voltage amplitude loop that compares a sum of the plurality of output voltages at the load to a reference voltage amplitude, generating an error amplitude voltage which is compensated and then transformed according to a space vector transformation to produce the reference space vector that serves as the set point for the inner space vector domain control loop.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to power conversion apparatus and methods, and more particularly, to apparatus and methods for producing polyphase alternating current (AC) power from a direct current (DC) source in apparatus such as uninterruptible power supplies (UPS). UPSs are power conversion devices that are commonly used to provide conditioned, reliable power for computer networks, telecommunications networks, medical equipment and the like. UPSs are widely used with computers and telecommunications devices, including but not limited to personal computers, workstations, mini computers, network servers, routers, switches, disk arrays and mainframe computers, to insure that valuable data is not lost and that the device can continue to operate notwithstanding temporary loss of an AC utility source. UPSs typically provide power to such electronic equipment from a secondary source, such as a battery, in the event that a primary alternating current (AC) utility source drops out (blackout) or fails to provide a proper voltage (brownout). 
     Referring to FIG. 1, a conventional pulse width modulated (PWM) polyphase (e.g., three-phase) UPS generates a polyphase AC output at a load  20  from a DC voltage V DC  generated between positive and negative voltage rails by a DC voltage generating circuit  10 . Depending on the configuration of the UPS, the DC voltage V DC  may be generated in a number of different ways. For example, the DC voltage V DC  may be directly generated by battery or, as shown, by DC/DC conversion of a lower battery voltage V B  generated by a battery  12 . In some configurations, the DC voltage V DC  may be generated from an AC source, or from a combination of an AC source and a DC source. The DC voltage V DC  is inverted by a polyphase PWM inverter circuit  30 , which typically includes a plurality of switches (e.g., transistors) that are selectively operated to synthesize AC voltage waveforms from the DC voltage V DC . Additional filtering may be provided to reduce harmonics generated by the switching operations. 
     In order to improve control of such PWM inverter circuits, so-called “space vector modulation” (SVM) techniques have recently been introduced. SVM techniques are commonly used in polyphase induction motor control applications, and typically involve transforming a “reference” voltage vector to a vector in a “d-q” or “space vector” coordinate domain, which is in turn used to generate a PWM switching pattern. In a closed loop motor control application, for example, the reference voltage may be a control voltage derived from an error voltage generated by a speed or voltage control loop. The vector produced by the space vector (d-q) transformation is mapped to various logical values of switching signals applied to the switching devices of a PWM inverter circuit based on its orientation in the d-q plane. A variety of mappings may be utilized, as described, for example, in the article by Hava et al. entitled “Carrier-Based PWM-VSI Overmodulation Strategies: Analysis, Comparison and Design,” IEEE Trans. on Power Electronics , Vol. 13, No. 4, pp. 674-689 (July 1998). 
     UPS&#39;s are often used to serve unbalanced polyphase loads, particularly in large-scale operations in which a single high-capacity UPS may be used to provide power to a variety of single-phase loads connected to individual phases. Although loads may be configured with a view toward minimizing phase imbalance, practical constraints in load location and use often result in significant load imbalances. Accordingly, it is generally desirable to compensate for imbalances in the loads presented to the phases of a UPS. Unfortunately, however, conventional polyphase UPS control schemes often provide poor regulation of individual phases. 
     SUMMARY OF THE INVENTION 
     According to embodiments of the present invention, UPSs, power conversion apparatus and power conversion methods are provided which may improve phase regulation of polyphase AC voltages in the presence of load imbalances. According to one embodiment of the present invention, a UPS includes a DC voltage generating circuit that produces a DC voltage. A space vector domain controlled inverter couples the DC voltage generating circuit to an AC load, and produces a polyphase AC output voltage at the load by sensing a plurality of voltages at the load, transforming the plurality of sensed voltages according to a space vector (d-q) transformation to produce an output space vector, generating an error space vector from the output space vector and a reference space vector, and selectively coupling the DC voltage generating circuit to the load responsive to the error space vector. In this manner, a voltage control loop is closed in the d-q domain, which may improve per-phase regulation of the polyphase AC output. Preferably, compensation is applied to the error space vector to produce a command space vector that compensates for poles or other transfer characteristics of the forward path of the voltage control loop. In an embodiment of the present invention, the reference space vector is generated by an outer voltage amplitude loop that compares a sum of the plurality of output voltages at the load to a reference voltage amplitude, generating an error amplitude voltage which is compensated and then transformed according to a space vector transformation to produce the reference space vector that serves as the set point for the inner, space vector domain control loop. 
     In particular, according to one embodiment of the present invention, an uninterruptible power supply (UPS) for supplying a polyphase AC output at a load includes a DC voltage generator that produces a DC voltage. A voltage sensor is configured to connect to the load and detects a plurality of output voltages at the load. A space vector domain controlled inverter is coupled to the voltage sensor and to the DC voltage generator and configured to connect to the load. The space vector domain controller inverter transforms the detected plurality of output voltages according to a space vector transformation to generate an output space vector corresponding to the detected plurality of output voltages. The space vector domain controlled inverter generates an error space vector from the output space vector and a reference space vector, and selectively couples the DC voltage generator to the load responsive to the error space vector. 
     In another embodiment of the present invention, the space vector domain controlled inverter comprises a space vector domain controller that transforms the detected plurality of output voltages according to a space vector transformation to estimate an output space vector corresponding to the detected plurality of output voltages. The space vector domain controller generates an error space vector from the output space vector and a reference space vector, and that generates a switching command signal responsive to the error space vector. A polyphase inverter circuit is coupled to the space vector domain controller and to the DC voltage generator and configured to connect to the load, and selectively couples the DC voltage generator to the load responsive to the generated switching command signal. Preferably, the space vector domain controller compensates the error space vector to generate a command space vector and generates the switching command signal responsive to the command space vector. 
     An output filter may be configured to couple the polyphase inverter circuit to the load. In one embodiment of the present invention, the output filter includes a transformer having first winding connected to the polyphase inverter circuit and a second winding configured to connect to the load. The voltage sensor detects a plurality of voltages produced at the second winding of the transformer. The space vector domain controller transforms the detected plurality of output voltages produced at the second winding of the transformer according to a space vector transformation that compensates for at least one of a phase and magnitude transformation imposed by the transformer. The polyphase inverter circuit is operative to selectively couple the DC voltage generator to the primary winding of the transformer responsive to the switching command signal generated by the space vector domain controller. 
     According to another aspect of the present invention, the space vector domain controller transforms the detected plurality of output voltages according to a first space vector transformation. The space vector domain controller generates a voltage amplitude error from the detected plurality of output voltages and a reference voltage amplitude, compensates the voltage amplitude error to produce a command voltage amplitude and transforms the command voltage amplitude according to a second space vector transformation to produce the reference space vector. The space vector domain controller preferably sums the detected plurality of output voltages to produce an output voltage amplitude and subtracts the output voltage amplitude from the reference voltage amplitude to generate the voltage amplitude error. 
     According to method aspects of the present invention, a voltage at a polyphase AC load is regulated by detecting a plurality of output voltages at the load and transforming the detected plurality of output voltages according to a space vector transformation to estimate an output space vector corresponding to the detected plurality of output voltages. An error space vector is generated from the output space vector and a reference space vector. A DC source is selectively coupled to the load responsive to the error space vector. The error space vector is preferably compensated to generate a command space vector, and the DC source is selectively coupled to the load responsive to the command space vector. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates an uninterruptible power supply (UPS) according to the prior art. 
     FIG. 2 illustrates a UPS according to an embodiment of the present invention. 
     FIG. 3 illustrates a polyphase inverter and output filter according to another embodiment of the present invention. 
     FIG. 4 illustrates a space vector domain controller according to another embodiment of the present invention. 
     FIGS. 5A-5B illustrate exemplary space vector modulation (SVM) operations. 
     FIG. 6 illustrates output current control according to yet another embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, like numbers refer to like elements. 
     FIG. 2 illustrates an uninterruptible power supply (UPS)  1  according to an embodiment of the present invention. The UPS  1  includes a DC voltage generating circuit  10  that produces a DC voltage V DC  and a space vector domain controlled inverter  100  that produces a polyphase (e.g., three phase) AC output to a load  20  from the DC voltage V DC  responsive to voltages (e.g., line to neutral voltages) sensed at the load  20  by a voltage sensor  300 . The space vector domain controlled inverter  100  includes a polyphase inverter circuit  120  that is responsive to one or more switching control signals produced by a space vector domain controller  110 , providing the polyphase AC output to the load  20  via an output filter  200 , for example, a filtering circuit including passive elements such as transformers, inductors and capacitors. 
     As shown, the DC voltage generating circuit  10  produces the DC voltage V DC  from a battery  12 . For example, the DC voltage generating circuit  10  may include a DC/DC converter circuit (not shown) that is operative to produce the DC voltage V DC  from a DC voltage V B  produced by the battery  12 . It will be appreciated, however, that the DC voltage generating circuit  10  may have any one of a variety of forms other than that illustrated in FIG.  2 . The DC voltage V DC  may be generated directly from a battery and/or from a source other than a battery, such as from an AC source. For example, in an “off-line” configuration, the UPS  1  may be configured such that the DC voltage V DC  is generated solely from a battery, with an AC source being configured to connect to the load  20  via a transfer switch (not shown) or similar arrangement. Alternatively, in an “on-line” configuration, the UPS  1  may be configured such that the DC voltage generating circuit  10  generates the DC voltage V DC  from a DC source and/or an AC source. 
     As shown, the space vector domain controlled inverter  100  has a nested loop structure, including an inner, space vector domain control loop  101 , around which a lower-bandwidth voltage amplitude loop  103  is closed. Referring to the inner control loop  101 , digital values V d  corresponding to voltages (e.g., line to neutral or line to line voltages) sensed by the voltage sensor  300  are processed by a space vector transformation circuit  102  that transforms the digital voltage values V d  into coordinate values of an output space vector V f   dq  corresponding to the polyphase AC output in a space vector (d-q) domain. The output space vector V f   dg  is subtracted from a reference space vector V r   dq  in a summing circuit  104 . The resulting error space vector V e   dq  is then compensated (e.g., filtered and/or limited) in a compensation circuit  106 , producing a command space vector V c   dq . The command space vector V c   dq  is then processed by a space vector modulation processing circuit  108  to produce one or more switching control signals for the polyphase inverter circuit  120 . 
     The outer loop  103  includes a voltage processing circuit  112  that sums the digital voltage V d  values produced by the voltage sensor  300 . The resulting output voltage amplitude |V f | is then subtracted from a reference voltage amplitude |V r | in a summing circuit  114 , producing a voltage amplitude error |V e |. The voltage amplitude error |V e | is then compensated (e.g., filtered and/or limited) in a compensation circuit  116  to produce a command voltage amplitude |V c |. The space vector transformation circuit  118  uses the command voltage amplitude |V c | along with a command phase angle φ c  to generate the reference space vector V r   dq , as will be described in greater detail below. 
     It will be appreciated that although the outer voltage amplitude loop  103  illustrated is preferably used to provide, for example, faster convergence in control of the polyphase AC output at the load  20 , the inner voltage loop  101  may be used alone, or other structures may be used to generate the reference space vector V r   dq  used as the point input to the inner, space vector domain control loop. For example, in applications, such as motor speed control, the reference space vector V r   dq  may be generated by a speed control loop, rather that a voltage amplitude loop. 
     The inner space vector domain control loop preferably processes the voltage values V d  at a greater rate than the outer loop. For example, in an exemplary 277/480V embodiment, the voltage sensor  300  may sample line-to-neutral voltages at the load  20  at a rate of 50 kHz (one every 20 μsec). The inner control loop may selectively “downsample” (or “decimate”) these voltage samples at a rate of 12.5 kHz, generating a new command space vector value every 80 μsec. The outer amplitude control loop may operate at an even slower rate, generating new command voltage amplitude |V c | values at a rate of 2.5 kHz (once every 400 μsec). It will be appreciated by those skilled in the art, however, that loop processing rates and other control parameters may be varied according to such factors as the nature of the load  20  and the control performance, e.g., transient response, stability, and accuracy, that is desired. 
     The space vector transformation circuits  102 , 118 , summing circuits  104 ,  114 , compensation circuits  106 ,  116 , and voltage processing circuit  112  are preferably implemented in a digital domain using a data processing device, for example, a microprocessor, microcontroller or digital signal processor (DSP) such as a chip of the TMS320CXX line produced by Texas Instruments. It will be appreciated, however, that these components can, in general, be implemented using other circuitry, such as discrete circuits or integrated circuits such as programmable logic devices (PLDs), application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). In addition, although the preferred embodiments illustrated perform control functions in a digital domain, functions of many of the illustrated components can be implemented in the analog domain using analog signal processing circuitry. 
     For the embodiment illustrated in FIG. 1, the polyphase inverter circuit  120  supplies the load  20  via an output filter  200 , which may simply be an “LC” low pass filter. However, in an embodiment of the present invention illustrated in FIG. 3, a three-phase, four-wire output (e.g., with an isolated neutral) is produced from a three-phase output. Accordingly, as illustrated in FIG. 3, an output filter  200 ′ may include a “delta-wye” transformer  210  that includes a primary winding  211  with phases a, b, c connected in a delta configuration, inductively coupled to a secondary winding  212  with phases A, B, C connected in a wye configuration. Besides providing a way to create a neutral N, the output filter  200 ′ can help reduce harmonics created by the inverter circuit  120 ′, here shown as including switches  122  connected in a conventional pulse-width modulator (PWM) configuration and responsive to switch command signals SC. Filter inductance Lf may include leakage inductance of the transformer  210  and other inductances connected to the primary and/or secondary windings of the transformer  210 . Filter capacitance Cf may be delta-connected, wye-connected, or a combination of both. The switches  122  of the inverter circuit  120 ′ may comprise any of a number of different types of switching devices, such as insulated gate bipolar transistors (IGBTs). 
     For purposes of the following discussion, it will be assumed that a three-phase “wye” output is to be generated at the load  20  illustrated in FIGS. 2 and 3. The voltage sensor  300  is assumed to sample line-to-neutral voltages at the wye-connected load  20 , producing corresponding digital values. The voltage processing circuit  112  of the outer voltage amplitude control loop sums and, preferably, scales and filters, these digital values for presentation to the summing circuit  114 . The summing circuit  114  subtracts the value produced by the voltage processing circuit  112  from the reference voltage amplitude |V r | to produce the voltage amplitude error |V e |. The compensation circuit  116  may implement, for example, a simple proportional integration (PI) compensation scheme to produce the command voltage amplitude |V c |. For example, the compensation circuit  116  may implement an algorithm along the following lines: 
      y n =y n−1 +α*x n , 
     where y n  represents the output of the compensation circuit for an nth iteration, x n  represents the input to the compensation circuit for the nth iteration, y n−1  denotes the output of the compensation circuit for a preceding n−1th iteration, and α denotes a constant. 
     The command phase angle φ c  can be generated in a number of different ways. For example, an analog sine wave generator may be used to generate a reference sine wave from which command phase angles φ c  can be computed by sampling the reference sine wave and computing the corresponding angle value. This sine wave generator may, for example, be synchronized with a particular phase of an AC source (e.g., a utility source which powers the load  20  under normal conditions), such that the command phase angle φ c  may be aligned to the AC source. Alternatively, command phase angle values can be synthesized in a digital domain using appropriate computations. These and other techniques for generating a command phase angle φ c  are well-know to those skilled in the art, and will not be discussed in greater detail herein. 
     FIG. 4 illustrates exemplary space vector domain control loop components according to an embodiment of the present invention. Referring to FIG. 4 in conjunction with FIG. 2, and assuming the inverter/filter configuration of FIG. 3, the command voltage amplitude |V c | and the command phase angle φ c  provide sufficient information from which an appropriate reference space vector V r   dq  can be synthesized by the space vector transformation circuit  118 ′. Using a convention by which the “a” phase voltage V a  generated by the polyphase inverter circuit  120 ′ is aligned with the “d” axis, the components d r , q r  of a reference space vector V r   dq  may be generated from the command voltage amplitude |V c | and the command phase angle φ c  according to the equations: 
     
       
         d r =β|V c |cos(φ c ), 
       
     
     and 
      q r =β|V c |sin(φ c ), 
     where β is a constant. 
     Due to the effects of the output filter  200 ′, the mapping performed by the space vector transformation circuit  102 ′ is generally more complex. The delta-wye transformation introduced by the transformer  210  can introduce a phase and magnitude transformation. The mapping performed by the space vector transformation circuit  102 ′ should account for this transformation. Assuming that the primary and secondary windings  211 ,  212  of the transformer  210  have the same number of turns, the transformer  210  produces a phase shift of 30° and a gain of {square root over (3)} (˜1.732) for the secondary line-to-neutral voltages V AN , V BN , V CN  with respect to corresponding ones of the line voltages V a , V b , V c  (where the voltages V a , V b , V c  are with respect to a “virtual neutral” on the primary side). For the illustrated embodiment, the following equations may be used to transform the phase to neutral voltage values V AN , V BN , V CN  into the space vector (d-q) domain components d f , q f  of the output space vector V f   dq :            d   f     =       (       V   AN     -     V   BN       )     *       3     2         ,   and             q   f     =         (       V   AN     -     V   BN       )     2     -       V   CN     .                              
     These equations serve to line up the secondary vector with the primary vector for the transformer shown in this embodiment. As will be appreciated by those skilled in the art, the mapping shown uses line to neutral voltage sensing; if the line to line voltages on the secondary side of the transformer  210  are sensed instead, a different mapping set of equations would be used. Similarly, if the transformer  210  is not present, e.g., if the load is connected directly to the inverter circuit  120 ′ and the line-to-line voltages sensed at this point, a different space vector transformation would be used. 
     Components d e , q e  of the error space vector V e   dq  are generated by subtracting respective ones of the feedback components d f , q f  from respective ones of the reference space vector components d r , q r . The error space vector components d e , q e  are then compensated by processing them in a compensation circuit  106 ′ (e.g., according to a digital compensation algorithm) to produce components d c , q c  of the command space vector V c   dq . The compensation preferably compensates for characteristics of the output filter  200 ′. The compensate may also compensate for known or estimated characteristics of the load  20 . Examples of DSP-based control algorithms are described, for example, in  Digital Control System Analysis and Design  by C. L. Phillips and H. T. Nagle, 2 nd  ed. (1990). Modeling and testing of such algorithms can be easily done using a software tool such as P-Sim, produced by Power Sim of Vancouver, BC. 
     For the embodiment illustrated in FIG. 3, in which an output filter  200 ′ is provided, the space vector compensation implemented by the compensation circuit  106 ′ preferably compensates for a complex pole introduced by the output filter  200 ′. For example, for a complex pole at 811 Hz, the following algorithm can be used at a sampling rate of 12.5 kHz (80 μsec) to provide modest gain and dampen the complex pole: 
     
       
         y c     n   =6.0*(0.256*x e     n   −0.449*x e     n−1   +0.229*x e     n−2   )−0.395*y c     n−1   +0.461*y c     n−2     
       
     
     where x e  is one of the d or q error space vector components d e , q e , y c  is a corresponding one of the d or q components d c , q c  of the command space vector V c   dq , and the subscripts n, n−1, and n−2 refer to an nth iteration and preceding n−1th and n−2th iterations. The coefficients of this algorithm can be adaptively changed, for example, if the pole shifts or otherwise changes due to load or other parametric changes. 
     Still referring to FIG. 4, the components d c , q c  of the command space vector V c   dq  are passed to a switching command signal generator  108 ′, which implements a space vector modulation (SVM) scheme to generate switching command signals SC that operate switches of a polyphase inverter circuit, such as the switches  122  of the polyphase inverter circuit  120 ′ of FIG.  3 . Potential advantages of SVM include ease of implementation with a microcontroller, DSP or other processor, and ease in implementing a discontinuous PWM (DPWM) strategy. DPWM has two potential advantages: (1) it can reduce switching losses; and (2) it can deliver increased voltage through overmodulation. Referring to the PWM inverter circuit  120 ′ illustrated in FIG. 3, in a discontinuous modulation scheme, one of the switches in a leg of the circuit is left “on” for 60 electrical degrees, while the other switch in the leg remains “off” during the same 60-degree period. Each of these 60-degree periods is referred to as a “sector”. 
     Discontinuous operation in a six-switch, three-phase inverter, such as that illustrated in FIG. 3, typically requires that a “positive” switching device, i.e., a switching device that couples its corresponding phase conductor to the positive DC rail, have its 60 degrees of operation when the voltage on its corresponding phase conductor is higher than the voltages on the other two phase conductors. Likewise, a “negative device,” i.e., a device that couples its corresponding phase conductor to the negative DC rail, typically must have its 60 degrees of discontinuous operation when the voltage on its corresponding phase conductor is less (more negative) than the voltages on the other two phase conductors. Consequently, this constrains the 60-degree period of a given switch to fall within a 120-degree window. 
     Accordingly, the sector location of the dq command space vector V c   dq  can be used by switching command signal generating circuit  108 ′ to determine the appropriate switching command signals SC to operate of switches of a polyphase inverter circuit. Several different types of SVM techniques can be utilized, each of which may provide different distortion, switching loss and other operating characteristics. For example, various ones of the SVM schemes described in van der Broeck et al., “Analysis and Realization of a Pulse Width Modulator Based on Voltage Space Vectors,” IEEE Transactions on Industrial Applications, vol. 24, no. 1, pp. 142-150 (February 1998), Holtz, “Pulsewidth Modulation—A Survey,” IEEE Transactions on Industrial Electronics, vol. 39, no. 5, pp. 410-420, and in Stefanovic et al., “Space Vector PWM Voltage Control with Optimized Switching Strategy,” IEEE IAS-1992 Annual Meeting, pp. 1025-1033 (1992) may be used with the present invention. 
     The aforementioned paper by Hava et al entitled “Carrier-Based PWM-VSI Overmodulation Strategies: Analysis, Comparison and Design” compares overmodulation SVM schemes, including schemes referred to a “Depenbrock” and “Ogasawara” schemes, which may be used with the present invention, and which are conceptually illustrated in FIGS. 5A and 5B, respectively. In FIGS. 5A and 5B, a six sector map overlays the d-q axis, with each sector comprising 60 degrees. In a first sector S 1 , phase “a” is coupled to positive DC rail; in a second sector S 2 , phase “c” is held to the negative DC rail; in a third sector S 3 , phase “b” is held to the positive DC rail; in a fourth sector S 4 , phase “a” is held to the negative DC rail; in a fifth sector S 5 , phase “c” is held to the positive DC rail; and in a sixth sector S 6 , phase “b” is held to the negative DC rail. With the sectors as such, and adhering to the convention that phase “a” is aligned with the “d” axis, the shaded areas of FIGs. SA and SB indicate allowable areas for which sector  1  operation can occur under the respective Depenbrock and Ogasawara techniques. A conventional technique for determining which sector the command space vector lies utilizes a sine look-up table. It is noted here that if the Ogasawara method is used, a phase shift caused by “closing the loop” may push the sector beyond its allowable 120-degree window. 
     An embodiment of the present invention uses an Ogasawara scheme and solves this problem by determining the sector after the d-q compensation. According to this embodiment of the present invention, the appropriate PWM operational sector for given d-q command space vector may be determined by the following pseudocode, where the variables SpaceVectorlndex_D and SpaceVectorIndex_Q denote the d and q components d c , q c , respectively, of the command space vector V c   dq : 
     
       
         
               
             
               
               
             
               
               
             
               
             
               
               
             
               
               
             
               
             
               
               
             
               
               
             
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
               
               
             
           
               
                   
               
             
             
               
                 TEST D-Q QUADRANT, THEN DETERMINE PWM INDEX 
               
               
                 SECTOR: 
               
               
                 CHECK QUAD 2: 
               
             
          
           
               
                   
                 IF SpaceVectorIndex_D &lt;=0 
               
               
                   
                 AND SpaceVectorIndex_Q &gt; 0 
               
               
                   
                 THEN in QUAD 2 
               
             
          
           
               
                   
                 IF SpaceVectorIndex_Q/2 + 0.866*SpaceVectorIndex_D &lt; 0 
               
               
                   
                 THEN in Sector 3 
               
               
                   
                 ELSE in Sector 2 
               
             
          
           
               
                 CHECK QUAD 3: 
               
             
          
           
               
                   
                 IF SpaceVectorIndex_D &lt;=0 
               
               
                   
                 AND SpaceVectorIndex_Q &lt;=0 
               
               
                   
                 THEN in QUAD 3 
               
             
          
           
               
                   
                 IF SpaceVectorIndex_Q/2 − 0.866*SpaceVectorIndex_D &lt; 0 
               
               
                   
                 THEN in Sector 5 
               
               
                   
                 ELSE in Sector 4 
               
             
          
           
               
                 CHECK QUAD 1: 
               
             
          
           
               
                   
                 IF SpaceVectorIndex_D &gt; 0 
               
               
                   
                 AND SpaceVectorIndex_Q &gt; 0 
               
               
                   
                 THEN in QUAD 1 
               
             
          
           
               
                   
                 IF SpaceVectorIndex_Q/2 − 0.866*SpaceVectorIndex_D &lt; 0 
               
               
                   
                 THEN in Sector 1 
               
               
                   
                 ELSE in Sector 2 
               
             
          
           
               
                 CHECK QUAD 4: 
               
             
          
           
               
                   
                 IF SpaceVectorIndex_D &gt; 0 
               
               
                   
                 AND SpaceVectorIndex_Q &lt;=0 
               
               
                   
                 THEN in QUAD 4 
               
             
          
           
               
                   
                 IF SpaceVectorIndex_Q/2 + 0.866*SpaceVectorIndex_D &lt; 0 
               
               
                   
                 THEN in Sector 5 
               
               
                   
                 ELSE in Sector 6 
               
             
          
           
               
                   
                 IF SpaceVectorIndex_D &lt;= 0 
               
             
          
           
               
                   
                 X1 = ABS(X1) 
               
               
                   
                 IF SpaceVectorIndex_Q &gt; 0 
               
             
          
           
               
                   
                 If ((SpaceVectorIndex_Q/2) − X1) &lt;=0) 
               
             
          
           
               
                   
                 INDEX SECTOR = 3 
               
             
          
           
               
                   
                 ELSE 
               
             
          
           
               
                   
                 INDEX SECTOR = 2 
               
             
          
           
               
                   
                 ELSE IF ABS[SpaceVectorIndex_Q/2] − X1 &lt;= 0 
               
             
          
           
               
                   
                 INDEX SECTOR = 4 
               
             
          
           
               
                   
                 ELSE 
               
             
          
           
               
                   
                 INDEX SECTOR = 5 
               
             
          
           
               
                   
                 ELSE IF SpaceVectorIndex_Q &gt; 0 
               
             
          
           
               
                   
                 IF (SpaceVectorIndex_Q/2 − X1) &lt;= 0) 
               
             
          
           
               
                   
                 INDEX SECTOR = 1 
               
             
          
           
               
                   
                 ELSE 
               
             
          
           
               
                   
                 INDEX SECTOR = 2 
               
             
          
           
               
                   
                 ELSE IF (ABS[SpaceVectorIndex_Q/2] − X1 &lt;= 0) 
               
             
          
           
               
                   
                 INDEX SECTOR 6 
               
             
          
           
               
                   
                 ELSE 
               
             
          
           
               
                   
                 INDEX SECTOR 5 
               
               
                   
                   
               
             
          
         
       
     
     It will be appreciated that the above-described pseudocode implementation is offered for exemplary purposes, and that other techniques may be used with the present invention. For example, other techniques for implementing an Ogasawara scheme can be used, as well as techniques that implement other SVM schemes, such as Depenbrock schemes. 
     Referring to FIGS. 2-4, a DC voltage may arise in the output produced by the polyphase inverter circuit  120 ,  120 ′ due to offset voltages of amplifiers used in the voltage sensor  300  and/or numeric underflow in processing in the control loop components of the space vector domain controller  100 ,  100 ′. This DC voltage can cause potentially destructive currents to flow in the primary winding  211  of the transformer  210 . According to an embodiment of the present invention, this DC voltage can be reduced by inclusion of a high pass filter in the compensation circuit  106 ,  106 ′ applied in the space vector domain controller  100 ,  100 ′. As with the other compensation, this high pass filter is preferably implemented in a digital domain using a microcontroller, DSP or similar computing devices, but can be implemented using other digital or analog circuitry. An exemplary algorithm for implementing such a high pass filter is given by: 
     
       
         y n =x n −x n−1 +γ* y n−1 , 
       
     
     where x n  represents an input “d” or “q” component value for an nth iteration, y n  represents a d or q component of the filter output for the nth iteration, x n−1  represents an input d or q component value for a preceding n−1th iteration, y n−1  represents a d or q component of the filter output for the n−1th iteration, and γ is a constant. 
     A UPS often needs to handle excessive overloads or faults on its output while remaining operational. A conventional technique for dealing with such an event is to add analog circuitry in the signal flow path that takes autonomous protective action in response to such an event. According to another aspect of the present invention, protective capability may be combined with the voltage control described above. Referring to FIG. 6, a switching command signal generation circuit  108 ″ that performs space vector modulation functions responsive to a command voltage V c   dq  (e.g., as described with reference to FIG. 4) is also responsive to current values I a , I b , Ib acquired by a current sensor  610  to limit the currents generated by the polyphase inverter circuit, where the current values I a , I b , I b  correspond to currents in the phases a, b, c supplied by the polyphase inverter circuit  120 ′. To implement a current limit, for example, the switching command signal generator circuit  108 ″ may compare the sensed current values I a , I b , I b  with a maximum value, and may act to shut down selected switches in the polyphase inverter circuit  120 ′ if one or more of the sensed currents I a , I b , I b  exceeds the maximum value. The acquisition and comparison of the sensed currents I a , I b , I b  can be done at higher rates than the voltage control loops (e.g., every 20 μsec) to accomplish an effective “current limit”. 
     In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.