Abstract:
A pipelined digital-to-analog converter includes a first sub analog-to-digital converter and a multiplying digital-to-analog converter. The first sub analog-to-digital converter, which is responsive to a first reference voltage, is configured to convert a first analog signal into a first digital signal. The multiplying digital-to-analog converter is responsive to the first analog signal, the first digital signal and a second reference voltage. The second reference voltage is generated independently of the first reference voltage in order to enhance the high frequency performance characteristics of the pipelined digital-to-analog converter.

Description:
REFERENCE TO PRIORITY APPLICATION 
   This application claims priority to Korean Patent Application No. 2004-116997, filed Dec. 30, 2004, the disclosure of which is hereby incorporated herein by reference. 
   FIELD OF THE INVENTION 
   The present invention relates to integrated circuit devices and, more particularly, to analog-to-digital converters. 
   BACKGROUND OF THE INVENTION 
   An analog-digital converting device converts an analog signal into a digital signal, and a pipelined analog-digital converting device is formed of a plurality of such analog-digital converting devices connected to one another.  FIG. 1  is a block diagram of a conventional pipelined analog-digital converting device  101 . Referring to  FIG. 1 , the conventional pipelined analog-digital converting device  101  includes first through n th  sub analog-digital converters  111   a  through  111   n , first through n th  multiplying digital to analog converters (MDACs)  121   a  through  121   n , and a sample/hold amplifier  131 . All of the first through n th  sub analog-digital converters  111   a  through  111   n , which may be flash analog-digital converters, and the first through n th  MDACs  121   a  through  121   n , use one reference voltage Vref. In other words, the first through n th  sub analog-digital converters  111   a  through  111   n , and the first through n th  MDACs  121   a  through  121   n  receive the reference voltage Vref supplied by a reference voltage generator (not shown). 
     FIG. 2  illustrates waveforms of signals transmitted to the pipelined analog-digital converting device  101  of  FIG. 1  and consequent operations of some elements of the pipelined analog-digital converting device  101 . In  FIG. 2 , S.S, S.H, R.S, S.C, and S.A are abbreviations for signal sampling, signal holding, reference sampling, signal comparing, and signal amplifying, respectively. Referring to  FIG. 2 , while a clock signal CK is at a high level (tk 1 ), the first sub analog-digital converter  111   a  samples an analog signal A 1  output from the sample/hold amplifier  131  of  FIG. 1 . At this time, the first MDAC  121   a  of  FIG. 1  samples the reference voltage Vref. While the clock signal CK is at the high level (tk 1 ), the first sub analog-digital converter  111   a  samples the reference voltage Vref and the first MDAC  121   a  amplifies the analog signal A 1 . 
   When the reference voltage Vref is applied to the pipelined analog-digital converting device  101 , the reference voltage Vref is stabilized at a constant level after some fluctuations during each clock cycle. When the operating frequency of the pipelined analog-digital converting device  101  is high, all operations are performed while the reference voltage Vref fluctuates. Such fluctuations of the reference voltage Vref may cause errors in the first through n th  MDACs  121   a  through  121   n , whose precision is required. To prevent such errors, the operating frequency of the pipelined analog-digital converting device  101  can be lowered. 
   In order to use a reference voltage that does not fluctuate, at a high operating frequency, a large capacity reference voltage generator may be used, resulting in an increase in the size of the reference voltage generator and high manufacturing costs. The reference voltage generator may be connected to a large external capacitor through a pin at the analog-digital converting device  101  and the reference voltage Vref generated by the reference voltage generator may be supplied to the capacitor. However, in this case, a dedicated pin is additionally required. 
   SUMMARY OF THE INVENTION 
   The present invention provides a pipelined analog-digital converting device that operates stably by reducing the fluctuations of a reference voltage. According to an aspect of the present invention, there is provided a pipelined analog-digital converting device including a first node to which a first reference voltage is applied, and a second node to which a second reference voltage is applied. At least one sub analog-digital converter, which is connected to the first node, receives an analog signal, converts the analog signal using the first reference voltage, and outputs a digital signal. At least one multiplying digital-analog converter, which is connected to the second node, receives a digital signal output from a corresponding sub analog-digital converter and an analog signal input to the corresponding sub analog-digital converter, converts the digital signal output from the corresponding sub analog-digital converter into an analog signal using the second reference voltage, compares the generated analog signal with the analog signal input to the corresponding sub analog-digital converter, and amplifies and outputs the difference between the analog signals. A last sub analog-digital converter, which is connected to the second node, receives an analog signal output from a corresponding multiplying digital-analog converter, converts the analog signal using the second reference voltage, and outputs a digital signal. 
   A first sub analog-digital converter of the at least one sub analog-digital converter may output a most significant bit of a digital signal output from the pipelined analog-digital converting device and the last sub analog-digital converter may output a least significant bit of the digital signal output from the pipelined analog-digital converting device. The device may further include a corrector correcting a digital signal generated by the at least sub analog-digital converter. 
   Each of the at least one multiplying digital-analog converter may include a sub digital-analog converter receiving a digital signal output from a corresponding sub analog-digital converter, converting the digital signal into an analog signal, and outputting the analog signal. A comparator is also configured to receive the analog signal output from the sub digital-analog converter and an analog signal input to the corresponding sub analog-digital converter. The comparator compares these analog signals, and outputs the difference between the analog signals. An amplifier is provided for amplifying and outputting the output of the comparator. 
   The device may further include a sample/hold amplifier, which transmits an analog signal to the first sub analog-digital converter of the at least one sub analog-digital converter, and a first multiplying digital-analog converter of the at least one multiplying digital-analog converter. At least one clock signal may be input to the at least one sub analog-digital converter and the at least one multiplying digital-analog converter. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram of a conventional pipelined analog-digital converting device; 
       FIG. 2  illustrates waveforms of signals transmitted to the pipelined analog-digital converting device of  FIG. 1  and operations of some elements of the pipelined analog-digital converting device; 
       FIG. 3  is a block diagram of a pipelined analog-digital converting device according to an embodiment of the present invention; 
       FIG. 4  is a detailed block diagram of a first MDAC illustrated in  FIG. 3 ; 
       FIG. 5  illustrates waveforms of signals transmitted to the pipelined analog-digital converting device of  FIG. 3  and operations of some elements of the pipelined analog-digital converting device; and 
       FIG. 6  is a block diagram of a 4-bit pipelined analog-digital converting device. 
   

   DETAILED DESCRIPTION OF THE INVENTION  
   The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth therein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Like reference numerals in the drawings denote like elements. 
     FIG. 3  is a block diagram of a pipelined analog-digital converting device  301  according to an embodiment of the present invention. Referring to  FIG. 3 , the pipelined analog-digital converting device  301  includes a sample/hold amplifier  331 , a first reference voltage generator  341 , a second reference voltage generator  342 , first and second nodes  351  and  352 , first through n th  sub analog-digital converters  311   a  through  311   n , first through (n−1) th  multiplying digital to analog converters (MDACs)  321   a  through  321   n− 1, and a digital corrector  361 . 
   The sample/hold amplifier  331  repeatedly samples and holds an analog signal input from an external source at regular intervals and outputs an analog signal AN 1 . The first reference voltage generator  341  generates a first reference voltage Vref 1 , and the second reference voltage generator  342  generates a second reference voltage Vref 2 . The first reference voltage Vref 1  and the second reference voltage Vref 2  may be set at equal or different magnitudes. However, the second reference voltage generator  342  may be more precise than the first reference voltage generator  341 . 
   The first and second nodes  351  and  352  are connected to the first and second reference voltage generators  341  and  342 , respectively. The first and second nodes  351  and  352  are needed to externally connect the first and second reference voltage generators  341  and  342  to the pipelined analog-digital converting device  301 . When the first and second reference voltage generators  341  and  342  are installed within the pipelined analog-digital converting device  301 , the first and second nodes  351  and  352  are not needed. 
   The first through (n−1) th  sub analog-digital converters  311   a  through  311   n− 1 are connected to the first node  351  and receive the first reference voltage Vref 1  generated by the first reference voltage generator  341 . The first through (n−1) th  sub analog-digital converters  311   a  through  311   n− 1 respectively receive first through (n−1) th  analog signals AN 1  through ANn- 1 , convert the first through (n−1) th  analog signals AN 1  through ANn−1 using the first reference voltage Vref 1 , and output first though (n−1) th  digital signals DN 1  through DNn−1. 
   The n th  sub digital-analog converter  311   n  receives an n th  analog signal ANn output from the (n−1) th  MDAC  321   n− 1, converts the n th  analog signal ANn using the second reference voltage Vref 2 , and outputs the n th  digital signal DNn. The first sub analog-digital converter  311   a  receives the first analog signal AN 1  output from the sample/hold amplifier  331 . The second through n th  sub analog-digital converters  311   b  through  311   n  receive the second through n th  analog signals AN 2  through ANn output from the first through (n−1) th  MDACs  321   a  through  321   n− 1. All of the first through n th  sub analog-digital converter  311   a  through  311   n  may be flash analog-digital converters. 
   The first through (n−1) th  MDACs  321   a  through  321   n− 1 are connected to the second node  352  and receive the second reference voltage Vref 2  generated by the second reference voltage generator  342 . The first through (n−1) th  MDACs  321   a  through  321   n− 1 receive digital signals output from the first through (n−1) th  sub analog-digital converters  311   a  through  311   n− 1 and the first through (n−1) th  analog signals DN 1  through DNn−1. 
   The first through (n−1) th  MDACs  321   a  through  321   n− 1 respectively convert the digital signals output from the first through (n−1) th  sub analog-digital converters  311   a  through  311   n− 1 into the second through n th  analog signals AN 2  through ANn, compare the second through n th  analog signals AN 2  through ANn with the first through (n−1) th  analog signals AN 1  through ANn−1, and amplify and output the differences between the compared analog signals. 
   At this time, the first MDAC  321   a  receives the first analog signal AN 1  output from the sample/hold amplifier  331 . The configurations of the first through (n−1) th  MDACs  321   a  through  321   n− 1 will be described later in detail with reference to  FIG. 4 . 
   The digital corrector  361  corrects the first through (n−1) th  digital signals DN 1  through DNn−1 output from the first through (n−1) th  sub analog-digital converters. In other words, since errors may be contained in the first through (n−1) th  digital signals DN 1  through DNn−1 output from the first through (n−1) th  sub analog-digital converters, the digital corrector  361  corrects such errors. However, the digital corrector  361  does not correct the n th  digital signal output from the n th  sub analog-digital converter  311   n . Therefore, the n th  sub analog-digital converter  311   n  is designed with precision to prevent errors. 
     FIG. 4  is a detailed block diagram of the first MDAC  321   a  illustrated in  FIG. 3 . Referring to  FIG. 4 , the first MDAC  321   a  includes a first sub digital-analog converter  411 , a comparator  421 , and an amplifier  431 . The first sub digital-analog converter  411  receives the first digital signal DN 1  output from the first sub analog-digital converter  311   a  of  FIG. 3 , converts the first digital signal DN 1  into a first analog signal ANA 1 , and outputs the first analog signal ANA 1 . The comparator  421  receives the first analog signal ANA 1  output from the first sub digital-analog converter  411  and the first analog signal AN 1  input to the first sub analog-digital converter  311   a  of  FIG. 1 , compares the first analog signal ANA 1  with the first analog signal AN 1 , and outputs the difference between them. The amplifier  431  amplifies the signal output from the comparator  421  and outputs the second analog signal AN 2  as an output signal of the first MDAC  321   a . The configurations of the second through (n−1) th  DMACs  321   b  through  321   n− 1 are identical to that of the first MDAC  321   a.    
     FIG. 5  illustrates waveforms of signals transmitted to the pipelined analog-digital converting device  301  of  FIG. 3  and consequent operations of some elements of the pipelined analog-digital converting device  301 . In  FIG. 5 , S.S, S.H, R.S, S.C, and S.A are abbreviations for signal sampling, signal holding, reference sampling, signal comparing, and signal amplifying, respectively. Referring to  FIGS. 3 and 5 , clock signals CK 1  and CK 2  are transmitted to the first through n th  sub analog-digital converters  311   a  through  311   n  of  FIG. 3  and the first through (n−1) th  MDACs  321   a  through  321   n− 1. 
   While clock signal CK 2  is at a high level (tk 2 ), the first sub analog-digital converter  311   a  of  FIG. 3  samples the first analog signal A 1  output from the sample/hold amplifier  331  of  FIG. 3 . At this time, the first MDAC  321   a  of  FIG. 3  samples the first reference voltage Vref 1  of  FIG. 3 . While the clock signal CK 2  is at the high level (tk 2 ), the first sub analog-digital converter  311   a  samples the first reference voltage Vref 1  and the first MDAC  321   a  of  FIG. 3  amplifies the first analog signal A 1 . 
   During tk 2 , the second reference voltage Vref 2  of  FIG. 3  applied to the first MDAC  321   a  of  FIG. 3  is maintained constant without fluctuations. Thus, the first MDAC  321   a  of  FIG. 3  can stably perform an amplifying operation. Also, the second through (n−1)th MDACs  321   b  through  321   n− 1 can stably perform the amplifying operations using the constant second reference voltage Vref 2  of  FIG. 3 . 
   Since the second reference voltage Vref 2  applied to the first through (n−1) th  MDACs  321   a  through  321   n− 1 is different from the first reference voltage applied to the first through (n−1) th  sub analog-digital converters  311   a  through  311   n− 1, the pipelined analog-digital converting device  301  of  FIG. 3  can stably perform a converting operation. 
     FIG. 6  is a block diagram of a 4-bit pipelined analog-digital converting device  601  according to an embodiment of the present invention. Referring to  FIG. 6 , the 4-bit pipelined analog-digital converting device  601  includes a sample/hold amplifier  631 , a first reference voltage generator  641 , a second reference voltage generator  642 , first and second sub analog-digital converters  611  and  612 , an MDAC  621 , and a digital corrector  661 . 
   The converting operation of the 4-bit pipelined analog-digital converting device  601  will now be described with reference to  FIG. 6 . It is assumed that 0.84[V] is output from the sample/hold amplifier  631  and the voltage level of an analog signal AP 1  output from the sample/hold amplifier  631  is between 0[V] and 1[V]. 
   The 0.84[V] output from the sample/hold amplifier  631  is converted into binary code by the first sub analog-digital converter  611 . As shown in Table 1 below, the first and second sub analog-digital converters  611  and  612  classify one volt into four 0.25-volt phases. The first and second sub analog-digital converters  611  and  612  sample voltages of the input analog signals AP 1  and AP 2  and determine to which the sampled voltages of the analog signals AP 1  and AP 2  belong. 
   
     
       
             
             
             
           
         
             
                 
               TABLE 1 
             
             
                 
                 
             
             
                 
               Voltage Level (Volt) 
               Binary Code 
             
             
                 
                 
             
           
           
             
                 
                 0~0.25 
               00 
             
             
                 
               0.25~0.5 
               01 
             
             
                 
                0.5~0.75 
               10 
             
             
                 
               0.75~1.0 
               11 
             
             
                 
                 
             
           
        
       
     
   
   As shown in Table 1, since 0.84 volt is between 0.75 and 1.0 volt, the first sub analog-digital converter  611  outputs “11.” 
   The binary code “11”, i.e. a digital signal, output from the first sub analog-digital converter  611  is transmitted to a sub digital-analog converter  623  included in the MDAC  621 . The sub digital-analog converter  623  converts “11” into an analog signal APP 1 . In other words, since “11” indicates a voltage between 0.75V and 1V, the sub digital-analog converter  623  outputs a 0.75V analog signal APP 1 . 
   A comparator  625  included in the MDAC  621  receives the analog signal AP 1  output from the sample/hold amplifier  631  and the analog signal APP 1  output from the sub digital-analog converter  623  and outputs a voltage equal to the difference between the analog signals AP 1  and APP 1 . Specifically, the voltage of the analog signal AP 1  output from the sample/hold amplifier  631  is 0.84V and the voltage of the analog signal APP 1  output from the sub digital-analog converter  623  is 0.75V. Therefore, the difference between the analog signals AP 1  and APP 1  is 0.09V. 
   An amplifier included in the MDAC  621  amplifies and outputs a 0.09V analog signal output from the comparator  625 . The amplifier  627  amplifies the 0.09V fourfold and outputs 0.36V. 
   The second sub analog-digital converter  612  receives and converts the 0.36V output from the MDAC  621  and outputs a digital signal “01.” The digital corrector  661  corrects a digital signal DP 1  output from the first sub analog-digital converter  611 . The 4-bit pipelined analog-digital converting device  601  receives and converts the 0.84-volt analog signal into a digital signal “1101.” 
   The 4-bit analog-digital converting device  601  may include three MDACs and four sub analog-digital converters. In this case, each of the MDACs generates a digital signal. 
   As described above, an analog-digital converting device according to the present invention receives different reference voltages from two reference voltage generators. Therefore, the analog-digital converting device has the following advantages. 
   First, MDACs operate stably since no time is required to receive stable reference voltages that do not fluctuate. 
   Second, since the MDACs operate stably, the operating frequency of the analog-digital converting device can be increased. Accordingly, the analog-digital converting device can be employed by a system in which high-speed operation is required. 
   Third, digital signals generated by sub analog-digital converters are corrected by a digital corrector. Thus, the sub analog-digital converters can receive reference voltages generated by a low-precision reference voltage generator, and the MDACs and the last sub analog-digital converter whose precision is required can receive a reference voltage generated by a high-precision reference voltage generator. Therefore, the precision of the analog-digital converting device is enhanced. 
   Fourth, since the digital signals generated by the sub analog-digital converters to which a first reference voltage is applied are corrected by the digital corrector, the analog-digital converting device is not affected by an offset between the first reference voltage and a second reference voltage. 
   While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.