Abstract:
A transistor amplifier including a bipolar transistor supplied with an input signal and a field effect transistor which is directly connected to an output electrode of the bipolar transistor to amplify a signal applied thereto. The transistor amplifier has a protective circuit which senses the load impedance and actuates a protective means across an input terminal of the transistor amplifier when the sensed load impedance is lower than a predetermined value. Accordingly, the transistor amplifier is protected against overload conditions.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The field of art to which this invention pertains is a transistor amplifier and more particularly a transistor amplifier having a protective circuit. 
     2. Description of the Prior Art 
     Transistor amplifiers particularly power transistor amplifiers for amplifying audio signals have been provided with protective circuits for protecting a power transistor from being damaged when a load, for example, a loudspeaker is short-circuited. There have been proposed various types of protective circuits. For example, there are methods of sensing the heat of a power transistor, and decoupling its input stage or its load in response to excessive heating. This heat detection is reliable but slow to respond to overload. Other methods of detecting current flowing through the power transistor have been used, however if the load is capacitive, such methods are not effective. A method of eliminating the above defect is disclosed in U.S. Pat. No. 3,904,979, in which there is described an embodiment to protect a power transistor even when the load is capacitive. 
     Recently, field effect transistors (hereinafter referred to as an FET) having characteristics similar to that of a triode have been used as power transistors. In such an arrangement, as the voltage applied to its gate electrode is increased from a negative voltage to ground potential, the drain current is accordingly increased. In a transistor amplifier using an FET, the input signal is shunted by a control signal from an overload detection circuit, but it is undesirable to hold the gate electrode of the FET in the ground potential. The reason is that if the gate voltage is equal to ground potential, the drain current may increase to the point where the output transistor is destroyed. 
     SUMMARY OF THE INVENTION 
     A principal object of this invention is to provide a novel transistor amplifier with a circuit for protecting an FET, used as an amplifier, from being damaged by an overload condition. 
     Another object of this invention is to provide a transistor amplifier with a protective circuit for preventing an FET from being destroyed by coupling an input electrode of the FET to a bipolar transistor, and an input electrode of the bipolar transistor is shunted by a signal from a protective means. 
     A further object of this invention is to provide a transistor amplifier with a protective circuit which performs its protective operation when a load impedance is sensed to be lower than a predetermined value. 
     Another object of this invention is to provide a transistor amplifier with a protective circuit which has a bipolar transistor connected to an input stage, an FET directly connected to an output terminal of the bipolar transistor to amplify a signal supplied thereto, a detecting circuit for detecting the load impedance, and a muting circuit connected to an input terminal of the bipolar transistor and controlled with a signal derived from the detecting circuit. 
     A further object of this invention is to provide a transistor amplifier with a protective circuit comprising a transistor amplifier which includes a bipolar transistor and an FET directly connected to its output, a circuit for detecting the impedance of a load connected to the FET, a shunt circuit connected to an input of the bipolar transistor, and a negative voltage source connected to an input of the FET, wherein when the detecting circuit is operated, the shunt circuit is actuated and a negative bias is applied to the input of the FET to prevent the FET from being destroyed. 
     Another object of this invention is to provide a transistor amplifier with a protective circuit which is composed of a bipolar transistor, an FET directly connected to an emitter electrode of the bipolar transistor, a circuit for detecting an overload condition of a load connected to the FET, a switching circuit connected between the base and emitter electrodes of the bipolar transistor and actuated by an output signal of the detecting circuit, and a capacitor connected to the emitter electrode of the bipolar transistor. 
     These and other objects, features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a sectional view showing an example of an FET with triode characteristics that may be used in a transistor amplifier employing a protective circuit according to the present invention; 
     FIG. 2 is a sectional view of another example of an FET with triode characteristics that may be used in a transistor amplifier with protective circuit according to the present invention; 
     FIG. 3 is a graph illustrating typical output characteristics of FETs of the types shown in FIGS. 1 and 2; 
     FIG. 4 is a circuit diagram of an example of a transistor amplifier with a protective circuit according to the present invention; 
     FIG. 5 is an equivalent circuit used for explaining the circuit of the present invention; 
     FIGS. 6 and 7 are graphs used for explaining the operational characteristics of the protective circuit of the present invention; and 
     FIG. 8 is a circuit diagram of a class-AB push-pull amplifier having a transistor amplifier and a protective circuit according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In a preferred embodiment of the invention, there is a newly developed amplifying element, namely a vertical junction type FET having triode characteristics wherein the product of its series resistance and conversion conductance is less than unit and which operates without a punch-through condition extending the total length of a channel. This vertical junction type FET will be described prior to circuit descriptions. Though a hitherto widely known junction type FET has pentode characteristics, the FET of this invention shows triode characteristics, has a low output impedance and a large conversion conductance, so that it operates with extremely high power. This FET is quite suitable for such use as an amplifying element of an output amplifier in an audio circuit. 
     FIG. 1 shows one example of this vertical junction type FET. The FET is formed of an intrinsic semiconductor region 1 having a low impurity concentration and high resistance, a P-type semiconductor region 2 having an annular configuration and formed on the upper portion of the intrinsic region 1, and an N-type semiconductor region 3 having a high impurity concentration and formed over both the intrinsic region 1 and the P-type region 2. A drain electrode D is formed at the lower surface of the intrinsic region 1, a gate electrode G is formed on the P-type region 2 and a source electrode S is formed on the N-type region 3. As a practically useable vertical junction type FET, a number of FETs of the type shown in FIG. 1 are combined to form a transistor such as shown in FIG. 2 wherein like reference numerals identify corresponding elements. In this FET, the P-type semiconductor region 2 is formed with a mesh-type structure. An additional N+ type semiconductor region 4 having a high impurity concentration is formed under the drain electrode D. 
     In this vertical junction type FET, the distance between the source electrode S and a channel formed at the periphery of the P-type semiconductor region 2 is short and its channel length itself is also short. In general, the apparent conversion conductance gm of a junction type FET maybe expressed as: ##EQU1## where G m  is the true conversion conductance and R c  is the series resistance. In the prior art junction type FET, the source-to-channel resistance is high. The channel resistance is high because of its narrow long configuration, and the channel-to-drain resistance is also high. Consequently, the series resistance R c  is very high, so that the apparent conversion conductance gm is substantially equal to the reciprocal of the series resistance R c . For this reason, the prior art junction type FET exhibits pentode characteristic and, as is apparent therefrom, the drain current becomes saturated as the drain voltage is increased. 
     However, the vertical junction type FET has characteristics such that the series resistance is small, the conversion conductance G m  is large, and the product of the series resistance R c  and the true conversion conductance G m  is less than unity as a whole. 
     A plot of the drain voltage V D  vs. drain current, I D , characteristic of the vertical junction type FET is graphically represented in FIG. 3. In this case, the abscissa represents the drain voltage V D  in volts (V) and the ordinate represents the drain current I D  in milliampers (mA) with gate voltages V G  of 0, -2, -4, -6, -8 and -10 V as the parameter. The characteristic curves are analogous to those of so-called triode characteristics. The series resistance R c  is substantially constant even in the environment of voltage variations, and the apparent conversion conductance gm becomes substantially like the true conversion conductance G m  according to variations in width of the depletion layer. Since the product of the conversion conductance G m  and the series resistance R c  is less than unity, the drain voltage, V D  vs. drain current, I D , characteristic of this FET is similar to triode characteristics with the result that large output with little distortion can be obtained. In this case, the series resistance R c  is the sum of the source-to-channel resistance, the channel resistance itself, and the resistance of the semiconductor region 1 which is the source region. 
     As is apparent from FIG. 3, as the gate voltage V G  is increased from a negative voltage toward ground potential, a large drain current flows even at a low drain voltage V D . Accordingly, it will be understood that when the gate electrode of the FET is grounded due to an overload condition, and the drain electrode of the FET has a constant voltage applied thereto, a large drain current flows therethrough making it impossible to cut off the FET. 
     In FIG. 4, reference numeral 15 designates an FET being used as an output amplifying element. The FET is an N-channel vertical junction type FET having triode characteristics. The FET 15 forms a source-follower type amplifier circuit, wherein its drain electrode is connected to a positive voltage source  +  B  1 , for example, 450 V, and its source electrode is coupled as an output terminal t 2  to which a load 7, such as a loudspeaker, is connected. 
     An NPN-type bipolar transistor, 14, is used as an amplifying element for driving the FET 15. The transistor 14 forms an emitter-follower type amplifier circuit in which its collector electrode is connected to the positive voltage source  +  B, and its emitter electrode is connected to the gate electrode of the FET 15. The base electrode of the transistor 14 is connected to an input terminal t 1 . The emitter electrode of the transistor 14 and the gate electrode of the FET 15 are both connected through a resistor 20 to a negative voltage source -B 1 , for example, of -50 V. 
     An overload detecting circuit 21 detects load impedance by the load voltage and the load current and produces a detected output when the load impedance is less than a predetermined value. A PNP-type switching transistor is shown at 13, and a capacitor 12 is connected between its base and emitter electrodes. The emitter electrode of the transistor 13 is connected to the source electrode of the FET 15, while the source electrode of the FET 15 is connected through a small resistor 6 for detecting the load current to the output terminal t 2 . The base electrode of the transistor 13 is connected through a series circuit of a rectifying diode 8 and a resistor 9 to the output terminal t 2  and also grounded through a series circuit of a resistor 10 and a rectifying diode 11. In this case, the diode 8 is connected with its anode at the base side of the transistor 13, while the diode 11 is connected with its anode at the ground side. 
     A transistor 16 is a switching element which forms a muting circuit. The collector electrode of the transistor 16 is connected to the base electrode of the transistor 14, its emitter electrode is connected to the emitter electrode of the transistor 14, and its base electrode is connected through a resistor 19 to the collector electrode of the transistor 13. A parallel circuit of a resistor 17 and a capacitor 18 is connected between the base and emitter electrodes of the transistor 16. 
     The operation of the circuit of FIG. 4 is described below. If the load impedance becomes less than a limit load impedance R 6  R 10  /R 9  which is determined by respective resistances R 6 , R 9  and R 10 , a voltage across the capacitor 12 exceeds the base-emitter voltage V BE  of the transistor 13, and the transistor 13 becomes conductive thereby to make the transistor 16 conductive. Consequently, the transistor 14 is turned &#34;off&#34; to lower the gate potential of the FET 15 to a negative value less than its pinch-off voltage so that the FET 15 becomes non-conductive, too. Thus, the FET 15 is prevented from damage which could be caused by the overload. In this case, the gate voltage of the FET 15 is not switched to the reference potential (the ground potential). The bipolar transistor 14 is provided at the input stage of the FET 15, and the base voltage of this transistor 14 is switched to the reference potential. Since the gate electrode of the transistor 15 is connected to the negative voltage source -B 1 , the gate potential is shifted to the negative side. As a result, no substantial drain current flows and hence the FET 15 is protected from being damaged by the overload condition. 
     The operation of the overload detecting circuit 21 will be described below. FIG. 5 shows an equivalent circuit of the circuit 21. In the circuit 21, if the load current is taken as i o , the load voltage as e o , and the resistance values of the respective resistors 6, 9 and 10 as R 6 , R 9  and R 10 , the resistor 6 is shown as a voltage source 6&#39; with an electromotive force i o  R l , and the load 7 is shown as a voltage source 7&#39; with an electromotive force e o . The capacitor 12 is charged by the output from the voltage source 6&#39; and discharged by the output from the voltage source 7&#39;. In other words, the voltages i o  R l  and e o  are subjected to a peak-value-rectification by the diodes 8 and 11 and supplied to the capacitor 12 in opposite polarities. 
     In this case, the forward resistances of the diodes 8 and 11 are neglected, and their forward voltage drops are taken as V f1  and V f2 . If a current flowing through this equivalent circuit at its stationary condition is taken as i, a terminal voltage across the capacitor 12 as V, the peak value of the current i o  as i p , and the peak value of the voltage e o  as e p , and the peak value of the voltage e o  as e p , the following equations are obtained. 
     
         -e.sub.p + V.sub.f1 + V.sub.f2 + (R.sub.9 + R.sub.10) . i = 0 1 
    
     
         V = R.sub.6 . i.sub.p - V.sub.f1 - R.sub.9 . i             2 
    
     From the equations (1) and (2), the following equation is derived by cancelling the current i. ##EQU2## When the voltage V expressed by the above equation (3) exceeds the voltage drop V BE  across the base-emitter of the transistor 13, the transistor 13 becomes conductive to produce an overload detecting signal. 
     If the equation (3) is rewritten on the assumption of V = V BE , the following equation (4) is obtained. ##EQU3## 
     Where, let it be assumed that ##EQU4## In other words, since the voltages i o  R 6  and e o  are peak-value-rectified by the diodes 8 and 11 and converted to a DC voltage by the capacitor 12, the terminal voltage V across the capacitor 12 becomes independent of the phase difference between the current i o  and the voltage e o  and takes on a value related to the peak values i p  and e p . Thus, the factor Z = e p  /i p  shows not only the pure resistance component of the load 7, but also its impedance component. 
     If the factors Z and K/R 6  are used, the equation (4) can be rewritten as follows: ##EQU5## 
     If the value of the load impedance Z for satisfying the condition i p  = ∞ is taken as Z∞, the value Z∞ is obtained from the equation (5) as follows: ##EQU6## 
     When the load impedance Z is greater than the value obtained by the equation (6), the current i p  becomes negative and hence the transistor 13 is not made conductive. However, in the case where the load impedance Z is smaller than the value Z∞, when the current i p  becomes greater than that obtained by the equation (5), the transistor 13 is made conductive to produce the overload detecting signal. 
     Equation (5) is shown by a curve in FIG. 6, in which a region d is such a region that the transistor 13 becomes conductive to produce the overload detecting signal. Furthermore the equation (4) is shown by a line in FIG. 7. When the load 7 is a pure resistor, the transistor 13 becomes conductive in a region f to produce the overload detecting signal. 
     In FIG. 4, the resistor 19 prevents the transistor 14 from being turned on when the transistor 13 becomes conductive due to the fact that the output of the transistor 13 causes the transistor 14 to raise its base potential. The resistor 17 prevents the transistor 14 from being turned on acording to the collector cut-off current I CBO  of the transistor 13. The capacitor 18 prevents the transistor 14 from being turned on when the transistor 13 is nonconductive due to the fact that the base input impedance of the transistor 16 is increased by the instantaneous increase of its base input voltage. 
     In addition, if the resistor 20 is formed of a series connection of two resistors, and the connection point of these two resistors is connected to the emitter electrode of the transistor 16 to keep its emitter potential negative, the transistor 16 can be nonconductive in every operating region of the FET 15. 
     Another embodiment of the invention is shown in FIG. 8. Reference numeral 28 designates a pure complementary class-AB push-pull amplifier circuit composed of N-channel and P-channel vertical junction type FETs 15a and 15b which correspond to the FET 15 of FIG. 4. A driving amplifier circuit 27 is composed of NPN-type and PNP-type transistors 14a and 14b corresponding to the transistor 14 of FIG. 4. Reference numeral 26 denotes a class-A amplifier circuit with 2-stage construction provided at the front stage of the driving amplifier circuit 27. A signal supplied to an imput terminal t o  is amplified by the amplifier 26 and supplied to the respective transistors 14a and 14b of the amplifier 27. The transistors 14a and 14b are also applied with bias voltages by the rear-stage amplifier in the circuit 26. The emitter electrodes of the transistors 14a and 14b are respectively connected through resistors 20a and 20b to voltage sources -B 2  and +B 2 . 
     The remaining circuit features are similar to that of FIG. 4, so that elements in FIG. 8 corresponding to those of FIG. 4 are expressed by the same reference numerals with a and b being respectively affixed thereto. Consequently, repeated description is omitted. In this case, however, the transistors 13a and 13b are respectively a PNP-type and an NPN-type, and the transistors 16a and 16b are respectively an NPN-type and a PNP-type. 
     Instead of both of overload detecting circuits 21a and 21b, one circuit 21a can be provided. In this case, the emitter electrode of the transistor 13a is connected to the source electrode of the FET 15a, but its base electrode is connected through a series circuit of the diode 8a and the resistor 9a to the source electrode of the FET 15b. Thus, the transistors 16a and 16b are simultaneously controlled &#34;on&#34; and &#34;off&#34; by the output signal of the transistor 13a. 
     According to the present invention as described above, the transistor amplifier with its protective circuit comprises an amplifying bipolar transistor with its base electrode being applied with an input signal, an amplifying FET with its gate electrode being directly connected to an output electrode of the bipolar transistor, an overoad detecting circuit connected to the FET, and a switching element connected between the base and emitter electrodes of the bipolar transistor, wherein a first voltage source with one polarity is connected to each one output electrode of the bipolar transistor and the FET, and a second voltage source with the other polarity is connected to the other output electrode of the bipolar transistor and to the gate electrode of the FET, whereby when it becomes overloaded, the switching element is rendered conductive by the detected output of the overload detecting circuit to make both the bipolar transistor ad the FET nonconductive. As a result, the FET as the amplifying element of the amplifier circuit is protected from being damaged by the overload condition. 
     The load impedance is detected by the overload detecting circuit and when the value of the detected load impedance is less than a predetermined value, the switching element is turned &#34;on&#34;. Even though the load current is quite large, the FET will not stop its amplifying operation unless the load impedance becomes a minimum as occurs at a short-circuit condition or the like to the former. When the load includes a large reactance in addition to resistance such as a condenser speaker, even if the load current is increased, there is only a temporary loss of FET operation. Consequently, the FET is protected and the output signal is maintained. 
     The above mentioned FET may also have a pentode characteristic and may be of junction type of MOS type. The switching element is not limited to a bipolar transistor, and another semiconductor switching element is also useable therefor. 
     It will be apparent that many modifications and variations may be effected without departing from the scope of the novel concepts of this invention.