Abstract:
An electrostatic discharge (ESD) protection circuit comprises a P-channel field effect transistor (PFET), a buffer and a damping network to provide improved protection for an integrated circuit against high-voltage ESD pulses. The ESD protection circuit is capable of being fabricated with a reduced surface area layout to be fully synthesisable with the integrated circuit which it is designed to protect.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to electronic circuits, and more particularly, to circuits for protection against electrostatic discharge (ESD). 2. Background 
     In order to protect solid state integrated circuits against electrostatic discharge, a variety of ESD protection circuits have been designed which absorb the energy of the electrostatic discharge, thereby protecting the integrated circuits from damage resulting from the high voltage pulses of the electrostatic discharge. A conventional circuit for ESD protection typically occupies a large surface area in an integrated circuit chip because it has very large transistor components. For example, large N-channel field effect transistors (NFETs) have been implemented as clamps in conventional circuits for ESD protection to absorb the high voltage, short duration pulses of electrostatic discharge. However, because of the large size of the transistors, conventional circuits for ESD protection are usually non-synthesisable with the integrated circuit which it is designed to protect. Furthermore, a conventional circuit for ESD protection with a large NFET clamp needs an N-well resistor connected to the drain of the NFET. Variations of the N-well resistor values due to uncertainties in existing foundry processes may cause ESD failures in conventional circuits with large NFET clamps. 
     SUMMARY OF THE INVENTION 
     The present invention provides an electrostatic discharge (ESD) protection circuit, roughly comprising: 
     a P-channel field effect transistor (PFET) having a source capable of receiving a source voltage at a source input that is susceptible to electrostatic discharge, a drain that is grounded, and a gate capable of receiving either a high voltage to turn off the PFET or a low voltage to turn on the PFET; 
     a buffer connected to the gate of the PFET; and 
     a damping network connected to the buffer. 
     Advantageously, the ESD protection circuit in an embodiment according to the present invention is capable of providing improved protection against ESD failure for integrated circuits. Furthermore, the ESD protection circuit in an embodiment according to the present invention is highly area efficient and fully synthesisable with the integrated circuit which it is designed to protect from electrostatic discharge. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be described with particular embodiments thereof, and references will be made to the drawings in which: 
     FIG. 1 shows a diagram of an embodiment of an electrostatic discharge (ESD) protection circuit; 
     FIG. 2 shows a diagram of another embodiment of the ESD protection circuit; and 
     FIG. 3 shows a diagram of yet another embodiment of the ESD protection circuit. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 shows a diagram of an embodiment of a circuit for electrostatic discharge (ESD) protection, comprising a P-channel field effect transistor (PFET)  2 , a buffer  4  which comprises first and second complementary metal oxide semiconductor (CMOS) inverters  6  and  8  connected together, and a damping network  10 . The PFET  2  has a source  2   a  which is connected to a source input  12  to receive a source voltage V, a drain  2   b  that is grounded, and a gate  2   c  that is capable of receiving either a high voltage from the first CMOS inverter  6  to turn off the PFET  2  or a low voltage to turn on the PFET  2 . 
     The source input  12  is susceptible to electrostatic discharge typically in the form of short duration, high voltage pulses. In the embodiment shown in FIG. 1, the source  2   a  of the PFET  2  is directly connected to the source input  12  without an intermediary resistor. In an embodiment, the PFET  2  has a relatively large device area when implemented on a semiconductor substrate to allow it to absorb the ESD pulses which may be carried to the source input  12 . For example, in an implementation in which the PFET  2  is designed to absorb ay “human body model” ESD pulse, which is known to a person skilled in the art, the layout of the PFET  2  comprises six slices each comprising  48  PFET fingers, each of the fingers having a width of 11.4 μm and a length of 0.35 μm using existing 0.35 μm process technology known to a person skilled in the art. 
     In the embodiment shown in FIG. 1, the first CMOS inverter  6  comprises a PFET  14  and an N-channel field effect transistor (NFET)  16 . The source  14   a  of the PFET  14  is connected to the source input  12 , and the source  16   a  of the NFET  16  is connected to ground. The drain  14   b  of the PFET  14  is connected to the drain  16   b  of the NFET  16  to form the output  18  of the first CMOS inverter  6 . In the embodiment shown in FIG. 1, the output  18  of the first CMOS inverter  6  is connected to the gate  2   c  of the PFET  2 . 
     The gate  14   c  of the PFET  14  and the gate  16   c  of the NFET  16  are connected together to form the input  20  to the first CMOS inverter  6 . In the embodiment shown in FIG. 1, the second CMOS inverter  8  has substantially the same configuration as that of the first CMOS inverter  6 . The second CMOS inverter  8  has an output  22  which is connected to the input  20  of the first CMOS inverter  6  and an input  24  which is connected to the damping network  10 . In the embodiment shown in FIG. 1, the second CMOS inverter  8  comprises a PFET  26  and an NFET  28 . The source  26   a  of the PFET  26  is connected to the source input  12 , whereas the source  28   a  of the NFET  28  is connected to ground. The drain  26   b  of the PFET  26  and the drain  28   b  of the NFET  28  are connected together to form the output  22  of the second CMOS inverter  8 . The gate  26   c  of the PFET  26  and the gate  28   c  of the NFET  28  are connected together to form the input  24  to the second CMOS inverter  8 . 
     In the embodiment shown on FIG. 1, a high voltage at the input  24  of the second CMOS inverter  8  results in a high voltage at the output  18  of the first CMOS inverter  6 , which turns off the PFET  2 . Conversely, a low voltage at the input  24  of the second CMOS inverter  8  results in a low voltage at the output  18  of the first CMOS inverter  6 , which turns on the PFET  2 . The CMOS inverters  6  and  8  together form a buffer  4  which relays voltage signals from the input  24  of the second CMOS inverter  8  to the output  18  of the first CMOS inverter  6 , but does not allow a current to flow between the input  24  and the output  18 . Both the first CMOS inverter  6  and the second CMOS inverter  8  are biased by the source voltage V at the source input  12 . 
     In the embodiment shown in FIG. 1, the damping network  10  comprises a resistor  30  having a first terminal  30   a  connected to the source input  12  and a second terminal  30   b  connected to the input  24  of the second CMOS inverter  8 , and a capacitor  32  having a first terminal  32   a  connected to the input  24  of the second CMOS inverter  8  and a second terminal  32   b  connected to ground. The damping network  10  dissipates the energy of a high voltage ESD pulse which may be received at the source input  12 . In the embodiment shown in FIG. 1, the damping network  10  and the buffer  4  formed by the two CMOS inverters  6  and  8  connected together perform the function of damping an electrostatic discharge which may be present at the source input  12 . 
     FIG. 2 shows another embodiment of a circuit for ESD protection according to the present invention, in which a buffer  34  comprising a single CMOS inverter  36  is connected to the PFET  2 . In this embodiment, the CMOS inverter  36  comprises a PFET  38  and an NFET  40 . The source  38   a  of the PFET  38  is connected to the source input  12 , whereas the source  40   a  of the NFET  40  is connected to ground. The drain  38   b  of the PFET  38  is connected to the drain  40   b  of the NFET  40  to form the output  42  of the CMOS inverter  36 . The gate  38   c  of the PFET  38  and the gate  40   c  of the NFET  40  are connected together to form the input  44  of the CMOS inverter  36 . A high voltage at the input  44  of the CMOS inverter  36  produces a low voltage at the output  42 , which turns on the PFET  2 . Conversely, a low voltage at the input  44  of the CMOS inverter  36  produces a high voltage at the output  42 , which turns off the PFET  2 . 
     In the embodiment shown in FIG. 2, a damping network  46  which comprises a capacitor  48  and a resistor  50  is connected to the buffer  34 . In this embodiment, the capacitor  48  has a first terminal  48   a  which is connected to the source input  12  and a second terminal  48   b  which is connected to the input  44  of the CMOS inverter  36 . The resistor  50  has a first terminal  50   a  which is connected to the input  44  of the CMOS inverter  36  and a second terminal  50   b  which is connected to ground. The damping network  46  and the buffer  34  together perform the function of damping an electrostatic discharge which may be present at the source input  12 . The CMOS inverter  36  is biased by the source voltage V at the source input  12  and no current flows between the input  44  and the output  42  of the CMOS inverter  36 . 
     FIG. 3 shows a circuit diagram of yet another embodiment in which only one PFET and one NFET are implemented for ESD protection. In this embodiment, the PFET  2  has a source  2   a  which is connected to the source input  12  carrying the bias voltage V, a drain  2   b  which is grounded, and a gate  2   c  which is connected to a buffer  52 . In this embodiment, the buffer  52  comprises a resistor  54  and an NFET  56  connected together. The resistor  54  has a first terminal  54   a  which is connected to the source input  12  and a second terminal  54   b  which is connected to the gate  2   c  of the PFET  2 . The source  56   a  of the NFET  56  is grounded while the drain  56   b  of the NFET  56  is connected to the gate  2   c  of the PFET  2  and the second terminal  54   b  of the resistor  54 . 
     In the embodiment shown in FIG. 3, a damping network  58  which comprises a capacitor  60  and a resistor  62  is connected to the buffer  52 . The capacitor  60  has a first terminal  60   a  which is connected to the source input  12  and a second terminal  60   b  which is connected to the gate  56   c  of the NFET  56 . The resistor  62  has a first terminal  62   a  which is connected to the gate  56   c  of the NFET  56  and a second terminal  62   b  which is connected to ground. In this embodiment, the resistor  54  serves as a pull-up resistor while the resistor  62  serves as a pull-down resistor. The resistors  54  and  62 , the NFET  56  and the capacitor  60  together perform the function of damping an electrostatic discharge which may be present at the source input  12  of the circuit. 
     From the above description of the invention it is manifest that various equivalents can be used to implement the concepts of the present invention without departing from its scope. Moreover, while the invention has been described with specific reference to certain embodiments, a person of ordinary skills in the art would recognize that changes can be made in form and detail without departing from the spirit and the scope of the invention. The described embodiments are to be considered in all respects as illustrative and not restrictive. It should also be understood that the invention is not limited to the particular embodiments described herein, but is capable of many equivalents, rearrangements, modifications, and substitutions without departing from the scope of the invention.