Abstract:
A semiconductor package device houses a die which comprises a power device, and the die further includes a silicon region over a substrate, a first plurality of trenches extending in the silicon region; a contiguous sinker trench extending along the perimeter of the die so as to completely surround the first plurality of trenches, the sinker trench extending from a top surface of the die through the silicon region, the sinker trench being lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the sinker trench makes electrical contact with the substrate along the bottom of the sinker trench and makes electrical contact with an interconnect layer along the top of the sinker trench; and a plurality of interconnect balls arranged in a grid array, an outer group of the plurality of interconnect balls electrically connecting to the conductive material in the sinker trench.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. Provisional Application No. 60/598,678, filed Aug. 3, 2004, incorporated herein by reference. Also, this application relates to application Ser. No. 11/026,276 titled “Power Semiconductor Devices and Methods of Manufacture” filed Dec. 29, 2004 incorporated herein by reference. 
     
    
     BACKGROUND 
       [0002]    This invention relates in general to semiconductor power devices and more particularly to power devices with top-side drain contact using a sinker trench. 
         [0003]    Unlike integrated circuits (ICs) which have a lateral structure with all interconnects available on the upper die surface, many power semiconductor devices have a vertical structure with the back of the die being an active electrical connection. For example, in vertical power MOSFET structures, the source and gate connections are at the top surface of the die and the drain connection is on the back side of the die. For some applications, it is desirable to make the drain connection accessible at the top side. Sinker trench structures are used for this purpose. 
         [0004]    In a first technique, diffusion sinkers extending from the top-side of the die down to the substrate (which forms the drain contact region of the device) are used to make the drain contact available at the top surface of the die. A drawback of this technique is that the lateral diffusion during the formation of the diffusion sinkers results in consumption of a significant amount of the silicon area. 
         [0005]    In a second technique, metal-filled vias extending from the top-side of the die clear through to the backside of the die are used to bring the back-side contact to the top-side of the die. Although, this technique does not suffer from the loss of active area as in the diffusion sinker technique, it however requires formation of very deep vias which adds to the complexity of the manufacturing process. Further, during conduction, the current is required to travel through long stretches of the substrate before reaching the drain contact, thus resulting in higher device on resistance Ron. 
         [0006]    Thus, an improved trench structure for making a back-side contact available at the top-side is desirable. 
       BRIEF SUMMARY 
       [0007]    In accordance with an embodiment of the invention, a semiconductor power device includes a substrate of a first conductivity type and an epitaxial layer of the first conductivity type over and in contact with the substrate. A first trench extends into and terminates within the epitaxial layer. A sinker trench extends from the top surface of the epitaxial layer through the epitaxial layer and terminates within the substrate. The sinker trench is laterally spaced from the first trench, and is wider and extends deeper than the first trench. The sinker trench is lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the sinker trench makes electrical contact with the substrate along the bottom of the trench and makes electrical contact with an interconnect layer along the top of the trench. 
         [0008]    In accordance with another embodiment of the invention, a semiconductor power device is formed as follows. An epitaxial layer is formed over and in contact with a substrate. The epitaxial layer and the substrate are of a first conductivity type. A first opening for forming a first trench and a second opening for forming a sinker trench are defined such that the second opening is wider than the first opening. A silicon etch is performed to simultaneously etch through the first and second openings to form the first trench and the sinker trench such that the first trench terminates within the epitaxial layer and the sinker trench terminates within the substrate. The sinker trench sidewalls and bottom are lined with an insulator. The sinker trench is filled with a conductive material such that the conductive material makes electrical contact with the substrate along the bottom of the sinker trench. An interconnect layer is formed over the epitaxial layer such that the interconnect layer makes electrical contact with the conductive material along the top surface of the sinker trench. 
         [0009]    In accordance with yet another embodiment of the invention, a semiconductor power device includes a plurality of groups of stripe-shaped trenches extending in a silicon region over a substrate. A contiguous sinker trench completely surrounds each group of the plurality of stripe-shaped trenches so as to isolate the plurality of groups of stripe-shaped trenches from one another. The contiguous sinker trench extends from a top surface of the silicon region through the silicon region and terminates within the substrate. The contiguous sinker trench is lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the contiguous sinker trench makes electrical contact with the substrate along the bottom of the contiguous sinker trench and makes electrical contact with an interconnect layer along the top of the contiguous sinker trench. 
         [0010]    In accordance with yet another embodiment of the invention, a semiconductor power device includes a plurality of groups of stripe-shaped gate trenches extending in a silicon region over a substrate. Each of a plurality of stripe-shaped sinker trenches extends between two adjacent groups of the plurality of groups of stripe-shaped gate trenches. The plurality of stripe-shaped sinker trenches extends from a top surface of the silicon region through the silicon region and terminate within the substrate. The plurality of stripe-shaped sinker trenches are lined with an insulator only along the sinker trench sidewalls so that a conductive material filling each sinker trench makes electrical contact with the substrate along the bottom of the sinker trench and makes electrical contact with an interconnect layer along the top of the sinker trench. 
         [0011]    In accordance with another embodiment of the invention, a semiconductor package device houses a die which includes a power device. The die includes a silicon region over a substrate. Each of a first plurality of trenches extends in the silicon region. A contiguous sinker trench extends along the perimeter of the die so as to completely surround the first plurality of trenches. The contiguous sinker trench extends from a top surface of the die through the silicon region and terminates within the substrate. The contiguous sinker trench is lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the contiguous sinker trench makes electrical contact with the substrate along the bottom of the contiguous sinker trench and makes electrical contact with an interconnect layer along the top of the contiguous sinker trench. A plurality of interconnect balls arranged in a grid array includes an outer group of the plurality of interconnect balls electrically connecting to the conductive material in the contiguous sinker trench. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  shows a simplified cross sectional view of an exemplary vertical power device in accordance with an embodiment of the invention; 
           [0013]      FIGS. 2-4  show various top layout views of a vertical power device with one or more sinker trenches in accordance with exemplary embodiments of the invention; and 
           [0014]      FIG. 5  is a top view illustrating the locations of interconnect balls in a ball-grid array package relative to a sinker trench extending along the perimeter of a die housed in the ball-grid array package, in accordance with an exemplary embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0015]    In accordance with an embodiment of the present invention, a sinker trench terminating within the silicon substrate is filled with a highly conductive material such as doped polysilicon or metallic material. The sinker trench is laterally spaced a predetermined distance from the active region wherein gate trenches are formed. The sinker trench is wider and extends deeper than the gate trenches, and is lined with an insulator only along its sidewalls. This technique eliminates the area loss due to side diffusion of the diffusion sinker approach, and results in improved on-resistance since a more conductive material is used than diffusion. Also, this technique requires a far shallower trench than that needed in the technique where a metal-filled trench extends from the top to the bottom of the die. The on-resistance is improved since the current need not travel through the entire depth of the substrate to reach the drain contact. 
         [0016]      FIG. 1  shows a simplified cross sectional view of a vertical trenched-gate power MOSFET structure  100  in accordance with an exemplary embodiment of the invention. An n-type epitaxial layer  104  extends over an n-type substrate  102  which forms the back side drain. A sinker trench  106  extends from the top surface of epitaxial layer  104  through epitaxial layer  104  terminating within substrate  102 . A dielectric layer  110  lines the sinker trench sidewalls. Dielectric layer  110  may be from any one of oxide, silicon nitride, silicon oxynitride, multilayer of oxide and nitride, any known low k insulating material, and any known high k insulating material. “Oxide” as used in this disclosure means a chemical vapor deposited oxide (Si x O y ) or a thermally grown silicon dioxide (SiO 2 ). Sinker trench  106  is filled with a conductive material  108  such as doped polysilicon, selective epitaxial silicon (SEG), metal, or metallic compounds. Conductive material  108  is in electrical contact with substrate  102  along the bottom of sinker trench  106 . Conductive material  108  thus makes the back-side drain available along the top side for interconnection. With the drain contact moved to the top surface, a back-side metal for contacting substrate  102  is no longer needed, but could be used in conjunction with the top side contact. The back side metal layer may be included for other purposes such as preventing the die from cracking and improving the heat transfer properties of the device. 
         [0017]    Well regions  114  of p-type conductivity extend along an upper portion of epitaxial layer  104 . Gate trenches  112  are laterally spaced from sinker trench  106  by a predetermined distance S 1 , and vertically extend from the top surface through p-type well regions  114  terminating at a predetermined depth within epitaxial layer  104 . Sinker trench  106  is wider and deeper than gate trenches  112 . Gate trenches  112  are lined with a dielectric layer  116 . The dielectric along the bottom of gate trenches  112  may optionally be made thicker than the dielectric along the gate trench sidewalls. Each gate trench  112  includes a gate electrode  118  and a dielectric layer  120  atop gate electrode  118  to reduce the gate to drain capacitance. Source regions  122  of n-type conductivity extend along an upper portion of well regions  114 . Source regions  122  overlap gate electrodes  118  along the vertical dimension. As can be seen well region  114  terminates a distance away from sinker trench  106 . In one embodiment, this distance is dictated by the device blocking voltage rating. In another embodiment, well region  114  terminates at and thus abuts sinker trench  106 . In this embodiment, for higher blocking voltage ratings, the thickness of the dielectric layer along sinker trench sidewalls needs to be made larger since the sinker dielectric is required to withstand a higher voltage. This may require a wider sinker trench if the conductive material  108  is required to have a minimum width for current handling purposes. 
         [0018]    In the on state, a conduction channel from source regions  122  to epitaxial layer  104  is formed in well regions  114  along gate trench sidewalls. A current thus flows from drain terminal  124  vertically through conductive material  108  of sinker trench  106 , then laterally through substrate  102 , and finally vertically through epitaxial layer  104 , the conduction channel in well regions  114 , and source regions  122 , to source terminal  126 . 
         [0019]    While the width of the gate trenches is generally kept as small as the manufacturing technology allows to maximize the packing density, a wider sinker trench is generally more desirable. A wider sinker trench is easier to fill, has lower resistance, and can more easily be extended deeper if needed. In one embodiment, sinker trench  106  and gate trenches  114  are formed at the same time. This is advantageous in that the sinker trench is self-aligned to the active region. In this embodiment, the widths of the sinker trench and the gate trenches and spacing S 1  between sinker trench  106  and the active region need to be carefully selected taking into account a number of factors. First, a ratio of width Ws of sinker trench  106  to width Wg of gate trenches  112  needs to be selected so that upon completion of the trench etch step sinker trench  106  and gate trenches  112  terminate at the desired depths. Second, the width ratio as well as spacing S 1  needs to be carefully selected to minimize micro-loading effect which occurs when trenches with different features are simultaneously etched. Micro-loading effect, if not addressed properly, may cause trenches with a wide opening have a wider bottom than top. This can lead to such problems as formation of pin-holes in the conductive material in the sinker trench. The micro-loading effect can also be minimized by selecting proper etch material. Third, the widths of the trenches and spacing S 1  impact the device on-resistance Ron. In the article by A. Andreini, et al., titled “A New Integrated Silicon Gate Technology Combining Bipolar Linear, CMOS Logic, and DMOS Power Parts,” IEEE Transaction on Electron Devices, Vol. ED-33, No. 12, December, 1986, pp 2025-2030, a formula is set forth in section IV-B at page 2028 which can be used to determine the optimum trench widths and spacing S 1  for the desired Ron. Although the power device described in this article uses a diffusion sinker, the same principles relating to optimizing Ron can be applied in the present invention. This article is incorporated herein by reference. 
         [0020]    The ratio of the width of the sinker trench to that of the gate trenches is also dependent on the type of conductive material used in the sinker trench. In general, a ratio of the sinker trench width to the gate trench width of less than 10:1 is desirable. In one embodiment wherein doped polysilicon is used as the conductive material, a ratio of sinker trench width to gate trench width of less than 5:1 is desirable. For example, for a gate trench width of 0.5 μm, a sinker trench width in the range of about 0.7 μm to 2.5 μm would be selected. If a metal or other highly conductive material is used in the sinker trench, a higher ratio (e.g., 3:1) is more desirable. Other than the relative width of the trenches, spacing S 1  between the sinker trench and the active region also impacts the micro-loading effect. A smaller spacing generally results in reduced micro-loading effect. 
         [0021]    In one embodiment, the depth of the gate trenches in the epitaxial layer is selected to be close to the interface between substrate  102  and epitaxial layer  104  so that a slightly wider sinker trench would reach through to contact substrate  102 . In an alternate embodiment, both the gate trenches and the sinker trench terminate within substrate  102 . 
         [0022]    In another embodiment, the sinker trench and the gate trenches are formed at different times. Thought the sinker trench would not be self-aligned to the active region, spacing S 1  is not a critical dimension. Advantages of forming the two trenches at different times include elimination of the micro-loading effect, and the ability to optimize each trench separately. 
         [0023]    In accordance with an embodiment of the present invention, a method of forming the power transistor shown in  FIG. 1  wherein the sinker trench and gate trenches are formed simultaneously, is as follows. Epitaxial layer  104  is formed over substrate  102 . Next, a masking layer is used to pattern the gate trench and sinker trench openings. Conventional plasma etch techniques are used to etch the silicon to form the sinker trench and gate trenches. An insulating layer, e.g., oxide, is then formed along sidewalls and bottom of both the gate trenches and the sinker trench. Increasing the insulating thickness or increase in the dielectric constant of the insulating material is advantageous in minimizing the area between the depletion region and sinker trench, distance S 1 , as some of the voltage from the depletion layer will be supported by the insulating layer thus reducing consumed silicon area by use of a sinker trench. 
         [0024]    A nitride layer is formed over the oxide layer in all trenches. The oxide and nitride layers are then removed from the bottom of the sinker trench using conventional photolithography and anisotropic etch techniques thus leaving an oxide-nitride bi-layer along the sinker trench sidewalls. Alternatively, a combination of anisotropic and isotropic etching or isotropic etching alone can be used. The combination of anisotropic and isotropic etching can advantageously be used to respectively remove the nitride and oxide layers from lower sidewall portions of the trench sinker (e.g., those lower sidewall portions extending in the substrate or even in the epitaxial layer—this would advantageously reduce the on-resistance). The resulting thicker bi-layer of dielectric along sinker trench sidewalls is advantageously capable of withstanding higher drain voltages. The sinker trench and gate trenches are then filled with in-situ doped polysilicon. The doped polysilicon is then etched back to planarize the top of the polysilicon in the trenches with the top surface of epitaxial layer  104 . Next, using a masking layer to cover the sinker trench, the polysilicon and oxide-nitride bi-layer are removed from the gate trenches. The gate trenches are then lined with a gate oxide layer and filled with gate polysilicon material. The excess gate polysilicon over the sinker trench is removed using a conventional photolithography and etch process to pattern the gate electrode. The remaining process steps for forming the insulating layer over the gate electrodes, the well regions, the source regions, the source and drain metal contact layers, as well as other steps to complete the device are carried out in accordance with conventional methods. 
         [0025]    In an alternate method, after trenches are formed, a thick oxide layer (as mentioned above, to reduce the spacing of the sinker trench to the well region) is formed along the sidewalls and bottom of the gate and sinker trenches. The thick oxide layer is then removed from the bottom of the sinker trenches using conventional photolithography and anisotropic etch techniques thus leaving the sidewalls of the sinker trench lined with the thick oxide while the gate trenches are protected. Alternatively, a combination of anisotropic and isotropic etching can be used to also remove the thick oxide from lower portions of the trench sinker sidewalls. The oxide layer may act as a sacrificial insulating layer for the gate trenches to improve the gate oxide integrity. The sinker trench and gate trenches are then filled with in-situ doped polysilicon. The doped polysilicon is then etched back to planarize the top of the polysilicon in the trenches with the top surface of epitaxial layer  104 . Next, using a masking layer to cover the sinker trench, the polysilicon and insulating layer are removed from the gate trenches. The gate trenches are then lined with a gate insulating layer and filled with gate polysilicon material. The excess gate polysilicon over the sinker trenches is removed using a conventional photolithography and etch process to pattern the gate electrode. The remaining process steps for forming the insulating layer over the gate electrodes, the well regions, the source regions, the source and drain metal contact layers, as well as other steps to complete the device are carried out in accordance with conventional methods. 
         [0026]    In another method, once trenches are formed, an insulating layer, e.g., gate oxide, is formed (grown or deposited) along the sidewalls and bottom of the gate and sinker trenches. The gate oxide layer is then removed from the bottom of the sinker trenches using conventional photolithography and anisotropic etch techniques thus leaving an oxide layer lining the sidewalls of the sinker trench while the gate trenches are protected. Alternatively, a combination of anisotropic and isotropic etching or isotropic etching alone can be used. The combination of anisotropic and isotropic etching can advantageously be used to remove the gate oxide layer from lower sidewall portions of the trench sinker (e.g., those lower sidewall portions extending in the substrate or even in the epitaxial layer—this would advantageously reduce the on-resistance). The sinker trench and gate trenches are then filled with in-situ doped polysilicon. The doped polysilicon is then patterned using conventional photolithography techniques and etched to form both the sinker (drain) and gate electrodes. The remaining process steps for forming the insulating layer over the gate electrodes, the well regions, the source regions, the source and drain metal contact layers, as well as other steps to complete the device are carried out in accordance with conventional methods. 
         [0027]    In yet another method, the sinker trench and gate trenches are formed independently by using separate masking steps. For example, using a first set of masks and processing steps the gate trenches are defined and etched, lined with gate oxide, and filled with polysilicon. Using a second set of masks and processing steps the sinker trench is defined and etched, lined with dielectric layer along its sidewalls, and filled with a conductive material. The order in which the sinker trench and gate trenches are formed may be reversed. 
         [0028]      FIG. 2  shows a simplified top layout view of the power device with sinker trench in accordance with an exemplary embodiment of the invention. The  FIG. 2  layout view depicts a stripe-shaped cell configuration. Stripe-shaped gate trenches  212   a  extend vertically and terminate in horizontally-extending gate trenches  212   b . As shown, the three groups of striped gate trenches are surrounded by a contiguous sinker trench  206 . In an alternate embodiment shown in  FIG. 3 , sinker trenches  306  are disposed between groups of gate trenches (only two of which are shown) and are repeated at such frequency and spacing as dictated by the desired Ron. In one variation of this embodiment, to achieve the same Ron as the back-side drain contact approach, the spacing between adjacent sinker trenches needs to be two times the thickness of the wafer. For example, for a 4 mils thick wafer, the sinker trenches may be spaced from one another by approximately 8 mils. For even a lower Ron, the sinker trenches may be placed closer together. In yet another embodiment shown in  FIG. 4 , striped gate trenches  412  extend horizontally, and vertically extending sinker trenches  406  separate the different groups of gate trenches. Sinker trenches  406  are interconnected by a metal interconnect  432 . Metal interconnect is shown as being enlarged along the right side of the figure forming a drain pad for bond-wire connection. Also a gate pad  430  is shown in a cut-out corner of one of the groups of gate trenches. 
         [0029]      FIG. 5  shows a top view of a die housing the power device with sinker trenches in accordance with an embodiment of the invention. The small circles depict the balls of a ball grid array package. The outer perimeter region  506  includes the sinker trench, and the balls in outer periphery region  506  thus provide the drain connection. Central region  507  represents the active region and the balls inside this region provide the source connection. The small square region  530  at the bottom left corner of central region  508  represents the gate pad and the ball inside region  530  provides the gate connection. 
         [0030]    As is readily apparent, the sinker trench structure  106  in  FIG. 1  may be used to bring the backside connection of any power device to the top surface and as such is not limited to use with vertical trenched-gate power MOSFETs. Same or similar sinker trench structures may be similarly integrated with such other vertically conducting power devices as planar gate MOSFETs (i.e., MOSFETs with the gate and its underlying channel region extending over and parallel to the silicon surface), and power diodes to make the anode or cathode contact regions available along the top for interconnection. Many other variations and alternatives are possible, including use of shielded gate and dual gate structures in different combinations with various charge balancing techniques many of which are described in detail in the above-referenced commonly assigned patent application Ser. No. 11/026,276 titled “Power Semiconductor Devices and Methods of Manufacture” filed Dec. 29, 2004, which is incorporated herein by reference in its entirety. Also, although  FIGS. 2-5  show layout implementations based on the open cell configuration, the invention is not limited as such. The structure shown in  FIG. 1  can also be implemented in any one of a number of well known closed cell configurations. Lastly, the dimensions in the cross section view in  FIG. 1  and the top layout views in  FIGS. 2-5  are not to scale and are merely illustrative.