Abstract:
A power converter for converting DC to AC power or DC to DC power includes an input circuit, a transformer, an output circuit, and a controller. The input circuit receives DC input power and creates high frequency pulses. The transformer transforms the high frequency pulses into at least two sets of transformed pulses, the sets of transformed pulses having alternating and opposite polarity. The transformer includes a primary winding and a secondary winding, where the primary winding is connected to the input circuit. The output circuit includes a plurality of switches for providing a full wave rectified or DC output, where the output circuit is connected to the secondary winding. The controller controls the switches to provide a continuous current path through the output circuit thus minimizing voltage spikes and ripple, and greatly reducing the cost and complexity of the output circuit usually required to handle these spikes and ripple. In addition, this provides for lagging currents typical of an inductive load and provides for clean zero crossing of the AC output wave.

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S)  
       [0001]     Reference is made to a copending application entitled “Power Converter with Dynamic Current Limiting,” filed on even date, and which is incorporated by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     The present invention relates to electrical power conversion and more particularly to a system and method for converting power from one form to another.  
         [0003]     Electrical power is typically supplied in one of two forms: direct current (DC) power and alternating current (AC) power. There are often times when it is desirable to convert from one form of power to the other form. This is accomplished by using a power converter. A power converter can convert power from AC to DC, DC to AC, AC to AC, or DC to DC. In this way, a power converter allows a device that uses one form or level of power to connect to a power source that supplies a different form or level of power.  
         [0004]     Known power converters currently exhibit multiple problems. First, large low-frequency transformers make power converters heavy, large, and expensive. Second, power converters using high-frequency transformers are less efficient, resulting in an output power that is significantly less than the input power. Third, some power converters using high-frequency transformers can generate large voltage spikes in the output section. Fourth, in an attempt to reduce or eliminate these voltage spikes, some power converters include extra circuitry which increases their size, weight, cost, and complexity. See, for example, U.S. Pat. No. 6,067,243 versus U.S. Pat. No. 6,236,192. Fifth, a zero volt pause is another problem found with power converters using high-frequency transformers. A zero volt pause occurs when the voltage on the output pauses briefly at zero volts, such as between pulses of a pulse width modulated (PWM) output. During this brief pause, the voltage can fluctuate between a small positive and negative voltage due to noise. These voltage fluctuations can cause major problems in sensitive electronics such as furnace controllers, laser printers, and copiers.  
         [0005]     Therefore, there is a need in the art for an efficient power converter with reduced size, weight, cost, and complexity, which does not experience large voltage spikes and exhibits a clean zero crossing.  
       BRIEF SUMMARY OF THE INVENTION  
       [0006]     The present invention is a power converter and a method of converting power. The power converter includes an input circuit, a high-frequency transformer, an output circuit, and a controller. The high-frequency transformer includes a primary winding that is connected to the input circuit and secondary winding connected to the output circuit. The secondary winding produces simultaneous pulses of an opposite and alternating polarity. The output circuit includes a first switch, and a second switch. The controller includes a primary controller that synchronizes the operation of the input controller with the output controller. The output controller controls the first switch and the second switch such that each switch is on except when blocking a pulse of an unwanted polarity.  
         [0007]     In one embodiment, DC power is received at input terminals of the input circuit from an external power source. The DC power is converted into high-frequency pulses by the input circuit. The high-frequency pulses are transformed by the high-frequency transformer into transformed pulses including desired pulses and undesired pulses. The first and second switches are maintained in an on position except when blocking undesired pulses. Finally, the desired pulses are converted into output power.  
         [0008]     By maintaining the switches in the on position except when blocking undesired pulses, the power converter of the present invention solves the problem of voltage spikes as encountered in the prior art. Voltage spikes occur when a power converter is driving a load and all current paths are temporarily shut off between pulses such that current cannot flow. This is typical of a PWM output. By maintaining the switches in an on position except when blocking undesired pulses, one of the switches is always on. In this way, a current path is always available through the output circuit, such that voltage spikes will not build up in the output circuit.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]      FIG. 1  is a schematic block diagram of the power converter of the present invention.  
         [0010]      FIG. 2  is an example of a timing diagram illustrating the operation of the power converter.  
         [0011]      FIG. 3  is an exploded timing diagram illustrating the unique timing of the power converter.  
         [0012]      FIG. 4  is a schematic block diagram of one embodiment of an output controller.  
     
    
     DETAILED DESCRIPTION  
       [0013]      FIG. 1  is a schematic block diagram of power converter  10  of the present invention. Power converter  10  generally includes input terminals IN 1  and IN 2 , input circuit  12 , high-frequency transformer  14 , output circuit  16 , controller  17 , and output terminals OUT 1  and OUT 2 . Controller  17  includes primary controller  18 , input controller  20 , and output controller  22 . In this embodiment, input DC power having a voltage V IN  is received at input terminals IN 1  and IN 2  from a DC power source. Power converter  10  provides output AC power having voltage V OUT  to an electrical load connected to output terminals OUT 1  and OUT 2 .  
         [0014]     Input circuit  12  can be any one of a plurality of well known input circuits such as but not limited to an H-bridge circuit or a push-pull circuit. Input circuit  12  is controlled by primary controller  18  and input controller  20  using either pulse-width modulation or pulse-phase modulation to convert DC power received at input terminals IN 1  and IN 2  to high-frequency pulses. Transformer  14  transforms the high-frequency pulses to the desired voltage according to a turns ratio of transformer  14 . The transformed pulses are then provided to output circuit  16 . Output circuit  16  is controlled by output controller  22  and converts the transformed pulses into the desired output form at output terminals OUT 1  and OUT 2 .  
         [0015]     Now that the general structure of power converter  10  has been described, power converter  10  will be described in more detail. Transformer  14  includes primary winding  30 , secondary winding  32 , and center tap  38 . Secondary winding  32  includes first portion or leg  34  and second portion or leg  36 . First node  40 , second node  42 , and third node  44  are provided between transformer  14  and output circuit  16 . First portion  34  is connected between center tap  38  and first node  40 . Center tap  38  is connected between first portion  34 , second portion  36 , and node  42 . Second portion  36  is connected between center tap  38  and third node  44 .  
         [0016]     Transformer  14  is a high-frequency transformer. High-frequency transformers provide multiple benefits over low-frequency transformers. Low-frequency transformers are often very large, heavy, and expensive. On the other hand, high-frequency transformers are smaller, less expensive, and much lighter. For example, a 60 Hz, two kilowatt transformer might weigh over 25 pounds, whereas a high-frequency two kilowatt transformer can weigh as little as 2.5 pounds. By using a high-frequency transformer for transformer  14 , the overall size, cost, and weight of power converter  10  is significantly reduced.  
         [0017]     Input circuit  12  provides high-frequency pulses to primary winding  30  of transformer  14 . The high-frequency pulses cause current to flow through primary winding  30 . The current flow creates a magnetic field in transformer  14  which induces current to flow through secondary winding  32 . The current flow through secondary winding  32  causes a voltage to be formed across the secondary winding. Using center tap  38  as a reference, the voltage at first node  40  (measured across first portion  34  from second node  42  to first node  40 ) is represented as V A . The voltage at node  44  (measured across second portion  36  from second node  42  to third node  44 ) is represented as V B . Each time a high-frequency pulse enters primary winding  30 , either a positive or a negative voltage is created at node  40 . At the same time, a voltage of equal magnitude but opposite polarity will be created at node  44 , such that when V A  is positive, V B  will be negative. On the other hand, when V A  is negative, V B  will be positive. In this way, every time a high-frequency pulse is formed on primary winding  30 , both a positive and a negative pulse will be supplied to output circuit  16 .  
         [0018]     In addition to this, the polarity of the pulses at V A  and V B  alternate such that a first pulse causing a positive V A  is followed by a second pulse causing a negative V A . At the same time, the first pulse causes a negative V B  that is followed by the second pulse that causes a positive V B .  
         [0019]     Output circuit  16  includes switch A, switch B, fourth node  54 , coil  56 , fifth node  57 , capacitor  58 , and sixth node  59 . Switch A includes first MOSFET  46  and second MOSFET  48 . Switch B includes third MOSFET  50  and fourth MOSFET  52 . Switch A is connected between first node  40  and fourth node  54 . Switch B is connected between third node  44  and fourth node  54 . Coil  56  is connected between fourth node  54  and fifth node  57 . Capacitor  58  (which is optional) is connected between fifth node  57  and sixth node  59 . Output terminals OUT 1  and OUT 2  are connected to fifth node  57  and sixth node  59 , respectively.  
         [0020]     Switches A and B are shown in this embodiment as back-to-back MOSFETs. One skilled in the art will recognize that switches A and B can be any suitable switches and are not limited to back-to-back MOSFETs. One benefit of the back-to-back MOSFET switches is their greater efficiency, resulting in little power being lost during switching. The back-to-back configuration means that the MOSFETs are connected in one of two ways: either the drains of the MOSFETS are connected together, or the sources of the MOSFETs are connected together. This configuration stops current flow in both directions through the switches when the switches are turned off.  
         [0021]     Switches A and B are controlled by control signals from output controller  22 . Control signal SWA+ is provided to the gates of first and second MOSFETs  46  and  48 . Control signal SWA− is provided to the common connection between first and second MOSFETs  46  and  48 . Similarly, control signal SWB+ is provided to the gates of third and fourth MOSFETs  50  and  52 . Control signal SWB− is provided to the common connection between third and fourth MOSFETs  50  and  52 .  
         [0022]     Since switches A and B are operated in the same manner, the operation of switches A and B will now be described with reference to switch A. To turn on switch A, such that current can flow through it, a positive pulse is supplied by SWA+ and a relatively negative pulse is supplied by SWA−. The MOSFETs, acting like small capacitors, store the energy that is received in the gates, and force the MOSFETs into the on state. As described with reference to  FIG. 4 , one embodiment of the output controller maintains the gate charge by utilizing a reverse biased zener diode  76 . In order to turn the switch off, a positive pulse is supplied by SWA− and a relatively negative pulse is supplied by SWA+. The negative pulse overrides zener diode  76  ( FIG. 4 ), and pulls the charge off of the gates, forcing the MOSFETs into the off state. The timing and operation of switches A and B and output controller  22  will be described in more detail with reference to  FIGS. 2-4 .  
         [0023]     After passing through switches A and B, power enters coil  56  through node  54 . Coil  56  is, for example, a low-frequency continuous current coil. The current flow through coil  56  is represented by I C  with positive current flow in the direction of fifth node  57 . Coil  56  causes the current to continue flowing even when V A  and V B  are zero. Finally, the output is filtered by capacitor  58 , which is a small capacitor that provides a small amount of filtering to remove any remaining ripple from the output before it enters the load.  
         [0024]     Controller  17  provides overall control and synchronization of power converter  10 . In addition, controller  17  controls switches A and B to maintain the switches on except when blocking a pulse of an unwanted polarity. This method of controlling switches A and B overcomes the problems with voltage spikes that prior power converters face. Voltage spikes occur in prior power converters when all current paths through the output circuit are turned off but current is still trying to flow. The present invention solves this problem by providing a constant path for current to flow through output circuit  16 . Output controller  22  operates switches A and B of output circuit  16  such that the switches only turn off to block undesired pulses. Since the pulses are provided to switches A and B with opposite and alternating polarities, there is never a period when both switches are closed at the same time. Only one switch is ever turned off at a time, and current is always able to flow through at least one of the switches. By providing a constant path for current to flow, voltage spikes cannot build up in the output circuit. This configuration also provides for lagging currents and therefore covers the four quadrant issue that power converters are presented with when supplying inductive loads.  
         [0025]     Primary controller  18  of controller  17  provides two control signals to input controller  20  and output controller  22 : ON TIME, and SIDE A OR /B SELECT. In addition, primary controller  18  provides a third control signal, NEGATIVE SELECT, to output controller  22 . The ON TIME signal is a timing signal that indicates when a pulse begins and ends. In other words, the ON TIME signal indicates the amount of time that a pulse is “on.” The SIDE A OR /B SELECT signal provides a timing signal to indicate whether switch A or switch B should be turned off to block an unwanted pulse. These control signals, and the operation of controller  17 , will be described in more detail with reference to  FIG. 4 .  
         [0026]      FIG. 2  is a timing diagram illustrating the operation of power converter  10 . The desired AC output (V OUT ) is shown. For this timing diagram it is assumed that input circuit  12  ( FIG. 1 ) provides high-frequency pulses to transformer  14  that are pulse-width modulated. When the high-frequency pulses enter transformer  14 , current is induced in secondary winding  32 . This current causes V A  and V B  to have non-zero voltages during the received pulse. Since V A  and V B  are both measured relative to second node  42  (which is connected to center tap  38 ), the voltages at V A  and V B  are the inverse of each other, such that when V A  is positive V B  is negative, and vice versa, as shown.  
         [0027]     Output controller  22  controls switches A and B to form the desired output by selecting whether a positive or a negative pulse is allowed to pass through switches A or B. For example, to create the first half-cycle (the positive half-cycle) of an AC output, it is desirable to operate first and second switches A and B in such a way that all negative pulses are blocked by switches A and B. This is done by allowing switch A to remain on at all times except when a negative pulse appears at switch A. At that point, switch A is turned off to block the negative pulse. After the negative pulse is over, switch A is turned back on. Similarly, switch B is controlled such that switch B remains on at all times except when a negative pulse appears at switch B. In this way, the voltage at node  54  (V A  or V B ) consists of only positive pulses during the first half-cycle. Coil  56  then converts the pulses into continuous current in one direction for half of the AC cycle. The current through coil  56  is shown as I C . Finally, capacitor  58  provides the final filtering to produce the first half-cycle of the AC output.  
         [0028]     Once the first half-cycle of the AC output has been created, the second half-cycle (negative half-cycle) can be created. In order to produce the negative half-cycle, it is desirable to block all positive pulses with switches A and B, but let all negative pulses pass through. Switch A is controlled by output controller  22  such that switch A remains on at all times except when a positive pulse appears at switch A. At that time, switch A is turned off to block the positive pulse. After the positive pulse is over, switch A is turned back on. Similarly, switch B is controlled by output controller  22  to remain on at all times except when blocking positive pulses. In this way, the voltage at node  54  (V A  or V B ) consists of only negative pulses during the second half-cycle. Coil  56  then converts the pulses into a continuous current in the opposite direction for the second half of the AC cycle, which is then filtered by capacitor  58 .  
         [0029]     Some prior power converters suffered from problems during the zero crossing. This occurs when the output voltage pauses at zero volts for a brief period of time, such as between PWM pulses or during the change from the AC positive half cycle to the negative half cycle (and vice versa). During this period, noise can cause minute voltage fluctuations in the output, which cause problems when driving sensitive electronic devices. The present invention solves this problem by eliminating any pause at zero volts. Rather than pausing at zero volts, the output voltage continuously builds with only a minor ripple and transitions smoothly between positive and negative voltage phases of the AC output without pausing. Note, this is all done without the aid of a free-wheeling diode (or AC switch) which adds complexity and still generates some voltage spikes.  
         [0030]      FIG. 3  is an exploded timing diagram illustrating the unique timing of power converter  10  of the present invention. As previously described, V A  and V B  are the voltages at first node  40  and third node  44 , respectively, measured with respect to second node  42 . Switches A and B are controlled by output controller  22  to block the undesired pulses from the output. To form a positive portion of an AC output, the switches are controlled such that only positive pulses pass to the output and all negative pulses are blocked. At t 1 , a first pulse is sent from input circuit  12 , through transformer  14 . As a result, V A  becomes negative and V B  becomes positive. In order to form the positive portion of an AC output the negative pulse must be blocked. This is done by shutting off switch A. Switch B remains on to allow the positive pulse to pass. This positive pulse causes V A  or V B  (at node  54 ) to be positive. This positive voltage is supplied to coil  56  which causes the current through coil  56  (I C ) to rise, resulting in a positive V OUT  at the output.  
         [0031]     After the first pulse has passed, both V A  and V B  return to 0 volts and switch A is turned back on. Now, both switch A and switch B allow coil  56  to maintain the current flow through the transformer, which decreases only slightly. Note that the decrease in current flow is exaggerated in  FIGS. 3 and 4  for illustrative purposes. At t 2 , a second pulse of opposite polarity is sent from input circuit  12 , through transformer  14 . As a result, V A  becomes positive and V B  becomes negative. In order to pass the positive pulse but block the negative pulse, switch A remains on and switch B is turned off. In this way, the positive pulse causes V A  or V B  to once again become positive, and this pulse is passed to coil  56 . Output controller  22  continues operating switches A and B to create the desired output signal V OUT .  
         [0032]      FIG. 4  is a schematic block diagram of one example of output controller  22 . Output controller  22  includes ON pulse generator  60 , ON pulse delay  62 , OFF pulse generator  64 , OFF pulse delay  68 , decoder  70 , first driver  72 , first pulse transformer  74 , first zener diode  76 , second driver  78 , second pulse transformer  80 , and second zener diode  82 .  
         [0033]     Output controller  22  receives three control signals from primary controller  18 : ON TIME, SIDE A OR /B SELECT, and NEGATIVE SELECT. The ON TIME signal is fed into. ON pulse generator  60 , OFF pulse generator  64 , and decoder  70 . The SIDE A OR /B SELECT and NEGATIVE SELECT control signals are fed into decoder  70 . The ON TIME control signal is a timing signal that indicates when pulses begin and end. In an exemplary embodiment, ON TIME is pulse width modulated to allow the formation of pulse width modulated pulses. The SIDE A OR /B SELECT control signal tells decoder  70  whether switch A or switch B should be turned off to block the pulse having the unwanted polarity. The NEGATIVE SELECT control signal tells decoder  70  to reverse the. SIDE A OR /B SELECT timing in order to create the negative half-cycle of the output waveform.  
         [0034]     The ON TIME signal is converted into an ON PULSE and an OFF PULSE by ON pulse generator  60  and OFF pulse generator  64 . This is done because switches A and B require separate control signals to turn on and to turn off, as previously described with reference to  FIG. 1 . ON pulse generator  60  receives the ON TIME control signal and creates an ON PULSE when it detects the leading edge of the ON TIME control signal. The ON PULSE is then delayed by ON pulse delay  62  to allow for more efficient switching. OFF pulse generator  64  also receives the ON TIME control signal, but creates an OFF PULSE when it detects the trailing edge of the ON TIME control signal. The OFF PULSE is then delayed by OFF pulse delay  62 .  
         [0035]     Decoder  70  receives the ON PULSE, OFF PULSE, ON TIME, SIDE A OR /B SELECT, and NEGATIVE SELECT control signals. Using these signals, Decoder  70  determines whether to send the ON and OFF pulses to side A or side B. If, for example, the unwanted pulse is about to be present at switch A, the control signals will instruct decoder  70  to turn off switch A. Decoder  70  receives a positive signal from SIDE A OR /B SELECT which tells decoder  70  that switch A should be controlled. A “low” signal on NEGATIVE SELECT indicates that the positive half-cycle of the output is being created and so switch A is correct. Decoder  70  receives the OFF PULSE, and passes the A OFF PULSE to driver  72 . Driver  72  creates a pulse in first pulse transformer  74  which creates a current through the secondary winding of first pulse transformer  74 . The current provides the appropriate signals for SWA+ and SWA−, which turns off switch A. After the appropriate amount of time, decoder  70  receives the ON PULSE signal. Once again, decoder  70  checks SIDE A OR /B SELECT and NEGATIVE SELECT signal, which indicate that switch A should be controlled. Decoder  70  then provides the A ON PULSE to driver  72 , which creates a pulse in pulse transformer  74 . The pulse creates a current that forms the appropriate SWA+ and SWA− control signals to turn switch A back on. Zener diode  76  ensures that switch A remains in the on state until it is turned off, by maintaining the charge in the gates of switch A.  
         [0036]     Switch B is controlled in the same way when either SIDE A OR /B SELECT is “low” and NEGATIVE SELECT is also “low,” or when SIDE A OR /B SELECT is positive and NEGATIVE SELECT is also positive. In this way, switches A and B can be controlled by output controller  22  to block all unwanted pulses from the output.  
         [0037]     Although the present invention has been described with reference to exemplary embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the present invention. For example, although MOSFET switches have been described as output switches A and B, other forms of switches, such as bipolar switches in parallel or solid state relays, may also be used. In addition, the invention is also applicable to output circuits including a tapless transformer output with an H-bridge.