Abstract:
A low-cost but highly accurate ohmmeter for measuring milliohm resistances is disclosed. The instrument employs a digital voltmeter (analog-to-digital converter) having an add-subtract mode which nulls any drift voltage following each measurement. A self biasing current source which eliminates common mode voltages to the high gain amplifier portion of the converter is used for resistance measurements.

Description:
BACKGROUND OF THE INVENTION 
     The present invention generally relates to electrical measuring instruments, and more particularly to an improved digital volt-ohmmeter capable of measuring milliohm resistances with precision and high accuracy. 
     The heart of any digital volt-ohmmeter is an analog-to-digital converter. Typically, the converter has an analog section and a digital section. The analog section may comprise a high gain differential amplifier connected to receive an input voltage across its input terminals and to provide an output voltage to one input of an analog comparator. The other input of the analog comparator in connected to a source of reference voltage, and when the voltages applied to the two inputs of the analog comparator are equal, an output signal indicative of this condition is generated. The digital section of the analog-to-digital converter may comprise a source of clock pulses connected through a gate to a digital counter. The output signal from the analog comparator is used to develop a gating signal so that the accumulated count in the digital counter is proportional to the voltage connected across the inputs of the high-gain differential amplifier. At the end of the measurement, the count accumulated in the digital counter may be either read out or displayed in a well known manner. 
     Problems arise in the measurement of very small voltage or resistance values. For example, it is often desirable to reliably and accurately measure the resistance of connections to integrated circuits. Such resistances are in the range of millohms. In order to measure such very small resistance values, it is necessary to significantly increase the gain of the input differential amplifier. Very high gains on the order of 1000 are often necessary; however, such high gains are usually accompanied by amplifier drift which adversely affects the accuracy of the measurement made. Moreover, because of the very high gain amplifier required for the measurement of such small resistances, common mode voltages to the amplifier cannot be tolerated. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a low-cost but highly accurate precision ohmmeter for measuring milliohm resistances. The foregoing and other objects of the invention are attained by providing an analog-to-digital converter having an add-subtract mode which nulls any drift voltage following each measurement. For resistance measurements, the instrumental comprises a self-biasing current source which eliminates common mode voltages to the amplifier portion of the converter. The system sensitivity achieved by the present invention is 10μV per milliohm. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The specific nature of the invention, as well as other objects, aspects, uses and advantages thereof, will clearly appear from the following description and from the accompanying drawings, in which: 
     FIG. 1 is a block diagram of the digital voltmeter according to the present invention; 
     FIG. 2 is a logic diagram of the clock and mode control logic which forms a part of the digital voltmeter shown in FIG. 1; 
     FIGS. 3A, 3B and 3C are wave forms illustrating the operation of the digital voltmeter according to the present invention; and 
     FIG. 4 is a schematic diagram of the self-biasing current source used with the digital voltmeter of FIG. 1 for making resistance measurements. de 
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 1 of the drawings, the voltage which is to be measured is applied across input terminals 11 and 12 of gates 13 and 14, respectively. The output of gate 13 is connected to the positive input of high-gain differential amplifier 15, while the output of gate 14 is applied to the negative input of amplifier 15. Circuit ground is connected to the inputs of gates 16 and 17, and the outputs of gates 16 and 17 are connected to the positive and negative inputs, respectively, of the high gain differential amplifier 15. Gates 13, 14 and 16, 17 are controlled by the clock and mode control logic 18 as explained in more detail hereinafter, particularly with reference to FIG. 2 of the drawings. 
     The output of high gain differential amplifier 15 is applied to one input of one analog comparator 19. Analog comparator 19 is a conventional device, known in the art, and is shown as comprising both positive and negative reference voltage sources. The high-gain differential amplifier 15 and the analog comparator 19 constitutes the analog portion of the analog-to-digital converter. 
     The digital portion of the analog-to-digital converter includes a binary counter 20 with provides a parallel output to digital-to-analog converter (DA) 21. The DAC counter 20 receives a gated clock pulse signal, referred to as the DAC clock, from the clock and mode control logic 18. The accumulated count in DAC counter 20 is converted to a corresponding analog voltage by the digital-to-analog converter 21 in a well-known manner. For example, the digital-to-analog converter 21 may be either a resistive or capacitive ladder network of a known design. The output of digital-to-analog converter 21 is connected to the second input of the analog comparator 19. 
     In addition to the DAC counter 20, there is also provided an up/down counter 22, also of well-known type. Up/down counter 22 counts in a forward or up direction in response to count up clock pulses from the clock and mode control logic 18 and counts in a backwward or down direction in response to count down clock pulses from the clock and mode control logic 18. The parallel outputs from up/down counter 22 are connected to display latches 23 which are enabled at the completion of a measurement by the clock and mode logic 18. The outputs of the display latches 23 are connected in parallel to a binary to decimal code converter 24 which energizes a suitable display device 25. Alternatively, the contents of the display latches 23 could be read out to some other data utilization device. 
     The differential amplifier 15 is set up so that it has an offset voltage which is always positive, but the amplitude of that offset voltage is not known because of the long term drift problems associated with very high gain DC amplifiers. This offset voltage adjustment is illustratively shown in FIG. 1 as provided by a variable resistance 26 connected to a source of negative voltage. The up/down counter 22 is used to subtract this output offset after each measurement. When the unknown voltage is being measured, the count that is accumulated in the up/down counter 22 represents the sum of the amplifier gain times V in  plus the amplifier offset voltage at the time of a first &#34;compare&#34; output from analog comparator 19. In order to obtain the correct representation of the unknown voltage V in , the inputs of the high gain differential amplifier 15 are switched to ground reference potential, and the amplifier output voltage binary representation is subtracted from the number previously counted in up/down counter 22. After this offset voltage is substracted, the count remaining in the up/down counter 22 is representative of only the unknown voltage V in . 
     In order to accomplish the measurement as just described, the clock and mode control logic 18 must control the following sequence of events: 
     1. Reset DAC and up/down counters 20 and 22, respectively, to 0. 
     2. Switch differential amplifier 15 inputs ± V in . 
     3. Select &#34;count up&#34; mode for up/down counter 22. 
     4. Gate clock pulses to DAC and up/down counters 20 and 22. 
     5. Stop the clock pulse output when a &#34;compare&#34; signal is generated by the analog comparator 19. 
     6. Reset the DAC counter 20. 
     7. Select to &#34;count down&#34; mode for up/down counter 22. 
     8. Switch the input of amplifier 15 to ground reference potential. 
     9. Gate clock pulses to DAC and up/down counters 20 and 22. 
     10. Stop clock pulses when a &#34;compare&#34; signal is generated by the analog comparator 19. 
     11. Load the count remaining in the up/down counter 22 into display system. 
     The clock and mode control logic 18, which controls the foregoing sequence of events, is illustrated in the logic diagram shown in FIG. 2. The clock 27 may include an oscillator and pulse forming circuits to provide clock pulses to the system. A measurement is initiated by a start pulse applied to one input of OR gate 28, the output of which sets flip-flop 29. Flip-flop 29 enables AND gate 30 which then passes the clock pulses from clock 27 to a decade counter 31. The parallel outputs of decade counter 31 are connected to a binary coded decimal (BC D)-to-decimal converter 32. The first decimal count output from BCD-to-decimal converter 32 is the sample V in  control signal which is connected on the one hand to gates 13 and 14, and on the other hand to a one-shot multivibrator 33 through an OR gate 34. The output pulse from one-shot 33 is used to reset flip-flop 29 and thereby inhibit the clock pulses to decade counter 31. The first decimal count output of BCD-to-decimal converter 32 is also connected to enable AND gate 35, the output of which is connected to the &#34;count up&#34; input to the up/down counter 22. 
     The output of one-shot 33 is additionally connected to the input of one-shot 36, which is triggered by the trailing edge of the output pulse from one-shot 33. The output of one-shot 36 sets flip-flop 37 which enables AND gate 38. The output of clock 27 is connected through AND gate 38 to AND gate 35. Thus, the decimal one output from BCD-to-decimal converter 32 selects the &#34;count up&#34; mode for the up/down counter 22, and when one shot 36 is fired setting flip-flop 37 and enabling AND gate 38, clock pulses are applied to the count up input of up/down counter 22, as well as to DAC counter 20. The delay introduced by one-shot 33 is typically on the order of 20μsec. and is used to allow the output of high gain differential amplifier 15 to stabilize before searching for a &#34;compare.&#34;. 
     When a &#34;compare&#34; signal is generated by the analog comparator, this signal is used to reset flip-flop 37 thereby disabling AND gate 38 and stopping all further clock pulses to the count up input of up/down counter 22. The compare signal is also applied through OR gate 28 to set flip-flop 29 thereby once again enabling AND gate 30. As a result, decade counter 31 begins to count again, and the second decimal count output from BCD-to-decimal converter 32 is a &#34;reset A&#34; which resets the DAC counter 20. The third decimal count output from the BCD-to-decimal converter is not used, but the fourth decimal count output is the sample V REF  which controls gates 16 and 17 to apply ground reference potential to the input of differential amplifier 15. This fourth decimal count output is also applied to one-shot 33 through OR gate 34 and further enables AND gate 39. The output of AND gate 39 is connected to the count down input of up/down counter 22. 
     As before, the output pulse from one-shot 33 resets flip-flop 29 thereby blocking further clock pulses to decade counter 31. One-shot 36 triggers on the trailing edge of the output pulse of one-shot 33 and sets flip-flop 37 to enable AND gate 38 thereby applying clock pulses to the count down input of up/down counter 22 and the DAC counter 20. 
     When a second &#34;compare&#34; signal is generated by the analog comparator, 19, flip-flop 37 is reset, stopping the clock pulses to the count down input of up/down counter 22, and flip-flop 29 is set to once again apply clock pulses to decade counter 31. The fifth decimal count from BCD-to-decimal converter 32 is not used, but the sixth decimal count is the &#34;load display latches&#34; signal which enables the display latches 23 to assume the count remaining in the up/down counter 22. The seventh decimal count output of the BCD-to-decimal converter 32 is not used, but the eighth decimal count is a &#34;reset B&#34; signal which resets the DAC and up/down counters 20 and 22. The ninth and tenth decimal counts could be used to signal an end of the measurement and to reset the system. 
     The principles of the measurement thus far described are illustrated in FIGS. 3A, 3B and 3C. FIG. 3A represents the voltage input to differential amplifier 15 from gates 13 and 14. FIG. 3B represents the output of differential amplifier 15 and illustrates the offset plus drift voltage which is associated with that output. FIG. 3C illustrates the digital-to-analog converter output showing the timing for the measurement of the unknown input voltage V in  during which the up/down counter 22 counts in the forward or up direction. After the first &#34;compare&#34; signal is generated by the analog comparator 19, the digital-to-analog converter again generates an outut voltage during which a measurement of ground reference potential is made and the up/down counter 22 counts in the backward or down direction. It will be appreciated by those skilled in the art that this add-substract feature which permits the nulling of any drift voltage following each measurement allows very inexpensive circuitry to be used for the very high gain differential amplifier 15. 
     To go along with the analog-to-digital converter which makes up the digital voltage meter, a self-referencing current source is used to provide a current into an unknown resistance for resistance measurements. FIG. 4 shows in schematic form the current source for resistance measurements which eliminates common mode voltage problems that might ordinarily be encountered using amplifiers with gains on the order of 1000. The current source comprises a bipolar transistor 40 having its emitter connected through resistor 41 to a source of negative potential and its base connected to circuit ground. The collector of transistor 40 is connected to the negative input of differential amplifier 42. A feedback resistor 43 is connected between the output of differential amplifier 42 and its negative input terminal. In addition, current feedback is provided by means of resistor 44 which is connected between the output of differential amplifier 42 and its positive input. Resistor 44 is also connected to test probe 45 and to one side of the unknown resistor R x . The + V in  input terminal 11 of gate 13 is connected to this same end of the unknown resistance R x  through test probe 46. 
     The current source includes a virtual ground circuit which comprises a second differential amplifier 7. The differential amplifier 47 negative input is connected to the - V in  terminal 12 of gate 14. The positive input of the differential amplifier 47 is connected to test probe 48 and to second end of unknown resistance R x . - V in  terminal 12 of gate 14 also goes to the lower end of R x  through test probe 49. The virtual ground circuit is configured such that the voltage developed at test probe 47 will be the voltage that the virtual ground amplifier 46 output will go below circuit ground. This causes the negative V in  terminal 12 to have no input bias voltage, thereby eliminating the common mode voltage problem previously encountered. 
     It will be apparent that the embodiment shown is only exemplary and that various modifications can be made in construction and arrangement within the scope of the invention as defined in the appended claims.