Abstract:
Architectures of multi-stage sample rate converters are disclosed. According to one aspect of the present invention, a received signal with a higher sampling rate is converted to a lower sampling rate. To prevent aliasing in the resultant signal, an anti-aliasing filter is introduced. The passband of the anti-aliasing filter is so adjusted according to the conversation rate of a sample rate converter. To keep the implementation relatively simple, the coefficients of the filter are kept constant. Therefore, the conversation rate of a sample rate converter is constrained in a limited range, thus requiring only a constant anti-aliasing filter. A series of halfband filters are then used to convert the signal to a desired sampling rate.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention is related to the area of digital signal processing. More particularly, the present invention is related to architectures of an integrated circuit for converting signal sample rates, which can be advantageously used in various wireless communication systems including WiMAX. 
   2. Description of the Related Art 
   The IEEE Standards Authority approved the 802.16 (also referred to as WiMAX) specification for wireless metropolitan-area networks (MANs) in the 2- to 11-GHz range, giving a seal of approval to technology that some people said could enable a disruptive change in communications. This is because partly WiMAX supports different sampling rates. Thus, sample rate converters are needed in both transmitters and receivers. 
   In this disclosure, architectures of multi-stage sample rate converters are disclosed. Besides many other applications, such sample rate converters can be advantageously used in systems supporting WiMAX. 
   SUMMARY OF THE INVENTION 
   This section is for the purpose of summarizing some aspects of the present invention and to briefly introduce some preferred embodiments. Simplifications or omissions in this section as well as in the abstract and the title may be made to avoid obscuring the purpose of this section, the abstract and the title. Such simplifications or omissions are not intended to limit the scope of the present invention 
   The invention pertains to architectures of multi-stage sample rate converters are disclosed. According to one aspect of the present invention, a received signal with a higher sampling rate is decimated to a lower sampling rate. To prevent aliasing in the resultant signal, an anti-aliasing filter is introduced. The passband of the anti-aliasing filter is so adjusted according to the conversation rate of a sample rate converter. To keep the implementation relatively simple, the coefficients of the filter are kept constant. Therefore, the conversation rate of a sample rate converter is constrained in a limited range, thus requiring only a constant anti-aliasing filter. A series of halfband filters are then used to convert the signal to a desired sampling rate. 
   The present invention may be implemented as an integrated circuit, an apparatus or a part of a system. According to one embodiment, the present invention is an integrated circuit comprising: an anti-alias filter to receive an input signal with a first sampling rate, the anti-alias filter designed to have a cut-off frequency; a sample rate converter, coupled to the anti-alias filter, designed to have a converting ratio that directly determines the cut-off frequency of the anti-alias filter; and one or more down-sampling converters coupled in series to the sample rate converter. As a result, an output with a second sampling rate is produced, wherein the first and second sample rates are generally different. 
   One of the objects, advantages and benefits of the present invention is to provide an architecture that can efficiently convert an input signal with a first sampling rate to an output signal with a second sample rate. Such an architecture may be advantageously used in various wireless communication systems including WiMAX 
   The foregoing and other objects, features and advantages of the invention will become more apparent from the following detailed description of a preferred embodiment, which proceeds with reference to the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and in which: 
       FIG. 1A  shows an exemplary architecture of a multi-stage sample rate converter according to one embodiment of the present invention; 
       FIG. 1B  shows the working principle of a sample rate converter that may be used in the architecture of the multi-stage sample rate converter in  FIG. 1A ; 
       FIG. 1C  shows a table of coefficients derived to be used to calculate the distance between two samples in the input and output signals (sequences); 
       FIG. 2  shows that a sample rate converter with Lagrange polynomial interpolator is implemented with a Farrow structure as in  FIG. 2 , where the number of unit delay elements is minimized; 
       FIG. 3  shows an implementation of a multi-stage sample rate converter that includes an anti-aliasing filter, a sample rate converter and three down-sampling converters 
       FIG. 4A  shows a partial spectrum of an exemplary input signal, which further shows a period of 2π in the frequency domain; and 
       FIG. 4B  shows a situation of signal aliasing which is caused by an input signal being down-sampled by R that expands R times in the frequency domain, resulting in overlapping with its images. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The detailed description of the invention is presented largely in terms of procedures, steps, logic blocks, processing, and other symbolic representations that directly or indirectly resemble the operations of data processing devices coupled to networks. These process descriptions and representations are typically used by those skilled in the art to most effectively convey the substance of their work to others skilled in the art. 
   Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the sample embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Further, the order of blocks in process flowcharts or diagrams representing one or more embodiments of the invention do not inherently indicate any particular order nor imply any limitations in the invention. 
   Referring now to the drawings, in which like numerals refer to like parts throughout the several views.  FIG. 1A  shows an exemplary architecture  100  of a multi-stage sample rate converter according to one embodiment of the present invention. The architecture  100  includes an anti-alias filter  102 , a sample rate converter  104  and a set of down-sampling converters  106 . The anti-alias filter  102  is essentially a low-pass filter with a cut-off frequency that is determined with respect to the sample rate converter  104 . According to one embodiment, the sample rate converter  104  is implemented with reference to Lars Erup, “Interpolation in digital modem—part II, implementation and performance”, IEEE Transactions on Communications, Vol. 41, No.: 16, June 1993, pp. 998-1008, which is hereby incorporated by reference. 
   One of the parameters the sample rate converter  104  has is a converting ratio between the sampling rates of the input and output signals. In general, the higher the ratio is, the lower the cut-off frequency of the anti-alias filter  102  has. From the hardware implementation perspective, the ratio is typically kept low (which may not be an integer) so that both the performance and easy hardware implementation of the anti-alias filter  102  as well as the sample rate converter  104  can be readily guaranteed. In one embodiment of down-sampling an input signal, provided that the sample rates for the input and output signals are Fin and Fout, respectively. Then the overall converting ratio R is equal to Fout/Fin. Whenever R is greater than 2, a half-band filter can be used. Accordingly, the converting ratio of the sample rate converter is generally greater than 1 but less than 2. 
     FIG. 1B  shows the working principle of the sample rate converter  104 . It is assumed there is an input sequence {A} with a sampling rate 48 MHz that needs to be converted to a sequence {B} with sampling rate of 60 MHz. In time domain, the positions of {A} and {B} are shown in  FIG. 1B . In other words, the value of each point of {B} needs to be calculated according to the corresponding adjacent points of {A}. 
   For each point B(n), the nearest point of {A} on its left, named A(m) is located. Then a five-order Lagrange polynomial interpolation is performed in accordance with the following equation: 
             B   ⁡     (   n   )       =       ∑     i   =     -   2       3     ⁢       C   i     ⁢     A   ⁡     (     m   +   i     )                 
It is assumed that the distance between B(n) and A(m) is μ, the coefficients C i  are derived and listed in Table 1 shown in  FIG. 1C . The sample rate converter  104  with Lagrange polynomial interpolator is implemented with Farrow structure as in  FIG. 2 , where the number of unit delay elements is minimized.
 
   It can be understood that the multi-stage sample rate converter  100  may be used for converting a sampling rate downwards as well as a sampling rate upwards.  FIG. 3  shows an implementation of a multi-stage sample rate converter  300  that includes an anti-aliasing filter  302 , a sample rate converter  304  and three down-sampling converters  306 ,  308  and  310 . The outputs from the sample rate converter  304  and the three down-sampling converters  306 ,  308  and  310  are coupled to a multi-port switch  312  (e.g., a multiplexer) controlled by a control signal from a controller  314 . As described above, the cut-off frequency of the anti-aliasing filter  302  is directly related to the converting ratio of the sample rate converter  304 . 
   According to one embodiment, the passband of the anti-aliasing filter  302  is adjusted according to the bandwidth of the input signal. The narrower the bandwidth of the input signal is, the higher the order of anti-aliasing filter is. To avoid the complexity of the anti-aliasing filter  302 , the converting ratio of the sample rate converter  304  is limited in range, which thus requires only a constant anti-aliasing filter. The further down-sampling of the sampling rate of the input sequence is performed by a set of down-sampling converters, such as the three down-sampling converters  306 ,  308  and  310 . More down-sampling converters may be used if necessary. In one embodiment, each of the down-sampling converters is a half-band filter. 
     FIG. 4A  shows a partial spectrum of an exemplary input signal, which further shows a period of 2π in the frequency domain.  FIG. 4B  shows a situation of signal aliasing which is caused by the input signal being down-sampled by R that expands R times in the frequency domain, resulting in overlapping with its images. To avoid such overlapping, the anti-aliasing filter  302  is introduced. If the down-sample rate (converting ratio) is R, in one embodiment, the pass-band of the anti-aliasing filter  302  is designed to be around π/R . With this limitation, the signal would not expand to π after the down-sampling, thus avoiding the overlapping (i.e., aliasing). 
   In operation, an input data sequence is coupled to the anti-aliasing filter  302  that filters out frequencies higher than the cut-off frequency. The filtered signal is then coupled to the sample rate converter  304  that converts the signal to a signal with a sampling rate per the fixed converting ratio of the sample rate converter  304 . This converted signal is then going through a number of down-sampling converters with a fixed converting ratio (e.g., 2). Each of the down-sampling converters (three of them are shown in the figure) produces a converted signal with a sampling rate lower than a previous one. These outputs, from the sample rate converter  304  as well as the three down-sampling converters  306 ,  308  and  310 , are coupled to the multi-port switch  312 . The output sequence can be produced from any one of the outputs via the multi-port switch  312  depending on application. 
   The present invention has been described in sufficient detail with a certain degree of particularity. It is understood to those skilled in the art that the present disclosure of embodiments has been made by way of examples only and that numerous changes in the arrangement and combination of parts may be resorted without departing from the spirit and scope of the invention as claimed. While the embodiments discussed herein may appear to include some limitations as to the presentation of the information units, in terms of the format and arrangement, the invention has applicability well beyond such embodiment, which can be appreciated by those skilled in the art. Accordingly, the scope of the present invention is defined by the appended claims rather than the foregoing description of embodiments.