Abstract:
A method and apparatus are disclosed for predistorting an input signal to a non-linear amplifier. An appropriate precorrection is determined for the input signal over a series of iterative stages according to an amplifier model. The amplifier model includes a limiting function that clips the input signal to reduce error due to amplifier saturation. The determined precorrection is then applied to the input signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to the field of signal correction in a communication system, and, more particularly, to precorrection of an information carrying input signal to a non-linear amplifier. 
     2. Description of the Prior Art 
     Correction for amplifiers has attracted a significant amount of interest recently, mainly due to increasingly strict requirements for spectral purity and demands for increased efficiency. With digital signal processing (DSP) circuits becoming less expensive and more powerful, predistortion of an information carrying signal has become a popular means of meeting these requirements. 
     Predistortion is relatively straightforward in a memoryless system. In a memoryless system, the output of the system at a given time depends solely on the input to the system at the given time. A solid first approximation of the characteristics of a memoryless amplifier can be provided by the transfer curves of the amplifier. Predistortion in such systems is well known in the art. 
     Most practical amplifiers, however, have memory, in the sense that prior inputs have an effect on the present output. Such a system can be only roughly approximated by memoryless system. One approach for dealing with non-linear systems with memory involves the Volterra series. When dealing with high power amplifiers, however, the limitations of the Volterra series become apparent; under present theory, a finite Volterra series can not handle the saturation that plagues any practical amplifier. 
     Efforts have been made to work around this limitation, but these efforts have achieved only limited success. One system was described at the Thirty-Second Annual Asilomar Conference on Signals, Systems, and Computing under the title “Exact and pth Order Equalization and Linearization of Recursive Polynomial Systems.” The system is shown to be capable of approximating non-linear systems with memory using the Volterra series. The derived model, however, is effective only for systems in which the amplifier model is of general minimum phase type. By “general phase type”, it is meant that the error is leading the signal, much as in a linear system that is non-minimum phase. Such a limitation is impractical for many applications. 
     SUMMARY OF THE INVENTION 
     To overcome the limitations discussed above, an apparatus is provided for precorrection of non-linear amplifiers, in particular those with memory. To this end, a method is disclosed for predistorting an input signal to a non-linear amplifier. An appropriate precorrection is determined for the input signal over a series of iterative stages according to an amplifier model. The amplifier model includes a limiting function that clips the input signal to reduce error due to amplifier saturation. The determined precorrection is then applied to the delayed input signal. 
     In accordance with another aspect of the invention, a method is disclosed for predistorting an input signal to a non-linear amplifier. An appropriate precorrection is determined for the input signal over a series of iterative stages, according to an amplifier model. The input signal is delayed between iterative stages. The determined precorrection is then applied to the delayed input signal. 
     In accordance with yet another aspect of the invention, an apparatus is disclosed for predistorting an input signal to a non-linear amplifier. The apparatus comprises a series of correction elements. Each of the correction elements includes a predistortion calculation portion that determines an appropriate precorrection for a signal input into the correction element in accordance with an amplifier model. The amplifier model includes a limiting function that clips the input signal to reduce error due to amplifier saturation. Each also includes a difference element that applies the determined precorrection to the delayed input signal. 
     In accordance with still another aspect of the invention, an apparatus is disclosed for predistorting an input signal to a non-linear amplifier. The apparatus comprises a series of correction elements. Each of the correction elements includes a predistortion calculation portion that determines an appropriate precorrection for a signal input into the correction element in accordance with an amplifier model. The correction elements also include a delay portion that delays the input signal. Additionally, each includes a difference element that applies the determined precorrection to the delayed input signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other features of the present invention will become apparent to one skilled in the art to which the present invention relates upon consideration of the following description of the invention with reference to the accompanying drawings, wherein: 
     FIG. 1 is a functional block diagram of the present invention; 
     FIG. 2 is a flow diagram illustrating the operation of an example embodiment of the present invention; 
     FIG. 3 is a functional block diagram of an alternate embodiment of the present invention; 
     FIG. 4 is a flow diagram illustrating the operation of an alternate embodiment of the present invention; 
     FIG. 5 is a graph showing the improvement in signal-to-distortion ratio in the present invention with the increase in the number of iterative stages used in the predistorter; 
     FIG. 6 is a functional diagram of an embodiment of the present invention in an adaptive predistortion system; 
     FIG. 7 is a functional diagram of an alternate embodiment of the present invention in an adaptive predistortion system; 
     FIG. 8 is a functional diagram of another alternate embodiment of the present invention in an adaptive predistortion system. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The predistorter of the present invention relies upon an iterative process to calculate and apply a predistortion to an information-carrying signal. For any practical amplifier, the iterative model will converge to provide an estimation of the predistortion necessary to correct for the distortion introduced by the amplifier. Further, this model may be improved almost indefinitely by the addition of more iterative stages and, with the addition of a delay, retains its effectiveness for amplifier models that lack general minimum phase characteristics. 
     The stability of the iterative model is maintained by including a soft-limiter function within the predistortion calculation. The soft-limiter function, in effect, compares the output of the amplifier to a clipped version of the original input. This allows the error to remain small near saturation levels, since the “error” is calculated as the difference between the output and this clipped version of the input. This has two advantages. To begin with, the error is kept small so that the iterative predistorter will converge, as convergence is only possible in a system where the error is bounded. Secondly, since a saturating amplifier is not invertable in a mathematical sense, avoiding saturation through the soft-limiter allows mathematical modeling of the inverse to remain a tractable problem. 
     FIG. 1 illustrates the iterative predistorter  10  of the present invention. The input signal U o (t) is passed to a cascade of correction elements  14 A- 14 N. The number of correction elements will vary with the application. While the accuracy of the predistortion will increase with the number of correction elements used, additional correction elements will increase the cost, complexity, and overall delay of the system. 
     The correction elements can be implemented in several ways. An analog set-up is feasible, where the precorrection is calculated by running the signal through a model amplifier and subtracting the original signal from the calculated signal. Alternatively, an appropriate correction term for a given input signal can be retrieved from a look-up table at each stage. In an example embodiment, the correction stages are implemented as digital signal processing devices (DSP). Accordingly, the elements and components described below may be conceptualized as functional blocks with the processor, as opposed to physical components of the system. 
     Each correction element (e.g.,  14 A) includes a predistortion calculation element  18 A- 18 N and a difference element  20 A- 20 N. The first correction element  14 A receives the input signal as input at the predistortion calculation element  18 A, and outputs a distorted signal from the difference element  20 A. Each correction element  14 B- 14 N after the first receives the output of the preceding element at the predistortion calculation portion  18 B- 18 N and samples the original signal at its difference element  20 B- 20 N. Thus, each successive correction element  14 B- 14 N acts to further refine the calculation of the predistortion. At the final correction element  14 N, the distorted signal is provided to an amplifier  22 . The distortion to the signal is intended to produce a predistorted input signal that will produce a desired output from the amplifier  22 . 
     A predistortion calculation element  18 A- 18 N receives an input signal and determines the amount of predistortion necessary to correct the input signal. Generally, this is accomplished by distorting the signal according to an amplifier model, and calculating the difference between the original and the distorted signal. It should be noted that each of the predistortion calculation elements  18 A- 18 N, calculate their precorrection according to the same function, ε(U), which is based upon the amplifier model. The characteristics of the amplifier will vary with the application, but the amplifier model of the present invention can be stated generally as: 
     y=p[U t +ε(u t )], where 
     y is the expected output value of the amplifier 
     u t  is the value of the original input signal; 
     ε(U t ) is the error expected to be introduced to the signal by the amplifier; and 
     p is a limiter function that clips the input signal when its absolute value exceeds a predetermined threshold. 
     The limiter function p reflects the behavior of the amplifier near saturation. Accordingly, the threshold value of the limiter can be set to reflect the saturation point of the amplifier, or it can be set at lower value to avoid driving the amplifier into heavy saturation. 
     The output of the predistortion calculation portion  18  is provided as one input of a difference element  20 . The original signal is sampled to provide the second input. The difference element  20  acts to subtract the calculated predistortion from the original signal. This is intended to distort the signal toward the ideal input signal for the amplifier. 
     At the final correction element  14 N, the distorted signal is output to the amplifier  22 . The amplifier  22 , in accordance with the model, nullifies the distortions introduced to the input signal. The output of the amplifier is essentially a distortion free replica of the original input signal. 
     FIG. 2 is a flow diagram of the run-time operation of a digital implementation of the present invention. The process  50  begins at step  52 . The process then proceeds to step  54 , where a counter variable, i, is initiated to a value of zero. The process then advances to step  56 , where the input signal U i (t) is sampled. For i=0, this signal is the original input signal. For i&gt;0, the sampled signal will be distorted, having undergone one or more iterations within the predistorter. 
     The process then advances to step  58 , where the sampled input signal is predistorted using a previously estimated correction function. At step  60 , the calculated predistortion is subtracted from the original input signal. As a result, the signal is precorrected as to counteract, in part, the distortion imposed by the amplifier. The process then proceeds to step  62 , where the system determines if the signal has passed through a sufficient number of iterative stages. In the example embodiment, this number is a predetermined threshold, but as an alternate embodiment, the system could terminate the iterations when the difference between successive signals becomes sufficiently small. If the proper number of iterations has not been reached, the process continues to step  64 . At step  64 , the counter variable is incremented upwards by one, and the process returns to step  56  to begin another iteration. 
     Returning to the decision at step  62 , if the proper number of iterations have been completed, the process progresses to step  66 , where the corrected signal is amplified and transmitted. The process then terminates at step  68 . 
     For an amplifier whose error is leading the signal (i.e. the amplifier lacks the general minimum phase property), the ideal inverse will not be causal or stable, even with the addition of the soft-limiter. This is comparable to a traditional linear non-minimum phase filter, which shows similar properties and lacks a stable inverse. To avoid this destabilizing effect, it is preferable to delay the input signal as the iterations are resolved. Thus, the accuracy of this model comes at a trade-off when dealing with an amplifier lacking general minimum phase characteristics; a stable model can be achieved and made indefinitely accurate, but at the cost of increasing the associated delay. 
     FIG. 3 illustrates an alternate embodiment  10 ′ of the iterative predistorter incorporating the delay discussed above. As before, the input signal U o ,(t) is passed to a cascade of correction elements  114 A- 114 N. With the addition of the delay, each correction element (e.g.,  114 A) can be envisioned as containing three basic components: a delay element  116 A- 116 N, a predistortion calculation element  118 A- 118 N, and a difference element  120 A- 120 N. The first correction element  14 A receives the input signal as input at both the delay element and the predistortion calculation element. It outputs both a delayed signal from the delay portion  116 A and a distorted signal from the difference element  120 A. Each correction element  114 B- 114 N after the first receives the outputs of the preceding element as its inputs. Thus, each successive correction element  114 B- 114 N acts to further delay the delayed signal and refine the calculation of the distortion. At the final correction element  114 N, the distorted signal is provided to an amplifier  122 . The distortion to the signal is intended to produce an ideal input signal that will produce a desired output from the amplifier  122 . 
     The delay elements  116 A- 116 N impose a time delay of a predetermined period on the original input signal U o (t). This occurs at each correction element  114 A- 114 N, such that the delayed output of the N th  correction element will be delayed by a period equal to N times the predetermined period. In an analog embodiment of the system, the delay may by imposed via a transmission line, a filter, or a similar time delaying device. 
     A predistortion calculation element  118 A- 118 N receives an input signal and determines the amount of predistortion necessary to correct the input signal. Generally, this is accomplished by distorting the signal according to an amplifier model, and calculating the difference between the original and the distorted signal. It should be noted that each of the predistortion calculation elements  18 A- 18 N, calculate their precorrection according to the same function, ε(U), which is based upon the amplifier model. The characteristics of the amplifier will vary with the application, but the amplifier model of the present embodiment can be stated generally as: 
     y=p[U t-D +ε(U t )], where 
     y is the expected output value of the amplifier 
     U t  is the value of the original input signal; 
     U t-d  is the value of the input signal after the predetermined period of delay; 
     ε(U t ) is the error expected to be introduced to the signal by the amplifier; and 
     p is the limiter function that clips the input signal when its absolute value exceeds a predetermined threshold. 
     As before, the output of the predistortion calculation portion is provided as one input of a difference element  120 . The second input is now provided by the delayed signal provided by the delay portion. The difference element  120  acts to subtract the calculated predistortion from the delayed signal. This is intended to distort the signal toward the ideal input signal for the amplifier. 
     At the final correction element  114 N, the distorted signal is output to the amplifier  122 . The amplifier  122 , in accordance with the model, nullifies the distortions introduced to the input signal. The output of the amplifier is essentially a distortion free replica of the original input signal. 
     FIG. 4 is a flow diagram of the run-time operation of a digital implementation of an alternate embodiment of the present invention incorporating a delay between iterative stages. The process  150  begins at step  152 . The process when proceeds to step  154 , where a counter variable, i, is initiated to a value of zero. The process then advances to step  156 , where the input signal u i (t) is sampled. For i=0, this signal is the original input signal. For i&gt;0, the sampled signal will be delayed and distorted, having undergone one or more iterations within the predistorter. 
     The process then advances to step  158 , where the sampled input signal is used to calculate a predistortion value based on the amplifier model. This value represents the amount of predistortion necessary to counteract the distorting effects of the amplifier. The process then proceeds to step  160 , where the original signal is delayed for a predetermined period of time. 
     At step  162 , the calculated final value from the iterative predistortion process is subtracted from the delayed input signal. As a result, the signal is precorrected as to counteract, in part, the distortion imposed by the amplifier. The process then proceeds to step  164 , where the system determines if the signal has passed through a sufficient number of iterative stages. 
     In the example embodiment, this number is a predetermined threshold, but as an alternate embodiment, the system could terminate the iterations when the difference between successive signals becomes sufficiently small. If the proper number of iterations has not been reached, the process continues to step  166 . At step  166 , the counter variable is incremented upwards by one, and the process returns to step  156  to begin another iteration. 
     Returning to the decision at step  164 , if the proper number of iterations have been completed, the process progresses to step  168 , where the corrected signal is amplified and transmitted. The process then terminates at step  170 . 
     Some amount of error will remain in the amplified signal, the degree of error varying inversely with the number of correction elements used. FIG. 5 illustrates the results of experimentation with a sample non-linear amplifier model with non-minimum phase characteristics:          y   t     =         x     t   ·   1              x     t   ·   1                   arctan        (            x     t   -   1            +          0.1        x   t              )       *          [     1   -     0.1        arctan        (       ∑     i   =   1     9                          x     t   -   i     f            )                           (       0.1             x     t   -   1              +     0.1             x   t              )       /     (     1   +          x     t   -   1              )                                          
     The graph shows signal-to-distortion ratio in decibels (dB) as a function of the number of iterations (i.e. correction stages) used in the predistorter. As the graph makes apparent, the signal-to-distortion ratio of the amplified signal decreases from around −11 dB for the uncorrected signal to −30 dB for a signal corrected through five iterations of the predistorter. In other words, the signal-to-distortion ratio is improved by nearly a factor of ten. Further iterations result in increased gains, with a reduction to −47 dB at thirty iterations. As FIG. 5 illustrates, so long as the system can accept a sufficiently large delay, the quality of the signal can be improved almost indefinitely. 
     FIG. 6 illustrates the predistorter of the present invention embodied in a communications system  200  with adaptive predistortion. The adaptive predistortion of this embodiment may be used successfully with either the initial embodiment introduced in FIG. 1 or the alternate embodiment of FIG. 3 that incorporates delays between the iterative stages. FIG. 6 contains a number of components in common with FIGS. 1 and 3, and discussion of these common components will be omitted except as they relate to the particular functions of the illustrated embodiment. 
     Turning to the illustrated embodiment, the input signal is provided by an exciter  224 . The signal is iteratively precorrected using a series of correction elements  214 A- 214 N. Each correction element  214 A- 214 N is controlled by a processing unit  226 . The processing unit samples the input signal and the output of the amplifier  222 , and estimates the amount of predistortion necessary to counteract the distortion introduced during amplification of the signal. This estimation is then provided to the correction elements  214 A- 214 N to refine the precorrection of the signal. In the example embodiment, the processing unit  226  is implemented as a digital signal processor. 
     After the signal is predistorted, it is passed to an up-converter  228 . Here, the signal is up-converted and passed to the amplifier  222 . The output of the amplifier is sampled through a down-converter  230  to the processing unit  226  for comparison with the original input signal. The results of this comparison are used to provide an accurate estimation of the amplifier error for the iterative predistortion. 
     FIG. 7 illustrates the claimed predistorter embodied in an alternative communications system  200 ′ with adaptive predistortion. FIG. 7 contains a number of components in common with FIG.  6 . Discussion of these common components will be omitted except as they relate to the particular functions of the illustrated embodiment. The numbering of these components will remain unchanged. 
     Turning to the illustrated embodiment, the input signal is provided by an exciter  224 . The signal is iteratively precorrected at a series of correction elements  214 A- 214 N. Each correction element  214 A- 214 N is controlled by a processing unit  226 . The processing unit samples the up-converted output of the final correction element  214 N and the output of the amplifier  222 . As before, the processing unit  226  is implemented as a digital signal processor in the example embodiment. 
     After the signal is predistorted, it is passed to an up converter  228 . The up-converted signal is sampled to the processing unit  226  through a down-converter  232 , and passed to the amplifier  222 . The output of the amplifier is sampled through a second down-converter  230  to the processing unit  226  for comparison with the predistorter output. The results of this comparison are used to provide an accurate estimation of the amplifier error to the correction elements  214 A- 214 N. 
     FIG. 8 illustrates the claimed predistorter embodied in a third communications system  200 ″ with adaptive predistortion. FIG. 8 contains a number of components in common with FIG.  7 . Discussion of these common components will be omitted except as they relate to the particular functions of the illustrated embodiment. The numbering of these components will remain unchanged. 
     Turning to the illustrated embodiment, the input signal is provided by an exciter  224 . The signal is iteratively precorrected at a series of correction elements  214 A- 214 N. Each correction element  214 A- 214 N is controlled by a processing unit  226 . The processing unit samples the output of the final correction element  214 N and the output of the amplifier  222 . As before, the processing unit  226  is implemented as a digital signal processor in the example embodiment. 
     After the signal is predistorted, it is sampled to the processing unit  226 . It is then passed to an up-converter  228 , which up-converts the signal and passes it to the amplifier  222 . The output of the amplifier is sampled through a down-converter  230  to the processing unit  226  for comparison with the predistorter output. The results of this comparison are used to provide an accurate estimation of the amplifier error to the error correction elements  214 A- 214 N. 
     It will be understood that the above description of the present invention is susceptible to various modifications, changes and adaptations, and the same are intended to be comprehended within the meaning and range of equivalents of the appended claims. The presently disclosed embodiments are considered in all respects to be illustrative, and not restrictive. The scope of the invention is indicated by the appended claims, rather than the foregoing description, and all changes that come within the meaning and range of equivalence thereof are intended to be embraced therein.