Abstract:
A display device and a method of driving the display device are provided. The display device includes a scan driver for transmitting scan signals to a plurality of scan lines, a data driver for transmitting data signals to a plurality of data lines, and a signal controller for controlling the transmissions of the scan driver and the data driver. The scan driver and the data driver are configured to begin operating in response to a reset signal. The signal controller is configured to detect the reset signal, to determine whether the detected reset signal is a normal reset signal or an abnormal reset signal applied after an on time at which power is supplied to the scan driver and the data driver, and to apply a normal reset signal when the detected reset signal is determined to be an abnormal reset signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority to and the benefit of Korean Patent Application No. 10-2008-0030323 filed in the Korean Intellectual Property Office on Apr. 1, 2008, the entire content of which is incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a display device and a method of driving the same. 
         [0004]    2. Description of the Related Art 
         [0005]    When a display device is turned on and starts to operate, a reset signal is input to a driver that controls the operation of the display device. The reset signal is a starting signal that initializes the driver in order to operate the display device. 
         [0006]    The reset signal has a predetermined waveform after power is supplied to the display device. The driver starts to operate when sensing the reset signal. In some instances, the reset signal may not have the predetermined waveform or the driver may not recognize the reset signal. Then, the driver is not started normally, and thus the display device may operate abnormally. Specifically, when the display device operates abnormally, an abnormal driving voltage and/or an abnormal driving command to control the driver are provided in the initial operation of the driver. An abnormal driving voltage and an abnormal driving command cause abnormally low luminance or abnormally high luminance of images, gray level distortion of images and abnormal colors in images. 
       SUMMARY OF THE INVENTION 
       [0007]    The present invention provides a display device and a method of driving the same which detects whether a reset signal is abnormal and generating a normal reset signal to initialize a driver. 
         [0008]    The present invention provides a display device and a method of driving the same for preventing abnormally low luminance or abnormally high luminance of images, gray level distortion of images, and abnormal colors in images caused by an abnormal reset signal. 
         [0009]    An exemplary embodiment of the present invention provides a display device including: a scan driver for transmitting scan signals to a plurality of scan lines; a data driver for transmitting data signals to a plurality of data lines; and a signal controller for controlling the transmissions of the scan driver and the data driver, wherein the scan driver and the data driver are configured to begin operating in response to a reset signal, and wherein the signal controller is configured to detect the reset signal, to determine whether the detected reset signal is a normal reset signal or an abnormal reset signal applied after an on time at which power is supplied to the scan driver and the data driver, and to apply a normal reset signal when the detected reset signal is determined to be an abnormal reset signal. 
         [0010]    The scan driver and the data driver may be configured to begin operating when a voltage of the reset signal is adjusted from a first level to a second level after the on time. 
         [0011]    The signal controller may be configured to determine that the detected reset signal is an abnormal reset signal when the detected reset signal corresponds to the first level at the on time and the voltage of the reset signal is not adjusted after the on time, and to apply a normal reset signal by adjusting the voltage of the reset signal to the second level. 
         [0012]    The signal controller may be configured to determine that the detected reset signal is an abnormal reset signal when the detected reset signal corresponds to the second level at the on time, and to apply a normal reset signal by adjusting the voltage of the reset signal to the first level, and then adjusting the voltage of the reset signal back to the second level. 
         [0013]    The signal controller may be configured to determine that the detected reset signal is an abnormal reset signal when the reset signal is adjusted from the first level to the second level at or before the on time, and to apply a normal reset signal by adjusting the voltage of the reset signal to the first level, and then adjusting the voltage of the reset signal back to the second level. 
         [0014]    The first level may correspond to a low level and the second level may correspond to a high level. 
         [0015]    The display device may further include: a plurality of pixels arranged in a matrix, each of the plurality of pixels including a switching transistor and a driving transistor; a driving voltage line for transmitting a driving voltage to the driving transistors of the plurality of pixels; a voltage generator for applying the driving voltage to the driving voltage line; and a gray voltage generator for generating a gray voltage, wherein the data driver is configured to convert an input video signal to a data voltage in accordance with the gray voltage and to apply the data voltage to the data lines. 
         [0016]    Each of the plurality of pixels may further include a capacitor coupled between an input terminal and a control terminal of the driving transistor, wherein the scan signals may be transmitted to a control terminal of the switching transistor, and wherein an output terminal of the switching transistor may be coupled to the control terminal of the driving transistor, an input terminal of the switching transistor may be coupled to a corresponding one of the data lines, and an output terminal of the driving transistor may be coupled to a light emitting element. 
         [0017]    The light emitting element may be an organic light emitting diode. 
         [0018]    Another exemplary embodiment of the present invention provides a method of driving a display device including at least one driver configured to begin operating after power is supplied in accordance with a reset signal, the method including: detecting the reset signal; determining whether the detected reset signal is a normal reset signal or an abnormal reset signal after the power is first supplied; and applying a normal reset signal when the detected reset signal is determined to be an abnormal reset signal. 
         [0019]    A normal reset signal may be detected when a voltage of the reset signal is adjusted from a first level to a second level after the power is first supplied. 
         [0020]    An abnormal reset signal may be detected when the voltage of the reset signal corresponds to the first level when the power is first supplied and the voltage of the reset signal is not adjusted after the power is first supplied, and wherein applying a normal reset signal may include adjusting the voltage of the reset signal to the second level. 
         [0021]    An abnormal reset signal may be detected when the voltage of the reset signal corresponds to the second level when the power is first supplied, and wherein applying a normal reset signal may include adjusting the voltage of the reset signal to the first level, and then adjusting the voltage of the reset signal back to the second level. 
         [0022]    An abnormal reset signal may be detected when the voltage of the reset signal is adjusted from the first level to the second level at or before a time when the power is first supplied, and wherein applying a normal reset signal may include adjusting the voltage of the reset signal to the first level, and then adjusting the voltage of the reset signal back to the second level. 
         [0023]    As described above, the present invention may detect whether a reset signal is abnormal and generates a normal reset signal to initialize the driver. Accordingly, it is possible to prevent abnormally low luminance or abnormally high luminance of images, gray level distortion of images, and abnormal colors in images caused by an abnormal reset signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0024]      FIG. 1  is a schematic block diagram of an organic light emitting display device according to an exemplary embodiment of the present invention. 
           [0025]      FIG. 2  is an equivalent circuit diagram of a single pixel in the organic light emitting display device according to an exemplary embodiment of the present invention. 
           [0026]      FIG. 3  is a drawing illustrating waveforms of abnormal reset signals. 
           [0027]      FIG. 4  is a drawing illustrating restoration of reset signals having abnormal waveforms in the organic light emitting display device according to an exemplary embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0028]    In the following detailed description, only certain exemplary embodiments of the present invention have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification. 
         [0029]    Throughout this specification and the claims that follow, when it is described that an element is “coupled” to another element, the element may be “directly coupled” to the other element or “electrically coupled” to the other element through one or more additional elements. In addition, unless explicitly described to the contrary, the word “comprise”, and variations such as “comprises” and “comprising”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements. 
         [0030]    An organic light emitting display according to an exemplary embodiment of the present invention will now be described with reference to  FIGS. 1 and 2 . 
         [0031]      FIG. 1  is a schematic block diagram of an organic light emitting display according to an exemplary embodiment of the present invention and  FIG. 2  is an equivalent circuit diagram of a single pixel of the organic light emitting display according to an exemplary embodiment of the present invention. 
         [0032]    As shown in  FIG. 1 , the organic light emitting display according to an exemplary embodiment of the present invention includes a display panel  100 , a scan driver  200 , a data driver  300 , a gray voltage generator  500 , a voltage generator  600 , and a signal controller  400 . 
         [0033]    The display panel  100  includes a driving voltage line VL, a plurality of scan signal lines S 1  through Sn, a plurality of data lines D 1  through Dm, and a plurality of pixels PX respectively connected to the plurality of scan lines S 1  through Sn and the plurality of data lines D 1  through Dm and arranged in a matrix form. 
         [0034]    A plurality of scan signals are respectively transmitted through the plurality of scan signal lines S 1  through Sn and a plurality of data signals are respectively transmitted through the plurality of data lines D 1  through Dm. The scan signals S 1  through Sn extend in a row direction and are arranged in parallel, and the data lines D 1  through Dm extended in a column direction and are also arranged in parallel. 
         [0035]    The driving voltage line VL transmits a driving voltage VDD and includes a main line VLm and a plurality of branch lines VLb branching off from the main line VLm. The main line VLm extends in a row direction and the branch lines VLb extend in a column direction. Alternatively, the main line VLm may extend in the column direction and the branch lines VLb may extend in the row direction, or the main line VLm and the branch lines VIb can alternatively be arranged in various other configurations. 
         [0036]    As shown in  FIG. 2 , a pixel PX, for example, a pixel PX connected to an i-th scan signal S i  and a j-th data line D j , includes an organic light emitting diode (OLED), a driving transistor M 1 , a storage capacitor C 1 , and a switching transistor M 2 . 
         [0037]    The switching transistor M 2  includes a control terminal connected to the scan signal line S 1 , an input terminal connected to the data line D j , and an output terminal connected to the driving transistor M 1 . The switching transistor M 2  transmits a data voltage applied to the data line D j  in response to a scan signal applied to the scan signal line S i . A data signal of the organic light emitting display device according to an exemplary embodiment of the present invention is a voltage signal having a level depending on a gray level of a corresponding pixel PX. However, the present invention is not limited thereto. 
         [0038]    The driving transistor M 1  includes a control terminal connected to the switching transistor M 2 , an input terminal connected to a corresponding branch line VLb of the driving voltage line VL, and an output terminal. The driving transistor M 1  receives a driving voltage VDD through the input terminal. The output terminal is connected to the OLED. The driving transistor M 1  provides an output current I OLED  having a magnitude depending on a voltage difference between the control terminal and the input terminal. 
         [0039]    The storage capacitor C 1  is connected between the control terminal and the input terminal of the driving transistor M 1 . The storage capacitor C 1  is charged with the data voltage and uniformly maintains a voltage difference corresponding to the data voltage. Therefore, a voltage difference between the control terminal and the input terminal of the driving transistor M 1  is uniformly maintained even after the switching transistor M 2  is turned off. 
         [0040]    The OLED includes an anode connected to the output terminal of the driving transistor M 1  and a cathode connected to a common voltage Vcom. The anode may be a pixel electrode (not shown) in a region partitioned by two adjacent scan lines and two adjacent data lines, and the cathode may be a part of a common electrode (not shown) on the front side of the display panel  100 . The OLED emits light with intensity depending on the output current I OLED  of the driving transistor M 1 . 
         [0041]    The OLED may emit light in one of three primary colors or light in one of the three primary colors and white. An example of the three primary colors includes red, green, and blue, and the three primary colors are spatially combined to obtain a desired color. Alternatively, OLEDs of all the pixels PX can emit white light, and some of the pixels PX can further include a color filter (not shown) that changes white light emitted from their OLEDs to light in one of the primary colors. 
         [0042]    The switching transistor M 2  and the driving transistor M 1  are p-channel field effect transistors (FETs) formed of polysilicon in one embodiment. In some embodiments, at least one of the switching transistor M 2  and the driving transistor M 1  may be an n-channel FET. Furthermore, the connecting configuration between the driving transistor M 1 , the switching transistor M 2 , the capacitor C 1 , and the OLED may be modified. 
         [0043]    Referring back to  FIG. 1 , the gray voltage generator  500  generates a plurality of reference gray voltages relating to luminance of the pixels PX. The number of reference gray voltages is smaller than the number of total gray levels. 
         [0044]    The scan driver  200  is connected to the scan signals S 1  through Sn of the display panel  100  and applies a scan signal of either a low voltage Von, which turns on the switching transistor M 1 , and a high voltage Voff, which turns off the switching transistor M 1 , to each of the scan signal lines S 1  through Sn. 
         [0045]    The data driver  300  is connected to the data lines D 1  through Dm, divides the reference gray voltages received from the gray voltage generator  500  to generate data voltages and applies the data voltages to the data lines D 1  through Dm. 
         [0046]    The voltage generator  600  is connected to the driving voltage line VL of the display panel  100 , generates the driving voltage VDD and applies the driving voltage VDD to the driving voltage line VL. Furthermore, the voltage generator  600  applies the common voltage Vcom to the display panel  100 . 
         [0047]    The signal controller  400  controls the scan driver  200 , the data driver  300 , and the gray voltage generator  500 . 
         [0048]    The driving devices  200 ,  300 ,  400 ,  500 , and  600  may be integrated into the display panel  100  together with the signal lines S 1  through Sn and D 1  through Dm and the transistors M 1  and M 2 . Alternatively, the driving devices  200 ,  300 ,  400 ,  500 , and  600  may be directly mounted on the display panel  100  in the form of at least one integrated circuit chip, mounted on a flexible printed circuit film (not shown) and bonded to the display panel  100  in the form of a tape carrier package (TCP), or mounted on an additional printed circuit board (not shown). Furthermore, the driving devices  200 ,  300 ,  400 ,  500 , and  600  may be integrated into a single chip and, in this case, at least one of the driving devices or at least one of the circuit elements constructing the driving devices may be located outside the single chip. 
         [0049]    The operation of the organic light emitting display device will now be explained in detail. 
         [0050]    When the display device is turned on, the display device is provided with power from an external power supply. When the display device is mounted in a mobile phone, the external power supply may be a battery of the mobile phone. That is, when the mobile phone is turned on, the power of the battery is applied to the display device. When the display device is applied to a monitor or a TV receiver, the display device provides power through a power line to the driving devices  200 ,  300 ,  400 ,  500 , and  600 . Here, the scan driver  200  and the data driver  300  that respectively apply scan signals and data signals to the display panel  100  generally receive a reset signal to initialize and begin operating after power is provided. The signal controller  400  applies the reset signal to the scan driver  200  and the data driver  300  when the display device is turned on. This process will be described later in more detail. 
         [0051]    The signal controller  400  receives input video signals R, G, and B and an input control signal for controlling display of the input video signal from an external graphics controller (not shown). The input video signals include luminance information of each pixel PX, the luminance having a gray level within a gray level range, for example, 1024=2 10 , 256=2 8 , or 64=2 6  gray levels. Examples of different input control signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock signal MCLK, and a data enable signal DE. 
         [0052]    The signal controller  400  appropriately processes the input video signals R, G, and B to generate an output video signal DAT on the basis of the input video signals R, G, and B and the input control signal, and to generate a scan control signal CONT 1  and a data control signal CONT 2 . The signal controller  400  sends the scan control signal CONT 1  to the gate driver  200  and transmits the data control signal CONT 2  and the output video signal DAT to the data driver  300 . Furthermore, the signal controller  400  initially transmits a reset signal RTS to the scan driver  200  and the data driver  300  and, when the reset signal is abnormal, restores the abnormal reset signal to a normal reset signal and then transmits the normal reset signal. 
         [0053]    The scan control signal CONT 1  includes a scan start signal STV that instructs scanning of the low voltage Von to be started and at least one clock signal that controls an output period of the low voltage Von. The scan control signal CONT 1  may further include an output enable signal OE for restricting the duration of a gate on voltage, that is, the low voltage Von. 
         [0054]    The data control signal CONT 2  includes a horizontal synchronization start signal STH that indicates the start of transmission of the output video signal DAT for pixels PX corresponding to a single row, a load signal LOAD that instructs analog data voltages to be applied to the data lines D 1  through Dm and a data clock signal HCLK. 
         [0055]    The gray voltage generator  500  generates a reference gray voltage and provides the reference gray voltage to the data driver  300 . 
         [0056]    The data driver  300  starts to operate according to the reset signal RTS, receives output video data DAT for pixels corresponding to a single row according to the data control signal CONT 2 , divides the reference gray voltage to generate analog data voltages corresponding to the output video data DAT, and then applies the analog data voltages to corresponding data lines D 1  through Dm. 
         [0057]    The scan driver  200  also begins operating according to the reset signal RTS and converts scan signals applied to the scan signal lines S 1  through Sn into the low voltage Von according to the scan control signal CONT 1 . Then, the switching transistors M 2  connected to a corresponding scan signal line of the scan signal lines S 1  through Sn are turned on, and data voltages applied to the data lines D 1  through Dm are provided to the control terminals of the driving transistors M 1  of the corresponding pixels PX. 
         [0058]    The data voltage applied to each driving transistor M 1  is charged in the storage capacitor C 1  and the charged voltage is maintained when the switching transistor M 2  is turned off. The driving transistor M 1  provided with the data voltage is turned on to output the output current I OLED  having a magnitude corresponding to the data voltage. The OLED emits light with intensity depending on the magnitude of the output current I OLED  of the driving transistor M 1 , and thus a corresponding pixel PX displays an image. 
         [0059]    After a lapse of one horizontal period (or “1H”) (one period of the horizontal synchronization signal Hsync and the data enable signal DE), the scan driver  200  and the data driver  300  repeat the aforementioned operation for pixels PX of the next row. In this manner, scan signals are applied to all the scan signal lines S 1  through Sn for a single frame to supply data voltages to all of the plurality of pixels PX. When one frame is finished, the next frame is started and the same operation is repeated. 
         [0060]    Restoration of a reset signal according to an exemplary embodiment of the present invention will now be described in detail with reference to  FIGS. 3 and 4 . 
         [0061]      FIG. 3  is a drawing illustrating waveforms of abnormal reset signals. 
         [0062]    When power is applied to the scan driver  200  and the data driver  300  at a time T 1 , a normal reset signal RTS has a waveform adjusted from a low level VL to a high level VH after the power is applied. Specifically, rising edge timing of the reset signal RTS is generated after the power is applied, and the scan driver  200  and the data driver  300  start to operate when they recognize the rising edge timing of the reset signal. However, reset signals RTS 1 , RTS 2 , and RTS 3  illustrated in  FIG. 3  do not have normal waveforms. 
         [0063]    The reset signal RTS 1  maintains a low level VL even after the time T 1  at which the power is applied. Then, the scan driver  200  and the data driver  300  may not be properly started. 
         [0064]    The reset signal RTS 2  continuously maintains a high level VH, and thus the scan driver  200  and the data driver  300  may not recognize a time at which the power is adjusted from the low level VL to the high level VH. In this case also, the scan driver  200  and the data driver  300  may not be properly started. 
         [0065]    A time at which the reset signal RTS 3  is adjusted from a low level VL to a high level VH corresponds to the time T 1 , and thus the scan driver  200  and the data driver  300  cannot recognize the time. 
         [0066]    The signal controller  400  detects a reset signal in synchronization with a time at which power is applied to the scan driver  200  and the data driver  300  for a period of time following application of power. The signal controller  400  determines whether the detected reset signal is normal. When a reset signal is abnormal, as illustrated in  FIG. 3 , the signal controller  400  restores the abnormal reset signal to a normal reset signal and transmits the restored normal reset signal to the scan driver  200  and the data driver  300 . 
         [0067]      FIG. 4  is a drawing illustrating reset signals restored from the reset signals RTS 1 , RTS 2 , and RTS  3  having abnormal waveforms illustrated in  FIG. 3 . 
         [0068]    When a reset signal RTS 1 ′ maintains the low level VL for a time TD 11  even after the time T 1 , the signal controller  400  increases the reset signal RTS 1 ′ to the high level VH and outputs the increased reset signal. 
         [0069]    The signal controller  400  detects a reset signal RTS 2 ′, which maintains the high level VH at the time T 1 , for a time TD 21  after the time T 1 . When the level of the reset signal RTS 2  is not varied for the time TD 21 , the signal controller  400  decreases the reset signal RTS 2  to the low level VL, and then increases the reset signal RTS 2  to the high level after a lapse of time TD 22 . Then, the reset signal RTS 2 ′ has a waveform adjusted from the low level VL to the high level VH after the time T 1 . The time TD 21  and the time TD 22  can be appropriately set such that a rising edge timing at which the reset signal RTS 2 ′ increases from the low level to the high level is generated. 
         [0070]    The signal controller  400  decreases a reset signal RTS 3 ′ to the low level after a lapse of time TD 31  when a time at which the reset signal RTS 3 ′ is adjusted from the low level to the high level corresponds to the time T 1  or earlier, and then increases the reset signal RTS 3 ′ after a predetermined lapse of time TD 32 . Then, the reset signal RTS 3 ′ has a waveform adjusted from the low level VL to the high level VH after the time T 1 . The time TD 31  and the time TD 32  can be appropriately set such that a rising edge timing at which the reset signal RTS 3 ′ increases from the low level to the high level is generated. 
         [0071]    As described above, the signal controller  400  restores a reset signal and transmits the restored reset signal to the scan driver and the data driver, and thus the scan driver and the data driver may be normally started after power is applied. 
         [0072]    While this invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but is instead intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.